Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 31
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 21
1 22:54:31.311493 lava-dispatcher, installed at version: 2023.05.1
2 22:54:31.311697 start: 0 validate
3 22:54:31.311824 Start time: 2023-06-05 22:54:31.311817+00:00 (UTC)
4 22:54:31.311950 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:54:31.312079 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 22:54:31.606151 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:54:31.606946 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:54:58.406492 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:54:58.407259 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:54:58.706106 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:54:58.706854 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 22:55:02.505562 validate duration: 31.19
14 22:55:02.505829 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:55:02.505929 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:55:02.506015 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:55:02.506156 Not decompressing ramdisk as can be used compressed.
18 22:55:02.506240 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230527.0/arm64/rootfs.cpio.gz
19 22:55:02.506306 saving as /var/lib/lava/dispatcher/tmp/10597637/tftp-deploy-_q_lfg_t/ramdisk/rootfs.cpio.gz
20 22:55:02.506366 total size: 43394293 (41MB)
21 22:55:02.803789 progress 0% (0MB)
22 22:55:02.814846 progress 5% (2MB)
23 22:55:02.825436 progress 10% (4MB)
24 22:55:02.835993 progress 15% (6MB)
25 22:55:02.846750 progress 20% (8MB)
26 22:55:02.857478 progress 25% (10MB)
27 22:55:02.868269 progress 30% (12MB)
28 22:55:02.879198 progress 35% (14MB)
29 22:55:02.890033 progress 40% (16MB)
30 22:55:02.900783 progress 45% (18MB)
31 22:55:02.911641 progress 50% (20MB)
32 22:55:02.922506 progress 55% (22MB)
33 22:55:02.933317 progress 60% (24MB)
34 22:55:02.944224 progress 65% (26MB)
35 22:55:02.955112 progress 70% (29MB)
36 22:55:02.965885 progress 75% (31MB)
37 22:55:02.976616 progress 80% (33MB)
38 22:55:02.987448 progress 85% (35MB)
39 22:55:02.998099 progress 90% (37MB)
40 22:55:03.008783 progress 95% (39MB)
41 22:55:03.019282 progress 100% (41MB)
42 22:55:03.019443 41MB downloaded in 0.51s (80.66MB/s)
43 22:55:03.019599 end: 1.1.1 http-download (duration 00:00:01) [common]
45 22:55:03.019861 end: 1.1 download-retry (duration 00:00:01) [common]
46 22:55:03.019949 start: 1.2 download-retry (timeout 00:09:59) [common]
47 22:55:03.020035 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 22:55:03.020181 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 22:55:03.020254 saving as /var/lib/lava/dispatcher/tmp/10597637/tftp-deploy-_q_lfg_t/kernel/Image
50 22:55:03.020317 total size: 45746688 (43MB)
51 22:55:03.020377 No compression specified
52 22:55:03.021493 progress 0% (0MB)
53 22:55:03.032730 progress 5% (2MB)
54 22:55:03.044120 progress 10% (4MB)
55 22:55:03.055556 progress 15% (6MB)
56 22:55:03.067071 progress 20% (8MB)
57 22:55:03.078550 progress 25% (10MB)
58 22:55:03.089964 progress 30% (13MB)
59 22:55:03.101353 progress 35% (15MB)
60 22:55:03.112747 progress 40% (17MB)
61 22:55:03.124180 progress 45% (19MB)
62 22:55:03.135683 progress 50% (21MB)
63 22:55:03.147090 progress 55% (24MB)
64 22:55:03.158703 progress 60% (26MB)
65 22:55:03.170160 progress 65% (28MB)
66 22:55:03.181494 progress 70% (30MB)
67 22:55:03.192842 progress 75% (32MB)
68 22:55:03.204036 progress 80% (34MB)
69 22:55:03.215333 progress 85% (37MB)
70 22:55:03.226625 progress 90% (39MB)
71 22:55:03.238026 progress 95% (41MB)
72 22:55:03.249306 progress 100% (43MB)
73 22:55:03.249436 43MB downloaded in 0.23s (190.42MB/s)
74 22:55:03.249585 end: 1.2.1 http-download (duration 00:00:00) [common]
76 22:55:03.249811 end: 1.2 download-retry (duration 00:00:00) [common]
77 22:55:03.249899 start: 1.3 download-retry (timeout 00:09:59) [common]
78 22:55:03.249990 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 22:55:03.250144 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 22:55:03.250216 saving as /var/lib/lava/dispatcher/tmp/10597637/tftp-deploy-_q_lfg_t/dtb/mt8192-asurada-spherion-r0.dtb
81 22:55:03.250278 total size: 46924 (0MB)
82 22:55:03.250337 No compression specified
83 22:55:03.251456 progress 69% (0MB)
84 22:55:03.251728 progress 100% (0MB)
85 22:55:03.251881 0MB downloaded in 0.00s (27.95MB/s)
86 22:55:03.252001 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:55:03.252221 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:55:03.252307 start: 1.4 download-retry (timeout 00:09:59) [common]
90 22:55:03.252390 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 22:55:03.252511 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 22:55:03.252597 saving as /var/lib/lava/dispatcher/tmp/10597637/tftp-deploy-_q_lfg_t/modules/modules.tar
93 22:55:03.252659 total size: 8552396 (8MB)
94 22:55:03.252719 Using unxz to decompress xz
95 22:55:03.256008 progress 0% (0MB)
96 22:55:03.276502 progress 5% (0MB)
97 22:55:03.299765 progress 10% (0MB)
98 22:55:03.330994 progress 15% (1MB)
99 22:55:03.357980 progress 20% (1MB)
100 22:55:03.383682 progress 25% (2MB)
101 22:55:03.409260 progress 30% (2MB)
102 22:55:03.435509 progress 35% (2MB)
103 22:55:03.460060 progress 40% (3MB)
104 22:55:03.485472 progress 45% (3MB)
105 22:55:03.509916 progress 50% (4MB)
106 22:55:03.533875 progress 55% (4MB)
107 22:55:03.557352 progress 60% (4MB)
108 22:55:03.581372 progress 65% (5MB)
109 22:55:03.605805 progress 70% (5MB)
110 22:55:03.629556 progress 75% (6MB)
111 22:55:03.655455 progress 80% (6MB)
112 22:55:03.680239 progress 85% (6MB)
113 22:55:03.704353 progress 90% (7MB)
114 22:55:03.727204 progress 95% (7MB)
115 22:55:03.751493 progress 100% (8MB)
116 22:55:03.758021 8MB downloaded in 0.51s (16.14MB/s)
117 22:55:03.758310 end: 1.4.1 http-download (duration 00:00:01) [common]
119 22:55:03.758568 end: 1.4 download-retry (duration 00:00:01) [common]
120 22:55:03.758661 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 22:55:03.758761 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 22:55:03.758848 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:55:03.758952 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 22:55:03.759185 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10597637/lava-overlay-vf0l_3lr
125 22:55:03.759330 makedir: /var/lib/lava/dispatcher/tmp/10597637/lava-overlay-vf0l_3lr/lava-10597637/bin
126 22:55:03.759442 makedir: /var/lib/lava/dispatcher/tmp/10597637/lava-overlay-vf0l_3lr/lava-10597637/tests
127 22:55:03.759547 makedir: /var/lib/lava/dispatcher/tmp/10597637/lava-overlay-vf0l_3lr/lava-10597637/results
128 22:55:03.759665 Creating /var/lib/lava/dispatcher/tmp/10597637/lava-overlay-vf0l_3lr/lava-10597637/bin/lava-add-keys
129 22:55:03.759812 Creating /var/lib/lava/dispatcher/tmp/10597637/lava-overlay-vf0l_3lr/lava-10597637/bin/lava-add-sources
130 22:55:03.759992 Creating /var/lib/lava/dispatcher/tmp/10597637/lava-overlay-vf0l_3lr/lava-10597637/bin/lava-background-process-start
131 22:55:03.760125 Creating /var/lib/lava/dispatcher/tmp/10597637/lava-overlay-vf0l_3lr/lava-10597637/bin/lava-background-process-stop
132 22:55:03.760249 Creating /var/lib/lava/dispatcher/tmp/10597637/lava-overlay-vf0l_3lr/lava-10597637/bin/lava-common-functions
133 22:55:03.760372 Creating /var/lib/lava/dispatcher/tmp/10597637/lava-overlay-vf0l_3lr/lava-10597637/bin/lava-echo-ipv4
134 22:55:03.760496 Creating /var/lib/lava/dispatcher/tmp/10597637/lava-overlay-vf0l_3lr/lava-10597637/bin/lava-install-packages
135 22:55:03.760620 Creating /var/lib/lava/dispatcher/tmp/10597637/lava-overlay-vf0l_3lr/lava-10597637/bin/lava-installed-packages
136 22:55:03.760743 Creating /var/lib/lava/dispatcher/tmp/10597637/lava-overlay-vf0l_3lr/lava-10597637/bin/lava-os-build
137 22:55:03.760920 Creating /var/lib/lava/dispatcher/tmp/10597637/lava-overlay-vf0l_3lr/lava-10597637/bin/lava-probe-channel
138 22:55:03.761042 Creating /var/lib/lava/dispatcher/tmp/10597637/lava-overlay-vf0l_3lr/lava-10597637/bin/lava-probe-ip
139 22:55:03.761163 Creating /var/lib/lava/dispatcher/tmp/10597637/lava-overlay-vf0l_3lr/lava-10597637/bin/lava-target-ip
140 22:55:03.761284 Creating /var/lib/lava/dispatcher/tmp/10597637/lava-overlay-vf0l_3lr/lava-10597637/bin/lava-target-mac
141 22:55:03.761404 Creating /var/lib/lava/dispatcher/tmp/10597637/lava-overlay-vf0l_3lr/lava-10597637/bin/lava-target-storage
142 22:55:03.761530 Creating /var/lib/lava/dispatcher/tmp/10597637/lava-overlay-vf0l_3lr/lava-10597637/bin/lava-test-case
143 22:55:03.761650 Creating /var/lib/lava/dispatcher/tmp/10597637/lava-overlay-vf0l_3lr/lava-10597637/bin/lava-test-event
144 22:55:03.761769 Creating /var/lib/lava/dispatcher/tmp/10597637/lava-overlay-vf0l_3lr/lava-10597637/bin/lava-test-feedback
145 22:55:03.761943 Creating /var/lib/lava/dispatcher/tmp/10597637/lava-overlay-vf0l_3lr/lava-10597637/bin/lava-test-raise
146 22:55:03.762119 Creating /var/lib/lava/dispatcher/tmp/10597637/lava-overlay-vf0l_3lr/lava-10597637/bin/lava-test-reference
147 22:55:03.762248 Creating /var/lib/lava/dispatcher/tmp/10597637/lava-overlay-vf0l_3lr/lava-10597637/bin/lava-test-runner
148 22:55:03.762372 Creating /var/lib/lava/dispatcher/tmp/10597637/lava-overlay-vf0l_3lr/lava-10597637/bin/lava-test-set
149 22:55:03.762496 Creating /var/lib/lava/dispatcher/tmp/10597637/lava-overlay-vf0l_3lr/lava-10597637/bin/lava-test-shell
150 22:55:03.762624 Updating /var/lib/lava/dispatcher/tmp/10597637/lava-overlay-vf0l_3lr/lava-10597637/bin/lava-install-packages (oe)
151 22:55:03.762776 Updating /var/lib/lava/dispatcher/tmp/10597637/lava-overlay-vf0l_3lr/lava-10597637/bin/lava-installed-packages (oe)
152 22:55:03.762969 Creating /var/lib/lava/dispatcher/tmp/10597637/lava-overlay-vf0l_3lr/lava-10597637/environment
153 22:55:03.763097 LAVA metadata
154 22:55:03.763174 - LAVA_JOB_ID=10597637
155 22:55:03.763241 - LAVA_DISPATCHER_IP=192.168.201.1
156 22:55:03.763351 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 22:55:03.763421 skipped lava-vland-overlay
158 22:55:03.763497 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 22:55:03.763579 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 22:55:03.763644 skipped lava-multinode-overlay
161 22:55:03.763719 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 22:55:03.763805 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 22:55:03.763888 Loading test definitions
164 22:55:03.763977 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 22:55:03.764055 Using /lava-10597637 at stage 0
166 22:55:03.764379 uuid=10597637_1.5.2.3.1 testdef=None
167 22:55:03.764469 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 22:55:03.764556 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 22:55:03.765121 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 22:55:03.765343 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 22:55:03.765959 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 22:55:03.766194 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 22:55:03.766786 runner path: /var/lib/lava/dispatcher/tmp/10597637/lava-overlay-vf0l_3lr/lava-10597637/0/tests/0_igt-gpu-panfrost test_uuid 10597637_1.5.2.3.1
176 22:55:03.766962 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 22:55:03.767168 Creating lava-test-runner.conf files
179 22:55:03.767232 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10597637/lava-overlay-vf0l_3lr/lava-10597637/0 for stage 0
180 22:55:03.767321 - 0_igt-gpu-panfrost
181 22:55:03.767421 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 22:55:03.767508 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 22:55:03.774105 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 22:55:03.774220 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 22:55:03.774310 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 22:55:03.774398 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 22:55:03.774487 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 22:55:05.072551 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 22:55:05.072955 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 22:55:05.073075 extracting modules file /var/lib/lava/dispatcher/tmp/10597637/tftp-deploy-_q_lfg_t/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597637/extract-overlay-ramdisk-pcbbdk9a/ramdisk
191 22:55:05.285577 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 22:55:05.285780 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 22:55:05.285910 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597637/compress-overlay-_wcxsvwz/overlay-1.5.2.4.tar.gz to ramdisk
194 22:55:05.286009 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597637/compress-overlay-_wcxsvwz/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10597637/extract-overlay-ramdisk-pcbbdk9a/ramdisk
195 22:55:05.292832 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 22:55:05.292948 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 22:55:05.293042 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 22:55:05.293132 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 22:55:05.293218 Building ramdisk /var/lib/lava/dispatcher/tmp/10597637/extract-overlay-ramdisk-pcbbdk9a/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10597637/extract-overlay-ramdisk-pcbbdk9a/ramdisk
200 22:55:06.205603 >> 369045 blocks
201 22:55:12.033534 rename /var/lib/lava/dispatcher/tmp/10597637/extract-overlay-ramdisk-pcbbdk9a/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10597637/tftp-deploy-_q_lfg_t/ramdisk/ramdisk.cpio.gz
202 22:55:12.033966 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 22:55:12.034093 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 22:55:12.034198 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 22:55:12.034308 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10597637/tftp-deploy-_q_lfg_t/kernel/Image'
206 22:55:23.523326 Returned 0 in 11 seconds
207 22:55:23.623933 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10597637/tftp-deploy-_q_lfg_t/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10597637/tftp-deploy-_q_lfg_t/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10597637/tftp-deploy-_q_lfg_t/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10597637/tftp-deploy-_q_lfg_t/kernel/image.itb
208 22:55:24.334030 output: FIT description: Kernel Image image with one or more FDT blobs
209 22:55:24.334388 output: Created: Mon Jun 5 23:55:24 2023
210 22:55:24.334475 output: Image 0 (kernel-1)
211 22:55:24.334544 output: Description:
212 22:55:24.334606 output: Created: Mon Jun 5 23:55:24 2023
213 22:55:24.334678 output: Type: Kernel Image
214 22:55:24.334740 output: Compression: lzma compressed
215 22:55:24.334801 output: Data Size: 10085945 Bytes = 9849.56 KiB = 9.62 MiB
216 22:55:24.334876 output: Architecture: AArch64
217 22:55:24.334936 output: OS: Linux
218 22:55:24.335001 output: Load Address: 0x00000000
219 22:55:24.335062 output: Entry Point: 0x00000000
220 22:55:24.335119 output: Hash algo: crc32
221 22:55:24.335172 output: Hash value: b2943ff2
222 22:55:24.335237 output: Image 1 (fdt-1)
223 22:55:24.335291 output: Description: mt8192-asurada-spherion-r0
224 22:55:24.335344 output: Created: Mon Jun 5 23:55:24 2023
225 22:55:24.335397 output: Type: Flat Device Tree
226 22:55:24.335460 output: Compression: uncompressed
227 22:55:24.335514 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 22:55:24.335568 output: Architecture: AArch64
229 22:55:24.335626 output: Hash algo: crc32
230 22:55:24.335679 output: Hash value: 1df858fa
231 22:55:24.335732 output: Image 2 (ramdisk-1)
232 22:55:24.335785 output: Description: unavailable
233 22:55:24.335845 output: Created: Mon Jun 5 23:55:24 2023
234 22:55:24.335898 output: Type: RAMDisk Image
235 22:55:24.335951 output: Compression: Unknown Compression
236 22:55:24.336009 output: Data Size: 56395176 Bytes = 55073.41 KiB = 53.78 MiB
237 22:55:24.336064 output: Architecture: AArch64
238 22:55:24.336117 output: OS: Linux
239 22:55:24.336169 output: Load Address: unavailable
240 22:55:24.336229 output: Entry Point: unavailable
241 22:55:24.336282 output: Hash algo: crc32
242 22:55:24.336334 output: Hash value: e9293060
243 22:55:24.336392 output: Default Configuration: 'conf-1'
244 22:55:24.336446 output: Configuration 0 (conf-1)
245 22:55:24.336498 output: Description: mt8192-asurada-spherion-r0
246 22:55:24.336550 output: Kernel: kernel-1
247 22:55:24.336614 output: Init Ramdisk: ramdisk-1
248 22:55:24.336667 output: FDT: fdt-1
249 22:55:24.336719 output: Loadables: kernel-1
250 22:55:24.336821 output:
251 22:55:24.337020 end: 1.5.8.1 prepare-fit (duration 00:00:12) [common]
252 22:55:24.337124 end: 1.5.8 prepare-kernel (duration 00:00:12) [common]
253 22:55:24.337236 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 22:55:24.337331 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 22:55:24.337416 No LXC device requested
256 22:55:24.337497 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 22:55:24.337598 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 22:55:24.337681 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 22:55:24.337764 Checking files for TFTP limit of 4294967296 bytes.
260 22:55:24.338279 end: 1 tftp-deploy (duration 00:00:22) [common]
261 22:55:24.338393 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 22:55:24.338485 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 22:55:24.338620 substitutions:
264 22:55:24.338690 - {DTB}: 10597637/tftp-deploy-_q_lfg_t/dtb/mt8192-asurada-spherion-r0.dtb
265 22:55:24.338762 - {INITRD}: 10597637/tftp-deploy-_q_lfg_t/ramdisk/ramdisk.cpio.gz
266 22:55:24.338824 - {KERNEL}: 10597637/tftp-deploy-_q_lfg_t/kernel/Image
267 22:55:24.338883 - {LAVA_MAC}: None
268 22:55:24.338947 - {PRESEED_CONFIG}: None
269 22:55:24.339005 - {PRESEED_LOCAL}: None
270 22:55:24.339059 - {RAMDISK}: 10597637/tftp-deploy-_q_lfg_t/ramdisk/ramdisk.cpio.gz
271 22:55:24.339114 - {ROOT_PART}: None
272 22:55:24.339176 - {ROOT}: None
273 22:55:24.339230 - {SERVER_IP}: 192.168.201.1
274 22:55:24.339283 - {TEE}: None
275 22:55:24.339344 Parsed boot commands:
276 22:55:24.339399 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 22:55:24.339572 Parsed boot commands: tftpboot 192.168.201.1 10597637/tftp-deploy-_q_lfg_t/kernel/image.itb 10597637/tftp-deploy-_q_lfg_t/kernel/cmdline
278 22:55:24.339661 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 22:55:24.339754 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 22:55:24.339848 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 22:55:24.339941 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 22:55:24.340014 Not connected, no need to disconnect.
283 22:55:24.340094 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 22:55:24.340174 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 22:55:24.340242 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-1'
286 22:55:24.343420 Setting prompt string to ['lava-test: # ']
287 22:55:24.343750 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 22:55:24.343860 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 22:55:24.343957 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 22:55:24.344053 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 22:55:24.344247 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
292 22:55:29.474990 >> Command sent successfully.
293 22:55:29.477575 Returned 0 in 5 seconds
294 22:55:29.577973 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 22:55:29.578548 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 22:55:29.578651 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 22:55:29.578742 Setting prompt string to 'Starting depthcharge on Spherion...'
299 22:55:29.578811 Changing prompt to 'Starting depthcharge on Spherion...'
300 22:55:29.578880 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 22:55:29.579144 [Enter `^Ec?' for help]
302 22:55:29.751892
303 22:55:29.752059
304 22:55:29.752135 F0: 102B 0000
305 22:55:29.752198
306 22:55:29.752258 F3: 1001 0000 [0200]
307 22:55:29.754525
308 22:55:29.754611 F3: 1001 0000
309 22:55:29.754678
310 22:55:29.754740 F7: 102D 0000
311 22:55:29.754800
312 22:55:29.758142 F1: 0000 0000
313 22:55:29.758228
314 22:55:29.758294 V0: 0000 0000 [0001]
315 22:55:29.758356
316 22:55:29.761290 00: 0007 8000
317 22:55:29.761376
318 22:55:29.761443 01: 0000 0000
319 22:55:29.761506
320 22:55:29.764576 BP: 0C00 0209 [0000]
321 22:55:29.764659
322 22:55:29.764726 G0: 1182 0000
323 22:55:29.764812
324 22:55:29.768433 EC: 0000 0021 [4000]
325 22:55:29.768520
326 22:55:29.768587 S7: 0000 0000 [0000]
327 22:55:29.768649
328 22:55:29.772175 CC: 0000 0000 [0001]
329 22:55:29.772262
330 22:55:29.772328 T0: 0000 0040 [010F]
331 22:55:29.772390
332 22:55:29.772448 Jump to BL
333 22:55:29.772504
334 22:55:29.798487
335 22:55:29.798632
336 22:55:29.798703
337 22:55:29.806058 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 22:55:29.809388 ARM64: Exception handlers installed.
339 22:55:29.813131 ARM64: Testing exception
340 22:55:29.816549 ARM64: Done test exception
341 22:55:29.823171 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 22:55:29.833093 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 22:55:29.839672 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 22:55:29.849562 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 22:55:29.856061 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 22:55:29.866264 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 22:55:29.876828 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 22:55:29.883215 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 22:55:29.901185 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 22:55:29.904619 WDT: Last reset was cold boot
351 22:55:29.908368 SPI1(PAD0) initialized at 2873684 Hz
352 22:55:29.911349 SPI5(PAD0) initialized at 992727 Hz
353 22:55:29.914930 VBOOT: Loading verstage.
354 22:55:29.921638 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 22:55:29.924773 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 22:55:29.927816 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 22:55:29.931216 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 22:55:29.938916 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 22:55:29.945269 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 22:55:29.956169 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 22:55:29.956272
362 22:55:29.956340
363 22:55:29.966428 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 22:55:29.969765 ARM64: Exception handlers installed.
365 22:55:29.973041 ARM64: Testing exception
366 22:55:29.973129 ARM64: Done test exception
367 22:55:29.979478 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 22:55:29.984151 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 22:55:29.997180 Probing TPM: . done!
370 22:55:29.997327 TPM ready after 0 ms
371 22:55:30.003901 Connected to device vid:did:rid of 1ae0:0028:00
372 22:55:30.011553 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 22:55:30.014907 Initialized TPM device CR50 revision 0
374 22:55:30.079976 tlcl_send_startup: Startup return code is 0
375 22:55:30.080132 TPM: setup succeeded
376 22:55:30.091700 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 22:55:30.100291 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 22:55:30.107304 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 22:55:30.119887 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 22:55:30.123450 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 22:55:30.131805 in-header: 03 07 00 00 08 00 00 00
382 22:55:30.135131 in-data: aa e4 47 04 13 02 00 00
383 22:55:30.139429 Chrome EC: UHEPI supported
384 22:55:30.145908 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 22:55:30.149625 in-header: 03 ad 00 00 08 00 00 00
386 22:55:30.153226 in-data: 00 20 20 08 00 00 00 00
387 22:55:30.153322 Phase 1
388 22:55:30.156898 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 22:55:30.164227 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 22:55:30.167743 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 22:55:30.171869 Recovery requested (1009000e)
392 22:55:30.181948 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 22:55:30.187894 tlcl_extend: response is 0
394 22:55:30.197695 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 22:55:30.203945 tlcl_extend: response is 0
396 22:55:30.210284 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 22:55:30.231605 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 22:55:30.238125 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 22:55:30.238252
400 22:55:30.238323
401 22:55:30.248204 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 22:55:30.251539 ARM64: Exception handlers installed.
403 22:55:30.254785 ARM64: Testing exception
404 22:55:30.254897 ARM64: Done test exception
405 22:55:30.276577 pmic_efuse_setting: Set efuses in 11 msecs
406 22:55:30.280036 pmwrap_interface_init: Select PMIF_VLD_RDY
407 22:55:30.287211 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 22:55:30.290999 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 22:55:30.293928 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 22:55:30.300424 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 22:55:30.303693 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 22:55:30.311018 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 22:55:30.314713 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 22:55:30.318670 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 22:55:30.325590 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 22:55:30.329622 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 22:55:30.333582 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 22:55:30.336206 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 22:55:30.343468 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 22:55:30.349557 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 22:55:30.353055 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 22:55:30.360527 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 22:55:30.367756 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 22:55:30.371213 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 22:55:30.378229 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 22:55:30.381980 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 22:55:30.389054 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 22:55:30.392811 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 22:55:30.399752 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 22:55:30.405596 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 22:55:30.409176 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 22:55:30.415783 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 22:55:30.422099 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 22:55:30.425642 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 22:55:30.429222 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 22:55:30.435396 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 22:55:30.438575 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 22:55:30.445355 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 22:55:30.448741 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 22:55:30.455655 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 22:55:30.458781 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 22:55:30.465261 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 22:55:30.471682 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 22:55:30.475160 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 22:55:30.478668 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 22:55:30.485681 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 22:55:30.489548 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 22:55:30.493044 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 22:55:30.496368 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 22:55:30.503076 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 22:55:30.506659 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 22:55:30.509818 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 22:55:30.513429 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 22:55:30.521139 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 22:55:30.524376 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 22:55:30.528155 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 22:55:30.532001 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 22:55:30.539757 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 22:55:30.546876 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 22:55:30.554483 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 22:55:30.560700 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 22:55:30.568194 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 22:55:30.574932 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 22:55:30.577928 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 22:55:30.581527 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 22:55:30.588808 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x7
467 22:55:30.595938 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 22:55:30.598997 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 22:55:30.602402 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 22:55:30.613857 [RTC]rtc_get_frequency_meter,154: input=15, output=772
471 22:55:30.623062 [RTC]rtc_get_frequency_meter,154: input=23, output=956
472 22:55:30.633379 [RTC]rtc_get_frequency_meter,154: input=19, output=866
473 22:55:30.641861 [RTC]rtc_get_frequency_meter,154: input=17, output=818
474 22:55:30.651908 [RTC]rtc_get_frequency_meter,154: input=16, output=795
475 22:55:30.655416 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
476 22:55:30.659587 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
477 22:55:30.665555 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
478 22:55:30.668926 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
479 22:55:30.671950 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
480 22:55:30.675326 ADC[4]: Raw value=903245 ID=7
481 22:55:30.678994 ADC[3]: Raw value=213179 ID=1
482 22:55:30.679090 RAM Code: 0x71
483 22:55:30.685400 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
484 22:55:30.688671 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
485 22:55:30.698595 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
486 22:55:30.705533 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
487 22:55:30.708648 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
488 22:55:30.711999 in-header: 03 07 00 00 08 00 00 00
489 22:55:30.715677 in-data: aa e4 47 04 13 02 00 00
490 22:55:30.718693 Chrome EC: UHEPI supported
491 22:55:30.725015 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
492 22:55:30.728760 in-header: 03 ed 00 00 08 00 00 00
493 22:55:30.731905 in-data: 80 20 60 08 00 00 00 00
494 22:55:30.735044 MRC: failed to locate region type 0.
495 22:55:30.738939 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
496 22:55:30.741890 DRAM-K: Running full calibration
497 22:55:30.748514 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
498 22:55:30.751873 header.status = 0x0
499 22:55:30.755409 header.version = 0x6 (expected: 0x6)
500 22:55:30.758526 header.size = 0xd00 (expected: 0xd00)
501 22:55:30.758619 header.flags = 0x0
502 22:55:30.764924 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
503 22:55:30.783507 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
504 22:55:30.790111 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
505 22:55:30.794069 dram_init: ddr_geometry: 2
506 22:55:30.797103 [EMI] MDL number = 2
507 22:55:30.797200 [EMI] Get MDL freq = 0
508 22:55:30.800278 dram_init: ddr_type: 0
509 22:55:30.800364 is_discrete_lpddr4: 1
510 22:55:30.803724 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
511 22:55:30.803812
512 22:55:30.803879
513 22:55:30.806846 [Bian_co] ETT version 0.0.0.1
514 22:55:30.813539 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
515 22:55:30.813652
516 22:55:30.816907 dramc_set_vcore_voltage set vcore to 650000
517 22:55:30.820212 Read voltage for 800, 4
518 22:55:30.820303 Vio18 = 0
519 22:55:30.820393 Vcore = 650000
520 22:55:30.823897 Vdram = 0
521 22:55:30.823988 Vddq = 0
522 22:55:30.824056 Vmddr = 0
523 22:55:30.826532 dram_init: config_dvfs: 1
524 22:55:30.830076 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
525 22:55:30.837070 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
526 22:55:30.840369 [SwImpedanceCal] DRVP=9, DRVN=15, ODTN=9
527 22:55:30.843555 freq_region=0, Reg: DRVP=9, DRVN=15, ODTN=9
528 22:55:30.846669 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
529 22:55:30.850368 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
530 22:55:30.853199 MEM_TYPE=3, freq_sel=18
531 22:55:30.856821 sv_algorithm_assistance_LP4_1600
532 22:55:30.860025 ============ PULL DRAM RESETB DOWN ============
533 22:55:30.866812 ========== PULL DRAM RESETB DOWN end =========
534 22:55:30.870195 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
535 22:55:30.873661 ===================================
536 22:55:30.876513 LPDDR4 DRAM CONFIGURATION
537 22:55:30.880136 ===================================
538 22:55:30.880228 EX_ROW_EN[0] = 0x0
539 22:55:30.882957 EX_ROW_EN[1] = 0x0
540 22:55:30.883043 LP4Y_EN = 0x0
541 22:55:30.886534 WORK_FSP = 0x0
542 22:55:30.886622 WL = 0x2
543 22:55:30.889857 RL = 0x2
544 22:55:30.889943 BL = 0x2
545 22:55:30.893410 RPST = 0x0
546 22:55:30.893499 RD_PRE = 0x0
547 22:55:30.896340 WR_PRE = 0x1
548 22:55:30.896425 WR_PST = 0x0
549 22:55:30.899763 DBI_WR = 0x0
550 22:55:30.899851 DBI_RD = 0x0
551 22:55:30.903051 OTF = 0x1
552 22:55:30.906490 ===================================
553 22:55:30.909695 ===================================
554 22:55:30.909811 ANA top config
555 22:55:30.913076 ===================================
556 22:55:30.916594 DLL_ASYNC_EN = 0
557 22:55:30.919832 ALL_SLAVE_EN = 1
558 22:55:30.923176 NEW_RANK_MODE = 1
559 22:55:30.923272 DLL_IDLE_MODE = 1
560 22:55:30.926873 LP45_APHY_COMB_EN = 1
561 22:55:30.929616 TX_ODT_DIS = 1
562 22:55:30.932903 NEW_8X_MODE = 1
563 22:55:30.936399 ===================================
564 22:55:30.939763 ===================================
565 22:55:30.943114 data_rate = 1600
566 22:55:30.943214 CKR = 1
567 22:55:30.946936 DQ_P2S_RATIO = 8
568 22:55:30.950379 ===================================
569 22:55:30.954033 CA_P2S_RATIO = 8
570 22:55:30.958124 DQ_CA_OPEN = 0
571 22:55:30.958243 DQ_SEMI_OPEN = 0
572 22:55:30.961150 CA_SEMI_OPEN = 0
573 22:55:30.965156 CA_FULL_RATE = 0
574 22:55:30.968495 DQ_CKDIV4_EN = 1
575 22:55:30.968593 CA_CKDIV4_EN = 1
576 22:55:30.972118 CA_PREDIV_EN = 0
577 22:55:30.975780 PH8_DLY = 0
578 22:55:30.979535 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
579 22:55:30.979632 DQ_AAMCK_DIV = 4
580 22:55:30.983062 CA_AAMCK_DIV = 4
581 22:55:30.987143 CA_ADMCK_DIV = 4
582 22:55:30.991296 DQ_TRACK_CA_EN = 0
583 22:55:30.994082 CA_PICK = 800
584 22:55:30.994175 CA_MCKIO = 800
585 22:55:30.997700 MCKIO_SEMI = 0
586 22:55:31.000956 PLL_FREQ = 3068
587 22:55:31.004431 DQ_UI_PI_RATIO = 32
588 22:55:31.008419 CA_UI_PI_RATIO = 0
589 22:55:31.008519 ===================================
590 22:55:31.011967 ===================================
591 22:55:31.015538 memory_type:LPDDR4
592 22:55:31.019252 GP_NUM : 10
593 22:55:31.019351 SRAM_EN : 1
594 22:55:31.022969 MD32_EN : 0
595 22:55:31.026465 ===================================
596 22:55:31.026556 [ANA_INIT] >>>>>>>>>>>>>>
597 22:55:31.030309 <<<<<< [CONFIGURE PHASE]: ANA_TX
598 22:55:31.034416 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
599 22:55:31.037431 ===================================
600 22:55:31.041516 data_rate = 1600,PCW = 0X7600
601 22:55:31.041616 ===================================
602 22:55:31.045116 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
603 22:55:31.052743 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
604 22:55:31.056721 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
605 22:55:31.063707 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
606 22:55:31.067580 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
607 22:55:31.067692 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
608 22:55:31.070957 [ANA_INIT] flow start
609 22:55:31.074747 [ANA_INIT] PLL >>>>>>>>
610 22:55:31.074847 [ANA_INIT] PLL <<<<<<<<
611 22:55:31.078761 [ANA_INIT] MIDPI >>>>>>>>
612 22:55:31.082364 [ANA_INIT] MIDPI <<<<<<<<
613 22:55:31.082465 [ANA_INIT] DLL >>>>>>>>
614 22:55:31.086374 [ANA_INIT] flow end
615 22:55:31.089677 ============ LP4 DIFF to SE enter ============
616 22:55:31.092683 ============ LP4 DIFF to SE exit ============
617 22:55:31.096517 [ANA_INIT] <<<<<<<<<<<<<
618 22:55:31.100015 [Flow] Enable top DCM control >>>>>
619 22:55:31.100115 [Flow] Enable top DCM control <<<<<
620 22:55:31.103839 Enable DLL master slave shuffle
621 22:55:31.111604 ==============================================================
622 22:55:31.111732 Gating Mode config
623 22:55:31.118871 ==============================================================
624 22:55:31.118997 Config description:
625 22:55:31.129858 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
626 22:55:31.137471 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
627 22:55:31.141052 SELPH_MODE 0: By rank 1: By Phase
628 22:55:31.144793 ==============================================================
629 22:55:31.148217 GAT_TRACK_EN = 1
630 22:55:31.152507 RX_GATING_MODE = 2
631 22:55:31.156128 RX_GATING_TRACK_MODE = 2
632 22:55:31.160036 SELPH_MODE = 1
633 22:55:31.160141 PICG_EARLY_EN = 1
634 22:55:31.163845 VALID_LAT_VALUE = 1
635 22:55:31.170901 ==============================================================
636 22:55:31.174645 Enter into Gating configuration >>>>
637 22:55:31.177961 Exit from Gating configuration <<<<
638 22:55:31.178062 Enter into DVFS_PRE_config >>>>>
639 22:55:31.189766 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
640 22:55:31.192926 Exit from DVFS_PRE_config <<<<<
641 22:55:31.196734 Enter into PICG configuration >>>>
642 22:55:31.200583 Exit from PICG configuration <<<<
643 22:55:31.203903 [RX_INPUT] configuration >>>>>
644 22:55:31.204001 [RX_INPUT] configuration <<<<<
645 22:55:31.211655 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
646 22:55:31.215366 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
647 22:55:31.222864 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
648 22:55:31.230065 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
649 22:55:31.233859 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
650 22:55:31.241370 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
651 22:55:31.244981 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
652 22:55:31.248870 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
653 22:55:31.252681 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
654 22:55:31.256331 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
655 22:55:31.260009 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
656 22:55:31.263894 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
657 22:55:31.267568 ===================================
658 22:55:31.271448 LPDDR4 DRAM CONFIGURATION
659 22:55:31.275084 ===================================
660 22:55:31.275184 EX_ROW_EN[0] = 0x0
661 22:55:31.278955 EX_ROW_EN[1] = 0x0
662 22:55:31.279049 LP4Y_EN = 0x0
663 22:55:31.282438 WORK_FSP = 0x0
664 22:55:31.282531 WL = 0x2
665 22:55:31.286189 RL = 0x2
666 22:55:31.286300 BL = 0x2
667 22:55:31.289717 RPST = 0x0
668 22:55:31.289808 RD_PRE = 0x0
669 22:55:31.293015 WR_PRE = 0x1
670 22:55:31.293104 WR_PST = 0x0
671 22:55:31.296483 DBI_WR = 0x0
672 22:55:31.296572 DBI_RD = 0x0
673 22:55:31.299593 OTF = 0x1
674 22:55:31.303288 ===================================
675 22:55:31.306548 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
676 22:55:31.310059 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
677 22:55:31.316321 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
678 22:55:31.319873 ===================================
679 22:55:31.319985 LPDDR4 DRAM CONFIGURATION
680 22:55:31.323304 ===================================
681 22:55:31.326544 EX_ROW_EN[0] = 0x10
682 22:55:31.326639 EX_ROW_EN[1] = 0x0
683 22:55:31.329903 LP4Y_EN = 0x0
684 22:55:31.329994 WORK_FSP = 0x0
685 22:55:31.333254 WL = 0x2
686 22:55:31.336448 RL = 0x2
687 22:55:31.336542 BL = 0x2
688 22:55:31.340140 RPST = 0x0
689 22:55:31.340229 RD_PRE = 0x0
690 22:55:31.342840 WR_PRE = 0x1
691 22:55:31.342928 WR_PST = 0x0
692 22:55:31.346302 DBI_WR = 0x0
693 22:55:31.346389 DBI_RD = 0x0
694 22:55:31.349586 OTF = 0x1
695 22:55:31.352722 ===================================
696 22:55:31.356340 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
697 22:55:31.361673 nWR fixed to 40
698 22:55:31.365094 [ModeRegInit_LP4] CH0 RK0
699 22:55:31.365186 [ModeRegInit_LP4] CH0 RK1
700 22:55:31.368430 [ModeRegInit_LP4] CH1 RK0
701 22:55:31.371552 [ModeRegInit_LP4] CH1 RK1
702 22:55:31.371642 match AC timing 13
703 22:55:31.378376 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
704 22:55:31.381526 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
705 22:55:31.385118 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
706 22:55:31.391624 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
707 22:55:31.394884 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
708 22:55:31.398184 [EMI DOE] emi_dcm 0
709 22:55:31.401486 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
710 22:55:31.401579 ==
711 22:55:31.406119 Dram Type= 6, Freq= 0, CH_0, rank 0
712 22:55:31.408192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
713 22:55:31.408283 ==
714 22:55:31.415025 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
715 22:55:31.421182 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
716 22:55:31.429911 [CA 0] Center 37 (7~68) winsize 62
717 22:55:31.432876 [CA 1] Center 38 (7~69) winsize 63
718 22:55:31.436352 [CA 2] Center 35 (5~66) winsize 62
719 22:55:31.439140 [CA 3] Center 35 (5~66) winsize 62
720 22:55:31.442542 [CA 4] Center 34 (4~65) winsize 62
721 22:55:31.446188 [CA 5] Center 33 (3~64) winsize 62
722 22:55:31.446278
723 22:55:31.450310 [CmdBusTrainingLP45] Vref(ca) range 1: 30
724 22:55:31.450399
725 22:55:31.452671 [CATrainingPosCal] consider 1 rank data
726 22:55:31.455837 u2DelayCellTimex100 = 270/100 ps
727 22:55:31.459501 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
728 22:55:31.466021 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
729 22:55:31.469115 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
730 22:55:31.472951 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
731 22:55:31.476127 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
732 22:55:31.479190 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
733 22:55:31.479282
734 22:55:31.482432 CA PerBit enable=1, Macro0, CA PI delay=33
735 22:55:31.482519
736 22:55:31.486043 [CBTSetCACLKResult] CA Dly = 33
737 22:55:31.486130 CS Dly: 5 (0~36)
738 22:55:31.489378 ==
739 22:55:31.489466 Dram Type= 6, Freq= 0, CH_0, rank 1
740 22:55:31.495770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
741 22:55:31.495913 ==
742 22:55:31.499465 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
743 22:55:31.506020 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
744 22:55:31.516044 [CA 0] Center 38 (7~69) winsize 63
745 22:55:31.519431 [CA 1] Center 38 (7~69) winsize 63
746 22:55:31.522280 [CA 2] Center 35 (5~66) winsize 62
747 22:55:31.525756 [CA 3] Center 35 (5~66) winsize 62
748 22:55:31.529021 [CA 4] Center 35 (4~66) winsize 63
749 22:55:31.532472 [CA 5] Center 34 (4~65) winsize 62
750 22:55:31.532562
751 22:55:31.535722 [CmdBusTrainingLP45] Vref(ca) range 1: 32
752 22:55:31.535808
753 22:55:31.539083 [CATrainingPosCal] consider 2 rank data
754 22:55:31.542556 u2DelayCellTimex100 = 270/100 ps
755 22:55:31.546065 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
756 22:55:31.549174 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
757 22:55:31.556210 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
758 22:55:31.559589 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
759 22:55:31.562402 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
760 22:55:31.565962 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
761 22:55:31.566051
762 22:55:31.569040 CA PerBit enable=1, Macro0, CA PI delay=34
763 22:55:31.569126
764 22:55:31.572453 [CBTSetCACLKResult] CA Dly = 34
765 22:55:31.572541 CS Dly: 5 (0~37)
766 22:55:31.572608
767 22:55:31.575875 ----->DramcWriteLeveling(PI) begin...
768 22:55:31.575964 ==
769 22:55:31.579031 Dram Type= 6, Freq= 0, CH_0, rank 0
770 22:55:31.585937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
771 22:55:31.586047 ==
772 22:55:31.589203 Write leveling (Byte 0): 33 => 33
773 22:55:31.592350 Write leveling (Byte 1): 29 => 29
774 22:55:31.595705 DramcWriteLeveling(PI) end<-----
775 22:55:31.595798
776 22:55:31.595868 ==
777 22:55:31.599828 Dram Type= 6, Freq= 0, CH_0, rank 0
778 22:55:31.602236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 22:55:31.602325 ==
780 22:55:31.606003 [Gating] SW mode calibration
781 22:55:31.614203 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
782 22:55:31.617460 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
783 22:55:31.620631 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
784 22:55:31.627519 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
785 22:55:31.630687 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
786 22:55:31.634836 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 22:55:31.637843 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 22:55:31.644878 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 22:55:31.648370 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 22:55:31.651517 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 22:55:31.658682 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 22:55:31.661346 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 22:55:31.664471 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 22:55:31.671119 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 22:55:31.674569 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 22:55:31.677578 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 22:55:31.684332 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 22:55:31.688188 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 22:55:31.691036 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
800 22:55:31.698078 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
801 22:55:31.700932 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
802 22:55:31.704210 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 22:55:31.710842 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 22:55:31.714147 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 22:55:31.718667 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 22:55:31.724514 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 22:55:31.727237 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 22:55:31.730578 0 9 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
809 22:55:31.737456 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
810 22:55:31.741066 0 9 12 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
811 22:55:31.744113 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 22:55:31.750475 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 22:55:31.753720 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 22:55:31.757129 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 22:55:31.763797 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
816 22:55:31.767376 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
817 22:55:31.770629 0 10 8 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
818 22:55:31.773598 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 22:55:31.780442 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 22:55:31.783504 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 22:55:31.787296 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 22:55:31.793504 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 22:55:31.796921 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 22:55:31.800335 0 11 4 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
825 22:55:31.806948 0 11 8 | B1->B0 | 2f2e 4646 | 1 0 | (0 0) (0 0)
826 22:55:31.810434 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
827 22:55:31.813421 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 22:55:31.820008 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 22:55:31.823633 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 22:55:31.826708 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 22:55:31.833460 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 22:55:31.836535 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
833 22:55:31.840317 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
834 22:55:31.846675 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 22:55:31.849995 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 22:55:31.853100 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 22:55:31.859783 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 22:55:31.862959 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 22:55:31.866284 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 22:55:31.873023 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 22:55:31.876440 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 22:55:31.879679 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 22:55:31.886532 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 22:55:31.889898 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 22:55:31.892935 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 22:55:31.899565 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 22:55:31.902648 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
848 22:55:31.906094 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
849 22:55:31.912708 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 22:55:31.912886 Total UI for P1: 0, mck2ui 16
851 22:55:31.919463 best dqsien dly found for B0: ( 0, 14, 2)
852 22:55:31.919613 Total UI for P1: 0, mck2ui 16
853 22:55:31.922861 best dqsien dly found for B1: ( 0, 14, 4)
854 22:55:31.929654 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
855 22:55:31.932713 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
856 22:55:31.932838
857 22:55:31.936094 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
858 22:55:31.939509 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
859 22:55:31.942739 [Gating] SW calibration Done
860 22:55:31.942830 ==
861 22:55:31.946042 Dram Type= 6, Freq= 0, CH_0, rank 0
862 22:55:31.949444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
863 22:55:31.949535 ==
864 22:55:31.949632 RX Vref Scan: 0
865 22:55:31.952942
866 22:55:31.953047 RX Vref 0 -> 0, step: 1
867 22:55:31.953147
868 22:55:31.956148 RX Delay -130 -> 252, step: 16
869 22:55:31.959544 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
870 22:55:31.963079 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
871 22:55:31.969436 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
872 22:55:31.973034 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
873 22:55:31.976396 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
874 22:55:31.979350 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
875 22:55:31.983384 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
876 22:55:31.989871 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
877 22:55:31.992943 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
878 22:55:31.996367 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
879 22:55:32.000104 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
880 22:55:32.002641 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
881 22:55:32.009145 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
882 22:55:32.012820 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
883 22:55:32.016126 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
884 22:55:32.019291 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
885 22:55:32.019391 ==
886 22:55:32.022727 Dram Type= 6, Freq= 0, CH_0, rank 0
887 22:55:32.029714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
888 22:55:32.029831 ==
889 22:55:32.029904 DQS Delay:
890 22:55:32.032638 DQS0 = 0, DQS1 = 0
891 22:55:32.032757 DQM Delay:
892 22:55:32.032871 DQM0 = 93, DQM1 = 82
893 22:55:32.036395 DQ Delay:
894 22:55:32.039163 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
895 22:55:32.042597 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
896 22:55:32.046302 DQ8 =77, DQ9 =61, DQ10 =85, DQ11 =77
897 22:55:32.049536 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
898 22:55:32.049637
899 22:55:32.049735
900 22:55:32.049812 ==
901 22:55:32.052467 Dram Type= 6, Freq= 0, CH_0, rank 0
902 22:55:32.056122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
903 22:55:32.056208 ==
904 22:55:32.056304
905 22:55:32.056416
906 22:55:32.059367 TX Vref Scan disable
907 22:55:32.062602 == TX Byte 0 ==
908 22:55:32.065909 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
909 22:55:32.069179 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
910 22:55:32.072701 == TX Byte 1 ==
911 22:55:32.075903 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
912 22:55:32.079158 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
913 22:55:32.079241 ==
914 22:55:32.082575 Dram Type= 6, Freq= 0, CH_0, rank 0
915 22:55:32.086062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
916 22:55:32.086170 ==
917 22:55:32.100574 TX Vref=22, minBit 6, minWin=27, winSum=440
918 22:55:32.103944 TX Vref=24, minBit 8, minWin=26, winSum=441
919 22:55:32.107126 TX Vref=26, minBit 8, minWin=26, winSum=442
920 22:55:32.110638 TX Vref=28, minBit 9, minWin=27, winSum=451
921 22:55:32.114245 TX Vref=30, minBit 11, minWin=27, winSum=455
922 22:55:32.120398 TX Vref=32, minBit 8, minWin=27, winSum=451
923 22:55:32.123869 [TxChooseVref] Worse bit 11, Min win 27, Win sum 455, Final Vref 30
924 22:55:32.123979
925 22:55:32.127803 Final TX Range 1 Vref 30
926 22:55:32.127899
927 22:55:32.127990 ==
928 22:55:32.130554 Dram Type= 6, Freq= 0, CH_0, rank 0
929 22:55:32.133884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
930 22:55:32.137272 ==
931 22:55:32.137369
932 22:55:32.137457
933 22:55:32.137553 TX Vref Scan disable
934 22:55:32.140731 == TX Byte 0 ==
935 22:55:32.144917 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
936 22:55:32.147640 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
937 22:55:32.150632 == TX Byte 1 ==
938 22:55:32.154978 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
939 22:55:32.160822 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
940 22:55:32.160933
941 22:55:32.161029 [DATLAT]
942 22:55:32.161113 Freq=800, CH0 RK0
943 22:55:32.161199
944 22:55:32.164091 DATLAT Default: 0xa
945 22:55:32.164183 0, 0xFFFF, sum = 0
946 22:55:32.167649 1, 0xFFFF, sum = 0
947 22:55:32.167742 2, 0xFFFF, sum = 0
948 22:55:32.171079 3, 0xFFFF, sum = 0
949 22:55:32.174604 4, 0xFFFF, sum = 0
950 22:55:32.174698 5, 0xFFFF, sum = 0
951 22:55:32.177685 6, 0xFFFF, sum = 0
952 22:55:32.177777 7, 0xFFFF, sum = 0
953 22:55:32.180893 8, 0xFFFF, sum = 0
954 22:55:32.180985 9, 0x0, sum = 1
955 22:55:32.181109 10, 0x0, sum = 2
956 22:55:32.184071 11, 0x0, sum = 3
957 22:55:32.184160 12, 0x0, sum = 4
958 22:55:32.187419 best_step = 10
959 22:55:32.187510
960 22:55:32.187615 ==
961 22:55:32.190711 Dram Type= 6, Freq= 0, CH_0, rank 0
962 22:55:32.194171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
963 22:55:32.194263 ==
964 22:55:32.197454 RX Vref Scan: 1
965 22:55:32.197544
966 22:55:32.197633 Set Vref Range= 32 -> 127
967 22:55:32.200684
968 22:55:32.200786 RX Vref 32 -> 127, step: 1
969 22:55:32.200905
970 22:55:32.203855 RX Delay -95 -> 252, step: 8
971 22:55:32.203944
972 22:55:32.207314 Set Vref, RX VrefLevel [Byte0]: 32
973 22:55:32.210632 [Byte1]: 32
974 22:55:32.210725
975 22:55:32.214880 Set Vref, RX VrefLevel [Byte0]: 33
976 22:55:32.217162 [Byte1]: 33
977 22:55:32.220986
978 22:55:32.221126 Set Vref, RX VrefLevel [Byte0]: 34
979 22:55:32.224453 [Byte1]: 34
980 22:55:32.228612
981 22:55:32.228772 Set Vref, RX VrefLevel [Byte0]: 35
982 22:55:32.231889 [Byte1]: 35
983 22:55:32.236329
984 22:55:32.236453 Set Vref, RX VrefLevel [Byte0]: 36
985 22:55:32.239446 [Byte1]: 36
986 22:55:32.243918
987 22:55:32.244018 Set Vref, RX VrefLevel [Byte0]: 37
988 22:55:32.246983 [Byte1]: 37
989 22:55:32.251429
990 22:55:32.251527 Set Vref, RX VrefLevel [Byte0]: 38
991 22:55:32.254943 [Byte1]: 38
992 22:55:32.259403
993 22:55:32.259525 Set Vref, RX VrefLevel [Byte0]: 39
994 22:55:32.262713 [Byte1]: 39
995 22:55:32.266717
996 22:55:32.266813 Set Vref, RX VrefLevel [Byte0]: 40
997 22:55:32.269926 [Byte1]: 40
998 22:55:32.275497
999 22:55:32.275629 Set Vref, RX VrefLevel [Byte0]: 41
1000 22:55:32.278140 [Byte1]: 41
1001 22:55:32.281805
1002 22:55:32.281899 Set Vref, RX VrefLevel [Byte0]: 42
1003 22:55:32.285898 [Byte1]: 42
1004 22:55:32.290096
1005 22:55:32.290204 Set Vref, RX VrefLevel [Byte0]: 43
1006 22:55:32.293043 [Byte1]: 43
1007 22:55:32.297397
1008 22:55:32.297497 Set Vref, RX VrefLevel [Byte0]: 44
1009 22:55:32.300665 [Byte1]: 44
1010 22:55:32.305012
1011 22:55:32.305113 Set Vref, RX VrefLevel [Byte0]: 45
1012 22:55:32.308443 [Byte1]: 45
1013 22:55:32.312218
1014 22:55:32.312314 Set Vref, RX VrefLevel [Byte0]: 46
1015 22:55:32.316106 [Byte1]: 46
1016 22:55:32.320212
1017 22:55:32.320309 Set Vref, RX VrefLevel [Byte0]: 47
1018 22:55:32.323166 [Byte1]: 47
1019 22:55:32.328109
1020 22:55:32.328202 Set Vref, RX VrefLevel [Byte0]: 48
1021 22:55:32.330861 [Byte1]: 48
1022 22:55:32.335259
1023 22:55:32.335355 Set Vref, RX VrefLevel [Byte0]: 49
1024 22:55:32.338835 [Byte1]: 49
1025 22:55:32.342775
1026 22:55:32.342874 Set Vref, RX VrefLevel [Byte0]: 50
1027 22:55:32.346321 [Byte1]: 50
1028 22:55:32.350533
1029 22:55:32.350624 Set Vref, RX VrefLevel [Byte0]: 51
1030 22:55:32.353618 [Byte1]: 51
1031 22:55:32.357876
1032 22:55:32.357969 Set Vref, RX VrefLevel [Byte0]: 52
1033 22:55:32.361195 [Byte1]: 52
1034 22:55:32.365804
1035 22:55:32.365899 Set Vref, RX VrefLevel [Byte0]: 53
1036 22:55:32.368943 [Byte1]: 53
1037 22:55:32.373401
1038 22:55:32.373492 Set Vref, RX VrefLevel [Byte0]: 54
1039 22:55:32.376677 [Byte1]: 54
1040 22:55:32.381055
1041 22:55:32.381188 Set Vref, RX VrefLevel [Byte0]: 55
1042 22:55:32.383895 [Byte1]: 55
1043 22:55:32.388086
1044 22:55:32.388178 Set Vref, RX VrefLevel [Byte0]: 56
1045 22:55:32.391571 [Byte1]: 56
1046 22:55:32.396515
1047 22:55:32.396608 Set Vref, RX VrefLevel [Byte0]: 57
1048 22:55:32.399164 [Byte1]: 57
1049 22:55:32.404306
1050 22:55:32.404397 Set Vref, RX VrefLevel [Byte0]: 58
1051 22:55:32.406847 [Byte1]: 58
1052 22:55:32.411402
1053 22:55:32.411493 Set Vref, RX VrefLevel [Byte0]: 59
1054 22:55:32.414354 [Byte1]: 59
1055 22:55:32.418819
1056 22:55:32.418915 Set Vref, RX VrefLevel [Byte0]: 60
1057 22:55:32.422085 [Byte1]: 60
1058 22:55:32.426371
1059 22:55:32.426463 Set Vref, RX VrefLevel [Byte0]: 61
1060 22:55:32.432970 [Byte1]: 61
1061 22:55:32.433070
1062 22:55:32.435921 Set Vref, RX VrefLevel [Byte0]: 62
1063 22:55:32.439477 [Byte1]: 62
1064 22:55:32.439570
1065 22:55:32.442471 Set Vref, RX VrefLevel [Byte0]: 63
1066 22:55:32.445973 [Byte1]: 63
1067 22:55:32.446068
1068 22:55:32.450130 Set Vref, RX VrefLevel [Byte0]: 64
1069 22:55:32.452481 [Byte1]: 64
1070 22:55:32.456715
1071 22:55:32.456818 Set Vref, RX VrefLevel [Byte0]: 65
1072 22:55:32.460045 [Byte1]: 65
1073 22:55:32.464298
1074 22:55:32.464393 Set Vref, RX VrefLevel [Byte0]: 66
1075 22:55:32.467604 [Byte1]: 66
1076 22:55:32.471757
1077 22:55:32.471855 Set Vref, RX VrefLevel [Byte0]: 67
1078 22:55:32.475404 [Byte1]: 67
1079 22:55:32.479173
1080 22:55:32.479272 Set Vref, RX VrefLevel [Byte0]: 68
1081 22:55:32.482735 [Byte1]: 68
1082 22:55:32.487315
1083 22:55:32.487443 Set Vref, RX VrefLevel [Byte0]: 69
1084 22:55:32.490477 [Byte1]: 69
1085 22:55:32.494646
1086 22:55:32.494768 Set Vref, RX VrefLevel [Byte0]: 70
1087 22:55:32.498113 [Byte1]: 70
1088 22:55:32.502261
1089 22:55:32.502357 Set Vref, RX VrefLevel [Byte0]: 71
1090 22:55:32.505386 [Byte1]: 71
1091 22:55:32.509938
1092 22:55:32.510035 Set Vref, RX VrefLevel [Byte0]: 72
1093 22:55:32.513387 [Byte1]: 72
1094 22:55:32.517610
1095 22:55:32.517713 Set Vref, RX VrefLevel [Byte0]: 73
1096 22:55:32.520620 [Byte1]: 73
1097 22:55:32.525120
1098 22:55:32.525221 Set Vref, RX VrefLevel [Byte0]: 74
1099 22:55:32.528122 [Byte1]: 74
1100 22:55:32.532585
1101 22:55:32.532713 Set Vref, RX VrefLevel [Byte0]: 75
1102 22:55:32.536373 [Byte1]: 75
1103 22:55:32.540116
1104 22:55:32.540224 Set Vref, RX VrefLevel [Byte0]: 76
1105 22:55:32.543861 [Byte1]: 76
1106 22:55:32.547546
1107 22:55:32.547654 Final RX Vref Byte 0 = 62 to rank0
1108 22:55:32.551426 Final RX Vref Byte 1 = 62 to rank0
1109 22:55:32.554786 Final RX Vref Byte 0 = 62 to rank1
1110 22:55:32.557446 Final RX Vref Byte 1 = 62 to rank1==
1111 22:55:32.560907 Dram Type= 6, Freq= 0, CH_0, rank 0
1112 22:55:32.567607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1113 22:55:32.567725 ==
1114 22:55:32.567819 DQS Delay:
1115 22:55:32.567903 DQS0 = 0, DQS1 = 0
1116 22:55:32.570875 DQM Delay:
1117 22:55:32.570963 DQM0 = 92, DQM1 = 83
1118 22:55:32.574561 DQ Delay:
1119 22:55:32.578189 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1120 22:55:32.580970 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1121 22:55:32.584366 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1122 22:55:32.587674 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =92
1123 22:55:32.587771
1124 22:55:32.587860
1125 22:55:32.594252 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c37, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1126 22:55:32.597537 CH0 RK0: MR19=606, MR18=3C37
1127 22:55:32.604042 CH0_RK0: MR19=0x606, MR18=0x3C37, DQSOSC=394, MR23=63, INC=95, DEC=63
1128 22:55:32.604164
1129 22:55:32.607762 ----->DramcWriteLeveling(PI) begin...
1130 22:55:32.607854 ==
1131 22:55:32.611157 Dram Type= 6, Freq= 0, CH_0, rank 1
1132 22:55:32.614265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1133 22:55:32.614369 ==
1134 22:55:32.617486 Write leveling (Byte 0): 31 => 31
1135 22:55:32.621039 Write leveling (Byte 1): 29 => 29
1136 22:55:32.624581 DramcWriteLeveling(PI) end<-----
1137 22:55:32.624714
1138 22:55:32.624843 ==
1139 22:55:32.627889 Dram Type= 6, Freq= 0, CH_0, rank 1
1140 22:55:32.630930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1141 22:55:32.631023 ==
1142 22:55:32.634379 [Gating] SW mode calibration
1143 22:55:32.640957 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1144 22:55:32.647852 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1145 22:55:32.650775 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1146 22:55:32.654308 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1147 22:55:32.660496 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1148 22:55:32.663885 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 22:55:32.667125 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 22:55:32.673861 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 22:55:32.677045 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 22:55:32.721303 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 22:55:32.721673 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 22:55:32.722229 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 22:55:32.722342 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 22:55:32.722796 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 22:55:32.723300 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 22:55:32.723763 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 22:55:32.724589 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 22:55:32.724696 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 22:55:32.724996 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 22:55:32.765405 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1163 22:55:32.765777 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1164 22:55:32.765872 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 22:55:32.765946 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 22:55:32.766303 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 22:55:32.766787 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 22:55:32.767285 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 22:55:32.767959 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 22:55:32.768111 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1171 22:55:32.768362 0 9 8 | B1->B0 | 2b2b 3333 | 0 1 | (0 0) (1 1)
1172 22:55:32.783462 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1173 22:55:32.783825 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1174 22:55:32.784088 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1175 22:55:32.784162 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 22:55:32.787133 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 22:55:32.790534 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 22:55:32.796868 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
1179 22:55:32.800457 0 10 8 | B1->B0 | 2e2e 2424 | 1 0 | (0 0) (0 0)
1180 22:55:32.803740 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 22:55:32.810193 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 22:55:32.813425 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 22:55:32.816996 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 22:55:32.824367 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 22:55:32.827063 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 22:55:32.830818 0 11 4 | B1->B0 | 2626 3231 | 0 1 | (0 0) (0 0)
1187 22:55:32.836791 0 11 8 | B1->B0 | 3939 4646 | 0 0 | (1 1) (0 0)
1188 22:55:32.840083 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 22:55:32.843547 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 22:55:32.849859 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 22:55:32.853991 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 22:55:32.857640 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 22:55:32.861255 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 22:55:32.868046 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1195 22:55:32.872229 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1196 22:55:32.874770 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 22:55:32.878494 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 22:55:32.885166 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 22:55:32.889647 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 22:55:32.892309 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 22:55:32.898620 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 22:55:32.901953 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 22:55:32.905509 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 22:55:32.912522 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 22:55:32.916104 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 22:55:32.918813 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 22:55:32.922038 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 22:55:32.928710 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 22:55:32.931909 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 22:55:32.935561 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1211 22:55:32.942214 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 22:55:32.945432 Total UI for P1: 0, mck2ui 16
1213 22:55:32.948919 best dqsien dly found for B0: ( 0, 14, 4)
1214 22:55:32.952045 Total UI for P1: 0, mck2ui 16
1215 22:55:32.955658 best dqsien dly found for B1: ( 0, 14, 4)
1216 22:55:32.958616 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1217 22:55:32.961996 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1218 22:55:32.962083
1219 22:55:32.965479 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1220 22:55:32.968747 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1221 22:55:32.972037 [Gating] SW calibration Done
1222 22:55:32.972124 ==
1223 22:55:32.975285 Dram Type= 6, Freq= 0, CH_0, rank 1
1224 22:55:32.978870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1225 22:55:32.978957 ==
1226 22:55:32.982229 RX Vref Scan: 0
1227 22:55:32.982327
1228 22:55:32.982393 RX Vref 0 -> 0, step: 1
1229 22:55:32.982454
1230 22:55:32.985509 RX Delay -130 -> 252, step: 16
1231 22:55:32.988750 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1232 22:55:32.995849 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1233 22:55:32.999292 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1234 22:55:33.001887 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1235 22:55:33.005233 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1236 22:55:33.008734 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1237 22:55:33.015095 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1238 22:55:33.018558 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1239 22:55:33.022018 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1240 22:55:33.025586 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1241 22:55:33.031721 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1242 22:55:33.034896 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1243 22:55:33.038781 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1244 22:55:33.041573 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1245 22:55:33.045216 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1246 22:55:33.051613 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1247 22:55:33.051714 ==
1248 22:55:33.055258 Dram Type= 6, Freq= 0, CH_0, rank 1
1249 22:55:33.058725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1250 22:55:33.058815 ==
1251 22:55:33.058882 DQS Delay:
1252 22:55:33.061538 DQS0 = 0, DQS1 = 0
1253 22:55:33.061622 DQM Delay:
1254 22:55:33.064983 DQM0 = 89, DQM1 = 80
1255 22:55:33.065068 DQ Delay:
1256 22:55:33.068191 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1257 22:55:33.071574 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1258 22:55:33.074844 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1259 22:55:33.078090 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
1260 22:55:33.078178
1261 22:55:33.078244
1262 22:55:33.078304 ==
1263 22:55:33.081477 Dram Type= 6, Freq= 0, CH_0, rank 1
1264 22:55:33.084731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1265 22:55:33.088423 ==
1266 22:55:33.088510
1267 22:55:33.088574
1268 22:55:33.088634 TX Vref Scan disable
1269 22:55:33.091474 == TX Byte 0 ==
1270 22:55:33.094913 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1271 22:55:33.097959 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1272 22:55:33.101389 == TX Byte 1 ==
1273 22:55:33.104551 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1274 22:55:33.108428 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1275 22:55:33.111197 ==
1276 22:55:33.114603 Dram Type= 6, Freq= 0, CH_0, rank 1
1277 22:55:33.117755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1278 22:55:33.117848 ==
1279 22:55:33.130539 TX Vref=22, minBit 3, minWin=27, winSum=445
1280 22:55:33.133754 TX Vref=24, minBit 8, minWin=27, winSum=448
1281 22:55:33.137089 TX Vref=26, minBit 8, minWin=27, winSum=448
1282 22:55:33.140644 TX Vref=28, minBit 8, minWin=27, winSum=452
1283 22:55:33.143866 TX Vref=30, minBit 8, minWin=27, winSum=454
1284 22:55:33.147160 TX Vref=32, minBit 8, minWin=27, winSum=453
1285 22:55:33.153958 [TxChooseVref] Worse bit 8, Min win 27, Win sum 454, Final Vref 30
1286 22:55:33.154086
1287 22:55:33.158134 Final TX Range 1 Vref 30
1288 22:55:33.158227
1289 22:55:33.158321 ==
1290 22:55:33.160578 Dram Type= 6, Freq= 0, CH_0, rank 1
1291 22:55:33.163626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1292 22:55:33.163703 ==
1293 22:55:33.163766
1294 22:55:33.163824
1295 22:55:33.167088 TX Vref Scan disable
1296 22:55:33.170737 == TX Byte 0 ==
1297 22:55:33.173908 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1298 22:55:33.177535 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1299 22:55:33.180267 == TX Byte 1 ==
1300 22:55:33.183898 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1301 22:55:33.187473 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1302 22:55:33.187560
1303 22:55:33.190522 [DATLAT]
1304 22:55:33.190627 Freq=800, CH0 RK1
1305 22:55:33.190695
1306 22:55:33.193836 DATLAT Default: 0xa
1307 22:55:33.193919 0, 0xFFFF, sum = 0
1308 22:55:33.197230 1, 0xFFFF, sum = 0
1309 22:55:33.197315 2, 0xFFFF, sum = 0
1310 22:55:33.200471 3, 0xFFFF, sum = 0
1311 22:55:33.200556 4, 0xFFFF, sum = 0
1312 22:55:33.203802 5, 0xFFFF, sum = 0
1313 22:55:33.203888 6, 0xFFFF, sum = 0
1314 22:55:33.207373 7, 0xFFFF, sum = 0
1315 22:55:33.207458 8, 0xFFFF, sum = 0
1316 22:55:33.210448 9, 0x0, sum = 1
1317 22:55:33.210531 10, 0x0, sum = 2
1318 22:55:33.213815 11, 0x0, sum = 3
1319 22:55:33.213900 12, 0x0, sum = 4
1320 22:55:33.217350 best_step = 10
1321 22:55:33.217436
1322 22:55:33.217501 ==
1323 22:55:33.220596 Dram Type= 6, Freq= 0, CH_0, rank 1
1324 22:55:33.223694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1325 22:55:33.223789 ==
1326 22:55:33.227440 RX Vref Scan: 0
1327 22:55:33.227524
1328 22:55:33.227589 RX Vref 0 -> 0, step: 1
1329 22:55:33.227648
1330 22:55:33.230498 RX Delay -79 -> 252, step: 8
1331 22:55:33.237233 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1332 22:55:33.240579 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1333 22:55:33.243967 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1334 22:55:33.247176 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1335 22:55:33.250259 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1336 22:55:33.256975 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1337 22:55:33.260230 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1338 22:55:33.263664 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1339 22:55:33.267322 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1340 22:55:33.270440 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1341 22:55:33.276990 iDelay=209, Bit 10, Center 84 (-15 ~ 184) 200
1342 22:55:33.280198 iDelay=209, Bit 11, Center 76 (-23 ~ 176) 200
1343 22:55:33.283435 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1344 22:55:33.286901 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1345 22:55:33.290600 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1346 22:55:33.297100 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1347 22:55:33.297202 ==
1348 22:55:33.300123 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 22:55:33.303499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 22:55:33.303585 ==
1351 22:55:33.303650 DQS Delay:
1352 22:55:33.306866 DQS0 = 0, DQS1 = 0
1353 22:55:33.306949 DQM Delay:
1354 22:55:33.310095 DQM0 = 91, DQM1 = 81
1355 22:55:33.310182 DQ Delay:
1356 22:55:33.313550 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1357 22:55:33.318432 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1358 22:55:33.320131 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1359 22:55:33.323396 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1360 22:55:33.323483
1361 22:55:33.323549
1362 22:55:33.333715 [DQSOSCAuto] RK1, (LSB)MR18= 0x441e, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
1363 22:55:33.333842 CH0 RK1: MR19=606, MR18=441E
1364 22:55:33.340208 CH0_RK1: MR19=0x606, MR18=0x441E, DQSOSC=392, MR23=63, INC=96, DEC=64
1365 22:55:33.343524 [RxdqsGatingPostProcess] freq 800
1366 22:55:33.351047 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1367 22:55:33.353951 Pre-setting of DQS Precalculation
1368 22:55:33.357183 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1369 22:55:33.357290 ==
1370 22:55:33.360091 Dram Type= 6, Freq= 0, CH_1, rank 0
1371 22:55:33.363554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1372 22:55:33.363647 ==
1373 22:55:33.370265 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1374 22:55:33.376690 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1375 22:55:33.385464 [CA 0] Center 36 (6~67) winsize 62
1376 22:55:33.388762 [CA 1] Center 36 (6~67) winsize 62
1377 22:55:33.392791 [CA 2] Center 34 (4~65) winsize 62
1378 22:55:33.395196 [CA 3] Center 34 (3~65) winsize 63
1379 22:55:33.398499 [CA 4] Center 34 (4~65) winsize 62
1380 22:55:33.401717 [CA 5] Center 34 (3~65) winsize 63
1381 22:55:33.401807
1382 22:55:33.405460 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1383 22:55:33.405548
1384 22:55:33.408369 [CATrainingPosCal] consider 1 rank data
1385 22:55:33.412127 u2DelayCellTimex100 = 270/100 ps
1386 22:55:33.415225 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1387 22:55:33.421767 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1388 22:55:33.425070 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1389 22:55:33.428304 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1390 22:55:33.431715 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1391 22:55:33.435040 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1392 22:55:33.435139
1393 22:55:33.438310 CA PerBit enable=1, Macro0, CA PI delay=34
1394 22:55:33.438399
1395 22:55:33.441764 [CBTSetCACLKResult] CA Dly = 34
1396 22:55:33.441851 CS Dly: 5 (0~36)
1397 22:55:33.445236 ==
1398 22:55:33.445321 Dram Type= 6, Freq= 0, CH_1, rank 1
1399 22:55:33.451844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1400 22:55:33.451950 ==
1401 22:55:33.455110 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1402 22:55:33.461855 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1403 22:55:33.472062 [CA 0] Center 36 (6~67) winsize 62
1404 22:55:33.474930 [CA 1] Center 36 (6~67) winsize 62
1405 22:55:33.478093 [CA 2] Center 35 (5~66) winsize 62
1406 22:55:33.481703 [CA 3] Center 34 (4~65) winsize 62
1407 22:55:33.485015 [CA 4] Center 34 (4~65) winsize 62
1408 22:55:33.488001 [CA 5] Center 34 (3~65) winsize 63
1409 22:55:33.488088
1410 22:55:33.491215 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1411 22:55:33.491303
1412 22:55:33.495142 [CATrainingPosCal] consider 2 rank data
1413 22:55:33.498030 u2DelayCellTimex100 = 270/100 ps
1414 22:55:33.501347 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1415 22:55:33.508059 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1416 22:55:33.511373 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1417 22:55:33.514827 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1418 22:55:33.518523 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1419 22:55:33.521961 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1420 22:55:33.522070
1421 22:55:33.525542 CA PerBit enable=1, Macro0, CA PI delay=34
1422 22:55:33.525647
1423 22:55:33.528979 [CBTSetCACLKResult] CA Dly = 34
1424 22:55:33.529070 CS Dly: 6 (0~38)
1425 22:55:33.529177
1426 22:55:33.532717 ----->DramcWriteLeveling(PI) begin...
1427 22:55:33.532844 ==
1428 22:55:33.536575 Dram Type= 6, Freq= 0, CH_1, rank 0
1429 22:55:33.540216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1430 22:55:33.540311 ==
1431 22:55:33.544222 Write leveling (Byte 0): 27 => 27
1432 22:55:33.547623 Write leveling (Byte 1): 29 => 29
1433 22:55:33.551598 DramcWriteLeveling(PI) end<-----
1434 22:55:33.551696
1435 22:55:33.551764 ==
1436 22:55:33.555383 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 22:55:33.558928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 22:55:33.559024 ==
1439 22:55:33.562165 [Gating] SW mode calibration
1440 22:55:33.568727 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1441 22:55:33.572043 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1442 22:55:33.579012 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1443 22:55:33.581940 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 22:55:33.585174 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1445 22:55:33.592070 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 22:55:33.596231 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 22:55:33.599157 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 22:55:33.605498 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 22:55:33.608512 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 22:55:33.611879 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 22:55:33.615114 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 22:55:33.621827 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 22:55:33.625825 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 22:55:33.628558 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 22:55:33.635130 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 22:55:33.638552 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 22:55:33.641872 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 22:55:33.648656 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1459 22:55:33.651814 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1460 22:55:33.655185 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 22:55:33.661974 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 22:55:33.665012 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 22:55:33.668817 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 22:55:33.674905 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 22:55:33.678333 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 22:55:33.681639 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 22:55:33.688125 0 9 4 | B1->B0 | 2525 2d2d | 1 1 | (1 1) (1 1)
1468 22:55:33.691746 0 9 8 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1469 22:55:33.694790 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1470 22:55:33.701768 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1471 22:55:33.705039 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1472 22:55:33.708556 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 22:55:33.714853 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 22:55:33.718244 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
1475 22:55:33.721395 0 10 4 | B1->B0 | 3030 2d2d | 0 0 | (0 1) (1 1)
1476 22:55:33.728162 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1477 22:55:33.732072 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 22:55:33.735147 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 22:55:33.738186 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 22:55:33.745160 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 22:55:33.748278 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 22:55:33.751246 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 22:55:33.758216 0 11 4 | B1->B0 | 2e2e 3a3a | 0 0 | (0 0) (0 0)
1484 22:55:33.761376 0 11 8 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1485 22:55:33.765311 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1486 22:55:33.771417 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1487 22:55:33.774734 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1488 22:55:33.778070 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 22:55:33.784627 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 22:55:33.788508 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 22:55:33.791484 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1492 22:55:33.797856 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1493 22:55:33.801362 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 22:55:33.804723 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 22:55:33.811534 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 22:55:33.814406 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 22:55:33.817713 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 22:55:33.824398 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 22:55:33.827944 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 22:55:33.831826 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 22:55:33.837883 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 22:55:33.841284 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 22:55:33.844510 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 22:55:33.851329 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 22:55:33.854367 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 22:55:33.857737 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1507 22:55:33.864600 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1508 22:55:33.864717 Total UI for P1: 0, mck2ui 16
1509 22:55:33.871053 best dqsien dly found for B0: ( 0, 14, 0)
1510 22:55:33.874556 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 22:55:33.877542 Total UI for P1: 0, mck2ui 16
1512 22:55:33.880935 best dqsien dly found for B1: ( 0, 14, 2)
1513 22:55:33.884326 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1514 22:55:33.887712 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1515 22:55:33.887831
1516 22:55:33.890866 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1517 22:55:33.894233 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1518 22:55:33.897788 [Gating] SW calibration Done
1519 22:55:33.897875 ==
1520 22:55:33.901163 Dram Type= 6, Freq= 0, CH_1, rank 0
1521 22:55:33.904437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1522 22:55:33.904526 ==
1523 22:55:33.907483 RX Vref Scan: 0
1524 22:55:33.907568
1525 22:55:33.911574 RX Vref 0 -> 0, step: 1
1526 22:55:33.911660
1527 22:55:33.911726 RX Delay -130 -> 252, step: 16
1528 22:55:33.917799 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1529 22:55:33.921118 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1530 22:55:33.924158 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1531 22:55:33.927397 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1532 22:55:33.931037 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1533 22:55:33.937651 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1534 22:55:33.940657 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1535 22:55:33.944750 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1536 22:55:33.947392 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1537 22:55:33.950656 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1538 22:55:33.957816 iDelay=206, Bit 10, Center 93 (-18 ~ 205) 224
1539 22:55:33.960970 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1540 22:55:33.964515 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1541 22:55:33.967306 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1542 22:55:33.970499 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1543 22:55:33.977773 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1544 22:55:33.977877 ==
1545 22:55:33.980809 Dram Type= 6, Freq= 0, CH_1, rank 0
1546 22:55:33.983881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1547 22:55:33.983972 ==
1548 22:55:33.984039 DQS Delay:
1549 22:55:33.987322 DQS0 = 0, DQS1 = 0
1550 22:55:33.987407 DQM Delay:
1551 22:55:33.990781 DQM0 = 90, DQM1 = 85
1552 22:55:33.990868 DQ Delay:
1553 22:55:33.994409 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1554 22:55:33.997357 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =93
1555 22:55:34.000567 DQ8 =69, DQ9 =69, DQ10 =93, DQ11 =77
1556 22:55:34.004300 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1557 22:55:34.004387
1558 22:55:34.004454
1559 22:55:34.004514 ==
1560 22:55:34.007625 Dram Type= 6, Freq= 0, CH_1, rank 0
1561 22:55:34.010524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1562 22:55:34.013801 ==
1563 22:55:34.013887
1564 22:55:34.013953
1565 22:55:34.014013 TX Vref Scan disable
1566 22:55:34.017495 == TX Byte 0 ==
1567 22:55:34.020571 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1568 22:55:34.023806 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1569 22:55:34.026998 == TX Byte 1 ==
1570 22:55:34.030453 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1571 22:55:34.034072 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1572 22:55:34.034161 ==
1573 22:55:34.037028 Dram Type= 6, Freq= 0, CH_1, rank 0
1574 22:55:34.043501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1575 22:55:34.043597 ==
1576 22:55:34.055866 TX Vref=22, minBit 8, minWin=27, winSum=448
1577 22:55:34.059008 TX Vref=24, minBit 10, minWin=27, winSum=453
1578 22:55:34.062747 TX Vref=26, minBit 13, minWin=27, winSum=452
1579 22:55:34.065527 TX Vref=28, minBit 15, minWin=27, winSum=458
1580 22:55:34.069034 TX Vref=30, minBit 15, minWin=27, winSum=457
1581 22:55:34.075865 TX Vref=32, minBit 12, minWin=27, winSum=454
1582 22:55:34.079371 [TxChooseVref] Worse bit 15, Min win 27, Win sum 458, Final Vref 28
1583 22:55:34.079469
1584 22:55:34.082230 Final TX Range 1 Vref 28
1585 22:55:34.082318
1586 22:55:34.082384 ==
1587 22:55:34.085598 Dram Type= 6, Freq= 0, CH_1, rank 0
1588 22:55:34.092355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1589 22:55:34.092466 ==
1590 22:55:34.092534
1591 22:55:34.092596
1592 22:55:34.092654 TX Vref Scan disable
1593 22:55:34.096556 == TX Byte 0 ==
1594 22:55:34.099814 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1595 22:55:34.106034 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1596 22:55:34.106140 == TX Byte 1 ==
1597 22:55:34.109754 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1598 22:55:34.113143 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1599 22:55:34.113237
1600 22:55:34.116799 [DATLAT]
1601 22:55:34.116904 Freq=800, CH1 RK0
1602 22:55:34.116972
1603 22:55:34.119808 DATLAT Default: 0xa
1604 22:55:34.119894 0, 0xFFFF, sum = 0
1605 22:55:34.123391 1, 0xFFFF, sum = 0
1606 22:55:34.123480 2, 0xFFFF, sum = 0
1607 22:55:34.126746 3, 0xFFFF, sum = 0
1608 22:55:34.126834 4, 0xFFFF, sum = 0
1609 22:55:34.130314 5, 0xFFFF, sum = 0
1610 22:55:34.130403 6, 0xFFFF, sum = 0
1611 22:55:34.133379 7, 0xFFFF, sum = 0
1612 22:55:34.133466 8, 0xFFFF, sum = 0
1613 22:55:34.136626 9, 0x0, sum = 1
1614 22:55:34.136713 10, 0x0, sum = 2
1615 22:55:34.140066 11, 0x0, sum = 3
1616 22:55:34.140153 12, 0x0, sum = 4
1617 22:55:34.142946 best_step = 10
1618 22:55:34.143031
1619 22:55:34.143098 ==
1620 22:55:34.147621 Dram Type= 6, Freq= 0, CH_1, rank 0
1621 22:55:34.150280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1622 22:55:34.150368 ==
1623 22:55:34.153162 RX Vref Scan: 1
1624 22:55:34.153248
1625 22:55:34.153315 Set Vref Range= 32 -> 127
1626 22:55:34.153378
1627 22:55:34.156442 RX Vref 32 -> 127, step: 1
1628 22:55:34.156526
1629 22:55:34.159625 RX Delay -95 -> 252, step: 8
1630 22:55:34.159711
1631 22:55:34.163685 Set Vref, RX VrefLevel [Byte0]: 32
1632 22:55:34.166622 [Byte1]: 32
1633 22:55:34.166709
1634 22:55:34.170343 Set Vref, RX VrefLevel [Byte0]: 33
1635 22:55:34.172703 [Byte1]: 33
1636 22:55:34.176283
1637 22:55:34.179652 Set Vref, RX VrefLevel [Byte0]: 34
1638 22:55:34.179742 [Byte1]: 34
1639 22:55:34.183895
1640 22:55:34.183988 Set Vref, RX VrefLevel [Byte0]: 35
1641 22:55:34.187254 [Byte1]: 35
1642 22:55:34.191781
1643 22:55:34.191876 Set Vref, RX VrefLevel [Byte0]: 36
1644 22:55:34.194934 [Byte1]: 36
1645 22:55:34.199352
1646 22:55:34.199446 Set Vref, RX VrefLevel [Byte0]: 37
1647 22:55:34.202843 [Byte1]: 37
1648 22:55:34.206729
1649 22:55:34.206817 Set Vref, RX VrefLevel [Byte0]: 38
1650 22:55:34.213315 [Byte1]: 38
1651 22:55:34.213415
1652 22:55:34.216738 Set Vref, RX VrefLevel [Byte0]: 39
1653 22:55:34.220287 [Byte1]: 39
1654 22:55:34.220380
1655 22:55:34.223251 Set Vref, RX VrefLevel [Byte0]: 40
1656 22:55:34.226845 [Byte1]: 40
1657 22:55:34.226936
1658 22:55:34.229785 Set Vref, RX VrefLevel [Byte0]: 41
1659 22:55:34.233015 [Byte1]: 41
1660 22:55:34.237408
1661 22:55:34.237500 Set Vref, RX VrefLevel [Byte0]: 42
1662 22:55:34.240559 [Byte1]: 42
1663 22:55:34.244992
1664 22:55:34.245085 Set Vref, RX VrefLevel [Byte0]: 43
1665 22:55:34.248292 [Byte1]: 43
1666 22:55:34.252355
1667 22:55:34.252446 Set Vref, RX VrefLevel [Byte0]: 44
1668 22:55:34.255683 [Byte1]: 44
1669 22:55:34.260169
1670 22:55:34.260260 Set Vref, RX VrefLevel [Byte0]: 45
1671 22:55:34.263290 [Byte1]: 45
1672 22:55:34.267662
1673 22:55:34.267756 Set Vref, RX VrefLevel [Byte0]: 46
1674 22:55:34.271015 [Byte1]: 46
1675 22:55:34.275236
1676 22:55:34.275327 Set Vref, RX VrefLevel [Byte0]: 47
1677 22:55:34.278877 [Byte1]: 47
1678 22:55:34.283039
1679 22:55:34.283136 Set Vref, RX VrefLevel [Byte0]: 48
1680 22:55:34.286527 [Byte1]: 48
1681 22:55:34.290302
1682 22:55:34.290395 Set Vref, RX VrefLevel [Byte0]: 49
1683 22:55:34.294000 [Byte1]: 49
1684 22:55:34.298592
1685 22:55:34.298684 Set Vref, RX VrefLevel [Byte0]: 50
1686 22:55:34.301241 [Byte1]: 50
1687 22:55:34.305672
1688 22:55:34.305767 Set Vref, RX VrefLevel [Byte0]: 51
1689 22:55:34.312692 [Byte1]: 51
1690 22:55:34.312851
1691 22:55:34.315388 Set Vref, RX VrefLevel [Byte0]: 52
1692 22:55:34.318733 [Byte1]: 52
1693 22:55:34.318828
1694 22:55:34.321978 Set Vref, RX VrefLevel [Byte0]: 53
1695 22:55:34.325260 [Byte1]: 53
1696 22:55:34.325360
1697 22:55:34.329042 Set Vref, RX VrefLevel [Byte0]: 54
1698 22:55:34.332455 [Byte1]: 54
1699 22:55:34.335847
1700 22:55:34.335937 Set Vref, RX VrefLevel [Byte0]: 55
1701 22:55:34.339295 [Byte1]: 55
1702 22:55:34.343432
1703 22:55:34.343522 Set Vref, RX VrefLevel [Byte0]: 56
1704 22:55:34.346905 [Byte1]: 56
1705 22:55:34.351528
1706 22:55:34.351621 Set Vref, RX VrefLevel [Byte0]: 57
1707 22:55:34.354357 [Byte1]: 57
1708 22:55:34.358984
1709 22:55:34.359078 Set Vref, RX VrefLevel [Byte0]: 58
1710 22:55:34.362207 [Byte1]: 58
1711 22:55:34.366523
1712 22:55:34.366615 Set Vref, RX VrefLevel [Byte0]: 59
1713 22:55:34.369674 [Byte1]: 59
1714 22:55:34.373985
1715 22:55:34.374075 Set Vref, RX VrefLevel [Byte0]: 60
1716 22:55:34.377300 [Byte1]: 60
1717 22:55:34.381550
1718 22:55:34.381656 Set Vref, RX VrefLevel [Byte0]: 61
1719 22:55:34.385046 [Byte1]: 61
1720 22:55:34.389495
1721 22:55:34.389590 Set Vref, RX VrefLevel [Byte0]: 62
1722 22:55:34.392429 [Byte1]: 62
1723 22:55:34.396691
1724 22:55:34.396870 Set Vref, RX VrefLevel [Byte0]: 63
1725 22:55:34.399913 [Byte1]: 63
1726 22:55:34.404238
1727 22:55:34.404337 Set Vref, RX VrefLevel [Byte0]: 64
1728 22:55:34.407991 [Byte1]: 64
1729 22:55:34.411964
1730 22:55:34.412058 Set Vref, RX VrefLevel [Byte0]: 65
1731 22:55:34.415343 [Byte1]: 65
1732 22:55:34.419642
1733 22:55:34.419746 Set Vref, RX VrefLevel [Byte0]: 66
1734 22:55:34.422997 [Byte1]: 66
1735 22:55:34.427429
1736 22:55:34.427527 Set Vref, RX VrefLevel [Byte0]: 67
1737 22:55:34.430516 [Byte1]: 67
1738 22:55:34.434939
1739 22:55:34.435032 Set Vref, RX VrefLevel [Byte0]: 68
1740 22:55:34.438758 [Byte1]: 68
1741 22:55:34.442489
1742 22:55:34.442581 Set Vref, RX VrefLevel [Byte0]: 69
1743 22:55:34.446169 [Byte1]: 69
1744 22:55:34.449773
1745 22:55:34.449862 Set Vref, RX VrefLevel [Byte0]: 70
1746 22:55:34.453234 [Byte1]: 70
1747 22:55:34.457371
1748 22:55:34.457464 Set Vref, RX VrefLevel [Byte0]: 71
1749 22:55:34.460753 [Byte1]: 71
1750 22:55:34.465107
1751 22:55:34.465198 Set Vref, RX VrefLevel [Byte0]: 72
1752 22:55:34.468753 [Byte1]: 72
1753 22:55:34.472762
1754 22:55:34.472895 Set Vref, RX VrefLevel [Byte0]: 73
1755 22:55:34.476248 [Byte1]: 73
1756 22:55:34.480238
1757 22:55:34.480329 Set Vref, RX VrefLevel [Byte0]: 74
1758 22:55:34.483840 [Byte1]: 74
1759 22:55:34.488004
1760 22:55:34.488095 Set Vref, RX VrefLevel [Byte0]: 75
1761 22:55:34.491500 [Byte1]: 75
1762 22:55:34.495601
1763 22:55:34.495693 Final RX Vref Byte 0 = 49 to rank0
1764 22:55:34.498603 Final RX Vref Byte 1 = 63 to rank0
1765 22:55:34.502097 Final RX Vref Byte 0 = 49 to rank1
1766 22:55:34.505286 Final RX Vref Byte 1 = 63 to rank1==
1767 22:55:34.508801 Dram Type= 6, Freq= 0, CH_1, rank 0
1768 22:55:34.515381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1769 22:55:34.515489 ==
1770 22:55:34.515561 DQS Delay:
1771 22:55:34.515624 DQS0 = 0, DQS1 = 0
1772 22:55:34.518690 DQM Delay:
1773 22:55:34.518779 DQM0 = 91, DQM1 = 83
1774 22:55:34.522300 DQ Delay:
1775 22:55:34.525838 DQ0 =96, DQ1 =84, DQ2 =80, DQ3 =88
1776 22:55:34.528646 DQ4 =92, DQ5 =100, DQ6 =100, DQ7 =88
1777 22:55:34.532076 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =80
1778 22:55:34.535437 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1779 22:55:34.535527
1780 22:55:34.535595
1781 22:55:34.542501 [DQSOSCAuto] RK0, (LSB)MR18= 0x324f, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1782 22:55:34.545590 CH1 RK0: MR19=606, MR18=324F
1783 22:55:34.552617 CH1_RK0: MR19=0x606, MR18=0x324F, DQSOSC=390, MR23=63, INC=97, DEC=64
1784 22:55:34.552725
1785 22:55:34.555528 ----->DramcWriteLeveling(PI) begin...
1786 22:55:34.555616 ==
1787 22:55:34.558504 Dram Type= 6, Freq= 0, CH_1, rank 1
1788 22:55:34.561894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1789 22:55:34.561984 ==
1790 22:55:34.565142 Write leveling (Byte 0): 30 => 30
1791 22:55:34.568327 Write leveling (Byte 1): 29 => 29
1792 22:55:34.571639 DramcWriteLeveling(PI) end<-----
1793 22:55:34.571727
1794 22:55:34.571794 ==
1795 22:55:34.575156 Dram Type= 6, Freq= 0, CH_1, rank 1
1796 22:55:34.578493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1797 22:55:34.578584 ==
1798 22:55:34.581635 [Gating] SW mode calibration
1799 22:55:34.588243 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1800 22:55:34.595243 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1801 22:55:34.598269 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1802 22:55:34.604772 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1803 22:55:34.608259 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 22:55:34.612129 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 22:55:34.618519 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 22:55:34.621359 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 22:55:34.624707 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 22:55:34.628022 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 22:55:34.634751 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 22:55:34.638187 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 22:55:34.641523 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 22:55:34.648359 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 22:55:34.651669 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 22:55:34.655103 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 22:55:34.661557 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 22:55:34.665066 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 22:55:34.668316 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1818 22:55:34.674801 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1819 22:55:34.678314 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 22:55:34.681235 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 22:55:34.687937 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 22:55:34.691633 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 22:55:34.694499 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 22:55:34.701279 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 22:55:34.704399 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 22:55:34.707697 0 9 4 | B1->B0 | 2424 2323 | 1 1 | (1 1) (1 1)
1827 22:55:34.714460 0 9 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
1828 22:55:34.717578 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 22:55:34.721009 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 22:55:34.727688 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 22:55:34.731024 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 22:55:34.734384 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 22:55:34.740905 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 22:55:34.744550 0 10 4 | B1->B0 | 2f2f 2f2f | 1 0 | (1 0) (1 0)
1835 22:55:34.747573 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 22:55:34.754157 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 22:55:34.757968 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 22:55:34.761712 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 22:55:34.768026 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 22:55:34.770752 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 22:55:34.774303 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 22:55:34.777665 0 11 4 | B1->B0 | 3131 2b2b | 0 0 | (0 0) (0 0)
1843 22:55:34.784261 0 11 8 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
1844 22:55:34.787317 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 22:55:34.791207 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 22:55:34.797828 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 22:55:34.801001 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 22:55:34.804244 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 22:55:34.810596 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 22:55:34.813834 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1851 22:55:34.817116 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 22:55:34.824030 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 22:55:34.827238 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 22:55:34.830518 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 22:55:34.837441 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 22:55:34.840734 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 22:55:34.844291 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 22:55:34.850432 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 22:55:34.853784 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 22:55:34.856947 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 22:55:34.863931 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 22:55:34.867684 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 22:55:34.870246 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 22:55:34.877120 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 22:55:34.880300 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 22:55:34.883842 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1867 22:55:34.890328 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 22:55:34.890435 Total UI for P1: 0, mck2ui 16
1869 22:55:34.897094 best dqsien dly found for B0: ( 0, 14, 4)
1870 22:55:34.897196 Total UI for P1: 0, mck2ui 16
1871 22:55:34.900505 best dqsien dly found for B1: ( 0, 14, 4)
1872 22:55:34.907255 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1873 22:55:34.910105 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1874 22:55:34.910199
1875 22:55:34.913739 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1876 22:55:34.916739 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1877 22:55:34.920260 [Gating] SW calibration Done
1878 22:55:34.920356 ==
1879 22:55:34.923702 Dram Type= 6, Freq= 0, CH_1, rank 1
1880 22:55:34.926697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1881 22:55:34.926798 ==
1882 22:55:34.929921 RX Vref Scan: 0
1883 22:55:34.930006
1884 22:55:34.930072 RX Vref 0 -> 0, step: 1
1885 22:55:34.930133
1886 22:55:34.933463 RX Delay -130 -> 252, step: 16
1887 22:55:34.936725 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1888 22:55:34.943881 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1889 22:55:34.946988 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1890 22:55:34.950258 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1891 22:55:34.953771 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1892 22:55:34.957045 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1893 22:55:34.960817 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1894 22:55:34.967167 iDelay=222, Bit 7, Center 85 (-18 ~ 189) 208
1895 22:55:34.970742 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1896 22:55:34.974098 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1897 22:55:34.977120 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1898 22:55:34.980618 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1899 22:55:34.986975 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1900 22:55:34.990159 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1901 22:55:34.994052 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1902 22:55:34.997049 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1903 22:55:34.997142 ==
1904 22:55:35.000216 Dram Type= 6, Freq= 0, CH_1, rank 1
1905 22:55:35.006715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1906 22:55:35.006813 ==
1907 22:55:35.006883 DQS Delay:
1908 22:55:35.010238 DQS0 = 0, DQS1 = 0
1909 22:55:35.010326 DQM Delay:
1910 22:55:35.010393 DQM0 = 88, DQM1 = 82
1911 22:55:35.013889 DQ Delay:
1912 22:55:35.017607 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1913 22:55:35.020221 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1914 22:55:35.023443 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1915 22:55:35.026951 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1916 22:55:35.027047
1917 22:55:35.027117
1918 22:55:35.027178 ==
1919 22:55:35.030444 Dram Type= 6, Freq= 0, CH_1, rank 1
1920 22:55:35.033534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1921 22:55:35.033621 ==
1922 22:55:35.033688
1923 22:55:35.033749
1924 22:55:35.037529 TX Vref Scan disable
1925 22:55:35.040606 == TX Byte 0 ==
1926 22:55:35.043468 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1927 22:55:35.047060 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1928 22:55:35.047150 == TX Byte 1 ==
1929 22:55:35.053546 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1930 22:55:35.056893 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1931 22:55:35.056986 ==
1932 22:55:35.060064 Dram Type= 6, Freq= 0, CH_1, rank 1
1933 22:55:35.063469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1934 22:55:35.063563 ==
1935 22:55:35.077546 TX Vref=22, minBit 5, minWin=27, winSum=447
1936 22:55:35.081222 TX Vref=24, minBit 13, minWin=27, winSum=451
1937 22:55:35.084245 TX Vref=26, minBit 3, minWin=27, winSum=453
1938 22:55:35.087641 TX Vref=28, minBit 3, minWin=28, winSum=459
1939 22:55:35.090682 TX Vref=30, minBit 9, minWin=27, winSum=456
1940 22:55:35.097513 TX Vref=32, minBit 8, minWin=28, winSum=457
1941 22:55:35.101021 [TxChooseVref] Worse bit 3, Min win 28, Win sum 459, Final Vref 28
1942 22:55:35.101118
1943 22:55:35.104155 Final TX Range 1 Vref 28
1944 22:55:35.104242
1945 22:55:35.104309 ==
1946 22:55:35.107413 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 22:55:35.110882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 22:55:35.110970 ==
1949 22:55:35.114002
1950 22:55:35.114088
1951 22:55:35.114155 TX Vref Scan disable
1952 22:55:35.117695 == TX Byte 0 ==
1953 22:55:35.120827 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1954 22:55:35.124486 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1955 22:55:35.127678 == TX Byte 1 ==
1956 22:55:35.131263 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1957 22:55:35.134109 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1958 22:55:35.137652
1959 22:55:35.137743 [DATLAT]
1960 22:55:35.137810 Freq=800, CH1 RK1
1961 22:55:35.137872
1962 22:55:35.140886 DATLAT Default: 0xa
1963 22:55:35.140972 0, 0xFFFF, sum = 0
1964 22:55:35.144757 1, 0xFFFF, sum = 0
1965 22:55:35.144856 2, 0xFFFF, sum = 0
1966 22:55:35.148205 3, 0xFFFF, sum = 0
1967 22:55:35.148293 4, 0xFFFF, sum = 0
1968 22:55:35.150943 5, 0xFFFF, sum = 0
1969 22:55:35.154131 6, 0xFFFF, sum = 0
1970 22:55:35.154219 7, 0xFFFF, sum = 0
1971 22:55:35.157267 8, 0xFFFF, sum = 0
1972 22:55:35.157355 9, 0x0, sum = 1
1973 22:55:35.160562 10, 0x0, sum = 2
1974 22:55:35.160650 11, 0x0, sum = 3
1975 22:55:35.160718 12, 0x0, sum = 4
1976 22:55:35.164046 best_step = 10
1977 22:55:35.164132
1978 22:55:35.164199 ==
1979 22:55:35.167622 Dram Type= 6, Freq= 0, CH_1, rank 1
1980 22:55:35.170656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1981 22:55:35.170745 ==
1982 22:55:35.173864 RX Vref Scan: 0
1983 22:55:35.173951
1984 22:55:35.174018 RX Vref 0 -> 0, step: 1
1985 22:55:35.174080
1986 22:55:35.178206 RX Delay -79 -> 252, step: 8
1987 22:55:35.184206 iDelay=209, Bit 0, Center 92 (-7 ~ 192) 200
1988 22:55:35.187265 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
1989 22:55:35.190715 iDelay=209, Bit 2, Center 76 (-23 ~ 176) 200
1990 22:55:35.193996 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
1991 22:55:35.197034 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1992 22:55:35.204230 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
1993 22:55:35.207647 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
1994 22:55:35.211083 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
1995 22:55:35.214014 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1996 22:55:35.217376 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
1997 22:55:35.223805 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
1998 22:55:35.227168 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
1999 22:55:35.230319 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2000 22:55:35.233731 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2001 22:55:35.237175 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2002 22:55:35.243990 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
2003 22:55:35.244097 ==
2004 22:55:35.247480 Dram Type= 6, Freq= 0, CH_1, rank 1
2005 22:55:35.250737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2006 22:55:35.250829 ==
2007 22:55:35.250898 DQS Delay:
2008 22:55:35.254035 DQS0 = 0, DQS1 = 0
2009 22:55:35.254123 DQM Delay:
2010 22:55:35.257128 DQM0 = 89, DQM1 = 84
2011 22:55:35.257213 DQ Delay:
2012 22:55:35.260426 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =88
2013 22:55:35.263860 DQ4 =92, DQ5 =100, DQ6 =96, DQ7 =88
2014 22:55:35.266976 DQ8 =68, DQ9 =76, DQ10 =88, DQ11 =80
2015 22:55:35.270407 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =92
2016 22:55:35.270498
2017 22:55:35.270565
2018 22:55:35.280479 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c11, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2019 22:55:35.280601 CH1 RK1: MR19=606, MR18=3C11
2020 22:55:35.287061 CH1_RK1: MR19=0x606, MR18=0x3C11, DQSOSC=394, MR23=63, INC=95, DEC=63
2021 22:55:35.290309 [RxdqsGatingPostProcess] freq 800
2022 22:55:35.296966 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2023 22:55:35.300687 Pre-setting of DQS Precalculation
2024 22:55:35.303515 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2025 22:55:35.310135 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2026 22:55:35.317277 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2027 22:55:35.320437
2028 22:55:35.320540
2029 22:55:35.320608 [Calibration Summary] 1600 Mbps
2030 22:55:35.323804 CH 0, Rank 0
2031 22:55:35.323889 SW Impedance : PASS
2032 22:55:35.326961 DUTY Scan : NO K
2033 22:55:35.330463 ZQ Calibration : PASS
2034 22:55:35.330551 Jitter Meter : NO K
2035 22:55:35.333966 CBT Training : PASS
2036 22:55:35.337112 Write leveling : PASS
2037 22:55:35.337200 RX DQS gating : PASS
2038 22:55:35.340475 RX DQ/DQS(RDDQC) : PASS
2039 22:55:35.344092 TX DQ/DQS : PASS
2040 22:55:35.344181 RX DATLAT : PASS
2041 22:55:35.346914 RX DQ/DQS(Engine): PASS
2042 22:55:35.350258 TX OE : NO K
2043 22:55:35.350345 All Pass.
2044 22:55:35.350412
2045 22:55:35.350473 CH 0, Rank 1
2046 22:55:35.353500 SW Impedance : PASS
2047 22:55:35.356704 DUTY Scan : NO K
2048 22:55:35.356837 ZQ Calibration : PASS
2049 22:55:35.360061 Jitter Meter : NO K
2050 22:55:35.364010 CBT Training : PASS
2051 22:55:35.364097 Write leveling : PASS
2052 22:55:35.366868 RX DQS gating : PASS
2053 22:55:35.366954 RX DQ/DQS(RDDQC) : PASS
2054 22:55:35.370428 TX DQ/DQS : PASS
2055 22:55:35.373586 RX DATLAT : PASS
2056 22:55:35.373672 RX DQ/DQS(Engine): PASS
2057 22:55:35.376753 TX OE : NO K
2058 22:55:35.376890 All Pass.
2059 22:55:35.376956
2060 22:55:35.380505 CH 1, Rank 0
2061 22:55:35.380590 SW Impedance : PASS
2062 22:55:35.383604 DUTY Scan : NO K
2063 22:55:35.387271 ZQ Calibration : PASS
2064 22:55:35.387360 Jitter Meter : NO K
2065 22:55:35.390696 CBT Training : PASS
2066 22:55:35.393514 Write leveling : PASS
2067 22:55:35.393601 RX DQS gating : PASS
2068 22:55:35.396991 RX DQ/DQS(RDDQC) : PASS
2069 22:55:35.400261 TX DQ/DQS : PASS
2070 22:55:35.400349 RX DATLAT : PASS
2071 22:55:35.403604 RX DQ/DQS(Engine): PASS
2072 22:55:35.403688 TX OE : NO K
2073 22:55:35.407067 All Pass.
2074 22:55:35.407152
2075 22:55:35.407218 CH 1, Rank 1
2076 22:55:35.410359 SW Impedance : PASS
2077 22:55:35.410503 DUTY Scan : NO K
2078 22:55:35.413473 ZQ Calibration : PASS
2079 22:55:35.417338 Jitter Meter : NO K
2080 22:55:35.417426 CBT Training : PASS
2081 22:55:35.420256 Write leveling : PASS
2082 22:55:35.423802 RX DQS gating : PASS
2083 22:55:35.423892 RX DQ/DQS(RDDQC) : PASS
2084 22:55:35.427017 TX DQ/DQS : PASS
2085 22:55:35.430090 RX DATLAT : PASS
2086 22:55:35.430177 RX DQ/DQS(Engine): PASS
2087 22:55:35.433444 TX OE : NO K
2088 22:55:35.433528 All Pass.
2089 22:55:35.433595
2090 22:55:35.436734 DramC Write-DBI off
2091 22:55:35.440675 PER_BANK_REFRESH: Hybrid Mode
2092 22:55:35.440782 TX_TRACKING: ON
2093 22:55:35.443475 [GetDramInforAfterCalByMRR] Vendor 6.
2094 22:55:35.447087 [GetDramInforAfterCalByMRR] Revision 606.
2095 22:55:35.450782 [GetDramInforAfterCalByMRR] Revision 2 0.
2096 22:55:35.453399 MR0 0x3b3b
2097 22:55:35.453485 MR8 0x5151
2098 22:55:35.456725 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2099 22:55:35.456837
2100 22:55:35.456904 MR0 0x3b3b
2101 22:55:35.460582 MR8 0x5151
2102 22:55:35.463623 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2103 22:55:35.463708
2104 22:55:35.473863 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2105 22:55:35.476895 [FAST_K] Save calibration result to emmc
2106 22:55:35.480415 [FAST_K] Save calibration result to emmc
2107 22:55:35.480503 dram_init: config_dvfs: 1
2108 22:55:35.486865 dramc_set_vcore_voltage set vcore to 662500
2109 22:55:35.486964 Read voltage for 1200, 2
2110 22:55:35.490826 Vio18 = 0
2111 22:55:35.490915 Vcore = 662500
2112 22:55:35.490983 Vdram = 0
2113 22:55:35.493657 Vddq = 0
2114 22:55:35.493743 Vmddr = 0
2115 22:55:35.497345 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2116 22:55:35.503868 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2117 22:55:35.506506 MEM_TYPE=3, freq_sel=15
2118 22:55:35.510106 sv_algorithm_assistance_LP4_1600
2119 22:55:35.513397 ============ PULL DRAM RESETB DOWN ============
2120 22:55:35.517080 ========== PULL DRAM RESETB DOWN end =========
2121 22:55:35.519971 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2122 22:55:35.523511 ===================================
2123 22:55:35.526544 LPDDR4 DRAM CONFIGURATION
2124 22:55:35.529919 ===================================
2125 22:55:35.533220 EX_ROW_EN[0] = 0x0
2126 22:55:35.533308 EX_ROW_EN[1] = 0x0
2127 22:55:35.536684 LP4Y_EN = 0x0
2128 22:55:35.536775 WORK_FSP = 0x0
2129 22:55:35.540357 WL = 0x4
2130 22:55:35.540443 RL = 0x4
2131 22:55:35.543104 BL = 0x2
2132 22:55:35.543190 RPST = 0x0
2133 22:55:35.546810 RD_PRE = 0x0
2134 22:55:35.546895 WR_PRE = 0x1
2135 22:55:35.549596 WR_PST = 0x0
2136 22:55:35.549681 DBI_WR = 0x0
2137 22:55:35.553025 DBI_RD = 0x0
2138 22:55:35.557182 OTF = 0x1
2139 22:55:35.559715 ===================================
2140 22:55:35.559808 ===================================
2141 22:55:35.563052 ANA top config
2142 22:55:35.566807 ===================================
2143 22:55:35.570342 DLL_ASYNC_EN = 0
2144 22:55:35.570431 ALL_SLAVE_EN = 0
2145 22:55:35.573043 NEW_RANK_MODE = 1
2146 22:55:35.576553 DLL_IDLE_MODE = 1
2147 22:55:35.580375 LP45_APHY_COMB_EN = 1
2148 22:55:35.583103 TX_ODT_DIS = 1
2149 22:55:35.583216 NEW_8X_MODE = 1
2150 22:55:35.586659 ===================================
2151 22:55:35.589757 ===================================
2152 22:55:35.593733 data_rate = 2400
2153 22:55:35.596673 CKR = 1
2154 22:55:35.599544 DQ_P2S_RATIO = 8
2155 22:55:35.603140 ===================================
2156 22:55:35.606494 CA_P2S_RATIO = 8
2157 22:55:35.609573 DQ_CA_OPEN = 0
2158 22:55:35.609661 DQ_SEMI_OPEN = 0
2159 22:55:35.613188 CA_SEMI_OPEN = 0
2160 22:55:35.616415 CA_FULL_RATE = 0
2161 22:55:35.619902 DQ_CKDIV4_EN = 0
2162 22:55:35.623718 CA_CKDIV4_EN = 0
2163 22:55:35.623813 CA_PREDIV_EN = 0
2164 22:55:35.626528 PH8_DLY = 17
2165 22:55:35.629543 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2166 22:55:35.632991 DQ_AAMCK_DIV = 4
2167 22:55:35.636085 CA_AAMCK_DIV = 4
2168 22:55:35.639708 CA_ADMCK_DIV = 4
2169 22:55:35.642810 DQ_TRACK_CA_EN = 0
2170 22:55:35.642896 CA_PICK = 1200
2171 22:55:35.646120 CA_MCKIO = 1200
2172 22:55:35.649707 MCKIO_SEMI = 0
2173 22:55:35.652604 PLL_FREQ = 2366
2174 22:55:35.655959 DQ_UI_PI_RATIO = 32
2175 22:55:35.659664 CA_UI_PI_RATIO = 0
2176 22:55:35.662899 ===================================
2177 22:55:35.666098 ===================================
2178 22:55:35.666186 memory_type:LPDDR4
2179 22:55:35.669261 GP_NUM : 10
2180 22:55:35.673831 SRAM_EN : 1
2181 22:55:35.673921 MD32_EN : 0
2182 22:55:35.676130 ===================================
2183 22:55:35.679263 [ANA_INIT] >>>>>>>>>>>>>>
2184 22:55:35.682890 <<<<<< [CONFIGURE PHASE]: ANA_TX
2185 22:55:35.686290 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2186 22:55:35.689169 ===================================
2187 22:55:35.692722 data_rate = 2400,PCW = 0X5b00
2188 22:55:35.695846 ===================================
2189 22:55:35.698961 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2190 22:55:35.702881 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2191 22:55:35.709371 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2192 22:55:35.712483 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2193 22:55:35.716051 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2194 22:55:35.722487 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2195 22:55:35.722606 [ANA_INIT] flow start
2196 22:55:35.725719 [ANA_INIT] PLL >>>>>>>>
2197 22:55:35.729063 [ANA_INIT] PLL <<<<<<<<
2198 22:55:35.729154 [ANA_INIT] MIDPI >>>>>>>>
2199 22:55:35.732359 [ANA_INIT] MIDPI <<<<<<<<
2200 22:55:35.735750 [ANA_INIT] DLL >>>>>>>>
2201 22:55:35.735839 [ANA_INIT] DLL <<<<<<<<
2202 22:55:35.738890 [ANA_INIT] flow end
2203 22:55:35.742566 ============ LP4 DIFF to SE enter ============
2204 22:55:35.746032 ============ LP4 DIFF to SE exit ============
2205 22:55:35.748944 [ANA_INIT] <<<<<<<<<<<<<
2206 22:55:35.752317 [Flow] Enable top DCM control >>>>>
2207 22:55:35.756165 [Flow] Enable top DCM control <<<<<
2208 22:55:35.759069 Enable DLL master slave shuffle
2209 22:55:35.765746 ==============================================================
2210 22:55:35.765851 Gating Mode config
2211 22:55:35.772248 ==============================================================
2212 22:55:35.772351 Config description:
2213 22:55:35.782159 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2214 22:55:35.788786 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2215 22:55:35.795977 SELPH_MODE 0: By rank 1: By Phase
2216 22:55:35.798909 ==============================================================
2217 22:55:35.802296 GAT_TRACK_EN = 1
2218 22:55:35.805564 RX_GATING_MODE = 2
2219 22:55:35.808983 RX_GATING_TRACK_MODE = 2
2220 22:55:35.812434 SELPH_MODE = 1
2221 22:55:35.815700 PICG_EARLY_EN = 1
2222 22:55:35.818731 VALID_LAT_VALUE = 1
2223 22:55:35.825348 ==============================================================
2224 22:55:35.829204 Enter into Gating configuration >>>>
2225 22:55:35.832488 Exit from Gating configuration <<<<
2226 22:55:35.832582 Enter into DVFS_PRE_config >>>>>
2227 22:55:35.845806 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2228 22:55:35.849834 Exit from DVFS_PRE_config <<<<<
2229 22:55:35.852280 Enter into PICG configuration >>>>
2230 22:55:35.855604 Exit from PICG configuration <<<<
2231 22:55:35.855692 [RX_INPUT] configuration >>>>>
2232 22:55:35.858672 [RX_INPUT] configuration <<<<<
2233 22:55:35.865335 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2234 22:55:35.868396 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2235 22:55:35.875063 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2236 22:55:35.881740 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2237 22:55:35.888457 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2238 22:55:35.895102 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2239 22:55:35.898489 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2240 22:55:35.901952 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2241 22:55:35.908657 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2242 22:55:35.911730 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2243 22:55:35.915001 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2244 22:55:35.918465 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2245 22:55:35.922018 ===================================
2246 22:55:35.925075 LPDDR4 DRAM CONFIGURATION
2247 22:55:35.928388 ===================================
2248 22:55:35.931675 EX_ROW_EN[0] = 0x0
2249 22:55:35.931766 EX_ROW_EN[1] = 0x0
2250 22:55:35.934911 LP4Y_EN = 0x0
2251 22:55:35.934998 WORK_FSP = 0x0
2252 22:55:35.938106 WL = 0x4
2253 22:55:35.938194 RL = 0x4
2254 22:55:35.941602 BL = 0x2
2255 22:55:35.941690 RPST = 0x0
2256 22:55:35.944812 RD_PRE = 0x0
2257 22:55:35.944898 WR_PRE = 0x1
2258 22:55:35.948411 WR_PST = 0x0
2259 22:55:35.948497 DBI_WR = 0x0
2260 22:55:35.951405 DBI_RD = 0x0
2261 22:55:35.955085 OTF = 0x1
2262 22:55:35.958350 ===================================
2263 22:55:35.961999 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2264 22:55:35.964900 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2265 22:55:35.968111 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2266 22:55:35.971241 ===================================
2267 22:55:35.975127 LPDDR4 DRAM CONFIGURATION
2268 22:55:35.978085 ===================================
2269 22:55:35.981299 EX_ROW_EN[0] = 0x10
2270 22:55:35.981387 EX_ROW_EN[1] = 0x0
2271 22:55:35.984524 LP4Y_EN = 0x0
2272 22:55:35.984626 WORK_FSP = 0x0
2273 22:55:35.987898 WL = 0x4
2274 22:55:35.987999 RL = 0x4
2275 22:55:35.991230 BL = 0x2
2276 22:55:35.991384 RPST = 0x0
2277 22:55:35.994644 RD_PRE = 0x0
2278 22:55:35.994731 WR_PRE = 0x1
2279 22:55:35.998030 WR_PST = 0x0
2280 22:55:35.998115 DBI_WR = 0x0
2281 22:55:36.001378 DBI_RD = 0x0
2282 22:55:36.001465 OTF = 0x1
2283 22:55:36.004620 ===================================
2284 22:55:36.011571 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2285 22:55:36.011678 ==
2286 22:55:36.014375 Dram Type= 6, Freq= 0, CH_0, rank 0
2287 22:55:36.020978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2288 22:55:36.021103 ==
2289 22:55:36.021195 [Duty_Offset_Calibration]
2290 22:55:36.024966 B0:2 B1:0 CA:1
2291 22:55:36.025055
2292 22:55:36.027685 [DutyScan_Calibration_Flow] k_type=0
2293 22:55:36.035944
2294 22:55:36.036067 ==CLK 0==
2295 22:55:36.039197 Final CLK duty delay cell = -4
2296 22:55:36.042819 [-4] MAX Duty = 5031%(X100), DQS PI = 26
2297 22:55:36.046348 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2298 22:55:36.049185 [-4] AVG Duty = 4953%(X100)
2299 22:55:36.049329
2300 22:55:36.052458 CH0 CLK Duty spec in!! Max-Min= 156%
2301 22:55:36.055853 [DutyScan_Calibration_Flow] ====Done====
2302 22:55:36.055941
2303 22:55:36.059025 [DutyScan_Calibration_Flow] k_type=1
2304 22:55:36.074825
2305 22:55:36.074974 ==DQS 0 ==
2306 22:55:36.078177 Final DQS duty delay cell = 0
2307 22:55:36.081452 [0] MAX Duty = 5187%(X100), DQS PI = 30
2308 22:55:36.085721 [0] MIN Duty = 4938%(X100), DQS PI = 0
2309 22:55:36.085816 [0] AVG Duty = 5062%(X100)
2310 22:55:36.088175
2311 22:55:36.088258 ==DQS 1 ==
2312 22:55:36.091663 Final DQS duty delay cell = -4
2313 22:55:36.094868 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2314 22:55:36.098339 [-4] MIN Duty = 4938%(X100), DQS PI = 6
2315 22:55:36.102202 [-4] AVG Duty = 5031%(X100)
2316 22:55:36.102293
2317 22:55:36.104538 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2318 22:55:36.104622
2319 22:55:36.107957 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2320 22:55:36.111199 [DutyScan_Calibration_Flow] ====Done====
2321 22:55:36.111283
2322 22:55:36.114492 [DutyScan_Calibration_Flow] k_type=3
2323 22:55:36.130939
2324 22:55:36.131093 ==DQM 0 ==
2325 22:55:36.134272 Final DQM duty delay cell = 0
2326 22:55:36.137110 [0] MAX Duty = 5062%(X100), DQS PI = 24
2327 22:55:36.140963 [0] MIN Duty = 4813%(X100), DQS PI = 2
2328 22:55:36.143997 [0] AVG Duty = 4937%(X100)
2329 22:55:36.144084
2330 22:55:36.144148 ==DQM 1 ==
2331 22:55:36.147187 Final DQM duty delay cell = -4
2332 22:55:36.150783 [-4] MAX Duty = 5000%(X100), DQS PI = 32
2333 22:55:36.153673 [-4] MIN Duty = 4813%(X100), DQS PI = 10
2334 22:55:36.157065 [-4] AVG Duty = 4906%(X100)
2335 22:55:36.157199
2336 22:55:36.160692 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2337 22:55:36.160848
2338 22:55:36.163830 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2339 22:55:36.167052 [DutyScan_Calibration_Flow] ====Done====
2340 22:55:36.167166
2341 22:55:36.170505 [DutyScan_Calibration_Flow] k_type=2
2342 22:55:36.186762
2343 22:55:36.186922 ==DQ 0 ==
2344 22:55:36.190611 Final DQ duty delay cell = -4
2345 22:55:36.193665 [-4] MAX Duty = 5031%(X100), DQS PI = 32
2346 22:55:36.196671 [-4] MIN Duty = 4875%(X100), DQS PI = 16
2347 22:55:36.199799 [-4] AVG Duty = 4953%(X100)
2348 22:55:36.199917
2349 22:55:36.199985 ==DQ 1 ==
2350 22:55:36.203306 Final DQ duty delay cell = 0
2351 22:55:36.206233 [0] MAX Duty = 4938%(X100), DQS PI = 4
2352 22:55:36.210215 [0] MIN Duty = 4907%(X100), DQS PI = 0
2353 22:55:36.213129 [0] AVG Duty = 4922%(X100)
2354 22:55:36.213211
2355 22:55:36.216994 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2356 22:55:36.217110
2357 22:55:36.220051 CH0 DQ 1 Duty spec in!! Max-Min= 31%
2358 22:55:36.223224 [DutyScan_Calibration_Flow] ====Done====
2359 22:55:36.223326 ==
2360 22:55:36.226403 Dram Type= 6, Freq= 0, CH_1, rank 0
2361 22:55:36.229898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2362 22:55:36.229993 ==
2363 22:55:36.232956 [Duty_Offset_Calibration]
2364 22:55:36.233042 B0:0 B1:-1 CA:2
2365 22:55:36.233109
2366 22:55:36.236772 [DutyScan_Calibration_Flow] k_type=0
2367 22:55:36.247128
2368 22:55:36.247267 ==CLK 0==
2369 22:55:36.250372 Final CLK duty delay cell = 0
2370 22:55:36.253669 [0] MAX Duty = 5156%(X100), DQS PI = 16
2371 22:55:36.256972 [0] MIN Duty = 4938%(X100), DQS PI = 46
2372 22:55:36.260063 [0] AVG Duty = 5047%(X100)
2373 22:55:36.260198
2374 22:55:36.263717 CH1 CLK Duty spec in!! Max-Min= 218%
2375 22:55:36.266928 [DutyScan_Calibration_Flow] ====Done====
2376 22:55:36.267047
2377 22:55:36.270160 [DutyScan_Calibration_Flow] k_type=1
2378 22:55:36.286478
2379 22:55:36.286694 ==DQS 0 ==
2380 22:55:36.289756 Final DQS duty delay cell = 0
2381 22:55:36.292929 [0] MAX Duty = 5093%(X100), DQS PI = 24
2382 22:55:36.296491 [0] MIN Duty = 4969%(X100), DQS PI = 0
2383 22:55:36.299377 [0] AVG Duty = 5031%(X100)
2384 22:55:36.299468
2385 22:55:36.299535 ==DQS 1 ==
2386 22:55:36.302992 Final DQS duty delay cell = 0
2387 22:55:36.306268 [0] MAX Duty = 5156%(X100), DQS PI = 0
2388 22:55:36.309960 [0] MIN Duty = 4875%(X100), DQS PI = 34
2389 22:55:36.310057 [0] AVG Duty = 5015%(X100)
2390 22:55:36.313037
2391 22:55:36.315966 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2392 22:55:36.316054
2393 22:55:36.319938 CH1 DQS 1 Duty spec in!! Max-Min= 281%
2394 22:55:36.322896 [DutyScan_Calibration_Flow] ====Done====
2395 22:55:36.322996
2396 22:55:36.326080 [DutyScan_Calibration_Flow] k_type=3
2397 22:55:36.342782
2398 22:55:36.342942 ==DQM 0 ==
2399 22:55:36.346094 Final DQM duty delay cell = 4
2400 22:55:36.349586 [4] MAX Duty = 5093%(X100), DQS PI = 22
2401 22:55:36.353009 [4] MIN Duty = 4969%(X100), DQS PI = 28
2402 22:55:36.355991 [4] AVG Duty = 5031%(X100)
2403 22:55:36.356092
2404 22:55:36.356159 ==DQM 1 ==
2405 22:55:36.359309 Final DQM duty delay cell = -4
2406 22:55:36.362671 [-4] MAX Duty = 5031%(X100), DQS PI = 62
2407 22:55:36.366252 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2408 22:55:36.369708 [-4] AVG Duty = 4891%(X100)
2409 22:55:36.369803
2410 22:55:36.373001 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2411 22:55:36.373090
2412 22:55:36.376099 CH1 DQM 1 Duty spec in!! Max-Min= 280%
2413 22:55:36.379194 [DutyScan_Calibration_Flow] ====Done====
2414 22:55:36.379279
2415 22:55:36.382578 [DutyScan_Calibration_Flow] k_type=2
2416 22:55:36.399588
2417 22:55:36.399713 ==DQ 0 ==
2418 22:55:36.403218 Final DQ duty delay cell = 0
2419 22:55:36.406250 [0] MAX Duty = 5062%(X100), DQS PI = 18
2420 22:55:36.409897 [0] MIN Duty = 4938%(X100), DQS PI = 30
2421 22:55:36.410007 [0] AVG Duty = 5000%(X100)
2422 22:55:36.412915
2423 22:55:36.412999 ==DQ 1 ==
2424 22:55:36.416732 Final DQ duty delay cell = 0
2425 22:55:36.419539 [0] MAX Duty = 5031%(X100), DQS PI = 0
2426 22:55:36.422951 [0] MIN Duty = 4813%(X100), DQS PI = 34
2427 22:55:36.423108 [0] AVG Duty = 4922%(X100)
2428 22:55:36.423204
2429 22:55:36.426145 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2430 22:55:36.429598
2431 22:55:36.432827 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2432 22:55:36.436169 [DutyScan_Calibration_Flow] ====Done====
2433 22:55:36.439404 nWR fixed to 30
2434 22:55:36.439492 [ModeRegInit_LP4] CH0 RK0
2435 22:55:36.442829 [ModeRegInit_LP4] CH0 RK1
2436 22:55:36.446777 [ModeRegInit_LP4] CH1 RK0
2437 22:55:36.449621 [ModeRegInit_LP4] CH1 RK1
2438 22:55:36.449705 match AC timing 7
2439 22:55:36.452660 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2440 22:55:36.459332 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2441 22:55:36.462538 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2442 22:55:36.469197 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2443 22:55:36.472749 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2444 22:55:36.472849 ==
2445 22:55:36.475875 Dram Type= 6, Freq= 0, CH_0, rank 0
2446 22:55:36.479391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2447 22:55:36.479478 ==
2448 22:55:36.486111 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2449 22:55:36.492294 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2450 22:55:36.499400 [CA 0] Center 38 (7~69) winsize 63
2451 22:55:36.503007 [CA 1] Center 38 (7~69) winsize 63
2452 22:55:36.506930 [CA 2] Center 34 (4~65) winsize 62
2453 22:55:36.509609 [CA 3] Center 34 (4~65) winsize 62
2454 22:55:36.512749 [CA 4] Center 33 (3~64) winsize 62
2455 22:55:36.516776 [CA 5] Center 32 (2~63) winsize 62
2456 22:55:36.516857
2457 22:55:36.519521 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2458 22:55:36.519629
2459 22:55:36.523047 [CATrainingPosCal] consider 1 rank data
2460 22:55:36.525970 u2DelayCellTimex100 = 270/100 ps
2461 22:55:36.529463 CA0 delay=38 (7~69),Diff = 6 PI (28 cell)
2462 22:55:36.532881 CA1 delay=38 (7~69),Diff = 6 PI (28 cell)
2463 22:55:36.539466 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2464 22:55:36.543261 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2465 22:55:36.545965 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2466 22:55:36.549489 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2467 22:55:36.549565
2468 22:55:36.553199 CA PerBit enable=1, Macro0, CA PI delay=32
2469 22:55:36.553274
2470 22:55:36.556209 [CBTSetCACLKResult] CA Dly = 32
2471 22:55:36.556291 CS Dly: 6 (0~37)
2472 22:55:36.556362 ==
2473 22:55:36.559560 Dram Type= 6, Freq= 0, CH_0, rank 1
2474 22:55:36.566413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2475 22:55:36.566521 ==
2476 22:55:36.569299 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2477 22:55:36.575806 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2478 22:55:36.585151 [CA 0] Center 38 (7~69) winsize 63
2479 22:55:36.588717 [CA 1] Center 38 (7~69) winsize 63
2480 22:55:36.592194 [CA 2] Center 35 (5~66) winsize 62
2481 22:55:36.594948 [CA 3] Center 35 (5~66) winsize 62
2482 22:55:36.598261 [CA 4] Center 33 (3~64) winsize 62
2483 22:55:36.601481 [CA 5] Center 33 (3~64) winsize 62
2484 22:55:36.601593
2485 22:55:36.604988 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2486 22:55:36.605114
2487 22:55:36.608961 [CATrainingPosCal] consider 2 rank data
2488 22:55:36.611999 u2DelayCellTimex100 = 270/100 ps
2489 22:55:36.615419 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2490 22:55:36.618412 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2491 22:55:36.625233 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
2492 22:55:36.628446 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2493 22:55:36.631746 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2494 22:55:36.635123 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2495 22:55:36.635232
2496 22:55:36.638410 CA PerBit enable=1, Macro0, CA PI delay=33
2497 22:55:36.638527
2498 22:55:36.641449 [CBTSetCACLKResult] CA Dly = 33
2499 22:55:36.641578 CS Dly: 7 (0~39)
2500 22:55:36.641678
2501 22:55:36.644726 ----->DramcWriteLeveling(PI) begin...
2502 22:55:36.648326 ==
2503 22:55:36.651791 Dram Type= 6, Freq= 0, CH_0, rank 0
2504 22:55:36.654781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2505 22:55:36.654902 ==
2506 22:55:36.658309 Write leveling (Byte 0): 33 => 33
2507 22:55:36.661511 Write leveling (Byte 1): 30 => 30
2508 22:55:36.665212 DramcWriteLeveling(PI) end<-----
2509 22:55:36.665347
2510 22:55:36.665488 ==
2511 22:55:36.667969 Dram Type= 6, Freq= 0, CH_0, rank 0
2512 22:55:36.671256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2513 22:55:36.671362 ==
2514 22:55:36.674954 [Gating] SW mode calibration
2515 22:55:36.681418 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2516 22:55:36.687715 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2517 22:55:36.691499 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2518 22:55:36.694762 0 15 4 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
2519 22:55:36.701288 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2520 22:55:36.704644 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 22:55:36.707949 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 22:55:36.714628 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2523 22:55:36.718154 0 15 24 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
2524 22:55:36.721082 0 15 28 | B1->B0 | 3434 2323 | 0 0 | (0 1) (1 0)
2525 22:55:36.725041 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
2526 22:55:36.731042 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2527 22:55:36.734448 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 22:55:36.737718 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 22:55:36.745231 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 22:55:36.748005 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 22:55:36.751007 1 0 24 | B1->B0 | 2323 3130 | 0 1 | (0 0) (0 0)
2532 22:55:36.757994 1 0 28 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2533 22:55:36.761053 1 1 0 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
2534 22:55:36.764655 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2535 22:55:36.771060 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 22:55:36.774280 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 22:55:36.777790 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 22:55:36.784249 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 22:55:36.787665 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 22:55:36.790784 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2541 22:55:36.797903 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2542 22:55:36.801070 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 22:55:36.804644 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 22:55:36.810780 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 22:55:36.814182 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 22:55:36.817729 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 22:55:36.824092 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 22:55:36.827700 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 22:55:36.831208 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 22:55:36.837687 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 22:55:36.840901 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 22:55:36.843951 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 22:55:36.850533 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 22:55:36.853930 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 22:55:36.857413 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2556 22:55:36.860709 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2557 22:55:36.867229 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2558 22:55:36.870735 Total UI for P1: 0, mck2ui 16
2559 22:55:36.874614 best dqsien dly found for B0: ( 1, 3, 26)
2560 22:55:36.877163 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 22:55:36.880587 Total UI for P1: 0, mck2ui 16
2562 22:55:36.884176 best dqsien dly found for B1: ( 1, 4, 0)
2563 22:55:36.887240 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2564 22:55:36.891073 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2565 22:55:36.891183
2566 22:55:36.893610 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2567 22:55:36.897204 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2568 22:55:36.900631 [Gating] SW calibration Done
2569 22:55:36.900738 ==
2570 22:55:36.903531 Dram Type= 6, Freq= 0, CH_0, rank 0
2571 22:55:36.910328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2572 22:55:36.910436 ==
2573 22:55:36.910531 RX Vref Scan: 0
2574 22:55:36.910624
2575 22:55:36.913564 RX Vref 0 -> 0, step: 1
2576 22:55:36.913662
2577 22:55:36.916800 RX Delay -40 -> 252, step: 8
2578 22:55:36.920521 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2579 22:55:36.923708 iDelay=208, Bit 1, Center 123 (56 ~ 191) 136
2580 22:55:36.927169 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2581 22:55:36.930083 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2582 22:55:36.936934 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2583 22:55:36.940249 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2584 22:55:36.943917 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2585 22:55:36.946870 iDelay=208, Bit 7, Center 131 (56 ~ 207) 152
2586 22:55:36.950424 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2587 22:55:36.957257 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2588 22:55:36.960392 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2589 22:55:36.963939 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2590 22:55:36.966914 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2591 22:55:36.970010 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2592 22:55:36.976995 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2593 22:55:36.980378 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2594 22:55:36.980503 ==
2595 22:55:36.983871 Dram Type= 6, Freq= 0, CH_0, rank 0
2596 22:55:36.986838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2597 22:55:36.986940 ==
2598 22:55:36.990691 DQS Delay:
2599 22:55:36.990792 DQS0 = 0, DQS1 = 0
2600 22:55:36.990882 DQM Delay:
2601 22:55:36.993593 DQM0 = 123, DQM1 = 110
2602 22:55:36.993693 DQ Delay:
2603 22:55:36.996608 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2604 22:55:36.999889 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =131
2605 22:55:37.003157 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2606 22:55:37.009971 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2607 22:55:37.010074
2608 22:55:37.010147
2609 22:55:37.010236 ==
2610 22:55:37.013958 Dram Type= 6, Freq= 0, CH_0, rank 0
2611 22:55:37.016976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2612 22:55:37.017057 ==
2613 22:55:37.017122
2614 22:55:37.017216
2615 22:55:37.020105 TX Vref Scan disable
2616 22:55:37.020203 == TX Byte 0 ==
2617 22:55:37.027184 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2618 22:55:37.030037 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2619 22:55:37.030147 == TX Byte 1 ==
2620 22:55:37.036712 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2621 22:55:37.040566 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2622 22:55:37.040672 ==
2623 22:55:37.043406 Dram Type= 6, Freq= 0, CH_0, rank 0
2624 22:55:37.046897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2625 22:55:37.046998 ==
2626 22:55:37.059463 TX Vref=22, minBit 0, minWin=23, winSum=396
2627 22:55:37.062523 TX Vref=24, minBit 3, minWin=24, winSum=402
2628 22:55:37.065892 TX Vref=26, minBit 0, minWin=24, winSum=407
2629 22:55:37.069123 TX Vref=28, minBit 0, minWin=25, winSum=412
2630 22:55:37.072738 TX Vref=30, minBit 0, minWin=25, winSum=417
2631 22:55:37.079299 TX Vref=32, minBit 1, minWin=25, winSum=414
2632 22:55:37.082462 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 30
2633 22:55:37.082563
2634 22:55:37.086146 Final TX Range 1 Vref 30
2635 22:55:37.086250
2636 22:55:37.086342 ==
2637 22:55:37.089214 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 22:55:37.092567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 22:55:37.092668 ==
2640 22:55:37.095617
2641 22:55:37.095732
2642 22:55:37.095823 TX Vref Scan disable
2643 22:55:37.099656 == TX Byte 0 ==
2644 22:55:37.102511 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2645 22:55:37.105818 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2646 22:55:37.108982 == TX Byte 1 ==
2647 22:55:37.112264 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2648 22:55:37.118769 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2649 22:55:37.118917
2650 22:55:37.119013 [DATLAT]
2651 22:55:37.119102 Freq=1200, CH0 RK0
2652 22:55:37.119189
2653 22:55:37.122597 DATLAT Default: 0xd
2654 22:55:37.122709 0, 0xFFFF, sum = 0
2655 22:55:37.125561 1, 0xFFFF, sum = 0
2656 22:55:37.125667 2, 0xFFFF, sum = 0
2657 22:55:37.129014 3, 0xFFFF, sum = 0
2658 22:55:37.132327 4, 0xFFFF, sum = 0
2659 22:55:37.132431 5, 0xFFFF, sum = 0
2660 22:55:37.135670 6, 0xFFFF, sum = 0
2661 22:55:37.135772 7, 0xFFFF, sum = 0
2662 22:55:37.139177 8, 0xFFFF, sum = 0
2663 22:55:37.139314 9, 0xFFFF, sum = 0
2664 22:55:37.142351 10, 0xFFFF, sum = 0
2665 22:55:37.142468 11, 0xFFFF, sum = 0
2666 22:55:37.145786 12, 0x0, sum = 1
2667 22:55:37.145889 13, 0x0, sum = 2
2668 22:55:37.149356 14, 0x0, sum = 3
2669 22:55:37.149456 15, 0x0, sum = 4
2670 22:55:37.149548 best_step = 13
2671 22:55:37.152274
2672 22:55:37.152372 ==
2673 22:55:37.155389 Dram Type= 6, Freq= 0, CH_0, rank 0
2674 22:55:37.159011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2675 22:55:37.159088 ==
2676 22:55:37.159158 RX Vref Scan: 1
2677 22:55:37.159247
2678 22:55:37.162260 Set Vref Range= 32 -> 127
2679 22:55:37.162359
2680 22:55:37.165491 RX Vref 32 -> 127, step: 1
2681 22:55:37.165590
2682 22:55:37.168768 RX Delay -13 -> 252, step: 4
2683 22:55:37.168875
2684 22:55:37.172162 Set Vref, RX VrefLevel [Byte0]: 32
2685 22:55:37.176471 [Byte1]: 32
2686 22:55:37.176566
2687 22:55:37.179042 Set Vref, RX VrefLevel [Byte0]: 33
2688 22:55:37.182015 [Byte1]: 33
2689 22:55:37.186301
2690 22:55:37.186400 Set Vref, RX VrefLevel [Byte0]: 34
2691 22:55:37.189130 [Byte1]: 34
2692 22:55:37.193346
2693 22:55:37.193433 Set Vref, RX VrefLevel [Byte0]: 35
2694 22:55:37.196984 [Byte1]: 35
2695 22:55:37.201249
2696 22:55:37.201350 Set Vref, RX VrefLevel [Byte0]: 36
2697 22:55:37.204620 [Byte1]: 36
2698 22:55:37.209069
2699 22:55:37.209174 Set Vref, RX VrefLevel [Byte0]: 37
2700 22:55:37.212551 [Byte1]: 37
2701 22:55:37.217041
2702 22:55:37.217124 Set Vref, RX VrefLevel [Byte0]: 38
2703 22:55:37.220609 [Byte1]: 38
2704 22:55:37.225005
2705 22:55:37.225090 Set Vref, RX VrefLevel [Byte0]: 39
2706 22:55:37.228254 [Byte1]: 39
2707 22:55:37.233055
2708 22:55:37.233166 Set Vref, RX VrefLevel [Byte0]: 40
2709 22:55:37.236377 [Byte1]: 40
2710 22:55:37.241114
2711 22:55:37.241198 Set Vref, RX VrefLevel [Byte0]: 41
2712 22:55:37.244162 [Byte1]: 41
2713 22:55:37.248657
2714 22:55:37.248741 Set Vref, RX VrefLevel [Byte0]: 42
2715 22:55:37.251996 [Byte1]: 42
2716 22:55:37.256891
2717 22:55:37.256978 Set Vref, RX VrefLevel [Byte0]: 43
2718 22:55:37.260143 [Byte1]: 43
2719 22:55:37.264398
2720 22:55:37.264482 Set Vref, RX VrefLevel [Byte0]: 44
2721 22:55:37.267969 [Byte1]: 44
2722 22:55:37.272340
2723 22:55:37.272424 Set Vref, RX VrefLevel [Byte0]: 45
2724 22:55:37.276354 [Byte1]: 45
2725 22:55:37.280373
2726 22:55:37.280457 Set Vref, RX VrefLevel [Byte0]: 46
2727 22:55:37.283726 [Byte1]: 46
2728 22:55:37.288067
2729 22:55:37.291265 Set Vref, RX VrefLevel [Byte0]: 47
2730 22:55:37.294676 [Byte1]: 47
2731 22:55:37.294761
2732 22:55:37.298509 Set Vref, RX VrefLevel [Byte0]: 48
2733 22:55:37.301327 [Byte1]: 48
2734 22:55:37.301412
2735 22:55:37.304481 Set Vref, RX VrefLevel [Byte0]: 49
2736 22:55:37.308246 [Byte1]: 49
2737 22:55:37.311649
2738 22:55:37.311733 Set Vref, RX VrefLevel [Byte0]: 50
2739 22:55:37.315053 [Byte1]: 50
2740 22:55:37.319636
2741 22:55:37.319721 Set Vref, RX VrefLevel [Byte0]: 51
2742 22:55:37.323951 [Byte1]: 51
2743 22:55:37.327892
2744 22:55:37.327978 Set Vref, RX VrefLevel [Byte0]: 52
2745 22:55:37.331183 [Byte1]: 52
2746 22:55:37.335464
2747 22:55:37.335549 Set Vref, RX VrefLevel [Byte0]: 53
2748 22:55:37.338875 [Byte1]: 53
2749 22:55:37.343626
2750 22:55:37.343712 Set Vref, RX VrefLevel [Byte0]: 54
2751 22:55:37.346885 [Byte1]: 54
2752 22:55:37.351580
2753 22:55:37.351665 Set Vref, RX VrefLevel [Byte0]: 55
2754 22:55:37.357515 [Byte1]: 55
2755 22:55:37.357600
2756 22:55:37.360985 Set Vref, RX VrefLevel [Byte0]: 56
2757 22:55:37.364137 [Byte1]: 56
2758 22:55:37.364221
2759 22:55:37.368321 Set Vref, RX VrefLevel [Byte0]: 57
2760 22:55:37.370880 [Byte1]: 57
2761 22:55:37.375505
2762 22:55:37.375589 Set Vref, RX VrefLevel [Byte0]: 58
2763 22:55:37.378374 [Byte1]: 58
2764 22:55:37.382815
2765 22:55:37.382897 Set Vref, RX VrefLevel [Byte0]: 59
2766 22:55:37.386068 [Byte1]: 59
2767 22:55:37.391237
2768 22:55:37.391320 Set Vref, RX VrefLevel [Byte0]: 60
2769 22:55:37.394200 [Byte1]: 60
2770 22:55:37.398861
2771 22:55:37.398944 Set Vref, RX VrefLevel [Byte0]: 61
2772 22:55:37.401980 [Byte1]: 61
2773 22:55:37.406584
2774 22:55:37.406666 Set Vref, RX VrefLevel [Byte0]: 62
2775 22:55:37.409651 [Byte1]: 62
2776 22:55:37.414562
2777 22:55:37.414646 Set Vref, RX VrefLevel [Byte0]: 63
2778 22:55:37.417579 [Byte1]: 63
2779 22:55:37.422366
2780 22:55:37.422449 Set Vref, RX VrefLevel [Byte0]: 64
2781 22:55:37.425605 [Byte1]: 64
2782 22:55:37.430078
2783 22:55:37.430183 Set Vref, RX VrefLevel [Byte0]: 65
2784 22:55:37.433482 [Byte1]: 65
2785 22:55:37.438641
2786 22:55:37.438724 Set Vref, RX VrefLevel [Byte0]: 66
2787 22:55:37.441504 [Byte1]: 66
2788 22:55:37.446516
2789 22:55:37.446600 Set Vref, RX VrefLevel [Byte0]: 67
2790 22:55:37.449253 [Byte1]: 67
2791 22:55:37.453792
2792 22:55:37.453875 Set Vref, RX VrefLevel [Byte0]: 68
2793 22:55:37.457484 [Byte1]: 68
2794 22:55:37.462197
2795 22:55:37.462280 Set Vref, RX VrefLevel [Byte0]: 69
2796 22:55:37.465021 [Byte1]: 69
2797 22:55:37.469676
2798 22:55:37.469759 Final RX Vref Byte 0 = 57 to rank0
2799 22:55:37.472907 Final RX Vref Byte 1 = 49 to rank0
2800 22:55:37.476362 Final RX Vref Byte 0 = 57 to rank1
2801 22:55:37.479932 Final RX Vref Byte 1 = 49 to rank1==
2802 22:55:37.483050 Dram Type= 6, Freq= 0, CH_0, rank 0
2803 22:55:37.489579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2804 22:55:37.489663 ==
2805 22:55:37.489731 DQS Delay:
2806 22:55:37.489794 DQS0 = 0, DQS1 = 0
2807 22:55:37.493835 DQM Delay:
2808 22:55:37.493917 DQM0 = 122, DQM1 = 109
2809 22:55:37.496108 DQ Delay:
2810 22:55:37.499703 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2811 22:55:37.503955 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2812 22:55:37.506307 DQ8 =102, DQ9 =94, DQ10 =110, DQ11 =106
2813 22:55:37.509619 DQ12 =114, DQ13 =110, DQ14 =122, DQ15 =116
2814 22:55:37.509733
2815 22:55:37.509799
2816 22:55:37.516464 [DQSOSCAuto] RK0, (LSB)MR18= 0xd0a, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
2817 22:55:37.519330 CH0 RK0: MR19=404, MR18=D0A
2818 22:55:37.526106 CH0_RK0: MR19=0x404, MR18=0xD0A, DQSOSC=405, MR23=63, INC=39, DEC=26
2819 22:55:37.526197
2820 22:55:37.529879 ----->DramcWriteLeveling(PI) begin...
2821 22:55:37.529966 ==
2822 22:55:37.532972 Dram Type= 6, Freq= 0, CH_0, rank 1
2823 22:55:37.536191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2824 22:55:37.539437 ==
2825 22:55:37.539521 Write leveling (Byte 0): 34 => 34
2826 22:55:37.542884 Write leveling (Byte 1): 28 => 28
2827 22:55:37.546080 DramcWriteLeveling(PI) end<-----
2828 22:55:37.546163
2829 22:55:37.546229 ==
2830 22:55:37.549432 Dram Type= 6, Freq= 0, CH_0, rank 1
2831 22:55:37.556186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2832 22:55:37.556274 ==
2833 22:55:37.556341 [Gating] SW mode calibration
2834 22:55:37.566011 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2835 22:55:37.569610 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2836 22:55:37.572798 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (1 0) (1 1)
2837 22:55:37.579693 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2838 22:55:37.582839 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2839 22:55:37.586022 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 22:55:37.592695 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 22:55:37.596074 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2842 22:55:37.599195 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2843 22:55:37.605796 0 15 28 | B1->B0 | 3434 3030 | 0 0 | (0 1) (1 0)
2844 22:55:37.609310 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2845 22:55:37.612684 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2846 22:55:37.619667 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 22:55:37.622532 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 22:55:37.625772 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 22:55:37.632509 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2850 22:55:37.635692 1 0 24 | B1->B0 | 2424 2929 | 0 0 | (0 0) (0 0)
2851 22:55:37.639354 1 0 28 | B1->B0 | 3c3c 4444 | 1 0 | (0 0) (0 0)
2852 22:55:37.645857 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2853 22:55:37.649002 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 22:55:37.652352 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 22:55:37.658994 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 22:55:37.662658 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 22:55:37.665649 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 22:55:37.672171 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2859 22:55:37.676036 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2860 22:55:37.678858 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 22:55:37.685706 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 22:55:37.689310 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 22:55:37.692581 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 22:55:37.698963 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 22:55:37.702303 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 22:55:37.705776 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 22:55:37.708859 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 22:55:37.715587 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 22:55:37.718592 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 22:55:37.721989 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 22:55:37.728754 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 22:55:37.732193 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 22:55:37.735422 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 22:55:37.742062 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 22:55:37.745761 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2876 22:55:37.748632 Total UI for P1: 0, mck2ui 16
2877 22:55:37.752099 best dqsien dly found for B0: ( 1, 3, 26)
2878 22:55:37.755592 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 22:55:37.758729 Total UI for P1: 0, mck2ui 16
2880 22:55:37.762033 best dqsien dly found for B1: ( 1, 3, 28)
2881 22:55:37.765121 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2882 22:55:37.768597 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2883 22:55:37.768683
2884 22:55:37.775018 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2885 22:55:37.778639 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2886 22:55:37.782250 [Gating] SW calibration Done
2887 22:55:37.782334 ==
2888 22:55:37.785255 Dram Type= 6, Freq= 0, CH_0, rank 1
2889 22:55:37.788545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2890 22:55:37.788630 ==
2891 22:55:37.788697 RX Vref Scan: 0
2892 22:55:37.788759
2893 22:55:37.791758 RX Vref 0 -> 0, step: 1
2894 22:55:37.791840
2895 22:55:37.794848 RX Delay -40 -> 252, step: 8
2896 22:55:37.798420 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2897 22:55:37.801759 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2898 22:55:37.808783 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2899 22:55:37.811489 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2900 22:55:37.815020 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2901 22:55:37.818311 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2902 22:55:37.821342 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2903 22:55:37.828267 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2904 22:55:37.831611 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2905 22:55:37.834832 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2906 22:55:37.838419 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2907 22:55:37.841410 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2908 22:55:37.848032 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2909 22:55:37.851386 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2910 22:55:37.854973 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2911 22:55:37.858141 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2912 22:55:37.858224 ==
2913 22:55:37.861836 Dram Type= 6, Freq= 0, CH_0, rank 1
2914 22:55:37.868244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2915 22:55:37.868331 ==
2916 22:55:37.868397 DQS Delay:
2917 22:55:37.868457 DQS0 = 0, DQS1 = 0
2918 22:55:37.871476 DQM Delay:
2919 22:55:37.871558 DQM0 = 120, DQM1 = 108
2920 22:55:37.874944 DQ Delay:
2921 22:55:37.878233 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2922 22:55:37.881465 DQ4 =123, DQ5 =115, DQ6 =127, DQ7 =127
2923 22:55:37.884691 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2924 22:55:37.888005 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2925 22:55:37.888109
2926 22:55:37.888204
2927 22:55:37.888295 ==
2928 22:55:37.891420 Dram Type= 6, Freq= 0, CH_0, rank 1
2929 22:55:37.894806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2930 22:55:37.894891 ==
2931 22:55:37.897794
2932 22:55:37.897876
2933 22:55:37.897943 TX Vref Scan disable
2934 22:55:37.901315 == TX Byte 0 ==
2935 22:55:37.904933 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2936 22:55:37.907803 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2937 22:55:37.911160 == TX Byte 1 ==
2938 22:55:37.914507 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2939 22:55:37.917980 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2940 22:55:37.918065 ==
2941 22:55:37.921381 Dram Type= 6, Freq= 0, CH_0, rank 1
2942 22:55:37.927506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2943 22:55:37.927595 ==
2944 22:55:37.939037 TX Vref=22, minBit 1, minWin=23, winSum=401
2945 22:55:37.942548 TX Vref=24, minBit 0, minWin=24, winSum=403
2946 22:55:37.946016 TX Vref=26, minBit 0, minWin=24, winSum=405
2947 22:55:37.949078 TX Vref=28, minBit 0, minWin=25, winSum=412
2948 22:55:37.952708 TX Vref=30, minBit 1, minWin=24, winSum=412
2949 22:55:37.955792 TX Vref=32, minBit 1, minWin=25, winSum=414
2950 22:55:37.962350 [TxChooseVref] Worse bit 1, Min win 25, Win sum 414, Final Vref 32
2951 22:55:37.962434
2952 22:55:37.965629 Final TX Range 1 Vref 32
2953 22:55:37.965712
2954 22:55:37.965777 ==
2955 22:55:37.969193 Dram Type= 6, Freq= 0, CH_0, rank 1
2956 22:55:37.972449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2957 22:55:37.972533 ==
2958 22:55:37.972599
2959 22:55:37.975671
2960 22:55:37.975754 TX Vref Scan disable
2961 22:55:37.979087 == TX Byte 0 ==
2962 22:55:37.982480 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2963 22:55:37.985441 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2964 22:55:37.988711 == TX Byte 1 ==
2965 22:55:37.992070 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2966 22:55:37.995297 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2967 22:55:37.998661
2968 22:55:37.998748 [DATLAT]
2969 22:55:37.998815 Freq=1200, CH0 RK1
2970 22:55:37.998876
2971 22:55:38.002050 DATLAT Default: 0xd
2972 22:55:38.002133 0, 0xFFFF, sum = 0
2973 22:55:38.005306 1, 0xFFFF, sum = 0
2974 22:55:38.005391 2, 0xFFFF, sum = 0
2975 22:55:38.009058 3, 0xFFFF, sum = 0
2976 22:55:38.011956 4, 0xFFFF, sum = 0
2977 22:55:38.012042 5, 0xFFFF, sum = 0
2978 22:55:38.015418 6, 0xFFFF, sum = 0
2979 22:55:38.015503 7, 0xFFFF, sum = 0
2980 22:55:38.018806 8, 0xFFFF, sum = 0
2981 22:55:38.018894 9, 0xFFFF, sum = 0
2982 22:55:38.022304 10, 0xFFFF, sum = 0
2983 22:55:38.022389 11, 0xFFFF, sum = 0
2984 22:55:38.025280 12, 0x0, sum = 1
2985 22:55:38.025368 13, 0x0, sum = 2
2986 22:55:38.028638 14, 0x0, sum = 3
2987 22:55:38.028737 15, 0x0, sum = 4
2988 22:55:38.028815 best_step = 13
2989 22:55:38.031914
2990 22:55:38.032020 ==
2991 22:55:38.035265 Dram Type= 6, Freq= 0, CH_0, rank 1
2992 22:55:38.038639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2993 22:55:38.038725 ==
2994 22:55:38.038791 RX Vref Scan: 0
2995 22:55:38.038851
2996 22:55:38.042013 RX Vref 0 -> 0, step: 1
2997 22:55:38.042096
2998 22:55:38.045265 RX Delay -21 -> 252, step: 4
2999 22:55:38.048417 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3000 22:55:38.055666 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3001 22:55:38.058355 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3002 22:55:38.061947 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3003 22:55:38.065521 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3004 22:55:38.068390 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3005 22:55:38.075054 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3006 22:55:38.078414 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3007 22:55:38.082073 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3008 22:55:38.085316 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3009 22:55:38.088640 iDelay=195, Bit 10, Center 108 (47 ~ 170) 124
3010 22:55:38.095432 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3011 22:55:38.098888 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3012 22:55:38.101721 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3013 22:55:38.105229 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3014 22:55:38.108265 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3015 22:55:38.111644 ==
3016 22:55:38.111731 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 22:55:38.118213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 22:55:38.118303 ==
3019 22:55:38.118370 DQS Delay:
3020 22:55:38.121548 DQS0 = 0, DQS1 = 0
3021 22:55:38.121634 DQM Delay:
3022 22:55:38.124965 DQM0 = 119, DQM1 = 107
3023 22:55:38.125070 DQ Delay:
3024 22:55:38.128106 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =114
3025 22:55:38.131363 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3026 22:55:38.135116 DQ8 =98, DQ9 =94, DQ10 =108, DQ11 =106
3027 22:55:38.138864 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3028 22:55:38.138952
3029 22:55:38.139019
3030 22:55:38.148427 [DQSOSCAuto] RK1, (LSB)MR18= 0xcf4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 405 ps
3031 22:55:38.148528 CH0 RK1: MR19=403, MR18=CF4
3032 22:55:38.154906 CH0_RK1: MR19=0x403, MR18=0xCF4, DQSOSC=405, MR23=63, INC=39, DEC=26
3033 22:55:38.158692 [RxdqsGatingPostProcess] freq 1200
3034 22:55:38.164638 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3035 22:55:38.168167 best DQS0 dly(2T, 0.5T) = (0, 11)
3036 22:55:38.171286 best DQS1 dly(2T, 0.5T) = (0, 12)
3037 22:55:38.174829 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3038 22:55:38.178335 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3039 22:55:38.181401 best DQS0 dly(2T, 0.5T) = (0, 11)
3040 22:55:38.181488 best DQS1 dly(2T, 0.5T) = (0, 11)
3041 22:55:38.184598 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3042 22:55:38.188898 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3043 22:55:38.191420 Pre-setting of DQS Precalculation
3044 22:55:38.197867 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3045 22:55:38.197967 ==
3046 22:55:38.201108 Dram Type= 6, Freq= 0, CH_1, rank 0
3047 22:55:38.205035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3048 22:55:38.205125 ==
3049 22:55:38.211059 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3050 22:55:38.218019 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3051 22:55:38.224694 [CA 0] Center 37 (7~67) winsize 61
3052 22:55:38.228134 [CA 1] Center 37 (7~68) winsize 62
3053 22:55:38.231417 [CA 2] Center 34 (4~65) winsize 62
3054 22:55:38.235286 [CA 3] Center 33 (3~64) winsize 62
3055 22:55:38.238145 [CA 4] Center 33 (3~64) winsize 62
3056 22:55:38.241693 [CA 5] Center 33 (3~63) winsize 61
3057 22:55:38.241781
3058 22:55:38.244693 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3059 22:55:38.244785
3060 22:55:38.248192 [CATrainingPosCal] consider 1 rank data
3061 22:55:38.251363 u2DelayCellTimex100 = 270/100 ps
3062 22:55:38.254897 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3063 22:55:38.258165 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3064 22:55:38.265454 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3065 22:55:38.268621 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3066 22:55:38.271806 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3067 22:55:38.274917 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3068 22:55:38.275002
3069 22:55:38.278220 CA PerBit enable=1, Macro0, CA PI delay=33
3070 22:55:38.278305
3071 22:55:38.281681 [CBTSetCACLKResult] CA Dly = 33
3072 22:55:38.281765 CS Dly: 4 (0~35)
3073 22:55:38.281833 ==
3074 22:55:38.284984 Dram Type= 6, Freq= 0, CH_1, rank 1
3075 22:55:38.292409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3076 22:55:38.292497 ==
3077 22:55:38.295103 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3078 22:55:38.301502 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3079 22:55:38.310383 [CA 0] Center 38 (8~68) winsize 61
3080 22:55:38.313640 [CA 1] Center 37 (7~68) winsize 62
3081 22:55:38.317208 [CA 2] Center 35 (5~65) winsize 61
3082 22:55:38.320680 [CA 3] Center 34 (4~65) winsize 62
3083 22:55:38.325315 [CA 4] Center 34 (4~64) winsize 61
3084 22:55:38.327004 [CA 5] Center 33 (3~64) winsize 62
3085 22:55:38.327093
3086 22:55:38.330528 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3087 22:55:38.330613
3088 22:55:38.334407 [CATrainingPosCal] consider 2 rank data
3089 22:55:38.336899 u2DelayCellTimex100 = 270/100 ps
3090 22:55:38.340426 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3091 22:55:38.347014 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3092 22:55:38.350546 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3093 22:55:38.353901 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3094 22:55:38.357228 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3095 22:55:38.360549 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3096 22:55:38.360633
3097 22:55:38.363645 CA PerBit enable=1, Macro0, CA PI delay=33
3098 22:55:38.363729
3099 22:55:38.367225 [CBTSetCACLKResult] CA Dly = 33
3100 22:55:38.367309 CS Dly: 5 (0~38)
3101 22:55:38.370339
3102 22:55:38.373388 ----->DramcWriteLeveling(PI) begin...
3103 22:55:38.373473 ==
3104 22:55:38.377037 Dram Type= 6, Freq= 0, CH_1, rank 0
3105 22:55:38.380208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3106 22:55:38.380293 ==
3107 22:55:38.383326 Write leveling (Byte 0): 24 => 24
3108 22:55:38.386675 Write leveling (Byte 1): 27 => 27
3109 22:55:38.390342 DramcWriteLeveling(PI) end<-----
3110 22:55:38.390427
3111 22:55:38.390494 ==
3112 22:55:38.393540 Dram Type= 6, Freq= 0, CH_1, rank 0
3113 22:55:38.396921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3114 22:55:38.397007 ==
3115 22:55:38.400144 [Gating] SW mode calibration
3116 22:55:38.406760 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3117 22:55:38.413131 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3118 22:55:38.416578 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3119 22:55:38.420159 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3120 22:55:38.426876 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3121 22:55:38.430235 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 22:55:38.433705 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3123 22:55:38.436652 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3124 22:55:38.443296 0 15 24 | B1->B0 | 2828 2626 | 0 0 | (0 0) (0 0)
3125 22:55:38.446445 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3126 22:55:38.449843 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 22:55:38.456379 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 22:55:38.459700 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 22:55:38.463393 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 22:55:38.469636 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 22:55:38.473234 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 22:55:38.476397 1 0 24 | B1->B0 | 3b3b 4444 | 0 0 | (0 0) (0 0)
3133 22:55:38.483090 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 22:55:38.486184 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 22:55:38.489565 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 22:55:38.496302 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 22:55:38.499815 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 22:55:38.503015 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 22:55:38.509971 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3140 22:55:38.513076 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3141 22:55:38.516149 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 22:55:38.522822 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 22:55:38.526116 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 22:55:38.529456 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 22:55:38.536203 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 22:55:38.539332 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 22:55:38.542828 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 22:55:38.549585 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 22:55:38.553596 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 22:55:38.556105 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 22:55:38.562683 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 22:55:38.566140 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 22:55:38.569315 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 22:55:38.575876 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 22:55:38.579254 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3156 22:55:38.582527 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3157 22:55:38.589548 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 22:55:38.589632 Total UI for P1: 0, mck2ui 16
3159 22:55:38.592512 best dqsien dly found for B0: ( 1, 3, 22)
3160 22:55:38.595901 Total UI for P1: 0, mck2ui 16
3161 22:55:38.599112 best dqsien dly found for B1: ( 1, 3, 24)
3162 22:55:38.602405 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3163 22:55:38.609134 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3164 22:55:38.609217
3165 22:55:38.612455 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3166 22:55:38.615887 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3167 22:55:38.619326 [Gating] SW calibration Done
3168 22:55:38.619408 ==
3169 22:55:38.622492 Dram Type= 6, Freq= 0, CH_1, rank 0
3170 22:55:38.625773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3171 22:55:38.625856 ==
3172 22:55:38.625922 RX Vref Scan: 0
3173 22:55:38.629151
3174 22:55:38.629233 RX Vref 0 -> 0, step: 1
3175 22:55:38.629299
3176 22:55:38.632472 RX Delay -40 -> 252, step: 8
3177 22:55:38.635900 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3178 22:55:38.639198 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3179 22:55:38.645779 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3180 22:55:38.649278 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3181 22:55:38.652779 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3182 22:55:38.655564 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3183 22:55:38.658993 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3184 22:55:38.665705 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3185 22:55:38.669014 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3186 22:55:38.672342 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3187 22:55:38.675785 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3188 22:55:38.678968 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3189 22:55:38.685677 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3190 22:55:38.688860 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3191 22:55:38.692161 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3192 22:55:38.695433 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3193 22:55:38.695515 ==
3194 22:55:38.699017 Dram Type= 6, Freq= 0, CH_1, rank 0
3195 22:55:38.705666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3196 22:55:38.705767 ==
3197 22:55:38.705833 DQS Delay:
3198 22:55:38.708949 DQS0 = 0, DQS1 = 0
3199 22:55:38.709032 DQM Delay:
3200 22:55:38.709098 DQM0 = 120, DQM1 = 112
3201 22:55:38.712278 DQ Delay:
3202 22:55:38.715735 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =119
3203 22:55:38.718854 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =123
3204 22:55:38.722164 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3205 22:55:38.725679 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3206 22:55:38.725762
3207 22:55:38.725827
3208 22:55:38.725886 ==
3209 22:55:38.728643 Dram Type= 6, Freq= 0, CH_1, rank 0
3210 22:55:38.732098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3211 22:55:38.735497 ==
3212 22:55:38.735602
3213 22:55:38.735666
3214 22:55:38.735726 TX Vref Scan disable
3215 22:55:38.738743 == TX Byte 0 ==
3216 22:55:38.742238 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3217 22:55:38.745383 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3218 22:55:38.749002 == TX Byte 1 ==
3219 22:55:38.752004 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3220 22:55:38.755536 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3221 22:55:38.755619 ==
3222 22:55:38.758644 Dram Type= 6, Freq= 0, CH_1, rank 0
3223 22:55:38.765431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3224 22:55:38.765514 ==
3225 22:55:38.776228 TX Vref=22, minBit 1, minWin=24, winSum=397
3226 22:55:38.779373 TX Vref=24, minBit 10, minWin=23, winSum=404
3227 22:55:38.782665 TX Vref=26, minBit 3, minWin=25, winSum=408
3228 22:55:38.785798 TX Vref=28, minBit 8, minWin=25, winSum=415
3229 22:55:38.789376 TX Vref=30, minBit 10, minWin=25, winSum=421
3230 22:55:38.796301 TX Vref=32, minBit 10, minWin=25, winSum=418
3231 22:55:38.799201 [TxChooseVref] Worse bit 10, Min win 25, Win sum 421, Final Vref 30
3232 22:55:38.799285
3233 22:55:38.802531 Final TX Range 1 Vref 30
3234 22:55:38.802614
3235 22:55:38.802680 ==
3236 22:55:38.806005 Dram Type= 6, Freq= 0, CH_1, rank 0
3237 22:55:38.809263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3238 22:55:38.812749 ==
3239 22:55:38.812852
3240 22:55:38.812918
3241 22:55:38.812977 TX Vref Scan disable
3242 22:55:38.816016 == TX Byte 0 ==
3243 22:55:38.820151 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3244 22:55:38.825980 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3245 22:55:38.826064 == TX Byte 1 ==
3246 22:55:38.829439 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3247 22:55:38.835936 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3248 22:55:38.836019
3249 22:55:38.836085 [DATLAT]
3250 22:55:38.836145 Freq=1200, CH1 RK0
3251 22:55:38.836204
3252 22:55:38.839299 DATLAT Default: 0xd
3253 22:55:38.839433 0, 0xFFFF, sum = 0
3254 22:55:38.842460 1, 0xFFFF, sum = 0
3255 22:55:38.845704 2, 0xFFFF, sum = 0
3256 22:55:38.845837 3, 0xFFFF, sum = 0
3257 22:55:38.849400 4, 0xFFFF, sum = 0
3258 22:55:38.849485 5, 0xFFFF, sum = 0
3259 22:55:38.852338 6, 0xFFFF, sum = 0
3260 22:55:38.852422 7, 0xFFFF, sum = 0
3261 22:55:38.855897 8, 0xFFFF, sum = 0
3262 22:55:38.855980 9, 0xFFFF, sum = 0
3263 22:55:38.859075 10, 0xFFFF, sum = 0
3264 22:55:38.859158 11, 0xFFFF, sum = 0
3265 22:55:38.862539 12, 0x0, sum = 1
3266 22:55:38.862623 13, 0x0, sum = 2
3267 22:55:38.865629 14, 0x0, sum = 3
3268 22:55:38.865713 15, 0x0, sum = 4
3269 22:55:38.869371 best_step = 13
3270 22:55:38.869453
3271 22:55:38.869518 ==
3272 22:55:38.872455 Dram Type= 6, Freq= 0, CH_1, rank 0
3273 22:55:38.876148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3274 22:55:38.876231 ==
3275 22:55:38.876297 RX Vref Scan: 1
3276 22:55:38.876358
3277 22:55:38.879010 Set Vref Range= 32 -> 127
3278 22:55:38.879092
3279 22:55:38.882750 RX Vref 32 -> 127, step: 1
3280 22:55:38.882834
3281 22:55:38.885650 RX Delay -13 -> 252, step: 4
3282 22:55:38.885734
3283 22:55:38.889129 Set Vref, RX VrefLevel [Byte0]: 32
3284 22:55:38.892429 [Byte1]: 32
3285 22:55:38.892513
3286 22:55:38.895837 Set Vref, RX VrefLevel [Byte0]: 33
3287 22:55:38.899270 [Byte1]: 33
3288 22:55:38.902429
3289 22:55:38.902513 Set Vref, RX VrefLevel [Byte0]: 34
3290 22:55:38.905574 [Byte1]: 34
3291 22:55:38.910134
3292 22:55:38.910218 Set Vref, RX VrefLevel [Byte0]: 35
3293 22:55:38.913541 [Byte1]: 35
3294 22:55:38.918538
3295 22:55:38.918622 Set Vref, RX VrefLevel [Byte0]: 36
3296 22:55:38.921622 [Byte1]: 36
3297 22:55:38.926245
3298 22:55:38.926329 Set Vref, RX VrefLevel [Byte0]: 37
3299 22:55:38.929603 [Byte1]: 37
3300 22:55:38.934191
3301 22:55:38.934273 Set Vref, RX VrefLevel [Byte0]: 38
3302 22:55:38.937045 [Byte1]: 38
3303 22:55:38.941693
3304 22:55:38.941780 Set Vref, RX VrefLevel [Byte0]: 39
3305 22:55:38.945194 [Byte1]: 39
3306 22:55:38.949628
3307 22:55:38.949738 Set Vref, RX VrefLevel [Byte0]: 40
3308 22:55:38.953184 [Byte1]: 40
3309 22:55:38.957905
3310 22:55:38.957987 Set Vref, RX VrefLevel [Byte0]: 41
3311 22:55:38.960890 [Byte1]: 41
3312 22:55:38.965813
3313 22:55:38.965895 Set Vref, RX VrefLevel [Byte0]: 42
3314 22:55:38.968937 [Byte1]: 42
3315 22:55:38.973580
3316 22:55:38.973722 Set Vref, RX VrefLevel [Byte0]: 43
3317 22:55:38.976589 [Byte1]: 43
3318 22:55:38.981131
3319 22:55:38.981274 Set Vref, RX VrefLevel [Byte0]: 44
3320 22:55:38.984403 [Byte1]: 44
3321 22:55:38.989115
3322 22:55:38.989259 Set Vref, RX VrefLevel [Byte0]: 45
3323 22:55:38.992518 [Byte1]: 45
3324 22:55:38.996881
3325 22:55:38.997029 Set Vref, RX VrefLevel [Byte0]: 46
3326 22:55:39.000534 [Byte1]: 46
3327 22:55:39.005040
3328 22:55:39.005180 Set Vref, RX VrefLevel [Byte0]: 47
3329 22:55:39.008192 [Byte1]: 47
3330 22:55:39.013214
3331 22:55:39.013359 Set Vref, RX VrefLevel [Byte0]: 48
3332 22:55:39.016210 [Byte1]: 48
3333 22:55:39.021300
3334 22:55:39.021412 Set Vref, RX VrefLevel [Byte0]: 49
3335 22:55:39.024676 [Byte1]: 49
3336 22:55:39.028952
3337 22:55:39.029058 Set Vref, RX VrefLevel [Byte0]: 50
3338 22:55:39.031899 [Byte1]: 50
3339 22:55:39.036442
3340 22:55:39.036543 Set Vref, RX VrefLevel [Byte0]: 51
3341 22:55:39.039731 [Byte1]: 51
3342 22:55:39.044163
3343 22:55:39.044260 Set Vref, RX VrefLevel [Byte0]: 52
3344 22:55:39.047894 [Byte1]: 52
3345 22:55:39.052061
3346 22:55:39.052150 Set Vref, RX VrefLevel [Byte0]: 53
3347 22:55:39.055841 [Byte1]: 53
3348 22:55:39.060382
3349 22:55:39.060485 Set Vref, RX VrefLevel [Byte0]: 54
3350 22:55:39.063380 [Byte1]: 54
3351 22:55:39.068234
3352 22:55:39.068316 Set Vref, RX VrefLevel [Byte0]: 55
3353 22:55:39.071366 [Byte1]: 55
3354 22:55:39.076076
3355 22:55:39.076222 Set Vref, RX VrefLevel [Byte0]: 56
3356 22:55:39.079284 [Byte1]: 56
3357 22:55:39.083827
3358 22:55:39.083972 Set Vref, RX VrefLevel [Byte0]: 57
3359 22:55:39.087377 [Byte1]: 57
3360 22:55:39.091643
3361 22:55:39.091781 Set Vref, RX VrefLevel [Byte0]: 58
3362 22:55:39.095283 [Byte1]: 58
3363 22:55:39.099454
3364 22:55:39.099542 Set Vref, RX VrefLevel [Byte0]: 59
3365 22:55:39.103006 [Byte1]: 59
3366 22:55:39.107580
3367 22:55:39.107689 Set Vref, RX VrefLevel [Byte0]: 60
3368 22:55:39.110734 [Byte1]: 60
3369 22:55:39.115259
3370 22:55:39.115374 Set Vref, RX VrefLevel [Byte0]: 61
3371 22:55:39.118694 [Byte1]: 61
3372 22:55:39.123330
3373 22:55:39.123439 Set Vref, RX VrefLevel [Byte0]: 62
3374 22:55:39.126592 [Byte1]: 62
3375 22:55:39.131429
3376 22:55:39.131535 Set Vref, RX VrefLevel [Byte0]: 63
3377 22:55:39.134558 [Byte1]: 63
3378 22:55:39.138937
3379 22:55:39.139042 Set Vref, RX VrefLevel [Byte0]: 64
3380 22:55:39.142233 [Byte1]: 64
3381 22:55:39.147612
3382 22:55:39.147696 Set Vref, RX VrefLevel [Byte0]: 65
3383 22:55:39.150474 [Byte1]: 65
3384 22:55:39.155013
3385 22:55:39.155090 Set Vref, RX VrefLevel [Byte0]: 66
3386 22:55:39.158287 [Byte1]: 66
3387 22:55:39.162606
3388 22:55:39.162682 Final RX Vref Byte 0 = 52 to rank0
3389 22:55:39.165872 Final RX Vref Byte 1 = 51 to rank0
3390 22:55:39.169219 Final RX Vref Byte 0 = 52 to rank1
3391 22:55:39.172582 Final RX Vref Byte 1 = 51 to rank1==
3392 22:55:39.175653 Dram Type= 6, Freq= 0, CH_1, rank 0
3393 22:55:39.182515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3394 22:55:39.182605 ==
3395 22:55:39.182701 DQS Delay:
3396 22:55:39.186027 DQS0 = 0, DQS1 = 0
3397 22:55:39.186104 DQM Delay:
3398 22:55:39.186167 DQM0 = 119, DQM1 = 111
3399 22:55:39.189186 DQ Delay:
3400 22:55:39.192471 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3401 22:55:39.195808 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =116
3402 22:55:39.199061 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3403 22:55:39.202404 DQ12 =122, DQ13 =116, DQ14 =118, DQ15 =116
3404 22:55:39.202489
3405 22:55:39.202556
3406 22:55:39.212463 [DQSOSCAuto] RK0, (LSB)MR18= 0x417, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3407 22:55:39.212551 CH1 RK0: MR19=404, MR18=417
3408 22:55:39.219309 CH1_RK0: MR19=0x404, MR18=0x417, DQSOSC=401, MR23=63, INC=40, DEC=27
3409 22:55:39.219396
3410 22:55:39.222464 ----->DramcWriteLeveling(PI) begin...
3411 22:55:39.222550 ==
3412 22:55:39.225960 Dram Type= 6, Freq= 0, CH_1, rank 1
3413 22:55:39.228976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3414 22:55:39.232336 ==
3415 22:55:39.232421 Write leveling (Byte 0): 25 => 25
3416 22:55:39.236232 Write leveling (Byte 1): 30 => 30
3417 22:55:39.239076 DramcWriteLeveling(PI) end<-----
3418 22:55:39.239159
3419 22:55:39.239224 ==
3420 22:55:39.242340 Dram Type= 6, Freq= 0, CH_1, rank 1
3421 22:55:39.249240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3422 22:55:39.249324 ==
3423 22:55:39.252180 [Gating] SW mode calibration
3424 22:55:39.258874 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3425 22:55:39.262100 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3426 22:55:39.268932 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3427 22:55:39.272358 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3428 22:55:39.275488 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3429 22:55:39.282125 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3430 22:55:39.285789 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3431 22:55:39.288610 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3432 22:55:39.295363 0 15 24 | B1->B0 | 2c2c 3434 | 0 0 | (1 0) (0 1)
3433 22:55:39.298822 0 15 28 | B1->B0 | 2323 2828 | 0 1 | (1 0) (0 0)
3434 22:55:39.302360 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3435 22:55:39.308879 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3436 22:55:39.312058 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3437 22:55:39.315207 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3438 22:55:39.321743 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3439 22:55:39.325194 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3440 22:55:39.328681 1 0 24 | B1->B0 | 4242 3333 | 0 0 | (0 0) (0 0)
3441 22:55:39.331690 1 0 28 | B1->B0 | 4646 4242 | 0 1 | (0 0) (0 0)
3442 22:55:39.338724 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3443 22:55:39.341692 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3444 22:55:39.344949 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3445 22:55:39.351921 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3446 22:55:39.355101 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3447 22:55:39.358566 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3448 22:55:39.365235 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3449 22:55:39.368560 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3450 22:55:39.371974 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3451 22:55:39.378281 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3452 22:55:39.381888 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3453 22:55:39.385338 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3454 22:55:39.391406 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3455 22:55:39.395067 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 22:55:39.398106 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 22:55:39.404795 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 22:55:39.408113 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 22:55:39.411263 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 22:55:39.417964 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 22:55:39.421039 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 22:55:39.424530 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 22:55:39.431533 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3464 22:55:39.434337 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3465 22:55:39.437937 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3466 22:55:39.441885 Total UI for P1: 0, mck2ui 16
3467 22:55:39.444168 best dqsien dly found for B1: ( 1, 3, 22)
3468 22:55:39.450774 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 22:55:39.450857 Total UI for P1: 0, mck2ui 16
3470 22:55:39.457259 best dqsien dly found for B0: ( 1, 3, 26)
3471 22:55:39.460806 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3472 22:55:39.464012 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3473 22:55:39.464095
3474 22:55:39.467182 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3475 22:55:39.470911 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3476 22:55:39.474689 [Gating] SW calibration Done
3477 22:55:39.474801 ==
3478 22:55:39.477580 Dram Type= 6, Freq= 0, CH_1, rank 1
3479 22:55:39.480327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3480 22:55:39.480425 ==
3481 22:55:39.483657 RX Vref Scan: 0
3482 22:55:39.483739
3483 22:55:39.483804 RX Vref 0 -> 0, step: 1
3484 22:55:39.487117
3485 22:55:39.487198 RX Delay -40 -> 252, step: 8
3486 22:55:39.493801 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3487 22:55:39.497107 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3488 22:55:39.500270 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3489 22:55:39.503608 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3490 22:55:39.506903 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3491 22:55:39.513408 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3492 22:55:39.516696 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3493 22:55:39.520429 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3494 22:55:39.523601 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3495 22:55:39.527552 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3496 22:55:39.533815 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3497 22:55:39.536597 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3498 22:55:39.539943 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3499 22:55:39.543374 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3500 22:55:39.546601 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3501 22:55:39.553294 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3502 22:55:39.553377 ==
3503 22:55:39.556562 Dram Type= 6, Freq= 0, CH_1, rank 1
3504 22:55:39.560168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3505 22:55:39.560251 ==
3506 22:55:39.560318 DQS Delay:
3507 22:55:39.563536 DQS0 = 0, DQS1 = 0
3508 22:55:39.563617 DQM Delay:
3509 22:55:39.566756 DQM0 = 120, DQM1 = 114
3510 22:55:39.566896 DQ Delay:
3511 22:55:39.569874 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =123
3512 22:55:39.573605 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3513 22:55:39.577298 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3514 22:55:39.579665 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =123
3515 22:55:39.579748
3516 22:55:39.583065
3517 22:55:39.583148 ==
3518 22:55:39.586398 Dram Type= 6, Freq= 0, CH_1, rank 1
3519 22:55:39.589794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3520 22:55:39.589879 ==
3521 22:55:39.589946
3522 22:55:39.590007
3523 22:55:39.593044 TX Vref Scan disable
3524 22:55:39.593128 == TX Byte 0 ==
3525 22:55:39.599641 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3526 22:55:39.602984 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3527 22:55:39.603068 == TX Byte 1 ==
3528 22:55:39.609784 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3529 22:55:39.613076 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3530 22:55:39.613161 ==
3531 22:55:39.616751 Dram Type= 6, Freq= 0, CH_1, rank 1
3532 22:55:39.619493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3533 22:55:39.619578 ==
3534 22:55:39.632058 TX Vref=22, minBit 3, minWin=24, winSum=411
3535 22:55:39.635358 TX Vref=24, minBit 1, minWin=25, winSum=415
3536 22:55:39.638422 TX Vref=26, minBit 1, minWin=25, winSum=422
3537 22:55:39.641981 TX Vref=28, minBit 3, minWin=25, winSum=425
3538 22:55:39.645205 TX Vref=30, minBit 9, minWin=25, winSum=425
3539 22:55:39.652010 TX Vref=32, minBit 1, minWin=26, winSum=424
3540 22:55:39.655326 [TxChooseVref] Worse bit 1, Min win 26, Win sum 424, Final Vref 32
3541 22:55:39.655410
3542 22:55:39.658387 Final TX Range 1 Vref 32
3543 22:55:39.658472
3544 22:55:39.658538 ==
3545 22:55:39.662066 Dram Type= 6, Freq= 0, CH_1, rank 1
3546 22:55:39.664702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3547 22:55:39.668376 ==
3548 22:55:39.668460
3549 22:55:39.668527
3550 22:55:39.668590 TX Vref Scan disable
3551 22:55:39.671614 == TX Byte 0 ==
3552 22:55:39.675548 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3553 22:55:39.681428 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3554 22:55:39.681513 == TX Byte 1 ==
3555 22:55:39.684926 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3556 22:55:39.691199 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3557 22:55:39.691283
3558 22:55:39.691349 [DATLAT]
3559 22:55:39.691410 Freq=1200, CH1 RK1
3560 22:55:39.691469
3561 22:55:39.694894 DATLAT Default: 0xd
3562 22:55:39.697969 0, 0xFFFF, sum = 0
3563 22:55:39.698055 1, 0xFFFF, sum = 0
3564 22:55:39.701343 2, 0xFFFF, sum = 0
3565 22:55:39.701427 3, 0xFFFF, sum = 0
3566 22:55:39.704736 4, 0xFFFF, sum = 0
3567 22:55:39.704863 5, 0xFFFF, sum = 0
3568 22:55:39.707851 6, 0xFFFF, sum = 0
3569 22:55:39.707935 7, 0xFFFF, sum = 0
3570 22:55:39.711187 8, 0xFFFF, sum = 0
3571 22:55:39.711271 9, 0xFFFF, sum = 0
3572 22:55:39.714609 10, 0xFFFF, sum = 0
3573 22:55:39.714693 11, 0xFFFF, sum = 0
3574 22:55:39.717616 12, 0x0, sum = 1
3575 22:55:39.717699 13, 0x0, sum = 2
3576 22:55:39.721560 14, 0x0, sum = 3
3577 22:55:39.721644 15, 0x0, sum = 4
3578 22:55:39.724936 best_step = 13
3579 22:55:39.725017
3580 22:55:39.725082 ==
3581 22:55:39.727434 Dram Type= 6, Freq= 0, CH_1, rank 1
3582 22:55:39.731005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3583 22:55:39.731089 ==
3584 22:55:39.734372 RX Vref Scan: 0
3585 22:55:39.734454
3586 22:55:39.734520 RX Vref 0 -> 0, step: 1
3587 22:55:39.734580
3588 22:55:39.737789 RX Delay -13 -> 252, step: 4
3589 22:55:39.744475 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3590 22:55:39.747523 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3591 22:55:39.750676 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3592 22:55:39.754476 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3593 22:55:39.757282 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3594 22:55:39.764013 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3595 22:55:39.767134 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3596 22:55:39.770686 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3597 22:55:39.774162 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3598 22:55:39.777078 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3599 22:55:39.784202 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3600 22:55:39.787522 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3601 22:55:39.790388 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3602 22:55:39.793654 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3603 22:55:39.800602 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3604 22:55:39.804589 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3605 22:55:39.804674 ==
3606 22:55:39.807132 Dram Type= 6, Freq= 0, CH_1, rank 1
3607 22:55:39.810055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3608 22:55:39.810141 ==
3609 22:55:39.813846 DQS Delay:
3610 22:55:39.813930 DQS0 = 0, DQS1 = 0
3611 22:55:39.813997 DQM Delay:
3612 22:55:39.816911 DQM0 = 119, DQM1 = 112
3613 22:55:39.816996 DQ Delay:
3614 22:55:39.820501 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3615 22:55:39.823602 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3616 22:55:39.826672 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =106
3617 22:55:39.833206 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3618 22:55:39.833294
3619 22:55:39.833366
3620 22:55:39.839852 [DQSOSCAuto] RK1, (LSB)MR18= 0x7ec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 407 ps
3621 22:55:39.843285 CH1 RK1: MR19=403, MR18=7EC
3622 22:55:39.849918 CH1_RK1: MR19=0x403, MR18=0x7EC, DQSOSC=407, MR23=63, INC=39, DEC=26
3623 22:55:39.853040 [RxdqsGatingPostProcess] freq 1200
3624 22:55:39.857006 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3625 22:55:39.859594 best DQS0 dly(2T, 0.5T) = (0, 11)
3626 22:55:39.863133 best DQS1 dly(2T, 0.5T) = (0, 11)
3627 22:55:39.866833 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3628 22:55:39.869779 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3629 22:55:39.872978 best DQS0 dly(2T, 0.5T) = (0, 11)
3630 22:55:39.876187 best DQS1 dly(2T, 0.5T) = (0, 11)
3631 22:55:39.879648 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3632 22:55:39.882791 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3633 22:55:39.886370 Pre-setting of DQS Precalculation
3634 22:55:39.889735 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3635 22:55:39.899453 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3636 22:55:39.906495 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3637 22:55:39.906585
3638 22:55:39.906652
3639 22:55:39.909704 [Calibration Summary] 2400 Mbps
3640 22:55:39.909790 CH 0, Rank 0
3641 22:55:39.912599 SW Impedance : PASS
3642 22:55:39.912684 DUTY Scan : NO K
3643 22:55:39.915950 ZQ Calibration : PASS
3644 22:55:39.919435 Jitter Meter : NO K
3645 22:55:39.919522 CBT Training : PASS
3646 22:55:39.922842 Write leveling : PASS
3647 22:55:39.925885 RX DQS gating : PASS
3648 22:55:39.925972 RX DQ/DQS(RDDQC) : PASS
3649 22:55:39.929262 TX DQ/DQS : PASS
3650 22:55:39.929364 RX DATLAT : PASS
3651 22:55:39.932727 RX DQ/DQS(Engine): PASS
3652 22:55:39.935942 TX OE : NO K
3653 22:55:39.936043 All Pass.
3654 22:55:39.936152
3655 22:55:39.936243 CH 0, Rank 1
3656 22:55:39.939357 SW Impedance : PASS
3657 22:55:39.942585 DUTY Scan : NO K
3658 22:55:39.942671 ZQ Calibration : PASS
3659 22:55:39.945977 Jitter Meter : NO K
3660 22:55:39.949152 CBT Training : PASS
3661 22:55:39.949281 Write leveling : PASS
3662 22:55:39.952301 RX DQS gating : PASS
3663 22:55:39.955517 RX DQ/DQS(RDDQC) : PASS
3664 22:55:39.955604 TX DQ/DQS : PASS
3665 22:55:39.959419 RX DATLAT : PASS
3666 22:55:39.962307 RX DQ/DQS(Engine): PASS
3667 22:55:39.962409 TX OE : NO K
3668 22:55:39.965613 All Pass.
3669 22:55:39.965729
3670 22:55:39.965796 CH 1, Rank 0
3671 22:55:39.969022 SW Impedance : PASS
3672 22:55:39.969107 DUTY Scan : NO K
3673 22:55:39.972444 ZQ Calibration : PASS
3674 22:55:39.975931 Jitter Meter : NO K
3675 22:55:39.976016 CBT Training : PASS
3676 22:55:39.978859 Write leveling : PASS
3677 22:55:39.981982 RX DQS gating : PASS
3678 22:55:39.982067 RX DQ/DQS(RDDQC) : PASS
3679 22:55:39.986027 TX DQ/DQS : PASS
3680 22:55:39.988916 RX DATLAT : PASS
3681 22:55:39.989045 RX DQ/DQS(Engine): PASS
3682 22:55:39.993055 TX OE : NO K
3683 22:55:39.993155 All Pass.
3684 22:55:39.993223
3685 22:55:39.995441 CH 1, Rank 1
3686 22:55:39.995525 SW Impedance : PASS
3687 22:55:39.998649 DUTY Scan : NO K
3688 22:55:39.998817 ZQ Calibration : PASS
3689 22:55:40.001929 Jitter Meter : NO K
3690 22:55:40.005555 CBT Training : PASS
3691 22:55:40.005639 Write leveling : PASS
3692 22:55:40.008603 RX DQS gating : PASS
3693 22:55:40.012215 RX DQ/DQS(RDDQC) : PASS
3694 22:55:40.012298 TX DQ/DQS : PASS
3695 22:55:40.015333 RX DATLAT : PASS
3696 22:55:40.018701 RX DQ/DQS(Engine): PASS
3697 22:55:40.018784 TX OE : NO K
3698 22:55:40.021864 All Pass.
3699 22:55:40.021948
3700 22:55:40.022013 DramC Write-DBI off
3701 22:55:40.025081 PER_BANK_REFRESH: Hybrid Mode
3702 22:55:40.025192 TX_TRACKING: ON
3703 22:55:40.035306 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3704 22:55:40.038533 [FAST_K] Save calibration result to emmc
3705 22:55:40.041723 dramc_set_vcore_voltage set vcore to 650000
3706 22:55:40.045068 Read voltage for 600, 5
3707 22:55:40.045154 Vio18 = 0
3708 22:55:40.048504 Vcore = 650000
3709 22:55:40.048614 Vdram = 0
3710 22:55:40.048708 Vddq = 0
3711 22:55:40.051817 Vmddr = 0
3712 22:55:40.055096 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3713 22:55:40.061869 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3714 22:55:40.061956 MEM_TYPE=3, freq_sel=19
3715 22:55:40.065262 sv_algorithm_assistance_LP4_1600
3716 22:55:40.071605 ============ PULL DRAM RESETB DOWN ============
3717 22:55:40.074905 ========== PULL DRAM RESETB DOWN end =========
3718 22:55:40.078253 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3719 22:55:40.081583 ===================================
3720 22:55:40.084682 LPDDR4 DRAM CONFIGURATION
3721 22:55:40.088556 ===================================
3722 22:55:40.091442 EX_ROW_EN[0] = 0x0
3723 22:55:40.091527 EX_ROW_EN[1] = 0x0
3724 22:55:40.095373 LP4Y_EN = 0x0
3725 22:55:40.095482 WORK_FSP = 0x0
3726 22:55:40.098444 WL = 0x2
3727 22:55:40.098553 RL = 0x2
3728 22:55:40.101238 BL = 0x2
3729 22:55:40.101348 RPST = 0x0
3730 22:55:40.104590 RD_PRE = 0x0
3731 22:55:40.104663 WR_PRE = 0x1
3732 22:55:40.107818 WR_PST = 0x0
3733 22:55:40.107937 DBI_WR = 0x0
3734 22:55:40.112154 DBI_RD = 0x0
3735 22:55:40.112255 OTF = 0x1
3736 22:55:40.114743 ===================================
3737 22:55:40.117684 ===================================
3738 22:55:40.121077 ANA top config
3739 22:55:40.124167 ===================================
3740 22:55:40.127535 DLL_ASYNC_EN = 0
3741 22:55:40.127646 ALL_SLAVE_EN = 1
3742 22:55:40.130748 NEW_RANK_MODE = 1
3743 22:55:40.134381 DLL_IDLE_MODE = 1
3744 22:55:40.137828 LP45_APHY_COMB_EN = 1
3745 22:55:40.137914 TX_ODT_DIS = 1
3746 22:55:40.140710 NEW_8X_MODE = 1
3747 22:55:40.144107 ===================================
3748 22:55:40.147249 ===================================
3749 22:55:40.150730 data_rate = 1200
3750 22:55:40.154618 CKR = 1
3751 22:55:40.157423 DQ_P2S_RATIO = 8
3752 22:55:40.160971 ===================================
3753 22:55:40.164213 CA_P2S_RATIO = 8
3754 22:55:40.164296 DQ_CA_OPEN = 0
3755 22:55:40.167603 DQ_SEMI_OPEN = 0
3756 22:55:40.170782 CA_SEMI_OPEN = 0
3757 22:55:40.173871 CA_FULL_RATE = 0
3758 22:55:40.177323 DQ_CKDIV4_EN = 1
3759 22:55:40.180828 CA_CKDIV4_EN = 1
3760 22:55:40.180900 CA_PREDIV_EN = 0
3761 22:55:40.183841 PH8_DLY = 0
3762 22:55:40.187765 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3763 22:55:40.190582 DQ_AAMCK_DIV = 4
3764 22:55:40.194066 CA_AAMCK_DIV = 4
3765 22:55:40.197076 CA_ADMCK_DIV = 4
3766 22:55:40.197161 DQ_TRACK_CA_EN = 0
3767 22:55:40.201248 CA_PICK = 600
3768 22:55:40.204672 CA_MCKIO = 600
3769 22:55:40.207526 MCKIO_SEMI = 0
3770 22:55:40.210530 PLL_FREQ = 2288
3771 22:55:40.213754 DQ_UI_PI_RATIO = 32
3772 22:55:40.217265 CA_UI_PI_RATIO = 0
3773 22:55:40.221016 ===================================
3774 22:55:40.223767 ===================================
3775 22:55:40.223858 memory_type:LPDDR4
3776 22:55:40.226983 GP_NUM : 10
3777 22:55:40.230289 SRAM_EN : 1
3778 22:55:40.230389 MD32_EN : 0
3779 22:55:40.233611 ===================================
3780 22:55:40.237031 [ANA_INIT] >>>>>>>>>>>>>>
3781 22:55:40.240109 <<<<<< [CONFIGURE PHASE]: ANA_TX
3782 22:55:40.243682 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3783 22:55:40.246800 ===================================
3784 22:55:40.250162 data_rate = 1200,PCW = 0X5800
3785 22:55:40.253457 ===================================
3786 22:55:40.256945 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3787 22:55:40.260243 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3788 22:55:40.267230 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3789 22:55:40.270067 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3790 22:55:40.273542 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3791 22:55:40.277152 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3792 22:55:40.280223 [ANA_INIT] flow start
3793 22:55:40.283643 [ANA_INIT] PLL >>>>>>>>
3794 22:55:40.283728 [ANA_INIT] PLL <<<<<<<<
3795 22:55:40.286457 [ANA_INIT] MIDPI >>>>>>>>
3796 22:55:40.290396 [ANA_INIT] MIDPI <<<<<<<<
3797 22:55:40.293408 [ANA_INIT] DLL >>>>>>>>
3798 22:55:40.293522 [ANA_INIT] flow end
3799 22:55:40.296801 ============ LP4 DIFF to SE enter ============
3800 22:55:40.303135 ============ LP4 DIFF to SE exit ============
3801 22:55:40.303249 [ANA_INIT] <<<<<<<<<<<<<
3802 22:55:40.306565 [Flow] Enable top DCM control >>>>>
3803 22:55:40.310053 [Flow] Enable top DCM control <<<<<
3804 22:55:40.313311 Enable DLL master slave shuffle
3805 22:55:40.319831 ==============================================================
3806 22:55:40.319935 Gating Mode config
3807 22:55:40.326267 ==============================================================
3808 22:55:40.329637 Config description:
3809 22:55:40.339733 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3810 22:55:40.346834 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3811 22:55:40.349465 SELPH_MODE 0: By rank 1: By Phase
3812 22:55:40.355982 ==============================================================
3813 22:55:40.359607 GAT_TRACK_EN = 1
3814 22:55:40.362806 RX_GATING_MODE = 2
3815 22:55:40.362922 RX_GATING_TRACK_MODE = 2
3816 22:55:40.366241 SELPH_MODE = 1
3817 22:55:40.369817 PICG_EARLY_EN = 1
3818 22:55:40.372549 VALID_LAT_VALUE = 1
3819 22:55:40.379867 ==============================================================
3820 22:55:40.382411 Enter into Gating configuration >>>>
3821 22:55:40.385666 Exit from Gating configuration <<<<
3822 22:55:40.389312 Enter into DVFS_PRE_config >>>>>
3823 22:55:40.399068 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3824 22:55:40.402416 Exit from DVFS_PRE_config <<<<<
3825 22:55:40.405984 Enter into PICG configuration >>>>
3826 22:55:40.409245 Exit from PICG configuration <<<<
3827 22:55:40.412216 [RX_INPUT] configuration >>>>>
3828 22:55:40.416056 [RX_INPUT] configuration <<<<<
3829 22:55:40.419020 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3830 22:55:40.425477 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3831 22:55:40.432351 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3832 22:55:40.438760 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3833 22:55:40.445809 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3834 22:55:40.448611 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3835 22:55:40.455005 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3836 22:55:40.458698 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3837 22:55:40.461799 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3838 22:55:40.465003 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3839 22:55:40.471709 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3840 22:55:40.475312 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3841 22:55:40.478221 ===================================
3842 22:55:40.481503 LPDDR4 DRAM CONFIGURATION
3843 22:55:40.485140 ===================================
3844 22:55:40.485223 EX_ROW_EN[0] = 0x0
3845 22:55:40.488344 EX_ROW_EN[1] = 0x0
3846 22:55:40.488427 LP4Y_EN = 0x0
3847 22:55:40.491666 WORK_FSP = 0x0
3848 22:55:40.491749 WL = 0x2
3849 22:55:40.494818 RL = 0x2
3850 22:55:40.494900 BL = 0x2
3851 22:55:40.498420 RPST = 0x0
3852 22:55:40.498502 RD_PRE = 0x0
3853 22:55:40.501804 WR_PRE = 0x1
3854 22:55:40.504901 WR_PST = 0x0
3855 22:55:40.504983 DBI_WR = 0x0
3856 22:55:40.508414 DBI_RD = 0x0
3857 22:55:40.508521 OTF = 0x1
3858 22:55:40.511763 ===================================
3859 22:55:40.515298 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3860 22:55:40.521990 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3861 22:55:40.524708 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3862 22:55:40.528462 ===================================
3863 22:55:40.531321 LPDDR4 DRAM CONFIGURATION
3864 22:55:40.534861 ===================================
3865 22:55:40.534946 EX_ROW_EN[0] = 0x10
3866 22:55:40.538111 EX_ROW_EN[1] = 0x0
3867 22:55:40.538193 LP4Y_EN = 0x0
3868 22:55:40.541537 WORK_FSP = 0x0
3869 22:55:40.541620 WL = 0x2
3870 22:55:40.544762 RL = 0x2
3871 22:55:40.544886 BL = 0x2
3872 22:55:40.547952 RPST = 0x0
3873 22:55:40.548034 RD_PRE = 0x0
3874 22:55:40.551350 WR_PRE = 0x1
3875 22:55:40.551432 WR_PST = 0x0
3876 22:55:40.554633 DBI_WR = 0x0
3877 22:55:40.558770 DBI_RD = 0x0
3878 22:55:40.558853 OTF = 0x1
3879 22:55:40.561119 ===================================
3880 22:55:40.567794 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3881 22:55:40.571550 nWR fixed to 30
3882 22:55:40.574434 [ModeRegInit_LP4] CH0 RK0
3883 22:55:40.574518 [ModeRegInit_LP4] CH0 RK1
3884 22:55:40.577698 [ModeRegInit_LP4] CH1 RK0
3885 22:55:40.581712 [ModeRegInit_LP4] CH1 RK1
3886 22:55:40.581794 match AC timing 17
3887 22:55:40.587830 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3888 22:55:40.591070 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3889 22:55:40.594316 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3890 22:55:40.601199 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3891 22:55:40.604465 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3892 22:55:40.604548 ==
3893 22:55:40.607700 Dram Type= 6, Freq= 0, CH_0, rank 0
3894 22:55:40.610973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3895 22:55:40.611056 ==
3896 22:55:40.617701 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3897 22:55:40.624734 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3898 22:55:40.627594 [CA 0] Center 36 (6~67) winsize 62
3899 22:55:40.630969 [CA 1] Center 36 (6~67) winsize 62
3900 22:55:40.634106 [CA 2] Center 34 (4~65) winsize 62
3901 22:55:40.637817 [CA 3] Center 34 (4~65) winsize 62
3902 22:55:40.640729 [CA 4] Center 34 (3~65) winsize 63
3903 22:55:40.644326 [CA 5] Center 33 (2~64) winsize 63
3904 22:55:40.644409
3905 22:55:40.647313 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3906 22:55:40.647396
3907 22:55:40.650726 [CATrainingPosCal] consider 1 rank data
3908 22:55:40.653882 u2DelayCellTimex100 = 270/100 ps
3909 22:55:40.657224 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3910 22:55:40.660871 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3911 22:55:40.663829 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3912 22:55:40.667788 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3913 22:55:40.673707 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3914 22:55:40.677114 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3915 22:55:40.677199
3916 22:55:40.680546 CA PerBit enable=1, Macro0, CA PI delay=33
3917 22:55:40.680630
3918 22:55:40.683563 [CBTSetCACLKResult] CA Dly = 33
3919 22:55:40.683646 CS Dly: 4 (0~35)
3920 22:55:40.683710 ==
3921 22:55:40.687907 Dram Type= 6, Freq= 0, CH_0, rank 1
3922 22:55:40.693588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3923 22:55:40.693672 ==
3924 22:55:40.697405 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3925 22:55:40.703525 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3926 22:55:40.707081 [CA 0] Center 36 (6~67) winsize 62
3927 22:55:40.710174 [CA 1] Center 36 (6~67) winsize 62
3928 22:55:40.713872 [CA 2] Center 35 (4~66) winsize 63
3929 22:55:40.716688 [CA 3] Center 35 (4~66) winsize 63
3930 22:55:40.720325 [CA 4] Center 34 (3~65) winsize 63
3931 22:55:40.723432 [CA 5] Center 33 (3~64) winsize 62
3932 22:55:40.723515
3933 22:55:40.727034 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3934 22:55:40.727116
3935 22:55:40.730363 [CATrainingPosCal] consider 2 rank data
3936 22:55:40.733490 u2DelayCellTimex100 = 270/100 ps
3937 22:55:40.736601 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3938 22:55:40.740012 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3939 22:55:40.746838 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3940 22:55:40.750221 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3941 22:55:40.753536 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3942 22:55:40.756664 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3943 22:55:40.756748
3944 22:55:40.760234 CA PerBit enable=1, Macro0, CA PI delay=33
3945 22:55:40.760316
3946 22:55:40.763507 [CBTSetCACLKResult] CA Dly = 33
3947 22:55:40.763589 CS Dly: 5 (0~37)
3948 22:55:40.763654
3949 22:55:40.766739 ----->DramcWriteLeveling(PI) begin...
3950 22:55:40.770218 ==
3951 22:55:40.770300 Dram Type= 6, Freq= 0, CH_0, rank 0
3952 22:55:40.776684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3953 22:55:40.776781 ==
3954 22:55:40.780096 Write leveling (Byte 0): 33 => 33
3955 22:55:40.783598 Write leveling (Byte 1): 29 => 29
3956 22:55:40.786545 DramcWriteLeveling(PI) end<-----
3957 22:55:40.786633
3958 22:55:40.786700 ==
3959 22:55:40.789857 Dram Type= 6, Freq= 0, CH_0, rank 0
3960 22:55:40.793333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3961 22:55:40.793417 ==
3962 22:55:40.796279 [Gating] SW mode calibration
3963 22:55:40.803189 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3964 22:55:40.809712 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3965 22:55:40.812720 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3966 22:55:40.816227 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3967 22:55:40.823240 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3968 22:55:40.825936 0 9 12 | B1->B0 | 3333 2f2f | 1 0 | (1 1) (0 1)
3969 22:55:40.829822 0 9 16 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
3970 22:55:40.835809 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3971 22:55:40.839697 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3972 22:55:40.842530 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3973 22:55:40.849321 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3974 22:55:40.852725 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3975 22:55:40.856025 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3976 22:55:40.862284 0 10 12 | B1->B0 | 2525 3737 | 0 0 | (0 0) (0 0)
3977 22:55:40.865717 0 10 16 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
3978 22:55:40.869131 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3979 22:55:40.875715 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3980 22:55:40.878931 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3981 22:55:40.882322 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3982 22:55:40.889040 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3983 22:55:40.892407 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 22:55:40.895707 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3985 22:55:40.901940 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3986 22:55:40.905786 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 22:55:40.908989 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 22:55:40.911762 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 22:55:40.918776 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 22:55:40.922478 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 22:55:40.925081 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 22:55:40.931972 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 22:55:40.935245 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 22:55:40.938466 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 22:55:40.945333 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 22:55:40.948657 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 22:55:40.951798 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 22:55:40.958305 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 22:55:40.961417 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 22:55:40.965075 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4001 22:55:40.971269 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4002 22:55:40.974600 Total UI for P1: 0, mck2ui 16
4003 22:55:40.978463 best dqsien dly found for B0: ( 0, 13, 12)
4004 22:55:40.981320 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 22:55:40.985152 Total UI for P1: 0, mck2ui 16
4006 22:55:40.987884 best dqsien dly found for B1: ( 0, 13, 14)
4007 22:55:40.992003 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4008 22:55:40.995033 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4009 22:55:40.995165
4010 22:55:40.997985 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4011 22:55:41.004815 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4012 22:55:41.004901 [Gating] SW calibration Done
4013 22:55:41.004987 ==
4014 22:55:41.007744 Dram Type= 6, Freq= 0, CH_0, rank 0
4015 22:55:41.014101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4016 22:55:41.014187 ==
4017 22:55:41.014272 RX Vref Scan: 0
4018 22:55:41.014352
4019 22:55:41.017544 RX Vref 0 -> 0, step: 1
4020 22:55:41.017629
4021 22:55:41.020705 RX Delay -230 -> 252, step: 16
4022 22:55:41.024616 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4023 22:55:41.027637 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4024 22:55:41.034437 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4025 22:55:41.037795 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4026 22:55:41.040865 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4027 22:55:41.044152 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4028 22:55:41.047717 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4029 22:55:41.054028 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4030 22:55:41.057177 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4031 22:55:41.060664 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4032 22:55:41.064277 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4033 22:55:41.070494 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4034 22:55:41.073842 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4035 22:55:41.077142 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4036 22:55:41.080568 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4037 22:55:41.087072 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4038 22:55:41.087173 ==
4039 22:55:41.090346 Dram Type= 6, Freq= 0, CH_0, rank 0
4040 22:55:41.093597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4041 22:55:41.093681 ==
4042 22:55:41.093747 DQS Delay:
4043 22:55:41.096762 DQS0 = 0, DQS1 = 0
4044 22:55:41.096883 DQM Delay:
4045 22:55:41.100374 DQM0 = 52, DQM1 = 40
4046 22:55:41.100457 DQ Delay:
4047 22:55:41.103549 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4048 22:55:41.107033 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4049 22:55:41.110065 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4050 22:55:41.113912 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4051 22:55:41.113996
4052 22:55:41.114061
4053 22:55:41.114121 ==
4054 22:55:41.116667 Dram Type= 6, Freq= 0, CH_0, rank 0
4055 22:55:41.119996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4056 22:55:41.120080 ==
4057 22:55:41.120146
4058 22:55:41.123474
4059 22:55:41.123557 TX Vref Scan disable
4060 22:55:41.126847 == TX Byte 0 ==
4061 22:55:41.130735 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4062 22:55:41.133809 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4063 22:55:41.136474 == TX Byte 1 ==
4064 22:55:41.139975 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4065 22:55:41.143421 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4066 22:55:41.146465 ==
4067 22:55:41.146548 Dram Type= 6, Freq= 0, CH_0, rank 0
4068 22:55:41.153482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4069 22:55:41.153567 ==
4070 22:55:41.153633
4071 22:55:41.153695
4072 22:55:41.156240 TX Vref Scan disable
4073 22:55:41.156324 == TX Byte 0 ==
4074 22:55:41.163498 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4075 22:55:41.166255 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4076 22:55:41.166342 == TX Byte 1 ==
4077 22:55:41.172796 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4078 22:55:41.176176 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4079 22:55:41.176260
4080 22:55:41.176326 [DATLAT]
4081 22:55:41.179435 Freq=600, CH0 RK0
4082 22:55:41.179518
4083 22:55:41.179584 DATLAT Default: 0x9
4084 22:55:41.182690 0, 0xFFFF, sum = 0
4085 22:55:41.182774 1, 0xFFFF, sum = 0
4086 22:55:41.186335 2, 0xFFFF, sum = 0
4087 22:55:41.189517 3, 0xFFFF, sum = 0
4088 22:55:41.189602 4, 0xFFFF, sum = 0
4089 22:55:41.192716 5, 0xFFFF, sum = 0
4090 22:55:41.192837 6, 0xFFFF, sum = 0
4091 22:55:41.196096 7, 0xFFFF, sum = 0
4092 22:55:41.196181 8, 0x0, sum = 1
4093 22:55:41.199353 9, 0x0, sum = 2
4094 22:55:41.199438 10, 0x0, sum = 3
4095 22:55:41.199507 11, 0x0, sum = 4
4096 22:55:41.202547 best_step = 9
4097 22:55:41.202632
4098 22:55:41.202699 ==
4099 22:55:41.206198 Dram Type= 6, Freq= 0, CH_0, rank 0
4100 22:55:41.209553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4101 22:55:41.209722 ==
4102 22:55:41.212827 RX Vref Scan: 1
4103 22:55:41.212993
4104 22:55:41.213069 RX Vref 0 -> 0, step: 1
4105 22:55:41.216043
4106 22:55:41.216210 RX Delay -179 -> 252, step: 8
4107 22:55:41.216291
4108 22:55:41.219808 Set Vref, RX VrefLevel [Byte0]: 57
4109 22:55:41.222691 [Byte1]: 49
4110 22:55:41.227503
4111 22:55:41.232718 Final RX Vref Byte 0 = 57 to rank0
4112 22:55:41.232926 Final RX Vref Byte 1 = 49 to rank0
4113 22:55:41.233209 Final RX Vref Byte 0 = 57 to rank1
4114 22:55:41.236742 Final RX Vref Byte 1 = 49 to rank1==
4115 22:55:41.240377 Dram Type= 6, Freq= 0, CH_0, rank 0
4116 22:55:41.247455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4117 22:55:41.247633 ==
4118 22:55:41.247720 DQS Delay:
4119 22:55:41.250305 DQS0 = 0, DQS1 = 0
4120 22:55:41.250489 DQM Delay:
4121 22:55:41.250581 DQM0 = 49, DQM1 = 39
4122 22:55:41.253341 DQ Delay:
4123 22:55:41.256779 DQ0 =44, DQ1 =52, DQ2 =48, DQ3 =44
4124 22:55:41.259642 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =56
4125 22:55:41.263179 DQ8 =36, DQ9 =24, DQ10 =36, DQ11 =36
4126 22:55:41.266642 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =48
4127 22:55:41.266861
4128 22:55:41.266983
4129 22:55:41.273382 [DQSOSCAuto] RK0, (LSB)MR18= 0x5c56, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4130 22:55:41.276469 CH0 RK0: MR19=808, MR18=5C56
4131 22:55:41.283428 CH0_RK0: MR19=0x808, MR18=0x5C56, DQSOSC=392, MR23=63, INC=170, DEC=113
4132 22:55:41.283688
4133 22:55:41.286294 ----->DramcWriteLeveling(PI) begin...
4134 22:55:41.286508 ==
4135 22:55:41.289627 Dram Type= 6, Freq= 0, CH_0, rank 1
4136 22:55:41.292988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4137 22:55:41.293323 ==
4138 22:55:41.296569 Write leveling (Byte 0): 33 => 33
4139 22:55:41.299491 Write leveling (Byte 1): 29 => 29
4140 22:55:41.303029 DramcWriteLeveling(PI) end<-----
4141 22:55:41.303555
4142 22:55:41.303877 ==
4143 22:55:41.306173 Dram Type= 6, Freq= 0, CH_0, rank 1
4144 22:55:41.312646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4145 22:55:41.312961 ==
4146 22:55:41.313027 [Gating] SW mode calibration
4147 22:55:41.322164 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4148 22:55:41.325748 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4149 22:55:41.328980 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4150 22:55:41.335353 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4151 22:55:41.338836 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4152 22:55:41.342488 0 9 12 | B1->B0 | 3131 3333 | 0 0 | (0 0) (0 1)
4153 22:55:41.349127 0 9 16 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
4154 22:55:41.351859 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4155 22:55:41.355377 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4156 22:55:41.361455 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4157 22:55:41.365089 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4158 22:55:41.368513 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4159 22:55:41.375158 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4160 22:55:41.378394 0 10 12 | B1->B0 | 2e2e 3232 | 0 0 | (0 0) (0 0)
4161 22:55:41.381652 0 10 16 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
4162 22:55:41.388123 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4163 22:55:41.391468 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4164 22:55:41.394645 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4165 22:55:41.401294 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4166 22:55:41.404758 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4167 22:55:41.408072 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4168 22:55:41.414862 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4169 22:55:41.418142 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4170 22:55:41.421150 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4171 22:55:41.427766 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4172 22:55:41.431063 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 22:55:41.434173 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4174 22:55:41.440781 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 22:55:41.444270 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 22:55:41.447633 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 22:55:41.454377 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 22:55:41.458082 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 22:55:41.460561 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 22:55:41.467264 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 22:55:41.470638 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 22:55:41.473920 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 22:55:41.480704 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 22:55:41.484068 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4185 22:55:41.487252 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4186 22:55:41.490758 Total UI for P1: 0, mck2ui 16
4187 22:55:41.493920 best dqsien dly found for B1: ( 0, 13, 12)
4188 22:55:41.500509 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 22:55:41.500619 Total UI for P1: 0, mck2ui 16
4190 22:55:41.507183 best dqsien dly found for B0: ( 0, 13, 14)
4191 22:55:41.510402 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4192 22:55:41.513677 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4193 22:55:41.513760
4194 22:55:41.517619 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4195 22:55:41.520409 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4196 22:55:41.523711 [Gating] SW calibration Done
4197 22:55:41.523794 ==
4198 22:55:41.526908 Dram Type= 6, Freq= 0, CH_0, rank 1
4199 22:55:41.530255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4200 22:55:41.530364 ==
4201 22:55:41.533470 RX Vref Scan: 0
4202 22:55:41.533552
4203 22:55:41.533618 RX Vref 0 -> 0, step: 1
4204 22:55:41.536674
4205 22:55:41.536805 RX Delay -230 -> 252, step: 16
4206 22:55:41.543523 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4207 22:55:41.546985 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4208 22:55:41.550433 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4209 22:55:41.553617 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4210 22:55:41.560434 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4211 22:55:41.563230 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4212 22:55:41.566721 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4213 22:55:41.569796 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4214 22:55:41.573139 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4215 22:55:41.579965 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4216 22:55:41.583488 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4217 22:55:41.586474 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4218 22:55:41.589694 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4219 22:55:41.596653 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4220 22:55:41.599544 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4221 22:55:41.603284 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4222 22:55:41.603365 ==
4223 22:55:41.606818 Dram Type= 6, Freq= 0, CH_0, rank 1
4224 22:55:41.609842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4225 22:55:41.613397 ==
4226 22:55:41.613494 DQS Delay:
4227 22:55:41.613587 DQS0 = 0, DQS1 = 0
4228 22:55:41.616074 DQM Delay:
4229 22:55:41.616172 DQM0 = 49, DQM1 = 42
4230 22:55:41.619722 DQ Delay:
4231 22:55:41.619831 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =41
4232 22:55:41.622854 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4233 22:55:41.626319 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4234 22:55:41.629663 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4235 22:55:41.629774
4236 22:55:41.633287
4237 22:55:41.633377 ==
4238 22:55:41.636281 Dram Type= 6, Freq= 0, CH_0, rank 1
4239 22:55:41.640043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4240 22:55:41.640139 ==
4241 22:55:41.640272
4242 22:55:41.640369
4243 22:55:41.642942 TX Vref Scan disable
4244 22:55:41.643062 == TX Byte 0 ==
4245 22:55:41.649708 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4246 22:55:41.652617 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4247 22:55:41.652726 == TX Byte 1 ==
4248 22:55:41.659761 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4249 22:55:41.663047 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4250 22:55:41.663225 ==
4251 22:55:41.666381 Dram Type= 6, Freq= 0, CH_0, rank 1
4252 22:55:41.669748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4253 22:55:41.669934 ==
4254 22:55:41.670026
4255 22:55:41.670111
4256 22:55:41.673339 TX Vref Scan disable
4257 22:55:41.676438 == TX Byte 0 ==
4258 22:55:41.679432 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4259 22:55:41.682936 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4260 22:55:41.686166 == TX Byte 1 ==
4261 22:55:41.689365 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4262 22:55:41.696578 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4263 22:55:41.696896
4264 22:55:41.697096 [DATLAT]
4265 22:55:41.697262 Freq=600, CH0 RK1
4266 22:55:41.697409
4267 22:55:41.699555 DATLAT Default: 0x9
4268 22:55:41.699883 0, 0xFFFF, sum = 0
4269 22:55:41.702845 1, 0xFFFF, sum = 0
4270 22:55:41.706488 2, 0xFFFF, sum = 0
4271 22:55:41.706988 3, 0xFFFF, sum = 0
4272 22:55:41.709518 4, 0xFFFF, sum = 0
4273 22:55:41.709911 5, 0xFFFF, sum = 0
4274 22:55:41.713038 6, 0xFFFF, sum = 0
4275 22:55:41.713434 7, 0xFFFF, sum = 0
4276 22:55:41.716560 8, 0x0, sum = 1
4277 22:55:41.717094 9, 0x0, sum = 2
4278 22:55:41.717425 10, 0x0, sum = 3
4279 22:55:41.719614 11, 0x0, sum = 4
4280 22:55:41.720117 best_step = 9
4281 22:55:41.720431
4282 22:55:41.720718 ==
4283 22:55:41.722981 Dram Type= 6, Freq= 0, CH_0, rank 1
4284 22:55:41.729050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4285 22:55:41.729555 ==
4286 22:55:41.729892 RX Vref Scan: 0
4287 22:55:41.730181
4288 22:55:41.732572 RX Vref 0 -> 0, step: 1
4289 22:55:41.733033
4290 22:55:41.735567 RX Delay -163 -> 252, step: 8
4291 22:55:41.739246 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4292 22:55:41.745711 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4293 22:55:41.749055 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4294 22:55:41.752667 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4295 22:55:41.755769 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4296 22:55:41.758809 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4297 22:55:41.765796 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4298 22:55:41.768969 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4299 22:55:41.772516 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4300 22:55:41.775749 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4301 22:55:41.782192 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4302 22:55:41.785220 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4303 22:55:41.789044 iDelay=205, Bit 12, Center 44 (-99 ~ 188) 288
4304 22:55:41.792017 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280
4305 22:55:41.798729 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4306 22:55:41.801777 iDelay=205, Bit 15, Center 44 (-99 ~ 188) 288
4307 22:55:41.802207 ==
4308 22:55:41.805564 Dram Type= 6, Freq= 0, CH_0, rank 1
4309 22:55:41.809209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4310 22:55:41.809733 ==
4311 22:55:41.810075 DQS Delay:
4312 22:55:41.811884 DQS0 = 0, DQS1 = 0
4313 22:55:41.812403 DQM Delay:
4314 22:55:41.815369 DQM0 = 48, DQM1 = 40
4315 22:55:41.815888 DQ Delay:
4316 22:55:41.818588 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4317 22:55:41.821825 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =52
4318 22:55:41.825264 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4319 22:55:41.828847 DQ12 =44, DQ13 =48, DQ14 =52, DQ15 =44
4320 22:55:41.829366
4321 22:55:41.829704
4322 22:55:41.838354 [DQSOSCAuto] RK1, (LSB)MR18= 0x6432, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
4323 22:55:41.838879 CH0 RK1: MR19=808, MR18=6432
4324 22:55:41.844760 CH0_RK1: MR19=0x808, MR18=0x6432, DQSOSC=391, MR23=63, INC=171, DEC=114
4325 22:55:41.848068 [RxdqsGatingPostProcess] freq 600
4326 22:55:41.854951 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4327 22:55:41.858390 Pre-setting of DQS Precalculation
4328 22:55:41.861780 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4329 22:55:41.862306 ==
4330 22:55:41.864838 Dram Type= 6, Freq= 0, CH_1, rank 0
4331 22:55:41.871112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4332 22:55:41.871640 ==
4333 22:55:41.874665 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4334 22:55:41.881210 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4335 22:55:41.884980 [CA 0] Center 35 (5~66) winsize 62
4336 22:55:41.887814 [CA 1] Center 35 (5~66) winsize 62
4337 22:55:41.890837 [CA 2] Center 34 (4~65) winsize 62
4338 22:55:41.894648 [CA 3] Center 34 (3~65) winsize 63
4339 22:55:41.897700 [CA 4] Center 34 (3~65) winsize 63
4340 22:55:41.900964 [CA 5] Center 33 (3~64) winsize 62
4341 22:55:41.901497
4342 22:55:41.904348 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4343 22:55:41.904906
4344 22:55:41.907710 [CATrainingPosCal] consider 1 rank data
4345 22:55:41.911219 u2DelayCellTimex100 = 270/100 ps
4346 22:55:41.914607 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4347 22:55:41.918089 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4348 22:55:41.924699 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4349 22:55:41.927900 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4350 22:55:41.930868 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4351 22:55:41.934449 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4352 22:55:41.934872
4353 22:55:41.937445 CA PerBit enable=1, Macro0, CA PI delay=33
4354 22:55:41.937861
4355 22:55:41.941157 [CBTSetCACLKResult] CA Dly = 33
4356 22:55:41.941682 CS Dly: 5 (0~36)
4357 22:55:41.944235 ==
4358 22:55:41.947402 Dram Type= 6, Freq= 0, CH_1, rank 1
4359 22:55:41.950482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4360 22:55:41.950906 ==
4361 22:55:41.954317 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4362 22:55:41.960895 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4363 22:55:41.964616 [CA 0] Center 35 (5~66) winsize 62
4364 22:55:41.967608 [CA 1] Center 35 (5~66) winsize 62
4365 22:55:41.970998 [CA 2] Center 34 (4~65) winsize 62
4366 22:55:41.974642 [CA 3] Center 34 (4~65) winsize 62
4367 22:55:41.977606 [CA 4] Center 34 (4~65) winsize 62
4368 22:55:41.981084 [CA 5] Center 33 (3~64) winsize 62
4369 22:55:41.981598
4370 22:55:41.984622 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4371 22:55:41.985087
4372 22:55:41.987799 [CATrainingPosCal] consider 2 rank data
4373 22:55:41.991242 u2DelayCellTimex100 = 270/100 ps
4374 22:55:41.993948 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4375 22:55:42.001381 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4376 22:55:42.004303 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4377 22:55:42.007869 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4378 22:55:42.010767 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4379 22:55:42.013936 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4380 22:55:42.014477
4381 22:55:42.017610 CA PerBit enable=1, Macro0, CA PI delay=33
4382 22:55:42.018145
4383 22:55:42.020941 [CBTSetCACLKResult] CA Dly = 33
4384 22:55:42.024081 CS Dly: 4 (0~35)
4385 22:55:42.024622
4386 22:55:42.027459 ----->DramcWriteLeveling(PI) begin...
4387 22:55:42.028003 ==
4388 22:55:42.030569 Dram Type= 6, Freq= 0, CH_1, rank 0
4389 22:55:42.033564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4390 22:55:42.034000 ==
4391 22:55:42.036807 Write leveling (Byte 0): 29 => 29
4392 22:55:42.040647 Write leveling (Byte 1): 30 => 30
4393 22:55:42.044101 DramcWriteLeveling(PI) end<-----
4394 22:55:42.044639
4395 22:55:42.045053 ==
4396 22:55:42.047220 Dram Type= 6, Freq= 0, CH_1, rank 0
4397 22:55:42.050546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4398 22:55:42.051091 ==
4399 22:55:42.054736 [Gating] SW mode calibration
4400 22:55:42.061139 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4401 22:55:42.067050 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4402 22:55:42.070100 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4403 22:55:42.073475 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4404 22:55:42.080053 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4405 22:55:42.083570 0 9 12 | B1->B0 | 2f2f 2929 | 1 0 | (1 0) (1 1)
4406 22:55:42.086753 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4407 22:55:42.093229 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4408 22:55:42.096850 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4409 22:55:42.100239 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4410 22:55:42.106619 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4411 22:55:42.110312 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4412 22:55:42.113607 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4413 22:55:42.120396 0 10 12 | B1->B0 | 3f3f 3d3d | 0 1 | (0 0) (0 0)
4414 22:55:42.123265 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4415 22:55:42.126910 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4416 22:55:42.133264 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4417 22:55:42.136319 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4418 22:55:42.140047 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 22:55:42.146119 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4420 22:55:42.149380 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4421 22:55:42.153168 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4422 22:55:42.159812 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4423 22:55:42.163301 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 22:55:42.166215 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 22:55:42.172547 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 22:55:42.175913 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 22:55:42.179294 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 22:55:42.185983 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 22:55:42.189040 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 22:55:42.192562 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 22:55:42.198893 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 22:55:42.201978 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 22:55:42.205879 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 22:55:42.212290 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 22:55:42.215693 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 22:55:42.218643 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4437 22:55:42.225680 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4438 22:55:42.226223 Total UI for P1: 0, mck2ui 16
4439 22:55:42.232354 best dqsien dly found for B1: ( 0, 13, 10)
4440 22:55:42.235839 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 22:55:42.238496 Total UI for P1: 0, mck2ui 16
4442 22:55:42.242038 best dqsien dly found for B0: ( 0, 13, 10)
4443 22:55:42.245274 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4444 22:55:42.248873 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4445 22:55:42.249412
4446 22:55:42.252383 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4447 22:55:42.255251 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4448 22:55:42.258565 [Gating] SW calibration Done
4449 22:55:42.259099 ==
4450 22:55:42.262235 Dram Type= 6, Freq= 0, CH_1, rank 0
4451 22:55:42.265905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4452 22:55:42.268646 ==
4453 22:55:42.269214 RX Vref Scan: 0
4454 22:55:42.269563
4455 22:55:42.272034 RX Vref 0 -> 0, step: 1
4456 22:55:42.272570
4457 22:55:42.275012 RX Delay -230 -> 252, step: 16
4458 22:55:42.278473 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4459 22:55:42.281572 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4460 22:55:42.284750 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4461 22:55:42.291465 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4462 22:55:42.294918 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4463 22:55:42.298067 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4464 22:55:42.301765 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4465 22:55:42.304967 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4466 22:55:42.311675 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4467 22:55:42.314573 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4468 22:55:42.318245 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4469 22:55:42.321176 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4470 22:55:42.328113 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4471 22:55:42.331003 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4472 22:55:42.334331 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4473 22:55:42.338019 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4474 22:55:42.341109 ==
4475 22:55:42.341640 Dram Type= 6, Freq= 0, CH_1, rank 0
4476 22:55:42.347767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4477 22:55:42.348301 ==
4478 22:55:42.348649 DQS Delay:
4479 22:55:42.351171 DQS0 = 0, DQS1 = 0
4480 22:55:42.351701 DQM Delay:
4481 22:55:42.354489 DQM0 = 50, DQM1 = 42
4482 22:55:42.355016 DQ Delay:
4483 22:55:42.357734 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4484 22:55:42.360980 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4485 22:55:42.364020 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4486 22:55:42.367433 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =41
4487 22:55:42.367960
4488 22:55:42.368302
4489 22:55:42.368618 ==
4490 22:55:42.370847 Dram Type= 6, Freq= 0, CH_1, rank 0
4491 22:55:42.374273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4492 22:55:42.374807 ==
4493 22:55:42.375156
4494 22:55:42.375475
4495 22:55:42.377545 TX Vref Scan disable
4496 22:55:42.381116 == TX Byte 0 ==
4497 22:55:42.384158 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4498 22:55:42.387673 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4499 22:55:42.390546 == TX Byte 1 ==
4500 22:55:42.394042 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4501 22:55:42.396988 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4502 22:55:42.397433 ==
4503 22:55:42.400674 Dram Type= 6, Freq= 0, CH_1, rank 0
4504 22:55:42.406962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4505 22:55:42.407403 ==
4506 22:55:42.407748
4507 22:55:42.408064
4508 22:55:42.408366 TX Vref Scan disable
4509 22:55:42.411060 == TX Byte 0 ==
4510 22:55:42.414762 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4511 22:55:42.421340 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4512 22:55:42.421869 == TX Byte 1 ==
4513 22:55:42.424171 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4514 22:55:42.431111 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4515 22:55:42.431639
4516 22:55:42.431990 [DATLAT]
4517 22:55:42.432313 Freq=600, CH1 RK0
4518 22:55:42.432625
4519 22:55:42.434129 DATLAT Default: 0x9
4520 22:55:42.437107 0, 0xFFFF, sum = 0
4521 22:55:42.437593 1, 0xFFFF, sum = 0
4522 22:55:42.440918 2, 0xFFFF, sum = 0
4523 22:55:42.441442 3, 0xFFFF, sum = 0
4524 22:55:42.444121 4, 0xFFFF, sum = 0
4525 22:55:42.444656 5, 0xFFFF, sum = 0
4526 22:55:42.447670 6, 0xFFFF, sum = 0
4527 22:55:42.448200 7, 0xFFFF, sum = 0
4528 22:55:42.450565 8, 0x0, sum = 1
4529 22:55:42.451097 9, 0x0, sum = 2
4530 22:55:42.453855 10, 0x0, sum = 3
4531 22:55:42.454413 11, 0x0, sum = 4
4532 22:55:42.454773 best_step = 9
4533 22:55:42.455095
4534 22:55:42.457541 ==
4535 22:55:42.460835 Dram Type= 6, Freq= 0, CH_1, rank 0
4536 22:55:42.463751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4537 22:55:42.464284 ==
4538 22:55:42.464649 RX Vref Scan: 1
4539 22:55:42.465027
4540 22:55:42.467379 RX Vref 0 -> 0, step: 1
4541 22:55:42.467907
4542 22:55:42.470656 RX Delay -163 -> 252, step: 8
4543 22:55:42.471183
4544 22:55:42.473836 Set Vref, RX VrefLevel [Byte0]: 52
4545 22:55:42.476920 [Byte1]: 51
4546 22:55:42.477354
4547 22:55:42.480174 Final RX Vref Byte 0 = 52 to rank0
4548 22:55:42.483446 Final RX Vref Byte 1 = 51 to rank0
4549 22:55:42.486559 Final RX Vref Byte 0 = 52 to rank1
4550 22:55:42.490359 Final RX Vref Byte 1 = 51 to rank1==
4551 22:55:42.493300 Dram Type= 6, Freq= 0, CH_1, rank 0
4552 22:55:42.496983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4553 22:55:42.500215 ==
4554 22:55:42.500649 DQS Delay:
4555 22:55:42.501073 DQS0 = 0, DQS1 = 0
4556 22:55:42.503131 DQM Delay:
4557 22:55:42.503650 DQM0 = 48, DQM1 = 40
4558 22:55:42.506726 DQ Delay:
4559 22:55:42.510313 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4560 22:55:42.510839 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =44
4561 22:55:42.513549 DQ8 =28, DQ9 =28, DQ10 =48, DQ11 =32
4562 22:55:42.516571 DQ12 =52, DQ13 =44, DQ14 =44, DQ15 =48
4563 22:55:42.520063
4564 22:55:42.520589
4565 22:55:42.526802 [DQSOSCAuto] RK0, (LSB)MR18= 0x5077, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
4566 22:55:42.530187 CH1 RK0: MR19=808, MR18=5077
4567 22:55:42.536306 CH1_RK0: MR19=0x808, MR18=0x5077, DQSOSC=387, MR23=63, INC=175, DEC=116
4568 22:55:42.536861
4569 22:55:42.539531 ----->DramcWriteLeveling(PI) begin...
4570 22:55:42.539969 ==
4571 22:55:42.543087 Dram Type= 6, Freq= 0, CH_1, rank 1
4572 22:55:42.546446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4573 22:55:42.546975 ==
4574 22:55:42.549718 Write leveling (Byte 0): 28 => 28
4575 22:55:42.553194 Write leveling (Byte 1): 30 => 30
4576 22:55:42.556540 DramcWriteLeveling(PI) end<-----
4577 22:55:42.557133
4578 22:55:42.557486 ==
4579 22:55:42.559727 Dram Type= 6, Freq= 0, CH_1, rank 1
4580 22:55:42.563304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4581 22:55:42.563836 ==
4582 22:55:42.566420 [Gating] SW mode calibration
4583 22:55:42.573082 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4584 22:55:42.579922 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4585 22:55:42.583032 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4586 22:55:42.586077 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4587 22:55:42.592877 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4588 22:55:42.596182 0 9 12 | B1->B0 | 2a2a 3333 | 1 1 | (1 0) (0 0)
4589 22:55:42.600023 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4590 22:55:42.606203 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4591 22:55:42.609319 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4592 22:55:42.615555 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4593 22:55:42.618746 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4594 22:55:42.622333 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4595 22:55:42.629191 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4596 22:55:42.632664 0 10 12 | B1->B0 | 3f3f 2c2c | 0 1 | (0 0) (0 0)
4597 22:55:42.635998 0 10 16 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
4598 22:55:42.642353 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4599 22:55:42.645459 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4600 22:55:42.648867 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4601 22:55:42.652413 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4602 22:55:42.658918 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4603 22:55:42.662187 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4604 22:55:42.665302 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4605 22:55:42.672049 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4606 22:55:42.675170 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4607 22:55:42.679069 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 22:55:42.685253 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 22:55:42.688942 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 22:55:42.692064 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 22:55:42.698257 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 22:55:42.701332 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 22:55:42.705116 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 22:55:42.711700 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 22:55:42.715080 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 22:55:42.718392 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 22:55:42.724918 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 22:55:42.728133 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 22:55:42.731871 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4620 22:55:42.738185 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4621 22:55:42.741092 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 22:55:42.744922 Total UI for P1: 0, mck2ui 16
4623 22:55:42.748158 best dqsien dly found for B0: ( 0, 13, 10)
4624 22:55:42.752143 Total UI for P1: 0, mck2ui 16
4625 22:55:42.754730 best dqsien dly found for B1: ( 0, 13, 12)
4626 22:55:42.758207 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4627 22:55:42.761398 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4628 22:55:42.761831
4629 22:55:42.764489 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4630 22:55:42.768022 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4631 22:55:42.771569 [Gating] SW calibration Done
4632 22:55:42.772102 ==
4633 22:55:42.774250 Dram Type= 6, Freq= 0, CH_1, rank 1
4634 22:55:42.781777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4635 22:55:42.782312 ==
4636 22:55:42.782657 RX Vref Scan: 0
4637 22:55:42.782979
4638 22:55:42.784659 RX Vref 0 -> 0, step: 1
4639 22:55:42.785272
4640 22:55:42.787840 RX Delay -230 -> 252, step: 16
4641 22:55:42.791281 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4642 22:55:42.794351 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4643 22:55:42.797983 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4644 22:55:42.804351 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4645 22:55:42.807704 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4646 22:55:42.811088 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4647 22:55:42.814001 iDelay=218, Bit 6, Center 49 (-102 ~ 201) 304
4648 22:55:42.820593 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4649 22:55:42.824138 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4650 22:55:42.827290 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4651 22:55:42.830594 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4652 22:55:42.837164 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4653 22:55:42.840489 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4654 22:55:42.843906 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4655 22:55:42.847124 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4656 22:55:42.853770 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4657 22:55:42.854310 ==
4658 22:55:42.856975 Dram Type= 6, Freq= 0, CH_1, rank 1
4659 22:55:42.860430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4660 22:55:42.861002 ==
4661 22:55:42.861356 DQS Delay:
4662 22:55:42.863623 DQS0 = 0, DQS1 = 0
4663 22:55:42.864158 DQM Delay:
4664 22:55:42.866990 DQM0 = 48, DQM1 = 46
4665 22:55:42.867528 DQ Delay:
4666 22:55:42.870259 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4667 22:55:42.873377 DQ4 =49, DQ5 =57, DQ6 =49, DQ7 =49
4668 22:55:42.877214 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4669 22:55:42.879549 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4670 22:55:42.879982
4671 22:55:42.880319
4672 22:55:42.880635 ==
4673 22:55:42.883361 Dram Type= 6, Freq= 0, CH_1, rank 1
4674 22:55:42.886622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4675 22:55:42.889665 ==
4676 22:55:42.890199
4677 22:55:42.890539
4678 22:55:42.890857 TX Vref Scan disable
4679 22:55:42.892870 == TX Byte 0 ==
4680 22:55:42.896720 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4681 22:55:42.900466 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4682 22:55:42.902893 == TX Byte 1 ==
4683 22:55:42.906604 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4684 22:55:42.910109 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4685 22:55:42.912712 ==
4686 22:55:42.916985 Dram Type= 6, Freq= 0, CH_1, rank 1
4687 22:55:42.919950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4688 22:55:42.920485 ==
4689 22:55:42.920864
4690 22:55:42.921181
4691 22:55:42.922845 TX Vref Scan disable
4692 22:55:42.926111 == TX Byte 0 ==
4693 22:55:42.929225 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4694 22:55:42.932972 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4695 22:55:42.935693 == TX Byte 1 ==
4696 22:55:42.938957 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4697 22:55:42.942777 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4698 22:55:42.943343
4699 22:55:42.943695 [DATLAT]
4700 22:55:42.945713 Freq=600, CH1 RK1
4701 22:55:42.946235
4702 22:55:42.949517 DATLAT Default: 0x9
4703 22:55:42.949948 0, 0xFFFF, sum = 0
4704 22:55:42.952129 1, 0xFFFF, sum = 0
4705 22:55:42.952563 2, 0xFFFF, sum = 0
4706 22:55:42.955700 3, 0xFFFF, sum = 0
4707 22:55:42.956344 4, 0xFFFF, sum = 0
4708 22:55:42.958847 5, 0xFFFF, sum = 0
4709 22:55:42.959388 6, 0xFFFF, sum = 0
4710 22:55:42.962572 7, 0xFFFF, sum = 0
4711 22:55:42.963114 8, 0x0, sum = 1
4712 22:55:42.965448 9, 0x0, sum = 2
4713 22:55:42.965888 10, 0x0, sum = 3
4714 22:55:42.968872 11, 0x0, sum = 4
4715 22:55:42.969312 best_step = 9
4716 22:55:42.969654
4717 22:55:42.969973 ==
4718 22:55:42.971796 Dram Type= 6, Freq= 0, CH_1, rank 1
4719 22:55:42.975554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4720 22:55:42.976100 ==
4721 22:55:42.979252 RX Vref Scan: 0
4722 22:55:42.979797
4723 22:55:42.982309 RX Vref 0 -> 0, step: 1
4724 22:55:42.982844
4725 22:55:42.983190 RX Delay -163 -> 252, step: 8
4726 22:55:42.990272 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4727 22:55:42.993185 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4728 22:55:42.996678 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4729 22:55:43.000172 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4730 22:55:43.002863 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4731 22:55:43.009960 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4732 22:55:43.013339 iDelay=205, Bit 6, Center 52 (-91 ~ 196) 288
4733 22:55:43.016601 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4734 22:55:43.019647 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4735 22:55:43.023140 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4736 22:55:43.029604 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4737 22:55:43.033005 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4738 22:55:43.036328 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4739 22:55:43.039366 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4740 22:55:43.046479 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4741 22:55:43.049549 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4742 22:55:43.049987 ==
4743 22:55:43.053043 Dram Type= 6, Freq= 0, CH_1, rank 1
4744 22:55:43.056273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4745 22:55:43.056894 ==
4746 22:55:43.059566 DQS Delay:
4747 22:55:43.060101 DQS0 = 0, DQS1 = 0
4748 22:55:43.060449 DQM Delay:
4749 22:55:43.063101 DQM0 = 48, DQM1 = 43
4750 22:55:43.063639 DQ Delay:
4751 22:55:43.066689 DQ0 =56, DQ1 =40, DQ2 =40, DQ3 =44
4752 22:55:43.069616 DQ4 =48, DQ5 =60, DQ6 =52, DQ7 =48
4753 22:55:43.072994 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4754 22:55:43.076112 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =56
4755 22:55:43.076651
4756 22:55:43.077050
4757 22:55:43.085855 [DQSOSCAuto] RK1, (LSB)MR18= 0x5e24, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
4758 22:55:43.089364 CH1 RK1: MR19=808, MR18=5E24
4759 22:55:43.092559 CH1_RK1: MR19=0x808, MR18=0x5E24, DQSOSC=392, MR23=63, INC=170, DEC=113
4760 22:55:43.095546 [RxdqsGatingPostProcess] freq 600
4761 22:55:43.102655 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4762 22:55:43.105643 Pre-setting of DQS Precalculation
4763 22:55:43.109323 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4764 22:55:43.119646 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4765 22:55:43.125625 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4766 22:55:43.126169
4767 22:55:43.126591
4768 22:55:43.128601 [Calibration Summary] 1200 Mbps
4769 22:55:43.129170 CH 0, Rank 0
4770 22:55:43.132042 SW Impedance : PASS
4771 22:55:43.132583 DUTY Scan : NO K
4772 22:55:43.136046 ZQ Calibration : PASS
4773 22:55:43.138397 Jitter Meter : NO K
4774 22:55:43.139055 CBT Training : PASS
4775 22:55:43.141955 Write leveling : PASS
4776 22:55:43.145037 RX DQS gating : PASS
4777 22:55:43.145469 RX DQ/DQS(RDDQC) : PASS
4778 22:55:43.148461 TX DQ/DQS : PASS
4779 22:55:43.151768 RX DATLAT : PASS
4780 22:55:43.152294 RX DQ/DQS(Engine): PASS
4781 22:55:43.155140 TX OE : NO K
4782 22:55:43.155685 All Pass.
4783 22:55:43.156037
4784 22:55:43.158388 CH 0, Rank 1
4785 22:55:43.158915 SW Impedance : PASS
4786 22:55:43.161622 DUTY Scan : NO K
4787 22:55:43.165185 ZQ Calibration : PASS
4788 22:55:43.165717 Jitter Meter : NO K
4789 22:55:43.168378 CBT Training : PASS
4790 22:55:43.171678 Write leveling : PASS
4791 22:55:43.172206 RX DQS gating : PASS
4792 22:55:43.174921 RX DQ/DQS(RDDQC) : PASS
4793 22:55:43.178456 TX DQ/DQS : PASS
4794 22:55:43.178983 RX DATLAT : PASS
4795 22:55:43.181636 RX DQ/DQS(Engine): PASS
4796 22:55:43.182128 TX OE : NO K
4797 22:55:43.185381 All Pass.
4798 22:55:43.185907
4799 22:55:43.186252 CH 1, Rank 0
4800 22:55:43.187914 SW Impedance : PASS
4801 22:55:43.188343 DUTY Scan : NO K
4802 22:55:43.191707 ZQ Calibration : PASS
4803 22:55:43.194887 Jitter Meter : NO K
4804 22:55:43.195319 CBT Training : PASS
4805 22:55:43.197929 Write leveling : PASS
4806 22:55:43.201420 RX DQS gating : PASS
4807 22:55:43.201868 RX DQ/DQS(RDDQC) : PASS
4808 22:55:43.204830 TX DQ/DQS : PASS
4809 22:55:43.207651 RX DATLAT : PASS
4810 22:55:43.208089 RX DQ/DQS(Engine): PASS
4811 22:55:43.211300 TX OE : NO K
4812 22:55:43.211835 All Pass.
4813 22:55:43.212281
4814 22:55:43.214624 CH 1, Rank 1
4815 22:55:43.215063 SW Impedance : PASS
4816 22:55:43.217761 DUTY Scan : NO K
4817 22:55:43.221187 ZQ Calibration : PASS
4818 22:55:43.221724 Jitter Meter : NO K
4819 22:55:43.224835 CBT Training : PASS
4820 22:55:43.228106 Write leveling : PASS
4821 22:55:43.228646 RX DQS gating : PASS
4822 22:55:43.231402 RX DQ/DQS(RDDQC) : PASS
4823 22:55:43.234556 TX DQ/DQS : PASS
4824 22:55:43.235096 RX DATLAT : PASS
4825 22:55:43.237833 RX DQ/DQS(Engine): PASS
4826 22:55:43.238376 TX OE : NO K
4827 22:55:43.240827 All Pass.
4828 22:55:43.241259
4829 22:55:43.241600 DramC Write-DBI off
4830 22:55:43.244360 PER_BANK_REFRESH: Hybrid Mode
4831 22:55:43.247677 TX_TRACKING: ON
4832 22:55:43.254138 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4833 22:55:43.257505 [FAST_K] Save calibration result to emmc
4834 22:55:43.264105 dramc_set_vcore_voltage set vcore to 662500
4835 22:55:43.264651 Read voltage for 933, 3
4836 22:55:43.266995 Vio18 = 0
4837 22:55:43.267424 Vcore = 662500
4838 22:55:43.267765 Vdram = 0
4839 22:55:43.270944 Vddq = 0
4840 22:55:43.271468 Vmddr = 0
4841 22:55:43.273962 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4842 22:55:43.280590 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4843 22:55:43.283725 MEM_TYPE=3, freq_sel=17
4844 22:55:43.287075 sv_algorithm_assistance_LP4_1600
4845 22:55:43.290190 ============ PULL DRAM RESETB DOWN ============
4846 22:55:43.294021 ========== PULL DRAM RESETB DOWN end =========
4847 22:55:43.296918 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4848 22:55:43.300453 ===================================
4849 22:55:43.303753 LPDDR4 DRAM CONFIGURATION
4850 22:55:43.306603 ===================================
4851 22:55:43.310084 EX_ROW_EN[0] = 0x0
4852 22:55:43.310601 EX_ROW_EN[1] = 0x0
4853 22:55:43.313579 LP4Y_EN = 0x0
4854 22:55:43.314098 WORK_FSP = 0x0
4855 22:55:43.316752 WL = 0x3
4856 22:55:43.317310 RL = 0x3
4857 22:55:43.319951 BL = 0x2
4858 22:55:43.320473 RPST = 0x0
4859 22:55:43.323841 RD_PRE = 0x0
4860 22:55:43.327032 WR_PRE = 0x1
4861 22:55:43.327551 WR_PST = 0x0
4862 22:55:43.329925 DBI_WR = 0x0
4863 22:55:43.330452 DBI_RD = 0x0
4864 22:55:43.333496 OTF = 0x1
4865 22:55:43.336727 ===================================
4866 22:55:43.339659 ===================================
4867 22:55:43.340264 ANA top config
4868 22:55:43.343211 ===================================
4869 22:55:43.346389 DLL_ASYNC_EN = 0
4870 22:55:43.350285 ALL_SLAVE_EN = 1
4871 22:55:43.350816 NEW_RANK_MODE = 1
4872 22:55:43.353043 DLL_IDLE_MODE = 1
4873 22:55:43.356477 LP45_APHY_COMB_EN = 1
4874 22:55:43.359930 TX_ODT_DIS = 1
4875 22:55:43.360463 NEW_8X_MODE = 1
4876 22:55:43.362823 ===================================
4877 22:55:43.366895 ===================================
4878 22:55:43.369585 data_rate = 1866
4879 22:55:43.373065 CKR = 1
4880 22:55:43.376014 DQ_P2S_RATIO = 8
4881 22:55:43.379771 ===================================
4882 22:55:43.383755 CA_P2S_RATIO = 8
4883 22:55:43.386514 DQ_CA_OPEN = 0
4884 22:55:43.389954 DQ_SEMI_OPEN = 0
4885 22:55:43.390505 CA_SEMI_OPEN = 0
4886 22:55:43.392989 CA_FULL_RATE = 0
4887 22:55:43.395887 DQ_CKDIV4_EN = 1
4888 22:55:43.399492 CA_CKDIV4_EN = 1
4889 22:55:43.402958 CA_PREDIV_EN = 0
4890 22:55:43.406080 PH8_DLY = 0
4891 22:55:43.406544 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4892 22:55:43.409542 DQ_AAMCK_DIV = 4
4893 22:55:43.412457 CA_AAMCK_DIV = 4
4894 22:55:43.416462 CA_ADMCK_DIV = 4
4895 22:55:43.419282 DQ_TRACK_CA_EN = 0
4896 22:55:43.422899 CA_PICK = 933
4897 22:55:43.423433 CA_MCKIO = 933
4898 22:55:43.426160 MCKIO_SEMI = 0
4899 22:55:43.429262 PLL_FREQ = 3732
4900 22:55:43.432593 DQ_UI_PI_RATIO = 32
4901 22:55:43.435904 CA_UI_PI_RATIO = 0
4902 22:55:43.438911 ===================================
4903 22:55:43.442422 ===================================
4904 22:55:43.445938 memory_type:LPDDR4
4905 22:55:43.446467 GP_NUM : 10
4906 22:55:43.448869 SRAM_EN : 1
4907 22:55:43.449300 MD32_EN : 0
4908 22:55:43.451873 ===================================
4909 22:55:43.455747 [ANA_INIT] >>>>>>>>>>>>>>
4910 22:55:43.458586 <<<<<< [CONFIGURE PHASE]: ANA_TX
4911 22:55:43.462320 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4912 22:55:43.465047 ===================================
4913 22:55:43.468579 data_rate = 1866,PCW = 0X8f00
4914 22:55:43.471991 ===================================
4915 22:55:43.474924 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4916 22:55:43.481764 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4917 22:55:43.485349 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4918 22:55:43.491813 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4919 22:55:43.494893 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4920 22:55:43.498478 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4921 22:55:43.498912 [ANA_INIT] flow start
4922 22:55:43.501540 [ANA_INIT] PLL >>>>>>>>
4923 22:55:43.504879 [ANA_INIT] PLL <<<<<<<<
4924 22:55:43.507887 [ANA_INIT] MIDPI >>>>>>>>
4925 22:55:43.508324 [ANA_INIT] MIDPI <<<<<<<<
4926 22:55:43.511693 [ANA_INIT] DLL >>>>>>>>
4927 22:55:43.514835 [ANA_INIT] flow end
4928 22:55:43.518039 ============ LP4 DIFF to SE enter ============
4929 22:55:43.522040 ============ LP4 DIFF to SE exit ============
4930 22:55:43.524651 [ANA_INIT] <<<<<<<<<<<<<
4931 22:55:43.527996 [Flow] Enable top DCM control >>>>>
4932 22:55:43.531986 [Flow] Enable top DCM control <<<<<
4933 22:55:43.534921 Enable DLL master slave shuffle
4934 22:55:43.538011 ==============================================================
4935 22:55:43.541072 Gating Mode config
4936 22:55:43.548078 ==============================================================
4937 22:55:43.548603 Config description:
4938 22:55:43.558449 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4939 22:55:43.564298 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4940 22:55:43.568087 SELPH_MODE 0: By rank 1: By Phase
4941 22:55:43.574411 ==============================================================
4942 22:55:43.577268 GAT_TRACK_EN = 1
4943 22:55:43.581026 RX_GATING_MODE = 2
4944 22:55:43.584572 RX_GATING_TRACK_MODE = 2
4945 22:55:43.587444 SELPH_MODE = 1
4946 22:55:43.591370 PICG_EARLY_EN = 1
4947 22:55:43.594219 VALID_LAT_VALUE = 1
4948 22:55:43.597433 ==============================================================
4949 22:55:43.600878 Enter into Gating configuration >>>>
4950 22:55:43.604309 Exit from Gating configuration <<<<
4951 22:55:43.607706 Enter into DVFS_PRE_config >>>>>
4952 22:55:43.617575 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4953 22:55:43.620617 Exit from DVFS_PRE_config <<<<<
4954 22:55:43.624251 Enter into PICG configuration >>>>
4955 22:55:43.627684 Exit from PICG configuration <<<<
4956 22:55:43.630764 [RX_INPUT] configuration >>>>>
4957 22:55:43.634343 [RX_INPUT] configuration <<<<<
4958 22:55:43.640440 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4959 22:55:43.643807 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4960 22:55:43.650944 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4961 22:55:43.657382 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4962 22:55:43.664012 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4963 22:55:43.670425 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4964 22:55:43.673921 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4965 22:55:43.677330 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4966 22:55:43.680833 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4967 22:55:43.687091 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4968 22:55:43.690440 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4969 22:55:43.693650 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4970 22:55:43.696741 ===================================
4971 22:55:43.700689 LPDDR4 DRAM CONFIGURATION
4972 22:55:43.703499 ===================================
4973 22:55:43.707080 EX_ROW_EN[0] = 0x0
4974 22:55:43.707509 EX_ROW_EN[1] = 0x0
4975 22:55:43.710124 LP4Y_EN = 0x0
4976 22:55:43.710556 WORK_FSP = 0x0
4977 22:55:43.713364 WL = 0x3
4978 22:55:43.713889 RL = 0x3
4979 22:55:43.716875 BL = 0x2
4980 22:55:43.717401 RPST = 0x0
4981 22:55:43.720336 RD_PRE = 0x0
4982 22:55:43.720892 WR_PRE = 0x1
4983 22:55:43.723373 WR_PST = 0x0
4984 22:55:43.723906 DBI_WR = 0x0
4985 22:55:43.726805 DBI_RD = 0x0
4986 22:55:43.727331 OTF = 0x1
4987 22:55:43.730282 ===================================
4988 22:55:43.736712 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4989 22:55:43.739586 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4990 22:55:43.743245 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4991 22:55:43.746332 ===================================
4992 22:55:43.749503 LPDDR4 DRAM CONFIGURATION
4993 22:55:43.752934 ===================================
4994 22:55:43.756174 EX_ROW_EN[0] = 0x10
4995 22:55:43.756707 EX_ROW_EN[1] = 0x0
4996 22:55:43.759645 LP4Y_EN = 0x0
4997 22:55:43.760169 WORK_FSP = 0x0
4998 22:55:43.763275 WL = 0x3
4999 22:55:43.763802 RL = 0x3
5000 22:55:43.766080 BL = 0x2
5001 22:55:43.766607 RPST = 0x0
5002 22:55:43.769236 RD_PRE = 0x0
5003 22:55:43.769666 WR_PRE = 0x1
5004 22:55:43.773055 WR_PST = 0x0
5005 22:55:43.773576 DBI_WR = 0x0
5006 22:55:43.776241 DBI_RD = 0x0
5007 22:55:43.776754 OTF = 0x1
5008 22:55:43.779339 ===================================
5009 22:55:43.786013 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5010 22:55:43.790578 nWR fixed to 30
5011 22:55:43.794290 [ModeRegInit_LP4] CH0 RK0
5012 22:55:43.794729 [ModeRegInit_LP4] CH0 RK1
5013 22:55:43.797037 [ModeRegInit_LP4] CH1 RK0
5014 22:55:43.800728 [ModeRegInit_LP4] CH1 RK1
5015 22:55:43.801293 match AC timing 9
5016 22:55:43.807067 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5017 22:55:43.810620 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5018 22:55:43.813871 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5019 22:55:43.820356 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5020 22:55:43.823907 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5021 22:55:43.824442 ==
5022 22:55:43.827174 Dram Type= 6, Freq= 0, CH_0, rank 0
5023 22:55:43.830456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5024 22:55:43.830992 ==
5025 22:55:43.837421 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5026 22:55:43.843504 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5027 22:55:43.847022 [CA 0] Center 37 (7~68) winsize 62
5028 22:55:43.850377 [CA 1] Center 38 (8~69) winsize 62
5029 22:55:43.853125 [CA 2] Center 35 (5~65) winsize 61
5030 22:55:43.856700 [CA 3] Center 34 (4~65) winsize 62
5031 22:55:43.860179 [CA 4] Center 34 (4~64) winsize 61
5032 22:55:43.863436 [CA 5] Center 33 (3~64) winsize 62
5033 22:55:43.863976
5034 22:55:43.866724 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5035 22:55:43.867260
5036 22:55:43.869960 [CATrainingPosCal] consider 1 rank data
5037 22:55:43.873540 u2DelayCellTimex100 = 270/100 ps
5038 22:55:43.876094 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5039 22:55:43.879870 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5040 22:55:43.883129 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5041 22:55:43.886437 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5042 22:55:43.892719 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5043 22:55:43.896063 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5044 22:55:43.896493
5045 22:55:43.899600 CA PerBit enable=1, Macro0, CA PI delay=33
5046 22:55:43.900028
5047 22:55:43.902848 [CBTSetCACLKResult] CA Dly = 33
5048 22:55:43.903333 CS Dly: 6 (0~37)
5049 22:55:43.903684 ==
5050 22:55:43.905987 Dram Type= 6, Freq= 0, CH_0, rank 1
5051 22:55:43.912986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5052 22:55:43.913418 ==
5053 22:55:43.915860 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5054 22:55:43.922526 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5055 22:55:43.926030 [CA 0] Center 38 (7~69) winsize 63
5056 22:55:43.928875 [CA 1] Center 38 (8~69) winsize 62
5057 22:55:43.932821 [CA 2] Center 36 (6~66) winsize 61
5058 22:55:43.935589 [CA 3] Center 35 (5~66) winsize 62
5059 22:55:43.939035 [CA 4] Center 34 (4~65) winsize 62
5060 22:55:43.942621 [CA 5] Center 34 (4~64) winsize 61
5061 22:55:43.943142
5062 22:55:43.945654 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5063 22:55:43.946083
5064 22:55:43.949040 [CATrainingPosCal] consider 2 rank data
5065 22:55:43.952358 u2DelayCellTimex100 = 270/100 ps
5066 22:55:43.955394 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5067 22:55:43.962013 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5068 22:55:43.965389 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5069 22:55:43.968881 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5070 22:55:43.971836 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5071 22:55:43.975190 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5072 22:55:43.975623
5073 22:55:43.978703 CA PerBit enable=1, Macro0, CA PI delay=34
5074 22:55:43.979174
5075 22:55:43.981520 [CBTSetCACLKResult] CA Dly = 34
5076 22:55:43.985149 CS Dly: 7 (0~39)
5077 22:55:43.985581
5078 22:55:43.988270 ----->DramcWriteLeveling(PI) begin...
5079 22:55:43.988710 ==
5080 22:55:43.991689 Dram Type= 6, Freq= 0, CH_0, rank 0
5081 22:55:43.994996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5082 22:55:43.995529 ==
5083 22:55:43.998169 Write leveling (Byte 0): 35 => 35
5084 22:55:44.001553 Write leveling (Byte 1): 28 => 28
5085 22:55:44.004938 DramcWriteLeveling(PI) end<-----
5086 22:55:44.005371
5087 22:55:44.005712 ==
5088 22:55:44.008102 Dram Type= 6, Freq= 0, CH_0, rank 0
5089 22:55:44.011260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5090 22:55:44.011731 ==
5091 22:55:44.014804 [Gating] SW mode calibration
5092 22:55:44.021379 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5093 22:55:44.027944 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5094 22:55:44.031996 0 14 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5095 22:55:44.034619 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5096 22:55:44.041325 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5097 22:55:44.044652 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5098 22:55:44.047952 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5099 22:55:44.054273 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5100 22:55:44.057577 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
5101 22:55:44.061114 0 14 28 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5102 22:55:44.067653 0 15 0 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
5103 22:55:44.071162 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5104 22:55:44.074431 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5105 22:55:44.080929 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5106 22:55:44.084446 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5107 22:55:44.087283 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5108 22:55:44.093890 0 15 24 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
5109 22:55:44.097107 0 15 28 | B1->B0 | 2626 3f3f | 0 0 | (0 0) (1 1)
5110 22:55:44.101068 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5111 22:55:44.106913 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5112 22:55:44.110295 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5113 22:55:44.113607 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5114 22:55:44.120493 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5115 22:55:44.123814 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5116 22:55:44.127088 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5117 22:55:44.133733 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5118 22:55:44.137260 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5119 22:55:44.140525 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 22:55:44.147220 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 22:55:44.150660 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 22:55:44.153357 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 22:55:44.160475 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 22:55:44.163776 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 22:55:44.166910 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 22:55:44.173683 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 22:55:44.177326 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 22:55:44.180289 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 22:55:44.186870 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 22:55:44.190103 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 22:55:44.193548 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5132 22:55:44.200115 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5133 22:55:44.203323 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5134 22:55:44.206376 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 22:55:44.210106 Total UI for P1: 0, mck2ui 16
5136 22:55:44.213676 best dqsien dly found for B0: ( 1, 2, 24)
5137 22:55:44.216921 Total UI for P1: 0, mck2ui 16
5138 22:55:44.220052 best dqsien dly found for B1: ( 1, 2, 30)
5139 22:55:44.223446 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5140 22:55:44.226953 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5141 22:55:44.227448
5142 22:55:44.230103 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5143 22:55:44.236579 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5144 22:55:44.237214 [Gating] SW calibration Done
5145 22:55:44.237707 ==
5146 22:55:44.240113 Dram Type= 6, Freq= 0, CH_0, rank 0
5147 22:55:44.246904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5148 22:55:44.247456 ==
5149 22:55:44.247939 RX Vref Scan: 0
5150 22:55:44.248398
5151 22:55:44.249535 RX Vref 0 -> 0, step: 1
5152 22:55:44.250021
5153 22:55:44.253354 RX Delay -80 -> 252, step: 8
5154 22:55:44.256306 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5155 22:55:44.259775 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5156 22:55:44.263302 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5157 22:55:44.269617 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5158 22:55:44.273333 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5159 22:55:44.276842 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5160 22:55:44.279822 iDelay=208, Bit 6, Center 119 (32 ~ 207) 176
5161 22:55:44.283440 iDelay=208, Bit 7, Center 119 (32 ~ 207) 176
5162 22:55:44.286580 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5163 22:55:44.293467 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5164 22:55:44.296574 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5165 22:55:44.299881 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5166 22:55:44.303313 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5167 22:55:44.306041 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5168 22:55:44.309530 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5169 22:55:44.316339 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5170 22:55:44.316945 ==
5171 22:55:44.319996 Dram Type= 6, Freq= 0, CH_0, rank 0
5172 22:55:44.322980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5173 22:55:44.323585 ==
5174 22:55:44.324079 DQS Delay:
5175 22:55:44.326068 DQS0 = 0, DQS1 = 0
5176 22:55:44.326554 DQM Delay:
5177 22:55:44.329932 DQM0 = 107, DQM1 = 90
5178 22:55:44.330419 DQ Delay:
5179 22:55:44.332444 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =103
5180 22:55:44.336146 DQ4 =107, DQ5 =95, DQ6 =119, DQ7 =119
5181 22:55:44.339405 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5182 22:55:44.342445 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5183 22:55:44.342937
5184 22:55:44.343375
5185 22:55:44.343791 ==
5186 22:55:44.345601 Dram Type= 6, Freq= 0, CH_0, rank 0
5187 22:55:44.352519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5188 22:55:44.353267 ==
5189 22:55:44.353921
5190 22:55:44.354532
5191 22:55:44.355146 TX Vref Scan disable
5192 22:55:44.356142 == TX Byte 0 ==
5193 22:55:44.359261 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5194 22:55:44.362821 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5195 22:55:44.366252 == TX Byte 1 ==
5196 22:55:44.368996 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5197 22:55:44.375614 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5198 22:55:44.375895 ==
5199 22:55:44.378661 Dram Type= 6, Freq= 0, CH_0, rank 0
5200 22:55:44.382279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5201 22:55:44.382499 ==
5202 22:55:44.382705
5203 22:55:44.382899
5204 22:55:44.385278 TX Vref Scan disable
5205 22:55:44.385571 == TX Byte 0 ==
5206 22:55:44.391849 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5207 22:55:44.395332 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5208 22:55:44.398714 == TX Byte 1 ==
5209 22:55:44.401959 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5210 22:55:44.405529 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5211 22:55:44.405747
5212 22:55:44.405939 [DATLAT]
5213 22:55:44.408354 Freq=933, CH0 RK0
5214 22:55:44.408545
5215 22:55:44.408723 DATLAT Default: 0xd
5216 22:55:44.411737 0, 0xFFFF, sum = 0
5217 22:55:44.415227 1, 0xFFFF, sum = 0
5218 22:55:44.415399 2, 0xFFFF, sum = 0
5219 22:55:44.418131 3, 0xFFFF, sum = 0
5220 22:55:44.418286 4, 0xFFFF, sum = 0
5221 22:55:44.421383 5, 0xFFFF, sum = 0
5222 22:55:44.421527 6, 0xFFFF, sum = 0
5223 22:55:44.425008 7, 0xFFFF, sum = 0
5224 22:55:44.425150 8, 0xFFFF, sum = 0
5225 22:55:44.428049 9, 0xFFFF, sum = 0
5226 22:55:44.428187 10, 0x0, sum = 1
5227 22:55:44.431540 11, 0x0, sum = 2
5228 22:55:44.431680 12, 0x0, sum = 3
5229 22:55:44.434527 13, 0x0, sum = 4
5230 22:55:44.434667 best_step = 11
5231 22:55:44.434792
5232 22:55:44.434913 ==
5233 22:55:44.438472 Dram Type= 6, Freq= 0, CH_0, rank 0
5234 22:55:44.441248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5235 22:55:44.444669 ==
5236 22:55:44.444857 RX Vref Scan: 1
5237 22:55:44.444999
5238 22:55:44.447998 RX Vref 0 -> 0, step: 1
5239 22:55:44.448140
5240 22:55:44.448268 RX Delay -53 -> 252, step: 4
5241 22:55:44.451101
5242 22:55:44.451237 Set Vref, RX VrefLevel [Byte0]: 57
5243 22:55:44.454573 [Byte1]: 49
5244 22:55:44.459377
5245 22:55:44.459514 Final RX Vref Byte 0 = 57 to rank0
5246 22:55:44.463097 Final RX Vref Byte 1 = 49 to rank0
5247 22:55:44.466011 Final RX Vref Byte 0 = 57 to rank1
5248 22:55:44.469462 Final RX Vref Byte 1 = 49 to rank1==
5249 22:55:44.472688 Dram Type= 6, Freq= 0, CH_0, rank 0
5250 22:55:44.479116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5251 22:55:44.479257 ==
5252 22:55:44.479386 DQS Delay:
5253 22:55:44.482783 DQS0 = 0, DQS1 = 0
5254 22:55:44.482919 DQM Delay:
5255 22:55:44.483045 DQM0 = 108, DQM1 = 92
5256 22:55:44.486212 DQ Delay:
5257 22:55:44.489156 DQ0 =108, DQ1 =108, DQ2 =104, DQ3 =106
5258 22:55:44.492357 DQ4 =110, DQ5 =100, DQ6 =116, DQ7 =114
5259 22:55:44.495982 DQ8 =86, DQ9 =78, DQ10 =92, DQ11 =90
5260 22:55:44.499507 DQ12 =96, DQ13 =94, DQ14 =104, DQ15 =100
5261 22:55:44.499642
5262 22:55:44.499769
5263 22:55:44.505742 [DQSOSCAuto] RK0, (LSB)MR18= 0x211d, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
5264 22:55:44.509118 CH0 RK0: MR19=505, MR18=211D
5265 22:55:44.515655 CH0_RK0: MR19=0x505, MR18=0x211D, DQSOSC=411, MR23=63, INC=64, DEC=42
5266 22:55:44.515800
5267 22:55:44.518686 ----->DramcWriteLeveling(PI) begin...
5268 22:55:44.518827 ==
5269 22:55:44.522167 Dram Type= 6, Freq= 0, CH_0, rank 1
5270 22:55:44.528736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5271 22:55:44.528913 ==
5272 22:55:44.532298 Write leveling (Byte 0): 34 => 34
5273 22:55:44.532434 Write leveling (Byte 1): 30 => 30
5274 22:55:44.535202 DramcWriteLeveling(PI) end<-----
5275 22:55:44.535337
5276 22:55:44.535462 ==
5277 22:55:44.539029 Dram Type= 6, Freq= 0, CH_0, rank 1
5278 22:55:44.545506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5279 22:55:44.545659 ==
5280 22:55:44.548391 [Gating] SW mode calibration
5281 22:55:44.555158 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5282 22:55:44.558303 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5283 22:55:44.565025 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5284 22:55:44.568144 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5285 22:55:44.571615 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5286 22:55:44.578192 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5287 22:55:44.581412 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5288 22:55:44.584507 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5289 22:55:44.591244 0 14 24 | B1->B0 | 3333 3131 | 1 0 | (1 1) (0 0)
5290 22:55:44.594510 0 14 28 | B1->B0 | 2d2d 2424 | 1 1 | (1 0) (1 0)
5291 22:55:44.597885 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5292 22:55:44.604400 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5293 22:55:44.607805 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5294 22:55:44.611431 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5295 22:55:44.617778 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5296 22:55:44.620976 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5297 22:55:44.624172 0 15 24 | B1->B0 | 2727 2e2e | 0 1 | (1 1) (1 1)
5298 22:55:44.631136 0 15 28 | B1->B0 | 3b3b 4444 | 0 0 | (0 0) (0 0)
5299 22:55:44.634194 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5300 22:55:44.637496 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5301 22:55:44.644055 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5302 22:55:44.647224 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5303 22:55:44.650450 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5304 22:55:44.657409 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5305 22:55:44.660416 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5306 22:55:44.664070 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5307 22:55:44.670404 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5308 22:55:44.673752 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5309 22:55:44.676674 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5310 22:55:44.683693 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 22:55:44.687177 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 22:55:44.690320 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 22:55:44.697096 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 22:55:44.700354 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 22:55:44.703594 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 22:55:44.710357 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 22:55:44.713746 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 22:55:44.716966 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 22:55:44.723382 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 22:55:44.726727 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 22:55:44.730611 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5322 22:55:44.736569 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5323 22:55:44.736831 Total UI for P1: 0, mck2ui 16
5324 22:55:44.743126 best dqsien dly found for B1: ( 1, 2, 26)
5325 22:55:44.746765 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 22:55:44.749732 Total UI for P1: 0, mck2ui 16
5327 22:55:44.753296 best dqsien dly found for B0: ( 1, 2, 26)
5328 22:55:44.756568 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5329 22:55:44.760108 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5330 22:55:44.760594
5331 22:55:44.763573 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5332 22:55:44.766381 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5333 22:55:44.770594 [Gating] SW calibration Done
5334 22:55:44.771269 ==
5335 22:55:44.773196 Dram Type= 6, Freq= 0, CH_0, rank 1
5336 22:55:44.776527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5337 22:55:44.779695 ==
5338 22:55:44.780361 RX Vref Scan: 0
5339 22:55:44.781023
5340 22:55:44.783425 RX Vref 0 -> 0, step: 1
5341 22:55:44.784093
5342 22:55:44.786352 RX Delay -80 -> 252, step: 8
5343 22:55:44.790079 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5344 22:55:44.793368 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5345 22:55:44.796172 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5346 22:55:44.799833 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5347 22:55:44.802483 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5348 22:55:44.809288 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5349 22:55:44.812318 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5350 22:55:44.815697 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5351 22:55:44.819021 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5352 22:55:44.822233 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5353 22:55:44.828724 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5354 22:55:44.832369 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5355 22:55:44.835199 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5356 22:55:44.839520 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5357 22:55:44.841915 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5358 22:55:44.845192 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5359 22:55:44.848733 ==
5360 22:55:44.852182 Dram Type= 6, Freq= 0, CH_0, rank 1
5361 22:55:44.855615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5362 22:55:44.855716 ==
5363 22:55:44.855808 DQS Delay:
5364 22:55:44.858738 DQS0 = 0, DQS1 = 0
5365 22:55:44.858836 DQM Delay:
5366 22:55:44.862353 DQM0 = 104, DQM1 = 91
5367 22:55:44.862863 DQ Delay:
5368 22:55:44.865943 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5369 22:55:44.868821 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =111
5370 22:55:44.872024 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5371 22:55:44.875434 DQ12 =99, DQ13 =95, DQ14 =99, DQ15 =95
5372 22:55:44.876003
5373 22:55:44.876506
5374 22:55:44.877028 ==
5375 22:55:44.878520 Dram Type= 6, Freq= 0, CH_0, rank 1
5376 22:55:44.882051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5377 22:55:44.885306 ==
5378 22:55:44.885804
5379 22:55:44.886260
5380 22:55:44.886704 TX Vref Scan disable
5381 22:55:44.889176 == TX Byte 0 ==
5382 22:55:44.892038 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5383 22:55:44.895300 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5384 22:55:44.898486 == TX Byte 1 ==
5385 22:55:44.901671 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5386 22:55:44.905067 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5387 22:55:44.908720 ==
5388 22:55:44.909231 Dram Type= 6, Freq= 0, CH_0, rank 1
5389 22:55:44.915539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5390 22:55:44.916057 ==
5391 22:55:44.916404
5392 22:55:44.916716
5393 22:55:44.917936 TX Vref Scan disable
5394 22:55:44.918377 == TX Byte 0 ==
5395 22:55:44.924984 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5396 22:55:44.928242 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5397 22:55:44.928673 == TX Byte 1 ==
5398 22:55:44.934455 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5399 22:55:44.937686 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5400 22:55:44.938127
5401 22:55:44.938470 [DATLAT]
5402 22:55:44.940994 Freq=933, CH0 RK1
5403 22:55:44.941459
5404 22:55:44.941816 DATLAT Default: 0xb
5405 22:55:44.944193 0, 0xFFFF, sum = 0
5406 22:55:44.944626 1, 0xFFFF, sum = 0
5407 22:55:44.948008 2, 0xFFFF, sum = 0
5408 22:55:44.950923 3, 0xFFFF, sum = 0
5409 22:55:44.951468 4, 0xFFFF, sum = 0
5410 22:55:44.954201 5, 0xFFFF, sum = 0
5411 22:55:44.954635 6, 0xFFFF, sum = 0
5412 22:55:44.957807 7, 0xFFFF, sum = 0
5413 22:55:44.958241 8, 0xFFFF, sum = 0
5414 22:55:44.961171 9, 0xFFFF, sum = 0
5415 22:55:44.961602 10, 0x0, sum = 1
5416 22:55:44.964691 11, 0x0, sum = 2
5417 22:55:44.965248 12, 0x0, sum = 3
5418 22:55:44.965603 13, 0x0, sum = 4
5419 22:55:44.968259 best_step = 11
5420 22:55:44.968683
5421 22:55:44.969074 ==
5422 22:55:44.971331 Dram Type= 6, Freq= 0, CH_0, rank 1
5423 22:55:44.974205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5424 22:55:44.974510 ==
5425 22:55:44.977140 RX Vref Scan: 0
5426 22:55:44.977368
5427 22:55:44.980756 RX Vref 0 -> 0, step: 1
5428 22:55:44.980984
5429 22:55:44.981133 RX Delay -53 -> 252, step: 4
5430 22:55:44.988199 iDelay=203, Bit 0, Center 104 (19 ~ 190) 172
5431 22:55:44.991449 iDelay=203, Bit 1, Center 106 (19 ~ 194) 176
5432 22:55:44.994855 iDelay=203, Bit 2, Center 104 (19 ~ 190) 172
5433 22:55:44.998015 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5434 22:55:45.001711 iDelay=203, Bit 4, Center 104 (19 ~ 190) 172
5435 22:55:45.008142 iDelay=203, Bit 5, Center 98 (11 ~ 186) 176
5436 22:55:45.011351 iDelay=203, Bit 6, Center 114 (27 ~ 202) 176
5437 22:55:45.014981 iDelay=203, Bit 7, Center 114 (31 ~ 198) 168
5438 22:55:45.018031 iDelay=203, Bit 8, Center 84 (-1 ~ 170) 172
5439 22:55:45.021483 iDelay=203, Bit 9, Center 80 (-1 ~ 162) 164
5440 22:55:45.028223 iDelay=203, Bit 10, Center 94 (11 ~ 178) 168
5441 22:55:45.031722 iDelay=203, Bit 11, Center 92 (11 ~ 174) 164
5442 22:55:45.034461 iDelay=203, Bit 12, Center 98 (15 ~ 182) 168
5443 22:55:45.038014 iDelay=203, Bit 13, Center 94 (11 ~ 178) 168
5444 22:55:45.041088 iDelay=203, Bit 14, Center 102 (19 ~ 186) 168
5445 22:55:45.047796 iDelay=203, Bit 15, Center 98 (15 ~ 182) 168
5446 22:55:45.047958 ==
5447 22:55:45.051187 Dram Type= 6, Freq= 0, CH_0, rank 1
5448 22:55:45.054494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5449 22:55:45.054627 ==
5450 22:55:45.054711 DQS Delay:
5451 22:55:45.057678 DQS0 = 0, DQS1 = 0
5452 22:55:45.057822 DQM Delay:
5453 22:55:45.061059 DQM0 = 105, DQM1 = 92
5454 22:55:45.061217 DQ Delay:
5455 22:55:45.065074 DQ0 =104, DQ1 =106, DQ2 =104, DQ3 =100
5456 22:55:45.067722 DQ4 =104, DQ5 =98, DQ6 =114, DQ7 =114
5457 22:55:45.071067 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =92
5458 22:55:45.075453 DQ12 =98, DQ13 =94, DQ14 =102, DQ15 =98
5459 22:55:45.075661
5460 22:55:45.075785
5461 22:55:45.084371 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c0c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 408 ps
5462 22:55:45.087615 CH0 RK1: MR19=505, MR18=2C0C
5463 22:55:45.090914 CH0_RK1: MR19=0x505, MR18=0x2C0C, DQSOSC=408, MR23=63, INC=65, DEC=43
5464 22:55:45.094564 [RxdqsGatingPostProcess] freq 933
5465 22:55:45.101270 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5466 22:55:45.104399 best DQS0 dly(2T, 0.5T) = (0, 10)
5467 22:55:45.107751 best DQS1 dly(2T, 0.5T) = (0, 10)
5468 22:55:45.111158 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5469 22:55:45.114533 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5470 22:55:45.118074 best DQS0 dly(2T, 0.5T) = (0, 10)
5471 22:55:45.120687 best DQS1 dly(2T, 0.5T) = (0, 10)
5472 22:55:45.124217 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5473 22:55:45.127657 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5474 22:55:45.130912 Pre-setting of DQS Precalculation
5475 22:55:45.134453 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5476 22:55:45.135031 ==
5477 22:55:45.137221 Dram Type= 6, Freq= 0, CH_1, rank 0
5478 22:55:45.140746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5479 22:55:45.141358 ==
5480 22:55:45.147165 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5481 22:55:45.154032 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5482 22:55:45.157265 [CA 0] Center 37 (7~68) winsize 62
5483 22:55:45.160380 [CA 1] Center 37 (7~68) winsize 62
5484 22:55:45.163949 [CA 2] Center 35 (6~65) winsize 60
5485 22:55:45.167425 [CA 3] Center 34 (4~65) winsize 62
5486 22:55:45.170306 [CA 4] Center 34 (4~65) winsize 62
5487 22:55:45.173615 [CA 5] Center 34 (4~64) winsize 61
5488 22:55:45.174210
5489 22:55:45.176669 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5490 22:55:45.177238
5491 22:55:45.180462 [CATrainingPosCal] consider 1 rank data
5492 22:55:45.183990 u2DelayCellTimex100 = 270/100 ps
5493 22:55:45.186600 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5494 22:55:45.190039 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5495 22:55:45.193637 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5496 22:55:45.196407 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5497 22:55:45.203299 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5498 22:55:45.206666 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5499 22:55:45.207145
5500 22:55:45.209889 CA PerBit enable=1, Macro0, CA PI delay=34
5501 22:55:45.210368
5502 22:55:45.213055 [CBTSetCACLKResult] CA Dly = 34
5503 22:55:45.213531 CS Dly: 6 (0~37)
5504 22:55:45.213910 ==
5505 22:55:45.216411 Dram Type= 6, Freq= 0, CH_1, rank 1
5506 22:55:45.223483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5507 22:55:45.224058 ==
5508 22:55:45.226663 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5509 22:55:45.233531 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5510 22:55:45.236572 [CA 0] Center 37 (7~68) winsize 62
5511 22:55:45.239671 [CA 1] Center 38 (8~69) winsize 62
5512 22:55:45.242691 [CA 2] Center 36 (6~66) winsize 61
5513 22:55:45.246186 [CA 3] Center 35 (5~65) winsize 61
5514 22:55:45.249360 [CA 4] Center 35 (5~65) winsize 61
5515 22:55:45.252559 [CA 5] Center 34 (5~64) winsize 60
5516 22:55:45.253081
5517 22:55:45.256431 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5518 22:55:45.257064
5519 22:55:45.259562 [CATrainingPosCal] consider 2 rank data
5520 22:55:45.262670 u2DelayCellTimex100 = 270/100 ps
5521 22:55:45.265805 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5522 22:55:45.272562 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5523 22:55:45.275721 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5524 22:55:45.278939 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5525 22:55:45.282630 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5526 22:55:45.285529 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5527 22:55:45.286010
5528 22:55:45.289332 CA PerBit enable=1, Macro0, CA PI delay=34
5529 22:55:45.289904
5530 22:55:45.292864 [CBTSetCACLKResult] CA Dly = 34
5531 22:55:45.293444 CS Dly: 7 (0~39)
5532 22:55:45.295599
5533 22:55:45.298920 ----->DramcWriteLeveling(PI) begin...
5534 22:55:45.299487 ==
5535 22:55:45.302177 Dram Type= 6, Freq= 0, CH_1, rank 0
5536 22:55:45.305215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5537 22:55:45.305694 ==
5538 22:55:45.308695 Write leveling (Byte 0): 28 => 28
5539 22:55:45.311832 Write leveling (Byte 1): 29 => 29
5540 22:55:45.315531 DramcWriteLeveling(PI) end<-----
5541 22:55:45.316108
5542 22:55:45.316490 ==
5543 22:55:45.318921 Dram Type= 6, Freq= 0, CH_1, rank 0
5544 22:55:45.322223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 22:55:45.322802 ==
5546 22:55:45.325646 [Gating] SW mode calibration
5547 22:55:45.332039 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5548 22:55:45.339131 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5549 22:55:45.342083 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5550 22:55:45.345215 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5551 22:55:45.352359 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5552 22:55:45.355648 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5553 22:55:45.358826 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5554 22:55:45.365211 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5555 22:55:45.368408 0 14 24 | B1->B0 | 3333 3030 | 0 0 | (0 0) (0 0)
5556 22:55:45.371978 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5557 22:55:45.378294 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5558 22:55:45.381760 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5559 22:55:45.385397 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5560 22:55:45.391479 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5561 22:55:45.394961 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5562 22:55:45.398371 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5563 22:55:45.404851 0 15 24 | B1->B0 | 2c2c 2d2d | 0 1 | (0 0) (0 0)
5564 22:55:45.408108 0 15 28 | B1->B0 | 4343 4343 | 0 0 | (0 0) (0 0)
5565 22:55:45.411257 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5566 22:55:45.418000 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5567 22:55:45.421329 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5568 22:55:45.425015 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5569 22:55:45.431335 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5570 22:55:45.434723 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5571 22:55:45.438067 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5572 22:55:45.444310 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 22:55:45.447939 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 22:55:45.451125 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 22:55:45.457821 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 22:55:45.461205 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 22:55:45.464876 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 22:55:45.471022 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 22:55:45.474279 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 22:55:45.477659 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 22:55:45.484400 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 22:55:45.487642 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 22:55:45.491741 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 22:55:45.497392 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 22:55:45.500470 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 22:55:45.504049 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 22:55:45.510628 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5588 22:55:45.514337 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5589 22:55:45.517437 Total UI for P1: 0, mck2ui 16
5590 22:55:45.520505 best dqsien dly found for B0: ( 1, 2, 24)
5591 22:55:45.523972 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 22:55:45.527223 Total UI for P1: 0, mck2ui 16
5593 22:55:45.530271 best dqsien dly found for B1: ( 1, 2, 28)
5594 22:55:45.533615 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5595 22:55:45.537157 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5596 22:55:45.537727
5597 22:55:45.540664 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5598 22:55:45.547210 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5599 22:55:45.547805 [Gating] SW calibration Done
5600 22:55:45.548189 ==
5601 22:55:45.550174 Dram Type= 6, Freq= 0, CH_1, rank 0
5602 22:55:45.556961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5603 22:55:45.557534 ==
5604 22:55:45.557915 RX Vref Scan: 0
5605 22:55:45.558279
5606 22:55:45.559750 RX Vref 0 -> 0, step: 1
5607 22:55:45.560224
5608 22:55:45.563586 RX Delay -80 -> 252, step: 8
5609 22:55:45.566631 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5610 22:55:45.570112 iDelay=208, Bit 1, Center 99 (16 ~ 183) 168
5611 22:55:45.573291 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5612 22:55:45.579860 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5613 22:55:45.583094 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5614 22:55:45.586708 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5615 22:55:45.589676 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5616 22:55:45.593057 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5617 22:55:45.599515 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5618 22:55:45.603101 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5619 22:55:45.606798 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5620 22:55:45.609820 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5621 22:55:45.613135 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5622 22:55:45.619494 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5623 22:55:45.622874 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5624 22:55:45.626003 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5625 22:55:45.626575 ==
5626 22:55:45.629404 Dram Type= 6, Freq= 0, CH_1, rank 0
5627 22:55:45.632703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5628 22:55:45.633215 ==
5629 22:55:45.635890 DQS Delay:
5630 22:55:45.636362 DQS0 = 0, DQS1 = 0
5631 22:55:45.639439 DQM Delay:
5632 22:55:45.640026 DQM0 = 103, DQM1 = 95
5633 22:55:45.640411 DQ Delay:
5634 22:55:45.642436 DQ0 =103, DQ1 =99, DQ2 =91, DQ3 =103
5635 22:55:45.645806 DQ4 =103, DQ5 =111, DQ6 =115, DQ7 =103
5636 22:55:45.649423 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =87
5637 22:55:45.655752 DQ12 =107, DQ13 =103, DQ14 =99, DQ15 =99
5638 22:55:45.656330
5639 22:55:45.656710
5640 22:55:45.657157 ==
5641 22:55:45.659260 Dram Type= 6, Freq= 0, CH_1, rank 0
5642 22:55:45.662305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5643 22:55:45.662884 ==
5644 22:55:45.663267
5645 22:55:45.663616
5646 22:55:45.665602 TX Vref Scan disable
5647 22:55:45.666076 == TX Byte 0 ==
5648 22:55:45.672681 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5649 22:55:45.676098 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5650 22:55:45.676674 == TX Byte 1 ==
5651 22:55:45.682776 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5652 22:55:45.685310 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5653 22:55:45.685806 ==
5654 22:55:45.689041 Dram Type= 6, Freq= 0, CH_1, rank 0
5655 22:55:45.692562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5656 22:55:45.693180 ==
5657 22:55:45.693568
5658 22:55:45.693924
5659 22:55:45.695760 TX Vref Scan disable
5660 22:55:45.699008 == TX Byte 0 ==
5661 22:55:45.702289 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5662 22:55:45.705238 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5663 22:55:45.708834 == TX Byte 1 ==
5664 22:55:45.711992 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5665 22:55:45.715191 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5666 22:55:45.715768
5667 22:55:45.718398 [DATLAT]
5668 22:55:45.718864 Freq=933, CH1 RK0
5669 22:55:45.719241
5670 22:55:45.721479 DATLAT Default: 0xd
5671 22:55:45.721948 0, 0xFFFF, sum = 0
5672 22:55:45.725340 1, 0xFFFF, sum = 0
5673 22:55:45.725923 2, 0xFFFF, sum = 0
5674 22:55:45.728529 3, 0xFFFF, sum = 0
5675 22:55:45.729160 4, 0xFFFF, sum = 0
5676 22:55:45.731804 5, 0xFFFF, sum = 0
5677 22:55:45.735000 6, 0xFFFF, sum = 0
5678 22:55:45.735581 7, 0xFFFF, sum = 0
5679 22:55:45.738242 8, 0xFFFF, sum = 0
5680 22:55:45.738724 9, 0xFFFF, sum = 0
5681 22:55:45.741460 10, 0x0, sum = 1
5682 22:55:45.742034 11, 0x0, sum = 2
5683 22:55:45.742414 12, 0x0, sum = 3
5684 22:55:45.744909 13, 0x0, sum = 4
5685 22:55:45.745388 best_step = 11
5686 22:55:45.745764
5687 22:55:45.748288 ==
5688 22:55:45.751588 Dram Type= 6, Freq= 0, CH_1, rank 0
5689 22:55:45.754946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5690 22:55:45.755522 ==
5691 22:55:45.755902 RX Vref Scan: 1
5692 22:55:45.756249
5693 22:55:45.758248 RX Vref 0 -> 0, step: 1
5694 22:55:45.758821
5695 22:55:45.761171 RX Delay -53 -> 252, step: 4
5696 22:55:45.761637
5697 22:55:45.764734 Set Vref, RX VrefLevel [Byte0]: 52
5698 22:55:45.768239 [Byte1]: 51
5699 22:55:45.768851
5700 22:55:45.771242 Final RX Vref Byte 0 = 52 to rank0
5701 22:55:45.774825 Final RX Vref Byte 1 = 51 to rank0
5702 22:55:45.777894 Final RX Vref Byte 0 = 52 to rank1
5703 22:55:45.781625 Final RX Vref Byte 1 = 51 to rank1==
5704 22:55:45.784729 Dram Type= 6, Freq= 0, CH_1, rank 0
5705 22:55:45.788286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5706 22:55:45.791312 ==
5707 22:55:45.791878 DQS Delay:
5708 22:55:45.792255 DQS0 = 0, DQS1 = 0
5709 22:55:45.794197 DQM Delay:
5710 22:55:45.794659 DQM0 = 104, DQM1 = 97
5711 22:55:45.797610 DQ Delay:
5712 22:55:45.800877 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =104
5713 22:55:45.804683 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =102
5714 22:55:45.807729 DQ8 =86, DQ9 =86, DQ10 =100, DQ11 =90
5715 22:55:45.810706 DQ12 =108, DQ13 =104, DQ14 =102, DQ15 =102
5716 22:55:45.811206
5717 22:55:45.811574
5718 22:55:45.817605 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c35, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
5719 22:55:45.820917 CH1 RK0: MR19=505, MR18=1C35
5720 22:55:45.827171 CH1_RK0: MR19=0x505, MR18=0x1C35, DQSOSC=405, MR23=63, INC=66, DEC=44
5721 22:55:45.827730
5722 22:55:45.830744 ----->DramcWriteLeveling(PI) begin...
5723 22:55:45.831329 ==
5724 22:55:45.834242 Dram Type= 6, Freq= 0, CH_1, rank 1
5725 22:55:45.837253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5726 22:55:45.837726 ==
5727 22:55:45.840626 Write leveling (Byte 0): 26 => 26
5728 22:55:45.843778 Write leveling (Byte 1): 26 => 26
5729 22:55:45.846947 DramcWriteLeveling(PI) end<-----
5730 22:55:45.847432
5731 22:55:45.847806 ==
5732 22:55:45.850467 Dram Type= 6, Freq= 0, CH_1, rank 1
5733 22:55:45.857138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5734 22:55:45.857731 ==
5735 22:55:45.858118 [Gating] SW mode calibration
5736 22:55:45.867202 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5737 22:55:45.870669 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5738 22:55:45.874191 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5739 22:55:45.880404 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5740 22:55:45.883995 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5741 22:55:45.887079 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5742 22:55:45.893713 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5743 22:55:45.897141 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5744 22:55:45.900221 0 14 24 | B1->B0 | 3030 3434 | 0 0 | (0 0) (0 1)
5745 22:55:45.906550 0 14 28 | B1->B0 | 2626 2929 | 0 0 | (1 0) (0 0)
5746 22:55:45.909948 0 15 0 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
5747 22:55:45.913320 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5748 22:55:45.919920 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5749 22:55:45.923347 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5750 22:55:45.926214 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5751 22:55:45.933132 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5752 22:55:45.936210 0 15 24 | B1->B0 | 2f2f 2727 | 0 1 | (0 0) (0 0)
5753 22:55:45.939509 0 15 28 | B1->B0 | 4141 3939 | 1 1 | (0 0) (0 0)
5754 22:55:45.946703 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5755 22:55:45.949803 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5756 22:55:45.953002 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5757 22:55:45.959223 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5758 22:55:45.962721 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5759 22:55:45.965873 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5760 22:55:45.972542 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5761 22:55:45.976294 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5762 22:55:45.978774 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5763 22:55:45.985326 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 22:55:45.988643 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 22:55:45.991825 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 22:55:45.998481 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 22:55:46.001799 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 22:55:46.005406 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 22:55:46.011740 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 22:55:46.015057 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 22:55:46.018648 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 22:55:46.024980 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 22:55:46.028430 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 22:55:46.031680 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 22:55:46.038405 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 22:55:46.041419 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5777 22:55:46.044654 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5778 22:55:46.048303 Total UI for P1: 0, mck2ui 16
5779 22:55:46.051391 best dqsien dly found for B1: ( 1, 2, 24)
5780 22:55:46.058145 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 22:55:46.058227 Total UI for P1: 0, mck2ui 16
5782 22:55:46.064990 best dqsien dly found for B0: ( 1, 2, 28)
5783 22:55:46.068041 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5784 22:55:46.071123 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5785 22:55:46.071207
5786 22:55:46.074499 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5787 22:55:46.077842 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5788 22:55:46.081139 [Gating] SW calibration Done
5789 22:55:46.081223 ==
5790 22:55:46.084656 Dram Type= 6, Freq= 0, CH_1, rank 1
5791 22:55:46.088110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5792 22:55:46.088185 ==
5793 22:55:46.090991 RX Vref Scan: 0
5794 22:55:46.091061
5795 22:55:46.091122 RX Vref 0 -> 0, step: 1
5796 22:55:46.094298
5797 22:55:46.094380 RX Delay -80 -> 252, step: 8
5798 22:55:46.101026 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5799 22:55:46.104071 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5800 22:55:46.107606 iDelay=208, Bit 2, Center 87 (0 ~ 175) 176
5801 22:55:46.110775 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5802 22:55:46.114025 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5803 22:55:46.117322 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5804 22:55:46.124235 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5805 22:55:46.127378 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5806 22:55:46.130610 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5807 22:55:46.133701 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5808 22:55:46.137503 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5809 22:55:46.140739 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5810 22:55:46.147089 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5811 22:55:46.150754 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5812 22:55:46.153686 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5813 22:55:46.157233 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5814 22:55:46.157308 ==
5815 22:55:46.160285 Dram Type= 6, Freq= 0, CH_1, rank 1
5816 22:55:46.166947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5817 22:55:46.167024 ==
5818 22:55:46.167088 DQS Delay:
5819 22:55:46.170764 DQS0 = 0, DQS1 = 0
5820 22:55:46.170839 DQM Delay:
5821 22:55:46.170909 DQM0 = 102, DQM1 = 95
5822 22:55:46.173677 DQ Delay:
5823 22:55:46.176840 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =99
5824 22:55:46.180163 DQ4 =103, DQ5 =115, DQ6 =111, DQ7 =99
5825 22:55:46.183531 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5826 22:55:46.186501 DQ12 =103, DQ13 =99, DQ14 =103, DQ15 =103
5827 22:55:46.186585
5828 22:55:46.186651
5829 22:55:46.186713 ==
5830 22:55:46.190100 Dram Type= 6, Freq= 0, CH_1, rank 1
5831 22:55:46.193203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5832 22:55:46.193286 ==
5833 22:55:46.193352
5834 22:55:46.193412
5835 22:55:46.196559 TX Vref Scan disable
5836 22:55:46.199982 == TX Byte 0 ==
5837 22:55:46.203548 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5838 22:55:46.206422 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5839 22:55:46.209939 == TX Byte 1 ==
5840 22:55:46.212925 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5841 22:55:46.216388 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5842 22:55:46.216472 ==
5843 22:55:46.219746 Dram Type= 6, Freq= 0, CH_1, rank 1
5844 22:55:46.226206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5845 22:55:46.226290 ==
5846 22:55:46.226357
5847 22:55:46.226416
5848 22:55:46.226475 TX Vref Scan disable
5849 22:55:46.230614 == TX Byte 0 ==
5850 22:55:46.233961 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5851 22:55:46.240346 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5852 22:55:46.240429 == TX Byte 1 ==
5853 22:55:46.243768 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5854 22:55:46.250404 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5855 22:55:46.250491
5856 22:55:46.250557 [DATLAT]
5857 22:55:46.250619 Freq=933, CH1 RK1
5858 22:55:46.250748
5859 22:55:46.253555 DATLAT Default: 0xb
5860 22:55:46.253638 0, 0xFFFF, sum = 0
5861 22:55:46.256659 1, 0xFFFF, sum = 0
5862 22:55:46.259791 2, 0xFFFF, sum = 0
5863 22:55:46.259875 3, 0xFFFF, sum = 0
5864 22:55:46.263319 4, 0xFFFF, sum = 0
5865 22:55:46.263404 5, 0xFFFF, sum = 0
5866 22:55:46.266577 6, 0xFFFF, sum = 0
5867 22:55:46.266668 7, 0xFFFF, sum = 0
5868 22:55:46.269947 8, 0xFFFF, sum = 0
5869 22:55:46.270112 9, 0xFFFF, sum = 0
5870 22:55:46.273434 10, 0x0, sum = 1
5871 22:55:46.273552 11, 0x0, sum = 2
5872 22:55:46.276655 12, 0x0, sum = 3
5873 22:55:46.276740 13, 0x0, sum = 4
5874 22:55:46.276840 best_step = 11
5875 22:55:46.279707
5876 22:55:46.279789 ==
5877 22:55:46.283019 Dram Type= 6, Freq= 0, CH_1, rank 1
5878 22:55:46.286501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5879 22:55:46.286934 ==
5880 22:55:46.287273 RX Vref Scan: 0
5881 22:55:46.287592
5882 22:55:46.290017 RX Vref 0 -> 0, step: 1
5883 22:55:46.290447
5884 22:55:46.293275 RX Delay -53 -> 252, step: 4
5885 22:55:46.299908 iDelay=199, Bit 0, Center 110 (35 ~ 186) 152
5886 22:55:46.303078 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5887 22:55:46.306622 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5888 22:55:46.309891 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5889 22:55:46.313094 iDelay=199, Bit 4, Center 108 (27 ~ 190) 164
5890 22:55:46.319883 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5891 22:55:46.323131 iDelay=199, Bit 6, Center 114 (35 ~ 194) 160
5892 22:55:46.326750 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5893 22:55:46.329936 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5894 22:55:46.333213 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5895 22:55:46.336267 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5896 22:55:46.342997 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5897 22:55:46.346588 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5898 22:55:46.349494 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5899 22:55:46.353042 iDelay=199, Bit 14, Center 104 (15 ~ 194) 180
5900 22:55:46.359536 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5901 22:55:46.360185 ==
5902 22:55:46.363046 Dram Type= 6, Freq= 0, CH_1, rank 1
5903 22:55:46.366399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 22:55:46.366971 ==
5905 22:55:46.367346 DQS Delay:
5906 22:55:46.369653 DQS0 = 0, DQS1 = 0
5907 22:55:46.370124 DQM Delay:
5908 22:55:46.372579 DQM0 = 105, DQM1 = 97
5909 22:55:46.373096 DQ Delay:
5910 22:55:46.375996 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =102
5911 22:55:46.379659 DQ4 =108, DQ5 =114, DQ6 =114, DQ7 =102
5912 22:55:46.382922 DQ8 =84, DQ9 =86, DQ10 =98, DQ11 =92
5913 22:55:46.386733 DQ12 =106, DQ13 =104, DQ14 =104, DQ15 =106
5914 22:55:46.387297
5915 22:55:46.387790
5916 22:55:46.396267 [DQSOSCAuto] RK1, (LSB)MR18= 0x20fe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
5917 22:55:46.396905 CH1 RK1: MR19=504, MR18=20FE
5918 22:55:46.402941 CH1_RK1: MR19=0x504, MR18=0x20FE, DQSOSC=411, MR23=63, INC=64, DEC=42
5919 22:55:46.406137 [RxdqsGatingPostProcess] freq 933
5920 22:55:46.412377 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5921 22:55:46.416029 best DQS0 dly(2T, 0.5T) = (0, 10)
5922 22:55:46.419207 best DQS1 dly(2T, 0.5T) = (0, 10)
5923 22:55:46.422503 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5924 22:55:46.425981 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5925 22:55:46.429456 best DQS0 dly(2T, 0.5T) = (0, 10)
5926 22:55:46.432885 best DQS1 dly(2T, 0.5T) = (0, 10)
5927 22:55:46.436016 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5928 22:55:46.436589 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5929 22:55:46.439390 Pre-setting of DQS Precalculation
5930 22:55:46.445751 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5931 22:55:46.452034 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5932 22:55:46.458974 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5933 22:55:46.459545
5934 22:55:46.459916
5935 22:55:46.462246 [Calibration Summary] 1866 Mbps
5936 22:55:46.465399 CH 0, Rank 0
5937 22:55:46.465967 SW Impedance : PASS
5938 22:55:46.468747 DUTY Scan : NO K
5939 22:55:46.472365 ZQ Calibration : PASS
5940 22:55:46.473105 Jitter Meter : NO K
5941 22:55:46.475315 CBT Training : PASS
5942 22:55:46.478937 Write leveling : PASS
5943 22:55:46.479505 RX DQS gating : PASS
5944 22:55:46.482659 RX DQ/DQS(RDDQC) : PASS
5945 22:55:46.483244 TX DQ/DQS : PASS
5946 22:55:46.485244 RX DATLAT : PASS
5947 22:55:46.488592 RX DQ/DQS(Engine): PASS
5948 22:55:46.489153 TX OE : NO K
5949 22:55:46.492118 All Pass.
5950 22:55:46.492708
5951 22:55:46.493189 CH 0, Rank 1
5952 22:55:46.495495 SW Impedance : PASS
5953 22:55:46.496066 DUTY Scan : NO K
5954 22:55:46.498714 ZQ Calibration : PASS
5955 22:55:46.501697 Jitter Meter : NO K
5956 22:55:46.502163 CBT Training : PASS
5957 22:55:46.505250 Write leveling : PASS
5958 22:55:46.508550 RX DQS gating : PASS
5959 22:55:46.509181 RX DQ/DQS(RDDQC) : PASS
5960 22:55:46.512225 TX DQ/DQS : PASS
5961 22:55:46.515104 RX DATLAT : PASS
5962 22:55:46.515673 RX DQ/DQS(Engine): PASS
5963 22:55:46.518474 TX OE : NO K
5964 22:55:46.519048 All Pass.
5965 22:55:46.519425
5966 22:55:46.521945 CH 1, Rank 0
5967 22:55:46.522514 SW Impedance : PASS
5968 22:55:46.525090 DUTY Scan : NO K
5969 22:55:46.528564 ZQ Calibration : PASS
5970 22:55:46.529169 Jitter Meter : NO K
5971 22:55:46.531961 CBT Training : PASS
5972 22:55:46.534925 Write leveling : PASS
5973 22:55:46.535392 RX DQS gating : PASS
5974 22:55:46.538470 RX DQ/DQS(RDDQC) : PASS
5975 22:55:46.541879 TX DQ/DQS : PASS
5976 22:55:46.542451 RX DATLAT : PASS
5977 22:55:46.544732 RX DQ/DQS(Engine): PASS
5978 22:55:46.545240 TX OE : NO K
5979 22:55:46.547906 All Pass.
5980 22:55:46.548370
5981 22:55:46.548736 CH 1, Rank 1
5982 22:55:46.551844 SW Impedance : PASS
5983 22:55:46.552416 DUTY Scan : NO K
5984 22:55:46.555002 ZQ Calibration : PASS
5985 22:55:46.558503 Jitter Meter : NO K
5986 22:55:46.559074 CBT Training : PASS
5987 22:55:46.561826 Write leveling : PASS
5988 22:55:46.565336 RX DQS gating : PASS
5989 22:55:46.565906 RX DQ/DQS(RDDQC) : PASS
5990 22:55:46.568293 TX DQ/DQS : PASS
5991 22:55:46.571635 RX DATLAT : PASS
5992 22:55:46.572204 RX DQ/DQS(Engine): PASS
5993 22:55:46.575060 TX OE : NO K
5994 22:55:46.575630 All Pass.
5995 22:55:46.576006
5996 22:55:46.578201 DramC Write-DBI off
5997 22:55:46.581418 PER_BANK_REFRESH: Hybrid Mode
5998 22:55:46.582195 TX_TRACKING: ON
5999 22:55:46.591283 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6000 22:55:46.594432 [FAST_K] Save calibration result to emmc
6001 22:55:46.597701 dramc_set_vcore_voltage set vcore to 650000
6002 22:55:46.601279 Read voltage for 400, 6
6003 22:55:46.601791 Vio18 = 0
6004 22:55:46.602176 Vcore = 650000
6005 22:55:46.604145 Vdram = 0
6006 22:55:46.604561 Vddq = 0
6007 22:55:46.604972 Vmddr = 0
6008 22:55:46.610963 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6009 22:55:46.614476 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6010 22:55:46.617684 MEM_TYPE=3, freq_sel=20
6011 22:55:46.621357 sv_algorithm_assistance_LP4_800
6012 22:55:46.624279 ============ PULL DRAM RESETB DOWN ============
6013 22:55:46.627671 ========== PULL DRAM RESETB DOWN end =========
6014 22:55:46.634526 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6015 22:55:46.637793 ===================================
6016 22:55:46.641284 LPDDR4 DRAM CONFIGURATION
6017 22:55:46.644024 ===================================
6018 22:55:46.644504 EX_ROW_EN[0] = 0x0
6019 22:55:46.647139 EX_ROW_EN[1] = 0x0
6020 22:55:46.647623 LP4Y_EN = 0x0
6021 22:55:46.650759 WORK_FSP = 0x0
6022 22:55:46.651256 WL = 0x2
6023 22:55:46.654239 RL = 0x2
6024 22:55:46.654709 BL = 0x2
6025 22:55:46.657399 RPST = 0x0
6026 22:55:46.657864 RD_PRE = 0x0
6027 22:55:46.660940 WR_PRE = 0x1
6028 22:55:46.661452 WR_PST = 0x0
6029 22:55:46.664013 DBI_WR = 0x0
6030 22:55:46.667204 DBI_RD = 0x0
6031 22:55:46.667688 OTF = 0x1
6032 22:55:46.670403 ===================================
6033 22:55:46.673566 ===================================
6034 22:55:46.674047 ANA top config
6035 22:55:46.677578 ===================================
6036 22:55:46.680389 DLL_ASYNC_EN = 0
6037 22:55:46.683490 ALL_SLAVE_EN = 1
6038 22:55:46.686703 NEW_RANK_MODE = 1
6039 22:55:46.690435 DLL_IDLE_MODE = 1
6040 22:55:46.690902 LP45_APHY_COMB_EN = 1
6041 22:55:46.693804 TX_ODT_DIS = 1
6042 22:55:46.696955 NEW_8X_MODE = 1
6043 22:55:46.700158 ===================================
6044 22:55:46.703458 ===================================
6045 22:55:46.706990 data_rate = 800
6046 22:55:46.710434 CKR = 1
6047 22:55:46.710913 DQ_P2S_RATIO = 4
6048 22:55:46.713452 ===================================
6049 22:55:46.716956 CA_P2S_RATIO = 4
6050 22:55:46.720513 DQ_CA_OPEN = 0
6051 22:55:46.723100 DQ_SEMI_OPEN = 1
6052 22:55:46.726574 CA_SEMI_OPEN = 1
6053 22:55:46.729799 CA_FULL_RATE = 0
6054 22:55:46.730407 DQ_CKDIV4_EN = 0
6055 22:55:46.733092 CA_CKDIV4_EN = 1
6056 22:55:46.736433 CA_PREDIV_EN = 0
6057 22:55:46.739742 PH8_DLY = 0
6058 22:55:46.742812 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6059 22:55:46.746444 DQ_AAMCK_DIV = 0
6060 22:55:46.746941 CA_AAMCK_DIV = 0
6061 22:55:46.749295 CA_ADMCK_DIV = 4
6062 22:55:46.752606 DQ_TRACK_CA_EN = 0
6063 22:55:46.756112 CA_PICK = 800
6064 22:55:46.759603 CA_MCKIO = 400
6065 22:55:46.762694 MCKIO_SEMI = 400
6066 22:55:46.765999 PLL_FREQ = 3016
6067 22:55:46.769404 DQ_UI_PI_RATIO = 32
6068 22:55:46.769875 CA_UI_PI_RATIO = 32
6069 22:55:46.773228 ===================================
6070 22:55:46.775902 ===================================
6071 22:55:46.779474 memory_type:LPDDR4
6072 22:55:46.782706 GP_NUM : 10
6073 22:55:46.783136 SRAM_EN : 1
6074 22:55:46.786018 MD32_EN : 0
6075 22:55:46.789346 ===================================
6076 22:55:46.792709 [ANA_INIT] >>>>>>>>>>>>>>
6077 22:55:46.795793 <<<<<< [CONFIGURE PHASE]: ANA_TX
6078 22:55:46.799191 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6079 22:55:46.802838 ===================================
6080 22:55:46.803314 data_rate = 800,PCW = 0X7400
6081 22:55:46.805743 ===================================
6082 22:55:46.809053 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6083 22:55:46.815850 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6084 22:55:46.829052 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6085 22:55:46.832317 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6086 22:55:46.835612 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6087 22:55:46.839283 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6088 22:55:46.842427 [ANA_INIT] flow start
6089 22:55:46.842971 [ANA_INIT] PLL >>>>>>>>
6090 22:55:46.845828 [ANA_INIT] PLL <<<<<<<<
6091 22:55:46.848974 [ANA_INIT] MIDPI >>>>>>>>
6092 22:55:46.849407 [ANA_INIT] MIDPI <<<<<<<<
6093 22:55:46.852229 [ANA_INIT] DLL >>>>>>>>
6094 22:55:46.855811 [ANA_INIT] flow end
6095 22:55:46.858747 ============ LP4 DIFF to SE enter ============
6096 22:55:46.862307 ============ LP4 DIFF to SE exit ============
6097 22:55:46.865974 [ANA_INIT] <<<<<<<<<<<<<
6098 22:55:46.869012 [Flow] Enable top DCM control >>>>>
6099 22:55:46.872504 [Flow] Enable top DCM control <<<<<
6100 22:55:46.875977 Enable DLL master slave shuffle
6101 22:55:46.878879 ==============================================================
6102 22:55:46.882254 Gating Mode config
6103 22:55:46.888644 ==============================================================
6104 22:55:46.889269 Config description:
6105 22:55:46.898418 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6106 22:55:46.905031 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6107 22:55:46.912088 SELPH_MODE 0: By rank 1: By Phase
6108 22:55:46.915460 ==============================================================
6109 22:55:46.918275 GAT_TRACK_EN = 0
6110 22:55:46.921853 RX_GATING_MODE = 2
6111 22:55:46.925266 RX_GATING_TRACK_MODE = 2
6112 22:55:46.928453 SELPH_MODE = 1
6113 22:55:46.931571 PICG_EARLY_EN = 1
6114 22:55:46.934760 VALID_LAT_VALUE = 1
6115 22:55:46.938547 ==============================================================
6116 22:55:46.944558 Enter into Gating configuration >>>>
6117 22:55:46.948489 Exit from Gating configuration <<<<
6118 22:55:46.949101 Enter into DVFS_PRE_config >>>>>
6119 22:55:46.961693 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6120 22:55:46.965189 Exit from DVFS_PRE_config <<<<<
6121 22:55:46.968010 Enter into PICG configuration >>>>
6122 22:55:46.971422 Exit from PICG configuration <<<<
6123 22:55:46.971998 [RX_INPUT] configuration >>>>>
6124 22:55:46.974672 [RX_INPUT] configuration <<<<<
6125 22:55:46.981041 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6126 22:55:46.984217 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6127 22:55:46.991359 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6128 22:55:46.997593 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6129 22:55:47.004310 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6130 22:55:47.010682 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6131 22:55:47.014440 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6132 22:55:47.017932 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6133 22:55:47.024311 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6134 22:55:47.027659 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6135 22:55:47.030999 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6136 22:55:47.037358 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6137 22:55:47.037829 ===================================
6138 22:55:47.041042 LPDDR4 DRAM CONFIGURATION
6139 22:55:47.044270 ===================================
6140 22:55:47.047431 EX_ROW_EN[0] = 0x0
6141 22:55:47.047902 EX_ROW_EN[1] = 0x0
6142 22:55:47.050842 LP4Y_EN = 0x0
6143 22:55:47.051413 WORK_FSP = 0x0
6144 22:55:47.053845 WL = 0x2
6145 22:55:47.054311 RL = 0x2
6146 22:55:47.056983 BL = 0x2
6147 22:55:47.057465 RPST = 0x0
6148 22:55:47.060700 RD_PRE = 0x0
6149 22:55:47.064082 WR_PRE = 0x1
6150 22:55:47.064652 WR_PST = 0x0
6151 22:55:47.067499 DBI_WR = 0x0
6152 22:55:47.068064 DBI_RD = 0x0
6153 22:55:47.070765 OTF = 0x1
6154 22:55:47.074188 ===================================
6155 22:55:47.077072 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6156 22:55:47.080469 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6157 22:55:47.083720 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6158 22:55:47.087177 ===================================
6159 22:55:47.090416 LPDDR4 DRAM CONFIGURATION
6160 22:55:47.093622 ===================================
6161 22:55:47.097144 EX_ROW_EN[0] = 0x10
6162 22:55:47.097713 EX_ROW_EN[1] = 0x0
6163 22:55:47.100276 LP4Y_EN = 0x0
6164 22:55:47.100923 WORK_FSP = 0x0
6165 22:55:47.103671 WL = 0x2
6166 22:55:47.104137 RL = 0x2
6167 22:55:47.106688 BL = 0x2
6168 22:55:47.110185 RPST = 0x0
6169 22:55:47.110752 RD_PRE = 0x0
6170 22:55:47.113423 WR_PRE = 0x1
6171 22:55:47.113893 WR_PST = 0x0
6172 22:55:47.116898 DBI_WR = 0x0
6173 22:55:47.117365 DBI_RD = 0x0
6174 22:55:47.119982 OTF = 0x1
6175 22:55:47.123055 ===================================
6176 22:55:47.130495 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6177 22:55:47.133133 nWR fixed to 30
6178 22:55:47.133601 [ModeRegInit_LP4] CH0 RK0
6179 22:55:47.136576 [ModeRegInit_LP4] CH0 RK1
6180 22:55:47.139657 [ModeRegInit_LP4] CH1 RK0
6181 22:55:47.140266 [ModeRegInit_LP4] CH1 RK1
6182 22:55:47.143008 match AC timing 19
6183 22:55:47.146390 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6184 22:55:47.149587 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6185 22:55:47.156092 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6186 22:55:47.159482 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6187 22:55:47.166376 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6188 22:55:47.166963 ==
6189 22:55:47.169498 Dram Type= 6, Freq= 0, CH_0, rank 0
6190 22:55:47.173143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6191 22:55:47.173729 ==
6192 22:55:47.179420 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6193 22:55:47.186210 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6194 22:55:47.186799 [CA 0] Center 36 (8~64) winsize 57
6195 22:55:47.189383 [CA 1] Center 36 (8~64) winsize 57
6196 22:55:47.192996 [CA 2] Center 36 (8~64) winsize 57
6197 22:55:47.196470 [CA 3] Center 36 (8~64) winsize 57
6198 22:55:47.199333 [CA 4] Center 36 (8~64) winsize 57
6199 22:55:47.202224 [CA 5] Center 36 (8~64) winsize 57
6200 22:55:47.202732
6201 22:55:47.205784 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6202 22:55:47.206273
6203 22:55:47.208983 [CATrainingPosCal] consider 1 rank data
6204 22:55:47.212631 u2DelayCellTimex100 = 270/100 ps
6205 22:55:47.215516 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6206 22:55:47.222260 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6207 22:55:47.225871 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6208 22:55:47.229242 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6209 22:55:47.232268 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6210 22:55:47.235701 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6211 22:55:47.236179
6212 22:55:47.238730 CA PerBit enable=1, Macro0, CA PI delay=36
6213 22:55:47.239202
6214 22:55:47.241935 [CBTSetCACLKResult] CA Dly = 36
6215 22:55:47.242501 CS Dly: 1 (0~32)
6216 22:55:47.245197 ==
6217 22:55:47.249053 Dram Type= 6, Freq= 0, CH_0, rank 1
6218 22:55:47.252098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6219 22:55:47.252577 ==
6220 22:55:47.258930 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6221 22:55:47.261688 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6222 22:55:47.265055 [CA 0] Center 36 (8~64) winsize 57
6223 22:55:47.268882 [CA 1] Center 36 (8~64) winsize 57
6224 22:55:47.271528 [CA 2] Center 36 (8~64) winsize 57
6225 22:55:47.274871 [CA 3] Center 36 (8~64) winsize 57
6226 22:55:47.278053 [CA 4] Center 36 (8~64) winsize 57
6227 22:55:47.282073 [CA 5] Center 36 (8~64) winsize 57
6228 22:55:47.282550
6229 22:55:47.285017 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6230 22:55:47.285495
6231 22:55:47.288238 [CATrainingPosCal] consider 2 rank data
6232 22:55:47.291318 u2DelayCellTimex100 = 270/100 ps
6233 22:55:47.294626 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 22:55:47.298257 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 22:55:47.301219 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 22:55:47.307821 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 22:55:47.311388 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 22:55:47.314144 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 22:55:47.314228
6240 22:55:47.317665 CA PerBit enable=1, Macro0, CA PI delay=36
6241 22:55:47.317750
6242 22:55:47.321018 [CBTSetCACLKResult] CA Dly = 36
6243 22:55:47.321102 CS Dly: 1 (0~32)
6244 22:55:47.321169
6245 22:55:47.323884 ----->DramcWriteLeveling(PI) begin...
6246 22:55:47.327539 ==
6247 22:55:47.327623 Dram Type= 6, Freq= 0, CH_0, rank 0
6248 22:55:47.334467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6249 22:55:47.334552 ==
6250 22:55:47.337513 Write leveling (Byte 0): 40 => 8
6251 22:55:47.340849 Write leveling (Byte 1): 32 => 0
6252 22:55:47.340961 DramcWriteLeveling(PI) end<-----
6253 22:55:47.344178
6254 22:55:47.344288 ==
6255 22:55:47.347298 Dram Type= 6, Freq= 0, CH_0, rank 0
6256 22:55:47.350578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6257 22:55:47.350687 ==
6258 22:55:47.353872 [Gating] SW mode calibration
6259 22:55:47.361112 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6260 22:55:47.364582 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6261 22:55:47.371069 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6262 22:55:47.373884 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6263 22:55:47.377474 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6264 22:55:47.383504 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6265 22:55:47.386809 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6266 22:55:47.390571 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6267 22:55:47.396781 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6268 22:55:47.400054 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6269 22:55:47.403512 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6270 22:55:47.406630 Total UI for P1: 0, mck2ui 16
6271 22:55:47.409859 best dqsien dly found for B0: ( 0, 14, 24)
6272 22:55:47.413282 Total UI for P1: 0, mck2ui 16
6273 22:55:47.417022 best dqsien dly found for B1: ( 0, 14, 24)
6274 22:55:47.423685 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6275 22:55:47.426872 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6276 22:55:47.427292
6277 22:55:47.430489 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6278 22:55:47.433330 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6279 22:55:47.436256 [Gating] SW calibration Done
6280 22:55:47.436344 ==
6281 22:55:47.439562 Dram Type= 6, Freq= 0, CH_0, rank 0
6282 22:55:47.443689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6283 22:55:47.443904 ==
6284 22:55:47.446563 RX Vref Scan: 0
6285 22:55:47.446733
6286 22:55:47.446860 RX Vref 0 -> 0, step: 1
6287 22:55:47.446982
6288 22:55:47.449691 RX Delay -410 -> 252, step: 16
6289 22:55:47.456400 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6290 22:55:47.459330 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6291 22:55:47.462834 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6292 22:55:47.465940 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6293 22:55:47.472933 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6294 22:55:47.476079 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6295 22:55:47.479687 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6296 22:55:47.482710 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6297 22:55:47.489219 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6298 22:55:47.492914 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6299 22:55:47.496370 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6300 22:55:47.499675 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6301 22:55:47.506548 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6302 22:55:47.509378 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6303 22:55:47.512847 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6304 22:55:47.516521 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6305 22:55:47.519916 ==
6306 22:55:47.523019 Dram Type= 6, Freq= 0, CH_0, rank 0
6307 22:55:47.526005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6308 22:55:47.526469 ==
6309 22:55:47.526835 DQS Delay:
6310 22:55:47.529633 DQS0 = 27, DQS1 = 43
6311 22:55:47.530186 DQM Delay:
6312 22:55:47.532846 DQM0 = 12, DQM1 = 12
6313 22:55:47.533401 DQ Delay:
6314 22:55:47.535893 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6315 22:55:47.539298 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6316 22:55:47.542802 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6317 22:55:47.545968 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6318 22:55:47.546588
6319 22:55:47.546959
6320 22:55:47.547430 ==
6321 22:55:47.549568 Dram Type= 6, Freq= 0, CH_0, rank 0
6322 22:55:47.552876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6323 22:55:47.553462 ==
6324 22:55:47.553922
6325 22:55:47.554369
6326 22:55:47.555713 TX Vref Scan disable
6327 22:55:47.556248 == TX Byte 0 ==
6328 22:55:47.562605 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6329 22:55:47.565583 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6330 22:55:47.566039 == TX Byte 1 ==
6331 22:55:47.571975 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6332 22:55:47.575646 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6333 22:55:47.575729 ==
6334 22:55:47.578812 Dram Type= 6, Freq= 0, CH_0, rank 0
6335 22:55:47.581776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6336 22:55:47.581857 ==
6337 22:55:47.581920
6338 22:55:47.581979
6339 22:55:47.585461 TX Vref Scan disable
6340 22:55:47.589068 == TX Byte 0 ==
6341 22:55:47.592330 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6342 22:55:47.594892 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6343 22:55:47.594975 == TX Byte 1 ==
6344 22:55:47.601853 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6345 22:55:47.605187 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6346 22:55:47.605269
6347 22:55:47.605334 [DATLAT]
6348 22:55:47.608408 Freq=400, CH0 RK0
6349 22:55:47.608497
6350 22:55:47.608566 DATLAT Default: 0xf
6351 22:55:47.611866 0, 0xFFFF, sum = 0
6352 22:55:47.615041 1, 0xFFFF, sum = 0
6353 22:55:47.615138 2, 0xFFFF, sum = 0
6354 22:55:47.618481 3, 0xFFFF, sum = 0
6355 22:55:47.618664 4, 0xFFFF, sum = 0
6356 22:55:47.621584 5, 0xFFFF, sum = 0
6357 22:55:47.621699 6, 0xFFFF, sum = 0
6358 22:55:47.624936 7, 0xFFFF, sum = 0
6359 22:55:47.625049 8, 0xFFFF, sum = 0
6360 22:55:47.628201 9, 0xFFFF, sum = 0
6361 22:55:47.628286 10, 0xFFFF, sum = 0
6362 22:55:47.631301 11, 0xFFFF, sum = 0
6363 22:55:47.631387 12, 0xFFFF, sum = 0
6364 22:55:47.634629 13, 0x0, sum = 1
6365 22:55:47.634713 14, 0x0, sum = 2
6366 22:55:47.638003 15, 0x0, sum = 3
6367 22:55:47.638093 16, 0x0, sum = 4
6368 22:55:47.641305 best_step = 14
6369 22:55:47.641400
6370 22:55:47.641475 ==
6371 22:55:47.644593 Dram Type= 6, Freq= 0, CH_0, rank 0
6372 22:55:47.647913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6373 22:55:47.648017 ==
6374 22:55:47.651443 RX Vref Scan: 1
6375 22:55:47.651555
6376 22:55:47.651644 RX Vref 0 -> 0, step: 1
6377 22:55:47.651728
6378 22:55:47.655115 RX Delay -327 -> 252, step: 8
6379 22:55:47.655228
6380 22:55:47.658083 Set Vref, RX VrefLevel [Byte0]: 57
6381 22:55:47.661215 [Byte1]: 49
6382 22:55:47.665595
6383 22:55:47.665838 Final RX Vref Byte 0 = 57 to rank0
6384 22:55:47.669119 Final RX Vref Byte 1 = 49 to rank0
6385 22:55:47.672158 Final RX Vref Byte 0 = 57 to rank1
6386 22:55:47.675598 Final RX Vref Byte 1 = 49 to rank1==
6387 22:55:47.678862 Dram Type= 6, Freq= 0, CH_0, rank 0
6388 22:55:47.685760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6389 22:55:47.686172 ==
6390 22:55:47.686427 DQS Delay:
6391 22:55:47.689380 DQS0 = 28, DQS1 = 48
6392 22:55:47.689787 DQM Delay:
6393 22:55:47.690043 DQM0 = 12, DQM1 = 15
6394 22:55:47.692185 DQ Delay:
6395 22:55:47.695748 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6396 22:55:47.698942 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6397 22:55:47.699520 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6398 22:55:47.705556 DQ12 =24, DQ13 =16, DQ14 =28, DQ15 =24
6399 22:55:47.706029
6400 22:55:47.706397
6401 22:55:47.712205 [DQSOSCAuto] RK0, (LSB)MR18= 0xaea6, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6402 22:55:47.715145 CH0 RK0: MR19=C0C, MR18=AEA6
6403 22:55:47.722206 CH0_RK0: MR19=0xC0C, MR18=0xAEA6, DQSOSC=388, MR23=63, INC=392, DEC=261
6404 22:55:47.722791 ==
6405 22:55:47.725232 Dram Type= 6, Freq= 0, CH_0, rank 1
6406 22:55:47.728813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6407 22:55:47.729401 ==
6408 22:55:47.731903 [Gating] SW mode calibration
6409 22:55:47.738754 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6410 22:55:47.745348 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6411 22:55:47.748690 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6412 22:55:47.751515 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6413 22:55:47.758259 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6414 22:55:47.762055 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6415 22:55:47.765242 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6416 22:55:47.771847 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6417 22:55:47.774794 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6418 22:55:47.778311 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6419 22:55:47.784598 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6420 22:55:47.785110 Total UI for P1: 0, mck2ui 16
6421 22:55:47.791874 best dqsien dly found for B0: ( 0, 14, 24)
6422 22:55:47.792451 Total UI for P1: 0, mck2ui 16
6423 22:55:47.798389 best dqsien dly found for B1: ( 0, 14, 24)
6424 22:55:47.801521 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6425 22:55:47.804665 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6426 22:55:47.805155
6427 22:55:47.808342 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6428 22:55:47.811667 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6429 22:55:47.814302 [Gating] SW calibration Done
6430 22:55:47.814778 ==
6431 22:55:47.817876 Dram Type= 6, Freq= 0, CH_0, rank 1
6432 22:55:47.821188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6433 22:55:47.821663 ==
6434 22:55:47.824525 RX Vref Scan: 0
6435 22:55:47.825019
6436 22:55:47.825390 RX Vref 0 -> 0, step: 1
6437 22:55:47.825736
6438 22:55:47.827992 RX Delay -410 -> 252, step: 16
6439 22:55:47.834841 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6440 22:55:47.837988 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6441 22:55:47.840874 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6442 22:55:47.843932 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6443 22:55:47.850949 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6444 22:55:47.854226 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6445 22:55:47.857167 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6446 22:55:47.860479 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6447 22:55:47.867060 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6448 22:55:47.870765 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6449 22:55:47.873649 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6450 22:55:47.879715 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6451 22:55:47.883577 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6452 22:55:47.886721 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6453 22:55:47.890023 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6454 22:55:47.896508 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6455 22:55:47.897110 ==
6456 22:55:47.899596 Dram Type= 6, Freq= 0, CH_0, rank 1
6457 22:55:47.903193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6458 22:55:47.903697 ==
6459 22:55:47.904140 DQS Delay:
6460 22:55:47.906656 DQS0 = 27, DQS1 = 43
6461 22:55:47.907297 DQM Delay:
6462 22:55:47.909971 DQM0 = 10, DQM1 = 15
6463 22:55:47.910543 DQ Delay:
6464 22:55:47.912932 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6465 22:55:47.916817 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =16
6466 22:55:47.919616 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6467 22:55:47.923264 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6468 22:55:47.923695
6469 22:55:47.924038
6470 22:55:47.924354 ==
6471 22:55:47.926123 Dram Type= 6, Freq= 0, CH_0, rank 1
6472 22:55:47.929933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6473 22:55:47.930369 ==
6474 22:55:47.930712
6475 22:55:47.931041
6476 22:55:47.932756 TX Vref Scan disable
6477 22:55:47.936141 == TX Byte 0 ==
6478 22:55:47.939347 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6479 22:55:47.943056 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6480 22:55:47.945718 == TX Byte 1 ==
6481 22:55:47.949380 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6482 22:55:47.952658 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6483 22:55:47.953249 ==
6484 22:55:47.956042 Dram Type= 6, Freq= 0, CH_0, rank 1
6485 22:55:47.959216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6486 22:55:47.959842 ==
6487 22:55:47.962774
6488 22:55:47.963239
6489 22:55:47.963696 TX Vref Scan disable
6490 22:55:47.965934 == TX Byte 0 ==
6491 22:55:47.969382 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6492 22:55:47.972581 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6493 22:55:47.975992 == TX Byte 1 ==
6494 22:55:47.979820 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6495 22:55:47.982691 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6496 22:55:47.983119
6497 22:55:47.983457 [DATLAT]
6498 22:55:47.986229 Freq=400, CH0 RK1
6499 22:55:47.986788
6500 22:55:47.989254 DATLAT Default: 0xe
6501 22:55:47.989679 0, 0xFFFF, sum = 0
6502 22:55:47.992218 1, 0xFFFF, sum = 0
6503 22:55:47.992653 2, 0xFFFF, sum = 0
6504 22:55:47.995576 3, 0xFFFF, sum = 0
6505 22:55:47.996119 4, 0xFFFF, sum = 0
6506 22:55:47.998988 5, 0xFFFF, sum = 0
6507 22:55:47.999559 6, 0xFFFF, sum = 0
6508 22:55:48.002460 7, 0xFFFF, sum = 0
6509 22:55:48.002919 8, 0xFFFF, sum = 0
6510 22:55:48.005675 9, 0xFFFF, sum = 0
6511 22:55:48.006113 10, 0xFFFF, sum = 0
6512 22:55:48.008866 11, 0xFFFF, sum = 0
6513 22:55:48.009305 12, 0xFFFF, sum = 0
6514 22:55:48.012111 13, 0x0, sum = 1
6515 22:55:48.012551 14, 0x0, sum = 2
6516 22:55:48.015603 15, 0x0, sum = 3
6517 22:55:48.016065 16, 0x0, sum = 4
6518 22:55:48.018739 best_step = 14
6519 22:55:48.019122
6520 22:55:48.019445 ==
6521 22:55:48.022314 Dram Type= 6, Freq= 0, CH_0, rank 1
6522 22:55:48.025388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6523 22:55:48.025783 ==
6524 22:55:48.028622 RX Vref Scan: 0
6525 22:55:48.029036
6526 22:55:48.029386 RX Vref 0 -> 0, step: 1
6527 22:55:48.029725
6528 22:55:48.031796 RX Delay -327 -> 252, step: 8
6529 22:55:48.039926 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6530 22:55:48.043413 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6531 22:55:48.046250 iDelay=217, Bit 2, Center -20 (-239 ~ 200) 440
6532 22:55:48.049828 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6533 22:55:48.056267 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6534 22:55:48.059736 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6535 22:55:48.063141 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6536 22:55:48.066077 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6537 22:55:48.072721 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6538 22:55:48.076530 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6539 22:55:48.079604 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6540 22:55:48.085536 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6541 22:55:48.088932 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6542 22:55:48.092196 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6543 22:55:48.095543 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6544 22:55:48.102429 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6545 22:55:48.102539 ==
6546 22:55:48.105413 Dram Type= 6, Freq= 0, CH_0, rank 1
6547 22:55:48.108694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6548 22:55:48.108792 ==
6549 22:55:48.108865 DQS Delay:
6550 22:55:48.112172 DQS0 = 28, DQS1 = 40
6551 22:55:48.112287 DQM Delay:
6552 22:55:48.115716 DQM0 = 11, DQM1 = 13
6553 22:55:48.115816 DQ Delay:
6554 22:55:48.119246 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6555 22:55:48.122568 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6556 22:55:48.125696 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6557 22:55:48.128986 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6558 22:55:48.129124
6559 22:55:48.129243
6560 22:55:48.135326 [DQSOSCAuto] RK1, (LSB)MR18= 0xbb6f, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps
6561 22:55:48.138817 CH0 RK1: MR19=C0C, MR18=BB6F
6562 22:55:48.145193 CH0_RK1: MR19=0xC0C, MR18=0xBB6F, DQSOSC=386, MR23=63, INC=396, DEC=264
6563 22:55:48.149075 [RxdqsGatingPostProcess] freq 400
6564 22:55:48.155399 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6565 22:55:48.158605 best DQS0 dly(2T, 0.5T) = (0, 10)
6566 22:55:48.162095 best DQS1 dly(2T, 0.5T) = (0, 10)
6567 22:55:48.162345 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6568 22:55:48.166164 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6569 22:55:48.168690 best DQS0 dly(2T, 0.5T) = (0, 10)
6570 22:55:48.172134 best DQS1 dly(2T, 0.5T) = (0, 10)
6571 22:55:48.175327 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6572 22:55:48.178561 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6573 22:55:48.182537 Pre-setting of DQS Precalculation
6574 22:55:48.188734 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6575 22:55:48.189220 ==
6576 22:55:48.191755 Dram Type= 6, Freq= 0, CH_1, rank 0
6577 22:55:48.194931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6578 22:55:48.195355 ==
6579 22:55:48.202033 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6580 22:55:48.208809 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6581 22:55:48.211666 [CA 0] Center 36 (8~64) winsize 57
6582 22:55:48.214885 [CA 1] Center 36 (8~64) winsize 57
6583 22:55:48.215485 [CA 2] Center 36 (8~64) winsize 57
6584 22:55:48.218467 [CA 3] Center 36 (8~64) winsize 57
6585 22:55:48.221766 [CA 4] Center 36 (8~64) winsize 57
6586 22:55:48.224790 [CA 5] Center 36 (8~64) winsize 57
6587 22:55:48.224936
6588 22:55:48.227910 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6589 22:55:48.227984
6590 22:55:48.234605 [CATrainingPosCal] consider 1 rank data
6591 22:55:48.234683 u2DelayCellTimex100 = 270/100 ps
6592 22:55:48.240665 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6593 22:55:48.244507 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6594 22:55:48.247493 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6595 22:55:48.250829 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6596 22:55:48.254382 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6597 22:55:48.257312 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6598 22:55:48.257411
6599 22:55:48.260866 CA PerBit enable=1, Macro0, CA PI delay=36
6600 22:55:48.260966
6601 22:55:48.264264 [CBTSetCACLKResult] CA Dly = 36
6602 22:55:48.267437 CS Dly: 1 (0~32)
6603 22:55:48.267539 ==
6604 22:55:48.270559 Dram Type= 6, Freq= 0, CH_1, rank 1
6605 22:55:48.274077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6606 22:55:48.274177 ==
6607 22:55:48.280381 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6608 22:55:48.283688 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6609 22:55:48.287445 [CA 0] Center 36 (8~64) winsize 57
6610 22:55:48.290344 [CA 1] Center 36 (8~64) winsize 57
6611 22:55:48.294007 [CA 2] Center 36 (8~64) winsize 57
6612 22:55:48.296814 [CA 3] Center 36 (8~64) winsize 57
6613 22:55:48.300227 [CA 4] Center 36 (8~64) winsize 57
6614 22:55:48.303680 [CA 5] Center 36 (8~64) winsize 57
6615 22:55:48.303781
6616 22:55:48.306935 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6617 22:55:48.307037
6618 22:55:48.310029 [CATrainingPosCal] consider 2 rank data
6619 22:55:48.313582 u2DelayCellTimex100 = 270/100 ps
6620 22:55:48.316607 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 22:55:48.320060 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 22:55:48.326826 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 22:55:48.329869 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 22:55:48.333644 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 22:55:48.336888 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 22:55:48.336988
6627 22:55:48.339766 CA PerBit enable=1, Macro0, CA PI delay=36
6628 22:55:48.339865
6629 22:55:48.343169 [CBTSetCACLKResult] CA Dly = 36
6630 22:55:48.346851 CS Dly: 1 (0~32)
6631 22:55:48.346950
6632 22:55:48.349793 ----->DramcWriteLeveling(PI) begin...
6633 22:55:48.349899 ==
6634 22:55:48.353333 Dram Type= 6, Freq= 0, CH_1, rank 0
6635 22:55:48.356517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6636 22:55:48.356619 ==
6637 22:55:48.359542 Write leveling (Byte 0): 40 => 8
6638 22:55:48.363260 Write leveling (Byte 1): 32 => 0
6639 22:55:48.366091 DramcWriteLeveling(PI) end<-----
6640 22:55:48.366192
6641 22:55:48.366284 ==
6642 22:55:48.369537 Dram Type= 6, Freq= 0, CH_1, rank 0
6643 22:55:48.372925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6644 22:55:48.373027 ==
6645 22:55:48.376021 [Gating] SW mode calibration
6646 22:55:48.382636 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6647 22:55:48.389445 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6648 22:55:48.393160 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6649 22:55:48.395846 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6650 22:55:48.402496 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6651 22:55:48.405635 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6652 22:55:48.408717 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6653 22:55:48.415600 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6654 22:55:48.418817 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6655 22:55:48.422003 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6656 22:55:48.429054 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6657 22:55:48.432009 Total UI for P1: 0, mck2ui 16
6658 22:55:48.435087 best dqsien dly found for B0: ( 0, 14, 24)
6659 22:55:48.435192 Total UI for P1: 0, mck2ui 16
6660 22:55:48.441787 best dqsien dly found for B1: ( 0, 14, 24)
6661 22:55:48.445342 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6662 22:55:48.448344 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6663 22:55:48.448444
6664 22:55:48.451899 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6665 22:55:48.455012 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6666 22:55:48.458360 [Gating] SW calibration Done
6667 22:55:48.458463 ==
6668 22:55:48.461508 Dram Type= 6, Freq= 0, CH_1, rank 0
6669 22:55:48.465123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6670 22:55:48.465228 ==
6671 22:55:48.468416 RX Vref Scan: 0
6672 22:55:48.468516
6673 22:55:48.471414 RX Vref 0 -> 0, step: 1
6674 22:55:48.471514
6675 22:55:48.471605 RX Delay -410 -> 252, step: 16
6676 22:55:48.478211 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6677 22:55:48.481612 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6678 22:55:48.484759 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6679 22:55:48.488022 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6680 22:55:48.494619 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6681 22:55:48.497968 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6682 22:55:48.502252 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6683 22:55:48.504601 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6684 22:55:48.511141 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6685 22:55:48.514500 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6686 22:55:48.518032 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6687 22:55:48.524472 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6688 22:55:48.527716 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6689 22:55:48.531099 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6690 22:55:48.534283 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6691 22:55:48.541012 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6692 22:55:48.541090 ==
6693 22:55:48.544612 Dram Type= 6, Freq= 0, CH_1, rank 0
6694 22:55:48.547705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6695 22:55:48.547820 ==
6696 22:55:48.547930 DQS Delay:
6697 22:55:48.550970 DQS0 = 27, DQS1 = 43
6698 22:55:48.551069 DQM Delay:
6699 22:55:48.554668 DQM0 = 8, DQM1 = 17
6700 22:55:48.554793 DQ Delay:
6701 22:55:48.557551 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6702 22:55:48.560899 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6703 22:55:48.564153 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6704 22:55:48.567596 DQ12 =32, DQ13 =32, DQ14 =16, DQ15 =24
6705 22:55:48.567706
6706 22:55:48.567805
6707 22:55:48.567903 ==
6708 22:55:48.571030 Dram Type= 6, Freq= 0, CH_1, rank 0
6709 22:55:48.574288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6710 22:55:48.574402 ==
6711 22:55:48.574495
6712 22:55:48.574583
6713 22:55:48.577707 TX Vref Scan disable
6714 22:55:48.580678 == TX Byte 0 ==
6715 22:55:48.584304 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6716 22:55:48.587597 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6717 22:55:48.587711 == TX Byte 1 ==
6718 22:55:48.593897 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6719 22:55:48.597888 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6720 22:55:48.598037 ==
6721 22:55:48.600671 Dram Type= 6, Freq= 0, CH_1, rank 0
6722 22:55:48.604282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6723 22:55:48.604384 ==
6724 22:55:48.607295
6725 22:55:48.607396
6726 22:55:48.607489 TX Vref Scan disable
6727 22:55:48.610390 == TX Byte 0 ==
6728 22:55:48.613992 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6729 22:55:48.616951 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6730 22:55:48.620382 == TX Byte 1 ==
6731 22:55:48.623543 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6732 22:55:48.627081 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6733 22:55:48.627192
6734 22:55:48.630548 [DATLAT]
6735 22:55:48.630632 Freq=400, CH1 RK0
6736 22:55:48.630699
6737 22:55:48.633529 DATLAT Default: 0xf
6738 22:55:48.633613 0, 0xFFFF, sum = 0
6739 22:55:48.637268 1, 0xFFFF, sum = 0
6740 22:55:48.637356 2, 0xFFFF, sum = 0
6741 22:55:48.640498 3, 0xFFFF, sum = 0
6742 22:55:48.640612 4, 0xFFFF, sum = 0
6743 22:55:48.643596 5, 0xFFFF, sum = 0
6744 22:55:48.643698 6, 0xFFFF, sum = 0
6745 22:55:48.647153 7, 0xFFFF, sum = 0
6746 22:55:48.647265 8, 0xFFFF, sum = 0
6747 22:55:48.650235 9, 0xFFFF, sum = 0
6748 22:55:48.650347 10, 0xFFFF, sum = 0
6749 22:55:48.653262 11, 0xFFFF, sum = 0
6750 22:55:48.656796 12, 0xFFFF, sum = 0
6751 22:55:48.656888 13, 0x0, sum = 1
6752 22:55:48.656953 14, 0x0, sum = 2
6753 22:55:48.660034 15, 0x0, sum = 3
6754 22:55:48.660119 16, 0x0, sum = 4
6755 22:55:48.663403 best_step = 14
6756 22:55:48.663487
6757 22:55:48.663553 ==
6758 22:55:48.666531 Dram Type= 6, Freq= 0, CH_1, rank 0
6759 22:55:48.669880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6760 22:55:48.669965 ==
6761 22:55:48.673083 RX Vref Scan: 1
6762 22:55:48.673195
6763 22:55:48.673289 RX Vref 0 -> 0, step: 1
6764 22:55:48.673379
6765 22:55:48.676638 RX Delay -327 -> 252, step: 8
6766 22:55:48.676738
6767 22:55:48.680017 Set Vref, RX VrefLevel [Byte0]: 52
6768 22:55:48.683219 [Byte1]: 51
6769 22:55:48.687980
6770 22:55:48.688076 Final RX Vref Byte 0 = 52 to rank0
6771 22:55:48.691599 Final RX Vref Byte 1 = 51 to rank0
6772 22:55:48.695048 Final RX Vref Byte 0 = 52 to rank1
6773 22:55:48.698258 Final RX Vref Byte 1 = 51 to rank1==
6774 22:55:48.701888 Dram Type= 6, Freq= 0, CH_1, rank 0
6775 22:55:48.707900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6776 22:55:48.708045 ==
6777 22:55:48.708156 DQS Delay:
6778 22:55:48.711670 DQS0 = 32, DQS1 = 40
6779 22:55:48.711882 DQM Delay:
6780 22:55:48.712059 DQM0 = 12, DQM1 = 12
6781 22:55:48.714664 DQ Delay:
6782 22:55:48.717941 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6783 22:55:48.718183 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6784 22:55:48.721148 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6785 22:55:48.724638 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6786 22:55:48.724861
6787 22:55:48.727897
6788 22:55:48.734775 [DQSOSCAuto] RK0, (LSB)MR18= 0x92cc, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6789 22:55:48.737823 CH1 RK0: MR19=C0C, MR18=92CC
6790 22:55:48.744762 CH1_RK0: MR19=0xC0C, MR18=0x92CC, DQSOSC=384, MR23=63, INC=400, DEC=267
6791 22:55:48.744863 ==
6792 22:55:48.747972 Dram Type= 6, Freq= 0, CH_1, rank 1
6793 22:55:48.750824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6794 22:55:48.750897 ==
6795 22:55:48.754176 [Gating] SW mode calibration
6796 22:55:48.761015 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6797 22:55:48.767453 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6798 22:55:48.770881 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6799 22:55:48.773798 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6800 22:55:48.780657 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6801 22:55:48.783801 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6802 22:55:48.787535 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6803 22:55:48.794033 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6804 22:55:48.797226 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6805 22:55:48.800544 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6806 22:55:48.807192 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6807 22:55:48.807270 Total UI for P1: 0, mck2ui 16
6808 22:55:48.813679 best dqsien dly found for B0: ( 0, 14, 24)
6809 22:55:48.813758 Total UI for P1: 0, mck2ui 16
6810 22:55:48.816899 best dqsien dly found for B1: ( 0, 14, 24)
6811 22:55:48.823582 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6812 22:55:48.826942 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6813 22:55:48.827026
6814 22:55:48.830289 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6815 22:55:48.833867 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6816 22:55:48.836986 [Gating] SW calibration Done
6817 22:55:48.837069 ==
6818 22:55:48.840799 Dram Type= 6, Freq= 0, CH_1, rank 1
6819 22:55:48.843512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6820 22:55:48.843596 ==
6821 22:55:48.846709 RX Vref Scan: 0
6822 22:55:48.846792
6823 22:55:48.846858 RX Vref 0 -> 0, step: 1
6824 22:55:48.846920
6825 22:55:48.850278 RX Delay -410 -> 252, step: 16
6826 22:55:48.856861 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6827 22:55:48.859980 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6828 22:55:48.863264 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6829 22:55:48.866854 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6830 22:55:48.873155 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6831 22:55:48.876510 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6832 22:55:48.879749 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6833 22:55:48.882883 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6834 22:55:48.889622 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6835 22:55:48.893032 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6836 22:55:48.896485 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6837 22:55:48.899829 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6838 22:55:48.907075 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6839 22:55:48.909592 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6840 22:55:48.912898 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6841 22:55:48.919227 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6842 22:55:48.919383 ==
6843 22:55:48.922701 Dram Type= 6, Freq= 0, CH_1, rank 1
6844 22:55:48.925768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6845 22:55:48.925991 ==
6846 22:55:48.926140 DQS Delay:
6847 22:55:48.929911 DQS0 = 35, DQS1 = 43
6848 22:55:48.930005 DQM Delay:
6849 22:55:48.933192 DQM0 = 18, DQM1 = 19
6850 22:55:48.933269 DQ Delay:
6851 22:55:48.935460 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6852 22:55:48.939243 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6853 22:55:48.942570 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6854 22:55:48.945759 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6855 22:55:48.945860
6856 22:55:48.945950
6857 22:55:48.946038 ==
6858 22:55:48.949139 Dram Type= 6, Freq= 0, CH_1, rank 1
6859 22:55:48.952016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6860 22:55:48.952090 ==
6861 22:55:48.952167
6862 22:55:48.955624
6863 22:55:48.955694 TX Vref Scan disable
6864 22:55:48.958709 == TX Byte 0 ==
6865 22:55:48.962209 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6866 22:55:48.965867 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6867 22:55:48.968557 == TX Byte 1 ==
6868 22:55:48.972214 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6869 22:55:48.975424 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6870 22:55:48.975855 ==
6871 22:55:48.979394 Dram Type= 6, Freq= 0, CH_1, rank 1
6872 22:55:48.982409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6873 22:55:48.985258 ==
6874 22:55:48.985817
6875 22:55:48.986256
6876 22:55:48.986708 TX Vref Scan disable
6877 22:55:48.988682 == TX Byte 0 ==
6878 22:55:48.992296 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6879 22:55:48.995300 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6880 22:55:48.998697 == TX Byte 1 ==
6881 22:55:49.002252 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6882 22:55:49.005326 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6883 22:55:49.005937
6884 22:55:49.008418 [DATLAT]
6885 22:55:49.009055 Freq=400, CH1 RK1
6886 22:55:49.009575
6887 22:55:49.012292 DATLAT Default: 0xe
6888 22:55:49.012915 0, 0xFFFF, sum = 0
6889 22:55:49.015013 1, 0xFFFF, sum = 0
6890 22:55:49.015572 2, 0xFFFF, sum = 0
6891 22:55:49.018824 3, 0xFFFF, sum = 0
6892 22:55:49.019446 4, 0xFFFF, sum = 0
6893 22:55:49.021902 5, 0xFFFF, sum = 0
6894 22:55:49.022515 6, 0xFFFF, sum = 0
6895 22:55:49.025512 7, 0xFFFF, sum = 0
6896 22:55:49.026135 8, 0xFFFF, sum = 0
6897 22:55:49.028473 9, 0xFFFF, sum = 0
6898 22:55:49.029098 10, 0xFFFF, sum = 0
6899 22:55:49.031525 11, 0xFFFF, sum = 0
6900 22:55:49.032112 12, 0xFFFF, sum = 0
6901 22:55:49.034854 13, 0x0, sum = 1
6902 22:55:49.035467 14, 0x0, sum = 2
6903 22:55:49.038881 15, 0x0, sum = 3
6904 22:55:49.039312 16, 0x0, sum = 4
6905 22:55:49.042087 best_step = 14
6906 22:55:49.042509
6907 22:55:49.042843 ==
6908 22:55:49.045214 Dram Type= 6, Freq= 0, CH_1, rank 1
6909 22:55:49.048382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6910 22:55:49.048844 ==
6911 22:55:49.051612 RX Vref Scan: 0
6912 22:55:49.052038
6913 22:55:49.052376 RX Vref 0 -> 0, step: 1
6914 22:55:49.052694
6915 22:55:49.054547 RX Delay -327 -> 252, step: 8
6916 22:55:49.063008 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6917 22:55:49.066249 iDelay=217, Bit 1, Center -24 (-239 ~ 192) 432
6918 22:55:49.069411 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6919 22:55:49.072927 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6920 22:55:49.080012 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6921 22:55:49.082532 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6922 22:55:49.086062 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6923 22:55:49.089966 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6924 22:55:49.096323 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6925 22:55:49.099711 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6926 22:55:49.103065 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6927 22:55:49.109514 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6928 22:55:49.113167 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6929 22:55:49.116643 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6930 22:55:49.119659 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6931 22:55:49.126409 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6932 22:55:49.126992 ==
6933 22:55:49.129337 Dram Type= 6, Freq= 0, CH_1, rank 1
6934 22:55:49.132747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6935 22:55:49.133262 ==
6936 22:55:49.133740 DQS Delay:
6937 22:55:49.135982 DQS0 = 32, DQS1 = 36
6938 22:55:49.136570 DQM Delay:
6939 22:55:49.139384 DQM0 = 12, DQM1 = 12
6940 22:55:49.139950 DQ Delay:
6941 22:55:49.142614 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6942 22:55:49.145696 DQ4 =16, DQ5 =20, DQ6 =16, DQ7 =12
6943 22:55:49.148882 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6944 22:55:49.152273 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
6945 22:55:49.152818
6946 22:55:49.153201
6947 22:55:49.158987 [DQSOSCAuto] RK1, (LSB)MR18= 0xb058, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 387 ps
6948 22:55:49.162719 CH1 RK1: MR19=C0C, MR18=B058
6949 22:55:49.168912 CH1_RK1: MR19=0xC0C, MR18=0xB058, DQSOSC=387, MR23=63, INC=394, DEC=262
6950 22:55:49.172344 [RxdqsGatingPostProcess] freq 400
6951 22:55:49.178965 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6952 22:55:49.182001 best DQS0 dly(2T, 0.5T) = (0, 10)
6953 22:55:49.185536 best DQS1 dly(2T, 0.5T) = (0, 10)
6954 22:55:49.188710 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6955 22:55:49.192595 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6956 22:55:49.193162 best DQS0 dly(2T, 0.5T) = (0, 10)
6957 22:55:49.195379 best DQS1 dly(2T, 0.5T) = (0, 10)
6958 22:55:49.198771 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6959 22:55:49.202048 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6960 22:55:49.205099 Pre-setting of DQS Precalculation
6961 22:55:49.212015 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6962 22:55:49.218370 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6963 22:55:49.225310 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6964 22:55:49.225882
6965 22:55:49.226251
6966 22:55:49.228718 [Calibration Summary] 800 Mbps
6967 22:55:49.229335 CH 0, Rank 0
6968 22:55:49.231424 SW Impedance : PASS
6969 22:55:49.235188 DUTY Scan : NO K
6970 22:55:49.235758 ZQ Calibration : PASS
6971 22:55:49.238715 Jitter Meter : NO K
6972 22:55:49.241953 CBT Training : PASS
6973 22:55:49.242422 Write leveling : PASS
6974 22:55:49.245079 RX DQS gating : PASS
6975 22:55:49.248077 RX DQ/DQS(RDDQC) : PASS
6976 22:55:49.248680 TX DQ/DQS : PASS
6977 22:55:49.251640 RX DATLAT : PASS
6978 22:55:49.255238 RX DQ/DQS(Engine): PASS
6979 22:55:49.255807 TX OE : NO K
6980 22:55:49.258202 All Pass.
6981 22:55:49.258759
6982 22:55:49.259177 CH 0, Rank 1
6983 22:55:49.261436 SW Impedance : PASS
6984 22:55:49.261902 DUTY Scan : NO K
6985 22:55:49.264836 ZQ Calibration : PASS
6986 22:55:49.268188 Jitter Meter : NO K
6987 22:55:49.268785 CBT Training : PASS
6988 22:55:49.271523 Write leveling : NO K
6989 22:55:49.274616 RX DQS gating : PASS
6990 22:55:49.275206 RX DQ/DQS(RDDQC) : PASS
6991 22:55:49.278136 TX DQ/DQS : PASS
6992 22:55:49.281182 RX DATLAT : PASS
6993 22:55:49.281649 RX DQ/DQS(Engine): PASS
6994 22:55:49.284889 TX OE : NO K
6995 22:55:49.285458 All Pass.
6996 22:55:49.285829
6997 22:55:49.288233 CH 1, Rank 0
6998 22:55:49.288697 SW Impedance : PASS
6999 22:55:49.291271 DUTY Scan : NO K
7000 22:55:49.291856 ZQ Calibration : PASS
7001 22:55:49.294640 Jitter Meter : NO K
7002 22:55:49.298030 CBT Training : PASS
7003 22:55:49.298601 Write leveling : PASS
7004 22:55:49.300915 RX DQS gating : PASS
7005 22:55:49.304446 RX DQ/DQS(RDDQC) : PASS
7006 22:55:49.304936 TX DQ/DQS : PASS
7007 22:55:49.307900 RX DATLAT : PASS
7008 22:55:49.311207 RX DQ/DQS(Engine): PASS
7009 22:55:49.311779 TX OE : NO K
7010 22:55:49.314592 All Pass.
7011 22:55:49.315162
7012 22:55:49.315533 CH 1, Rank 1
7013 22:55:49.317435 SW Impedance : PASS
7014 22:55:49.317947 DUTY Scan : NO K
7015 22:55:49.320997 ZQ Calibration : PASS
7016 22:55:49.324392 Jitter Meter : NO K
7017 22:55:49.325004 CBT Training : PASS
7018 22:55:49.327629 Write leveling : NO K
7019 22:55:49.330775 RX DQS gating : PASS
7020 22:55:49.331244 RX DQ/DQS(RDDQC) : PASS
7021 22:55:49.334233 TX DQ/DQS : PASS
7022 22:55:49.337650 RX DATLAT : PASS
7023 22:55:49.338227 RX DQ/DQS(Engine): PASS
7024 22:55:49.341285 TX OE : NO K
7025 22:55:49.341864 All Pass.
7026 22:55:49.342237
7027 22:55:49.344007 DramC Write-DBI off
7028 22:55:49.347587 PER_BANK_REFRESH: Hybrid Mode
7029 22:55:49.348186 TX_TRACKING: ON
7030 22:55:49.357182 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7031 22:55:49.360825 [FAST_K] Save calibration result to emmc
7032 22:55:49.363785 dramc_set_vcore_voltage set vcore to 725000
7033 22:55:49.367134 Read voltage for 1600, 0
7034 22:55:49.367609 Vio18 = 0
7035 22:55:49.368008 Vcore = 725000
7036 22:55:49.370978 Vdram = 0
7037 22:55:49.371553 Vddq = 0
7038 22:55:49.371931 Vmddr = 0
7039 22:55:49.377510 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7040 22:55:49.380706 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7041 22:55:49.384012 MEM_TYPE=3, freq_sel=13
7042 22:55:49.387269 sv_algorithm_assistance_LP4_3733
7043 22:55:49.390949 ============ PULL DRAM RESETB DOWN ============
7044 22:55:49.394034 ========== PULL DRAM RESETB DOWN end =========
7045 22:55:49.400515 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7046 22:55:49.403309 ===================================
7047 22:55:49.403776 LPDDR4 DRAM CONFIGURATION
7048 22:55:49.406652 ===================================
7049 22:55:49.409837 EX_ROW_EN[0] = 0x0
7050 22:55:49.413629 EX_ROW_EN[1] = 0x0
7051 22:55:49.414189 LP4Y_EN = 0x0
7052 22:55:49.416458 WORK_FSP = 0x1
7053 22:55:49.416976 WL = 0x5
7054 22:55:49.420113 RL = 0x5
7055 22:55:49.420685 BL = 0x2
7056 22:55:49.423410 RPST = 0x0
7057 22:55:49.423973 RD_PRE = 0x0
7058 22:55:49.426663 WR_PRE = 0x1
7059 22:55:49.427224 WR_PST = 0x1
7060 22:55:49.429856 DBI_WR = 0x0
7061 22:55:49.430426 DBI_RD = 0x0
7062 22:55:49.433076 OTF = 0x1
7063 22:55:49.436243 ===================================
7064 22:55:49.440053 ===================================
7065 22:55:49.440634 ANA top config
7066 22:55:49.442927 ===================================
7067 22:55:49.446147 DLL_ASYNC_EN = 0
7068 22:55:49.449640 ALL_SLAVE_EN = 0
7069 22:55:49.453077 NEW_RANK_MODE = 1
7070 22:55:49.453550 DLL_IDLE_MODE = 1
7071 22:55:49.456240 LP45_APHY_COMB_EN = 1
7072 22:55:49.459649 TX_ODT_DIS = 0
7073 22:55:49.462766 NEW_8X_MODE = 1
7074 22:55:49.466051 ===================================
7075 22:55:49.469578 ===================================
7076 22:55:49.472583 data_rate = 3200
7077 22:55:49.475930 CKR = 1
7078 22:55:49.476547 DQ_P2S_RATIO = 8
7079 22:55:49.479458 ===================================
7080 22:55:49.482658 CA_P2S_RATIO = 8
7081 22:55:49.485815 DQ_CA_OPEN = 0
7082 22:55:49.489361 DQ_SEMI_OPEN = 0
7083 22:55:49.492888 CA_SEMI_OPEN = 0
7084 22:55:49.495960 CA_FULL_RATE = 0
7085 22:55:49.496568 DQ_CKDIV4_EN = 0
7086 22:55:49.499507 CA_CKDIV4_EN = 0
7087 22:55:49.502328 CA_PREDIV_EN = 0
7088 22:55:49.505599 PH8_DLY = 12
7089 22:55:49.509140 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7090 22:55:49.512376 DQ_AAMCK_DIV = 4
7091 22:55:49.512914 CA_AAMCK_DIV = 4
7092 22:55:49.515662 CA_ADMCK_DIV = 4
7093 22:55:49.519112 DQ_TRACK_CA_EN = 0
7094 22:55:49.522306 CA_PICK = 1600
7095 22:55:49.525651 CA_MCKIO = 1600
7096 22:55:49.528755 MCKIO_SEMI = 0
7097 22:55:49.532179 PLL_FREQ = 3068
7098 22:55:49.532264 DQ_UI_PI_RATIO = 32
7099 22:55:49.535502 CA_UI_PI_RATIO = 0
7100 22:55:49.538986 ===================================
7101 22:55:49.541865 ===================================
7102 22:55:49.545517 memory_type:LPDDR4
7103 22:55:49.548568 GP_NUM : 10
7104 22:55:49.548665 SRAM_EN : 1
7105 22:55:49.551780 MD32_EN : 0
7106 22:55:49.555788 ===================================
7107 22:55:49.558515 [ANA_INIT] >>>>>>>>>>>>>>
7108 22:55:49.561453 <<<<<< [CONFIGURE PHASE]: ANA_TX
7109 22:55:49.564792 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7110 22:55:49.568432 ===================================
7111 22:55:49.568518 data_rate = 3200,PCW = 0X7600
7112 22:55:49.571831 ===================================
7113 22:55:49.574719 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7114 22:55:49.581915 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7115 22:55:49.588310 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7116 22:55:49.591616 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7117 22:55:49.594808 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7118 22:55:49.598625 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7119 22:55:49.601511 [ANA_INIT] flow start
7120 22:55:49.601595 [ANA_INIT] PLL >>>>>>>>
7121 22:55:49.604668 [ANA_INIT] PLL <<<<<<<<
7122 22:55:49.608279 [ANA_INIT] MIDPI >>>>>>>>
7123 22:55:49.611563 [ANA_INIT] MIDPI <<<<<<<<
7124 22:55:49.611647 [ANA_INIT] DLL >>>>>>>>
7125 22:55:49.614683 [ANA_INIT] DLL <<<<<<<<
7126 22:55:49.617869 [ANA_INIT] flow end
7127 22:55:49.621507 ============ LP4 DIFF to SE enter ============
7128 22:55:49.624922 ============ LP4 DIFF to SE exit ============
7129 22:55:49.628495 [ANA_INIT] <<<<<<<<<<<<<
7130 22:55:49.631166 [Flow] Enable top DCM control >>>>>
7131 22:55:49.634731 [Flow] Enable top DCM control <<<<<
7132 22:55:49.637751 Enable DLL master slave shuffle
7133 22:55:49.641304 ==============================================================
7134 22:55:49.644520 Gating Mode config
7135 22:55:49.647717 ==============================================================
7136 22:55:49.651023 Config description:
7137 22:55:49.661065 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7138 22:55:49.667683 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7139 22:55:49.670851 SELPH_MODE 0: By rank 1: By Phase
7140 22:55:49.677511 ==============================================================
7141 22:55:49.680771 GAT_TRACK_EN = 1
7142 22:55:49.684120 RX_GATING_MODE = 2
7143 22:55:49.687616 RX_GATING_TRACK_MODE = 2
7144 22:55:49.690695 SELPH_MODE = 1
7145 22:55:49.694329 PICG_EARLY_EN = 1
7146 22:55:49.694413 VALID_LAT_VALUE = 1
7147 22:55:49.700751 ==============================================================
7148 22:55:49.704432 Enter into Gating configuration >>>>
7149 22:55:49.708022 Exit from Gating configuration <<<<
7150 22:55:49.710671 Enter into DVFS_PRE_config >>>>>
7151 22:55:49.723849 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7152 22:55:49.723935 Exit from DVFS_PRE_config <<<<<
7153 22:55:49.727165 Enter into PICG configuration >>>>
7154 22:55:49.730270 Exit from PICG configuration <<<<
7155 22:55:49.733883 [RX_INPUT] configuration >>>>>
7156 22:55:49.737268 [RX_INPUT] configuration <<<<<
7157 22:55:49.743595 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7158 22:55:49.746937 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7159 22:55:49.753990 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7160 22:55:49.760269 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7161 22:55:49.767012 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7162 22:55:49.774188 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7163 22:55:49.777199 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7164 22:55:49.780063 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7165 22:55:49.783325 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7166 22:55:49.789791 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7167 22:55:49.793306 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7168 22:55:49.796648 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7169 22:55:49.800287 ===================================
7170 22:55:49.803403 LPDDR4 DRAM CONFIGURATION
7171 22:55:49.806494 ===================================
7172 22:55:49.810633 EX_ROW_EN[0] = 0x0
7173 22:55:49.810717 EX_ROW_EN[1] = 0x0
7174 22:55:49.813293 LP4Y_EN = 0x0
7175 22:55:49.813406 WORK_FSP = 0x1
7176 22:55:49.816616 WL = 0x5
7177 22:55:49.816724 RL = 0x5
7178 22:55:49.819514 BL = 0x2
7179 22:55:49.819621 RPST = 0x0
7180 22:55:49.823491 RD_PRE = 0x0
7181 22:55:49.823596 WR_PRE = 0x1
7182 22:55:49.826539 WR_PST = 0x1
7183 22:55:49.826639 DBI_WR = 0x0
7184 22:55:49.829559 DBI_RD = 0x0
7185 22:55:49.829663 OTF = 0x1
7186 22:55:49.833168 ===================================
7187 22:55:49.836335 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7188 22:55:49.843166 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7189 22:55:49.846449 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7190 22:55:49.849639 ===================================
7191 22:55:49.853213 LPDDR4 DRAM CONFIGURATION
7192 22:55:49.856484 ===================================
7193 22:55:49.856562 EX_ROW_EN[0] = 0x10
7194 22:55:49.859524 EX_ROW_EN[1] = 0x0
7195 22:55:49.863199 LP4Y_EN = 0x0
7196 22:55:49.863370 WORK_FSP = 0x1
7197 22:55:49.866274 WL = 0x5
7198 22:55:49.866396 RL = 0x5
7199 22:55:49.869516 BL = 0x2
7200 22:55:49.869622 RPST = 0x0
7201 22:55:49.873068 RD_PRE = 0x0
7202 22:55:49.873173 WR_PRE = 0x1
7203 22:55:49.876609 WR_PST = 0x1
7204 22:55:49.876721 DBI_WR = 0x0
7205 22:55:49.879729 DBI_RD = 0x0
7206 22:55:49.879840 OTF = 0x1
7207 22:55:49.882992 ===================================
7208 22:55:49.889935 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7209 22:55:49.890154 ==
7210 22:55:49.892826 Dram Type= 6, Freq= 0, CH_0, rank 0
7211 22:55:49.896294 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7212 22:55:49.899430 ==
7213 22:55:49.899703 [Duty_Offset_Calibration]
7214 22:55:49.903155 B0:2 B1:0 CA:1
7215 22:55:49.903431
7216 22:55:49.905845 [DutyScan_Calibration_Flow] k_type=0
7217 22:55:49.914100
7218 22:55:49.914182 ==CLK 0==
7219 22:55:49.917635 Final CLK duty delay cell = -4
7220 22:55:49.921126 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7221 22:55:49.924170 [-4] MIN Duty = 4813%(X100), DQS PI = 62
7222 22:55:49.927757 [-4] AVG Duty = 4922%(X100)
7223 22:55:49.927940
7224 22:55:49.930654 CH0 CLK Duty spec in!! Max-Min= 218%
7225 22:55:49.934232 [DutyScan_Calibration_Flow] ====Done====
7226 22:55:49.934431
7227 22:55:49.937172 [DutyScan_Calibration_Flow] k_type=1
7228 22:55:49.954297
7229 22:55:49.954556 ==DQS 0 ==
7230 22:55:49.957400 Final DQS duty delay cell = 0
7231 22:55:49.960689 [0] MAX Duty = 5249%(X100), DQS PI = 32
7232 22:55:49.963793 [0] MIN Duty = 4969%(X100), DQS PI = 2
7233 22:55:49.967563 [0] AVG Duty = 5109%(X100)
7234 22:55:49.967971
7235 22:55:49.968247 ==DQS 1 ==
7236 22:55:49.970526 Final DQS duty delay cell = -4
7237 22:55:49.973724 [-4] MAX Duty = 5125%(X100), DQS PI = 28
7238 22:55:49.977233 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7239 22:55:49.980762 [-4] AVG Duty = 5000%(X100)
7240 22:55:49.981278
7241 22:55:49.984338 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7242 22:55:49.984989
7243 22:55:49.987726 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7244 22:55:49.990451 [DutyScan_Calibration_Flow] ====Done====
7245 22:55:49.990930
7246 22:55:49.994023 [DutyScan_Calibration_Flow] k_type=3
7247 22:55:50.010994
7248 22:55:50.011576 ==DQM 0 ==
7249 22:55:50.014021 Final DQM duty delay cell = 0
7250 22:55:50.017272 [0] MAX Duty = 5124%(X100), DQS PI = 26
7251 22:55:50.020571 [0] MIN Duty = 4844%(X100), DQS PI = 0
7252 22:55:50.021197 [0] AVG Duty = 4984%(X100)
7253 22:55:50.024070
7254 22:55:50.024651 ==DQM 1 ==
7255 22:55:50.027450 Final DQM duty delay cell = -4
7256 22:55:50.030521 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7257 22:55:50.033932 [-4] MIN Duty = 4751%(X100), DQS PI = 18
7258 22:55:50.037141 [-4] AVG Duty = 4891%(X100)
7259 22:55:50.037623
7260 22:55:50.040423 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7261 22:55:50.040944
7262 22:55:50.043896 CH0 DQM 1 Duty spec in!! Max-Min= 280%
7263 22:55:50.047275 [DutyScan_Calibration_Flow] ====Done====
7264 22:55:50.047757
7265 22:55:50.050303 [DutyScan_Calibration_Flow] k_type=2
7266 22:55:50.067973
7267 22:55:50.068518 ==DQ 0 ==
7268 22:55:50.071714 Final DQ duty delay cell = 0
7269 22:55:50.074632 [0] MAX Duty = 5124%(X100), DQS PI = 30
7270 22:55:50.077934 [0] MIN Duty = 5000%(X100), DQS PI = 18
7271 22:55:50.078418 [0] AVG Duty = 5062%(X100)
7272 22:55:50.081584
7273 22:55:50.082050 ==DQ 1 ==
7274 22:55:50.084573 Final DQ duty delay cell = 0
7275 22:55:50.087918 [0] MAX Duty = 4969%(X100), DQS PI = 42
7276 22:55:50.091359 [0] MIN Duty = 4875%(X100), DQS PI = 0
7277 22:55:50.091941 [0] AVG Duty = 4922%(X100)
7278 22:55:50.094647
7279 22:55:50.098061 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7280 22:55:50.098646
7281 22:55:50.101101 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7282 22:55:50.104629 [DutyScan_Calibration_Flow] ====Done====
7283 22:55:50.105314 ==
7284 22:55:50.108003 Dram Type= 6, Freq= 0, CH_1, rank 0
7285 22:55:50.111215 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7286 22:55:50.111802 ==
7287 22:55:50.114777 [Duty_Offset_Calibration]
7288 22:55:50.115348 B0:0 B1:-1 CA:2
7289 22:55:50.115723
7290 22:55:50.117915 [DutyScan_Calibration_Flow] k_type=0
7291 22:55:50.128828
7292 22:55:50.129402 ==CLK 0==
7293 22:55:50.131418 Final CLK duty delay cell = 0
7294 22:55:50.134759 [0] MAX Duty = 5156%(X100), DQS PI = 42
7295 22:55:50.137928 [0] MIN Duty = 4906%(X100), DQS PI = 12
7296 22:55:50.141400 [0] AVG Duty = 5031%(X100)
7297 22:55:50.141859
7298 22:55:50.144499 CH1 CLK Duty spec in!! Max-Min= 250%
7299 22:55:50.148093 [DutyScan_Calibration_Flow] ====Done====
7300 22:55:50.148548
7301 22:55:50.151284 [DutyScan_Calibration_Flow] k_type=1
7302 22:55:50.168528
7303 22:55:50.169280 ==DQS 0 ==
7304 22:55:50.171447 Final DQS duty delay cell = 0
7305 22:55:50.174721 [0] MAX Duty = 5062%(X100), DQS PI = 8
7306 22:55:50.177708 [0] MIN Duty = 5000%(X100), DQS PI = 0
7307 22:55:50.178171 [0] AVG Duty = 5031%(X100)
7308 22:55:50.181434
7309 22:55:50.181989 ==DQS 1 ==
7310 22:55:50.184664 Final DQS duty delay cell = 0
7311 22:55:50.187629 [0] MAX Duty = 5187%(X100), DQS PI = 26
7312 22:55:50.190904 [0] MIN Duty = 4813%(X100), DQS PI = 2
7313 22:55:50.194594 [0] AVG Duty = 5000%(X100)
7314 22:55:50.195157
7315 22:55:50.197791 CH1 DQS 0 Duty spec in!! Max-Min= 62%
7316 22:55:50.198254
7317 22:55:50.201216 CH1 DQS 1 Duty spec in!! Max-Min= 374%
7318 22:55:50.204397 [DutyScan_Calibration_Flow] ====Done====
7319 22:55:50.205023
7320 22:55:50.207664 [DutyScan_Calibration_Flow] k_type=3
7321 22:55:50.225667
7322 22:55:50.226223 ==DQM 0 ==
7323 22:55:50.229348 Final DQM duty delay cell = 4
7324 22:55:50.232756 [4] MAX Duty = 5125%(X100), DQS PI = 22
7325 22:55:50.235566 [4] MIN Duty = 4969%(X100), DQS PI = 0
7326 22:55:50.238739 [4] AVG Duty = 5047%(X100)
7327 22:55:50.239200
7328 22:55:50.239563 ==DQM 1 ==
7329 22:55:50.241651 Final DQM duty delay cell = 0
7330 22:55:50.245307 [0] MAX Duty = 5343%(X100), DQS PI = 28
7331 22:55:50.248321 [0] MIN Duty = 4907%(X100), DQS PI = 2
7332 22:55:50.251952 [0] AVG Duty = 5125%(X100)
7333 22:55:50.252411
7334 22:55:50.254981 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7335 22:55:50.255450
7336 22:55:50.258360 CH1 DQM 1 Duty spec in!! Max-Min= 436%
7337 22:55:50.261756 [DutyScan_Calibration_Flow] ====Done====
7338 22:55:50.262214
7339 22:55:50.265082 [DutyScan_Calibration_Flow] k_type=2
7340 22:55:50.281625
7341 22:55:50.281807 ==DQ 0 ==
7342 22:55:50.284956 Final DQ duty delay cell = 0
7343 22:55:50.288276 [0] MAX Duty = 5093%(X100), DQS PI = 22
7344 22:55:50.291880 [0] MIN Duty = 4938%(X100), DQS PI = 0
7345 22:55:50.292000 [0] AVG Duty = 5015%(X100)
7346 22:55:50.295245
7347 22:55:50.295377 ==DQ 1 ==
7348 22:55:50.298304 Final DQ duty delay cell = 0
7349 22:55:50.301396 [0] MAX Duty = 5094%(X100), DQS PI = 34
7350 22:55:50.304595 [0] MIN Duty = 4813%(X100), DQS PI = 2
7351 22:55:50.304713 [0] AVG Duty = 4953%(X100)
7352 22:55:50.304822
7353 22:55:50.308186 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7354 22:55:50.311159
7355 22:55:50.314886 CH1 DQ 1 Duty spec in!! Max-Min= 281%
7356 22:55:50.317821 [DutyScan_Calibration_Flow] ====Done====
7357 22:55:50.321151 nWR fixed to 30
7358 22:55:50.321235 [ModeRegInit_LP4] CH0 RK0
7359 22:55:50.324824 [ModeRegInit_LP4] CH0 RK1
7360 22:55:50.327920 [ModeRegInit_LP4] CH1 RK0
7361 22:55:50.331228 [ModeRegInit_LP4] CH1 RK1
7362 22:55:50.331326 match AC timing 5
7363 22:55:50.337844 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7364 22:55:50.341182 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7365 22:55:50.344564 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7366 22:55:50.351117 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7367 22:55:50.354279 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7368 22:55:50.354350 [MiockJmeterHQA]
7369 22:55:50.354411
7370 22:55:50.357266 [DramcMiockJmeter] u1RxGatingPI = 0
7371 22:55:50.360861 0 : 4365, 4140
7372 22:55:50.360937 4 : 4252, 4027
7373 22:55:50.364049 8 : 4252, 4027
7374 22:55:50.364121 12 : 4252, 4027
7375 22:55:50.367376 16 : 4255, 4029
7376 22:55:50.367477 20 : 4253, 4026
7377 22:55:50.367569 24 : 4252, 4026
7378 22:55:50.370713 28 : 4360, 4138
7379 22:55:50.370795 32 : 4250, 4026
7380 22:55:50.374091 36 : 4250, 4027
7381 22:55:50.374163 40 : 4249, 4027
7382 22:55:50.377168 44 : 4253, 4029
7383 22:55:50.377243 48 : 4250, 4027
7384 22:55:50.380421 52 : 4250, 4026
7385 22:55:50.380500 56 : 4363, 4139
7386 22:55:50.380565 60 : 4249, 4027
7387 22:55:50.383832 64 : 4253, 4029
7388 22:55:50.383931 68 : 4250, 4027
7389 22:55:50.387295 72 : 4361, 4137
7390 22:55:50.387397 76 : 4250, 4026
7391 22:55:50.390430 80 : 4250, 4027
7392 22:55:50.390501 84 : 4252, 4029
7393 22:55:50.390574 88 : 4250, 3450
7394 22:55:50.394167 92 : 4253, 0
7395 22:55:50.394237 96 : 4250, 0
7396 22:55:50.397430 100 : 4250, 0
7397 22:55:50.397508 104 : 4363, 0
7398 22:55:50.397572 108 : 4250, 0
7399 22:55:50.400822 112 : 4250, 0
7400 22:55:50.400897 116 : 4253, 0
7401 22:55:50.403660 120 : 4250, 0
7402 22:55:50.403757 124 : 4250, 0
7403 22:55:50.403851 128 : 4250, 0
7404 22:55:50.407232 132 : 4250, 0
7405 22:55:50.407332 136 : 4360, 0
7406 22:55:50.407422 140 : 4361, 0
7407 22:55:50.410259 144 : 4364, 0
7408 22:55:50.410356 148 : 4250, 0
7409 22:55:50.413798 152 : 4253, 0
7410 22:55:50.413879 156 : 4250, 0
7411 22:55:50.413943 160 : 4250, 0
7412 22:55:50.416885 164 : 4250, 0
7413 22:55:50.416960 168 : 4250, 0
7414 22:55:50.420397 172 : 4252, 0
7415 22:55:50.420474 176 : 4250, 0
7416 22:55:50.420549 180 : 4250, 0
7417 22:55:50.423645 184 : 4250, 0
7418 22:55:50.423750 188 : 4250, 0
7419 22:55:50.427105 192 : 4361, 0
7420 22:55:50.427192 196 : 4360, 0
7421 22:55:50.427267 200 : 4250, 2
7422 22:55:50.430345 204 : 4250, 2494
7423 22:55:50.430420 208 : 4250, 4027
7424 22:55:50.433541 212 : 4250, 4027
7425 22:55:50.433617 216 : 4250, 4026
7426 22:55:50.436867 220 : 4255, 4029
7427 22:55:50.436938 224 : 4250, 4027
7428 22:55:50.440098 228 : 4361, 4137
7429 22:55:50.440174 232 : 4252, 4029
7430 22:55:50.443670 236 : 4361, 4137
7431 22:55:50.443776 240 : 4250, 4027
7432 22:55:50.447065 244 : 4252, 4030
7433 22:55:50.447163 248 : 4255, 4032
7434 22:55:50.447254 252 : 4250, 4026
7435 22:55:50.449999 256 : 4255, 4029
7436 22:55:50.450075 260 : 4360, 4137
7437 22:55:50.453414 264 : 4249, 4027
7438 22:55:50.453487 268 : 4250, 4026
7439 22:55:50.456670 272 : 4255, 4029
7440 22:55:50.456785 276 : 4250, 4027
7441 22:55:50.460137 280 : 4362, 4137
7442 22:55:50.460210 284 : 4250, 4026
7443 22:55:50.463555 288 : 4363, 4137
7444 22:55:50.463654 292 : 4250, 4027
7445 22:55:50.467033 296 : 4250, 4027
7446 22:55:50.467107 300 : 4254, 4032
7447 22:55:50.470055 304 : 4250, 4026
7448 22:55:50.470135 308 : 4255, 4029
7449 22:55:50.470200 312 : 4360, 3903
7450 22:55:50.473568 316 : 4249, 1808
7451 22:55:50.473647
7452 22:55:50.476689 MIOCK jitter meter ch=0
7453 22:55:50.476824
7454 22:55:50.479896 1T = (316-92) = 224 dly cells
7455 22:55:50.483454 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7456 22:55:50.483555 ==
7457 22:55:50.486379 Dram Type= 6, Freq= 0, CH_0, rank 0
7458 22:55:50.493316 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7459 22:55:50.493398 ==
7460 22:55:50.496501 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7461 22:55:50.503032 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7462 22:55:50.506217 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7463 22:55:50.512853 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7464 22:55:50.520250 [CA 0] Center 43 (13~73) winsize 61
7465 22:55:50.524068 [CA 1] Center 43 (13~73) winsize 61
7466 22:55:50.527053 [CA 2] Center 38 (8~68) winsize 61
7467 22:55:50.530445 [CA 3] Center 37 (8~67) winsize 60
7468 22:55:50.533526 [CA 4] Center 36 (6~66) winsize 61
7469 22:55:50.536929 [CA 5] Center 35 (5~65) winsize 61
7470 22:55:50.537003
7471 22:55:50.540336 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7472 22:55:50.540404
7473 22:55:50.544236 [CATrainingPosCal] consider 1 rank data
7474 22:55:50.546975 u2DelayCellTimex100 = 290/100 ps
7475 22:55:50.553537 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7476 22:55:50.556574 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7477 22:55:50.560011 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7478 22:55:50.563515 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7479 22:55:50.566530 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7480 22:55:50.570187 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7481 22:55:50.570273
7482 22:55:50.573280 CA PerBit enable=1, Macro0, CA PI delay=35
7483 22:55:50.573358
7484 22:55:50.576296 [CBTSetCACLKResult] CA Dly = 35
7485 22:55:50.579982 CS Dly: 9 (0~40)
7486 22:55:50.583104 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7487 22:55:50.586345 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7488 22:55:50.586418 ==
7489 22:55:50.589643 Dram Type= 6, Freq= 0, CH_0, rank 1
7490 22:55:50.596061 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7491 22:55:50.596137 ==
7492 22:55:50.599711 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7493 22:55:50.606510 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7494 22:55:50.609635 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7495 22:55:50.616259 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7496 22:55:50.624115 [CA 0] Center 43 (13~74) winsize 62
7497 22:55:50.627093 [CA 1] Center 43 (13~73) winsize 61
7498 22:55:50.630221 [CA 2] Center 38 (9~68) winsize 60
7499 22:55:50.633849 [CA 3] Center 38 (9~68) winsize 60
7500 22:55:50.636929 [CA 4] Center 37 (7~67) winsize 61
7501 22:55:50.640362 [CA 5] Center 36 (6~66) winsize 61
7502 22:55:50.640434
7503 22:55:50.643727 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7504 22:55:50.643806
7505 22:55:50.647165 [CATrainingPosCal] consider 2 rank data
7506 22:55:50.650150 u2DelayCellTimex100 = 290/100 ps
7507 22:55:50.653517 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7508 22:55:50.660075 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7509 22:55:50.663547 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7510 22:55:50.666870 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7511 22:55:50.669958 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7512 22:55:50.673581 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7513 22:55:50.673685
7514 22:55:50.676944 CA PerBit enable=1, Macro0, CA PI delay=35
7515 22:55:50.677053
7516 22:55:50.680198 [CBTSetCACLKResult] CA Dly = 35
7517 22:55:50.683421 CS Dly: 10 (0~43)
7518 22:55:50.686667 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7519 22:55:50.690346 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7520 22:55:50.690420
7521 22:55:50.693570 ----->DramcWriteLeveling(PI) begin...
7522 22:55:50.693662 ==
7523 22:55:50.696718 Dram Type= 6, Freq= 0, CH_0, rank 0
7524 22:55:50.703363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7525 22:55:50.703447 ==
7526 22:55:50.706710 Write leveling (Byte 0): 38 => 38
7527 22:55:50.706798 Write leveling (Byte 1): 31 => 31
7528 22:55:50.710315 DramcWriteLeveling(PI) end<-----
7529 22:55:50.710399
7530 22:55:50.713153 ==
7531 22:55:50.713237 Dram Type= 6, Freq= 0, CH_0, rank 0
7532 22:55:50.720163 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7533 22:55:50.720294 ==
7534 22:55:50.723328 [Gating] SW mode calibration
7535 22:55:50.730063 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7536 22:55:50.733123 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7537 22:55:50.739561 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7538 22:55:50.742860 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7539 22:55:50.746291 1 4 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
7540 22:55:50.752903 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7541 22:55:50.756491 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7542 22:55:50.759629 1 4 20 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
7543 22:55:50.766142 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7544 22:55:50.769475 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7545 22:55:50.772739 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7546 22:55:50.779731 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7547 22:55:50.783175 1 5 8 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
7548 22:55:50.786234 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
7549 22:55:50.792782 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
7550 22:55:50.796117 1 5 20 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
7551 22:55:50.799354 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7552 22:55:50.806077 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7553 22:55:50.809443 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7554 22:55:50.812517 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7555 22:55:50.819278 1 6 8 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
7556 22:55:50.822744 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7557 22:55:50.825976 1 6 16 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7558 22:55:50.832505 1 6 20 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7559 22:55:50.835973 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7560 22:55:50.839458 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7561 22:55:50.846050 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7562 22:55:50.848785 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7563 22:55:50.852549 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7564 22:55:50.858708 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7565 22:55:50.862227 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7566 22:55:50.865755 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7567 22:55:50.871871 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7568 22:55:50.875107 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7569 22:55:50.878772 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7570 22:55:50.885221 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 22:55:50.888761 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 22:55:50.892037 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 22:55:50.898450 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 22:55:50.901664 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 22:55:50.905041 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 22:55:50.912085 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 22:55:50.915121 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 22:55:50.918572 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 22:55:50.924991 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7580 22:55:50.928563 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7581 22:55:50.931752 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7582 22:55:50.935188 Total UI for P1: 0, mck2ui 16
7583 22:55:50.938447 best dqsien dly found for B0: ( 1, 9, 10)
7584 22:55:50.944860 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7585 22:55:50.948298 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7586 22:55:50.951427 Total UI for P1: 0, mck2ui 16
7587 22:55:50.955284 best dqsien dly found for B1: ( 1, 9, 18)
7588 22:55:50.958092 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7589 22:55:50.961377 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7590 22:55:50.961993
7591 22:55:50.964960 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7592 22:55:50.968182 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7593 22:55:50.971349 [Gating] SW calibration Done
7594 22:55:50.971822 ==
7595 22:55:50.975120 Dram Type= 6, Freq= 0, CH_0, rank 0
7596 22:55:50.978284 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7597 22:55:50.981458 ==
7598 22:55:50.981950 RX Vref Scan: 0
7599 22:55:50.982328
7600 22:55:50.984579 RX Vref 0 -> 0, step: 1
7601 22:55:50.985094
7602 22:55:50.985466 RX Delay 0 -> 252, step: 8
7603 22:55:50.991520 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7604 22:55:50.994316 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7605 22:55:50.997593 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7606 22:55:51.001276 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7607 22:55:51.004423 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7608 22:55:51.011136 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7609 22:55:51.014057 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7610 22:55:51.017656 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7611 22:55:51.020861 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7612 22:55:51.024529 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7613 22:55:51.030986 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7614 22:55:51.034361 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7615 22:55:51.037535 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7616 22:55:51.041005 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7617 22:55:51.047644 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7618 22:55:51.050770 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7619 22:55:51.051292 ==
7620 22:55:51.053692 Dram Type= 6, Freq= 0, CH_0, rank 0
7621 22:55:51.057689 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7622 22:55:51.058273 ==
7623 22:55:51.058652 DQS Delay:
7624 22:55:51.060450 DQS0 = 0, DQS1 = 0
7625 22:55:51.060952 DQM Delay:
7626 22:55:51.064156 DQM0 = 138, DQM1 = 127
7627 22:55:51.064840 DQ Delay:
7628 22:55:51.067575 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7629 22:55:51.070645 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7630 22:55:51.074068 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7631 22:55:51.080942 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7632 22:55:51.081502
7633 22:55:51.081877
7634 22:55:51.082223 ==
7635 22:55:51.084035 Dram Type= 6, Freq= 0, CH_0, rank 0
7636 22:55:51.087184 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7637 22:55:51.087754 ==
7638 22:55:51.088130
7639 22:55:51.088474
7640 22:55:51.090907 TX Vref Scan disable
7641 22:55:51.091492 == TX Byte 0 ==
7642 22:55:51.096551 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7643 22:55:51.099890 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7644 22:55:51.100636 == TX Byte 1 ==
7645 22:55:51.106633 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7646 22:55:51.110337 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7647 22:55:51.110809 ==
7648 22:55:51.113775 Dram Type= 6, Freq= 0, CH_0, rank 0
7649 22:55:51.116904 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7650 22:55:51.117377 ==
7651 22:55:51.131524
7652 22:55:51.134361 TX Vref early break, caculate TX vref
7653 22:55:51.137842 TX Vref=16, minBit 0, minWin=23, winSum=380
7654 22:55:51.141275 TX Vref=18, minBit 0, minWin=23, winSum=386
7655 22:55:51.144221 TX Vref=20, minBit 0, minWin=24, winSum=397
7656 22:55:51.147213 TX Vref=22, minBit 7, minWin=24, winSum=408
7657 22:55:51.150869 TX Vref=24, minBit 2, minWin=25, winSum=418
7658 22:55:51.157272 TX Vref=26, minBit 0, minWin=26, winSum=425
7659 22:55:51.160469 TX Vref=28, minBit 2, minWin=25, winSum=427
7660 22:55:51.163902 TX Vref=30, minBit 2, minWin=25, winSum=419
7661 22:55:51.166968 TX Vref=32, minBit 2, minWin=25, winSum=410
7662 22:55:51.170241 TX Vref=34, minBit 3, minWin=24, winSum=398
7663 22:55:51.177074 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 26
7664 22:55:51.177157
7665 22:55:51.179999 Final TX Range 0 Vref 26
7666 22:55:51.180082
7667 22:55:51.180174 ==
7668 22:55:51.183425 Dram Type= 6, Freq= 0, CH_0, rank 0
7669 22:55:51.186671 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7670 22:55:51.186755 ==
7671 22:55:51.186821
7672 22:55:51.186881
7673 22:55:51.190039 TX Vref Scan disable
7674 22:55:51.196647 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7675 22:55:51.196756 == TX Byte 0 ==
7676 22:55:51.199997 u2DelayCellOfst[0]=13 cells (4 PI)
7677 22:55:51.203465 u2DelayCellOfst[1]=16 cells (5 PI)
7678 22:55:51.206571 u2DelayCellOfst[2]=13 cells (4 PI)
7679 22:55:51.209712 u2DelayCellOfst[3]=13 cells (4 PI)
7680 22:55:51.213441 u2DelayCellOfst[4]=6 cells (2 PI)
7681 22:55:51.216624 u2DelayCellOfst[5]=0 cells (0 PI)
7682 22:55:51.219687 u2DelayCellOfst[6]=16 cells (5 PI)
7683 22:55:51.223161 u2DelayCellOfst[7]=16 cells (5 PI)
7684 22:55:51.226543 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7685 22:55:51.229618 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7686 22:55:51.233229 == TX Byte 1 ==
7687 22:55:51.236277 u2DelayCellOfst[8]=0 cells (0 PI)
7688 22:55:51.239916 u2DelayCellOfst[9]=0 cells (0 PI)
7689 22:55:51.240001 u2DelayCellOfst[10]=6 cells (2 PI)
7690 22:55:51.242924 u2DelayCellOfst[11]=3 cells (1 PI)
7691 22:55:51.246171 u2DelayCellOfst[12]=10 cells (3 PI)
7692 22:55:51.249484 u2DelayCellOfst[13]=10 cells (3 PI)
7693 22:55:51.252871 u2DelayCellOfst[14]=16 cells (5 PI)
7694 22:55:51.256086 u2DelayCellOfst[15]=10 cells (3 PI)
7695 22:55:51.262933 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7696 22:55:51.266270 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7697 22:55:51.266354 DramC Write-DBI on
7698 22:55:51.266421 ==
7699 22:55:51.269589 Dram Type= 6, Freq= 0, CH_0, rank 0
7700 22:55:51.275715 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7701 22:55:51.275841 ==
7702 22:55:51.275915
7703 22:55:51.275982
7704 22:55:51.276050 TX Vref Scan disable
7705 22:55:51.280156 == TX Byte 0 ==
7706 22:55:51.283401 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7707 22:55:51.286734 == TX Byte 1 ==
7708 22:55:51.290007 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7709 22:55:51.293191 DramC Write-DBI off
7710 22:55:51.293310
7711 22:55:51.293439 [DATLAT]
7712 22:55:51.293531 Freq=1600, CH0 RK0
7713 22:55:51.293620
7714 22:55:51.296652 DATLAT Default: 0xf
7715 22:55:51.300454 0, 0xFFFF, sum = 0
7716 22:55:51.300561 1, 0xFFFF, sum = 0
7717 22:55:51.303359 2, 0xFFFF, sum = 0
7718 22:55:51.303473 3, 0xFFFF, sum = 0
7719 22:55:51.306560 4, 0xFFFF, sum = 0
7720 22:55:51.306638 5, 0xFFFF, sum = 0
7721 22:55:51.310001 6, 0xFFFF, sum = 0
7722 22:55:51.310078 7, 0xFFFF, sum = 0
7723 22:55:51.312835 8, 0xFFFF, sum = 0
7724 22:55:51.312925 9, 0xFFFF, sum = 0
7725 22:55:51.316163 10, 0xFFFF, sum = 0
7726 22:55:51.316235 11, 0xFFFF, sum = 0
7727 22:55:51.319807 12, 0xFFFF, sum = 0
7728 22:55:51.319878 13, 0xFFFF, sum = 0
7729 22:55:51.322895 14, 0x0, sum = 1
7730 22:55:51.322971 15, 0x0, sum = 2
7731 22:55:51.326074 16, 0x0, sum = 3
7732 22:55:51.326146 17, 0x0, sum = 4
7733 22:55:51.329801 best_step = 15
7734 22:55:51.329869
7735 22:55:51.329932 ==
7736 22:55:51.332847 Dram Type= 6, Freq= 0, CH_0, rank 0
7737 22:55:51.336436 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7738 22:55:51.336517 ==
7739 22:55:51.339412 RX Vref Scan: 1
7740 22:55:51.339484
7741 22:55:51.339545 Set Vref Range= 24 -> 127
7742 22:55:51.339609
7743 22:55:51.342891 RX Vref 24 -> 127, step: 1
7744 22:55:51.342959
7745 22:55:51.346245 RX Delay 19 -> 252, step: 4
7746 22:55:51.346314
7747 22:55:51.349502 Set Vref, RX VrefLevel [Byte0]: 24
7748 22:55:51.352679 [Byte1]: 24
7749 22:55:51.352752
7750 22:55:51.356362 Set Vref, RX VrefLevel [Byte0]: 25
7751 22:55:51.359399 [Byte1]: 25
7752 22:55:51.362752
7753 22:55:51.362823 Set Vref, RX VrefLevel [Byte0]: 26
7754 22:55:51.366015 [Byte1]: 26
7755 22:55:51.370359
7756 22:55:51.370441 Set Vref, RX VrefLevel [Byte0]: 27
7757 22:55:51.373660 [Byte1]: 27
7758 22:55:51.377718
7759 22:55:51.377790 Set Vref, RX VrefLevel [Byte0]: 28
7760 22:55:51.381330 [Byte1]: 28
7761 22:55:51.385620
7762 22:55:51.385688 Set Vref, RX VrefLevel [Byte0]: 29
7763 22:55:51.389066 [Byte1]: 29
7764 22:55:51.393083
7765 22:55:51.393153 Set Vref, RX VrefLevel [Byte0]: 30
7766 22:55:51.396155 [Byte1]: 30
7767 22:55:51.400613
7768 22:55:51.400701 Set Vref, RX VrefLevel [Byte0]: 31
7769 22:55:51.404069 [Byte1]: 31
7770 22:55:51.408200
7771 22:55:51.408270 Set Vref, RX VrefLevel [Byte0]: 32
7772 22:55:51.411601 [Byte1]: 32
7773 22:55:51.415942
7774 22:55:51.416013 Set Vref, RX VrefLevel [Byte0]: 33
7775 22:55:51.419169 [Byte1]: 33
7776 22:55:51.423522
7777 22:55:51.423600 Set Vref, RX VrefLevel [Byte0]: 34
7778 22:55:51.426821 [Byte1]: 34
7779 22:55:51.430934
7780 22:55:51.431045 Set Vref, RX VrefLevel [Byte0]: 35
7781 22:55:51.434571 [Byte1]: 35
7782 22:55:51.438429
7783 22:55:51.438537 Set Vref, RX VrefLevel [Byte0]: 36
7784 22:55:51.442044 [Byte1]: 36
7785 22:55:51.446110
7786 22:55:51.449270 Set Vref, RX VrefLevel [Byte0]: 37
7787 22:55:51.449345 [Byte1]: 37
7788 22:55:51.453566
7789 22:55:51.453640 Set Vref, RX VrefLevel [Byte0]: 38
7790 22:55:51.457038 [Byte1]: 38
7791 22:55:51.461175
7792 22:55:51.461246 Set Vref, RX VrefLevel [Byte0]: 39
7793 22:55:51.464407 [Byte1]: 39
7794 22:55:51.468794
7795 22:55:51.468882 Set Vref, RX VrefLevel [Byte0]: 40
7796 22:55:51.472172 [Byte1]: 40
7797 22:55:51.476377
7798 22:55:51.476490 Set Vref, RX VrefLevel [Byte0]: 41
7799 22:55:51.479541 [Byte1]: 41
7800 22:55:51.484179
7801 22:55:51.484255 Set Vref, RX VrefLevel [Byte0]: 42
7802 22:55:51.487510 [Byte1]: 42
7803 22:55:51.491809
7804 22:55:51.491881 Set Vref, RX VrefLevel [Byte0]: 43
7805 22:55:51.495113 [Byte1]: 43
7806 22:55:51.498905
7807 22:55:51.498977 Set Vref, RX VrefLevel [Byte0]: 44
7808 22:55:51.502298 [Byte1]: 44
7809 22:55:51.506819
7810 22:55:51.506890 Set Vref, RX VrefLevel [Byte0]: 45
7811 22:55:51.509921 [Byte1]: 45
7812 22:55:51.514509
7813 22:55:51.514585 Set Vref, RX VrefLevel [Byte0]: 46
7814 22:55:51.517569 [Byte1]: 46
7815 22:55:51.522156
7816 22:55:51.522236 Set Vref, RX VrefLevel [Byte0]: 47
7817 22:55:51.524920 [Byte1]: 47
7818 22:55:51.529526
7819 22:55:51.529609 Set Vref, RX VrefLevel [Byte0]: 48
7820 22:55:51.532469 [Byte1]: 48
7821 22:55:51.537100
7822 22:55:51.537178 Set Vref, RX VrefLevel [Byte0]: 49
7823 22:55:51.540121 [Byte1]: 49
7824 22:55:51.544609
7825 22:55:51.544689 Set Vref, RX VrefLevel [Byte0]: 50
7826 22:55:51.547909 [Byte1]: 50
7827 22:55:51.552176
7828 22:55:51.552258 Set Vref, RX VrefLevel [Byte0]: 51
7829 22:55:51.555297 [Byte1]: 51
7830 22:55:51.559528
7831 22:55:51.559602 Set Vref, RX VrefLevel [Byte0]: 52
7832 22:55:51.562957 [Byte1]: 52
7833 22:55:51.567489
7834 22:55:51.567561 Set Vref, RX VrefLevel [Byte0]: 53
7835 22:55:51.570361 [Byte1]: 53
7836 22:55:51.574842
7837 22:55:51.574926 Set Vref, RX VrefLevel [Byte0]: 54
7838 22:55:51.578012 [Byte1]: 54
7839 22:55:51.582378
7840 22:55:51.582467 Set Vref, RX VrefLevel [Byte0]: 55
7841 22:55:51.585844 [Byte1]: 55
7842 22:55:51.590091
7843 22:55:51.590170 Set Vref, RX VrefLevel [Byte0]: 56
7844 22:55:51.593401 [Byte1]: 56
7845 22:55:51.597324
7846 22:55:51.597403 Set Vref, RX VrefLevel [Byte0]: 57
7847 22:55:51.600885 [Byte1]: 57
7848 22:55:51.605116
7849 22:55:51.605201 Set Vref, RX VrefLevel [Byte0]: 58
7850 22:55:51.608603 [Byte1]: 58
7851 22:55:51.612696
7852 22:55:51.612793 Set Vref, RX VrefLevel [Byte0]: 59
7853 22:55:51.616376 [Byte1]: 59
7854 22:55:51.620353
7855 22:55:51.620439 Set Vref, RX VrefLevel [Byte0]: 60
7856 22:55:51.623883 [Byte1]: 60
7857 22:55:51.628050
7858 22:55:51.628135 Set Vref, RX VrefLevel [Byte0]: 61
7859 22:55:51.631035 [Byte1]: 61
7860 22:55:51.635407
7861 22:55:51.635492 Set Vref, RX VrefLevel [Byte0]: 62
7862 22:55:51.638618 [Byte1]: 62
7863 22:55:51.642841
7864 22:55:51.642926 Set Vref, RX VrefLevel [Byte0]: 63
7865 22:55:51.646114 [Byte1]: 63
7866 22:55:51.650988
7867 22:55:51.651101 Set Vref, RX VrefLevel [Byte0]: 64
7868 22:55:51.654064 [Byte1]: 64
7869 22:55:51.657926
7870 22:55:51.658001 Set Vref, RX VrefLevel [Byte0]: 65
7871 22:55:51.661279 [Byte1]: 65
7872 22:55:51.665648
7873 22:55:51.665725 Set Vref, RX VrefLevel [Byte0]: 66
7874 22:55:51.668955 [Byte1]: 66
7875 22:55:51.673121
7876 22:55:51.673202 Set Vref, RX VrefLevel [Byte0]: 67
7877 22:55:51.676437 [Byte1]: 67
7878 22:55:51.681112
7879 22:55:51.681185 Set Vref, RX VrefLevel [Byte0]: 68
7880 22:55:51.684336 [Byte1]: 68
7881 22:55:51.688431
7882 22:55:51.688502 Set Vref, RX VrefLevel [Byte0]: 69
7883 22:55:51.691581 [Byte1]: 69
7884 22:55:51.695967
7885 22:55:51.696051 Set Vref, RX VrefLevel [Byte0]: 70
7886 22:55:51.699243 [Byte1]: 70
7887 22:55:51.703789
7888 22:55:51.703872 Set Vref, RX VrefLevel [Byte0]: 71
7889 22:55:51.706797 [Byte1]: 71
7890 22:55:51.711121
7891 22:55:51.711204 Set Vref, RX VrefLevel [Byte0]: 72
7892 22:55:51.714581 [Byte1]: 72
7893 22:55:51.718669
7894 22:55:51.718752 Set Vref, RX VrefLevel [Byte0]: 73
7895 22:55:51.721951 [Byte1]: 73
7896 22:55:51.726186
7897 22:55:51.726270 Set Vref, RX VrefLevel [Byte0]: 74
7898 22:55:51.729564 [Byte1]: 74
7899 22:55:51.734032
7900 22:55:51.734115 Set Vref, RX VrefLevel [Byte0]: 75
7901 22:55:51.737010 [Byte1]: 75
7902 22:55:51.741425
7903 22:55:51.741507 Set Vref, RX VrefLevel [Byte0]: 76
7904 22:55:51.744693 [Byte1]: 76
7905 22:55:51.749171
7906 22:55:51.749255 Set Vref, RX VrefLevel [Byte0]: 77
7907 22:55:51.752463 [Byte1]: 77
7908 22:55:51.756991
7909 22:55:51.757077 Set Vref, RX VrefLevel [Byte0]: 78
7910 22:55:51.760140 [Byte1]: 78
7911 22:55:51.764186
7912 22:55:51.764269 Set Vref, RX VrefLevel [Byte0]: 79
7913 22:55:51.767371 [Byte1]: 79
7914 22:55:51.771944
7915 22:55:51.772028 Set Vref, RX VrefLevel [Byte0]: 80
7916 22:55:51.774965 [Byte1]: 80
7917 22:55:51.779234
7918 22:55:51.779314 Set Vref, RX VrefLevel [Byte0]: 81
7919 22:55:51.782761 [Byte1]: 81
7920 22:55:51.787163
7921 22:55:51.787235 Final RX Vref Byte 0 = 63 to rank0
7922 22:55:51.790152 Final RX Vref Byte 1 = 60 to rank0
7923 22:55:51.793389 Final RX Vref Byte 0 = 63 to rank1
7924 22:55:51.796685 Final RX Vref Byte 1 = 60 to rank1==
7925 22:55:51.800222 Dram Type= 6, Freq= 0, CH_0, rank 0
7926 22:55:51.806863 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7927 22:55:51.806952 ==
7928 22:55:51.807025 DQS Delay:
7929 22:55:51.807090 DQS0 = 0, DQS1 = 0
7930 22:55:51.810380 DQM Delay:
7931 22:55:51.810455 DQM0 = 136, DQM1 = 125
7932 22:55:51.813381 DQ Delay:
7933 22:55:51.816624 DQ0 =136, DQ1 =136, DQ2 =132, DQ3 =134
7934 22:55:51.819866 DQ4 =140, DQ5 =126, DQ6 =146, DQ7 =144
7935 22:55:51.823076 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =118
7936 22:55:51.826513 DQ12 =130, DQ13 =128, DQ14 =136, DQ15 =134
7937 22:55:51.826588
7938 22:55:51.826658
7939 22:55:51.826722
7940 22:55:51.829652 [DramC_TX_OE_Calibration] TA2
7941 22:55:51.833178 Original DQ_B0 (3 6) =30, OEN = 27
7942 22:55:51.836046 Original DQ_B1 (3 6) =30, OEN = 27
7943 22:55:51.839688 24, 0x0, End_B0=24 End_B1=24
7944 22:55:51.842845 25, 0x0, End_B0=25 End_B1=25
7945 22:55:51.842924 26, 0x0, End_B0=26 End_B1=26
7946 22:55:51.845954 27, 0x0, End_B0=27 End_B1=27
7947 22:55:51.849448 28, 0x0, End_B0=28 End_B1=28
7948 22:55:51.853089 29, 0x0, End_B0=29 End_B1=29
7949 22:55:51.853174 30, 0x0, End_B0=30 End_B1=30
7950 22:55:51.855913 31, 0x4141, End_B0=30 End_B1=30
7951 22:55:51.859256 Byte0 end_step=30 best_step=27
7952 22:55:51.862597 Byte1 end_step=30 best_step=27
7953 22:55:51.866009 Byte0 TX OE(2T, 0.5T) = (3, 3)
7954 22:55:51.869083 Byte1 TX OE(2T, 0.5T) = (3, 3)
7955 22:55:51.869164
7956 22:55:51.869229
7957 22:55:51.875588 [DQSOSCAuto] RK0, (LSB)MR18= 0x201e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
7958 22:55:51.878912 CH0 RK0: MR19=303, MR18=201E
7959 22:55:51.885978 CH0_RK0: MR19=0x303, MR18=0x201E, DQSOSC=393, MR23=63, INC=23, DEC=15
7960 22:55:51.886063
7961 22:55:51.888904 ----->DramcWriteLeveling(PI) begin...
7962 22:55:51.888981 ==
7963 22:55:51.892330 Dram Type= 6, Freq= 0, CH_0, rank 1
7964 22:55:51.895733 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7965 22:55:51.895808 ==
7966 22:55:51.898707 Write leveling (Byte 0): 37 => 37
7967 22:55:51.901974 Write leveling (Byte 1): 27 => 27
7968 22:55:51.905194 DramcWriteLeveling(PI) end<-----
7969 22:55:51.905277
7970 22:55:51.905340 ==
7971 22:55:51.908619 Dram Type= 6, Freq= 0, CH_0, rank 1
7972 22:55:51.915407 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7973 22:55:51.915491 ==
7974 22:55:51.915559 [Gating] SW mode calibration
7975 22:55:51.925388 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7976 22:55:51.928700 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7977 22:55:51.932498 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7978 22:55:51.938664 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7979 22:55:51.941927 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7980 22:55:51.945004 1 4 12 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)
7981 22:55:51.952048 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7982 22:55:51.955001 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7983 22:55:51.958182 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7984 22:55:51.965132 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7985 22:55:51.968213 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7986 22:55:51.971440 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7987 22:55:51.978161 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7988 22:55:51.981923 1 5 12 | B1->B0 | 3333 2525 | 1 1 | (1 1) (1 0)
7989 22:55:51.985046 1 5 16 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
7990 22:55:51.991670 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7991 22:55:51.994624 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7992 22:55:51.998175 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7993 22:55:52.004366 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7994 22:55:52.007465 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7995 22:55:52.011106 1 6 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
7996 22:55:52.017578 1 6 12 | B1->B0 | 3030 4242 | 0 1 | (1 1) (0 0)
7997 22:55:52.020785 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7998 22:55:52.024063 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7999 22:55:52.030810 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8000 22:55:52.034671 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8001 22:55:52.037685 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8002 22:55:52.044217 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8003 22:55:52.047212 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8004 22:55:52.050606 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8005 22:55:52.057058 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8006 22:55:52.060644 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 22:55:52.063893 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 22:55:52.070248 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 22:55:52.073841 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 22:55:52.077049 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 22:55:52.083696 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 22:55:52.086957 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 22:55:52.090604 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 22:55:52.097086 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 22:55:52.100533 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 22:55:52.103563 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 22:55:52.110362 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 22:55:52.113739 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 22:55:52.116698 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8020 22:55:52.123405 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8021 22:55:52.126801 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8022 22:55:52.130042 Total UI for P1: 0, mck2ui 16
8023 22:55:52.133293 best dqsien dly found for B0: ( 1, 9, 10)
8024 22:55:52.136647 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8025 22:55:52.140209 Total UI for P1: 0, mck2ui 16
8026 22:55:52.143321 best dqsien dly found for B1: ( 1, 9, 16)
8027 22:55:52.146929 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8028 22:55:52.149629 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8029 22:55:52.149711
8030 22:55:52.156859 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8031 22:55:52.159684 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8032 22:55:52.162822 [Gating] SW calibration Done
8033 22:55:52.162905 ==
8034 22:55:52.166846 Dram Type= 6, Freq= 0, CH_0, rank 1
8035 22:55:52.169709 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8036 22:55:52.169791 ==
8037 22:55:52.169875 RX Vref Scan: 0
8038 22:55:52.172750
8039 22:55:52.172889 RX Vref 0 -> 0, step: 1
8040 22:55:52.172975
8041 22:55:52.175970 RX Delay 0 -> 252, step: 8
8042 22:55:52.179360 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8043 22:55:52.182867 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8044 22:55:52.189607 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8045 22:55:52.192664 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8046 22:55:52.195855 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8047 22:55:52.199162 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8048 22:55:52.202717 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8049 22:55:52.209362 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8050 22:55:52.212662 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8051 22:55:52.215988 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8052 22:55:52.219100 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8053 22:55:52.222384 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8054 22:55:52.229107 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8055 22:55:52.232563 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8056 22:55:52.235586 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8057 22:55:52.239196 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8058 22:55:52.239282 ==
8059 22:55:52.242715 Dram Type= 6, Freq= 0, CH_0, rank 1
8060 22:55:52.249295 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8061 22:55:52.249379 ==
8062 22:55:52.249446 DQS Delay:
8063 22:55:52.252647 DQS0 = 0, DQS1 = 0
8064 22:55:52.252756 DQM Delay:
8065 22:55:52.252859 DQM0 = 136, DQM1 = 125
8066 22:55:52.255634 DQ Delay:
8067 22:55:52.258824 DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131
8068 22:55:52.262526 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8069 22:55:52.265504 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8070 22:55:52.268848 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8071 22:55:52.268932
8072 22:55:52.268997
8073 22:55:52.269058 ==
8074 22:55:52.271988 Dram Type= 6, Freq= 0, CH_0, rank 1
8075 22:55:52.278858 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8076 22:55:52.278943 ==
8077 22:55:52.279009
8078 22:55:52.279070
8079 22:55:52.279129 TX Vref Scan disable
8080 22:55:52.281907 == TX Byte 0 ==
8081 22:55:52.285515 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8082 22:55:52.291868 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8083 22:55:52.291951 == TX Byte 1 ==
8084 22:55:52.295427 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8085 22:55:52.301953 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8086 22:55:52.302038 ==
8087 22:55:52.305635 Dram Type= 6, Freq= 0, CH_0, rank 1
8088 22:55:52.308235 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8089 22:55:52.308320 ==
8090 22:55:52.322016
8091 22:55:52.325617 TX Vref early break, caculate TX vref
8092 22:55:52.328619 TX Vref=16, minBit 0, minWin=23, winSum=387
8093 22:55:52.331961 TX Vref=18, minBit 0, minWin=24, winSum=399
8094 22:55:52.335645 TX Vref=20, minBit 0, minWin=23, winSum=404
8095 22:55:52.339159 TX Vref=22, minBit 0, minWin=25, winSum=415
8096 22:55:52.341805 TX Vref=24, minBit 0, minWin=25, winSum=421
8097 22:55:52.348731 TX Vref=26, minBit 2, minWin=25, winSum=429
8098 22:55:52.351963 TX Vref=28, minBit 0, minWin=26, winSum=425
8099 22:55:52.355222 TX Vref=30, minBit 2, minWin=25, winSum=420
8100 22:55:52.358426 TX Vref=32, minBit 0, minWin=25, winSum=410
8101 22:55:52.361883 TX Vref=34, minBit 2, minWin=24, winSum=401
8102 22:55:52.368396 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 28
8103 22:55:52.368480
8104 22:55:52.372239 Final TX Range 0 Vref 28
8105 22:55:52.372322
8106 22:55:52.372388 ==
8107 22:55:52.375179 Dram Type= 6, Freq= 0, CH_0, rank 1
8108 22:55:52.378534 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8109 22:55:52.378618 ==
8110 22:55:52.378684
8111 22:55:52.378745
8112 22:55:52.382147 TX Vref Scan disable
8113 22:55:52.388209 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8114 22:55:52.388327 == TX Byte 0 ==
8115 22:55:52.391457 u2DelayCellOfst[0]=10 cells (3 PI)
8116 22:55:52.394943 u2DelayCellOfst[1]=16 cells (5 PI)
8117 22:55:52.398073 u2DelayCellOfst[2]=10 cells (3 PI)
8118 22:55:52.401356 u2DelayCellOfst[3]=10 cells (3 PI)
8119 22:55:52.404472 u2DelayCellOfst[4]=6 cells (2 PI)
8120 22:55:52.407762 u2DelayCellOfst[5]=0 cells (0 PI)
8121 22:55:52.411029 u2DelayCellOfst[6]=16 cells (5 PI)
8122 22:55:52.414508 u2DelayCellOfst[7]=13 cells (4 PI)
8123 22:55:52.417814 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8124 22:55:52.421251 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8125 22:55:52.424548 == TX Byte 1 ==
8126 22:55:52.427773 u2DelayCellOfst[8]=0 cells (0 PI)
8127 22:55:52.430954 u2DelayCellOfst[9]=0 cells (0 PI)
8128 22:55:52.431030 u2DelayCellOfst[10]=6 cells (2 PI)
8129 22:55:52.434609 u2DelayCellOfst[11]=3 cells (1 PI)
8130 22:55:52.437526 u2DelayCellOfst[12]=13 cells (4 PI)
8131 22:55:52.441229 u2DelayCellOfst[13]=10 cells (3 PI)
8132 22:55:52.444392 u2DelayCellOfst[14]=13 cells (4 PI)
8133 22:55:52.447430 u2DelayCellOfst[15]=10 cells (3 PI)
8134 22:55:52.454386 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8135 22:55:52.457665 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8136 22:55:52.457743 DramC Write-DBI on
8137 22:55:52.457808 ==
8138 22:55:52.460687 Dram Type= 6, Freq= 0, CH_0, rank 1
8139 22:55:52.467364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8140 22:55:52.467514 ==
8141 22:55:52.467611
8142 22:55:52.467704
8143 22:55:52.467794 TX Vref Scan disable
8144 22:55:52.471688 == TX Byte 0 ==
8145 22:55:52.475138 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8146 22:55:52.478045 == TX Byte 1 ==
8147 22:55:52.481470 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8148 22:55:52.484796 DramC Write-DBI off
8149 22:55:52.484898
8150 22:55:52.484964 [DATLAT]
8151 22:55:52.485044 Freq=1600, CH0 RK1
8152 22:55:52.485154
8153 22:55:52.488266 DATLAT Default: 0xf
8154 22:55:52.491610 0, 0xFFFF, sum = 0
8155 22:55:52.491731 1, 0xFFFF, sum = 0
8156 22:55:52.494563 2, 0xFFFF, sum = 0
8157 22:55:52.494670 3, 0xFFFF, sum = 0
8158 22:55:52.498080 4, 0xFFFF, sum = 0
8159 22:55:52.498193 5, 0xFFFF, sum = 0
8160 22:55:52.501486 6, 0xFFFF, sum = 0
8161 22:55:52.501594 7, 0xFFFF, sum = 0
8162 22:55:52.504676 8, 0xFFFF, sum = 0
8163 22:55:52.504822 9, 0xFFFF, sum = 0
8164 22:55:52.508148 10, 0xFFFF, sum = 0
8165 22:55:52.508282 11, 0xFFFF, sum = 0
8166 22:55:52.510998 12, 0xFFFF, sum = 0
8167 22:55:52.511119 13, 0xFFFF, sum = 0
8168 22:55:52.514572 14, 0x0, sum = 1
8169 22:55:52.514704 15, 0x0, sum = 2
8170 22:55:52.517782 16, 0x0, sum = 3
8171 22:55:52.517886 17, 0x0, sum = 4
8172 22:55:52.521357 best_step = 15
8173 22:55:52.521468
8174 22:55:52.521578 ==
8175 22:55:52.524472 Dram Type= 6, Freq= 0, CH_0, rank 1
8176 22:55:52.527706 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8177 22:55:52.527825 ==
8178 22:55:52.531178 RX Vref Scan: 0
8179 22:55:52.531305
8180 22:55:52.531401 RX Vref 0 -> 0, step: 1
8181 22:55:52.531504
8182 22:55:52.534551 RX Delay 11 -> 252, step: 4
8183 22:55:52.541162 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8184 22:55:52.544279 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8185 22:55:52.547502 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8186 22:55:52.550919 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8187 22:55:52.554192 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8188 22:55:52.561113 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8189 22:55:52.564160 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8190 22:55:52.567133 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8191 22:55:52.570536 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8192 22:55:52.574325 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8193 22:55:52.580763 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8194 22:55:52.583707 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8195 22:55:52.587339 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8196 22:55:52.590608 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8197 22:55:52.593879 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8198 22:55:52.600758 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8199 22:55:52.600887 ==
8200 22:55:52.603796 Dram Type= 6, Freq= 0, CH_0, rank 1
8201 22:55:52.606913 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8202 22:55:52.607027 ==
8203 22:55:52.607120 DQS Delay:
8204 22:55:52.610512 DQS0 = 0, DQS1 = 0
8205 22:55:52.610599 DQM Delay:
8206 22:55:52.613448 DQM0 = 133, DQM1 = 123
8207 22:55:52.613527 DQ Delay:
8208 22:55:52.617261 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =130
8209 22:55:52.620262 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8210 22:55:52.623400 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =118
8211 22:55:52.630198 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8212 22:55:52.630274
8213 22:55:52.630337
8214 22:55:52.630404
8215 22:55:52.630465 [DramC_TX_OE_Calibration] TA2
8216 22:55:52.633420 Original DQ_B0 (3 6) =30, OEN = 27
8217 22:55:52.636622 Original DQ_B1 (3 6) =30, OEN = 27
8218 22:55:52.639824 24, 0x0, End_B0=24 End_B1=24
8219 22:55:52.643220 25, 0x0, End_B0=25 End_B1=25
8220 22:55:52.646465 26, 0x0, End_B0=26 End_B1=26
8221 22:55:52.649730 27, 0x0, End_B0=27 End_B1=27
8222 22:55:52.649800 28, 0x0, End_B0=28 End_B1=28
8223 22:55:52.653114 29, 0x0, End_B0=29 End_B1=29
8224 22:55:52.656292 30, 0x0, End_B0=30 End_B1=30
8225 22:55:52.659911 31, 0x4141, End_B0=30 End_B1=30
8226 22:55:52.663097 Byte0 end_step=30 best_step=27
8227 22:55:52.663172 Byte1 end_step=30 best_step=27
8228 22:55:52.666602 Byte0 TX OE(2T, 0.5T) = (3, 3)
8229 22:55:52.669600 Byte1 TX OE(2T, 0.5T) = (3, 3)
8230 22:55:52.669692
8231 22:55:52.669773
8232 22:55:52.679513 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e0c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 394 ps
8233 22:55:52.679611 CH0 RK1: MR19=303, MR18=1E0C
8234 22:55:52.686220 CH0_RK1: MR19=0x303, MR18=0x1E0C, DQSOSC=394, MR23=63, INC=23, DEC=15
8235 22:55:52.689300 [RxdqsGatingPostProcess] freq 1600
8236 22:55:52.695887 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8237 22:55:52.699384 best DQS0 dly(2T, 0.5T) = (1, 1)
8238 22:55:52.702612 best DQS1 dly(2T, 0.5T) = (1, 1)
8239 22:55:52.705942 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8240 22:55:52.709173 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8241 22:55:52.713270 best DQS0 dly(2T, 0.5T) = (1, 1)
8242 22:55:52.713355 best DQS1 dly(2T, 0.5T) = (1, 1)
8243 22:55:52.716333 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8244 22:55:52.719157 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8245 22:55:52.722699 Pre-setting of DQS Precalculation
8246 22:55:52.729397 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8247 22:55:52.729484 ==
8248 22:55:52.732483 Dram Type= 6, Freq= 0, CH_1, rank 0
8249 22:55:52.736042 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8250 22:55:52.736128 ==
8251 22:55:52.742375 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8252 22:55:52.745815 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8253 22:55:52.749160 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8254 22:55:52.755941 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8255 22:55:52.764859 [CA 0] Center 40 (11~70) winsize 60
8256 22:55:52.767986 [CA 1] Center 41 (11~71) winsize 61
8257 22:55:52.771164 [CA 2] Center 37 (8~67) winsize 60
8258 22:55:52.774523 [CA 3] Center 36 (7~66) winsize 60
8259 22:55:52.777863 [CA 4] Center 36 (7~66) winsize 60
8260 22:55:52.781373 [CA 5] Center 36 (6~66) winsize 61
8261 22:55:52.781456
8262 22:55:52.784525 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8263 22:55:52.784608
8264 22:55:52.787679 [CATrainingPosCal] consider 1 rank data
8265 22:55:52.790893 u2DelayCellTimex100 = 290/100 ps
8266 22:55:52.797531 CA0 delay=40 (11~70),Diff = 4 PI (13 cell)
8267 22:55:52.800914 CA1 delay=41 (11~71),Diff = 5 PI (16 cell)
8268 22:55:52.804425 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8269 22:55:52.807720 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8270 22:55:52.810792 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8271 22:55:52.814634 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8272 22:55:52.814718
8273 22:55:52.817397 CA PerBit enable=1, Macro0, CA PI delay=36
8274 22:55:52.817480
8275 22:55:52.820632 [CBTSetCACLKResult] CA Dly = 36
8276 22:55:52.824050 CS Dly: 8 (0~39)
8277 22:55:52.827508 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8278 22:55:52.830979 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8279 22:55:52.831063 ==
8280 22:55:52.833992 Dram Type= 6, Freq= 0, CH_1, rank 1
8281 22:55:52.837658 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8282 22:55:52.840820 ==
8283 22:55:52.844183 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8284 22:55:52.847343 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8285 22:55:52.854084 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8286 22:55:52.860691 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8287 22:55:52.867809 [CA 0] Center 42 (13~72) winsize 60
8288 22:55:52.871005 [CA 1] Center 42 (12~72) winsize 61
8289 22:55:52.874305 [CA 2] Center 38 (9~68) winsize 60
8290 22:55:52.877651 [CA 3] Center 37 (8~67) winsize 60
8291 22:55:52.880925 [CA 4] Center 37 (8~67) winsize 60
8292 22:55:52.884091 [CA 5] Center 37 (8~67) winsize 60
8293 22:55:52.884173
8294 22:55:52.887509 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8295 22:55:52.887592
8296 22:55:52.894063 [CATrainingPosCal] consider 2 rank data
8297 22:55:52.894145 u2DelayCellTimex100 = 290/100 ps
8298 22:55:52.900700 CA0 delay=41 (13~70),Diff = 4 PI (13 cell)
8299 22:55:52.903830 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8300 22:55:52.907656 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8301 22:55:52.910686 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8302 22:55:52.914053 CA4 delay=37 (8~66),Diff = 0 PI (0 cell)
8303 22:55:52.917416 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8304 22:55:52.917527
8305 22:55:52.921077 CA PerBit enable=1, Macro0, CA PI delay=37
8306 22:55:52.921158
8307 22:55:52.924130 [CBTSetCACLKResult] CA Dly = 37
8308 22:55:52.927375 CS Dly: 9 (0~42)
8309 22:55:52.930378 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8310 22:55:52.933965 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8311 22:55:52.934047
8312 22:55:52.937282 ----->DramcWriteLeveling(PI) begin...
8313 22:55:52.937365 ==
8314 22:55:52.940401 Dram Type= 6, Freq= 0, CH_1, rank 0
8315 22:55:52.947289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8316 22:55:52.947371 ==
8317 22:55:52.950239 Write leveling (Byte 0): 24 => 24
8318 22:55:52.953259 Write leveling (Byte 1): 28 => 28
8319 22:55:52.953341 DramcWriteLeveling(PI) end<-----
8320 22:55:52.957119
8321 22:55:52.957200 ==
8322 22:55:52.960078 Dram Type= 6, Freq= 0, CH_1, rank 0
8323 22:55:52.963537 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8324 22:55:52.963619 ==
8325 22:55:52.966576 [Gating] SW mode calibration
8326 22:55:52.973462 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8327 22:55:52.976886 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8328 22:55:52.983272 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8329 22:55:52.986806 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8330 22:55:52.989965 1 4 8 | B1->B0 | 2828 2e2e | 0 1 | (0 0) (1 1)
8331 22:55:52.996550 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8332 22:55:52.999812 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8333 22:55:53.003080 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8334 22:55:53.009992 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8335 22:55:53.013063 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8336 22:55:53.016479 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8337 22:55:53.023122 1 5 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8338 22:55:53.026624 1 5 8 | B1->B0 | 2929 2626 | 1 0 | (1 0) (1 0)
8339 22:55:53.029546 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
8340 22:55:53.036095 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8341 22:55:53.039478 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8342 22:55:53.042958 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8343 22:55:53.049407 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8344 22:55:53.052545 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8345 22:55:53.055924 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8346 22:55:53.062553 1 6 8 | B1->B0 | 4242 4545 | 0 0 | (0 0) (0 0)
8347 22:55:53.065801 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8348 22:55:53.069053 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8349 22:55:53.076035 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8350 22:55:53.079198 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8351 22:55:53.082254 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8352 22:55:53.088675 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8353 22:55:53.092045 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8354 22:55:53.095513 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8355 22:55:53.102521 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8356 22:55:53.105572 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 22:55:53.108917 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 22:55:53.115294 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 22:55:53.118356 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 22:55:53.121994 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 22:55:53.128576 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 22:55:53.132139 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 22:55:53.135334 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 22:55:53.142091 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 22:55:53.145232 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 22:55:53.148326 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 22:55:53.155109 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 22:55:53.157989 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 22:55:53.161426 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 22:55:53.168333 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8371 22:55:53.171247 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8372 22:55:53.174656 Total UI for P1: 0, mck2ui 16
8373 22:55:53.178218 best dqsien dly found for B0: ( 1, 9, 8)
8374 22:55:53.181199 Total UI for P1: 0, mck2ui 16
8375 22:55:53.184397 best dqsien dly found for B1: ( 1, 9, 8)
8376 22:55:53.187747 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8377 22:55:53.191393 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8378 22:55:53.191477
8379 22:55:53.194416 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8380 22:55:53.197917 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8381 22:55:53.200995 [Gating] SW calibration Done
8382 22:55:53.201078 ==
8383 22:55:53.204602 Dram Type= 6, Freq= 0, CH_1, rank 0
8384 22:55:53.207557 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8385 22:55:53.211061 ==
8386 22:55:53.211144 RX Vref Scan: 0
8387 22:55:53.211211
8388 22:55:53.214143 RX Vref 0 -> 0, step: 1
8389 22:55:53.214227
8390 22:55:53.217237 RX Delay 0 -> 252, step: 8
8391 22:55:53.220953 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8392 22:55:53.224116 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8393 22:55:53.227608 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8394 22:55:53.230974 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8395 22:55:53.237572 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8396 22:55:53.240661 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8397 22:55:53.244211 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8398 22:55:53.247492 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8399 22:55:53.250631 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8400 22:55:53.254180 iDelay=200, Bit 9, Center 123 (80 ~ 167) 88
8401 22:55:53.260611 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8402 22:55:53.263910 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8403 22:55:53.267103 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8404 22:55:53.270744 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8405 22:55:53.277084 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8406 22:55:53.280622 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8407 22:55:53.280707 ==
8408 22:55:53.283727 Dram Type= 6, Freq= 0, CH_1, rank 0
8409 22:55:53.287339 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8410 22:55:53.287425 ==
8411 22:55:53.287509 DQS Delay:
8412 22:55:53.290271 DQS0 = 0, DQS1 = 0
8413 22:55:53.290357 DQM Delay:
8414 22:55:53.293641 DQM0 = 138, DQM1 = 131
8415 22:55:53.293726 DQ Delay:
8416 22:55:53.297429 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =139
8417 22:55:53.300400 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8418 22:55:53.303832 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
8419 22:55:53.310091 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =135
8420 22:55:53.310175
8421 22:55:53.310241
8422 22:55:53.310301 ==
8423 22:55:53.313333 Dram Type= 6, Freq= 0, CH_1, rank 0
8424 22:55:53.316663 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8425 22:55:53.316761 ==
8426 22:55:53.316850
8427 22:55:53.316912
8428 22:55:53.319986 TX Vref Scan disable
8429 22:55:53.320070 == TX Byte 0 ==
8430 22:55:53.326619 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8431 22:55:53.329778 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8432 22:55:53.329861 == TX Byte 1 ==
8433 22:55:53.336459 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8434 22:55:53.339717 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8435 22:55:53.339795 ==
8436 22:55:53.343199 Dram Type= 6, Freq= 0, CH_1, rank 0
8437 22:55:53.346206 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8438 22:55:53.346276 ==
8439 22:55:53.359567
8440 22:55:53.362717 TX Vref early break, caculate TX vref
8441 22:55:53.366118 TX Vref=16, minBit 8, minWin=22, winSum=370
8442 22:55:53.369315 TX Vref=18, minBit 10, minWin=21, winSum=377
8443 22:55:53.372495 TX Vref=20, minBit 10, minWin=22, winSum=384
8444 22:55:53.375906 TX Vref=22, minBit 15, minWin=23, winSum=398
8445 22:55:53.382725 TX Vref=24, minBit 10, minWin=23, winSum=409
8446 22:55:53.385611 TX Vref=26, minBit 9, minWin=25, winSum=419
8447 22:55:53.389149 TX Vref=28, minBit 8, minWin=25, winSum=416
8448 22:55:53.392552 TX Vref=30, minBit 13, minWin=23, winSum=407
8449 22:55:53.395807 TX Vref=32, minBit 12, minWin=23, winSum=397
8450 22:55:53.402093 [TxChooseVref] Worse bit 9, Min win 25, Win sum 419, Final Vref 26
8451 22:55:53.402165
8452 22:55:53.405266 Final TX Range 0 Vref 26
8453 22:55:53.405335
8454 22:55:53.405401 ==
8455 22:55:53.408894 Dram Type= 6, Freq= 0, CH_1, rank 0
8456 22:55:53.412165 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8457 22:55:53.412237 ==
8458 22:55:53.412298
8459 22:55:53.412355
8460 22:55:53.415290 TX Vref Scan disable
8461 22:55:53.421966 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8462 22:55:53.422047 == TX Byte 0 ==
8463 22:55:53.425289 u2DelayCellOfst[0]=13 cells (4 PI)
8464 22:55:53.428763 u2DelayCellOfst[1]=6 cells (2 PI)
8465 22:55:53.432049 u2DelayCellOfst[2]=0 cells (0 PI)
8466 22:55:53.435350 u2DelayCellOfst[3]=6 cells (2 PI)
8467 22:55:53.438465 u2DelayCellOfst[4]=6 cells (2 PI)
8468 22:55:53.441857 u2DelayCellOfst[5]=16 cells (5 PI)
8469 22:55:53.445192 u2DelayCellOfst[6]=16 cells (5 PI)
8470 22:55:53.448542 u2DelayCellOfst[7]=6 cells (2 PI)
8471 22:55:53.451805 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8472 22:55:53.454904 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8473 22:55:53.458276 == TX Byte 1 ==
8474 22:55:53.458350 u2DelayCellOfst[8]=0 cells (0 PI)
8475 22:55:53.461451 u2DelayCellOfst[9]=3 cells (1 PI)
8476 22:55:53.465268 u2DelayCellOfst[10]=10 cells (3 PI)
8477 22:55:53.468233 u2DelayCellOfst[11]=3 cells (1 PI)
8478 22:55:53.471877 u2DelayCellOfst[12]=16 cells (5 PI)
8479 22:55:53.475519 u2DelayCellOfst[13]=16 cells (5 PI)
8480 22:55:53.478563 u2DelayCellOfst[14]=16 cells (5 PI)
8481 22:55:53.481680 u2DelayCellOfst[15]=16 cells (5 PI)
8482 22:55:53.485231 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8483 22:55:53.491603 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8484 22:55:53.491677 DramC Write-DBI on
8485 22:55:53.491740 ==
8486 22:55:53.495058 Dram Type= 6, Freq= 0, CH_1, rank 0
8487 22:55:53.501442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8488 22:55:53.501514 ==
8489 22:55:53.501583
8490 22:55:53.501646
8491 22:55:53.501703 TX Vref Scan disable
8492 22:55:53.504840 == TX Byte 0 ==
8493 22:55:53.508578 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8494 22:55:53.511562 == TX Byte 1 ==
8495 22:55:53.515238 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8496 22:55:53.518379 DramC Write-DBI off
8497 22:55:53.518451
8498 22:55:53.518513 [DATLAT]
8499 22:55:53.518571 Freq=1600, CH1 RK0
8500 22:55:53.518635
8501 22:55:53.521350 DATLAT Default: 0xf
8502 22:55:53.524808 0, 0xFFFF, sum = 0
8503 22:55:53.524883 1, 0xFFFF, sum = 0
8504 22:55:53.528151 2, 0xFFFF, sum = 0
8505 22:55:53.528223 3, 0xFFFF, sum = 0
8506 22:55:53.531266 4, 0xFFFF, sum = 0
8507 22:55:53.531335 5, 0xFFFF, sum = 0
8508 22:55:53.534715 6, 0xFFFF, sum = 0
8509 22:55:53.534788 7, 0xFFFF, sum = 0
8510 22:55:53.537993 8, 0xFFFF, sum = 0
8511 22:55:53.538067 9, 0xFFFF, sum = 0
8512 22:55:53.541597 10, 0xFFFF, sum = 0
8513 22:55:53.541673 11, 0xFFFF, sum = 0
8514 22:55:53.544663 12, 0xFFFF, sum = 0
8515 22:55:53.544735 13, 0xFFFF, sum = 0
8516 22:55:53.548130 14, 0x0, sum = 1
8517 22:55:53.548204 15, 0x0, sum = 2
8518 22:55:53.551642 16, 0x0, sum = 3
8519 22:55:53.551718 17, 0x0, sum = 4
8520 22:55:53.554605 best_step = 15
8521 22:55:53.554679
8522 22:55:53.554739 ==
8523 22:55:53.558019 Dram Type= 6, Freq= 0, CH_1, rank 0
8524 22:55:53.561379 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8525 22:55:53.561454 ==
8526 22:55:53.564467 RX Vref Scan: 1
8527 22:55:53.564544
8528 22:55:53.564607 Set Vref Range= 24 -> 127
8529 22:55:53.564667
8530 22:55:53.567785 RX Vref 24 -> 127, step: 1
8531 22:55:53.567862
8532 22:55:53.571264 RX Delay 19 -> 252, step: 4
8533 22:55:53.571340
8534 22:55:53.574339 Set Vref, RX VrefLevel [Byte0]: 24
8535 22:55:53.577838 [Byte1]: 24
8536 22:55:53.577914
8537 22:55:53.581152 Set Vref, RX VrefLevel [Byte0]: 25
8538 22:55:53.584389 [Byte1]: 25
8539 22:55:53.587622
8540 22:55:53.587696 Set Vref, RX VrefLevel [Byte0]: 26
8541 22:55:53.591271 [Byte1]: 26
8542 22:55:53.595176
8543 22:55:53.595251 Set Vref, RX VrefLevel [Byte0]: 27
8544 22:55:53.598507 [Byte1]: 27
8545 22:55:53.603065
8546 22:55:53.603141 Set Vref, RX VrefLevel [Byte0]: 28
8547 22:55:53.606160 [Byte1]: 28
8548 22:55:53.610603
8549 22:55:53.610676 Set Vref, RX VrefLevel [Byte0]: 29
8550 22:55:53.613607 [Byte1]: 29
8551 22:55:53.618184
8552 22:55:53.618261 Set Vref, RX VrefLevel [Byte0]: 30
8553 22:55:53.621274 [Byte1]: 30
8554 22:55:53.625463
8555 22:55:53.625540 Set Vref, RX VrefLevel [Byte0]: 31
8556 22:55:53.632236 [Byte1]: 31
8557 22:55:53.632312
8558 22:55:53.635575 Set Vref, RX VrefLevel [Byte0]: 32
8559 22:55:53.638516 [Byte1]: 32
8560 22:55:53.638596
8561 22:55:53.642178 Set Vref, RX VrefLevel [Byte0]: 33
8562 22:55:53.645291 [Byte1]: 33
8563 22:55:53.645373
8564 22:55:53.648972 Set Vref, RX VrefLevel [Byte0]: 34
8565 22:55:53.652210 [Byte1]: 34
8566 22:55:53.655857
8567 22:55:53.655934 Set Vref, RX VrefLevel [Byte0]: 35
8568 22:55:53.659230 [Byte1]: 35
8569 22:55:53.663568
8570 22:55:53.663635 Set Vref, RX VrefLevel [Byte0]: 36
8571 22:55:53.667113 [Byte1]: 36
8572 22:55:53.671065
8573 22:55:53.671141 Set Vref, RX VrefLevel [Byte0]: 37
8574 22:55:53.674673 [Byte1]: 37
8575 22:55:53.678685
8576 22:55:53.678759 Set Vref, RX VrefLevel [Byte0]: 38
8577 22:55:53.682091 [Byte1]: 38
8578 22:55:53.686058
8579 22:55:53.686147 Set Vref, RX VrefLevel [Byte0]: 39
8580 22:55:53.689402 [Byte1]: 39
8581 22:55:53.693681
8582 22:55:53.693770 Set Vref, RX VrefLevel [Byte0]: 40
8583 22:55:53.696928 [Byte1]: 40
8584 22:55:53.701293
8585 22:55:53.701375 Set Vref, RX VrefLevel [Byte0]: 41
8586 22:55:53.704596 [Byte1]: 41
8587 22:55:53.709084
8588 22:55:53.709166 Set Vref, RX VrefLevel [Byte0]: 42
8589 22:55:53.712254 [Byte1]: 42
8590 22:55:53.716302
8591 22:55:53.716384 Set Vref, RX VrefLevel [Byte0]: 43
8592 22:55:53.719609 [Byte1]: 43
8593 22:55:53.723853
8594 22:55:53.723934 Set Vref, RX VrefLevel [Byte0]: 44
8595 22:55:53.727424 [Byte1]: 44
8596 22:55:53.731572
8597 22:55:53.731653 Set Vref, RX VrefLevel [Byte0]: 45
8598 22:55:53.734775 [Byte1]: 45
8599 22:55:53.739656
8600 22:55:53.739738 Set Vref, RX VrefLevel [Byte0]: 46
8601 22:55:53.742794 [Byte1]: 46
8602 22:55:53.746602
8603 22:55:53.746684 Set Vref, RX VrefLevel [Byte0]: 47
8604 22:55:53.750158 [Byte1]: 47
8605 22:55:53.754323
8606 22:55:53.754409 Set Vref, RX VrefLevel [Byte0]: 48
8607 22:55:53.757926 [Byte1]: 48
8608 22:55:53.761774
8609 22:55:53.761856 Set Vref, RX VrefLevel [Byte0]: 49
8610 22:55:53.765185 [Byte1]: 49
8611 22:55:53.769266
8612 22:55:53.769347 Set Vref, RX VrefLevel [Byte0]: 50
8613 22:55:53.772607 [Byte1]: 50
8614 22:55:53.777111
8615 22:55:53.777192 Set Vref, RX VrefLevel [Byte0]: 51
8616 22:55:53.780713 [Byte1]: 51
8617 22:55:53.784495
8618 22:55:53.784577 Set Vref, RX VrefLevel [Byte0]: 52
8619 22:55:53.788149 [Byte1]: 52
8620 22:55:53.792100
8621 22:55:53.792184 Set Vref, RX VrefLevel [Byte0]: 53
8622 22:55:53.795687 [Byte1]: 53
8623 22:55:53.799776
8624 22:55:53.799857 Set Vref, RX VrefLevel [Byte0]: 54
8625 22:55:53.803099 [Byte1]: 54
8626 22:55:53.807417
8627 22:55:53.807498 Set Vref, RX VrefLevel [Byte0]: 55
8628 22:55:53.810580 [Byte1]: 55
8629 22:55:53.815140
8630 22:55:53.815221 Set Vref, RX VrefLevel [Byte0]: 56
8631 22:55:53.818350 [Byte1]: 56
8632 22:55:53.822525
8633 22:55:53.822607 Set Vref, RX VrefLevel [Byte0]: 57
8634 22:55:53.825867 [Byte1]: 57
8635 22:55:53.830281
8636 22:55:53.830362 Set Vref, RX VrefLevel [Byte0]: 58
8637 22:55:53.833761 [Byte1]: 58
8638 22:55:53.837729
8639 22:55:53.837811 Set Vref, RX VrefLevel [Byte0]: 59
8640 22:55:53.841087 [Byte1]: 59
8641 22:55:53.845468
8642 22:55:53.845550 Set Vref, RX VrefLevel [Byte0]: 60
8643 22:55:53.848281 [Byte1]: 60
8644 22:55:53.852949
8645 22:55:53.853031 Set Vref, RX VrefLevel [Byte0]: 61
8646 22:55:53.856208 [Byte1]: 61
8647 22:55:53.860028
8648 22:55:53.863572 Set Vref, RX VrefLevel [Byte0]: 62
8649 22:55:53.863655 [Byte1]: 62
8650 22:55:53.868039
8651 22:55:53.868121 Set Vref, RX VrefLevel [Byte0]: 63
8652 22:55:53.871493 [Byte1]: 63
8653 22:55:53.875572
8654 22:55:53.875654 Set Vref, RX VrefLevel [Byte0]: 64
8655 22:55:53.879370 [Byte1]: 64
8656 22:55:53.882948
8657 22:55:53.883030 Set Vref, RX VrefLevel [Byte0]: 65
8658 22:55:53.886188 [Byte1]: 65
8659 22:55:53.891413
8660 22:55:53.891495 Set Vref, RX VrefLevel [Byte0]: 66
8661 22:55:53.897147 [Byte1]: 66
8662 22:55:53.897229
8663 22:55:53.900318 Set Vref, RX VrefLevel [Byte0]: 67
8664 22:55:53.903679 [Byte1]: 67
8665 22:55:53.903762
8666 22:55:53.906811 Set Vref, RX VrefLevel [Byte0]: 68
8667 22:55:53.910426 [Byte1]: 68
8668 22:55:53.910508
8669 22:55:53.913788 Set Vref, RX VrefLevel [Byte0]: 69
8670 22:55:53.917058 [Byte1]: 69
8671 22:55:53.920799
8672 22:55:53.920893 Set Vref, RX VrefLevel [Byte0]: 70
8673 22:55:53.924364 [Byte1]: 70
8674 22:55:53.928758
8675 22:55:53.928845 Set Vref, RX VrefLevel [Byte0]: 71
8676 22:55:53.931679 [Byte1]: 71
8677 22:55:53.936168
8678 22:55:53.936249 Set Vref, RX VrefLevel [Byte0]: 72
8679 22:55:53.939190 [Byte1]: 72
8680 22:55:53.943502
8681 22:55:53.943584 Set Vref, RX VrefLevel [Byte0]: 73
8682 22:55:53.947015 [Byte1]: 73
8683 22:55:53.951185
8684 22:55:53.951266 Set Vref, RX VrefLevel [Byte0]: 74
8685 22:55:53.954666 [Byte1]: 74
8686 22:55:53.958885
8687 22:55:53.958970 Final RX Vref Byte 0 = 61 to rank0
8688 22:55:53.961947 Final RX Vref Byte 1 = 62 to rank0
8689 22:55:53.965492 Final RX Vref Byte 0 = 61 to rank1
8690 22:55:53.968790 Final RX Vref Byte 1 = 62 to rank1==
8691 22:55:53.971772 Dram Type= 6, Freq= 0, CH_1, rank 0
8692 22:55:53.978752 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8693 22:55:53.978838 ==
8694 22:55:53.978904 DQS Delay:
8695 22:55:53.981766 DQS0 = 0, DQS1 = 0
8696 22:55:53.981850 DQM Delay:
8697 22:55:53.981916 DQM0 = 134, DQM1 = 129
8698 22:55:53.985100 DQ Delay:
8699 22:55:53.988664 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =132
8700 22:55:53.991715 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =132
8701 22:55:53.994901 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =122
8702 22:55:53.998264 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =136
8703 22:55:53.998348
8704 22:55:53.998415
8705 22:55:53.998475
8706 22:55:54.001655 [DramC_TX_OE_Calibration] TA2
8707 22:55:54.004726 Original DQ_B0 (3 6) =30, OEN = 27
8708 22:55:54.008563 Original DQ_B1 (3 6) =30, OEN = 27
8709 22:55:54.011561 24, 0x0, End_B0=24 End_B1=24
8710 22:55:54.014736 25, 0x0, End_B0=25 End_B1=25
8711 22:55:54.014821 26, 0x0, End_B0=26 End_B1=26
8712 22:55:54.018015 27, 0x0, End_B0=27 End_B1=27
8713 22:55:54.021636 28, 0x0, End_B0=28 End_B1=28
8714 22:55:54.024781 29, 0x0, End_B0=29 End_B1=29
8715 22:55:54.024907 30, 0x0, End_B0=30 End_B1=30
8716 22:55:54.028290 31, 0x4141, End_B0=30 End_B1=30
8717 22:55:54.031525 Byte0 end_step=30 best_step=27
8718 22:55:54.034653 Byte1 end_step=30 best_step=27
8719 22:55:54.037974 Byte0 TX OE(2T, 0.5T) = (3, 3)
8720 22:55:54.041273 Byte1 TX OE(2T, 0.5T) = (3, 3)
8721 22:55:54.041357
8722 22:55:54.041423
8723 22:55:54.048097 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a28, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
8724 22:55:54.051189 CH1 RK0: MR19=303, MR18=1A28
8725 22:55:54.057793 CH1_RK0: MR19=0x303, MR18=0x1A28, DQSOSC=389, MR23=63, INC=24, DEC=16
8726 22:55:54.057878
8727 22:55:54.061478 ----->DramcWriteLeveling(PI) begin...
8728 22:55:54.061564 ==
8729 22:55:54.064359 Dram Type= 6, Freq= 0, CH_1, rank 1
8730 22:55:54.067676 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8731 22:55:54.067760 ==
8732 22:55:54.071100 Write leveling (Byte 0): 24 => 24
8733 22:55:54.074511 Write leveling (Byte 1): 30 => 30
8734 22:55:54.077540 DramcWriteLeveling(PI) end<-----
8735 22:55:54.077623
8736 22:55:54.077689 ==
8737 22:55:54.081066 Dram Type= 6, Freq= 0, CH_1, rank 1
8738 22:55:54.084921 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8739 22:55:54.085007 ==
8740 22:55:54.087671 [Gating] SW mode calibration
8741 22:55:54.094210 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8742 22:55:54.100749 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8743 22:55:54.104441 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8744 22:55:54.110975 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8745 22:55:54.114101 1 4 8 | B1->B0 | 3434 2323 | 1 1 | (1 1) (0 0)
8746 22:55:54.117523 1 4 12 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 1)
8747 22:55:54.123809 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8748 22:55:54.127317 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8749 22:55:54.130552 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8750 22:55:54.137692 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8751 22:55:54.140719 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8752 22:55:54.143819 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8753 22:55:54.150522 1 5 8 | B1->B0 | 2424 3434 | 0 1 | (1 0) (1 0)
8754 22:55:54.154034 1 5 12 | B1->B0 | 2323 2f2f | 0 1 | (1 0) (1 0)
8755 22:55:54.157102 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8756 22:55:54.163487 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8757 22:55:54.166926 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8758 22:55:54.170354 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8759 22:55:54.176966 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8760 22:55:54.179933 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8761 22:55:54.183433 1 6 8 | B1->B0 | 4141 2323 | 0 0 | (0 0) (0 0)
8762 22:55:54.189795 1 6 12 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
8763 22:55:54.193076 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8764 22:55:54.196499 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8765 22:55:54.203223 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8766 22:55:54.206371 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8767 22:55:54.209606 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8768 22:55:54.216210 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8769 22:55:54.220125 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8770 22:55:54.223102 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8771 22:55:54.229912 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 22:55:54.232722 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 22:55:54.236244 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 22:55:54.242706 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 22:55:54.246156 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 22:55:54.249368 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 22:55:54.256047 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 22:55:54.259137 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 22:55:54.262514 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 22:55:54.269511 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 22:55:54.272545 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 22:55:54.275946 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 22:55:54.282449 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 22:55:54.285717 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 22:55:54.289160 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8786 22:55:54.295972 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8787 22:55:54.298976 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8788 22:55:54.302378 Total UI for P1: 0, mck2ui 16
8789 22:55:54.305494 best dqsien dly found for B0: ( 1, 9, 10)
8790 22:55:54.309209 Total UI for P1: 0, mck2ui 16
8791 22:55:54.312263 best dqsien dly found for B1: ( 1, 9, 10)
8792 22:55:54.315726 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8793 22:55:54.318748 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8794 22:55:54.318832
8795 22:55:54.322234 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8796 22:55:54.325908 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8797 22:55:54.328709 [Gating] SW calibration Done
8798 22:55:54.328801 ==
8799 22:55:54.332030 Dram Type= 6, Freq= 0, CH_1, rank 1
8800 22:55:54.335345 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8801 22:55:54.338681 ==
8802 22:55:54.338763 RX Vref Scan: 0
8803 22:55:54.338831
8804 22:55:54.341847 RX Vref 0 -> 0, step: 1
8805 22:55:54.341931
8806 22:55:54.341997 RX Delay 0 -> 252, step: 8
8807 22:55:54.348733 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8808 22:55:54.351851 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8809 22:55:54.355495 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8810 22:55:54.359724 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8811 22:55:54.361963 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8812 22:55:54.368730 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8813 22:55:54.371566 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8814 22:55:54.375436 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8815 22:55:54.378524 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8816 22:55:54.381583 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8817 22:55:54.388437 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8818 22:55:54.391712 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8819 22:55:54.394859 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8820 22:55:54.398400 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8821 22:55:54.404750 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8822 22:55:54.408237 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8823 22:55:54.408321 ==
8824 22:55:54.411460 Dram Type= 6, Freq= 0, CH_1, rank 1
8825 22:55:54.414735 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8826 22:55:54.414819 ==
8827 22:55:54.418008 DQS Delay:
8828 22:55:54.418091 DQS0 = 0, DQS1 = 0
8829 22:55:54.418158 DQM Delay:
8830 22:55:54.421200 DQM0 = 136, DQM1 = 131
8831 22:55:54.421283 DQ Delay:
8832 22:55:54.424422 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8833 22:55:54.427621 DQ4 =139, DQ5 =147, DQ6 =143, DQ7 =135
8834 22:55:54.434313 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8835 22:55:54.437890 DQ12 =143, DQ13 =139, DQ14 =135, DQ15 =143
8836 22:55:54.437978
8837 22:55:54.438053
8838 22:55:54.438116 ==
8839 22:55:54.440807 Dram Type= 6, Freq= 0, CH_1, rank 1
8840 22:55:54.444716 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8841 22:55:54.444821 ==
8842 22:55:54.444888
8843 22:55:54.444948
8844 22:55:54.447589 TX Vref Scan disable
8845 22:55:54.450940 == TX Byte 0 ==
8846 22:55:54.454691 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8847 22:55:54.457317 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8848 22:55:54.460758 == TX Byte 1 ==
8849 22:55:54.464122 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8850 22:55:54.467638 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8851 22:55:54.467721 ==
8852 22:55:54.470727 Dram Type= 6, Freq= 0, CH_1, rank 1
8853 22:55:54.474121 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8854 22:55:54.477181 ==
8855 22:55:54.488660
8856 22:55:54.491957 TX Vref early break, caculate TX vref
8857 22:55:54.495298 TX Vref=16, minBit 9, minWin=21, winSum=381
8858 22:55:54.498631 TX Vref=18, minBit 10, minWin=22, winSum=390
8859 22:55:54.501744 TX Vref=20, minBit 8, minWin=23, winSum=400
8860 22:55:54.505204 TX Vref=22, minBit 8, minWin=24, winSum=403
8861 22:55:54.508519 TX Vref=24, minBit 9, minWin=24, winSum=411
8862 22:55:54.515714 TX Vref=26, minBit 8, minWin=24, winSum=415
8863 22:55:54.518722 TX Vref=28, minBit 0, minWin=25, winSum=415
8864 22:55:54.521992 TX Vref=30, minBit 8, minWin=24, winSum=405
8865 22:55:54.525260 TX Vref=32, minBit 8, minWin=22, winSum=396
8866 22:55:54.528502 TX Vref=34, minBit 8, minWin=23, winSum=390
8867 22:55:54.534981 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 28
8868 22:55:54.535065
8869 22:55:54.538422 Final TX Range 0 Vref 28
8870 22:55:54.538506
8871 22:55:54.538572 ==
8872 22:55:54.541913 Dram Type= 6, Freq= 0, CH_1, rank 1
8873 22:55:54.544980 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8874 22:55:54.545064 ==
8875 22:55:54.545131
8876 22:55:54.545192
8877 22:55:54.548570 TX Vref Scan disable
8878 22:55:54.554679 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8879 22:55:54.554763 == TX Byte 0 ==
8880 22:55:54.558096 u2DelayCellOfst[0]=16 cells (5 PI)
8881 22:55:54.561371 u2DelayCellOfst[1]=10 cells (3 PI)
8882 22:55:54.565264 u2DelayCellOfst[2]=0 cells (0 PI)
8883 22:55:54.568106 u2DelayCellOfst[3]=10 cells (3 PI)
8884 22:55:54.571224 u2DelayCellOfst[4]=10 cells (3 PI)
8885 22:55:54.575089 u2DelayCellOfst[5]=20 cells (6 PI)
8886 22:55:54.577928 u2DelayCellOfst[6]=20 cells (6 PI)
8887 22:55:54.581623 u2DelayCellOfst[7]=6 cells (2 PI)
8888 22:55:54.584416 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8889 22:55:54.588175 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8890 22:55:54.591142 == TX Byte 1 ==
8891 22:55:54.594721 u2DelayCellOfst[8]=0 cells (0 PI)
8892 22:55:54.594803 u2DelayCellOfst[9]=3 cells (1 PI)
8893 22:55:54.597694 u2DelayCellOfst[10]=10 cells (3 PI)
8894 22:55:54.601130 u2DelayCellOfst[11]=3 cells (1 PI)
8895 22:55:54.604556 u2DelayCellOfst[12]=13 cells (4 PI)
8896 22:55:54.608026 u2DelayCellOfst[13]=16 cells (5 PI)
8897 22:55:54.611652 u2DelayCellOfst[14]=16 cells (5 PI)
8898 22:55:54.614240 u2DelayCellOfst[15]=16 cells (5 PI)
8899 22:55:54.620918 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8900 22:55:54.624177 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8901 22:55:54.624259 DramC Write-DBI on
8902 22:55:54.624324 ==
8903 22:55:54.627706 Dram Type= 6, Freq= 0, CH_1, rank 1
8904 22:55:54.634222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8905 22:55:54.634305 ==
8906 22:55:54.634370
8907 22:55:54.634431
8908 22:55:54.634490 TX Vref Scan disable
8909 22:55:54.638309 == TX Byte 0 ==
8910 22:55:54.641641 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8911 22:55:54.644901 == TX Byte 1 ==
8912 22:55:54.648169 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8913 22:55:54.651378 DramC Write-DBI off
8914 22:55:54.651461
8915 22:55:54.651525 [DATLAT]
8916 22:55:54.651586 Freq=1600, CH1 RK1
8917 22:55:54.651645
8918 22:55:54.654516 DATLAT Default: 0xf
8919 22:55:54.657923 0, 0xFFFF, sum = 0
8920 22:55:54.658007 1, 0xFFFF, sum = 0
8921 22:55:54.661208 2, 0xFFFF, sum = 0
8922 22:55:54.661291 3, 0xFFFF, sum = 0
8923 22:55:54.664386 4, 0xFFFF, sum = 0
8924 22:55:54.664469 5, 0xFFFF, sum = 0
8925 22:55:54.667894 6, 0xFFFF, sum = 0
8926 22:55:54.668006 7, 0xFFFF, sum = 0
8927 22:55:54.671102 8, 0xFFFF, sum = 0
8928 22:55:54.671186 9, 0xFFFF, sum = 0
8929 22:55:54.674464 10, 0xFFFF, sum = 0
8930 22:55:54.674547 11, 0xFFFF, sum = 0
8931 22:55:54.677849 12, 0xFFFF, sum = 0
8932 22:55:54.677932 13, 0xFFFF, sum = 0
8933 22:55:54.681125 14, 0x0, sum = 1
8934 22:55:54.681209 15, 0x0, sum = 2
8935 22:55:54.684640 16, 0x0, sum = 3
8936 22:55:54.684724 17, 0x0, sum = 4
8937 22:55:54.688021 best_step = 15
8938 22:55:54.688104
8939 22:55:54.688170 ==
8940 22:55:54.690960 Dram Type= 6, Freq= 0, CH_1, rank 1
8941 22:55:54.694192 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8942 22:55:54.694277 ==
8943 22:55:54.697884 RX Vref Scan: 0
8944 22:55:54.697967
8945 22:55:54.698032 RX Vref 0 -> 0, step: 1
8946 22:55:54.698094
8947 22:55:54.701286 RX Delay 19 -> 252, step: 4
8948 22:55:54.707361 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
8949 22:55:54.710894 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8950 22:55:54.713867 iDelay=195, Bit 2, Center 122 (75 ~ 170) 96
8951 22:55:54.717821 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8952 22:55:54.720494 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8953 22:55:54.724129 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8954 22:55:54.730749 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8955 22:55:54.733698 iDelay=195, Bit 7, Center 132 (83 ~ 182) 100
8956 22:55:54.737310 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8957 22:55:54.740591 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8958 22:55:54.743619 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8959 22:55:54.750526 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8960 22:55:54.753569 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8961 22:55:54.756897 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8962 22:55:54.760616 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8963 22:55:54.767012 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8964 22:55:54.767096 ==
8965 22:55:54.770334 Dram Type= 6, Freq= 0, CH_1, rank 1
8966 22:55:54.773724 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8967 22:55:54.773808 ==
8968 22:55:54.773875 DQS Delay:
8969 22:55:54.776623 DQS0 = 0, DQS1 = 0
8970 22:55:54.776738 DQM Delay:
8971 22:55:54.780297 DQM0 = 134, DQM1 = 130
8972 22:55:54.780381 DQ Delay:
8973 22:55:54.783679 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8974 22:55:54.786592 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8975 22:55:54.790289 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =126
8976 22:55:54.793091 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
8977 22:55:54.793175
8978 22:55:54.796679
8979 22:55:54.796762
8980 22:55:54.796869 [DramC_TX_OE_Calibration] TA2
8981 22:55:54.800199 Original DQ_B0 (3 6) =30, OEN = 27
8982 22:55:54.803070 Original DQ_B1 (3 6) =30, OEN = 27
8983 22:55:54.806738 24, 0x0, End_B0=24 End_B1=24
8984 22:55:54.809941 25, 0x0, End_B0=25 End_B1=25
8985 22:55:54.813063 26, 0x0, End_B0=26 End_B1=26
8986 22:55:54.813149 27, 0x0, End_B0=27 End_B1=27
8987 22:55:54.816461 28, 0x0, End_B0=28 End_B1=28
8988 22:55:54.819657 29, 0x0, End_B0=29 End_B1=29
8989 22:55:54.822819 30, 0x0, End_B0=30 End_B1=30
8990 22:55:54.826247 31, 0x4141, End_B0=30 End_B1=30
8991 22:55:54.826336 Byte0 end_step=30 best_step=27
8992 22:55:54.829393 Byte1 end_step=30 best_step=27
8993 22:55:54.833007 Byte0 TX OE(2T, 0.5T) = (3, 3)
8994 22:55:54.836411 Byte1 TX OE(2T, 0.5T) = (3, 3)
8995 22:55:54.836495
8996 22:55:54.836560
8997 22:55:54.846113 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f0a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 394 ps
8998 22:55:54.846199 CH1 RK1: MR19=303, MR18=1F0A
8999 22:55:54.853091 CH1_RK1: MR19=0x303, MR18=0x1F0A, DQSOSC=394, MR23=63, INC=23, DEC=15
9000 22:55:54.856147 [RxdqsGatingPostProcess] freq 1600
9001 22:55:54.863150 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9002 22:55:54.866485 best DQS0 dly(2T, 0.5T) = (1, 1)
9003 22:55:54.869844 best DQS1 dly(2T, 0.5T) = (1, 1)
9004 22:55:54.869946 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9005 22:55:54.872677 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9006 22:55:54.876070 best DQS0 dly(2T, 0.5T) = (1, 1)
9007 22:55:54.879840 best DQS1 dly(2T, 0.5T) = (1, 1)
9008 22:55:54.882864 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9009 22:55:54.885996 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9010 22:55:54.889196 Pre-setting of DQS Precalculation
9011 22:55:54.892592 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9012 22:55:54.902674 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9013 22:55:54.909288 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9014 22:55:54.909367
9015 22:55:54.909431
9016 22:55:54.912699 [Calibration Summary] 3200 Mbps
9017 22:55:54.912833 CH 0, Rank 0
9018 22:55:54.915943 SW Impedance : PASS
9019 22:55:54.919247 DUTY Scan : NO K
9020 22:55:54.919349 ZQ Calibration : PASS
9021 22:55:54.922278 Jitter Meter : NO K
9022 22:55:54.925676 CBT Training : PASS
9023 22:55:54.925775 Write leveling : PASS
9024 22:55:54.928902 RX DQS gating : PASS
9025 22:55:54.929002 RX DQ/DQS(RDDQC) : PASS
9026 22:55:54.932252 TX DQ/DQS : PASS
9027 22:55:54.935526 RX DATLAT : PASS
9028 22:55:54.935624 RX DQ/DQS(Engine): PASS
9029 22:55:54.938852 TX OE : PASS
9030 22:55:54.938951 All Pass.
9031 22:55:54.939043
9032 22:55:54.941961 CH 0, Rank 1
9033 22:55:54.942062 SW Impedance : PASS
9034 22:55:54.945866 DUTY Scan : NO K
9035 22:55:54.948958 ZQ Calibration : PASS
9036 22:55:54.949056 Jitter Meter : NO K
9037 22:55:54.951900 CBT Training : PASS
9038 22:55:54.955299 Write leveling : PASS
9039 22:55:54.955399 RX DQS gating : PASS
9040 22:55:54.958693 RX DQ/DQS(RDDQC) : PASS
9041 22:55:54.962103 TX DQ/DQS : PASS
9042 22:55:54.962202 RX DATLAT : PASS
9043 22:55:54.965263 RX DQ/DQS(Engine): PASS
9044 22:55:54.968490 TX OE : PASS
9045 22:55:54.968588 All Pass.
9046 22:55:54.968677
9047 22:55:54.968773 CH 1, Rank 0
9048 22:55:54.971999 SW Impedance : PASS
9049 22:55:54.975434 DUTY Scan : NO K
9050 22:55:54.975533 ZQ Calibration : PASS
9051 22:55:54.978309 Jitter Meter : NO K
9052 22:55:54.982350 CBT Training : PASS
9053 22:55:54.982452 Write leveling : PASS
9054 22:55:54.985403 RX DQS gating : PASS
9055 22:55:54.985500 RX DQ/DQS(RDDQC) : PASS
9056 22:55:54.988586 TX DQ/DQS : PASS
9057 22:55:54.991525 RX DATLAT : PASS
9058 22:55:54.991624 RX DQ/DQS(Engine): PASS
9059 22:55:54.995102 TX OE : PASS
9060 22:55:54.995201 All Pass.
9061 22:55:54.995293
9062 22:55:54.998726 CH 1, Rank 1
9063 22:55:54.998827 SW Impedance : PASS
9064 22:55:55.001897 DUTY Scan : NO K
9065 22:55:55.005155 ZQ Calibration : PASS
9066 22:55:55.005251 Jitter Meter : NO K
9067 22:55:55.008518 CBT Training : PASS
9068 22:55:55.011511 Write leveling : PASS
9069 22:55:55.011606 RX DQS gating : PASS
9070 22:55:55.015092 RX DQ/DQS(RDDQC) : PASS
9071 22:55:55.017965 TX DQ/DQS : PASS
9072 22:55:55.018063 RX DATLAT : PASS
9073 22:55:55.021593 RX DQ/DQS(Engine): PASS
9074 22:55:55.025213 TX OE : PASS
9075 22:55:55.025310 All Pass.
9076 22:55:55.025402
9077 22:55:55.028089 DramC Write-DBI on
9078 22:55:55.028188 PER_BANK_REFRESH: Hybrid Mode
9079 22:55:55.031414 TX_TRACKING: ON
9080 22:55:55.038276 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9081 22:55:55.048041 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9082 22:55:55.054604 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9083 22:55:55.057776 [FAST_K] Save calibration result to emmc
9084 22:55:55.061062 sync common calibartion params.
9085 22:55:55.064224 sync cbt_mode0:1, 1:1
9086 22:55:55.064307 dram_init: ddr_geometry: 2
9087 22:55:55.067629 dram_init: ddr_geometry: 2
9088 22:55:55.070861 dram_init: ddr_geometry: 2
9089 22:55:55.074754 0:dram_rank_size:100000000
9090 22:55:55.074839 1:dram_rank_size:100000000
9091 22:55:55.080715 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9092 22:55:55.083885 DFS_SHUFFLE_HW_MODE: ON
9093 22:55:55.087576 dramc_set_vcore_voltage set vcore to 725000
9094 22:55:55.090801 Read voltage for 1600, 0
9095 22:55:55.090876 Vio18 = 0
9096 22:55:55.090951 Vcore = 725000
9097 22:55:55.094170 Vdram = 0
9098 22:55:55.094246 Vddq = 0
9099 22:55:55.094315 Vmddr = 0
9100 22:55:55.097363 switch to 3200 Mbps bootup
9101 22:55:55.097439 [DramcRunTimeConfig]
9102 22:55:55.101022 PHYPLL
9103 22:55:55.101098 DPM_CONTROL_AFTERK: ON
9104 22:55:55.103718 PER_BANK_REFRESH: ON
9105 22:55:55.107267 REFRESH_OVERHEAD_REDUCTION: ON
9106 22:55:55.107347 CMD_PICG_NEW_MODE: OFF
9107 22:55:55.110447 XRTWTW_NEW_MODE: ON
9108 22:55:55.110524 XRTRTR_NEW_MODE: ON
9109 22:55:55.113639 TX_TRACKING: ON
9110 22:55:55.113713 RDSEL_TRACKING: OFF
9111 22:55:55.117373 DQS Precalculation for DVFS: ON
9112 22:55:55.120507 RX_TRACKING: OFF
9113 22:55:55.120581 HW_GATING DBG: ON
9114 22:55:55.124122 ZQCS_ENABLE_LP4: ON
9115 22:55:55.124199 RX_PICG_NEW_MODE: ON
9116 22:55:55.127429 TX_PICG_NEW_MODE: ON
9117 22:55:55.127504 ENABLE_RX_DCM_DPHY: ON
9118 22:55:55.130528 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9119 22:55:55.133489 DUMMY_READ_FOR_TRACKING: OFF
9120 22:55:55.137049 !!! SPM_CONTROL_AFTERK: OFF
9121 22:55:55.140398 !!! SPM could not control APHY
9122 22:55:55.140479 IMPEDANCE_TRACKING: ON
9123 22:55:55.143613 TEMP_SENSOR: ON
9124 22:55:55.143685 HW_SAVE_FOR_SR: OFF
9125 22:55:55.146955 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9126 22:55:55.150460 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9127 22:55:55.153650 Read ODT Tracking: ON
9128 22:55:55.157125 Refresh Rate DeBounce: ON
9129 22:55:55.157195 DFS_NO_QUEUE_FLUSH: ON
9130 22:55:55.160186 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9131 22:55:55.163428 ENABLE_DFS_RUNTIME_MRW: OFF
9132 22:55:55.167044 DDR_RESERVE_NEW_MODE: ON
9133 22:55:55.167114 MR_CBT_SWITCH_FREQ: ON
9134 22:55:55.170085 =========================
9135 22:55:55.189015 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9136 22:55:55.192643 dram_init: ddr_geometry: 2
9137 22:55:55.210823 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9138 22:55:55.214023 dram_init: dram init end (result: 0)
9139 22:55:55.220660 DRAM-K: Full calibration passed in 24465 msecs
9140 22:55:55.223980 MRC: failed to locate region type 0.
9141 22:55:55.224073 DRAM rank0 size:0x100000000,
9142 22:55:55.227090 DRAM rank1 size=0x100000000
9143 22:55:55.237084 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9144 22:55:55.243553 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9145 22:55:55.250556 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9146 22:55:55.257229 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9147 22:55:55.260347 DRAM rank0 size:0x100000000,
9148 22:55:55.263617 DRAM rank1 size=0x100000000
9149 22:55:55.263693 CBMEM:
9150 22:55:55.266865 IMD: root @ 0xfffff000 254 entries.
9151 22:55:55.270296 IMD: root @ 0xffffec00 62 entries.
9152 22:55:55.273410 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9153 22:55:55.280135 WARNING: RO_VPD is uninitialized or empty.
9154 22:55:55.283420 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9155 22:55:55.290613 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9156 22:55:55.303531 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9157 22:55:55.314794 BS: romstage times (exec / console): total (unknown) / 23972 ms
9158 22:55:55.314879
9159 22:55:55.314968
9160 22:55:55.325244 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9161 22:55:55.328183 ARM64: Exception handlers installed.
9162 22:55:55.331314 ARM64: Testing exception
9163 22:55:55.334852 ARM64: Done test exception
9164 22:55:55.334936 Enumerating buses...
9165 22:55:55.337948 Show all devs... Before device enumeration.
9166 22:55:55.341288 Root Device: enabled 1
9167 22:55:55.344559 CPU_CLUSTER: 0: enabled 1
9168 22:55:55.344641 CPU: 00: enabled 1
9169 22:55:55.348002 Compare with tree...
9170 22:55:55.348084 Root Device: enabled 1
9171 22:55:55.351469 CPU_CLUSTER: 0: enabled 1
9172 22:55:55.354466 CPU: 00: enabled 1
9173 22:55:55.354548 Root Device scanning...
9174 22:55:55.358124 scan_static_bus for Root Device
9175 22:55:55.360927 CPU_CLUSTER: 0 enabled
9176 22:55:55.364586 scan_static_bus for Root Device done
9177 22:55:55.367396 scan_bus: bus Root Device finished in 8 msecs
9178 22:55:55.367479 done
9179 22:55:55.374410 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9180 22:55:55.377441 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9181 22:55:55.384554 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9182 22:55:55.387351 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9183 22:55:55.390688 Allocating resources...
9184 22:55:55.394147 Reading resources...
9185 22:55:55.397315 Root Device read_resources bus 0 link: 0
9186 22:55:55.400613 DRAM rank0 size:0x100000000,
9187 22:55:55.400713 DRAM rank1 size=0x100000000
9188 22:55:55.404605 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9189 22:55:55.407165 CPU: 00 missing read_resources
9190 22:55:55.414036 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9191 22:55:55.417324 Root Device read_resources bus 0 link: 0 done
9192 22:55:55.417411 Done reading resources.
9193 22:55:55.423990 Show resources in subtree (Root Device)...After reading.
9194 22:55:55.427158 Root Device child on link 0 CPU_CLUSTER: 0
9195 22:55:55.430723 CPU_CLUSTER: 0 child on link 0 CPU: 00
9196 22:55:55.440413 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9197 22:55:55.440498 CPU: 00
9198 22:55:55.443486 Root Device assign_resources, bus 0 link: 0
9199 22:55:55.446927 CPU_CLUSTER: 0 missing set_resources
9200 22:55:55.453699 Root Device assign_resources, bus 0 link: 0 done
9201 22:55:55.453783 Done setting resources.
9202 22:55:55.460086 Show resources in subtree (Root Device)...After assigning values.
9203 22:55:55.463256 Root Device child on link 0 CPU_CLUSTER: 0
9204 22:55:55.466876 CPU_CLUSTER: 0 child on link 0 CPU: 00
9205 22:55:55.476718 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9206 22:55:55.476808 CPU: 00
9207 22:55:55.480098 Done allocating resources.
9208 22:55:55.486455 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9209 22:55:55.486563 Enabling resources...
9210 22:55:55.489498 done.
9211 22:55:55.492897 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9212 22:55:55.496297 Initializing devices...
9213 22:55:55.496398 Root Device init
9214 22:55:55.499652 init hardware done!
9215 22:55:55.499755 0x00000018: ctrlr->caps
9216 22:55:55.503309 52.000 MHz: ctrlr->f_max
9217 22:55:55.506276 0.400 MHz: ctrlr->f_min
9218 22:55:55.506378 0x40ff8080: ctrlr->voltages
9219 22:55:55.509618 sclk: 390625
9220 22:55:55.509717 Bus Width = 1
9221 22:55:55.513178 sclk: 390625
9222 22:55:55.513277 Bus Width = 1
9223 22:55:55.516247 Early init status = 3
9224 22:55:55.519930 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9225 22:55:55.523524 in-header: 03 fc 00 00 01 00 00 00
9226 22:55:55.526911 in-data: 00
9227 22:55:55.530016 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9228 22:55:55.535569 in-header: 03 fd 00 00 00 00 00 00
9229 22:55:55.539281 in-data:
9230 22:55:55.542127 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9231 22:55:55.546695 in-header: 03 fc 00 00 01 00 00 00
9232 22:55:55.549968 in-data: 00
9233 22:55:55.553325 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9234 22:55:55.559032 in-header: 03 fd 00 00 00 00 00 00
9235 22:55:55.562537 in-data:
9236 22:55:55.565779 [SSUSB] Setting up USB HOST controller...
9237 22:55:55.568835 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9238 22:55:55.572262 [SSUSB] phy power-on done.
9239 22:55:55.575455 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9240 22:55:55.582157 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9241 22:55:55.585505 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9242 22:55:55.591955 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9243 22:55:55.598727 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9244 22:55:55.605140 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9245 22:55:55.611680 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9246 22:55:55.618407 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9247 22:55:55.622138 SPM: binary array size = 0x9dc
9248 22:55:55.624936 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9249 22:55:55.631620 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9250 22:55:55.638293 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9251 22:55:55.645221 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9252 22:55:55.648193 configure_display: Starting display init
9253 22:55:55.682417 anx7625_power_on_init: Init interface.
9254 22:55:55.685600 anx7625_disable_pd_protocol: Disabled PD feature.
9255 22:55:55.688713 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9256 22:55:55.716586 anx7625_start_dp_work: Secure OCM version=00
9257 22:55:55.719975 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9258 22:55:55.734558 sp_tx_get_edid_block: EDID Block = 1
9259 22:55:55.837103 Extracted contents:
9260 22:55:55.840624 header: 00 ff ff ff ff ff ff 00
9261 22:55:55.843817 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9262 22:55:55.847252 version: 01 04
9263 22:55:55.850605 basic params: 95 1f 11 78 0a
9264 22:55:55.853764 chroma info: 76 90 94 55 54 90 27 21 50 54
9265 22:55:55.856962 established: 00 00 00
9266 22:55:55.863661 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9267 22:55:55.866958 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9268 22:55:55.873900 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9269 22:55:55.880466 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9270 22:55:55.886686 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9271 22:55:55.890155 extensions: 00
9272 22:55:55.890256 checksum: fb
9273 22:55:55.890350
9274 22:55:55.893696 Manufacturer: IVO Model 57d Serial Number 0
9275 22:55:55.896527 Made week 0 of 2020
9276 22:55:55.900196 EDID version: 1.4
9277 22:55:55.900295 Digital display
9278 22:55:55.903061 6 bits per primary color channel
9279 22:55:55.903162 DisplayPort interface
9280 22:55:55.906738 Maximum image size: 31 cm x 17 cm
9281 22:55:55.910215 Gamma: 220%
9282 22:55:55.910317 Check DPMS levels
9283 22:55:55.913011 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9284 22:55:55.920524 First detailed timing is preferred timing
9285 22:55:55.920626 Established timings supported:
9286 22:55:55.923199 Standard timings supported:
9287 22:55:55.926525 Detailed timings
9288 22:55:55.929818 Hex of detail: 383680a07038204018303c0035ae10000019
9289 22:55:55.936729 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9290 22:55:55.939736 0780 0798 07c8 0820 hborder 0
9291 22:55:55.943024 0438 043b 0447 0458 vborder 0
9292 22:55:55.946185 -hsync -vsync
9293 22:55:55.946273 Did detailed timing
9294 22:55:55.953056 Hex of detail: 000000000000000000000000000000000000
9295 22:55:55.956298 Manufacturer-specified data, tag 0
9296 22:55:55.959585 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9297 22:55:55.962728 ASCII string: InfoVision
9298 22:55:55.966066 Hex of detail: 000000fe00523134304e574635205248200a
9299 22:55:55.969454 ASCII string: R140NWF5 RH
9300 22:55:55.969555 Checksum
9301 22:55:55.972579 Checksum: 0xfb (valid)
9302 22:55:55.975974 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9303 22:55:55.979303 DSI data_rate: 832800000 bps
9304 22:55:55.985806 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9305 22:55:55.989094 anx7625_parse_edid: pixelclock(138800).
9306 22:55:55.992744 hactive(1920), hsync(48), hfp(24), hbp(88)
9307 22:55:55.995650 vactive(1080), vsync(12), vfp(3), vbp(17)
9308 22:55:55.999406 anx7625_dsi_config: config dsi.
9309 22:55:56.005913 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9310 22:55:56.019212 anx7625_dsi_config: success to config DSI
9311 22:55:56.022482 anx7625_dp_start: MIPI phy setup OK.
9312 22:55:56.025917 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9313 22:55:56.029216 mtk_ddp_mode_set invalid vrefresh 60
9314 22:55:56.032449 main_disp_path_setup
9315 22:55:56.032547 ovl_layer_smi_id_en
9316 22:55:56.036040 ovl_layer_smi_id_en
9317 22:55:56.036140 ccorr_config
9318 22:55:56.036228 aal_config
9319 22:55:56.039414 gamma_config
9320 22:55:56.039514 postmask_config
9321 22:55:56.042464 dither_config
9322 22:55:56.045867 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9323 22:55:56.052349 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9324 22:55:56.055694 Root Device init finished in 555 msecs
9325 22:55:56.058824 CPU_CLUSTER: 0 init
9326 22:55:56.065613 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9327 22:55:56.069004 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9328 22:55:56.072225 APU_MBOX 0x190000b0 = 0x10001
9329 22:55:56.075565 APU_MBOX 0x190001b0 = 0x10001
9330 22:55:56.078856 APU_MBOX 0x190005b0 = 0x10001
9331 22:55:56.082380 APU_MBOX 0x190006b0 = 0x10001
9332 22:55:56.085598 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9333 22:55:56.098364 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9334 22:55:56.111060 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9335 22:55:56.117141 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9336 22:55:56.129066 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9337 22:55:56.138448 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9338 22:55:56.141493 CPU_CLUSTER: 0 init finished in 81 msecs
9339 22:55:56.145020 Devices initialized
9340 22:55:56.147852 Show all devs... After init.
9341 22:55:56.147951 Root Device: enabled 1
9342 22:55:56.151187 CPU_CLUSTER: 0: enabled 1
9343 22:55:56.154603 CPU: 00: enabled 1
9344 22:55:56.157884 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9345 22:55:56.161001 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9346 22:55:56.164729 ELOG: NV offset 0x57f000 size 0x1000
9347 22:55:56.171162 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9348 22:55:56.178137 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9349 22:55:56.181450 ELOG: Event(17) added with size 13 at 2023-06-05 22:55:53 UTC
9350 22:55:56.187605 out: cmd=0x121: 03 db 21 01 00 00 00 00
9351 22:55:56.191086 in-header: 03 52 00 00 2c 00 00 00
9352 22:55:56.200965 in-data: 0d 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9353 22:55:56.207855 ELOG: Event(A1) added with size 10 at 2023-06-05 22:55:53 UTC
9354 22:55:56.214675 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9355 22:55:56.221020 ELOG: Event(A0) added with size 9 at 2023-06-05 22:55:53 UTC
9356 22:55:56.223953 ELOG: Event(16) added with size 11 at 2023-06-05 22:55:53 UTC
9357 22:55:56.299663 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9358 22:55:56.302873 elog_add_boot_reason: Logged dev mode boot
9359 22:55:56.309465 BS: BS_POST_DEVICE entry times (exec / console): 71 / 74 ms
9360 22:55:56.309540 Finalize devices...
9361 22:55:56.312757 Devices finalized
9362 22:55:56.315978 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9363 22:55:56.319483 Writing coreboot table at 0xffe64000
9364 22:55:56.326104 0. 000000000010a000-0000000000113fff: RAMSTAGE
9365 22:55:56.329375 1. 0000000040000000-00000000400fffff: RAM
9366 22:55:56.332844 2. 0000000040100000-000000004032afff: RAMSTAGE
9367 22:55:56.335909 3. 000000004032b000-00000000545fffff: RAM
9368 22:55:56.339224 4. 0000000054600000-000000005465ffff: BL31
9369 22:55:56.342831 5. 0000000054660000-00000000ffe63fff: RAM
9370 22:55:56.349141 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9371 22:55:56.352708 7. 0000000100000000-000000023fffffff: RAM
9372 22:55:56.355849 Passing 5 GPIOs to payload:
9373 22:55:56.359323 NAME | PORT | POLARITY | VALUE
9374 22:55:56.366247 EC in RW | 0x000000aa | low | undefined
9375 22:55:56.369561 EC interrupt | 0x00000005 | low | undefined
9376 22:55:56.375849 TPM interrupt | 0x000000ab | high | undefined
9377 22:55:56.379010 SD card detect | 0x00000011 | high | undefined
9378 22:55:56.382653 speaker enable | 0x00000093 | high | undefined
9379 22:55:56.385566 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9380 22:55:56.389133 in-header: 03 f9 00 00 02 00 00 00
9381 22:55:56.392309 in-data: 02 00
9382 22:55:56.395812 ADC[4]: Raw value=901401 ID=7
9383 22:55:56.398963 ADC[3]: Raw value=213179 ID=1
9384 22:55:56.399047 RAM Code: 0x71
9385 22:55:56.402575 ADC[6]: Raw value=74502 ID=0
9386 22:55:56.405427 ADC[5]: Raw value=212072 ID=1
9387 22:55:56.405510 SKU Code: 0x1
9388 22:55:56.412568 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4bb3
9389 22:55:56.412654 coreboot table: 964 bytes.
9390 22:55:56.415469 IMD ROOT 0. 0xfffff000 0x00001000
9391 22:55:56.418999 IMD SMALL 1. 0xffffe000 0x00001000
9392 22:55:56.422065 RO MCACHE 2. 0xffffc000 0x00001104
9393 22:55:56.425491 CONSOLE 3. 0xfff7c000 0x00080000
9394 22:55:56.428817 FMAP 4. 0xfff7b000 0x00000452
9395 22:55:56.432258 TIME STAMP 5. 0xfff7a000 0x00000910
9396 22:55:56.435324 VBOOT WORK 6. 0xfff66000 0x00014000
9397 22:55:56.438524 RAMOOPS 7. 0xffe66000 0x00100000
9398 22:55:56.442167 COREBOOT 8. 0xffe64000 0x00002000
9399 22:55:56.445304 IMD small region:
9400 22:55:56.448987 IMD ROOT 0. 0xffffec00 0x00000400
9401 22:55:56.451646 VPD 1. 0xffffeba0 0x0000004c
9402 22:55:56.455158 MMC STATUS 2. 0xffffeb80 0x00000004
9403 22:55:56.462108 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9404 22:55:56.462192 Probing TPM: done!
9405 22:55:56.465130 Connected to device vid:did:rid of 1ae0:0028:00
9406 22:55:56.476342 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9407 22:55:56.479849 Initialized TPM device CR50 revision 0
9408 22:55:56.483589 Checking cr50 for pending updates
9409 22:55:56.487729 Reading cr50 TPM mode
9410 22:55:56.495998 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9411 22:55:56.502585 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9412 22:55:56.542822 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9413 22:55:56.546453 Checking segment from ROM address 0x40100000
9414 22:55:56.549298 Checking segment from ROM address 0x4010001c
9415 22:55:56.555982 Loading segment from ROM address 0x40100000
9416 22:55:56.556066 code (compression=0)
9417 22:55:56.565965 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9418 22:55:56.572770 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9419 22:55:56.572888 it's not compressed!
9420 22:55:56.580652 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9421 22:55:56.582802 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9422 22:55:56.603933 Loading segment from ROM address 0x4010001c
9423 22:55:56.604018 Entry Point 0x80000000
9424 22:55:56.607522 Loaded segments
9425 22:55:56.610934 BS: BS_PAYLOAD_LOAD run times (exec / console): 49 / 61 ms
9426 22:55:56.617342 Jumping to boot code at 0x80000000(0xffe64000)
9427 22:55:56.623860 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9428 22:55:56.630508 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9429 22:55:56.638452 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9430 22:55:56.642166 Checking segment from ROM address 0x40100000
9431 22:55:56.645216 Checking segment from ROM address 0x4010001c
9432 22:55:56.651832 Loading segment from ROM address 0x40100000
9433 22:55:56.651916 code (compression=1)
9434 22:55:56.658384 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9435 22:55:56.668457 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9436 22:55:56.668541 using LZMA
9437 22:55:56.676910 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9438 22:55:56.683670 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9439 22:55:56.686705 Loading segment from ROM address 0x4010001c
9440 22:55:56.686781 Entry Point 0x54601000
9441 22:55:56.690539 Loaded segments
9442 22:55:56.693379 NOTICE: MT8192 bl31_setup
9443 22:55:56.700706 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9444 22:55:56.704005 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9445 22:55:56.707197 WARNING: region 0:
9446 22:55:56.710371 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9447 22:55:56.710454 WARNING: region 1:
9448 22:55:56.716760 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9449 22:55:56.720219 WARNING: region 2:
9450 22:55:56.723676 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9451 22:55:56.727368 WARNING: region 3:
9452 22:55:56.730243 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9453 22:55:56.733449 WARNING: region 4:
9454 22:55:56.740008 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9455 22:55:56.740091 WARNING: region 5:
9456 22:55:56.743298 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9457 22:55:56.746536 WARNING: region 6:
9458 22:55:56.750260 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9459 22:55:56.753671 WARNING: region 7:
9460 22:55:56.757189 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9461 22:55:56.763401 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9462 22:55:56.766473 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9463 22:55:56.772968 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9464 22:55:56.776770 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9465 22:55:56.779602 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9466 22:55:56.786237 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9467 22:55:56.789988 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9468 22:55:56.793071 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9469 22:55:56.799907 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9470 22:55:56.802959 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9471 22:55:56.809687 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9472 22:55:56.812930 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9473 22:55:56.816073 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9474 22:55:56.822945 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9475 22:55:56.826268 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9476 22:55:56.829670 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9477 22:55:56.836055 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9478 22:55:56.839428 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9479 22:55:56.845847 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9480 22:55:56.849374 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9481 22:55:56.853062 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9482 22:55:56.859431 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9483 22:55:56.862558 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9484 22:55:56.869265 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9485 22:55:56.872089 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9486 22:55:56.875753 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9487 22:55:56.882509 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9488 22:55:56.885710 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9489 22:55:56.892178 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9490 22:55:56.895501 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9491 22:55:56.898551 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9492 22:55:56.905516 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9493 22:55:56.908978 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9494 22:55:56.911777 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9495 22:55:56.918769 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9496 22:55:56.921788 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9497 22:55:56.925037 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9498 22:55:56.928187 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9499 22:55:56.934896 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9500 22:55:56.938360 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9501 22:55:56.941894 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9502 22:55:56.944962 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9503 22:55:56.951819 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9504 22:55:56.954663 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9505 22:55:56.957994 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9506 22:55:56.964759 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9507 22:55:56.968544 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9508 22:55:56.971570 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9509 22:55:56.978116 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9510 22:55:56.981509 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9511 22:55:56.985050 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9512 22:55:56.991758 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9513 22:55:56.994569 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9514 22:55:57.001486 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9515 22:55:57.004656 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9516 22:55:57.007842 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9517 22:55:57.014664 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9518 22:55:57.017905 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9519 22:55:57.024362 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9520 22:55:57.027786 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9521 22:55:57.034334 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9522 22:55:57.038075 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9523 22:55:57.044425 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9524 22:55:57.047760 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9525 22:55:57.051002 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9526 22:55:57.057781 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9527 22:55:57.060790 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9528 22:55:57.067624 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9529 22:55:57.070813 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9530 22:55:57.077764 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9531 22:55:57.080922 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9532 22:55:57.087331 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9533 22:55:57.090627 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9534 22:55:57.094024 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9535 22:55:57.100798 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9536 22:55:57.104359 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9537 22:55:57.110577 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9538 22:55:57.113746 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9539 22:55:57.120887 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9540 22:55:57.124148 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9541 22:55:57.130423 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9542 22:55:57.133950 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9543 22:55:57.137077 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9544 22:55:57.143643 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9545 22:55:57.147250 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9546 22:55:57.154023 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9547 22:55:57.156959 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9548 22:55:57.163855 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9549 22:55:57.166828 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9550 22:55:57.170504 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9551 22:55:57.176948 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9552 22:55:57.180346 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9553 22:55:57.187210 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9554 22:55:57.190251 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9555 22:55:57.197066 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9556 22:55:57.200251 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9557 22:55:57.203456 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9558 22:55:57.210057 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9559 22:55:57.213601 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9560 22:55:57.216916 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9561 22:55:57.220129 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9562 22:55:57.226565 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9563 22:55:57.229932 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9564 22:55:57.236816 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9565 22:55:57.240104 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9566 22:55:57.243278 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9567 22:55:57.249712 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9568 22:55:57.253036 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9569 22:55:57.260114 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9570 22:55:57.262960 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9571 22:55:57.266522 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9572 22:55:57.273251 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9573 22:55:57.276522 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9574 22:55:57.283251 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9575 22:55:57.286179 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9576 22:55:57.289408 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9577 22:55:57.296094 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9578 22:55:57.299695 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9579 22:55:57.302693 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9580 22:55:57.309320 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9581 22:55:57.313177 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9582 22:55:57.315987 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9583 22:55:57.319233 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9584 22:55:57.325762 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9585 22:55:57.329358 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9586 22:55:57.332524 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9587 22:55:57.339327 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9588 22:55:57.342452 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9589 22:55:57.348997 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9590 22:55:57.352112 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9591 22:55:57.355620 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9592 22:55:57.361974 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9593 22:55:57.365294 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9594 22:55:57.372349 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9595 22:55:57.375833 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9596 22:55:57.379244 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9597 22:55:57.385798 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9598 22:55:57.388887 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9599 22:55:57.395479 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9600 22:55:57.398523 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9601 22:55:57.402086 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9602 22:55:57.408663 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9603 22:55:57.411860 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9604 22:55:57.418859 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9605 22:55:57.422164 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9606 22:55:57.425271 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9607 22:55:57.431783 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9608 22:55:57.435526 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9609 22:55:57.441679 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9610 22:55:57.445407 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9611 22:55:57.448763 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9612 22:55:57.455153 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9613 22:55:57.458499 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9614 22:55:57.461983 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9615 22:55:57.468144 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9616 22:55:57.471594 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9617 22:55:57.478462 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9618 22:55:57.481871 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9619 22:55:57.485091 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9620 22:55:57.491635 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9621 22:55:57.495004 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9622 22:55:57.501421 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9623 22:55:57.505037 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9624 22:55:57.508051 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9625 22:55:57.514740 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9626 22:55:57.518254 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9627 22:55:57.524497 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9628 22:55:57.527884 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9629 22:55:57.531256 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9630 22:55:57.537918 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9631 22:55:57.541273 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9632 22:55:57.547710 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9633 22:55:57.551469 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9634 22:55:57.554275 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9635 22:55:57.560722 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9636 22:55:57.564261 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9637 22:55:57.570801 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9638 22:55:57.574875 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9639 22:55:57.577304 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9640 22:55:57.583971 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9641 22:55:57.587448 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9642 22:55:57.593955 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9643 22:55:57.597118 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9644 22:55:57.600527 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9645 22:55:57.607264 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9646 22:55:57.610489 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9647 22:55:57.617090 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9648 22:55:57.620331 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9649 22:55:57.623594 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9650 22:55:57.630253 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9651 22:55:57.633500 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9652 22:55:57.640004 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9653 22:55:57.643373 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9654 22:55:57.649955 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9655 22:55:57.653284 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9656 22:55:57.656420 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9657 22:55:57.663344 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9658 22:55:57.666393 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9659 22:55:57.673010 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9660 22:55:57.676498 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9661 22:55:57.682913 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9662 22:55:57.686021 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9663 22:55:57.690084 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9664 22:55:57.695878 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9665 22:55:57.699165 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9666 22:55:57.705927 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9667 22:55:57.709149 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9668 22:55:57.715948 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9669 22:55:57.718916 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9670 22:55:57.722519 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9671 22:55:57.728950 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9672 22:55:57.732189 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9673 22:55:57.738858 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9674 22:55:57.742120 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9675 22:55:57.745767 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9676 22:55:57.752330 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9677 22:55:57.755444 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9678 22:55:57.761731 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9679 22:55:57.765148 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9680 22:55:57.771946 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9681 22:55:57.775192 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9682 22:55:57.781623 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9683 22:55:57.784998 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9684 22:55:57.788589 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9685 22:55:57.795149 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9686 22:55:57.798579 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9687 22:55:57.804949 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9688 22:55:57.808568 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9689 22:55:57.811537 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9690 22:55:57.818649 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9691 22:55:57.821437 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9692 22:55:57.824431 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9693 22:55:57.828017 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9694 22:55:57.834344 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9695 22:55:57.837768 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9696 22:55:57.840928 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9697 22:55:57.847823 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9698 22:55:57.851153 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9699 22:55:57.854514 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9700 22:55:57.861095 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9701 22:55:57.864250 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9702 22:55:57.871064 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9703 22:55:57.874419 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9704 22:55:57.877471 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9705 22:55:57.884021 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9706 22:55:57.887288 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9707 22:55:57.894127 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9708 22:55:57.897186 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9709 22:55:57.901018 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9710 22:55:57.907263 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9711 22:55:57.910444 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9712 22:55:57.913747 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9713 22:55:57.920395 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9714 22:55:57.923713 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9715 22:55:57.927141 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9716 22:55:57.933684 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9717 22:55:57.937215 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9718 22:55:57.943573 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9719 22:55:57.946810 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9720 22:55:57.950163 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9721 22:55:57.957060 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9722 22:55:57.960287 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9723 22:55:57.966607 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9724 22:55:57.970182 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9725 22:55:57.973478 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9726 22:55:57.980224 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9727 22:55:57.983520 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9728 22:55:57.987205 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9729 22:55:57.993718 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9730 22:55:57.996671 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9731 22:55:57.999720 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9732 22:55:58.003151 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9733 22:55:58.009632 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9734 22:55:58.013019 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9735 22:55:58.016425 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9736 22:55:58.019626 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9737 22:55:58.026430 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9738 22:55:58.029277 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9739 22:55:58.033111 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9740 22:55:58.035929 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9741 22:55:58.042961 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9742 22:55:58.045975 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9743 22:55:58.049570 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9744 22:55:58.055924 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9745 22:55:58.059232 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9746 22:55:58.066148 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9747 22:55:58.069135 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9748 22:55:58.076069 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9749 22:55:58.079200 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9750 22:55:58.082574 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9751 22:55:58.089004 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9752 22:55:58.092401 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9753 22:55:58.099011 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9754 22:55:58.102185 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9755 22:55:58.105362 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9756 22:55:58.112240 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9757 22:55:58.115225 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9758 22:55:58.121953 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9759 22:55:58.125037 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9760 22:55:58.128554 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9761 22:55:58.135109 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9762 22:55:58.138498 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9763 22:55:58.145026 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9764 22:55:58.148459 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9765 22:55:58.155184 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9766 22:55:58.158689 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9767 22:55:58.161499 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9768 22:55:58.168185 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9769 22:55:58.171280 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9770 22:55:58.178216 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9771 22:55:58.181675 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9772 22:55:58.188224 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9773 22:55:58.191564 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9774 22:55:58.194670 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9775 22:55:58.201106 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9776 22:55:58.204556 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9777 22:55:58.211526 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9778 22:55:58.214650 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9779 22:55:58.217843 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9780 22:55:58.224244 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9781 22:55:58.227438 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9782 22:55:58.234299 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9783 22:55:58.237603 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9784 22:55:58.241311 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9785 22:55:58.247754 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9786 22:55:58.250830 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9787 22:55:58.257437 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9788 22:55:58.260667 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9789 22:55:58.267324 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9790 22:55:58.270779 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9791 22:55:58.274020 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9792 22:55:58.280478 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9793 22:55:58.283820 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9794 22:55:58.290571 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9795 22:55:58.293728 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9796 22:55:58.297202 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9797 22:55:58.303863 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9798 22:55:58.307302 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9799 22:55:58.313543 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9800 22:55:58.317086 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9801 22:55:58.320146 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9802 22:55:58.326663 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9803 22:55:58.330129 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9804 22:55:58.336720 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9805 22:55:58.340144 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9806 22:55:58.343705 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9807 22:55:58.350252 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9808 22:55:58.353244 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9809 22:55:58.359805 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9810 22:55:58.363223 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9811 22:55:58.369651 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9812 22:55:58.372785 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9813 22:55:58.379571 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9814 22:55:58.383293 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9815 22:55:58.386392 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9816 22:55:58.393042 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9817 22:55:58.396087 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9818 22:55:58.403120 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9819 22:55:58.406264 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9820 22:55:58.412706 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9821 22:55:58.416200 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9822 22:55:58.419642 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9823 22:55:58.426332 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9824 22:55:58.429607 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9825 22:55:58.436334 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9826 22:55:58.439603 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9827 22:55:58.445911 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9828 22:55:58.449287 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9829 22:55:58.453060 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9830 22:55:58.459073 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9831 22:55:58.463007 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9832 22:55:58.469397 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9833 22:55:58.472423 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9834 22:55:58.479205 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9835 22:55:58.482328 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9836 22:55:58.489424 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9837 22:55:58.492179 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9838 22:55:58.495569 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9839 22:55:58.501975 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9840 22:55:58.505392 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9841 22:55:58.511724 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9842 22:55:58.515482 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9843 22:55:58.522991 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9844 22:55:58.524956 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9845 22:55:58.531740 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9846 22:55:58.534845 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9847 22:55:58.538248 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9848 22:55:58.544646 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9849 22:55:58.548479 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9850 22:55:58.554956 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9851 22:55:58.558037 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9852 22:55:58.564630 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9853 22:55:58.567599 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9854 22:55:58.571029 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9855 22:55:58.577499 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9856 22:55:58.580971 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9857 22:55:58.587913 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9858 22:55:58.591068 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9859 22:55:58.597310 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9860 22:55:58.600962 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9861 22:55:58.607393 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9862 22:55:58.610771 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9863 22:55:58.614256 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9864 22:55:58.620638 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9865 22:55:58.624303 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9866 22:55:58.630411 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9867 22:55:58.633701 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9868 22:55:58.640332 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9869 22:55:58.643896 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9870 22:55:58.650485 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9871 22:55:58.653769 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9872 22:55:58.660394 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9873 22:55:58.663456 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9874 22:55:58.670268 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9875 22:55:58.673219 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9876 22:55:58.679874 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9877 22:55:58.683165 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9878 22:55:58.689902 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9879 22:55:58.693248 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9880 22:55:58.699520 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9881 22:55:58.702850 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9882 22:55:58.709580 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9883 22:55:58.712874 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9884 22:55:58.720110 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9885 22:55:58.722908 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9886 22:55:58.729590 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9887 22:55:58.733073 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9888 22:55:58.739548 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9889 22:55:58.742627 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9890 22:55:58.749771 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9891 22:55:58.752484 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9892 22:55:58.759400 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9893 22:55:58.762823 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9894 22:55:58.769037 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9895 22:55:58.772401 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9896 22:55:58.775557 INFO: [APUAPC] vio 0
9897 22:55:58.779019 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9898 22:55:58.785420 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9899 22:55:58.788827 INFO: [APUAPC] D0_APC_0: 0x400510
9900 22:55:58.788905 INFO: [APUAPC] D0_APC_1: 0x0
9901 22:55:58.792249 INFO: [APUAPC] D0_APC_2: 0x1540
9902 22:55:58.795505 INFO: [APUAPC] D0_APC_3: 0x0
9903 22:55:58.799027 INFO: [APUAPC] D1_APC_0: 0xffffffff
9904 22:55:58.802356 INFO: [APUAPC] D1_APC_1: 0xffffffff
9905 22:55:58.805453 INFO: [APUAPC] D1_APC_2: 0x3fffff
9906 22:55:58.808559 INFO: [APUAPC] D1_APC_3: 0x0
9907 22:55:58.811981 INFO: [APUAPC] D2_APC_0: 0xffffffff
9908 22:55:58.815618 INFO: [APUAPC] D2_APC_1: 0xffffffff
9909 22:55:58.818908 INFO: [APUAPC] D2_APC_2: 0x3fffff
9910 22:55:58.821963 INFO: [APUAPC] D2_APC_3: 0x0
9911 22:55:58.825315 INFO: [APUAPC] D3_APC_0: 0xffffffff
9912 22:55:58.828510 INFO: [APUAPC] D3_APC_1: 0xffffffff
9913 22:55:58.832151 INFO: [APUAPC] D3_APC_2: 0x3fffff
9914 22:55:58.834908 INFO: [APUAPC] D3_APC_3: 0x0
9915 22:55:58.838420 INFO: [APUAPC] D4_APC_0: 0xffffffff
9916 22:55:58.841984 INFO: [APUAPC] D4_APC_1: 0xffffffff
9917 22:55:58.844961 INFO: [APUAPC] D4_APC_2: 0x3fffff
9918 22:55:58.848641 INFO: [APUAPC] D4_APC_3: 0x0
9919 22:55:58.851570 INFO: [APUAPC] D5_APC_0: 0xffffffff
9920 22:55:58.854943 INFO: [APUAPC] D5_APC_1: 0xffffffff
9921 22:55:58.858209 INFO: [APUAPC] D5_APC_2: 0x3fffff
9922 22:55:58.861424 INFO: [APUAPC] D5_APC_3: 0x0
9923 22:55:58.864895 INFO: [APUAPC] D6_APC_0: 0xffffffff
9924 22:55:58.868355 INFO: [APUAPC] D6_APC_1: 0xffffffff
9925 22:55:58.871627 INFO: [APUAPC] D6_APC_2: 0x3fffff
9926 22:55:58.874753 INFO: [APUAPC] D6_APC_3: 0x0
9927 22:55:58.878019 INFO: [APUAPC] D7_APC_0: 0xffffffff
9928 22:55:58.881287 INFO: [APUAPC] D7_APC_1: 0xffffffff
9929 22:55:58.884636 INFO: [APUAPC] D7_APC_2: 0x3fffff
9930 22:55:58.887841 INFO: [APUAPC] D7_APC_3: 0x0
9931 22:55:58.891116 INFO: [APUAPC] D8_APC_0: 0xffffffff
9932 22:55:58.894348 INFO: [APUAPC] D8_APC_1: 0xffffffff
9933 22:55:58.897587 INFO: [APUAPC] D8_APC_2: 0x3fffff
9934 22:55:58.901675 INFO: [APUAPC] D8_APC_3: 0x0
9935 22:55:58.904399 INFO: [APUAPC] D9_APC_0: 0xffffffff
9936 22:55:58.907499 INFO: [APUAPC] D9_APC_1: 0xffffffff
9937 22:55:58.911069 INFO: [APUAPC] D9_APC_2: 0x3fffff
9938 22:55:58.914338 INFO: [APUAPC] D9_APC_3: 0x0
9939 22:55:58.917565 INFO: [APUAPC] D10_APC_0: 0xffffffff
9940 22:55:58.921124 INFO: [APUAPC] D10_APC_1: 0xffffffff
9941 22:55:58.924329 INFO: [APUAPC] D10_APC_2: 0x3fffff
9942 22:55:58.927550 INFO: [APUAPC] D10_APC_3: 0x0
9943 22:55:58.930865 INFO: [APUAPC] D11_APC_0: 0xffffffff
9944 22:55:58.933995 INFO: [APUAPC] D11_APC_1: 0xffffffff
9945 22:55:58.937495 INFO: [APUAPC] D11_APC_2: 0x3fffff
9946 22:55:58.940748 INFO: [APUAPC] D11_APC_3: 0x0
9947 22:55:58.944135 INFO: [APUAPC] D12_APC_0: 0xffffffff
9948 22:55:58.947423 INFO: [APUAPC] D12_APC_1: 0xffffffff
9949 22:55:58.950780 INFO: [APUAPC] D12_APC_2: 0x3fffff
9950 22:55:58.954257 INFO: [APUAPC] D12_APC_3: 0x0
9951 22:55:58.957386 INFO: [APUAPC] D13_APC_0: 0xffffffff
9952 22:55:58.960555 INFO: [APUAPC] D13_APC_1: 0xffffffff
9953 22:55:58.963981 INFO: [APUAPC] D13_APC_2: 0x3fffff
9954 22:55:58.967164 INFO: [APUAPC] D13_APC_3: 0x0
9955 22:55:58.970340 INFO: [APUAPC] D14_APC_0: 0xffffffff
9956 22:55:58.973770 INFO: [APUAPC] D14_APC_1: 0xffffffff
9957 22:55:58.976968 INFO: [APUAPC] D14_APC_2: 0x3fffff
9958 22:55:58.980389 INFO: [APUAPC] D14_APC_3: 0x0
9959 22:55:58.983752 INFO: [APUAPC] D15_APC_0: 0xffffffff
9960 22:55:58.987269 INFO: [APUAPC] D15_APC_1: 0xffffffff
9961 22:55:58.990625 INFO: [APUAPC] D15_APC_2: 0x3fffff
9962 22:55:58.993456 INFO: [APUAPC] D15_APC_3: 0x0
9963 22:55:58.997005 INFO: [APUAPC] APC_CON: 0x4
9964 22:55:59.000408 INFO: [NOCDAPC] D0_APC_0: 0x0
9965 22:55:59.003552 INFO: [NOCDAPC] D0_APC_1: 0x0
9966 22:55:59.003629 INFO: [NOCDAPC] D1_APC_0: 0x0
9967 22:55:59.006877 INFO: [NOCDAPC] D1_APC_1: 0xfff
9968 22:55:59.010276 INFO: [NOCDAPC] D2_APC_0: 0x0
9969 22:55:59.013194 INFO: [NOCDAPC] D2_APC_1: 0xfff
9970 22:55:59.016628 INFO: [NOCDAPC] D3_APC_0: 0x0
9971 22:55:59.020037 INFO: [NOCDAPC] D3_APC_1: 0xfff
9972 22:55:59.023431 INFO: [NOCDAPC] D4_APC_0: 0x0
9973 22:55:59.027054 INFO: [NOCDAPC] D4_APC_1: 0xfff
9974 22:55:59.029674 INFO: [NOCDAPC] D5_APC_0: 0x0
9975 22:55:59.033063 INFO: [NOCDAPC] D5_APC_1: 0xfff
9976 22:55:59.036567 INFO: [NOCDAPC] D6_APC_0: 0x0
9977 22:55:59.039749 INFO: [NOCDAPC] D6_APC_1: 0xfff
9978 22:55:59.039823 INFO: [NOCDAPC] D7_APC_0: 0x0
9979 22:55:59.044222 INFO: [NOCDAPC] D7_APC_1: 0xfff
9980 22:55:59.046663 INFO: [NOCDAPC] D8_APC_0: 0x0
9981 22:55:59.049597 INFO: [NOCDAPC] D8_APC_1: 0xfff
9982 22:55:59.053126 INFO: [NOCDAPC] D9_APC_0: 0x0
9983 22:55:59.056513 INFO: [NOCDAPC] D9_APC_1: 0xfff
9984 22:55:59.059846 INFO: [NOCDAPC] D10_APC_0: 0x0
9985 22:55:59.063288 INFO: [NOCDAPC] D10_APC_1: 0xfff
9986 22:55:59.066363 INFO: [NOCDAPC] D11_APC_0: 0x0
9987 22:55:59.069721 INFO: [NOCDAPC] D11_APC_1: 0xfff
9988 22:55:59.073131 INFO: [NOCDAPC] D12_APC_0: 0x0
9989 22:55:59.076494 INFO: [NOCDAPC] D12_APC_1: 0xfff
9990 22:55:59.079606 INFO: [NOCDAPC] D13_APC_0: 0x0
9991 22:55:59.079681 INFO: [NOCDAPC] D13_APC_1: 0xfff
9992 22:55:59.083171 INFO: [NOCDAPC] D14_APC_0: 0x0
9993 22:55:59.086312 INFO: [NOCDAPC] D14_APC_1: 0xfff
9994 22:55:59.089637 INFO: [NOCDAPC] D15_APC_0: 0x0
9995 22:55:59.092664 INFO: [NOCDAPC] D15_APC_1: 0xfff
9996 22:55:59.096306 INFO: [NOCDAPC] APC_CON: 0x4
9997 22:55:59.099496 INFO: [APUAPC] set_apusys_apc done
9998 22:55:59.102779 INFO: [DEVAPC] devapc_init done
9999 22:55:59.106500 INFO: GICv3 without legacy support detected.
10000 22:55:59.112606 INFO: ARM GICv3 driver initialized in EL3
10001 22:55:59.116117 INFO: Maximum SPI INTID supported: 639
10002 22:55:59.119518 INFO: BL31: Initializing runtime services
10003 22:55:59.125888 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10004 22:55:59.125964 INFO: SPM: enable CPC mode
10005 22:55:59.132536 INFO: mcdi ready for mcusys-off-idle and system suspend
10006 22:55:59.135775 INFO: BL31: Preparing for EL3 exit to normal world
10007 22:55:59.142267 INFO: Entry point address = 0x80000000
10008 22:55:59.142349 INFO: SPSR = 0x8
10009 22:55:59.148714
10010 22:55:59.148835
10011 22:55:59.148903
10012 22:55:59.151859 Starting depthcharge on Spherion...
10013 22:55:59.151937
10014 22:55:59.151999 Wipe memory regions:
10015 22:55:59.152063
10016 22:55:59.152685 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10017 22:55:59.152822 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10018 22:55:59.152925 Setting prompt string to ['asurada:']
10019 22:55:59.153005 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10020 22:55:59.155066 [0x00000040000000, 0x00000054600000)
10021 22:55:59.277374
10022 22:55:59.277478 [0x00000054660000, 0x00000080000000)
10023 22:55:59.536648
10024 22:55:59.536776 [0x000000821a7280, 0x000000ffe64000)
10025 22:56:00.280704
10026 22:56:00.280860 [0x00000100000000, 0x00000240000000)
10027 22:56:02.168290
10028 22:56:02.171816 Initializing XHCI USB controller at 0x11200000.
10029 22:56:03.210176
10030 22:56:03.213765 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10031 22:56:03.213858
10032 22:56:03.213933
10033 22:56:03.213997
10034 22:56:03.214273 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10036 22:56:03.314600 asurada: tftpboot 192.168.201.1 10597637/tftp-deploy-_q_lfg_t/kernel/image.itb 10597637/tftp-deploy-_q_lfg_t/kernel/cmdline
10037 22:56:03.314765 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10038 22:56:03.314856 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10039 22:56:03.319135 tftpboot 192.168.201.1 10597637/tftp-deploy-_q_lfg_t/kernel/image.ittp-deploy-_q_lfg_t/kernel/cmdline
10040 22:56:03.319247
10041 22:56:03.319351 Waiting for link
10042 22:56:03.479657
10043 22:56:03.479814 R8152: Initializing
10044 22:56:03.479883
10045 22:56:03.483081 Version 9 (ocp_data = 6010)
10046 22:56:03.483172
10047 22:56:03.486066 R8152: Done initializing
10048 22:56:03.486149
10049 22:56:03.486214 Adding net device
10050 22:56:05.358962
10051 22:56:05.359529 done.
10052 22:56:05.359904
10053 22:56:05.360249 MAC: 00:e0:4c:72:2d:d6
10054 22:56:05.360586
10055 22:56:05.361880 Sending DHCP discover... done.
10056 22:56:05.362347
10057 22:56:05.365559 Waiting for reply... done.
10058 22:56:05.366124
10059 22:56:05.368860 Sending DHCP request... done.
10060 22:56:05.369340
10061 22:56:05.373167 Waiting for reply... done.
10062 22:56:05.373730
10063 22:56:05.374103 My ip is 192.168.201.21
10064 22:56:05.374448
10065 22:56:05.375876 The DHCP server ip is 192.168.201.1
10066 22:56:05.376344
10067 22:56:05.382784 TFTP server IP predefined by user: 192.168.201.1
10068 22:56:05.383358
10069 22:56:05.389105 Bootfile predefined by user: 10597637/tftp-deploy-_q_lfg_t/kernel/image.itb
10070 22:56:05.389619
10071 22:56:05.389992 Sending tftp read request... done.
10072 22:56:05.392077
10073 22:56:05.395427 Waiting for the transfer...
10074 22:56:05.395576
10075 22:56:05.729095 00000000 ################################################################
10076 22:56:05.729252
10077 22:56:06.082058 00080000 ################################################################
10078 22:56:06.082241
10079 22:56:06.397976 00100000 ################################################################
10080 22:56:06.398118
10081 22:56:06.692118 00180000 ################################################################
10082 22:56:06.692258
10083 22:56:07.074281 00200000 ################################################################
10084 22:56:07.074788
10085 22:56:07.423853 00280000 ################################################################
10086 22:56:07.423986
10087 22:56:07.673088 00300000 ################################################################
10088 22:56:07.673228
10089 22:56:07.943291 00380000 ################################################################
10090 22:56:07.943455
10091 22:56:08.206645 00400000 ################################################################
10092 22:56:08.206777
10093 22:56:08.474622 00480000 ################################################################
10094 22:56:08.474755
10095 22:56:08.729546 00500000 ################################################################
10096 22:56:08.729676
10097 22:56:08.988409 00580000 ################################################################
10098 22:56:08.988566
10099 22:56:09.253562 00600000 ################################################################
10100 22:56:09.253714
10101 22:56:09.512977 00680000 ################################################################
10102 22:56:09.513100
10103 22:56:09.769999 00700000 ################################################################
10104 22:56:09.770130
10105 22:56:10.039508 00780000 ################################################################
10106 22:56:10.039632
10107 22:56:10.333746 00800000 ################################################################
10108 22:56:10.333880
10109 22:56:10.590077 00880000 ################################################################
10110 22:56:10.590218
10111 22:56:10.839218 00900000 ################################################################
10112 22:56:10.839343
10113 22:56:11.089166 00980000 ################################################################
10114 22:56:11.089307
10115 22:56:11.365055 00a00000 ################################################################
10116 22:56:11.365185
10117 22:56:11.669157 00a80000 ################################################################
10118 22:56:11.669291
10119 22:56:11.925670 00b00000 ################################################################
10120 22:56:11.925800
10121 22:56:12.196846 00b80000 ################################################################
10122 22:56:12.196989
10123 22:56:12.514997 00c00000 ################################################################
10124 22:56:12.515135
10125 22:56:12.809338 00c80000 ################################################################
10126 22:56:12.809481
10127 22:56:13.106264 00d00000 ################################################################
10128 22:56:13.106399
10129 22:56:13.400377 00d80000 ################################################################
10130 22:56:13.400513
10131 22:56:13.698159 00e00000 ################################################################
10132 22:56:13.698288
10133 22:56:13.995201 00e80000 ################################################################
10134 22:56:13.995338
10135 22:56:14.293449 00f00000 ################################################################
10136 22:56:14.293593
10137 22:56:14.590176 00f80000 ################################################################
10138 22:56:14.590307
10139 22:56:14.878155 01000000 ################################################################
10140 22:56:14.878286
10141 22:56:15.175347 01080000 ################################################################
10142 22:56:15.175510
10143 22:56:15.470124 01100000 ################################################################
10144 22:56:15.470290
10145 22:56:15.801714 01180000 ################################################################
10146 22:56:15.801898
10147 22:56:16.086366 01200000 ################################################################
10148 22:56:16.086525
10149 22:56:16.335784 01280000 ################################################################
10150 22:56:16.335931
10151 22:56:16.627184 01300000 ################################################################
10152 22:56:16.627331
10153 22:56:16.978848 01380000 ################################################################
10154 22:56:16.979003
10155 22:56:17.336686 01400000 ################################################################
10156 22:56:17.336884
10157 22:56:17.643606 01480000 ################################################################
10158 22:56:17.643781
10159 22:56:17.898089 01500000 ################################################################
10160 22:56:17.898263
10161 22:56:18.153022 01580000 ################################################################
10162 22:56:18.153197
10163 22:56:18.404048 01600000 ################################################################
10164 22:56:18.404221
10165 22:56:18.699913 01680000 ################################################################
10166 22:56:18.700054
10167 22:56:18.953149 01700000 ################################################################
10168 22:56:18.953310
10169 22:56:19.202758 01780000 ################################################################
10170 22:56:19.202927
10171 22:56:19.458276 01800000 ################################################################
10172 22:56:19.458415
10173 22:56:19.748218 01880000 ################################################################
10174 22:56:19.748364
10175 22:56:20.026616 01900000 ################################################################
10176 22:56:20.026754
10177 22:56:20.316251 01980000 ################################################################
10178 22:56:20.316397
10179 22:56:20.611935 01a00000 ################################################################
10180 22:56:20.612070
10181 22:56:20.908002 01a80000 ################################################################
10182 22:56:20.908132
10183 22:56:21.203141 01b00000 ################################################################
10184 22:56:21.203283
10185 22:56:21.523498 01b80000 ################################################################
10186 22:56:21.523677
10187 22:56:21.865353 01c00000 ################################################################
10188 22:56:21.865510
10189 22:56:22.178082 01c80000 ################################################################
10190 22:56:22.178258
10191 22:56:22.493020 01d00000 ################################################################
10192 22:56:22.493167
10193 22:56:22.790264 01d80000 ################################################################
10194 22:56:22.790397
10195 22:56:23.086564 01e00000 ################################################################
10196 22:56:23.086703
10197 22:56:23.383099 01e80000 ################################################################
10198 22:56:23.383229
10199 22:56:23.650147 01f00000 ################################################################
10200 22:56:23.650278
10201 22:56:23.903088 01f80000 ################################################################
10202 22:56:23.903245
10203 22:56:24.175513 02000000 ################################################################
10204 22:56:24.175669
10205 22:56:24.434255 02080000 ################################################################
10206 22:56:24.434433
10207 22:56:24.691621 02100000 ################################################################
10208 22:56:24.691751
10209 22:56:24.977704 02180000 ################################################################
10210 22:56:24.977838
10211 22:56:25.246745 02200000 ################################################################
10212 22:56:25.246875
10213 22:56:25.540394 02280000 ################################################################
10214 22:56:25.540537
10215 22:56:25.837436 02300000 ################################################################
10216 22:56:25.837572
10217 22:56:26.134055 02380000 ################################################################
10218 22:56:26.134190
10219 22:56:26.406415 02400000 ################################################################
10220 22:56:26.406563
10221 22:56:26.698706 02480000 ################################################################
10222 22:56:26.698846
10223 22:56:26.981490 02500000 ################################################################
10224 22:56:26.981628
10225 22:56:27.263099 02580000 ################################################################
10226 22:56:27.263238
10227 22:56:27.532558 02600000 ################################################################
10228 22:56:27.532699
10229 22:56:27.823992 02680000 ################################################################
10230 22:56:27.824142
10231 22:56:28.138205 02700000 ################################################################
10232 22:56:28.138348
10233 22:56:28.387788 02780000 ################################################################
10234 22:56:28.387923
10235 22:56:28.637696 02800000 ################################################################
10236 22:56:28.637832
10237 22:56:28.903932 02880000 ################################################################
10238 22:56:28.904067
10239 22:56:29.155151 02900000 ################################################################
10240 22:56:29.155281
10241 22:56:29.421702 02980000 ################################################################
10242 22:56:29.421848
10243 22:56:29.693249 02a00000 ################################################################
10244 22:56:29.693383
10245 22:56:29.954969 02a80000 ################################################################
10246 22:56:29.955101
10247 22:56:30.213528 02b00000 ################################################################
10248 22:56:30.213662
10249 22:56:30.538560 02b80000 ################################################################
10250 22:56:30.538731
10251 22:56:30.892927 02c00000 ################################################################
10252 22:56:30.893078
10253 22:56:31.247633 02c80000 ################################################################
10254 22:56:31.247836
10255 22:56:31.572370 02d00000 ################################################################
10256 22:56:31.572601
10257 22:56:31.863750 02d80000 ################################################################
10258 22:56:31.863951
10259 22:56:32.135149 02e00000 ################################################################
10260 22:56:32.135357
10261 22:56:32.406761 02e80000 ################################################################
10262 22:56:32.406922
10263 22:56:32.689437 02f00000 ################################################################
10264 22:56:32.689584
10265 22:56:32.972104 02f80000 ################################################################
10266 22:56:32.972312
10267 22:56:33.255445 03000000 ################################################################
10268 22:56:33.255611
10269 22:56:33.537279 03080000 ################################################################
10270 22:56:33.537440
10271 22:56:33.824593 03100000 ################################################################
10272 22:56:33.824796
10273 22:56:34.103183 03180000 ################################################################
10274 22:56:34.103377
10275 22:56:34.374039 03200000 ################################################################
10276 22:56:34.374261
10277 22:56:34.650794 03280000 ################################################################
10278 22:56:34.650960
10279 22:56:34.917943 03300000 ################################################################
10280 22:56:34.918136
10281 22:56:35.196013 03380000 ################################################################
10282 22:56:35.196215
10283 22:56:35.481389 03400000 ################################################################
10284 22:56:35.481637
10285 22:56:35.764575 03480000 ################################################################
10286 22:56:35.764807
10287 22:56:36.045334 03500000 ################################################################
10288 22:56:36.045536
10289 22:56:36.326520 03580000 ################################################################
10290 22:56:36.326681
10291 22:56:36.599277 03600000 ################################################################
10292 22:56:36.599443
10293 22:56:36.848143 03680000 ################################################################
10294 22:56:36.848333
10295 22:56:37.108367 03700000 ################################################################
10296 22:56:37.108588
10297 22:56:37.359324 03780000 ################################################################
10298 22:56:37.359480
10299 22:56:37.601230 03800000 ################################################################
10300 22:56:37.601386
10301 22:56:37.890667 03880000 ################################################################
10302 22:56:37.890834
10303 22:56:38.174378 03900000 ################################################################
10304 22:56:38.174533
10305 22:56:38.453780 03980000 ################################################################
10306 22:56:38.453934
10307 22:56:38.754215 03a00000 ################################################################
10308 22:56:38.754422
10309 22:56:39.086016 03a80000 ################################################################
10310 22:56:39.086215
10311 22:56:39.364526 03b00000 ################################################################
10312 22:56:39.364731
10313 22:56:39.653633 03b80000 ################################################################
10314 22:56:39.653844
10315 22:56:39.994627 03c00000 ################################################################
10316 22:56:39.994835
10317 22:56:40.289489 03c80000 ################################################################
10318 22:56:40.289697
10319 22:56:40.558458 03d00000 ################################################################
10320 22:56:40.558667
10321 22:56:40.830084 03d80000 ################################################################
10322 22:56:40.830290
10323 22:56:41.088839 03e00000 ################################################################
10324 22:56:41.089043
10325 22:56:41.406634 03e80000 ################################################################
10326 22:56:41.406841
10327 22:56:41.685097 03f00000 ########################################################## done.
10328 22:56:41.685334
10329 22:56:41.688361 The bootfile was 66530078 bytes long.
10330 22:56:41.688526
10331 22:56:41.691771 Sending tftp read request... done.
10332 22:56:41.691916
10333 22:56:41.695395 Waiting for the transfer...
10334 22:56:41.695541
10335 22:56:41.695664 00000000 # done.
10336 22:56:41.695793
10337 22:56:41.705040 Command line loaded dynamically from TFTP file: 10597637/tftp-deploy-_q_lfg_t/kernel/cmdline
10338 22:56:41.705233
10339 22:56:41.714921 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10340 22:56:41.715100
10341 22:56:41.718027 Loading FIT.
10342 22:56:41.718165
10343 22:56:41.718287 Image ramdisk-1 has 56395176 bytes.
10344 22:56:41.721214
10345 22:56:41.721364 Image fdt-1 has 46924 bytes.
10346 22:56:41.721496
10347 22:56:41.724684 Image kernel-1 has 10085945 bytes.
10348 22:56:41.724846
10349 22:56:41.734559 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10350 22:56:41.734750
10351 22:56:41.751099 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10352 22:56:41.751319
10353 22:56:41.757847 Choosing best match conf-1 for compat google,spherion-rev2.
10354 22:56:41.761604
10355 22:56:41.765370 Connected to device vid:did:rid of 1ae0:0028:00
10356 22:56:41.773234
10357 22:56:41.776324 tpm_get_response: command 0x17b, return code 0x0
10358 22:56:41.776472
10359 22:56:41.782594 ec_init: CrosEC protocol v3 supported (256, 248)
10360 22:56:41.782751
10361 22:56:41.785819 tpm_cleanup: add release locality here.
10362 22:56:41.785976
10363 22:56:41.789315 Shutting down all USB controllers.
10364 22:56:41.789470
10365 22:56:41.792594 Removing current net device
10366 22:56:41.792732
10367 22:56:41.796056 Exiting depthcharge with code 4 at timestamp: 71996953
10368 22:56:41.799206
10369 22:56:41.802881 LZMA decompressing kernel-1 to 0x821a6718
10370 22:56:41.803036
10371 22:56:41.806093 LZMA decompressing kernel-1 to 0x40000000
10372 22:56:43.072176
10373 22:56:43.072376 jumping to kernel
10374 22:56:43.073248 end: 2.2.4 bootloader-commands (duration 00:00:44) [common]
10375 22:56:43.073429 start: 2.2.5 auto-login-action (timeout 00:03:41) [common]
10376 22:56:43.073550 Setting prompt string to ['Linux version [0-9]']
10377 22:56:43.073657 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10378 22:56:43.073767 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10379 22:56:43.154056
10380 22:56:43.157149 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10381 22:56:43.160866 start: 2.2.5.1 login-action (timeout 00:03:41) [common]
10382 22:56:43.160991 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10383 22:56:43.161112 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10384 22:56:43.161241 Using line separator: #'\n'#
10385 22:56:43.161305 No login prompt set.
10386 22:56:43.161370 Parsing kernel messages
10387 22:56:43.161428 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10388 22:56:43.161532 [login-action] Waiting for messages, (timeout 00:03:41)
10389 22:56:43.180439 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1612582-arm64-gcc-10-defconfig-arm64-chromebook-7xwc5) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 22:41:02 UTC 2023
10390 22:56:43.183604 [ 0.000000] random: crng init done
10391 22:56:43.186630 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10392 22:56:43.190040 [ 0.000000] efi: UEFI not found.
10393 22:56:43.200012 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10394 22:56:43.206470 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10395 22:56:43.216574 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10396 22:56:43.226616 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10397 22:56:43.233170 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10398 22:56:43.236461 [ 0.000000] printk: bootconsole [mtk8250] enabled
10399 22:56:43.245075 [ 0.000000] NUMA: No NUMA configuration found
10400 22:56:43.251969 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10401 22:56:43.258286 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10402 22:56:43.258467 [ 0.000000] Zone ranges:
10403 22:56:43.265285 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10404 22:56:43.268280 [ 0.000000] DMA32 empty
10405 22:56:43.274823 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10406 22:56:43.278248 [ 0.000000] Movable zone start for each node
10407 22:56:43.281695 [ 0.000000] Early memory node ranges
10408 22:56:43.287934 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10409 22:56:43.294639 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10410 22:56:43.301583 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10411 22:56:43.308164 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10412 22:56:43.314459 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10413 22:56:43.321158 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10414 22:56:43.377573 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10415 22:56:43.384382 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10416 22:56:43.391006 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10417 22:56:43.394414 [ 0.000000] psci: probing for conduit method from DT.
10418 22:56:43.400680 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10419 22:56:43.403871 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10420 22:56:43.410650 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10421 22:56:43.414095 [ 0.000000] psci: SMC Calling Convention v1.2
10422 22:56:43.420604 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10423 22:56:43.424183 [ 0.000000] Detected VIPT I-cache on CPU0
10424 22:56:43.430267 [ 0.000000] CPU features: detected: GIC system register CPU interface
10425 22:56:43.437270 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10426 22:56:43.443618 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10427 22:56:43.450531 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10428 22:56:43.460251 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10429 22:56:43.466858 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10430 22:56:43.470561 [ 0.000000] alternatives: applying boot alternatives
10431 22:56:43.476679 [ 0.000000] Fallback order for Node 0: 0
10432 22:56:43.483661 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10433 22:56:43.486837 [ 0.000000] Policy zone: Normal
10434 22:56:43.496914 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10435 22:56:43.507005 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10436 22:56:43.519678 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10437 22:56:43.529566 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10438 22:56:43.536118 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10439 22:56:43.539253 <6>[ 0.000000] software IO TLB: area num 8.
10440 22:56:43.596278 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10441 22:56:43.745258 <6>[ 0.000000] Memory: 7917868K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 434900K reserved, 32768K cma-reserved)
10442 22:56:43.752291 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10443 22:56:43.758989 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10444 22:56:43.762115 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10445 22:56:43.768552 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10446 22:56:43.774938 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10447 22:56:43.778006 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10448 22:56:43.787931 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10449 22:56:43.794873 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10450 22:56:43.801099 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10451 22:56:43.807527 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10452 22:56:43.811150 <6>[ 0.000000] GICv3: 608 SPIs implemented
10453 22:56:43.814304 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10454 22:56:43.820605 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10455 22:56:43.824130 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10456 22:56:43.831148 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10457 22:56:43.844311 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10458 22:56:43.857054 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10459 22:56:43.863663 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10460 22:56:43.871873 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10461 22:56:43.884796 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10462 22:56:43.891090 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10463 22:56:43.897974 <6>[ 0.009176] Console: colour dummy device 80x25
10464 22:56:43.907807 <6>[ 0.013899] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10465 22:56:43.914471 <6>[ 0.024341] pid_max: default: 32768 minimum: 301
10466 22:56:43.918502 <6>[ 0.029214] LSM: Security Framework initializing
10467 22:56:43.924896 <6>[ 0.034152] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10468 22:56:43.934652 <6>[ 0.041967] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10469 22:56:43.944597 <6>[ 0.051402] cblist_init_generic: Setting adjustable number of callback queues.
10470 22:56:43.948139 <6>[ 0.058903] cblist_init_generic: Setting shift to 3 and lim to 1.
10471 22:56:43.954497 <6>[ 0.065242] cblist_init_generic: Setting shift to 3 and lim to 1.
10472 22:56:43.960814 <6>[ 0.071648] rcu: Hierarchical SRCU implementation.
10473 22:56:43.967505 <6>[ 0.076662] rcu: Max phase no-delay instances is 1000.
10474 22:56:43.973833 <6>[ 0.083689] EFI services will not be available.
10475 22:56:43.977007 <6>[ 0.088687] smp: Bringing up secondary CPUs ...
10476 22:56:43.984813 <6>[ 0.093742] Detected VIPT I-cache on CPU1
10477 22:56:43.991507 <6>[ 0.093812] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10478 22:56:43.998501 <6>[ 0.093842] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10479 22:56:44.001645 <6>[ 0.094181] Detected VIPT I-cache on CPU2
10480 22:56:44.008499 <6>[ 0.094236] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10481 22:56:44.018028 <6>[ 0.094253] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10482 22:56:44.021196 <6>[ 0.094511] Detected VIPT I-cache on CPU3
10483 22:56:44.028203 <6>[ 0.094558] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10484 22:56:44.034383 <6>[ 0.094571] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10485 22:56:44.037852 <6>[ 0.094876] CPU features: detected: Spectre-v4
10486 22:56:44.044519 <6>[ 0.094882] CPU features: detected: Spectre-BHB
10487 22:56:44.047926 <6>[ 0.094888] Detected PIPT I-cache on CPU4
10488 22:56:44.054691 <6>[ 0.094945] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10489 22:56:44.061399 <6>[ 0.094961] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10490 22:56:44.067931 <6>[ 0.095255] Detected PIPT I-cache on CPU5
10491 22:56:44.074412 <6>[ 0.095318] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10492 22:56:44.081206 <6>[ 0.095334] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10493 22:56:44.084428 <6>[ 0.095618] Detected PIPT I-cache on CPU6
10494 22:56:44.091083 <6>[ 0.095682] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10495 22:56:44.097542 <6>[ 0.095698] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10496 22:56:44.103926 <6>[ 0.095998] Detected PIPT I-cache on CPU7
10497 22:56:44.110961 <6>[ 0.096063] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10498 22:56:44.117378 <6>[ 0.096079] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10499 22:56:44.121184 <6>[ 0.096127] smp: Brought up 1 node, 8 CPUs
10500 22:56:44.127286 <6>[ 0.237391] SMP: Total of 8 processors activated.
10501 22:56:44.130840 <6>[ 0.242343] CPU features: detected: 32-bit EL0 Support
10502 22:56:44.141022 <6>[ 0.247739] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10503 22:56:44.147273 <6>[ 0.256593] CPU features: detected: Common not Private translations
10504 22:56:44.153744 <6>[ 0.263069] CPU features: detected: CRC32 instructions
10505 22:56:44.157183 <6>[ 0.268421] CPU features: detected: RCpc load-acquire (LDAPR)
10506 22:56:44.164133 <6>[ 0.274380] CPU features: detected: LSE atomic instructions
10507 22:56:44.170316 <6>[ 0.280161] CPU features: detected: Privileged Access Never
10508 22:56:44.177197 <6>[ 0.285977] CPU features: detected: RAS Extension Support
10509 22:56:44.183755 <6>[ 0.291585] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10510 22:56:44.186985 <6>[ 0.298850] CPU: All CPU(s) started at EL2
10511 22:56:44.193790 <6>[ 0.303192] alternatives: applying system-wide alternatives
10512 22:56:44.202505 <6>[ 0.313893] devtmpfs: initialized
10513 22:56:44.215256 <6>[ 0.322827] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10514 22:56:44.224924 <6>[ 0.332791] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10515 22:56:44.231324 <6>[ 0.341019] pinctrl core: initialized pinctrl subsystem
10516 22:56:44.235001 <6>[ 0.347656] DMI not present or invalid.
10517 22:56:44.241116 <6>[ 0.352067] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10518 22:56:44.251321 <6>[ 0.358953] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10519 22:56:44.257705 <6>[ 0.366542] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10520 22:56:44.267792 <6>[ 0.374775] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10521 22:56:44.270884 <6>[ 0.383020] audit: initializing netlink subsys (disabled)
10522 22:56:44.281029 <5>[ 0.388716] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10523 22:56:44.287084 <6>[ 0.389382] thermal_sys: Registered thermal governor 'step_wise'
10524 22:56:44.293601 <6>[ 0.396684] thermal_sys: Registered thermal governor 'power_allocator'
10525 22:56:44.297402 <6>[ 0.402938] cpuidle: using governor menu
10526 22:56:44.303807 <6>[ 0.413902] NET: Registered PF_QIPCRTR protocol family
10527 22:56:44.310796 <6>[ 0.419383] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10528 22:56:44.317187 <6>[ 0.426487] ASID allocator initialised with 32768 entries
10529 22:56:44.320301 <6>[ 0.433048] Serial: AMBA PL011 UART driver
10530 22:56:44.330631 <4>[ 0.441643] Trying to register duplicate clock ID: 134
10531 22:56:44.386062 <6>[ 0.500878] KASLR enabled
10532 22:56:44.400483 <6>[ 0.508592] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10533 22:56:44.407155 <6>[ 0.515608] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10534 22:56:44.414226 <6>[ 0.522097] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10535 22:56:44.420416 <6>[ 0.529105] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10536 22:56:44.426905 <6>[ 0.535592] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10537 22:56:44.434090 <6>[ 0.542596] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10538 22:56:44.440381 <6>[ 0.549084] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10539 22:56:44.447010 <6>[ 0.556091] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10540 22:56:44.450476 <6>[ 0.563583] ACPI: Interpreter disabled.
10541 22:56:44.458796 <6>[ 0.569974] iommu: Default domain type: Translated
10542 22:56:44.465264 <6>[ 0.575139] iommu: DMA domain TLB invalidation policy: strict mode
10543 22:56:44.468355 <5>[ 0.581799] SCSI subsystem initialized
10544 22:56:44.475165 <6>[ 0.586040] usbcore: registered new interface driver usbfs
10545 22:56:44.481956 <6>[ 0.591774] usbcore: registered new interface driver hub
10546 22:56:44.484960 <6>[ 0.597327] usbcore: registered new device driver usb
10547 22:56:44.492446 <6>[ 0.603435] pps_core: LinuxPPS API ver. 1 registered
10548 22:56:44.502112 <6>[ 0.608631] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10549 22:56:44.505733 <6>[ 0.617978] PTP clock support registered
10550 22:56:44.508651 <6>[ 0.622219] EDAC MC: Ver: 3.0.0
10551 22:56:44.515890 <6>[ 0.627394] FPGA manager framework
10552 22:56:44.522498 <6>[ 0.631074] Advanced Linux Sound Architecture Driver Initialized.
10553 22:56:44.525872 <6>[ 0.637848] vgaarb: loaded
10554 22:56:44.532450 <6>[ 0.641003] clocksource: Switched to clocksource arch_sys_counter
10555 22:56:44.536246 <5>[ 0.647451] VFS: Disk quotas dquot_6.6.0
10556 22:56:44.542581 <6>[ 0.651633] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10557 22:56:44.545969 <6>[ 0.658825] pnp: PnP ACPI: disabled
10558 22:56:44.554240 <6>[ 0.665543] NET: Registered PF_INET protocol family
10559 22:56:44.563968 <6>[ 0.671135] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10560 22:56:44.575380 <6>[ 0.683451] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10561 22:56:44.585580 <6>[ 0.692267] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10562 22:56:44.591877 <6>[ 0.700239] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10563 22:56:44.601591 <6>[ 0.708939] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10564 22:56:44.608152 <6>[ 0.718678] TCP: Hash tables configured (established 65536 bind 65536)
10565 22:56:44.614638 <6>[ 0.725538] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10566 22:56:44.624732 <6>[ 0.732738] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10567 22:56:44.631174 <6>[ 0.740435] NET: Registered PF_UNIX/PF_LOCAL protocol family
10568 22:56:44.637947 <6>[ 0.746600] RPC: Registered named UNIX socket transport module.
10569 22:56:44.641273 <6>[ 0.752755] RPC: Registered udp transport module.
10570 22:56:44.647797 <6>[ 0.757690] RPC: Registered tcp transport module.
10571 22:56:44.654362 <6>[ 0.762622] RPC: Registered tcp NFSv4.1 backchannel transport module.
10572 22:56:44.657962 <6>[ 0.769290] PCI: CLS 0 bytes, default 64
10573 22:56:44.661152 <6>[ 0.773690] Unpacking initramfs...
10574 22:56:44.670808 <6>[ 0.777458] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10575 22:56:44.677872 <6>[ 0.786111] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10576 22:56:44.684325 <6>[ 0.794953] kvm [1]: IPA Size Limit: 40 bits
10577 22:56:44.687386 <6>[ 0.799483] kvm [1]: GICv3: no GICV resource entry
10578 22:56:44.694342 <6>[ 0.804504] kvm [1]: disabling GICv2 emulation
10579 22:56:44.700554 <6>[ 0.809196] kvm [1]: GIC system register CPU interface enabled
10580 22:56:44.704129 <6>[ 0.815366] kvm [1]: vgic interrupt IRQ18
10581 22:56:44.707424 <6>[ 0.819724] kvm [1]: VHE mode initialized successfully
10582 22:56:44.714924 <5>[ 0.826139] Initialise system trusted keyrings
10583 22:56:44.721479 <6>[ 0.830936] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10584 22:56:44.730006 <6>[ 0.841272] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10585 22:56:44.736528 <5>[ 0.847649] NFS: Registering the id_resolver key type
10586 22:56:44.740091 <5>[ 0.852955] Key type id_resolver registered
10587 22:56:44.746440 <5>[ 0.857369] Key type id_legacy registered
10588 22:56:44.752951 <6>[ 0.861673] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10589 22:56:44.759409 <6>[ 0.868596] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10590 22:56:44.766063 <6>[ 0.876331] 9p: Installing v9fs 9p2000 file system support
10591 22:56:44.802512 <5>[ 0.913672] Key type asymmetric registered
10592 22:56:44.805842 <5>[ 0.918009] Asymmetric key parser 'x509' registered
10593 22:56:44.815478 <6>[ 0.923155] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10594 22:56:44.818853 <6>[ 0.930777] io scheduler mq-deadline registered
10595 22:56:44.822236 <6>[ 0.935541] io scheduler kyber registered
10596 22:56:44.841101 <6>[ 0.952426] EINJ: ACPI disabled.
10597 22:56:44.873534 <4>[ 0.977929] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10598 22:56:44.883212 <4>[ 0.988556] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10599 22:56:44.898174 <6>[ 1.009463] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10600 22:56:44.906140 <6>[ 1.017512] printk: console [ttyS0] disabled
10601 22:56:44.934485 <6>[ 1.042161] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10602 22:56:44.940894 <6>[ 1.051639] printk: console [ttyS0] enabled
10603 22:56:44.943992 <6>[ 1.051639] printk: console [ttyS0] enabled
10604 22:56:44.950612 <6>[ 1.060534] printk: bootconsole [mtk8250] disabled
10605 22:56:44.954422 <6>[ 1.060534] printk: bootconsole [mtk8250] disabled
10606 22:56:44.960711 <6>[ 1.071753] SuperH (H)SCI(F) driver initialized
10607 22:56:44.963831 <6>[ 1.077048] msm_serial: driver initialized
10608 22:56:44.978038 <6>[ 1.086007] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10609 22:56:44.988201 <6>[ 1.094555] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10610 22:56:44.994569 <6>[ 1.103098] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10611 22:56:45.004283 <6>[ 1.111728] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10612 22:56:45.014220 <6>[ 1.120434] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10613 22:56:45.020984 <6>[ 1.129153] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10614 22:56:45.031040 <6>[ 1.137694] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10615 22:56:45.037199 <6>[ 1.146504] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10616 22:56:45.046987 <6>[ 1.155048] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10617 22:56:45.059250 <6>[ 1.170608] loop: module loaded
10618 22:56:45.066118 <6>[ 1.176592] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10619 22:56:45.088541 <4>[ 1.199861] mtk-pmic-keys: Failed to locate of_node [id: -1]
10620 22:56:45.095087 <6>[ 1.206557] megasas: 07.719.03.00-rc1
10621 22:56:45.104670 <6>[ 1.216075] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10622 22:56:45.116403 <6>[ 1.224387] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10623 22:56:45.129232 <6>[ 1.240299] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10624 22:56:45.189086 <6>[ 1.293525] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10625 22:56:47.057338 <6>[ 3.168707] Freeing initrd memory: 55068K
10626 22:56:47.067564 <6>[ 3.178986] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10627 22:56:47.078397 <6>[ 3.189872] tun: Universal TUN/TAP device driver, 1.6
10628 22:56:47.081597 <6>[ 3.195936] thunder_xcv, ver 1.0
10629 22:56:47.085068 <6>[ 3.199443] thunder_bgx, ver 1.0
10630 22:56:47.088230 <6>[ 3.202938] nicpf, ver 1.0
10631 22:56:47.098694 <6>[ 3.206945] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10632 22:56:47.102303 <6>[ 3.214421] hns3: Copyright (c) 2017 Huawei Corporation.
10633 22:56:47.108748 <6>[ 3.220008] hclge is initializing
10634 22:56:47.112132 <6>[ 3.223589] e1000: Intel(R) PRO/1000 Network Driver
10635 22:56:47.118870 <6>[ 3.228717] e1000: Copyright (c) 1999-2006 Intel Corporation.
10636 22:56:47.121973 <6>[ 3.234730] e1000e: Intel(R) PRO/1000 Network Driver
10637 22:56:47.128431 <6>[ 3.239945] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10638 22:56:47.135225 <6>[ 3.246129] igb: Intel(R) Gigabit Ethernet Network Driver
10639 22:56:47.141710 <6>[ 3.251779] igb: Copyright (c) 2007-2014 Intel Corporation.
10640 22:56:47.148321 <6>[ 3.257617] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10641 22:56:47.154963 <6>[ 3.264135] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10642 22:56:47.158358 <6>[ 3.270592] sky2: driver version 1.30
10643 22:56:47.164687 <6>[ 3.275569] VFIO - User Level meta-driver version: 0.3
10644 22:56:47.172643 <6>[ 3.283779] usbcore: registered new interface driver usb-storage
10645 22:56:47.178988 <6>[ 3.290227] usbcore: registered new device driver onboard-usb-hub
10646 22:56:47.187771 <6>[ 3.299299] mt6397-rtc mt6359-rtc: registered as rtc0
10647 22:56:47.197621 <6>[ 3.304765] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T22:56:44 UTC (1686005804)
10648 22:56:47.201305 <6>[ 3.314328] i2c_dev: i2c /dev entries driver
10649 22:56:47.217767 <6>[ 3.326003] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10650 22:56:47.224545 <6>[ 3.336205] sdhci: Secure Digital Host Controller Interface driver
10651 22:56:47.231286 <6>[ 3.342644] sdhci: Copyright(c) Pierre Ossman
10652 22:56:47.237737 <6>[ 3.348044] Synopsys Designware Multimedia Card Interface Driver
10653 22:56:47.241109 <6>[ 3.354668] mmc0: CQHCI version 5.10
10654 22:56:47.247688 <6>[ 3.355199] sdhci-pltfm: SDHCI platform and OF driver helper
10655 22:56:47.255437 <6>[ 3.366535] ledtrig-cpu: registered to indicate activity on CPUs
10656 22:56:47.265503 <6>[ 3.373882] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10657 22:56:47.269402 <6>[ 3.381291] usbcore: registered new interface driver usbhid
10658 22:56:47.275730 <6>[ 3.387120] usbhid: USB HID core driver
10659 22:56:47.282110 <6>[ 3.391359] spi_master spi0: will run message pump with realtime priority
10660 22:56:47.329705 <6>[ 3.434774] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10661 22:56:47.349541 <6>[ 3.450416] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10662 22:56:47.352525 <6>[ 3.463986] mmc0: Command Queue Engine enabled
10663 22:56:47.359544 <6>[ 3.466517] cros-ec-spi spi0.0: Chrome EC device registered
10664 22:56:47.366304 <6>[ 3.468726] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10665 22:56:47.369746 <6>[ 3.482030] mmcblk0: mmc0:0001 DA4128 116 GiB
10666 22:56:47.384524 <6>[ 3.492653] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10667 22:56:47.391369 <6>[ 3.494089] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10668 22:56:47.397957 <6>[ 3.504126] NET: Registered PF_PACKET protocol family
10669 22:56:47.401011 <6>[ 3.508940] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10670 22:56:47.407507 <6>[ 3.513309] 9pnet: Installing 9P2000 support
10671 22:56:47.410884 <6>[ 3.519100] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10672 22:56:47.417467 <5>[ 3.522967] Key type dns_resolver registered
10673 22:56:47.423966 <6>[ 3.528837] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10674 22:56:47.427191 <6>[ 3.533231] registered taskstats version 1
10675 22:56:47.430743 <5>[ 3.543594] Loading compiled-in X.509 certificates
10676 22:56:47.465718 <4>[ 3.570773] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10677 22:56:47.475688 <4>[ 3.581487] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10678 22:56:47.486012 <3>[ 3.594527] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10679 22:56:47.498740 <6>[ 3.610152] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10680 22:56:47.505459 <6>[ 3.616976] xhci-mtk 11200000.usb: xHCI Host Controller
10681 22:56:47.511996 <6>[ 3.622478] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10682 22:56:47.522078 <6>[ 3.630327] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10683 22:56:47.528627 <6>[ 3.639756] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10684 22:56:47.535320 <6>[ 3.645927] xhci-mtk 11200000.usb: xHCI Host Controller
10685 22:56:47.541927 <6>[ 3.651424] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10686 22:56:47.548457 <6>[ 3.659085] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10687 22:56:47.555559 <6>[ 3.666975] hub 1-0:1.0: USB hub found
10688 22:56:47.558835 <6>[ 3.671008] hub 1-0:1.0: 1 port detected
10689 22:56:47.568727 <6>[ 3.675355] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10690 22:56:47.572120 <6>[ 3.683972] hub 2-0:1.0: USB hub found
10691 22:56:47.575560 <6>[ 3.687990] hub 2-0:1.0: 1 port detected
10692 22:56:47.583416 <6>[ 3.695105] mtk-msdc 11f70000.mmc: Got CD GPIO
10693 22:56:47.600789 <6>[ 3.708950] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10694 22:56:47.607449 <6>[ 3.716974] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10695 22:56:47.617222 <4>[ 3.724944] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10696 22:56:47.626941 <6>[ 3.734597] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10697 22:56:47.634256 <6>[ 3.742678] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10698 22:56:47.640429 <6>[ 3.750710] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10699 22:56:47.650411 <6>[ 3.758630] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10700 22:56:47.657108 <6>[ 3.766452] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10701 22:56:47.666980 <6>[ 3.774277] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10702 22:56:47.677044 <6>[ 3.784952] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10703 22:56:47.686862 <6>[ 3.793325] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10704 22:56:47.693192 <6>[ 3.801679] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10705 22:56:47.703000 <6>[ 3.810024] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10706 22:56:47.709813 <6>[ 3.818367] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10707 22:56:47.719970 <6>[ 3.826709] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10708 22:56:47.726323 <6>[ 3.835053] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10709 22:56:47.735985 <6>[ 3.843396] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10710 22:56:47.743131 <6>[ 3.851739] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10711 22:56:47.753068 <6>[ 3.860082] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10712 22:56:47.759365 <6>[ 3.868425] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10713 22:56:47.769029 <6>[ 3.876769] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10714 22:56:47.775772 <6>[ 3.885113] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10715 22:56:47.785452 <6>[ 3.893456] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10716 22:56:47.792045 <6>[ 3.901803] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10717 22:56:47.798833 <6>[ 3.910720] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10718 22:56:47.806458 <6>[ 3.918211] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10719 22:56:47.813690 <6>[ 3.925298] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10720 22:56:47.824114 <6>[ 3.932460] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10721 22:56:47.830503 <6>[ 3.939810] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10722 22:56:47.840672 <6>[ 3.946784] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10723 22:56:47.847119 <6>[ 3.955938] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10724 22:56:47.856972 <6>[ 3.965064] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10725 22:56:47.867246 <6>[ 3.974367] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10726 22:56:47.876711 <6>[ 3.983841] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10727 22:56:47.887207 <6>[ 3.993322] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10728 22:56:47.897003 <6>[ 4.002451] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10729 22:56:47.903385 <6>[ 4.011925] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10730 22:56:47.913546 <6>[ 4.021052] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10731 22:56:47.923275 <6>[ 4.030369] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10732 22:56:47.933135 <6>[ 4.040536] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10733 22:56:47.943426 <6>[ 4.052018] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10734 22:56:47.965112 <6>[ 4.073413] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10735 22:56:47.993672 <6>[ 4.105472] hub 2-1:1.0: USB hub found
10736 22:56:47.997095 <6>[ 4.109977] hub 2-1:1.0: 3 ports detected
10737 22:56:48.116964 <6>[ 4.225254] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10738 22:56:48.269904 <6>[ 4.381540] hub 1-1:1.0: USB hub found
10739 22:56:48.273296 <6>[ 4.385895] hub 1-1:1.0: 4 ports detected
10740 22:56:48.348747 <6>[ 4.457515] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10741 22:56:48.593214 <6>[ 4.701281] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10742 22:56:48.726399 <6>[ 4.837538] hub 1-1.4:1.0: USB hub found
10743 22:56:48.729912 <6>[ 4.842237] hub 1-1.4:1.0: 2 ports detected
10744 22:56:49.025628 <6>[ 5.133289] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10745 22:56:49.217286 <6>[ 5.325272] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10746 22:57:00.221660 <6>[ 16.337848] ALSA device list:
10747 22:57:00.227974 <6>[ 16.341106] No soundcards found.
10748 22:57:00.240727 <6>[ 16.353490] Freeing unused kernel memory: 8384K
10749 22:57:00.243644 <6>[ 16.358421] Run /init as init process
10750 22:57:00.274003 <6>[ 16.387137] NET: Registered PF_INET6 protocol family
10751 22:57:00.281175 <6>[ 16.393602] Segment Routing with IPv6
10752 22:57:00.284283 <6>[ 16.397566] In-situ OAM (IOAM) with IPv6
10753 22:57:00.318797 <30>[ 16.411997] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10754 22:57:00.322084 <30>[ 16.435856] systemd[1]: Detected architecture arm64.
10755 22:57:00.322172
10756 22:57:00.328664 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10757 22:57:00.328748
10758 22:57:00.344341 <30>[ 16.457376] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10759 22:57:00.503297 <30>[ 16.613167] systemd[1]: Queued start job for default target Graphical Interface.
10760 22:57:00.537650 <30>[ 16.650577] systemd[1]: Created slice system-getty.slice.
10761 22:57:00.544312 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10762 22:57:00.560949 <30>[ 16.673840] systemd[1]: Created slice system-modprobe.slice.
10763 22:57:00.567326 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10764 22:57:00.585238 <30>[ 16.698419] systemd[1]: Created slice system-serial\x2dgetty.slice.
10765 22:57:00.595521 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10766 22:57:00.608695 <30>[ 16.721749] systemd[1]: Created slice User and Session Slice.
10767 22:57:00.615093 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10768 22:57:00.635904 <30>[ 16.745508] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10769 22:57:00.645563 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10770 22:57:00.659645 <30>[ 16.769408] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10771 22:57:00.666197 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10772 22:57:00.686791 <30>[ 16.793357] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10773 22:57:00.693728 <30>[ 16.805373] systemd[1]: Reached target Local Encrypted Volumes.
10774 22:57:00.700188 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10775 22:57:00.716792 <30>[ 16.829603] systemd[1]: Reached target Paths.
10776 22:57:00.719978 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10777 22:57:00.736456 <30>[ 16.849262] systemd[1]: Reached target Remote File Systems.
10778 22:57:00.742810 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10779 22:57:00.756346 <30>[ 16.869276] systemd[1]: Reached target Slices.
10780 22:57:00.759683 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10781 22:57:00.776030 <30>[ 16.889325] systemd[1]: Reached target Swap.
10782 22:57:00.779734 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10783 22:57:00.799616 <30>[ 16.909544] systemd[1]: Listening on initctl Compatibility Named Pipe.
10784 22:57:00.806179 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10785 22:57:00.813058 <30>[ 16.924213] systemd[1]: Listening on Journal Audit Socket.
10786 22:57:00.822297 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10787 22:57:00.832248 <30>[ 16.945538] systemd[1]: Listening on Journal Socket (/dev/log).
10788 22:57:00.838822 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10789 22:57:00.856440 <30>[ 16.969558] systemd[1]: Listening on Journal Socket.
10790 22:57:00.862953 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10791 22:57:00.876552 <30>[ 16.989594] systemd[1]: Listening on udev Control Socket.
10792 22:57:00.882966 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10793 22:57:00.900689 <30>[ 17.013974] systemd[1]: Listening on udev Kernel Socket.
10794 22:57:00.907460 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10795 22:57:00.956079 <30>[ 17.069428] systemd[1]: Mounting Huge Pages File System...
10796 22:57:00.962873 Mounting [0;1;39mHuge Pages File System[0m...
10797 22:57:00.978000 <30>[ 17.091155] systemd[1]: Mounting POSIX Message Queue File System...
10798 22:57:00.984532 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10799 22:57:01.032471 <30>[ 17.145450] systemd[1]: Mounting Kernel Debug File System...
10800 22:57:01.038956 Mounting [0;1;39mKernel Debug File System[0m...
10801 22:57:01.055430 <30>[ 17.165497] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10802 22:57:01.066442 <30>[ 17.176269] systemd[1]: Starting Create list of static device nodes for the current kernel...
10803 22:57:01.073007 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10804 22:57:01.090240 <30>[ 17.203364] systemd[1]: Starting Load Kernel Module configfs...
10805 22:57:01.096929 Starting [0;1;39mLoad Kernel Module configfs[0m...
10806 22:57:01.114129 <30>[ 17.227330] systemd[1]: Starting Load Kernel Module drm...
10807 22:57:01.120969 Starting [0;1;39mLoad Kernel Module drm[0m...
10808 22:57:01.139621 <30>[ 17.249425] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10809 22:57:01.149850 <30>[ 17.262991] systemd[1]: Starting Journal Service...
10810 22:57:01.152985 Starting [0;1;39mJournal Service[0m...
10811 22:57:01.171027 <30>[ 17.283884] systemd[1]: Starting Load Kernel Modules...
10812 22:57:01.177240 Starting [0;1;39mLoad Kernel Modules[0m...
10813 22:57:01.197969 <30>[ 17.307961] systemd[1]: Starting Remount Root and Kernel File Systems...
10814 22:57:01.204514 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10815 22:57:01.222537 <30>[ 17.335866] systemd[1]: Starting Coldplug All udev Devices...
10816 22:57:01.228962 Starting [0;1;39mColdplug All udev Devices[0m...
10817 22:57:01.247139 <30>[ 17.360312] systemd[1]: Mounted Huge Pages File System.
10818 22:57:01.253670 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10819 22:57:01.268529 <30>[ 17.381758] systemd[1]: Started Journal Service.
10820 22:57:01.275147 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10821 22:57:01.289651 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10822 22:57:01.304649 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10823 22:57:01.324527 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10824 22:57:01.343035 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10825 22:57:01.361657 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10826 22:57:01.377924 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10827 22:57:01.397005 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10828 22:57:01.416242 See 'systemctl status systemd-remount-fs.service' for details.
10829 22:57:01.476546 Mounting [0;1;39mKernel Configuration File System[0m...
10830 22:57:01.494688 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10831 22:57:01.512627 <46>[ 17.622554] systemd-journald[179]: Received client request to flush runtime journal.
10832 22:57:01.521068 Starting [0;1;39mLoad/Save Random Seed[0m...
10833 22:57:01.539363 Starting [0;1;39mApply Kernel Variables[0m...
10834 22:57:01.555415 Starting [0;1;39mCreate System Users[0m...
10835 22:57:01.576639 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10836 22:57:01.596643 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10837 22:57:01.609412 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10838 22:57:01.625584 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10839 22:57:01.641058 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10840 22:57:01.660957 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10841 22:57:01.713347 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10842 22:57:01.735078 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10843 22:57:01.752654 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10844 22:57:01.772080 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10845 22:57:01.820321 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10846 22:57:01.843785 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10847 22:57:01.861362 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10848 22:57:01.881076 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10849 22:57:01.925173 Starting [0;1;39mNetwork Time Synchronization[0m...
10850 22:57:01.944913 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10851 22:57:01.975868 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10852 22:57:02.042959 [[0;32m OK [0m] Created slic<6>[ 18.151991] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10853 22:57:02.046081 e [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10854 22:57:02.056281 <6>[ 18.169306] remoteproc remoteproc0: scp is available
10855 22:57:02.068282 <4>[ 18.178069] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10856 22:57:02.076432 <6>[ 18.189650] remoteproc remoteproc0: powering up scp
10857 22:57:02.086245 <4>[ 18.195047] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10858 22:57:02.092989 <3>[ 18.204886] remoteproc remoteproc0: request_firmware failed: -2
10859 22:57:02.099740 <3>[ 18.209536] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10860 22:57:02.110097 Startin<3>[ 18.219795] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10861 22:57:02.119940 g [0;1;39mLoad/<3>[ 18.229458] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10862 22:57:02.132672 Save Screen …of leds:white:kbd<3>[ 18.241297] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10863 22:57:02.139296 _backlight[0m..<6>[ 18.248052] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10864 22:57:02.139452 .
10865 22:57:02.149283 <3>[ 18.249597] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10866 22:57:02.155750 <6>[ 18.258591] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10867 22:57:02.166052 <3>[ 18.267051] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10868 22:57:02.175797 <6>[ 18.275560] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10869 22:57:02.182353 <3>[ 18.283658] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10870 22:57:02.188738 <3>[ 18.283667] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10871 22:57:02.198993 <3>[ 18.305708] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10872 22:57:02.212135 [[0;32m OK [0m] Started [0;1;39mNetwork Tim<3>[ 18.320467] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10873 22:57:02.218712 e Synchronizatio<4>[ 18.327450] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10874 22:57:02.222022 n[0m.
10875 22:57:02.228804 <3>[ 18.331796] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10876 22:57:02.238364 <3>[ 18.347162] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10877 22:57:02.245007 <4>[ 18.351191] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10878 22:57:02.251996 <6>[ 18.356756] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10879 22:57:02.261771 <3>[ 18.366575] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10880 22:57:02.268086 <3>[ 18.378441] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10881 22:57:02.278010 <3>[ 18.378461] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10882 22:57:02.284687 <3>[ 18.378473] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10883 22:57:02.291324 <3>[ 18.378483] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10884 22:57:02.301114 [[0;32m OK [<6>[ 18.387090] usbcore: registered new interface driver r8152
10885 22:57:02.307998 0m] Finished [0<3>[ 18.392730] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10886 22:57:02.317932 ;1;39mLoad/Save <4>[ 18.399645] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10887 22:57:02.324471 <4>[ 18.399645] Fallback method does not support PEC.
10888 22:57:02.330737 Screen …s of l<6>[ 18.402910] mc: Linux media interface: v0.10
10889 22:57:02.340732 eds:white:kbd_ba<6>[ 18.421433] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10890 22:57:02.344309 cklight[0m.
10891 22:57:02.351454 <3>[ 18.461291] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10892 22:57:02.354982 <6>[ 18.463507] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10893 22:57:02.364665 <6>[ 18.466018] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10894 22:57:02.374602 <3>[ 18.472176] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10895 22:57:02.381011 <6>[ 18.474657] pci_bus 0000:00: root bus resource [bus 00-ff]
10896 22:57:02.387833 <6>[ 18.498203] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10897 22:57:02.394133 <6>[ 18.503579] videodev: Linux video capture interface: v2.00
10898 22:57:02.404163 <6>[ 18.505339] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10899 22:57:02.407803 <6>[ 18.505428] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10900 22:57:02.418157 [[0;32m OK [<6>[ 18.525367] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10901 22:57:02.424905 <6>[ 18.527322] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10902 22:57:02.434918 0m] Found device<3>[ 18.537329] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10903 22:57:02.444613 [0;1;39m/dev/t<3>[ 18.537998] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10904 22:57:02.444827 tyS0[0m.
10905 22:57:02.451113 <6>[ 18.544223] pci 0000:00:00.0: supports D1 D2
10906 22:57:02.458280 <6>[ 18.568090] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10907 22:57:02.464751 <3>[ 18.568439] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10908 22:57:02.471833 <4>[ 18.571831] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10909 22:57:02.481589 <4>[ 18.571840] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10910 22:57:02.488336 <6>[ 18.576926] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10911 22:57:02.498216 <3>[ 18.589635] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10912 22:57:02.501827 <6>[ 18.591409] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10913 22:57:02.511754 <3>[ 18.620518] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10914 22:57:02.515060 <6>[ 18.621052] r8152 2-1.3:1.0 eth0: v1.12.13
10915 22:57:02.525285 <6>[ 18.621953] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10916 22:57:02.532077 <6>[ 18.642528] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10917 22:57:02.538889 <6>[ 18.650017] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10918 22:57:02.548705 <3>[ 18.654952] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10919 22:57:02.551970 <6>[ 18.657606] pci 0000:01:00.0: supports D1 D2
10920 22:57:02.558544 <6>[ 18.670804] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10921 22:57:02.568718 <3>[ 18.681282] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10922 22:57:02.578562 <3>[ 18.686958] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 22:57:02.584933 <3>[ 18.688053] elants_i2c 4-0010: (read fw id) unexpected response: ff ff
10924 22:57:02.591461 <6>[ 18.696751] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10925 22:57:02.601868 <6>[ 18.703399] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10926 22:57:02.608855 <6>[ 18.710172] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10927 22:57:02.618912 <3>[ 18.719231] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10928 22:57:02.625479 <6>[ 18.736355] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10929 22:57:02.635308 <6>[ 18.736388] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10930 22:57:02.638694 <6>[ 18.745599] Bluetooth: Core ver 2.22
10931 22:57:02.645203 <6>[ 18.745616] usbcore: registered new interface driver cdc_ether
10932 22:57:02.652243 [[0;32m OK [<6>[ 18.752402] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10933 22:57:02.658768 0m] Reached targ<6>[ 18.756295] NET: Registered PF_BLUETOOTH protocol family
10934 22:57:02.668943 et [0;1;39mSyst<6>[ 18.756446] usbcore: registered new interface driver r8153_ecm
10935 22:57:02.678879 em Initializatio<6>[ 18.762321] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10936 22:57:02.679071 n[0m.
10937 22:57:02.685869 <6>[ 18.768706] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10938 22:57:02.692245 <6>[ 18.771705] Bluetooth: HCI device and connection manager initialized
10939 22:57:02.698561 <3>[ 18.778431] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10940 22:57:02.705488 <6>[ 18.778650] pci 0000:00:00.0: PCI bridge to [bus 01]
10941 22:57:02.709030 <6>[ 18.786129] Bluetooth: HCI socket layer initialized
10942 22:57:02.716111 <6>[ 18.787349] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10943 22:57:02.729700 <6>[ 18.788660] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10944 22:57:02.737335 <6>[ 18.788818] usbcore: registered new interface driver uvcvideo
10945 22:57:02.743692 <6>[ 18.795486] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10946 22:57:02.746947 <6>[ 18.802270] Bluetooth: L2CAP socket layer initialized
10947 22:57:02.753817 <6>[ 18.809097] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10948 22:57:02.761202 <6>[ 18.817839] Bluetooth: SCO socket layer initialized
10949 22:57:02.767754 <6>[ 18.818551] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10950 22:57:02.770871 <6>[ 18.822544] remoteproc remoteproc0: powering up scp
10951 22:57:02.781260 <4>[ 18.822591] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10952 22:57:02.788158 <3>[ 18.822599] remoteproc remoteproc0: request_firmware failed: -2
10953 22:57:02.795176 <3>[ 18.822602] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10954 22:57:02.801285 <6>[ 18.824052] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10955 22:57:02.811105 <3>[ 18.839182] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10956 22:57:02.814441 <6>[ 18.848109] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10957 22:57:02.821384 <6>[ 18.867584] usbcore: registered new interface driver btusb
10958 22:57:02.831219 <4>[ 18.868101] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10959 22:57:02.837636 <3>[ 18.868112] Bluetooth: hci0: Failed to load firmware file (-2)
10960 22:57:02.844018 <3>[ 18.868115] Bluetooth: hci0: Failed to set up firmware (-2)
10961 22:57:02.854260 <4>[ 18.868119] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10962 22:57:02.863975 <5>[ 18.893145] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10963 22:57:02.870967 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10964 22:57:02.882766 <5>[ 18.993045] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10965 22:57:02.889390 <4>[ 19.000126] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10966 22:57:02.895948 <6>[ 19.009048] cfg80211: failed to load regulatory.db
10967 22:57:02.902688 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10968 22:57:02.916519 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10969 22:57:02.936373 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10970 22:57:02.943050 <6>[ 19.053349] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10971 22:57:02.949478 <6>[ 19.060861] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10972 22:57:02.953341 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10973 22:57:02.971455 [[0;32m OK [0m] Listening on [0;1;39mD-Bus <6>[ 19.085384] mt7921e 0000:01:00.0: ASIC revision: 79610010
10974 22:57:02.974804 System Message Bus Socket[0m.
10975 22:57:02.992245 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10976 22:57:03.007934 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10977 22:57:03.027487 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10978 22:57:03.078214 <4>[ 19.185100] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10979 22:57:03.100701 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10980 22:57:03.126905 Starting [0;1;39mUser Login Management[0m...
10981 22:57:03.142758 Starting [0;1;39mPermit User Sessions[0m...
10982 22:57:03.163542 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10983 22:57:03.176350 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10984 22:57:03.212314 [[0;32m OK [0m] Started [0;<4>[ 19.318150] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10985 22:57:03.212473 1;39mGetty on tty1[0m.
10986 22:57:03.240509 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10987 22:57:03.260066 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10988 22:57:03.296433 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10989 22:57:03.313011 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10990 22:57:03.336785 [[0;32m OK [<4>[ 19.443839] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10991 22:57:03.343310 0m] Started [0;1;39mUser Login Management[0m.
10992 22:57:03.358901 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10993 22:57:03.375905 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10994 22:57:03.440969 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10995 22:57:03.457766 <4>[ 19.564813] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10996 22:57:03.483032 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10997 22:57:03.536136
10998 22:57:03.536359
10999 22:57:03.539321 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11000 22:57:03.539456
11001 22:57:03.542785 debian-bullseye-arm64 login: root (automatic login)
11002 22:57:03.542918
11003 22:57:03.543041
11004 22:57:03.559831 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 22:41:02 UTC 2023 aarch64
11005 22:57:03.559946
11006 22:57:03.566852 The programs included with the Debian GNU/Linux system are free software;
11007 22:57:03.579937 the exact distribution term<4>[ 19.685800] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11008 22:57:03.582843 s for each program are described in the
11009 22:57:03.586426 individual files in /usr/share/doc/*/copyright.
11010 22:57:03.590087
11011 22:57:03.592990 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11012 22:57:03.596033 permitted by applicable law.
11013 22:57:03.596516 Matched prompt #10: / #
11015 22:57:03.596867 Setting prompt string to ['/ #']
11016 22:57:03.596993 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11018 22:57:03.597293 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11019 22:57:03.597412 start: 2.2.6 expect-shell-connection (timeout 00:03:21) [common]
11020 22:57:03.597512 Setting prompt string to ['/ #']
11021 22:57:03.597602 Forcing a shell prompt, looking for ['/ #']
11023 22:57:03.647864 / #
11024 22:57:03.648115 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11025 22:57:03.648271 Waiting using forced prompt support (timeout 00:02:30)
11026 22:57:03.652923
11027 22:57:03.653285 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11028 22:57:03.653457 start: 2.2.7 export-device-env (timeout 00:03:21) [common]
11029 22:57:03.653631 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11030 22:57:03.653789 end: 2.2 depthcharge-retry (duration 00:01:39) [common]
11031 22:57:03.653949 end: 2 depthcharge-action (duration 00:01:39) [common]
11032 22:57:03.654103 start: 3 lava-test-retry (timeout 00:07:59) [common]
11033 22:57:03.654263 start: 3.1 lava-test-shell (timeout 00:07:59) [common]
11034 22:57:03.654398 Using namespace: common
11036 22:57:03.754859 / # #
11037 22:57:03.755048 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11038 22:57:03.755204 <4>[ 19.807503] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11039 22:57:03.759563 #
11040 22:57:03.759833 Using /lava-10597637
11042 22:57:03.860167 / # export SHELL=/bin/sh
11043 22:57:03.860480 <4>[ 19.927552] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11044 22:57:03.865737 export SHELL=/bin/sh
11046 22:57:03.966315 / # . /lava-10597637/environment
11047 22:57:03.966531 . /lava-10597637/environment<4>[ 20.047856] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11048 22:57:03.971076
11050 22:57:04.071640 / # /lava-10597637/bin/lava-test-runner /lava-10597637/0
11051 22:57:04.071813 Test shell timeout: 10s (minimum of the action and connection timeout)
11052 22:57:04.072149 /lava-10597637/bin/lava-test-runner /lava-10597637/0<4>[ 20.167298] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11053 22:57:04.076888
11054 22:57:04.120946 + export TESTRUN_ID=0_igt-gpu-panf<8>[ 20.214579] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 10597637_1.5.2.3.1>
11055 22:57:04.121140 rost
11056 22:57:04.121215 + cd /lava-10597637/0/tests/0_igt-gpu-panfrost
11057 22:57:04.121281 + cat uuid
11058 22:57:04.121347 + UUID=10597637_1.5.2.3.1
11059 22:57:04.121437 + set +x
11060 22:57:04.121682 Received signal: <STARTRUN> 0_igt-gpu-panfrost 10597637_1.5.2.3.1
11061 22:57:04.121750 Starting test lava.0_igt-gpu-panfrost (10597637_1.5.2.3.1)
11062 22:57:04.121833 Skipping test definition patterns.
11063 22:57:04.122210 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime panfrost_submit
11064 22:57:04.131787 <8>[ 20.244959] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
11065 22:57:04.132063 Received signal: <TESTSET> START panfrost_gem_new
11066 22:57:04.132147 Starting test_set panfrost_gem_new
11067 22:57:04.153802 <14>[ 20.267508] [IGT] panfrost_gem_new: executing
11068 22:57:04.160631 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11069 22:57:04.164117 <14>[ 20.278085] [IGT] panfrost_gem_new: exiting, ret=77
11070 22:57:04.180657 Test requirement not met in function drm_open_driver, file ../li<4>[ 20.288767] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11071 22:57:04.190176 b/drmtest.c:621:<8>[ 20.292433] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
11072 22:57:04.190288
11073 22:57:04.190534 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
11075 22:57:04.193699 Test requirement: !(fd<0)
11076 22:57:04.196896 No known gpu found for chipset flags 0x32 (panfrost)
11077 22:57:04.200026 Last errno: 2, No such file or directory
11078 22:57:04.206946 [1mSubtest gem-new-4096: SKIP (0.000s)[0m
11079 22:57:04.218361 <14>[ 20.331868] [IGT] panfrost_gem_new: executing
11080 22:57:04.228140 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.339926] [IGT] panfrost_gem_new: exiting, ret=77
11081 22:57:04.228296 .1.31 aarch64)
11082 22:57:04.241304 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.352358] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
11083 22:57:04.241437 b/drmtest.c:621:
11084 22:57:04.241689 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
11086 22:57:04.244937 Test requirement: !(fd<0)
11087 22:57:04.251789 No known gpu found for chipset flags 0x32 (panfrost)
11088 22:57:04.254723 Last errno: 2, No such file or directory
11089 22:57:04.258043 [1mSubtest gem-new-0: SKIP (0.000s)[0m
11090 22:57:04.264655 <14>[ 20.377913] [IGT] panfrost_gem_new: executing
11091 22:57:04.274733 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.386227] [IGT] panfrost_gem_new: exiting, ret=77
11092 22:57:04.274862 .1.31 aarch64)
11093 22:57:04.287774 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:<8>[ 20.399397] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
11094 22:57:04.288066 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
11096 22:57:04.290935
11097 22:57:04.291025 Test requirement: !(fd<0)
11098 22:57:04.297375 No <3>[ 20.410217] mt7921e 0000:01:00.0: hardware init failed
11099 22:57:04.300922 <8>[ 20.411151] <LAVA_SIGNAL_TESTSET STOP>
11100 22:57:04.301188 Received signal: <TESTSET> STOP
11101 22:57:04.301274 Closing test_set panfrost_gem_new
11102 22:57:04.307454 known gpu found for chipset flags 0x32 (panfrost)
11103 22:57:04.310867 Last errno: 2, No such file or directory
11104 22:57:04.314206 [1mSubtest gem-new-zeroed: SKIP (0.000s)[0m
11105 22:57:04.327011 <8>[ 20.440785] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
11106 22:57:04.327300 Received signal: <TESTSET> START panfrost_get_param
11107 22:57:04.327384 Starting test_set panfrost_get_param
11108 22:57:04.350101 <14>[ 20.463602] [IGT] panfrost_get_param: executing
11109 22:57:04.359854 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.471850] [IGT] panfrost_get_param: exiting, ret=77
11110 22:57:04.359964 .1.31 aarch64)
11111 22:57:04.373133 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.484584] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
11112 22:57:04.373426 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
11114 22:57:04.376423 b/drmtest.c:621:
11115 22:57:04.376513 Test requirement: !(fd<0)
11116 22:57:04.382814 No known gpu found for chipset flags 0x32 (panfrost)
11117 22:57:04.386384 Last errno: 2, No such file or directory
11118 22:57:04.389391 [1mSubtest base-params: SKIP (0.000s)[0m
11119 22:57:04.397002 <14>[ 20.510344] [IGT] panfrost_get_param: executing
11120 22:57:04.406673 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.518735] [IGT] panfrost_get_param: exiting, ret=77
11121 22:57:04.406783 .1.31 aarch64)
11122 22:57:04.419809 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.531051] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
11123 22:57:04.420096 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
11125 22:57:04.422989 b/drmtest.c:621:
11126 22:57:04.423108 Test requirement: !(fd<0)
11127 22:57:04.429833 No known gpu found for chipset flags 0x32 (panfrost)
11128 22:57:04.432772 Last errno: 2, No such file or directory
11129 22:57:04.436404 [1mSubtest get-bad-param: SKIP (0.000s)[0m
11130 22:57:04.443803 <14>[ 20.557398] [IGT] panfrost_get_param: executing
11131 22:57:04.453837 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.565734] [IGT] panfrost_get_param: exiting, ret=77
11132 22:57:04.453951 .1.31 aarch64)
11133 22:57:04.467196 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.578601] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
11134 22:57:04.467488 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
11136 22:57:04.470419 b/drmtest.c:621:
11137 22:57:04.473474 Test requireme<8>[ 20.588008] <LAVA_SIGNAL_TESTSET STOP>
11138 22:57:04.473722 Received signal: <TESTSET> STOP
11139 22:57:04.473793 Closing test_set panfrost_get_param
11140 22:57:04.477016 nt: !(fd<0)
11141 22:57:04.480416 No known gpu found for chipset flags 0x32 (panfrost)
11142 22:57:04.483469 Last errno: 2, No such file or directory
11143 22:57:04.486581 [1mSubtest get-bad-padding: SKIP (0.000s)[0m
11144 22:57:04.500614 <8>[ 20.614469] <LAVA_SIGNAL_TESTSET START panfrost_prime>
11145 22:57:04.500968 Received signal: <TESTSET> START panfrost_prime
11146 22:57:04.501049 Starting test_set panfrost_prime
11147 22:57:04.523438 <14>[ 20.636910] [IGT] panfrost_prime: executing
11148 22:57:04.533225 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.644645] [IGT] panfrost_prime: exiting, ret=77
11149 22:57:04.533337 .1.31 aarch64)
11150 22:57:04.546535 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.656936] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
11151 22:57:04.546843 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
11153 22:57:04.549647 b/drmtest.c:621:
11154 22:57:04.552809 Test requireme<8>[ 20.666707] <LAVA_SIGNAL_TESTSET STOP>
11155 22:57:04.553058 nt: !(fd<0)
11156 22:57:04.553325 Received signal: <TESTSET> STOP
11157 22:57:04.553394 Closing test_set panfrost_prime
11158 22:57:04.559483 No known gpu found for chipset flags 0x32 (panfrost)
11159 22:57:04.562756 Last errno: 2, No such file or directory
11160 22:57:04.566162 [1mSubtest gem-prime-import: SKIP (0.000s)[0m
11161 22:57:04.578789 <8>[ 20.692365] <LAVA_SIGNAL_TESTSET START panfrost_submit>
11162 22:57:04.579107 Received signal: <TESTSET> START panfrost_submit
11163 22:57:04.579189 Starting test_set panfrost_submit
11164 22:57:04.601198 <14>[ 20.714799] [IGT] panfrost_submit: executing
11165 22:57:04.611131 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.722782] [IGT] panfrost_submit: exiting, ret=77
11166 22:57:04.611219 .1.31 aarch64)
11167 22:57:04.624097 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.734879] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
11168 22:57:04.624236 b/drmtest.c:621:
11169 22:57:04.624524 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
11171 22:57:04.627681 Test requirement: !(fd<0)
11172 22:57:04.634232 No known gpu found for chipset flags 0x32 (panfrost)
11173 22:57:04.637646 Last errno: 2, No such file or directory
11174 22:57:04.640724 [1mSubtest pan-submit: SKIP (0.000s)[0m
11175 22:57:04.647219 <14>[ 20.760161] [IGT] panfrost_submit: executing
11176 22:57:04.657192 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.768218] [IGT] panfrost_submit: exiting, ret=77
11177 22:57:04.657299 .1.31 aarch64)
11178 22:57:04.670326 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.780131] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
11179 22:57:04.670477 b/drmtest.c:621:
11180 22:57:04.670762 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
11182 22:57:04.673963 Test requirement: !(fd<0)
11183 22:57:04.680557 No known gpu found for chipset flags 0x32 (panfrost)
11184 22:57:04.683532 Last errno: 2, No such file or directory
11185 22:57:04.687034 [1mSubtest pan-submit-error-no-jc: SKIP (0.000s)[0m
11186 22:57:04.693643 <14>[ 20.806290] [IGT] panfrost_submit: executing
11187 22:57:04.700358 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.814198] [IGT] panfrost_submit: exiting, ret=77
11188 22:57:04.703672 .1.31 aarch64)
11189 22:57:04.716632 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.826514] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
11190 22:57:04.716957 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
11192 22:57:04.720194 b/drmtest.c:621:
11193 22:57:04.720273 Test requirement: !(fd<0)
11194 22:57:04.726698 No known gpu found for chipset flags 0x32 (panfrost)
11195 22:57:04.730094 Last errno: 2, No such file or directory
11196 22:57:04.736611 [1mSubtest pan-submit-error-bad-in-syncs: SKIP (0.000s)[0m
11197 22:57:04.739945 <14>[ 20.852776] [IGT] panfrost_submit: executing
11198 22:57:04.749629 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.861461] [IGT] panfrost_submit: exiting, ret=77
11199 22:57:04.749748 .1.31 aarch64)
11200 22:57:04.763122 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
11202 22:57:04.766386 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.873520] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
11203 22:57:04.766498 b/drmtest.c:621:
11204 22:57:04.769379 Test requirement: !(fd<0)
11205 22:57:04.772677 No known gpu found for chipset flags 0x32 (panfrost)
11206 22:57:04.776227 Last errno: 2, No such file or directory
11207 22:57:04.782443 [1mSubtest pan-submit-error-bad-bo-handles: SKIP (0.000s)[0m
11208 22:57:04.785937 <14>[ 20.900590] [IGT] panfrost_submit: executing
11209 22:57:04.795653 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.909081] [IGT] panfrost_submit: exiting, ret=77
11210 22:57:04.799162 .1.31 aarch64)
11211 22:57:04.812601 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.921188] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
11212 22:57:04.812957 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11214 22:57:04.815498 b/drmtest.c:621:
11215 22:57:04.815605 Test requirement: !(fd<0)
11216 22:57:04.822225 No known gpu found for chipset flags 0x32 (panfrost)
11217 22:57:04.825243 Last errno: 2, No such file or directory
11218 22:57:04.828953 [1mSubtest pan-submit-error-bad-requirements: SKIP (0.000s)[0m
11219 22:57:04.835336 <14>[ 20.948208] [IGT] panfrost_submit: executing
11220 22:57:04.844973 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.956861] [IGT] panfrost_submit: exiting, ret=77
11221 22:57:04.845089 .1.31 aarch64)
11222 22:57:04.858516 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.968821] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
11223 22:57:04.858831 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11225 22:57:04.861650 b/drmtest.c:621:
11226 22:57:04.865026 Test requirement: !(fd<0)
11227 22:57:04.868135 No known gpu found for chipset flags 0x32 (panfrost)
11228 22:57:04.871630 Last errno: 2, No such file or directory
11229 22:57:04.878043 [1mSubtest pan-submit-error-bad-out-sync: SKIP (0.000s)[0m
11230 22:57:04.881386 <14>[ 20.995657] [IGT] panfrost_submit: executing
11231 22:57:04.891315 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 21.004133] [IGT] panfrost_submit: exiting, ret=77
11232 22:57:04.891422 .1.31 aarch64)
11233 22:57:04.904748 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.016256] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
11234 22:57:04.905104 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11236 22:57:04.907792 b/drmtest.c:621:
11237 22:57:04.907903 Test requirement: !(fd<0)
11238 22:57:04.914507 No known gpu found for chipset flags 0x32 (panfrost)
11239 22:57:04.918055 Last errno: 2, No such file or directory
11240 22:57:04.921253 [1mSubtest pan-reset: SKIP (0.000s)[0m
11241 22:57:04.928409 <14>[ 21.041100] [IGT] panfrost_submit: executing
11242 22:57:04.937792 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 21.048926] [IGT] panfrost_submit: exiting, ret=77
11243 22:57:04.937907 .1.31 aarch64)
11244 22:57:04.951231 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.060958] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
11245 22:57:04.951518 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11247 22:57:04.954306 b/drmtest.c:621:
11248 22:57:04.954384 Test requirement: !(fd<0)
11249 22:57:04.960817 No known gpu found for chipset flags 0x32 (panfrost)
11250 22:57:04.964135 Last errno: 2, No such file or directory
11251 22:57:04.967746 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
11252 22:57:04.973989 <14>[ 21.086947] [IGT] panfrost_submit: executing
11253 22:57:04.984180 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 21.095063] [IGT] panfrost_submit: exiting, ret=77
11254 22:57:04.984283 .1.31 aarch64)
11255 22:57:04.997211 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.106714] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11256 22:57:04.997519 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11258 22:57:05.000644 b/drmtest.c:621:
11259 22:57:05.003697 Test requireme<8>[ 21.117716] <LAVA_SIGNAL_TESTSET STOP>
11260 22:57:05.003803 nt: !(fd<0)
11261 22:57:05.004071 Received signal: <TESTSET> STOP
11262 22:57:05.004165 Closing test_set panfrost_submit
11263 22:57:05.010900 Received signal: <ENDRUN> 0_igt-gpu-panfrost 10597637_1.5.2.3.1
11264 22:57:05.011005 Ending use of test pattern.
11265 22:57:05.011073 Ending test lava.0_igt-gpu-panfrost (10597637_1.5.2.3.1), duration 0.89
11267 22:57:05.013849 No <8>[ 21.123494] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 10597637_1.5.2.3.1>
11268 22:57:05.017138 known gpu found for chipset flags 0x32 (panfrost)
11269 22:57:05.020761 Last errno: 2, No such file or directory
11270 22:57:05.023783 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11271 22:57:05.026818 + set +x
11272 22:57:05.026898 <LAVA_TEST_RUNNER EXIT>
11273 22:57:05.027138 ok: lava_test_shell seems to have completed
11274 22:57:05.027454 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11275 22:57:05.027564 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11276 22:57:05.027686 end: 3 lava-test-retry (duration 00:00:01) [common]
11277 22:57:05.027812 start: 4 finalize (timeout 00:07:57) [common]
11278 22:57:05.027935 start: 4.1 power-off (timeout 00:00:30) [common]
11279 22:57:05.028123 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11280 22:57:05.105797 >> Command sent successfully.
11281 22:57:05.108571 Returned 0 in 0 seconds
11282 22:57:05.208890 end: 4.1 power-off (duration 00:00:00) [common]
11284 22:57:05.209257 start: 4.2 read-feedback (timeout 00:07:57) [common]
11285 22:57:05.209525 Listened to connection for namespace 'common' for up to 1s
11286 22:57:06.210451 Finalising connection for namespace 'common'
11287 22:57:06.210658 Disconnecting from shell: Finalise
11288 22:57:06.210770 / #
11289 22:57:06.311136 end: 4.2 read-feedback (duration 00:00:01) [common]
11290 22:57:06.311362 end: 4 finalize (duration 00:00:01) [common]
11291 22:57:06.311527 Cleaning after the job
11292 22:57:06.311655 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597637/tftp-deploy-_q_lfg_t/ramdisk
11293 22:57:06.318172 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597637/tftp-deploy-_q_lfg_t/kernel
11294 22:57:06.324746 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597637/tftp-deploy-_q_lfg_t/dtb
11295 22:57:06.325066 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597637/tftp-deploy-_q_lfg_t/modules
11296 22:57:06.331064 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10597637
11297 22:57:06.446698 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10597637
11298 22:57:06.446913 Job finished correctly