Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 47
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 31
1 22:57:31.623110 lava-dispatcher, installed at version: 2023.05.1
2 22:57:31.623306 start: 0 validate
3 22:57:31.623468 Start time: 2023-06-05 22:57:31.623461+00:00 (UTC)
4 22:57:31.623595 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:57:31.623724 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 22:57:31.909992 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:57:31.910180 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:57:32.191253 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:57:32.191439 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:57:32.476068 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:57:32.476246 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 22:57:32.760993 Using caching service: 'http://localhost/cache/?uri=%s'
13 22:57:32.761149 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 22:57:33.052633 validate duration: 1.43
16 22:57:33.052917 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:57:33.053018 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:57:33.053112 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:57:33.053260 Not decompressing ramdisk as can be used compressed.
20 22:57:33.053354 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/initrd.cpio.gz
21 22:57:33.053423 saving as /var/lib/lava/dispatcher/tmp/10597663/tftp-deploy-1ioyhets/ramdisk/initrd.cpio.gz
22 22:57:33.053496 total size: 4665601 (4MB)
23 22:57:33.054561 progress 0% (0MB)
24 22:57:33.056021 progress 5% (0MB)
25 22:57:33.057350 progress 10% (0MB)
26 22:57:33.058671 progress 15% (0MB)
27 22:57:33.059918 progress 20% (0MB)
28 22:57:33.061155 progress 25% (1MB)
29 22:57:33.062379 progress 30% (1MB)
30 22:57:33.063599 progress 35% (1MB)
31 22:57:33.064830 progress 40% (1MB)
32 22:57:33.066209 progress 45% (2MB)
33 22:57:33.067428 progress 50% (2MB)
34 22:57:33.068645 progress 55% (2MB)
35 22:57:33.069873 progress 60% (2MB)
36 22:57:33.071099 progress 65% (2MB)
37 22:57:33.072318 progress 70% (3MB)
38 22:57:33.073548 progress 75% (3MB)
39 22:57:33.074763 progress 80% (3MB)
40 22:57:33.076145 progress 85% (3MB)
41 22:57:33.077378 progress 90% (4MB)
42 22:57:33.078599 progress 95% (4MB)
43 22:57:33.079839 progress 100% (4MB)
44 22:57:33.079997 4MB downloaded in 0.03s (167.92MB/s)
45 22:57:33.080153 end: 1.1.1 http-download (duration 00:00:00) [common]
47 22:57:33.080404 end: 1.1 download-retry (duration 00:00:00) [common]
48 22:57:33.080498 start: 1.2 download-retry (timeout 00:10:00) [common]
49 22:57:33.080590 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 22:57:33.080746 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 22:57:33.080831 saving as /var/lib/lava/dispatcher/tmp/10597663/tftp-deploy-1ioyhets/kernel/Image
52 22:57:33.080896 total size: 45746688 (43MB)
53 22:57:33.080958 No compression specified
54 22:57:33.082062 progress 0% (0MB)
55 22:57:33.093639 progress 5% (2MB)
56 22:57:33.105849 progress 10% (4MB)
57 22:57:33.117557 progress 15% (6MB)
58 22:57:33.129249 progress 20% (8MB)
59 22:57:33.141058 progress 25% (10MB)
60 22:57:33.152925 progress 30% (13MB)
61 22:57:33.164981 progress 35% (15MB)
62 22:57:33.176681 progress 40% (17MB)
63 22:57:33.188381 progress 45% (19MB)
64 22:57:33.199928 progress 50% (21MB)
65 22:57:33.211572 progress 55% (24MB)
66 22:57:33.223076 progress 60% (26MB)
67 22:57:33.234690 progress 65% (28MB)
68 22:57:33.246325 progress 70% (30MB)
69 22:57:33.258260 progress 75% (32MB)
70 22:57:33.269793 progress 80% (34MB)
71 22:57:33.281356 progress 85% (37MB)
72 22:57:33.292922 progress 90% (39MB)
73 22:57:33.304855 progress 95% (41MB)
74 22:57:33.316292 progress 100% (43MB)
75 22:57:33.316449 43MB downloaded in 0.24s (185.22MB/s)
76 22:57:33.316603 end: 1.2.1 http-download (duration 00:00:00) [common]
78 22:57:33.316885 end: 1.2 download-retry (duration 00:00:00) [common]
79 22:57:33.316975 start: 1.3 download-retry (timeout 00:10:00) [common]
80 22:57:33.317065 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 22:57:33.317223 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 22:57:33.317296 saving as /var/lib/lava/dispatcher/tmp/10597663/tftp-deploy-1ioyhets/dtb/mt8192-asurada-spherion-r0.dtb
83 22:57:33.317359 total size: 46924 (0MB)
84 22:57:33.317420 No compression specified
85 22:57:33.318533 progress 69% (0MB)
86 22:57:33.318806 progress 100% (0MB)
87 22:57:33.318961 0MB downloaded in 0.00s (28.00MB/s)
88 22:57:33.319083 end: 1.3.1 http-download (duration 00:00:00) [common]
90 22:57:33.319313 end: 1.3 download-retry (duration 00:00:00) [common]
91 22:57:33.319399 start: 1.4 download-retry (timeout 00:10:00) [common]
92 22:57:33.319483 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 22:57:33.319645 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/full.rootfs.tar.xz
94 22:57:33.319714 saving as /var/lib/lava/dispatcher/tmp/10597663/tftp-deploy-1ioyhets/nfsrootfs/full.rootfs.tar
95 22:57:33.319776 total size: 200770336 (191MB)
96 22:57:33.319837 Using unxz to decompress xz
97 22:57:33.323125 progress 0% (0MB)
98 22:57:33.854278 progress 5% (9MB)
99 22:57:34.372517 progress 10% (19MB)
100 22:57:34.954354 progress 15% (28MB)
101 22:57:35.322027 progress 20% (38MB)
102 22:57:35.649203 progress 25% (47MB)
103 22:57:36.244281 progress 30% (57MB)
104 22:57:36.793268 progress 35% (67MB)
105 22:57:37.380171 progress 40% (76MB)
106 22:57:37.948074 progress 45% (86MB)
107 22:57:38.547920 progress 50% (95MB)
108 22:57:39.176685 progress 55% (105MB)
109 22:57:39.863933 progress 60% (114MB)
110 22:57:39.982260 progress 65% (124MB)
111 22:57:40.130024 progress 70% (134MB)
112 22:57:40.228389 progress 75% (143MB)
113 22:57:40.302368 progress 80% (153MB)
114 22:57:40.371759 progress 85% (162MB)
115 22:57:40.471118 progress 90% (172MB)
116 22:57:40.753258 progress 95% (181MB)
117 22:57:41.336444 progress 100% (191MB)
118 22:57:41.341132 191MB downloaded in 8.02s (23.87MB/s)
119 22:57:41.341447 end: 1.4.1 http-download (duration 00:00:08) [common]
121 22:57:41.341853 end: 1.4 download-retry (duration 00:00:08) [common]
122 22:57:41.341975 start: 1.5 download-retry (timeout 00:09:52) [common]
123 22:57:41.342095 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 22:57:41.342289 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 22:57:41.342388 saving as /var/lib/lava/dispatcher/tmp/10597663/tftp-deploy-1ioyhets/modules/modules.tar
126 22:57:41.342480 total size: 8552396 (8MB)
127 22:57:41.342573 Using unxz to decompress xz
128 22:57:41.346137 progress 0% (0MB)
129 22:57:41.367656 progress 5% (0MB)
130 22:57:41.391573 progress 10% (0MB)
131 22:57:41.422221 progress 15% (1MB)
132 22:57:41.448445 progress 20% (1MB)
133 22:57:41.474542 progress 25% (2MB)
134 22:57:41.500793 progress 30% (2MB)
135 22:57:41.526738 progress 35% (2MB)
136 22:57:41.551507 progress 40% (3MB)
137 22:57:41.576950 progress 45% (3MB)
138 22:57:41.602035 progress 50% (4MB)
139 22:57:41.626286 progress 55% (4MB)
140 22:57:41.649849 progress 60% (4MB)
141 22:57:41.674253 progress 65% (5MB)
142 22:57:41.699947 progress 70% (5MB)
143 22:57:41.724697 progress 75% (6MB)
144 22:57:41.751030 progress 80% (6MB)
145 22:57:41.776337 progress 85% (6MB)
146 22:57:41.801592 progress 90% (7MB)
147 22:57:41.825219 progress 95% (7MB)
148 22:57:41.850517 progress 100% (8MB)
149 22:57:41.857686 8MB downloaded in 0.52s (15.83MB/s)
150 22:57:41.857982 end: 1.5.1 http-download (duration 00:00:01) [common]
152 22:57:41.858337 end: 1.5 download-retry (duration 00:00:01) [common]
153 22:57:41.858429 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 22:57:41.858523 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 22:57:45.341310 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10597663/extract-nfsrootfs-15xou4fs
156 22:57:45.341516 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 22:57:45.341625 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 22:57:45.341805 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo
159 22:57:45.341952 makedir: /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo/lava-10597663/bin
160 22:57:45.342063 makedir: /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo/lava-10597663/tests
161 22:57:45.342170 makedir: /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo/lava-10597663/results
162 22:57:45.342273 Creating /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo/lava-10597663/bin/lava-add-keys
163 22:57:45.342414 Creating /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo/lava-10597663/bin/lava-add-sources
164 22:57:45.342541 Creating /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo/lava-10597663/bin/lava-background-process-start
165 22:57:45.342666 Creating /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo/lava-10597663/bin/lava-background-process-stop
166 22:57:45.342794 Creating /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo/lava-10597663/bin/lava-common-functions
167 22:57:45.342917 Creating /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo/lava-10597663/bin/lava-echo-ipv4
168 22:57:45.343042 Creating /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo/lava-10597663/bin/lava-install-packages
169 22:57:45.343164 Creating /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo/lava-10597663/bin/lava-installed-packages
170 22:57:45.343287 Creating /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo/lava-10597663/bin/lava-os-build
171 22:57:45.343410 Creating /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo/lava-10597663/bin/lava-probe-channel
172 22:57:45.343533 Creating /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo/lava-10597663/bin/lava-probe-ip
173 22:57:45.343656 Creating /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo/lava-10597663/bin/lava-target-ip
174 22:57:45.343777 Creating /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo/lava-10597663/bin/lava-target-mac
175 22:57:45.343897 Creating /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo/lava-10597663/bin/lava-target-storage
176 22:57:45.344022 Creating /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo/lava-10597663/bin/lava-test-case
177 22:57:45.344144 Creating /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo/lava-10597663/bin/lava-test-event
178 22:57:45.344265 Creating /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo/lava-10597663/bin/lava-test-feedback
179 22:57:45.344387 Creating /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo/lava-10597663/bin/lava-test-raise
180 22:57:45.344508 Creating /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo/lava-10597663/bin/lava-test-reference
181 22:57:45.344633 Creating /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo/lava-10597663/bin/lava-test-runner
182 22:57:45.344756 Creating /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo/lava-10597663/bin/lava-test-set
183 22:57:45.344882 Creating /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo/lava-10597663/bin/lava-test-shell
184 22:57:45.345010 Updating /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo/lava-10597663/bin/lava-add-keys (debian)
185 22:57:45.345158 Updating /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo/lava-10597663/bin/lava-add-sources (debian)
186 22:57:45.345301 Updating /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo/lava-10597663/bin/lava-install-packages (debian)
187 22:57:45.345443 Updating /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo/lava-10597663/bin/lava-installed-packages (debian)
188 22:57:45.345583 Updating /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo/lava-10597663/bin/lava-os-build (debian)
189 22:57:45.345707 Creating /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo/lava-10597663/environment
190 22:57:45.345806 LAVA metadata
191 22:57:45.345877 - LAVA_JOB_ID=10597663
192 22:57:45.345942 - LAVA_DISPATCHER_IP=192.168.201.1
193 22:57:45.346042 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 22:57:45.346109 skipped lava-vland-overlay
195 22:57:45.346185 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 22:57:45.346265 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 22:57:45.346327 skipped lava-multinode-overlay
198 22:57:45.346401 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 22:57:45.346480 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 22:57:45.346554 Loading test definitions
201 22:57:45.346645 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 22:57:45.346716 Using /lava-10597663 at stage 0
203 22:57:45.347046 uuid=10597663_1.6.2.3.1 testdef=None
204 22:57:45.347138 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 22:57:45.347225 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 22:57:45.347682 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 22:57:45.347916 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 22:57:45.348476 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 22:57:45.348710 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 22:57:45.349317 runner path: /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo/lava-10597663/0/tests/0_timesync-off test_uuid 10597663_1.6.2.3.1
213 22:57:45.349471 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 22:57:45.349719 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 22:57:45.349794 Using /lava-10597663 at stage 0
217 22:57:45.349892 Fetching tests from https://github.com/kernelci/test-definitions.git
218 22:57:45.349971 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo/lava-10597663/0/tests/1_kselftest-arm64'
219 22:57:48.588109 Running '/usr/bin/git checkout kernelci.org
220 22:57:48.734428 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo/lava-10597663/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 22:57:48.735221 uuid=10597663_1.6.2.3.5 testdef=None
222 22:57:48.735406 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 22:57:48.735728 start: 1.6.2.3.6 test-overlay (timeout 00:09:44) [common]
225 22:57:48.736586 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 22:57:48.736915 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:44) [common]
228 22:57:48.738042 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 22:57:48.738360 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:44) [common]
231 22:57:48.739427 runner path: /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo/lava-10597663/0/tests/1_kselftest-arm64 test_uuid 10597663_1.6.2.3.5
232 22:57:48.739528 BOARD='mt8192-asurada-spherion-r0'
233 22:57:48.739633 BRANCH='cip'
234 22:57:48.739731 SKIPFILE='/dev/null'
235 22:57:48.739828 SKIP_INSTALL='True'
236 22:57:48.739933 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 22:57:48.740030 TST_CASENAME=''
238 22:57:48.740154 TST_CMDFILES='arm64'
239 22:57:48.740368 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 22:57:48.740733 Creating lava-test-runner.conf files
242 22:57:48.740861 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10597663/lava-overlay-lio6sdwo/lava-10597663/0 for stage 0
243 22:57:48.741021 - 0_timesync-off
244 22:57:48.741114 - 1_kselftest-arm64
245 22:57:48.741249 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 22:57:48.741387 start: 1.6.2.4 compress-overlay (timeout 00:09:44) [common]
247 22:57:56.522246 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 22:57:56.522408 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:37) [common]
249 22:57:56.522500 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 22:57:56.522609 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 22:57:56.522735 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:37) [common]
252 22:57:56.637709 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 22:57:56.638087 start: 1.6.4 extract-modules (timeout 00:09:36) [common]
254 22:57:56.638241 extracting modules file /var/lib/lava/dispatcher/tmp/10597663/tftp-deploy-1ioyhets/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597663/extract-nfsrootfs-15xou4fs
255 22:57:56.923984 extracting modules file /var/lib/lava/dispatcher/tmp/10597663/tftp-deploy-1ioyhets/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597663/extract-overlay-ramdisk-jju5dc4u/ramdisk
256 22:57:57.199871 end: 1.6.4 extract-modules (duration 00:00:01) [common]
257 22:57:57.200048 start: 1.6.5 apply-overlay-tftp (timeout 00:09:36) [common]
258 22:57:57.200180 [common] Applying overlay to NFS
259 22:57:57.200279 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597663/compress-overlay-voryfzpb/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10597663/extract-nfsrootfs-15xou4fs
260 22:57:58.256104 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 22:57:58.256304 start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
262 22:57:58.256442 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 22:57:58.256628 start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
264 22:57:58.256753 Building ramdisk /var/lib/lava/dispatcher/tmp/10597663/extract-overlay-ramdisk-jju5dc4u/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10597663/extract-overlay-ramdisk-jju5dc4u/ramdisk
265 22:57:58.518227 >> 117807 blocks
266 22:58:00.525985 rename /var/lib/lava/dispatcher/tmp/10597663/extract-overlay-ramdisk-jju5dc4u/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10597663/tftp-deploy-1ioyhets/ramdisk/ramdisk.cpio.gz
267 22:58:00.526466 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 22:58:00.526622 start: 1.6.8 prepare-kernel (timeout 00:09:33) [common]
269 22:58:00.526761 start: 1.6.8.1 prepare-fit (timeout 00:09:33) [common]
270 22:58:00.526901 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10597663/tftp-deploy-1ioyhets/kernel/Image'
271 22:58:12.871256 Returned 0 in 12 seconds
272 22:58:12.971893 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10597663/tftp-deploy-1ioyhets/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10597663/tftp-deploy-1ioyhets/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10597663/tftp-deploy-1ioyhets/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10597663/tftp-deploy-1ioyhets/kernel/image.itb
273 22:58:13.274715 output: FIT description: Kernel Image image with one or more FDT blobs
274 22:58:13.275126 output: Created: Mon Jun 5 23:58:13 2023
275 22:58:13.275233 output: Image 0 (kernel-1)
276 22:58:13.275374 output: Description:
277 22:58:13.275473 output: Created: Mon Jun 5 23:58:13 2023
278 22:58:13.275567 output: Type: Kernel Image
279 22:58:13.275677 output: Compression: lzma compressed
280 22:58:13.275821 output: Data Size: 10085945 Bytes = 9849.56 KiB = 9.62 MiB
281 22:58:13.275916 output: Architecture: AArch64
282 22:58:13.276006 output: OS: Linux
283 22:58:13.276111 output: Load Address: 0x00000000
284 22:58:13.276202 output: Entry Point: 0x00000000
285 22:58:13.276289 output: Hash algo: crc32
286 22:58:13.276421 output: Hash value: b2943ff2
287 22:58:13.276508 output: Image 1 (fdt-1)
288 22:58:13.276592 output: Description: mt8192-asurada-spherion-r0
289 22:58:13.276682 output: Created: Mon Jun 5 23:58:13 2023
290 22:58:13.276792 output: Type: Flat Device Tree
291 22:58:13.276970 output: Compression: uncompressed
292 22:58:13.277141 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 22:58:13.277265 output: Architecture: AArch64
294 22:58:13.277353 output: Hash algo: crc32
295 22:58:13.277520 output: Hash value: 1df858fa
296 22:58:13.277646 output: Image 2 (ramdisk-1)
297 22:58:13.277792 output: Description: unavailable
298 22:58:13.277898 output: Created: Mon Jun 5 23:58:13 2023
299 22:58:13.277985 output: Type: RAMDisk Image
300 22:58:13.278097 output: Compression: Unknown Compression
301 22:58:13.278200 output: Data Size: 17645803 Bytes = 17232.23 KiB = 16.83 MiB
302 22:58:13.278287 output: Architecture: AArch64
303 22:58:13.278403 output: OS: Linux
304 22:58:13.278486 output: Load Address: unavailable
305 22:58:13.278585 output: Entry Point: unavailable
306 22:58:13.278683 output: Hash algo: crc32
307 22:58:13.278781 output: Hash value: 80750ed7
308 22:58:13.278868 output: Default Configuration: 'conf-1'
309 22:58:13.278968 output: Configuration 0 (conf-1)
310 22:58:13.279055 output: Description: mt8192-asurada-spherion-r0
311 22:58:13.279138 output: Kernel: kernel-1
312 22:58:13.279233 output: Init Ramdisk: ramdisk-1
313 22:58:13.279322 output: FDT: fdt-1
314 22:58:13.279404 output: Loadables: kernel-1
315 22:58:13.279486 output:
316 22:58:13.279754 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 22:58:13.279884 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 22:58:13.280035 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 22:58:13.280167 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
320 22:58:13.280274 No LXC device requested
321 22:58:13.280383 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 22:58:13.280506 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
323 22:58:13.280638 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 22:58:13.280750 Checking files for TFTP limit of 4294967296 bytes.
325 22:58:13.281486 end: 1 tftp-deploy (duration 00:00:40) [common]
326 22:58:13.281635 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 22:58:13.281787 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 22:58:13.281958 substitutions:
329 22:58:13.282062 - {DTB}: 10597663/tftp-deploy-1ioyhets/dtb/mt8192-asurada-spherion-r0.dtb
330 22:58:13.282160 - {INITRD}: 10597663/tftp-deploy-1ioyhets/ramdisk/ramdisk.cpio.gz
331 22:58:13.282291 - {KERNEL}: 10597663/tftp-deploy-1ioyhets/kernel/Image
332 22:58:13.282383 - {LAVA_MAC}: None
333 22:58:13.282502 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10597663/extract-nfsrootfs-15xou4fs
334 22:58:13.282592 - {NFS_SERVER_IP}: 192.168.201.1
335 22:58:13.282696 - {PRESEED_CONFIG}: None
336 22:58:13.282817 - {PRESEED_LOCAL}: None
337 22:58:13.282904 - {RAMDISK}: 10597663/tftp-deploy-1ioyhets/ramdisk/ramdisk.cpio.gz
338 22:58:13.283063 - {ROOT_PART}: None
339 22:58:13.283153 - {ROOT}: None
340 22:58:13.283248 - {SERVER_IP}: 192.168.201.1
341 22:58:13.283346 - {TEE}: None
342 22:58:13.283435 Parsed boot commands:
343 22:58:13.283551 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 22:58:13.283797 Parsed boot commands: tftpboot 192.168.201.1 10597663/tftp-deploy-1ioyhets/kernel/image.itb 10597663/tftp-deploy-1ioyhets/kernel/cmdline
345 22:58:13.283938 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 22:58:13.284133 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 22:58:13.284306 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 22:58:13.284433 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 22:58:13.284539 Not connected, no need to disconnect.
350 22:58:13.284650 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 22:58:13.284792 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 22:58:13.284910 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-1'
353 22:58:13.288622 Setting prompt string to ['lava-test: # ']
354 22:58:13.289097 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 22:58:13.289277 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 22:58:13.289438 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 22:58:13.289582 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 22:58:13.289949 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
359 22:58:18.424834 >> Command sent successfully.
360 22:58:18.427075 Returned 0 in 5 seconds
361 22:58:18.527451 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 22:58:18.527842 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 22:58:18.527979 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 22:58:18.528106 Setting prompt string to 'Starting depthcharge on Spherion...'
366 22:58:18.528211 Changing prompt to 'Starting depthcharge on Spherion...'
367 22:58:18.528318 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 22:58:18.528647 [Enter `^Ec?' for help]
369 22:58:18.701523
370 22:58:18.701697
371 22:58:18.701802 F0: 102B 0000
372 22:58:18.701898
373 22:58:18.701993 F3: 1001 0000 [0200]
374 22:58:18.705045
375 22:58:18.705123 F3: 1001 0000
376 22:58:18.705189
377 22:58:18.705250 F7: 102D 0000
378 22:58:18.705310
379 22:58:18.707956 F1: 0000 0000
380 22:58:18.708023
381 22:58:18.708082 V0: 0000 0000 [0001]
382 22:58:18.708140
383 22:58:18.711594 00: 0007 8000
384 22:58:18.711681
385 22:58:18.711748 01: 0000 0000
386 22:58:18.711812
387 22:58:18.714722 BP: 0C00 0209 [0000]
388 22:58:18.714811
389 22:58:18.714920 G0: 1182 0000
390 22:58:18.714986
391 22:58:18.718238 EC: 0000 0021 [4000]
392 22:58:18.718332
393 22:58:18.718405 S7: 0000 0000 [0000]
394 22:58:18.718469
395 22:58:18.721720 CC: 0000 0000 [0001]
396 22:58:18.721810
397 22:58:18.721879 T0: 0000 0040 [010F]
398 22:58:18.721947
399 22:58:18.722008 Jump to BL
400 22:58:18.724680
401 22:58:18.748380
402 22:58:18.748498
403 22:58:18.748591
404 22:58:18.755984 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 22:58:18.759526 ARM64: Exception handlers installed.
406 22:58:18.762581 ARM64: Testing exception
407 22:58:18.766031 ARM64: Done test exception
408 22:58:18.772496 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 22:58:18.782552 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 22:58:18.789344 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 22:58:18.799638 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 22:58:18.805969 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 22:58:18.816112 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 22:58:18.826631 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 22:58:18.833154 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 22:58:18.851501 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 22:58:18.854528 WDT: Last reset was cold boot
418 22:58:18.857705 SPI1(PAD0) initialized at 2873684 Hz
419 22:58:18.860913 SPI5(PAD0) initialized at 992727 Hz
420 22:58:18.864471 VBOOT: Loading verstage.
421 22:58:18.870975 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 22:58:18.874481 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 22:58:18.877501 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 22:58:18.881019 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 22:58:18.888431 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 22:58:18.895031 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 22:58:18.906027 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 22:58:18.906121
429 22:58:18.906190
430 22:58:18.915886 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 22:58:18.919459 ARM64: Exception handlers installed.
432 22:58:18.922488 ARM64: Testing exception
433 22:58:18.922601 ARM64: Done test exception
434 22:58:18.929040 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 22:58:18.932579 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 22:58:18.947087 Probing TPM: . done!
437 22:58:18.947212 TPM ready after 0 ms
438 22:58:18.954071 Connected to device vid:did:rid of 1ae0:0028:00
439 22:58:18.960596 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 22:58:19.018788 Initialized TPM device CR50 revision 0
441 22:58:19.030265 tlcl_send_startup: Startup return code is 0
442 22:58:19.030417 TPM: setup succeeded
443 22:58:19.041869 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 22:58:19.050425 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 22:58:19.060487 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 22:58:19.069968 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 22:58:19.073480 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 22:58:19.080058 in-header: 03 07 00 00 08 00 00 00
449 22:58:19.083592 in-data: aa e4 47 04 13 02 00 00
450 22:58:19.087068 Chrome EC: UHEPI supported
451 22:58:19.094240 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 22:58:19.097628 in-header: 03 ad 00 00 08 00 00 00
453 22:58:19.101495 in-data: 00 20 20 08 00 00 00 00
454 22:58:19.101587 Phase 1
455 22:58:19.105123 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 22:58:19.112630 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 22:58:19.119815 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 22:58:19.119937 Recovery requested (1009000e)
459 22:58:19.130261 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 22:58:19.136268 tlcl_extend: response is 0
461 22:58:19.146416 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 22:58:19.152556 tlcl_extend: response is 0
463 22:58:19.159182 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 22:58:19.179664 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 22:58:19.186196 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 22:58:19.186295
467 22:58:19.186387
468 22:58:19.196080 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 22:58:19.200043 ARM64: Exception handlers installed.
470 22:58:19.200143 ARM64: Testing exception
471 22:58:19.203548 ARM64: Done test exception
472 22:58:19.224967 pmic_efuse_setting: Set efuses in 11 msecs
473 22:58:19.228266 pmwrap_interface_init: Select PMIF_VLD_RDY
474 22:58:19.235483 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 22:58:19.238604 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 22:58:19.245541 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 22:58:19.248527 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 22:58:19.252396 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 22:58:19.259160 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 22:58:19.262603 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 22:58:19.269734 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 22:58:19.273232 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 22:58:19.277072 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 22:58:19.280659 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 22:58:19.287242 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 22:58:19.290190 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 22:58:19.297204 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 22:58:19.303603 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 22:58:19.307414 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 22:58:19.314543 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 22:58:19.318342 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 22:58:19.324609 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 22:58:19.331316 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 22:58:19.335436 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 22:58:19.342045 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 22:58:19.348662 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 22:58:19.352188 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 22:58:19.358709 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 22:58:19.365305 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 22:58:19.368510 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 22:58:19.375104 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 22:58:19.378702 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 22:58:19.385157 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 22:58:19.388660 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 22:58:19.395130 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 22:58:19.398776 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 22:58:19.405266 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 22:58:19.408186 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 22:58:19.414753 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 22:58:19.418262 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 22:58:19.425006 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 22:58:19.428029 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 22:58:19.431995 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 22:58:19.435415 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 22:58:19.442384 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 22:58:19.445725 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 22:58:19.448979 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 22:58:19.455783 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 22:58:19.459127 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 22:58:19.462138 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 22:58:19.468736 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 22:58:19.472278 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 22:58:19.475771 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 22:58:19.478721 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 22:58:19.489041 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 22:58:19.495665 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 22:58:19.502299 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 22:58:19.508729 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 22:58:19.518871 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 22:58:19.522295 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 22:58:19.525660 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 22:58:19.531762 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 22:58:19.538740 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x7
534 22:58:19.541847 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 22:58:19.549198 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 22:58:19.552419 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 22:58:19.562331 [RTC]rtc_get_frequency_meter,154: input=15, output=771
538 22:58:19.571205 [RTC]rtc_get_frequency_meter,154: input=23, output=957
539 22:58:19.581251 [RTC]rtc_get_frequency_meter,154: input=19, output=864
540 22:58:19.590711 [RTC]rtc_get_frequency_meter,154: input=17, output=819
541 22:58:19.600188 [RTC]rtc_get_frequency_meter,154: input=16, output=796
542 22:58:19.603241 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
543 22:58:19.610213 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
544 22:58:19.613248 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
545 22:58:19.616470 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
546 22:58:19.619866 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
547 22:58:19.623313 ADC[4]: Raw value=902876 ID=7
548 22:58:19.626888 ADC[3]: Raw value=213179 ID=1
549 22:58:19.630085 RAM Code: 0x71
550 22:58:19.633420 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
551 22:58:19.636883 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
552 22:58:19.646731 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
553 22:58:19.653292 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 22:58:19.656654 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
555 22:58:19.659928 in-header: 03 07 00 00 08 00 00 00
556 22:58:19.663028 in-data: aa e4 47 04 13 02 00 00
557 22:58:19.666318 Chrome EC: UHEPI supported
558 22:58:19.673185 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
559 22:58:19.676317 in-header: 03 ed 00 00 08 00 00 00
560 22:58:19.679674 in-data: 80 20 60 08 00 00 00 00
561 22:58:19.683248 MRC: failed to locate region type 0.
562 22:58:19.689868 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
563 22:58:19.692933 DRAM-K: Running full calibration
564 22:58:19.699460 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
565 22:58:19.699570 header.status = 0x0
566 22:58:19.702941 header.version = 0x6 (expected: 0x6)
567 22:58:19.706388 header.size = 0xd00 (expected: 0xd00)
568 22:58:19.709781 header.flags = 0x0
569 22:58:19.716079 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
570 22:58:19.732824 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
571 22:58:19.739681 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
572 22:58:19.742782 dram_init: ddr_geometry: 2
573 22:58:19.746128 [EMI] MDL number = 2
574 22:58:19.746213 [EMI] Get MDL freq = 0
575 22:58:19.749682 dram_init: ddr_type: 0
576 22:58:19.749768 is_discrete_lpddr4: 1
577 22:58:19.753015 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
578 22:58:19.753102
579 22:58:19.753177
580 22:58:19.756133 [Bian_co] ETT version 0.0.0.1
581 22:58:19.762788 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
582 22:58:19.762874
583 22:58:19.766106 dramc_set_vcore_voltage set vcore to 650000
584 22:58:19.766193 Read voltage for 800, 4
585 22:58:19.769631 Vio18 = 0
586 22:58:19.769716 Vcore = 650000
587 22:58:19.769784 Vdram = 0
588 22:58:19.772627 Vddq = 0
589 22:58:19.772745 Vmddr = 0
590 22:58:19.776140 dram_init: config_dvfs: 1
591 22:58:19.779548 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
592 22:58:19.787052 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
593 22:58:19.790721 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
594 22:58:19.794275 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
595 22:58:19.798312 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
596 22:58:19.801798 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
597 22:58:19.801921 MEM_TYPE=3, freq_sel=18
598 22:58:19.805375 sv_algorithm_assistance_LP4_1600
599 22:58:19.809358 ============ PULL DRAM RESETB DOWN ============
600 22:58:19.812959 ========== PULL DRAM RESETB DOWN end =========
601 22:58:19.820558 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
602 22:58:19.823911 ===================================
603 22:58:19.824001 LPDDR4 DRAM CONFIGURATION
604 22:58:19.827806 ===================================
605 22:58:19.831616 EX_ROW_EN[0] = 0x0
606 22:58:19.831705 EX_ROW_EN[1] = 0x0
607 22:58:19.834985 LP4Y_EN = 0x0
608 22:58:19.835072 WORK_FSP = 0x0
609 22:58:19.838976 WL = 0x2
610 22:58:19.839065 RL = 0x2
611 22:58:19.839136 BL = 0x2
612 22:58:19.842309 RPST = 0x0
613 22:58:19.842397 RD_PRE = 0x0
614 22:58:19.845869 WR_PRE = 0x1
615 22:58:19.848971 WR_PST = 0x0
616 22:58:19.849057 DBI_WR = 0x0
617 22:58:19.852038 DBI_RD = 0x0
618 22:58:19.852151 OTF = 0x1
619 22:58:19.855691 ===================================
620 22:58:19.858545 ===================================
621 22:58:19.858658 ANA top config
622 22:58:19.862079 ===================================
623 22:58:19.865566 DLL_ASYNC_EN = 0
624 22:58:19.868874 ALL_SLAVE_EN = 1
625 22:58:19.871812 NEW_RANK_MODE = 1
626 22:58:19.875209 DLL_IDLE_MODE = 1
627 22:58:19.875327 LP45_APHY_COMB_EN = 1
628 22:58:19.878618 TX_ODT_DIS = 1
629 22:58:19.881963 NEW_8X_MODE = 1
630 22:58:19.885308 ===================================
631 22:58:19.888873 ===================================
632 22:58:19.891810 data_rate = 1600
633 22:58:19.895616 CKR = 1
634 22:58:19.895721 DQ_P2S_RATIO = 8
635 22:58:19.899223 ===================================
636 22:58:19.902711 CA_P2S_RATIO = 8
637 22:58:19.906710 DQ_CA_OPEN = 0
638 22:58:19.910207 DQ_SEMI_OPEN = 0
639 22:58:19.910292 CA_SEMI_OPEN = 0
640 22:58:19.914328 CA_FULL_RATE = 0
641 22:58:19.917705 DQ_CKDIV4_EN = 1
642 22:58:19.921184 CA_CKDIV4_EN = 1
643 22:58:19.921261 CA_PREDIV_EN = 0
644 22:58:19.924750 PH8_DLY = 0
645 22:58:19.927803 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
646 22:58:19.931249 DQ_AAMCK_DIV = 4
647 22:58:19.934689 CA_AAMCK_DIV = 4
648 22:58:19.934768 CA_ADMCK_DIV = 4
649 22:58:19.938240 DQ_TRACK_CA_EN = 0
650 22:58:19.941122 CA_PICK = 800
651 22:58:19.944594 CA_MCKIO = 800
652 22:58:19.947682 MCKIO_SEMI = 0
653 22:58:19.951102 PLL_FREQ = 3068
654 22:58:19.954555 DQ_UI_PI_RATIO = 32
655 22:58:19.954632 CA_UI_PI_RATIO = 0
656 22:58:19.958134 ===================================
657 22:58:19.960956 ===================================
658 22:58:19.964364 memory_type:LPDDR4
659 22:58:19.967637 GP_NUM : 10
660 22:58:19.967724 SRAM_EN : 1
661 22:58:19.971060 MD32_EN : 0
662 22:58:19.974404 ===================================
663 22:58:19.978049 [ANA_INIT] >>>>>>>>>>>>>>
664 22:58:19.978135 <<<<<< [CONFIGURE PHASE]: ANA_TX
665 22:58:19.981390 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
666 22:58:19.985217 ===================================
667 22:58:19.988736 data_rate = 1600,PCW = 0X7600
668 22:58:19.992698 ===================================
669 22:58:19.996285 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
670 22:58:20.000271 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
671 22:58:20.007621 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
672 22:58:20.011345 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
673 22:58:20.014353 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
674 22:58:20.017965 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
675 22:58:20.021000 [ANA_INIT] flow start
676 22:58:20.021086 [ANA_INIT] PLL >>>>>>>>
677 22:58:20.024298 [ANA_INIT] PLL <<<<<<<<
678 22:58:20.027904 [ANA_INIT] MIDPI >>>>>>>>
679 22:58:20.030784 [ANA_INIT] MIDPI <<<<<<<<
680 22:58:20.030869 [ANA_INIT] DLL >>>>>>>>
681 22:58:20.034190 [ANA_INIT] flow end
682 22:58:20.037508 ============ LP4 DIFF to SE enter ============
683 22:58:20.040717 ============ LP4 DIFF to SE exit ============
684 22:58:20.044130 [ANA_INIT] <<<<<<<<<<<<<
685 22:58:20.047651 [Flow] Enable top DCM control >>>>>
686 22:58:20.051038 [Flow] Enable top DCM control <<<<<
687 22:58:20.054341 Enable DLL master slave shuffle
688 22:58:20.060899 ==============================================================
689 22:58:20.060988 Gating Mode config
690 22:58:20.068022 ==============================================================
691 22:58:20.068111 Config description:
692 22:58:20.077413 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
693 22:58:20.083802 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
694 22:58:20.090885 SELPH_MODE 0: By rank 1: By Phase
695 22:58:20.094177 ==============================================================
696 22:58:20.097149 GAT_TRACK_EN = 1
697 22:58:20.100396 RX_GATING_MODE = 2
698 22:58:20.103722 RX_GATING_TRACK_MODE = 2
699 22:58:20.107195 SELPH_MODE = 1
700 22:58:20.110852 PICG_EARLY_EN = 1
701 22:58:20.113837 VALID_LAT_VALUE = 1
702 22:58:20.120726 ==============================================================
703 22:58:20.123717 Enter into Gating configuration >>>>
704 22:58:20.127308 Exit from Gating configuration <<<<
705 22:58:20.127395 Enter into DVFS_PRE_config >>>>>
706 22:58:20.140705 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
707 22:58:20.143888 Exit from DVFS_PRE_config <<<<<
708 22:58:20.147399 Enter into PICG configuration >>>>
709 22:58:20.150812 Exit from PICG configuration <<<<
710 22:58:20.150898 [RX_INPUT] configuration >>>>>
711 22:58:20.153712 [RX_INPUT] configuration <<<<<
712 22:58:20.160547 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
713 22:58:20.164003 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
714 22:58:20.170924 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
715 22:58:20.177554 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
716 22:58:20.184300 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
717 22:58:20.191583 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
718 22:58:20.195471 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
719 22:58:20.199049 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
720 22:58:20.202563 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
721 22:58:20.206149 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
722 22:58:20.210069 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
723 22:58:20.213851 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
724 22:58:20.217013 ===================================
725 22:58:20.220693 LPDDR4 DRAM CONFIGURATION
726 22:58:20.224741 ===================================
727 22:58:20.224871 EX_ROW_EN[0] = 0x0
728 22:58:20.228030 EX_ROW_EN[1] = 0x0
729 22:58:20.228109 LP4Y_EN = 0x0
730 22:58:20.231654 WORK_FSP = 0x0
731 22:58:20.231739 WL = 0x2
732 22:58:20.235246 RL = 0x2
733 22:58:20.235331 BL = 0x2
734 22:58:20.239226 RPST = 0x0
735 22:58:20.239337 RD_PRE = 0x0
736 22:58:20.243179 WR_PRE = 0x1
737 22:58:20.243259 WR_PST = 0x0
738 22:58:20.246935 DBI_WR = 0x0
739 22:58:20.247031 DBI_RD = 0x0
740 22:58:20.247108 OTF = 0x1
741 22:58:20.250355 ===================================
742 22:58:20.253704 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
743 22:58:20.261411 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
744 22:58:20.264724 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
745 22:58:20.268545 ===================================
746 22:58:20.268651 LPDDR4 DRAM CONFIGURATION
747 22:58:20.271878 ===================================
748 22:58:20.275814 EX_ROW_EN[0] = 0x10
749 22:58:20.275899 EX_ROW_EN[1] = 0x0
750 22:58:20.279134 LP4Y_EN = 0x0
751 22:58:20.279210 WORK_FSP = 0x0
752 22:58:20.283103 WL = 0x2
753 22:58:20.283188 RL = 0x2
754 22:58:20.286856 BL = 0x2
755 22:58:20.286938 RPST = 0x0
756 22:58:20.290354 RD_PRE = 0x0
757 22:58:20.290426 WR_PRE = 0x1
758 22:58:20.294235 WR_PST = 0x0
759 22:58:20.294309 DBI_WR = 0x0
760 22:58:20.297559 DBI_RD = 0x0
761 22:58:20.297659 OTF = 0x1
762 22:58:20.301312 ===================================
763 22:58:20.308643 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
764 22:58:20.312446 nWR fixed to 40
765 22:58:20.312548 [ModeRegInit_LP4] CH0 RK0
766 22:58:20.315920 [ModeRegInit_LP4] CH0 RK1
767 22:58:20.319243 [ModeRegInit_LP4] CH1 RK0
768 22:58:20.319323 [ModeRegInit_LP4] CH1 RK1
769 22:58:20.323184 match AC timing 13
770 22:58:20.326829 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
771 22:58:20.330646 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
772 22:58:20.334161 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
773 22:58:20.341984 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
774 22:58:20.345375 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
775 22:58:20.345451 [EMI DOE] emi_dcm 0
776 22:58:20.349270 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
777 22:58:20.349347 ==
778 22:58:20.352996 Dram Type= 6, Freq= 0, CH_0, rank 0
779 22:58:20.356309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 22:58:20.360242 ==
781 22:58:20.364053 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 22:58:20.370612 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 22:58:20.379004 [CA 0] Center 38 (7~69) winsize 63
784 22:58:20.382304 [CA 1] Center 38 (7~69) winsize 63
785 22:58:20.385746 [CA 2] Center 35 (5~66) winsize 62
786 22:58:20.389028 [CA 3] Center 35 (5~66) winsize 62
787 22:58:20.392860 [CA 4] Center 34 (4~65) winsize 62
788 22:58:20.396317 [CA 5] Center 33 (3~64) winsize 62
789 22:58:20.396391
790 22:58:20.400204 [CmdBusTrainingLP45] Vref(ca) range 1: 32
791 22:58:20.400277
792 22:58:20.403907 [CATrainingPosCal] consider 1 rank data
793 22:58:20.408091 u2DelayCellTimex100 = 270/100 ps
794 22:58:20.411619 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
795 22:58:20.415089 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
796 22:58:20.418625 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
797 22:58:20.422656 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
798 22:58:20.425934 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
799 22:58:20.430150 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
800 22:58:20.430225
801 22:58:20.433333 CA PerBit enable=1, Macro0, CA PI delay=33
802 22:58:20.433411
803 22:58:20.437060 [CBTSetCACLKResult] CA Dly = 33
804 22:58:20.437157 CS Dly: 6 (0~37)
805 22:58:20.437222 ==
806 22:58:20.440944 Dram Type= 6, Freq= 0, CH_0, rank 1
807 22:58:20.444971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
808 22:58:20.445056 ==
809 22:58:20.448498 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
810 22:58:20.455654 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
811 22:58:20.465713 [CA 0] Center 38 (7~69) winsize 63
812 22:58:20.468979 [CA 1] Center 38 (7~69) winsize 63
813 22:58:20.472675 [CA 2] Center 36 (6~67) winsize 62
814 22:58:20.476694 [CA 3] Center 36 (5~67) winsize 63
815 22:58:20.480014 [CA 4] Center 35 (4~66) winsize 63
816 22:58:20.483442 [CA 5] Center 34 (4~65) winsize 62
817 22:58:20.483536
818 22:58:20.486768 [CmdBusTrainingLP45] Vref(ca) range 1: 34
819 22:58:20.486862
820 22:58:20.489782 [CATrainingPosCal] consider 2 rank data
821 22:58:20.493430 u2DelayCellTimex100 = 270/100 ps
822 22:58:20.496640 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
823 22:58:20.500082 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
824 22:58:20.503070 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
825 22:58:20.506507 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
826 22:58:20.509576 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
827 22:58:20.513401 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
828 22:58:20.516325
829 22:58:20.519840 CA PerBit enable=1, Macro0, CA PI delay=34
830 22:58:20.519912
831 22:58:20.523255 [CBTSetCACLKResult] CA Dly = 34
832 22:58:20.523329 CS Dly: 6 (0~38)
833 22:58:20.523393
834 22:58:20.526676 ----->DramcWriteLeveling(PI) begin...
835 22:58:20.526756 ==
836 22:58:20.529943 Dram Type= 6, Freq= 0, CH_0, rank 0
837 22:58:20.533232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
838 22:58:20.536418 ==
839 22:58:20.536523 Write leveling (Byte 0): 32 => 32
840 22:58:20.539767 Write leveling (Byte 1): 32 => 32
841 22:58:20.543046 DramcWriteLeveling(PI) end<-----
842 22:58:20.543150
843 22:58:20.543247 ==
844 22:58:20.546455 Dram Type= 6, Freq= 0, CH_0, rank 0
845 22:58:20.553194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
846 22:58:20.553276 ==
847 22:58:20.553344 [Gating] SW mode calibration
848 22:58:20.563732 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
849 22:58:20.567601 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
850 22:58:20.571363 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
851 22:58:20.574571 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
852 22:58:20.581089 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
853 22:58:20.584445 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 22:58:20.587904 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 22:58:20.594791 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 22:58:20.598000 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 22:58:20.601300 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 22:58:20.604790 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 22:58:20.611475 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 22:58:20.614629 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 22:58:20.618091 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 22:58:20.624377 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 22:58:20.627779 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 22:58:20.631249 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 22:58:20.637706 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 22:58:20.641077 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 22:58:20.644466 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
868 22:58:20.651280 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
869 22:58:20.654329 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 22:58:20.657763 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 22:58:20.664461 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 22:58:20.667702 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 22:58:20.671111 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 22:58:20.677820 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 22:58:20.681066 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
876 22:58:20.684327 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
877 22:58:20.691233 0 9 12 | B1->B0 | 2e2d 3434 | 1 1 | (1 1) (1 1)
878 22:58:20.694649 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 22:58:20.697580 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 22:58:20.704113 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 22:58:20.707737 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 22:58:20.711116 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
883 22:58:20.717787 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
884 22:58:20.720867 0 10 8 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
885 22:58:20.724230 0 10 12 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
886 22:58:20.727683 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 22:58:20.734640 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 22:58:20.737457 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 22:58:20.741086 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 22:58:20.747547 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 22:58:20.750777 0 11 4 | B1->B0 | 2323 3636 | 0 0 | (0 0) (1 1)
892 22:58:20.754115 0 11 8 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
893 22:58:20.760839 0 11 12 | B1->B0 | 3f3e 4646 | 1 0 | (0 0) (0 0)
894 22:58:20.764233 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 22:58:20.767550 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 22:58:20.774196 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 22:58:20.777658 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 22:58:20.781147 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
899 22:58:20.787554 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
900 22:58:20.790932 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
901 22:58:20.794247 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 22:58:20.800670 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 22:58:20.803990 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 22:58:20.807247 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 22:58:20.813876 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 22:58:20.817324 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 22:58:20.820551 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 22:58:20.827286 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 22:58:20.830736 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 22:58:20.834134 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 22:58:20.840578 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 22:58:20.844241 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 22:58:20.847578 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 22:58:20.853833 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 22:58:20.857246 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
916 22:58:20.860683 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
917 22:58:20.864037 Total UI for P1: 0, mck2ui 16
918 22:58:20.867019 best dqsien dly found for B0: ( 0, 14, 4)
919 22:58:20.870606 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
920 22:58:20.873836 Total UI for P1: 0, mck2ui 16
921 22:58:20.877047 best dqsien dly found for B1: ( 0, 14, 8)
922 22:58:20.880424 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
923 22:58:20.887054 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
924 22:58:20.887169
925 22:58:20.890387 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
926 22:58:20.893777 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
927 22:58:20.897086 [Gating] SW calibration Done
928 22:58:20.897159 ==
929 22:58:20.900108 Dram Type= 6, Freq= 0, CH_0, rank 0
930 22:58:20.903584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 22:58:20.903656 ==
932 22:58:20.903719 RX Vref Scan: 0
933 22:58:20.903787
934 22:58:20.907072 RX Vref 0 -> 0, step: 1
935 22:58:20.907173
936 22:58:20.910377 RX Delay -130 -> 252, step: 16
937 22:58:20.913946 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
938 22:58:20.917277 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
939 22:58:20.923700 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
940 22:58:20.926963 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
941 22:58:20.930498 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
942 22:58:20.933772 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
943 22:58:20.937221 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
944 22:58:20.943835 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
945 22:58:20.947200 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
946 22:58:20.950619 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
947 22:58:20.954055 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
948 22:58:20.957013 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
949 22:58:20.963596 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
950 22:58:20.967349 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
951 22:58:20.970559 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
952 22:58:20.973520 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
953 22:58:20.973600 ==
954 22:58:20.977426 Dram Type= 6, Freq= 0, CH_0, rank 0
955 22:58:20.980542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
956 22:58:20.983931 ==
957 22:58:20.984005 DQS Delay:
958 22:58:20.984069 DQS0 = 0, DQS1 = 0
959 22:58:20.987260 DQM Delay:
960 22:58:20.987367 DQM0 = 93, DQM1 = 81
961 22:58:20.990193 DQ Delay:
962 22:58:20.993896 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =93
963 22:58:20.997343 DQ4 =93, DQ5 =77, DQ6 =109, DQ7 =101
964 22:58:20.997431 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
965 22:58:21.003651 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
966 22:58:21.003739
967 22:58:21.003801
968 22:58:21.003860 ==
969 22:58:21.007114 Dram Type= 6, Freq= 0, CH_0, rank 0
970 22:58:21.010501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 22:58:21.010574 ==
972 22:58:21.010638
973 22:58:21.010698
974 22:58:21.013713 TX Vref Scan disable
975 22:58:21.013784 == TX Byte 0 ==
976 22:58:21.020611 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
977 22:58:21.023884 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
978 22:58:21.023985 == TX Byte 1 ==
979 22:58:21.030186 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
980 22:58:21.033955 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
981 22:58:21.034083 ==
982 22:58:21.036807 Dram Type= 6, Freq= 0, CH_0, rank 0
983 22:58:21.040277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
984 22:58:21.040386 ==
985 22:58:21.054086 TX Vref=22, minBit 6, minWin=27, winSum=440
986 22:58:21.057425 TX Vref=24, minBit 8, minWin=27, winSum=446
987 22:58:21.060740 TX Vref=26, minBit 8, minWin=27, winSum=449
988 22:58:21.064266 TX Vref=28, minBit 8, minWin=27, winSum=455
989 22:58:21.067178 TX Vref=30, minBit 5, minWin=28, winSum=460
990 22:58:21.073770 TX Vref=32, minBit 10, minWin=27, winSum=452
991 22:58:21.077254 [TxChooseVref] Worse bit 5, Min win 28, Win sum 460, Final Vref 30
992 22:58:21.077372
993 22:58:21.080339 Final TX Range 1 Vref 30
994 22:58:21.080475
995 22:58:21.080581 ==
996 22:58:21.083666 Dram Type= 6, Freq= 0, CH_0, rank 0
997 22:58:21.086806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
998 22:58:21.090316 ==
999 22:58:21.090427
1000 22:58:21.090532
1001 22:58:21.090632 TX Vref Scan disable
1002 22:58:21.093672 == TX Byte 0 ==
1003 22:58:21.097449 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1004 22:58:21.104116 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1005 22:58:21.104247 == TX Byte 1 ==
1006 22:58:21.107492 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1007 22:58:21.110399 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1008 22:58:21.113820
1009 22:58:21.113927 [DATLAT]
1010 22:58:21.114039 Freq=800, CH0 RK0
1011 22:58:21.114136
1012 22:58:21.117210 DATLAT Default: 0xa
1013 22:58:21.117328 0, 0xFFFF, sum = 0
1014 22:58:21.120508 1, 0xFFFF, sum = 0
1015 22:58:21.120618 2, 0xFFFF, sum = 0
1016 22:58:21.123593 3, 0xFFFF, sum = 0
1017 22:58:21.127078 4, 0xFFFF, sum = 0
1018 22:58:21.127191 5, 0xFFFF, sum = 0
1019 22:58:21.130503 6, 0xFFFF, sum = 0
1020 22:58:21.130611 7, 0xFFFF, sum = 0
1021 22:58:21.133842 8, 0xFFFF, sum = 0
1022 22:58:21.133963 9, 0x0, sum = 1
1023 22:58:21.134067 10, 0x0, sum = 2
1024 22:58:21.137155 11, 0x0, sum = 3
1025 22:58:21.137280 12, 0x0, sum = 4
1026 22:58:21.140528 best_step = 10
1027 22:58:21.140637
1028 22:58:21.140733 ==
1029 22:58:21.144077 Dram Type= 6, Freq= 0, CH_0, rank 0
1030 22:58:21.147406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1031 22:58:21.147518 ==
1032 22:58:21.150796 RX Vref Scan: 1
1033 22:58:21.150905
1034 22:58:21.151005 Set Vref Range= 32 -> 127
1035 22:58:21.151097
1036 22:58:21.153788 RX Vref 32 -> 127, step: 1
1037 22:58:21.153893
1038 22:58:21.157428 RX Delay -95 -> 252, step: 8
1039 22:58:21.157532
1040 22:58:21.160512 Set Vref, RX VrefLevel [Byte0]: 32
1041 22:58:21.163789 [Byte1]: 32
1042 22:58:21.163899
1043 22:58:21.167364 Set Vref, RX VrefLevel [Byte0]: 33
1044 22:58:21.170648 [Byte1]: 33
1045 22:58:21.174123
1046 22:58:21.174230 Set Vref, RX VrefLevel [Byte0]: 34
1047 22:58:21.177533 [Byte1]: 34
1048 22:58:21.182167
1049 22:58:21.182278 Set Vref, RX VrefLevel [Byte0]: 35
1050 22:58:21.185103 [Byte1]: 35
1051 22:58:21.189260
1052 22:58:21.189381 Set Vref, RX VrefLevel [Byte0]: 36
1053 22:58:21.192741 [Byte1]: 36
1054 22:58:21.197222
1055 22:58:21.197340 Set Vref, RX VrefLevel [Byte0]: 37
1056 22:58:21.200276 [Byte1]: 37
1057 22:58:21.204684
1058 22:58:21.204810 Set Vref, RX VrefLevel [Byte0]: 38
1059 22:58:21.208074 [Byte1]: 38
1060 22:58:21.212110
1061 22:58:21.212241 Set Vref, RX VrefLevel [Byte0]: 39
1062 22:58:21.215695 [Byte1]: 39
1063 22:58:21.220141
1064 22:58:21.220257 Set Vref, RX VrefLevel [Byte0]: 40
1065 22:58:21.223412 [Byte1]: 40
1066 22:58:21.227556
1067 22:58:21.227676 Set Vref, RX VrefLevel [Byte0]: 41
1068 22:58:21.231044 [Byte1]: 41
1069 22:58:21.235467
1070 22:58:21.235593 Set Vref, RX VrefLevel [Byte0]: 42
1071 22:58:21.238748 [Byte1]: 42
1072 22:58:21.243177
1073 22:58:21.243296 Set Vref, RX VrefLevel [Byte0]: 43
1074 22:58:21.246089 [Byte1]: 43
1075 22:58:21.250067
1076 22:58:21.250175 Set Vref, RX VrefLevel [Byte0]: 44
1077 22:58:21.254069 [Byte1]: 44
1078 22:58:21.258056
1079 22:58:21.258144 Set Vref, RX VrefLevel [Byte0]: 45
1080 22:58:21.261556 [Byte1]: 45
1081 22:58:21.265210
1082 22:58:21.265298 Set Vref, RX VrefLevel [Byte0]: 46
1083 22:58:21.268539 [Byte1]: 46
1084 22:58:21.273092
1085 22:58:21.273175 Set Vref, RX VrefLevel [Byte0]: 47
1086 22:58:21.276462 [Byte1]: 47
1087 22:58:21.280799
1088 22:58:21.280882 Set Vref, RX VrefLevel [Byte0]: 48
1089 22:58:21.283756 [Byte1]: 48
1090 22:58:21.288028
1091 22:58:21.288115 Set Vref, RX VrefLevel [Byte0]: 49
1092 22:58:21.291648 [Byte1]: 49
1093 22:58:21.296065
1094 22:58:21.296151 Set Vref, RX VrefLevel [Byte0]: 50
1095 22:58:21.299144 [Byte1]: 50
1096 22:58:21.303450
1097 22:58:21.303536 Set Vref, RX VrefLevel [Byte0]: 51
1098 22:58:21.306481 [Byte1]: 51
1099 22:58:21.311266
1100 22:58:21.311352 Set Vref, RX VrefLevel [Byte0]: 52
1101 22:58:21.314596 [Byte1]: 52
1102 22:58:21.318653
1103 22:58:21.318743 Set Vref, RX VrefLevel [Byte0]: 53
1104 22:58:21.322116 [Byte1]: 53
1105 22:58:21.326434
1106 22:58:21.326520 Set Vref, RX VrefLevel [Byte0]: 54
1107 22:58:21.329330 [Byte1]: 54
1108 22:58:21.333969
1109 22:58:21.334055 Set Vref, RX VrefLevel [Byte0]: 55
1110 22:58:21.337436 [Byte1]: 55
1111 22:58:21.341713
1112 22:58:21.341828 Set Vref, RX VrefLevel [Byte0]: 56
1113 22:58:21.344523 [Byte1]: 56
1114 22:58:21.349006
1115 22:58:21.349092 Set Vref, RX VrefLevel [Byte0]: 57
1116 22:58:21.352273 [Byte1]: 57
1117 22:58:21.356590
1118 22:58:21.356677 Set Vref, RX VrefLevel [Byte0]: 58
1119 22:58:21.360011 [Byte1]: 58
1120 22:58:21.364309
1121 22:58:21.364395 Set Vref, RX VrefLevel [Byte0]: 59
1122 22:58:21.367619 [Byte1]: 59
1123 22:58:21.372048
1124 22:58:21.372131 Set Vref, RX VrefLevel [Byte0]: 60
1125 22:58:21.375047 [Byte1]: 60
1126 22:58:21.379194
1127 22:58:21.379278 Set Vref, RX VrefLevel [Byte0]: 61
1128 22:58:21.385966 [Byte1]: 61
1129 22:58:21.386049
1130 22:58:21.389350 Set Vref, RX VrefLevel [Byte0]: 62
1131 22:58:21.392784 [Byte1]: 62
1132 22:58:21.392868
1133 22:58:21.396199 Set Vref, RX VrefLevel [Byte0]: 63
1134 22:58:21.399464 [Byte1]: 63
1135 22:58:21.399583
1136 22:58:21.402618 Set Vref, RX VrefLevel [Byte0]: 64
1137 22:58:21.405760 [Byte1]: 64
1138 22:58:21.410055
1139 22:58:21.410139 Set Vref, RX VrefLevel [Byte0]: 65
1140 22:58:21.413222 [Byte1]: 65
1141 22:58:21.417631
1142 22:58:21.417715 Set Vref, RX VrefLevel [Byte0]: 66
1143 22:58:21.420627 [Byte1]: 66
1144 22:58:21.425084
1145 22:58:21.425205 Set Vref, RX VrefLevel [Byte0]: 67
1146 22:58:21.428475 [Byte1]: 67
1147 22:58:21.432703
1148 22:58:21.432813 Set Vref, RX VrefLevel [Byte0]: 68
1149 22:58:21.436075 [Byte1]: 68
1150 22:58:21.440470
1151 22:58:21.440583 Set Vref, RX VrefLevel [Byte0]: 69
1152 22:58:21.443255 [Byte1]: 69
1153 22:58:21.448058
1154 22:58:21.448143 Set Vref, RX VrefLevel [Byte0]: 70
1155 22:58:21.451023 [Byte1]: 70
1156 22:58:21.455612
1157 22:58:21.455697 Set Vref, RX VrefLevel [Byte0]: 71
1158 22:58:21.458881 [Byte1]: 71
1159 22:58:21.462813
1160 22:58:21.462889 Set Vref, RX VrefLevel [Byte0]: 72
1161 22:58:21.466313 [Byte1]: 72
1162 22:58:21.470460
1163 22:58:21.470545 Set Vref, RX VrefLevel [Byte0]: 73
1164 22:58:21.473830 [Byte1]: 73
1165 22:58:21.478188
1166 22:58:21.478267 Set Vref, RX VrefLevel [Byte0]: 74
1167 22:58:21.481714 [Byte1]: 74
1168 22:58:21.485642
1169 22:58:21.485750 Set Vref, RX VrefLevel [Byte0]: 75
1170 22:58:21.489002 [Byte1]: 75
1171 22:58:21.493444
1172 22:58:21.493555 Set Vref, RX VrefLevel [Byte0]: 76
1173 22:58:21.496841 [Byte1]: 76
1174 22:58:21.501086
1175 22:58:21.501167 Final RX Vref Byte 0 = 60 to rank0
1176 22:58:21.504160 Final RX Vref Byte 1 = 62 to rank0
1177 22:58:21.507325 Final RX Vref Byte 0 = 60 to rank1
1178 22:58:21.510737 Final RX Vref Byte 1 = 62 to rank1==
1179 22:58:21.514331 Dram Type= 6, Freq= 0, CH_0, rank 0
1180 22:58:21.521073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1181 22:58:21.521160 ==
1182 22:58:21.521228 DQS Delay:
1183 22:58:21.521291 DQS0 = 0, DQS1 = 0
1184 22:58:21.524015 DQM Delay:
1185 22:58:21.524090 DQM0 = 93, DQM1 = 83
1186 22:58:21.527447 DQ Delay:
1187 22:58:21.530888 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1188 22:58:21.534342 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1189 22:58:21.537249 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1190 22:58:21.541004 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =92
1191 22:58:21.541104
1192 22:58:21.541173
1193 22:58:21.547380 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c37, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1194 22:58:21.550564 CH0 RK0: MR19=606, MR18=3C37
1195 22:58:21.557410 CH0_RK0: MR19=0x606, MR18=0x3C37, DQSOSC=394, MR23=63, INC=95, DEC=63
1196 22:58:21.557505
1197 22:58:21.560326 ----->DramcWriteLeveling(PI) begin...
1198 22:58:21.560402 ==
1199 22:58:21.563720 Dram Type= 6, Freq= 0, CH_0, rank 1
1200 22:58:21.567605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1201 22:58:21.567718 ==
1202 22:58:21.570498 Write leveling (Byte 0): 31 => 31
1203 22:58:21.573767 Write leveling (Byte 1): 29 => 29
1204 22:58:21.577195 DramcWriteLeveling(PI) end<-----
1205 22:58:21.577273
1206 22:58:21.577336 ==
1207 22:58:21.580643 Dram Type= 6, Freq= 0, CH_0, rank 1
1208 22:58:21.584070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1209 22:58:21.584146 ==
1210 22:58:21.587097 [Gating] SW mode calibration
1211 22:58:21.593828 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1212 22:58:21.600267 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1213 22:58:21.603653 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1214 22:58:21.610650 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1215 22:58:21.613982 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 22:58:21.617082 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 22:58:21.620385 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 22:58:21.626808 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 22:58:21.671238 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 22:58:21.671601 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 22:58:21.671709 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 22:58:21.671810 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 22:58:21.672180 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 22:58:21.672461 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 22:58:21.672567 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 22:58:21.672671 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 22:58:21.672780 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 22:58:21.672874 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 22:58:21.715247 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 22:58:21.715747 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1231 22:58:21.715871 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 22:58:21.716170 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 22:58:21.716271 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 22:58:21.716398 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 22:58:21.716774 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 22:58:21.716861 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 22:58:21.717151 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 22:58:21.717271 0 9 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1239 22:58:21.733453 0 9 8 | B1->B0 | 2e2e 3232 | 1 1 | (1 1) (1 1)
1240 22:58:21.733809 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 22:58:21.733946 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 22:58:21.734053 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 22:58:21.737347 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 22:58:21.740458 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 22:58:21.743982 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 22:58:21.750201 0 10 4 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (0 0)
1247 22:58:21.753647 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (1 0)
1248 22:58:21.757111 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 22:58:21.763610 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 22:58:21.767061 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 22:58:21.770684 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 22:58:21.777006 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 22:58:21.780340 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 22:58:21.783845 0 11 4 | B1->B0 | 2424 2e2d | 0 1 | (0 0) (0 0)
1255 22:58:21.790671 0 11 8 | B1->B0 | 3939 4544 | 0 1 | (0 0) (0 0)
1256 22:58:21.793652 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 22:58:21.797185 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 22:58:21.803717 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 22:58:21.807185 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 22:58:21.811196 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 22:58:21.814674 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1262 22:58:21.821184 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1263 22:58:21.824630 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 22:58:21.828047 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 22:58:21.831491 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 22:58:21.838465 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 22:58:21.842128 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 22:58:21.845078 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 22:58:21.851925 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 22:58:21.855266 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 22:58:21.858599 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 22:58:21.865171 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 22:58:21.868289 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 22:58:21.871616 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 22:58:21.878422 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 22:58:21.881782 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 22:58:21.885367 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 22:58:21.888649 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1279 22:58:21.891978 Total UI for P1: 0, mck2ui 16
1280 22:58:21.894998 best dqsien dly found for B0: ( 0, 14, 2)
1281 22:58:21.901906 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1282 22:58:21.905435 Total UI for P1: 0, mck2ui 16
1283 22:58:21.908393 best dqsien dly found for B1: ( 0, 14, 4)
1284 22:58:21.911850 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1285 22:58:21.915227 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1286 22:58:21.915331
1287 22:58:21.918285 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1288 22:58:21.921639 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1289 22:58:21.925142 [Gating] SW calibration Done
1290 22:58:21.925218 ==
1291 22:58:21.928489 Dram Type= 6, Freq= 0, CH_0, rank 1
1292 22:58:21.931861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1293 22:58:21.931943 ==
1294 22:58:21.934833 RX Vref Scan: 0
1295 22:58:21.934912
1296 22:58:21.934977 RX Vref 0 -> 0, step: 1
1297 22:58:21.935044
1298 22:58:21.938292 RX Delay -130 -> 252, step: 16
1299 22:58:21.944861 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1300 22:58:21.948405 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1301 22:58:21.951776 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1302 22:58:21.955011 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1303 22:58:21.958101 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1304 22:58:21.961693 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1305 22:58:21.968245 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1306 22:58:21.971537 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1307 22:58:21.975052 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1308 22:58:21.978180 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1309 22:58:21.981746 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1310 22:58:21.988230 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1311 22:58:21.991549 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1312 22:58:21.995318 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1313 22:58:21.998296 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1314 22:58:22.004818 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1315 22:58:22.004945 ==
1316 22:58:22.008525 Dram Type= 6, Freq= 0, CH_0, rank 1
1317 22:58:22.011559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1318 22:58:22.011671 ==
1319 22:58:22.011791 DQS Delay:
1320 22:58:22.014963 DQS0 = 0, DQS1 = 0
1321 22:58:22.015077 DQM Delay:
1322 22:58:22.018065 DQM0 = 88, DQM1 = 80
1323 22:58:22.018171 DQ Delay:
1324 22:58:22.021708 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1325 22:58:22.025112 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
1326 22:58:22.028215 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1327 22:58:22.031651 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
1328 22:58:22.031760
1329 22:58:22.031865
1330 22:58:22.031967 ==
1331 22:58:22.034580 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 22:58:22.038108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 22:58:22.038229 ==
1334 22:58:22.038337
1335 22:58:22.041336
1336 22:58:22.041469 TX Vref Scan disable
1337 22:58:22.044892 == TX Byte 0 ==
1338 22:58:22.048175 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1339 22:58:22.051633 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1340 22:58:22.054849 == TX Byte 1 ==
1341 22:58:22.058145 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1342 22:58:22.061586 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1343 22:58:22.061693 ==
1344 22:58:22.064850 Dram Type= 6, Freq= 0, CH_0, rank 1
1345 22:58:22.071283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1346 22:58:22.071394 ==
1347 22:58:22.083233 TX Vref=22, minBit 8, minWin=27, winSum=446
1348 22:58:22.086803 TX Vref=24, minBit 8, minWin=27, winSum=450
1349 22:58:22.089784 TX Vref=26, minBit 8, minWin=27, winSum=451
1350 22:58:22.093218 TX Vref=28, minBit 8, minWin=27, winSum=457
1351 22:58:22.096506 TX Vref=30, minBit 8, minWin=27, winSum=455
1352 22:58:22.099801 TX Vref=32, minBit 6, minWin=28, winSum=457
1353 22:58:22.106665 [TxChooseVref] Worse bit 6, Min win 28, Win sum 457, Final Vref 32
1354 22:58:22.106779
1355 22:58:22.110060 Final TX Range 1 Vref 32
1356 22:58:22.110136
1357 22:58:22.110201 ==
1358 22:58:22.113009 Dram Type= 6, Freq= 0, CH_0, rank 1
1359 22:58:22.116404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1360 22:58:22.116509 ==
1361 22:58:22.116606
1362 22:58:22.120020
1363 22:58:22.120123 TX Vref Scan disable
1364 22:58:22.123030 == TX Byte 0 ==
1365 22:58:22.126508 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1366 22:58:22.132869 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1367 22:58:22.132972 == TX Byte 1 ==
1368 22:58:22.136269 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1369 22:58:22.143047 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1370 22:58:22.143159
1371 22:58:22.143227 [DATLAT]
1372 22:58:22.143301 Freq=800, CH0 RK1
1373 22:58:22.143363
1374 22:58:22.146434 DATLAT Default: 0xa
1375 22:58:22.146518 0, 0xFFFF, sum = 0
1376 22:58:22.149726 1, 0xFFFF, sum = 0
1377 22:58:22.149809 2, 0xFFFF, sum = 0
1378 22:58:22.153343 3, 0xFFFF, sum = 0
1379 22:58:22.156391 4, 0xFFFF, sum = 0
1380 22:58:22.156503 5, 0xFFFF, sum = 0
1381 22:58:22.159651 6, 0xFFFF, sum = 0
1382 22:58:22.159735 7, 0xFFFF, sum = 0
1383 22:58:22.163422 8, 0xFFFF, sum = 0
1384 22:58:22.163502 9, 0x0, sum = 1
1385 22:58:22.163568 10, 0x0, sum = 2
1386 22:58:22.166643 11, 0x0, sum = 3
1387 22:58:22.166727 12, 0x0, sum = 4
1388 22:58:22.169807 best_step = 10
1389 22:58:22.169891
1390 22:58:22.169957 ==
1391 22:58:22.173110 Dram Type= 6, Freq= 0, CH_0, rank 1
1392 22:58:22.176380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1393 22:58:22.176483 ==
1394 22:58:22.179462 RX Vref Scan: 0
1395 22:58:22.179540
1396 22:58:22.179603 RX Vref 0 -> 0, step: 1
1397 22:58:22.182665
1398 22:58:22.182742 RX Delay -79 -> 252, step: 8
1399 22:58:22.190075 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1400 22:58:22.193019 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1401 22:58:22.196442 iDelay=209, Bit 2, Center 92 (-15 ~ 200) 216
1402 22:58:22.199880 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1403 22:58:22.203090 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1404 22:58:22.209616 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1405 22:58:22.213084 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1406 22:58:22.216531 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1407 22:58:22.219943 iDelay=209, Bit 8, Center 76 (-23 ~ 176) 200
1408 22:58:22.222858 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1409 22:58:22.229514 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1410 22:58:22.232929 iDelay=209, Bit 11, Center 76 (-23 ~ 176) 200
1411 22:58:22.236535 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1412 22:58:22.239618 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1413 22:58:22.246212 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1414 22:58:22.249613 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1415 22:58:22.249694 ==
1416 22:58:22.252564 Dram Type= 6, Freq= 0, CH_0, rank 1
1417 22:58:22.256398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1418 22:58:22.256514 ==
1419 22:58:22.256622 DQS Delay:
1420 22:58:22.259747 DQS0 = 0, DQS1 = 0
1421 22:58:22.259833 DQM Delay:
1422 22:58:22.262552 DQM0 = 91, DQM1 = 81
1423 22:58:22.262641 DQ Delay:
1424 22:58:22.266338 DQ0 =88, DQ1 =92, DQ2 =92, DQ3 =84
1425 22:58:22.269256 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1426 22:58:22.272599 DQ8 =76, DQ9 =72, DQ10 =80, DQ11 =76
1427 22:58:22.275858 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1428 22:58:22.275937
1429 22:58:22.276022
1430 22:58:22.285819 [DQSOSCAuto] RK1, (LSB)MR18= 0x411c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
1431 22:58:22.285909 CH0 RK1: MR19=606, MR18=411C
1432 22:58:22.292582 CH0_RK1: MR19=0x606, MR18=0x411C, DQSOSC=393, MR23=63, INC=95, DEC=63
1433 22:58:22.296095 [RxdqsGatingPostProcess] freq 800
1434 22:58:22.302601 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1435 22:58:22.305898 Pre-setting of DQS Precalculation
1436 22:58:22.309237 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1437 22:58:22.309324 ==
1438 22:58:22.312585 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 22:58:22.319019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 22:58:22.319107 ==
1441 22:58:22.322381 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1442 22:58:22.329149 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1443 22:58:22.338488 [CA 0] Center 36 (6~67) winsize 62
1444 22:58:22.341882 [CA 1] Center 36 (6~67) winsize 62
1445 22:58:22.344831 [CA 2] Center 34 (4~65) winsize 62
1446 22:58:22.348180 [CA 3] Center 34 (3~65) winsize 63
1447 22:58:22.351590 [CA 4] Center 34 (4~65) winsize 62
1448 22:58:22.355102 [CA 5] Center 33 (3~64) winsize 62
1449 22:58:22.355187
1450 22:58:22.358643 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1451 22:58:22.358728
1452 22:58:22.361772 [CATrainingPosCal] consider 1 rank data
1453 22:58:22.364933 u2DelayCellTimex100 = 270/100 ps
1454 22:58:22.368227 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1455 22:58:22.371624 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1456 22:58:22.378464 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1457 22:58:22.381302 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1458 22:58:22.384973 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1459 22:58:22.388297 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1460 22:58:22.388407
1461 22:58:22.391477 CA PerBit enable=1, Macro0, CA PI delay=33
1462 22:58:22.391589
1463 22:58:22.394966 [CBTSetCACLKResult] CA Dly = 33
1464 22:58:22.395081 CS Dly: 5 (0~36)
1465 22:58:22.397918 ==
1466 22:58:22.398030 Dram Type= 6, Freq= 0, CH_1, rank 1
1467 22:58:22.404667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1468 22:58:22.404791 ==
1469 22:58:22.408253 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1470 22:58:22.414905 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1471 22:58:22.424238 [CA 0] Center 37 (7~67) winsize 61
1472 22:58:22.427762 [CA 1] Center 36 (6~67) winsize 62
1473 22:58:22.431259 [CA 2] Center 35 (4~66) winsize 63
1474 22:58:22.434257 [CA 3] Center 34 (4~65) winsize 62
1475 22:58:22.437753 [CA 4] Center 34 (4~65) winsize 62
1476 22:58:22.441157 [CA 5] Center 34 (4~65) winsize 62
1477 22:58:22.441266
1478 22:58:22.444560 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1479 22:58:22.444670
1480 22:58:22.447833 [CATrainingPosCal] consider 2 rank data
1481 22:58:22.451083 u2DelayCellTimex100 = 270/100 ps
1482 22:58:22.454601 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1483 22:58:22.457579 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1484 22:58:22.464461 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1485 22:58:22.467761 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1486 22:58:22.471420 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1487 22:58:22.475301 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1488 22:58:22.475388
1489 22:58:22.478752 CA PerBit enable=1, Macro0, CA PI delay=34
1490 22:58:22.478837
1491 22:58:22.482574 [CBTSetCACLKResult] CA Dly = 34
1492 22:58:22.482660 CS Dly: 6 (0~38)
1493 22:58:22.482727
1494 22:58:22.486302 ----->DramcWriteLeveling(PI) begin...
1495 22:58:22.486388 ==
1496 22:58:22.489980 Dram Type= 6, Freq= 0, CH_1, rank 0
1497 22:58:22.493698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1498 22:58:22.493808 ==
1499 22:58:22.497273 Write leveling (Byte 0): 27 => 27
1500 22:58:22.501187 Write leveling (Byte 1): 29 => 29
1501 22:58:22.504967 DramcWriteLeveling(PI) end<-----
1502 22:58:22.505076
1503 22:58:22.505184 ==
1504 22:58:22.505287 Dram Type= 6, Freq= 0, CH_1, rank 0
1505 22:58:22.511664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1506 22:58:22.511773 ==
1507 22:58:22.514977 [Gating] SW mode calibration
1508 22:58:22.521839 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1509 22:58:22.525288 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1510 22:58:22.531626 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1511 22:58:22.535047 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1512 22:58:22.538644 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 22:58:22.545063 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 22:58:22.548511 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 22:58:22.551931 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 22:58:22.555087 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 22:58:22.561539 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 22:58:22.564952 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 22:58:22.568309 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 22:58:22.575219 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 22:58:22.578556 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 22:58:22.581527 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 22:58:22.588513 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 22:58:22.591581 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 22:58:22.594919 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1526 22:58:22.601505 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1527 22:58:22.605120 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 22:58:22.608126 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 22:58:22.614729 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 22:58:22.618278 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 22:58:22.621569 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 22:58:22.627976 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 22:58:22.631473 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 22:58:22.634924 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 22:58:22.641617 0 9 4 | B1->B0 | 2424 2a2a | 0 1 | (0 0) (0 0)
1536 22:58:22.644560 0 9 8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1537 22:58:22.647950 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 22:58:22.654853 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 22:58:22.657989 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 22:58:22.661457 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 22:58:22.668323 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 22:58:22.671352 0 10 0 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
1543 22:58:22.674902 0 10 4 | B1->B0 | 2f2f 2b2b | 1 1 | (1 0) (1 0)
1544 22:58:22.678308 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1545 22:58:22.684682 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 22:58:22.688191 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 22:58:22.691301 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 22:58:22.697886 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 22:58:22.701093 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 22:58:22.704330 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 22:58:22.711479 0 11 4 | B1->B0 | 3434 3b3b | 0 0 | (1 1) (0 0)
1552 22:58:22.714791 0 11 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1553 22:58:22.718117 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 22:58:22.724559 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 22:58:22.727891 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 22:58:22.731145 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 22:58:22.737636 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 22:58:22.741153 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 22:58:22.744602 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1560 22:58:22.751306 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1561 22:58:22.754234 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 22:58:22.757719 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 22:58:22.764269 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 22:58:22.767658 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 22:58:22.771055 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 22:58:22.777594 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 22:58:22.781124 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 22:58:22.784432 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 22:58:22.790780 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 22:58:22.794299 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 22:58:22.797769 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 22:58:22.804539 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 22:58:22.807757 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 22:58:22.810660 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 22:58:22.814727 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1576 22:58:22.821237 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1577 22:58:22.824033 Total UI for P1: 0, mck2ui 16
1578 22:58:22.827568 best dqsien dly found for B0: ( 0, 14, 4)
1579 22:58:22.830943 Total UI for P1: 0, mck2ui 16
1580 22:58:22.834321 best dqsien dly found for B1: ( 0, 14, 4)
1581 22:58:22.837298 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1582 22:58:22.840758 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1583 22:58:22.840848
1584 22:58:22.844380 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1585 22:58:22.847401 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1586 22:58:22.850994 [Gating] SW calibration Done
1587 22:58:22.851087 ==
1588 22:58:22.854058 Dram Type= 6, Freq= 0, CH_1, rank 0
1589 22:58:22.857202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1590 22:58:22.857284 ==
1591 22:58:22.860650 RX Vref Scan: 0
1592 22:58:22.860761
1593 22:58:22.860923 RX Vref 0 -> 0, step: 1
1594 22:58:22.860989
1595 22:58:22.864178 RX Delay -130 -> 252, step: 16
1596 22:58:22.871073 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1597 22:58:22.873919 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1598 22:58:22.877443 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1599 22:58:22.880486 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1600 22:58:22.883933 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1601 22:58:22.890706 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1602 22:58:22.893721 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1603 22:58:22.897215 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1604 22:58:22.900602 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1605 22:58:22.903850 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1606 22:58:22.910565 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1607 22:58:22.913702 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1608 22:58:22.917109 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1609 22:58:22.920639 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1610 22:58:22.923612 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1611 22:58:22.930704 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1612 22:58:22.930792 ==
1613 22:58:22.934094 Dram Type= 6, Freq= 0, CH_1, rank 0
1614 22:58:22.936997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1615 22:58:22.937084 ==
1616 22:58:22.937176 DQS Delay:
1617 22:58:22.940253 DQS0 = 0, DQS1 = 0
1618 22:58:22.940338 DQM Delay:
1619 22:58:22.943597 DQM0 = 89, DQM1 = 80
1620 22:58:22.943700 DQ Delay:
1621 22:58:22.946981 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1622 22:58:22.950483 DQ4 =93, DQ5 =101, DQ6 =101, DQ7 =85
1623 22:58:22.953764 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1624 22:58:22.957242 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1625 22:58:22.957327
1626 22:58:22.957392
1627 22:58:22.957454 ==
1628 22:58:22.960219 Dram Type= 6, Freq= 0, CH_1, rank 0
1629 22:58:22.963650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1630 22:58:22.967099 ==
1631 22:58:22.967183
1632 22:58:22.967250
1633 22:58:22.967311 TX Vref Scan disable
1634 22:58:22.970094 == TX Byte 0 ==
1635 22:58:22.973348 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1636 22:58:22.976861 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1637 22:58:22.980325 == TX Byte 1 ==
1638 22:58:22.983463 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1639 22:58:22.986722 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1640 22:58:22.990387 ==
1641 22:58:22.990469 Dram Type= 6, Freq= 0, CH_1, rank 0
1642 22:58:22.996659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1643 22:58:22.996784 ==
1644 22:58:23.009145 TX Vref=22, minBit 14, minWin=27, winSum=450
1645 22:58:23.012397 TX Vref=24, minBit 15, minWin=27, winSum=453
1646 22:58:23.015689 TX Vref=26, minBit 15, minWin=27, winSum=456
1647 22:58:23.018906 TX Vref=28, minBit 15, minWin=27, winSum=457
1648 22:58:23.022234 TX Vref=30, minBit 15, minWin=27, winSum=460
1649 22:58:23.028705 TX Vref=32, minBit 12, minWin=27, winSum=456
1650 22:58:23.032298 [TxChooseVref] Worse bit 15, Min win 27, Win sum 460, Final Vref 30
1651 22:58:23.032409
1652 22:58:23.035691 Final TX Range 1 Vref 30
1653 22:58:23.035805
1654 22:58:23.035920 ==
1655 22:58:23.039193 Dram Type= 6, Freq= 0, CH_1, rank 0
1656 22:58:23.042180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1657 22:58:23.045511 ==
1658 22:58:23.045621
1659 22:58:23.045692
1660 22:58:23.045756 TX Vref Scan disable
1661 22:58:23.049440 == TX Byte 0 ==
1662 22:58:23.052831 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1663 22:58:23.056399 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1664 22:58:23.059868 == TX Byte 1 ==
1665 22:58:23.063045 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1666 22:58:23.066667 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1667 22:58:23.066795
1668 22:58:23.069658 [DATLAT]
1669 22:58:23.069794 Freq=800, CH1 RK0
1670 22:58:23.069922
1671 22:58:23.073166 DATLAT Default: 0xa
1672 22:58:23.073283 0, 0xFFFF, sum = 0
1673 22:58:23.076553 1, 0xFFFF, sum = 0
1674 22:58:23.076685 2, 0xFFFF, sum = 0
1675 22:58:23.079686 3, 0xFFFF, sum = 0
1676 22:58:23.079817 4, 0xFFFF, sum = 0
1677 22:58:23.083175 5, 0xFFFF, sum = 0
1678 22:58:23.083284 6, 0xFFFF, sum = 0
1679 22:58:23.086614 7, 0xFFFF, sum = 0
1680 22:58:23.086721 8, 0xFFFF, sum = 0
1681 22:58:23.089613 9, 0x0, sum = 1
1682 22:58:23.089725 10, 0x0, sum = 2
1683 22:58:23.092985 11, 0x0, sum = 3
1684 22:58:23.093094 12, 0x0, sum = 4
1685 22:58:23.096349 best_step = 10
1686 22:58:23.096475
1687 22:58:23.096572 ==
1688 22:58:23.099571 Dram Type= 6, Freq= 0, CH_1, rank 0
1689 22:58:23.103161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1690 22:58:23.103258 ==
1691 22:58:23.106469 RX Vref Scan: 1
1692 22:58:23.106583
1693 22:58:23.106677 Set Vref Range= 32 -> 127
1694 22:58:23.106789
1695 22:58:23.109565 RX Vref 32 -> 127, step: 1
1696 22:58:23.109644
1697 22:58:23.112898 RX Delay -95 -> 252, step: 8
1698 22:58:23.112981
1699 22:58:23.116241 Set Vref, RX VrefLevel [Byte0]: 32
1700 22:58:23.119993 [Byte1]: 32
1701 22:58:23.120075
1702 22:58:23.122871 Set Vref, RX VrefLevel [Byte0]: 33
1703 22:58:23.126278 [Byte1]: 33
1704 22:58:23.129946
1705 22:58:23.130059 Set Vref, RX VrefLevel [Byte0]: 34
1706 22:58:23.132811 [Byte1]: 34
1707 22:58:23.137468
1708 22:58:23.137575 Set Vref, RX VrefLevel [Byte0]: 35
1709 22:58:23.140479 [Byte1]: 35
1710 22:58:23.145009
1711 22:58:23.145094 Set Vref, RX VrefLevel [Byte0]: 36
1712 22:58:23.148322 [Byte1]: 36
1713 22:58:23.152772
1714 22:58:23.152855 Set Vref, RX VrefLevel [Byte0]: 37
1715 22:58:23.155689 [Byte1]: 37
1716 22:58:23.160242
1717 22:58:23.163225 Set Vref, RX VrefLevel [Byte0]: 38
1718 22:58:23.163366 [Byte1]: 38
1719 22:58:23.167692
1720 22:58:23.167813 Set Vref, RX VrefLevel [Byte0]: 39
1721 22:58:23.170730 [Byte1]: 39
1722 22:58:23.175145
1723 22:58:23.175239 Set Vref, RX VrefLevel [Byte0]: 40
1724 22:58:23.178609 [Byte1]: 40
1725 22:58:23.182828
1726 22:58:23.182905 Set Vref, RX VrefLevel [Byte0]: 41
1727 22:58:23.186214 [Byte1]: 41
1728 22:58:23.190487
1729 22:58:23.190565 Set Vref, RX VrefLevel [Byte0]: 42
1730 22:58:23.193906 [Byte1]: 42
1731 22:58:23.198313
1732 22:58:23.198405 Set Vref, RX VrefLevel [Byte0]: 43
1733 22:58:23.201547 [Byte1]: 43
1734 22:58:23.205694
1735 22:58:23.205798 Set Vref, RX VrefLevel [Byte0]: 44
1736 22:58:23.208938 [Byte1]: 44
1737 22:58:23.213029
1738 22:58:23.213122 Set Vref, RX VrefLevel [Byte0]: 45
1739 22:58:23.216513 [Byte1]: 45
1740 22:58:23.220749
1741 22:58:23.220893 Set Vref, RX VrefLevel [Byte0]: 46
1742 22:58:23.224108 [Byte1]: 46
1743 22:58:23.228502
1744 22:58:23.228627 Set Vref, RX VrefLevel [Byte0]: 47
1745 22:58:23.231775 [Byte1]: 47
1746 22:58:23.236018
1747 22:58:23.236128 Set Vref, RX VrefLevel [Byte0]: 48
1748 22:58:23.239394 [Byte1]: 48
1749 22:58:23.243735
1750 22:58:23.243819 Set Vref, RX VrefLevel [Byte0]: 49
1751 22:58:23.247094 [Byte1]: 49
1752 22:58:23.251335
1753 22:58:23.251439 Set Vref, RX VrefLevel [Byte0]: 50
1754 22:58:23.254737 [Byte1]: 50
1755 22:58:23.258754
1756 22:58:23.261989 Set Vref, RX VrefLevel [Byte0]: 51
1757 22:58:23.265553 [Byte1]: 51
1758 22:58:23.265659
1759 22:58:23.268504 Set Vref, RX VrefLevel [Byte0]: 52
1760 22:58:23.272004 [Byte1]: 52
1761 22:58:23.272087
1762 22:58:23.275386 Set Vref, RX VrefLevel [Byte0]: 53
1763 22:58:23.278402 [Byte1]: 53
1764 22:58:23.278483
1765 22:58:23.282269 Set Vref, RX VrefLevel [Byte0]: 54
1766 22:58:23.285186 [Byte1]: 54
1767 22:58:23.289405
1768 22:58:23.289486 Set Vref, RX VrefLevel [Byte0]: 55
1769 22:58:23.292402 [Byte1]: 55
1770 22:58:23.296787
1771 22:58:23.296905 Set Vref, RX VrefLevel [Byte0]: 56
1772 22:58:23.300253 [Byte1]: 56
1773 22:58:23.304526
1774 22:58:23.304654 Set Vref, RX VrefLevel [Byte0]: 57
1775 22:58:23.307716 [Byte1]: 57
1776 22:58:23.312062
1777 22:58:23.312141 Set Vref, RX VrefLevel [Byte0]: 58
1778 22:58:23.315540 [Byte1]: 58
1779 22:58:23.319417
1780 22:58:23.319540 Set Vref, RX VrefLevel [Byte0]: 59
1781 22:58:23.323041 [Byte1]: 59
1782 22:58:23.327182
1783 22:58:23.327259 Set Vref, RX VrefLevel [Byte0]: 60
1784 22:58:23.330373 [Byte1]: 60
1785 22:58:23.334921
1786 22:58:23.335043 Set Vref, RX VrefLevel [Byte0]: 61
1787 22:58:23.338264 [Byte1]: 61
1788 22:58:23.342196
1789 22:58:23.342303 Set Vref, RX VrefLevel [Byte0]: 62
1790 22:58:23.345624 [Byte1]: 62
1791 22:58:23.349983
1792 22:58:23.350065 Set Vref, RX VrefLevel [Byte0]: 63
1793 22:58:23.353307 [Byte1]: 63
1794 22:58:23.357888
1795 22:58:23.357965 Set Vref, RX VrefLevel [Byte0]: 64
1796 22:58:23.360805 [Byte1]: 64
1797 22:58:23.365262
1798 22:58:23.365353 Set Vref, RX VrefLevel [Byte0]: 65
1799 22:58:23.368544 [Byte1]: 65
1800 22:58:23.372993
1801 22:58:23.373075 Set Vref, RX VrefLevel [Byte0]: 66
1802 22:58:23.376322 [Byte1]: 66
1803 22:58:23.380556
1804 22:58:23.380635 Set Vref, RX VrefLevel [Byte0]: 67
1805 22:58:23.383447 [Byte1]: 67
1806 22:58:23.387990
1807 22:58:23.388072 Set Vref, RX VrefLevel [Byte0]: 68
1808 22:58:23.394455 [Byte1]: 68
1809 22:58:23.394538
1810 22:58:23.397881 Set Vref, RX VrefLevel [Byte0]: 69
1811 22:58:23.401330 [Byte1]: 69
1812 22:58:23.401421
1813 22:58:23.404231 Set Vref, RX VrefLevel [Byte0]: 70
1814 22:58:23.407577 [Byte1]: 70
1815 22:58:23.410826
1816 22:58:23.410908 Set Vref, RX VrefLevel [Byte0]: 71
1817 22:58:23.413946 [Byte1]: 71
1818 22:58:23.418396
1819 22:58:23.418475 Set Vref, RX VrefLevel [Byte0]: 72
1820 22:58:23.421737 [Byte1]: 72
1821 22:58:23.425903
1822 22:58:23.425997 Set Vref, RX VrefLevel [Byte0]: 73
1823 22:58:23.429164 [Byte1]: 73
1824 22:58:23.433744
1825 22:58:23.433837 Set Vref, RX VrefLevel [Byte0]: 74
1826 22:58:23.436953 [Byte1]: 74
1827 22:58:23.441102
1828 22:58:23.441230 Set Vref, RX VrefLevel [Byte0]: 75
1829 22:58:23.444621 [Byte1]: 75
1830 22:58:23.448799
1831 22:58:23.448913 Set Vref, RX VrefLevel [Byte0]: 76
1832 22:58:23.452194 [Byte1]: 76
1833 22:58:23.456205
1834 22:58:23.456320 Set Vref, RX VrefLevel [Byte0]: 77
1835 22:58:23.459969 [Byte1]: 77
1836 22:58:23.463842
1837 22:58:23.463927 Set Vref, RX VrefLevel [Byte0]: 78
1838 22:58:23.467253 [Byte1]: 78
1839 22:58:23.471652
1840 22:58:23.471768 Final RX Vref Byte 0 = 51 to rank0
1841 22:58:23.475179 Final RX Vref Byte 1 = 63 to rank0
1842 22:58:23.478216 Final RX Vref Byte 0 = 51 to rank1
1843 22:58:23.481582 Final RX Vref Byte 1 = 63 to rank1==
1844 22:58:23.484951 Dram Type= 6, Freq= 0, CH_1, rank 0
1845 22:58:23.488311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1846 22:58:23.491810 ==
1847 22:58:23.491929 DQS Delay:
1848 22:58:23.492028 DQS0 = 0, DQS1 = 0
1849 22:58:23.495062 DQM Delay:
1850 22:58:23.495170 DQM0 = 93, DQM1 = 83
1851 22:58:23.498231 DQ Delay:
1852 22:58:23.501580 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1853 22:58:23.501704 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
1854 22:58:23.505088 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =80
1855 22:58:23.511651 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1856 22:58:23.511737
1857 22:58:23.511804
1858 22:58:23.518218 [DQSOSCAuto] RK0, (LSB)MR18= 0x3350, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
1859 22:58:23.521898 CH1 RK0: MR19=606, MR18=3350
1860 22:58:23.528631 CH1_RK0: MR19=0x606, MR18=0x3350, DQSOSC=389, MR23=63, INC=97, DEC=65
1861 22:58:23.528745
1862 22:58:23.531765 ----->DramcWriteLeveling(PI) begin...
1863 22:58:23.531888 ==
1864 22:58:23.535056 Dram Type= 6, Freq= 0, CH_1, rank 1
1865 22:58:23.538350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1866 22:58:23.538466 ==
1867 22:58:23.541589 Write leveling (Byte 0): 28 => 28
1868 22:58:23.545258 Write leveling (Byte 1): 32 => 32
1869 22:58:23.548630 DramcWriteLeveling(PI) end<-----
1870 22:58:23.548715
1871 22:58:23.548797 ==
1872 22:58:23.551553 Dram Type= 6, Freq= 0, CH_1, rank 1
1873 22:58:23.554999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1874 22:58:23.555084 ==
1875 22:58:23.558485 [Gating] SW mode calibration
1876 22:58:23.565013 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1877 22:58:23.571724 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1878 22:58:23.575132 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1879 22:58:23.578104 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1880 22:58:23.584751 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 22:58:23.588046 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 22:58:23.591581 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 22:58:23.597997 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 22:58:23.601683 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 22:58:23.604829 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 22:58:23.611631 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 22:58:23.614945 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 22:58:23.618433 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 22:58:23.624629 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 22:58:23.628070 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 22:58:23.631540 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 22:58:23.637721 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 22:58:23.641458 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 22:58:23.644612 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 22:58:23.651042 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1896 22:58:23.654695 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 22:58:23.658154 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 22:58:23.661560 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 22:58:23.667773 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 22:58:23.671134 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 22:58:23.674586 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 22:58:23.681452 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 22:58:23.684755 0 9 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1904 22:58:23.688123 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1905 22:58:23.694223 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1906 22:58:23.697603 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1907 22:58:23.701057 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1908 22:58:23.707634 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1909 22:58:23.710949 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1910 22:58:23.714425 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1911 22:58:23.721167 0 10 4 | B1->B0 | 2b2b 3131 | 0 0 | (0 0) (0 0)
1912 22:58:23.724482 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1913 22:58:23.727645 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 22:58:23.734477 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 22:58:23.737843 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 22:58:23.740805 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 22:58:23.747931 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 22:58:23.751020 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 22:58:23.754227 0 11 4 | B1->B0 | 3535 3232 | 0 0 | (0 0) (0 0)
1920 22:58:23.761054 0 11 8 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
1921 22:58:23.764097 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1922 22:58:23.767629 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1923 22:58:23.773919 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 22:58:23.777408 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 22:58:23.780868 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 22:58:23.787602 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 22:58:23.790614 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1928 22:58:23.793855 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 22:58:23.800699 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 22:58:23.804018 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 22:58:23.807514 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 22:58:23.814127 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 22:58:23.817048 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 22:58:23.820414 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 22:58:23.823969 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 22:58:23.830506 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 22:58:23.833868 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 22:58:23.837151 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 22:58:23.844045 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 22:58:23.847533 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 22:58:23.850857 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 22:58:23.857687 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1943 22:58:23.860589 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1944 22:58:23.864210 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1945 22:58:23.867473 Total UI for P1: 0, mck2ui 16
1946 22:58:23.870940 best dqsien dly found for B0: ( 0, 14, 6)
1947 22:58:23.873848 Total UI for P1: 0, mck2ui 16
1948 22:58:23.877169 best dqsien dly found for B1: ( 0, 14, 2)
1949 22:58:23.880715 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1950 22:58:23.884137 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1951 22:58:23.884223
1952 22:58:23.890472 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1953 22:58:23.893907 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1954 22:58:23.893992 [Gating] SW calibration Done
1955 22:58:23.897225 ==
1956 22:58:23.897322 Dram Type= 6, Freq= 0, CH_1, rank 1
1957 22:58:23.904036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1958 22:58:23.904120 ==
1959 22:58:23.904192 RX Vref Scan: 0
1960 22:58:23.904254
1961 22:58:23.907138 RX Vref 0 -> 0, step: 1
1962 22:58:23.907221
1963 22:58:23.910450 RX Delay -130 -> 252, step: 16
1964 22:58:23.913815 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1965 22:58:23.917051 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1966 22:58:23.920327 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1967 22:58:23.927041 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1968 22:58:23.930573 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1969 22:58:23.933801 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1970 22:58:23.937132 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1971 22:58:23.940597 iDelay=222, Bit 7, Center 85 (-18 ~ 189) 208
1972 22:58:23.947189 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1973 22:58:23.950127 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1974 22:58:23.953509 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1975 22:58:23.956843 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1976 22:58:23.960143 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1977 22:58:23.966969 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1978 22:58:23.970416 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1979 22:58:23.973881 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1980 22:58:23.973963 ==
1981 22:58:23.976902 Dram Type= 6, Freq= 0, CH_1, rank 1
1982 22:58:23.980533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1983 22:58:23.983807 ==
1984 22:58:23.983900 DQS Delay:
1985 22:58:23.983974 DQS0 = 0, DQS1 = 0
1986 22:58:23.986763 DQM Delay:
1987 22:58:23.986837 DQM0 = 91, DQM1 = 82
1988 22:58:23.990233 DQ Delay:
1989 22:58:23.990308 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1990 22:58:23.993686 DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =85
1991 22:58:23.997065 DQ8 =61, DQ9 =77, DQ10 =85, DQ11 =77
1992 22:58:24.000511 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =85
1993 22:58:24.000614
1994 22:58:24.003412
1995 22:58:24.003499 ==
1996 22:58:24.006859 Dram Type= 6, Freq= 0, CH_1, rank 1
1997 22:58:24.010272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1998 22:58:24.010359 ==
1999 22:58:24.010439
2000 22:58:24.010502
2001 22:58:24.013707 TX Vref Scan disable
2002 22:58:24.013785 == TX Byte 0 ==
2003 22:58:24.020017 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2004 22:58:24.023658 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2005 22:58:24.023735 == TX Byte 1 ==
2006 22:58:24.030084 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
2007 22:58:24.033521 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
2008 22:58:24.033656 ==
2009 22:58:24.036694 Dram Type= 6, Freq= 0, CH_1, rank 1
2010 22:58:24.040078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2011 22:58:24.040185 ==
2012 22:58:24.053785 TX Vref=22, minBit 8, minWin=27, winSum=446
2013 22:58:24.057160 TX Vref=24, minBit 13, minWin=27, winSum=452
2014 22:58:24.060492 TX Vref=26, minBit 15, minWin=27, winSum=457
2015 22:58:24.063499 TX Vref=28, minBit 13, minWin=27, winSum=456
2016 22:58:24.070444 TX Vref=30, minBit 13, minWin=27, winSum=458
2017 22:58:24.073523 TX Vref=32, minBit 15, minWin=27, winSum=455
2018 22:58:24.076668 [TxChooseVref] Worse bit 13, Min win 27, Win sum 458, Final Vref 30
2019 22:58:24.080201
2020 22:58:24.080277 Final TX Range 1 Vref 30
2021 22:58:24.080361
2022 22:58:24.080431 ==
2023 22:58:24.083529 Dram Type= 6, Freq= 0, CH_1, rank 1
2024 22:58:24.090051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2025 22:58:24.090143 ==
2026 22:58:24.090229
2027 22:58:24.090294
2028 22:58:24.090355 TX Vref Scan disable
2029 22:58:24.094374 == TX Byte 0 ==
2030 22:58:24.097747 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2031 22:58:24.101178 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2032 22:58:24.104574 == TX Byte 1 ==
2033 22:58:24.108015 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
2034 22:58:24.110850 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
2035 22:58:24.114559
2036 22:58:24.114637 [DATLAT]
2037 22:58:24.114704 Freq=800, CH1 RK1
2038 22:58:24.114782
2039 22:58:24.117665 DATLAT Default: 0xa
2040 22:58:24.117744 0, 0xFFFF, sum = 0
2041 22:58:24.121074 1, 0xFFFF, sum = 0
2042 22:58:24.121168 2, 0xFFFF, sum = 0
2043 22:58:24.124491 3, 0xFFFF, sum = 0
2044 22:58:24.124596 4, 0xFFFF, sum = 0
2045 22:58:24.127708 5, 0xFFFF, sum = 0
2046 22:58:24.127788 6, 0xFFFF, sum = 0
2047 22:58:24.131084 7, 0xFFFF, sum = 0
2048 22:58:24.134579 8, 0xFFFF, sum = 0
2049 22:58:24.134694 9, 0x0, sum = 1
2050 22:58:24.134811 10, 0x0, sum = 2
2051 22:58:24.137521 11, 0x0, sum = 3
2052 22:58:24.137609 12, 0x0, sum = 4
2053 22:58:24.140829 best_step = 10
2054 22:58:24.140919
2055 22:58:24.140994 ==
2056 22:58:24.144531 Dram Type= 6, Freq= 0, CH_1, rank 1
2057 22:58:24.147455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2058 22:58:24.147555 ==
2059 22:58:24.150791 RX Vref Scan: 0
2060 22:58:24.150895
2061 22:58:24.150966 RX Vref 0 -> 0, step: 1
2062 22:58:24.151030
2063 22:58:24.154218 RX Delay -95 -> 252, step: 8
2064 22:58:24.160905 iDelay=209, Bit 0, Center 92 (-7 ~ 192) 200
2065 22:58:24.164342 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
2066 22:58:24.167601 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2067 22:58:24.171075 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2068 22:58:24.174256 iDelay=209, Bit 4, Center 96 (-7 ~ 200) 208
2069 22:58:24.180966 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2070 22:58:24.184223 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2071 22:58:24.187549 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2072 22:58:24.190706 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2073 22:58:24.194006 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2074 22:58:24.200927 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2075 22:58:24.204272 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2076 22:58:24.207652 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2077 22:58:24.211066 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2078 22:58:24.214475 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2079 22:58:24.220785 iDelay=209, Bit 15, Center 92 (-23 ~ 208) 232
2080 22:58:24.220879 ==
2081 22:58:24.224175 Dram Type= 6, Freq= 0, CH_1, rank 1
2082 22:58:24.227441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2083 22:58:24.227521 ==
2084 22:58:24.227603 DQS Delay:
2085 22:58:24.230874 DQS0 = 0, DQS1 = 0
2086 22:58:24.230961 DQM Delay:
2087 22:58:24.234080 DQM0 = 90, DQM1 = 83
2088 22:58:24.234165 DQ Delay:
2089 22:58:24.237599 DQ0 =92, DQ1 =84, DQ2 =80, DQ3 =88
2090 22:58:24.241016 DQ4 =96, DQ5 =100, DQ6 =96, DQ7 =88
2091 22:58:24.244379 DQ8 =68, DQ9 =72, DQ10 =88, DQ11 =80
2092 22:58:24.247698 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =92
2093 22:58:24.247784
2094 22:58:24.247851
2095 22:58:24.254349 [DQSOSCAuto] RK1, (LSB)MR18= 0x350a, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
2096 22:58:24.257805 CH1 RK1: MR19=606, MR18=350A
2097 22:58:24.264046 CH1_RK1: MR19=0x606, MR18=0x350A, DQSOSC=396, MR23=63, INC=94, DEC=62
2098 22:58:24.267582 [RxdqsGatingPostProcess] freq 800
2099 22:58:24.274308 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2100 22:58:24.277303 Pre-setting of DQS Precalculation
2101 22:58:24.280989 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2102 22:58:24.287405 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2103 22:58:24.294291 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2104 22:58:24.294389
2105 22:58:24.294453
2106 22:58:24.297472 [Calibration Summary] 1600 Mbps
2107 22:58:24.300862 CH 0, Rank 0
2108 22:58:24.300939 SW Impedance : PASS
2109 22:58:24.304280 DUTY Scan : NO K
2110 22:58:24.307276 ZQ Calibration : PASS
2111 22:58:24.307362 Jitter Meter : NO K
2112 22:58:24.310588 CBT Training : PASS
2113 22:58:24.313971 Write leveling : PASS
2114 22:58:24.314071 RX DQS gating : PASS
2115 22:58:24.317354 RX DQ/DQS(RDDQC) : PASS
2116 22:58:24.320780 TX DQ/DQS : PASS
2117 22:58:24.320866 RX DATLAT : PASS
2118 22:58:24.324069 RX DQ/DQS(Engine): PASS
2119 22:58:24.324165 TX OE : NO K
2120 22:58:24.327553 All Pass.
2121 22:58:24.327650
2122 22:58:24.327730 CH 0, Rank 1
2123 22:58:24.330963 SW Impedance : PASS
2124 22:58:24.331093 DUTY Scan : NO K
2125 22:58:24.333871 ZQ Calibration : PASS
2126 22:58:24.337195 Jitter Meter : NO K
2127 22:58:24.337293 CBT Training : PASS
2128 22:58:24.340611 Write leveling : PASS
2129 22:58:24.344090 RX DQS gating : PASS
2130 22:58:24.344166 RX DQ/DQS(RDDQC) : PASS
2131 22:58:24.347140 TX DQ/DQS : PASS
2132 22:58:24.350408 RX DATLAT : PASS
2133 22:58:24.350485 RX DQ/DQS(Engine): PASS
2134 22:58:24.354086 TX OE : NO K
2135 22:58:24.354286 All Pass.
2136 22:58:24.354409
2137 22:58:24.356965 CH 1, Rank 0
2138 22:58:24.357039 SW Impedance : PASS
2139 22:58:24.360453 DUTY Scan : NO K
2140 22:58:24.363844 ZQ Calibration : PASS
2141 22:58:24.363965 Jitter Meter : NO K
2142 22:58:24.367285 CBT Training : PASS
2143 22:58:24.370631 Write leveling : PASS
2144 22:58:24.370728 RX DQS gating : PASS
2145 22:58:24.373663 RX DQ/DQS(RDDQC) : PASS
2146 22:58:24.373741 TX DQ/DQS : PASS
2147 22:58:24.377035 RX DATLAT : PASS
2148 22:58:24.380529 RX DQ/DQS(Engine): PASS
2149 22:58:24.380604 TX OE : NO K
2150 22:58:24.383952 All Pass.
2151 22:58:24.384022
2152 22:58:24.384083 CH 1, Rank 1
2153 22:58:24.387331 SW Impedance : PASS
2154 22:58:24.387403 DUTY Scan : NO K
2155 22:58:24.390160 ZQ Calibration : PASS
2156 22:58:24.393738 Jitter Meter : NO K
2157 22:58:24.393850 CBT Training : PASS
2158 22:58:24.396957 Write leveling : PASS
2159 22:58:24.400372 RX DQS gating : PASS
2160 22:58:24.400485 RX DQ/DQS(RDDQC) : PASS
2161 22:58:24.403924 TX DQ/DQS : PASS
2162 22:58:24.406937 RX DATLAT : PASS
2163 22:58:24.407044 RX DQ/DQS(Engine): PASS
2164 22:58:24.410554 TX OE : NO K
2165 22:58:24.410661 All Pass.
2166 22:58:24.410760
2167 22:58:24.413613 DramC Write-DBI off
2168 22:58:24.416956 PER_BANK_REFRESH: Hybrid Mode
2169 22:58:24.417034 TX_TRACKING: ON
2170 22:58:24.420333 [GetDramInforAfterCalByMRR] Vendor 6.
2171 22:58:24.423743 [GetDramInforAfterCalByMRR] Revision 606.
2172 22:58:24.426608 [GetDramInforAfterCalByMRR] Revision 2 0.
2173 22:58:24.430015 MR0 0x3b3b
2174 22:58:24.430122 MR8 0x5151
2175 22:58:24.433400 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2176 22:58:24.433483
2177 22:58:24.433551 MR0 0x3b3b
2178 22:58:24.436897 MR8 0x5151
2179 22:58:24.440155 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2180 22:58:24.440262
2181 22:58:24.450389 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2182 22:58:24.453227 [FAST_K] Save calibration result to emmc
2183 22:58:24.456596 [FAST_K] Save calibration result to emmc
2184 22:58:24.456709 dram_init: config_dvfs: 1
2185 22:58:24.463357 dramc_set_vcore_voltage set vcore to 662500
2186 22:58:24.463475 Read voltage for 1200, 2
2187 22:58:24.466774 Vio18 = 0
2188 22:58:24.466893 Vcore = 662500
2189 22:58:24.466994 Vdram = 0
2190 22:58:24.469688 Vddq = 0
2191 22:58:24.469816 Vmddr = 0
2192 22:58:24.473066 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2193 22:58:24.479622 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2194 22:58:24.483096 MEM_TYPE=3, freq_sel=15
2195 22:58:24.486583 sv_algorithm_assistance_LP4_1600
2196 22:58:24.490041 ============ PULL DRAM RESETB DOWN ============
2197 22:58:24.493321 ========== PULL DRAM RESETB DOWN end =========
2198 22:58:24.496643 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2199 22:58:24.499999 ===================================
2200 22:58:24.503287 LPDDR4 DRAM CONFIGURATION
2201 22:58:24.506335 ===================================
2202 22:58:24.509869 EX_ROW_EN[0] = 0x0
2203 22:58:24.509953 EX_ROW_EN[1] = 0x0
2204 22:58:24.513257 LP4Y_EN = 0x0
2205 22:58:24.513342 WORK_FSP = 0x0
2206 22:58:24.516461 WL = 0x4
2207 22:58:24.516578 RL = 0x4
2208 22:58:24.519658 BL = 0x2
2209 22:58:24.519741 RPST = 0x0
2210 22:58:24.522940 RD_PRE = 0x0
2211 22:58:24.523024 WR_PRE = 0x1
2212 22:58:24.526344 WR_PST = 0x0
2213 22:58:24.529679 DBI_WR = 0x0
2214 22:58:24.529764 DBI_RD = 0x0
2215 22:58:24.533103 OTF = 0x1
2216 22:58:24.536408 ===================================
2217 22:58:24.539881 ===================================
2218 22:58:24.539966 ANA top config
2219 22:58:24.543222 ===================================
2220 22:58:24.546426 DLL_ASYNC_EN = 0
2221 22:58:24.549827 ALL_SLAVE_EN = 0
2222 22:58:24.549913 NEW_RANK_MODE = 1
2223 22:58:24.552707 DLL_IDLE_MODE = 1
2224 22:58:24.556154 LP45_APHY_COMB_EN = 1
2225 22:58:24.559496 TX_ODT_DIS = 1
2226 22:58:24.559605 NEW_8X_MODE = 1
2227 22:58:24.562746 ===================================
2228 22:58:24.566081 ===================================
2229 22:58:24.569462 data_rate = 2400
2230 22:58:24.572836 CKR = 1
2231 22:58:24.576365 DQ_P2S_RATIO = 8
2232 22:58:24.579744 ===================================
2233 22:58:24.582643 CA_P2S_RATIO = 8
2234 22:58:24.586039 DQ_CA_OPEN = 0
2235 22:58:24.586142 DQ_SEMI_OPEN = 0
2236 22:58:24.589555 CA_SEMI_OPEN = 0
2237 22:58:24.592582 CA_FULL_RATE = 0
2238 22:58:24.595918 DQ_CKDIV4_EN = 0
2239 22:58:24.599489 CA_CKDIV4_EN = 0
2240 22:58:24.602460 CA_PREDIV_EN = 0
2241 22:58:24.602590 PH8_DLY = 17
2242 22:58:24.605907 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2243 22:58:24.609237 DQ_AAMCK_DIV = 4
2244 22:58:24.612477 CA_AAMCK_DIV = 4
2245 22:58:24.615640 CA_ADMCK_DIV = 4
2246 22:58:24.619246 DQ_TRACK_CA_EN = 0
2247 22:58:24.622669 CA_PICK = 1200
2248 22:58:24.622794 CA_MCKIO = 1200
2249 22:58:24.625980 MCKIO_SEMI = 0
2250 22:58:24.629012 PLL_FREQ = 2366
2251 22:58:24.632496 DQ_UI_PI_RATIO = 32
2252 22:58:24.635757 CA_UI_PI_RATIO = 0
2253 22:58:24.639202 ===================================
2254 22:58:24.642583 ===================================
2255 22:58:24.645637 memory_type:LPDDR4
2256 22:58:24.645735 GP_NUM : 10
2257 22:58:24.649296 SRAM_EN : 1
2258 22:58:24.649409 MD32_EN : 0
2259 22:58:24.652653 ===================================
2260 22:58:24.656076 [ANA_INIT] >>>>>>>>>>>>>>
2261 22:58:24.659031 <<<<<< [CONFIGURE PHASE]: ANA_TX
2262 22:58:24.662482 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2263 22:58:24.665841 ===================================
2264 22:58:24.669250 data_rate = 2400,PCW = 0X5b00
2265 22:58:24.672248 ===================================
2266 22:58:24.675594 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2267 22:58:24.682075 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2268 22:58:24.685637 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2269 22:58:24.692082 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2270 22:58:24.695564 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2271 22:58:24.699016 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2272 22:58:24.699115 [ANA_INIT] flow start
2273 22:58:24.702276 [ANA_INIT] PLL >>>>>>>>
2274 22:58:24.705687 [ANA_INIT] PLL <<<<<<<<
2275 22:58:24.705778 [ANA_INIT] MIDPI >>>>>>>>
2276 22:58:24.708665 [ANA_INIT] MIDPI <<<<<<<<
2277 22:58:24.712134 [ANA_INIT] DLL >>>>>>>>
2278 22:58:24.712213 [ANA_INIT] DLL <<<<<<<<
2279 22:58:24.715425 [ANA_INIT] flow end
2280 22:58:24.719054 ============ LP4 DIFF to SE enter ============
2281 22:58:24.722493 ============ LP4 DIFF to SE exit ============
2282 22:58:24.725524 [ANA_INIT] <<<<<<<<<<<<<
2283 22:58:24.728803 [Flow] Enable top DCM control >>>>>
2284 22:58:24.732504 [Flow] Enable top DCM control <<<<<
2285 22:58:24.735476 Enable DLL master slave shuffle
2286 22:58:24.742045 ==============================================================
2287 22:58:24.742131 Gating Mode config
2288 22:58:24.748892 ==============================================================
2289 22:58:24.748979 Config description:
2290 22:58:24.758991 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2291 22:58:24.765295 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2292 22:58:24.772202 SELPH_MODE 0: By rank 1: By Phase
2293 22:58:24.775575 ==============================================================
2294 22:58:24.778506 GAT_TRACK_EN = 1
2295 22:58:24.781931 RX_GATING_MODE = 2
2296 22:58:24.785399 RX_GATING_TRACK_MODE = 2
2297 22:58:24.788807 SELPH_MODE = 1
2298 22:58:24.792223 PICG_EARLY_EN = 1
2299 22:58:24.795105 VALID_LAT_VALUE = 1
2300 22:58:24.802007 ==============================================================
2301 22:58:24.805424 Enter into Gating configuration >>>>
2302 22:58:24.808560 Exit from Gating configuration <<<<
2303 22:58:24.808644 Enter into DVFS_PRE_config >>>>>
2304 22:58:24.821703 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2305 22:58:24.824860 Exit from DVFS_PRE_config <<<<<
2306 22:58:24.828274 Enter into PICG configuration >>>>
2307 22:58:24.831562 Exit from PICG configuration <<<<
2308 22:58:24.835004 [RX_INPUT] configuration >>>>>
2309 22:58:24.835104 [RX_INPUT] configuration <<<<<
2310 22:58:24.841649 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2311 22:58:24.848289 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2312 22:58:24.851602 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2313 22:58:24.858291 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2314 22:58:24.865074 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2315 22:58:24.871523 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2316 22:58:24.874825 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2317 22:58:24.877899 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2318 22:58:24.884859 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2319 22:58:24.888059 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2320 22:58:24.891591 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2321 22:58:24.898065 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2322 22:58:24.901536 ===================================
2323 22:58:24.901642 LPDDR4 DRAM CONFIGURATION
2324 22:58:24.904518 ===================================
2325 22:58:24.907927 EX_ROW_EN[0] = 0x0
2326 22:58:24.908028 EX_ROW_EN[1] = 0x0
2327 22:58:24.911195 LP4Y_EN = 0x0
2328 22:58:24.911303 WORK_FSP = 0x0
2329 22:58:24.914551 WL = 0x4
2330 22:58:24.914657 RL = 0x4
2331 22:58:24.917936 BL = 0x2
2332 22:58:24.918037 RPST = 0x0
2333 22:58:24.921354 RD_PRE = 0x0
2334 22:58:24.924768 WR_PRE = 0x1
2335 22:58:24.924873 WR_PST = 0x0
2336 22:58:24.927938 DBI_WR = 0x0
2337 22:58:24.928048 DBI_RD = 0x0
2338 22:58:24.931361 OTF = 0x1
2339 22:58:24.934778 ===================================
2340 22:58:24.937721 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2341 22:58:24.941107 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2342 22:58:24.944529 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2343 22:58:24.947880 ===================================
2344 22:58:24.951031 LPDDR4 DRAM CONFIGURATION
2345 22:58:24.954575 ===================================
2346 22:58:24.957778 EX_ROW_EN[0] = 0x10
2347 22:58:24.957872 EX_ROW_EN[1] = 0x0
2348 22:58:24.961029 LP4Y_EN = 0x0
2349 22:58:24.961112 WORK_FSP = 0x0
2350 22:58:24.964271 WL = 0x4
2351 22:58:24.964354 RL = 0x4
2352 22:58:24.967633 BL = 0x2
2353 22:58:24.967715 RPST = 0x0
2354 22:58:24.971048 RD_PRE = 0x0
2355 22:58:24.974410 WR_PRE = 0x1
2356 22:58:24.974491 WR_PST = 0x0
2357 22:58:24.977361 DBI_WR = 0x0
2358 22:58:24.977443 DBI_RD = 0x0
2359 22:58:24.981097 OTF = 0x1
2360 22:58:24.984440 ===================================
2361 22:58:24.987360 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2362 22:58:24.990780 ==
2363 22:58:24.990862 Dram Type= 6, Freq= 0, CH_0, rank 0
2364 22:58:24.997635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2365 22:58:24.997718 ==
2366 22:58:25.001038 [Duty_Offset_Calibration]
2367 22:58:25.001120 B0:2 B1:0 CA:1
2368 22:58:25.001184
2369 22:58:25.004024 [DutyScan_Calibration_Flow] k_type=0
2370 22:58:25.012761
2371 22:58:25.012850 ==CLK 0==
2372 22:58:25.015968 Final CLK duty delay cell = -4
2373 22:58:25.019272 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2374 22:58:25.022673 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2375 22:58:25.026080 [-4] AVG Duty = 4953%(X100)
2376 22:58:25.026156
2377 22:58:25.029566 CH0 CLK Duty spec in!! Max-Min= 156%
2378 22:58:25.032873 [DutyScan_Calibration_Flow] ====Done====
2379 22:58:25.032955
2380 22:58:25.036062 [DutyScan_Calibration_Flow] k_type=1
2381 22:58:25.051632
2382 22:58:25.051723 ==DQS 0 ==
2383 22:58:25.054882 Final DQS duty delay cell = 0
2384 22:58:25.058093 [0] MAX Duty = 5187%(X100), DQS PI = 30
2385 22:58:25.061326 [0] MIN Duty = 4938%(X100), DQS PI = 0
2386 22:58:25.064984 [0] AVG Duty = 5062%(X100)
2387 22:58:25.065065
2388 22:58:25.065129 ==DQS 1 ==
2389 22:58:25.068221 Final DQS duty delay cell = -4
2390 22:58:25.071588 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2391 22:58:25.074557 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2392 22:58:25.078017 [-4] AVG Duty = 5031%(X100)
2393 22:58:25.078098
2394 22:58:25.081392 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2395 22:58:25.081505
2396 22:58:25.084652 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2397 22:58:25.087971 [DutyScan_Calibration_Flow] ====Done====
2398 22:58:25.088099
2399 22:58:25.091369 [DutyScan_Calibration_Flow] k_type=3
2400 22:58:25.108499
2401 22:58:25.108624 ==DQM 0 ==
2402 22:58:25.112033 Final DQM duty delay cell = 0
2403 22:58:25.114955 [0] MAX Duty = 5062%(X100), DQS PI = 24
2404 22:58:25.118309 [0] MIN Duty = 4844%(X100), DQS PI = 0
2405 22:58:25.118395 [0] AVG Duty = 4953%(X100)
2406 22:58:25.121491
2407 22:58:25.121583 ==DQM 1 ==
2408 22:58:25.124771 Final DQM duty delay cell = 0
2409 22:58:25.128155 [0] MAX Duty = 5218%(X100), DQS PI = 50
2410 22:58:25.131563 [0] MIN Duty = 5000%(X100), DQS PI = 22
2411 22:58:25.135012 [0] AVG Duty = 5109%(X100)
2412 22:58:25.135102
2413 22:58:25.138161 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2414 22:58:25.138237
2415 22:58:25.141425 CH0 DQM 1 Duty spec in!! Max-Min= 218%
2416 22:58:25.145054 [DutyScan_Calibration_Flow] ====Done====
2417 22:58:25.145136
2418 22:58:25.148027 [DutyScan_Calibration_Flow] k_type=2
2419 22:58:25.165087
2420 22:58:25.165171 ==DQ 0 ==
2421 22:58:25.167941 Final DQ duty delay cell = -4
2422 22:58:25.171599 [-4] MAX Duty = 5031%(X100), DQS PI = 32
2423 22:58:25.174665 [-4] MIN Duty = 4875%(X100), DQS PI = 16
2424 22:58:25.178341 [-4] AVG Duty = 4953%(X100)
2425 22:58:25.178448
2426 22:58:25.178540 ==DQ 1 ==
2427 22:58:25.181247 Final DQ duty delay cell = 4
2428 22:58:25.184581 [4] MAX Duty = 5093%(X100), DQS PI = 4
2429 22:58:25.187975 [4] MIN Duty = 5031%(X100), DQS PI = 14
2430 22:58:25.191242 [4] AVG Duty = 5062%(X100)
2431 22:58:25.191345
2432 22:58:25.194584 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2433 22:58:25.194662
2434 22:58:25.197971 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2435 22:58:25.201377 [DutyScan_Calibration_Flow] ====Done====
2436 22:58:25.201446 ==
2437 22:58:25.204713 Dram Type= 6, Freq= 0, CH_1, rank 0
2438 22:58:25.208242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2439 22:58:25.208317 ==
2440 22:58:25.211543 [Duty_Offset_Calibration]
2441 22:58:25.211614 B0:0 B1:-1 CA:2
2442 22:58:25.211675
2443 22:58:25.214952 [DutyScan_Calibration_Flow] k_type=0
2444 22:58:25.225291
2445 22:58:25.225395 ==CLK 0==
2446 22:58:25.228676 Final CLK duty delay cell = 0
2447 22:58:25.231835 [0] MAX Duty = 5156%(X100), DQS PI = 16
2448 22:58:25.234875 [0] MIN Duty = 4938%(X100), DQS PI = 44
2449 22:58:25.234946 [0] AVG Duty = 5047%(X100)
2450 22:58:25.238521
2451 22:58:25.241782 CH1 CLK Duty spec in!! Max-Min= 218%
2452 22:58:25.245038 [DutyScan_Calibration_Flow] ====Done====
2453 22:58:25.245139
2454 22:58:25.248547 [DutyScan_Calibration_Flow] k_type=1
2455 22:58:25.264555
2456 22:58:25.264671 ==DQS 0 ==
2457 22:58:25.268193 Final DQS duty delay cell = 0
2458 22:58:25.271235 [0] MAX Duty = 5093%(X100), DQS PI = 24
2459 22:58:25.274626 [0] MIN Duty = 4969%(X100), DQS PI = 0
2460 22:58:25.274737 [0] AVG Duty = 5031%(X100)
2461 22:58:25.277973
2462 22:58:25.278076 ==DQS 1 ==
2463 22:58:25.281464 Final DQS duty delay cell = 0
2464 22:58:25.284555 [0] MAX Duty = 5156%(X100), DQS PI = 0
2465 22:58:25.288064 [0] MIN Duty = 4875%(X100), DQS PI = 34
2466 22:58:25.288170 [0] AVG Duty = 5015%(X100)
2467 22:58:25.288266
2468 22:58:25.294760 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2469 22:58:25.294876
2470 22:58:25.298242 CH1 DQS 1 Duty spec in!! Max-Min= 281%
2471 22:58:25.301158 [DutyScan_Calibration_Flow] ====Done====
2472 22:58:25.301267
2473 22:58:25.304578 [DutyScan_Calibration_Flow] k_type=3
2474 22:58:25.321048
2475 22:58:25.321162 ==DQM 0 ==
2476 22:58:25.324032 Final DQM duty delay cell = 4
2477 22:58:25.327488 [4] MAX Duty = 5093%(X100), DQS PI = 6
2478 22:58:25.330704 [4] MIN Duty = 4938%(X100), DQS PI = 48
2479 22:58:25.334195 [4] AVG Duty = 5015%(X100)
2480 22:58:25.334313
2481 22:58:25.334422 ==DQM 1 ==
2482 22:58:25.337548 Final DQM duty delay cell = -4
2483 22:58:25.341263 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2484 22:58:25.344476 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2485 22:58:25.347561 [-4] AVG Duty = 4875%(X100)
2486 22:58:25.347669
2487 22:58:25.350894 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2488 22:58:25.350970
2489 22:58:25.354250 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2490 22:58:25.357634 [DutyScan_Calibration_Flow] ====Done====
2491 22:58:25.357708
2492 22:58:25.360446 [DutyScan_Calibration_Flow] k_type=2
2493 22:58:25.377643
2494 22:58:25.377728 ==DQ 0 ==
2495 22:58:25.381191 Final DQ duty delay cell = 0
2496 22:58:25.384468 [0] MAX Duty = 5062%(X100), DQS PI = 20
2497 22:58:25.387665 [0] MIN Duty = 4938%(X100), DQS PI = 44
2498 22:58:25.391179 [0] AVG Duty = 5000%(X100)
2499 22:58:25.391253
2500 22:58:25.391318 ==DQ 1 ==
2501 22:58:25.394266 Final DQ duty delay cell = 0
2502 22:58:25.397381 [0] MAX Duty = 5031%(X100), DQS PI = 0
2503 22:58:25.401015 [0] MIN Duty = 4813%(X100), DQS PI = 34
2504 22:58:25.401091 [0] AVG Duty = 4922%(X100)
2505 22:58:25.404001
2506 22:58:25.407485 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2507 22:58:25.407590
2508 22:58:25.410458 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2509 22:58:25.414027 [DutyScan_Calibration_Flow] ====Done====
2510 22:58:25.417416 nWR fixed to 30
2511 22:58:25.417502 [ModeRegInit_LP4] CH0 RK0
2512 22:58:25.420883 [ModeRegInit_LP4] CH0 RK1
2513 22:58:25.424278 [ModeRegInit_LP4] CH1 RK0
2514 22:58:25.427178 [ModeRegInit_LP4] CH1 RK1
2515 22:58:25.427260 match AC timing 7
2516 22:58:25.433983 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2517 22:58:25.437177 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2518 22:58:25.440636 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2519 22:58:25.447519 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2520 22:58:25.450346 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2521 22:58:25.450459 ==
2522 22:58:25.453952 Dram Type= 6, Freq= 0, CH_0, rank 0
2523 22:58:25.457228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2524 22:58:25.457332 ==
2525 22:58:25.463953 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2526 22:58:25.470342 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2527 22:58:25.477443 [CA 0] Center 38 (7~69) winsize 63
2528 22:58:25.480727 [CA 1] Center 38 (7~69) winsize 63
2529 22:58:25.484315 [CA 2] Center 35 (5~66) winsize 62
2530 22:58:25.487531 [CA 3] Center 35 (4~66) winsize 63
2531 22:58:25.490984 [CA 4] Center 34 (4~65) winsize 62
2532 22:58:25.494459 [CA 5] Center 33 (3~63) winsize 61
2533 22:58:25.494573
2534 22:58:25.497605 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2535 22:58:25.497730
2536 22:58:25.501177 [CATrainingPosCal] consider 1 rank data
2537 22:58:25.504235 u2DelayCellTimex100 = 270/100 ps
2538 22:58:25.507789 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2539 22:58:25.511037 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2540 22:58:25.517455 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2541 22:58:25.520970 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2542 22:58:25.524363 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2543 22:58:25.527378 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2544 22:58:25.527491
2545 22:58:25.530714 CA PerBit enable=1, Macro0, CA PI delay=33
2546 22:58:25.530824
2547 22:58:25.534158 [CBTSetCACLKResult] CA Dly = 33
2548 22:58:25.534239 CS Dly: 6 (0~37)
2549 22:58:25.534304 ==
2550 22:58:25.537590 Dram Type= 6, Freq= 0, CH_0, rank 1
2551 22:58:25.544139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2552 22:58:25.544234 ==
2553 22:58:25.547619 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2554 22:58:25.554311 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2555 22:58:25.563228 [CA 0] Center 39 (8~70) winsize 63
2556 22:58:25.566557 [CA 1] Center 38 (8~69) winsize 62
2557 22:58:25.570011 [CA 2] Center 35 (5~66) winsize 62
2558 22:58:25.573453 [CA 3] Center 35 (5~66) winsize 62
2559 22:58:25.576838 [CA 4] Center 34 (4~65) winsize 62
2560 22:58:25.579937 [CA 5] Center 33 (3~64) winsize 62
2561 22:58:25.580014
2562 22:58:25.583273 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2563 22:58:25.583352
2564 22:58:25.586644 [CATrainingPosCal] consider 2 rank data
2565 22:58:25.590028 u2DelayCellTimex100 = 270/100 ps
2566 22:58:25.593447 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2567 22:58:25.596782 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2568 22:58:25.603512 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2569 22:58:25.606837 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2570 22:58:25.610090 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2571 22:58:25.613154 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2572 22:58:25.613231
2573 22:58:25.616585 CA PerBit enable=1, Macro0, CA PI delay=33
2574 22:58:25.616689
2575 22:58:25.619886 [CBTSetCACLKResult] CA Dly = 33
2576 22:58:25.619960 CS Dly: 7 (0~39)
2577 22:58:25.620022
2578 22:58:25.623404 ----->DramcWriteLeveling(PI) begin...
2579 22:58:25.626284 ==
2580 22:58:25.629643 Dram Type= 6, Freq= 0, CH_0, rank 0
2581 22:58:25.633064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2582 22:58:25.633140 ==
2583 22:58:25.636435 Write leveling (Byte 0): 35 => 35
2584 22:58:25.639784 Write leveling (Byte 1): 33 => 33
2585 22:58:25.642670 DramcWriteLeveling(PI) end<-----
2586 22:58:25.642744
2587 22:58:25.642814 ==
2588 22:58:25.646254 Dram Type= 6, Freq= 0, CH_0, rank 0
2589 22:58:25.649574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2590 22:58:25.649663 ==
2591 22:58:25.653116 [Gating] SW mode calibration
2592 22:58:25.659662 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2593 22:58:25.666184 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2594 22:58:25.669608 0 15 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2595 22:58:25.672556 0 15 4 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
2596 22:58:25.678992 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2597 22:58:25.682314 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2598 22:58:25.685625 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2599 22:58:25.692524 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2600 22:58:25.695887 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
2601 22:58:25.699157 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2602 22:58:25.705475 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
2603 22:58:25.708805 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2604 22:58:25.712278 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2605 22:58:25.718945 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2606 22:58:25.722384 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2607 22:58:25.725510 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2608 22:58:25.732113 1 0 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2609 22:58:25.735548 1 0 28 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
2610 22:58:25.739005 1 1 0 | B1->B0 | 3333 4646 | 1 0 | (0 0) (0 0)
2611 22:58:25.745133 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2612 22:58:25.748368 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2613 22:58:25.752056 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2614 22:58:25.758400 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2615 22:58:25.761727 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2616 22:58:25.765049 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2617 22:58:25.771767 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2618 22:58:25.774593 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2619 22:58:25.778501 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2620 22:58:25.784941 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 22:58:25.788056 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 22:58:25.791425 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 22:58:25.797974 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 22:58:25.801441 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 22:58:25.804865 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 22:58:25.811201 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 22:58:25.814943 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 22:58:25.817774 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 22:58:25.824482 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 22:58:25.827829 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 22:58:25.831405 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 22:58:25.834512 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 22:58:25.841118 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2634 22:58:25.844482 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2635 22:58:25.847845 Total UI for P1: 0, mck2ui 16
2636 22:58:25.850930 best dqsien dly found for B0: ( 1, 3, 28)
2637 22:58:25.854397 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2638 22:58:25.858052 Total UI for P1: 0, mck2ui 16
2639 22:58:25.861041 best dqsien dly found for B1: ( 1, 3, 30)
2640 22:58:25.864461 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2641 22:58:25.867763 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2642 22:58:25.870905
2643 22:58:25.874271 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2644 22:58:25.877673 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2645 22:58:25.881039 [Gating] SW calibration Done
2646 22:58:25.881115 ==
2647 22:58:25.884486 Dram Type= 6, Freq= 0, CH_0, rank 0
2648 22:58:25.887828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2649 22:58:25.887914 ==
2650 22:58:25.887977 RX Vref Scan: 0
2651 22:58:25.888036
2652 22:58:25.891124 RX Vref 0 -> 0, step: 1
2653 22:58:25.891220
2654 22:58:25.894341 RX Delay -40 -> 252, step: 8
2655 22:58:25.897678 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2656 22:58:25.901207 iDelay=208, Bit 1, Center 127 (56 ~ 199) 144
2657 22:58:25.908034 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2658 22:58:25.910982 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2659 22:58:25.914272 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2660 22:58:25.918070 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2661 22:58:25.920967 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2662 22:58:25.927710 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2663 22:58:25.931139 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2664 22:58:25.934312 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2665 22:58:25.937551 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2666 22:58:25.941058 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2667 22:58:25.944397 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2668 22:58:25.951234 iDelay=208, Bit 13, Center 111 (48 ~ 175) 128
2669 22:58:25.954604 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2670 22:58:25.957856 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2671 22:58:25.957940 ==
2672 22:58:25.961056 Dram Type= 6, Freq= 0, CH_0, rank 0
2673 22:58:25.964498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2674 22:58:25.967838 ==
2675 22:58:25.967922 DQS Delay:
2676 22:58:25.967988 DQS0 = 0, DQS1 = 0
2677 22:58:25.970787 DQM Delay:
2678 22:58:25.970870 DQM0 = 123, DQM1 = 109
2679 22:58:25.974506 DQ Delay:
2680 22:58:25.977643 DQ0 =123, DQ1 =127, DQ2 =119, DQ3 =119
2681 22:58:25.981146 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2682 22:58:25.984152 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2683 22:58:25.987508 DQ12 =115, DQ13 =111, DQ14 =123, DQ15 =115
2684 22:58:25.987590
2685 22:58:25.987654
2686 22:58:25.987714 ==
2687 22:58:25.990936 Dram Type= 6, Freq= 0, CH_0, rank 0
2688 22:58:25.994307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2689 22:58:25.994389 ==
2690 22:58:25.994453
2691 22:58:25.994513
2692 22:58:25.997477 TX Vref Scan disable
2693 22:58:26.000874 == TX Byte 0 ==
2694 22:58:26.004269 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2695 22:58:26.007732 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2696 22:58:26.010566 == TX Byte 1 ==
2697 22:58:26.014176 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2698 22:58:26.017416 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2699 22:58:26.017498 ==
2700 22:58:26.020640 Dram Type= 6, Freq= 0, CH_0, rank 0
2701 22:58:26.027449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2702 22:58:26.027532 ==
2703 22:58:26.037839 TX Vref=22, minBit 7, minWin=23, winSum=399
2704 22:58:26.041202 TX Vref=24, minBit 1, minWin=24, winSum=406
2705 22:58:26.044446 TX Vref=26, minBit 0, minWin=25, winSum=413
2706 22:58:26.047891 TX Vref=28, minBit 1, minWin=25, winSum=414
2707 22:58:26.051051 TX Vref=30, minBit 3, minWin=25, winSum=416
2708 22:58:26.054574 TX Vref=32, minBit 0, minWin=25, winSum=412
2709 22:58:26.060989 [TxChooseVref] Worse bit 3, Min win 25, Win sum 416, Final Vref 30
2710 22:58:26.061097
2711 22:58:26.064205 Final TX Range 1 Vref 30
2712 22:58:26.064308
2713 22:58:26.064404 ==
2714 22:58:26.067592 Dram Type= 6, Freq= 0, CH_0, rank 0
2715 22:58:26.071056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2716 22:58:26.071142 ==
2717 22:58:26.074126
2718 22:58:26.074210
2719 22:58:26.074278 TX Vref Scan disable
2720 22:58:26.077487 == TX Byte 0 ==
2721 22:58:26.081056 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2722 22:58:26.084361 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2723 22:58:26.087715 == TX Byte 1 ==
2724 22:58:26.091052 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2725 22:58:26.094035 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2726 22:58:26.097489
2727 22:58:26.097601 [DATLAT]
2728 22:58:26.097707 Freq=1200, CH0 RK0
2729 22:58:26.097804
2730 22:58:26.100664 DATLAT Default: 0xd
2731 22:58:26.100787 0, 0xFFFF, sum = 0
2732 22:58:26.104361 1, 0xFFFF, sum = 0
2733 22:58:26.104465 2, 0xFFFF, sum = 0
2734 22:58:26.107255 3, 0xFFFF, sum = 0
2735 22:58:26.110607 4, 0xFFFF, sum = 0
2736 22:58:26.110728 5, 0xFFFF, sum = 0
2737 22:58:26.114061 6, 0xFFFF, sum = 0
2738 22:58:26.114173 7, 0xFFFF, sum = 0
2739 22:58:26.117547 8, 0xFFFF, sum = 0
2740 22:58:26.117658 9, 0xFFFF, sum = 0
2741 22:58:26.120532 10, 0xFFFF, sum = 0
2742 22:58:26.120642 11, 0xFFFF, sum = 0
2743 22:58:26.124235 12, 0x0, sum = 1
2744 22:58:26.124345 13, 0x0, sum = 2
2745 22:58:26.127506 14, 0x0, sum = 3
2746 22:58:26.127589 15, 0x0, sum = 4
2747 22:58:26.127655 best_step = 13
2748 22:58:26.130954
2749 22:58:26.131035 ==
2750 22:58:26.133879 Dram Type= 6, Freq= 0, CH_0, rank 0
2751 22:58:26.137289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2752 22:58:26.137373 ==
2753 22:58:26.137438 RX Vref Scan: 1
2754 22:58:26.137498
2755 22:58:26.140743 Set Vref Range= 32 -> 127
2756 22:58:26.140868
2757 22:58:26.144106 RX Vref 32 -> 127, step: 1
2758 22:58:26.144191
2759 22:58:26.147556 RX Delay -13 -> 252, step: 4
2760 22:58:26.147639
2761 22:58:26.150541 Set Vref, RX VrefLevel [Byte0]: 32
2762 22:58:26.154070 [Byte1]: 32
2763 22:58:26.154183
2764 22:58:26.157394 Set Vref, RX VrefLevel [Byte0]: 33
2765 22:58:26.160420 [Byte1]: 33
2766 22:58:26.163791
2767 22:58:26.163872 Set Vref, RX VrefLevel [Byte0]: 34
2768 22:58:26.167010 [Byte1]: 34
2769 22:58:26.171634
2770 22:58:26.171717 Set Vref, RX VrefLevel [Byte0]: 35
2771 22:58:26.175146 [Byte1]: 35
2772 22:58:26.179400
2773 22:58:26.179485 Set Vref, RX VrefLevel [Byte0]: 36
2774 22:58:26.182895 [Byte1]: 36
2775 22:58:26.187747
2776 22:58:26.187832 Set Vref, RX VrefLevel [Byte0]: 37
2777 22:58:26.190613 [Byte1]: 37
2778 22:58:26.195483
2779 22:58:26.195567 Set Vref, RX VrefLevel [Byte0]: 38
2780 22:58:26.198860 [Byte1]: 38
2781 22:58:26.203264
2782 22:58:26.203349 Set Vref, RX VrefLevel [Byte0]: 39
2783 22:58:26.206752 [Byte1]: 39
2784 22:58:26.211020
2785 22:58:26.211110 Set Vref, RX VrefLevel [Byte0]: 40
2786 22:58:26.214404 [Byte1]: 40
2787 22:58:26.219226
2788 22:58:26.219303 Set Vref, RX VrefLevel [Byte0]: 41
2789 22:58:26.222174 [Byte1]: 41
2790 22:58:26.226923
2791 22:58:26.227004 Set Vref, RX VrefLevel [Byte0]: 42
2792 22:58:26.230159 [Byte1]: 42
2793 22:58:26.234610
2794 22:58:26.234712 Set Vref, RX VrefLevel [Byte0]: 43
2795 22:58:26.241991 [Byte1]: 43
2796 22:58:26.242072
2797 22:58:26.244593 Set Vref, RX VrefLevel [Byte0]: 44
2798 22:58:26.248044 [Byte1]: 44
2799 22:58:26.248147
2800 22:58:26.251528 Set Vref, RX VrefLevel [Byte0]: 45
2801 22:58:26.254508 [Byte1]: 45
2802 22:58:26.258627
2803 22:58:26.258733 Set Vref, RX VrefLevel [Byte0]: 46
2804 22:58:26.261905 [Byte1]: 46
2805 22:58:26.266235
2806 22:58:26.266338 Set Vref, RX VrefLevel [Byte0]: 47
2807 22:58:26.269859 [Byte1]: 47
2808 22:58:26.274316
2809 22:58:26.274418 Set Vref, RX VrefLevel [Byte0]: 48
2810 22:58:26.277900 [Byte1]: 48
2811 22:58:26.282357
2812 22:58:26.282458 Set Vref, RX VrefLevel [Byte0]: 49
2813 22:58:26.285717 [Byte1]: 49
2814 22:58:26.289999
2815 22:58:26.290131 Set Vref, RX VrefLevel [Byte0]: 50
2816 22:58:26.293246 [Byte1]: 50
2817 22:58:26.297745
2818 22:58:26.297875 Set Vref, RX VrefLevel [Byte0]: 51
2819 22:58:26.301155 [Byte1]: 51
2820 22:58:26.306017
2821 22:58:26.306145 Set Vref, RX VrefLevel [Byte0]: 52
2822 22:58:26.309374 [Byte1]: 52
2823 22:58:26.313578
2824 22:58:26.313708 Set Vref, RX VrefLevel [Byte0]: 53
2825 22:58:26.317023 [Byte1]: 53
2826 22:58:26.321524
2827 22:58:26.321652 Set Vref, RX VrefLevel [Byte0]: 54
2828 22:58:26.325010 [Byte1]: 54
2829 22:58:26.329438
2830 22:58:26.329595 Set Vref, RX VrefLevel [Byte0]: 55
2831 22:58:26.332983 [Byte1]: 55
2832 22:58:26.337378
2833 22:58:26.340746 Set Vref, RX VrefLevel [Byte0]: 56
2834 22:58:26.340880 [Byte1]: 56
2835 22:58:26.345269
2836 22:58:26.345368 Set Vref, RX VrefLevel [Byte0]: 57
2837 22:58:26.348730 [Byte1]: 57
2838 22:58:26.353065
2839 22:58:26.353175 Set Vref, RX VrefLevel [Byte0]: 58
2840 22:58:26.356561 [Byte1]: 58
2841 22:58:26.361225
2842 22:58:26.361367 Set Vref, RX VrefLevel [Byte0]: 59
2843 22:58:26.364384 [Byte1]: 59
2844 22:58:26.369117
2845 22:58:26.369243 Set Vref, RX VrefLevel [Byte0]: 60
2846 22:58:26.372053 [Byte1]: 60
2847 22:58:26.376997
2848 22:58:26.377104 Set Vref, RX VrefLevel [Byte0]: 61
2849 22:58:26.380064 [Byte1]: 61
2850 22:58:26.384939
2851 22:58:26.385044 Set Vref, RX VrefLevel [Byte0]: 62
2852 22:58:26.388107 [Byte1]: 62
2853 22:58:26.392499
2854 22:58:26.392605 Set Vref, RX VrefLevel [Byte0]: 63
2855 22:58:26.396271 [Byte1]: 63
2856 22:58:26.400598
2857 22:58:26.400708 Set Vref, RX VrefLevel [Byte0]: 64
2858 22:58:26.406805 [Byte1]: 64
2859 22:58:26.406911
2860 22:58:26.410279 Set Vref, RX VrefLevel [Byte0]: 65
2861 22:58:26.413549 [Byte1]: 65
2862 22:58:26.413634
2863 22:58:26.416736 Set Vref, RX VrefLevel [Byte0]: 66
2864 22:58:26.420210 [Byte1]: 66
2865 22:58:26.424045
2866 22:58:26.424131 Set Vref, RX VrefLevel [Byte0]: 67
2867 22:58:26.427555 [Byte1]: 67
2868 22:58:26.432059
2869 22:58:26.432181 Set Vref, RX VrefLevel [Byte0]: 68
2870 22:58:26.435529 [Byte1]: 68
2871 22:58:26.439831
2872 22:58:26.439939 Set Vref, RX VrefLevel [Byte0]: 69
2873 22:58:26.443305 [Byte1]: 69
2874 22:58:26.447669
2875 22:58:26.447790 Set Vref, RX VrefLevel [Byte0]: 70
2876 22:58:26.451259 [Byte1]: 70
2877 22:58:26.456086
2878 22:58:26.456170 Final RX Vref Byte 0 = 59 to rank0
2879 22:58:26.459042 Final RX Vref Byte 1 = 50 to rank0
2880 22:58:26.462408 Final RX Vref Byte 0 = 59 to rank1
2881 22:58:26.465779 Final RX Vref Byte 1 = 50 to rank1==
2882 22:58:26.468987 Dram Type= 6, Freq= 0, CH_0, rank 0
2883 22:58:26.475717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2884 22:58:26.475838 ==
2885 22:58:26.475911 DQS Delay:
2886 22:58:26.475975 DQS0 = 0, DQS1 = 0
2887 22:58:26.479152 DQM Delay:
2888 22:58:26.479258 DQM0 = 123, DQM1 = 109
2889 22:58:26.482518 DQ Delay:
2890 22:58:26.485415 DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =120
2891 22:58:26.489035 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2892 22:58:26.492542 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =108
2893 22:58:26.495858 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2894 22:58:26.495962
2895 22:58:26.496055
2896 22:58:26.502341 [DQSOSCAuto] RK0, (LSB)MR18= 0x805, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
2897 22:58:26.505769 CH0 RK0: MR19=404, MR18=805
2898 22:58:26.512592 CH0_RK0: MR19=0x404, MR18=0x805, DQSOSC=406, MR23=63, INC=39, DEC=26
2899 22:58:26.512677
2900 22:58:26.515490 ----->DramcWriteLeveling(PI) begin...
2901 22:58:26.515575 ==
2902 22:58:26.519316 Dram Type= 6, Freq= 0, CH_0, rank 1
2903 22:58:26.522667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2904 22:58:26.525463 ==
2905 22:58:26.525547 Write leveling (Byte 0): 34 => 34
2906 22:58:26.528790 Write leveling (Byte 1): 30 => 30
2907 22:58:26.532184 DramcWriteLeveling(PI) end<-----
2908 22:58:26.532268
2909 22:58:26.532334 ==
2910 22:58:26.535604 Dram Type= 6, Freq= 0, CH_0, rank 1
2911 22:58:26.542247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2912 22:58:26.542333 ==
2913 22:58:26.542401 [Gating] SW mode calibration
2914 22:58:26.552399 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2915 22:58:26.555402 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2916 22:58:26.562175 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2917 22:58:26.565534 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2918 22:58:26.568919 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2919 22:58:26.572309 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2920 22:58:26.578554 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2921 22:58:26.582024 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2922 22:58:26.585395 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2923 22:58:26.591806 0 15 28 | B1->B0 | 2d2d 2d2d | 0 0 | (0 0) (0 1)
2924 22:58:26.594980 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2925 22:58:26.598892 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2926 22:58:26.604879 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2927 22:58:26.608462 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2928 22:58:26.611935 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2929 22:58:26.618407 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2930 22:58:26.621624 1 0 24 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
2931 22:58:26.625231 1 0 28 | B1->B0 | 3d3d 4545 | 1 0 | (0 0) (0 0)
2932 22:58:26.631531 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2933 22:58:26.635003 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2934 22:58:26.638496 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 22:58:26.645156 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 22:58:26.648243 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 22:58:26.651664 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 22:58:26.658467 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 22:58:26.661386 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2940 22:58:26.664829 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 22:58:26.671724 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 22:58:26.674683 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 22:58:26.677981 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 22:58:26.684690 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 22:58:26.688067 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 22:58:26.691460 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 22:58:26.697999 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 22:58:26.701629 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 22:58:26.704566 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 22:58:26.711509 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 22:58:26.714699 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 22:58:26.718051 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 22:58:26.724754 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 22:58:26.728089 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 22:58:26.731330 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2956 22:58:26.734834 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2957 22:58:26.738225 Total UI for P1: 0, mck2ui 16
2958 22:58:26.741181 best dqsien dly found for B0: ( 1, 3, 28)
2959 22:58:26.744549 Total UI for P1: 0, mck2ui 16
2960 22:58:26.748048 best dqsien dly found for B1: ( 1, 3, 28)
2961 22:58:26.751025 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2962 22:58:26.754360 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2963 22:58:26.757907
2964 22:58:26.761291 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2965 22:58:26.764651 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2966 22:58:26.768017 [Gating] SW calibration Done
2967 22:58:26.768107 ==
2968 22:58:26.771473 Dram Type= 6, Freq= 0, CH_0, rank 1
2969 22:58:26.774357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2970 22:58:26.774445 ==
2971 22:58:26.774506 RX Vref Scan: 0
2972 22:58:26.777882
2973 22:58:26.777970 RX Vref 0 -> 0, step: 1
2974 22:58:26.778034
2975 22:58:26.781239 RX Delay -40 -> 252, step: 8
2976 22:58:26.784431 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2977 22:58:26.787919 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2978 22:58:26.794699 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2979 22:58:26.797933 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2980 22:58:26.801353 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2981 22:58:26.804299 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2982 22:58:26.808065 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2983 22:58:26.814461 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2984 22:58:26.817590 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2985 22:58:26.820973 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2986 22:58:26.824318 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2987 22:58:26.827699 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2988 22:58:26.834360 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2989 22:58:26.837694 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2990 22:58:26.841175 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2991 22:58:26.844166 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2992 22:58:26.844241 ==
2993 22:58:26.847535 Dram Type= 6, Freq= 0, CH_0, rank 1
2994 22:58:26.854295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2995 22:58:26.854380 ==
2996 22:58:26.854454 DQS Delay:
2997 22:58:26.854518 DQS0 = 0, DQS1 = 0
2998 22:58:26.857634 DQM Delay:
2999 22:58:26.857713 DQM0 = 120, DQM1 = 108
3000 22:58:26.861108 DQ Delay:
3001 22:58:26.864177 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
3002 22:58:26.867515 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
3003 22:58:26.870925 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3004 22:58:26.874438 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
3005 22:58:26.874515
3006 22:58:26.874578
3007 22:58:26.874638 ==
3008 22:58:26.877724 Dram Type= 6, Freq= 0, CH_0, rank 1
3009 22:58:26.880625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3010 22:58:26.880730 ==
3011 22:58:26.884051
3012 22:58:26.884122
3013 22:58:26.884193 TX Vref Scan disable
3014 22:58:26.887696 == TX Byte 0 ==
3015 22:58:26.891037 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3016 22:58:26.893994 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3017 22:58:26.897386 == TX Byte 1 ==
3018 22:58:26.900698 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3019 22:58:26.904111 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3020 22:58:26.904195 ==
3021 22:58:26.907285 Dram Type= 6, Freq= 0, CH_0, rank 1
3022 22:58:26.914255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3023 22:58:26.914347 ==
3024 22:58:26.924751 TX Vref=22, minBit 4, minWin=24, winSum=411
3025 22:58:26.928450 TX Vref=24, minBit 7, minWin=24, winSum=416
3026 22:58:26.931758 TX Vref=26, minBit 1, minWin=24, winSum=416
3027 22:58:26.935112 TX Vref=28, minBit 4, minWin=24, winSum=416
3028 22:58:26.938243 TX Vref=30, minBit 1, minWin=25, winSum=424
3029 22:58:26.945010 TX Vref=32, minBit 1, minWin=25, winSum=421
3030 22:58:26.948063 [TxChooseVref] Worse bit 1, Min win 25, Win sum 424, Final Vref 30
3031 22:58:26.948192
3032 22:58:26.951523 Final TX Range 1 Vref 30
3033 22:58:26.951614
3034 22:58:26.951682 ==
3035 22:58:26.954951 Dram Type= 6, Freq= 0, CH_0, rank 1
3036 22:58:26.957890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3037 22:58:26.957978 ==
3038 22:58:26.961378
3039 22:58:26.961462
3040 22:58:26.961528 TX Vref Scan disable
3041 22:58:26.964679 == TX Byte 0 ==
3042 22:58:26.967989 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3043 22:58:26.974499 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3044 22:58:26.974584 == TX Byte 1 ==
3045 22:58:26.978043 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3046 22:58:26.984785 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3047 22:58:26.984870
3048 22:58:26.984936 [DATLAT]
3049 22:58:26.984999 Freq=1200, CH0 RK1
3050 22:58:26.985059
3051 22:58:26.988198 DATLAT Default: 0xd
3052 22:58:26.988282 0, 0xFFFF, sum = 0
3053 22:58:26.991006 1, 0xFFFF, sum = 0
3054 22:58:26.994316 2, 0xFFFF, sum = 0
3055 22:58:26.994445 3, 0xFFFF, sum = 0
3056 22:58:26.997701 4, 0xFFFF, sum = 0
3057 22:58:26.997829 5, 0xFFFF, sum = 0
3058 22:58:27.001014 6, 0xFFFF, sum = 0
3059 22:58:27.001137 7, 0xFFFF, sum = 0
3060 22:58:27.004513 8, 0xFFFF, sum = 0
3061 22:58:27.004601 9, 0xFFFF, sum = 0
3062 22:58:27.007994 10, 0xFFFF, sum = 0
3063 22:58:27.008080 11, 0xFFFF, sum = 0
3064 22:58:27.011255 12, 0x0, sum = 1
3065 22:58:27.011357 13, 0x0, sum = 2
3066 22:58:27.014491 14, 0x0, sum = 3
3067 22:58:27.014597 15, 0x0, sum = 4
3068 22:58:27.017982 best_step = 13
3069 22:58:27.018078
3070 22:58:27.018168 ==
3071 22:58:27.021391 Dram Type= 6, Freq= 0, CH_0, rank 1
3072 22:58:27.024284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3073 22:58:27.024384 ==
3074 22:58:27.024474 RX Vref Scan: 0
3075 22:58:27.024563
3076 22:58:27.027920 RX Vref 0 -> 0, step: 1
3077 22:58:27.028017
3078 22:58:27.031267 RX Delay -21 -> 252, step: 4
3079 22:58:27.034540 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3080 22:58:27.040998 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3081 22:58:27.044479 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3082 22:58:27.047820 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3083 22:58:27.051218 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3084 22:58:27.054203 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3085 22:58:27.061048 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3086 22:58:27.064395 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3087 22:58:27.067738 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3088 22:58:27.071148 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3089 22:58:27.074118 iDelay=195, Bit 10, Center 108 (47 ~ 170) 124
3090 22:58:27.080942 iDelay=195, Bit 11, Center 104 (43 ~ 166) 124
3091 22:58:27.084332 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3092 22:58:27.087790 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3093 22:58:27.091193 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3094 22:58:27.094481 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3095 22:58:27.097667 ==
3096 22:58:27.101118 Dram Type= 6, Freq= 0, CH_0, rank 1
3097 22:58:27.104433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3098 22:58:27.104532 ==
3099 22:58:27.104599 DQS Delay:
3100 22:58:27.107514 DQS0 = 0, DQS1 = 0
3101 22:58:27.107589 DQM Delay:
3102 22:58:27.110995 DQM0 = 119, DQM1 = 107
3103 22:58:27.111088 DQ Delay:
3104 22:58:27.114403 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =114
3105 22:58:27.117582 DQ4 =122, DQ5 =114, DQ6 =126, DQ7 =126
3106 22:58:27.120979 DQ8 =98, DQ9 =94, DQ10 =108, DQ11 =104
3107 22:58:27.124463 DQ12 =112, DQ13 =110, DQ14 =120, DQ15 =114
3108 22:58:27.124551
3109 22:58:27.124615
3110 22:58:27.134454 [DQSOSCAuto] RK1, (LSB)MR18= 0xdf4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 405 ps
3111 22:58:27.134553 CH0 RK1: MR19=403, MR18=DF4
3112 22:58:27.140642 CH0_RK1: MR19=0x403, MR18=0xDF4, DQSOSC=405, MR23=63, INC=39, DEC=26
3113 22:58:27.144122 [RxdqsGatingPostProcess] freq 1200
3114 22:58:27.150673 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3115 22:58:27.154363 best DQS0 dly(2T, 0.5T) = (0, 11)
3116 22:58:27.157863 best DQS1 dly(2T, 0.5T) = (0, 11)
3117 22:58:27.160794 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3118 22:58:27.164187 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3119 22:58:27.164291 best DQS0 dly(2T, 0.5T) = (0, 11)
3120 22:58:27.167550 best DQS1 dly(2T, 0.5T) = (0, 11)
3121 22:58:27.170977 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3122 22:58:27.174415 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3123 22:58:27.177725 Pre-setting of DQS Precalculation
3124 22:58:27.184394 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3125 22:58:27.184488 ==
3126 22:58:27.187814 Dram Type= 6, Freq= 0, CH_1, rank 0
3127 22:58:27.190726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3128 22:58:27.190835 ==
3129 22:58:27.197592 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3130 22:58:27.203931 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3131 22:58:27.210661 [CA 0] Center 37 (7~68) winsize 62
3132 22:58:27.214064 [CA 1] Center 37 (7~68) winsize 62
3133 22:58:27.217458 [CA 2] Center 35 (5~65) winsize 61
3134 22:58:27.220830 [CA 3] Center 34 (4~65) winsize 62
3135 22:58:27.224205 [CA 4] Center 34 (3~65) winsize 63
3136 22:58:27.227595 [CA 5] Center 33 (3~64) winsize 62
3137 22:58:27.227678
3138 22:58:27.231033 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3139 22:58:27.231141
3140 22:58:27.233929 [CATrainingPosCal] consider 1 rank data
3141 22:58:27.237337 u2DelayCellTimex100 = 270/100 ps
3142 22:58:27.240829 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3143 22:58:27.244257 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3144 22:58:27.250605 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3145 22:58:27.253915 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3146 22:58:27.257480 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
3147 22:58:27.260597 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3148 22:58:27.260700
3149 22:58:27.264309 CA PerBit enable=1, Macro0, CA PI delay=33
3150 22:58:27.264384
3151 22:58:27.267725 [CBTSetCACLKResult] CA Dly = 33
3152 22:58:27.267825 CS Dly: 5 (0~36)
3153 22:58:27.270546 ==
3154 22:58:27.270644 Dram Type= 6, Freq= 0, CH_1, rank 1
3155 22:58:27.277165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3156 22:58:27.277239 ==
3157 22:58:27.281034 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3158 22:58:27.287389 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3159 22:58:27.296629 [CA 0] Center 38 (8~68) winsize 61
3160 22:58:27.300039 [CA 1] Center 38 (7~69) winsize 63
3161 22:58:27.303321 [CA 2] Center 35 (5~66) winsize 62
3162 22:58:27.306361 [CA 3] Center 35 (5~65) winsize 61
3163 22:58:27.309699 [CA 4] Center 35 (5~65) winsize 61
3164 22:58:27.313009 [CA 5] Center 34 (4~64) winsize 61
3165 22:58:27.313108
3166 22:58:27.316453 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3167 22:58:27.316551
3168 22:58:27.319813 [CATrainingPosCal] consider 2 rank data
3169 22:58:27.323220 u2DelayCellTimex100 = 270/100 ps
3170 22:58:27.326495 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3171 22:58:27.329905 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3172 22:58:27.336606 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3173 22:58:27.340016 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3174 22:58:27.343131 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3175 22:58:27.346346 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3176 22:58:27.346455
3177 22:58:27.349785 CA PerBit enable=1, Macro0, CA PI delay=34
3178 22:58:27.349893
3179 22:58:27.353180 [CBTSetCACLKResult] CA Dly = 34
3180 22:58:27.353287 CS Dly: 6 (0~38)
3181 22:58:27.353387
3182 22:58:27.356587 ----->DramcWriteLeveling(PI) begin...
3183 22:58:27.359847 ==
3184 22:58:27.362978 Dram Type= 6, Freq= 0, CH_1, rank 0
3185 22:58:27.366229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3186 22:58:27.366303 ==
3187 22:58:27.370046 Write leveling (Byte 0): 24 => 24
3188 22:58:27.372978 Write leveling (Byte 1): 28 => 28
3189 22:58:27.376261 DramcWriteLeveling(PI) end<-----
3190 22:58:27.376373
3191 22:58:27.376469 ==
3192 22:58:27.379437 Dram Type= 6, Freq= 0, CH_1, rank 0
3193 22:58:27.382887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3194 22:58:27.382991 ==
3195 22:58:27.386715 [Gating] SW mode calibration
3196 22:58:27.392958 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3197 22:58:27.396474 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3198 22:58:27.402857 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3199 22:58:27.406267 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3200 22:58:27.409575 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3201 22:58:27.416171 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3202 22:58:27.419582 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3203 22:58:27.423027 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3204 22:58:27.429654 0 15 24 | B1->B0 | 2d2d 2626 | 0 0 | (0 1) (1 0)
3205 22:58:27.432938 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3206 22:58:27.436427 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3207 22:58:27.442784 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3208 22:58:27.446027 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3209 22:58:27.449778 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3210 22:58:27.456095 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3211 22:58:27.459531 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3212 22:58:27.462889 1 0 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3213 22:58:27.469379 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3214 22:58:27.472704 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 22:58:27.475950 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3216 22:58:27.482643 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 22:58:27.485823 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3218 22:58:27.489182 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 22:58:27.496024 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3220 22:58:27.499383 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3221 22:58:27.502269 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3222 22:58:27.509077 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 22:58:27.512511 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 22:58:27.515644 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 22:58:27.522632 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 22:58:27.526044 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 22:58:27.529085 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 22:58:27.535665 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 22:58:27.539293 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 22:58:27.542598 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 22:58:27.549053 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 22:58:27.552424 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 22:58:27.555721 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 22:58:27.559275 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 22:58:27.565649 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3236 22:58:27.568836 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3237 22:58:27.572199 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3238 22:58:27.575547 Total UI for P1: 0, mck2ui 16
3239 22:58:27.578778 best dqsien dly found for B0: ( 1, 3, 22)
3240 22:58:27.581980 Total UI for P1: 0, mck2ui 16
3241 22:58:27.585739 best dqsien dly found for B1: ( 1, 3, 24)
3242 22:58:27.589095 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3243 22:58:27.592245 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3244 22:58:27.592331
3245 22:58:27.598933 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3246 22:58:27.602467 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3247 22:58:27.605888 [Gating] SW calibration Done
3248 22:58:27.605972 ==
3249 22:58:27.608701 Dram Type= 6, Freq= 0, CH_1, rank 0
3250 22:58:27.612204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3251 22:58:27.612288 ==
3252 22:58:27.612371 RX Vref Scan: 0
3253 22:58:27.612449
3254 22:58:27.615679 RX Vref 0 -> 0, step: 1
3255 22:58:27.615762
3256 22:58:27.619046 RX Delay -40 -> 252, step: 8
3257 22:58:27.622069 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3258 22:58:27.625528 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3259 22:58:27.632346 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3260 22:58:27.635246 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3261 22:58:27.638592 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3262 22:58:27.642012 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3263 22:58:27.645503 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3264 22:58:27.652160 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3265 22:58:27.655484 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3266 22:58:27.658697 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3267 22:58:27.662079 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3268 22:58:27.665669 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3269 22:58:27.672119 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3270 22:58:27.675399 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3271 22:58:27.678776 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3272 22:58:27.682210 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3273 22:58:27.682295 ==
3274 22:58:27.685098 Dram Type= 6, Freq= 0, CH_1, rank 0
3275 22:58:27.688609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3276 22:58:27.691669 ==
3277 22:58:27.691753 DQS Delay:
3278 22:58:27.691836 DQS0 = 0, DQS1 = 0
3279 22:58:27.695423 DQM Delay:
3280 22:58:27.695507 DQM0 = 119, DQM1 = 112
3281 22:58:27.698684 DQ Delay:
3282 22:58:27.701606 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3283 22:58:27.705007 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3284 22:58:27.708572 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3285 22:58:27.711837 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3286 22:58:27.711978
3287 22:58:27.712063
3288 22:58:27.712143 ==
3289 22:58:27.714857 Dram Type= 6, Freq= 0, CH_1, rank 0
3290 22:58:27.718396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3291 22:58:27.718482 ==
3292 22:58:27.721759
3293 22:58:27.721842
3294 22:58:27.721927 TX Vref Scan disable
3295 22:58:27.725068 == TX Byte 0 ==
3296 22:58:27.728349 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3297 22:58:27.731709 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3298 22:58:27.735141 == TX Byte 1 ==
3299 22:58:27.738034 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3300 22:58:27.741402 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3301 22:58:27.741516 ==
3302 22:58:27.745018 Dram Type= 6, Freq= 0, CH_1, rank 0
3303 22:58:27.751710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3304 22:58:27.751813 ==
3305 22:58:27.762311 TX Vref=22, minBit 3, minWin=24, winSum=403
3306 22:58:27.765292 TX Vref=24, minBit 1, minWin=25, winSum=410
3307 22:58:27.768631 TX Vref=26, minBit 9, minWin=25, winSum=419
3308 22:58:27.772129 TX Vref=28, minBit 10, minWin=25, winSum=423
3309 22:58:27.775557 TX Vref=30, minBit 10, minWin=25, winSum=422
3310 22:58:27.782278 TX Vref=32, minBit 14, minWin=25, winSum=422
3311 22:58:27.785615 [TxChooseVref] Worse bit 10, Min win 25, Win sum 423, Final Vref 28
3312 22:58:27.785701
3313 22:58:27.788500 Final TX Range 1 Vref 28
3314 22:58:27.788587
3315 22:58:27.788691 ==
3316 22:58:27.791881 Dram Type= 6, Freq= 0, CH_1, rank 0
3317 22:58:27.795172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3318 22:58:27.798596 ==
3319 22:58:27.798681
3320 22:58:27.798766
3321 22:58:27.798845 TX Vref Scan disable
3322 22:58:27.802258 == TX Byte 0 ==
3323 22:58:27.805372 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3324 22:58:27.812160 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3325 22:58:27.812247 == TX Byte 1 ==
3326 22:58:27.815542 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3327 22:58:27.821848 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3328 22:58:27.821934
3329 22:58:27.822020 [DATLAT]
3330 22:58:27.822099 Freq=1200, CH1 RK0
3331 22:58:27.822177
3332 22:58:27.825694 DATLAT Default: 0xd
3333 22:58:27.825779 0, 0xFFFF, sum = 0
3334 22:58:27.828612 1, 0xFFFF, sum = 0
3335 22:58:27.831833 2, 0xFFFF, sum = 0
3336 22:58:27.831919 3, 0xFFFF, sum = 0
3337 22:58:27.835313 4, 0xFFFF, sum = 0
3338 22:58:27.835400 5, 0xFFFF, sum = 0
3339 22:58:27.838666 6, 0xFFFF, sum = 0
3340 22:58:27.838782 7, 0xFFFF, sum = 0
3341 22:58:27.841689 8, 0xFFFF, sum = 0
3342 22:58:27.841801 9, 0xFFFF, sum = 0
3343 22:58:27.845131 10, 0xFFFF, sum = 0
3344 22:58:27.845209 11, 0xFFFF, sum = 0
3345 22:58:27.848695 12, 0x0, sum = 1
3346 22:58:27.848809 13, 0x0, sum = 2
3347 22:58:27.852101 14, 0x0, sum = 3
3348 22:58:27.852212 15, 0x0, sum = 4
3349 22:58:27.855148 best_step = 13
3350 22:58:27.855221
3351 22:58:27.855283 ==
3352 22:58:27.858643 Dram Type= 6, Freq= 0, CH_1, rank 0
3353 22:58:27.862024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3354 22:58:27.862108 ==
3355 22:58:27.862181 RX Vref Scan: 1
3356 22:58:27.862246
3357 22:58:27.865280 Set Vref Range= 32 -> 127
3358 22:58:27.865364
3359 22:58:27.868587 RX Vref 32 -> 127, step: 1
3360 22:58:27.868701
3361 22:58:27.871674 RX Delay -13 -> 252, step: 4
3362 22:58:27.871761
3363 22:58:27.875483 Set Vref, RX VrefLevel [Byte0]: 32
3364 22:58:27.878483 [Byte1]: 32
3365 22:58:27.878557
3366 22:58:27.881716 Set Vref, RX VrefLevel [Byte0]: 33
3367 22:58:27.885006 [Byte1]: 33
3368 22:58:27.888382
3369 22:58:27.888453 Set Vref, RX VrefLevel [Byte0]: 34
3370 22:58:27.891904 [Byte1]: 34
3371 22:58:27.896664
3372 22:58:27.896751 Set Vref, RX VrefLevel [Byte0]: 35
3373 22:58:27.900142 [Byte1]: 35
3374 22:58:27.904454
3375 22:58:27.904566 Set Vref, RX VrefLevel [Byte0]: 36
3376 22:58:27.907661 [Byte1]: 36
3377 22:58:27.912518
3378 22:58:27.912619 Set Vref, RX VrefLevel [Byte0]: 37
3379 22:58:27.915428 [Byte1]: 37
3380 22:58:27.920375
3381 22:58:27.920475 Set Vref, RX VrefLevel [Byte0]: 38
3382 22:58:27.923729 [Byte1]: 38
3383 22:58:27.928083
3384 22:58:27.928178 Set Vref, RX VrefLevel [Byte0]: 39
3385 22:58:27.931500 [Byte1]: 39
3386 22:58:27.936020
3387 22:58:27.936111 Set Vref, RX VrefLevel [Byte0]: 40
3388 22:58:27.939060 [Byte1]: 40
3389 22:58:27.944030
3390 22:58:27.944129 Set Vref, RX VrefLevel [Byte0]: 41
3391 22:58:27.947315 [Byte1]: 41
3392 22:58:27.951599
3393 22:58:27.951776 Set Vref, RX VrefLevel [Byte0]: 42
3394 22:58:27.955243 [Byte1]: 42
3395 22:58:27.959648
3396 22:58:27.959749 Set Vref, RX VrefLevel [Byte0]: 43
3397 22:58:27.963049 [Byte1]: 43
3398 22:58:27.967380
3399 22:58:27.967483 Set Vref, RX VrefLevel [Byte0]: 44
3400 22:58:27.970976 [Byte1]: 44
3401 22:58:27.975248
3402 22:58:27.975329 Set Vref, RX VrefLevel [Byte0]: 45
3403 22:58:27.978724 [Byte1]: 45
3404 22:58:27.983087
3405 22:58:27.983173 Set Vref, RX VrefLevel [Byte0]: 46
3406 22:58:27.986819 [Byte1]: 46
3407 22:58:27.991054
3408 22:58:27.991136 Set Vref, RX VrefLevel [Byte0]: 47
3409 22:58:27.994446 [Byte1]: 47
3410 22:58:27.999299
3411 22:58:27.999381 Set Vref, RX VrefLevel [Byte0]: 48
3412 22:58:28.002287 [Byte1]: 48
3413 22:58:28.007099
3414 22:58:28.007183 Set Vref, RX VrefLevel [Byte0]: 49
3415 22:58:28.010489 [Byte1]: 49
3416 22:58:28.014836
3417 22:58:28.014915 Set Vref, RX VrefLevel [Byte0]: 50
3418 22:58:28.018339 [Byte1]: 50
3419 22:58:28.022837
3420 22:58:28.022934 Set Vref, RX VrefLevel [Byte0]: 51
3421 22:58:28.025721 [Byte1]: 51
3422 22:58:28.030559
3423 22:58:28.030638 Set Vref, RX VrefLevel [Byte0]: 52
3424 22:58:28.034105 [Byte1]: 52
3425 22:58:28.038277
3426 22:58:28.038350 Set Vref, RX VrefLevel [Byte0]: 53
3427 22:58:28.041573 [Byte1]: 53
3428 22:58:28.046538
3429 22:58:28.046621 Set Vref, RX VrefLevel [Byte0]: 54
3430 22:58:28.049513 [Byte1]: 54
3431 22:58:28.054507
3432 22:58:28.054588 Set Vref, RX VrefLevel [Byte0]: 55
3433 22:58:28.057356 [Byte1]: 55
3434 22:58:28.062046
3435 22:58:28.062132 Set Vref, RX VrefLevel [Byte0]: 56
3436 22:58:28.065424 [Byte1]: 56
3437 22:58:28.069827
3438 22:58:28.069900 Set Vref, RX VrefLevel [Byte0]: 57
3439 22:58:28.073471 [Byte1]: 57
3440 22:58:28.077617
3441 22:58:28.077706 Set Vref, RX VrefLevel [Byte0]: 58
3442 22:58:28.081042 [Byte1]: 58
3443 22:58:28.085523
3444 22:58:28.085599 Set Vref, RX VrefLevel [Byte0]: 59
3445 22:58:28.088932 [Byte1]: 59
3446 22:58:28.093602
3447 22:58:28.093690 Set Vref, RX VrefLevel [Byte0]: 60
3448 22:58:28.096990 [Byte1]: 60
3449 22:58:28.101763
3450 22:58:28.101841 Set Vref, RX VrefLevel [Byte0]: 61
3451 22:58:28.104647 [Byte1]: 61
3452 22:58:28.109554
3453 22:58:28.109636 Set Vref, RX VrefLevel [Byte0]: 62
3454 22:58:28.113041 [Byte1]: 62
3455 22:58:28.117520
3456 22:58:28.117607 Set Vref, RX VrefLevel [Byte0]: 63
3457 22:58:28.120878 [Byte1]: 63
3458 22:58:28.125262
3459 22:58:28.128411 Set Vref, RX VrefLevel [Byte0]: 64
3460 22:58:28.131731 [Byte1]: 64
3461 22:58:28.131811
3462 22:58:28.134977 Set Vref, RX VrefLevel [Byte0]: 65
3463 22:58:28.138448 [Byte1]: 65
3464 22:58:28.138525
3465 22:58:28.141853 Final RX Vref Byte 0 = 53 to rank0
3466 22:58:28.145181 Final RX Vref Byte 1 = 52 to rank0
3467 22:58:28.148598 Final RX Vref Byte 0 = 53 to rank1
3468 22:58:28.151594 Final RX Vref Byte 1 = 52 to rank1==
3469 22:58:28.154949 Dram Type= 6, Freq= 0, CH_1, rank 0
3470 22:58:28.158338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3471 22:58:28.158431 ==
3472 22:58:28.161706 DQS Delay:
3473 22:58:28.161786 DQS0 = 0, DQS1 = 0
3474 22:58:28.164885 DQM Delay:
3475 22:58:28.164968 DQM0 = 119, DQM1 = 112
3476 22:58:28.165033 DQ Delay:
3477 22:58:28.168339 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3478 22:58:28.175187 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =118
3479 22:58:28.178323 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3480 22:58:28.181701 DQ12 =122, DQ13 =118, DQ14 =120, DQ15 =118
3481 22:58:28.181786
3482 22:58:28.181850
3483 22:58:28.188505 [DQSOSCAuto] RK0, (LSB)MR18= 0x317, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3484 22:58:28.191518 CH1 RK0: MR19=404, MR18=317
3485 22:58:28.198628 CH1_RK0: MR19=0x404, MR18=0x317, DQSOSC=401, MR23=63, INC=40, DEC=27
3486 22:58:28.198716
3487 22:58:28.201827 ----->DramcWriteLeveling(PI) begin...
3488 22:58:28.201913 ==
3489 22:58:28.204815 Dram Type= 6, Freq= 0, CH_1, rank 1
3490 22:58:28.208217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3491 22:58:28.208302 ==
3492 22:58:28.211418 Write leveling (Byte 0): 25 => 25
3493 22:58:28.214823 Write leveling (Byte 1): 28 => 28
3494 22:58:28.218228 DramcWriteLeveling(PI) end<-----
3495 22:58:28.218311
3496 22:58:28.218377 ==
3497 22:58:28.221768 Dram Type= 6, Freq= 0, CH_1, rank 1
3498 22:58:28.225045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3499 22:58:28.228048 ==
3500 22:58:28.228131 [Gating] SW mode calibration
3501 22:58:28.234870 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3502 22:58:28.241472 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3503 22:58:28.244821 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3504 22:58:28.251463 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3505 22:58:28.254454 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3506 22:58:28.257817 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3507 22:58:28.264667 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3508 22:58:28.267987 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3509 22:58:28.271295 0 15 24 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 0)
3510 22:58:28.277667 0 15 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
3511 22:58:28.281381 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3512 22:58:28.284596 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3513 22:58:28.291103 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3514 22:58:28.294524 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3515 22:58:28.297916 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3516 22:58:28.304430 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3517 22:58:28.307722 1 0 24 | B1->B0 | 3f3f 3030 | 0 1 | (0 0) (0 0)
3518 22:58:28.311055 1 0 28 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
3519 22:58:28.317582 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3520 22:58:28.321024 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3521 22:58:28.324433 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3522 22:58:28.331073 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3523 22:58:28.334089 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3524 22:58:28.337481 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3525 22:58:28.344307 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3526 22:58:28.347564 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3527 22:58:28.350430 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 22:58:28.354247 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 22:58:28.360525 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 22:58:28.363913 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 22:58:28.367234 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 22:58:28.373862 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 22:58:28.377236 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 22:58:28.380634 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 22:58:28.386862 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 22:58:28.390117 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 22:58:28.393464 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 22:58:28.400299 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 22:58:28.403609 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 22:58:28.406741 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 22:58:28.413507 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3542 22:58:28.416986 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3543 22:58:28.419949 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3544 22:58:28.423427 Total UI for P1: 0, mck2ui 16
3545 22:58:28.426767 best dqsien dly found for B0: ( 1, 3, 26)
3546 22:58:28.430133 Total UI for P1: 0, mck2ui 16
3547 22:58:28.433133 best dqsien dly found for B1: ( 1, 3, 26)
3548 22:58:28.436477 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3549 22:58:28.439645 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3550 22:58:28.443056
3551 22:58:28.446517 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3552 22:58:28.449966 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3553 22:58:28.453072 [Gating] SW calibration Done
3554 22:58:28.453161 ==
3555 22:58:28.456335 Dram Type= 6, Freq= 0, CH_1, rank 1
3556 22:58:28.459721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3557 22:58:28.459798 ==
3558 22:58:28.462708 RX Vref Scan: 0
3559 22:58:28.462781
3560 22:58:28.462844 RX Vref 0 -> 0, step: 1
3561 22:58:28.462936
3562 22:58:28.466158 RX Delay -40 -> 252, step: 8
3563 22:58:28.469531 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3564 22:58:28.472984 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3565 22:58:28.479663 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3566 22:58:28.482587 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3567 22:58:28.486074 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3568 22:58:28.489444 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3569 22:58:28.496175 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3570 22:58:28.499117 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3571 22:58:28.502570 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3572 22:58:28.505945 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3573 22:58:28.509328 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3574 22:58:28.515772 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3575 22:58:28.519291 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3576 22:58:28.522623 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3577 22:58:28.525571 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3578 22:58:28.528978 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3579 22:58:28.532405 ==
3580 22:58:28.532532 Dram Type= 6, Freq= 0, CH_1, rank 1
3581 22:58:28.539133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3582 22:58:28.539256 ==
3583 22:58:28.539374 DQS Delay:
3584 22:58:28.542520 DQS0 = 0, DQS1 = 0
3585 22:58:28.542606 DQM Delay:
3586 22:58:28.545895 DQM0 = 120, DQM1 = 113
3587 22:58:28.545979 DQ Delay:
3588 22:58:28.548741 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =123
3589 22:58:28.552138 DQ4 =119, DQ5 =131, DQ6 =123, DQ7 =115
3590 22:58:28.555459 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3591 22:58:28.558650 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =123
3592 22:58:28.558761
3593 22:58:28.558856
3594 22:58:28.558961 ==
3595 22:58:28.562125 Dram Type= 6, Freq= 0, CH_1, rank 1
3596 22:58:28.568539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3597 22:58:28.568651 ==
3598 22:58:28.568756
3599 22:58:28.568876
3600 22:58:28.568971 TX Vref Scan disable
3601 22:58:28.572488 == TX Byte 0 ==
3602 22:58:28.575487 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3603 22:58:28.582203 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3604 22:58:28.582324 == TX Byte 1 ==
3605 22:58:28.585573 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3606 22:58:28.591782 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3607 22:58:28.591890 ==
3608 22:58:28.595453 Dram Type= 6, Freq= 0, CH_1, rank 1
3609 22:58:28.598330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3610 22:58:28.598436 ==
3611 22:58:28.610275 TX Vref=22, minBit 1, minWin=25, winSum=414
3612 22:58:28.613400 TX Vref=24, minBit 9, minWin=25, winSum=422
3613 22:58:28.616591 TX Vref=26, minBit 0, minWin=26, winSum=427
3614 22:58:28.619825 TX Vref=28, minBit 1, minWin=26, winSum=429
3615 22:58:28.623015 TX Vref=30, minBit 8, minWin=26, winSum=427
3616 22:58:28.629863 TX Vref=32, minBit 7, minWin=26, winSum=426
3617 22:58:28.633252 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 28
3618 22:58:28.633360
3619 22:58:28.636463 Final TX Range 1 Vref 28
3620 22:58:28.636568
3621 22:58:28.636678 ==
3622 22:58:28.639877 Dram Type= 6, Freq= 0, CH_1, rank 1
3623 22:58:28.642838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3624 22:58:28.646242 ==
3625 22:58:28.646363
3626 22:58:28.646461
3627 22:58:28.646555 TX Vref Scan disable
3628 22:58:28.649958 == TX Byte 0 ==
3629 22:58:28.653362 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3630 22:58:28.659686 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3631 22:58:28.659799 == TX Byte 1 ==
3632 22:58:28.663068 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3633 22:58:28.669663 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3634 22:58:28.669776
3635 22:58:28.669888 [DATLAT]
3636 22:58:28.669983 Freq=1200, CH1 RK1
3637 22:58:28.670077
3638 22:58:28.672676 DATLAT Default: 0xd
3639 22:58:28.676136 0, 0xFFFF, sum = 0
3640 22:58:28.676255 1, 0xFFFF, sum = 0
3641 22:58:28.679524 2, 0xFFFF, sum = 0
3642 22:58:28.679630 3, 0xFFFF, sum = 0
3643 22:58:28.682934 4, 0xFFFF, sum = 0
3644 22:58:28.683061 5, 0xFFFF, sum = 0
3645 22:58:28.685741 6, 0xFFFF, sum = 0
3646 22:58:28.685862 7, 0xFFFF, sum = 0
3647 22:58:28.689142 8, 0xFFFF, sum = 0
3648 22:58:28.689253 9, 0xFFFF, sum = 0
3649 22:58:28.692535 10, 0xFFFF, sum = 0
3650 22:58:28.692643 11, 0xFFFF, sum = 0
3651 22:58:28.695951 12, 0x0, sum = 1
3652 22:58:28.696064 13, 0x0, sum = 2
3653 22:58:28.699134 14, 0x0, sum = 3
3654 22:58:28.699259 15, 0x0, sum = 4
3655 22:58:28.702372 best_step = 13
3656 22:58:28.702499
3657 22:58:28.702595 ==
3658 22:58:28.705783 Dram Type= 6, Freq= 0, CH_1, rank 1
3659 22:58:28.709210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3660 22:58:28.709320 ==
3661 22:58:28.712191 RX Vref Scan: 0
3662 22:58:28.712300
3663 22:58:28.712393 RX Vref 0 -> 0, step: 1
3664 22:58:28.712508
3665 22:58:28.715636 RX Delay -13 -> 252, step: 4
3666 22:58:28.722281 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3667 22:58:28.725384 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3668 22:58:28.729273 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3669 22:58:28.732165 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3670 22:58:28.735624 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3671 22:58:28.742504 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3672 22:58:28.745546 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3673 22:58:28.748845 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3674 22:58:28.752093 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3675 22:58:28.755518 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3676 22:58:28.762034 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3677 22:58:28.765547 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3678 22:58:28.768517 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3679 22:58:28.771854 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3680 22:58:28.775383 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3681 22:58:28.781976 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3682 22:58:28.782087 ==
3683 22:58:28.785390 Dram Type= 6, Freq= 0, CH_1, rank 1
3684 22:58:28.788559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3685 22:58:28.788670 ==
3686 22:58:28.788775 DQS Delay:
3687 22:58:28.791987 DQS0 = 0, DQS1 = 0
3688 22:58:28.792098 DQM Delay:
3689 22:58:28.794871 DQM0 = 119, DQM1 = 113
3690 22:58:28.794980 DQ Delay:
3691 22:58:28.798390 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3692 22:58:28.801700 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3693 22:58:28.804817 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =106
3694 22:58:28.808374 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3695 22:58:28.811656
3696 22:58:28.811762
3697 22:58:28.818459 [DQSOSCAuto] RK1, (LSB)MR18= 0x9ed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 406 ps
3698 22:58:28.821804 CH1 RK1: MR19=403, MR18=9ED
3699 22:58:28.828213 CH1_RK1: MR19=0x403, MR18=0x9ED, DQSOSC=406, MR23=63, INC=39, DEC=26
3700 22:58:28.831531 [RxdqsGatingPostProcess] freq 1200
3701 22:58:28.834969 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3702 22:58:28.838078 best DQS0 dly(2T, 0.5T) = (0, 11)
3703 22:58:28.841353 best DQS1 dly(2T, 0.5T) = (0, 11)
3704 22:58:28.844897 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3705 22:58:28.848247 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3706 22:58:28.851208 best DQS0 dly(2T, 0.5T) = (0, 11)
3707 22:58:28.854618 best DQS1 dly(2T, 0.5T) = (0, 11)
3708 22:58:28.858245 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3709 22:58:28.861158 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3710 22:58:28.864640 Pre-setting of DQS Precalculation
3711 22:58:28.867559 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3712 22:58:28.877676 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3713 22:58:28.884234 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3714 22:58:28.884338
3715 22:58:28.884434
3716 22:58:28.887446 [Calibration Summary] 2400 Mbps
3717 22:58:28.887545 CH 0, Rank 0
3718 22:58:28.890653 SW Impedance : PASS
3719 22:58:28.890754 DUTY Scan : NO K
3720 22:58:28.893829 ZQ Calibration : PASS
3721 22:58:28.897714 Jitter Meter : NO K
3722 22:58:28.897791 CBT Training : PASS
3723 22:58:28.900699 Write leveling : PASS
3724 22:58:28.904186 RX DQS gating : PASS
3725 22:58:28.904259 RX DQ/DQS(RDDQC) : PASS
3726 22:58:28.907472 TX DQ/DQS : PASS
3727 22:58:28.910698 RX DATLAT : PASS
3728 22:58:28.910800 RX DQ/DQS(Engine): PASS
3729 22:58:28.914078 TX OE : NO K
3730 22:58:28.914176 All Pass.
3731 22:58:28.914266
3732 22:58:28.917539 CH 0, Rank 1
3733 22:58:28.917655 SW Impedance : PASS
3734 22:58:28.920409 DUTY Scan : NO K
3735 22:58:28.920524 ZQ Calibration : PASS
3736 22:58:28.923613 Jitter Meter : NO K
3737 22:58:28.927031 CBT Training : PASS
3738 22:58:28.927148 Write leveling : PASS
3739 22:58:28.930297 RX DQS gating : PASS
3740 22:58:28.934000 RX DQ/DQS(RDDQC) : PASS
3741 22:58:28.934112 TX DQ/DQS : PASS
3742 22:58:28.937006 RX DATLAT : PASS
3743 22:58:28.940498 RX DQ/DQS(Engine): PASS
3744 22:58:28.940610 TX OE : NO K
3745 22:58:28.943844 All Pass.
3746 22:58:28.943948
3747 22:58:28.944030 CH 1, Rank 0
3748 22:58:28.946808 SW Impedance : PASS
3749 22:58:28.946918 DUTY Scan : NO K
3750 22:58:28.950311 ZQ Calibration : PASS
3751 22:58:28.953628 Jitter Meter : NO K
3752 22:58:28.953740 CBT Training : PASS
3753 22:58:28.957029 Write leveling : PASS
3754 22:58:28.960353 RX DQS gating : PASS
3755 22:58:28.960475 RX DQ/DQS(RDDQC) : PASS
3756 22:58:28.963717 TX DQ/DQS : PASS
3757 22:58:28.966654 RX DATLAT : PASS
3758 22:58:28.966764 RX DQ/DQS(Engine): PASS
3759 22:58:28.970020 TX OE : NO K
3760 22:58:28.970131 All Pass.
3761 22:58:28.970228
3762 22:58:28.973546 CH 1, Rank 1
3763 22:58:28.973655 SW Impedance : PASS
3764 22:58:28.976778 DUTY Scan : NO K
3765 22:58:28.980234 ZQ Calibration : PASS
3766 22:58:28.980348 Jitter Meter : NO K
3767 22:58:28.983335 CBT Training : PASS
3768 22:58:28.983443 Write leveling : PASS
3769 22:58:28.986581 RX DQS gating : PASS
3770 22:58:28.990018 RX DQ/DQS(RDDQC) : PASS
3771 22:58:28.990129 TX DQ/DQS : PASS
3772 22:58:28.993411 RX DATLAT : PASS
3773 22:58:28.996536 RX DQ/DQS(Engine): PASS
3774 22:58:28.996640 TX OE : NO K
3775 22:58:28.999877 All Pass.
3776 22:58:28.999979
3777 22:58:29.000072 DramC Write-DBI off
3778 22:58:29.003554 PER_BANK_REFRESH: Hybrid Mode
3779 22:58:29.006455 TX_TRACKING: ON
3780 22:58:29.012976 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3781 22:58:29.016301 [FAST_K] Save calibration result to emmc
3782 22:58:29.023062 dramc_set_vcore_voltage set vcore to 650000
3783 22:58:29.023145 Read voltage for 600, 5
3784 22:58:29.026372 Vio18 = 0
3785 22:58:29.026455 Vcore = 650000
3786 22:58:29.026521 Vdram = 0
3787 22:58:29.026582 Vddq = 0
3788 22:58:29.029629 Vmddr = 0
3789 22:58:29.032672 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3790 22:58:29.039401 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3791 22:58:29.042643 MEM_TYPE=3, freq_sel=19
3792 22:58:29.042758 sv_algorithm_assistance_LP4_1600
3793 22:58:29.049536 ============ PULL DRAM RESETB DOWN ============
3794 22:58:29.052459 ========== PULL DRAM RESETB DOWN end =========
3795 22:58:29.055886 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3796 22:58:29.059335 ===================================
3797 22:58:29.062759 LPDDR4 DRAM CONFIGURATION
3798 22:58:29.066050 ===================================
3799 22:58:29.069525 EX_ROW_EN[0] = 0x0
3800 22:58:29.069631 EX_ROW_EN[1] = 0x0
3801 22:58:29.072406 LP4Y_EN = 0x0
3802 22:58:29.072504 WORK_FSP = 0x0
3803 22:58:29.075835 WL = 0x2
3804 22:58:29.075937 RL = 0x2
3805 22:58:29.079209 BL = 0x2
3806 22:58:29.079308 RPST = 0x0
3807 22:58:29.082216 RD_PRE = 0x0
3808 22:58:29.082327 WR_PRE = 0x1
3809 22:58:29.085570 WR_PST = 0x0
3810 22:58:29.088783 DBI_WR = 0x0
3811 22:58:29.088876 DBI_RD = 0x0
3812 22:58:29.092355 OTF = 0x1
3813 22:58:29.095251 ===================================
3814 22:58:29.098635 ===================================
3815 22:58:29.098733 ANA top config
3816 22:58:29.102262 ===================================
3817 22:58:29.105301 DLL_ASYNC_EN = 0
3818 22:58:29.108626 ALL_SLAVE_EN = 1
3819 22:58:29.108725 NEW_RANK_MODE = 1
3820 22:58:29.112132 DLL_IDLE_MODE = 1
3821 22:58:29.115427 LP45_APHY_COMB_EN = 1
3822 22:58:29.118564 TX_ODT_DIS = 1
3823 22:58:29.118672 NEW_8X_MODE = 1
3824 22:58:29.121549 ===================================
3825 22:58:29.125031 ===================================
3826 22:58:29.128476 data_rate = 1200
3827 22:58:29.131425 CKR = 1
3828 22:58:29.134715 DQ_P2S_RATIO = 8
3829 22:58:29.138042 ===================================
3830 22:58:29.141168 CA_P2S_RATIO = 8
3831 22:58:29.144907 DQ_CA_OPEN = 0
3832 22:58:29.147854 DQ_SEMI_OPEN = 0
3833 22:58:29.147935 CA_SEMI_OPEN = 0
3834 22:58:29.151241 CA_FULL_RATE = 0
3835 22:58:29.154725 DQ_CKDIV4_EN = 1
3836 22:58:29.157622 CA_CKDIV4_EN = 1
3837 22:58:29.160995 CA_PREDIV_EN = 0
3838 22:58:29.164375 PH8_DLY = 0
3839 22:58:29.164458 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3840 22:58:29.167680 DQ_AAMCK_DIV = 4
3841 22:58:29.170916 CA_AAMCK_DIV = 4
3842 22:58:29.174331 CA_ADMCK_DIV = 4
3843 22:58:29.177754 DQ_TRACK_CA_EN = 0
3844 22:58:29.181208 CA_PICK = 600
3845 22:58:29.184637 CA_MCKIO = 600
3846 22:58:29.184721 MCKIO_SEMI = 0
3847 22:58:29.187611 PLL_FREQ = 2288
3848 22:58:29.191125 DQ_UI_PI_RATIO = 32
3849 22:58:29.194430 CA_UI_PI_RATIO = 0
3850 22:58:29.197315 ===================================
3851 22:58:29.200865 ===================================
3852 22:58:29.203848 memory_type:LPDDR4
3853 22:58:29.203932 GP_NUM : 10
3854 22:58:29.207429 SRAM_EN : 1
3855 22:58:29.210637 MD32_EN : 0
3856 22:58:29.214200 ===================================
3857 22:58:29.214284 [ANA_INIT] >>>>>>>>>>>>>>
3858 22:58:29.217164 <<<<<< [CONFIGURE PHASE]: ANA_TX
3859 22:58:29.220784 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3860 22:58:29.224036 ===================================
3861 22:58:29.227709 data_rate = 1200,PCW = 0X5800
3862 22:58:29.230511 ===================================
3863 22:58:29.233971 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3864 22:58:29.240709 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3865 22:58:29.244039 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3866 22:58:29.250554 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3867 22:58:29.253998 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3868 22:58:29.257042 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3869 22:58:29.257125 [ANA_INIT] flow start
3870 22:58:29.260412 [ANA_INIT] PLL >>>>>>>>
3871 22:58:29.263830 [ANA_INIT] PLL <<<<<<<<
3872 22:58:29.266806 [ANA_INIT] MIDPI >>>>>>>>
3873 22:58:29.266888 [ANA_INIT] MIDPI <<<<<<<<
3874 22:58:29.270067 [ANA_INIT] DLL >>>>>>>>
3875 22:58:29.273801 [ANA_INIT] flow end
3876 22:58:29.277206 ============ LP4 DIFF to SE enter ============
3877 22:58:29.280122 ============ LP4 DIFF to SE exit ============
3878 22:58:29.283514 [ANA_INIT] <<<<<<<<<<<<<
3879 22:58:29.286959 [Flow] Enable top DCM control >>>>>
3880 22:58:29.290316 [Flow] Enable top DCM control <<<<<
3881 22:58:29.293655 Enable DLL master slave shuffle
3882 22:58:29.296865 ==============================================================
3883 22:58:29.300265 Gating Mode config
3884 22:58:29.303610 ==============================================================
3885 22:58:29.306616 Config description:
3886 22:58:29.316630 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3887 22:58:29.323415 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3888 22:58:29.326678 SELPH_MODE 0: By rank 1: By Phase
3889 22:58:29.332941 ==============================================================
3890 22:58:29.336248 GAT_TRACK_EN = 1
3891 22:58:29.339622 RX_GATING_MODE = 2
3892 22:58:29.343132 RX_GATING_TRACK_MODE = 2
3893 22:58:29.346163 SELPH_MODE = 1
3894 22:58:29.349434 PICG_EARLY_EN = 1
3895 22:58:29.353022 VALID_LAT_VALUE = 1
3896 22:58:29.356381 ==============================================================
3897 22:58:29.359285 Enter into Gating configuration >>>>
3898 22:58:29.362696 Exit from Gating configuration <<<<
3899 22:58:29.366243 Enter into DVFS_PRE_config >>>>>
3900 22:58:29.379264 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3901 22:58:29.379351 Exit from DVFS_PRE_config <<<<<
3902 22:58:29.382614 Enter into PICG configuration >>>>
3903 22:58:29.385951 Exit from PICG configuration <<<<
3904 22:58:29.389584 [RX_INPUT] configuration >>>>>
3905 22:58:29.392337 [RX_INPUT] configuration <<<<<
3906 22:58:29.399055 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3907 22:58:29.402325 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3908 22:58:29.409079 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3909 22:58:29.415492 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3910 22:58:29.422070 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3911 22:58:29.429119 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3912 22:58:29.432310 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3913 22:58:29.435427 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3914 22:58:29.439091 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3915 22:58:29.445431 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3916 22:58:29.448686 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3917 22:58:29.451671 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3918 22:58:29.455358 ===================================
3919 22:58:29.458505 LPDDR4 DRAM CONFIGURATION
3920 22:58:29.461921 ===================================
3921 22:58:29.465332 EX_ROW_EN[0] = 0x0
3922 22:58:29.465415 EX_ROW_EN[1] = 0x0
3923 22:58:29.468271 LP4Y_EN = 0x0
3924 22:58:29.468354 WORK_FSP = 0x0
3925 22:58:29.471685 WL = 0x2
3926 22:58:29.471768 RL = 0x2
3927 22:58:29.475086 BL = 0x2
3928 22:58:29.475168 RPST = 0x0
3929 22:58:29.478144 RD_PRE = 0x0
3930 22:58:29.478224 WR_PRE = 0x1
3931 22:58:29.481454 WR_PST = 0x0
3932 22:58:29.481625 DBI_WR = 0x0
3933 22:58:29.485305 DBI_RD = 0x0
3934 22:58:29.488512 OTF = 0x1
3935 22:58:29.488590 ===================================
3936 22:58:29.494958 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3937 22:58:29.498360 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3938 22:58:29.501290 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3939 22:58:29.504995 ===================================
3940 22:58:29.508341 LPDDR4 DRAM CONFIGURATION
3941 22:58:29.511727 ===================================
3942 22:58:29.514664 EX_ROW_EN[0] = 0x10
3943 22:58:29.514750 EX_ROW_EN[1] = 0x0
3944 22:58:29.518136 LP4Y_EN = 0x0
3945 22:58:29.518225 WORK_FSP = 0x0
3946 22:58:29.521597 WL = 0x2
3947 22:58:29.521686 RL = 0x2
3948 22:58:29.524525 BL = 0x2
3949 22:58:29.524617 RPST = 0x0
3950 22:58:29.528162 RD_PRE = 0x0
3951 22:58:29.528239 WR_PRE = 0x1
3952 22:58:29.531371 WR_PST = 0x0
3953 22:58:29.531448 DBI_WR = 0x0
3954 22:58:29.534645 DBI_RD = 0x0
3955 22:58:29.534725 OTF = 0x1
3956 22:58:29.538058 ===================================
3957 22:58:29.544447 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3958 22:58:29.549412 nWR fixed to 30
3959 22:58:29.552753 [ModeRegInit_LP4] CH0 RK0
3960 22:58:29.552883 [ModeRegInit_LP4] CH0 RK1
3961 22:58:29.556133 [ModeRegInit_LP4] CH1 RK0
3962 22:58:29.559448 [ModeRegInit_LP4] CH1 RK1
3963 22:58:29.559529 match AC timing 17
3964 22:58:29.565907 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3965 22:58:29.569462 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3966 22:58:29.572386 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3967 22:58:29.579161 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3968 22:58:29.582510 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3969 22:58:29.582595 ==
3970 22:58:29.585655 Dram Type= 6, Freq= 0, CH_0, rank 0
3971 22:58:29.589028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3972 22:58:29.589115 ==
3973 22:58:29.595889 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3974 22:58:29.602326 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3975 22:58:29.605810 [CA 0] Center 36 (6~67) winsize 62
3976 22:58:29.608977 [CA 1] Center 36 (6~67) winsize 62
3977 22:58:29.612396 [CA 2] Center 34 (4~65) winsize 62
3978 22:58:29.615282 [CA 3] Center 34 (3~65) winsize 63
3979 22:58:29.618646 [CA 4] Center 33 (3~64) winsize 62
3980 22:58:29.622125 [CA 5] Center 33 (2~64) winsize 63
3981 22:58:29.622213
3982 22:58:29.625061 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3983 22:58:29.625148
3984 22:58:29.628644 [CATrainingPosCal] consider 1 rank data
3985 22:58:29.631932 u2DelayCellTimex100 = 270/100 ps
3986 22:58:29.635136 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3987 22:58:29.638492 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3988 22:58:29.641924 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3989 22:58:29.648477 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3990 22:58:29.651928 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3991 22:58:29.655108 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3992 22:58:29.655251
3993 22:58:29.658378 CA PerBit enable=1, Macro0, CA PI delay=33
3994 22:58:29.658475
3995 22:58:29.661724 [CBTSetCACLKResult] CA Dly = 33
3996 22:58:29.661809 CS Dly: 5 (0~36)
3997 22:58:29.661870 ==
3998 22:58:29.665056 Dram Type= 6, Freq= 0, CH_0, rank 1
3999 22:58:29.671660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4000 22:58:29.671761 ==
4001 22:58:29.674551 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4002 22:58:29.681586 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4003 22:58:29.684938 [CA 0] Center 36 (6~67) winsize 62
4004 22:58:29.688274 [CA 1] Center 36 (6~67) winsize 62
4005 22:58:29.691454 [CA 2] Center 35 (5~65) winsize 61
4006 22:58:29.694850 [CA 3] Center 34 (4~65) winsize 62
4007 22:58:29.697779 [CA 4] Center 34 (3~65) winsize 63
4008 22:58:29.701254 [CA 5] Center 33 (3~64) winsize 62
4009 22:58:29.701354
4010 22:58:29.704567 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4011 22:58:29.704667
4012 22:58:29.708048 [CATrainingPosCal] consider 2 rank data
4013 22:58:29.710951 u2DelayCellTimex100 = 270/100 ps
4014 22:58:29.714720 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4015 22:58:29.721013 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4016 22:58:29.724547 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4017 22:58:29.727573 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4018 22:58:29.730997 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4019 22:58:29.734363 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4020 22:58:29.734463
4021 22:58:29.737578 CA PerBit enable=1, Macro0, CA PI delay=33
4022 22:58:29.737654
4023 22:58:29.740858 [CBTSetCACLKResult] CA Dly = 33
4024 22:58:29.744243 CS Dly: 5 (0~37)
4025 22:58:29.744343
4026 22:58:29.747137 ----->DramcWriteLeveling(PI) begin...
4027 22:58:29.747234 ==
4028 22:58:29.750521 Dram Type= 6, Freq= 0, CH_0, rank 0
4029 22:58:29.753710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4030 22:58:29.753811 ==
4031 22:58:29.756891 Write leveling (Byte 0): 33 => 33
4032 22:58:29.760322 Write leveling (Byte 1): 30 => 30
4033 22:58:29.763662 DramcWriteLeveling(PI) end<-----
4034 22:58:29.763779
4035 22:58:29.763846 ==
4036 22:58:29.767241 Dram Type= 6, Freq= 0, CH_0, rank 0
4037 22:58:29.770421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4038 22:58:29.770523 ==
4039 22:58:29.773714 [Gating] SW mode calibration
4040 22:58:29.780002 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4041 22:58:29.786743 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4042 22:58:29.790103 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4043 22:58:29.793425 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4044 22:58:29.800131 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4045 22:58:29.803141 0 9 12 | B1->B0 | 3434 2e2e | 1 1 | (1 0) (1 0)
4046 22:58:29.806709 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4047 22:58:29.812910 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4048 22:58:29.816655 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4049 22:58:29.822825 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4050 22:58:29.826296 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4051 22:58:29.829654 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4052 22:58:29.832975 0 10 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
4053 22:58:29.839460 0 10 12 | B1->B0 | 2525 3838 | 0 0 | (0 0) (1 1)
4054 22:58:29.842667 0 10 16 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
4055 22:58:29.849184 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 22:58:29.852523 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 22:58:29.855920 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 22:58:29.862669 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 22:58:29.865911 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 22:58:29.869229 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4061 22:58:29.876027 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4062 22:58:29.878728 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 22:58:29.882282 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 22:58:29.889219 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 22:58:29.892543 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 22:58:29.895581 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 22:58:29.898829 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 22:58:29.905421 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 22:58:29.908792 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 22:58:29.915061 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 22:58:29.918580 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 22:58:29.921859 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 22:58:29.928489 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 22:58:29.931862 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 22:58:29.935267 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 22:58:29.938715 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 22:58:29.945024 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4078 22:58:29.948310 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4079 22:58:29.951506 Total UI for P1: 0, mck2ui 16
4080 22:58:29.954903 best dqsien dly found for B0: ( 0, 13, 12)
4081 22:58:29.958229 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4082 22:58:29.961625 Total UI for P1: 0, mck2ui 16
4083 22:58:29.965123 best dqsien dly found for B1: ( 0, 13, 16)
4084 22:58:29.968398 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4085 22:58:29.974981 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4086 22:58:29.975064
4087 22:58:29.978236 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4088 22:58:29.981291 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4089 22:58:29.984918 [Gating] SW calibration Done
4090 22:58:29.985004 ==
4091 22:58:29.987859 Dram Type= 6, Freq= 0, CH_0, rank 0
4092 22:58:29.991189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4093 22:58:29.991340 ==
4094 22:58:29.994629 RX Vref Scan: 0
4095 22:58:29.994714
4096 22:58:29.994779 RX Vref 0 -> 0, step: 1
4097 22:58:29.994840
4098 22:58:29.998088 RX Delay -230 -> 252, step: 16
4099 22:58:30.000926 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4100 22:58:30.007803 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4101 22:58:30.011233 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4102 22:58:30.014305 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4103 22:58:30.017713 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4104 22:58:30.024224 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4105 22:58:30.027716 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4106 22:58:30.030703 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4107 22:58:30.034149 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4108 22:58:30.040490 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4109 22:58:30.043879 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4110 22:58:30.047341 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4111 22:58:30.050732 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4112 22:58:30.057231 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4113 22:58:30.060508 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4114 22:58:30.063948 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4115 22:58:30.064031 ==
4116 22:58:30.066966 Dram Type= 6, Freq= 0, CH_0, rank 0
4117 22:58:30.070314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4118 22:58:30.070398 ==
4119 22:58:30.073992 DQS Delay:
4120 22:58:30.074117 DQS0 = 0, DQS1 = 0
4121 22:58:30.077037 DQM Delay:
4122 22:58:30.077113 DQM0 = 51, DQM1 = 41
4123 22:58:30.077174 DQ Delay:
4124 22:58:30.080553 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4125 22:58:30.084098 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4126 22:58:30.087192 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4127 22:58:30.090345 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =49
4128 22:58:30.090455
4129 22:58:30.090551
4130 22:58:30.093867 ==
4131 22:58:30.097319 Dram Type= 6, Freq= 0, CH_0, rank 0
4132 22:58:30.100223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4133 22:58:30.100308 ==
4134 22:58:30.100375
4135 22:58:30.100436
4136 22:58:30.103591 TX Vref Scan disable
4137 22:58:30.103676 == TX Byte 0 ==
4138 22:58:30.110255 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4139 22:58:30.113670 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4140 22:58:30.113747 == TX Byte 1 ==
4141 22:58:30.120051 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4142 22:58:30.123556 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4143 22:58:30.123654 ==
4144 22:58:30.126525 Dram Type= 6, Freq= 0, CH_0, rank 0
4145 22:58:30.129943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4146 22:58:30.130027 ==
4147 22:58:30.130093
4148 22:58:30.130153
4149 22:58:30.133135 TX Vref Scan disable
4150 22:58:30.136638 == TX Byte 0 ==
4151 22:58:30.139607 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4152 22:58:30.142942 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4153 22:58:30.146706 == TX Byte 1 ==
4154 22:58:30.149711 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4155 22:58:30.153118 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4156 22:58:30.156460
4157 22:58:30.156543 [DATLAT]
4158 22:58:30.156609 Freq=600, CH0 RK0
4159 22:58:30.156670
4160 22:58:30.159674 DATLAT Default: 0x9
4161 22:58:30.159757 0, 0xFFFF, sum = 0
4162 22:58:30.163080 1, 0xFFFF, sum = 0
4163 22:58:30.163168 2, 0xFFFF, sum = 0
4164 22:58:30.166340 3, 0xFFFF, sum = 0
4165 22:58:30.166425 4, 0xFFFF, sum = 0
4166 22:58:30.169712 5, 0xFFFF, sum = 0
4167 22:58:30.173176 6, 0xFFFF, sum = 0
4168 22:58:30.173261 7, 0xFFFF, sum = 0
4169 22:58:30.173328 8, 0x0, sum = 1
4170 22:58:30.176530 9, 0x0, sum = 2
4171 22:58:30.176614 10, 0x0, sum = 3
4172 22:58:30.179392 11, 0x0, sum = 4
4173 22:58:30.179489 best_step = 9
4174 22:58:30.179553
4175 22:58:30.179612 ==
4176 22:58:30.182846 Dram Type= 6, Freq= 0, CH_0, rank 0
4177 22:58:30.189324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4178 22:58:30.189427 ==
4179 22:58:30.189524 RX Vref Scan: 1
4180 22:58:30.189619
4181 22:58:30.192436 RX Vref 0 -> 0, step: 1
4182 22:58:30.192517
4183 22:58:30.195824 RX Delay -163 -> 252, step: 8
4184 22:58:30.195906
4185 22:58:30.199127 Set Vref, RX VrefLevel [Byte0]: 59
4186 22:58:30.202526 [Byte1]: 50
4187 22:58:30.202612
4188 22:58:30.205951 Final RX Vref Byte 0 = 59 to rank0
4189 22:58:30.208905 Final RX Vref Byte 1 = 50 to rank0
4190 22:58:30.212222 Final RX Vref Byte 0 = 59 to rank1
4191 22:58:30.215858 Final RX Vref Byte 1 = 50 to rank1==
4192 22:58:30.218876 Dram Type= 6, Freq= 0, CH_0, rank 0
4193 22:58:30.222216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4194 22:58:30.222333 ==
4195 22:58:30.225668 DQS Delay:
4196 22:58:30.225751 DQS0 = 0, DQS1 = 0
4197 22:58:30.228996 DQM Delay:
4198 22:58:30.229090 DQM0 = 50, DQM1 = 37
4199 22:58:30.229159 DQ Delay:
4200 22:58:30.232101 DQ0 =48, DQ1 =52, DQ2 =48, DQ3 =44
4201 22:58:30.235387 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4202 22:58:30.238748 DQ8 =32, DQ9 =24, DQ10 =36, DQ11 =32
4203 22:58:30.242084 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4204 22:58:30.242220
4205 22:58:30.242321
4206 22:58:30.251855 [DQSOSCAuto] RK0, (LSB)MR18= 0x5751, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
4207 22:58:30.255333 CH0 RK0: MR19=808, MR18=5751
4208 22:58:30.262123 CH0_RK0: MR19=0x808, MR18=0x5751, DQSOSC=393, MR23=63, INC=169, DEC=113
4209 22:58:30.262254
4210 22:58:30.265252 ----->DramcWriteLeveling(PI) begin...
4211 22:58:30.265376 ==
4212 22:58:30.268756 Dram Type= 6, Freq= 0, CH_0, rank 1
4213 22:58:30.272227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4214 22:58:30.272380 ==
4215 22:58:30.275598 Write leveling (Byte 0): 36 => 36
4216 22:58:30.278548 Write leveling (Byte 1): 32 => 32
4217 22:58:30.281921 DramcWriteLeveling(PI) end<-----
4218 22:58:30.282122
4219 22:58:30.282281 ==
4220 22:58:30.285202 Dram Type= 6, Freq= 0, CH_0, rank 1
4221 22:58:30.288668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4222 22:58:30.288963 ==
4223 22:58:30.292124 [Gating] SW mode calibration
4224 22:58:30.298444 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4225 22:58:30.304661 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4226 22:58:30.308218 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4227 22:58:30.311571 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4228 22:58:30.318235 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4229 22:58:30.321638 0 9 12 | B1->B0 | 3232 2f2f | 1 1 | (1 1) (1 0)
4230 22:58:30.324529 0 9 16 | B1->B0 | 2525 2525 | 1 0 | (1 0) (0 0)
4231 22:58:30.331412 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4232 22:58:30.334857 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4233 22:58:30.337739 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 22:58:30.344441 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 22:58:30.347843 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 22:58:30.351179 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4237 22:58:30.357959 0 10 12 | B1->B0 | 3131 3535 | 1 0 | (0 0) (0 0)
4238 22:58:30.360885 0 10 16 | B1->B0 | 4545 4545 | 0 0 | (0 0) (0 0)
4239 22:58:30.364657 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 22:58:30.371168 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 22:58:30.374094 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 22:58:30.377535 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 22:58:30.384230 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 22:58:30.387668 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 22:58:30.391087 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4246 22:58:30.397336 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 22:58:30.400867 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 22:58:30.403936 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 22:58:30.410563 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 22:58:30.413810 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 22:58:30.417272 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 22:58:30.423830 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 22:58:30.426873 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 22:58:30.430193 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 22:58:30.437020 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 22:58:30.440342 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 22:58:30.443579 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 22:58:30.450537 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 22:58:30.453455 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 22:58:30.457081 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 22:58:30.463350 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4262 22:58:30.466693 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4263 22:58:30.470061 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4264 22:58:30.473320 Total UI for P1: 0, mck2ui 16
4265 22:58:30.476677 best dqsien dly found for B0: ( 0, 13, 14)
4266 22:58:30.480121 Total UI for P1: 0, mck2ui 16
4267 22:58:30.483495 best dqsien dly found for B1: ( 0, 13, 16)
4268 22:58:30.486490 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4269 22:58:30.489850 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4270 22:58:30.489932
4271 22:58:30.496577 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4272 22:58:30.499599 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4273 22:58:30.503052 [Gating] SW calibration Done
4274 22:58:30.503134 ==
4275 22:58:30.506380 Dram Type= 6, Freq= 0, CH_0, rank 1
4276 22:58:30.509843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4277 22:58:30.509925 ==
4278 22:58:30.509990 RX Vref Scan: 0
4279 22:58:30.510050
4280 22:58:30.512870 RX Vref 0 -> 0, step: 1
4281 22:58:30.513019
4282 22:58:30.516280 RX Delay -230 -> 252, step: 16
4283 22:58:30.519466 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4284 22:58:30.522675 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4285 22:58:30.529315 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4286 22:58:30.532746 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4287 22:58:30.535994 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4288 22:58:30.539479 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4289 22:58:30.546178 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4290 22:58:30.549340 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4291 22:58:30.552687 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4292 22:58:30.556057 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4293 22:58:30.562628 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4294 22:58:30.566069 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4295 22:58:30.569097 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4296 22:58:30.572613 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4297 22:58:30.579047 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4298 22:58:30.582518 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4299 22:58:30.582620 ==
4300 22:58:30.585480 Dram Type= 6, Freq= 0, CH_0, rank 1
4301 22:58:30.588725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4302 22:58:30.588854 ==
4303 22:58:30.592126 DQS Delay:
4304 22:58:30.592208 DQS0 = 0, DQS1 = 0
4305 22:58:30.592273 DQM Delay:
4306 22:58:30.595599 DQM0 = 50, DQM1 = 42
4307 22:58:30.595707 DQ Delay:
4308 22:58:30.599120 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =41
4309 22:58:30.602050 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4310 22:58:30.605590 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4311 22:58:30.608635 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4312 22:58:30.608744
4313 22:58:30.608857
4314 22:58:30.608919 ==
4315 22:58:30.612014 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 22:58:30.618646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 22:58:30.618737 ==
4318 22:58:30.618803
4319 22:58:30.618863
4320 22:58:30.618921 TX Vref Scan disable
4321 22:58:30.622380 == TX Byte 0 ==
4322 22:58:30.625754 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4323 22:58:30.632148 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4324 22:58:30.632256 == TX Byte 1 ==
4325 22:58:30.635566 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4326 22:58:30.642095 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4327 22:58:30.642203 ==
4328 22:58:30.645530 Dram Type= 6, Freq= 0, CH_0, rank 1
4329 22:58:30.649026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4330 22:58:30.649134 ==
4331 22:58:30.649227
4332 22:58:30.649315
4333 22:58:30.651995 TX Vref Scan disable
4334 22:58:30.655254 == TX Byte 0 ==
4335 22:58:30.658757 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4336 22:58:30.662107 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4337 22:58:30.665073 == TX Byte 1 ==
4338 22:58:30.668433 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4339 22:58:30.671895 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4340 22:58:30.671977
4341 22:58:30.675050 [DATLAT]
4342 22:58:30.675131 Freq=600, CH0 RK1
4343 22:58:30.675196
4344 22:58:30.678282 DATLAT Default: 0x9
4345 22:58:30.678363 0, 0xFFFF, sum = 0
4346 22:58:30.681989 1, 0xFFFF, sum = 0
4347 22:58:30.682073 2, 0xFFFF, sum = 0
4348 22:58:30.685308 3, 0xFFFF, sum = 0
4349 22:58:30.685392 4, 0xFFFF, sum = 0
4350 22:58:30.688651 5, 0xFFFF, sum = 0
4351 22:58:30.688768 6, 0xFFFF, sum = 0
4352 22:58:30.692073 7, 0xFFFF, sum = 0
4353 22:58:30.692156 8, 0x0, sum = 1
4354 22:58:30.695219 9, 0x0, sum = 2
4355 22:58:30.695301 10, 0x0, sum = 3
4356 22:58:30.698520 11, 0x0, sum = 4
4357 22:58:30.698633 best_step = 9
4358 22:58:30.698729
4359 22:58:30.698820 ==
4360 22:58:30.701583 Dram Type= 6, Freq= 0, CH_0, rank 1
4361 22:58:30.705082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4362 22:58:30.705162 ==
4363 22:58:30.708582 RX Vref Scan: 0
4364 22:58:30.708715
4365 22:58:30.711425 RX Vref 0 -> 0, step: 1
4366 22:58:30.711536
4367 22:58:30.711623 RX Delay -179 -> 252, step: 8
4368 22:58:30.719499 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4369 22:58:30.722751 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4370 22:58:30.726174 iDelay=205, Bit 2, Center 48 (-99 ~ 196) 296
4371 22:58:30.729543 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4372 22:58:30.732651 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4373 22:58:30.739512 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4374 22:58:30.742527 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4375 22:58:30.746185 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4376 22:58:30.749203 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4377 22:58:30.755928 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4378 22:58:30.759176 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4379 22:58:30.762569 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4380 22:58:30.765973 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4381 22:58:30.772126 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280
4382 22:58:30.775557 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4383 22:58:30.779028 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4384 22:58:30.779109 ==
4385 22:58:30.782448 Dram Type= 6, Freq= 0, CH_0, rank 1
4386 22:58:30.785584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4387 22:58:30.785667 ==
4388 22:58:30.788762 DQS Delay:
4389 22:58:30.788858 DQS0 = 0, DQS1 = 0
4390 22:58:30.791965 DQM Delay:
4391 22:58:30.792046 DQM0 = 49, DQM1 = 42
4392 22:58:30.792110 DQ Delay:
4393 22:58:30.795477 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =44
4394 22:58:30.798949 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =56
4395 22:58:30.801923 DQ8 =36, DQ9 =28, DQ10 =40, DQ11 =32
4396 22:58:30.805431 DQ12 =48, DQ13 =48, DQ14 =52, DQ15 =52
4397 22:58:30.805513
4398 22:58:30.805577
4399 22:58:30.815618 [DQSOSCAuto] RK1, (LSB)MR18= 0x612f, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
4400 22:58:30.818476 CH0 RK1: MR19=808, MR18=612F
4401 22:58:30.825498 CH0_RK1: MR19=0x808, MR18=0x612F, DQSOSC=391, MR23=63, INC=171, DEC=114
4402 22:58:30.825581 [RxdqsGatingPostProcess] freq 600
4403 22:58:30.832081 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4404 22:58:30.835181 Pre-setting of DQS Precalculation
4405 22:58:30.838517 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4406 22:58:30.841909 ==
4407 22:58:30.845001 Dram Type= 6, Freq= 0, CH_1, rank 0
4408 22:58:30.848518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4409 22:58:30.848603 ==
4410 22:58:30.851801 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4411 22:58:30.858010 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4412 22:58:30.862255 [CA 0] Center 35 (5~66) winsize 62
4413 22:58:30.865488 [CA 1] Center 35 (5~66) winsize 62
4414 22:58:30.868926 [CA 2] Center 34 (4~65) winsize 62
4415 22:58:30.872184 [CA 3] Center 34 (3~65) winsize 63
4416 22:58:30.875516 [CA 4] Center 34 (4~65) winsize 62
4417 22:58:30.878611 [CA 5] Center 33 (3~64) winsize 62
4418 22:58:30.878695
4419 22:58:30.882067 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4420 22:58:30.882189
4421 22:58:30.885456 [CATrainingPosCal] consider 1 rank data
4422 22:58:30.888661 u2DelayCellTimex100 = 270/100 ps
4423 22:58:30.892006 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4424 22:58:30.898604 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4425 22:58:30.902086 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4426 22:58:30.905222 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4427 22:58:30.908619 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4428 22:58:30.911608 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4429 22:58:30.911690
4430 22:58:30.915034 CA PerBit enable=1, Macro0, CA PI delay=33
4431 22:58:30.915116
4432 22:58:30.918470 [CBTSetCACLKResult] CA Dly = 33
4433 22:58:30.921460 CS Dly: 5 (0~36)
4434 22:58:30.921542 ==
4435 22:58:30.924972 Dram Type= 6, Freq= 0, CH_1, rank 1
4436 22:58:30.928605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4437 22:58:30.928687 ==
4438 22:58:30.935090 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4439 22:58:30.938056 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4440 22:58:30.942290 [CA 0] Center 36 (6~66) winsize 61
4441 22:58:30.945612 [CA 1] Center 35 (5~66) winsize 62
4442 22:58:30.948572 [CA 2] Center 34 (4~65) winsize 62
4443 22:58:30.952323 [CA 3] Center 34 (4~65) winsize 62
4444 22:58:30.955302 [CA 4] Center 34 (4~65) winsize 62
4445 22:58:30.958525 [CA 5] Center 34 (4~65) winsize 62
4446 22:58:30.958610
4447 22:58:30.962026 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4448 22:58:30.962148
4449 22:58:30.965415 [CATrainingPosCal] consider 2 rank data
4450 22:58:30.968589 u2DelayCellTimex100 = 270/100 ps
4451 22:58:30.972006 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4452 22:58:30.978482 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4453 22:58:30.981885 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4454 22:58:30.985244 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4455 22:58:30.988620 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4456 22:58:30.991537 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4457 22:58:30.991648
4458 22:58:30.994763 CA PerBit enable=1, Macro0, CA PI delay=34
4459 22:58:30.994859
4460 22:58:30.998073 [CBTSetCACLKResult] CA Dly = 34
4461 22:58:31.001193 CS Dly: 5 (0~37)
4462 22:58:31.001267
4463 22:58:31.004735 ----->DramcWriteLeveling(PI) begin...
4464 22:58:31.004855 ==
4465 22:58:31.008148 Dram Type= 6, Freq= 0, CH_1, rank 0
4466 22:58:31.011648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4467 22:58:31.011735 ==
4468 22:58:31.014574 Write leveling (Byte 0): 29 => 29
4469 22:58:31.018031 Write leveling (Byte 1): 29 => 29
4470 22:58:31.021355 DramcWriteLeveling(PI) end<-----
4471 22:58:31.021439
4472 22:58:31.021505 ==
4473 22:58:31.024760 Dram Type= 6, Freq= 0, CH_1, rank 0
4474 22:58:31.027811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4475 22:58:31.027893 ==
4476 22:58:31.031022 [Gating] SW mode calibration
4477 22:58:31.037717 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4478 22:58:31.044534 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4479 22:58:31.047781 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4480 22:58:31.051310 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4481 22:58:31.057596 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4482 22:58:31.060901 0 9 12 | B1->B0 | 2e2e 2c2c | 1 0 | (1 1) (1 1)
4483 22:58:31.064183 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4484 22:58:31.071121 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4485 22:58:31.074342 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4486 22:58:31.077294 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4487 22:58:31.084057 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4488 22:58:31.087444 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4489 22:58:31.090876 0 10 8 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
4490 22:58:31.097518 0 10 12 | B1->B0 | 3939 3b3b | 0 0 | (0 0) (0 0)
4491 22:58:31.100610 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4492 22:58:31.103999 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 22:58:31.110325 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 22:58:31.113748 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 22:58:31.117229 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 22:58:31.123521 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4497 22:58:31.126944 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4498 22:58:31.130404 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4499 22:58:31.137170 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 22:58:31.140387 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 22:58:31.143770 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 22:58:31.150517 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 22:58:31.153702 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 22:58:31.157144 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 22:58:31.163508 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 22:58:31.166744 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 22:58:31.170574 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 22:58:31.176878 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 22:58:31.179981 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 22:58:31.183331 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 22:58:31.190240 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 22:58:31.193071 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 22:58:31.196568 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 22:58:31.203012 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4515 22:58:31.203110 Total UI for P1: 0, mck2ui 16
4516 22:58:31.210026 best dqsien dly found for B0: ( 0, 13, 10)
4517 22:58:31.213309 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4518 22:58:31.216324 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4519 22:58:31.219792 Total UI for P1: 0, mck2ui 16
4520 22:58:31.223167 best dqsien dly found for B1: ( 0, 13, 14)
4521 22:58:31.226133 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4522 22:58:31.229512 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4523 22:58:31.229628
4524 22:58:31.236210 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4525 22:58:31.239726 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4526 22:58:31.239835 [Gating] SW calibration Done
4527 22:58:31.242927 ==
4528 22:58:31.246156 Dram Type= 6, Freq= 0, CH_1, rank 0
4529 22:58:31.249539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4530 22:58:31.249622 ==
4531 22:58:31.249687 RX Vref Scan: 0
4532 22:58:31.249749
4533 22:58:31.253006 RX Vref 0 -> 0, step: 1
4534 22:58:31.253088
4535 22:58:31.256253 RX Delay -230 -> 252, step: 16
4536 22:58:31.259504 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4537 22:58:31.262449 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4538 22:58:31.269301 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4539 22:58:31.272417 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4540 22:58:31.275799 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4541 22:58:31.279180 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4542 22:58:31.285549 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4543 22:58:31.289060 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4544 22:58:31.292534 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4545 22:58:31.295382 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4546 22:58:31.302223 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4547 22:58:31.305593 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4548 22:58:31.308820 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4549 22:58:31.311987 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4550 22:58:31.315420 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4551 22:58:31.321847 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4552 22:58:31.321931 ==
4553 22:58:31.325257 Dram Type= 6, Freq= 0, CH_1, rank 0
4554 22:58:31.328617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4555 22:58:31.328703 ==
4556 22:58:31.328791 DQS Delay:
4557 22:58:31.332099 DQS0 = 0, DQS1 = 0
4558 22:58:31.332181 DQM Delay:
4559 22:58:31.335533 DQM0 = 50, DQM1 = 40
4560 22:58:31.335615 DQ Delay:
4561 22:58:31.338524 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4562 22:58:31.342001 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4563 22:58:31.345331 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4564 22:58:31.348444 DQ12 =57, DQ13 =41, DQ14 =41, DQ15 =41
4565 22:58:31.348532
4566 22:58:31.348634
4567 22:58:31.348740 ==
4568 22:58:31.351876 Dram Type= 6, Freq= 0, CH_1, rank 0
4569 22:58:31.358164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 22:58:31.358261 ==
4571 22:58:31.358346
4572 22:58:31.358445
4573 22:58:31.358523 TX Vref Scan disable
4574 22:58:31.361648 == TX Byte 0 ==
4575 22:58:31.365011 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4576 22:58:31.371486 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4577 22:58:31.371599 == TX Byte 1 ==
4578 22:58:31.374786 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4579 22:58:31.381296 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4580 22:58:31.381404 ==
4581 22:58:31.384791 Dram Type= 6, Freq= 0, CH_1, rank 0
4582 22:58:31.388198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4583 22:58:31.388312 ==
4584 22:58:31.388430
4585 22:58:31.388522
4586 22:58:31.390995 TX Vref Scan disable
4587 22:58:31.394650 == TX Byte 0 ==
4588 22:58:31.397951 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4589 22:58:31.401150 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4590 22:58:31.404534 == TX Byte 1 ==
4591 22:58:31.407868 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4592 22:58:31.411116 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4593 22:58:31.411201
4594 22:58:31.411267 [DATLAT]
4595 22:58:31.414491 Freq=600, CH1 RK0
4596 22:58:31.414577
4597 22:58:31.417862 DATLAT Default: 0x9
4598 22:58:31.417946 0, 0xFFFF, sum = 0
4599 22:58:31.421227 1, 0xFFFF, sum = 0
4600 22:58:31.421312 2, 0xFFFF, sum = 0
4601 22:58:31.424593 3, 0xFFFF, sum = 0
4602 22:58:31.424678 4, 0xFFFF, sum = 0
4603 22:58:31.427580 5, 0xFFFF, sum = 0
4604 22:58:31.427665 6, 0xFFFF, sum = 0
4605 22:58:31.431076 7, 0xFFFF, sum = 0
4606 22:58:31.431161 8, 0x0, sum = 1
4607 22:58:31.434413 9, 0x0, sum = 2
4608 22:58:31.434498 10, 0x0, sum = 3
4609 22:58:31.437242 11, 0x0, sum = 4
4610 22:58:31.437327 best_step = 9
4611 22:58:31.437393
4612 22:58:31.437454 ==
4613 22:58:31.440719 Dram Type= 6, Freq= 0, CH_1, rank 0
4614 22:58:31.444172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4615 22:58:31.444257 ==
4616 22:58:31.447620 RX Vref Scan: 1
4617 22:58:31.447703
4618 22:58:31.450832 RX Vref 0 -> 0, step: 1
4619 22:58:31.450916
4620 22:58:31.450982 RX Delay -179 -> 252, step: 8
4621 22:58:31.451043
4622 22:58:31.454050 Set Vref, RX VrefLevel [Byte0]: 53
4623 22:58:31.457436 [Byte1]: 52
4624 22:58:31.461780
4625 22:58:31.461863 Final RX Vref Byte 0 = 53 to rank0
4626 22:58:31.465506 Final RX Vref Byte 1 = 52 to rank0
4627 22:58:31.468896 Final RX Vref Byte 0 = 53 to rank1
4628 22:58:31.471743 Final RX Vref Byte 1 = 52 to rank1==
4629 22:58:31.475545 Dram Type= 6, Freq= 0, CH_1, rank 0
4630 22:58:31.482168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4631 22:58:31.482252 ==
4632 22:58:31.482317 DQS Delay:
4633 22:58:31.482377 DQS0 = 0, DQS1 = 0
4634 22:58:31.485344 DQM Delay:
4635 22:58:31.485429 DQM0 = 48, DQM1 = 40
4636 22:58:31.488686 DQ Delay:
4637 22:58:31.491602 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4638 22:58:31.495002 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =44
4639 22:58:31.498233 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4640 22:58:31.501603 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =44
4641 22:58:31.501703
4642 22:58:31.501770
4643 22:58:31.508200 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b72, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4644 22:58:31.511510 CH1 RK0: MR19=808, MR18=4B72
4645 22:58:31.518156 CH1_RK0: MR19=0x808, MR18=0x4B72, DQSOSC=388, MR23=63, INC=174, DEC=116
4646 22:58:31.518239
4647 22:58:31.521498 ----->DramcWriteLeveling(PI) begin...
4648 22:58:31.521585 ==
4649 22:58:31.524945 Dram Type= 6, Freq= 0, CH_1, rank 1
4650 22:58:31.528279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4651 22:58:31.528388 ==
4652 22:58:31.531224 Write leveling (Byte 0): 29 => 29
4653 22:58:31.534627 Write leveling (Byte 1): 29 => 29
4654 22:58:31.537921 DramcWriteLeveling(PI) end<-----
4655 22:58:31.538005
4656 22:58:31.538071 ==
4657 22:58:31.541334 Dram Type= 6, Freq= 0, CH_1, rank 1
4658 22:58:31.544757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4659 22:58:31.548325 ==
4660 22:58:31.548434 [Gating] SW mode calibration
4661 22:58:31.554559 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4662 22:58:31.561122 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4663 22:58:31.564520 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4664 22:58:31.571156 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4665 22:58:31.574543 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
4666 22:58:31.577531 0 9 12 | B1->B0 | 2828 3030 | 0 0 | (1 1) (0 1)
4667 22:58:31.584265 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4668 22:58:31.587918 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4669 22:58:31.590797 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4670 22:58:31.597736 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4671 22:58:31.600950 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4672 22:58:31.604383 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4673 22:58:31.611047 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4674 22:58:31.614281 0 10 12 | B1->B0 | 3b3b 2a2a | 0 0 | (0 0) (0 0)
4675 22:58:31.617401 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4676 22:58:31.623958 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4677 22:58:31.627358 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4678 22:58:31.630778 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4679 22:58:31.637595 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4680 22:58:31.640446 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 22:58:31.643855 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4682 22:58:31.650590 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4683 22:58:31.653631 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 22:58:31.657026 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 22:58:31.663536 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 22:58:31.667002 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 22:58:31.670387 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 22:58:31.676749 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 22:58:31.680150 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 22:58:31.683546 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 22:58:31.690289 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 22:58:31.693502 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 22:58:31.696965 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 22:58:31.703172 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 22:58:31.706387 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 22:58:31.709821 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 22:58:31.716606 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 22:58:31.719974 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4699 22:58:31.723058 Total UI for P1: 0, mck2ui 16
4700 22:58:31.726422 best dqsien dly found for B0: ( 0, 13, 10)
4701 22:58:31.729693 Total UI for P1: 0, mck2ui 16
4702 22:58:31.733180 best dqsien dly found for B1: ( 0, 13, 10)
4703 22:58:31.736532 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4704 22:58:31.739525 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4705 22:58:31.739608
4706 22:58:31.743316 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4707 22:58:31.746177 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4708 22:58:31.749573 [Gating] SW calibration Done
4709 22:58:31.749656 ==
4710 22:58:31.753112 Dram Type= 6, Freq= 0, CH_1, rank 1
4711 22:58:31.756054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4712 22:58:31.759486 ==
4713 22:58:31.759569 RX Vref Scan: 0
4714 22:58:31.759635
4715 22:58:31.763025 RX Vref 0 -> 0, step: 1
4716 22:58:31.763107
4717 22:58:31.766215 RX Delay -230 -> 252, step: 16
4718 22:58:31.769528 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4719 22:58:31.772860 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4720 22:58:31.776267 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4721 22:58:31.779314 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4722 22:58:31.786192 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4723 22:58:31.789113 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4724 22:58:31.792603 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4725 22:58:31.795875 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4726 22:58:31.802592 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4727 22:58:31.805980 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4728 22:58:31.808988 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4729 22:58:31.812236 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4730 22:58:31.819093 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4731 22:58:31.822093 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4732 22:58:31.825502 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4733 22:58:31.829047 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4734 22:58:31.829129 ==
4735 22:58:31.832083 Dram Type= 6, Freq= 0, CH_1, rank 1
4736 22:58:31.838650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4737 22:58:31.838771 ==
4738 22:58:31.838867 DQS Delay:
4739 22:58:31.842186 DQS0 = 0, DQS1 = 0
4740 22:58:31.842285 DQM Delay:
4741 22:58:31.845235 DQM0 = 49, DQM1 = 46
4742 22:58:31.845317 DQ Delay:
4743 22:58:31.849044 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4744 22:58:31.852035 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4745 22:58:31.855503 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4746 22:58:31.858467 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4747 22:58:31.858549
4748 22:58:31.858613
4749 22:58:31.858671 ==
4750 22:58:31.861771 Dram Type= 6, Freq= 0, CH_1, rank 1
4751 22:58:31.865579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4752 22:58:31.865675 ==
4753 22:58:31.865739
4754 22:58:31.865799
4755 22:58:31.868674 TX Vref Scan disable
4756 22:58:31.872073 == TX Byte 0 ==
4757 22:58:31.875639 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4758 22:58:31.878647 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4759 22:58:31.881930 == TX Byte 1 ==
4760 22:58:31.885239 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4761 22:58:31.888588 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4762 22:58:31.888671 ==
4763 22:58:31.891905 Dram Type= 6, Freq= 0, CH_1, rank 1
4764 22:58:31.895304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4765 22:58:31.898325 ==
4766 22:58:31.898406
4767 22:58:31.898471
4768 22:58:31.898530 TX Vref Scan disable
4769 22:58:31.902336 == TX Byte 0 ==
4770 22:58:31.905851 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4771 22:58:31.909140 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4772 22:58:31.911995 == TX Byte 1 ==
4773 22:58:31.915679 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4774 22:58:31.918992 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4775 22:58:31.922430
4776 22:58:31.922511 [DATLAT]
4777 22:58:31.922575 Freq=600, CH1 RK1
4778 22:58:31.922636
4779 22:58:31.925922 DATLAT Default: 0x9
4780 22:58:31.926038 0, 0xFFFF, sum = 0
4781 22:58:31.928932 1, 0xFFFF, sum = 0
4782 22:58:31.929015 2, 0xFFFF, sum = 0
4783 22:58:31.932259 3, 0xFFFF, sum = 0
4784 22:58:31.935529 4, 0xFFFF, sum = 0
4785 22:58:31.935612 5, 0xFFFF, sum = 0
4786 22:58:31.938581 6, 0xFFFF, sum = 0
4787 22:58:31.938665 7, 0xFFFF, sum = 0
4788 22:58:31.942068 8, 0x0, sum = 1
4789 22:58:31.942151 9, 0x0, sum = 2
4790 22:58:31.942218 10, 0x0, sum = 3
4791 22:58:31.945593 11, 0x0, sum = 4
4792 22:58:31.945677 best_step = 9
4793 22:58:31.945740
4794 22:58:31.945799 ==
4795 22:58:31.949103 Dram Type= 6, Freq= 0, CH_1, rank 1
4796 22:58:31.955382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4797 22:58:31.955463 ==
4798 22:58:31.955529 RX Vref Scan: 0
4799 22:58:31.955589
4800 22:58:31.958761 RX Vref 0 -> 0, step: 1
4801 22:58:31.958843
4802 22:58:31.962164 RX Delay -163 -> 252, step: 8
4803 22:58:31.965150 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4804 22:58:31.971889 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4805 22:58:31.975032 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4806 22:58:31.978690 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4807 22:58:31.981570 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4808 22:58:31.984959 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4809 22:58:31.991416 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4810 22:58:31.994606 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4811 22:58:31.998072 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4812 22:58:32.001659 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4813 22:58:32.007929 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4814 22:58:32.011353 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4815 22:58:32.014281 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4816 22:58:32.017965 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4817 22:58:32.021222 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4818 22:58:32.027748 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4819 22:58:32.027850 ==
4820 22:58:32.031194 Dram Type= 6, Freq= 0, CH_1, rank 1
4821 22:58:32.034646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4822 22:58:32.034728 ==
4823 22:58:32.034793 DQS Delay:
4824 22:58:32.037667 DQS0 = 0, DQS1 = 0
4825 22:58:32.037765 DQM Delay:
4826 22:58:32.040882 DQM0 = 49, DQM1 = 43
4827 22:58:32.040964 DQ Delay:
4828 22:58:32.044570 DQ0 =56, DQ1 =40, DQ2 =40, DQ3 =48
4829 22:58:32.047913 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =44
4830 22:58:32.051132 DQ8 =32, DQ9 =32, DQ10 =44, DQ11 =40
4831 22:58:32.054163 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =56
4832 22:58:32.054246
4833 22:58:32.054310
4834 22:58:32.064117 [DQSOSCAuto] RK1, (LSB)MR18= 0x5b20, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
4835 22:58:32.064202 CH1 RK1: MR19=808, MR18=5B20
4836 22:58:32.070694 CH1_RK1: MR19=0x808, MR18=0x5B20, DQSOSC=392, MR23=63, INC=170, DEC=113
4837 22:58:32.074106 [RxdqsGatingPostProcess] freq 600
4838 22:58:32.080657 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4839 22:58:32.084110 Pre-setting of DQS Precalculation
4840 22:58:32.087019 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4841 22:58:32.093986 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4842 22:58:32.103841 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4843 22:58:32.103923
4844 22:58:32.103988
4845 22:58:32.106949 [Calibration Summary] 1200 Mbps
4846 22:58:32.107109 CH 0, Rank 0
4847 22:58:32.110180 SW Impedance : PASS
4848 22:58:32.110263 DUTY Scan : NO K
4849 22:58:32.113640 ZQ Calibration : PASS
4850 22:58:32.117154 Jitter Meter : NO K
4851 22:58:32.117237 CBT Training : PASS
4852 22:58:32.120147 Write leveling : PASS
4853 22:58:32.120228 RX DQS gating : PASS
4854 22:58:32.123376 RX DQ/DQS(RDDQC) : PASS
4855 22:58:32.126723 TX DQ/DQS : PASS
4856 22:58:32.126806 RX DATLAT : PASS
4857 22:58:32.130034 RX DQ/DQS(Engine): PASS
4858 22:58:32.133580 TX OE : NO K
4859 22:58:32.133663 All Pass.
4860 22:58:32.133728
4861 22:58:32.133788 CH 0, Rank 1
4862 22:58:32.136680 SW Impedance : PASS
4863 22:58:32.140089 DUTY Scan : NO K
4864 22:58:32.140198 ZQ Calibration : PASS
4865 22:58:32.143049 Jitter Meter : NO K
4866 22:58:32.146361 CBT Training : PASS
4867 22:58:32.146443 Write leveling : PASS
4868 22:58:32.149855 RX DQS gating : PASS
4869 22:58:32.153107 RX DQ/DQS(RDDQC) : PASS
4870 22:58:32.153205 TX DQ/DQS : PASS
4871 22:58:32.156408 RX DATLAT : PASS
4872 22:58:32.159559 RX DQ/DQS(Engine): PASS
4873 22:58:32.159642 TX OE : NO K
4874 22:58:32.162811 All Pass.
4875 22:58:32.162893
4876 22:58:32.162957 CH 1, Rank 0
4877 22:58:32.166569 SW Impedance : PASS
4878 22:58:32.166677 DUTY Scan : NO K
4879 22:58:32.169649 ZQ Calibration : PASS
4880 22:58:32.173141 Jitter Meter : NO K
4881 22:58:32.173276 CBT Training : PASS
4882 22:58:32.176080 Write leveling : PASS
4883 22:58:32.179535 RX DQS gating : PASS
4884 22:58:32.179646 RX DQ/DQS(RDDQC) : PASS
4885 22:58:32.182663 TX DQ/DQS : PASS
4886 22:58:32.186065 RX DATLAT : PASS
4887 22:58:32.186150 RX DQ/DQS(Engine): PASS
4888 22:58:32.189432 TX OE : NO K
4889 22:58:32.189524 All Pass.
4890 22:58:32.189591
4891 22:58:32.192878 CH 1, Rank 1
4892 22:58:32.192960 SW Impedance : PASS
4893 22:58:32.196002 DUTY Scan : NO K
4894 22:58:32.199014 ZQ Calibration : PASS
4895 22:58:32.199096 Jitter Meter : NO K
4896 22:58:32.202499 CBT Training : PASS
4897 22:58:32.205557 Write leveling : PASS
4898 22:58:32.205639 RX DQS gating : PASS
4899 22:58:32.208943 RX DQ/DQS(RDDQC) : PASS
4900 22:58:32.209024 TX DQ/DQS : PASS
4901 22:58:32.212346 RX DATLAT : PASS
4902 22:58:32.215623 RX DQ/DQS(Engine): PASS
4903 22:58:32.215711 TX OE : NO K
4904 22:58:32.219021 All Pass.
4905 22:58:32.219103
4906 22:58:32.219168 DramC Write-DBI off
4907 22:58:32.222024 PER_BANK_REFRESH: Hybrid Mode
4908 22:58:32.225384 TX_TRACKING: ON
4909 22:58:32.232504 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4910 22:58:32.235524 [FAST_K] Save calibration result to emmc
4911 22:58:32.238958 dramc_set_vcore_voltage set vcore to 662500
4912 22:58:32.242420 Read voltage for 933, 3
4913 22:58:32.242502 Vio18 = 0
4914 22:58:32.245490 Vcore = 662500
4915 22:58:32.245573 Vdram = 0
4916 22:58:32.245637 Vddq = 0
4917 22:58:32.248854 Vmddr = 0
4918 22:58:32.252146 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4919 22:58:32.258801 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4920 22:58:32.258913 MEM_TYPE=3, freq_sel=17
4921 22:58:32.262170 sv_algorithm_assistance_LP4_1600
4922 22:58:32.269031 ============ PULL DRAM RESETB DOWN ============
4923 22:58:32.272245 ========== PULL DRAM RESETB DOWN end =========
4924 22:58:32.275702 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4925 22:58:32.278544 ===================================
4926 22:58:32.281862 LPDDR4 DRAM CONFIGURATION
4927 22:58:32.285390 ===================================
4928 22:58:32.288559 EX_ROW_EN[0] = 0x0
4929 22:58:32.288661 EX_ROW_EN[1] = 0x0
4930 22:58:32.292148 LP4Y_EN = 0x0
4931 22:58:32.292259 WORK_FSP = 0x0
4932 22:58:32.295395 WL = 0x3
4933 22:58:32.295495 RL = 0x3
4934 22:58:32.298354 BL = 0x2
4935 22:58:32.298454 RPST = 0x0
4936 22:58:32.302010 RD_PRE = 0x0
4937 22:58:32.302112 WR_PRE = 0x1
4938 22:58:32.305277 WR_PST = 0x0
4939 22:58:32.305379 DBI_WR = 0x0
4940 22:58:32.308615 DBI_RD = 0x0
4941 22:58:32.308716 OTF = 0x1
4942 22:58:32.311956 ===================================
4943 22:58:32.315297 ===================================
4944 22:58:32.318471 ANA top config
4945 22:58:32.321830 ===================================
4946 22:58:32.325203 DLL_ASYNC_EN = 0
4947 22:58:32.325306 ALL_SLAVE_EN = 1
4948 22:58:32.328588 NEW_RANK_MODE = 1
4949 22:58:32.331959 DLL_IDLE_MODE = 1
4950 22:58:32.335281 LP45_APHY_COMB_EN = 1
4951 22:58:32.335384 TX_ODT_DIS = 1
4952 22:58:32.338249 NEW_8X_MODE = 1
4953 22:58:32.341700 ===================================
4954 22:58:32.345145 ===================================
4955 22:58:32.348518 data_rate = 1866
4956 22:58:32.351600 CKR = 1
4957 22:58:32.354798 DQ_P2S_RATIO = 8
4958 22:58:32.358209 ===================================
4959 22:58:32.361465 CA_P2S_RATIO = 8
4960 22:58:32.361575 DQ_CA_OPEN = 0
4961 22:58:32.364847 DQ_SEMI_OPEN = 0
4962 22:58:32.368157 CA_SEMI_OPEN = 0
4963 22:58:32.371579 CA_FULL_RATE = 0
4964 22:58:32.374528 DQ_CKDIV4_EN = 1
4965 22:58:32.378301 CA_CKDIV4_EN = 1
4966 22:58:32.378391 CA_PREDIV_EN = 0
4967 22:58:32.381139 PH8_DLY = 0
4968 22:58:32.384650 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4969 22:58:32.388153 DQ_AAMCK_DIV = 4
4970 22:58:32.391404 CA_AAMCK_DIV = 4
4971 22:58:32.394771 CA_ADMCK_DIV = 4
4972 22:58:32.394853 DQ_TRACK_CA_EN = 0
4973 22:58:32.398082 CA_PICK = 933
4974 22:58:32.400977 CA_MCKIO = 933
4975 22:58:32.404461 MCKIO_SEMI = 0
4976 22:58:32.407968 PLL_FREQ = 3732
4977 22:58:32.411077 DQ_UI_PI_RATIO = 32
4978 22:58:32.414630 CA_UI_PI_RATIO = 0
4979 22:58:32.418174 ===================================
4980 22:58:32.421084 ===================================
4981 22:58:32.421167 memory_type:LPDDR4
4982 22:58:32.424350 GP_NUM : 10
4983 22:58:32.427835 SRAM_EN : 1
4984 22:58:32.427917 MD32_EN : 0
4985 22:58:32.431184 ===================================
4986 22:58:32.434059 [ANA_INIT] >>>>>>>>>>>>>>
4987 22:58:32.437539 <<<<<< [CONFIGURE PHASE]: ANA_TX
4988 22:58:32.440791 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4989 22:58:32.444319 ===================================
4990 22:58:32.447604 data_rate = 1866,PCW = 0X8f00
4991 22:58:32.450659 ===================================
4992 22:58:32.454099 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4993 22:58:32.457577 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4994 22:58:32.464170 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4995 22:58:32.467430 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4996 22:58:32.470815 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4997 22:58:32.477126 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4998 22:58:32.477209 [ANA_INIT] flow start
4999 22:58:32.480527 [ANA_INIT] PLL >>>>>>>>
5000 22:58:32.480609 [ANA_INIT] PLL <<<<<<<<
5001 22:58:32.483787 [ANA_INIT] MIDPI >>>>>>>>
5002 22:58:32.487153 [ANA_INIT] MIDPI <<<<<<<<
5003 22:58:32.490528 [ANA_INIT] DLL >>>>>>>>
5004 22:58:32.490632 [ANA_INIT] flow end
5005 22:58:32.493439 ============ LP4 DIFF to SE enter ============
5006 22:58:32.500011 ============ LP4 DIFF to SE exit ============
5007 22:58:32.500094 [ANA_INIT] <<<<<<<<<<<<<
5008 22:58:32.503433 [Flow] Enable top DCM control >>>>>
5009 22:58:32.506927 [Flow] Enable top DCM control <<<<<
5010 22:58:32.510145 Enable DLL master slave shuffle
5011 22:58:32.516917 ==============================================================
5012 22:58:32.519939 Gating Mode config
5013 22:58:32.523320 ==============================================================
5014 22:58:32.527003 Config description:
5015 22:58:32.536691 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5016 22:58:32.543287 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5017 22:58:32.546669 SELPH_MODE 0: By rank 1: By Phase
5018 22:58:32.553065 ==============================================================
5019 22:58:32.556577 GAT_TRACK_EN = 1
5020 22:58:32.559955 RX_GATING_MODE = 2
5021 22:58:32.563226 RX_GATING_TRACK_MODE = 2
5022 22:58:32.563305 SELPH_MODE = 1
5023 22:58:32.566366 PICG_EARLY_EN = 1
5024 22:58:32.569803 VALID_LAT_VALUE = 1
5025 22:58:32.576539 ==============================================================
5026 22:58:32.579469 Enter into Gating configuration >>>>
5027 22:58:32.582999 Exit from Gating configuration <<<<
5028 22:58:32.586384 Enter into DVFS_PRE_config >>>>>
5029 22:58:32.595965 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5030 22:58:32.599589 Exit from DVFS_PRE_config <<<<<
5031 22:58:32.602965 Enter into PICG configuration >>>>
5032 22:58:32.606365 Exit from PICG configuration <<<<
5033 22:58:32.609353 [RX_INPUT] configuration >>>>>
5034 22:58:32.612683 [RX_INPUT] configuration <<<<<
5035 22:58:32.615924 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5036 22:58:32.622605 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5037 22:58:32.629464 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5038 22:58:32.636037 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5039 22:58:32.642534 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5040 22:58:32.645921 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5041 22:58:32.652303 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5042 22:58:32.655690 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5043 22:58:32.659144 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5044 22:58:32.662620 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5045 22:58:32.669270 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5046 22:58:32.672254 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5047 22:58:32.675506 ===================================
5048 22:58:32.678948 LPDDR4 DRAM CONFIGURATION
5049 22:58:32.682421 ===================================
5050 22:58:32.682507 EX_ROW_EN[0] = 0x0
5051 22:58:32.685387 EX_ROW_EN[1] = 0x0
5052 22:58:32.685471 LP4Y_EN = 0x0
5053 22:58:32.688755 WORK_FSP = 0x0
5054 22:58:32.688847 WL = 0x3
5055 22:58:32.692217 RL = 0x3
5056 22:58:32.692349 BL = 0x2
5057 22:58:32.695419 RPST = 0x0
5058 22:58:32.695500 RD_PRE = 0x0
5059 22:58:32.698623 WR_PRE = 0x1
5060 22:58:32.701900 WR_PST = 0x0
5061 22:58:32.701986 DBI_WR = 0x0
5062 22:58:32.705509 DBI_RD = 0x0
5063 22:58:32.705590 OTF = 0x1
5064 22:58:32.708871 ===================================
5065 22:58:32.711817 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5066 22:58:32.718394 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5067 22:58:32.722126 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5068 22:58:32.725117 ===================================
5069 22:58:32.728434 LPDDR4 DRAM CONFIGURATION
5070 22:58:32.731958 ===================================
5071 22:58:32.732042 EX_ROW_EN[0] = 0x10
5072 22:58:32.735187 EX_ROW_EN[1] = 0x0
5073 22:58:32.735270 LP4Y_EN = 0x0
5074 22:58:32.738361 WORK_FSP = 0x0
5075 22:58:32.738445 WL = 0x3
5076 22:58:32.741645 RL = 0x3
5077 22:58:32.741728 BL = 0x2
5078 22:58:32.745071 RPST = 0x0
5079 22:58:32.745154 RD_PRE = 0x0
5080 22:58:32.748531 WR_PRE = 0x1
5081 22:58:32.751271 WR_PST = 0x0
5082 22:58:32.751387 DBI_WR = 0x0
5083 22:58:32.755162 DBI_RD = 0x0
5084 22:58:32.755248 OTF = 0x1
5085 22:58:32.758054 ===================================
5086 22:58:32.764501 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5087 22:58:32.768386 nWR fixed to 30
5088 22:58:32.771946 [ModeRegInit_LP4] CH0 RK0
5089 22:58:32.772031 [ModeRegInit_LP4] CH0 RK1
5090 22:58:32.775295 [ModeRegInit_LP4] CH1 RK0
5091 22:58:32.778138 [ModeRegInit_LP4] CH1 RK1
5092 22:58:32.778226 match AC timing 9
5093 22:58:32.785215 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5094 22:58:32.788019 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5095 22:58:32.791587 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5096 22:58:32.798426 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5097 22:58:32.801753 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5098 22:58:32.801838 ==
5099 22:58:32.804572 Dram Type= 6, Freq= 0, CH_0, rank 0
5100 22:58:32.808231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5101 22:58:32.808315 ==
5102 22:58:32.814678 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5103 22:58:32.821101 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5104 22:58:32.824669 [CA 0] Center 38 (7~69) winsize 63
5105 22:58:32.828099 [CA 1] Center 38 (8~69) winsize 62
5106 22:58:32.831501 [CA 2] Center 35 (5~66) winsize 62
5107 22:58:32.834539 [CA 3] Center 34 (4~65) winsize 62
5108 22:58:32.837861 [CA 4] Center 34 (4~65) winsize 62
5109 22:58:32.841027 [CA 5] Center 33 (3~64) winsize 62
5110 22:58:32.841135
5111 22:58:32.844686 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5112 22:58:32.844812
5113 22:58:32.847645 [CATrainingPosCal] consider 1 rank data
5114 22:58:32.850954 u2DelayCellTimex100 = 270/100 ps
5115 22:58:32.854282 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5116 22:58:32.857599 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5117 22:58:32.861041 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5118 22:58:32.864387 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5119 22:58:32.870804 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5120 22:58:32.874113 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5121 22:58:32.874220
5122 22:58:32.877758 CA PerBit enable=1, Macro0, CA PI delay=33
5123 22:58:32.877867
5124 22:58:32.880669 [CBTSetCACLKResult] CA Dly = 33
5125 22:58:32.880785 CS Dly: 6 (0~37)
5126 22:58:32.880881 ==
5127 22:58:32.883933 Dram Type= 6, Freq= 0, CH_0, rank 1
5128 22:58:32.890653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5129 22:58:32.890763 ==
5130 22:58:32.894044 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5131 22:58:32.900357 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5132 22:58:32.903784 [CA 0] Center 38 (8~69) winsize 62
5133 22:58:32.907273 [CA 1] Center 38 (8~69) winsize 62
5134 22:58:32.910905 [CA 2] Center 36 (6~66) winsize 61
5135 22:58:32.914093 [CA 3] Center 35 (5~66) winsize 62
5136 22:58:32.917330 [CA 4] Center 35 (5~65) winsize 61
5137 22:58:32.920632 [CA 5] Center 34 (4~64) winsize 61
5138 22:58:32.920737
5139 22:58:32.924077 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5140 22:58:32.924182
5141 22:58:32.927410 [CATrainingPosCal] consider 2 rank data
5142 22:58:32.930665 u2DelayCellTimex100 = 270/100 ps
5143 22:58:32.934063 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5144 22:58:32.937435 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5145 22:58:32.943495 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5146 22:58:32.946786 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5147 22:58:32.950436 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5148 22:58:32.953479 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5149 22:58:32.953563
5150 22:58:32.956707 CA PerBit enable=1, Macro0, CA PI delay=34
5151 22:58:32.956829
5152 22:58:32.959793 [CBTSetCACLKResult] CA Dly = 34
5153 22:58:32.959875 CS Dly: 7 (0~40)
5154 22:58:32.963211
5155 22:58:32.966677 ----->DramcWriteLeveling(PI) begin...
5156 22:58:32.966763 ==
5157 22:58:32.970152 Dram Type= 6, Freq= 0, CH_0, rank 0
5158 22:58:32.973137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5159 22:58:32.973223 ==
5160 22:58:32.976591 Write leveling (Byte 0): 35 => 35
5161 22:58:32.979809 Write leveling (Byte 1): 30 => 30
5162 22:58:32.982985 DramcWriteLeveling(PI) end<-----
5163 22:58:32.983070
5164 22:58:32.983136 ==
5165 22:58:32.986524 Dram Type= 6, Freq= 0, CH_0, rank 0
5166 22:58:32.989704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5167 22:58:32.989788 ==
5168 22:58:32.993073 [Gating] SW mode calibration
5169 22:58:32.999429 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5170 22:58:33.006438 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5171 22:58:33.009820 0 14 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5172 22:58:33.012710 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5173 22:58:33.019355 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5174 22:58:33.023049 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5175 22:58:33.025987 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5176 22:58:33.032652 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5177 22:58:33.035907 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 0)
5178 22:58:33.039356 0 14 28 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
5179 22:58:33.046100 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
5180 22:58:33.049601 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5181 22:58:33.052884 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5182 22:58:33.059273 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5183 22:58:33.062610 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5184 22:58:33.065797 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5185 22:58:33.072609 0 15 24 | B1->B0 | 2323 3130 | 0 1 | (0 0) (0 0)
5186 22:58:33.075647 0 15 28 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
5187 22:58:33.079138 1 0 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5188 22:58:33.085613 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5189 22:58:33.089024 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5190 22:58:33.092257 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 22:58:33.098843 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5192 22:58:33.102291 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 22:58:33.105274 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5194 22:58:33.112124 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5195 22:58:33.115442 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5196 22:58:33.118422 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 22:58:33.125008 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 22:58:33.128667 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 22:58:33.131914 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 22:58:33.138479 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 22:58:33.141815 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 22:58:33.145120 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 22:58:33.151865 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 22:58:33.155033 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 22:58:33.158307 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 22:58:33.164712 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 22:58:33.167885 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 22:58:33.171344 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 22:58:33.177997 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5210 22:58:33.181502 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5211 22:58:33.184899 Total UI for P1: 0, mck2ui 16
5212 22:58:33.187779 best dqsien dly found for B0: ( 1, 2, 24)
5213 22:58:33.191306 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5214 22:58:33.194773 Total UI for P1: 0, mck2ui 16
5215 22:58:33.198190 best dqsien dly found for B1: ( 1, 2, 28)
5216 22:58:33.201496 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5217 22:58:33.204930 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5218 22:58:33.205012
5219 22:58:33.207703 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5220 22:58:33.214629 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5221 22:58:33.214752 [Gating] SW calibration Done
5222 22:58:33.214845 ==
5223 22:58:33.217933 Dram Type= 6, Freq= 0, CH_0, rank 0
5224 22:58:33.224291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5225 22:58:33.224399 ==
5226 22:58:33.224492 RX Vref Scan: 0
5227 22:58:33.224581
5228 22:58:33.227687 RX Vref 0 -> 0, step: 1
5229 22:58:33.227796
5230 22:58:33.231022 RX Delay -80 -> 252, step: 8
5231 22:58:33.234157 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5232 22:58:33.237621 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5233 22:58:33.240833 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5234 22:58:33.247615 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5235 22:58:33.250968 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5236 22:58:33.254014 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5237 22:58:33.257494 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5238 22:58:33.260549 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5239 22:58:33.267560 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5240 22:58:33.270802 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5241 22:58:33.274033 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5242 22:58:33.277452 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5243 22:58:33.280746 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5244 22:58:33.284182 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5245 22:58:33.290520 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5246 22:58:33.294167 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5247 22:58:33.294286 ==
5248 22:58:33.297425 Dram Type= 6, Freq= 0, CH_0, rank 0
5249 22:58:33.300321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5250 22:58:33.300404 ==
5251 22:58:33.303655 DQS Delay:
5252 22:58:33.303736 DQS0 = 0, DQS1 = 0
5253 22:58:33.303800 DQM Delay:
5254 22:58:33.306991 DQM0 = 107, DQM1 = 91
5255 22:58:33.307072 DQ Delay:
5256 22:58:33.310433 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =103
5257 22:58:33.313487 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =115
5258 22:58:33.317247 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5259 22:58:33.320174 DQ12 =91, DQ13 =91, DQ14 =103, DQ15 =103
5260 22:58:33.323666
5261 22:58:33.323746
5262 22:58:33.323810 ==
5263 22:58:33.327063 Dram Type= 6, Freq= 0, CH_0, rank 0
5264 22:58:33.330021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5265 22:58:33.330119 ==
5266 22:58:33.330186
5267 22:58:33.330247
5268 22:58:33.333429 TX Vref Scan disable
5269 22:58:33.333510 == TX Byte 0 ==
5270 22:58:33.340126 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5271 22:58:33.343455 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5272 22:58:33.343557 == TX Byte 1 ==
5273 22:58:33.349896 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5274 22:58:33.353243 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5275 22:58:33.353325 ==
5276 22:58:33.356654 Dram Type= 6, Freq= 0, CH_0, rank 0
5277 22:58:33.360074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5278 22:58:33.360157 ==
5279 22:58:33.360221
5280 22:58:33.360281
5281 22:58:33.363382 TX Vref Scan disable
5282 22:58:33.366610 == TX Byte 0 ==
5283 22:58:33.369635 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5284 22:58:33.373374 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5285 22:58:33.376783 == TX Byte 1 ==
5286 22:58:33.379932 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5287 22:58:33.382859 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5288 22:58:33.382943
5289 22:58:33.386304 [DATLAT]
5290 22:58:33.386396 Freq=933, CH0 RK0
5291 22:58:33.386481
5292 22:58:33.389745 DATLAT Default: 0xd
5293 22:58:33.389828 0, 0xFFFF, sum = 0
5294 22:58:33.393075 1, 0xFFFF, sum = 0
5295 22:58:33.393159 2, 0xFFFF, sum = 0
5296 22:58:33.396522 3, 0xFFFF, sum = 0
5297 22:58:33.396633 4, 0xFFFF, sum = 0
5298 22:58:33.399757 5, 0xFFFF, sum = 0
5299 22:58:33.399841 6, 0xFFFF, sum = 0
5300 22:58:33.403156 7, 0xFFFF, sum = 0
5301 22:58:33.405974 8, 0xFFFF, sum = 0
5302 22:58:33.406077 9, 0xFFFF, sum = 0
5303 22:58:33.409351 10, 0x0, sum = 1
5304 22:58:33.409436 11, 0x0, sum = 2
5305 22:58:33.409502 12, 0x0, sum = 3
5306 22:58:33.412779 13, 0x0, sum = 4
5307 22:58:33.412864 best_step = 11
5308 22:58:33.412930
5309 22:58:33.412992 ==
5310 22:58:33.416242 Dram Type= 6, Freq= 0, CH_0, rank 0
5311 22:58:33.423022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5312 22:58:33.423107 ==
5313 22:58:33.423173 RX Vref Scan: 1
5314 22:58:33.423235
5315 22:58:33.426080 RX Vref 0 -> 0, step: 1
5316 22:58:33.426163
5317 22:58:33.429640 RX Delay -53 -> 252, step: 4
5318 22:58:33.429724
5319 22:58:33.432510 Set Vref, RX VrefLevel [Byte0]: 59
5320 22:58:33.436135 [Byte1]: 50
5321 22:58:33.436218
5322 22:58:33.439071 Final RX Vref Byte 0 = 59 to rank0
5323 22:58:33.442611 Final RX Vref Byte 1 = 50 to rank0
5324 22:58:33.445973 Final RX Vref Byte 0 = 59 to rank1
5325 22:58:33.449213 Final RX Vref Byte 1 = 50 to rank1==
5326 22:58:33.452586 Dram Type= 6, Freq= 0, CH_0, rank 0
5327 22:58:33.455706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5328 22:58:33.455790 ==
5329 22:58:33.459243 DQS Delay:
5330 22:58:33.459327 DQS0 = 0, DQS1 = 0
5331 22:58:33.462386 DQM Delay:
5332 22:58:33.462471 DQM0 = 107, DQM1 = 92
5333 22:58:33.465645 DQ Delay:
5334 22:58:33.468761 DQ0 =108, DQ1 =108, DQ2 =102, DQ3 =106
5335 22:58:33.472260 DQ4 =106, DQ5 =100, DQ6 =116, DQ7 =114
5336 22:58:33.475690 DQ8 =88, DQ9 =78, DQ10 =92, DQ11 =90
5337 22:58:33.479007 DQ12 =96, DQ13 =94, DQ14 =104, DQ15 =98
5338 22:58:33.479090
5339 22:58:33.479156
5340 22:58:33.485358 [DQSOSCAuto] RK0, (LSB)MR18= 0x2824, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
5341 22:58:33.488659 CH0 RK0: MR19=505, MR18=2824
5342 22:58:33.495099 CH0_RK0: MR19=0x505, MR18=0x2824, DQSOSC=409, MR23=63, INC=64, DEC=43
5343 22:58:33.495182
5344 22:58:33.498549 ----->DramcWriteLeveling(PI) begin...
5345 22:58:33.498632 ==
5346 22:58:33.501800 Dram Type= 6, Freq= 0, CH_0, rank 1
5347 22:58:33.505566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5348 22:58:33.505649 ==
5349 22:58:33.508533 Write leveling (Byte 0): 31 => 31
5350 22:58:33.512006 Write leveling (Byte 1): 28 => 28
5351 22:58:33.515155 DramcWriteLeveling(PI) end<-----
5352 22:58:33.515257
5353 22:58:33.515350 ==
5354 22:58:33.518562 Dram Type= 6, Freq= 0, CH_0, rank 1
5355 22:58:33.522073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5356 22:58:33.524913 ==
5357 22:58:33.525022 [Gating] SW mode calibration
5358 22:58:33.535091 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5359 22:58:33.538533 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5360 22:58:33.541618 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5361 22:58:33.548295 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5362 22:58:33.551488 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5363 22:58:33.554880 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5364 22:58:33.561621 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5365 22:58:33.564843 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5366 22:58:33.568439 0 14 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (0 0)
5367 22:58:33.574902 0 14 28 | B1->B0 | 2c2c 2525 | 1 0 | (1 0) (0 1)
5368 22:58:33.578335 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
5369 22:58:33.581616 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5370 22:58:33.588018 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5371 22:58:33.591492 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5372 22:58:33.594323 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5373 22:58:33.601257 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5374 22:58:33.604552 0 15 24 | B1->B0 | 2828 2e2e | 0 0 | (1 1) (0 0)
5375 22:58:33.607837 0 15 28 | B1->B0 | 3838 3f3e | 1 1 | (0 0) (0 0)
5376 22:58:33.614612 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 22:58:33.617949 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 22:58:33.620886 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 22:58:33.627678 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 22:58:33.630983 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 22:58:33.634394 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5382 22:58:33.640753 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 22:58:33.644127 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 22:58:33.647497 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5385 22:58:33.654013 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 22:58:33.657258 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 22:58:33.660502 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 22:58:33.667459 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 22:58:33.670325 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 22:58:33.673630 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 22:58:33.680567 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 22:58:33.683747 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 22:58:33.687025 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 22:58:33.693675 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 22:58:33.697099 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 22:58:33.700488 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 22:58:33.706804 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 22:58:33.710170 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5399 22:58:33.713538 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5400 22:58:33.720366 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5401 22:58:33.720453 Total UI for P1: 0, mck2ui 16
5402 22:58:33.723718 best dqsien dly found for B0: ( 1, 2, 26)
5403 22:58:33.727000 Total UI for P1: 0, mck2ui 16
5404 22:58:33.729907 best dqsien dly found for B1: ( 1, 2, 26)
5405 22:58:33.733399 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5406 22:58:33.740184 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5407 22:58:33.740261
5408 22:58:33.743203 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5409 22:58:33.746578 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5410 22:58:33.750051 [Gating] SW calibration Done
5411 22:58:33.750124 ==
5412 22:58:33.753051 Dram Type= 6, Freq= 0, CH_0, rank 1
5413 22:58:33.756466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5414 22:58:33.756552 ==
5415 22:58:33.759725 RX Vref Scan: 0
5416 22:58:33.759797
5417 22:58:33.759860 RX Vref 0 -> 0, step: 1
5418 22:58:33.759918
5419 22:58:33.763358 RX Delay -80 -> 252, step: 8
5420 22:58:33.766344 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5421 22:58:33.773049 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5422 22:58:33.776283 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5423 22:58:33.779527 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5424 22:58:33.782963 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5425 22:58:33.786209 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5426 22:58:33.789721 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5427 22:58:33.796328 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5428 22:58:33.799557 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5429 22:58:33.803062 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5430 22:58:33.805953 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5431 22:58:33.809443 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5432 22:58:33.812986 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5433 22:58:33.819500 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5434 22:58:33.822885 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5435 22:58:33.825772 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5436 22:58:33.825857 ==
5437 22:58:33.829481 Dram Type= 6, Freq= 0, CH_0, rank 1
5438 22:58:33.832486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5439 22:58:33.832571 ==
5440 22:58:33.835948 DQS Delay:
5441 22:58:33.836032 DQS0 = 0, DQS1 = 0
5442 22:58:33.839445 DQM Delay:
5443 22:58:33.839528 DQM0 = 105, DQM1 = 89
5444 22:58:33.839595 DQ Delay:
5445 22:58:33.842748 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5446 22:58:33.845615 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =111
5447 22:58:33.849065 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5448 22:58:33.852421 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =95
5449 22:58:33.855877
5450 22:58:33.855960
5451 22:58:33.856026 ==
5452 22:58:33.859217 Dram Type= 6, Freq= 0, CH_0, rank 1
5453 22:58:33.862158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5454 22:58:33.862244 ==
5455 22:58:33.862312
5456 22:58:33.862373
5457 22:58:33.865498 TX Vref Scan disable
5458 22:58:33.865583 == TX Byte 0 ==
5459 22:58:33.872516 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5460 22:58:33.875472 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5461 22:58:33.875556 == TX Byte 1 ==
5462 22:58:33.882165 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5463 22:58:33.885513 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5464 22:58:33.885597 ==
5465 22:58:33.888567 Dram Type= 6, Freq= 0, CH_0, rank 1
5466 22:58:33.892237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5467 22:58:33.892324 ==
5468 22:58:33.892391
5469 22:58:33.892453
5470 22:58:33.895195 TX Vref Scan disable
5471 22:58:33.898939 == TX Byte 0 ==
5472 22:58:33.901987 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5473 22:58:33.905049 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5474 22:58:33.908727 == TX Byte 1 ==
5475 22:58:33.911754 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5476 22:58:33.915163 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5477 22:58:33.915248
5478 22:58:33.918572 [DATLAT]
5479 22:58:33.918669 Freq=933, CH0 RK1
5480 22:58:33.918774
5481 22:58:33.921665 DATLAT Default: 0xb
5482 22:58:33.921765 0, 0xFFFF, sum = 0
5483 22:58:33.925064 1, 0xFFFF, sum = 0
5484 22:58:33.925150 2, 0xFFFF, sum = 0
5485 22:58:33.928479 3, 0xFFFF, sum = 0
5486 22:58:33.928564 4, 0xFFFF, sum = 0
5487 22:58:33.931764 5, 0xFFFF, sum = 0
5488 22:58:33.934754 6, 0xFFFF, sum = 0
5489 22:58:33.934839 7, 0xFFFF, sum = 0
5490 22:58:33.938498 8, 0xFFFF, sum = 0
5491 22:58:33.938584 9, 0xFFFF, sum = 0
5492 22:58:33.941460 10, 0x0, sum = 1
5493 22:58:33.941545 11, 0x0, sum = 2
5494 22:58:33.941613 12, 0x0, sum = 3
5495 22:58:33.944963 13, 0x0, sum = 4
5496 22:58:33.945049 best_step = 11
5497 22:58:33.945115
5498 22:58:33.947929 ==
5499 22:58:33.948013 Dram Type= 6, Freq= 0, CH_0, rank 1
5500 22:58:33.954884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5501 22:58:33.954969 ==
5502 22:58:33.955036 RX Vref Scan: 0
5503 22:58:33.955097
5504 22:58:33.958327 RX Vref 0 -> 0, step: 1
5505 22:58:33.958414
5506 22:58:33.961337 RX Delay -53 -> 252, step: 4
5507 22:58:33.964626 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5508 22:58:33.970909 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5509 22:58:33.974724 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5510 22:58:33.978010 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5511 22:58:33.981101 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5512 22:58:33.984502 iDelay=199, Bit 5, Center 100 (15 ~ 186) 172
5513 22:58:33.991183 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5514 22:58:33.994495 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5515 22:58:33.997671 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5516 22:58:34.001144 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5517 22:58:34.004465 iDelay=199, Bit 10, Center 92 (7 ~ 178) 172
5518 22:58:34.010877 iDelay=199, Bit 11, Center 90 (7 ~ 174) 168
5519 22:58:34.014119 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5520 22:58:34.017472 iDelay=199, Bit 13, Center 96 (15 ~ 178) 164
5521 22:58:34.020701 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5522 22:58:34.024123 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5523 22:58:34.024205 ==
5524 22:58:34.027396 Dram Type= 6, Freq= 0, CH_0, rank 1
5525 22:58:34.033960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5526 22:58:34.034043 ==
5527 22:58:34.034109 DQS Delay:
5528 22:58:34.037350 DQS0 = 0, DQS1 = 0
5529 22:58:34.037479 DQM Delay:
5530 22:58:34.040789 DQM0 = 104, DQM1 = 92
5531 22:58:34.040876 DQ Delay:
5532 22:58:34.044124 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =98
5533 22:58:34.047030 DQ4 =106, DQ5 =100, DQ6 =112, DQ7 =112
5534 22:58:34.050476 DQ8 =86, DQ9 =80, DQ10 =92, DQ11 =90
5535 22:58:34.053856 DQ12 =98, DQ13 =96, DQ14 =100, DQ15 =98
5536 22:58:34.053938
5537 22:58:34.054002
5538 22:58:34.060656 [DQSOSCAuto] RK1, (LSB)MR18= 0x2507, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 410 ps
5539 22:58:34.063511 CH0 RK1: MR19=505, MR18=2507
5540 22:58:34.070308 CH0_RK1: MR19=0x505, MR18=0x2507, DQSOSC=410, MR23=63, INC=64, DEC=42
5541 22:58:34.073694 [RxdqsGatingPostProcess] freq 933
5542 22:58:34.080112 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5543 22:58:34.083523 best DQS0 dly(2T, 0.5T) = (0, 10)
5544 22:58:34.086454 best DQS1 dly(2T, 0.5T) = (0, 10)
5545 22:58:34.089806 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5546 22:58:34.093602 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5547 22:58:34.093684 best DQS0 dly(2T, 0.5T) = (0, 10)
5548 22:58:34.096626 best DQS1 dly(2T, 0.5T) = (0, 10)
5549 22:58:34.099991 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5550 22:58:34.103123 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5551 22:58:34.106494 Pre-setting of DQS Precalculation
5552 22:58:34.113016 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5553 22:58:34.113098 ==
5554 22:58:34.116263 Dram Type= 6, Freq= 0, CH_1, rank 0
5555 22:58:34.119509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5556 22:58:34.119621 ==
5557 22:58:34.126017 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5558 22:58:34.132707 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5559 22:58:34.136130 [CA 0] Center 37 (7~68) winsize 62
5560 22:58:34.139131 [CA 1] Center 37 (7~68) winsize 62
5561 22:58:34.142701 [CA 2] Center 35 (5~65) winsize 61
5562 22:58:34.145805 [CA 3] Center 35 (5~65) winsize 61
5563 22:58:34.149248 [CA 4] Center 35 (5~66) winsize 62
5564 22:58:34.152630 [CA 5] Center 34 (4~65) winsize 62
5565 22:58:34.152741
5566 22:58:34.155657 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5567 22:58:34.155740
5568 22:58:34.159226 [CATrainingPosCal] consider 1 rank data
5569 22:58:34.162583 u2DelayCellTimex100 = 270/100 ps
5570 22:58:34.165455 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5571 22:58:34.168891 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5572 22:58:34.172282 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5573 22:58:34.175618 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5574 22:58:34.179028 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5575 22:58:34.182380 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5576 22:58:34.185731
5577 22:58:34.188600 CA PerBit enable=1, Macro0, CA PI delay=34
5578 22:58:34.188712
5579 22:58:34.191989 [CBTSetCACLKResult] CA Dly = 34
5580 22:58:34.192074 CS Dly: 6 (0~37)
5581 22:58:34.192141 ==
5582 22:58:34.195161 Dram Type= 6, Freq= 0, CH_1, rank 1
5583 22:58:34.198483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5584 22:58:34.198566 ==
5585 22:58:34.205298 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5586 22:58:34.211863 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5587 22:58:34.215218 [CA 0] Center 38 (7~69) winsize 63
5588 22:58:34.218547 [CA 1] Center 38 (7~69) winsize 63
5589 22:58:34.221503 [CA 2] Center 36 (6~66) winsize 61
5590 22:58:34.224795 [CA 3] Center 35 (6~65) winsize 60
5591 22:58:34.228028 [CA 4] Center 35 (6~65) winsize 60
5592 22:58:34.231422 [CA 5] Center 35 (5~65) winsize 61
5593 22:58:34.231505
5594 22:58:34.234695 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5595 22:58:34.234779
5596 22:58:34.237923 [CATrainingPosCal] consider 2 rank data
5597 22:58:34.241288 u2DelayCellTimex100 = 270/100 ps
5598 22:58:34.244516 CA0 delay=37 (7~68),Diff = 2 PI (12 cell)
5599 22:58:34.248317 CA1 delay=37 (7~68),Diff = 2 PI (12 cell)
5600 22:58:34.251138 CA2 delay=35 (6~65),Diff = 0 PI (0 cell)
5601 22:58:34.257931 CA3 delay=35 (6~65),Diff = 0 PI (0 cell)
5602 22:58:34.260967 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
5603 22:58:34.264436 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5604 22:58:34.264518
5605 22:58:34.267829 CA PerBit enable=1, Macro0, CA PI delay=35
5606 22:58:34.267912
5607 22:58:34.271181 [CBTSetCACLKResult] CA Dly = 35
5608 22:58:34.271264 CS Dly: 7 (0~39)
5609 22:58:34.271329
5610 22:58:34.274565 ----->DramcWriteLeveling(PI) begin...
5611 22:58:34.277512 ==
5612 22:58:34.277594 Dram Type= 6, Freq= 0, CH_1, rank 0
5613 22:58:34.284214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5614 22:58:34.284299 ==
5615 22:58:34.287529 Write leveling (Byte 0): 29 => 29
5616 22:58:34.291008 Write leveling (Byte 1): 29 => 29
5617 22:58:34.294445 DramcWriteLeveling(PI) end<-----
5618 22:58:34.294529
5619 22:58:34.294596 ==
5620 22:58:34.297780 Dram Type= 6, Freq= 0, CH_1, rank 0
5621 22:58:34.301133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5622 22:58:34.301218 ==
5623 22:58:34.304350 [Gating] SW mode calibration
5624 22:58:34.310544 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5625 22:58:34.317306 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5626 22:58:34.320598 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5627 22:58:34.323921 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5628 22:58:34.330599 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5629 22:58:34.333786 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5630 22:58:34.337127 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5631 22:58:34.343952 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5632 22:58:34.346877 0 14 24 | B1->B0 | 3131 2f2f | 1 1 | (1 1) (1 0)
5633 22:58:34.350116 0 14 28 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
5634 22:58:34.356779 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5635 22:58:34.360164 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5636 22:58:34.363619 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5637 22:58:34.370027 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5638 22:58:34.373398 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5639 22:58:34.376488 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5640 22:58:34.383280 0 15 24 | B1->B0 | 2929 3030 | 0 0 | (0 0) (0 0)
5641 22:58:34.386624 0 15 28 | B1->B0 | 3f3f 4141 | 0 0 | (1 1) (0 0)
5642 22:58:34.389897 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 22:58:34.393380 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 22:58:34.400207 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 22:58:34.403452 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5646 22:58:34.406611 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5647 22:58:34.413374 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5648 22:58:34.416514 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5649 22:58:34.419528 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5650 22:58:34.426621 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 22:58:34.429549 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 22:58:34.433051 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 22:58:34.439694 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 22:58:34.442813 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 22:58:34.446423 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 22:58:34.452896 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 22:58:34.456277 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 22:58:34.459595 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 22:58:34.466080 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 22:58:34.469510 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 22:58:34.472424 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 22:58:34.479260 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 22:58:34.482652 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5664 22:58:34.486153 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5665 22:58:34.492323 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5666 22:58:34.495641 Total UI for P1: 0, mck2ui 16
5667 22:58:34.499133 best dqsien dly found for B0: ( 1, 2, 22)
5668 22:58:34.502531 Total UI for P1: 0, mck2ui 16
5669 22:58:34.505438 best dqsien dly found for B1: ( 1, 2, 24)
5670 22:58:34.508691 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5671 22:58:34.512138 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5672 22:58:34.512221
5673 22:58:34.515605 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5674 22:58:34.518812 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5675 22:58:34.522220 [Gating] SW calibration Done
5676 22:58:34.522303 ==
5677 22:58:34.525658 Dram Type= 6, Freq= 0, CH_1, rank 0
5678 22:58:34.528974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5679 22:58:34.529057 ==
5680 22:58:34.532214 RX Vref Scan: 0
5681 22:58:34.532331
5682 22:58:34.535200 RX Vref 0 -> 0, step: 1
5683 22:58:34.535273
5684 22:58:34.535334 RX Delay -80 -> 252, step: 8
5685 22:58:34.542046 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5686 22:58:34.545289 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5687 22:58:34.548884 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5688 22:58:34.551937 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5689 22:58:34.555149 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5690 22:58:34.561755 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5691 22:58:34.565002 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5692 22:58:34.568591 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5693 22:58:34.571535 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5694 22:58:34.574969 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5695 22:58:34.578381 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5696 22:58:34.584999 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5697 22:58:34.588496 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5698 22:58:34.591411 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5699 22:58:34.594862 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5700 22:58:34.598190 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5701 22:58:34.598272 ==
5702 22:58:34.601524 Dram Type= 6, Freq= 0, CH_1, rank 0
5703 22:58:34.608397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5704 22:58:34.608480 ==
5705 22:58:34.608545 DQS Delay:
5706 22:58:34.611648 DQS0 = 0, DQS1 = 0
5707 22:58:34.611731 DQM Delay:
5708 22:58:34.611796 DQM0 = 102, DQM1 = 95
5709 22:58:34.614842 DQ Delay:
5710 22:58:34.618416 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =103
5711 22:58:34.621224 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =99
5712 22:58:34.625023 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5713 22:58:34.627950 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99
5714 22:58:34.628032
5715 22:58:34.628097
5716 22:58:34.628156 ==
5717 22:58:34.631271 Dram Type= 6, Freq= 0, CH_1, rank 0
5718 22:58:34.634601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5719 22:58:34.634703 ==
5720 22:58:34.634769
5721 22:58:34.638070
5722 22:58:34.638152 TX Vref Scan disable
5723 22:58:34.641415 == TX Byte 0 ==
5724 22:58:34.644272 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5725 22:58:34.647740 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5726 22:58:34.651098 == TX Byte 1 ==
5727 22:58:34.654330 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5728 22:58:34.657791 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5729 22:58:34.657887 ==
5730 22:58:34.660991 Dram Type= 6, Freq= 0, CH_1, rank 0
5731 22:58:34.667472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 22:58:34.667611 ==
5733 22:58:34.667704
5734 22:58:34.667795
5735 22:58:34.667869 TX Vref Scan disable
5736 22:58:34.671918 == TX Byte 0 ==
5737 22:58:34.674906 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5738 22:58:34.681628 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5739 22:58:34.681711 == TX Byte 1 ==
5740 22:58:34.684939 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5741 22:58:34.691312 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5742 22:58:34.691422
5743 22:58:34.691518 [DATLAT]
5744 22:58:34.691630 Freq=933, CH1 RK0
5745 22:58:34.691729
5746 22:58:34.694688 DATLAT Default: 0xd
5747 22:58:34.698149 0, 0xFFFF, sum = 0
5748 22:58:34.698233 1, 0xFFFF, sum = 0
5749 22:58:34.701417 2, 0xFFFF, sum = 0
5750 22:58:34.701577 3, 0xFFFF, sum = 0
5751 22:58:34.704702 4, 0xFFFF, sum = 0
5752 22:58:34.704825 5, 0xFFFF, sum = 0
5753 22:58:34.708140 6, 0xFFFF, sum = 0
5754 22:58:34.708223 7, 0xFFFF, sum = 0
5755 22:58:34.711476 8, 0xFFFF, sum = 0
5756 22:58:34.711559 9, 0xFFFF, sum = 0
5757 22:58:34.714418 10, 0x0, sum = 1
5758 22:58:34.714518 11, 0x0, sum = 2
5759 22:58:34.718013 12, 0x0, sum = 3
5760 22:58:34.718097 13, 0x0, sum = 4
5761 22:58:34.718163 best_step = 11
5762 22:58:34.721412
5763 22:58:34.721519 ==
5764 22:58:34.724433 Dram Type= 6, Freq= 0, CH_1, rank 0
5765 22:58:34.728105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5766 22:58:34.728205 ==
5767 22:58:34.728295 RX Vref Scan: 1
5768 22:58:34.728383
5769 22:58:34.730991 RX Vref 0 -> 0, step: 1
5770 22:58:34.731075
5771 22:58:34.734526 RX Delay -53 -> 252, step: 4
5772 22:58:34.734609
5773 22:58:34.737814 Set Vref, RX VrefLevel [Byte0]: 53
5774 22:58:34.740644 [Byte1]: 52
5775 22:58:34.744095
5776 22:58:34.744198 Final RX Vref Byte 0 = 53 to rank0
5777 22:58:34.747647 Final RX Vref Byte 1 = 52 to rank0
5778 22:58:34.750913 Final RX Vref Byte 0 = 53 to rank1
5779 22:58:34.754005 Final RX Vref Byte 1 = 52 to rank1==
5780 22:58:34.757340 Dram Type= 6, Freq= 0, CH_1, rank 0
5781 22:58:34.763777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5782 22:58:34.763861 ==
5783 22:58:34.763947 DQS Delay:
5784 22:58:34.767330 DQS0 = 0, DQS1 = 0
5785 22:58:34.767412 DQM Delay:
5786 22:58:34.767476 DQM0 = 104, DQM1 = 97
5787 22:58:34.770400 DQ Delay:
5788 22:58:34.773960 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5789 22:58:34.777369 DQ4 =102, DQ5 =112, DQ6 =114, DQ7 =102
5790 22:58:34.780701 DQ8 =86, DQ9 =84, DQ10 =100, DQ11 =92
5791 22:58:34.783662 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =102
5792 22:58:34.783757
5793 22:58:34.783875
5794 22:58:34.793445 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b33, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 413 ps
5795 22:58:34.793562 CH1 RK0: MR19=505, MR18=1B33
5796 22:58:34.800203 CH1_RK0: MR19=0x505, MR18=0x1B33, DQSOSC=405, MR23=63, INC=66, DEC=44
5797 22:58:34.800288
5798 22:58:34.803576 ----->DramcWriteLeveling(PI) begin...
5799 22:58:34.803660 ==
5800 22:58:34.806680 Dram Type= 6, Freq= 0, CH_1, rank 1
5801 22:58:34.813542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5802 22:58:34.813627 ==
5803 22:58:34.816978 Write leveling (Byte 0): 27 => 27
5804 22:58:34.817089 Write leveling (Byte 1): 28 => 28
5805 22:58:34.820288 DramcWriteLeveling(PI) end<-----
5806 22:58:34.820386
5807 22:58:34.820476 ==
5808 22:58:34.823578 Dram Type= 6, Freq= 0, CH_1, rank 1
5809 22:58:34.830303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5810 22:58:34.830415 ==
5811 22:58:34.833673 [Gating] SW mode calibration
5812 22:58:34.839955 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5813 22:58:34.843241 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5814 22:58:34.849956 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5815 22:58:34.853170 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5816 22:58:34.856555 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5817 22:58:34.863425 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5818 22:58:34.866676 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5819 22:58:34.869912 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5820 22:58:34.876332 0 14 24 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 0)
5821 22:58:34.879561 0 14 28 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 1)
5822 22:58:34.882991 0 15 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5823 22:58:34.889295 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5824 22:58:34.892615 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5825 22:58:34.896079 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5826 22:58:34.902943 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5827 22:58:34.905965 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5828 22:58:34.909076 0 15 24 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
5829 22:58:34.915816 0 15 28 | B1->B0 | 4444 4444 | 0 0 | (0 0) (1 1)
5830 22:58:34.919252 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5831 22:58:34.922611 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 22:58:34.928732 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5833 22:58:34.932543 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5834 22:58:34.935297 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5835 22:58:34.942383 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5836 22:58:34.945287 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5837 22:58:34.948793 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5838 22:58:34.955599 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 22:58:34.959044 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 22:58:34.962047 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 22:58:34.968693 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 22:58:34.972184 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 22:58:34.975538 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 22:58:34.982076 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 22:58:34.985184 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 22:58:34.988283 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 22:58:34.995149 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 22:58:34.998612 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 22:58:35.001641 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 22:58:35.008134 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 22:58:35.011787 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 22:58:35.014918 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5853 22:58:35.021665 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5854 22:58:35.024561 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5855 22:58:35.027981 Total UI for P1: 0, mck2ui 16
5856 22:58:35.031301 best dqsien dly found for B0: ( 1, 2, 28)
5857 22:58:35.034702 Total UI for P1: 0, mck2ui 16
5858 22:58:35.038084 best dqsien dly found for B1: ( 1, 2, 26)
5859 22:58:35.041347 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5860 22:58:35.044633 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5861 22:58:35.044731
5862 22:58:35.048013 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5863 22:58:35.051284 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5864 22:58:35.054568 [Gating] SW calibration Done
5865 22:58:35.054650 ==
5866 22:58:35.058065 Dram Type= 6, Freq= 0, CH_1, rank 1
5867 22:58:35.061402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5868 22:58:35.061486 ==
5869 22:58:35.064732 RX Vref Scan: 0
5870 22:58:35.064834
5871 22:58:35.067676 RX Vref 0 -> 0, step: 1
5872 22:58:35.067758
5873 22:58:35.067822 RX Delay -80 -> 252, step: 8
5874 22:58:35.074504 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5875 22:58:35.077998 iDelay=208, Bit 1, Center 99 (16 ~ 183) 168
5876 22:58:35.081373 iDelay=208, Bit 2, Center 87 (0 ~ 175) 176
5877 22:58:35.084629 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5878 22:58:35.087995 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5879 22:58:35.094513 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5880 22:58:35.097861 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5881 22:58:35.101206 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5882 22:58:35.104622 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5883 22:58:35.108045 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5884 22:58:35.110978 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5885 22:58:35.117569 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5886 22:58:35.121005 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5887 22:58:35.124364 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5888 22:58:35.127408 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5889 22:58:35.134013 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5890 22:58:35.134097 ==
5891 22:58:35.137603 Dram Type= 6, Freq= 0, CH_1, rank 1
5892 22:58:35.141050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5893 22:58:35.141134 ==
5894 22:58:35.141200 DQS Delay:
5895 22:58:35.144403 DQS0 = 0, DQS1 = 0
5896 22:58:35.144485 DQM Delay:
5897 22:58:35.147703 DQM0 = 103, DQM1 = 95
5898 22:58:35.147787 DQ Delay:
5899 22:58:35.150949 DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =103
5900 22:58:35.153874 DQ4 =103, DQ5 =115, DQ6 =111, DQ7 =103
5901 22:58:35.157616 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5902 22:58:35.160518 DQ12 =107, DQ13 =103, DQ14 =99, DQ15 =107
5903 22:58:35.160601
5904 22:58:35.160667
5905 22:58:35.160728 ==
5906 22:58:35.163842 Dram Type= 6, Freq= 0, CH_1, rank 1
5907 22:58:35.170822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5908 22:58:35.170906 ==
5909 22:58:35.170973
5910 22:58:35.171034
5911 22:58:35.171092 TX Vref Scan disable
5912 22:58:35.173841 == TX Byte 0 ==
5913 22:58:35.177222 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5914 22:58:35.180568 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5915 22:58:35.184014 == TX Byte 1 ==
5916 22:58:35.187405 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5917 22:58:35.190555 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5918 22:58:35.193625 ==
5919 22:58:35.197180 Dram Type= 6, Freq= 0, CH_1, rank 1
5920 22:58:35.200412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5921 22:58:35.200494 ==
5922 22:58:35.200558
5923 22:58:35.200618
5924 22:58:35.203761 TX Vref Scan disable
5925 22:58:35.203842 == TX Byte 0 ==
5926 22:58:35.210579 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5927 22:58:35.213904 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5928 22:58:35.213987 == TX Byte 1 ==
5929 22:58:35.220367 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5930 22:58:35.223522 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5931 22:58:35.223604
5932 22:58:35.223669 [DATLAT]
5933 22:58:35.226866 Freq=933, CH1 RK1
5934 22:58:35.226947
5935 22:58:35.227012 DATLAT Default: 0xb
5936 22:58:35.230291 0, 0xFFFF, sum = 0
5937 22:58:35.230415 1, 0xFFFF, sum = 0
5938 22:58:35.233597 2, 0xFFFF, sum = 0
5939 22:58:35.233709 3, 0xFFFF, sum = 0
5940 22:58:35.237031 4, 0xFFFF, sum = 0
5941 22:58:35.237114 5, 0xFFFF, sum = 0
5942 22:58:35.240269 6, 0xFFFF, sum = 0
5943 22:58:35.243536 7, 0xFFFF, sum = 0
5944 22:58:35.243621 8, 0xFFFF, sum = 0
5945 22:58:35.246940 9, 0xFFFF, sum = 0
5946 22:58:35.247025 10, 0x0, sum = 1
5947 22:58:35.250231 11, 0x0, sum = 2
5948 22:58:35.250331 12, 0x0, sum = 3
5949 22:58:35.250425 13, 0x0, sum = 4
5950 22:58:35.253442 best_step = 11
5951 22:58:35.253525
5952 22:58:35.253591 ==
5953 22:58:35.256948 Dram Type= 6, Freq= 0, CH_1, rank 1
5954 22:58:35.260148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5955 22:58:35.260246 ==
5956 22:58:35.263496 RX Vref Scan: 0
5957 22:58:35.263620
5958 22:58:35.263700 RX Vref 0 -> 0, step: 1
5959 22:58:35.267034
5960 22:58:35.267144 RX Delay -53 -> 252, step: 4
5961 22:58:35.274227 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5962 22:58:35.277625 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5963 22:58:35.280530 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5964 22:58:35.284154 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5965 22:58:35.287464 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5966 22:58:35.294192 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5967 22:58:35.297282 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5968 22:58:35.300631 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5969 22:58:35.303705 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5970 22:58:35.307540 iDelay=199, Bit 9, Center 90 (7 ~ 174) 168
5971 22:58:35.313941 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5972 22:58:35.316873 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5973 22:58:35.320266 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5974 22:58:35.323623 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5975 22:58:35.326840 iDelay=199, Bit 14, Center 106 (19 ~ 194) 176
5976 22:58:35.333500 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5977 22:58:35.333586 ==
5978 22:58:35.337086 Dram Type= 6, Freq= 0, CH_1, rank 1
5979 22:58:35.339953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5980 22:58:35.340039 ==
5981 22:58:35.340106 DQS Delay:
5982 22:58:35.343234 DQS0 = 0, DQS1 = 0
5983 22:58:35.343318 DQM Delay:
5984 22:58:35.346586 DQM0 = 104, DQM1 = 98
5985 22:58:35.346670 DQ Delay:
5986 22:58:35.350087 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =102
5987 22:58:35.353329 DQ4 =106, DQ5 =116, DQ6 =112, DQ7 =102
5988 22:58:35.356448 DQ8 =84, DQ9 =90, DQ10 =98, DQ11 =92
5989 22:58:35.359785 DQ12 =106, DQ13 =104, DQ14 =106, DQ15 =106
5990 22:58:35.359869
5991 22:58:35.359935
5992 22:58:35.370214 [DQSOSCAuto] RK1, (LSB)MR18= 0x20fd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 411 ps
5993 22:58:35.373134 CH1 RK1: MR19=504, MR18=20FD
5994 22:58:35.376506 CH1_RK1: MR19=0x504, MR18=0x20FD, DQSOSC=411, MR23=63, INC=64, DEC=42
5995 22:58:35.379967 [RxdqsGatingPostProcess] freq 933
5996 22:58:35.386446 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5997 22:58:35.389479 best DQS0 dly(2T, 0.5T) = (0, 10)
5998 22:58:35.392879 best DQS1 dly(2T, 0.5T) = (0, 10)
5999 22:58:35.396352 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6000 22:58:35.399684 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6001 22:58:35.403053 best DQS0 dly(2T, 0.5T) = (0, 10)
6002 22:58:35.406180 best DQS1 dly(2T, 0.5T) = (0, 10)
6003 22:58:35.409750 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6004 22:58:35.412931 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6005 22:58:35.416400 Pre-setting of DQS Precalculation
6006 22:58:35.419793 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6007 22:58:35.426045 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6008 22:58:35.432668 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6009 22:58:35.432788
6010 22:58:35.436137
6011 22:58:35.436250 [Calibration Summary] 1866 Mbps
6012 22:58:35.439473 CH 0, Rank 0
6013 22:58:35.439585 SW Impedance : PASS
6014 22:58:35.442579 DUTY Scan : NO K
6015 22:58:35.446196 ZQ Calibration : PASS
6016 22:58:35.446299 Jitter Meter : NO K
6017 22:58:35.449457 CBT Training : PASS
6018 22:58:35.452451 Write leveling : PASS
6019 22:58:35.452555 RX DQS gating : PASS
6020 22:58:35.455910 RX DQ/DQS(RDDQC) : PASS
6021 22:58:35.459156 TX DQ/DQS : PASS
6022 22:58:35.459263 RX DATLAT : PASS
6023 22:58:35.462499 RX DQ/DQS(Engine): PASS
6024 22:58:35.466112 TX OE : NO K
6025 22:58:35.466241 All Pass.
6026 22:58:35.466354
6027 22:58:35.466502 CH 0, Rank 1
6028 22:58:35.469195 SW Impedance : PASS
6029 22:58:35.472468 DUTY Scan : NO K
6030 22:58:35.472589 ZQ Calibration : PASS
6031 22:58:35.475966 Jitter Meter : NO K
6032 22:58:35.476039 CBT Training : PASS
6033 22:58:35.479482 Write leveling : PASS
6034 22:58:35.482537 RX DQS gating : PASS
6035 22:58:35.482639 RX DQ/DQS(RDDQC) : PASS
6036 22:58:35.485946 TX DQ/DQS : PASS
6037 22:58:35.489477 RX DATLAT : PASS
6038 22:58:35.489577 RX DQ/DQS(Engine): PASS
6039 22:58:35.492870 TX OE : NO K
6040 22:58:35.492986 All Pass.
6041 22:58:35.493130
6042 22:58:35.495677 CH 1, Rank 0
6043 22:58:35.495780 SW Impedance : PASS
6044 22:58:35.499166 DUTY Scan : NO K
6045 22:58:35.502625 ZQ Calibration : PASS
6046 22:58:35.502726 Jitter Meter : NO K
6047 22:58:35.506001 CBT Training : PASS
6048 22:58:35.509004 Write leveling : PASS
6049 22:58:35.509104 RX DQS gating : PASS
6050 22:58:35.512431 RX DQ/DQS(RDDQC) : PASS
6051 22:58:35.515610 TX DQ/DQS : PASS
6052 22:58:35.515702 RX DATLAT : PASS
6053 22:58:35.518944 RX DQ/DQS(Engine): PASS
6054 22:58:35.522200 TX OE : NO K
6055 22:58:35.522307 All Pass.
6056 22:58:35.522402
6057 22:58:35.522495 CH 1, Rank 1
6058 22:58:35.525762 SW Impedance : PASS
6059 22:58:35.529150 DUTY Scan : NO K
6060 22:58:35.529250 ZQ Calibration : PASS
6061 22:58:35.532151 Jitter Meter : NO K
6062 22:58:35.535556 CBT Training : PASS
6063 22:58:35.535662 Write leveling : PASS
6064 22:58:35.538756 RX DQS gating : PASS
6065 22:58:35.538862 RX DQ/DQS(RDDQC) : PASS
6066 22:58:35.542113 TX DQ/DQS : PASS
6067 22:58:35.545160 RX DATLAT : PASS
6068 22:58:35.545264 RX DQ/DQS(Engine): PASS
6069 22:58:35.548476 TX OE : NO K
6070 22:58:35.548576 All Pass.
6071 22:58:35.548670
6072 22:58:35.551712 DramC Write-DBI off
6073 22:58:35.554940 PER_BANK_REFRESH: Hybrid Mode
6074 22:58:35.555041 TX_TRACKING: ON
6075 22:58:35.565318 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6076 22:58:35.568234 [FAST_K] Save calibration result to emmc
6077 22:58:35.571968 dramc_set_vcore_voltage set vcore to 650000
6078 22:58:35.574804 Read voltage for 400, 6
6079 22:58:35.574909 Vio18 = 0
6080 22:58:35.578489 Vcore = 650000
6081 22:58:35.578589 Vdram = 0
6082 22:58:35.578679 Vddq = 0
6083 22:58:35.578774 Vmddr = 0
6084 22:58:35.584809 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6085 22:58:35.591574 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6086 22:58:35.591679 MEM_TYPE=3, freq_sel=20
6087 22:58:35.595005 sv_algorithm_assistance_LP4_800
6088 22:58:35.598032 ============ PULL DRAM RESETB DOWN ============
6089 22:58:35.604945 ========== PULL DRAM RESETB DOWN end =========
6090 22:58:35.608263 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6091 22:58:35.611678 ===================================
6092 22:58:35.614695 LPDDR4 DRAM CONFIGURATION
6093 22:58:35.618118 ===================================
6094 22:58:35.618229 EX_ROW_EN[0] = 0x0
6095 22:58:35.621339 EX_ROW_EN[1] = 0x0
6096 22:58:35.621439 LP4Y_EN = 0x0
6097 22:58:35.624616 WORK_FSP = 0x0
6098 22:58:35.624715 WL = 0x2
6099 22:58:35.627750 RL = 0x2
6100 22:58:35.631448 BL = 0x2
6101 22:58:35.631569 RPST = 0x0
6102 22:58:35.634490 RD_PRE = 0x0
6103 22:58:35.634591 WR_PRE = 0x1
6104 22:58:35.637814 WR_PST = 0x0
6105 22:58:35.637920 DBI_WR = 0x0
6106 22:58:35.641064 DBI_RD = 0x0
6107 22:58:35.641299 OTF = 0x1
6108 22:58:35.644540 ===================================
6109 22:58:35.647456 ===================================
6110 22:58:35.650970 ANA top config
6111 22:58:35.654400 ===================================
6112 22:58:35.654489 DLL_ASYNC_EN = 0
6113 22:58:35.657475 ALL_SLAVE_EN = 1
6114 22:58:35.660888 NEW_RANK_MODE = 1
6115 22:58:35.664312 DLL_IDLE_MODE = 1
6116 22:58:35.664450 LP45_APHY_COMB_EN = 1
6117 22:58:35.667465 TX_ODT_DIS = 1
6118 22:58:35.670799 NEW_8X_MODE = 1
6119 22:58:35.674127 ===================================
6120 22:58:35.677409 ===================================
6121 22:58:35.680641 data_rate = 800
6122 22:58:35.684330 CKR = 1
6123 22:58:35.687774 DQ_P2S_RATIO = 4
6124 22:58:35.690702 ===================================
6125 22:58:35.690784 CA_P2S_RATIO = 4
6126 22:58:35.694197 DQ_CA_OPEN = 0
6127 22:58:35.697144 DQ_SEMI_OPEN = 1
6128 22:58:35.700510 CA_SEMI_OPEN = 1
6129 22:58:35.703978 CA_FULL_RATE = 0
6130 22:58:35.707006 DQ_CKDIV4_EN = 0
6131 22:58:35.707089 CA_CKDIV4_EN = 1
6132 22:58:35.710446 CA_PREDIV_EN = 0
6133 22:58:35.713680 PH8_DLY = 0
6134 22:58:35.717188 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6135 22:58:35.720490 DQ_AAMCK_DIV = 0
6136 22:58:35.723838 CA_AAMCK_DIV = 0
6137 22:58:35.723922 CA_ADMCK_DIV = 4
6138 22:58:35.727187 DQ_TRACK_CA_EN = 0
6139 22:58:35.730540 CA_PICK = 800
6140 22:58:35.733358 CA_MCKIO = 400
6141 22:58:35.736938 MCKIO_SEMI = 400
6142 22:58:35.740181 PLL_FREQ = 3016
6143 22:58:35.743484 DQ_UI_PI_RATIO = 32
6144 22:58:35.746792 CA_UI_PI_RATIO = 32
6145 22:58:35.750050 ===================================
6146 22:58:35.753409 ===================================
6147 22:58:35.753506 memory_type:LPDDR4
6148 22:58:35.756950 GP_NUM : 10
6149 22:58:35.757132 SRAM_EN : 1
6150 22:58:35.760267 MD32_EN : 0
6151 22:58:35.763478 ===================================
6152 22:58:35.766953 [ANA_INIT] >>>>>>>>>>>>>>
6153 22:58:35.770298 <<<<<< [CONFIGURE PHASE]: ANA_TX
6154 22:58:35.773525 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6155 22:58:35.777049 ===================================
6156 22:58:35.777136 data_rate = 800,PCW = 0X7400
6157 22:58:35.780333 ===================================
6158 22:58:35.783618 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6159 22:58:35.790276 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6160 22:58:35.803437 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6161 22:58:35.806408 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6162 22:58:35.809767 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6163 22:58:35.813160 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6164 22:58:35.816591 [ANA_INIT] flow start
6165 22:58:35.816697 [ANA_INIT] PLL >>>>>>>>
6166 22:58:35.819527 [ANA_INIT] PLL <<<<<<<<
6167 22:58:35.822944 [ANA_INIT] MIDPI >>>>>>>>
6168 22:58:35.826306 [ANA_INIT] MIDPI <<<<<<<<
6169 22:58:35.826385 [ANA_INIT] DLL >>>>>>>>
6170 22:58:35.829583 [ANA_INIT] flow end
6171 22:58:35.832933 ============ LP4 DIFF to SE enter ============
6172 22:58:35.836286 ============ LP4 DIFF to SE exit ============
6173 22:58:35.839616 [ANA_INIT] <<<<<<<<<<<<<
6174 22:58:35.842827 [Flow] Enable top DCM control >>>>>
6175 22:58:35.846100 [Flow] Enable top DCM control <<<<<
6176 22:58:35.849258 Enable DLL master slave shuffle
6177 22:58:35.855987 ==============================================================
6178 22:58:35.856113 Gating Mode config
6179 22:58:35.862602 ==============================================================
6180 22:58:35.862722 Config description:
6181 22:58:35.872243 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6182 22:58:35.879102 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6183 22:58:35.885591 SELPH_MODE 0: By rank 1: By Phase
6184 22:58:35.888861 ==============================================================
6185 22:58:35.892198 GAT_TRACK_EN = 0
6186 22:58:35.895571 RX_GATING_MODE = 2
6187 22:58:35.898513 RX_GATING_TRACK_MODE = 2
6188 22:58:35.902139 SELPH_MODE = 1
6189 22:58:35.905463 PICG_EARLY_EN = 1
6190 22:58:35.908845 VALID_LAT_VALUE = 1
6191 22:58:35.915247 ==============================================================
6192 22:58:35.918633 Enter into Gating configuration >>>>
6193 22:58:35.922168 Exit from Gating configuration <<<<
6194 22:58:35.925046 Enter into DVFS_PRE_config >>>>>
6195 22:58:35.935197 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6196 22:58:35.938549 Exit from DVFS_PRE_config <<<<<
6197 22:58:35.941548 Enter into PICG configuration >>>>
6198 22:58:35.944940 Exit from PICG configuration <<<<
6199 22:58:35.948204 [RX_INPUT] configuration >>>>>
6200 22:58:35.948294 [RX_INPUT] configuration <<<<<
6201 22:58:35.954845 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6202 22:58:35.961327 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6203 22:58:35.968208 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6204 22:58:35.971554 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6205 22:58:35.978163 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6206 22:58:35.984668 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6207 22:58:35.988019 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6208 22:58:35.991527 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6209 22:58:35.998199 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6210 22:58:36.001189 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6211 22:58:36.004576 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6212 22:58:36.011415 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6213 22:58:36.014278 ===================================
6214 22:58:36.014390 LPDDR4 DRAM CONFIGURATION
6215 22:58:36.018077 ===================================
6216 22:58:36.020964 EX_ROW_EN[0] = 0x0
6217 22:58:36.024447 EX_ROW_EN[1] = 0x0
6218 22:58:36.024556 LP4Y_EN = 0x0
6219 22:58:36.027822 WORK_FSP = 0x0
6220 22:58:36.027928 WL = 0x2
6221 22:58:36.031248 RL = 0x2
6222 22:58:36.031351 BL = 0x2
6223 22:58:36.034676 RPST = 0x0
6224 22:58:36.034783 RD_PRE = 0x0
6225 22:58:36.037612 WR_PRE = 0x1
6226 22:58:36.037717 WR_PST = 0x0
6227 22:58:36.040844 DBI_WR = 0x0
6228 22:58:36.040949 DBI_RD = 0x0
6229 22:58:36.044150 OTF = 0x1
6230 22:58:36.047425 ===================================
6231 22:58:36.050823 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6232 22:58:36.054181 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6233 22:58:36.060677 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6234 22:58:36.064423 ===================================
6235 22:58:36.064537 LPDDR4 DRAM CONFIGURATION
6236 22:58:36.067521 ===================================
6237 22:58:36.070740 EX_ROW_EN[0] = 0x10
6238 22:58:36.074185 EX_ROW_EN[1] = 0x0
6239 22:58:36.074307 LP4Y_EN = 0x0
6240 22:58:36.077217 WORK_FSP = 0x0
6241 22:58:36.077325 WL = 0x2
6242 22:58:36.080574 RL = 0x2
6243 22:58:36.080683 BL = 0x2
6244 22:58:36.084005 RPST = 0x0
6245 22:58:36.084112 RD_PRE = 0x0
6246 22:58:36.087383 WR_PRE = 0x1
6247 22:58:36.087489 WR_PST = 0x0
6248 22:58:36.090490 DBI_WR = 0x0
6249 22:58:36.090597 DBI_RD = 0x0
6250 22:58:36.093867 OTF = 0x1
6251 22:58:36.097321 ===================================
6252 22:58:36.103762 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6253 22:58:36.107290 nWR fixed to 30
6254 22:58:36.107400 [ModeRegInit_LP4] CH0 RK0
6255 22:58:36.110116 [ModeRegInit_LP4] CH0 RK1
6256 22:58:36.114057 [ModeRegInit_LP4] CH1 RK0
6257 22:58:36.116994 [ModeRegInit_LP4] CH1 RK1
6258 22:58:36.117102 match AC timing 19
6259 22:58:36.123612 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6260 22:58:36.126992 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6261 22:58:36.130500 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6262 22:58:36.136924 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6263 22:58:36.140367 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6264 22:58:36.140475 ==
6265 22:58:36.143655 Dram Type= 6, Freq= 0, CH_0, rank 0
6266 22:58:36.147077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6267 22:58:36.147186 ==
6268 22:58:36.153383 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6269 22:58:36.159935 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6270 22:58:36.163244 [CA 0] Center 36 (8~64) winsize 57
6271 22:58:36.166579 [CA 1] Center 36 (8~64) winsize 57
6272 22:58:36.166687 [CA 2] Center 36 (8~64) winsize 57
6273 22:58:36.169844 [CA 3] Center 36 (8~64) winsize 57
6274 22:58:36.173247 [CA 4] Center 36 (8~64) winsize 57
6275 22:58:36.176522 [CA 5] Center 36 (8~64) winsize 57
6276 22:58:36.176633
6277 22:58:36.179714 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6278 22:58:36.179818
6279 22:58:36.186683 [CATrainingPosCal] consider 1 rank data
6280 22:58:36.186799 u2DelayCellTimex100 = 270/100 ps
6281 22:58:36.193146 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 22:58:36.196291 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 22:58:36.199797 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 22:58:36.203027 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 22:58:36.206512 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 22:58:36.209381 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 22:58:36.209484
6288 22:58:36.212842 CA PerBit enable=1, Macro0, CA PI delay=36
6289 22:58:36.212946
6290 22:58:36.216274 [CBTSetCACLKResult] CA Dly = 36
6291 22:58:36.219552 CS Dly: 1 (0~32)
6292 22:58:36.219657 ==
6293 22:58:36.222973 Dram Type= 6, Freq= 0, CH_0, rank 1
6294 22:58:36.225890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6295 22:58:36.226001 ==
6296 22:58:36.232816 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6297 22:58:36.235837 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6298 22:58:36.239415 [CA 0] Center 36 (8~64) winsize 57
6299 22:58:36.242361 [CA 1] Center 36 (8~64) winsize 57
6300 22:58:36.245698 [CA 2] Center 36 (8~64) winsize 57
6301 22:58:36.249490 [CA 3] Center 36 (8~64) winsize 57
6302 22:58:36.252502 [CA 4] Center 36 (8~64) winsize 57
6303 22:58:36.256059 [CA 5] Center 36 (8~64) winsize 57
6304 22:58:36.256166
6305 22:58:36.259345 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6306 22:58:36.259460
6307 22:58:36.262268 [CATrainingPosCal] consider 2 rank data
6308 22:58:36.265642 u2DelayCellTimex100 = 270/100 ps
6309 22:58:36.269029 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 22:58:36.272301 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 22:58:36.278930 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 22:58:36.282390 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 22:58:36.285666 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 22:58:36.288892 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6315 22:58:36.289008
6316 22:58:36.292083 CA PerBit enable=1, Macro0, CA PI delay=36
6317 22:58:36.292200
6318 22:58:36.295310 [CBTSetCACLKResult] CA Dly = 36
6319 22:58:36.295424 CS Dly: 1 (0~32)
6320 22:58:36.298688
6321 22:58:36.301855 ----->DramcWriteLeveling(PI) begin...
6322 22:58:36.301964 ==
6323 22:58:36.305195 Dram Type= 6, Freq= 0, CH_0, rank 0
6324 22:58:36.308479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6325 22:58:36.308603 ==
6326 22:58:36.311995 Write leveling (Byte 0): 40 => 8
6327 22:58:36.315437 Write leveling (Byte 1): 32 => 0
6328 22:58:36.318377 DramcWriteLeveling(PI) end<-----
6329 22:58:36.318485
6330 22:58:36.318597 ==
6331 22:58:36.322154 Dram Type= 6, Freq= 0, CH_0, rank 0
6332 22:58:36.325127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 22:58:36.325235 ==
6334 22:58:36.328462 [Gating] SW mode calibration
6335 22:58:36.335311 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6336 22:58:36.341743 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6337 22:58:36.345156 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6338 22:58:36.348517 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6339 22:58:36.355040 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6340 22:58:36.358470 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6341 22:58:36.361885 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6342 22:58:36.368164 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6343 22:58:36.371477 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6344 22:58:36.374902 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6345 22:58:36.378192 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6346 22:58:36.381525 Total UI for P1: 0, mck2ui 16
6347 22:58:36.384895 best dqsien dly found for B0: ( 0, 14, 24)
6348 22:58:36.388353 Total UI for P1: 0, mck2ui 16
6349 22:58:36.391571 best dqsien dly found for B1: ( 0, 14, 24)
6350 22:58:36.394699 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6351 22:58:36.401429 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6352 22:58:36.401507
6353 22:58:36.404670 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6354 22:58:36.408181 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6355 22:58:36.411247 [Gating] SW calibration Done
6356 22:58:36.411346 ==
6357 22:58:36.414518 Dram Type= 6, Freq= 0, CH_0, rank 0
6358 22:58:36.417925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6359 22:58:36.418000 ==
6360 22:58:36.421463 RX Vref Scan: 0
6361 22:58:36.421540
6362 22:58:36.421623 RX Vref 0 -> 0, step: 1
6363 22:58:36.421726
6364 22:58:36.424889 RX Delay -410 -> 252, step: 16
6365 22:58:36.428220 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6366 22:58:36.434571 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6367 22:58:36.438072 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6368 22:58:36.441434 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6369 22:58:36.444876 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6370 22:58:36.451232 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6371 22:58:36.454576 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6372 22:58:36.457736 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6373 22:58:36.461189 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6374 22:58:36.467779 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6375 22:58:36.470886 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6376 22:58:36.474302 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6377 22:58:36.477763 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6378 22:58:36.484300 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6379 22:58:36.487714 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6380 22:58:36.491031 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6381 22:58:36.491135 ==
6382 22:58:36.494353 Dram Type= 6, Freq= 0, CH_0, rank 0
6383 22:58:36.500742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6384 22:58:36.500860 ==
6385 22:58:36.500957 DQS Delay:
6386 22:58:36.504173 DQS0 = 19, DQS1 = 43
6387 22:58:36.504277 DQM Delay:
6388 22:58:36.504371 DQM0 = 6, DQM1 = 15
6389 22:58:36.507629 DQ Delay:
6390 22:58:36.510899 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6391 22:58:36.511001 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6392 22:58:36.514072 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6393 22:58:36.517417 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6394 22:58:36.517513
6395 22:58:36.520870
6396 22:58:36.520964 ==
6397 22:58:36.523978 Dram Type= 6, Freq= 0, CH_0, rank 0
6398 22:58:36.527450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6399 22:58:36.527556 ==
6400 22:58:36.527651
6401 22:58:36.527739
6402 22:58:36.530899 TX Vref Scan disable
6403 22:58:36.530997 == TX Byte 0 ==
6404 22:58:36.533783 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6405 22:58:36.540669 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6406 22:58:36.540796 == TX Byte 1 ==
6407 22:58:36.544020 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6408 22:58:36.550435 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6409 22:58:36.550518 ==
6410 22:58:36.553878 Dram Type= 6, Freq= 0, CH_0, rank 0
6411 22:58:36.557338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6412 22:58:36.557420 ==
6413 22:58:36.557484
6414 22:58:36.557543
6415 22:58:36.560237 TX Vref Scan disable
6416 22:58:36.560318 == TX Byte 0 ==
6417 22:58:36.566963 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6418 22:58:36.570249 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6419 22:58:36.570333 == TX Byte 1 ==
6420 22:58:36.576980 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6421 22:58:36.580465 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6422 22:58:36.580546
6423 22:58:36.580610 [DATLAT]
6424 22:58:36.583881 Freq=400, CH0 RK0
6425 22:58:36.583963
6426 22:58:36.584027 DATLAT Default: 0xf
6427 22:58:36.587071 0, 0xFFFF, sum = 0
6428 22:58:36.587154 1, 0xFFFF, sum = 0
6429 22:58:36.589966 2, 0xFFFF, sum = 0
6430 22:58:36.590048 3, 0xFFFF, sum = 0
6431 22:58:36.593424 4, 0xFFFF, sum = 0
6432 22:58:36.593568 5, 0xFFFF, sum = 0
6433 22:58:36.596742 6, 0xFFFF, sum = 0
6434 22:58:36.596866 7, 0xFFFF, sum = 0
6435 22:58:36.600121 8, 0xFFFF, sum = 0
6436 22:58:36.600204 9, 0xFFFF, sum = 0
6437 22:58:36.603381 10, 0xFFFF, sum = 0
6438 22:58:36.606579 11, 0xFFFF, sum = 0
6439 22:58:36.606661 12, 0xFFFF, sum = 0
6440 22:58:36.610015 13, 0x0, sum = 1
6441 22:58:36.610097 14, 0x0, sum = 2
6442 22:58:36.610163 15, 0x0, sum = 3
6443 22:58:36.613100 16, 0x0, sum = 4
6444 22:58:36.613182 best_step = 14
6445 22:58:36.613247
6446 22:58:36.616653 ==
6447 22:58:36.616771 Dram Type= 6, Freq= 0, CH_0, rank 0
6448 22:58:36.623308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6449 22:58:36.623391 ==
6450 22:58:36.623456 RX Vref Scan: 1
6451 22:58:36.623549
6452 22:58:36.626343 RX Vref 0 -> 0, step: 1
6453 22:58:36.626453
6454 22:58:36.629972 RX Delay -327 -> 252, step: 8
6455 22:58:36.630057
6456 22:58:36.633138 Set Vref, RX VrefLevel [Byte0]: 59
6457 22:58:36.636439 [Byte1]: 50
6458 22:58:36.639871
6459 22:58:36.639943 Final RX Vref Byte 0 = 59 to rank0
6460 22:58:36.643448 Final RX Vref Byte 1 = 50 to rank0
6461 22:58:36.646535 Final RX Vref Byte 0 = 59 to rank1
6462 22:58:36.649922 Final RX Vref Byte 1 = 50 to rank1==
6463 22:58:36.653474 Dram Type= 6, Freq= 0, CH_0, rank 0
6464 22:58:36.659922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6465 22:58:36.659997 ==
6466 22:58:36.660061 DQS Delay:
6467 22:58:36.663343 DQS0 = 28, DQS1 = 48
6468 22:58:36.663418 DQM Delay:
6469 22:58:36.663499 DQM0 = 11, DQM1 = 16
6470 22:58:36.666544 DQ Delay:
6471 22:58:36.669454 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6472 22:58:36.669526 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6473 22:58:36.672856 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6474 22:58:36.676147 DQ12 =24, DQ13 =16, DQ14 =28, DQ15 =24
6475 22:58:36.679574
6476 22:58:36.679654
6477 22:58:36.686474 [DQSOSCAuto] RK0, (LSB)MR18= 0xaca4, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6478 22:58:36.689426 CH0 RK0: MR19=C0C, MR18=ACA4
6479 22:58:36.696157 CH0_RK0: MR19=0xC0C, MR18=0xACA4, DQSOSC=388, MR23=63, INC=392, DEC=261
6480 22:58:36.696299 ==
6481 22:58:36.699650 Dram Type= 6, Freq= 0, CH_0, rank 1
6482 22:58:36.703089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6483 22:58:36.703173 ==
6484 22:58:36.706438 [Gating] SW mode calibration
6485 22:58:36.712975 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6486 22:58:36.719543 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6487 22:58:36.722936 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6488 22:58:36.726416 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6489 22:58:36.732994 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6490 22:58:36.736273 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6491 22:58:36.739477 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6492 22:58:36.746002 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6493 22:58:36.749148 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6494 22:58:36.752532 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6495 22:58:36.756136 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6496 22:58:36.759547 Total UI for P1: 0, mck2ui 16
6497 22:58:36.762484 best dqsien dly found for B0: ( 0, 14, 24)
6498 22:58:36.766190 Total UI for P1: 0, mck2ui 16
6499 22:58:36.769016 best dqsien dly found for B1: ( 0, 14, 24)
6500 22:58:36.772749 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6501 22:58:36.779031 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6502 22:58:36.779114
6503 22:58:36.782623 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6504 22:58:36.785687 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6505 22:58:36.789233 [Gating] SW calibration Done
6506 22:58:36.789316 ==
6507 22:58:36.792512 Dram Type= 6, Freq= 0, CH_0, rank 1
6508 22:58:36.795743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6509 22:58:36.795827 ==
6510 22:58:36.799199 RX Vref Scan: 0
6511 22:58:36.799312
6512 22:58:36.799410 RX Vref 0 -> 0, step: 1
6513 22:58:36.799531
6514 22:58:36.802468 RX Delay -410 -> 252, step: 16
6515 22:58:36.805934 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6516 22:58:36.812195 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6517 22:58:36.815980 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6518 22:58:36.818833 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6519 22:58:36.822225 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6520 22:58:36.828752 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6521 22:58:36.832326 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6522 22:58:36.835560 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6523 22:58:36.838752 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6524 22:58:36.845643 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6525 22:58:36.848828 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6526 22:58:36.851793 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6527 22:58:36.858578 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6528 22:58:36.862018 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6529 22:58:36.864981 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6530 22:58:36.868443 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6531 22:58:36.868526 ==
6532 22:58:36.871837 Dram Type= 6, Freq= 0, CH_0, rank 1
6533 22:58:36.878416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6534 22:58:36.878501 ==
6535 22:58:36.878567 DQS Delay:
6536 22:58:36.881896 DQS0 = 19, DQS1 = 43
6537 22:58:36.881979 DQM Delay:
6538 22:58:36.885247 DQM0 = 3, DQM1 = 15
6539 22:58:36.885329 DQ Delay:
6540 22:58:36.888141 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6541 22:58:36.891576 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =8
6542 22:58:36.891660 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6543 22:58:36.894950 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6544 22:58:36.898235
6545 22:58:36.898318
6546 22:58:36.898383 ==
6547 22:58:36.901398 Dram Type= 6, Freq= 0, CH_0, rank 1
6548 22:58:36.904786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6549 22:58:36.904869 ==
6550 22:58:36.904936
6551 22:58:36.904996
6552 22:58:36.908223 TX Vref Scan disable
6553 22:58:36.908306 == TX Byte 0 ==
6554 22:58:36.911549 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6555 22:58:36.917850 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6556 22:58:36.917934 == TX Byte 1 ==
6557 22:58:36.921199 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6558 22:58:36.928010 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6559 22:58:36.928093 ==
6560 22:58:36.930983 Dram Type= 6, Freq= 0, CH_0, rank 1
6561 22:58:36.934212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6562 22:58:36.934302 ==
6563 22:58:36.934368
6564 22:58:36.934429
6565 22:58:36.937563 TX Vref Scan disable
6566 22:58:36.937646 == TX Byte 0 ==
6567 22:58:36.943989 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6568 22:58:36.947452 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6569 22:58:36.947535 == TX Byte 1 ==
6570 22:58:36.953932 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6571 22:58:36.957496 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6572 22:58:36.957580
6573 22:58:36.957646 [DATLAT]
6574 22:58:36.961101 Freq=400, CH0 RK1
6575 22:58:36.961185
6576 22:58:36.961250 DATLAT Default: 0xe
6577 22:58:36.964023 0, 0xFFFF, sum = 0
6578 22:58:36.964108 1, 0xFFFF, sum = 0
6579 22:58:36.967464 2, 0xFFFF, sum = 0
6580 22:58:36.967548 3, 0xFFFF, sum = 0
6581 22:58:36.970889 4, 0xFFFF, sum = 0
6582 22:58:36.970974 5, 0xFFFF, sum = 0
6583 22:58:36.973784 6, 0xFFFF, sum = 0
6584 22:58:36.973869 7, 0xFFFF, sum = 0
6585 22:58:36.977090 8, 0xFFFF, sum = 0
6586 22:58:36.977175 9, 0xFFFF, sum = 0
6587 22:58:36.980389 10, 0xFFFF, sum = 0
6588 22:58:36.983746 11, 0xFFFF, sum = 0
6589 22:58:36.983858 12, 0xFFFF, sum = 0
6590 22:58:36.987229 13, 0x0, sum = 1
6591 22:58:36.987313 14, 0x0, sum = 2
6592 22:58:36.987380 15, 0x0, sum = 3
6593 22:58:36.990342 16, 0x0, sum = 4
6594 22:58:36.990426 best_step = 14
6595 22:58:36.990491
6596 22:58:36.993917 ==
6597 22:58:36.993998 Dram Type= 6, Freq= 0, CH_0, rank 1
6598 22:58:37.000665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6599 22:58:37.000749 ==
6600 22:58:37.000839 RX Vref Scan: 0
6601 22:58:37.000901
6602 22:58:37.003878 RX Vref 0 -> 0, step: 1
6603 22:58:37.003959
6604 22:58:37.007161 RX Delay -327 -> 252, step: 8
6605 22:58:37.013962 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6606 22:58:37.016917 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6607 22:58:37.020370 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6608 22:58:37.023595 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6609 22:58:37.030440 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6610 22:58:37.033869 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6611 22:58:37.037051 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6612 22:58:37.040447 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6613 22:58:37.046704 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6614 22:58:37.050391 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6615 22:58:37.053728 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6616 22:58:37.056742 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6617 22:58:37.063585 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6618 22:58:37.066983 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6619 22:58:37.070003 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6620 22:58:37.076577 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6621 22:58:37.076698 ==
6622 22:58:37.079880 Dram Type= 6, Freq= 0, CH_0, rank 1
6623 22:58:37.083143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6624 22:58:37.083250 ==
6625 22:58:37.083344 DQS Delay:
6626 22:58:37.086504 DQS0 = 28, DQS1 = 40
6627 22:58:37.086607 DQM Delay:
6628 22:58:37.089926 DQM0 = 9, DQM1 = 11
6629 22:58:37.090026 DQ Delay:
6630 22:58:37.093154 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6631 22:58:37.096627 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6632 22:58:37.100048 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6633 22:58:37.102948 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6634 22:58:37.103049
6635 22:58:37.103143
6636 22:58:37.109933 [DQSOSCAuto] RK1, (LSB)MR18= 0xb66b, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 387 ps
6637 22:58:37.113121 CH0 RK1: MR19=C0C, MR18=B66B
6638 22:58:37.119443 CH0_RK1: MR19=0xC0C, MR18=0xB66B, DQSOSC=387, MR23=63, INC=394, DEC=262
6639 22:58:37.122870 [RxdqsGatingPostProcess] freq 400
6640 22:58:37.129711 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6641 22:58:37.133063 best DQS0 dly(2T, 0.5T) = (0, 10)
6642 22:58:37.133146 best DQS1 dly(2T, 0.5T) = (0, 10)
6643 22:58:37.135973 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6644 22:58:37.139265 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6645 22:58:37.142911 best DQS0 dly(2T, 0.5T) = (0, 10)
6646 22:58:37.145910 best DQS1 dly(2T, 0.5T) = (0, 10)
6647 22:58:37.149311 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6648 22:58:37.152591 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6649 22:58:37.156126 Pre-setting of DQS Precalculation
6650 22:58:37.162529 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6651 22:58:37.162638 ==
6652 22:58:37.165743 Dram Type= 6, Freq= 0, CH_1, rank 0
6653 22:58:37.169152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6654 22:58:37.169266 ==
6655 22:58:37.175992 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6656 22:58:37.182352 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6657 22:58:37.182459 [CA 0] Center 36 (8~64) winsize 57
6658 22:58:37.185650 [CA 1] Center 36 (8~64) winsize 57
6659 22:58:37.189256 [CA 2] Center 36 (8~64) winsize 57
6660 22:58:37.192259 [CA 3] Center 36 (8~64) winsize 57
6661 22:58:37.195497 [CA 4] Center 36 (8~64) winsize 57
6662 22:58:37.198883 [CA 5] Center 36 (8~64) winsize 57
6663 22:58:37.198990
6664 22:58:37.202304 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6665 22:58:37.202405
6666 22:58:37.205662 [CATrainingPosCal] consider 1 rank data
6667 22:58:37.209050 u2DelayCellTimex100 = 270/100 ps
6668 22:58:37.211928 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 22:58:37.218837 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 22:58:37.222050 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 22:58:37.225538 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 22:58:37.229024 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 22:58:37.232233 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 22:58:37.232341
6675 22:58:37.235077 CA PerBit enable=1, Macro0, CA PI delay=36
6676 22:58:37.235183
6677 22:58:37.238542 [CBTSetCACLKResult] CA Dly = 36
6678 22:58:37.238642 CS Dly: 1 (0~32)
6679 22:58:37.241989 ==
6680 22:58:37.245333 Dram Type= 6, Freq= 0, CH_1, rank 1
6681 22:58:37.248629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6682 22:58:37.248731 ==
6683 22:58:37.251950 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6684 22:58:37.258598 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6685 22:58:37.261638 [CA 0] Center 36 (8~64) winsize 57
6686 22:58:37.264970 [CA 1] Center 36 (8~64) winsize 57
6687 22:58:37.268377 [CA 2] Center 36 (8~64) winsize 57
6688 22:58:37.271564 [CA 3] Center 36 (8~64) winsize 57
6689 22:58:37.274691 [CA 4] Center 36 (8~64) winsize 57
6690 22:58:37.278116 [CA 5] Center 36 (8~64) winsize 57
6691 22:58:37.278225
6692 22:58:37.281519 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6693 22:58:37.281637
6694 22:58:37.284918 [CATrainingPosCal] consider 2 rank data
6695 22:58:37.288263 u2DelayCellTimex100 = 270/100 ps
6696 22:58:37.291426 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 22:58:37.295097 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 22:58:37.298089 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 22:58:37.301332 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 22:58:37.308084 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 22:58:37.311542 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6702 22:58:37.311658
6703 22:58:37.314948 CA PerBit enable=1, Macro0, CA PI delay=36
6704 22:58:37.315050
6705 22:58:37.317840 [CBTSetCACLKResult] CA Dly = 36
6706 22:58:37.317945 CS Dly: 1 (0~32)
6707 22:58:37.318038
6708 22:58:37.321429 ----->DramcWriteLeveling(PI) begin...
6709 22:58:37.321533 ==
6710 22:58:37.324731 Dram Type= 6, Freq= 0, CH_1, rank 0
6711 22:58:37.331607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6712 22:58:37.331711 ==
6713 22:58:37.334441 Write leveling (Byte 0): 40 => 8
6714 22:58:37.337770 Write leveling (Byte 1): 32 => 0
6715 22:58:37.337877 DramcWriteLeveling(PI) end<-----
6716 22:58:37.337972
6717 22:58:37.341163 ==
6718 22:58:37.344643 Dram Type= 6, Freq= 0, CH_1, rank 0
6719 22:58:37.347623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 22:58:37.347743 ==
6721 22:58:37.351295 [Gating] SW mode calibration
6722 22:58:37.357544 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6723 22:58:37.360853 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6724 22:58:37.367735 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6725 22:58:37.371073 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6726 22:58:37.374547 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6727 22:58:37.380950 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6728 22:58:37.384441 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6729 22:58:37.387359 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6730 22:58:37.394454 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6731 22:58:37.397577 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6732 22:58:37.400934 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6733 22:58:37.404456 Total UI for P1: 0, mck2ui 16
6734 22:58:37.407804 best dqsien dly found for B0: ( 0, 14, 24)
6735 22:58:37.411074 Total UI for P1: 0, mck2ui 16
6736 22:58:37.414423 best dqsien dly found for B1: ( 0, 14, 24)
6737 22:58:37.417481 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6738 22:58:37.420795 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6739 22:58:37.420913
6740 22:58:37.427196 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6741 22:58:37.430549 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6742 22:58:37.433919 [Gating] SW calibration Done
6743 22:58:37.434023 ==
6744 22:58:37.437337 Dram Type= 6, Freq= 0, CH_1, rank 0
6745 22:58:37.440587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6746 22:58:37.440689 ==
6747 22:58:37.440790 RX Vref Scan: 0
6748 22:58:37.440924
6749 22:58:37.443918 RX Vref 0 -> 0, step: 1
6750 22:58:37.443988
6751 22:58:37.447216 RX Delay -410 -> 252, step: 16
6752 22:58:37.450578 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6753 22:58:37.457098 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6754 22:58:37.460495 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6755 22:58:37.463771 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6756 22:58:37.466975 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6757 22:58:37.473854 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6758 22:58:37.477258 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6759 22:58:37.480672 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6760 22:58:37.483958 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6761 22:58:37.490194 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6762 22:58:37.493599 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6763 22:58:37.496963 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6764 22:58:37.500169 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6765 22:58:37.506942 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6766 22:58:37.510175 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6767 22:58:37.513591 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6768 22:58:37.513700 ==
6769 22:58:37.516980 Dram Type= 6, Freq= 0, CH_1, rank 0
6770 22:58:37.520336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6771 22:58:37.523719 ==
6772 22:58:37.523818 DQS Delay:
6773 22:58:37.523896 DQS0 = 27, DQS1 = 35
6774 22:58:37.526627 DQM Delay:
6775 22:58:37.526724 DQM0 = 8, DQM1 = 10
6776 22:58:37.530294 DQ Delay:
6777 22:58:37.530399 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6778 22:58:37.533631 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6779 22:58:37.536912 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6780 22:58:37.539898 DQ12 =24, DQ13 =16, DQ14 =8, DQ15 =16
6781 22:58:37.539999
6782 22:58:37.540098
6783 22:58:37.540189 ==
6784 22:58:37.543537 Dram Type= 6, Freq= 0, CH_1, rank 0
6785 22:58:37.549866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6786 22:58:37.549973 ==
6787 22:58:37.550071
6788 22:58:37.550166
6789 22:58:37.550254 TX Vref Scan disable
6790 22:58:37.553361 == TX Byte 0 ==
6791 22:58:37.556711 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6792 22:58:37.559855 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6793 22:58:37.563143 == TX Byte 1 ==
6794 22:58:37.566557 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6795 22:58:37.569816 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6796 22:58:37.573148 ==
6797 22:58:37.576557 Dram Type= 6, Freq= 0, CH_1, rank 0
6798 22:58:37.579440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6799 22:58:37.579548 ==
6800 22:58:37.579645
6801 22:58:37.579735
6802 22:58:37.582832 TX Vref Scan disable
6803 22:58:37.582936 == TX Byte 0 ==
6804 22:58:37.586386 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6805 22:58:37.592995 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6806 22:58:37.593101 == TX Byte 1 ==
6807 22:58:37.596382 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6808 22:58:37.602965 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6809 22:58:37.603070
6810 22:58:37.603166 [DATLAT]
6811 22:58:37.603257 Freq=400, CH1 RK0
6812 22:58:37.605876
6813 22:58:37.605976 DATLAT Default: 0xf
6814 22:58:37.609308 0, 0xFFFF, sum = 0
6815 22:58:37.609414 1, 0xFFFF, sum = 0
6816 22:58:37.612548 2, 0xFFFF, sum = 0
6817 22:58:37.612665 3, 0xFFFF, sum = 0
6818 22:58:37.615839 4, 0xFFFF, sum = 0
6819 22:58:37.615943 5, 0xFFFF, sum = 0
6820 22:58:37.619214 6, 0xFFFF, sum = 0
6821 22:58:37.619333 7, 0xFFFF, sum = 0
6822 22:58:37.622564 8, 0xFFFF, sum = 0
6823 22:58:37.622666 9, 0xFFFF, sum = 0
6824 22:58:37.625871 10, 0xFFFF, sum = 0
6825 22:58:37.625992 11, 0xFFFF, sum = 0
6826 22:58:37.629038 12, 0xFFFF, sum = 0
6827 22:58:37.629142 13, 0x0, sum = 1
6828 22:58:37.632647 14, 0x0, sum = 2
6829 22:58:37.632751 15, 0x0, sum = 3
6830 22:58:37.635885 16, 0x0, sum = 4
6831 22:58:37.635994 best_step = 14
6832 22:58:37.636092
6833 22:58:37.636183 ==
6834 22:58:37.638974 Dram Type= 6, Freq= 0, CH_1, rank 0
6835 22:58:37.645586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6836 22:58:37.645694 ==
6837 22:58:37.645878 RX Vref Scan: 1
6838 22:58:37.645971
6839 22:58:37.648888 RX Vref 0 -> 0, step: 1
6840 22:58:37.648983
6841 22:58:37.652268 RX Delay -311 -> 252, step: 8
6842 22:58:37.652370
6843 22:58:37.655576 Set Vref, RX VrefLevel [Byte0]: 53
6844 22:58:37.658555 [Byte1]: 52
6845 22:58:37.661872
6846 22:58:37.661978 Final RX Vref Byte 0 = 53 to rank0
6847 22:58:37.665104 Final RX Vref Byte 1 = 52 to rank0
6848 22:58:37.668566 Final RX Vref Byte 0 = 53 to rank1
6849 22:58:37.671810 Final RX Vref Byte 1 = 52 to rank1==
6850 22:58:37.675090 Dram Type= 6, Freq= 0, CH_1, rank 0
6851 22:58:37.681452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6852 22:58:37.681557 ==
6853 22:58:37.681655 DQS Delay:
6854 22:58:37.684857 DQS0 = 32, DQS1 = 40
6855 22:58:37.684956 DQM Delay:
6856 22:58:37.685042 DQM0 = 11, DQM1 = 13
6857 22:58:37.688218 DQ Delay:
6858 22:58:37.691591 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6859 22:58:37.694956 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6860 22:58:37.695063 DQ8 =0, DQ9 =0, DQ10 =20, DQ11 =4
6861 22:58:37.698298 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6862 22:58:37.701720
6863 22:58:37.701956
6864 22:58:37.707854 [DQSOSCAuto] RK0, (LSB)MR18= 0x98d2, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6865 22:58:37.711285 CH1 RK0: MR19=C0C, MR18=98D2
6866 22:58:37.717667 CH1_RK0: MR19=0xC0C, MR18=0x98D2, DQSOSC=383, MR23=63, INC=402, DEC=268
6867 22:58:37.717771 ==
6868 22:58:37.721256 Dram Type= 6, Freq= 0, CH_1, rank 1
6869 22:58:37.724672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6870 22:58:37.724800 ==
6871 22:58:37.727972 [Gating] SW mode calibration
6872 22:58:37.734317 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6873 22:58:37.740979 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6874 22:58:37.744369 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6875 22:58:37.747336 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6876 22:58:37.754412 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6877 22:58:37.757368 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6878 22:58:37.760794 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6879 22:58:37.767545 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6880 22:58:37.770747 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6881 22:58:37.774243 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6882 22:58:37.780747 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6883 22:58:37.780873 Total UI for P1: 0, mck2ui 16
6884 22:58:37.787523 best dqsien dly found for B0: ( 0, 14, 24)
6885 22:58:37.787605 Total UI for P1: 0, mck2ui 16
6886 22:58:37.793984 best dqsien dly found for B1: ( 0, 14, 24)
6887 22:58:37.797401 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6888 22:58:37.800313 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6889 22:58:37.800399
6890 22:58:37.803817 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6891 22:58:37.807114 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6892 22:58:37.810435 [Gating] SW calibration Done
6893 22:58:37.810518 ==
6894 22:58:37.813612 Dram Type= 6, Freq= 0, CH_1, rank 1
6895 22:58:37.817100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6896 22:58:37.817218 ==
6897 22:58:37.820432 RX Vref Scan: 0
6898 22:58:37.820532
6899 22:58:37.820623 RX Vref 0 -> 0, step: 1
6900 22:58:37.820712
6901 22:58:37.823644 RX Delay -410 -> 252, step: 16
6902 22:58:37.830482 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6903 22:58:37.833680 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6904 22:58:37.837133 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6905 22:58:37.840063 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6906 22:58:37.847220 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6907 22:58:37.850539 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6908 22:58:37.853529 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6909 22:58:37.857129 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6910 22:58:37.863326 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6911 22:58:37.866715 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6912 22:58:37.870012 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6913 22:58:37.873675 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6914 22:58:37.879887 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6915 22:58:37.883557 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6916 22:58:37.886542 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6917 22:58:37.893378 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6918 22:58:37.893460 ==
6919 22:58:37.896762 Dram Type= 6, Freq= 0, CH_1, rank 1
6920 22:58:37.899764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6921 22:58:37.899873 ==
6922 22:58:37.899966 DQS Delay:
6923 22:58:37.903085 DQS0 = 35, DQS1 = 43
6924 22:58:37.903167 DQM Delay:
6925 22:58:37.906443 DQM0 = 16, DQM1 = 19
6926 22:58:37.906525 DQ Delay:
6927 22:58:37.909872 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6928 22:58:37.913065 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6929 22:58:37.916267 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6930 22:58:37.919632 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6931 22:58:37.919714
6932 22:58:37.919780
6933 22:58:37.919839 ==
6934 22:58:37.922987 Dram Type= 6, Freq= 0, CH_1, rank 1
6935 22:58:37.926293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6936 22:58:37.926376 ==
6937 22:58:37.926441
6938 22:58:37.926501
6939 22:58:37.929443 TX Vref Scan disable
6940 22:58:37.932734 == TX Byte 0 ==
6941 22:58:37.936094 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6942 22:58:37.939526 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6943 22:58:37.942986 == TX Byte 1 ==
6944 22:58:37.946357 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6945 22:58:37.949686 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6946 22:58:37.949796 ==
6947 22:58:37.952570 Dram Type= 6, Freq= 0, CH_1, rank 1
6948 22:58:37.955983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6949 22:58:37.956066 ==
6950 22:58:37.959365
6951 22:58:37.959446
6952 22:58:37.959511 TX Vref Scan disable
6953 22:58:37.962580 == TX Byte 0 ==
6954 22:58:37.966030 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6955 22:58:37.969554 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6956 22:58:37.972485 == TX Byte 1 ==
6957 22:58:37.975788 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6958 22:58:37.978981 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6959 22:58:37.979065
6960 22:58:37.979132 [DATLAT]
6961 22:58:37.982435 Freq=400, CH1 RK1
6962 22:58:37.982518
6963 22:58:37.985727 DATLAT Default: 0xe
6964 22:58:37.985809 0, 0xFFFF, sum = 0
6965 22:58:37.988897 1, 0xFFFF, sum = 0
6966 22:58:37.988980 2, 0xFFFF, sum = 0
6967 22:58:37.992298 3, 0xFFFF, sum = 0
6968 22:58:37.992382 4, 0xFFFF, sum = 0
6969 22:58:37.995610 5, 0xFFFF, sum = 0
6970 22:58:37.995694 6, 0xFFFF, sum = 0
6971 22:58:37.999086 7, 0xFFFF, sum = 0
6972 22:58:37.999169 8, 0xFFFF, sum = 0
6973 22:58:38.002546 9, 0xFFFF, sum = 0
6974 22:58:38.002629 10, 0xFFFF, sum = 0
6975 22:58:38.005425 11, 0xFFFF, sum = 0
6976 22:58:38.005509 12, 0xFFFF, sum = 0
6977 22:58:38.008761 13, 0x0, sum = 1
6978 22:58:38.008866 14, 0x0, sum = 2
6979 22:58:38.012261 15, 0x0, sum = 3
6980 22:58:38.012371 16, 0x0, sum = 4
6981 22:58:38.015489 best_step = 14
6982 22:58:38.015606
6983 22:58:38.015671 ==
6984 22:58:38.019249 Dram Type= 6, Freq= 0, CH_1, rank 1
6985 22:58:38.022241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6986 22:58:38.022352 ==
6987 22:58:38.025763 RX Vref Scan: 0
6988 22:58:38.025868
6989 22:58:38.025961 RX Vref 0 -> 0, step: 1
6990 22:58:38.026058
6991 22:58:38.028661 RX Delay -327 -> 252, step: 8
6992 22:58:38.036357 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6993 22:58:38.039583 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6994 22:58:38.043074 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6995 22:58:38.049354 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6996 22:58:38.052570 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6997 22:58:38.056124 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6998 22:58:38.059385 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6999 22:58:38.066029 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
7000 22:58:38.069348 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
7001 22:58:38.072886 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
7002 22:58:38.075800 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
7003 22:58:38.082492 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
7004 22:58:38.085909 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
7005 22:58:38.089235 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
7006 22:58:38.092424 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
7007 22:58:38.098729 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7008 22:58:38.098834 ==
7009 22:58:38.102148 Dram Type= 6, Freq= 0, CH_1, rank 1
7010 22:58:38.105669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7011 22:58:38.105777 ==
7012 22:58:38.109039 DQS Delay:
7013 22:58:38.109144 DQS0 = 32, DQS1 = 36
7014 22:58:38.109239 DQM Delay:
7015 22:58:38.111945 DQM0 = 13, DQM1 = 11
7016 22:58:38.112044 DQ Delay:
7017 22:58:38.115398 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =12
7018 22:58:38.118807 DQ4 =16, DQ5 =20, DQ6 =16, DQ7 =12
7019 22:58:38.122148 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
7020 22:58:38.125425 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
7021 22:58:38.125537
7022 22:58:38.125645
7023 22:58:38.135741 [DQSOSCAuto] RK1, (LSB)MR18= 0xae56, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 388 ps
7024 22:58:38.135854 CH1 RK1: MR19=C0C, MR18=AE56
7025 22:58:38.141944 CH1_RK1: MR19=0xC0C, MR18=0xAE56, DQSOSC=388, MR23=63, INC=392, DEC=261
7026 22:58:38.145235 [RxdqsGatingPostProcess] freq 400
7027 22:58:38.151497 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7028 22:58:38.154703 best DQS0 dly(2T, 0.5T) = (0, 10)
7029 22:58:38.158093 best DQS1 dly(2T, 0.5T) = (0, 10)
7030 22:58:38.161530 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7031 22:58:38.164975 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7032 22:58:38.167901 best DQS0 dly(2T, 0.5T) = (0, 10)
7033 22:58:38.171477 best DQS1 dly(2T, 0.5T) = (0, 10)
7034 22:58:38.174867 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7035 22:58:38.177814 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7036 22:58:38.181295 Pre-setting of DQS Precalculation
7037 22:58:38.184228 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7038 22:58:38.191046 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7039 22:58:38.197440 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7040 22:58:38.197527
7041 22:58:38.197594
7042 22:58:38.200920 [Calibration Summary] 800 Mbps
7043 22:58:38.204417 CH 0, Rank 0
7044 22:58:38.204501 SW Impedance : PASS
7045 22:58:38.207382 DUTY Scan : NO K
7046 22:58:38.210797 ZQ Calibration : PASS
7047 22:58:38.210881 Jitter Meter : NO K
7048 22:58:38.214153 CBT Training : PASS
7049 22:58:38.217446 Write leveling : PASS
7050 22:58:38.217530 RX DQS gating : PASS
7051 22:58:38.220877 RX DQ/DQS(RDDQC) : PASS
7052 22:58:38.224316 TX DQ/DQS : PASS
7053 22:58:38.224400 RX DATLAT : PASS
7054 22:58:38.227331 RX DQ/DQS(Engine): PASS
7055 22:58:38.230745 TX OE : NO K
7056 22:58:38.230829 All Pass.
7057 22:58:38.230896
7058 22:58:38.230957 CH 0, Rank 1
7059 22:58:38.233957 SW Impedance : PASS
7060 22:58:38.237170 DUTY Scan : NO K
7061 22:58:38.237253 ZQ Calibration : PASS
7062 22:58:38.240748 Jitter Meter : NO K
7063 22:58:38.243904 CBT Training : PASS
7064 22:58:38.243988 Write leveling : NO K
7065 22:58:38.247294 RX DQS gating : PASS
7066 22:58:38.247378 RX DQ/DQS(RDDQC) : PASS
7067 22:58:38.250810 TX DQ/DQS : PASS
7068 22:58:38.254059 RX DATLAT : PASS
7069 22:58:38.254144 RX DQ/DQS(Engine): PASS
7070 22:58:38.257417 TX OE : NO K
7071 22:58:38.257501 All Pass.
7072 22:58:38.257568
7073 22:58:38.260601 CH 1, Rank 0
7074 22:58:38.260684 SW Impedance : PASS
7075 22:58:38.264024 DUTY Scan : NO K
7076 22:58:38.267431 ZQ Calibration : PASS
7077 22:58:38.267542 Jitter Meter : NO K
7078 22:58:38.270395 CBT Training : PASS
7079 22:58:38.273635 Write leveling : PASS
7080 22:58:38.273720 RX DQS gating : PASS
7081 22:58:38.277436 RX DQ/DQS(RDDQC) : PASS
7082 22:58:38.280338 TX DQ/DQS : PASS
7083 22:58:38.280422 RX DATLAT : PASS
7084 22:58:38.283757 RX DQ/DQS(Engine): PASS
7085 22:58:38.287043 TX OE : NO K
7086 22:58:38.287127 All Pass.
7087 22:58:38.287201
7088 22:58:38.287264 CH 1, Rank 1
7089 22:58:38.290411 SW Impedance : PASS
7090 22:58:38.293830 DUTY Scan : NO K
7091 22:58:38.293914 ZQ Calibration : PASS
7092 22:58:38.296718 Jitter Meter : NO K
7093 22:58:38.296810 CBT Training : PASS
7094 22:58:38.300546 Write leveling : NO K
7095 22:58:38.303515 RX DQS gating : PASS
7096 22:58:38.303599 RX DQ/DQS(RDDQC) : PASS
7097 22:58:38.306895 TX DQ/DQS : PASS
7098 22:58:38.310381 RX DATLAT : PASS
7099 22:58:38.310465 RX DQ/DQS(Engine): PASS
7100 22:58:38.313390 TX OE : NO K
7101 22:58:38.313474 All Pass.
7102 22:58:38.313540
7103 22:58:38.316772 DramC Write-DBI off
7104 22:58:38.320199 PER_BANK_REFRESH: Hybrid Mode
7105 22:58:38.320284 TX_TRACKING: ON
7106 22:58:38.330292 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7107 22:58:38.333391 [FAST_K] Save calibration result to emmc
7108 22:58:38.336709 dramc_set_vcore_voltage set vcore to 725000
7109 22:58:38.339998 Read voltage for 1600, 0
7110 22:58:38.340082 Vio18 = 0
7111 22:58:38.340148 Vcore = 725000
7112 22:58:38.343639 Vdram = 0
7113 22:58:38.343722 Vddq = 0
7114 22:58:38.343789 Vmddr = 0
7115 22:58:38.350261 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7116 22:58:38.353506 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7117 22:58:38.356901 MEM_TYPE=3, freq_sel=13
7118 22:58:38.359879 sv_algorithm_assistance_LP4_3733
7119 22:58:38.363549 ============ PULL DRAM RESETB DOWN ============
7120 22:58:38.369964 ========== PULL DRAM RESETB DOWN end =========
7121 22:58:38.373306 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7122 22:58:38.376665 ===================================
7123 22:58:38.380115 LPDDR4 DRAM CONFIGURATION
7124 22:58:38.383219 ===================================
7125 22:58:38.383295 EX_ROW_EN[0] = 0x0
7126 22:58:38.386592 EX_ROW_EN[1] = 0x0
7127 22:58:38.386666 LP4Y_EN = 0x0
7128 22:58:38.389622 WORK_FSP = 0x1
7129 22:58:38.389736 WL = 0x5
7130 22:58:38.392934 RL = 0x5
7131 22:58:38.393018 BL = 0x2
7132 22:58:38.396147 RPST = 0x0
7133 22:58:38.396279 RD_PRE = 0x0
7134 22:58:38.399678 WR_PRE = 0x1
7135 22:58:38.402959 WR_PST = 0x1
7136 22:58:38.403143 DBI_WR = 0x0
7137 22:58:38.405922 DBI_RD = 0x0
7138 22:58:38.406035 OTF = 0x1
7139 22:58:38.409380 ===================================
7140 22:58:38.412737 ===================================
7141 22:58:38.412840 ANA top config
7142 22:58:38.416203 ===================================
7143 22:58:38.419610 DLL_ASYNC_EN = 0
7144 22:58:38.422534 ALL_SLAVE_EN = 0
7145 22:58:38.425968 NEW_RANK_MODE = 1
7146 22:58:38.429340 DLL_IDLE_MODE = 1
7147 22:58:38.429412 LP45_APHY_COMB_EN = 1
7148 22:58:38.432762 TX_ODT_DIS = 0
7149 22:58:38.436228 NEW_8X_MODE = 1
7150 22:58:38.439140 ===================================
7151 22:58:38.442498 ===================================
7152 22:58:38.445712 data_rate = 3200
7153 22:58:38.449082 CKR = 1
7154 22:58:38.452382 DQ_P2S_RATIO = 8
7155 22:58:38.455763 ===================================
7156 22:58:38.455838 CA_P2S_RATIO = 8
7157 22:58:38.458984 DQ_CA_OPEN = 0
7158 22:58:38.462517 DQ_SEMI_OPEN = 0
7159 22:58:38.465707 CA_SEMI_OPEN = 0
7160 22:58:38.468914 CA_FULL_RATE = 0
7161 22:58:38.472233 DQ_CKDIV4_EN = 0
7162 22:58:38.472310 CA_CKDIV4_EN = 0
7163 22:58:38.475709 CA_PREDIV_EN = 0
7164 22:58:38.479073 PH8_DLY = 12
7165 22:58:38.482443 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7166 22:58:38.485653 DQ_AAMCK_DIV = 4
7167 22:58:38.489066 CA_AAMCK_DIV = 4
7168 22:58:38.489148 CA_ADMCK_DIV = 4
7169 22:58:38.491976 DQ_TRACK_CA_EN = 0
7170 22:58:38.495450 CA_PICK = 1600
7171 22:58:38.498666 CA_MCKIO = 1600
7172 22:58:38.501949 MCKIO_SEMI = 0
7173 22:58:38.505344 PLL_FREQ = 3068
7174 22:58:38.508477 DQ_UI_PI_RATIO = 32
7175 22:58:38.511952 CA_UI_PI_RATIO = 0
7176 22:58:38.512038 ===================================
7177 22:58:38.515517 ===================================
7178 22:58:38.518501 memory_type:LPDDR4
7179 22:58:38.521882 GP_NUM : 10
7180 22:58:38.521954 SRAM_EN : 1
7181 22:58:38.525327 MD32_EN : 0
7182 22:58:38.528204 ===================================
7183 22:58:38.531599 [ANA_INIT] >>>>>>>>>>>>>>
7184 22:58:38.535049 <<<<<< [CONFIGURE PHASE]: ANA_TX
7185 22:58:38.538387 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7186 22:58:38.541504 ===================================
7187 22:58:38.544912 data_rate = 3200,PCW = 0X7600
7188 22:58:38.548325 ===================================
7189 22:58:38.551613 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7190 22:58:38.554640 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7191 22:58:38.561549 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7192 22:58:38.564922 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7193 22:58:38.567831 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7194 22:58:38.571200 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7195 22:58:38.574415 [ANA_INIT] flow start
7196 22:58:38.577933 [ANA_INIT] PLL >>>>>>>>
7197 22:58:38.578009 [ANA_INIT] PLL <<<<<<<<
7198 22:58:38.581354 [ANA_INIT] MIDPI >>>>>>>>
7199 22:58:38.584266 [ANA_INIT] MIDPI <<<<<<<<
7200 22:58:38.587897 [ANA_INIT] DLL >>>>>>>>
7201 22:58:38.587978 [ANA_INIT] DLL <<<<<<<<
7202 22:58:38.591279 [ANA_INIT] flow end
7203 22:58:38.594196 ============ LP4 DIFF to SE enter ============
7204 22:58:38.597653 ============ LP4 DIFF to SE exit ============
7205 22:58:38.601154 [ANA_INIT] <<<<<<<<<<<<<
7206 22:58:38.604358 [Flow] Enable top DCM control >>>>>
7207 22:58:38.607671 [Flow] Enable top DCM control <<<<<
7208 22:58:38.611160 Enable DLL master slave shuffle
7209 22:58:38.617290 ==============================================================
7210 22:58:38.617379 Gating Mode config
7211 22:58:38.624166 ==============================================================
7212 22:58:38.624252 Config description:
7213 22:58:38.633889 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7214 22:58:38.640373 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7215 22:58:38.646926 SELPH_MODE 0: By rank 1: By Phase
7216 22:58:38.650443 ==============================================================
7217 22:58:38.653755 GAT_TRACK_EN = 1
7218 22:58:38.656946 RX_GATING_MODE = 2
7219 22:58:38.660231 RX_GATING_TRACK_MODE = 2
7220 22:58:38.663685 SELPH_MODE = 1
7221 22:58:38.667089 PICG_EARLY_EN = 1
7222 22:58:38.670014 VALID_LAT_VALUE = 1
7223 22:58:38.676729 ==============================================================
7224 22:58:38.680209 Enter into Gating configuration >>>>
7225 22:58:38.683693 Exit from Gating configuration <<<<
7226 22:58:38.683825 Enter into DVFS_PRE_config >>>>>
7227 22:58:38.696441 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7228 22:58:38.699997 Exit from DVFS_PRE_config <<<<<
7229 22:58:38.703271 Enter into PICG configuration >>>>
7230 22:58:38.706531 Exit from PICG configuration <<<<
7231 22:58:38.706612 [RX_INPUT] configuration >>>>>
7232 22:58:38.709830 [RX_INPUT] configuration <<<<<
7233 22:58:38.716509 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7234 22:58:38.719880 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7235 22:58:38.726372 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7236 22:58:38.733180 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7237 22:58:38.739816 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7238 22:58:38.746622 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7239 22:58:38.749460 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7240 22:58:38.753029 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7241 22:58:38.759734 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7242 22:58:38.762964 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7243 22:58:38.766354 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7244 22:58:38.772680 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7245 22:58:38.776056 ===================================
7246 22:58:38.776141 LPDDR4 DRAM CONFIGURATION
7247 22:58:38.779433 ===================================
7248 22:58:38.782796 EX_ROW_EN[0] = 0x0
7249 22:58:38.782881 EX_ROW_EN[1] = 0x0
7250 22:58:38.785829 LP4Y_EN = 0x0
7251 22:58:38.789479 WORK_FSP = 0x1
7252 22:58:38.789564 WL = 0x5
7253 22:58:38.792517 RL = 0x5
7254 22:58:38.792628 BL = 0x2
7255 22:58:38.796054 RPST = 0x0
7256 22:58:38.796139 RD_PRE = 0x0
7257 22:58:38.799142 WR_PRE = 0x1
7258 22:58:38.799226 WR_PST = 0x1
7259 22:58:38.802308 DBI_WR = 0x0
7260 22:58:38.802392 DBI_RD = 0x0
7261 22:58:38.805662 OTF = 0x1
7262 22:58:38.809144 ===================================
7263 22:58:38.812346 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7264 22:58:38.815708 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7265 22:58:38.822282 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7266 22:58:38.825649 ===================================
7267 22:58:38.825734 LPDDR4 DRAM CONFIGURATION
7268 22:58:38.829118 ===================================
7269 22:58:38.832039 EX_ROW_EN[0] = 0x10
7270 22:58:38.832123 EX_ROW_EN[1] = 0x0
7271 22:58:38.835411 LP4Y_EN = 0x0
7272 22:58:38.838799 WORK_FSP = 0x1
7273 22:58:38.838882 WL = 0x5
7274 22:58:38.841805 RL = 0x5
7275 22:58:38.841888 BL = 0x2
7276 22:58:38.845144 RPST = 0x0
7277 22:58:38.845228 RD_PRE = 0x0
7278 22:58:38.848636 WR_PRE = 0x1
7279 22:58:38.848747 WR_PST = 0x1
7280 22:58:38.852075 DBI_WR = 0x0
7281 22:58:38.852158 DBI_RD = 0x0
7282 22:58:38.855465 OTF = 0x1
7283 22:58:38.858391 ===================================
7284 22:58:38.865215 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7285 22:58:38.865300 ==
7286 22:58:38.868505 Dram Type= 6, Freq= 0, CH_0, rank 0
7287 22:58:38.871495 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7288 22:58:38.871582 ==
7289 22:58:38.874974 [Duty_Offset_Calibration]
7290 22:58:38.875058 B0:2 B1:0 CA:1
7291 22:58:38.875125
7292 22:58:38.878389 [DutyScan_Calibration_Flow] k_type=0
7293 22:58:38.887835
7294 22:58:38.887916 ==CLK 0==
7295 22:58:38.891242 Final CLK duty delay cell = -4
7296 22:58:38.894620 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7297 22:58:38.897893 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7298 22:58:38.901079 [-4] AVG Duty = 4922%(X100)
7299 22:58:38.901161
7300 22:58:38.904494 CH0 CLK Duty spec in!! Max-Min= 218%
7301 22:58:38.907896 [DutyScan_Calibration_Flow] ====Done====
7302 22:58:38.907979
7303 22:58:38.910956 [DutyScan_Calibration_Flow] k_type=1
7304 22:58:38.927432
7305 22:58:38.927515 ==DQS 0 ==
7306 22:58:38.930792 Final DQS duty delay cell = 0
7307 22:58:38.933706 [0] MAX Duty = 5249%(X100), DQS PI = 32
7308 22:58:38.937071 [0] MIN Duty = 4969%(X100), DQS PI = 0
7309 22:58:38.940485 [0] AVG Duty = 5109%(X100)
7310 22:58:38.940592
7311 22:58:38.940684 ==DQS 1 ==
7312 22:58:38.944027 Final DQS duty delay cell = -4
7313 22:58:38.947429 [-4] MAX Duty = 5094%(X100), DQS PI = 28
7314 22:58:38.950816 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7315 22:58:38.953742 [-4] AVG Duty = 4984%(X100)
7316 22:58:38.953819
7317 22:58:38.957123 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7318 22:58:38.957196
7319 22:58:38.960548 CH0 DQS 1 Duty spec in!! Max-Min= 219%
7320 22:58:38.964027 [DutyScan_Calibration_Flow] ====Done====
7321 22:58:38.964110
7322 22:58:38.966935 [DutyScan_Calibration_Flow] k_type=3
7323 22:58:38.983931
7324 22:58:38.984013 ==DQM 0 ==
7325 22:58:38.987224 Final DQM duty delay cell = 0
7326 22:58:38.990613 [0] MAX Duty = 5093%(X100), DQS PI = 24
7327 22:58:38.993964 [0] MIN Duty = 4844%(X100), DQS PI = 2
7328 22:58:38.994045 [0] AVG Duty = 4968%(X100)
7329 22:58:38.997453
7330 22:58:38.997534 ==DQM 1 ==
7331 22:58:39.000974 Final DQM duty delay cell = -4
7332 22:58:39.003827 [-4] MAX Duty = 5031%(X100), DQS PI = 46
7333 22:58:39.006974 [-4] MIN Duty = 4751%(X100), DQS PI = 10
7334 22:58:39.010315 [-4] AVG Duty = 4891%(X100)
7335 22:58:39.010420
7336 22:58:39.013919 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7337 22:58:39.014023
7338 22:58:39.016872 CH0 DQM 1 Duty spec in!! Max-Min= 280%
7339 22:58:39.020464 [DutyScan_Calibration_Flow] ====Done====
7340 22:58:39.020566
7341 22:58:39.023711 [DutyScan_Calibration_Flow] k_type=2
7342 22:58:39.041430
7343 22:58:39.041534 ==DQ 0 ==
7344 22:58:39.044804 Final DQ duty delay cell = 0
7345 22:58:39.047787 [0] MAX Duty = 5156%(X100), DQS PI = 36
7346 22:58:39.051065 [0] MIN Duty = 5000%(X100), DQS PI = 0
7347 22:58:39.051167 [0] AVG Duty = 5078%(X100)
7348 22:58:39.054483
7349 22:58:39.054582 ==DQ 1 ==
7350 22:58:39.057903 Final DQ duty delay cell = 0
7351 22:58:39.061288 [0] MAX Duty = 4969%(X100), DQS PI = 44
7352 22:58:39.064701 [0] MIN Duty = 4875%(X100), DQS PI = 0
7353 22:58:39.064842 [0] AVG Duty = 4922%(X100)
7354 22:58:39.064936
7355 22:58:39.070892 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7356 22:58:39.070998
7357 22:58:39.074262 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7358 22:58:39.077394 [DutyScan_Calibration_Flow] ====Done====
7359 22:58:39.077498 ==
7360 22:58:39.080820 Dram Type= 6, Freq= 0, CH_1, rank 0
7361 22:58:39.084290 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7362 22:58:39.084392 ==
7363 22:58:39.087659 [Duty_Offset_Calibration]
7364 22:58:39.087761 B0:0 B1:-1 CA:2
7365 22:58:39.087851
7366 22:58:39.090927 [DutyScan_Calibration_Flow] k_type=0
7367 22:58:39.101535
7368 22:58:39.101641 ==CLK 0==
7369 22:58:39.105056 Final CLK duty delay cell = 0
7370 22:58:39.108409 [0] MAX Duty = 5156%(X100), DQS PI = 10
7371 22:58:39.111495 [0] MIN Duty = 4906%(X100), DQS PI = 46
7372 22:58:39.114811 [0] AVG Duty = 5031%(X100)
7373 22:58:39.114910
7374 22:58:39.118262 CH1 CLK Duty spec in!! Max-Min= 250%
7375 22:58:39.121515 [DutyScan_Calibration_Flow] ====Done====
7376 22:58:39.121615
7377 22:58:39.124585 [DutyScan_Calibration_Flow] k_type=1
7378 22:58:39.141526
7379 22:58:39.141633 ==DQS 0 ==
7380 22:58:39.144477 Final DQS duty delay cell = 0
7381 22:58:39.147962 [0] MAX Duty = 5124%(X100), DQS PI = 26
7382 22:58:39.151437 [0] MIN Duty = 4969%(X100), DQS PI = 2
7383 22:58:39.154355 [0] AVG Duty = 5046%(X100)
7384 22:58:39.154450
7385 22:58:39.154544 ==DQS 1 ==
7386 22:58:39.157820 Final DQS duty delay cell = 0
7387 22:58:39.161188 [0] MAX Duty = 5187%(X100), DQS PI = 0
7388 22:58:39.164654 [0] MIN Duty = 4813%(X100), DQS PI = 34
7389 22:58:39.167543 [0] AVG Duty = 5000%(X100)
7390 22:58:39.167644
7391 22:58:39.170909 CH1 DQS 0 Duty spec in!! Max-Min= 155%
7392 22:58:39.171015
7393 22:58:39.174341 CH1 DQS 1 Duty spec in!! Max-Min= 374%
7394 22:58:39.177728 [DutyScan_Calibration_Flow] ====Done====
7395 22:58:39.177825
7396 22:58:39.181011 [DutyScan_Calibration_Flow] k_type=3
7397 22:58:39.198838
7398 22:58:39.198943 ==DQM 0 ==
7399 22:58:39.202097 Final DQM duty delay cell = 4
7400 22:58:39.205442 [4] MAX Duty = 5125%(X100), DQS PI = 6
7401 22:58:39.208995 [4] MIN Duty = 4969%(X100), DQS PI = 46
7402 22:58:39.209085 [4] AVG Duty = 5047%(X100)
7403 22:58:39.212443
7404 22:58:39.212543 ==DQM 1 ==
7405 22:58:39.215238 Final DQM duty delay cell = 0
7406 22:58:39.218849 [0] MAX Duty = 5281%(X100), DQS PI = 58
7407 22:58:39.222256 [0] MIN Duty = 4907%(X100), DQS PI = 34
7408 22:58:39.225968 [0] AVG Duty = 5094%(X100)
7409 22:58:39.226066
7410 22:58:39.228709 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7411 22:58:39.228854
7412 22:58:39.231863 CH1 DQM 1 Duty spec in!! Max-Min= 374%
7413 22:58:39.235386 [DutyScan_Calibration_Flow] ====Done====
7414 22:58:39.235489
7415 22:58:39.238464 [DutyScan_Calibration_Flow] k_type=2
7416 22:58:39.255910
7417 22:58:39.256005 ==DQ 0 ==
7418 22:58:39.258847 Final DQ duty delay cell = 0
7419 22:58:39.262206 [0] MAX Duty = 5093%(X100), DQS PI = 20
7420 22:58:39.265596 [0] MIN Duty = 4969%(X100), DQS PI = 46
7421 22:58:39.265698 [0] AVG Duty = 5031%(X100)
7422 22:58:39.269028
7423 22:58:39.269187 ==DQ 1 ==
7424 22:58:39.272518 Final DQ duty delay cell = 0
7425 22:58:39.275309 [0] MAX Duty = 5094%(X100), DQS PI = 2
7426 22:58:39.278789 [0] MIN Duty = 4813%(X100), DQS PI = 34
7427 22:58:39.278890 [0] AVG Duty = 4953%(X100)
7428 22:58:39.282269
7429 22:58:39.285399 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7430 22:58:39.285505
7431 22:58:39.288714 CH1 DQ 1 Duty spec in!! Max-Min= 281%
7432 22:58:39.292180 [DutyScan_Calibration_Flow] ====Done====
7433 22:58:39.295712 nWR fixed to 30
7434 22:58:39.295815 [ModeRegInit_LP4] CH0 RK0
7435 22:58:39.298906 [ModeRegInit_LP4] CH0 RK1
7436 22:58:39.302041 [ModeRegInit_LP4] CH1 RK0
7437 22:58:39.305467 [ModeRegInit_LP4] CH1 RK1
7438 22:58:39.305538 match AC timing 5
7439 22:58:39.311907 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7440 22:58:39.315397 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7441 22:58:39.318727 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7442 22:58:39.325399 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7443 22:58:39.328724 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7444 22:58:39.328852 [MiockJmeterHQA]
7445 22:58:39.328960
7446 22:58:39.332030 [DramcMiockJmeter] u1RxGatingPI = 0
7447 22:58:39.334882 0 : 4254, 4027
7448 22:58:39.334982 4 : 4363, 4137
7449 22:58:39.338277 8 : 4252, 4027
7450 22:58:39.338375 12 : 4254, 4029
7451 22:58:39.338465 16 : 4257, 4032
7452 22:58:39.341527 20 : 4253, 4026
7453 22:58:39.341605 24 : 4363, 4138
7454 22:58:39.344807 28 : 4363, 4138
7455 22:58:39.344905 32 : 4252, 4027
7456 22:58:39.348349 36 : 4252, 4027
7457 22:58:39.348446 40 : 4253, 4027
7458 22:58:39.351451 44 : 4252, 4027
7459 22:58:39.351552 48 : 4255, 4029
7460 22:58:39.351688 52 : 4363, 4137
7461 22:58:39.354803 56 : 4252, 4026
7462 22:58:39.354906 60 : 4252, 4027
7463 22:58:39.358187 64 : 4253, 4029
7464 22:58:39.358336 68 : 4252, 4029
7465 22:58:39.361580 72 : 4250, 4027
7466 22:58:39.361649 76 : 4360, 4138
7467 22:58:39.364923 80 : 4360, 4137
7468 22:58:39.365114 84 : 4250, 4027
7469 22:58:39.365258 88 : 4249, 3353
7470 22:58:39.367876 92 : 4250, 0
7471 22:58:39.367974 96 : 4363, 0
7472 22:58:39.371362 100 : 4250, 0
7473 22:58:39.371464 104 : 4255, 0
7474 22:58:39.371563 108 : 4250, 0
7475 22:58:39.374666 112 : 4253, 0
7476 22:58:39.374783 116 : 4360, 0
7477 22:58:39.378007 120 : 4361, 0
7478 22:58:39.378105 124 : 4363, 0
7479 22:58:39.378169 128 : 4250, 0
7480 22:58:39.380954 132 : 4250, 0
7481 22:58:39.381022 136 : 4250, 0
7482 22:58:39.384480 140 : 4250, 0
7483 22:58:39.384575 144 : 4249, 0
7484 22:58:39.384663 148 : 4250, 0
7485 22:58:39.387798 152 : 4252, 0
7486 22:58:39.387919 156 : 4249, 0
7487 22:58:39.388012 160 : 4250, 0
7488 22:58:39.391012 164 : 4252, 0
7489 22:58:39.391112 168 : 4360, 0
7490 22:58:39.394417 172 : 4361, 0
7491 22:58:39.394531 176 : 4250, 0
7492 22:58:39.394630 180 : 4249, 0
7493 22:58:39.397730 184 : 4360, 0
7494 22:58:39.397828 188 : 4361, 0
7495 22:58:39.401123 192 : 4252, 0
7496 22:58:39.401207 196 : 4250, 0
7497 22:58:39.401272 200 : 4250, 1
7498 22:58:39.404426 204 : 4250, 2491
7499 22:58:39.404509 208 : 4360, 4137
7500 22:58:39.407601 212 : 4363, 4140
7501 22:58:39.407684 216 : 4250, 4027
7502 22:58:39.410991 220 : 4249, 4027
7503 22:58:39.411105 224 : 4363, 4140
7504 22:58:39.414482 228 : 4250, 4027
7505 22:58:39.414566 232 : 4250, 4027
7506 22:58:39.417580 236 : 4249, 4027
7507 22:58:39.417662 240 : 4252, 4029
7508 22:58:39.420902 244 : 4250, 4026
7509 22:58:39.420984 248 : 4250, 4027
7510 22:58:39.421049 252 : 4363, 4138
7511 22:58:39.424211 256 : 4250, 4027
7512 22:58:39.424293 260 : 4250, 4027
7513 22:58:39.427419 264 : 4361, 4137
7514 22:58:39.427518 268 : 4250, 4027
7515 22:58:39.430859 272 : 4249, 4027
7516 22:58:39.430941 276 : 4363, 4140
7517 22:58:39.433799 280 : 4250, 4027
7518 22:58:39.433891 284 : 4250, 4027
7519 22:58:39.437132 288 : 4252, 4027
7520 22:58:39.437214 292 : 4252, 4029
7521 22:58:39.440650 296 : 4250, 4027
7522 22:58:39.440769 300 : 4250, 4027
7523 22:58:39.443979 304 : 4360, 4138
7524 22:58:39.444089 308 : 4250, 4027
7525 22:58:39.446941 312 : 4250, 3841
7526 22:58:39.447024 316 : 4361, 1982
7527 22:58:39.447089
7528 22:58:39.450212 MIOCK jitter meter ch=0
7529 22:58:39.450293
7530 22:58:39.454002 1T = (316-92) = 224 dly cells
7531 22:58:39.456732 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7532 22:58:39.456856 ==
7533 22:58:39.460312 Dram Type= 6, Freq= 0, CH_0, rank 0
7534 22:58:39.466954 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7535 22:58:39.467083 ==
7536 22:58:39.470199 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7537 22:58:39.476705 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7538 22:58:39.480136 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7539 22:58:39.486502 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7540 22:58:39.494427 [CA 0] Center 43 (13~73) winsize 61
7541 22:58:39.497944 [CA 1] Center 43 (13~73) winsize 61
7542 22:58:39.501496 [CA 2] Center 38 (8~68) winsize 61
7543 22:58:39.504414 [CA 3] Center 37 (8~67) winsize 60
7544 22:58:39.507605 [CA 4] Center 36 (6~66) winsize 61
7545 22:58:39.510904 [CA 5] Center 35 (5~65) winsize 61
7546 22:58:39.510985
7547 22:58:39.514397 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7548 22:58:39.514478
7549 22:58:39.517758 [CATrainingPosCal] consider 1 rank data
7550 22:58:39.521128 u2DelayCellTimex100 = 290/100 ps
7551 22:58:39.527809 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7552 22:58:39.530998 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7553 22:58:39.534358 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7554 22:58:39.537770 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7555 22:58:39.541104 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7556 22:58:39.543861 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7557 22:58:39.543957
7558 22:58:39.547374 CA PerBit enable=1, Macro0, CA PI delay=35
7559 22:58:39.547456
7560 22:58:39.550719 [CBTSetCACLKResult] CA Dly = 35
7561 22:58:39.553887 CS Dly: 9 (0~40)
7562 22:58:39.557434 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7563 22:58:39.560745 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7564 22:58:39.560843 ==
7565 22:58:39.563968 Dram Type= 6, Freq= 0, CH_0, rank 1
7566 22:58:39.570379 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7567 22:58:39.570485 ==
7568 22:58:39.573854 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7569 22:58:39.580645 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7570 22:58:39.583581 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7571 22:58:39.590496 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7572 22:58:39.597868 [CA 0] Center 43 (13~74) winsize 62
7573 22:58:39.601363 [CA 1] Center 43 (14~73) winsize 60
7574 22:58:39.604207 [CA 2] Center 38 (9~68) winsize 60
7575 22:58:39.607728 [CA 3] Center 38 (9~68) winsize 60
7576 22:58:39.611188 [CA 4] Center 37 (7~67) winsize 61
7577 22:58:39.614170 [CA 5] Center 36 (6~66) winsize 61
7578 22:58:39.614254
7579 22:58:39.617666 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7580 22:58:39.617798
7581 22:58:39.624211 [CATrainingPosCal] consider 2 rank data
7582 22:58:39.624294 u2DelayCellTimex100 = 290/100 ps
7583 22:58:39.631032 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7584 22:58:39.634306 CA1 delay=43 (14~73),Diff = 8 PI (26 cell)
7585 22:58:39.637300 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7586 22:58:39.640978 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7587 22:58:39.644058 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7588 22:58:39.647312 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7589 22:58:39.647396
7590 22:58:39.650915 CA PerBit enable=1, Macro0, CA PI delay=35
7591 22:58:39.651033
7592 22:58:39.654345 [CBTSetCACLKResult] CA Dly = 35
7593 22:58:39.657164 CS Dly: 10 (0~43)
7594 22:58:39.660538 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7595 22:58:39.663944 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7596 22:58:39.664053
7597 22:58:39.666904 ----->DramcWriteLeveling(PI) begin...
7598 22:58:39.667005 ==
7599 22:58:39.670700 Dram Type= 6, Freq= 0, CH_0, rank 0
7600 22:58:39.677138 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7601 22:58:39.677222 ==
7602 22:58:39.680365 Write leveling (Byte 0): 35 => 35
7603 22:58:39.683529 Write leveling (Byte 1): 31 => 31
7604 22:58:39.686911 DramcWriteLeveling(PI) end<-----
7605 22:58:39.687026
7606 22:58:39.687129 ==
7607 22:58:39.689994 Dram Type= 6, Freq= 0, CH_0, rank 0
7608 22:58:39.693674 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7609 22:58:39.693789 ==
7610 22:58:39.696500 [Gating] SW mode calibration
7611 22:58:39.703302 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7612 22:58:39.710170 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7613 22:58:39.713498 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7614 22:58:39.716545 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7615 22:58:39.723366 1 4 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
7616 22:58:39.726446 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7617 22:58:39.729950 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7618 22:58:39.736216 1 4 20 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
7619 22:58:39.739979 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7620 22:58:39.742931 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7621 22:58:39.749559 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7622 22:58:39.752719 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7623 22:58:39.756150 1 5 8 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
7624 22:58:39.759562 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7625 22:58:39.766219 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
7626 22:58:39.769137 1 5 20 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
7627 22:58:39.775769 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7628 22:58:39.779033 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7629 22:58:39.782558 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7630 22:58:39.789204 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7631 22:58:39.792215 1 6 8 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
7632 22:58:39.795612 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7633 22:58:39.802436 1 6 16 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7634 22:58:39.805785 1 6 20 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
7635 22:58:39.808830 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7636 22:58:39.812548 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7637 22:58:39.819029 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7638 22:58:39.822476 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7639 22:58:39.825226 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7640 22:58:39.832278 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7641 22:58:39.835322 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7642 22:58:39.838948 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7643 22:58:39.845766 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7644 22:58:39.848509 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 22:58:39.851949 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 22:58:39.858594 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 22:58:39.861976 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 22:58:39.865473 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 22:58:39.871942 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 22:58:39.875199 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 22:58:39.878462 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 22:58:39.885296 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 22:58:39.888222 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 22:58:39.891582 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 22:58:39.898488 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 22:58:39.901555 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7657 22:58:39.904993 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7658 22:58:39.908298 Total UI for P1: 0, mck2ui 16
7659 22:58:39.911444 best dqsien dly found for B0: ( 1, 9, 12)
7660 22:58:39.918210 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7661 22:58:39.921652 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7662 22:58:39.925166 Total UI for P1: 0, mck2ui 16
7663 22:58:39.928467 best dqsien dly found for B1: ( 1, 9, 20)
7664 22:58:39.931322 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7665 22:58:39.934846 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7666 22:58:39.934954
7667 22:58:39.937780 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7668 22:58:39.944607 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7669 22:58:39.944726 [Gating] SW calibration Done
7670 22:58:39.944846 ==
7671 22:58:39.947814 Dram Type= 6, Freq= 0, CH_0, rank 0
7672 22:58:39.954419 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7673 22:58:39.954524 ==
7674 22:58:39.954622 RX Vref Scan: 0
7675 22:58:39.954715
7676 22:58:39.957723 RX Vref 0 -> 0, step: 1
7677 22:58:39.957825
7678 22:58:39.960901 RX Delay 0 -> 252, step: 8
7679 22:58:39.964395 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7680 22:58:39.967481 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7681 22:58:39.971208 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7682 22:58:39.974702 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7683 22:58:39.980975 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7684 22:58:39.984273 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7685 22:58:39.987516 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7686 22:58:39.990808 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7687 22:58:39.994288 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7688 22:58:40.000740 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7689 22:58:40.004120 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7690 22:58:40.007199 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7691 22:58:40.010737 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7692 22:58:40.013990 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7693 22:58:40.020576 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7694 22:58:40.023535 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7695 22:58:40.023634 ==
7696 22:58:40.026978 Dram Type= 6, Freq= 0, CH_0, rank 0
7697 22:58:40.030377 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7698 22:58:40.030480 ==
7699 22:58:40.033685 DQS Delay:
7700 22:58:40.033785 DQS0 = 0, DQS1 = 0
7701 22:58:40.036703 DQM Delay:
7702 22:58:40.036857 DQM0 = 137, DQM1 = 127
7703 22:58:40.036957 DQ Delay:
7704 22:58:40.040207 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7705 22:58:40.046720 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7706 22:58:40.050045 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7707 22:58:40.053507 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7708 22:58:40.053586
7709 22:58:40.053661
7710 22:58:40.053722 ==
7711 22:58:40.056502 Dram Type= 6, Freq= 0, CH_0, rank 0
7712 22:58:40.060005 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7713 22:58:40.060104 ==
7714 22:58:40.060196
7715 22:58:40.060283
7716 22:58:40.063186 TX Vref Scan disable
7717 22:58:40.066559 == TX Byte 0 ==
7718 22:58:40.069943 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7719 22:58:40.073382 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7720 22:58:40.076302 == TX Byte 1 ==
7721 22:58:40.079937 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7722 22:58:40.083294 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7723 22:58:40.083391 ==
7724 22:58:40.086315 Dram Type= 6, Freq= 0, CH_0, rank 0
7725 22:58:40.089899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7726 22:58:40.093297 ==
7727 22:58:40.104530
7728 22:58:40.107864 TX Vref early break, caculate TX vref
7729 22:58:40.110931 TX Vref=16, minBit 1, minWin=23, winSum=376
7730 22:58:40.114406 TX Vref=18, minBit 8, minWin=23, winSum=385
7731 22:58:40.117770 TX Vref=20, minBit 4, minWin=24, winSum=399
7732 22:58:40.120801 TX Vref=22, minBit 0, minWin=25, winSum=409
7733 22:58:40.124244 TX Vref=24, minBit 1, minWin=25, winSum=416
7734 22:58:40.130748 TX Vref=26, minBit 10, minWin=25, winSum=424
7735 22:58:40.134157 TX Vref=28, minBit 0, minWin=26, winSum=431
7736 22:58:40.137399 TX Vref=30, minBit 2, minWin=25, winSum=424
7737 22:58:40.140885 TX Vref=32, minBit 0, minWin=25, winSum=412
7738 22:58:40.143926 TX Vref=34, minBit 0, minWin=25, winSum=406
7739 22:58:40.150754 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 28
7740 22:58:40.150838
7741 22:58:40.153895 Final TX Range 0 Vref 28
7742 22:58:40.153978
7743 22:58:40.154043 ==
7744 22:58:40.157344 Dram Type= 6, Freq= 0, CH_0, rank 0
7745 22:58:40.160629 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7746 22:58:40.160737 ==
7747 22:58:40.160876
7748 22:58:40.160965
7749 22:58:40.163578 TX Vref Scan disable
7750 22:58:40.170213 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7751 22:58:40.170296 == TX Byte 0 ==
7752 22:58:40.173583 u2DelayCellOfst[0]=13 cells (4 PI)
7753 22:58:40.176832 u2DelayCellOfst[1]=16 cells (5 PI)
7754 22:58:40.180276 u2DelayCellOfst[2]=10 cells (3 PI)
7755 22:58:40.183760 u2DelayCellOfst[3]=13 cells (4 PI)
7756 22:58:40.186673 u2DelayCellOfst[4]=6 cells (2 PI)
7757 22:58:40.190154 u2DelayCellOfst[5]=0 cells (0 PI)
7758 22:58:40.193521 u2DelayCellOfst[6]=16 cells (5 PI)
7759 22:58:40.196933 u2DelayCellOfst[7]=16 cells (5 PI)
7760 22:58:40.199913 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7761 22:58:40.203448 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7762 22:58:40.206539 == TX Byte 1 ==
7763 22:58:40.210005 u2DelayCellOfst[8]=0 cells (0 PI)
7764 22:58:40.213185 u2DelayCellOfst[9]=0 cells (0 PI)
7765 22:58:40.216467 u2DelayCellOfst[10]=10 cells (3 PI)
7766 22:58:40.220006 u2DelayCellOfst[11]=3 cells (1 PI)
7767 22:58:40.220119 u2DelayCellOfst[12]=10 cells (3 PI)
7768 22:58:40.223019 u2DelayCellOfst[13]=10 cells (3 PI)
7769 22:58:40.226289 u2DelayCellOfst[14]=13 cells (4 PI)
7770 22:58:40.229813 u2DelayCellOfst[15]=10 cells (3 PI)
7771 22:58:40.236279 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7772 22:58:40.239605 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7773 22:58:40.239688 DramC Write-DBI on
7774 22:58:40.242873 ==
7775 22:58:40.242955 Dram Type= 6, Freq= 0, CH_0, rank 0
7776 22:58:40.249452 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7777 22:58:40.249561 ==
7778 22:58:40.249659
7779 22:58:40.249747
7780 22:58:40.252907 TX Vref Scan disable
7781 22:58:40.252990 == TX Byte 0 ==
7782 22:58:40.259490 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7783 22:58:40.259574 == TX Byte 1 ==
7784 22:58:40.262537 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7785 22:58:40.266029 DramC Write-DBI off
7786 22:58:40.266112
7787 22:58:40.266177 [DATLAT]
7788 22:58:40.269403 Freq=1600, CH0 RK0
7789 22:58:40.269487
7790 22:58:40.269553 DATLAT Default: 0xf
7791 22:58:40.272688 0, 0xFFFF, sum = 0
7792 22:58:40.272812 1, 0xFFFF, sum = 0
7793 22:58:40.275796 2, 0xFFFF, sum = 0
7794 22:58:40.275880 3, 0xFFFF, sum = 0
7795 22:58:40.279375 4, 0xFFFF, sum = 0
7796 22:58:40.279461 5, 0xFFFF, sum = 0
7797 22:58:40.282549 6, 0xFFFF, sum = 0
7798 22:58:40.285830 7, 0xFFFF, sum = 0
7799 22:58:40.285917 8, 0xFFFF, sum = 0
7800 22:58:40.289109 9, 0xFFFF, sum = 0
7801 22:58:40.289195 10, 0xFFFF, sum = 0
7802 22:58:40.292496 11, 0xFFFF, sum = 0
7803 22:58:40.292581 12, 0xFFFF, sum = 0
7804 22:58:40.295925 13, 0xFFFF, sum = 0
7805 22:58:40.296011 14, 0x0, sum = 1
7806 22:58:40.299055 15, 0x0, sum = 2
7807 22:58:40.299141 16, 0x0, sum = 3
7808 22:58:40.302340 17, 0x0, sum = 4
7809 22:58:40.302431 best_step = 15
7810 22:58:40.302499
7811 22:58:40.302562 ==
7812 22:58:40.305797 Dram Type= 6, Freq= 0, CH_0, rank 0
7813 22:58:40.309164 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7814 22:58:40.312587 ==
7815 22:58:40.312671 RX Vref Scan: 1
7816 22:58:40.312739
7817 22:58:40.315522 Set Vref Range= 24 -> 127
7818 22:58:40.315606
7819 22:58:40.318965 RX Vref 24 -> 127, step: 1
7820 22:58:40.319050
7821 22:58:40.319117 RX Delay 19 -> 252, step: 4
7822 22:58:40.319182
7823 22:58:40.322422 Set Vref, RX VrefLevel [Byte0]: 24
7824 22:58:40.325275 [Byte1]: 24
7825 22:58:40.329106
7826 22:58:40.329191 Set Vref, RX VrefLevel [Byte0]: 25
7827 22:58:40.332477 [Byte1]: 25
7828 22:58:40.336860
7829 22:58:40.336945 Set Vref, RX VrefLevel [Byte0]: 26
7830 22:58:40.340315 [Byte1]: 26
7831 22:58:40.344082
7832 22:58:40.344167 Set Vref, RX VrefLevel [Byte0]: 27
7833 22:58:40.347710 [Byte1]: 27
7834 22:58:40.351890
7835 22:58:40.351973 Set Vref, RX VrefLevel [Byte0]: 28
7836 22:58:40.355345 [Byte1]: 28
7837 22:58:40.359490
7838 22:58:40.359576 Set Vref, RX VrefLevel [Byte0]: 29
7839 22:58:40.362848 [Byte1]: 29
7840 22:58:40.367002
7841 22:58:40.367086 Set Vref, RX VrefLevel [Byte0]: 30
7842 22:58:40.370439 [Byte1]: 30
7843 22:58:40.374740
7844 22:58:40.374825 Set Vref, RX VrefLevel [Byte0]: 31
7845 22:58:40.377973 [Byte1]: 31
7846 22:58:40.382464
7847 22:58:40.382549 Set Vref, RX VrefLevel [Byte0]: 32
7848 22:58:40.385355 [Byte1]: 32
7849 22:58:40.389728
7850 22:58:40.389814 Set Vref, RX VrefLevel [Byte0]: 33
7851 22:58:40.392791 [Byte1]: 33
7852 22:58:40.397295
7853 22:58:40.397407 Set Vref, RX VrefLevel [Byte0]: 34
7854 22:58:40.400650 [Byte1]: 34
7855 22:58:40.404741
7856 22:58:40.404830 Set Vref, RX VrefLevel [Byte0]: 35
7857 22:58:40.408401 [Byte1]: 35
7858 22:58:40.412442
7859 22:58:40.412540 Set Vref, RX VrefLevel [Byte0]: 36
7860 22:58:40.415826 [Byte1]: 36
7861 22:58:40.420114
7862 22:58:40.420189 Set Vref, RX VrefLevel [Byte0]: 37
7863 22:58:40.423520 [Byte1]: 37
7864 22:58:40.427711
7865 22:58:40.427826 Set Vref, RX VrefLevel [Byte0]: 38
7866 22:58:40.431105 [Byte1]: 38
7867 22:58:40.435093
7868 22:58:40.435165 Set Vref, RX VrefLevel [Byte0]: 39
7869 22:58:40.438235 [Byte1]: 39
7870 22:58:40.442656
7871 22:58:40.442760 Set Vref, RX VrefLevel [Byte0]: 40
7872 22:58:40.446163 [Byte1]: 40
7873 22:58:40.450308
7874 22:58:40.450414 Set Vref, RX VrefLevel [Byte0]: 41
7875 22:58:40.453800 [Byte1]: 41
7876 22:58:40.457845
7877 22:58:40.457919 Set Vref, RX VrefLevel [Byte0]: 42
7878 22:58:40.461308 [Byte1]: 42
7879 22:58:40.465313
7880 22:58:40.465395 Set Vref, RX VrefLevel [Byte0]: 43
7881 22:58:40.468479 [Byte1]: 43
7882 22:58:40.472913
7883 22:58:40.472991 Set Vref, RX VrefLevel [Byte0]: 44
7884 22:58:40.476427 [Byte1]: 44
7885 22:58:40.480714
7886 22:58:40.480840 Set Vref, RX VrefLevel [Byte0]: 45
7887 22:58:40.483866 [Byte1]: 45
7888 22:58:40.488239
7889 22:58:40.488337 Set Vref, RX VrefLevel [Byte0]: 46
7890 22:58:40.491492 [Byte1]: 46
7891 22:58:40.495715
7892 22:58:40.495811 Set Vref, RX VrefLevel [Byte0]: 47
7893 22:58:40.499230 [Byte1]: 47
7894 22:58:40.503165
7895 22:58:40.503236 Set Vref, RX VrefLevel [Byte0]: 48
7896 22:58:40.506513 [Byte1]: 48
7897 22:58:40.510773
7898 22:58:40.510882 Set Vref, RX VrefLevel [Byte0]: 49
7899 22:58:40.514262 [Byte1]: 49
7900 22:58:40.518216
7901 22:58:40.518315 Set Vref, RX VrefLevel [Byte0]: 50
7902 22:58:40.521645 [Byte1]: 50
7903 22:58:40.525974
7904 22:58:40.526044 Set Vref, RX VrefLevel [Byte0]: 51
7905 22:58:40.529484 [Byte1]: 51
7906 22:58:40.533459
7907 22:58:40.533566 Set Vref, RX VrefLevel [Byte0]: 52
7908 22:58:40.536715 [Byte1]: 52
7909 22:58:40.541209
7910 22:58:40.541278 Set Vref, RX VrefLevel [Byte0]: 53
7911 22:58:40.544535 [Byte1]: 53
7912 22:58:40.548518
7913 22:58:40.548614 Set Vref, RX VrefLevel [Byte0]: 54
7914 22:58:40.551918 [Byte1]: 54
7915 22:58:40.556470
7916 22:58:40.556573 Set Vref, RX VrefLevel [Byte0]: 55
7917 22:58:40.559900 [Byte1]: 55
7918 22:58:40.563804
7919 22:58:40.563875 Set Vref, RX VrefLevel [Byte0]: 56
7920 22:58:40.567053 [Byte1]: 56
7921 22:58:40.571409
7922 22:58:40.571522 Set Vref, RX VrefLevel [Byte0]: 57
7923 22:58:40.574894 [Byte1]: 57
7924 22:58:40.579348
7925 22:58:40.579429 Set Vref, RX VrefLevel [Byte0]: 58
7926 22:58:40.582148 [Byte1]: 58
7927 22:58:40.586817
7928 22:58:40.586899 Set Vref, RX VrefLevel [Byte0]: 59
7929 22:58:40.589846 [Byte1]: 59
7930 22:58:40.594109
7931 22:58:40.594236 Set Vref, RX VrefLevel [Byte0]: 60
7932 22:58:40.597638 [Byte1]: 60
7933 22:58:40.601744
7934 22:58:40.601907 Set Vref, RX VrefLevel [Byte0]: 61
7935 22:58:40.605112 [Byte1]: 61
7936 22:58:40.609132
7937 22:58:40.609213 Set Vref, RX VrefLevel [Byte0]: 62
7938 22:58:40.612473 [Byte1]: 62
7939 22:58:40.616920
7940 22:58:40.617003 Set Vref, RX VrefLevel [Byte0]: 63
7941 22:58:40.620440 [Byte1]: 63
7942 22:58:40.624373
7943 22:58:40.624482 Set Vref, RX VrefLevel [Byte0]: 64
7944 22:58:40.627813 [Byte1]: 64
7945 22:58:40.632065
7946 22:58:40.632165 Set Vref, RX VrefLevel [Byte0]: 65
7947 22:58:40.635550 [Byte1]: 65
7948 22:58:40.639590
7949 22:58:40.639672 Set Vref, RX VrefLevel [Byte0]: 66
7950 22:58:40.643205 [Byte1]: 66
7951 22:58:40.647226
7952 22:58:40.647336 Set Vref, RX VrefLevel [Byte0]: 67
7953 22:58:40.650373 [Byte1]: 67
7954 22:58:40.654882
7955 22:58:40.654964 Set Vref, RX VrefLevel [Byte0]: 68
7956 22:58:40.661290 [Byte1]: 68
7957 22:58:40.661373
7958 22:58:40.664586 Set Vref, RX VrefLevel [Byte0]: 69
7959 22:58:40.668017 [Byte1]: 69
7960 22:58:40.668099
7961 22:58:40.671061 Set Vref, RX VrefLevel [Byte0]: 70
7962 22:58:40.674551 [Byte1]: 70
7963 22:58:40.674634
7964 22:58:40.677805 Set Vref, RX VrefLevel [Byte0]: 71
7965 22:58:40.681320 [Byte1]: 71
7966 22:58:40.685431
7967 22:58:40.685514 Set Vref, RX VrefLevel [Byte0]: 72
7968 22:58:40.688499 [Byte1]: 72
7969 22:58:40.692867
7970 22:58:40.692959 Set Vref, RX VrefLevel [Byte0]: 73
7971 22:58:40.696226 [Byte1]: 73
7972 22:58:40.700138
7973 22:58:40.700248 Set Vref, RX VrefLevel [Byte0]: 74
7974 22:58:40.703618 [Byte1]: 74
7975 22:58:40.708066
7976 22:58:40.708167 Set Vref, RX VrefLevel [Byte0]: 75
7977 22:58:40.711028 [Byte1]: 75
7978 22:58:40.715392
7979 22:58:40.715475 Set Vref, RX VrefLevel [Byte0]: 76
7980 22:58:40.718584 [Byte1]: 76
7981 22:58:40.723014
7982 22:58:40.723116 Set Vref, RX VrefLevel [Byte0]: 77
7983 22:58:40.726165 [Byte1]: 77
7984 22:58:40.730439
7985 22:58:40.730521 Set Vref, RX VrefLevel [Byte0]: 78
7986 22:58:40.733918 [Byte1]: 78
7987 22:58:40.738273
7988 22:58:40.738355 Set Vref, RX VrefLevel [Byte0]: 79
7989 22:58:40.741648 [Byte1]: 79
7990 22:58:40.745523
7991 22:58:40.745605 Set Vref, RX VrefLevel [Byte0]: 80
7992 22:58:40.749217 [Byte1]: 80
7993 22:58:40.753200
7994 22:58:40.753304 Final RX Vref Byte 0 = 62 to rank0
7995 22:58:40.756516 Final RX Vref Byte 1 = 61 to rank0
7996 22:58:40.759891 Final RX Vref Byte 0 = 62 to rank1
7997 22:58:40.763135 Final RX Vref Byte 1 = 61 to rank1==
7998 22:58:40.766162 Dram Type= 6, Freq= 0, CH_0, rank 0
7999 22:58:40.772850 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8000 22:58:40.772960 ==
8001 22:58:40.773055 DQS Delay:
8002 22:58:40.776367 DQS0 = 0, DQS1 = 0
8003 22:58:40.776464 DQM Delay:
8004 22:58:40.776584 DQM0 = 136, DQM1 = 124
8005 22:58:40.779424 DQ Delay:
8006 22:58:40.783172 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =134
8007 22:58:40.786069 DQ4 =140, DQ5 =126, DQ6 =144, DQ7 =144
8008 22:58:40.789521 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =118
8009 22:58:40.792693 DQ12 =130, DQ13 =128, DQ14 =136, DQ15 =132
8010 22:58:40.792834
8011 22:58:40.792932
8012 22:58:40.792998
8013 22:58:40.796058 [DramC_TX_OE_Calibration] TA2
8014 22:58:40.799505 Original DQ_B0 (3 6) =30, OEN = 27
8015 22:58:40.802383 Original DQ_B1 (3 6) =30, OEN = 27
8016 22:58:40.805803 24, 0x0, End_B0=24 End_B1=24
8017 22:58:40.809035 25, 0x0, End_B0=25 End_B1=25
8018 22:58:40.809119 26, 0x0, End_B0=26 End_B1=26
8019 22:58:40.812317 27, 0x0, End_B0=27 End_B1=27
8020 22:58:40.815608 28, 0x0, End_B0=28 End_B1=28
8021 22:58:40.818989 29, 0x0, End_B0=29 End_B1=29
8022 22:58:40.819104 30, 0x0, End_B0=30 End_B1=30
8023 22:58:40.822319 31, 0x4141, End_B0=30 End_B1=30
8024 22:58:40.825826 Byte0 end_step=30 best_step=27
8025 22:58:40.829162 Byte1 end_step=30 best_step=27
8026 22:58:40.832080 Byte0 TX OE(2T, 0.5T) = (3, 3)
8027 22:58:40.835483 Byte1 TX OE(2T, 0.5T) = (3, 3)
8028 22:58:40.835567
8029 22:58:40.835631
8030 22:58:40.842100 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b19, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
8031 22:58:40.845508 CH0 RK0: MR19=303, MR18=1B19
8032 22:58:40.852258 CH0_RK0: MR19=0x303, MR18=0x1B19, DQSOSC=396, MR23=63, INC=23, DEC=15
8033 22:58:40.852343
8034 22:58:40.855463 ----->DramcWriteLeveling(PI) begin...
8035 22:58:40.855574 ==
8036 22:58:40.858619 Dram Type= 6, Freq= 0, CH_0, rank 1
8037 22:58:40.861958 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8038 22:58:40.862043 ==
8039 22:58:40.865266 Write leveling (Byte 0): 39 => 39
8040 22:58:40.868543 Write leveling (Byte 1): 30 => 30
8041 22:58:40.872016 DramcWriteLeveling(PI) end<-----
8042 22:58:40.872100
8043 22:58:40.872182 ==
8044 22:58:40.875500 Dram Type= 6, Freq= 0, CH_0, rank 1
8045 22:58:40.878604 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8046 22:58:40.881863 ==
8047 22:58:40.881947 [Gating] SW mode calibration
8048 22:58:40.891507 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8049 22:58:40.894768 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8050 22:58:40.898405 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8051 22:58:40.905129 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8052 22:58:40.908230 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8053 22:58:40.911361 1 4 12 | B1->B0 | 2424 3131 | 1 0 | (0 0) (0 0)
8054 22:58:40.917949 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8055 22:58:40.921367 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8056 22:58:40.924634 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8057 22:58:40.930996 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8058 22:58:40.934478 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8059 22:58:40.938053 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8060 22:58:40.944326 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8061 22:58:40.947847 1 5 12 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (1 0)
8062 22:58:40.951223 1 5 16 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
8063 22:58:40.957479 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8064 22:58:40.960941 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8065 22:58:40.964052 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8066 22:58:40.970533 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8067 22:58:40.974291 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8068 22:58:40.977186 1 6 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
8069 22:58:40.984002 1 6 12 | B1->B0 | 3030 4545 | 0 0 | (0 0) (0 0)
8070 22:58:40.987389 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8071 22:58:40.990552 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8072 22:58:40.997461 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8073 22:58:41.000738 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8074 22:58:41.004053 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8075 22:58:41.010303 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8076 22:58:41.014197 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8077 22:58:41.017006 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8078 22:58:41.023620 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8079 22:58:41.026951 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 22:58:41.030217 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 22:58:41.037125 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 22:58:41.040488 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 22:58:41.043585 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 22:58:41.050487 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 22:58:41.053456 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 22:58:41.056939 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 22:58:41.063300 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 22:58:41.067108 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 22:58:41.070154 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 22:58:41.076809 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 22:58:41.080227 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 22:58:41.083554 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8093 22:58:41.090021 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8094 22:58:41.093250 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8095 22:58:41.096657 Total UI for P1: 0, mck2ui 16
8096 22:58:41.099800 best dqsien dly found for B0: ( 1, 9, 10)
8097 22:58:41.103247 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8098 22:58:41.106319 Total UI for P1: 0, mck2ui 16
8099 22:58:41.109541 best dqsien dly found for B1: ( 1, 9, 14)
8100 22:58:41.112937 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8101 22:58:41.116295 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8102 22:58:41.116416
8103 22:58:41.123040 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8104 22:58:41.126491 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8105 22:58:41.126568 [Gating] SW calibration Done
8106 22:58:41.129490 ==
8107 22:58:41.132819 Dram Type= 6, Freq= 0, CH_0, rank 1
8108 22:58:41.136117 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8109 22:58:41.136193 ==
8110 22:58:41.136263 RX Vref Scan: 0
8111 22:58:41.136340
8112 22:58:41.139620 RX Vref 0 -> 0, step: 1
8113 22:58:41.139723
8114 22:58:41.143039 RX Delay 0 -> 252, step: 8
8115 22:58:41.146062 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8116 22:58:41.149686 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8117 22:58:41.152706 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8118 22:58:41.159176 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8119 22:58:41.162747 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8120 22:58:41.165760 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8121 22:58:41.169315 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8122 22:58:41.172664 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8123 22:58:41.179059 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8124 22:58:41.182401 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8125 22:58:41.185704 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8126 22:58:41.188784 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8127 22:58:41.195575 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8128 22:58:41.198893 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8129 22:58:41.202065 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8130 22:58:41.205390 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8131 22:58:41.205474 ==
8132 22:58:41.208869 Dram Type= 6, Freq= 0, CH_0, rank 1
8133 22:58:41.215437 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8134 22:58:41.215526 ==
8135 22:58:41.215593 DQS Delay:
8136 22:58:41.218458 DQS0 = 0, DQS1 = 0
8137 22:58:41.218538 DQM Delay:
8138 22:58:41.218611 DQM0 = 136, DQM1 = 125
8139 22:58:41.222039 DQ Delay:
8140 22:58:41.224982 DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131
8141 22:58:41.228300 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8142 22:58:41.231597 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8143 22:58:41.234981 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8144 22:58:41.235057
8145 22:58:41.235137
8146 22:58:41.235207 ==
8147 22:58:41.238311 Dram Type= 6, Freq= 0, CH_0, rank 1
8148 22:58:41.244933 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8149 22:58:41.245015 ==
8150 22:58:41.245088
8151 22:58:41.245150
8152 22:58:41.245228 TX Vref Scan disable
8153 22:58:41.248423 == TX Byte 0 ==
8154 22:58:41.251494 Update DQ dly =995 (3 ,6, 35) DQ OEN =(3 ,3)
8155 22:58:41.254991 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8156 22:58:41.258129 == TX Byte 1 ==
8157 22:58:41.261591 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8158 22:58:41.268463 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8159 22:58:41.268574 ==
8160 22:58:41.271859 Dram Type= 6, Freq= 0, CH_0, rank 1
8161 22:58:41.274832 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8162 22:58:41.274917 ==
8163 22:58:41.288248
8164 22:58:41.291535 TX Vref early break, caculate TX vref
8165 22:58:41.295066 TX Vref=16, minBit 8, minWin=22, winSum=387
8166 22:58:41.298341 TX Vref=18, minBit 0, minWin=24, winSum=396
8167 22:58:41.301642 TX Vref=20, minBit 8, minWin=24, winSum=406
8168 22:58:41.304616 TX Vref=22, minBit 0, minWin=25, winSum=415
8169 22:58:41.308138 TX Vref=24, minBit 2, minWin=25, winSum=424
8170 22:58:41.314808 TX Vref=26, minBit 0, minWin=26, winSum=432
8171 22:58:41.318142 TX Vref=28, minBit 0, minWin=26, winSum=432
8172 22:58:41.321299 TX Vref=30, minBit 1, minWin=26, winSum=429
8173 22:58:41.324629 TX Vref=32, minBit 0, minWin=25, winSum=421
8174 22:58:41.328177 TX Vref=34, minBit 0, minWin=25, winSum=409
8175 22:58:41.334378 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 26
8176 22:58:41.334477
8177 22:58:41.337853 Final TX Range 0 Vref 26
8178 22:58:41.337937
8179 22:58:41.338001 ==
8180 22:58:41.341121 Dram Type= 6, Freq= 0, CH_0, rank 1
8181 22:58:41.344445 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8182 22:58:41.344557 ==
8183 22:58:41.344653
8184 22:58:41.344756
8185 22:58:41.347993 TX Vref Scan disable
8186 22:58:41.354471 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8187 22:58:41.354556 == TX Byte 0 ==
8188 22:58:41.357431 u2DelayCellOfst[0]=13 cells (4 PI)
8189 22:58:41.360850 u2DelayCellOfst[1]=20 cells (6 PI)
8190 22:58:41.363913 u2DelayCellOfst[2]=13 cells (4 PI)
8191 22:58:41.367556 u2DelayCellOfst[3]=13 cells (4 PI)
8192 22:58:41.370922 u2DelayCellOfst[4]=10 cells (3 PI)
8193 22:58:41.373951 u2DelayCellOfst[5]=0 cells (0 PI)
8194 22:58:41.377458 u2DelayCellOfst[6]=16 cells (5 PI)
8195 22:58:41.380742 u2DelayCellOfst[7]=16 cells (5 PI)
8196 22:58:41.384155 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8197 22:58:41.387064 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8198 22:58:41.390506 == TX Byte 1 ==
8199 22:58:41.393854 u2DelayCellOfst[8]=0 cells (0 PI)
8200 22:58:41.397147 u2DelayCellOfst[9]=0 cells (0 PI)
8201 22:58:41.400483 u2DelayCellOfst[10]=6 cells (2 PI)
8202 22:58:41.400583 u2DelayCellOfst[11]=3 cells (1 PI)
8203 22:58:41.403938 u2DelayCellOfst[12]=13 cells (4 PI)
8204 22:58:41.407124 u2DelayCellOfst[13]=13 cells (4 PI)
8205 22:58:41.410330 u2DelayCellOfst[14]=13 cells (4 PI)
8206 22:58:41.413797 u2DelayCellOfst[15]=10 cells (3 PI)
8207 22:58:41.420172 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8208 22:58:41.423453 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8209 22:58:41.423537 DramC Write-DBI on
8210 22:58:41.426677 ==
8211 22:58:41.426826 Dram Type= 6, Freq= 0, CH_0, rank 1
8212 22:58:41.433435 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8213 22:58:41.433535 ==
8214 22:58:41.433616
8215 22:58:41.433709
8216 22:58:41.436544 TX Vref Scan disable
8217 22:58:41.436652 == TX Byte 0 ==
8218 22:58:41.443249 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8219 22:58:41.443332 == TX Byte 1 ==
8220 22:58:41.446505 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8221 22:58:41.449991 DramC Write-DBI off
8222 22:58:41.450076
8223 22:58:41.450160 [DATLAT]
8224 22:58:41.453566 Freq=1600, CH0 RK1
8225 22:58:41.453651
8226 22:58:41.453734 DATLAT Default: 0xf
8227 22:58:41.456491 0, 0xFFFF, sum = 0
8228 22:58:41.456577 1, 0xFFFF, sum = 0
8229 22:58:41.459881 2, 0xFFFF, sum = 0
8230 22:58:41.459967 3, 0xFFFF, sum = 0
8231 22:58:41.463351 4, 0xFFFF, sum = 0
8232 22:58:41.463437 5, 0xFFFF, sum = 0
8233 22:58:41.466342 6, 0xFFFF, sum = 0
8234 22:58:41.466427 7, 0xFFFF, sum = 0
8235 22:58:41.470005 8, 0xFFFF, sum = 0
8236 22:58:41.473196 9, 0xFFFF, sum = 0
8237 22:58:41.473307 10, 0xFFFF, sum = 0
8238 22:58:41.476152 11, 0xFFFF, sum = 0
8239 22:58:41.476256 12, 0xFFFF, sum = 0
8240 22:58:41.479633 13, 0xFFFF, sum = 0
8241 22:58:41.479707 14, 0x0, sum = 1
8242 22:58:41.483039 15, 0x0, sum = 2
8243 22:58:41.483124 16, 0x0, sum = 3
8244 22:58:41.486518 17, 0x0, sum = 4
8245 22:58:41.486604 best_step = 15
8246 22:58:41.486688
8247 22:58:41.486766 ==
8248 22:58:41.489839 Dram Type= 6, Freq= 0, CH_0, rank 1
8249 22:58:41.492681 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8250 22:58:41.496001 ==
8251 22:58:41.496085 RX Vref Scan: 0
8252 22:58:41.496169
8253 22:58:41.499455 RX Vref 0 -> 0, step: 1
8254 22:58:41.499540
8255 22:58:41.499623 RX Delay 11 -> 252, step: 4
8256 22:58:41.506787 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8257 22:58:41.510119 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8258 22:58:41.513139 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8259 22:58:41.516586 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8260 22:58:41.523293 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8261 22:58:41.526291 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8262 22:58:41.529572 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8263 22:58:41.533118 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8264 22:58:41.536444 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8265 22:58:41.539777 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8266 22:58:41.546573 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8267 22:58:41.549734 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8268 22:58:41.552966 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8269 22:58:41.556371 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8270 22:58:41.562958 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8271 22:58:41.566344 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8272 22:58:41.566452 ==
8273 22:58:41.569776 Dram Type= 6, Freq= 0, CH_0, rank 1
8274 22:58:41.573181 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8275 22:58:41.573264 ==
8276 22:58:41.576080 DQS Delay:
8277 22:58:41.576177 DQS0 = 0, DQS1 = 0
8278 22:58:41.576283 DQM Delay:
8279 22:58:41.579593 DQM0 = 133, DQM1 = 123
8280 22:58:41.579677 DQ Delay:
8281 22:58:41.582456 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =130
8282 22:58:41.585941 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =140
8283 22:58:41.592666 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8284 22:58:41.596041 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8285 22:58:41.596137
8286 22:58:41.596313
8287 22:58:41.596460
8288 22:58:41.599086 [DramC_TX_OE_Calibration] TA2
8289 22:58:41.602309 Original DQ_B0 (3 6) =30, OEN = 27
8290 22:58:41.602391 Original DQ_B1 (3 6) =30, OEN = 27
8291 22:58:41.605826 24, 0x0, End_B0=24 End_B1=24
8292 22:58:41.608859 25, 0x0, End_B0=25 End_B1=25
8293 22:58:41.612388 26, 0x0, End_B0=26 End_B1=26
8294 22:58:41.616007 27, 0x0, End_B0=27 End_B1=27
8295 22:58:41.616092 28, 0x0, End_B0=28 End_B1=28
8296 22:58:41.618774 29, 0x0, End_B0=29 End_B1=29
8297 22:58:41.622203 30, 0x0, End_B0=30 End_B1=30
8298 22:58:41.626176 31, 0x5151, End_B0=30 End_B1=30
8299 22:58:41.628930 Byte0 end_step=30 best_step=27
8300 22:58:41.632305 Byte1 end_step=30 best_step=27
8301 22:58:41.632511 Byte0 TX OE(2T, 0.5T) = (3, 3)
8302 22:58:41.635331 Byte1 TX OE(2T, 0.5T) = (3, 3)
8303 22:58:41.635428
8304 22:58:41.635523
8305 22:58:41.645388 [DQSOSCAuto] RK1, (LSB)MR18= 0x200d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
8306 22:58:41.648802 CH0 RK1: MR19=303, MR18=200D
8307 22:58:41.651695 CH0_RK1: MR19=0x303, MR18=0x200D, DQSOSC=393, MR23=63, INC=23, DEC=15
8308 22:58:41.655034 [RxdqsGatingPostProcess] freq 1600
8309 22:58:41.661710 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8310 22:58:41.665184 best DQS0 dly(2T, 0.5T) = (1, 1)
8311 22:58:41.668536 best DQS1 dly(2T, 0.5T) = (1, 1)
8312 22:58:41.671907 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8313 22:58:41.674978 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8314 22:58:41.678438 best DQS0 dly(2T, 0.5T) = (1, 1)
8315 22:58:41.681507 best DQS1 dly(2T, 0.5T) = (1, 1)
8316 22:58:41.684865 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8317 22:58:41.684948 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8318 22:58:41.688316 Pre-setting of DQS Precalculation
8319 22:58:41.694791 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8320 22:58:41.694876 ==
8321 22:58:41.698254 Dram Type= 6, Freq= 0, CH_1, rank 0
8322 22:58:41.701541 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8323 22:58:41.701656 ==
8324 22:58:41.707839 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8325 22:58:41.711441 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8326 22:58:41.714522 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8327 22:58:41.721024 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8328 22:58:41.731039 [CA 0] Center 40 (11~70) winsize 60
8329 22:58:41.733994 [CA 1] Center 41 (11~71) winsize 61
8330 22:58:41.737337 [CA 2] Center 37 (8~67) winsize 60
8331 22:58:41.740882 [CA 3] Center 36 (7~66) winsize 60
8332 22:58:41.744119 [CA 4] Center 36 (7~66) winsize 60
8333 22:58:41.747415 [CA 5] Center 36 (6~66) winsize 61
8334 22:58:41.747501
8335 22:58:41.750838 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8336 22:58:41.750922
8337 22:58:41.757487 [CATrainingPosCal] consider 1 rank data
8338 22:58:41.757571 u2DelayCellTimex100 = 290/100 ps
8339 22:58:41.763673 CA0 delay=40 (11~70),Diff = 4 PI (13 cell)
8340 22:58:41.767108 CA1 delay=41 (11~71),Diff = 5 PI (16 cell)
8341 22:58:41.770609 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8342 22:58:41.773613 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8343 22:58:41.777074 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8344 22:58:41.780158 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8345 22:58:41.780241
8346 22:58:41.783531 CA PerBit enable=1, Macro0, CA PI delay=36
8347 22:58:41.783613
8348 22:58:41.786901 [CBTSetCACLKResult] CA Dly = 36
8349 22:58:41.789978 CS Dly: 9 (0~40)
8350 22:58:41.793363 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8351 22:58:41.796702 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8352 22:58:41.796823 ==
8353 22:58:41.800094 Dram Type= 6, Freq= 0, CH_1, rank 1
8354 22:58:41.806424 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8355 22:58:41.806507 ==
8356 22:58:41.809959 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8357 22:58:41.816345 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8358 22:58:41.819593 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8359 22:58:41.826561 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8360 22:58:41.834074 [CA 0] Center 42 (13~72) winsize 60
8361 22:58:41.837263 [CA 1] Center 42 (13~72) winsize 60
8362 22:58:41.840904 [CA 2] Center 38 (9~68) winsize 60
8363 22:58:41.844088 [CA 3] Center 37 (8~67) winsize 60
8364 22:58:41.847332 [CA 4] Center 38 (9~67) winsize 59
8365 22:58:41.850386 [CA 5] Center 37 (8~67) winsize 60
8366 22:58:41.850493
8367 22:58:41.853818 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8368 22:58:41.853915
8369 22:58:41.857345 [CATrainingPosCal] consider 2 rank data
8370 22:58:41.860622 u2DelayCellTimex100 = 290/100 ps
8371 22:58:41.864138 CA0 delay=41 (13~70),Diff = 4 PI (13 cell)
8372 22:58:41.870597 CA1 delay=42 (13~71),Diff = 5 PI (16 cell)
8373 22:58:41.873533 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8374 22:58:41.877037 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8375 22:58:41.880488 CA4 delay=37 (9~66),Diff = 0 PI (0 cell)
8376 22:58:41.883550 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8377 22:58:41.883651
8378 22:58:41.887141 CA PerBit enable=1, Macro0, CA PI delay=37
8379 22:58:41.887256
8380 22:58:41.890567 [CBTSetCACLKResult] CA Dly = 37
8381 22:58:41.893604 CS Dly: 10 (0~42)
8382 22:58:41.897156 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8383 22:58:41.900487 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8384 22:58:41.900569
8385 22:58:41.903584 ----->DramcWriteLeveling(PI) begin...
8386 22:58:41.903667 ==
8387 22:58:41.906751 Dram Type= 6, Freq= 0, CH_1, rank 0
8388 22:58:41.913476 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8389 22:58:41.913559 ==
8390 22:58:41.916709 Write leveling (Byte 0): 25 => 25
8391 22:58:41.916828 Write leveling (Byte 1): 28 => 28
8392 22:58:41.920299 DramcWriteLeveling(PI) end<-----
8393 22:58:41.920417
8394 22:58:41.920491 ==
8395 22:58:41.923743 Dram Type= 6, Freq= 0, CH_1, rank 0
8396 22:58:41.930131 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8397 22:58:41.930209 ==
8398 22:58:41.933544 [Gating] SW mode calibration
8399 22:58:41.940280 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8400 22:58:41.943664 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8401 22:58:41.950024 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8402 22:58:41.953658 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8403 22:58:41.956786 1 4 8 | B1->B0 | 2626 2c2c | 0 0 | (0 0) (0 0)
8404 22:58:41.963186 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8405 22:58:41.966735 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8406 22:58:41.970040 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8407 22:58:41.976338 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8408 22:58:41.979675 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8409 22:58:41.983174 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8410 22:58:41.989643 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8411 22:58:41.993145 1 5 8 | B1->B0 | 3232 2a2a | 0 0 | (0 0) (1 0)
8412 22:58:41.996110 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8413 22:58:42.002888 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8414 22:58:42.006243 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8415 22:58:42.009584 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8416 22:58:42.012831 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8417 22:58:42.019764 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8418 22:58:42.023220 1 6 4 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
8419 22:58:42.026449 1 6 8 | B1->B0 | 3a3a 3f3f | 0 0 | (0 0) (0 0)
8420 22:58:42.032884 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8421 22:58:42.036204 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8422 22:58:42.039487 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8423 22:58:42.045955 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8424 22:58:42.049449 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8425 22:58:42.052880 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8426 22:58:42.059206 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8427 22:58:42.062546 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8428 22:58:42.065792 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8429 22:58:42.072692 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 22:58:42.075826 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 22:58:42.079019 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 22:58:42.086156 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 22:58:42.089147 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 22:58:42.092579 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 22:58:42.099202 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 22:58:42.102276 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 22:58:42.105799 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 22:58:42.112423 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 22:58:42.115638 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 22:58:42.119194 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 22:58:42.125549 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 22:58:42.129197 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 22:58:42.132190 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8444 22:58:42.138650 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8445 22:58:42.138734 Total UI for P1: 0, mck2ui 16
8446 22:58:42.145437 best dqsien dly found for B0: ( 1, 9, 8)
8447 22:58:42.148649 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8448 22:58:42.151716 Total UI for P1: 0, mck2ui 16
8449 22:58:42.155354 best dqsien dly found for B1: ( 1, 9, 12)
8450 22:58:42.158806 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8451 22:58:42.162147 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8452 22:58:42.162231
8453 22:58:42.165100 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8454 22:58:42.168566 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8455 22:58:42.171858 [Gating] SW calibration Done
8456 22:58:42.171941 ==
8457 22:58:42.174996 Dram Type= 6, Freq= 0, CH_1, rank 0
8458 22:58:42.181510 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8459 22:58:42.181588 ==
8460 22:58:42.181654 RX Vref Scan: 0
8461 22:58:42.181713
8462 22:58:42.184683 RX Vref 0 -> 0, step: 1
8463 22:58:42.184791
8464 22:58:42.188247 RX Delay 0 -> 252, step: 8
8465 22:58:42.191642 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8466 22:58:42.194784 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8467 22:58:42.198375 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8468 22:58:42.201531 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8469 22:58:42.208103 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8470 22:58:42.211594 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8471 22:58:42.214533 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8472 22:58:42.218212 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8473 22:58:42.221427 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8474 22:58:42.224564 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8475 22:58:42.231419 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8476 22:58:42.234558 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8477 22:58:42.238089 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8478 22:58:42.241498 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8479 22:58:42.247603 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8480 22:58:42.250961 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8481 22:58:42.251045 ==
8482 22:58:42.254466 Dram Type= 6, Freq= 0, CH_1, rank 0
8483 22:58:42.257535 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8484 22:58:42.257620 ==
8485 22:58:42.261092 DQS Delay:
8486 22:58:42.261180 DQS0 = 0, DQS1 = 0
8487 22:58:42.261247 DQM Delay:
8488 22:58:42.264258 DQM0 = 137, DQM1 = 131
8489 22:58:42.264342 DQ Delay:
8490 22:58:42.267571 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =139
8491 22:58:42.270985 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8492 22:58:42.277632 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8493 22:58:42.281004 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8494 22:58:42.281098
8495 22:58:42.281172
8496 22:58:42.281233 ==
8497 22:58:42.283997 Dram Type= 6, Freq= 0, CH_1, rank 0
8498 22:58:42.287423 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8499 22:58:42.287527 ==
8500 22:58:42.287621
8501 22:58:42.287711
8502 22:58:42.290648 TX Vref Scan disable
8503 22:58:42.293850 == TX Byte 0 ==
8504 22:58:42.297084 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8505 22:58:42.300514 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8506 22:58:42.304017 == TX Byte 1 ==
8507 22:58:42.307493 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8508 22:58:42.310550 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8509 22:58:42.310635 ==
8510 22:58:42.313577 Dram Type= 6, Freq= 0, CH_1, rank 0
8511 22:58:42.317026 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8512 22:58:42.320393 ==
8513 22:58:42.331326
8514 22:58:42.334463 TX Vref early break, caculate TX vref
8515 22:58:42.337533 TX Vref=16, minBit 8, minWin=22, winSum=370
8516 22:58:42.341084 TX Vref=18, minBit 10, minWin=21, winSum=380
8517 22:58:42.344055 TX Vref=20, minBit 15, minWin=22, winSum=389
8518 22:58:42.347518 TX Vref=22, minBit 15, minWin=23, winSum=395
8519 22:58:42.354314 TX Vref=24, minBit 10, minWin=23, winSum=405
8520 22:58:42.357633 TX Vref=26, minBit 14, minWin=24, winSum=414
8521 22:58:42.360631 TX Vref=28, minBit 10, minWin=25, winSum=418
8522 22:58:42.364277 TX Vref=30, minBit 8, minWin=25, winSum=414
8523 22:58:42.367621 TX Vref=32, minBit 9, minWin=23, winSum=404
8524 22:58:42.370618 TX Vref=34, minBit 10, minWin=23, winSum=396
8525 22:58:42.377609 [TxChooseVref] Worse bit 10, Min win 25, Win sum 418, Final Vref 28
8526 22:58:42.377692
8527 22:58:42.380871 Final TX Range 0 Vref 28
8528 22:58:42.380987
8529 22:58:42.381085 ==
8530 22:58:42.384038 Dram Type= 6, Freq= 0, CH_1, rank 0
8531 22:58:42.387089 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8532 22:58:42.390391 ==
8533 22:58:42.390497
8534 22:58:42.390598
8535 22:58:42.390689 TX Vref Scan disable
8536 22:58:42.397470 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8537 22:58:42.397583 == TX Byte 0 ==
8538 22:58:42.400646 u2DelayCellOfst[0]=16 cells (5 PI)
8539 22:58:42.403632 u2DelayCellOfst[1]=10 cells (3 PI)
8540 22:58:42.407245 u2DelayCellOfst[2]=0 cells (0 PI)
8541 22:58:42.410717 u2DelayCellOfst[3]=3 cells (1 PI)
8542 22:58:42.413683 u2DelayCellOfst[4]=6 cells (2 PI)
8543 22:58:42.417276 u2DelayCellOfst[5]=16 cells (5 PI)
8544 22:58:42.420283 u2DelayCellOfst[6]=16 cells (5 PI)
8545 22:58:42.423631 u2DelayCellOfst[7]=6 cells (2 PI)
8546 22:58:42.427180 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8547 22:58:42.430388 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8548 22:58:42.433566 == TX Byte 1 ==
8549 22:58:42.436867 u2DelayCellOfst[8]=0 cells (0 PI)
8550 22:58:42.440208 u2DelayCellOfst[9]=3 cells (1 PI)
8551 22:58:42.443545 u2DelayCellOfst[10]=10 cells (3 PI)
8552 22:58:42.447053 u2DelayCellOfst[11]=3 cells (1 PI)
8553 22:58:42.447139 u2DelayCellOfst[12]=16 cells (5 PI)
8554 22:58:42.450238 u2DelayCellOfst[13]=20 cells (6 PI)
8555 22:58:42.453512 u2DelayCellOfst[14]=20 cells (6 PI)
8556 22:58:42.456518 u2DelayCellOfst[15]=20 cells (6 PI)
8557 22:58:42.463266 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8558 22:58:42.466488 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8559 22:58:42.466575 DramC Write-DBI on
8560 22:58:42.470056 ==
8561 22:58:42.473390 Dram Type= 6, Freq= 0, CH_1, rank 0
8562 22:58:42.476890 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8563 22:58:42.476978 ==
8564 22:58:42.477064
8565 22:58:42.477145
8566 22:58:42.479976 TX Vref Scan disable
8567 22:58:42.480089 == TX Byte 0 ==
8568 22:58:42.486429 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8569 22:58:42.486514 == TX Byte 1 ==
8570 22:58:42.489562 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8571 22:58:42.492999 DramC Write-DBI off
8572 22:58:42.493083
8573 22:58:42.493167 [DATLAT]
8574 22:58:42.496381 Freq=1600, CH1 RK0
8575 22:58:42.496490
8576 22:58:42.496592 DATLAT Default: 0xf
8577 22:58:42.499542 0, 0xFFFF, sum = 0
8578 22:58:42.499644 1, 0xFFFF, sum = 0
8579 22:58:42.503171 2, 0xFFFF, sum = 0
8580 22:58:42.503334 3, 0xFFFF, sum = 0
8581 22:58:42.506345 4, 0xFFFF, sum = 0
8582 22:58:42.506445 5, 0xFFFF, sum = 0
8583 22:58:42.509696 6, 0xFFFF, sum = 0
8584 22:58:42.512629 7, 0xFFFF, sum = 0
8585 22:58:42.512752 8, 0xFFFF, sum = 0
8586 22:58:42.515940 9, 0xFFFF, sum = 0
8587 22:58:42.516067 10, 0xFFFF, sum = 0
8588 22:58:42.519529 11, 0xFFFF, sum = 0
8589 22:58:42.519627 12, 0xFFFF, sum = 0
8590 22:58:42.522880 13, 0xFFFF, sum = 0
8591 22:58:42.522950 14, 0x0, sum = 1
8592 22:58:42.525927 15, 0x0, sum = 2
8593 22:58:42.526087 16, 0x0, sum = 3
8594 22:58:42.529172 17, 0x0, sum = 4
8595 22:58:42.529241 best_step = 15
8596 22:58:42.529299
8597 22:58:42.529391 ==
8598 22:58:42.532496 Dram Type= 6, Freq= 0, CH_1, rank 0
8599 22:58:42.536081 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8600 22:58:42.538996 ==
8601 22:58:42.539069 RX Vref Scan: 1
8602 22:58:42.539134
8603 22:58:42.542390 Set Vref Range= 24 -> 127
8604 22:58:42.542460
8605 22:58:42.545767 RX Vref 24 -> 127, step: 1
8606 22:58:42.545844
8607 22:58:42.545906 RX Delay 19 -> 252, step: 4
8608 22:58:42.545965
8609 22:58:42.549202 Set Vref, RX VrefLevel [Byte0]: 24
8610 22:58:42.552030 [Byte1]: 24
8611 22:58:42.555907
8612 22:58:42.555977 Set Vref, RX VrefLevel [Byte0]: 25
8613 22:58:42.559412 [Byte1]: 25
8614 22:58:42.563603
8615 22:58:42.563705 Set Vref, RX VrefLevel [Byte0]: 26
8616 22:58:42.566901 [Byte1]: 26
8617 22:58:42.571271
8618 22:58:42.571382 Set Vref, RX VrefLevel [Byte0]: 27
8619 22:58:42.574722 [Byte1]: 27
8620 22:58:42.578871
8621 22:58:42.578956 Set Vref, RX VrefLevel [Byte0]: 28
8622 22:58:42.582357 [Byte1]: 28
8623 22:58:42.586296
8624 22:58:42.586378 Set Vref, RX VrefLevel [Byte0]: 29
8625 22:58:42.589492 [Byte1]: 29
8626 22:58:42.593915
8627 22:58:42.593998 Set Vref, RX VrefLevel [Byte0]: 30
8628 22:58:42.597271 [Byte1]: 30
8629 22:58:42.601590
8630 22:58:42.601673 Set Vref, RX VrefLevel [Byte0]: 31
8631 22:58:42.604793 [Byte1]: 31
8632 22:58:42.609304
8633 22:58:42.612175 Set Vref, RX VrefLevel [Byte0]: 32
8634 22:58:42.615798 [Byte1]: 32
8635 22:58:42.615907
8636 22:58:42.618878 Set Vref, RX VrefLevel [Byte0]: 33
8637 22:58:42.622494 [Byte1]: 33
8638 22:58:42.622583
8639 22:58:42.625601 Set Vref, RX VrefLevel [Byte0]: 34
8640 22:58:42.629037 [Byte1]: 34
8641 22:58:42.629120
8642 22:58:42.632112 Set Vref, RX VrefLevel [Byte0]: 35
8643 22:58:42.635510 [Byte1]: 35
8644 22:58:42.639499
8645 22:58:42.639608 Set Vref, RX VrefLevel [Byte0]: 36
8646 22:58:42.642802 [Byte1]: 36
8647 22:58:42.647262
8648 22:58:42.647344 Set Vref, RX VrefLevel [Byte0]: 37
8649 22:58:42.650199 [Byte1]: 37
8650 22:58:42.654571
8651 22:58:42.654654 Set Vref, RX VrefLevel [Byte0]: 38
8652 22:58:42.657946 [Byte1]: 38
8653 22:58:42.662277
8654 22:58:42.662363 Set Vref, RX VrefLevel [Byte0]: 39
8655 22:58:42.665745 [Byte1]: 39
8656 22:58:42.669995
8657 22:58:42.670079 Set Vref, RX VrefLevel [Byte0]: 40
8658 22:58:42.672967 [Byte1]: 40
8659 22:58:42.677349
8660 22:58:42.677433 Set Vref, RX VrefLevel [Byte0]: 41
8661 22:58:42.680667 [Byte1]: 41
8662 22:58:42.684731
8663 22:58:42.684838 Set Vref, RX VrefLevel [Byte0]: 42
8664 22:58:42.688030 [Byte1]: 42
8665 22:58:42.692346
8666 22:58:42.692456 Set Vref, RX VrefLevel [Byte0]: 43
8667 22:58:42.695560 [Byte1]: 43
8668 22:58:42.699958
8669 22:58:42.700041 Set Vref, RX VrefLevel [Byte0]: 44
8670 22:58:42.703437 [Byte1]: 44
8671 22:58:42.707624
8672 22:58:42.707707 Set Vref, RX VrefLevel [Byte0]: 45
8673 22:58:42.710957 [Byte1]: 45
8674 22:58:42.715353
8675 22:58:42.715435 Set Vref, RX VrefLevel [Byte0]: 46
8676 22:58:42.718681 [Byte1]: 46
8677 22:58:42.722725
8678 22:58:42.722821 Set Vref, RX VrefLevel [Byte0]: 47
8679 22:58:42.726071 [Byte1]: 47
8680 22:58:42.730593
8681 22:58:42.730668 Set Vref, RX VrefLevel [Byte0]: 48
8682 22:58:42.733545 [Byte1]: 48
8683 22:58:42.737861
8684 22:58:42.737939 Set Vref, RX VrefLevel [Byte0]: 49
8685 22:58:42.744307 [Byte1]: 49
8686 22:58:42.744417
8687 22:58:42.747659 Set Vref, RX VrefLevel [Byte0]: 50
8688 22:58:42.750985 [Byte1]: 50
8689 22:58:42.751059
8690 22:58:42.754371 Set Vref, RX VrefLevel [Byte0]: 51
8691 22:58:42.757696 [Byte1]: 51
8692 22:58:42.757773
8693 22:58:42.760641 Set Vref, RX VrefLevel [Byte0]: 52
8694 22:58:42.764052 [Byte1]: 52
8695 22:58:42.767947
8696 22:58:42.768057 Set Vref, RX VrefLevel [Byte0]: 53
8697 22:58:42.771259 [Byte1]: 53
8698 22:58:42.775886
8699 22:58:42.776003 Set Vref, RX VrefLevel [Byte0]: 54
8700 22:58:42.778779 [Byte1]: 54
8701 22:58:42.783171
8702 22:58:42.783254 Set Vref, RX VrefLevel [Byte0]: 55
8703 22:58:42.786782 [Byte1]: 55
8704 22:58:42.790987
8705 22:58:42.791108 Set Vref, RX VrefLevel [Byte0]: 56
8706 22:58:42.794377 [Byte1]: 56
8707 22:58:42.798600
8708 22:58:42.798677 Set Vref, RX VrefLevel [Byte0]: 57
8709 22:58:42.801922 [Byte1]: 57
8710 22:58:42.805832
8711 22:58:42.805932 Set Vref, RX VrefLevel [Byte0]: 58
8712 22:58:42.809171 [Byte1]: 58
8713 22:58:42.813453
8714 22:58:42.813532 Set Vref, RX VrefLevel [Byte0]: 59
8715 22:58:42.816888 [Byte1]: 59
8716 22:58:42.821177
8717 22:58:42.821255 Set Vref, RX VrefLevel [Byte0]: 60
8718 22:58:42.824454 [Byte1]: 60
8719 22:58:42.828852
8720 22:58:42.828941 Set Vref, RX VrefLevel [Byte0]: 61
8721 22:58:42.832114 [Byte1]: 61
8722 22:58:42.836444
8723 22:58:42.836519 Set Vref, RX VrefLevel [Byte0]: 62
8724 22:58:42.839426 [Byte1]: 62
8725 22:58:42.843762
8726 22:58:42.843834 Set Vref, RX VrefLevel [Byte0]: 63
8727 22:58:42.847067 [Byte1]: 63
8728 22:58:42.851395
8729 22:58:42.851474 Set Vref, RX VrefLevel [Byte0]: 64
8730 22:58:42.854721 [Byte1]: 64
8731 22:58:42.859080
8732 22:58:42.859169 Set Vref, RX VrefLevel [Byte0]: 65
8733 22:58:42.862451 [Byte1]: 65
8734 22:58:42.866946
8735 22:58:42.867021 Set Vref, RX VrefLevel [Byte0]: 66
8736 22:58:42.870190 [Byte1]: 66
8737 22:58:42.874090
8738 22:58:42.877327 Set Vref, RX VrefLevel [Byte0]: 67
8739 22:58:42.880679 [Byte1]: 67
8740 22:58:42.880778
8741 22:58:42.884107 Set Vref, RX VrefLevel [Byte0]: 68
8742 22:58:42.887457 [Byte1]: 68
8743 22:58:42.887530
8744 22:58:42.890778 Set Vref, RX VrefLevel [Byte0]: 69
8745 22:58:42.893855 [Byte1]: 69
8746 22:58:42.893944
8747 22:58:42.897280 Set Vref, RX VrefLevel [Byte0]: 70
8748 22:58:42.900500 [Byte1]: 70
8749 22:58:42.904646
8750 22:58:42.904727 Set Vref, RX VrefLevel [Byte0]: 71
8751 22:58:42.907608 [Byte1]: 71
8752 22:58:42.911984
8753 22:58:42.912056 Set Vref, RX VrefLevel [Byte0]: 72
8754 22:58:42.915249 [Byte1]: 72
8755 22:58:42.919650
8756 22:58:42.919759 Set Vref, RX VrefLevel [Byte0]: 73
8757 22:58:42.922685 [Byte1]: 73
8758 22:58:42.927080
8759 22:58:42.927161 Set Vref, RX VrefLevel [Byte0]: 74
8760 22:58:42.930572 [Byte1]: 74
8761 22:58:42.934705
8762 22:58:42.934787 Final RX Vref Byte 0 = 59 to rank0
8763 22:58:42.938034 Final RX Vref Byte 1 = 62 to rank0
8764 22:58:42.941391 Final RX Vref Byte 0 = 59 to rank1
8765 22:58:42.944905 Final RX Vref Byte 1 = 62 to rank1==
8766 22:58:42.947930 Dram Type= 6, Freq= 0, CH_1, rank 0
8767 22:58:42.954518 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8768 22:58:42.954601 ==
8769 22:58:42.954667 DQS Delay:
8770 22:58:42.954726 DQS0 = 0, DQS1 = 0
8771 22:58:42.957897 DQM Delay:
8772 22:58:42.957979 DQM0 = 134, DQM1 = 129
8773 22:58:42.961134 DQ Delay:
8774 22:58:42.964479 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =132
8775 22:58:42.967971 DQ4 =130, DQ5 =144, DQ6 =146, DQ7 =132
8776 22:58:42.971336 DQ8 =116, DQ9 =118, DQ10 =134, DQ11 =122
8777 22:58:42.974757 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =136
8778 22:58:42.974840
8779 22:58:42.974904
8780 22:58:42.974963
8781 22:58:42.977707 [DramC_TX_OE_Calibration] TA2
8782 22:58:42.980950 Original DQ_B0 (3 6) =30, OEN = 27
8783 22:58:42.984357 Original DQ_B1 (3 6) =30, OEN = 27
8784 22:58:42.987730 24, 0x0, End_B0=24 End_B1=24
8785 22:58:42.987816 25, 0x0, End_B0=25 End_B1=25
8786 22:58:42.991154 26, 0x0, End_B0=26 End_B1=26
8787 22:58:42.994503 27, 0x0, End_B0=27 End_B1=27
8788 22:58:42.997717 28, 0x0, End_B0=28 End_B1=28
8789 22:58:43.001060 29, 0x0, End_B0=29 End_B1=29
8790 22:58:43.001147 30, 0x0, End_B0=30 End_B1=30
8791 22:58:43.004439 31, 0x4141, End_B0=30 End_B1=30
8792 22:58:43.007607 Byte0 end_step=30 best_step=27
8793 22:58:43.011054 Byte1 end_step=30 best_step=27
8794 22:58:43.014546 Byte0 TX OE(2T, 0.5T) = (3, 3)
8795 22:58:43.017314 Byte1 TX OE(2T, 0.5T) = (3, 3)
8796 22:58:43.017399
8797 22:58:43.017483
8798 22:58:43.024399 [DQSOSCAuto] RK0, (LSB)MR18= 0x1927, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8799 22:58:43.027255 CH1 RK0: MR19=303, MR18=1927
8800 22:58:43.034228 CH1_RK0: MR19=0x303, MR18=0x1927, DQSOSC=390, MR23=63, INC=24, DEC=16
8801 22:58:43.034314
8802 22:58:43.037561 ----->DramcWriteLeveling(PI) begin...
8803 22:58:43.037648 ==
8804 22:58:43.040857 Dram Type= 6, Freq= 0, CH_1, rank 1
8805 22:58:43.044068 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8806 22:58:43.044154 ==
8807 22:58:43.047520 Write leveling (Byte 0): 25 => 25
8808 22:58:43.050926 Write leveling (Byte 1): 29 => 29
8809 22:58:43.054222 DramcWriteLeveling(PI) end<-----
8810 22:58:43.054305
8811 22:58:43.054371 ==
8812 22:58:43.057450 Dram Type= 6, Freq= 0, CH_1, rank 1
8813 22:58:43.060710 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8814 22:58:43.060846 ==
8815 22:58:43.064124 [Gating] SW mode calibration
8816 22:58:43.070722 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8817 22:58:43.077192 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8818 22:58:43.080557 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8819 22:58:43.087067 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8820 22:58:43.090355 1 4 8 | B1->B0 | 3333 2323 | 1 0 | (0 0) (1 1)
8821 22:58:43.093824 1 4 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 0)
8822 22:58:43.100417 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8823 22:58:43.103743 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8824 22:58:43.107165 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8825 22:58:43.113690 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8826 22:58:43.116662 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8827 22:58:43.120060 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8828 22:58:43.126693 1 5 8 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 0)
8829 22:58:43.130111 1 5 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8830 22:58:43.133558 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8831 22:58:43.139936 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8832 22:58:43.143367 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8833 22:58:43.146776 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8834 22:58:43.153263 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8835 22:58:43.156371 1 6 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8836 22:58:43.159649 1 6 8 | B1->B0 | 4343 2424 | 0 0 | (0 0) (0 0)
8837 22:58:43.166201 1 6 12 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
8838 22:58:43.169389 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8839 22:58:43.172865 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8840 22:58:43.179415 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8841 22:58:43.182892 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8842 22:58:43.186410 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8843 22:58:43.189343 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8844 22:58:43.195981 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8845 22:58:43.199443 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8846 22:58:43.202851 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 22:58:43.209056 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 22:58:43.212529 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 22:58:43.215894 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 22:58:43.222605 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 22:58:43.225854 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 22:58:43.229246 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 22:58:43.235389 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 22:58:43.238797 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 22:58:43.245157 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 22:58:43.248663 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 22:58:43.252021 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 22:58:43.255303 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 22:58:43.261936 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8860 22:58:43.265112 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8861 22:58:43.268498 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8862 22:58:43.271956 Total UI for P1: 0, mck2ui 16
8863 22:58:43.275249 best dqsien dly found for B0: ( 1, 9, 6)
8864 22:58:43.278332 Total UI for P1: 0, mck2ui 16
8865 22:58:43.281686 best dqsien dly found for B1: ( 1, 9, 6)
8866 22:58:43.284937 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8867 22:58:43.288475 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8868 22:58:43.291786
8869 22:58:43.295085 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8870 22:58:43.298510 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8871 22:58:43.301586 [Gating] SW calibration Done
8872 22:58:43.301671 ==
8873 22:58:43.304975 Dram Type= 6, Freq= 0, CH_1, rank 1
8874 22:58:43.308338 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8875 22:58:43.308445 ==
8876 22:58:43.308540 RX Vref Scan: 0
8877 22:58:43.311554
8878 22:58:43.311639 RX Vref 0 -> 0, step: 1
8879 22:58:43.311707
8880 22:58:43.315007 RX Delay 0 -> 252, step: 8
8881 22:58:43.317975 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8882 22:58:43.321737 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8883 22:58:43.328005 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8884 22:58:43.331330 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8885 22:58:43.335061 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8886 22:58:43.338479 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8887 22:58:43.341475 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8888 22:58:43.348370 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8889 22:58:43.351296 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8890 22:58:43.354646 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8891 22:58:43.357928 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8892 22:58:43.361343 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8893 22:58:43.368087 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8894 22:58:43.371673 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8895 22:58:43.374553 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8896 22:58:43.378046 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8897 22:58:43.378128 ==
8898 22:58:43.381499 Dram Type= 6, Freq= 0, CH_1, rank 1
8899 22:58:43.387734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8900 22:58:43.387837 ==
8901 22:58:43.387930 DQS Delay:
8902 22:58:43.391172 DQS0 = 0, DQS1 = 0
8903 22:58:43.391255 DQM Delay:
8904 22:58:43.391322 DQM0 = 136, DQM1 = 132
8905 22:58:43.394364 DQ Delay:
8906 22:58:43.397887 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8907 22:58:43.401223 DQ4 =139, DQ5 =147, DQ6 =139, DQ7 =135
8908 22:58:43.404536 DQ8 =115, DQ9 =123, DQ10 =131, DQ11 =127
8909 22:58:43.407907 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =143
8910 22:58:43.408006
8911 22:58:43.408089
8912 22:58:43.408160 ==
8913 22:58:43.411305 Dram Type= 6, Freq= 0, CH_1, rank 1
8914 22:58:43.414174 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8915 22:58:43.417460 ==
8916 22:58:43.417539
8917 22:58:43.417607
8918 22:58:43.417675 TX Vref Scan disable
8919 22:58:43.420692 == TX Byte 0 ==
8920 22:58:43.424420 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8921 22:58:43.427861 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8922 22:58:43.430722 == TX Byte 1 ==
8923 22:58:43.434127 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8924 22:58:43.437306 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8925 22:58:43.440749 ==
8926 22:58:43.440874 Dram Type= 6, Freq= 0, CH_1, rank 1
8927 22:58:43.447607 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8928 22:58:43.447684 ==
8929 22:58:43.459433
8930 22:58:43.462960 TX Vref early break, caculate TX vref
8931 22:58:43.465783 TX Vref=16, minBit 9, minWin=21, winSum=377
8932 22:58:43.469204 TX Vref=18, minBit 9, minWin=22, winSum=386
8933 22:58:43.472432 TX Vref=20, minBit 9, minWin=22, winSum=392
8934 22:58:43.476194 TX Vref=22, minBit 9, minWin=23, winSum=404
8935 22:58:43.479097 TX Vref=24, minBit 8, minWin=24, winSum=411
8936 22:58:43.485845 TX Vref=26, minBit 15, minWin=24, winSum=419
8937 22:58:43.489261 TX Vref=28, minBit 8, minWin=25, winSum=420
8938 22:58:43.492331 TX Vref=30, minBit 10, minWin=24, winSum=411
8939 22:58:43.495816 TX Vref=32, minBit 0, minWin=24, winSum=402
8940 22:58:43.499137 TX Vref=34, minBit 9, minWin=22, winSum=390
8941 22:58:43.505495 [TxChooseVref] Worse bit 8, Min win 25, Win sum 420, Final Vref 28
8942 22:58:43.505579
8943 22:58:43.508980 Final TX Range 0 Vref 28
8944 22:58:43.509063
8945 22:58:43.509134 ==
8946 22:58:43.512021 Dram Type= 6, Freq= 0, CH_1, rank 1
8947 22:58:43.515520 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8948 22:58:43.515603 ==
8949 22:58:43.515669
8950 22:58:43.515729
8951 22:58:43.518917 TX Vref Scan disable
8952 22:58:43.525473 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8953 22:58:43.525556 == TX Byte 0 ==
8954 22:58:43.528706 u2DelayCellOfst[0]=13 cells (4 PI)
8955 22:58:43.532069 u2DelayCellOfst[1]=10 cells (3 PI)
8956 22:58:43.535495 u2DelayCellOfst[2]=0 cells (0 PI)
8957 22:58:43.538936 u2DelayCellOfst[3]=3 cells (1 PI)
8958 22:58:43.542089 u2DelayCellOfst[4]=6 cells (2 PI)
8959 22:58:43.545448 u2DelayCellOfst[5]=16 cells (5 PI)
8960 22:58:43.548484 u2DelayCellOfst[6]=16 cells (5 PI)
8961 22:58:43.551819 u2DelayCellOfst[7]=3 cells (1 PI)
8962 22:58:43.555291 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8963 22:58:43.558844 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8964 22:58:43.561763 == TX Byte 1 ==
8965 22:58:43.565371 u2DelayCellOfst[8]=0 cells (0 PI)
8966 22:58:43.565454 u2DelayCellOfst[9]=3 cells (1 PI)
8967 22:58:43.568294 u2DelayCellOfst[10]=6 cells (2 PI)
8968 22:58:43.571786 u2DelayCellOfst[11]=3 cells (1 PI)
8969 22:58:43.575021 u2DelayCellOfst[12]=13 cells (4 PI)
8970 22:58:43.578402 u2DelayCellOfst[13]=16 cells (5 PI)
8971 22:58:43.581753 u2DelayCellOfst[14]=16 cells (5 PI)
8972 22:58:43.584937 u2DelayCellOfst[15]=16 cells (5 PI)
8973 22:58:43.591658 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8974 22:58:43.594639 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8975 22:58:43.594722 DramC Write-DBI on
8976 22:58:43.594788 ==
8977 22:58:43.598006 Dram Type= 6, Freq= 0, CH_1, rank 1
8978 22:58:43.604621 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8979 22:58:43.604704 ==
8980 22:58:43.604794
8981 22:58:43.604871
8982 22:58:43.604947 TX Vref Scan disable
8983 22:58:43.608974 == TX Byte 0 ==
8984 22:58:43.612368 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8985 22:58:43.615308 == TX Byte 1 ==
8986 22:58:43.618827 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8987 22:58:43.621818 DramC Write-DBI off
8988 22:58:43.621901
8989 22:58:43.622004 [DATLAT]
8990 22:58:43.622094 Freq=1600, CH1 RK1
8991 22:58:43.622153
8992 22:58:43.625265 DATLAT Default: 0xf
8993 22:58:43.628819 0, 0xFFFF, sum = 0
8994 22:58:43.628903 1, 0xFFFF, sum = 0
8995 22:58:43.632185 2, 0xFFFF, sum = 0
8996 22:58:43.632269 3, 0xFFFF, sum = 0
8997 22:58:43.635101 4, 0xFFFF, sum = 0
8998 22:58:43.635191 5, 0xFFFF, sum = 0
8999 22:58:43.638518 6, 0xFFFF, sum = 0
9000 22:58:43.638602 7, 0xFFFF, sum = 0
9001 22:58:43.641909 8, 0xFFFF, sum = 0
9002 22:58:43.641992 9, 0xFFFF, sum = 0
9003 22:58:43.645124 10, 0xFFFF, sum = 0
9004 22:58:43.645210 11, 0xFFFF, sum = 0
9005 22:58:43.648524 12, 0xFFFF, sum = 0
9006 22:58:43.648608 13, 0xFFFF, sum = 0
9007 22:58:43.651856 14, 0x0, sum = 1
9008 22:58:43.651960 15, 0x0, sum = 2
9009 22:58:43.654946 16, 0x0, sum = 3
9010 22:58:43.655030 17, 0x0, sum = 4
9011 22:58:43.658366 best_step = 15
9012 22:58:43.658473
9013 22:58:43.658567 ==
9014 22:58:43.661831 Dram Type= 6, Freq= 0, CH_1, rank 1
9015 22:58:43.665062 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9016 22:58:43.665144 ==
9017 22:58:43.668436 RX Vref Scan: 0
9018 22:58:43.668518
9019 22:58:43.668583 RX Vref 0 -> 0, step: 1
9020 22:58:43.668644
9021 22:58:43.671407 RX Delay 19 -> 252, step: 4
9022 22:58:43.674835 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
9023 22:58:43.681724 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9024 22:58:43.684891 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
9025 22:58:43.688080 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
9026 22:58:43.691550 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9027 22:58:43.694847 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
9028 22:58:43.701537 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
9029 22:58:43.704924 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
9030 22:58:43.707997 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
9031 22:58:43.711533 iDelay=195, Bit 9, Center 120 (71 ~ 170) 100
9032 22:58:43.714799 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9033 22:58:43.721625 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
9034 22:58:43.724621 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9035 22:58:43.727792 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9036 22:58:43.731231 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9037 22:58:43.734574 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
9038 22:58:43.737666 ==
9039 22:58:43.741084 Dram Type= 6, Freq= 0, CH_1, rank 1
9040 22:58:43.744477 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9041 22:58:43.744560 ==
9042 22:58:43.744627 DQS Delay:
9043 22:58:43.747785 DQS0 = 0, DQS1 = 0
9044 22:58:43.747868 DQM Delay:
9045 22:58:43.751115 DQM0 = 133, DQM1 = 130
9046 22:58:43.751198 DQ Delay:
9047 22:58:43.754471 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
9048 22:58:43.757545 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =130
9049 22:58:43.761035 DQ8 =112, DQ9 =120, DQ10 =130, DQ11 =126
9050 22:58:43.764134 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
9051 22:58:43.764233
9052 22:58:43.764355
9053 22:58:43.764502
9054 22:58:43.767509 [DramC_TX_OE_Calibration] TA2
9055 22:58:43.771016 Original DQ_B0 (3 6) =30, OEN = 27
9056 22:58:43.773981 Original DQ_B1 (3 6) =30, OEN = 27
9057 22:58:43.777604 24, 0x0, End_B0=24 End_B1=24
9058 22:58:43.780586 25, 0x0, End_B0=25 End_B1=25
9059 22:58:43.780685 26, 0x0, End_B0=26 End_B1=26
9060 22:58:43.784109 27, 0x0, End_B0=27 End_B1=27
9061 22:58:43.787285 28, 0x0, End_B0=28 End_B1=28
9062 22:58:43.790975 29, 0x0, End_B0=29 End_B1=29
9063 22:58:43.793839 30, 0x0, End_B0=30 End_B1=30
9064 22:58:43.793924 31, 0x5151, End_B0=30 End_B1=30
9065 22:58:43.797565 Byte0 end_step=30 best_step=27
9066 22:58:43.800343 Byte1 end_step=30 best_step=27
9067 22:58:43.804062 Byte0 TX OE(2T, 0.5T) = (3, 3)
9068 22:58:43.806993 Byte1 TX OE(2T, 0.5T) = (3, 3)
9069 22:58:43.807076
9070 22:58:43.807142
9071 22:58:43.813819 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c06, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
9072 22:58:43.816763 CH1 RK1: MR19=303, MR18=1C06
9073 22:58:43.823455 CH1_RK1: MR19=0x303, MR18=0x1C06, DQSOSC=395, MR23=63, INC=23, DEC=15
9074 22:58:43.826910 [RxdqsGatingPostProcess] freq 1600
9075 22:58:43.833287 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9076 22:58:43.836629 best DQS0 dly(2T, 0.5T) = (1, 1)
9077 22:58:43.836717 best DQS1 dly(2T, 0.5T) = (1, 1)
9078 22:58:43.839932 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9079 22:58:43.843309 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9080 22:58:43.846867 best DQS0 dly(2T, 0.5T) = (1, 1)
9081 22:58:43.849830 best DQS1 dly(2T, 0.5T) = (1, 1)
9082 22:58:43.853160 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9083 22:58:43.856436 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9084 22:58:43.859759 Pre-setting of DQS Precalculation
9085 22:58:43.866576 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9086 22:58:43.872978 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9087 22:58:43.879789 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9088 22:58:43.879874
9089 22:58:43.879941
9090 22:58:43.883182 [Calibration Summary] 3200 Mbps
9091 22:58:43.883265 CH 0, Rank 0
9092 22:58:43.886156 SW Impedance : PASS
9093 22:58:43.889502 DUTY Scan : NO K
9094 22:58:43.889585 ZQ Calibration : PASS
9095 22:58:43.892978 Jitter Meter : NO K
9096 22:58:43.896329 CBT Training : PASS
9097 22:58:43.896412 Write leveling : PASS
9098 22:58:43.899535 RX DQS gating : PASS
9099 22:58:43.899618 RX DQ/DQS(RDDQC) : PASS
9100 22:58:43.902732 TX DQ/DQS : PASS
9101 22:58:43.906325 RX DATLAT : PASS
9102 22:58:43.906408 RX DQ/DQS(Engine): PASS
9103 22:58:43.909586 TX OE : PASS
9104 22:58:43.909669 All Pass.
9105 22:58:43.909823
9106 22:58:43.913139 CH 0, Rank 1
9107 22:58:43.913249 SW Impedance : PASS
9108 22:58:43.916046 DUTY Scan : NO K
9109 22:58:43.919475 ZQ Calibration : PASS
9110 22:58:43.919558 Jitter Meter : NO K
9111 22:58:43.922832 CBT Training : PASS
9112 22:58:43.926314 Write leveling : PASS
9113 22:58:43.926399 RX DQS gating : PASS
9114 22:58:43.929373 RX DQ/DQS(RDDQC) : PASS
9115 22:58:43.932841 TX DQ/DQS : PASS
9116 22:58:43.932980 RX DATLAT : PASS
9117 22:58:43.936143 RX DQ/DQS(Engine): PASS
9118 22:58:43.939502 TX OE : PASS
9119 22:58:43.939584 All Pass.
9120 22:58:43.939650
9121 22:58:43.939709 CH 1, Rank 0
9122 22:58:43.942404 SW Impedance : PASS
9123 22:58:43.946188 DUTY Scan : NO K
9124 22:58:43.946270 ZQ Calibration : PASS
9125 22:58:43.949021 Jitter Meter : NO K
9126 22:58:43.952417 CBT Training : PASS
9127 22:58:43.952499 Write leveling : PASS
9128 22:58:43.955884 RX DQS gating : PASS
9129 22:58:43.955966 RX DQ/DQS(RDDQC) : PASS
9130 22:58:43.959059 TX DQ/DQS : PASS
9131 22:58:43.962547 RX DATLAT : PASS
9132 22:58:43.962629 RX DQ/DQS(Engine): PASS
9133 22:58:43.966051 TX OE : PASS
9134 22:58:43.966140 All Pass.
9135 22:58:43.966206
9136 22:58:43.968940 CH 1, Rank 1
9137 22:58:43.969022 SW Impedance : PASS
9138 22:58:43.972434 DUTY Scan : NO K
9139 22:58:43.975962 ZQ Calibration : PASS
9140 22:58:43.976045 Jitter Meter : NO K
9141 22:58:43.979377 CBT Training : PASS
9142 22:58:43.982287 Write leveling : PASS
9143 22:58:43.982369 RX DQS gating : PASS
9144 22:58:43.985803 RX DQ/DQS(RDDQC) : PASS
9145 22:58:43.989260 TX DQ/DQS : PASS
9146 22:58:43.989343 RX DATLAT : PASS
9147 22:58:43.992162 RX DQ/DQS(Engine): PASS
9148 22:58:43.995658 TX OE : PASS
9149 22:58:43.995740 All Pass.
9150 22:58:43.995806
9151 22:58:43.995865 DramC Write-DBI on
9152 22:58:43.999087 PER_BANK_REFRESH: Hybrid Mode
9153 22:58:44.002639 TX_TRACKING: ON
9154 22:58:44.008757 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9155 22:58:44.018510 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9156 22:58:44.025322 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9157 22:58:44.028574 [FAST_K] Save calibration result to emmc
9158 22:58:44.031891 sync common calibartion params.
9159 22:58:44.035434 sync cbt_mode0:1, 1:1
9160 22:58:44.035517 dram_init: ddr_geometry: 2
9161 22:58:44.038828 dram_init: ddr_geometry: 2
9162 22:58:44.041630 dram_init: ddr_geometry: 2
9163 22:58:44.045127 0:dram_rank_size:100000000
9164 22:58:44.045211 1:dram_rank_size:100000000
9165 22:58:44.051693 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9166 22:58:44.055485 DFS_SHUFFLE_HW_MODE: ON
9167 22:58:44.058332 dramc_set_vcore_voltage set vcore to 725000
9168 22:58:44.058414 Read voltage for 1600, 0
9169 22:58:44.061433 Vio18 = 0
9170 22:58:44.061565 Vcore = 725000
9171 22:58:44.061717 Vdram = 0
9172 22:58:44.064939 Vddq = 0
9173 22:58:44.065041 Vmddr = 0
9174 22:58:44.068073 switch to 3200 Mbps bootup
9175 22:58:44.068146 [DramcRunTimeConfig]
9176 22:58:44.068207 PHYPLL
9177 22:58:44.071341 DPM_CONTROL_AFTERK: ON
9178 22:58:44.074672 PER_BANK_REFRESH: ON
9179 22:58:44.078269 REFRESH_OVERHEAD_REDUCTION: ON
9180 22:58:44.078392 CMD_PICG_NEW_MODE: OFF
9181 22:58:44.081237 XRTWTW_NEW_MODE: ON
9182 22:58:44.081312 XRTRTR_NEW_MODE: ON
9183 22:58:44.084638 TX_TRACKING: ON
9184 22:58:44.084739 RDSEL_TRACKING: OFF
9185 22:58:44.088200 DQS Precalculation for DVFS: ON
9186 22:58:44.091104 RX_TRACKING: OFF
9187 22:58:44.091187 HW_GATING DBG: ON
9188 22:58:44.094506 ZQCS_ENABLE_LP4: ON
9189 22:58:44.094589 RX_PICG_NEW_MODE: ON
9190 22:58:44.097890 TX_PICG_NEW_MODE: ON
9191 22:58:44.097973 ENABLE_RX_DCM_DPHY: ON
9192 22:58:44.101446 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9193 22:58:44.104719 DUMMY_READ_FOR_TRACKING: OFF
9194 22:58:44.108039 !!! SPM_CONTROL_AFTERK: OFF
9195 22:58:44.111264 !!! SPM could not control APHY
9196 22:58:44.111347 IMPEDANCE_TRACKING: ON
9197 22:58:44.114464 TEMP_SENSOR: ON
9198 22:58:44.114547 HW_SAVE_FOR_SR: OFF
9199 22:58:44.117596 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9200 22:58:44.120790 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9201 22:58:44.124196 Read ODT Tracking: ON
9202 22:58:44.127600 Refresh Rate DeBounce: ON
9203 22:58:44.127682 DFS_NO_QUEUE_FLUSH: ON
9204 22:58:44.131007 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9205 22:58:44.134524 ENABLE_DFS_RUNTIME_MRW: OFF
9206 22:58:44.137525 DDR_RESERVE_NEW_MODE: ON
9207 22:58:44.137607 MR_CBT_SWITCH_FREQ: ON
9208 22:58:44.140550 =========================
9209 22:58:44.159559 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9210 22:58:44.162844 dram_init: ddr_geometry: 2
9211 22:58:44.181322 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9212 22:58:44.184679 dram_init: dram init end (result: 0)
9213 22:58:44.191401 DRAM-K: Full calibration passed in 24487 msecs
9214 22:58:44.194441 MRC: failed to locate region type 0.
9215 22:58:44.194527 DRAM rank0 size:0x100000000,
9216 22:58:44.197724 DRAM rank1 size=0x100000000
9217 22:58:44.207659 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9218 22:58:44.214085 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9219 22:58:44.220940 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9220 22:58:44.227808 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9221 22:58:44.231166 DRAM rank0 size:0x100000000,
9222 22:58:44.233989 DRAM rank1 size=0x100000000
9223 22:58:44.234089 CBMEM:
9224 22:58:44.237270 IMD: root @ 0xfffff000 254 entries.
9225 22:58:44.240565 IMD: root @ 0xffffec00 62 entries.
9226 22:58:44.244046 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9227 22:58:44.250526 WARNING: RO_VPD is uninitialized or empty.
9228 22:58:44.253908 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9229 22:58:44.261214 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9230 22:58:44.274171 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9231 22:58:44.285360 BS: romstage times (exec / console): total (unknown) / 23990 ms
9232 22:58:44.285446
9233 22:58:44.285512
9234 22:58:44.295253 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9235 22:58:44.298687 ARM64: Exception handlers installed.
9236 22:58:44.302013 ARM64: Testing exception
9237 22:58:44.304967 ARM64: Done test exception
9238 22:58:44.305069 Enumerating buses...
9239 22:58:44.308091 Show all devs... Before device enumeration.
9240 22:58:44.311823 Root Device: enabled 1
9241 22:58:44.314796 CPU_CLUSTER: 0: enabled 1
9242 22:58:44.314879 CPU: 00: enabled 1
9243 22:58:44.318242 Compare with tree...
9244 22:58:44.318326 Root Device: enabled 1
9245 22:58:44.321602 CPU_CLUSTER: 0: enabled 1
9246 22:58:44.324892 CPU: 00: enabled 1
9247 22:58:44.324975 Root Device scanning...
9248 22:58:44.328385 scan_static_bus for Root Device
9249 22:58:44.331647 CPU_CLUSTER: 0 enabled
9250 22:58:44.334792 scan_static_bus for Root Device done
9251 22:58:44.338072 scan_bus: bus Root Device finished in 8 msecs
9252 22:58:44.338156 done
9253 22:58:44.345003 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9254 22:58:44.348050 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9255 22:58:44.354444 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9256 22:58:44.357940 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9257 22:58:44.361352 Allocating resources...
9258 22:58:44.364509 Reading resources...
9259 22:58:44.367957 Root Device read_resources bus 0 link: 0
9260 22:58:44.370946 DRAM rank0 size:0x100000000,
9261 22:58:44.371048 DRAM rank1 size=0x100000000
9262 22:58:44.377876 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9263 22:58:44.377957 CPU: 00 missing read_resources
9264 22:58:44.384226 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9265 22:58:44.387602 Root Device read_resources bus 0 link: 0 done
9266 22:58:44.391084 Done reading resources.
9267 22:58:44.394571 Show resources in subtree (Root Device)...After reading.
9268 22:58:44.397531 Root Device child on link 0 CPU_CLUSTER: 0
9269 22:58:44.401093 CPU_CLUSTER: 0 child on link 0 CPU: 00
9270 22:58:44.411007 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9271 22:58:44.411085 CPU: 00
9272 22:58:44.414533 Root Device assign_resources, bus 0 link: 0
9273 22:58:44.417392 CPU_CLUSTER: 0 missing set_resources
9274 22:58:44.424176 Root Device assign_resources, bus 0 link: 0 done
9275 22:58:44.424252 Done setting resources.
9276 22:58:44.430341 Show resources in subtree (Root Device)...After assigning values.
9277 22:58:44.434003 Root Device child on link 0 CPU_CLUSTER: 0
9278 22:58:44.437139 CPU_CLUSTER: 0 child on link 0 CPU: 00
9279 22:58:44.447375 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9280 22:58:44.447489 CPU: 00
9281 22:58:44.450274 Done allocating resources.
9282 22:58:44.457108 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9283 22:58:44.457190 Enabling resources...
9284 22:58:44.460286 done.
9285 22:58:44.463630 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9286 22:58:44.466874 Initializing devices...
9287 22:58:44.466953 Root Device init
9288 22:58:44.470390 init hardware done!
9289 22:58:44.470473 0x00000018: ctrlr->caps
9290 22:58:44.473606 52.000 MHz: ctrlr->f_max
9291 22:58:44.476534 0.400 MHz: ctrlr->f_min
9292 22:58:44.476619 0x40ff8080: ctrlr->voltages
9293 22:58:44.479944 sclk: 390625
9294 22:58:44.480027 Bus Width = 1
9295 22:58:44.483171 sclk: 390625
9296 22:58:44.483253 Bus Width = 1
9297 22:58:44.486608 Early init status = 3
9298 22:58:44.489970 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9299 22:58:44.493523 in-header: 03 fc 00 00 01 00 00 00
9300 22:58:44.496491 in-data: 00
9301 22:58:44.499787 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9302 22:58:44.505293 in-header: 03 fd 00 00 00 00 00 00
9303 22:58:44.508175 in-data:
9304 22:58:44.511658 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9305 22:58:44.516025 in-header: 03 fc 00 00 01 00 00 00
9306 22:58:44.519547 in-data: 00
9307 22:58:44.522468 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9308 22:58:44.528255 in-header: 03 fd 00 00 00 00 00 00
9309 22:58:44.531626 in-data:
9310 22:58:44.534645 [SSUSB] Setting up USB HOST controller...
9311 22:58:44.537984 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9312 22:58:44.541377 [SSUSB] phy power-on done.
9313 22:58:44.544622 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9314 22:58:44.551404 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9315 22:58:44.554814 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9316 22:58:44.561260 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9317 22:58:44.567863 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9318 22:58:44.574460 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9319 22:58:44.581247 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9320 22:58:44.587570 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9321 22:58:44.590746 SPM: binary array size = 0x9dc
9322 22:58:44.594365 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9323 22:58:44.600893 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9324 22:58:44.607232 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9325 22:58:44.614099 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9326 22:58:44.616997 configure_display: Starting display init
9327 22:58:44.651487 anx7625_power_on_init: Init interface.
9328 22:58:44.654704 anx7625_disable_pd_protocol: Disabled PD feature.
9329 22:58:44.657856 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9330 22:58:44.685861 anx7625_start_dp_work: Secure OCM version=00
9331 22:58:44.689186 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9332 22:58:44.703956 sp_tx_get_edid_block: EDID Block = 1
9333 22:58:44.806556 Extracted contents:
9334 22:58:44.809903 header: 00 ff ff ff ff ff ff 00
9335 22:58:44.813290 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9336 22:58:44.816190 version: 01 04
9337 22:58:44.819562 basic params: 95 1f 11 78 0a
9338 22:58:44.823053 chroma info: 76 90 94 55 54 90 27 21 50 54
9339 22:58:44.826106 established: 00 00 00
9340 22:58:44.833074 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9341 22:58:44.836010 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9342 22:58:44.842942 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9343 22:58:44.849538 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9344 22:58:44.855814 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9345 22:58:44.859527 extensions: 00
9346 22:58:44.859610 checksum: fb
9347 22:58:44.859676
9348 22:58:44.862700 Manufacturer: IVO Model 57d Serial Number 0
9349 22:58:44.865727 Made week 0 of 2020
9350 22:58:44.869487 EDID version: 1.4
9351 22:58:44.869569 Digital display
9352 22:58:44.872587 6 bits per primary color channel
9353 22:58:44.872700 DisplayPort interface
9354 22:58:44.875610 Maximum image size: 31 cm x 17 cm
9355 22:58:44.879163 Gamma: 220%
9356 22:58:44.879246 Check DPMS levels
9357 22:58:44.885506 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9358 22:58:44.888979 First detailed timing is preferred timing
9359 22:58:44.889063 Established timings supported:
9360 22:58:44.892305 Standard timings supported:
9361 22:58:44.895701 Detailed timings
9362 22:58:44.898860 Hex of detail: 383680a07038204018303c0035ae10000019
9363 22:58:44.905774 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9364 22:58:44.908659 0780 0798 07c8 0820 hborder 0
9365 22:58:44.912031 0438 043b 0447 0458 vborder 0
9366 22:58:44.915489 -hsync -vsync
9367 22:58:44.915569 Did detailed timing
9368 22:58:44.922170 Hex of detail: 000000000000000000000000000000000000
9369 22:58:44.925206 Manufacturer-specified data, tag 0
9370 22:58:44.928709 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9371 22:58:44.931734 ASCII string: InfoVision
9372 22:58:44.935169 Hex of detail: 000000fe00523134304e574635205248200a
9373 22:58:44.938587 ASCII string: R140NWF5 RH
9374 22:58:44.938667 Checksum
9375 22:58:44.941878 Checksum: 0xfb (valid)
9376 22:58:44.944866 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9377 22:58:44.948692 DSI data_rate: 832800000 bps
9378 22:58:44.955096 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9379 22:58:44.958468 anx7625_parse_edid: pixelclock(138800).
9380 22:58:44.961877 hactive(1920), hsync(48), hfp(24), hbp(88)
9381 22:58:44.964885 vactive(1080), vsync(12), vfp(3), vbp(17)
9382 22:58:44.968086 anx7625_dsi_config: config dsi.
9383 22:58:44.975098 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9384 22:58:44.988483 anx7625_dsi_config: success to config DSI
9385 22:58:44.991868 anx7625_dp_start: MIPI phy setup OK.
9386 22:58:44.995256 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9387 22:58:44.998678 mtk_ddp_mode_set invalid vrefresh 60
9388 22:58:45.001868 main_disp_path_setup
9389 22:58:45.001949 ovl_layer_smi_id_en
9390 22:58:45.005099 ovl_layer_smi_id_en
9391 22:58:45.005180 ccorr_config
9392 22:58:45.005245 aal_config
9393 22:58:45.008472 gamma_config
9394 22:58:45.008554 postmask_config
9395 22:58:45.011781 dither_config
9396 22:58:45.015240 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9397 22:58:45.021552 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9398 22:58:45.024942 Root Device init finished in 554 msecs
9399 22:58:45.028466 CPU_CLUSTER: 0 init
9400 22:58:45.034771 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9401 22:58:45.041547 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9402 22:58:45.041629 APU_MBOX 0x190000b0 = 0x10001
9403 22:58:45.044516 APU_MBOX 0x190001b0 = 0x10001
9404 22:58:45.047939 APU_MBOX 0x190005b0 = 0x10001
9405 22:58:45.051346 APU_MBOX 0x190006b0 = 0x10001
9406 22:58:45.057584 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9407 22:58:45.067508 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9408 22:58:45.079793 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9409 22:58:45.086302 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9410 22:58:45.097996 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9411 22:58:45.107055 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9412 22:58:45.110911 CPU_CLUSTER: 0 init finished in 81 msecs
9413 22:58:45.113735 Devices initialized
9414 22:58:45.117195 Show all devs... After init.
9415 22:58:45.117300 Root Device: enabled 1
9416 22:58:45.120510 CPU_CLUSTER: 0: enabled 1
9417 22:58:45.124076 CPU: 00: enabled 1
9418 22:58:45.126895 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9419 22:58:45.130455 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9420 22:58:45.133875 ELOG: NV offset 0x57f000 size 0x1000
9421 22:58:45.140360 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9422 22:58:45.147167 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9423 22:58:45.150007 ELOG: Event(17) added with size 13 at 2023-06-05 22:58:42 UTC
9424 22:58:45.156944 out: cmd=0x121: 03 db 21 01 00 00 00 00
9425 22:58:45.160334 in-header: 03 3d 00 00 2c 00 00 00
9426 22:58:45.170125 in-data: 22 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9427 22:58:45.176760 ELOG: Event(A1) added with size 10 at 2023-06-05 22:58:42 UTC
9428 22:58:45.183167 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9429 22:58:45.189768 ELOG: Event(A0) added with size 9 at 2023-06-05 22:58:42 UTC
9430 22:58:45.193293 elog_add_boot_reason: Logged dev mode boot
9431 22:58:45.199658 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9432 22:58:45.199746 Finalize devices...
9433 22:58:45.203219 Devices finalized
9434 22:58:45.206440 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9435 22:58:45.209719 Writing coreboot table at 0xffe64000
9436 22:58:45.212673 0. 000000000010a000-0000000000113fff: RAMSTAGE
9437 22:58:45.219529 1. 0000000040000000-00000000400fffff: RAM
9438 22:58:45.222845 2. 0000000040100000-000000004032afff: RAMSTAGE
9439 22:58:45.226230 3. 000000004032b000-00000000545fffff: RAM
9440 22:58:45.229050 4. 0000000054600000-000000005465ffff: BL31
9441 22:58:45.232477 5. 0000000054660000-00000000ffe63fff: RAM
9442 22:58:45.239330 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9443 22:58:45.242241 7. 0000000100000000-000000023fffffff: RAM
9444 22:58:45.245684 Passing 5 GPIOs to payload:
9445 22:58:45.249047 NAME | PORT | POLARITY | VALUE
9446 22:58:45.255469 EC in RW | 0x000000aa | low | undefined
9447 22:58:45.258778 EC interrupt | 0x00000005 | low | undefined
9448 22:58:45.265719 TPM interrupt | 0x000000ab | high | undefined
9449 22:58:45.268581 SD card detect | 0x00000011 | high | undefined
9450 22:58:45.272067 speaker enable | 0x00000093 | high | undefined
9451 22:58:45.275525 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9452 22:58:45.278470 in-header: 03 f9 00 00 02 00 00 00
9453 22:58:45.282237 in-data: 02 00
9454 22:58:45.285058 ADC[4]: Raw value=901770 ID=7
9455 22:58:45.288556 ADC[3]: Raw value=213179 ID=1
9456 22:58:45.288665 RAM Code: 0x71
9457 22:58:45.292013 ADC[6]: Raw value=74502 ID=0
9458 22:58:45.295364 ADC[5]: Raw value=212072 ID=1
9459 22:58:45.295446 SKU Code: 0x1
9460 22:58:45.301976 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4bb3
9461 22:58:45.302060 coreboot table: 964 bytes.
9462 22:58:45.305133 IMD ROOT 0. 0xfffff000 0x00001000
9463 22:58:45.308459 IMD SMALL 1. 0xffffe000 0x00001000
9464 22:58:45.311573 RO MCACHE 2. 0xffffc000 0x00001104
9465 22:58:45.314771 CONSOLE 3. 0xfff7c000 0x00080000
9466 22:58:45.318132 FMAP 4. 0xfff7b000 0x00000452
9467 22:58:45.321587 TIME STAMP 5. 0xfff7a000 0x00000910
9468 22:58:45.325135 VBOOT WORK 6. 0xfff66000 0x00014000
9469 22:58:45.328345 RAMOOPS 7. 0xffe66000 0x00100000
9470 22:58:45.331748 COREBOOT 8. 0xffe64000 0x00002000
9471 22:58:45.335104 IMD small region:
9472 22:58:45.338083 IMD ROOT 0. 0xffffec00 0x00000400
9473 22:58:45.341493 VPD 1. 0xffffeba0 0x0000004c
9474 22:58:45.344902 MMC STATUS 2. 0xffffeb80 0x00000004
9475 22:58:45.351227 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9476 22:58:45.351310 Probing TPM: done!
9477 22:58:45.358030 Connected to device vid:did:rid of 1ae0:0028:00
9478 22:58:45.364905 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9479 22:58:45.367876 Initialized TPM device CR50 revision 0
9480 22:58:45.371320 Checking cr50 for pending updates
9481 22:58:45.377141 Reading cr50 TPM mode
9482 22:58:45.385613 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9483 22:58:45.392024 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9484 22:58:45.432323 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9485 22:58:45.435382 Checking segment from ROM address 0x40100000
9486 22:58:45.438758 Checking segment from ROM address 0x4010001c
9487 22:58:45.445198 Loading segment from ROM address 0x40100000
9488 22:58:45.445281 code (compression=0)
9489 22:58:45.455384 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9490 22:58:45.461690 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9491 22:58:45.461775 it's not compressed!
9492 22:58:45.468514 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9493 22:58:45.474875 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9494 22:58:45.492624 Loading segment from ROM address 0x4010001c
9495 22:58:45.492708 Entry Point 0x80000000
9496 22:58:45.496134 Loaded segments
9497 22:58:45.499040 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9498 22:58:45.505882 Jumping to boot code at 0x80000000(0xffe64000)
9499 22:58:45.512223 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9500 22:58:45.518807 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9501 22:58:45.527201 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9502 22:58:45.530493 Checking segment from ROM address 0x40100000
9503 22:58:45.533763 Checking segment from ROM address 0x4010001c
9504 22:58:45.540589 Loading segment from ROM address 0x40100000
9505 22:58:45.540686 code (compression=1)
9506 22:58:45.547166 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9507 22:58:45.556942 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9508 22:58:45.557025 using LZMA
9509 22:58:45.565241 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9510 22:58:45.572024 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9511 22:58:45.575421 Loading segment from ROM address 0x4010001c
9512 22:58:45.575504 Entry Point 0x54601000
9513 22:58:45.578441 Loaded segments
9514 22:58:45.582032 NOTICE: MT8192 bl31_setup
9515 22:58:45.589205 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9516 22:58:45.592049 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9517 22:58:45.595695 WARNING: region 0:
9518 22:58:45.598744 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9519 22:58:45.598827 WARNING: region 1:
9520 22:58:45.605651 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9521 22:58:45.608662 WARNING: region 2:
9522 22:58:45.612376 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9523 22:58:45.615718 WARNING: region 3:
9524 22:58:45.618605 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9525 22:58:45.622466 WARNING: region 4:
9526 22:58:45.629041 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9527 22:58:45.629124 WARNING: region 5:
9528 22:58:45.632299 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9529 22:58:45.635514 WARNING: region 6:
9530 22:58:45.638850 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9531 22:58:45.642016 WARNING: region 7:
9532 22:58:45.645491 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9533 22:58:45.651895 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9534 22:58:45.655551 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9535 22:58:45.658500 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9536 22:58:45.665273 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9537 22:58:45.669149 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9538 22:58:45.672169 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9539 22:58:45.678977 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9540 22:58:45.682019 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9541 22:58:45.688950 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9542 22:58:45.691936 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9543 22:58:45.695241 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9544 22:58:45.702215 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9545 22:58:45.705582 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9546 22:58:45.708483 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9547 22:58:45.715194 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9548 22:58:45.718621 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9549 22:58:45.725444 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9550 22:58:45.728597 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9551 22:58:45.731887 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9552 22:58:45.738374 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9553 22:58:45.741940 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9554 22:58:45.745071 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9555 22:58:45.751872 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9556 22:58:45.754857 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9557 22:58:45.761694 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9558 22:58:45.765122 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9559 22:58:45.771574 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9560 22:58:45.774972 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9561 22:58:45.778093 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9562 22:58:45.784895 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9563 22:58:45.788297 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9564 22:58:45.795199 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9565 22:58:45.798006 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9566 22:58:45.801368 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9567 22:58:45.804670 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9568 22:58:45.811548 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9569 22:58:45.814864 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9570 22:58:45.818320 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9571 22:58:45.821543 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9572 22:58:45.827966 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9573 22:58:45.831437 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9574 22:58:45.834597 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9575 22:58:45.837821 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9576 22:58:45.844539 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9577 22:58:45.847838 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9578 22:58:45.851427 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9579 22:58:45.854769 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9580 22:58:45.861174 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9581 22:58:45.864678 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9582 22:58:45.871087 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9583 22:58:45.874522 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9584 22:58:45.878004 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9585 22:58:45.884383 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9586 22:58:45.887716 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9587 22:58:45.894153 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9588 22:58:45.897493 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9589 22:58:45.904317 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9590 22:58:45.907460 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9591 22:58:45.910907 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9592 22:58:45.917440 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9593 22:58:45.920913 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9594 22:58:45.927266 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9595 22:58:45.930634 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9596 22:58:45.937523 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9597 22:58:45.940833 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9598 22:58:45.947462 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9599 22:58:45.950861 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9600 22:58:45.954300 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9601 22:58:45.960813 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9602 22:58:45.964151 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9603 22:58:45.970715 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9604 22:58:45.974215 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9605 22:58:45.980484 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9606 22:58:45.983896 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9607 22:58:45.987016 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9608 22:58:45.993836 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9609 22:58:45.997292 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9610 22:58:46.003880 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9611 22:58:46.007348 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9612 22:58:46.013533 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9613 22:58:46.016835 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9614 22:58:46.023508 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9615 22:58:46.026923 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9616 22:58:46.030235 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9617 22:58:46.037210 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9618 22:58:46.040615 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9619 22:58:46.047033 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9620 22:58:46.050347 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9621 22:58:46.053891 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9622 22:58:46.060178 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9623 22:58:46.064026 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9624 22:58:46.070221 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9625 22:58:46.073643 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9626 22:58:46.080251 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9627 22:58:46.083373 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9628 22:58:46.089928 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9629 22:58:46.093340 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9630 22:58:46.096822 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9631 22:58:46.100367 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9632 22:58:46.107085 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9633 22:58:46.110075 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9634 22:58:46.113517 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9635 22:58:46.119828 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9636 22:58:46.123382 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9637 22:58:46.130076 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9638 22:58:46.133432 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9639 22:58:46.136367 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9640 22:58:46.143538 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9641 22:58:46.146395 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9642 22:58:46.152982 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9643 22:58:46.156489 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9644 22:58:46.159906 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9645 22:58:46.166211 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9646 22:58:46.169861 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9647 22:58:46.176265 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9648 22:58:46.179680 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9649 22:58:46.183145 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9650 22:58:46.186470 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9651 22:58:46.193156 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9652 22:58:46.196253 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9653 22:58:46.199599 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9654 22:58:46.205997 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9655 22:58:46.209914 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9656 22:58:46.212909 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9657 22:58:46.215897 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9658 22:58:46.222659 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9659 22:58:46.226046 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9660 22:58:46.232759 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9661 22:58:46.236233 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9662 22:58:46.239525 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9663 22:58:46.246288 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9664 22:58:46.249207 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9665 22:58:46.255829 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9666 22:58:46.259201 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9667 22:58:46.262620 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9668 22:58:46.269229 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9669 22:58:46.272604 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9670 22:58:46.279162 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9671 22:58:46.282567 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9672 22:58:46.286164 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9673 22:58:46.292520 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9674 22:58:46.295752 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9675 22:58:46.302282 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9676 22:58:46.306205 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9677 22:58:46.309157 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9678 22:58:46.315724 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9679 22:58:46.319296 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9680 22:58:46.322251 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9681 22:58:46.329208 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9682 22:58:46.332109 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9683 22:58:46.338858 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9684 22:58:46.342154 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9685 22:58:46.345419 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9686 22:58:46.352247 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9687 22:58:46.355684 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9688 22:58:46.362128 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9689 22:58:46.365621 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9690 22:58:46.368525 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9691 22:58:46.375346 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9692 22:58:46.378585 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9693 22:58:46.385099 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9694 22:58:46.388512 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9695 22:58:46.392040 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9696 22:58:46.398659 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9697 22:58:46.401758 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9698 22:58:46.408559 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9699 22:58:46.411871 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9700 22:58:46.415140 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9701 22:58:46.421781 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9702 22:58:46.424606 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9703 22:58:46.431668 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9704 22:58:46.435068 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9705 22:58:46.438017 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9706 22:58:46.444666 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9707 22:58:46.447939 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9708 22:58:46.454696 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9709 22:58:46.457617 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9710 22:58:46.461355 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9711 22:58:46.468047 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9712 22:58:46.470846 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9713 22:58:46.477552 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9714 22:58:46.481042 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9715 22:58:46.484231 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9716 22:58:46.490872 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9717 22:58:46.494346 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9718 22:58:46.500720 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9719 22:58:46.504184 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9720 22:58:46.507544 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9721 22:58:46.513960 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9722 22:58:46.517634 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9723 22:58:46.524064 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9724 22:58:46.527106 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9725 22:58:46.534114 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9726 22:58:46.537520 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9727 22:58:46.540459 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9728 22:58:46.547253 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9729 22:58:46.550139 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9730 22:58:46.557032 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9731 22:58:46.560007 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9732 22:58:46.563606 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9733 22:58:46.570107 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9734 22:58:46.573476 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9735 22:58:46.580099 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9736 22:58:46.583485 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9737 22:58:46.589972 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9738 22:58:46.593353 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9739 22:58:46.596757 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9740 22:58:46.603467 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9741 22:58:46.606743 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9742 22:58:46.613059 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9743 22:58:46.616488 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9744 22:58:46.623366 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9745 22:58:46.626196 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9746 22:58:46.629465 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9747 22:58:46.636151 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9748 22:58:46.639432 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9749 22:58:46.646469 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9750 22:58:46.649686 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9751 22:58:46.655780 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9752 22:58:46.659225 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9753 22:58:46.662748 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9754 22:58:46.669436 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9755 22:58:46.672664 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9756 22:58:46.679059 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9757 22:58:46.682538 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9758 22:58:46.688914 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9759 22:58:46.692325 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9760 22:58:46.695453 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9761 22:58:46.702284 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9762 22:58:46.705726 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9763 22:58:46.709066 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9764 22:58:46.712236 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9765 22:58:46.718618 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9766 22:58:46.721970 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9767 22:58:46.725226 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9768 22:58:46.731764 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9769 22:58:46.735423 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9770 22:58:46.741674 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9771 22:58:46.745020 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9772 22:58:46.748474 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9773 22:58:46.754960 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9774 22:58:46.758459 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9775 22:58:46.761827 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9776 22:58:46.768369 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9777 22:58:46.771415 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9778 22:58:46.774811 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9779 22:58:46.781609 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9780 22:58:46.785036 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9781 22:58:46.787943 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9782 22:58:46.794530 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9783 22:58:46.797808 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9784 22:58:46.804403 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9785 22:58:46.807894 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9786 22:58:46.810874 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9787 22:58:46.817618 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9788 22:58:46.821074 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9789 22:58:46.827476 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9790 22:58:46.831132 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9791 22:58:46.834029 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9792 22:58:46.840794 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9793 22:58:46.844070 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9794 22:58:46.847307 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9795 22:58:46.854090 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9796 22:58:46.857150 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9797 22:58:46.863898 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9798 22:58:46.867092 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9799 22:58:46.870488 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9800 22:58:46.877013 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9801 22:58:46.880017 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9802 22:58:46.883622 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9803 22:58:46.886936 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9804 22:58:46.893433 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9805 22:58:46.896956 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9806 22:58:46.899936 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9807 22:58:46.903253 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9808 22:58:46.910009 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9809 22:58:46.913017 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9810 22:58:46.916343 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9811 22:58:46.919589 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9812 22:58:46.926334 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9813 22:58:46.929687 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9814 22:58:46.933094 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9815 22:58:46.939838 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9816 22:58:46.942711 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9817 22:58:46.949574 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9818 22:58:46.952946 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9819 22:58:46.956391 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9820 22:58:46.962928 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9821 22:58:46.966179 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9822 22:58:46.972644 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9823 22:58:46.976175 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9824 22:58:46.979580 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9825 22:58:46.985830 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9826 22:58:46.989475 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9827 22:58:46.996055 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9828 22:58:46.999428 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9829 22:58:47.005670 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9830 22:58:47.008941 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9831 22:58:47.012473 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9832 22:58:47.018703 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9833 22:58:47.022394 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9834 22:58:47.028979 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9835 22:58:47.032022 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9836 22:58:47.038708 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9837 22:58:47.042021 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9838 22:58:47.045474 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9839 22:58:47.052112 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9840 22:58:47.055095 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9841 22:58:47.061653 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9842 22:58:47.065020 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9843 22:58:47.068393 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9844 22:58:47.075131 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9845 22:58:47.078619 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9846 22:58:47.085090 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9847 22:58:47.088340 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9848 22:58:47.091719 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9849 22:58:47.098173 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9850 22:58:47.101678 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9851 22:58:47.107998 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9852 22:58:47.111137 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9853 22:58:47.118092 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9854 22:58:47.121457 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9855 22:58:47.124410 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9856 22:58:47.131458 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9857 22:58:47.134416 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9858 22:58:47.141425 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9859 22:58:47.144650 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9860 22:58:47.151115 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9861 22:58:47.154526 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9862 22:58:47.157849 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9863 22:58:47.164396 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9864 22:58:47.167875 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9865 22:58:47.174480 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9866 22:58:47.177801 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9867 22:58:47.181271 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9868 22:58:47.187486 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9869 22:58:47.190884 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9870 22:58:47.197482 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9871 22:58:47.200701 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9872 22:58:47.204119 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9873 22:58:47.210484 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9874 22:58:47.213829 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9875 22:58:47.220578 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9876 22:58:47.223574 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9877 22:58:47.230332 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9878 22:58:47.233619 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9879 22:58:47.237078 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9880 22:58:47.243399 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9881 22:58:47.246761 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9882 22:58:47.253430 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9883 22:58:47.256943 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9884 22:58:47.263487 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9885 22:58:47.266599 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9886 22:58:47.269797 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9887 22:58:47.276578 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9888 22:58:47.279908 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9889 22:58:47.286261 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9890 22:58:47.289664 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9891 22:58:47.296387 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9892 22:58:47.299377 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9893 22:58:47.305999 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9894 22:58:47.309516 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9895 22:58:47.312976 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9896 22:58:47.319505 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9897 22:58:47.322421 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9898 22:58:47.329366 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9899 22:58:47.332701 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9900 22:58:47.339150 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9901 22:58:47.342586 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9902 22:58:47.345516 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9903 22:58:47.352227 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9904 22:58:47.355627 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9905 22:58:47.362005 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9906 22:58:47.365443 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9907 22:58:47.372163 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9908 22:58:47.375444 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9909 22:58:47.382193 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9910 22:58:47.385249 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9911 22:58:47.388620 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9912 22:58:47.395420 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9913 22:58:47.398385 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9914 22:58:47.405086 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9915 22:58:47.408212 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9916 22:58:47.414895 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9917 22:58:47.418186 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9918 22:58:47.421512 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9919 22:58:47.428236 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9920 22:58:47.431597 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9921 22:58:47.438354 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9922 22:58:47.441593 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9923 22:58:47.448342 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9924 22:58:47.451264 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9925 22:58:47.457969 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9926 22:58:47.461490 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9927 22:58:47.464463 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9928 22:58:47.471301 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9929 22:58:47.474596 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9930 22:58:47.480871 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9931 22:58:47.484141 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9932 22:58:47.490761 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9933 22:58:47.494476 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9934 22:58:47.497770 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9935 22:58:47.504345 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9936 22:58:47.507253 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9937 22:58:47.514366 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9938 22:58:47.517365 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9939 22:58:47.524118 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9940 22:58:47.527304 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9941 22:58:47.534103 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9942 22:58:47.537019 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9943 22:58:47.543754 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9944 22:58:47.547111 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9945 22:58:47.554007 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9946 22:58:47.557340 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9947 22:58:47.563540 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9948 22:58:47.567015 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9949 22:58:47.573354 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9950 22:58:47.576753 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9951 22:58:47.583437 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9952 22:58:47.586898 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9953 22:58:47.590404 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9954 22:58:47.596886 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9955 22:58:47.600132 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9956 22:58:47.606764 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9957 22:58:47.610255 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9958 22:58:47.616774 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9959 22:58:47.622978 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9960 22:58:47.626422 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9961 22:58:47.633173 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9962 22:58:47.636517 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9963 22:58:47.642864 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9964 22:58:47.646246 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9965 22:58:47.652912 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9966 22:58:47.655931 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9967 22:58:47.659468 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9968 22:58:47.662770 INFO: [APUAPC] vio 0
9969 22:58:47.669241 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9970 22:58:47.672633 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9971 22:58:47.676111 INFO: [APUAPC] D0_APC_0: 0x400510
9972 22:58:47.679536 INFO: [APUAPC] D0_APC_1: 0x0
9973 22:58:47.682399 INFO: [APUAPC] D0_APC_2: 0x1540
9974 22:58:47.685754 INFO: [APUAPC] D0_APC_3: 0x0
9975 22:58:47.689438 INFO: [APUAPC] D1_APC_0: 0xffffffff
9976 22:58:47.692298 INFO: [APUAPC] D1_APC_1: 0xffffffff
9977 22:58:47.695651 INFO: [APUAPC] D1_APC_2: 0x3fffff
9978 22:58:47.698968 INFO: [APUAPC] D1_APC_3: 0x0
9979 22:58:47.702374 INFO: [APUAPC] D2_APC_0: 0xffffffff
9980 22:58:47.705392 INFO: [APUAPC] D2_APC_1: 0xffffffff
9981 22:58:47.708926 INFO: [APUAPC] D2_APC_2: 0x3fffff
9982 22:58:47.709010 INFO: [APUAPC] D2_APC_3: 0x0
9983 22:58:47.715769 INFO: [APUAPC] D3_APC_0: 0xffffffff
9984 22:58:47.718696 INFO: [APUAPC] D3_APC_1: 0xffffffff
9985 22:58:47.721932 INFO: [APUAPC] D3_APC_2: 0x3fffff
9986 22:58:47.722016 INFO: [APUAPC] D3_APC_3: 0x0
9987 22:58:47.725368 INFO: [APUAPC] D4_APC_0: 0xffffffff
9988 22:58:47.732208 INFO: [APUAPC] D4_APC_1: 0xffffffff
9989 22:58:47.735467 INFO: [APUAPC] D4_APC_2: 0x3fffff
9990 22:58:47.735611 INFO: [APUAPC] D4_APC_3: 0x0
9991 22:58:47.738338 INFO: [APUAPC] D5_APC_0: 0xffffffff
9992 22:58:47.741852 INFO: [APUAPC] D5_APC_1: 0xffffffff
9993 22:58:47.745290 INFO: [APUAPC] D5_APC_2: 0x3fffff
9994 22:58:47.748729 INFO: [APUAPC] D5_APC_3: 0x0
9995 22:58:47.752047 INFO: [APUAPC] D6_APC_0: 0xffffffff
9996 22:58:47.754874 INFO: [APUAPC] D6_APC_1: 0xffffffff
9997 22:58:47.758298 INFO: [APUAPC] D6_APC_2: 0x3fffff
9998 22:58:47.761685 INFO: [APUAPC] D6_APC_3: 0x0
9999 22:58:47.765144 INFO: [APUAPC] D7_APC_0: 0xffffffff
10000 22:58:47.768361 INFO: [APUAPC] D7_APC_1: 0xffffffff
10001 22:58:47.771810 INFO: [APUAPC] D7_APC_2: 0x3fffff
10002 22:58:47.775327 INFO: [APUAPC] D7_APC_3: 0x0
10003 22:58:47.778123 INFO: [APUAPC] D8_APC_0: 0xffffffff
10004 22:58:47.781588 INFO: [APUAPC] D8_APC_1: 0xffffffff
10005 22:58:47.784831 INFO: [APUAPC] D8_APC_2: 0x3fffff
10006 22:58:47.788222 INFO: [APUAPC] D8_APC_3: 0x0
10007 22:58:47.791596 INFO: [APUAPC] D9_APC_0: 0xffffffff
10008 22:58:47.794943 INFO: [APUAPC] D9_APC_1: 0xffffffff
10009 22:58:47.797863 INFO: [APUAPC] D9_APC_2: 0x3fffff
10010 22:58:47.801219 INFO: [APUAPC] D9_APC_3: 0x0
10011 22:58:47.804552 INFO: [APUAPC] D10_APC_0: 0xffffffff
10012 22:58:47.807846 INFO: [APUAPC] D10_APC_1: 0xffffffff
10013 22:58:47.811168 INFO: [APUAPC] D10_APC_2: 0x3fffff
10014 22:58:47.814282 INFO: [APUAPC] D10_APC_3: 0x0
10015 22:58:47.817827 INFO: [APUAPC] D11_APC_0: 0xffffffff
10016 22:58:47.821112 INFO: [APUAPC] D11_APC_1: 0xffffffff
10017 22:58:47.824257 INFO: [APUAPC] D11_APC_2: 0x3fffff
10018 22:58:47.827651 INFO: [APUAPC] D11_APC_3: 0x0
10019 22:58:47.831061 INFO: [APUAPC] D12_APC_0: 0xffffffff
10020 22:58:47.834395 INFO: [APUAPC] D12_APC_1: 0xffffffff
10021 22:58:47.837691 INFO: [APUAPC] D12_APC_2: 0x3fffff
10022 22:58:47.840828 INFO: [APUAPC] D12_APC_3: 0x0
10023 22:58:47.844319 INFO: [APUAPC] D13_APC_0: 0xffffffff
10024 22:58:47.847363 INFO: [APUAPC] D13_APC_1: 0xffffffff
10025 22:58:47.850787 INFO: [APUAPC] D13_APC_2: 0x3fffff
10026 22:58:47.854265 INFO: [APUAPC] D13_APC_3: 0x0
10027 22:58:47.857517 INFO: [APUAPC] D14_APC_0: 0xffffffff
10028 22:58:47.860917 INFO: [APUAPC] D14_APC_1: 0xffffffff
10029 22:58:47.863910 INFO: [APUAPC] D14_APC_2: 0x3fffff
10030 22:58:47.867288 INFO: [APUAPC] D14_APC_3: 0x0
10031 22:58:47.870636 INFO: [APUAPC] D15_APC_0: 0xffffffff
10032 22:58:47.873918 INFO: [APUAPC] D15_APC_1: 0xffffffff
10033 22:58:47.877245 INFO: [APUAPC] D15_APC_2: 0x3fffff
10034 22:58:47.880751 INFO: [APUAPC] D15_APC_3: 0x0
10035 22:58:47.883669 INFO: [APUAPC] APC_CON: 0x4
10036 22:58:47.887266 INFO: [NOCDAPC] D0_APC_0: 0x0
10037 22:58:47.890654 INFO: [NOCDAPC] D0_APC_1: 0x0
10038 22:58:47.894065 INFO: [NOCDAPC] D1_APC_0: 0x0
10039 22:58:47.897256 INFO: [NOCDAPC] D1_APC_1: 0xfff
10040 22:58:47.900613 INFO: [NOCDAPC] D2_APC_0: 0x0
10041 22:58:47.903739 INFO: [NOCDAPC] D2_APC_1: 0xfff
10042 22:58:47.903824 INFO: [NOCDAPC] D3_APC_0: 0x0
10043 22:58:47.907093 INFO: [NOCDAPC] D3_APC_1: 0xfff
10044 22:58:47.910442 INFO: [NOCDAPC] D4_APC_0: 0x0
10045 22:58:47.913774 INFO: [NOCDAPC] D4_APC_1: 0xfff
10046 22:58:47.917180 INFO: [NOCDAPC] D5_APC_0: 0x0
10047 22:58:47.920386 INFO: [NOCDAPC] D5_APC_1: 0xfff
10048 22:58:47.923618 INFO: [NOCDAPC] D6_APC_0: 0x0
10049 22:58:47.927029 INFO: [NOCDAPC] D6_APC_1: 0xfff
10050 22:58:47.930068 INFO: [NOCDAPC] D7_APC_0: 0x0
10051 22:58:47.933750 INFO: [NOCDAPC] D7_APC_1: 0xfff
10052 22:58:47.936753 INFO: [NOCDAPC] D8_APC_0: 0x0
10053 22:58:47.940201 INFO: [NOCDAPC] D8_APC_1: 0xfff
10054 22:58:47.940303 INFO: [NOCDAPC] D9_APC_0: 0x0
10055 22:58:47.943507 INFO: [NOCDAPC] D9_APC_1: 0xfff
10056 22:58:47.946776 INFO: [NOCDAPC] D10_APC_0: 0x0
10057 22:58:47.950266 INFO: [NOCDAPC] D10_APC_1: 0xfff
10058 22:58:47.953580 INFO: [NOCDAPC] D11_APC_0: 0x0
10059 22:58:47.956937 INFO: [NOCDAPC] D11_APC_1: 0xfff
10060 22:58:47.960274 INFO: [NOCDAPC] D12_APC_0: 0x0
10061 22:58:47.963548 INFO: [NOCDAPC] D12_APC_1: 0xfff
10062 22:58:47.967050 INFO: [NOCDAPC] D13_APC_0: 0x0
10063 22:58:47.970075 INFO: [NOCDAPC] D13_APC_1: 0xfff
10064 22:58:47.973394 INFO: [NOCDAPC] D14_APC_0: 0x0
10065 22:58:47.976529 INFO: [NOCDAPC] D14_APC_1: 0xfff
10066 22:58:47.979943 INFO: [NOCDAPC] D15_APC_0: 0x0
10067 22:58:47.982909 INFO: [NOCDAPC] D15_APC_1: 0xfff
10068 22:58:47.986204 INFO: [NOCDAPC] APC_CON: 0x4
10069 22:58:47.989606 INFO: [APUAPC] set_apusys_apc done
10070 22:58:47.989712 INFO: [DEVAPC] devapc_init done
10071 22:58:47.996373 INFO: GICv3 without legacy support detected.
10072 22:58:47.999296 INFO: ARM GICv3 driver initialized in EL3
10073 22:58:48.002892 INFO: Maximum SPI INTID supported: 639
10074 22:58:48.006352 INFO: BL31: Initializing runtime services
10075 22:58:48.012640 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10076 22:58:48.016066 INFO: SPM: enable CPC mode
10077 22:58:48.019379 INFO: mcdi ready for mcusys-off-idle and system suspend
10078 22:58:48.025777 INFO: BL31: Preparing for EL3 exit to normal world
10079 22:58:48.029342 INFO: Entry point address = 0x80000000
10080 22:58:48.032517 INFO: SPSR = 0x8
10081 22:58:48.036887
10082 22:58:48.036993
10083 22:58:48.037087
10084 22:58:48.040225 Starting depthcharge on Spherion...
10085 22:58:48.040323
10086 22:58:48.040415 Wipe memory regions:
10087 22:58:48.040508
10088 22:58:48.041333 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10089 22:58:48.041469 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10090 22:58:48.041589 Setting prompt string to ['asurada:']
10091 22:58:48.041707 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10092 22:58:48.043635 [0x00000040000000, 0x00000054600000)
10093 22:58:48.165820
10094 22:58:48.165974 [0x00000054660000, 0x00000080000000)
10095 22:58:48.426597
10096 22:58:48.426773 [0x000000821a7280, 0x000000ffe64000)
10097 22:58:49.171493
10098 22:58:49.171648 [0x00000100000000, 0x00000240000000)
10099 22:58:51.061871
10100 22:58:51.064890 Initializing XHCI USB controller at 0x11200000.
10101 22:58:52.103913
10102 22:58:52.106952 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10103 22:58:52.107046
10104 22:58:52.107113
10105 22:58:52.107173
10106 22:58:52.107450 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10108 22:58:52.207768 asurada: tftpboot 192.168.201.1 10597663/tftp-deploy-1ioyhets/kernel/image.itb 10597663/tftp-deploy-1ioyhets/kernel/cmdline
10109 22:58:52.207904 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10110 22:58:52.207986 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10111 22:58:52.211872 tftpboot 192.168.201.1 10597663/tftp-deploy-1ioyhets/kernel/image.itp-deploy-1ioyhets/kernel/cmdline
10112 22:58:52.211958
10113 22:58:52.212023 Waiting for link
10114 22:58:52.372592
10115 22:58:52.372733 R8152: Initializing
10116 22:58:52.372842
10117 22:58:52.375585 Version 9 (ocp_data = 6010)
10118 22:58:52.375669
10119 22:58:52.378880 R8152: Done initializing
10120 22:58:52.378963
10121 22:58:52.379027 Adding net device
10122 22:58:54.325192
10123 22:58:54.325347 done.
10124 22:58:54.325415
10125 22:58:54.325475 MAC: 00:e0:4c:72:2d:d6
10126 22:58:54.325534
10127 22:58:54.328453 Sending DHCP discover... done.
10128 22:58:54.328537
10129 22:58:54.331843 Waiting for reply... done.
10130 22:58:54.331926
10131 22:58:54.335280 Sending DHCP request... done.
10132 22:58:54.335362
10133 22:58:54.338622 Waiting for reply... done.
10134 22:58:54.338705
10135 22:58:54.338769 My ip is 192.168.201.21
10136 22:58:54.338829
10137 22:58:54.341904 The DHCP server ip is 192.168.201.1
10138 22:58:54.341987
10139 22:58:54.348838 TFTP server IP predefined by user: 192.168.201.1
10140 22:58:54.348921
10141 22:58:54.355134 Bootfile predefined by user: 10597663/tftp-deploy-1ioyhets/kernel/image.itb
10142 22:58:54.355218
10143 22:58:54.358518 Sending tftp read request... done.
10144 22:58:54.358601
10145 22:58:54.361872 Waiting for the transfer...
10146 22:58:54.361954
10147 22:58:54.646455 00000000 ################################################################
10148 22:58:54.646604
10149 22:58:54.909414 00080000 ################################################################
10150 22:58:54.909553
10151 22:58:55.166794 00100000 ################################################################
10152 22:58:55.166936
10153 22:58:55.452078 00180000 ################################################################
10154 22:58:55.452222
10155 22:58:55.719013 00200000 ################################################################
10156 22:58:55.719162
10157 22:58:55.993705 00280000 ################################################################
10158 22:58:55.993851
10159 22:58:56.320540 00300000 ################################################################
10160 22:58:56.320719
10161 22:58:56.694469 00380000 ################################################################
10162 22:58:56.694621
10163 22:58:57.021497 00400000 ################################################################
10164 22:58:57.021648
10165 22:58:57.309374 00480000 ################################################################
10166 22:58:57.309527
10167 22:58:57.578351 00500000 ################################################################
10168 22:58:57.578503
10169 22:58:57.842182 00580000 ################################################################
10170 22:58:57.842356
10171 22:58:58.120957 00600000 ################################################################
10172 22:58:58.121143
10173 22:58:58.401843 00680000 ################################################################
10174 22:58:58.401997
10175 22:58:58.680286 00700000 ################################################################
10176 22:58:58.680470
10177 22:58:58.944663 00780000 ################################################################
10178 22:58:58.944823
10179 22:58:59.231037 00800000 ################################################################
10180 22:58:59.231216
10181 22:58:59.512077 00880000 ################################################################
10182 22:58:59.512260
10183 22:58:59.782892 00900000 ################################################################
10184 22:58:59.783045
10185 22:59:00.062986 00980000 ################################################################
10186 22:59:00.063137
10187 22:59:00.339015 00a00000 ################################################################
10188 22:59:00.339165
10189 22:59:00.612599 00a80000 ################################################################
10190 22:59:00.612799
10191 22:59:00.902665 00b00000 ################################################################
10192 22:59:00.902841
10193 22:59:01.178311 00b80000 ################################################################
10194 22:59:01.178490
10195 22:59:01.510969 00c00000 ################################################################
10196 22:59:01.511160
10197 22:59:01.844315 00c80000 ################################################################
10198 22:59:01.844491
10199 22:59:02.119545 00d00000 ################################################################
10200 22:59:02.119710
10201 22:59:02.399283 00d80000 ################################################################
10202 22:59:02.399457
10203 22:59:02.687164 00e00000 ################################################################
10204 22:59:02.687339
10205 22:59:02.987625 00e80000 ################################################################
10206 22:59:02.987779
10207 22:59:03.275081 00f00000 ################################################################
10208 22:59:03.275244
10209 22:59:03.552889 00f80000 ################################################################
10210 22:59:03.553025
10211 22:59:03.819752 01000000 ################################################################
10212 22:59:03.819913
10213 22:59:04.074279 01080000 ################################################################
10214 22:59:04.074465
10215 22:59:04.326712 01100000 ################################################################
10216 22:59:04.326869
10217 22:59:04.579031 01180000 ################################################################
10218 22:59:04.579189
10219 22:59:04.831387 01200000 ################################################################
10220 22:59:04.831539
10221 22:59:05.095434 01280000 ################################################################
10222 22:59:05.095587
10223 22:59:05.355782 01300000 ################################################################
10224 22:59:05.355925
10225 22:59:05.645320 01380000 ################################################################
10226 22:59:05.645476
10227 22:59:05.935272 01400000 ################################################################
10228 22:59:05.935430
10229 22:59:06.207320 01480000 ################################################################
10230 22:59:06.207480
10231 22:59:06.471113 01500000 ################################################################
10232 22:59:06.471251
10233 22:59:06.800753 01580000 ################################################################
10234 22:59:06.800893
10235 22:59:07.056955 01600000 ################################################################
10236 22:59:07.057087
10237 22:59:07.329073 01680000 ################################################################
10238 22:59:07.329207
10239 22:59:07.578157 01700000 ################################################################
10240 22:59:07.578290
10241 22:59:07.851897 01780000 ################################################################
10242 22:59:07.852025
10243 22:59:08.145819 01800000 ################################################################
10244 22:59:08.145975
10245 22:59:08.436027 01880000 ################################################################
10246 22:59:08.436223
10247 22:59:08.721900 01900000 ################################################################
10248 22:59:08.722046
10249 22:59:08.975785 01980000 ################################################################
10250 22:59:08.975920
10251 22:59:09.236196 01a00000 ################################################################ done.
10252 22:59:09.236339
10253 22:59:09.239696 The bootfile was 27780706 bytes long.
10254 22:59:09.239782
10255 22:59:09.243084 Sending tftp read request... done.
10256 22:59:09.243173
10257 22:59:09.246554 Waiting for the transfer...
10258 22:59:09.246650
10259 22:59:09.246726 00000000 # done.
10260 22:59:09.246799
10261 22:59:09.256470 Command line loaded dynamically from TFTP file: 10597663/tftp-deploy-1ioyhets/kernel/cmdline
10262 22:59:09.256694
10263 22:59:09.272671 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10597663/extract-nfsrootfs-15xou4fs,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10264 22:59:09.276083
10265 22:59:09.276283 Loading FIT.
10266 22:59:09.276420
10267 22:59:09.279740 Image ramdisk-1 has 17645803 bytes.
10268 22:59:09.280009
10269 22:59:09.282938 Image fdt-1 has 46924 bytes.
10270 22:59:09.283211
10271 22:59:09.286515 Image kernel-1 has 10085945 bytes.
10272 22:59:09.286856
10273 22:59:09.292717 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10274 22:59:09.293060
10275 22:59:09.312948 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10276 22:59:09.313747
10277 22:59:09.316306 Choosing best match conf-1 for compat google,spherion-rev2.
10278 22:59:09.320738
10279 22:59:09.325142 Connected to device vid:did:rid of 1ae0:0028:00
10280 22:59:09.332505
10281 22:59:09.335708 tpm_get_response: command 0x17b, return code 0x0
10282 22:59:09.336378
10283 22:59:09.338919 ec_init: CrosEC protocol v3 supported (256, 248)
10284 22:59:09.343494
10285 22:59:09.346718 tpm_cleanup: add release locality here.
10286 22:59:09.347183
10287 22:59:09.350027 Shutting down all USB controllers.
10288 22:59:09.350640
10289 22:59:09.351170 Removing current net device
10290 22:59:09.351731
10291 22:59:09.356917 Exiting depthcharge with code 4 at timestamp: 50604634
10292 22:59:09.357408
10293 22:59:09.360188 LZMA decompressing kernel-1 to 0x821a6718
10294 22:59:09.360857
10295 22:59:09.363356 LZMA decompressing kernel-1 to 0x40000000
10296 22:59:10.630234
10297 22:59:10.630790 jumping to kernel
10298 22:59:10.632361 end: 2.2.4 bootloader-commands (duration 00:00:23) [common]
10299 22:59:10.633053 start: 2.2.5 auto-login-action (timeout 00:04:03) [common]
10300 22:59:10.633481 Setting prompt string to ['Linux version [0-9]']
10301 22:59:10.633872 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10302 22:59:10.634253 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10303 22:59:10.711872
10304 22:59:10.715328 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10305 22:59:10.718950 start: 2.2.5.1 login-action (timeout 00:04:03) [common]
10306 22:59:10.719473 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10307 22:59:10.719896 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10308 22:59:10.720267 Using line separator: #'\n'#
10309 22:59:10.720582 No login prompt set.
10310 22:59:10.720969 Parsing kernel messages
10311 22:59:10.721472 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10312 22:59:10.722069 [login-action] Waiting for messages, (timeout 00:04:03)
10313 22:59:10.738767 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1612582-arm64-gcc-10-defconfig-arm64-chromebook-7xwc5) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 22:41:02 UTC 2023
10314 22:59:10.741379 [ 0.000000] random: crng init done
10315 22:59:10.745457 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10316 22:59:10.748489 [ 0.000000] efi: UEFI not found.
10317 22:59:10.758155 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10318 22:59:10.764699 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10319 22:59:10.774816 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10320 22:59:10.784827 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10321 22:59:10.791229 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10322 22:59:10.797804 [ 0.000000] printk: bootconsole [mtk8250] enabled
10323 22:59:10.804422 [ 0.000000] NUMA: No NUMA configuration found
10324 22:59:10.811174 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10325 22:59:10.814272 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10326 22:59:10.817905 [ 0.000000] Zone ranges:
10327 22:59:10.824259 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10328 22:59:10.827593 [ 0.000000] DMA32 empty
10329 22:59:10.834287 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10330 22:59:10.837740 [ 0.000000] Movable zone start for each node
10331 22:59:10.840838 [ 0.000000] Early memory node ranges
10332 22:59:10.847529 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10333 22:59:10.853914 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10334 22:59:10.860735 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10335 22:59:10.867216 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10336 22:59:10.870467 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10337 22:59:10.879918 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10338 22:59:10.935779 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10339 22:59:10.942723 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10340 22:59:10.949104 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10341 22:59:10.952372 [ 0.000000] psci: probing for conduit method from DT.
10342 22:59:10.958992 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10343 22:59:10.962418 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10344 22:59:10.968685 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10345 22:59:10.972401 [ 0.000000] psci: SMC Calling Convention v1.2
10346 22:59:10.978633 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10347 22:59:10.982417 [ 0.000000] Detected VIPT I-cache on CPU0
10348 22:59:10.989052 [ 0.000000] CPU features: detected: GIC system register CPU interface
10349 22:59:10.995262 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10350 22:59:11.001954 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10351 22:59:11.008887 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10352 22:59:11.018271 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10353 22:59:11.025063 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10354 22:59:11.028030 [ 0.000000] alternatives: applying boot alternatives
10355 22:59:11.034693 [ 0.000000] Fallback order for Node 0: 0
10356 22:59:11.041198 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10357 22:59:11.044906 [ 0.000000] Policy zone: Normal
10358 22:59:11.064521 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10597663/extract-nfsrootfs-15xou4fs,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10359 22:59:11.074124 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10360 22:59:11.086902 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10361 22:59:11.096868 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10362 22:59:11.103178 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10363 22:59:11.106054 <6>[ 0.000000] software IO TLB: area num 8.
10364 22:59:11.163220 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10365 22:59:11.312349 <6>[ 0.000000] Memory: 7955712K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397056K reserved, 32768K cma-reserved)
10366 22:59:11.319214 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10367 22:59:11.325701 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10368 22:59:11.329174 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10369 22:59:11.335992 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10370 22:59:11.342530 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10371 22:59:11.345603 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10372 22:59:11.355107 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10373 22:59:11.361996 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10374 22:59:11.368532 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10375 22:59:11.374928 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10376 22:59:11.378474 <6>[ 0.000000] GICv3: 608 SPIs implemented
10377 22:59:11.382208 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10378 22:59:11.388330 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10379 22:59:11.392083 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10380 22:59:11.398086 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10381 22:59:11.411114 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10382 22:59:11.424807 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10383 22:59:11.431059 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10384 22:59:11.439169 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10385 22:59:11.451922 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10386 22:59:11.458573 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10387 22:59:11.465536 <6>[ 0.009229] Console: colour dummy device 80x25
10388 22:59:11.475399 <6>[ 0.013956] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10389 22:59:11.482458 <6>[ 0.024397] pid_max: default: 32768 minimum: 301
10390 22:59:11.485376 <6>[ 0.029271] LSM: Security Framework initializing
10391 22:59:11.491700 <6>[ 0.034208] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10392 22:59:11.502070 <6>[ 0.042022] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10393 22:59:11.508519 <6>[ 0.051451] cblist_init_generic: Setting adjustable number of callback queues.
10394 22:59:11.515115 <6>[ 0.058905] cblist_init_generic: Setting shift to 3 and lim to 1.
10395 22:59:11.521758 <6>[ 0.065284] cblist_init_generic: Setting shift to 3 and lim to 1.
10396 22:59:11.528159 <6>[ 0.071691] rcu: Hierarchical SRCU implementation.
10397 22:59:11.534658 <6>[ 0.076704] rcu: Max phase no-delay instances is 1000.
10398 22:59:11.538307 <6>[ 0.083758] EFI services will not be available.
10399 22:59:11.545057 <6>[ 0.088731] smp: Bringing up secondary CPUs ...
10400 22:59:11.552242 <6>[ 0.093812] Detected VIPT I-cache on CPU1
10401 22:59:11.558838 <6>[ 0.093884] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10402 22:59:11.565794 <6>[ 0.093916] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10403 22:59:11.568851 <6>[ 0.094258] Detected VIPT I-cache on CPU2
10404 22:59:11.575646 <6>[ 0.094311] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10405 22:59:11.585349 <6>[ 0.094327] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10406 22:59:11.588581 <6>[ 0.094587] Detected VIPT I-cache on CPU3
10407 22:59:11.595779 <6>[ 0.094633] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10408 22:59:11.601721 <6>[ 0.094646] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10409 22:59:11.608303 <6>[ 0.094952] CPU features: detected: Spectre-v4
10410 22:59:11.611511 <6>[ 0.094959] CPU features: detected: Spectre-BHB
10411 22:59:11.615091 <6>[ 0.094964] Detected PIPT I-cache on CPU4
10412 22:59:11.622059 <6>[ 0.095020] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10413 22:59:11.627865 <6>[ 0.095036] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10414 22:59:11.634781 <6>[ 0.095331] Detected PIPT I-cache on CPU5
10415 22:59:11.641575 <6>[ 0.095393] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10416 22:59:11.648346 <6>[ 0.095409] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10417 22:59:11.651176 <6>[ 0.095694] Detected PIPT I-cache on CPU6
10418 22:59:11.657690 <6>[ 0.095760] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10419 22:59:11.664890 <6>[ 0.095776] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10420 22:59:11.671202 <6>[ 0.096071] Detected PIPT I-cache on CPU7
10421 22:59:11.677971 <6>[ 0.096136] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10422 22:59:11.684642 <6>[ 0.096152] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10423 22:59:11.687515 <6>[ 0.096198] smp: Brought up 1 node, 8 CPUs
10424 22:59:11.694265 <6>[ 0.237476] SMP: Total of 8 processors activated.
10425 22:59:11.697497 <6>[ 0.242397] CPU features: detected: 32-bit EL0 Support
10426 22:59:11.707150 <6>[ 0.247761] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10427 22:59:11.714236 <6>[ 0.256561] CPU features: detected: Common not Private translations
10428 22:59:11.720457 <6>[ 0.263077] CPU features: detected: CRC32 instructions
10429 22:59:11.724037 <6>[ 0.268428] CPU features: detected: RCpc load-acquire (LDAPR)
10430 22:59:11.730932 <6>[ 0.274387] CPU features: detected: LSE atomic instructions
10431 22:59:11.737099 <6>[ 0.280168] CPU features: detected: Privileged Access Never
10432 22:59:11.743663 <6>[ 0.285984] CPU features: detected: RAS Extension Support
10433 22:59:11.750276 <6>[ 0.291592] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10434 22:59:11.754072 <6>[ 0.298813] CPU: All CPU(s) started at EL2
10435 22:59:11.759955 <6>[ 0.303156] alternatives: applying system-wide alternatives
10436 22:59:11.770277 <6>[ 0.313823] devtmpfs: initialized
10437 22:59:11.782570 <6>[ 0.322698] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10438 22:59:11.791912 <6>[ 0.332665] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10439 22:59:11.798433 <6>[ 0.340678] pinctrl core: initialized pinctrl subsystem
10440 22:59:11.801625 <6>[ 0.347322] DMI not present or invalid.
10441 22:59:11.808364 <6>[ 0.351731] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10442 22:59:11.818544 <6>[ 0.358591] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10443 22:59:11.825023 <6>[ 0.366169] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10444 22:59:11.834870 <6>[ 0.374378] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10445 22:59:11.838389 <6>[ 0.382616] audit: initializing netlink subsys (disabled)
10446 22:59:11.848255 <5>[ 0.388307] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10447 22:59:11.854492 <6>[ 0.389016] thermal_sys: Registered thermal governor 'step_wise'
10448 22:59:11.861341 <6>[ 0.396275] thermal_sys: Registered thermal governor 'power_allocator'
10449 22:59:11.864297 <6>[ 0.402528] cpuidle: using governor menu
10450 22:59:11.871074 <6>[ 0.413487] NET: Registered PF_QIPCRTR protocol family
10451 22:59:11.877642 <6>[ 0.418973] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10452 22:59:11.884556 <6>[ 0.426077] ASID allocator initialised with 32768 entries
10453 22:59:11.887571 <6>[ 0.432635] Serial: AMBA PL011 UART driver
10454 22:59:11.897223 <4>[ 0.441271] Trying to register duplicate clock ID: 134
10455 22:59:11.951303 <6>[ 0.498528] KASLR enabled
10456 22:59:11.965787 <6>[ 0.506265] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10457 22:59:11.972389 <6>[ 0.513279] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10458 22:59:11.979071 <6>[ 0.519767] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10459 22:59:11.985152 <6>[ 0.526772] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10460 22:59:11.992039 <6>[ 0.533261] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10461 22:59:11.998574 <6>[ 0.540269] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10462 22:59:12.004837 <6>[ 0.546756] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10463 22:59:12.011644 <6>[ 0.553764] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10464 22:59:12.014824 <6>[ 0.561208] ACPI: Interpreter disabled.
10465 22:59:12.024061 <6>[ 0.567600] iommu: Default domain type: Translated
10466 22:59:12.030228 <6>[ 0.572714] iommu: DMA domain TLB invalidation policy: strict mode
10467 22:59:12.033552 <5>[ 0.579368] SCSI subsystem initialized
10468 22:59:12.040555 <6>[ 0.583534] usbcore: registered new interface driver usbfs
10469 22:59:12.047280 <6>[ 0.589269] usbcore: registered new interface driver hub
10470 22:59:12.050689 <6>[ 0.594819] usbcore: registered new device driver usb
10471 22:59:12.056704 <6>[ 0.600900] pps_core: LinuxPPS API ver. 1 registered
10472 22:59:12.066841 <6>[ 0.606092] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10473 22:59:12.070267 <6>[ 0.615434] PTP clock support registered
10474 22:59:12.073236 <6>[ 0.619673] EDAC MC: Ver: 3.0.0
10475 22:59:12.080929 <6>[ 0.624809] FPGA manager framework
10476 22:59:12.087523 <6>[ 0.628489] Advanced Linux Sound Architecture Driver Initialized.
10477 22:59:12.090984 <6>[ 0.635252] vgaarb: loaded
10478 22:59:12.097297 <6>[ 0.638420] clocksource: Switched to clocksource arch_sys_counter
10479 22:59:12.100667 <5>[ 0.644841] VFS: Disk quotas dquot_6.6.0
10480 22:59:12.107039 <6>[ 0.649023] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10481 22:59:12.110184 <6>[ 0.656212] pnp: PnP ACPI: disabled
10482 22:59:12.119120 <6>[ 0.662877] NET: Registered PF_INET protocol family
10483 22:59:12.129215 <6>[ 0.668457] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10484 22:59:12.140119 <6>[ 0.680757] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10485 22:59:12.149976 <6>[ 0.689571] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10486 22:59:12.156731 <6>[ 0.697542] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10487 22:59:12.166364 <6>[ 0.706238] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10488 22:59:12.173162 <6>[ 0.715985] TCP: Hash tables configured (established 65536 bind 65536)
10489 22:59:12.179439 <6>[ 0.722842] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10490 22:59:12.189101 <6>[ 0.730036] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10491 22:59:12.195828 <6>[ 0.737737] NET: Registered PF_UNIX/PF_LOCAL protocol family
10492 22:59:12.202338 <6>[ 0.743900] RPC: Registered named UNIX socket transport module.
10493 22:59:12.205673 <6>[ 0.750050] RPC: Registered udp transport module.
10494 22:59:12.212346 <6>[ 0.754983] RPC: Registered tcp transport module.
10495 22:59:12.218948 <6>[ 0.759914] RPC: Registered tcp NFSv4.1 backchannel transport module.
10496 22:59:12.222098 <6>[ 0.766586] PCI: CLS 0 bytes, default 64
10497 22:59:12.225146 <6>[ 0.770926] Unpacking initramfs...
10498 22:59:12.242562 <6>[ 0.783062] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10499 22:59:12.252334 <6>[ 0.791697] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10500 22:59:12.256136 <6>[ 0.800528] kvm [1]: IPA Size Limit: 40 bits
10501 22:59:12.262221 <6>[ 0.805056] kvm [1]: GICv3: no GICV resource entry
10502 22:59:12.265726 <6>[ 0.810076] kvm [1]: disabling GICv2 emulation
10503 22:59:12.272218 <6>[ 0.814760] kvm [1]: GIC system register CPU interface enabled
10504 22:59:12.275300 <6>[ 0.820920] kvm [1]: vgic interrupt IRQ18
10505 22:59:12.283038 <6>[ 0.826485] kvm [1]: VHE mode initialized successfully
10506 22:59:12.289127 <5>[ 0.832883] Initialise system trusted keyrings
10507 22:59:12.295652 <6>[ 0.837706] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10508 22:59:12.303534 <6>[ 0.847636] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10509 22:59:12.309983 <5>[ 0.854011] NFS: Registering the id_resolver key type
10510 22:59:12.313457 <5>[ 0.859316] Key type id_resolver registered
10511 22:59:12.320233 <5>[ 0.863730] Key type id_legacy registered
10512 22:59:12.326657 <6>[ 0.868012] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10513 22:59:12.333156 <6>[ 0.874930] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10514 22:59:12.339875 <6>[ 0.882694] 9p: Installing v9fs 9p2000 file system support
10515 22:59:12.376665 <5>[ 0.920559] Key type asymmetric registered
10516 22:59:12.379559 <5>[ 0.924894] Asymmetric key parser 'x509' registered
10517 22:59:12.389995 <6>[ 0.930048] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10518 22:59:12.393413 <6>[ 0.937664] io scheduler mq-deadline registered
10519 22:59:12.396532 <6>[ 0.942427] io scheduler kyber registered
10520 22:59:12.415274 <6>[ 0.959292] EINJ: ACPI disabled.
10521 22:59:12.447732 <4>[ 0.984826] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10522 22:59:12.457616 <4>[ 0.995444] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10523 22:59:12.472491 <6>[ 1.016314] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10524 22:59:12.480182 <6>[ 1.024431] printk: console [ttyS0] disabled
10525 22:59:12.508616 <6>[ 1.049081] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10526 22:59:12.515189 <6>[ 1.058561] printk: console [ttyS0] enabled
10527 22:59:12.518248 <6>[ 1.058561] printk: console [ttyS0] enabled
10528 22:59:12.524747 <6>[ 1.067455] printk: bootconsole [mtk8250] disabled
10529 22:59:12.528397 <6>[ 1.067455] printk: bootconsole [mtk8250] disabled
10530 22:59:12.534825 <6>[ 1.078783] SuperH (H)SCI(F) driver initialized
10531 22:59:12.538516 <6>[ 1.084038] msm_serial: driver initialized
10532 22:59:12.552232 <6>[ 1.092969] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10533 22:59:12.562060 <6>[ 1.101516] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10534 22:59:12.568442 <6>[ 1.110057] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10535 22:59:12.578608 <6>[ 1.118684] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10536 22:59:12.588723 <6>[ 1.127391] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10537 22:59:12.595561 <6>[ 1.136106] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10538 22:59:12.605423 <6>[ 1.144649] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10539 22:59:12.612116 <6>[ 1.153462] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10540 22:59:12.622096 <6>[ 1.162006] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10541 22:59:12.633606 <6>[ 1.177498] loop: module loaded
10542 22:59:12.640241 <6>[ 1.183461] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10543 22:59:12.662635 <4>[ 1.206737] mtk-pmic-keys: Failed to locate of_node [id: -1]
10544 22:59:12.669229 <6>[ 1.213545] megasas: 07.719.03.00-rc1
10545 22:59:12.678904 <6>[ 1.223077] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10546 22:59:12.689675 <6>[ 1.233799] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10547 22:59:12.706726 <6>[ 1.250515] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10548 22:59:12.767356 <6>[ 1.304778] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10549 22:59:12.951149 <6>[ 1.495246] Freeing initrd memory: 17228K
10550 22:59:12.961330 <6>[ 1.505368] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10551 22:59:12.971923 <6>[ 1.516163] tun: Universal TUN/TAP device driver, 1.6
10552 22:59:12.975508 <6>[ 1.522208] thunder_xcv, ver 1.0
10553 22:59:12.978630 <6>[ 1.525713] thunder_bgx, ver 1.0
10554 22:59:12.982314 <6>[ 1.529210] nicpf, ver 1.0
10555 22:59:12.992427 <6>[ 1.533199] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10556 22:59:12.995868 <6>[ 1.540675] hns3: Copyright (c) 2017 Huawei Corporation.
10557 22:59:13.002279 <6>[ 1.546272] hclge is initializing
10558 22:59:13.005484 <6>[ 1.549845] e1000: Intel(R) PRO/1000 Network Driver
10559 22:59:13.012507 <6>[ 1.554974] e1000: Copyright (c) 1999-2006 Intel Corporation.
10560 22:59:13.015823 <6>[ 1.560987] e1000e: Intel(R) PRO/1000 Network Driver
10561 22:59:13.022481 <6>[ 1.566203] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10562 22:59:13.028806 <6>[ 1.572388] igb: Intel(R) Gigabit Ethernet Network Driver
10563 22:59:13.035620 <6>[ 1.578038] igb: Copyright (c) 2007-2014 Intel Corporation.
10564 22:59:13.042263 <6>[ 1.583874] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10565 22:59:13.048842 <6>[ 1.590391] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10566 22:59:13.052246 <6>[ 1.596850] sky2: driver version 1.30
10567 22:59:13.058657 <6>[ 1.601824] VFIO - User Level meta-driver version: 0.3
10568 22:59:13.066056 <6>[ 1.610024] usbcore: registered new interface driver usb-storage
10569 22:59:13.072588 <6>[ 1.616473] usbcore: registered new device driver onboard-usb-hub
10570 22:59:13.081434 <6>[ 1.625568] mt6397-rtc mt6359-rtc: registered as rtc0
10571 22:59:13.091441 <6>[ 1.631033] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T22:59:10 UTC (1686005950)
10572 22:59:13.094748 <6>[ 1.640592] i2c_dev: i2c /dev entries driver
10573 22:59:13.111488 <6>[ 1.652172] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10574 22:59:13.118311 <6>[ 1.662352] sdhci: Secure Digital Host Controller Interface driver
10575 22:59:13.124996 <6>[ 1.668788] sdhci: Copyright(c) Pierre Ossman
10576 22:59:13.131763 <6>[ 1.674184] Synopsys Designware Multimedia Card Interface Driver
10577 22:59:13.134927 <6>[ 1.680795] mmc0: CQHCI version 5.10
10578 22:59:13.141431 <6>[ 1.681347] sdhci-pltfm: SDHCI platform and OF driver helper
10579 22:59:13.148665 <6>[ 1.692958] ledtrig-cpu: registered to indicate activity on CPUs
10580 22:59:13.159421 <6>[ 1.700374] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10581 22:59:13.162958 <6>[ 1.707798] usbcore: registered new interface driver usbhid
10582 22:59:13.169838 <6>[ 1.713631] usbhid: USB HID core driver
10583 22:59:13.175968 <6>[ 1.717890] spi_master spi0: will run message pump with realtime priority
10584 22:59:13.224394 <6>[ 1.761546] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10585 22:59:13.243334 <6>[ 1.776726] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10586 22:59:13.246855 <6>[ 1.790294] mmc0: Command Queue Engine enabled
10587 22:59:13.253231 <6>[ 1.792007] cros-ec-spi spi0.0: Chrome EC device registered
10588 22:59:13.256749 <6>[ 1.795030] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10589 22:59:13.264335 <6>[ 1.808211] mmcblk0: mmc0:0001 DA4128 116 GiB
10590 22:59:13.274569 <6>[ 1.818037] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10591 22:59:13.283895 <6>[ 1.820164] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10592 22:59:13.290447 <6>[ 1.825394] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10593 22:59:13.293834 <6>[ 1.835394] NET: Registered PF_PACKET protocol family
10594 22:59:13.300880 <6>[ 1.839125] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10595 22:59:13.303742 <6>[ 1.843915] 9pnet: Installing 9P2000 support
10596 22:59:13.310323 <6>[ 1.849676] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10597 22:59:13.316695 <5>[ 1.853597] Key type dns_resolver registered
10598 22:59:13.320591 <6>[ 1.865217] registered taskstats version 1
10599 22:59:13.326820 <5>[ 1.869664] Loading compiled-in X.509 certificates
10600 22:59:13.360410 <4>[ 1.897672] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10601 22:59:13.370206 <4>[ 1.908367] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10602 22:59:13.380108 <3>[ 1.921129] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10603 22:59:13.392651 <6>[ 1.936715] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10604 22:59:13.399528 <6>[ 1.943603] xhci-mtk 11200000.usb: xHCI Host Controller
10605 22:59:13.405986 <6>[ 1.949108] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10606 22:59:13.416080 <6>[ 1.956961] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10607 22:59:13.422689 <6>[ 1.966389] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10608 22:59:13.429644 <6>[ 1.972477] xhci-mtk 11200000.usb: xHCI Host Controller
10609 22:59:13.436032 <6>[ 1.977962] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10610 22:59:13.442719 <6>[ 1.985613] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10611 22:59:13.449291 <6>[ 1.993362] hub 1-0:1.0: USB hub found
10612 22:59:13.452573 <6>[ 1.997396] hub 1-0:1.0: 1 port detected
10613 22:59:13.462714 <6>[ 2.001730] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10614 22:59:13.465613 <6>[ 2.010338] hub 2-0:1.0: USB hub found
10615 22:59:13.469145 <6>[ 2.014354] hub 2-0:1.0: 1 port detected
10616 22:59:13.477525 <6>[ 2.021395] mtk-msdc 11f70000.mmc: Got CD GPIO
10617 22:59:13.495161 <6>[ 2.035985] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10618 22:59:13.501753 <6>[ 2.044023] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10619 22:59:13.511945 <4>[ 2.051999] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10620 22:59:13.521869 <6>[ 2.061654] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10621 22:59:13.528515 <6>[ 2.069738] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10622 22:59:13.535078 <6>[ 2.077774] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10623 22:59:13.545467 <6>[ 2.085691] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10624 22:59:13.551970 <6>[ 2.093513] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10625 22:59:13.561950 <6>[ 2.101336] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10626 22:59:13.571493 <6>[ 2.112064] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10627 22:59:13.578369 <6>[ 2.120432] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10628 22:59:13.588244 <6>[ 2.128786] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10629 22:59:13.594842 <6>[ 2.137129] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10630 22:59:13.604697 <6>[ 2.145473] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10631 22:59:13.611678 <6>[ 2.153815] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10632 22:59:13.621310 <6>[ 2.162158] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10633 22:59:13.631285 <6>[ 2.170502] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10634 22:59:13.637949 <6>[ 2.178844] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10635 22:59:13.647895 <6>[ 2.187187] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10636 22:59:13.654816 <6>[ 2.195531] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10637 22:59:13.664814 <6>[ 2.203874] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10638 22:59:13.670851 <6>[ 2.212218] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10639 22:59:13.680735 <6>[ 2.220566] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10640 22:59:13.687428 <6>[ 2.228913] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10641 22:59:13.694316 <6>[ 2.237810] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10642 22:59:13.704214 <6>[ 2.245255] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10643 22:59:13.711155 <6>[ 2.252309] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10644 22:59:13.717726 <6>[ 2.259435] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10645 22:59:13.724581 <6>[ 2.266705] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10646 22:59:13.734286 <6>[ 2.273612] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10647 22:59:13.743793 <6>[ 2.282754] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10648 22:59:13.750564 <6>[ 2.291881] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10649 22:59:13.760856 <6>[ 2.301183] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10650 22:59:13.770829 <6>[ 2.310657] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10651 22:59:13.780546 <6>[ 2.320132] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10652 22:59:13.790508 <6>[ 2.329259] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10653 22:59:13.800313 <6>[ 2.338734] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10654 22:59:13.807167 <6>[ 2.347862] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10655 22:59:13.816584 <6>[ 2.357163] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10656 22:59:13.826935 <6>[ 2.367330] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10657 22:59:13.837722 <6>[ 2.378820] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10658 22:59:13.844565 <6>[ 2.388538] Trying to probe devices needed for running init ...
10659 22:59:13.877590 <6>[ 2.418669] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10660 22:59:14.030482 <6>[ 2.574647] hub 1-1:1.0: USB hub found
10661 22:59:14.033813 <6>[ 2.579001] hub 1-1:1.0: 4 ports detected
10662 22:59:14.157898 <6>[ 2.699055] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10663 22:59:14.184563 <6>[ 2.728945] hub 2-1:1.0: USB hub found
10664 22:59:14.187858 <6>[ 2.733472] hub 2-1:1.0: 3 ports detected
10665 22:59:14.353645 <6>[ 2.894718] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10666 22:59:14.486236 <6>[ 3.030801] hub 1-1.4:1.0: USB hub found
10667 22:59:14.489526 <6>[ 3.035454] hub 1-1.4:1.0: 2 ports detected
10668 22:59:14.565694 <6>[ 3.106746] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10669 22:59:14.785731 <6>[ 3.326663] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10670 22:59:14.969594 <6>[ 3.510628] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10671 22:59:26.118043 <6>[ 14.667252] ALSA device list:
10672 22:59:26.124873 <6>[ 14.670509] No soundcards found.
10673 22:59:26.137419 <6>[ 14.682916] Freeing unused kernel memory: 8384K
10674 22:59:26.140204 <6>[ 14.687851] Run /init as init process
10675 22:59:26.150830 Loading, please wait...
10676 22:59:26.169878 Starting version 247.3-7+deb11u2
10677 22:59:26.514792 <6>[ 15.057393] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10678 22:59:26.529445 <3>[ 15.071588] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10679 22:59:26.536103 <3>[ 15.079748] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10680 22:59:26.542243 <6>[ 15.082011] remoteproc remoteproc0: scp is available
10681 22:59:26.549357 <3>[ 15.087846] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10682 22:59:26.558965 <3>[ 15.092588] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10683 22:59:26.569133 <4>[ 15.093205] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10684 22:59:26.575572 <3>[ 15.103714] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10685 22:59:26.582265 <6>[ 15.109354] remoteproc remoteproc0: powering up scp
10686 22:59:26.588605 <3>[ 15.119138] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10687 22:59:26.598984 <6>[ 15.122324] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10688 22:59:26.605485 <6>[ 15.122360] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10689 22:59:26.615586 <6>[ 15.122372] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10690 22:59:26.625177 <4>[ 15.127225] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10691 22:59:26.631894 <3>[ 15.132364] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10692 22:59:26.638594 <3>[ 15.140420] remoteproc remoteproc0: request_firmware failed: -2
10693 22:59:26.648358 <3>[ 15.148013] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10694 22:59:26.655166 <4>[ 15.160132] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10695 22:59:26.658922 <6>[ 15.165337] mc: Linux media interface: v0.10
10696 22:59:26.668322 <3>[ 15.169865] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10697 22:59:26.674837 <6>[ 15.170920] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10698 22:59:26.681487 <4>[ 15.175450] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10699 22:59:26.691161 <3>[ 15.184559] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10700 22:59:26.698467 <4>[ 15.196679] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10701 22:59:26.704912 <4>[ 15.196679] Fallback method does not support PEC.
10702 22:59:26.711606 <3>[ 15.197665] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10703 22:59:26.721481 <3>[ 15.223644] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10704 22:59:26.728367 <3>[ 15.225386] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10705 22:59:26.734739 <6>[ 15.237617] usbcore: registered new interface driver r8152
10706 22:59:26.741440 <3>[ 15.247991] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10707 22:59:26.748306 <6>[ 15.251218] videodev: Linux video capture interface: v2.00
10708 22:59:26.754735 <6>[ 15.269224] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10709 22:59:26.764541 <3>[ 15.271294] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10710 22:59:26.767983 <6>[ 15.279353] pci_bus 0000:00: root bus resource [bus 00-ff]
10711 22:59:26.778213 <3>[ 15.285051] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10712 22:59:26.787881 <6>[ 15.291060] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10713 22:59:26.794689 <6>[ 15.291468] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10714 22:59:26.804490 <6>[ 15.293121] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10715 22:59:26.811272 <3>[ 15.298867] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10716 22:59:26.817669 <3>[ 15.302643] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10717 22:59:26.827629 <6>[ 15.305724] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10718 22:59:26.837637 <3>[ 15.313826] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10719 22:59:26.843927 <3>[ 15.313885] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10720 22:59:26.853995 <3>[ 15.313940] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10721 22:59:26.857233 <6>[ 15.319572] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10722 22:59:26.867701 <6>[ 15.330744] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10723 22:59:26.874308 <6>[ 15.337797] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10724 22:59:26.883672 <4>[ 15.369717] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10725 22:59:26.887069 <6>[ 15.378667] pci 0000:00:00.0: supports D1 D2
10726 22:59:26.893613 <4>[ 15.387181] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10727 22:59:26.903744 <6>[ 15.395227] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10728 22:59:26.910112 <6>[ 15.397125] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10729 22:59:26.917081 <3>[ 15.406695] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10730 22:59:26.923485 <6>[ 15.409676] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10731 22:59:26.926965 <6>[ 15.466567] r8152 2-1.3:1.0 eth0: v1.12.13
10732 22:59:26.933351 <6>[ 15.467367] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10733 22:59:26.943234 <6>[ 15.485436] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10734 22:59:26.949651 <6>[ 15.492930] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10735 22:59:26.952846 <6>[ 15.500513] pci 0000:01:00.0: supports D1 D2
10736 22:59:26.959479 <6>[ 15.505054] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10737 22:59:26.968684 <3>[ 15.514807] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10738 22:59:26.979462 <3>[ 15.521704] elants_i2c 4-0010: (read fw id) unexpected response: ff ff
10739 22:59:26.985752 <6>[ 15.522604] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10740 22:59:26.992712 <6>[ 15.528666] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10741 22:59:27.002562 <6>[ 15.535382] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10742 22:59:27.009104 <6>[ 15.552754] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10743 22:59:27.018696 <6>[ 15.560793] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10744 22:59:27.025456 <6>[ 15.561282] usbcore: registered new interface driver cdc_ether
10745 22:59:27.031886 <6>[ 15.568811] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10746 22:59:27.038688 <6>[ 15.568832] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10747 22:59:27.045424 <6>[ 15.568851] pci 0000:00:00.0: PCI bridge to [bus 01]
10748 22:59:27.052161 <6>[ 15.583656] usbcore: registered new interface driver r8153_ecm
10749 22:59:27.055009 <6>[ 15.583677] Bluetooth: Core ver 2.22
10750 22:59:27.061908 <6>[ 15.583734] NET: Registered PF_BLUETOOTH protocol family
10751 22:59:27.068376 <6>[ 15.583737] Bluetooth: HCI device and connection manager initialized
10752 22:59:27.071981 <6>[ 15.583752] Bluetooth: HCI socket layer initialized
10753 22:59:27.078300 <6>[ 15.583757] Bluetooth: L2CAP socket layer initialized
10754 22:59:27.081653 <6>[ 15.583766] Bluetooth: SCO socket layer initialized
10755 22:59:27.091736 <6>[ 15.590973] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10756 22:59:27.097801 <6>[ 15.592365] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10757 22:59:27.111235 <6>[ 15.593715] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10758 22:59:27.117790 <6>[ 15.593880] usbcore: registered new interface driver uvcvideo
10759 22:59:27.120916 <6>[ 15.605649] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10760 22:59:27.127562 <6>[ 15.606315] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10761 22:59:27.134087 <6>[ 15.612766] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10762 22:59:27.140889 <6>[ 15.619289] usbcore: registered new interface driver btusb
10763 22:59:27.147364 <6>[ 15.619433] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10764 22:59:27.154342 <6>[ 15.619752] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10765 22:59:27.164264 <4>[ 15.620051] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10766 22:59:27.170594 <3>[ 15.620061] Bluetooth: hci0: Failed to load firmware file (-2)
10767 22:59:27.174050 <3>[ 15.620065] Bluetooth: hci0: Failed to set up firmware (-2)
10768 22:59:27.187191 <4>[ 15.620068] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10769 22:59:27.209892 <5>[ 15.752477] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10770 22:59:27.229003 <5>[ 15.771480] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10771 22:59:27.235517 <4>[ 15.778374] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10772 22:59:27.242071 <6>[ 15.787570] cfg80211: failed to load regulatory.db
10773 22:59:27.286928 <6>[ 15.829869] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10774 22:59:27.293676 <6>[ 15.837377] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10775 22:59:27.318346 <6>[ 15.864217] mt7921e 0000:01:00.0: ASIC revision: 79610010
10776 22:59:27.423238 <4>[ 15.962231] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10777 22:59:27.426164 Begin: Loading essential drivers ... done.
10778 22:59:27.433075 Begin: Running /scripts/init-premount ... done.
10779 22:59:27.439509 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10780 22:59:27.446512 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10781 22:59:27.452670 Device /sys/class/net/enx00e04c722dd6 found
10782 22:59:27.453152 done.
10783 22:59:27.520323 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10784 22:59:27.545250 <4>[ 16.084659] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10785 22:59:27.665080 <4>[ 16.204296] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10786 22:59:27.780748 <4>[ 16.320100] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10787 22:59:27.896750 <4>[ 16.436062] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10788 22:59:28.012680 <4>[ 16.552009] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10789 22:59:28.128513 <4>[ 16.668003] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10790 22:59:28.244590 <4>[ 16.784100] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10791 22:59:28.360858 <4>[ 16.900000] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10792 22:59:28.476757 <4>[ 17.015976] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10793 22:59:28.540567 <6>[ 17.086241] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
10794 22:59:28.583635 <3>[ 17.129888] mt7921e 0000:01:00.0: hardware init failed
10795 22:59:28.587348 IP-Config: no response after 2 secs - giving up
10796 22:59:28.628157 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10797 22:59:28.631370 IP-Config: enx00e04c722dd6 complete (dhcp from 192.168.201.1):
10798 22:59:28.638228 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10799 22:59:28.648023 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10800 22:59:28.654442 host : mt8192-asurada-spherion-r0-cbg-1
10801 22:59:28.660957 domain : lava-rack
10802 22:59:28.664035 rootserver: 192.168.201.1 rootpath:
10803 22:59:28.664459 filename :
10804 22:59:28.708878 done.
10805 22:59:28.715367 Begin: Running /scripts/nfs-bottom ... done.
10806 22:59:28.732638 Begin: Running /scripts/init-bottom ... done.
10807 22:59:29.799173 <6>[ 18.345714] NET: Registered PF_INET6 protocol family
10808 22:59:29.806652 <6>[ 18.352932] Segment Routing with IPv6
10809 22:59:29.809505 <6>[ 18.356931] In-situ OAM (IOAM) with IPv6
10810 22:59:29.912425 <30>[ 18.439065] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10811 22:59:29.915617 <30>[ 18.462838] systemd[1]: Detected architecture arm64.
10812 22:59:29.934536
10813 22:59:29.937602 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10814 22:59:29.937714
10815 22:59:29.954298 <30>[ 18.500801] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10816 22:59:30.430538 <30>[ 18.973582] systemd[1]: Queued start job for default target Graphical Interface.
10817 22:59:30.469640 <30>[ 19.015855] systemd[1]: Created slice system-getty.slice.
10818 22:59:30.475904 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10819 22:59:30.492991 <30>[ 19.039391] systemd[1]: Created slice system-modprobe.slice.
10820 22:59:30.499879 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10821 22:59:30.517869 <30>[ 19.063860] systemd[1]: Created slice system-serial\x2dgetty.slice.
10822 22:59:30.527870 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10823 22:59:30.541084 <30>[ 19.087199] systemd[1]: Created slice User and Session Slice.
10824 22:59:30.547870 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10825 22:59:30.568952 <30>[ 19.111272] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10826 22:59:30.578488 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10827 22:59:30.595678 <30>[ 19.138874] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10828 22:59:30.601994 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10829 22:59:30.622578 <30>[ 19.162810] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10830 22:59:30.629244 <30>[ 19.174851] systemd[1]: Reached target Local Encrypted Volumes.
10831 22:59:30.636216 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10832 22:59:30.652501 <30>[ 19.198969] systemd[1]: Reached target Paths.
10833 22:59:30.655664 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10834 22:59:30.672684 <30>[ 19.218752] systemd[1]: Reached target Remote File Systems.
10835 22:59:30.679025 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10836 22:59:30.696612 <30>[ 19.242972] systemd[1]: Reached target Slices.
10837 22:59:30.703053 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10838 22:59:30.716214 <30>[ 19.262711] systemd[1]: Reached target Swap.
10839 22:59:30.719651 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10840 22:59:30.740420 <30>[ 19.283201] systemd[1]: Listening on initctl Compatibility Named Pipe.
10841 22:59:30.746845 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10842 22:59:30.753393 <30>[ 19.298765] systemd[1]: Listening on Journal Audit Socket.
10843 22:59:30.759554 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10844 22:59:30.773478 <30>[ 19.319705] systemd[1]: Listening on Journal Socket (/dev/log).
10845 22:59:30.779961 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10846 22:59:30.797375 <30>[ 19.343515] systemd[1]: Listening on Journal Socket.
10847 22:59:30.803855 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10848 22:59:30.821016 <30>[ 19.364201] systemd[1]: Listening on Network Service Netlink Socket.
10849 22:59:30.827614 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10850 22:59:30.843214 <30>[ 19.389591] systemd[1]: Listening on udev Control Socket.
10851 22:59:30.849971 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10852 22:59:30.864850 <30>[ 19.410998] systemd[1]: Listening on udev Kernel Socket.
10853 22:59:30.871224 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10854 22:59:30.924470 <30>[ 19.470779] systemd[1]: Mounting Huge Pages File System...
10855 22:59:30.930606 Mounting [0;1;39mHuge Pages File System[0m...
10856 22:59:30.946604 <30>[ 19.493008] systemd[1]: Mounting POSIX Message Queue File System...
10857 22:59:30.953619 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10858 22:59:30.970898 <30>[ 19.517182] systemd[1]: Mounting Kernel Debug File System...
10859 22:59:30.977453 Mounting [0;1;39mKernel Debug File System[0m...
10860 22:59:30.996062 <30>[ 19.539129] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10861 22:59:31.035861 <30>[ 19.579272] systemd[1]: Starting Create list of static device nodes for the current kernel...
10862 22:59:31.042326 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10863 22:59:31.063002 <30>[ 19.609464] systemd[1]: Starting Load Kernel Module configfs...
10864 22:59:31.069498 Starting [0;1;39mLoad Kernel Module configfs[0m...
10865 22:59:31.086556 <30>[ 19.633125] systemd[1]: Starting Load Kernel Module drm...
10866 22:59:31.093007 Starting [0;1;39mLoad Kernel Module drm[0m...
10867 22:59:31.110339 <30>[ 19.657174] systemd[1]: Starting Load Kernel Module fuse...
10868 22:59:31.117182 Starting [0;1;39mLoad Kernel Module fuse[0m...
10869 22:59:31.145232 <6>[ 19.691783] fuse: init (API version 7.37)
10870 22:59:31.155301 <30>[ 19.693378] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10871 22:59:31.163205 <30>[ 19.709836] systemd[1]: Starting Journal Service...
10872 22:59:31.166641 Starting [0;1;39mJournal Service[0m...
10873 22:59:31.190476 <30>[ 19.737217] systemd[1]: Starting Load Kernel Modules...
10874 22:59:31.197295 Starting [0;1;39mLoad Kernel Modules[0m...
10875 22:59:31.218051 <30>[ 19.761296] systemd[1]: Starting Remount Root and Kernel File Systems...
10876 22:59:31.224516 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10877 22:59:31.239523 <30>[ 19.786519] systemd[1]: Starting Coldplug All udev Devices...
10878 22:59:31.246287 Starting [0;1;39mColdplug All udev Devices[0m...
10879 22:59:31.262949 <30>[ 19.809534] systemd[1]: Mounted Huge Pages File System.
10880 22:59:31.269704 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10881 22:59:31.284652 <30>[ 19.831157] systemd[1]: Mounted POSIX Message Queue File System.
10882 22:59:31.291058 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10883 22:59:31.308365 <30>[ 19.855089] systemd[1]: Mounted Kernel Debug File System.
10884 22:59:31.318596 <3>[ 19.860348] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10885 22:59:31.325183 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10886 22:59:31.344529 <30>[ 19.887741] systemd[1]: Finished Create list of static device nodes for the current kernel.
10887 22:59:31.354777 <3>[ 19.893679] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10888 22:59:31.361168 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10889 22:59:31.381055 <30>[ 19.927910] systemd[1]: modprobe@configfs.service: Succeeded.
10890 22:59:31.388149 <30>[ 19.934643] systemd[1]: Finished Load Kernel Module configfs.
10891 22:59:31.401409 [[0;32m OK [0m] Finished [0<3>[ 19.942723] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10892 22:59:31.404673 ;1;39mLoad Kernel Module configfs[0m.
10893 22:59:31.421609 <30>[ 19.967600] systemd[1]: modprobe@drm.service: Succeeded.
10894 22:59:31.428078 <30>[ 19.973815] systemd[1]: Finished Load Kernel Module drm.
10895 22:59:31.438194 <3>[ 19.976371] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10896 22:59:31.441148 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10897 22:59:31.457537 <30>[ 20.003716] systemd[1]: modprobe@fuse.service: Succeeded.
10898 22:59:31.467521 <3>[ 20.008047] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10899 22:59:31.470498 <30>[ 20.010010] systemd[1]: Finished Load Kernel Module fuse.
10900 22:59:31.477617 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10901 22:59:31.493117 <30>[ 20.039671] systemd[1]: Finished Load Kernel Modules.
10902 22:59:31.502680 <3>[ 20.039783] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10903 22:59:31.509333 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10904 22:59:31.526046 <30>[ 20.072303] systemd[1]: Finished Remount Root and Kernel File Systems.
10905 22:59:31.535627 <3>[ 20.075265] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10906 22:59:31.542817 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10907 22:59:31.567188 <3>[ 20.110436] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10908 22:59:31.604480 <30>[ 20.150946] systemd[1]: Mounting FUSE Control File System...
10909 22:59:31.611379 Mounting [0;1;39mFUSE Control File System[0m...
10910 22:59:31.633915 <30>[ 20.177345] systemd[1]: Mounting Kernel Configuration File System...
10911 22:59:31.637174 Mounting [0;1;39mKernel Configuration File System[0m...
10912 22:59:31.658552 <30>[ 20.201815] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10913 22:59:31.668832 <30>[ 20.210807] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10914 22:59:31.677031 <30>[ 20.223384] systemd[1]: Starting Load/Save Random Seed...
10915 22:59:31.683338 Starting [0;1;39mLoad/Save Random Seed[0m...
10916 22:59:31.703055 <30>[ 20.249941] systemd[1]: Starting Apply Kernel Variables...
10917 22:59:31.709721 Starting [0;1;39mApply Kernel Variables[0m...
10918 22:59:31.727632 <30>[ 20.274181] systemd[1]: Starting Create System Users...
10919 22:59:31.733889 Starting [0;1;39mCreate System Users[0m...
10920 22:59:31.754521 <4>[ 20.300735] power_supply_show_property: 2 callbacks suppressed
10921 22:59:31.764027 <3>[ 20.300753] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10922 22:59:31.767899 <30>[ 20.300957] systemd[1]: Started Journal Service.
10923 22:59:31.774402 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10924 22:59:31.791091 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10925 22:59:31.804917 <3>[ 20.347901] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10926 22:59:31.811789 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10927 22:59:31.826503 <3>[ 20.369746] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10928 22:59:31.836591 <3>[ 20.372122] power_supply sbs-5-000b: driver failed to report `capacity_level' property: -6
10929 22:59:31.850413 <4>[ 20.378577] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10930 22:59:31.860045 <3>[ 20.402720] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10931 22:59:31.873271 [[0;32m OK [0m] Finished [0;1;39mLoad/Save <3>[ 20.414457] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 22:59:31.873837 Random Seed[0m.
10933 22:59:31.891047 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10934 22:59:31.901073 <3>[ 20.444336] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 22:59:31.913141 See 'systemctl status systemd-udev-trigger.service' for details.
10936 22:59:31.930844 <3>[ 20.473690] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10937 22:59:31.937040 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10938 22:59:31.960244 [[0;32m OK [0m] Finished [0;1;39mCreate Sys<3>[ 20.503107] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10939 22:59:31.963112 tem Users[0m.
10940 22:59:31.989616 <3>[ 20.532503] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 22:59:32.001032 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10942 22:59:32.020859 <3>[ 20.563793] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10943 22:59:32.029812 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10944 22:59:32.092314 <46>[ 20.635376] systemd-journald[290]: Received client request to flush runtime journal.
10945 22:59:32.098720 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10946 22:59:32.113740 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10947 22:59:32.128244 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10948 22:59:32.188271 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10949 22:59:33.459437 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10950 22:59:33.517364 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10951 22:59:33.540341 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10952 22:59:33.566562 Starting [0;1;39mNetwork Service[0m...
10953 22:59:33.869922 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10954 22:59:33.888996 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10955 22:59:33.936110 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10956 22:59:34.129081 <6>[ 22.676068] remoteproc remoteproc0: powering up scp
10957 22:59:34.170109 <4>[ 22.714015] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10958 22:59:34.177005 <3>[ 22.723930] remoteproc remoteproc0: request_firmware failed: -2
10959 22:59:34.186962 <3>[ 22.730122] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10960 22:59:34.294113 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10961 22:59:34.312266 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10962 22:59:34.351851 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10963 22:59:34.380959 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10964 22:59:34.399399 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10965 22:59:34.444606 Starting [0;1;39mNetwork Name Resolution[0m...
10966 22:59:34.467067 Starting [0;1;39mNetwork Time Synchronization[0m...
10967 22:59:34.482453 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10968 22:59:34.503274 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10969 22:59:34.537634 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10970 22:59:34.552636 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10971 22:59:34.674646 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10972 22:59:34.692176 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10973 22:59:34.711102 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10974 22:59:34.723583 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10975 22:59:34.739859 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10976 22:59:34.880494 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10977 22:59:34.914337 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10978 22:59:34.942865 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10979 22:59:34.966053 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10980 22:59:34.979423 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10981 22:59:35.020747 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10982 22:59:35.035756 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10983 22:59:35.051487 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10984 22:59:35.084794 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10985 22:59:35.115035 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10986 22:59:35.149972 Starting [0;1;39mUser Login Management[0m...
10987 22:59:35.164660 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10988 22:59:35.180264 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10989 22:59:35.199051 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10990 22:59:35.236540 Starting [0;1;39mPermit User Sessions[0m...
10991 22:59:35.371697 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10992 22:59:35.420539 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10993 22:59:35.439416 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10994 22:59:35.456078 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10995 22:59:35.477020 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10996 22:59:35.497833 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10997 22:59:35.517613 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10998 22:59:35.532007 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10999 22:59:35.583902 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11000 22:59:35.622809 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11001 22:59:35.726473
11002 22:59:35.726639
11003 22:59:35.729381 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11004 22:59:35.729490
11005 22:59:35.732682 debian-bullseye-arm64 login: root (automatic login)
11006 22:59:35.732793
11007 22:59:35.732870
11008 22:59:36.001582 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 22:41:02 UTC 2023 aarch64
11009 22:59:36.001728
11010 22:59:36.008054 The programs included with the Debian GNU/Linux system are free software;
11011 22:59:36.014644 the exact distribution terms for each program are described in the
11012 22:59:36.018064 individual files in /usr/share/doc/*/copyright.
11013 22:59:36.018187
11014 22:59:36.024811 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11015 22:59:36.027715 permitted by applicable law.
11016 22:59:36.805026 Matched prompt #10: / #
11018 22:59:36.805331 Setting prompt string to ['/ #']
11019 22:59:36.805429 end: 2.2.5.1 login-action (duration 00:00:26) [common]
11021 22:59:36.805624 end: 2.2.5 auto-login-action (duration 00:00:26) [common]
11022 22:59:36.805712 start: 2.2.6 expect-shell-connection (timeout 00:03:36) [common]
11023 22:59:36.805783 Setting prompt string to ['/ #']
11024 22:59:36.805874 Forcing a shell prompt, looking for ['/ #']
11026 22:59:36.856104 / #
11027 22:59:36.856235 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11028 22:59:36.856318 Waiting using forced prompt support (timeout 00:02:30)
11029 22:59:36.860679
11030 22:59:36.860974 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11031 22:59:36.861067 start: 2.2.7 export-device-env (timeout 00:03:36) [common]
11033 22:59:36.961418 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10597663/extract-nfsrootfs-15xou4fs'
11034 22:59:36.966386 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10597663/extract-nfsrootfs-15xou4fs'
11036 22:59:37.066859 / # export NFS_SERVER_IP='192.168.201.1'
11037 22:59:37.071483 export NFS_SERVER_IP='192.168.201.1'
11038 22:59:37.071779 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11039 22:59:37.071883 end: 2.2 depthcharge-retry (duration 00:01:24) [common]
11040 22:59:37.072009 end: 2 depthcharge-action (duration 00:01:24) [common]
11041 22:59:37.072116 start: 3 lava-test-retry (timeout 00:07:56) [common]
11042 22:59:37.072210 start: 3.1 lava-test-shell (timeout 00:07:56) [common]
11043 22:59:37.072286 Using namespace: common
11045 22:59:37.172648 / # #
11046 22:59:37.172960 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11047 22:59:37.178245 #
11048 22:59:37.178728 Using /lava-10597663
11050 22:59:37.279462 / # export SHELL=/bin/bash
11051 22:59:37.285532 export SHELL=/bin/bash
11053 22:59:37.387036 / # . /lava-10597663/environment
11054 22:59:37.393137 . /lava-10597663/environment
11056 22:59:37.497706 / # /lava-10597663/bin/lava-test-runner /lava-10597663/0
11057 22:59:37.497854 Test shell timeout: 10s (minimum of the action and connection timeout)
11058 22:59:37.502725 /lava-10597663/bin/lava-test-runner /lava-10597663/0
11059 22:59:37.729758 + export TESTRUN_ID=0_timesync-off
11060 22:59:37.733137 + TESTRUN_ID=0_timesync-off
11061 22:59:37.736563 + cd /lava-10597663/0/tests/0_timesync-off
11062 22:59:37.739602 ++ cat uuid
11063 22:59:37.742923 + UUID=10597663_1.6.2.3.1
11064 22:59:37.743011 + set +x
11065 22:59:37.746420 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10597663_1.6.2.3.1>
11066 22:59:37.746704 Received signal: <STARTRUN> 0_timesync-off 10597663_1.6.2.3.1
11067 22:59:37.746803 Starting test lava.0_timesync-off (10597663_1.6.2.3.1)
11068 22:59:37.746905 Skipping test definition patterns.
11069 22:59:37.749349 + systemctl stop systemd-timesyncd
11070 22:59:37.775730 + set +x
11071 22:59:37.779143 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10597663_1.6.2.3.1>
11072 22:59:37.779398 Received signal: <ENDRUN> 0_timesync-off 10597663_1.6.2.3.1
11073 22:59:37.779485 Ending use of test pattern.
11074 22:59:37.779549 Ending test lava.0_timesync-off (10597663_1.6.2.3.1), duration 0.03
11076 22:59:37.823707 + export TESTRUN_ID=1_kselftest-arm64
11077 22:59:37.823794 + TESTRUN_ID=1_kselftest-arm64
11078 22:59:37.830002 + cd /lava-10597663/0/tests/1_kselftest-arm64
11079 22:59:37.830087 ++ cat uuid
11080 22:59:37.833415 + UUID=10597663_1.6.2.3.5
11081 22:59:37.833500 + set +x
11082 22:59:37.837163 Received signal: <STARTRUN> 1_kselftest-arm64 10597663_1.6.2.3.5
11083 22:59:37.837271 Starting test lava.1_kselftest-arm64 (10597663_1.6.2.3.5)
11084 22:59:37.837371 Skipping test definition patterns.
11085 22:59:37.839896 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 10597663_1.6.2.3.5>
11086 22:59:37.839980 + cd ./automated/linux/kselftest/
11087 22:59:37.866592 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11088 22:59:37.876598 INFO: install_deps skipped
11089 22:59:37.977580 --2023-06-05 22:59:35-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11090 22:59:37.988276 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
11091 22:59:38.132245 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
11092 22:59:38.274769 HTTP request sent, awaiting response... 200 OK
11093 22:59:38.278229 Length: 2703120 (2.6M) [application/octet-stream]
11094 22:59:38.281259 Saving to: 'kselftest.tar.xz'
11095 22:59:38.281851
11096 22:59:38.282350
11097 22:59:38.560316 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11098 22:59:38.845894 kselftest.tar.xz 1%[ ] 46.39K 167KB/s
11099 22:59:39.325759 kselftest.tar.xz 8%[> ] 217.50K 390KB/s
11100 22:59:39.621834 kselftest.tar.xz 30%[=====> ] 811.40K 789KB/s
11101 22:59:39.628403 kselftest.tar.xz 91%[=================> ] 2.35M 1.78MB/s
11102 22:59:39.634969 kselftest.tar.xz 100%[===================>] 2.58M 1.95MB/s in 1.3s
11103 22:59:39.635393
11104 22:59:39.864422 2023-06-05 22:59:37 (1.95 MB/s) - 'kselftest.tar.xz' saved [2703120/2703120]
11105 22:59:39.864577
11106 22:59:44.340416 skiplist:
11107 22:59:44.343668 ========================================
11108 22:59:44.347091 ========================================
11109 22:59:44.380024 arm64:tags_test
11110 22:59:44.383500 arm64:run_tags_test.sh
11111 22:59:44.383581 arm64:fake_sigreturn_bad_magic
11112 22:59:44.387020 arm64:fake_sigreturn_bad_size
11113 22:59:44.390409 arm64:fake_sigreturn_bad_size_for_magic0
11114 22:59:44.393542 arm64:fake_sigreturn_duplicated_fpsimd
11115 22:59:44.396572 arm64:fake_sigreturn_misaligned_sp
11116 22:59:44.400023 arm64:fake_sigreturn_missing_fpsimd
11117 22:59:44.403576 arm64:fake_sigreturn_sme_change_vl
11118 22:59:44.406443 arm64:fake_sigreturn_sve_change_vl
11119 22:59:44.409751 arm64:mangle_pstate_invalid_compat_toggle
11120 22:59:44.413315 arm64:mangle_pstate_invalid_daif_bits
11121 22:59:44.416345 arm64:mangle_pstate_invalid_mode_el1h
11122 22:59:44.419678 arm64:mangle_pstate_invalid_mode_el1t
11123 22:59:44.422892 arm64:mangle_pstate_invalid_mode_el2h
11124 22:59:44.426453 arm64:mangle_pstate_invalid_mode_el2t
11125 22:59:44.429898 arm64:mangle_pstate_invalid_mode_el3h
11126 22:59:44.436185 arm64:mangle_pstate_invalid_mode_el3t
11127 22:59:44.436269 arm64:sme_trap_no_sm
11128 22:59:44.439781 arm64:sme_trap_non_streaming
11129 22:59:44.439865 arm64:sme_trap_za
11130 22:59:44.442709 arm64:sme_vl
11131 22:59:44.442792 arm64:ssve_regs
11132 22:59:44.446124 arm64:sve_regs
11133 22:59:44.446208 arm64:sve_vl
11134 22:59:44.446291 arm64:za_no_regs
11135 22:59:44.449518 arm64:za_regs
11136 22:59:44.449602 arm64:pac
11137 22:59:44.453008 arm64:fp-stress
11138 22:59:44.453097 arm64:sve-ptrace
11139 22:59:44.456084 arm64:sve-probe-vls
11140 22:59:44.456164 arm64:vec-syscfg
11141 22:59:44.456247 arm64:za-fork
11142 22:59:44.459559 arm64:za-ptrace
11143 22:59:44.463163 arm64:check_buffer_fill
11144 22:59:44.463268 arm64:check_child_memory
11145 22:59:44.465924 arm64:check_gcr_el1_cswitch
11146 22:59:44.469708 arm64:check_ksm_options
11147 22:59:44.470137 arm64:check_mmap_options
11148 22:59:44.472653 arm64:check_prctl
11149 22:59:44.476055 arm64:check_tags_inclusion
11150 22:59:44.476483 arm64:check_user_mem
11151 22:59:44.479651 arm64:btitest
11152 22:59:44.480078 arm64:nobtitest
11153 22:59:44.480503 arm64:hwcap
11154 22:59:44.483080 arm64:ptrace
11155 22:59:44.483508 arm64:syscall-abi
11156 22:59:44.486117 arm64:tpidr2
11157 22:59:44.489519 ============== Tests to run ===============
11158 22:59:44.489949 arm64:tags_test
11159 22:59:44.492413 arm64:run_tags_test.sh
11160 22:59:44.495871 arm64:fake_sigreturn_bad_magic
11161 22:59:44.499288 arm64:fake_sigreturn_bad_size
11162 22:59:44.502458 arm64:fake_sigreturn_bad_size_for_magic0
11163 22:59:44.505876 arm64:fake_sigreturn_duplicated_fpsimd
11164 22:59:44.509410 arm64:fake_sigreturn_misaligned_sp
11165 22:59:44.512423 arm64:fake_sigreturn_missing_fpsimd
11166 22:59:44.515632 arm64:fake_sigreturn_sme_change_vl
11167 22:59:44.516062 arm64:fake_sigreturn_sve_change_vl
11168 22:59:44.522423 arm64:mangle_pstate_invalid_compat_toggle
11169 22:59:44.526168 arm64:mangle_pstate_invalid_daif_bits
11170 22:59:44.529043 arm64:mangle_pstate_invalid_mode_el1h
11171 22:59:44.532288 arm64:mangle_pstate_invalid_mode_el1t
11172 22:59:44.535971 arm64:mangle_pstate_invalid_mode_el2h
11173 22:59:44.538906 arm64:mangle_pstate_invalid_mode_el2t
11174 22:59:44.542170 arm64:mangle_pstate_invalid_mode_el3h
11175 22:59:44.545592 arm64:mangle_pstate_invalid_mode_el3t
11176 22:59:44.546062 arm64:sme_trap_no_sm
11177 22:59:44.549067 arm64:sme_trap_non_streaming
11178 22:59:44.552388 arm64:sme_trap_za
11179 22:59:44.552897 arm64:sme_vl
11180 22:59:44.553293 arm64:ssve_regs
11181 22:59:44.555264 arm64:sve_regs
11182 22:59:44.555836 arm64:sve_vl
11183 22:59:44.558746 arm64:za_no_regs
11184 22:59:44.559345 arm64:za_regs
11185 22:59:44.559729 arm64:pac
11186 22:59:44.562201 arm64:fp-stress
11187 22:59:44.562668 arm64:sve-ptrace
11188 22:59:44.565179 arm64:sve-probe-vls
11189 22:59:44.565649 arm64:vec-syscfg
11190 22:59:44.568490 arm64:za-fork
11191 22:59:44.569008 arm64:za-ptrace
11192 22:59:44.571889 arm64:check_buffer_fill
11193 22:59:44.575130 arm64:check_child_memory
11194 22:59:44.575214 arm64:check_gcr_el1_cswitch
11195 22:59:44.578476 arm64:check_ksm_options
11196 22:59:44.581904 arm64:check_mmap_options
11197 22:59:44.581993 arm64:check_prctl
11198 22:59:44.584807 arm64:check_tags_inclusion
11199 22:59:44.584897 arm64:check_user_mem
11200 22:59:44.588121 arm64:btitest
11201 22:59:44.588217 arm64:nobtitest
11202 22:59:44.591713 arm64:hwcap
11203 22:59:44.591816 arm64:ptrace
11204 22:59:44.594592 arm64:syscall-abi
11205 22:59:44.594695 arm64:tpidr2
11206 22:59:44.598447 ===========End Tests to run ===============
11207 22:59:44.780449 <12>[ 33.328191] kselftest: Running tests in arm64
11208 22:59:44.790376 TAP version 13
11209 22:59:44.802599 1..48
11210 22:59:44.818314 # selftests: arm64: tags_test
11211 22:59:45.180106 ok 1 selftests: arm64: tags_test
11212 22:59:45.193340 # selftests: arm64: run_tags_test.sh
11213 22:59:45.240512 # --------------------
11214 22:59:45.243860 # running tags test
11215 22:59:45.243958 # --------------------
11216 22:59:45.246961 # [PASS]
11217 22:59:45.250409 ok 2 selftests: arm64: run_tags_test.sh
11218 22:59:45.259192 # selftests: arm64: fake_sigreturn_bad_magic
11219 22:59:45.307971 # Registered handlers for all signals.
11220 22:59:45.308636 # Detected MINSTKSIGSZ:4720
11221 22:59:45.311548 # Testcase initialized.
11222 22:59:45.315086 # uc context validated.
11223 22:59:45.318079 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11224 22:59:45.321074 # Handled SIG_COPYCTX
11225 22:59:45.321687 # Available space:3568
11226 22:59:45.327976 # Using badly built context - ERR: BAD MAGIC !
11227 22:59:45.334724 # SIG_OK -- SP:0xFFFFFACB0F60 si_addr@:0xfffffacb0f60 si_code:2 token@:0xfffffacafd00 offset:-4704
11228 22:59:45.337845 # ==>> completed. PASS(1)
11229 22:59:45.344154 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11230 22:59:45.350692 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFACAFD00
11231 22:59:45.357290 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11232 22:59:45.360561 # selftests: arm64: fake_sigreturn_bad_size
11233 22:59:45.372942 # Registered handlers for all signals.
11234 22:59:45.373026 # Detected MINSTKSIGSZ:4720
11235 22:59:45.376055 # Testcase initialized.
11236 22:59:45.379723 # uc context validated.
11237 22:59:45.382693 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11238 22:59:45.386261 # Handled SIG_COPYCTX
11239 22:59:45.386346 # Available space:3568
11240 22:59:45.389282 # uc context validated.
11241 22:59:45.395890 # Using badly built context - ERR: Bad size for esr_context
11242 22:59:45.402639 # SIG_OK -- SP:0xFFFFF38FE6F0 si_addr@:0xfffff38fe6f0 si_code:2 token@:0xfffff38fd490 offset:-4704
11243 22:59:45.405928 # ==>> completed. PASS(1)
11244 22:59:45.412415 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11245 22:59:45.419238 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF38FD490
11246 22:59:45.422314 ok 4 selftests: arm64: fake_sigreturn_bad_size
11247 22:59:45.429403 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11248 22:59:45.432372 # Registered handlers for all signals.
11249 22:59:45.435814 # Detected MINSTKSIGSZ:4720
11250 22:59:45.439147 # Testcase initialized.
11251 22:59:45.439269 # uc context validated.
11252 22:59:45.445743 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11253 22:59:45.449144 # Handled SIG_COPYCTX
11254 22:59:45.449263 # Available space:3568
11255 22:59:45.455708 # Using badly built context - ERR: Bad size for terminator
11256 22:59:45.465949 # SIG_OK -- SP:0xFFFFF2C1F350 si_addr@:0xfffff2c1f350 si_code:2 token@:0xfffff2c1e0f0 offset:-4704
11257 22:59:45.466113 # ==>> completed. PASS(1)
11258 22:59:45.475648 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11259 22:59:45.482176 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF2C1E0F0
11260 22:59:45.485569 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11261 22:59:45.492291 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11262 22:59:45.498934 # Registered handlers for all signals.
11263 22:59:45.499569 # Detected MINSTKSIGSZ:4720
11264 22:59:45.502218 # Testcase initialized.
11265 22:59:45.505513 # uc context validated.
11266 22:59:45.508676 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11267 22:59:45.511771 # Handled SIG_COPYCTX
11268 22:59:45.512400 # Available space:3568
11269 22:59:45.518603 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11270 22:59:45.528112 # SIG_OK -- SP:0xFFFFDB3B5210 si_addr@:0xffffdb3b5210 si_code:2 token@:0xffffdb3b3fb0 offset:-4704
11271 22:59:45.528211 # ==>> completed. PASS(1)
11272 22:59:45.538073 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11273 22:59:45.544425 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDB3B3FB0
11274 22:59:45.547992 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11275 22:59:45.551135 # selftests: arm64: fake_sigreturn_misaligned_sp
11276 22:59:45.563649 # Registered handlers for all signals.
11277 22:59:45.563772 # Detected MINSTKSIGSZ:4720
11278 22:59:45.566945 # Testcase initialized.
11279 22:59:45.570460 # uc context validated.
11280 22:59:45.573770 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11281 22:59:45.576789 # Handled SIG_COPYCTX
11282 22:59:45.583575 # SIG_OK -- SP:0xFFFFCC480B03 si_addr@:0xffffcc480b03 si_code:2 token@:0xffffcc480b03 offset:0
11283 22:59:45.586759 # ==>> completed. PASS(1)
11284 22:59:45.593839 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11285 22:59:45.600515 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCC480B03
11286 22:59:45.607004 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11287 22:59:45.610006 # selftests: arm64: fake_sigreturn_missing_fpsimd
11288 22:59:45.628640 # Registered handlers for all signals.
11289 22:59:45.629145 # Detected MINSTKSIGSZ:4720
11290 22:59:45.632009 # Testcase initialized.
11291 22:59:45.635384 # uc context validated.
11292 22:59:45.638549 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11293 22:59:45.641673 # Handled SIG_COPYCTX
11294 22:59:45.645195 # Mangling template header. Spare space:4096
11295 22:59:45.648650 # Using badly built context - ERR: Missing FPSIMD
11296 22:59:45.658048 # SIG_OK -- SP:0xFFFFCD464A30 si_addr@:0xffffcd464a30 si_code:2 token@:0xffffcd4637d0 offset:-4704
11297 22:59:45.661728 # ==>> completed. PASS(1)
11298 22:59:45.668253 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11299 22:59:45.675066 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCD4637D0
11300 22:59:45.678162 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11301 22:59:45.684722 # selftests: arm64: fake_sigreturn_sme_change_vl
11302 22:59:45.696472 # Registered handlers for all signals.
11303 22:59:45.697051 # Detected MINSTKSIGSZ:4720
11304 22:59:45.699615 # ==>> completed. SKIP.
11305 22:59:45.705940 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11306 22:59:45.709377 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11307 22:59:45.715919 # selftests: arm64: fake_sigreturn_sve_change_vl
11308 22:59:45.765224 # Registered handlers for all signals.
11309 22:59:45.765777 # Detected MINSTKSIGSZ:4720
11310 22:59:45.768656 # ==>> completed. SKIP.
11311 22:59:45.775323 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11312 22:59:45.778366 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11313 22:59:45.785002 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11314 22:59:45.833929 # Registered handlers for all signals.
11315 22:59:45.834481 # Detected MINSTKSIGSZ:4720
11316 22:59:45.837300 # Testcase initialized.
11317 22:59:45.840592 # uc context validated.
11318 22:59:45.841096 # Handled SIG_TRIG
11319 22:59:45.850702 # SIG_OK -- SP:0xFFFFFB4EBC50 si_addr@:0xfffffb4ebc50 si_code:2 token@:(nil) offset:-281474897984592
11320 22:59:45.853596 # ==>> completed. PASS(1)
11321 22:59:45.860245 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11322 22:59:45.867118 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11323 22:59:45.870675 # selftests: arm64: mangle_pstate_invalid_daif_bits
11324 22:59:45.899814 # Registered handlers for all signals.
11325 22:59:45.900378 # Detected MINSTKSIGSZ:4720
11326 22:59:45.902900 # Testcase initialized.
11327 22:59:45.906438 # uc context validated.
11328 22:59:45.907046 # Handled SIG_TRIG
11329 22:59:45.916210 # SIG_OK -- SP:0xFFFFE41ACD20 si_addr@:0xffffe41acd20 si_code:2 token@:(nil) offset:-281474508705056
11330 22:59:45.919440 # ==>> completed. PASS(1)
11331 22:59:45.926021 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11332 22:59:45.929260 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11333 22:59:45.935737 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11334 22:59:45.969965 # Registered handlers for all signals.
11335 22:59:45.970526 # Detected MINSTKSIGSZ:4720
11336 22:59:45.972894 # Testcase initialized.
11337 22:59:45.976306 # uc context validated.
11338 22:59:45.976830 # Handled SIG_TRIG
11339 22:59:45.986013 # SIG_OK -- SP:0xFFFFEA862200 si_addr@:0xffffea862200 si_code:2 token@:(nil) offset:-281474616402432
11340 22:59:45.989271 # ==>> completed. PASS(1)
11341 22:59:45.995719 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11342 22:59:45.999232 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11343 22:59:46.005532 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11344 22:59:46.038127 # Registered handlers for all signals.
11345 22:59:46.038687 # Detected MINSTKSIGSZ:4720
11346 22:59:46.041354 # Testcase initialized.
11347 22:59:46.045082 # uc context validated.
11348 22:59:46.045551 # Handled SIG_TRIG
11349 22:59:46.054957 # SIG_OK -- SP:0xFFFFECEC1C70 si_addr@:0xffffecec1c70 si_code:2 token@:(nil) offset:-281474656640112
11350 22:59:46.058322 # ==>> completed. PASS(1)
11351 22:59:46.064721 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11352 22:59:46.067799 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11353 22:59:46.074992 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11354 22:59:46.102824 # Registered handlers for all signals.
11355 22:59:46.103377 # Detected MINSTKSIGSZ:4720
11356 22:59:46.106360 # Testcase initialized.
11357 22:59:46.109754 # uc context validated.
11358 22:59:46.110241 # Handled SIG_TRIG
11359 22:59:46.119425 # SIG_OK -- SP:0xFFFFE16135A0 si_addr@:0xffffe16135a0 si_code:2 token@:(nil) offset:-281474462987680
11360 22:59:46.123081 # ==>> completed. PASS(1)
11361 22:59:46.129436 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11362 22:59:46.132824 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11363 22:59:46.139496 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11364 22:59:46.170164 # Registered handlers for all signals.
11365 22:59:46.170749 # Detected MINSTKSIGSZ:4720
11366 22:59:46.173397 # Testcase initialized.
11367 22:59:46.176986 # uc context validated.
11368 22:59:46.177463 # Handled SIG_TRIG
11369 22:59:46.186979 # SIG_OK -- SP:0xFFFFEAC15850 si_addr@:0xffffeac15850 si_code:2 token@:(nil) offset:-281474620282960
11370 22:59:46.190230 # ==>> completed. PASS(1)
11371 22:59:46.196833 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11372 22:59:46.199968 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11373 22:59:46.206406 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11374 22:59:46.237930 # Registered handlers for all signals.
11375 22:59:46.238475 # Detected MINSTKSIGSZ:4720
11376 22:59:46.241386 # Testcase initialized.
11377 22:59:46.244426 # uc context validated.
11378 22:59:46.245044 # Handled SIG_TRIG
11379 22:59:46.254316 # SIG_OK -- SP:0xFFFFD86104D0 si_addr@:0xffffd86104d0 si_code:2 token@:(nil) offset:-281474311980240
11380 22:59:46.257598 # ==>> completed. PASS(1)
11381 22:59:46.264348 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11382 22:59:46.267520 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11383 22:59:46.273751 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11384 22:59:46.304428 # Registered handlers for all signals.
11385 22:59:46.304999 # Detected MINSTKSIGSZ:4720
11386 22:59:46.307746 # Testcase initialized.
11387 22:59:46.311163 # uc context validated.
11388 22:59:46.311582 # Handled SIG_TRIG
11389 22:59:46.320857 # SIG_OK -- SP:0xFFFFF29D5180 si_addr@:0xfffff29d5180 si_code:2 token@:(nil) offset:-281474752139648
11390 22:59:46.324245 # ==>> completed. PASS(1)
11391 22:59:46.331106 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11392 22:59:46.334473 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11393 22:59:46.337409 # selftests: arm64: sme_trap_no_sm
11394 22:59:46.369604 # Registered handlers for all signals.
11395 22:59:46.370135 # Detected MINSTKSIGSZ:4720
11396 22:59:46.372868 # ==>> completed. SKIP.
11397 22:59:46.382576 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11398 22:59:46.386346 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11399 22:59:46.389286 # selftests: arm64: sme_trap_non_streaming
11400 22:59:46.435269 # Registered handlers for all signals.
11401 22:59:46.435794 # Detected MINSTKSIGSZ:4720
11402 22:59:46.438253 # ==>> completed. SKIP.
11403 22:59:46.448441 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11404 22:59:46.454883 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11405 22:59:46.457964 # selftests: arm64: sme_trap_za
11406 22:59:46.501523 # Registered handlers for all signals.
11407 22:59:46.502054 # Detected MINSTKSIGSZ:4720
11408 22:59:46.504833 # Testcase initialized.
11409 22:59:46.514679 # SIG_OK -- SP:0xFFFFEDD29820 si_addr@:0xaaaab2072510 si_code:1 token@:(nil) offset:-187650107974928
11410 22:59:46.515147 # ==>> completed. PASS(1)
11411 22:59:46.524626 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11412 22:59:46.528035 ok 21 selftests: arm64: sme_trap_za
11413 22:59:46.528467 # selftests: arm64: sme_vl
11414 22:59:46.568018 # Registered handlers for all signals.
11415 22:59:46.568535 # Detected MINSTKSIGSZ:4720
11416 22:59:46.571400 # ==>> completed. SKIP.
11417 22:59:46.578027 # # SME VL :: Check that we get the right SME VL reported
11418 22:59:46.581102 ok 22 selftests: arm64: sme_vl # SKIP
11419 22:59:46.584479 # selftests: arm64: ssve_regs
11420 22:59:46.635689 # Registered handlers for all signals.
11421 22:59:46.636213 # Detected MINSTKSIGSZ:4720
11422 22:59:46.639154 # ==>> completed. SKIP.
11423 22:59:46.645987 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11424 22:59:46.649291 ok 23 selftests: arm64: ssve_regs # SKIP
11425 22:59:46.652217 # selftests: arm64: sve_regs
11426 22:59:46.703258 # Registered handlers for all signals.
11427 22:59:46.703846 # Detected MINSTKSIGSZ:4720
11428 22:59:46.706662 # ==>> completed. SKIP.
11429 22:59:46.712874 # # SVE registers :: Check that we get the right SVE registers reported
11430 22:59:46.716534 ok 24 selftests: arm64: sve_regs # SKIP
11431 22:59:46.719229 # selftests: arm64: sve_vl
11432 22:59:46.767468 # Registered handlers for all signals.
11433 22:59:46.767986 # Detected MINSTKSIGSZ:4720
11434 22:59:46.771011 # ==>> completed. SKIP.
11435 22:59:46.777348 # # SVE VL :: Check that we get the right SVE VL reported
11436 22:59:46.780845 ok 25 selftests: arm64: sve_vl # SKIP
11437 22:59:46.783699 # selftests: arm64: za_no_regs
11438 22:59:46.832469 # Registered handlers for all signals.
11439 22:59:46.833098 # Detected MINSTKSIGSZ:4720
11440 22:59:46.835852 # ==>> completed. SKIP.
11441 22:59:46.842582 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11442 22:59:46.845545 ok 26 selftests: arm64: za_no_regs # SKIP
11443 22:59:46.848933 # selftests: arm64: za_regs
11444 22:59:46.898089 # Registered handlers for all signals.
11445 22:59:46.898621 # Detected MINSTKSIGSZ:4720
11446 22:59:46.901322 # ==>> completed. SKIP.
11447 22:59:46.908438 # # ZA register :: Check that we get the right ZA registers reported
11448 22:59:46.911131 ok 27 selftests: arm64: za_regs # SKIP
11449 22:59:46.914555 # selftests: arm64: pac
11450 22:59:46.961452 # TAP version 13
11451 22:59:46.962016 # 1..7
11452 22:59:46.964671 # # Starting 7 tests from 1 test cases.
11453 22:59:46.968028 # # RUN global.corrupt_pac ...
11454 22:59:46.971072 # # SKIP PAUTH not enabled
11455 22:59:46.974446 # # OK global.corrupt_pac
11456 22:59:46.977820 # ok 1 # SKIP PAUTH not enabled
11457 22:59:46.984471 # # RUN global.pac_instructions_not_nop ...
11458 22:59:46.987927 # # SKIP PAUTH not enabled
11459 22:59:46.990831 # # OK global.pac_instructions_not_nop
11460 22:59:46.994046 # ok 2 # SKIP PAUTH not enabled
11461 22:59:47.000989 # # RUN global.pac_instructions_not_nop_generic ...
11462 22:59:47.004371 # # SKIP Generic PAUTH not enabled
11463 22:59:47.007489 # # OK global.pac_instructions_not_nop_generic
11464 22:59:47.014088 # ok 3 # SKIP Generic PAUTH not enabled
11465 22:59:47.017542 # # RUN global.single_thread_different_keys ...
11466 22:59:47.020918 # # SKIP PAUTH not enabled
11467 22:59:47.027370 # # OK global.single_thread_different_keys
11468 22:59:47.027792 # ok 4 # SKIP PAUTH not enabled
11469 22:59:47.033862 # # RUN global.exec_changed_keys ...
11470 22:59:47.037371 # # SKIP PAUTH not enabled
11471 22:59:47.040328 # # OK global.exec_changed_keys
11472 22:59:47.043902 # ok 5 # SKIP PAUTH not enabled
11473 22:59:47.047179 # # RUN global.context_switch_keep_keys ...
11474 22:59:47.050550 # # SKIP PAUTH not enabled
11475 22:59:47.056820 # # OK global.context_switch_keep_keys
11476 22:59:47.057253 # ok 6 # SKIP PAUTH not enabled
11477 22:59:47.063499 # # RUN global.context_switch_keep_keys_generic ...
11478 22:59:47.066868 # # SKIP Generic PAUTH not enabled
11479 22:59:47.074103 # # OK global.context_switch_keep_keys_generic
11480 22:59:47.076725 # ok 7 # SKIP Generic PAUTH not enabled
11481 22:59:47.080062 # # PASSED: 7 / 7 tests passed.
11482 22:59:47.083694 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11483 22:59:47.086829 ok 28 selftests: arm64: pac
11484 22:59:47.090252 # selftests: arm64: fp-stress
11485 22:59:57.075342 # TAP version 13
11486 22:59:57.075869 # 1..16
11487 22:59:57.078343 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11488 22:59:57.081609 # # Will run for 10s
11489 22:59:57.082038 # # Started FPSIMD-0-0
11490 22:59:57.085081 # # Started FPSIMD-0-1
11491 22:59:57.088409 # # Started FPSIMD-1-0
11492 22:59:57.088871 # # Started FPSIMD-1-1
11493 22:59:57.091524 # # Started FPSIMD-2-0
11494 22:59:57.091946 # # Started FPSIMD-2-1
11495 22:59:57.095063 # # Started FPSIMD-3-0
11496 22:59:57.098355 # # Started FPSIMD-3-1
11497 22:59:57.098984 # # Started FPSIMD-4-0
11498 22:59:57.101248 # # Started FPSIMD-4-1
11499 22:59:57.104682 # # Started FPSIMD-5-0
11500 22:59:57.105150 # # Started FPSIMD-5-1
11501 22:59:57.108004 # # Started FPSIMD-6-0
11502 22:59:57.108651 # # Started FPSIMD-6-1
11503 22:59:57.111307 # # Started FPSIMD-7-0
11504 22:59:57.114405 # # Started FPSIMD-7-1
11505 22:59:57.118293 # # FPSIMD-0-0: Vector length: 128 bits
11506 22:59:57.121461 # # FPSIMD-0-0: PID: 1120
11507 22:59:57.124870 # # FPSIMD-0-1: Vector length: 128 bits
11508 22:59:57.125287 # # FPSIMD-0-1: PID: 1121
11509 22:59:57.128001 # # FPSIMD-3-0: Vector length: 128 bits
11510 22:59:57.131028 # # FPSIMD-3-0: PID: 1126
11511 22:59:57.134813 # # FPSIMD-1-0: Vector length: 128 bits
11512 22:59:57.137706 # # FPSIMD-1-0: PID: 1122
11513 22:59:57.141074 # # FPSIMD-2-0: Vector length: 128 bits
11514 22:59:57.144220 # # FPSIMD-2-0: PID: 1124
11515 22:59:57.147582 # # FPSIMD-7-1: Vector length: 128 bits
11516 22:59:57.148004 # # FPSIMD-7-1: PID: 1135
11517 22:59:57.154111 # # FPSIMD-4-1: Vector length: 128 bits
11518 22:59:57.154539 # # FPSIMD-4-1: PID: 1129
11519 22:59:57.157700 # # FPSIMD-4-0: Vector length: 128 bits
11520 22:59:57.161129 # # FPSIMD-4-0: PID: 1128
11521 22:59:57.163910 # # FPSIMD-3-1: Vector length: 128 bits
11522 22:59:57.167407 # # FPSIMD-3-1: PID: 1127
11523 22:59:57.170301 # # FPSIMD-2-1: Vector length: 128 bits
11524 22:59:57.173576 # # FPSIMD-2-1: PID: 1125
11525 22:59:57.177035 # # FPSIMD-1-1: Vector length: 128 bits
11526 22:59:57.177146 # # FPSIMD-1-1: PID: 1123
11527 22:59:57.183593 # # FPSIMD-5-0: Vector length: 128 bits
11528 22:59:57.183706 # # FPSIMD-5-0: PID: 1130
11529 22:59:57.186847 # # FPSIMD-6-1: Vector length: 128 bits
11530 22:59:57.189891 # # FPSIMD-6-1: PID: 1133
11531 22:59:57.193390 # # FPSIMD-7-0: Vector length: 128 bits
11532 22:59:57.196741 # # FPSIMD-7-0: PID: 1134
11533 22:59:57.200005 # # FPSIMD-5-1: Vector length: 128 bits
11534 22:59:57.203305 # # FPSIMD-5-1: PID: 1131
11535 22:59:57.206856 # # FPSIMD-6-0: Vector length: 128 bits
11536 22:59:57.206940 # # FPSIMD-6-0: PID: 1132
11537 22:59:57.209934 # # Finishing up...
11538 22:59:57.216833 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=548384, signals=10
11539 22:59:57.223714 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=708084, signals=10
11540 22:59:57.229990 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=432130, signals=10
11541 22:59:57.239977 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=1708631, signals=10
11542 22:59:57.246737 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=1904276, signals=10
11543 22:59:57.253321 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=775690, signals=10
11544 22:59:57.259783 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=952874, signals=9
11545 22:59:57.262984 # ok 1 FPSIMD-0-0
11546 22:59:57.263411 # ok 2 FPSIMD-0-1
11547 22:59:57.266390 # ok 3 FPSIMD-1-0
11548 22:59:57.266816 # ok 4 FPSIMD-1-1
11549 22:59:57.269858 # ok 5 FPSIMD-2-0
11550 22:59:57.270315 # ok 6 FPSIMD-2-1
11551 22:59:57.273237 # ok 7 FPSIMD-3-0
11552 22:59:57.273711 # ok 8 FPSIMD-3-1
11553 22:59:57.276103 # ok 9 FPSIMD-4-0
11554 22:59:57.276527 # ok 10 FPSIMD-4-1
11555 22:59:57.279861 # ok 11 FPSIMD-5-0
11556 22:59:57.280451 # ok 12 FPSIMD-5-1
11557 22:59:57.282791 # ok 13 FPSIMD-6-0
11558 22:59:57.283291 # ok 14 FPSIMD-6-1
11559 22:59:57.286300 # ok 15 FPSIMD-7-0
11560 22:59:57.286887 # ok 16 FPSIMD-7-1
11561 22:59:57.292868 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=715720, signals=9
11562 22:59:57.299221 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=405577, signals=10
11563 22:59:57.309628 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=1559859, signals=10
11564 22:59:57.315842 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=497020, signals=9
11565 22:59:57.322328 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=445762, signals=9
11566 22:59:57.329254 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=697746, signals=9
11567 22:59:57.336185 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=656329, signals=10
11568 22:59:57.342619 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=448591, signals=10
11569 22:59:57.352241 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=374406, signals=10
11570 22:59:57.355648 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11571 22:59:57.358716 ok 29 selftests: arm64: fp-stress
11572 22:59:57.362044 # selftests: arm64: sve-ptrace
11573 22:59:57.362473 # TAP version 13
11574 22:59:57.365320 # 1..4104
11575 22:59:57.365745 # ok 2 # SKIP SVE not available
11576 22:59:57.372065 # # Planned tests != run tests (4104 != 1)
11577 22:59:57.375528 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11578 22:59:57.378787 ok 30 selftests: arm64: sve-ptrace # SKIP
11579 22:59:57.382101 # selftests: arm64: sve-probe-vls
11580 22:59:57.385622 # TAP version 13
11581 22:59:57.386049 # 1..2
11582 22:59:57.388959 # ok 2 # SKIP SVE not available
11583 22:59:57.392319 # # Planned tests != run tests (2 != 1)
11584 22:59:57.395646 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11585 22:59:57.402087 ok 31 selftests: arm64: sve-probe-vls # SKIP
11586 22:59:57.402516 # selftests: arm64: vec-syscfg
11587 22:59:57.405594 # TAP version 13
11588 22:59:57.406022 # 1..20
11589 22:59:57.408464 # ok 1 # SKIP SVE not supported
11590 22:59:57.411747 # ok 2 # SKIP SVE not supported
11591 22:59:57.415174 # ok 3 # SKIP SVE not supported
11592 22:59:57.418463 # ok 4 # SKIP SVE not supported
11593 22:59:57.418971 # ok 5 # SKIP SVE not supported
11594 22:59:57.421810 # ok 6 # SKIP SVE not supported
11595 22:59:57.425185 # ok 7 # SKIP SVE not supported
11596 22:59:57.428354 # ok 8 # SKIP SVE not supported
11597 22:59:57.431807 # ok 9 # SKIP SVE not supported
11598 22:59:57.435303 # ok 10 # SKIP SVE not supported
11599 22:59:57.438586 # ok 11 # SKIP SME not supported
11600 22:59:57.441601 # ok 12 # SKIP SME not supported
11601 22:59:57.442054 # ok 13 # SKIP SME not supported
11602 22:59:57.444724 # ok 14 # SKIP SME not supported
11603 22:59:57.447956 # ok 15 # SKIP SME not supported
11604 22:59:57.451169 # ok 16 # SKIP SME not supported
11605 22:59:57.454611 # ok 17 # SKIP SME not supported
11606 22:59:57.457849 # ok 18 # SKIP SME not supported
11607 22:59:57.461012 # ok 19 # SKIP SME not supported
11608 22:59:57.464540 # ok 20 # SKIP SME not supported
11609 22:59:57.467367 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11610 22:59:57.471139 ok 32 selftests: arm64: vec-syscfg
11611 22:59:57.474082 # selftests: arm64: za-fork
11612 22:59:57.474185 # TAP version 13
11613 22:59:57.477652 # 1..1
11614 22:59:57.477757 # # PID: 1205
11615 22:59:57.480967 # # SME support not present
11616 22:59:57.481080 # ok 0 skipped
11617 22:59:57.487667 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11618 22:59:57.491135 ok 33 selftests: arm64: za-fork
11619 22:59:57.491273 # selftests: arm64: za-ptrace
11620 22:59:57.494085 # TAP version 13
11621 22:59:57.494239 # 1..1
11622 22:59:57.497267 # ok 2 # SKIP SME not available
11623 22:59:57.504405 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11624 22:59:57.507282 ok 34 selftests: arm64: za-ptrace # SKIP
11625 22:59:57.511015 # selftests: arm64: check_buffer_fill
11626 22:59:57.513961 # # SKIP: MTE features unavailable
11627 22:59:57.517234 ok 35 selftests: arm64: check_buffer_fill # SKIP
11628 22:59:57.520639 # selftests: arm64: check_child_memory
11629 22:59:57.558200 # # SKIP: MTE features unavailable
11630 22:59:57.564838 ok 36 selftests: arm64: check_child_memory # SKIP
11631 22:59:57.580438 # selftests: arm64: check_gcr_el1_cswitch
11632 22:59:57.628483 # # SKIP: MTE features unavailable
11633 22:59:57.635101 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11634 22:59:57.648984 # selftests: arm64: check_ksm_options
11635 22:59:57.696309 # # SKIP: MTE features unavailable
11636 22:59:57.702593 ok 38 selftests: arm64: check_ksm_options # SKIP
11637 22:59:57.717447 # selftests: arm64: check_mmap_options
11638 22:59:57.764443 # # SKIP: MTE features unavailable
11639 22:59:57.771220 ok 39 selftests: arm64: check_mmap_options # SKIP
11640 22:59:57.782952 # selftests: arm64: check_prctl
11641 22:59:57.820671 <6>[ 46.372699] vpu: disabling
11642 22:59:57.823370 <6>[ 46.375768] vproc2: disabling
11643 22:59:57.826933 <6>[ 46.379070] vproc1: disabling
11644 22:59:57.829902 <6>[ 46.382339] vaud18: disabling
11645 22:59:57.836725 <6>[ 46.385753] vsram_others: disabling
11646 22:59:57.839896 # TAP version 13<6>[ 46.389646] va09: disabling
11647 22:59:57.840331
11648 22:59:57.840670 # 1..5
11649 22:59:57.843335 # ok 1<6>[ 46.394064] vsram_md: disabling
11650 22:59:57.849846 check_basic_rea<6>[ 46.398890] Vgpu: disabling
11651 22:59:57.850274 d
11652 22:59:57.850613 # ok 2 NONE
11653 22:59:57.852802 # ok 3 # SKIP SYNC
11654 22:59:57.853277 # ok 4 # SKIP ASYNC
11655 22:59:57.856194 # ok 5 # SKIP SYNC+ASYNC
11656 22:59:57.859620 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11657 22:59:57.863120 ok 40 selftests: arm64: check_prctl
11658 22:59:57.869438 # selftests: arm64: check_tags_inclusion
11659 22:59:57.899574 # # SKIP: MTE features unavailable
11660 22:59:57.906416 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11661 22:59:57.916089 # selftests: arm64: check_user_mem
11662 22:59:57.965274 # # SKIP: MTE features unavailable
11663 22:59:57.971383 ok 42 selftests: arm64: check_user_mem # SKIP
11664 22:59:57.981913 # selftests: arm64: btitest
11665 22:59:58.028645 # TAP version 13
11666 22:59:58.028829 # 1..18
11667 22:59:58.031950 # # HWCAP_PACA not present
11668 22:59:58.035353 # # HWCAP2_BTI not present
11669 22:59:58.038521 # # Test binary built for BTI
11670 22:59:58.042040 # ok 1 nohint_func/call_using_br_x0 # SKIP
11671 22:59:58.045053 # ok 1 nohint_func/call_using_br_x16 # SKIP
11672 22:59:58.048673 # ok 1 nohint_func/call_using_blr # SKIP
11673 22:59:58.052016 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11674 22:59:58.055273 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11675 22:59:58.061701 # ok 1 bti_none_func/call_using_blr # SKIP
11676 22:59:58.065323 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11677 22:59:58.068713 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11678 22:59:58.071861 # ok 1 bti_c_func/call_using_blr # SKIP
11679 22:59:58.075336 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11680 22:59:58.078391 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11681 22:59:58.081701 # ok 1 bti_j_func/call_using_blr # SKIP
11682 22:59:58.085219 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11683 22:59:58.091436 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11684 22:59:58.094957 # ok 1 bti_jc_func/call_using_blr # SKIP
11685 22:59:58.097942 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11686 22:59:58.101626 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11687 22:59:58.104743 # ok 1 paciasp_func/call_using_blr # SKIP
11688 22:59:58.111264 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11689 22:59:58.114690 # # WARNING - EXPECTED TEST COUNT WRONG
11690 22:59:58.118264 ok 43 selftests: arm64: btitest
11691 22:59:58.121219 # selftests: arm64: nobtitest
11692 22:59:58.121644 # TAP version 13
11693 22:59:58.121985 # 1..18
11694 22:59:58.124705 # # HWCAP_PACA not present
11695 22:59:58.127784 # # HWCAP2_BTI not present
11696 22:59:58.131225 # # Test binary not built for BTI
11697 22:59:58.134604 # ok 1 nohint_func/call_using_br_x0 # SKIP
11698 22:59:58.137988 # ok 1 nohint_func/call_using_br_x16 # SKIP
11699 22:59:58.141222 # ok 1 nohint_func/call_using_blr # SKIP
11700 22:59:58.144521 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11701 22:59:58.151001 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11702 22:59:58.153868 # ok 1 bti_none_func/call_using_blr # SKIP
11703 22:59:58.157236 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11704 22:59:58.160905 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11705 22:59:58.164534 # ok 1 bti_c_func/call_using_blr # SKIP
11706 22:59:58.167451 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11707 22:59:58.170792 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11708 22:59:58.174154 # ok 1 bti_j_func/call_using_blr # SKIP
11709 22:59:58.180735 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11710 22:59:58.183787 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11711 22:59:58.187464 # ok 1 bti_jc_func/call_using_blr # SKIP
11712 22:59:58.190786 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11713 22:59:58.193840 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11714 22:59:58.197069 # ok 1 paciasp_func/call_using_blr # SKIP
11715 22:59:58.203856 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11716 22:59:58.207664 # # WARNING - EXPECTED TEST COUNT WRONG
11717 22:59:58.210659 ok 44 selftests: arm64: nobtitest
11718 22:59:58.213973 # selftests: arm64: hwcap
11719 22:59:58.214537 # TAP version 13
11720 22:59:58.215052 # 1..28
11721 22:59:58.216862 # ok 1 cpuinfo_match_RNG
11722 22:59:58.220304 # # SIGILL reported for RNG
11723 22:59:58.223920 # ok 2 # SKIP sigill_RNG
11724 22:59:58.224344 # ok 3 cpuinfo_match_SME
11725 22:59:58.227152 # ok 4 sigill_SME
11726 22:59:58.227676 # ok 5 cpuinfo_match_SVE
11727 22:59:58.230835 # ok 6 sigill_SVE
11728 22:59:58.233459 # ok 7 cpuinfo_match_SVE 2
11729 22:59:58.233892 # # SIGILL reported for SVE 2
11730 22:59:58.236911 # ok 8 # SKIP sigill_SVE 2
11731 22:59:58.239872 # ok 9 cpuinfo_match_SVE AES
11732 22:59:58.243283 # # SIGILL reported for SVE AES
11733 22:59:58.246856 # ok 10 # SKIP sigill_SVE AES
11734 22:59:58.249674 # ok 11 cpuinfo_match_SVE2 PMULL
11735 22:59:58.250235 # # SIGILL reported for SVE2 PMULL
11736 22:59:58.252886 # ok 12 # SKIP sigill_SVE2 PMULL
11737 22:59:58.255973 # ok 13 cpuinfo_match_SVE2 BITPERM
11738 22:59:58.259536 # # SIGILL reported for SVE2 BITPERM
11739 22:59:58.262984 # ok 14 # SKIP sigill_SVE2 BITPERM
11740 22:59:58.266327 # ok 15 cpuinfo_match_SVE2 SHA3
11741 22:59:58.269426 # # SIGILL reported for SVE2 SHA3
11742 22:59:58.272955 # ok 16 # SKIP sigill_SVE2 SHA3
11743 22:59:58.276082 # ok 17 cpuinfo_match_SVE2 SM4
11744 22:59:58.279593 # # SIGILL reported for SVE2 SM4
11745 22:59:58.279682 # ok 18 # SKIP sigill_SVE2 SM4
11746 22:59:58.282744 # ok 19 cpuinfo_match_SVE2 I8MM
11747 22:59:58.286148 # # SIGILL reported for SVE2 I8MM
11748 22:59:58.289390 # ok 20 # SKIP sigill_SVE2 I8MM
11749 22:59:58.292770 # ok 21 cpuinfo_match_SVE2 F32MM
11750 22:59:58.295703 # # SIGILL reported for SVE2 F32MM
11751 22:59:58.299194 # ok 22 # SKIP sigill_SVE2 F32MM
11752 22:59:58.302619 # ok 23 cpuinfo_match_SVE2 F64MM
11753 22:59:58.305519 # # SIGILL reported for SVE2 F64MM
11754 22:59:58.309117 # ok 24 # SKIP sigill_SVE2 F64MM
11755 22:59:58.309210 # ok 25 cpuinfo_match_SVE2 BF16
11756 22:59:58.312448 # # SIGILL reported for SVE2 BF16
11757 22:59:58.315719 # ok 26 # SKIP sigill_SVE2 BF16
11758 22:59:58.319177 # ok 27 cpuinfo_match_SVE2 EBF16
11759 22:59:58.322409 # ok 28 # SKIP sigill_SVE2 EBF16
11760 22:59:58.329199 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11761 22:59:58.329310 ok 45 selftests: arm64: hwcap
11762 22:59:58.332323 # selftests: arm64: ptrace
11763 22:59:58.335706 # TAP version 13
11764 22:59:58.335811 # 1..7
11765 22:59:58.338911 # # Parent is 1434, child is 1435
11766 22:59:58.338999 # ok 1 read_tpidr_one
11767 22:59:58.342237 # ok 2 write_tpidr_one
11768 22:59:58.345775 # ok 3 verify_tpidr_one
11769 22:59:58.345881 # ok 4 count_tpidrs
11770 22:59:58.348990 # ok 5 tpidr2_write
11771 22:59:58.349099 # ok 6 tpidr2_read
11772 22:59:58.352389 # ok 7 write_tpidr_only
11773 22:59:58.355654 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11774 22:59:58.358719 ok 46 selftests: arm64: ptrace
11775 22:59:58.362114 # selftests: arm64: syscall-abi
11776 22:59:58.365413 # TAP version 13
11777 22:59:58.365526 # 1..2
11778 22:59:58.365595 # ok 1 getpid() FPSIMD
11779 22:59:58.368759 # ok 2 sched_yield() FPSIMD
11780 22:59:58.375478 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11781 22:59:58.378429 ok 47 selftests: arm64: syscall-abi
11782 22:59:58.378517 # selftests: arm64: tpidr2
11783 22:59:58.381846 # TAP version 13
11784 22:59:58.381928 # 1..5
11785 22:59:58.385349 # # PID: 1469
11786 22:59:58.385433 # # SME support not present
11787 22:59:58.388267 # ok 0 skipped, TPIDR2 not supported
11788 22:59:58.391875 # ok 1 skipped, TPIDR2 not supported
11789 22:59:58.394889 # ok 2 skipped, TPIDR2 not supported
11790 22:59:58.398527 # ok 3 skipped, TPIDR2 not supported
11791 22:59:58.401525 # ok 4 skipped, TPIDR2 not supported
11792 22:59:58.408357 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11793 22:59:58.411562 ok 48 selftests: arm64: tpidr2
11794 22:59:58.863039 arm64_tags_test pass
11795 22:59:58.866397 arm64_run_tags_test_sh pass
11796 22:59:58.869580 arm64_fake_sigreturn_bad_magic pass
11797 22:59:58.872655 arm64_fake_sigreturn_bad_size pass
11798 22:59:58.876342 arm64_fake_sigreturn_bad_size_for_magic0 pass
11799 22:59:58.879523 arm64_fake_sigreturn_duplicated_fpsimd pass
11800 22:59:58.882775 arm64_fake_sigreturn_misaligned_sp pass
11801 22:59:58.886513 arm64_fake_sigreturn_missing_fpsimd pass
11802 22:59:58.889666 arm64_fake_sigreturn_sme_change_vl skip
11803 22:59:58.896266 arm64_fake_sigreturn_sve_change_vl skip
11804 22:59:58.899204 arm64_mangle_pstate_invalid_compat_toggle pass
11805 22:59:58.902724 arm64_mangle_pstate_invalid_daif_bits pass
11806 22:59:58.905908 arm64_mangle_pstate_invalid_mode_el1h pass
11807 22:59:58.909355 arm64_mangle_pstate_invalid_mode_el1t pass
11808 22:59:58.912562 arm64_mangle_pstate_invalid_mode_el2h pass
11809 22:59:58.919010 arm64_mangle_pstate_invalid_mode_el2t pass
11810 22:59:58.922611 arm64_mangle_pstate_invalid_mode_el3h pass
11811 22:59:58.925557 arm64_mangle_pstate_invalid_mode_el3t pass
11812 22:59:58.928949 arm64_sme_trap_no_sm skip
11813 22:59:58.932454 arm64_sme_trap_non_streaming skip
11814 22:59:58.932530 arm64_sme_trap_za pass
11815 22:59:58.935610 arm64_sme_vl skip
11816 22:59:58.935727 arm64_ssve_regs skip
11817 22:59:58.938778 arm64_sve_regs skip
11818 22:59:58.938867 arm64_sve_vl skip
11819 22:59:58.942143 arm64_za_no_regs skip
11820 22:59:58.942268 arm64_za_regs skip
11821 22:59:58.945625 arm64_pac_PAUTH_not_enabled skip
11822 22:59:58.948587 arm64_pac_PAUTH_not_enabled skip
11823 22:59:58.952080 arm64_pac_Generic_PAUTH_not_enabled skip
11824 22:59:58.955477 arm64_pac_PAUTH_not_enabled skip
11825 22:59:58.958518 arm64_pac_PAUTH_not_enabled skip
11826 22:59:58.962031 arm64_pac_PAUTH_not_enabled skip
11827 22:59:58.965190 arm64_pac_Generic_PAUTH_not_enabled skip
11828 22:59:58.968585 arm64_pac pass
11829 22:59:58.968668 arm64_fp-stress_FPSIMD-0-0 pass
11830 22:59:58.971895 arm64_fp-stress_FPSIMD-0-1 pass
11831 22:59:58.975202 arm64_fp-stress_FPSIMD-1-0 pass
11832 22:59:58.978455 arm64_fp-stress_FPSIMD-1-1 pass
11833 22:59:58.981915 arm64_fp-stress_FPSIMD-2-0 pass
11834 22:59:58.984871 arm64_fp-stress_FPSIMD-2-1 pass
11835 22:59:58.988183 arm64_fp-stress_FPSIMD-3-0 pass
11836 22:59:58.988290 arm64_fp-stress_FPSIMD-3-1 pass
11837 22:59:58.991532 arm64_fp-stress_FPSIMD-4-0 pass
11838 22:59:58.994883 arm64_fp-stress_FPSIMD-4-1 pass
11839 22:59:58.998510 arm64_fp-stress_FPSIMD-5-0 pass
11840 22:59:59.001651 arm64_fp-stress_FPSIMD-5-1 pass
11841 22:59:59.004871 arm64_fp-stress_FPSIMD-6-0 pass
11842 22:59:59.008363 arm64_fp-stress_FPSIMD-6-1 pass
11843 22:59:59.011471 arm64_fp-stress_FPSIMD-7-0 pass
11844 22:59:59.011555 arm64_fp-stress_FPSIMD-7-1 pass
11845 22:59:59.014468 arm64_fp-stress pass
11846 22:59:59.017972 arm64_sve-ptrace_SVE_not_available skip
11847 22:59:59.021391 arm64_sve-ptrace skip
11848 22:59:59.024984 arm64_sve-probe-vls_SVE_not_available skip
11849 22:59:59.025080 arm64_sve-probe-vls skip
11850 22:59:59.031530 arm64_vec-syscfg_SVE_not_supported skip
11851 22:59:59.034476 arm64_vec-syscfg_SVE_not_supported skip
11852 22:59:59.038117 arm64_vec-syscfg_SVE_not_supported skip
11853 22:59:59.041240 arm64_vec-syscfg_SVE_not_supported skip
11854 22:59:59.044755 arm64_vec-syscfg_SVE_not_supported skip
11855 22:59:59.047675 arm64_vec-syscfg_SVE_not_supported skip
11856 22:59:59.051241 arm64_vec-syscfg_SVE_not_supported skip
11857 22:59:59.054392 arm64_vec-syscfg_SVE_not_supported skip
11858 22:59:59.057639 arm64_vec-syscfg_SVE_not_supported skip
11859 22:59:59.061159 arm64_vec-syscfg_SVE_not_supported skip
11860 22:59:59.064233 arm64_vec-syscfg_SME_not_supported skip
11861 22:59:59.067388 arm64_vec-syscfg_SME_not_supported skip
11862 22:59:59.070948 arm64_vec-syscfg_SME_not_supported skip
11863 22:59:59.077610 arm64_vec-syscfg_SME_not_supported skip
11864 22:59:59.080533 arm64_vec-syscfg_SME_not_supported skip
11865 22:59:59.084209 arm64_vec-syscfg_SME_not_supported skip
11866 22:59:59.087652 arm64_vec-syscfg_SME_not_supported skip
11867 22:59:59.090711 arm64_vec-syscfg_SME_not_supported skip
11868 22:59:59.094457 arm64_vec-syscfg_SME_not_supported skip
11869 22:59:59.097529 arm64_vec-syscfg_SME_not_supported skip
11870 22:59:59.100749 arm64_vec-syscfg pass
11871 22:59:59.100848 arm64_za-fork_skipped pass
11872 22:59:59.104143 arm64_za-fork pass
11873 22:59:59.107436 arm64_za-ptrace_SME_not_available skip
11874 22:59:59.110845 arm64_za-ptrace skip
11875 22:59:59.111270 arm64_check_buffer_fill skip
11876 22:59:59.114331 arm64_check_child_memory skip
11877 22:59:59.117077 arm64_check_gcr_el1_cswitch skip
11878 22:59:59.120738 arm64_check_ksm_options skip
11879 22:59:59.123887 arm64_check_mmap_options skip
11880 22:59:59.127367 arm64_check_prctl_check_basic_read pass
11881 22:59:59.127936 arm64_check_prctl_NONE pass
11882 22:59:59.130436 arm64_check_prctl_SYNC skip
11883 22:59:59.133942 arm64_check_prctl_ASYNC skip
11884 22:59:59.137261 arm64_check_prctl_SYNC_ASYNC skip
11885 22:59:59.140401 arm64_check_prctl pass
11886 22:59:59.140951 arm64_check_tags_inclusion skip
11887 22:59:59.143863 arm64_check_user_mem skip
11888 22:59:59.147401 arm64_btitest_nohint_func_call_using_br_x0 skip
11889 22:59:59.153416 arm64_btitest_nohint_func_call_using_br_x16 skip
11890 22:59:59.156534 arm64_btitest_nohint_func_call_using_blr skip
11891 22:59:59.160081 arm64_btitest_bti_none_func_call_using_br_x0 skip
11892 22:59:59.166483 arm64_btitest_bti_none_func_call_using_br_x16 skip
11893 22:59:59.170041 arm64_btitest_bti_none_func_call_using_blr skip
11894 22:59:59.173450 arm64_btitest_bti_c_func_call_using_br_x0 skip
11895 22:59:59.179611 arm64_btitest_bti_c_func_call_using_br_x16 skip
11896 22:59:59.183128 arm64_btitest_bti_c_func_call_using_blr skip
11897 22:59:59.186685 arm64_btitest_bti_j_func_call_using_br_x0 skip
11898 22:59:59.190053 arm64_btitest_bti_j_func_call_using_br_x16 skip
11899 22:59:59.192931 arm64_btitest_bti_j_func_call_using_blr skip
11900 22:59:59.199372 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11901 22:59:59.202944 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11902 22:59:59.206354 arm64_btitest_bti_jc_func_call_using_blr skip
11903 22:59:59.212950 arm64_btitest_paciasp_func_call_using_br_x0 skip
11904 22:59:59.216602 arm64_btitest_paciasp_func_call_using_br_x16 skip
11905 22:59:59.219658 arm64_btitest_paciasp_func_call_using_blr skip
11906 22:59:59.222649 arm64_btitest pass
11907 22:59:59.226121 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11908 22:59:59.229132 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11909 22:59:59.236283 arm64_nobtitest_nohint_func_call_using_blr skip
11910 22:59:59.239125 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11911 22:59:59.245715 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11912 22:59:59.249204 arm64_nobtitest_bti_none_func_call_using_blr skip
11913 22:59:59.252294 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11914 22:59:59.259249 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11915 22:59:59.262317 arm64_nobtitest_bti_c_func_call_using_blr skip
11916 22:59:59.265797 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11917 22:59:59.268751 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11918 22:59:59.275756 arm64_nobtitest_bti_j_func_call_using_blr skip
11919 22:59:59.278950 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11920 22:59:59.282375 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11921 22:59:59.288748 arm64_nobtitest_bti_jc_func_call_using_blr skip
11922 22:59:59.292019 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11923 22:59:59.298919 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11924 22:59:59.302103 arm64_nobtitest_paciasp_func_call_using_blr skip
11925 22:59:59.302189 arm64_nobtitest pass
11926 22:59:59.305159 arm64_hwcap_cpuinfo_match_RNG pass
11927 22:59:59.308515 arm64_hwcap_sigill_RNG skip
11928 22:59:59.311957 arm64_hwcap_cpuinfo_match_SME pass
11929 22:59:59.315089 arm64_hwcap_sigill_SME pass
11930 22:59:59.318530 arm64_hwcap_cpuinfo_match_SVE pass
11931 22:59:59.321521 arm64_hwcap_sigill_SVE pass
11932 22:59:59.324963 arm64_hwcap_cpuinfo_match_SVE_2 pass
11933 22:59:59.325048 arm64_hwcap_sigill_SVE_2 skip
11934 22:59:59.328349 arm64_hwcap_cpuinfo_match_SVE_AES pass
11935 22:59:59.331751 arm64_hwcap_sigill_SVE_AES skip
11936 22:59:59.335150 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11937 22:59:59.338154 arm64_hwcap_sigill_SVE2_PMULL skip
11938 22:59:59.344755 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11939 22:59:59.348062 arm64_hwcap_sigill_SVE2_BITPERM skip
11940 22:59:59.351519 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11941 22:59:59.354891 arm64_hwcap_sigill_SVE2_SHA3 skip
11942 22:59:59.357869 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11943 22:59:59.361629 arm64_hwcap_sigill_SVE2_SM4 skip
11944 22:59:59.364504 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11945 22:59:59.368040 arm64_hwcap_sigill_SVE2_I8MM skip
11946 22:59:59.371317 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11947 22:59:59.374861 arm64_hwcap_sigill_SVE2_F32MM skip
11948 22:59:59.377758 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11949 22:59:59.381042 arm64_hwcap_sigill_SVE2_F64MM skip
11950 22:59:59.384628 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
11951 22:59:59.387721 arm64_hwcap_sigill_SVE2_BF16 skip
11952 22:59:59.391076 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
11953 22:59:59.394503 arm64_hwcap_sigill_SVE2_EBF16 skip
11954 22:59:59.394585 arm64_hwcap pass
11955 22:59:59.397325 arm64_ptrace_read_tpidr_one pass
11956 22:59:59.401146 arm64_ptrace_write_tpidr_one pass
11957 22:59:59.403979 arm64_ptrace_verify_tpidr_one pass
11958 22:59:59.407779 arm64_ptrace_count_tpidrs pass
11959 22:59:59.410753 arm64_ptrace_tpidr2_write pass
11960 22:59:59.413967 arm64_ptrace_tpidr2_read pass
11961 22:59:59.417433 arm64_ptrace_write_tpidr_only pass
11962 22:59:59.417516 arm64_ptrace pass
11963 22:59:59.420816 arm64_syscall-abi_getpid_FPSIMD pass
11964 22:59:59.424168 arm64_syscall-abi_sched_yield_FPSIMD pass
11965 22:59:59.427083 arm64_syscall-abi pass
11966 22:59:59.430479 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11967 22:59:59.433870 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11968 22:59:59.440237 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11969 22:59:59.443865 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11970 22:59:59.447301 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11971 22:59:59.450236 arm64_tpidr2 pass
11972 22:59:59.453637 + ../../utils/send-to-lava.sh ./output/result.txt
11973 22:59:59.460477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
11974 22:59:59.460759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
11976 22:59:59.463609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
11978 22:59:59.466972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
11979 22:59:59.473351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
11980 22:59:59.473605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
11982 22:59:59.479892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
11983 22:59:59.480168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
11985 22:59:59.486470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
11986 22:59:59.486723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
11988 22:59:59.493244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
11989 22:59:59.493498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
11991 22:59:59.503002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
11992 22:59:59.503278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
11994 22:59:59.509588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
11995 22:59:59.509838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
11997 22:59:59.516414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
11998 22:59:59.516666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
12000 22:59:59.546125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
12001 22:59:59.546377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
12003 22:59:59.582871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
12004 22:59:59.583125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
12006 22:59:59.618260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
12007 22:59:59.618520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
12009 22:59:59.655891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
12010 22:59:59.656146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
12012 22:59:59.689049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
12013 22:59:59.689304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
12015 22:59:59.738928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
12016 22:59:59.739610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
12018 22:59:59.782726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
12019 22:59:59.783398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
12021 22:59:59.830412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
12022 22:59:59.831086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
12024 22:59:59.877159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
12025 22:59:59.877416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
12027 22:59:59.910539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
12028 22:59:59.910801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
12030 22:59:59.941214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
12032 22:59:59.944301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
12033 22:59:59.972838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
12034 22:59:59.973091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
12036 23:00:00.004479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
12037 23:00:00.004733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
12039 23:00:00.037238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
12040 23:00:00.037495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
12042 23:00:00.075112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
12043 23:00:00.075365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
12045 23:00:00.111315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
12046 23:00:00.111574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
12048 23:00:00.145468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
12049 23:00:00.145725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
12051 23:00:00.185042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
12052 23:00:00.185296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
12054 23:00:00.227444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12056 23:00:00.230151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12057 23:00:00.265199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12059 23:00:00.268507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12060 23:00:00.307309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
12061 23:00:00.307678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
12063 23:00:00.337362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12065 23:00:00.340036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12066 23:00:00.372815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12068 23:00:00.375778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12069 23:00:00.406634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12071 23:00:00.409300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12072 23:00:00.445840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
12073 23:00:00.446147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
12075 23:00:00.472924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
12076 23:00:00.473303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
12078 23:00:00.506297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
12079 23:00:00.506588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
12081 23:00:00.541521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
12082 23:00:00.541809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
12084 23:00:00.576684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
12085 23:00:00.576958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
12087 23:00:00.611091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
12088 23:00:00.611373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
12090 23:00:00.648344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
12091 23:00:00.648625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
12093 23:00:00.683547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
12094 23:00:00.683818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
12096 23:00:00.718989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
12097 23:00:00.719269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
12099 23:00:00.752187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
12100 23:00:00.752449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12102 23:00:00.785519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12103 23:00:00.785813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12105 23:00:00.814842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12106 23:00:00.815119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12108 23:00:00.843813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12109 23:00:00.844078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12111 23:00:00.884694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12112 23:00:00.885037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12114 23:00:00.922698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12115 23:00:00.923070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12117 23:00:00.953849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12118 23:00:00.954215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12120 23:00:00.986954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12121 23:00:00.987260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12123 23:00:01.018306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12124 23:00:01.018658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12126 23:00:01.050705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12127 23:00:01.051009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12129 23:00:01.086795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip>
12130 23:00:01.087091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip
12132 23:00:01.119753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12133 23:00:01.120055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12135 23:00:01.157678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip>
12136 23:00:01.157949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip
12138 23:00:01.187866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12139 23:00:01.188157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12141 23:00:01.226400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12142 23:00:01.226715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12144 23:00:01.263631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12145 23:00:01.263899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12147 23:00:01.295589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12148 23:00:01.295861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12150 23:00:01.329202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12151 23:00:01.329483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12153 23:00:01.360311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12154 23:00:01.360569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12156 23:00:01.392718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12157 23:00:01.393028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12159 23:00:01.421151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12160 23:00:01.421426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12162 23:00:01.449791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12163 23:00:01.450051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12165 23:00:01.482125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12166 23:00:01.482388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12168 23:00:01.513371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12169 23:00:01.513641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12171 23:00:01.546481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12172 23:00:01.546760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12174 23:00:01.576887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12175 23:00:01.577176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12177 23:00:01.606581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12178 23:00:01.606838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12180 23:00:01.638324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12181 23:00:01.638634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12183 23:00:01.666559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12184 23:00:01.666826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12186 23:00:01.695542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12187 23:00:01.695821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12189 23:00:01.723101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12190 23:00:01.723398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12192 23:00:01.753302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12193 23:00:01.753604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12195 23:00:01.786256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12196 23:00:01.786538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12198 23:00:01.818054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12199 23:00:01.818370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12201 23:00:01.847153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12202 23:00:01.847432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12204 23:00:01.878974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12205 23:00:01.879260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12207 23:00:01.910983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12208 23:00:01.911275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12210 23:00:01.945924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip>
12211 23:00:01.946197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip
12213 23:00:01.976250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12214 23:00:01.976556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12216 23:00:02.010856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12217 23:00:02.011230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12219 23:00:02.048570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12220 23:00:02.048879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12222 23:00:02.083449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12224 23:00:02.086031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12225 23:00:02.117779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12226 23:00:02.118133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12228 23:00:02.150231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12229 23:00:02.150562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12231 23:00:02.186495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12232 23:00:02.186840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12234 23:00:02.213438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12235 23:00:02.213759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12237 23:00:02.245895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip>
12238 23:00:02.246235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip
12240 23:00:02.275282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip>
12241 23:00:02.275545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip
12243 23:00:02.308625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip
12245 23:00:02.311843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip>
12246 23:00:02.342327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12247 23:00:02.342595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12249 23:00:02.376524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12250 23:00:02.376823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12252 23:00:02.409365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12253 23:00:02.409649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12255 23:00:02.443204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12256 23:00:02.443511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12258 23:00:02.477510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12259 23:00:02.477811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12261 23:00:02.508956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12262 23:00:02.509228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12264 23:00:02.542576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12265 23:00:02.542889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12267 23:00:02.570584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12268 23:00:02.570931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12270 23:00:02.603552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12271 23:00:02.603911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12273 23:00:02.637990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12274 23:00:02.638347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12276 23:00:02.670000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12277 23:00:02.670410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12279 23:00:02.701198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12280 23:00:02.701488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12282 23:00:02.729926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12283 23:00:02.730211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12285 23:00:02.769892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12286 23:00:02.770201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12288 23:00:02.811305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12289 23:00:02.811640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12291 23:00:02.854081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12292 23:00:02.854416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12294 23:00:02.896413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12295 23:00:02.896731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12297 23:00:02.939148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12298 23:00:02.939488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12300 23:00:02.981181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12301 23:00:02.981504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12303 23:00:03.023913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12304 23:00:03.024262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12306 23:00:03.061028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12307 23:00:03.061344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12309 23:00:03.096207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12310 23:00:03.096545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12312 23:00:03.141559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12313 23:00:03.141896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12315 23:00:03.181241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12316 23:00:03.181566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12318 23:00:03.222041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12319 23:00:03.222370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12321 23:00:03.262082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12322 23:00:03.262404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12324 23:00:03.301934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12325 23:00:03.302298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12327 23:00:03.341940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12328 23:00:03.342317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12330 23:00:03.381691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12331 23:00:03.382009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12333 23:00:03.422280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12334 23:00:03.422627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12336 23:00:03.461222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12337 23:00:03.461540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12339 23:00:03.496878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12340 23:00:03.497201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12342 23:00:03.533974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12343 23:00:03.534285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12345 23:00:03.572320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12346 23:00:03.572652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12348 23:00:03.609053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12349 23:00:03.609372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12351 23:00:03.648714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12352 23:00:03.649060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12354 23:00:03.689422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12355 23:00:03.689726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12357 23:00:03.729442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12358 23:00:03.729804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12360 23:00:03.770326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12361 23:00:03.770614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12363 23:00:03.810870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12364 23:00:03.811149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12366 23:00:03.847466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12367 23:00:03.847763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12369 23:00:03.890126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12370 23:00:03.890424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12372 23:00:03.927759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip>
12373 23:00:03.928057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip
12375 23:00:03.967470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12376 23:00:03.967765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12378 23:00:04.008773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12379 23:00:04.009094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12381 23:00:04.043136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12382 23:00:04.043447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12384 23:00:04.079146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12385 23:00:04.079421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12387 23:00:04.110694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12388 23:00:04.110970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12390 23:00:04.135260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip>
12391 23:00:04.135525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip
12393 23:00:04.176105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12394 23:00:04.176368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12396 23:00:04.202989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip>
12397 23:00:04.203244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip
12399 23:00:04.244367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12400 23:00:04.244627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12402 23:00:04.279192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip>
12403 23:00:04.279448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip
12405 23:00:04.316563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12406 23:00:04.316878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12408 23:00:04.354077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip>
12409 23:00:04.354368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip
12411 23:00:04.396012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12412 23:00:04.396276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12414 23:00:04.430792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip>
12415 23:00:04.431049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip
12417 23:00:04.467921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12418 23:00:04.468174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12420 23:00:04.496527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip
12422 23:00:04.499676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip>
12423 23:00:04.534161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12424 23:00:04.534426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12426 23:00:04.569523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip
12428 23:00:04.572744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip>
12429 23:00:04.603835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12430 23:00:04.604113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12432 23:00:04.646290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip>
12433 23:00:04.646655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip
12435 23:00:04.699397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12436 23:00:04.699697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12438 23:00:04.742293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip>
12439 23:00:04.742562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip
12441 23:00:04.776857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12442 23:00:04.777120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12444 23:00:04.810793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip
12446 23:00:04.813528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip>
12447 23:00:04.852161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12448 23:00:04.852450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12450 23:00:04.888654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
12451 23:00:04.888944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
12453 23:00:04.922137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12454 23:00:04.922463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12456 23:00:04.958115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12458 23:00:04.960868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12459 23:00:04.990989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12461 23:00:04.994386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12462 23:00:05.029040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12463 23:00:05.029298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12465 23:00:05.065696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12466 23:00:05.065951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12468 23:00:05.101873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12469 23:00:05.102128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12471 23:00:05.137262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12472 23:00:05.137527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12474 23:00:05.167470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12475 23:00:05.167729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12477 23:00:05.200616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12478 23:00:05.200893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12480 23:00:05.232901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12481 23:00:05.233175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12483 23:00:05.268023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12484 23:00:05.268285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12486 23:00:05.292681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12487 23:00:05.292952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12489 23:00:05.333580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12490 23:00:05.333862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12492 23:00:05.368383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12493 23:00:05.368665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12495 23:00:05.397856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12496 23:00:05.398131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12498 23:00:05.435528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12499 23:00:05.435817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12501 23:00:05.466321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12502 23:00:05.466577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12504 23:00:05.492874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12505 23:00:05.492984 + set +x
12506 23:00:05.493251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12508 23:00:05.499763 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 10597663_1.6.2.3.5>
12509 23:00:05.500015 Received signal: <ENDRUN> 1_kselftest-arm64 10597663_1.6.2.3.5
12510 23:00:05.500087 Ending use of test pattern.
12511 23:00:05.500150 Ending test lava.1_kselftest-arm64 (10597663_1.6.2.3.5), duration 27.66
12513 23:00:05.502722 <LAVA_TEST_RUNNER EXIT>
12514 23:00:05.502975 ok: lava_test_shell seems to have completed
12515 23:00:05.503907 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: skip
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: skip
arm64_check_prctl_SYNC_ASYNC: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: skip
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: skip
arm64_hwcap_sigill_SVE2_BITPERM: skip
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: skip
arm64_hwcap_sigill_SVE2_F64MM: skip
arm64_hwcap_sigill_SVE2_I8MM: skip
arm64_hwcap_sigill_SVE2_PMULL: skip
arm64_hwcap_sigill_SVE2_SHA3: skip
arm64_hwcap_sigill_SVE2_SM4: skip
arm64_hwcap_sigill_SVE_2: skip
arm64_hwcap_sigill_SVE_AES: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_Generic_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_SVE_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_SVE_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_not_supported: skip
arm64_vec-syscfg_SVE_not_supported: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_SME_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
12516 23:00:05.504051 end: 3.1 lava-test-shell (duration 00:00:28) [common]
12517 23:00:05.504137 end: 3 lava-test-retry (duration 00:00:28) [common]
12518 23:00:05.504222 start: 4 finalize (timeout 00:07:28) [common]
12519 23:00:05.504309 start: 4.1 power-off (timeout 00:00:30) [common]
12520 23:00:05.504457 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
12521 23:00:05.580278 >> Command sent successfully.
12522 23:00:05.582795 Returned 0 in 0 seconds
12523 23:00:05.683198 end: 4.1 power-off (duration 00:00:00) [common]
12525 23:00:05.683529 start: 4.2 read-feedback (timeout 00:07:27) [common]
12526 23:00:05.683813 Listened to connection for namespace 'common' for up to 1s
12527 23:00:06.684881 Finalising connection for namespace 'common'
12528 23:00:06.685507 Disconnecting from shell: Finalise
12529 23:00:06.686086 / #
12530 23:00:06.786800 end: 4.2 read-feedback (duration 00:00:01) [common]
12531 23:00:06.786978 end: 4 finalize (duration 00:00:01) [common]
12532 23:00:06.787097 Cleaning after the job
12533 23:00:06.787196 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597663/tftp-deploy-1ioyhets/ramdisk
12534 23:00:06.789060 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597663/tftp-deploy-1ioyhets/kernel
12535 23:00:06.797005 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597663/tftp-deploy-1ioyhets/dtb
12536 23:00:06.797192 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597663/tftp-deploy-1ioyhets/nfsrootfs
12537 23:00:06.857170 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597663/tftp-deploy-1ioyhets/modules
12538 23:00:06.862052 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10597663
12539 23:00:07.385919 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10597663
12540 23:00:07.386105 Job finished correctly