Boot log: mt8192-asurada-spherion-r0

    1 22:58:25.530404  lava-dispatcher, installed at version: 2023.05.1
    2 22:58:25.530621  start: 0 validate
    3 22:58:25.530755  Start time: 2023-06-05 22:58:25.530746+00:00 (UTC)
    4 22:58:25.530880  Using caching service: 'http://localhost/cache/?uri=%s'
    5 22:58:25.531007  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
    6 22:58:25.821544  Using caching service: 'http://localhost/cache/?uri=%s'
    7 22:58:25.821798  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
    8 22:58:26.102782  Using caching service: 'http://localhost/cache/?uri=%s'
    9 22:58:26.103027  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
   10 22:58:26.387933  Using caching service: 'http://localhost/cache/?uri=%s'
   11 22:58:26.388172  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
   12 22:58:26.673203  Using caching service: 'http://localhost/cache/?uri=%s'
   13 22:58:26.673452  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
   14 22:58:26.966582  validate duration: 1.44
   16 22:58:26.966934  start: 1 tftp-deploy (timeout 00:10:00) [common]
   17 22:58:26.967066  start: 1.1 download-retry (timeout 00:10:00) [common]
   18 22:58:26.967186  start: 1.1.1 http-download (timeout 00:10:00) [common]
   19 22:58:26.967347  Not decompressing ramdisk as can be used compressed.
   20 22:58:26.967464  downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/initrd.cpio.gz
   21 22:58:26.967558  saving as /var/lib/lava/dispatcher/tmp/10597704/tftp-deploy-2k1f8v8j/ramdisk/initrd.cpio.gz
   22 22:58:26.967648  total size: 4665601 (4MB)
   23 22:58:26.969197  progress   0% (0MB)
   24 22:58:26.970747  progress   5% (0MB)
   25 22:58:26.972072  progress  10% (0MB)
   26 22:58:26.973469  progress  15% (0MB)
   27 22:58:26.974780  progress  20% (0MB)
   28 22:58:26.976071  progress  25% (1MB)
   29 22:58:26.977441  progress  30% (1MB)
   30 22:58:26.978766  progress  35% (1MB)
   31 22:58:26.980073  progress  40% (1MB)
   32 22:58:26.981557  progress  45% (2MB)
   33 22:58:26.982914  progress  50% (2MB)
   34 22:58:26.984204  progress  55% (2MB)
   35 22:58:26.985591  progress  60% (2MB)
   36 22:58:26.986896  progress  65% (2MB)
   37 22:58:26.988193  progress  70% (3MB)
   38 22:58:26.989493  progress  75% (3MB)
   39 22:58:26.990743  progress  80% (3MB)
   40 22:58:26.992179  progress  85% (3MB)
   41 22:58:26.993545  progress  90% (4MB)
   42 22:58:26.994785  progress  95% (4MB)
   43 22:58:26.996069  progress 100% (4MB)
   44 22:58:26.996252  4MB downloaded in 0.03s (155.58MB/s)
   45 22:58:26.996452  end: 1.1.1 http-download (duration 00:00:00) [common]
   47 22:58:26.996764  end: 1.1 download-retry (duration 00:00:00) [common]
   48 22:58:26.996851  start: 1.2 download-retry (timeout 00:10:00) [common]
   49 22:58:26.996943  start: 1.2.1 http-download (timeout 00:10:00) [common]
   50 22:58:26.997073  downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
   51 22:58:26.997152  saving as /var/lib/lava/dispatcher/tmp/10597704/tftp-deploy-2k1f8v8j/kernel/Image
   52 22:58:26.997213  total size: 45746688 (43MB)
   53 22:58:26.997271  No compression specified
   54 22:58:26.998461  progress   0% (0MB)
   55 22:58:27.010739  progress   5% (2MB)
   56 22:58:27.022972  progress  10% (4MB)
   57 22:58:27.035457  progress  15% (6MB)
   58 22:58:27.048128  progress  20% (8MB)
   59 22:58:27.060734  progress  25% (10MB)
   60 22:58:27.072809  progress  30% (13MB)
   61 22:58:27.084916  progress  35% (15MB)
   62 22:58:27.096389  progress  40% (17MB)
   63 22:58:27.107821  progress  45% (19MB)
   64 22:58:27.119173  progress  50% (21MB)
   65 22:58:27.130434  progress  55% (24MB)
   66 22:58:27.141889  progress  60% (26MB)
   67 22:58:27.153612  progress  65% (28MB)
   68 22:58:27.165136  progress  70% (30MB)
   69 22:58:27.176513  progress  75% (32MB)
   70 22:58:27.187879  progress  80% (34MB)
   71 22:58:27.199378  progress  85% (37MB)
   72 22:58:27.210880  progress  90% (39MB)
   73 22:58:27.222222  progress  95% (41MB)
   74 22:58:27.233875  progress 100% (43MB)
   75 22:58:27.234007  43MB downloaded in 0.24s (184.25MB/s)
   76 22:58:27.234152  end: 1.2.1 http-download (duration 00:00:00) [common]
   78 22:58:27.234382  end: 1.2 download-retry (duration 00:00:00) [common]
   79 22:58:27.234470  start: 1.3 download-retry (timeout 00:10:00) [common]
   80 22:58:27.234558  start: 1.3.1 http-download (timeout 00:10:00) [common]
   81 22:58:27.234688  downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
   82 22:58:27.234757  saving as /var/lib/lava/dispatcher/tmp/10597704/tftp-deploy-2k1f8v8j/dtb/mt8192-asurada-spherion-r0.dtb
   83 22:58:27.234818  total size: 46924 (0MB)
   84 22:58:27.234877  No compression specified
   85 22:58:27.235942  progress  69% (0MB)
   86 22:58:27.236209  progress 100% (0MB)
   87 22:58:27.236361  0MB downloaded in 0.00s (29.05MB/s)
   88 22:58:27.236477  end: 1.3.1 http-download (duration 00:00:00) [common]
   90 22:58:27.236711  end: 1.3 download-retry (duration 00:00:00) [common]
   91 22:58:27.236794  start: 1.4 download-retry (timeout 00:10:00) [common]
   92 22:58:27.236875  start: 1.4.1 http-download (timeout 00:10:00) [common]
   93 22:58:27.236987  downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/full.rootfs.tar.xz
   94 22:58:27.237054  saving as /var/lib/lava/dispatcher/tmp/10597704/tftp-deploy-2k1f8v8j/nfsrootfs/full.rootfs.tar
   95 22:58:27.237116  total size: 200770336 (191MB)
   96 22:58:27.237190  Using unxz to decompress xz
   97 22:58:27.242107  progress   0% (0MB)
   98 22:58:27.765025  progress   5% (9MB)
   99 22:58:28.273762  progress  10% (19MB)
  100 22:58:28.854166  progress  15% (28MB)
  101 22:58:29.220407  progress  20% (38MB)
  102 22:58:29.543993  progress  25% (47MB)
  103 22:58:30.136198  progress  30% (57MB)
  104 22:58:30.686216  progress  35% (67MB)
  105 22:58:31.276344  progress  40% (76MB)
  106 22:58:31.865898  progress  45% (86MB)
  107 22:58:32.475880  progress  50% (95MB)
  108 22:58:33.161842  progress  55% (105MB)
  109 22:58:33.851486  progress  60% (114MB)
  110 22:58:33.980003  progress  65% (124MB)
  111 22:58:34.124812  progress  70% (134MB)
  112 22:58:34.224991  progress  75% (143MB)
  113 22:58:34.305321  progress  80% (153MB)
  114 22:58:34.380645  progress  85% (162MB)
  115 22:58:34.484001  progress  90% (172MB)
  116 22:58:34.787021  progress  95% (181MB)
  117 22:58:35.418427  progress 100% (191MB)
  118 22:58:35.423420  191MB downloaded in 8.19s (23.39MB/s)
  119 22:58:35.423780  end: 1.4.1 http-download (duration 00:00:08) [common]
  121 22:58:35.424212  end: 1.4 download-retry (duration 00:00:08) [common]
  122 22:58:35.424353  start: 1.5 download-retry (timeout 00:09:52) [common]
  123 22:58:35.424483  start: 1.5.1 http-download (timeout 00:09:52) [common]
  124 22:58:35.424689  downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
  125 22:58:35.424795  saving as /var/lib/lava/dispatcher/tmp/10597704/tftp-deploy-2k1f8v8j/modules/modules.tar
  126 22:58:35.424904  total size: 8552396 (8MB)
  127 22:58:35.425004  Using unxz to decompress xz
  128 22:58:35.429040  progress   0% (0MB)
  129 22:58:35.451757  progress   5% (0MB)
  130 22:58:35.477935  progress  10% (0MB)
  131 22:58:35.512024  progress  15% (1MB)
  132 22:58:35.541121  progress  20% (1MB)
  133 22:58:35.569711  progress  25% (2MB)
  134 22:58:35.597803  progress  30% (2MB)
  135 22:58:35.626210  progress  35% (2MB)
  136 22:58:35.653890  progress  40% (3MB)
  137 22:58:35.684697  progress  45% (3MB)
  138 22:58:35.713228  progress  50% (4MB)
  139 22:58:35.741706  progress  55% (4MB)
  140 22:58:35.768196  progress  60% (4MB)
  141 22:58:35.795884  progress  65% (5MB)
  142 22:58:35.823566  progress  70% (5MB)
  143 22:58:35.850483  progress  75% (6MB)
  144 22:58:35.879760  progress  80% (6MB)
  145 22:58:35.907540  progress  85% (6MB)
  146 22:58:35.934667  progress  90% (7MB)
  147 22:58:35.960665  progress  95% (7MB)
  148 22:58:35.987955  progress 100% (8MB)
  149 22:58:35.995080  8MB downloaded in 0.57s (14.30MB/s)
  150 22:58:35.995423  end: 1.5.1 http-download (duration 00:00:01) [common]
  152 22:58:35.995808  end: 1.5 download-retry (duration 00:00:01) [common]
  153 22:58:35.995936  start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
  154 22:58:35.996065  start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
  155 22:58:40.727039  Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10597704/extract-nfsrootfs-9szzfhg_
  156 22:58:40.727262  end: 1.6.1 extract-nfsrootfs (duration 00:00:05) [common]
  157 22:58:40.727371  start: 1.6.2 lava-overlay (timeout 00:09:46) [common]
  158 22:58:40.727543  [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr
  159 22:58:40.727677  makedir: /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr/lava-10597704/bin
  160 22:58:40.727782  makedir: /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr/lava-10597704/tests
  161 22:58:40.727883  makedir: /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr/lava-10597704/results
  162 22:58:40.727995  Creating /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr/lava-10597704/bin/lava-add-keys
  163 22:58:40.728136  Creating /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr/lava-10597704/bin/lava-add-sources
  164 22:58:40.728267  Creating /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr/lava-10597704/bin/lava-background-process-start
  165 22:58:40.728399  Creating /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr/lava-10597704/bin/lava-background-process-stop
  166 22:58:40.728535  Creating /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr/lava-10597704/bin/lava-common-functions
  167 22:58:40.728663  Creating /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr/lava-10597704/bin/lava-echo-ipv4
  168 22:58:40.728789  Creating /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr/lava-10597704/bin/lava-install-packages
  169 22:58:40.728913  Creating /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr/lava-10597704/bin/lava-installed-packages
  170 22:58:40.729035  Creating /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr/lava-10597704/bin/lava-os-build
  171 22:58:40.729169  Creating /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr/lava-10597704/bin/lava-probe-channel
  172 22:58:40.729299  Creating /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr/lava-10597704/bin/lava-probe-ip
  173 22:58:40.729427  Creating /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr/lava-10597704/bin/lava-target-ip
  174 22:58:40.729558  Creating /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr/lava-10597704/bin/lava-target-mac
  175 22:58:40.729688  Creating /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr/lava-10597704/bin/lava-target-storage
  176 22:58:40.729821  Creating /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr/lava-10597704/bin/lava-test-case
  177 22:58:40.729950  Creating /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr/lava-10597704/bin/lava-test-event
  178 22:58:40.730078  Creating /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr/lava-10597704/bin/lava-test-feedback
  179 22:58:40.730202  Creating /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr/lava-10597704/bin/lava-test-raise
  180 22:58:40.730336  Creating /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr/lava-10597704/bin/lava-test-reference
  181 22:58:40.730462  Creating /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr/lava-10597704/bin/lava-test-runner
  182 22:58:40.730591  Creating /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr/lava-10597704/bin/lava-test-set
  183 22:58:40.730720  Creating /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr/lava-10597704/bin/lava-test-shell
  184 22:58:40.730863  Updating /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr/lava-10597704/bin/lava-add-keys (debian)
  185 22:58:40.731034  Updating /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr/lava-10597704/bin/lava-add-sources (debian)
  186 22:58:40.731221  Updating /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr/lava-10597704/bin/lava-install-packages (debian)
  187 22:58:40.731420  Updating /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr/lava-10597704/bin/lava-installed-packages (debian)
  188 22:58:40.731621  Updating /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr/lava-10597704/bin/lava-os-build (debian)
  189 22:58:40.731777  Creating /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr/lava-10597704/environment
  190 22:58:40.731910  LAVA metadata
  191 22:58:40.732009  - LAVA_JOB_ID=10597704
  192 22:58:40.732103  - LAVA_DISPATCHER_IP=192.168.201.1
  193 22:58:40.732251  start: 1.6.2.1 lava-vland-overlay (timeout 00:09:46) [common]
  194 22:58:40.732347  skipped lava-vland-overlay
  195 22:58:40.732456  end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
  196 22:58:40.732567  start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:46) [common]
  197 22:58:40.732632  skipped lava-multinode-overlay
  198 22:58:40.732710  end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
  199 22:58:40.732795  start: 1.6.2.3 test-definition (timeout 00:09:46) [common]
  200 22:58:40.732871  Loading test definitions
  201 22:58:40.732965  start: 1.6.2.3.1 inline-repo-action (timeout 00:09:46) [common]
  202 22:58:40.733041  Using /lava-10597704 at stage 0
  203 22:58:40.733326  uuid=10597704_1.6.2.3.1 testdef=None
  204 22:58:40.733417  end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
  205 22:58:40.733509  start: 1.6.2.3.2 test-overlay (timeout 00:09:46) [common]
  206 22:58:40.733965  end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
  208 22:58:40.734198  start: 1.6.2.3.3 test-install-overlay (timeout 00:09:46) [common]
  209 22:58:40.734776  end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
  211 22:58:40.735015  start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:46) [common]
  212 22:58:40.735568  runner path: /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr/lava-10597704/0/tests/0_timesync-off test_uuid 10597704_1.6.2.3.1
  213 22:58:40.735721  end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
  215 22:58:40.735962  start: 1.6.2.3.5 git-repo-action (timeout 00:09:46) [common]
  216 22:58:40.736038  Using /lava-10597704 at stage 0
  217 22:58:40.736141  Fetching tests from https://github.com/kernelci/test-definitions.git
  218 22:58:40.736226  Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr/lava-10597704/0/tests/1_kselftest-rtc'
  219 22:58:43.469291  Running '/usr/bin/git checkout kernelci.org
  220 22:58:43.617487  Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr/lava-10597704/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
  221 22:58:43.618519  uuid=10597704_1.6.2.3.5 testdef=None
  222 22:58:43.618732  end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
  224 22:58:43.619155  start: 1.6.2.3.6 test-overlay (timeout 00:09:43) [common]
  225 22:58:43.620346  end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
  227 22:58:43.620693  start: 1.6.2.3.7 test-install-overlay (timeout 00:09:43) [common]
  228 22:58:43.622107  end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
  230 22:58:43.622532  start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:43) [common]
  231 22:58:43.624305  runner path: /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr/lava-10597704/0/tests/1_kselftest-rtc test_uuid 10597704_1.6.2.3.5
  232 22:58:43.624443  BOARD='mt8192-asurada-spherion-r0'
  233 22:58:43.624553  BRANCH='cip'
  234 22:58:43.624655  SKIPFILE='/dev/null'
  235 22:58:43.624755  SKIP_INSTALL='True'
  236 22:58:43.624844  TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
  237 22:58:43.624950  TST_CASENAME=''
  238 22:58:43.625050  TST_CMDFILES='rtc'
  239 22:58:43.625245  end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
  241 22:58:43.625637  Creating lava-test-runner.conf files
  242 22:58:43.625742  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10597704/lava-overlay-0aucjfjr/lava-10597704/0 for stage 0
  243 22:58:43.625879  - 0_timesync-off
  244 22:58:43.625978  - 1_kselftest-rtc
  245 22:58:43.626116  end: 1.6.2.3 test-definition (duration 00:00:03) [common]
  246 22:58:43.626247  start: 1.6.2.4 compress-overlay (timeout 00:09:43) [common]
  247 22:58:51.402675  end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
  248 22:58:51.402842  start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:36) [common]
  249 22:58:51.402936  end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
  250 22:58:51.403040  end: 1.6.2 lava-overlay (duration 00:00:11) [common]
  251 22:58:51.403135  start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:36) [common]
  252 22:58:51.525133  end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
  253 22:58:51.525515  start: 1.6.4 extract-modules (timeout 00:09:35) [common]
  254 22:58:51.525646  extracting modules file /var/lib/lava/dispatcher/tmp/10597704/tftp-deploy-2k1f8v8j/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597704/extract-nfsrootfs-9szzfhg_
  255 22:58:51.746443  extracting modules file /var/lib/lava/dispatcher/tmp/10597704/tftp-deploy-2k1f8v8j/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597704/extract-overlay-ramdisk-f7zhoslf/ramdisk
  256 22:58:51.966376  end: 1.6.4 extract-modules (duration 00:00:00) [common]
  257 22:58:51.966561  start: 1.6.5 apply-overlay-tftp (timeout 00:09:35) [common]
  258 22:58:51.966693  [common] Applying overlay to NFS
  259 22:58:51.966806  [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597704/compress-overlay-9fl8a2ql/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10597704/extract-nfsrootfs-9szzfhg_
  260 22:58:52.994160  end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
  261 22:58:52.994385  start: 1.6.6 configure-preseed-file (timeout 00:09:34) [common]
  262 22:58:52.994530  end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
  263 22:58:52.994667  start: 1.6.7 compress-ramdisk (timeout 00:09:34) [common]
  264 22:58:52.994785  Building ramdisk /var/lib/lava/dispatcher/tmp/10597704/extract-overlay-ramdisk-f7zhoslf/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10597704/extract-overlay-ramdisk-f7zhoslf/ramdisk
  265 22:58:53.279773  >> 117807 blocks

  266 22:58:55.247278  rename /var/lib/lava/dispatcher/tmp/10597704/extract-overlay-ramdisk-f7zhoslf/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10597704/tftp-deploy-2k1f8v8j/ramdisk/ramdisk.cpio.gz
  267 22:58:55.247752  end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
  268 22:58:55.247872  start: 1.6.8 prepare-kernel (timeout 00:09:32) [common]
  269 22:58:55.247975  start: 1.6.8.1 prepare-fit (timeout 00:09:32) [common]
  270 22:58:55.248080  Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10597704/tftp-deploy-2k1f8v8j/kernel/Image'
  271 22:59:08.121328  Returned 0 in 12 seconds
  272 22:59:08.221977  mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10597704/tftp-deploy-2k1f8v8j/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10597704/tftp-deploy-2k1f8v8j/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10597704/tftp-deploy-2k1f8v8j/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10597704/tftp-deploy-2k1f8v8j/kernel/image.itb
  273 22:59:08.560958  output: FIT description: Kernel Image image with one or more FDT blobs
  274 22:59:08.561357  output: Created:         Mon Jun  5 23:59:08 2023
  275 22:59:08.561439  output:  Image 0 (kernel-1)
  276 22:59:08.561508  output:   Description:  
  277 22:59:08.561572  output:   Created:      Mon Jun  5 23:59:08 2023
  278 22:59:08.561637  output:   Type:         Kernel Image
  279 22:59:08.561698  output:   Compression:  lzma compressed
  280 22:59:08.561759  output:   Data Size:    10085945 Bytes = 9849.56 KiB = 9.62 MiB
  281 22:59:08.561821  output:   Architecture: AArch64
  282 22:59:08.561879  output:   OS:           Linux
  283 22:59:08.561937  output:   Load Address: 0x00000000
  284 22:59:08.561994  output:   Entry Point:  0x00000000
  285 22:59:08.562051  output:   Hash algo:    crc32
  286 22:59:08.562105  output:   Hash value:   b2943ff2
  287 22:59:08.562159  output:  Image 1 (fdt-1)
  288 22:59:08.562212  output:   Description:  mt8192-asurada-spherion-r0
  289 22:59:08.562266  output:   Created:      Mon Jun  5 23:59:08 2023
  290 22:59:08.562320  output:   Type:         Flat Device Tree
  291 22:59:08.562373  output:   Compression:  uncompressed
  292 22:59:08.562426  output:   Data Size:    46924 Bytes = 45.82 KiB = 0.04 MiB
  293 22:59:08.562479  output:   Architecture: AArch64
  294 22:59:08.562532  output:   Hash algo:    crc32
  295 22:59:08.562585  output:   Hash value:   1df858fa
  296 22:59:08.562638  output:  Image 2 (ramdisk-1)
  297 22:59:08.562691  output:   Description:  unavailable
  298 22:59:08.562744  output:   Created:      Mon Jun  5 23:59:08 2023
  299 22:59:08.562798  output:   Type:         RAMDisk Image
  300 22:59:08.562850  output:   Compression:  Unknown Compression
  301 22:59:08.562904  output:   Data Size:    17645557 Bytes = 17231.99 KiB = 16.83 MiB
  302 22:59:08.562963  output:   Architecture: AArch64
  303 22:59:08.563017  output:   OS:           Linux
  304 22:59:08.563070  output:   Load Address: unavailable
  305 22:59:08.563123  output:   Entry Point:  unavailable
  306 22:59:08.563176  output:   Hash algo:    crc32
  307 22:59:08.563228  output:   Hash value:   ea675f1c
  308 22:59:08.563281  output:  Default Configuration: 'conf-1'
  309 22:59:08.563333  output:  Configuration 0 (conf-1)
  310 22:59:08.563386  output:   Description:  mt8192-asurada-spherion-r0
  311 22:59:08.563439  output:   Kernel:       kernel-1
  312 22:59:08.563491  output:   Init Ramdisk: ramdisk-1
  313 22:59:08.563545  output:   FDT:          fdt-1
  314 22:59:08.563597  output:   Loadables:    kernel-1
  315 22:59:08.563650  output: 
  316 22:59:08.563850  end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
  317 22:59:08.563948  end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
  318 22:59:08.564051  end: 1.6 prepare-tftp-overlay (duration 00:00:33) [common]
  319 22:59:08.564147  start: 1.7 lxc-create-udev-rule-action (timeout 00:09:18) [common]
  320 22:59:08.564230  No LXC device requested
  321 22:59:08.564309  end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
  322 22:59:08.564395  start: 1.8 deploy-device-env (timeout 00:09:18) [common]
  323 22:59:08.564474  end: 1.8 deploy-device-env (duration 00:00:00) [common]
  324 22:59:08.564556  Checking files for TFTP limit of 4294967296 bytes.
  325 22:59:08.565066  end: 1 tftp-deploy (duration 00:00:42) [common]
  326 22:59:08.565179  start: 2 depthcharge-action (timeout 00:05:00) [common]
  327 22:59:08.565272  start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
  328 22:59:08.565397  substitutions:
  329 22:59:08.565467  - {DTB}: 10597704/tftp-deploy-2k1f8v8j/dtb/mt8192-asurada-spherion-r0.dtb
  330 22:59:08.565531  - {INITRD}: 10597704/tftp-deploy-2k1f8v8j/ramdisk/ramdisk.cpio.gz
  331 22:59:08.565591  - {KERNEL}: 10597704/tftp-deploy-2k1f8v8j/kernel/Image
  332 22:59:08.565668  - {LAVA_MAC}: None
  333 22:59:08.565767  - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10597704/extract-nfsrootfs-9szzfhg_
  334 22:59:08.565875  - {NFS_SERVER_IP}: 192.168.201.1
  335 22:59:08.565943  - {PRESEED_CONFIG}: None
  336 22:59:08.566003  - {PRESEED_LOCAL}: None
  337 22:59:08.566061  - {RAMDISK}: 10597704/tftp-deploy-2k1f8v8j/ramdisk/ramdisk.cpio.gz
  338 22:59:08.566117  - {ROOT_PART}: None
  339 22:59:08.566173  - {ROOT}: None
  340 22:59:08.566228  - {SERVER_IP}: 192.168.201.1
  341 22:59:08.566282  - {TEE}: None
  342 22:59:08.566336  Parsed boot commands:
  343 22:59:08.566390  - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
  344 22:59:08.566574  Parsed boot commands: tftpboot 192.168.201.1 10597704/tftp-deploy-2k1f8v8j/kernel/image.itb 10597704/tftp-deploy-2k1f8v8j/kernel/cmdline 
  345 22:59:08.566668  end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
  346 22:59:08.566753  start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
  347 22:59:08.566844  start: 2.2.1 reset-connection (timeout 00:05:00) [common]
  348 22:59:08.566933  start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
  349 22:59:08.567009  Not connected, no need to disconnect.
  350 22:59:08.567084  end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
  351 22:59:08.567166  start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
  352 22:59:08.567235  [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-9'
  353 22:59:08.570653  Setting prompt string to ['lava-test: # ']
  354 22:59:08.571018  end: 2.2.1.2 connect-device (duration 00:00:00) [common]
  355 22:59:08.571133  end: 2.2.1 reset-connection (duration 00:00:00) [common]
  356 22:59:08.571238  start: 2.2.2 reset-device (timeout 00:05:00) [common]
  357 22:59:08.571333  start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
  358 22:59:08.571528  Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
  359 22:59:13.726176  >> Command sent successfully.

  360 22:59:13.738540  Returned 0 in 5 seconds
  361 22:59:13.839916  end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
  363 22:59:13.841546  end: 2.2.2 reset-device (duration 00:00:05) [common]
  364 22:59:13.842345  start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
  365 22:59:13.842990  Setting prompt string to 'Starting depthcharge on Spherion...'
  366 22:59:13.843543  Changing prompt to 'Starting depthcharge on Spherion...'
  367 22:59:13.844088  depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
  368 22:59:13.845518  [Enter `^Ec?' for help]

  369 22:59:14.001288  

  370 22:59:14.001815  

  371 22:59:14.002160  F0: 102B 0000

  372 22:59:14.002495  

  373 22:59:14.002886  F3: 1001 0000 [0200]

  374 22:59:14.003234  

  375 22:59:14.004658  F3: 1001 0000

  376 22:59:14.005085  

  377 22:59:14.005423  F7: 102D 0000

  378 22:59:14.005743  

  379 22:59:14.006049  F1: 0000 0000

  380 22:59:14.006348  

  381 22:59:14.008132  V0: 0000 0000 [0001]

  382 22:59:14.008602  

  383 22:59:14.009097  00: 0007 8000

  384 22:59:14.009458  

  385 22:59:14.011562  01: 0000 0000

  386 22:59:14.012182  

  387 22:59:14.012695  BP: 0C00 0209 [0000]

  388 22:59:14.013029  

  389 22:59:14.014555  G0: 1182 0000

  390 22:59:14.015104  

  391 22:59:14.015570  EC: 0000 0021 [4000]

  392 22:59:14.016022  

  393 22:59:14.018330  S7: 0000 0000 [0000]

  394 22:59:14.018801  

  395 22:59:14.019147  CC: 0000 0000 [0001]

  396 22:59:14.021296  

  397 22:59:14.021892  T0: 0000 0040 [010F]

  398 22:59:14.022401  

  399 22:59:14.022744  Jump to BL

  400 22:59:14.023090  

  401 22:59:14.047953  

  402 22:59:14.048562  

  403 22:59:14.048967  

  404 22:59:14.055406  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...

  405 22:59:14.059041  ARM64: Exception handlers installed.

  406 22:59:14.062556  ARM64: Testing exception

  407 22:59:14.066095  ARM64: Done test exception

  408 22:59:14.073505  Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000

  409 22:59:14.083729  Mapping address range [0x00000000:0x200000000) as     cacheable | read-write |     secure | device

  410 22:59:14.089840  Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000

  411 22:59:14.100003  Mapping address range [0x00100000:0x00120000) as     cacheable | read-write |     secure | normal

  412 22:59:14.106945  Backing address range [0x00000000:0x40000000) with new page table @0x0010f000

  413 22:59:14.113620  Backing address range [0x00000000:0x00200000) with new page table @0x00110000

  414 22:59:14.124616  Mapping address range [0x00200000:0x00300000) as     cacheable | read-write |     secure | normal

  415 22:59:14.130916  Backing address range [0x00200000:0x00400000) with new page table @0x00111000

  416 22:59:14.150866  Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write |     secure | normal

  417 22:59:14.153856  WDT: Last reset was cold boot

  418 22:59:14.157705  SPI1(PAD0) initialized at 2873684 Hz

  419 22:59:14.160931  SPI5(PAD0) initialized at 992727 Hz

  420 22:59:14.164084  VBOOT: Loading verstage.

  421 22:59:14.170929  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  422 22:59:14.174009  FMAP: Found "FLASH" version 1.1 at 0x20000.

  423 22:59:14.177524  FMAP: base = 0x0 size = 0x800000 #areas = 25

  424 22:59:14.180378  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

  425 22:59:14.188108  CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes

  426 22:59:14.194539  CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150

  427 22:59:14.205316  read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps

  428 22:59:14.205768  

  429 22:59:14.206207  

  430 22:59:14.215530  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...

  431 22:59:14.218861  ARM64: Exception handlers installed.

  432 22:59:14.222159  ARM64: Testing exception

  433 22:59:14.225437  ARM64: Done test exception

  434 22:59:14.229198  FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)

  435 22:59:14.232087  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  436 22:59:14.246751  Probing TPM: . done!

  437 22:59:14.247201  TPM ready after 0 ms

  438 22:59:14.253530  Connected to device vid:did:rid of 1ae0:0028:00

  439 22:59:14.263054  Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8

  440 22:59:14.301705  Initialized TPM device CR50 revision 0

  441 22:59:14.313916  tlcl_send_startup: Startup return code is 0

  442 22:59:14.314556  TPM: setup succeeded

  443 22:59:14.326354  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0

  444 22:59:14.334240  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

  445 22:59:14.341689  VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)

  446 22:59:14.355125  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

  447 22:59:14.358157  out: cmd=0xd: 03 f0 0d 00 00 00 00 00 

  448 22:59:14.361222  in-header: 03 07 00 00 08 00 00 00 

  449 22:59:14.364915  in-data: aa e4 47 04 13 02 00 00 

  450 22:59:14.368118  Chrome EC: UHEPI supported

  451 22:59:14.374838  out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 

  452 22:59:14.377787  in-header: 03 ad 00 00 08 00 00 00 

  453 22:59:14.381309  in-data: 00 20 20 08 00 00 00 00 

  454 22:59:14.381748  Phase 1

  455 22:59:14.384695  FMAP: area GBB found @ 3f5000 (12032 bytes)

  456 22:59:14.391278  VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7

  457 22:59:14.397451  VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7

  458 22:59:14.401010  Recovery requested (1009000e)

  459 22:59:14.405083  TPM: Extending digest for VBOOT: boot mode into PCR 0

  460 22:59:14.413580  tlcl_extend: response is 0

  461 22:59:14.421961  TPM: Extending digest for VBOOT: GBB HWID into PCR 1

  462 22:59:14.427068  tlcl_extend: response is 0

  463 22:59:14.433596  CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c

  464 22:59:14.453865  read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps

  465 22:59:14.460750  BS: bootblock times (exec / console): total (unknown) / 148 ms

  466 22:59:14.461187  

  467 22:59:14.461533  

  468 22:59:14.471654  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...

  469 22:59:14.474707  ARM64: Exception handlers installed.

  470 22:59:14.475147  ARM64: Testing exception

  471 22:59:14.478547  ARM64: Done test exception

  472 22:59:14.500196  pmic_efuse_setting: Set efuses in 11 msecs

  473 22:59:14.504321  pmwrap_interface_init: Select PMIF_VLD_RDY

  474 22:59:14.507502  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a

  475 22:59:14.514416  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a

  476 22:59:14.517763  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a

  477 22:59:14.524151  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a

  478 22:59:14.528286  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a

  479 22:59:14.531040  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a

  480 22:59:14.538181  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a

  481 22:59:14.541209  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a

  482 22:59:14.548054  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c

  483 22:59:14.551231  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a

  484 22:59:14.558036  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a

  485 22:59:14.561004  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c

  486 22:59:14.564197  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c

  487 22:59:14.571049  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a

  488 22:59:14.577897  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a

  489 22:59:14.584612  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a

  490 22:59:14.587714  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a

  491 22:59:14.594302  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a

  492 22:59:14.600929  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a

  493 22:59:14.604639  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a

  494 22:59:14.611240  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c

  495 22:59:14.618439  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a

  496 22:59:14.622302  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a

  497 22:59:14.629297  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c

  498 22:59:14.632248  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c

  499 22:59:14.639288  [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa

  500 22:59:14.642854  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92

  501 22:59:14.649596  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2

  502 22:59:14.652689  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82

  503 22:59:14.659854  [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10

  504 22:59:14.663684  [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425

  505 22:59:14.668681  [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010

  506 22:59:14.674848  [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f

  507 22:59:14.678598  [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000

  508 22:59:14.681640  [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8

  509 22:59:14.688300  [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb

  510 22:59:14.691959  [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698

  511 22:59:14.699049  [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3

  512 22:59:14.702597  [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92

  513 22:59:14.706286  [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a

  514 22:59:14.712944  [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2

  515 22:59:14.716449  [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a

  516 22:59:14.719528  [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a

  517 22:59:14.725935  [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a

  518 22:59:14.729601  [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a

  519 22:59:14.732623  [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82

  520 22:59:14.736248  [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c

  521 22:59:14.742845  [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a

  522 22:59:14.746194  [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a

  523 22:59:14.749166  [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c

  524 22:59:14.755836  [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c

  525 22:59:14.762449  [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248

  526 22:59:14.772141  [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1

  527 22:59:14.775917  [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0

  528 22:59:14.782149  [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248

  529 22:59:14.792407  [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0

  530 22:59:14.796075  [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0

  531 22:59:14.802293  [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1

  532 22:59:14.805300  [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1

  533 22:59:14.812616  [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x2e

  534 22:59:14.819093  [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2

  535 22:59:14.822238  [RTC]rtc_osc_init,62: osc32con val = 0xde6c

  536 22:59:14.825289  [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a

  537 22:59:14.836972  [RTC]rtc_get_frequency_meter,154: input=15, output=834

  538 22:59:14.846263  [RTC]rtc_get_frequency_meter,154: input=7, output=709

  539 22:59:14.855748  [RTC]rtc_get_frequency_meter,154: input=11, output=772

  540 22:59:14.864954  [RTC]rtc_get_frequency_meter,154: input=13, output=804

  541 22:59:14.874314  [RTC]rtc_get_frequency_meter,154: input=12, output=788

  542 22:59:14.884012  [RTC]rtc_get_frequency_meter,154: input=12, output=788

  543 22:59:14.893762  [RTC]rtc_get_frequency_meter,154: input=13, output=803

  544 22:59:14.896876  [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13

  545 22:59:14.904295  [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c

  546 22:59:14.907265  [RTC]rtc_boot_common,202: RTC_STATE_REBOOT

  547 22:59:14.910656  [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486

  548 22:59:14.917518  [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1

  549 22:59:14.920461  [RTC]rtc_bbpu_power_on,300: done BBPU=0x81

  550 22:59:14.924173  ADC[4]: Raw value=906357 ID=7

  551 22:59:14.924703  ADC[3]: Raw value=212912 ID=1

  552 22:59:14.927118  RAM Code: 0x71

  553 22:59:14.930987  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

  554 22:59:14.937329  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  555 22:59:14.944161  CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014

  556 22:59:14.950520  DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE

  557 22:59:14.953747  out: cmd=0xd: 03 f0 0d 00 00 00 00 00 

  558 22:59:14.957256  in-header: 03 07 00 00 08 00 00 00 

  559 22:59:14.960339  in-data: aa e4 47 04 13 02 00 00 

  560 22:59:14.964138  Chrome EC: UHEPI supported

  561 22:59:14.970441  out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 

  562 22:59:14.973546  in-header: 03 dd 00 00 08 00 00 00 

  563 22:59:14.977240  in-data: 90 20 60 08 00 00 00 00 

  564 22:59:14.980241  MRC: failed to locate region type 0.

  565 22:59:14.986956  DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)

  566 22:59:14.990058  DRAM-K: Running full calibration

  567 22:59:14.996861  DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE

  568 22:59:14.997428  header.status = 0x0

  569 22:59:14.999951  header.version = 0x6 (expected: 0x6)

  570 22:59:15.003680  header.size = 0xd00 (expected: 0xd00)

  571 22:59:15.006942  header.flags = 0x0

  572 22:59:15.013658  CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40

  573 22:59:15.030061  read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps

  574 22:59:15.037451  dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6

  575 22:59:15.040349  dram_init: ddr_geometry: 2

  576 22:59:15.043667  [EMI] MDL number = 2

  577 22:59:15.044100  [EMI] Get MDL freq = 0

  578 22:59:15.046751  dram_init: ddr_type: 0

  579 22:59:15.047181  is_discrete_lpddr4: 1

  580 22:59:15.050244  [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0

  581 22:59:15.050679  

  582 22:59:15.051026  

  583 22:59:15.053811  [Bian_co] ETT version 0.0.0.1

  584 22:59:15.060252   dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6

  585 22:59:15.060849  

  586 22:59:15.063687  dramc_set_vcore_voltage set vcore to 650000

  587 22:59:15.064124  Read voltage for 800, 4

  588 22:59:15.067346  Vio18 = 0

  589 22:59:15.067792  Vcore = 650000

  590 22:59:15.068143  Vdram = 0

  591 22:59:15.070389  Vddq = 0

  592 22:59:15.070825  Vmddr = 0

  593 22:59:15.073538  dram_init: config_dvfs: 1

  594 22:59:15.077193  [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0

  595 22:59:15.083979  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

  596 22:59:15.087125  [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9

  597 22:59:15.090267  freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9

  598 22:59:15.093718  [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9

  599 22:59:15.097066  freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9

  600 22:59:15.100207  MEM_TYPE=3, freq_sel=18

  601 22:59:15.103828  sv_algorithm_assistance_LP4_1600 

  602 22:59:15.106965  ============ PULL DRAM RESETB DOWN ============

  603 22:59:15.110030  ========== PULL DRAM RESETB DOWN end =========

  604 22:59:15.116915  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  605 22:59:15.120101  =================================== 

  606 22:59:15.123389  LPDDR4 DRAM CONFIGURATION

  607 22:59:15.126983  =================================== 

  608 22:59:15.127596  EX_ROW_EN[0]    = 0x0

  609 22:59:15.130557  EX_ROW_EN[1]    = 0x0

  610 22:59:15.131177  LP4Y_EN      = 0x0

  611 22:59:15.133684  WORK_FSP     = 0x0

  612 22:59:15.134385  WL           = 0x2

  613 22:59:15.137185  RL           = 0x2

  614 22:59:15.137882  BL           = 0x2

  615 22:59:15.140185  RPST         = 0x0

  616 22:59:15.140896  RD_PRE       = 0x0

  617 22:59:15.143899  WR_PRE       = 0x1

  618 22:59:15.144487  WR_PST       = 0x0

  619 22:59:15.146933  DBI_WR       = 0x0

  620 22:59:15.147561  DBI_RD       = 0x0

  621 22:59:15.150358  OTF          = 0x1

  622 22:59:15.153369  =================================== 

  623 22:59:15.156932  =================================== 

  624 22:59:15.157607  ANA top config

  625 22:59:15.160468  =================================== 

  626 22:59:15.163260  DLL_ASYNC_EN            =  0

  627 22:59:15.167054  ALL_SLAVE_EN            =  1

  628 22:59:15.169922  NEW_RANK_MODE           =  1

  629 22:59:15.170262  DLL_IDLE_MODE           =  1

  630 22:59:15.173349  LP45_APHY_COMB_EN       =  1

  631 22:59:15.176452  TX_ODT_DIS              =  1

  632 22:59:15.180247  NEW_8X_MODE             =  1

  633 22:59:15.183326  =================================== 

  634 22:59:15.186888  =================================== 

  635 22:59:15.190046  data_rate                  = 1600

  636 22:59:15.190355  CKR                        = 1

  637 22:59:15.193195  DQ_P2S_RATIO               = 8

  638 22:59:15.196563  =================================== 

  639 22:59:15.200291  CA_P2S_RATIO               = 8

  640 22:59:15.203555  DQ_CA_OPEN                 = 0

  641 22:59:15.206397  DQ_SEMI_OPEN               = 0

  642 22:59:15.210285  CA_SEMI_OPEN               = 0

  643 22:59:15.210662  CA_FULL_RATE               = 0

  644 22:59:15.213330  DQ_CKDIV4_EN               = 1

  645 22:59:15.216451  CA_CKDIV4_EN               = 1

  646 22:59:15.219763  CA_PREDIV_EN               = 0

  647 22:59:15.223252  PH8_DLY                    = 0

  648 22:59:15.226764  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

  649 22:59:15.227072  DQ_AAMCK_DIV               = 4

  650 22:59:15.229747  CA_AAMCK_DIV               = 4

  651 22:59:15.233497  CA_ADMCK_DIV               = 4

  652 22:59:15.236480  DQ_TRACK_CA_EN             = 0

  653 22:59:15.239558  CA_PICK                    = 800

  654 22:59:15.243272  CA_MCKIO                   = 800

  655 22:59:15.243669  MCKIO_SEMI                 = 0

  656 22:59:15.246996  PLL_FREQ                   = 3068

  657 22:59:15.250052  DQ_UI_PI_RATIO             = 32

  658 22:59:15.253317  CA_UI_PI_RATIO             = 0

  659 22:59:15.256489  =================================== 

  660 22:59:15.259900  =================================== 

  661 22:59:15.262989  memory_type:LPDDR4         

  662 22:59:15.263492  GP_NUM     : 10       

  663 22:59:15.266668  SRAM_EN    : 1       

  664 22:59:15.269997  MD32_EN    : 0       

  665 22:59:15.272988  =================================== 

  666 22:59:15.273408  [ANA_INIT] >>>>>>>>>>>>>> 

  667 22:59:15.276553  <<<<<< [CONFIGURE PHASE]: ANA_TX

  668 22:59:15.279398  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

  669 22:59:15.283396  =================================== 

  670 22:59:15.286666  data_rate = 1600,PCW = 0X7600

  671 22:59:15.289629  =================================== 

  672 22:59:15.293171  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

  673 22:59:15.299947  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

  674 22:59:15.303052  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

  675 22:59:15.309711  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

  676 22:59:15.312846  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

  677 22:59:15.316661  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

  678 22:59:15.317130  [ANA_INIT] flow start 

  679 22:59:15.319617  [ANA_INIT] PLL >>>>>>>> 

  680 22:59:15.322645  [ANA_INIT] PLL <<<<<<<< 

  681 22:59:15.326409  [ANA_INIT] MIDPI >>>>>>>> 

  682 22:59:15.326863  [ANA_INIT] MIDPI <<<<<<<< 

  683 22:59:15.329984  [ANA_INIT] DLL >>>>>>>> 

  684 22:59:15.330393  [ANA_INIT] flow end 

  685 22:59:15.336782  ============ LP4 DIFF to SE enter ============

  686 22:59:15.339854  ============ LP4 DIFF to SE exit  ============

  687 22:59:15.342786  [ANA_INIT] <<<<<<<<<<<<< 

  688 22:59:15.346449  [Flow] Enable top DCM control >>>>> 

  689 22:59:15.349945  [Flow] Enable top DCM control <<<<< 

  690 22:59:15.350488  Enable DLL master slave shuffle 

  691 22:59:15.356396  ============================================================== 

  692 22:59:15.359818  Gating Mode config

  693 22:59:15.363040  ============================================================== 

  694 22:59:15.366365  Config description: 

  695 22:59:15.376209  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

  696 22:59:15.382730  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

  697 22:59:15.386478  SELPH_MODE            0: By rank         1: By Phase 

  698 22:59:15.393104  ============================================================== 

  699 22:59:15.396176  GAT_TRACK_EN                 =  1

  700 22:59:15.399924  RX_GATING_MODE               =  2

  701 22:59:15.402862  RX_GATING_TRACK_MODE         =  2

  702 22:59:15.406708  SELPH_MODE                   =  1

  703 22:59:15.407224  PICG_EARLY_EN                =  1

  704 22:59:15.409761  VALID_LAT_VALUE              =  1

  705 22:59:15.416374  ============================================================== 

  706 22:59:15.419384  Enter into Gating configuration >>>> 

  707 22:59:15.423011  Exit from Gating configuration <<<< 

  708 22:59:15.426197  Enter into  DVFS_PRE_config >>>>> 

  709 22:59:15.436103  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

  710 22:59:15.439680  Exit from  DVFS_PRE_config <<<<< 

  711 22:59:15.442878  Enter into PICG configuration >>>> 

  712 22:59:15.446324  Exit from PICG configuration <<<< 

  713 22:59:15.449306  [RX_INPUT] configuration >>>>> 

  714 22:59:15.452955  [RX_INPUT] configuration <<<<< 

  715 22:59:15.455912  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

  716 22:59:15.463569  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

  717 22:59:15.470941  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

  718 22:59:15.474416  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

  719 22:59:15.481934  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

  720 22:59:15.489024  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

  721 22:59:15.492830  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

  722 22:59:15.495981  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

  723 22:59:15.499679  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

  724 22:59:15.503135  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

  725 22:59:15.507009  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

  726 22:59:15.514575  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  727 22:59:15.515014  =================================== 

  728 22:59:15.518089  LPDDR4 DRAM CONFIGURATION

  729 22:59:15.521130  =================================== 

  730 22:59:15.525045  EX_ROW_EN[0]    = 0x0

  731 22:59:15.525457  EX_ROW_EN[1]    = 0x0

  732 22:59:15.528748  LP4Y_EN      = 0x0

  733 22:59:15.529292  WORK_FSP     = 0x0

  734 22:59:15.531839  WL           = 0x2

  735 22:59:15.532253  RL           = 0x2

  736 22:59:15.535519  BL           = 0x2

  737 22:59:15.535931  RPST         = 0x0

  738 22:59:15.536425  RD_PRE       = 0x0

  739 22:59:15.539753  WR_PRE       = 0x1

  740 22:59:15.540202  WR_PST       = 0x0

  741 22:59:15.543436  DBI_WR       = 0x0

  742 22:59:15.543983  DBI_RD       = 0x0

  743 22:59:15.546935  OTF          = 0x1

  744 22:59:15.550564  =================================== 

  745 22:59:15.554926  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

  746 22:59:15.558025  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

  747 22:59:15.562033  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  748 22:59:15.565548  =================================== 

  749 22:59:15.568930  LPDDR4 DRAM CONFIGURATION

  750 22:59:15.572454  =================================== 

  751 22:59:15.573225  EX_ROW_EN[0]    = 0x10

  752 22:59:15.575995  EX_ROW_EN[1]    = 0x0

  753 22:59:15.576549  LP4Y_EN      = 0x0

  754 22:59:15.580023  WORK_FSP     = 0x0

  755 22:59:15.580691  WL           = 0x2

  756 22:59:15.583505  RL           = 0x2

  757 22:59:15.584163  BL           = 0x2

  758 22:59:15.584682  RPST         = 0x0

  759 22:59:15.587756  RD_PRE       = 0x0

  760 22:59:15.588388  WR_PRE       = 0x1

  761 22:59:15.591149  WR_PST       = 0x0

  762 22:59:15.591630  DBI_WR       = 0x0

  763 22:59:15.594929  DBI_RD       = 0x0

  764 22:59:15.595589  OTF          = 0x1

  765 22:59:15.597986  =================================== 

  766 22:59:15.604747  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

  767 22:59:15.609016  nWR fixed to 40

  768 22:59:15.609411  [ModeRegInit_LP4] CH0 RK0

  769 22:59:15.612691  [ModeRegInit_LP4] CH0 RK1

  770 22:59:15.616386  [ModeRegInit_LP4] CH1 RK0

  771 22:59:15.616869  [ModeRegInit_LP4] CH1 RK1

  772 22:59:15.620106  match AC timing 13

  773 22:59:15.623757  dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1

  774 22:59:15.627457  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

  775 22:59:15.633799  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

  776 22:59:15.637489  [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17

  777 22:59:15.640500  [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)

  778 22:59:15.643899  [EMI DOE] emi_dcm 0

  779 22:59:15.647090  [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600

  780 22:59:15.647516  ==

  781 22:59:15.650917  Dram Type= 6, Freq= 0, CH_0, rank 0

  782 22:59:15.653586  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  783 22:59:15.657984  ==

  784 22:59:15.661179  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

  785 22:59:15.667574  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

  786 22:59:15.676303  [CA 0] Center 37 (7~68) winsize 62

  787 22:59:15.679271  [CA 1] Center 37 (6~68) winsize 63

  788 22:59:15.682913  [CA 2] Center 34 (4~65) winsize 62

  789 22:59:15.685831  [CA 3] Center 34 (4~65) winsize 62

  790 22:59:15.689364  [CA 4] Center 33 (3~64) winsize 62

  791 22:59:15.692926  [CA 5] Center 33 (3~64) winsize 62

  792 22:59:15.693478  

  793 22:59:15.696547  [CmdBusTrainingLP45] Vref(ca) range 1: 34

  794 22:59:15.696985  

  795 22:59:15.699589  [CATrainingPosCal] consider 1 rank data

  796 22:59:15.703304  u2DelayCellTimex100 = 270/100 ps

  797 22:59:15.706237  CA0 delay=37 (7~68),Diff = 4 PI (28 cell)

  798 22:59:15.709632  CA1 delay=37 (6~68),Diff = 4 PI (28 cell)

  799 22:59:15.712711  CA2 delay=34 (4~65),Diff = 1 PI (7 cell)

  800 22:59:15.719627  CA3 delay=34 (4~65),Diff = 1 PI (7 cell)

  801 22:59:15.723357  CA4 delay=33 (3~64),Diff = 0 PI (0 cell)

  802 22:59:15.726444  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

  803 22:59:15.726916  

  804 22:59:15.729628  CA PerBit enable=1, Macro0, CA PI delay=33

  805 22:59:15.730029  

  806 22:59:15.732654  [CBTSetCACLKResult] CA Dly = 33

  807 22:59:15.733080  CS Dly: 7 (0~38)

  808 22:59:15.733402  ==

  809 22:59:15.736265  Dram Type= 6, Freq= 0, CH_0, rank 1

  810 22:59:15.742524  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  811 22:59:15.742988  ==

  812 22:59:15.746039  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

  813 22:59:15.752566  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

  814 22:59:15.762283  [CA 0] Center 37 (6~68) winsize 63

  815 22:59:15.765386  [CA 1] Center 37 (7~68) winsize 62

  816 22:59:15.768989  [CA 2] Center 34 (4~65) winsize 62

  817 22:59:15.771953  [CA 3] Center 34 (4~65) winsize 62

  818 22:59:15.775436  [CA 4] Center 33 (3~64) winsize 62

  819 22:59:15.778524  [CA 5] Center 33 (3~64) winsize 62

  820 22:59:15.779167  

  821 22:59:15.781945  [CmdBusTrainingLP45] Vref(ca) range 1: 34

  822 22:59:15.782348  

  823 22:59:15.785766  [CATrainingPosCal] consider 2 rank data

  824 22:59:15.788467  u2DelayCellTimex100 = 270/100 ps

  825 22:59:15.792120  CA0 delay=37 (7~68),Diff = 4 PI (28 cell)

  826 22:59:15.798740  CA1 delay=37 (7~68),Diff = 4 PI (28 cell)

  827 22:59:15.802030  CA2 delay=34 (4~65),Diff = 1 PI (7 cell)

  828 22:59:15.805873  CA3 delay=34 (4~65),Diff = 1 PI (7 cell)

  829 22:59:15.809428  CA4 delay=33 (3~64),Diff = 0 PI (0 cell)

  830 22:59:15.813094  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

  831 22:59:15.813512  

  832 22:59:15.816966  CA PerBit enable=1, Macro0, CA PI delay=33

  833 22:59:15.817378  

  834 22:59:15.817745  [CBTSetCACLKResult] CA Dly = 33

  835 22:59:15.820421  CS Dly: 7 (0~38)

  836 22:59:15.820857  

  837 22:59:15.824315  ----->DramcWriteLeveling(PI) begin...

  838 22:59:15.824772  ==

  839 22:59:15.828040  Dram Type= 6, Freq= 0, CH_0, rank 0

  840 22:59:15.831816  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  841 22:59:15.832399  ==

  842 22:59:15.834838  Write leveling (Byte 0): 31 => 31

  843 22:59:15.838058  Write leveling (Byte 1): 30 => 30

  844 22:59:15.841858  DramcWriteLeveling(PI) end<-----

  845 22:59:15.842408  

  846 22:59:15.842897  ==

  847 22:59:15.845008  Dram Type= 6, Freq= 0, CH_0, rank 0

  848 22:59:15.848450  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  849 22:59:15.849007  ==

  850 22:59:15.851493  [Gating] SW mode calibration

  851 22:59:15.858246  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

  852 22:59:15.864746  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

  853 22:59:15.868193   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

  854 22:59:15.871323   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)

  855 22:59:15.877860   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

  856 22:59:15.881537   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  857 22:59:15.884616   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  858 22:59:15.891638   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  859 22:59:15.894432   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  860 22:59:15.898064   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  861 22:59:15.904631   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  862 22:59:15.907796   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  863 22:59:15.911396   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  864 22:59:15.918111   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  865 22:59:15.921330   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  866 22:59:15.924295   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  867 22:59:15.931110   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  868 22:59:15.934235   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  869 22:59:15.937995   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  870 22:59:15.944124   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)

  871 22:59:15.947913   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)

  872 22:59:15.951011   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  873 22:59:15.954506   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  874 22:59:15.961117   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  875 22:59:15.964172   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  876 22:59:15.967830   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  877 22:59:15.974365   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  878 22:59:15.977515   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  879 22:59:15.981118   0  9  8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)

  880 22:59:15.987502   0  9 12 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)

  881 22:59:15.990558   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  882 22:59:15.994024   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  883 22:59:16.000409   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  884 22:59:16.004016   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  885 22:59:16.007393   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  886 22:59:16.014281   0 10  4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)

  887 22:59:16.017361   0 10  8 | B1->B0 | 3434 2b2b | 0 0 | (0 0) (0 0)

  888 22:59:16.021018   0 10 12 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)

  889 22:59:16.027149   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  890 22:59:16.030790   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  891 22:59:16.033898   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  892 22:59:16.040740   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  893 22:59:16.044254   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  894 22:59:16.047258   0 11  4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)

  895 22:59:16.053702   0 11  8 | B1->B0 | 2727 4242 | 0 0 | (0 0) (0 0)

  896 22:59:16.057150   0 11 12 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)

  897 22:59:16.060827   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  898 22:59:16.066997   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  899 22:59:16.070650   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  900 22:59:16.073650   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  901 22:59:16.080147   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  902 22:59:16.083868   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  903 22:59:16.087185   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

  904 22:59:16.093936   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  905 22:59:16.097468   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  906 22:59:16.100475   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  907 22:59:16.103890   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  908 22:59:16.110292   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  909 22:59:16.114034   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  910 22:59:16.117099   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  911 22:59:16.124384   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  912 22:59:16.127905   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  913 22:59:16.131634   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  914 22:59:16.134699   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  915 22:59:16.142198   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  916 22:59:16.146519   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  917 22:59:16.149609   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  918 22:59:16.153496   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  919 22:59:16.157183   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

  920 22:59:16.160788   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  921 22:59:16.164366  Total UI for P1: 0, mck2ui 16

  922 22:59:16.168601  best dqsien dly found for B0: ( 0, 14,  8)

  923 22:59:16.172130  Total UI for P1: 0, mck2ui 16

  924 22:59:16.175691  best dqsien dly found for B1: ( 0, 14,  8)

  925 22:59:16.179317  best DQS0 dly(MCK, UI, PI) = (0, 14, 8)

  926 22:59:16.182913  best DQS1 dly(MCK, UI, PI) = (0, 14, 8)

  927 22:59:16.183330  

  928 22:59:16.186594  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)

  929 22:59:16.190192  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)

  930 22:59:16.193850  [Gating] SW calibration Done

  931 22:59:16.194259  ==

  932 22:59:16.196869  Dram Type= 6, Freq= 0, CH_0, rank 0

  933 22:59:16.200412  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  934 22:59:16.200883  ==

  935 22:59:16.203231  RX Vref Scan: 0

  936 22:59:16.203601  

  937 22:59:16.203993  RX Vref 0 -> 0, step: 1

  938 22:59:16.204368  

  939 22:59:16.207079  RX Delay -130 -> 252, step: 16

  940 22:59:16.210461  iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240

  941 22:59:16.217149  iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240

  942 22:59:16.220055  iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240

  943 22:59:16.223733  iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240

  944 22:59:16.226821  iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240

  945 22:59:16.229826  iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240

  946 22:59:16.237159  iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240

  947 22:59:16.241064  iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240

  948 22:59:16.244961  iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256

  949 22:59:16.248364  iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256

  950 22:59:16.252147  iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240

  951 22:59:16.255224  iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256

  952 22:59:16.259008  iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256

  953 22:59:16.262134  iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256

  954 22:59:16.269094  iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240

  955 22:59:16.272397  iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256

  956 22:59:16.272843  ==

  957 22:59:16.275680  Dram Type= 6, Freq= 0, CH_0, rank 0

  958 22:59:16.279218  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  959 22:59:16.279634  ==

  960 22:59:16.280143  DQS Delay:

  961 22:59:16.282111  DQS0 = 0, DQS1 = 0

  962 22:59:16.282507  DQM Delay:

  963 22:59:16.285837  DQM0 = 87, DQM1 = 71

  964 22:59:16.286343  DQ Delay:

  965 22:59:16.288675  DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85

  966 22:59:16.292391  DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101

  967 22:59:16.295208  DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61

  968 22:59:16.298826  DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77

  969 22:59:16.299260  

  970 22:59:16.299599  

  971 22:59:16.299896  ==

  972 22:59:16.302360  Dram Type= 6, Freq= 0, CH_0, rank 0

  973 22:59:16.309193  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  974 22:59:16.309638  ==

  975 22:59:16.309984  

  976 22:59:16.310291  

  977 22:59:16.310583  	TX Vref Scan disable

  978 22:59:16.312037   == TX Byte 0 ==

  979 22:59:16.315442  Update DQ  dly =581 (2 ,1, 37)  DQ  OEN =(1 ,6)

  980 22:59:16.321960  Update DQM dly =581 (2 ,1, 37)  DQM OEN =(1 ,6)

  981 22:59:16.322368   == TX Byte 1 ==

  982 22:59:16.325436  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

  983 22:59:16.332170  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

  984 22:59:16.332747  ==

  985 22:59:16.335321  Dram Type= 6, Freq= 0, CH_0, rank 0

  986 22:59:16.338762  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  987 22:59:16.339216  ==

  988 22:59:16.351092  TX Vref=22, minBit 8, minWin=27, winSum=442

  989 22:59:16.354663  TX Vref=24, minBit 5, minWin=27, winSum=446

  990 22:59:16.357813  TX Vref=26, minBit 8, minWin=27, winSum=444

  991 22:59:16.360957  TX Vref=28, minBit 8, minWin=27, winSum=446

  992 22:59:16.364577  TX Vref=30, minBit 8, minWin=27, winSum=443

  993 22:59:16.367627  TX Vref=32, minBit 9, minWin=26, winSum=439

  994 22:59:16.374256  [TxChooseVref] Worse bit 5, Min win 27, Win sum 446, Final Vref 24

  995 22:59:16.374806  

  996 22:59:16.377885  Final TX Range 1 Vref 24

  997 22:59:16.378286  

  998 22:59:16.378597  ==

  999 22:59:16.380818  Dram Type= 6, Freq= 0, CH_0, rank 0

 1000 22:59:16.384285  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1001 22:59:16.384766  ==

 1002 22:59:16.385140  

 1003 22:59:16.387962  

 1004 22:59:16.388356  	TX Vref Scan disable

 1005 22:59:16.391148   == TX Byte 0 ==

 1006 22:59:16.394025  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1007 22:59:16.397596  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1008 22:59:16.401179   == TX Byte 1 ==

 1009 22:59:16.404196  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1010 22:59:16.407775  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1011 22:59:16.410820  

 1012 22:59:16.411476  [DATLAT]

 1013 22:59:16.412134  Freq=800, CH0 RK0

 1014 22:59:16.412703  

 1015 22:59:16.414319  DATLAT Default: 0xa

 1016 22:59:16.414741  0, 0xFFFF, sum = 0

 1017 22:59:16.417947  1, 0xFFFF, sum = 0

 1018 22:59:16.418532  2, 0xFFFF, sum = 0

 1019 22:59:16.420729  3, 0xFFFF, sum = 0

 1020 22:59:16.421184  4, 0xFFFF, sum = 0

 1021 22:59:16.424184  5, 0xFFFF, sum = 0

 1022 22:59:16.427857  6, 0xFFFF, sum = 0

 1023 22:59:16.428406  7, 0xFFFF, sum = 0

 1024 22:59:16.430643  8, 0xFFFF, sum = 0

 1025 22:59:16.431177  9, 0x0, sum = 1

 1026 22:59:16.431597  10, 0x0, sum = 2

 1027 22:59:16.434471  11, 0x0, sum = 3

 1028 22:59:16.434926  12, 0x0, sum = 4

 1029 22:59:16.437391  best_step = 10

 1030 22:59:16.437915  

 1031 22:59:16.438289  ==

 1032 22:59:16.440564  Dram Type= 6, Freq= 0, CH_0, rank 0

 1033 22:59:16.444118  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1034 22:59:16.444722  ==

 1035 22:59:16.448082  RX Vref Scan: 1

 1036 22:59:16.448580  

 1037 22:59:16.449021  Set Vref Range= 32 -> 127

 1038 22:59:16.450975  

 1039 22:59:16.451448  RX Vref 32 -> 127, step: 1

 1040 22:59:16.451803  

 1041 22:59:16.454052  RX Delay -111 -> 252, step: 8

 1042 22:59:16.454482  

 1043 22:59:16.457810  Set Vref, RX VrefLevel [Byte0]: 32

 1044 22:59:16.460752                           [Byte1]: 32

 1045 22:59:16.461249  

 1046 22:59:16.464447  Set Vref, RX VrefLevel [Byte0]: 33

 1047 22:59:16.467684                           [Byte1]: 33

 1048 22:59:16.471753  

 1049 22:59:16.472274  Set Vref, RX VrefLevel [Byte0]: 34

 1050 22:59:16.474872                           [Byte1]: 34

 1051 22:59:16.479105  

 1052 22:59:16.479748  Set Vref, RX VrefLevel [Byte0]: 35

 1053 22:59:16.482650                           [Byte1]: 35

 1054 22:59:16.486831  

 1055 22:59:16.487311  Set Vref, RX VrefLevel [Byte0]: 36

 1056 22:59:16.489843                           [Byte1]: 36

 1057 22:59:16.494568  

 1058 22:59:16.495108  Set Vref, RX VrefLevel [Byte0]: 37

 1059 22:59:16.498010                           [Byte1]: 37

 1060 22:59:16.502448  

 1061 22:59:16.502847  Set Vref, RX VrefLevel [Byte0]: 38

 1062 22:59:16.505363                           [Byte1]: 38

 1063 22:59:16.509450  

 1064 22:59:16.509835  Set Vref, RX VrefLevel [Byte0]: 39

 1065 22:59:16.513237                           [Byte1]: 39

 1066 22:59:16.517416  

 1067 22:59:16.517803  Set Vref, RX VrefLevel [Byte0]: 40

 1068 22:59:16.520904                           [Byte1]: 40

 1069 22:59:16.524914  

 1070 22:59:16.525302  Set Vref, RX VrefLevel [Byte0]: 41

 1071 22:59:16.528492                           [Byte1]: 41

 1072 22:59:16.532758  

 1073 22:59:16.533145  Set Vref, RX VrefLevel [Byte0]: 42

 1074 22:59:16.536195                           [Byte1]: 42

 1075 22:59:16.540013  

 1076 22:59:16.540561  Set Vref, RX VrefLevel [Byte0]: 43

 1077 22:59:16.543549                           [Byte1]: 43

 1078 22:59:16.547972  

 1079 22:59:16.548381  Set Vref, RX VrefLevel [Byte0]: 44

 1080 22:59:16.551067                           [Byte1]: 44

 1081 22:59:16.555846  

 1082 22:59:16.556273  Set Vref, RX VrefLevel [Byte0]: 45

 1083 22:59:16.558970                           [Byte1]: 45

 1084 22:59:16.563334  

 1085 22:59:16.563846  Set Vref, RX VrefLevel [Byte0]: 46

 1086 22:59:16.566402                           [Byte1]: 46

 1087 22:59:16.570861  

 1088 22:59:16.571268  Set Vref, RX VrefLevel [Byte0]: 47

 1089 22:59:16.573880                           [Byte1]: 47

 1090 22:59:16.578239  

 1091 22:59:16.578624  Set Vref, RX VrefLevel [Byte0]: 48

 1092 22:59:16.581753                           [Byte1]: 48

 1093 22:59:16.585814  

 1094 22:59:16.586430  Set Vref, RX VrefLevel [Byte0]: 49

 1095 22:59:16.589476                           [Byte1]: 49

 1096 22:59:16.593838  

 1097 22:59:16.594228  Set Vref, RX VrefLevel [Byte0]: 50

 1098 22:59:16.596784                           [Byte1]: 50

 1099 22:59:16.601557  

 1100 22:59:16.601943  Set Vref, RX VrefLevel [Byte0]: 51

 1101 22:59:16.604385                           [Byte1]: 51

 1102 22:59:16.609130  

 1103 22:59:16.609518  Set Vref, RX VrefLevel [Byte0]: 52

 1104 22:59:16.611992                           [Byte1]: 52

 1105 22:59:16.617018  

 1106 22:59:16.617402  Set Vref, RX VrefLevel [Byte0]: 53

 1107 22:59:16.619964                           [Byte1]: 53

 1108 22:59:16.624622  

 1109 22:59:16.624985  Set Vref, RX VrefLevel [Byte0]: 54

 1110 22:59:16.627472                           [Byte1]: 54

 1111 22:59:16.631887  

 1112 22:59:16.632303  Set Vref, RX VrefLevel [Byte0]: 55

 1113 22:59:16.635546                           [Byte1]: 55

 1114 22:59:16.639601  

 1115 22:59:16.639990  Set Vref, RX VrefLevel [Byte0]: 56

 1116 22:59:16.643143                           [Byte1]: 56

 1117 22:59:16.647361  

 1118 22:59:16.647904  Set Vref, RX VrefLevel [Byte0]: 57

 1119 22:59:16.650425                           [Byte1]: 57

 1120 22:59:16.654721  

 1121 22:59:16.655288  Set Vref, RX VrefLevel [Byte0]: 58

 1122 22:59:16.658336                           [Byte1]: 58

 1123 22:59:16.662630  

 1124 22:59:16.663186  Set Vref, RX VrefLevel [Byte0]: 59

 1125 22:59:16.665957                           [Byte1]: 59

 1126 22:59:16.670191  

 1127 22:59:16.673851  Set Vref, RX VrefLevel [Byte0]: 60

 1128 22:59:16.674429                           [Byte1]: 60

 1129 22:59:16.678090  

 1130 22:59:16.678639  Set Vref, RX VrefLevel [Byte0]: 61

 1131 22:59:16.681352                           [Byte1]: 61

 1132 22:59:16.685680  

 1133 22:59:16.686292  Set Vref, RX VrefLevel [Byte0]: 62

 1134 22:59:16.689289                           [Byte1]: 62

 1135 22:59:16.693118  

 1136 22:59:16.693594  Set Vref, RX VrefLevel [Byte0]: 63

 1137 22:59:16.697026                           [Byte1]: 63

 1138 22:59:16.701421  

 1139 22:59:16.701905  Set Vref, RX VrefLevel [Byte0]: 64

 1140 22:59:16.704295                           [Byte1]: 64

 1141 22:59:16.708582  

 1142 22:59:16.709153  Set Vref, RX VrefLevel [Byte0]: 65

 1143 22:59:16.712192                           [Byte1]: 65

 1144 22:59:16.716434  

 1145 22:59:16.716922  Set Vref, RX VrefLevel [Byte0]: 66

 1146 22:59:16.719949                           [Byte1]: 66

 1147 22:59:16.724150  

 1148 22:59:16.724578  Set Vref, RX VrefLevel [Byte0]: 67

 1149 22:59:16.727092                           [Byte1]: 67

 1150 22:59:16.731827  

 1151 22:59:16.732215  Set Vref, RX VrefLevel [Byte0]: 68

 1152 22:59:16.734634                           [Byte1]: 68

 1153 22:59:16.738749  

 1154 22:59:16.742104  Set Vref, RX VrefLevel [Byte0]: 69

 1155 22:59:16.742697                           [Byte1]: 69

 1156 22:59:16.746935  

 1157 22:59:16.747434  Set Vref, RX VrefLevel [Byte0]: 70

 1158 22:59:16.750179                           [Byte1]: 70

 1159 22:59:16.754556  

 1160 22:59:16.755081  Set Vref, RX VrefLevel [Byte0]: 71

 1161 22:59:16.757732                           [Byte1]: 71

 1162 22:59:16.762570  

 1163 22:59:16.763238  Set Vref, RX VrefLevel [Byte0]: 72

 1164 22:59:16.765544                           [Byte1]: 72

 1165 22:59:16.769850  

 1166 22:59:16.770483  Set Vref, RX VrefLevel [Byte0]: 73

 1167 22:59:16.773557                           [Byte1]: 73

 1168 22:59:16.777322  

 1169 22:59:16.777886  Set Vref, RX VrefLevel [Byte0]: 74

 1170 22:59:16.781084                           [Byte1]: 74

 1171 22:59:16.785422  

 1172 22:59:16.786018  Set Vref, RX VrefLevel [Byte0]: 75

 1173 22:59:16.788426                           [Byte1]: 75

 1174 22:59:16.792646  

 1175 22:59:16.793215  Set Vref, RX VrefLevel [Byte0]: 76

 1176 22:59:16.795616                           [Byte1]: 76

 1177 22:59:16.800500  

 1178 22:59:16.801031  Set Vref, RX VrefLevel [Byte0]: 77

 1179 22:59:16.803497                           [Byte1]: 77

 1180 22:59:16.808249  

 1181 22:59:16.808713  Set Vref, RX VrefLevel [Byte0]: 78

 1182 22:59:16.811397                           [Byte1]: 78

 1183 22:59:16.815732  

 1184 22:59:16.816122  Final RX Vref Byte 0 = 60 to rank0

 1185 22:59:16.819935  Final RX Vref Byte 1 = 50 to rank0

 1186 22:59:16.823332  Final RX Vref Byte 0 = 60 to rank1

 1187 22:59:16.827017  Final RX Vref Byte 1 = 50 to rank1==

 1188 22:59:16.830560  Dram Type= 6, Freq= 0, CH_0, rank 0

 1189 22:59:16.834074  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1190 22:59:16.834580  ==

 1191 22:59:16.834903  DQS Delay:

 1192 22:59:16.837961  DQS0 = 0, DQS1 = 0

 1193 22:59:16.838354  DQM Delay:

 1194 22:59:16.841629  DQM0 = 85, DQM1 = 75

 1195 22:59:16.842018  DQ Delay:

 1196 22:59:16.845129  DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =80

 1197 22:59:16.848877  DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96

 1198 22:59:16.849391  DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =68

 1199 22:59:16.852883  DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84

 1200 22:59:16.853275  

 1201 22:59:16.853584  

 1202 22:59:16.863807  [DQSOSCAuto] RK0, (LSB)MR18= 0x4729, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 392 ps

 1203 22:59:16.864327  CH0 RK0: MR19=606, MR18=4729

 1204 22:59:16.870658  CH0_RK0: MR19=0x606, MR18=0x4729, DQSOSC=392, MR23=63, INC=96, DEC=64

 1205 22:59:16.871053  

 1206 22:59:16.874421  ----->DramcWriteLeveling(PI) begin...

 1207 22:59:16.874823  ==

 1208 22:59:16.878077  Dram Type= 6, Freq= 0, CH_0, rank 1

 1209 22:59:16.881653  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1210 22:59:16.882084  ==

 1211 22:59:16.885437  Write leveling (Byte 0): 32 => 32

 1212 22:59:16.889009  Write leveling (Byte 1): 33 => 33

 1213 22:59:16.892570  DramcWriteLeveling(PI) end<-----

 1214 22:59:16.892997  

 1215 22:59:16.893423  ==

 1216 22:59:16.896350  Dram Type= 6, Freq= 0, CH_0, rank 1

 1217 22:59:16.900187  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1218 22:59:16.900634  ==

 1219 22:59:16.903642  [Gating] SW mode calibration

 1220 22:59:16.911088  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1221 22:59:16.914196  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1222 22:59:16.918462   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1223 22:59:16.921972   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)

 1224 22:59:16.966292   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)

 1225 22:59:16.966727   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 1226 22:59:16.967062   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1227 22:59:16.967760   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1228 22:59:16.968151   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1229 22:59:16.968462   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1230 22:59:16.968881   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1231 22:59:16.969197   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1232 22:59:16.969659   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1233 22:59:16.969977   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1234 22:59:17.009980   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1235 22:59:17.010526   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1236 22:59:17.011344   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1237 22:59:17.011826   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1238 22:59:17.012283   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1239 22:59:17.012729   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1240 22:59:17.013058   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)

 1241 22:59:17.013355   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 1242 22:59:17.013645   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1243 22:59:17.013929   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1244 22:59:17.054097   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1245 22:59:17.055125   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1246 22:59:17.055669   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1247 22:59:17.056096   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1248 22:59:17.056669   0  9  8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)

 1249 22:59:17.057007   0  9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)

 1250 22:59:17.057382   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1251 22:59:17.057692   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1252 22:59:17.057985   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1253 22:59:17.058276   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1254 22:59:17.098205   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1255 22:59:17.098790   0 10  4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)

 1256 22:59:17.099148   0 10  8 | B1->B0 | 3232 2525 | 1 1 | (0 0) (1 0)

 1257 22:59:17.099773   0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)

 1258 22:59:17.100111   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1259 22:59:17.100423   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1260 22:59:17.100767   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1261 22:59:17.101066   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1262 22:59:17.101381   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1263 22:59:17.101838   0 11  4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)

 1264 22:59:17.107128   0 11  8 | B1->B0 | 2f2f 3535 | 0 0 | (0 0) (0 0)

 1265 22:59:17.110691   0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)

 1266 22:59:17.113731   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1267 22:59:17.117424   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1268 22:59:17.121574   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1269 22:59:17.125225   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1270 22:59:17.128893   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1271 22:59:17.132965   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 1272 22:59:17.139688   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 1273 22:59:17.143200   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1274 22:59:17.146443   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1275 22:59:17.152981   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1276 22:59:17.156627   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1277 22:59:17.160107   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1278 22:59:17.166595   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1279 22:59:17.169611   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1280 22:59:17.172843   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1281 22:59:17.179478   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1282 22:59:17.182721   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1283 22:59:17.186181   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1284 22:59:17.192600   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1285 22:59:17.196043   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1286 22:59:17.199196   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1287 22:59:17.202966   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 1288 22:59:17.209773   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 1289 22:59:17.212909   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 1290 22:59:17.215759  Total UI for P1: 0, mck2ui 16

 1291 22:59:17.219314  best dqsien dly found for B0: ( 0, 14,  6)

 1292 22:59:17.222930   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1293 22:59:17.225992  Total UI for P1: 0, mck2ui 16

 1294 22:59:17.229618  best dqsien dly found for B1: ( 0, 14, 12)

 1295 22:59:17.232737  best DQS0 dly(MCK, UI, PI) = (0, 14, 6)

 1296 22:59:17.239305  best DQS1 dly(MCK, UI, PI) = (0, 14, 12)

 1297 22:59:17.239944  

 1298 22:59:17.242478  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)

 1299 22:59:17.245829  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)

 1300 22:59:17.249245  [Gating] SW calibration Done

 1301 22:59:17.249665  ==

 1302 22:59:17.252753  Dram Type= 6, Freq= 0, CH_0, rank 1

 1303 22:59:17.255762  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1304 22:59:17.256198  ==

 1305 22:59:17.256727  RX Vref Scan: 0

 1306 22:59:17.257051  

 1307 22:59:17.259109  RX Vref 0 -> 0, step: 1

 1308 22:59:17.259534  

 1309 22:59:17.262820  RX Delay -130 -> 252, step: 16

 1310 22:59:17.265677  iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240

 1311 22:59:17.269195  iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240

 1312 22:59:17.276169  iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240

 1313 22:59:17.279067  iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256

 1314 22:59:17.282772  iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240

 1315 22:59:17.285790  iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240

 1316 22:59:17.289012  iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256

 1317 22:59:17.295230  iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256

 1318 22:59:17.299021  iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240

 1319 22:59:17.302158  iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256

 1320 22:59:17.305868  iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256

 1321 22:59:17.312585  iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240

 1322 22:59:17.315439  iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240

 1323 22:59:17.318535  iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240

 1324 22:59:17.322280  iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240

 1325 22:59:17.325333  iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240

 1326 22:59:17.325888  ==

 1327 22:59:17.328973  Dram Type= 6, Freq= 0, CH_0, rank 1

 1328 22:59:17.335570  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1329 22:59:17.336022  ==

 1330 22:59:17.336399  DQS Delay:

 1331 22:59:17.338680  DQS0 = 0, DQS1 = 0

 1332 22:59:17.339129  DQM Delay:

 1333 22:59:17.342223  DQM0 = 84, DQM1 = 77

 1334 22:59:17.342664  DQ Delay:

 1335 22:59:17.345240  DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77

 1336 22:59:17.348943  DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93

 1337 22:59:17.351872  DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69

 1338 22:59:17.355481  DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85

 1339 22:59:17.356037  

 1340 22:59:17.356399  

 1341 22:59:17.356790  ==

 1342 22:59:17.358429  Dram Type= 6, Freq= 0, CH_0, rank 1

 1343 22:59:17.361820  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1344 22:59:17.362254  ==

 1345 22:59:17.362609  

 1346 22:59:17.362949  

 1347 22:59:17.365508  	TX Vref Scan disable

 1348 22:59:17.368351   == TX Byte 0 ==

 1349 22:59:17.372027  Update DQ  dly =583 (2 ,1, 39)  DQ  OEN =(1 ,6)

 1350 22:59:17.375482  Update DQM dly =583 (2 ,1, 39)  DQM OEN =(1 ,6)

 1351 22:59:17.378582   == TX Byte 1 ==

 1352 22:59:17.381816  Update DQ  dly =584 (2 ,1, 40)  DQ  OEN =(1 ,6)

 1353 22:59:17.384993  Update DQM dly =584 (2 ,1, 40)  DQM OEN =(1 ,6)

 1354 22:59:17.385426  ==

 1355 22:59:17.388707  Dram Type= 6, Freq= 0, CH_0, rank 1

 1356 22:59:17.391668  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1357 22:59:17.394630  ==

 1358 22:59:17.406293  TX Vref=22, minBit 8, minWin=27, winSum=445

 1359 22:59:17.409462  TX Vref=24, minBit 13, minWin=27, winSum=448

 1360 22:59:17.412617  TX Vref=26, minBit 8, minWin=27, winSum=449

 1361 22:59:17.416169  TX Vref=28, minBit 0, minWin=28, winSum=451

 1362 22:59:17.419266  TX Vref=30, minBit 10, minWin=27, winSum=448

 1363 22:59:17.426017  TX Vref=32, minBit 9, minWin=27, winSum=446

 1364 22:59:17.429278  [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 28

 1365 22:59:17.429827  

 1366 22:59:17.432301  Final TX Range 1 Vref 28

 1367 22:59:17.432791  

 1368 22:59:17.433112  ==

 1369 22:59:17.436137  Dram Type= 6, Freq= 0, CH_0, rank 1

 1370 22:59:17.439673  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1371 22:59:17.442717  ==

 1372 22:59:17.443125  

 1373 22:59:17.443444  

 1374 22:59:17.443743  	TX Vref Scan disable

 1375 22:59:17.446340   == TX Byte 0 ==

 1376 22:59:17.449273  Update DQ  dly =582 (2 ,1, 38)  DQ  OEN =(1 ,6)

 1377 22:59:17.456336  Update DQM dly =582 (2 ,1, 38)  DQM OEN =(1 ,6)

 1378 22:59:17.456851   == TX Byte 1 ==

 1379 22:59:17.459497  Update DQ  dly =583 (2 ,1, 39)  DQ  OEN =(1 ,6)

 1380 22:59:17.465954  Update DQM dly =583 (2 ,1, 39)  DQM OEN =(1 ,6)

 1381 22:59:17.466373  

 1382 22:59:17.466693  [DATLAT]

 1383 22:59:17.466993  Freq=800, CH0 RK1

 1384 22:59:17.467282  

 1385 22:59:17.469333  DATLAT Default: 0xa

 1386 22:59:17.469857  0, 0xFFFF, sum = 0

 1387 22:59:17.472899  1, 0xFFFF, sum = 0

 1388 22:59:17.473529  2, 0xFFFF, sum = 0

 1389 22:59:17.475799  3, 0xFFFF, sum = 0

 1390 22:59:17.479350  4, 0xFFFF, sum = 0

 1391 22:59:17.479771  5, 0xFFFF, sum = 0

 1392 22:59:17.482413  6, 0xFFFF, sum = 0

 1393 22:59:17.482832  7, 0xFFFF, sum = 0

 1394 22:59:17.486184  8, 0xFFFF, sum = 0

 1395 22:59:17.486605  9, 0x0, sum = 1

 1396 22:59:17.489123  10, 0x0, sum = 2

 1397 22:59:17.489547  11, 0x0, sum = 3

 1398 22:59:17.489878  12, 0x0, sum = 4

 1399 22:59:17.492324  best_step = 10

 1400 22:59:17.492817  

 1401 22:59:17.493144  ==

 1402 22:59:17.496097  Dram Type= 6, Freq= 0, CH_0, rank 1

 1403 22:59:17.498923  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1404 22:59:17.499309  ==

 1405 22:59:17.502798  RX Vref Scan: 0

 1406 22:59:17.503325  

 1407 22:59:17.505707  RX Vref 0 -> 0, step: 1

 1408 22:59:17.506121  

 1409 22:59:17.506452  RX Delay -111 -> 252, step: 8

 1410 22:59:17.513127  iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224

 1411 22:59:17.516143  iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232

 1412 22:59:17.519591  iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224

 1413 22:59:17.522540  iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232

 1414 22:59:17.526405  iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232

 1415 22:59:17.532930  iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232

 1416 22:59:17.535880  iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232

 1417 22:59:17.539055  iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232

 1418 22:59:17.542610  iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224

 1419 22:59:17.545730  iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232

 1420 22:59:17.552775  iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232

 1421 22:59:17.555792  iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232

 1422 22:59:17.559329  iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232

 1423 22:59:17.562329  iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232

 1424 22:59:17.568762  iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224

 1425 22:59:17.572613  iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232

 1426 22:59:17.573032  ==

 1427 22:59:17.576201  Dram Type= 6, Freq= 0, CH_0, rank 1

 1428 22:59:17.579078  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1429 22:59:17.579657  ==

 1430 22:59:17.582577  DQS Delay:

 1431 22:59:17.582998  DQS0 = 0, DQS1 = 0

 1432 22:59:17.583488  DQM Delay:

 1433 22:59:17.585759  DQM0 = 85, DQM1 = 76

 1434 22:59:17.586185  DQ Delay:

 1435 22:59:17.588743  DQ0 =80, DQ1 =92, DQ2 =80, DQ3 =84

 1436 22:59:17.592482  DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =92

 1437 22:59:17.595642  DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =68

 1438 22:59:17.599338  DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84

 1439 22:59:17.599896  

 1440 22:59:17.600371  

 1441 22:59:17.609363  [DQSOSCAuto] RK1, (LSB)MR18= 0x440a, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 392 ps

 1442 22:59:17.609912  CH0 RK1: MR19=606, MR18=440A

 1443 22:59:17.615468  CH0_RK1: MR19=0x606, MR18=0x440A, DQSOSC=392, MR23=63, INC=96, DEC=64

 1444 22:59:17.619031  [RxdqsGatingPostProcess] freq 800

 1445 22:59:17.625508  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 1446 22:59:17.629028  Pre-setting of DQS Precalculation

 1447 22:59:17.632618  [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10

 1448 22:59:17.633049  ==

 1449 22:59:17.635538  Dram Type= 6, Freq= 0, CH_1, rank 0

 1450 22:59:17.642170  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1451 22:59:17.642603  ==

 1452 22:59:17.645900  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 1453 22:59:17.652489  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

 1454 22:59:17.661101  [CA 0] Center 35 (5~66) winsize 62

 1455 22:59:17.664769  [CA 1] Center 36 (5~67) winsize 63

 1456 22:59:17.667740  [CA 2] Center 34 (4~64) winsize 61

 1457 22:59:17.671194  [CA 3] Center 34 (3~65) winsize 63

 1458 22:59:17.674820  [CA 4] Center 34 (4~65) winsize 62

 1459 22:59:17.677786  [CA 5] Center 33 (3~64) winsize 62

 1460 22:59:17.678219  

 1461 22:59:17.681283  [CmdBusTrainingLP45] Vref(ca) range 1: 30

 1462 22:59:17.681714  

 1463 22:59:17.684857  [CATrainingPosCal] consider 1 rank data

 1464 22:59:17.687519  u2DelayCellTimex100 = 270/100 ps

 1465 22:59:17.691220  CA0 delay=35 (5~66),Diff = 2 PI (14 cell)

 1466 22:59:17.694348  CA1 delay=36 (5~67),Diff = 3 PI (21 cell)

 1467 22:59:17.701251  CA2 delay=34 (4~64),Diff = 1 PI (7 cell)

 1468 22:59:17.704246  CA3 delay=34 (3~65),Diff = 1 PI (7 cell)

 1469 22:59:17.707483  CA4 delay=34 (4~65),Diff = 1 PI (7 cell)

 1470 22:59:17.711145  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 1471 22:59:17.711577  

 1472 22:59:17.714360  CA PerBit enable=1, Macro0, CA PI delay=33

 1473 22:59:17.714819  

 1474 22:59:17.717783  [CBTSetCACLKResult] CA Dly = 33

 1475 22:59:17.718213  CS Dly: 5 (0~36)

 1476 22:59:17.721153  ==

 1477 22:59:17.721583  Dram Type= 6, Freq= 0, CH_1, rank 1

 1478 22:59:17.727583  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1479 22:59:17.728014  ==

 1480 22:59:17.730796  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 1481 22:59:17.737634  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

 1482 22:59:17.747123  [CA 0] Center 36 (5~67) winsize 63

 1483 22:59:17.750857  [CA 1] Center 36 (6~67) winsize 62

 1484 22:59:17.753826  [CA 2] Center 34 (4~65) winsize 62

 1485 22:59:17.757475  [CA 3] Center 34 (3~65) winsize 63

 1486 22:59:17.760327  [CA 4] Center 34 (4~65) winsize 62

 1487 22:59:17.763922  [CA 5] Center 33 (3~64) winsize 62

 1488 22:59:17.764347  

 1489 22:59:17.767246  [CmdBusTrainingLP45] Vref(ca) range 1: 34

 1490 22:59:17.767670  

 1491 22:59:17.770744  [CATrainingPosCal] consider 2 rank data

 1492 22:59:17.773687  u2DelayCellTimex100 = 270/100 ps

 1493 22:59:17.777348  CA0 delay=35 (5~66),Diff = 2 PI (14 cell)

 1494 22:59:17.780845  CA1 delay=36 (6~67),Diff = 3 PI (21 cell)

 1495 22:59:17.787048  CA2 delay=34 (4~64),Diff = 1 PI (7 cell)

 1496 22:59:17.790619  CA3 delay=34 (3~65),Diff = 1 PI (7 cell)

 1497 22:59:17.794100  CA4 delay=34 (4~65),Diff = 1 PI (7 cell)

 1498 22:59:17.797228  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 1499 22:59:17.797730  

 1500 22:59:17.800229  CA PerBit enable=1, Macro0, CA PI delay=33

 1501 22:59:17.800720  

 1502 22:59:17.804130  [CBTSetCACLKResult] CA Dly = 33

 1503 22:59:17.804599  CS Dly: 6 (0~38)

 1504 22:59:17.804947  

 1505 22:59:17.807280  ----->DramcWriteLeveling(PI) begin...

 1506 22:59:17.810338  ==

 1507 22:59:17.814086  Dram Type= 6, Freq= 0, CH_1, rank 0

 1508 22:59:17.817190  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1509 22:59:17.817661  ==

 1510 22:59:17.820000  Write leveling (Byte 0): 28 => 28

 1511 22:59:17.823799  Write leveling (Byte 1): 31 => 31

 1512 22:59:17.826832  DramcWriteLeveling(PI) end<-----

 1513 22:59:17.827262  

 1514 22:59:17.827601  ==

 1515 22:59:17.830088  Dram Type= 6, Freq= 0, CH_1, rank 0

 1516 22:59:17.833680  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1517 22:59:17.834114  ==

 1518 22:59:17.836838  [Gating] SW mode calibration

 1519 22:59:17.843500  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1520 22:59:17.850136  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1521 22:59:17.853236   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1522 22:59:17.856887   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1523 22:59:17.863515   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1524 22:59:17.866794   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1525 22:59:17.869746   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1526 22:59:17.876540   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1527 22:59:17.879682   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1528 22:59:17.883247   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1529 22:59:17.889740   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1530 22:59:17.893252   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1531 22:59:17.896323   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1532 22:59:17.903057   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1533 22:59:17.906185   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1534 22:59:17.909673   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1535 22:59:17.916229   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1536 22:59:17.919280   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1537 22:59:17.922874   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1538 22:59:17.929666   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)

 1539 22:59:17.932608   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)

 1540 22:59:17.935576   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1541 22:59:17.942575   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1542 22:59:17.946149   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1543 22:59:17.949287   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1544 22:59:17.952847   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1545 22:59:17.959123   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1546 22:59:17.962602   0  9  4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)

 1547 22:59:17.965679   0  9  8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)

 1548 22:59:17.972361   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1549 22:59:17.975750   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1550 22:59:17.979068   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1551 22:59:17.985813   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1552 22:59:17.988808   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1553 22:59:17.992240   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1554 22:59:17.998676   0 10  4 | B1->B0 | 3333 3232 | 0 0 | (0 0) (0 0)

 1555 22:59:18.002221   0 10  8 | B1->B0 | 2d2d 2424 | 0 0 | (0 1) (1 1)

 1556 22:59:18.005433   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1557 22:59:18.012093   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1558 22:59:18.015634   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1559 22:59:18.018784   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1560 22:59:18.025517   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1561 22:59:18.028472   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1562 22:59:18.032203   0 11  4 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)

 1563 22:59:18.038571   0 11  8 | B1->B0 | 3c3c 4343 | 0 0 | (0 0) (0 0)

 1564 22:59:18.042318   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1565 22:59:18.045389   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1566 22:59:18.051994   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1567 22:59:18.055206   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1568 22:59:18.058649   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1569 22:59:18.065284   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 1570 22:59:18.068935   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 1571 22:59:18.071546   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 1572 22:59:18.078536   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1573 22:59:18.082041   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1574 22:59:18.084984   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1575 22:59:18.092088   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1576 22:59:18.095015   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1577 22:59:18.098496   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1578 22:59:18.105050   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1579 22:59:18.108601   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1580 22:59:18.111598   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1581 22:59:18.118523   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1582 22:59:18.121700   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1583 22:59:18.125442   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1584 22:59:18.128300   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1585 22:59:18.135127   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 1586 22:59:18.138269   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 1587 22:59:18.141858   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 1588 22:59:18.145056  Total UI for P1: 0, mck2ui 16

 1589 22:59:18.148122  best dqsien dly found for B0: ( 0, 14,  2)

 1590 22:59:18.154779   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1591 22:59:18.158478  Total UI for P1: 0, mck2ui 16

 1592 22:59:18.161420  best dqsien dly found for B1: ( 0, 14,  6)

 1593 22:59:18.165039  best DQS0 dly(MCK, UI, PI) = (0, 14, 2)

 1594 22:59:18.167941  best DQS1 dly(MCK, UI, PI) = (0, 14, 6)

 1595 22:59:18.168498  

 1596 22:59:18.171634  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)

 1597 22:59:18.175164  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)

 1598 22:59:18.178255  [Gating] SW calibration Done

 1599 22:59:18.178768  ==

 1600 22:59:18.181365  Dram Type= 6, Freq= 0, CH_1, rank 0

 1601 22:59:18.184888  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1602 22:59:18.185450  ==

 1603 22:59:18.187838  RX Vref Scan: 0

 1604 22:59:18.188386  

 1605 22:59:18.188816  RX Vref 0 -> 0, step: 1

 1606 22:59:18.189138  

 1607 22:59:18.191433  RX Delay -130 -> 252, step: 16

 1608 22:59:18.198430  iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240

 1609 22:59:18.201454  iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240

 1610 22:59:18.204942  iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240

 1611 22:59:18.207697  iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240

 1612 22:59:18.211370  iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240

 1613 22:59:18.218149  iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240

 1614 22:59:18.221281  iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240

 1615 22:59:18.224868  iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240

 1616 22:59:18.227910  iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240

 1617 22:59:18.231420  iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240

 1618 22:59:18.237680  iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256

 1619 22:59:18.240823  iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240

 1620 22:59:18.244465  iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256

 1621 22:59:18.247512  iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256

 1622 22:59:18.251189  iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240

 1623 22:59:18.258032  iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240

 1624 22:59:18.258475  ==

 1625 22:59:18.261071  Dram Type= 6, Freq= 0, CH_1, rank 0

 1626 22:59:18.264120  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1627 22:59:18.264626  ==

 1628 22:59:18.264978  DQS Delay:

 1629 22:59:18.267401  DQS0 = 0, DQS1 = 0

 1630 22:59:18.267855  DQM Delay:

 1631 22:59:18.271130  DQM0 = 87, DQM1 = 76

 1632 22:59:18.271581  DQ Delay:

 1633 22:59:18.274107  DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85

 1634 22:59:18.277418  DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85

 1635 22:59:18.280432  DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69

 1636 22:59:18.284342  DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =85

 1637 22:59:18.284816  

 1638 22:59:18.285156  

 1639 22:59:18.285468  ==

 1640 22:59:18.287846  Dram Type= 6, Freq= 0, CH_1, rank 0

 1641 22:59:18.290831  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1642 22:59:18.294264  ==

 1643 22:59:18.294710  

 1644 22:59:18.295069  

 1645 22:59:18.295392  	TX Vref Scan disable

 1646 22:59:18.297351   == TX Byte 0 ==

 1647 22:59:18.300715  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1648 22:59:18.303772  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1649 22:59:18.307424   == TX Byte 1 ==

 1650 22:59:18.310968  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1651 22:59:18.313871  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1652 22:59:18.317220  ==

 1653 22:59:18.320921  Dram Type= 6, Freq= 0, CH_1, rank 0

 1654 22:59:18.323763  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1655 22:59:18.324285  ==

 1656 22:59:18.336110  TX Vref=22, minBit 11, minWin=26, winSum=442

 1657 22:59:18.339782  TX Vref=24, minBit 8, minWin=27, winSum=445

 1658 22:59:18.342824  TX Vref=26, minBit 8, minWin=27, winSum=447

 1659 22:59:18.346328  TX Vref=28, minBit 9, minWin=27, winSum=450

 1660 22:59:18.349451  TX Vref=30, minBit 9, minWin=27, winSum=449

 1661 22:59:18.356383  TX Vref=32, minBit 9, minWin=27, winSum=448

 1662 22:59:18.359435  [TxChooseVref] Worse bit 9, Min win 27, Win sum 450, Final Vref 28

 1663 22:59:18.359891  

 1664 22:59:18.363158  Final TX Range 1 Vref 28

 1665 22:59:18.363593  

 1666 22:59:18.364019  ==

 1667 22:59:18.366238  Dram Type= 6, Freq= 0, CH_1, rank 0

 1668 22:59:18.369714  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1669 22:59:18.370150  ==

 1670 22:59:18.372602  

 1671 22:59:18.373133  

 1672 22:59:18.373475  	TX Vref Scan disable

 1673 22:59:18.376304   == TX Byte 0 ==

 1674 22:59:18.379826  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 1675 22:59:18.386441  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 1676 22:59:18.386863   == TX Byte 1 ==

 1677 22:59:18.389390  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1678 22:59:18.396065  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1679 22:59:18.396754  

 1680 22:59:18.397172  [DATLAT]

 1681 22:59:18.397530  Freq=800, CH1 RK0

 1682 22:59:18.397843  

 1683 22:59:18.399122  DATLAT Default: 0xa

 1684 22:59:18.399550  0, 0xFFFF, sum = 0

 1685 22:59:18.402775  1, 0xFFFF, sum = 0

 1686 22:59:18.405791  2, 0xFFFF, sum = 0

 1687 22:59:18.406243  3, 0xFFFF, sum = 0

 1688 22:59:18.409203  4, 0xFFFF, sum = 0

 1689 22:59:18.409618  5, 0xFFFF, sum = 0

 1690 22:59:18.412748  6, 0xFFFF, sum = 0

 1691 22:59:18.413200  7, 0xFFFF, sum = 0

 1692 22:59:18.416147  8, 0xFFFF, sum = 0

 1693 22:59:18.416623  9, 0x0, sum = 1

 1694 22:59:18.419151  10, 0x0, sum = 2

 1695 22:59:18.419715  11, 0x0, sum = 3

 1696 22:59:18.420351  12, 0x0, sum = 4

 1697 22:59:18.422751  best_step = 10

 1698 22:59:18.423175  

 1699 22:59:18.423508  ==

 1700 22:59:18.425800  Dram Type= 6, Freq= 0, CH_1, rank 0

 1701 22:59:18.429603  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1702 22:59:18.430034  ==

 1703 22:59:18.432640  RX Vref Scan: 1

 1704 22:59:18.433273  

 1705 22:59:18.436244  Set Vref Range= 32 -> 127

 1706 22:59:18.436709  

 1707 22:59:18.437229  RX Vref 32 -> 127, step: 1

 1708 22:59:18.437726  

 1709 22:59:18.439341  RX Delay -95 -> 252, step: 8

 1710 22:59:18.439767  

 1711 22:59:18.442419  Set Vref, RX VrefLevel [Byte0]: 32

 1712 22:59:18.446158                           [Byte1]: 32

 1713 22:59:18.446612  

 1714 22:59:18.449288  Set Vref, RX VrefLevel [Byte0]: 33

 1715 22:59:18.452292                           [Byte1]: 33

 1716 22:59:18.456617  

 1717 22:59:18.457044  Set Vref, RX VrefLevel [Byte0]: 34

 1718 22:59:18.459661                           [Byte1]: 34

 1719 22:59:18.464074  

 1720 22:59:18.464559  Set Vref, RX VrefLevel [Byte0]: 35

 1721 22:59:18.467796                           [Byte1]: 35

 1722 22:59:18.471696  

 1723 22:59:18.472120  Set Vref, RX VrefLevel [Byte0]: 36

 1724 22:59:18.475116                           [Byte1]: 36

 1725 22:59:18.479582  

 1726 22:59:18.480086  Set Vref, RX VrefLevel [Byte0]: 37

 1727 22:59:18.482626                           [Byte1]: 37

 1728 22:59:18.486757  

 1729 22:59:18.487206  Set Vref, RX VrefLevel [Byte0]: 38

 1730 22:59:18.490463                           [Byte1]: 38

 1731 22:59:18.494902  

 1732 22:59:18.495453  Set Vref, RX VrefLevel [Byte0]: 39

 1733 22:59:18.497977                           [Byte1]: 39

 1734 22:59:18.502168  

 1735 22:59:18.502596  Set Vref, RX VrefLevel [Byte0]: 40

 1736 22:59:18.505440                           [Byte1]: 40

 1737 22:59:18.509878  

 1738 22:59:18.510452  Set Vref, RX VrefLevel [Byte0]: 41

 1739 22:59:18.513282                           [Byte1]: 41

 1740 22:59:18.517327  

 1741 22:59:18.517773  Set Vref, RX VrefLevel [Byte0]: 42

 1742 22:59:18.520922                           [Byte1]: 42

 1743 22:59:18.525061  

 1744 22:59:18.525590  Set Vref, RX VrefLevel [Byte0]: 43

 1745 22:59:18.528150                           [Byte1]: 43

 1746 22:59:18.532437  

 1747 22:59:18.532602  Set Vref, RX VrefLevel [Byte0]: 44

 1748 22:59:18.535586                           [Byte1]: 44

 1749 22:59:18.539896  

 1750 22:59:18.539978  Set Vref, RX VrefLevel [Byte0]: 45

 1751 22:59:18.542945                           [Byte1]: 45

 1752 22:59:18.547350  

 1753 22:59:18.547433  Set Vref, RX VrefLevel [Byte0]: 46

 1754 22:59:18.550427                           [Byte1]: 46

 1755 22:59:18.554762  

 1756 22:59:18.554844  Set Vref, RX VrefLevel [Byte0]: 47

 1757 22:59:18.558344                           [Byte1]: 47

 1758 22:59:18.562696  

 1759 22:59:18.562778  Set Vref, RX VrefLevel [Byte0]: 48

 1760 22:59:18.565945                           [Byte1]: 48

 1761 22:59:18.570170  

 1762 22:59:18.570252  Set Vref, RX VrefLevel [Byte0]: 49

 1763 22:59:18.573871                           [Byte1]: 49

 1764 22:59:18.577933  

 1765 22:59:18.578033  Set Vref, RX VrefLevel [Byte0]: 50

 1766 22:59:18.580999                           [Byte1]: 50

 1767 22:59:18.585606  

 1768 22:59:18.585688  Set Vref, RX VrefLevel [Byte0]: 51

 1769 22:59:18.588775                           [Byte1]: 51

 1770 22:59:18.592922  

 1771 22:59:18.593013  Set Vref, RX VrefLevel [Byte0]: 52

 1772 22:59:18.596489                           [Byte1]: 52

 1773 22:59:18.600803  

 1774 22:59:18.600885  Set Vref, RX VrefLevel [Byte0]: 53

 1775 22:59:18.603908                           [Byte1]: 53

 1776 22:59:18.607893  

 1777 22:59:18.607975  Set Vref, RX VrefLevel [Byte0]: 54

 1778 22:59:18.611519                           [Byte1]: 54

 1779 22:59:18.616077  

 1780 22:59:18.616159  Set Vref, RX VrefLevel [Byte0]: 55

 1781 22:59:18.618966                           [Byte1]: 55

 1782 22:59:18.623083  

 1783 22:59:18.623169  Set Vref, RX VrefLevel [Byte0]: 56

 1784 22:59:18.626829                           [Byte1]: 56

 1785 22:59:18.630890  

 1786 22:59:18.630972  Set Vref, RX VrefLevel [Byte0]: 57

 1787 22:59:18.634068                           [Byte1]: 57

 1788 22:59:18.638757  

 1789 22:59:18.638839  Set Vref, RX VrefLevel [Byte0]: 58

 1790 22:59:18.641672                           [Byte1]: 58

 1791 22:59:18.646157  

 1792 22:59:18.646266  Set Vref, RX VrefLevel [Byte0]: 59

 1793 22:59:18.649306                           [Byte1]: 59

 1794 22:59:18.653677  

 1795 22:59:18.653759  Set Vref, RX VrefLevel [Byte0]: 60

 1796 22:59:18.657368                           [Byte1]: 60

 1797 22:59:18.661005  

 1798 22:59:18.661087  Set Vref, RX VrefLevel [Byte0]: 61

 1799 22:59:18.664649                           [Byte1]: 61

 1800 22:59:18.668968  

 1801 22:59:18.669051  Set Vref, RX VrefLevel [Byte0]: 62

 1802 22:59:18.672069                           [Byte1]: 62

 1803 22:59:18.676441  

 1804 22:59:18.676560  Set Vref, RX VrefLevel [Byte0]: 63

 1805 22:59:18.679576                           [Byte1]: 63

 1806 22:59:18.684305  

 1807 22:59:18.684387  Set Vref, RX VrefLevel [Byte0]: 64

 1808 22:59:18.687316                           [Byte1]: 64

 1809 22:59:18.691981  

 1810 22:59:18.692063  Set Vref, RX VrefLevel [Byte0]: 65

 1811 22:59:18.695197                           [Byte1]: 65

 1812 22:59:18.699448  

 1813 22:59:18.699545  Set Vref, RX VrefLevel [Byte0]: 66

 1814 22:59:18.702441                           [Byte1]: 66

 1815 22:59:18.706842  

 1816 22:59:18.706950  Set Vref, RX VrefLevel [Byte0]: 67

 1817 22:59:18.710388                           [Byte1]: 67

 1818 22:59:18.714459  

 1819 22:59:18.714567  Set Vref, RX VrefLevel [Byte0]: 68

 1820 22:59:18.717546                           [Byte1]: 68

 1821 22:59:18.721819  

 1822 22:59:18.721901  Set Vref, RX VrefLevel [Byte0]: 69

 1823 22:59:18.725301                           [Byte1]: 69

 1824 22:59:18.729596  

 1825 22:59:18.729680  Set Vref, RX VrefLevel [Byte0]: 70

 1826 22:59:18.733115                           [Byte1]: 70

 1827 22:59:18.737312  

 1828 22:59:18.737394  Set Vref, RX VrefLevel [Byte0]: 71

 1829 22:59:18.740446                           [Byte1]: 71

 1830 22:59:18.744696  

 1831 22:59:18.744779  Set Vref, RX VrefLevel [Byte0]: 72

 1832 22:59:18.748247                           [Byte1]: 72

 1833 22:59:18.752545  

 1834 22:59:18.752640  Set Vref, RX VrefLevel [Byte0]: 73

 1835 22:59:18.755788                           [Byte1]: 73

 1836 22:59:18.760058  

 1837 22:59:18.760140  Set Vref, RX VrefLevel [Byte0]: 74

 1838 22:59:18.763836                           [Byte1]: 74

 1839 22:59:18.767514  

 1840 22:59:18.767597  Set Vref, RX VrefLevel [Byte0]: 75

 1841 22:59:18.771169                           [Byte1]: 75

 1842 22:59:18.775581  

 1843 22:59:18.775663  Set Vref, RX VrefLevel [Byte0]: 76

 1844 22:59:18.778599                           [Byte1]: 76

 1845 22:59:18.782969  

 1846 22:59:18.783055  Set Vref, RX VrefLevel [Byte0]: 77

 1847 22:59:18.785987                           [Byte1]: 77

 1848 22:59:18.790750  

 1849 22:59:18.790832  Set Vref, RX VrefLevel [Byte0]: 78

 1850 22:59:18.793771                           [Byte1]: 78

 1851 22:59:18.798153  

 1852 22:59:18.798236  Set Vref, RX VrefLevel [Byte0]: 79

 1853 22:59:18.801203                           [Byte1]: 79

 1854 22:59:18.805904  

 1855 22:59:18.805990  Final RX Vref Byte 0 = 57 to rank0

 1856 22:59:18.809077  Final RX Vref Byte 1 = 65 to rank0

 1857 22:59:18.812227  Final RX Vref Byte 0 = 57 to rank1

 1858 22:59:18.815773  Final RX Vref Byte 1 = 65 to rank1==

 1859 22:59:18.819445  Dram Type= 6, Freq= 0, CH_1, rank 0

 1860 22:59:18.825689  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1861 22:59:18.825795  ==

 1862 22:59:18.825863  DQS Delay:

 1863 22:59:18.825925  DQS0 = 0, DQS1 = 0

 1864 22:59:18.828723  DQM Delay:

 1865 22:59:18.828812  DQM0 = 84, DQM1 = 77

 1866 22:59:18.832118  DQ Delay:

 1867 22:59:18.835562  DQ0 =88, DQ1 =80, DQ2 =76, DQ3 =84

 1868 22:59:18.839106  DQ4 =76, DQ5 =96, DQ6 =96, DQ7 =80

 1869 22:59:18.842327  DQ8 =64, DQ9 =68, DQ10 =80, DQ11 =68

 1870 22:59:18.845659  DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =88

 1871 22:59:18.845739  

 1872 22:59:18.845816  

 1873 22:59:18.851858  [DQSOSCAuto] RK0, (LSB)MR18= 0x321e, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps

 1874 22:59:18.855551  CH1 RK0: MR19=606, MR18=321E

 1875 22:59:18.862365  CH1_RK0: MR19=0x606, MR18=0x321E, DQSOSC=397, MR23=63, INC=93, DEC=62

 1876 22:59:18.862448  

 1877 22:59:18.864915  ----->DramcWriteLeveling(PI) begin...

 1878 22:59:18.864992  ==

 1879 22:59:18.868752  Dram Type= 6, Freq= 0, CH_1, rank 1

 1880 22:59:18.871608  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1881 22:59:18.871682  ==

 1882 22:59:18.875522  Write leveling (Byte 0): 26 => 26

 1883 22:59:18.878477  Write leveling (Byte 1): 30 => 30

 1884 22:59:18.881542  DramcWriteLeveling(PI) end<-----

 1885 22:59:18.881613  

 1886 22:59:18.881674  ==

 1887 22:59:18.885230  Dram Type= 6, Freq= 0, CH_1, rank 1

 1888 22:59:18.888384  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1889 22:59:18.888494  ==

 1890 22:59:18.891434  [Gating] SW mode calibration

 1891 22:59:18.898436  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1892 22:59:18.905057  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1893 22:59:18.908125   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1894 22:59:18.914978   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1895 22:59:18.918332   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1896 22:59:18.921916   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1897 22:59:18.928484   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1898 22:59:18.931448   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1899 22:59:18.935066   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1900 22:59:18.938017   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1901 22:59:18.945093   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1902 22:59:18.947923   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1903 22:59:18.951739   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1904 22:59:18.957805   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1905 22:59:18.960902   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1906 22:59:18.967702   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1907 22:59:18.971261   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1908 22:59:18.974870   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1909 22:59:18.980929   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1910 22:59:18.984458   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1911 22:59:18.987629   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1912 22:59:18.994377   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1913 22:59:18.997366   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1914 22:59:19.001041   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1915 22:59:19.004486   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1916 22:59:19.010658   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1917 22:59:19.014283   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1918 22:59:19.017526   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1919 22:59:19.024156   0  9  8 | B1->B0 | 2f2f 2c2c | 0 1 | (0 0) (0 0)

 1920 22:59:19.027113   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1921 22:59:19.030637   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1922 22:59:19.037006   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1923 22:59:19.040445   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1924 22:59:19.043937   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1925 22:59:19.050407   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1926 22:59:19.053592   0 10  4 | B1->B0 | 3131 3333 | 0 1 | (0 1) (0 0)

 1927 22:59:19.056568   0 10  8 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)

 1928 22:59:19.063424   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1929 22:59:19.066564   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1930 22:59:19.073435   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1931 22:59:19.076442   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1932 22:59:19.080027   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1933 22:59:19.083153   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1934 22:59:19.089846   0 11  4 | B1->B0 | 2e2e 2929 | 0 0 | (0 0) (0 0)

 1935 22:59:19.093473   0 11  8 | B1->B0 | 3b3b 3a3a | 1 0 | (0 0) (1 1)

 1936 22:59:19.096453   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1937 22:59:19.103264   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1938 22:59:19.106743   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1939 22:59:19.109707   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1940 22:59:19.116418   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1941 22:59:19.120043   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 1942 22:59:19.122664   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 1943 22:59:19.129149   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 1944 22:59:19.132812   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1945 22:59:19.136408   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1946 22:59:19.142480   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1947 22:59:19.145943   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1948 22:59:19.149493   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1949 22:59:19.156070   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1950 22:59:19.159674   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1951 22:59:19.162743   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1952 22:59:19.169572   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1953 22:59:19.172731   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1954 22:59:19.176343   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1955 22:59:19.182601   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1956 22:59:19.186466   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1957 22:59:19.189522   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1958 22:59:19.195620   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 1959 22:59:19.199336   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 1960 22:59:19.202286  Total UI for P1: 0, mck2ui 16

 1961 22:59:19.205966  best dqsien dly found for B1: ( 0, 14,  4)

 1962 22:59:19.208875   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1963 22:59:19.212390  Total UI for P1: 0, mck2ui 16

 1964 22:59:19.215875  best dqsien dly found for B0: ( 0, 14,  8)

 1965 22:59:19.219074  best DQS0 dly(MCK, UI, PI) = (0, 14, 8)

 1966 22:59:19.222696  best DQS1 dly(MCK, UI, PI) = (0, 14, 4)

 1967 22:59:19.222779  

 1968 22:59:19.225748  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)

 1969 22:59:19.232435  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1970 22:59:19.232539  [Gating] SW calibration Done

 1971 22:59:19.232621  ==

 1972 22:59:19.235304  Dram Type= 6, Freq= 0, CH_1, rank 1

 1973 22:59:19.242552  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1974 22:59:19.242635  ==

 1975 22:59:19.242700  RX Vref Scan: 0

 1976 22:59:19.242760  

 1977 22:59:19.245202  RX Vref 0 -> 0, step: 1

 1978 22:59:19.245284  

 1979 22:59:19.248639  RX Delay -130 -> 252, step: 16

 1980 22:59:19.252032  iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240

 1981 22:59:19.255001  iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240

 1982 22:59:19.261992  iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240

 1983 22:59:19.265028  iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240

 1984 22:59:19.268739  iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240

 1985 22:59:19.271784  iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240

 1986 22:59:19.275558  iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256

 1987 22:59:19.278653  iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240

 1988 22:59:19.285413  iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256

 1989 22:59:19.288425  iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240

 1990 22:59:19.292139  iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256

 1991 22:59:19.295334  iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240

 1992 22:59:19.298850  iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240

 1993 22:59:19.305530  iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240

 1994 22:59:19.308493  iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256

 1995 22:59:19.312272  iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240

 1996 22:59:19.312372  ==

 1997 22:59:19.315364  Dram Type= 6, Freq= 0, CH_1, rank 1

 1998 22:59:19.318809  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1999 22:59:19.321925  ==

 2000 22:59:19.322024  DQS Delay:

 2001 22:59:19.322114  DQS0 = 0, DQS1 = 0

 2002 22:59:19.324981  DQM Delay:

 2003 22:59:19.325052  DQM0 = 84, DQM1 = 76

 2004 22:59:19.328522  DQ Delay:

 2005 22:59:19.331723  DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85

 2006 22:59:19.331830  DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85

 2007 22:59:19.335393  DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69

 2008 22:59:19.341500  DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85

 2009 22:59:19.341581  

 2010 22:59:19.341645  

 2011 22:59:19.341725  ==

 2012 22:59:19.345102  Dram Type= 6, Freq= 0, CH_1, rank 1

 2013 22:59:19.348542  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2014 22:59:19.348625  ==

 2015 22:59:19.348689  

 2016 22:59:19.348748  

 2017 22:59:19.351556  	TX Vref Scan disable

 2018 22:59:19.351694   == TX Byte 0 ==

 2019 22:59:19.358412  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 2020 22:59:19.361371  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 2021 22:59:19.361453   == TX Byte 1 ==

 2022 22:59:19.368447  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 2023 22:59:19.371454  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 2024 22:59:19.371536  ==

 2025 22:59:19.374684  Dram Type= 6, Freq= 0, CH_1, rank 1

 2026 22:59:19.378376  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2027 22:59:19.378458  ==

 2028 22:59:19.392580  TX Vref=22, minBit 1, minWin=27, winSum=441

 2029 22:59:19.395549  TX Vref=24, minBit 1, minWin=27, winSum=445

 2030 22:59:19.399166  TX Vref=26, minBit 9, minWin=27, winSum=450

 2031 22:59:19.402237  TX Vref=28, minBit 8, minWin=27, winSum=453

 2032 22:59:19.405405  TX Vref=30, minBit 0, minWin=28, winSum=451

 2033 22:59:19.412139  TX Vref=32, minBit 5, minWin=27, winSum=447

 2034 22:59:19.415893  [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 30

 2035 22:59:19.415976  

 2036 22:59:19.418941  Final TX Range 1 Vref 30

 2037 22:59:19.419022  

 2038 22:59:19.419086  ==

 2039 22:59:19.421874  Dram Type= 6, Freq= 0, CH_1, rank 1

 2040 22:59:19.425072  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2041 22:59:19.428218  ==

 2042 22:59:19.428299  

 2043 22:59:19.428363  

 2044 22:59:19.428422  	TX Vref Scan disable

 2045 22:59:19.432447   == TX Byte 0 ==

 2046 22:59:19.435648  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 2047 22:59:19.442110  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 2048 22:59:19.442192   == TX Byte 1 ==

 2049 22:59:19.445811  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 2050 22:59:19.451814  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 2051 22:59:19.451897  

 2052 22:59:19.451960  [DATLAT]

 2053 22:59:19.452020  Freq=800, CH1 RK1

 2054 22:59:19.452077  

 2055 22:59:19.455297  DATLAT Default: 0xa

 2056 22:59:19.455378  0, 0xFFFF, sum = 0

 2057 22:59:19.458809  1, 0xFFFF, sum = 0

 2058 22:59:19.461722  2, 0xFFFF, sum = 0

 2059 22:59:19.461805  3, 0xFFFF, sum = 0

 2060 22:59:19.465317  4, 0xFFFF, sum = 0

 2061 22:59:19.465401  5, 0xFFFF, sum = 0

 2062 22:59:19.468611  6, 0xFFFF, sum = 0

 2063 22:59:19.468694  7, 0xFFFF, sum = 0

 2064 22:59:19.471928  8, 0xFFFF, sum = 0

 2065 22:59:19.472010  9, 0x0, sum = 1

 2066 22:59:19.474989  10, 0x0, sum = 2

 2067 22:59:19.475071  11, 0x0, sum = 3

 2068 22:59:19.475137  12, 0x0, sum = 4

 2069 22:59:19.478731  best_step = 10

 2070 22:59:19.478812  

 2071 22:59:19.478876  ==

 2072 22:59:19.481888  Dram Type= 6, Freq= 0, CH_1, rank 1

 2073 22:59:19.484971  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2074 22:59:19.485053  ==

 2075 22:59:19.488101  RX Vref Scan: 0

 2076 22:59:19.488214  

 2077 22:59:19.491866  RX Vref 0 -> 0, step: 1

 2078 22:59:19.491947  

 2079 22:59:19.492010  RX Delay -111 -> 252, step: 8

 2080 22:59:19.498641  iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232

 2081 22:59:19.502364  iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224

 2082 22:59:19.505450  iDelay=217, Bit 2, Center 72 (-47 ~ 192) 240

 2083 22:59:19.508610  iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232

 2084 22:59:19.515311  iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232

 2085 22:59:19.518480  iDelay=217, Bit 5, Center 92 (-23 ~ 208) 232

 2086 22:59:19.522308  iDelay=217, Bit 6, Center 96 (-23 ~ 216) 240

 2087 22:59:19.525107  iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240

 2088 22:59:19.528630  iDelay=217, Bit 8, Center 64 (-55 ~ 184) 240

 2089 22:59:19.532250  iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232

 2090 22:59:19.539005  iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240

 2091 22:59:19.542141  iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232

 2092 22:59:19.545467  iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232

 2093 22:59:19.548886  iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232

 2094 22:59:19.555376  iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232

 2095 22:59:19.559018  iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240

 2096 22:59:19.559135  ==

 2097 22:59:19.561916  Dram Type= 6, Freq= 0, CH_1, rank 1

 2098 22:59:19.564985  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2099 22:59:19.565146  ==

 2100 22:59:19.568452  DQS Delay:

 2101 22:59:19.568629  DQS0 = 0, DQS1 = 0

 2102 22:59:19.568740  DQM Delay:

 2103 22:59:19.572245  DQM0 = 85, DQM1 = 77

 2104 22:59:19.572443  DQ Delay:

 2105 22:59:19.575469  DQ0 =92, DQ1 =80, DQ2 =72, DQ3 =84

 2106 22:59:19.578475  DQ4 =84, DQ5 =92, DQ6 =96, DQ7 =80

 2107 22:59:19.582113  DQ8 =64, DQ9 =68, DQ10 =80, DQ11 =68

 2108 22:59:19.585202  DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88

 2109 22:59:19.585405  

 2110 22:59:19.585565  

 2111 22:59:19.595339  [DQSOSCAuto] RK1, (LSB)MR18= 0x1810, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps

 2112 22:59:19.598511  CH1 RK1: MR19=606, MR18=1810

 2113 22:59:19.601551  CH1_RK1: MR19=0x606, MR18=0x1810, DQSOSC=403, MR23=63, INC=90, DEC=60

 2114 22:59:19.605223  [RxdqsGatingPostProcess] freq 800

 2115 22:59:19.611879  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 2116 22:59:19.614847  Pre-setting of DQS Precalculation

 2117 22:59:19.618437  [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10

 2118 22:59:19.628470  sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4

 2119 22:59:19.635019  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 2120 22:59:19.635444  

 2121 22:59:19.635774  

 2122 22:59:19.638057  [Calibration Summary] 1600 Mbps

 2123 22:59:19.638478  CH 0, Rank 0

 2124 22:59:19.641656  SW Impedance     : PASS

 2125 22:59:19.642079  DUTY Scan        : NO K

 2126 22:59:19.644910  ZQ Calibration   : PASS

 2127 22:59:19.648397  Jitter Meter     : NO K

 2128 22:59:19.649083  CBT Training     : PASS

 2129 22:59:19.651291  Write leveling   : PASS

 2130 22:59:19.654843  RX DQS gating    : PASS

 2131 22:59:19.655269  RX DQ/DQS(RDDQC) : PASS

 2132 22:59:19.657770  TX DQ/DQS        : PASS

 2133 22:59:19.661212  RX DATLAT        : PASS

 2134 22:59:19.661643  RX DQ/DQS(Engine): PASS

 2135 22:59:19.664742  TX OE            : NO K

 2136 22:59:19.665169  All Pass.

 2137 22:59:19.665511  

 2138 22:59:19.668195  CH 0, Rank 1

 2139 22:59:19.668793  SW Impedance     : PASS

 2140 22:59:19.671037  DUTY Scan        : NO K

 2141 22:59:19.671460  ZQ Calibration   : PASS

 2142 22:59:19.674366  Jitter Meter     : NO K

 2143 22:59:19.678214  CBT Training     : PASS

 2144 22:59:19.678757  Write leveling   : PASS

 2145 22:59:19.681474  RX DQS gating    : PASS

 2146 22:59:19.684354  RX DQ/DQS(RDDQC) : PASS

 2147 22:59:19.684874  TX DQ/DQS        : PASS

 2148 22:59:19.688139  RX DATLAT        : PASS

 2149 22:59:19.691231  RX DQ/DQS(Engine): PASS

 2150 22:59:19.691892  TX OE            : NO K

 2151 22:59:19.694314  All Pass.

 2152 22:59:19.695142  

 2153 22:59:19.696050  CH 1, Rank 0

 2154 22:59:19.698024  SW Impedance     : PASS

 2155 22:59:19.698607  DUTY Scan        : NO K

 2156 22:59:19.701155  ZQ Calibration   : PASS

 2157 22:59:19.704679  Jitter Meter     : NO K

 2158 22:59:19.705415  CBT Training     : PASS

 2159 22:59:19.707845  Write leveling   : PASS

 2160 22:59:19.711397  RX DQS gating    : PASS

 2161 22:59:19.711817  RX DQ/DQS(RDDQC) : PASS

 2162 22:59:19.714418  TX DQ/DQS        : PASS

 2163 22:59:19.714905  RX DATLAT        : PASS

 2164 22:59:19.717999  RX DQ/DQS(Engine): PASS

 2165 22:59:19.721083  TX OE            : NO K

 2166 22:59:19.721725  All Pass.

 2167 22:59:19.722326  

 2168 22:59:19.724236  CH 1, Rank 1

 2169 22:59:19.724856  SW Impedance     : PASS

 2170 22:59:19.727472  DUTY Scan        : NO K

 2171 22:59:19.727999  ZQ Calibration   : PASS

 2172 22:59:19.731027  Jitter Meter     : NO K

 2173 22:59:19.734624  CBT Training     : PASS

 2174 22:59:19.735101  Write leveling   : PASS

 2175 22:59:19.737585  RX DQS gating    : PASS

 2176 22:59:19.740812  RX DQ/DQS(RDDQC) : PASS

 2177 22:59:19.741365  TX DQ/DQS        : PASS

 2178 22:59:19.744243  RX DATLAT        : PASS

 2179 22:59:19.747545  RX DQ/DQS(Engine): PASS

 2180 22:59:19.747962  TX OE            : NO K

 2181 22:59:19.751114  All Pass.

 2182 22:59:19.751530  

 2183 22:59:19.751858  DramC Write-DBI off

 2184 22:59:19.754135  	PER_BANK_REFRESH: Hybrid Mode

 2185 22:59:19.754553  TX_TRACKING: ON

 2186 22:59:19.757853  [GetDramInforAfterCalByMRR] Vendor 6.

 2187 22:59:19.764252  [GetDramInforAfterCalByMRR] Revision 606.

 2188 22:59:19.767759  [GetDramInforAfterCalByMRR] Revision 2 0.

 2189 22:59:19.768182  MR0 0x3b3b

 2190 22:59:19.768511  MR8 0x5151

 2191 22:59:19.770823  RK0, DieNum 2, Density 16Gb, RKsize 32Gb.

 2192 22:59:19.774482  

 2193 22:59:19.774901  MR0 0x3b3b

 2194 22:59:19.775290  MR8 0x5151

 2195 22:59:19.777208  RK1, DieNum 2, Density 16Gb, RKsize 32Gb.

 2196 22:59:19.777664  

 2197 22:59:19.787815  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0

 2198 22:59:19.790748  [FAST_K] Save calibration result to emmc

 2199 22:59:19.793934  [FAST_K] Save calibration result to emmc

 2200 22:59:19.797112  dram_init: config_dvfs: 1

 2201 22:59:19.800829  dramc_set_vcore_voltage set vcore to 662500

 2202 22:59:19.803960  Read voltage for 1200, 2

 2203 22:59:19.804383  Vio18 = 0

 2204 22:59:19.804769  Vcore = 662500

 2205 22:59:19.807544  Vdram = 0

 2206 22:59:19.807963  Vddq = 0

 2207 22:59:19.808294  Vmddr = 0

 2208 22:59:19.814027  [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0

 2209 22:59:19.817135  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 2210 22:59:19.820675  MEM_TYPE=3, freq_sel=15

 2211 22:59:19.823803  sv_algorithm_assistance_LP4_1600 

 2212 22:59:19.827700  ============ PULL DRAM RESETB DOWN ============

 2213 22:59:19.830722  ========== PULL DRAM RESETB DOWN end =========

 2214 22:59:19.837453  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2215 22:59:19.840393  =================================== 

 2216 22:59:19.844103  LPDDR4 DRAM CONFIGURATION

 2217 22:59:19.847095  =================================== 

 2218 22:59:19.847518  EX_ROW_EN[0]    = 0x0

 2219 22:59:19.850617  EX_ROW_EN[1]    = 0x0

 2220 22:59:19.851044  LP4Y_EN      = 0x0

 2221 22:59:19.853799  WORK_FSP     = 0x0

 2222 22:59:19.854236  WL           = 0x4

 2223 22:59:19.857174  RL           = 0x4

 2224 22:59:19.857700  BL           = 0x2

 2225 22:59:19.860319  RPST         = 0x0

 2226 22:59:19.860792  RD_PRE       = 0x0

 2227 22:59:19.863867  WR_PRE       = 0x1

 2228 22:59:19.864292  WR_PST       = 0x0

 2229 22:59:19.866853  DBI_WR       = 0x0

 2230 22:59:19.867277  DBI_RD       = 0x0

 2231 22:59:19.870436  OTF          = 0x1

 2232 22:59:19.873880  =================================== 

 2233 22:59:19.876991  =================================== 

 2234 22:59:19.877515  ANA top config

 2235 22:59:19.880199  =================================== 

 2236 22:59:19.883621  DLL_ASYNC_EN            =  0

 2237 22:59:19.887143  ALL_SLAVE_EN            =  0

 2238 22:59:19.890298  NEW_RANK_MODE           =  1

 2239 22:59:19.890727  DLL_IDLE_MODE           =  1

 2240 22:59:19.893343  LP45_APHY_COMB_EN       =  1

 2241 22:59:19.896921  TX_ODT_DIS              =  1

 2242 22:59:19.900032  NEW_8X_MODE             =  1

 2243 22:59:19.903514  =================================== 

 2244 22:59:19.906661  =================================== 

 2245 22:59:19.910316  data_rate                  = 2400

 2246 22:59:19.913325  CKR                        = 1

 2247 22:59:19.913778  DQ_P2S_RATIO               = 8

 2248 22:59:19.916607  =================================== 

 2249 22:59:19.919809  CA_P2S_RATIO               = 8

 2250 22:59:19.923408  DQ_CA_OPEN                 = 0

 2251 22:59:19.926527  DQ_SEMI_OPEN               = 0

 2252 22:59:19.930243  CA_SEMI_OPEN               = 0

 2253 22:59:19.930673  CA_FULL_RATE               = 0

 2254 22:59:19.933182  DQ_CKDIV4_EN               = 0

 2255 22:59:19.936293  CA_CKDIV4_EN               = 0

 2256 22:59:19.940088  CA_PREDIV_EN               = 0

 2257 22:59:19.943062  PH8_DLY                    = 17

 2258 22:59:19.946914  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 2259 22:59:19.947604  DQ_AAMCK_DIV               = 4

 2260 22:59:19.949829  CA_AAMCK_DIV               = 4

 2261 22:59:19.953438  CA_ADMCK_DIV               = 4

 2262 22:59:19.956310  DQ_TRACK_CA_EN             = 0

 2263 22:59:19.960234  CA_PICK                    = 1200

 2264 22:59:19.963214  CA_MCKIO                   = 1200

 2265 22:59:19.966805  MCKIO_SEMI                 = 0

 2266 22:59:19.969723  PLL_FREQ                   = 2366

 2267 22:59:19.970333  DQ_UI_PI_RATIO             = 32

 2268 22:59:19.973167  CA_UI_PI_RATIO             = 0

 2269 22:59:19.976300  =================================== 

 2270 22:59:19.979864  =================================== 

 2271 22:59:19.983309  memory_type:LPDDR4         

 2272 22:59:19.986286  GP_NUM     : 10       

 2273 22:59:19.986714  SRAM_EN    : 1       

 2274 22:59:19.989874  MD32_EN    : 0       

 2275 22:59:19.993276  =================================== 

 2276 22:59:19.993761  [ANA_INIT] >>>>>>>>>>>>>> 

 2277 22:59:19.996181  <<<<<< [CONFIGURE PHASE]: ANA_TX

 2278 22:59:19.999933  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 2279 22:59:20.002902  =================================== 

 2280 22:59:20.006743  data_rate = 2400,PCW = 0X5b00

 2281 22:59:20.009757  =================================== 

 2282 22:59:20.012866  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 2283 22:59:20.019403  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 2284 22:59:20.026217  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 2285 22:59:20.029281  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 2286 22:59:20.033007  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 2287 22:59:20.036088  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 2288 22:59:20.039611  [ANA_INIT] flow start 

 2289 22:59:20.040035  [ANA_INIT] PLL >>>>>>>> 

 2290 22:59:20.042674  [ANA_INIT] PLL <<<<<<<< 

 2291 22:59:20.045882  [ANA_INIT] MIDPI >>>>>>>> 

 2292 22:59:20.046465  [ANA_INIT] MIDPI <<<<<<<< 

 2293 22:59:20.049316  [ANA_INIT] DLL >>>>>>>> 

 2294 22:59:20.052473  [ANA_INIT] DLL <<<<<<<< 

 2295 22:59:20.052942  [ANA_INIT] flow end 

 2296 22:59:20.059252  ============ LP4 DIFF to SE enter ============

 2297 22:59:20.063010  ============ LP4 DIFF to SE exit  ============

 2298 22:59:20.066131  [ANA_INIT] <<<<<<<<<<<<< 

 2299 22:59:20.069706  [Flow] Enable top DCM control >>>>> 

 2300 22:59:20.072573  [Flow] Enable top DCM control <<<<< 

 2301 22:59:20.073151  Enable DLL master slave shuffle 

 2302 22:59:20.079572  ============================================================== 

 2303 22:59:20.082321  Gating Mode config

 2304 22:59:20.085881  ============================================================== 

 2305 22:59:20.088969  Config description: 

 2306 22:59:20.099490  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 2307 22:59:20.105692  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 2308 22:59:20.109130  SELPH_MODE            0: By rank         1: By Phase 

 2309 22:59:20.115711  ============================================================== 

 2310 22:59:20.118885  GAT_TRACK_EN                 =  1

 2311 22:59:20.122292  RX_GATING_MODE               =  2

 2312 22:59:20.125273  RX_GATING_TRACK_MODE         =  2

 2313 22:59:20.128882  SELPH_MODE                   =  1

 2314 22:59:20.129314  PICG_EARLY_EN                =  1

 2315 22:59:20.132373  VALID_LAT_VALUE              =  1

 2316 22:59:20.138883  ============================================================== 

 2317 22:59:20.142555  Enter into Gating configuration >>>> 

 2318 22:59:20.145660  Exit from Gating configuration <<<< 

 2319 22:59:20.148635  Enter into  DVFS_PRE_config >>>>> 

 2320 22:59:20.158858  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 2321 22:59:20.162440  Exit from  DVFS_PRE_config <<<<< 

 2322 22:59:20.165471  Enter into PICG configuration >>>> 

 2323 22:59:20.168510  Exit from PICG configuration <<<< 

 2324 22:59:20.172344  [RX_INPUT] configuration >>>>> 

 2325 22:59:20.175139  [RX_INPUT] configuration <<<<< 

 2326 22:59:20.178420  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 2327 22:59:20.185710  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 2328 22:59:20.192227  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 2329 22:59:20.198884  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 2330 22:59:20.205312  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 2331 22:59:20.208939  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 2332 22:59:20.215022  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 2333 22:59:20.218664  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 2334 22:59:20.221604  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 2335 22:59:20.225211  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 2336 22:59:20.231547  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 2337 22:59:20.235332  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2338 22:59:20.238291  =================================== 

 2339 22:59:20.242053  LPDDR4 DRAM CONFIGURATION

 2340 22:59:20.245063  =================================== 

 2341 22:59:20.245732  EX_ROW_EN[0]    = 0x0

 2342 22:59:20.248129  EX_ROW_EN[1]    = 0x0

 2343 22:59:20.248812  LP4Y_EN      = 0x0

 2344 22:59:20.251858  WORK_FSP     = 0x0

 2345 22:59:20.252295  WL           = 0x4

 2346 22:59:20.254884  RL           = 0x4

 2347 22:59:20.255318  BL           = 0x2

 2348 22:59:20.258501  RPST         = 0x0

 2349 22:59:20.258949  RD_PRE       = 0x0

 2350 22:59:20.261391  WR_PRE       = 0x1

 2351 22:59:20.265133  WR_PST       = 0x0

 2352 22:59:20.265579  DBI_WR       = 0x0

 2353 22:59:20.268107  DBI_RD       = 0x0

 2354 22:59:20.268758  OTF          = 0x1

 2355 22:59:20.271225  =================================== 

 2356 22:59:20.274792  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 2357 22:59:20.278417  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 2358 22:59:20.284921  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2359 22:59:20.287776  =================================== 

 2360 22:59:20.291294  LPDDR4 DRAM CONFIGURATION

 2361 22:59:20.294887  =================================== 

 2362 22:59:20.295299  EX_ROW_EN[0]    = 0x10

 2363 22:59:20.297786  EX_ROW_EN[1]    = 0x0

 2364 22:59:20.298302  LP4Y_EN      = 0x0

 2365 22:59:20.301219  WORK_FSP     = 0x0

 2366 22:59:20.301633  WL           = 0x4

 2367 22:59:20.304955  RL           = 0x4

 2368 22:59:20.305372  BL           = 0x2

 2369 22:59:20.307939  RPST         = 0x0

 2370 22:59:20.308384  RD_PRE       = 0x0

 2371 22:59:20.311395  WR_PRE       = 0x1

 2372 22:59:20.311941  WR_PST       = 0x0

 2373 22:59:20.314214  DBI_WR       = 0x0

 2374 22:59:20.317883  DBI_RD       = 0x0

 2375 22:59:20.318171  OTF          = 0x1

 2376 22:59:20.321180  =================================== 

 2377 22:59:20.327587  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 2378 22:59:20.327769  ==

 2379 22:59:20.331082  Dram Type= 6, Freq= 0, CH_0, rank 0

 2380 22:59:20.334600  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2381 22:59:20.334879  ==

 2382 22:59:20.337585  [Duty_Offset_Calibration]

 2383 22:59:20.337786  	B0:1	B1:-1	CA:0

 2384 22:59:20.340701  

 2385 22:59:20.340878  [DutyScan_Calibration_Flow] k_type=0

 2386 22:59:20.352243  

 2387 22:59:20.352483  ==CLK 0==

 2388 22:59:20.355281  Final CLK duty delay cell = 0

 2389 22:59:20.358465  [0] MAX Duty = 5125%(X100), DQS PI = 24

 2390 22:59:20.361884  [0] MIN Duty = 4907%(X100), DQS PI = 8

 2391 22:59:20.362144  [0] AVG Duty = 5016%(X100)

 2392 22:59:20.365025  

 2393 22:59:20.365259  CH0 CLK Duty spec in!! Max-Min= 218%

 2394 22:59:20.371785  [DutyScan_Calibration_Flow] ====Done====

 2395 22:59:20.372036  

 2396 22:59:20.375065  [DutyScan_Calibration_Flow] k_type=1

 2397 22:59:20.389598  

 2398 22:59:20.390037  ==DQS 0 ==

 2399 22:59:20.393359  Final DQS duty delay cell = -4

 2400 22:59:20.396270  [-4] MAX Duty = 5062%(X100), DQS PI = 16

 2401 22:59:20.399801  [-4] MIN Duty = 4875%(X100), DQS PI = 54

 2402 22:59:20.403260  [-4] AVG Duty = 4968%(X100)

 2403 22:59:20.403676  

 2404 22:59:20.404016  ==DQS 1 ==

 2405 22:59:20.406636  Final DQS duty delay cell = -4

 2406 22:59:20.409711  [-4] MAX Duty = 5000%(X100), DQS PI = 6

 2407 22:59:20.413041  [-4] MIN Duty = 4876%(X100), DQS PI = 24

 2408 22:59:20.416614  [-4] AVG Duty = 4938%(X100)

 2409 22:59:20.417056  

 2410 22:59:20.419674  CH0 DQS 0 Duty spec in!! Max-Min= 187%

 2411 22:59:20.420113  

 2412 22:59:20.422756  CH0 DQS 1 Duty spec in!! Max-Min= 124%

 2413 22:59:20.426338  [DutyScan_Calibration_Flow] ====Done====

 2414 22:59:20.426755  

 2415 22:59:20.429770  [DutyScan_Calibration_Flow] k_type=3

 2416 22:59:20.447633  

 2417 22:59:20.448049  ==DQM 0 ==

 2418 22:59:20.451404  Final DQM duty delay cell = 0

 2419 22:59:20.454336  [0] MAX Duty = 5031%(X100), DQS PI = 0

 2420 22:59:20.458042  [0] MIN Duty = 4875%(X100), DQS PI = 8

 2421 22:59:20.458459  [0] AVG Duty = 4953%(X100)

 2422 22:59:20.458786  

 2423 22:59:20.461074  ==DQM 1 ==

 2424 22:59:20.464716  Final DQM duty delay cell = 4

 2425 22:59:20.467496  [4] MAX Duty = 5187%(X100), DQS PI = 14

 2426 22:59:20.471196  [4] MIN Duty = 5000%(X100), DQS PI = 24

 2427 22:59:20.471649  [4] AVG Duty = 5093%(X100)

 2428 22:59:20.474189  

 2429 22:59:20.477623  CH0 DQM 0 Duty spec in!! Max-Min= 156%

 2430 22:59:20.478157  

 2431 22:59:20.480856  CH0 DQM 1 Duty spec in!! Max-Min= 187%

 2432 22:59:20.484361  [DutyScan_Calibration_Flow] ====Done====

 2433 22:59:20.484843  

 2434 22:59:20.487392  [DutyScan_Calibration_Flow] k_type=2

 2435 22:59:20.502719  

 2436 22:59:20.503148  ==DQ 0 ==

 2437 22:59:20.505856  Final DQ duty delay cell = -4

 2438 22:59:20.509329  [-4] MAX Duty = 5031%(X100), DQS PI = 22

 2439 22:59:20.512794  [-4] MIN Duty = 4907%(X100), DQS PI = 0

 2440 22:59:20.516250  [-4] AVG Duty = 4969%(X100)

 2441 22:59:20.516683  

 2442 22:59:20.517040  ==DQ 1 ==

 2443 22:59:20.519285  Final DQ duty delay cell = -4

 2444 22:59:20.522651  [-4] MAX Duty = 4969%(X100), DQS PI = 52

 2445 22:59:20.525923  [-4] MIN Duty = 4876%(X100), DQS PI = 14

 2446 22:59:20.529582  [-4] AVG Duty = 4922%(X100)

 2447 22:59:20.530153  

 2448 22:59:20.532322  CH0 DQ 0 Duty spec in!! Max-Min= 124%

 2449 22:59:20.532882  

 2450 22:59:20.536220  CH0 DQ 1 Duty spec in!! Max-Min= 93%

 2451 22:59:20.539359  [DutyScan_Calibration_Flow] ====Done====

 2452 22:59:20.539791  ==

 2453 22:59:20.542947  Dram Type= 6, Freq= 0, CH_1, rank 0

 2454 22:59:20.546299  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2455 22:59:20.546728  ==

 2456 22:59:20.549682  [Duty_Offset_Calibration]

 2457 22:59:20.550148  	B0:-1	B1:1	CA:2

 2458 22:59:20.550488  

 2459 22:59:20.552821  [DutyScan_Calibration_Flow] k_type=0

 2460 22:59:20.563125  

 2461 22:59:20.563585  ==CLK 0==

 2462 22:59:20.566414  Final CLK duty delay cell = 0

 2463 22:59:20.569954  [0] MAX Duty = 5156%(X100), DQS PI = 22

 2464 22:59:20.572916  [0] MIN Duty = 4969%(X100), DQS PI = 62

 2465 22:59:20.576564  [0] AVG Duty = 5062%(X100)

 2466 22:59:20.576987  

 2467 22:59:20.579554  CH1 CLK Duty spec in!! Max-Min= 187%

 2468 22:59:20.583166  [DutyScan_Calibration_Flow] ====Done====

 2469 22:59:20.583588  

 2470 22:59:20.586302  [DutyScan_Calibration_Flow] k_type=1

 2471 22:59:20.602900  

 2472 22:59:20.603328  ==DQS 0 ==

 2473 22:59:20.605813  Final DQS duty delay cell = 0

 2474 22:59:20.609202  [0] MAX Duty = 5156%(X100), DQS PI = 48

 2475 22:59:20.612067  [0] MIN Duty = 4907%(X100), DQS PI = 6

 2476 22:59:20.615574  [0] AVG Duty = 5031%(X100)

 2477 22:59:20.615998  

 2478 22:59:20.616396  ==DQS 1 ==

 2479 22:59:20.618631  Final DQS duty delay cell = 0

 2480 22:59:20.622174  [0] MAX Duty = 5094%(X100), DQS PI = 12

 2481 22:59:20.625309  [0] MIN Duty = 4969%(X100), DQS PI = 56

 2482 22:59:20.628848  [0] AVG Duty = 5031%(X100)

 2483 22:59:20.629273  

 2484 22:59:20.632038  CH1 DQS 0 Duty spec in!! Max-Min= 249%

 2485 22:59:20.632462  

 2486 22:59:20.635592  CH1 DQS 1 Duty spec in!! Max-Min= 125%

 2487 22:59:20.638815  [DutyScan_Calibration_Flow] ====Done====

 2488 22:59:20.639239  

 2489 22:59:20.642504  [DutyScan_Calibration_Flow] k_type=3

 2490 22:59:20.658344  

 2491 22:59:20.658899  ==DQM 0 ==

 2492 22:59:20.661590  Final DQM duty delay cell = -4

 2493 22:59:20.664812  [-4] MAX Duty = 5062%(X100), DQS PI = 34

 2494 22:59:20.668488  [-4] MIN Duty = 4876%(X100), DQS PI = 6

 2495 22:59:20.671460  [-4] AVG Duty = 4969%(X100)

 2496 22:59:20.671885  

 2497 22:59:20.672222  ==DQM 1 ==

 2498 22:59:20.675085  Final DQM duty delay cell = 0

 2499 22:59:20.677957  [0] MAX Duty = 5156%(X100), DQS PI = 4

 2500 22:59:20.681579  [0] MIN Duty = 5000%(X100), DQS PI = 30

 2501 22:59:20.684701  [0] AVG Duty = 5078%(X100)

 2502 22:59:20.685125  

 2503 22:59:20.688354  CH1 DQM 0 Duty spec in!! Max-Min= 186%

 2504 22:59:20.688927  

 2505 22:59:20.691143  CH1 DQM 1 Duty spec in!! Max-Min= 156%

 2506 22:59:20.694894  [DutyScan_Calibration_Flow] ====Done====

 2507 22:59:20.695409  

 2508 22:59:20.698093  [DutyScan_Calibration_Flow] k_type=2

 2509 22:59:20.714787  

 2510 22:59:20.715216  ==DQ 0 ==

 2511 22:59:20.718449  Final DQ duty delay cell = 0

 2512 22:59:20.721425  [0] MAX Duty = 5156%(X100), DQS PI = 28

 2513 22:59:20.724929  [0] MIN Duty = 4907%(X100), DQS PI = 6

 2514 22:59:20.725359  [0] AVG Duty = 5031%(X100)

 2515 22:59:20.725701  

 2516 22:59:20.728296  ==DQ 1 ==

 2517 22:59:20.731417  Final DQ duty delay cell = 0

 2518 22:59:20.735218  [0] MAX Duty = 5124%(X100), DQS PI = 10

 2519 22:59:20.738150  [0] MIN Duty = 4969%(X100), DQS PI = 0

 2520 22:59:20.738781  [0] AVG Duty = 5046%(X100)

 2521 22:59:20.739299  

 2522 22:59:20.741842  CH1 DQ 0 Duty spec in!! Max-Min= 249%

 2523 22:59:20.744987  

 2524 22:59:20.748015  CH1 DQ 1 Duty spec in!! Max-Min= 155%

 2525 22:59:20.751176  [DutyScan_Calibration_Flow] ====Done====

 2526 22:59:20.754979  nWR fixed to 30

 2527 22:59:20.755426  [ModeRegInit_LP4] CH0 RK0

 2528 22:59:20.758069  [ModeRegInit_LP4] CH0 RK1

 2529 22:59:20.761251  [ModeRegInit_LP4] CH1 RK0

 2530 22:59:20.761677  [ModeRegInit_LP4] CH1 RK1

 2531 22:59:20.764834  match AC timing 7

 2532 22:59:20.767933  dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1

 2533 22:59:20.771601  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 2534 22:59:20.777681  [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12

 2535 22:59:20.784200  [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25

 2536 22:59:20.788238  [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)

 2537 22:59:20.788714  ==

 2538 22:59:20.791005  Dram Type= 6, Freq= 0, CH_0, rank 0

 2539 22:59:20.794807  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2540 22:59:20.795237  ==

 2541 22:59:20.801574  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 2542 22:59:20.807490  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 2543 22:59:20.814583  [CA 0] Center 39 (9~70) winsize 62

 2544 22:59:20.818131  [CA 1] Center 39 (9~69) winsize 61

 2545 22:59:20.821073  [CA 2] Center 35 (5~66) winsize 62

 2546 22:59:20.824684  [CA 3] Center 35 (5~66) winsize 62

 2547 22:59:20.828282  [CA 4] Center 33 (4~63) winsize 60

 2548 22:59:20.831344  [CA 5] Center 33 (3~63) winsize 61

 2549 22:59:20.831784  

 2550 22:59:20.834844  [CmdBusTrainingLP45] Vref(ca) range 1: 33

 2551 22:59:20.835273  

 2552 22:59:20.838213  [CATrainingPosCal] consider 1 rank data

 2553 22:59:20.841136  u2DelayCellTimex100 = 270/100 ps

 2554 22:59:20.844462  CA0 delay=39 (9~70),Diff = 6 PI (28 cell)

 2555 22:59:20.851122  CA1 delay=39 (9~69),Diff = 6 PI (28 cell)

 2556 22:59:20.854221  CA2 delay=35 (5~66),Diff = 2 PI (9 cell)

 2557 22:59:20.858007  CA3 delay=35 (5~66),Diff = 2 PI (9 cell)

 2558 22:59:20.861098  CA4 delay=33 (4~63),Diff = 0 PI (0 cell)

 2559 22:59:20.864632  CA5 delay=33 (3~63),Diff = 0 PI (0 cell)

 2560 22:59:20.865163  

 2561 22:59:20.867956  CA PerBit enable=1, Macro0, CA PI delay=33

 2562 22:59:20.868356  

 2563 22:59:20.871770  [CBTSetCACLKResult] CA Dly = 33

 2564 22:59:20.872322  CS Dly: 8 (0~39)

 2565 22:59:20.874717  ==

 2566 22:59:20.875240  Dram Type= 6, Freq= 0, CH_0, rank 1

 2567 22:59:20.881096  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2568 22:59:20.881534  ==

 2569 22:59:20.884722  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 2570 22:59:20.891232  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 2571 22:59:20.900623  [CA 0] Center 39 (9~70) winsize 62

 2572 22:59:20.904324  [CA 1] Center 39 (9~70) winsize 62

 2573 22:59:20.907331  [CA 2] Center 35 (5~66) winsize 62

 2574 22:59:20.910626  [CA 3] Center 34 (4~65) winsize 62

 2575 22:59:20.913735  [CA 4] Center 33 (3~64) winsize 62

 2576 22:59:20.917211  [CA 5] Center 33 (3~63) winsize 61

 2577 22:59:20.917853  

 2578 22:59:20.920355  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 2579 22:59:20.920946  

 2580 22:59:20.923782  [CATrainingPosCal] consider 2 rank data

 2581 22:59:20.927383  u2DelayCellTimex100 = 270/100 ps

 2582 22:59:20.930265  CA0 delay=39 (9~70),Diff = 6 PI (28 cell)

 2583 22:59:20.937125  CA1 delay=39 (9~69),Diff = 6 PI (28 cell)

 2584 22:59:20.940116  CA2 delay=35 (5~66),Diff = 2 PI (9 cell)

 2585 22:59:20.943447  CA3 delay=35 (5~65),Diff = 2 PI (9 cell)

 2586 22:59:20.947178  CA4 delay=33 (4~63),Diff = 0 PI (0 cell)

 2587 22:59:20.950335  CA5 delay=33 (3~63),Diff = 0 PI (0 cell)

 2588 22:59:20.950765  

 2589 22:59:20.953400  CA PerBit enable=1, Macro0, CA PI delay=33

 2590 22:59:20.953850  

 2591 22:59:20.957049  [CBTSetCACLKResult] CA Dly = 33

 2592 22:59:20.957481  CS Dly: 9 (0~41)

 2593 22:59:20.960277  

 2594 22:59:20.963845  ----->DramcWriteLeveling(PI) begin...

 2595 22:59:20.964284  ==

 2596 22:59:20.966771  Dram Type= 6, Freq= 0, CH_0, rank 0

 2597 22:59:20.970600  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2598 22:59:20.971052  ==

 2599 22:59:20.973586  Write leveling (Byte 0): 33 => 33

 2600 22:59:20.976799  Write leveling (Byte 1): 29 => 29

 2601 22:59:20.980325  DramcWriteLeveling(PI) end<-----

 2602 22:59:20.980847  

 2603 22:59:20.981277  ==

 2604 22:59:20.983523  Dram Type= 6, Freq= 0, CH_0, rank 0

 2605 22:59:20.986610  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2606 22:59:20.987042  ==

 2607 22:59:20.990073  [Gating] SW mode calibration

 2608 22:59:20.996929  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 2609 22:59:21.003298  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 2610 22:59:21.006971   0 15  0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)

 2611 22:59:21.010026   0 15  4 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)

 2612 22:59:21.016719   0 15  8 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)

 2613 22:59:21.020257   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2614 22:59:21.023206   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2615 22:59:21.029773   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2616 22:59:21.033218   0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2617 22:59:21.036785   0 15 28 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)

 2618 22:59:21.043177   1  0  0 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)

 2619 22:59:21.046699   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2620 22:59:21.050103   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2621 22:59:21.053181   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2622 22:59:21.059487   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2623 22:59:21.063163   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2624 22:59:21.066187   1  0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2625 22:59:21.072951   1  0 28 | B1->B0 | 2323 3838 | 0 1 | (0 0) (0 0)

 2626 22:59:21.076169   1  1  0 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)

 2627 22:59:21.079819   1  1  4 | B1->B0 | 403f 4646 | 1 0 | (0 0) (0 0)

 2628 22:59:21.086027   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2629 22:59:21.089969   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2630 22:59:21.092781   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2631 22:59:21.100008   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2632 22:59:21.102823   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 2633 22:59:21.106632   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 2634 22:59:21.112780   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 2635 22:59:21.116296   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2636 22:59:21.119395   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2637 22:59:21.126035   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2638 22:59:21.129432   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2639 22:59:21.133050   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2640 22:59:21.139477   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2641 22:59:21.142693   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2642 22:59:21.146035   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2643 22:59:21.152657   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2644 22:59:21.156063   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2645 22:59:21.159135   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2646 22:59:21.166017   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2647 22:59:21.169600   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2648 22:59:21.172670   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 2649 22:59:21.176491   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)

 2650 22:59:21.179520  Total UI for P1: 0, mck2ui 16

 2651 22:59:21.182583  best dqsien dly found for B0: ( 1,  3, 24)

 2652 22:59:21.189438   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 2653 22:59:21.192621   1  4  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2654 22:59:21.196318  Total UI for P1: 0, mck2ui 16

 2655 22:59:21.199273  best dqsien dly found for B1: ( 1,  4,  0)

 2656 22:59:21.202896  best DQS0 dly(MCK, UI, PI) = (1, 3, 24)

 2657 22:59:21.206021  best DQS1 dly(MCK, UI, PI) = (1, 4, 0)

 2658 22:59:21.206503  

 2659 22:59:21.209379  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)

 2660 22:59:21.212656  best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)

 2661 22:59:21.216189  [Gating] SW calibration Done

 2662 22:59:21.216662  ==

 2663 22:59:21.219218  Dram Type= 6, Freq= 0, CH_0, rank 0

 2664 22:59:21.225914  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2665 22:59:21.226345  ==

 2666 22:59:21.226683  RX Vref Scan: 0

 2667 22:59:21.227071  

 2668 22:59:21.229119  RX Vref 0 -> 0, step: 1

 2669 22:59:21.229763  

 2670 22:59:21.232664  RX Delay -40 -> 252, step: 8

 2671 22:59:21.235443  iDelay=200, Bit 0, Center 119 (48 ~ 191) 144

 2672 22:59:21.238891  iDelay=200, Bit 1, Center 119 (48 ~ 191) 144

 2673 22:59:21.242401  iDelay=200, Bit 2, Center 115 (40 ~ 191) 152

 2674 22:59:21.248955  iDelay=200, Bit 3, Center 115 (40 ~ 191) 152

 2675 22:59:21.252234  iDelay=200, Bit 4, Center 123 (48 ~ 199) 152

 2676 22:59:21.255683  iDelay=200, Bit 5, Center 111 (40 ~ 183) 144

 2677 22:59:21.258753  iDelay=200, Bit 6, Center 127 (56 ~ 199) 144

 2678 22:59:21.262471  iDelay=200, Bit 7, Center 127 (56 ~ 199) 144

 2679 22:59:21.265509  iDelay=200, Bit 8, Center 95 (24 ~ 167) 144

 2680 22:59:21.272360  iDelay=200, Bit 9, Center 95 (24 ~ 167) 144

 2681 22:59:21.275502  iDelay=200, Bit 10, Center 111 (40 ~ 183) 144

 2682 22:59:21.278488  iDelay=200, Bit 11, Center 103 (32 ~ 175) 144

 2683 22:59:21.282229  iDelay=200, Bit 12, Center 111 (40 ~ 183) 144

 2684 22:59:21.285477  iDelay=200, Bit 13, Center 111 (40 ~ 183) 144

 2685 22:59:21.292161  iDelay=200, Bit 14, Center 119 (48 ~ 191) 144

 2686 22:59:21.295707  iDelay=200, Bit 15, Center 111 (40 ~ 183) 144

 2687 22:59:21.296133  ==

 2688 22:59:21.298835  Dram Type= 6, Freq= 0, CH_0, rank 0

 2689 22:59:21.301792  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2690 22:59:21.302214  ==

 2691 22:59:21.305386  DQS Delay:

 2692 22:59:21.305886  DQS0 = 0, DQS1 = 0

 2693 22:59:21.306226  DQM Delay:

 2694 22:59:21.308945  DQM0 = 119, DQM1 = 107

 2695 22:59:21.309464  DQ Delay:

 2696 22:59:21.312147  DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115

 2697 22:59:21.315209  DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127

 2698 22:59:21.321822  DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103

 2699 22:59:21.324884  DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111

 2700 22:59:21.325308  

 2701 22:59:21.325642  

 2702 22:59:21.325948  ==

 2703 22:59:21.328355  Dram Type= 6, Freq= 0, CH_0, rank 0

 2704 22:59:21.331686  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2705 22:59:21.332191  ==

 2706 22:59:21.332589  

 2707 22:59:21.332917  

 2708 22:59:21.335136  	TX Vref Scan disable

 2709 22:59:21.338703   == TX Byte 0 ==

 2710 22:59:21.341708  Update DQ  dly =851 (3 ,2, 19)  DQ  OEN =(2 ,7)

 2711 22:59:21.345118  Update DQM dly =851 (3 ,2, 19)  DQM OEN =(2 ,7)

 2712 22:59:21.347994   == TX Byte 1 ==

 2713 22:59:21.351616  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 2714 22:59:21.355107  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 2715 22:59:21.355577  ==

 2716 22:59:21.358687  Dram Type= 6, Freq= 0, CH_0, rank 0

 2717 22:59:21.361810  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2718 22:59:21.364786  ==

 2719 22:59:21.375214  TX Vref=22, minBit 5, minWin=25, winSum=417

 2720 22:59:21.378414  TX Vref=24, minBit 1, minWin=25, winSum=418

 2721 22:59:21.381295  TX Vref=26, minBit 1, minWin=25, winSum=427

 2722 22:59:21.385179  TX Vref=28, minBit 13, minWin=25, winSum=434

 2723 22:59:21.388192  TX Vref=30, minBit 5, minWin=26, winSum=432

 2724 22:59:21.394468  TX Vref=32, minBit 4, minWin=26, winSum=430

 2725 22:59:21.398103  [TxChooseVref] Worse bit 5, Min win 26, Win sum 432, Final Vref 30

 2726 22:59:21.398529  

 2727 22:59:21.401106  Final TX Range 1 Vref 30

 2728 22:59:21.401532  

 2729 22:59:21.401860  ==

 2730 22:59:21.404834  Dram Type= 6, Freq= 0, CH_0, rank 0

 2731 22:59:21.407700  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2732 22:59:21.411477  ==

 2733 22:59:21.411903  

 2734 22:59:21.412230  

 2735 22:59:21.412580  	TX Vref Scan disable

 2736 22:59:21.414779   == TX Byte 0 ==

 2737 22:59:21.417984  Update DQ  dly =851 (3 ,2, 19)  DQ  OEN =(2 ,7)

 2738 22:59:21.421463  Update DQM dly =851 (3 ,2, 19)  DQM OEN =(2 ,7)

 2739 22:59:21.424765   == TX Byte 1 ==

 2740 22:59:21.428167  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 2741 22:59:21.435062  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 2742 22:59:21.435625  

 2743 22:59:21.436570  [DATLAT]

 2744 22:59:21.437422  Freq=1200, CH0 RK0

 2745 22:59:21.438149  

 2746 22:59:21.439232  DATLAT Default: 0xd

 2747 22:59:21.439856  0, 0xFFFF, sum = 0

 2748 22:59:21.441589  1, 0xFFFF, sum = 0

 2749 22:59:21.442077  2, 0xFFFF, sum = 0

 2750 22:59:21.444771  3, 0xFFFF, sum = 0

 2751 22:59:21.448123  4, 0xFFFF, sum = 0

 2752 22:59:21.448732  5, 0xFFFF, sum = 0

 2753 22:59:21.451762  6, 0xFFFF, sum = 0

 2754 22:59:21.452190  7, 0xFFFF, sum = 0

 2755 22:59:21.454666  8, 0xFFFF, sum = 0

 2756 22:59:21.455111  9, 0xFFFF, sum = 0

 2757 22:59:21.458044  10, 0xFFFF, sum = 0

 2758 22:59:21.458641  11, 0xFFFF, sum = 0

 2759 22:59:21.460998  12, 0x0, sum = 1

 2760 22:59:21.461518  13, 0x0, sum = 2

 2761 22:59:21.464689  14, 0x0, sum = 3

 2762 22:59:21.465119  15, 0x0, sum = 4

 2763 22:59:21.467631  best_step = 13

 2764 22:59:21.468078  

 2765 22:59:21.468419  ==

 2766 22:59:21.471212  Dram Type= 6, Freq= 0, CH_0, rank 0

 2767 22:59:21.474337  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2768 22:59:21.474766  ==

 2769 22:59:21.475102  RX Vref Scan: 1

 2770 22:59:21.478097  

 2771 22:59:21.478518  Set Vref Range= 32 -> 127

 2772 22:59:21.478851  

 2773 22:59:21.481191  RX Vref 32 -> 127, step: 1

 2774 22:59:21.481615  

 2775 22:59:21.484159  RX Delay -21 -> 252, step: 4

 2776 22:59:21.484614  

 2777 22:59:21.488052  Set Vref, RX VrefLevel [Byte0]: 32

 2778 22:59:21.491150                           [Byte1]: 32

 2779 22:59:21.491575  

 2780 22:59:21.494217  Set Vref, RX VrefLevel [Byte0]: 33

 2781 22:59:21.497764                           [Byte1]: 33

 2782 22:59:21.501737  

 2783 22:59:21.502160  Set Vref, RX VrefLevel [Byte0]: 34

 2784 22:59:21.504620                           [Byte1]: 34

 2785 22:59:21.509428  

 2786 22:59:21.509951  Set Vref, RX VrefLevel [Byte0]: 35

 2787 22:59:21.512396                           [Byte1]: 35

 2788 22:59:21.517197  

 2789 22:59:21.517765  Set Vref, RX VrefLevel [Byte0]: 36

 2790 22:59:21.520868                           [Byte1]: 36

 2791 22:59:21.525218  

 2792 22:59:21.525671  Set Vref, RX VrefLevel [Byte0]: 37

 2793 22:59:21.528555                           [Byte1]: 37

 2794 22:59:21.533055  

 2795 22:59:21.533490  Set Vref, RX VrefLevel [Byte0]: 38

 2796 22:59:21.536649                           [Byte1]: 38

 2797 22:59:21.540922  

 2798 22:59:21.541401  Set Vref, RX VrefLevel [Byte0]: 39

 2799 22:59:21.544452                           [Byte1]: 39

 2800 22:59:21.548641  

 2801 22:59:21.549348  Set Vref, RX VrefLevel [Byte0]: 40

 2802 22:59:21.552033                           [Byte1]: 40

 2803 22:59:21.556816  

 2804 22:59:21.557251  Set Vref, RX VrefLevel [Byte0]: 41

 2805 22:59:21.560265                           [Byte1]: 41

 2806 22:59:21.564765  

 2807 22:59:21.565203  Set Vref, RX VrefLevel [Byte0]: 42

 2808 22:59:21.568349                           [Byte1]: 42

 2809 22:59:21.572444  

 2810 22:59:21.573003  Set Vref, RX VrefLevel [Byte0]: 43

 2811 22:59:21.576046                           [Byte1]: 43

 2812 22:59:21.580849  

 2813 22:59:21.581320  Set Vref, RX VrefLevel [Byte0]: 44

 2814 22:59:21.583941                           [Byte1]: 44

 2815 22:59:21.588396  

 2816 22:59:21.588867  Set Vref, RX VrefLevel [Byte0]: 45

 2817 22:59:21.592113                           [Byte1]: 45

 2818 22:59:21.596377  

 2819 22:59:21.596877  Set Vref, RX VrefLevel [Byte0]: 46

 2820 22:59:21.599387                           [Byte1]: 46

 2821 22:59:21.604450  

 2822 22:59:21.604915  Set Vref, RX VrefLevel [Byte0]: 47

 2823 22:59:21.607499                           [Byte1]: 47

 2824 22:59:21.612381  

 2825 22:59:21.612867  Set Vref, RX VrefLevel [Byte0]: 48

 2826 22:59:21.615500                           [Byte1]: 48

 2827 22:59:21.620234  

 2828 22:59:21.620750  Set Vref, RX VrefLevel [Byte0]: 49

 2829 22:59:21.623706                           [Byte1]: 49

 2830 22:59:21.627853  

 2831 22:59:21.628310  Set Vref, RX VrefLevel [Byte0]: 50

 2832 22:59:21.631380                           [Byte1]: 50

 2833 22:59:21.636271  

 2834 22:59:21.639110  Set Vref, RX VrefLevel [Byte0]: 51

 2835 22:59:21.639687                           [Byte1]: 51

 2836 22:59:21.643959  

 2837 22:59:21.644598  Set Vref, RX VrefLevel [Byte0]: 52

 2838 22:59:21.647557                           [Byte1]: 52

 2839 22:59:21.651800  

 2840 22:59:21.652237  Set Vref, RX VrefLevel [Byte0]: 53

 2841 22:59:21.655301                           [Byte1]: 53

 2842 22:59:21.659850  

 2843 22:59:21.660278  Set Vref, RX VrefLevel [Byte0]: 54

 2844 22:59:21.663226                           [Byte1]: 54

 2845 22:59:21.668055  

 2846 22:59:21.668629  Set Vref, RX VrefLevel [Byte0]: 55

 2847 22:59:21.671187                           [Byte1]: 55

 2848 22:59:21.675791  

 2849 22:59:21.676214  Set Vref, RX VrefLevel [Byte0]: 56

 2850 22:59:21.679424                           [Byte1]: 56

 2851 22:59:21.683793  

 2852 22:59:21.684420  Set Vref, RX VrefLevel [Byte0]: 57

 2853 22:59:21.686696                           [Byte1]: 57

 2854 22:59:21.691719  

 2855 22:59:21.692301  Set Vref, RX VrefLevel [Byte0]: 58

 2856 22:59:21.694862                           [Byte1]: 58

 2857 22:59:21.699690  

 2858 22:59:21.700172  Set Vref, RX VrefLevel [Byte0]: 59

 2859 22:59:21.702730                           [Byte1]: 59

 2860 22:59:21.707563  

 2861 22:59:21.708127  Set Vref, RX VrefLevel [Byte0]: 60

 2862 22:59:21.710707                           [Byte1]: 60

 2863 22:59:21.715180  

 2864 22:59:21.715735  Set Vref, RX VrefLevel [Byte0]: 61

 2865 22:59:21.718810                           [Byte1]: 61

 2866 22:59:21.723159  

 2867 22:59:21.723604  Set Vref, RX VrefLevel [Byte0]: 62

 2868 22:59:21.726358                           [Byte1]: 62

 2869 22:59:21.731170  

 2870 22:59:21.731627  Set Vref, RX VrefLevel [Byte0]: 63

 2871 22:59:21.734271                           [Byte1]: 63

 2872 22:59:21.739003  

 2873 22:59:21.739434  Set Vref, RX VrefLevel [Byte0]: 64

 2874 22:59:21.742550                           [Byte1]: 64

 2875 22:59:21.746857  

 2876 22:59:21.747282  Set Vref, RX VrefLevel [Byte0]: 65

 2877 22:59:21.750526                           [Byte1]: 65

 2878 22:59:21.754678  

 2879 22:59:21.755360  Set Vref, RX VrefLevel [Byte0]: 66

 2880 22:59:21.758072                           [Byte1]: 66

 2881 22:59:21.763013  

 2882 22:59:21.763718  Set Vref, RX VrefLevel [Byte0]: 67

 2883 22:59:21.766303                           [Byte1]: 67

 2884 22:59:21.770471  

 2885 22:59:21.771130  Set Vref, RX VrefLevel [Byte0]: 68

 2886 22:59:21.774104                           [Byte1]: 68

 2887 22:59:21.778882  

 2888 22:59:21.779531  Set Vref, RX VrefLevel [Byte0]: 69

 2889 22:59:21.781778                           [Byte1]: 69

 2890 22:59:21.786552  

 2891 22:59:21.787144  Set Vref, RX VrefLevel [Byte0]: 70

 2892 22:59:21.789732                           [Byte1]: 70

 2893 22:59:21.794578  

 2894 22:59:21.795183  Set Vref, RX VrefLevel [Byte0]: 71

 2895 22:59:21.797732                           [Byte1]: 71

 2896 22:59:21.802643  

 2897 22:59:21.803362  Set Vref, RX VrefLevel [Byte0]: 72

 2898 22:59:21.805710                           [Byte1]: 72

 2899 22:59:21.810727  

 2900 22:59:21.811336  Set Vref, RX VrefLevel [Byte0]: 73

 2901 22:59:21.813661                           [Byte1]: 73

 2902 22:59:21.818569  

 2903 22:59:21.818994  Set Vref, RX VrefLevel [Byte0]: 74

 2904 22:59:21.821522                           [Byte1]: 74

 2905 22:59:21.826418  

 2906 22:59:21.826845  Set Vref, RX VrefLevel [Byte0]: 75

 2907 22:59:21.829434                           [Byte1]: 75

 2908 22:59:21.834110  

 2909 22:59:21.837715  Final RX Vref Byte 0 = 60 to rank0

 2910 22:59:21.838149  Final RX Vref Byte 1 = 49 to rank0

 2911 22:59:21.840858  Final RX Vref Byte 0 = 60 to rank1

 2912 22:59:21.843945  Final RX Vref Byte 1 = 49 to rank1==

 2913 22:59:21.847415  Dram Type= 6, Freq= 0, CH_0, rank 0

 2914 22:59:21.854193  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2915 22:59:21.854696  ==

 2916 22:59:21.855221  DQS Delay:

 2917 22:59:21.857116  DQS0 = 0, DQS1 = 0

 2918 22:59:21.857566  DQM Delay:

 2919 22:59:21.857929  DQM0 = 119, DQM1 = 107

 2920 22:59:21.860814  DQ Delay:

 2921 22:59:21.864294  DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116

 2922 22:59:21.867205  DQ4 =118, DQ5 =114, DQ6 =126, DQ7 =126

 2923 22:59:21.870701  DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =100

 2924 22:59:21.873746  DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =116

 2925 22:59:21.874331  

 2926 22:59:21.874817  

 2927 22:59:21.883754  [DQSOSCAuto] RK0, (LSB)MR18= 0xef9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 404 ps

 2928 22:59:21.884190  CH0 RK0: MR19=403, MR18=EF9

 2929 22:59:21.890073  CH0_RK0: MR19=0x403, MR18=0xEF9, DQSOSC=404, MR23=63, INC=40, DEC=26

 2930 22:59:21.890522  

 2931 22:59:21.893803  ----->DramcWriteLeveling(PI) begin...

 2932 22:59:21.894339  ==

 2933 22:59:21.896926  Dram Type= 6, Freq= 0, CH_0, rank 1

 2934 22:59:21.900601  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2935 22:59:21.903668  ==

 2936 22:59:21.904089  Write leveling (Byte 0): 32 => 32

 2937 22:59:21.906910  Write leveling (Byte 1): 28 => 28

 2938 22:59:21.910563  DramcWriteLeveling(PI) end<-----

 2939 22:59:21.910989  

 2940 22:59:21.911322  ==

 2941 22:59:21.913542  Dram Type= 6, Freq= 0, CH_0, rank 1

 2942 22:59:21.920258  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2943 22:59:21.920829  ==

 2944 22:59:21.923480  [Gating] SW mode calibration

 2945 22:59:21.930452  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 2946 22:59:21.933346  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 2947 22:59:21.940401   0 15  0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)

 2948 22:59:21.943615   0 15  4 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)

 2949 22:59:21.946708   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2950 22:59:21.953394   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2951 22:59:21.957067   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2952 22:59:21.960264   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2953 22:59:21.966711   0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 2954 22:59:21.970138   0 15 28 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)

 2955 22:59:21.973134   1  0  0 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)

 2956 22:59:21.979669   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2957 22:59:21.983191   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2958 22:59:21.986716   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2959 22:59:21.993162   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2960 22:59:21.996166   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2961 22:59:21.999391   1  0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2962 22:59:22.006279   1  0 28 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 1)

 2963 22:59:22.009717   1  1  0 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)

 2964 22:59:22.012808   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2965 22:59:22.019677   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2966 22:59:22.022758   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2967 22:59:22.025905   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2968 22:59:22.032460   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2969 22:59:22.036283   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 2970 22:59:22.039076   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 2971 22:59:22.042800   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 2972 22:59:22.049458   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2973 22:59:22.052724   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2974 22:59:22.055621   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2975 22:59:22.062280   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2976 22:59:22.066042   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2977 22:59:22.068995   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2978 22:59:22.075778   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2979 22:59:22.078824   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2980 22:59:22.082223   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2981 22:59:22.088753   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2982 22:59:22.092332   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2983 22:59:22.095776   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2984 22:59:22.102322   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2985 22:59:22.105407   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2986 22:59:22.109169   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 2987 22:59:22.115200   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 2988 22:59:22.119005   1  4  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2989 22:59:22.122024  Total UI for P1: 0, mck2ui 16

 2990 22:59:22.125704  best dqsien dly found for B0: ( 1,  3, 30)

 2991 22:59:22.128763  Total UI for P1: 0, mck2ui 16

 2992 22:59:22.132470  best dqsien dly found for B1: ( 1,  3, 30)

 2993 22:59:22.135631  best DQS0 dly(MCK, UI, PI) = (1, 3, 30)

 2994 22:59:22.138764  best DQS1 dly(MCK, UI, PI) = (1, 3, 30)

 2995 22:59:22.139195  

 2996 22:59:22.142365  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)

 2997 22:59:22.145315  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)

 2998 22:59:22.148875  [Gating] SW calibration Done

 2999 22:59:22.149302  ==

 3000 22:59:22.152352  Dram Type= 6, Freq= 0, CH_0, rank 1

 3001 22:59:22.155310  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3002 22:59:22.159021  ==

 3003 22:59:22.159454  RX Vref Scan: 0

 3004 22:59:22.159880  

 3005 22:59:22.162132  RX Vref 0 -> 0, step: 1

 3006 22:59:22.162560  

 3007 22:59:22.165169  RX Delay -40 -> 252, step: 8

 3008 22:59:22.168882  iDelay=200, Bit 0, Center 115 (48 ~ 183) 136

 3009 22:59:22.171620  iDelay=200, Bit 1, Center 119 (48 ~ 191) 144

 3010 22:59:22.175112  iDelay=200, Bit 2, Center 111 (40 ~ 183) 144

 3011 22:59:22.178605  iDelay=200, Bit 3, Center 115 (40 ~ 191) 152

 3012 22:59:22.184923  iDelay=200, Bit 4, Center 119 (48 ~ 191) 144

 3013 22:59:22.188378  iDelay=200, Bit 5, Center 111 (40 ~ 183) 144

 3014 22:59:22.191942  iDelay=200, Bit 6, Center 123 (48 ~ 199) 152

 3015 22:59:22.194809  iDelay=200, Bit 7, Center 123 (48 ~ 199) 152

 3016 22:59:22.198407  iDelay=200, Bit 8, Center 95 (24 ~ 167) 144

 3017 22:59:22.204852  iDelay=200, Bit 9, Center 95 (24 ~ 167) 144

 3018 22:59:22.208619  iDelay=200, Bit 10, Center 111 (40 ~ 183) 144

 3019 22:59:22.211570  iDelay=200, Bit 11, Center 103 (32 ~ 175) 144

 3020 22:59:22.215279  iDelay=200, Bit 12, Center 111 (40 ~ 183) 144

 3021 22:59:22.218404  iDelay=200, Bit 13, Center 119 (48 ~ 191) 144

 3022 22:59:22.225158  iDelay=200, Bit 14, Center 119 (48 ~ 191) 144

 3023 22:59:22.228205  iDelay=200, Bit 15, Center 111 (40 ~ 183) 144

 3024 22:59:22.228744  ==

 3025 22:59:22.231974  Dram Type= 6, Freq= 0, CH_0, rank 1

 3026 22:59:22.234931  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3027 22:59:22.235360  ==

 3028 22:59:22.238120  DQS Delay:

 3029 22:59:22.238941  DQS0 = 0, DQS1 = 0

 3030 22:59:22.239770  DQM Delay:

 3031 22:59:22.241748  DQM0 = 117, DQM1 = 108

 3032 22:59:22.242317  DQ Delay:

 3033 22:59:22.244899  DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115

 3034 22:59:22.248075  DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123

 3035 22:59:22.251477  DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103

 3036 22:59:22.258029  DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111

 3037 22:59:22.258688  

 3038 22:59:22.259308  

 3039 22:59:22.259855  ==

 3040 22:59:22.260956  Dram Type= 6, Freq= 0, CH_0, rank 1

 3041 22:59:22.264727  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3042 22:59:22.265220  ==

 3043 22:59:22.265701  

 3044 22:59:22.266026  

 3045 22:59:22.267731  	TX Vref Scan disable

 3046 22:59:22.268299   == TX Byte 0 ==

 3047 22:59:22.274447  Update DQ  dly =851 (3 ,2, 19)  DQ  OEN =(2 ,7)

 3048 22:59:22.278007  Update DQM dly =851 (3 ,2, 19)  DQM OEN =(2 ,7)

 3049 22:59:22.278496   == TX Byte 1 ==

 3050 22:59:22.284246  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3051 22:59:22.288022  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3052 22:59:22.288445  ==

 3053 22:59:22.290972  Dram Type= 6, Freq= 0, CH_0, rank 1

 3054 22:59:22.294378  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3055 22:59:22.294806  ==

 3056 22:59:22.307891  TX Vref=22, minBit 12, minWin=25, winSum=418

 3057 22:59:22.311032  TX Vref=24, minBit 13, minWin=25, winSum=423

 3058 22:59:22.314720  TX Vref=26, minBit 5, minWin=26, winSum=430

 3059 22:59:22.317714  TX Vref=28, minBit 13, minWin=26, winSum=434

 3060 22:59:22.320939  TX Vref=30, minBit 12, minWin=26, winSum=433

 3061 22:59:22.327686  TX Vref=32, minBit 13, minWin=25, winSum=428

 3062 22:59:22.330652  [TxChooseVref] Worse bit 13, Min win 26, Win sum 434, Final Vref 28

 3063 22:59:22.334193  

 3064 22:59:22.334626  Final TX Range 1 Vref 28

 3065 22:59:22.334974  

 3066 22:59:22.335337  ==

 3067 22:59:22.337394  Dram Type= 6, Freq= 0, CH_0, rank 1

 3068 22:59:22.344126  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3069 22:59:22.344585  ==

 3070 22:59:22.344931  

 3071 22:59:22.345245  

 3072 22:59:22.345542  	TX Vref Scan disable

 3073 22:59:22.347847   == TX Byte 0 ==

 3074 22:59:22.351415  Update DQ  dly =851 (3 ,2, 19)  DQ  OEN =(2 ,7)

 3075 22:59:22.358080  Update DQM dly =851 (3 ,2, 19)  DQM OEN =(2 ,7)

 3076 22:59:22.358729   == TX Byte 1 ==

 3077 22:59:22.361033  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3078 22:59:22.367884  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3079 22:59:22.368494  

 3080 22:59:22.369096  [DATLAT]

 3081 22:59:22.369696  Freq=1200, CH0 RK1

 3082 22:59:22.370223  

 3083 22:59:22.371114  DATLAT Default: 0xd

 3084 22:59:22.374566  0, 0xFFFF, sum = 0

 3085 22:59:22.375232  1, 0xFFFF, sum = 0

 3086 22:59:22.377580  2, 0xFFFF, sum = 0

 3087 22:59:22.378129  3, 0xFFFF, sum = 0

 3088 22:59:22.380722  4, 0xFFFF, sum = 0

 3089 22:59:22.381348  5, 0xFFFF, sum = 0

 3090 22:59:22.384105  6, 0xFFFF, sum = 0

 3091 22:59:22.384815  7, 0xFFFF, sum = 0

 3092 22:59:22.387249  8, 0xFFFF, sum = 0

 3093 22:59:22.387817  9, 0xFFFF, sum = 0

 3094 22:59:22.390698  10, 0xFFFF, sum = 0

 3095 22:59:22.391133  11, 0xFFFF, sum = 0

 3096 22:59:22.394410  12, 0x0, sum = 1

 3097 22:59:22.394814  13, 0x0, sum = 2

 3098 22:59:22.397531  14, 0x0, sum = 3

 3099 22:59:22.398047  15, 0x0, sum = 4

 3100 22:59:22.400831  best_step = 13

 3101 22:59:22.401582  

 3102 22:59:22.402154  ==

 3103 22:59:22.403761  Dram Type= 6, Freq= 0, CH_0, rank 1

 3104 22:59:22.407278  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3105 22:59:22.408024  ==

 3106 22:59:22.410871  RX Vref Scan: 0

 3107 22:59:22.411453  

 3108 22:59:22.412035  RX Vref 0 -> 0, step: 1

 3109 22:59:22.412561  

 3110 22:59:22.414017  RX Delay -21 -> 252, step: 4

 3111 22:59:22.420888  iDelay=199, Bit 0, Center 114 (47 ~ 182) 136

 3112 22:59:22.423961  iDelay=199, Bit 1, Center 118 (47 ~ 190) 144

 3113 22:59:22.427122  iDelay=199, Bit 2, Center 110 (43 ~ 178) 136

 3114 22:59:22.430324  iDelay=199, Bit 3, Center 114 (43 ~ 186) 144

 3115 22:59:22.434079  iDelay=199, Bit 4, Center 116 (47 ~ 186) 140

 3116 22:59:22.440725  iDelay=199, Bit 5, Center 110 (43 ~ 178) 136

 3117 22:59:22.443710  iDelay=199, Bit 6, Center 126 (55 ~ 198) 144

 3118 22:59:22.446886  iDelay=199, Bit 7, Center 124 (55 ~ 194) 140

 3119 22:59:22.450368  iDelay=199, Bit 8, Center 96 (27 ~ 166) 140

 3120 22:59:22.453646  iDelay=199, Bit 9, Center 94 (27 ~ 162) 136

 3121 22:59:22.460268  iDelay=199, Bit 10, Center 110 (43 ~ 178) 136

 3122 22:59:22.463711  iDelay=199, Bit 11, Center 100 (35 ~ 166) 132

 3123 22:59:22.466697  iDelay=199, Bit 12, Center 114 (47 ~ 182) 136

 3124 22:59:22.470341  iDelay=199, Bit 13, Center 114 (47 ~ 182) 136

 3125 22:59:22.474132  iDelay=199, Bit 14, Center 118 (55 ~ 182) 128

 3126 22:59:22.480129  iDelay=199, Bit 15, Center 116 (51 ~ 182) 132

 3127 22:59:22.480775  ==

 3128 22:59:22.483764  Dram Type= 6, Freq= 0, CH_0, rank 1

 3129 22:59:22.486666  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3130 22:59:22.487203  ==

 3131 22:59:22.487710  DQS Delay:

 3132 22:59:22.490071  DQS0 = 0, DQS1 = 0

 3133 22:59:22.490505  DQM Delay:

 3134 22:59:22.493253  DQM0 = 116, DQM1 = 107

 3135 22:59:22.493678  DQ Delay:

 3136 22:59:22.496670  DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =114

 3137 22:59:22.500344  DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124

 3138 22:59:22.503283  DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100

 3139 22:59:22.506736  DQ12 =114, DQ13 =114, DQ14 =118, DQ15 =116

 3140 22:59:22.507332  

 3141 22:59:22.507801  

 3142 22:59:22.516692  [DQSOSCAuto] RK1, (LSB)MR18= 0x10eb, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 403 ps

 3143 22:59:22.519771  CH0 RK1: MR19=403, MR18=10EB

 3144 22:59:22.526446  CH0_RK1: MR19=0x403, MR18=0x10EB, DQSOSC=403, MR23=63, INC=40, DEC=26

 3145 22:59:22.526880  [RxdqsGatingPostProcess] freq 1200

 3146 22:59:22.533207  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 3147 22:59:22.536896  best DQS0 dly(2T, 0.5T) = (0, 11)

 3148 22:59:22.540060  best DQS1 dly(2T, 0.5T) = (0, 12)

 3149 22:59:22.543185  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3150 22:59:22.546412  best DQS1 P1 dly(2T, 0.5T) = (1, 0)

 3151 22:59:22.549605  best DQS0 dly(2T, 0.5T) = (0, 11)

 3152 22:59:22.553190  best DQS1 dly(2T, 0.5T) = (0, 11)

 3153 22:59:22.556218  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3154 22:59:22.559879  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3155 22:59:22.562891  Pre-setting of DQS Precalculation

 3156 22:59:22.565968  [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13

 3157 22:59:22.566394  ==

 3158 22:59:22.569613  Dram Type= 6, Freq= 0, CH_1, rank 0

 3159 22:59:22.575830  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3160 22:59:22.576254  ==

 3161 22:59:22.579567  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3162 22:59:22.586161  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35

 3163 22:59:22.594631  [CA 0] Center 37 (7~68) winsize 62

 3164 22:59:22.597760  [CA 1] Center 37 (7~68) winsize 62

 3165 22:59:22.601286  [CA 2] Center 34 (4~64) winsize 61

 3166 22:59:22.604147  [CA 3] Center 33 (3~64) winsize 62

 3167 22:59:22.607545  [CA 4] Center 34 (5~64) winsize 60

 3168 22:59:22.611033  [CA 5] Center 33 (3~64) winsize 62

 3169 22:59:22.611680  

 3170 22:59:22.614236  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3171 22:59:22.614803  

 3172 22:59:22.617781  [CATrainingPosCal] consider 1 rank data

 3173 22:59:22.621135  u2DelayCellTimex100 = 270/100 ps

 3174 22:59:22.624250  CA0 delay=37 (7~68),Diff = 4 PI (19 cell)

 3175 22:59:22.627492  CA1 delay=37 (7~68),Diff = 4 PI (19 cell)

 3176 22:59:22.634281  CA2 delay=34 (4~64),Diff = 1 PI (4 cell)

 3177 22:59:22.637462  CA3 delay=33 (3~64),Diff = 0 PI (0 cell)

 3178 22:59:22.640950  CA4 delay=34 (5~64),Diff = 1 PI (4 cell)

 3179 22:59:22.644162  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 3180 22:59:22.644856  

 3181 22:59:22.647837  CA PerBit enable=1, Macro0, CA PI delay=33

 3182 22:59:22.648454  

 3183 22:59:22.650755  [CBTSetCACLKResult] CA Dly = 33

 3184 22:59:22.651354  CS Dly: 5 (0~36)

 3185 22:59:22.654056  ==

 3186 22:59:22.654670  Dram Type= 6, Freq= 0, CH_1, rank 1

 3187 22:59:22.660559  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3188 22:59:22.661243  ==

 3189 22:59:22.664155  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3190 22:59:22.671082  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 3191 22:59:22.680210  [CA 0] Center 37 (7~68) winsize 62

 3192 22:59:22.683336  [CA 1] Center 38 (8~68) winsize 61

 3193 22:59:22.686963  [CA 2] Center 34 (4~65) winsize 62

 3194 22:59:22.690184  [CA 3] Center 33 (3~64) winsize 62

 3195 22:59:22.693230  [CA 4] Center 34 (3~65) winsize 63

 3196 22:59:22.696268  [CA 5] Center 33 (3~64) winsize 62

 3197 22:59:22.696880  

 3198 22:59:22.699821  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 3199 22:59:22.700413  

 3200 22:59:22.703366  [CATrainingPosCal] consider 2 rank data

 3201 22:59:22.706344  u2DelayCellTimex100 = 270/100 ps

 3202 22:59:22.709618  CA0 delay=37 (7~68),Diff = 4 PI (19 cell)

 3203 22:59:22.716606  CA1 delay=38 (8~68),Diff = 5 PI (24 cell)

 3204 22:59:22.719565  CA2 delay=34 (4~64),Diff = 1 PI (4 cell)

 3205 22:59:22.723096  CA3 delay=33 (3~64),Diff = 0 PI (0 cell)

 3206 22:59:22.726731  CA4 delay=34 (5~64),Diff = 1 PI (4 cell)

 3207 22:59:22.729826  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 3208 22:59:22.730255  

 3209 22:59:22.733681  CA PerBit enable=1, Macro0, CA PI delay=33

 3210 22:59:22.734112  

 3211 22:59:22.736619  [CBTSetCACLKResult] CA Dly = 33

 3212 22:59:22.737047  CS Dly: 7 (0~40)

 3213 22:59:22.737425  

 3214 22:59:22.739743  ----->DramcWriteLeveling(PI) begin...

 3215 22:59:22.743408  ==

 3216 22:59:22.746398  Dram Type= 6, Freq= 0, CH_1, rank 0

 3217 22:59:22.749589  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3218 22:59:22.750021  ==

 3219 22:59:22.753442  Write leveling (Byte 0): 25 => 25

 3220 22:59:22.756466  Write leveling (Byte 1): 27 => 27

 3221 22:59:22.759459  DramcWriteLeveling(PI) end<-----

 3222 22:59:22.759886  

 3223 22:59:22.760220  ==

 3224 22:59:22.763174  Dram Type= 6, Freq= 0, CH_1, rank 0

 3225 22:59:22.766171  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3226 22:59:22.766602  ==

 3227 22:59:22.769349  [Gating] SW mode calibration

 3228 22:59:22.776076  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 3229 22:59:22.782720  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 3230 22:59:22.786368   0 15  0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)

 3231 22:59:22.789240   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3232 22:59:22.795863   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3233 22:59:22.799439   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3234 22:59:22.803013   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3235 22:59:22.809608   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3236 22:59:22.812653   0 15 24 | B1->B0 | 3434 2b2b | 1 1 | (1 0) (1 0)

 3237 22:59:22.815996   0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)

 3238 22:59:22.822543   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3239 22:59:22.826058   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3240 22:59:22.828884   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3241 22:59:22.835571   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3242 22:59:22.838763   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3243 22:59:22.842437   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3244 22:59:22.849239   1  0 24 | B1->B0 | 2525 3d3d | 0 0 | (0 0) (0 0)

 3245 22:59:22.852225   1  0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)

 3246 22:59:22.855353   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3247 22:59:22.862061   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3248 22:59:22.865810   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3249 22:59:22.868846   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3250 22:59:22.871889   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3251 22:59:22.878654   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3252 22:59:22.882143   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 3253 22:59:22.885311   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 3254 22:59:22.891898   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3255 22:59:22.895513   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3256 22:59:22.898545   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3257 22:59:22.905166   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3258 22:59:22.908794   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3259 22:59:22.911740   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3260 22:59:22.918296   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3261 22:59:22.921751   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3262 22:59:22.925339   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3263 22:59:22.931614   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3264 22:59:22.935170   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3265 22:59:22.938371   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3266 22:59:22.945266   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3267 22:59:22.948348   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3268 22:59:22.951762   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3269 22:59:22.958657   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3270 22:59:22.961883   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3271 22:59:22.965616  Total UI for P1: 0, mck2ui 16

 3272 22:59:22.968678  best dqsien dly found for B0: ( 1,  3, 26)

 3273 22:59:22.971913  Total UI for P1: 0, mck2ui 16

 3274 22:59:22.975098  best dqsien dly found for B1: ( 1,  3, 26)

 3275 22:59:22.978232  best DQS0 dly(MCK, UI, PI) = (1, 3, 26)

 3276 22:59:22.981956  best DQS1 dly(MCK, UI, PI) = (1, 3, 26)

 3277 22:59:22.982570  

 3278 22:59:22.984950  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)

 3279 22:59:22.988345  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)

 3280 22:59:22.991639  [Gating] SW calibration Done

 3281 22:59:22.992197  ==

 3282 22:59:22.994822  Dram Type= 6, Freq= 0, CH_1, rank 0

 3283 22:59:22.998240  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3284 22:59:23.001564  ==

 3285 22:59:23.001958  RX Vref Scan: 0

 3286 22:59:23.002297  

 3287 22:59:23.004702  RX Vref 0 -> 0, step: 1

 3288 22:59:23.005040  

 3289 22:59:23.005378  RX Delay -40 -> 252, step: 8

 3290 22:59:23.012040  iDelay=208, Bit 0, Center 123 (48 ~ 199) 152

 3291 22:59:23.014940  iDelay=208, Bit 1, Center 111 (40 ~ 183) 144

 3292 22:59:23.017981  iDelay=208, Bit 2, Center 111 (40 ~ 183) 144

 3293 22:59:23.021552  iDelay=208, Bit 3, Center 115 (40 ~ 191) 152

 3294 22:59:23.027972  iDelay=208, Bit 4, Center 115 (48 ~ 183) 136

 3295 22:59:23.030939  iDelay=208, Bit 5, Center 131 (56 ~ 207) 152

 3296 22:59:23.034488  iDelay=208, Bit 6, Center 127 (56 ~ 199) 144

 3297 22:59:23.037704  iDelay=208, Bit 7, Center 115 (48 ~ 183) 136

 3298 22:59:23.040876  iDelay=208, Bit 8, Center 95 (24 ~ 167) 144

 3299 22:59:23.044549  iDelay=208, Bit 9, Center 99 (24 ~ 175) 152

 3300 22:59:23.050690  iDelay=208, Bit 10, Center 111 (40 ~ 183) 144

 3301 22:59:23.054018  iDelay=208, Bit 11, Center 95 (24 ~ 167) 144

 3302 22:59:23.057542  iDelay=208, Bit 12, Center 119 (48 ~ 191) 144

 3303 22:59:23.060587  iDelay=208, Bit 13, Center 119 (48 ~ 191) 144

 3304 22:59:23.067254  iDelay=208, Bit 14, Center 119 (48 ~ 191) 144

 3305 22:59:23.070954  iDelay=208, Bit 15, Center 119 (48 ~ 191) 144

 3306 22:59:23.071061  ==

 3307 22:59:23.074135  Dram Type= 6, Freq= 0, CH_1, rank 0

 3308 22:59:23.077215  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3309 22:59:23.077319  ==

 3310 22:59:23.080404  DQS Delay:

 3311 22:59:23.080502  DQS0 = 0, DQS1 = 0

 3312 22:59:23.080577  DQM Delay:

 3313 22:59:23.084031  DQM0 = 118, DQM1 = 109

 3314 22:59:23.084135  DQ Delay:

 3315 22:59:23.087094  DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115

 3316 22:59:23.090605  DQ4 =115, DQ5 =131, DQ6 =127, DQ7 =115

 3317 22:59:23.093820  DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95

 3318 22:59:23.100551  DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119

 3319 22:59:23.100637  

 3320 22:59:23.100705  

 3321 22:59:23.100767  ==

 3322 22:59:23.104048  Dram Type= 6, Freq= 0, CH_1, rank 0

 3323 22:59:23.106921  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3324 22:59:23.107008  ==

 3325 22:59:23.107094  

 3326 22:59:23.107166  

 3327 22:59:23.110092  	TX Vref Scan disable

 3328 22:59:23.110176   == TX Byte 0 ==

 3329 22:59:23.116631  Update DQ  dly =843 (3 ,2, 11)  DQ  OEN =(2 ,7)

 3330 22:59:23.120360  Update DQM dly =843 (3 ,2, 11)  DQM OEN =(2 ,7)

 3331 22:59:23.120472   == TX Byte 1 ==

 3332 22:59:23.126785  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3333 22:59:23.130345  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3334 22:59:23.130462  ==

 3335 22:59:23.133199  Dram Type= 6, Freq= 0, CH_1, rank 0

 3336 22:59:23.136793  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3337 22:59:23.136878  ==

 3338 22:59:23.149445  TX Vref=22, minBit 8, minWin=25, winSum=418

 3339 22:59:23.152578  TX Vref=24, minBit 10, minWin=25, winSum=426

 3340 22:59:23.156166  TX Vref=26, minBit 11, minWin=25, winSum=432

 3341 22:59:23.159224  TX Vref=28, minBit 8, minWin=26, winSum=434

 3342 22:59:23.162921  TX Vref=30, minBit 11, minWin=25, winSum=435

 3343 22:59:23.169657  TX Vref=32, minBit 9, minWin=26, winSum=427

 3344 22:59:23.172742  [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 28

 3345 22:59:23.172826  

 3346 22:59:23.175638  Final TX Range 1 Vref 28

 3347 22:59:23.175747  

 3348 22:59:23.175866  ==

 3349 22:59:23.179439  Dram Type= 6, Freq= 0, CH_1, rank 0

 3350 22:59:23.182449  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3351 22:59:23.186205  ==

 3352 22:59:23.186284  

 3353 22:59:23.186361  

 3354 22:59:23.186426  	TX Vref Scan disable

 3355 22:59:23.189325   == TX Byte 0 ==

 3356 22:59:23.192719  Update DQ  dly =843 (3 ,2, 11)  DQ  OEN =(2 ,7)

 3357 22:59:23.199208  Update DQM dly =843 (3 ,2, 11)  DQM OEN =(2 ,7)

 3358 22:59:23.199352   == TX Byte 1 ==

 3359 22:59:23.202329  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3360 22:59:23.209104  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3361 22:59:23.209189  

 3362 22:59:23.209260  [DATLAT]

 3363 22:59:23.209321  Freq=1200, CH1 RK0

 3364 22:59:23.209379  

 3365 22:59:23.212887  DATLAT Default: 0xd

 3366 22:59:23.212987  0, 0xFFFF, sum = 0

 3367 22:59:23.216151  1, 0xFFFF, sum = 0

 3368 22:59:23.219277  2, 0xFFFF, sum = 0

 3369 22:59:23.219365  3, 0xFFFF, sum = 0

 3370 22:59:23.222446  4, 0xFFFF, sum = 0

 3371 22:59:23.222551  5, 0xFFFF, sum = 0

 3372 22:59:23.226018  6, 0xFFFF, sum = 0

 3373 22:59:23.226154  7, 0xFFFF, sum = 0

 3374 22:59:23.228832  8, 0xFFFF, sum = 0

 3375 22:59:23.228916  9, 0xFFFF, sum = 0

 3376 22:59:23.232333  10, 0xFFFF, sum = 0

 3377 22:59:23.232452  11, 0xFFFF, sum = 0

 3378 22:59:23.235353  12, 0x0, sum = 1

 3379 22:59:23.235472  13, 0x0, sum = 2

 3380 22:59:23.238841  14, 0x0, sum = 3

 3381 22:59:23.238927  15, 0x0, sum = 4

 3382 22:59:23.242347  best_step = 13

 3383 22:59:23.242423  

 3384 22:59:23.242484  ==

 3385 22:59:23.245434  Dram Type= 6, Freq= 0, CH_1, rank 0

 3386 22:59:23.248989  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3387 22:59:23.249077  ==

 3388 22:59:23.249140  RX Vref Scan: 1

 3389 22:59:23.252108  

 3390 22:59:23.252181  Set Vref Range= 32 -> 127

 3391 22:59:23.252242  

 3392 22:59:23.255751  RX Vref 32 -> 127, step: 1

 3393 22:59:23.255858  

 3394 22:59:23.258816  RX Delay -21 -> 252, step: 4

 3395 22:59:23.258902  

 3396 22:59:23.262538  Set Vref, RX VrefLevel [Byte0]: 32

 3397 22:59:23.265557                           [Byte1]: 32

 3398 22:59:23.265652  

 3399 22:59:23.268679  Set Vref, RX VrefLevel [Byte0]: 33

 3400 22:59:23.272293                           [Byte1]: 33

 3401 22:59:23.276020  

 3402 22:59:23.276122  Set Vref, RX VrefLevel [Byte0]: 34

 3403 22:59:23.279134                           [Byte1]: 34

 3404 22:59:23.284034  

 3405 22:59:23.284146  Set Vref, RX VrefLevel [Byte0]: 35

 3406 22:59:23.287088                           [Byte1]: 35

 3407 22:59:23.291571  

 3408 22:59:23.291653  Set Vref, RX VrefLevel [Byte0]: 36

 3409 22:59:23.295242                           [Byte1]: 36

 3410 22:59:23.299378  

 3411 22:59:23.299456  Set Vref, RX VrefLevel [Byte0]: 37

 3412 22:59:23.302927                           [Byte1]: 37

 3413 22:59:23.307322  

 3414 22:59:23.307402  Set Vref, RX VrefLevel [Byte0]: 38

 3415 22:59:23.310941                           [Byte1]: 38

 3416 22:59:23.315457  

 3417 22:59:23.315538  Set Vref, RX VrefLevel [Byte0]: 39

 3418 22:59:23.318782                           [Byte1]: 39

 3419 22:59:23.323727  

 3420 22:59:23.323795  Set Vref, RX VrefLevel [Byte0]: 40

 3421 22:59:23.326813                           [Byte1]: 40

 3422 22:59:23.331458  

 3423 22:59:23.331555  Set Vref, RX VrefLevel [Byte0]: 41

 3424 22:59:23.334418                           [Byte1]: 41

 3425 22:59:23.339034  

 3426 22:59:23.339108  Set Vref, RX VrefLevel [Byte0]: 42

 3427 22:59:23.342551                           [Byte1]: 42

 3428 22:59:23.347030  

 3429 22:59:23.347126  Set Vref, RX VrefLevel [Byte0]: 43

 3430 22:59:23.350603                           [Byte1]: 43

 3431 22:59:23.355419  

 3432 22:59:23.355530  Set Vref, RX VrefLevel [Byte0]: 44

 3433 22:59:23.358420                           [Byte1]: 44

 3434 22:59:23.363423  

 3435 22:59:23.363527  Set Vref, RX VrefLevel [Byte0]: 45

 3436 22:59:23.366487                           [Byte1]: 45

 3437 22:59:23.370780  

 3438 22:59:23.370879  Set Vref, RX VrefLevel [Byte0]: 46

 3439 22:59:23.374112                           [Byte1]: 46

 3440 22:59:23.379064  

 3441 22:59:23.379170  Set Vref, RX VrefLevel [Byte0]: 47

 3442 22:59:23.382017                           [Byte1]: 47

 3443 22:59:23.386957  

 3444 22:59:23.387056  Set Vref, RX VrefLevel [Byte0]: 48

 3445 22:59:23.390063                           [Byte1]: 48

 3446 22:59:23.394419  

 3447 22:59:23.394518  Set Vref, RX VrefLevel [Byte0]: 49

 3448 22:59:23.398087                           [Byte1]: 49

 3449 22:59:23.402291  

 3450 22:59:23.402391  Set Vref, RX VrefLevel [Byte0]: 50

 3451 22:59:23.405612                           [Byte1]: 50

 3452 22:59:23.410302  

 3453 22:59:23.410378  Set Vref, RX VrefLevel [Byte0]: 51

 3454 22:59:23.413537                           [Byte1]: 51

 3455 22:59:23.418463  

 3456 22:59:23.418558  Set Vref, RX VrefLevel [Byte0]: 52

 3457 22:59:23.424798                           [Byte1]: 52

 3458 22:59:23.424874  

 3459 22:59:23.428049  Set Vref, RX VrefLevel [Byte0]: 53

 3460 22:59:23.431717                           [Byte1]: 53

 3461 22:59:23.431799  

 3462 22:59:23.434611  Set Vref, RX VrefLevel [Byte0]: 54

 3463 22:59:23.437982                           [Byte1]: 54

 3464 22:59:23.442143  

 3465 22:59:23.442236  Set Vref, RX VrefLevel [Byte0]: 55

 3466 22:59:23.445783                           [Byte1]: 55

 3467 22:59:23.449809  

 3468 22:59:23.449894  Set Vref, RX VrefLevel [Byte0]: 56

 3469 22:59:23.453223                           [Byte1]: 56

 3470 22:59:23.457984  

 3471 22:59:23.458063  Set Vref, RX VrefLevel [Byte0]: 57

 3472 22:59:23.461156                           [Byte1]: 57

 3473 22:59:23.466017  

 3474 22:59:23.466216  Set Vref, RX VrefLevel [Byte0]: 58

 3475 22:59:23.469192                           [Byte1]: 58

 3476 22:59:23.474146  

 3477 22:59:23.474253  Set Vref, RX VrefLevel [Byte0]: 59

 3478 22:59:23.477182                           [Byte1]: 59

 3479 22:59:23.482073  

 3480 22:59:23.482155  Set Vref, RX VrefLevel [Byte0]: 60

 3481 22:59:23.485115                           [Byte1]: 60

 3482 22:59:23.489987  

 3483 22:59:23.490058  Set Vref, RX VrefLevel [Byte0]: 61

 3484 22:59:23.493108                           [Byte1]: 61

 3485 22:59:23.497456  

 3486 22:59:23.497557  Set Vref, RX VrefLevel [Byte0]: 62

 3487 22:59:23.500734                           [Byte1]: 62

 3488 22:59:23.505625  

 3489 22:59:23.505706  Set Vref, RX VrefLevel [Byte0]: 63

 3490 22:59:23.509132                           [Byte1]: 63

 3491 22:59:23.513868  

 3492 22:59:23.513950  Set Vref, RX VrefLevel [Byte0]: 64

 3493 22:59:23.516919                           [Byte1]: 64

 3494 22:59:23.521050  

 3495 22:59:23.521136  Set Vref, RX VrefLevel [Byte0]: 65

 3496 22:59:23.524801                           [Byte1]: 65

 3497 22:59:23.529197  

 3498 22:59:23.529283  Set Vref, RX VrefLevel [Byte0]: 66

 3499 22:59:23.532555                           [Byte1]: 66

 3500 22:59:23.537412  

 3501 22:59:23.537502  Set Vref, RX VrefLevel [Byte0]: 67

 3502 22:59:23.540352                           [Byte1]: 67

 3503 22:59:23.545051  

 3504 22:59:23.545186  Set Vref, RX VrefLevel [Byte0]: 68

 3505 22:59:23.548095                           [Byte1]: 68

 3506 22:59:23.552827  

 3507 22:59:23.556262  Final RX Vref Byte 0 = 45 to rank0

 3508 22:59:23.556337  Final RX Vref Byte 1 = 57 to rank0

 3509 22:59:23.559268  Final RX Vref Byte 0 = 45 to rank1

 3510 22:59:23.562832  Final RX Vref Byte 1 = 57 to rank1==

 3511 22:59:23.566434  Dram Type= 6, Freq= 0, CH_1, rank 0

 3512 22:59:23.572762  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3513 22:59:23.572848  ==

 3514 22:59:23.572913  DQS Delay:

 3515 22:59:23.576321  DQS0 = 0, DQS1 = 0

 3516 22:59:23.576428  DQM Delay:

 3517 22:59:23.576541  DQM0 = 115, DQM1 = 111

 3518 22:59:23.579556  DQ Delay:

 3519 22:59:23.582817  DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =112

 3520 22:59:23.585941  DQ4 =112, DQ5 =126, DQ6 =126, DQ7 =114

 3521 22:59:23.589051  DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =100

 3522 22:59:23.592774  DQ12 =118, DQ13 =118, DQ14 =122, DQ15 =118

 3523 22:59:23.592856  

 3524 22:59:23.592921  

 3525 22:59:23.602684  [DQSOSCAuto] RK0, (LSB)MR18= 0x3f7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 408 ps

 3526 22:59:23.602767  CH1 RK0: MR19=403, MR18=3F7

 3527 22:59:23.609435  CH1_RK0: MR19=0x403, MR18=0x3F7, DQSOSC=408, MR23=63, INC=39, DEC=26

 3528 22:59:23.609556  

 3529 22:59:23.612377  ----->DramcWriteLeveling(PI) begin...

 3530 22:59:23.612462  ==

 3531 22:59:23.615877  Dram Type= 6, Freq= 0, CH_1, rank 1

 3532 22:59:23.622718  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3533 22:59:23.622803  ==

 3534 22:59:23.625727  Write leveling (Byte 0): 24 => 24

 3535 22:59:23.625810  Write leveling (Byte 1): 29 => 29

 3536 22:59:23.629019  DramcWriteLeveling(PI) end<-----

 3537 22:59:23.629101  

 3538 22:59:23.632736  ==

 3539 22:59:23.635843  Dram Type= 6, Freq= 0, CH_1, rank 1

 3540 22:59:23.638674  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3541 22:59:23.638757  ==

 3542 22:59:23.642248  [Gating] SW mode calibration

 3543 22:59:23.648710  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 3544 22:59:23.652140  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 3545 22:59:23.658690   0 15  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3546 22:59:23.662012   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3547 22:59:23.665071   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3548 22:59:23.671863   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3549 22:59:23.675429   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3550 22:59:23.678535   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3551 22:59:23.685358   0 15 24 | B1->B0 | 2f2f 3434 | 1 1 | (1 0) (1 0)

 3552 22:59:23.688473   0 15 28 | B1->B0 | 2323 2424 | 0 1 | (1 0) (1 0)

 3553 22:59:23.691616   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3554 22:59:23.698400   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3555 22:59:23.701405   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3556 22:59:23.704581   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3557 22:59:23.711430   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3558 22:59:23.714440   1  0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 3559 22:59:23.717997   1  0 24 | B1->B0 | 3b3b 2626 | 0 1 | (0 0) (0 0)

 3560 22:59:23.724404   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3561 22:59:23.727430   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3562 22:59:23.734328   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3563 22:59:23.737443   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3564 22:59:23.741029   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3565 22:59:23.744040   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3566 22:59:23.750425   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3567 22:59:23.753881   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 3568 22:59:23.757202   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 3569 22:59:23.763915   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3570 22:59:23.767546   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3571 22:59:23.770759   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3572 22:59:23.777405   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3573 22:59:23.780415   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3574 22:59:23.783448   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3575 22:59:23.790242   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3576 22:59:23.793866   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3577 22:59:23.796949   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3578 22:59:23.803781   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3579 22:59:23.806826   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3580 22:59:23.809820   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3581 22:59:23.816670   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3582 22:59:23.819566   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3583 22:59:23.823177   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3584 22:59:23.829729   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3585 22:59:23.833121   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3586 22:59:23.836945  Total UI for P1: 0, mck2ui 16

 3587 22:59:23.839976  best dqsien dly found for B0: ( 1,  3, 26)

 3588 22:59:23.843136  Total UI for P1: 0, mck2ui 16

 3589 22:59:23.846348  best dqsien dly found for B1: ( 1,  3, 26)

 3590 22:59:23.849731  best DQS0 dly(MCK, UI, PI) = (1, 3, 26)

 3591 22:59:23.853482  best DQS1 dly(MCK, UI, PI) = (1, 3, 26)

 3592 22:59:23.853565  

 3593 22:59:23.856368  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)

 3594 22:59:23.859789  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)

 3595 22:59:23.863141  [Gating] SW calibration Done

 3596 22:59:23.863259  ==

 3597 22:59:23.865943  Dram Type= 6, Freq= 0, CH_1, rank 1

 3598 22:59:23.872894  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3599 22:59:23.872978  ==

 3600 22:59:23.873042  RX Vref Scan: 0

 3601 22:59:23.873140  

 3602 22:59:23.876442  RX Vref 0 -> 0, step: 1

 3603 22:59:23.876578  

 3604 22:59:23.879244  RX Delay -40 -> 252, step: 8

 3605 22:59:23.882950  iDelay=200, Bit 0, Center 123 (56 ~ 191) 136

 3606 22:59:23.886205  iDelay=200, Bit 1, Center 111 (40 ~ 183) 144

 3607 22:59:23.889159  iDelay=200, Bit 2, Center 107 (40 ~ 175) 136

 3608 22:59:23.895729  iDelay=200, Bit 3, Center 111 (40 ~ 183) 144

 3609 22:59:23.899500  iDelay=200, Bit 4, Center 115 (40 ~ 191) 152

 3610 22:59:23.902533  iDelay=200, Bit 5, Center 127 (56 ~ 199) 144

 3611 22:59:23.905685  iDelay=200, Bit 6, Center 127 (56 ~ 199) 144

 3612 22:59:23.909428  iDelay=200, Bit 7, Center 115 (40 ~ 191) 152

 3613 22:59:23.912404  iDelay=200, Bit 8, Center 95 (24 ~ 167) 144

 3614 22:59:23.919151  iDelay=200, Bit 9, Center 103 (32 ~ 175) 144

 3615 22:59:23.922327  iDelay=200, Bit 10, Center 111 (40 ~ 183) 144

 3616 22:59:23.925547  iDelay=200, Bit 11, Center 103 (32 ~ 175) 144

 3617 22:59:23.929329  iDelay=200, Bit 12, Center 119 (48 ~ 191) 144

 3618 22:59:23.935828  iDelay=200, Bit 13, Center 119 (48 ~ 191) 144

 3619 22:59:23.938854  iDelay=200, Bit 14, Center 115 (40 ~ 191) 152

 3620 22:59:23.941983  iDelay=200, Bit 15, Center 119 (48 ~ 191) 144

 3621 22:59:23.942064  ==

 3622 22:59:23.945654  Dram Type= 6, Freq= 0, CH_1, rank 1

 3623 22:59:23.948707  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3624 22:59:23.948789  ==

 3625 22:59:23.952406  DQS Delay:

 3626 22:59:23.952487  DQS0 = 0, DQS1 = 0

 3627 22:59:23.955396  DQM Delay:

 3628 22:59:23.955502  DQM0 = 117, DQM1 = 110

 3629 22:59:23.959055  DQ Delay:

 3630 22:59:23.961971  DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =111

 3631 22:59:23.965564  DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115

 3632 22:59:23.969056  DQ8 =95, DQ9 =103, DQ10 =111, DQ11 =103

 3633 22:59:23.972063  DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119

 3634 22:59:23.972145  

 3635 22:59:23.972208  

 3636 22:59:23.972267  ==

 3637 22:59:23.975404  Dram Type= 6, Freq= 0, CH_1, rank 1

 3638 22:59:23.978449  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3639 22:59:23.978532  ==

 3640 22:59:23.978596  

 3641 22:59:23.978655  

 3642 22:59:23.982004  	TX Vref Scan disable

 3643 22:59:23.984967   == TX Byte 0 ==

 3644 22:59:23.988450  Update DQ  dly =843 (3 ,2, 11)  DQ  OEN =(2 ,7)

 3645 22:59:23.991994  Update DQM dly =843 (3 ,2, 11)  DQM OEN =(2 ,7)

 3646 22:59:23.995077   == TX Byte 1 ==

 3647 22:59:23.998421  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 3648 22:59:24.002106  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 3649 22:59:24.002213  ==

 3650 22:59:24.005165  Dram Type= 6, Freq= 0, CH_1, rank 1

 3651 22:59:24.011362  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3652 22:59:24.011475  ==

 3653 22:59:24.022442  TX Vref=22, minBit 8, minWin=25, winSum=424

 3654 22:59:24.025579  TX Vref=24, minBit 8, minWin=25, winSum=428

 3655 22:59:24.028734  TX Vref=26, minBit 8, minWin=25, winSum=433

 3656 22:59:24.032385  TX Vref=28, minBit 8, minWin=26, winSum=435

 3657 22:59:24.035330  TX Vref=30, minBit 8, minWin=26, winSum=436

 3658 22:59:24.042006  TX Vref=32, minBit 9, minWin=25, winSum=431

 3659 22:59:24.045086  [TxChooseVref] Worse bit 8, Min win 26, Win sum 436, Final Vref 30

 3660 22:59:24.045168  

 3661 22:59:24.048317  Final TX Range 1 Vref 30

 3662 22:59:24.048399  

 3663 22:59:24.048462  ==

 3664 22:59:24.051923  Dram Type= 6, Freq= 0, CH_1, rank 1

 3665 22:59:24.055093  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3666 22:59:24.058809  ==

 3667 22:59:24.058890  

 3668 22:59:24.058954  

 3669 22:59:24.059013  	TX Vref Scan disable

 3670 22:59:24.062228   == TX Byte 0 ==

 3671 22:59:24.065174  Update DQ  dly =842 (3 ,2, 10)  DQ  OEN =(2 ,7)

 3672 22:59:24.072230  Update DQM dly =842 (3 ,2, 10)  DQM OEN =(2 ,7)

 3673 22:59:24.072314   == TX Byte 1 ==

 3674 22:59:24.075656  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 3675 22:59:24.082219  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 3676 22:59:24.082300  

 3677 22:59:24.082367  [DATLAT]

 3678 22:59:24.082450  Freq=1200, CH1 RK1

 3679 22:59:24.082510  

 3680 22:59:24.085706  DATLAT Default: 0xd

 3681 22:59:24.085788  0, 0xFFFF, sum = 0

 3682 22:59:24.088488  1, 0xFFFF, sum = 0

 3683 22:59:24.091883  2, 0xFFFF, sum = 0

 3684 22:59:24.092040  3, 0xFFFF, sum = 0

 3685 22:59:24.095366  4, 0xFFFF, sum = 0

 3686 22:59:24.095475  5, 0xFFFF, sum = 0

 3687 22:59:24.098210  6, 0xFFFF, sum = 0

 3688 22:59:24.098292  7, 0xFFFF, sum = 0

 3689 22:59:24.101499  8, 0xFFFF, sum = 0

 3690 22:59:24.101587  9, 0xFFFF, sum = 0

 3691 22:59:24.105281  10, 0xFFFF, sum = 0

 3692 22:59:24.105363  11, 0xFFFF, sum = 0

 3693 22:59:24.108431  12, 0x0, sum = 1

 3694 22:59:24.108525  13, 0x0, sum = 2

 3695 22:59:24.111678  14, 0x0, sum = 3

 3696 22:59:24.111751  15, 0x0, sum = 4

 3697 22:59:24.114761  best_step = 13

 3698 22:59:24.114843  

 3699 22:59:24.114908  ==

 3700 22:59:24.118371  Dram Type= 6, Freq= 0, CH_1, rank 1

 3701 22:59:24.121596  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3702 22:59:24.121680  ==

 3703 22:59:24.124684  RX Vref Scan: 0

 3704 22:59:24.124767  

 3705 22:59:24.124833  RX Vref 0 -> 0, step: 1

 3706 22:59:24.124894  

 3707 22:59:24.128404  RX Delay -21 -> 252, step: 4

 3708 22:59:24.135034  iDelay=195, Bit 0, Center 120 (55 ~ 186) 132

 3709 22:59:24.138157  iDelay=195, Bit 1, Center 110 (47 ~ 174) 128

 3710 22:59:24.140978  iDelay=195, Bit 2, Center 106 (43 ~ 170) 128

 3711 22:59:24.144491  iDelay=195, Bit 3, Center 112 (47 ~ 178) 132

 3712 22:59:24.148173  iDelay=195, Bit 4, Center 114 (47 ~ 182) 136

 3713 22:59:24.154450  iDelay=195, Bit 5, Center 126 (63 ~ 190) 128

 3714 22:59:24.158059  iDelay=195, Bit 6, Center 130 (67 ~ 194) 128

 3715 22:59:24.161086  iDelay=195, Bit 7, Center 112 (47 ~ 178) 132

 3716 22:59:24.164212  iDelay=195, Bit 8, Center 98 (31 ~ 166) 136

 3717 22:59:24.167861  iDelay=195, Bit 9, Center 100 (35 ~ 166) 132

 3718 22:59:24.174383  iDelay=195, Bit 10, Center 112 (47 ~ 178) 132

 3719 22:59:24.177304  iDelay=195, Bit 11, Center 100 (35 ~ 166) 132

 3720 22:59:24.180831  iDelay=195, Bit 12, Center 118 (51 ~ 186) 136

 3721 22:59:24.184352  iDelay=195, Bit 13, Center 118 (51 ~ 186) 136

 3722 22:59:24.190597  iDelay=195, Bit 14, Center 118 (51 ~ 186) 136

 3723 22:59:24.194181  iDelay=195, Bit 15, Center 120 (51 ~ 190) 140

 3724 22:59:24.194263  ==

 3725 22:59:24.197643  Dram Type= 6, Freq= 0, CH_1, rank 1

 3726 22:59:24.200468  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3727 22:59:24.200586  ==

 3728 22:59:24.203835  DQS Delay:

 3729 22:59:24.203916  DQS0 = 0, DQS1 = 0

 3730 22:59:24.203979  DQM Delay:

 3731 22:59:24.206993  DQM0 = 116, DQM1 = 110

 3732 22:59:24.207087  DQ Delay:

 3733 22:59:24.210699  DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =112

 3734 22:59:24.213812  DQ4 =114, DQ5 =126, DQ6 =130, DQ7 =112

 3735 22:59:24.216945  DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =100

 3736 22:59:24.223639  DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =120

 3737 22:59:24.223721  

 3738 22:59:24.223793  

 3739 22:59:24.230460  [DQSOSCAuto] RK1, (LSB)MR18= 0xf7f3, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps

 3740 22:59:24.233597  CH1 RK1: MR19=303, MR18=F7F3

 3741 22:59:24.240242  CH1_RK1: MR19=0x303, MR18=0xF7F3, DQSOSC=413, MR23=63, INC=38, DEC=25

 3742 22:59:24.243371  [RxdqsGatingPostProcess] freq 1200

 3743 22:59:24.246971  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 3744 22:59:24.249992  best DQS0 dly(2T, 0.5T) = (0, 11)

 3745 22:59:24.253808  best DQS1 dly(2T, 0.5T) = (0, 11)

 3746 22:59:24.256881  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3747 22:59:24.259808  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3748 22:59:24.263542  best DQS0 dly(2T, 0.5T) = (0, 11)

 3749 22:59:24.266543  best DQS1 dly(2T, 0.5T) = (0, 11)

 3750 22:59:24.270321  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3751 22:59:24.273307  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3752 22:59:24.276452  Pre-setting of DQS Precalculation

 3753 22:59:24.280052  [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13

 3754 22:59:24.289998  sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2

 3755 22:59:24.296147  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 3756 22:59:24.296229  

 3757 22:59:24.296293  

 3758 22:59:24.299553  [Calibration Summary] 2400 Mbps

 3759 22:59:24.299636  CH 0, Rank 0

 3760 22:59:24.303074  SW Impedance     : PASS

 3761 22:59:24.303156  DUTY Scan        : NO K

 3762 22:59:24.306720  ZQ Calibration   : PASS

 3763 22:59:24.309456  Jitter Meter     : NO K

 3764 22:59:24.309539  CBT Training     : PASS

 3765 22:59:24.313154  Write leveling   : PASS

 3766 22:59:24.316361  RX DQS gating    : PASS

 3767 22:59:24.316443  RX DQ/DQS(RDDQC) : PASS

 3768 22:59:24.319405  TX DQ/DQS        : PASS

 3769 22:59:24.322942  RX DATLAT        : PASS

 3770 22:59:24.323024  RX DQ/DQS(Engine): PASS

 3771 22:59:24.326138  TX OE            : NO K

 3772 22:59:24.326220  All Pass.

 3773 22:59:24.326284  

 3774 22:59:24.329223  CH 0, Rank 1

 3775 22:59:24.329305  SW Impedance     : PASS

 3776 22:59:24.333010  DUTY Scan        : NO K

 3777 22:59:24.335991  ZQ Calibration   : PASS

 3778 22:59:24.336071  Jitter Meter     : NO K

 3779 22:59:24.339515  CBT Training     : PASS

 3780 22:59:24.342515  Write leveling   : PASS

 3781 22:59:24.342596  RX DQS gating    : PASS

 3782 22:59:24.345643  RX DQ/DQS(RDDQC) : PASS

 3783 22:59:24.349291  TX DQ/DQS        : PASS

 3784 22:59:24.349372  RX DATLAT        : PASS

 3785 22:59:24.352743  RX DQ/DQS(Engine): PASS

 3786 22:59:24.355881  TX OE            : NO K

 3787 22:59:24.355963  All Pass.

 3788 22:59:24.356026  

 3789 22:59:24.356084  CH 1, Rank 0

 3790 22:59:24.359035  SW Impedance     : PASS

 3791 22:59:24.362045  DUTY Scan        : NO K

 3792 22:59:24.362127  ZQ Calibration   : PASS

 3793 22:59:24.365877  Jitter Meter     : NO K

 3794 22:59:24.368958  CBT Training     : PASS

 3795 22:59:24.369040  Write leveling   : PASS

 3796 22:59:24.372047  RX DQS gating    : PASS

 3797 22:59:24.372129  RX DQ/DQS(RDDQC) : PASS

 3798 22:59:24.375615  TX DQ/DQS        : PASS

 3799 22:59:24.378734  RX DATLAT        : PASS

 3800 22:59:24.378815  RX DQ/DQS(Engine): PASS

 3801 22:59:24.382020  TX OE            : NO K

 3802 22:59:24.382102  All Pass.

 3803 22:59:24.382166  

 3804 22:59:24.385377  CH 1, Rank 1

 3805 22:59:24.385458  SW Impedance     : PASS

 3806 22:59:24.388897  DUTY Scan        : NO K

 3807 22:59:24.392121  ZQ Calibration   : PASS

 3808 22:59:24.392201  Jitter Meter     : NO K

 3809 22:59:24.395233  CBT Training     : PASS

 3810 22:59:24.398614  Write leveling   : PASS

 3811 22:59:24.398696  RX DQS gating    : PASS

 3812 22:59:24.402178  RX DQ/DQS(RDDQC) : PASS

 3813 22:59:24.405016  TX DQ/DQS        : PASS

 3814 22:59:24.405098  RX DATLAT        : PASS

 3815 22:59:24.408658  RX DQ/DQS(Engine): PASS

 3816 22:59:24.411560  TX OE            : NO K

 3817 22:59:24.411642  All Pass.

 3818 22:59:24.411705  

 3819 22:59:24.415064  DramC Write-DBI off

 3820 22:59:24.415146  	PER_BANK_REFRESH: Hybrid Mode

 3821 22:59:24.418546  TX_TRACKING: ON

 3822 22:59:24.425184  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1

 3823 22:59:24.431474  [FAST_K] Save calibration result to emmc

 3824 22:59:24.435092  dramc_set_vcore_voltage set vcore to 650000

 3825 22:59:24.435173  Read voltage for 600, 5

 3826 22:59:24.438125  Vio18 = 0

 3827 22:59:24.438207  Vcore = 650000

 3828 22:59:24.438270  Vdram = 0

 3829 22:59:24.441850  Vddq = 0

 3830 22:59:24.441930  Vmddr = 0

 3831 22:59:24.444862  [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0

 3832 22:59:24.451168  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 3833 22:59:24.454620  MEM_TYPE=3, freq_sel=19

 3834 22:59:24.457773  sv_algorithm_assistance_LP4_1600 

 3835 22:59:24.461362  ============ PULL DRAM RESETB DOWN ============

 3836 22:59:24.464478  ========== PULL DRAM RESETB DOWN end =========

 3837 22:59:24.471372  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3838 22:59:24.474399  =================================== 

 3839 22:59:24.474480  LPDDR4 DRAM CONFIGURATION

 3840 22:59:24.477425  =================================== 

 3841 22:59:24.481060  EX_ROW_EN[0]    = 0x0

 3842 22:59:24.484280  EX_ROW_EN[1]    = 0x0

 3843 22:59:24.484386  LP4Y_EN      = 0x0

 3844 22:59:24.487868  WORK_FSP     = 0x0

 3845 22:59:24.487950  WL           = 0x2

 3846 22:59:24.490878  RL           = 0x2

 3847 22:59:24.490959  BL           = 0x2

 3848 22:59:24.494347  RPST         = 0x0

 3849 22:59:24.494444  RD_PRE       = 0x0

 3850 22:59:24.497664  WR_PRE       = 0x1

 3851 22:59:24.497739  WR_PST       = 0x0

 3852 22:59:24.500697  DBI_WR       = 0x0

 3853 22:59:24.500779  DBI_RD       = 0x0

 3854 22:59:24.504083  OTF          = 0x1

 3855 22:59:24.507346  =================================== 

 3856 22:59:24.510775  =================================== 

 3857 22:59:24.510873  ANA top config

 3858 22:59:24.514045  =================================== 

 3859 22:59:24.516954  DLL_ASYNC_EN            =  0

 3860 22:59:24.520347  ALL_SLAVE_EN            =  1

 3861 22:59:24.523711  NEW_RANK_MODE           =  1

 3862 22:59:24.523794  DLL_IDLE_MODE           =  1

 3863 22:59:24.527103  LP45_APHY_COMB_EN       =  1

 3864 22:59:24.530386  TX_ODT_DIS              =  1

 3865 22:59:24.533920  NEW_8X_MODE             =  1

 3866 22:59:24.537001  =================================== 

 3867 22:59:24.540181  =================================== 

 3868 22:59:24.543312  data_rate                  = 1200

 3869 22:59:24.543464  CKR                        = 1

 3870 22:59:24.547096  DQ_P2S_RATIO               = 8

 3871 22:59:24.550123  =================================== 

 3872 22:59:24.553172  CA_P2S_RATIO               = 8

 3873 22:59:24.556792  DQ_CA_OPEN                 = 0

 3874 22:59:24.560312  DQ_SEMI_OPEN               = 0

 3875 22:59:24.563341  CA_SEMI_OPEN               = 0

 3876 22:59:24.563502  CA_FULL_RATE               = 0

 3877 22:59:24.566404  DQ_CKDIV4_EN               = 1

 3878 22:59:24.570106  CA_CKDIV4_EN               = 1

 3879 22:59:24.573200  CA_PREDIV_EN               = 0

 3880 22:59:24.576297  PH8_DLY                    = 0

 3881 22:59:24.579416  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 3882 22:59:24.579596  DQ_AAMCK_DIV               = 4

 3883 22:59:24.583069  CA_AAMCK_DIV               = 4

 3884 22:59:24.586131  CA_ADMCK_DIV               = 4

 3885 22:59:24.590004  DQ_TRACK_CA_EN             = 0

 3886 22:59:24.593118  CA_PICK                    = 600

 3887 22:59:24.596399  CA_MCKIO                   = 600

 3888 22:59:24.599760  MCKIO_SEMI                 = 0

 3889 22:59:24.599901  PLL_FREQ                   = 2288

 3890 22:59:24.603245  DQ_UI_PI_RATIO             = 32

 3891 22:59:24.606846  CA_UI_PI_RATIO             = 0

 3892 22:59:24.609820  =================================== 

 3893 22:59:24.613232  =================================== 

 3894 22:59:24.616149  memory_type:LPDDR4         

 3895 22:59:24.616223  GP_NUM     : 10       

 3896 22:59:24.619516  SRAM_EN    : 1       

 3897 22:59:24.622969  MD32_EN    : 0       

 3898 22:59:24.626040  =================================== 

 3899 22:59:24.626123  [ANA_INIT] >>>>>>>>>>>>>> 

 3900 22:59:24.629537  <<<<<< [CONFIGURE PHASE]: ANA_TX

 3901 22:59:24.632803  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 3902 22:59:24.635868  =================================== 

 3903 22:59:24.639492  data_rate = 1200,PCW = 0X5800

 3904 22:59:24.642552  =================================== 

 3905 22:59:24.646222  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 3906 22:59:24.652454  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 3907 22:59:24.659243  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 3908 22:59:24.662247  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 3909 22:59:24.665847  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 3910 22:59:24.669100  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 3911 22:59:24.672200  [ANA_INIT] flow start 

 3912 22:59:24.672285  [ANA_INIT] PLL >>>>>>>> 

 3913 22:59:24.675331  [ANA_INIT] PLL <<<<<<<< 

 3914 22:59:24.679133  [ANA_INIT] MIDPI >>>>>>>> 

 3915 22:59:24.679217  [ANA_INIT] MIDPI <<<<<<<< 

 3916 22:59:24.682065  [ANA_INIT] DLL >>>>>>>> 

 3917 22:59:24.685279  [ANA_INIT] flow end 

 3918 22:59:24.688874  ============ LP4 DIFF to SE enter ============

 3919 22:59:24.691998  ============ LP4 DIFF to SE exit  ============

 3920 22:59:24.695771  [ANA_INIT] <<<<<<<<<<<<< 

 3921 22:59:24.698889  [Flow] Enable top DCM control >>>>> 

 3922 22:59:24.701911  [Flow] Enable top DCM control <<<<< 

 3923 22:59:24.705384  Enable DLL master slave shuffle 

 3924 22:59:24.711991  ============================================================== 

 3925 22:59:24.712078  Gating Mode config

 3926 22:59:24.718377  ============================================================== 

 3927 22:59:24.718463  Config description: 

 3928 22:59:24.728334  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 3929 22:59:24.734886  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 3930 22:59:24.741666  SELPH_MODE            0: By rank         1: By Phase 

 3931 22:59:24.744752  ============================================================== 

 3932 22:59:24.748324  GAT_TRACK_EN                 =  1

 3933 22:59:24.751404  RX_GATING_MODE               =  2

 3934 22:59:24.754691  RX_GATING_TRACK_MODE         =  2

 3935 22:59:24.757776  SELPH_MODE                   =  1

 3936 22:59:24.761536  PICG_EARLY_EN                =  1

 3937 22:59:24.764531  VALID_LAT_VALUE              =  1

 3938 22:59:24.771026  ============================================================== 

 3939 22:59:24.774146  Enter into Gating configuration >>>> 

 3940 22:59:24.777935  Exit from Gating configuration <<<< 

 3941 22:59:24.781025  Enter into  DVFS_PRE_config >>>>> 

 3942 22:59:24.791068  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 3943 22:59:24.794125  Exit from  DVFS_PRE_config <<<<< 

 3944 22:59:24.797258  Enter into PICG configuration >>>> 

 3945 22:59:24.800961  Exit from PICG configuration <<<< 

 3946 22:59:24.804007  [RX_INPUT] configuration >>>>> 

 3947 22:59:24.804110  [RX_INPUT] configuration <<<<< 

 3948 22:59:24.810685  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 3949 22:59:24.817424  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 3950 22:59:24.820775  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 3951 22:59:24.827053  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 3952 22:59:24.834045  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 3953 22:59:24.840281  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 3954 22:59:24.843664  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 3955 22:59:24.847317  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 3956 22:59:24.853410  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 3957 22:59:24.857053  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 3958 22:59:24.860053  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 3959 22:59:24.866805  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3960 22:59:24.870389  =================================== 

 3961 22:59:24.870499  LPDDR4 DRAM CONFIGURATION

 3962 22:59:24.873357  =================================== 

 3963 22:59:24.877160  EX_ROW_EN[0]    = 0x0

 3964 22:59:24.880164  EX_ROW_EN[1]    = 0x0

 3965 22:59:24.880270  LP4Y_EN      = 0x0

 3966 22:59:24.883339  WORK_FSP     = 0x0

 3967 22:59:24.883448  WL           = 0x2

 3968 22:59:24.886990  RL           = 0x2

 3969 22:59:24.887091  BL           = 0x2

 3970 22:59:24.890031  RPST         = 0x0

 3971 22:59:24.890133  RD_PRE       = 0x0

 3972 22:59:24.893082  WR_PRE       = 0x1

 3973 22:59:24.893188  WR_PST       = 0x0

 3974 22:59:24.896884  DBI_WR       = 0x0

 3975 22:59:24.896997  DBI_RD       = 0x0

 3976 22:59:24.899744  OTF          = 0x1

 3977 22:59:24.902933  =================================== 

 3978 22:59:24.906681  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 3979 22:59:24.909708  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 3980 22:59:24.916290  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3981 22:59:24.919897  =================================== 

 3982 22:59:24.920009  LPDDR4 DRAM CONFIGURATION

 3983 22:59:24.922996  =================================== 

 3984 22:59:24.925926  EX_ROW_EN[0]    = 0x10

 3985 22:59:24.929465  EX_ROW_EN[1]    = 0x0

 3986 22:59:24.929584  LP4Y_EN      = 0x0

 3987 22:59:24.932959  WORK_FSP     = 0x0

 3988 22:59:24.933074  WL           = 0x2

 3989 22:59:24.935935  RL           = 0x2

 3990 22:59:24.936038  BL           = 0x2

 3991 22:59:24.939750  RPST         = 0x0

 3992 22:59:24.939869  RD_PRE       = 0x0

 3993 22:59:24.942443  WR_PRE       = 0x1

 3994 22:59:24.942554  WR_PST       = 0x0

 3995 22:59:24.945863  DBI_WR       = 0x0

 3996 22:59:24.945977  DBI_RD       = 0x0

 3997 22:59:24.949139  OTF          = 0x1

 3998 22:59:24.952633  =================================== 

 3999 22:59:24.959380  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 4000 22:59:24.962390  nWR fixed to 30

 4001 22:59:24.962537  [ModeRegInit_LP4] CH0 RK0

 4002 22:59:24.966062  [ModeRegInit_LP4] CH0 RK1

 4003 22:59:24.969260  [ModeRegInit_LP4] CH1 RK0

 4004 22:59:24.972305  [ModeRegInit_LP4] CH1 RK1

 4005 22:59:24.972407  match AC timing 17

 4006 22:59:24.978823  dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1

 4007 22:59:24.982694  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 4008 22:59:24.985826  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

 4009 22:59:24.992071  [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17

 4010 22:59:24.995172  [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)

 4011 22:59:24.995313  ==

 4012 22:59:24.998893  Dram Type= 6, Freq= 0, CH_0, rank 0

 4013 22:59:25.002017  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4014 22:59:25.002101  ==

 4015 22:59:25.008707  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4016 22:59:25.015227  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33

 4017 22:59:25.018343  [CA 0] Center 36 (6~66) winsize 61

 4018 22:59:25.021841  [CA 1] Center 36 (6~66) winsize 61

 4019 22:59:25.024915  [CA 2] Center 34 (4~65) winsize 62

 4020 22:59:25.028560  [CA 3] Center 34 (4~65) winsize 62

 4021 22:59:25.031384  [CA 4] Center 33 (3~64) winsize 62

 4022 22:59:25.034842  [CA 5] Center 33 (3~64) winsize 62

 4023 22:59:25.034934  

 4024 22:59:25.038611  [CmdBusTrainingLP45] Vref(ca) range 1: 33

 4025 22:59:25.038694  

 4026 22:59:25.041246  [CATrainingPosCal] consider 1 rank data

 4027 22:59:25.044921  u2DelayCellTimex100 = 270/100 ps

 4028 22:59:25.047923  CA0 delay=36 (6~66),Diff = 3 PI (28 cell)

 4029 22:59:25.051407  CA1 delay=36 (6~66),Diff = 3 PI (28 cell)

 4030 22:59:25.054856  CA2 delay=34 (4~65),Diff = 1 PI (9 cell)

 4031 22:59:25.057815  CA3 delay=34 (4~65),Diff = 1 PI (9 cell)

 4032 22:59:25.064525  CA4 delay=33 (3~64),Diff = 0 PI (0 cell)

 4033 22:59:25.067603  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 4034 22:59:25.067687  

 4035 22:59:25.071317  CA PerBit enable=1, Macro0, CA PI delay=33

 4036 22:59:25.071425  

 4037 22:59:25.074372  [CBTSetCACLKResult] CA Dly = 33

 4038 22:59:25.074456  CS Dly: 5 (0~36)

 4039 22:59:25.074522  ==

 4040 22:59:25.077461  Dram Type= 6, Freq= 0, CH_0, rank 1

 4041 22:59:25.084001  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4042 22:59:25.084085  ==

 4043 22:59:25.087854  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4044 22:59:25.093874  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 4045 22:59:25.097559  [CA 0] Center 35 (5~66) winsize 62

 4046 22:59:25.100565  [CA 1] Center 36 (6~66) winsize 61

 4047 22:59:25.104223  [CA 2] Center 34 (4~64) winsize 61

 4048 22:59:25.107432  [CA 3] Center 33 (3~64) winsize 62

 4049 22:59:25.110386  [CA 4] Center 33 (3~64) winsize 62

 4050 22:59:25.114057  [CA 5] Center 33 (2~64) winsize 63

 4051 22:59:25.114167  

 4052 22:59:25.117130  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 4053 22:59:25.117230  

 4054 22:59:25.120232  [CATrainingPosCal] consider 2 rank data

 4055 22:59:25.123793  u2DelayCellTimex100 = 270/100 ps

 4056 22:59:25.126820  CA0 delay=36 (6~66),Diff = 3 PI (28 cell)

 4057 22:59:25.133472  CA1 delay=36 (6~66),Diff = 3 PI (28 cell)

 4058 22:59:25.137003  CA2 delay=34 (4~64),Diff = 1 PI (9 cell)

 4059 22:59:25.140213  CA3 delay=34 (4~64),Diff = 1 PI (9 cell)

 4060 22:59:25.143741  CA4 delay=33 (3~64),Diff = 0 PI (0 cell)

 4061 22:59:25.147347  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 4062 22:59:25.147446  

 4063 22:59:25.150797  CA PerBit enable=1, Macro0, CA PI delay=33

 4064 22:59:25.150897  

 4065 22:59:25.153545  [CBTSetCACLKResult] CA Dly = 33

 4066 22:59:25.153641  CS Dly: 5 (0~36)

 4067 22:59:25.157131  

 4068 22:59:25.160079  ----->DramcWriteLeveling(PI) begin...

 4069 22:59:25.160155  ==

 4070 22:59:25.163765  Dram Type= 6, Freq= 0, CH_0, rank 0

 4071 22:59:25.166844  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4072 22:59:25.166929  ==

 4073 22:59:25.169846  Write leveling (Byte 0): 34 => 34

 4074 22:59:25.173077  Write leveling (Byte 1): 30 => 30

 4075 22:59:25.176743  DramcWriteLeveling(PI) end<-----

 4076 22:59:25.176827  

 4077 22:59:25.176892  ==

 4078 22:59:25.179821  Dram Type= 6, Freq= 0, CH_0, rank 0

 4079 22:59:25.183380  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4080 22:59:25.183464  ==

 4081 22:59:25.186505  [Gating] SW mode calibration

 4082 22:59:25.193145  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4083 22:59:25.199452  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4084 22:59:25.203170   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4085 22:59:25.206346   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4086 22:59:25.212869   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4087 22:59:25.215950   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)

 4088 22:59:25.219154   0  9 16 | B1->B0 | 2f2f 2424 | 0 0 | (1 1) (0 0)

 4089 22:59:25.225725   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4090 22:59:25.229284   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4091 22:59:25.232310   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4092 22:59:25.239388   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4093 22:59:25.242363   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4094 22:59:25.245413   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4095 22:59:25.252418   0 10 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)

 4096 22:59:25.255446   0 10 16 | B1->B0 | 3434 3c3c | 0 0 | (0 0) (1 1)

 4097 22:59:25.258824   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4098 22:59:25.265771   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4099 22:59:25.268850   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4100 22:59:25.271950   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4101 22:59:25.278689   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4102 22:59:25.282411   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4103 22:59:25.285339   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4104 22:59:25.291993   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4105 22:59:25.294983   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4106 22:59:25.298777   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4107 22:59:25.304902   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4108 22:59:25.308523   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4109 22:59:25.311764   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4110 22:59:25.318017   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4111 22:59:25.321866   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4112 22:59:25.324745   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4113 22:59:25.331383   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4114 22:59:25.334997   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4115 22:59:25.337955   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4116 22:59:25.344391   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4117 22:59:25.347732   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4118 22:59:25.351376   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4119 22:59:25.357630   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 4120 22:59:25.361157   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 4121 22:59:25.364679  Total UI for P1: 0, mck2ui 16

 4122 22:59:25.367595  best dqsien dly found for B0: ( 0, 13, 12)

 4123 22:59:25.370532   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4124 22:59:25.374340  Total UI for P1: 0, mck2ui 16

 4125 22:59:25.377425  best dqsien dly found for B1: ( 0, 13, 14)

 4126 22:59:25.381117  best DQS0 dly(MCK, UI, PI) = (0, 13, 12)

 4127 22:59:25.387231  best DQS1 dly(MCK, UI, PI) = (0, 13, 14)

 4128 22:59:25.387338  

 4129 22:59:25.390879  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4130 22:59:25.393843  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4131 22:59:25.397490  [Gating] SW calibration Done

 4132 22:59:25.397631  ==

 4133 22:59:25.400396  Dram Type= 6, Freq= 0, CH_0, rank 0

 4134 22:59:25.404102  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4135 22:59:25.404186  ==

 4136 22:59:25.407155  RX Vref Scan: 0

 4137 22:59:25.407263  

 4138 22:59:25.407362  RX Vref 0 -> 0, step: 1

 4139 22:59:25.407452  

 4140 22:59:25.410443  RX Delay -230 -> 252, step: 16

 4141 22:59:25.414055  iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320

 4142 22:59:25.420233  iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320

 4143 22:59:25.423660  iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320

 4144 22:59:25.426996  iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320

 4145 22:59:25.430237  iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336

 4146 22:59:25.436977  iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336

 4147 22:59:25.440140  iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336

 4148 22:59:25.443629  iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336

 4149 22:59:25.446539  iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336

 4150 22:59:25.449987  iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336

 4151 22:59:25.456971  iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336

 4152 22:59:25.460187  iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352

 4153 22:59:25.463783  iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336

 4154 22:59:25.466664  iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336

 4155 22:59:25.473077  iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336

 4156 22:59:25.476783  iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336

 4157 22:59:25.476885  ==

 4158 22:59:25.480022  Dram Type= 6, Freq= 0, CH_0, rank 0

 4159 22:59:25.483115  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4160 22:59:25.483199  ==

 4161 22:59:25.486240  DQS Delay:

 4162 22:59:25.486347  DQS0 = 0, DQS1 = 0

 4163 22:59:25.486441  DQM Delay:

 4164 22:59:25.489962  DQM0 = 43, DQM1 = 30

 4165 22:59:25.490046  DQ Delay:

 4166 22:59:25.493054  DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41

 4167 22:59:25.496483  DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49

 4168 22:59:25.499699  DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25

 4169 22:59:25.503421  DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33

 4170 22:59:25.503504  

 4171 22:59:25.503569  

 4172 22:59:25.503628  ==

 4173 22:59:25.506451  Dram Type= 6, Freq= 0, CH_0, rank 0

 4174 22:59:25.513046  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4175 22:59:25.513159  ==

 4176 22:59:25.513251  

 4177 22:59:25.513340  

 4178 22:59:25.513428  	TX Vref Scan disable

 4179 22:59:25.516900   == TX Byte 0 ==

 4180 22:59:25.520431  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 4181 22:59:25.526630  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 4182 22:59:25.526714   == TX Byte 1 ==

 4183 22:59:25.530188  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4184 22:59:25.536740  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4185 22:59:25.536824  ==

 4186 22:59:25.540053  Dram Type= 6, Freq= 0, CH_0, rank 0

 4187 22:59:25.543046  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4188 22:59:25.543154  ==

 4189 22:59:25.543248  

 4190 22:59:25.543336  

 4191 22:59:25.546508  	TX Vref Scan disable

 4192 22:59:25.550013   == TX Byte 0 ==

 4193 22:59:25.553583  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 4194 22:59:25.556401  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 4195 22:59:25.559913   == TX Byte 1 ==

 4196 22:59:25.563014  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4197 22:59:25.566373  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4198 22:59:25.566462  

 4199 22:59:25.569967  [DATLAT]

 4200 22:59:25.570051  Freq=600, CH0 RK0

 4201 22:59:25.570117  

 4202 22:59:25.572914  DATLAT Default: 0x9

 4203 22:59:25.572997  0, 0xFFFF, sum = 0

 4204 22:59:25.576377  1, 0xFFFF, sum = 0

 4205 22:59:25.576461  2, 0xFFFF, sum = 0

 4206 22:59:25.579391  3, 0xFFFF, sum = 0

 4207 22:59:25.579502  4, 0xFFFF, sum = 0

 4208 22:59:25.583074  5, 0xFFFF, sum = 0

 4209 22:59:25.583164  6, 0xFFFF, sum = 0

 4210 22:59:25.586215  7, 0xFFFF, sum = 0

 4211 22:59:25.586299  8, 0x0, sum = 1

 4212 22:59:25.589999  9, 0x0, sum = 2

 4213 22:59:25.590084  10, 0x0, sum = 3

 4214 22:59:25.593126  11, 0x0, sum = 4

 4215 22:59:25.593211  best_step = 9

 4216 22:59:25.593276  

 4217 22:59:25.593336  ==

 4218 22:59:25.596195  Dram Type= 6, Freq= 0, CH_0, rank 0

 4219 22:59:25.599740  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4220 22:59:25.599825  ==

 4221 22:59:25.602632  RX Vref Scan: 1

 4222 22:59:25.602739  

 4223 22:59:25.606459  RX Vref 0 -> 0, step: 1

 4224 22:59:25.606542  

 4225 22:59:25.606609  RX Delay -195 -> 252, step: 8

 4226 22:59:25.609477  

 4227 22:59:25.609559  Set Vref, RX VrefLevel [Byte0]: 60

 4228 22:59:25.612804                           [Byte1]: 49

 4229 22:59:25.617713  

 4230 22:59:25.617795  Final RX Vref Byte 0 = 60 to rank0

 4231 22:59:25.620733  Final RX Vref Byte 1 = 49 to rank0

 4232 22:59:25.624395  Final RX Vref Byte 0 = 60 to rank1

 4233 22:59:25.627386  Final RX Vref Byte 1 = 49 to rank1==

 4234 22:59:25.630733  Dram Type= 6, Freq= 0, CH_0, rank 0

 4235 22:59:25.637280  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4236 22:59:25.637365  ==

 4237 22:59:25.637431  DQS Delay:

 4238 22:59:25.640775  DQS0 = 0, DQS1 = 0

 4239 22:59:25.640858  DQM Delay:

 4240 22:59:25.640924  DQM0 = 43, DQM1 = 32

 4241 22:59:25.644230  DQ Delay:

 4242 22:59:25.647362  DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40

 4243 22:59:25.650980  DQ4 =40, DQ5 =32, DQ6 =52, DQ7 =52

 4244 22:59:25.653952  DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24

 4245 22:59:25.657396  DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40

 4246 22:59:25.657479  

 4247 22:59:25.657544  

 4248 22:59:25.663730  [DQSOSCAuto] RK0, (LSB)MR18= 0x643c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 391 ps

 4249 22:59:25.667397  CH0 RK0: MR19=808, MR18=643C

 4250 22:59:25.673854  CH0_RK0: MR19=0x808, MR18=0x643C, DQSOSC=391, MR23=63, INC=171, DEC=114

 4251 22:59:25.673938  

 4252 22:59:25.677381  ----->DramcWriteLeveling(PI) begin...

 4253 22:59:25.677466  ==

 4254 22:59:25.680341  Dram Type= 6, Freq= 0, CH_0, rank 1

 4255 22:59:25.683870  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4256 22:59:25.683954  ==

 4257 22:59:25.686988  Write leveling (Byte 0): 34 => 34

 4258 22:59:25.690793  Write leveling (Byte 1): 33 => 33

 4259 22:59:25.693886  DramcWriteLeveling(PI) end<-----

 4260 22:59:25.693970  

 4261 22:59:25.694035  ==

 4262 22:59:25.696861  Dram Type= 6, Freq= 0, CH_0, rank 1

 4263 22:59:25.700549  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4264 22:59:25.700633  ==

 4265 22:59:25.703454  [Gating] SW mode calibration

 4266 22:59:25.710039  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4267 22:59:25.716830  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4268 22:59:25.719950   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4269 22:59:25.726861   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4270 22:59:25.729629   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4271 22:59:25.733358   0  9 12 | B1->B0 | 3232 3434 | 1 0 | (1 0) (1 1)

 4272 22:59:25.739545   0  9 16 | B1->B0 | 2d2d 2929 | 0 0 | (0 0) (0 0)

 4273 22:59:25.743199   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4274 22:59:25.746252   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4275 22:59:25.752702   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4276 22:59:25.756397   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4277 22:59:25.759356   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4278 22:59:25.766232   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4279 22:59:25.769213   0 10 12 | B1->B0 | 2626 2626 | 0 1 | (0 0) (0 0)

 4280 22:59:25.772752   0 10 16 | B1->B0 | 3d3d 3f3f | 0 0 | (0 0) (0 0)

 4281 22:59:25.779328   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4282 22:59:25.782459   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4283 22:59:25.786038   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4284 22:59:25.792765   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4285 22:59:25.795904   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4286 22:59:25.799080   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4287 22:59:25.805952   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4288 22:59:25.808985   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4289 22:59:25.812189   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4290 22:59:25.818944   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4291 22:59:25.822657   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4292 22:59:25.825659   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4293 22:59:25.832552   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4294 22:59:25.835570   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4295 22:59:25.839283   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4296 22:59:25.845293   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4297 22:59:25.849200   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4298 22:59:25.852361   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4299 22:59:25.859131   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4300 22:59:25.861983   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4301 22:59:25.865366   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4302 22:59:25.871464   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4303 22:59:25.874921   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4304 22:59:25.878299   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4305 22:59:25.881899  Total UI for P1: 0, mck2ui 16

 4306 22:59:25.884765  best dqsien dly found for B0: ( 0, 13, 14)

 4307 22:59:25.888275  Total UI for P1: 0, mck2ui 16

 4308 22:59:25.891781  best dqsien dly found for B1: ( 0, 13, 14)

 4309 22:59:25.894865  best DQS0 dly(MCK, UI, PI) = (0, 13, 14)

 4310 22:59:25.900960  best DQS1 dly(MCK, UI, PI) = (0, 13, 14)

 4311 22:59:25.901541  

 4312 22:59:25.904785  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4313 22:59:25.907741  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4314 22:59:25.911239  [Gating] SW calibration Done

 4315 22:59:25.911803  ==

 4316 22:59:25.914841  Dram Type= 6, Freq= 0, CH_0, rank 1

 4317 22:59:25.917992  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4318 22:59:25.918566  ==

 4319 22:59:25.921079  RX Vref Scan: 0

 4320 22:59:25.921529  

 4321 22:59:25.921979  RX Vref 0 -> 0, step: 1

 4322 22:59:25.922459  

 4323 22:59:25.924113  RX Delay -230 -> 252, step: 16

 4324 22:59:25.927873  iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320

 4325 22:59:25.934195  iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336

 4326 22:59:25.937340  iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320

 4327 22:59:25.940997  iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320

 4328 22:59:25.944783  iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320

 4329 22:59:25.950920  iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336

 4330 22:59:25.953990  iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336

 4331 22:59:25.957571  iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336

 4332 22:59:25.960863  iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320

 4333 22:59:25.963891  iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320

 4334 22:59:25.970514  iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336

 4335 22:59:25.974150  iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320

 4336 22:59:25.977848  iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320

 4337 22:59:25.980461  iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336

 4338 22:59:25.987180  iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336

 4339 22:59:25.990243  iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320

 4340 22:59:25.990884  ==

 4341 22:59:25.993621  Dram Type= 6, Freq= 0, CH_0, rank 1

 4342 22:59:25.996359  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4343 22:59:25.996774  ==

 4344 22:59:25.999801  DQS Delay:

 4345 22:59:26.000025  DQS0 = 0, DQS1 = 0

 4346 22:59:26.003232  DQM Delay:

 4347 22:59:26.003424  DQM0 = 43, DQM1 = 36

 4348 22:59:26.003581  DQ Delay:

 4349 22:59:26.006327  DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41

 4350 22:59:26.009830  DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49

 4351 22:59:26.012940  DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25

 4352 22:59:26.015954  DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41

 4353 22:59:26.016029  

 4354 22:59:26.019439  

 4355 22:59:26.019510  ==

 4356 22:59:26.022488  Dram Type= 6, Freq= 0, CH_0, rank 1

 4357 22:59:26.026427  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4358 22:59:26.026505  ==

 4359 22:59:26.026569  

 4360 22:59:26.026626  

 4361 22:59:26.029360  	TX Vref Scan disable

 4362 22:59:26.029444   == TX Byte 0 ==

 4363 22:59:26.036237  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 4364 22:59:26.039197  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 4365 22:59:26.039279   == TX Byte 1 ==

 4366 22:59:26.045941  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 4367 22:59:26.049097  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 4368 22:59:26.049178  ==

 4369 22:59:26.052716  Dram Type= 6, Freq= 0, CH_0, rank 1

 4370 22:59:26.056008  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4371 22:59:26.056088  ==

 4372 22:59:26.056151  

 4373 22:59:26.056208  

 4374 22:59:26.059087  	TX Vref Scan disable

 4375 22:59:26.062246   == TX Byte 0 ==

 4376 22:59:26.066188  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 4377 22:59:26.069219  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 4378 22:59:26.072227   == TX Byte 1 ==

 4379 22:59:26.075376  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 4380 22:59:26.082218  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 4381 22:59:26.082375  

 4382 22:59:26.082499  [DATLAT]

 4383 22:59:26.082618  Freq=600, CH0 RK1

 4384 22:59:26.082734  

 4385 22:59:26.085284  DATLAT Default: 0x9

 4386 22:59:26.085395  0, 0xFFFF, sum = 0

 4387 22:59:26.088704  1, 0xFFFF, sum = 0

 4388 22:59:26.088833  2, 0xFFFF, sum = 0

 4389 22:59:26.092263  3, 0xFFFF, sum = 0

 4390 22:59:26.095550  4, 0xFFFF, sum = 0

 4391 22:59:26.095734  5, 0xFFFF, sum = 0

 4392 22:59:26.098910  6, 0xFFFF, sum = 0

 4393 22:59:26.099130  7, 0xFFFF, sum = 0

 4394 22:59:26.102455  8, 0x0, sum = 1

 4395 22:59:26.102631  9, 0x0, sum = 2

 4396 22:59:26.102769  10, 0x0, sum = 3

 4397 22:59:26.105160  11, 0x0, sum = 4

 4398 22:59:26.105341  best_step = 9

 4399 22:59:26.105491  

 4400 22:59:26.105615  ==

 4401 22:59:26.108482  Dram Type= 6, Freq= 0, CH_0, rank 1

 4402 22:59:26.115183  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4403 22:59:26.115427  ==

 4404 22:59:26.115622  RX Vref Scan: 0

 4405 22:59:26.115801  

 4406 22:59:26.118451  RX Vref 0 -> 0, step: 1

 4407 22:59:26.118748  

 4408 22:59:26.122137  RX Delay -179 -> 252, step: 8

 4409 22:59:26.125091  iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296

 4410 22:59:26.132140  iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304

 4411 22:59:26.135587  iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304

 4412 22:59:26.138683  iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312

 4413 22:59:26.142024  iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304

 4414 22:59:26.149190  iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312

 4415 22:59:26.152032  iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312

 4416 22:59:26.155118  iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312

 4417 22:59:26.158724  iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304

 4418 22:59:26.161876  iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304

 4419 22:59:26.168724  iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312

 4420 22:59:26.171597  iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304

 4421 22:59:26.174828  iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304

 4422 22:59:26.178419  iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304

 4423 22:59:26.185290  iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296

 4424 22:59:26.188147  iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304

 4425 22:59:26.188644  ==

 4426 22:59:26.191638  Dram Type= 6, Freq= 0, CH_0, rank 1

 4427 22:59:26.194908  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4428 22:59:26.195564  ==

 4429 22:59:26.198362  DQS Delay:

 4430 22:59:26.198927  DQS0 = 0, DQS1 = 0

 4431 22:59:26.199411  DQM Delay:

 4432 22:59:26.201875  DQM0 = 41, DQM1 = 37

 4433 22:59:26.202406  DQ Delay:

 4434 22:59:26.205136  DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40

 4435 22:59:26.208470  DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48

 4436 22:59:26.211915  DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28

 4437 22:59:26.214570  DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44

 4438 22:59:26.215092  

 4439 22:59:26.215561  

 4440 22:59:26.224621  [DQSOSCAuto] RK1, (LSB)MR18= 0x6519, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 390 ps

 4441 22:59:26.228191  CH0 RK1: MR19=808, MR18=6519

 4442 22:59:26.234541  CH0_RK1: MR19=0x808, MR18=0x6519, DQSOSC=390, MR23=63, INC=172, DEC=114

 4443 22:59:26.235079  [RxdqsGatingPostProcess] freq 600

 4444 22:59:26.241184  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 4445 22:59:26.244926  Pre-setting of DQS Precalculation

 4446 22:59:26.247941  [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9

 4447 22:59:26.248370  ==

 4448 22:59:26.251570  Dram Type= 6, Freq= 0, CH_1, rank 0

 4449 22:59:26.258506  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4450 22:59:26.258939  ==

 4451 22:59:26.261547  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4452 22:59:26.267466  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 4453 22:59:26.271142  [CA 0] Center 35 (5~66) winsize 62

 4454 22:59:26.274910  [CA 1] Center 35 (5~66) winsize 62

 4455 22:59:26.278002  [CA 2] Center 34 (3~65) winsize 63

 4456 22:59:26.281592  [CA 3] Center 33 (3~64) winsize 62

 4457 22:59:26.284784  [CA 4] Center 34 (4~65) winsize 62

 4458 22:59:26.287810  [CA 5] Center 33 (3~64) winsize 62

 4459 22:59:26.288319  

 4460 22:59:26.290936  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 4461 22:59:26.291428  

 4462 22:59:26.294658  [CATrainingPosCal] consider 1 rank data

 4463 22:59:26.298227  u2DelayCellTimex100 = 270/100 ps

 4464 22:59:26.301284  CA0 delay=35 (5~66),Diff = 2 PI (19 cell)

 4465 22:59:26.307627  CA1 delay=35 (5~66),Diff = 2 PI (19 cell)

 4466 22:59:26.310935  CA2 delay=34 (3~65),Diff = 1 PI (9 cell)

 4467 22:59:26.314476  CA3 delay=33 (3~64),Diff = 0 PI (0 cell)

 4468 22:59:26.317406  CA4 delay=34 (4~65),Diff = 1 PI (9 cell)

 4469 22:59:26.320903  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 4470 22:59:26.321333  

 4471 22:59:26.324255  CA PerBit enable=1, Macro0, CA PI delay=33

 4472 22:59:26.324810  

 4473 22:59:26.327167  [CBTSetCACLKResult] CA Dly = 33

 4474 22:59:26.330683  CS Dly: 5 (0~36)

 4475 22:59:26.331115  ==

 4476 22:59:26.333852  Dram Type= 6, Freq= 0, CH_1, rank 1

 4477 22:59:26.337452  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4478 22:59:26.337881  ==

 4479 22:59:26.344014  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4480 22:59:26.347191  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 4481 22:59:26.351382  [CA 0] Center 35 (5~66) winsize 62

 4482 22:59:26.354666  [CA 1] Center 36 (6~66) winsize 61

 4483 22:59:26.358262  [CA 2] Center 34 (4~65) winsize 62

 4484 22:59:26.361274  [CA 3] Center 34 (4~65) winsize 62

 4485 22:59:26.364901  [CA 4] Center 34 (4~65) winsize 62

 4486 22:59:26.367945  [CA 5] Center 33 (3~64) winsize 62

 4487 22:59:26.368471  

 4488 22:59:26.371828  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 4489 22:59:26.372259  

 4490 22:59:26.374627  [CATrainingPosCal] consider 2 rank data

 4491 22:59:26.377926  u2DelayCellTimex100 = 270/100 ps

 4492 22:59:26.381732  CA0 delay=35 (5~66),Diff = 2 PI (19 cell)

 4493 22:59:26.388571  CA1 delay=36 (6~66),Diff = 3 PI (28 cell)

 4494 22:59:26.391453  CA2 delay=34 (4~65),Diff = 1 PI (9 cell)

 4495 22:59:26.394557  CA3 delay=34 (4~64),Diff = 1 PI (9 cell)

 4496 22:59:26.398221  CA4 delay=34 (4~65),Diff = 1 PI (9 cell)

 4497 22:59:26.401321  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 4498 22:59:26.401752  

 4499 22:59:26.404288  CA PerBit enable=1, Macro0, CA PI delay=33

 4500 22:59:26.404796  

 4501 22:59:26.407842  [CBTSetCACLKResult] CA Dly = 33

 4502 22:59:26.411210  CS Dly: 5 (0~37)

 4503 22:59:26.411778  

 4504 22:59:26.414319  ----->DramcWriteLeveling(PI) begin...

 4505 22:59:26.414754  ==

 4506 22:59:26.417783  Dram Type= 6, Freq= 0, CH_1, rank 0

 4507 22:59:26.421174  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4508 22:59:26.421602  ==

 4509 22:59:26.424461  Write leveling (Byte 0): 31 => 31

 4510 22:59:26.427386  Write leveling (Byte 1): 31 => 31

 4511 22:59:26.431017  DramcWriteLeveling(PI) end<-----

 4512 22:59:26.431623  

 4513 22:59:26.432109  ==

 4514 22:59:26.434162  Dram Type= 6, Freq= 0, CH_1, rank 0

 4515 22:59:26.436991  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4516 22:59:26.437414  ==

 4517 22:59:26.440647  [Gating] SW mode calibration

 4518 22:59:26.447235  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4519 22:59:26.453508  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4520 22:59:26.457096   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4521 22:59:26.460182   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4522 22:59:26.466935   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4523 22:59:26.470146   0  9 12 | B1->B0 | 3131 2e2e | 0 1 | (0 1) (1 1)

 4524 22:59:26.473316   0  9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4525 22:59:26.480070   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4526 22:59:26.483293   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4527 22:59:26.489940   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4528 22:59:26.493044   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4529 22:59:26.496096   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4530 22:59:26.502821   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4531 22:59:26.506498   0 10 12 | B1->B0 | 3131 3a3a | 0 1 | (0 0) (0 0)

 4532 22:59:26.509524   0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)

 4533 22:59:26.516180   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4534 22:59:26.519018   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4535 22:59:26.522432   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4536 22:59:26.529459   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4537 22:59:26.532392   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4538 22:59:26.535897   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4539 22:59:26.542679   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 4540 22:59:26.545601   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4541 22:59:26.549147   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4542 22:59:26.556003   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4543 22:59:26.559089   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4544 22:59:26.562230   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4545 22:59:26.568443   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4546 22:59:26.571655   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4547 22:59:26.575284   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4548 22:59:26.581502   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4549 22:59:26.585064   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4550 22:59:26.588282   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4551 22:59:26.594794   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4552 22:59:26.597935   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4553 22:59:26.601749   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4554 22:59:26.608384   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4555 22:59:26.611275   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 4556 22:59:26.614979   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4557 22:59:26.618083  Total UI for P1: 0, mck2ui 16

 4558 22:59:26.621588  best dqsien dly found for B0: ( 0, 13, 12)

 4559 22:59:26.624490  Total UI for P1: 0, mck2ui 16

 4560 22:59:26.628263  best dqsien dly found for B1: ( 0, 13, 14)

 4561 22:59:26.631186  best DQS0 dly(MCK, UI, PI) = (0, 13, 12)

 4562 22:59:26.634590  best DQS1 dly(MCK, UI, PI) = (0, 13, 14)

 4563 22:59:26.635022  

 4564 22:59:26.640838  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4565 22:59:26.644372  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4566 22:59:26.644845  [Gating] SW calibration Done

 4567 22:59:26.647663  ==

 4568 22:59:26.650957  Dram Type= 6, Freq= 0, CH_1, rank 0

 4569 22:59:26.654065  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4570 22:59:26.654495  ==

 4571 22:59:26.654833  RX Vref Scan: 0

 4572 22:59:26.655148  

 4573 22:59:26.657770  RX Vref 0 -> 0, step: 1

 4574 22:59:26.658199  

 4575 22:59:26.660974  RX Delay -230 -> 252, step: 16

 4576 22:59:26.664073  iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320

 4577 22:59:26.667753  iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320

 4578 22:59:26.673747  iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336

 4579 22:59:26.677612  iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320

 4580 22:59:26.680503  iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320

 4581 22:59:26.683793  iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320

 4582 22:59:26.690354  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4583 22:59:26.694064  iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336

 4584 22:59:26.697149  iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320

 4585 22:59:26.700791  iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336

 4586 22:59:26.707404  iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336

 4587 22:59:26.710488  iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320

 4588 22:59:26.713653  iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336

 4589 22:59:26.717142  iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352

 4590 22:59:26.720303  iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352

 4591 22:59:26.726860  iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336

 4592 22:59:26.727442  ==

 4593 22:59:26.730507  Dram Type= 6, Freq= 0, CH_1, rank 0

 4594 22:59:26.733629  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4595 22:59:26.734280  ==

 4596 22:59:26.736702  DQS Delay:

 4597 22:59:26.737297  DQS0 = 0, DQS1 = 0

 4598 22:59:26.737800  DQM Delay:

 4599 22:59:26.740077  DQM0 = 45, DQM1 = 37

 4600 22:59:26.740650  DQ Delay:

 4601 22:59:26.743289  DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41

 4602 22:59:26.746739  DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =33

 4603 22:59:26.750255  DQ8 =25, DQ9 =33, DQ10 =33, DQ11 =25

 4604 22:59:26.753686  DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =49

 4605 22:59:26.754335  

 4606 22:59:26.754837  

 4607 22:59:26.755338  ==

 4608 22:59:26.757063  Dram Type= 6, Freq= 0, CH_1, rank 0

 4609 22:59:26.762943  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4610 22:59:26.763367  ==

 4611 22:59:26.763696  

 4612 22:59:26.764003  

 4613 22:59:26.764317  	TX Vref Scan disable

 4614 22:59:26.766789   == TX Byte 0 ==

 4615 22:59:26.769826  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 4616 22:59:26.776570  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 4617 22:59:26.777067   == TX Byte 1 ==

 4618 22:59:26.779854  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4619 22:59:26.786656  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4620 22:59:26.787082  ==

 4621 22:59:26.789708  Dram Type= 6, Freq= 0, CH_1, rank 0

 4622 22:59:26.793532  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4623 22:59:26.793957  ==

 4624 22:59:26.794293  

 4625 22:59:26.794726  

 4626 22:59:26.796384  	TX Vref Scan disable

 4627 22:59:26.799659   == TX Byte 0 ==

 4628 22:59:26.803333  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 4629 22:59:26.806340  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 4630 22:59:26.809950   == TX Byte 1 ==

 4631 22:59:26.812960  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4632 22:59:26.816057  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4633 22:59:26.816602  

 4634 22:59:26.816943  [DATLAT]

 4635 22:59:26.819854  Freq=600, CH1 RK0

 4636 22:59:26.820282  

 4637 22:59:26.822889  DATLAT Default: 0x9

 4638 22:59:26.823314  0, 0xFFFF, sum = 0

 4639 22:59:26.826512  1, 0xFFFF, sum = 0

 4640 22:59:26.826946  2, 0xFFFF, sum = 0

 4641 22:59:26.829573  3, 0xFFFF, sum = 0

 4642 22:59:26.830068  4, 0xFFFF, sum = 0

 4643 22:59:26.832570  5, 0xFFFF, sum = 0

 4644 22:59:26.833144  6, 0xFFFF, sum = 0

 4645 22:59:26.835707  7, 0xFFFF, sum = 0

 4646 22:59:26.836245  8, 0x0, sum = 1

 4647 22:59:26.839501  9, 0x0, sum = 2

 4648 22:59:26.840191  10, 0x0, sum = 3

 4649 22:59:26.842384  11, 0x0, sum = 4

 4650 22:59:26.842902  best_step = 9

 4651 22:59:26.843473  

 4652 22:59:26.844045  ==

 4653 22:59:26.845687  Dram Type= 6, Freq= 0, CH_1, rank 0

 4654 22:59:26.849011  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4655 22:59:26.849589  ==

 4656 22:59:26.852314  RX Vref Scan: 1

 4657 22:59:26.852924  

 4658 22:59:26.855722  RX Vref 0 -> 0, step: 1

 4659 22:59:26.856196  

 4660 22:59:26.856686  RX Delay -179 -> 252, step: 8

 4661 22:59:26.859433  

 4662 22:59:26.859872  Set Vref, RX VrefLevel [Byte0]: 45

 4663 22:59:26.862108                           [Byte1]: 57

 4664 22:59:26.866937  

 4665 22:59:26.867496  Final RX Vref Byte 0 = 45 to rank0

 4666 22:59:26.870331  Final RX Vref Byte 1 = 57 to rank0

 4667 22:59:26.874063  Final RX Vref Byte 0 = 45 to rank1

 4668 22:59:26.877082  Final RX Vref Byte 1 = 57 to rank1==

 4669 22:59:26.880202  Dram Type= 6, Freq= 0, CH_1, rank 0

 4670 22:59:26.886788  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4671 22:59:26.887388  ==

 4672 22:59:26.887743  DQS Delay:

 4673 22:59:26.890649  DQS0 = 0, DQS1 = 0

 4674 22:59:26.891071  DQM Delay:

 4675 22:59:26.891408  DQM0 = 47, DQM1 = 38

 4676 22:59:26.893710  DQ Delay:

 4677 22:59:26.896819  DQ0 =52, DQ1 =40, DQ2 =40, DQ3 =44

 4678 22:59:26.900332  DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =40

 4679 22:59:26.903477  DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28

 4680 22:59:26.906564  DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =48

 4681 22:59:26.907036  

 4682 22:59:26.907375  

 4683 22:59:26.913305  [DQSOSCAuto] RK0, (LSB)MR18= 0x4c31, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps

 4684 22:59:26.916422  CH1 RK0: MR19=808, MR18=4C31

 4685 22:59:26.923246  CH1_RK0: MR19=0x808, MR18=0x4C31, DQSOSC=395, MR23=63, INC=168, DEC=112

 4686 22:59:26.923982  

 4687 22:59:26.926729  ----->DramcWriteLeveling(PI) begin...

 4688 22:59:26.927213  ==

 4689 22:59:26.929718  Dram Type= 6, Freq= 0, CH_1, rank 1

 4690 22:59:26.933503  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4691 22:59:26.933992  ==

 4692 22:59:26.936774  Write leveling (Byte 0): 29 => 29

 4693 22:59:26.939479  Write leveling (Byte 1): 29 => 29

 4694 22:59:26.943115  DramcWriteLeveling(PI) end<-----

 4695 22:59:26.943955  

 4696 22:59:26.944507  ==

 4697 22:59:26.946576  Dram Type= 6, Freq= 0, CH_1, rank 1

 4698 22:59:26.949509  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4699 22:59:26.952891  ==

 4700 22:59:26.953385  [Gating] SW mode calibration

 4701 22:59:26.962776  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4702 22:59:26.966078  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4703 22:59:26.969470   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4704 22:59:26.975794   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4705 22:59:26.979460   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4706 22:59:26.982775   0  9 12 | B1->B0 | 3030 3333 | 1 0 | (1 0) (0 0)

 4707 22:59:26.989150   0  9 16 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 0)

 4708 22:59:26.992163   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4709 22:59:26.995787   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4710 22:59:27.001881   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4711 22:59:27.005605   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4712 22:59:27.008748   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4713 22:59:27.015396   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4714 22:59:27.018512   0 10 12 | B1->B0 | 3a3a 2626 | 0 0 | (0 0) (1 1)

 4715 22:59:27.021806   0 10 16 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)

 4716 22:59:27.028612   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4717 22:59:27.031488   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4718 22:59:27.038426   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4719 22:59:27.041675   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4720 22:59:27.044649   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4721 22:59:27.051017   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4722 22:59:27.054662   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4723 22:59:27.058031   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4724 22:59:27.064458   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4725 22:59:27.067916   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4726 22:59:27.070835   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4727 22:59:27.077508   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4728 22:59:27.080976   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4729 22:59:27.084579   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4730 22:59:27.091133   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4731 22:59:27.094299   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4732 22:59:27.097419   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4733 22:59:27.104198   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4734 22:59:27.107277   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4735 22:59:27.111069   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4736 22:59:27.117153   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4737 22:59:27.120188   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4738 22:59:27.124063   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 4739 22:59:27.130153   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4740 22:59:27.130581  Total UI for P1: 0, mck2ui 16

 4741 22:59:27.137048  best dqsien dly found for B0: ( 0, 13, 14)

 4742 22:59:27.137476  Total UI for P1: 0, mck2ui 16

 4743 22:59:27.139978  best dqsien dly found for B1: ( 0, 13, 12)

 4744 22:59:27.147176  best DQS0 dly(MCK, UI, PI) = (0, 13, 14)

 4745 22:59:27.150205  best DQS1 dly(MCK, UI, PI) = (0, 13, 12)

 4746 22:59:27.150773  

 4747 22:59:27.153773  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4748 22:59:27.156726  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4749 22:59:27.160415  [Gating] SW calibration Done

 4750 22:59:27.161049  ==

 4751 22:59:27.163041  Dram Type= 6, Freq= 0, CH_1, rank 1

 4752 22:59:27.166693  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4753 22:59:27.167252  ==

 4754 22:59:27.170171  RX Vref Scan: 0

 4755 22:59:27.170596  

 4756 22:59:27.170929  RX Vref 0 -> 0, step: 1

 4757 22:59:27.171249  

 4758 22:59:27.173044  RX Delay -230 -> 252, step: 16

 4759 22:59:27.179912  iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320

 4760 22:59:27.183399  iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320

 4761 22:59:27.186577  iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320

 4762 22:59:27.190032  iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320

 4763 22:59:27.193058  iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320

 4764 22:59:27.199603  iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320

 4765 22:59:27.203295  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4766 22:59:27.206406  iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320

 4767 22:59:27.209460  iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320

 4768 22:59:27.216238  iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320

 4769 22:59:27.219295  iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336

 4770 22:59:27.222981  iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336

 4771 22:59:27.226080  iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336

 4772 22:59:27.232878  iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336

 4773 22:59:27.235941  iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336

 4774 22:59:27.239035  iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336

 4775 22:59:27.239462  ==

 4776 22:59:27.242558  Dram Type= 6, Freq= 0, CH_1, rank 1

 4777 22:59:27.245654  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4778 22:59:27.248839  ==

 4779 22:59:27.249422  DQS Delay:

 4780 22:59:27.249785  DQS0 = 0, DQS1 = 0

 4781 22:59:27.252490  DQM Delay:

 4782 22:59:27.253220  DQM0 = 43, DQM1 = 39

 4783 22:59:27.255563  DQ Delay:

 4784 22:59:27.258717  DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41

 4785 22:59:27.259199  DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41

 4786 22:59:27.262134  DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33

 4787 22:59:27.268474  DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49

 4788 22:59:27.269168  

 4789 22:59:27.269684  

 4790 22:59:27.270148  ==

 4791 22:59:27.271902  Dram Type= 6, Freq= 0, CH_1, rank 1

 4792 22:59:27.275488  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4793 22:59:27.275922  ==

 4794 22:59:27.276264  

 4795 22:59:27.276642  

 4796 22:59:27.279112  	TX Vref Scan disable

 4797 22:59:27.279542   == TX Byte 0 ==

 4798 22:59:27.285542  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4799 22:59:27.288562  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4800 22:59:27.289080   == TX Byte 1 ==

 4801 22:59:27.294949  Update DQ  dly =573 (2 ,1, 29)  DQ  OEN =(1 ,6)

 4802 22:59:27.298523  Update DQM dly =573 (2 ,1, 29)  DQM OEN =(1 ,6)

 4803 22:59:27.299098  ==

 4804 22:59:27.301552  Dram Type= 6, Freq= 0, CH_1, rank 1

 4805 22:59:27.305478  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4806 22:59:27.305908  ==

 4807 22:59:27.306247  

 4808 22:59:27.308544  

 4809 22:59:27.308999  	TX Vref Scan disable

 4810 22:59:27.312256   == TX Byte 0 ==

 4811 22:59:27.315397  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4812 22:59:27.321946  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4813 22:59:27.322375   == TX Byte 1 ==

 4814 22:59:27.325051  Update DQ  dly =573 (2 ,1, 29)  DQ  OEN =(1 ,6)

 4815 22:59:27.331773  Update DQM dly =573 (2 ,1, 29)  DQM OEN =(1 ,6)

 4816 22:59:27.332200  

 4817 22:59:27.332575  [DATLAT]

 4818 22:59:27.333011  Freq=600, CH1 RK1

 4819 22:59:27.333331  

 4820 22:59:27.334652  DATLAT Default: 0x9

 4821 22:59:27.337835  0, 0xFFFF, sum = 0

 4822 22:59:27.338271  1, 0xFFFF, sum = 0

 4823 22:59:27.341517  2, 0xFFFF, sum = 0

 4824 22:59:27.341950  3, 0xFFFF, sum = 0

 4825 22:59:27.344841  4, 0xFFFF, sum = 0

 4826 22:59:27.345275  5, 0xFFFF, sum = 0

 4827 22:59:27.348473  6, 0xFFFF, sum = 0

 4828 22:59:27.348945  7, 0xFFFF, sum = 0

 4829 22:59:27.351545  8, 0x0, sum = 1

 4830 22:59:27.351980  9, 0x0, sum = 2

 4831 22:59:27.354576  10, 0x0, sum = 3

 4832 22:59:27.355014  11, 0x0, sum = 4

 4833 22:59:27.355364  best_step = 9

 4834 22:59:27.355682  

 4835 22:59:27.357762  ==

 4836 22:59:27.361312  Dram Type= 6, Freq= 0, CH_1, rank 1

 4837 22:59:27.364287  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4838 22:59:27.364781  ==

 4839 22:59:27.365372  RX Vref Scan: 0

 4840 22:59:27.365844  

 4841 22:59:27.367827  RX Vref 0 -> 0, step: 1

 4842 22:59:27.368312  

 4843 22:59:27.370926  RX Delay -179 -> 252, step: 8

 4844 22:59:27.377765  iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296

 4845 22:59:27.381355  iDelay=205, Bit 1, Center 40 (-107 ~ 188) 296

 4846 22:59:27.384339  iDelay=205, Bit 2, Center 32 (-115 ~ 180) 296

 4847 22:59:27.387570  iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296

 4848 22:59:27.391399  iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304

 4849 22:59:27.398072  iDelay=205, Bit 5, Center 56 (-91 ~ 204) 296

 4850 22:59:27.400825  iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296

 4851 22:59:27.404224  iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304

 4852 22:59:27.407772  iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312

 4853 22:59:27.411059  iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312

 4854 22:59:27.417204  iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312

 4855 22:59:27.420795  iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304

 4856 22:59:27.423890  iDelay=205, Bit 12, Center 48 (-107 ~ 204) 312

 4857 22:59:27.430698  iDelay=205, Bit 13, Center 48 (-107 ~ 204) 312

 4858 22:59:27.433830  iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304

 4859 22:59:27.437271  iDelay=205, Bit 15, Center 48 (-107 ~ 204) 312

 4860 22:59:27.437693  ==

 4861 22:59:27.440611  Dram Type= 6, Freq= 0, CH_1, rank 1

 4862 22:59:27.443638  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4863 22:59:27.444058  ==

 4864 22:59:27.447293  DQS Delay:

 4865 22:59:27.447710  DQS0 = 0, DQS1 = 0

 4866 22:59:27.450551  DQM Delay:

 4867 22:59:27.451101  DQM0 = 45, DQM1 = 38

 4868 22:59:27.451437  DQ Delay:

 4869 22:59:27.453953  DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40

 4870 22:59:27.457191  DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44

 4871 22:59:27.460219  DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28

 4872 22:59:27.463377  DQ12 =48, DQ13 =48, DQ14 =44, DQ15 =48

 4873 22:59:27.463459  

 4874 22:59:27.463524  

 4875 22:59:27.473059  [DQSOSCAuto] RK1, (LSB)MR18= 0x2f23, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 400 ps

 4876 22:59:27.476554  CH1 RK1: MR19=808, MR18=2F23

 4877 22:59:27.482958  CH1_RK1: MR19=0x808, MR18=0x2F23, DQSOSC=400, MR23=63, INC=163, DEC=109

 4878 22:59:27.483042  [RxdqsGatingPostProcess] freq 600

 4879 22:59:27.489531  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 4880 22:59:27.493126  Pre-setting of DQS Precalculation

 4881 22:59:27.496141  [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9

 4882 22:59:27.506325  sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5

 4883 22:59:27.512793  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 4884 22:59:27.512877  

 4885 22:59:27.512943  

 4886 22:59:27.516406  [Calibration Summary] 1200 Mbps

 4887 22:59:27.516534  CH 0, Rank 0

 4888 22:59:27.519803  SW Impedance     : PASS

 4889 22:59:27.519886  DUTY Scan        : NO K

 4890 22:59:27.522785  ZQ Calibration   : PASS

 4891 22:59:27.525934  Jitter Meter     : NO K

 4892 22:59:27.526018  CBT Training     : PASS

 4893 22:59:27.529873  Write leveling   : PASS

 4894 22:59:27.532772  RX DQS gating    : PASS

 4895 22:59:27.532855  RX DQ/DQS(RDDQC) : PASS

 4896 22:59:27.535865  TX DQ/DQS        : PASS

 4897 22:59:27.539722  RX DATLAT        : PASS

 4898 22:59:27.539847  RX DQ/DQS(Engine): PASS

 4899 22:59:27.542814  TX OE            : NO K

 4900 22:59:27.542898  All Pass.

 4901 22:59:27.542964  

 4902 22:59:27.546046  CH 0, Rank 1

 4903 22:59:27.546165  SW Impedance     : PASS

 4904 22:59:27.549030  DUTY Scan        : NO K

 4905 22:59:27.552706  ZQ Calibration   : PASS

 4906 22:59:27.552779  Jitter Meter     : NO K

 4907 22:59:27.555810  CBT Training     : PASS

 4908 22:59:27.559514  Write leveling   : PASS

 4909 22:59:27.559620  RX DQS gating    : PASS

 4910 22:59:27.562505  RX DQ/DQS(RDDQC) : PASS

 4911 22:59:27.565737  TX DQ/DQS        : PASS

 4912 22:59:27.565820  RX DATLAT        : PASS

 4913 22:59:27.569191  RX DQ/DQS(Engine): PASS

 4914 22:59:27.572306  TX OE            : NO K

 4915 22:59:27.572415  All Pass.

 4916 22:59:27.572507  

 4917 22:59:27.572643  CH 1, Rank 0

 4918 22:59:27.575886  SW Impedance     : PASS

 4919 22:59:27.578765  DUTY Scan        : NO K

 4920 22:59:27.578849  ZQ Calibration   : PASS

 4921 22:59:27.582272  Jitter Meter     : NO K

 4922 22:59:27.582356  CBT Training     : PASS

 4923 22:59:27.586066  Write leveling   : PASS

 4924 22:59:27.588727  RX DQS gating    : PASS

 4925 22:59:27.588811  RX DQ/DQS(RDDQC) : PASS

 4926 22:59:27.592194  TX DQ/DQS        : PASS

 4927 22:59:27.595771  RX DATLAT        : PASS

 4928 22:59:27.595854  RX DQ/DQS(Engine): PASS

 4929 22:59:27.598591  TX OE            : NO K

 4930 22:59:27.598674  All Pass.

 4931 22:59:27.598739  

 4932 22:59:27.602192  CH 1, Rank 1

 4933 22:59:27.602275  SW Impedance     : PASS

 4934 22:59:27.605863  DUTY Scan        : NO K

 4935 22:59:27.608798  ZQ Calibration   : PASS

 4936 22:59:27.608895  Jitter Meter     : NO K

 4937 22:59:27.611731  CBT Training     : PASS

 4938 22:59:27.615091  Write leveling   : PASS

 4939 22:59:27.615241  RX DQS gating    : PASS

 4940 22:59:27.618820  RX DQ/DQS(RDDQC) : PASS

 4941 22:59:27.621840  TX DQ/DQS        : PASS

 4942 22:59:27.621940  RX DATLAT        : PASS

 4943 22:59:27.625377  RX DQ/DQS(Engine): PASS

 4944 22:59:27.628384  TX OE            : NO K

 4945 22:59:27.628509  All Pass.

 4946 22:59:27.628622  

 4947 22:59:27.631538  DramC Write-DBI off

 4948 22:59:27.631615  	PER_BANK_REFRESH: Hybrid Mode

 4949 22:59:27.635182  TX_TRACKING: ON

 4950 22:59:27.641482  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1

 4951 22:59:27.648349  [FAST_K] Save calibration result to emmc

 4952 22:59:27.651440  dramc_set_vcore_voltage set vcore to 662500

 4953 22:59:27.651539  Read voltage for 933, 3

 4954 22:59:27.655138  Vio18 = 0

 4955 22:59:27.655235  Vcore = 662500

 4956 22:59:27.655328  Vdram = 0

 4957 22:59:27.658079  Vddq = 0

 4958 22:59:27.658174  Vmddr = 0

 4959 22:59:27.661271  [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0

 4960 22:59:27.668200  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 4961 22:59:27.671031  MEM_TYPE=3, freq_sel=17

 4962 22:59:27.674248  sv_algorithm_assistance_LP4_1600 

 4963 22:59:27.677952  ============ PULL DRAM RESETB DOWN ============

 4964 22:59:27.681313  ========== PULL DRAM RESETB DOWN end =========

 4965 22:59:27.687880  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 4966 22:59:27.691000  =================================== 

 4967 22:59:27.691112  LPDDR4 DRAM CONFIGURATION

 4968 22:59:27.694587  =================================== 

 4969 22:59:27.697456  EX_ROW_EN[0]    = 0x0

 4970 22:59:27.701072  EX_ROW_EN[1]    = 0x0

 4971 22:59:27.701173  LP4Y_EN      = 0x0

 4972 22:59:27.704082  WORK_FSP     = 0x0

 4973 22:59:27.704184  WL           = 0x3

 4974 22:59:27.707589  RL           = 0x3

 4975 22:59:27.707688  BL           = 0x2

 4976 22:59:27.710573  RPST         = 0x0

 4977 22:59:27.710684  RD_PRE       = 0x0

 4978 22:59:27.714228  WR_PRE       = 0x1

 4979 22:59:27.714333  WR_PST       = 0x0

 4980 22:59:27.717171  DBI_WR       = 0x0

 4981 22:59:27.717269  DBI_RD       = 0x0

 4982 22:59:27.720704  OTF          = 0x1

 4983 22:59:27.724345  =================================== 

 4984 22:59:27.727459  =================================== 

 4985 22:59:27.727561  ANA top config

 4986 22:59:27.730689  =================================== 

 4987 22:59:27.733709  DLL_ASYNC_EN            =  0

 4988 22:59:27.737292  ALL_SLAVE_EN            =  1

 4989 22:59:27.740445  NEW_RANK_MODE           =  1

 4990 22:59:27.740588  DLL_IDLE_MODE           =  1

 4991 22:59:27.743551  LP45_APHY_COMB_EN       =  1

 4992 22:59:27.747320  TX_ODT_DIS              =  1

 4993 22:59:27.750482  NEW_8X_MODE             =  1

 4994 22:59:27.753446  =================================== 

 4995 22:59:27.757176  =================================== 

 4996 22:59:27.760232  data_rate                  = 1866

 4997 22:59:27.760336  CKR                        = 1

 4998 22:59:27.763839  DQ_P2S_RATIO               = 8

 4999 22:59:27.766893  =================================== 

 5000 22:59:27.769965  CA_P2S_RATIO               = 8

 5001 22:59:27.773720  DQ_CA_OPEN                 = 0

 5002 22:59:27.776654  DQ_SEMI_OPEN               = 0

 5003 22:59:27.780340  CA_SEMI_OPEN               = 0

 5004 22:59:27.780450  CA_FULL_RATE               = 0

 5005 22:59:27.783457  DQ_CKDIV4_EN               = 1

 5006 22:59:27.786923  CA_CKDIV4_EN               = 1

 5007 22:59:27.789843  CA_PREDIV_EN               = 0

 5008 22:59:27.793357  PH8_DLY                    = 0

 5009 22:59:27.796275  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 5010 22:59:27.796359  DQ_AAMCK_DIV               = 4

 5011 22:59:27.799745  CA_AAMCK_DIV               = 4

 5012 22:59:27.803310  CA_ADMCK_DIV               = 4

 5013 22:59:27.806209  DQ_TRACK_CA_EN             = 0

 5014 22:59:27.809742  CA_PICK                    = 933

 5015 22:59:27.812713  CA_MCKIO                   = 933

 5016 22:59:27.816204  MCKIO_SEMI                 = 0

 5017 22:59:27.816280  PLL_FREQ                   = 3732

 5018 22:59:27.819774  DQ_UI_PI_RATIO             = 32

 5019 22:59:27.822725  CA_UI_PI_RATIO             = 0

 5020 22:59:27.826099  =================================== 

 5021 22:59:27.829829  =================================== 

 5022 22:59:27.832861  memory_type:LPDDR4         

 5023 22:59:27.835987  GP_NUM     : 10       

 5024 22:59:27.836073  SRAM_EN    : 1       

 5025 22:59:27.839801  MD32_EN    : 0       

 5026 22:59:27.842871  =================================== 

 5027 22:59:27.842956  [ANA_INIT] >>>>>>>>>>>>>> 

 5028 22:59:27.845908  <<<<<< [CONFIGURE PHASE]: ANA_TX

 5029 22:59:27.848974  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 5030 22:59:27.852660  =================================== 

 5031 22:59:27.855749  data_rate = 1866,PCW = 0X8f00

 5032 22:59:27.858908  =================================== 

 5033 22:59:27.862682  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 5034 22:59:27.868704  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 5035 22:59:27.875412  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 5036 22:59:27.878620  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 5037 22:59:27.882041  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 5038 22:59:27.885121  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 5039 22:59:27.888799  [ANA_INIT] flow start 

 5040 22:59:27.888881  [ANA_INIT] PLL >>>>>>>> 

 5041 22:59:27.891747  [ANA_INIT] PLL <<<<<<<< 

 5042 22:59:27.895303  [ANA_INIT] MIDPI >>>>>>>> 

 5043 22:59:27.898306  [ANA_INIT] MIDPI <<<<<<<< 

 5044 22:59:27.898388  [ANA_INIT] DLL >>>>>>>> 

 5045 22:59:27.901999  [ANA_INIT] flow end 

 5046 22:59:27.905420  ============ LP4 DIFF to SE enter ============

 5047 22:59:27.908403  ============ LP4 DIFF to SE exit  ============

 5048 22:59:27.911812  [ANA_INIT] <<<<<<<<<<<<< 

 5049 22:59:27.915390  [Flow] Enable top DCM control >>>>> 

 5050 22:59:27.918477  [Flow] Enable top DCM control <<<<< 

 5051 22:59:27.921842  Enable DLL master slave shuffle 

 5052 22:59:27.928479  ============================================================== 

 5053 22:59:27.928624  Gating Mode config

 5054 22:59:27.935246  ============================================================== 

 5055 22:59:27.935329  Config description: 

 5056 22:59:27.945078  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 5057 22:59:27.951258  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 5058 22:59:27.958148  SELPH_MODE            0: By rank         1: By Phase 

 5059 22:59:27.961135  ============================================================== 

 5060 22:59:27.964349  GAT_TRACK_EN                 =  1

 5061 22:59:27.967560  RX_GATING_MODE               =  2

 5062 22:59:27.971164  RX_GATING_TRACK_MODE         =  2

 5063 22:59:27.974257  SELPH_MODE                   =  1

 5064 22:59:27.977963  PICG_EARLY_EN                =  1

 5065 22:59:27.981060  VALID_LAT_VALUE              =  1

 5066 22:59:27.987801  ============================================================== 

 5067 22:59:27.990929  Enter into Gating configuration >>>> 

 5068 22:59:27.994518  Exit from Gating configuration <<<< 

 5069 22:59:27.997561  Enter into  DVFS_PRE_config >>>>> 

 5070 22:59:28.007644  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 5071 22:59:28.010529  Exit from  DVFS_PRE_config <<<<< 

 5072 22:59:28.013997  Enter into PICG configuration >>>> 

 5073 22:59:28.017653  Exit from PICG configuration <<<< 

 5074 22:59:28.020392  [RX_INPUT] configuration >>>>> 

 5075 22:59:28.020500  [RX_INPUT] configuration <<<<< 

 5076 22:59:28.027450  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 5077 22:59:28.033460  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 5078 22:59:28.040417  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 5079 22:59:28.043340  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 5080 22:59:28.050063  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 5081 22:59:28.056244  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 5082 22:59:28.059869  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 5083 22:59:28.066115  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 5084 22:59:28.069819  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 5085 22:59:28.072876  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 5086 22:59:28.076459  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 5087 22:59:28.082835  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 5088 22:59:28.085954  =================================== 

 5089 22:59:28.089620  LPDDR4 DRAM CONFIGURATION

 5090 22:59:28.092744  =================================== 

 5091 22:59:28.092834  EX_ROW_EN[0]    = 0x0

 5092 22:59:28.095733  EX_ROW_EN[1]    = 0x0

 5093 22:59:28.095808  LP4Y_EN      = 0x0

 5094 22:59:28.099364  WORK_FSP     = 0x0

 5095 22:59:28.099441  WL           = 0x3

 5096 22:59:28.102874  RL           = 0x3

 5097 22:59:28.102947  BL           = 0x2

 5098 22:59:28.105748  RPST         = 0x0

 5099 22:59:28.105862  RD_PRE       = 0x0

 5100 22:59:28.109240  WR_PRE       = 0x1

 5101 22:59:28.109322  WR_PST       = 0x0

 5102 22:59:28.112373  DBI_WR       = 0x0

 5103 22:59:28.112484  DBI_RD       = 0x0

 5104 22:59:28.115823  OTF          = 0x1

 5105 22:59:28.119294  =================================== 

 5106 22:59:28.122461  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 5107 22:59:28.125938  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 5108 22:59:28.132443  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 5109 22:59:28.135921  =================================== 

 5110 22:59:28.138724  LPDDR4 DRAM CONFIGURATION

 5111 22:59:28.142368  =================================== 

 5112 22:59:28.142451  EX_ROW_EN[0]    = 0x10

 5113 22:59:28.145357  EX_ROW_EN[1]    = 0x0

 5114 22:59:28.145439  LP4Y_EN      = 0x0

 5115 22:59:28.149123  WORK_FSP     = 0x0

 5116 22:59:28.149206  WL           = 0x3

 5117 22:59:28.152175  RL           = 0x3

 5118 22:59:28.152291  BL           = 0x2

 5119 22:59:28.155349  RPST         = 0x0

 5120 22:59:28.155432  RD_PRE       = 0x0

 5121 22:59:28.158989  WR_PRE       = 0x1

 5122 22:59:28.159072  WR_PST       = 0x0

 5123 22:59:28.162025  DBI_WR       = 0x0

 5124 22:59:28.162108  DBI_RD       = 0x0

 5125 22:59:28.165171  OTF          = 0x1

 5126 22:59:28.168791  =================================== 

 5127 22:59:28.175265  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 5128 22:59:28.178811  nWR fixed to 30

 5129 22:59:28.181960  [ModeRegInit_LP4] CH0 RK0

 5130 22:59:28.182045  [ModeRegInit_LP4] CH0 RK1

 5131 22:59:28.185680  [ModeRegInit_LP4] CH1 RK0

 5132 22:59:28.188704  [ModeRegInit_LP4] CH1 RK1

 5133 22:59:28.188788  match AC timing 9

 5134 22:59:28.195157  dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1

 5135 22:59:28.198639  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 5136 22:59:28.201810  [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10

 5137 22:59:28.208387  [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21

 5138 22:59:28.211378  [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)

 5139 22:59:28.211462  ==

 5140 22:59:28.214869  Dram Type= 6, Freq= 0, CH_0, rank 0

 5141 22:59:28.218549  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5142 22:59:28.218690  ==

 5143 22:59:28.224938  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5144 22:59:28.231611  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33

 5145 22:59:28.234660  [CA 0] Center 37 (7~68) winsize 62

 5146 22:59:28.238279  [CA 1] Center 37 (7~68) winsize 62

 5147 22:59:28.241793  [CA 2] Center 34 (4~65) winsize 62

 5148 22:59:28.244908  [CA 3] Center 34 (4~65) winsize 62

 5149 22:59:28.247997  [CA 4] Center 33 (3~64) winsize 62

 5150 22:59:28.251778  [CA 5] Center 33 (3~63) winsize 61

 5151 22:59:28.251866  

 5152 22:59:28.254827  [CmdBusTrainingLP45] Vref(ca) range 1: 33

 5153 22:59:28.254910  

 5154 22:59:28.257976  [CATrainingPosCal] consider 1 rank data

 5155 22:59:28.261586  u2DelayCellTimex100 = 270/100 ps

 5156 22:59:28.264739  CA0 delay=37 (7~68),Diff = 4 PI (24 cell)

 5157 22:59:28.268360  CA1 delay=37 (7~68),Diff = 4 PI (24 cell)

 5158 22:59:28.271416  CA2 delay=34 (4~65),Diff = 1 PI (6 cell)

 5159 22:59:28.274548  CA3 delay=34 (4~65),Diff = 1 PI (6 cell)

 5160 22:59:28.278275  CA4 delay=33 (3~64),Diff = 0 PI (0 cell)

 5161 22:59:28.284422  CA5 delay=33 (3~63),Diff = 0 PI (0 cell)

 5162 22:59:28.284507  

 5163 22:59:28.288085  CA PerBit enable=1, Macro0, CA PI delay=33

 5164 22:59:28.288168  

 5165 22:59:28.291202  [CBTSetCACLKResult] CA Dly = 33

 5166 22:59:28.291284  CS Dly: 7 (0~38)

 5167 22:59:28.291350  ==

 5168 22:59:28.294989  Dram Type= 6, Freq= 0, CH_0, rank 1

 5169 22:59:28.297826  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5170 22:59:28.301204  ==

 5171 22:59:28.304410  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5172 22:59:28.311092  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5173 22:59:28.314059  [CA 0] Center 37 (7~68) winsize 62

 5174 22:59:28.317627  [CA 1] Center 37 (7~68) winsize 62

 5175 22:59:28.321061  [CA 2] Center 34 (4~65) winsize 62

 5176 22:59:28.324147  [CA 3] Center 34 (4~65) winsize 62

 5177 22:59:28.327171  [CA 4] Center 33 (3~64) winsize 62

 5178 22:59:28.330576  [CA 5] Center 33 (3~63) winsize 61

 5179 22:59:28.330677  

 5180 22:59:28.334186  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5181 22:59:28.334272  

 5182 22:59:28.337288  [CATrainingPosCal] consider 2 rank data

 5183 22:59:28.340778  u2DelayCellTimex100 = 270/100 ps

 5184 22:59:28.343627  CA0 delay=37 (7~68),Diff = 4 PI (24 cell)

 5185 22:59:28.347059  CA1 delay=37 (7~68),Diff = 4 PI (24 cell)

 5186 22:59:28.353908  CA2 delay=34 (4~65),Diff = 1 PI (6 cell)

 5187 22:59:28.357102  CA3 delay=34 (4~65),Diff = 1 PI (6 cell)

 5188 22:59:28.360641  CA4 delay=33 (3~64),Diff = 0 PI (0 cell)

 5189 22:59:28.363714  CA5 delay=33 (3~63),Diff = 0 PI (0 cell)

 5190 22:59:28.363796  

 5191 22:59:28.366821  CA PerBit enable=1, Macro0, CA PI delay=33

 5192 22:59:28.366905  

 5193 22:59:28.370561  [CBTSetCACLKResult] CA Dly = 33

 5194 22:59:28.370644  CS Dly: 7 (0~39)

 5195 22:59:28.370710  

 5196 22:59:28.373612  ----->DramcWriteLeveling(PI) begin...

 5197 22:59:28.376731  ==

 5198 22:59:28.379920  Dram Type= 6, Freq= 0, CH_0, rank 0

 5199 22:59:28.383503  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5200 22:59:28.383587  ==

 5201 22:59:28.387099  Write leveling (Byte 0): 33 => 33

 5202 22:59:28.390120  Write leveling (Byte 1): 30 => 30

 5203 22:59:28.393282  DramcWriteLeveling(PI) end<-----

 5204 22:59:28.393365  

 5205 22:59:28.393430  ==

 5206 22:59:28.396997  Dram Type= 6, Freq= 0, CH_0, rank 0

 5207 22:59:28.400065  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5208 22:59:28.400149  ==

 5209 22:59:28.403668  [Gating] SW mode calibration

 5210 22:59:28.410382  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5211 22:59:28.416794  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5212 22:59:28.419873   0 14  0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)

 5213 22:59:28.423526   0 14  4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)

 5214 22:59:28.426447   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5215 22:59:28.433027   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5216 22:59:28.436406   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5217 22:59:28.443097   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5218 22:59:28.446565   0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5219 22:59:28.449564   0 14 28 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)

 5220 22:59:28.456227   0 15  0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)

 5221 22:59:28.459427   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5222 22:59:28.462948   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5223 22:59:28.469377   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5224 22:59:28.472460   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5225 22:59:28.476334   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5226 22:59:28.482531   0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5227 22:59:28.485684   0 15 28 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)

 5228 22:59:28.489423   1  0  0 | B1->B0 | 2d2c 3f3f | 1 0 | (0 0) (0 0)

 5229 22:59:28.495914   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5230 22:59:28.498987   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5231 22:59:28.502709   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5232 22:59:28.505683   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5233 22:59:28.512633   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5234 22:59:28.515799   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5235 22:59:28.519244   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5236 22:59:28.525751   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 5237 22:59:28.528696   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5238 22:59:28.532056   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5239 22:59:28.539011   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5240 22:59:28.541835   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5241 22:59:28.548509   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5242 22:59:28.552024   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5243 22:59:28.555010   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5244 22:59:28.561602   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5245 22:59:28.564744   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5246 22:59:28.568467   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5247 22:59:28.574719   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5248 22:59:28.578481   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5249 22:59:28.581492   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5250 22:59:28.585319   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5251 22:59:28.591490   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 5252 22:59:28.594996   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 5253 22:59:28.598111  Total UI for P1: 0, mck2ui 16

 5254 22:59:28.601162  best dqsien dly found for B0: ( 1,  2, 28)

 5255 22:59:28.604812   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 5256 22:59:28.611360   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5257 22:59:28.614447  Total UI for P1: 0, mck2ui 16

 5258 22:59:28.617967  best dqsien dly found for B1: ( 1,  3,  2)

 5259 22:59:28.620939  best DQS0 dly(MCK, UI, PI) = (1, 2, 28)

 5260 22:59:28.624430  best DQS1 dly(MCK, UI, PI) = (1, 3, 2)

 5261 22:59:28.624509  

 5262 22:59:28.627632  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)

 5263 22:59:28.631198  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)

 5264 22:59:28.634272  [Gating] SW calibration Done

 5265 22:59:28.634359  ==

 5266 22:59:28.637746  Dram Type= 6, Freq= 0, CH_0, rank 0

 5267 22:59:28.640622  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5268 22:59:28.640705  ==

 5269 22:59:28.644109  RX Vref Scan: 0

 5270 22:59:28.644218  

 5271 22:59:28.647624  RX Vref 0 -> 0, step: 1

 5272 22:59:28.647766  

 5273 22:59:28.647865  RX Delay -80 -> 252, step: 8

 5274 22:59:28.654314  iDelay=208, Bit 0, Center 99 (0 ~ 199) 200

 5275 22:59:28.657177  iDelay=208, Bit 1, Center 99 (0 ~ 199) 200

 5276 22:59:28.660658  iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200

 5277 22:59:28.663721  iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200

 5278 22:59:28.667441  iDelay=208, Bit 4, Center 99 (0 ~ 199) 200

 5279 22:59:28.670595  iDelay=208, Bit 5, Center 91 (-8 ~ 191) 200

 5280 22:59:28.677236  iDelay=208, Bit 6, Center 107 (8 ~ 207) 200

 5281 22:59:28.680374  iDelay=208, Bit 7, Center 107 (8 ~ 207) 200

 5282 22:59:28.683484  iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192

 5283 22:59:28.687169  iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184

 5284 22:59:28.690334  iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192

 5285 22:59:28.696608  iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192

 5286 22:59:28.700133  iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200

 5287 22:59:28.703213  iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200

 5288 22:59:28.706910  iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200

 5289 22:59:28.713109  iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200

 5290 22:59:28.713192  ==

 5291 22:59:28.716637  Dram Type= 6, Freq= 0, CH_0, rank 0

 5292 22:59:28.719570  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5293 22:59:28.719653  ==

 5294 22:59:28.719718  DQS Delay:

 5295 22:59:28.723132  DQS0 = 0, DQS1 = 0

 5296 22:59:28.723214  DQM Delay:

 5297 22:59:28.726175  DQM0 = 98, DQM1 = 85

 5298 22:59:28.726258  DQ Delay:

 5299 22:59:28.729913  DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91

 5300 22:59:28.732817  DQ4 =99, DQ5 =91, DQ6 =107, DQ7 =107

 5301 22:59:28.736346  DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79

 5302 22:59:28.739365  DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91

 5303 22:59:28.739448  

 5304 22:59:28.739512  

 5305 22:59:28.739572  ==

 5306 22:59:28.742988  Dram Type= 6, Freq= 0, CH_0, rank 0

 5307 22:59:28.746616  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5308 22:59:28.746704  ==

 5309 22:59:28.749804  

 5310 22:59:28.749886  

 5311 22:59:28.749952  	TX Vref Scan disable

 5312 22:59:28.752667   == TX Byte 0 ==

 5313 22:59:28.756134  Update DQ  dly =716 (2 ,6, 12)  DQ  OEN =(2 ,3)

 5314 22:59:28.759137  Update DQM dly =716 (2 ,6, 12)  DQM OEN =(2 ,3)

 5315 22:59:28.762816   == TX Byte 1 ==

 5316 22:59:28.765652  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5317 22:59:28.769399  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5318 22:59:28.769482  ==

 5319 22:59:28.772386  Dram Type= 6, Freq= 0, CH_0, rank 0

 5320 22:59:28.778937  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5321 22:59:28.779022  ==

 5322 22:59:28.779094  

 5323 22:59:28.779159  

 5324 22:59:28.782582  	TX Vref Scan disable

 5325 22:59:28.782665   == TX Byte 0 ==

 5326 22:59:28.788766  Update DQ  dly =715 (2 ,6, 11)  DQ  OEN =(2 ,3)

 5327 22:59:28.791925  Update DQM dly =715 (2 ,6, 11)  DQM OEN =(2 ,3)

 5328 22:59:28.792008   == TX Byte 1 ==

 5329 22:59:28.798808  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5330 22:59:28.801759  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5331 22:59:28.801842  

 5332 22:59:28.801907  [DATLAT]

 5333 22:59:28.805366  Freq=933, CH0 RK0

 5334 22:59:28.805449  

 5335 22:59:28.805513  DATLAT Default: 0xd

 5336 22:59:28.808408  0, 0xFFFF, sum = 0

 5337 22:59:28.808492  1, 0xFFFF, sum = 0

 5338 22:59:28.812176  2, 0xFFFF, sum = 0

 5339 22:59:28.812263  3, 0xFFFF, sum = 0

 5340 22:59:28.815110  4, 0xFFFF, sum = 0

 5341 22:59:28.818324  5, 0xFFFF, sum = 0

 5342 22:59:28.818410  6, 0xFFFF, sum = 0

 5343 22:59:28.821975  7, 0xFFFF, sum = 0

 5344 22:59:28.822059  8, 0xFFFF, sum = 0

 5345 22:59:28.824852  9, 0xFFFF, sum = 0

 5346 22:59:28.824935  10, 0x0, sum = 1

 5347 22:59:28.828433  11, 0x0, sum = 2

 5348 22:59:28.828526  12, 0x0, sum = 3

 5349 22:59:28.831431  13, 0x0, sum = 4

 5350 22:59:28.831516  best_step = 11

 5351 22:59:28.831581  

 5352 22:59:28.831640  ==

 5353 22:59:28.834978  Dram Type= 6, Freq= 0, CH_0, rank 0

 5354 22:59:28.838099  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5355 22:59:28.838183  ==

 5356 22:59:28.841611  RX Vref Scan: 1

 5357 22:59:28.841693  

 5358 22:59:28.844533  RX Vref 0 -> 0, step: 1

 5359 22:59:28.844629  

 5360 22:59:28.844694  RX Delay -61 -> 252, step: 4

 5361 22:59:28.844755  

 5362 22:59:28.848054  Set Vref, RX VrefLevel [Byte0]: 60

 5363 22:59:28.851615                           [Byte1]: 49

 5364 22:59:28.856322  

 5365 22:59:28.856404  Final RX Vref Byte 0 = 60 to rank0

 5366 22:59:28.859327  Final RX Vref Byte 1 = 49 to rank0

 5367 22:59:28.862938  Final RX Vref Byte 0 = 60 to rank1

 5368 22:59:28.865727  Final RX Vref Byte 1 = 49 to rank1==

 5369 22:59:28.869285  Dram Type= 6, Freq= 0, CH_0, rank 0

 5370 22:59:28.876062  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5371 22:59:28.876146  ==

 5372 22:59:28.876210  DQS Delay:

 5373 22:59:28.879180  DQS0 = 0, DQS1 = 0

 5374 22:59:28.879261  DQM Delay:

 5375 22:59:28.879324  DQM0 = 97, DQM1 = 85

 5376 22:59:28.882251  DQ Delay:

 5377 22:59:28.885984  DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =92

 5378 22:59:28.889104  DQ4 =98, DQ5 =88, DQ6 =108, DQ7 =106

 5379 22:59:28.892251  DQ8 =76, DQ9 =74, DQ10 =86, DQ11 =78

 5380 22:59:28.895914  DQ12 =90, DQ13 =90, DQ14 =98, DQ15 =94

 5381 22:59:28.895996  

 5382 22:59:28.896059  

 5383 22:59:28.902138  [DQSOSCAuto] RK0, (LSB)MR18= 0x2c12, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 408 ps

 5384 22:59:28.905457  CH0 RK0: MR19=505, MR18=2C12

 5385 22:59:28.912049  CH0_RK0: MR19=0x505, MR18=0x2C12, DQSOSC=408, MR23=63, INC=65, DEC=43

 5386 22:59:28.912130  

 5387 22:59:28.915557  ----->DramcWriteLeveling(PI) begin...

 5388 22:59:28.915639  ==

 5389 22:59:28.918800  Dram Type= 6, Freq= 0, CH_0, rank 1

 5390 22:59:28.921914  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5391 22:59:28.921996  ==

 5392 22:59:28.924973  Write leveling (Byte 0): 33 => 33

 5393 22:59:28.928545  Write leveling (Byte 1): 32 => 32

 5394 22:59:28.932205  DramcWriteLeveling(PI) end<-----

 5395 22:59:28.932286  

 5396 22:59:28.932348  ==

 5397 22:59:28.935356  Dram Type= 6, Freq= 0, CH_0, rank 1

 5398 22:59:28.941826  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5399 22:59:28.941907  ==

 5400 22:59:28.941971  [Gating] SW mode calibration

 5401 22:59:28.951766  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5402 22:59:28.954728  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5403 22:59:28.958335   0 14  0 | B1->B0 | 2b2b 3131 | 1 0 | (1 1) (0 0)

 5404 22:59:28.964827   0 14  4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)

 5405 22:59:28.968368   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5406 22:59:28.971408   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5407 22:59:28.978005   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5408 22:59:28.981743   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5409 22:59:28.984739   0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5410 22:59:28.991529   0 14 28 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 1)

 5411 22:59:28.994686   0 15  0 | B1->B0 | 2d2d 2626 | 0 0 | (0 0) (0 0)

 5412 22:59:28.997829   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5413 22:59:29.004631   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5414 22:59:29.007743   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5415 22:59:29.010847   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5416 22:59:29.017693   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5417 22:59:29.020735   0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5418 22:59:29.024087   0 15 28 | B1->B0 | 2626 3333 | 0 1 | (0 0) (0 0)

 5419 22:59:29.030771   1  0  0 | B1->B0 | 3e3e 4545 | 0 0 | (1 1) (0 0)

 5420 22:59:29.034187   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5421 22:59:29.037153   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5422 22:59:29.043692   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5423 22:59:29.047373   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5424 22:59:29.050312   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5425 22:59:29.057329   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5426 22:59:29.060203   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5427 22:59:29.063805   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 5428 22:59:29.070544   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5429 22:59:29.073610   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5430 22:59:29.076867   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5431 22:59:29.083717   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5432 22:59:29.086875   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5433 22:59:29.090017   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5434 22:59:29.096844   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5435 22:59:29.100600   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5436 22:59:29.103725   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5437 22:59:29.110502   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5438 22:59:29.113429   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5439 22:59:29.117186   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5440 22:59:29.123124   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5441 22:59:29.126289   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5442 22:59:29.129998   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 5443 22:59:29.136707   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5444 22:59:29.139558  Total UI for P1: 0, mck2ui 16

 5445 22:59:29.143224  best dqsien dly found for B0: ( 1,  2, 28)

 5446 22:59:29.143324  Total UI for P1: 0, mck2ui 16

 5447 22:59:29.149816  best dqsien dly found for B1: ( 1,  2, 30)

 5448 22:59:29.152936  best DQS0 dly(MCK, UI, PI) = (1, 2, 28)

 5449 22:59:29.156473  best DQS1 dly(MCK, UI, PI) = (1, 2, 30)

 5450 22:59:29.156566  

 5451 22:59:29.159309  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)

 5452 22:59:29.162767  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)

 5453 22:59:29.166403  [Gating] SW calibration Done

 5454 22:59:29.166497  ==

 5455 22:59:29.169382  Dram Type= 6, Freq= 0, CH_0, rank 1

 5456 22:59:29.172395  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5457 22:59:29.172502  ==

 5458 22:59:29.175954  RX Vref Scan: 0

 5459 22:59:29.176057  

 5460 22:59:29.179477  RX Vref 0 -> 0, step: 1

 5461 22:59:29.179582  

 5462 22:59:29.179674  RX Delay -80 -> 252, step: 8

 5463 22:59:29.186144  iDelay=208, Bit 0, Center 95 (0 ~ 191) 192

 5464 22:59:29.189204  iDelay=208, Bit 1, Center 99 (0 ~ 199) 200

 5465 22:59:29.192349  iDelay=208, Bit 2, Center 91 (0 ~ 183) 184

 5466 22:59:29.195418  iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200

 5467 22:59:29.199048  iDelay=208, Bit 4, Center 99 (0 ~ 199) 200

 5468 22:59:29.202350  iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192

 5469 22:59:29.208940  iDelay=208, Bit 6, Center 107 (8 ~ 207) 200

 5470 22:59:29.212096  iDelay=208, Bit 7, Center 107 (8 ~ 207) 200

 5471 22:59:29.215171  iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192

 5472 22:59:29.218889  iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192

 5473 22:59:29.221987  iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200

 5474 22:59:29.228601  iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192

 5475 22:59:29.231802  iDelay=208, Bit 12, Center 95 (0 ~ 191) 192

 5476 22:59:29.235602  iDelay=208, Bit 13, Center 95 (0 ~ 191) 192

 5477 22:59:29.238708  iDelay=208, Bit 14, Center 95 (0 ~ 191) 192

 5478 22:59:29.241685  iDelay=208, Bit 15, Center 95 (0 ~ 191) 192

 5479 22:59:29.241800  ==

 5480 22:59:29.245177  Dram Type= 6, Freq= 0, CH_0, rank 1

 5481 22:59:29.251901  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5482 22:59:29.251985  ==

 5483 22:59:29.252050  DQS Delay:

 5484 22:59:29.255513  DQS0 = 0, DQS1 = 0

 5485 22:59:29.255595  DQM Delay:

 5486 22:59:29.255660  DQM0 = 97, DQM1 = 88

 5487 22:59:29.258441  DQ Delay:

 5488 22:59:29.261439  DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91

 5489 22:59:29.264860  DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107

 5490 22:59:29.268040  DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79

 5491 22:59:29.271501  DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95

 5492 22:59:29.271584  

 5493 22:59:29.271648  

 5494 22:59:29.271708  ==

 5495 22:59:29.274989  Dram Type= 6, Freq= 0, CH_0, rank 1

 5496 22:59:29.278186  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5497 22:59:29.278269  ==

 5498 22:59:29.278335  

 5499 22:59:29.278394  

 5500 22:59:29.281728  	TX Vref Scan disable

 5501 22:59:29.284562   == TX Byte 0 ==

 5502 22:59:29.288167  Update DQ  dly =717 (2 ,6, 13)  DQ  OEN =(2 ,3)

 5503 22:59:29.291244  Update DQM dly =717 (2 ,6, 13)  DQM OEN =(2 ,3)

 5504 22:59:29.294368   == TX Byte 1 ==

 5505 22:59:29.298126  Update DQ  dly =714 (2 ,6, 10)  DQ  OEN =(2 ,3)

 5506 22:59:29.301243  Update DQM dly =714 (2 ,6, 10)  DQM OEN =(2 ,3)

 5507 22:59:29.301325  ==

 5508 22:59:29.304334  Dram Type= 6, Freq= 0, CH_0, rank 1

 5509 22:59:29.308002  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5510 22:59:29.311139  ==

 5511 22:59:29.311221  

 5512 22:59:29.311286  

 5513 22:59:29.311345  	TX Vref Scan disable

 5514 22:59:29.314852   == TX Byte 0 ==

 5515 22:59:29.317907  Update DQ  dly =716 (2 ,6, 12)  DQ  OEN =(2 ,3)

 5516 22:59:29.324495  Update DQM dly =716 (2 ,6, 12)  DQM OEN =(2 ,3)

 5517 22:59:29.324624   == TX Byte 1 ==

 5518 22:59:29.327664  Update DQ  dly =714 (2 ,6, 10)  DQ  OEN =(2 ,3)

 5519 22:59:29.334832  Update DQM dly =714 (2 ,6, 10)  DQM OEN =(2 ,3)

 5520 22:59:29.334915  

 5521 22:59:29.334979  [DATLAT]

 5522 22:59:29.335039  Freq=933, CH0 RK1

 5523 22:59:29.335098  

 5524 22:59:29.337948  DATLAT Default: 0xb

 5525 22:59:29.341052  0, 0xFFFF, sum = 0

 5526 22:59:29.341135  1, 0xFFFF, sum = 0

 5527 22:59:29.344759  2, 0xFFFF, sum = 0

 5528 22:59:29.344842  3, 0xFFFF, sum = 0

 5529 22:59:29.347571  4, 0xFFFF, sum = 0

 5530 22:59:29.347654  5, 0xFFFF, sum = 0

 5531 22:59:29.351186  6, 0xFFFF, sum = 0

 5532 22:59:29.351269  7, 0xFFFF, sum = 0

 5533 22:59:29.354182  8, 0xFFFF, sum = 0

 5534 22:59:29.354265  9, 0xFFFF, sum = 0

 5535 22:59:29.357756  10, 0x0, sum = 1

 5536 22:59:29.357839  11, 0x0, sum = 2

 5537 22:59:29.360900  12, 0x0, sum = 3

 5538 22:59:29.360983  13, 0x0, sum = 4

 5539 22:59:29.361049  best_step = 11

 5540 22:59:29.364369  

 5541 22:59:29.364479  ==

 5542 22:59:29.367341  Dram Type= 6, Freq= 0, CH_0, rank 1

 5543 22:59:29.370787  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5544 22:59:29.370870  ==

 5545 22:59:29.370935  RX Vref Scan: 0

 5546 22:59:29.370996  

 5547 22:59:29.374359  RX Vref 0 -> 0, step: 1

 5548 22:59:29.374441  

 5549 22:59:29.377258  RX Delay -61 -> 252, step: 4

 5550 22:59:29.383962  iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188

 5551 22:59:29.387523  iDelay=203, Bit 1, Center 98 (3 ~ 194) 192

 5552 22:59:29.390516  iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184

 5553 22:59:29.394061  iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192

 5554 22:59:29.397211  iDelay=203, Bit 4, Center 96 (3 ~ 190) 188

 5555 22:59:29.400274  iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192

 5556 22:59:29.407038  iDelay=203, Bit 6, Center 106 (11 ~ 202) 192

 5557 22:59:29.410604  iDelay=203, Bit 7, Center 104 (11 ~ 198) 188

 5558 22:59:29.413714  iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184

 5559 22:59:29.416897  iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184

 5560 22:59:29.420554  iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192

 5561 22:59:29.426813  iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184

 5562 22:59:29.429947  iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188

 5563 22:59:29.433397  iDelay=203, Bit 13, Center 90 (-5 ~ 186) 192

 5564 22:59:29.436442  iDelay=203, Bit 14, Center 94 (3 ~ 186) 184

 5565 22:59:29.440249  iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188

 5566 22:59:29.443472  ==

 5567 22:59:29.446387  Dram Type= 6, Freq= 0, CH_0, rank 1

 5568 22:59:29.450025  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5569 22:59:29.450108  ==

 5570 22:59:29.450174  DQS Delay:

 5571 22:59:29.453412  DQS0 = 0, DQS1 = 0

 5572 22:59:29.453494  DQM Delay:

 5573 22:59:29.456289  DQM0 = 95, DQM1 = 85

 5574 22:59:29.456372  DQ Delay:

 5575 22:59:29.459773  DQ0 =92, DQ1 =98, DQ2 =90, DQ3 =94

 5576 22:59:29.463202  DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104

 5577 22:59:29.466868  DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78

 5578 22:59:29.469691  DQ12 =92, DQ13 =90, DQ14 =94, DQ15 =92

 5579 22:59:29.469774  

 5580 22:59:29.469875  

 5581 22:59:29.476597  [DQSOSCAuto] RK1, (LSB)MR18= 0x27f7, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 409 ps

 5582 22:59:29.479410  CH0 RK1: MR19=504, MR18=27F7

 5583 22:59:29.485964  CH0_RK1: MR19=0x504, MR18=0x27F7, DQSOSC=409, MR23=63, INC=64, DEC=43

 5584 22:59:29.489510  [RxdqsGatingPostProcess] freq 933

 5585 22:59:29.496022  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 5586 22:59:29.499145  best DQS0 dly(2T, 0.5T) = (0, 10)

 5587 22:59:29.499228  best DQS1 dly(2T, 0.5T) = (0, 11)

 5588 22:59:29.502960  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5589 22:59:29.506067  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 5590 22:59:29.509106  best DQS0 dly(2T, 0.5T) = (0, 10)

 5591 22:59:29.512244  best DQS1 dly(2T, 0.5T) = (0, 10)

 5592 22:59:29.515862  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5593 22:59:29.519011  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5594 22:59:29.522809  Pre-setting of DQS Precalculation

 5595 22:59:29.529616  [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11

 5596 22:59:29.529699  ==

 5597 22:59:29.532680  Dram Type= 6, Freq= 0, CH_1, rank 0

 5598 22:59:29.535625  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5599 22:59:29.535742  ==

 5600 22:59:29.542434  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5601 22:59:29.549093  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5602 22:59:29.552081  [CA 0] Center 36 (6~67) winsize 62

 5603 22:59:29.555547  [CA 1] Center 37 (6~68) winsize 63

 5604 22:59:29.558517  [CA 2] Center 34 (4~65) winsize 62

 5605 22:59:29.562278  [CA 3] Center 33 (3~64) winsize 62

 5606 22:59:29.565218  [CA 4] Center 34 (4~64) winsize 61

 5607 22:59:29.568684  [CA 5] Center 33 (3~64) winsize 62

 5608 22:59:29.568767  

 5609 22:59:29.572204  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5610 22:59:29.572287  

 5611 22:59:29.575291  [CATrainingPosCal] consider 1 rank data

 5612 22:59:29.578810  u2DelayCellTimex100 = 270/100 ps

 5613 22:59:29.581816  CA0 delay=36 (6~67),Diff = 3 PI (18 cell)

 5614 22:59:29.585223  CA1 delay=37 (6~68),Diff = 4 PI (24 cell)

 5615 22:59:29.588642  CA2 delay=34 (4~65),Diff = 1 PI (6 cell)

 5616 22:59:29.591715  CA3 delay=33 (3~64),Diff = 0 PI (0 cell)

 5617 22:59:29.595243  CA4 delay=34 (4~64),Diff = 1 PI (6 cell)

 5618 22:59:29.598868  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 5619 22:59:29.598951  

 5620 22:59:29.601781  CA PerBit enable=1, Macro0, CA PI delay=33

 5621 22:59:29.605087  

 5622 22:59:29.605170  [CBTSetCACLKResult] CA Dly = 33

 5623 22:59:29.608185  CS Dly: 6 (0~37)

 5624 22:59:29.608267  ==

 5625 22:59:29.611949  Dram Type= 6, Freq= 0, CH_1, rank 1

 5626 22:59:29.615046  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5627 22:59:29.615131  ==

 5628 22:59:29.621300  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5629 22:59:29.628118  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 5630 22:59:29.631864  [CA 0] Center 36 (6~67) winsize 62

 5631 22:59:29.634899  [CA 1] Center 37 (7~67) winsize 61

 5632 22:59:29.638066  [CA 2] Center 34 (4~65) winsize 62

 5633 22:59:29.641675  [CA 3] Center 33 (3~64) winsize 62

 5634 22:59:29.644496  [CA 4] Center 34 (3~65) winsize 63

 5635 22:59:29.648212  [CA 5] Center 33 (3~64) winsize 62

 5636 22:59:29.648295  

 5637 22:59:29.651326  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 5638 22:59:29.651409  

 5639 22:59:29.654437  [CATrainingPosCal] consider 2 rank data

 5640 22:59:29.658156  u2DelayCellTimex100 = 270/100 ps

 5641 22:59:29.661452  CA0 delay=36 (6~67),Diff = 3 PI (18 cell)

 5642 22:59:29.664738  CA1 delay=37 (7~67),Diff = 4 PI (24 cell)

 5643 22:59:29.667843  CA2 delay=34 (4~65),Diff = 1 PI (6 cell)

 5644 22:59:29.671281  CA3 delay=33 (3~64),Diff = 0 PI (0 cell)

 5645 22:59:29.674306  CA4 delay=34 (4~64),Diff = 1 PI (6 cell)

 5646 22:59:29.677833  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 5647 22:59:29.681398  

 5648 22:59:29.684446  CA PerBit enable=1, Macro0, CA PI delay=33

 5649 22:59:29.684583  

 5650 22:59:29.687378  [CBTSetCACLKResult] CA Dly = 33

 5651 22:59:29.687461  CS Dly: 7 (0~39)

 5652 22:59:29.687526  

 5653 22:59:29.691009  ----->DramcWriteLeveling(PI) begin...

 5654 22:59:29.691094  ==

 5655 22:59:29.694011  Dram Type= 6, Freq= 0, CH_1, rank 0

 5656 22:59:29.700654  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5657 22:59:29.700737  ==

 5658 22:59:29.704170  Write leveling (Byte 0): 23 => 23

 5659 22:59:29.704252  Write leveling (Byte 1): 27 => 27

 5660 22:59:29.707222  DramcWriteLeveling(PI) end<-----

 5661 22:59:29.707306  

 5662 22:59:29.707370  ==

 5663 22:59:29.710413  Dram Type= 6, Freq= 0, CH_1, rank 0

 5664 22:59:29.717116  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5665 22:59:29.717200  ==

 5666 22:59:29.720840  [Gating] SW mode calibration

 5667 22:59:29.726970  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5668 22:59:29.730750  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5669 22:59:29.736969   0 14  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5670 22:59:29.740061   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5671 22:59:29.743764   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5672 22:59:29.750400   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5673 22:59:29.753472   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5674 22:59:29.757078   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5675 22:59:29.763153   0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)

 5676 22:59:29.766769   0 14 28 | B1->B0 | 2f2f 2e2e | 1 0 | (1 0) (0 0)

 5677 22:59:29.769785   0 15  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5678 22:59:29.776427   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5679 22:59:29.779881   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5680 22:59:29.782769   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5681 22:59:29.789355   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5682 22:59:29.792975   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5683 22:59:29.795861   0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5684 22:59:29.802405   0 15 28 | B1->B0 | 2f2f 3636 | 0 0 | (1 1) (1 1)

 5685 22:59:29.805898   1  0  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5686 22:59:29.809436   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5687 22:59:29.815636   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5688 22:59:29.819461   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5689 22:59:29.822426   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5690 22:59:29.829198   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5691 22:59:29.832180   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5692 22:59:29.835304   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 5693 22:59:29.842093   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5694 22:59:29.845704   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5695 22:59:29.848894   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5696 22:59:29.855587   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5697 22:59:29.858750   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5698 22:59:29.861836   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5699 22:59:29.868474   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5700 22:59:29.872214   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5701 22:59:29.875134   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5702 22:59:29.881567   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5703 22:59:29.885195   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5704 22:59:29.888117   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5705 22:59:29.895046   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5706 22:59:29.898265   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5707 22:59:29.901531   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5708 22:59:29.908062   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5709 22:59:29.911627   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5710 22:59:29.914576  Total UI for P1: 0, mck2ui 16

 5711 22:59:29.918282  best dqsien dly found for B0: ( 1,  2, 26)

 5712 22:59:29.921456  Total UI for P1: 0, mck2ui 16

 5713 22:59:29.924427  best dqsien dly found for B1: ( 1,  2, 26)

 5714 22:59:29.928114  best DQS0 dly(MCK, UI, PI) = (1, 2, 26)

 5715 22:59:29.931201  best DQS1 dly(MCK, UI, PI) = (1, 2, 26)

 5716 22:59:29.931284  

 5717 22:59:29.934832  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5718 22:59:29.937790  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5719 22:59:29.941647  [Gating] SW calibration Done

 5720 22:59:29.941730  ==

 5721 22:59:29.944779  Dram Type= 6, Freq= 0, CH_1, rank 0

 5722 22:59:29.951511  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5723 22:59:29.951595  ==

 5724 22:59:29.951661  RX Vref Scan: 0

 5725 22:59:29.951722  

 5726 22:59:29.954619  RX Vref 0 -> 0, step: 1

 5727 22:59:29.954702  

 5728 22:59:29.957453  RX Delay -80 -> 252, step: 8

 5729 22:59:29.961186  iDelay=208, Bit 0, Center 107 (16 ~ 199) 184

 5730 22:59:29.964335  iDelay=208, Bit 1, Center 95 (0 ~ 191) 192

 5731 22:59:29.967346  iDelay=208, Bit 2, Center 95 (0 ~ 191) 192

 5732 22:59:29.970929  iDelay=208, Bit 3, Center 95 (0 ~ 191) 192

 5733 22:59:29.977426  iDelay=208, Bit 4, Center 95 (0 ~ 191) 192

 5734 22:59:29.981146  iDelay=208, Bit 5, Center 111 (16 ~ 207) 192

 5735 22:59:29.984385  iDelay=208, Bit 6, Center 111 (16 ~ 207) 192

 5736 22:59:29.987506  iDelay=208, Bit 7, Center 95 (0 ~ 191) 192

 5737 22:59:29.990508  iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192

 5738 22:59:29.993806  iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200

 5739 22:59:30.000336  iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200

 5740 22:59:30.003906  iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184

 5741 22:59:30.006874  iDelay=208, Bit 12, Center 99 (0 ~ 199) 200

 5742 22:59:30.010399  iDelay=208, Bit 13, Center 99 (0 ~ 199) 200

 5743 22:59:30.013974  iDelay=208, Bit 14, Center 99 (0 ~ 199) 200

 5744 22:59:30.020170  iDelay=208, Bit 15, Center 99 (0 ~ 199) 200

 5745 22:59:30.020254  ==

 5746 22:59:30.023679  Dram Type= 6, Freq= 0, CH_1, rank 0

 5747 22:59:30.026881  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5748 22:59:30.026965  ==

 5749 22:59:30.027030  DQS Delay:

 5750 22:59:30.029938  DQS0 = 0, DQS1 = 0

 5751 22:59:30.030021  DQM Delay:

 5752 22:59:30.033766  DQM0 = 100, DQM1 = 91

 5753 22:59:30.033849  DQ Delay:

 5754 22:59:30.036865  DQ0 =107, DQ1 =95, DQ2 =95, DQ3 =95

 5755 22:59:30.040708  DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95

 5756 22:59:30.043719  DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =83

 5757 22:59:30.046814  DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99

 5758 22:59:30.046896  

 5759 22:59:30.046961  

 5760 22:59:30.047022  ==

 5761 22:59:30.050469  Dram Type= 6, Freq= 0, CH_1, rank 0

 5762 22:59:30.053488  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5763 22:59:30.056559  ==

 5764 22:59:30.056642  

 5765 22:59:30.056707  

 5766 22:59:30.056768  	TX Vref Scan disable

 5767 22:59:30.060105   == TX Byte 0 ==

 5768 22:59:30.063031  Update DQ  dly =707 (2 ,5, 35)  DQ  OEN =(2 ,2)

 5769 22:59:30.066804  Update DQM dly =707 (2 ,5, 35)  DQM OEN =(2 ,2)

 5770 22:59:30.069879   == TX Byte 1 ==

 5771 22:59:30.073595  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5772 22:59:30.076487  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5773 22:59:30.079592  ==

 5774 22:59:30.083043  Dram Type= 6, Freq= 0, CH_1, rank 0

 5775 22:59:30.086763  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5776 22:59:30.086847  ==

 5777 22:59:30.086949  

 5778 22:59:30.087052  

 5779 22:59:30.089841  	TX Vref Scan disable

 5780 22:59:30.089925   == TX Byte 0 ==

 5781 22:59:30.096321  Update DQ  dly =706 (2 ,5, 34)  DQ  OEN =(2 ,2)

 5782 22:59:30.099869  Update DQM dly =706 (2 ,5, 34)  DQM OEN =(2 ,2)

 5783 22:59:30.099952   == TX Byte 1 ==

 5784 22:59:30.106318  Update DQ  dly =708 (2 ,5, 36)  DQ  OEN =(2 ,2)

 5785 22:59:30.109876  Update DQM dly =708 (2 ,5, 36)  DQM OEN =(2 ,2)

 5786 22:59:30.109958  

 5787 22:59:30.110022  [DATLAT]

 5788 22:59:30.112859  Freq=933, CH1 RK0

 5789 22:59:30.112942  

 5790 22:59:30.113007  DATLAT Default: 0xd

 5791 22:59:30.115863  0, 0xFFFF, sum = 0

 5792 22:59:30.115946  1, 0xFFFF, sum = 0

 5793 22:59:30.119403  2, 0xFFFF, sum = 0

 5794 22:59:30.122958  3, 0xFFFF, sum = 0

 5795 22:59:30.123042  4, 0xFFFF, sum = 0

 5796 22:59:30.126030  5, 0xFFFF, sum = 0

 5797 22:59:30.126114  6, 0xFFFF, sum = 0

 5798 22:59:30.129128  7, 0xFFFF, sum = 0

 5799 22:59:30.129212  8, 0xFFFF, sum = 0

 5800 22:59:30.132867  9, 0xFFFF, sum = 0

 5801 22:59:30.132951  10, 0x0, sum = 1

 5802 22:59:30.135962  11, 0x0, sum = 2

 5803 22:59:30.136084  12, 0x0, sum = 3

 5804 22:59:30.136150  13, 0x0, sum = 4

 5805 22:59:30.139547  best_step = 11

 5806 22:59:30.139628  

 5807 22:59:30.139692  ==

 5808 22:59:30.142570  Dram Type= 6, Freq= 0, CH_1, rank 0

 5809 22:59:30.145724  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5810 22:59:30.145807  ==

 5811 22:59:30.148830  RX Vref Scan: 1

 5812 22:59:30.148912  

 5813 22:59:30.152394  RX Vref 0 -> 0, step: 1

 5814 22:59:30.152476  

 5815 22:59:30.152577  RX Delay -61 -> 252, step: 4

 5816 22:59:30.152638  

 5817 22:59:30.155527  Set Vref, RX VrefLevel [Byte0]: 45

 5818 22:59:30.158683                           [Byte1]: 57

 5819 22:59:30.163594  

 5820 22:59:30.163676  Final RX Vref Byte 0 = 45 to rank0

 5821 22:59:30.167196  Final RX Vref Byte 1 = 57 to rank0

 5822 22:59:30.170333  Final RX Vref Byte 0 = 45 to rank1

 5823 22:59:30.173439  Final RX Vref Byte 1 = 57 to rank1==

 5824 22:59:30.177083  Dram Type= 6, Freq= 0, CH_1, rank 0

 5825 22:59:30.183710  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5826 22:59:30.183794  ==

 5827 22:59:30.183860  DQS Delay:

 5828 22:59:30.187111  DQS0 = 0, DQS1 = 0

 5829 22:59:30.187193  DQM Delay:

 5830 22:59:30.187258  DQM0 = 101, DQM1 = 94

 5831 22:59:30.189993  DQ Delay:

 5832 22:59:30.193246  DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =98

 5833 22:59:30.196848  DQ4 =98, DQ5 =110, DQ6 =110, DQ7 =96

 5834 22:59:30.199832  DQ8 =84, DQ9 =86, DQ10 =96, DQ11 =84

 5835 22:59:30.203363  DQ12 =102, DQ13 =100, DQ14 =102, DQ15 =102

 5836 22:59:30.203445  

 5837 22:59:30.203510  

 5838 22:59:30.209851  [DQSOSCAuto] RK0, (LSB)MR18= 0x1c0c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 412 ps

 5839 22:59:30.213293  CH1 RK0: MR19=505, MR18=1C0C

 5840 22:59:30.219940  CH1_RK0: MR19=0x505, MR18=0x1C0C, DQSOSC=412, MR23=63, INC=63, DEC=42

 5841 22:59:30.220023  

 5842 22:59:30.223007  ----->DramcWriteLeveling(PI) begin...

 5843 22:59:30.223091  ==

 5844 22:59:30.226545  Dram Type= 6, Freq= 0, CH_1, rank 1

 5845 22:59:30.230208  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5846 22:59:30.230291  ==

 5847 22:59:30.233395  Write leveling (Byte 0): 25 => 25

 5848 22:59:30.236365  Write leveling (Byte 1): 27 => 27

 5849 22:59:30.239503  DramcWriteLeveling(PI) end<-----

 5850 22:59:30.239585  

 5851 22:59:30.239649  ==

 5852 22:59:30.243164  Dram Type= 6, Freq= 0, CH_1, rank 1

 5853 22:59:30.249457  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5854 22:59:30.249539  ==

 5855 22:59:30.249605  [Gating] SW mode calibration

 5856 22:59:30.259308  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5857 22:59:30.262937  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5858 22:59:30.269720   0 14  0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)

 5859 22:59:30.272720   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5860 22:59:30.275844   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5861 22:59:30.282685   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5862 22:59:30.285734   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5863 22:59:30.289234   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5864 22:59:30.295556   0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)

 5865 22:59:30.298732   0 14 28 | B1->B0 | 2b2b 2e2e | 0 0 | (0 0) (0 0)

 5866 22:59:30.302285   0 15  0 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 0)

 5867 22:59:30.308732   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5868 22:59:30.312179   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5869 22:59:30.315664   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5870 22:59:30.322235   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5871 22:59:30.325227   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5872 22:59:30.328764   0 15 24 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)

 5873 22:59:30.335570   0 15 28 | B1->B0 | 3e3e 3737 | 0 0 | (0 0) (0 0)

 5874 22:59:30.338607   1  0  0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)

 5875 22:59:30.341734   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5876 22:59:30.348398   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5877 22:59:30.351549   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5878 22:59:30.355163   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5879 22:59:30.361844   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5880 22:59:30.364878   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5881 22:59:30.368509   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5882 22:59:30.375269   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5883 22:59:30.378419   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5884 22:59:30.381517   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5885 22:59:30.387758   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5886 22:59:30.391415   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5887 22:59:30.394486   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5888 22:59:30.401187   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5889 22:59:30.404285   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5890 22:59:30.407927   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5891 22:59:30.414257   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5892 22:59:30.417723   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5893 22:59:30.421103   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5894 22:59:30.427696   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5895 22:59:30.430701   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5896 22:59:30.434079   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5897 22:59:30.440925   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 5898 22:59:30.441009  Total UI for P1: 0, mck2ui 16

 5899 22:59:30.444029  best dqsien dly found for B1: ( 1,  2, 24)

 5900 22:59:30.450782   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5901 22:59:30.454354  Total UI for P1: 0, mck2ui 16

 5902 22:59:30.457528  best dqsien dly found for B0: ( 1,  2, 26)

 5903 22:59:30.461050  best DQS0 dly(MCK, UI, PI) = (1, 2, 26)

 5904 22:59:30.464210  best DQS1 dly(MCK, UI, PI) = (1, 2, 24)

 5905 22:59:30.464309  

 5906 22:59:30.467153  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5907 22:59:30.470910  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)

 5908 22:59:30.474021  [Gating] SW calibration Done

 5909 22:59:30.474103  ==

 5910 22:59:30.477653  Dram Type= 6, Freq= 0, CH_1, rank 1

 5911 22:59:30.480752  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5912 22:59:30.480835  ==

 5913 22:59:30.483853  RX Vref Scan: 0

 5914 22:59:30.483934  

 5915 22:59:30.487008  RX Vref 0 -> 0, step: 1

 5916 22:59:30.487091  

 5917 22:59:30.487156  RX Delay -80 -> 252, step: 8

 5918 22:59:30.493804  iDelay=208, Bit 0, Center 103 (8 ~ 199) 192

 5919 22:59:30.497313  iDelay=208, Bit 1, Center 91 (0 ~ 183) 184

 5920 22:59:30.500277  iDelay=208, Bit 2, Center 91 (0 ~ 183) 184

 5921 22:59:30.503885  iDelay=208, Bit 3, Center 95 (8 ~ 183) 176

 5922 22:59:30.507430  iDelay=208, Bit 4, Center 95 (0 ~ 191) 192

 5923 22:59:30.510531  iDelay=208, Bit 5, Center 107 (16 ~ 199) 184

 5924 22:59:30.516855  iDelay=208, Bit 6, Center 111 (16 ~ 207) 192

 5925 22:59:30.520347  iDelay=208, Bit 7, Center 95 (0 ~ 191) 192

 5926 22:59:30.523335  iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192

 5927 22:59:30.526975  iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192

 5928 22:59:30.529974  iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200

 5929 22:59:30.536460  iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200

 5930 22:59:30.540264  iDelay=208, Bit 12, Center 103 (8 ~ 199) 192

 5931 22:59:30.543292  iDelay=208, Bit 13, Center 99 (0 ~ 199) 200

 5932 22:59:30.546373  iDelay=208, Bit 14, Center 99 (0 ~ 199) 200

 5933 22:59:30.550190  iDelay=208, Bit 15, Center 99 (0 ~ 199) 200

 5934 22:59:30.550279  ==

 5935 22:59:30.553211  Dram Type= 6, Freq= 0, CH_1, rank 1

 5936 22:59:30.560083  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5937 22:59:30.560192  ==

 5938 22:59:30.560285  DQS Delay:

 5939 22:59:30.563186  DQS0 = 0, DQS1 = 0

 5940 22:59:30.563294  DQM Delay:

 5941 22:59:30.563387  DQM0 = 98, DQM1 = 91

 5942 22:59:30.566831  DQ Delay:

 5943 22:59:30.569999  DQ0 =103, DQ1 =91, DQ2 =91, DQ3 =95

 5944 22:59:30.573103  DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95

 5945 22:59:30.576269  DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83

 5946 22:59:30.579972  DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =99

 5947 22:59:30.580055  

 5948 22:59:30.580119  

 5949 22:59:30.580179  ==

 5950 22:59:30.583054  Dram Type= 6, Freq= 0, CH_1, rank 1

 5951 22:59:30.586700  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5952 22:59:30.586783  ==

 5953 22:59:30.586848  

 5954 22:59:30.586908  

 5955 22:59:30.589719  	TX Vref Scan disable

 5956 22:59:30.592862   == TX Byte 0 ==

 5957 22:59:30.596488  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5958 22:59:30.599568  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5959 22:59:30.603100   == TX Byte 1 ==

 5960 22:59:30.605972  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5961 22:59:30.609521  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5962 22:59:30.609604  ==

 5963 22:59:30.612725  Dram Type= 6, Freq= 0, CH_1, rank 1

 5964 22:59:30.619122  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5965 22:59:30.619205  ==

 5966 22:59:30.619270  

 5967 22:59:30.619331  

 5968 22:59:30.619388  	TX Vref Scan disable

 5969 22:59:30.623099   == TX Byte 0 ==

 5970 22:59:30.626745  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5971 22:59:30.633214  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5972 22:59:30.633297   == TX Byte 1 ==

 5973 22:59:30.636738  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5974 22:59:30.643288  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5975 22:59:30.643370  

 5976 22:59:30.643435  [DATLAT]

 5977 22:59:30.643495  Freq=933, CH1 RK1

 5978 22:59:30.643554  

 5979 22:59:30.646413  DATLAT Default: 0xb

 5980 22:59:30.646494  0, 0xFFFF, sum = 0

 5981 22:59:30.649412  1, 0xFFFF, sum = 0

 5982 22:59:30.653118  2, 0xFFFF, sum = 0

 5983 22:59:30.653201  3, 0xFFFF, sum = 0

 5984 22:59:30.656204  4, 0xFFFF, sum = 0

 5985 22:59:30.656287  5, 0xFFFF, sum = 0

 5986 22:59:30.659365  6, 0xFFFF, sum = 0

 5987 22:59:30.659448  7, 0xFFFF, sum = 0

 5988 22:59:30.662881  8, 0xFFFF, sum = 0

 5989 22:59:30.662965  9, 0xFFFF, sum = 0

 5990 22:59:30.666012  10, 0x0, sum = 1

 5991 22:59:30.666096  11, 0x0, sum = 2

 5992 22:59:30.669200  12, 0x0, sum = 3

 5993 22:59:30.669283  13, 0x0, sum = 4

 5994 22:59:30.672731  best_step = 11

 5995 22:59:30.672813  

 5996 22:59:30.672876  ==

 5997 22:59:30.675815  Dram Type= 6, Freq= 0, CH_1, rank 1

 5998 22:59:30.679386  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5999 22:59:30.679469  ==

 6000 22:59:30.679535  RX Vref Scan: 0

 6001 22:59:30.682623  

 6002 22:59:30.682705  RX Vref 0 -> 0, step: 1

 6003 22:59:30.682769  

 6004 22:59:30.685653  RX Delay -61 -> 252, step: 4

 6005 22:59:30.692281  iDelay=203, Bit 0, Center 106 (19 ~ 194) 176

 6006 22:59:30.695532  iDelay=203, Bit 1, Center 96 (11 ~ 182) 172

 6007 22:59:30.699090  iDelay=203, Bit 2, Center 92 (7 ~ 178) 172

 6008 22:59:30.702333  iDelay=203, Bit 3, Center 98 (15 ~ 182) 168

 6009 22:59:30.705882  iDelay=203, Bit 4, Center 100 (11 ~ 190) 180

 6010 22:59:30.712284  iDelay=203, Bit 5, Center 110 (23 ~ 198) 176

 6011 22:59:30.715941  iDelay=203, Bit 6, Center 114 (27 ~ 202) 176

 6012 22:59:30.718859  iDelay=203, Bit 7, Center 96 (7 ~ 186) 180

 6013 22:59:30.721865  iDelay=203, Bit 8, Center 82 (-9 ~ 174) 184

 6014 22:59:30.725473  iDelay=203, Bit 9, Center 82 (-9 ~ 174) 184

 6015 22:59:30.729034  iDelay=203, Bit 10, Center 94 (3 ~ 186) 184

 6016 22:59:30.735433  iDelay=203, Bit 11, Center 84 (-5 ~ 174) 180

 6017 22:59:30.738472  iDelay=203, Bit 12, Center 100 (7 ~ 194) 188

 6018 22:59:30.742144  iDelay=203, Bit 13, Center 100 (7 ~ 194) 188

 6019 22:59:30.745159  iDelay=203, Bit 14, Center 100 (11 ~ 190) 180

 6020 22:59:30.748753  iDelay=203, Bit 15, Center 100 (7 ~ 194) 188

 6021 22:59:30.751823  ==

 6022 22:59:30.754924  Dram Type= 6, Freq= 0, CH_1, rank 1

 6023 22:59:30.758573  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 6024 22:59:30.758655  ==

 6025 22:59:30.758720  DQS Delay:

 6026 22:59:30.761716  DQS0 = 0, DQS1 = 0

 6027 22:59:30.761856  DQM Delay:

 6028 22:59:30.765423  DQM0 = 101, DQM1 = 92

 6029 22:59:30.765504  DQ Delay:

 6030 22:59:30.768412  DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98

 6031 22:59:30.771452  DQ4 =100, DQ5 =110, DQ6 =114, DQ7 =96

 6032 22:59:30.775075  DQ8 =82, DQ9 =82, DQ10 =94, DQ11 =84

 6033 22:59:30.778247  DQ12 =100, DQ13 =100, DQ14 =100, DQ15 =100

 6034 22:59:30.778328  

 6035 22:59:30.778392  

 6036 22:59:30.788419  [DQSOSCAuto] RK1, (LSB)MR18= 0x701, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps

 6037 22:59:30.788549  CH1 RK1: MR19=505, MR18=701

 6038 22:59:30.794503  CH1_RK1: MR19=0x505, MR18=0x701, DQSOSC=419, MR23=63, INC=61, DEC=41

 6039 22:59:30.798196  [RxdqsGatingPostProcess] freq 933

 6040 22:59:30.804325  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 6041 22:59:30.807917  best DQS0 dly(2T, 0.5T) = (0, 10)

 6042 22:59:30.810979  best DQS1 dly(2T, 0.5T) = (0, 10)

 6043 22:59:30.814681  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 6044 22:59:30.817696  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 6045 22:59:30.817779  best DQS0 dly(2T, 0.5T) = (0, 10)

 6046 22:59:30.821230  best DQS1 dly(2T, 0.5T) = (0, 10)

 6047 22:59:30.824161  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 6048 22:59:30.827802  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 6049 22:59:30.831253  Pre-setting of DQS Precalculation

 6050 22:59:30.837479  [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11

 6051 22:59:30.844208  sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3

 6052 22:59:30.850845  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 6053 22:59:30.850928  

 6054 22:59:30.850993  

 6055 22:59:30.853986  [Calibration Summary] 1866 Mbps

 6056 22:59:30.857062  CH 0, Rank 0

 6057 22:59:30.857144  SW Impedance     : PASS

 6058 22:59:30.860780  DUTY Scan        : NO K

 6059 22:59:30.863717  ZQ Calibration   : PASS

 6060 22:59:30.863847  Jitter Meter     : NO K

 6061 22:59:30.866907  CBT Training     : PASS

 6062 22:59:30.866989  Write leveling   : PASS

 6063 22:59:30.870745  RX DQS gating    : PASS

 6064 22:59:30.873760  RX DQ/DQS(RDDQC) : PASS

 6065 22:59:30.873842  TX DQ/DQS        : PASS

 6066 22:59:30.877276  RX DATLAT        : PASS

 6067 22:59:30.880368  RX DQ/DQS(Engine): PASS

 6068 22:59:30.880476  TX OE            : NO K

 6069 22:59:30.883552  All Pass.

 6070 22:59:30.883635  

 6071 22:59:30.883700  CH 0, Rank 1

 6072 22:59:30.886807  SW Impedance     : PASS

 6073 22:59:30.886890  DUTY Scan        : NO K

 6074 22:59:30.890483  ZQ Calibration   : PASS

 6075 22:59:30.893645  Jitter Meter     : NO K

 6076 22:59:30.893728  CBT Training     : PASS

 6077 22:59:30.896733  Write leveling   : PASS

 6078 22:59:30.900417  RX DQS gating    : PASS

 6079 22:59:30.900500  RX DQ/DQS(RDDQC) : PASS

 6080 22:59:30.903403  TX DQ/DQS        : PASS

 6081 22:59:30.906467  RX DATLAT        : PASS

 6082 22:59:30.906550  RX DQ/DQS(Engine): PASS

 6083 22:59:30.910165  TX OE            : NO K

 6084 22:59:30.910247  All Pass.

 6085 22:59:30.910313  

 6086 22:59:30.913062  CH 1, Rank 0

 6087 22:59:30.913145  SW Impedance     : PASS

 6088 22:59:30.916843  DUTY Scan        : NO K

 6089 22:59:30.919909  ZQ Calibration   : PASS

 6090 22:59:30.919992  Jitter Meter     : NO K

 6091 22:59:30.922976  CBT Training     : PASS

 6092 22:59:30.926646  Write leveling   : PASS

 6093 22:59:30.926733  RX DQS gating    : PASS

 6094 22:59:30.929551  RX DQ/DQS(RDDQC) : PASS

 6095 22:59:30.933114  TX DQ/DQS        : PASS

 6096 22:59:30.933197  RX DATLAT        : PASS

 6097 22:59:30.936131  RX DQ/DQS(Engine): PASS

 6098 22:59:30.939589  TX OE            : NO K

 6099 22:59:30.939672  All Pass.

 6100 22:59:30.939737  

 6101 22:59:30.939797  CH 1, Rank 1

 6102 22:59:30.942902  SW Impedance     : PASS

 6103 22:59:30.946189  DUTY Scan        : NO K

 6104 22:59:30.946271  ZQ Calibration   : PASS

 6105 22:59:30.949328  Jitter Meter     : NO K

 6106 22:59:30.949409  CBT Training     : PASS

 6107 22:59:30.953075  Write leveling   : PASS

 6108 22:59:30.956041  RX DQS gating    : PASS

 6109 22:59:30.956124  RX DQ/DQS(RDDQC) : PASS

 6110 22:59:30.959723  TX DQ/DQS        : PASS

 6111 22:59:30.962939  RX DATLAT        : PASS

 6112 22:59:30.963020  RX DQ/DQS(Engine): PASS

 6113 22:59:30.965915  TX OE            : NO K

 6114 22:59:30.965997  All Pass.

 6115 22:59:30.966061  

 6116 22:59:30.969038  DramC Write-DBI off

 6117 22:59:30.972136  	PER_BANK_REFRESH: Hybrid Mode

 6118 22:59:30.972218  TX_TRACKING: ON

 6119 22:59:30.981982  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0

 6120 22:59:30.985734  [FAST_K] Save calibration result to emmc

 6121 22:59:30.988913  dramc_set_vcore_voltage set vcore to 650000

 6122 22:59:30.991947  Read voltage for 400, 6

 6123 22:59:30.992028  Vio18 = 0

 6124 22:59:30.995546  Vcore = 650000

 6125 22:59:30.995627  Vdram = 0

 6126 22:59:30.995691  Vddq = 0

 6127 22:59:30.995751  Vmddr = 0

 6128 22:59:31.002257  [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0

 6129 22:59:31.008815  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 6130 22:59:31.008899  MEM_TYPE=3, freq_sel=20

 6131 22:59:31.011767  sv_algorithm_assistance_LP4_800 

 6132 22:59:31.015157  ============ PULL DRAM RESETB DOWN ============

 6133 22:59:31.021531  ========== PULL DRAM RESETB DOWN end =========

 6134 22:59:31.025179  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6135 22:59:31.028182  =================================== 

 6136 22:59:31.031866  LPDDR4 DRAM CONFIGURATION

 6137 22:59:31.034785  =================================== 

 6138 22:59:31.034867  EX_ROW_EN[0]    = 0x0

 6139 22:59:31.038333  EX_ROW_EN[1]    = 0x0

 6140 22:59:31.038415  LP4Y_EN      = 0x0

 6141 22:59:31.041363  WORK_FSP     = 0x0

 6142 22:59:31.044761  WL           = 0x2

 6143 22:59:31.044842  RL           = 0x2

 6144 22:59:31.048288  BL           = 0x2

 6145 22:59:31.048369  RPST         = 0x0

 6146 22:59:31.051310  RD_PRE       = 0x0

 6147 22:59:31.051392  WR_PRE       = 0x1

 6148 22:59:31.054363  WR_PST       = 0x0

 6149 22:59:31.054445  DBI_WR       = 0x0

 6150 22:59:31.057927  DBI_RD       = 0x0

 6151 22:59:31.058008  OTF          = 0x1

 6152 22:59:31.061432  =================================== 

 6153 22:59:31.064489  =================================== 

 6154 22:59:31.067800  ANA top config

 6155 22:59:31.071477  =================================== 

 6156 22:59:31.071568  DLL_ASYNC_EN            =  0

 6157 22:59:31.074613  ALL_SLAVE_EN            =  1

 6158 22:59:31.077720  NEW_RANK_MODE           =  1

 6159 22:59:31.081308  DLL_IDLE_MODE           =  1

 6160 22:59:31.084287  LP45_APHY_COMB_EN       =  1

 6161 22:59:31.084369  TX_ODT_DIS              =  1

 6162 22:59:31.087382  NEW_8X_MODE             =  1

 6163 22:59:31.091203  =================================== 

 6164 22:59:31.094363  =================================== 

 6165 22:59:31.097540  data_rate                  =  800

 6166 22:59:31.101149  CKR                        = 1

 6167 22:59:31.104216  DQ_P2S_RATIO               = 4

 6168 22:59:31.107457  =================================== 

 6169 22:59:31.110878  CA_P2S_RATIO               = 4

 6170 22:59:31.110959  DQ_CA_OPEN                 = 0

 6171 22:59:31.113879  DQ_SEMI_OPEN               = 1

 6172 22:59:31.117552  CA_SEMI_OPEN               = 1

 6173 22:59:31.120542  CA_FULL_RATE               = 0

 6174 22:59:31.124306  DQ_CKDIV4_EN               = 0

 6175 22:59:31.127365  CA_CKDIV4_EN               = 1

 6176 22:59:31.127447  CA_PREDIV_EN               = 0

 6177 22:59:31.130461  PH8_DLY                    = 0

 6178 22:59:31.134013  SEMI_OPEN_CA_PICK_MCK_RATIO= 4

 6179 22:59:31.137029  DQ_AAMCK_DIV               = 0

 6180 22:59:31.140557  CA_AAMCK_DIV               = 0

 6181 22:59:31.143617  CA_ADMCK_DIV               = 4

 6182 22:59:31.143700  DQ_TRACK_CA_EN             = 0

 6183 22:59:31.147007  CA_PICK                    = 800

 6184 22:59:31.150474  CA_MCKIO                   = 400

 6185 22:59:31.153533  MCKIO_SEMI                 = 400

 6186 22:59:31.156993  PLL_FREQ                   = 3016

 6187 22:59:31.160030  DQ_UI_PI_RATIO             = 32

 6188 22:59:31.163680  CA_UI_PI_RATIO             = 32

 6189 22:59:31.166627  =================================== 

 6190 22:59:31.170269  =================================== 

 6191 22:59:31.170378  memory_type:LPDDR4         

 6192 22:59:31.173283  GP_NUM     : 10       

 6193 22:59:31.176987  SRAM_EN    : 1       

 6194 22:59:31.177095  MD32_EN    : 0       

 6195 22:59:31.180026  =================================== 

 6196 22:59:31.183225  [ANA_INIT] >>>>>>>>>>>>>> 

 6197 22:59:31.186254  <<<<<< [CONFIGURE PHASE]: ANA_TX

 6198 22:59:31.189903  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 6199 22:59:31.193046  =================================== 

 6200 22:59:31.196009  data_rate = 800,PCW = 0X7400

 6201 22:59:31.199754  =================================== 

 6202 22:59:31.202820  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 6203 22:59:31.209581  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 6204 22:59:31.219325  WARN: tr->DQ_AAMCK_DIV=  0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 6205 22:59:31.222958  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 6206 22:59:31.225985  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 6207 22:59:31.232796  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 6208 22:59:31.232882  [ANA_INIT] flow start 

 6209 22:59:31.235755  [ANA_INIT] PLL >>>>>>>> 

 6210 22:59:31.235840  [ANA_INIT] PLL <<<<<<<< 

 6211 22:59:31.239401  [ANA_INIT] MIDPI >>>>>>>> 

 6212 22:59:31.242171  [ANA_INIT] MIDPI <<<<<<<< 

 6213 22:59:31.245815  [ANA_INIT] DLL >>>>>>>> 

 6214 22:59:31.245899  [ANA_INIT] flow end 

 6215 22:59:31.248778  ============ LP4 DIFF to SE enter ============

 6216 22:59:31.255503  ============ LP4 DIFF to SE exit  ============

 6217 22:59:31.255625  [ANA_INIT] <<<<<<<<<<<<< 

 6218 22:59:31.258673  [Flow] Enable top DCM control >>>>> 

 6219 22:59:31.262263  [Flow] Enable top DCM control <<<<< 

 6220 22:59:31.265274  Enable DLL master slave shuffle 

 6221 22:59:31.271810  ============================================================== 

 6222 22:59:31.275563  Gating Mode config

 6223 22:59:31.278554  ============================================================== 

 6224 22:59:31.281661  Config description: 

 6225 22:59:31.291982  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 6226 22:59:31.298177  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 6227 22:59:31.301132  SELPH_MODE            0: By rank         1: By Phase 

 6228 22:59:31.307930  ============================================================== 

 6229 22:59:31.311633  GAT_TRACK_EN                 =  0

 6230 22:59:31.314719  RX_GATING_MODE               =  2

 6231 22:59:31.317895  RX_GATING_TRACK_MODE         =  2

 6232 22:59:31.321496  SELPH_MODE                   =  1

 6233 22:59:31.321579  PICG_EARLY_EN                =  1

 6234 22:59:31.324290  VALID_LAT_VALUE              =  1

 6235 22:59:31.331200  ============================================================== 

 6236 22:59:31.334142  Enter into Gating configuration >>>> 

 6237 22:59:31.337897  Exit from Gating configuration <<<< 

 6238 22:59:31.341265  Enter into  DVFS_PRE_config >>>>> 

 6239 22:59:31.350906  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 6240 22:59:31.354467  Exit from  DVFS_PRE_config <<<<< 

 6241 22:59:31.357366  Enter into PICG configuration >>>> 

 6242 22:59:31.360889  Exit from PICG configuration <<<< 

 6243 22:59:31.363941  [RX_INPUT] configuration >>>>> 

 6244 22:59:31.367428  [RX_INPUT] configuration <<<<< 

 6245 22:59:31.373734  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 6246 22:59:31.377337  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 6247 22:59:31.383538  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 6248 22:59:31.390215  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 6249 22:59:31.397134  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 6250 22:59:31.403304  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 6251 22:59:31.406924  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 6252 22:59:31.409921  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 6253 22:59:31.413602  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 6254 22:59:31.420365  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 6255 22:59:31.423446  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 6256 22:59:31.426760  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6257 22:59:31.430146  =================================== 

 6258 22:59:31.433348  LPDDR4 DRAM CONFIGURATION

 6259 22:59:31.436461  =================================== 

 6260 22:59:31.436590  EX_ROW_EN[0]    = 0x0

 6261 22:59:31.439686  EX_ROW_EN[1]    = 0x0

 6262 22:59:31.443327  LP4Y_EN      = 0x0

 6263 22:59:31.443408  WORK_FSP     = 0x0

 6264 22:59:31.446187  WL           = 0x2

 6265 22:59:31.446281  RL           = 0x2

 6266 22:59:31.449791  BL           = 0x2

 6267 22:59:31.449872  RPST         = 0x0

 6268 22:59:31.452765  RD_PRE       = 0x0

 6269 22:59:31.452871  WR_PRE       = 0x1

 6270 22:59:31.456382  WR_PST       = 0x0

 6271 22:59:31.456477  DBI_WR       = 0x0

 6272 22:59:31.459919  DBI_RD       = 0x0

 6273 22:59:31.460000  OTF          = 0x1

 6274 22:59:31.462826  =================================== 

 6275 22:59:31.466392  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 6276 22:59:31.472988  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 6277 22:59:31.476392  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6278 22:59:31.479302  =================================== 

 6279 22:59:31.482929  LPDDR4 DRAM CONFIGURATION

 6280 22:59:31.486137  =================================== 

 6281 22:59:31.486220  EX_ROW_EN[0]    = 0x10

 6282 22:59:31.489718  EX_ROW_EN[1]    = 0x0

 6283 22:59:31.492790  LP4Y_EN      = 0x0

 6284 22:59:31.492872  WORK_FSP     = 0x0

 6285 22:59:31.495842  WL           = 0x2

 6286 22:59:31.495949  RL           = 0x2

 6287 22:59:31.499589  BL           = 0x2

 6288 22:59:31.499689  RPST         = 0x0

 6289 22:59:31.502739  RD_PRE       = 0x0

 6290 22:59:31.502822  WR_PRE       = 0x1

 6291 22:59:31.505744  WR_PST       = 0x0

 6292 22:59:31.505827  DBI_WR       = 0x0

 6293 22:59:31.509362  DBI_RD       = 0x0

 6294 22:59:31.509445  OTF          = 0x1

 6295 22:59:31.512445  =================================== 

 6296 22:59:31.519351  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 6297 22:59:31.523685  nWR fixed to 30

 6298 22:59:31.526776  [ModeRegInit_LP4] CH0 RK0

 6299 22:59:31.526860  [ModeRegInit_LP4] CH0 RK1

 6300 22:59:31.530313  [ModeRegInit_LP4] CH1 RK0

 6301 22:59:31.533293  [ModeRegInit_LP4] CH1 RK1

 6302 22:59:31.533376  match AC timing 19

 6303 22:59:31.540374  dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1

 6304 22:59:31.543543  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 6305 22:59:31.546647  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

 6306 22:59:31.553289  [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17

 6307 22:59:31.556288  [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)

 6308 22:59:31.556397  ==

 6309 22:59:31.559710  Dram Type= 6, Freq= 0, CH_0, rank 0

 6310 22:59:31.563251  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6311 22:59:31.563335  ==

 6312 22:59:31.569767  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6313 22:59:31.576320  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33

 6314 22:59:31.579903  [CA 0] Center 36 (8~64) winsize 57

 6315 22:59:31.582923  [CA 1] Center 36 (8~64) winsize 57

 6316 22:59:31.586455  [CA 2] Center 36 (8~64) winsize 57

 6317 22:59:31.589575  [CA 3] Center 36 (8~64) winsize 57

 6318 22:59:31.593194  [CA 4] Center 36 (8~64) winsize 57

 6319 22:59:31.593277  [CA 5] Center 36 (8~64) winsize 57

 6320 22:59:31.596305  

 6321 22:59:31.599776  [CmdBusTrainingLP45] Vref(ca) range 1: 33

 6322 22:59:31.599860  

 6323 22:59:31.602877  [CATrainingPosCal] consider 1 rank data

 6324 22:59:31.606056  u2DelayCellTimex100 = 270/100 ps

 6325 22:59:31.609827  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6326 22:59:31.612997  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6327 22:59:31.616032  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6328 22:59:31.619840  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6329 22:59:31.622935  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6330 22:59:31.626060  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6331 22:59:31.626143  

 6332 22:59:31.629186  CA PerBit enable=1, Macro0, CA PI delay=36

 6333 22:59:31.629294  

 6334 22:59:31.632889  [CBTSetCACLKResult] CA Dly = 36

 6335 22:59:31.635676  CS Dly: 1 (0~32)

 6336 22:59:31.635758  ==

 6337 22:59:31.639263  Dram Type= 6, Freq= 0, CH_0, rank 1

 6338 22:59:31.642510  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6339 22:59:31.642594  ==

 6340 22:59:31.649416  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6341 22:59:31.655865  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6342 22:59:31.658921  [CA 0] Center 36 (8~64) winsize 57

 6343 22:59:31.661941  [CA 1] Center 36 (8~64) winsize 57

 6344 22:59:31.665472  [CA 2] Center 36 (8~64) winsize 57

 6345 22:59:31.669007  [CA 3] Center 36 (8~64) winsize 57

 6346 22:59:31.669090  [CA 4] Center 36 (8~64) winsize 57

 6347 22:59:31.671906  [CA 5] Center 36 (8~64) winsize 57

 6348 22:59:31.671989  

 6349 22:59:31.678942  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6350 22:59:31.679027  

 6351 22:59:31.682032  [CATrainingPosCal] consider 2 rank data

 6352 22:59:31.685428  u2DelayCellTimex100 = 270/100 ps

 6353 22:59:31.688377  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6354 22:59:31.691915  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6355 22:59:31.695019  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6356 22:59:31.698735  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6357 22:59:31.701901  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6358 22:59:31.704947  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6359 22:59:31.705030  

 6360 22:59:31.708627  CA PerBit enable=1, Macro0, CA PI delay=36

 6361 22:59:31.708725  

 6362 22:59:31.711764  [CBTSetCACLKResult] CA Dly = 36

 6363 22:59:31.714966  CS Dly: 1 (0~32)

 6364 22:59:31.715046  

 6365 22:59:31.718085  ----->DramcWriteLeveling(PI) begin...

 6366 22:59:31.718166  ==

 6367 22:59:31.721761  Dram Type= 6, Freq= 0, CH_0, rank 0

 6368 22:59:31.724815  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6369 22:59:31.724897  ==

 6370 22:59:31.727995  Write leveling (Byte 0): 40 => 8

 6371 22:59:31.731711  Write leveling (Byte 1): 32 => 0

 6372 22:59:31.734850  DramcWriteLeveling(PI) end<-----

 6373 22:59:31.734931  

 6374 22:59:31.734995  ==

 6375 22:59:31.738324  Dram Type= 6, Freq= 0, CH_0, rank 0

 6376 22:59:31.741347  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6377 22:59:31.741427  ==

 6378 22:59:31.745260  [Gating] SW mode calibration

 6379 22:59:31.751446  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6380 22:59:31.757755  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6381 22:59:31.761314   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6382 22:59:31.767682   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6383 22:59:31.771189   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6384 22:59:31.774638   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6385 22:59:31.780759   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6386 22:59:31.784154   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6387 22:59:31.787324   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6388 22:59:31.794340   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6389 22:59:31.797242   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6390 22:59:31.800942  Total UI for P1: 0, mck2ui 16

 6391 22:59:31.804139  best dqsien dly found for B0: ( 0, 14, 24)

 6392 22:59:31.807231  Total UI for P1: 0, mck2ui 16

 6393 22:59:31.810230  best dqsien dly found for B1: ( 0, 14, 24)

 6394 22:59:31.814088  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6395 22:59:31.817070  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6396 22:59:31.817150  

 6397 22:59:31.820272  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6398 22:59:31.823851  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6399 22:59:31.826910  [Gating] SW calibration Done

 6400 22:59:31.826992  ==

 6401 22:59:31.830084  Dram Type= 6, Freq= 0, CH_0, rank 0

 6402 22:59:31.833698  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6403 22:59:31.837282  ==

 6404 22:59:31.837364  RX Vref Scan: 0

 6405 22:59:31.837430  

 6406 22:59:31.840326  RX Vref 0 -> 0, step: 1

 6407 22:59:31.840409  

 6408 22:59:31.843176  RX Delay -410 -> 252, step: 16

 6409 22:59:31.846705  iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496

 6410 22:59:31.850312  iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496

 6411 22:59:31.856339  iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496

 6412 22:59:31.860029  iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496

 6413 22:59:31.863024  iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512

 6414 22:59:31.866743  iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512

 6415 22:59:31.873189  iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512

 6416 22:59:31.876505  iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512

 6417 22:59:31.879485  iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512

 6418 22:59:31.883194  iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512

 6419 22:59:31.889714  iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512

 6420 22:59:31.892797  iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496

 6421 22:59:31.896041  iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512

 6422 22:59:31.899331  iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512

 6423 22:59:31.906015  iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496

 6424 22:59:31.909215  iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512

 6425 22:59:31.909300  ==

 6426 22:59:31.912866  Dram Type= 6, Freq= 0, CH_0, rank 0

 6427 22:59:31.915935  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6428 22:59:31.916019  ==

 6429 22:59:31.919677  DQS Delay:

 6430 22:59:31.919760  DQS0 = 43, DQS1 = 59

 6431 22:59:31.922897  DQM Delay:

 6432 22:59:31.922980  DQM0 = 10, DQM1 = 12

 6433 22:59:31.923045  DQ Delay:

 6434 22:59:31.925964  DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8

 6435 22:59:31.929481  DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16

 6436 22:59:31.932593  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8

 6437 22:59:31.935617  DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16

 6438 22:59:31.935700  

 6439 22:59:31.935765  

 6440 22:59:31.935826  ==

 6441 22:59:31.939208  Dram Type= 6, Freq= 0, CH_0, rank 0

 6442 22:59:31.946186  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6443 22:59:31.946295  ==

 6444 22:59:31.946387  

 6445 22:59:31.946475  

 6446 22:59:31.946562  	TX Vref Scan disable

 6447 22:59:31.948905   == TX Byte 0 ==

 6448 22:59:31.952293  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6449 22:59:31.955529  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6450 22:59:31.958631   == TX Byte 1 ==

 6451 22:59:31.962319  Update DQ  dly =572 (4 ,1, 28)  DQ  OEN =(3 ,2)

 6452 22:59:31.965418  Update DQM dly =572 (4 ,1, 28)  DQM OEN =(3 ,2)

 6453 22:59:31.968885  ==

 6454 22:59:31.971886  Dram Type= 6, Freq= 0, CH_0, rank 0

 6455 22:59:31.975468  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6456 22:59:31.975550  ==

 6457 22:59:31.975615  

 6458 22:59:31.975674  

 6459 22:59:31.978976  	TX Vref Scan disable

 6460 22:59:31.979058   == TX Byte 0 ==

 6461 22:59:31.981852  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6462 22:59:31.988926  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6463 22:59:31.989014   == TX Byte 1 ==

 6464 22:59:31.991672  Update DQ  dly =572 (4 ,1, 28)  DQ  OEN =(3 ,2)

 6465 22:59:31.998503  Update DQM dly =572 (4 ,1, 28)  DQM OEN =(3 ,2)

 6466 22:59:31.998596  

 6467 22:59:31.998685  [DATLAT]

 6468 22:59:31.998786  Freq=400, CH0 RK0

 6469 22:59:31.998863  

 6470 22:59:32.002068  DATLAT Default: 0xf

 6471 22:59:32.005081  0, 0xFFFF, sum = 0

 6472 22:59:32.005165  1, 0xFFFF, sum = 0

 6473 22:59:32.008636  2, 0xFFFF, sum = 0

 6474 22:59:32.008747  3, 0xFFFF, sum = 0

 6475 22:59:32.011833  4, 0xFFFF, sum = 0

 6476 22:59:32.011918  5, 0xFFFF, sum = 0

 6477 22:59:32.015539  6, 0xFFFF, sum = 0

 6478 22:59:32.015617  7, 0xFFFF, sum = 0

 6479 22:59:32.018620  8, 0xFFFF, sum = 0

 6480 22:59:32.018698  9, 0xFFFF, sum = 0

 6481 22:59:32.021771  10, 0xFFFF, sum = 0

 6482 22:59:32.021853  11, 0xFFFF, sum = 0

 6483 22:59:32.024819  12, 0xFFFF, sum = 0

 6484 22:59:32.024900  13, 0x0, sum = 1

 6485 22:59:32.028675  14, 0x0, sum = 2

 6486 22:59:32.028756  15, 0x0, sum = 3

 6487 22:59:32.031656  16, 0x0, sum = 4

 6488 22:59:32.031732  best_step = 14

 6489 22:59:32.031837  

 6490 22:59:32.031934  ==

 6491 22:59:32.034906  Dram Type= 6, Freq= 0, CH_0, rank 0

 6492 22:59:32.038537  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6493 22:59:32.041669  ==

 6494 22:59:32.041742  RX Vref Scan: 1

 6495 22:59:32.041825  

 6496 22:59:32.044751  RX Vref 0 -> 0, step: 1

 6497 22:59:32.044828  

 6498 22:59:32.048456  RX Delay -359 -> 252, step: 8

 6499 22:59:32.048606  

 6500 22:59:32.051489  Set Vref, RX VrefLevel [Byte0]: 60

 6501 22:59:32.054745                           [Byte1]: 49

 6502 22:59:32.054830  

 6503 22:59:32.057993  Final RX Vref Byte 0 = 60 to rank0

 6504 22:59:32.061545  Final RX Vref Byte 1 = 49 to rank0

 6505 22:59:32.064854  Final RX Vref Byte 0 = 60 to rank1

 6506 22:59:32.068067  Final RX Vref Byte 1 = 49 to rank1==

 6507 22:59:32.071020  Dram Type= 6, Freq= 0, CH_0, rank 0

 6508 22:59:32.074685  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6509 22:59:32.078100  ==

 6510 22:59:32.078183  DQS Delay:

 6511 22:59:32.078248  DQS0 = 48, DQS1 = 60

 6512 22:59:32.081729  DQM Delay:

 6513 22:59:32.081812  DQM0 = 11, DQM1 = 12

 6514 22:59:32.084583  DQ Delay:

 6515 22:59:32.084697  DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8

 6516 22:59:32.088104  DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20

 6517 22:59:32.091081  DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4

 6518 22:59:32.094618  DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20

 6519 22:59:32.094701  

 6520 22:59:32.094765  

 6521 22:59:32.104254  [DQSOSCAuto] RK0, (LSB)MR18= 0xba7d, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 386 ps

 6522 22:59:32.107750  CH0 RK0: MR19=C0C, MR18=BA7D

 6523 22:59:32.114351  CH0_RK0: MR19=0xC0C, MR18=0xBA7D, DQSOSC=386, MR23=63, INC=396, DEC=264

 6524 22:59:32.114434  ==

 6525 22:59:32.117441  Dram Type= 6, Freq= 0, CH_0, rank 1

 6526 22:59:32.120652  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6527 22:59:32.120735  ==

 6528 22:59:32.124427  [Gating] SW mode calibration

 6529 22:59:32.130630  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6530 22:59:32.137410  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6531 22:59:32.140356   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6532 22:59:32.144025   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6533 22:59:32.150300   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6534 22:59:32.153946   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6535 22:59:32.157769   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6536 22:59:32.163723   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6537 22:59:32.166764   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6538 22:59:32.170586   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6539 22:59:32.176644   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6540 22:59:32.176764  Total UI for P1: 0, mck2ui 16

 6541 22:59:32.180365  best dqsien dly found for B0: ( 0, 14, 24)

 6542 22:59:32.183280  Total UI for P1: 0, mck2ui 16

 6543 22:59:32.186878  best dqsien dly found for B1: ( 0, 14, 24)

 6544 22:59:32.193361  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6545 22:59:32.196437  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6546 22:59:32.196559  

 6547 22:59:32.199881  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6548 22:59:32.202965  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6549 22:59:32.206561  [Gating] SW calibration Done

 6550 22:59:32.206642  ==

 6551 22:59:32.209648  Dram Type= 6, Freq= 0, CH_0, rank 1

 6552 22:59:32.213151  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6553 22:59:32.213233  ==

 6554 22:59:32.216014  RX Vref Scan: 0

 6555 22:59:32.216096  

 6556 22:59:32.216159  RX Vref 0 -> 0, step: 1

 6557 22:59:32.216217  

 6558 22:59:32.219928  RX Delay -410 -> 252, step: 16

 6559 22:59:32.226059  iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496

 6560 22:59:32.229611  iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512

 6561 22:59:32.232635  iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496

 6562 22:59:32.236457  iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496

 6563 22:59:32.242757  iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496

 6564 22:59:32.246365  iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512

 6565 22:59:32.249474  iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512

 6566 22:59:32.252466  iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496

 6567 22:59:32.259195  iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496

 6568 22:59:32.262677  iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512

 6569 22:59:32.265668  iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512

 6570 22:59:32.269288  iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496

 6571 22:59:32.275558  iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496

 6572 22:59:32.279055  iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496

 6573 22:59:32.282094  iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496

 6574 22:59:32.289088  iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496

 6575 22:59:32.289172  ==

 6576 22:59:32.292128  Dram Type= 6, Freq= 0, CH_0, rank 1

 6577 22:59:32.295652  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6578 22:59:32.295757  ==

 6579 22:59:32.295845  DQS Delay:

 6580 22:59:32.298507  DQS0 = 43, DQS1 = 59

 6581 22:59:32.298589  DQM Delay:

 6582 22:59:32.302125  DQM0 = 11, DQM1 = 16

 6583 22:59:32.302208  DQ Delay:

 6584 22:59:32.305060  DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8

 6585 22:59:32.308759  DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24

 6586 22:59:32.311682  DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8

 6587 22:59:32.315109  DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24

 6588 22:59:32.315191  

 6589 22:59:32.315255  

 6590 22:59:32.315314  ==

 6591 22:59:32.318702  Dram Type= 6, Freq= 0, CH_0, rank 1

 6592 22:59:32.321780  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6593 22:59:32.321863  ==

 6594 22:59:32.321927  

 6595 22:59:32.321988  

 6596 22:59:32.325040  	TX Vref Scan disable

 6597 22:59:32.328109   == TX Byte 0 ==

 6598 22:59:32.331828  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6599 22:59:32.334952  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6600 22:59:32.338089   == TX Byte 1 ==

 6601 22:59:32.341849  Update DQ  dly =577 (4 ,2, 1)  DQ  OEN =(3 ,3)

 6602 22:59:32.344790  Update DQM dly =577 (4 ,2, 1)  DQM OEN =(3 ,3)

 6603 22:59:32.344873  ==

 6604 22:59:32.348048  Dram Type= 6, Freq= 0, CH_0, rank 1

 6605 22:59:32.351213  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6606 22:59:32.351295  ==

 6607 22:59:32.354872  

 6608 22:59:32.354954  

 6609 22:59:32.355018  	TX Vref Scan disable

 6610 22:59:32.357963   == TX Byte 0 ==

 6611 22:59:32.361659  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6612 22:59:32.364434  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6613 22:59:32.368120   == TX Byte 1 ==

 6614 22:59:32.371230  Update DQ  dly =577 (4 ,2, 1)  DQ  OEN =(3 ,3)

 6615 22:59:32.374385  Update DQM dly =577 (4 ,2, 1)  DQM OEN =(3 ,3)

 6616 22:59:32.374466  

 6617 22:59:32.374531  [DATLAT]

 6618 22:59:32.378024  Freq=400, CH0 RK1

 6619 22:59:32.378106  

 6620 22:59:32.380906  DATLAT Default: 0xe

 6621 22:59:32.380992  0, 0xFFFF, sum = 0

 6622 22:59:32.384490  1, 0xFFFF, sum = 0

 6623 22:59:32.384631  2, 0xFFFF, sum = 0

 6624 22:59:32.387510  3, 0xFFFF, sum = 0

 6625 22:59:32.387594  4, 0xFFFF, sum = 0

 6626 22:59:32.391121  5, 0xFFFF, sum = 0

 6627 22:59:32.391212  6, 0xFFFF, sum = 0

 6628 22:59:32.394058  7, 0xFFFF, sum = 0

 6629 22:59:32.394168  8, 0xFFFF, sum = 0

 6630 22:59:32.397689  9, 0xFFFF, sum = 0

 6631 22:59:32.397776  10, 0xFFFF, sum = 0

 6632 22:59:32.401280  11, 0xFFFF, sum = 0

 6633 22:59:32.401362  12, 0xFFFF, sum = 0

 6634 22:59:32.404642  13, 0x0, sum = 1

 6635 22:59:32.404725  14, 0x0, sum = 2

 6636 22:59:32.407647  15, 0x0, sum = 3

 6637 22:59:32.407758  16, 0x0, sum = 4

 6638 22:59:32.411164  best_step = 14

 6639 22:59:32.411246  

 6640 22:59:32.411311  ==

 6641 22:59:32.414688  Dram Type= 6, Freq= 0, CH_0, rank 1

 6642 22:59:32.417767  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6643 22:59:32.417851  ==

 6644 22:59:32.421138  RX Vref Scan: 0

 6645 22:59:32.421220  

 6646 22:59:32.421284  RX Vref 0 -> 0, step: 1

 6647 22:59:32.421344  

 6648 22:59:32.424239  RX Delay -359 -> 252, step: 8

 6649 22:59:32.432216  iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480

 6650 22:59:32.435298  iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488

 6651 22:59:32.438448  iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480

 6652 22:59:32.445303  iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488

 6653 22:59:32.448315  iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488

 6654 22:59:32.451933  iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488

 6655 22:59:32.455099  iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488

 6656 22:59:32.461823  iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488

 6657 22:59:32.464845  iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488

 6658 22:59:32.468415  iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488

 6659 22:59:32.471320  iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488

 6660 22:59:32.478074  iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488

 6661 22:59:32.481922  iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488

 6662 22:59:32.484896  iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496

 6663 22:59:32.488413  iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488

 6664 22:59:32.494903  iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488

 6665 22:59:32.494982  ==

 6666 22:59:32.498521  Dram Type= 6, Freq= 0, CH_0, rank 1

 6667 22:59:32.501435  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6668 22:59:32.501534  ==

 6669 22:59:32.501623  DQS Delay:

 6670 22:59:32.505066  DQS0 = 44, DQS1 = 60

 6671 22:59:32.505138  DQM Delay:

 6672 22:59:32.508616  DQM0 = 8, DQM1 = 15

 6673 22:59:32.508717  DQ Delay:

 6674 22:59:32.511567  DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =8

 6675 22:59:32.514632  DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16

 6676 22:59:32.518261  DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8

 6677 22:59:32.521307  DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24

 6678 22:59:32.521381  

 6679 22:59:32.521445  

 6680 22:59:32.527775  [DQSOSCAuto] RK1, (LSB)MR18= 0xb23f, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 387 ps

 6681 22:59:32.531476  CH0 RK1: MR19=C0C, MR18=B23F

 6682 22:59:32.538090  CH0_RK1: MR19=0xC0C, MR18=0xB23F, DQSOSC=387, MR23=63, INC=394, DEC=262

 6683 22:59:32.541252  [RxdqsGatingPostProcess] freq 400

 6684 22:59:32.547847  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 6685 22:59:32.547929  best DQS0 dly(2T, 0.5T) = (0, 10)

 6686 22:59:32.551029  best DQS1 dly(2T, 0.5T) = (0, 10)

 6687 22:59:32.554737  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6688 22:59:32.557874  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6689 22:59:32.561092  best DQS0 dly(2T, 0.5T) = (0, 10)

 6690 22:59:32.564713  best DQS1 dly(2T, 0.5T) = (0, 10)

 6691 22:59:32.567924  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6692 22:59:32.571331  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6693 22:59:32.575032  Pre-setting of DQS Precalculation

 6694 22:59:32.580928  [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14

 6695 22:59:32.581012  ==

 6696 22:59:32.584144  Dram Type= 6, Freq= 0, CH_1, rank 0

 6697 22:59:32.587911  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6698 22:59:32.587994  ==

 6699 22:59:32.593932  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6700 22:59:32.597542  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6701 22:59:32.601142  [CA 0] Center 36 (8~64) winsize 57

 6702 22:59:32.604085  [CA 1] Center 36 (8~64) winsize 57

 6703 22:59:32.607557  [CA 2] Center 36 (8~64) winsize 57

 6704 22:59:32.610415  [CA 3] Center 36 (8~64) winsize 57

 6705 22:59:32.613783  [CA 4] Center 36 (8~64) winsize 57

 6706 22:59:32.617440  [CA 5] Center 36 (8~64) winsize 57

 6707 22:59:32.617522  

 6708 22:59:32.620384  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6709 22:59:32.620466  

 6710 22:59:32.623981  [CATrainingPosCal] consider 1 rank data

 6711 22:59:32.627120  u2DelayCellTimex100 = 270/100 ps

 6712 22:59:32.630604  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6713 22:59:32.633623  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6714 22:59:32.640403  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6715 22:59:32.643441  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6716 22:59:32.647041  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6717 22:59:32.650286  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6718 22:59:32.650368  

 6719 22:59:32.653280  CA PerBit enable=1, Macro0, CA PI delay=36

 6720 22:59:32.653363  

 6721 22:59:32.657095  [CBTSetCACLKResult] CA Dly = 36

 6722 22:59:32.657177  CS Dly: 1 (0~32)

 6723 22:59:32.660196  ==

 6724 22:59:32.663174  Dram Type= 6, Freq= 0, CH_1, rank 1

 6725 22:59:32.666900  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6726 22:59:32.666983  ==

 6727 22:59:32.670186  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6728 22:59:32.676291  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 6729 22:59:32.679671  [CA 0] Center 36 (8~64) winsize 57

 6730 22:59:32.683374  [CA 1] Center 36 (8~64) winsize 57

 6731 22:59:32.686374  [CA 2] Center 36 (8~64) winsize 57

 6732 22:59:32.690082  [CA 3] Center 36 (8~64) winsize 57

 6733 22:59:32.693024  [CA 4] Center 36 (8~64) winsize 57

 6734 22:59:32.696735  [CA 5] Center 36 (8~64) winsize 57

 6735 22:59:32.696818  

 6736 22:59:32.699792  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 6737 22:59:32.699875  

 6738 22:59:32.702740  [CATrainingPosCal] consider 2 rank data

 6739 22:59:32.706310  u2DelayCellTimex100 = 270/100 ps

 6740 22:59:32.709647  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6741 22:59:32.712771  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6742 22:59:32.716378  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6743 22:59:32.722671  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6744 22:59:32.726275  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6745 22:59:32.729363  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6746 22:59:32.729446  

 6747 22:59:32.732444  CA PerBit enable=1, Macro0, CA PI delay=36

 6748 22:59:32.732570  

 6749 22:59:32.735958  [CBTSetCACLKResult] CA Dly = 36

 6750 22:59:32.736041  CS Dly: 1 (0~32)

 6751 22:59:32.736107  

 6752 22:59:32.739002  ----->DramcWriteLeveling(PI) begin...

 6753 22:59:32.742769  ==

 6754 22:59:32.742852  Dram Type= 6, Freq= 0, CH_1, rank 0

 6755 22:59:32.749023  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6756 22:59:32.749106  ==

 6757 22:59:32.752794  Write leveling (Byte 0): 40 => 8

 6758 22:59:32.755819  Write leveling (Byte 1): 32 => 0

 6759 22:59:32.755902  DramcWriteLeveling(PI) end<-----

 6760 22:59:32.758864  

 6761 22:59:32.758947  ==

 6762 22:59:32.762670  Dram Type= 6, Freq= 0, CH_1, rank 0

 6763 22:59:32.765642  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6764 22:59:32.765737  ==

 6765 22:59:32.769289  [Gating] SW mode calibration

 6766 22:59:32.775499  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6767 22:59:32.779090  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6768 22:59:32.785658   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6769 22:59:32.788486   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6770 22:59:32.792319   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6771 22:59:32.798903   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6772 22:59:32.801860   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6773 22:59:32.805497   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6774 22:59:32.811958   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6775 22:59:32.814933   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6776 22:59:32.818583   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6777 22:59:32.821936  Total UI for P1: 0, mck2ui 16

 6778 22:59:32.825043  best dqsien dly found for B0: ( 0, 14, 24)

 6779 22:59:32.828640  Total UI for P1: 0, mck2ui 16

 6780 22:59:32.831683  best dqsien dly found for B1: ( 0, 14, 24)

 6781 22:59:32.834672  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6782 22:59:32.841870  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6783 22:59:32.841952  

 6784 22:59:32.844836  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6785 22:59:32.847865  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6786 22:59:32.851595  [Gating] SW calibration Done

 6787 22:59:32.851695  ==

 6788 22:59:32.854697  Dram Type= 6, Freq= 0, CH_1, rank 0

 6789 22:59:32.857821  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6790 22:59:32.857903  ==

 6791 22:59:32.861484  RX Vref Scan: 0

 6792 22:59:32.861579  

 6793 22:59:32.861670  RX Vref 0 -> 0, step: 1

 6794 22:59:32.861768  

 6795 22:59:32.864674  RX Delay -410 -> 252, step: 16

 6796 22:59:32.868402  iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512

 6797 22:59:32.874520  iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496

 6798 22:59:32.878105  iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512

 6799 22:59:32.880982  iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496

 6800 22:59:32.884462  iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496

 6801 22:59:32.891012  iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496

 6802 22:59:32.894147  iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496

 6803 22:59:32.897772  iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496

 6804 22:59:32.904523  iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496

 6805 22:59:32.907467  iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512

 6806 22:59:32.911017  iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512

 6807 22:59:32.914127  iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496

 6808 22:59:32.920925  iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512

 6809 22:59:32.923804  iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512

 6810 22:59:32.927316  iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512

 6811 22:59:32.930411  iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512

 6812 22:59:32.933903  ==

 6813 22:59:32.936984  Dram Type= 6, Freq= 0, CH_1, rank 0

 6814 22:59:32.940721  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6815 22:59:32.940829  ==

 6816 22:59:32.941024  DQS Delay:

 6817 22:59:32.943612  DQS0 = 43, DQS1 = 51

 6818 22:59:32.943682  DQM Delay:

 6819 22:59:32.947132  DQM0 = 12, DQM1 = 14

 6820 22:59:32.947227  DQ Delay:

 6821 22:59:32.950356  DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8

 6822 22:59:32.953555  DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8

 6823 22:59:32.957118  DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0

 6824 22:59:32.960274  DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24

 6825 22:59:32.960378  

 6826 22:59:32.960467  

 6827 22:59:32.960590  ==

 6828 22:59:32.963993  Dram Type= 6, Freq= 0, CH_1, rank 0

 6829 22:59:32.967081  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6830 22:59:32.967196  ==

 6831 22:59:32.967285  

 6832 22:59:32.967383  

 6833 22:59:32.970266  	TX Vref Scan disable

 6834 22:59:32.970334   == TX Byte 0 ==

 6835 22:59:32.976904  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6836 22:59:32.979976  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6837 22:59:32.980058   == TX Byte 1 ==

 6838 22:59:32.986784  Update DQ  dly =572 (4 ,1, 28)  DQ  OEN =(3 ,2)

 6839 22:59:32.990189  Update DQM dly =572 (4 ,1, 28)  DQM OEN =(3 ,2)

 6840 22:59:32.990271  ==

 6841 22:59:32.993343  Dram Type= 6, Freq= 0, CH_1, rank 0

 6842 22:59:32.996939  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6843 22:59:32.997021  ==

 6844 22:59:32.997086  

 6845 22:59:32.997144  

 6846 22:59:33.000039  	TX Vref Scan disable

 6847 22:59:33.003098   == TX Byte 0 ==

 6848 22:59:33.006726  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6849 22:59:33.009725  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6850 22:59:33.013272   == TX Byte 1 ==

 6851 22:59:33.016753  Update DQ  dly =572 (4 ,1, 28)  DQ  OEN =(3 ,2)

 6852 22:59:33.019777  Update DQM dly =572 (4 ,1, 28)  DQM OEN =(3 ,2)

 6853 22:59:33.019877  

 6854 22:59:33.019966  [DATLAT]

 6855 22:59:33.023411  Freq=400, CH1 RK0

 6856 22:59:33.023493  

 6857 22:59:33.023556  DATLAT Default: 0xf

 6858 22:59:33.026339  0, 0xFFFF, sum = 0

 6859 22:59:33.029915  1, 0xFFFF, sum = 0

 6860 22:59:33.030062  2, 0xFFFF, sum = 0

 6861 22:59:33.032793  3, 0xFFFF, sum = 0

 6862 22:59:33.032876  4, 0xFFFF, sum = 0

 6863 22:59:33.036311  5, 0xFFFF, sum = 0

 6864 22:59:33.036413  6, 0xFFFF, sum = 0

 6865 22:59:33.039807  7, 0xFFFF, sum = 0

 6866 22:59:33.039889  8, 0xFFFF, sum = 0

 6867 22:59:33.042846  9, 0xFFFF, sum = 0

 6868 22:59:33.042929  10, 0xFFFF, sum = 0

 6869 22:59:33.045994  11, 0xFFFF, sum = 0

 6870 22:59:33.046076  12, 0xFFFF, sum = 0

 6871 22:59:33.049434  13, 0x0, sum = 1

 6872 22:59:33.049517  14, 0x0, sum = 2

 6873 22:59:33.052928  15, 0x0, sum = 3

 6874 22:59:33.053010  16, 0x0, sum = 4

 6875 22:59:33.056037  best_step = 14

 6876 22:59:33.056117  

 6877 22:59:33.056247  ==

 6878 22:59:33.059062  Dram Type= 6, Freq= 0, CH_1, rank 0

 6879 22:59:33.063026  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6880 22:59:33.063146  ==

 6881 22:59:33.066075  RX Vref Scan: 1

 6882 22:59:33.066147  

 6883 22:59:33.066207  RX Vref 0 -> 0, step: 1

 6884 22:59:33.066264  

 6885 22:59:33.069322  RX Delay -343 -> 252, step: 8

 6886 22:59:33.069403  

 6887 22:59:33.072453  Set Vref, RX VrefLevel [Byte0]: 45

 6888 22:59:33.075570                           [Byte1]: 57

 6889 22:59:33.080354  

 6890 22:59:33.080435  Final RX Vref Byte 0 = 45 to rank0

 6891 22:59:33.083464  Final RX Vref Byte 1 = 57 to rank0

 6892 22:59:33.087227  Final RX Vref Byte 0 = 45 to rank1

 6893 22:59:33.090260  Final RX Vref Byte 1 = 57 to rank1==

 6894 22:59:33.093870  Dram Type= 6, Freq= 0, CH_1, rank 0

 6895 22:59:33.100418  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6896 22:59:33.100500  ==

 6897 22:59:33.100604  DQS Delay:

 6898 22:59:33.103442  DQS0 = 44, DQS1 = 56

 6899 22:59:33.103523  DQM Delay:

 6900 22:59:33.103588  DQM0 = 9, DQM1 = 14

 6901 22:59:33.107103  DQ Delay:

 6902 22:59:33.110177  DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4

 6903 22:59:33.110258  DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8

 6904 22:59:33.113247  DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =4

 6905 22:59:33.116735  DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24

 6906 22:59:33.116816  

 6907 22:59:33.116881  

 6908 22:59:33.126785  [DQSOSCAuto] RK0, (LSB)MR18= 0x956c, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps

 6909 22:59:33.129896  CH1 RK0: MR19=C0C, MR18=956C

 6910 22:59:33.136288  CH1_RK0: MR19=0xC0C, MR18=0x956C, DQSOSC=391, MR23=63, INC=386, DEC=257

 6911 22:59:33.136401  ==

 6912 22:59:33.139826  Dram Type= 6, Freq= 0, CH_1, rank 1

 6913 22:59:33.143253  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6914 22:59:33.143336  ==

 6915 22:59:33.146359  [Gating] SW mode calibration

 6916 22:59:33.153016  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6917 22:59:33.159610  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6918 22:59:33.163236   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6919 22:59:33.166297   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6920 22:59:33.173248   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6921 22:59:33.176274   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6922 22:59:33.179412   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6923 22:59:33.186291   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6924 22:59:33.189336   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6925 22:59:33.193166   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6926 22:59:33.199413   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6927 22:59:33.199523  Total UI for P1: 0, mck2ui 16

 6928 22:59:33.202683  best dqsien dly found for B0: ( 0, 14, 24)

 6929 22:59:33.206337  Total UI for P1: 0, mck2ui 16

 6930 22:59:33.209301  best dqsien dly found for B1: ( 0, 14, 24)

 6931 22:59:33.215944  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6932 22:59:33.219042  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6933 22:59:33.219150  

 6934 22:59:33.222582  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6935 22:59:33.226033  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6936 22:59:33.228905  [Gating] SW calibration Done

 6937 22:59:33.229021  ==

 6938 22:59:33.232417  Dram Type= 6, Freq= 0, CH_1, rank 1

 6939 22:59:33.235970  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6940 22:59:33.236081  ==

 6941 22:59:33.238986  RX Vref Scan: 0

 6942 22:59:33.239092  

 6943 22:59:33.239190  RX Vref 0 -> 0, step: 1

 6944 22:59:33.239283  

 6945 22:59:33.242099  RX Delay -410 -> 252, step: 16

 6946 22:59:33.249088  iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496

 6947 22:59:33.252033  iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496

 6948 22:59:33.255221  iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496

 6949 22:59:33.258796  iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496

 6950 22:59:33.265570  iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496

 6951 22:59:33.268675  iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496

 6952 22:59:33.271790  iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496

 6953 22:59:33.275543  iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496

 6954 22:59:33.282304  iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496

 6955 22:59:33.285418  iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512

 6956 22:59:33.288500  iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512

 6957 22:59:33.291637  iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512

 6958 22:59:33.298450  iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512

 6959 22:59:33.302051  iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512

 6960 22:59:33.304934  iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512

 6961 22:59:33.311513  iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512

 6962 22:59:33.311596  ==

 6963 22:59:33.315357  Dram Type= 6, Freq= 0, CH_1, rank 1

 6964 22:59:33.318464  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6965 22:59:33.318571  ==

 6966 22:59:33.318664  DQS Delay:

 6967 22:59:33.321378  DQS0 = 51, DQS1 = 51

 6968 22:59:33.321459  DQM Delay:

 6969 22:59:33.325030  DQM0 = 18, DQM1 = 15

 6970 22:59:33.325118  DQ Delay:

 6971 22:59:33.328158  DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16

 6972 22:59:33.331573  DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16

 6973 22:59:33.334736  DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =8

 6974 22:59:33.338220  DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24

 6975 22:59:33.338328  

 6976 22:59:33.338438  

 6977 22:59:33.338530  ==

 6978 22:59:33.341188  Dram Type= 6, Freq= 0, CH_1, rank 1

 6979 22:59:33.344733  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6980 22:59:33.344844  ==

 6981 22:59:33.344938  

 6982 22:59:33.345027  

 6983 22:59:33.347703  	TX Vref Scan disable

 6984 22:59:33.351277   == TX Byte 0 ==

 6985 22:59:33.354989  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6986 22:59:33.357997  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6987 22:59:33.358118   == TX Byte 1 ==

 6988 22:59:33.364692  Update DQ  dly =577 (4 ,2, 1)  DQ  OEN =(3 ,3)

 6989 22:59:33.367689  Update DQM dly =577 (4 ,2, 1)  DQM OEN =(3 ,3)

 6990 22:59:33.367796  ==

 6991 22:59:33.371298  Dram Type= 6, Freq= 0, CH_1, rank 1

 6992 22:59:33.374371  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6993 22:59:33.374487  ==

 6994 22:59:33.374585  

 6995 22:59:33.377469  

 6996 22:59:33.377577  	TX Vref Scan disable

 6997 22:59:33.381168   == TX Byte 0 ==

 6998 22:59:33.384374  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6999 22:59:33.387283  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 7000 22:59:33.391038   == TX Byte 1 ==

 7001 22:59:33.394072  Update DQ  dly =577 (4 ,2, 1)  DQ  OEN =(3 ,3)

 7002 22:59:33.397842  Update DQM dly =577 (4 ,2, 1)  DQM OEN =(3 ,3)

 7003 22:59:33.397923  

 7004 22:59:33.398005  [DATLAT]

 7005 22:59:33.400926  Freq=400, CH1 RK1

 7006 22:59:33.401010  

 7007 22:59:33.401094  DATLAT Default: 0xe

 7008 22:59:33.403960  0, 0xFFFF, sum = 0

 7009 22:59:33.407221  1, 0xFFFF, sum = 0

 7010 22:59:33.407346  2, 0xFFFF, sum = 0

 7011 22:59:33.410880  3, 0xFFFF, sum = 0

 7012 22:59:33.410965  4, 0xFFFF, sum = 0

 7013 22:59:33.413945  5, 0xFFFF, sum = 0

 7014 22:59:33.414032  6, 0xFFFF, sum = 0

 7015 22:59:33.417054  7, 0xFFFF, sum = 0

 7016 22:59:33.417139  8, 0xFFFF, sum = 0

 7017 22:59:33.420720  9, 0xFFFF, sum = 0

 7018 22:59:33.420806  10, 0xFFFF, sum = 0

 7019 22:59:33.423860  11, 0xFFFF, sum = 0

 7020 22:59:33.423949  12, 0xFFFF, sum = 0

 7021 22:59:33.426945  13, 0x0, sum = 1

 7022 22:59:33.427031  14, 0x0, sum = 2

 7023 22:59:33.430487  15, 0x0, sum = 3

 7024 22:59:33.430572  16, 0x0, sum = 4

 7025 22:59:33.433623  best_step = 14

 7026 22:59:33.433707  

 7027 22:59:33.433807  ==

 7028 22:59:33.437106  Dram Type= 6, Freq= 0, CH_1, rank 1

 7029 22:59:33.440492  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 7030 22:59:33.440594  ==

 7031 22:59:33.444077  RX Vref Scan: 0

 7032 22:59:33.444201  

 7033 22:59:33.444318  RX Vref 0 -> 0, step: 1

 7034 22:59:33.444432  

 7035 22:59:33.446936  RX Delay -343 -> 252, step: 8

 7036 22:59:33.454753  iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480

 7037 22:59:33.458287  iDelay=217, Bit 1, Center -40 (-279 ~ 200) 480

 7038 22:59:33.461475  iDelay=217, Bit 2, Center -48 (-287 ~ 192) 480

 7039 22:59:33.467964  iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480

 7040 22:59:33.471120  iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488

 7041 22:59:33.474034  iDelay=217, Bit 5, Center -24 (-263 ~ 216) 480

 7042 22:59:33.477859  iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480

 7043 22:59:33.484546  iDelay=217, Bit 7, Center -36 (-279 ~ 208) 488

 7044 22:59:33.487688  iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496

 7045 22:59:33.490836  iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496

 7046 22:59:33.494525  iDelay=217, Bit 10, Center -44 (-295 ~ 208) 504

 7047 22:59:33.500828  iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496

 7048 22:59:33.504509  iDelay=217, Bit 12, Center -36 (-287 ~ 216) 504

 7049 22:59:33.507452  iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496

 7050 22:59:33.513946  iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496

 7051 22:59:33.517771  iDelay=217, Bit 15, Center -36 (-287 ~ 216) 504

 7052 22:59:33.518293  ==

 7053 22:59:33.520966  Dram Type= 6, Freq= 0, CH_1, rank 1

 7054 22:59:33.524082  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 7055 22:59:33.524565  ==

 7056 22:59:33.527152  DQS Delay:

 7057 22:59:33.527579  DQS0 = 48, DQS1 = 56

 7058 22:59:33.527914  DQM Delay:

 7059 22:59:33.530632  DQM0 = 13, DQM1 = 10

 7060 22:59:33.531071  DQ Delay:

 7061 22:59:33.534349  DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8

 7062 22:59:33.537200  DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12

 7063 22:59:33.540708  DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0

 7064 22:59:33.543804  DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20

 7065 22:59:33.544233  

 7066 22:59:33.544634  

 7067 22:59:33.554065  [DQSOSCAuto] RK1, (LSB)MR18= 0x6756, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps

 7068 22:59:33.554532  CH1 RK1: MR19=C0C, MR18=6756

 7069 22:59:33.560795  CH1_RK1: MR19=0xC0C, MR18=0x6756, DQSOSC=396, MR23=63, INC=376, DEC=251

 7070 22:59:33.563650  [RxdqsGatingPostProcess] freq 400

 7071 22:59:33.570704  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 7072 22:59:33.573614  best DQS0 dly(2T, 0.5T) = (0, 10)

 7073 22:59:33.576706  best DQS1 dly(2T, 0.5T) = (0, 10)

 7074 22:59:33.580281  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 7075 22:59:33.583344  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 7076 22:59:33.587108  best DQS0 dly(2T, 0.5T) = (0, 10)

 7077 22:59:33.587682  best DQS1 dly(2T, 0.5T) = (0, 10)

 7078 22:59:33.590398  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 7079 22:59:33.594003  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 7080 22:59:33.596984  Pre-setting of DQS Precalculation

 7081 22:59:33.603241  [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14

 7082 22:59:33.609973  sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6

 7083 22:59:33.616666  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 7084 22:59:33.617095  

 7085 22:59:33.617432  

 7086 22:59:33.619677  [Calibration Summary] 800 Mbps

 7087 22:59:33.623265  CH 0, Rank 0

 7088 22:59:33.623685  SW Impedance     : PASS

 7089 22:59:33.626270  DUTY Scan        : NO K

 7090 22:59:33.630103  ZQ Calibration   : PASS

 7091 22:59:33.630528  Jitter Meter     : NO K

 7092 22:59:33.633013  CBT Training     : PASS

 7093 22:59:33.636021  Write leveling   : PASS

 7094 22:59:33.636472  RX DQS gating    : PASS

 7095 22:59:33.639540  RX DQ/DQS(RDDQC) : PASS

 7096 22:59:33.640010  TX DQ/DQS        : PASS

 7097 22:59:33.643142  RX DATLAT        : PASS

 7098 22:59:33.646120  RX DQ/DQS(Engine): PASS

 7099 22:59:33.646604  TX OE            : NO K

 7100 22:59:33.649440  All Pass.

 7101 22:59:33.649860  

 7102 22:59:33.650189  CH 0, Rank 1

 7103 22:59:33.653156  SW Impedance     : PASS

 7104 22:59:33.653578  DUTY Scan        : NO K

 7105 22:59:33.656051  ZQ Calibration   : PASS

 7106 22:59:33.659816  Jitter Meter     : NO K

 7107 22:59:33.660407  CBT Training     : PASS

 7108 22:59:33.662720  Write leveling   : NO K

 7109 22:59:33.666717  RX DQS gating    : PASS

 7110 22:59:33.667196  RX DQ/DQS(RDDQC) : PASS

 7111 22:59:33.669078  TX DQ/DQS        : PASS

 7112 22:59:33.672723  RX DATLAT        : PASS

 7113 22:59:33.673224  RX DQ/DQS(Engine): PASS

 7114 22:59:33.675907  TX OE            : NO K

 7115 22:59:33.676569  All Pass.

 7116 22:59:33.676976  

 7117 22:59:33.679285  CH 1, Rank 0

 7118 22:59:33.679717  SW Impedance     : PASS

 7119 22:59:33.682483  DUTY Scan        : NO K

 7120 22:59:33.686157  ZQ Calibration   : PASS

 7121 22:59:33.686633  Jitter Meter     : NO K

 7122 22:59:33.689154  CBT Training     : PASS

 7123 22:59:33.692781  Write leveling   : PASS

 7124 22:59:33.693310  RX DQS gating    : PASS

 7125 22:59:33.695711  RX DQ/DQS(RDDQC) : PASS

 7126 22:59:33.698798  TX DQ/DQS        : PASS

 7127 22:59:33.699298  RX DATLAT        : PASS

 7128 22:59:33.702348  RX DQ/DQS(Engine): PASS

 7129 22:59:33.705585  TX OE            : NO K

 7130 22:59:33.706343  All Pass.

 7131 22:59:33.706955  

 7132 22:59:33.707648  CH 1, Rank 1

 7133 22:59:33.709344  SW Impedance     : PASS

 7134 22:59:33.712181  DUTY Scan        : NO K

 7135 22:59:33.712642  ZQ Calibration   : PASS

 7136 22:59:33.715350  Jitter Meter     : NO K

 7137 22:59:33.715797  CBT Training     : PASS

 7138 22:59:33.719071  Write leveling   : NO K

 7139 22:59:33.721942  RX DQS gating    : PASS

 7140 22:59:33.722383  RX DQ/DQS(RDDQC) : PASS

 7141 22:59:33.725700  TX DQ/DQS        : PASS

 7142 22:59:33.728655  RX DATLAT        : PASS

 7143 22:59:33.729094  RX DQ/DQS(Engine): PASS

 7144 22:59:33.732346  TX OE            : NO K

 7145 22:59:33.732825  All Pass.

 7146 22:59:33.733162  

 7147 22:59:33.735417  DramC Write-DBI off

 7148 22:59:33.738781  	PER_BANK_REFRESH: Hybrid Mode

 7149 22:59:33.739284  TX_TRACKING: ON

 7150 22:59:33.748694  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0

 7151 22:59:33.752131  [FAST_K] Save calibration result to emmc

 7152 22:59:33.754888  dramc_set_vcore_voltage set vcore to 725000

 7153 22:59:33.758452  Read voltage for 1600, 0

 7154 22:59:33.758886  Vio18 = 0

 7155 22:59:33.761445  Vcore = 725000

 7156 22:59:33.761886  Vdram = 0

 7157 22:59:33.762222  Vddq = 0

 7158 22:59:33.762534  Vmddr = 0

 7159 22:59:33.768587  [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0

 7160 22:59:33.774690  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 7161 22:59:33.775277  MEM_TYPE=3, freq_sel=13

 7162 22:59:33.778193  sv_algorithm_assistance_LP4_3733 

 7163 22:59:33.781179  ============ PULL DRAM RESETB DOWN ============

 7164 22:59:33.787782  ========== PULL DRAM RESETB DOWN end =========

 7165 22:59:33.791521  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7166 22:59:33.794732  =================================== 

 7167 22:59:33.797595  LPDDR4 DRAM CONFIGURATION

 7168 22:59:33.801304  =================================== 

 7169 22:59:33.801883  EX_ROW_EN[0]    = 0x0

 7170 22:59:33.804355  EX_ROW_EN[1]    = 0x0

 7171 22:59:33.807986  LP4Y_EN      = 0x0

 7172 22:59:33.808577  WORK_FSP     = 0x1

 7173 22:59:33.811085  WL           = 0x5

 7174 22:59:33.811707  RL           = 0x5

 7175 22:59:33.814491  BL           = 0x2

 7176 22:59:33.815059  RPST         = 0x0

 7177 22:59:33.817554  RD_PRE       = 0x0

 7178 22:59:33.818127  WR_PRE       = 0x1

 7179 22:59:33.821362  WR_PST       = 0x1

 7180 22:59:33.821826  DBI_WR       = 0x0

 7181 22:59:33.824289  DBI_RD       = 0x0

 7182 22:59:33.824760  OTF          = 0x1

 7183 22:59:33.827508  =================================== 

 7184 22:59:33.831127  =================================== 

 7185 22:59:33.834277  ANA top config

 7186 22:59:33.837255  =================================== 

 7187 22:59:33.837796  DLL_ASYNC_EN            =  0

 7188 22:59:33.840854  ALL_SLAVE_EN            =  0

 7189 22:59:33.844189  NEW_RANK_MODE           =  1

 7190 22:59:33.846950  DLL_IDLE_MODE           =  1

 7191 22:59:33.850717  LP45_APHY_COMB_EN       =  1

 7192 22:59:33.851140  TX_ODT_DIS              =  0

 7193 22:59:33.853675  NEW_8X_MODE             =  1

 7194 22:59:33.857099  =================================== 

 7195 22:59:33.860630  =================================== 

 7196 22:59:33.864078  data_rate                  = 3200

 7197 22:59:33.867141  CKR                        = 1

 7198 22:59:33.870603  DQ_P2S_RATIO               = 8

 7199 22:59:33.873742  =================================== 

 7200 22:59:33.876617  CA_P2S_RATIO               = 8

 7201 22:59:33.877040  DQ_CA_OPEN                 = 0

 7202 22:59:33.880274  DQ_SEMI_OPEN               = 0

 7203 22:59:33.883388  CA_SEMI_OPEN               = 0

 7204 22:59:33.887046  CA_FULL_RATE               = 0

 7205 22:59:33.889998  DQ_CKDIV4_EN               = 0

 7206 22:59:33.893722  CA_CKDIV4_EN               = 0

 7207 22:59:33.894144  CA_PREDIV_EN               = 0

 7208 22:59:33.896997  PH8_DLY                    = 12

 7209 22:59:33.899936  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 7210 22:59:33.902870  DQ_AAMCK_DIV               = 4

 7211 22:59:33.906669  CA_AAMCK_DIV               = 4

 7212 22:59:33.909771  CA_ADMCK_DIV               = 4

 7213 22:59:33.910219  DQ_TRACK_CA_EN             = 0

 7214 22:59:33.913452  CA_PICK                    = 1600

 7215 22:59:33.916590  CA_MCKIO                   = 1600

 7216 22:59:33.919700  MCKIO_SEMI                 = 0

 7217 22:59:33.923198  PLL_FREQ                   = 3068

 7218 22:59:33.926190  DQ_UI_PI_RATIO             = 32

 7219 22:59:33.929426  CA_UI_PI_RATIO             = 0

 7220 22:59:33.932974  =================================== 

 7221 22:59:33.936050  =================================== 

 7222 22:59:33.936472  memory_type:LPDDR4         

 7223 22:59:33.939830  GP_NUM     : 10       

 7224 22:59:33.942898  SRAM_EN    : 1       

 7225 22:59:33.943438  MD32_EN    : 0       

 7226 22:59:33.946429  =================================== 

 7227 22:59:33.949585  [ANA_INIT] >>>>>>>>>>>>>> 

 7228 22:59:33.952689  <<<<<< [CONFIGURE PHASE]: ANA_TX

 7229 22:59:33.955894  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 7230 22:59:33.959417  =================================== 

 7231 22:59:33.963034  data_rate = 3200,PCW = 0X7600

 7232 22:59:33.965953  =================================== 

 7233 22:59:33.969586  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 7234 22:59:33.972403  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 7235 22:59:33.979481  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 7236 22:59:33.986026  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 7237 22:59:33.989218  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 7238 22:59:33.992278  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 7239 22:59:33.992743  [ANA_INIT] flow start 

 7240 22:59:33.995915  [ANA_INIT] PLL >>>>>>>> 

 7241 22:59:33.998945  [ANA_INIT] PLL <<<<<<<< 

 7242 22:59:33.999363  [ANA_INIT] MIDPI >>>>>>>> 

 7243 22:59:34.002242  [ANA_INIT] MIDPI <<<<<<<< 

 7244 22:59:34.005637  [ANA_INIT] DLL >>>>>>>> 

 7245 22:59:34.006145  [ANA_INIT] DLL <<<<<<<< 

 7246 22:59:34.008971  [ANA_INIT] flow end 

 7247 22:59:34.011916  ============ LP4 DIFF to SE enter ============

 7248 22:59:34.018627  ============ LP4 DIFF to SE exit  ============

 7249 22:59:34.019051  [ANA_INIT] <<<<<<<<<<<<< 

 7250 22:59:34.022307  [Flow] Enable top DCM control >>>>> 

 7251 22:59:34.025357  [Flow] Enable top DCM control <<<<< 

 7252 22:59:34.029144  Enable DLL master slave shuffle 

 7253 22:59:34.035306  ============================================================== 

 7254 22:59:34.035747  Gating Mode config

 7255 22:59:34.041932  ============================================================== 

 7256 22:59:34.045111  Config description: 

 7257 22:59:34.051724  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 7258 22:59:34.061285  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 7259 22:59:34.064766  SELPH_MODE            0: By rank         1: By Phase 

 7260 22:59:34.071074  ============================================================== 

 7261 22:59:34.074656  GAT_TRACK_EN                 =  1

 7262 22:59:34.075075  RX_GATING_MODE               =  2

 7263 22:59:34.077780  RX_GATING_TRACK_MODE         =  2

 7264 22:59:34.081315  SELPH_MODE                   =  1

 7265 22:59:34.084868  PICG_EARLY_EN                =  1

 7266 22:59:34.087911  VALID_LAT_VALUE              =  1

 7267 22:59:34.094589  ============================================================== 

 7268 22:59:34.098082  Enter into Gating configuration >>>> 

 7269 22:59:34.101242  Exit from Gating configuration <<<< 

 7270 22:59:34.104198  Enter into  DVFS_PRE_config >>>>> 

 7271 22:59:34.114067  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 7272 22:59:34.117875  Exit from  DVFS_PRE_config <<<<< 

 7273 22:59:34.120660  Enter into PICG configuration >>>> 

 7274 22:59:34.124378  Exit from PICG configuration <<<< 

 7275 22:59:34.127912  [RX_INPUT] configuration >>>>> 

 7276 22:59:34.131103  [RX_INPUT] configuration <<<<< 

 7277 22:59:34.134084  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 7278 22:59:34.141035  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 7279 22:59:34.147675  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 7280 22:59:34.154171  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 7281 22:59:34.157414  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 7282 22:59:34.164563  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 7283 22:59:34.167267  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 7284 22:59:34.173907  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 7285 22:59:34.177225  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 7286 22:59:34.180772  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 7287 22:59:34.183473  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 7288 22:59:34.190387  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7289 22:59:34.193567  =================================== 

 7290 22:59:34.197315  LPDDR4 DRAM CONFIGURATION

 7291 22:59:34.200147  =================================== 

 7292 22:59:34.200727  EX_ROW_EN[0]    = 0x0

 7293 22:59:34.204218  EX_ROW_EN[1]    = 0x0

 7294 22:59:34.204692  LP4Y_EN      = 0x0

 7295 22:59:34.207156  WORK_FSP     = 0x1

 7296 22:59:34.207577  WL           = 0x5

 7297 22:59:34.210290  RL           = 0x5

 7298 22:59:34.210739  BL           = 0x2

 7299 22:59:34.214021  RPST         = 0x0

 7300 22:59:34.214443  RD_PRE       = 0x0

 7301 22:59:34.216939  WR_PRE       = 0x1

 7302 22:59:34.217455  WR_PST       = 0x1

 7303 22:59:34.220115  DBI_WR       = 0x0

 7304 22:59:34.220602  DBI_RD       = 0x0

 7305 22:59:34.223681  OTF          = 0x1

 7306 22:59:34.226874  =================================== 

 7307 22:59:34.229624  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 7308 22:59:34.233210  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 7309 22:59:34.240120  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7310 22:59:34.243285  =================================== 

 7311 22:59:34.243368  LPDDR4 DRAM CONFIGURATION

 7312 22:59:34.246220  =================================== 

 7313 22:59:34.249325  EX_ROW_EN[0]    = 0x10

 7314 22:59:34.253025  EX_ROW_EN[1]    = 0x0

 7315 22:59:34.253108  LP4Y_EN      = 0x0

 7316 22:59:34.256003  WORK_FSP     = 0x1

 7317 22:59:34.256085  WL           = 0x5

 7318 22:59:34.259722  RL           = 0x5

 7319 22:59:34.259804  BL           = 0x2

 7320 22:59:34.262782  RPST         = 0x0

 7321 22:59:34.262864  RD_PRE       = 0x0

 7322 22:59:34.265880  WR_PRE       = 0x1

 7323 22:59:34.265963  WR_PST       = 0x1

 7324 22:59:34.269497  DBI_WR       = 0x0

 7325 22:59:34.269579  DBI_RD       = 0x0

 7326 22:59:34.272454  OTF          = 0x1

 7327 22:59:34.275879  =================================== 

 7328 22:59:34.283028  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 7329 22:59:34.283124  ==

 7330 22:59:34.286036  Dram Type= 6, Freq= 0, CH_0, rank 0

 7331 22:59:34.289559  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7332 22:59:34.289642  ==

 7333 22:59:34.292304  [Duty_Offset_Calibration]

 7334 22:59:34.292389  	B0:1	B1:-1	CA:0

 7335 22:59:34.292482  

 7336 22:59:34.295925  [DutyScan_Calibration_Flow] k_type=0

 7337 22:59:34.307216  

 7338 22:59:34.307299  ==CLK 0==

 7339 22:59:34.310327  Final CLK duty delay cell = 0

 7340 22:59:34.314070  [0] MAX Duty = 5125%(X100), DQS PI = 20

 7341 22:59:34.317224  [0] MIN Duty = 4907%(X100), DQS PI = 6

 7342 22:59:34.317306  [0] AVG Duty = 5016%(X100)

 7343 22:59:34.320351  

 7344 22:59:34.323317  CH0 CLK Duty spec in!! Max-Min= 218%

 7345 22:59:34.327010  [DutyScan_Calibration_Flow] ====Done====

 7346 22:59:34.327092  

 7347 22:59:34.329884  [DutyScan_Calibration_Flow] k_type=1

 7348 22:59:34.346318  

 7349 22:59:34.346400  ==DQS 0 ==

 7350 22:59:34.349852  Final DQS duty delay cell = -4

 7351 22:59:34.352961  [-4] MAX Duty = 4969%(X100), DQS PI = 16

 7352 22:59:34.355894  [-4] MIN Duty = 4875%(X100), DQS PI = 48

 7353 22:59:34.358948  [-4] AVG Duty = 4922%(X100)

 7354 22:59:34.359030  

 7355 22:59:34.359094  ==DQS 1 ==

 7356 22:59:34.362677  Final DQS duty delay cell = 0

 7357 22:59:34.365910  [0] MAX Duty = 5187%(X100), DQS PI = 4

 7358 22:59:34.369454  [0] MIN Duty = 5031%(X100), DQS PI = 18

 7359 22:59:34.372358  [0] AVG Duty = 5109%(X100)

 7360 22:59:34.372450  

 7361 22:59:34.376268  CH0 DQS 0 Duty spec in!! Max-Min= 94%

 7362 22:59:34.376368  

 7363 22:59:34.379233  CH0 DQS 1 Duty spec in!! Max-Min= 156%

 7364 22:59:34.382430  [DutyScan_Calibration_Flow] ====Done====

 7365 22:59:34.382539  

 7366 22:59:34.385277  [DutyScan_Calibration_Flow] k_type=3

 7367 22:59:34.403587  

 7368 22:59:34.404036  ==DQM 0 ==

 7369 22:59:34.407185  Final DQM duty delay cell = 0

 7370 22:59:34.410689  [0] MAX Duty = 5124%(X100), DQS PI = 22

 7371 22:59:34.413900  [0] MIN Duty = 4907%(X100), DQS PI = 10

 7372 22:59:34.417023  [0] AVG Duty = 5015%(X100)

 7373 22:59:34.417629  

 7374 22:59:34.418112  ==DQM 1 ==

 7375 22:59:34.420770  Final DQM duty delay cell = 0

 7376 22:59:34.423627  [0] MAX Duty = 5031%(X100), DQS PI = 52

 7377 22:59:34.426935  [0] MIN Duty = 4813%(X100), DQS PI = 20

 7378 22:59:34.430110  [0] AVG Duty = 4922%(X100)

 7379 22:59:34.430524  

 7380 22:59:34.433754  CH0 DQM 0 Duty spec in!! Max-Min= 217%

 7381 22:59:34.434282  

 7382 22:59:34.436802  CH0 DQM 1 Duty spec in!! Max-Min= 218%

 7383 22:59:34.439828  [DutyScan_Calibration_Flow] ====Done====

 7384 22:59:34.440240  

 7385 22:59:34.443609  [DutyScan_Calibration_Flow] k_type=2

 7386 22:59:34.460146  

 7387 22:59:34.460597  ==DQ 0 ==

 7388 22:59:34.463909  Final DQ duty delay cell = -4

 7389 22:59:34.466977  [-4] MAX Duty = 5031%(X100), DQS PI = 24

 7390 22:59:34.470078  [-4] MIN Duty = 4876%(X100), DQS PI = 50

 7391 22:59:34.473805  [-4] AVG Duty = 4953%(X100)

 7392 22:59:34.474225  

 7393 22:59:34.474554  ==DQ 1 ==

 7394 22:59:34.477059  Final DQ duty delay cell = 0

 7395 22:59:34.480005  [0] MAX Duty = 5125%(X100), DQS PI = 48

 7396 22:59:34.483353  [0] MIN Duty = 4969%(X100), DQS PI = 38

 7397 22:59:34.486840  [0] AVG Duty = 5047%(X100)

 7398 22:59:34.487256  

 7399 22:59:34.490097  CH0 DQ 0 Duty spec in!! Max-Min= 155%

 7400 22:59:34.490517  

 7401 22:59:34.493604  CH0 DQ 1 Duty spec in!! Max-Min= 156%

 7402 22:59:34.496790  [DutyScan_Calibration_Flow] ====Done====

 7403 22:59:34.497281  ==

 7404 22:59:34.499669  Dram Type= 6, Freq= 0, CH_1, rank 0

 7405 22:59:34.503162  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7406 22:59:34.503580  ==

 7407 22:59:34.506723  [Duty_Offset_Calibration]

 7408 22:59:34.507137  	B0:-1	B1:1	CA:2

 7409 22:59:34.507463  

 7410 22:59:34.510030  [DutyScan_Calibration_Flow] k_type=0

 7411 22:59:34.521312  

 7412 22:59:34.521728  ==CLK 0==

 7413 22:59:34.524314  Final CLK duty delay cell = 0

 7414 22:59:34.527342  [0] MAX Duty = 5187%(X100), DQS PI = 22

 7415 22:59:34.530654  [0] MIN Duty = 4969%(X100), DQS PI = 62

 7416 22:59:34.534195  [0] AVG Duty = 5078%(X100)

 7417 22:59:34.534611  

 7418 22:59:34.537360  CH1 CLK Duty spec in!! Max-Min= 218%

 7419 22:59:34.540954  [DutyScan_Calibration_Flow] ====Done====

 7420 22:59:34.541495  

 7421 22:59:34.544033  [DutyScan_Calibration_Flow] k_type=1

 7422 22:59:34.560735  

 7423 22:59:34.561149  ==DQS 0 ==

 7424 22:59:34.564458  Final DQS duty delay cell = 0

 7425 22:59:34.567343  [0] MAX Duty = 5156%(X100), DQS PI = 20

 7426 22:59:34.570272  [0] MIN Duty = 4938%(X100), DQS PI = 8

 7427 22:59:34.573541  [0] AVG Duty = 5047%(X100)

 7428 22:59:34.573959  

 7429 22:59:34.574287  ==DQS 1 ==

 7430 22:59:34.577262  Final DQS duty delay cell = 0

 7431 22:59:34.580306  [0] MAX Duty = 5093%(X100), DQS PI = 26

 7432 22:59:34.583844  [0] MIN Duty = 4969%(X100), DQS PI = 56

 7433 22:59:34.586897  [0] AVG Duty = 5031%(X100)

 7434 22:59:34.587542  

 7435 22:59:34.589928  CH1 DQS 0 Duty spec in!! Max-Min= 218%

 7436 22:59:34.590341  

 7437 22:59:34.593724  CH1 DQS 1 Duty spec in!! Max-Min= 124%

 7438 22:59:34.596693  [DutyScan_Calibration_Flow] ====Done====

 7439 22:59:34.597146  

 7440 22:59:34.600302  [DutyScan_Calibration_Flow] k_type=3

 7441 22:59:34.616961  

 7442 22:59:34.617403  ==DQM 0 ==

 7443 22:59:34.619904  Final DQM duty delay cell = -4

 7444 22:59:34.623183  [-4] MAX Duty = 5062%(X100), DQS PI = 34

 7445 22:59:34.626707  [-4] MIN Duty = 4782%(X100), DQS PI = 10

 7446 22:59:34.629849  [-4] AVG Duty = 4922%(X100)

 7447 22:59:34.630275  

 7448 22:59:34.630610  ==DQM 1 ==

 7449 22:59:34.632981  Final DQM duty delay cell = 0

 7450 22:59:34.636591  [0] MAX Duty = 5125%(X100), DQS PI = 0

 7451 22:59:34.639559  [0] MIN Duty = 4969%(X100), DQS PI = 28

 7452 22:59:34.643140  [0] AVG Duty = 5047%(X100)

 7453 22:59:34.643581  

 7454 22:59:34.646265  CH1 DQM 0 Duty spec in!! Max-Min= 280%

 7455 22:59:34.646688  

 7456 22:59:34.649987  CH1 DQM 1 Duty spec in!! Max-Min= 156%

 7457 22:59:34.653231  [DutyScan_Calibration_Flow] ====Done====

 7458 22:59:34.653652  

 7459 22:59:34.656231  [DutyScan_Calibration_Flow] k_type=2

 7460 22:59:34.673952  

 7461 22:59:34.674372  ==DQ 0 ==

 7462 22:59:34.676967  Final DQ duty delay cell = 0

 7463 22:59:34.680760  [0] MAX Duty = 5156%(X100), DQS PI = 30

 7464 22:59:34.683551  [0] MIN Duty = 4906%(X100), DQS PI = 8

 7465 22:59:34.684011  [0] AVG Duty = 5031%(X100)

 7466 22:59:34.687202  

 7467 22:59:34.687646  ==DQ 1 ==

 7468 22:59:34.690194  Final DQ duty delay cell = 0

 7469 22:59:34.693872  [0] MAX Duty = 5156%(X100), DQS PI = 8

 7470 22:59:34.697203  [0] MIN Duty = 4969%(X100), DQS PI = 56

 7471 22:59:34.697632  [0] AVG Duty = 5062%(X100)

 7472 22:59:34.698040  

 7473 22:59:34.703808  CH1 DQ 0 Duty spec in!! Max-Min= 250%

 7474 22:59:34.704360  

 7475 22:59:34.706928  CH1 DQ 1 Duty spec in!! Max-Min= 187%

 7476 22:59:34.710448  [DutyScan_Calibration_Flow] ====Done====

 7477 22:59:34.713521  nWR fixed to 30

 7478 22:59:34.713953  [ModeRegInit_LP4] CH0 RK0

 7479 22:59:34.716764  [ModeRegInit_LP4] CH0 RK1

 7480 22:59:34.720119  [ModeRegInit_LP4] CH1 RK0

 7481 22:59:34.723456  [ModeRegInit_LP4] CH1 RK1

 7482 22:59:34.723883  match AC timing 5

 7483 22:59:34.730249  dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1

 7484 22:59:34.733487  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 7485 22:59:34.736745  [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14

 7486 22:59:34.743534  [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29

 7487 22:59:34.746616  [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)

 7488 22:59:34.747042  [MiockJmeterHQA]

 7489 22:59:34.747379  

 7490 22:59:34.749545  [DramcMiockJmeter] u1RxGatingPI = 0

 7491 22:59:34.753207  0 : 4252, 4027

 7492 22:59:34.753641  4 : 4255, 4029

 7493 22:59:34.756391  8 : 4365, 4140

 7494 22:59:34.756895  12 : 4252, 4027

 7495 22:59:34.759743  16 : 4363, 4138

 7496 22:59:34.760269  20 : 4253, 4026

 7497 22:59:34.760689  24 : 4253, 4026

 7498 22:59:34.762640  28 : 4252, 4027

 7499 22:59:34.763071  32 : 4363, 4137

 7500 22:59:34.766357  36 : 4363, 4138

 7501 22:59:34.766794  40 : 4252, 4026

 7502 22:59:34.769470  44 : 4253, 4026

 7503 22:59:34.769974  48 : 4254, 4029

 7504 22:59:34.772940  52 : 4252, 4026

 7505 22:59:34.773375  56 : 4255, 4029

 7506 22:59:34.773714  60 : 4252, 4026

 7507 22:59:34.776103  64 : 4253, 4027

 7508 22:59:34.776558  68 : 4252, 4026

 7509 22:59:34.779015  72 : 4252, 4027

 7510 22:59:34.779448  76 : 4255, 4030

 7511 22:59:34.782697  80 : 4254, 4029

 7512 22:59:34.783129  84 : 4363, 4140

 7513 22:59:34.786048  88 : 4360, 4138

 7514 22:59:34.786508  92 : 4362, 505

 7515 22:59:34.786862  96 : 4250, 0

 7516 22:59:34.789597  100 : 4363, 0

 7517 22:59:34.790030  104 : 4252, 0

 7518 22:59:34.790375  108 : 4250, 0

 7519 22:59:34.792449  112 : 4250, 0

 7520 22:59:34.792923  116 : 4250, 0

 7521 22:59:34.796019  120 : 4250, 0

 7522 22:59:34.796686  124 : 4249, 0

 7523 22:59:34.797114  128 : 4250, 0

 7524 22:59:34.799084  132 : 4250, 0

 7525 22:59:34.799706  136 : 4250, 0

 7526 22:59:34.802264  140 : 4360, 0

 7527 22:59:34.802699  144 : 4366, 0

 7528 22:59:34.803043  148 : 4360, 0

 7529 22:59:34.806011  152 : 4250, 0

 7530 22:59:34.806445  156 : 4361, 0

 7531 22:59:34.809030  160 : 4250, 0

 7532 22:59:34.809464  164 : 4250, 0

 7533 22:59:34.809805  168 : 4250, 0

 7534 22:59:34.812055  172 : 4249, 0

 7535 22:59:34.812492  176 : 4250, 0

 7536 22:59:34.815723  180 : 4250, 0

 7537 22:59:34.816363  184 : 4250, 0

 7538 22:59:34.816986  188 : 4250, 0

 7539 22:59:34.818705  192 : 4360, 0

 7540 22:59:34.819334  196 : 4250, 0

 7541 22:59:34.822369  200 : 4361, 0

 7542 22:59:34.822975  204 : 4250, 0

 7543 22:59:34.823555  208 : 4250, 0

 7544 22:59:34.825845  212 : 4363, 0

 7545 22:59:34.826299  216 : 4250, 0

 7546 22:59:34.826774  220 : 4250, 0

 7547 22:59:34.828971  224 : 4255, 300

 7548 22:59:34.829405  228 : 4252, 3585

 7549 22:59:34.832275  232 : 4250, 4027

 7550 22:59:34.832752  236 : 4361, 4137

 7551 22:59:34.835308  240 : 4250, 4027

 7552 22:59:34.835740  244 : 4250, 4026

 7553 22:59:34.838704  248 : 4250, 4026

 7554 22:59:34.839137  252 : 4363, 4140

 7555 22:59:34.841954  256 : 4250, 4027

 7556 22:59:34.842400  260 : 4250, 4026

 7557 22:59:34.845441  264 : 4360, 4137

 7558 22:59:34.845876  268 : 4250, 4027

 7559 22:59:34.848478  272 : 4250, 4027

 7560 22:59:34.848949  276 : 4361, 4138

 7561 22:59:34.849356  280 : 4361, 4137

 7562 22:59:34.852189  284 : 4250, 4027

 7563 22:59:34.852659  288 : 4249, 4027

 7564 22:59:34.855288  292 : 4250, 4027

 7565 22:59:34.855720  296 : 4250, 4026

 7566 22:59:34.858305  300 : 4250, 4027

 7567 22:59:34.858804  304 : 4363, 4140

 7568 22:59:34.861747  308 : 4250, 4027

 7569 22:59:34.861831  312 : 4250, 4026

 7570 22:59:34.864793  316 : 4363, 4140

 7571 22:59:34.864877  320 : 4250, 4027

 7572 22:59:34.867810  324 : 4250, 4027

 7573 22:59:34.867894  328 : 4361, 4137

 7574 22:59:34.871442  332 : 4361, 4137

 7575 22:59:34.871526  336 : 4250, 3514

 7576 22:59:34.871592  340 : 4254, 1513

 7577 22:59:34.874560  

 7578 22:59:34.874643  	MIOCK jitter meter	ch=0

 7579 22:59:34.874709  

 7580 22:59:34.878002  1T = (340-92) = 248 dly cells

 7581 22:59:34.884890  Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps

 7582 22:59:34.885011  ==

 7583 22:59:34.888054  Dram Type= 6, Freq= 0, CH_0, rank 0

 7584 22:59:34.891097  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7585 22:59:34.891181  ==

 7586 22:59:34.897710  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 7587 22:59:34.901356  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1

 7588 22:59:34.904505  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1

 7589 22:59:34.911265  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 7590 22:59:34.920415  [CA 0] Center 43 (13~74) winsize 62

 7591 22:59:34.924035  [CA 1] Center 43 (13~74) winsize 62

 7592 22:59:34.927367  [CA 2] Center 39 (10~69) winsize 60

 7593 22:59:34.930937  [CA 3] Center 39 (9~69) winsize 61

 7594 22:59:34.933837  [CA 4] Center 37 (8~66) winsize 59

 7595 22:59:34.937233  [CA 5] Center 36 (7~66) winsize 60

 7596 22:59:34.937315  

 7597 22:59:34.940081  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 7598 22:59:34.940164  

 7599 22:59:34.947075  [CATrainingPosCal] consider 1 rank data

 7600 22:59:34.947157  u2DelayCellTimex100 = 262/100 ps

 7601 22:59:34.953611  CA0 delay=43 (13~74),Diff = 7 PI (26 cell)

 7602 22:59:34.956959  CA1 delay=43 (13~74),Diff = 7 PI (26 cell)

 7603 22:59:34.960429  CA2 delay=39 (10~69),Diff = 3 PI (11 cell)

 7604 22:59:34.963422  CA3 delay=39 (9~69),Diff = 3 PI (11 cell)

 7605 22:59:34.966567  CA4 delay=37 (8~66),Diff = 1 PI (3 cell)

 7606 22:59:34.970237  CA5 delay=36 (7~66),Diff = 0 PI (0 cell)

 7607 22:59:34.970319  

 7608 22:59:34.973356  CA PerBit enable=1, Macro0, CA PI delay=36

 7609 22:59:34.973439  

 7610 22:59:34.977195  [CBTSetCACLKResult] CA Dly = 36

 7611 22:59:34.980135  CS Dly: 11 (0~42)

 7612 22:59:34.983216  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0

 7613 22:59:34.986322  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0

 7614 22:59:34.986404  ==

 7615 22:59:34.989878  Dram Type= 6, Freq= 0, CH_0, rank 1

 7616 22:59:34.996710  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7617 22:59:34.996799  ==

 7618 22:59:34.999692  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 7619 22:59:35.006383  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1

 7620 22:59:35.009515  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1

 7621 22:59:35.016334  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 7622 22:59:35.024299  [CA 0] Center 42 (12~73) winsize 62

 7623 22:59:35.027958  [CA 1] Center 43 (13~73) winsize 61

 7624 22:59:35.031072  [CA 2] Center 37 (8~67) winsize 60

 7625 22:59:35.034293  [CA 3] Center 37 (7~67) winsize 61

 7626 22:59:35.037313  [CA 4] Center 35 (6~65) winsize 60

 7627 22:59:35.040932  [CA 5] Center 35 (5~65) winsize 61

 7628 22:59:35.041016  

 7629 22:59:35.043811  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 7630 22:59:35.043885  

 7631 22:59:35.047393  [CATrainingPosCal] consider 2 rank data

 7632 22:59:35.050571  u2DelayCellTimex100 = 262/100 ps

 7633 22:59:35.057474  CA0 delay=43 (13~73),Diff = 7 PI (26 cell)

 7634 22:59:35.060469  CA1 delay=43 (13~73),Diff = 7 PI (26 cell)

 7635 22:59:35.064040  CA2 delay=38 (10~67),Diff = 2 PI (7 cell)

 7636 22:59:35.067424  CA3 delay=38 (9~67),Diff = 2 PI (7 cell)

 7637 22:59:35.070508  CA4 delay=36 (8~65),Diff = 0 PI (0 cell)

 7638 22:59:35.074162  CA5 delay=36 (7~65),Diff = 0 PI (0 cell)

 7639 22:59:35.074245  

 7640 22:59:35.077202  CA PerBit enable=1, Macro0, CA PI delay=36

 7641 22:59:35.077285  

 7642 22:59:35.080781  [CBTSetCACLKResult] CA Dly = 36

 7643 22:59:35.084001  CS Dly: 12 (0~44)

 7644 22:59:35.087004  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0

 7645 22:59:35.090727  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0

 7646 22:59:35.090809  

 7647 22:59:35.093657  ----->DramcWriteLeveling(PI) begin...

 7648 22:59:35.093742  ==

 7649 22:59:35.096813  Dram Type= 6, Freq= 0, CH_0, rank 0

 7650 22:59:35.103459  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7651 22:59:35.103543  ==

 7652 22:59:35.107052  Write leveling (Byte 0): 35 => 35

 7653 22:59:35.110647  Write leveling (Byte 1): 28 => 28

 7654 22:59:35.110731  DramcWriteLeveling(PI) end<-----

 7655 22:59:35.110796  

 7656 22:59:35.113692  ==

 7657 22:59:35.116732  Dram Type= 6, Freq= 0, CH_0, rank 0

 7658 22:59:35.119823  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7659 22:59:35.119923  ==

 7660 22:59:35.123590  [Gating] SW mode calibration

 7661 22:59:35.130201  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 7662 22:59:35.133283  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 7663 22:59:35.140044   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7664 22:59:35.143127   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7665 22:59:35.146261   1  4  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7666 22:59:35.152927   1  4 12 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (1 1)

 7667 22:59:35.156495   1  4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)

 7668 22:59:35.159865   1  4 20 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)

 7669 22:59:35.166824   1  4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)

 7670 22:59:35.169590   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7671 22:59:35.172704   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7672 22:59:35.179577   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7673 22:59:35.183016   1  5  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 7674 22:59:35.186429   1  5 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 0)

 7675 22:59:35.192650   1  5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)

 7676 22:59:35.196227   1  5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)

 7677 22:59:35.199398   1  5 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)

 7678 22:59:35.206385   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7679 22:59:35.210057   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7680 22:59:35.212856   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7681 22:59:35.220043   1  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7682 22:59:35.222868   1  6 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)

 7683 22:59:35.226075   1  6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)

 7684 22:59:35.233095   1  6 20 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)

 7685 22:59:35.235627   1  6 24 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)

 7686 22:59:35.239190   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7687 22:59:35.245936   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7688 22:59:35.249392   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7689 22:59:35.252242   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7690 22:59:35.259008   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 7691 22:59:35.262336   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)

 7692 22:59:35.265827   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 7693 22:59:35.272197   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7694 22:59:35.275361   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7695 22:59:35.278684   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7696 22:59:35.285106   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7697 22:59:35.288792   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7698 22:59:35.292078   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7699 22:59:35.298572   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7700 22:59:35.302035   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7701 22:59:35.305452   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7702 22:59:35.311768   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7703 22:59:35.315086   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7704 22:59:35.318036   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7705 22:59:35.324913   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 7706 22:59:35.328478   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 7707 22:59:35.331686   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 7708 22:59:35.334799  Total UI for P1: 0, mck2ui 16

 7709 22:59:35.338341  best dqsien dly found for B0: ( 1,  9, 10)

 7710 22:59:35.345140   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 7711 22:59:35.348597   1  9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 7712 22:59:35.351474   1  9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7713 22:59:35.355516  Total UI for P1: 0, mck2ui 16

 7714 22:59:35.358211  best dqsien dly found for B1: ( 1,  9, 20)

 7715 22:59:35.361198  best DQS0 dly(MCK, UI, PI) = (1, 9, 10)

 7716 22:59:35.364802  best DQS1 dly(MCK, UI, PI) = (1, 9, 20)

 7717 22:59:35.365231  

 7718 22:59:35.371334  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)

 7719 22:59:35.374710  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)

 7720 22:59:35.377672  [Gating] SW calibration Done

 7721 22:59:35.378163  ==

 7722 22:59:35.381311  Dram Type= 6, Freq= 0, CH_0, rank 0

 7723 22:59:35.384019  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7724 22:59:35.384664  ==

 7725 22:59:35.387561  RX Vref Scan: 0

 7726 22:59:35.387982  

 7727 22:59:35.388356  RX Vref 0 -> 0, step: 1

 7728 22:59:35.388704  

 7729 22:59:35.391038  RX Delay 0 -> 252, step: 8

 7730 22:59:35.394552  iDelay=200, Bit 0, Center 135 (88 ~ 183) 96

 7731 22:59:35.397783  iDelay=200, Bit 1, Center 139 (88 ~ 191) 104

 7732 22:59:35.404190  iDelay=200, Bit 2, Center 131 (80 ~ 183) 104

 7733 22:59:35.407308  iDelay=200, Bit 3, Center 131 (80 ~ 183) 104

 7734 22:59:35.410441  iDelay=200, Bit 4, Center 135 (80 ~ 191) 112

 7735 22:59:35.414172  iDelay=200, Bit 5, Center 119 (64 ~ 175) 112

 7736 22:59:35.417137  iDelay=200, Bit 6, Center 143 (88 ~ 199) 112

 7737 22:59:35.423633  iDelay=200, Bit 7, Center 147 (96 ~ 199) 104

 7738 22:59:35.427309  iDelay=200, Bit 8, Center 115 (56 ~ 175) 120

 7739 22:59:35.430412  iDelay=200, Bit 9, Center 115 (64 ~ 167) 104

 7740 22:59:35.433541  iDelay=200, Bit 10, Center 127 (72 ~ 183) 112

 7741 22:59:35.437318  iDelay=200, Bit 11, Center 119 (64 ~ 175) 112

 7742 22:59:35.443461  iDelay=200, Bit 12, Center 131 (80 ~ 183) 104

 7743 22:59:35.446726  iDelay=200, Bit 13, Center 131 (80 ~ 183) 104

 7744 22:59:35.450453  iDelay=200, Bit 14, Center 139 (88 ~ 191) 104

 7745 22:59:35.453623  iDelay=200, Bit 15, Center 131 (72 ~ 191) 120

 7746 22:59:35.456565  ==

 7747 22:59:35.456989  Dram Type= 6, Freq= 0, CH_0, rank 0

 7748 22:59:35.463435  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7749 22:59:35.463860  ==

 7750 22:59:35.464195  DQS Delay:

 7751 22:59:35.466921  DQS0 = 0, DQS1 = 0

 7752 22:59:35.467346  DQM Delay:

 7753 22:59:35.469791  DQM0 = 135, DQM1 = 126

 7754 22:59:35.470314  DQ Delay:

 7755 22:59:35.473251  DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131

 7756 22:59:35.476228  DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =147

 7757 22:59:35.479764  DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119

 7758 22:59:35.483203  DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =131

 7759 22:59:35.483625  

 7760 22:59:35.483953  

 7761 22:59:35.484260  ==

 7762 22:59:35.486801  Dram Type= 6, Freq= 0, CH_0, rank 0

 7763 22:59:35.493219  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7764 22:59:35.493727  ==

 7765 22:59:35.494122  

 7766 22:59:35.494462  

 7767 22:59:35.494922  	TX Vref Scan disable

 7768 22:59:35.496633   == TX Byte 0 ==

 7769 22:59:35.500049  Update DQ  dly =990 (3 ,6, 30)  DQ  OEN =(3 ,3)

 7770 22:59:35.506929  Update DQM dly =990 (3 ,6, 30)  DQM OEN =(3 ,3)

 7771 22:59:35.507361   == TX Byte 1 ==

 7772 22:59:35.509801  Update DQ  dly =983 (3 ,6, 23)  DQ  OEN =(3 ,3)

 7773 22:59:35.516594  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 7774 22:59:35.517166  ==

 7775 22:59:35.519448  Dram Type= 6, Freq= 0, CH_0, rank 0

 7776 22:59:35.523182  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7777 22:59:35.523291  ==

 7778 22:59:35.535629  

 7779 22:59:35.539266  TX Vref early break, caculate TX vref

 7780 22:59:35.542396  TX Vref=16, minBit 1, minWin=22, winSum=370

 7781 22:59:35.545916  TX Vref=18, minBit 1, minWin=23, winSum=382

 7782 22:59:35.548908  TX Vref=20, minBit 4, minWin=23, winSum=394

 7783 22:59:35.552473  TX Vref=22, minBit 3, minWin=24, winSum=400

 7784 22:59:35.555578  TX Vref=24, minBit 0, minWin=25, winSum=411

 7785 22:59:35.562346  TX Vref=26, minBit 3, minWin=25, winSum=421

 7786 22:59:35.565463  TX Vref=28, minBit 0, minWin=25, winSum=421

 7787 22:59:35.569031  TX Vref=30, minBit 0, minWin=24, winSum=411

 7788 22:59:35.572181  TX Vref=32, minBit 0, minWin=24, winSum=400

 7789 22:59:35.575558  TX Vref=34, minBit 4, minWin=23, winSum=391

 7790 22:59:35.581953  [TxChooseVref] Worse bit 3, Min win 25, Win sum 421, Final Vref 26

 7791 22:59:35.582039  

 7792 22:59:35.585107  Final TX Range 0 Vref 26

 7793 22:59:35.585191  

 7794 22:59:35.585274  ==

 7795 22:59:35.588438  Dram Type= 6, Freq= 0, CH_0, rank 0

 7796 22:59:35.591860  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7797 22:59:35.591952  ==

 7798 22:59:35.592022  

 7799 22:59:35.592087  

 7800 22:59:35.595344  	TX Vref Scan disable

 7801 22:59:35.601669  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps

 7802 22:59:35.601773   == TX Byte 0 ==

 7803 22:59:35.604951  u2DelayCellOfst[0]=14 cells (4 PI)

 7804 22:59:35.608633  u2DelayCellOfst[1]=18 cells (5 PI)

 7805 22:59:35.611819  u2DelayCellOfst[2]=14 cells (4 PI)

 7806 22:59:35.615106  u2DelayCellOfst[3]=14 cells (4 PI)

 7807 22:59:35.618267  u2DelayCellOfst[4]=11 cells (3 PI)

 7808 22:59:35.621383  u2DelayCellOfst[5]=0 cells (0 PI)

 7809 22:59:35.625080  u2DelayCellOfst[6]=22 cells (6 PI)

 7810 22:59:35.628001  u2DelayCellOfst[7]=22 cells (6 PI)

 7811 22:59:35.631696  Update DQ  dly =987 (3 ,6, 27)  DQ  OEN =(3 ,3)

 7812 22:59:35.634746  Update DQM dly =990 (3 ,6, 30)  DQM OEN =(3 ,3)

 7813 22:59:35.637904   == TX Byte 1 ==

 7814 22:59:35.641561  u2DelayCellOfst[8]=0 cells (0 PI)

 7815 22:59:35.644793  u2DelayCellOfst[9]=3 cells (1 PI)

 7816 22:59:35.648467  u2DelayCellOfst[10]=7 cells (2 PI)

 7817 22:59:35.649020  u2DelayCellOfst[11]=0 cells (0 PI)

 7818 22:59:35.651680  u2DelayCellOfst[12]=11 cells (3 PI)

 7819 22:59:35.654522  u2DelayCellOfst[13]=11 cells (3 PI)

 7820 22:59:35.658222  u2DelayCellOfst[14]=14 cells (4 PI)

 7821 22:59:35.661400  u2DelayCellOfst[15]=11 cells (3 PI)

 7822 22:59:35.668016  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 7823 22:59:35.671329  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 7824 22:59:35.671767  DramC Write-DBI on

 7825 22:59:35.675004  ==

 7826 22:59:35.675427  Dram Type= 6, Freq= 0, CH_0, rank 0

 7827 22:59:35.681480  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7828 22:59:35.681915  ==

 7829 22:59:35.682291  

 7830 22:59:35.682734  

 7831 22:59:35.684365  	TX Vref Scan disable

 7832 22:59:35.684958   == TX Byte 0 ==

 7833 22:59:35.691257  Update DQM dly =735 (2 ,6, 31)  DQM OEN =(3 ,3)

 7834 22:59:35.691733   == TX Byte 1 ==

 7835 22:59:35.694420  Update DQM dly =724 (2 ,6, 20)  DQM OEN =(3 ,3)

 7836 22:59:35.698072  DramC Write-DBI off

 7837 22:59:35.698567  

 7838 22:59:35.698909  [DATLAT]

 7839 22:59:35.700951  Freq=1600, CH0 RK0

 7840 22:59:35.701451  

 7841 22:59:35.701812  DATLAT Default: 0xf

 7842 22:59:35.704340  0, 0xFFFF, sum = 0

 7843 22:59:35.704837  1, 0xFFFF, sum = 0

 7844 22:59:35.707659  2, 0xFFFF, sum = 0

 7845 22:59:35.708115  3, 0xFFFF, sum = 0

 7846 22:59:35.711050  4, 0xFFFF, sum = 0

 7847 22:59:35.711485  5, 0xFFFF, sum = 0

 7848 22:59:35.714034  6, 0xFFFF, sum = 0

 7849 22:59:35.714467  7, 0xFFFF, sum = 0

 7850 22:59:35.717657  8, 0xFFFF, sum = 0

 7851 22:59:35.720787  9, 0xFFFF, sum = 0

 7852 22:59:35.721221  10, 0xFFFF, sum = 0

 7853 22:59:35.724018  11, 0xFFFF, sum = 0

 7854 22:59:35.724448  12, 0xFFFF, sum = 0

 7855 22:59:35.727671  13, 0xFFFF, sum = 0

 7856 22:59:35.728203  14, 0x0, sum = 1

 7857 22:59:35.730927  15, 0x0, sum = 2

 7858 22:59:35.731359  16, 0x0, sum = 3

 7859 22:59:35.734553  17, 0x0, sum = 4

 7860 22:59:35.734986  best_step = 15

 7861 22:59:35.735321  

 7862 22:59:35.735682  ==

 7863 22:59:35.737550  Dram Type= 6, Freq= 0, CH_0, rank 0

 7864 22:59:35.740611  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7865 22:59:35.744604  ==

 7866 22:59:35.745120  RX Vref Scan: 1

 7867 22:59:35.745461  

 7868 22:59:35.747263  Set Vref Range= 24 -> 127

 7869 22:59:35.747689  

 7870 22:59:35.750387  RX Vref 24 -> 127, step: 1

 7871 22:59:35.750831  

 7872 22:59:35.751171  RX Delay 11 -> 252, step: 4

 7873 22:59:35.751491  

 7874 22:59:35.753560  Set Vref, RX VrefLevel [Byte0]: 24

 7875 22:59:35.757245                           [Byte1]: 24

 7876 22:59:35.760718  

 7877 22:59:35.761159  Set Vref, RX VrefLevel [Byte0]: 25

 7878 22:59:35.764299                           [Byte1]: 25

 7879 22:59:35.768634  

 7880 22:59:35.769281  Set Vref, RX VrefLevel [Byte0]: 26

 7881 22:59:35.771563                           [Byte1]: 26

 7882 22:59:35.775955  

 7883 22:59:35.776455  Set Vref, RX VrefLevel [Byte0]: 27

 7884 22:59:35.779179                           [Byte1]: 27

 7885 22:59:35.783963  

 7886 22:59:35.784454  Set Vref, RX VrefLevel [Byte0]: 28

 7887 22:59:35.787047                           [Byte1]: 28

 7888 22:59:35.791119  

 7889 22:59:35.791539  Set Vref, RX VrefLevel [Byte0]: 29

 7890 22:59:35.794435                           [Byte1]: 29

 7891 22:59:35.798942  

 7892 22:59:35.799399  Set Vref, RX VrefLevel [Byte0]: 30

 7893 22:59:35.802362                           [Byte1]: 30

 7894 22:59:35.806532  

 7895 22:59:35.806951  Set Vref, RX VrefLevel [Byte0]: 31

 7896 22:59:35.809637                           [Byte1]: 31

 7897 22:59:35.814251  

 7898 22:59:35.814851  Set Vref, RX VrefLevel [Byte0]: 32

 7899 22:59:35.817651                           [Byte1]: 32

 7900 22:59:35.821619  

 7901 22:59:35.822181  Set Vref, RX VrefLevel [Byte0]: 33

 7902 22:59:35.825175                           [Byte1]: 33

 7903 22:59:35.829578  

 7904 22:59:35.829999  Set Vref, RX VrefLevel [Byte0]: 34

 7905 22:59:35.832503                           [Byte1]: 34

 7906 22:59:35.836829  

 7907 22:59:35.837249  Set Vref, RX VrefLevel [Byte0]: 35

 7908 22:59:35.840366                           [Byte1]: 35

 7909 22:59:35.844796  

 7910 22:59:35.845218  Set Vref, RX VrefLevel [Byte0]: 36

 7911 22:59:35.847691                           [Byte1]: 36

 7912 22:59:35.852118  

 7913 22:59:35.852591  Set Vref, RX VrefLevel [Byte0]: 37

 7914 22:59:35.855325                           [Byte1]: 37

 7915 22:59:35.859657  

 7916 22:59:35.860207  Set Vref, RX VrefLevel [Byte0]: 38

 7917 22:59:35.863169                           [Byte1]: 38

 7918 22:59:35.867236  

 7919 22:59:35.867757  Set Vref, RX VrefLevel [Byte0]: 39

 7920 22:59:35.870428                           [Byte1]: 39

 7921 22:59:35.874795  

 7922 22:59:35.875217  Set Vref, RX VrefLevel [Byte0]: 40

 7923 22:59:35.878091                           [Byte1]: 40

 7924 22:59:35.882835  

 7925 22:59:35.883451  Set Vref, RX VrefLevel [Byte0]: 41

 7926 22:59:35.885939                           [Byte1]: 41

 7927 22:59:35.890414  

 7928 22:59:35.890835  Set Vref, RX VrefLevel [Byte0]: 42

 7929 22:59:35.894084                           [Byte1]: 42

 7930 22:59:35.897933  

 7931 22:59:35.898576  Set Vref, RX VrefLevel [Byte0]: 43

 7932 22:59:35.900892                           [Byte1]: 43

 7933 22:59:35.905700  

 7934 22:59:35.906378  Set Vref, RX VrefLevel [Byte0]: 44

 7935 22:59:35.908905                           [Byte1]: 44

 7936 22:59:35.913147  

 7937 22:59:35.913623  Set Vref, RX VrefLevel [Byte0]: 45

 7938 22:59:35.916625                           [Byte1]: 45

 7939 22:59:35.920613  

 7940 22:59:35.921290  Set Vref, RX VrefLevel [Byte0]: 46

 7941 22:59:35.924160                           [Byte1]: 46

 7942 22:59:35.928273  

 7943 22:59:35.928852  Set Vref, RX VrefLevel [Byte0]: 47

 7944 22:59:35.931786                           [Byte1]: 47

 7945 22:59:35.936022  

 7946 22:59:35.936601  Set Vref, RX VrefLevel [Byte0]: 48

 7947 22:59:35.939125                           [Byte1]: 48

 7948 22:59:35.943353  

 7949 22:59:35.943929  Set Vref, RX VrefLevel [Byte0]: 49

 7950 22:59:35.946990                           [Byte1]: 49

 7951 22:59:35.951348  

 7952 22:59:35.951892  Set Vref, RX VrefLevel [Byte0]: 50

 7953 22:59:35.954451                           [Byte1]: 50

 7954 22:59:35.958813  

 7955 22:59:35.959361  Set Vref, RX VrefLevel [Byte0]: 51

 7956 22:59:35.962057                           [Byte1]: 51

 7957 22:59:35.966255  

 7958 22:59:35.966882  Set Vref, RX VrefLevel [Byte0]: 52

 7959 22:59:35.969636                           [Byte1]: 52

 7960 22:59:35.973872  

 7961 22:59:35.974456  Set Vref, RX VrefLevel [Byte0]: 53

 7962 22:59:35.977546                           [Byte1]: 53

 7963 22:59:35.981325  

 7964 22:59:35.981933  Set Vref, RX VrefLevel [Byte0]: 54

 7965 22:59:35.984963                           [Byte1]: 54

 7966 22:59:35.989176  

 7967 22:59:35.989762  Set Vref, RX VrefLevel [Byte0]: 55

 7968 22:59:35.992800                           [Byte1]: 55

 7969 22:59:35.997230  

 7970 22:59:35.997815  Set Vref, RX VrefLevel [Byte0]: 56

 7971 22:59:36.000229                           [Byte1]: 56

 7972 22:59:36.004748  

 7973 22:59:36.005166  Set Vref, RX VrefLevel [Byte0]: 57

 7974 22:59:36.007607                           [Byte1]: 57

 7975 22:59:36.012169  

 7976 22:59:36.012625  Set Vref, RX VrefLevel [Byte0]: 58

 7977 22:59:36.015283                           [Byte1]: 58

 7978 22:59:36.020036  

 7979 22:59:36.020454  Set Vref, RX VrefLevel [Byte0]: 59

 7980 22:59:36.023373                           [Byte1]: 59

 7981 22:59:36.027542  

 7982 22:59:36.028031  Set Vref, RX VrefLevel [Byte0]: 60

 7983 22:59:36.030723                           [Byte1]: 60

 7984 22:59:36.034749  

 7985 22:59:36.035167  Set Vref, RX VrefLevel [Byte0]: 61

 7986 22:59:36.038330                           [Byte1]: 61

 7987 22:59:36.042719  

 7988 22:59:36.043150  Set Vref, RX VrefLevel [Byte0]: 62

 7989 22:59:36.045540                           [Byte1]: 62

 7990 22:59:36.050558  

 7991 22:59:36.050983  Set Vref, RX VrefLevel [Byte0]: 63

 7992 22:59:36.053230                           [Byte1]: 63

 7993 22:59:36.058178  

 7994 22:59:36.058614  Set Vref, RX VrefLevel [Byte0]: 64

 7995 22:59:36.061283                           [Byte1]: 64

 7996 22:59:36.065299  

 7997 22:59:36.065826  Set Vref, RX VrefLevel [Byte0]: 65

 7998 22:59:36.068978                           [Byte1]: 65

 7999 22:59:36.073216  

 8000 22:59:36.073851  Set Vref, RX VrefLevel [Byte0]: 66

 8001 22:59:36.077079                           [Byte1]: 66

 8002 22:59:36.081204  

 8003 22:59:36.081726  Set Vref, RX VrefLevel [Byte0]: 67

 8004 22:59:36.083811                           [Byte1]: 67

 8005 22:59:36.088386  

 8006 22:59:36.088965  Set Vref, RX VrefLevel [Byte0]: 68

 8007 22:59:36.091643                           [Byte1]: 68

 8008 22:59:36.095958  

 8009 22:59:36.096468  Set Vref, RX VrefLevel [Byte0]: 69

 8010 22:59:36.099092                           [Byte1]: 69

 8011 22:59:36.103679  

 8012 22:59:36.106887  Set Vref, RX VrefLevel [Byte0]: 70

 8013 22:59:36.109967                           [Byte1]: 70

 8014 22:59:36.110543  

 8015 22:59:36.113466  Set Vref, RX VrefLevel [Byte0]: 71

 8016 22:59:36.116573                           [Byte1]: 71

 8017 22:59:36.117208  

 8018 22:59:36.120141  Set Vref, RX VrefLevel [Byte0]: 72

 8019 22:59:36.123031                           [Byte1]: 72

 8020 22:59:36.126394  

 8021 22:59:36.126870  Set Vref, RX VrefLevel [Byte0]: 73

 8022 22:59:36.129588                           [Byte1]: 73

 8023 22:59:36.133692  

 8024 22:59:36.134257  Set Vref, RX VrefLevel [Byte0]: 74

 8025 22:59:36.137142                           [Byte1]: 74

 8026 22:59:36.141967  

 8027 22:59:36.142394  Set Vref, RX VrefLevel [Byte0]: 75

 8028 22:59:36.144884                           [Byte1]: 75

 8029 22:59:36.149299  

 8030 22:59:36.149727  Set Vref, RX VrefLevel [Byte0]: 76

 8031 22:59:36.152508                           [Byte1]: 76

 8032 22:59:36.157230  

 8033 22:59:36.157752  Set Vref, RX VrefLevel [Byte0]: 77

 8034 22:59:36.160319                           [Byte1]: 77

 8035 22:59:36.165030  

 8036 22:59:36.165569  Set Vref, RX VrefLevel [Byte0]: 78

 8037 22:59:36.167705                           [Byte1]: 78

 8038 22:59:36.172052  

 8039 22:59:36.172598  Final RX Vref Byte 0 = 67 to rank0

 8040 22:59:36.175081  Final RX Vref Byte 1 = 60 to rank0

 8041 22:59:36.178804  Final RX Vref Byte 0 = 67 to rank1

 8042 22:59:36.181740  Final RX Vref Byte 1 = 60 to rank1==

 8043 22:59:36.185616  Dram Type= 6, Freq= 0, CH_0, rank 0

 8044 22:59:36.191707  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8045 22:59:36.192195  ==

 8046 22:59:36.192621  DQS Delay:

 8047 22:59:36.195528  DQS0 = 0, DQS1 = 0

 8048 22:59:36.195953  DQM Delay:

 8049 22:59:36.196334  DQM0 = 132, DQM1 = 123

 8050 22:59:36.198538  DQ Delay:

 8051 22:59:36.201666  DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =132

 8052 22:59:36.205431  DQ4 =132, DQ5 =120, DQ6 =140, DQ7 =140

 8053 22:59:36.208544  DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120

 8054 22:59:36.211541  DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =128

 8055 22:59:36.211971  

 8056 22:59:36.212304  

 8057 22:59:36.212699  

 8058 22:59:36.215288  [DramC_TX_OE_Calibration] TA2

 8059 22:59:36.218492  Original DQ_B0 (3 6) =30, OEN = 27

 8060 22:59:36.221457  Original DQ_B1 (3 6) =30, OEN = 27

 8061 22:59:36.225054  24, 0x0, End_B0=24 End_B1=24

 8062 22:59:36.225488  25, 0x0, End_B0=25 End_B1=25

 8063 22:59:36.227907  26, 0x0, End_B0=26 End_B1=26

 8064 22:59:36.231811  27, 0x0, End_B0=27 End_B1=27

 8065 22:59:36.234962  28, 0x0, End_B0=28 End_B1=28

 8066 22:59:36.238066  29, 0x0, End_B0=29 End_B1=29

 8067 22:59:36.238605  30, 0x0, End_B0=30 End_B1=30

 8068 22:59:36.241431  31, 0x4141, End_B0=30 End_B1=30

 8069 22:59:36.244301  Byte0 end_step=30  best_step=27

 8070 22:59:36.248030  Byte1 end_step=30  best_step=27

 8071 22:59:36.251399  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8072 22:59:36.254372  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8073 22:59:36.254803  

 8074 22:59:36.255135  

 8075 22:59:36.260979  [DQSOSCAuto] RK0, (LSB)MR18= 0x2011, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps

 8076 22:59:36.264652  CH0 RK0: MR19=303, MR18=2011

 8077 22:59:36.271090  CH0_RK0: MR19=0x303, MR18=0x2011, DQSOSC=393, MR23=63, INC=23, DEC=15

 8078 22:59:36.271611  

 8079 22:59:36.274190  ----->DramcWriteLeveling(PI) begin...

 8080 22:59:36.274620  ==

 8081 22:59:36.277825  Dram Type= 6, Freq= 0, CH_0, rank 1

 8082 22:59:36.280745  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8083 22:59:36.281171  ==

 8084 22:59:36.284144  Write leveling (Byte 0): 35 => 35

 8085 22:59:36.287727  Write leveling (Byte 1): 28 => 28

 8086 22:59:36.290877  DramcWriteLeveling(PI) end<-----

 8087 22:59:36.291300  

 8088 22:59:36.291630  ==

 8089 22:59:36.294513  Dram Type= 6, Freq= 0, CH_0, rank 1

 8090 22:59:36.297450  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8091 22:59:36.300625  ==

 8092 22:59:36.301047  [Gating] SW mode calibration

 8093 22:59:36.310716  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8094 22:59:36.314025  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8095 22:59:36.317411   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8096 22:59:36.324245   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8097 22:59:36.327270   1  4  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8098 22:59:36.330490   1  4 12 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 1)

 8099 22:59:36.337415   1  4 16 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)

 8100 22:59:36.340291   1  4 20 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)

 8101 22:59:36.343900   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8102 22:59:36.350618   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8103 22:59:36.353430   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8104 22:59:36.357196   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8105 22:59:36.363621   1  5  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8106 22:59:36.366685   1  5 12 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)

 8107 22:59:36.369662   1  5 16 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 0)

 8108 22:59:36.376592   1  5 20 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)

 8109 22:59:36.379824   1  5 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)

 8110 22:59:36.383367   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8111 22:59:36.389487   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8112 22:59:36.393149   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8113 22:59:36.396803   1  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8114 22:59:36.403097   1  6 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)

 8115 22:59:36.405945   1  6 16 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)

 8116 22:59:36.409793   1  6 20 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)

 8117 22:59:36.415818   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8118 22:59:36.419708   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8119 22:59:36.422749   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8120 22:59:36.429375   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8121 22:59:36.432846   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8122 22:59:36.435865   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8123 22:59:36.442935   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 8124 22:59:36.445774   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8125 22:59:36.449168   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 8126 22:59:36.456037   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8127 22:59:36.459331   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8128 22:59:36.462326   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8129 22:59:36.468669   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8130 22:59:36.473323   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8131 22:59:36.475348   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8132 22:59:36.482270   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8133 22:59:36.485358   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8134 22:59:36.488298   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8135 22:59:36.495392   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8136 22:59:36.498326   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8137 22:59:36.502100   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8138 22:59:36.508380   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 8139 22:59:36.511990   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 8140 22:59:36.514927  Total UI for P1: 0, mck2ui 16

 8141 22:59:36.518069  best dqsien dly found for B0: ( 1,  9, 12)

 8142 22:59:36.521727   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 8143 22:59:36.528707   1  9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8144 22:59:36.529137  Total UI for P1: 0, mck2ui 16

 8145 22:59:36.534730  best dqsien dly found for B1: ( 1,  9, 18)

 8146 22:59:36.538403  best DQS0 dly(MCK, UI, PI) = (1, 9, 12)

 8147 22:59:36.541930  best DQS1 dly(MCK, UI, PI) = (1, 9, 18)

 8148 22:59:36.542351  

 8149 22:59:36.544967  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)

 8150 22:59:36.548410  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)

 8151 22:59:36.551224  [Gating] SW calibration Done

 8152 22:59:36.551645  ==

 8153 22:59:36.554807  Dram Type= 6, Freq= 0, CH_0, rank 1

 8154 22:59:36.558172  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8155 22:59:36.558696  ==

 8156 22:59:36.561757  RX Vref Scan: 0

 8157 22:59:36.562177  

 8158 22:59:36.562701  RX Vref 0 -> 0, step: 1

 8159 22:59:36.563052  

 8160 22:59:36.564763  RX Delay 0 -> 252, step: 8

 8161 22:59:36.567730  iDelay=208, Bit 0, Center 135 (80 ~ 191) 112

 8162 22:59:36.574378  iDelay=208, Bit 1, Center 135 (80 ~ 191) 112

 8163 22:59:36.577962  iDelay=208, Bit 2, Center 127 (72 ~ 183) 112

 8164 22:59:36.581003  iDelay=208, Bit 3, Center 127 (72 ~ 183) 112

 8165 22:59:36.584813  iDelay=208, Bit 4, Center 135 (80 ~ 191) 112

 8166 22:59:36.587824  iDelay=208, Bit 5, Center 123 (64 ~ 183) 120

 8167 22:59:36.594451  iDelay=208, Bit 6, Center 139 (80 ~ 199) 120

 8168 22:59:36.597375  iDelay=208, Bit 7, Center 147 (88 ~ 207) 120

 8169 22:59:36.600922  iDelay=208, Bit 8, Center 115 (56 ~ 175) 120

 8170 22:59:36.604374  iDelay=208, Bit 9, Center 115 (56 ~ 175) 120

 8171 22:59:36.610910  iDelay=208, Bit 10, Center 131 (72 ~ 191) 120

 8172 22:59:36.614327  iDelay=208, Bit 11, Center 123 (64 ~ 183) 120

 8173 22:59:36.617660  iDelay=208, Bit 12, Center 131 (72 ~ 191) 120

 8174 22:59:36.620607  iDelay=208, Bit 13, Center 135 (80 ~ 191) 112

 8175 22:59:36.624408  iDelay=208, Bit 14, Center 139 (80 ~ 199) 120

 8176 22:59:36.631025  iDelay=208, Bit 15, Center 135 (80 ~ 191) 112

 8177 22:59:36.631573  ==

 8178 22:59:36.633954  Dram Type= 6, Freq= 0, CH_0, rank 1

 8179 22:59:36.637224  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8180 22:59:36.637733  ==

 8181 22:59:36.638223  DQS Delay:

 8182 22:59:36.640792  DQS0 = 0, DQS1 = 0

 8183 22:59:36.641214  DQM Delay:

 8184 22:59:36.643822  DQM0 = 133, DQM1 = 128

 8185 22:59:36.644239  DQ Delay:

 8186 22:59:36.647401  DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127

 8187 22:59:36.650797  DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =147

 8188 22:59:36.653701  DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123

 8189 22:59:36.657201  DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135

 8190 22:59:36.657637  

 8191 22:59:36.660171  

 8192 22:59:36.660772  ==

 8193 22:59:36.663721  Dram Type= 6, Freq= 0, CH_0, rank 1

 8194 22:59:36.666849  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8195 22:59:36.667336  ==

 8196 22:59:36.667682  

 8197 22:59:36.668016  

 8198 22:59:36.670347  	TX Vref Scan disable

 8199 22:59:36.670770   == TX Byte 0 ==

 8200 22:59:36.676765  Update DQ  dly =991 (3 ,6, 31)  DQ  OEN =(3 ,3)

 8201 22:59:36.680122  Update DQM dly =991 (3 ,6, 31)  DQM OEN =(3 ,3)

 8202 22:59:36.680205   == TX Byte 1 ==

 8203 22:59:36.686922  Update DQ  dly =984 (3 ,6, 24)  DQ  OEN =(3 ,3)

 8204 22:59:36.690025  Update DQM dly =984 (3 ,6, 24)  DQM OEN =(3 ,3)

 8205 22:59:36.690108  ==

 8206 22:59:36.693075  Dram Type= 6, Freq= 0, CH_0, rank 1

 8207 22:59:36.696236  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8208 22:59:36.696335  ==

 8209 22:59:36.710614  

 8210 22:59:36.713543  TX Vref early break, caculate TX vref

 8211 22:59:36.717290  TX Vref=16, minBit 0, minWin=22, winSum=375

 8212 22:59:36.720329  TX Vref=18, minBit 0, minWin=23, winSum=391

 8213 22:59:36.723512  TX Vref=20, minBit 0, minWin=23, winSum=395

 8214 22:59:36.727175  TX Vref=22, minBit 3, minWin=24, winSum=406

 8215 22:59:36.730263  TX Vref=24, minBit 2, minWin=24, winSum=407

 8216 22:59:36.736940  TX Vref=26, minBit 0, minWin=25, winSum=416

 8217 22:59:36.739955  TX Vref=28, minBit 0, minWin=24, winSum=410

 8218 22:59:36.743758  TX Vref=30, minBit 0, minWin=24, winSum=402

 8219 22:59:36.746675  TX Vref=32, minBit 1, minWin=23, winSum=398

 8220 22:59:36.750346  TX Vref=34, minBit 1, minWin=23, winSum=386

 8221 22:59:36.757076  [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 26

 8222 22:59:36.757160  

 8223 22:59:36.760037  Final TX Range 0 Vref 26

 8224 22:59:36.760119  

 8225 22:59:36.760184  ==

 8226 22:59:36.763616  Dram Type= 6, Freq= 0, CH_0, rank 1

 8227 22:59:36.766525  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8228 22:59:36.766607  ==

 8229 22:59:36.766673  

 8230 22:59:36.766734  

 8231 22:59:36.770079  	TX Vref Scan disable

 8232 22:59:36.776814  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps

 8233 22:59:36.776896   == TX Byte 0 ==

 8234 22:59:36.779804  u2DelayCellOfst[0]=11 cells (3 PI)

 8235 22:59:36.783230  u2DelayCellOfst[1]=14 cells (4 PI)

 8236 22:59:36.786291  u2DelayCellOfst[2]=11 cells (3 PI)

 8237 22:59:36.789957  u2DelayCellOfst[3]=14 cells (4 PI)

 8238 22:59:36.793073  u2DelayCellOfst[4]=7 cells (2 PI)

 8239 22:59:36.796748  u2DelayCellOfst[5]=0 cells (0 PI)

 8240 22:59:36.799850  u2DelayCellOfst[6]=18 cells (5 PI)

 8241 22:59:36.802860  u2DelayCellOfst[7]=18 cells (5 PI)

 8242 22:59:36.805973  Update DQ  dly =989 (3 ,6, 29)  DQ  OEN =(3 ,3)

 8243 22:59:36.809442  Update DQM dly =991 (3 ,6, 31)  DQM OEN =(3 ,3)

 8244 22:59:36.812978   == TX Byte 1 ==

 8245 22:59:36.816037  u2DelayCellOfst[8]=0 cells (0 PI)

 8246 22:59:36.819782  u2DelayCellOfst[9]=3 cells (1 PI)

 8247 22:59:36.819864  u2DelayCellOfst[10]=7 cells (2 PI)

 8248 22:59:36.822897  u2DelayCellOfst[11]=3 cells (1 PI)

 8249 22:59:36.826022  u2DelayCellOfst[12]=11 cells (3 PI)

 8250 22:59:36.829120  u2DelayCellOfst[13]=11 cells (3 PI)

 8251 22:59:36.832253  u2DelayCellOfst[14]=18 cells (5 PI)

 8252 22:59:36.835738  u2DelayCellOfst[15]=11 cells (3 PI)

 8253 22:59:36.842417  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 8254 22:59:36.845515  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 8255 22:59:36.845597  DramC Write-DBI on

 8256 22:59:36.849212  ==

 8257 22:59:36.852171  Dram Type= 6, Freq= 0, CH_0, rank 1

 8258 22:59:36.855850  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8259 22:59:36.855933  ==

 8260 22:59:36.855998  

 8261 22:59:36.856058  

 8262 22:59:36.858841  	TX Vref Scan disable

 8263 22:59:36.858923   == TX Byte 0 ==

 8264 22:59:36.865435  Update DQM dly =735 (2 ,6, 31)  DQM OEN =(3 ,3)

 8265 22:59:36.865518   == TX Byte 1 ==

 8266 22:59:36.868990  Update DQM dly =725 (2 ,6, 21)  DQM OEN =(3 ,3)

 8267 22:59:36.872000  DramC Write-DBI off

 8268 22:59:36.872087  

 8269 22:59:36.872156  [DATLAT]

 8270 22:59:36.875626  Freq=1600, CH0 RK1

 8271 22:59:36.875720  

 8272 22:59:36.875794  DATLAT Default: 0xf

 8273 22:59:36.878641  0, 0xFFFF, sum = 0

 8274 22:59:36.878738  1, 0xFFFF, sum = 0

 8275 22:59:36.882448  2, 0xFFFF, sum = 0

 8276 22:59:36.882552  3, 0xFFFF, sum = 0

 8277 22:59:36.885507  4, 0xFFFF, sum = 0

 8278 22:59:36.885621  5, 0xFFFF, sum = 0

 8279 22:59:36.888404  6, 0xFFFF, sum = 0

 8280 22:59:36.892208  7, 0xFFFF, sum = 0

 8281 22:59:36.892293  8, 0xFFFF, sum = 0

 8282 22:59:36.895225  9, 0xFFFF, sum = 0

 8283 22:59:36.895313  10, 0xFFFF, sum = 0

 8284 22:59:36.898446  11, 0xFFFF, sum = 0

 8285 22:59:36.898558  12, 0xFFFF, sum = 0

 8286 22:59:36.901447  13, 0xFFFF, sum = 0

 8287 22:59:36.901536  14, 0x0, sum = 1

 8288 22:59:36.905220  15, 0x0, sum = 2

 8289 22:59:36.905346  16, 0x0, sum = 3

 8290 22:59:36.908146  17, 0x0, sum = 4

 8291 22:59:36.908241  best_step = 15

 8292 22:59:36.908316  

 8293 22:59:36.908385  ==

 8294 22:59:36.911863  Dram Type= 6, Freq= 0, CH_0, rank 1

 8295 22:59:36.914893  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8296 22:59:36.918336  ==

 8297 22:59:36.918418  RX Vref Scan: 0

 8298 22:59:36.918484  

 8299 22:59:36.921674  RX Vref 0 -> 0, step: 1

 8300 22:59:36.921757  

 8301 22:59:36.924537  RX Delay 11 -> 252, step: 4

 8302 22:59:36.927753  iDelay=195, Bit 0, Center 128 (79 ~ 178) 100

 8303 22:59:36.931625  iDelay=195, Bit 1, Center 134 (79 ~ 190) 112

 8304 22:59:36.934760  iDelay=195, Bit 2, Center 124 (71 ~ 178) 108

 8305 22:59:36.941398  iDelay=195, Bit 3, Center 128 (75 ~ 182) 108

 8306 22:59:36.944695  iDelay=195, Bit 4, Center 132 (79 ~ 186) 108

 8307 22:59:36.948177  iDelay=195, Bit 5, Center 120 (67 ~ 174) 108

 8308 22:59:36.951319  iDelay=195, Bit 6, Center 138 (83 ~ 194) 112

 8309 22:59:36.954390  iDelay=195, Bit 7, Center 140 (87 ~ 194) 108

 8310 22:59:36.960888  iDelay=195, Bit 8, Center 116 (63 ~ 170) 108

 8311 22:59:36.964414  iDelay=195, Bit 9, Center 112 (59 ~ 166) 108

 8312 22:59:36.968065  iDelay=195, Bit 10, Center 128 (75 ~ 182) 108

 8313 22:59:36.970953  iDelay=195, Bit 11, Center 120 (67 ~ 174) 108

 8314 22:59:36.974525  iDelay=195, Bit 12, Center 128 (75 ~ 182) 108

 8315 22:59:36.981099  iDelay=195, Bit 13, Center 132 (79 ~ 186) 108

 8316 22:59:36.984254  iDelay=195, Bit 14, Center 136 (83 ~ 190) 108

 8317 22:59:36.987913  iDelay=195, Bit 15, Center 132 (79 ~ 186) 108

 8318 22:59:36.988090  ==

 8319 22:59:36.990937  Dram Type= 6, Freq= 0, CH_0, rank 1

 8320 22:59:36.997560  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8321 22:59:36.997807  ==

 8322 22:59:36.998138  DQS Delay:

 8323 22:59:36.998379  DQS0 = 0, DQS1 = 0

 8324 22:59:37.000734  DQM Delay:

 8325 22:59:37.001029  DQM0 = 130, DQM1 = 125

 8326 22:59:37.003661  DQ Delay:

 8327 22:59:37.007636  DQ0 =128, DQ1 =134, DQ2 =124, DQ3 =128

 8328 22:59:37.010807  DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =140

 8329 22:59:37.014351  DQ8 =116, DQ9 =112, DQ10 =128, DQ11 =120

 8330 22:59:37.017313  DQ12 =128, DQ13 =132, DQ14 =136, DQ15 =132

 8331 22:59:37.017734  

 8332 22:59:37.018063  

 8333 22:59:37.018367  

 8334 22:59:37.020835  [DramC_TX_OE_Calibration] TA2

 8335 22:59:37.023882  Original DQ_B0 (3 6) =30, OEN = 27

 8336 22:59:37.026980  Original DQ_B1 (3 6) =30, OEN = 27

 8337 22:59:37.030706  24, 0x0, End_B0=24 End_B1=24

 8338 22:59:37.031129  25, 0x0, End_B0=25 End_B1=25

 8339 22:59:37.033892  26, 0x0, End_B0=26 End_B1=26

 8340 22:59:37.037189  27, 0x0, End_B0=27 End_B1=27

 8341 22:59:37.040174  28, 0x0, End_B0=28 End_B1=28

 8342 22:59:37.043160  29, 0x0, End_B0=29 End_B1=29

 8343 22:59:37.043563  30, 0x0, End_B0=30 End_B1=30

 8344 22:59:37.047157  31, 0x4141, End_B0=30 End_B1=30

 8345 22:59:37.050268  Byte0 end_step=30  best_step=27

 8346 22:59:37.053361  Byte1 end_step=30  best_step=27

 8347 22:59:37.057098  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8348 22:59:37.060239  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8349 22:59:37.060714  

 8350 22:59:37.061148  

 8351 22:59:37.066737  [DQSOSCAuto] RK1, (LSB)MR18= 0x1e02, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps

 8352 22:59:37.069648  CH0 RK1: MR19=303, MR18=1E02

 8353 22:59:37.076713  CH0_RK1: MR19=0x303, MR18=0x1E02, DQSOSC=394, MR23=63, INC=23, DEC=15

 8354 22:59:37.079706  [RxdqsGatingPostProcess] freq 1600

 8355 22:59:37.086330  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 8356 22:59:37.086750  best DQS0 dly(2T, 0.5T) = (1, 1)

 8357 22:59:37.090135  best DQS1 dly(2T, 0.5T) = (1, 1)

 8358 22:59:37.092957  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8359 22:59:37.095969  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8360 22:59:37.099532  best DQS0 dly(2T, 0.5T) = (1, 1)

 8361 22:59:37.102667  best DQS1 dly(2T, 0.5T) = (1, 1)

 8362 22:59:37.106310  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8363 22:59:37.109422  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8364 22:59:37.112511  Pre-setting of DQS Precalculation

 8365 22:59:37.116107  [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15

 8366 22:59:37.116400  ==

 8367 22:59:37.119012  Dram Type= 6, Freq= 0, CH_1, rank 0

 8368 22:59:37.125389  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8369 22:59:37.125610  ==

 8370 22:59:37.128930  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 8371 22:59:37.135101  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1

 8372 22:59:37.138996  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1

 8373 22:59:37.145077  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 8374 22:59:37.153872  [CA 0] Center 41 (12~71) winsize 60

 8375 22:59:37.156852  [CA 1] Center 42 (12~72) winsize 61

 8376 22:59:37.159991  [CA 2] Center 37 (8~66) winsize 59

 8377 22:59:37.162988  [CA 3] Center 36 (7~65) winsize 59

 8378 22:59:37.166733  [CA 4] Center 36 (7~66) winsize 60

 8379 22:59:37.169747  [CA 5] Center 36 (7~66) winsize 60

 8380 22:59:37.169955  

 8381 22:59:37.173422  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 8382 22:59:37.173667  

 8383 22:59:37.179436  [CATrainingPosCal] consider 1 rank data

 8384 22:59:37.179562  u2DelayCellTimex100 = 262/100 ps

 8385 22:59:37.185982  CA0 delay=41 (12~71),Diff = 5 PI (18 cell)

 8386 22:59:37.189645  CA1 delay=42 (12~72),Diff = 6 PI (22 cell)

 8387 22:59:37.192749  CA2 delay=37 (8~66),Diff = 1 PI (3 cell)

 8388 22:59:37.195864  CA3 delay=36 (7~65),Diff = 0 PI (0 cell)

 8389 22:59:37.199285  CA4 delay=36 (7~66),Diff = 0 PI (0 cell)

 8390 22:59:37.202452  CA5 delay=36 (7~66),Diff = 0 PI (0 cell)

 8391 22:59:37.202551  

 8392 22:59:37.206128  CA PerBit enable=1, Macro0, CA PI delay=36

 8393 22:59:37.206208  

 8394 22:59:37.209221  [CBTSetCACLKResult] CA Dly = 36

 8395 22:59:37.212293  CS Dly: 8 (0~39)

 8396 22:59:37.215895  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0

 8397 22:59:37.218934  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0

 8398 22:59:37.219020  ==

 8399 22:59:37.222673  Dram Type= 6, Freq= 0, CH_1, rank 1

 8400 22:59:37.228743  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8401 22:59:37.228824  ==

 8402 22:59:37.232265  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 8403 22:59:37.239042  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1

 8404 22:59:37.242262  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1

 8405 22:59:37.248964  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 8406 22:59:37.256318  [CA 0] Center 42 (14~71) winsize 58

 8407 22:59:37.260041  [CA 1] Center 42 (13~72) winsize 60

 8408 22:59:37.263032  [CA 2] Center 37 (8~67) winsize 60

 8409 22:59:37.266177  [CA 3] Center 37 (7~67) winsize 61

 8410 22:59:37.269354  [CA 4] Center 38 (9~67) winsize 59

 8411 22:59:37.272890  [CA 5] Center 37 (8~67) winsize 60

 8412 22:59:37.272973  

 8413 22:59:37.276406  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 8414 22:59:37.276488  

 8415 22:59:37.279320  [CATrainingPosCal] consider 2 rank data

 8416 22:59:37.282867  u2DelayCellTimex100 = 262/100 ps

 8417 22:59:37.289517  CA0 delay=42 (14~71),Diff = 6 PI (22 cell)

 8418 22:59:37.292406  CA1 delay=42 (13~72),Diff = 6 PI (22 cell)

 8419 22:59:37.296086  CA2 delay=37 (8~66),Diff = 1 PI (3 cell)

 8420 22:59:37.299130  CA3 delay=36 (7~65),Diff = 0 PI (0 cell)

 8421 22:59:37.302821  CA4 delay=37 (9~66),Diff = 1 PI (3 cell)

 8422 22:59:37.305750  CA5 delay=37 (8~66),Diff = 1 PI (3 cell)

 8423 22:59:37.305834  

 8424 22:59:37.309558  CA PerBit enable=1, Macro0, CA PI delay=36

 8425 22:59:37.309641  

 8426 22:59:37.312622  [CBTSetCACLKResult] CA Dly = 36

 8427 22:59:37.315763  CS Dly: 10 (0~43)

 8428 22:59:37.319478  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0

 8429 22:59:37.322548  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0

 8430 22:59:37.322630  

 8431 22:59:37.325641  ----->DramcWriteLeveling(PI) begin...

 8432 22:59:37.325724  ==

 8433 22:59:37.329254  Dram Type= 6, Freq= 0, CH_1, rank 0

 8434 22:59:37.335352  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8435 22:59:37.335435  ==

 8436 22:59:37.338845  Write leveling (Byte 0): 23 => 23

 8437 22:59:37.341909  Write leveling (Byte 1): 27 => 27

 8438 22:59:37.341992  DramcWriteLeveling(PI) end<-----

 8439 22:59:37.345638  

 8440 22:59:37.345719  ==

 8441 22:59:37.348492  Dram Type= 6, Freq= 0, CH_1, rank 0

 8442 22:59:37.352222  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8443 22:59:37.352305  ==

 8444 22:59:37.355368  [Gating] SW mode calibration

 8445 22:59:37.362085  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8446 22:59:37.365046  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8447 22:59:37.371911   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8448 22:59:37.375045   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8449 22:59:37.378601   1  4  8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)

 8450 22:59:37.384929   1  4 12 | B1->B0 | 3131 3434 | 0 1 | (1 0) (1 1)

 8451 22:59:37.387955   1  4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8452 22:59:37.391556   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8453 22:59:37.398429   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8454 22:59:37.401628   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8455 22:59:37.404685   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8456 22:59:37.411249   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8457 22:59:37.414855   1  5  8 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)

 8458 22:59:37.417935   1  5 12 | B1->B0 | 3232 2828 | 1 0 | (1 0) (0 1)

 8459 22:59:37.424962   1  5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8460 22:59:37.427944   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8461 22:59:37.431071   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8462 22:59:37.437742   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8463 22:59:37.441231   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8464 22:59:37.444330   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8465 22:59:37.451232   1  6  8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 8466 22:59:37.454150   1  6 12 | B1->B0 | 3232 4040 | 0 0 | (0 0) (0 0)

 8467 22:59:37.457874   1  6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8468 22:59:37.464027   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8469 22:59:37.467216   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8470 22:59:37.470963   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8471 22:59:37.477638   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8472 22:59:37.480621   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8473 22:59:37.483576   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8474 22:59:37.490518   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8475 22:59:37.493468   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8476 22:59:37.497070   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8477 22:59:37.503495   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8478 22:59:37.507256   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8479 22:59:37.510217   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8480 22:59:37.516720   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8481 22:59:37.520377   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8482 22:59:37.523316   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8483 22:59:37.530077   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8484 22:59:37.533286   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8485 22:59:37.536945   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8486 22:59:37.543555   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8487 22:59:37.546392   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8488 22:59:37.549959   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8489 22:59:37.556758   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 8490 22:59:37.559703   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8491 22:59:37.562874   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8492 22:59:37.566483  Total UI for P1: 0, mck2ui 16

 8493 22:59:37.569697  best dqsien dly found for B0: ( 1,  9, 10)

 8494 22:59:37.572779  Total UI for P1: 0, mck2ui 16

 8495 22:59:37.576395  best dqsien dly found for B1: ( 1,  9, 12)

 8496 22:59:37.579582  best DQS0 dly(MCK, UI, PI) = (1, 9, 10)

 8497 22:59:37.583173  best DQS1 dly(MCK, UI, PI) = (1, 9, 12)

 8498 22:59:37.586210  

 8499 22:59:37.589204  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)

 8500 22:59:37.592726  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)

 8501 22:59:37.596371  [Gating] SW calibration Done

 8502 22:59:37.596479  ==

 8503 22:59:37.599485  Dram Type= 6, Freq= 0, CH_1, rank 0

 8504 22:59:37.603005  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8505 22:59:37.603129  ==

 8506 22:59:37.606426  RX Vref Scan: 0

 8507 22:59:37.606509  

 8508 22:59:37.606575  RX Vref 0 -> 0, step: 1

 8509 22:59:37.606635  

 8510 22:59:37.609416  RX Delay 0 -> 252, step: 8

 8511 22:59:37.612575  iDelay=208, Bit 0, Center 139 (88 ~ 191) 104

 8512 22:59:37.616153  iDelay=208, Bit 1, Center 131 (80 ~ 183) 104

 8513 22:59:37.622581  iDelay=208, Bit 2, Center 127 (72 ~ 183) 112

 8514 22:59:37.625804  iDelay=208, Bit 3, Center 135 (80 ~ 191) 112

 8515 22:59:37.629460  iDelay=208, Bit 4, Center 131 (72 ~ 191) 120

 8516 22:59:37.632633  iDelay=208, Bit 5, Center 151 (96 ~ 207) 112

 8517 22:59:37.636269  iDelay=208, Bit 6, Center 147 (96 ~ 199) 104

 8518 22:59:37.642465  iDelay=208, Bit 7, Center 135 (80 ~ 191) 112

 8519 22:59:37.646032  iDelay=208, Bit 8, Center 119 (64 ~ 175) 112

 8520 22:59:37.648934  iDelay=208, Bit 9, Center 115 (56 ~ 175) 120

 8521 22:59:37.652505  iDelay=208, Bit 10, Center 127 (72 ~ 183) 112

 8522 22:59:37.655514  iDelay=208, Bit 11, Center 119 (64 ~ 175) 112

 8523 22:59:37.662193  iDelay=208, Bit 12, Center 135 (80 ~ 191) 112

 8524 22:59:37.665272  iDelay=208, Bit 13, Center 139 (80 ~ 199) 120

 8525 22:59:37.668972  iDelay=208, Bit 14, Center 135 (80 ~ 191) 112

 8526 22:59:37.672038  iDelay=208, Bit 15, Center 135 (80 ~ 191) 112

 8527 22:59:37.675100  ==

 8528 22:59:37.675183  Dram Type= 6, Freq= 0, CH_1, rank 0

 8529 22:59:37.681801  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8530 22:59:37.681885  ==

 8531 22:59:37.681950  DQS Delay:

 8532 22:59:37.685021  DQS0 = 0, DQS1 = 0

 8533 22:59:37.685104  DQM Delay:

 8534 22:59:37.688610  DQM0 = 137, DQM1 = 128

 8535 22:59:37.688693  DQ Delay:

 8536 22:59:37.691549  DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =135

 8537 22:59:37.695113  DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135

 8538 22:59:37.698603  DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119

 8539 22:59:37.701685  DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135

 8540 22:59:37.701769  

 8541 22:59:37.701834  

 8542 22:59:37.701893  ==

 8543 22:59:37.705287  Dram Type= 6, Freq= 0, CH_1, rank 0

 8544 22:59:37.711315  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8545 22:59:37.711399  ==

 8546 22:59:37.711465  

 8547 22:59:37.711525  

 8548 22:59:37.715002  	TX Vref Scan disable

 8549 22:59:37.715086   == TX Byte 0 ==

 8550 22:59:37.718090  Update DQ  dly =979 (3 ,6, 19)  DQ  OEN =(3 ,3)

 8551 22:59:37.724709  Update DQM dly =979 (3 ,6, 19)  DQM OEN =(3 ,3)

 8552 22:59:37.724805   == TX Byte 1 ==

 8553 22:59:37.727674  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 8554 22:59:37.734536  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8555 22:59:37.734649  ==

 8556 22:59:37.737849  Dram Type= 6, Freq= 0, CH_1, rank 0

 8557 22:59:37.741544  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8558 22:59:37.741680  ==

 8559 22:59:37.754628  

 8560 22:59:37.757882  TX Vref early break, caculate TX vref

 8561 22:59:37.760947  TX Vref=16, minBit 5, minWin=21, winSum=371

 8562 22:59:37.764696  TX Vref=18, minBit 5, minWin=21, winSum=379

 8563 22:59:37.768199  TX Vref=20, minBit 0, minWin=23, winSum=390

 8564 22:59:37.771389  TX Vref=22, minBit 5, minWin=22, winSum=399

 8565 22:59:37.774620  TX Vref=24, minBit 5, minWin=23, winSum=407

 8566 22:59:37.781162  TX Vref=26, minBit 0, minWin=24, winSum=412

 8567 22:59:37.784181  TX Vref=28, minBit 0, minWin=24, winSum=416

 8568 22:59:37.787102  TX Vref=30, minBit 0, minWin=24, winSum=408

 8569 22:59:37.790100  TX Vref=32, minBit 0, minWin=23, winSum=400

 8570 22:59:37.793745  TX Vref=34, minBit 5, minWin=22, winSum=391

 8571 22:59:37.800078  [TxChooseVref] Worse bit 0, Min win 24, Win sum 416, Final Vref 28

 8572 22:59:37.800204  

 8573 22:59:37.803723  Final TX Range 0 Vref 28

 8574 22:59:37.803835  

 8575 22:59:37.803903  ==

 8576 22:59:37.806710  Dram Type= 6, Freq= 0, CH_1, rank 0

 8577 22:59:37.810431  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8578 22:59:37.810514  ==

 8579 22:59:37.810578  

 8580 22:59:37.810639  

 8581 22:59:37.813332  	TX Vref Scan disable

 8582 22:59:37.820034  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps

 8583 22:59:37.820141   == TX Byte 0 ==

 8584 22:59:37.823151  u2DelayCellOfst[0]=14 cells (4 PI)

 8585 22:59:37.826829  u2DelayCellOfst[1]=11 cells (3 PI)

 8586 22:59:37.830001  u2DelayCellOfst[2]=0 cells (0 PI)

 8587 22:59:37.833096  u2DelayCellOfst[3]=3 cells (1 PI)

 8588 22:59:37.836791  u2DelayCellOfst[4]=7 cells (2 PI)

 8589 22:59:37.839871  u2DelayCellOfst[5]=18 cells (5 PI)

 8590 22:59:37.842927  u2DelayCellOfst[6]=18 cells (5 PI)

 8591 22:59:37.846654  u2DelayCellOfst[7]=3 cells (1 PI)

 8592 22:59:37.849726  Update DQ  dly =977 (3 ,6, 17)  DQ  OEN =(3 ,3)

 8593 22:59:37.852891  Update DQM dly =979 (3 ,6, 19)  DQM OEN =(3 ,3)

 8594 22:59:37.856523   == TX Byte 1 ==

 8595 22:59:37.859989  u2DelayCellOfst[8]=0 cells (0 PI)

 8596 22:59:37.862906  u2DelayCellOfst[9]=3 cells (1 PI)

 8597 22:59:37.866538  u2DelayCellOfst[10]=11 cells (3 PI)

 8598 22:59:37.866621  u2DelayCellOfst[11]=3 cells (1 PI)

 8599 22:59:37.869658  u2DelayCellOfst[12]=14 cells (4 PI)

 8600 22:59:37.872749  u2DelayCellOfst[13]=14 cells (4 PI)

 8601 22:59:37.876410  u2DelayCellOfst[14]=18 cells (5 PI)

 8602 22:59:37.879364  u2DelayCellOfst[15]=18 cells (5 PI)

 8603 22:59:37.886166  Update DQ  dly =979 (3 ,6, 19)  DQ  OEN =(3 ,3)

 8604 22:59:37.889368  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8605 22:59:37.889451  DramC Write-DBI on

 8606 22:59:37.892409  ==

 8607 22:59:37.892493  Dram Type= 6, Freq= 0, CH_1, rank 0

 8608 22:59:37.899041  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8609 22:59:37.899125  ==

 8610 22:59:37.899190  

 8611 22:59:37.899249  

 8612 22:59:37.902616  	TX Vref Scan disable

 8613 22:59:37.902699   == TX Byte 0 ==

 8614 22:59:37.909670  Update DQM dly =720 (2 ,6, 16)  DQM OEN =(3 ,3)

 8615 22:59:37.909753   == TX Byte 1 ==

 8616 22:59:37.912606  Update DQM dly =722 (2 ,6, 18)  DQM OEN =(3 ,3)

 8617 22:59:37.915558  DramC Write-DBI off

 8618 22:59:37.915640  

 8619 22:59:37.915704  [DATLAT]

 8620 22:59:37.919134  Freq=1600, CH1 RK0

 8621 22:59:37.919217  

 8622 22:59:37.919282  DATLAT Default: 0xf

 8623 22:59:37.922118  0, 0xFFFF, sum = 0

 8624 22:59:37.922201  1, 0xFFFF, sum = 0

 8625 22:59:37.925947  2, 0xFFFF, sum = 0

 8626 22:59:37.926029  3, 0xFFFF, sum = 0

 8627 22:59:37.928980  4, 0xFFFF, sum = 0

 8628 22:59:37.929101  5, 0xFFFF, sum = 0

 8629 22:59:37.932562  6, 0xFFFF, sum = 0

 8630 22:59:37.932641  7, 0xFFFF, sum = 0

 8631 22:59:37.935687  8, 0xFFFF, sum = 0

 8632 22:59:37.938639  9, 0xFFFF, sum = 0

 8633 22:59:37.938723  10, 0xFFFF, sum = 0

 8634 22:59:37.942381  11, 0xFFFF, sum = 0

 8635 22:59:37.942490  12, 0xFFFF, sum = 0

 8636 22:59:37.945393  13, 0xFFFF, sum = 0

 8637 22:59:37.945477  14, 0x0, sum = 1

 8638 22:59:37.948671  15, 0x0, sum = 2

 8639 22:59:37.948755  16, 0x0, sum = 3

 8640 22:59:37.952284  17, 0x0, sum = 4

 8641 22:59:37.952393  best_step = 15

 8642 22:59:37.952485  

 8643 22:59:37.952605  ==

 8644 22:59:37.955263  Dram Type= 6, Freq= 0, CH_1, rank 0

 8645 22:59:37.958806  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8646 22:59:37.958888  ==

 8647 22:59:37.961908  RX Vref Scan: 1

 8648 22:59:37.961989  

 8649 22:59:37.965575  Set Vref Range= 24 -> 127

 8650 22:59:37.965656  

 8651 22:59:37.965720  RX Vref 24 -> 127, step: 1

 8652 22:59:37.968409  

 8653 22:59:37.968490  RX Delay 11 -> 252, step: 4

 8654 22:59:37.968593  

 8655 22:59:37.971936  Set Vref, RX VrefLevel [Byte0]: 24

 8656 22:59:37.974958                           [Byte1]: 24

 8657 22:59:37.978700  

 8658 22:59:37.978780  Set Vref, RX VrefLevel [Byte0]: 25

 8659 22:59:37.982395                           [Byte1]: 25

 8660 22:59:37.986278  

 8661 22:59:37.986359  Set Vref, RX VrefLevel [Byte0]: 26

 8662 22:59:37.989993                           [Byte1]: 26

 8663 22:59:37.993708  

 8664 22:59:37.993788  Set Vref, RX VrefLevel [Byte0]: 27

 8665 22:59:37.997350                           [Byte1]: 27

 8666 22:59:38.001686  

 8667 22:59:38.001768  Set Vref, RX VrefLevel [Byte0]: 28

 8668 22:59:38.004655                           [Byte1]: 28

 8669 22:59:38.009364  

 8670 22:59:38.009445  Set Vref, RX VrefLevel [Byte0]: 29

 8671 22:59:38.012317                           [Byte1]: 29

 8672 22:59:38.016482  

 8673 22:59:38.016615  Set Vref, RX VrefLevel [Byte0]: 30

 8674 22:59:38.019945                           [Byte1]: 30

 8675 22:59:38.024628  

 8676 22:59:38.024748  Set Vref, RX VrefLevel [Byte0]: 31

 8677 22:59:38.027614                           [Byte1]: 31

 8678 22:59:38.032209  

 8679 22:59:38.032304  Set Vref, RX VrefLevel [Byte0]: 32

 8680 22:59:38.035268                           [Byte1]: 32

 8681 22:59:38.039870  

 8682 22:59:38.039951  Set Vref, RX VrefLevel [Byte0]: 33

 8683 22:59:38.042945                           [Byte1]: 33

 8684 22:59:38.047311  

 8685 22:59:38.047399  Set Vref, RX VrefLevel [Byte0]: 34

 8686 22:59:38.050267                           [Byte1]: 34

 8687 22:59:38.054931  

 8688 22:59:38.055352  Set Vref, RX VrefLevel [Byte0]: 35

 8689 22:59:38.058679                           [Byte1]: 35

 8690 22:59:38.062941  

 8691 22:59:38.063360  Set Vref, RX VrefLevel [Byte0]: 36

 8692 22:59:38.066123                           [Byte1]: 36

 8693 22:59:38.070419  

 8694 22:59:38.070840  Set Vref, RX VrefLevel [Byte0]: 37

 8695 22:59:38.074311                           [Byte1]: 37

 8696 22:59:38.078268  

 8697 22:59:38.078688  Set Vref, RX VrefLevel [Byte0]: 38

 8698 22:59:38.081409                           [Byte1]: 38

 8699 22:59:38.085821  

 8700 22:59:38.086239  Set Vref, RX VrefLevel [Byte0]: 39

 8701 22:59:38.088842                           [Byte1]: 39

 8702 22:59:38.093160  

 8703 22:59:38.093582  Set Vref, RX VrefLevel [Byte0]: 40

 8704 22:59:38.096903                           [Byte1]: 40

 8705 22:59:38.100782  

 8706 22:59:38.101319  Set Vref, RX VrefLevel [Byte0]: 41

 8707 22:59:38.104306                           [Byte1]: 41

 8708 22:59:38.108742  

 8709 22:59:38.109290  Set Vref, RX VrefLevel [Byte0]: 42

 8710 22:59:38.111769                           [Byte1]: 42

 8711 22:59:38.116290  

 8712 22:59:38.116872  Set Vref, RX VrefLevel [Byte0]: 43

 8713 22:59:38.119468                           [Byte1]: 43

 8714 22:59:38.124046  

 8715 22:59:38.124474  Set Vref, RX VrefLevel [Byte0]: 44

 8716 22:59:38.127198                           [Byte1]: 44

 8717 22:59:38.131569  

 8718 22:59:38.131997  Set Vref, RX VrefLevel [Byte0]: 45

 8719 22:59:38.135190                           [Byte1]: 45

 8720 22:59:38.138755  

 8721 22:59:38.139204  Set Vref, RX VrefLevel [Byte0]: 46

 8722 22:59:38.142490                           [Byte1]: 46

 8723 22:59:38.146429  

 8724 22:59:38.146874  Set Vref, RX VrefLevel [Byte0]: 47

 8725 22:59:38.149742                           [Byte1]: 47

 8726 22:59:38.154145  

 8727 22:59:38.154671  Set Vref, RX VrefLevel [Byte0]: 48

 8728 22:59:38.157553                           [Byte1]: 48

 8729 22:59:38.161760  

 8730 22:59:38.162202  Set Vref, RX VrefLevel [Byte0]: 49

 8731 22:59:38.164819                           [Byte1]: 49

 8732 22:59:38.169103  

 8733 22:59:38.169658  Set Vref, RX VrefLevel [Byte0]: 50

 8734 22:59:38.172698                           [Byte1]: 50

 8735 22:59:38.177067  

 8736 22:59:38.177502  Set Vref, RX VrefLevel [Byte0]: 51

 8737 22:59:38.179996                           [Byte1]: 51

 8738 22:59:38.184773  

 8739 22:59:38.185330  Set Vref, RX VrefLevel [Byte0]: 52

 8740 22:59:38.187810                           [Byte1]: 52

 8741 22:59:38.192027  

 8742 22:59:38.192451  Set Vref, RX VrefLevel [Byte0]: 53

 8743 22:59:38.195370                           [Byte1]: 53

 8744 22:59:38.199539  

 8745 22:59:38.199969  Set Vref, RX VrefLevel [Byte0]: 54

 8746 22:59:38.202750                           [Byte1]: 54

 8747 22:59:38.207056  

 8748 22:59:38.207614  Set Vref, RX VrefLevel [Byte0]: 55

 8749 22:59:38.210741                           [Byte1]: 55

 8750 22:59:38.214836  

 8751 22:59:38.215414  Set Vref, RX VrefLevel [Byte0]: 56

 8752 22:59:38.218194                           [Byte1]: 56

 8753 22:59:38.222409  

 8754 22:59:38.222834  Set Vref, RX VrefLevel [Byte0]: 57

 8755 22:59:38.225997                           [Byte1]: 57

 8756 22:59:38.229979  

 8757 22:59:38.230547  Set Vref, RX VrefLevel [Byte0]: 58

 8758 22:59:38.233636                           [Byte1]: 58

 8759 22:59:38.237541  

 8760 22:59:38.238109  Set Vref, RX VrefLevel [Byte0]: 59

 8761 22:59:38.241326                           [Byte1]: 59

 8762 22:59:38.245675  

 8763 22:59:38.246103  Set Vref, RX VrefLevel [Byte0]: 60

 8764 22:59:38.248628                           [Byte1]: 60

 8765 22:59:38.253291  

 8766 22:59:38.253714  Set Vref, RX VrefLevel [Byte0]: 61

 8767 22:59:38.256274                           [Byte1]: 61

 8768 22:59:38.260633  

 8769 22:59:38.261050  Set Vref, RX VrefLevel [Byte0]: 62

 8770 22:59:38.263647                           [Byte1]: 62

 8771 22:59:38.268160  

 8772 22:59:38.268677  Set Vref, RX VrefLevel [Byte0]: 63

 8773 22:59:38.271881                           [Byte1]: 63

 8774 22:59:38.276269  

 8775 22:59:38.276735  Set Vref, RX VrefLevel [Byte0]: 64

 8776 22:59:38.279289                           [Byte1]: 64

 8777 22:59:38.283466  

 8778 22:59:38.284057  Set Vref, RX VrefLevel [Byte0]: 65

 8779 22:59:38.286930                           [Byte1]: 65

 8780 22:59:38.291260  

 8781 22:59:38.291686  Set Vref, RX VrefLevel [Byte0]: 66

 8782 22:59:38.294897                           [Byte1]: 66

 8783 22:59:38.298636  

 8784 22:59:38.299081  Set Vref, RX VrefLevel [Byte0]: 67

 8785 22:59:38.302154                           [Byte1]: 67

 8786 22:59:38.306526  

 8787 22:59:38.307063  Set Vref, RX VrefLevel [Byte0]: 68

 8788 22:59:38.309756                           [Byte1]: 68

 8789 22:59:38.314125  

 8790 22:59:38.314735  Set Vref, RX VrefLevel [Byte0]: 69

 8791 22:59:38.317527                           [Byte1]: 69

 8792 22:59:38.321512  

 8793 22:59:38.322100  Set Vref, RX VrefLevel [Byte0]: 70

 8794 22:59:38.324913                           [Byte1]: 70

 8795 22:59:38.328932  

 8796 22:59:38.329348  Set Vref, RX VrefLevel [Byte0]: 71

 8797 22:59:38.332506                           [Byte1]: 71

 8798 22:59:38.337104  

 8799 22:59:38.337519  Set Vref, RX VrefLevel [Byte0]: 72

 8800 22:59:38.340047                           [Byte1]: 72

 8801 22:59:38.344338  

 8802 22:59:38.344902  Set Vref, RX VrefLevel [Byte0]: 73

 8803 22:59:38.347966                           [Byte1]: 73

 8804 22:59:38.352255  

 8805 22:59:38.352697  Final RX Vref Byte 0 = 53 to rank0

 8806 22:59:38.355149  Final RX Vref Byte 1 = 58 to rank0

 8807 22:59:38.358665  Final RX Vref Byte 0 = 53 to rank1

 8808 22:59:38.361828  Final RX Vref Byte 1 = 58 to rank1==

 8809 22:59:38.365001  Dram Type= 6, Freq= 0, CH_1, rank 0

 8810 22:59:38.371797  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8811 22:59:38.372219  ==

 8812 22:59:38.372596  DQS Delay:

 8813 22:59:38.374906  DQS0 = 0, DQS1 = 0

 8814 22:59:38.375322  DQM Delay:

 8815 22:59:38.375648  DQM0 = 133, DQM1 = 127

 8816 22:59:38.378752  DQ Delay:

 8817 22:59:38.381839  DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130

 8818 22:59:38.385421  DQ4 =130, DQ5 =146, DQ6 =142, DQ7 =128

 8819 22:59:38.388172  DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =116

 8820 22:59:38.391683  DQ12 =136, DQ13 =136, DQ14 =136, DQ15 =138

 8821 22:59:38.392254  

 8822 22:59:38.392664  

 8823 22:59:38.392984  

 8824 22:59:38.395055  [DramC_TX_OE_Calibration] TA2

 8825 22:59:38.398292  Original DQ_B0 (3 6) =30, OEN = 27

 8826 22:59:38.401440  Original DQ_B1 (3 6) =30, OEN = 27

 8827 22:59:38.405140  24, 0x0, End_B0=24 End_B1=24

 8828 22:59:38.408199  25, 0x0, End_B0=25 End_B1=25

 8829 22:59:38.408666  26, 0x0, End_B0=26 End_B1=26

 8830 22:59:38.411304  27, 0x0, End_B0=27 End_B1=27

 8831 22:59:38.415005  28, 0x0, End_B0=28 End_B1=28

 8832 22:59:38.417976  29, 0x0, End_B0=29 End_B1=29

 8833 22:59:38.418447  30, 0x0, End_B0=30 End_B1=30

 8834 22:59:38.421371  31, 0x4141, End_B0=30 End_B1=30

 8835 22:59:38.424900  Byte0 end_step=30  best_step=27

 8836 22:59:38.427823  Byte1 end_step=30  best_step=27

 8837 22:59:38.431422  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8838 22:59:38.434949  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8839 22:59:38.435372  

 8840 22:59:38.435706  

 8841 22:59:38.441460  [DQSOSCAuto] RK0, (LSB)MR18= 0x1b11, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps

 8842 22:59:38.444384  CH1 RK0: MR19=303, MR18=1B11

 8843 22:59:38.450845  CH1_RK0: MR19=0x303, MR18=0x1B11, DQSOSC=396, MR23=63, INC=23, DEC=15

 8844 22:59:38.451272  

 8845 22:59:38.454787  ----->DramcWriteLeveling(PI) begin...

 8846 22:59:38.455312  ==

 8847 22:59:38.457836  Dram Type= 6, Freq= 0, CH_1, rank 1

 8848 22:59:38.461047  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8849 22:59:38.461543  ==

 8850 22:59:38.464193  Write leveling (Byte 0): 22 => 22

 8851 22:59:38.467901  Write leveling (Byte 1): 26 => 26

 8852 22:59:38.470984  DramcWriteLeveling(PI) end<-----

 8853 22:59:38.471636  

 8854 22:59:38.471985  ==

 8855 22:59:38.474122  Dram Type= 6, Freq= 0, CH_1, rank 1

 8856 22:59:38.477754  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8857 22:59:38.480582  ==

 8858 22:59:38.481018  [Gating] SW mode calibration

 8859 22:59:38.490408  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8860 22:59:38.493443  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8861 22:59:38.499925   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8862 22:59:38.503729   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8863 22:59:38.506935   1  4  8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)

 8864 22:59:38.512989   1  4 12 | B1->B0 | 3434 2323 | 1 0 | (0 0) (0 0)

 8865 22:59:38.516863   1  4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8866 22:59:38.519846   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8867 22:59:38.526721   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8868 22:59:38.529632   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8869 22:59:38.533150   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8870 22:59:38.539756   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8871 22:59:38.542700   1  5  8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)

 8872 22:59:38.546003   1  5 12 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 0)

 8873 22:59:38.552682   1  5 16 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 0)

 8874 22:59:38.556186   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8875 22:59:38.559165   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8876 22:59:38.565835   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8877 22:59:38.569583   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8878 22:59:38.572627   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8879 22:59:38.579367   1  6  8 | B1->B0 | 302f 2323 | 1 0 | (0 0) (0 0)

 8880 22:59:38.582478   1  6 12 | B1->B0 | 4646 2626 | 0 0 | (0 0) (0 0)

 8881 22:59:38.586225   1  6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8882 22:59:38.592335   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8883 22:59:38.596164   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8884 22:59:38.599186   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8885 22:59:38.602149   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8886 22:59:38.609062   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8887 22:59:38.612022   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8888 22:59:38.615704   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8889 22:59:38.622117   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 8890 22:59:38.625696   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8891 22:59:38.628802   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8892 22:59:38.635187   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8893 22:59:38.638676   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8894 22:59:38.642400   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8895 22:59:38.648844   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8896 22:59:38.651450   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8897 22:59:38.658486   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8898 22:59:38.661447   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8899 22:59:38.665224   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8900 22:59:38.671885   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8901 22:59:38.674731   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8902 22:59:38.677746   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8903 22:59:38.684429   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8904 22:59:38.687519   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8905 22:59:38.691151   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 8906 22:59:38.694358  Total UI for P1: 0, mck2ui 16

 8907 22:59:38.697300  best dqsien dly found for B1: ( 1,  9, 10)

 8908 22:59:38.704027   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8909 22:59:38.704456  Total UI for P1: 0, mck2ui 16

 8910 22:59:38.710693  best dqsien dly found for B0: ( 1,  9, 12)

 8911 22:59:38.713810  best DQS0 dly(MCK, UI, PI) = (1, 9, 12)

 8912 22:59:38.717610  best DQS1 dly(MCK, UI, PI) = (1, 9, 10)

 8913 22:59:38.718080  

 8914 22:59:38.720598  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)

 8915 22:59:38.723847  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)

 8916 22:59:38.727765  [Gating] SW calibration Done

 8917 22:59:38.728304  ==

 8918 22:59:38.730628  Dram Type= 6, Freq= 0, CH_1, rank 1

 8919 22:59:38.733602  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8920 22:59:38.734051  ==

 8921 22:59:38.737155  RX Vref Scan: 0

 8922 22:59:38.737700  

 8923 22:59:38.738176  RX Vref 0 -> 0, step: 1

 8924 22:59:38.738720  

 8925 22:59:38.740636  RX Delay 0 -> 252, step: 8

 8926 22:59:38.743609  iDelay=208, Bit 0, Center 143 (88 ~ 199) 112

 8927 22:59:38.750212  iDelay=208, Bit 1, Center 131 (72 ~ 191) 120

 8928 22:59:38.753893  iDelay=208, Bit 2, Center 123 (64 ~ 183) 120

 8929 22:59:38.756946  iDelay=208, Bit 3, Center 135 (80 ~ 191) 112

 8930 22:59:38.760271  iDelay=208, Bit 4, Center 131 (72 ~ 191) 120

 8931 22:59:38.763896  iDelay=208, Bit 5, Center 147 (88 ~ 207) 120

 8932 22:59:38.769931  iDelay=208, Bit 6, Center 147 (88 ~ 207) 120

 8933 22:59:38.773610  iDelay=208, Bit 7, Center 135 (80 ~ 191) 112

 8934 22:59:38.776600  iDelay=208, Bit 8, Center 115 (56 ~ 175) 120

 8935 22:59:38.780334  iDelay=208, Bit 9, Center 115 (56 ~ 175) 120

 8936 22:59:38.786603  iDelay=208, Bit 10, Center 131 (72 ~ 191) 120

 8937 22:59:38.790203  iDelay=208, Bit 11, Center 119 (64 ~ 175) 112

 8938 22:59:38.793243  iDelay=208, Bit 12, Center 139 (80 ~ 199) 120

 8939 22:59:38.796297  iDelay=208, Bit 13, Center 139 (80 ~ 199) 120

 8940 22:59:38.799932  iDelay=208, Bit 14, Center 131 (72 ~ 191) 120

 8941 22:59:38.806354  iDelay=208, Bit 15, Center 139 (80 ~ 199) 120

 8942 22:59:38.806921  ==

 8943 22:59:38.809916  Dram Type= 6, Freq= 0, CH_1, rank 1

 8944 22:59:38.812815  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8945 22:59:38.813327  ==

 8946 22:59:38.813709  DQS Delay:

 8947 22:59:38.815906  DQS0 = 0, DQS1 = 0

 8948 22:59:38.816435  DQM Delay:

 8949 22:59:38.819384  DQM0 = 136, DQM1 = 128

 8950 22:59:38.819789  DQ Delay:

 8951 22:59:38.822505  DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135

 8952 22:59:38.826208  DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135

 8953 22:59:38.829367  DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119

 8954 22:59:38.832501  DQ12 =139, DQ13 =139, DQ14 =131, DQ15 =139

 8955 22:59:38.836137  

 8956 22:59:38.836776  

 8957 22:59:38.837192  ==

 8958 22:59:38.839634  Dram Type= 6, Freq= 0, CH_1, rank 1

 8959 22:59:38.842670  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8960 22:59:38.843316  ==

 8961 22:59:38.843796  

 8962 22:59:38.844196  

 8963 22:59:38.846006  	TX Vref Scan disable

 8964 22:59:38.846562   == TX Byte 0 ==

 8965 22:59:38.852369  Update DQ  dly =979 (3 ,6, 19)  DQ  OEN =(3 ,3)

 8966 22:59:38.856055  Update DQM dly =979 (3 ,6, 19)  DQM OEN =(3 ,3)

 8967 22:59:38.856624   == TX Byte 1 ==

 8968 22:59:38.862535  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 8969 22:59:38.866039  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8970 22:59:38.866511  ==

 8971 22:59:38.869158  Dram Type= 6, Freq= 0, CH_1, rank 1

 8972 22:59:38.872015  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8973 22:59:38.872654  ==

 8974 22:59:38.887613  

 8975 22:59:38.890670  TX Vref early break, caculate TX vref

 8976 22:59:38.893693  TX Vref=16, minBit 0, minWin=22, winSum=381

 8977 22:59:38.896876  TX Vref=18, minBit 0, minWin=22, winSum=391

 8978 22:59:38.900504  TX Vref=20, minBit 5, minWin=23, winSum=395

 8979 22:59:38.903578  TX Vref=22, minBit 5, minWin=23, winSum=405

 8980 22:59:38.907319  TX Vref=24, minBit 0, minWin=23, winSum=413

 8981 22:59:38.913852  TX Vref=26, minBit 0, minWin=24, winSum=418

 8982 22:59:38.916783  TX Vref=28, minBit 0, minWin=23, winSum=415

 8983 22:59:38.920555  TX Vref=30, minBit 0, minWin=23, winSum=411

 8984 22:59:38.923501  TX Vref=32, minBit 0, minWin=23, winSum=406

 8985 22:59:38.926651  TX Vref=34, minBit 0, minWin=21, winSum=398

 8986 22:59:38.930326  TX Vref=36, minBit 0, minWin=21, winSum=381

 8987 22:59:38.936638  [TxChooseVref] Worse bit 0, Min win 24, Win sum 418, Final Vref 26

 8988 22:59:38.937188  

 8989 22:59:38.940288  Final TX Range 0 Vref 26

 8990 22:59:38.940851  

 8991 22:59:38.941250  ==

 8992 22:59:38.943227  Dram Type= 6, Freq= 0, CH_1, rank 1

 8993 22:59:38.946805  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8994 22:59:38.947464  ==

 8995 22:59:38.949728  

 8996 22:59:38.950278  

 8997 22:59:38.950779  	TX Vref Scan disable

 8998 22:59:38.956467  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps

 8999 22:59:38.956987   == TX Byte 0 ==

 9000 22:59:38.959920  u2DelayCellOfst[0]=14 cells (4 PI)

 9001 22:59:38.963546  u2DelayCellOfst[1]=11 cells (3 PI)

 9002 22:59:38.966544  u2DelayCellOfst[2]=0 cells (0 PI)

 9003 22:59:38.969569  u2DelayCellOfst[3]=3 cells (1 PI)

 9004 22:59:38.973037  u2DelayCellOfst[4]=3 cells (1 PI)

 9005 22:59:38.976671  u2DelayCellOfst[5]=18 cells (5 PI)

 9006 22:59:38.979848  u2DelayCellOfst[6]=18 cells (5 PI)

 9007 22:59:38.982894  u2DelayCellOfst[7]=3 cells (1 PI)

 9008 22:59:38.986041  Update DQ  dly =977 (3 ,6, 17)  DQ  OEN =(3 ,3)

 9009 22:59:38.989567  Update DQM dly =979 (3 ,6, 19)  DQM OEN =(3 ,3)

 9010 22:59:38.992954   == TX Byte 1 ==

 9011 22:59:38.995956  u2DelayCellOfst[8]=0 cells (0 PI)

 9012 22:59:38.999147  u2DelayCellOfst[9]=7 cells (2 PI)

 9013 22:59:39.002796  u2DelayCellOfst[10]=11 cells (3 PI)

 9014 22:59:39.005948  u2DelayCellOfst[11]=7 cells (2 PI)

 9015 22:59:39.009000  u2DelayCellOfst[12]=14 cells (4 PI)

 9016 22:59:39.012642  u2DelayCellOfst[13]=18 cells (5 PI)

 9017 22:59:39.015689  u2DelayCellOfst[14]=18 cells (5 PI)

 9018 22:59:39.016115  u2DelayCellOfst[15]=18 cells (5 PI)

 9019 22:59:39.022473  Update DQ  dly =978 (3 ,6, 18)  DQ  OEN =(3 ,3)

 9020 22:59:39.025435  Update DQM dly =980 (3 ,6, 20)  DQM OEN =(3 ,3)

 9021 22:59:39.029183  DramC Write-DBI on

 9022 22:59:39.029611  ==

 9023 22:59:39.032051  Dram Type= 6, Freq= 0, CH_1, rank 1

 9024 22:59:39.036018  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 9025 22:59:39.036449  ==

 9026 22:59:39.036841  

 9027 22:59:39.037159  

 9028 22:59:39.039072  	TX Vref Scan disable

 9029 22:59:39.039503   == TX Byte 0 ==

 9030 22:59:39.045384  Update DQM dly =720 (2 ,6, 16)  DQM OEN =(3 ,3)

 9031 22:59:39.045815   == TX Byte 1 ==

 9032 22:59:39.048983  Update DQM dly =721 (2 ,6, 17)  DQM OEN =(3 ,3)

 9033 22:59:39.052011  DramC Write-DBI off

 9034 22:59:39.052438  

 9035 22:59:39.052841  [DATLAT]

 9036 22:59:39.055524  Freq=1600, CH1 RK1

 9037 22:59:39.055952  

 9038 22:59:39.056319  DATLAT Default: 0xf

 9039 22:59:39.058763  0, 0xFFFF, sum = 0

 9040 22:59:39.061881  1, 0xFFFF, sum = 0

 9041 22:59:39.062328  2, 0xFFFF, sum = 0

 9042 22:59:39.065324  3, 0xFFFF, sum = 0

 9043 22:59:39.065757  4, 0xFFFF, sum = 0

 9044 22:59:39.068276  5, 0xFFFF, sum = 0

 9045 22:59:39.068796  6, 0xFFFF, sum = 0

 9046 22:59:39.072045  7, 0xFFFF, sum = 0

 9047 22:59:39.072475  8, 0xFFFF, sum = 0

 9048 22:59:39.075121  9, 0xFFFF, sum = 0

 9049 22:59:39.075552  10, 0xFFFF, sum = 0

 9050 22:59:39.078642  11, 0xFFFF, sum = 0

 9051 22:59:39.079186  12, 0xFFFF, sum = 0

 9052 22:59:39.081620  13, 0xFFFF, sum = 0

 9053 22:59:39.082056  14, 0x0, sum = 1

 9054 22:59:39.085293  15, 0x0, sum = 2

 9055 22:59:39.085722  16, 0x0, sum = 3

 9056 22:59:39.088871  17, 0x0, sum = 4

 9057 22:59:39.089306  best_step = 15

 9058 22:59:39.089706  

 9059 22:59:39.090056  ==

 9060 22:59:39.092020  Dram Type= 6, Freq= 0, CH_1, rank 1

 9061 22:59:39.095630  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 9062 22:59:39.098671  ==

 9063 22:59:39.099096  RX Vref Scan: 0

 9064 22:59:39.099433  

 9065 22:59:39.101712  RX Vref 0 -> 0, step: 1

 9066 22:59:39.102131  

 9067 22:59:39.105343  RX Delay 11 -> 252, step: 4

 9068 22:59:39.108568  iDelay=203, Bit 0, Center 140 (87 ~ 194) 108

 9069 22:59:39.111698  iDelay=203, Bit 1, Center 128 (75 ~ 182) 108

 9070 22:59:39.114715  iDelay=203, Bit 2, Center 122 (67 ~ 178) 112

 9071 22:59:39.121322  iDelay=203, Bit 3, Center 130 (79 ~ 182) 104

 9072 22:59:39.125032  iDelay=203, Bit 4, Center 132 (75 ~ 190) 116

 9073 22:59:39.128209  iDelay=203, Bit 5, Center 144 (91 ~ 198) 108

 9074 22:59:39.131262  iDelay=203, Bit 6, Center 146 (91 ~ 202) 112

 9075 22:59:39.135094  iDelay=203, Bit 7, Center 130 (79 ~ 182) 104

 9076 22:59:39.141257  iDelay=203, Bit 8, Center 112 (55 ~ 170) 116

 9077 22:59:39.144360  iDelay=203, Bit 9, Center 116 (63 ~ 170) 108

 9078 22:59:39.148054  iDelay=203, Bit 10, Center 126 (71 ~ 182) 112

 9079 22:59:39.151272  iDelay=203, Bit 11, Center 118 (67 ~ 170) 104

 9080 22:59:39.157852  iDelay=203, Bit 12, Center 134 (79 ~ 190) 112

 9081 22:59:39.161365  iDelay=203, Bit 13, Center 136 (83 ~ 190) 108

 9082 22:59:39.164880  iDelay=203, Bit 14, Center 134 (79 ~ 190) 112

 9083 22:59:39.168033  iDelay=203, Bit 15, Center 138 (83 ~ 194) 112

 9084 22:59:39.168457  ==

 9085 22:59:39.171300  Dram Type= 6, Freq= 0, CH_1, rank 1

 9086 22:59:39.174780  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 9087 22:59:39.178402  ==

 9088 22:59:39.178932  DQS Delay:

 9089 22:59:39.179272  DQS0 = 0, DQS1 = 0

 9090 22:59:39.181012  DQM Delay:

 9091 22:59:39.181435  DQM0 = 134, DQM1 = 126

 9092 22:59:39.184565  DQ Delay:

 9093 22:59:39.187692  DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130

 9094 22:59:39.191344  DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130

 9095 22:59:39.194270  DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =118

 9096 22:59:39.197864  DQ12 =134, DQ13 =136, DQ14 =134, DQ15 =138

 9097 22:59:39.198390  

 9098 22:59:39.198725  

 9099 22:59:39.199036  

 9100 22:59:39.200791  [DramC_TX_OE_Calibration] TA2

 9101 22:59:39.204349  Original DQ_B0 (3 6) =30, OEN = 27

 9102 22:59:39.207484  Original DQ_B1 (3 6) =30, OEN = 27

 9103 22:59:39.210681  24, 0x0, End_B0=24 End_B1=24

 9104 22:59:39.211112  25, 0x0, End_B0=25 End_B1=25

 9105 22:59:39.214467  26, 0x0, End_B0=26 End_B1=26

 9106 22:59:39.217466  27, 0x0, End_B0=27 End_B1=27

 9107 22:59:39.220479  28, 0x0, End_B0=28 End_B1=28

 9108 22:59:39.220947  29, 0x0, End_B0=29 End_B1=29

 9109 22:59:39.224251  30, 0x0, End_B0=30 End_B1=30

 9110 22:59:39.227221  31, 0x5151, End_B0=30 End_B1=30

 9111 22:59:39.231132  Byte0 end_step=30  best_step=27

 9112 22:59:39.233867  Byte1 end_step=30  best_step=27

 9113 22:59:39.237913  Byte0 TX OE(2T, 0.5T) = (3, 3)

 9114 22:59:39.240794  Byte1 TX OE(2T, 0.5T) = (3, 3)

 9115 22:59:39.241220  

 9116 22:59:39.241574  

 9117 22:59:39.247354  [DQSOSCAuto] RK1, (LSB)MR18= 0xd08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps

 9118 22:59:39.250440  CH1 RK1: MR19=303, MR18=D08

 9119 22:59:39.257192  CH1_RK1: MR19=0x303, MR18=0xD08, DQSOSC=403, MR23=63, INC=22, DEC=15

 9120 22:59:39.260262  [RxdqsGatingPostProcess] freq 1600

 9121 22:59:39.263508  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 9122 22:59:39.267111  best DQS0 dly(2T, 0.5T) = (1, 1)

 9123 22:59:39.270274  best DQS1 dly(2T, 0.5T) = (1, 1)

 9124 22:59:39.273807  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 9125 22:59:39.277208  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 9126 22:59:39.280344  best DQS0 dly(2T, 0.5T) = (1, 1)

 9127 22:59:39.283249  best DQS1 dly(2T, 0.5T) = (1, 1)

 9128 22:59:39.286630  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 9129 22:59:39.290288  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 9130 22:59:39.293212  Pre-setting of DQS Precalculation

 9131 22:59:39.296926  [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15

 9132 22:59:39.303042  sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0

 9133 22:59:39.313401  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 9134 22:59:39.313833  

 9135 22:59:39.314173  

 9136 22:59:39.314487  [Calibration Summary] 3200 Mbps

 9137 22:59:39.316416  CH 0, Rank 0

 9138 22:59:39.320158  SW Impedance     : PASS

 9139 22:59:39.320623  DUTY Scan        : NO K

 9140 22:59:39.323299  ZQ Calibration   : PASS

 9141 22:59:39.323723  Jitter Meter     : NO K

 9142 22:59:39.326417  CBT Training     : PASS

 9143 22:59:39.329518  Write leveling   : PASS

 9144 22:59:39.329945  RX DQS gating    : PASS

 9145 22:59:39.332903  RX DQ/DQS(RDDQC) : PASS

 9146 22:59:39.336088  TX DQ/DQS        : PASS

 9147 22:59:39.336541  RX DATLAT        : PASS

 9148 22:59:39.339763  RX DQ/DQS(Engine): PASS

 9149 22:59:39.342741  TX OE            : PASS

 9150 22:59:39.343171  All Pass.

 9151 22:59:39.343508  

 9152 22:59:39.343823  CH 0, Rank 1

 9153 22:59:39.346486  SW Impedance     : PASS

 9154 22:59:39.349644  DUTY Scan        : NO K

 9155 22:59:39.350072  ZQ Calibration   : PASS

 9156 22:59:39.353171  Jitter Meter     : NO K

 9157 22:59:39.355987  CBT Training     : PASS

 9158 22:59:39.356415  Write leveling   : PASS

 9159 22:59:39.359958  RX DQS gating    : PASS

 9160 22:59:39.362597  RX DQ/DQS(RDDQC) : PASS

 9161 22:59:39.363121  TX DQ/DQS        : PASS

 9162 22:59:39.365578  RX DATLAT        : PASS

 9163 22:59:39.369069  RX DQ/DQS(Engine): PASS

 9164 22:59:39.369674  TX OE            : PASS

 9165 22:59:39.372510  All Pass.

 9166 22:59:39.372986  

 9167 22:59:39.373321  CH 1, Rank 0

 9168 22:59:39.375934  SW Impedance     : PASS

 9169 22:59:39.376453  DUTY Scan        : NO K

 9170 22:59:39.378860  ZQ Calibration   : PASS

 9171 22:59:39.382255  Jitter Meter     : NO K

 9172 22:59:39.382877  CBT Training     : PASS

 9173 22:59:39.385237  Write leveling   : PASS

 9174 22:59:39.389001  RX DQS gating    : PASS

 9175 22:59:39.389460  RX DQ/DQS(RDDQC) : PASS

 9176 22:59:39.392400  TX DQ/DQS        : PASS

 9177 22:59:39.395571  RX DATLAT        : PASS

 9178 22:59:39.395996  RX DQ/DQS(Engine): PASS

 9179 22:59:39.398623  TX OE            : PASS

 9180 22:59:39.399085  All Pass.

 9181 22:59:39.399423  

 9182 22:59:39.402241  CH 1, Rank 1

 9183 22:59:39.402671  SW Impedance     : PASS

 9184 22:59:39.405262  DUTY Scan        : NO K

 9185 22:59:39.408418  ZQ Calibration   : PASS

 9186 22:59:39.408967  Jitter Meter     : NO K

 9187 22:59:39.411903  CBT Training     : PASS

 9188 22:59:39.412337  Write leveling   : PASS

 9189 22:59:39.415181  RX DQS gating    : PASS

 9190 22:59:39.418552  RX DQ/DQS(RDDQC) : PASS

 9191 22:59:39.419087  TX DQ/DQS        : PASS

 9192 22:59:39.421932  RX DATLAT        : PASS

 9193 22:59:39.425055  RX DQ/DQS(Engine): PASS

 9194 22:59:39.425481  TX OE            : PASS

 9195 22:59:39.428623  All Pass.

 9196 22:59:39.429048  

 9197 22:59:39.429387  DramC Write-DBI on

 9198 22:59:39.431842  	PER_BANK_REFRESH: Hybrid Mode

 9199 22:59:39.434903  TX_TRACKING: ON

 9200 22:59:39.441218  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0

 9201 22:59:39.451299  sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1

 9202 22:59:39.458131  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 9203 22:59:39.461215  [FAST_K] Save calibration result to emmc

 9204 22:59:39.464284  sync common calibartion params.

 9205 22:59:39.464852  sync cbt_mode0:1, 1:1

 9206 22:59:39.467953  dram_init: ddr_geometry: 2

 9207 22:59:39.470822  dram_init: ddr_geometry: 2

 9208 22:59:39.474451  dram_init: ddr_geometry: 2

 9209 22:59:39.474875  0:dram_rank_size:100000000

 9210 22:59:39.477896  1:dram_rank_size:100000000

 9211 22:59:39.484157  sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000

 9212 22:59:39.484680  DFS_SHUFFLE_HW_MODE: ON

 9213 22:59:39.490776  dramc_set_vcore_voltage set vcore to 725000

 9214 22:59:39.491233  Read voltage for 1600, 0

 9215 22:59:39.493799  Vio18 = 0

 9216 22:59:39.494222  Vcore = 725000

 9217 22:59:39.494556  Vdram = 0

 9218 22:59:39.497205  Vddq = 0

 9219 22:59:39.497627  Vmddr = 0

 9220 22:59:39.500325  switch to 3200 Mbps bootup

 9221 22:59:39.500792  [DramcRunTimeConfig]

 9222 22:59:39.501133  PHYPLL

 9223 22:59:39.503876  DPM_CONTROL_AFTERK: ON

 9224 22:59:39.507329  PER_BANK_REFRESH: ON

 9225 22:59:39.507755  REFRESH_OVERHEAD_REDUCTION: ON

 9226 22:59:39.510249  CMD_PICG_NEW_MODE: OFF

 9227 22:59:39.513476  XRTWTW_NEW_MODE: ON

 9228 22:59:39.513922  XRTRTR_NEW_MODE: ON

 9229 22:59:39.517041  TX_TRACKING: ON

 9230 22:59:39.517462  RDSEL_TRACKING: OFF

 9231 22:59:39.520237  DQS Precalculation for DVFS: ON

 9232 22:59:39.523642  RX_TRACKING: OFF

 9233 22:59:39.524193  HW_GATING DBG: ON

 9234 22:59:39.526965  ZQCS_ENABLE_LP4: ON

 9235 22:59:39.527382  RX_PICG_NEW_MODE: ON

 9236 22:59:39.530130  TX_PICG_NEW_MODE: ON

 9237 22:59:39.530573  ENABLE_RX_DCM_DPHY: ON

 9238 22:59:39.533817  LOWPOWER_GOLDEN_SETTINGS(DCM): ON

 9239 22:59:39.536868  DUMMY_READ_FOR_TRACKING: OFF

 9240 22:59:39.540610  !!! SPM_CONTROL_AFTERK: OFF

 9241 22:59:39.543457  !!! SPM could not control APHY

 9242 22:59:39.543914  IMPEDANCE_TRACKING: ON

 9243 22:59:39.547081  TEMP_SENSOR: ON

 9244 22:59:39.547500  HW_SAVE_FOR_SR: OFF

 9245 22:59:39.550109  CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF

 9246 22:59:39.553165  PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF

 9247 22:59:39.556471  Read ODT Tracking: ON

 9248 22:59:39.560127  Refresh Rate DeBounce: ON

 9249 22:59:39.560580  DFS_NO_QUEUE_FLUSH: ON

 9250 22:59:39.563250  DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF

 9251 22:59:39.566831  ENABLE_DFS_RUNTIME_MRW: OFF

 9252 22:59:39.569912  DDR_RESERVE_NEW_MODE: ON

 9253 22:59:39.570330  MR_CBT_SWITCH_FREQ: ON

 9254 22:59:39.572762  =========================

 9255 22:59:39.592411  [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)

 9256 22:59:39.595328  dram_init: ddr_geometry: 2

 9257 22:59:39.613203  [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)

 9258 22:59:39.616850  dram_init: dram init end (result: 0)

 9259 22:59:39.623282  DRAM-K: Full calibration passed in 24621 msecs

 9260 22:59:39.626429  MRC: failed to locate region type 0.

 9261 22:59:39.626853  DRAM rank0 size:0x100000000,

 9262 22:59:39.630110  DRAM rank1 size=0x100000000

 9263 22:59:39.639973  Mapping address range [0x40000000:0x240000000) as     cacheable | read-write | non-secure | normal

 9264 22:59:39.646588  Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal

 9265 22:59:39.652968  Backing address range [0x40000000:0x80000000) with new page table @0x00112000

 9266 22:59:39.662688  Backing address range [0x40000000:0x40200000) with new page table @0x00113000

 9267 22:59:39.663110  DRAM rank0 size:0x100000000,

 9268 22:59:39.666377  DRAM rank1 size=0x100000000

 9269 22:59:39.666796  CBMEM:

 9270 22:59:39.669524  IMD: root @ 0xfffff000 254 entries.

 9271 22:59:39.672451  IMD: root @ 0xffffec00 62 entries.

 9272 22:59:39.676267  FMAP: area RO_VPD found @ 3f8000 (32768 bytes)

 9273 22:59:39.682323  WARNING: RO_VPD is uninitialized or empty.

 9274 22:59:39.686102  FMAP: area RW_VPD found @ 577000 (16384 bytes)

 9275 22:59:39.693544  CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80

 9276 22:59:39.705971  read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps

 9277 22:59:39.718022  BS: romstage times (exec / console): total (unknown) / 24116 ms

 9278 22:59:39.718615  

 9279 22:59:39.718961  

 9280 22:59:39.727638  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...

 9281 22:59:39.730831  ARM64: Exception handlers installed.

 9282 22:59:39.733728  ARM64: Testing exception

 9283 22:59:39.737516  ARM64: Done test exception

 9284 22:59:39.737955  Enumerating buses...

 9285 22:59:39.740672  Show all devs... Before device enumeration.

 9286 22:59:39.743874  Root Device: enabled 1

 9287 22:59:39.747514  CPU_CLUSTER: 0: enabled 1

 9288 22:59:39.747959  CPU: 00: enabled 1

 9289 22:59:39.750555  Compare with tree...

 9290 22:59:39.751015  Root Device: enabled 1

 9291 22:59:39.754140   CPU_CLUSTER: 0: enabled 1

 9292 22:59:39.757400    CPU: 00: enabled 1

 9293 22:59:39.757939  Root Device scanning...

 9294 22:59:39.760724  scan_static_bus for Root Device

 9295 22:59:39.763990  CPU_CLUSTER: 0 enabled

 9296 22:59:39.767357  scan_static_bus for Root Device done

 9297 22:59:39.770135  scan_bus: bus Root Device finished in 8 msecs

 9298 22:59:39.770623  done

 9299 22:59:39.776951  BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms

 9300 22:59:39.780684  FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)

 9301 22:59:39.786496  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

 9302 22:59:39.793096  BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms

 9303 22:59:39.793568  Allocating resources...

 9304 22:59:39.796671  Reading resources...

 9305 22:59:39.800077  Root Device read_resources bus 0 link: 0

 9306 22:59:39.803000  DRAM rank0 size:0x100000000,

 9307 22:59:39.803441  DRAM rank1 size=0x100000000

 9308 22:59:39.809455  CPU_CLUSTER: 0 read_resources bus 0 link: 0

 9309 22:59:39.810023  CPU: 00 missing read_resources

 9310 22:59:39.816513  CPU_CLUSTER: 0 read_resources bus 0 link: 0 done

 9311 22:59:39.819660  Root Device read_resources bus 0 link: 0 done

 9312 22:59:39.822701  Done reading resources.

 9313 22:59:39.826216  Show resources in subtree (Root Device)...After reading.

 9314 22:59:39.829638   Root Device child on link 0 CPU_CLUSTER: 0

 9315 22:59:39.832493    CPU_CLUSTER: 0 child on link 0 CPU: 00

 9316 22:59:39.842564    CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0

 9317 22:59:39.842994     CPU: 00

 9318 22:59:39.849224  Root Device assign_resources, bus 0 link: 0

 9319 22:59:39.852579  CPU_CLUSTER: 0 missing set_resources

 9320 22:59:39.856387  Root Device assign_resources, bus 0 link: 0 done

 9321 22:59:39.859104  Done setting resources.

 9322 22:59:39.862834  Show resources in subtree (Root Device)...After assigning values.

 9323 22:59:39.865820   Root Device child on link 0 CPU_CLUSTER: 0

 9324 22:59:39.872432    CPU_CLUSTER: 0 child on link 0 CPU: 00

 9325 22:59:39.879154    CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0

 9326 22:59:39.882656     CPU: 00

 9327 22:59:39.883167  Done allocating resources.

 9328 22:59:39.888767  BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms

 9329 22:59:39.889207  Enabling resources...

 9330 22:59:39.892277  done.

 9331 22:59:39.895464  BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms

 9332 22:59:39.898713  Initializing devices...

 9333 22:59:39.899136  Root Device init

 9334 22:59:39.901842  init hardware done!

 9335 22:59:39.902266  0x00000018: ctrlr->caps

 9336 22:59:39.905279  52.000 MHz: ctrlr->f_max

 9337 22:59:39.908731  0.400 MHz: ctrlr->f_min

 9338 22:59:39.911793  0x40ff8080: ctrlr->voltages

 9339 22:59:39.912243  sclk: 390625

 9340 22:59:39.912623  Bus Width = 1

 9341 22:59:39.914986  sclk: 390625

 9342 22:59:39.915506  Bus Width = 1

 9343 22:59:39.918475  Early init status = 3

 9344 22:59:39.921968  out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00 

 9345 22:59:39.924990  in-header: 03 fc 00 00 01 00 00 00 

 9346 22:59:39.928871  in-data: 00 

 9347 22:59:39.932070  out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01 

 9348 22:59:39.936318  in-header: 03 fd 00 00 00 00 00 00 

 9349 22:59:39.939770  in-data: 

 9350 22:59:39.942840  out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00 

 9351 22:59:39.947140  in-header: 03 fc 00 00 01 00 00 00 

 9352 22:59:39.950250  in-data: 00 

 9353 22:59:39.953503  out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01 

 9354 22:59:39.959404  in-header: 03 fd 00 00 00 00 00 00 

 9355 22:59:39.962407  in-data: 

 9356 22:59:39.965503  [SSUSB] Setting up USB HOST controller...

 9357 22:59:39.968735  [SSUSB] u3phy_ports_enable u2p:1, u3p:1

 9358 22:59:39.971912  [SSUSB] phy power-on done.

 9359 22:59:39.975359  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

 9360 22:59:39.981991  CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c

 9361 22:59:39.984971  mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)

 9362 22:59:39.991715  CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c

 9363 22:59:39.998405  read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps

 9364 22:59:40.004852  mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)

 9365 22:59:40.011539  CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204

 9366 22:59:40.018334  read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps

 9367 22:59:40.021168  SPM: binary array size = 0x9dc

 9368 22:59:40.028135  SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)

 9369 22:59:40.031080  spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18

 9370 22:59:40.037715  mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)

 9371 22:59:40.044121  SPM: spm_init done in 34 msecs, spm pc = 0x3f4

 9372 22:59:40.047179  configure_display: Starting display init

 9373 22:59:40.082052  anx7625_power_on_init: Init interface.

 9374 22:59:40.085530  anx7625_disable_pd_protocol: Disabled PD feature.

 9375 22:59:40.088835  anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.

 9376 22:59:40.116363  anx7625_start_dp_work: Secure OCM version=00

 9377 22:59:40.119752  anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91

 9378 22:59:40.134674  sp_tx_get_edid_block: EDID Block = 1

 9379 22:59:40.237217  Extracted contents:

 9380 22:59:40.241029  header:          00 ff ff ff ff ff ff 00

 9381 22:59:40.243494  serial number:   26 cf 7d 05 00 00 00 00 00 1e

 9382 22:59:40.247207  version:         01 04

 9383 22:59:40.250264  basic params:    95 1f 11 78 0a

 9384 22:59:40.253783  chroma info:     76 90 94 55 54 90 27 21 50 54

 9385 22:59:40.256998  established:     00 00 00

 9386 22:59:40.263841  standard:        01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01

 9387 22:59:40.270510  descriptor 1:    38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19

 9388 22:59:40.273585  descriptor 2:    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

 9389 22:59:40.280253  descriptor 3:    00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20

 9390 22:59:40.286873  descriptor 4:    00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a

 9391 22:59:40.289892  extensions:      00

 9392 22:59:40.290311  checksum:        fb

 9393 22:59:40.290644  

 9394 22:59:40.296982  Manufacturer: IVO Model 57d Serial Number 0

 9395 22:59:40.297504  Made week 0 of 2020

 9396 22:59:40.300204  EDID version: 1.4

 9397 22:59:40.300781  Digital display

 9398 22:59:40.303017  6 bits per primary color channel

 9399 22:59:40.306642  DisplayPort interface

 9400 22:59:40.307068  Maximum image size: 31 cm x 17 cm

 9401 22:59:40.309662  Gamma: 220%

 9402 22:59:40.310080  Check DPMS levels

 9403 22:59:40.316356  Supported color formats: RGB 4:4:4, YCrCb 4:2:2

 9404 22:59:40.319367  First detailed timing is preferred timing

 9405 22:59:40.322710  Established timings supported:

 9406 22:59:40.323234  Standard timings supported:

 9407 22:59:40.326072  Detailed timings

 9408 22:59:40.329494  Hex of detail: 383680a07038204018303c0035ae10000019

 9409 22:59:40.336382  Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm

 9410 22:59:40.339325                 0780 0798 07c8 0820 hborder 0

 9411 22:59:40.343264                 0438 043b 0447 0458 vborder 0

 9412 22:59:40.345918                 -hsync -vsync

 9413 22:59:40.346345  Did detailed timing

 9414 22:59:40.352714  Hex of detail: 000000000000000000000000000000000000

 9415 22:59:40.355848  Manufacturer-specified data, tag 0

 9416 22:59:40.359311  Hex of detail: 000000fe00496e666f566973696f6e0a2020

 9417 22:59:40.362330  ASCII string: InfoVision

 9418 22:59:40.366000  Hex of detail: 000000fe00523134304e574635205248200a

 9419 22:59:40.368707  ASCII string: R140NWF5 RH 

 9420 22:59:40.369141  Checksum

 9421 22:59:40.372391  Checksum: 0xfb (valid)

 9422 22:59:40.375413  configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz

 9423 22:59:40.378758  DSI data_rate: 832800000 bps

 9424 22:59:40.385240  anx7625_parse_edid: detected IVO panel, use k value 0x3b

 9425 22:59:40.388985  anx7625_parse_edid: pixelclock(138800).

 9426 22:59:40.391908   hactive(1920), hsync(48), hfp(24), hbp(88)

 9427 22:59:40.395391   vactive(1080), vsync(12), vfp(3), vbp(17)

 9428 22:59:40.399150  anx7625_dsi_config: config dsi.

 9429 22:59:40.405304  anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).

 9430 22:59:40.419442  anx7625_dsi_config: success to config DSI

 9431 22:59:40.422562  anx7625_dp_start: MIPI phy setup OK.

 9432 22:59:40.425708  mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4

 9433 22:59:40.429367  mtk_ddp_mode_set invalid vrefresh 60

 9434 22:59:40.432149  main_disp_path_setup

 9435 22:59:40.432616  ovl_layer_smi_id_en

 9436 22:59:40.435707  ovl_layer_smi_id_en

 9437 22:59:40.436131  ccorr_config

 9438 22:59:40.436466  aal_config

 9439 22:59:40.439178  gamma_config

 9440 22:59:40.439679  postmask_config

 9441 22:59:40.442385  dither_config

 9442 22:59:40.445909  framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32

 9443 22:59:40.452397                     x_res x y_res: 1920 x 1080, size: 8294400 at 0x0

 9444 22:59:40.455235  Root Device init finished in 552 msecs

 9445 22:59:40.458991  CPU_CLUSTER: 0 init

 9446 22:59:40.465556  Mapping address range [0x00200000:0x00300000) as     cacheable | read-write |     secure | device

 9447 22:59:40.468646  INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff

 9448 22:59:40.471874  APU_MBOX 0x190000b0 = 0x10001

 9449 22:59:40.475569  APU_MBOX 0x190001b0 = 0x10001

 9450 22:59:40.478753  APU_MBOX 0x190005b0 = 0x10001

 9451 22:59:40.482405  APU_MBOX 0x190006b0 = 0x10001

 9452 22:59:40.485476  CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c

 9453 22:59:40.498169  read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps

 9454 22:59:40.510791  mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)

 9455 22:59:40.516959  CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0

 9456 22:59:40.528628  read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps

 9457 22:59:40.537856  mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)

 9458 22:59:40.541417  CPU_CLUSTER: 0 init finished in 81 msecs

 9459 22:59:40.544708  Devices initialized

 9460 22:59:40.547715  Show all devs... After init.

 9461 22:59:40.548118  Root Device: enabled 1

 9462 22:59:40.550970  CPU_CLUSTER: 0: enabled 1

 9463 22:59:40.554358  CPU: 00: enabled 1

 9464 22:59:40.557965  BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms

 9465 22:59:40.561505  FMAP: area RW_ELOG found @ 57f000 (4096 bytes)

 9466 22:59:40.564263  ELOG: NV offset 0x57f000 size 0x1000

 9467 22:59:40.570876  read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps

 9468 22:59:40.577306  ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024

 9469 22:59:40.581002  ELOG: Event(17) added with size 13 at 2023-06-05 22:59:40 UTC

 9470 22:59:40.586934  out: cmd=0x121: 03 db 21 01 00 00 00 00 

 9471 22:59:40.590591  in-header: 03 c5 00 00 2c 00 00 00 

 9472 22:59:40.600185  in-data: 9a 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 

 9473 22:59:40.607408  ELOG: Event(A1) added with size 10 at 2023-06-05 22:59:40 UTC

 9474 22:59:40.613585  elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b

 9475 22:59:40.620642  ELOG: Event(A0) added with size 9 at 2023-06-05 22:59:40 UTC

 9476 22:59:40.623593  elog_add_boot_reason: Logged dev mode boot

 9477 22:59:40.630189  BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms

 9478 22:59:40.630273  Finalize devices...

 9479 22:59:40.633197  Devices finalized

 9480 22:59:40.636572  BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms

 9481 22:59:40.640253  Writing coreboot table at 0xffe64000

 9482 22:59:40.643291   0. 000000000010a000-0000000000113fff: RAMSTAGE

 9483 22:59:40.650271   1. 0000000040000000-00000000400fffff: RAM

 9484 22:59:40.653343   2. 0000000040100000-000000004032afff: RAMSTAGE

 9485 22:59:40.656330   3. 000000004032b000-00000000545fffff: RAM

 9486 22:59:40.659939   4. 0000000054600000-000000005465ffff: BL31

 9487 22:59:40.662996   5. 0000000054660000-00000000ffe63fff: RAM

 9488 22:59:40.670212   6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES

 9489 22:59:40.673355   7. 0000000100000000-000000023fffffff: RAM

 9490 22:59:40.676388  Passing 5 GPIOs to payload:

 9491 22:59:40.679522              NAME |       PORT | POLARITY |     VALUE

 9492 22:59:40.686267          EC in RW | 0x000000aa |      low | undefined

 9493 22:59:40.689340      EC interrupt | 0x00000005 |      low | undefined

 9494 22:59:40.693200     TPM interrupt | 0x000000ab |     high | undefined

 9495 22:59:40.699569    SD card detect | 0x00000011 |     high | undefined

 9496 22:59:40.703101    speaker enable | 0x00000093 |     high | undefined

 9497 22:59:40.706273  out: cmd=0x6: 03 f7 06 00 00 00 00 00 

 9498 22:59:40.710506  in-header: 03 f9 00 00 02 00 00 00 

 9499 22:59:40.714302  in-data: 02 00 

 9500 22:59:40.717282  ADC[4]: Raw value=905248 ID=7

 9501 22:59:40.720494  ADC[3]: Raw value=214021 ID=1

 9502 22:59:40.720600  RAM Code: 0x71

 9503 22:59:40.724279  ADC[6]: Raw value=75036 ID=0

 9504 22:59:40.727279  ADC[5]: Raw value=213282 ID=1

 9505 22:59:40.727368  SKU Code: 0x1

 9506 22:59:40.733587  Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a129

 9507 22:59:40.733682  coreboot table: 964 bytes.

 9508 22:59:40.737254  IMD ROOT    0. 0xfffff000 0x00001000

 9509 22:59:40.740141  IMD SMALL   1. 0xffffe000 0x00001000

 9510 22:59:40.743657  RO MCACHE   2. 0xffffc000 0x00001104

 9511 22:59:40.747142  CONSOLE     3. 0xfff7c000 0x00080000

 9512 22:59:40.750143  FMAP        4. 0xfff7b000 0x00000452

 9513 22:59:40.753882  TIME STAMP  5. 0xfff7a000 0x00000910

 9514 22:59:40.757117  VBOOT WORK  6. 0xfff66000 0x00014000

 9515 22:59:40.760746  RAMOOPS     7. 0xffe66000 0x00100000

 9516 22:59:40.763650  COREBOOT    8. 0xffe64000 0x00002000

 9517 22:59:40.767359  IMD small region:

 9518 22:59:40.770332    IMD ROOT    0. 0xffffec00 0x00000400

 9519 22:59:40.774093    VPD         1. 0xffffeba0 0x0000004c

 9520 22:59:40.777254    MMC STATUS  2. 0xffffeb80 0x00000004

 9521 22:59:40.783646  BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms

 9522 22:59:40.784042  Probing TPM:  done!

 9523 22:59:40.790768  Connected to device vid:did:rid of 1ae0:0028:00

 9524 22:59:40.796737  Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8

 9525 22:59:40.800406  Initialized TPM device CR50 revision 0

 9526 22:59:40.804072  Checking cr50 for pending updates

 9527 22:59:40.809153  Reading cr50 TPM mode

 9528 22:59:40.818084  BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms

 9529 22:59:40.824859  CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098

 9530 22:59:40.864450  read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps

 9531 22:59:40.867931  Checking segment from ROM address 0x40100000

 9532 22:59:40.871492  Checking segment from ROM address 0x4010001c

 9533 22:59:40.878666  Loading segment from ROM address 0x40100000

 9534 22:59:40.879194    code (compression=0)

 9535 22:59:40.884675    New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178

 9536 22:59:40.894499  Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178

 9537 22:59:40.895048  it's not compressed!

 9538 22:59:40.901351  [ 0x80000000, 8004f178, 0x821a7280) <- 40100038

 9539 22:59:40.907602  Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108

 9540 22:59:40.925314  Loading segment from ROM address 0x4010001c

 9541 22:59:40.925827    Entry Point 0x80000000

 9542 22:59:40.928430  Loaded segments

 9543 22:59:40.932098  BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms

 9544 22:59:40.938515  Jumping to boot code at 0x80000000(0xffe64000)

 9545 22:59:40.944987  CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes

 9546 22:59:40.951437  CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290

 9547 22:59:40.959537  read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps

 9548 22:59:40.963130  Checking segment from ROM address 0x40100000

 9549 22:59:40.966006  Checking segment from ROM address 0x4010001c

 9550 22:59:40.972440  Loading segment from ROM address 0x40100000

 9551 22:59:40.972920    code (compression=1)

 9552 22:59:40.979393    New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470

 9553 22:59:40.989245  Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470

 9554 22:59:40.989914  using LZMA

 9555 22:59:40.997673  [ 0x54600000, 54614abc, 0x5462e000) <- 40100038

 9556 22:59:41.004592  Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544

 9557 22:59:41.007415  Loading segment from ROM address 0x4010001c

 9558 22:59:41.007888    Entry Point 0x54601000

 9559 22:59:41.011262  Loaded segments

 9560 22:59:41.014113  NOTICE:  MT8192 bl31_setup

 9561 22:59:41.021320  NOTICE:  BL31: v2.4(debug):v2.4-448-gce3ebc861

 9562 22:59:41.025040  NOTICE:  BL31: Built : Sat Sep 11 09:59:37 UTC 2021

 9563 22:59:41.028039  WARNING: region 0:

 9564 22:59:41.031671  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9565 22:59:41.032106  WARNING: region 1:

 9566 22:59:41.038523  WARNING: 	sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d

 9567 22:59:41.041386  WARNING: region 2:

 9568 22:59:41.044610  WARNING: 	sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d

 9569 22:59:41.047688  WARNING: region 3:

 9570 22:59:41.051434  WARNING: 	sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d

 9571 22:59:41.055182  WARNING: region 4:

 9572 22:59:41.061186  WARNING: 	sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d

 9573 22:59:41.061620  WARNING: region 5:

 9574 22:59:41.064611  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9575 22:59:41.068292  WARNING: region 6:

 9576 22:59:41.071182  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9577 22:59:41.074908  WARNING: region 7:

 9578 22:59:41.078065  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9579 22:59:41.084620  INFO:    [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000

 9580 22:59:41.087946  INFO:    [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0

 9581 22:59:41.091148  INFO:    [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff

 9582 22:59:41.098005  INFO:    [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff

 9583 22:59:41.101242  INFO:    [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff

 9584 22:59:41.104381  INFO:    [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00

 9585 22:59:41.111452  INFO:    [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff

 9586 22:59:41.114523  INFO:    [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff

 9587 22:59:41.120765  INFO:    [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff

 9588 22:59:41.124116  INFO:    [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff

 9589 22:59:41.127746  INFO:    [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff

 9590 22:59:41.134160  INFO:    [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff

 9591 22:59:41.137585  INFO:    [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff

 9592 22:59:41.140733  INFO:    [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff

 9593 22:59:41.147384  INFO:    [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff

 9594 22:59:41.150606  INFO:    [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff

 9595 22:59:41.157240  INFO:    [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff

 9596 22:59:41.160305  INFO:    [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff

 9597 22:59:41.163876  INFO:    [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff

 9598 22:59:41.170411  INFO:    [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff

 9599 22:59:41.173752  INFO:    [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff

 9600 22:59:41.180887  INFO:    [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff

 9601 22:59:41.184069  INFO:    [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff

 9602 22:59:41.187032  INFO:    [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff

 9603 22:59:41.193693  INFO:    [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff

 9604 22:59:41.197279  INFO:    [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff

 9605 22:59:41.204067  INFO:    [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff

 9606 22:59:41.207044  INFO:    [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff

 9607 22:59:41.210702  INFO:    [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff

 9608 22:59:41.216785  INFO:    [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff

 9609 22:59:41.220712  INFO:    [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff

 9610 22:59:41.227128  INFO:    [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff

 9611 22:59:41.230124  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0

 9612 22:59:41.234224  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0

 9613 22:59:41.237108  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0

 9614 22:59:41.244239  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0

 9615 22:59:41.247098  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0

 9616 22:59:41.250130  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0

 9617 22:59:41.254129  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0

 9618 22:59:41.260440  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0

 9619 22:59:41.263418  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0

 9620 22:59:41.266556  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0

 9621 22:59:41.270075  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0

 9622 22:59:41.276848  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0

 9623 22:59:41.280217  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0

 9624 22:59:41.283154  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0

 9625 22:59:41.286804  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0

 9626 22:59:41.293324  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0

 9627 22:59:41.296562  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff

 9628 22:59:41.303230  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff

 9629 22:59:41.306453  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff

 9630 22:59:41.309406  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff

 9631 22:59:41.316178  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff

 9632 22:59:41.319709  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff

 9633 22:59:41.325938  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff

 9634 22:59:41.329678  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff

 9635 22:59:41.336027  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff

 9636 22:59:41.339073  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff

 9637 22:59:41.342808  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff

 9638 22:59:41.349546  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff

 9639 22:59:41.352748  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff

 9640 22:59:41.359556  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff

 9641 22:59:41.362740  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff

 9642 22:59:41.369342  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff

 9643 22:59:41.372380  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff

 9644 22:59:41.379034  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff

 9645 22:59:41.382480  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff

 9646 22:59:41.386058  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff

 9647 22:59:41.392416  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff

 9648 22:59:41.395390  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff

 9649 22:59:41.402639  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff

 9650 22:59:41.405709  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff

 9651 22:59:41.412500  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff

 9652 22:59:41.415455  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff

 9653 22:59:41.422288  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff

 9654 22:59:41.425396  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff

 9655 22:59:41.429016  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff

 9656 22:59:41.435403  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff

 9657 22:59:41.438988  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff

 9658 22:59:41.445423  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff

 9659 22:59:41.448609  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff

 9660 22:59:41.455173  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff

 9661 22:59:41.458778  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff

 9662 22:59:41.465587  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff

 9663 22:59:41.468512  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff

 9664 22:59:41.472072  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff

 9665 22:59:41.478724  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff

 9666 22:59:41.481692  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff

 9667 22:59:41.488708  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff

 9668 22:59:41.491772  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff

 9669 22:59:41.498429  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff

 9670 22:59:41.502015  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff

 9671 22:59:41.505745  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff

 9672 22:59:41.511766  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff

 9673 22:59:41.515857  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff

 9674 22:59:41.521757  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff

 9675 22:59:41.525617  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0

 9676 22:59:41.528479  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0

 9677 22:59:41.535547  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0

 9678 22:59:41.538850  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0

 9679 22:59:41.541782  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0

 9680 22:59:41.545266  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff

 9681 22:59:41.551859  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff

 9682 22:59:41.554788  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff

 9683 22:59:41.561761  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff

 9684 22:59:41.564803  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff

 9685 22:59:41.571848  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff

 9686 22:59:41.574945  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff

 9687 22:59:41.578719  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff

 9688 22:59:41.585023  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff

 9689 22:59:41.588396  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff

 9690 22:59:41.591413  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff

 9691 22:59:41.598038  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff

 9692 22:59:41.601547  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff

 9693 22:59:41.608098  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff

 9694 22:59:41.611954  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff

 9695 22:59:41.614924  INFO:    [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18

 9696 22:59:41.621865  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000

 9697 22:59:41.625006  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004

 9698 22:59:41.628355  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0

 9699 22:59:41.634749  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0

 9700 22:59:41.638195  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0

 9701 22:59:41.641307  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0

 9702 22:59:41.644890  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000

 9703 22:59:41.651450  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff

 9704 22:59:41.655082  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff

 9705 22:59:41.658104  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff

 9706 22:59:41.664862  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff

 9707 22:59:41.668011  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff

 9708 22:59:41.674608  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff

 9709 22:59:41.677664  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff

 9710 22:59:41.681316  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc

 9711 22:59:41.687905  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff

 9712 22:59:41.691461  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf

 9713 22:59:41.697680  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff

 9714 22:59:41.701168  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc

 9715 22:59:41.704192  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff

 9716 22:59:41.710702  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff

 9717 22:59:41.713686  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff

 9718 22:59:41.720491  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff

 9719 22:59:41.723966  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff

 9720 22:59:41.727114  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff

 9721 22:59:41.733903  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff

 9722 22:59:41.737136  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff

 9723 22:59:41.743993  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff

 9724 22:59:41.747063  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff

 9725 22:59:41.750501  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff

 9726 22:59:41.757087  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff

 9727 22:59:41.760692  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff

 9728 22:59:41.763754  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff

 9729 22:59:41.770628  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff

 9730 22:59:41.773680  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff

 9731 22:59:41.780377  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff

 9732 22:59:41.783464  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff

 9733 22:59:41.786630  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff

 9734 22:59:41.793308  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff

 9735 22:59:41.796700  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff

 9736 22:59:41.803278  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff

 9737 22:59:41.806736  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff

 9738 22:59:41.809827  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff

 9739 22:59:41.816394  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff

 9740 22:59:41.819967  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff

 9741 22:59:41.826681  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff

 9742 22:59:41.829935  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff

 9743 22:59:41.832944  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff

 9744 22:59:41.840174  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff

 9745 22:59:41.843313  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff

 9746 22:59:41.850126  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff

 9747 22:59:41.853217  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff

 9748 22:59:41.856960  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff

 9749 22:59:41.863115  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff

 9750 22:59:41.866202  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff

 9751 22:59:41.872960  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff

 9752 22:59:41.876011  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff

 9753 22:59:41.879763  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff

 9754 22:59:41.886745  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff

 9755 22:59:41.889915  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff

 9756 22:59:41.896178  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff

 9757 22:59:41.899443  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff

 9758 22:59:41.902922  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff

 9759 22:59:41.909437  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff

 9760 22:59:41.912787  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff

 9761 22:59:41.919229  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff

 9762 22:59:41.922122  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff

 9763 22:59:41.928857  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff

 9764 22:59:41.931832  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff

 9765 22:59:41.935500  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff

 9766 22:59:41.942479  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff

 9767 22:59:41.945407  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff

 9768 22:59:41.951991  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff

 9769 22:59:41.955214  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff

 9770 22:59:41.958914  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff

 9771 22:59:41.965059  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff

 9772 22:59:41.968202  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff

 9773 22:59:41.975004  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff

 9774 22:59:41.978120  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff

 9775 22:59:41.984661  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff

 9776 22:59:41.987889  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff

 9777 22:59:41.991548  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff

 9778 22:59:41.997804  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff

 9779 22:59:42.000881  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff

 9780 22:59:42.007800  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff

 9781 22:59:42.010884  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff

 9782 22:59:42.017991  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff

 9783 22:59:42.021087  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff

 9784 22:59:42.024166  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff

 9785 22:59:42.030805  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff

 9786 22:59:42.033949  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff

 9787 22:59:42.040630  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff

 9788 22:59:42.043661  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff

 9789 22:59:42.050748  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff

 9790 22:59:42.054611  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff

 9791 22:59:42.057625  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff

 9792 22:59:42.064314  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff

 9793 22:59:42.067396  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff

 9794 22:59:42.074244  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff

 9795 22:59:42.077486  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff

 9796 22:59:42.080673  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff

 9797 22:59:42.087466  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff

 9798 22:59:42.090650  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff

 9799 22:59:42.097251  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff

 9800 22:59:42.101313  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff

 9801 22:59:42.107463  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff

 9802 22:59:42.110836  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff

 9803 22:59:42.113745  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff

 9804 22:59:42.120287  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff

 9805 22:59:42.123639  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff

 9806 22:59:42.130656  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff

 9807 22:59:42.133989  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff

 9808 22:59:42.136975  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0

 9809 22:59:42.140480  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0

 9810 22:59:42.147352  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0

 9811 22:59:42.150340  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0

 9812 22:59:42.153257  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0

 9813 22:59:42.160218  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff

 9814 22:59:42.163188  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff

 9815 22:59:42.166972  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff

 9816 22:59:42.173064  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff

 9817 22:59:42.176704  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf

 9818 22:59:42.179722  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff

 9819 22:59:42.186409  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff

 9820 22:59:42.190021  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff

 9821 22:59:42.196478  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff

 9822 22:59:42.199574  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf

 9823 22:59:42.202692  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff

 9824 22:59:42.209966  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff

 9825 22:59:42.212985  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff

 9826 22:59:42.219544  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff

 9827 22:59:42.222624  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf

 9828 22:59:42.225996  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff

 9829 22:59:42.232491  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff

 9830 22:59:42.236191  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff

 9831 22:59:42.239738  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff

 9832 22:59:42.246380  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf

 9833 22:59:42.249413  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff

 9834 22:59:42.252494  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff

 9835 22:59:42.259436  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff

 9836 22:59:42.262547  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff

 9837 22:59:42.269328  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf

 9838 22:59:42.272593  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff

 9839 22:59:42.275488  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff

 9840 22:59:42.282159  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff

 9841 22:59:42.285817  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff

 9842 22:59:42.289235  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf

 9843 22:59:42.296136  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff

 9844 22:59:42.299194  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff

 9845 22:59:42.305499  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff

 9846 22:59:42.308637  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff

 9847 22:59:42.312107  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf

 9848 22:59:42.315080  INFO:    [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0

 9849 22:59:42.322019  INFO:    [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3

 9850 22:59:42.324865  INFO:    [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3

 9851 22:59:42.328300  INFO:    [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3

 9852 22:59:42.331751  INFO:    [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0

 9853 22:59:42.338328  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400

 9854 22:59:42.341330  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0

 9855 22:59:42.344986  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0

 9856 22:59:42.348213  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0

 9857 22:59:42.354927  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0

 9858 22:59:42.357940  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0

 9859 22:59:42.361532  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000

 9860 22:59:42.367680  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0

 9861 22:59:42.371288  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff

 9862 22:59:42.374354  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff

 9863 22:59:42.381615  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff

 9864 22:59:42.384680  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff

 9865 22:59:42.391025  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff

 9866 22:59:42.394658  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff

 9867 22:59:42.400522  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff

 9868 22:59:42.403664  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f

 9869 22:59:42.407388  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3

 9870 22:59:42.413413  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff

 9871 22:59:42.416946  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff

 9872 22:59:42.423485  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff

 9873 22:59:42.426547  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff

 9874 22:59:42.433583  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff

 9875 22:59:42.436487  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff

 9876 22:59:42.440208  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f

 9877 22:59:42.446743  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff

 9878 22:59:42.450114  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff

 9879 22:59:42.456384  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff

 9880 22:59:42.459975  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff

 9881 22:59:42.466093  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff

 9882 22:59:42.469748  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff

 9883 22:59:42.472792  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff

 9884 22:59:42.479566  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f

 9885 22:59:42.482605  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff

 9886 22:59:42.489496  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff

 9887 22:59:42.493056  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff

 9888 22:59:42.496189  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff

 9889 22:59:42.502928  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff

 9890 22:59:42.506076  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff

 9891 22:59:42.512944  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff

 9892 22:59:42.516046  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f

 9893 22:59:42.518981  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff

 9894 22:59:42.525538  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff

 9895 22:59:42.529009  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff

 9896 22:59:42.535558  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff

 9897 22:59:42.539038  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff

 9898 22:59:42.545668  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff

 9899 22:59:42.549282  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff

 9900 22:59:42.552270  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f

 9901 22:59:42.559024  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff

 9902 22:59:42.562521  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff

 9903 22:59:42.568812  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff

 9904 22:59:42.572435  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff

 9905 22:59:42.575475  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff

 9906 22:59:42.582102  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff

 9907 22:59:42.585414  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff

 9908 22:59:42.592283  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f

 9909 22:59:42.595376  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff

 9910 22:59:42.598812  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff

 9911 22:59:42.605863  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff

 9912 22:59:42.608873  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff

 9913 22:59:42.615838  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff

 9914 22:59:42.618869  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff

 9915 22:59:42.625548  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff

 9916 22:59:42.629065  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f

 9917 22:59:42.632055  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff

 9918 22:59:42.638561  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff

 9919 22:59:42.641987  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff

 9920 22:59:42.648478  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff

 9921 22:59:42.652113  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff

 9922 22:59:42.655137  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff

 9923 22:59:42.661639  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff

 9924 22:59:42.665287  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f

 9925 22:59:42.672269  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff

 9926 22:59:42.675251  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff

 9927 22:59:42.678312  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff

 9928 22:59:42.684884  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff

 9929 22:59:42.688609  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff

 9930 22:59:42.694665  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff

 9931 22:59:42.698409  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff

 9932 22:59:42.701279  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f

 9933 22:59:42.708626  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff

 9934 22:59:42.711787  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff

 9935 22:59:42.718366  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff

 9936 22:59:42.721411  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff

 9937 22:59:42.728002  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff

 9938 22:59:42.730877  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff

 9939 22:59:42.738230  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff

 9940 22:59:42.741067  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f

 9941 22:59:42.744463  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff

 9942 22:59:42.750934  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff

 9943 22:59:42.754286  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff

 9944 22:59:42.761315  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff

 9945 22:59:42.764221  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff

 9946 22:59:42.771157  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff

 9947 22:59:42.774217  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff

 9948 22:59:42.781047  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f

 9949 22:59:42.783998  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff

 9950 22:59:42.787085  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff

 9951 22:59:42.793828  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff

 9952 22:59:42.797584  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff

 9953 22:59:42.803726  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff

 9954 22:59:42.807215  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff

 9955 22:59:42.813812  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff

 9956 22:59:42.816958  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f

 9957 22:59:42.823773  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff

 9958 22:59:42.826933  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff

 9959 22:59:42.833385  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff

 9960 22:59:42.837040  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff

 9961 22:59:42.840010  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff

 9962 22:59:42.846602  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff

 9963 22:59:42.849948  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff

 9964 22:59:42.856509  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f

 9965 22:59:42.860253  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff

 9966 22:59:42.866420  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff

 9967 22:59:42.869882  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff

 9968 22:59:42.876640  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff

 9969 22:59:42.880230  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff

 9970 22:59:42.882824  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff

 9971 22:59:42.889542  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff

 9972 22:59:42.892734  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f

 9973 22:59:42.899463  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff

 9974 22:59:42.902525  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff

 9975 22:59:42.909425  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff

 9976 22:59:42.912437  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff

 9977 22:59:42.918971  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff

 9978 22:59:42.922593  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff

 9979 22:59:42.928966  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff

 9980 22:59:42.932559  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f

 9981 22:59:42.935516  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0

 9982 22:59:42.942147  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000

 9983 22:59:42.945623  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff

 9984 22:59:42.952051  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff

 9985 22:59:42.955550  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3

 9986 22:59:42.962231  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff

 9987 22:59:42.965382  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff

 9988 22:59:42.968755  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff

 9989 22:59:42.975322  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff

 9990 22:59:42.978371  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff

 9991 22:59:42.985198  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff

 9992 22:59:42.988269  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff

 9993 22:59:42.994604  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff

 9994 22:59:42.998313  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff

 9995 22:59:43.004680  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff

 9996 22:59:43.007783  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff

 9997 22:59:43.014529  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff

 9998 22:59:43.017923  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff

 9999 22:59:43.024098  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff

10000 22:59:43.027723  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff

10001 22:59:43.034597  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff

10002 22:59:43.037670  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff

10003 22:59:43.044164  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff

10004 22:59:43.047842  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff

10005 22:59:43.054401  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff

10006 22:59:43.057431  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff

10007 22:59:43.063855  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff

10008 22:59:43.067463  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff

10009 22:59:43.073572  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff

10010 22:59:43.080713  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff

10011 22:59:43.083445  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff

10012 22:59:43.090243  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff

10013 22:59:43.093461  INFO:    [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0

10014 22:59:43.093563  INFO:    [APUAPC] vio 0

10015 22:59:43.100949  INFO:    [APUAPC] set_apusys_ao_apc - SUCCESS!

10016 22:59:43.104085  INFO:    [APUAPC] set_apusys_noc_dapc - SUCCESS!

10017 22:59:43.107213  INFO:    [APUAPC] D0_APC_0: 0x400510

10018 22:59:43.110841  INFO:    [APUAPC] D0_APC_1: 0x0

10019 22:59:43.113895  INFO:    [APUAPC] D0_APC_2: 0x1540

10020 22:59:43.117537  INFO:    [APUAPC] D0_APC_3: 0x0

10021 22:59:43.120498  INFO:    [APUAPC] D1_APC_0: 0xffffffff

10022 22:59:43.124200  INFO:    [APUAPC] D1_APC_1: 0xffffffff

10023 22:59:43.127180  INFO:    [APUAPC] D1_APC_2: 0x3fffff

10024 22:59:43.130278  INFO:    [APUAPC] D1_APC_3: 0x0

10025 22:59:43.134117  INFO:    [APUAPC] D2_APC_0: 0xffffffff

10026 22:59:43.137215  INFO:    [APUAPC] D2_APC_1: 0xffffffff

10027 22:59:43.140259  INFO:    [APUAPC] D2_APC_2: 0x3fffff

10028 22:59:43.143265  INFO:    [APUAPC] D2_APC_3: 0x0

10029 22:59:43.147065  INFO:    [APUAPC] D3_APC_0: 0xffffffff

10030 22:59:43.149938  INFO:    [APUAPC] D3_APC_1: 0xffffffff

10031 22:59:43.153603  INFO:    [APUAPC] D3_APC_2: 0x3fffff

10032 22:59:43.156526  INFO:    [APUAPC] D3_APC_3: 0x0

10033 22:59:43.160004  INFO:    [APUAPC] D4_APC_0: 0xffffffff

10034 22:59:43.163631  INFO:    [APUAPC] D4_APC_1: 0xffffffff

10035 22:59:43.166479  INFO:    [APUAPC] D4_APC_2: 0x3fffff

10036 22:59:43.170104  INFO:    [APUAPC] D4_APC_3: 0x0

10037 22:59:43.173502  INFO:    [APUAPC] D5_APC_0: 0xffffffff

10038 22:59:43.176629  INFO:    [APUAPC] D5_APC_1: 0xffffffff

10039 22:59:43.179997  INFO:    [APUAPC] D5_APC_2: 0x3fffff

10040 22:59:43.183072  INFO:    [APUAPC] D5_APC_3: 0x0

10041 22:59:43.186546  INFO:    [APUAPC] D6_APC_0: 0xffffffff

10042 22:59:43.189467  INFO:    [APUAPC] D6_APC_1: 0xffffffff

10043 22:59:43.193126  INFO:    [APUAPC] D6_APC_2: 0x3fffff

10044 22:59:43.196219  INFO:    [APUAPC] D6_APC_3: 0x0

10045 22:59:43.200215  INFO:    [APUAPC] D7_APC_0: 0xffffffff

10046 22:59:43.203341  INFO:    [APUAPC] D7_APC_1: 0xffffffff

10047 22:59:43.206539  INFO:    [APUAPC] D7_APC_2: 0x3fffff

10048 22:59:43.206963  INFO:    [APUAPC] D7_APC_3: 0x0

10049 22:59:43.213155  INFO:    [APUAPC] D8_APC_0: 0xffffffff

10050 22:59:43.216691  INFO:    [APUAPC] D8_APC_1: 0xffffffff

10051 22:59:43.219926  INFO:    [APUAPC] D8_APC_2: 0x3fffff

10052 22:59:43.220363  INFO:    [APUAPC] D8_APC_3: 0x0

10053 22:59:43.223120  INFO:    [APUAPC] D9_APC_0: 0xffffffff

10054 22:59:43.229568  INFO:    [APUAPC] D9_APC_1: 0xffffffff

10055 22:59:43.233292  INFO:    [APUAPC] D9_APC_2: 0x3fffff

10056 22:59:43.233726  INFO:    [APUAPC] D9_APC_3: 0x0

10057 22:59:43.236246  INFO:    [APUAPC] D10_APC_0: 0xffffffff

10058 22:59:43.243055  INFO:    [APUAPC] D10_APC_1: 0xffffffff

10059 22:59:43.246085  INFO:    [APUAPC] D10_APC_2: 0x3fffff

10060 22:59:43.246516  INFO:    [APUAPC] D10_APC_3: 0x0

10061 22:59:43.252978  INFO:    [APUAPC] D11_APC_0: 0xffffffff

10062 22:59:43.255809  INFO:    [APUAPC] D11_APC_1: 0xffffffff

10063 22:59:43.259697  INFO:    [APUAPC] D11_APC_2: 0x3fffff

10064 22:59:43.262280  INFO:    [APUAPC] D11_APC_3: 0x0

10065 22:59:43.265793  INFO:    [APUAPC] D12_APC_0: 0xffffffff

10066 22:59:43.269055  INFO:    [APUAPC] D12_APC_1: 0xffffffff

10067 22:59:43.272717  INFO:    [APUAPC] D12_APC_2: 0x3fffff

10068 22:59:43.275863  INFO:    [APUAPC] D12_APC_3: 0x0

10069 22:59:43.278833  INFO:    [APUAPC] D13_APC_0: 0xffffffff

10070 22:59:43.282411  INFO:    [APUAPC] D13_APC_1: 0xffffffff

10071 22:59:43.285398  INFO:    [APUAPC] D13_APC_2: 0x3fffff

10072 22:59:43.288992  INFO:    [APUAPC] D13_APC_3: 0x0

10073 22:59:43.292372  INFO:    [APUAPC] D14_APC_0: 0xffffffff

10074 22:59:43.295626  INFO:    [APUAPC] D14_APC_1: 0xffffffff

10075 22:59:43.298677  INFO:    [APUAPC] D14_APC_2: 0x3fffff

10076 22:59:43.302499  INFO:    [APUAPC] D14_APC_3: 0x0

10077 22:59:43.305358  INFO:    [APUAPC] D15_APC_0: 0xffffffff

10078 22:59:43.309303  INFO:    [APUAPC] D15_APC_1: 0xffffffff

10079 22:59:43.312212  INFO:    [APUAPC] D15_APC_2: 0x3fffff

10080 22:59:43.315429  INFO:    [APUAPC] D15_APC_3: 0x0

10081 22:59:43.319110  INFO:    [APUAPC] APC_CON: 0x4

10082 22:59:43.319815  INFO:    [NOCDAPC] D0_APC_0: 0x0

10083 22:59:43.321982  INFO:    [NOCDAPC] D0_APC_1: 0x0

10084 22:59:43.325034  INFO:    [NOCDAPC] D1_APC_0: 0x0

10085 22:59:43.328742  INFO:    [NOCDAPC] D1_APC_1: 0xfff

10086 22:59:43.332171  INFO:    [NOCDAPC] D2_APC_0: 0x0

10087 22:59:43.335250  INFO:    [NOCDAPC] D2_APC_1: 0xfff

10088 22:59:43.338585  INFO:    [NOCDAPC] D3_APC_0: 0x0

10089 22:59:43.342066  INFO:    [NOCDAPC] D3_APC_1: 0xfff

10090 22:59:43.345161  INFO:    [NOCDAPC] D4_APC_0: 0x0

10091 22:59:43.348327  INFO:    [NOCDAPC] D4_APC_1: 0xfff

10092 22:59:43.351451  INFO:    [NOCDAPC] D5_APC_0: 0x0

10093 22:59:43.351876  INFO:    [NOCDAPC] D5_APC_1: 0xfff

10094 22:59:43.354891  INFO:    [NOCDAPC] D6_APC_0: 0x0

10095 22:59:43.358498  INFO:    [NOCDAPC] D6_APC_1: 0xfff

10096 22:59:43.361582  INFO:    [NOCDAPC] D7_APC_0: 0x0

10097 22:59:43.365158  INFO:    [NOCDAPC] D7_APC_1: 0xfff

10098 22:59:43.368000  INFO:    [NOCDAPC] D8_APC_0: 0x0

10099 22:59:43.371611  INFO:    [NOCDAPC] D8_APC_1: 0xfff

10100 22:59:43.374996  INFO:    [NOCDAPC] D9_APC_0: 0x0

10101 22:59:43.377914  INFO:    [NOCDAPC] D9_APC_1: 0xfff

10102 22:59:43.381571  INFO:    [NOCDAPC] D10_APC_0: 0x0

10103 22:59:43.384579  INFO:    [NOCDAPC] D10_APC_1: 0xfff

10104 22:59:43.388104  INFO:    [NOCDAPC] D11_APC_0: 0x0

10105 22:59:43.391099  INFO:    [NOCDAPC] D11_APC_1: 0xfff

10106 22:59:43.391524  INFO:    [NOCDAPC] D12_APC_0: 0x0

10107 22:59:43.394673  INFO:    [NOCDAPC] D12_APC_1: 0xfff

10108 22:59:43.397637  INFO:    [NOCDAPC] D13_APC_0: 0x0

10109 22:59:43.401227  INFO:    [NOCDAPC] D13_APC_1: 0xfff

10110 22:59:43.404159  INFO:    [NOCDAPC] D14_APC_0: 0x0

10111 22:59:43.407264  INFO:    [NOCDAPC] D14_APC_1: 0xfff

10112 22:59:43.411181  INFO:    [NOCDAPC] D15_APC_0: 0x0

10113 22:59:43.414019  INFO:    [NOCDAPC] D15_APC_1: 0xfff

10114 22:59:43.417064  INFO:    [NOCDAPC] APC_CON: 0x4

10115 22:59:43.420827  INFO:    [APUAPC] set_apusys_apc done

10116 22:59:43.423922  INFO:    [DEVAPC] devapc_init done

10117 22:59:43.427068  INFO:    GICv3 without legacy support detected.

10118 22:59:43.430778  INFO:    ARM GICv3 driver initialized in EL3

10119 22:59:43.436797  INFO:    Maximum SPI INTID supported: 639

10120 22:59:43.440573  INFO:    BL31: Initializing runtime services

10121 22:59:43.446468  WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!

10122 22:59:43.446578  INFO:    SPM: enable CPC mode

10123 22:59:43.453389  INFO:    mcdi ready for mcusys-off-idle and system suspend

10124 22:59:43.456271  INFO:    BL31: Preparing for EL3 exit to normal world

10125 22:59:43.459851  INFO:    Entry point address = 0x80000000

10126 22:59:43.462885  INFO:    SPSR = 0x8

10127 22:59:43.469359  

10128 22:59:43.469439  

10129 22:59:43.469505  

10130 22:59:43.472377  Starting depthcharge on Spherion...

10131 22:59:43.472483  

10132 22:59:43.472614  Wipe memory regions:

10133 22:59:43.472692  

10134 22:59:43.473324  end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10135 22:59:43.473431  start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10136 22:59:43.473516  Setting prompt string to ['asurada:']
10137 22:59:43.473598  bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10138 22:59:43.475372  	[0x00000040000000, 0x00000054600000)

10139 22:59:43.597997  

10140 22:59:43.598154  	[0x00000054660000, 0x00000080000000)

10141 22:59:43.859180  

10142 22:59:43.859752  	[0x000000821a7280, 0x000000ffe64000)

10143 22:59:44.603955  

10144 22:59:44.604484  	[0x00000100000000, 0x00000240000000)

10145 22:59:46.494000  

10146 22:59:46.497170  Initializing XHCI USB controller at 0x11200000.

10147 22:59:47.479240  

10148 22:59:47.479765  R8152: Initializing

10149 22:59:47.480105  

10150 22:59:47.482031  Version 9 (ocp_data = 6010)

10151 22:59:47.482452  

10152 22:59:47.485605  R8152: Done initializing

10153 22:59:47.486025  

10154 22:59:47.486357  Adding net device

10155 22:59:48.007714  

10156 22:59:48.010331  [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43

10157 22:59:48.010760  

10158 22:59:48.011092  

10159 22:59:48.011402  

10160 22:59:48.012137  Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10162 22:59:48.113367  asurada: tftpboot 192.168.201.1 10597704/tftp-deploy-2k1f8v8j/kernel/image.itb 10597704/tftp-deploy-2k1f8v8j/kernel/cmdline 

10163 22:59:48.113989  Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10164 22:59:48.114401  bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10165 22:59:48.119221  tftpboot 192.168.201.1 10597704/tftp-deploy-2k1f8v8j/kernel/image.ittp-deploy-2k1f8v8j/kernel/cmdline 

10166 22:59:48.119653  

10167 22:59:48.119989  Waiting for link

10168 22:59:48.321514  

10169 22:59:48.322119  done.

10170 22:59:48.322467  

10171 22:59:48.322781  MAC: f4:f5:e8:50:de:0a

10172 22:59:48.323081  

10173 22:59:48.324589  Sending DHCP discover... done.

10174 22:59:48.325027  

10175 22:59:48.327954  Waiting for reply... done.

10176 22:59:48.328346  

10177 22:59:48.331499  Sending DHCP request... done.

10178 22:59:48.331919  

10179 22:59:48.339436  Waiting for reply... done.

10180 22:59:48.339965  

10181 22:59:48.340357  My ip is 192.168.201.14

10182 22:59:48.340796  

10183 22:59:48.342684  The DHCP server ip is 192.168.201.1

10184 22:59:48.343117  

10185 22:59:48.349736  TFTP server IP predefined by user: 192.168.201.1

10186 22:59:48.350165  

10187 22:59:48.355853  Bootfile predefined by user: 10597704/tftp-deploy-2k1f8v8j/kernel/image.itb

10188 22:59:48.356281  

10189 22:59:48.356663  Sending tftp read request... done.

10190 22:59:48.358999  

10191 22:59:48.365001  Waiting for the transfer... 

10192 22:59:48.365515  

10193 22:59:48.698171  00000000 ################################################################

10194 22:59:48.698324  

10195 22:59:48.933180  00080000 ################################################################

10196 22:59:48.933322  

10197 22:59:49.169819  00100000 ################################################################

10198 22:59:49.169993  

10199 22:59:49.425533  00180000 ################################################################

10200 22:59:49.425686  

10201 22:59:49.656119  00200000 ################################################################

10202 22:59:49.656303  

10203 22:59:49.885793  00280000 ################################################################

10204 22:59:49.885940  

10205 22:59:50.114485  00300000 ################################################################

10206 22:59:50.114635  

10207 22:59:50.338173  00380000 ################################################################

10208 22:59:50.338360  

10209 22:59:50.562489  00400000 ################################################################

10210 22:59:50.562662  

10211 22:59:50.792404  00480000 ################################################################

10212 22:59:50.792563  

10213 22:59:51.041931  00500000 ################################################################

10214 22:59:51.042079  

10215 22:59:51.278264  00580000 ################################################################

10216 22:59:51.278414  

10217 22:59:51.520774  00600000 ################################################################

10218 22:59:51.520930  

10219 22:59:51.840119  00680000 ################################################################

10220 22:59:51.840314  

10221 22:59:52.117576  00700000 ################################################################

10222 22:59:52.117750  

10223 22:59:52.416300  00780000 ################################################################

10224 22:59:52.416502  

10225 22:59:52.664907  00800000 ################################################################

10226 22:59:52.665076  

10227 22:59:52.919403  00880000 ################################################################

10228 22:59:52.919550  

10229 22:59:53.153731  00900000 ################################################################

10230 22:59:53.153881  

10231 22:59:53.379347  00980000 ################################################################

10232 22:59:53.379520  

10233 22:59:53.604893  00a00000 ################################################################

10234 22:59:53.605064  

10235 22:59:53.833064  00a80000 ################################################################

10236 22:59:53.833212  

10237 22:59:54.057838  00b00000 ################################################################

10238 22:59:54.057984  

10239 22:59:54.284666  00b80000 ################################################################

10240 22:59:54.284811  

10241 22:59:54.511555  00c00000 ################################################################

10242 22:59:54.511735  

10243 22:59:54.735675  00c80000 ################################################################

10244 22:59:54.735820  

10245 22:59:54.962686  00d00000 ################################################################

10246 22:59:54.962847  

10247 22:59:55.186920  00d80000 ################################################################

10248 22:59:55.187069  

10249 22:59:55.421941  00e00000 ################################################################

10250 22:59:55.422109  

10251 22:59:55.658028  00e80000 ################################################################

10252 22:59:55.658180  

10253 22:59:55.888858  00f00000 ################################################################

10254 22:59:55.889005  

10255 22:59:56.115167  00f80000 ################################################################

10256 22:59:56.115313  

10257 22:59:56.338832  01000000 ################################################################

10258 22:59:56.338981  

10259 22:59:56.568322  01080000 ################################################################

10260 22:59:56.568500  

10261 22:59:56.792706  01100000 ################################################################

10262 22:59:56.792856  

10263 22:59:57.017544  01180000 ################################################################

10264 22:59:57.017718  

10265 22:59:57.241276  01200000 ################################################################

10266 22:59:57.241421  

10267 22:59:57.481253  01280000 ################################################################

10268 22:59:57.481400  

10269 22:59:57.708183  01300000 ################################################################

10270 22:59:57.708329  

10271 22:59:57.933304  01380000 ################################################################

10272 22:59:57.933451  

10273 22:59:58.158611  01400000 ################################################################

10274 22:59:58.158760  

10275 22:59:58.390199  01480000 ################################################################

10276 22:59:58.390341  

10277 22:59:58.618159  01500000 ################################################################

10278 22:59:58.618308  

10279 22:59:58.845008  01580000 ################################################################

10280 22:59:58.845160  

10281 22:59:59.073124  01600000 ################################################################

10282 22:59:59.073283  

10283 22:59:59.299259  01680000 ################################################################

10284 22:59:59.299439  

10285 22:59:59.520411  01700000 ################################################################

10286 22:59:59.520603  

10287 22:59:59.742388  01780000 ################################################################

10288 22:59:59.742555  

10289 22:59:59.978128  01800000 ################################################################

10290 22:59:59.978281  

10291 23:00:00.200907  01880000 ################################################################

10292 23:00:00.201082  

10293 23:00:00.420489  01900000 ################################################################

10294 23:00:00.420668  

10295 23:00:00.650078  01980000 ################################################################

10296 23:00:00.650228  

10297 23:00:00.876193  01a00000 ################################################################ done.

10298 23:00:00.876374  

10299 23:00:00.879600  The bootfile was 27780462 bytes long.

10300 23:00:00.879709  

10301 23:00:00.882851  Sending tftp read request... done.

10302 23:00:00.882969  

10303 23:00:00.885906  Waiting for the transfer... 

10304 23:00:00.886019  

10305 23:00:00.886122  00000000 # done.

10306 23:00:00.886220  

10307 23:00:00.895932  Command line loaded dynamically from TFTP file: 10597704/tftp-deploy-2k1f8v8j/kernel/cmdline

10308 23:00:00.896035  

10309 23:00:00.912428  The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10597704/extract-nfsrootfs-9szzfhg_,tcp,hard ip=dhcp tftpserverip=192.168.201.1

10310 23:00:00.915669  

10311 23:00:00.915759  Loading FIT.

10312 23:00:00.915830  

10313 23:00:00.919274  Image ramdisk-1 has 17645557 bytes.

10314 23:00:00.919376  

10315 23:00:00.922252  Image fdt-1 has 46924 bytes.

10316 23:00:00.922358  

10317 23:00:00.925747  Image kernel-1 has 10085945 bytes.

10318 23:00:00.925846  

10319 23:00:00.932267  Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion

10320 23:00:00.932383  

10321 23:00:00.952320  Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192

10322 23:00:00.952472  

10323 23:00:00.955483  Choosing best match conf-1 for compat google,spherion-rev2.

10324 23:00:00.960254  

10325 23:00:00.964450  Connected to device vid:did:rid of 1ae0:0028:00

10326 23:00:00.971863  

10327 23:00:00.975453  tpm_get_response: command 0x17b, return code 0x0

10328 23:00:00.975547  

10329 23:00:00.978325  ec_init: CrosEC protocol v3 supported (256, 248)

10330 23:00:00.983664  

10331 23:00:00.986839  tpm_cleanup: add release locality here.

10332 23:00:00.986927  

10333 23:00:00.986995  Shutting down all USB controllers.

10334 23:00:00.990407  

10335 23:00:00.990492  Removing current net device

10336 23:00:00.990560  

10337 23:00:00.996494  Exiting depthcharge with code 4 at timestamp: 46945696

10338 23:00:00.996593  

10339 23:00:01.000220  LZMA decompressing kernel-1 to 0x821a6718

10340 23:00:01.000307  

10341 23:00:01.003504  LZMA decompressing kernel-1 to 0x40000000

10342 23:00:02.270449  

10343 23:00:02.270614  jumping to kernel

10344 23:00:02.271032  end: 2.2.4 bootloader-commands (duration 00:00:19) [common]
10345 23:00:02.271134  start: 2.2.5 auto-login-action (timeout 00:04:06) [common]
10346 23:00:02.271213  Setting prompt string to ['Linux version [0-9]']
10347 23:00:02.271282  Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10348 23:00:02.271353  auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10349 23:00:02.351763  

10350 23:00:02.355387  [    0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]

10351 23:00:02.358661  start: 2.2.5.1 login-action (timeout 00:04:06) [common]
10352 23:00:02.358760  The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10353 23:00:02.358850  Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10354 23:00:02.358930  Using line separator: #'\n'#
10355 23:00:02.358993  No login prompt set.
10356 23:00:02.359062  Parsing kernel messages
10357 23:00:02.359122  ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10358 23:00:02.359224  [login-action] Waiting for messages, (timeout 00:04:06)
10359 23:00:02.378074  [    0.000000] Linux version 6.1.31 (KernelCI@build-j1612582-arm64-gcc-10-defconfig-arm64-chromebook-7xwc5) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun  5 22:41:02 UTC 2023

10360 23:00:02.381932  [    0.000000] random: crng init done

10361 23:00:02.387872  [    0.000000] Machine model: Google Spherion (rev0 - 3)

10362 23:00:02.391447  [    0.000000] efi: UEFI not found.

10363 23:00:02.398052  [    0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB

10364 23:00:02.404208  [    0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool

10365 23:00:02.414557  [    0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB

10366 23:00:02.424735  [    0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool

10367 23:00:02.430816  [    0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')

10368 23:00:02.437559  [    0.000000] printk: bootconsole [mtk8250] enabled

10369 23:00:02.444084  [    0.000000] NUMA: No NUMA configuration found

10370 23:00:02.450330  [    0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]

10371 23:00:02.453924  [    0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]

10372 23:00:02.457076  [    0.000000] Zone ranges:

10373 23:00:02.463668  [    0.000000]   DMA      [mem 0x0000000040000000-0x00000000ffffffff]

10374 23:00:02.467346  [    0.000000]   DMA32    empty

10375 23:00:02.473392  [    0.000000]   Normal   [mem 0x0000000100000000-0x000000023fffffff]

10376 23:00:02.476972  [    0.000000] Movable zone start for each node

10377 23:00:02.480478  [    0.000000] Early memory node ranges

10378 23:00:02.487002  [    0.000000]   node   0: [mem 0x0000000040000000-0x000000004fffffff]

10379 23:00:02.493693  [    0.000000]   node   0: [mem 0x0000000050000000-0x00000000528fffff]

10380 23:00:02.500075  [    0.000000]   node   0: [mem 0x0000000052900000-0x00000000545fffff]

10381 23:00:02.506863  [    0.000000]   node   0: [mem 0x0000000054700000-0x00000000ffdfffff]

10382 23:00:02.513685  [    0.000000]   node   0: [mem 0x0000000100000000-0x000000023fffffff]

10383 23:00:02.520082  [    0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]

10384 23:00:02.576134  [    0.000000] On node 0, zone DMA: 256 pages in unavailable ranges

10385 23:00:02.582813  [    0.000000] On node 0, zone Normal: 512 pages in unavailable ranges

10386 23:00:02.589373  [    0.000000] cma: Reserved 32 MiB at 0x00000000fde00000

10387 23:00:02.592350  [    0.000000] psci: probing for conduit method from DT.

10388 23:00:02.599053  [    0.000000] psci: PSCIv1.1 detected in firmware.

10389 23:00:02.602602  [    0.000000] psci: Using standard PSCI v0.2 function IDs

10390 23:00:02.608730  [    0.000000] psci: MIGRATE_INFO_TYPE not supported.

10391 23:00:02.612363  [    0.000000] psci: SMC Calling Convention v1.2

10392 23:00:02.618474  [    0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016

10393 23:00:02.622151  [    0.000000] Detected VIPT I-cache on CPU0

10394 23:00:02.628395  [    0.000000] CPU features: detected: GIC system register CPU interface

10395 23:00:02.635265  [    0.000000] CPU features: detected: Virtualization Host Extensions

10396 23:00:02.641961  [    0.000000] CPU features: kernel page table isolation forced ON by KASLR

10397 23:00:02.648581  [    0.000000] CPU features: detected: Kernel page table isolation (KPTI)

10398 23:00:02.658087  [    0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009

10399 23:00:02.664853  [    0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923

10400 23:00:02.668013  [    0.000000] alternatives: applying boot alternatives

10401 23:00:02.674807  [    0.000000] Fallback order for Node 0: 0 

10402 23:00:02.681087  [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 2063616

10403 23:00:02.684565  [    0.000000] Policy zone: Normal

10404 23:00:02.704410  [    0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10597704/extract-nfsrootfs-9szzfhg_,tcp,hard ip=dhcp tftpserverip=192.168.201.1

10405 23:00:02.714496  <5>[    0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.

10406 23:00:02.725020  <6>[    0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)

10407 23:00:02.735174  <6>[    0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)

10408 23:00:02.742039  <6>[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off

10409 23:00:02.745068  <6>[    0.000000] software IO TLB: area num 8.

10410 23:00:02.802115  <6>[    0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)

10411 23:00:02.950996  <6>[    0.000000] Memory: 7955712K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397056K reserved, 32768K cma-reserved)

10412 23:00:02.957688  <6>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1

10413 23:00:02.964336  <6>[    0.000000] rcu: Preemptible hierarchical RCU implementation.

10414 23:00:02.967333  <6>[    0.000000] rcu: 	RCU event tracing is enabled.

10415 23:00:02.974262  <6>[    0.000000] rcu: 	RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.

10416 23:00:02.981128  <6>[    0.000000] 	Trampoline variant of Tasks RCU enabled.

10417 23:00:02.984130  <6>[    0.000000] 	Tracing variant of Tasks RCU enabled.

10418 23:00:02.993718  <6>[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.

10419 23:00:03.000244  <6>[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8

10420 23:00:03.007268  <6>[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0

10421 23:00:03.013478  <6>[    0.000000] GICv3: GIC: Using split EOI/Deactivate mode

10422 23:00:03.016743  <6>[    0.000000] GICv3: 608 SPIs implemented

10423 23:00:03.020587  <6>[    0.000000] GICv3: 0 Extended SPIs implemented

10424 23:00:03.026982  <6>[    0.000000] Root IRQ handler: gic_handle_irq

10425 23:00:03.029936  <6>[    0.000000] GICv3: GICv3 features: 16 PPIs

10426 23:00:03.036682  <6>[    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000

10427 23:00:03.049866  <6>[    0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }

10428 23:00:03.063159  <6>[    0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }

10429 23:00:03.069738  <6>[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.

10430 23:00:03.077661  <6>[    0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).

10431 23:00:03.091175  <6>[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns

10432 23:00:03.097210  <6>[    0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns

10433 23:00:03.104393  <6>[    0.009181] Console: colour dummy device 80x25

10434 23:00:03.114027  <6>[    0.013936] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)

10435 23:00:03.120512  <6>[    0.024378] pid_max: default: 32768 minimum: 301

10436 23:00:03.123503  <6>[    0.029250] LSM: Security Framework initializing

10437 23:00:03.131088  <6>[    0.034187] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)

10438 23:00:03.140863  <6>[    0.042001] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)

10439 23:00:03.150415  <6>[    0.051431] cblist_init_generic: Setting adjustable number of callback queues.

10440 23:00:03.153440  <6>[    0.058885] cblist_init_generic: Setting shift to 3 and lim to 1.

10441 23:00:03.160061  <6>[    0.065224] cblist_init_generic: Setting shift to 3 and lim to 1.

10442 23:00:03.166918  <6>[    0.071634] rcu: Hierarchical SRCU implementation.

10443 23:00:03.173161  <6>[    0.076647] rcu: 	Max phase no-delay instances is 1000.

10444 23:00:03.180033  <6>[    0.083666] EFI services will not be available.

10445 23:00:03.183064  <6>[    0.088664] smp: Bringing up secondary CPUs ...

10446 23:00:03.191183  <6>[    0.093718] Detected VIPT I-cache on CPU1

10447 23:00:03.197382  <6>[    0.093788] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000

10448 23:00:03.204156  <6>[    0.093819] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]

10449 23:00:03.207027  <6>[    0.094151] Detected VIPT I-cache on CPU2

10450 23:00:03.214144  <6>[    0.094201] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000

10451 23:00:03.223829  <6>[    0.094217] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]

10452 23:00:03.227567  <6>[    0.094474] Detected VIPT I-cache on CPU3

10453 23:00:03.233976  <6>[    0.094520] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000

10454 23:00:03.240119  <6>[    0.094534] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]

10455 23:00:03.243883  <6>[    0.094837] CPU features: detected: Spectre-v4

10456 23:00:03.250153  <6>[    0.094843] CPU features: detected: Spectre-BHB

10457 23:00:03.253834  <6>[    0.094849] Detected PIPT I-cache on CPU4

10458 23:00:03.260420  <6>[    0.094905] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000

10459 23:00:03.267212  <6>[    0.094921] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]

10460 23:00:03.273198  <6>[    0.095216] Detected PIPT I-cache on CPU5

10461 23:00:03.280365  <6>[    0.095279] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000

10462 23:00:03.287119  <6>[    0.095296] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]

10463 23:00:03.290109  <6>[    0.095576] Detected PIPT I-cache on CPU6

10464 23:00:03.296282  <6>[    0.095634] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000

10465 23:00:03.306089  <6>[    0.095649] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]

10466 23:00:03.309857  <6>[    0.095935] Detected PIPT I-cache on CPU7

10467 23:00:03.316252  <6>[    0.095999] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000

10468 23:00:03.322825  <6>[    0.096016] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]

10469 23:00:03.326474  <6>[    0.096064] smp: Brought up 1 node, 8 CPUs

10470 23:00:03.332964  <6>[    0.237470] SMP: Total of 8 processors activated.

10471 23:00:03.335942  <6>[    0.242422] CPU features: detected: 32-bit EL0 Support

10472 23:00:03.346314  <6>[    0.247785] CPU features: detected: Data cache clean to the PoU not required for I/D coherence

10473 23:00:03.353010  <6>[    0.256585] CPU features: detected: Common not Private translations

10474 23:00:03.359413  <6>[    0.263060] CPU features: detected: CRC32 instructions

10475 23:00:03.363057  <6>[    0.268412] CPU features: detected: RCpc load-acquire (LDAPR)

10476 23:00:03.369213  <6>[    0.274372] CPU features: detected: LSE atomic instructions

10477 23:00:03.375767  <6>[    0.280153] CPU features: detected: Privileged Access Never

10478 23:00:03.382301  <6>[    0.285933] CPU features: detected: RAS Extension Support

10479 23:00:03.389053  <6>[    0.291542] CPU features: detected: Speculative Store Bypassing Safe (SSBS)

10480 23:00:03.392658  <6>[    0.298807] CPU: All CPU(s) started at EL2

10481 23:00:03.398903  <6>[    0.303123] alternatives: applying system-wide alternatives

10482 23:00:03.408154  <6>[    0.313768] devtmpfs: initialized

10483 23:00:03.421143  <6>[    0.322724] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns

10484 23:00:03.430850  <6>[    0.332688] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)

10485 23:00:03.437230  <6>[    0.340818] pinctrl core: initialized pinctrl subsystem

10486 23:00:03.440351  <6>[    0.347416] DMI not present or invalid.

10487 23:00:03.447156  <6>[    0.351825] NET: Registered PF_NETLINK/PF_ROUTE protocol family

10488 23:00:03.456957  <6>[    0.358707] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations

10489 23:00:03.463641  <6>[    0.366291] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations

10490 23:00:03.473374  <6>[    0.374513] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations

10491 23:00:03.477088  <6>[    0.382753] audit: initializing netlink subsys (disabled)

10492 23:00:03.486928  <5>[    0.388450] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1

10493 23:00:03.493568  <6>[    0.389148] thermal_sys: Registered thermal governor 'step_wise'

10494 23:00:03.499777  <6>[    0.396416] thermal_sys: Registered thermal governor 'power_allocator'

10495 23:00:03.503607  <6>[    0.402673] cpuidle: using governor menu

10496 23:00:03.509513  <6>[    0.413638] NET: Registered PF_QIPCRTR protocol family

10497 23:00:03.516305  <6>[    0.419126] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.

10498 23:00:03.523011  <6>[    0.426227] ASID allocator initialised with 32768 entries

10499 23:00:03.525959  <6>[    0.432788] Serial: AMBA PL011 UART driver

10500 23:00:03.536409  <4>[    0.441432] Trying to register duplicate clock ID: 134

10501 23:00:03.592383  <6>[    0.500867] KASLR enabled

10502 23:00:03.606494  <6>[    0.508596] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages

10503 23:00:03.613349  <6>[    0.515610] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page

10504 23:00:03.620134  <6>[    0.522100] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages

10505 23:00:03.626233  <6>[    0.529106] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page

10506 23:00:03.633321  <6>[    0.535591] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages

10507 23:00:03.639877  <6>[    0.542599] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page

10508 23:00:03.646345  <6>[    0.549088] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages

10509 23:00:03.652892  <6>[    0.556093] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page

10510 23:00:03.655842  <6>[    0.563566] ACPI: Interpreter disabled.

10511 23:00:03.665077  <6>[    0.569962] iommu: Default domain type: Translated 

10512 23:00:03.671621  <6>[    0.575121] iommu: DMA domain TLB invalidation policy: strict mode 

10513 23:00:03.674731  <5>[    0.581751] SCSI subsystem initialized

10514 23:00:03.681389  <6>[    0.585990] usbcore: registered new interface driver usbfs

10515 23:00:03.688110  <6>[    0.591720] usbcore: registered new interface driver hub

10516 23:00:03.691055  <6>[    0.597274] usbcore: registered new device driver usb

10517 23:00:03.698626  <6>[    0.603376] pps_core: LinuxPPS API ver. 1 registered

10518 23:00:03.708375  <6>[    0.608568] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>

10519 23:00:03.711491  <6>[    0.617908] PTP clock support registered

10520 23:00:03.714623  <6>[    0.622149] EDAC MC: Ver: 3.0.0

10521 23:00:03.721944  <6>[    0.627321] FPGA manager framework

10522 23:00:03.728757  <6>[    0.630998] Advanced Linux Sound Architecture Driver Initialized.

10523 23:00:03.731723  <6>[    0.637763] vgaarb: loaded

10524 23:00:03.738290  <6>[    0.640943] clocksource: Switched to clocksource arch_sys_counter

10525 23:00:03.741732  <5>[    0.647393] VFS: Disk quotas dquot_6.6.0

10526 23:00:03.748373  <6>[    0.651578] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)

10527 23:00:03.751729  <6>[    0.658772] pnp: PnP ACPI: disabled

10528 23:00:03.760173  <6>[    0.665429] NET: Registered PF_INET protocol family

10529 23:00:03.769623  <6>[    0.671014] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)

10530 23:00:03.781549  <6>[    0.683323] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)

10531 23:00:03.791448  <6>[    0.692137] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)

10532 23:00:03.797860  <6>[    0.700109] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)

10533 23:00:03.807207  <6>[    0.708806] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)

10534 23:00:03.814004  <6>[    0.718548] TCP: Hash tables configured (established 65536 bind 65536)

10535 23:00:03.820902  <6>[    0.725406] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)

10536 23:00:03.830662  <6>[    0.732603] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)

10537 23:00:03.837304  <6>[    0.740304] NET: Registered PF_UNIX/PF_LOCAL protocol family

10538 23:00:03.843872  <6>[    0.746468] RPC: Registered named UNIX socket transport module.

10539 23:00:03.847303  <6>[    0.752619] RPC: Registered udp transport module.

10540 23:00:03.853869  <6>[    0.757553] RPC: Registered tcp transport module.

10541 23:00:03.860375  <6>[    0.762486] RPC: Registered tcp NFSv4.1 backchannel transport module.

10542 23:00:03.863661  <6>[    0.769155] PCI: CLS 0 bytes, default 64

10543 23:00:03.867073  <6>[    0.773535] Unpacking initramfs...

10544 23:00:03.876912  <6>[    0.777625] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available

10545 23:00:03.883561  <6>[    0.786255] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available

10546 23:00:03.889751  <6>[    0.795107] kvm [1]: IPA Size Limit: 40 bits

10547 23:00:03.893670  <6>[    0.799625] kvm [1]: GICv3: no GICV resource entry

10548 23:00:03.900048  <6>[    0.804645] kvm [1]: disabling GICv2 emulation

10549 23:00:03.906481  <6>[    0.809330] kvm [1]: GIC system register CPU interface enabled

10550 23:00:03.909496  <6>[    0.815490] kvm [1]: vgic interrupt IRQ18

10551 23:00:03.916358  <6>[    0.819841] kvm [1]: VHE mode initialized successfully

10552 23:00:03.919488  <5>[    0.826243] Initialise system trusted keyrings

10553 23:00:03.926235  <6>[    0.831032] workingset: timestamp_bits=42 max_order=21 bucket_order=0

10554 23:00:03.936107  <6>[    0.841247] squashfs: version 4.0 (2009/01/31) Phillip Lougher

10555 23:00:03.942309  <5>[    0.847618] NFS: Registering the id_resolver key type

10556 23:00:03.945973  <5>[    0.852915] Key type id_resolver registered

10557 23:00:03.952652  <5>[    0.857328] Key type id_legacy registered

10558 23:00:03.959453  <6>[    0.861621] nfs4filelayout_init: NFSv4 File Layout Driver Registering...

10559 23:00:03.965483  <6>[    0.868543] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...

10560 23:00:03.972157  <6>[    0.876271] 9p: Installing v9fs 9p2000 file system support

10561 23:00:04.009887  <5>[    0.914927] Key type asymmetric registered

10562 23:00:04.012886  <5>[    0.919259] Asymmetric key parser 'x509' registered

10563 23:00:04.022799  <6>[    0.924391] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)

10564 23:00:04.026444  <6>[    0.932001] io scheduler mq-deadline registered

10565 23:00:04.029593  <6>[    0.936760] io scheduler kyber registered

10566 23:00:04.048390  <6>[    0.953477] EINJ: ACPI disabled.

10567 23:00:04.080332  <4>[    0.979007] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10568 23:00:04.090029  <4>[    0.989630] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10569 23:00:04.104522  <6>[    1.010149] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled

10570 23:00:04.112585  <6>[    1.018086] printk: console [ttyS0] disabled

10571 23:00:04.140877  <6>[    1.042734] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2

10572 23:00:04.147464  <6>[    1.052213] printk: console [ttyS0] enabled

10573 23:00:04.150582  <6>[    1.052213] printk: console [ttyS0] enabled

10574 23:00:04.157477  <6>[    1.061130] printk: bootconsole [mtk8250] disabled

10575 23:00:04.160383  <6>[    1.061130] printk: bootconsole [mtk8250] disabled

10576 23:00:04.167186  <6>[    1.072156] SuperH (H)SCI(F) driver initialized

10577 23:00:04.170373  <6>[    1.077425] msm_serial: driver initialized

10578 23:00:04.184048  <6>[    1.086292] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000

10579 23:00:04.194286  <6>[    1.094837] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000

10580 23:00:04.200383  <6>[    1.103383] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000

10581 23:00:04.210890  <6>[    1.112011] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000

10582 23:00:04.220729  <6>[    1.120717] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000

10583 23:00:04.227259  <6>[    1.129431] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000

10584 23:00:04.237253  <6>[    1.137971] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000

10585 23:00:04.243505  <6>[    1.146775] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000

10586 23:00:04.253105  <6>[    1.155318] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000

10587 23:00:04.265869  <6>[    1.170821] loop: module loaded

10588 23:00:04.272450  <6>[    1.176628] vgpu11_sshub: Bringing 400000uV into 575000-575000uV

10589 23:00:04.295273  <4>[    1.199976] mtk-pmic-keys: Failed to locate of_node [id: -1]

10590 23:00:04.301751  <6>[    1.206726] megasas: 07.719.03.00-rc1

10591 23:00:04.311073  <6>[    1.216427] spi-nor spi2.0: w25q64jwm (8192 Kbytes)

10592 23:00:04.319159  <6>[    1.224329] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2

10593 23:00:04.336097  <6>[    1.240903] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)

10594 23:00:04.396274  <6>[    1.295092] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7

10595 23:00:04.637873  <6>[    1.543331] Freeing initrd memory: 17228K

10596 23:00:04.648399  <6>[    1.553404] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz

10597 23:00:04.658847  <6>[    1.564259] tun: Universal TUN/TAP device driver, 1.6

10598 23:00:04.662127  <6>[    1.570306] thunder_xcv, ver 1.0

10599 23:00:04.665258  <6>[    1.573810] thunder_bgx, ver 1.0

10600 23:00:04.669011  <6>[    1.577304] nicpf, ver 1.0

10601 23:00:04.679167  <6>[    1.581313] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version

10602 23:00:04.682825  <6>[    1.588788] hns3: Copyright (c) 2017 Huawei Corporation.

10603 23:00:04.689530  <6>[    1.594374] hclge is initializing

10604 23:00:04.692396  <6>[    1.597954] e1000: Intel(R) PRO/1000 Network Driver

10605 23:00:04.699065  <6>[    1.603083] e1000: Copyright (c) 1999-2006 Intel Corporation.

10606 23:00:04.702684  <6>[    1.609096] e1000e: Intel(R) PRO/1000 Network Driver

10607 23:00:04.708814  <6>[    1.614312] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.

10608 23:00:04.715531  <6>[    1.620500] igb: Intel(R) Gigabit Ethernet Network Driver

10609 23:00:04.722141  <6>[    1.626149] igb: Copyright (c) 2007-2014 Intel Corporation.

10610 23:00:04.728828  <6>[    1.631985] igbvf: Intel(R) Gigabit Virtual Function Network Driver

10611 23:00:04.735508  <6>[    1.638503] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.

10612 23:00:04.738993  <6>[    1.644963] sky2: driver version 1.30

10613 23:00:04.745459  <6>[    1.649947] VFIO - User Level meta-driver version: 0.3

10614 23:00:04.753069  <6>[    1.658188] usbcore: registered new interface driver usb-storage

10615 23:00:04.759275  <6>[    1.664631] usbcore: registered new device driver onboard-usb-hub

10616 23:00:04.768554  <6>[    1.673716] mt6397-rtc mt6359-rtc: registered as rtc0

10617 23:00:04.778267  <6>[    1.679195] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T23:00:05 UTC (1686006005)

10618 23:00:04.781918  <6>[    1.688794] i2c_dev: i2c /dev entries driver

10619 23:00:04.798647  <6>[    1.700474] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)

10620 23:00:04.805445  <6>[    1.710654] sdhci: Secure Digital Host Controller Interface driver

10621 23:00:04.812121  <6>[    1.717091] sdhci: Copyright(c) Pierre Ossman

10622 23:00:04.818954  <6>[    1.722482] Synopsys Designware Multimedia Card Interface Driver

10623 23:00:04.821899  <6>[    1.729094] mmc0: CQHCI version 5.10

10624 23:00:04.828450  <6>[    1.729640] sdhci-pltfm: SDHCI platform and OF driver helper

10625 23:00:04.835809  <6>[    1.741313] ledtrig-cpu: registered to indicate activity on CPUs

10626 23:00:04.846449  <6>[    1.748723] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000

10627 23:00:04.850077  <6>[    1.756122] usbcore: registered new interface driver usbhid

10628 23:00:04.856821  <6>[    1.761959] usbhid: USB HID core driver

10629 23:00:04.863500  <6>[    1.766212] spi_master spi0: will run message pump with realtime priority

10630 23:00:04.911282  <6>[    1.809715] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0

10631 23:00:04.919234  <6>[    1.824502] mmc0: Command Queue Engine enabled

10632 23:00:04.925828  <6>[    1.829247] mmc0: new HS400 Enhanced strobe MMC card at address 0001

10633 23:00:04.939162  <6>[    1.836466] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1

10634 23:00:04.945876  <6>[    1.836634] mmcblk0: mmc0:0001 DA4128 116 GiB 

10635 23:00:04.952851  <6>[    1.855754] cros-ec-spi spi0.0: Chrome EC device registered

10636 23:00:04.955896  <6>[    1.859790]  mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12

10637 23:00:04.963947  <6>[    1.869023] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB 

10638 23:00:04.970893  <6>[    1.874971] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB 

10639 23:00:04.977493  <6>[    1.880895] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)

10640 23:00:04.999302  <6>[    1.901035] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)

10641 23:00:05.007042  <6>[    1.912468] NET: Registered PF_PACKET protocol family

10642 23:00:05.010689  <6>[    1.917908] 9pnet: Installing 9P2000 support

10643 23:00:05.017675  <5>[    1.922472] Key type dns_resolver registered

10644 23:00:05.020717  <6>[    1.927683] registered taskstats version 1

10645 23:00:05.026916  <5>[    1.932119] Loading compiled-in X.509 certificates

10646 23:00:05.060576  <4>[    1.959086] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10647 23:00:05.070347  <4>[    1.969790] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10648 23:00:05.080666  <3>[    1.982452] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)

10649 23:00:05.092288  <6>[    1.997911] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102

10650 23:00:05.099555  <6>[    2.004653] xhci-mtk 11200000.usb: xHCI Host Controller

10651 23:00:05.106146  <6>[    2.010148] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1

10652 23:00:05.115804  <6>[    2.018005] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010

10653 23:00:05.122817  <6>[    2.027435] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000

10654 23:00:05.129652  <6>[    2.033631] xhci-mtk 11200000.usb: xHCI Host Controller

10655 23:00:05.135882  <6>[    2.039130] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2

10656 23:00:05.142538  <6>[    2.046797] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed

10657 23:00:05.149218  <6>[    2.054680] hub 1-0:1.0: USB hub found

10658 23:00:05.152768  <6>[    2.058719] hub 1-0:1.0: 1 port detected

10659 23:00:05.162716  <6>[    2.063075] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.

10660 23:00:05.165890  <6>[    2.071872] hub 2-0:1.0: USB hub found

10661 23:00:05.168913  <6>[    2.075906] hub 2-0:1.0: 1 port detected

10662 23:00:05.178032  <6>[    2.083173] mtk-msdc 11f70000.mmc: Got CD GPIO

10663 23:00:05.195329  <6>[    2.097038] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()

10664 23:00:05.201665  <6>[    2.105061] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()

10665 23:00:05.211786  <4>[    2.113036] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW

10666 23:00:05.221410  <6>[    2.122703] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()

10667 23:00:05.228121  <6>[    2.130785] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()

10668 23:00:05.234883  <6>[    2.138812] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()

10669 23:00:05.244512  <6>[    2.146733] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()

10670 23:00:05.251881  <6>[    2.154553] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()

10671 23:00:05.261425  <6>[    2.162373] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39

10672 23:00:05.271343  <6>[    2.173087] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)

10673 23:00:05.278209  <6>[    2.181453] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)

10674 23:00:05.288077  <6>[    2.189798] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)

10675 23:00:05.294828  <6>[    2.198142] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)

10676 23:00:05.304870  <6>[    2.206487] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)

10677 23:00:05.314332  <6>[    2.214830] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)

10678 23:00:05.320829  <6>[    2.223172] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)

10679 23:00:05.330682  <6>[    2.231515] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)

10680 23:00:05.337362  <6>[    2.239858] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)

10681 23:00:05.347499  <6>[    2.248202] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)

10682 23:00:05.354336  <6>[    2.256552] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)

10683 23:00:05.363971  <6>[    2.264895] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)

10684 23:00:05.370828  <6>[    2.273238] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)

10685 23:00:05.380414  <6>[    2.281583] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)

10686 23:00:05.387192  <6>[    2.289931] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)

10687 23:00:05.394044  <6>[    2.298861] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0

10688 23:00:05.400986  <6>[    2.306309] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0

10689 23:00:05.408376  <6>[    2.313342] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0

10690 23:00:05.418180  <6>[    2.320432] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0

10691 23:00:05.425272  <6>[    2.327699] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0

10692 23:00:05.434977  <6>[    2.334606] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)

10693 23:00:05.441836  <6>[    2.343745] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)

10694 23:00:05.451274  <6>[    2.352874] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)

10695 23:00:05.461212  <6>[    2.362176] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)

10696 23:00:05.471344  <6>[    2.371651] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)

10697 23:00:05.481542  <6>[    2.381126] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)

10698 23:00:05.487683  <6>[    2.390253] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)

10699 23:00:05.497879  <6>[    2.399728] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)

10700 23:00:05.507766  <6>[    2.408855] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)

10701 23:00:05.517513  <6>[    2.418156] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing

10702 23:00:05.527628  <6>[    2.428323] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing

10703 23:00:05.538617  <6>[    2.440381] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0

10704 23:00:05.544699  <6>[    2.450181] Trying to probe devices needed for running init ...

10705 23:00:05.559320  <6>[    2.461239] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk

10706 23:00:05.586519  <6>[    2.491774] hub 2-1:1.0: USB hub found

10707 23:00:05.589629  <6>[    2.496170] hub 2-1:1.0: 3 ports detected

10708 23:00:05.710860  <6>[    2.613195] usb 1-1: new high-speed USB device number 2 using xhci-mtk

10709 23:00:05.865267  <6>[    2.770839] hub 1-1:1.0: USB hub found

10710 23:00:05.868786  <6>[    2.775319] hub 1-1:1.0: 4 ports detected

10711 23:00:06.190527  <6>[    3.093085] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk

10712 23:00:06.321950  <6>[    3.227098] hub 1-1.1:1.0: USB hub found

10713 23:00:06.325001  <6>[    3.231378] hub 1-1.1:1.0: 4 ports detected

10714 23:00:06.439268  <6>[    3.341078] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk

10715 23:00:06.571981  <6>[    3.477256] hub 1-1.4:1.0: USB hub found

10716 23:00:06.575135  <6>[    3.481921] hub 1-1.4:1.0: 2 ports detected

10717 23:00:06.655254  <6>[    3.557218] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk

10718 23:00:06.843172  <6>[    3.745214] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk

10719 23:00:06.927902  <3>[    3.833317] usb 1-1.1.4: device descriptor read/64, error -32

10720 23:00:07.120351  <3>[    4.025421] usb 1-1.1.4: device descriptor read/64, error -32

10721 23:00:07.315216  <6>[    4.217215] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk

10722 23:00:07.503034  <6>[    4.405214] usb 1-1.1.4: new full-speed USB device number 8 using xhci-mtk

10723 23:00:07.588153  <3>[    4.493423] usb 1-1.1.4: device descriptor read/64, error -32

10724 23:00:07.780359  <3>[    4.685424] usb 1-1.1.4: device descriptor read/64, error -32

10725 23:00:07.892362  <6>[    4.797782] usb 1-1.1-port4: attempt power cycle

10726 23:00:07.979456  <6>[    4.881246] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk

10727 23:00:08.503121  <6>[    5.405197] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk

10728 23:00:08.509981  <4>[    5.412663] usb 1-1.1.4: Device not responding to setup address.

10729 23:00:08.719810  <4>[    5.625478] usb 1-1.1.4: Device not responding to setup address.

10730 23:00:08.931474  <3>[    5.837206] usb 1-1.1.4: device not accepting address 10, error -71

10731 23:00:09.018932  <6>[    5.921244] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk

10732 23:00:09.025844  <4>[    5.928753] usb 1-1.1.4: Device not responding to setup address.

10733 23:00:09.236055  <4>[    6.141496] usb 1-1.1.4: Device not responding to setup address.

10734 23:00:09.448099  <3>[    6.353203] usb 1-1.1.4: device not accepting address 11, error -71

10735 23:00:09.454676  <3>[    6.360150] usb 1-1.1-port4: unable to enumerate USB device

10736 23:00:17.827441  <6>[   14.737780] ALSA device list:

10737 23:00:17.834109  <6>[   14.741035]   No soundcards found.

10738 23:00:17.846676  <6>[   14.753443] Freeing unused kernel memory: 8384K

10739 23:00:17.849854  <6>[   14.758378] Run /init as init process

10740 23:00:17.860649  Loading, please wait...

10741 23:00:17.878836  Starting version 247.3-7+deb11u2

10742 23:00:18.218680  <6>[   15.121867] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000

10743 23:00:18.226763  <6>[   15.133851] remoteproc remoteproc0: scp is available

10744 23:00:18.236858  <3>[   15.134997] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10745 23:00:18.246681  <4>[   15.139326] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2

10746 23:00:18.253638  <6>[   15.146891] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:

10747 23:00:18.260202  <6>[   15.146917] mtk-pcie-gen3 11230000.pcie:      MEM 0x0012000000..0x00127fffff -> 0x0012000000

10748 23:00:18.270171  <6>[   15.146927] mtk-pcie-gen3 11230000.pcie:       IO 0x0012800000..0x0012ffffff -> 0x0012800000

10749 23:00:18.279672  <3>[   15.148647] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10750 23:00:18.283382  <6>[   15.157212] remoteproc remoteproc0: powering up scp

10751 23:00:18.289729  <4>[   15.161788] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator

10752 23:00:18.299603  <3>[   15.164810] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10753 23:00:18.306449  <4>[   15.170791] elants_i2c 4-0010: supply vccio not found, using dummy regulator

10754 23:00:18.316088  <4>[   15.173611] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2

10755 23:00:18.322755  <3>[   15.197465] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10756 23:00:18.329265  <3>[   15.202693] remoteproc remoteproc0: request_firmware failed: -2

10757 23:00:18.336340  <6>[   15.207725] mc: Linux media interface: v0.10

10758 23:00:18.342329  <3>[   15.210877] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10759 23:00:18.352292  <3>[   15.210896] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10760 23:00:18.359111  <3>[   15.210910] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10761 23:00:18.365833  <6>[   15.226961] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered

10762 23:00:18.375620  <3>[   15.228053] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10763 23:00:18.382047  <6>[   15.238371] videodev: Linux video capture interface: v2.00

10764 23:00:18.388500  <3>[   15.242426] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10765 23:00:18.395604  <6>[   15.243973] usbcore: registered new interface driver r8152

10766 23:00:18.401832  <4>[   15.250290] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.

10767 23:00:18.408732  <4>[   15.250290] Fallback method does not support PEC.

10768 23:00:18.415328  <3>[   15.255076] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10769 23:00:18.421876  <6>[   15.266482] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00

10770 23:00:18.432011  <3>[   15.271185] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10771 23:00:18.438520  <3>[   15.271192] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10772 23:00:18.448744  <3>[   15.271262] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10773 23:00:18.452434  <6>[   15.278907] pci_bus 0000:00: root bus resource [bus 00-ff]

10774 23:00:18.462176  <3>[   15.286938] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10775 23:00:18.468877  <3>[   15.286945] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10776 23:00:18.479053  <3>[   15.286953] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10777 23:00:18.485770  <6>[   15.292706] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]

10778 23:00:18.492426  <3>[   15.300769] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10779 23:00:18.502527  <3>[   15.300804] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10780 23:00:18.512477  <6>[   15.306550] pci_bus 0000:00: root bus resource [io  0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])

10781 23:00:18.518645  <6>[   15.335431] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk

10782 23:00:18.525106  <6>[   15.343566] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400

10783 23:00:18.535097  <6>[   15.344187] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2

10784 23:00:18.545425  <6>[   15.346280] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003

10785 23:00:18.551879  <6>[   15.346571] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3

10786 23:00:18.561822  <3>[   15.359278] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10787 23:00:18.568668  <6>[   15.359475] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]

10788 23:00:18.574673  <6>[   15.365646] usbcore: registered new interface driver cdc_ether

10789 23:00:18.578172  <6>[   15.373379] pci 0000:00:00.0: supports D1 D2

10790 23:00:18.588326  <3>[   15.389537] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10791 23:00:18.591308  <6>[   15.390421] Bluetooth: Core ver 2.22

10792 23:00:18.598103  <6>[   15.390423] usbcore: registered new interface driver r8153_ecm

10793 23:00:18.604490  <6>[   15.390504] NET: Registered PF_BLUETOOTH protocol family

10794 23:00:18.611444  <6>[   15.390508] Bluetooth: HCI device and connection manager initialized

10795 23:00:18.614454  <6>[   15.390547] Bluetooth: HCI socket layer initialized

10796 23:00:18.621202  <6>[   15.390556] Bluetooth: L2CAP socket layer initialized

10797 23:00:18.624388  <6>[   15.390571] Bluetooth: SCO socket layer initialized

10798 23:00:18.634578  <6>[   15.396627] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold

10799 23:00:18.641124  <6>[   15.413846] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)

10800 23:00:18.647655  <6>[   15.424620] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring

10801 23:00:18.661219  <6>[   15.431759] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4

10802 23:00:18.667621  <6>[   15.436439] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000

10803 23:00:18.674292  <6>[   15.437416] usbcore: registered new interface driver btusb

10804 23:00:18.683912  <4>[   15.438178] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2

10805 23:00:18.690979  <3>[   15.438188] Bluetooth: hci0: Failed to load firmware file (-2)

10806 23:00:18.693788  <3>[   15.438191] Bluetooth: hci0: Failed to set up firmware (-2)

10807 23:00:18.707272  <4>[   15.438195] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.

10808 23:00:18.710310  <6>[   15.445886] usbcore: registered new interface driver uvcvideo

10809 23:00:18.720189  <6>[   15.455707] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]

10810 23:00:18.727021  <6>[   15.456439] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0

10811 23:00:18.733732  <4>[   15.460408] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2

10812 23:00:18.743499  <4>[   15.460417] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)

10813 23:00:18.746834  <6>[   15.521125] r8152 1-1.1.1:1.0 eth0: v1.12.13

10814 23:00:18.753336  <6>[   15.522449] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]

10815 23:00:18.759864  <6>[   15.538247] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0

10816 23:00:18.769602  <6>[   15.544870] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]

10817 23:00:18.773289  <6>[   15.680655] pci 0000:01:00.0: supports D1 D2

10818 23:00:18.779410  <6>[   15.685182] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold

10819 23:00:18.797449  <6>[   15.701206] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01

10820 23:00:18.804018  <6>[   15.708125] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]

10821 23:00:18.810548  <6>[   15.716213] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]

10822 23:00:18.820429  <6>[   15.724218] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]

10823 23:00:18.827250  <6>[   15.732225] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]

10824 23:00:18.836974  <6>[   15.740233] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]

10825 23:00:18.840487  <6>[   15.748238] pci 0000:00:00.0: PCI bridge to [bus 01]

10826 23:00:18.850111  <6>[   15.753460] pci 0000:00:00.0:   bridge window [mem 0x12000000-0x121fffff 64bit pref]

10827 23:00:18.856723  <6>[   15.761620] pcieport 0000:00:00.0: enabling device (0000 -> 0002)

10828 23:00:18.863914  <6>[   15.768857] pcieport 0000:00:00.0: PME: Signaling with IRQ 283

10829 23:00:18.869996  <6>[   15.775325] pcieport 0000:00:00.0: AER: enabled with IRQ 283

10830 23:00:18.888689  <5>[   15.792230] cfg80211: Loading compiled-in X.509 certificates for regulatory database

10831 23:00:18.908376  <5>[   15.811708] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'

10832 23:00:18.914807  <4>[   15.818615] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2

10833 23:00:18.921483  <6>[   15.827502] cfg80211: failed to load regulatory.db

10834 23:00:18.967139  <6>[   15.870470] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000

10835 23:00:18.973670  <6>[   15.877984] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)

10836 23:00:18.998135  <6>[   15.904685] mt7921e 0000:01:00.0: ASIC revision: 79610010

10837 23:00:19.104618  <4>[   16.004498] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10838 23:00:19.108087  Begin: Loading essential drivers ... done.

10839 23:00:19.114920  Begin: Running /scripts/init-premount ... done.

10840 23:00:19.121073  Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.

10841 23:00:19.127601  Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available

10842 23:00:19.134549  Device /sys/class/net/enxf4f5e850de0a found

10843 23:00:19.135080  done.

10844 23:00:19.189825  IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP

10845 23:00:19.226893  <4>[   16.127469] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10846 23:00:19.346424  <4>[   16.246876] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10847 23:00:19.462026  <4>[   16.362797] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10848 23:00:19.577884  <4>[   16.478683] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10849 23:00:19.694574  <4>[   16.594622] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10850 23:00:19.810551  <4>[   16.710519] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10851 23:00:19.926300  <4>[   16.826484] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10852 23:00:20.042195  <4>[   16.942387] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10853 23:00:20.158418  <4>[   17.058526] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10854 23:00:20.240654  <6>[   17.147540] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on

10855 23:00:20.265516  <3>[   17.172318] mt7921e 0000:01:00.0: hardware init failed

10856 23:00:20.272140  IP-Config: no response after 2 secs - giving up

10857 23:00:20.317452  IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP

10858 23:00:21.419575  IP-Config: enxf4f5e850de0a complete (dhcp from 192.168.201.1):

10859 23:00:21.426409   address: 192.168.201.14   broadcast: 192.168.201.255  netmask: 255.255.255.0   

10860 23:00:21.432955   gateway: 192.168.201.1    dns0     : 192.168.201.1    dns1   : 0.0.0.0         

10861 23:00:21.439333   host   : mt8192-asurada-spherion-r0-cbg-9                                

10862 23:00:21.446309   domain : lava-rack                                                       

10863 23:00:21.452466   rootserver: 192.168.201.1 rootpath: 

10864 23:00:21.452673   filename  : 

10865 23:00:21.492918  done.

10866 23:00:21.500326  Begin: Running /scripts/nfs-bottom ... done.

10867 23:00:21.519283  Begin: Running /scripts/init-bottom ... done.

10868 23:00:22.623805  <6>[   19.530572] NET: Registered PF_INET6 protocol family

10869 23:00:22.630777  <6>[   19.537342] Segment Routing with IPv6

10870 23:00:22.633311  <6>[   19.541320] In-situ OAM (IOAM) with IPv6

10871 23:00:22.746005  <30>[   19.633498] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)

10872 23:00:22.749032  <30>[   19.657287] systemd[1]: Detected architecture arm64.

10873 23:00:22.769013  

10874 23:00:22.772499  Welcome to Debian GNU/Linux 11 (bullseye)!

10875 23:00:22.772948  

10876 23:00:22.792213  <30>[   19.699304] systemd[1]: Set hostname to <debian-bullseye-arm64>.

10877 23:00:23.310628  <30>[   20.214307] systemd[1]: Queued start job for default target Graphical Interface.

10878 23:00:23.339440  <30>[   20.246159] systemd[1]: Created slice system-getty.slice.

10879 23:00:23.345701  [  OK  ] Created slice system-getty.slice.

10880 23:00:23.363063  <30>[   20.269702] systemd[1]: Created slice system-modprobe.slice.

10881 23:00:23.368816  [  OK  ] Created slice system-modprobe.slice.

10882 23:00:23.386981  <30>[   20.293550] systemd[1]: Created slice system-serial\x2dgetty.slice.

10883 23:00:23.396375  [  OK  ] Created slice system-serial\x2dgetty.slice.

10884 23:00:23.410409  <30>[   20.317568] systemd[1]: Created slice User and Session Slice.

10885 23:00:23.416980  [  OK  ] Created slice User and Session Slice.

10886 23:00:23.437529  <30>[   20.341252] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.

10887 23:00:23.447543  [  OK  ] Started Dispatch Password …ts to Console Directory Watch.

10888 23:00:23.461582  <30>[   20.365139] systemd[1]: Started Forward Password Requests to Wall Directory Watch.

10889 23:00:23.468260  [  OK  ] Started Forward Password R…uests to Wall Directory Watch.

10890 23:00:23.488884  <30>[   20.389123] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.

10891 23:00:23.495117  <30>[   20.401108] systemd[1]: Reached target Local Encrypted Volumes.

10892 23:00:23.501949  [  OK  ] Reached target Local Encrypted Volumes.

10893 23:00:23.518910  <30>[   20.425552] systemd[1]: Reached target Paths.

10894 23:00:23.521699  [  OK  ] Reached target Paths.

10895 23:00:23.537730  <30>[   20.445064] systemd[1]: Reached target Remote File Systems.

10896 23:00:23.544891  [  OK  ] Reached target Remote File Systems.

10897 23:00:23.558328  <30>[   20.465050] systemd[1]: Reached target Slices.

10898 23:00:23.561387  [  OK  ] Reached target Slices.

10899 23:00:23.578553  <30>[   20.485067] systemd[1]: Reached target Swap.

10900 23:00:23.581201  [  OK  ] Reached target Swap.

10901 23:00:23.601841  <30>[   20.505398] systemd[1]: Listening on initctl Compatibility Named Pipe.

10902 23:00:23.608623  [  OK  ] Listening on initctl Compatibility Named Pipe.

10903 23:00:23.624140  <30>[   20.531056] systemd[1]: Listening on Journal Audit Socket.

10904 23:00:23.630832  [  OK  ] Listening on Journal Audit Socket.

10905 23:00:23.647198  <30>[   20.554108] systemd[1]: Listening on Journal Socket (/dev/log).

10906 23:00:23.654280  [  OK  ] Listening on Journal Socket (/dev/log).

10907 23:00:23.671177  <30>[   20.578017] systemd[1]: Listening on Journal Socket.

10908 23:00:23.677739  [  OK  ] Listening on Journal Socket.

10909 23:00:23.694928  <30>[   20.598401] systemd[1]: Listening on Network Service Netlink Socket.

10910 23:00:23.701475  [  OK  ] Listening on Network Service Netlink Socket.

10911 23:00:23.716690  <30>[   20.623532] systemd[1]: Listening on udev Control Socket.

10912 23:00:23.723128  [  OK  ] Listening on udev Control Socket.

10913 23:00:23.738188  <30>[   20.645246] systemd[1]: Listening on udev Kernel Socket.

10914 23:00:23.744311  [  OK  ] Listening on udev Kernel Socket.

10915 23:00:23.770013  <30>[   20.677229] systemd[1]: Mounting Huge Pages File System...

10916 23:00:23.776421           Mounting Huge Pages File System...

10917 23:00:23.791877  <30>[   20.699214] systemd[1]: Mounting POSIX Message Queue File System...

10918 23:00:23.798585           Mounting POSIX Message Queue File System...

10919 23:00:23.816131  <30>[   20.723460] systemd[1]: Mounting Kernel Debug File System...

10920 23:00:23.822784           Mounting Kernel Debug File System...

10921 23:00:23.841570  <30>[   20.745372] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.

10922 23:00:23.894083  <30>[   20.797752] systemd[1]: Starting Create list of static device nodes for the current kernel...

10923 23:00:23.900676           Starting Create list of st…odes for the current kernel...

10924 23:00:23.920612  <30>[   20.827801] systemd[1]: Starting Load Kernel Module configfs...

10925 23:00:23.927430           Starting Load Kernel Module configfs...

10926 23:00:23.944656  <30>[   20.851886] systemd[1]: Starting Load Kernel Module drm...

10927 23:00:23.951286           Starting Load Kernel Module drm...

10928 23:00:23.969139  <30>[   20.875862] systemd[1]: Starting Load Kernel Module fuse...

10929 23:00:23.975228           Starting Load Kernel Module fuse...

10930 23:00:24.004919  <6>[   20.912015] fuse: init (API version 7.37)

10931 23:00:24.014863  <30>[   20.912528] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.

10932 23:00:24.023333  <30>[   20.930103] systemd[1]: Starting Journal Service...

10933 23:00:24.026661           Starting Journal Service...

10934 23:00:24.050160  <30>[   20.957458] systemd[1]: Starting Load Kernel Modules...

10935 23:00:24.056685           Starting Load Kernel Modules...

10936 23:00:24.076373  <30>[   20.980163] systemd[1]: Starting Remount Root and Kernel File Systems...

10937 23:00:24.083159           Starting Remount Root and Kernel File Systems...

10938 23:00:24.102171  <30>[   21.009051] systemd[1]: Starting Coldplug All udev Devices...

10939 23:00:24.108651           Starting Coldplug All udev Devices...

10940 23:00:24.125344  <30>[   21.032432] systemd[1]: Mounted Huge Pages File System.

10941 23:00:24.132046  [  OK  ] Mounted Huge Pages File System.

10942 23:00:24.146176  <30>[   21.053660] systemd[1]: Mounted POSIX Message Queue File System.

10943 23:00:24.152831  [  OK  ] Mounted POSIX Message Queue File System.

10944 23:00:24.169999  <30>[   21.077546] systemd[1]: Mounted Kernel Debug File System.

10945 23:00:24.176842  [  OK  ] Mounted Kernel Debug File System.

10946 23:00:24.188077  <3>[   21.091658] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10947 23:00:24.198320  <30>[   21.102155] systemd[1]: Finished Create list of static device nodes for the current kernel.

10948 23:00:24.207813  [  OK  ] Finished Create list of st… nodes for the current kernel.

10949 23:00:24.223875  <3>[   21.128047] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10950 23:00:24.231136  <30>[   21.138058] systemd[1]: modprobe@configfs.service: Succeeded.

10951 23:00:24.237433  <30>[   21.144768] systemd[1]: Finished Load Kernel Module configfs.

10952 23:00:24.243668  [  OK  ] Finished Load Kernel Module configfs.

10953 23:00:24.259656  <30>[   21.166489] systemd[1]: modprobe@drm.service: Succeeded.

10954 23:00:24.265765  <30>[   21.172712] systemd[1]: Finished Load Kernel Module drm.

10955 23:00:24.276436  <3>[   21.173862] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10956 23:00:24.282625  [  OK  ] Finished Load Kernel Module drm.

10957 23:00:24.300081  <30>[   21.206181] systemd[1]: modprobe@fuse.service: Succeeded.

10958 23:00:24.309261  <3>[   21.211228] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10959 23:00:24.313061  <30>[   21.212477] systemd[1]: Finished Load Kernel Module fuse.

10960 23:00:24.319541  [  OK  ] Finished Load Kernel Module fuse.

10961 23:00:24.334893  <30>[   21.242270] systemd[1]: Finished Load Kernel Modules.

10962 23:00:24.345320  <3>[   21.245682] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10963 23:00:24.351355  [  OK  ] Finished Load Kernel Modules.

10964 23:00:24.364179  <30>[   21.270880] systemd[1]: Finished Remount Root and Kernel File Systems.

10965 23:00:24.381630  [  OK  ] Finished Remount Root and Kernel Fi<3>[   21.282635] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10966 23:00:24.382236  le Systems.

10967 23:00:24.413252  <3>[   21.317102] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10968 23:00:24.430349  <30>[   21.337358] systemd[1]: Mounting FUSE Control File System...

10969 23:00:24.436995           Mounting FUSE Control File System...

10970 23:00:24.448460  <3>[   21.352253] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10971 23:00:24.460471  <30>[   21.364207] systemd[1]: Mounting Kernel Configuration File System...

10972 23:00:24.463508           Mounting Kernel Configuration File System...

10973 23:00:24.481984  <3>[   21.386053] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10974 23:00:24.494771  <30>[   21.398981] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.

10975 23:00:24.504644  <30>[   21.408285] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.

10976 23:00:24.533251  <3>[   21.437161] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10977 23:00:24.540004  <30>[   21.441457] systemd[1]: Starting Load/Save Random Seed...

10978 23:00:24.543056           Starting Load/Save Random Seed...

10979 23:00:24.561214  <30>[   21.468401] systemd[1]: Starting Apply Kernel Variables...

10980 23:00:24.568317           Starting Apply Kernel Variables...

10981 23:00:24.586030  <30>[   21.493389] systemd[1]: Starting Create System Users...

10982 23:00:24.592304           Starting Create System Users...

10983 23:00:24.608324  <30>[   21.515928] systemd[1]: Mounted FUSE Control File System.

10984 23:00:24.615063  [  OK  ] Mounted FUSE Control File System.

10985 23:00:24.629886  <30>[   21.537440] systemd[1]: Started Journal Service.

10986 23:00:24.636923  [  OK  ] Started Journal Service.

10987 23:00:24.651423  [  OK  ] Mounted Kernel Configuration File System.

10988 23:00:24.675821  <4>[   21.573363] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent

10989 23:00:24.685730  <3>[   21.589047] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5

10990 23:00:24.688910  [  OK  ] Finished Load/Save Random Seed.

10991 23:00:24.711446  [FAILED] Failed to start Coldplug All udev Devices.

10992 23:00:24.725819  See 'systemctl status systemd-udev-trigger.service' for details.

10993 23:00:24.743458  [  OK  ] Finished Apply Kernel Variables.

10994 23:00:24.758766  [  OK  ] Finished Create System Users.

10995 23:00:24.795102           Starting Flush Journal to Persistent Storage...

10996 23:00:24.812236           Starting Create Static Device Nodes in /dev...

10997 23:00:24.855318  <46>[   21.759046] systemd-journald[292]: Received client request to flush runtime journal.

10998 23:00:25.609291  [  OK  ] Finished Create Static Device Nodes in /dev.

10999 23:00:25.621745  [  OK  ] Reached target Local File Systems (Pre).

11000 23:00:25.637438  [  OK  ] Reached target Local File Systems.

11001 23:00:25.681331           Starting Rule-based Manage…for Device Events and Files...

11002 23:00:26.244704  [  OK  ] Finished Flush Journal to Persistent Storage.

11003 23:00:26.290834           Starting Create Volatile Files and Directories...

11004 23:00:26.311083  [  OK  ] Started Rule-based Manager for Device Events and Files.

11005 23:00:26.334882           Starting Network Service...

11006 23:00:26.669362  [  OK  ] Found device /dev/ttyS0.

11007 23:00:26.691608  [  OK  ] Created slice system-systemd\x2dbacklight.slice.

11008 23:00:26.733791           Starting Load/Save Screen …of leds:white:kbd_backlight...

11009 23:00:26.897840  <6>[   23.805671] remoteproc remoteproc0: powering up scp

11010 23:00:26.922081  <4>[   23.826828] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2

11011 23:00:26.929088  <3>[   23.836759] remoteproc remoteproc0: request_firmware failed: -2

11012 23:00:26.938701  <3>[   23.842959] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!

11013 23:00:27.037120  [  OK  ] Finished Load/Save Screen …s of leds:white:kbd_backlight.

11014 23:00:27.049759  [  OK  ] Started Network Service.

11015 23:00:27.088438  [  OK  ] Finished Create Volatile Files and Directories.

11016 23:00:27.119269  [  OK  ] Reached target Bluetooth.

11017 23:00:27.136882  [  OK  ] Listening on Load/Save RF …itch Status /dev/rfkill Watch.

11018 23:00:27.182089           Starting Network Name Resolution...

11019 23:00:27.205470           Starting Network Time Synchronization...

11020 23:00:27.224158           Starting Update UTMP about System Boot/Shutdown...

11021 23:00:27.246012           Starting Load/Save RF Kill Switch Status...

11022 23:00:27.276828  [  OK  ] Finished Update UTMP about System Boot/Shutdown.

11023 23:00:27.329976  [  OK  ] Started Load/Save RF Kill Switch Status.

11024 23:00:27.439032  [  OK  ] Started Network Time Synchronization.

11025 23:00:27.454002  [  OK  ] Reached target System Initialization.

11026 23:00:27.473168  [  OK  ] Started Daily Cleanup of Temporary Directories.

11027 23:00:27.485368  [  OK  ] Reached target System Time Set.

11028 23:00:27.501476  [  OK  ] Reached target System Time Synchronized.

11029 23:00:27.613604  [  OK  ] Started Daily apt download activities.

11030 23:00:27.666688  [  OK  ] Started Daily apt upgrade and clean activities.

11031 23:00:27.692711  [  OK  ] Started Periodic ext4 Onli…ata Check for All Filesystems.

11032 23:00:28.245522  [  OK  ] Started Discard unused blocks once a week.

11033 23:00:28.261838  [  OK  ] Reached target Timers.

11034 23:00:28.424186  [  OK  ] Listening on D-Bus System Message Bus Socket.

11035 23:00:28.437821  [  OK  ] Reached target Sockets.

11036 23:00:28.453663  [  OK  ] Reached target Basic System.

11037 23:00:28.486038  [  OK  ] Started D-Bus System Message Bus.

11038 23:00:28.821373           Starting Remove Stale Onli…t4 Metadata Check Snapshots...

11039 23:00:28.870249           Starting User Login Management...

11040 23:00:28.890568  [  OK  ] Started Network Name Resolution.

11041 23:00:28.910985  [  OK  ] Reached target Network.

11042 23:00:28.932522  [  OK  ] Reached target Host and Network Name Lookups.

11043 23:00:28.981554           Starting Permit User Sessions...

11044 23:00:29.078493  [  OK  ] Finished Permit User Sessions.

11045 23:00:29.118544  [  OK  ] Started Getty on tty1.

11046 23:00:29.140188  [  OK  ] Started Serial Getty on ttyS0.

11047 23:00:29.159410  [  OK  ] Reached target Login Prompts.

11048 23:00:29.178972  [  OK  ] Finished Remove Stale Onli…ext4 Metadata Check Snapshots.

11049 23:00:29.199503  [  OK  ] Started User Login Management.

11050 23:00:29.219516  [  OK  ] Reached target Multi-User System.

11051 23:00:29.234118  [  OK  ] Reached target Graphical Interface.

11052 23:00:29.273323           Starting Update UTMP about System Runlevel Changes...

11053 23:00:29.310791  [  OK  ] Finished Update UTMP about System Runlevel Changes.

11054 23:00:29.377285  

11055 23:00:29.377889  

11056 23:00:29.380823  Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0

11057 23:00:29.381314  

11058 23:00:29.383814  debian-bullseye-arm64 login: root (automatic login)

11059 23:00:29.384310  

11060 23:00:29.384783  

11061 23:00:29.706493  Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun  5 22:41:02 UTC 2023 aarch64

11062 23:00:29.706659  

11063 23:00:29.712911  The programs included with the Debian GNU/Linux system are free software;

11064 23:00:29.719600  the exact distribution terms for each program are described in the

11065 23:00:29.723042  individual files in /usr/share/doc/*/copyright.

11066 23:00:29.723166  

11067 23:00:29.729991  Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent

11068 23:00:29.732845  permitted by applicable law.

11069 23:00:30.467900  Matched prompt #10: / #
11071 23:00:30.468179  Setting prompt string to ['/ #']
11072 23:00:30.468276  end: 2.2.5.1 login-action (duration 00:00:28) [common]
11074 23:00:30.468598  end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11075 23:00:30.468691  start: 2.2.6 expect-shell-connection (timeout 00:03:38) [common]
11076 23:00:30.468766  Setting prompt string to ['/ #']
11077 23:00:30.468828  Forcing a shell prompt, looking for ['/ #']
11079 23:00:30.519097  / # 

11080 23:00:30.519293  expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11081 23:00:30.519404  Waiting using forced prompt support (timeout 00:02:30)
11082 23:00:30.524318  

11083 23:00:30.524708  end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11084 23:00:30.524874  start: 2.2.7 export-device-env (timeout 00:03:38) [common]
11086 23:00:30.625481  / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10597704/extract-nfsrootfs-9szzfhg_'

11087 23:00:30.631553  export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10597704/extract-nfsrootfs-9szzfhg_'

11089 23:00:30.733082  / # export NFS_SERVER_IP='192.168.201.1'

11090 23:00:30.739317  export NFS_SERVER_IP='192.168.201.1'

11091 23:00:30.740328  end: 2.2.7 export-device-env (duration 00:00:00) [common]
11092 23:00:30.740904  end: 2.2 depthcharge-retry (duration 00:01:22) [common]
11093 23:00:30.741455  end: 2 depthcharge-action (duration 00:01:22) [common]
11094 23:00:30.741983  start: 3 lava-test-retry (timeout 00:07:56) [common]
11095 23:00:30.742641  start: 3.1 lava-test-shell (timeout 00:07:56) [common]
11096 23:00:30.743124  Using namespace: common
11098 23:00:30.844367  / # #

11099 23:00:30.845067  lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11100 23:00:30.850757  #

11101 23:00:30.851601  Using /lava-10597704
11103 23:00:30.952688  / # export SHELL=/bin/bash

11104 23:00:30.958868  export SHELL=/bin/bash

11106 23:00:31.060213  / # . /lava-10597704/environment

11107 23:00:31.066273  . /lava-10597704/environment

11109 23:00:31.171744  / # /lava-10597704/bin/lava-test-runner /lava-10597704/0

11110 23:00:31.172152  Test shell timeout: 10s (minimum of the action and connection timeout)
11111 23:00:31.177987  /lava-10597704/bin/lava-test-runner /lava-10597704/0

11112 23:00:31.386741  + export TESTRUN_ID=0_timesync-off

11113 23:00:31.390267  + TESTRUN_ID=0_timesync-off

11114 23:00:31.393588  + cd /lava-10597704/0/tests/0_timesync-off

11115 23:00:31.397071  ++ cat uuid

11116 23:00:31.397205  + UUID=10597704_1.6.2.3.1

11117 23:00:31.400257  + set +x

11118 23:00:31.403286  <LAVA_SIGNAL_STARTRUN 0_timesync-off 10597704_1.6.2.3.1>

11119 23:00:31.403572  Received signal: <STARTRUN> 0_timesync-off 10597704_1.6.2.3.1
11120 23:00:31.403676  Starting test lava.0_timesync-off (10597704_1.6.2.3.1)
11121 23:00:31.403799  Skipping test definition patterns.
11122 23:00:31.406425  + systemctl stop systemd-timesyncd

11123 23:00:31.429262  + set +x

11124 23:00:31.432842  <LAVA_SIGNAL_ENDRUN 0_timesync-off 10597704_1.6.2.3.1>

11125 23:00:31.433129  Received signal: <ENDRUN> 0_timesync-off 10597704_1.6.2.3.1
11126 23:00:31.433251  Ending use of test pattern.
11127 23:00:31.433346  Ending test lava.0_timesync-off (10597704_1.6.2.3.1), duration 0.03
11129 23:00:31.479571  + export TESTRUN_ID=1_kselftest-rtc

11130 23:00:31.483528  + TESTRUN_ID=1_kselftest-rtc

11131 23:00:31.486520  + cd /lava-10597704/0/tests/1_kselftest-rtc

11132 23:00:31.489512  ++ cat uuid

11133 23:00:31.489596  + UUID=10597704_1.6.2.3.5

11134 23:00:31.493217  + set +x

11135 23:00:31.496100  <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 10597704_1.6.2.3.5>

11136 23:00:31.496384  Received signal: <STARTRUN> 1_kselftest-rtc 10597704_1.6.2.3.5
11137 23:00:31.496480  Starting test lava.1_kselftest-rtc (10597704_1.6.2.3.5)
11138 23:00:31.496625  Skipping test definition patterns.
11139 23:00:31.499123  + cd ./automated/linux/kselftest/

11140 23:00:31.525553  + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1

11141 23:00:31.543712  INFO: install_deps skipped

11142 23:00:31.643959  --2023-06-05 23:00:31--  http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz

11143 23:00:31.650106  Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28

11144 23:00:31.788366  Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.

11145 23:00:31.934273  HTTP request sent, awaiting response... 200 OK

11146 23:00:31.937212  Length: 2703120 (2.6M) [application/octet-stream]

11147 23:00:31.940391  Saving to: 'kselftest.tar.xz'

11148 23:00:31.940909  

11149 23:00:31.941358  

11150 23:00:32.238776  kselftest.tar.xz      0%[                    ]       0  --.-KB/s               

11151 23:00:32.529233  kselftest.tar.xz      1%[                    ]  46.39K   153KB/s               

11152 23:00:32.820731  kselftest.tar.xz      8%[>                   ] 217.50K   366KB/s               

11153 23:00:33.164720  kselftest.tar.xz     33%[=====>              ] 896.25K  1012KB/s               

11154 23:00:33.171302  kselftest.tar.xz     48%[========>           ]   1.24M  1.01MB/s               

11155 23:00:33.178110  kselftest.tar.xz    100%[===================>]   2.58M  2.08MB/s    in 1.2s    

11156 23:00:33.178204  

11157 23:00:33.412451  2023-06-05 23:00:33 (2.08 MB/s) - 'kselftest.tar.xz' saved [2703120/2703120]

11158 23:00:33.412629  

11159 23:00:38.054408  skiplist:

11160 23:00:38.057438  ========================================

11161 23:00:38.060420  ========================================

11162 23:00:38.094289  rtc:rtctest

11163 23:00:38.108906  ============== Tests to run ===============

11164 23:00:38.109025  rtc:rtctest

11165 23:00:38.112601  ===========End Tests to run ===============

11166 23:00:38.183601  <12>[   35.092767] kselftest: Running tests in rtc

11167 23:00:38.190947  TAP version 13

11168 23:00:38.201610  1..1

11169 23:00:38.224717  # selftests: rtc: rtctest

11170 23:00:38.571591  # TAP version 13

11171 23:00:38.571722  # 1..8

11172 23:00:38.575266  # # Starting 8 tests from 2 test cases.

11173 23:00:38.578424  # #  RUN           rtc.date_read ...

11174 23:00:38.584710  # # rtctest.c:49:date_read:Current RTC date/time is 05/06/2023 23:00:38.

11175 23:00:38.587980  # #            OK  rtc.date_read

11176 23:00:38.591692  # ok 1 rtc.date_read

11177 23:00:38.594891  # #  RUN           rtc.date_read_loop ...

11178 23:00:38.604425  # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).

11179 23:00:49.247264  <6>[   46.161197] vpu: disabling

11180 23:00:49.250815  <6>[   46.164249] vproc2: disabling

11181 23:00:49.254453  <6>[   46.167520] vproc1: disabling

11182 23:00:49.257782  <6>[   46.170781] vaud18: disabling

11183 23:00:49.263790  <6>[   46.174185] vsram_others: disabling

11184 23:00:49.267422  <6>[   46.178059] va09: disabling

11185 23:00:49.270225  <6>[   46.181164] vsram_md: disabling

11186 23:00:49.273804  <6>[   46.184648] Vgpu: disabling

11187 23:01:09.021506  # # rtctest.c:115:date_read_loop:Performed 2725 RTC time reads.

11188 23:01:09.024468  # #            OK  rtc.date_read_loop

11189 23:01:09.027776  # ok 2 rtc.date_read_loop

11190 23:01:09.031435  # #  RUN           rtc.uie_read ...

11191 23:01:11.999078  # #            OK  rtc.uie_read

11192 23:01:12.002586  # ok 3 rtc.uie_read

11193 23:01:12.005726  # #  RUN           rtc.uie_select ...

11194 23:01:14.999341  # #            OK  rtc.uie_select

11195 23:01:15.002205  # ok 4 rtc.uie_select

11196 23:01:15.005611  # #  RUN           rtc.alarm_alm_set ...

11197 23:01:15.012831  # # rtctest.c:202:alarm_alm_set:Alarm time now set to 23:01:18.

11198 23:01:15.015600  # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)

11199 23:01:15.022456  # # alarm_alm_set: Test terminated by assertion

11200 23:01:15.025371  # #          FAIL  rtc.alarm_alm_set

11201 23:01:15.028710  # not ok 5 rtc.alarm_alm_set

11202 23:01:15.032101  # #  RUN           rtc.alarm_wkalm_set ...

11203 23:01:15.038982  # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 05/06/2023 23:01:18.

11204 23:01:18.002380  # #            OK  rtc.alarm_wkalm_set

11205 23:01:18.002916  # ok 6 rtc.alarm_wkalm_set

11206 23:01:18.008397  # #  RUN           rtc.alarm_alm_set_minute ...

11207 23:01:18.011696  # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 23:02:00.

11208 23:01:18.018611  # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)

11209 23:01:18.025271  # # alarm_alm_set_minute: Test terminated by assertion

11210 23:01:18.028583  # #          FAIL  rtc.alarm_alm_set_minute

11211 23:01:18.031621  # not ok 7 rtc.alarm_alm_set_minute

11212 23:01:18.034484  # #  RUN           rtc.alarm_wkalm_set_minute ...

11213 23:01:18.041717  # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 05/06/2023 23:02:00.

11214 23:01:59.996765  # #            OK  rtc.alarm_wkalm_set_minute

11215 23:01:59.999727  # ok 8 rtc.alarm_wkalm_set_minute

11216 23:02:00.003358  # # FAILED: 6 / 8 tests passed.

11217 23:02:00.006710  # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0

11218 23:02:00.009368  not ok 1 selftests: rtc: rtctest # exit=1

11219 23:02:00.498857  rtc_rtctest_rtc_date_read pass

11220 23:02:00.502293  rtc_rtctest_rtc_date_read_loop pass

11221 23:02:00.505334  rtc_rtctest_rtc_uie_read pass

11222 23:02:00.508519  rtc_rtctest_rtc_uie_select pass

11223 23:02:00.512239  rtc_rtctest_rtc_alarm_alm_set fail

11224 23:02:00.515222  rtc_rtctest_rtc_alarm_wkalm_set pass

11225 23:02:00.518877  rtc_rtctest_rtc_alarm_alm_set_minute fail

11226 23:02:00.521814  rtc_rtctest_rtc_alarm_wkalm_set_minute pass

11227 23:02:00.525659  rtc_rtctest fail

11228 23:02:00.528618  + ../../utils/send-to-lava.sh ./output/result.txt

11229 23:02:00.570560  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>

11230 23:02:00.570847  Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11232 23:02:00.623432  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>

11233 23:02:00.623720  Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11235 23:02:00.666056  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>

11236 23:02:00.666332  Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11238 23:02:00.713757  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>

11239 23:02:00.714045  Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11241 23:02:00.760123  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>

11242 23:02:00.760484  Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11244 23:02:00.796145  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>

11245 23:02:00.796557  Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11247 23:02:00.835632  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>

11248 23:02:00.835986  Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11250 23:02:00.867887  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>

11251 23:02:00.868243  Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11253 23:02:00.901661  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>

11254 23:02:00.901839  + set +x

11255 23:02:00.902124  Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11257 23:02:00.907839  <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 10597704_1.6.2.3.5>

11258 23:02:00.908100  Received signal: <ENDRUN> 1_kselftest-rtc 10597704_1.6.2.3.5
11259 23:02:00.908204  Ending use of test pattern.
11260 23:02:00.908299  Ending test lava.1_kselftest-rtc (10597704_1.6.2.3.5), duration 89.41
11262 23:02:00.908666  ok: lava_test_shell seems to have completed
11263 23:02:00.908887  rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass

11264 23:02:00.909016  end: 3.1 lava-test-shell (duration 00:01:30) [common]
11265 23:02:00.909136  end: 3 lava-test-retry (duration 00:01:30) [common]
11266 23:02:00.909258  start: 4 finalize (timeout 00:06:26) [common]
11267 23:02:00.909377  start: 4.1 power-off (timeout 00:00:30) [common]
11268 23:02:00.909602  Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11269 23:02:00.985870  >> Command sent successfully.

11270 23:02:00.988713  Returned 0 in 0 seconds
11271 23:02:01.089182  end: 4.1 power-off (duration 00:00:00) [common]
11273 23:02:01.089537  start: 4.2 read-feedback (timeout 00:06:26) [common]
11275 23:02:01.090109  Listened to connection for namespace 'common' for up to 1s
11276 23:02:02.090766  Finalising connection for namespace 'common'
11277 23:02:02.090958  Disconnecting from shell: Finalise
11278 23:02:02.091039  / # 
11279 23:02:02.191385  end: 4.2 read-feedback (duration 00:00:01) [common]
11280 23:02:02.191567  end: 4 finalize (duration 00:00:01) [common]
11281 23:02:02.191688  Cleaning after the job
11282 23:02:02.191785  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597704/tftp-deploy-2k1f8v8j/ramdisk
11283 23:02:02.194061  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597704/tftp-deploy-2k1f8v8j/kernel
11284 23:02:02.202732  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597704/tftp-deploy-2k1f8v8j/dtb
11285 23:02:02.203000  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597704/tftp-deploy-2k1f8v8j/nfsrootfs
11286 23:02:02.267479  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597704/tftp-deploy-2k1f8v8j/modules
11287 23:02:02.272855  Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10597704
11288 23:02:02.800346  Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10597704
11289 23:02:02.800556  Job finished correctly