Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 38
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 31
1 22:58:08.814373 lava-dispatcher, installed at version: 2023.05.1
2 22:58:08.814591 start: 0 validate
3 22:58:08.814720 Start time: 2023-06-05 22:58:08.814711+00:00 (UTC)
4 22:58:08.814855 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:58:08.814988 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 22:58:09.126430 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:58:09.127176 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:58:09.411025 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:58:09.411802 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:58:09.700140 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:58:09.700916 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 22:58:09.990181 Using caching service: 'http://localhost/cache/?uri=%s'
13 22:58:09.990643 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 22:58:10.280162 validate duration: 1.47
16 22:58:10.281380 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:58:10.281881 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:58:10.282350 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:58:10.283214 Not decompressing ramdisk as can be used compressed.
20 22:58:10.283718 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230527.0/arm64/initrd.cpio.gz
21 22:58:10.284070 saving as /var/lib/lava/dispatcher/tmp/10597675/tftp-deploy-5qtcemid/ramdisk/initrd.cpio.gz
22 22:58:10.284393 total size: 4665273 (4MB)
23 22:58:10.289301 progress 0% (0MB)
24 22:58:10.296692 progress 5% (0MB)
25 22:58:10.301294 progress 10% (0MB)
26 22:58:10.304905 progress 15% (0MB)
27 22:58:10.308092 progress 20% (0MB)
28 22:58:10.310771 progress 25% (1MB)
29 22:58:10.313272 progress 30% (1MB)
30 22:58:10.315486 progress 35% (1MB)
31 22:58:10.317653 progress 40% (1MB)
32 22:58:10.319838 progress 45% (2MB)
33 22:58:10.321729 progress 50% (2MB)
34 22:58:10.323475 progress 55% (2MB)
35 22:58:10.325150 progress 60% (2MB)
36 22:58:10.326831 progress 65% (2MB)
37 22:58:10.328380 progress 70% (3MB)
38 22:58:10.329895 progress 75% (3MB)
39 22:58:10.331384 progress 80% (3MB)
40 22:58:10.333010 progress 85% (3MB)
41 22:58:10.334400 progress 90% (4MB)
42 22:58:10.335778 progress 95% (4MB)
43 22:58:10.337205 progress 100% (4MB)
44 22:58:10.337364 4MB downloaded in 0.05s (83.98MB/s)
45 22:58:10.337521 end: 1.1.1 http-download (duration 00:00:00) [common]
47 22:58:10.337768 end: 1.1 download-retry (duration 00:00:00) [common]
48 22:58:10.337859 start: 1.2 download-retry (timeout 00:10:00) [common]
49 22:58:10.337945 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 22:58:10.338127 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 22:58:10.338203 saving as /var/lib/lava/dispatcher/tmp/10597675/tftp-deploy-5qtcemid/kernel/Image
52 22:58:10.338267 total size: 45746688 (43MB)
53 22:58:10.338329 No compression specified
54 22:58:10.339427 progress 0% (0MB)
55 22:58:10.350868 progress 5% (2MB)
56 22:58:10.362454 progress 10% (4MB)
57 22:58:10.373951 progress 15% (6MB)
58 22:58:10.385499 progress 20% (8MB)
59 22:58:10.396972 progress 25% (10MB)
60 22:58:10.408303 progress 30% (13MB)
61 22:58:10.419798 progress 35% (15MB)
62 22:58:10.431255 progress 40% (17MB)
63 22:58:10.443002 progress 45% (19MB)
64 22:58:10.454614 progress 50% (21MB)
65 22:58:10.466087 progress 55% (24MB)
66 22:58:10.477659 progress 60% (26MB)
67 22:58:10.489207 progress 65% (28MB)
68 22:58:10.500729 progress 70% (30MB)
69 22:58:10.512204 progress 75% (32MB)
70 22:58:10.523540 progress 80% (34MB)
71 22:58:10.535004 progress 85% (37MB)
72 22:58:10.546658 progress 90% (39MB)
73 22:58:10.558061 progress 95% (41MB)
74 22:58:10.569404 progress 100% (43MB)
75 22:58:10.569544 43MB downloaded in 0.23s (188.64MB/s)
76 22:58:10.569696 end: 1.2.1 http-download (duration 00:00:00) [common]
78 22:58:10.569930 end: 1.2 download-retry (duration 00:00:00) [common]
79 22:58:10.570019 start: 1.3 download-retry (timeout 00:10:00) [common]
80 22:58:10.570109 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 22:58:10.570289 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 22:58:10.570362 saving as /var/lib/lava/dispatcher/tmp/10597675/tftp-deploy-5qtcemid/dtb/mt8192-asurada-spherion-r0.dtb
83 22:58:10.570428 total size: 46924 (0MB)
84 22:58:10.570490 No compression specified
85 22:58:10.571656 progress 69% (0MB)
86 22:58:10.571927 progress 100% (0MB)
87 22:58:10.572082 0MB downloaded in 0.00s (27.11MB/s)
88 22:58:10.572203 end: 1.3.1 http-download (duration 00:00:00) [common]
90 22:58:10.572426 end: 1.3 download-retry (duration 00:00:00) [common]
91 22:58:10.572512 start: 1.4 download-retry (timeout 00:10:00) [common]
92 22:58:10.572596 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 22:58:10.572753 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230527.0/arm64/full.rootfs.tar.xz
94 22:58:10.572823 saving as /var/lib/lava/dispatcher/tmp/10597675/tftp-deploy-5qtcemid/nfsrootfs/full.rootfs.tar
95 22:58:10.572884 total size: 89386020 (85MB)
96 22:58:10.572948 Using unxz to decompress xz
97 22:58:10.576513 progress 0% (0MB)
98 22:58:10.785711 progress 5% (4MB)
99 22:58:11.000315 progress 10% (8MB)
100 22:58:11.250099 progress 15% (12MB)
101 22:58:11.441303 progress 20% (17MB)
102 22:58:11.534117 progress 25% (21MB)
103 22:58:11.779977 progress 30% (25MB)
104 22:58:12.059180 progress 35% (29MB)
105 22:58:12.317802 progress 40% (34MB)
106 22:58:12.572681 progress 45% (38MB)
107 22:58:12.820031 progress 50% (42MB)
108 22:58:13.090800 progress 55% (46MB)
109 22:58:13.423476 progress 60% (51MB)
110 22:58:13.695507 progress 65% (55MB)
111 22:58:14.007310 progress 70% (59MB)
112 22:58:14.323505 progress 75% (63MB)
113 22:58:14.627869 progress 80% (68MB)
114 22:58:14.885759 progress 85% (72MB)
115 22:58:15.117269 progress 90% (76MB)
116 22:58:15.375243 progress 95% (81MB)
117 22:58:15.641127 progress 100% (85MB)
118 22:58:15.647333 85MB downloaded in 5.07s (16.80MB/s)
119 22:58:15.647660 end: 1.4.1 http-download (duration 00:00:05) [common]
121 22:58:15.647931 end: 1.4 download-retry (duration 00:00:05) [common]
122 22:58:15.648025 start: 1.5 download-retry (timeout 00:09:55) [common]
123 22:58:15.648117 start: 1.5.1 http-download (timeout 00:09:55) [common]
124 22:58:15.648300 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 22:58:15.648375 saving as /var/lib/lava/dispatcher/tmp/10597675/tftp-deploy-5qtcemid/modules/modules.tar
126 22:58:15.648439 total size: 8552396 (8MB)
127 22:58:15.648506 Using unxz to decompress xz
128 22:58:15.652075 progress 0% (0MB)
129 22:58:15.673200 progress 5% (0MB)
130 22:58:15.697149 progress 10% (0MB)
131 22:58:15.728012 progress 15% (1MB)
132 22:58:15.753873 progress 20% (1MB)
133 22:58:15.778826 progress 25% (2MB)
134 22:58:15.803970 progress 30% (2MB)
135 22:58:15.830136 progress 35% (2MB)
136 22:58:15.855212 progress 40% (3MB)
137 22:58:15.880592 progress 45% (3MB)
138 22:58:15.905492 progress 50% (4MB)
139 22:58:15.929819 progress 55% (4MB)
140 22:58:15.953573 progress 60% (4MB)
141 22:58:15.978673 progress 65% (5MB)
142 22:58:16.004254 progress 70% (5MB)
143 22:58:16.029013 progress 75% (6MB)
144 22:58:16.056453 progress 80% (6MB)
145 22:58:16.082282 progress 85% (6MB)
146 22:58:16.107236 progress 90% (7MB)
147 22:58:16.131052 progress 95% (7MB)
148 22:58:16.155906 progress 100% (8MB)
149 22:58:16.162514 8MB downloaded in 0.51s (15.87MB/s)
150 22:58:16.162794 end: 1.5.1 http-download (duration 00:00:01) [common]
152 22:58:16.163069 end: 1.5 download-retry (duration 00:00:01) [common]
153 22:58:16.163166 start: 1.6 prepare-tftp-overlay (timeout 00:09:54) [common]
154 22:58:16.163265 start: 1.6.1 extract-nfsrootfs (timeout 00:09:54) [common]
155 22:58:17.833157 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10597675/extract-nfsrootfs-rk96f8r0
156 22:58:17.833380 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 22:58:17.833513 start: 1.6.2 lava-overlay (timeout 00:09:52) [common]
158 22:58:17.833758 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10597675/lava-overlay-89og4d_1
159 22:58:17.833997 makedir: /var/lib/lava/dispatcher/tmp/10597675/lava-overlay-89og4d_1/lava-10597675/bin
160 22:58:17.834171 makedir: /var/lib/lava/dispatcher/tmp/10597675/lava-overlay-89og4d_1/lava-10597675/tests
161 22:58:17.834342 makedir: /var/lib/lava/dispatcher/tmp/10597675/lava-overlay-89og4d_1/lava-10597675/results
162 22:58:17.834477 Creating /var/lib/lava/dispatcher/tmp/10597675/lava-overlay-89og4d_1/lava-10597675/bin/lava-add-keys
163 22:58:17.834625 Creating /var/lib/lava/dispatcher/tmp/10597675/lava-overlay-89og4d_1/lava-10597675/bin/lava-add-sources
164 22:58:17.834755 Creating /var/lib/lava/dispatcher/tmp/10597675/lava-overlay-89og4d_1/lava-10597675/bin/lava-background-process-start
165 22:58:17.834883 Creating /var/lib/lava/dispatcher/tmp/10597675/lava-overlay-89og4d_1/lava-10597675/bin/lava-background-process-stop
166 22:58:17.835028 Creating /var/lib/lava/dispatcher/tmp/10597675/lava-overlay-89og4d_1/lava-10597675/bin/lava-common-functions
167 22:58:17.835189 Creating /var/lib/lava/dispatcher/tmp/10597675/lava-overlay-89og4d_1/lava-10597675/bin/lava-echo-ipv4
168 22:58:17.835349 Creating /var/lib/lava/dispatcher/tmp/10597675/lava-overlay-89og4d_1/lava-10597675/bin/lava-install-packages
169 22:58:17.835479 Creating /var/lib/lava/dispatcher/tmp/10597675/lava-overlay-89og4d_1/lava-10597675/bin/lava-installed-packages
170 22:58:17.835602 Creating /var/lib/lava/dispatcher/tmp/10597675/lava-overlay-89og4d_1/lava-10597675/bin/lava-os-build
171 22:58:17.835727 Creating /var/lib/lava/dispatcher/tmp/10597675/lava-overlay-89og4d_1/lava-10597675/bin/lava-probe-channel
172 22:58:17.835851 Creating /var/lib/lava/dispatcher/tmp/10597675/lava-overlay-89og4d_1/lava-10597675/bin/lava-probe-ip
173 22:58:17.835977 Creating /var/lib/lava/dispatcher/tmp/10597675/lava-overlay-89og4d_1/lava-10597675/bin/lava-target-ip
174 22:58:17.836103 Creating /var/lib/lava/dispatcher/tmp/10597675/lava-overlay-89og4d_1/lava-10597675/bin/lava-target-mac
175 22:58:17.836226 Creating /var/lib/lava/dispatcher/tmp/10597675/lava-overlay-89og4d_1/lava-10597675/bin/lava-target-storage
176 22:58:17.836353 Creating /var/lib/lava/dispatcher/tmp/10597675/lava-overlay-89og4d_1/lava-10597675/bin/lava-test-case
177 22:58:17.836475 Creating /var/lib/lava/dispatcher/tmp/10597675/lava-overlay-89og4d_1/lava-10597675/bin/lava-test-event
178 22:58:17.836612 Creating /var/lib/lava/dispatcher/tmp/10597675/lava-overlay-89og4d_1/lava-10597675/bin/lava-test-feedback
179 22:58:17.836767 Creating /var/lib/lava/dispatcher/tmp/10597675/lava-overlay-89og4d_1/lava-10597675/bin/lava-test-raise
180 22:58:17.836924 Creating /var/lib/lava/dispatcher/tmp/10597675/lava-overlay-89og4d_1/lava-10597675/bin/lava-test-reference
181 22:58:17.837080 Creating /var/lib/lava/dispatcher/tmp/10597675/lava-overlay-89og4d_1/lava-10597675/bin/lava-test-runner
182 22:58:17.837238 Creating /var/lib/lava/dispatcher/tmp/10597675/lava-overlay-89og4d_1/lava-10597675/bin/lava-test-set
183 22:58:17.837400 Creating /var/lib/lava/dispatcher/tmp/10597675/lava-overlay-89og4d_1/lava-10597675/bin/lava-test-shell
184 22:58:17.837558 Updating /var/lib/lava/dispatcher/tmp/10597675/lava-overlay-89og4d_1/lava-10597675/bin/lava-install-packages (oe)
185 22:58:18.278835 Updating /var/lib/lava/dispatcher/tmp/10597675/lava-overlay-89og4d_1/lava-10597675/bin/lava-installed-packages (oe)
186 22:58:18.279071 Creating /var/lib/lava/dispatcher/tmp/10597675/lava-overlay-89og4d_1/lava-10597675/environment
187 22:58:18.279215 LAVA metadata
188 22:58:18.279321 - LAVA_JOB_ID=10597675
189 22:58:18.279458 - LAVA_DISPATCHER_IP=192.168.201.1
190 22:58:18.279613 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:52) [common]
191 22:58:18.279717 skipped lava-vland-overlay
192 22:58:18.279829 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 22:58:18.279944 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:52) [common]
194 22:58:18.280036 skipped lava-multinode-overlay
195 22:58:18.280141 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 22:58:18.280259 start: 1.6.2.3 test-definition (timeout 00:09:52) [common]
197 22:58:18.280369 Loading test definitions
198 22:58:18.280501 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:52) [common]
199 22:58:18.280604 Using /lava-10597675 at stage 0
200 22:58:18.281158 uuid=10597675_1.6.2.3.1 testdef=None
201 22:58:18.281280 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 22:58:18.281399 start: 1.6.2.3.2 test-overlay (timeout 00:09:52) [common]
203 22:58:18.282086 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 22:58:18.282340 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:52) [common]
206 22:58:18.283032 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 22:58:18.283425 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:52) [common]
209 22:58:18.968131 runner path: /var/lib/lava/dispatcher/tmp/10597675/lava-overlay-89og4d_1/lava-10597675/0/tests/0_lc-compliance test_uuid 10597675_1.6.2.3.1
210 22:58:18.968363 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:01) [common]
212 22:58:18.968608 Creating lava-test-runner.conf files
213 22:58:18.968675 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10597675/lava-overlay-89og4d_1/lava-10597675/0 for stage 0
214 22:58:18.968783 - 0_lc-compliance
215 22:58:18.968900 end: 1.6.2.3 test-definition (duration 00:00:01) [common]
216 22:58:18.968989 start: 1.6.2.4 compress-overlay (timeout 00:09:51) [common]
217 22:58:19.097633 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 22:58:19.097823 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:51) [common]
219 22:58:19.097948 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 22:58:19.098076 end: 1.6.2 lava-overlay (duration 00:00:01) [common]
221 22:58:19.098209 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:51) [common]
222 22:58:19.218581 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 22:58:19.218974 start: 1.6.4 extract-modules (timeout 00:09:51) [common]
224 22:58:19.219113 extracting modules file /var/lib/lava/dispatcher/tmp/10597675/tftp-deploy-5qtcemid/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597675/extract-nfsrootfs-rk96f8r0
225 22:58:19.489091 extracting modules file /var/lib/lava/dispatcher/tmp/10597675/tftp-deploy-5qtcemid/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597675/extract-overlay-ramdisk-c4jd945y/ramdisk
226 22:58:19.758763 end: 1.6.4 extract-modules (duration 00:00:01) [common]
227 22:58:19.758922 start: 1.6.5 apply-overlay-tftp (timeout 00:09:51) [common]
228 22:58:19.759017 [common] Applying overlay to NFS
229 22:58:19.759103 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597675/compress-overlay-of2mel0j/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10597675/extract-nfsrootfs-rk96f8r0
230 22:58:19.766007 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 22:58:19.766121 start: 1.6.6 configure-preseed-file (timeout 00:09:51) [common]
232 22:58:19.766231 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 22:58:19.766324 start: 1.6.7 compress-ramdisk (timeout 00:09:51) [common]
234 22:58:19.766404 Building ramdisk /var/lib/lava/dispatcher/tmp/10597675/extract-overlay-ramdisk-c4jd945y/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10597675/extract-overlay-ramdisk-c4jd945y/ramdisk
235 22:58:20.339126 >> 117807 blocks
236 22:58:22.298036 rename /var/lib/lava/dispatcher/tmp/10597675/extract-overlay-ramdisk-c4jd945y/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10597675/tftp-deploy-5qtcemid/ramdisk/ramdisk.cpio.gz
237 22:58:22.298459 end: 1.6.7 compress-ramdisk (duration 00:00:03) [common]
238 22:58:22.298581 start: 1.6.8 prepare-kernel (timeout 00:09:48) [common]
239 22:58:22.298683 start: 1.6.8.1 prepare-fit (timeout 00:09:48) [common]
240 22:58:22.298788 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10597675/tftp-deploy-5qtcemid/kernel/Image'
241 22:58:35.760727 Returned 0 in 13 seconds
242 22:58:35.861375 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10597675/tftp-deploy-5qtcemid/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10597675/tftp-deploy-5qtcemid/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10597675/tftp-deploy-5qtcemid/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10597675/tftp-deploy-5qtcemid/kernel/image.itb
243 22:58:36.509850 output: FIT description: Kernel Image image with one or more FDT blobs
244 22:58:36.510196 output: Created: Mon Jun 5 23:58:36 2023
245 22:58:36.510273 output: Image 0 (kernel-1)
246 22:58:36.510355 output: Description:
247 22:58:36.510425 output: Created: Mon Jun 5 23:58:36 2023
248 22:58:36.510490 output: Type: Kernel Image
249 22:58:36.510558 output: Compression: lzma compressed
250 22:58:36.510621 output: Data Size: 10085945 Bytes = 9849.56 KiB = 9.62 MiB
251 22:58:36.510697 output: Architecture: AArch64
252 22:58:36.510770 output: OS: Linux
253 22:58:36.510829 output: Load Address: 0x00000000
254 22:58:36.510887 output: Entry Point: 0x00000000
255 22:58:36.510945 output: Hash algo: crc32
256 22:58:36.511001 output: Hash value: b2943ff2
257 22:58:36.511056 output: Image 1 (fdt-1)
258 22:58:36.511111 output: Description: mt8192-asurada-spherion-r0
259 22:58:36.511166 output: Created: Mon Jun 5 23:58:36 2023
260 22:58:36.511221 output: Type: Flat Device Tree
261 22:58:36.511276 output: Compression: uncompressed
262 22:58:36.511356 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
263 22:58:36.511430 output: Architecture: AArch64
264 22:58:36.511484 output: Hash algo: crc32
265 22:58:36.511538 output: Hash value: 1df858fa
266 22:58:36.511593 output: Image 2 (ramdisk-1)
267 22:58:36.511646 output: Description: unavailable
268 22:58:36.511700 output: Created: Mon Jun 5 23:58:36 2023
269 22:58:36.511755 output: Type: RAMDisk Image
270 22:58:36.511809 output: Compression: Unknown Compression
271 22:58:36.511863 output: Data Size: 17642277 Bytes = 17228.79 KiB = 16.82 MiB
272 22:58:36.511918 output: Architecture: AArch64
273 22:58:36.511972 output: OS: Linux
274 22:58:36.512026 output: Load Address: unavailable
275 22:58:36.512080 output: Entry Point: unavailable
276 22:58:36.512134 output: Hash algo: crc32
277 22:58:36.512188 output: Hash value: a127d813
278 22:58:36.512241 output: Default Configuration: 'conf-1'
279 22:58:36.512295 output: Configuration 0 (conf-1)
280 22:58:36.512348 output: Description: mt8192-asurada-spherion-r0
281 22:58:36.512403 output: Kernel: kernel-1
282 22:58:36.512457 output: Init Ramdisk: ramdisk-1
283 22:58:36.512511 output: FDT: fdt-1
284 22:58:36.512565 output: Loadables: kernel-1
285 22:58:36.512619 output:
286 22:58:36.512815 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
287 22:58:36.512917 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
288 22:58:36.513022 end: 1.6 prepare-tftp-overlay (duration 00:00:20) [common]
289 22:58:36.513113 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:34) [common]
290 22:58:36.513193 No LXC device requested
291 22:58:36.513275 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 22:58:36.513359 start: 1.8 deploy-device-env (timeout 00:09:34) [common]
293 22:58:36.513466 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 22:58:36.513600 Checking files for TFTP limit of 4294967296 bytes.
295 22:58:36.514148 end: 1 tftp-deploy (duration 00:00:26) [common]
296 22:58:36.514252 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 22:58:36.514348 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 22:58:36.514472 substitutions:
299 22:58:36.514539 - {DTB}: 10597675/tftp-deploy-5qtcemid/dtb/mt8192-asurada-spherion-r0.dtb
300 22:58:36.514631 - {INITRD}: 10597675/tftp-deploy-5qtcemid/ramdisk/ramdisk.cpio.gz
301 22:58:36.514706 - {KERNEL}: 10597675/tftp-deploy-5qtcemid/kernel/Image
302 22:58:36.514765 - {LAVA_MAC}: None
303 22:58:36.514824 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10597675/extract-nfsrootfs-rk96f8r0
304 22:58:36.514880 - {NFS_SERVER_IP}: 192.168.201.1
305 22:58:36.514935 - {PRESEED_CONFIG}: None
306 22:58:36.514991 - {PRESEED_LOCAL}: None
307 22:58:36.515046 - {RAMDISK}: 10597675/tftp-deploy-5qtcemid/ramdisk/ramdisk.cpio.gz
308 22:58:36.515101 - {ROOT_PART}: None
309 22:58:36.515157 - {ROOT}: None
310 22:58:36.515213 - {SERVER_IP}: 192.168.201.1
311 22:58:36.515269 - {TEE}: None
312 22:58:36.515347 Parsed boot commands:
313 22:58:36.515474 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 22:58:36.515654 Parsed boot commands: tftpboot 192.168.201.1 10597675/tftp-deploy-5qtcemid/kernel/image.itb 10597675/tftp-deploy-5qtcemid/kernel/cmdline
315 22:58:36.515744 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 22:58:36.515835 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 22:58:36.515927 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 22:58:36.516015 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 22:58:36.516085 Not connected, no need to disconnect.
320 22:58:36.516160 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 22:58:36.516240 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 22:58:36.516308 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-0'
323 22:58:36.519493 Setting prompt string to ['lava-test: # ']
324 22:58:36.519845 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 22:58:36.519955 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 22:58:36.520051 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 22:58:36.520147 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 22:58:36.520359 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
329 22:58:41.660372 >> Command sent successfully.
330 22:58:41.670681 Returned 0 in 5 seconds
331 22:58:41.771879 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 22:58:41.773335 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 22:58:41.773857 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 22:58:41.774304 Setting prompt string to 'Starting depthcharge on Spherion...'
336 22:58:41.774687 Changing prompt to 'Starting depthcharge on Spherion...'
337 22:58:41.775056 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 22:58:41.776449 [Enter `^Ec?' for help]
339 22:58:41.937267
340 22:58:41.937804
341 22:58:41.938163 F0: 102B 0000
342 22:58:41.938507
343 22:58:41.938820 F3: 1001 0000 [0200]
344 22:58:41.939284
345 22:58:41.941515 F3: 1001 0000
346 22:58:41.941950
347 22:58:41.942377 F7: 102D 0000
348 22:58:41.942780
349 22:58:41.943102 F1: 0000 0000
350 22:58:41.943459
351 22:58:41.944911 V0: 0000 0000 [0001]
352 22:58:41.945361
353 22:58:41.945707 00: 0007 8000
354 22:58:41.946163
355 22:58:41.948636 01: 0000 0000
356 22:58:41.949079
357 22:58:41.949425 BP: 0C00 0209 [0000]
358 22:58:41.949775
359 22:58:41.950237 G0: 1182 0000
360 22:58:41.950569
361 22:58:41.952537 EC: 0000 0021 [4000]
362 22:58:41.952995
363 22:58:41.953485 S7: 0000 0000 [0000]
364 22:58:41.953826
365 22:58:41.956383 CC: 0000 0000 [0001]
366 22:58:41.956818
367 22:58:41.957314 T0: 0000 0040 [010F]
368 22:58:41.959870
369 22:58:41.960306 Jump to BL
370 22:58:41.960756
371 22:58:41.984143
372 22:58:41.984628
373 22:58:41.984977
374 22:58:41.991370 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
375 22:58:41.995360 ARM64: Exception handlers installed.
376 22:58:41.999315 ARM64: Testing exception
377 22:58:42.002720 ARM64: Done test exception
378 22:58:42.010074 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
379 22:58:42.017027 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
380 22:58:42.024263 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
381 22:58:42.035014 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
382 22:58:42.041209 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
383 22:58:42.052274 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
384 22:58:42.062658 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
385 22:58:42.069732 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
386 22:58:42.086950 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
387 22:58:42.090484 WDT: Last reset was cold boot
388 22:58:42.094090 SPI1(PAD0) initialized at 2873684 Hz
389 22:58:42.097436 SPI5(PAD0) initialized at 992727 Hz
390 22:58:42.100307 VBOOT: Loading verstage.
391 22:58:42.106965 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
392 22:58:42.110236 FMAP: Found "FLASH" version 1.1 at 0x20000.
393 22:58:42.113606 FMAP: base = 0x0 size = 0x800000 #areas = 25
394 22:58:42.116872 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
395 22:58:42.124017 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
396 22:58:42.131035 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
397 22:58:42.141893 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
398 22:58:42.142029
399 22:58:42.142124
400 22:58:42.152982 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
401 22:58:42.156022 ARM64: Exception handlers installed.
402 22:58:42.156116 ARM64: Testing exception
403 22:58:42.159727 ARM64: Done test exception
404 22:58:42.162818 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
405 22:58:42.169221 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
406 22:58:42.182696 Probing TPM: . done!
407 22:58:42.182792 TPM ready after 0 ms
408 22:58:42.190087 Connected to device vid:did:rid of 1ae0:0028:00
409 22:58:42.197528 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
410 22:58:42.256876 Initialized TPM device CR50 revision 0
411 22:58:42.269010 tlcl_send_startup: Startup return code is 0
412 22:58:42.269121 TPM: setup succeeded
413 22:58:42.280131 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
414 22:58:42.288853 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 22:58:42.301542 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
416 22:58:42.312310 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
417 22:58:42.315852 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
418 22:58:42.319230 in-header: 03 07 00 00 08 00 00 00
419 22:58:42.322580 in-data: aa e4 47 04 13 02 00 00
420 22:58:42.322668 Chrome EC: UHEPI supported
421 22:58:42.329867 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
422 22:58:42.333979 in-header: 03 95 00 00 08 00 00 00
423 22:58:42.338036 in-data: 18 20 20 08 00 00 00 00
424 22:58:42.338122 Phase 1
425 22:58:42.341906 FMAP: area GBB found @ 3f5000 (12032 bytes)
426 22:58:42.349121 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
427 22:58:42.356658 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
428 22:58:42.356753 Recovery requested (1009000e)
429 22:58:42.368672 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 22:58:42.372482 tlcl_extend: response is 0
431 22:58:42.381885 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 22:58:42.387074 tlcl_extend: response is 0
433 22:58:42.393834 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 22:58:42.413851 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
435 22:58:42.420513 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 22:58:42.420641
437 22:58:42.420740
438 22:58:42.429935 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 22:58:42.433394 ARM64: Exception handlers installed.
440 22:58:42.436893 ARM64: Testing exception
441 22:58:42.437018 ARM64: Done test exception
442 22:58:42.459188 pmic_efuse_setting: Set efuses in 11 msecs
443 22:58:42.462394 pmwrap_interface_init: Select PMIF_VLD_RDY
444 22:58:42.469560 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 22:58:42.472763 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 22:58:42.476542 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 22:58:42.484164 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 22:58:42.487854 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 22:58:42.491775 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 22:58:42.498588 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 22:58:42.503202 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 22:58:42.506574 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 22:58:42.509890 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 22:58:42.517973 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 22:58:42.521307 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 22:58:42.525226 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 22:58:42.532703 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 22:58:42.536134 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 22:58:42.542984 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 22:58:42.550424 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 22:58:42.554417 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 22:58:42.562240 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 22:58:42.565508 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 22:58:42.573065 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 22:58:42.576880 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 22:58:42.583862 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 22:58:42.587629 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 22:58:42.591643 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 22:58:42.598710 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 22:58:42.602242 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 22:58:42.609635 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 22:58:42.613203 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 22:58:42.617122 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 22:58:42.624849 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 22:58:42.628054 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 22:58:42.631910 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 22:58:42.639398 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 22:58:42.643173 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 22:58:42.647154 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 22:58:42.654581 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 22:58:42.657942 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 22:58:42.661863 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 22:58:42.668902 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 22:58:42.871768 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 22:58:42.872495 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 22:58:42.873063 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 22:58:42.873655 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 22:58:42.874237 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 22:58:42.874814 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 22:58:42.875425 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 22:58:42.876023 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 22:58:42.876623 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 22:58:42.877207 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 22:58:42.877778 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 22:58:42.878346 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
496 22:58:42.878923 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 22:58:42.879535 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 22:58:42.880098 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 22:58:42.880604 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 22:58:42.881177 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 22:58:42.881774 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 22:58:42.882343 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 22:58:42.882908 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
504 22:58:42.883506 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 22:58:42.884052 [RTC]rtc_osc_init,62: osc32con val = 0xde70
506 22:58:42.884628 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 22:58:42.885186 [RTC]rtc_get_frequency_meter,154: input=15, output=759
508 22:58:42.885759 [RTC]rtc_get_frequency_meter,154: input=23, output=942
509 22:58:42.886328 [RTC]rtc_get_frequency_meter,154: input=19, output=851
510 22:58:42.886934 [RTC]rtc_get_frequency_meter,154: input=17, output=805
511 22:58:42.887534 [RTC]rtc_get_frequency_meter,154: input=16, output=782
512 22:58:42.888064 [RTC]rtc_get_frequency_meter,154: input=16, output=782
513 22:58:42.888498 [RTC]rtc_get_frequency_meter,154: input=17, output=803
514 22:58:42.889057 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
515 22:58:42.889635 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
516 22:58:42.890199 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
517 22:58:42.919535 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
518 22:58:42.919745 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
519 22:58:42.919873 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
520 22:58:42.919992 ADC[4]: Raw value=906203 ID=7
521 22:58:42.920104 ADC[3]: Raw value=213441 ID=1
522 22:58:42.920214 RAM Code: 0x71
523 22:58:42.920322 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
524 22:58:42.920429 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
525 22:58:42.920751 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
526 22:58:42.920875 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
527 22:58:42.920986 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
528 22:58:42.921095 in-header: 03 07 00 00 08 00 00 00
529 22:58:42.921262 in-data: aa e4 47 04 13 02 00 00
530 22:58:42.925407 Chrome EC: UHEPI supported
531 22:58:42.932770 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
532 22:58:42.936035 in-header: 03 95 00 00 08 00 00 00
533 22:58:42.940044 in-data: 18 20 20 08 00 00 00 00
534 22:58:42.943364 MRC: failed to locate region type 0.
535 22:58:42.947606 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
536 22:58:42.950853 DRAM-K: Running full calibration
537 22:58:42.958021 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
538 22:58:42.958143 header.status = 0x0
539 22:58:42.961805 header.version = 0x6 (expected: 0x6)
540 22:58:42.965267 header.size = 0xd00 (expected: 0xd00)
541 22:58:42.969304 header.flags = 0x0
542 22:58:42.972587 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
543 22:58:42.992232 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
544 22:58:42.999973 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
545 22:58:43.000091 dram_init: ddr_geometry: 2
546 22:58:43.003414 [EMI] MDL number = 2
547 22:58:43.007579 [EMI] Get MDL freq = 0
548 22:58:43.007679 dram_init: ddr_type: 0
549 22:58:43.010650 is_discrete_lpddr4: 1
550 22:58:43.010746 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
551 22:58:43.014667
552 22:58:43.014756
553 22:58:43.014824 [Bian_co] ETT version 0.0.0.1
554 22:58:43.018550 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
555 22:58:43.022898
556 22:58:43.023012 dramc_set_vcore_voltage set vcore to 650000
557 22:58:43.026696 Read voltage for 800, 4
558 22:58:43.026810 Vio18 = 0
559 22:58:43.030590 Vcore = 650000
560 22:58:43.030686 Vdram = 0
561 22:58:43.030755 Vddq = 0
562 22:58:43.030861 Vmddr = 0
563 22:58:43.033701 dram_init: config_dvfs: 1
564 22:58:43.037847 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
565 22:58:43.045368 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
566 22:58:43.048790 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
567 22:58:43.052792 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
568 22:58:43.056038 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
569 22:58:43.059320 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
570 22:58:43.062760 MEM_TYPE=3, freq_sel=18
571 22:58:43.066262 sv_algorithm_assistance_LP4_1600
572 22:58:43.069683 ============ PULL DRAM RESETB DOWN ============
573 22:58:43.073142 ========== PULL DRAM RESETB DOWN end =========
574 22:58:43.076965 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
575 22:58:43.081106 ===================================
576 22:58:43.084349 LPDDR4 DRAM CONFIGURATION
577 22:58:43.088426 ===================================
578 22:58:43.088526 EX_ROW_EN[0] = 0x0
579 22:58:43.091664 EX_ROW_EN[1] = 0x0
580 22:58:43.091783 LP4Y_EN = 0x0
581 22:58:43.095699 WORK_FSP = 0x0
582 22:58:43.095916 WL = 0x2
583 22:58:43.098817 RL = 0x2
584 22:58:43.098990 BL = 0x2
585 22:58:43.102672 RPST = 0x0
586 22:58:43.102905 RD_PRE = 0x0
587 22:58:43.105426 WR_PRE = 0x1
588 22:58:43.105679 WR_PST = 0x0
589 22:58:43.109253 DBI_WR = 0x0
590 22:58:43.109533 DBI_RD = 0x0
591 22:58:43.112417 OTF = 0x1
592 22:58:43.115847 ===================================
593 22:58:43.119646 ===================================
594 22:58:43.119938 ANA top config
595 22:58:43.122897 ===================================
596 22:58:43.126652 DLL_ASYNC_EN = 0
597 22:58:43.126990 ALL_SLAVE_EN = 1
598 22:58:43.129861 NEW_RANK_MODE = 1
599 22:58:43.133465 DLL_IDLE_MODE = 1
600 22:58:43.136711 LP45_APHY_COMB_EN = 1
601 22:58:43.139883 TX_ODT_DIS = 1
602 22:58:43.140366 NEW_8X_MODE = 1
603 22:58:43.143465 ===================================
604 22:58:43.146890 ===================================
605 22:58:43.150255 data_rate = 1600
606 22:58:43.153631 CKR = 1
607 22:58:43.156907 DQ_P2S_RATIO = 8
608 22:58:43.160415 ===================================
609 22:58:43.161120 CA_P2S_RATIO = 8
610 22:58:43.163416 DQ_CA_OPEN = 0
611 22:58:43.167372 DQ_SEMI_OPEN = 0
612 22:58:43.170592 CA_SEMI_OPEN = 0
613 22:58:43.173944 CA_FULL_RATE = 0
614 22:58:43.177257 DQ_CKDIV4_EN = 1
615 22:58:43.177914 CA_CKDIV4_EN = 1
616 22:58:43.180578 CA_PREDIV_EN = 0
617 22:58:43.184090 PH8_DLY = 0
618 22:58:43.187409 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
619 22:58:43.190651 DQ_AAMCK_DIV = 4
620 22:58:43.194079 CA_AAMCK_DIV = 4
621 22:58:43.194656 CA_ADMCK_DIV = 4
622 22:58:43.197531 DQ_TRACK_CA_EN = 0
623 22:58:43.200833 CA_PICK = 800
624 22:58:43.204138 CA_MCKIO = 800
625 22:58:43.207971 MCKIO_SEMI = 0
626 22:58:43.211773 PLL_FREQ = 3068
627 22:58:43.212355 DQ_UI_PI_RATIO = 32
628 22:58:43.215116 CA_UI_PI_RATIO = 0
629 22:58:43.218992 ===================================
630 22:58:43.222282 ===================================
631 22:58:43.226398 memory_type:LPDDR4
632 22:58:43.226828 GP_NUM : 10
633 22:58:43.230155 SRAM_EN : 1
634 22:58:43.230614 MD32_EN : 0
635 22:58:43.233901 ===================================
636 22:58:43.237627 [ANA_INIT] >>>>>>>>>>>>>>
637 22:58:43.238060 <<<<<< [CONFIGURE PHASE]: ANA_TX
638 22:58:43.240987 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
639 22:58:43.244290 ===================================
640 22:58:43.247412 data_rate = 1600,PCW = 0X7600
641 22:58:43.251077 ===================================
642 22:58:43.254438 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
643 22:58:43.261286 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 22:58:43.264698 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
645 22:58:43.271040 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
646 22:58:43.274217 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
647 22:58:43.277738 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
648 22:58:43.281020 [ANA_INIT] flow start
649 22:58:43.281462 [ANA_INIT] PLL >>>>>>>>
650 22:58:43.284383 [ANA_INIT] PLL <<<<<<<<
651 22:58:43.287710 [ANA_INIT] MIDPI >>>>>>>>
652 22:58:43.288153 [ANA_INIT] MIDPI <<<<<<<<
653 22:58:43.291077 [ANA_INIT] DLL >>>>>>>>
654 22:58:43.294512 [ANA_INIT] flow end
655 22:58:43.297888 ============ LP4 DIFF to SE enter ============
656 22:58:43.301161 ============ LP4 DIFF to SE exit ============
657 22:58:43.304510 [ANA_INIT] <<<<<<<<<<<<<
658 22:58:43.307887 [Flow] Enable top DCM control >>>>>
659 22:58:43.311200 [Flow] Enable top DCM control <<<<<
660 22:58:43.314263 Enable DLL master slave shuffle
661 22:58:43.318045 ==============================================================
662 22:58:43.321437 Gating Mode config
663 22:58:43.324745 ==============================================================
664 22:58:43.328099 Config description:
665 22:58:43.337794 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
666 22:58:43.344674 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
667 22:58:43.348397 SELPH_MODE 0: By rank 1: By Phase
668 22:58:43.354695 ==============================================================
669 22:58:43.357821 GAT_TRACK_EN = 1
670 22:58:43.361530 RX_GATING_MODE = 2
671 22:58:43.364886 RX_GATING_TRACK_MODE = 2
672 22:58:43.368320 SELPH_MODE = 1
673 22:58:43.368762 PICG_EARLY_EN = 1
674 22:58:43.371050 VALID_LAT_VALUE = 1
675 22:58:43.378499 ==============================================================
676 22:58:43.381414 Enter into Gating configuration >>>>
677 22:58:43.384654 Exit from Gating configuration <<<<
678 22:58:43.387849 Enter into DVFS_PRE_config >>>>>
679 22:58:43.397485 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
680 22:58:43.400745 Exit from DVFS_PRE_config <<<<<
681 22:58:43.404019 Enter into PICG configuration >>>>
682 22:58:43.407306 Exit from PICG configuration <<<<
683 22:58:43.410650 [RX_INPUT] configuration >>>>>
684 22:58:43.414065 [RX_INPUT] configuration <<<<<
685 22:58:43.417221 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
686 22:58:43.424358 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
687 22:58:43.430903 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
688 22:58:43.437652 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
689 22:58:43.444188 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
690 22:58:43.447345 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
691 22:58:43.454278 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
692 22:58:43.457515 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
693 22:58:43.460602 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
694 22:58:43.464412 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
695 22:58:43.467479 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
696 22:58:43.474239 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 22:58:43.477552 ===================================
698 22:58:43.480936 LPDDR4 DRAM CONFIGURATION
699 22:58:43.484172 ===================================
700 22:58:43.484389 EX_ROW_EN[0] = 0x0
701 22:58:43.487591 EX_ROW_EN[1] = 0x0
702 22:58:43.487809 LP4Y_EN = 0x0
703 22:58:43.490644 WORK_FSP = 0x0
704 22:58:43.490834 WL = 0x2
705 22:58:43.494585 RL = 0x2
706 22:58:43.494751 BL = 0x2
707 22:58:43.497979 RPST = 0x0
708 22:58:43.498149 RD_PRE = 0x0
709 22:58:43.500607 WR_PRE = 0x1
710 22:58:43.500760 WR_PST = 0x0
711 22:58:43.503926 DBI_WR = 0x0
712 22:58:43.504087 DBI_RD = 0x0
713 22:58:43.507775 OTF = 0x1
714 22:58:43.511074 ===================================
715 22:58:43.514594 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
716 22:58:43.517813 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
717 22:58:43.524522 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
718 22:58:43.527766 ===================================
719 22:58:43.527848 LPDDR4 DRAM CONFIGURATION
720 22:58:43.531490 ===================================
721 22:58:43.534282 EX_ROW_EN[0] = 0x10
722 22:58:43.534378 EX_ROW_EN[1] = 0x0
723 22:58:43.538147 LP4Y_EN = 0x0
724 22:58:43.538295 WORK_FSP = 0x0
725 22:58:43.541591 WL = 0x2
726 22:58:43.544870 RL = 0x2
727 22:58:43.545018 BL = 0x2
728 22:58:43.548198 RPST = 0x0
729 22:58:43.548278 RD_PRE = 0x0
730 22:58:43.551318 WR_PRE = 0x1
731 22:58:43.551499 WR_PST = 0x0
732 22:58:43.554584 DBI_WR = 0x0
733 22:58:43.554705 DBI_RD = 0x0
734 22:58:43.557652 OTF = 0x1
735 22:58:43.561568 ===================================
736 22:58:43.564688 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
737 22:58:43.569932 nWR fixed to 40
738 22:58:43.573016 [ModeRegInit_LP4] CH0 RK0
739 22:58:43.573102 [ModeRegInit_LP4] CH0 RK1
740 22:58:43.576818 [ModeRegInit_LP4] CH1 RK0
741 22:58:43.580223 [ModeRegInit_LP4] CH1 RK1
742 22:58:43.580309 match AC timing 13
743 22:58:43.586846 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
744 22:58:43.590145 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
745 22:58:43.593488 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
746 22:58:43.599818 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
747 22:58:43.603256 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
748 22:58:43.603399 [EMI DOE] emi_dcm 0
749 22:58:43.609957 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
750 22:58:43.610050 ==
751 22:58:43.613389 Dram Type= 6, Freq= 0, CH_0, rank 0
752 22:58:43.616740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
753 22:58:43.616847 ==
754 22:58:43.623775 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
755 22:58:43.629747 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
756 22:58:43.637667 [CA 0] Center 36 (6~67) winsize 62
757 22:58:43.640755 [CA 1] Center 36 (6~67) winsize 62
758 22:58:43.644442 [CA 2] Center 34 (4~65) winsize 62
759 22:58:43.647621 [CA 3] Center 33 (3~64) winsize 62
760 22:58:43.651023 [CA 4] Center 33 (3~64) winsize 62
761 22:58:43.654395 [CA 5] Center 32 (2~62) winsize 61
762 22:58:43.654691
763 22:58:43.657658 [CmdBusTrainingLP45] Vref(ca) range 1: 34
764 22:58:43.657968
765 22:58:43.660768 [CATrainingPosCal] consider 1 rank data
766 22:58:43.664661 u2DelayCellTimex100 = 270/100 ps
767 22:58:43.668098 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
768 22:58:43.671275 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
769 22:58:43.678236 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
770 22:58:43.681221 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
771 22:58:43.684473 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
772 22:58:43.687857 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
773 22:58:43.688369
774 22:58:43.691128 CA PerBit enable=1, Macro0, CA PI delay=32
775 22:58:43.691672
776 22:58:43.694610 [CBTSetCACLKResult] CA Dly = 32
777 22:58:43.695127 CS Dly: 5 (0~36)
778 22:58:43.695524 ==
779 22:58:43.698001 Dram Type= 6, Freq= 0, CH_0, rank 1
780 22:58:43.704425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 22:58:43.704882 ==
782 22:58:43.707850 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
783 22:58:43.714514 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
784 22:58:43.723975 [CA 0] Center 36 (6~67) winsize 62
785 22:58:43.727475 [CA 1] Center 36 (6~67) winsize 62
786 22:58:43.730694 [CA 2] Center 34 (4~64) winsize 61
787 22:58:43.734068 [CA 3] Center 33 (3~64) winsize 62
788 22:58:43.737459 [CA 4] Center 32 (2~63) winsize 62
789 22:58:43.741027 [CA 5] Center 32 (2~63) winsize 62
790 22:58:43.741589
791 22:58:43.743953 [CmdBusTrainingLP45] Vref(ca) range 1: 32
792 22:58:43.744391
793 22:58:43.747768 [CATrainingPosCal] consider 2 rank data
794 22:58:43.750721 u2DelayCellTimex100 = 270/100 ps
795 22:58:43.754295 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
796 22:58:43.757503 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
797 22:58:43.764091 CA2 delay=34 (4~64),Diff = 2 PI (14 cell)
798 22:58:43.767268 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
799 22:58:43.771308 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
800 22:58:43.774654 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
801 22:58:43.775391
802 22:58:43.777666 CA PerBit enable=1, Macro0, CA PI delay=32
803 22:58:43.778193
804 22:58:43.780854 [CBTSetCACLKResult] CA Dly = 32
805 22:58:43.781293 CS Dly: 5 (0~36)
806 22:58:43.781633
807 22:58:43.784616 ----->DramcWriteLeveling(PI) begin...
808 22:58:43.785058 ==
809 22:58:43.787986 Dram Type= 6, Freq= 0, CH_0, rank 0
810 22:58:43.791647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 22:58:43.792086 ==
812 22:58:43.795444 Write leveling (Byte 0): 33 => 33
813 22:58:43.799087 Write leveling (Byte 1): 32 => 32
814 22:58:43.803188 DramcWriteLeveling(PI) end<-----
815 22:58:43.803710
816 22:58:43.804098 ==
817 22:58:43.805947 Dram Type= 6, Freq= 0, CH_0, rank 0
818 22:58:43.809126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
819 22:58:43.809609 ==
820 22:58:43.813049 [Gating] SW mode calibration
821 22:58:43.821014 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
822 22:58:43.824253 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
823 22:58:43.830441 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
824 22:58:43.833934 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
825 22:58:43.837431 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
826 22:58:43.844042 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
827 22:58:43.847180 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 22:58:43.850516 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 22:58:43.857772 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 22:58:43.860780 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 22:58:43.863954 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 22:58:43.870780 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 22:58:43.873864 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 22:58:43.877714 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 22:58:43.883866 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 22:58:43.887607 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 22:58:43.890636 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 22:58:43.894567 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 22:58:43.900823 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 22:58:43.904022 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
841 22:58:43.907430 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
842 22:58:43.914211 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 22:58:43.917396 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 22:58:43.920647 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 22:58:43.927447 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 22:58:43.930964 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 22:58:43.934141 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 22:58:43.940946 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 22:58:43.944423 0 9 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
850 22:58:43.947838 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
851 22:58:43.954508 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 22:58:43.957840 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 22:58:43.961123 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 22:58:43.964401 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
855 22:58:43.970770 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
856 22:58:43.974097 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
857 22:58:43.977532 0 10 8 | B1->B0 | 3333 2727 | 0 0 | (0 1) (0 0)
858 22:58:43.984082 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 22:58:43.987918 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 22:58:43.991089 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 22:58:43.998043 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 22:58:44.001306 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 22:58:44.004332 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 22:58:44.010816 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
865 22:58:44.014089 0 11 8 | B1->B0 | 2b2b 4040 | 0 1 | (0 0) (0 0)
866 22:58:44.017595 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
867 22:58:44.024190 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 22:58:44.028211 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 22:58:44.031430 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 22:58:44.038146 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 22:58:44.040966 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 22:58:44.044318 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
873 22:58:44.048200 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
874 22:58:44.054323 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
875 22:58:44.058190 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 22:58:44.061612 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 22:58:44.068104 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 22:58:44.071460 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 22:58:44.074845 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 22:58:44.081374 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 22:58:44.084763 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 22:58:44.088078 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 22:58:44.094828 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 22:58:44.098041 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 22:58:44.101733 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 22:58:44.108077 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 22:58:44.111355 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 22:58:44.114588 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
889 22:58:44.117910 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
890 22:58:44.121264 Total UI for P1: 0, mck2ui 16
891 22:58:44.125394 best dqsien dly found for B0: ( 0, 14, 4)
892 22:58:44.131281 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
893 22:58:44.134693 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 22:58:44.138420 Total UI for P1: 0, mck2ui 16
895 22:58:44.141609 best dqsien dly found for B1: ( 0, 14, 10)
896 22:58:44.144869 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
897 22:58:44.148273 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
898 22:58:44.148485
899 22:58:44.151726 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
900 22:58:44.155055 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
901 22:58:44.158321 [Gating] SW calibration Done
902 22:58:44.158493 ==
903 22:58:44.161564 Dram Type= 6, Freq= 0, CH_0, rank 0
904 22:58:44.164933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
905 22:58:44.165095 ==
906 22:58:44.168285 RX Vref Scan: 0
907 22:58:44.168443
908 22:58:44.171597 RX Vref 0 -> 0, step: 1
909 22:58:44.171739
910 22:58:44.171812 RX Delay -130 -> 252, step: 16
911 22:58:44.178858 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
912 22:58:44.181529 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
913 22:58:44.185244 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
914 22:58:44.188612 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
915 22:58:44.192045 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
916 22:58:44.198631 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
917 22:58:44.201676 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
918 22:58:44.205407 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
919 22:58:44.208624 iDelay=222, Bit 8, Center 69 (-34 ~ 173) 208
920 22:58:44.211811 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
921 22:58:44.218920 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
922 22:58:44.222224 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
923 22:58:44.225454 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
924 22:58:44.228769 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
925 22:58:44.232175 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
926 22:58:44.238990 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
927 22:58:44.239159 ==
928 22:58:44.241593 Dram Type= 6, Freq= 0, CH_0, rank 0
929 22:58:44.245396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
930 22:58:44.245557 ==
931 22:58:44.245629 DQS Delay:
932 22:58:44.248717 DQS0 = 0, DQS1 = 0
933 22:58:44.248863 DQM Delay:
934 22:58:44.252086 DQM0 = 89, DQM1 = 81
935 22:58:44.252235 DQ Delay:
936 22:58:44.255390 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
937 22:58:44.258761 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
938 22:58:44.262076 DQ8 =69, DQ9 =77, DQ10 =77, DQ11 =77
939 22:58:44.265321 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
940 22:58:44.265472
941 22:58:44.265541
942 22:58:44.265604 ==
943 22:58:44.268614 Dram Type= 6, Freq= 0, CH_0, rank 0
944 22:58:44.272018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
945 22:58:44.272180 ==
946 22:58:44.272250
947 22:58:44.275361
948 22:58:44.275514 TX Vref Scan disable
949 22:58:44.278650 == TX Byte 0 ==
950 22:58:44.282002 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
951 22:58:44.285313 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
952 22:58:44.288661 == TX Byte 1 ==
953 22:58:44.291814 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
954 22:58:44.295626 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
955 22:58:44.295792 ==
956 22:58:44.298979 Dram Type= 6, Freq= 0, CH_0, rank 0
957 22:58:44.305591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
958 22:58:44.305761 ==
959 22:58:44.316843 TX Vref=22, minBit 8, minWin=27, winSum=445
960 22:58:44.320694 TX Vref=24, minBit 10, minWin=27, winSum=450
961 22:58:44.323858 TX Vref=26, minBit 10, minWin=27, winSum=451
962 22:58:44.326902 TX Vref=28, minBit 11, minWin=27, winSum=456
963 22:58:44.330796 TX Vref=30, minBit 0, minWin=28, winSum=456
964 22:58:44.337173 TX Vref=32, minBit 12, minWin=27, winSum=453
965 22:58:44.340586 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 30
966 22:58:44.340746
967 22:58:44.343891 Final TX Range 1 Vref 30
968 22:58:44.344040
969 22:58:44.344108 ==
970 22:58:44.347135 Dram Type= 6, Freq= 0, CH_0, rank 0
971 22:58:44.350334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
972 22:58:44.350490 ==
973 22:58:44.353486
974 22:58:44.353632
975 22:58:44.353701 TX Vref Scan disable
976 22:58:44.357624 == TX Byte 0 ==
977 22:58:44.360282 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
978 22:58:44.364348 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
979 22:58:44.367503 == TX Byte 1 ==
980 22:58:44.370618 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
981 22:58:44.374049 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
982 22:58:44.377407
983 22:58:44.377571 [DATLAT]
984 22:58:44.377641 Freq=800, CH0 RK0
985 22:58:44.377704
986 22:58:44.380652 DATLAT Default: 0xa
987 22:58:44.380790 0, 0xFFFF, sum = 0
988 22:58:44.383736 1, 0xFFFF, sum = 0
989 22:58:44.383888 2, 0xFFFF, sum = 0
990 22:58:44.387172 3, 0xFFFF, sum = 0
991 22:58:44.387354 4, 0xFFFF, sum = 0
992 22:58:44.390609 5, 0xFFFF, sum = 0
993 22:58:44.390759 6, 0xFFFF, sum = 0
994 22:58:44.394059 7, 0xFFFF, sum = 0
995 22:58:44.394213 8, 0xFFFF, sum = 0
996 22:58:44.397314 9, 0x0, sum = 1
997 22:58:44.397461 10, 0x0, sum = 2
998 22:58:44.400690 11, 0x0, sum = 3
999 22:58:44.400837 12, 0x0, sum = 4
1000 22:58:44.403903 best_step = 10
1001 22:58:44.404049
1002 22:58:44.404117 ==
1003 22:58:44.407305 Dram Type= 6, Freq= 0, CH_0, rank 0
1004 22:58:44.410603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1005 22:58:44.410764 ==
1006 22:58:44.414508 RX Vref Scan: 1
1007 22:58:44.414668
1008 22:58:44.414740 Set Vref Range= 32 -> 127
1009 22:58:44.414804
1010 22:58:44.417666 RX Vref 32 -> 127, step: 1
1011 22:58:44.417808
1012 22:58:44.420459 RX Delay -79 -> 252, step: 8
1013 22:58:44.420591
1014 22:58:44.424497 Set Vref, RX VrefLevel [Byte0]: 32
1015 22:58:44.427616 [Byte1]: 32
1016 22:58:44.427773
1017 22:58:44.430621 Set Vref, RX VrefLevel [Byte0]: 33
1018 22:58:44.434241 [Byte1]: 33
1019 22:58:44.437542
1020 22:58:44.437703 Set Vref, RX VrefLevel [Byte0]: 34
1021 22:58:44.440718 [Byte1]: 34
1022 22:58:44.444796
1023 22:58:44.444959 Set Vref, RX VrefLevel [Byte0]: 35
1024 22:58:44.448841 [Byte1]: 35
1025 22:58:44.452821
1026 22:58:44.452918 Set Vref, RX VrefLevel [Byte0]: 36
1027 22:58:44.456714 [Byte1]: 36
1028 22:58:44.460738
1029 22:58:44.460858 Set Vref, RX VrefLevel [Byte0]: 37
1030 22:58:44.464174 [Byte1]: 37
1031 22:58:44.468238
1032 22:58:44.468331 Set Vref, RX VrefLevel [Byte0]: 38
1033 22:58:44.471674 [Byte1]: 38
1034 22:58:44.475475
1035 22:58:44.475556 Set Vref, RX VrefLevel [Byte0]: 39
1036 22:58:44.478833 [Byte1]: 39
1037 22:58:44.483009
1038 22:58:44.483091 Set Vref, RX VrefLevel [Byte0]: 40
1039 22:58:44.486142 [Byte1]: 40
1040 22:58:44.490098
1041 22:58:44.490180 Set Vref, RX VrefLevel [Byte0]: 41
1042 22:58:44.493452 [Byte1]: 41
1043 22:58:44.497561
1044 22:58:44.497642 Set Vref, RX VrefLevel [Byte0]: 42
1045 22:58:44.500941 [Byte1]: 42
1046 22:58:44.505528
1047 22:58:44.505610 Set Vref, RX VrefLevel [Byte0]: 43
1048 22:58:44.508827 [Byte1]: 43
1049 22:58:44.512698
1050 22:58:44.512780 Set Vref, RX VrefLevel [Byte0]: 44
1051 22:58:44.515950 [Byte1]: 44
1052 22:58:44.520550
1053 22:58:44.520631 Set Vref, RX VrefLevel [Byte0]: 45
1054 22:58:44.523707 [Byte1]: 45
1055 22:58:44.528310
1056 22:58:44.528391 Set Vref, RX VrefLevel [Byte0]: 46
1057 22:58:44.531382 [Byte1]: 46
1058 22:58:44.535651
1059 22:58:44.535732 Set Vref, RX VrefLevel [Byte0]: 47
1060 22:58:44.538869 [Byte1]: 47
1061 22:58:44.543206
1062 22:58:44.543337 Set Vref, RX VrefLevel [Byte0]: 48
1063 22:58:44.546232 [Byte1]: 48
1064 22:58:44.550957
1065 22:58:44.551039 Set Vref, RX VrefLevel [Byte0]: 49
1066 22:58:44.554261 [Byte1]: 49
1067 22:58:44.558305
1068 22:58:44.558413 Set Vref, RX VrefLevel [Byte0]: 50
1069 22:58:44.561654 [Byte1]: 50
1070 22:58:44.566188
1071 22:58:44.566270 Set Vref, RX VrefLevel [Byte0]: 51
1072 22:58:44.568819 [Byte1]: 51
1073 22:58:44.573656
1074 22:58:44.573738 Set Vref, RX VrefLevel [Byte0]: 52
1075 22:58:44.576298 [Byte1]: 52
1076 22:58:44.580961
1077 22:58:44.581043 Set Vref, RX VrefLevel [Byte0]: 53
1078 22:58:44.584484 [Byte1]: 53
1079 22:58:44.588351
1080 22:58:44.588462 Set Vref, RX VrefLevel [Byte0]: 54
1081 22:58:44.591525 [Byte1]: 54
1082 22:58:44.596007
1083 22:58:44.596087 Set Vref, RX VrefLevel [Byte0]: 55
1084 22:58:44.599349 [Byte1]: 55
1085 22:58:44.603466
1086 22:58:44.603547 Set Vref, RX VrefLevel [Byte0]: 56
1087 22:58:44.606879 [Byte1]: 56
1088 22:58:44.610979
1089 22:58:44.611060 Set Vref, RX VrefLevel [Byte0]: 57
1090 22:58:44.614262 [Byte1]: 57
1091 22:58:44.618708
1092 22:58:44.618791 Set Vref, RX VrefLevel [Byte0]: 58
1093 22:58:44.622055 [Byte1]: 58
1094 22:58:44.626212
1095 22:58:44.626293 Set Vref, RX VrefLevel [Byte0]: 59
1096 22:58:44.629662 [Byte1]: 59
1097 22:58:44.633575
1098 22:58:44.633658 Set Vref, RX VrefLevel [Byte0]: 60
1099 22:58:44.636819 [Byte1]: 60
1100 22:58:44.641225
1101 22:58:44.641307 Set Vref, RX VrefLevel [Byte0]: 61
1102 22:58:44.644402 [Byte1]: 61
1103 22:58:44.648782
1104 22:58:44.648863 Set Vref, RX VrefLevel [Byte0]: 62
1105 22:58:44.651867 [Byte1]: 62
1106 22:58:44.656218
1107 22:58:44.656300 Set Vref, RX VrefLevel [Byte0]: 63
1108 22:58:44.659576 [Byte1]: 63
1109 22:58:44.663653
1110 22:58:44.663735 Set Vref, RX VrefLevel [Byte0]: 64
1111 22:58:44.667048 [Byte1]: 64
1112 22:58:44.671468
1113 22:58:44.671549 Set Vref, RX VrefLevel [Byte0]: 65
1114 22:58:44.674963 [Byte1]: 65
1115 22:58:44.678835
1116 22:58:44.678942 Set Vref, RX VrefLevel [Byte0]: 66
1117 22:58:44.682113 [Byte1]: 66
1118 22:58:44.686694
1119 22:58:44.686775 Set Vref, RX VrefLevel [Byte0]: 67
1120 22:58:44.690142 [Byte1]: 67
1121 22:58:44.694098
1122 22:58:44.694208 Set Vref, RX VrefLevel [Byte0]: 68
1123 22:58:44.697447 [Byte1]: 68
1124 22:58:44.701998
1125 22:58:44.702083 Set Vref, RX VrefLevel [Byte0]: 69
1126 22:58:44.704714 [Byte1]: 69
1127 22:58:44.709246
1128 22:58:44.709356 Set Vref, RX VrefLevel [Byte0]: 70
1129 22:58:44.712581 [Byte1]: 70
1130 22:58:44.716678
1131 22:58:44.716766 Set Vref, RX VrefLevel [Byte0]: 71
1132 22:58:44.720064 [Byte1]: 71
1133 22:58:44.724485
1134 22:58:44.724570 Set Vref, RX VrefLevel [Byte0]: 72
1135 22:58:44.727691 [Byte1]: 72
1136 22:58:44.731690
1137 22:58:44.731777 Set Vref, RX VrefLevel [Byte0]: 73
1138 22:58:44.735088 [Byte1]: 73
1139 22:58:44.739191
1140 22:58:44.739277 Set Vref, RX VrefLevel [Byte0]: 74
1141 22:58:44.742495 [Byte1]: 74
1142 22:58:44.746912
1143 22:58:44.746998 Set Vref, RX VrefLevel [Byte0]: 75
1144 22:58:44.750006 [Byte1]: 75
1145 22:58:44.754229
1146 22:58:44.754331 Set Vref, RX VrefLevel [Byte0]: 76
1147 22:58:44.757506 [Byte1]: 76
1148 22:58:44.761861
1149 22:58:44.761946 Final RX Vref Byte 0 = 57 to rank0
1150 22:58:44.765495 Final RX Vref Byte 1 = 62 to rank0
1151 22:58:44.768701 Final RX Vref Byte 0 = 57 to rank1
1152 22:58:44.771998 Final RX Vref Byte 1 = 62 to rank1==
1153 22:58:44.775252 Dram Type= 6, Freq= 0, CH_0, rank 0
1154 22:58:44.782367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1155 22:58:44.782459 ==
1156 22:58:44.782545 DQS Delay:
1157 22:58:44.782629 DQS0 = 0, DQS1 = 0
1158 22:58:44.785653 DQM Delay:
1159 22:58:44.785742 DQM0 = 92, DQM1 = 85
1160 22:58:44.788894 DQ Delay:
1161 22:58:44.788997 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1162 22:58:44.792187 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1163 22:58:44.795520 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =76
1164 22:58:44.798714 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1165 22:58:44.802176
1166 22:58:44.802390
1167 22:58:44.809341 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a40, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1168 22:58:44.812673 CH0 RK0: MR19=606, MR18=4A40
1169 22:58:44.819208 CH0_RK0: MR19=0x606, MR18=0x4A40, DQSOSC=391, MR23=63, INC=96, DEC=64
1170 22:58:44.819369
1171 22:58:44.822611 ----->DramcWriteLeveling(PI) begin...
1172 22:58:44.822700 ==
1173 22:58:44.825859 Dram Type= 6, Freq= 0, CH_0, rank 1
1174 22:58:44.829424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1175 22:58:44.829855 ==
1176 22:58:44.832648 Write leveling (Byte 0): 33 => 33
1177 22:58:44.835943 Write leveling (Byte 1): 29 => 29
1178 22:58:44.839205 DramcWriteLeveling(PI) end<-----
1179 22:58:44.839631
1180 22:58:44.839959 ==
1181 22:58:44.843203 Dram Type= 6, Freq= 0, CH_0, rank 1
1182 22:58:44.846493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1183 22:58:44.846921 ==
1184 22:58:44.849921 [Gating] SW mode calibration
1185 22:58:44.856446 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1186 22:58:44.899771 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1187 22:58:44.900348 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1188 22:58:44.900723 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1189 22:58:44.901430 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1190 22:58:44.901771 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1191 22:58:44.902124 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 22:58:44.902431 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 22:58:44.902743 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 22:58:44.903033 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 22:58:44.903375 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 22:58:44.903841 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 22:58:44.910792 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 22:58:44.913588 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 22:58:44.917514 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 22:58:44.924273 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 22:58:44.926915 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 22:58:44.930388 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 22:58:44.936985 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 22:58:44.940812 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 22:58:44.944167 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1206 22:58:44.950466 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 22:58:44.954301 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 22:58:44.957056 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 22:58:44.964215 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 22:58:44.967415 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 22:58:44.970747 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 22:58:44.977583 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 22:58:44.980617 0 9 8 | B1->B0 | 3131 3030 | 0 1 | (0 0) (1 1)
1214 22:58:44.983804 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1215 22:58:44.986963 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1216 22:58:44.994076 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1217 22:58:44.997487 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1218 22:58:45.000608 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1219 22:58:45.007795 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1220 22:58:45.010966 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1221 22:58:45.014187 0 10 8 | B1->B0 | 2525 2323 | 1 0 | (1 1) (0 0)
1222 22:58:45.020874 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 22:58:45.024217 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 22:58:45.028326 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 22:58:45.031547 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 22:58:45.035443 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 22:58:45.042768 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 22:58:45.046000 0 11 4 | B1->B0 | 2a2a 2424 | 0 0 | (1 1) (0 0)
1229 22:58:45.049969 0 11 8 | B1->B0 | 3d3d 4141 | 0 0 | (0 0) (0 0)
1230 22:58:45.056573 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1231 22:58:45.060644 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1232 22:58:45.063964 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1233 22:58:45.066988 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1234 22:58:45.073629 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 22:58:45.077003 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1236 22:58:45.080743 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1237 22:58:45.083885 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1238 22:58:45.090806 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1239 22:58:45.093853 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1240 22:58:45.097134 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1241 22:58:45.104013 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 22:58:45.107125 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 22:58:45.110919 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 22:58:45.117484 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 22:58:45.120434 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 22:58:45.123822 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 22:58:45.130328 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 22:58:45.133651 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 22:58:45.136849 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 22:58:45.143474 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 22:58:45.146829 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 22:58:45.150134 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 22:58:45.157159 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1254 22:58:45.157293 Total UI for P1: 0, mck2ui 16
1255 22:58:45.160567 best dqsien dly found for B0: ( 0, 14, 6)
1256 22:58:45.166570 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1257 22:58:45.170576 Total UI for P1: 0, mck2ui 16
1258 22:58:45.173765 best dqsien dly found for B1: ( 0, 14, 8)
1259 22:58:45.177306 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1260 22:58:45.179990 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1261 22:58:45.180269
1262 22:58:45.183229 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1263 22:58:45.186594 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1264 22:58:45.190505 [Gating] SW calibration Done
1265 22:58:45.190846 ==
1266 22:58:45.193805 Dram Type= 6, Freq= 0, CH_0, rank 1
1267 22:58:45.197263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1268 22:58:45.197701 ==
1269 22:58:45.200422 RX Vref Scan: 0
1270 22:58:45.201043
1271 22:58:45.203597 RX Vref 0 -> 0, step: 1
1272 22:58:45.204193
1273 22:58:45.204588 RX Delay -130 -> 252, step: 16
1274 22:58:45.210058 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1275 22:58:45.213756 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1276 22:58:45.216997 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1277 22:58:45.220479 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1278 22:58:45.223781 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1279 22:58:45.230178 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1280 22:58:45.233613 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1281 22:58:45.236920 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
1282 22:58:45.240289 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1283 22:58:45.243436 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1284 22:58:45.250166 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1285 22:58:45.253394 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1286 22:58:45.257003 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1287 22:58:45.260712 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1288 22:58:45.263999 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1289 22:58:45.270520 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1290 22:58:45.270963 ==
1291 22:58:45.273814 Dram Type= 6, Freq= 0, CH_0, rank 1
1292 22:58:45.277043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1293 22:58:45.277484 ==
1294 22:58:45.277919 DQS Delay:
1295 22:58:45.280428 DQS0 = 0, DQS1 = 0
1296 22:58:45.280863 DQM Delay:
1297 22:58:45.283761 DQM0 = 93, DQM1 = 82
1298 22:58:45.284285 DQ Delay:
1299 22:58:45.287162 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1300 22:58:45.290371 DQ4 =93, DQ5 =85, DQ6 =101, DQ7 =109
1301 22:58:45.293684 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1302 22:58:45.297006 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1303 22:58:45.297447
1304 22:58:45.297882
1305 22:58:45.298295 ==
1306 22:58:45.300738 Dram Type= 6, Freq= 0, CH_0, rank 1
1307 22:58:45.304042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1308 22:58:45.304686 ==
1309 22:58:45.305271
1310 22:58:45.305868
1311 22:58:45.307065 TX Vref Scan disable
1312 22:58:45.310415 == TX Byte 0 ==
1313 22:58:45.313606 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1314 22:58:45.316885 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1315 22:58:45.320320 == TX Byte 1 ==
1316 22:58:45.323991 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1317 22:58:45.326883 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1318 22:58:45.327495 ==
1319 22:58:45.330581 Dram Type= 6, Freq= 0, CH_0, rank 1
1320 22:58:45.337570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1321 22:58:45.338147 ==
1322 22:58:45.349675 TX Vref=22, minBit 9, minWin=27, winSum=448
1323 22:58:45.353020 TX Vref=24, minBit 1, minWin=28, winSum=454
1324 22:58:45.356145 TX Vref=26, minBit 1, minWin=28, winSum=456
1325 22:58:45.359436 TX Vref=28, minBit 7, minWin=28, winSum=457
1326 22:58:45.362968 TX Vref=30, minBit 4, minWin=28, winSum=459
1327 22:58:45.369359 TX Vref=32, minBit 12, minWin=27, winSum=454
1328 22:58:45.372478 [TxChooseVref] Worse bit 4, Min win 28, Win sum 459, Final Vref 30
1329 22:58:45.373162
1330 22:58:45.375921 Final TX Range 1 Vref 30
1331 22:58:45.376591
1332 22:58:45.377201 ==
1333 22:58:45.379130 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 22:58:45.382213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 22:58:45.382675 ==
1336 22:58:45.383118
1337 22:58:45.385428
1338 22:58:45.385772 TX Vref Scan disable
1339 22:58:45.389481 == TX Byte 0 ==
1340 22:58:45.392353 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1341 22:58:45.395900 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1342 22:58:45.399387 == TX Byte 1 ==
1343 22:58:45.403270 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1344 22:58:45.405875 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1345 22:58:45.409249
1346 22:58:45.409388 [DATLAT]
1347 22:58:45.409515 Freq=800, CH0 RK1
1348 22:58:45.409689
1349 22:58:45.412460 DATLAT Default: 0xa
1350 22:58:45.412584 0, 0xFFFF, sum = 0
1351 22:58:45.416048 1, 0xFFFF, sum = 0
1352 22:58:45.416132 2, 0xFFFF, sum = 0
1353 22:58:45.419265 3, 0xFFFF, sum = 0
1354 22:58:45.419447 4, 0xFFFF, sum = 0
1355 22:58:45.422442 5, 0xFFFF, sum = 0
1356 22:58:45.422570 6, 0xFFFF, sum = 0
1357 22:58:45.425840 7, 0xFFFF, sum = 0
1358 22:58:45.429251 8, 0xFFFF, sum = 0
1359 22:58:45.429357 9, 0x0, sum = 1
1360 22:58:45.429438 10, 0x0, sum = 2
1361 22:58:45.432437 11, 0x0, sum = 3
1362 22:58:45.432579 12, 0x0, sum = 4
1363 22:58:45.435625 best_step = 10
1364 22:58:45.435749
1365 22:58:45.435842 ==
1366 22:58:45.439379 Dram Type= 6, Freq= 0, CH_0, rank 1
1367 22:58:45.442377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1368 22:58:45.442518 ==
1369 22:58:45.445586 RX Vref Scan: 0
1370 22:58:45.445744
1371 22:58:45.445839 RX Vref 0 -> 0, step: 1
1372 22:58:45.445927
1373 22:58:45.449361 RX Delay -79 -> 252, step: 8
1374 22:58:45.456144 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1375 22:58:45.459437 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1376 22:58:45.462718 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1377 22:58:45.466090 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1378 22:58:45.469435 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1379 22:58:45.472690 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1380 22:58:45.479046 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1381 22:58:45.482381 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1382 22:58:45.485622 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1383 22:58:45.489599 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1384 22:58:45.492911 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1385 22:58:45.499387 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1386 22:58:45.502664 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1387 22:58:45.506063 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1388 22:58:45.509335 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1389 22:58:45.515843 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1390 22:58:45.516001 ==
1391 22:58:45.519070 Dram Type= 6, Freq= 0, CH_0, rank 1
1392 22:58:45.522390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1393 22:58:45.522526 ==
1394 22:58:45.522624 DQS Delay:
1395 22:58:45.526125 DQS0 = 0, DQS1 = 0
1396 22:58:45.526235 DQM Delay:
1397 22:58:45.529387 DQM0 = 93, DQM1 = 83
1398 22:58:45.529489 DQ Delay:
1399 22:58:45.532777 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1400 22:58:45.536153 DQ4 =92, DQ5 =88, DQ6 =100, DQ7 =100
1401 22:58:45.539535 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1402 22:58:45.542614 DQ12 =92, DQ13 =84, DQ14 =92, DQ15 =92
1403 22:58:45.542699
1404 22:58:45.542767
1405 22:58:45.549655 [DQSOSCAuto] RK1, (LSB)MR18= 0x4313, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1406 22:58:45.552827 CH0 RK1: MR19=606, MR18=4313
1407 22:58:45.559247 CH0_RK1: MR19=0x606, MR18=0x4313, DQSOSC=393, MR23=63, INC=95, DEC=63
1408 22:58:45.562673 [RxdqsGatingPostProcess] freq 800
1409 22:58:45.569364 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1410 22:58:45.569460 Pre-setting of DQS Precalculation
1411 22:58:45.575931 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1412 22:58:45.576112 ==
1413 22:58:45.579138 Dram Type= 6, Freq= 0, CH_1, rank 0
1414 22:58:45.583050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1415 22:58:45.583163 ==
1416 22:58:45.589611 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1417 22:58:45.596250 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1418 22:58:45.604174 [CA 0] Center 36 (6~67) winsize 62
1419 22:58:45.607348 [CA 1] Center 36 (6~67) winsize 62
1420 22:58:45.610687 [CA 2] Center 35 (5~65) winsize 61
1421 22:58:45.614131 [CA 3] Center 34 (4~65) winsize 62
1422 22:58:45.617390 [CA 4] Center 35 (5~65) winsize 61
1423 22:58:45.620575 [CA 5] Center 34 (4~65) winsize 62
1424 22:58:45.620688
1425 22:58:45.624204 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1426 22:58:45.624309
1427 22:58:45.627589 [CATrainingPosCal] consider 1 rank data
1428 22:58:45.630657 u2DelayCellTimex100 = 270/100 ps
1429 22:58:45.633916 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1430 22:58:45.637791 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1431 22:58:45.644364 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1432 22:58:45.647832 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1433 22:58:45.650903 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1434 22:58:45.653923 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1435 22:58:45.654003
1436 22:58:45.657299 CA PerBit enable=1, Macro0, CA PI delay=34
1437 22:58:45.657400
1438 22:58:45.660538 [CBTSetCACLKResult] CA Dly = 34
1439 22:58:45.660648 CS Dly: 6 (0~37)
1440 22:58:45.660750 ==
1441 22:58:45.664254 Dram Type= 6, Freq= 0, CH_1, rank 1
1442 22:58:45.670941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 22:58:45.671068 ==
1444 22:58:45.674247 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1445 22:58:45.680990 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1446 22:58:45.690099 [CA 0] Center 36 (6~67) winsize 62
1447 22:58:45.693874 [CA 1] Center 37 (6~68) winsize 63
1448 22:58:45.697920 [CA 2] Center 35 (5~66) winsize 62
1449 22:58:45.701808 [CA 3] Center 34 (4~65) winsize 62
1450 22:58:45.705215 [CA 4] Center 35 (5~65) winsize 61
1451 22:58:45.708981 [CA 5] Center 34 (4~65) winsize 62
1452 22:58:45.709118
1453 22:58:45.712951 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1454 22:58:45.713065
1455 22:58:45.716374 [CATrainingPosCal] consider 2 rank data
1456 22:58:45.716482 u2DelayCellTimex100 = 270/100 ps
1457 22:58:45.720639 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1458 22:58:45.723729 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1459 22:58:45.727656 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1460 22:58:45.731452 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1461 22:58:45.734729 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1462 22:58:45.741447 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1463 22:58:45.741668
1464 22:58:45.744688 CA PerBit enable=1, Macro0, CA PI delay=34
1465 22:58:45.744826
1466 22:58:45.748031 [CBTSetCACLKResult] CA Dly = 34
1467 22:58:45.748168 CS Dly: 6 (0~38)
1468 22:58:45.748267
1469 22:58:45.751356 ----->DramcWriteLeveling(PI) begin...
1470 22:58:45.751445 ==
1471 22:58:45.754804 Dram Type= 6, Freq= 0, CH_1, rank 0
1472 22:58:45.757938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1473 22:58:45.761325 ==
1474 22:58:45.761479 Write leveling (Byte 0): 29 => 29
1475 22:58:45.764383 Write leveling (Byte 1): 29 => 29
1476 22:58:45.768070 DramcWriteLeveling(PI) end<-----
1477 22:58:45.768214
1478 22:58:45.768303 ==
1479 22:58:45.771306 Dram Type= 6, Freq= 0, CH_1, rank 0
1480 22:58:45.778030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1481 22:58:45.778129 ==
1482 22:58:45.778198 [Gating] SW mode calibration
1483 22:58:45.788201 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1484 22:58:45.791382 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1485 22:58:45.794714 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1486 22:58:45.801125 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1487 22:58:45.804403 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 22:58:45.807787 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 22:58:45.814996 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 22:58:45.818296 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 22:58:45.821058 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 22:58:45.827967 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 22:58:45.831132 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 22:58:45.834586 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 22:58:45.841553 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 22:58:45.844615 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 22:58:45.848285 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 22:58:45.854761 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 22:58:45.857907 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 22:58:45.861390 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 22:58:45.864930 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 22:58:45.871349 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1503 22:58:45.874568 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1504 22:58:45.878185 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 22:58:45.885028 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 22:58:45.888247 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 22:58:45.891500 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 22:58:45.898417 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 22:58:45.901649 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 22:58:45.904745 0 9 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1511 22:58:45.911253 0 9 8 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1512 22:58:45.914629 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1513 22:58:45.917803 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1514 22:58:45.924658 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1515 22:58:45.928058 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1516 22:58:45.931424 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1517 22:58:45.938135 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1518 22:58:45.941662 0 10 4 | B1->B0 | 3131 2b2b | 1 1 | (1 0) (1 1)
1519 22:58:45.944786 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1520 22:58:45.948318 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 22:58:45.955027 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 22:58:45.958154 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 22:58:45.961863 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 22:58:45.968186 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 22:58:45.971494 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 22:58:45.974776 0 11 4 | B1->B0 | 2828 3333 | 0 0 | (0 0) (0 0)
1527 22:58:45.981558 0 11 8 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1528 22:58:45.984722 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1529 22:58:45.988019 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1530 22:58:45.994769 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1531 22:58:45.998119 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1532 22:58:46.001594 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1533 22:58:46.008216 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1534 22:58:46.011455 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1535 22:58:46.014667 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1536 22:58:46.021738 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1537 22:58:46.025179 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1538 22:58:46.028537 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 22:58:46.031941 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 22:58:46.038496 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 22:58:46.041852 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 22:58:46.045307 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 22:58:46.051788 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 22:58:46.055099 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 22:58:46.058565 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 22:58:46.065260 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 22:58:46.068355 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 22:58:46.071506 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 22:58:46.078642 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 22:58:46.081851 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1551 22:58:46.084922 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 22:58:46.088190 Total UI for P1: 0, mck2ui 16
1553 22:58:46.092092 best dqsien dly found for B0: ( 0, 14, 6)
1554 22:58:46.095148 Total UI for P1: 0, mck2ui 16
1555 22:58:46.098531 best dqsien dly found for B1: ( 0, 14, 4)
1556 22:58:46.101857 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1557 22:58:46.105231 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1558 22:58:46.105489
1559 22:58:46.110728 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1560 22:58:46.115174 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1561 22:58:46.115317 [Gating] SW calibration Done
1562 22:58:46.115450 ==
1563 22:58:46.118414 Dram Type= 6, Freq= 0, CH_1, rank 0
1564 22:58:46.127894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1565 22:58:46.128016 ==
1566 22:58:46.128121 RX Vref Scan: 0
1567 22:58:46.128215
1568 22:58:46.128808 RX Vref 0 -> 0, step: 1
1569 22:58:46.128908
1570 22:58:46.132079 RX Delay -130 -> 252, step: 16
1571 22:58:46.135515 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1572 22:58:46.138899 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1573 22:58:46.141597 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1574 22:58:46.145152 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1575 22:58:46.152212 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1576 22:58:46.155478 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1577 22:58:46.158238 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1578 22:58:46.162183 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1579 22:58:46.167924 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1580 22:58:46.172068 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1581 22:58:46.175272 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1582 22:58:46.181725 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1583 22:58:46.182075 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1584 22:58:46.188783 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1585 22:58:46.191917 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1586 22:58:46.195606 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1587 22:58:46.195837 ==
1588 22:58:46.198651 Dram Type= 6, Freq= 0, CH_1, rank 0
1589 22:58:46.201895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1590 22:58:46.202158 ==
1591 22:58:46.205262 DQS Delay:
1592 22:58:46.205491 DQS0 = 0, DQS1 = 0
1593 22:58:46.205687 DQM Delay:
1594 22:58:46.208529 DQM0 = 93, DQM1 = 87
1595 22:58:46.208893 DQ Delay:
1596 22:58:46.213095 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1597 22:58:46.215494 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1598 22:58:46.218872 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1599 22:58:46.222062 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1600 22:58:46.222494
1601 22:58:46.222838
1602 22:58:46.223154 ==
1603 22:58:46.225815 Dram Type= 6, Freq= 0, CH_1, rank 0
1604 22:58:46.232131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1605 22:58:46.232582 ==
1606 22:58:46.232930
1607 22:58:46.233444
1608 22:58:46.233792 TX Vref Scan disable
1609 22:58:46.235868 == TX Byte 0 ==
1610 22:58:46.239279 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1611 22:58:46.242769 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1612 22:58:46.246096 == TX Byte 1 ==
1613 22:58:46.249543 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1614 22:58:46.253122 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1615 22:58:46.258183 ==
1616 22:58:46.258656 Dram Type= 6, Freq= 0, CH_1, rank 0
1617 22:58:46.262701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1618 22:58:46.263137 ==
1619 22:58:46.275725 TX Vref=22, minBit 2, minWin=26, winSum=441
1620 22:58:46.278463 TX Vref=24, minBit 0, minWin=27, winSum=444
1621 22:58:46.282283 TX Vref=26, minBit 1, minWin=27, winSum=448
1622 22:58:46.285711 TX Vref=28, minBit 2, minWin=27, winSum=448
1623 22:58:46.288666 TX Vref=30, minBit 0, minWin=27, winSum=448
1624 22:58:46.291963 TX Vref=32, minBit 0, minWin=27, winSum=445
1625 22:58:46.299040 [TxChooseVref] Worse bit 1, Min win 27, Win sum 448, Final Vref 26
1626 22:58:46.299537
1627 22:58:46.302192 Final TX Range 1 Vref 26
1628 22:58:46.302791
1629 22:58:46.303272 ==
1630 22:58:46.305229 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 22:58:46.308900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 22:58:46.309452 ==
1633 22:58:46.309998
1634 22:58:46.310631
1635 22:58:46.313565 TX Vref Scan disable
1636 22:58:46.315369 == TX Byte 0 ==
1637 22:58:46.318938 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1638 22:58:46.322274 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1639 22:58:46.325491 == TX Byte 1 ==
1640 22:58:46.331046 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1641 22:58:46.332441 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1642 22:58:46.332866
1643 22:58:46.335568 [DATLAT]
1644 22:58:46.335989 Freq=800, CH1 RK0
1645 22:58:46.336326
1646 22:58:46.338745 DATLAT Default: 0xa
1647 22:58:46.339166 0, 0xFFFF, sum = 0
1648 22:58:46.341916 1, 0xFFFF, sum = 0
1649 22:58:46.342563 2, 0xFFFF, sum = 0
1650 22:58:46.345871 3, 0xFFFF, sum = 0
1651 22:58:46.346420 4, 0xFFFF, sum = 0
1652 22:58:46.349191 5, 0xFFFF, sum = 0
1653 22:58:46.349714 6, 0xFFFF, sum = 0
1654 22:58:46.351946 7, 0xFFFF, sum = 0
1655 22:58:46.352459 8, 0xFFFF, sum = 0
1656 22:58:46.355052 9, 0x0, sum = 1
1657 22:58:46.355650 10, 0x0, sum = 2
1658 22:58:46.358591 11, 0x0, sum = 3
1659 22:58:46.359060 12, 0x0, sum = 4
1660 22:58:46.361893 best_step = 10
1661 22:58:46.362315
1662 22:58:46.362719 ==
1663 22:58:46.365254 Dram Type= 6, Freq= 0, CH_1, rank 0
1664 22:58:46.368615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1665 22:58:46.369040 ==
1666 22:58:46.369377 RX Vref Scan: 1
1667 22:58:46.369691
1668 22:58:46.372618 Set Vref Range= 32 -> 127
1669 22:58:46.373039
1670 22:58:46.375274 RX Vref 32 -> 127, step: 1
1671 22:58:46.375775
1672 22:58:46.379260 RX Delay -79 -> 252, step: 8
1673 22:58:46.379751
1674 22:58:46.382482 Set Vref, RX VrefLevel [Byte0]: 32
1675 22:58:46.385362 [Byte1]: 32
1676 22:58:46.385865
1677 22:58:46.388835 Set Vref, RX VrefLevel [Byte0]: 33
1678 22:58:46.392018 [Byte1]: 33
1679 22:58:46.392520
1680 22:58:46.395191 Set Vref, RX VrefLevel [Byte0]: 34
1681 22:58:46.398921 [Byte1]: 34
1682 22:58:46.402702
1683 22:58:46.403408 Set Vref, RX VrefLevel [Byte0]: 35
1684 22:58:46.406007 [Byte1]: 35
1685 22:58:46.409922
1686 22:58:46.410494 Set Vref, RX VrefLevel [Byte0]: 36
1687 22:58:46.412877 [Byte1]: 36
1688 22:58:46.417365
1689 22:58:46.417826 Set Vref, RX VrefLevel [Byte0]: 37
1690 22:58:46.421172 [Byte1]: 37
1691 22:58:46.425035
1692 22:58:46.425478 Set Vref, RX VrefLevel [Byte0]: 38
1693 22:58:46.428451 [Byte1]: 38
1694 22:58:46.432735
1695 22:58:46.433176 Set Vref, RX VrefLevel [Byte0]: 39
1696 22:58:46.435833 [Byte1]: 39
1697 22:58:46.440280
1698 22:58:46.440700 Set Vref, RX VrefLevel [Byte0]: 40
1699 22:58:46.443851 [Byte1]: 40
1700 22:58:46.448100
1701 22:58:46.448526 Set Vref, RX VrefLevel [Byte0]: 41
1702 22:58:46.451435 [Byte1]: 41
1703 22:58:46.455444
1704 22:58:46.455887 Set Vref, RX VrefLevel [Byte0]: 42
1705 22:58:46.458765 [Byte1]: 42
1706 22:58:46.462799
1707 22:58:46.463553 Set Vref, RX VrefLevel [Byte0]: 43
1708 22:58:46.465963 [Byte1]: 43
1709 22:58:46.470444
1710 22:58:46.471072 Set Vref, RX VrefLevel [Byte0]: 44
1711 22:58:46.473947 [Byte1]: 44
1712 22:58:46.477928
1713 22:58:46.478337 Set Vref, RX VrefLevel [Byte0]: 45
1714 22:58:46.481205 [Byte1]: 45
1715 22:58:46.485136
1716 22:58:46.485360 Set Vref, RX VrefLevel [Byte0]: 46
1717 22:58:46.488620 [Byte1]: 46
1718 22:58:46.492437
1719 22:58:46.492675 Set Vref, RX VrefLevel [Byte0]: 47
1720 22:58:46.496525 [Byte1]: 47
1721 22:58:46.500380
1722 22:58:46.500551 Set Vref, RX VrefLevel [Byte0]: 48
1723 22:58:46.503631 [Byte1]: 48
1724 22:58:46.507920
1725 22:58:46.508096 Set Vref, RX VrefLevel [Byte0]: 49
1726 22:58:46.510963 [Byte1]: 49
1727 22:58:46.515619
1728 22:58:46.515779 Set Vref, RX VrefLevel [Byte0]: 50
1729 22:58:46.518957 [Byte1]: 50
1730 22:58:46.523202
1731 22:58:46.523374 Set Vref, RX VrefLevel [Byte0]: 51
1732 22:58:46.526306 [Byte1]: 51
1733 22:58:46.530647
1734 22:58:46.530814 Set Vref, RX VrefLevel [Byte0]: 52
1735 22:58:46.533853 [Byte1]: 52
1736 22:58:46.537821
1737 22:58:46.538009 Set Vref, RX VrefLevel [Byte0]: 53
1738 22:58:46.541181 [Byte1]: 53
1739 22:58:46.545773
1740 22:58:46.545943 Set Vref, RX VrefLevel [Byte0]: 54
1741 22:58:46.549056 [Byte1]: 54
1742 22:58:46.552855
1743 22:58:46.553014 Set Vref, RX VrefLevel [Byte0]: 55
1744 22:58:46.556569 [Byte1]: 55
1745 22:58:46.560830
1746 22:58:46.560920 Set Vref, RX VrefLevel [Byte0]: 56
1747 22:58:46.564248 [Byte1]: 56
1748 22:58:46.568291
1749 22:58:46.568383 Set Vref, RX VrefLevel [Byte0]: 57
1750 22:58:46.571627 [Byte1]: 57
1751 22:58:46.575768
1752 22:58:46.575884 Set Vref, RX VrefLevel [Byte0]: 58
1753 22:58:46.579008 [Byte1]: 58
1754 22:58:46.583017
1755 22:58:46.583133 Set Vref, RX VrefLevel [Byte0]: 59
1756 22:58:46.586916 [Byte1]: 59
1757 22:58:46.590967
1758 22:58:46.591157 Set Vref, RX VrefLevel [Byte0]: 60
1759 22:58:46.594289 [Byte1]: 60
1760 22:58:46.598264
1761 22:58:46.598367 Set Vref, RX VrefLevel [Byte0]: 61
1762 22:58:46.601602 [Byte1]: 61
1763 22:58:46.606400
1764 22:58:46.606491 Set Vref, RX VrefLevel [Byte0]: 62
1765 22:58:46.609438 [Byte1]: 62
1766 22:58:46.613301
1767 22:58:46.613426 Set Vref, RX VrefLevel [Byte0]: 63
1768 22:58:46.616556 [Byte1]: 63
1769 22:58:46.620932
1770 22:58:46.621099 Set Vref, RX VrefLevel [Byte0]: 64
1771 22:58:46.624827 [Byte1]: 64
1772 22:58:46.628850
1773 22:58:46.628979 Set Vref, RX VrefLevel [Byte0]: 65
1774 22:58:46.631929 [Byte1]: 65
1775 22:58:46.636265
1776 22:58:46.636465 Set Vref, RX VrefLevel [Byte0]: 66
1777 22:58:46.639594 [Byte1]: 66
1778 22:58:46.643581
1779 22:58:46.643873 Set Vref, RX VrefLevel [Byte0]: 67
1780 22:58:46.646903 [Byte1]: 67
1781 22:58:46.651311
1782 22:58:46.651641 Set Vref, RX VrefLevel [Byte0]: 68
1783 22:58:46.654556 [Byte1]: 68
1784 22:58:46.659158
1785 22:58:46.659470 Set Vref, RX VrefLevel [Byte0]: 69
1786 22:58:46.662333 [Byte1]: 69
1787 22:58:46.666180
1788 22:58:46.666411 Set Vref, RX VrefLevel [Byte0]: 70
1789 22:58:46.669809 [Byte1]: 70
1790 22:58:46.674168
1791 22:58:46.674392 Set Vref, RX VrefLevel [Byte0]: 71
1792 22:58:46.677414 [Byte1]: 71
1793 22:58:46.681274
1794 22:58:46.681543 Set Vref, RX VrefLevel [Byte0]: 72
1795 22:58:46.684778 [Byte1]: 72
1796 22:58:46.689607
1797 22:58:46.690254 Final RX Vref Byte 0 = 58 to rank0
1798 22:58:46.692188 Final RX Vref Byte 1 = 54 to rank0
1799 22:58:46.695544 Final RX Vref Byte 0 = 58 to rank1
1800 22:58:46.698943 Final RX Vref Byte 1 = 54 to rank1==
1801 22:58:46.702474 Dram Type= 6, Freq= 0, CH_1, rank 0
1802 22:58:46.709187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1803 22:58:46.709596 ==
1804 22:58:46.709924 DQS Delay:
1805 22:58:46.710379 DQS0 = 0, DQS1 = 0
1806 22:58:46.712501 DQM Delay:
1807 22:58:46.712844 DQM0 = 96, DQM1 = 89
1808 22:58:46.715809 DQ Delay:
1809 22:58:46.719065 DQ0 =100, DQ1 =88, DQ2 =88, DQ3 =92
1810 22:58:46.722298 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =92
1811 22:58:46.726115 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1812 22:58:46.729456 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1813 22:58:46.729801
1814 22:58:46.730064
1815 22:58:46.735711 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c48, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1816 22:58:46.738944 CH1 RK0: MR19=606, MR18=2C48
1817 22:58:46.745761 CH1_RK0: MR19=0x606, MR18=0x2C48, DQSOSC=391, MR23=63, INC=96, DEC=64
1818 22:58:46.746019
1819 22:58:46.748934 ----->DramcWriteLeveling(PI) begin...
1820 22:58:46.749102 ==
1821 22:58:46.752326 Dram Type= 6, Freq= 0, CH_1, rank 1
1822 22:58:46.755552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1823 22:58:46.755680 ==
1824 22:58:46.758905 Write leveling (Byte 0): 30 => 30
1825 22:58:46.762242 Write leveling (Byte 1): 31 => 31
1826 22:58:46.765569 DramcWriteLeveling(PI) end<-----
1827 22:58:46.765725
1828 22:58:46.765826 ==
1829 22:58:46.768969 Dram Type= 6, Freq= 0, CH_1, rank 1
1830 22:58:46.772107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1831 22:58:46.772240 ==
1832 22:58:46.775684 [Gating] SW mode calibration
1833 22:58:46.782488 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1834 22:58:46.789102 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1835 22:58:46.792572 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1836 22:58:46.795729 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1837 22:58:46.802480 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 22:58:46.805986 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 22:58:46.809290 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 22:58:46.816013 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 22:58:46.819236 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 22:58:46.822716 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 22:58:46.828914 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 22:58:46.832916 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 22:58:46.836126 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 22:58:46.842555 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 22:58:46.845782 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 22:58:46.848907 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 22:58:46.852682 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 22:58:46.859380 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 22:58:46.863243 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1852 22:58:46.866025 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1853 22:58:46.872794 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 22:58:46.876015 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 22:58:46.879241 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 22:58:46.886334 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 22:58:46.889804 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 22:58:46.892695 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 22:58:46.899850 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 22:58:46.903103 0 9 4 | B1->B0 | 2b2b 2322 | 1 1 | (1 1) (0 0)
1861 22:58:46.906554 0 9 8 | B1->B0 | 3434 3231 | 1 1 | (1 1) (1 1)
1862 22:58:46.913317 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1863 22:58:46.916600 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1864 22:58:46.919691 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1865 22:58:46.922984 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1866 22:58:46.929700 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1867 22:58:46.932902 0 10 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1868 22:58:46.936188 0 10 4 | B1->B0 | 2525 2f2f | 0 1 | (1 0) (1 0)
1869 22:58:46.942620 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 0)
1870 22:58:46.946605 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 22:58:46.949998 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 22:58:46.956298 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 22:58:46.959509 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 22:58:46.962771 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 22:58:46.969996 0 11 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1876 22:58:46.972577 0 11 4 | B1->B0 | 4242 2c2c | 0 0 | (0 0) (0 0)
1877 22:58:46.976158 0 11 8 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1878 22:58:46.983555 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1879 22:58:46.986871 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1880 22:58:46.989701 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1881 22:58:46.993464 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1882 22:58:46.999889 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1883 22:58:47.003029 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1884 22:58:47.006952 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1885 22:58:47.013237 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1886 22:58:47.016413 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 22:58:47.019756 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 22:58:47.026367 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 22:58:47.030249 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 22:58:47.033625 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 22:58:47.040001 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 22:58:47.043255 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1893 22:58:47.046595 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 22:58:47.053243 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 22:58:47.057040 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 22:58:47.060238 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 22:58:47.066521 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 22:58:47.070269 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 22:58:47.073641 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1900 22:58:47.079615 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1901 22:58:47.083009 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1902 22:58:47.087010 Total UI for P1: 0, mck2ui 16
1903 22:58:47.090239 best dqsien dly found for B0: ( 0, 14, 4)
1904 22:58:47.093519 Total UI for P1: 0, mck2ui 16
1905 22:58:47.096868 best dqsien dly found for B1: ( 0, 14, 2)
1906 22:58:47.100246 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1907 22:58:47.103473 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1908 22:58:47.103862
1909 22:58:47.106617 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1910 22:58:47.109761 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1911 22:58:47.113616 [Gating] SW calibration Done
1912 22:58:47.113949 ==
1913 22:58:47.117193 Dram Type= 6, Freq= 0, CH_1, rank 1
1914 22:58:47.119804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1915 22:58:47.120220 ==
1916 22:58:47.123834 RX Vref Scan: 0
1917 22:58:47.124196
1918 22:58:47.124563 RX Vref 0 -> 0, step: 1
1919 22:58:47.124816
1920 22:58:47.126535 RX Delay -130 -> 252, step: 16
1921 22:58:47.130470 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1922 22:58:47.136990 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1923 22:58:47.140303 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1924 22:58:47.143650 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1925 22:58:47.147030 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1926 22:58:47.150285 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1927 22:58:47.156689 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1928 22:58:47.160196 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1929 22:58:47.163367 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1930 22:58:47.167031 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1931 22:58:47.170250 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1932 22:58:47.176666 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1933 22:58:47.179938 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1934 22:58:47.183270 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1935 22:58:47.187435 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1936 22:58:47.191081 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1937 22:58:47.193476 ==
1938 22:58:47.193873 Dram Type= 6, Freq= 0, CH_1, rank 1
1939 22:58:47.200496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1940 22:58:47.201050 ==
1941 22:58:47.201426 DQS Delay:
1942 22:58:47.203912 DQS0 = 0, DQS1 = 0
1943 22:58:47.204498 DQM Delay:
1944 22:58:47.207242 DQM0 = 92, DQM1 = 87
1945 22:58:47.207868 DQ Delay:
1946 22:58:47.210482 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1947 22:58:47.214049 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1948 22:58:47.217113 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1949 22:58:47.220717 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1950 22:58:47.221186
1951 22:58:47.221581
1952 22:58:47.222175 ==
1953 22:58:47.224000 Dram Type= 6, Freq= 0, CH_1, rank 1
1954 22:58:47.227247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1955 22:58:47.227747 ==
1956 22:58:47.228124
1957 22:58:47.228472
1958 22:58:47.230659 TX Vref Scan disable
1959 22:58:47.234079 == TX Byte 0 ==
1960 22:58:47.237460 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1961 22:58:47.240701 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1962 22:58:47.244143 == TX Byte 1 ==
1963 22:58:47.247679 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1964 22:58:47.250641 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1965 22:58:47.251120 ==
1966 22:58:47.254260 Dram Type= 6, Freq= 0, CH_1, rank 1
1967 22:58:47.257652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1968 22:58:47.260708 ==
1969 22:58:47.271916 TX Vref=22, minBit 0, minWin=27, winSum=440
1970 22:58:47.275004 TX Vref=24, minBit 0, minWin=27, winSum=445
1971 22:58:47.278693 TX Vref=26, minBit 2, minWin=27, winSum=450
1972 22:58:47.281504 TX Vref=28, minBit 2, minWin=27, winSum=449
1973 22:58:47.285415 TX Vref=30, minBit 0, minWin=27, winSum=451
1974 22:58:47.288375 TX Vref=32, minBit 0, minWin=27, winSum=447
1975 22:58:47.295177 [TxChooseVref] Worse bit 0, Min win 27, Win sum 451, Final Vref 30
1976 22:58:47.295890
1977 22:58:47.298606 Final TX Range 1 Vref 30
1978 22:58:47.299176
1979 22:58:47.299690 ==
1980 22:58:47.301817 Dram Type= 6, Freq= 0, CH_1, rank 1
1981 22:58:47.304897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1982 22:58:47.305377 ==
1983 22:58:47.305753
1984 22:58:47.308174
1985 22:58:47.308649 TX Vref Scan disable
1986 22:58:47.311489 == TX Byte 0 ==
1987 22:58:47.315052 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1988 22:58:47.318358 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1989 22:58:47.321806 == TX Byte 1 ==
1990 22:58:47.324777 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1991 22:58:47.328430 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1992 22:58:47.328907
1993 22:58:47.331765 [DATLAT]
1994 22:58:47.332280 Freq=800, CH1 RK1
1995 22:58:47.332659
1996 22:58:47.334958 DATLAT Default: 0xa
1997 22:58:47.335498 0, 0xFFFF, sum = 0
1998 22:58:47.338447 1, 0xFFFF, sum = 0
1999 22:58:47.338930 2, 0xFFFF, sum = 0
2000 22:58:47.341892 3, 0xFFFF, sum = 0
2001 22:58:47.342482 4, 0xFFFF, sum = 0
2002 22:58:47.345395 5, 0xFFFF, sum = 0
2003 22:58:47.345970 6, 0xFFFF, sum = 0
2004 22:58:47.348415 7, 0xFFFF, sum = 0
2005 22:58:47.348897 8, 0xFFFF, sum = 0
2006 22:58:47.351812 9, 0x0, sum = 1
2007 22:58:47.352397 10, 0x0, sum = 2
2008 22:58:47.355001 11, 0x0, sum = 3
2009 22:58:47.355665 12, 0x0, sum = 4
2010 22:58:47.358295 best_step = 10
2011 22:58:47.358867
2012 22:58:47.359244 ==
2013 22:58:47.361644 Dram Type= 6, Freq= 0, CH_1, rank 1
2014 22:58:47.364892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2015 22:58:47.365369 ==
2016 22:58:47.368308 RX Vref Scan: 0
2017 22:58:47.368780
2018 22:58:47.369153 RX Vref 0 -> 0, step: 1
2019 22:58:47.369501
2020 22:58:47.371663 RX Delay -79 -> 252, step: 8
2021 22:58:47.378881 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2022 22:58:47.381717 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2023 22:58:47.385228 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2024 22:58:47.389545 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2025 22:58:47.391659 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2026 22:58:47.395494 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2027 22:58:47.401820 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2028 22:58:47.405035 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2029 22:58:47.408353 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2030 22:58:47.411906 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2031 22:58:47.415396 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
2032 22:58:47.418736 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2033 22:58:47.425243 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2034 22:58:47.428569 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2035 22:58:47.431950 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2036 22:58:47.435071 iDelay=209, Bit 15, Center 100 (1 ~ 200) 200
2037 22:58:47.435701 ==
2038 22:58:47.438874 Dram Type= 6, Freq= 0, CH_1, rank 1
2039 22:58:47.445333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2040 22:58:47.445907 ==
2041 22:58:47.446289 DQS Delay:
2042 22:58:47.446647 DQS0 = 0, DQS1 = 0
2043 22:58:47.448391 DQM Delay:
2044 22:58:47.448864 DQM0 = 97, DQM1 = 92
2045 22:58:47.451894 DQ Delay:
2046 22:58:47.455411 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2047 22:58:47.458529 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =96
2048 22:58:47.462003 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =88
2049 22:58:47.465432 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =100
2050 22:58:47.465908
2051 22:58:47.466284
2052 22:58:47.472326 [DQSOSCAuto] RK1, (LSB)MR18= 0x4610, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
2053 22:58:47.475857 CH1 RK1: MR19=606, MR18=4610
2054 22:58:47.482095 CH1_RK1: MR19=0x606, MR18=0x4610, DQSOSC=392, MR23=63, INC=96, DEC=64
2055 22:58:47.485524 [RxdqsGatingPostProcess] freq 800
2056 22:58:47.489038 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2057 22:58:47.492466 Pre-setting of DQS Precalculation
2058 22:58:47.498782 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2059 22:58:47.505200 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2060 22:58:47.512308 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2061 22:58:47.512857
2062 22:58:47.513226
2063 22:58:47.515612 [Calibration Summary] 1600 Mbps
2064 22:58:47.516080 CH 0, Rank 0
2065 22:58:47.518879 SW Impedance : PASS
2066 22:58:47.522201 DUTY Scan : NO K
2067 22:58:47.522669 ZQ Calibration : PASS
2068 22:58:47.525647 Jitter Meter : NO K
2069 22:58:47.528832 CBT Training : PASS
2070 22:58:47.529255 Write leveling : PASS
2071 22:58:47.532356 RX DQS gating : PASS
2072 22:58:47.535786 RX DQ/DQS(RDDQC) : PASS
2073 22:58:47.536207 TX DQ/DQS : PASS
2074 22:58:47.538297 RX DATLAT : PASS
2075 22:58:47.538762 RX DQ/DQS(Engine): PASS
2076 22:58:47.542173 TX OE : NO K
2077 22:58:47.542596 All Pass.
2078 22:58:47.542972
2079 22:58:47.545518 CH 0, Rank 1
2080 22:58:47.545939 SW Impedance : PASS
2081 22:58:47.548778 DUTY Scan : NO K
2082 22:58:47.552071 ZQ Calibration : PASS
2083 22:58:47.552494 Jitter Meter : NO K
2084 22:58:47.555404 CBT Training : PASS
2085 22:58:47.558734 Write leveling : PASS
2086 22:58:47.559179 RX DQS gating : PASS
2087 22:58:47.561962 RX DQ/DQS(RDDQC) : PASS
2088 22:58:47.565217 TX DQ/DQS : PASS
2089 22:58:47.565648 RX DATLAT : PASS
2090 22:58:47.568539 RX DQ/DQS(Engine): PASS
2091 22:58:47.572009 TX OE : NO K
2092 22:58:47.572433 All Pass.
2093 22:58:47.572770
2094 22:58:47.573083 CH 1, Rank 0
2095 22:58:47.575297 SW Impedance : PASS
2096 22:58:47.578691 DUTY Scan : NO K
2097 22:58:47.579115 ZQ Calibration : PASS
2098 22:58:47.581984 Jitter Meter : NO K
2099 22:58:47.582409 CBT Training : PASS
2100 22:58:47.585293 Write leveling : PASS
2101 22:58:47.588394 RX DQS gating : PASS
2102 22:58:47.588704 RX DQ/DQS(RDDQC) : PASS
2103 22:58:47.592278 TX DQ/DQS : PASS
2104 22:58:47.595501 RX DATLAT : PASS
2105 22:58:47.595774 RX DQ/DQS(Engine): PASS
2106 22:58:47.598634 TX OE : NO K
2107 22:58:47.598821 All Pass.
2108 22:58:47.598968
2109 22:58:47.601808 CH 1, Rank 1
2110 22:58:47.602005 SW Impedance : PASS
2111 22:58:47.604861 DUTY Scan : NO K
2112 22:58:47.608621 ZQ Calibration : PASS
2113 22:58:47.608762 Jitter Meter : NO K
2114 22:58:47.611758 CBT Training : PASS
2115 22:58:47.615147 Write leveling : PASS
2116 22:58:47.615278 RX DQS gating : PASS
2117 22:58:47.618296 RX DQ/DQS(RDDQC) : PASS
2118 22:58:47.618400 TX DQ/DQS : PASS
2119 22:58:47.627119 RX DATLAT : PASS
2120 22:58:47.627207 RX DQ/DQS(Engine): PASS
2121 22:58:47.627276 TX OE : NO K
2122 22:58:47.628737 All Pass.
2123 22:58:47.628822
2124 22:58:47.628889 DramC Write-DBI off
2125 22:58:47.632060 PER_BANK_REFRESH: Hybrid Mode
2126 22:58:47.635299 TX_TRACKING: ON
2127 22:58:47.638720 [GetDramInforAfterCalByMRR] Vendor 6.
2128 22:58:47.642011 [GetDramInforAfterCalByMRR] Revision 606.
2129 22:58:47.645658 [GetDramInforAfterCalByMRR] Revision 2 0.
2130 22:58:47.645824 MR0 0x3b3b
2131 22:58:47.645902 MR8 0x5151
2132 22:58:47.648829 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2133 22:58:47.652196
2134 22:58:47.652335 MR0 0x3b3b
2135 22:58:47.652409 MR8 0x5151
2136 22:58:47.655309 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2137 22:58:47.655495
2138 22:58:47.665490 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2139 22:58:47.668727 [FAST_K] Save calibration result to emmc
2140 22:58:47.671950 [FAST_K] Save calibration result to emmc
2141 22:58:47.675200 dram_init: config_dvfs: 1
2142 22:58:47.678590 dramc_set_vcore_voltage set vcore to 662500
2143 22:58:47.681925 Read voltage for 1200, 2
2144 22:58:47.682099 Vio18 = 0
2145 22:58:47.682203 Vcore = 662500
2146 22:58:47.685845 Vdram = 0
2147 22:58:47.686011 Vddq = 0
2148 22:58:47.686094 Vmddr = 0
2149 22:58:47.692297 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2150 22:58:47.695293 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2151 22:58:47.698995 MEM_TYPE=3, freq_sel=15
2152 22:58:47.702166 sv_algorithm_assistance_LP4_1600
2153 22:58:47.705151 ============ PULL DRAM RESETB DOWN ============
2154 22:58:47.708725 ========== PULL DRAM RESETB DOWN end =========
2155 22:58:47.715290 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2156 22:58:47.718859 ===================================
2157 22:58:47.719035 LPDDR4 DRAM CONFIGURATION
2158 22:58:47.722081 ===================================
2159 22:58:47.725801 EX_ROW_EN[0] = 0x0
2160 22:58:47.728795 EX_ROW_EN[1] = 0x0
2161 22:58:47.729040 LP4Y_EN = 0x0
2162 22:58:47.732148 WORK_FSP = 0x0
2163 22:58:47.732392 WL = 0x4
2164 22:58:47.735257 RL = 0x4
2165 22:58:47.735534 BL = 0x2
2166 22:58:47.738527 RPST = 0x0
2167 22:58:47.738770 RD_PRE = 0x0
2168 22:58:47.742424 WR_PRE = 0x1
2169 22:58:47.742668 WR_PST = 0x0
2170 22:58:47.745679 DBI_WR = 0x0
2171 22:58:47.745924 DBI_RD = 0x0
2172 22:58:47.749070 OTF = 0x1
2173 22:58:47.752246 ===================================
2174 22:58:47.755457 ===================================
2175 22:58:47.755650 ANA top config
2176 22:58:47.758698 ===================================
2177 22:58:47.762381 DLL_ASYNC_EN = 0
2178 22:58:47.765289 ALL_SLAVE_EN = 0
2179 22:58:47.765427 NEW_RANK_MODE = 1
2180 22:58:47.769372 DLL_IDLE_MODE = 1
2181 22:58:47.771871 LP45_APHY_COMB_EN = 1
2182 22:58:47.775915 TX_ODT_DIS = 1
2183 22:58:47.779071 NEW_8X_MODE = 1
2184 22:58:47.782349 ===================================
2185 22:58:47.785628 ===================================
2186 22:58:47.785718 data_rate = 2400
2187 22:58:47.789026 CKR = 1
2188 22:58:47.792350 DQ_P2S_RATIO = 8
2189 22:58:47.795649 ===================================
2190 22:58:47.798784 CA_P2S_RATIO = 8
2191 22:58:47.801908 DQ_CA_OPEN = 0
2192 22:58:47.805251 DQ_SEMI_OPEN = 0
2193 22:58:47.805335 CA_SEMI_OPEN = 0
2194 22:58:47.808947 CA_FULL_RATE = 0
2195 22:58:47.811881 DQ_CKDIV4_EN = 0
2196 22:58:47.815655 CA_CKDIV4_EN = 0
2197 22:58:47.818684 CA_PREDIV_EN = 0
2198 22:58:47.822200 PH8_DLY = 17
2199 22:58:47.822287 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2200 22:58:47.825137 DQ_AAMCK_DIV = 4
2201 22:58:47.828312 CA_AAMCK_DIV = 4
2202 22:58:47.832285 CA_ADMCK_DIV = 4
2203 22:58:47.835566 DQ_TRACK_CA_EN = 0
2204 22:58:47.838681 CA_PICK = 1200
2205 22:58:47.842055 CA_MCKIO = 1200
2206 22:58:47.842225 MCKIO_SEMI = 0
2207 22:58:47.845083 PLL_FREQ = 2366
2208 22:58:47.848341 DQ_UI_PI_RATIO = 32
2209 22:58:47.852180 CA_UI_PI_RATIO = 0
2210 22:58:47.855425 ===================================
2211 22:58:47.858704 ===================================
2212 22:58:47.862078 memory_type:LPDDR4
2213 22:58:47.862193 GP_NUM : 10
2214 22:58:47.865418 SRAM_EN : 1
2215 22:58:47.865503 MD32_EN : 0
2216 22:58:47.868700 ===================================
2217 22:58:47.871845 [ANA_INIT] >>>>>>>>>>>>>>
2218 22:58:47.874943 <<<<<< [CONFIGURE PHASE]: ANA_TX
2219 22:58:47.878656 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2220 22:58:47.881624 ===================================
2221 22:58:47.885420 data_rate = 2400,PCW = 0X5b00
2222 22:58:47.888664 ===================================
2223 22:58:47.891964 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2224 22:58:47.898401 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2225 22:58:47.901719 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2226 22:58:47.908699 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2227 22:58:47.911965 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2228 22:58:47.915780 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2229 22:58:47.915871 [ANA_INIT] flow start
2230 22:58:47.918758 [ANA_INIT] PLL >>>>>>>>
2231 22:58:47.922027 [ANA_INIT] PLL <<<<<<<<
2232 22:58:47.922115 [ANA_INIT] MIDPI >>>>>>>>
2233 22:58:47.925525 [ANA_INIT] MIDPI <<<<<<<<
2234 22:58:47.928620 [ANA_INIT] DLL >>>>>>>>
2235 22:58:47.928708 [ANA_INIT] DLL <<<<<<<<
2236 22:58:47.932219 [ANA_INIT] flow end
2237 22:58:47.935476 ============ LP4 DIFF to SE enter ============
2238 22:58:47.939098 ============ LP4 DIFF to SE exit ============
2239 22:58:47.942242 [ANA_INIT] <<<<<<<<<<<<<
2240 22:58:47.945460 [Flow] Enable top DCM control >>>>>
2241 22:58:47.948789 [Flow] Enable top DCM control <<<<<
2242 22:58:47.952559 Enable DLL master slave shuffle
2243 22:58:47.958976 ==============================================================
2244 22:58:47.959067 Gating Mode config
2245 22:58:47.965604 ==============================================================
2246 22:58:47.965753 Config description:
2247 22:58:47.975873 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2248 22:58:47.982214 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2249 22:58:47.989114 SELPH_MODE 0: By rank 1: By Phase
2250 22:58:47.992719 ==============================================================
2251 22:58:47.995863 GAT_TRACK_EN = 1
2252 22:58:47.999092 RX_GATING_MODE = 2
2253 22:58:48.002583 RX_GATING_TRACK_MODE = 2
2254 22:58:48.005904 SELPH_MODE = 1
2255 22:58:48.009081 PICG_EARLY_EN = 1
2256 22:58:48.012248 VALID_LAT_VALUE = 1
2257 22:58:48.015521 ==============================================================
2258 22:58:48.019197 Enter into Gating configuration >>>>
2259 22:58:48.022193 Exit from Gating configuration <<<<
2260 22:58:48.025488 Enter into DVFS_PRE_config >>>>>
2261 22:58:48.038832 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2262 22:58:48.038972 Exit from DVFS_PRE_config <<<<<
2263 22:58:48.042556 Enter into PICG configuration >>>>
2264 22:58:48.045586 Exit from PICG configuration <<<<
2265 22:58:48.049164 [RX_INPUT] configuration >>>>>
2266 22:58:48.052561 [RX_INPUT] configuration <<<<<
2267 22:58:48.059006 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2268 22:58:48.062454 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2269 22:58:48.068871 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2270 22:58:48.076058 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2271 22:58:48.082573 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2272 22:58:48.089408 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2273 22:58:48.092611 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2274 22:58:48.095930 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2275 22:58:48.099550 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2276 22:58:48.105942 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2277 22:58:48.109183 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2278 22:58:48.112561 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2279 22:58:48.116450 ===================================
2280 22:58:48.119345 LPDDR4 DRAM CONFIGURATION
2281 22:58:48.122724 ===================================
2282 22:58:48.122818 EX_ROW_EN[0] = 0x0
2283 22:58:48.125978 EX_ROW_EN[1] = 0x0
2284 22:58:48.126071 LP4Y_EN = 0x0
2285 22:58:48.129881 WORK_FSP = 0x0
2286 22:58:48.130000 WL = 0x4
2287 22:58:48.132657 RL = 0x4
2288 22:58:48.132743 BL = 0x2
2289 22:58:48.135958 RPST = 0x0
2290 22:58:48.139508 RD_PRE = 0x0
2291 22:58:48.139621 WR_PRE = 0x1
2292 22:58:48.142444 WR_PST = 0x0
2293 22:58:48.142530 DBI_WR = 0x0
2294 22:58:48.146130 DBI_RD = 0x0
2295 22:58:48.146217 OTF = 0x1
2296 22:58:48.149185 ===================================
2297 22:58:48.152934 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2298 22:58:48.155993 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2299 22:58:48.162886 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2300 22:58:48.166095 ===================================
2301 22:58:48.169407 LPDDR4 DRAM CONFIGURATION
2302 22:58:48.169499 ===================================
2303 22:58:48.172693 EX_ROW_EN[0] = 0x10
2304 22:58:48.175893 EX_ROW_EN[1] = 0x0
2305 22:58:48.175980 LP4Y_EN = 0x0
2306 22:58:48.179750 WORK_FSP = 0x0
2307 22:58:48.179836 WL = 0x4
2308 22:58:48.182900 RL = 0x4
2309 22:58:48.182986 BL = 0x2
2310 22:58:48.186115 RPST = 0x0
2311 22:58:48.186201 RD_PRE = 0x0
2312 22:58:48.189278 WR_PRE = 0x1
2313 22:58:48.189363 WR_PST = 0x0
2314 22:58:48.193116 DBI_WR = 0x0
2315 22:58:48.193203 DBI_RD = 0x0
2316 22:58:48.196191 OTF = 0x1
2317 22:58:48.199323 ===================================
2318 22:58:48.206098 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2319 22:58:48.206223 ==
2320 22:58:48.209551 Dram Type= 6, Freq= 0, CH_0, rank 0
2321 22:58:48.212913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2322 22:58:48.213002 ==
2323 22:58:48.216082 [Duty_Offset_Calibration]
2324 22:58:48.216168 B0:2 B1:1 CA:1
2325 22:58:48.216253
2326 22:58:48.219352 [DutyScan_Calibration_Flow] k_type=0
2327 22:58:48.230123
2328 22:58:48.230237 ==CLK 0==
2329 22:58:48.233311 Final CLK duty delay cell = 0
2330 22:58:48.236999 [0] MAX Duty = 5187%(X100), DQS PI = 24
2331 22:58:48.239988 [0] MIN Duty = 4875%(X100), DQS PI = 0
2332 22:58:48.240077 [0] AVG Duty = 5031%(X100)
2333 22:58:48.243555
2334 22:58:48.243640 CH0 CLK Duty spec in!! Max-Min= 312%
2335 22:58:48.249643 [DutyScan_Calibration_Flow] ====Done====
2336 22:58:48.249734
2337 22:58:48.253338 [DutyScan_Calibration_Flow] k_type=1
2338 22:58:48.268467
2339 22:58:48.268609 ==DQS 0 ==
2340 22:58:48.271722 Final DQS duty delay cell = -4
2341 22:58:48.275080 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2342 22:58:48.278498 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2343 22:58:48.281744 [-4] AVG Duty = 4937%(X100)
2344 22:58:48.281828
2345 22:58:48.281892 ==DQS 1 ==
2346 22:58:48.284965 Final DQS duty delay cell = 0
2347 22:58:48.288855 [0] MAX Duty = 5156%(X100), DQS PI = 0
2348 22:58:48.292089 [0] MIN Duty = 5000%(X100), DQS PI = 34
2349 22:58:48.295251 [0] AVG Duty = 5078%(X100)
2350 22:58:48.295359
2351 22:58:48.298420 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2352 22:58:48.298502
2353 22:58:48.301663 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2354 22:58:48.305024 [DutyScan_Calibration_Flow] ====Done====
2355 22:58:48.305106
2356 22:58:48.308255 [DutyScan_Calibration_Flow] k_type=3
2357 22:58:48.325004
2358 22:58:48.325117 ==DQM 0 ==
2359 22:58:48.328230 Final DQM duty delay cell = 0
2360 22:58:48.331987 [0] MAX Duty = 5156%(X100), DQS PI = 30
2361 22:58:48.335127 [0] MIN Duty = 4907%(X100), DQS PI = 58
2362 22:58:48.335211 [0] AVG Duty = 5031%(X100)
2363 22:58:48.338630
2364 22:58:48.338737 ==DQM 1 ==
2365 22:58:48.341931 Final DQM duty delay cell = 0
2366 22:58:48.345126 [0] MAX Duty = 5125%(X100), DQS PI = 24
2367 22:58:48.348700 [0] MIN Duty = 5062%(X100), DQS PI = 14
2368 22:58:48.348788 [0] AVG Duty = 5093%(X100)
2369 22:58:48.351749
2370 22:58:48.355553 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2371 22:58:48.355636
2372 22:58:48.358688 CH0 DQM 1 Duty spec in!! Max-Min= 63%
2373 22:58:48.362217 [DutyScan_Calibration_Flow] ====Done====
2374 22:58:48.362300
2375 22:58:48.365421 [DutyScan_Calibration_Flow] k_type=2
2376 22:58:48.381828
2377 22:58:48.381943 ==DQ 0 ==
2378 22:58:48.385199 Final DQ duty delay cell = 0
2379 22:58:48.388473 [0] MAX Duty = 5031%(X100), DQS PI = 26
2380 22:58:48.391679 [0] MIN Duty = 4875%(X100), DQS PI = 62
2381 22:58:48.391762 [0] AVG Duty = 4953%(X100)
2382 22:58:48.394834
2383 22:58:48.394915 ==DQ 1 ==
2384 22:58:48.398084 Final DQ duty delay cell = 0
2385 22:58:48.401283 [0] MAX Duty = 5093%(X100), DQS PI = 24
2386 22:58:48.404687 [0] MIN Duty = 4938%(X100), DQS PI = 36
2387 22:58:48.404771 [0] AVG Duty = 5015%(X100)
2388 22:58:48.404836
2389 22:58:48.411277 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2390 22:58:48.411408
2391 22:58:48.414702 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2392 22:58:48.418359 [DutyScan_Calibration_Flow] ====Done====
2393 22:58:48.418442 ==
2394 22:58:48.421822 Dram Type= 6, Freq= 0, CH_1, rank 0
2395 22:58:48.425037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2396 22:58:48.425119 ==
2397 22:58:48.428264 [Duty_Offset_Calibration]
2398 22:58:48.428347 B0:1 B1:0 CA:0
2399 22:58:48.428413
2400 22:58:48.431593 [DutyScan_Calibration_Flow] k_type=0
2401 22:58:48.441187
2402 22:58:48.441280 ==CLK 0==
2403 22:58:48.444136 Final CLK duty delay cell = -4
2404 22:58:48.447233 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2405 22:58:48.451048 [-4] MIN Duty = 4907%(X100), DQS PI = 50
2406 22:58:48.454139 [-4] AVG Duty = 4969%(X100)
2407 22:58:48.454243
2408 22:58:48.458093 CH1 CLK Duty spec in!! Max-Min= 124%
2409 22:58:48.461068 [DutyScan_Calibration_Flow] ====Done====
2410 22:58:48.461153
2411 22:58:48.464194 [DutyScan_Calibration_Flow] k_type=1
2412 22:58:48.480755
2413 22:58:48.480883 ==DQS 0 ==
2414 22:58:48.483891 Final DQS duty delay cell = 0
2415 22:58:48.487265 [0] MAX Duty = 5094%(X100), DQS PI = 26
2416 22:58:48.490550 [0] MIN Duty = 4844%(X100), DQS PI = 0
2417 22:58:48.490637 [0] AVG Duty = 4969%(X100)
2418 22:58:48.493761
2419 22:58:48.493846 ==DQS 1 ==
2420 22:58:48.497017 Final DQS duty delay cell = 0
2421 22:58:48.500973 [0] MAX Duty = 5187%(X100), DQS PI = 18
2422 22:58:48.504126 [0] MIN Duty = 4969%(X100), DQS PI = 10
2423 22:58:48.504212 [0] AVG Duty = 5078%(X100)
2424 22:58:48.507288
2425 22:58:48.510610 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2426 22:58:48.510720
2427 22:58:48.513868 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2428 22:58:48.517120 [DutyScan_Calibration_Flow] ====Done====
2429 22:58:48.517206
2430 22:58:48.520393 [DutyScan_Calibration_Flow] k_type=3
2431 22:58:48.537330
2432 22:58:48.537457 ==DQM 0 ==
2433 22:58:48.540416 Final DQM duty delay cell = 0
2434 22:58:48.544126 [0] MAX Duty = 5156%(X100), DQS PI = 6
2435 22:58:48.547491 [0] MIN Duty = 5031%(X100), DQS PI = 0
2436 22:58:48.547580 [0] AVG Duty = 5093%(X100)
2437 22:58:48.547666
2438 22:58:48.550576 ==DQM 1 ==
2439 22:58:48.553828 Final DQM duty delay cell = 0
2440 22:58:48.557378 [0] MAX Duty = 5062%(X100), DQS PI = 28
2441 22:58:48.560666 [0] MIN Duty = 4907%(X100), DQS PI = 34
2442 22:58:48.560783 [0] AVG Duty = 4984%(X100)
2443 22:58:48.560883
2444 22:58:48.567235 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2445 22:58:48.567383
2446 22:58:48.570899 CH1 DQM 1 Duty spec in!! Max-Min= 155%
2447 22:58:48.573901 [DutyScan_Calibration_Flow] ====Done====
2448 22:58:48.573985
2449 22:58:48.577323 [DutyScan_Calibration_Flow] k_type=2
2450 22:58:48.592781
2451 22:58:48.592897 ==DQ 0 ==
2452 22:58:48.596141 Final DQ duty delay cell = -4
2453 22:58:48.599916 [-4] MAX Duty = 5094%(X100), DQS PI = 12
2454 22:58:48.603148 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2455 22:58:48.606468 [-4] AVG Duty = 5016%(X100)
2456 22:58:48.606552
2457 22:58:48.606617 ==DQ 1 ==
2458 22:58:48.609575 Final DQ duty delay cell = 0
2459 22:58:48.612705 [0] MAX Duty = 5125%(X100), DQS PI = 20
2460 22:58:48.615982 [0] MIN Duty = 4938%(X100), DQS PI = 34
2461 22:58:48.616064 [0] AVG Duty = 5031%(X100)
2462 22:58:48.619264
2463 22:58:48.622944 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2464 22:58:48.623104
2465 22:58:48.626191 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2466 22:58:48.629753 [DutyScan_Calibration_Flow] ====Done====
2467 22:58:48.632975 nWR fixed to 30
2468 22:58:48.633085 [ModeRegInit_LP4] CH0 RK0
2469 22:58:48.636388 [ModeRegInit_LP4] CH0 RK1
2470 22:58:48.639606 [ModeRegInit_LP4] CH1 RK0
2471 22:58:48.642730 [ModeRegInit_LP4] CH1 RK1
2472 22:58:48.642854 match AC timing 7
2473 22:58:48.646665 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2474 22:58:48.653204 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2475 22:58:48.656409 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2476 22:58:48.659615 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2477 22:58:48.666712 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2478 22:58:48.666893 ==
2479 22:58:48.669795 Dram Type= 6, Freq= 0, CH_0, rank 0
2480 22:58:48.672819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2481 22:58:48.672933 ==
2482 22:58:48.680005 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2483 22:58:48.686295 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2484 22:58:48.693448 [CA 0] Center 39 (8~70) winsize 63
2485 22:58:48.696467 [CA 1] Center 39 (8~70) winsize 63
2486 22:58:48.700286 [CA 2] Center 35 (5~66) winsize 62
2487 22:58:48.703474 [CA 3] Center 34 (4~65) winsize 62
2488 22:58:48.706910 [CA 4] Center 33 (3~64) winsize 62
2489 22:58:48.709882 [CA 5] Center 32 (3~62) winsize 60
2490 22:58:48.710029
2491 22:58:48.713121 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2492 22:58:48.713264
2493 22:58:48.716811 [CATrainingPosCal] consider 1 rank data
2494 22:58:48.720090 u2DelayCellTimex100 = 270/100 ps
2495 22:58:48.723423 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2496 22:58:48.726481 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2497 22:58:48.732934 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2498 22:58:48.736774 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2499 22:58:48.739762 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2500 22:58:48.742907 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2501 22:58:48.743061
2502 22:58:48.746482 CA PerBit enable=1, Macro0, CA PI delay=32
2503 22:58:48.746719
2504 22:58:48.750299 [CBTSetCACLKResult] CA Dly = 32
2505 22:58:48.750546 CS Dly: 6 (0~37)
2506 22:58:48.753496 ==
2507 22:58:48.753788 Dram Type= 6, Freq= 0, CH_0, rank 1
2508 22:58:48.760001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2509 22:58:48.760335 ==
2510 22:58:48.763233 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2511 22:58:48.770170 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2512 22:58:48.779019 [CA 0] Center 38 (8~69) winsize 62
2513 22:58:48.782724 [CA 1] Center 38 (8~69) winsize 62
2514 22:58:48.786356 [CA 2] Center 35 (4~66) winsize 63
2515 22:58:48.789732 [CA 3] Center 34 (4~65) winsize 62
2516 22:58:48.793052 [CA 4] Center 33 (3~64) winsize 62
2517 22:58:48.795849 [CA 5] Center 32 (3~62) winsize 60
2518 22:58:48.796363
2519 22:58:48.799830 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2520 22:58:48.800368
2521 22:58:48.802619 [CATrainingPosCal] consider 2 rank data
2522 22:58:48.806615 u2DelayCellTimex100 = 270/100 ps
2523 22:58:48.809419 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2524 22:58:48.812626 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2525 22:58:48.819658 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2526 22:58:48.823069 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2527 22:58:48.826252 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2528 22:58:48.829259 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2529 22:58:48.829696
2530 22:58:48.833413 CA PerBit enable=1, Macro0, CA PI delay=32
2531 22:58:48.833954
2532 22:58:48.836478 [CBTSetCACLKResult] CA Dly = 32
2533 22:58:48.836922 CS Dly: 6 (0~38)
2534 22:58:48.837264
2535 22:58:48.839761 ----->DramcWriteLeveling(PI) begin...
2536 22:58:48.842968 ==
2537 22:58:48.843422 Dram Type= 6, Freq= 0, CH_0, rank 0
2538 22:58:48.849732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2539 22:58:48.850163 ==
2540 22:58:48.853144 Write leveling (Byte 0): 34 => 34
2541 22:58:48.856069 Write leveling (Byte 1): 27 => 27
2542 22:58:48.856497 DramcWriteLeveling(PI) end<-----
2543 22:58:48.859298
2544 22:58:48.859777 ==
2545 22:58:48.862909 Dram Type= 6, Freq= 0, CH_0, rank 0
2546 22:58:48.866100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2547 22:58:48.866633 ==
2548 22:58:48.869212 [Gating] SW mode calibration
2549 22:58:48.876209 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2550 22:58:48.879667 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2551 22:58:48.886358 0 15 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2552 22:58:48.889750 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2553 22:58:48.892567 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2554 22:58:48.899475 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2555 22:58:48.902987 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2556 22:58:48.906340 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2557 22:58:48.912661 0 15 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
2558 22:58:48.916589 0 15 28 | B1->B0 | 3333 2424 | 1 0 | (1 0) (1 0)
2559 22:58:48.919918 1 0 0 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
2560 22:58:48.926286 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2561 22:58:48.929953 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2562 22:58:48.933493 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2563 22:58:48.940170 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2564 22:58:48.943165 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2565 22:58:48.946564 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2566 22:58:48.949843 1 0 28 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
2567 22:58:48.956382 1 1 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
2568 22:58:48.959459 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2569 22:58:48.962808 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2570 22:58:48.970026 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2571 22:58:48.973253 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2572 22:58:48.976394 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2573 22:58:48.983097 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2574 22:58:48.986519 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2575 22:58:48.988944 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2576 22:58:48.996062 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 22:58:48.998972 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 22:58:49.002849 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 22:58:49.009522 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 22:58:49.012654 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2581 22:58:49.016344 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2582 22:58:49.023043 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2583 22:58:49.026465 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2584 22:58:49.029404 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2585 22:58:49.036459 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2586 22:58:49.039801 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2587 22:58:49.043248 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 22:58:49.046676 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 22:58:49.053212 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 22:58:49.056399 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2591 22:58:49.059510 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2592 22:58:49.062665 Total UI for P1: 0, mck2ui 16
2593 22:58:49.066131 best dqsien dly found for B0: ( 1, 3, 28)
2594 22:58:49.069771 Total UI for P1: 0, mck2ui 16
2595 22:58:49.072867 best dqsien dly found for B1: ( 1, 3, 28)
2596 22:58:49.076118 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2597 22:58:49.079781 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2598 22:58:49.080317
2599 22:58:49.087037 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2600 22:58:49.089814 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2601 22:58:49.090251 [Gating] SW calibration Done
2602 22:58:49.093496 ==
2603 22:58:49.096494 Dram Type= 6, Freq= 0, CH_0, rank 0
2604 22:58:49.099819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2605 22:58:49.100278 ==
2606 22:58:49.100750 RX Vref Scan: 0
2607 22:58:49.101194
2608 22:58:49.103116 RX Vref 0 -> 0, step: 1
2609 22:58:49.103641
2610 22:58:49.106275 RX Delay -40 -> 252, step: 8
2611 22:58:49.109890 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2612 22:58:49.112922 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2613 22:58:49.116405 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2614 22:58:49.123241 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
2615 22:58:49.126901 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2616 22:58:49.129936 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2617 22:58:49.133107 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2618 22:58:49.136190 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2619 22:58:49.143253 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2620 22:58:49.146641 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2621 22:58:49.149937 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2622 22:58:49.153257 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2623 22:58:49.156428 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2624 22:58:49.162966 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2625 22:58:49.167052 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2626 22:58:49.170154 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2627 22:58:49.170580 ==
2628 22:58:49.173228 Dram Type= 6, Freq= 0, CH_0, rank 0
2629 22:58:49.176426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2630 22:58:49.176852 ==
2631 22:58:49.180121 DQS Delay:
2632 22:58:49.180544 DQS0 = 0, DQS1 = 0
2633 22:58:49.183357 DQM Delay:
2634 22:58:49.183783 DQM0 = 122, DQM1 = 113
2635 22:58:49.184121 DQ Delay:
2636 22:58:49.186670 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =123
2637 22:58:49.190006 DQ4 =123, DQ5 =115, DQ6 =127, DQ7 =127
2638 22:58:49.196443 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2639 22:58:49.200098 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
2640 22:58:49.200522
2641 22:58:49.200855
2642 22:58:49.201165 ==
2643 22:58:49.202977 Dram Type= 6, Freq= 0, CH_0, rank 0
2644 22:58:49.206938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2645 22:58:49.207401 ==
2646 22:58:49.207749
2647 22:58:49.208066
2648 22:58:49.210343 TX Vref Scan disable
2649 22:58:49.213277 == TX Byte 0 ==
2650 22:58:49.216920 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2651 22:58:49.219910 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2652 22:58:49.220338 == TX Byte 1 ==
2653 22:58:49.226599 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2654 22:58:49.230228 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2655 22:58:49.230862 ==
2656 22:58:49.233208 Dram Type= 6, Freq= 0, CH_0, rank 0
2657 22:58:49.236961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2658 22:58:49.237451 ==
2659 22:58:49.250138 TX Vref=22, minBit 7, minWin=24, winSum=405
2660 22:58:49.253729 TX Vref=24, minBit 4, minWin=24, winSum=415
2661 22:58:49.256770 TX Vref=26, minBit 2, minWin=25, winSum=419
2662 22:58:49.260157 TX Vref=28, minBit 0, minWin=26, winSum=421
2663 22:58:49.263208 TX Vref=30, minBit 0, minWin=26, winSum=423
2664 22:58:49.266962 TX Vref=32, minBit 0, minWin=26, winSum=423
2665 22:58:49.273477 [TxChooseVref] Worse bit 0, Min win 26, Win sum 423, Final Vref 30
2666 22:58:49.273953
2667 22:58:49.276764 Final TX Range 1 Vref 30
2668 22:58:49.277255
2669 22:58:49.277596 ==
2670 22:58:49.280546 Dram Type= 6, Freq= 0, CH_0, rank 0
2671 22:58:49.283607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2672 22:58:49.284102 ==
2673 22:58:49.284447
2674 22:58:49.284814
2675 22:58:49.286879 TX Vref Scan disable
2676 22:58:49.290056 == TX Byte 0 ==
2677 22:58:49.293573 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2678 22:58:49.297502 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2679 22:58:49.300646 == TX Byte 1 ==
2680 22:58:49.303781 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2681 22:58:49.307408 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2682 22:58:49.307844
2683 22:58:49.310539 [DATLAT]
2684 22:58:49.310971 Freq=1200, CH0 RK0
2685 22:58:49.311420
2686 22:58:49.313479 DATLAT Default: 0xd
2687 22:58:49.313965 0, 0xFFFF, sum = 0
2688 22:58:49.316872 1, 0xFFFF, sum = 0
2689 22:58:49.317416 2, 0xFFFF, sum = 0
2690 22:58:49.320484 3, 0xFFFF, sum = 0
2691 22:58:49.320980 4, 0xFFFF, sum = 0
2692 22:58:49.323642 5, 0xFFFF, sum = 0
2693 22:58:49.324125 6, 0xFFFF, sum = 0
2694 22:58:49.326625 7, 0xFFFF, sum = 0
2695 22:58:49.327124 8, 0xFFFF, sum = 0
2696 22:58:49.330142 9, 0xFFFF, sum = 0
2697 22:58:49.334099 10, 0xFFFF, sum = 0
2698 22:58:49.334537 11, 0xFFFF, sum = 0
2699 22:58:49.337004 12, 0x0, sum = 1
2700 22:58:49.337453 13, 0x0, sum = 2
2701 22:58:49.337803 14, 0x0, sum = 3
2702 22:58:49.340098 15, 0x0, sum = 4
2703 22:58:49.340549 best_step = 13
2704 22:58:49.340893
2705 22:58:49.341209 ==
2706 22:58:49.343720 Dram Type= 6, Freq= 0, CH_0, rank 0
2707 22:58:49.350403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2708 22:58:49.350834 ==
2709 22:58:49.351173 RX Vref Scan: 1
2710 22:58:49.351544
2711 22:58:49.353828 Set Vref Range= 32 -> 127
2712 22:58:49.354252
2713 22:58:49.357067 RX Vref 32 -> 127, step: 1
2714 22:58:49.357493
2715 22:58:49.360380 RX Delay -13 -> 252, step: 4
2716 22:58:49.360875
2717 22:58:49.363482 Set Vref, RX VrefLevel [Byte0]: 32
2718 22:58:49.366827 [Byte1]: 32
2719 22:58:49.367251
2720 22:58:49.370053 Set Vref, RX VrefLevel [Byte0]: 33
2721 22:58:49.373376 [Byte1]: 33
2722 22:58:49.373801
2723 22:58:49.377338 Set Vref, RX VrefLevel [Byte0]: 34
2724 22:58:49.379891 [Byte1]: 34
2725 22:58:49.384276
2726 22:58:49.384786 Set Vref, RX VrefLevel [Byte0]: 35
2727 22:58:49.387569 [Byte1]: 35
2728 22:58:49.392102
2729 22:58:49.392521 Set Vref, RX VrefLevel [Byte0]: 36
2730 22:58:49.395394 [Byte1]: 36
2731 22:58:49.399957
2732 22:58:49.400374 Set Vref, RX VrefLevel [Byte0]: 37
2733 22:58:49.403215 [Byte1]: 37
2734 22:58:49.407754
2735 22:58:49.408173 Set Vref, RX VrefLevel [Byte0]: 38
2736 22:58:49.410834 [Byte1]: 38
2737 22:58:49.415850
2738 22:58:49.416266 Set Vref, RX VrefLevel [Byte0]: 39
2739 22:58:49.418827 [Byte1]: 39
2740 22:58:49.423366
2741 22:58:49.423786 Set Vref, RX VrefLevel [Byte0]: 40
2742 22:58:49.427198 [Byte1]: 40
2743 22:58:49.431447
2744 22:58:49.432114 Set Vref, RX VrefLevel [Byte0]: 41
2745 22:58:49.435066 [Byte1]: 41
2746 22:58:49.439279
2747 22:58:49.439752 Set Vref, RX VrefLevel [Byte0]: 42
2748 22:58:49.442504 [Byte1]: 42
2749 22:58:49.447394
2750 22:58:49.447825 Set Vref, RX VrefLevel [Byte0]: 43
2751 22:58:49.453565 [Byte1]: 43
2752 22:58:49.453989
2753 22:58:49.457128 Set Vref, RX VrefLevel [Byte0]: 44
2754 22:58:49.460383 [Byte1]: 44
2755 22:58:49.460837
2756 22:58:49.463691 Set Vref, RX VrefLevel [Byte0]: 45
2757 22:58:49.466851 [Byte1]: 45
2758 22:58:49.470726
2759 22:58:49.471145 Set Vref, RX VrefLevel [Byte0]: 46
2760 22:58:49.474138 [Byte1]: 46
2761 22:58:49.478707
2762 22:58:49.479129 Set Vref, RX VrefLevel [Byte0]: 47
2763 22:58:49.482122 [Byte1]: 47
2764 22:58:49.486766
2765 22:58:49.487185 Set Vref, RX VrefLevel [Byte0]: 48
2766 22:58:49.490035 [Byte1]: 48
2767 22:58:49.494489
2768 22:58:49.494911 Set Vref, RX VrefLevel [Byte0]: 49
2769 22:58:49.497585 [Byte1]: 49
2770 22:58:49.502716
2771 22:58:49.503137 Set Vref, RX VrefLevel [Byte0]: 50
2772 22:58:49.506005 [Byte1]: 50
2773 22:58:49.510653
2774 22:58:49.511072 Set Vref, RX VrefLevel [Byte0]: 51
2775 22:58:49.514043 [Byte1]: 51
2776 22:58:49.517906
2777 22:58:49.518330 Set Vref, RX VrefLevel [Byte0]: 52
2778 22:58:49.521722 [Byte1]: 52
2779 22:58:49.525987
2780 22:58:49.526533 Set Vref, RX VrefLevel [Byte0]: 53
2781 22:58:49.529524 [Byte1]: 53
2782 22:58:49.533936
2783 22:58:49.534358 Set Vref, RX VrefLevel [Byte0]: 54
2784 22:58:49.537126 [Byte1]: 54
2785 22:58:49.542015
2786 22:58:49.542439 Set Vref, RX VrefLevel [Byte0]: 55
2787 22:58:49.545383 [Byte1]: 55
2788 22:58:49.549636
2789 22:58:49.550061 Set Vref, RX VrefLevel [Byte0]: 56
2790 22:58:49.553171 [Byte1]: 56
2791 22:58:49.557628
2792 22:58:49.558054 Set Vref, RX VrefLevel [Byte0]: 57
2793 22:58:49.561298 [Byte1]: 57
2794 22:58:49.565340
2795 22:58:49.565761 Set Vref, RX VrefLevel [Byte0]: 58
2796 22:58:49.568991 [Byte1]: 58
2797 22:58:49.573615
2798 22:58:49.574254 Set Vref, RX VrefLevel [Byte0]: 59
2799 22:58:49.576509 [Byte1]: 59
2800 22:58:49.581165
2801 22:58:49.581856 Set Vref, RX VrefLevel [Byte0]: 60
2802 22:58:49.584902 [Byte1]: 60
2803 22:58:49.589475
2804 22:58:49.589935 Set Vref, RX VrefLevel [Byte0]: 61
2805 22:58:49.592745 [Byte1]: 61
2806 22:58:49.597393
2807 22:58:49.597821 Set Vref, RX VrefLevel [Byte0]: 62
2808 22:58:49.600528 [Byte1]: 62
2809 22:58:49.604930
2810 22:58:49.605357 Set Vref, RX VrefLevel [Byte0]: 63
2811 22:58:49.608158 [Byte1]: 63
2812 22:58:49.612694
2813 22:58:49.613121 Set Vref, RX VrefLevel [Byte0]: 64
2814 22:58:49.616192 [Byte1]: 64
2815 22:58:49.620693
2816 22:58:49.621134 Set Vref, RX VrefLevel [Byte0]: 65
2817 22:58:49.623895 [Byte1]: 65
2818 22:58:49.628981
2819 22:58:49.629568 Set Vref, RX VrefLevel [Byte0]: 66
2820 22:58:49.632321 [Byte1]: 66
2821 22:58:49.636546
2822 22:58:49.636976 Set Vref, RX VrefLevel [Byte0]: 67
2823 22:58:49.639667 [Byte1]: 67
2824 22:58:49.644419
2825 22:58:49.644889 Set Vref, RX VrefLevel [Byte0]: 68
2826 22:58:49.647757 [Byte1]: 68
2827 22:58:49.652235
2828 22:58:49.652795 Final RX Vref Byte 0 = 56 to rank0
2829 22:58:49.656074 Final RX Vref Byte 1 = 57 to rank0
2830 22:58:49.658930 Final RX Vref Byte 0 = 56 to rank1
2831 22:58:49.662610 Final RX Vref Byte 1 = 57 to rank1==
2832 22:58:49.665920 Dram Type= 6, Freq= 0, CH_0, rank 0
2833 22:58:49.669005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2834 22:58:49.672537 ==
2835 22:58:49.672967 DQS Delay:
2836 22:58:49.673307 DQS0 = 0, DQS1 = 0
2837 22:58:49.676288 DQM Delay:
2838 22:58:49.676766 DQM0 = 121, DQM1 = 113
2839 22:58:49.679620 DQ Delay:
2840 22:58:49.682501 DQ0 =120, DQ1 =122, DQ2 =120, DQ3 =120
2841 22:58:49.685805 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2842 22:58:49.689204 DQ8 =100, DQ9 =102, DQ10 =116, DQ11 =106
2843 22:58:49.692530 DQ12 =120, DQ13 =118, DQ14 =126, DQ15 =122
2844 22:58:49.692961
2845 22:58:49.693298
2846 22:58:49.699104 [DQSOSCAuto] RK0, (LSB)MR18= 0x130c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2847 22:58:49.702419 CH0 RK0: MR19=404, MR18=130C
2848 22:58:49.709159 CH0_RK0: MR19=0x404, MR18=0x130C, DQSOSC=402, MR23=63, INC=40, DEC=27
2849 22:58:49.709602
2850 22:58:49.712358 ----->DramcWriteLeveling(PI) begin...
2851 22:58:49.712795 ==
2852 22:58:49.715711 Dram Type= 6, Freq= 0, CH_0, rank 1
2853 22:58:49.719416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2854 22:58:49.722838 ==
2855 22:58:49.723267 Write leveling (Byte 0): 33 => 33
2856 22:58:49.726168 Write leveling (Byte 1): 29 => 29
2857 22:58:49.729477 DramcWriteLeveling(PI) end<-----
2858 22:58:49.729905
2859 22:58:49.730243 ==
2860 22:58:49.732730 Dram Type= 6, Freq= 0, CH_0, rank 1
2861 22:58:49.739123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2862 22:58:49.739597 ==
2863 22:58:49.739943 [Gating] SW mode calibration
2864 22:58:49.749021 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2865 22:58:49.752771 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2866 22:58:49.755875 0 15 0 | B1->B0 | 3333 2e2e | 0 1 | (0 0) (0 0)
2867 22:58:49.762456 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2868 22:58:49.766235 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2869 22:58:49.769222 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2870 22:58:49.776172 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2871 22:58:49.779823 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2872 22:58:49.782591 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2873 22:58:49.789458 0 15 28 | B1->B0 | 2f2f 2c2c | 1 1 | (1 0) (1 0)
2874 22:58:49.792811 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2875 22:58:49.796388 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2876 22:58:49.802925 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2877 22:58:49.805957 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2878 22:58:49.809259 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2879 22:58:49.816370 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2880 22:58:49.819466 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2881 22:58:49.822669 1 0 28 | B1->B0 | 3d3d 3a3a | 0 0 | (0 0) (0 0)
2882 22:58:49.829332 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2883 22:58:49.832651 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2884 22:58:49.835899 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2885 22:58:49.839157 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2886 22:58:49.845566 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2887 22:58:49.849452 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2888 22:58:49.852489 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2889 22:58:49.859266 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2890 22:58:49.862183 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 22:58:49.866091 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 22:58:49.872879 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 22:58:49.875837 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 22:58:49.879483 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 22:58:49.886220 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 22:58:49.889133 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 22:58:49.892421 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 22:58:49.899198 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 22:58:49.902557 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 22:58:49.905895 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 22:58:49.913075 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 22:58:49.916228 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 22:58:49.919611 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 22:58:49.922659 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
2905 22:58:49.929536 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2906 22:58:49.932889 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2907 22:58:49.936253 Total UI for P1: 0, mck2ui 16
2908 22:58:49.939456 best dqsien dly found for B1: ( 1, 3, 26)
2909 22:58:49.942764 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2910 22:58:49.945865 Total UI for P1: 0, mck2ui 16
2911 22:58:49.949799 best dqsien dly found for B0: ( 1, 3, 30)
2912 22:58:49.953045 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2913 22:58:49.956212 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
2914 22:58:49.956878
2915 22:58:49.963043 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2916 22:58:49.966196 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
2917 22:58:49.970020 [Gating] SW calibration Done
2918 22:58:49.970514 ==
2919 22:58:49.973094 Dram Type= 6, Freq= 0, CH_0, rank 1
2920 22:58:49.976535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2921 22:58:49.977095 ==
2922 22:58:49.977550 RX Vref Scan: 0
2923 22:58:49.977914
2924 22:58:49.979676 RX Vref 0 -> 0, step: 1
2925 22:58:49.980202
2926 22:58:49.983415 RX Delay -40 -> 252, step: 8
2927 22:58:49.986428 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2928 22:58:49.989850 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2929 22:58:49.992809 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2930 22:58:49.999831 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2931 22:58:50.002890 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2932 22:58:50.006844 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2933 22:58:50.010079 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2934 22:58:50.013201 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2935 22:58:50.019789 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
2936 22:58:50.023510 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2937 22:58:50.026640 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2938 22:58:50.029805 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2939 22:58:50.033559 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2940 22:58:50.039871 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2941 22:58:50.043184 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2942 22:58:50.046598 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2943 22:58:50.047116 ==
2944 22:58:50.050341 Dram Type= 6, Freq= 0, CH_0, rank 1
2945 22:58:50.053463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2946 22:58:50.054032 ==
2947 22:58:50.056637 DQS Delay:
2948 22:58:50.057083 DQS0 = 0, DQS1 = 0
2949 22:58:50.057423 DQM Delay:
2950 22:58:50.060245 DQM0 = 122, DQM1 = 113
2951 22:58:50.060672 DQ Delay:
2952 22:58:50.063728 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2953 22:58:50.066797 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2954 22:58:50.070092 DQ8 =103, DQ9 =99, DQ10 =115, DQ11 =107
2955 22:58:50.076979 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
2956 22:58:50.077408
2957 22:58:50.077743
2958 22:58:50.078051 ==
2959 22:58:50.079948 Dram Type= 6, Freq= 0, CH_0, rank 1
2960 22:58:50.083500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2961 22:58:50.083930 ==
2962 22:58:50.084268
2963 22:58:50.084582
2964 22:58:50.086674 TX Vref Scan disable
2965 22:58:50.087099 == TX Byte 0 ==
2966 22:58:50.093197 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2967 22:58:50.096705 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2968 22:58:50.097130 == TX Byte 1 ==
2969 22:58:50.103621 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2970 22:58:50.106449 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2971 22:58:50.106876 ==
2972 22:58:50.109654 Dram Type= 6, Freq= 0, CH_0, rank 1
2973 22:58:50.112904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2974 22:58:50.113332 ==
2975 22:58:50.126401 TX Vref=22, minBit 1, minWin=25, winSum=414
2976 22:58:50.129891 TX Vref=24, minBit 3, minWin=25, winSum=419
2977 22:58:50.133220 TX Vref=26, minBit 0, minWin=26, winSum=421
2978 22:58:50.136324 TX Vref=28, minBit 0, minWin=26, winSum=426
2979 22:58:50.140109 TX Vref=30, minBit 0, minWin=26, winSum=430
2980 22:58:50.143414 TX Vref=32, minBit 0, minWin=26, winSum=429
2981 22:58:50.149944 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 30
2982 22:58:50.150380
2983 22:58:50.153117 Final TX Range 1 Vref 30
2984 22:58:50.153564
2985 22:58:50.153930 ==
2986 22:58:50.156370 Dram Type= 6, Freq= 0, CH_0, rank 1
2987 22:58:50.159853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2988 22:58:50.160278 ==
2989 22:58:50.160616
2990 22:58:50.163036
2991 22:58:50.163615 TX Vref Scan disable
2992 22:58:50.166243 == TX Byte 0 ==
2993 22:58:50.170117 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2994 22:58:50.173463 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2995 22:58:50.176497 == TX Byte 1 ==
2996 22:58:50.179591 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2997 22:58:50.183293 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2998 22:58:50.183864
2999 22:58:50.186414 [DATLAT]
3000 22:58:50.186851 Freq=1200, CH0 RK1
3001 22:58:50.187187
3002 22:58:50.190148 DATLAT Default: 0xd
3003 22:58:50.190569 0, 0xFFFF, sum = 0
3004 22:58:50.193067 1, 0xFFFF, sum = 0
3005 22:58:50.193494 2, 0xFFFF, sum = 0
3006 22:58:50.196872 3, 0xFFFF, sum = 0
3007 22:58:50.197296 4, 0xFFFF, sum = 0
3008 22:58:50.199914 5, 0xFFFF, sum = 0
3009 22:58:50.200349 6, 0xFFFF, sum = 0
3010 22:58:50.203065 7, 0xFFFF, sum = 0
3011 22:58:50.203603 8, 0xFFFF, sum = 0
3012 22:58:50.206758 9, 0xFFFF, sum = 0
3013 22:58:50.209856 10, 0xFFFF, sum = 0
3014 22:58:50.210358 11, 0xFFFF, sum = 0
3015 22:58:50.213500 12, 0x0, sum = 1
3016 22:58:50.213957 13, 0x0, sum = 2
3017 22:58:50.214361 14, 0x0, sum = 3
3018 22:58:50.216618 15, 0x0, sum = 4
3019 22:58:50.217106 best_step = 13
3020 22:58:50.217451
3021 22:58:50.217768 ==
3022 22:58:50.219780 Dram Type= 6, Freq= 0, CH_0, rank 1
3023 22:58:50.227168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3024 22:58:50.227708 ==
3025 22:58:50.228052 RX Vref Scan: 0
3026 22:58:50.228441
3027 22:58:50.230400 RX Vref 0 -> 0, step: 1
3028 22:58:50.230885
3029 22:58:50.233470 RX Delay -13 -> 252, step: 4
3030 22:58:50.236762 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3031 22:58:50.240318 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3032 22:58:50.247020 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3033 22:58:50.250307 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3034 22:58:50.253484 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3035 22:58:50.256734 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3036 22:58:50.260377 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3037 22:58:50.266837 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3038 22:58:50.270065 iDelay=195, Bit 8, Center 102 (35 ~ 170) 136
3039 22:58:50.273383 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3040 22:58:50.276729 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3041 22:58:50.280582 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3042 22:58:50.286656 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3043 22:58:50.290275 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3044 22:58:50.293232 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3045 22:58:50.297003 iDelay=195, Bit 15, Center 120 (59 ~ 182) 124
3046 22:58:50.297429 ==
3047 22:58:50.300249 Dram Type= 6, Freq= 0, CH_0, rank 1
3048 22:58:50.303718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3049 22:58:50.306814 ==
3050 22:58:50.307370 DQS Delay:
3051 22:58:50.307735 DQS0 = 0, DQS1 = 0
3052 22:58:50.310453 DQM Delay:
3053 22:58:50.310875 DQM0 = 120, DQM1 = 112
3054 22:58:50.313943 DQ Delay:
3055 22:58:50.316950 DQ0 =118, DQ1 =120, DQ2 =118, DQ3 =118
3056 22:58:50.320724 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3057 22:58:50.323703 DQ8 =102, DQ9 =100, DQ10 =112, DQ11 =104
3058 22:58:50.326712 DQ12 =118, DQ13 =118, DQ14 =122, DQ15 =120
3059 22:58:50.327138
3060 22:58:50.327557
3061 22:58:50.334022 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 403 ps
3062 22:58:50.337267 CH0 RK1: MR19=403, MR18=10F1
3063 22:58:50.343840 CH0_RK1: MR19=0x403, MR18=0x10F1, DQSOSC=403, MR23=63, INC=40, DEC=26
3064 22:58:50.347092 [RxdqsGatingPostProcess] freq 1200
3065 22:58:50.354176 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3066 22:58:50.354601 best DQS0 dly(2T, 0.5T) = (0, 11)
3067 22:58:50.357490 best DQS1 dly(2T, 0.5T) = (0, 11)
3068 22:58:50.360837 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3069 22:58:50.363785 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3070 22:58:50.366977 best DQS0 dly(2T, 0.5T) = (0, 11)
3071 22:58:50.370204 best DQS1 dly(2T, 0.5T) = (0, 11)
3072 22:58:50.373520 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3073 22:58:50.377515 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3074 22:58:50.380879 Pre-setting of DQS Precalculation
3075 22:58:50.384010 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3076 22:58:50.387169 ==
3077 22:58:50.390835 Dram Type= 6, Freq= 0, CH_1, rank 0
3078 22:58:50.393929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3079 22:58:50.394523 ==
3080 22:58:50.397598 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3081 22:58:50.403586 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3082 22:58:50.412936 [CA 0] Center 37 (7~68) winsize 62
3083 22:58:50.416327 [CA 1] Center 37 (7~68) winsize 62
3084 22:58:50.419906 [CA 2] Center 35 (5~65) winsize 61
3085 22:58:50.423082 [CA 3] Center 34 (4~64) winsize 61
3086 22:58:50.426212 [CA 4] Center 34 (4~64) winsize 61
3087 22:58:50.429874 [CA 5] Center 33 (3~63) winsize 61
3088 22:58:50.430501
3089 22:58:50.432778 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3090 22:58:50.433332
3091 22:58:50.435985 [CATrainingPosCal] consider 1 rank data
3092 22:58:50.439284 u2DelayCellTimex100 = 270/100 ps
3093 22:58:50.443163 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3094 22:58:50.446531 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3095 22:58:50.453006 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3096 22:58:50.456291 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3097 22:58:50.460077 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3098 22:58:50.463223 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3099 22:58:50.463691
3100 22:58:50.466783 CA PerBit enable=1, Macro0, CA PI delay=33
3101 22:58:50.467207
3102 22:58:50.469818 [CBTSetCACLKResult] CA Dly = 33
3103 22:58:50.470242 CS Dly: 8 (0~39)
3104 22:58:50.470578 ==
3105 22:58:50.473090 Dram Type= 6, Freq= 0, CH_1, rank 1
3106 22:58:50.479440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3107 22:58:50.479867 ==
3108 22:58:50.482767 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3109 22:58:50.489451 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3110 22:58:50.498897 [CA 0] Center 37 (7~68) winsize 62
3111 22:58:50.502059 [CA 1] Center 37 (7~68) winsize 62
3112 22:58:50.505007 [CA 2] Center 35 (5~65) winsize 61
3113 22:58:50.508660 [CA 3] Center 34 (4~64) winsize 61
3114 22:58:50.511624 [CA 4] Center 34 (4~65) winsize 62
3115 22:58:50.515219 [CA 5] Center 34 (4~64) winsize 61
3116 22:58:50.515745
3117 22:58:50.518260 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3118 22:58:50.518682
3119 22:58:50.521839 [CATrainingPosCal] consider 2 rank data
3120 22:58:50.525353 u2DelayCellTimex100 = 270/100 ps
3121 22:58:50.528505 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3122 22:58:50.531812 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3123 22:58:50.538555 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3124 22:58:50.541812 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3125 22:58:50.544943 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3126 22:58:50.548335 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3127 22:58:50.548831
3128 22:58:50.551698 CA PerBit enable=1, Macro0, CA PI delay=33
3129 22:58:50.552121
3130 22:58:50.554936 [CBTSetCACLKResult] CA Dly = 33
3131 22:58:50.555399 CS Dly: 9 (0~41)
3132 22:58:50.555765
3133 22:58:50.558350 ----->DramcWriteLeveling(PI) begin...
3134 22:58:50.562106 ==
3135 22:58:50.565271 Dram Type= 6, Freq= 0, CH_1, rank 0
3136 22:58:50.568276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3137 22:58:50.568704 ==
3138 22:58:50.571739 Write leveling (Byte 0): 25 => 25
3139 22:58:50.575293 Write leveling (Byte 1): 29 => 29
3140 22:58:50.578496 DramcWriteLeveling(PI) end<-----
3141 22:58:50.578921
3142 22:58:50.579254 ==
3143 22:58:50.582131 Dram Type= 6, Freq= 0, CH_1, rank 0
3144 22:58:50.585401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3145 22:58:50.585917 ==
3146 22:58:50.588770 [Gating] SW mode calibration
3147 22:58:50.595541 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3148 22:58:50.598622 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3149 22:58:50.605615 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3150 22:58:50.608735 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3151 22:58:50.611771 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3152 22:58:50.618571 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3153 22:58:50.621629 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3154 22:58:50.625276 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3155 22:58:50.632032 0 15 24 | B1->B0 | 3131 2b2b | 1 0 | (1 0) (0 0)
3156 22:58:50.634970 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3157 22:58:50.638717 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3158 22:58:50.644999 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3159 22:58:50.648746 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3160 22:58:50.652100 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3161 22:58:50.658847 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3162 22:58:50.662115 1 0 20 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
3163 22:58:50.665416 1 0 24 | B1->B0 | 3838 4343 | 0 0 | (0 0) (0 0)
3164 22:58:50.672334 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 22:58:50.675373 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 22:58:50.678559 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 22:58:50.681896 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3168 22:58:50.689029 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3169 22:58:50.692368 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3170 22:58:50.695642 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3171 22:58:50.702213 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3172 22:58:50.705332 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3173 22:58:50.709202 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 22:58:50.716100 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 22:58:50.719145 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 22:58:50.721986 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 22:58:50.728920 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 22:58:50.732493 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 22:58:50.735323 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 22:58:50.742057 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 22:58:50.745630 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 22:58:50.748722 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 22:58:50.755538 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 22:58:50.758922 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 22:58:50.762262 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 22:58:50.765589 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 22:58:50.772221 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3188 22:58:50.775396 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3189 22:58:50.779059 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3190 22:58:50.781979 Total UI for P1: 0, mck2ui 16
3191 22:58:50.785673 best dqsien dly found for B0: ( 1, 3, 26)
3192 22:58:50.788905 Total UI for P1: 0, mck2ui 16
3193 22:58:50.792090 best dqsien dly found for B1: ( 1, 3, 26)
3194 22:58:50.795354 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3195 22:58:50.798773 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3196 22:58:50.799200
3197 22:58:50.805815 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3198 22:58:50.809114 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3199 22:58:50.812267 [Gating] SW calibration Done
3200 22:58:50.812692 ==
3201 22:58:50.815714 Dram Type= 6, Freq= 0, CH_1, rank 0
3202 22:58:50.818772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3203 22:58:50.819203 ==
3204 22:58:50.819591 RX Vref Scan: 0
3205 22:58:50.819912
3206 22:58:50.822185 RX Vref 0 -> 0, step: 1
3207 22:58:50.822613
3208 22:58:50.825505 RX Delay -40 -> 252, step: 8
3209 22:58:50.828451 iDelay=200, Bit 0, Center 127 (56 ~ 199) 144
3210 22:58:50.832180 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3211 22:58:50.838891 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3212 22:58:50.841990 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3213 22:58:50.845609 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3214 22:58:50.848507 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3215 22:58:50.852409 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3216 22:58:50.858494 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3217 22:58:50.862396 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3218 22:58:50.865577 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3219 22:58:50.868895 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3220 22:58:50.872078 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3221 22:58:50.878774 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3222 22:58:50.882001 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3223 22:58:50.885979 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3224 22:58:50.888875 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3225 22:58:50.889304 ==
3226 22:58:50.892401 Dram Type= 6, Freq= 0, CH_1, rank 0
3227 22:58:50.895664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3228 22:58:50.898897 ==
3229 22:58:50.899599 DQS Delay:
3230 22:58:50.900103 DQS0 = 0, DQS1 = 0
3231 22:58:50.902171 DQM Delay:
3232 22:58:50.902663 DQM0 = 120, DQM1 = 116
3233 22:58:50.905378 DQ Delay:
3234 22:58:50.908907 DQ0 =127, DQ1 =115, DQ2 =107, DQ3 =119
3235 22:58:50.912003 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =119
3236 22:58:50.915250 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3237 22:58:50.918489 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3238 22:58:50.918916
3239 22:58:50.919253
3240 22:58:50.919615 ==
3241 22:58:50.921856 Dram Type= 6, Freq= 0, CH_1, rank 0
3242 22:58:50.925610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3243 22:58:50.926039 ==
3244 22:58:50.926398
3245 22:58:50.928601
3246 22:58:50.929022 TX Vref Scan disable
3247 22:58:50.932353 == TX Byte 0 ==
3248 22:58:50.935709 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3249 22:58:50.938611 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3250 22:58:50.942328 == TX Byte 1 ==
3251 22:58:50.945500 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3252 22:58:50.949185 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3253 22:58:50.949612 ==
3254 22:58:50.952441 Dram Type= 6, Freq= 0, CH_1, rank 0
3255 22:58:50.955859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3256 22:58:50.958880 ==
3257 22:58:50.969592 TX Vref=22, minBit 2, minWin=25, winSum=412
3258 22:58:50.972934 TX Vref=24, minBit 9, minWin=25, winSum=419
3259 22:58:50.976223 TX Vref=26, minBit 1, minWin=26, winSum=426
3260 22:58:50.979421 TX Vref=28, minBit 9, minWin=25, winSum=430
3261 22:58:50.982843 TX Vref=30, minBit 2, minWin=26, winSum=429
3262 22:58:50.985765 TX Vref=32, minBit 2, minWin=26, winSum=429
3263 22:58:50.992927 [TxChooseVref] Worse bit 2, Min win 26, Win sum 429, Final Vref 30
3264 22:58:50.993365
3265 22:58:50.996158 Final TX Range 1 Vref 30
3266 22:58:50.996588
3267 22:58:50.996922 ==
3268 22:58:50.999654 Dram Type= 6, Freq= 0, CH_1, rank 0
3269 22:58:51.002598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3270 22:58:51.003026 ==
3271 22:58:51.003399
3272 22:58:51.003719
3273 22:58:51.005890 TX Vref Scan disable
3274 22:58:51.009171 == TX Byte 0 ==
3275 22:58:51.013091 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3276 22:58:51.016046 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3277 22:58:51.019508 == TX Byte 1 ==
3278 22:58:51.022532 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3279 22:58:51.026302 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3280 22:58:51.027038
3281 22:58:51.029637 [DATLAT]
3282 22:58:51.030056 Freq=1200, CH1 RK0
3283 22:58:51.030456
3284 22:58:51.032973 DATLAT Default: 0xd
3285 22:58:51.033651 0, 0xFFFF, sum = 0
3286 22:58:51.035822 1, 0xFFFF, sum = 0
3287 22:58:51.036435 2, 0xFFFF, sum = 0
3288 22:58:51.039700 3, 0xFFFF, sum = 0
3289 22:58:51.040133 4, 0xFFFF, sum = 0
3290 22:58:51.042992 5, 0xFFFF, sum = 0
3291 22:58:51.043457 6, 0xFFFF, sum = 0
3292 22:58:51.046038 7, 0xFFFF, sum = 0
3293 22:58:51.046463 8, 0xFFFF, sum = 0
3294 22:58:51.049604 9, 0xFFFF, sum = 0
3295 22:58:51.052683 10, 0xFFFF, sum = 0
3296 22:58:51.053114 11, 0xFFFF, sum = 0
3297 22:58:51.056237 12, 0x0, sum = 1
3298 22:58:51.056671 13, 0x0, sum = 2
3299 22:58:51.057015 14, 0x0, sum = 3
3300 22:58:51.059151 15, 0x0, sum = 4
3301 22:58:51.059601 best_step = 13
3302 22:58:51.059939
3303 22:58:51.060266 ==
3304 22:58:51.062817 Dram Type= 6, Freq= 0, CH_1, rank 0
3305 22:58:51.069743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3306 22:58:51.070174 ==
3307 22:58:51.070512 RX Vref Scan: 1
3308 22:58:51.070825
3309 22:58:51.072774 Set Vref Range= 32 -> 127
3310 22:58:51.073168
3311 22:58:51.075893 RX Vref 32 -> 127, step: 1
3312 22:58:51.076194
3313 22:58:51.076435 RX Delay -5 -> 252, step: 4
3314 22:58:51.078990
3315 22:58:51.079217 Set Vref, RX VrefLevel [Byte0]: 32
3316 22:58:51.082937 [Byte1]: 32
3317 22:58:51.086844
3318 22:58:51.087027 Set Vref, RX VrefLevel [Byte0]: 33
3319 22:58:51.090691 [Byte1]: 33
3320 22:58:51.095241
3321 22:58:51.095417 Set Vref, RX VrefLevel [Byte0]: 34
3322 22:58:51.098547 [Byte1]: 34
3323 22:58:51.103143
3324 22:58:51.103300 Set Vref, RX VrefLevel [Byte0]: 35
3325 22:58:51.106162 [Byte1]: 35
3326 22:58:51.110343
3327 22:58:51.110492 Set Vref, RX VrefLevel [Byte0]: 36
3328 22:58:51.114107 [Byte1]: 36
3329 22:58:51.118625
3330 22:58:51.118783 Set Vref, RX VrefLevel [Byte0]: 37
3331 22:58:51.121794 [Byte1]: 37
3332 22:58:51.126604
3333 22:58:51.126733 Set Vref, RX VrefLevel [Byte0]: 38
3334 22:58:51.130152 [Byte1]: 38
3335 22:58:51.134220
3336 22:58:51.134631 Set Vref, RX VrefLevel [Byte0]: 39
3337 22:58:51.137890 [Byte1]: 39
3338 22:58:51.142285
3339 22:58:51.142699 Set Vref, RX VrefLevel [Byte0]: 40
3340 22:58:51.145323 [Byte1]: 40
3341 22:58:51.149827
3342 22:58:51.150241 Set Vref, RX VrefLevel [Byte0]: 41
3343 22:58:51.153611 [Byte1]: 41
3344 22:58:51.158149
3345 22:58:51.158563 Set Vref, RX VrefLevel [Byte0]: 42
3346 22:58:51.160986 [Byte1]: 42
3347 22:58:51.166085
3348 22:58:51.166496 Set Vref, RX VrefLevel [Byte0]: 43
3349 22:58:51.168994 [Byte1]: 43
3350 22:58:51.173798
3351 22:58:51.174227 Set Vref, RX VrefLevel [Byte0]: 44
3352 22:58:51.177177 [Byte1]: 44
3353 22:58:51.181602
3354 22:58:51.182220 Set Vref, RX VrefLevel [Byte0]: 45
3355 22:58:51.184890 [Byte1]: 45
3356 22:58:51.189554
3357 22:58:51.189969 Set Vref, RX VrefLevel [Byte0]: 46
3358 22:58:51.193242 [Byte1]: 46
3359 22:58:51.197498
3360 22:58:51.197917 Set Vref, RX VrefLevel [Byte0]: 47
3361 22:58:51.200846 [Byte1]: 47
3362 22:58:51.205374
3363 22:58:51.205793 Set Vref, RX VrefLevel [Byte0]: 48
3364 22:58:51.208648 [Byte1]: 48
3365 22:58:51.212953
3366 22:58:51.213633 Set Vref, RX VrefLevel [Byte0]: 49
3367 22:58:51.216022 [Byte1]: 49
3368 22:58:51.220848
3369 22:58:51.221264 Set Vref, RX VrefLevel [Byte0]: 50
3370 22:58:51.224394 [Byte1]: 50
3371 22:58:51.228996
3372 22:58:51.229406 Set Vref, RX VrefLevel [Byte0]: 51
3373 22:58:51.232135 [Byte1]: 51
3374 22:58:51.236910
3375 22:58:51.237350 Set Vref, RX VrefLevel [Byte0]: 52
3376 22:58:51.239924 [Byte1]: 52
3377 22:58:51.243952
3378 22:58:51.244391 Set Vref, RX VrefLevel [Byte0]: 53
3379 22:58:51.247883 [Byte1]: 53
3380 22:58:51.252379
3381 22:58:51.252798 Set Vref, RX VrefLevel [Byte0]: 54
3382 22:58:51.255970 [Byte1]: 54
3383 22:58:51.260312
3384 22:58:51.260742 Set Vref, RX VrefLevel [Byte0]: 55
3385 22:58:51.263359 [Byte1]: 55
3386 22:58:51.268203
3387 22:58:51.268631 Set Vref, RX VrefLevel [Byte0]: 56
3388 22:58:51.271297 [Byte1]: 56
3389 22:58:51.276017
3390 22:58:51.276462 Set Vref, RX VrefLevel [Byte0]: 57
3391 22:58:51.278878 [Byte1]: 57
3392 22:58:51.283839
3393 22:58:51.284271 Set Vref, RX VrefLevel [Byte0]: 58
3394 22:58:51.286897 [Byte1]: 58
3395 22:58:51.291675
3396 22:58:51.292108 Set Vref, RX VrefLevel [Byte0]: 59
3397 22:58:51.294826 [Byte1]: 59
3398 22:58:51.299309
3399 22:58:51.299803 Set Vref, RX VrefLevel [Byte0]: 60
3400 22:58:51.302590 [Byte1]: 60
3401 22:58:51.307228
3402 22:58:51.307699 Set Vref, RX VrefLevel [Byte0]: 61
3403 22:58:51.310532 [Byte1]: 61
3404 22:58:51.315002
3405 22:58:51.315310 Set Vref, RX VrefLevel [Byte0]: 62
3406 22:58:51.318204 [Byte1]: 62
3407 22:58:51.322750
3408 22:58:51.323027 Set Vref, RX VrefLevel [Byte0]: 63
3409 22:58:51.325813 [Byte1]: 63
3410 22:58:51.330428
3411 22:58:51.330629 Set Vref, RX VrefLevel [Byte0]: 64
3412 22:58:51.334087 [Byte1]: 64
3413 22:58:51.338642
3414 22:58:51.338812 Set Vref, RX VrefLevel [Byte0]: 65
3415 22:58:51.341688 [Byte1]: 65
3416 22:58:51.346466
3417 22:58:51.346680 Set Vref, RX VrefLevel [Byte0]: 66
3418 22:58:51.349576 [Byte1]: 66
3419 22:58:51.354059
3420 22:58:51.354246 Set Vref, RX VrefLevel [Byte0]: 67
3421 22:58:51.357243 [Byte1]: 67
3422 22:58:51.362098
3423 22:58:51.362280 Set Vref, RX VrefLevel [Byte0]: 68
3424 22:58:51.365391 [Byte1]: 68
3425 22:58:51.370094
3426 22:58:51.370358 Set Vref, RX VrefLevel [Byte0]: 69
3427 22:58:51.373075 [Byte1]: 69
3428 22:58:51.377628
3429 22:58:51.377874 Final RX Vref Byte 0 = 52 to rank0
3430 22:58:51.381222 Final RX Vref Byte 1 = 48 to rank0
3431 22:58:51.384572 Final RX Vref Byte 0 = 52 to rank1
3432 22:58:51.387854 Final RX Vref Byte 1 = 48 to rank1==
3433 22:58:51.391228 Dram Type= 6, Freq= 0, CH_1, rank 0
3434 22:58:51.394355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3435 22:58:51.398112 ==
3436 22:58:51.398571 DQS Delay:
3437 22:58:51.398914 DQS0 = 0, DQS1 = 0
3438 22:58:51.401119 DQM Delay:
3439 22:58:51.401548 DQM0 = 120, DQM1 = 116
3440 22:58:51.404629 DQ Delay:
3441 22:58:51.407947 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3442 22:58:51.411113 DQ4 =118, DQ5 =130, DQ6 =130, DQ7 =120
3443 22:58:51.414475 DQ8 =102, DQ9 =106, DQ10 =118, DQ11 =108
3444 22:58:51.418553 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3445 22:58:51.419081
3446 22:58:51.419473
3447 22:58:51.424819 [DQSOSCAuto] RK0, (LSB)MR18= 0x316, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3448 22:58:51.428190 CH1 RK0: MR19=404, MR18=316
3449 22:58:51.434180 CH1_RK0: MR19=0x404, MR18=0x316, DQSOSC=401, MR23=63, INC=40, DEC=27
3450 22:58:51.434700
3451 22:58:51.438025 ----->DramcWriteLeveling(PI) begin...
3452 22:58:51.438616 ==
3453 22:58:51.441087 Dram Type= 6, Freq= 0, CH_1, rank 1
3454 22:58:51.444800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3455 22:58:51.445246 ==
3456 22:58:51.448099 Write leveling (Byte 0): 26 => 26
3457 22:58:51.451436 Write leveling (Byte 1): 30 => 30
3458 22:58:51.454897 DramcWriteLeveling(PI) end<-----
3459 22:58:51.455367
3460 22:58:51.455735 ==
3461 22:58:51.458114 Dram Type= 6, Freq= 0, CH_1, rank 1
3462 22:58:51.464584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3463 22:58:51.465024 ==
3464 22:58:51.465366 [Gating] SW mode calibration
3465 22:58:51.474344 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3466 22:58:51.477702 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3467 22:58:51.480902 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3468 22:58:51.487677 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3469 22:58:51.491242 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3470 22:58:51.494148 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3471 22:58:51.500598 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3472 22:58:51.504412 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3473 22:58:51.507547 0 15 24 | B1->B0 | 2b2b 3333 | 0 1 | (0 1) (1 0)
3474 22:58:51.514095 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 0)
3475 22:58:51.517283 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3476 22:58:51.520599 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3477 22:58:51.527767 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3478 22:58:51.531016 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3479 22:58:51.534149 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3480 22:58:51.541124 1 0 20 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
3481 22:58:51.544338 1 0 24 | B1->B0 | 4242 2828 | 0 0 | (0 0) (0 0)
3482 22:58:51.547508 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 22:58:51.550532 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3484 22:58:51.557785 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 22:58:51.561043 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 22:58:51.564431 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3487 22:58:51.570884 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3488 22:58:51.573928 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3489 22:58:51.577662 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3490 22:58:51.584035 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3491 22:58:51.587226 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 22:58:51.590514 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 22:58:51.597769 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 22:58:51.600778 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 22:58:51.603876 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 22:58:51.610431 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 22:58:51.614166 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 22:58:51.617134 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 22:58:51.624046 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 22:58:51.627276 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 22:58:51.630482 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 22:58:51.637642 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 22:58:51.640459 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 22:58:51.644136 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3505 22:58:51.650580 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3506 22:58:51.650857 Total UI for P1: 0, mck2ui 16
3507 22:58:51.657006 best dqsien dly found for B1: ( 1, 3, 20)
3508 22:58:51.660663 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3509 22:58:51.663918 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 22:58:51.667133 Total UI for P1: 0, mck2ui 16
3511 22:58:51.670347 best dqsien dly found for B0: ( 1, 3, 26)
3512 22:58:51.673725 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3513 22:58:51.677623 best DQS1 dly(MCK, UI, PI) = (1, 3, 20)
3514 22:58:51.677892
3515 22:58:51.680760 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3516 22:58:51.687472 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 20)
3517 22:58:51.687814 [Gating] SW calibration Done
3518 22:58:51.688022 ==
3519 22:58:51.690858 Dram Type= 6, Freq= 0, CH_1, rank 1
3520 22:58:51.697184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3521 22:58:51.697447 ==
3522 22:58:51.697652 RX Vref Scan: 0
3523 22:58:51.697843
3524 22:58:51.700352 RX Vref 0 -> 0, step: 1
3525 22:58:51.700618
3526 22:58:51.703450 RX Delay -40 -> 252, step: 8
3527 22:58:51.707188 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3528 22:58:51.710466 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3529 22:58:51.714100 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3530 22:58:51.720795 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3531 22:58:51.723741 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3532 22:58:51.726713 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3533 22:58:51.730530 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3534 22:58:51.733826 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3535 22:58:51.740426 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3536 22:58:51.743595 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3537 22:58:51.746769 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
3538 22:58:51.750592 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3539 22:58:51.753979 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3540 22:58:51.760189 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3541 22:58:51.763782 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3542 22:58:51.766938 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3543 22:58:51.767590 ==
3544 22:58:51.770148 Dram Type= 6, Freq= 0, CH_1, rank 1
3545 22:58:51.773937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3546 22:58:51.774408 ==
3547 22:58:51.777174 DQS Delay:
3548 22:58:51.777777 DQS0 = 0, DQS1 = 0
3549 22:58:51.780485 DQM Delay:
3550 22:58:51.781029 DQM0 = 121, DQM1 = 118
3551 22:58:51.783601 DQ Delay:
3552 22:58:51.787063 DQ0 =123, DQ1 =119, DQ2 =107, DQ3 =119
3553 22:58:51.789933 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =119
3554 22:58:51.793534 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3555 22:58:51.796748 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3556 22:58:51.797021
3557 22:58:51.797232
3558 22:58:51.797444 ==
3559 22:58:51.800055 Dram Type= 6, Freq= 0, CH_1, rank 1
3560 22:58:51.803791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3561 22:58:51.804357 ==
3562 22:58:51.804837
3563 22:58:51.805356
3564 22:58:51.806884 TX Vref Scan disable
3565 22:58:51.809949 == TX Byte 0 ==
3566 22:58:51.813904 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3567 22:58:51.816887 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3568 22:58:51.819854 == TX Byte 1 ==
3569 22:58:51.823521 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3570 22:58:51.826556 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3571 22:58:51.827101 ==
3572 22:58:51.830289 Dram Type= 6, Freq= 0, CH_1, rank 1
3573 22:58:51.837089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3574 22:58:51.837579 ==
3575 22:58:51.847387 TX Vref=22, minBit 9, minWin=25, winSum=419
3576 22:58:51.850507 TX Vref=24, minBit 2, minWin=26, winSum=428
3577 22:58:51.853618 TX Vref=26, minBit 4, minWin=26, winSum=430
3578 22:58:51.857002 TX Vref=28, minBit 9, minWin=26, winSum=435
3579 22:58:51.860189 TX Vref=30, minBit 9, minWin=26, winSum=435
3580 22:58:51.866963 TX Vref=32, minBit 9, minWin=26, winSum=436
3581 22:58:51.870624 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 32
3582 22:58:51.871073
3583 22:58:51.873549 Final TX Range 1 Vref 32
3584 22:58:51.873859
3585 22:58:51.874103 ==
3586 22:58:51.876943 Dram Type= 6, Freq= 0, CH_1, rank 1
3587 22:58:51.880223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3588 22:58:51.880536 ==
3589 22:58:51.883399
3590 22:58:51.883792
3591 22:58:51.884122 TX Vref Scan disable
3592 22:58:51.886777 == TX Byte 0 ==
3593 22:58:51.890042 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3594 22:58:51.897189 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3595 22:58:51.897590 == TX Byte 1 ==
3596 22:58:51.900035 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3597 22:58:51.906492 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3598 22:58:51.906806
3599 22:58:51.907049 [DATLAT]
3600 22:58:51.907276 Freq=1200, CH1 RK1
3601 22:58:51.907554
3602 22:58:51.909664 DATLAT Default: 0xd
3603 22:58:51.909973 0, 0xFFFF, sum = 0
3604 22:58:51.913418 1, 0xFFFF, sum = 0
3605 22:58:51.916607 2, 0xFFFF, sum = 0
3606 22:58:51.916990 3, 0xFFFF, sum = 0
3607 22:58:51.919894 4, 0xFFFF, sum = 0
3608 22:58:51.920257 5, 0xFFFF, sum = 0
3609 22:58:51.922856 6, 0xFFFF, sum = 0
3610 22:58:51.923449 7, 0xFFFF, sum = 0
3611 22:58:51.926625 8, 0xFFFF, sum = 0
3612 22:58:51.927088 9, 0xFFFF, sum = 0
3613 22:58:51.929659 10, 0xFFFF, sum = 0
3614 22:58:51.930115 11, 0xFFFF, sum = 0
3615 22:58:51.933285 12, 0x0, sum = 1
3616 22:58:51.933660 13, 0x0, sum = 2
3617 22:58:51.936590 14, 0x0, sum = 3
3618 22:58:51.936909 15, 0x0, sum = 4
3619 22:58:51.937159 best_step = 13
3620 22:58:51.939606
3621 22:58:51.939908 ==
3622 22:58:51.943253 Dram Type= 6, Freq= 0, CH_1, rank 1
3623 22:58:51.946281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3624 22:58:51.946611 ==
3625 22:58:51.946855 RX Vref Scan: 0
3626 22:58:51.947085
3627 22:58:51.949534 RX Vref 0 -> 0, step: 1
3628 22:58:51.949847
3629 22:58:51.952908 RX Delay -5 -> 252, step: 4
3630 22:58:51.956235 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3631 22:58:51.963266 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3632 22:58:51.966520 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3633 22:58:51.969792 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3634 22:58:51.973098 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3635 22:58:51.976272 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3636 22:58:51.983004 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3637 22:58:51.986332 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3638 22:58:51.989580 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3639 22:58:51.992841 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3640 22:58:51.996199 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3641 22:58:52.003080 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3642 22:58:52.006222 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3643 22:58:52.009374 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3644 22:58:52.012645 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3645 22:58:52.016446 iDelay=195, Bit 15, Center 126 (67 ~ 186) 120
3646 22:58:52.019480 ==
3647 22:58:52.019666 Dram Type= 6, Freq= 0, CH_1, rank 1
3648 22:58:52.026071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3649 22:58:52.026208 ==
3650 22:58:52.026279 DQS Delay:
3651 22:58:52.029687 DQS0 = 0, DQS1 = 0
3652 22:58:52.029806 DQM Delay:
3653 22:58:52.032660 DQM0 = 120, DQM1 = 117
3654 22:58:52.032745 DQ Delay:
3655 22:58:52.036363 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118
3656 22:58:52.039634 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3657 22:58:52.042688 DQ8 =106, DQ9 =106, DQ10 =116, DQ11 =110
3658 22:58:52.045990 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126
3659 22:58:52.046074
3660 22:58:52.046140
3661 22:58:52.056235 [DQSOSCAuto] RK1, (LSB)MR18= 0xfec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 404 ps
3662 22:58:52.056348 CH1 RK1: MR19=403, MR18=FEC
3663 22:58:52.062551 CH1_RK1: MR19=0x403, MR18=0xFEC, DQSOSC=404, MR23=63, INC=40, DEC=26
3664 22:58:52.066305 [RxdqsGatingPostProcess] freq 1200
3665 22:58:52.072851 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3666 22:58:52.076205 best DQS0 dly(2T, 0.5T) = (0, 11)
3667 22:58:52.079443 best DQS1 dly(2T, 0.5T) = (0, 11)
3668 22:58:52.082700 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3669 22:58:52.085708 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3670 22:58:52.089309 best DQS0 dly(2T, 0.5T) = (0, 11)
3671 22:58:52.092704 best DQS1 dly(2T, 0.5T) = (0, 11)
3672 22:58:52.095794 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3673 22:58:52.095951 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3674 22:58:52.098999 Pre-setting of DQS Precalculation
3675 22:58:52.105571 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3676 22:58:52.112726 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3677 22:58:52.119786 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3678 22:58:52.120218
3679 22:58:52.120553
3680 22:58:52.122736 [Calibration Summary] 2400 Mbps
3681 22:58:52.125885 CH 0, Rank 0
3682 22:58:52.126315 SW Impedance : PASS
3683 22:58:52.129227 DUTY Scan : NO K
3684 22:58:52.132917 ZQ Calibration : PASS
3685 22:58:52.133463 Jitter Meter : NO K
3686 22:58:52.136144 CBT Training : PASS
3687 22:58:52.136575 Write leveling : PASS
3688 22:58:52.138950 RX DQS gating : PASS
3689 22:58:52.142655 RX DQ/DQS(RDDQC) : PASS
3690 22:58:52.143086 TX DQ/DQS : PASS
3691 22:58:52.145687 RX DATLAT : PASS
3692 22:58:52.149431 RX DQ/DQS(Engine): PASS
3693 22:58:52.149861 TX OE : NO K
3694 22:58:52.152405 All Pass.
3695 22:58:52.152832
3696 22:58:52.153170 CH 0, Rank 1
3697 22:58:52.156005 SW Impedance : PASS
3698 22:58:52.156433 DUTY Scan : NO K
3699 22:58:52.159052 ZQ Calibration : PASS
3700 22:58:52.162335 Jitter Meter : NO K
3701 22:58:52.162758 CBT Training : PASS
3702 22:58:52.165416 Write leveling : PASS
3703 22:58:52.169159 RX DQS gating : PASS
3704 22:58:52.169389 RX DQ/DQS(RDDQC) : PASS
3705 22:58:52.172466 TX DQ/DQS : PASS
3706 22:58:52.175672 RX DATLAT : PASS
3707 22:58:52.175856 RX DQ/DQS(Engine): PASS
3708 22:58:52.178830 TX OE : NO K
3709 22:58:52.178986 All Pass.
3710 22:58:52.179109
3711 22:58:52.182067 CH 1, Rank 0
3712 22:58:52.182302 SW Impedance : PASS
3713 22:58:52.185397 DUTY Scan : NO K
3714 22:58:52.188682 ZQ Calibration : PASS
3715 22:58:52.188852 Jitter Meter : NO K
3716 22:58:52.191955 CBT Training : PASS
3717 22:58:52.195074 Write leveling : PASS
3718 22:58:52.195208 RX DQS gating : PASS
3719 22:58:52.198520 RX DQ/DQS(RDDQC) : PASS
3720 22:58:52.198652 TX DQ/DQS : PASS
3721 22:58:52.201522 RX DATLAT : PASS
3722 22:58:52.204927 RX DQ/DQS(Engine): PASS
3723 22:58:52.205060 TX OE : NO K
3724 22:58:52.208429 All Pass.
3725 22:58:52.208561
3726 22:58:52.208665 CH 1, Rank 1
3727 22:58:52.212294 SW Impedance : PASS
3728 22:58:52.212519 DUTY Scan : NO K
3729 22:58:52.215377 ZQ Calibration : PASS
3730 22:58:52.218546 Jitter Meter : NO K
3731 22:58:52.218754 CBT Training : PASS
3732 22:58:52.221630 Write leveling : PASS
3733 22:58:52.224774 RX DQS gating : PASS
3734 22:58:52.224968 RX DQ/DQS(RDDQC) : PASS
3735 22:58:52.228587 TX DQ/DQS : PASS
3736 22:58:52.231962 RX DATLAT : PASS
3737 22:58:52.232195 RX DQ/DQS(Engine): PASS
3738 22:58:52.235114 TX OE : NO K
3739 22:58:52.235424 All Pass.
3740 22:58:52.235652
3741 22:58:52.238388 DramC Write-DBI off
3742 22:58:52.241695 PER_BANK_REFRESH: Hybrid Mode
3743 22:58:52.242056 TX_TRACKING: ON
3744 22:58:52.251521 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3745 22:58:52.254957 [FAST_K] Save calibration result to emmc
3746 22:58:52.258465 dramc_set_vcore_voltage set vcore to 650000
3747 22:58:52.261370 Read voltage for 600, 5
3748 22:58:52.261794 Vio18 = 0
3749 22:58:52.262128 Vcore = 650000
3750 22:58:52.264678 Vdram = 0
3751 22:58:52.265115 Vddq = 0
3752 22:58:52.265481 Vmddr = 0
3753 22:58:52.271826 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3754 22:58:52.275010 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3755 22:58:52.277896 MEM_TYPE=3, freq_sel=19
3756 22:58:52.281911 sv_algorithm_assistance_LP4_1600
3757 22:58:52.285238 ============ PULL DRAM RESETB DOWN ============
3758 22:58:52.288134 ========== PULL DRAM RESETB DOWN end =========
3759 22:58:52.294762 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3760 22:58:52.297927 ===================================
3761 22:58:52.301454 LPDDR4 DRAM CONFIGURATION
3762 22:58:52.304889 ===================================
3763 22:58:52.305316 EX_ROW_EN[0] = 0x0
3764 22:58:52.308126 EX_ROW_EN[1] = 0x0
3765 22:58:52.308550 LP4Y_EN = 0x0
3766 22:58:52.311350 WORK_FSP = 0x0
3767 22:58:52.311780 WL = 0x2
3768 22:58:52.314577 RL = 0x2
3769 22:58:52.314999 BL = 0x2
3770 22:58:52.317698 RPST = 0x0
3771 22:58:52.318120 RD_PRE = 0x0
3772 22:58:52.321073 WR_PRE = 0x1
3773 22:58:52.321499 WR_PST = 0x0
3774 22:58:52.324316 DBI_WR = 0x0
3775 22:58:52.324741 DBI_RD = 0x0
3776 22:58:52.328323 OTF = 0x1
3777 22:58:52.331209 ===================================
3778 22:58:52.334259 ===================================
3779 22:58:52.334687 ANA top config
3780 22:58:52.338051 ===================================
3781 22:58:52.341370 DLL_ASYNC_EN = 0
3782 22:58:52.344578 ALL_SLAVE_EN = 1
3783 22:58:52.347809 NEW_RANK_MODE = 1
3784 22:58:52.348349 DLL_IDLE_MODE = 1
3785 22:58:52.351170 LP45_APHY_COMB_EN = 1
3786 22:58:52.354082 TX_ODT_DIS = 1
3787 22:58:52.357792 NEW_8X_MODE = 1
3788 22:58:52.361385 ===================================
3789 22:58:52.364158 ===================================
3790 22:58:52.367999 data_rate = 1200
3791 22:58:52.368597 CKR = 1
3792 22:58:52.370962 DQ_P2S_RATIO = 8
3793 22:58:52.374786 ===================================
3794 22:58:52.377752 CA_P2S_RATIO = 8
3795 22:58:52.380877 DQ_CA_OPEN = 0
3796 22:58:52.384840 DQ_SEMI_OPEN = 0
3797 22:58:52.387757 CA_SEMI_OPEN = 0
3798 22:58:52.388249 CA_FULL_RATE = 0
3799 22:58:52.390946 DQ_CKDIV4_EN = 1
3800 22:58:52.394113 CA_CKDIV4_EN = 1
3801 22:58:52.397336 CA_PREDIV_EN = 0
3802 22:58:52.400642 PH8_DLY = 0
3803 22:58:52.403919 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3804 22:58:52.404225 DQ_AAMCK_DIV = 4
3805 22:58:52.407560 CA_AAMCK_DIV = 4
3806 22:58:52.410701 CA_ADMCK_DIV = 4
3807 22:58:52.413887 DQ_TRACK_CA_EN = 0
3808 22:58:52.417305 CA_PICK = 600
3809 22:58:52.420887 CA_MCKIO = 600
3810 22:58:52.424159 MCKIO_SEMI = 0
3811 22:58:52.424306 PLL_FREQ = 2288
3812 22:58:52.427290 DQ_UI_PI_RATIO = 32
3813 22:58:52.430688 CA_UI_PI_RATIO = 0
3814 22:58:52.433766 ===================================
3815 22:58:52.437032 ===================================
3816 22:58:52.440775 memory_type:LPDDR4
3817 22:58:52.440945 GP_NUM : 10
3818 22:58:52.444237 SRAM_EN : 1
3819 22:58:52.447563 MD32_EN : 0
3820 22:58:52.450717 ===================================
3821 22:58:52.450922 [ANA_INIT] >>>>>>>>>>>>>>
3822 22:58:52.454131 <<<<<< [CONFIGURE PHASE]: ANA_TX
3823 22:58:52.457326 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3824 22:58:52.460525 ===================================
3825 22:58:52.463526 data_rate = 1200,PCW = 0X5800
3826 22:58:52.467160 ===================================
3827 22:58:52.470167 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3828 22:58:52.476954 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3829 22:58:52.479973 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3830 22:58:52.486753 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3831 22:58:52.490494 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3832 22:58:52.493300 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3833 22:58:52.497123 [ANA_INIT] flow start
3834 22:58:52.497238 [ANA_INIT] PLL >>>>>>>>
3835 22:58:52.500252 [ANA_INIT] PLL <<<<<<<<
3836 22:58:52.503511 [ANA_INIT] MIDPI >>>>>>>>
3837 22:58:52.503672 [ANA_INIT] MIDPI <<<<<<<<
3838 22:58:52.506757 [ANA_INIT] DLL >>>>>>>>
3839 22:58:52.510052 [ANA_INIT] flow end
3840 22:58:52.513163 ============ LP4 DIFF to SE enter ============
3841 22:58:52.517019 ============ LP4 DIFF to SE exit ============
3842 22:58:52.520358 [ANA_INIT] <<<<<<<<<<<<<
3843 22:58:52.523742 [Flow] Enable top DCM control >>>>>
3844 22:58:52.526812 [Flow] Enable top DCM control <<<<<
3845 22:58:52.530056 Enable DLL master slave shuffle
3846 22:58:52.533188 ==============================================================
3847 22:58:52.536677 Gating Mode config
3848 22:58:52.543737 ==============================================================
3849 22:58:52.544357 Config description:
3850 22:58:52.553568 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3851 22:58:52.560107 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3852 22:58:52.563306 SELPH_MODE 0: By rank 1: By Phase
3853 22:58:52.569848 ==============================================================
3854 22:58:52.573501 GAT_TRACK_EN = 1
3855 22:58:52.576568 RX_GATING_MODE = 2
3856 22:58:52.580123 RX_GATING_TRACK_MODE = 2
3857 22:58:52.583420 SELPH_MODE = 1
3858 22:58:52.586549 PICG_EARLY_EN = 1
3859 22:58:52.589506 VALID_LAT_VALUE = 1
3860 22:58:52.593099 ==============================================================
3861 22:58:52.595989 Enter into Gating configuration >>>>
3862 22:58:52.599443 Exit from Gating configuration <<<<
3863 22:58:52.603125 Enter into DVFS_PRE_config >>>>>
3864 22:58:52.616337 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3865 22:58:52.616526 Exit from DVFS_PRE_config <<<<<
3866 22:58:52.619379 Enter into PICG configuration >>>>
3867 22:58:52.622630 Exit from PICG configuration <<<<
3868 22:58:52.626418 [RX_INPUT] configuration >>>>>
3869 22:58:52.629523 [RX_INPUT] configuration <<<<<
3870 22:58:52.636201 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3871 22:58:52.639477 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3872 22:58:52.646000 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3873 22:58:52.652713 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3874 22:58:52.659713 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3875 22:58:52.666083 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3876 22:58:52.669402 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3877 22:58:52.672790 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3878 22:58:52.675971 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3879 22:58:52.682555 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3880 22:58:52.686198 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3881 22:58:52.689344 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3882 22:58:52.692914 ===================================
3883 22:58:52.695853 LPDDR4 DRAM CONFIGURATION
3884 22:58:52.699449 ===================================
3885 22:58:52.699670 EX_ROW_EN[0] = 0x0
3886 22:58:52.702434 EX_ROW_EN[1] = 0x0
3887 22:58:52.706205 LP4Y_EN = 0x0
3888 22:58:52.706355 WORK_FSP = 0x0
3889 22:58:52.709110 WL = 0x2
3890 22:58:52.709263 RL = 0x2
3891 22:58:52.712815 BL = 0x2
3892 22:58:52.712925 RPST = 0x0
3893 22:58:52.715847 RD_PRE = 0x0
3894 22:58:52.716018 WR_PRE = 0x1
3895 22:58:52.719008 WR_PST = 0x0
3896 22:58:52.719153 DBI_WR = 0x0
3897 22:58:52.722205 DBI_RD = 0x0
3898 22:58:52.722378 OTF = 0x1
3899 22:58:52.725571 ===================================
3900 22:58:52.729409 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3901 22:58:52.735718 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3902 22:58:52.739050 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3903 22:58:52.742363 ===================================
3904 22:58:52.745682 LPDDR4 DRAM CONFIGURATION
3905 22:58:52.748935 ===================================
3906 22:58:52.749059 EX_ROW_EN[0] = 0x10
3907 22:58:52.752218 EX_ROW_EN[1] = 0x0
3908 22:58:52.755429 LP4Y_EN = 0x0
3909 22:58:52.755518 WORK_FSP = 0x0
3910 22:58:52.758927 WL = 0x2
3911 22:58:52.759013 RL = 0x2
3912 22:58:52.761949 BL = 0x2
3913 22:58:52.762035 RPST = 0x0
3914 22:58:52.765159 RD_PRE = 0x0
3915 22:58:52.765231 WR_PRE = 0x1
3916 22:58:52.768985 WR_PST = 0x0
3917 22:58:52.769071 DBI_WR = 0x0
3918 22:58:52.772164 DBI_RD = 0x0
3919 22:58:52.772254 OTF = 0x1
3920 22:58:52.775495 ===================================
3921 22:58:52.782038 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3922 22:58:52.785940 nWR fixed to 30
3923 22:58:52.789124 [ModeRegInit_LP4] CH0 RK0
3924 22:58:52.789230 [ModeRegInit_LP4] CH0 RK1
3925 22:58:52.792980 [ModeRegInit_LP4] CH1 RK0
3926 22:58:52.795866 [ModeRegInit_LP4] CH1 RK1
3927 22:58:52.796041 match AC timing 17
3928 22:58:52.802735 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3929 22:58:52.805811 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3930 22:58:52.809508 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3931 22:58:52.816059 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3932 22:58:52.819832 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3933 22:58:52.819921 ==
3934 22:58:52.823053 Dram Type= 6, Freq= 0, CH_0, rank 0
3935 22:58:52.826308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3936 22:58:52.826393 ==
3937 22:58:52.832671 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3938 22:58:52.839383 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3939 22:58:52.842776 [CA 0] Center 35 (5~66) winsize 62
3940 22:58:52.846132 [CA 1] Center 35 (5~66) winsize 62
3941 22:58:52.849352 [CA 2] Center 33 (3~64) winsize 62
3942 22:58:52.852751 [CA 3] Center 33 (2~64) winsize 63
3943 22:58:52.855923 [CA 4] Center 33 (2~64) winsize 63
3944 22:58:52.859744 [CA 5] Center 32 (2~63) winsize 62
3945 22:58:52.859846
3946 22:58:52.862924 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3947 22:58:52.863042
3948 22:58:52.866076 [CATrainingPosCal] consider 1 rank data
3949 22:58:52.869146 u2DelayCellTimex100 = 270/100 ps
3950 22:58:52.872564 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3951 22:58:52.876441 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3952 22:58:52.879650 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3953 22:58:52.882760 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3954 22:58:52.886047 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3955 22:58:52.889278 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3956 22:58:52.889505
3957 22:58:52.895844 CA PerBit enable=1, Macro0, CA PI delay=32
3958 22:58:52.896169
3959 22:58:52.899073 [CBTSetCACLKResult] CA Dly = 32
3960 22:58:52.899359 CS Dly: 4 (0~35)
3961 22:58:52.899532 ==
3962 22:58:52.902906 Dram Type= 6, Freq= 0, CH_0, rank 1
3963 22:58:52.905860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3964 22:58:52.906074 ==
3965 22:58:52.912638 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3966 22:58:52.919415 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3967 22:58:52.922529 [CA 0] Center 35 (5~66) winsize 62
3968 22:58:52.926236 [CA 1] Center 35 (5~66) winsize 62
3969 22:58:52.929446 [CA 2] Center 34 (3~65) winsize 63
3970 22:58:52.932557 [CA 3] Center 33 (3~64) winsize 62
3971 22:58:52.935793 [CA 4] Center 32 (2~63) winsize 62
3972 22:58:52.939495 [CA 5] Center 32 (1~63) winsize 63
3973 22:58:52.939706
3974 22:58:52.942767 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3975 22:58:52.943028
3976 22:58:52.945695 [CATrainingPosCal] consider 2 rank data
3977 22:58:52.949097 u2DelayCellTimex100 = 270/100 ps
3978 22:58:52.952413 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3979 22:58:52.955803 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3980 22:58:52.958791 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3981 22:58:52.962645 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3982 22:58:52.965945 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3983 22:58:52.972479 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3984 22:58:52.972966
3985 22:58:52.975624 CA PerBit enable=1, Macro0, CA PI delay=32
3986 22:58:52.975904
3987 22:58:52.978922 [CBTSetCACLKResult] CA Dly = 32
3988 22:58:52.979130 CS Dly: 4 (0~36)
3989 22:58:52.979410
3990 22:58:52.982455 ----->DramcWriteLeveling(PI) begin...
3991 22:58:52.982674 ==
3992 22:58:52.985787 Dram Type= 6, Freq= 0, CH_0, rank 0
3993 22:58:52.989117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3994 22:58:52.992314 ==
3995 22:58:52.992541 Write leveling (Byte 0): 34 => 34
3996 22:58:52.995651 Write leveling (Byte 1): 32 => 32
3997 22:58:52.999230 DramcWriteLeveling(PI) end<-----
3998 22:58:52.999484
3999 22:58:52.999650 ==
4000 22:58:53.002336 Dram Type= 6, Freq= 0, CH_0, rank 0
4001 22:58:53.009275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4002 22:58:53.009491 ==
4003 22:58:53.012263 [Gating] SW mode calibration
4004 22:58:53.018907 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4005 22:58:53.022079 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4006 22:58:53.028998 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4007 22:58:53.032120 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4008 22:58:53.035177 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4009 22:58:53.042347 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
4010 22:58:53.045452 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
4011 22:58:53.049114 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4012 22:58:53.055546 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4013 22:58:53.058803 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4014 22:58:53.062026 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4015 22:58:53.065336 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4016 22:58:53.072432 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4017 22:58:53.075690 0 10 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
4018 22:58:53.079121 0 10 16 | B1->B0 | 3131 4646 | 1 0 | (0 0) (0 0)
4019 22:58:53.085577 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 22:58:53.088756 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 22:58:53.092553 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 22:58:53.098958 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 22:58:53.102121 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4024 22:58:53.105377 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 22:58:53.112077 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4026 22:58:53.115457 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 22:58:53.118957 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 22:58:53.125819 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 22:58:53.129478 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 22:58:53.132608 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 22:58:53.138958 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 22:58:53.142759 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 22:58:53.146065 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 22:58:53.149210 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 22:58:53.156032 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 22:58:53.159006 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 22:58:53.162357 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 22:58:53.168819 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 22:58:53.172506 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 22:58:53.175675 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 22:58:53.182091 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4042 22:58:53.185875 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4043 22:58:53.189291 Total UI for P1: 0, mck2ui 16
4044 22:58:53.192483 best dqsien dly found for B0: ( 0, 13, 12)
4045 22:58:53.195412 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 22:58:53.199070 Total UI for P1: 0, mck2ui 16
4047 22:58:53.202277 best dqsien dly found for B1: ( 0, 13, 14)
4048 22:58:53.205611 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4049 22:58:53.208522 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4050 22:58:53.211649
4051 22:58:53.214908 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4052 22:58:53.218754 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4053 22:58:53.221424 [Gating] SW calibration Done
4054 22:58:53.221507 ==
4055 22:58:53.225093 Dram Type= 6, Freq= 0, CH_0, rank 0
4056 22:58:53.228839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4057 22:58:53.228925 ==
4058 22:58:53.228990 RX Vref Scan: 0
4059 22:58:53.229050
4060 22:58:53.231859 RX Vref 0 -> 0, step: 1
4061 22:58:53.231941
4062 22:58:53.234868 RX Delay -230 -> 252, step: 16
4063 22:58:53.238526 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4064 22:58:53.241710 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4065 22:58:53.248426 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4066 22:58:53.251634 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4067 22:58:53.254941 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4068 22:58:53.258261 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4069 22:58:53.264962 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4070 22:58:53.268398 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4071 22:58:53.271843 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4072 22:58:53.274983 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4073 22:58:53.278623 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4074 22:58:53.285308 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4075 22:58:53.288449 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4076 22:58:53.291766 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4077 22:58:53.295089 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4078 22:58:53.301565 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4079 22:58:53.301647 ==
4080 22:58:53.305249 Dram Type= 6, Freq= 0, CH_0, rank 0
4081 22:58:53.308393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4082 22:58:53.308476 ==
4083 22:58:53.308541 DQS Delay:
4084 22:58:53.311550 DQS0 = 0, DQS1 = 0
4085 22:58:53.311632 DQM Delay:
4086 22:58:53.315519 DQM0 = 50, DQM1 = 45
4087 22:58:53.315601 DQ Delay:
4088 22:58:53.318828 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4089 22:58:53.322006 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4090 22:58:53.325144 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4091 22:58:53.328645 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4092 22:58:53.328727
4093 22:58:53.328791
4094 22:58:53.328850 ==
4095 22:58:53.331682 Dram Type= 6, Freq= 0, CH_0, rank 0
4096 22:58:53.335414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4097 22:58:53.335497 ==
4098 22:58:53.335561
4099 22:58:53.335620
4100 22:58:53.338532 TX Vref Scan disable
4101 22:58:53.342072 == TX Byte 0 ==
4102 22:58:53.345103 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4103 22:58:53.348908 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4104 22:58:53.352060 == TX Byte 1 ==
4105 22:58:53.355736 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4106 22:58:53.358414 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4107 22:58:53.358497 ==
4108 22:58:53.361628 Dram Type= 6, Freq= 0, CH_0, rank 0
4109 22:58:53.368692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4110 22:58:53.368858 ==
4111 22:58:53.368967
4112 22:58:53.369059
4113 22:58:53.369148 TX Vref Scan disable
4114 22:58:53.373004 == TX Byte 0 ==
4115 22:58:53.376238 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4116 22:58:53.382863 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4117 22:58:53.383294 == TX Byte 1 ==
4118 22:58:53.387198 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4119 22:58:53.393285 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4120 22:58:53.393796
4121 22:58:53.394135 [DATLAT]
4122 22:58:53.394447 Freq=600, CH0 RK0
4123 22:58:53.394748
4124 22:58:53.396897 DATLAT Default: 0x9
4125 22:58:53.397441 0, 0xFFFF, sum = 0
4126 22:58:53.399984 1, 0xFFFF, sum = 0
4127 22:58:53.400514 2, 0xFFFF, sum = 0
4128 22:58:53.403286 3, 0xFFFF, sum = 0
4129 22:58:53.403865 4, 0xFFFF, sum = 0
4130 22:58:53.406607 5, 0xFFFF, sum = 0
4131 22:58:53.409696 6, 0xFFFF, sum = 0
4132 22:58:53.410229 7, 0xFFFF, sum = 0
4133 22:58:53.410606 8, 0x0, sum = 1
4134 22:58:53.413727 9, 0x0, sum = 2
4135 22:58:53.414312 10, 0x0, sum = 3
4136 22:58:53.416600 11, 0x0, sum = 4
4137 22:58:53.417081 best_step = 9
4138 22:58:53.417457
4139 22:58:53.417807 ==
4140 22:58:53.419698 Dram Type= 6, Freq= 0, CH_0, rank 0
4141 22:58:53.426794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4142 22:58:53.427426 ==
4143 22:58:53.427816 RX Vref Scan: 1
4144 22:58:53.428167
4145 22:58:53.430746 RX Vref 0 -> 0, step: 1
4146 22:58:53.431475
4147 22:58:53.433071 RX Delay -163 -> 252, step: 8
4148 22:58:53.433545
4149 22:58:53.436558 Set Vref, RX VrefLevel [Byte0]: 56
4150 22:58:53.440193 [Byte1]: 57
4151 22:58:53.440777
4152 22:58:53.443013 Final RX Vref Byte 0 = 56 to rank0
4153 22:58:53.446728 Final RX Vref Byte 1 = 57 to rank0
4154 22:58:53.449638 Final RX Vref Byte 0 = 56 to rank1
4155 22:58:53.452989 Final RX Vref Byte 1 = 57 to rank1==
4156 22:58:53.457182 Dram Type= 6, Freq= 0, CH_0, rank 0
4157 22:58:53.459839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4158 22:58:53.460347 ==
4159 22:58:53.463110 DQS Delay:
4160 22:58:53.463635 DQS0 = 0, DQS1 = 0
4161 22:58:53.464015 DQM Delay:
4162 22:58:53.466157 DQM0 = 54, DQM1 = 47
4163 22:58:53.466633 DQ Delay:
4164 22:58:53.469380 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4165 22:58:53.473204 DQ4 =56, DQ5 =44, DQ6 =64, DQ7 =60
4166 22:58:53.476164 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4167 22:58:53.479424 DQ12 =52, DQ13 =52, DQ14 =60, DQ15 =52
4168 22:58:53.479861
4169 22:58:53.480207
4170 22:58:53.489839 [DQSOSCAuto] RK0, (LSB)MR18= 0x6d60, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4171 22:58:53.493104 CH0 RK0: MR19=808, MR18=6D60
4172 22:58:53.496311 CH0_RK0: MR19=0x808, MR18=0x6D60, DQSOSC=389, MR23=63, INC=173, DEC=115
4173 22:58:53.496755
4174 22:58:53.499464 ----->DramcWriteLeveling(PI) begin...
4175 22:58:53.502733 ==
4176 22:58:53.503040 Dram Type= 6, Freq= 0, CH_0, rank 1
4177 22:58:53.509247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4178 22:58:53.509453 ==
4179 22:58:53.512514 Write leveling (Byte 0): 33 => 33
4180 22:58:53.515758 Write leveling (Byte 1): 30 => 30
4181 22:58:53.519659 DramcWriteLeveling(PI) end<-----
4182 22:58:53.519830
4183 22:58:53.519943 ==
4184 22:58:53.522789 Dram Type= 6, Freq= 0, CH_0, rank 1
4185 22:58:53.525995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4186 22:58:53.526201 ==
4187 22:58:53.529496 [Gating] SW mode calibration
4188 22:58:53.536018 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4189 22:58:53.539386 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4190 22:58:53.546416 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4191 22:58:53.549364 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4192 22:58:53.552948 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4193 22:58:53.559034 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4194 22:58:53.562642 0 9 16 | B1->B0 | 2c2c 2727 | 0 0 | (1 1) (0 0)
4195 22:58:53.565778 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4196 22:58:53.572639 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4197 22:58:53.576076 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4198 22:58:53.579152 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4199 22:58:53.585503 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4200 22:58:53.589379 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4201 22:58:53.592794 0 10 12 | B1->B0 | 2626 2626 | 0 0 | (0 0) (0 0)
4202 22:58:53.599773 0 10 16 | B1->B0 | 3b3b 4242 | 0 0 | (0 0) (1 1)
4203 22:58:53.603287 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4204 22:58:53.606090 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 22:58:53.612915 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 22:58:53.616099 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4207 22:58:53.619456 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4208 22:58:53.626375 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4209 22:58:53.629196 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4210 22:58:53.632782 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 22:58:53.639409 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 22:58:53.642814 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 22:58:53.646197 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 22:58:53.652545 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 22:58:53.655640 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 22:58:53.659448 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 22:58:53.665462 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 22:58:53.669029 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 22:58:53.672595 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 22:58:53.675692 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 22:58:53.682310 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 22:58:53.685388 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 22:58:53.689291 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 22:58:53.695891 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 22:58:53.699117 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4226 22:58:53.702334 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4227 22:58:53.705683 Total UI for P1: 0, mck2ui 16
4228 22:58:53.708885 best dqsien dly found for B0: ( 0, 13, 12)
4229 22:58:53.715519 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 22:58:53.719076 Total UI for P1: 0, mck2ui 16
4231 22:58:53.722390 best dqsien dly found for B1: ( 0, 13, 14)
4232 22:58:53.725580 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4233 22:58:53.728830 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4234 22:58:53.729260
4235 22:58:53.732093 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4236 22:58:53.735247 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4237 22:58:53.738843 [Gating] SW calibration Done
4238 22:58:53.739388 ==
4239 22:58:53.742111 Dram Type= 6, Freq= 0, CH_0, rank 1
4240 22:58:53.745077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4241 22:58:53.745577 ==
4242 22:58:53.748599 RX Vref Scan: 0
4243 22:58:53.749085
4244 22:58:53.749742 RX Vref 0 -> 0, step: 1
4245 22:58:53.751762
4246 22:58:53.752342 RX Delay -230 -> 252, step: 16
4247 22:58:53.759091 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4248 22:58:53.762143 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4249 22:58:53.765399 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4250 22:58:53.768579 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4251 22:58:53.774844 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4252 22:58:53.778501 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4253 22:58:53.781580 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4254 22:58:53.784658 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4255 22:58:53.788468 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4256 22:58:53.794975 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4257 22:58:53.798287 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4258 22:58:53.801549 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4259 22:58:53.804825 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4260 22:58:53.811200 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4261 22:58:53.814865 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4262 22:58:53.817847 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4263 22:58:53.817948 ==
4264 22:58:53.821545 Dram Type= 6, Freq= 0, CH_0, rank 1
4265 22:58:53.824824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4266 22:58:53.824896 ==
4267 22:58:53.828022 DQS Delay:
4268 22:58:53.828102 DQS0 = 0, DQS1 = 0
4269 22:58:53.831274 DQM Delay:
4270 22:58:53.831408 DQM0 = 52, DQM1 = 47
4271 22:58:53.831472 DQ Delay:
4272 22:58:53.834706 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4273 22:58:53.837778 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4274 22:58:53.841288 DQ8 =41, DQ9 =41, DQ10 =49, DQ11 =49
4275 22:58:53.844811 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4276 22:58:53.844918
4277 22:58:53.845010
4278 22:58:53.847975 ==
4279 22:58:53.851410 Dram Type= 6, Freq= 0, CH_0, rank 1
4280 22:58:53.854676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4281 22:58:53.854781 ==
4282 22:58:53.854872
4283 22:58:53.854958
4284 22:58:53.857968 TX Vref Scan disable
4285 22:58:53.858036 == TX Byte 0 ==
4286 22:58:53.864857 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4287 22:58:53.867515 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4288 22:58:53.867622 == TX Byte 1 ==
4289 22:58:53.874598 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4290 22:58:53.877666 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4291 22:58:53.877741 ==
4292 22:58:53.881381 Dram Type= 6, Freq= 0, CH_0, rank 1
4293 22:58:53.884425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4294 22:58:53.884501 ==
4295 22:58:53.884604
4296 22:58:53.884679
4297 22:58:53.887954 TX Vref Scan disable
4298 22:58:53.891111 == TX Byte 0 ==
4299 22:58:53.894693 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4300 22:58:53.897885 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4301 22:58:53.901515 == TX Byte 1 ==
4302 22:58:53.904562 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4303 22:58:53.908433 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4304 22:58:53.908604
4305 22:58:53.911929 [DATLAT]
4306 22:58:53.912428 Freq=600, CH0 RK1
4307 22:58:53.912803
4308 22:58:53.914919 DATLAT Default: 0x9
4309 22:58:53.915385 0, 0xFFFF, sum = 0
4310 22:58:53.918131 1, 0xFFFF, sum = 0
4311 22:58:53.918603 2, 0xFFFF, sum = 0
4312 22:58:53.921342 3, 0xFFFF, sum = 0
4313 22:58:53.921851 4, 0xFFFF, sum = 0
4314 22:58:53.925263 5, 0xFFFF, sum = 0
4315 22:58:53.925787 6, 0xFFFF, sum = 0
4316 22:58:53.928059 7, 0xFFFF, sum = 0
4317 22:58:53.928486 8, 0x0, sum = 1
4318 22:58:53.931696 9, 0x0, sum = 2
4319 22:58:53.932182 10, 0x0, sum = 3
4320 22:58:53.934985 11, 0x0, sum = 4
4321 22:58:53.935630 best_step = 9
4322 22:58:53.936131
4323 22:58:53.936593 ==
4324 22:58:53.938081 Dram Type= 6, Freq= 0, CH_0, rank 1
4325 22:58:53.941408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4326 22:58:53.944680 ==
4327 22:58:53.945102 RX Vref Scan: 0
4328 22:58:53.945437
4329 22:58:53.947858 RX Vref 0 -> 0, step: 1
4330 22:58:53.948645
4331 22:58:53.950920 RX Delay -179 -> 252, step: 8
4332 22:58:53.954798 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4333 22:58:53.958143 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4334 22:58:53.964664 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4335 22:58:53.967789 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4336 22:58:53.971580 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4337 22:58:53.974964 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4338 22:58:53.978165 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4339 22:58:53.984548 iDelay=205, Bit 7, Center 60 (-83 ~ 204) 288
4340 22:58:53.987683 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4341 22:58:53.991539 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4342 22:58:53.994324 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4343 22:58:53.998092 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4344 22:58:54.004703 iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288
4345 22:58:54.007783 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4346 22:58:54.011776 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4347 22:58:54.014482 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4348 22:58:54.015004 ==
4349 22:58:54.018121 Dram Type= 6, Freq= 0, CH_0, rank 1
4350 22:58:54.024200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 22:58:54.024624 ==
4352 22:58:54.024953 DQS Delay:
4353 22:58:54.028153 DQS0 = 0, DQS1 = 0
4354 22:58:54.028677 DQM Delay:
4355 22:58:54.029009 DQM0 = 53, DQM1 = 46
4356 22:58:54.031506 DQ Delay:
4357 22:58:54.034656 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4358 22:58:54.037701 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =60
4359 22:58:54.041448 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =40
4360 22:58:54.044688 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4361 22:58:54.045222
4362 22:58:54.045556
4363 22:58:54.051222 [DQSOSCAuto] RK1, (LSB)MR18= 0x6020, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4364 22:58:54.054478 CH0 RK1: MR19=808, MR18=6020
4365 22:58:54.061220 CH0_RK1: MR19=0x808, MR18=0x6020, DQSOSC=391, MR23=63, INC=171, DEC=114
4366 22:58:54.064399 [RxdqsGatingPostProcess] freq 600
4367 22:58:54.067934 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4368 22:58:54.071041 Pre-setting of DQS Precalculation
4369 22:58:54.077530 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4370 22:58:54.078058 ==
4371 22:58:54.081352 Dram Type= 6, Freq= 0, CH_1, rank 0
4372 22:58:54.084634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4373 22:58:54.085076 ==
4374 22:58:54.091460 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4375 22:58:54.097853 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4376 22:58:54.100650 [CA 0] Center 35 (5~66) winsize 62
4377 22:58:54.103969 [CA 1] Center 35 (5~66) winsize 62
4378 22:58:54.107673 [CA 2] Center 34 (4~65) winsize 62
4379 22:58:54.111225 [CA 3] Center 34 (4~65) winsize 62
4380 22:58:54.111725 [CA 4] Center 34 (4~65) winsize 62
4381 22:58:54.114483 [CA 5] Center 34 (3~65) winsize 63
4382 22:58:54.115006
4383 22:58:54.120987 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4384 22:58:54.121408
4385 22:58:54.124528 [CATrainingPosCal] consider 1 rank data
4386 22:58:54.127707 u2DelayCellTimex100 = 270/100 ps
4387 22:58:54.131398 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4388 22:58:54.134144 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4389 22:58:54.138214 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4390 22:58:54.141351 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4391 22:58:54.144484 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4392 22:58:54.147383 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4393 22:58:54.147812
4394 22:58:54.150603 CA PerBit enable=1, Macro0, CA PI delay=34
4395 22:58:54.151046
4396 22:58:54.153917 [CBTSetCACLKResult] CA Dly = 34
4397 22:58:54.157164 CS Dly: 6 (0~37)
4398 22:58:54.157768 ==
4399 22:58:54.161282 Dram Type= 6, Freq= 0, CH_1, rank 1
4400 22:58:54.164275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4401 22:58:54.164735 ==
4402 22:58:54.171210 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4403 22:58:54.177831 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4404 22:58:54.180812 [CA 0] Center 36 (5~67) winsize 63
4405 22:58:54.184131 [CA 1] Center 36 (5~67) winsize 63
4406 22:58:54.187584 [CA 2] Center 34 (4~65) winsize 62
4407 22:58:54.190743 [CA 3] Center 34 (4~65) winsize 62
4408 22:58:54.194131 [CA 4] Center 35 (4~66) winsize 63
4409 22:58:54.197416 [CA 5] Center 34 (3~65) winsize 63
4410 22:58:54.197981
4411 22:58:54.201192 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4412 22:58:54.201756
4413 22:58:54.204545 [CATrainingPosCal] consider 2 rank data
4414 22:58:54.207443 u2DelayCellTimex100 = 270/100 ps
4415 22:58:54.211040 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4416 22:58:54.213744 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4417 22:58:54.217542 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4418 22:58:54.220702 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4419 22:58:54.223787 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4420 22:58:54.226939 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4421 22:58:54.227509
4422 22:58:54.230962 CA PerBit enable=1, Macro0, CA PI delay=34
4423 22:58:54.231590
4424 22:58:54.233704 [CBTSetCACLKResult] CA Dly = 34
4425 22:58:54.237158 CS Dly: 6 (0~38)
4426 22:58:54.237626
4427 22:58:54.240490 ----->DramcWriteLeveling(PI) begin...
4428 22:58:54.241072 ==
4429 22:58:54.243927 Dram Type= 6, Freq= 0, CH_1, rank 0
4430 22:58:54.246999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4431 22:58:54.247524 ==
4432 22:58:54.250577 Write leveling (Byte 0): 32 => 32
4433 22:58:54.253592 Write leveling (Byte 1): 32 => 32
4434 22:58:54.257249 DramcWriteLeveling(PI) end<-----
4435 22:58:54.257813
4436 22:58:54.258185 ==
4437 22:58:54.261246 Dram Type= 6, Freq= 0, CH_1, rank 0
4438 22:58:54.264097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4439 22:58:54.264527 ==
4440 22:58:54.267234 [Gating] SW mode calibration
4441 22:58:54.273839 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4442 22:58:54.280260 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4443 22:58:54.283965 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4444 22:58:54.286996 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4445 22:58:54.294494 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4446 22:58:54.297134 0 9 12 | B1->B0 | 3030 2e2e | 0 1 | (0 1) (1 1)
4447 22:58:54.301089 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4448 22:58:54.307523 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4449 22:58:54.310714 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4450 22:58:54.313949 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4451 22:58:54.320399 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4452 22:58:54.323703 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4453 22:58:54.327366 0 10 8 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
4454 22:58:54.333525 0 10 12 | B1->B0 | 3f3f 3f3f | 0 0 | (0 0) (0 0)
4455 22:58:54.336693 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 22:58:54.340288 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 22:58:54.347122 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 22:58:54.350233 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 22:58:54.353920 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4460 22:58:54.360234 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 22:58:54.363439 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4462 22:58:54.366820 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4463 22:58:54.373655 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 22:58:54.376970 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 22:58:54.380497 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 22:58:54.387064 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 22:58:54.390630 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 22:58:54.393773 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 22:58:54.400548 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 22:58:54.403761 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 22:58:54.407189 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 22:58:54.410227 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 22:58:54.417240 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 22:58:54.420213 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 22:58:54.423404 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 22:58:54.430401 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 22:58:54.433181 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4478 22:58:54.437097 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 22:58:54.440071 Total UI for P1: 0, mck2ui 16
4480 22:58:54.443793 best dqsien dly found for B0: ( 0, 13, 8)
4481 22:58:54.446943 Total UI for P1: 0, mck2ui 16
4482 22:58:54.450364 best dqsien dly found for B1: ( 0, 13, 8)
4483 22:58:54.453318 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4484 22:58:54.457227 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4485 22:58:54.457801
4486 22:58:54.462988 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4487 22:58:54.466933 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4488 22:58:54.470044 [Gating] SW calibration Done
4489 22:58:54.470527 ==
4490 22:58:54.473288 Dram Type= 6, Freq= 0, CH_1, rank 0
4491 22:58:54.476657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4492 22:58:54.477240 ==
4493 22:58:54.477619 RX Vref Scan: 0
4494 22:58:54.477968
4495 22:58:54.479855 RX Vref 0 -> 0, step: 1
4496 22:58:54.480328
4497 22:58:54.483097 RX Delay -230 -> 252, step: 16
4498 22:58:54.486044 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4499 22:58:54.490269 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4500 22:58:54.496554 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4501 22:58:54.499673 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4502 22:58:54.503221 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4503 22:58:54.506440 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4504 22:58:54.513004 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4505 22:58:54.516354 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4506 22:58:54.519643 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4507 22:58:54.523280 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4508 22:58:54.526470 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4509 22:58:54.532789 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4510 22:58:54.535952 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4511 22:58:54.539564 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4512 22:58:54.542683 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4513 22:58:54.549352 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4514 22:58:54.549796 ==
4515 22:58:54.552975 Dram Type= 6, Freq= 0, CH_1, rank 0
4516 22:58:54.555960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4517 22:58:54.556392 ==
4518 22:58:54.556750 DQS Delay:
4519 22:58:54.559205 DQS0 = 0, DQS1 = 0
4520 22:58:54.559679 DQM Delay:
4521 22:58:54.562697 DQM0 = 52, DQM1 = 50
4522 22:58:54.563120 DQ Delay:
4523 22:58:54.565733 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4524 22:58:54.568978 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4525 22:58:54.572716 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4526 22:58:54.575878 DQ12 =65, DQ13 =57, DQ14 =57, DQ15 =65
4527 22:58:54.576301
4528 22:58:54.576634
4529 22:58:54.576944 ==
4530 22:58:54.579189 Dram Type= 6, Freq= 0, CH_1, rank 0
4531 22:58:54.582355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4532 22:58:54.582811 ==
4533 22:58:54.583197
4534 22:58:54.583633
4535 22:58:54.585787 TX Vref Scan disable
4536 22:58:54.589082 == TX Byte 0 ==
4537 22:58:54.592845 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4538 22:58:54.595839 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4539 22:58:54.598877 == TX Byte 1 ==
4540 22:58:54.602687 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4541 22:58:54.605900 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4542 22:58:54.606320 ==
4543 22:58:54.608887 Dram Type= 6, Freq= 0, CH_1, rank 0
4544 22:58:54.615374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4545 22:58:54.615457 ==
4546 22:58:54.615526
4547 22:58:54.615586
4548 22:58:54.615643 TX Vref Scan disable
4549 22:58:54.619766 == TX Byte 0 ==
4550 22:58:54.623134 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4551 22:58:54.629491 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4552 22:58:54.629572 == TX Byte 1 ==
4553 22:58:54.632729 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4554 22:58:54.639935 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4555 22:58:54.640018
4556 22:58:54.640083 [DATLAT]
4557 22:58:54.640143 Freq=600, CH1 RK0
4558 22:58:54.640201
4559 22:58:54.643189 DATLAT Default: 0x9
4560 22:58:54.643270 0, 0xFFFF, sum = 0
4561 22:58:54.646102 1, 0xFFFF, sum = 0
4562 22:58:54.646185 2, 0xFFFF, sum = 0
4563 22:58:54.649611 3, 0xFFFF, sum = 0
4564 22:58:54.652918 4, 0xFFFF, sum = 0
4565 22:58:54.653001 5, 0xFFFF, sum = 0
4566 22:58:54.656574 6, 0xFFFF, sum = 0
4567 22:58:54.656658 7, 0xFFFF, sum = 0
4568 22:58:54.656724 8, 0x0, sum = 1
4569 22:58:54.659528 9, 0x0, sum = 2
4570 22:58:54.659616 10, 0x0, sum = 3
4571 22:58:54.662993 11, 0x0, sum = 4
4572 22:58:54.663076 best_step = 9
4573 22:58:54.663144
4574 22:58:54.663215 ==
4575 22:58:54.666548 Dram Type= 6, Freq= 0, CH_1, rank 0
4576 22:58:54.672771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4577 22:58:54.672854 ==
4578 22:58:54.672918 RX Vref Scan: 1
4579 22:58:54.672978
4580 22:58:54.676380 RX Vref 0 -> 0, step: 1
4581 22:58:54.676462
4582 22:58:54.679437 RX Delay -163 -> 252, step: 8
4583 22:58:54.679518
4584 22:58:54.683193 Set Vref, RX VrefLevel [Byte0]: 52
4585 22:58:54.686496 [Byte1]: 48
4586 22:58:54.686577
4587 22:58:54.689715 Final RX Vref Byte 0 = 52 to rank0
4588 22:58:54.692920 Final RX Vref Byte 1 = 48 to rank0
4589 22:58:54.696266 Final RX Vref Byte 0 = 52 to rank1
4590 22:58:54.699283 Final RX Vref Byte 1 = 48 to rank1==
4591 22:58:54.702634 Dram Type= 6, Freq= 0, CH_1, rank 0
4592 22:58:54.706314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4593 22:58:54.706396 ==
4594 22:58:54.709557 DQS Delay:
4595 22:58:54.709638 DQS0 = 0, DQS1 = 0
4596 22:58:54.709703 DQM Delay:
4597 22:58:54.712799 DQM0 = 48, DQM1 = 46
4598 22:58:54.712881 DQ Delay:
4599 22:58:54.715960 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4600 22:58:54.719246 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4601 22:58:54.722501 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4602 22:58:54.726491 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4603 22:58:54.726573
4604 22:58:54.726637
4605 22:58:54.735947 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c72, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4606 22:58:54.739159 CH1 RK0: MR19=808, MR18=4C72
4607 22:58:54.742500 CH1_RK0: MR19=0x808, MR18=0x4C72, DQSOSC=388, MR23=63, INC=174, DEC=116
4608 22:58:54.742585
4609 22:58:54.746320 ----->DramcWriteLeveling(PI) begin...
4610 22:58:54.749055 ==
4611 22:58:54.752319 Dram Type= 6, Freq= 0, CH_1, rank 1
4612 22:58:54.756027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4613 22:58:54.756111 ==
4614 22:58:54.759518 Write leveling (Byte 0): 30 => 30
4615 22:58:54.762538 Write leveling (Byte 1): 30 => 30
4616 22:58:54.765741 DramcWriteLeveling(PI) end<-----
4617 22:58:54.765827
4618 22:58:54.765891 ==
4619 22:58:54.769201 Dram Type= 6, Freq= 0, CH_1, rank 1
4620 22:58:54.772308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4621 22:58:54.772413 ==
4622 22:58:54.775904 [Gating] SW mode calibration
4623 22:58:54.782663 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4624 22:58:54.785780 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4625 22:58:54.792658 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4626 22:58:54.795855 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4627 22:58:54.799774 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4628 22:58:54.806602 0 9 12 | B1->B0 | 2e2e 2e2e | 0 1 | (1 0) (1 0)
4629 22:58:54.809579 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4630 22:58:54.812761 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4631 22:58:54.819266 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4632 22:58:54.822551 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4633 22:58:54.825708 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4634 22:58:54.832832 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4635 22:58:54.835930 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4636 22:58:54.839490 0 10 12 | B1->B0 | 3a3a 3838 | 0 0 | (0 0) (0 0)
4637 22:58:54.846114 0 10 16 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
4638 22:58:54.849281 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 22:58:54.852456 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 22:58:54.858898 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 22:58:54.862230 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4642 22:58:54.866046 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 22:58:54.872503 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 22:58:54.875521 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 22:58:54.879318 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 22:58:54.885546 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 22:58:54.889087 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 22:58:54.892524 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 22:58:54.899254 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 22:58:54.902433 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 22:58:54.905728 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 22:58:54.912175 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 22:58:54.915925 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 22:58:54.919021 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 22:58:54.925931 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 22:58:54.929036 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 22:58:54.932378 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 22:58:54.938796 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 22:58:54.941940 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4660 22:58:54.945803 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4661 22:58:54.949141 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4662 22:58:54.952389 Total UI for P1: 0, mck2ui 16
4663 22:58:54.955751 best dqsien dly found for B0: ( 0, 13, 12)
4664 22:58:54.958858 Total UI for P1: 0, mck2ui 16
4665 22:58:54.962156 best dqsien dly found for B1: ( 0, 13, 10)
4666 22:58:54.966016 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4667 22:58:54.972401 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4668 22:58:54.972829
4669 22:58:54.975746 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4670 22:58:54.978786 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4671 22:58:54.982409 [Gating] SW calibration Done
4672 22:58:54.982912 ==
4673 22:58:54.985423 Dram Type= 6, Freq= 0, CH_1, rank 1
4674 22:58:54.988940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4675 22:58:54.989392 ==
4676 22:58:54.989730 RX Vref Scan: 0
4677 22:58:54.992658
4678 22:58:54.993076 RX Vref 0 -> 0, step: 1
4679 22:58:54.993452
4680 22:58:54.995483 RX Delay -230 -> 252, step: 16
4681 22:58:54.999197 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4682 22:58:55.005371 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4683 22:58:55.008967 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4684 22:58:55.011975 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4685 22:58:55.015258 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4686 22:58:55.018472 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4687 22:58:55.025190 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4688 22:58:55.028876 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4689 22:58:55.032171 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4690 22:58:55.035414 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4691 22:58:55.042064 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4692 22:58:55.045203 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4693 22:58:55.048878 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4694 22:58:55.052141 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4695 22:58:55.058624 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4696 22:58:55.061924 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4697 22:58:55.062348 ==
4698 22:58:55.065235 Dram Type= 6, Freq= 0, CH_1, rank 1
4699 22:58:55.068487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4700 22:58:55.068912 ==
4701 22:58:55.069250 DQS Delay:
4702 22:58:55.071657 DQS0 = 0, DQS1 = 0
4703 22:58:55.072079 DQM Delay:
4704 22:58:55.074956 DQM0 = 50, DQM1 = 47
4705 22:58:55.075432 DQ Delay:
4706 22:58:55.078272 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4707 22:58:55.082047 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4708 22:58:55.085224 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4709 22:58:55.088527 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4710 22:58:55.089066
4711 22:58:55.089405
4712 22:58:55.089717 ==
4713 22:58:55.091881 Dram Type= 6, Freq= 0, CH_1, rank 1
4714 22:58:55.094908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4715 22:58:55.098378 ==
4716 22:58:55.098839
4717 22:58:55.099175
4718 22:58:55.099539 TX Vref Scan disable
4719 22:58:55.101955 == TX Byte 0 ==
4720 22:58:55.104921 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4721 22:58:55.108430 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4722 22:58:55.111481 == TX Byte 1 ==
4723 22:58:55.115210 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4724 22:58:55.118339 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4725 22:58:55.122107 ==
4726 22:58:55.125456 Dram Type= 6, Freq= 0, CH_1, rank 1
4727 22:58:55.128501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4728 22:58:55.129049 ==
4729 22:58:55.129565
4730 22:58:55.130022
4731 22:58:55.131560 TX Vref Scan disable
4732 22:58:55.132046 == TX Byte 0 ==
4733 22:58:55.138553 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4734 22:58:55.141825 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4735 22:58:55.142340 == TX Byte 1 ==
4736 22:58:55.148183 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4737 22:58:55.151286 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4738 22:58:55.151742
4739 22:58:55.152214 [DATLAT]
4740 22:58:55.154498 Freq=600, CH1 RK1
4741 22:58:55.154893
4742 22:58:55.155388 DATLAT Default: 0x9
4743 22:58:55.157850 0, 0xFFFF, sum = 0
4744 22:58:55.158241 1, 0xFFFF, sum = 0
4745 22:58:55.161160 2, 0xFFFF, sum = 0
4746 22:58:55.165063 3, 0xFFFF, sum = 0
4747 22:58:55.165515 4, 0xFFFF, sum = 0
4748 22:58:55.168345 5, 0xFFFF, sum = 0
4749 22:58:55.168892 6, 0xFFFF, sum = 0
4750 22:58:55.171057 7, 0xFFFF, sum = 0
4751 22:58:55.171662 8, 0x0, sum = 1
4752 22:58:55.174345 9, 0x0, sum = 2
4753 22:58:55.174857 10, 0x0, sum = 3
4754 22:58:55.175352 11, 0x0, sum = 4
4755 22:58:55.177866 best_step = 9
4756 22:58:55.178295
4757 22:58:55.178635 ==
4758 22:58:55.181365 Dram Type= 6, Freq= 0, CH_1, rank 1
4759 22:58:55.184460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4760 22:58:55.184904 ==
4761 22:58:55.188393 RX Vref Scan: 0
4762 22:58:55.188822
4763 22:58:55.189163 RX Vref 0 -> 0, step: 1
4764 22:58:55.191516
4765 22:58:55.191943 RX Delay -163 -> 252, step: 8
4766 22:58:55.198701 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4767 22:58:55.201664 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4768 22:58:55.205460 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4769 22:58:55.208392 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4770 22:58:55.211982 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4771 22:58:55.218636 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4772 22:58:55.221588 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4773 22:58:55.225377 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4774 22:58:55.228435 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4775 22:58:55.235211 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4776 22:58:55.238118 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4777 22:58:55.242028 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4778 22:58:55.244808 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4779 22:58:55.248663 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4780 22:58:55.255167 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4781 22:58:55.257976 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4782 22:58:55.258430 ==
4783 22:58:55.262233 Dram Type= 6, Freq= 0, CH_1, rank 1
4784 22:58:55.265076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4785 22:58:55.265515 ==
4786 22:58:55.268515 DQS Delay:
4787 22:58:55.268944 DQS0 = 0, DQS1 = 0
4788 22:58:55.269285 DQM Delay:
4789 22:58:55.271698 DQM0 = 48, DQM1 = 45
4790 22:58:55.272129 DQ Delay:
4791 22:58:55.274797 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4792 22:58:55.278036 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =44
4793 22:58:55.281395 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4794 22:58:55.284697 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =52
4795 22:58:55.285155
4796 22:58:55.285508
4797 22:58:55.294846 [DQSOSCAuto] RK1, (LSB)MR18= 0x6d25, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 389 ps
4798 22:58:55.298059 CH1 RK1: MR19=808, MR18=6D25
4799 22:58:55.301284 CH1_RK1: MR19=0x808, MR18=0x6D25, DQSOSC=389, MR23=63, INC=173, DEC=115
4800 22:58:55.304509 [RxdqsGatingPostProcess] freq 600
4801 22:58:55.311458 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4802 22:58:55.314843 Pre-setting of DQS Precalculation
4803 22:58:55.317988 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4804 22:58:55.328018 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4805 22:58:55.335123 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4806 22:58:55.335745
4807 22:58:55.336126
4808 22:58:55.337743 [Calibration Summary] 1200 Mbps
4809 22:58:55.338216 CH 0, Rank 0
4810 22:58:55.341122 SW Impedance : PASS
4811 22:58:55.341685 DUTY Scan : NO K
4812 22:58:55.344757 ZQ Calibration : PASS
4813 22:58:55.348244 Jitter Meter : NO K
4814 22:58:55.349146 CBT Training : PASS
4815 22:58:55.351043 Write leveling : PASS
4816 22:58:55.354342 RX DQS gating : PASS
4817 22:58:55.354823 RX DQ/DQS(RDDQC) : PASS
4818 22:58:55.358091 TX DQ/DQS : PASS
4819 22:58:55.361333 RX DATLAT : PASS
4820 22:58:55.361805 RX DQ/DQS(Engine): PASS
4821 22:58:55.364383 TX OE : NO K
4822 22:58:55.364855 All Pass.
4823 22:58:55.365225
4824 22:58:55.365566 CH 0, Rank 1
4825 22:58:55.368234 SW Impedance : PASS
4826 22:58:55.371509 DUTY Scan : NO K
4827 22:58:55.372011 ZQ Calibration : PASS
4828 22:58:55.374757 Jitter Meter : NO K
4829 22:58:55.378227 CBT Training : PASS
4830 22:58:55.378756 Write leveling : PASS
4831 22:58:55.381324 RX DQS gating : PASS
4832 22:58:55.384756 RX DQ/DQS(RDDQC) : PASS
4833 22:58:55.385285 TX DQ/DQS : PASS
4834 22:58:55.387791 RX DATLAT : PASS
4835 22:58:55.391212 RX DQ/DQS(Engine): PASS
4836 22:58:55.391763 TX OE : NO K
4837 22:58:55.394202 All Pass.
4838 22:58:55.394625
4839 22:58:55.394961 CH 1, Rank 0
4840 22:58:55.397719 SW Impedance : PASS
4841 22:58:55.398249 DUTY Scan : NO K
4842 22:58:55.401511 ZQ Calibration : PASS
4843 22:58:55.404631 Jitter Meter : NO K
4844 22:58:55.405058 CBT Training : PASS
4845 22:58:55.407869 Write leveling : PASS
4846 22:58:55.411444 RX DQS gating : PASS
4847 22:58:55.411983 RX DQ/DQS(RDDQC) : PASS
4848 22:58:55.414959 TX DQ/DQS : PASS
4849 22:58:55.415522 RX DATLAT : PASS
4850 22:58:55.418233 RX DQ/DQS(Engine): PASS
4851 22:58:55.420930 TX OE : NO K
4852 22:58:55.421361 All Pass.
4853 22:58:55.421705
4854 22:58:55.422021 CH 1, Rank 1
4855 22:58:55.423929 SW Impedance : PASS
4856 22:58:55.427194 DUTY Scan : NO K
4857 22:58:55.427686 ZQ Calibration : PASS
4858 22:58:55.430943 Jitter Meter : NO K
4859 22:58:55.434125 CBT Training : PASS
4860 22:58:55.434548 Write leveling : PASS
4861 22:58:55.437580 RX DQS gating : PASS
4862 22:58:55.440702 RX DQ/DQS(RDDQC) : PASS
4863 22:58:55.441155 TX DQ/DQS : PASS
4864 22:58:55.444116 RX DATLAT : PASS
4865 22:58:55.447828 RX DQ/DQS(Engine): PASS
4866 22:58:55.448390 TX OE : NO K
4867 22:58:55.450495 All Pass.
4868 22:58:55.450963
4869 22:58:55.451380 DramC Write-DBI off
4870 22:58:55.454182 PER_BANK_REFRESH: Hybrid Mode
4871 22:58:55.454669 TX_TRACKING: ON
4872 22:58:55.464073 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4873 22:58:55.467088 [FAST_K] Save calibration result to emmc
4874 22:58:55.470904 dramc_set_vcore_voltage set vcore to 662500
4875 22:58:55.474182 Read voltage for 933, 3
4876 22:58:55.474605 Vio18 = 0
4877 22:58:55.477433 Vcore = 662500
4878 22:58:55.477856 Vdram = 0
4879 22:58:55.478191 Vddq = 0
4880 22:58:55.478501 Vmddr = 0
4881 22:58:55.483873 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4882 22:58:55.490975 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4883 22:58:55.491655 MEM_TYPE=3, freq_sel=17
4884 22:58:55.494070 sv_algorithm_assistance_LP4_1600
4885 22:58:55.497323 ============ PULL DRAM RESETB DOWN ============
4886 22:58:55.503696 ========== PULL DRAM RESETB DOWN end =========
4887 22:58:55.507301 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4888 22:58:55.511222 ===================================
4889 22:58:55.514378 LPDDR4 DRAM CONFIGURATION
4890 22:58:55.517306 ===================================
4891 22:58:55.517781 EX_ROW_EN[0] = 0x0
4892 22:58:55.520527 EX_ROW_EN[1] = 0x0
4893 22:58:55.520997 LP4Y_EN = 0x0
4894 22:58:55.523781 WORK_FSP = 0x0
4895 22:58:55.527013 WL = 0x3
4896 22:58:55.527501 RL = 0x3
4897 22:58:55.530598 BL = 0x2
4898 22:58:55.531192 RPST = 0x0
4899 22:58:55.533600 RD_PRE = 0x0
4900 22:58:55.534067 WR_PRE = 0x1
4901 22:58:55.536861 WR_PST = 0x0
4902 22:58:55.537327 DBI_WR = 0x0
4903 22:58:55.540556 DBI_RD = 0x0
4904 22:58:55.541049 OTF = 0x1
4905 22:58:55.543437 ===================================
4906 22:58:55.547610 ===================================
4907 22:58:55.550670 ANA top config
4908 22:58:55.553800 ===================================
4909 22:58:55.554234 DLL_ASYNC_EN = 0
4910 22:58:55.557013 ALL_SLAVE_EN = 1
4911 22:58:55.559884 NEW_RANK_MODE = 1
4912 22:58:55.563435 DLL_IDLE_MODE = 1
4913 22:58:55.563962 LP45_APHY_COMB_EN = 1
4914 22:58:55.567098 TX_ODT_DIS = 1
4915 22:58:55.570249 NEW_8X_MODE = 1
4916 22:58:55.573711 ===================================
4917 22:58:55.576758 ===================================
4918 22:58:55.579952 data_rate = 1866
4919 22:58:55.583954 CKR = 1
4920 22:58:55.587279 DQ_P2S_RATIO = 8
4921 22:58:55.587760 ===================================
4922 22:58:55.590592 CA_P2S_RATIO = 8
4923 22:58:55.594002 DQ_CA_OPEN = 0
4924 22:58:55.597175 DQ_SEMI_OPEN = 0
4925 22:58:55.600151 CA_SEMI_OPEN = 0
4926 22:58:55.603536 CA_FULL_RATE = 0
4927 22:58:55.604065 DQ_CKDIV4_EN = 1
4928 22:58:55.606983 CA_CKDIV4_EN = 1
4929 22:58:55.610740 CA_PREDIV_EN = 0
4930 22:58:55.614069 PH8_DLY = 0
4931 22:58:55.617067 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4932 22:58:55.620334 DQ_AAMCK_DIV = 4
4933 22:58:55.620919 CA_AAMCK_DIV = 4
4934 22:58:55.623555 CA_ADMCK_DIV = 4
4935 22:58:55.626893 DQ_TRACK_CA_EN = 0
4936 22:58:55.630761 CA_PICK = 933
4937 22:58:55.633796 CA_MCKIO = 933
4938 22:58:55.637006 MCKIO_SEMI = 0
4939 22:58:55.640341 PLL_FREQ = 3732
4940 22:58:55.640918 DQ_UI_PI_RATIO = 32
4941 22:58:55.644209 CA_UI_PI_RATIO = 0
4942 22:58:55.647148 ===================================
4943 22:58:55.650256 ===================================
4944 22:58:55.653842 memory_type:LPDDR4
4945 22:58:55.656861 GP_NUM : 10
4946 22:58:55.657332 SRAM_EN : 1
4947 22:58:55.660108 MD32_EN : 0
4948 22:58:55.663431 ===================================
4949 22:58:55.663903 [ANA_INIT] >>>>>>>>>>>>>>
4950 22:58:55.667199 <<<<<< [CONFIGURE PHASE]: ANA_TX
4951 22:58:55.670534 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4952 22:58:55.673239 ===================================
4953 22:58:55.677001 data_rate = 1866,PCW = 0X8f00
4954 22:58:55.679863 ===================================
4955 22:58:55.683519 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4956 22:58:55.690564 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4957 22:58:55.697049 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4958 22:58:55.700330 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4959 22:58:55.703753 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4960 22:58:55.707060 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4961 22:58:55.710947 [ANA_INIT] flow start
4962 22:58:55.711556 [ANA_INIT] PLL >>>>>>>>
4963 22:58:55.714105 [ANA_INIT] PLL <<<<<<<<
4964 22:58:55.717173 [ANA_INIT] MIDPI >>>>>>>>
4965 22:58:55.717644 [ANA_INIT] MIDPI <<<<<<<<
4966 22:58:55.720792 [ANA_INIT] DLL >>>>>>>>
4967 22:58:55.723726 [ANA_INIT] flow end
4968 22:58:55.726968 ============ LP4 DIFF to SE enter ============
4969 22:58:55.730633 ============ LP4 DIFF to SE exit ============
4970 22:58:55.734026 [ANA_INIT] <<<<<<<<<<<<<
4971 22:58:55.737146 [Flow] Enable top DCM control >>>>>
4972 22:58:55.740341 [Flow] Enable top DCM control <<<<<
4973 22:58:55.743965 Enable DLL master slave shuffle
4974 22:58:55.746932 ==============================================================
4975 22:58:55.750359 Gating Mode config
4976 22:58:55.757034 ==============================================================
4977 22:58:55.757516 Config description:
4978 22:58:55.766892 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4979 22:58:55.773825 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4980 22:58:55.777445 SELPH_MODE 0: By rank 1: By Phase
4981 22:58:55.783483 ==============================================================
4982 22:58:55.787453 GAT_TRACK_EN = 1
4983 22:58:55.790236 RX_GATING_MODE = 2
4984 22:58:55.793483 RX_GATING_TRACK_MODE = 2
4985 22:58:55.797090 SELPH_MODE = 1
4986 22:58:55.800015 PICG_EARLY_EN = 1
4987 22:58:55.800503 VALID_LAT_VALUE = 1
4988 22:58:55.806816 ==============================================================
4989 22:58:55.810172 Enter into Gating configuration >>>>
4990 22:58:55.813350 Exit from Gating configuration <<<<
4991 22:58:55.816818 Enter into DVFS_PRE_config >>>>>
4992 22:58:55.826488 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4993 22:58:55.830111 Exit from DVFS_PRE_config <<<<<
4994 22:58:55.833335 Enter into PICG configuration >>>>
4995 22:58:55.836687 Exit from PICG configuration <<<<
4996 22:58:55.839865 [RX_INPUT] configuration >>>>>
4997 22:58:55.843548 [RX_INPUT] configuration <<<<<
4998 22:58:55.850430 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4999 22:58:55.853541 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5000 22:58:55.859802 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5001 22:58:55.866347 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5002 22:58:55.872836 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5003 22:58:55.879807 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5004 22:58:55.883153 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5005 22:58:55.886696 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5006 22:58:55.890308 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5007 22:58:55.896519 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5008 22:58:55.899811 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5009 22:58:55.903315 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5010 22:58:55.906267 ===================================
5011 22:58:55.909473 LPDDR4 DRAM CONFIGURATION
5012 22:58:55.912710 ===================================
5013 22:58:55.913141 EX_ROW_EN[0] = 0x0
5014 22:58:55.915907 EX_ROW_EN[1] = 0x0
5015 22:58:55.916509 LP4Y_EN = 0x0
5016 22:58:55.919755 WORK_FSP = 0x0
5017 22:58:55.922763 WL = 0x3
5018 22:58:55.923191 RL = 0x3
5019 22:58:55.926104 BL = 0x2
5020 22:58:55.926534 RPST = 0x0
5021 22:58:55.929374 RD_PRE = 0x0
5022 22:58:55.929803 WR_PRE = 0x1
5023 22:58:55.933269 WR_PST = 0x0
5024 22:58:55.933731 DBI_WR = 0x0
5025 22:58:55.936186 DBI_RD = 0x0
5026 22:58:55.936835 OTF = 0x1
5027 22:58:55.939296 ===================================
5028 22:58:55.942746 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5029 22:58:55.949644 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5030 22:58:55.952933 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5031 22:58:55.956140 ===================================
5032 22:58:55.959399 LPDDR4 DRAM CONFIGURATION
5033 22:58:55.963420 ===================================
5034 22:58:55.963858 EX_ROW_EN[0] = 0x10
5035 22:58:55.966374 EX_ROW_EN[1] = 0x0
5036 22:58:55.966804 LP4Y_EN = 0x0
5037 22:58:55.969360 WORK_FSP = 0x0
5038 22:58:55.969913 WL = 0x3
5039 22:58:55.973027 RL = 0x3
5040 22:58:55.973451 BL = 0x2
5041 22:58:55.976562 RPST = 0x0
5042 22:58:55.976987 RD_PRE = 0x0
5043 22:58:55.979619 WR_PRE = 0x1
5044 22:58:55.980045 WR_PST = 0x0
5045 22:58:55.983178 DBI_WR = 0x0
5046 22:58:55.983699 DBI_RD = 0x0
5047 22:58:55.986575 OTF = 0x1
5048 22:58:55.989879 ===================================
5049 22:58:55.996215 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5050 22:58:55.999826 nWR fixed to 30
5051 22:58:56.002842 [ModeRegInit_LP4] CH0 RK0
5052 22:58:56.003434 [ModeRegInit_LP4] CH0 RK1
5053 22:58:56.006720 [ModeRegInit_LP4] CH1 RK0
5054 22:58:56.010089 [ModeRegInit_LP4] CH1 RK1
5055 22:58:56.010611 match AC timing 9
5056 22:58:56.016250 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5057 22:58:56.019568 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5058 22:58:56.022857 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5059 22:58:56.030141 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5060 22:58:56.033446 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5061 22:58:56.033973 ==
5062 22:58:56.036400 Dram Type= 6, Freq= 0, CH_0, rank 0
5063 22:58:56.039505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5064 22:58:56.039961 ==
5065 22:58:56.046183 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5066 22:58:56.052390 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5067 22:58:56.055772 [CA 0] Center 37 (6~68) winsize 63
5068 22:58:56.059691 [CA 1] Center 37 (6~68) winsize 63
5069 22:58:56.062890 [CA 2] Center 34 (4~65) winsize 62
5070 22:58:56.066053 [CA 3] Center 34 (3~65) winsize 63
5071 22:58:56.069365 [CA 4] Center 33 (3~64) winsize 62
5072 22:58:56.072762 [CA 5] Center 32 (2~62) winsize 61
5073 22:58:56.073223
5074 22:58:56.075866 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5075 22:58:56.076311
5076 22:58:56.079425 [CATrainingPosCal] consider 1 rank data
5077 22:58:56.082893 u2DelayCellTimex100 = 270/100 ps
5078 22:58:56.085586 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5079 22:58:56.089368 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5080 22:58:56.092931 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5081 22:58:56.095925 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5082 22:58:56.099089 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5083 22:58:56.102218 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5084 22:58:56.105589
5085 22:58:56.109410 CA PerBit enable=1, Macro0, CA PI delay=32
5086 22:58:56.110013
5087 22:58:56.112500 [CBTSetCACLKResult] CA Dly = 32
5088 22:58:56.113080 CS Dly: 5 (0~36)
5089 22:58:56.113577 ==
5090 22:58:56.115710 Dram Type= 6, Freq= 0, CH_0, rank 1
5091 22:58:56.119419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5092 22:58:56.119996 ==
5093 22:58:56.125818 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5094 22:58:56.132202 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5095 22:58:56.135517 [CA 0] Center 37 (6~68) winsize 63
5096 22:58:56.138785 [CA 1] Center 37 (6~68) winsize 63
5097 22:58:56.142013 [CA 2] Center 34 (4~65) winsize 62
5098 22:58:56.145790 [CA 3] Center 33 (3~64) winsize 62
5099 22:58:56.149120 [CA 4] Center 33 (3~63) winsize 61
5100 22:58:56.152368 [CA 5] Center 32 (2~62) winsize 61
5101 22:58:56.152801
5102 22:58:56.155630 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5103 22:58:56.156265
5104 22:58:56.158693 [CATrainingPosCal] consider 2 rank data
5105 22:58:56.162622 u2DelayCellTimex100 = 270/100 ps
5106 22:58:56.165744 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5107 22:58:56.169089 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5108 22:58:56.172297 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5109 22:58:56.175662 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5110 22:58:56.178897 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5111 22:58:56.185712 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5112 22:58:56.186269
5113 22:58:56.188687 CA PerBit enable=1, Macro0, CA PI delay=32
5114 22:58:56.189193
5115 22:58:56.192292 [CBTSetCACLKResult] CA Dly = 32
5116 22:58:56.192721 CS Dly: 5 (0~37)
5117 22:58:56.193169
5118 22:58:56.196038 ----->DramcWriteLeveling(PI) begin...
5119 22:58:56.196459 ==
5120 22:58:56.198920 Dram Type= 6, Freq= 0, CH_0, rank 0
5121 22:58:56.205318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5122 22:58:56.205753 ==
5123 22:58:56.209139 Write leveling (Byte 0): 33 => 33
5124 22:58:56.209636 Write leveling (Byte 1): 31 => 31
5125 22:58:56.212208 DramcWriteLeveling(PI) end<-----
5126 22:58:56.212733
5127 22:58:56.213075 ==
5128 22:58:56.215712 Dram Type= 6, Freq= 0, CH_0, rank 0
5129 22:58:56.222065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5130 22:58:56.222509 ==
5131 22:58:56.225790 [Gating] SW mode calibration
5132 22:58:56.232064 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5133 22:58:56.235207 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5134 22:58:56.241732 0 14 0 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
5135 22:58:56.245127 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5136 22:58:56.248928 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5137 22:58:56.255100 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5138 22:58:56.258502 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5139 22:58:56.261654 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5140 22:58:56.268336 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
5141 22:58:56.272158 0 14 28 | B1->B0 | 3434 2525 | 0 0 | (0 0) (1 0)
5142 22:58:56.275440 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
5143 22:58:56.278760 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5144 22:58:56.285241 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5145 22:58:56.288508 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5146 22:58:56.292285 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5147 22:58:56.298659 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5148 22:58:56.302170 0 15 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5149 22:58:56.305271 0 15 28 | B1->B0 | 2525 403f | 0 1 | (0 0) (0 0)
5150 22:58:56.311867 1 0 0 | B1->B0 | 4040 4646 | 0 0 | (1 1) (0 0)
5151 22:58:56.314955 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 22:58:56.318673 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 22:58:56.325094 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 22:58:56.328448 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 22:58:56.332003 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5156 22:58:56.338425 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5157 22:58:56.341616 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5158 22:58:56.345007 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5159 22:58:56.351564 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5160 22:58:56.355164 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 22:58:56.358413 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 22:58:56.364582 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 22:58:56.368527 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 22:58:56.371077 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 22:58:56.378263 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 22:58:56.381566 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 22:58:56.384844 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 22:58:56.391411 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 22:58:56.394691 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 22:58:56.397666 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 22:58:56.405005 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 22:58:56.407863 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 22:58:56.411685 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5174 22:58:56.414539 Total UI for P1: 0, mck2ui 16
5175 22:58:56.417642 best dqsien dly found for B0: ( 1, 2, 26)
5176 22:58:56.424423 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 22:58:56.424853 Total UI for P1: 0, mck2ui 16
5178 22:58:56.428150 best dqsien dly found for B1: ( 1, 2, 28)
5179 22:58:56.434706 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5180 22:58:56.437938 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5181 22:58:56.438436
5182 22:58:56.441023 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5183 22:58:56.444125 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5184 22:58:56.448101 [Gating] SW calibration Done
5185 22:58:56.448532 ==
5186 22:58:56.451266 Dram Type= 6, Freq= 0, CH_0, rank 0
5187 22:58:56.454628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5188 22:58:56.455201 ==
5189 22:58:56.457955 RX Vref Scan: 0
5190 22:58:56.458379
5191 22:58:56.458713 RX Vref 0 -> 0, step: 1
5192 22:58:56.459023
5193 22:58:56.461048 RX Delay -80 -> 252, step: 8
5194 22:58:56.464283 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5195 22:58:56.470901 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5196 22:58:56.473973 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5197 22:58:56.477465 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5198 22:58:56.480633 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5199 22:58:56.483884 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5200 22:58:56.487292 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5201 22:58:56.494507 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5202 22:58:56.497903 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5203 22:58:56.500768 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5204 22:58:56.503979 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5205 22:58:56.507117 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5206 22:58:56.510939 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5207 22:58:56.517342 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5208 22:58:56.520935 iDelay=208, Bit 14, Center 107 (16 ~ 199) 184
5209 22:58:56.524047 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5210 22:58:56.524480 ==
5211 22:58:56.527936 Dram Type= 6, Freq= 0, CH_0, rank 0
5212 22:58:56.530642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5213 22:58:56.531070 ==
5214 22:58:56.534016 DQS Delay:
5215 22:58:56.534572 DQS0 = 0, DQS1 = 0
5216 22:58:56.537210 DQM Delay:
5217 22:58:56.537842 DQM0 = 104, DQM1 = 95
5218 22:58:56.538389 DQ Delay:
5219 22:58:56.540645 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5220 22:58:56.543783 DQ4 =103, DQ5 =95, DQ6 =111, DQ7 =115
5221 22:58:56.547365 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5222 22:58:56.550396 DQ12 =99, DQ13 =103, DQ14 =107, DQ15 =99
5223 22:58:56.553903
5224 22:58:56.554415
5225 22:58:56.554892 ==
5226 22:58:56.557095 Dram Type= 6, Freq= 0, CH_0, rank 0
5227 22:58:56.560530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5228 22:58:56.561056 ==
5229 22:58:56.561398
5230 22:58:56.561707
5231 22:58:56.563791 TX Vref Scan disable
5232 22:58:56.564345 == TX Byte 0 ==
5233 22:58:56.570950 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5234 22:58:56.574067 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5235 22:58:56.574745 == TX Byte 1 ==
5236 22:58:56.580402 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5237 22:58:56.583842 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5238 22:58:56.584271 ==
5239 22:58:56.586948 Dram Type= 6, Freq= 0, CH_0, rank 0
5240 22:58:56.590232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5241 22:58:56.590659 ==
5242 22:58:56.590994
5243 22:58:56.591305
5244 22:58:56.594272 TX Vref Scan disable
5245 22:58:56.596824 == TX Byte 0 ==
5246 22:58:56.600199 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5247 22:58:56.604078 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5248 22:58:56.607081 == TX Byte 1 ==
5249 22:58:56.610465 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5250 22:58:56.613855 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5251 22:58:56.614282
5252 22:58:56.616983 [DATLAT]
5253 22:58:56.617408 Freq=933, CH0 RK0
5254 22:58:56.617746
5255 22:58:56.620157 DATLAT Default: 0xd
5256 22:58:56.620631 0, 0xFFFF, sum = 0
5257 22:58:56.623766 1, 0xFFFF, sum = 0
5258 22:58:56.624298 2, 0xFFFF, sum = 0
5259 22:58:56.626729 3, 0xFFFF, sum = 0
5260 22:58:56.627144 4, 0xFFFF, sum = 0
5261 22:58:56.630754 5, 0xFFFF, sum = 0
5262 22:58:56.631187 6, 0xFFFF, sum = 0
5263 22:58:56.633449 7, 0xFFFF, sum = 0
5264 22:58:56.633881 8, 0xFFFF, sum = 0
5265 22:58:56.637170 9, 0xFFFF, sum = 0
5266 22:58:56.637602 10, 0x0, sum = 1
5267 22:58:56.640461 11, 0x0, sum = 2
5268 22:58:56.640977 12, 0x0, sum = 3
5269 22:58:56.643578 13, 0x0, sum = 4
5270 22:58:56.644009 best_step = 11
5271 22:58:56.644343
5272 22:58:56.644655 ==
5273 22:58:56.646639 Dram Type= 6, Freq= 0, CH_0, rank 0
5274 22:58:56.653545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5275 22:58:56.653973 ==
5276 22:58:56.654308 RX Vref Scan: 1
5277 22:58:56.654619
5278 22:58:56.656698 RX Vref 0 -> 0, step: 1
5279 22:58:56.657122
5280 22:58:56.660211 RX Delay -53 -> 252, step: 4
5281 22:58:56.660636
5282 22:58:56.663274 Set Vref, RX VrefLevel [Byte0]: 56
5283 22:58:56.667226 [Byte1]: 57
5284 22:58:56.667925
5285 22:58:56.670320 Final RX Vref Byte 0 = 56 to rank0
5286 22:58:56.673926 Final RX Vref Byte 1 = 57 to rank0
5287 22:58:56.676913 Final RX Vref Byte 0 = 56 to rank1
5288 22:58:56.680124 Final RX Vref Byte 1 = 57 to rank1==
5289 22:58:56.683388 Dram Type= 6, Freq= 0, CH_0, rank 0
5290 22:58:56.686419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5291 22:58:56.686850 ==
5292 22:58:56.690328 DQS Delay:
5293 22:58:56.690752 DQS0 = 0, DQS1 = 0
5294 22:58:56.691089 DQM Delay:
5295 22:58:56.693576 DQM0 = 105, DQM1 = 97
5296 22:58:56.694221 DQ Delay:
5297 22:58:56.696837 DQ0 =104, DQ1 =106, DQ2 =104, DQ3 =102
5298 22:58:56.700125 DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =110
5299 22:58:56.703391 DQ8 =88, DQ9 =90, DQ10 =98, DQ11 =92
5300 22:58:56.710029 DQ12 =100, DQ13 =100, DQ14 =106, DQ15 =104
5301 22:58:56.710455
5302 22:58:56.710805
5303 22:58:56.717034 [DQSOSCAuto] RK0, (LSB)MR18= 0x3229, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5304 22:58:56.720287 CH0 RK0: MR19=505, MR18=3229
5305 22:58:56.726714 CH0_RK0: MR19=0x505, MR18=0x3229, DQSOSC=406, MR23=63, INC=65, DEC=43
5306 22:58:56.727153
5307 22:58:56.730013 ----->DramcWriteLeveling(PI) begin...
5308 22:58:56.730442 ==
5309 22:58:56.733468 Dram Type= 6, Freq= 0, CH_0, rank 1
5310 22:58:56.736507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5311 22:58:56.736938 ==
5312 22:58:56.740118 Write leveling (Byte 0): 35 => 35
5313 22:58:56.743725 Write leveling (Byte 1): 27 => 27
5314 22:58:56.746770 DramcWriteLeveling(PI) end<-----
5315 22:58:56.747196
5316 22:58:56.747594 ==
5317 22:58:56.749855 Dram Type= 6, Freq= 0, CH_0, rank 1
5318 22:58:56.753685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5319 22:58:56.754114 ==
5320 22:58:56.756754 [Gating] SW mode calibration
5321 22:58:56.763705 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5322 22:58:56.769853 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5323 22:58:56.773501 0 14 0 | B1->B0 | 3333 3232 | 0 1 | (0 0) (0 0)
5324 22:58:56.776599 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5325 22:58:56.783108 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5326 22:58:56.786861 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5327 22:58:56.790161 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5328 22:58:56.796571 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5329 22:58:56.799886 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5330 22:58:56.803041 0 14 28 | B1->B0 | 2d2d 2e2e | 0 1 | (0 0) (1 0)
5331 22:58:56.809627 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
5332 22:58:56.813495 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5333 22:58:56.816458 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5334 22:58:56.823547 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5335 22:58:56.826153 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5336 22:58:56.829442 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5337 22:58:56.836151 0 15 24 | B1->B0 | 2727 2323 | 1 0 | (0 0) (0 0)
5338 22:58:56.839227 0 15 28 | B1->B0 | 3939 3f3f | 0 0 | (0 0) (0 0)
5339 22:58:56.842977 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5340 22:58:56.849457 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 22:58:56.852542 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 22:58:56.855795 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 22:58:56.862328 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5344 22:58:56.866139 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5345 22:58:56.869331 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 22:58:56.872635 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5347 22:58:56.879343 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5348 22:58:56.882419 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 22:58:56.886209 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 22:58:56.892486 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 22:58:56.895717 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 22:58:56.899573 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 22:58:56.905508 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 22:58:56.909332 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 22:58:56.912636 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 22:58:56.918999 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 22:58:56.922702 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 22:58:56.926031 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 22:58:56.932505 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 22:58:56.935818 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 22:58:56.939043 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 22:58:56.945569 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5363 22:58:56.949450 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 22:58:56.952418 Total UI for P1: 0, mck2ui 16
5365 22:58:56.955415 best dqsien dly found for B0: ( 1, 2, 28)
5366 22:58:56.959079 Total UI for P1: 0, mck2ui 16
5367 22:58:56.962234 best dqsien dly found for B1: ( 1, 2, 28)
5368 22:58:56.965434 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5369 22:58:56.968676 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5370 22:58:56.968799
5371 22:58:56.972357 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5372 22:58:56.975613 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5373 22:58:56.978880 [Gating] SW calibration Done
5374 22:58:56.979034 ==
5375 22:58:56.982229 Dram Type= 6, Freq= 0, CH_0, rank 1
5376 22:58:56.985391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5377 22:58:56.989044 ==
5378 22:58:56.989153 RX Vref Scan: 0
5379 22:58:56.989254
5380 22:58:56.991960 RX Vref 0 -> 0, step: 1
5381 22:58:56.992074
5382 22:58:56.995569 RX Delay -80 -> 252, step: 8
5383 22:58:56.998731 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5384 22:58:57.001926 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5385 22:58:57.005727 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5386 22:58:57.008952 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5387 22:58:57.012132 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5388 22:58:57.018836 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5389 22:58:57.022084 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5390 22:58:57.025139 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5391 22:58:57.028855 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5392 22:58:57.032156 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5393 22:58:57.035644 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5394 22:58:57.042142 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5395 22:58:57.045374 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5396 22:58:57.048805 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5397 22:58:57.052182 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5398 22:58:57.055282 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5399 22:58:57.055880 ==
5400 22:58:57.058986 Dram Type= 6, Freq= 0, CH_0, rank 1
5401 22:58:57.065486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5402 22:58:57.066091 ==
5403 22:58:57.066609 DQS Delay:
5404 22:58:57.069021 DQS0 = 0, DQS1 = 0
5405 22:58:57.069620 DQM Delay:
5406 22:58:57.072059 DQM0 = 105, DQM1 = 93
5407 22:58:57.072636 DQ Delay:
5408 22:58:57.075251 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =99
5409 22:58:57.078620 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5410 22:58:57.082292 DQ8 =87, DQ9 =79, DQ10 =95, DQ11 =87
5411 22:58:57.085735 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99
5412 22:58:57.086303
5413 22:58:57.086808
5414 22:58:57.087356 ==
5415 22:58:57.089015 Dram Type= 6, Freq= 0, CH_0, rank 1
5416 22:58:57.091990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5417 22:58:57.092550 ==
5418 22:58:57.093030
5419 22:58:57.093487
5420 22:58:57.095065 TX Vref Scan disable
5421 22:58:57.099046 == TX Byte 0 ==
5422 22:58:57.101895 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5423 22:58:57.105398 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5424 22:58:57.108553 == TX Byte 1 ==
5425 22:58:57.111966 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5426 22:58:57.115163 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5427 22:58:57.115728 ==
5428 22:58:57.118358 Dram Type= 6, Freq= 0, CH_0, rank 1
5429 22:58:57.124915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5430 22:58:57.125432 ==
5431 22:58:57.125924
5432 22:58:57.126373
5433 22:58:57.126812 TX Vref Scan disable
5434 22:58:57.129582 == TX Byte 0 ==
5435 22:58:57.132575 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5436 22:58:57.135869 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5437 22:58:57.139214 == TX Byte 1 ==
5438 22:58:57.142774 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5439 22:58:57.145850 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5440 22:58:57.149803
5441 22:58:57.150319 [DATLAT]
5442 22:58:57.150788 Freq=933, CH0 RK1
5443 22:58:57.151241
5444 22:58:57.152999 DATLAT Default: 0xb
5445 22:58:57.153420 0, 0xFFFF, sum = 0
5446 22:58:57.156275 1, 0xFFFF, sum = 0
5447 22:58:57.156703 2, 0xFFFF, sum = 0
5448 22:58:57.159696 3, 0xFFFF, sum = 0
5449 22:58:57.160131 4, 0xFFFF, sum = 0
5450 22:58:57.162796 5, 0xFFFF, sum = 0
5451 22:58:57.163514 6, 0xFFFF, sum = 0
5452 22:58:57.165947 7, 0xFFFF, sum = 0
5453 22:58:57.169631 8, 0xFFFF, sum = 0
5454 22:58:57.170065 9, 0xFFFF, sum = 0
5455 22:58:57.172567 10, 0x0, sum = 1
5456 22:58:57.173001 11, 0x0, sum = 2
5457 22:58:57.173378 12, 0x0, sum = 3
5458 22:58:57.176217 13, 0x0, sum = 4
5459 22:58:57.176648 best_step = 11
5460 22:58:57.177037
5461 22:58:57.179686 ==
5462 22:58:57.180115 Dram Type= 6, Freq= 0, CH_0, rank 1
5463 22:58:57.185864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5464 22:58:57.186295 ==
5465 22:58:57.186634 RX Vref Scan: 0
5466 22:58:57.186952
5467 22:58:57.189525 RX Vref 0 -> 0, step: 1
5468 22:58:57.189948
5469 22:58:57.192758 RX Delay -53 -> 252, step: 4
5470 22:58:57.196038 iDelay=199, Bit 0, Center 100 (11 ~ 190) 180
5471 22:58:57.202931 iDelay=199, Bit 1, Center 104 (19 ~ 190) 172
5472 22:58:57.206096 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5473 22:58:57.209200 iDelay=199, Bit 3, Center 100 (11 ~ 190) 180
5474 22:58:57.212702 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5475 22:58:57.215838 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5476 22:58:57.222357 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5477 22:58:57.225841 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5478 22:58:57.229108 iDelay=199, Bit 8, Center 88 (7 ~ 170) 164
5479 22:58:57.232469 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5480 22:58:57.235519 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5481 22:58:57.239154 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5482 22:58:57.245674 iDelay=199, Bit 12, Center 102 (19 ~ 186) 168
5483 22:58:57.248983 iDelay=199, Bit 13, Center 100 (15 ~ 186) 172
5484 22:58:57.252417 iDelay=199, Bit 14, Center 104 (23 ~ 186) 164
5485 22:58:57.255574 iDelay=199, Bit 15, Center 104 (23 ~ 186) 164
5486 22:58:57.255899 ==
5487 22:58:57.258808 Dram Type= 6, Freq= 0, CH_0, rank 1
5488 22:58:57.265265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5489 22:58:57.265575 ==
5490 22:58:57.265816 DQS Delay:
5491 22:58:57.268415 DQS0 = 0, DQS1 = 0
5492 22:58:57.268719 DQM Delay:
5493 22:58:57.272325 DQM0 = 103, DQM1 = 96
5494 22:58:57.272629 DQ Delay:
5495 22:58:57.275405 DQ0 =100, DQ1 =104, DQ2 =102, DQ3 =100
5496 22:58:57.278635 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112
5497 22:58:57.282010 DQ8 =88, DQ9 =86, DQ10 =98, DQ11 =88
5498 22:58:57.285232 DQ12 =102, DQ13 =100, DQ14 =104, DQ15 =104
5499 22:58:57.285629
5500 22:58:57.285889
5501 22:58:57.295410 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b04, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 408 ps
5502 22:58:57.295807 CH0 RK1: MR19=505, MR18=2B04
5503 22:58:57.301802 CH0_RK1: MR19=0x505, MR18=0x2B04, DQSOSC=408, MR23=63, INC=65, DEC=43
5504 22:58:57.305595 [RxdqsGatingPostProcess] freq 933
5505 22:58:57.312115 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5506 22:58:57.315302 best DQS0 dly(2T, 0.5T) = (0, 10)
5507 22:58:57.318451 best DQS1 dly(2T, 0.5T) = (0, 10)
5508 22:58:57.322012 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5509 22:58:57.324802 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5510 22:58:57.325360 best DQS0 dly(2T, 0.5T) = (0, 10)
5511 22:58:57.328714 best DQS1 dly(2T, 0.5T) = (0, 10)
5512 22:58:57.331678 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5513 22:58:57.334999 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5514 22:58:57.338388 Pre-setting of DQS Precalculation
5515 22:58:57.345185 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5516 22:58:57.345763 ==
5517 22:58:57.348500 Dram Type= 6, Freq= 0, CH_1, rank 0
5518 22:58:57.351858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5519 22:58:57.352512 ==
5520 22:58:57.358194 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5521 22:58:57.365079 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5522 22:58:57.368331 [CA 0] Center 36 (6~67) winsize 62
5523 22:58:57.371495 [CA 1] Center 36 (6~67) winsize 62
5524 22:58:57.374738 [CA 2] Center 34 (4~65) winsize 62
5525 22:58:57.377948 [CA 3] Center 34 (4~65) winsize 62
5526 22:58:57.381167 [CA 4] Center 34 (4~64) winsize 61
5527 22:58:57.381622 [CA 5] Center 33 (3~64) winsize 62
5528 22:58:57.385041
5529 22:58:57.388248 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5530 22:58:57.388686
5531 22:58:57.391244 [CATrainingPosCal] consider 1 rank data
5532 22:58:57.394717 u2DelayCellTimex100 = 270/100 ps
5533 22:58:57.397861 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5534 22:58:57.401643 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5535 22:58:57.404639 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5536 22:58:57.408227 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5537 22:58:57.411318 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5538 22:58:57.414449 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5539 22:58:57.414949
5540 22:58:57.417834 CA PerBit enable=1, Macro0, CA PI delay=33
5541 22:58:57.418324
5542 22:58:57.421137 [CBTSetCACLKResult] CA Dly = 33
5543 22:58:57.424730 CS Dly: 7 (0~38)
5544 22:58:57.425349 ==
5545 22:58:57.428084 Dram Type= 6, Freq= 0, CH_1, rank 1
5546 22:58:57.431131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5547 22:58:57.431790 ==
5548 22:58:57.437741 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5549 22:58:57.444686 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5550 22:58:57.447735 [CA 0] Center 36 (6~67) winsize 62
5551 22:58:57.451504 [CA 1] Center 37 (6~68) winsize 63
5552 22:58:57.454777 [CA 2] Center 34 (4~65) winsize 62
5553 22:58:57.457847 [CA 3] Center 34 (4~65) winsize 62
5554 22:58:57.461145 [CA 4] Center 34 (4~65) winsize 62
5555 22:58:57.464398 [CA 5] Center 34 (4~64) winsize 61
5556 22:58:57.464976
5557 22:58:57.467884 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5558 22:58:57.468327
5559 22:58:57.471042 [CATrainingPosCal] consider 2 rank data
5560 22:58:57.474345 u2DelayCellTimex100 = 270/100 ps
5561 22:58:57.477497 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5562 22:58:57.480875 CA1 delay=36 (6~67),Diff = 2 PI (12 cell)
5563 22:58:57.484720 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
5564 22:58:57.487948 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5565 22:58:57.491133 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5566 22:58:57.494546 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5567 22:58:57.495072
5568 22:58:57.497746 CA PerBit enable=1, Macro0, CA PI delay=34
5569 22:58:57.498181
5570 22:58:57.501079 [CBTSetCACLKResult] CA Dly = 34
5571 22:58:57.504529 CS Dly: 8 (0~40)
5572 22:58:57.504987
5573 22:58:57.507554 ----->DramcWriteLeveling(PI) begin...
5574 22:58:57.507956 ==
5575 22:58:57.511101 Dram Type= 6, Freq= 0, CH_1, rank 0
5576 22:58:57.514230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5577 22:58:57.514673 ==
5578 22:58:57.517839 Write leveling (Byte 0): 27 => 27
5579 22:58:57.521001 Write leveling (Byte 1): 27 => 27
5580 22:58:57.524390 DramcWriteLeveling(PI) end<-----
5581 22:58:57.524817
5582 22:58:57.525151 ==
5583 22:58:57.527491 Dram Type= 6, Freq= 0, CH_1, rank 0
5584 22:58:57.531242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5585 22:58:57.534405 ==
5586 22:58:57.534963 [Gating] SW mode calibration
5587 22:58:57.541134 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5588 22:58:57.547692 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5589 22:58:57.550855 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5590 22:58:57.557586 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5591 22:58:57.561238 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5592 22:58:57.564445 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5593 22:58:57.570991 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5594 22:58:57.574235 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5595 22:58:57.577658 0 14 24 | B1->B0 | 3131 2f2f | 1 0 | (1 0) (0 1)
5596 22:58:57.584207 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5597 22:58:57.587262 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5598 22:58:57.590665 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5599 22:58:57.597103 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5600 22:58:57.600504 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5601 22:58:57.604207 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 22:58:57.610620 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 22:58:57.613706 0 15 24 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
5604 22:58:57.617440 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5605 22:58:57.620561 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 22:58:57.627619 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 22:58:57.630268 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 22:58:57.633571 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 22:58:57.640870 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 22:58:57.644105 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 22:58:57.647111 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 22:58:57.653883 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5613 22:58:57.656824 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 22:58:57.660538 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 22:58:57.667080 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 22:58:57.670248 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 22:58:57.673601 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 22:58:57.680293 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 22:58:57.684077 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 22:58:57.687271 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 22:58:57.693659 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 22:58:57.696932 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 22:58:57.700117 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 22:58:57.706890 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 22:58:57.710454 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 22:58:57.713604 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 22:58:57.720080 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5628 22:58:57.723642 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5629 22:58:57.726603 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 22:58:57.730400 Total UI for P1: 0, mck2ui 16
5631 22:58:57.733288 best dqsien dly found for B0: ( 1, 2, 26)
5632 22:58:57.737070 Total UI for P1: 0, mck2ui 16
5633 22:58:57.739965 best dqsien dly found for B1: ( 1, 2, 26)
5634 22:58:57.743165 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5635 22:58:57.746989 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5636 22:58:57.747624
5637 22:58:57.750329 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5638 22:58:57.757036 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5639 22:58:57.757671 [Gating] SW calibration Done
5640 22:58:57.758264 ==
5641 22:58:57.759743 Dram Type= 6, Freq= 0, CH_1, rank 0
5642 22:58:57.766952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5643 22:58:57.767620 ==
5644 22:58:57.768224 RX Vref Scan: 0
5645 22:58:57.768667
5646 22:58:57.769765 RX Vref 0 -> 0, step: 1
5647 22:58:57.770273
5648 22:58:57.773447 RX Delay -80 -> 252, step: 8
5649 22:58:57.776610 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5650 22:58:57.780361 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5651 22:58:57.783540 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5652 22:58:57.786584 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5653 22:58:57.793108 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5654 22:58:57.796966 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5655 22:58:57.800344 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5656 22:58:57.803440 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5657 22:58:57.806694 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5658 22:58:57.810048 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5659 22:58:57.816387 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5660 22:58:57.820285 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5661 22:58:57.823575 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5662 22:58:57.826733 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5663 22:58:57.829930 iDelay=208, Bit 14, Center 107 (16 ~ 199) 184
5664 22:58:57.836494 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5665 22:58:57.837082 ==
5666 22:58:57.840221 Dram Type= 6, Freq= 0, CH_1, rank 0
5667 22:58:57.843386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5668 22:58:57.843997 ==
5669 22:58:57.844373 DQS Delay:
5670 22:58:57.846271 DQS0 = 0, DQS1 = 0
5671 22:58:57.846768 DQM Delay:
5672 22:58:57.850085 DQM0 = 102, DQM1 = 98
5673 22:58:57.850649 DQ Delay:
5674 22:58:57.853287 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5675 22:58:57.856309 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =103
5676 22:58:57.859706 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5677 22:58:57.863552 DQ12 =107, DQ13 =107, DQ14 =107, DQ15 =103
5678 22:58:57.864001
5679 22:58:57.864596
5680 22:58:57.865126 ==
5681 22:58:57.866707 Dram Type= 6, Freq= 0, CH_1, rank 0
5682 22:58:57.873044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5683 22:58:57.873632 ==
5684 22:58:57.874137
5685 22:58:57.874600
5686 22:58:57.875108 TX Vref Scan disable
5687 22:58:57.876539 == TX Byte 0 ==
5688 22:58:57.879805 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5689 22:58:57.886233 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5690 22:58:57.886663 == TX Byte 1 ==
5691 22:58:57.889952 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5692 22:58:57.896395 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5693 22:58:57.896834 ==
5694 22:58:57.899579 Dram Type= 6, Freq= 0, CH_1, rank 0
5695 22:58:57.903388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5696 22:58:57.903818 ==
5697 22:58:57.904160
5698 22:58:57.904474
5699 22:58:57.906680 TX Vref Scan disable
5700 22:58:57.907106 == TX Byte 0 ==
5701 22:58:57.913386 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5702 22:58:57.916636 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5703 22:58:57.917065 == TX Byte 1 ==
5704 22:58:57.922947 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5705 22:58:57.926374 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5706 22:58:57.926800
5707 22:58:57.927185 [DATLAT]
5708 22:58:57.929606 Freq=933, CH1 RK0
5709 22:58:57.930030
5710 22:58:57.930366 DATLAT Default: 0xd
5711 22:58:57.932815 0, 0xFFFF, sum = 0
5712 22:58:57.933244 1, 0xFFFF, sum = 0
5713 22:58:57.936082 2, 0xFFFF, sum = 0
5714 22:58:57.936660 3, 0xFFFF, sum = 0
5715 22:58:57.939581 4, 0xFFFF, sum = 0
5716 22:58:57.940102 5, 0xFFFF, sum = 0
5717 22:58:57.942816 6, 0xFFFF, sum = 0
5718 22:58:57.945851 7, 0xFFFF, sum = 0
5719 22:58:57.946414 8, 0xFFFF, sum = 0
5720 22:58:57.949572 9, 0xFFFF, sum = 0
5721 22:58:57.950108 10, 0x0, sum = 1
5722 22:58:57.950584 11, 0x0, sum = 2
5723 22:58:57.952792 12, 0x0, sum = 3
5724 22:58:57.953224 13, 0x0, sum = 4
5725 22:58:57.956058 best_step = 11
5726 22:58:57.956487
5727 22:58:57.956825 ==
5728 22:58:57.959884 Dram Type= 6, Freq= 0, CH_1, rank 0
5729 22:58:57.962915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5730 22:58:57.963381 ==
5731 22:58:57.966105 RX Vref Scan: 1
5732 22:58:57.966728
5733 22:58:57.967538 RX Vref 0 -> 0, step: 1
5734 22:58:57.969386
5735 22:58:57.969869 RX Delay -45 -> 252, step: 4
5736 22:58:57.970309
5737 22:58:57.972644 Set Vref, RX VrefLevel [Byte0]: 52
5738 22:58:57.975792 [Byte1]: 48
5739 22:58:57.980093
5740 22:58:57.980535 Final RX Vref Byte 0 = 52 to rank0
5741 22:58:57.983823 Final RX Vref Byte 1 = 48 to rank0
5742 22:58:57.986869 Final RX Vref Byte 0 = 52 to rank1
5743 22:58:57.990425 Final RX Vref Byte 1 = 48 to rank1==
5744 22:58:57.994034 Dram Type= 6, Freq= 0, CH_1, rank 0
5745 22:58:58.000319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5746 22:58:58.000855 ==
5747 22:58:58.001321 DQS Delay:
5748 22:58:58.001685 DQS0 = 0, DQS1 = 0
5749 22:58:58.003308 DQM Delay:
5750 22:58:58.003922 DQM0 = 103, DQM1 = 101
5751 22:58:58.006750 DQ Delay:
5752 22:58:58.009995 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =100
5753 22:58:58.013072 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5754 22:58:58.016365 DQ8 =90, DQ9 =90, DQ10 =100, DQ11 =96
5755 22:58:58.020434 DQ12 =108, DQ13 =106, DQ14 =108, DQ15 =110
5756 22:58:58.020888
5757 22:58:58.021220
5758 22:58:58.026637 [DQSOSCAuto] RK0, (LSB)MR18= 0x162e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5759 22:58:58.029781 CH1 RK0: MR19=505, MR18=162E
5760 22:58:58.036452 CH1_RK0: MR19=0x505, MR18=0x162E, DQSOSC=407, MR23=63, INC=65, DEC=43
5761 22:58:58.037202
5762 22:58:58.040445 ----->DramcWriteLeveling(PI) begin...
5763 22:58:58.041069 ==
5764 22:58:58.043313 Dram Type= 6, Freq= 0, CH_1, rank 1
5765 22:58:58.046758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5766 22:58:58.049971 ==
5767 22:58:58.050510 Write leveling (Byte 0): 27 => 27
5768 22:58:58.053355 Write leveling (Byte 1): 31 => 31
5769 22:58:58.057178 DramcWriteLeveling(PI) end<-----
5770 22:58:58.057834
5771 22:58:58.058398 ==
5772 22:58:58.060005 Dram Type= 6, Freq= 0, CH_1, rank 1
5773 22:58:58.066701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5774 22:58:58.067374 ==
5775 22:58:58.067956 [Gating] SW mode calibration
5776 22:58:58.076947 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5777 22:58:58.080252 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5778 22:58:58.083531 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5779 22:58:58.089850 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5780 22:58:58.092984 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5781 22:58:58.096042 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5782 22:58:58.102851 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5783 22:58:58.106462 0 14 20 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
5784 22:58:58.109426 0 14 24 | B1->B0 | 2f2f 3131 | 0 0 | (0 0) (0 0)
5785 22:58:58.115857 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5786 22:58:58.119615 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5787 22:58:58.122906 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5788 22:58:58.129305 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5789 22:58:58.132941 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5790 22:58:58.136206 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5791 22:58:58.143454 0 15 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5792 22:58:58.146314 0 15 24 | B1->B0 | 3535 2b2b | 0 1 | (0 0) (0 0)
5793 22:58:58.149516 0 15 28 | B1->B0 | 4646 3e3e | 0 0 | (0 0) (0 0)
5794 22:58:58.156630 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 22:58:58.160077 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5796 22:58:58.162972 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5797 22:58:58.169922 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 22:58:58.173172 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 22:58:58.176003 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5800 22:58:58.182777 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5801 22:58:58.186467 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 22:58:58.189738 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 22:58:58.196419 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 22:58:58.199622 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 22:58:58.202863 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 22:58:58.209494 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 22:58:58.213144 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 22:58:58.216132 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 22:58:58.219891 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 22:58:58.226444 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 22:58:58.229701 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 22:58:58.232921 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 22:58:58.239442 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 22:58:58.242643 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 22:58:58.246310 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 22:58:58.252533 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5817 22:58:58.256598 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5818 22:58:58.259080 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5819 22:58:58.262259 Total UI for P1: 0, mck2ui 16
5820 22:58:58.266030 best dqsien dly found for B0: ( 1, 2, 26)
5821 22:58:58.269151 Total UI for P1: 0, mck2ui 16
5822 22:58:58.272433 best dqsien dly found for B1: ( 1, 2, 26)
5823 22:58:58.275838 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5824 22:58:58.279184 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5825 22:58:58.279645
5826 22:58:58.285865 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5827 22:58:58.289636 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5828 22:58:58.290065 [Gating] SW calibration Done
5829 22:58:58.292972 ==
5830 22:58:58.296241 Dram Type= 6, Freq= 0, CH_1, rank 1
5831 22:58:58.299862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5832 22:58:58.300393 ==
5833 22:58:58.300737 RX Vref Scan: 0
5834 22:58:58.301055
5835 22:58:58.302828 RX Vref 0 -> 0, step: 1
5836 22:58:58.303251
5837 22:58:58.305864 RX Delay -80 -> 252, step: 8
5838 22:58:58.309649 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5839 22:58:58.312746 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5840 22:58:58.316439 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5841 22:58:58.322448 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5842 22:58:58.326187 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5843 22:58:58.329461 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5844 22:58:58.332764 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5845 22:58:58.336000 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5846 22:58:58.339124 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5847 22:58:58.343051 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5848 22:58:58.349541 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5849 22:58:58.352760 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5850 22:58:58.356003 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5851 22:58:58.359443 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5852 22:58:58.363296 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5853 22:58:58.369460 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5854 22:58:58.369933 ==
5855 22:58:58.372781 Dram Type= 6, Freq= 0, CH_1, rank 1
5856 22:58:58.375837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5857 22:58:58.376315 ==
5858 22:58:58.376688 DQS Delay:
5859 22:58:58.379102 DQS0 = 0, DQS1 = 0
5860 22:58:58.379615 DQM Delay:
5861 22:58:58.382487 DQM0 = 102, DQM1 = 97
5862 22:58:58.382914 DQ Delay:
5863 22:58:58.385909 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5864 22:58:58.389489 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5865 22:58:58.392805 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5866 22:58:58.395967 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =107
5867 22:58:58.396394
5868 22:58:58.396731
5869 22:58:58.397044 ==
5870 22:58:58.399782 Dram Type= 6, Freq= 0, CH_1, rank 1
5871 22:58:58.402635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5872 22:58:58.406075 ==
5873 22:58:58.406500
5874 22:58:58.406835
5875 22:58:58.407149 TX Vref Scan disable
5876 22:58:58.409252 == TX Byte 0 ==
5877 22:58:58.412649 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5878 22:58:58.416101 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5879 22:58:58.418802 == TX Byte 1 ==
5880 22:58:58.421906 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5881 22:58:58.425676 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5882 22:58:58.428514 ==
5883 22:58:58.432028 Dram Type= 6, Freq= 0, CH_1, rank 1
5884 22:58:58.435430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5885 22:58:58.435605 ==
5886 22:58:58.435689
5887 22:58:58.435766
5888 22:58:58.438749 TX Vref Scan disable
5889 22:58:58.438931 == TX Byte 0 ==
5890 22:58:58.445939 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5891 22:58:58.449261 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5892 22:58:58.449469 == TX Byte 1 ==
5893 22:58:58.455523 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5894 22:58:58.459038 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5895 22:58:58.459277
5896 22:58:58.459435 [DATLAT]
5897 22:58:58.461890 Freq=933, CH1 RK1
5898 22:58:58.462050
5899 22:58:58.462172 DATLAT Default: 0xb
5900 22:58:58.465552 0, 0xFFFF, sum = 0
5901 22:58:58.465817 1, 0xFFFF, sum = 0
5902 22:58:58.468443 2, 0xFFFF, sum = 0
5903 22:58:58.468656 3, 0xFFFF, sum = 0
5904 22:58:58.472167 4, 0xFFFF, sum = 0
5905 22:58:58.472394 5, 0xFFFF, sum = 0
5906 22:58:58.475500 6, 0xFFFF, sum = 0
5907 22:58:58.478904 7, 0xFFFF, sum = 0
5908 22:58:58.479370 8, 0xFFFF, sum = 0
5909 22:58:58.482098 9, 0xFFFF, sum = 0
5910 22:58:58.482553 10, 0x0, sum = 1
5911 22:58:58.482897 11, 0x0, sum = 2
5912 22:58:58.485530 12, 0x0, sum = 3
5913 22:58:58.486184 13, 0x0, sum = 4
5914 22:58:58.488562 best_step = 11
5915 22:58:58.489030
5916 22:58:58.489504 ==
5917 22:58:58.491904 Dram Type= 6, Freq= 0, CH_1, rank 1
5918 22:58:58.494979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5919 22:58:58.495489 ==
5920 22:58:58.498418 RX Vref Scan: 0
5921 22:58:58.498845
5922 22:58:58.499182 RX Vref 0 -> 0, step: 1
5923 22:58:58.501661
5924 22:58:58.502090 RX Delay -45 -> 252, step: 4
5925 22:58:58.509738 iDelay=199, Bit 0, Center 108 (27 ~ 190) 164
5926 22:58:58.513083 iDelay=199, Bit 1, Center 100 (19 ~ 182) 164
5927 22:58:58.516191 iDelay=199, Bit 2, Center 94 (11 ~ 178) 168
5928 22:58:58.519672 iDelay=199, Bit 3, Center 100 (19 ~ 182) 164
5929 22:58:58.522761 iDelay=199, Bit 4, Center 100 (19 ~ 182) 164
5930 22:58:58.529183 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5931 22:58:58.532964 iDelay=199, Bit 6, Center 114 (31 ~ 198) 168
5932 22:58:58.536082 iDelay=199, Bit 7, Center 102 (19 ~ 186) 168
5933 22:58:58.539233 iDelay=199, Bit 8, Center 88 (3 ~ 174) 172
5934 22:58:58.543111 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5935 22:58:58.546391 iDelay=199, Bit 10, Center 100 (15 ~ 186) 172
5936 22:58:58.552580 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5937 22:58:58.555830 iDelay=199, Bit 12, Center 110 (23 ~ 198) 176
5938 22:58:58.559927 iDelay=199, Bit 13, Center 106 (23 ~ 190) 168
5939 22:58:58.562776 iDelay=199, Bit 14, Center 104 (23 ~ 186) 164
5940 22:58:58.565969 iDelay=199, Bit 15, Center 108 (23 ~ 194) 172
5941 22:58:58.569060 ==
5942 22:58:58.573033 Dram Type= 6, Freq= 0, CH_1, rank 1
5943 22:58:58.576319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5944 22:58:58.576796 ==
5945 22:58:58.577176 DQS Delay:
5946 22:58:58.579523 DQS0 = 0, DQS1 = 0
5947 22:58:58.580020 DQM Delay:
5948 22:58:58.582703 DQM0 = 104, DQM1 = 99
5949 22:58:58.583636 DQ Delay:
5950 22:58:58.585573 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =100
5951 22:58:58.588999 DQ4 =100, DQ5 =116, DQ6 =114, DQ7 =102
5952 22:58:58.592837 DQ8 =88, DQ9 =88, DQ10 =100, DQ11 =92
5953 22:58:58.596028 DQ12 =110, DQ13 =106, DQ14 =104, DQ15 =108
5954 22:58:58.596472
5955 22:58:58.596911
5956 22:58:58.606211 [DQSOSCAuto] RK1, (LSB)MR18= 0x2cff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 408 ps
5957 22:58:58.606920 CH1 RK1: MR19=504, MR18=2CFF
5958 22:58:58.612574 CH1_RK1: MR19=0x504, MR18=0x2CFF, DQSOSC=408, MR23=63, INC=65, DEC=43
5959 22:58:58.616145 [RxdqsGatingPostProcess] freq 933
5960 22:58:58.622443 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5961 22:58:58.625824 best DQS0 dly(2T, 0.5T) = (0, 10)
5962 22:58:58.629710 best DQS1 dly(2T, 0.5T) = (0, 10)
5963 22:58:58.632963 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5964 22:58:58.635883 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5965 22:58:58.636313 best DQS0 dly(2T, 0.5T) = (0, 10)
5966 22:58:58.639495 best DQS1 dly(2T, 0.5T) = (0, 10)
5967 22:58:58.642596 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5968 22:58:58.645716 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5969 22:58:58.649345 Pre-setting of DQS Precalculation
5970 22:58:58.655622 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5971 22:58:58.662146 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5972 22:58:58.668621 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5973 22:58:58.668704
5974 22:58:58.668773
5975 22:58:58.672503 [Calibration Summary] 1866 Mbps
5976 22:58:58.672586 CH 0, Rank 0
5977 22:58:58.675659 SW Impedance : PASS
5978 22:58:58.678869 DUTY Scan : NO K
5979 22:58:58.678944 ZQ Calibration : PASS
5980 22:58:58.682001 Jitter Meter : NO K
5981 22:58:58.685376 CBT Training : PASS
5982 22:58:58.685459 Write leveling : PASS
5983 22:58:58.689080 RX DQS gating : PASS
5984 22:58:58.692291 RX DQ/DQS(RDDQC) : PASS
5985 22:58:58.692375 TX DQ/DQS : PASS
5986 22:58:58.695530 RX DATLAT : PASS
5987 22:58:58.698839 RX DQ/DQS(Engine): PASS
5988 22:58:58.698921 TX OE : NO K
5989 22:58:58.702061 All Pass.
5990 22:58:58.702143
5991 22:58:58.702208 CH 0, Rank 1
5992 22:58:58.705172 SW Impedance : PASS
5993 22:58:58.705254 DUTY Scan : NO K
5994 22:58:58.708997 ZQ Calibration : PASS
5995 22:58:58.709086 Jitter Meter : NO K
5996 22:58:58.712294 CBT Training : PASS
5997 22:58:58.715275 Write leveling : PASS
5998 22:58:58.715386 RX DQS gating : PASS
5999 22:58:58.718544 RX DQ/DQS(RDDQC) : PASS
6000 22:58:58.722350 TX DQ/DQS : PASS
6001 22:58:58.722453 RX DATLAT : PASS
6002 22:58:58.725538 RX DQ/DQS(Engine): PASS
6003 22:58:58.728599 TX OE : NO K
6004 22:58:58.728723 All Pass.
6005 22:58:58.728820
6006 22:58:58.728910 CH 1, Rank 0
6007 22:58:58.731832 SW Impedance : PASS
6008 22:58:58.735022 DUTY Scan : NO K
6009 22:58:58.735159 ZQ Calibration : PASS
6010 22:58:58.738279 Jitter Meter : NO K
6011 22:58:58.742080 CBT Training : PASS
6012 22:58:58.742234 Write leveling : PASS
6013 22:58:58.745289 RX DQS gating : PASS
6014 22:58:58.748928 RX DQ/DQS(RDDQC) : PASS
6015 22:58:58.749149 TX DQ/DQS : PASS
6016 22:58:58.752102 RX DATLAT : PASS
6017 22:58:58.755413 RX DQ/DQS(Engine): PASS
6018 22:58:58.755655 TX OE : NO K
6019 22:58:58.755850 All Pass.
6020 22:58:58.758495
6021 22:58:58.758832 CH 1, Rank 1
6022 22:58:58.762190 SW Impedance : PASS
6023 22:58:58.762488 DUTY Scan : NO K
6024 22:58:58.765804 ZQ Calibration : PASS
6025 22:58:58.766473 Jitter Meter : NO K
6026 22:58:58.768544 CBT Training : PASS
6027 22:58:58.772338 Write leveling : PASS
6028 22:58:58.772828 RX DQS gating : PASS
6029 22:58:58.775639 RX DQ/DQS(RDDQC) : PASS
6030 22:58:58.778774 TX DQ/DQS : PASS
6031 22:58:58.779266 RX DATLAT : PASS
6032 22:58:58.782058 RX DQ/DQS(Engine): PASS
6033 22:58:58.785329 TX OE : NO K
6034 22:58:58.785816 All Pass.
6035 22:58:58.786308
6036 22:58:58.788445 DramC Write-DBI off
6037 22:58:58.789116 PER_BANK_REFRESH: Hybrid Mode
6038 22:58:58.791812 TX_TRACKING: ON
6039 22:58:58.798728 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6040 22:58:58.805272 [FAST_K] Save calibration result to emmc
6041 22:58:58.808642 dramc_set_vcore_voltage set vcore to 650000
6042 22:58:58.809125 Read voltage for 400, 6
6043 22:58:58.811846 Vio18 = 0
6044 22:58:58.812276 Vcore = 650000
6045 22:58:58.812619 Vdram = 0
6046 22:58:58.815246 Vddq = 0
6047 22:58:58.815822 Vmddr = 0
6048 22:58:58.818678 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6049 22:58:58.824997 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6050 22:58:58.828747 MEM_TYPE=3, freq_sel=20
6051 22:58:58.831441 sv_algorithm_assistance_LP4_800
6052 22:58:58.835392 ============ PULL DRAM RESETB DOWN ============
6053 22:58:58.838619 ========== PULL DRAM RESETB DOWN end =========
6054 22:58:58.844988 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6055 22:58:58.848363 ===================================
6056 22:58:58.848893 LPDDR4 DRAM CONFIGURATION
6057 22:58:58.851510 ===================================
6058 22:58:58.855505 EX_ROW_EN[0] = 0x0
6059 22:58:58.856048 EX_ROW_EN[1] = 0x0
6060 22:58:58.858710 LP4Y_EN = 0x0
6061 22:58:58.859466 WORK_FSP = 0x0
6062 22:58:58.861808 WL = 0x2
6063 22:58:58.864682 RL = 0x2
6064 22:58:58.865238 BL = 0x2
6065 22:58:58.868281 RPST = 0x0
6066 22:58:58.868709 RD_PRE = 0x0
6067 22:58:58.871190 WR_PRE = 0x1
6068 22:58:58.871656 WR_PST = 0x0
6069 22:58:58.874799 DBI_WR = 0x0
6070 22:58:58.875228 DBI_RD = 0x0
6071 22:58:58.878019 OTF = 0x1
6072 22:58:58.881943 ===================================
6073 22:58:58.884626 ===================================
6074 22:58:58.885057 ANA top config
6075 22:58:58.887866 ===================================
6076 22:58:58.891704 DLL_ASYNC_EN = 0
6077 22:58:58.895370 ALL_SLAVE_EN = 1
6078 22:58:58.895938 NEW_RANK_MODE = 1
6079 22:58:58.898614 DLL_IDLE_MODE = 1
6080 22:58:58.901697 LP45_APHY_COMB_EN = 1
6081 22:58:58.904829 TX_ODT_DIS = 1
6082 22:58:58.905266 NEW_8X_MODE = 1
6083 22:58:58.908847 ===================================
6084 22:58:58.912239 ===================================
6085 22:58:58.915527 data_rate = 800
6086 22:58:58.918594 CKR = 1
6087 22:58:58.921761 DQ_P2S_RATIO = 4
6088 22:58:58.925000 ===================================
6089 22:58:58.928331 CA_P2S_RATIO = 4
6090 22:58:58.931512 DQ_CA_OPEN = 0
6091 22:58:58.932024 DQ_SEMI_OPEN = 1
6092 22:58:58.935270 CA_SEMI_OPEN = 1
6093 22:58:58.938417 CA_FULL_RATE = 0
6094 22:58:58.941307 DQ_CKDIV4_EN = 0
6095 22:58:58.944360 CA_CKDIV4_EN = 1
6096 22:58:58.947724 CA_PREDIV_EN = 0
6097 22:58:58.947809 PH8_DLY = 0
6098 22:58:58.951010 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6099 22:58:58.954414 DQ_AAMCK_DIV = 0
6100 22:58:58.957820 CA_AAMCK_DIV = 0
6101 22:58:58.961157 CA_ADMCK_DIV = 4
6102 22:58:58.964172 DQ_TRACK_CA_EN = 0
6103 22:58:58.967816 CA_PICK = 800
6104 22:58:58.967981 CA_MCKIO = 400
6105 22:58:58.970844 MCKIO_SEMI = 400
6106 22:58:58.973941 PLL_FREQ = 3016
6107 22:58:58.977447 DQ_UI_PI_RATIO = 32
6108 22:58:58.980549 CA_UI_PI_RATIO = 32
6109 22:58:58.984185 ===================================
6110 22:58:58.987301 ===================================
6111 22:58:58.991089 memory_type:LPDDR4
6112 22:58:58.991301 GP_NUM : 10
6113 22:58:58.994713 SRAM_EN : 1
6114 22:58:58.995051 MD32_EN : 0
6115 22:58:58.997295 ===================================
6116 22:58:59.001419 [ANA_INIT] >>>>>>>>>>>>>>
6117 22:58:59.004560 <<<<<< [CONFIGURE PHASE]: ANA_TX
6118 22:58:59.007780 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6119 22:58:59.010755 ===================================
6120 22:58:59.014065 data_rate = 800,PCW = 0X7400
6121 22:58:59.017726 ===================================
6122 22:58:59.021207 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6123 22:58:59.027898 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6124 22:58:59.037958 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6125 22:58:59.041331 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6126 22:58:59.044548 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6127 22:58:59.047582 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6128 22:58:59.051249 [ANA_INIT] flow start
6129 22:58:59.054318 [ANA_INIT] PLL >>>>>>>>
6130 22:58:59.054792 [ANA_INIT] PLL <<<<<<<<
6131 22:58:59.057470 [ANA_INIT] MIDPI >>>>>>>>
6132 22:58:59.060860 [ANA_INIT] MIDPI <<<<<<<<
6133 22:58:59.064075 [ANA_INIT] DLL >>>>>>>>
6134 22:58:59.064587 [ANA_INIT] flow end
6135 22:58:59.067798 ============ LP4 DIFF to SE enter ============
6136 22:58:59.074347 ============ LP4 DIFF to SE exit ============
6137 22:58:59.074906 [ANA_INIT] <<<<<<<<<<<<<
6138 22:58:59.077198 [Flow] Enable top DCM control >>>>>
6139 22:58:59.080796 [Flow] Enable top DCM control <<<<<
6140 22:58:59.084175 Enable DLL master slave shuffle
6141 22:58:59.090920 ==============================================================
6142 22:58:59.091477 Gating Mode config
6143 22:58:59.097412 ==============================================================
6144 22:58:59.100560 Config description:
6145 22:58:59.107796 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6146 22:58:59.114210 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6147 22:58:59.120943 SELPH_MODE 0: By rank 1: By Phase
6148 22:58:59.127237 ==============================================================
6149 22:58:59.130948 GAT_TRACK_EN = 0
6150 22:58:59.131556 RX_GATING_MODE = 2
6151 22:58:59.133948 RX_GATING_TRACK_MODE = 2
6152 22:58:59.137233 SELPH_MODE = 1
6153 22:58:59.140479 PICG_EARLY_EN = 1
6154 22:58:59.144063 VALID_LAT_VALUE = 1
6155 22:58:59.150402 ==============================================================
6156 22:58:59.153994 Enter into Gating configuration >>>>
6157 22:58:59.156864 Exit from Gating configuration <<<<
6158 22:58:59.160541 Enter into DVFS_PRE_config >>>>>
6159 22:58:59.170190 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6160 22:58:59.173664 Exit from DVFS_PRE_config <<<<<
6161 22:58:59.176953 Enter into PICG configuration >>>>
6162 22:58:59.180156 Exit from PICG configuration <<<<
6163 22:58:59.184009 [RX_INPUT] configuration >>>>>
6164 22:58:59.186939 [RX_INPUT] configuration <<<<<
6165 22:58:59.190537 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6166 22:58:59.196585 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6167 22:58:59.203073 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6168 22:58:59.206724 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6169 22:58:59.213545 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6170 22:58:59.219859 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6171 22:58:59.223624 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6172 22:58:59.226749 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6173 22:58:59.233403 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6174 22:58:59.236688 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6175 22:58:59.239959 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6176 22:58:59.246286 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6177 22:58:59.250046 ===================================
6178 22:58:59.250478 LPDDR4 DRAM CONFIGURATION
6179 22:58:59.252975 ===================================
6180 22:58:59.256766 EX_ROW_EN[0] = 0x0
6181 22:58:59.260037 EX_ROW_EN[1] = 0x0
6182 22:58:59.260610 LP4Y_EN = 0x0
6183 22:58:59.263147 WORK_FSP = 0x0
6184 22:58:59.263684 WL = 0x2
6185 22:58:59.266398 RL = 0x2
6186 22:58:59.266853 BL = 0x2
6187 22:58:59.270488 RPST = 0x0
6188 22:58:59.271114 RD_PRE = 0x0
6189 22:58:59.273500 WR_PRE = 0x1
6190 22:58:59.274123 WR_PST = 0x0
6191 22:58:59.276703 DBI_WR = 0x0
6192 22:58:59.277303 DBI_RD = 0x0
6193 22:58:59.280057 OTF = 0x1
6194 22:58:59.283410 ===================================
6195 22:58:59.286705 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6196 22:58:59.289878 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6197 22:58:59.296751 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6198 22:58:59.299574 ===================================
6199 22:58:59.300044 LPDDR4 DRAM CONFIGURATION
6200 22:58:59.303143 ===================================
6201 22:58:59.306298 EX_ROW_EN[0] = 0x10
6202 22:58:59.306839 EX_ROW_EN[1] = 0x0
6203 22:58:59.309337 LP4Y_EN = 0x0
6204 22:58:59.309904 WORK_FSP = 0x0
6205 22:58:59.312897 WL = 0x2
6206 22:58:59.316480 RL = 0x2
6207 22:58:59.317013 BL = 0x2
6208 22:58:59.320032 RPST = 0x0
6209 22:58:59.320510 RD_PRE = 0x0
6210 22:58:59.323067 WR_PRE = 0x1
6211 22:58:59.323581 WR_PST = 0x0
6212 22:58:59.325948 DBI_WR = 0x0
6213 22:58:59.326425 DBI_RD = 0x0
6214 22:58:59.330009 OTF = 0x1
6215 22:58:59.333483 ===================================
6216 22:58:59.336609 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6217 22:58:59.341715 nWR fixed to 30
6218 22:58:59.345120 [ModeRegInit_LP4] CH0 RK0
6219 22:58:59.345564 [ModeRegInit_LP4] CH0 RK1
6220 22:58:59.348404 [ModeRegInit_LP4] CH1 RK0
6221 22:58:59.351714 [ModeRegInit_LP4] CH1 RK1
6222 22:58:59.352274 match AC timing 19
6223 22:58:59.358735 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6224 22:58:59.362101 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6225 22:58:59.364937 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6226 22:58:59.371895 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6227 22:58:59.375067 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6228 22:58:59.375623 ==
6229 22:58:59.378547 Dram Type= 6, Freq= 0, CH_0, rank 0
6230 22:58:59.381676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6231 22:58:59.382113 ==
6232 22:58:59.388159 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6233 22:58:59.395425 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6234 22:58:59.398748 [CA 0] Center 36 (8~64) winsize 57
6235 22:58:59.401883 [CA 1] Center 36 (8~64) winsize 57
6236 22:58:59.405163 [CA 2] Center 36 (8~64) winsize 57
6237 22:58:59.405594 [CA 3] Center 36 (8~64) winsize 57
6238 22:58:59.408748 [CA 4] Center 36 (8~64) winsize 57
6239 22:58:59.411795 [CA 5] Center 36 (8~64) winsize 57
6240 22:58:59.412225
6241 22:58:59.414903 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6242 22:58:59.418526
6243 22:58:59.421688 [CATrainingPosCal] consider 1 rank data
6244 22:58:59.424669 u2DelayCellTimex100 = 270/100 ps
6245 22:58:59.428130 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 22:58:59.431723 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 22:58:59.434717 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 22:58:59.438072 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 22:58:59.441237 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 22:58:59.445149 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 22:58:59.445594
6252 22:58:59.448249 CA PerBit enable=1, Macro0, CA PI delay=36
6253 22:58:59.448677
6254 22:58:59.451478 [CBTSetCACLKResult] CA Dly = 36
6255 22:58:59.454889 CS Dly: 1 (0~32)
6256 22:58:59.455318 ==
6257 22:58:59.458134 Dram Type= 6, Freq= 0, CH_0, rank 1
6258 22:58:59.461378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6259 22:58:59.461878 ==
6260 22:58:59.468103 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6261 22:58:59.471159 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6262 22:58:59.474324 [CA 0] Center 36 (8~64) winsize 57
6263 22:58:59.477718 [CA 1] Center 36 (8~64) winsize 57
6264 22:58:59.481029 [CA 2] Center 36 (8~64) winsize 57
6265 22:58:59.484868 [CA 3] Center 36 (8~64) winsize 57
6266 22:58:59.488083 [CA 4] Center 36 (8~64) winsize 57
6267 22:58:59.491381 [CA 5] Center 36 (8~64) winsize 57
6268 22:58:59.491815
6269 22:58:59.494627 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6270 22:58:59.495058
6271 22:58:59.497903 [CATrainingPosCal] consider 2 rank data
6272 22:58:59.501380 u2DelayCellTimex100 = 270/100 ps
6273 22:58:59.504477 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 22:58:59.507850 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 22:58:59.511669 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 22:58:59.517958 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 22:58:59.520657 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 22:58:59.524421 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 22:58:59.524505
6280 22:58:59.527449 CA PerBit enable=1, Macro0, CA PI delay=36
6281 22:58:59.527532
6282 22:58:59.531013 [CBTSetCACLKResult] CA Dly = 36
6283 22:58:59.531097 CS Dly: 1 (0~32)
6284 22:58:59.531163
6285 22:58:59.534100 ----->DramcWriteLeveling(PI) begin...
6286 22:58:59.537681 ==
6287 22:58:59.537764 Dram Type= 6, Freq= 0, CH_0, rank 0
6288 22:58:59.543869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6289 22:58:59.543953 ==
6290 22:58:59.547808 Write leveling (Byte 0): 40 => 8
6291 22:58:59.551009 Write leveling (Byte 1): 40 => 8
6292 22:58:59.551086 DramcWriteLeveling(PI) end<-----
6293 22:58:59.554202
6294 22:58:59.554310 ==
6295 22:58:59.557485 Dram Type= 6, Freq= 0, CH_0, rank 0
6296 22:58:59.560793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6297 22:58:59.560938 ==
6298 22:58:59.564071 [Gating] SW mode calibration
6299 22:58:59.570443 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6300 22:58:59.573797 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6301 22:58:59.580588 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6302 22:58:59.583860 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6303 22:58:59.587481 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6304 22:58:59.593910 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6305 22:58:59.597282 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6306 22:58:59.600595 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6307 22:58:59.607026 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6308 22:58:59.610117 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6309 22:58:59.613422 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6310 22:58:59.617230 Total UI for P1: 0, mck2ui 16
6311 22:58:59.620391 best dqsien dly found for B0: ( 0, 14, 24)
6312 22:58:59.623679 Total UI for P1: 0, mck2ui 16
6313 22:58:59.626738 best dqsien dly found for B1: ( 0, 14, 24)
6314 22:58:59.630445 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6315 22:58:59.633499 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6316 22:58:59.633583
6317 22:58:59.640298 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6318 22:58:59.643914 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6319 22:58:59.646883 [Gating] SW calibration Done
6320 22:58:59.646967 ==
6321 22:58:59.650035 Dram Type= 6, Freq= 0, CH_0, rank 0
6322 22:58:59.653909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6323 22:58:59.654059 ==
6324 22:58:59.654171 RX Vref Scan: 0
6325 22:58:59.654234
6326 22:58:59.657063 RX Vref 0 -> 0, step: 1
6327 22:58:59.657146
6328 22:58:59.660434 RX Delay -410 -> 252, step: 16
6329 22:58:59.663816 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6330 22:58:59.670254 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6331 22:58:59.673432 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6332 22:58:59.676672 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6333 22:58:59.679853 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6334 22:58:59.686586 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6335 22:58:59.689875 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6336 22:58:59.693051 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6337 22:58:59.696652 iDelay=230, Bit 8, Center -27 (-250 ~ 197) 448
6338 22:58:59.703312 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6339 22:58:59.706557 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6340 22:58:59.709761 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6341 22:58:59.713155 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6342 22:58:59.719699 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6343 22:58:59.723182 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6344 22:58:59.726480 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6345 22:58:59.726555 ==
6346 22:58:59.729900 Dram Type= 6, Freq= 0, CH_0, rank 0
6347 22:58:59.732973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 22:58:59.736592 ==
6349 22:58:59.736674 DQS Delay:
6350 22:58:59.736738 DQS0 = 27, DQS1 = 35
6351 22:58:59.739532 DQM Delay:
6352 22:58:59.739614 DQM0 = 10, DQM1 = 12
6353 22:58:59.743203 DQ Delay:
6354 22:58:59.746175 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6355 22:58:59.746257 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6356 22:58:59.749823 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6357 22:58:59.752853 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6358 22:58:59.752934
6359 22:58:59.752998
6360 22:58:59.756616 ==
6361 22:58:59.759966 Dram Type= 6, Freq= 0, CH_0, rank 0
6362 22:58:59.763051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6363 22:58:59.763133 ==
6364 22:58:59.763197
6365 22:58:59.763265
6366 22:58:59.766380 TX Vref Scan disable
6367 22:58:59.766461 == TX Byte 0 ==
6368 22:58:59.769611 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6369 22:58:59.776096 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6370 22:58:59.776180 == TX Byte 1 ==
6371 22:58:59.779970 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6372 22:58:59.783164 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6373 22:58:59.786571 ==
6374 22:58:59.789637 Dram Type= 6, Freq= 0, CH_0, rank 0
6375 22:58:59.792769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6376 22:58:59.792851 ==
6377 22:58:59.792915
6378 22:58:59.792975
6379 22:58:59.796111 TX Vref Scan disable
6380 22:58:59.796192 == TX Byte 0 ==
6381 22:58:59.799801 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6382 22:58:59.806125 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6383 22:58:59.806208 == TX Byte 1 ==
6384 22:58:59.810191 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6385 22:58:59.812762 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6386 22:58:59.816623
6387 22:58:59.816706 [DATLAT]
6388 22:58:59.816771 Freq=400, CH0 RK0
6389 22:58:59.816833
6390 22:58:59.819845 DATLAT Default: 0xf
6391 22:58:59.819927 0, 0xFFFF, sum = 0
6392 22:58:59.823131 1, 0xFFFF, sum = 0
6393 22:58:59.823215 2, 0xFFFF, sum = 0
6394 22:58:59.826349 3, 0xFFFF, sum = 0
6395 22:58:59.826433 4, 0xFFFF, sum = 0
6396 22:58:59.829499 5, 0xFFFF, sum = 0
6397 22:58:59.832846 6, 0xFFFF, sum = 0
6398 22:58:59.832931 7, 0xFFFF, sum = 0
6399 22:58:59.836071 8, 0xFFFF, sum = 0
6400 22:58:59.836154 9, 0xFFFF, sum = 0
6401 22:58:59.839293 10, 0xFFFF, sum = 0
6402 22:58:59.839399 11, 0xFFFF, sum = 0
6403 22:58:59.842934 12, 0xFFFF, sum = 0
6404 22:58:59.843017 13, 0x0, sum = 1
6405 22:58:59.846517 14, 0x0, sum = 2
6406 22:58:59.846601 15, 0x0, sum = 3
6407 22:58:59.849404 16, 0x0, sum = 4
6408 22:58:59.849488 best_step = 14
6409 22:58:59.849553
6410 22:58:59.849613 ==
6411 22:58:59.853108 Dram Type= 6, Freq= 0, CH_0, rank 0
6412 22:58:59.856097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6413 22:58:59.856181 ==
6414 22:58:59.859797 RX Vref Scan: 1
6415 22:58:59.859879
6416 22:58:59.862909 RX Vref 0 -> 0, step: 1
6417 22:58:59.862991
6418 22:58:59.863056 RX Delay -311 -> 252, step: 8
6419 22:58:59.863117
6420 22:58:59.865911 Set Vref, RX VrefLevel [Byte0]: 56
6421 22:58:59.869263 [Byte1]: 57
6422 22:58:59.874956
6423 22:58:59.875039 Final RX Vref Byte 0 = 56 to rank0
6424 22:58:59.878333 Final RX Vref Byte 1 = 57 to rank0
6425 22:58:59.881472 Final RX Vref Byte 0 = 56 to rank1
6426 22:58:59.884541 Final RX Vref Byte 1 = 57 to rank1==
6427 22:58:59.888473 Dram Type= 6, Freq= 0, CH_0, rank 0
6428 22:58:59.895092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6429 22:58:59.895175 ==
6430 22:58:59.895241 DQS Delay:
6431 22:58:59.898156 DQS0 = 24, DQS1 = 36
6432 22:58:59.898239 DQM Delay:
6433 22:58:59.898304 DQM0 = 7, DQM1 = 13
6434 22:58:59.901222 DQ Delay:
6435 22:58:59.901304 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6436 22:58:59.905037 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6437 22:58:59.908250 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6438 22:58:59.911483 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6439 22:58:59.911566
6440 22:58:59.911631
6441 22:58:59.921520 [DQSOSCAuto] RK0, (LSB)MR18= 0xcab7, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 384 ps
6442 22:58:59.924716 CH0 RK0: MR19=C0C, MR18=CAB7
6443 22:58:59.928058 CH0_RK0: MR19=0xC0C, MR18=0xCAB7, DQSOSC=384, MR23=63, INC=400, DEC=267
6444 22:58:59.931784 ==
6445 22:58:59.934954 Dram Type= 6, Freq= 0, CH_0, rank 1
6446 22:58:59.938211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 22:58:59.938294 ==
6448 22:58:59.941563 [Gating] SW mode calibration
6449 22:58:59.948037 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6450 22:58:59.951150 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6451 22:58:59.958010 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6452 22:58:59.961487 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6453 22:58:59.964424 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6454 22:58:59.971123 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6455 22:58:59.974437 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6456 22:58:59.978209 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6457 22:58:59.984806 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6458 22:58:59.988038 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6459 22:58:59.991300 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6460 22:58:59.994586 Total UI for P1: 0, mck2ui 16
6461 22:58:59.997883 best dqsien dly found for B0: ( 0, 14, 24)
6462 22:59:00.001215 Total UI for P1: 0, mck2ui 16
6463 22:59:00.004933 best dqsien dly found for B1: ( 0, 14, 24)
6464 22:59:00.008130 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6465 22:59:00.011211 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6466 22:59:00.011319
6467 22:59:00.017761 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6468 22:59:00.021638 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6469 22:59:00.021722 [Gating] SW calibration Done
6470 22:59:00.024667 ==
6471 22:59:00.028299 Dram Type= 6, Freq= 0, CH_0, rank 1
6472 22:59:00.031535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6473 22:59:00.031619 ==
6474 22:59:00.031684 RX Vref Scan: 0
6475 22:59:00.031743
6476 22:59:00.034854 RX Vref 0 -> 0, step: 1
6477 22:59:00.034937
6478 22:59:00.038063 RX Delay -410 -> 252, step: 16
6479 22:59:00.041253 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6480 22:59:00.044473 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6481 22:59:00.051732 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6482 22:59:00.054392 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6483 22:59:00.058126 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6484 22:59:00.061198 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6485 22:59:00.067946 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6486 22:59:00.071663 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6487 22:59:00.074682 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6488 22:59:00.078376 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6489 22:59:00.084452 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6490 22:59:00.087670 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6491 22:59:00.091270 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6492 22:59:00.094591 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6493 22:59:00.101072 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6494 22:59:00.104381 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6495 22:59:00.104464 ==
6496 22:59:00.107760 Dram Type= 6, Freq= 0, CH_0, rank 1
6497 22:59:00.110836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 22:59:00.110935 ==
6499 22:59:00.114447 DQS Delay:
6500 22:59:00.114530 DQS0 = 19, DQS1 = 35
6501 22:59:00.117452 DQM Delay:
6502 22:59:00.117533 DQM0 = 5, DQM1 = 10
6503 22:59:00.117598 DQ Delay:
6504 22:59:00.121214 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6505 22:59:00.124426 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6506 22:59:00.127647 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6507 22:59:00.130795 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6508 22:59:00.130877
6509 22:59:00.130942
6510 22:59:00.131002 ==
6511 22:59:00.134559 Dram Type= 6, Freq= 0, CH_0, rank 1
6512 22:59:00.140748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6513 22:59:00.140832 ==
6514 22:59:00.140898
6515 22:59:00.140958
6516 22:59:00.141030 TX Vref Scan disable
6517 22:59:00.144129 == TX Byte 0 ==
6518 22:59:00.147802 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6519 22:59:00.150978 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6520 22:59:00.154416 == TX Byte 1 ==
6521 22:59:00.158514 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6522 22:59:00.161319 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6523 22:59:00.161756 ==
6524 22:59:00.164863 Dram Type= 6, Freq= 0, CH_0, rank 1
6525 22:59:00.170956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6526 22:59:00.171546 ==
6527 22:59:00.172083
6528 22:59:00.172434
6529 22:59:00.172783 TX Vref Scan disable
6530 22:59:00.174048 == TX Byte 0 ==
6531 22:59:00.177899 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6532 22:59:00.180987 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6533 22:59:00.184192 == TX Byte 1 ==
6534 22:59:00.187881 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6535 22:59:00.191042 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6536 22:59:00.191599
6537 22:59:00.194124 [DATLAT]
6538 22:59:00.194542 Freq=400, CH0 RK1
6539 22:59:00.194878
6540 22:59:00.197499 DATLAT Default: 0xe
6541 22:59:00.197919 0, 0xFFFF, sum = 0
6542 22:59:00.200753 1, 0xFFFF, sum = 0
6543 22:59:00.201182 2, 0xFFFF, sum = 0
6544 22:59:00.204622 3, 0xFFFF, sum = 0
6545 22:59:00.205222 4, 0xFFFF, sum = 0
6546 22:59:00.207775 5, 0xFFFF, sum = 0
6547 22:59:00.208493 6, 0xFFFF, sum = 0
6548 22:59:00.210948 7, 0xFFFF, sum = 0
6549 22:59:00.211408 8, 0xFFFF, sum = 0
6550 22:59:00.214027 9, 0xFFFF, sum = 0
6551 22:59:00.214580 10, 0xFFFF, sum = 0
6552 22:59:00.217410 11, 0xFFFF, sum = 0
6553 22:59:00.220481 12, 0xFFFF, sum = 0
6554 22:59:00.220913 13, 0x0, sum = 1
6555 22:59:00.221258 14, 0x0, sum = 2
6556 22:59:00.224432 15, 0x0, sum = 3
6557 22:59:00.224966 16, 0x0, sum = 4
6558 22:59:00.227358 best_step = 14
6559 22:59:00.227784
6560 22:59:00.228120 ==
6561 22:59:00.231188 Dram Type= 6, Freq= 0, CH_0, rank 1
6562 22:59:00.233870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6563 22:59:00.234295 ==
6564 22:59:00.238032 RX Vref Scan: 0
6565 22:59:00.238559
6566 22:59:00.238895 RX Vref 0 -> 0, step: 1
6567 22:59:00.239208
6568 22:59:00.240940 RX Delay -311 -> 252, step: 8
6569 22:59:00.248946 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6570 22:59:00.252303 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6571 22:59:00.255697 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6572 22:59:00.259071 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6573 22:59:00.265600 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6574 22:59:00.268772 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6575 22:59:00.272185 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6576 22:59:00.275053 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6577 22:59:00.281921 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6578 22:59:00.284951 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6579 22:59:00.288544 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6580 22:59:00.291665 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6581 22:59:00.298396 iDelay=217, Bit 12, Center -16 (-239 ~ 208) 448
6582 22:59:00.302510 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6583 22:59:00.305304 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6584 22:59:00.312311 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6585 22:59:00.312836 ==
6586 22:59:00.315542 Dram Type= 6, Freq= 0, CH_0, rank 1
6587 22:59:00.319061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6588 22:59:00.319718 ==
6589 22:59:00.320348 DQS Delay:
6590 22:59:00.321941 DQS0 = 24, DQS1 = 32
6591 22:59:00.322568 DQM Delay:
6592 22:59:00.325038 DQM0 = 8, DQM1 = 10
6593 22:59:00.325503 DQ Delay:
6594 22:59:00.328287 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6595 22:59:00.332148 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6596 22:59:00.335286 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6597 22:59:00.338584 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6598 22:59:00.339115
6599 22:59:00.339493
6600 22:59:00.345069 [DQSOSCAuto] RK1, (LSB)MR18= 0xc061, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 386 ps
6601 22:59:00.348349 CH0 RK1: MR19=C0C, MR18=C061
6602 22:59:00.354834 CH0_RK1: MR19=0xC0C, MR18=0xC061, DQSOSC=386, MR23=63, INC=396, DEC=264
6603 22:59:00.357906 [RxdqsGatingPostProcess] freq 400
6604 22:59:00.361763 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6605 22:59:00.365116 best DQS0 dly(2T, 0.5T) = (0, 10)
6606 22:59:00.368381 best DQS1 dly(2T, 0.5T) = (0, 10)
6607 22:59:00.371787 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6608 22:59:00.375016 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6609 22:59:00.378270 best DQS0 dly(2T, 0.5T) = (0, 10)
6610 22:59:00.381448 best DQS1 dly(2T, 0.5T) = (0, 10)
6611 22:59:00.385186 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6612 22:59:00.388041 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6613 22:59:00.391489 Pre-setting of DQS Precalculation
6614 22:59:00.397650 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6615 22:59:00.398270 ==
6616 22:59:00.401471 Dram Type= 6, Freq= 0, CH_1, rank 0
6617 22:59:00.404524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6618 22:59:00.404955 ==
6619 22:59:00.408321 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6620 22:59:00.415058 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6621 22:59:00.418387 [CA 0] Center 36 (8~64) winsize 57
6622 22:59:00.421660 [CA 1] Center 36 (8~64) winsize 57
6623 22:59:00.424580 [CA 2] Center 36 (8~64) winsize 57
6624 22:59:00.427869 [CA 3] Center 36 (8~64) winsize 57
6625 22:59:00.431203 [CA 4] Center 36 (8~64) winsize 57
6626 22:59:00.434326 [CA 5] Center 36 (8~64) winsize 57
6627 22:59:00.434797
6628 22:59:00.437892 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6629 22:59:00.438364
6630 22:59:00.441204 [CATrainingPosCal] consider 1 rank data
6631 22:59:00.445190 u2DelayCellTimex100 = 270/100 ps
6632 22:59:00.448194 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 22:59:00.451423 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 22:59:00.454558 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 22:59:00.457590 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 22:59:00.461068 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 22:59:00.467912 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 22:59:00.468338
6639 22:59:00.471078 CA PerBit enable=1, Macro0, CA PI delay=36
6640 22:59:00.471552
6641 22:59:00.474190 [CBTSetCACLKResult] CA Dly = 36
6642 22:59:00.474616 CS Dly: 1 (0~32)
6643 22:59:00.474954 ==
6644 22:59:00.478058 Dram Type= 6, Freq= 0, CH_1, rank 1
6645 22:59:00.481271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6646 22:59:00.484464 ==
6647 22:59:00.487810 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6648 22:59:00.494319 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6649 22:59:00.497616 [CA 0] Center 36 (8~64) winsize 57
6650 22:59:00.501196 [CA 1] Center 36 (8~64) winsize 57
6651 22:59:00.504198 [CA 2] Center 36 (8~64) winsize 57
6652 22:59:00.507739 [CA 3] Center 36 (8~64) winsize 57
6653 22:59:00.511041 [CA 4] Center 36 (8~64) winsize 57
6654 22:59:00.514168 [CA 5] Center 36 (8~64) winsize 57
6655 22:59:00.514598
6656 22:59:00.518038 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6657 22:59:00.518469
6658 22:59:00.521029 [CATrainingPosCal] consider 2 rank data
6659 22:59:00.524470 u2DelayCellTimex100 = 270/100 ps
6660 22:59:00.527771 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 22:59:00.531058 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 22:59:00.534329 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 22:59:00.537525 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 22:59:00.541474 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 22:59:00.544414 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 22:59:00.544874
6667 22:59:00.547859 CA PerBit enable=1, Macro0, CA PI delay=36
6668 22:59:00.548431
6669 22:59:00.550980 [CBTSetCACLKResult] CA Dly = 36
6670 22:59:00.554321 CS Dly: 1 (0~32)
6671 22:59:00.554816
6672 22:59:00.557676 ----->DramcWriteLeveling(PI) begin...
6673 22:59:00.558131 ==
6674 22:59:00.560885 Dram Type= 6, Freq= 0, CH_1, rank 0
6675 22:59:00.564149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6676 22:59:00.564650 ==
6677 22:59:00.567807 Write leveling (Byte 0): 40 => 8
6678 22:59:00.570930 Write leveling (Byte 1): 40 => 8
6679 22:59:00.574120 DramcWriteLeveling(PI) end<-----
6680 22:59:00.574550
6681 22:59:00.574887 ==
6682 22:59:00.577952 Dram Type= 6, Freq= 0, CH_1, rank 0
6683 22:59:00.581013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6684 22:59:00.581742 ==
6685 22:59:00.584305 [Gating] SW mode calibration
6686 22:59:00.590909 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6687 22:59:00.597796 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6688 22:59:00.600735 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6689 22:59:00.604566 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6690 22:59:00.611165 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6691 22:59:00.614065 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6692 22:59:00.617903 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6693 22:59:00.624297 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6694 22:59:00.627425 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6695 22:59:00.631314 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6696 22:59:00.637971 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6697 22:59:00.638405 Total UI for P1: 0, mck2ui 16
6698 22:59:00.644465 best dqsien dly found for B0: ( 0, 14, 24)
6699 22:59:00.644900 Total UI for P1: 0, mck2ui 16
6700 22:59:00.651016 best dqsien dly found for B1: ( 0, 14, 24)
6701 22:59:00.654335 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6702 22:59:00.657496 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6703 22:59:00.658109
6704 22:59:00.660750 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6705 22:59:00.664031 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6706 22:59:00.667308 [Gating] SW calibration Done
6707 22:59:00.667789 ==
6708 22:59:00.671407 Dram Type= 6, Freq= 0, CH_1, rank 0
6709 22:59:00.674845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6710 22:59:00.675437 ==
6711 22:59:00.677629 RX Vref Scan: 0
6712 22:59:00.678057
6713 22:59:00.678402 RX Vref 0 -> 0, step: 1
6714 22:59:00.678725
6715 22:59:00.680767 RX Delay -410 -> 252, step: 16
6716 22:59:00.687784 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6717 22:59:00.690893 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6718 22:59:00.694216 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6719 22:59:00.697395 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6720 22:59:00.704189 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6721 22:59:00.707170 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6722 22:59:00.710742 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6723 22:59:00.713874 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6724 22:59:00.720457 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6725 22:59:00.723452 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6726 22:59:00.727053 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6727 22:59:00.730116 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6728 22:59:00.736768 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6729 22:59:00.740173 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6730 22:59:00.743955 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6731 22:59:00.747315 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6732 22:59:00.750523 ==
6733 22:59:00.753104 Dram Type= 6, Freq= 0, CH_1, rank 0
6734 22:59:00.756444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 22:59:00.756528 ==
6736 22:59:00.756602 DQS Delay:
6737 22:59:00.760046 DQS0 = 35, DQS1 = 35
6738 22:59:00.760130 DQM Delay:
6739 22:59:00.763046 DQM0 = 18, DQM1 = 13
6740 22:59:00.763129 DQ Delay:
6741 22:59:00.766330 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6742 22:59:00.770047 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6743 22:59:00.773311 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6744 22:59:00.776553 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6745 22:59:00.776653
6746 22:59:00.776743
6747 22:59:00.776831 ==
6748 22:59:00.779908 Dram Type= 6, Freq= 0, CH_1, rank 0
6749 22:59:00.783155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6750 22:59:00.783256 ==
6751 22:59:00.783390
6752 22:59:00.783453
6753 22:59:00.786337 TX Vref Scan disable
6754 22:59:00.786407 == TX Byte 0 ==
6755 22:59:00.793069 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6756 22:59:00.796330 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6757 22:59:00.796406 == TX Byte 1 ==
6758 22:59:00.803445 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6759 22:59:00.806770 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6760 22:59:00.806855 ==
6761 22:59:00.809991 Dram Type= 6, Freq= 0, CH_1, rank 0
6762 22:59:00.813324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6763 22:59:00.813398 ==
6764 22:59:00.813461
6765 22:59:00.813521
6766 22:59:00.816530 TX Vref Scan disable
6767 22:59:00.816600 == TX Byte 0 ==
6768 22:59:00.822848 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6769 22:59:00.826165 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6770 22:59:00.826242 == TX Byte 1 ==
6771 22:59:00.833139 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6772 22:59:00.836198 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6773 22:59:00.836276
6774 22:59:00.836340 [DATLAT]
6775 22:59:00.839765 Freq=400, CH1 RK0
6776 22:59:00.839838
6777 22:59:00.839899 DATLAT Default: 0xf
6778 22:59:00.842902 0, 0xFFFF, sum = 0
6779 22:59:00.842979 1, 0xFFFF, sum = 0
6780 22:59:00.846472 2, 0xFFFF, sum = 0
6781 22:59:00.846578 3, 0xFFFF, sum = 0
6782 22:59:00.849642 4, 0xFFFF, sum = 0
6783 22:59:00.849718 5, 0xFFFF, sum = 0
6784 22:59:00.852865 6, 0xFFFF, sum = 0
6785 22:59:00.852938 7, 0xFFFF, sum = 0
6786 22:59:00.856133 8, 0xFFFF, sum = 0
6787 22:59:00.859505 9, 0xFFFF, sum = 0
6788 22:59:00.859596 10, 0xFFFF, sum = 0
6789 22:59:00.863422 11, 0xFFFF, sum = 0
6790 22:59:00.863507 12, 0xFFFF, sum = 0
6791 22:59:00.866449 13, 0x0, sum = 1
6792 22:59:00.866534 14, 0x0, sum = 2
6793 22:59:00.869434 15, 0x0, sum = 3
6794 22:59:00.869510 16, 0x0, sum = 4
6795 22:59:00.869574 best_step = 14
6796 22:59:00.869633
6797 22:59:00.873009 ==
6798 22:59:00.876178 Dram Type= 6, Freq= 0, CH_1, rank 0
6799 22:59:00.879361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6800 22:59:00.879456 ==
6801 22:59:00.879552 RX Vref Scan: 1
6802 22:59:00.879615
6803 22:59:00.883262 RX Vref 0 -> 0, step: 1
6804 22:59:00.883365
6805 22:59:00.885923 RX Delay -311 -> 252, step: 8
6806 22:59:00.886003
6807 22:59:00.889761 Set Vref, RX VrefLevel [Byte0]: 52
6808 22:59:00.892815 [Byte1]: 48
6809 22:59:00.896512
6810 22:59:00.896585 Final RX Vref Byte 0 = 52 to rank0
6811 22:59:00.899986 Final RX Vref Byte 1 = 48 to rank0
6812 22:59:00.903152 Final RX Vref Byte 0 = 52 to rank1
6813 22:59:00.906377 Final RX Vref Byte 1 = 48 to rank1==
6814 22:59:00.909626 Dram Type= 6, Freq= 0, CH_1, rank 0
6815 22:59:00.916113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6816 22:59:00.916189 ==
6817 22:59:00.916253 DQS Delay:
6818 22:59:00.919488 DQS0 = 32, DQS1 = 32
6819 22:59:00.919589 DQM Delay:
6820 22:59:00.919694 DQM0 = 13, DQM1 = 11
6821 22:59:00.923132 DQ Delay:
6822 22:59:00.926409 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6823 22:59:00.929711 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =12
6824 22:59:00.929785 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6825 22:59:00.932969 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
6826 22:59:00.933068
6827 22:59:00.936663
6828 22:59:00.943255 [DQSOSCAuto] RK0, (LSB)MR18= 0x93cc, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6829 22:59:00.946321 CH1 RK0: MR19=C0C, MR18=93CC
6830 22:59:00.952953 CH1_RK0: MR19=0xC0C, MR18=0x93CC, DQSOSC=384, MR23=63, INC=400, DEC=267
6831 22:59:00.953050 ==
6832 22:59:00.956005 Dram Type= 6, Freq= 0, CH_1, rank 1
6833 22:59:00.959733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 22:59:00.959811 ==
6835 22:59:00.963093 [Gating] SW mode calibration
6836 22:59:00.969631 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6837 22:59:00.976594 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6838 22:59:00.979624 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6839 22:59:00.982751 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6840 22:59:00.986347 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6841 22:59:00.992969 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6842 22:59:00.996281 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6843 22:59:00.999472 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6844 22:59:01.006164 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6845 22:59:01.009768 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6846 22:59:01.012916 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6847 22:59:01.016205 Total UI for P1: 0, mck2ui 16
6848 22:59:01.019544 best dqsien dly found for B0: ( 0, 14, 24)
6849 22:59:01.022876 Total UI for P1: 0, mck2ui 16
6850 22:59:01.026059 best dqsien dly found for B1: ( 0, 14, 24)
6851 22:59:01.029333 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6852 22:59:01.032596 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6853 22:59:01.036433
6854 22:59:01.039728 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6855 22:59:01.042990 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6856 22:59:01.046624 [Gating] SW calibration Done
6857 22:59:01.046708 ==
6858 22:59:01.049476 Dram Type= 6, Freq= 0, CH_1, rank 1
6859 22:59:01.052527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6860 22:59:01.052611 ==
6861 22:59:01.052678 RX Vref Scan: 0
6862 22:59:01.052740
6863 22:59:01.056266 RX Vref 0 -> 0, step: 1
6864 22:59:01.056350
6865 22:59:01.059370 RX Delay -410 -> 252, step: 16
6866 22:59:01.062558 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6867 22:59:01.069056 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6868 22:59:01.072945 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6869 22:59:01.075651 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6870 22:59:01.079450 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6871 22:59:01.085947 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6872 22:59:01.089215 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6873 22:59:01.092767 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6874 22:59:01.096386 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6875 22:59:01.099602 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6876 22:59:01.105713 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6877 22:59:01.108847 iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464
6878 22:59:01.112492 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6879 22:59:01.119267 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6880 22:59:01.122682 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6881 22:59:01.125942 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6882 22:59:01.126026 ==
6883 22:59:01.129248 Dram Type= 6, Freq= 0, CH_1, rank 1
6884 22:59:01.132370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 22:59:01.135568 ==
6886 22:59:01.135652 DQS Delay:
6887 22:59:01.135719 DQS0 = 35, DQS1 = 35
6888 22:59:01.138873 DQM Delay:
6889 22:59:01.138956 DQM0 = 17, DQM1 = 14
6890 22:59:01.142070 DQ Delay:
6891 22:59:01.145388 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6892 22:59:01.145471 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6893 22:59:01.148597 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6894 22:59:01.155146 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6895 22:59:01.155230
6896 22:59:01.155296
6897 22:59:01.155397 ==
6898 22:59:01.158755 Dram Type= 6, Freq= 0, CH_1, rank 1
6899 22:59:01.162466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6900 22:59:01.162551 ==
6901 22:59:01.162617
6902 22:59:01.162678
6903 22:59:01.165504 TX Vref Scan disable
6904 22:59:01.165587 == TX Byte 0 ==
6905 22:59:01.168691 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6906 22:59:01.175488 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6907 22:59:01.175572 == TX Byte 1 ==
6908 22:59:01.178754 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6909 22:59:01.185014 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6910 22:59:01.185099 ==
6911 22:59:01.188331 Dram Type= 6, Freq= 0, CH_1, rank 1
6912 22:59:01.191640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6913 22:59:01.191725 ==
6914 22:59:01.191792
6915 22:59:01.191854
6916 22:59:01.194823 TX Vref Scan disable
6917 22:59:01.194907 == TX Byte 0 ==
6918 22:59:01.201540 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6919 22:59:01.205191 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6920 22:59:01.205276 == TX Byte 1 ==
6921 22:59:01.208422 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6922 22:59:01.214879 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6923 22:59:01.214963
6924 22:59:01.215030 [DATLAT]
6925 22:59:01.218596 Freq=400, CH1 RK1
6926 22:59:01.218681
6927 22:59:01.218760 DATLAT Default: 0xe
6928 22:59:01.221839 0, 0xFFFF, sum = 0
6929 22:59:01.221925 1, 0xFFFF, sum = 0
6930 22:59:01.225212 2, 0xFFFF, sum = 0
6931 22:59:01.225309 3, 0xFFFF, sum = 0
6932 22:59:01.228353 4, 0xFFFF, sum = 0
6933 22:59:01.228439 5, 0xFFFF, sum = 0
6934 22:59:01.231722 6, 0xFFFF, sum = 0
6935 22:59:01.231810 7, 0xFFFF, sum = 0
6936 22:59:01.234918 8, 0xFFFF, sum = 0
6937 22:59:01.235003 9, 0xFFFF, sum = 0
6938 22:59:01.238644 10, 0xFFFF, sum = 0
6939 22:59:01.238729 11, 0xFFFF, sum = 0
6940 22:59:01.241996 12, 0xFFFF, sum = 0
6941 22:59:01.242082 13, 0x0, sum = 1
6942 22:59:01.245119 14, 0x0, sum = 2
6943 22:59:01.245204 15, 0x0, sum = 3
6944 22:59:01.248372 16, 0x0, sum = 4
6945 22:59:01.248465 best_step = 14
6946 22:59:01.248533
6947 22:59:01.248595 ==
6948 22:59:01.251579 Dram Type= 6, Freq= 0, CH_1, rank 1
6949 22:59:01.258073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6950 22:59:01.258157 ==
6951 22:59:01.258225 RX Vref Scan: 0
6952 22:59:01.258287
6953 22:59:01.261951 RX Vref 0 -> 0, step: 1
6954 22:59:01.262050
6955 22:59:01.264965 RX Delay -311 -> 252, step: 8
6956 22:59:01.271617 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6957 22:59:01.274629 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6958 22:59:01.278387 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6959 22:59:01.281331 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6960 22:59:01.287998 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6961 22:59:01.291237 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6962 22:59:01.294460 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6963 22:59:01.298354 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6964 22:59:01.301449 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6965 22:59:01.307993 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6966 22:59:01.311767 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
6967 22:59:01.314860 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6968 22:59:01.321385 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6969 22:59:01.324702 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6970 22:59:01.327792 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6971 22:59:01.331469 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6972 22:59:01.331589 ==
6973 22:59:01.334595 Dram Type= 6, Freq= 0, CH_1, rank 1
6974 22:59:01.341502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6975 22:59:01.341596 ==
6976 22:59:01.341662 DQS Delay:
6977 22:59:01.344713 DQS0 = 28, DQS1 = 32
6978 22:59:01.344784 DQM Delay:
6979 22:59:01.348018 DQM0 = 10, DQM1 = 11
6980 22:59:01.348101 DQ Delay:
6981 22:59:01.351217 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6982 22:59:01.354383 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6983 22:59:01.354467 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6984 22:59:01.361571 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6985 22:59:01.361654
6986 22:59:01.361721
6987 22:59:01.368136 [DQSOSCAuto] RK1, (LSB)MR18= 0xc759, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
6988 22:59:01.371237 CH1 RK1: MR19=C0C, MR18=C759
6989 22:59:01.378404 CH1_RK1: MR19=0xC0C, MR18=0xC759, DQSOSC=385, MR23=63, INC=398, DEC=265
6990 22:59:01.381313 [RxdqsGatingPostProcess] freq 400
6991 22:59:01.384405 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6992 22:59:01.387590 best DQS0 dly(2T, 0.5T) = (0, 10)
6993 22:59:01.391333 best DQS1 dly(2T, 0.5T) = (0, 10)
6994 22:59:01.394411 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6995 22:59:01.397710 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6996 22:59:01.401035 best DQS0 dly(2T, 0.5T) = (0, 10)
6997 22:59:01.404449 best DQS1 dly(2T, 0.5T) = (0, 10)
6998 22:59:01.408115 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6999 22:59:01.411398 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7000 22:59:01.414643 Pre-setting of DQS Precalculation
7001 22:59:01.417751 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7002 22:59:01.424579 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7003 22:59:01.434293 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7004 22:59:01.434377
7005 22:59:01.434444
7006 22:59:01.437472 [Calibration Summary] 800 Mbps
7007 22:59:01.437548 CH 0, Rank 0
7008 22:59:01.441279 SW Impedance : PASS
7009 22:59:01.441393 DUTY Scan : NO K
7010 22:59:01.444236 ZQ Calibration : PASS
7011 22:59:01.447739 Jitter Meter : NO K
7012 22:59:01.447853 CBT Training : PASS
7013 22:59:01.450958 Write leveling : PASS
7014 22:59:01.451062 RX DQS gating : PASS
7015 22:59:01.454219 RX DQ/DQS(RDDQC) : PASS
7016 22:59:01.457612 TX DQ/DQS : PASS
7017 22:59:01.457685 RX DATLAT : PASS
7018 22:59:01.460770 RX DQ/DQS(Engine): PASS
7019 22:59:01.464028 TX OE : NO K
7020 22:59:01.464103 All Pass.
7021 22:59:01.464175
7022 22:59:01.464234 CH 0, Rank 1
7023 22:59:01.467276 SW Impedance : PASS
7024 22:59:01.470641 DUTY Scan : NO K
7025 22:59:01.470727 ZQ Calibration : PASS
7026 22:59:01.474478 Jitter Meter : NO K
7027 22:59:01.477523 CBT Training : PASS
7028 22:59:01.477641 Write leveling : NO K
7029 22:59:01.480748 RX DQS gating : PASS
7030 22:59:01.484133 RX DQ/DQS(RDDQC) : PASS
7031 22:59:01.484217 TX DQ/DQS : PASS
7032 22:59:01.487716 RX DATLAT : PASS
7033 22:59:01.490873 RX DQ/DQS(Engine): PASS
7034 22:59:01.490978 TX OE : NO K
7035 22:59:01.491070 All Pass.
7036 22:59:01.494033
7037 22:59:01.494130 CH 1, Rank 0
7038 22:59:01.497538 SW Impedance : PASS
7039 22:59:01.497646 DUTY Scan : NO K
7040 22:59:01.500678 ZQ Calibration : PASS
7041 22:59:01.500779 Jitter Meter : NO K
7042 22:59:01.503865 CBT Training : PASS
7043 22:59:01.507398 Write leveling : PASS
7044 22:59:01.507476 RX DQS gating : PASS
7045 22:59:01.510497 RX DQ/DQS(RDDQC) : PASS
7046 22:59:01.514310 TX DQ/DQS : PASS
7047 22:59:01.514389 RX DATLAT : PASS
7048 22:59:01.517484 RX DQ/DQS(Engine): PASS
7049 22:59:01.520732 TX OE : NO K
7050 22:59:01.520805 All Pass.
7051 22:59:01.520867
7052 22:59:01.520938 CH 1, Rank 1
7053 22:59:01.523879 SW Impedance : PASS
7054 22:59:01.527613 DUTY Scan : NO K
7055 22:59:01.527713 ZQ Calibration : PASS
7056 22:59:01.530958 Jitter Meter : NO K
7057 22:59:01.534069 CBT Training : PASS
7058 22:59:01.534168 Write leveling : NO K
7059 22:59:01.537265 RX DQS gating : PASS
7060 22:59:01.540402 RX DQ/DQS(RDDQC) : PASS
7061 22:59:01.540513 TX DQ/DQS : PASS
7062 22:59:01.544186 RX DATLAT : PASS
7063 22:59:01.547306 RX DQ/DQS(Engine): PASS
7064 22:59:01.547434 TX OE : NO K
7065 22:59:01.547499 All Pass.
7066 22:59:01.547569
7067 22:59:01.550339 DramC Write-DBI off
7068 22:59:01.554179 PER_BANK_REFRESH: Hybrid Mode
7069 22:59:01.554306 TX_TRACKING: ON
7070 22:59:01.563854 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7071 22:59:01.567059 [FAST_K] Save calibration result to emmc
7072 22:59:01.570331 dramc_set_vcore_voltage set vcore to 725000
7073 22:59:01.573621 Read voltage for 1600, 0
7074 22:59:01.573720 Vio18 = 0
7075 22:59:01.576992 Vcore = 725000
7076 22:59:01.577064 Vdram = 0
7077 22:59:01.577125 Vddq = 0
7078 22:59:01.577226 Vmddr = 0
7079 22:59:01.583922 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7080 22:59:01.590437 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7081 22:59:01.590526 MEM_TYPE=3, freq_sel=13
7082 22:59:01.593546 sv_algorithm_assistance_LP4_3733
7083 22:59:01.597396 ============ PULL DRAM RESETB DOWN ============
7084 22:59:01.604021 ========== PULL DRAM RESETB DOWN end =========
7085 22:59:01.607118 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7086 22:59:01.610305 ===================================
7087 22:59:01.613621 LPDDR4 DRAM CONFIGURATION
7088 22:59:01.616706 ===================================
7089 22:59:01.616781 EX_ROW_EN[0] = 0x0
7090 22:59:01.620477 EX_ROW_EN[1] = 0x0
7091 22:59:01.620578 LP4Y_EN = 0x0
7092 22:59:01.623690 WORK_FSP = 0x1
7093 22:59:01.623769 WL = 0x5
7094 22:59:01.627110 RL = 0x5
7095 22:59:01.630431 BL = 0x2
7096 22:59:01.630542 RPST = 0x0
7097 22:59:01.633525 RD_PRE = 0x0
7098 22:59:01.633606 WR_PRE = 0x1
7099 22:59:01.636723 WR_PST = 0x1
7100 22:59:01.636826 DBI_WR = 0x0
7101 22:59:01.639925 DBI_RD = 0x0
7102 22:59:01.640012 OTF = 0x1
7103 22:59:01.643606 ===================================
7104 22:59:01.646960 ===================================
7105 22:59:01.650135 ANA top config
7106 22:59:01.653229 ===================================
7107 22:59:01.653300 DLL_ASYNC_EN = 0
7108 22:59:01.656809 ALL_SLAVE_EN = 0
7109 22:59:01.659849 NEW_RANK_MODE = 1
7110 22:59:01.663521 DLL_IDLE_MODE = 1
7111 22:59:01.663601 LP45_APHY_COMB_EN = 1
7112 22:59:01.666728 TX_ODT_DIS = 0
7113 22:59:01.670120 NEW_8X_MODE = 1
7114 22:59:01.673415 ===================================
7115 22:59:01.676633 ===================================
7116 22:59:01.679853 data_rate = 3200
7117 22:59:01.683030 CKR = 1
7118 22:59:01.683117 DQ_P2S_RATIO = 8
7119 22:59:01.686836 ===================================
7120 22:59:01.689983 CA_P2S_RATIO = 8
7121 22:59:01.693294 DQ_CA_OPEN = 0
7122 22:59:01.696983 DQ_SEMI_OPEN = 0
7123 22:59:01.700090 CA_SEMI_OPEN = 0
7124 22:59:01.703099 CA_FULL_RATE = 0
7125 22:59:01.703182 DQ_CKDIV4_EN = 0
7126 22:59:01.706873 CA_CKDIV4_EN = 0
7127 22:59:01.709945 CA_PREDIV_EN = 0
7128 22:59:01.713605 PH8_DLY = 12
7129 22:59:01.716692 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7130 22:59:01.719907 DQ_AAMCK_DIV = 4
7131 22:59:01.720007 CA_AAMCK_DIV = 4
7132 22:59:01.723625 CA_ADMCK_DIV = 4
7133 22:59:01.726900 DQ_TRACK_CA_EN = 0
7134 22:59:01.730125 CA_PICK = 1600
7135 22:59:01.733517 CA_MCKIO = 1600
7136 22:59:01.736401 MCKIO_SEMI = 0
7137 22:59:01.740118 PLL_FREQ = 3068
7138 22:59:01.743332 DQ_UI_PI_RATIO = 32
7139 22:59:01.743429 CA_UI_PI_RATIO = 0
7140 22:59:01.746498 ===================================
7141 22:59:01.749618 ===================================
7142 22:59:01.752870 memory_type:LPDDR4
7143 22:59:01.756196 GP_NUM : 10
7144 22:59:01.756279 SRAM_EN : 1
7145 22:59:01.759886 MD32_EN : 0
7146 22:59:01.762968 ===================================
7147 22:59:01.765988 [ANA_INIT] >>>>>>>>>>>>>>
7148 22:59:01.769690 <<<<<< [CONFIGURE PHASE]: ANA_TX
7149 22:59:01.773054 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7150 22:59:01.776414 ===================================
7151 22:59:01.776535 data_rate = 3200,PCW = 0X7600
7152 22:59:01.779528 ===================================
7153 22:59:01.782763 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7154 22:59:01.789889 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7155 22:59:01.796283 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7156 22:59:01.799537 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7157 22:59:01.802858 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7158 22:59:01.806127 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7159 22:59:01.809907 [ANA_INIT] flow start
7160 22:59:01.809997 [ANA_INIT] PLL >>>>>>>>
7161 22:59:01.812969 [ANA_INIT] PLL <<<<<<<<
7162 22:59:01.816067 [ANA_INIT] MIDPI >>>>>>>>
7163 22:59:01.819737 [ANA_INIT] MIDPI <<<<<<<<
7164 22:59:01.819831 [ANA_INIT] DLL >>>>>>>>
7165 22:59:01.822850 [ANA_INIT] DLL <<<<<<<<
7166 22:59:01.822952 [ANA_INIT] flow end
7167 22:59:01.829617 ============ LP4 DIFF to SE enter ============
7168 22:59:01.833342 ============ LP4 DIFF to SE exit ============
7169 22:59:01.836613 [ANA_INIT] <<<<<<<<<<<<<
7170 22:59:01.839949 [Flow] Enable top DCM control >>>>>
7171 22:59:01.843276 [Flow] Enable top DCM control <<<<<
7172 22:59:01.843371 Enable DLL master slave shuffle
7173 22:59:01.849642 ==============================================================
7174 22:59:01.852686 Gating Mode config
7175 22:59:01.856089 ==============================================================
7176 22:59:01.859903 Config description:
7177 22:59:01.869473 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7178 22:59:01.876137 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7179 22:59:01.879355 SELPH_MODE 0: By rank 1: By Phase
7180 22:59:01.886431 ==============================================================
7181 22:59:01.889648 GAT_TRACK_EN = 1
7182 22:59:01.892848 RX_GATING_MODE = 2
7183 22:59:01.896023 RX_GATING_TRACK_MODE = 2
7184 22:59:01.899280 SELPH_MODE = 1
7185 22:59:01.899400 PICG_EARLY_EN = 1
7186 22:59:01.902633 VALID_LAT_VALUE = 1
7187 22:59:01.909186 ==============================================================
7188 22:59:01.912542 Enter into Gating configuration >>>>
7189 22:59:01.916188 Exit from Gating configuration <<<<
7190 22:59:01.919110 Enter into DVFS_PRE_config >>>>>
7191 22:59:01.929483 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7192 22:59:01.932512 Exit from DVFS_PRE_config <<<<<
7193 22:59:01.936112 Enter into PICG configuration >>>>
7194 22:59:01.939091 Exit from PICG configuration <<<<
7195 22:59:01.942470 [RX_INPUT] configuration >>>>>
7196 22:59:01.945948 [RX_INPUT] configuration <<<<<
7197 22:59:01.949100 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7198 22:59:01.955899 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7199 22:59:01.962798 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7200 22:59:01.969251 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7201 22:59:01.972618 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7202 22:59:01.979549 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7203 22:59:01.983132 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7204 22:59:01.989239 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7205 22:59:01.992539 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7206 22:59:01.995919 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7207 22:59:01.999091 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7208 22:59:02.006288 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7209 22:59:02.009506 ===================================
7210 22:59:02.012792 LPDDR4 DRAM CONFIGURATION
7211 22:59:02.016055 ===================================
7212 22:59:02.016128 EX_ROW_EN[0] = 0x0
7213 22:59:02.019313 EX_ROW_EN[1] = 0x0
7214 22:59:02.019421 LP4Y_EN = 0x0
7215 22:59:02.022527 WORK_FSP = 0x1
7216 22:59:02.022622 WL = 0x5
7217 22:59:02.025628 RL = 0x5
7218 22:59:02.025696 BL = 0x2
7219 22:59:02.029369 RPST = 0x0
7220 22:59:02.029442 RD_PRE = 0x0
7221 22:59:02.032540 WR_PRE = 0x1
7222 22:59:02.032622 WR_PST = 0x1
7223 22:59:02.036104 DBI_WR = 0x0
7224 22:59:02.036186 DBI_RD = 0x0
7225 22:59:02.039127 OTF = 0x1
7226 22:59:02.042778 ===================================
7227 22:59:02.045893 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7228 22:59:02.049021 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7229 22:59:02.055891 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7230 22:59:02.058929 ===================================
7231 22:59:02.059049 LPDDR4 DRAM CONFIGURATION
7232 22:59:02.062550 ===================================
7233 22:59:02.065731 EX_ROW_EN[0] = 0x10
7234 22:59:02.068894 EX_ROW_EN[1] = 0x0
7235 22:59:02.069002 LP4Y_EN = 0x0
7236 22:59:02.072709 WORK_FSP = 0x1
7237 22:59:02.072825 WL = 0x5
7238 22:59:02.075986 RL = 0x5
7239 22:59:02.076089 BL = 0x2
7240 22:59:02.079224 RPST = 0x0
7241 22:59:02.079365 RD_PRE = 0x0
7242 22:59:02.082334 WR_PRE = 0x1
7243 22:59:02.082409 WR_PST = 0x1
7244 22:59:02.086064 DBI_WR = 0x0
7245 22:59:02.086151 DBI_RD = 0x0
7246 22:59:02.089275 OTF = 0x1
7247 22:59:02.092766 ===================================
7248 22:59:02.098859 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7249 22:59:02.098946 ==
7250 22:59:02.102607 Dram Type= 6, Freq= 0, CH_0, rank 0
7251 22:59:02.105751 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7252 22:59:02.105830 ==
7253 22:59:02.108983 [Duty_Offset_Calibration]
7254 22:59:02.109068 B0:2 B1:1 CA:1
7255 22:59:02.109137
7256 22:59:02.112355 [DutyScan_Calibration_Flow] k_type=0
7257 22:59:02.122887
7258 22:59:02.122967 ==CLK 0==
7259 22:59:02.126113 Final CLK duty delay cell = 0
7260 22:59:02.129308 [0] MAX Duty = 5156%(X100), DQS PI = 22
7261 22:59:02.133052 [0] MIN Duty = 4907%(X100), DQS PI = 0
7262 22:59:02.133139 [0] AVG Duty = 5031%(X100)
7263 22:59:02.136089
7264 22:59:02.136174 CH0 CLK Duty spec in!! Max-Min= 249%
7265 22:59:02.142891 [DutyScan_Calibration_Flow] ====Done====
7266 22:59:02.142974
7267 22:59:02.145957 [DutyScan_Calibration_Flow] k_type=1
7268 22:59:02.161035
7269 22:59:02.161122 ==DQS 0 ==
7270 22:59:02.164245 Final DQS duty delay cell = -4
7271 22:59:02.167899 [-4] MAX Duty = 5156%(X100), DQS PI = 26
7272 22:59:02.171196 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7273 22:59:02.174241 [-4] AVG Duty = 4906%(X100)
7274 22:59:02.174349
7275 22:59:02.174418 ==DQS 1 ==
7276 22:59:02.178127 Final DQS duty delay cell = -4
7277 22:59:02.181273 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7278 22:59:02.184610 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7279 22:59:02.187817 [-4] AVG Duty = 4891%(X100)
7280 22:59:02.187892
7281 22:59:02.190919 CH0 DQS 0 Duty spec in!! Max-Min= 499%
7282 22:59:02.190997
7283 22:59:02.194633 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7284 22:59:02.197794 [DutyScan_Calibration_Flow] ====Done====
7285 22:59:02.197871
7286 22:59:02.200991 [DutyScan_Calibration_Flow] k_type=3
7287 22:59:02.218156
7288 22:59:02.218239 ==DQM 0 ==
7289 22:59:02.221419 Final DQM duty delay cell = 0
7290 22:59:02.224662 [0] MAX Duty = 5218%(X100), DQS PI = 34
7291 22:59:02.227918 [0] MIN Duty = 4907%(X100), DQS PI = 54
7292 22:59:02.231140 [0] AVG Duty = 5062%(X100)
7293 22:59:02.231213
7294 22:59:02.231277 ==DQM 1 ==
7295 22:59:02.234876 Final DQM duty delay cell = -4
7296 22:59:02.238108 [-4] MAX Duty = 5000%(X100), DQS PI = 24
7297 22:59:02.241312 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7298 22:59:02.244564 [-4] AVG Duty = 4922%(X100)
7299 22:59:02.244633
7300 22:59:02.248139 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7301 22:59:02.248207
7302 22:59:02.251139 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7303 22:59:02.254989 [DutyScan_Calibration_Flow] ====Done====
7304 22:59:02.255064
7305 22:59:02.258045 [DutyScan_Calibration_Flow] k_type=2
7306 22:59:02.275521
7307 22:59:02.275633 ==DQ 0 ==
7308 22:59:02.279112 Final DQ duty delay cell = 0
7309 22:59:02.282240 [0] MAX Duty = 5062%(X100), DQS PI = 24
7310 22:59:02.285449 [0] MIN Duty = 4907%(X100), DQS PI = 0
7311 22:59:02.285530 [0] AVG Duty = 4984%(X100)
7312 22:59:02.288790
7313 22:59:02.288862 ==DQ 1 ==
7314 22:59:02.292051 Final DQ duty delay cell = 0
7315 22:59:02.295356 [0] MAX Duty = 5156%(X100), DQS PI = 22
7316 22:59:02.299004 [0] MIN Duty = 4938%(X100), DQS PI = 34
7317 22:59:02.299081 [0] AVG Duty = 5047%(X100)
7318 22:59:02.299148
7319 22:59:02.302266 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7320 22:59:02.305417
7321 22:59:02.309087 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7322 22:59:02.312195 [DutyScan_Calibration_Flow] ====Done====
7323 22:59:02.312267 ==
7324 22:59:02.315893 Dram Type= 6, Freq= 0, CH_1, rank 0
7325 22:59:02.319220 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7326 22:59:02.319292 ==
7327 22:59:02.322381 [Duty_Offset_Calibration]
7328 22:59:02.322447 B0:1 B1:0 CA:0
7329 22:59:02.322511
7330 22:59:02.325647 [DutyScan_Calibration_Flow] k_type=0
7331 22:59:02.335454
7332 22:59:02.335529 ==CLK 0==
7333 22:59:02.338490 Final CLK duty delay cell = -4
7334 22:59:02.341671 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7335 22:59:02.344942 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7336 22:59:02.348144 [-4] AVG Duty = 4922%(X100)
7337 22:59:02.348218
7338 22:59:02.351908 CH1 CLK Duty spec in!! Max-Min= 156%
7339 22:59:02.355430 [DutyScan_Calibration_Flow] ====Done====
7340 22:59:02.355505
7341 22:59:02.358399 [DutyScan_Calibration_Flow] k_type=1
7342 22:59:02.375234
7343 22:59:02.375315 ==DQS 0 ==
7344 22:59:02.378411 Final DQS duty delay cell = 0
7345 22:59:02.381522 [0] MAX Duty = 5094%(X100), DQS PI = 18
7346 22:59:02.385177 [0] MIN Duty = 4844%(X100), DQS PI = 50
7347 22:59:02.388290 [0] AVG Duty = 4969%(X100)
7348 22:59:02.388364
7349 22:59:02.388426 ==DQS 1 ==
7350 22:59:02.391593 Final DQS duty delay cell = 0
7351 22:59:02.395530 [0] MAX Duty = 5249%(X100), DQS PI = 16
7352 22:59:02.398766 [0] MIN Duty = 4969%(X100), DQS PI = 6
7353 22:59:02.398840 [0] AVG Duty = 5109%(X100)
7354 22:59:02.401930
7355 22:59:02.405034 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7356 22:59:02.405106
7357 22:59:02.408297 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7358 22:59:02.411577 [DutyScan_Calibration_Flow] ====Done====
7359 22:59:02.411652
7360 22:59:02.415321 [DutyScan_Calibration_Flow] k_type=3
7361 22:59:02.431982
7362 22:59:02.432058 ==DQM 0 ==
7363 22:59:02.435102 Final DQM duty delay cell = 0
7364 22:59:02.438330 [0] MAX Duty = 5187%(X100), DQS PI = 8
7365 22:59:02.442013 [0] MIN Duty = 4969%(X100), DQS PI = 48
7366 22:59:02.442090 [0] AVG Duty = 5078%(X100)
7367 22:59:02.445184
7368 22:59:02.445253 ==DQM 1 ==
7369 22:59:02.448395 Final DQM duty delay cell = 0
7370 22:59:02.451837 [0] MAX Duty = 5062%(X100), DQS PI = 14
7371 22:59:02.455172 [0] MIN Duty = 4907%(X100), DQS PI = 52
7372 22:59:02.455247 [0] AVG Duty = 4984%(X100)
7373 22:59:02.458922
7374 22:59:02.462029 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7375 22:59:02.462113
7376 22:59:02.465583 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7377 22:59:02.468634 [DutyScan_Calibration_Flow] ====Done====
7378 22:59:02.468717
7379 22:59:02.471802 [DutyScan_Calibration_Flow] k_type=2
7380 22:59:02.488085
7381 22:59:02.488188 ==DQ 0 ==
7382 22:59:02.491285 Final DQ duty delay cell = -4
7383 22:59:02.494773 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7384 22:59:02.497970 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7385 22:59:02.501282 [-4] AVG Duty = 4968%(X100)
7386 22:59:02.501380
7387 22:59:02.501470 ==DQ 1 ==
7388 22:59:02.504459 Final DQ duty delay cell = 0
7389 22:59:02.508248 [0] MAX Duty = 5156%(X100), DQS PI = 18
7390 22:59:02.511358 [0] MIN Duty = 4938%(X100), DQS PI = 8
7391 22:59:02.511434 [0] AVG Duty = 5047%(X100)
7392 22:59:02.514598
7393 22:59:02.517754 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7394 22:59:02.517826
7395 22:59:02.521462 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7396 22:59:02.524805 [DutyScan_Calibration_Flow] ====Done====
7397 22:59:02.527939 nWR fixed to 30
7398 22:59:02.528028 [ModeRegInit_LP4] CH0 RK0
7399 22:59:02.531255 [ModeRegInit_LP4] CH0 RK1
7400 22:59:02.534597 [ModeRegInit_LP4] CH1 RK0
7401 22:59:02.537949 [ModeRegInit_LP4] CH1 RK1
7402 22:59:02.538034 match AC timing 5
7403 22:59:02.541800 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7404 22:59:02.548143 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7405 22:59:02.551332 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7406 22:59:02.557996 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7407 22:59:02.561402 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7408 22:59:02.561487 [MiockJmeterHQA]
7409 22:59:02.561572
7410 22:59:02.564493 [DramcMiockJmeter] u1RxGatingPI = 0
7411 22:59:02.567636 0 : 4363, 4138
7412 22:59:02.567723 4 : 4252, 4027
7413 22:59:02.571620 8 : 4365, 4140
7414 22:59:02.571706 12 : 4253, 4027
7415 22:59:02.571795 16 : 4255, 4031
7416 22:59:02.574419 20 : 4363, 4137
7417 22:59:02.574505 24 : 4252, 4027
7418 22:59:02.577724 28 : 4360, 4138
7419 22:59:02.577810 32 : 4252, 4027
7420 22:59:02.580980 36 : 4250, 4027
7421 22:59:02.581067 40 : 4250, 4027
7422 22:59:02.584563 44 : 4250, 4026
7423 22:59:02.584650 48 : 4363, 4140
7424 22:59:02.584755 52 : 4363, 4140
7425 22:59:02.587744 56 : 4250, 4027
7426 22:59:02.587831 60 : 4250, 4027
7427 22:59:02.590843 64 : 4363, 4140
7428 22:59:02.590943 68 : 4250, 4027
7429 22:59:02.594135 72 : 4361, 4137
7430 22:59:02.594237 76 : 4250, 4026
7431 22:59:02.594356 80 : 4250, 4027
7432 22:59:02.597818 84 : 4249, 4027
7433 22:59:02.597905 88 : 4253, 341
7434 22:59:02.601035 92 : 4363, 0
7435 22:59:02.601122 96 : 4253, 0
7436 22:59:02.601209 100 : 4363, 0
7437 22:59:02.604116 104 : 4253, 0
7438 22:59:02.604203 108 : 4249, 0
7439 22:59:02.607667 112 : 4254, 0
7440 22:59:02.607753 116 : 4253, 0
7441 22:59:02.607839 120 : 4250, 0
7442 22:59:02.610950 124 : 4249, 0
7443 22:59:02.611052 128 : 4253, 0
7444 22:59:02.614119 132 : 4361, 0
7445 22:59:02.614206 136 : 4250, 0
7446 22:59:02.614292 140 : 4250, 0
7447 22:59:02.617471 144 : 4252, 0
7448 22:59:02.617557 148 : 4363, 0
7449 22:59:02.620673 152 : 4250, 0
7450 22:59:02.620760 156 : 4255, 0
7451 22:59:02.620847 160 : 4250, 0
7452 22:59:02.624681 164 : 4363, 0
7453 22:59:02.624768 168 : 4250, 0
7454 22:59:02.624854 172 : 4250, 0
7455 22:59:02.627877 176 : 4250, 0
7456 22:59:02.627963 180 : 4253, 0
7457 22:59:02.630926 184 : 4361, 0
7458 22:59:02.631016 188 : 4361, 0
7459 22:59:02.631102 192 : 4363, 0
7460 22:59:02.634504 196 : 4255, 0
7461 22:59:02.634590 200 : 4361, 0
7462 22:59:02.637880 204 : 4250, 1250
7463 22:59:02.637967 208 : 4363, 4123
7464 22:59:02.641109 212 : 4361, 4137
7465 22:59:02.641195 216 : 4250, 4027
7466 22:59:02.644358 220 : 4250, 4027
7467 22:59:02.644445 224 : 4252, 4030
7468 22:59:02.644531 228 : 4249, 4027
7469 22:59:02.647601 232 : 4252, 4029
7470 22:59:02.647687 236 : 4252, 4029
7471 22:59:02.650729 240 : 4252, 4030
7472 22:59:02.650829 244 : 4363, 4140
7473 22:59:02.654020 248 : 4253, 4026
7474 22:59:02.654107 252 : 4250, 4027
7475 22:59:02.657885 256 : 4249, 4027
7476 22:59:02.657971 260 : 4363, 4140
7477 22:59:02.661141 264 : 4360, 4137
7478 22:59:02.661227 268 : 4250, 4027
7479 22:59:02.663895 272 : 4363, 4140
7480 22:59:02.663982 276 : 4252, 4030
7481 22:59:02.667219 280 : 4249, 4027
7482 22:59:02.667307 284 : 4253, 4029
7483 22:59:02.667415 288 : 4250, 4026
7484 22:59:02.670456 292 : 4252, 4030
7485 22:59:02.670558 296 : 4363, 4140
7486 22:59:02.674261 300 : 4255, 4029
7487 22:59:02.674378 304 : 4252, 4029
7488 22:59:02.677522 308 : 4250, 3998
7489 22:59:02.677608 312 : 4363, 2068
7490 22:59:02.677694
7491 22:59:02.680753 MIOCK jitter meter ch=0
7492 22:59:02.680839
7493 22:59:02.684127 1T = (312-88) = 224 dly cells
7494 22:59:02.690847 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7495 22:59:02.690961 ==
7496 22:59:02.694082 Dram Type= 6, Freq= 0, CH_0, rank 0
7497 22:59:02.697784 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7498 22:59:02.697871 ==
7499 22:59:02.704071 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7500 22:59:02.707158 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7501 22:59:02.711020 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7502 22:59:02.717119 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7503 22:59:02.725597 [CA 0] Center 42 (12~73) winsize 62
7504 22:59:02.728844 [CA 1] Center 43 (12~74) winsize 63
7505 22:59:02.732172 [CA 2] Center 37 (8~67) winsize 60
7506 22:59:02.735972 [CA 3] Center 37 (7~67) winsize 61
7507 22:59:02.738850 [CA 4] Center 36 (6~66) winsize 61
7508 22:59:02.742471 [CA 5] Center 35 (6~64) winsize 59
7509 22:59:02.742556
7510 22:59:02.745677 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7511 22:59:02.745764
7512 22:59:02.749037 [CATrainingPosCal] consider 1 rank data
7513 22:59:02.752428 u2DelayCellTimex100 = 290/100 ps
7514 22:59:02.755594 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7515 22:59:02.762654 CA1 delay=43 (12~74),Diff = 8 PI (26 cell)
7516 22:59:02.765342 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7517 22:59:02.768637 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7518 22:59:02.772587 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7519 22:59:02.775761 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7520 22:59:02.775846
7521 22:59:02.778957 CA PerBit enable=1, Macro0, CA PI delay=35
7522 22:59:02.779062
7523 22:59:02.782144 [CBTSetCACLKResult] CA Dly = 35
7524 22:59:02.785433 CS Dly: 9 (0~40)
7525 22:59:02.788593 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7526 22:59:02.792461 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7527 22:59:02.792547 ==
7528 22:59:02.795269 Dram Type= 6, Freq= 0, CH_0, rank 1
7529 22:59:02.798902 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7530 22:59:02.802299 ==
7531 22:59:02.805293 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7532 22:59:02.808850 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7533 22:59:02.815453 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7534 22:59:02.818394 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7535 22:59:02.828910 [CA 0] Center 43 (13~73) winsize 61
7536 22:59:02.832160 [CA 1] Center 43 (13~73) winsize 61
7537 22:59:02.835508 [CA 2] Center 38 (8~68) winsize 61
7538 22:59:02.839258 [CA 3] Center 38 (8~68) winsize 61
7539 22:59:02.842495 [CA 4] Center 36 (6~66) winsize 61
7540 22:59:02.845547 [CA 5] Center 35 (6~65) winsize 60
7541 22:59:02.845633
7542 22:59:02.849296 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7543 22:59:02.849413
7544 22:59:02.852183 [CATrainingPosCal] consider 2 rank data
7545 22:59:02.855542 u2DelayCellTimex100 = 290/100 ps
7546 22:59:02.858637 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7547 22:59:02.865639 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7548 22:59:02.868983 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7549 22:59:02.872258 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7550 22:59:02.875551 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7551 22:59:02.878835 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7552 22:59:02.878907
7553 22:59:02.882101 CA PerBit enable=1, Macro0, CA PI delay=35
7554 22:59:02.882196
7555 22:59:02.885817 [CBTSetCACLKResult] CA Dly = 35
7556 22:59:02.885897 CS Dly: 10 (0~42)
7557 22:59:02.892444 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7558 22:59:02.895506 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7559 22:59:02.895589
7560 22:59:02.898708 ----->DramcWriteLeveling(PI) begin...
7561 22:59:02.898808 ==
7562 22:59:02.902538 Dram Type= 6, Freq= 0, CH_0, rank 0
7563 22:59:02.905505 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7564 22:59:02.905587 ==
7565 22:59:02.908584 Write leveling (Byte 0): 34 => 34
7566 22:59:02.912400 Write leveling (Byte 1): 28 => 28
7567 22:59:02.915213 DramcWriteLeveling(PI) end<-----
7568 22:59:02.915317
7569 22:59:02.915477 ==
7570 22:59:02.918678 Dram Type= 6, Freq= 0, CH_0, rank 0
7571 22:59:02.925579 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7572 22:59:02.925665 ==
7573 22:59:02.925732 [Gating] SW mode calibration
7574 22:59:02.935139 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7575 22:59:02.938451 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7576 22:59:02.941740 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7577 22:59:02.948869 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7578 22:59:02.952501 1 4 8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
7579 22:59:02.955068 1 4 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (1 1)
7580 22:59:02.961762 1 4 16 | B1->B0 | 2626 3434 | 1 1 | (1 1) (1 1)
7581 22:59:02.964943 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7582 22:59:02.971347 1 4 24 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7583 22:59:02.974625 1 4 28 | B1->B0 | 3434 3636 | 1 1 | (1 1) (0 0)
7584 22:59:02.978593 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7585 22:59:02.981920 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7586 22:59:02.988269 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
7587 22:59:02.991711 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
7588 22:59:02.994961 1 5 16 | B1->B0 | 3333 2726 | 0 1 | (1 0) (0 0)
7589 22:59:03.001572 1 5 20 | B1->B0 | 2b2b 2424 | 0 0 | (1 0) (0 0)
7590 22:59:03.004633 1 5 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
7591 22:59:03.008361 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7592 22:59:03.014974 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 22:59:03.017916 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7594 22:59:03.021559 1 6 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
7595 22:59:03.028257 1 6 12 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
7596 22:59:03.031287 1 6 16 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
7597 22:59:03.035039 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7598 22:59:03.041235 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7599 22:59:03.044335 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7600 22:59:03.048110 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7601 22:59:03.054497 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7602 22:59:03.058294 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7603 22:59:03.060987 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7604 22:59:03.067811 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7605 22:59:03.071397 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7606 22:59:03.074667 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 22:59:03.081124 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 22:59:03.084523 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 22:59:03.087805 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 22:59:03.094320 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 22:59:03.097686 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 22:59:03.100995 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 22:59:03.107582 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 22:59:03.111287 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 22:59:03.114674 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 22:59:03.121026 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 22:59:03.124253 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 22:59:03.127257 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7619 22:59:03.130999 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7620 22:59:03.137629 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7621 22:59:03.141238 Total UI for P1: 0, mck2ui 16
7622 22:59:03.144325 best dqsien dly found for B0: ( 1, 9, 10)
7623 22:59:03.147469 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7624 22:59:03.151068 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7625 22:59:03.157468 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7626 22:59:03.157546 Total UI for P1: 0, mck2ui 16
7627 22:59:03.164290 best dqsien dly found for B1: ( 1, 9, 20)
7628 22:59:03.167638 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7629 22:59:03.170861 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7630 22:59:03.170942
7631 22:59:03.174511 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7632 22:59:03.177488 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7633 22:59:03.180693 [Gating] SW calibration Done
7634 22:59:03.180770 ==
7635 22:59:03.184630 Dram Type= 6, Freq= 0, CH_0, rank 0
7636 22:59:03.187365 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7637 22:59:03.187459 ==
7638 22:59:03.191263 RX Vref Scan: 0
7639 22:59:03.191360
7640 22:59:03.191438 RX Vref 0 -> 0, step: 1
7641 22:59:03.194443
7642 22:59:03.194517 RX Delay 0 -> 252, step: 8
7643 22:59:03.197566 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7644 22:59:03.204054 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7645 22:59:03.207287 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7646 22:59:03.210546 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7647 22:59:03.214337 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7648 22:59:03.217548 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7649 22:59:03.224262 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7650 22:59:03.227610 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7651 22:59:03.230874 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7652 22:59:03.234054 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7653 22:59:03.237115 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7654 22:59:03.243902 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7655 22:59:03.247403 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7656 22:59:03.250891 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7657 22:59:03.253907 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7658 22:59:03.257109 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7659 22:59:03.260418 ==
7660 22:59:03.264291 Dram Type= 6, Freq= 0, CH_0, rank 0
7661 22:59:03.267107 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7662 22:59:03.267181 ==
7663 22:59:03.267244 DQS Delay:
7664 22:59:03.270278 DQS0 = 0, DQS1 = 0
7665 22:59:03.270349 DQM Delay:
7666 22:59:03.274202 DQM0 = 137, DQM1 = 129
7667 22:59:03.274274 DQ Delay:
7668 22:59:03.277443 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7669 22:59:03.280512 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7670 22:59:03.283699 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7671 22:59:03.287516 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7672 22:59:03.287596
7673 22:59:03.287661
7674 22:59:03.287723 ==
7675 22:59:03.290762 Dram Type= 6, Freq= 0, CH_0, rank 0
7676 22:59:03.297263 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7677 22:59:03.297339 ==
7678 22:59:03.297403
7679 22:59:03.297462
7680 22:59:03.297523 TX Vref Scan disable
7681 22:59:03.301177 == TX Byte 0 ==
7682 22:59:03.304338 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7683 22:59:03.307675 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7684 22:59:03.310986 == TX Byte 1 ==
7685 22:59:03.314264 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7686 22:59:03.321190 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7687 22:59:03.321270 ==
7688 22:59:03.324466 Dram Type= 6, Freq= 0, CH_0, rank 0
7689 22:59:03.327710 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7690 22:59:03.327787 ==
7691 22:59:03.340449
7692 22:59:03.343498 TX Vref early break, caculate TX vref
7693 22:59:03.346730 TX Vref=16, minBit 0, minWin=23, winSum=379
7694 22:59:03.350453 TX Vref=18, minBit 7, minWin=23, winSum=389
7695 22:59:03.353525 TX Vref=20, minBit 0, minWin=24, winSum=400
7696 22:59:03.357180 TX Vref=22, minBit 3, minWin=25, winSum=414
7697 22:59:03.360642 TX Vref=24, minBit 7, minWin=25, winSum=422
7698 22:59:03.363788 TX Vref=26, minBit 1, minWin=25, winSum=422
7699 22:59:03.370414 TX Vref=28, minBit 0, minWin=25, winSum=421
7700 22:59:03.373526 TX Vref=30, minBit 8, minWin=24, winSum=414
7701 22:59:03.377241 TX Vref=32, minBit 6, minWin=24, winSum=405
7702 22:59:03.380458 TX Vref=34, minBit 6, minWin=23, winSum=393
7703 22:59:03.386919 [TxChooseVref] Worse bit 7, Min win 25, Win sum 422, Final Vref 24
7704 22:59:03.387006
7705 22:59:03.390128 Final TX Range 0 Vref 24
7706 22:59:03.390212
7707 22:59:03.390279 ==
7708 22:59:03.393720 Dram Type= 6, Freq= 0, CH_0, rank 0
7709 22:59:03.396756 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7710 22:59:03.396866 ==
7711 22:59:03.396960
7712 22:59:03.397052
7713 22:59:03.400031 TX Vref Scan disable
7714 22:59:03.407138 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7715 22:59:03.407215 == TX Byte 0 ==
7716 22:59:03.409807 u2DelayCellOfst[0]=10 cells (3 PI)
7717 22:59:03.413664 u2DelayCellOfst[1]=13 cells (4 PI)
7718 22:59:03.416990 u2DelayCellOfst[2]=10 cells (3 PI)
7719 22:59:03.420129 u2DelayCellOfst[3]=10 cells (3 PI)
7720 22:59:03.423319 u2DelayCellOfst[4]=6 cells (2 PI)
7721 22:59:03.426659 u2DelayCellOfst[5]=0 cells (0 PI)
7722 22:59:03.429939 u2DelayCellOfst[6]=16 cells (5 PI)
7723 22:59:03.433317 u2DelayCellOfst[7]=13 cells (4 PI)
7724 22:59:03.436618 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7725 22:59:03.439961 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7726 22:59:03.443014 == TX Byte 1 ==
7727 22:59:03.443096 u2DelayCellOfst[8]=0 cells (0 PI)
7728 22:59:03.446731 u2DelayCellOfst[9]=0 cells (0 PI)
7729 22:59:03.449932 u2DelayCellOfst[10]=10 cells (3 PI)
7730 22:59:03.453231 u2DelayCellOfst[11]=3 cells (1 PI)
7731 22:59:03.456403 u2DelayCellOfst[12]=13 cells (4 PI)
7732 22:59:03.460246 u2DelayCellOfst[13]=13 cells (4 PI)
7733 22:59:03.463412 u2DelayCellOfst[14]=16 cells (5 PI)
7734 22:59:03.466281 u2DelayCellOfst[15]=13 cells (4 PI)
7735 22:59:03.469970 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7736 22:59:03.476338 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7737 22:59:03.476446 DramC Write-DBI on
7738 22:59:03.476555 ==
7739 22:59:03.479886 Dram Type= 6, Freq= 0, CH_0, rank 0
7740 22:59:03.482987 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7741 22:59:03.483092 ==
7742 22:59:03.486878
7743 22:59:03.486978
7744 22:59:03.487109 TX Vref Scan disable
7745 22:59:03.490019 == TX Byte 0 ==
7746 22:59:03.493257 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7747 22:59:03.496411 == TX Byte 1 ==
7748 22:59:03.499644 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7749 22:59:03.503061 DramC Write-DBI off
7750 22:59:03.503162
7751 22:59:03.503260 [DATLAT]
7752 22:59:03.503386 Freq=1600, CH0 RK0
7753 22:59:03.503478
7754 22:59:03.506238 DATLAT Default: 0xf
7755 22:59:03.506348 0, 0xFFFF, sum = 0
7756 22:59:03.509825 1, 0xFFFF, sum = 0
7757 22:59:03.512939 2, 0xFFFF, sum = 0
7758 22:59:03.513020 3, 0xFFFF, sum = 0
7759 22:59:03.516225 4, 0xFFFF, sum = 0
7760 22:59:03.516328 5, 0xFFFF, sum = 0
7761 22:59:03.519583 6, 0xFFFF, sum = 0
7762 22:59:03.519659 7, 0xFFFF, sum = 0
7763 22:59:03.522962 8, 0xFFFF, sum = 0
7764 22:59:03.523064 9, 0xFFFF, sum = 0
7765 22:59:03.526058 10, 0xFFFF, sum = 0
7766 22:59:03.526161 11, 0xFFFF, sum = 0
7767 22:59:03.529327 12, 0xFFFF, sum = 0
7768 22:59:03.529431 13, 0xFFFF, sum = 0
7769 22:59:03.533191 14, 0x0, sum = 1
7770 22:59:03.533296 15, 0x0, sum = 2
7771 22:59:03.536616 16, 0x0, sum = 3
7772 22:59:03.536721 17, 0x0, sum = 4
7773 22:59:03.539985 best_step = 15
7774 22:59:03.540068
7775 22:59:03.540134 ==
7776 22:59:03.543474 Dram Type= 6, Freq= 0, CH_0, rank 0
7777 22:59:03.546421 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7778 22:59:03.546505 ==
7779 22:59:03.546571 RX Vref Scan: 1
7780 22:59:03.549522
7781 22:59:03.549605 Set Vref Range= 24 -> 127
7782 22:59:03.549670
7783 22:59:03.552784 RX Vref 24 -> 127, step: 1
7784 22:59:03.552867
7785 22:59:03.556676 RX Delay 19 -> 252, step: 4
7786 22:59:03.556759
7787 22:59:03.559862 Set Vref, RX VrefLevel [Byte0]: 24
7788 22:59:03.562879 [Byte1]: 24
7789 22:59:03.562961
7790 22:59:03.566674 Set Vref, RX VrefLevel [Byte0]: 25
7791 22:59:03.569771 [Byte1]: 25
7792 22:59:03.569854
7793 22:59:03.573374 Set Vref, RX VrefLevel [Byte0]: 26
7794 22:59:03.576235 [Byte1]: 26
7795 22:59:03.580086
7796 22:59:03.580173 Set Vref, RX VrefLevel [Byte0]: 27
7797 22:59:03.583831 [Byte1]: 27
7798 22:59:03.587553
7799 22:59:03.587636 Set Vref, RX VrefLevel [Byte0]: 28
7800 22:59:03.590764 [Byte1]: 28
7801 22:59:03.595257
7802 22:59:03.595401 Set Vref, RX VrefLevel [Byte0]: 29
7803 22:59:03.598455 [Byte1]: 29
7804 22:59:03.602840
7805 22:59:03.602923 Set Vref, RX VrefLevel [Byte0]: 30
7806 22:59:03.605977 [Byte1]: 30
7807 22:59:03.610366
7808 22:59:03.610448 Set Vref, RX VrefLevel [Byte0]: 31
7809 22:59:03.613445 [Byte1]: 31
7810 22:59:03.617717
7811 22:59:03.617800 Set Vref, RX VrefLevel [Byte0]: 32
7812 22:59:03.621580 [Byte1]: 32
7813 22:59:03.625562
7814 22:59:03.625666 Set Vref, RX VrefLevel [Byte0]: 33
7815 22:59:03.628696 [Byte1]: 33
7816 22:59:03.633252
7817 22:59:03.633368 Set Vref, RX VrefLevel [Byte0]: 34
7818 22:59:03.636681 [Byte1]: 34
7819 22:59:03.640595
7820 22:59:03.640695 Set Vref, RX VrefLevel [Byte0]: 35
7821 22:59:03.643907 [Byte1]: 35
7822 22:59:03.648389
7823 22:59:03.648488 Set Vref, RX VrefLevel [Byte0]: 36
7824 22:59:03.651395 [Byte1]: 36
7825 22:59:03.655781
7826 22:59:03.655864 Set Vref, RX VrefLevel [Byte0]: 37
7827 22:59:03.659088 [Byte1]: 37
7828 22:59:03.663695
7829 22:59:03.663777 Set Vref, RX VrefLevel [Byte0]: 38
7830 22:59:03.666868 [Byte1]: 38
7831 22:59:03.671117
7832 22:59:03.671200 Set Vref, RX VrefLevel [Byte0]: 39
7833 22:59:03.674208 [Byte1]: 39
7834 22:59:03.678506
7835 22:59:03.678589 Set Vref, RX VrefLevel [Byte0]: 40
7836 22:59:03.681685 [Byte1]: 40
7837 22:59:03.686067
7838 22:59:03.686150 Set Vref, RX VrefLevel [Byte0]: 41
7839 22:59:03.689258 [Byte1]: 41
7840 22:59:03.693934
7841 22:59:03.694016 Set Vref, RX VrefLevel [Byte0]: 42
7842 22:59:03.697011 [Byte1]: 42
7843 22:59:03.701074
7844 22:59:03.701157 Set Vref, RX VrefLevel [Byte0]: 43
7845 22:59:03.704854 [Byte1]: 43
7846 22:59:03.708852
7847 22:59:03.708934 Set Vref, RX VrefLevel [Byte0]: 44
7848 22:59:03.712003 [Byte1]: 44
7849 22:59:03.716488
7850 22:59:03.716571 Set Vref, RX VrefLevel [Byte0]: 45
7851 22:59:03.719466 [Byte1]: 45
7852 22:59:03.724233
7853 22:59:03.724319 Set Vref, RX VrefLevel [Byte0]: 46
7854 22:59:03.727538 [Byte1]: 46
7855 22:59:03.731362
7856 22:59:03.731437 Set Vref, RX VrefLevel [Byte0]: 47
7857 22:59:03.734645 [Byte1]: 47
7858 22:59:03.739248
7859 22:59:03.739364 Set Vref, RX VrefLevel [Byte0]: 48
7860 22:59:03.742566 [Byte1]: 48
7861 22:59:03.746481
7862 22:59:03.746564 Set Vref, RX VrefLevel [Byte0]: 49
7863 22:59:03.749791 [Byte1]: 49
7864 22:59:03.754350
7865 22:59:03.754463 Set Vref, RX VrefLevel [Byte0]: 50
7866 22:59:03.757444 [Byte1]: 50
7867 22:59:03.762040
7868 22:59:03.762123 Set Vref, RX VrefLevel [Byte0]: 51
7869 22:59:03.765295 [Byte1]: 51
7870 22:59:03.769149
7871 22:59:03.769233 Set Vref, RX VrefLevel [Byte0]: 52
7872 22:59:03.772554 [Byte1]: 52
7873 22:59:03.776825
7874 22:59:03.776908 Set Vref, RX VrefLevel [Byte0]: 53
7875 22:59:03.780624 [Byte1]: 53
7876 22:59:03.784428
7877 22:59:03.784512 Set Vref, RX VrefLevel [Byte0]: 54
7878 22:59:03.787698 [Byte1]: 54
7879 22:59:03.792247
7880 22:59:03.792360 Set Vref, RX VrefLevel [Byte0]: 55
7881 22:59:03.795441 [Byte1]: 55
7882 22:59:03.799730
7883 22:59:03.799807 Set Vref, RX VrefLevel [Byte0]: 56
7884 22:59:03.803241 [Byte1]: 56
7885 22:59:03.807196
7886 22:59:03.807278 Set Vref, RX VrefLevel [Byte0]: 57
7887 22:59:03.810883 [Byte1]: 57
7888 22:59:03.814699
7889 22:59:03.814788 Set Vref, RX VrefLevel [Byte0]: 58
7890 22:59:03.817974 [Byte1]: 58
7891 22:59:03.822503
7892 22:59:03.822612 Set Vref, RX VrefLevel [Byte0]: 59
7893 22:59:03.825539 [Byte1]: 59
7894 22:59:03.829780
7895 22:59:03.829855 Set Vref, RX VrefLevel [Byte0]: 60
7896 22:59:03.833541 [Byte1]: 60
7897 22:59:03.837413
7898 22:59:03.837483 Set Vref, RX VrefLevel [Byte0]: 61
7899 22:59:03.840764 [Byte1]: 61
7900 22:59:03.845254
7901 22:59:03.845325 Set Vref, RX VrefLevel [Byte0]: 62
7902 22:59:03.848595 [Byte1]: 62
7903 22:59:03.852486
7904 22:59:03.852556 Set Vref, RX VrefLevel [Byte0]: 63
7905 22:59:03.856341 [Byte1]: 63
7906 22:59:03.860092
7907 22:59:03.860164 Set Vref, RX VrefLevel [Byte0]: 64
7908 22:59:03.864040 [Byte1]: 64
7909 22:59:03.867910
7910 22:59:03.867980 Set Vref, RX VrefLevel [Byte0]: 65
7911 22:59:03.871241 [Byte1]: 65
7912 22:59:03.875281
7913 22:59:03.875413 Set Vref, RX VrefLevel [Byte0]: 66
7914 22:59:03.878642 [Byte1]: 66
7915 22:59:03.882943
7916 22:59:03.883050 Set Vref, RX VrefLevel [Byte0]: 67
7917 22:59:03.886551 [Byte1]: 67
7918 22:59:03.890764
7919 22:59:03.890849 Set Vref, RX VrefLevel [Byte0]: 68
7920 22:59:03.893861 [Byte1]: 68
7921 22:59:03.898254
7922 22:59:03.898337 Set Vref, RX VrefLevel [Byte0]: 69
7923 22:59:03.901593 [Byte1]: 69
7924 22:59:03.905971
7925 22:59:03.906057 Set Vref, RX VrefLevel [Byte0]: 70
7926 22:59:03.909058 [Byte1]: 70
7927 22:59:03.913252
7928 22:59:03.913336 Set Vref, RX VrefLevel [Byte0]: 71
7929 22:59:03.916344 [Byte1]: 71
7930 22:59:03.920968
7931 22:59:03.921052 Set Vref, RX VrefLevel [Byte0]: 72
7932 22:59:03.924157 [Byte1]: 72
7933 22:59:03.928766
7934 22:59:03.928849 Set Vref, RX VrefLevel [Byte0]: 73
7935 22:59:03.932018 [Byte1]: 73
7936 22:59:03.936200
7937 22:59:03.936284 Set Vref, RX VrefLevel [Byte0]: 74
7938 22:59:03.939670 [Byte1]: 74
7939 22:59:03.943828
7940 22:59:03.943925 Set Vref, RX VrefLevel [Byte0]: 75
7941 22:59:03.946844 [Byte1]: 75
7942 22:59:03.950765
7943 22:59:03.954049 Final RX Vref Byte 0 = 54 to rank0
7944 22:59:03.954133 Final RX Vref Byte 1 = 57 to rank0
7945 22:59:03.957460 Final RX Vref Byte 0 = 54 to rank1
7946 22:59:03.961312 Final RX Vref Byte 1 = 57 to rank1==
7947 22:59:03.964691 Dram Type= 6, Freq= 0, CH_0, rank 0
7948 22:59:03.971002 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7949 22:59:03.971086 ==
7950 22:59:03.971153 DQS Delay:
7951 22:59:03.971214 DQS0 = 0, DQS1 = 0
7952 22:59:03.974321 DQM Delay:
7953 22:59:03.974390 DQM0 = 133, DQM1 = 127
7954 22:59:03.977496 DQ Delay:
7955 22:59:03.980681 DQ0 =134, DQ1 =136, DQ2 =132, DQ3 =130
7956 22:59:03.984551 DQ4 =132, DQ5 =122, DQ6 =142, DQ7 =138
7957 22:59:03.987792 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7958 22:59:03.991005 DQ12 =132, DQ13 =130, DQ14 =138, DQ15 =134
7959 22:59:03.991088
7960 22:59:03.991155
7961 22:59:03.991216
7962 22:59:03.993987 [DramC_TX_OE_Calibration] TA2
7963 22:59:03.997551 Original DQ_B0 (3 6) =30, OEN = 27
7964 22:59:04.001014 Original DQ_B1 (3 6) =30, OEN = 27
7965 22:59:04.003916 24, 0x0, End_B0=24 End_B1=24
7966 22:59:04.003996 25, 0x0, End_B0=25 End_B1=25
7967 22:59:04.007806 26, 0x0, End_B0=26 End_B1=26
7968 22:59:04.010863 27, 0x0, End_B0=27 End_B1=27
7969 22:59:04.014253 28, 0x0, End_B0=28 End_B1=28
7970 22:59:04.017307 29, 0x0, End_B0=29 End_B1=29
7971 22:59:04.017419 30, 0x0, End_B0=30 End_B1=30
7972 22:59:04.020472 31, 0x4141, End_B0=30 End_B1=30
7973 22:59:04.024075 Byte0 end_step=30 best_step=27
7974 22:59:04.027788 Byte1 end_step=30 best_step=27
7975 22:59:04.030498 Byte0 TX OE(2T, 0.5T) = (3, 3)
7976 22:59:04.033757 Byte1 TX OE(2T, 0.5T) = (3, 3)
7977 22:59:04.033858
7978 22:59:04.033951
7979 22:59:04.040918 [DQSOSCAuto] RK0, (LSB)MR18= 0x2521, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
7980 22:59:04.044030 CH0 RK0: MR19=303, MR18=2521
7981 22:59:04.050795 CH0_RK0: MR19=0x303, MR18=0x2521, DQSOSC=391, MR23=63, INC=24, DEC=16
7982 22:59:04.050900
7983 22:59:04.054356 ----->DramcWriteLeveling(PI) begin...
7984 22:59:04.054457 ==
7985 22:59:04.057528 Dram Type= 6, Freq= 0, CH_0, rank 1
7986 22:59:04.060609 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7987 22:59:04.060689 ==
7988 22:59:04.063990 Write leveling (Byte 0): 36 => 36
7989 22:59:04.067205 Write leveling (Byte 1): 26 => 26
7990 22:59:04.070468 DramcWriteLeveling(PI) end<-----
7991 22:59:04.070566
7992 22:59:04.070656 ==
7993 22:59:04.074328 Dram Type= 6, Freq= 0, CH_0, rank 1
7994 22:59:04.077610 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7995 22:59:04.077708 ==
7996 22:59:04.080852 [Gating] SW mode calibration
7997 22:59:04.087555 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7998 22:59:04.093864 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7999 22:59:04.097223 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8000 22:59:04.100472 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8001 22:59:04.107200 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8002 22:59:04.110637 1 4 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8003 22:59:04.113645 1 4 16 | B1->B0 | 3232 3636 | 1 1 | (0 0) (1 1)
8004 22:59:04.120379 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8005 22:59:04.123685 1 4 24 | B1->B0 | 3434 3838 | 1 0 | (1 1) (0 0)
8006 22:59:04.126865 1 4 28 | B1->B0 | 3434 3534 | 1 1 | (1 1) (1 1)
8007 22:59:04.133792 1 5 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8008 22:59:04.136947 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8009 22:59:04.140200 1 5 8 | B1->B0 | 3434 3535 | 1 0 | (1 0) (1 0)
8010 22:59:04.146708 1 5 12 | B1->B0 | 3434 3535 | 1 0 | (1 0) (0 1)
8011 22:59:04.150612 1 5 16 | B1->B0 | 3131 2525 | 1 0 | (1 0) (1 0)
8012 22:59:04.153917 1 5 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8013 22:59:04.160115 1 5 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8014 22:59:04.163576 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8015 22:59:04.167323 1 6 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8016 22:59:04.173789 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8017 22:59:04.176872 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8018 22:59:04.180266 1 6 12 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
8019 22:59:04.186601 1 6 16 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
8020 22:59:04.189924 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8021 22:59:04.193365 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8022 22:59:04.200468 1 6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8023 22:59:04.203655 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8024 22:59:04.206940 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8025 22:59:04.213263 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8026 22:59:04.216356 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8027 22:59:04.219989 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8028 22:59:04.226512 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 22:59:04.229692 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 22:59:04.233473 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 22:59:04.236617 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 22:59:04.243517 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 22:59:04.246674 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 22:59:04.249819 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 22:59:04.256299 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 22:59:04.259510 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 22:59:04.263406 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 22:59:04.269542 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 22:59:04.273243 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 22:59:04.276269 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 22:59:04.283383 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8042 22:59:04.286624 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8043 22:59:04.289914 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8044 22:59:04.296593 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8045 22:59:04.296698 Total UI for P1: 0, mck2ui 16
8046 22:59:04.303045 best dqsien dly found for B0: ( 1, 9, 12)
8047 22:59:04.303159 Total UI for P1: 0, mck2ui 16
8048 22:59:04.309599 best dqsien dly found for B1: ( 1, 9, 12)
8049 22:59:04.312928 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8050 22:59:04.316698 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8051 22:59:04.316795
8052 22:59:04.319831 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8053 22:59:04.322940 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8054 22:59:04.326595 [Gating] SW calibration Done
8055 22:59:04.326690 ==
8056 22:59:04.329695 Dram Type= 6, Freq= 0, CH_0, rank 1
8057 22:59:04.333341 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8058 22:59:04.333439 ==
8059 22:59:04.336341 RX Vref Scan: 0
8060 22:59:04.336437
8061 22:59:04.336526 RX Vref 0 -> 0, step: 1
8062 22:59:04.336615
8063 22:59:04.339500 RX Delay 0 -> 252, step: 8
8064 22:59:04.343112 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8065 22:59:04.349678 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8066 22:59:04.353261 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8067 22:59:04.356359 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8068 22:59:04.359486 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8069 22:59:04.363423 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8070 22:59:04.369673 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8071 22:59:04.372923 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8072 22:59:04.376158 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8073 22:59:04.379433 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8074 22:59:04.383127 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8075 22:59:04.389414 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8076 22:59:04.392675 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8077 22:59:04.395969 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8078 22:59:04.399976 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8079 22:59:04.402629 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8080 22:59:04.406444 ==
8081 22:59:04.406529 Dram Type= 6, Freq= 0, CH_0, rank 1
8082 22:59:04.413044 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8083 22:59:04.413128 ==
8084 22:59:04.413195 DQS Delay:
8085 22:59:04.416277 DQS0 = 0, DQS1 = 0
8086 22:59:04.416362 DQM Delay:
8087 22:59:04.419548 DQM0 = 136, DQM1 = 128
8088 22:59:04.419650 DQ Delay:
8089 22:59:04.422783 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8090 22:59:04.425941 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8091 22:59:04.429613 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8092 22:59:04.432853 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8093 22:59:04.432955
8094 22:59:04.433046
8095 22:59:04.433134 ==
8096 22:59:04.436086 Dram Type= 6, Freq= 0, CH_0, rank 1
8097 22:59:04.442991 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8098 22:59:04.443075 ==
8099 22:59:04.443141
8100 22:59:04.443202
8101 22:59:04.443262 TX Vref Scan disable
8102 22:59:04.446591 == TX Byte 0 ==
8103 22:59:04.449941 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8104 22:59:04.456235 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8105 22:59:04.456319 == TX Byte 1 ==
8106 22:59:04.459467 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8107 22:59:04.463000 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8108 22:59:04.466568 ==
8109 22:59:04.469849 Dram Type= 6, Freq= 0, CH_0, rank 1
8110 22:59:04.472984 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8111 22:59:04.473085 ==
8112 22:59:04.486750
8113 22:59:04.489656 TX Vref early break, caculate TX vref
8114 22:59:04.493341 TX Vref=16, minBit 0, minWin=23, winSum=384
8115 22:59:04.496647 TX Vref=18, minBit 3, minWin=23, winSum=393
8116 22:59:04.499873 TX Vref=20, minBit 1, minWin=23, winSum=400
8117 22:59:04.503119 TX Vref=22, minBit 1, minWin=24, winSum=410
8118 22:59:04.506377 TX Vref=24, minBit 1, minWin=24, winSum=417
8119 22:59:04.512952 TX Vref=26, minBit 7, minWin=24, winSum=424
8120 22:59:04.516308 TX Vref=28, minBit 3, minWin=25, winSum=420
8121 22:59:04.519540 TX Vref=30, minBit 3, minWin=25, winSum=417
8122 22:59:04.522920 TX Vref=32, minBit 2, minWin=24, winSum=408
8123 22:59:04.526661 TX Vref=34, minBit 0, minWin=24, winSum=393
8124 22:59:04.533021 [TxChooseVref] Worse bit 3, Min win 25, Win sum 420, Final Vref 28
8125 22:59:04.533109
8126 22:59:04.536258 Final TX Range 0 Vref 28
8127 22:59:04.536368
8128 22:59:04.536463 ==
8129 22:59:04.539996 Dram Type= 6, Freq= 0, CH_0, rank 1
8130 22:59:04.543046 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8131 22:59:04.543156 ==
8132 22:59:04.543260
8133 22:59:04.543383
8134 22:59:04.546372 TX Vref Scan disable
8135 22:59:04.553451 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8136 22:59:04.553533 == TX Byte 0 ==
8137 22:59:04.556610 u2DelayCellOfst[0]=13 cells (4 PI)
8138 22:59:04.559968 u2DelayCellOfst[1]=13 cells (4 PI)
8139 22:59:04.563502 u2DelayCellOfst[2]=10 cells (3 PI)
8140 22:59:04.566169 u2DelayCellOfst[3]=10 cells (3 PI)
8141 22:59:04.569695 u2DelayCellOfst[4]=10 cells (3 PI)
8142 22:59:04.573114 u2DelayCellOfst[5]=0 cells (0 PI)
8143 22:59:04.576652 u2DelayCellOfst[6]=16 cells (5 PI)
8144 22:59:04.576743 u2DelayCellOfst[7]=16 cells (5 PI)
8145 22:59:04.583025 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8146 22:59:04.586302 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8147 22:59:04.589583 == TX Byte 1 ==
8148 22:59:04.589657 u2DelayCellOfst[8]=0 cells (0 PI)
8149 22:59:04.592800 u2DelayCellOfst[9]=0 cells (0 PI)
8150 22:59:04.595913 u2DelayCellOfst[10]=6 cells (2 PI)
8151 22:59:04.599305 u2DelayCellOfst[11]=0 cells (0 PI)
8152 22:59:04.602883 u2DelayCellOfst[12]=10 cells (3 PI)
8153 22:59:04.606069 u2DelayCellOfst[13]=6 cells (2 PI)
8154 22:59:04.609418 u2DelayCellOfst[14]=13 cells (4 PI)
8155 22:59:04.612469 u2DelayCellOfst[15]=10 cells (3 PI)
8156 22:59:04.616257 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8157 22:59:04.622744 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8158 22:59:04.622834 DramC Write-DBI on
8159 22:59:04.622903 ==
8160 22:59:04.625958 Dram Type= 6, Freq= 0, CH_0, rank 1
8161 22:59:04.629039 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8162 22:59:04.629140 ==
8163 22:59:04.632845
8164 22:59:04.632946
8165 22:59:04.633038 TX Vref Scan disable
8166 22:59:04.636190 == TX Byte 0 ==
8167 22:59:04.639288 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8168 22:59:04.642515 == TX Byte 1 ==
8169 22:59:04.646451 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8170 22:59:04.646552 DramC Write-DBI off
8171 22:59:04.649407
8172 22:59:04.649509 [DATLAT]
8173 22:59:04.649604 Freq=1600, CH0 RK1
8174 22:59:04.649699
8175 22:59:04.652626 DATLAT Default: 0xf
8176 22:59:04.652729 0, 0xFFFF, sum = 0
8177 22:59:04.655923 1, 0xFFFF, sum = 0
8178 22:59:04.656026 2, 0xFFFF, sum = 0
8179 22:59:04.659164 3, 0xFFFF, sum = 0
8180 22:59:04.659265 4, 0xFFFF, sum = 0
8181 22:59:04.663184 5, 0xFFFF, sum = 0
8182 22:59:04.663289 6, 0xFFFF, sum = 0
8183 22:59:04.666211 7, 0xFFFF, sum = 0
8184 22:59:04.669356 8, 0xFFFF, sum = 0
8185 22:59:04.669452 9, 0xFFFF, sum = 0
8186 22:59:04.673028 10, 0xFFFF, sum = 0
8187 22:59:04.673112 11, 0xFFFF, sum = 0
8188 22:59:04.676257 12, 0xFFFF, sum = 0
8189 22:59:04.676361 13, 0xFFFF, sum = 0
8190 22:59:04.679432 14, 0x0, sum = 1
8191 22:59:04.679509 15, 0x0, sum = 2
8192 22:59:04.683011 16, 0x0, sum = 3
8193 22:59:04.683135 17, 0x0, sum = 4
8194 22:59:04.683254 best_step = 15
8195 22:59:04.686056
8196 22:59:04.686156 ==
8197 22:59:04.689177 Dram Type= 6, Freq= 0, CH_0, rank 1
8198 22:59:04.692923 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8199 22:59:04.693025 ==
8200 22:59:04.693123 RX Vref Scan: 0
8201 22:59:04.693216
8202 22:59:04.696208 RX Vref 0 -> 0, step: 1
8203 22:59:04.696308
8204 22:59:04.699483 RX Delay 19 -> 252, step: 4
8205 22:59:04.702690 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8206 22:59:04.709560 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8207 22:59:04.712735 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8208 22:59:04.715758 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8209 22:59:04.719802 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8210 22:59:04.722455 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8211 22:59:04.725791 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8212 22:59:04.732738 iDelay=191, Bit 7, Center 142 (95 ~ 190) 96
8213 22:59:04.735991 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8214 22:59:04.739358 iDelay=191, Bit 9, Center 118 (67 ~ 170) 104
8215 22:59:04.742595 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8216 22:59:04.749164 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8217 22:59:04.752314 iDelay=191, Bit 12, Center 132 (83 ~ 182) 100
8218 22:59:04.755501 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8219 22:59:04.759487 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8220 22:59:04.762575 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8221 22:59:04.762657 ==
8222 22:59:04.765926 Dram Type= 6, Freq= 0, CH_0, rank 1
8223 22:59:04.772250 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8224 22:59:04.772334 ==
8225 22:59:04.772400 DQS Delay:
8226 22:59:04.776185 DQS0 = 0, DQS1 = 0
8227 22:59:04.776268 DQM Delay:
8228 22:59:04.779163 DQM0 = 134, DQM1 = 127
8229 22:59:04.779246 DQ Delay:
8230 22:59:04.782665 DQ0 =134, DQ1 =136, DQ2 =130, DQ3 =134
8231 22:59:04.785967 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =142
8232 22:59:04.789128 DQ8 =118, DQ9 =118, DQ10 =128, DQ11 =118
8233 22:59:04.792254 DQ12 =132, DQ13 =134, DQ14 =136, DQ15 =134
8234 22:59:04.792329
8235 22:59:04.792393
8236 22:59:04.792453
8237 22:59:04.795787 [DramC_TX_OE_Calibration] TA2
8238 22:59:04.798932 Original DQ_B0 (3 6) =30, OEN = 27
8239 22:59:04.802251 Original DQ_B1 (3 6) =30, OEN = 27
8240 22:59:04.806044 24, 0x0, End_B0=24 End_B1=24
8241 22:59:04.809001 25, 0x0, End_B0=25 End_B1=25
8242 22:59:04.809077 26, 0x0, End_B0=26 End_B1=26
8243 22:59:04.812234 27, 0x0, End_B0=27 End_B1=27
8244 22:59:04.815489 28, 0x0, End_B0=28 End_B1=28
8245 22:59:04.819090 29, 0x0, End_B0=29 End_B1=29
8246 22:59:04.819165 30, 0x0, End_B0=30 End_B1=30
8247 22:59:04.822356 31, 0x4141, End_B0=30 End_B1=30
8248 22:59:04.825573 Byte0 end_step=30 best_step=27
8249 22:59:04.828711 Byte1 end_step=30 best_step=27
8250 22:59:04.832014 Byte0 TX OE(2T, 0.5T) = (3, 3)
8251 22:59:04.835917 Byte1 TX OE(2T, 0.5T) = (3, 3)
8252 22:59:04.835991
8253 22:59:04.836056
8254 22:59:04.842087 [DQSOSCAuto] RK1, (LSB)MR18= 0x2109, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8255 22:59:04.845235 CH0 RK1: MR19=303, MR18=2109
8256 22:59:04.852393 CH0_RK1: MR19=0x303, MR18=0x2109, DQSOSC=393, MR23=63, INC=23, DEC=15
8257 22:59:04.855534 [RxdqsGatingPostProcess] freq 1600
8258 22:59:04.858592 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8259 22:59:04.861960 best DQS0 dly(2T, 0.5T) = (1, 1)
8260 22:59:04.865310 best DQS1 dly(2T, 0.5T) = (1, 1)
8261 22:59:04.868671 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8262 22:59:04.871825 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8263 22:59:04.875724 best DQS0 dly(2T, 0.5T) = (1, 1)
8264 22:59:04.878906 best DQS1 dly(2T, 0.5T) = (1, 1)
8265 22:59:04.882207 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8266 22:59:04.885306 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8267 22:59:04.888949 Pre-setting of DQS Precalculation
8268 22:59:04.891998 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8269 22:59:04.892084 ==
8270 22:59:04.895290 Dram Type= 6, Freq= 0, CH_1, rank 0
8271 22:59:04.898616 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8272 22:59:04.902240 ==
8273 22:59:04.905137 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8274 22:59:04.908890 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8275 22:59:04.915094 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8276 22:59:04.922133 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8277 22:59:04.929207 [CA 0] Center 42 (13~72) winsize 60
8278 22:59:04.932521 [CA 1] Center 42 (12~72) winsize 61
8279 22:59:04.935785 [CA 2] Center 39 (10~68) winsize 59
8280 22:59:04.938900 [CA 3] Center 38 (9~67) winsize 59
8281 22:59:04.942052 [CA 4] Center 38 (9~68) winsize 60
8282 22:59:04.945442 [CA 5] Center 37 (8~67) winsize 60
8283 22:59:04.945519
8284 22:59:04.948614 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8285 22:59:04.948686
8286 22:59:04.955724 [CATrainingPosCal] consider 1 rank data
8287 22:59:04.955805 u2DelayCellTimex100 = 290/100 ps
8288 22:59:04.961969 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8289 22:59:04.965264 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8290 22:59:04.968465 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8291 22:59:04.971857 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8292 22:59:04.975154 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8293 22:59:04.979008 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8294 22:59:04.979083
8295 22:59:04.982377 CA PerBit enable=1, Macro0, CA PI delay=37
8296 22:59:04.982479
8297 22:59:04.985705 [CBTSetCACLKResult] CA Dly = 37
8298 22:59:04.988893 CS Dly: 11 (0~42)
8299 22:59:04.992061 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8300 22:59:04.995062 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8301 22:59:04.995172 ==
8302 22:59:04.998316 Dram Type= 6, Freq= 0, CH_1, rank 1
8303 22:59:05.005611 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8304 22:59:05.005695 ==
8305 22:59:05.008756 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8306 22:59:05.011928 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8307 22:59:05.018335 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8308 22:59:05.024849 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8309 22:59:05.032381 [CA 0] Center 42 (12~72) winsize 61
8310 22:59:05.035657 [CA 1] Center 42 (13~72) winsize 60
8311 22:59:05.038828 [CA 2] Center 39 (9~69) winsize 61
8312 22:59:05.042757 [CA 3] Center 38 (9~68) winsize 60
8313 22:59:05.045902 [CA 4] Center 39 (9~69) winsize 61
8314 22:59:05.049139 [CA 5] Center 37 (8~67) winsize 60
8315 22:59:05.049219
8316 22:59:05.052379 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8317 22:59:05.052455
8318 22:59:05.055406 [CATrainingPosCal] consider 2 rank data
8319 22:59:05.058700 u2DelayCellTimex100 = 290/100 ps
8320 22:59:05.062451 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8321 22:59:05.068712 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8322 22:59:05.072049 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8323 22:59:05.075289 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8324 22:59:05.078628 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8325 22:59:05.082428 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8326 22:59:05.082506
8327 22:59:05.085732 CA PerBit enable=1, Macro0, CA PI delay=37
8328 22:59:05.085808
8329 22:59:05.088922 [CBTSetCACLKResult] CA Dly = 37
8330 22:59:05.092182 CS Dly: 12 (0~45)
8331 22:59:05.095358 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8332 22:59:05.098633 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8333 22:59:05.098708
8334 22:59:05.101738 ----->DramcWriteLeveling(PI) begin...
8335 22:59:05.101816 ==
8336 22:59:05.105668 Dram Type= 6, Freq= 0, CH_1, rank 0
8337 22:59:05.111817 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8338 22:59:05.111896 ==
8339 22:59:05.115126 Write leveling (Byte 0): 25 => 25
8340 22:59:05.115210 Write leveling (Byte 1): 27 => 27
8341 22:59:05.119046 DramcWriteLeveling(PI) end<-----
8342 22:59:05.119124
8343 22:59:05.119187 ==
8344 22:59:05.122202 Dram Type= 6, Freq= 0, CH_1, rank 0
8345 22:59:05.128363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8346 22:59:05.128445 ==
8347 22:59:05.132233 [Gating] SW mode calibration
8348 22:59:05.138411 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8349 22:59:05.141706 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8350 22:59:05.148610 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8351 22:59:05.151886 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8352 22:59:05.155128 1 4 8 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
8353 22:59:05.162000 1 4 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
8354 22:59:05.165366 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8355 22:59:05.168578 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8356 22:59:05.175323 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8357 22:59:05.178853 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8358 22:59:05.182026 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8359 22:59:05.188489 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8360 22:59:05.191860 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
8361 22:59:05.195054 1 5 12 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
8362 22:59:05.198355 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 22:59:05.205500 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 22:59:05.208665 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 22:59:05.211943 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 22:59:05.218581 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 22:59:05.221703 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 22:59:05.224967 1 6 8 | B1->B0 | 2424 3e3e | 0 1 | (1 1) (0 0)
8369 22:59:05.232012 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8370 22:59:05.234956 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8371 22:59:05.238697 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8372 22:59:05.244868 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8373 22:59:05.248491 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8374 22:59:05.251859 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8375 22:59:05.258222 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8376 22:59:05.261912 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8377 22:59:05.265116 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8378 22:59:05.271620 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8379 22:59:05.275281 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 22:59:05.278340 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 22:59:05.284864 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 22:59:05.288176 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 22:59:05.291292 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 22:59:05.297982 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 22:59:05.301275 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 22:59:05.304483 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 22:59:05.311540 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 22:59:05.314813 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 22:59:05.318067 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 22:59:05.321318 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 22:59:05.328282 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 22:59:05.331473 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8393 22:59:05.335286 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8394 22:59:05.341392 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 22:59:05.344898 Total UI for P1: 0, mck2ui 16
8396 22:59:05.348504 best dqsien dly found for B0: ( 1, 9, 10)
8397 22:59:05.348586 Total UI for P1: 0, mck2ui 16
8398 22:59:05.354780 best dqsien dly found for B1: ( 1, 9, 12)
8399 22:59:05.357941 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8400 22:59:05.361835 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8401 22:59:05.361925
8402 22:59:05.364969 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8403 22:59:05.368085 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8404 22:59:05.371181 [Gating] SW calibration Done
8405 22:59:05.371282 ==
8406 22:59:05.374572 Dram Type= 6, Freq= 0, CH_1, rank 0
8407 22:59:05.377863 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8408 22:59:05.377964 ==
8409 22:59:05.381006 RX Vref Scan: 0
8410 22:59:05.381103
8411 22:59:05.384354 RX Vref 0 -> 0, step: 1
8412 22:59:05.384451
8413 22:59:05.384546 RX Delay 0 -> 252, step: 8
8414 22:59:05.387586 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8415 22:59:05.394734 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8416 22:59:05.398048 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8417 22:59:05.401344 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8418 22:59:05.404656 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8419 22:59:05.407823 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8420 22:59:05.414725 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8421 22:59:05.417918 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8422 22:59:05.421296 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8423 22:59:05.424532 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8424 22:59:05.427714 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8425 22:59:05.434224 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8426 22:59:05.437916 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8427 22:59:05.441104 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8428 22:59:05.444296 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8429 22:59:05.447524 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8430 22:59:05.451112 ==
8431 22:59:05.454145 Dram Type= 6, Freq= 0, CH_1, rank 0
8432 22:59:05.457917 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8433 22:59:05.458001 ==
8434 22:59:05.458067 DQS Delay:
8435 22:59:05.461001 DQS0 = 0, DQS1 = 0
8436 22:59:05.461084 DQM Delay:
8437 22:59:05.464571 DQM0 = 137, DQM1 = 132
8438 22:59:05.464654 DQ Delay:
8439 22:59:05.467706 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8440 22:59:05.470911 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8441 22:59:05.474102 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8442 22:59:05.477500 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8443 22:59:05.477583
8444 22:59:05.477648
8445 22:59:05.477707 ==
8446 22:59:05.480746 Dram Type= 6, Freq= 0, CH_1, rank 0
8447 22:59:05.487258 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8448 22:59:05.487388 ==
8449 22:59:05.487501
8450 22:59:05.487592
8451 22:59:05.487666 TX Vref Scan disable
8452 22:59:05.491293 == TX Byte 0 ==
8453 22:59:05.494516 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8454 22:59:05.500986 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8455 22:59:05.501070 == TX Byte 1 ==
8456 22:59:05.504235 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8457 22:59:05.510923 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8458 22:59:05.511007 ==
8459 22:59:05.514207 Dram Type= 6, Freq= 0, CH_1, rank 0
8460 22:59:05.517405 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8461 22:59:05.517489 ==
8462 22:59:05.531076
8463 22:59:05.534075 TX Vref early break, caculate TX vref
8464 22:59:05.537811 TX Vref=16, minBit 1, minWin=21, winSum=371
8465 22:59:05.541108 TX Vref=18, minBit 6, minWin=22, winSum=383
8466 22:59:05.544317 TX Vref=20, minBit 1, minWin=23, winSum=393
8467 22:59:05.547362 TX Vref=22, minBit 1, minWin=23, winSum=402
8468 22:59:05.550547 TX Vref=24, minBit 0, minWin=25, winSum=417
8469 22:59:05.557337 TX Vref=26, minBit 0, minWin=25, winSum=425
8470 22:59:05.561064 TX Vref=28, minBit 2, minWin=25, winSum=428
8471 22:59:05.564430 TX Vref=30, minBit 0, minWin=25, winSum=419
8472 22:59:05.567587 TX Vref=32, minBit 0, minWin=24, winSum=414
8473 22:59:05.570507 TX Vref=34, minBit 0, minWin=24, winSum=406
8474 22:59:05.573904 TX Vref=36, minBit 0, minWin=23, winSum=392
8475 22:59:05.580437 [TxChooseVref] Worse bit 2, Min win 25, Win sum 428, Final Vref 28
8476 22:59:05.580526
8477 22:59:05.584189 Final TX Range 0 Vref 28
8478 22:59:05.584298
8479 22:59:05.584404 ==
8480 22:59:05.587483 Dram Type= 6, Freq= 0, CH_1, rank 0
8481 22:59:05.590545 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8482 22:59:05.590649 ==
8483 22:59:05.590749
8484 22:59:05.590846
8485 22:59:05.593696 TX Vref Scan disable
8486 22:59:05.600307 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8487 22:59:05.600393 == TX Byte 0 ==
8488 22:59:05.604114 u2DelayCellOfst[0]=20 cells (6 PI)
8489 22:59:05.607392 u2DelayCellOfst[1]=10 cells (3 PI)
8490 22:59:05.610633 u2DelayCellOfst[2]=0 cells (0 PI)
8491 22:59:05.613874 u2DelayCellOfst[3]=6 cells (2 PI)
8492 22:59:05.617176 u2DelayCellOfst[4]=10 cells (3 PI)
8493 22:59:05.620461 u2DelayCellOfst[5]=16 cells (5 PI)
8494 22:59:05.623677 u2DelayCellOfst[6]=20 cells (6 PI)
8495 22:59:05.627045 u2DelayCellOfst[7]=6 cells (2 PI)
8496 22:59:05.630385 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8497 22:59:05.633674 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8498 22:59:05.637412 == TX Byte 1 ==
8499 22:59:05.640419 u2DelayCellOfst[8]=0 cells (0 PI)
8500 22:59:05.640504 u2DelayCellOfst[9]=3 cells (1 PI)
8501 22:59:05.643646 u2DelayCellOfst[10]=10 cells (3 PI)
8502 22:59:05.647005 u2DelayCellOfst[11]=3 cells (1 PI)
8503 22:59:05.650270 u2DelayCellOfst[12]=13 cells (4 PI)
8504 22:59:05.653988 u2DelayCellOfst[13]=13 cells (4 PI)
8505 22:59:05.657114 u2DelayCellOfst[14]=16 cells (5 PI)
8506 22:59:05.660220 u2DelayCellOfst[15]=16 cells (5 PI)
8507 22:59:05.663579 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8508 22:59:05.670615 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8509 22:59:05.670697 DramC Write-DBI on
8510 22:59:05.670762 ==
8511 22:59:05.673802 Dram Type= 6, Freq= 0, CH_1, rank 0
8512 22:59:05.680065 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8513 22:59:05.680148 ==
8514 22:59:05.680213
8515 22:59:05.680274
8516 22:59:05.680332 TX Vref Scan disable
8517 22:59:05.684248 == TX Byte 0 ==
8518 22:59:05.687844 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8519 22:59:05.690725 == TX Byte 1 ==
8520 22:59:05.694298 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8521 22:59:05.694382 DramC Write-DBI off
8522 22:59:05.697375
8523 22:59:05.697505 [DATLAT]
8524 22:59:05.697612 Freq=1600, CH1 RK0
8525 22:59:05.697701
8526 22:59:05.701275 DATLAT Default: 0xf
8527 22:59:05.701382 0, 0xFFFF, sum = 0
8528 22:59:05.703991 1, 0xFFFF, sum = 0
8529 22:59:05.704066 2, 0xFFFF, sum = 0
8530 22:59:05.707743 3, 0xFFFF, sum = 0
8531 22:59:05.707826 4, 0xFFFF, sum = 0
8532 22:59:05.710896 5, 0xFFFF, sum = 0
8533 22:59:05.710979 6, 0xFFFF, sum = 0
8534 22:59:05.714267 7, 0xFFFF, sum = 0
8535 22:59:05.717402 8, 0xFFFF, sum = 0
8536 22:59:05.717486 9, 0xFFFF, sum = 0
8537 22:59:05.720641 10, 0xFFFF, sum = 0
8538 22:59:05.720724 11, 0xFFFF, sum = 0
8539 22:59:05.723975 12, 0xFFFF, sum = 0
8540 22:59:05.724078 13, 0xFFFF, sum = 0
8541 22:59:05.727805 14, 0x0, sum = 1
8542 22:59:05.727889 15, 0x0, sum = 2
8543 22:59:05.730376 16, 0x0, sum = 3
8544 22:59:05.730461 17, 0x0, sum = 4
8545 22:59:05.733921 best_step = 15
8546 22:59:05.734003
8547 22:59:05.734069 ==
8548 22:59:05.737122 Dram Type= 6, Freq= 0, CH_1, rank 0
8549 22:59:05.740962 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8550 22:59:05.741046 ==
8551 22:59:05.741113 RX Vref Scan: 1
8552 22:59:05.744084
8553 22:59:05.744166 Set Vref Range= 24 -> 127
8554 22:59:05.744232
8555 22:59:05.747146 RX Vref 24 -> 127, step: 1
8556 22:59:05.747229
8557 22:59:05.750423 RX Delay 27 -> 252, step: 4
8558 22:59:05.750506
8559 22:59:05.753721 Set Vref, RX VrefLevel [Byte0]: 24
8560 22:59:05.756867 [Byte1]: 24
8561 22:59:05.756950
8562 22:59:05.760536 Set Vref, RX VrefLevel [Byte0]: 25
8563 22:59:05.763649 [Byte1]: 25
8564 22:59:05.763731
8565 22:59:05.766811 Set Vref, RX VrefLevel [Byte0]: 26
8566 22:59:05.770205 [Byte1]: 26
8567 22:59:05.774423
8568 22:59:05.774524 Set Vref, RX VrefLevel [Byte0]: 27
8569 22:59:05.777677 [Byte1]: 27
8570 22:59:05.781502
8571 22:59:05.781585 Set Vref, RX VrefLevel [Byte0]: 28
8572 22:59:05.785366 [Byte1]: 28
8573 22:59:05.789311
8574 22:59:05.789394 Set Vref, RX VrefLevel [Byte0]: 29
8575 22:59:05.792368 [Byte1]: 29
8576 22:59:05.796628
8577 22:59:05.796732 Set Vref, RX VrefLevel [Byte0]: 30
8578 22:59:05.800254 [Byte1]: 30
8579 22:59:05.804381
8580 22:59:05.804485 Set Vref, RX VrefLevel [Byte0]: 31
8581 22:59:05.807346 [Byte1]: 31
8582 22:59:05.811915
8583 22:59:05.812015 Set Vref, RX VrefLevel [Byte0]: 32
8584 22:59:05.815131 [Byte1]: 32
8585 22:59:05.819587
8586 22:59:05.819666 Set Vref, RX VrefLevel [Byte0]: 33
8587 22:59:05.822878 [Byte1]: 33
8588 22:59:05.826904
8589 22:59:05.827002 Set Vref, RX VrefLevel [Byte0]: 34
8590 22:59:05.830069 [Byte1]: 34
8591 22:59:05.834536
8592 22:59:05.834631 Set Vref, RX VrefLevel [Byte0]: 35
8593 22:59:05.837818 [Byte1]: 35
8594 22:59:05.841663
8595 22:59:05.841760 Set Vref, RX VrefLevel [Byte0]: 36
8596 22:59:05.845474 [Byte1]: 36
8597 22:59:05.849330
8598 22:59:05.849440 Set Vref, RX VrefLevel [Byte0]: 37
8599 22:59:05.853057 [Byte1]: 37
8600 22:59:05.857012
8601 22:59:05.857107 Set Vref, RX VrefLevel [Byte0]: 38
8602 22:59:05.860346 [Byte1]: 38
8603 22:59:05.864731
8604 22:59:05.864814 Set Vref, RX VrefLevel [Byte0]: 39
8605 22:59:05.867762 [Byte1]: 39
8606 22:59:05.872174
8607 22:59:05.872259 Set Vref, RX VrefLevel [Byte0]: 40
8608 22:59:05.875322 [Byte1]: 40
8609 22:59:05.879756
8610 22:59:05.879841 Set Vref, RX VrefLevel [Byte0]: 41
8611 22:59:05.882739 [Byte1]: 41
8612 22:59:05.887488
8613 22:59:05.887574 Set Vref, RX VrefLevel [Byte0]: 42
8614 22:59:05.890653 [Byte1]: 42
8615 22:59:05.894504
8616 22:59:05.894589 Set Vref, RX VrefLevel [Byte0]: 43
8617 22:59:05.897847 [Byte1]: 43
8618 22:59:05.902364
8619 22:59:05.902449 Set Vref, RX VrefLevel [Byte0]: 44
8620 22:59:05.905432 [Byte1]: 44
8621 22:59:05.909750
8622 22:59:05.909833 Set Vref, RX VrefLevel [Byte0]: 45
8623 22:59:05.913302 [Byte1]: 45
8624 22:59:05.917526
8625 22:59:05.917614 Set Vref, RX VrefLevel [Byte0]: 46
8626 22:59:05.920492 [Byte1]: 46
8627 22:59:05.925096
8628 22:59:05.925179 Set Vref, RX VrefLevel [Byte0]: 47
8629 22:59:05.928398 [Byte1]: 47
8630 22:59:05.932411
8631 22:59:05.932515 Set Vref, RX VrefLevel [Byte0]: 48
8632 22:59:05.935684 [Byte1]: 48
8633 22:59:05.940149
8634 22:59:05.940252 Set Vref, RX VrefLevel [Byte0]: 49
8635 22:59:05.943475 [Byte1]: 49
8636 22:59:05.947404
8637 22:59:05.947505 Set Vref, RX VrefLevel [Byte0]: 50
8638 22:59:05.950525 [Byte1]: 50
8639 22:59:05.954897
8640 22:59:05.955009 Set Vref, RX VrefLevel [Byte0]: 51
8641 22:59:05.958197 [Byte1]: 51
8642 22:59:05.962659
8643 22:59:05.962770 Set Vref, RX VrefLevel [Byte0]: 52
8644 22:59:05.965884 [Byte1]: 52
8645 22:59:05.969979
8646 22:59:05.970089 Set Vref, RX VrefLevel [Byte0]: 53
8647 22:59:05.973172 [Byte1]: 53
8648 22:59:05.977441
8649 22:59:05.977524 Set Vref, RX VrefLevel [Byte0]: 54
8650 22:59:05.981019 [Byte1]: 54
8651 22:59:05.984930
8652 22:59:05.985013 Set Vref, RX VrefLevel [Byte0]: 55
8653 22:59:05.988552 [Byte1]: 55
8654 22:59:05.992337
8655 22:59:05.992419 Set Vref, RX VrefLevel [Byte0]: 56
8656 22:59:05.995977 [Byte1]: 56
8657 22:59:05.999956
8658 22:59:06.000040 Set Vref, RX VrefLevel [Byte0]: 57
8659 22:59:06.003248 [Byte1]: 57
8660 22:59:06.007922
8661 22:59:06.008005 Set Vref, RX VrefLevel [Byte0]: 58
8662 22:59:06.011178 [Byte1]: 58
8663 22:59:06.015489
8664 22:59:06.015577 Set Vref, RX VrefLevel [Byte0]: 59
8665 22:59:06.018388 [Byte1]: 59
8666 22:59:06.022715
8667 22:59:06.022793 Set Vref, RX VrefLevel [Byte0]: 60
8668 22:59:06.026175 [Byte1]: 60
8669 22:59:06.030505
8670 22:59:06.030587 Set Vref, RX VrefLevel [Byte0]: 61
8671 22:59:06.033701 [Byte1]: 61
8672 22:59:06.037594
8673 22:59:06.037669 Set Vref, RX VrefLevel [Byte0]: 62
8674 22:59:06.040778 [Byte1]: 62
8675 22:59:06.045523
8676 22:59:06.045594 Set Vref, RX VrefLevel [Byte0]: 63
8677 22:59:06.048795 [Byte1]: 63
8678 22:59:06.052750
8679 22:59:06.052833 Set Vref, RX VrefLevel [Byte0]: 64
8680 22:59:06.056530 [Byte1]: 64
8681 22:59:06.060339
8682 22:59:06.060422 Set Vref, RX VrefLevel [Byte0]: 65
8683 22:59:06.063738 [Byte1]: 65
8684 22:59:06.068318
8685 22:59:06.068401 Set Vref, RX VrefLevel [Byte0]: 66
8686 22:59:06.070942 [Byte1]: 66
8687 22:59:06.075506
8688 22:59:06.075582 Set Vref, RX VrefLevel [Byte0]: 67
8689 22:59:06.078711 [Byte1]: 67
8690 22:59:06.083102
8691 22:59:06.083185 Set Vref, RX VrefLevel [Byte0]: 68
8692 22:59:06.086258 [Byte1]: 68
8693 22:59:06.090634
8694 22:59:06.090717 Set Vref, RX VrefLevel [Byte0]: 69
8695 22:59:06.093887 [Byte1]: 69
8696 22:59:06.097997
8697 22:59:06.098080 Set Vref, RX VrefLevel [Byte0]: 70
8698 22:59:06.101216 [Byte1]: 70
8699 22:59:06.105433
8700 22:59:06.105516 Set Vref, RX VrefLevel [Byte0]: 71
8701 22:59:06.108762 [Byte1]: 71
8702 22:59:06.113381
8703 22:59:06.113464 Set Vref, RX VrefLevel [Byte0]: 72
8704 22:59:06.116638 [Byte1]: 72
8705 22:59:06.120544
8706 22:59:06.120626 Set Vref, RX VrefLevel [Byte0]: 73
8707 22:59:06.124320 [Byte1]: 73
8708 22:59:06.128293
8709 22:59:06.128376 Set Vref, RX VrefLevel [Byte0]: 74
8710 22:59:06.131475 [Byte1]: 74
8711 22:59:06.135606
8712 22:59:06.135689 Set Vref, RX VrefLevel [Byte0]: 75
8713 22:59:06.138792 [Byte1]: 75
8714 22:59:06.143160
8715 22:59:06.143242 Final RX Vref Byte 0 = 57 to rank0
8716 22:59:06.146499 Final RX Vref Byte 1 = 57 to rank0
8717 22:59:06.149819 Final RX Vref Byte 0 = 57 to rank1
8718 22:59:06.153113 Final RX Vref Byte 1 = 57 to rank1==
8719 22:59:06.156368 Dram Type= 6, Freq= 0, CH_1, rank 0
8720 22:59:06.163157 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8721 22:59:06.163242 ==
8722 22:59:06.163308 DQS Delay:
8723 22:59:06.163383 DQS0 = 0, DQS1 = 0
8724 22:59:06.166364 DQM Delay:
8725 22:59:06.166447 DQM0 = 134, DQM1 = 131
8726 22:59:06.169537 DQ Delay:
8727 22:59:06.173450 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8728 22:59:06.176764 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =134
8729 22:59:06.180064 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8730 22:59:06.183361 DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140
8731 22:59:06.183457
8732 22:59:06.183523
8733 22:59:06.183583
8734 22:59:06.186393 [DramC_TX_OE_Calibration] TA2
8735 22:59:06.189582 Original DQ_B0 (3 6) =30, OEN = 27
8736 22:59:06.193315 Original DQ_B1 (3 6) =30, OEN = 27
8737 22:59:06.196443 24, 0x0, End_B0=24 End_B1=24
8738 22:59:06.196527 25, 0x0, End_B0=25 End_B1=25
8739 22:59:06.199773 26, 0x0, End_B0=26 End_B1=26
8740 22:59:06.203502 27, 0x0, End_B0=27 End_B1=27
8741 22:59:06.206496 28, 0x0, End_B0=28 End_B1=28
8742 22:59:06.206594 29, 0x0, End_B0=29 End_B1=29
8743 22:59:06.210145 30, 0x0, End_B0=30 End_B1=30
8744 22:59:06.213299 31, 0x5151, End_B0=30 End_B1=30
8745 22:59:06.216617 Byte0 end_step=30 best_step=27
8746 22:59:06.219832 Byte1 end_step=30 best_step=27
8747 22:59:06.223089 Byte0 TX OE(2T, 0.5T) = (3, 3)
8748 22:59:06.223198 Byte1 TX OE(2T, 0.5T) = (3, 3)
8749 22:59:06.223292
8750 22:59:06.226917
8751 22:59:06.233585 [DQSOSCAuto] RK0, (LSB)MR18= 0x1926, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8752 22:59:06.236654 CH1 RK0: MR19=303, MR18=1926
8753 22:59:06.243317 CH1_RK0: MR19=0x303, MR18=0x1926, DQSOSC=390, MR23=63, INC=24, DEC=16
8754 22:59:06.243416
8755 22:59:06.246341 ----->DramcWriteLeveling(PI) begin...
8756 22:59:06.246425 ==
8757 22:59:06.250151 Dram Type= 6, Freq= 0, CH_1, rank 1
8758 22:59:06.253380 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8759 22:59:06.253465 ==
8760 22:59:06.256696 Write leveling (Byte 0): 25 => 25
8761 22:59:06.259821 Write leveling (Byte 1): 28 => 28
8762 22:59:06.263082 DramcWriteLeveling(PI) end<-----
8763 22:59:06.263165
8764 22:59:06.263232 ==
8765 22:59:06.266275 Dram Type= 6, Freq= 0, CH_1, rank 1
8766 22:59:06.269451 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8767 22:59:06.269535 ==
8768 22:59:06.273366 [Gating] SW mode calibration
8769 22:59:06.279992 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8770 22:59:06.286429 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8771 22:59:06.289544 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 22:59:06.293444 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8773 22:59:06.299871 1 4 8 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
8774 22:59:06.303064 1 4 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
8775 22:59:06.306281 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 22:59:06.313292 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 22:59:06.316322 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8778 22:59:06.320086 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8779 22:59:06.326694 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8780 22:59:06.329422 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8781 22:59:06.333130 1 5 8 | B1->B0 | 2b2b 3434 | 1 1 | (1 0) (1 1)
8782 22:59:06.339784 1 5 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)
8783 22:59:06.342938 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 22:59:06.346107 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 22:59:06.352758 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 22:59:06.355939 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8787 22:59:06.359302 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 22:59:06.366381 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 22:59:06.369516 1 6 8 | B1->B0 | 4545 2323 | 0 0 | (0 0) (0 0)
8790 22:59:06.372866 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 22:59:06.375953 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 22:59:06.382636 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 22:59:06.385863 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 22:59:06.389748 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 22:59:06.396049 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8796 22:59:06.399445 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8797 22:59:06.402611 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8798 22:59:06.409099 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8799 22:59:06.412898 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8800 22:59:06.416075 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 22:59:06.422993 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 22:59:06.426072 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 22:59:06.429192 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 22:59:06.435857 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 22:59:06.439566 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 22:59:06.442796 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 22:59:06.449124 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 22:59:06.452283 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 22:59:06.455475 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 22:59:06.462193 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 22:59:06.465928 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 22:59:06.469294 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 22:59:06.475593 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8814 22:59:06.478858 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8815 22:59:06.482144 Total UI for P1: 0, mck2ui 16
8816 22:59:06.485461 best dqsien dly found for B1: ( 1, 9, 8)
8817 22:59:06.488695 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8818 22:59:06.491970 Total UI for P1: 0, mck2ui 16
8819 22:59:06.495363 best dqsien dly found for B0: ( 1, 9, 12)
8820 22:59:06.499123 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8821 22:59:06.502404 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8822 22:59:06.502487
8823 22:59:06.505714 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8824 22:59:06.512093 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8825 22:59:06.512176 [Gating] SW calibration Done
8826 22:59:06.515231 ==
8827 22:59:06.515361 Dram Type= 6, Freq= 0, CH_1, rank 1
8828 22:59:06.522118 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8829 22:59:06.522202 ==
8830 22:59:06.522269 RX Vref Scan: 0
8831 22:59:06.522330
8832 22:59:06.525471 RX Vref 0 -> 0, step: 1
8833 22:59:06.525554
8834 22:59:06.528551 RX Delay 0 -> 252, step: 8
8835 22:59:06.532142 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8836 22:59:06.535120 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8837 22:59:06.539001 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8838 22:59:06.545342 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8839 22:59:06.548584 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8840 22:59:06.551929 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8841 22:59:06.555171 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8842 22:59:06.558802 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8843 22:59:06.564953 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8844 22:59:06.568566 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8845 22:59:06.571724 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8846 22:59:06.575505 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8847 22:59:06.578613 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8848 22:59:06.585113 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8849 22:59:06.588380 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8850 22:59:06.591549 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8851 22:59:06.591633 ==
8852 22:59:06.594818 Dram Type= 6, Freq= 0, CH_1, rank 1
8853 22:59:06.598752 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8854 22:59:06.598836 ==
8855 22:59:06.601841 DQS Delay:
8856 22:59:06.601924 DQS0 = 0, DQS1 = 0
8857 22:59:06.605008 DQM Delay:
8858 22:59:06.605090 DQM0 = 136, DQM1 = 133
8859 22:59:06.608342 DQ Delay:
8860 22:59:06.611679 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8861 22:59:06.614953 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8862 22:59:06.618219 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8863 22:59:06.621964 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8864 22:59:06.622047
8865 22:59:06.622112
8866 22:59:06.622173 ==
8867 22:59:06.625175 Dram Type= 6, Freq= 0, CH_1, rank 1
8868 22:59:06.628309 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8869 22:59:06.628393 ==
8870 22:59:06.628459
8871 22:59:06.628519
8872 22:59:06.631758 TX Vref Scan disable
8873 22:59:06.634998 == TX Byte 0 ==
8874 22:59:06.638043 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8875 22:59:06.641638 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8876 22:59:06.644555 == TX Byte 1 ==
8877 22:59:06.647864 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8878 22:59:06.651566 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8879 22:59:06.651649 ==
8880 22:59:06.654939 Dram Type= 6, Freq= 0, CH_1, rank 1
8881 22:59:06.661292 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8882 22:59:06.661376 ==
8883 22:59:06.673536
8884 22:59:06.677280 TX Vref early break, caculate TX vref
8885 22:59:06.680317 TX Vref=16, minBit 0, minWin=22, winSum=384
8886 22:59:06.683606 TX Vref=18, minBit 0, minWin=23, winSum=392
8887 22:59:06.687248 TX Vref=20, minBit 2, minWin=23, winSum=402
8888 22:59:06.690660 TX Vref=22, minBit 1, minWin=24, winSum=405
8889 22:59:06.694038 TX Vref=24, minBit 0, minWin=24, winSum=419
8890 22:59:06.700603 TX Vref=26, minBit 0, minWin=25, winSum=422
8891 22:59:06.704049 TX Vref=28, minBit 0, minWin=25, winSum=426
8892 22:59:06.707127 TX Vref=30, minBit 0, minWin=25, winSum=423
8893 22:59:06.710270 TX Vref=32, minBit 1, minWin=24, winSum=417
8894 22:59:06.713609 TX Vref=34, minBit 0, minWin=25, winSum=411
8895 22:59:06.716931 TX Vref=36, minBit 0, minWin=24, winSum=397
8896 22:59:06.724100 [TxChooseVref] Worse bit 0, Min win 25, Win sum 426, Final Vref 28
8897 22:59:06.724187
8898 22:59:06.727219 Final TX Range 0 Vref 28
8899 22:59:06.727351
8900 22:59:06.727436 ==
8901 22:59:06.730506 Dram Type= 6, Freq= 0, CH_1, rank 1
8902 22:59:06.733668 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8903 22:59:06.733752 ==
8904 22:59:06.733817
8905 22:59:06.733878
8906 22:59:06.736878 TX Vref Scan disable
8907 22:59:06.744079 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8908 22:59:06.744162 == TX Byte 0 ==
8909 22:59:06.747024 u2DelayCellOfst[0]=20 cells (6 PI)
8910 22:59:06.750647 u2DelayCellOfst[1]=13 cells (4 PI)
8911 22:59:06.753569 u2DelayCellOfst[2]=0 cells (0 PI)
8912 22:59:06.757360 u2DelayCellOfst[3]=6 cells (2 PI)
8913 22:59:06.760541 u2DelayCellOfst[4]=10 cells (3 PI)
8914 22:59:06.763794 u2DelayCellOfst[5]=20 cells (6 PI)
8915 22:59:06.766948 u2DelayCellOfst[6]=20 cells (6 PI)
8916 22:59:06.770532 u2DelayCellOfst[7]=6 cells (2 PI)
8917 22:59:06.773664 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8918 22:59:06.776802 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8919 22:59:06.780507 == TX Byte 1 ==
8920 22:59:06.780589 u2DelayCellOfst[8]=0 cells (0 PI)
8921 22:59:06.783746 u2DelayCellOfst[9]=3 cells (1 PI)
8922 22:59:06.786674 u2DelayCellOfst[10]=10 cells (3 PI)
8923 22:59:06.790486 u2DelayCellOfst[11]=0 cells (0 PI)
8924 22:59:06.793561 u2DelayCellOfst[12]=13 cells (4 PI)
8925 22:59:06.796825 u2DelayCellOfst[13]=13 cells (4 PI)
8926 22:59:06.800116 u2DelayCellOfst[14]=16 cells (5 PI)
8927 22:59:06.803305 u2DelayCellOfst[15]=16 cells (5 PI)
8928 22:59:06.806603 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8929 22:59:06.813740 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8930 22:59:06.813824 DramC Write-DBI on
8931 22:59:06.813891 ==
8932 22:59:06.816947 Dram Type= 6, Freq= 0, CH_1, rank 1
8933 22:59:06.820258 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8934 22:59:06.823547 ==
8935 22:59:06.823629
8936 22:59:06.823694
8937 22:59:06.823756 TX Vref Scan disable
8938 22:59:06.827006 == TX Byte 0 ==
8939 22:59:06.830105 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8940 22:59:06.833243 == TX Byte 1 ==
8941 22:59:06.837225 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8942 22:59:06.840312 DramC Write-DBI off
8943 22:59:06.840395
8944 22:59:06.840460 [DATLAT]
8945 22:59:06.840519 Freq=1600, CH1 RK1
8946 22:59:06.840578
8947 22:59:06.843578 DATLAT Default: 0xf
8948 22:59:06.843660 0, 0xFFFF, sum = 0
8949 22:59:06.846934 1, 0xFFFF, sum = 0
8950 22:59:06.850027 2, 0xFFFF, sum = 0
8951 22:59:06.850132 3, 0xFFFF, sum = 0
8952 22:59:06.853807 4, 0xFFFF, sum = 0
8953 22:59:06.853892 5, 0xFFFF, sum = 0
8954 22:59:06.856928 6, 0xFFFF, sum = 0
8955 22:59:06.857012 7, 0xFFFF, sum = 0
8956 22:59:06.860354 8, 0xFFFF, sum = 0
8957 22:59:06.860440 9, 0xFFFF, sum = 0
8958 22:59:06.863501 10, 0xFFFF, sum = 0
8959 22:59:06.863590 11, 0xFFFF, sum = 0
8960 22:59:06.866826 12, 0xFFFF, sum = 0
8961 22:59:06.866933 13, 0xFFFF, sum = 0
8962 22:59:06.870182 14, 0x0, sum = 1
8963 22:59:06.870298 15, 0x0, sum = 2
8964 22:59:06.873436 16, 0x0, sum = 3
8965 22:59:06.873527 17, 0x0, sum = 4
8966 22:59:06.876994 best_step = 15
8967 22:59:06.877097
8968 22:59:06.877203 ==
8969 22:59:06.880226 Dram Type= 6, Freq= 0, CH_1, rank 1
8970 22:59:06.883280 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8971 22:59:06.883413 ==
8972 22:59:06.883498 RX Vref Scan: 0
8973 22:59:06.886926
8974 22:59:06.887033 RX Vref 0 -> 0, step: 1
8975 22:59:06.887126
8976 22:59:06.889966 RX Delay 19 -> 252, step: 4
8977 22:59:06.893461 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8978 22:59:06.900414 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8979 22:59:06.903701 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8980 22:59:06.906988 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8981 22:59:06.910436 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8982 22:59:06.913502 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8983 22:59:06.916612 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8984 22:59:06.923648 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8985 22:59:06.927003 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8986 22:59:06.930448 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8987 22:59:06.933509 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8988 22:59:06.936826 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8989 22:59:06.943359 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8990 22:59:06.947138 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8991 22:59:06.950431 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8992 22:59:06.953597 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8993 22:59:06.953686 ==
8994 22:59:06.957223 Dram Type= 6, Freq= 0, CH_1, rank 1
8995 22:59:06.963842 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8996 22:59:06.963946 ==
8997 22:59:06.964028 DQS Delay:
8998 22:59:06.964105 DQS0 = 0, DQS1 = 0
8999 22:59:06.966779 DQM Delay:
9000 22:59:06.966891 DQM0 = 134, DQM1 = 130
9001 22:59:06.970455 DQ Delay:
9002 22:59:06.973566 DQ0 =138, DQ1 =130, DQ2 =120, DQ3 =130
9003 22:59:06.977350 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9004 22:59:06.980636 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
9005 22:59:06.983534 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =138
9006 22:59:06.983617
9007 22:59:06.983682
9008 22:59:06.983743
9009 22:59:06.987203 [DramC_TX_OE_Calibration] TA2
9010 22:59:06.990386 Original DQ_B0 (3 6) =30, OEN = 27
9011 22:59:06.993889 Original DQ_B1 (3 6) =30, OEN = 27
9012 22:59:06.996966 24, 0x0, End_B0=24 End_B1=24
9013 22:59:06.997051 25, 0x0, End_B0=25 End_B1=25
9014 22:59:07.000747 26, 0x0, End_B0=26 End_B1=26
9015 22:59:07.003671 27, 0x0, End_B0=27 End_B1=27
9016 22:59:07.006689 28, 0x0, End_B0=28 End_B1=28
9017 22:59:07.006773 29, 0x0, End_B0=29 End_B1=29
9018 22:59:07.010746 30, 0x0, End_B0=30 End_B1=30
9019 22:59:07.013362 31, 0x4545, End_B0=30 End_B1=30
9020 22:59:07.017282 Byte0 end_step=30 best_step=27
9021 22:59:07.020398 Byte1 end_step=30 best_step=27
9022 22:59:07.023704 Byte0 TX OE(2T, 0.5T) = (3, 3)
9023 22:59:07.023787 Byte1 TX OE(2T, 0.5T) = (3, 3)
9024 22:59:07.023853
9025 22:59:07.023915
9026 22:59:07.033335 [DQSOSCAuto] RK1, (LSB)MR18= 0x2509, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
9027 22:59:07.036649 CH1 RK1: MR19=303, MR18=2509
9028 22:59:07.043768 CH1_RK1: MR19=0x303, MR18=0x2509, DQSOSC=391, MR23=63, INC=24, DEC=16
9029 22:59:07.043855 [RxdqsGatingPostProcess] freq 1600
9030 22:59:07.050312 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9031 22:59:07.053420 best DQS0 dly(2T, 0.5T) = (1, 1)
9032 22:59:07.056651 best DQS1 dly(2T, 0.5T) = (1, 1)
9033 22:59:07.060368 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9034 22:59:07.063640 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9035 22:59:07.066991 best DQS0 dly(2T, 0.5T) = (1, 1)
9036 22:59:07.070358 best DQS1 dly(2T, 0.5T) = (1, 1)
9037 22:59:07.073481 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9038 22:59:07.076442 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9039 22:59:07.076525 Pre-setting of DQS Precalculation
9040 22:59:07.083256 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9041 22:59:07.090442 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9042 22:59:07.096799 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9043 22:59:07.096883
9044 22:59:07.096948
9045 22:59:07.099963 [Calibration Summary] 3200 Mbps
9046 22:59:07.103530 CH 0, Rank 0
9047 22:59:07.103613 SW Impedance : PASS
9048 22:59:07.106557 DUTY Scan : NO K
9049 22:59:07.110244 ZQ Calibration : PASS
9050 22:59:07.110327 Jitter Meter : NO K
9051 22:59:07.113227 CBT Training : PASS
9052 22:59:07.116502 Write leveling : PASS
9053 22:59:07.116584 RX DQS gating : PASS
9054 22:59:07.119777 RX DQ/DQS(RDDQC) : PASS
9055 22:59:07.119859 TX DQ/DQS : PASS
9056 22:59:07.123606 RX DATLAT : PASS
9057 22:59:07.126608 RX DQ/DQS(Engine): PASS
9058 22:59:07.126690 TX OE : PASS
9059 22:59:07.129839 All Pass.
9060 22:59:07.129922
9061 22:59:07.129987 CH 0, Rank 1
9062 22:59:07.133062 SW Impedance : PASS
9063 22:59:07.133145 DUTY Scan : NO K
9064 22:59:07.136438 ZQ Calibration : PASS
9065 22:59:07.139588 Jitter Meter : NO K
9066 22:59:07.139671 CBT Training : PASS
9067 22:59:07.143038 Write leveling : PASS
9068 22:59:07.146529 RX DQS gating : PASS
9069 22:59:07.146612 RX DQ/DQS(RDDQC) : PASS
9070 22:59:07.150214 TX DQ/DQS : PASS
9071 22:59:07.152913 RX DATLAT : PASS
9072 22:59:07.152995 RX DQ/DQS(Engine): PASS
9073 22:59:07.156628 TX OE : PASS
9074 22:59:07.156716 All Pass.
9075 22:59:07.156782
9076 22:59:07.159635 CH 1, Rank 0
9077 22:59:07.159717 SW Impedance : PASS
9078 22:59:07.162932 DUTY Scan : NO K
9079 22:59:07.166820 ZQ Calibration : PASS
9080 22:59:07.166903 Jitter Meter : NO K
9081 22:59:07.170086 CBT Training : PASS
9082 22:59:07.173284 Write leveling : PASS
9083 22:59:07.173367 RX DQS gating : PASS
9084 22:59:07.176407 RX DQ/DQS(RDDQC) : PASS
9085 22:59:07.176494 TX DQ/DQS : PASS
9086 22:59:07.179643 RX DATLAT : PASS
9087 22:59:07.182953 RX DQ/DQS(Engine): PASS
9088 22:59:07.183051 TX OE : PASS
9089 22:59:07.186640 All Pass.
9090 22:59:07.186723
9091 22:59:07.186789 CH 1, Rank 1
9092 22:59:07.189753 SW Impedance : PASS
9093 22:59:07.189863 DUTY Scan : NO K
9094 22:59:07.192952 ZQ Calibration : PASS
9095 22:59:07.196158 Jitter Meter : NO K
9096 22:59:07.196260 CBT Training : PASS
9097 22:59:07.199918 Write leveling : PASS
9098 22:59:07.202877 RX DQS gating : PASS
9099 22:59:07.202953 RX DQ/DQS(RDDQC) : PASS
9100 22:59:07.206495 TX DQ/DQS : PASS
9101 22:59:07.209604 RX DATLAT : PASS
9102 22:59:07.209702 RX DQ/DQS(Engine): PASS
9103 22:59:07.213278 TX OE : PASS
9104 22:59:07.213380 All Pass.
9105 22:59:07.213469
9106 22:59:07.216142 DramC Write-DBI on
9107 22:59:07.219378 PER_BANK_REFRESH: Hybrid Mode
9108 22:59:07.219453 TX_TRACKING: ON
9109 22:59:07.229447 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9110 22:59:07.236132 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9111 22:59:07.242719 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9112 22:59:07.246050 [FAST_K] Save calibration result to emmc
9113 22:59:07.249408 sync common calibartion params.
9114 22:59:07.252621 sync cbt_mode0:1, 1:1
9115 22:59:07.256526 dram_init: ddr_geometry: 2
9116 22:59:07.256624 dram_init: ddr_geometry: 2
9117 22:59:07.259775 dram_init: ddr_geometry: 2
9118 22:59:07.263218 0:dram_rank_size:100000000
9119 22:59:07.263321 1:dram_rank_size:100000000
9120 22:59:07.269807 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9121 22:59:07.273054 DFS_SHUFFLE_HW_MODE: ON
9122 22:59:07.276153 dramc_set_vcore_voltage set vcore to 725000
9123 22:59:07.279449 Read voltage for 1600, 0
9124 22:59:07.279547 Vio18 = 0
9125 22:59:07.279642 Vcore = 725000
9126 22:59:07.282652 Vdram = 0
9127 22:59:07.282751 Vddq = 0
9128 22:59:07.282840 Vmddr = 0
9129 22:59:07.286601 switch to 3200 Mbps bootup
9130 22:59:07.286700 [DramcRunTimeConfig]
9131 22:59:07.289364 PHYPLL
9132 22:59:07.289467 DPM_CONTROL_AFTERK: ON
9133 22:59:07.293006 PER_BANK_REFRESH: ON
9134 22:59:07.296100 REFRESH_OVERHEAD_REDUCTION: ON
9135 22:59:07.296176 CMD_PICG_NEW_MODE: OFF
9136 22:59:07.299417 XRTWTW_NEW_MODE: ON
9137 22:59:07.299492 XRTRTR_NEW_MODE: ON
9138 22:59:07.302687 TX_TRACKING: ON
9139 22:59:07.302783 RDSEL_TRACKING: OFF
9140 22:59:07.305877 DQS Precalculation for DVFS: ON
9141 22:59:07.309543 RX_TRACKING: OFF
9142 22:59:07.309639 HW_GATING DBG: ON
9143 22:59:07.313095 ZQCS_ENABLE_LP4: ON
9144 22:59:07.313190 RX_PICG_NEW_MODE: ON
9145 22:59:07.316149 TX_PICG_NEW_MODE: ON
9146 22:59:07.316226 ENABLE_RX_DCM_DPHY: ON
9147 22:59:07.319802 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9148 22:59:07.322914 DUMMY_READ_FOR_TRACKING: OFF
9149 22:59:07.326520 !!! SPM_CONTROL_AFTERK: OFF
9150 22:59:07.329553 !!! SPM could not control APHY
9151 22:59:07.329630 IMPEDANCE_TRACKING: ON
9152 22:59:07.333325 TEMP_SENSOR: ON
9153 22:59:07.333400 HW_SAVE_FOR_SR: OFF
9154 22:59:07.336437 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9155 22:59:07.339424 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9156 22:59:07.343064 Read ODT Tracking: ON
9157 22:59:07.346349 Refresh Rate DeBounce: ON
9158 22:59:07.346447 DFS_NO_QUEUE_FLUSH: ON
9159 22:59:07.349594 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9160 22:59:07.352867 ENABLE_DFS_RUNTIME_MRW: OFF
9161 22:59:07.356186 DDR_RESERVE_NEW_MODE: ON
9162 22:59:07.356257 MR_CBT_SWITCH_FREQ: ON
9163 22:59:07.359505 =========================
9164 22:59:07.378045 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9165 22:59:07.380996 dram_init: ddr_geometry: 2
9166 22:59:07.399573 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9167 22:59:07.403144 dram_init: dram init end (result: 0)
9168 22:59:07.409814 DRAM-K: Full calibration passed in 24446 msecs
9169 22:59:07.412918 MRC: failed to locate region type 0.
9170 22:59:07.413017 DRAM rank0 size:0x100000000,
9171 22:59:07.416201 DRAM rank1 size=0x100000000
9172 22:59:07.425975 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9173 22:59:07.433206 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9174 22:59:07.439840 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9175 22:59:07.446462 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9176 22:59:07.449329 DRAM rank0 size:0x100000000,
9177 22:59:07.453060 DRAM rank1 size=0x100000000
9178 22:59:07.453161 CBMEM:
9179 22:59:07.456309 IMD: root @ 0xfffff000 254 entries.
9180 22:59:07.459620 IMD: root @ 0xffffec00 62 entries.
9181 22:59:07.463034 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9182 22:59:07.466327 WARNING: RO_VPD is uninitialized or empty.
9183 22:59:07.472842 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9184 22:59:07.479514 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9185 22:59:07.492410 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9186 22:59:07.503686 BS: romstage times (exec / console): total (unknown) / 23980 ms
9187 22:59:07.503765
9188 22:59:07.503830
9189 22:59:07.513780 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9190 22:59:07.516918 ARM64: Exception handlers installed.
9191 22:59:07.520692 ARM64: Testing exception
9192 22:59:07.523999 ARM64: Done test exception
9193 22:59:07.524070 Enumerating buses...
9194 22:59:07.527278 Show all devs... Before device enumeration.
9195 22:59:07.530511 Root Device: enabled 1
9196 22:59:07.533590 CPU_CLUSTER: 0: enabled 1
9197 22:59:07.533686 CPU: 00: enabled 1
9198 22:59:07.537277 Compare with tree...
9199 22:59:07.537378 Root Device: enabled 1
9200 22:59:07.540358 CPU_CLUSTER: 0: enabled 1
9201 22:59:07.544004 CPU: 00: enabled 1
9202 22:59:07.544105 Root Device scanning...
9203 22:59:07.546944 scan_static_bus for Root Device
9204 22:59:07.550652 CPU_CLUSTER: 0 enabled
9205 22:59:07.553728 scan_static_bus for Root Device done
9206 22:59:07.557444 scan_bus: bus Root Device finished in 8 msecs
9207 22:59:07.557520 done
9208 22:59:07.563751 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9209 22:59:07.566976 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9210 22:59:07.573364 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9211 22:59:07.576649 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9212 22:59:07.579972 Allocating resources...
9213 22:59:07.583302 Reading resources...
9214 22:59:07.586584 Root Device read_resources bus 0 link: 0
9215 22:59:07.586683 DRAM rank0 size:0x100000000,
9216 22:59:07.590348 DRAM rank1 size=0x100000000
9217 22:59:07.593653 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9218 22:59:07.596592 CPU: 00 missing read_resources
9219 22:59:07.600400 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9220 22:59:07.606789 Root Device read_resources bus 0 link: 0 done
9221 22:59:07.606899 Done reading resources.
9222 22:59:07.613260 Show resources in subtree (Root Device)...After reading.
9223 22:59:07.616388 Root Device child on link 0 CPU_CLUSTER: 0
9224 22:59:07.619548 CPU_CLUSTER: 0 child on link 0 CPU: 00
9225 22:59:07.629995 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9226 22:59:07.630115 CPU: 00
9227 22:59:07.633364 Root Device assign_resources, bus 0 link: 0
9228 22:59:07.636516 CPU_CLUSTER: 0 missing set_resources
9229 22:59:07.640264 Root Device assign_resources, bus 0 link: 0 done
9230 22:59:07.643187 Done setting resources.
9231 22:59:07.649891 Show resources in subtree (Root Device)...After assigning values.
9232 22:59:07.653690 Root Device child on link 0 CPU_CLUSTER: 0
9233 22:59:07.656748 CPU_CLUSTER: 0 child on link 0 CPU: 00
9234 22:59:07.666404 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9235 22:59:07.666489 CPU: 00
9236 22:59:07.670145 Done allocating resources.
9237 22:59:07.673359 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9238 22:59:07.676677 Enabling resources...
9239 22:59:07.676793 done.
9240 22:59:07.683271 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9241 22:59:07.683395 Initializing devices...
9242 22:59:07.686463 Root Device init
9243 22:59:07.686564 init hardware done!
9244 22:59:07.689655 0x00000018: ctrlr->caps
9245 22:59:07.693370 52.000 MHz: ctrlr->f_max
9246 22:59:07.693456 0.400 MHz: ctrlr->f_min
9247 22:59:07.696691 0x40ff8080: ctrlr->voltages
9248 22:59:07.696776 sclk: 390625
9249 22:59:07.699873 Bus Width = 1
9250 22:59:07.699960 sclk: 390625
9251 22:59:07.700027 Bus Width = 1
9252 22:59:07.703410 Early init status = 3
9253 22:59:07.709543 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9254 22:59:07.713541 in-header: 03 fc 00 00 01 00 00 00
9255 22:59:07.716724 in-data: 00
9256 22:59:07.719794 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9257 22:59:07.724364 in-header: 03 fd 00 00 00 00 00 00
9258 22:59:07.727559 in-data:
9259 22:59:07.730845 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9260 22:59:07.735532 in-header: 03 fc 00 00 01 00 00 00
9261 22:59:07.738919 in-data: 00
9262 22:59:07.742241 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9263 22:59:07.747351 in-header: 03 fd 00 00 00 00 00 00
9264 22:59:07.751077 in-data:
9265 22:59:07.754140 [SSUSB] Setting up USB HOST controller...
9266 22:59:07.757964 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9267 22:59:07.760846 [SSUSB] phy power-on done.
9268 22:59:07.764123 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9269 22:59:07.770818 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9270 22:59:07.774513 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9271 22:59:07.781406 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9272 22:59:07.787942 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9273 22:59:07.794555 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9274 22:59:07.800992 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9275 22:59:07.807489 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9276 22:59:07.807572 SPM: binary array size = 0x9dc
9277 22:59:07.814672 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9278 22:59:07.821107 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9279 22:59:07.827920 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9280 22:59:07.831100 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9281 22:59:07.834320 configure_display: Starting display init
9282 22:59:07.870716 anx7625_power_on_init: Init interface.
9283 22:59:07.874575 anx7625_disable_pd_protocol: Disabled PD feature.
9284 22:59:07.877570 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9285 22:59:07.905406 anx7625_start_dp_work: Secure OCM version=00
9286 22:59:07.908659 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9287 22:59:07.923102 sp_tx_get_edid_block: EDID Block = 1
9288 22:59:08.026226 Extracted contents:
9289 22:59:08.029373 header: 00 ff ff ff ff ff ff 00
9290 22:59:08.032567 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9291 22:59:08.035911 version: 01 04
9292 22:59:08.038967 basic params: 95 1f 11 78 0a
9293 22:59:08.042496 chroma info: 76 90 94 55 54 90 27 21 50 54
9294 22:59:08.046117 established: 00 00 00
9295 22:59:08.052638 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9296 22:59:08.055850 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9297 22:59:08.062065 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9298 22:59:08.069137 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9299 22:59:08.075405 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9300 22:59:08.079068 extensions: 00
9301 22:59:08.079173 checksum: fb
9302 22:59:08.079271
9303 22:59:08.082008 Manufacturer: IVO Model 57d Serial Number 0
9304 22:59:08.085863 Made week 0 of 2020
9305 22:59:08.085970 EDID version: 1.4
9306 22:59:08.088744 Digital display
9307 22:59:08.092411 6 bits per primary color channel
9308 22:59:08.092519 DisplayPort interface
9309 22:59:08.095609 Maximum image size: 31 cm x 17 cm
9310 22:59:08.098809 Gamma: 220%
9311 22:59:08.098910 Check DPMS levels
9312 22:59:08.102299 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9313 22:59:08.105367 First detailed timing is preferred timing
9314 22:59:08.108636 Established timings supported:
9315 22:59:08.112493 Standard timings supported:
9316 22:59:08.115806 Detailed timings
9317 22:59:08.119158 Hex of detail: 383680a07038204018303c0035ae10000019
9318 22:59:08.122372 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9319 22:59:08.128707 0780 0798 07c8 0820 hborder 0
9320 22:59:08.131901 0438 043b 0447 0458 vborder 0
9321 22:59:08.135703 -hsync -vsync
9322 22:59:08.135818 Did detailed timing
9323 22:59:08.142167 Hex of detail: 000000000000000000000000000000000000
9324 22:59:08.142281 Manufacturer-specified data, tag 0
9325 22:59:08.148605 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9326 22:59:08.148712 ASCII string: InfoVision
9327 22:59:08.155360 Hex of detail: 000000fe00523134304e574635205248200a
9328 22:59:08.158599 ASCII string: R140NWF5 RH
9329 22:59:08.158672 Checksum
9330 22:59:08.158735 Checksum: 0xfb (valid)
9331 22:59:08.165674 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9332 22:59:08.168352 DSI data_rate: 832800000 bps
9333 22:59:08.172229 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9334 22:59:08.178728 anx7625_parse_edid: pixelclock(138800).
9335 22:59:08.181792 hactive(1920), hsync(48), hfp(24), hbp(88)
9336 22:59:08.185390 vactive(1080), vsync(12), vfp(3), vbp(17)
9337 22:59:08.188499 anx7625_dsi_config: config dsi.
9338 22:59:08.195418 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9339 22:59:08.208072 anx7625_dsi_config: success to config DSI
9340 22:59:08.211331 anx7625_dp_start: MIPI phy setup OK.
9341 22:59:08.214529 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9342 22:59:08.217778 mtk_ddp_mode_set invalid vrefresh 60
9343 22:59:08.221113 main_disp_path_setup
9344 22:59:08.221213 ovl_layer_smi_id_en
9345 22:59:08.224941 ovl_layer_smi_id_en
9346 22:59:08.225040 ccorr_config
9347 22:59:08.225151 aal_config
9348 22:59:08.228078 gamma_config
9349 22:59:08.228184 postmask_config
9350 22:59:08.231231 dither_config
9351 22:59:08.234540 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9352 22:59:08.241441 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9353 22:59:08.244506 Root Device init finished in 555 msecs
9354 22:59:08.244607 CPU_CLUSTER: 0 init
9355 22:59:08.254816 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9356 22:59:08.258063 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9357 22:59:08.261308 APU_MBOX 0x190000b0 = 0x10001
9358 22:59:08.264465 APU_MBOX 0x190001b0 = 0x10001
9359 22:59:08.268064 APU_MBOX 0x190005b0 = 0x10001
9360 22:59:08.271460 APU_MBOX 0x190006b0 = 0x10001
9361 22:59:08.274746 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9362 22:59:08.287050 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9363 22:59:08.299243 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9364 22:59:08.306038 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9365 22:59:08.317792 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9366 22:59:08.327018 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9367 22:59:08.330259 CPU_CLUSTER: 0 init finished in 81 msecs
9368 22:59:08.333331 Devices initialized
9369 22:59:08.336488 Show all devs... After init.
9370 22:59:08.336590 Root Device: enabled 1
9371 22:59:08.339753 CPU_CLUSTER: 0: enabled 1
9372 22:59:08.343603 CPU: 00: enabled 1
9373 22:59:08.346830 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9374 22:59:08.349918 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9375 22:59:08.353060 ELOG: NV offset 0x57f000 size 0x1000
9376 22:59:08.360184 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9377 22:59:08.366709 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9378 22:59:08.369861 ELOG: Event(17) added with size 13 at 2023-06-05 22:59:01 UTC
9379 22:59:08.376036 out: cmd=0x121: 03 db 21 01 00 00 00 00
9380 22:59:08.379999 in-header: 03 e2 00 00 2c 00 00 00
9381 22:59:08.389920 in-data: 7d 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9382 22:59:08.396304 ELOG: Event(A1) added with size 10 at 2023-06-05 22:59:01 UTC
9383 22:59:08.403002 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9384 22:59:08.409815 ELOG: Event(A0) added with size 9 at 2023-06-05 22:59:01 UTC
9385 22:59:08.412853 elog_add_boot_reason: Logged dev mode boot
9386 22:59:08.416562 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9387 22:59:08.419616 Finalize devices...
9388 22:59:08.422821 Devices finalized
9389 22:59:08.426562 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9390 22:59:08.429764 Writing coreboot table at 0xffe64000
9391 22:59:08.433038 0. 000000000010a000-0000000000113fff: RAMSTAGE
9392 22:59:08.436322 1. 0000000040000000-00000000400fffff: RAM
9393 22:59:08.442689 2. 0000000040100000-000000004032afff: RAMSTAGE
9394 22:59:08.446061 3. 000000004032b000-00000000545fffff: RAM
9395 22:59:08.449307 4. 0000000054600000-000000005465ffff: BL31
9396 22:59:08.452524 5. 0000000054660000-00000000ffe63fff: RAM
9397 22:59:08.459160 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9398 22:59:08.462918 7. 0000000100000000-000000023fffffff: RAM
9399 22:59:08.466203 Passing 5 GPIOs to payload:
9400 22:59:08.469505 NAME | PORT | POLARITY | VALUE
9401 22:59:08.472653 EC in RW | 0x000000aa | low | undefined
9402 22:59:08.479058 EC interrupt | 0x00000005 | low | undefined
9403 22:59:08.482666 TPM interrupt | 0x000000ab | high | undefined
9404 22:59:08.489206 SD card detect | 0x00000011 | high | undefined
9405 22:59:08.492459 speaker enable | 0x00000093 | high | undefined
9406 22:59:08.495672 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9407 22:59:08.499729 in-header: 03 f9 00 00 02 00 00 00
9408 22:59:08.502312 in-data: 02 00
9409 22:59:08.505955 ADC[4]: Raw value=904726 ID=7
9410 22:59:08.509088 ADC[3]: Raw value=213441 ID=1
9411 22:59:08.509164 RAM Code: 0x71
9412 22:59:08.512939 ADC[6]: Raw value=75332 ID=0
9413 22:59:08.515712 ADC[5]: Raw value=213441 ID=1
9414 22:59:08.515797 SKU Code: 0x1
9415 22:59:08.522455 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4e98
9416 22:59:08.522544 coreboot table: 964 bytes.
9417 22:59:08.525503 IMD ROOT 0. 0xfffff000 0x00001000
9418 22:59:08.529099 IMD SMALL 1. 0xffffe000 0x00001000
9419 22:59:08.532135 RO MCACHE 2. 0xffffc000 0x00001104
9420 22:59:08.536008 CONSOLE 3. 0xfff7c000 0x00080000
9421 22:59:08.539267 FMAP 4. 0xfff7b000 0x00000452
9422 22:59:08.542421 TIME STAMP 5. 0xfff7a000 0x00000910
9423 22:59:08.545690 VBOOT WORK 6. 0xfff66000 0x00014000
9424 22:59:08.549032 RAMOOPS 7. 0xffe66000 0x00100000
9425 22:59:08.552415 COREBOOT 8. 0xffe64000 0x00002000
9426 22:59:08.555579 IMD small region:
9427 22:59:08.558838 IMD ROOT 0. 0xffffec00 0x00000400
9428 22:59:08.561956 VPD 1. 0xffffeba0 0x0000004c
9429 22:59:08.565651 MMC STATUS 2. 0xffffeb80 0x00000004
9430 22:59:08.568577 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9431 22:59:08.572432 Probing TPM: done!
9432 22:59:08.575648 Connected to device vid:did:rid of 1ae0:0028:00
9433 22:59:08.586965 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
9434 22:59:08.590122 Initialized TPM device CR50 revision 0
9435 22:59:08.594129 Checking cr50 for pending updates
9436 22:59:08.597494 Reading cr50 TPM mode
9437 22:59:08.606045 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9438 22:59:08.612991 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9439 22:59:08.652862 read SPI 0x3990ec 0x4f1b0: 34852 us, 9296 KB/s, 74.368 Mbps
9440 22:59:08.656189 Checking segment from ROM address 0x40100000
9441 22:59:08.659392 Checking segment from ROM address 0x4010001c
9442 22:59:08.666679 Loading segment from ROM address 0x40100000
9443 22:59:08.666756 code (compression=0)
9444 22:59:08.673441 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9445 22:59:08.683013 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9446 22:59:08.683124 it's not compressed!
9447 22:59:08.689791 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9448 22:59:08.693008 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9449 22:59:08.713573 Loading segment from ROM address 0x4010001c
9450 22:59:08.713659 Entry Point 0x80000000
9451 22:59:08.716883 Loaded segments
9452 22:59:08.720154 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9453 22:59:08.726660 Jumping to boot code at 0x80000000(0xffe64000)
9454 22:59:08.733513 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9455 22:59:08.740129 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9456 22:59:08.748119 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9457 22:59:08.751266 Checking segment from ROM address 0x40100000
9458 22:59:08.754569 Checking segment from ROM address 0x4010001c
9459 22:59:08.761077 Loading segment from ROM address 0x40100000
9460 22:59:08.761188 code (compression=1)
9461 22:59:08.767788 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9462 22:59:08.777932 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9463 22:59:08.778036 using LZMA
9464 22:59:08.785928 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9465 22:59:08.792966 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9466 22:59:08.796254 Loading segment from ROM address 0x4010001c
9467 22:59:08.796339 Entry Point 0x54601000
9468 22:59:08.799265 Loaded segments
9469 22:59:08.802919 NOTICE: MT8192 bl31_setup
9470 22:59:08.809549 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9471 22:59:08.812830 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9472 22:59:08.816559 WARNING: region 0:
9473 22:59:08.819761 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9474 22:59:08.819844 WARNING: region 1:
9475 22:59:08.826455 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9476 22:59:08.829597 WARNING: region 2:
9477 22:59:08.833485 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9478 22:59:08.836737 WARNING: region 3:
9479 22:59:08.839856 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9480 22:59:08.843107 WARNING: region 4:
9481 22:59:08.849462 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9482 22:59:08.849544 WARNING: region 5:
9483 22:59:08.852937 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9484 22:59:08.856627 WARNING: region 6:
9485 22:59:08.859610 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9486 22:59:08.859693 WARNING: region 7:
9487 22:59:08.866870 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9488 22:59:08.873377 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9489 22:59:08.876550 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9490 22:59:08.879917 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9491 22:59:08.886762 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9492 22:59:08.890122 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9493 22:59:08.892947 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9494 22:59:08.899860 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9495 22:59:08.903259 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9496 22:59:08.910040 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9497 22:59:08.913428 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9498 22:59:08.916717 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9499 22:59:08.923269 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9500 22:59:08.926570 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9501 22:59:08.930442 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9502 22:59:08.936766 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9503 22:59:08.940085 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9504 22:59:08.943520 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9505 22:59:08.950117 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9506 22:59:08.953274 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9507 22:59:08.956959 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9508 22:59:08.963224 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9509 22:59:08.966667 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9510 22:59:08.973731 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9511 22:59:08.977080 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9512 22:59:08.980268 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9513 22:59:08.987226 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9514 22:59:08.990499 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9515 22:59:08.996972 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9516 22:59:09.000678 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9517 22:59:09.003806 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9518 22:59:09.010706 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9519 22:59:09.013634 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9520 22:59:09.017072 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9521 22:59:09.023527 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9522 22:59:09.027307 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9523 22:59:09.030653 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9524 22:59:09.033842 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9525 22:59:09.040368 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9526 22:59:09.043597 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9527 22:59:09.046979 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9528 22:59:09.050239 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9529 22:59:09.057147 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9530 22:59:09.060682 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9531 22:59:09.063546 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9532 22:59:09.067110 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9533 22:59:09.073694 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9534 22:59:09.077615 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9535 22:59:09.080821 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9536 22:59:09.087254 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9537 22:59:09.090441 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9538 22:59:09.093612 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9539 22:59:09.100598 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9540 22:59:09.103874 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9541 22:59:09.110251 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9542 22:59:09.113545 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9543 22:59:09.116816 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9544 22:59:09.123786 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9545 22:59:09.127581 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9546 22:59:09.133758 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9547 22:59:09.137052 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9548 22:59:09.143660 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9549 22:59:09.147431 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9550 22:59:09.153900 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9551 22:59:09.157156 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9552 22:59:09.160991 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9553 22:59:09.167105 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9554 22:59:09.170905 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9555 22:59:09.177520 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9556 22:59:09.180586 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9557 22:59:09.184332 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9558 22:59:09.190762 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9559 22:59:09.193986 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9560 22:59:09.201082 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9561 22:59:09.204380 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9562 22:59:09.211009 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9563 22:59:09.214062 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9564 22:59:09.217264 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9565 22:59:09.223774 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9566 22:59:09.227043 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9567 22:59:09.233944 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9568 22:59:09.236965 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9569 22:59:09.243906 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9570 22:59:09.247047 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9571 22:59:09.254076 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9572 22:59:09.256970 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9573 22:59:09.260731 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9574 22:59:09.267221 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9575 22:59:09.270454 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9576 22:59:09.277373 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9577 22:59:09.280326 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9578 22:59:09.287575 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9579 22:59:09.290542 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9580 22:59:09.294126 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9581 22:59:09.300516 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9582 22:59:09.303999 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9583 22:59:09.310680 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9584 22:59:09.313922 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9585 22:59:09.317212 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9586 22:59:09.320486 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9587 22:59:09.327242 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9588 22:59:09.330472 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9589 22:59:09.334359 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9590 22:59:09.340705 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9591 22:59:09.344271 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9592 22:59:09.350882 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9593 22:59:09.354100 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9594 22:59:09.357315 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9595 22:59:09.363786 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9596 22:59:09.367686 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9597 22:59:09.374243 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9598 22:59:09.377474 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9599 22:59:09.380826 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9600 22:59:09.387703 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9601 22:59:09.390590 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9602 22:59:09.397721 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9603 22:59:09.400692 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9604 22:59:09.404455 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9605 22:59:09.407581 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9606 22:59:09.414466 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9607 22:59:09.417652 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9608 22:59:09.421065 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9609 22:59:09.424303 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9610 22:59:09.430999 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9611 22:59:09.434694 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9612 22:59:09.437977 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9613 22:59:09.444652 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9614 22:59:09.447827 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9615 22:59:09.450969 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9616 22:59:09.457591 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9617 22:59:09.461303 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9618 22:59:09.467824 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9619 22:59:09.471125 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9620 22:59:09.474357 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9621 22:59:09.481260 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9622 22:59:09.484621 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9623 22:59:09.491201 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9624 22:59:09.494339 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9625 22:59:09.497924 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9626 22:59:09.504569 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9627 22:59:09.507593 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9628 22:59:09.511083 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9629 22:59:09.517581 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9630 22:59:09.521393 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9631 22:59:09.527887 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9632 22:59:09.531139 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9633 22:59:09.534254 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9634 22:59:09.541486 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9635 22:59:09.544662 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9636 22:59:09.551257 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9637 22:59:09.554762 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9638 22:59:09.557788 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9639 22:59:09.564761 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9640 22:59:09.567788 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9641 22:59:09.571267 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9642 22:59:09.577738 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9643 22:59:09.581633 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9644 22:59:09.588130 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9645 22:59:09.591405 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9646 22:59:09.594662 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9647 22:59:09.600959 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9648 22:59:09.604837 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9649 22:59:09.611060 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9650 22:59:09.614105 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9651 22:59:09.617957 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9652 22:59:09.624122 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9653 22:59:09.627963 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9654 22:59:09.631402 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9655 22:59:09.637596 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9656 22:59:09.640932 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9657 22:59:09.647858 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9658 22:59:09.651161 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9659 22:59:09.654427 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9660 22:59:09.660857 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9661 22:59:09.664109 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9662 22:59:09.671151 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9663 22:59:09.674237 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9664 22:59:09.677744 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9665 22:59:09.684437 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9666 22:59:09.687560 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9667 22:59:09.690853 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9668 22:59:09.697586 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9669 22:59:09.700868 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9670 22:59:09.707217 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9671 22:59:09.711116 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9672 22:59:09.714353 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9673 22:59:09.720839 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9674 22:59:09.723974 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9675 22:59:09.730701 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9676 22:59:09.734188 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9677 22:59:09.737230 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9678 22:59:09.744400 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9679 22:59:09.747573 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9680 22:59:09.753766 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9681 22:59:09.757348 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9682 22:59:09.763790 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9683 22:59:09.767647 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9684 22:59:09.770951 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9685 22:59:09.777459 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9686 22:59:09.780572 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9687 22:59:09.787267 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9688 22:59:09.790887 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9689 22:59:09.794069 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9690 22:59:09.800635 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9691 22:59:09.803925 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9692 22:59:09.810344 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9693 22:59:09.814342 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9694 22:59:09.820576 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9695 22:59:09.823545 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9696 22:59:09.827019 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9697 22:59:09.833622 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9698 22:59:09.837241 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9699 22:59:09.843726 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9700 22:59:09.846943 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9701 22:59:09.853617 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9702 22:59:09.856816 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9703 22:59:09.860442 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9704 22:59:09.866769 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9705 22:59:09.869944 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9706 22:59:09.876591 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9707 22:59:09.879827 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9708 22:59:09.883697 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9709 22:59:09.889912 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9710 22:59:09.893659 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9711 22:59:09.899831 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9712 22:59:09.903037 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9713 22:59:09.910074 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9714 22:59:09.913300 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9715 22:59:09.916431 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9716 22:59:09.923631 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9717 22:59:09.926696 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9718 22:59:09.929825 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9719 22:59:09.933392 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9720 22:59:09.939922 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9721 22:59:09.943008 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9722 22:59:09.946579 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9723 22:59:09.952944 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9724 22:59:09.956317 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9725 22:59:09.959527 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9726 22:59:09.966382 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9727 22:59:09.969531 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9728 22:59:09.973238 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9729 22:59:09.979588 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9730 22:59:09.983024 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9731 22:59:09.986146 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9732 22:59:09.993402 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9733 22:59:09.996581 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9734 22:59:10.002961 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9735 22:59:10.006493 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9736 22:59:10.009701 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9737 22:59:10.016127 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9738 22:59:10.019296 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9739 22:59:10.022584 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9740 22:59:10.029719 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9741 22:59:10.033199 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9742 22:59:10.036367 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9743 22:59:10.042705 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9744 22:59:10.046018 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9745 22:59:10.052694 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9746 22:59:10.056299 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9747 22:59:10.059512 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9748 22:59:10.066073 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9749 22:59:10.069322 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9750 22:59:10.076117 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9751 22:59:10.079759 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9752 22:59:10.082975 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9753 22:59:10.086146 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9754 22:59:10.093210 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9755 22:59:10.096268 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9756 22:59:10.102864 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9757 22:59:10.106023 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9758 22:59:10.109295 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9759 22:59:10.112950 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9760 22:59:10.116065 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9761 22:59:10.122525 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9762 22:59:10.126280 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9763 22:59:10.129446 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9764 22:59:10.132715 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9765 22:59:10.139136 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9766 22:59:10.142939 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9767 22:59:10.146267 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9768 22:59:10.149343 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9769 22:59:10.156083 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9770 22:59:10.159051 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9771 22:59:10.165773 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9772 22:59:10.169545 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9773 22:59:10.172810 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9774 22:59:10.179204 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9775 22:59:10.182948 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9776 22:59:10.189610 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9777 22:59:10.192597 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9778 22:59:10.195746 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9779 22:59:10.202296 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9780 22:59:10.205573 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9781 22:59:10.212081 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9782 22:59:10.215877 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9783 22:59:10.222241 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9784 22:59:10.225973 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9785 22:59:10.229047 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9786 22:59:10.235600 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9787 22:59:10.238841 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9788 22:59:10.245561 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9789 22:59:10.248606 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9790 22:59:10.251934 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9791 22:59:10.258826 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9792 22:59:10.261960 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9793 22:59:10.265696 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9794 22:59:10.272496 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9795 22:59:10.275696 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9796 22:59:10.282236 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9797 22:59:10.285289 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9798 22:59:10.291968 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9799 22:59:10.295576 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9800 22:59:10.298722 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9801 22:59:10.305272 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9802 22:59:10.309100 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9803 22:59:10.315567 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9804 22:59:10.318613 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9805 22:59:10.321919 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9806 22:59:10.328974 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9807 22:59:10.331894 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9808 22:59:10.338814 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9809 22:59:10.342050 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9810 22:59:10.345445 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9811 22:59:10.351846 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9812 22:59:10.355170 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9813 22:59:10.362058 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9814 22:59:10.365266 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9815 22:59:10.372095 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9816 22:59:10.375560 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9817 22:59:10.378551 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9818 22:59:10.385291 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9819 22:59:10.388402 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9820 22:59:10.392147 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9821 22:59:10.398679 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9822 22:59:10.402305 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9823 22:59:10.408546 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9824 22:59:10.411942 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9825 22:59:10.415110 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9826 22:59:10.422087 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9827 22:59:10.425418 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9828 22:59:10.431766 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9829 22:59:10.435607 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9830 22:59:10.441605 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9831 22:59:10.445439 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9832 22:59:10.448676 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9833 22:59:10.455386 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9834 22:59:10.458653 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9835 22:59:10.464897 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9836 22:59:10.468425 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9837 22:59:10.471720 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9838 22:59:10.478358 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9839 22:59:10.482077 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9840 22:59:10.488450 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9841 22:59:10.491835 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9842 22:59:10.495001 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9843 22:59:10.501879 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9844 22:59:10.505046 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9845 22:59:10.511753 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9846 22:59:10.515553 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9847 22:59:10.521871 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9848 22:59:10.525294 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9849 22:59:10.528427 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9850 22:59:10.534832 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9851 22:59:10.538270 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9852 22:59:10.544739 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9853 22:59:10.548333 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9854 22:59:10.554792 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9855 22:59:10.558097 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9856 22:59:10.564599 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9857 22:59:10.568116 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9858 22:59:10.571413 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9859 22:59:10.577832 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9860 22:59:10.581056 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9861 22:59:10.587932 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9862 22:59:10.591518 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9863 22:59:10.598118 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9864 22:59:10.601409 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9865 22:59:10.604509 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9866 22:59:10.610989 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9867 22:59:10.614530 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9868 22:59:10.621292 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9869 22:59:10.624524 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9870 22:59:10.631018 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9871 22:59:10.634422 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9872 22:59:10.640889 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9873 22:59:10.644224 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9874 22:59:10.647522 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9875 22:59:10.653939 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9876 22:59:10.657518 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9877 22:59:10.663926 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9878 22:59:10.667226 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9879 22:59:10.674229 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9880 22:59:10.677432 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9881 22:59:10.680868 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9882 22:59:10.687192 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9883 22:59:10.690859 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9884 22:59:10.696969 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9885 22:59:10.700260 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9886 22:59:10.706873 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9887 22:59:10.710237 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9888 22:59:10.717049 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9889 22:59:10.720263 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9890 22:59:10.723911 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9891 22:59:10.730167 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9892 22:59:10.733793 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9893 22:59:10.740328 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9894 22:59:10.743730 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9895 22:59:10.750140 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9896 22:59:10.753393 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9897 22:59:10.760375 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9898 22:59:10.763706 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9899 22:59:10.766742 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9900 22:59:10.773252 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9901 22:59:10.776967 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9902 22:59:10.783561 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9903 22:59:10.786857 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9904 22:59:10.793350 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9905 22:59:10.797015 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9906 22:59:10.803176 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9907 22:59:10.807108 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9908 22:59:10.813602 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9909 22:59:10.816801 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9910 22:59:10.823224 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9911 22:59:10.826575 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9912 22:59:10.833336 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9913 22:59:10.836372 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9914 22:59:10.843698 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9915 22:59:10.846676 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9916 22:59:10.853127 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9917 22:59:10.856316 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9918 22:59:10.863436 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9919 22:59:10.866624 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9920 22:59:10.873002 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9921 22:59:10.876715 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9922 22:59:10.883597 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9923 22:59:10.883683 INFO: [APUAPC] vio 0
9924 22:59:10.890082 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9925 22:59:10.893279 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9926 22:59:10.896601 INFO: [APUAPC] D0_APC_0: 0x400510
9927 22:59:10.899726 INFO: [APUAPC] D0_APC_1: 0x0
9928 22:59:10.903449 INFO: [APUAPC] D0_APC_2: 0x1540
9929 22:59:10.906481 INFO: [APUAPC] D0_APC_3: 0x0
9930 22:59:10.910025 INFO: [APUAPC] D1_APC_0: 0xffffffff
9931 22:59:10.913448 INFO: [APUAPC] D1_APC_1: 0xffffffff
9932 22:59:10.916528 INFO: [APUAPC] D1_APC_2: 0x3fffff
9933 22:59:10.919810 INFO: [APUAPC] D1_APC_3: 0x0
9934 22:59:10.923061 INFO: [APUAPC] D2_APC_0: 0xffffffff
9935 22:59:10.926205 INFO: [APUAPC] D2_APC_1: 0xffffffff
9936 22:59:10.929575 INFO: [APUAPC] D2_APC_2: 0x3fffff
9937 22:59:10.933447 INFO: [APUAPC] D2_APC_3: 0x0
9938 22:59:10.936735 INFO: [APUAPC] D3_APC_0: 0xffffffff
9939 22:59:10.939764 INFO: [APUAPC] D3_APC_1: 0xffffffff
9940 22:59:10.943311 INFO: [APUAPC] D3_APC_2: 0x3fffff
9941 22:59:10.943435 INFO: [APUAPC] D3_APC_3: 0x0
9942 22:59:10.946474 INFO: [APUAPC] D4_APC_0: 0xffffffff
9943 22:59:10.953014 INFO: [APUAPC] D4_APC_1: 0xffffffff
9944 22:59:10.956300 INFO: [APUAPC] D4_APC_2: 0x3fffff
9945 22:59:10.956421 INFO: [APUAPC] D4_APC_3: 0x0
9946 22:59:10.959513 INFO: [APUAPC] D5_APC_0: 0xffffffff
9947 22:59:10.962763 INFO: [APUAPC] D5_APC_1: 0xffffffff
9948 22:59:10.966003 INFO: [APUAPC] D5_APC_2: 0x3fffff
9949 22:59:10.969785 INFO: [APUAPC] D5_APC_3: 0x0
9950 22:59:10.973222 INFO: [APUAPC] D6_APC_0: 0xffffffff
9951 22:59:10.976365 INFO: [APUAPC] D6_APC_1: 0xffffffff
9952 22:59:10.979587 INFO: [APUAPC] D6_APC_2: 0x3fffff
9953 22:59:10.982769 INFO: [APUAPC] D6_APC_3: 0x0
9954 22:59:10.986394 INFO: [APUAPC] D7_APC_0: 0xffffffff
9955 22:59:10.989598 INFO: [APUAPC] D7_APC_1: 0xffffffff
9956 22:59:10.992880 INFO: [APUAPC] D7_APC_2: 0x3fffff
9957 22:59:10.996098 INFO: [APUAPC] D7_APC_3: 0x0
9958 22:59:10.999495 INFO: [APUAPC] D8_APC_0: 0xffffffff
9959 22:59:11.002709 INFO: [APUAPC] D8_APC_1: 0xffffffff
9960 22:59:11.005986 INFO: [APUAPC] D8_APC_2: 0x3fffff
9961 22:59:11.009735 INFO: [APUAPC] D8_APC_3: 0x0
9962 22:59:11.012914 INFO: [APUAPC] D9_APC_0: 0xffffffff
9963 22:59:11.015859 INFO: [APUAPC] D9_APC_1: 0xffffffff
9964 22:59:11.019677 INFO: [APUAPC] D9_APC_2: 0x3fffff
9965 22:59:11.023000 INFO: [APUAPC] D9_APC_3: 0x0
9966 22:59:11.026334 INFO: [APUAPC] D10_APC_0: 0xffffffff
9967 22:59:11.029429 INFO: [APUAPC] D10_APC_1: 0xffffffff
9968 22:59:11.032748 INFO: [APUAPC] D10_APC_2: 0x3fffff
9969 22:59:11.036008 INFO: [APUAPC] D10_APC_3: 0x0
9970 22:59:11.039196 INFO: [APUAPC] D11_APC_0: 0xffffffff
9971 22:59:11.042526 INFO: [APUAPC] D11_APC_1: 0xffffffff
9972 22:59:11.045822 INFO: [APUAPC] D11_APC_2: 0x3fffff
9973 22:59:11.049001 INFO: [APUAPC] D11_APC_3: 0x0
9974 22:59:11.052656 INFO: [APUAPC] D12_APC_0: 0xffffffff
9975 22:59:11.056068 INFO: [APUAPC] D12_APC_1: 0xffffffff
9976 22:59:11.059276 INFO: [APUAPC] D12_APC_2: 0x3fffff
9977 22:59:11.062237 INFO: [APUAPC] D12_APC_3: 0x0
9978 22:59:11.065747 INFO: [APUAPC] D13_APC_0: 0xffffffff
9979 22:59:11.069112 INFO: [APUAPC] D13_APC_1: 0xffffffff
9980 22:59:11.072318 INFO: [APUAPC] D13_APC_2: 0x3fffff
9981 22:59:11.075698 INFO: [APUAPC] D13_APC_3: 0x0
9982 22:59:11.078962 INFO: [APUAPC] D14_APC_0: 0xffffffff
9983 22:59:11.082284 INFO: [APUAPC] D14_APC_1: 0xffffffff
9984 22:59:11.085967 INFO: [APUAPC] D14_APC_2: 0x3fffff
9985 22:59:11.089010 INFO: [APUAPC] D14_APC_3: 0x0
9986 22:59:11.092275 INFO: [APUAPC] D15_APC_0: 0xffffffff
9987 22:59:11.095842 INFO: [APUAPC] D15_APC_1: 0xffffffff
9988 22:59:11.099071 INFO: [APUAPC] D15_APC_2: 0x3fffff
9989 22:59:11.102478 INFO: [APUAPC] D15_APC_3: 0x0
9990 22:59:11.105822 INFO: [APUAPC] APC_CON: 0x4
9991 22:59:11.109053 INFO: [NOCDAPC] D0_APC_0: 0x0
9992 22:59:11.112206 INFO: [NOCDAPC] D0_APC_1: 0x0
9993 22:59:11.115963 INFO: [NOCDAPC] D1_APC_0: 0x0
9994 22:59:11.118942 INFO: [NOCDAPC] D1_APC_1: 0xfff
9995 22:59:11.119051 INFO: [NOCDAPC] D2_APC_0: 0x0
9996 22:59:11.121991 INFO: [NOCDAPC] D2_APC_1: 0xfff
9997 22:59:11.125563 INFO: [NOCDAPC] D3_APC_0: 0x0
9998 22:59:11.128810 INFO: [NOCDAPC] D3_APC_1: 0xfff
9999 22:59:11.132096 INFO: [NOCDAPC] D4_APC_0: 0x0
10000 22:59:11.135410 INFO: [NOCDAPC] D4_APC_1: 0xfff
10001 22:59:11.138631 INFO: [NOCDAPC] D5_APC_0: 0x0
10002 22:59:11.142414 INFO: [NOCDAPC] D5_APC_1: 0xfff
10003 22:59:11.145676 INFO: [NOCDAPC] D6_APC_0: 0x0
10004 22:59:11.149024 INFO: [NOCDAPC] D6_APC_1: 0xfff
10005 22:59:11.152444 INFO: [NOCDAPC] D7_APC_0: 0x0
10006 22:59:11.152520 INFO: [NOCDAPC] D7_APC_1: 0xfff
10007 22:59:11.155633 INFO: [NOCDAPC] D8_APC_0: 0x0
10008 22:59:11.158766 INFO: [NOCDAPC] D8_APC_1: 0xfff
10009 22:59:11.161803 INFO: [NOCDAPC] D9_APC_0: 0x0
10010 22:59:11.165612 INFO: [NOCDAPC] D9_APC_1: 0xfff
10011 22:59:11.168850 INFO: [NOCDAPC] D10_APC_0: 0x0
10012 22:59:11.172238 INFO: [NOCDAPC] D10_APC_1: 0xfff
10013 22:59:11.175410 INFO: [NOCDAPC] D11_APC_0: 0x0
10014 22:59:11.178370 INFO: [NOCDAPC] D11_APC_1: 0xfff
10015 22:59:11.182264 INFO: [NOCDAPC] D12_APC_0: 0x0
10016 22:59:11.185513 INFO: [NOCDAPC] D12_APC_1: 0xfff
10017 22:59:11.188764 INFO: [NOCDAPC] D13_APC_0: 0x0
10018 22:59:11.192049 INFO: [NOCDAPC] D13_APC_1: 0xfff
10019 22:59:11.192154 INFO: [NOCDAPC] D14_APC_0: 0x0
10020 22:59:11.195172 INFO: [NOCDAPC] D14_APC_1: 0xfff
10021 22:59:11.198364 INFO: [NOCDAPC] D15_APC_0: 0x0
10022 22:59:11.202140 INFO: [NOCDAPC] D15_APC_1: 0xfff
10023 22:59:11.205496 INFO: [NOCDAPC] APC_CON: 0x4
10024 22:59:11.208831 INFO: [APUAPC] set_apusys_apc done
10025 22:59:11.212044 INFO: [DEVAPC] devapc_init done
10026 22:59:11.215444 INFO: GICv3 without legacy support detected.
10027 22:59:11.222185 INFO: ARM GICv3 driver initialized in EL3
10028 22:59:11.225438 INFO: Maximum SPI INTID supported: 639
10029 22:59:11.228364 INFO: BL31: Initializing runtime services
10030 22:59:11.235200 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10031 22:59:11.235309 INFO: SPM: enable CPC mode
10032 22:59:11.242278 INFO: mcdi ready for mcusys-off-idle and system suspend
10033 22:59:11.245586 INFO: BL31: Preparing for EL3 exit to normal world
10034 22:59:11.248832 INFO: Entry point address = 0x80000000
10035 22:59:11.252196 INFO: SPSR = 0x8
10036 22:59:11.258064
10037 22:59:11.258168
10038 22:59:11.258277
10039 22:59:11.261104 Starting depthcharge on Spherion...
10040 22:59:11.261209
10041 22:59:11.261303 Wipe memory regions:
10042 22:59:11.261392
10043 22:59:11.262104 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10044 22:59:11.262239 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10045 22:59:11.262363 Setting prompt string to ['asurada:']
10046 22:59:11.262476 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10047 22:59:11.264355 [0x00000040000000, 0x00000054600000)
10048 22:59:11.386369
10049 22:59:11.386535 [0x00000054660000, 0x00000080000000)
10050 22:59:11.647332
10051 22:59:11.647490 [0x000000821a7280, 0x000000ffe64000)
10052 22:59:12.391588
10053 22:59:12.391762 [0x00000100000000, 0x00000240000000)
10054 22:59:14.281293
10055 22:59:14.284473 Initializing XHCI USB controller at 0x11200000.
10056 22:59:15.323472
10057 22:59:15.326616 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10058 22:59:15.326720
10059 22:59:15.326797
10060 22:59:15.326861
10061 22:59:15.327157 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10063 22:59:15.427588 asurada: tftpboot 192.168.201.1 10597675/tftp-deploy-5qtcemid/kernel/image.itb 10597675/tftp-deploy-5qtcemid/kernel/cmdline
10064 22:59:15.427781 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10065 22:59:15.427923 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10066 22:59:15.432377 tftpboot 192.168.201.1 10597675/tftp-deploy-5qtcemid/kernel/image.ittp-deploy-5qtcemid/kernel/cmdline
10067 22:59:15.432465
10068 22:59:15.432542 Waiting for link
10069 22:59:15.593461
10070 22:59:15.593635 R8152: Initializing
10071 22:59:15.593722
10072 22:59:15.596338 Version 9 (ocp_data = 6010)
10073 22:59:15.596414
10074 22:59:15.599860 R8152: Done initializing
10075 22:59:15.599954
10076 22:59:15.600018 Adding net device
10077 22:59:17.545185
10078 22:59:17.545367 done.
10079 22:59:17.545443
10080 22:59:17.545509 MAC: 00:e0:4c:78:7a:aa
10081 22:59:17.545587
10082 22:59:17.548414 Sending DHCP discover... done.
10083 22:59:17.548501
10084 22:59:17.551709 Waiting for reply... done.
10085 22:59:17.551807
10086 22:59:17.554987 Sending DHCP request... done.
10087 22:59:17.555093
10088 22:59:17.560253 Waiting for reply... done.
10089 22:59:17.560337
10090 22:59:17.560427 My ip is 192.168.201.12
10091 22:59:17.560496
10092 22:59:17.563329 The DHCP server ip is 192.168.201.1
10093 22:59:17.563426
10094 22:59:17.569825 TFTP server IP predefined by user: 192.168.201.1
10095 22:59:17.569919
10096 22:59:17.576564 Bootfile predefined by user: 10597675/tftp-deploy-5qtcemid/kernel/image.itb
10097 22:59:17.576647
10098 22:59:17.576714 Sending tftp read request... done.
10099 22:59:17.579559
10100 22:59:17.583428 Waiting for the transfer...
10101 22:59:17.583534
10102 22:59:17.852757 00000000 ################################################################
10103 22:59:17.852944
10104 22:59:18.109353 00080000 ################################################################
10105 22:59:18.109542
10106 22:59:18.373742 00100000 ################################################################
10107 22:59:18.373895
10108 22:59:18.630994 00180000 ################################################################
10109 22:59:18.631177
10110 22:59:18.886111 00200000 ################################################################
10111 22:59:18.886297
10112 22:59:19.148336 00280000 ################################################################
10113 22:59:19.148524
10114 22:59:19.401356 00300000 ################################################################
10115 22:59:19.401540
10116 22:59:19.655886 00380000 ################################################################
10117 22:59:19.656074
10118 22:59:19.910414 00400000 ################################################################
10119 22:59:19.910601
10120 22:59:20.165248 00480000 ################################################################
10121 22:59:20.165438
10122 22:59:20.419603 00500000 ################################################################
10123 22:59:20.419758
10124 22:59:20.676330 00580000 ################################################################
10125 22:59:20.676540
10126 22:59:20.932665 00600000 ################################################################
10127 22:59:20.932871
10128 22:59:21.190786 00680000 ################################################################
10129 22:59:21.190983
10130 22:59:21.440983 00700000 ################################################################
10131 22:59:21.441155
10132 22:59:21.685346 00780000 ################################################################
10133 22:59:21.685527
10134 22:59:21.930490 00800000 ################################################################
10135 22:59:21.930672
10136 22:59:22.176683 00880000 ################################################################
10137 22:59:22.176862
10138 22:59:22.428170 00900000 ################################################################
10139 22:59:22.428327
10140 22:59:22.703958 00980000 ################################################################
10141 22:59:22.704127
10142 22:59:22.989413 00a00000 ################################################################
10143 22:59:22.989582
10144 22:59:23.253484 00a80000 ################################################################
10145 22:59:23.253631
10146 22:59:23.513068 00b00000 ################################################################
10147 22:59:23.513252
10148 22:59:23.771596 00b80000 ################################################################
10149 22:59:23.771782
10150 22:59:24.030490 00c00000 ################################################################
10151 22:59:24.030645
10152 22:59:24.288232 00c80000 ################################################################
10153 22:59:24.288386
10154 22:59:24.549835 00d00000 ################################################################
10155 22:59:24.549995
10156 22:59:24.800470 00d80000 ################################################################
10157 22:59:24.800687
10158 22:59:25.045731 00e00000 ################################################################
10159 22:59:25.045957
10160 22:59:25.288670 00e80000 ################################################################
10161 22:59:25.288871
10162 22:59:25.533855 00f00000 ################################################################
10163 22:59:25.534038
10164 22:59:25.778768 00f80000 ################################################################
10165 22:59:25.778976
10166 22:59:26.029564 01000000 ################################################################
10167 22:59:26.029746
10168 22:59:26.286248 01080000 ################################################################
10169 22:59:26.286401
10170 22:59:26.544915 01100000 ################################################################
10171 22:59:26.545110
10172 22:59:26.807076 01180000 ################################################################
10173 22:59:26.807272
10174 22:59:27.066497 01200000 ################################################################
10175 22:59:27.066662
10176 22:59:27.318937 01280000 ################################################################
10177 22:59:27.319085
10178 22:59:27.574866 01300000 ################################################################
10179 22:59:27.575063
10180 22:59:27.829331 01380000 ################################################################
10181 22:59:27.829491
10182 22:59:28.092750 01400000 ################################################################
10183 22:59:28.092906
10184 22:59:28.350480 01480000 ################################################################
10185 22:59:28.350645
10186 22:59:28.607005 01500000 ################################################################
10187 22:59:28.607174
10188 22:59:28.875642 01580000 ################################################################
10189 22:59:28.875823
10190 22:59:29.126372 01600000 ################################################################
10191 22:59:29.126550
10192 22:59:29.383859 01680000 ################################################################
10193 22:59:29.384028
10194 22:59:29.641084 01700000 ################################################################
10195 22:59:29.641263
10196 22:59:29.905391 01780000 ################################################################
10197 22:59:29.905588
10198 22:59:30.165339 01800000 ################################################################
10199 22:59:30.165519
10200 22:59:30.414588 01880000 ################################################################
10201 22:59:30.414768
10202 22:59:30.683495 01900000 ################################################################
10203 22:59:30.683648
10204 22:59:30.941842 01980000 ################################################################
10205 22:59:30.942020
10206 22:59:31.195418 01a00000 ############################################################### done.
10207 22:59:31.195596
10208 22:59:31.198674 The bootfile was 27777182 bytes long.
10209 22:59:31.198762
10210 22:59:31.198836 Sending tftp read request... done.
10211 22:59:31.202038
10212 22:59:31.202145 Waiting for the transfer...
10213 22:59:31.202252
10214 22:59:31.205615 00000000 # done.
10215 22:59:31.205732
10216 22:59:31.212546 Command line loaded dynamically from TFTP file: 10597675/tftp-deploy-5qtcemid/kernel/cmdline
10217 22:59:31.212657
10218 22:59:31.232360 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10597675/extract-nfsrootfs-rk96f8r0,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10219 22:59:31.232486
10220 22:59:31.232571 Loading FIT.
10221 22:59:31.235180
10222 22:59:31.235284 Image ramdisk-1 has 17642277 bytes.
10223 22:59:31.238292
10224 22:59:31.238383 Image fdt-1 has 46924 bytes.
10225 22:59:31.238450
10226 22:59:31.241673 Image kernel-1 has 10085945 bytes.
10227 22:59:31.241781
10228 22:59:31.252289 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10229 22:59:31.252403
10230 22:59:31.268828 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10231 22:59:31.268961
10232 22:59:31.275497 Choosing best match conf-1 for compat google,spherion-rev2.
10233 22:59:31.275585
10234 22:59:31.283209 Connected to device vid:did:rid of 1ae0:0028:00
10235 22:59:31.291685
10236 22:59:31.294930 tpm_get_response: command 0x17b, return code 0x0
10237 22:59:31.295036
10238 22:59:31.298209 ec_init: CrosEC protocol v3 supported (256, 248)
10239 22:59:31.302111
10240 22:59:31.305395 tpm_cleanup: add release locality here.
10241 22:59:31.305505
10242 22:59:31.305607 Shutting down all USB controllers.
10243 22:59:31.308525
10244 22:59:31.308633 Removing current net device
10245 22:59:31.308731
10246 22:59:31.315454 Exiting depthcharge with code 4 at timestamp: 49327978
10247 22:59:31.315543
10248 22:59:31.318677 LZMA decompressing kernel-1 to 0x821a6718
10249 22:59:31.318782
10250 22:59:31.322135 LZMA decompressing kernel-1 to 0x40000000
10251 22:59:32.588855
10252 22:59:32.589015 jumping to kernel
10253 22:59:32.589423 end: 2.2.4 bootloader-commands (duration 00:00:21) [common]
10254 22:59:32.589523 start: 2.2.5 auto-login-action (timeout 00:04:04) [common]
10255 22:59:32.589605 Setting prompt string to ['Linux version [0-9]']
10256 22:59:32.589677 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10257 22:59:32.589748 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10258 22:59:32.671010
10259 22:59:32.674130 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10260 22:59:32.677439 start: 2.2.5.1 login-action (timeout 00:04:04) [common]
10261 22:59:32.677534 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10262 22:59:32.677628 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10263 22:59:32.677705 Using line separator: #'\n'#
10264 22:59:32.677767 No login prompt set.
10265 22:59:32.677832 Parsing kernel messages
10266 22:59:32.677897 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10267 22:59:32.678006 [login-action] Waiting for messages, (timeout 00:04:04)
10268 22:59:32.697455 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1612582-arm64-gcc-10-defconfig-arm64-chromebook-7xwc5) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 22:41:02 UTC 2023
10269 22:59:32.700803 [ 0.000000] random: crng init done
10270 22:59:32.704017 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10271 22:59:32.707192 [ 0.000000] efi: UEFI not found.
10272 22:59:32.717227 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10273 22:59:32.723626 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10274 22:59:32.734153 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10275 22:59:32.743598 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10276 22:59:32.750622 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10277 22:59:32.753702 [ 0.000000] printk: bootconsole [mtk8250] enabled
10278 22:59:32.762609 [ 0.000000] NUMA: No NUMA configuration found
10279 22:59:32.768824 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10280 22:59:32.775590 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10281 22:59:32.775705 [ 0.000000] Zone ranges:
10282 22:59:32.782311 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10283 22:59:32.785543 [ 0.000000] DMA32 empty
10284 22:59:32.792492 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10285 22:59:32.795465 [ 0.000000] Movable zone start for each node
10286 22:59:32.798545 [ 0.000000] Early memory node ranges
10287 22:59:32.805721 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10288 22:59:32.812274 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10289 22:59:32.818782 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10290 22:59:32.825143 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10291 22:59:32.832227 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10292 22:59:32.838648 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10293 22:59:32.894625 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10294 22:59:32.901533 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10295 22:59:32.907807 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10296 22:59:32.911071 [ 0.000000] psci: probing for conduit method from DT.
10297 22:59:32.918156 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10298 22:59:32.921393 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10299 22:59:32.927901 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10300 22:59:32.931248 [ 0.000000] psci: SMC Calling Convention v1.2
10301 22:59:32.937779 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10302 22:59:32.941135 [ 0.000000] Detected VIPT I-cache on CPU0
10303 22:59:32.947583 [ 0.000000] CPU features: detected: GIC system register CPU interface
10304 22:59:32.954724 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10305 22:59:32.960966 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10306 22:59:32.967991 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10307 22:59:32.974727 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10308 22:59:32.981086 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10309 22:59:32.987878 [ 0.000000] alternatives: applying boot alternatives
10310 22:59:32.991614 [ 0.000000] Fallback order for Node 0: 0
10311 22:59:32.997749 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10312 22:59:33.001525 [ 0.000000] Policy zone: Normal
10313 22:59:33.024632 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10597675/extract-nfsrootfs-rk96f8r0,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10314 22:59:33.034286 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10315 22:59:33.044743 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10316 22:59:33.054299 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10317 22:59:33.060822 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10318 22:59:33.064021 <6>[ 0.000000] software IO TLB: area num 8.
10319 22:59:33.120706 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10320 22:59:33.269683 <6>[ 0.000000] Memory: 7955716K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397052K reserved, 32768K cma-reserved)
10321 22:59:33.276731 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10322 22:59:33.282988 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10323 22:59:33.286694 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10324 22:59:33.293065 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10325 22:59:33.299767 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10326 22:59:33.303042 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10327 22:59:33.312852 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10328 22:59:33.319705 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10329 22:59:33.323231 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10330 22:59:33.330761 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10331 22:59:33.334415 <6>[ 0.000000] GICv3: 608 SPIs implemented
10332 22:59:33.341147 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10333 22:59:33.343946 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10334 22:59:33.347642 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10335 22:59:33.357468 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10336 22:59:33.367471 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10337 22:59:33.380615 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10338 22:59:33.387040 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10339 22:59:33.396389 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10340 22:59:33.409956 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10341 22:59:33.416500 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10342 22:59:33.422939 <6>[ 0.009232] Console: colour dummy device 80x25
10343 22:59:33.432778 <6>[ 0.013957] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10344 22:59:33.436436 <6>[ 0.024399] pid_max: default: 32768 minimum: 301
10345 22:59:33.443266 <6>[ 0.029266] LSM: Security Framework initializing
10346 22:59:33.449395 <6>[ 0.034206] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10347 22:59:33.459899 <6>[ 0.042020] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10348 22:59:33.466357 <6>[ 0.051450] cblist_init_generic: Setting adjustable number of callback queues.
10349 22:59:33.472762 <6>[ 0.058950] cblist_init_generic: Setting shift to 3 and lim to 1.
10350 22:59:33.479353 <6>[ 0.065290] cblist_init_generic: Setting shift to 3 and lim to 1.
10351 22:59:33.486445 <6>[ 0.071698] rcu: Hierarchical SRCU implementation.
10352 22:59:33.489599 <6>[ 0.076711] rcu: Max phase no-delay instances is 1000.
10353 22:59:33.497252 <6>[ 0.083731] EFI services will not be available.
10354 22:59:33.500958 <6>[ 0.088728] smp: Bringing up secondary CPUs ...
10355 22:59:33.509662 <6>[ 0.093781] Detected VIPT I-cache on CPU1
10356 22:59:33.516442 <6>[ 0.093853] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10357 22:59:33.523116 <6>[ 0.093885] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10358 22:59:33.526499 <6>[ 0.094220] Detected VIPT I-cache on CPU2
10359 22:59:33.533550 <6>[ 0.094272] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10360 22:59:33.540005 <6>[ 0.094288] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10361 22:59:33.546364 <6>[ 0.094552] Detected VIPT I-cache on CPU3
10362 22:59:33.553260 <6>[ 0.094600] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10363 22:59:33.559478 <6>[ 0.094614] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10364 22:59:33.563232 <6>[ 0.094922] CPU features: detected: Spectre-v4
10365 22:59:33.569654 <6>[ 0.094929] CPU features: detected: Spectre-BHB
10366 22:59:33.572923 <6>[ 0.094935] Detected PIPT I-cache on CPU4
10367 22:59:33.579318 <6>[ 0.094993] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10368 22:59:33.586644 <6>[ 0.095010] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10369 22:59:33.592682 <6>[ 0.095303] Detected PIPT I-cache on CPU5
10370 22:59:33.599231 <6>[ 0.095365] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10371 22:59:33.606295 <6>[ 0.095382] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10372 22:59:33.609285 <6>[ 0.095669] Detected PIPT I-cache on CPU6
10373 22:59:33.615960 <6>[ 0.095734] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10374 22:59:33.622524 <6>[ 0.095750] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10375 22:59:33.626453 <6>[ 0.096048] Detected PIPT I-cache on CPU7
10376 22:59:33.636147 <6>[ 0.096113] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10377 22:59:33.642483 <6>[ 0.096129] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10378 22:59:33.646150 <6>[ 0.096176] smp: Brought up 1 node, 8 CPUs
10379 22:59:33.649202 <6>[ 0.237524] SMP: Total of 8 processors activated.
10380 22:59:33.656070 <6>[ 0.242445] CPU features: detected: 32-bit EL0 Support
10381 22:59:33.665877 <6>[ 0.247809] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10382 22:59:33.673151 <6>[ 0.256609] CPU features: detected: Common not Private translations
10383 22:59:33.676438 <6>[ 0.263085] CPU features: detected: CRC32 instructions
10384 22:59:33.682764 <6>[ 0.268469] CPU features: detected: RCpc load-acquire (LDAPR)
10385 22:59:33.689359 <6>[ 0.274429] CPU features: detected: LSE atomic instructions
10386 22:59:33.695729 <6>[ 0.280210] CPU features: detected: Privileged Access Never
10387 22:59:33.699137 <6>[ 0.285990] CPU features: detected: RAS Extension Support
10388 22:59:33.705649 <6>[ 0.291598] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10389 22:59:33.712779 <6>[ 0.298849] CPU: All CPU(s) started at EL2
10390 22:59:33.719103 <6>[ 0.303166] alternatives: applying system-wide alternatives
10391 22:59:33.727072 <6>[ 0.313873] devtmpfs: initialized
10392 22:59:33.739590 <6>[ 0.322781] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10393 22:59:33.749479 <6>[ 0.332746] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10394 22:59:33.756117 <6>[ 0.340979] pinctrl core: initialized pinctrl subsystem
10395 22:59:33.760058 <6>[ 0.347603] DMI not present or invalid.
10396 22:59:33.766203 <6>[ 0.352009] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10397 22:59:33.775845 <6>[ 0.358899] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10398 22:59:33.782789 <6>[ 0.366485] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10399 22:59:33.792929 <6>[ 0.374714] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10400 22:59:33.796134 <6>[ 0.382956] audit: initializing netlink subsys (disabled)
10401 22:59:33.806294 <5>[ 0.388651] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10402 22:59:33.812757 <6>[ 0.389348] thermal_sys: Registered thermal governor 'step_wise'
10403 22:59:33.819319 <6>[ 0.396617] thermal_sys: Registered thermal governor 'power_allocator'
10404 22:59:33.822485 <6>[ 0.402873] cpuidle: using governor menu
10405 22:59:33.829398 <6>[ 0.413830] NET: Registered PF_QIPCRTR protocol family
10406 22:59:33.835956 <6>[ 0.419318] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10407 22:59:33.839083 <6>[ 0.426418] ASID allocator initialised with 32768 entries
10408 22:59:33.846308 <6>[ 0.432967] Serial: AMBA PL011 UART driver
10409 22:59:33.855472 <4>[ 0.441569] Trying to register duplicate clock ID: 134
10410 22:59:33.909097 <6>[ 0.498597] KASLR enabled
10411 22:59:33.923484 <6>[ 0.506285] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10412 22:59:33.929395 <6>[ 0.513298] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10413 22:59:33.936597 <6>[ 0.519787] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10414 22:59:33.942798 <6>[ 0.526790] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10415 22:59:33.949326 <6>[ 0.533279] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10416 22:59:33.956284 <6>[ 0.540283] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10417 22:59:33.962493 <6>[ 0.546770] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10418 22:59:33.969590 <6>[ 0.553772] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10419 22:59:33.972767 <6>[ 0.561249] ACPI: Interpreter disabled.
10420 22:59:33.981147 <6>[ 0.567670] iommu: Default domain type: Translated
10421 22:59:33.987975 <6>[ 0.572784] iommu: DMA domain TLB invalidation policy: strict mode
10422 22:59:33.991094 <5>[ 0.579448] SCSI subsystem initialized
10423 22:59:33.997868 <6>[ 0.583682] usbcore: registered new interface driver usbfs
10424 22:59:34.004693 <6>[ 0.589411] usbcore: registered new interface driver hub
10425 22:59:34.007816 <6>[ 0.594965] usbcore: registered new device driver usb
10426 22:59:34.014996 <6>[ 0.601065] pps_core: LinuxPPS API ver. 1 registered
10427 22:59:34.024738 <6>[ 0.606259] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10428 22:59:34.027964 <6>[ 0.615600] PTP clock support registered
10429 22:59:34.031237 <6>[ 0.619838] EDAC MC: Ver: 3.0.0
10430 22:59:34.038996 <6>[ 0.625009] FPGA manager framework
10431 22:59:34.045434 <6>[ 0.628686] Advanced Linux Sound Architecture Driver Initialized.
10432 22:59:34.048558 <6>[ 0.635450] vgaarb: loaded
10433 22:59:34.055128 <6>[ 0.638622] clocksource: Switched to clocksource arch_sys_counter
10434 22:59:34.058171 <5>[ 0.645070] VFS: Disk quotas dquot_6.6.0
10435 22:59:34.064952 <6>[ 0.649255] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10436 22:59:34.068467 <6>[ 0.656448] pnp: PnP ACPI: disabled
10437 22:59:34.076940 <6>[ 0.663151] NET: Registered PF_INET protocol family
10438 22:59:34.086678 <6>[ 0.668747] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10439 22:59:34.098064 <6>[ 0.681089] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10440 22:59:34.108245 <6>[ 0.689904] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10441 22:59:34.114854 <6>[ 0.697874] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10442 22:59:34.121424 <6>[ 0.706573] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10443 22:59:34.133494 <6>[ 0.716309] TCP: Hash tables configured (established 65536 bind 65536)
10444 22:59:34.139631 <6>[ 0.723166] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10445 22:59:34.146295 <6>[ 0.730363] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10446 22:59:34.152929 <6>[ 0.738062] NET: Registered PF_UNIX/PF_LOCAL protocol family
10447 22:59:34.159747 <6>[ 0.744220] RPC: Registered named UNIX socket transport module.
10448 22:59:34.163399 <6>[ 0.750373] RPC: Registered udp transport module.
10449 22:59:34.169537 <6>[ 0.755303] RPC: Registered tcp transport module.
10450 22:59:34.176384 <6>[ 0.760234] RPC: Registered tcp NFSv4.1 backchannel transport module.
10451 22:59:34.179668 <6>[ 0.766902] PCI: CLS 0 bytes, default 64
10452 22:59:34.182778 <6>[ 0.771281] Unpacking initramfs...
10453 22:59:34.200091 <6>[ 0.783166] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10454 22:59:34.210014 <6>[ 0.791824] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10455 22:59:34.213184 <6>[ 0.800621] kvm [1]: IPA Size Limit: 40 bits
10456 22:59:34.219717 <6>[ 0.805150] kvm [1]: GICv3: no GICV resource entry
10457 22:59:34.223549 <6>[ 0.810169] kvm [1]: disabling GICv2 emulation
10458 22:59:34.230112 <6>[ 0.814855] kvm [1]: GIC system register CPU interface enabled
10459 22:59:34.233297 <6>[ 0.821019] kvm [1]: vgic interrupt IRQ18
10460 22:59:34.239835 <6>[ 0.825390] kvm [1]: VHE mode initialized successfully
10461 22:59:34.246905 <5>[ 0.831774] Initialise system trusted keyrings
10462 22:59:34.252861 <6>[ 0.836587] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10463 22:59:34.260062 <6>[ 0.846604] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10464 22:59:34.266943 <5>[ 0.852987] NFS: Registering the id_resolver key type
10465 22:59:34.269984 <5>[ 0.858297] Key type id_resolver registered
10466 22:59:34.276767 <5>[ 0.862712] Key type id_legacy registered
10467 22:59:34.283506 <6>[ 0.866987] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10468 22:59:34.290211 <6>[ 0.873905] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10469 22:59:34.296486 <6>[ 0.881617] 9p: Installing v9fs 9p2000 file system support
10470 22:59:34.333581 <5>[ 0.919814] Key type asymmetric registered
10471 22:59:34.336888 <5>[ 0.924147] Asymmetric key parser 'x509' registered
10472 22:59:34.346691 <6>[ 0.929289] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10473 22:59:34.349872 <6>[ 0.936901] io scheduler mq-deadline registered
10474 22:59:34.353166 <6>[ 0.941675] io scheduler kyber registered
10475 22:59:34.372209 <6>[ 0.958486] EINJ: ACPI disabled.
10476 22:59:34.403665 <4>[ 0.983625] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10477 22:59:34.413328 <4>[ 0.994255] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10478 22:59:34.428290 <6>[ 1.014847] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10479 22:59:34.436405 <6>[ 1.022842] printk: console [ttyS0] disabled
10480 22:59:34.464512 <6>[ 1.047512] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10481 22:59:34.470954 <6>[ 1.057006] printk: console [ttyS0] enabled
10482 22:59:34.474164 <6>[ 1.057006] printk: console [ttyS0] enabled
10483 22:59:34.480740 <6>[ 1.065903] printk: bootconsole [mtk8250] disabled
10484 22:59:34.484406 <6>[ 1.065903] printk: bootconsole [mtk8250] disabled
10485 22:59:34.491052 <6>[ 1.077107] SuperH (H)SCI(F) driver initialized
10486 22:59:34.494222 <6>[ 1.082371] msm_serial: driver initialized
10487 22:59:34.508209 <6>[ 1.091284] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10488 22:59:34.517974 <6>[ 1.099827] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10489 22:59:34.524519 <6>[ 1.108368] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10490 22:59:34.534792 <6>[ 1.116995] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10491 22:59:34.541655 <6>[ 1.125700] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10492 22:59:34.551292 <6>[ 1.134414] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10493 22:59:34.561145 <6>[ 1.142954] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10494 22:59:34.567692 <6>[ 1.151753] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10495 22:59:34.577891 <6>[ 1.160294] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10496 22:59:34.589439 <6>[ 1.175751] loop: module loaded
10497 22:59:34.595706 <6>[ 1.181850] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10498 22:59:34.618436 <4>[ 1.205025] mtk-pmic-keys: Failed to locate of_node [id: -1]
10499 22:59:34.625527 <6>[ 1.211742] megasas: 07.719.03.00-rc1
10500 22:59:34.634448 <6>[ 1.221186] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10501 22:59:34.647818 <6>[ 1.234003] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10502 22:59:34.664291 <6>[ 1.250812] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10503 22:59:34.721615 <6>[ 1.301563] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9
10504 22:59:34.914140 <6>[ 1.500774] Freeing initrd memory: 17224K
10505 22:59:34.924278 <6>[ 1.510762] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10506 22:59:34.935557 <6>[ 1.521589] tun: Universal TUN/TAP device driver, 1.6
10507 22:59:34.938338 <6>[ 1.527642] thunder_xcv, ver 1.0
10508 22:59:34.941990 <6>[ 1.531147] thunder_bgx, ver 1.0
10509 22:59:34.945099 <6>[ 1.534646] nicpf, ver 1.0
10510 22:59:34.955305 <6>[ 1.538645] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10511 22:59:34.958737 <6>[ 1.546118] hns3: Copyright (c) 2017 Huawei Corporation.
10512 22:59:34.962414 <6>[ 1.551705] hclge is initializing
10513 22:59:34.968771 <6>[ 1.555285] e1000: Intel(R) PRO/1000 Network Driver
10514 22:59:34.975637 <6>[ 1.560414] e1000: Copyright (c) 1999-2006 Intel Corporation.
10515 22:59:34.978795 <6>[ 1.566425] e1000e: Intel(R) PRO/1000 Network Driver
10516 22:59:34.985517 <6>[ 1.571641] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10517 22:59:34.992191 <6>[ 1.577829] igb: Intel(R) Gigabit Ethernet Network Driver
10518 22:59:34.999151 <6>[ 1.583479] igb: Copyright (c) 2007-2014 Intel Corporation.
10519 22:59:35.005650 <6>[ 1.589315] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10520 22:59:35.009046 <6>[ 1.595833] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10521 22:59:35.015846 <6>[ 1.602288] sky2: driver version 1.30
10522 22:59:35.022382 <6>[ 1.607274] VFIO - User Level meta-driver version: 0.3
10523 22:59:35.028763 <6>[ 1.615476] usbcore: registered new interface driver usb-storage
10524 22:59:35.035614 <6>[ 1.621917] usbcore: registered new device driver onboard-usb-hub
10525 22:59:35.044852 <6>[ 1.631002] mt6397-rtc mt6359-rtc: registered as rtc0
10526 22:59:35.054326 <6>[ 1.636467] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T22:59:27 UTC (1686005967)
10527 22:59:35.057978 <6>[ 1.646024] i2c_dev: i2c /dev entries driver
10528 22:59:35.074325 <6>[ 1.657640] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10529 22:59:35.081157 <6>[ 1.667823] sdhci: Secure Digital Host Controller Interface driver
10530 22:59:35.087970 <6>[ 1.674261] sdhci: Copyright(c) Pierre Ossman
10531 22:59:35.094903 <6>[ 1.679648] Synopsys Designware Multimedia Card Interface Driver
10532 22:59:35.098166 <6>[ 1.686247] mmc0: CQHCI version 5.10
10533 22:59:35.104549 <6>[ 1.686809] sdhci-pltfm: SDHCI platform and OF driver helper
10534 22:59:35.111279 <6>[ 1.698098] ledtrig-cpu: registered to indicate activity on CPUs
10535 22:59:35.122378 <6>[ 1.705384] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10536 22:59:35.125562 <6>[ 1.712772] usbcore: registered new interface driver usbhid
10537 22:59:35.132055 <6>[ 1.718602] usbhid: USB HID core driver
10538 22:59:35.139008 <6>[ 1.722848] spi_master spi0: will run message pump with realtime priority
10539 22:59:35.184796 <6>[ 1.764998] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10540 22:59:35.204795 <6>[ 1.780937] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10541 22:59:35.208205 <6>[ 1.794520] mmc0: Command Queue Engine enabled
10542 22:59:35.215305 <6>[ 1.796599] cros-ec-spi spi0.0: Chrome EC device registered
10543 22:59:35.218736 <6>[ 1.799257] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10544 22:59:35.225702 <6>[ 1.812526] mmcblk0: mmc0:0001 DA4128 116 GiB
10545 22:59:35.238828 <6>[ 1.822212] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10546 22:59:35.245847 <6>[ 1.824894] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10547 22:59:35.252786 <6>[ 1.833722] NET: Registered PF_PACKET protocol family
10548 22:59:35.255929 <6>[ 1.838652] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10549 22:59:35.262139 <6>[ 1.842876] 9pnet: Installing 9P2000 support
10550 22:59:35.265830 <6>[ 1.848674] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10551 22:59:35.268929 <5>[ 1.852546] Key type dns_resolver registered
10552 22:59:35.275436 <6>[ 1.858425] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10553 22:59:35.282587 <6>[ 1.862798] registered taskstats version 1
10554 22:59:35.285738 <5>[ 1.873181] Loading compiled-in X.509 certificates
10555 22:59:35.320163 <4>[ 1.900412] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10556 22:59:35.330520 <4>[ 1.911114] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10557 22:59:35.340920 <3>[ 1.924021] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10558 22:59:35.352994 <6>[ 1.939561] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10559 22:59:35.360190 <6>[ 1.946382] xhci-mtk 11200000.usb: xHCI Host Controller
10560 22:59:35.366232 <6>[ 1.951881] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10561 22:59:35.376618 <6>[ 1.959727] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10562 22:59:35.383558 <6>[ 1.969159] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10563 22:59:35.390194 <6>[ 1.975347] xhci-mtk 11200000.usb: xHCI Host Controller
10564 22:59:35.396595 <6>[ 1.980844] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10565 22:59:35.403142 <6>[ 1.988507] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10566 22:59:35.410338 <6>[ 1.996417] hub 1-0:1.0: USB hub found
10567 22:59:35.413510 <6>[ 2.000451] hub 1-0:1.0: 1 port detected
10568 22:59:35.420216 <6>[ 2.004816] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10569 22:59:35.427202 <6>[ 2.013612] hub 2-0:1.0: USB hub found
10570 22:59:35.430247 <6>[ 2.017648] hub 2-0:1.0: 1 port detected
10571 22:59:35.438126 <6>[ 2.024719] mtk-msdc 11f70000.mmc: Got CD GPIO
10572 22:59:35.456388 <6>[ 2.039275] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10573 22:59:35.462625 <6>[ 2.047304] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10574 22:59:35.472852 <4>[ 2.055305] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10575 22:59:35.482386 <6>[ 2.064964] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10576 22:59:35.489204 <6>[ 2.073046] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10577 22:59:35.496450 <6>[ 2.081083] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10578 22:59:35.506532 <6>[ 2.088998] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10579 22:59:35.512804 <6>[ 2.096819] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10580 22:59:35.522535 <6>[ 2.104644] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10581 22:59:35.533013 <6>[ 2.115399] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10582 22:59:35.539499 <6>[ 2.123777] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10583 22:59:35.550066 <6>[ 2.132126] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10584 22:59:35.556538 <6>[ 2.140469] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10585 22:59:35.566354 <6>[ 2.148811] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10586 22:59:35.573292 <6>[ 2.157153] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10587 22:59:35.583402 <6>[ 2.165495] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10588 22:59:35.590012 <6>[ 2.173838] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10589 22:59:35.599841 <6>[ 2.182181] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10590 22:59:35.606408 <6>[ 2.190523] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10591 22:59:35.616633 <6>[ 2.198867] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10592 22:59:35.622968 <6>[ 2.207210] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10593 22:59:35.633286 <6>[ 2.215553] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10594 22:59:35.640023 <6>[ 2.223898] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10595 22:59:35.649637 <6>[ 2.232247] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10596 22:59:35.656209 <6>[ 2.241145] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10597 22:59:35.662814 <6>[ 2.248581] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10598 22:59:35.670102 <6>[ 2.255596] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10599 22:59:35.676244 <6>[ 2.262703] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10600 22:59:35.683426 <6>[ 2.269967] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10601 22:59:35.693897 <6>[ 2.276916] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10602 22:59:35.704136 <6>[ 2.286068] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10603 22:59:35.713732 <6>[ 2.295202] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10604 22:59:35.723798 <6>[ 2.304505] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10605 22:59:35.730441 <6>[ 2.313980] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10606 22:59:35.740577 <6>[ 2.323454] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10607 22:59:35.750410 <6>[ 2.332582] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10608 22:59:35.760248 <6>[ 2.342056] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10609 22:59:35.769945 <6>[ 2.351190] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10610 22:59:35.780287 <6>[ 2.360493] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10611 22:59:35.789746 <6>[ 2.370660] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10612 22:59:35.800197 <6>[ 2.382537] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10613 22:59:35.806310 <6>[ 2.392316] Trying to probe devices needed for running init ...
10614 22:59:35.819806 <6>[ 2.403107] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10615 22:59:35.848743 <6>[ 2.435096] hub 2-1:1.0: USB hub found
10616 22:59:35.851683 <6>[ 2.439582] hub 2-1:1.0: 3 ports detected
10617 22:59:35.971192 <6>[ 2.554866] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10618 22:59:36.124962 <6>[ 2.711225] hub 1-1:1.0: USB hub found
10619 22:59:36.128200 <6>[ 2.715580] hub 1-1:1.0: 4 ports detected
10620 22:59:36.203791 <6>[ 2.787148] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10621 22:59:36.447378 <6>[ 3.030867] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10622 22:59:36.578973 <6>[ 3.165444] hub 1-1.4:1.0: USB hub found
10623 22:59:36.582101 <6>[ 3.169981] hub 1-1.4:1.0: 2 ports detected
10624 22:59:36.879397 <6>[ 3.462890] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10625 22:59:37.063659 <6>[ 3.646868] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10626 22:59:48.108497 <6>[ 14.699451] ALSA device list:
10627 22:59:48.114803 <6>[ 14.702707] No soundcards found.
10628 22:59:48.127508 <6>[ 14.715099] Freeing unused kernel memory: 8384K
10629 22:59:48.130578 <6>[ 14.720034] Run /init as init process
10630 22:59:48.140186 Loading, please wait...
10631 22:59:48.159882 Starting version 247.3-7+deb11u2
10632 22:59:48.476910 <6>[ 15.061792] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10633 22:59:48.489159 <6>[ 15.076881] remoteproc remoteproc0: scp is available
10634 22:59:48.498582 <4>[ 15.083000] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10635 22:59:48.505544 <6>[ 15.092886] remoteproc remoteproc0: powering up scp
10636 22:59:48.512030 <3>[ 15.095117] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10637 22:59:48.522552 <4>[ 15.098059] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10638 22:59:48.532497 <3>[ 15.106127] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10639 22:59:48.535666 <6>[ 15.116483] mc: Linux media interface: v0.10
10640 22:59:48.542333 <6>[ 15.120233] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10641 22:59:48.552264 <6>[ 15.120264] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10642 22:59:48.562014 <6>[ 15.120276] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10643 22:59:48.565252 <3>[ 15.124035] remoteproc remoteproc0: request_firmware failed: -2
10644 22:59:48.575068 <6>[ 15.124941] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10645 22:59:48.581662 <3>[ 15.128323] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10646 22:59:48.591735 <3>[ 15.128402] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10647 22:59:48.598200 <3>[ 15.128410] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10648 22:59:48.608418 <3>[ 15.128417] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10649 22:59:48.615253 <3>[ 15.128425] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10650 22:59:48.621730 <3>[ 15.128431] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10651 22:59:48.631252 <3>[ 15.128469] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10652 22:59:48.637931 <3>[ 15.128508] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10653 22:59:48.648260 <3>[ 15.128515] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10654 22:59:48.654720 <3>[ 15.128521] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10655 22:59:48.664629 <3>[ 15.128591] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10656 22:59:48.667703 <6>[ 15.142805] usbcore: registered new interface driver r8152
10657 22:59:48.677566 <3>[ 15.146792] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10658 22:59:48.684725 <4>[ 15.154314] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10659 22:59:48.690782 <3>[ 15.159797] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10660 22:59:48.701338 <3>[ 15.159808] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10661 22:59:48.708235 <4>[ 15.169196] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10662 22:59:48.715332 <3>[ 15.175605] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10663 22:59:48.721864 <6>[ 15.180388] videodev: Linux video capture interface: v2.00
10664 22:59:48.728949 <6>[ 15.235101] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10665 22:59:48.736274 <3>[ 15.240314] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10666 22:59:48.742685 <6>[ 15.244090] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10667 22:59:48.749355 <6>[ 15.244098] pci_bus 0000:00: root bus resource [bus 00-ff]
10668 22:59:48.756022 <6>[ 15.244106] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10669 22:59:48.765402 <6>[ 15.244112] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10670 22:59:48.772337 <6>[ 15.244144] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10671 22:59:48.782443 <6>[ 15.244162] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10672 22:59:48.785542 <6>[ 15.244243] pci 0000:00:00.0: supports D1 D2
10673 22:59:48.792230 <6>[ 15.244247] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10674 22:59:48.798525 <6>[ 15.246066] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10675 22:59:48.805377 <6>[ 15.246168] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10676 22:59:48.815664 <6>[ 15.246196] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10677 22:59:48.822149 <6>[ 15.246215] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10678 22:59:48.828764 <6>[ 15.246233] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10679 22:59:48.831852 <6>[ 15.246343] pci 0000:01:00.0: supports D1 D2
10680 22:59:48.842048 <6>[ 15.246346] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10681 22:59:48.852015 <6>[ 15.255701] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10682 22:59:48.858374 <6>[ 15.262324] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10683 22:59:48.865433 <6>[ 15.270732] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10684 22:59:48.875375 <4>[ 15.270941] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10685 22:59:48.878374 <4>[ 15.270941] Fallback method does not support PEC.
10686 22:59:48.888361 <4>[ 15.274116] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10687 22:59:48.898561 <4>[ 15.274125] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10688 22:59:48.904865 <6>[ 15.277831] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10689 22:59:48.914532 <6>[ 15.295221] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10690 22:59:48.924548 <3>[ 15.300056] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10691 22:59:48.931248 <6>[ 15.301147] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10692 22:59:48.938091 <6>[ 15.301161] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10693 22:59:48.947958 <3>[ 15.323881] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10694 22:59:48.951227 <6>[ 15.331092] Bluetooth: Core ver 2.22
10695 22:59:48.961196 <6>[ 15.331136] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10696 22:59:48.967636 <6>[ 15.331156] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10697 22:59:48.974744 <6>[ 15.331173] pci 0000:00:00.0: PCI bridge to [bus 01]
10698 22:59:48.981428 <6>[ 15.331181] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10699 22:59:48.987634 <6>[ 15.331391] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10700 22:59:48.994361 <6>[ 15.332271] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10701 22:59:48.997393 <6>[ 15.332656] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10702 22:59:49.004112 <6>[ 15.343300] usbcore: registered new interface driver cdc_ether
10703 22:59:49.010760 <6>[ 15.350073] NET: Registered PF_BLUETOOTH protocol family
10704 22:59:49.017714 <5>[ 15.352727] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10705 22:59:49.024490 <5>[ 15.362854] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10706 22:59:49.031037 <6>[ 15.366176] Bluetooth: HCI device and connection manager initialized
10707 22:59:49.037537 <6>[ 15.366273] r8152 2-1.3:1.0 eth0: v1.12.13
10708 22:59:49.044635 <6>[ 15.367696] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10709 22:59:49.057847 <6>[ 15.368934] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10710 22:59:49.061085 <6>[ 15.369094] usbcore: registered new interface driver uvcvideo
10711 22:59:49.070879 <4>[ 15.373756] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10712 22:59:49.077457 <6>[ 15.373896] usbcore: registered new interface driver r8153_ecm
10713 22:59:49.080693 <6>[ 15.378188] Bluetooth: HCI socket layer initialized
10714 22:59:49.087351 <6>[ 15.381775] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10715 22:59:49.094031 <6>[ 15.385054] cfg80211: failed to load regulatory.db
10716 22:59:49.097089 <6>[ 15.393308] Bluetooth: L2CAP socket layer initialized
10717 22:59:49.103777 <6>[ 15.407932] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10718 22:59:49.110261 <6>[ 15.414558] Bluetooth: SCO socket layer initialized
10719 22:59:49.120053 <6>[ 15.708051] usbcore: registered new interface driver btusb
10720 22:59:49.130013 <4>[ 15.708724] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10721 22:59:49.136819 <3>[ 15.724413] Bluetooth: hci0: Failed to load firmware file (-2)
10722 22:59:49.143733 <3>[ 15.730517] Bluetooth: hci0: Failed to set up firmware (-2)
10723 22:59:49.153550 <4>[ 15.736361] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10724 22:59:49.205172 <6>[ 15.789832] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10725 22:59:49.211993 <6>[ 15.797347] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10726 22:59:49.236088 <6>[ 15.824148] mt7921e 0000:01:00.0: ASIC revision: 79610010
10727 22:59:49.341640 <4>[ 15.922918] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10728 22:59:49.344871 Begin: Loading essential drivers ... done.
10729 22:59:49.352003 Begin: Running /scripts/init-premount ... done.
10730 22:59:49.358203 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10731 22:59:49.364692 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10732 22:59:49.367989 Device /sys/class/net/enx00e04c787aaa found
10733 22:59:49.371161 done.
10734 22:59:49.410265 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10735 22:59:49.463390 <4>[ 16.044976] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10736 22:59:49.583085 <4>[ 16.164530] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10737 22:59:49.698808 <4>[ 16.280334] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10738 22:59:49.814908 <4>[ 16.396211] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10739 22:59:49.930659 <4>[ 16.512218] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10740 22:59:50.046394 <4>[ 16.628132] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10741 22:59:50.162338 <4>[ 16.744090] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10742 22:59:50.278630 <4>[ 16.860079] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10743 22:59:50.394561 <4>[ 16.976048] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10744 22:59:50.405583 <6>[ 16.993486] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10745 22:59:50.501522 <3>[ 17.089968] mt7921e 0000:01:00.0: hardware init failed
10746 22:59:50.548038 IP-Config: no response after 2 secs - giving up
10747 22:59:50.602107 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10748 22:59:50.605128 IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):
10749 22:59:50.611840 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10750 22:59:50.618223 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10751 22:59:50.625091 host : mt8192-asurada-spherion-r0-cbg-0
10752 22:59:50.631895 domain : lava-rack
10753 22:59:50.634885 rootserver: 192.168.201.1 rootpath:
10754 22:59:50.638200 filename :
10755 22:59:50.672998 done.
10756 22:59:50.679929 Begin: Running /scripts/nfs-bottom ... done.
10757 22:59:50.697116 Begin: Running /scripts/init-bottom ... done.
10758 22:59:51.818585 <6>[ 18.407091] NET: Registered PF_INET6 protocol family
10759 22:59:51.825297 <6>[ 18.413862] Segment Routing with IPv6
10760 22:59:51.828396 <6>[ 18.417847] In-situ OAM (IOAM) with IPv6
10761 22:59:51.939763 <30>[ 18.508153] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10762 22:59:51.942916 <30>[ 18.531903] systemd[1]: Detected architecture arm64.
10763 22:59:51.962167
10764 22:59:51.965318 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10765 22:59:51.965425
10766 22:59:51.984380 <30>[ 18.572723] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10767 22:59:52.506249 <30>[ 19.091651] systemd[1]: Queued start job for default target Graphical Interface.
10768 22:59:52.523145 <30>[ 19.111906] systemd[1]: Created slice system-getty.slice.
10769 22:59:52.529813 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10770 22:59:52.546788 <30>[ 19.135560] systemd[1]: Created slice system-modprobe.slice.
10771 22:59:52.553582 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10772 22:59:52.571039 <30>[ 19.159499] systemd[1]: Created slice system-serial\x2dgetty.slice.
10773 22:59:52.581061 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10774 22:59:52.594946 <30>[ 19.183353] systemd[1]: Created slice User and Session Slice.
10775 22:59:52.601544 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10776 22:59:52.622079 <30>[ 19.207085] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10777 22:59:52.628593 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10778 22:59:52.645931 <30>[ 19.230973] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10779 22:59:52.652323 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10780 22:59:52.673139 <30>[ 19.254972] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10781 22:59:52.679478 <30>[ 19.266988] systemd[1]: Reached target Local Encrypted Volumes.
10782 22:59:52.686268 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10783 22:59:52.702091 <30>[ 19.290967] systemd[1]: Reached target Paths.
10784 22:59:52.705926 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10785 22:59:52.722121 <30>[ 19.310931] systemd[1]: Reached target Remote File Systems.
10786 22:59:52.728615 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10787 22:59:52.746678 <30>[ 19.335168] systemd[1]: Reached target Slices.
10788 22:59:52.750003 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10789 22:59:52.766098 <30>[ 19.354949] systemd[1]: Reached target Swap.
10790 22:59:52.769693 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10791 22:59:52.790284 <30>[ 19.375259] systemd[1]: Listening on initctl Compatibility Named Pipe.
10792 22:59:52.796419 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10793 22:59:52.803040 <30>[ 19.390733] systemd[1]: Listening on Journal Audit Socket.
10794 22:59:52.809821 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10795 22:59:52.823130 <30>[ 19.411989] systemd[1]: Listening on Journal Socket (/dev/log).
10796 22:59:52.829765 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10797 22:59:52.847193 <30>[ 19.435751] systemd[1]: Listening on Journal Socket.
10798 22:59:52.853729 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10799 22:59:52.870680 <30>[ 19.456062] systemd[1]: Listening on Network Service Netlink Socket.
10800 22:59:52.877429 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10801 22:59:52.892626 <30>[ 19.481413] systemd[1]: Listening on udev Control Socket.
10802 22:59:52.899425 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10803 22:59:52.914934 <30>[ 19.503172] systemd[1]: Listening on udev Kernel Socket.
10804 22:59:52.921001 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10805 22:59:52.954672 <30>[ 19.543198] systemd[1]: Mounting Huge Pages File System...
10806 22:59:52.961108 Mounting [0;1;39mHuge Pages File System[0m...
10807 22:59:52.976941 <30>[ 19.565404] systemd[1]: Mounting POSIX Message Queue File System...
10808 22:59:52.983800 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10809 22:59:53.001071 <30>[ 19.589451] systemd[1]: Mounting Kernel Debug File System...
10810 22:59:53.007734 Mounting [0;1;39mKernel Debug File System[0m...
10811 22:59:53.026103 <30>[ 19.611140] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10812 22:59:53.041642 <30>[ 19.626907] systemd[1]: Starting Create list of static device nodes for the current kernel...
10813 22:59:53.048190 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10814 22:59:53.068930 <30>[ 19.657519] systemd[1]: Starting Load Kernel Module configfs...
10815 22:59:53.075426 Starting [0;1;39mLoad Kernel Module configfs[0m...
10816 22:59:53.092710 <30>[ 19.681515] systemd[1]: Starting Load Kernel Module drm...
10817 22:59:53.099502 Starting [0;1;39mLoad Kernel Module drm[0m...
10818 22:59:53.117265 <30>[ 19.705524] systemd[1]: Starting Load Kernel Module fuse...
10819 22:59:53.123744 Starting [0;1;39mLoad Kernel Module fuse[0m...
10820 22:59:53.150619 <6>[ 19.739166] fuse: init (API version 7.37)
10821 22:59:53.160285 <30>[ 19.739754] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10822 22:59:53.187095 <30>[ 19.775398] systemd[1]: Starting Journal Service...
10823 22:59:53.190065 Starting [0;1;39mJournal Service[0m...
10824 22:59:53.213845 <30>[ 19.802084] systemd[1]: Starting Load Kernel Modules...
10825 22:59:53.219985 Starting [0;1;39mLoad Kernel Modules[0m...
10826 22:59:53.241027 <30>[ 19.826269] systemd[1]: Starting Remount Root and Kernel File Systems...
10827 22:59:53.247698 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10828 22:59:53.265264 <30>[ 19.853860] systemd[1]: Starting Coldplug All udev Devices...
10829 22:59:53.271753 Starting [0;1;39mColdplug All udev Devices[0m...
10830 22:59:53.289159 <30>[ 19.877955] systemd[1]: Mounted Huge Pages File System.
10831 22:59:53.295995 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10832 22:59:53.311079 <30>[ 19.899263] systemd[1]: Mounted POSIX Message Queue File System.
10833 22:59:53.317114 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10834 22:59:53.335628 <30>[ 19.923453] systemd[1]: Mounted Kernel Debug File System.
10835 22:59:53.348600 [[0;32m OK [0m] Mounted [0;1;39mKernel Debu<3>[ 19.932643] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10836 22:59:53.351843 g File System[0m.
10837 22:59:53.371392 <30>[ 19.955793] systemd[1]: Finished Create list of static device nodes for the current kernel.
10838 22:59:53.381349 [[0;32m OK [<3>[ 19.965807] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10839 22:59:53.387993 0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10840 22:59:53.403544 <30>[ 19.992017] systemd[1]: modprobe@configfs.service: Succeeded.
10841 22:59:53.410547 <30>[ 19.998707] systemd[1]: Finished Load Kernel Module configfs.
10842 22:59:53.424076 [[0;32m OK [0m] Finished [0;1;39mLoad Kerne<3>[ 20.007799] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10843 22:59:53.427187 l Module configfs[0m.
10844 22:59:53.443614 <30>[ 20.031861] systemd[1]: modprobe@drm.service: Succeeded.
10845 22:59:53.450176 <30>[ 20.038189] systemd[1]: Finished Load Kernel Module drm.
10846 22:59:53.460337 <3>[ 20.039659] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10847 22:59:53.463590 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10848 22:59:53.479704 <30>[ 20.068046] systemd[1]: modprobe@fuse.service: Succeeded.
10849 22:59:53.487074 <30>[ 20.074487] systemd[1]: Finished Load Kernel Module fuse.
10850 22:59:53.496879 <3>[ 20.075116] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10851 22:59:53.500076 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10852 22:59:53.520066 <30>[ 20.108469] systemd[1]: Finished Load Kernel Modules.
10853 22:59:53.529987 <3>[ 20.112546] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10854 22:59:53.533579 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10855 22:59:53.552436 <30>[ 20.140423] systemd[1]: Finished Remount Root and Kernel File Systems.
10856 22:59:53.565500 [[0;32m OK [<3>[ 20.148334] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10857 22:59:53.568702 0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10858 22:59:53.597038 <3>[ 20.182101] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10859 22:59:53.618365 <30>[ 20.205970] systemd[1]: Mounting FUSE Control File System...
10860 22:59:53.624994 Mounting [0;1;39mFUSE Control File System[0m...
10861 22:59:53.641381 <30>[ 20.229409] systemd[1]: Mounting Kernel Configuration File System...
10862 22:59:53.647749 Mounting [0;1;39mKernel Configuration File System[0m...
10863 22:59:53.669870 <30>[ 20.255357] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10864 22:59:53.679693 <30>[ 20.264401] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10865 22:59:53.718543 <30>[ 20.307235] systemd[1]: Starting Load/Save Random Seed...
10866 22:59:53.725128 Starting [0;1;39mLoad/Save Random Seed[0m...
10867 22:59:53.746247 <30>[ 20.334530] systemd[1]: Starting Apply Kernel Variables...
10868 22:59:53.752183 Starting [0;1;39mApply Kernel Variables[0m...
10869 22:59:53.769432 <4>[ 20.357440] power_supply_show_property: 2 callbacks suppressed
10870 22:59:53.779157 <3>[ 20.357456] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10871 22:59:53.786189 <30>[ 20.358027] systemd[1]: Starting Create System Users...
10872 22:59:53.790028 Starting [0;1;39mCreate System Users[0m...
10873 22:59:53.799862 <3>[ 20.384080] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10874 22:59:53.808431 <30>[ 20.396969] systemd[1]: Started Journal Service.
10875 22:59:53.814871 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10876 22:59:53.842745 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0<3>[ 20.425375] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10877 22:59:53.849291 <3>[ 20.426341] power_supply sbs-5-000b: driver failed to report `current_now' property: -6
10878 22:59:53.865737 <4>[ 20.435074] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10879 22:59:53.865907 m.
10880 22:59:53.872712 <3>[ 20.458954] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10881 22:59:53.882709 <3>[ 20.463932] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10882 22:59:53.889744 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10883 22:59:53.914789 [[0;1;31mFAILED<3>[ 20.497637] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10884 22:59:53.918180 [0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10885 22:59:53.944788 See 'systemctl status systemd-ud<3>[ 20.528559] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10886 22:59:53.948022 ev-trigger.service' for details.
10887 22:59:53.963497 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10888 22:59:53.974999 <3>[ 20.560610] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10889 22:59:53.981896 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10890 22:59:54.006201 [[0;32m OK [0m] Finished [0;1;39mCreate Sys<3>[ 20.591163] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10891 22:59:54.009170 tem Users[0m.
10892 22:59:54.037649 <3>[ 20.622503] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 22:59:54.054493 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10894 22:59:54.074148 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10895 22:59:54.112037 <46>[ 20.697056] systemd-journald[296]: Received client request to flush runtime journal.
10896 22:59:54.140927 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10897 22:59:54.159155 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10898 22:59:54.174503 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10899 22:59:54.230470 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10900 22:59:55.477072 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10901 22:59:55.522657 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10902 22:59:55.542685 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10903 22:59:55.567121 Starting [0;1;39mNetwork Service[0m...
10904 22:59:55.876882 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10905 22:59:55.900028 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10906 22:59:55.946903 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10907 22:59:56.184612 <6>[ 22.773802] remoteproc remoteproc0: powering up scp
10908 22:59:56.209964 <4>[ 22.795906] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10909 22:59:56.217046 <3>[ 22.805826] remoteproc remoteproc0: request_firmware failed: -2
10910 22:59:56.226625 <3>[ 22.812197] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10911 22:59:56.308026 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10912 22:59:56.326924 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10913 22:59:56.352107 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10914 22:59:56.366363 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10915 22:59:56.389538 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10916 22:59:56.434588 Starting [0;1;39mNetwork Name Resolution[0m...
10917 22:59:56.457481 Starting [0;1;39mNetwork Time Synchronization[0m...
10918 22:59:56.472851 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10919 22:59:56.494134 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10920 22:59:56.525947 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10921 22:59:56.572064 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10922 22:59:56.695300 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10923 22:59:56.715158 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10924 22:59:56.733229 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10925 22:59:56.750283 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10926 22:59:56.770375 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10927 22:59:56.883333 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10928 22:59:56.921814 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10929 22:59:56.955303 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10930 22:59:57.425017 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10931 22:59:57.438121 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10932 22:59:57.692368 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10933 22:59:57.710096 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10934 22:59:57.726183 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10935 22:59:57.758636 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10936 22:59:58.061821 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10937 22:59:58.094374 Starting [0;1;39mUser Login Management[0m...
10938 22:59:58.110710 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10939 22:59:58.128106 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10940 22:59:58.145358 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10941 22:59:58.174035 Starting [0;1;39mPermit User Sessions[0m...
10942 22:59:58.306920 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10943 22:59:58.350730 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10944 22:59:58.370207 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10945 22:59:58.390418 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10946 22:59:58.410905 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10947 22:59:58.427881 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10948 22:59:58.435442 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10949 22:59:58.450075 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10950 22:59:58.490269 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10951 22:59:58.526190 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10952 22:59:58.585482
10953 22:59:58.585688
10954 22:59:58.589245 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10955 22:59:58.589367
10956 22:59:58.592371 debian-bullseye-arm64 login: root (automatic login)
10957 22:59:58.592480
10958 22:59:58.592582
10959 22:59:58.927786 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 22:41:02 UTC 2023 aarch64
10960 22:59:58.927941
10961 22:59:58.934343 The programs included with the Debian GNU/Linux system are free software;
10962 22:59:58.940989 the exact distribution terms for each program are described in the
10963 22:59:58.944167 individual files in /usr/share/doc/*/copyright.
10964 22:59:58.944276
10965 22:59:58.951167 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10966 22:59:58.951281 permitted by applicable law.
10967 22:59:58.998995 Matched prompt #10: / #
10969 22:59:58.999395 Setting prompt string to ['/ #']
10970 22:59:58.999528 end: 2.2.5.1 login-action (duration 00:00:26) [common]
10972 22:59:58.999844 end: 2.2.5 auto-login-action (duration 00:00:26) [common]
10973 22:59:58.999966 start: 2.2.6 expect-shell-connection (timeout 00:03:38) [common]
10974 22:59:59.000072 Setting prompt string to ['/ #']
10975 22:59:59.000167 Forcing a shell prompt, looking for ['/ #']
10977 22:59:59.050431 / #
10978 22:59:59.050633 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10979 22:59:59.050750 Waiting using forced prompt support (timeout 00:02:30)
10980 22:59:59.055018
10981 22:59:59.055347 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10982 22:59:59.055486 start: 2.2.7 export-device-env (timeout 00:03:37) [common]
10984 22:59:59.155897 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10597675/extract-nfsrootfs-rk96f8r0'
10985 22:59:59.160671 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10597675/extract-nfsrootfs-rk96f8r0'
10987 22:59:59.261309 / # export NFS_SERVER_IP='192.168.201.1'
10988 22:59:59.265767 export NFS_SERVER_IP='192.168.201.1'
10989 22:59:59.266092 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10990 22:59:59.266226 end: 2.2 depthcharge-retry (duration 00:01:23) [common]
10991 22:59:59.266355 end: 2 depthcharge-action (duration 00:01:23) [common]
10992 22:59:59.266488 start: 3 lava-test-retry (timeout 00:30:00) [common]
10993 22:59:59.266620 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
10994 22:59:59.266733 Using namespace: common
10996 22:59:59.367113 / # #
10997 22:59:59.367319 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
10998 22:59:59.371762 #
10999 22:59:59.372074 Using /lava-10597675
11001 22:59:59.472462 / # export SHELL=/bin/sh
11002 22:59:59.477558 export SHELL=/bin/sh
11004 22:59:59.578131 / # . /lava-10597675/environment
11005 22:59:59.583666 . /lava-10597675/environment
11007 22:59:59.688688 / # /lava-10597675/bin/lava-test-runner /lava-10597675/0
11008 22:59:59.688885 Test shell timeout: 10s (minimum of the action and connection timeout)
11009 22:59:59.693881 /lava-10597675/bin/lava-test-runner /lava-10597675/0
11010 22:59:59.880771 + export TESTRUN_ID=0_lc-compliance
11011 22:59:59.887424 + cd /lava-10597675/0/tests/0_lc-compliance
11012 22:59:59.887543 + cat uuid
11013 22:59:59.891033 + UUID=10597675_1.6.2.3.1
11014 22:59:59.891160 + set +x
11015 22:59:59.897376 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 10597675_1.6.2.3.1>
11016 22:59:59.897700 Received signal: <STARTRUN> 0_lc-compliance 10597675_1.6.2.3.1
11017 22:59:59.897826 Starting test lava.0_lc-compliance (10597675_1.6.2.3.1)
11018 22:59:59.897955 Skipping test definition patterns.
11019 22:59:59.900581 + /usr/bin/lc-compliance-parser.sh
11020 23:00:01.041072 [0:00:27.513406231] [400] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:298 [0mlibcamera v0.0.0+1-76e1cb9f
11021 23:00:01.045015 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
11022 23:00:01.054378 [0:00:27.529095001] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11023 23:00:01.116402 [0:00:27.588577077] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11024 23:00:01.119592 [==========] Running 120 tests from 1 test suite.
11025 23:00:01.173658 [0:00:27.645758770] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11026 23:00:01.185532 [----------] Global test environment set-up.
11027 23:00:01.231022 [0:00:27.703406231] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11028 23:00:01.253424 [----------] 120 tests from CaptureTests/SingleStream
11029 23:00:01.307603 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11030 23:00:01.352456 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11031 23:00:01.352819 Received signal: <TESTSET> START CaptureTests/SingleStream
11032 23:00:01.352960 Starting test_set CaptureTests/SingleStream
11033 23:00:01.355697 Camera needs 4 requests, can't test only 1
11034 23:00:01.409561 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11035 23:00:01.463138
11036 23:00:01.534484 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (61 ms)
11037 23:00:01.609378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11038 23:00:01.609747 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11040 23:00:01.622302 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11041 23:00:01.663006 [0:00:28.135017308] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11042 23:00:01.665669 Camera needs 4 requests, can't test only 2
11043 23:00:01.724228 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11044 23:00:01.771900
11045 23:00:01.825789 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (57 ms)
11046 23:00:01.886753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11047 23:00:01.887125 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11049 23:00:01.897038 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11050 23:00:01.935342 Camera needs 4 requests, can't test only 3
11051 23:00:01.993131 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11052 23:00:02.041677
11053 23:00:02.108535 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (57 ms)
11054 23:00:02.176447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11055 23:00:02.176802 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11057 23:00:02.193899 [0:00:28.666407154] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11058 23:00:02.197234 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11059 23:00:02.236613 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (432 ms)
11060 23:00:02.298292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11061 23:00:02.298660 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11063 23:00:02.311185 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11064 23:00:02.355215 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (532 ms)
11065 23:00:02.430599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11066 23:00:02.430966 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11068 23:00:02.442557 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11069 23:00:02.884076 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (698 ms)
11070 23:00:02.894297 [0:00:29.366494770] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11071 23:00:02.972575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11072 23:00:02.972942 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11074 23:00:02.984649 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11075 23:00:03.788350 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (905 ms)
11076 23:00:03.797968 [0:00:30.269913770] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11077 23:00:03.867767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11078 23:00:03.868174 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11080 23:00:03.877120 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11081 23:00:05.187997 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (1399 ms)
11082 23:00:05.197821 [0:00:31.669208770] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11083 23:00:05.264634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11084 23:00:05.264971 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11086 23:00:05.277407 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11087 23:00:07.287472 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (2100 ms)
11088 23:00:07.297072 [0:00:33.769169847] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11089 23:00:07.355437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11090 23:00:07.355836 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11092 23:00:07.367081 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11093 23:00:10.519148 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (3232 ms)
11094 23:00:10.528896 [0:00:37.000731078] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11095 23:00:10.586620 [0:00:37.059572463] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11096 23:00:10.605259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11097 23:00:10.605621 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11099 23:00:10.616379 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11100 23:00:10.644984 [0:00:37.118557001] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11101 23:00:10.662581 Camera needs 4 requests, can't test only 1
11102 23:00:10.702554 [0:00:37.175839155] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11103 23:00:10.723339 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11104 23:00:10.774214
11105 23:00:10.829287 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (58 ms)
11106 23:00:10.893948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11107 23:00:10.894303 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11109 23:00:10.904675 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11110 23:00:10.944894 Camera needs 4 requests, can't test only 2
11111 23:00:11.005253 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11112 23:00:11.061629
11113 23:00:11.121234 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (60 ms)
11114 23:00:11.134579 [0:00:37.607690924] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11115 23:00:11.192932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11116 23:00:11.193313 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11118 23:00:11.202837 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11119 23:00:11.238202 Camera needs 4 requests, can't test only 3
11120 23:00:11.299030 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11121 23:00:11.354023
11122 23:00:11.414527 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (57 ms)
11123 23:00:11.472087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11124 23:00:11.472407 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11126 23:00:11.480959 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11127 23:00:11.515893 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (432 ms)
11128 23:00:11.568274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11129 23:00:11.568602 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11131 23:00:11.578277 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11132 23:00:11.657984 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (532 ms)
11133 23:00:11.671285 [0:00:38.140578386] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11134 23:00:11.733128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11135 23:00:11.733465 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11137 23:00:11.744117 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11138 23:00:12.390349 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (732 ms)
11139 23:00:12.403432 [0:00:38.872850617] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11140 23:00:12.466114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11141 23:00:12.466456 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11143 23:00:12.477089 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11144 23:00:13.293437 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (904 ms)
11145 23:00:13.306613 [0:00:39.775295386] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11146 23:00:13.379224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11147 23:00:13.379614 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11149 23:00:13.390490 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11150 23:00:14.695502 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (1398 ms)
11151 23:00:14.705510 [0:00:41.173659617] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11152 23:00:14.770578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11153 23:00:14.770929 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11155 23:00:14.780111 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11156 23:00:16.790535 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (2099 ms)
11157 23:00:16.803687 [0:00:43.272407463] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11158 23:00:16.854631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11159 23:00:16.854987 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11161 23:00:16.864097 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11162 23:00:19.560347 <6>[ 46.154806] vpu: disabling
11163 23:00:19.563336 <6>[ 46.157856] vproc2: disabling
11164 23:00:19.566577 <6>[ 46.161128] vproc1: disabling
11165 23:00:19.569936 <6>[ 46.164389] vaud18: disabling
11166 23:00:19.576665 <6>[ 46.167794] vsram_others: disabling
11167 23:00:19.580035 <6>[ 46.172107] va09: disabling
11168 23:00:19.583545 <6>[ 46.175227] vsram_md: disabling
11169 23:00:19.586650 <6>[ 46.178721] Vgpu: disabling
11170 23:00:19.957901 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (3168 ms)
11171 23:00:19.970679 [0:00:46.439867463] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11172 23:00:20.024929 [0:00:46.498986540] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11173 23:00:20.081540 [0:00:46.555953002] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11174 23:00:20.091474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11175 23:00:20.091823 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11177 23:00:20.105231 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11178 23:00:20.137061 [0:00:46.611523694] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11179 23:00:20.154730 Camera needs 4 requests, can't test only 1
11180 23:00:20.214173 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11181 23:00:20.273358
11182 23:00:20.333101 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (59 ms)
11183 23:00:20.397071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11184 23:00:20.397425 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11186 23:00:20.409004 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11187 23:00:20.449742 Camera needs 4 requests, can't test only 2
11188 23:00:20.504031 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11189 23:00:20.560291
11190 23:00:20.570264 [0:00:47.045958617] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11191 23:00:20.624956 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (57 ms)
11192 23:00:20.691299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11193 23:00:20.691665 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11195 23:00:20.702891 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11196 23:00:20.741944 Camera needs 4 requests, can't test only 3
11197 23:00:20.798228 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11198 23:00:20.851087
11199 23:00:20.912400 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (55 ms)
11200 23:00:20.979118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11201 23:00:20.979484 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11203 23:00:20.990905 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11204 23:00:21.027348 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (435 ms)
11205 23:00:21.082537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11206 23:00:21.082883 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11208 23:00:21.094758 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11209 23:00:21.104669 [0:00:47.577153232] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11210 23:00:21.141557 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (531 ms)
11211 23:00:21.206734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11212 23:00:21.207078 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11214 23:00:21.219859 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11215 23:00:21.730542 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (636 ms)
11216 23:00:21.744073 [0:00:48.213690771] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11217 23:00:21.812092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11218 23:00:21.812442 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11220 23:00:21.823663 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11221 23:00:22.631896 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (901 ms)
11222 23:00:22.645061 [0:00:49.114541463] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11223 23:00:22.713164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11224 23:00:22.713502 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11226 23:00:22.724431 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11227 23:00:24.030412 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (1399 ms)
11228 23:00:24.043393 [0:00:50.512905540] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11229 23:00:24.112551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11230 23:00:24.112906 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11232 23:00:24.121975 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11233 23:00:26.128547 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (2098 ms)
11234 23:00:26.141751 [0:00:52.611538771] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11235 23:00:26.197865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11236 23:00:26.198194 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11238 23:00:26.208316 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11239 23:00:29.360037 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (3231 ms)
11240 23:00:29.373075 [0:00:55.842965541] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11241 23:00:29.425726 [0:00:55.901006541] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11242 23:00:29.432480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11243 23:00:29.432776 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11245 23:00:29.441921 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11246 23:00:29.475880 Camera needs 4 requests, can't test only 1
11247 23:00:29.485535 [0:00:55.957859541] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11248 23:00:29.541283 [0:00:56.016557079] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11249 23:00:29.544708 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11250 23:00:29.592151
11251 23:00:29.639573 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (58 ms)
11252 23:00:29.696224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11253 23:00:29.696558 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11255 23:00:29.706026 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11256 23:00:29.740376 Camera needs 4 requests, can't test only 2
11257 23:00:29.788097 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11258 23:00:29.832114
11259 23:00:29.881058 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (57 ms)
11260 23:00:29.931586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11261 23:00:29.931939 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11263 23:00:29.942463 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11264 23:00:29.973358 [0:00:56.449216525] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11265 23:00:29.985238 Camera needs 4 requests, can't test only 3
11266 23:00:30.032618 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11267 23:00:30.077867
11268 23:00:30.129163 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (58 ms)
11269 23:00:30.182897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11270 23:00:30.183219 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11272 23:00:30.192836 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11273 23:00:30.226983 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (433 ms)
11274 23:00:30.281018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11275 23:00:30.281374 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11277 23:00:30.290272 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11278 23:00:30.498637 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (533 ms)
11279 23:00:30.511966 [0:00:56.984351605] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11280 23:00:30.566134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11281 23:00:30.566512 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11283 23:00:30.575942 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11284 23:00:31.200615 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (701 ms)
11285 23:00:31.213679 [0:00:57.686065207] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11286 23:00:31.265270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11287 23:00:31.265599 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11289 23:00:31.274536 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11290 23:00:32.102368 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (902 ms)
11291 23:00:32.115855 [0:00:58.587582391] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11292 23:00:32.181720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11293 23:00:32.182102 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11295 23:00:32.191700 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11296 23:00:33.503572 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (1400 ms)
11297 23:00:33.516225 [0:00:59.987989116] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11298 23:00:33.574740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11299 23:00:33.575044 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11301 23:00:33.584859 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11302 23:00:35.636603 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (2133 ms)
11303 23:00:35.649799 [0:01:02.122220377] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11304 23:00:35.701687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11305 23:00:35.702010 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11307 23:00:35.712091 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11308 23:00:38.868570 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (3232 ms)
11309 23:00:38.881977 [0:01:05.354084443] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11310 23:00:38.936657 [0:01:05.411335033] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11311 23:00:38.942658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11312 23:00:38.942978 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11314 23:00:38.952615 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11315 23:00:38.992792 [0:01:05.467693195] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11316 23:00:38.995996 Camera needs 4 requests, can't test only 1
11317 23:00:39.052124 [0:01:05.526932845] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11318 23:00:39.055364 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11319 23:00:39.100436
11320 23:00:39.150433 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (59 ms)
11321 23:00:39.205076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11322 23:00:39.205438 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11324 23:00:39.214552 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11325 23:00:39.247968 Camera needs 4 requests, can't test only 2
11326 23:00:39.298138 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11327 23:00:39.344828
11328 23:00:39.398865 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (57 ms)
11329 23:00:39.456462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11330 23:00:39.456811 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11332 23:00:39.465722 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11333 23:00:39.507877 Camera needs 4 requests, can't test only 3
11334 23:00:39.558208 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11335 23:00:39.608113
11336 23:00:39.660959 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (59 ms)
11337 23:00:39.718571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11338 23:00:39.718916 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11340 23:00:39.729784 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11341 23:00:40.271088 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (1227 ms)
11342 23:00:40.284125 [0:01:06.755262703] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11343 23:00:40.332551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11344 23:00:40.332896 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11346 23:00:40.342065 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11347 23:00:41.859279 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (1589 ms)
11348 23:00:41.872768 [0:01:08.343748773] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11349 23:00:41.923440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11350 23:00:41.923804 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11352 23:00:41.932870 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11353 23:00:43.918997 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (2059 ms)
11354 23:00:43.931870 [0:01:10.403419218] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11355 23:00:43.980688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11356 23:00:43.981039 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11358 23:00:43.991434 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11359 23:00:46.611763 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (2693 ms)
11360 23:00:46.624820 [0:01:13.095815838] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11361 23:00:46.669754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11362 23:00:46.670099 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11364 23:00:46.681145 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11365 23:00:50.798561 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (4187 ms)
11366 23:00:50.811292 [0:01:17.283429559] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11367 23:00:50.857688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11368 23:00:50.858050 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11370 23:00:50.867336 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11371 23:00:57.084942 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (6287 ms)
11372 23:00:57.097894 [0:01:23.570073392] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11373 23:00:57.143872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11374 23:00:57.144214 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11376 23:00:57.153447 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11377 23:01:06.739445 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (9655 ms)
11378 23:01:06.752650 [0:01:33.225608139] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11379 23:01:06.806573 [0:01:33.283053123] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11380 23:01:06.813011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11381 23:01:06.813316 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11383 23:01:06.819510 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11384 23:01:06.852398 Camera needs 4 requests, can't test only 1
11385 23:01:06.865637 [0:01:33.342156616] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11386 23:01:06.904768 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11387 23:01:06.923773 [0:01:33.400082976] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11388 23:01:06.956532
11389 23:01:07.007728 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (59 ms)
11390 23:01:07.059910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11391 23:01:07.060213 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11393 23:01:07.065930 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11394 23:01:07.096897 Camera needs 4 requests, can't test only 2
11395 23:01:07.142669 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11396 23:01:07.183478
11397 23:01:07.235291 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (59 ms)
11398 23:01:07.290785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11399 23:01:07.291101 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11401 23:01:07.297155 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11402 23:01:07.329878 Camera needs 4 requests, can't test only 3
11403 23:01:07.375800 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11404 23:01:07.427964
11405 23:01:07.483488 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (58 ms)
11406 23:01:07.536038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11407 23:01:07.536352 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11409 23:01:07.542680 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11410 23:01:08.177197 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (1259 ms)
11411 23:01:08.187309 [0:01:34.660226266] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11412 23:01:08.239043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11413 23:01:08.239355 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11415 23:01:08.245717 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11416 23:01:09.766302 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (1589 ms)
11417 23:01:09.776388 [0:01:36.250024317] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11418 23:01:09.827081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11419 23:01:09.827437 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11421 23:01:09.833767 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11422 23:01:11.825154 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (2059 ms)
11423 23:01:11.834935 [0:01:38.309039773] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11424 23:01:11.885875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11425 23:01:11.886205 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11427 23:01:11.892814 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11428 23:01:14.521269 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (2697 ms)
11429 23:01:14.531072 [0:01:41.004799878] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11430 23:01:14.586065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11431 23:01:14.586423 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11433 23:01:14.592998 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11434 23:01:18.709568 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (4189 ms)
11435 23:01:18.719545 [0:01:45.194356232] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11436 23:01:18.771693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11437 23:01:18.772031 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11439 23:01:18.779020 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11440 23:01:24.997387 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (6288 ms)
11441 23:01:25.007569 [0:01:51.480510524] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11442 23:01:25.055337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11443 23:01:25.055692 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11445 23:01:25.061951 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11446 23:01:34.651593 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (9655 ms)
11447 23:01:34.660956 [0:02:01.136246433] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11448 23:01:34.714951 [0:02:01.194300974] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11449 23:01:34.721319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11450 23:01:34.721594 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11452 23:01:34.730056 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11453 23:01:34.759776 Camera needs 4 requests, can't test only 1
11454 23:01:34.769786 [0:02:01.251199043] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11455 23:01:34.812076 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11456 23:01:34.829032 [0:02:01.308228617] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11457 23:01:34.862771
11458 23:01:34.916029 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (58 ms)
11459 23:01:34.968031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11460 23:01:34.968384 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11462 23:01:34.974385 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11463 23:01:35.005497 Camera needs 4 requests, can't test only 2
11464 23:01:35.054566 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11465 23:01:35.098642
11466 23:01:35.155261 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (57 ms)
11467 23:01:35.211481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11468 23:01:35.211799 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11470 23:01:35.218260 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11471 23:01:35.250872 Camera needs 4 requests, can't test only 3
11472 23:01:35.305096 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11473 23:01:35.347844
11474 23:01:35.401369 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (58 ms)
11475 23:01:35.453480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11476 23:01:35.453805 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11478 23:01:35.460200 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11479 23:01:35.981784 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (1157 ms)
11480 23:01:35.991292 [0:02:02.467376606] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11481 23:01:36.048362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11482 23:01:36.048705 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11484 23:01:36.055205 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11485 23:01:37.363003 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (1381 ms)
11486 23:01:37.372737 [0:02:03.847866265] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11487 23:01:37.432109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11488 23:01:37.432468 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11490 23:01:37.440248 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11491 23:01:39.403630 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (2040 ms)
11492 23:01:39.413157 [0:02:05.888161800] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11493 23:01:39.470107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11494 23:01:39.470449 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11496 23:01:39.476761 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11497 23:01:42.081166 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (2677 ms)
11498 23:01:42.091037 [0:02:08.564689519] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11499 23:01:42.143686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11500 23:01:42.144028 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11502 23:01:42.150034 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11503 23:01:46.285396 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (4203 ms)
11504 23:01:46.295704 [0:02:12.768604489] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11505 23:01:46.353698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11506 23:01:46.354035 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11508 23:01:46.361418 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11509 23:01:52.555175 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (6269 ms)
11510 23:01:52.564752 [0:02:19.039132909] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11511 23:01:52.631081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11512 23:01:52.631443 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11514 23:01:52.641771 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11515 23:02:02.257399 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (9702 ms)
11516 23:02:02.267600 [0:02:28.741630506] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11517 23:02:02.318214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11518 23:02:02.318576 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11520 23:02:02.328193 [0:02:28.799346669] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11521 23:02:02.334267 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11522 23:02:02.362667 Camera needs 4 requests, can't test only 1
11523 23:02:02.378100 [0:02:28.855800448] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11524 23:02:02.417940 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11525 23:02:02.437164 [0:02:28.914602402] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11526 23:02:02.469093
11527 23:02:02.521389 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (60 ms)
11528 23:02:02.576167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11529 23:02:02.576463 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11531 23:02:02.583895 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11532 23:02:02.617786 Camera needs 4 requests, can't test only 2
11533 23:02:02.665796 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11534 23:02:02.710214
11535 23:02:02.763540 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (57 ms)
11536 23:02:02.826403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11537 23:02:02.826749 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11539 23:02:02.832634 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11540 23:02:02.864213 Camera needs 4 requests, can't test only 3
11541 23:02:02.908444 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11542 23:02:02.949597
11543 23:02:03.007413 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (57 ms)
11544 23:02:03.066190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11545 23:02:03.066518 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11547 23:02:03.072657 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11548 23:02:03.689720 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (1258 ms)
11549 23:02:03.699843 [0:02:30.174113249] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11550 23:02:03.761460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11551 23:02:03.762199 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11553 23:02:03.770690 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11554 23:02:05.215246 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (1525 ms)
11555 23:02:05.224521 [0:02:31.698560847] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11556 23:02:05.276932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11557 23:02:05.277218 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11559 23:02:05.283683 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11560 23:02:07.274004 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (2059 ms)
11561 23:02:07.283944 [0:02:33.756500284] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11562 23:02:07.341373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11563 23:02:07.342118 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11565 23:02:07.349318 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11566 23:02:09.966010 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (2692 ms)
11567 23:02:09.975389 [0:02:36.450144146] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11568 23:02:10.035302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11569 23:02:10.036070 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11571 23:02:10.043981 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11572 23:02:14.154356 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (4188 ms)
11573 23:02:14.164083 [0:02:40.636509245] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11574 23:02:14.219868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11575 23:02:14.220156 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11577 23:02:14.226193 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11578 23:02:20.439501 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (6285 ms)
11579 23:02:20.449407 [0:02:46.923331944] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11580 23:02:20.509095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11581 23:02:20.509386 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11583 23:02:20.515752 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11584 23:02:30.062361 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (9623 ms)
11585 23:02:30.071968 [0:02:56.546547015] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11586 23:02:30.128679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11587 23:02:30.128978 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11589 23:02:30.135895 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11590 23:02:30.360472 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (302 ms)
11591 23:02:30.373179 [0:02:56.847184443] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11592 23:02:30.430508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11593 23:02:30.430849 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11595 23:02:30.440908 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11596 23:02:30.627958 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (267 ms)
11597 23:02:30.637766 [0:02:57.115380126] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11598 23:02:30.691153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11599 23:02:30.691498 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11601 23:02:30.700662 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11602 23:02:30.930224 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (302 ms)
11603 23:02:30.943182 [0:02:57.417687230] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11604 23:02:30.992665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11605 23:02:30.993002 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11607 23:02:31.003871 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11608 23:02:31.363099 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (433 ms)
11609 23:02:31.376023 [0:02:57.849890114] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11610 23:02:31.435677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11611 23:02:31.435973 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11613 23:02:31.446431 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11614 23:02:31.831977 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (468 ms)
11615 23:02:31.844668 [0:02:58.317769261] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11616 23:02:31.899797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11617 23:02:31.900126 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11619 23:02:31.910508 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11620 23:02:32.529301 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (698 ms)
11621 23:02:32.542486 [0:02:59.015196757] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11622 23:02:32.599284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11623 23:02:32.599640 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11625 23:02:32.610139 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11626 23:02:33.429520 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (900 ms)
11627 23:02:33.442386 [0:02:59.915233957] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11628 23:02:33.498695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11629 23:02:33.499043 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11631 23:02:33.509553 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11632 23:02:34.825905 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (1397 ms)
11633 23:02:34.839140 [0:03:01.312302499] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11634 23:02:34.900070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11635 23:02:34.900423 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11637 23:02:34.911248 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11638 23:02:36.917570 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (2092 ms)
11639 23:02:36.930825 [0:03:03.403928424] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11640 23:02:36.991433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11641 23:02:36.991747 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11643 23:02:37.003080 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11644 23:02:40.148249 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (3230 ms)
11645 23:02:40.161022 [0:03:06.634635660] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11646 23:02:40.221411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11647 23:02:40.221710 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11649 23:02:40.232457 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11650 23:02:40.387786 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (237 ms)
11651 23:02:40.397838 [0:03:06.871248487] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11652 23:02:40.456515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11653 23:02:40.456801 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11655 23:02:40.464296 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11656 23:02:40.656717 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (268 ms)
11657 23:02:40.666211 [0:03:07.139455601] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11658 23:02:40.728303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11659 23:02:40.728614 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11661 23:02:40.738720 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11662 23:02:40.957996 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (302 ms)
11663 23:02:40.968472 [0:03:07.441679650] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11664 23:02:41.026730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11665 23:02:41.027045 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11667 23:02:41.034273 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11668 23:02:41.326258 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (368 ms)
11669 23:02:41.336069 [0:03:07.809317301] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11670 23:02:41.397868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11671 23:02:41.398213 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11673 23:02:41.407148 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11674 23:02:41.794334 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (468 ms)
11675 23:02:41.804243 [0:03:08.279242016] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11676 23:02:41.857935 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11678 23:02:41.861013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11679 23:02:41.869581 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11680 23:02:42.495050 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (700 ms)
11681 23:02:42.504753 [0:03:08.978205504] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11682 23:02:42.559361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11683 23:02:42.559654 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11685 23:02:42.565774 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11686 23:02:43.394644 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (900 ms)
11687 23:02:43.404054 [0:03:09.878611039] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11688 23:02:43.459189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11689 23:02:43.459542 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11691 23:02:43.467177 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11692 23:02:44.792293 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (1398 ms)
11693 23:02:44.802785 [0:03:11.276090268] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11694 23:02:44.856904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11695 23:02:44.857655 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11697 23:02:44.864221 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11698 23:02:46.890885 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (2099 ms)
11699 23:02:46.900823 [0:03:13.374353742] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11700 23:02:46.965977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11701 23:02:46.966281 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11703 23:02:46.972316 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11704 23:02:50.121543 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (3230 ms)
11705 23:02:50.131449 [0:03:16.605765649] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11706 23:02:50.200316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11707 23:02:50.201232 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11709 23:02:50.208694 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11710 23:02:50.422484 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (301 ms)
11711 23:02:50.432174 [0:03:16.906964966] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11712 23:02:50.496822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11713 23:02:50.497115 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11715 23:02:50.505381 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11716 23:02:50.755797 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (334 ms)
11717 23:02:50.765695 [0:03:17.239452057] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11718 23:02:50.825044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11719 23:02:50.825396 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11721 23:02:50.833431 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11722 23:02:51.057087 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (301 ms)
11723 23:02:51.066923 [0:03:17.541460311] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11724 23:02:51.120625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11725 23:02:51.120973 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11727 23:02:51.129523 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11728 23:02:51.523384 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (467 ms)
11729 23:02:51.533678 [0:03:18.008287118] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11730 23:02:51.588340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11731 23:02:51.588666 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11733 23:02:51.594918 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11734 23:02:52.090634 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (567 ms)
11735 23:02:52.100813 [0:03:18.574719254] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11736 23:02:52.148959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11737 23:02:52.149270 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11739 23:02:52.155681 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11740 23:02:52.789346 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (698 ms)
11741 23:02:52.799386 [0:03:19.273838181] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11742 23:02:52.865185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11743 23:02:52.865944 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11745 23:02:52.875654 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11746 23:02:53.690936 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (903 ms)
11747 23:02:53.701029 [0:03:20.176064531] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11748 23:02:53.756585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11749 23:02:53.756879 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11751 23:02:53.764265 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11752 23:02:55.091173 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (1400 ms)
11753 23:02:55.101150 [0:03:21.576196222] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11754 23:02:55.152139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11755 23:02:55.152454 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11757 23:02:55.159303 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11758 23:02:57.191766 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (2100 ms)
11759 23:02:57.201872 [0:03:23.676778731] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11760 23:02:57.261074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11761 23:02:57.261375 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11763 23:02:57.269302 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11764 23:03:00.424437 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (3233 ms)
11765 23:03:00.433994 [0:03:26.909564013] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11766 23:03:00.493892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11767 23:03:00.494213 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11769 23:03:00.500549 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11770 23:03:00.725516 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (301 ms)
11771 23:03:00.735414 [0:03:27.210512632] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11772 23:03:00.797789 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11774 23:03:00.800750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11775 23:03:00.808867 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11776 23:03:00.992735 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (267 ms)
11777 23:03:01.002379 [0:03:27.477538944] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11778 23:03:01.066120 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11780 23:03:01.068932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11781 23:03:01.077578 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11782 23:03:01.294098 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (302 ms)
11783 23:03:01.304138 [0:03:27.779523813] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11784 23:03:01.368396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11785 23:03:01.368703 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11787 23:03:01.378732 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11788 23:03:01.725218 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (434 ms)
11789 23:03:01.738798 [0:03:28.213224482] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11790 23:03:01.796651 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11792 23:03:01.799640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11793 23:03:01.808098 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11794 23:03:02.195151 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (468 ms)
11795 23:03:02.205183 [0:03:28.680828158] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11796 23:03:02.255138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11797 23:03:02.255445 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11799 23:03:02.265923 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11800 23:03:02.895534 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (700 ms)
11801 23:03:02.905618 [0:03:29.380350969] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11802 23:03:02.966448 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11804 23:03:02.969294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11805 23:03:02.978604 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11806 23:03:03.795389 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (900 ms)
11807 23:03:03.805495 [0:03:30.280921220] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11808 23:03:03.873410 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11810 23:03:03.876350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11811 23:03:03.886071 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11812 23:03:05.195604 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (1399 ms)
11813 23:03:05.205715 [0:03:31.681061771] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11814 23:03:05.267445 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11816 23:03:05.270916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11817 23:03:05.277780 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11818 23:03:07.295079 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (2101 ms)
11819 23:03:07.305858 [0:03:33.781314410] [400] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11820 23:03:07.360883 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11822 23:03:07.363866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11823 23:03:07.371119 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11824 23:03:10.464943 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (3170 ms)
11825 23:03:10.520781 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11827 23:03:10.523893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11828 23:03:10.533549 [----------] 120 tests from CaptureTests/SingleStream (189423 ms total)
11829 23:03:10.580362
11830 23:03:10.640709 [----------] Global test environment tear-down
11831 23:03:10.689827 [==========] 120 tests from 1 test suite ran. (189423 ms total)
11832 23:03:10.737596 <LAVA_SIGNAL_TESTSET STOP>
11833 23:03:10.737912 Received signal: <TESTSET> STOP
11834 23:03:10.738021 Closing test_set CaptureTests/SingleStream
11835 23:03:10.743030 + set +x
11836 23:03:10.746772 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 10597675_1.6.2.3.1>
11837 23:03:10.747010 Received signal: <ENDRUN> 0_lc-compliance 10597675_1.6.2.3.1
11838 23:03:10.747087 Ending use of test pattern.
11839 23:03:10.747148 Ending test lava.0_lc-compliance (10597675_1.6.2.3.1), duration 190.85
11841 23:03:10.750040 <LAVA_TEST_RUNNER EXIT>
11842 23:03:10.750291 ok: lava_test_shell seems to have completed
11843 23:03:10.752139 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
11844 23:03:10.752314 end: 3.1 lava-test-shell (duration 00:03:11) [common]
11845 23:03:10.752403 end: 3 lava-test-retry (duration 00:03:11) [common]
11846 23:03:10.752490 start: 4 finalize (timeout 00:10:00) [common]
11847 23:03:10.752587 start: 4.1 power-off (timeout 00:00:30) [common]
11848 23:03:10.752738 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11849 23:03:10.828735 >> Command sent successfully.
11850 23:03:10.831251 Returned 0 in 0 seconds
11851 23:03:10.932109 end: 4.1 power-off (duration 00:00:00) [common]
11853 23:03:10.933537 start: 4.2 read-feedback (timeout 00:10:00) [common]
11854 23:03:10.934722 Listened to connection for namespace 'common' for up to 1s
11855 23:03:11.935414 Finalising connection for namespace 'common'
11856 23:03:11.936071 Disconnecting from shell: Finalise
11857 23:03:11.936509 / #
11858 23:03:12.037563 end: 4.2 read-feedback (duration 00:00:01) [common]
11859 23:03:12.038261 end: 4 finalize (duration 00:00:01) [common]
11860 23:03:12.038903 Cleaning after the job
11861 23:03:12.039391 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597675/tftp-deploy-5qtcemid/ramdisk
11862 23:03:12.048333 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597675/tftp-deploy-5qtcemid/kernel
11863 23:03:12.076889 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597675/tftp-deploy-5qtcemid/dtb
11864 23:03:12.077268 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597675/tftp-deploy-5qtcemid/nfsrootfs
11865 23:03:12.122292 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597675/tftp-deploy-5qtcemid/modules
11866 23:03:12.127512 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10597675
11867 23:03:12.386373 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10597675
11868 23:03:12.386554 Job finished correctly