Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 29
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 67
1 22:54:27.581705 lava-dispatcher, installed at version: 2023.05.1
2 22:54:27.581921 start: 0 validate
3 22:54:27.582055 Start time: 2023-06-05 22:54:27.582047+00:00 (UTC)
4 22:54:27.582189 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:54:27.582320 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 22:54:27.872972 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:54:27.874057 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:54:28.170869 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:54:28.171664 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:55:03.647878 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:55:03.648712 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 22:55:04.229488 validate duration: 36.65
14 22:55:04.230749 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:55:04.231352 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:55:04.231836 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:55:04.232465 Not decompressing ramdisk as can be used compressed.
18 22:55:04.232938 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230527.0/arm64/rootfs.cpio.gz
19 22:55:04.233304 saving as /var/lib/lava/dispatcher/tmp/10597642/tftp-deploy-sufuthx6/ramdisk/rootfs.cpio.gz
20 22:55:04.233647 total size: 27151647 (25MB)
21 22:55:07.598492 progress 0% (0MB)
22 22:55:07.633771 progress 5% (1MB)
23 22:55:07.648029 progress 10% (2MB)
24 22:55:07.658161 progress 15% (3MB)
25 22:55:07.666354 progress 20% (5MB)
26 22:55:07.673549 progress 25% (6MB)
27 22:55:07.680428 progress 30% (7MB)
28 22:55:07.687405 progress 35% (9MB)
29 22:55:07.694277 progress 40% (10MB)
30 22:55:07.701038 progress 45% (11MB)
31 22:55:07.707948 progress 50% (12MB)
32 22:55:07.714772 progress 55% (14MB)
33 22:55:07.721771 progress 60% (15MB)
34 22:55:07.728566 progress 65% (16MB)
35 22:55:07.735601 progress 70% (18MB)
36 22:55:07.742391 progress 75% (19MB)
37 22:55:07.749190 progress 80% (20MB)
38 22:55:07.756251 progress 85% (22MB)
39 22:55:07.763018 progress 90% (23MB)
40 22:55:07.769890 progress 95% (24MB)
41 22:55:07.776760 progress 100% (25MB)
42 22:55:07.776957 25MB downloaded in 3.54s (7.31MB/s)
43 22:55:07.777108 end: 1.1.1 http-download (duration 00:00:04) [common]
45 22:55:07.777344 end: 1.1 download-retry (duration 00:00:04) [common]
46 22:55:07.777434 start: 1.2 download-retry (timeout 00:09:56) [common]
47 22:55:07.777517 start: 1.2.1 http-download (timeout 00:09:56) [common]
48 22:55:07.777647 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 22:55:07.777718 saving as /var/lib/lava/dispatcher/tmp/10597642/tftp-deploy-sufuthx6/kernel/Image
50 22:55:07.777779 total size: 45746688 (43MB)
51 22:55:07.777840 No compression specified
52 22:55:07.779610 progress 0% (0MB)
53 22:55:07.791272 progress 5% (2MB)
54 22:55:07.802767 progress 10% (4MB)
55 22:55:07.814414 progress 15% (6MB)
56 22:55:07.825975 progress 20% (8MB)
57 22:55:07.837413 progress 25% (10MB)
58 22:55:07.848708 progress 30% (13MB)
59 22:55:07.860451 progress 35% (15MB)
60 22:55:07.872157 progress 40% (17MB)
61 22:55:07.883833 progress 45% (19MB)
62 22:55:07.895416 progress 50% (21MB)
63 22:55:07.906709 progress 55% (24MB)
64 22:55:07.918184 progress 60% (26MB)
65 22:55:07.929790 progress 65% (28MB)
66 22:55:07.941481 progress 70% (30MB)
67 22:55:07.953219 progress 75% (32MB)
68 22:55:07.964757 progress 80% (34MB)
69 22:55:07.976299 progress 85% (37MB)
70 22:55:07.987923 progress 90% (39MB)
71 22:55:07.999330 progress 95% (41MB)
72 22:55:08.010686 progress 100% (43MB)
73 22:55:08.010936 43MB downloaded in 0.23s (187.13MB/s)
74 22:55:08.011123 end: 1.2.1 http-download (duration 00:00:00) [common]
76 22:55:08.011351 end: 1.2 download-retry (duration 00:00:00) [common]
77 22:55:08.011441 start: 1.3 download-retry (timeout 00:09:56) [common]
78 22:55:08.011529 start: 1.3.1 http-download (timeout 00:09:56) [common]
79 22:55:08.011664 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 22:55:08.011735 saving as /var/lib/lava/dispatcher/tmp/10597642/tftp-deploy-sufuthx6/dtb/mt8192-asurada-spherion-r0.dtb
81 22:55:08.011796 total size: 46924 (0MB)
82 22:55:08.011856 No compression specified
83 22:55:08.013018 progress 69% (0MB)
84 22:55:08.013298 progress 100% (0MB)
85 22:55:08.013462 0MB downloaded in 0.00s (26.91MB/s)
86 22:55:08.013590 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:55:08.013810 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:55:08.013893 start: 1.4 download-retry (timeout 00:09:56) [common]
90 22:55:08.013975 start: 1.4.1 http-download (timeout 00:09:56) [common]
91 22:55:08.014082 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 22:55:08.014162 saving as /var/lib/lava/dispatcher/tmp/10597642/tftp-deploy-sufuthx6/modules/modules.tar
93 22:55:08.014227 total size: 8552396 (8MB)
94 22:55:08.014288 Using unxz to decompress xz
95 22:55:08.017625 progress 0% (0MB)
96 22:55:08.038132 progress 5% (0MB)
97 22:55:08.061522 progress 10% (0MB)
98 22:55:08.091746 progress 15% (1MB)
99 22:55:08.117139 progress 20% (1MB)
100 22:55:08.141747 progress 25% (2MB)
101 22:55:08.166362 progress 30% (2MB)
102 22:55:08.191987 progress 35% (2MB)
103 22:55:08.216308 progress 40% (3MB)
104 22:55:08.241103 progress 45% (3MB)
105 22:55:08.265700 progress 50% (4MB)
106 22:55:08.289939 progress 55% (4MB)
107 22:55:08.313173 progress 60% (4MB)
108 22:55:08.337176 progress 65% (5MB)
109 22:55:08.361693 progress 70% (5MB)
110 22:55:08.385574 progress 75% (6MB)
111 22:55:08.411093 progress 80% (6MB)
112 22:55:08.435468 progress 85% (6MB)
113 22:55:08.459577 progress 90% (7MB)
114 22:55:08.482449 progress 95% (7MB)
115 22:55:08.506388 progress 100% (8MB)
116 22:55:08.512827 8MB downloaded in 0.50s (16.36MB/s)
117 22:55:08.513098 end: 1.4.1 http-download (duration 00:00:00) [common]
119 22:55:08.513368 end: 1.4 download-retry (duration 00:00:00) [common]
120 22:55:08.513464 start: 1.5 prepare-tftp-overlay (timeout 00:09:56) [common]
121 22:55:08.513560 start: 1.5.1 extract-nfsrootfs (timeout 00:09:56) [common]
122 22:55:08.513643 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:55:08.513727 start: 1.5.2 lava-overlay (timeout 00:09:56) [common]
124 22:55:08.513947 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10597642/lava-overlay-4bndpx4d
125 22:55:08.514073 makedir: /var/lib/lava/dispatcher/tmp/10597642/lava-overlay-4bndpx4d/lava-10597642/bin
126 22:55:08.514179 makedir: /var/lib/lava/dispatcher/tmp/10597642/lava-overlay-4bndpx4d/lava-10597642/tests
127 22:55:08.514274 makedir: /var/lib/lava/dispatcher/tmp/10597642/lava-overlay-4bndpx4d/lava-10597642/results
128 22:55:08.514384 Creating /var/lib/lava/dispatcher/tmp/10597642/lava-overlay-4bndpx4d/lava-10597642/bin/lava-add-keys
129 22:55:08.514526 Creating /var/lib/lava/dispatcher/tmp/10597642/lava-overlay-4bndpx4d/lava-10597642/bin/lava-add-sources
130 22:55:08.514651 Creating /var/lib/lava/dispatcher/tmp/10597642/lava-overlay-4bndpx4d/lava-10597642/bin/lava-background-process-start
131 22:55:08.514776 Creating /var/lib/lava/dispatcher/tmp/10597642/lava-overlay-4bndpx4d/lava-10597642/bin/lava-background-process-stop
132 22:55:08.514974 Creating /var/lib/lava/dispatcher/tmp/10597642/lava-overlay-4bndpx4d/lava-10597642/bin/lava-common-functions
133 22:55:08.515098 Creating /var/lib/lava/dispatcher/tmp/10597642/lava-overlay-4bndpx4d/lava-10597642/bin/lava-echo-ipv4
134 22:55:08.515219 Creating /var/lib/lava/dispatcher/tmp/10597642/lava-overlay-4bndpx4d/lava-10597642/bin/lava-install-packages
135 22:55:08.515341 Creating /var/lib/lava/dispatcher/tmp/10597642/lava-overlay-4bndpx4d/lava-10597642/bin/lava-installed-packages
136 22:55:08.515462 Creating /var/lib/lava/dispatcher/tmp/10597642/lava-overlay-4bndpx4d/lava-10597642/bin/lava-os-build
137 22:55:08.515583 Creating /var/lib/lava/dispatcher/tmp/10597642/lava-overlay-4bndpx4d/lava-10597642/bin/lava-probe-channel
138 22:55:08.515704 Creating /var/lib/lava/dispatcher/tmp/10597642/lava-overlay-4bndpx4d/lava-10597642/bin/lava-probe-ip
139 22:55:08.515822 Creating /var/lib/lava/dispatcher/tmp/10597642/lava-overlay-4bndpx4d/lava-10597642/bin/lava-target-ip
140 22:55:08.515939 Creating /var/lib/lava/dispatcher/tmp/10597642/lava-overlay-4bndpx4d/lava-10597642/bin/lava-target-mac
141 22:55:08.516056 Creating /var/lib/lava/dispatcher/tmp/10597642/lava-overlay-4bndpx4d/lava-10597642/bin/lava-target-storage
142 22:55:08.516179 Creating /var/lib/lava/dispatcher/tmp/10597642/lava-overlay-4bndpx4d/lava-10597642/bin/lava-test-case
143 22:55:08.516298 Creating /var/lib/lava/dispatcher/tmp/10597642/lava-overlay-4bndpx4d/lava-10597642/bin/lava-test-event
144 22:55:08.516415 Creating /var/lib/lava/dispatcher/tmp/10597642/lava-overlay-4bndpx4d/lava-10597642/bin/lava-test-feedback
145 22:55:08.516539 Creating /var/lib/lava/dispatcher/tmp/10597642/lava-overlay-4bndpx4d/lava-10597642/bin/lava-test-raise
146 22:55:08.516672 Creating /var/lib/lava/dispatcher/tmp/10597642/lava-overlay-4bndpx4d/lava-10597642/bin/lava-test-reference
147 22:55:08.516791 Creating /var/lib/lava/dispatcher/tmp/10597642/lava-overlay-4bndpx4d/lava-10597642/bin/lava-test-runner
148 22:55:08.516910 Creating /var/lib/lava/dispatcher/tmp/10597642/lava-overlay-4bndpx4d/lava-10597642/bin/lava-test-set
149 22:55:08.517031 Creating /var/lib/lava/dispatcher/tmp/10597642/lava-overlay-4bndpx4d/lava-10597642/bin/lava-test-shell
150 22:55:08.517172 Updating /var/lib/lava/dispatcher/tmp/10597642/lava-overlay-4bndpx4d/lava-10597642/bin/lava-install-packages (oe)
151 22:55:08.517355 Updating /var/lib/lava/dispatcher/tmp/10597642/lava-overlay-4bndpx4d/lava-10597642/bin/lava-installed-packages (oe)
152 22:55:08.517503 Creating /var/lib/lava/dispatcher/tmp/10597642/lava-overlay-4bndpx4d/lava-10597642/environment
153 22:55:08.517631 LAVA metadata
154 22:55:08.517731 - LAVA_JOB_ID=10597642
155 22:55:08.517798 - LAVA_DISPATCHER_IP=192.168.201.1
156 22:55:08.517901 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:56) [common]
157 22:55:08.517968 skipped lava-vland-overlay
158 22:55:08.518043 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 22:55:08.518123 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:56) [common]
160 22:55:08.518184 skipped lava-multinode-overlay
161 22:55:08.518258 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 22:55:08.518339 start: 1.5.2.3 test-definition (timeout 00:09:56) [common]
163 22:55:08.518412 Loading test definitions
164 22:55:08.518502 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:56) [common]
165 22:55:08.518575 Using /lava-10597642 at stage 0
166 22:55:08.518905 uuid=10597642_1.5.2.3.1 testdef=None
167 22:55:08.518993 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 22:55:08.519078 start: 1.5.2.3.2 test-overlay (timeout 00:09:56) [common]
169 22:55:08.519573 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 22:55:08.519799 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:56) [common]
172 22:55:08.520391 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 22:55:08.520618 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:56) [common]
175 22:55:08.521197 runner path: /var/lib/lava/dispatcher/tmp/10597642/lava-overlay-4bndpx4d/lava-10597642/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 10597642_1.5.2.3.1
176 22:55:08.521349 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 22:55:08.521555 Creating lava-test-runner.conf files
179 22:55:08.521617 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10597642/lava-overlay-4bndpx4d/lava-10597642/0 for stage 0
180 22:55:08.521703 - 0_v4l2-compliance-mtk-vcodec-enc
181 22:55:08.521796 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 22:55:08.521881 start: 1.5.2.4 compress-overlay (timeout 00:09:56) [common]
183 22:55:08.528461 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 22:55:08.528565 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:56) [common]
185 22:55:08.528651 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 22:55:08.528735 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 22:55:08.528824 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
188 22:55:09.228048 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 22:55:09.228407 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
190 22:55:09.228524 extracting modules file /var/lib/lava/dispatcher/tmp/10597642/tftp-deploy-sufuthx6/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597642/extract-overlay-ramdisk-i5mt_pir/ramdisk
191 22:55:09.440816 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 22:55:09.440990 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
193 22:55:09.441089 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597642/compress-overlay-u1fmu5hb/overlay-1.5.2.4.tar.gz to ramdisk
194 22:55:09.441174 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597642/compress-overlay-u1fmu5hb/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10597642/extract-overlay-ramdisk-i5mt_pir/ramdisk
195 22:55:09.447618 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 22:55:09.447738 start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
197 22:55:09.447831 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 22:55:09.447921 start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
199 22:55:09.448001 Building ramdisk /var/lib/lava/dispatcher/tmp/10597642/extract-overlay-ramdisk-i5mt_pir/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10597642/extract-overlay-ramdisk-i5mt_pir/ramdisk
200 22:55:10.053510 >> 230342 blocks
201 22:55:14.011674 rename /var/lib/lava/dispatcher/tmp/10597642/extract-overlay-ramdisk-i5mt_pir/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10597642/tftp-deploy-sufuthx6/ramdisk/ramdisk.cpio.gz
202 22:55:14.012098 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 22:55:14.012216 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 22:55:14.012316 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 22:55:14.012431 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10597642/tftp-deploy-sufuthx6/kernel/Image'
206 22:55:25.653690 Returned 0 in 11 seconds
207 22:55:25.754280 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10597642/tftp-deploy-sufuthx6/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10597642/tftp-deploy-sufuthx6/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10597642/tftp-deploy-sufuthx6/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10597642/tftp-deploy-sufuthx6/kernel/image.itb
208 22:55:26.335789 output: FIT description: Kernel Image image with one or more FDT blobs
209 22:55:26.336148 output: Created: Mon Jun 5 23:55:26 2023
210 22:55:26.336224 output: Image 0 (kernel-1)
211 22:55:26.336290 output: Description:
212 22:55:26.336352 output: Created: Mon Jun 5 23:55:26 2023
213 22:55:26.336413 output: Type: Kernel Image
214 22:55:26.336474 output: Compression: lzma compressed
215 22:55:26.336535 output: Data Size: 10085945 Bytes = 9849.56 KiB = 9.62 MiB
216 22:55:26.336590 output: Architecture: AArch64
217 22:55:26.336645 output: OS: Linux
218 22:55:26.336705 output: Load Address: 0x00000000
219 22:55:26.336777 output: Entry Point: 0x00000000
220 22:55:26.336832 output: Hash algo: crc32
221 22:55:26.336888 output: Hash value: b2943ff2
222 22:55:26.336941 output: Image 1 (fdt-1)
223 22:55:26.336993 output: Description: mt8192-asurada-spherion-r0
224 22:55:26.337046 output: Created: Mon Jun 5 23:55:26 2023
225 22:55:26.337098 output: Type: Flat Device Tree
226 22:55:26.337150 output: Compression: uncompressed
227 22:55:26.337202 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 22:55:26.337254 output: Architecture: AArch64
229 22:55:26.337306 output: Hash algo: crc32
230 22:55:26.337358 output: Hash value: 1df858fa
231 22:55:26.337410 output: Image 2 (ramdisk-1)
232 22:55:26.337461 output: Description: unavailable
233 22:55:26.337513 output: Created: Mon Jun 5 23:55:26 2023
234 22:55:26.337565 output: Type: RAMDisk Image
235 22:55:26.337617 output: Compression: Unknown Compression
236 22:55:26.337669 output: Data Size: 40126170 Bytes = 39185.71 KiB = 38.27 MiB
237 22:55:26.337721 output: Architecture: AArch64
238 22:55:26.337772 output: OS: Linux
239 22:55:26.337824 output: Load Address: unavailable
240 22:55:26.337876 output: Entry Point: unavailable
241 22:55:26.337928 output: Hash algo: crc32
242 22:55:26.337979 output: Hash value: e2c0e4e4
243 22:55:26.338031 output: Default Configuration: 'conf-1'
244 22:55:26.338082 output: Configuration 0 (conf-1)
245 22:55:26.338134 output: Description: mt8192-asurada-spherion-r0
246 22:55:26.338185 output: Kernel: kernel-1
247 22:55:26.338236 output: Init Ramdisk: ramdisk-1
248 22:55:26.338288 output: FDT: fdt-1
249 22:55:26.338340 output: Loadables: kernel-1
250 22:55:26.338392 output:
251 22:55:26.338581 end: 1.5.8.1 prepare-fit (duration 00:00:12) [common]
252 22:55:26.338678 end: 1.5.8 prepare-kernel (duration 00:00:12) [common]
253 22:55:26.338815 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
254 22:55:26.338955 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 22:55:26.339029 No LXC device requested
256 22:55:26.339108 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 22:55:26.339193 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 22:55:26.339269 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 22:55:26.339337 Checking files for TFTP limit of 4294967296 bytes.
260 22:55:26.339817 end: 1 tftp-deploy (duration 00:00:22) [common]
261 22:55:26.339923 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 22:55:26.340013 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 22:55:26.340129 substitutions:
264 22:55:26.340194 - {DTB}: 10597642/tftp-deploy-sufuthx6/dtb/mt8192-asurada-spherion-r0.dtb
265 22:55:26.340260 - {INITRD}: 10597642/tftp-deploy-sufuthx6/ramdisk/ramdisk.cpio.gz
266 22:55:26.340328 - {KERNEL}: 10597642/tftp-deploy-sufuthx6/kernel/Image
267 22:55:26.340389 - {LAVA_MAC}: None
268 22:55:26.340445 - {PRESEED_CONFIG}: None
269 22:55:26.340499 - {PRESEED_LOCAL}: None
270 22:55:26.340552 - {RAMDISK}: 10597642/tftp-deploy-sufuthx6/ramdisk/ramdisk.cpio.gz
271 22:55:26.340606 - {ROOT_PART}: None
272 22:55:26.340659 - {ROOT}: None
273 22:55:26.340728 - {SERVER_IP}: 192.168.201.1
274 22:55:26.340814 - {TEE}: None
275 22:55:26.340885 Parsed boot commands:
276 22:55:26.340941 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 22:55:26.341108 Parsed boot commands: tftpboot 192.168.201.1 10597642/tftp-deploy-sufuthx6/kernel/image.itb 10597642/tftp-deploy-sufuthx6/kernel/cmdline
278 22:55:26.341198 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 22:55:26.341281 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 22:55:26.341371 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 22:55:26.341457 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 22:55:26.341526 Not connected, no need to disconnect.
283 22:55:26.341598 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 22:55:26.341675 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 22:55:26.341740 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-8'
286 22:55:26.344924 Setting prompt string to ['lava-test: # ']
287 22:55:26.345265 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 22:55:26.345372 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 22:55:26.345468 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 22:55:26.345555 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 22:55:26.345755 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
292 22:55:31.477433 >> Command sent successfully.
293 22:55:31.479822 Returned 0 in 5 seconds
294 22:55:31.580193 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 22:55:31.580759 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 22:55:31.580859 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 22:55:31.580946 Setting prompt string to 'Starting depthcharge on Spherion...'
299 22:55:31.581013 Changing prompt to 'Starting depthcharge on Spherion...'
300 22:55:31.581084 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 22:55:31.581338 [Enter `^Ec?' for help]
302 22:55:31.753233
303 22:55:31.753390
304 22:55:31.753460 F0: 102B 0000
305 22:55:31.753523
306 22:55:31.753588 F3: 1001 0000 [0200]
307 22:55:31.756071
308 22:55:31.756148 F3: 1001 0000
309 22:55:31.756216
310 22:55:31.756281 F7: 102D 0000
311 22:55:31.756357
312 22:55:31.759485 F1: 0000 0000
313 22:55:31.759554
314 22:55:31.759612 V0: 0000 0000 [0001]
315 22:55:31.759672
316 22:55:31.762842 00: 0007 8000
317 22:55:31.762916
318 22:55:31.762975 01: 0000 0000
319 22:55:31.763033
320 22:55:31.766104 BP: 0C00 0209 [0000]
321 22:55:31.766204
322 22:55:31.766261 G0: 1182 0000
323 22:55:31.766323
324 22:55:31.769583 EC: 0000 0021 [4000]
325 22:55:31.769651
326 22:55:31.769710 S7: 0000 0000 [0000]
327 22:55:31.769765
328 22:55:31.773182 CC: 0000 0000 [0001]
329 22:55:31.773282
330 22:55:31.773376 T0: 0000 0040 [010F]
331 22:55:31.773464
332 22:55:31.776387 Jump to BL
333 22:55:31.776489
334 22:55:31.800072
335 22:55:31.800190
336 22:55:31.800287
337 22:55:31.806982 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 22:55:31.810138 ARM64: Exception handlers installed.
339 22:55:31.814048 ARM64: Testing exception
340 22:55:31.817357 ARM64: Done test exception
341 22:55:31.823822 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 22:55:31.834047 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 22:55:31.840720 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 22:55:31.850771 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 22:55:31.857439 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 22:55:31.867769 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 22:55:31.877545 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 22:55:31.884461 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 22:55:31.902962 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 22:55:31.906301 WDT: Last reset was cold boot
351 22:55:31.909426 SPI1(PAD0) initialized at 2873684 Hz
352 22:55:31.912852 SPI5(PAD0) initialized at 992727 Hz
353 22:55:31.916472 VBOOT: Loading verstage.
354 22:55:31.922674 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 22:55:31.925971 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 22:55:31.929329 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 22:55:31.933044 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 22:55:31.939819 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 22:55:31.946706 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 22:55:31.957818 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 22:55:31.957906
362 22:55:31.957974
363 22:55:31.967782 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 22:55:31.970844 ARM64: Exception handlers installed.
365 22:55:31.974763 ARM64: Testing exception
366 22:55:31.974868 ARM64: Done test exception
367 22:55:31.981003 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 22:55:31.984441 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 22:55:31.998575 Probing TPM: . done!
370 22:55:31.998667 TPM ready after 0 ms
371 22:55:32.005447 Connected to device vid:did:rid of 1ae0:0028:00
372 22:55:32.012160 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 22:55:32.054476 Initialized TPM device CR50 revision 0
374 22:55:32.066650 tlcl_send_startup: Startup return code is 0
375 22:55:32.066758 TPM: setup succeeded
376 22:55:32.077769 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 22:55:32.087343 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 22:55:32.097867 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 22:55:32.107338 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 22:55:32.110577 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 22:55:32.114289 in-header: 03 07 00 00 08 00 00 00
382 22:55:32.117990 in-data: aa e4 47 04 13 02 00 00
383 22:55:32.121745 Chrome EC: UHEPI supported
384 22:55:32.128715 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 22:55:32.132584 in-header: 03 9d 00 00 08 00 00 00
386 22:55:32.135794 in-data: 10 20 20 08 00 00 00 00
387 22:55:32.135910 Phase 1
388 22:55:32.139323 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 22:55:32.147214 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 22:55:32.150383 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 22:55:32.154344 Recovery requested (1009000e)
392 22:55:32.164282 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 22:55:32.167414 tlcl_extend: response is 0
394 22:55:32.175848 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 22:55:32.180918 tlcl_extend: response is 0
396 22:55:32.187738 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 22:55:32.208857 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 22:55:32.216176 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 22:55:32.216270
400 22:55:32.216346
401 22:55:32.226586 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 22:55:32.230029 ARM64: Exception handlers installed.
403 22:55:32.230114 ARM64: Testing exception
404 22:55:32.233272 ARM64: Done test exception
405 22:55:32.254051 pmic_efuse_setting: Set efuses in 11 msecs
406 22:55:32.257857 pmwrap_interface_init: Select PMIF_VLD_RDY
407 22:55:32.264575 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 22:55:32.268087 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 22:55:32.271857 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 22:55:32.279124 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 22:55:32.282148 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 22:55:32.285549 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 22:55:32.292765 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 22:55:32.296631 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 22:55:32.300305 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 22:55:32.306773 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 22:55:32.309797 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 22:55:32.316814 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 22:55:32.319598 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 22:55:32.326563 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 22:55:32.333527 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 22:55:32.337081 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 22:55:32.343498 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 22:55:32.350050 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 22:55:32.353344 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 22:55:32.360504 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 22:55:32.364159 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 22:55:32.371125 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 22:55:32.377773 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 22:55:32.381405 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 22:55:32.388566 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 22:55:32.392172 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 22:55:32.398784 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 22:55:32.402469 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 22:55:32.409178 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 22:55:32.412640 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 22:55:32.419420 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 22:55:32.422952 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 22:55:32.426270 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 22:55:32.433931 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 22:55:32.437792 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 22:55:32.441336 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 22:55:32.448422 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 22:55:32.451123 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 22:55:32.457759 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 22:55:32.461557 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 22:55:32.464620 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 22:55:32.471198 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 22:55:32.474480 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 22:55:32.477861 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 22:55:32.484253 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 22:55:32.488160 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 22:55:32.491219 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 22:55:32.497679 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 22:55:32.501121 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 22:55:32.504392 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 22:55:32.507696 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 22:55:32.517729 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 22:55:32.524080 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 22:55:32.530783 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 22:55:32.537431 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 22:55:32.547260 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 22:55:32.550447 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 22:55:32.553885 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 22:55:32.560447 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 22:55:32.567154 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
467 22:55:32.573876 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 22:55:32.576846 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 22:55:32.580488 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 22:55:32.590991 [RTC]rtc_get_frequency_meter,154: input=15, output=794
471 22:55:32.594333 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 22:55:32.601669 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 22:55:32.604142 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
474 22:55:32.607608 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 22:55:32.611127 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
476 22:55:32.614557 ADC[4]: Raw value=898150 ID=7
477 22:55:32.617674 ADC[3]: Raw value=212700 ID=1
478 22:55:32.621005 RAM Code: 0x71
479 22:55:32.624430 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 22:55:32.627644 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 22:55:32.638547 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 22:55:32.644954 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 22:55:32.648001 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 22:55:32.651223 in-header: 03 07 00 00 08 00 00 00
485 22:55:32.654414 in-data: aa e4 47 04 13 02 00 00
486 22:55:32.658374 Chrome EC: UHEPI supported
487 22:55:32.661723 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 22:55:32.665781 in-header: 03 d5 00 00 08 00 00 00
489 22:55:32.669438 in-data: 98 20 60 08 00 00 00 00
490 22:55:32.673215 MRC: failed to locate region type 0.
491 22:55:32.680142 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 22:55:32.683499 DRAM-K: Running full calibration
493 22:55:32.689709 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 22:55:32.689793 header.status = 0x0
495 22:55:32.693282 header.version = 0x6 (expected: 0x6)
496 22:55:32.697389 header.size = 0xd00 (expected: 0xd00)
497 22:55:32.700516 header.flags = 0x0
498 22:55:32.707125 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 22:55:32.723495 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
500 22:55:32.729658 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 22:55:32.732849 dram_init: ddr_geometry: 2
502 22:55:32.736460 [EMI] MDL number = 2
503 22:55:32.736544 [EMI] Get MDL freq = 0
504 22:55:32.739426 dram_init: ddr_type: 0
505 22:55:32.739509 is_discrete_lpddr4: 1
506 22:55:32.743025 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 22:55:32.743109
508 22:55:32.746741
509 22:55:32.746887 [Bian_co] ETT version 0.0.0.1
510 22:55:32.752862 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 22:55:32.752945
512 22:55:32.756504 dramc_set_vcore_voltage set vcore to 650000
513 22:55:32.759363 Read voltage for 800, 4
514 22:55:32.759446 Vio18 = 0
515 22:55:32.759513 Vcore = 650000
516 22:55:32.762681 Vdram = 0
517 22:55:32.762765 Vddq = 0
518 22:55:32.762838 Vmddr = 0
519 22:55:32.766399 dram_init: config_dvfs: 1
520 22:55:32.769418 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 22:55:32.776737 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 22:55:32.779252 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
523 22:55:32.782464 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
524 22:55:32.785619 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
525 22:55:32.792263 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
526 22:55:32.792348 MEM_TYPE=3, freq_sel=18
527 22:55:32.796486 sv_algorithm_assistance_LP4_1600
528 22:55:32.799360 ============ PULL DRAM RESETB DOWN ============
529 22:55:32.807349 ========== PULL DRAM RESETB DOWN end =========
530 22:55:32.810405 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 22:55:32.813535 ===================================
532 22:55:32.813619 LPDDR4 DRAM CONFIGURATION
533 22:55:32.817515 ===================================
534 22:55:32.820648 EX_ROW_EN[0] = 0x0
535 22:55:32.820733 EX_ROW_EN[1] = 0x0
536 22:55:32.824341 LP4Y_EN = 0x0
537 22:55:32.824424 WORK_FSP = 0x0
538 22:55:32.828057 WL = 0x2
539 22:55:32.828141 RL = 0x2
540 22:55:32.832273 BL = 0x2
541 22:55:32.832356 RPST = 0x0
542 22:55:32.835947 RD_PRE = 0x0
543 22:55:32.836031 WR_PRE = 0x1
544 22:55:32.839261 WR_PST = 0x0
545 22:55:32.839345 DBI_WR = 0x0
546 22:55:32.842983 DBI_RD = 0x0
547 22:55:32.843067 OTF = 0x1
548 22:55:32.846523 ===================================
549 22:55:32.850314 ===================================
550 22:55:32.850398 ANA top config
551 22:55:32.853914 ===================================
552 22:55:32.857344 DLL_ASYNC_EN = 0
553 22:55:32.860923 ALL_SLAVE_EN = 1
554 22:55:32.861006 NEW_RANK_MODE = 1
555 22:55:32.864550 DLL_IDLE_MODE = 1
556 22:55:32.867986 LP45_APHY_COMB_EN = 1
557 22:55:32.868070 TX_ODT_DIS = 1
558 22:55:32.871700 NEW_8X_MODE = 1
559 22:55:32.875592 ===================================
560 22:55:32.879208 ===================================
561 22:55:32.882597 data_rate = 1600
562 22:55:32.886352 CKR = 1
563 22:55:32.886436 DQ_P2S_RATIO = 8
564 22:55:32.890301 ===================================
565 22:55:32.893610 CA_P2S_RATIO = 8
566 22:55:32.897019 DQ_CA_OPEN = 0
567 22:55:32.900197 DQ_SEMI_OPEN = 0
568 22:55:32.900279 CA_SEMI_OPEN = 0
569 22:55:32.903406 CA_FULL_RATE = 0
570 22:55:32.906497 DQ_CKDIV4_EN = 1
571 22:55:32.909989 CA_CKDIV4_EN = 1
572 22:55:32.913381 CA_PREDIV_EN = 0
573 22:55:32.916885 PH8_DLY = 0
574 22:55:32.916968 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 22:55:32.919974 DQ_AAMCK_DIV = 4
576 22:55:32.922977 CA_AAMCK_DIV = 4
577 22:55:32.926663 CA_ADMCK_DIV = 4
578 22:55:32.929944 DQ_TRACK_CA_EN = 0
579 22:55:32.933249 CA_PICK = 800
580 22:55:32.936691 CA_MCKIO = 800
581 22:55:32.936775 MCKIO_SEMI = 0
582 22:55:32.939976 PLL_FREQ = 3068
583 22:55:32.943088 DQ_UI_PI_RATIO = 32
584 22:55:32.946491 CA_UI_PI_RATIO = 0
585 22:55:32.949664 ===================================
586 22:55:32.953077 ===================================
587 22:55:32.956352 memory_type:LPDDR4
588 22:55:32.956486 GP_NUM : 10
589 22:55:32.959454 SRAM_EN : 1
590 22:55:32.962784 MD32_EN : 0
591 22:55:32.962877 ===================================
592 22:55:32.966395 [ANA_INIT] >>>>>>>>>>>>>>
593 22:55:32.969827 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 22:55:32.973077 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 22:55:32.976338 ===================================
596 22:55:32.979579 data_rate = 1600,PCW = 0X7600
597 22:55:32.982731 ===================================
598 22:55:32.986148 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 22:55:32.992722 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 22:55:32.995920 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 22:55:33.002818 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 22:55:33.006132 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 22:55:33.009820 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 22:55:33.009907 [ANA_INIT] flow start
605 22:55:33.013054 [ANA_INIT] PLL >>>>>>>>
606 22:55:33.016847 [ANA_INIT] PLL <<<<<<<<
607 22:55:33.016933 [ANA_INIT] MIDPI >>>>>>>>
608 22:55:33.019997 [ANA_INIT] MIDPI <<<<<<<<
609 22:55:33.023878 [ANA_INIT] DLL >>>>>>>>
610 22:55:33.023962 [ANA_INIT] flow end
611 22:55:33.027657 ============ LP4 DIFF to SE enter ============
612 22:55:33.031345 ============ LP4 DIFF to SE exit ============
613 22:55:33.034860 [ANA_INIT] <<<<<<<<<<<<<
614 22:55:33.038716 [Flow] Enable top DCM control >>>>>
615 22:55:33.042417 [Flow] Enable top DCM control <<<<<
616 22:55:33.042502 Enable DLL master slave shuffle
617 22:55:33.050007 ==============================================================
618 22:55:33.050117 Gating Mode config
619 22:55:33.056477 ==============================================================
620 22:55:33.059575 Config description:
621 22:55:33.069855 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 22:55:33.076667 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 22:55:33.079868 SELPH_MODE 0: By rank 1: By Phase
624 22:55:33.085978 ==============================================================
625 22:55:33.089374 GAT_TRACK_EN = 1
626 22:55:33.093111 RX_GATING_MODE = 2
627 22:55:33.096045 RX_GATING_TRACK_MODE = 2
628 22:55:33.096129 SELPH_MODE = 1
629 22:55:33.099515 PICG_EARLY_EN = 1
630 22:55:33.102796 VALID_LAT_VALUE = 1
631 22:55:33.109913 ==============================================================
632 22:55:33.113215 Enter into Gating configuration >>>>
633 22:55:33.116565 Exit from Gating configuration <<<<
634 22:55:33.119224 Enter into DVFS_PRE_config >>>>>
635 22:55:33.129856 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 22:55:33.132815 Exit from DVFS_PRE_config <<<<<
637 22:55:33.135843 Enter into PICG configuration >>>>
638 22:55:33.139490 Exit from PICG configuration <<<<
639 22:55:33.142413 [RX_INPUT] configuration >>>>>
640 22:55:33.146027 [RX_INPUT] configuration <<<<<
641 22:55:33.149317 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 22:55:33.155541 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 22:55:33.162189 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 22:55:33.168920 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 22:55:33.175468 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 22:55:33.179103 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 22:55:33.186004 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 22:55:33.188838 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 22:55:33.192142 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 22:55:33.195683 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 22:55:33.198789 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 22:55:33.205600 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 22:55:33.208874 ===================================
654 22:55:33.212545 LPDDR4 DRAM CONFIGURATION
655 22:55:33.215256 ===================================
656 22:55:33.215365 EX_ROW_EN[0] = 0x0
657 22:55:33.218682 EX_ROW_EN[1] = 0x0
658 22:55:33.218792 LP4Y_EN = 0x0
659 22:55:33.222100 WORK_FSP = 0x0
660 22:55:33.222182 WL = 0x2
661 22:55:33.225659 RL = 0x2
662 22:55:33.225742 BL = 0x2
663 22:55:33.228842 RPST = 0x0
664 22:55:33.228925 RD_PRE = 0x0
665 22:55:33.231862 WR_PRE = 0x1
666 22:55:33.231946 WR_PST = 0x0
667 22:55:33.235281 DBI_WR = 0x0
668 22:55:33.238486 DBI_RD = 0x0
669 22:55:33.238569 OTF = 0x1
670 22:55:33.241867 ===================================
671 22:55:33.245490 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 22:55:33.248572 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 22:55:33.254899 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 22:55:33.258625 ===================================
675 22:55:33.261918 LPDDR4 DRAM CONFIGURATION
676 22:55:33.262001 ===================================
677 22:55:33.265264 EX_ROW_EN[0] = 0x10
678 22:55:33.268359 EX_ROW_EN[1] = 0x0
679 22:55:33.268442 LP4Y_EN = 0x0
680 22:55:33.271545 WORK_FSP = 0x0
681 22:55:33.271627 WL = 0x2
682 22:55:33.275286 RL = 0x2
683 22:55:33.275369 BL = 0x2
684 22:55:33.278401 RPST = 0x0
685 22:55:33.278484 RD_PRE = 0x0
686 22:55:33.281917 WR_PRE = 0x1
687 22:55:33.282000 WR_PST = 0x0
688 22:55:33.284738 DBI_WR = 0x0
689 22:55:33.284821 DBI_RD = 0x0
690 22:55:33.288523 OTF = 0x1
691 22:55:33.292236 ===================================
692 22:55:33.298550 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 22:55:33.301993 nWR fixed to 40
694 22:55:33.302079 [ModeRegInit_LP4] CH0 RK0
695 22:55:33.305763 [ModeRegInit_LP4] CH0 RK1
696 22:55:33.309520 [ModeRegInit_LP4] CH1 RK0
697 22:55:33.309605 [ModeRegInit_LP4] CH1 RK1
698 22:55:33.313249 match AC timing 13
699 22:55:33.317055 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 22:55:33.320346 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 22:55:33.324091 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 22:55:33.331415 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 22:55:33.335004 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 22:55:33.335090 [EMI DOE] emi_dcm 0
705 22:55:33.341955 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 22:55:33.342042 ==
707 22:55:33.345618 Dram Type= 6, Freq= 0, CH_0, rank 0
708 22:55:33.349115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 22:55:33.349202 ==
710 22:55:33.353014 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 22:55:33.359978 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 22:55:33.369554 [CA 0] Center 38 (7~69) winsize 63
713 22:55:33.373320 [CA 1] Center 37 (7~68) winsize 62
714 22:55:33.377078 [CA 2] Center 35 (5~66) winsize 62
715 22:55:33.380276 [CA 3] Center 35 (5~66) winsize 62
716 22:55:33.384044 [CA 4] Center 34 (4~65) winsize 62
717 22:55:33.388042 [CA 5] Center 33 (3~64) winsize 62
718 22:55:33.388130
719 22:55:33.391758 [CmdBusTrainingLP45] Vref(ca) range 1: 34
720 22:55:33.391846
721 22:55:33.395353 [CATrainingPosCal] consider 1 rank data
722 22:55:33.395440 u2DelayCellTimex100 = 270/100 ps
723 22:55:33.398730 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
724 22:55:33.402730 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
725 22:55:33.406072 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
726 22:55:33.409691 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
727 22:55:33.413662 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
728 22:55:33.417283 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
729 22:55:33.417372
730 22:55:33.420943 CA PerBit enable=1, Macro0, CA PI delay=33
731 22:55:33.424747
732 22:55:33.424835 [CBTSetCACLKResult] CA Dly = 33
733 22:55:33.428416 CS Dly: 6 (0~37)
734 22:55:33.428503 ==
735 22:55:33.431737 Dram Type= 6, Freq= 0, CH_0, rank 1
736 22:55:33.435406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 22:55:33.435494 ==
738 22:55:33.439266 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 22:55:33.446548 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 22:55:33.455634 [CA 0] Center 38 (7~69) winsize 63
741 22:55:33.459454 [CA 1] Center 38 (7~69) winsize 63
742 22:55:33.462642 [CA 2] Center 35 (5~66) winsize 62
743 22:55:33.466457 [CA 3] Center 35 (5~66) winsize 62
744 22:55:33.469859 [CA 4] Center 34 (4~65) winsize 62
745 22:55:33.473914 [CA 5] Center 34 (4~65) winsize 62
746 22:55:33.473999
747 22:55:33.477401 [CmdBusTrainingLP45] Vref(ca) range 1: 32
748 22:55:33.477486
749 22:55:33.481528 [CATrainingPosCal] consider 2 rank data
750 22:55:33.481614 u2DelayCellTimex100 = 270/100 ps
751 22:55:33.488467 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
752 22:55:33.491990 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
753 22:55:33.495115 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
754 22:55:33.499050 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
755 22:55:33.502800 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
756 22:55:33.506960 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
757 22:55:33.507047
758 22:55:33.510272 CA PerBit enable=1, Macro0, CA PI delay=34
759 22:55:33.510366
760 22:55:33.513839 [CBTSetCACLKResult] CA Dly = 34
761 22:55:33.513951 CS Dly: 6 (0~38)
762 22:55:33.514045
763 22:55:33.517404 ----->DramcWriteLeveling(PI) begin...
764 22:55:33.517495 ==
765 22:55:33.521216 Dram Type= 6, Freq= 0, CH_0, rank 0
766 22:55:33.524327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 22:55:33.524413 ==
768 22:55:33.528354 Write leveling (Byte 0): 31 => 31
769 22:55:33.532133 Write leveling (Byte 1): 31 => 31
770 22:55:33.535660 DramcWriteLeveling(PI) end<-----
771 22:55:33.535745
772 22:55:33.535810 ==
773 22:55:33.538869 Dram Type= 6, Freq= 0, CH_0, rank 0
774 22:55:33.542951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 22:55:33.543037 ==
776 22:55:33.546437 [Gating] SW mode calibration
777 22:55:33.550099 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 22:55:33.557263 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 22:55:33.561000 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 22:55:33.564481 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
781 22:55:33.571804 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
782 22:55:33.576011 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
783 22:55:33.579791 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 22:55:33.582778 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 22:55:33.586791 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 22:55:33.590605 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 22:55:33.597598 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 22:55:33.601375 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 22:55:33.604973 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 22:55:33.609427 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 22:55:33.615754 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 22:55:33.619058 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 22:55:33.622135 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 22:55:33.625643 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 22:55:33.632562 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 22:55:33.636386 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 22:55:33.639125 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
798 22:55:33.645579 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 22:55:33.648886 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 22:55:33.652075 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 22:55:33.658914 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 22:55:33.661994 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 22:55:33.665347 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 22:55:33.672342 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 22:55:33.675824 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 22:55:33.678795 0 9 12 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
807 22:55:33.685335 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 22:55:33.689115 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 22:55:33.692010 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 22:55:33.698858 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 22:55:33.702143 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 22:55:33.705934 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 22:55:33.712088 0 10 8 | B1->B0 | 3434 3131 | 0 0 | (0 0) (1 1)
814 22:55:33.716049 0 10 12 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
815 22:55:33.718991 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 22:55:33.722600 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 22:55:33.728729 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 22:55:33.732159 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 22:55:33.735346 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 22:55:33.741943 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 22:55:33.745544 0 11 8 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (0 0)
822 22:55:33.748857 0 11 12 | B1->B0 | 3030 4444 | 0 0 | (0 0) (0 0)
823 22:55:33.755618 0 11 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
824 22:55:33.758806 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 22:55:33.761981 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 22:55:33.768888 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 22:55:33.772136 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 22:55:33.775406 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 22:55:33.781790 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
830 22:55:33.785365 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
831 22:55:33.788763 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 22:55:33.795571 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 22:55:33.798789 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 22:55:33.802160 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 22:55:33.808550 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 22:55:33.812179 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 22:55:33.815421 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 22:55:33.821905 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 22:55:33.825146 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 22:55:33.828810 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 22:55:33.835344 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 22:55:33.838554 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 22:55:33.841857 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 22:55:33.848473 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 22:55:33.851550 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
846 22:55:33.854814 Total UI for P1: 0, mck2ui 16
847 22:55:33.858247 best dqsien dly found for B0: ( 0, 14, 6)
848 22:55:33.861456 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
849 22:55:33.865120 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 22:55:33.868321 Total UI for P1: 0, mck2ui 16
851 22:55:33.871584 best dqsien dly found for B1: ( 0, 14, 10)
852 22:55:33.877895 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
853 22:55:33.881515 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
854 22:55:33.881625
855 22:55:33.884663 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
856 22:55:33.887869 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
857 22:55:33.891621 [Gating] SW calibration Done
858 22:55:33.891708 ==
859 22:55:33.894700 Dram Type= 6, Freq= 0, CH_0, rank 0
860 22:55:33.898237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
861 22:55:33.898325 ==
862 22:55:33.901549 RX Vref Scan: 0
863 22:55:33.901635
864 22:55:33.901722 RX Vref 0 -> 0, step: 1
865 22:55:33.901803
866 22:55:33.904766 RX Delay -130 -> 252, step: 16
867 22:55:33.907939 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
868 22:55:33.914765 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
869 22:55:33.918144 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
870 22:55:33.921331 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
871 22:55:33.924352 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
872 22:55:33.927873 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
873 22:55:33.935102 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
874 22:55:33.937831 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
875 22:55:33.941381 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
876 22:55:33.944684 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
877 22:55:33.948019 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
878 22:55:33.954311 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
879 22:55:33.957540 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
880 22:55:33.960843 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
881 22:55:33.964320 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
882 22:55:33.968000 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
883 22:55:33.970799 ==
884 22:55:33.970920 Dram Type= 6, Freq= 0, CH_0, rank 0
885 22:55:33.977927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
886 22:55:33.978011 ==
887 22:55:33.978077 DQS Delay:
888 22:55:33.981470 DQS0 = 0, DQS1 = 0
889 22:55:33.981552 DQM Delay:
890 22:55:33.984418 DQM0 = 80, DQM1 = 69
891 22:55:33.984500 DQ Delay:
892 22:55:33.987708 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
893 22:55:33.990802 DQ4 =77, DQ5 =69, DQ6 =85, DQ7 =93
894 22:55:33.994610 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
895 22:55:33.998422 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
896 22:55:33.998504
897 22:55:33.998569
898 22:55:33.998632 ==
899 22:55:34.001684 Dram Type= 6, Freq= 0, CH_0, rank 0
900 22:55:34.004887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
901 22:55:34.004973 ==
902 22:55:34.005040
903 22:55:34.005101
904 22:55:34.008195 TX Vref Scan disable
905 22:55:34.008279 == TX Byte 0 ==
906 22:55:34.015219 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
907 22:55:34.018640 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
908 22:55:34.018724 == TX Byte 1 ==
909 22:55:34.025848 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
910 22:55:34.028467 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
911 22:55:34.028552 ==
912 22:55:34.031517 Dram Type= 6, Freq= 0, CH_0, rank 0
913 22:55:34.035202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 22:55:34.035289 ==
915 22:55:34.048364 TX Vref=22, minBit 5, minWin=26, winSum=431
916 22:55:34.051692 TX Vref=24, minBit 11, minWin=26, winSum=433
917 22:55:34.055061 TX Vref=26, minBit 1, minWin=27, winSum=438
918 22:55:34.058498 TX Vref=28, minBit 1, minWin=27, winSum=440
919 22:55:34.062160 TX Vref=30, minBit 1, minWin=27, winSum=439
920 22:55:34.069086 TX Vref=32, minBit 10, minWin=26, winSum=437
921 22:55:34.071731 [TxChooseVref] Worse bit 1, Min win 27, Win sum 440, Final Vref 28
922 22:55:34.071815
923 22:55:34.075288 Final TX Range 1 Vref 28
924 22:55:34.075372
925 22:55:34.075440 ==
926 22:55:34.078383 Dram Type= 6, Freq= 0, CH_0, rank 0
927 22:55:34.081517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 22:55:34.085238 ==
929 22:55:34.085322
930 22:55:34.085388
931 22:55:34.085449 TX Vref Scan disable
932 22:55:34.088569 == TX Byte 0 ==
933 22:55:34.092163 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
934 22:55:34.098220 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
935 22:55:34.098305 == TX Byte 1 ==
936 22:55:34.101587 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
937 22:55:34.108535 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
938 22:55:34.108620
939 22:55:34.108687 [DATLAT]
940 22:55:34.108748 Freq=800, CH0 RK0
941 22:55:34.108808
942 22:55:34.112200 DATLAT Default: 0xa
943 22:55:34.112289 0, 0xFFFF, sum = 0
944 22:55:34.114678 1, 0xFFFF, sum = 0
945 22:55:34.117982 2, 0xFFFF, sum = 0
946 22:55:34.118065 3, 0xFFFF, sum = 0
947 22:55:34.121628 4, 0xFFFF, sum = 0
948 22:55:34.121711 5, 0xFFFF, sum = 0
949 22:55:34.125049 6, 0xFFFF, sum = 0
950 22:55:34.125133 7, 0xFFFF, sum = 0
951 22:55:34.128042 8, 0xFFFF, sum = 0
952 22:55:34.128125 9, 0x0, sum = 1
953 22:55:34.131305 10, 0x0, sum = 2
954 22:55:34.131398 11, 0x0, sum = 3
955 22:55:34.131464 12, 0x0, sum = 4
956 22:55:34.134570 best_step = 10
957 22:55:34.134652
958 22:55:34.134716 ==
959 22:55:34.137945 Dram Type= 6, Freq= 0, CH_0, rank 0
960 22:55:34.141342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
961 22:55:34.141425 ==
962 22:55:34.144976 RX Vref Scan: 1
963 22:55:34.145058
964 22:55:34.147969 Set Vref Range= 32 -> 127
965 22:55:34.148052
966 22:55:34.148117 RX Vref 32 -> 127, step: 1
967 22:55:34.148186
968 22:55:34.151319 RX Delay -111 -> 252, step: 8
969 22:55:34.151401
970 22:55:34.154711 Set Vref, RX VrefLevel [Byte0]: 32
971 22:55:34.157864 [Byte1]: 32
972 22:55:34.161559
973 22:55:34.161640 Set Vref, RX VrefLevel [Byte0]: 33
974 22:55:34.164642 [Byte1]: 33
975 22:55:34.169265
976 22:55:34.169347 Set Vref, RX VrefLevel [Byte0]: 34
977 22:55:34.172389 [Byte1]: 34
978 22:55:34.176857
979 22:55:34.176939 Set Vref, RX VrefLevel [Byte0]: 35
980 22:55:34.180099 [Byte1]: 35
981 22:55:34.184568
982 22:55:34.184650 Set Vref, RX VrefLevel [Byte0]: 36
983 22:55:34.187456 [Byte1]: 36
984 22:55:34.192136
985 22:55:34.192218 Set Vref, RX VrefLevel [Byte0]: 37
986 22:55:34.195432 [Byte1]: 37
987 22:55:34.199635
988 22:55:34.199717 Set Vref, RX VrefLevel [Byte0]: 38
989 22:55:34.202963 [Byte1]: 38
990 22:55:34.207092
991 22:55:34.207178 Set Vref, RX VrefLevel [Byte0]: 39
992 22:55:34.210668 [Byte1]: 39
993 22:55:34.214786
994 22:55:34.214920 Set Vref, RX VrefLevel [Byte0]: 40
995 22:55:34.218611 [Byte1]: 40
996 22:55:34.222494
997 22:55:34.222602 Set Vref, RX VrefLevel [Byte0]: 41
998 22:55:34.225942 [Byte1]: 41
999 22:55:34.230476
1000 22:55:34.230584 Set Vref, RX VrefLevel [Byte0]: 42
1001 22:55:34.233627 [Byte1]: 42
1002 22:55:34.237631
1003 22:55:34.237739 Set Vref, RX VrefLevel [Byte0]: 43
1004 22:55:34.241127 [Byte1]: 43
1005 22:55:34.245439
1006 22:55:34.245522 Set Vref, RX VrefLevel [Byte0]: 44
1007 22:55:34.248901 [Byte1]: 44
1008 22:55:34.252968
1009 22:55:34.253079 Set Vref, RX VrefLevel [Byte0]: 45
1010 22:55:34.256794 [Byte1]: 45
1011 22:55:34.260557
1012 22:55:34.260640 Set Vref, RX VrefLevel [Byte0]: 46
1013 22:55:34.264155 [Byte1]: 46
1014 22:55:34.268507
1015 22:55:34.268589 Set Vref, RX VrefLevel [Byte0]: 47
1016 22:55:34.272168 [Byte1]: 47
1017 22:55:34.276592
1018 22:55:34.276675 Set Vref, RX VrefLevel [Byte0]: 48
1019 22:55:34.279900 [Byte1]: 48
1020 22:55:34.283519
1021 22:55:34.283602 Set Vref, RX VrefLevel [Byte0]: 49
1022 22:55:34.286809 [Byte1]: 49
1023 22:55:34.290935
1024 22:55:34.294602 Set Vref, RX VrefLevel [Byte0]: 50
1025 22:55:34.294689 [Byte1]: 50
1026 22:55:34.298811
1027 22:55:34.298932 Set Vref, RX VrefLevel [Byte0]: 51
1028 22:55:34.302380 [Byte1]: 51
1029 22:55:34.306808
1030 22:55:34.306933 Set Vref, RX VrefLevel [Byte0]: 52
1031 22:55:34.309852 [Byte1]: 52
1032 22:55:34.314638
1033 22:55:34.314745 Set Vref, RX VrefLevel [Byte0]: 53
1034 22:55:34.317427 [Byte1]: 53
1035 22:55:34.322549
1036 22:55:34.322656 Set Vref, RX VrefLevel [Byte0]: 54
1037 22:55:34.325951 [Byte1]: 54
1038 22:55:34.329594
1039 22:55:34.329675 Set Vref, RX VrefLevel [Byte0]: 55
1040 22:55:34.333108 [Byte1]: 55
1041 22:55:34.336999
1042 22:55:34.337080 Set Vref, RX VrefLevel [Byte0]: 56
1043 22:55:34.340946 [Byte1]: 56
1044 22:55:34.344780
1045 22:55:34.344861 Set Vref, RX VrefLevel [Byte0]: 57
1046 22:55:34.347853 [Byte1]: 57
1047 22:55:34.352475
1048 22:55:34.352582 Set Vref, RX VrefLevel [Byte0]: 58
1049 22:55:34.355533 [Byte1]: 58
1050 22:55:34.359908
1051 22:55:34.360016 Set Vref, RX VrefLevel [Byte0]: 59
1052 22:55:34.363414 [Byte1]: 59
1053 22:55:34.367899
1054 22:55:34.367981 Set Vref, RX VrefLevel [Byte0]: 60
1055 22:55:34.370962 [Byte1]: 60
1056 22:55:34.375521
1057 22:55:34.375625 Set Vref, RX VrefLevel [Byte0]: 61
1058 22:55:34.378604 [Byte1]: 61
1059 22:55:34.382930
1060 22:55:34.383014 Set Vref, RX VrefLevel [Byte0]: 62
1061 22:55:34.386245 [Byte1]: 62
1062 22:55:34.390605
1063 22:55:34.390690 Set Vref, RX VrefLevel [Byte0]: 63
1064 22:55:34.394288 [Byte1]: 63
1065 22:55:34.398692
1066 22:55:34.398773 Set Vref, RX VrefLevel [Byte0]: 64
1067 22:55:34.401935 [Byte1]: 64
1068 22:55:34.406476
1069 22:55:34.406556 Set Vref, RX VrefLevel [Byte0]: 65
1070 22:55:34.409186 [Byte1]: 65
1071 22:55:34.413663
1072 22:55:34.413744 Set Vref, RX VrefLevel [Byte0]: 66
1073 22:55:34.417042 [Byte1]: 66
1074 22:55:34.421407
1075 22:55:34.421501 Set Vref, RX VrefLevel [Byte0]: 67
1076 22:55:34.424409 [Byte1]: 67
1077 22:55:34.428972
1078 22:55:34.429053 Set Vref, RX VrefLevel [Byte0]: 68
1079 22:55:34.432139 [Byte1]: 68
1080 22:55:34.436594
1081 22:55:34.436675 Set Vref, RX VrefLevel [Byte0]: 69
1082 22:55:34.439612 [Byte1]: 69
1083 22:55:34.444112
1084 22:55:34.444193 Set Vref, RX VrefLevel [Byte0]: 70
1085 22:55:34.447732 [Byte1]: 70
1086 22:55:34.451756
1087 22:55:34.451838 Set Vref, RX VrefLevel [Byte0]: 71
1088 22:55:34.455015 [Byte1]: 71
1089 22:55:34.459578
1090 22:55:34.459659 Set Vref, RX VrefLevel [Byte0]: 72
1091 22:55:34.462544 [Byte1]: 72
1092 22:55:34.466906
1093 22:55:34.466991 Set Vref, RX VrefLevel [Byte0]: 73
1094 22:55:34.470510 [Byte1]: 73
1095 22:55:34.474631
1096 22:55:34.474711 Set Vref, RX VrefLevel [Byte0]: 74
1097 22:55:34.477935 [Byte1]: 74
1098 22:55:34.482715
1099 22:55:34.482796 Set Vref, RX VrefLevel [Byte0]: 75
1100 22:55:34.485884 [Byte1]: 75
1101 22:55:34.489845
1102 22:55:34.489925 Set Vref, RX VrefLevel [Byte0]: 76
1103 22:55:34.493259 [Byte1]: 76
1104 22:55:34.497589
1105 22:55:34.497670 Set Vref, RX VrefLevel [Byte0]: 77
1106 22:55:34.501313 [Byte1]: 77
1107 22:55:34.505454
1108 22:55:34.505561 Set Vref, RX VrefLevel [Byte0]: 78
1109 22:55:34.508911 [Byte1]: 78
1110 22:55:34.513036
1111 22:55:34.513117 Set Vref, RX VrefLevel [Byte0]: 79
1112 22:55:34.516101 [Byte1]: 79
1113 22:55:34.520876
1114 22:55:34.520957 Set Vref, RX VrefLevel [Byte0]: 80
1115 22:55:34.523971 [Byte1]: 80
1116 22:55:34.528320
1117 22:55:34.528401 Final RX Vref Byte 0 = 63 to rank0
1118 22:55:34.531758 Final RX Vref Byte 1 = 59 to rank0
1119 22:55:34.534766 Final RX Vref Byte 0 = 63 to rank1
1120 22:55:34.538220 Final RX Vref Byte 1 = 59 to rank1==
1121 22:55:34.541838 Dram Type= 6, Freq= 0, CH_0, rank 0
1122 22:55:34.548080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1123 22:55:34.548162 ==
1124 22:55:34.548228 DQS Delay:
1125 22:55:34.548287 DQS0 = 0, DQS1 = 0
1126 22:55:34.551342 DQM Delay:
1127 22:55:34.551424 DQM0 = 81, DQM1 = 67
1128 22:55:34.554664 DQ Delay:
1129 22:55:34.558158 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1130 22:55:34.561383 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1131 22:55:34.564846 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1132 22:55:34.568207 DQ12 =72, DQ13 =72, DQ14 =76, DQ15 =76
1133 22:55:34.568289
1134 22:55:34.568353
1135 22:55:34.574719 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c2b, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
1136 22:55:34.578021 CH0 RK0: MR19=606, MR18=2C2B
1137 22:55:34.584837 CH0_RK0: MR19=0x606, MR18=0x2C2B, DQSOSC=398, MR23=63, INC=93, DEC=62
1138 22:55:34.584920
1139 22:55:34.588184 ----->DramcWriteLeveling(PI) begin...
1140 22:55:34.588266 ==
1141 22:55:34.591540 Dram Type= 6, Freq= 0, CH_0, rank 1
1142 22:55:34.594881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1143 22:55:34.594963 ==
1144 22:55:34.598137 Write leveling (Byte 0): 31 => 31
1145 22:55:34.601370 Write leveling (Byte 1): 30 => 30
1146 22:55:34.604602 DramcWriteLeveling(PI) end<-----
1147 22:55:34.604683
1148 22:55:34.604748 ==
1149 22:55:34.607731 Dram Type= 6, Freq= 0, CH_0, rank 1
1150 22:55:34.611125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 22:55:34.611208 ==
1152 22:55:34.614496 [Gating] SW mode calibration
1153 22:55:34.620906 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1154 22:55:34.627941 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1155 22:55:34.631033 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1156 22:55:34.634460 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1157 22:55:34.641197 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1158 22:55:34.644353 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 22:55:34.647927 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 22:55:34.654398 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 22:55:34.657694 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 22:55:34.660941 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 22:55:34.667957 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 22:55:34.671872 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 22:55:34.674925 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 22:55:34.721795 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 22:55:34.721896 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 22:55:34.722193 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 22:55:34.722585 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 22:55:34.722896 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 22:55:34.722986 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 22:55:34.723086 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1173 22:55:34.723556 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1174 22:55:34.724160 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 22:55:34.724442 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 22:55:34.765510 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 22:55:34.765602 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 22:55:34.765870 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 22:55:34.765954 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 22:55:34.766280 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1181 22:55:34.767037 0 9 8 | B1->B0 | 2323 2929 | 0 0 | (1 1) (0 0)
1182 22:55:34.767121 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1183 22:55:34.767570 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 22:55:34.768185 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 22:55:34.768463 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 22:55:34.783483 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 22:55:34.783566 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 22:55:34.783819 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
1189 22:55:34.784065 0 10 8 | B1->B0 | 3131 2a2a | 1 0 | (1 0) (0 0)
1190 22:55:34.787086 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1191 22:55:34.790313 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 22:55:34.793820 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 22:55:34.799980 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 22:55:34.803444 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 22:55:34.806978 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 22:55:34.810303 0 11 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1197 22:55:34.816701 0 11 8 | B1->B0 | 2b2b 3d3d | 1 0 | (0 0) (0 0)
1198 22:55:34.820033 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1199 22:55:34.823344 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 22:55:34.829848 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 22:55:34.833566 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 22:55:34.836860 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 22:55:34.844336 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 22:55:34.848143 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1205 22:55:34.851692 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 22:55:34.854927 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1207 22:55:34.861538 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 22:55:34.865135 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 22:55:34.868445 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 22:55:34.871567 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 22:55:34.878677 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 22:55:34.881901 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 22:55:34.885227 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 22:55:34.892466 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 22:55:34.895107 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 22:55:34.898439 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 22:55:34.905005 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 22:55:34.908572 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 22:55:34.912206 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 22:55:34.918107 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1221 22:55:34.921425 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1222 22:55:34.924719 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1223 22:55:34.928119 Total UI for P1: 0, mck2ui 16
1224 22:55:34.931389 best dqsien dly found for B0: ( 0, 14, 6)
1225 22:55:34.935091 Total UI for P1: 0, mck2ui 16
1226 22:55:34.938569 best dqsien dly found for B1: ( 0, 14, 10)
1227 22:55:34.941654 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1228 22:55:34.944814 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1229 22:55:34.944897
1230 22:55:34.951456 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1231 22:55:34.954570 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1232 22:55:34.954657 [Gating] SW calibration Done
1233 22:55:34.958165 ==
1234 22:55:34.961337 Dram Type= 6, Freq= 0, CH_0, rank 1
1235 22:55:34.964742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1236 22:55:34.964827 ==
1237 22:55:34.964893 RX Vref Scan: 0
1238 22:55:34.964953
1239 22:55:34.968098 RX Vref 0 -> 0, step: 1
1240 22:55:34.968210
1241 22:55:34.971031 RX Delay -130 -> 252, step: 16
1242 22:55:34.974615 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1243 22:55:34.977692 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1244 22:55:34.984379 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1245 22:55:34.988492 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1246 22:55:34.991308 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1247 22:55:34.994398 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1248 22:55:34.997741 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1249 22:55:35.004137 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1250 22:55:35.008000 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1251 22:55:35.011324 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1252 22:55:35.014398 iDelay=222, Bit 10, Center 61 (-66 ~ 189) 256
1253 22:55:35.017553 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1254 22:55:35.024557 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1255 22:55:35.028003 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1256 22:55:35.031214 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1257 22:55:35.034956 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1258 22:55:35.035045 ==
1259 22:55:35.037637 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 22:55:35.044138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 22:55:35.044222 ==
1262 22:55:35.044289 DQS Delay:
1263 22:55:35.044354 DQS0 = 0, DQS1 = 0
1264 22:55:35.047539 DQM Delay:
1265 22:55:35.047622 DQM0 = 79, DQM1 = 68
1266 22:55:35.050779 DQ Delay:
1267 22:55:35.054207 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =69
1268 22:55:35.057388 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
1269 22:55:35.061067 DQ8 =61, DQ9 =53, DQ10 =61, DQ11 =61
1270 22:55:35.064375 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1271 22:55:35.064459
1272 22:55:35.064525
1273 22:55:35.064585 ==
1274 22:55:35.068057 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 22:55:35.070593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 22:55:35.070676 ==
1277 22:55:35.070742
1278 22:55:35.070803
1279 22:55:35.073906 TX Vref Scan disable
1280 22:55:35.073989 == TX Byte 0 ==
1281 22:55:35.080850 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1282 22:55:35.083970 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1283 22:55:35.084053 == TX Byte 1 ==
1284 22:55:35.091028 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1285 22:55:35.094291 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1286 22:55:35.094374 ==
1287 22:55:35.097136 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 22:55:35.100362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 22:55:35.100446 ==
1290 22:55:35.114580 TX Vref=22, minBit 11, minWin=26, winSum=431
1291 22:55:35.117662 TX Vref=24, minBit 1, minWin=27, winSum=437
1292 22:55:35.121631 TX Vref=26, minBit 1, minWin=27, winSum=441
1293 22:55:35.124256 TX Vref=28, minBit 1, minWin=27, winSum=439
1294 22:55:35.127855 TX Vref=30, minBit 1, minWin=27, winSum=444
1295 22:55:35.134604 TX Vref=32, minBit 1, minWin=27, winSum=441
1296 22:55:35.137891 [TxChooseVref] Worse bit 1, Min win 27, Win sum 444, Final Vref 30
1297 22:55:35.137972
1298 22:55:35.141160 Final TX Range 1 Vref 30
1299 22:55:35.141241
1300 22:55:35.141305 ==
1301 22:55:35.144431 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 22:55:35.147691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 22:55:35.151101 ==
1304 22:55:35.151182
1305 22:55:35.151245
1306 22:55:35.151304 TX Vref Scan disable
1307 22:55:35.154311 == TX Byte 0 ==
1308 22:55:35.157665 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1309 22:55:35.164633 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1310 22:55:35.164714 == TX Byte 1 ==
1311 22:55:35.167905 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1312 22:55:35.174399 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1313 22:55:35.174479
1314 22:55:35.174544 [DATLAT]
1315 22:55:35.174603 Freq=800, CH0 RK1
1316 22:55:35.174661
1317 22:55:35.177756 DATLAT Default: 0xa
1318 22:55:35.177837 0, 0xFFFF, sum = 0
1319 22:55:35.181522 1, 0xFFFF, sum = 0
1320 22:55:35.184238 2, 0xFFFF, sum = 0
1321 22:55:35.184321 3, 0xFFFF, sum = 0
1322 22:55:35.187331 4, 0xFFFF, sum = 0
1323 22:55:35.187413 5, 0xFFFF, sum = 0
1324 22:55:35.190820 6, 0xFFFF, sum = 0
1325 22:55:35.190940 7, 0xFFFF, sum = 0
1326 22:55:35.194613 8, 0xFFFF, sum = 0
1327 22:55:35.194695 9, 0x0, sum = 1
1328 22:55:35.197689 10, 0x0, sum = 2
1329 22:55:35.197771 11, 0x0, sum = 3
1330 22:55:35.197837 12, 0x0, sum = 4
1331 22:55:35.200867 best_step = 10
1332 22:55:35.200948
1333 22:55:35.201012 ==
1334 22:55:35.203926 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 22:55:35.207439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 22:55:35.207522 ==
1337 22:55:35.210754 RX Vref Scan: 0
1338 22:55:35.210864
1339 22:55:35.213653 RX Vref 0 -> 0, step: 1
1340 22:55:35.213733
1341 22:55:35.213797 RX Delay -111 -> 252, step: 8
1342 22:55:35.221423 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1343 22:55:35.224450 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1344 22:55:35.227663 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1345 22:55:35.231147 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
1346 22:55:35.234370 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1347 22:55:35.240905 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1348 22:55:35.244348 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1349 22:55:35.247622 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1350 22:55:35.250935 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1351 22:55:35.254335 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1352 22:55:35.261083 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1353 22:55:35.264240 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1354 22:55:35.267568 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1355 22:55:35.270751 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1356 22:55:35.277597 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1357 22:55:35.280835 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1358 22:55:35.280918 ==
1359 22:55:35.284004 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 22:55:35.287191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 22:55:35.287276 ==
1362 22:55:35.290412 DQS Delay:
1363 22:55:35.290514 DQS0 = 0, DQS1 = 0
1364 22:55:35.290606 DQM Delay:
1365 22:55:35.294011 DQM0 = 79, DQM1 = 70
1366 22:55:35.294094 DQ Delay:
1367 22:55:35.297069 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =76
1368 22:55:35.300834 DQ4 =76, DQ5 =64, DQ6 =88, DQ7 =92
1369 22:55:35.303839 DQ8 =60, DQ9 =56, DQ10 =72, DQ11 =64
1370 22:55:35.307471 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =80
1371 22:55:35.307554
1372 22:55:35.307619
1373 22:55:35.317494 [DQSOSCAuto] RK1, (LSB)MR18= 0x4721, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
1374 22:55:35.317578 CH0 RK1: MR19=606, MR18=4721
1375 22:55:35.323942 CH0_RK1: MR19=0x606, MR18=0x4721, DQSOSC=392, MR23=63, INC=96, DEC=64
1376 22:55:35.327109 [RxdqsGatingPostProcess] freq 800
1377 22:55:35.334191 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1378 22:55:35.337182 Pre-setting of DQS Precalculation
1379 22:55:35.340534 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1380 22:55:35.340618 ==
1381 22:55:35.343933 Dram Type= 6, Freq= 0, CH_1, rank 0
1382 22:55:35.350330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1383 22:55:35.350414 ==
1384 22:55:35.353513 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1385 22:55:35.360510 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1386 22:55:35.369688 [CA 0] Center 36 (6~66) winsize 61
1387 22:55:35.372914 [CA 1] Center 36 (6~67) winsize 62
1388 22:55:35.376189 [CA 2] Center 35 (5~65) winsize 61
1389 22:55:35.379639 [CA 3] Center 34 (4~64) winsize 61
1390 22:55:35.382381 [CA 4] Center 35 (5~65) winsize 61
1391 22:55:35.385660 [CA 5] Center 34 (4~64) winsize 61
1392 22:55:35.385742
1393 22:55:35.389485 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1394 22:55:35.389568
1395 22:55:35.392741 [CATrainingPosCal] consider 1 rank data
1396 22:55:35.395845 u2DelayCellTimex100 = 270/100 ps
1397 22:55:35.399456 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1398 22:55:35.406090 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1399 22:55:35.409038 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1400 22:55:35.412674 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1401 22:55:35.415974 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1402 22:55:35.419039 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1403 22:55:35.419123
1404 22:55:35.422668 CA PerBit enable=1, Macro0, CA PI delay=34
1405 22:55:35.422789
1406 22:55:35.425464 [CBTSetCACLKResult] CA Dly = 34
1407 22:55:35.428796 CS Dly: 5 (0~36)
1408 22:55:35.428879 ==
1409 22:55:35.432899 Dram Type= 6, Freq= 0, CH_1, rank 1
1410 22:55:35.435585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 22:55:35.435669 ==
1412 22:55:35.442224 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1413 22:55:35.445544 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1414 22:55:35.455517 [CA 0] Center 37 (7~67) winsize 61
1415 22:55:35.459315 [CA 1] Center 36 (6~67) winsize 62
1416 22:55:35.462095 [CA 2] Center 35 (5~65) winsize 61
1417 22:55:35.465428 [CA 3] Center 34 (4~64) winsize 61
1418 22:55:35.469276 [CA 4] Center 34 (4~65) winsize 62
1419 22:55:35.472091 [CA 5] Center 33 (3~64) winsize 62
1420 22:55:35.472174
1421 22:55:35.475608 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1422 22:55:35.475692
1423 22:55:35.478573 [CATrainingPosCal] consider 2 rank data
1424 22:55:35.482275 u2DelayCellTimex100 = 270/100 ps
1425 22:55:35.485487 CA0 delay=36 (7~66),Diff = 2 PI (14 cell)
1426 22:55:35.492059 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1427 22:55:35.495479 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1428 22:55:35.499288 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1429 22:55:35.502606 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1430 22:55:35.506634 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1431 22:55:35.506718
1432 22:55:35.509981 CA PerBit enable=1, Macro0, CA PI delay=34
1433 22:55:35.510057
1434 22:55:35.513955 [CBTSetCACLKResult] CA Dly = 34
1435 22:55:35.514040 CS Dly: 6 (0~38)
1436 22:55:35.514107
1437 22:55:35.517388 ----->DramcWriteLeveling(PI) begin...
1438 22:55:35.517501 ==
1439 22:55:35.520974 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 22:55:35.524456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 22:55:35.524540 ==
1442 22:55:35.527899 Write leveling (Byte 0): 28 => 28
1443 22:55:35.531758 Write leveling (Byte 1): 30 => 30
1444 22:55:35.535411 DramcWriteLeveling(PI) end<-----
1445 22:55:35.535492
1446 22:55:35.535557 ==
1447 22:55:35.538406 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 22:55:35.541720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 22:55:35.541804 ==
1450 22:55:35.545177 [Gating] SW mode calibration
1451 22:55:35.551439 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1452 22:55:35.558252 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1453 22:55:35.561363 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1454 22:55:35.564976 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1455 22:55:35.571860 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1456 22:55:35.574573 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 22:55:35.577858 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 22:55:35.584644 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 22:55:35.588039 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 22:55:35.591385 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 22:55:35.597865 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 22:55:35.601110 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 22:55:35.604742 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 22:55:35.610915 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 22:55:35.614855 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 22:55:35.617737 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 22:55:35.624461 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 22:55:35.627995 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 22:55:35.631228 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 22:55:35.637997 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 22:55:35.641553 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1472 22:55:35.644307 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 22:55:35.650671 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 22:55:35.653792 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 22:55:35.657528 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 22:55:35.663866 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 22:55:35.667032 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 22:55:35.670595 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 22:55:35.677058 0 9 8 | B1->B0 | 2626 2524 | 1 1 | (0 0) (1 1)
1480 22:55:35.680628 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 22:55:35.683849 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 22:55:35.690552 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 22:55:35.693825 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 22:55:35.697061 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 22:55:35.703676 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 22:55:35.706783 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
1487 22:55:35.710015 0 10 8 | B1->B0 | 2f2f 2e2e | 0 0 | (1 1) (1 1)
1488 22:55:35.716879 0 10 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1489 22:55:35.720203 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 22:55:35.724016 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 22:55:35.729961 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 22:55:35.733538 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 22:55:35.736632 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 22:55:35.743533 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1495 22:55:35.746501 0 11 8 | B1->B0 | 3635 3838 | 1 0 | (0 0) (0 0)
1496 22:55:35.749737 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 22:55:35.756518 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 22:55:35.760541 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 22:55:35.762962 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 22:55:35.766510 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 22:55:35.772906 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 22:55:35.776112 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 22:55:35.779982 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1504 22:55:35.786476 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 22:55:35.789470 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 22:55:35.792677 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 22:55:35.799833 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 22:55:35.803262 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 22:55:35.806460 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 22:55:35.813157 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 22:55:35.816417 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 22:55:35.819638 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 22:55:35.826043 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 22:55:35.829304 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 22:55:35.832660 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 22:55:35.839346 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 22:55:35.842450 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 22:55:35.845798 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 22:55:35.852586 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1520 22:55:35.855807 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1521 22:55:35.859180 Total UI for P1: 0, mck2ui 16
1522 22:55:35.862877 best dqsien dly found for B0: ( 0, 14, 8)
1523 22:55:35.865844 Total UI for P1: 0, mck2ui 16
1524 22:55:35.869240 best dqsien dly found for B1: ( 0, 14, 8)
1525 22:55:35.872193 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1526 22:55:35.875722 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1527 22:55:35.875813
1528 22:55:35.879055 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1529 22:55:35.882557 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1530 22:55:35.885551 [Gating] SW calibration Done
1531 22:55:35.885640 ==
1532 22:55:35.888677 Dram Type= 6, Freq= 0, CH_1, rank 0
1533 22:55:35.892522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1534 22:55:35.896015 ==
1535 22:55:35.896105 RX Vref Scan: 0
1536 22:55:35.896191
1537 22:55:35.898813 RX Vref 0 -> 0, step: 1
1538 22:55:35.898908
1539 22:55:35.902089 RX Delay -130 -> 252, step: 16
1540 22:55:35.905528 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1541 22:55:35.908790 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1542 22:55:35.912097 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1543 22:55:35.915362 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1544 22:55:35.922079 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1545 22:55:35.925677 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1546 22:55:35.929291 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1547 22:55:35.932231 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1548 22:55:35.935752 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1549 22:55:35.942043 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1550 22:55:35.945392 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1551 22:55:35.948538 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1552 22:55:35.952085 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1553 22:55:35.955478 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1554 22:55:35.962094 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1555 22:55:35.965709 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1556 22:55:35.965807 ==
1557 22:55:35.968631 Dram Type= 6, Freq= 0, CH_1, rank 0
1558 22:55:35.972126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1559 22:55:35.972215 ==
1560 22:55:35.975342 DQS Delay:
1561 22:55:35.975430 DQS0 = 0, DQS1 = 0
1562 22:55:35.975517 DQM Delay:
1563 22:55:35.978443 DQM0 = 81, DQM1 = 71
1564 22:55:35.978530 DQ Delay:
1565 22:55:35.981920 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1566 22:55:35.985114 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1567 22:55:35.988332 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1568 22:55:35.991636 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1569 22:55:35.991726
1570 22:55:35.991813
1571 22:55:35.991894 ==
1572 22:55:35.994822 Dram Type= 6, Freq= 0, CH_1, rank 0
1573 22:55:36.001569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1574 22:55:36.001667 ==
1575 22:55:36.001755
1576 22:55:36.001836
1577 22:55:36.001915 TX Vref Scan disable
1578 22:55:36.005339 == TX Byte 0 ==
1579 22:55:36.008676 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1580 22:55:36.015338 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1581 22:55:36.015441 == TX Byte 1 ==
1582 22:55:36.018489 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1583 22:55:36.025203 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1584 22:55:36.025303 ==
1585 22:55:36.028614 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 22:55:36.031839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1587 22:55:36.031929 ==
1588 22:55:36.044332 TX Vref=22, minBit 1, minWin=27, winSum=440
1589 22:55:36.047455 TX Vref=24, minBit 1, minWin=27, winSum=442
1590 22:55:36.050948 TX Vref=26, minBit 1, minWin=27, winSum=445
1591 22:55:36.054486 TX Vref=28, minBit 4, minWin=27, winSum=446
1592 22:55:36.057848 TX Vref=30, minBit 5, minWin=27, winSum=448
1593 22:55:36.064322 TX Vref=32, minBit 5, minWin=27, winSum=446
1594 22:55:36.067589 [TxChooseVref] Worse bit 5, Min win 27, Win sum 448, Final Vref 30
1595 22:55:36.067684
1596 22:55:36.070996 Final TX Range 1 Vref 30
1597 22:55:36.071084
1598 22:55:36.071169 ==
1599 22:55:36.073938 Dram Type= 6, Freq= 0, CH_1, rank 0
1600 22:55:36.077968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1601 22:55:36.078059 ==
1602 22:55:36.078126
1603 22:55:36.078186
1604 22:55:36.081339 TX Vref Scan disable
1605 22:55:36.084503 == TX Byte 0 ==
1606 22:55:36.087942 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1607 22:55:36.091078 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1608 22:55:36.094725 == TX Byte 1 ==
1609 22:55:36.097665 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1610 22:55:36.100919 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1611 22:55:36.101011
1612 22:55:36.104108 [DATLAT]
1613 22:55:36.104194 Freq=800, CH1 RK0
1614 22:55:36.104261
1615 22:55:36.107589 DATLAT Default: 0xa
1616 22:55:36.107675 0, 0xFFFF, sum = 0
1617 22:55:36.111039 1, 0xFFFF, sum = 0
1618 22:55:36.111130 2, 0xFFFF, sum = 0
1619 22:55:36.114251 3, 0xFFFF, sum = 0
1620 22:55:36.114336 4, 0xFFFF, sum = 0
1621 22:55:36.117365 5, 0xFFFF, sum = 0
1622 22:55:36.117452 6, 0xFFFF, sum = 0
1623 22:55:36.120911 7, 0xFFFF, sum = 0
1624 22:55:36.124181 8, 0xFFFF, sum = 0
1625 22:55:36.124270 9, 0x0, sum = 1
1626 22:55:36.124338 10, 0x0, sum = 2
1627 22:55:36.127903 11, 0x0, sum = 3
1628 22:55:36.127990 12, 0x0, sum = 4
1629 22:55:36.131129 best_step = 10
1630 22:55:36.131223
1631 22:55:36.131291 ==
1632 22:55:36.134456 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 22:55:36.137751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 22:55:36.137838 ==
1635 22:55:36.140573 RX Vref Scan: 1
1636 22:55:36.140657
1637 22:55:36.140723 Set Vref Range= 32 -> 127
1638 22:55:36.144507
1639 22:55:36.144594 RX Vref 32 -> 127, step: 1
1640 22:55:36.144661
1641 22:55:36.147311 RX Delay -111 -> 252, step: 8
1642 22:55:36.147395
1643 22:55:36.151139 Set Vref, RX VrefLevel [Byte0]: 32
1644 22:55:36.154172 [Byte1]: 32
1645 22:55:36.154260
1646 22:55:36.157408 Set Vref, RX VrefLevel [Byte0]: 33
1647 22:55:36.160533 [Byte1]: 33
1648 22:55:36.164665
1649 22:55:36.164757 Set Vref, RX VrefLevel [Byte0]: 34
1650 22:55:36.168071 [Byte1]: 34
1651 22:55:36.172236
1652 22:55:36.172325 Set Vref, RX VrefLevel [Byte0]: 35
1653 22:55:36.175470 [Byte1]: 35
1654 22:55:36.180260
1655 22:55:36.180353 Set Vref, RX VrefLevel [Byte0]: 36
1656 22:55:36.183173 [Byte1]: 36
1657 22:55:36.187832
1658 22:55:36.187924 Set Vref, RX VrefLevel [Byte0]: 37
1659 22:55:36.190810 [Byte1]: 37
1660 22:55:36.195044
1661 22:55:36.195135 Set Vref, RX VrefLevel [Byte0]: 38
1662 22:55:36.198558 [Byte1]: 38
1663 22:55:36.202967
1664 22:55:36.203058 Set Vref, RX VrefLevel [Byte0]: 39
1665 22:55:36.206234 [Byte1]: 39
1666 22:55:36.210448
1667 22:55:36.210563 Set Vref, RX VrefLevel [Byte0]: 40
1668 22:55:36.213773 [Byte1]: 40
1669 22:55:36.218103
1670 22:55:36.218197 Set Vref, RX VrefLevel [Byte0]: 41
1671 22:55:36.221411 [Byte1]: 41
1672 22:55:36.225691
1673 22:55:36.225783 Set Vref, RX VrefLevel [Byte0]: 42
1674 22:55:36.229321 [Byte1]: 42
1675 22:55:36.233610
1676 22:55:36.233704 Set Vref, RX VrefLevel [Byte0]: 43
1677 22:55:36.236749 [Byte1]: 43
1678 22:55:36.241164
1679 22:55:36.241255 Set Vref, RX VrefLevel [Byte0]: 44
1680 22:55:36.244395 [Byte1]: 44
1681 22:55:36.249125
1682 22:55:36.249218 Set Vref, RX VrefLevel [Byte0]: 45
1683 22:55:36.252246 [Byte1]: 45
1684 22:55:36.256221
1685 22:55:36.256314 Set Vref, RX VrefLevel [Byte0]: 46
1686 22:55:36.259935 [Byte1]: 46
1687 22:55:36.263961
1688 22:55:36.264055 Set Vref, RX VrefLevel [Byte0]: 47
1689 22:55:36.267470 [Byte1]: 47
1690 22:55:36.272451
1691 22:55:36.272547 Set Vref, RX VrefLevel [Byte0]: 48
1692 22:55:36.275012 [Byte1]: 48
1693 22:55:36.279323
1694 22:55:36.279415 Set Vref, RX VrefLevel [Byte0]: 49
1695 22:55:36.283269 [Byte1]: 49
1696 22:55:36.287257
1697 22:55:36.287348 Set Vref, RX VrefLevel [Byte0]: 50
1698 22:55:36.290139 [Byte1]: 50
1699 22:55:36.294801
1700 22:55:36.294900 Set Vref, RX VrefLevel [Byte0]: 51
1701 22:55:36.298296 [Byte1]: 51
1702 22:55:36.302448
1703 22:55:36.302536 Set Vref, RX VrefLevel [Byte0]: 52
1704 22:55:36.306199 [Byte1]: 52
1705 22:55:36.309872
1706 22:55:36.309966 Set Vref, RX VrefLevel [Byte0]: 53
1707 22:55:36.313516 [Byte1]: 53
1708 22:55:36.317376
1709 22:55:36.317467 Set Vref, RX VrefLevel [Byte0]: 54
1710 22:55:36.321201 [Byte1]: 54
1711 22:55:36.325469
1712 22:55:36.325559 Set Vref, RX VrefLevel [Byte0]: 55
1713 22:55:36.328773 [Byte1]: 55
1714 22:55:36.332962
1715 22:55:36.333051 Set Vref, RX VrefLevel [Byte0]: 56
1716 22:55:36.336150 [Byte1]: 56
1717 22:55:36.340588
1718 22:55:36.340676 Set Vref, RX VrefLevel [Byte0]: 57
1719 22:55:36.344209 [Byte1]: 57
1720 22:55:36.348132
1721 22:55:36.348220 Set Vref, RX VrefLevel [Byte0]: 58
1722 22:55:36.351389 [Byte1]: 58
1723 22:55:36.355779
1724 22:55:36.355868 Set Vref, RX VrefLevel [Byte0]: 59
1725 22:55:36.358966 [Byte1]: 59
1726 22:55:36.363891
1727 22:55:36.364003 Set Vref, RX VrefLevel [Byte0]: 60
1728 22:55:36.367124 [Byte1]: 60
1729 22:55:36.371248
1730 22:55:36.371342 Set Vref, RX VrefLevel [Byte0]: 61
1731 22:55:36.374422 [Byte1]: 61
1732 22:55:36.378809
1733 22:55:36.378940 Set Vref, RX VrefLevel [Byte0]: 62
1734 22:55:36.381909 [Byte1]: 62
1735 22:55:36.386450
1736 22:55:36.386539 Set Vref, RX VrefLevel [Byte0]: 63
1737 22:55:36.390126 [Byte1]: 63
1738 22:55:36.393976
1739 22:55:36.394064 Set Vref, RX VrefLevel [Byte0]: 64
1740 22:55:36.397239 [Byte1]: 64
1741 22:55:36.401608
1742 22:55:36.401699 Set Vref, RX VrefLevel [Byte0]: 65
1743 22:55:36.405413 [Byte1]: 65
1744 22:55:36.409451
1745 22:55:36.409549 Set Vref, RX VrefLevel [Byte0]: 66
1746 22:55:36.412952 [Byte1]: 66
1747 22:55:36.417052
1748 22:55:36.417144 Set Vref, RX VrefLevel [Byte0]: 67
1749 22:55:36.420093 [Byte1]: 67
1750 22:55:36.424887
1751 22:55:36.424979 Set Vref, RX VrefLevel [Byte0]: 68
1752 22:55:36.427727 [Byte1]: 68
1753 22:55:36.432127
1754 22:55:36.432217 Set Vref, RX VrefLevel [Byte0]: 69
1755 22:55:36.435556 [Byte1]: 69
1756 22:55:36.439977
1757 22:55:36.440069 Set Vref, RX VrefLevel [Byte0]: 70
1758 22:55:36.443327 [Byte1]: 70
1759 22:55:36.447808
1760 22:55:36.447898 Set Vref, RX VrefLevel [Byte0]: 71
1761 22:55:36.451069 [Byte1]: 71
1762 22:55:36.455787
1763 22:55:36.455885 Set Vref, RX VrefLevel [Byte0]: 72
1764 22:55:36.458337 [Byte1]: 72
1765 22:55:36.463265
1766 22:55:36.463357 Set Vref, RX VrefLevel [Byte0]: 73
1767 22:55:36.466348 [Byte1]: 73
1768 22:55:36.470711
1769 22:55:36.470804 Set Vref, RX VrefLevel [Byte0]: 74
1770 22:55:36.473912 [Byte1]: 74
1771 22:55:36.478483
1772 22:55:36.478576 Set Vref, RX VrefLevel [Byte0]: 75
1773 22:55:36.481653 [Byte1]: 75
1774 22:55:36.485658
1775 22:55:36.485751 Set Vref, RX VrefLevel [Byte0]: 76
1776 22:55:36.488823 [Byte1]: 76
1777 22:55:36.493458
1778 22:55:36.493552 Set Vref, RX VrefLevel [Byte0]: 77
1779 22:55:36.496522 [Byte1]: 77
1780 22:55:36.501103
1781 22:55:36.501198 Final RX Vref Byte 0 = 60 to rank0
1782 22:55:36.504485 Final RX Vref Byte 1 = 55 to rank0
1783 22:55:36.507557 Final RX Vref Byte 0 = 60 to rank1
1784 22:55:36.510812 Final RX Vref Byte 1 = 55 to rank1==
1785 22:55:36.514234 Dram Type= 6, Freq= 0, CH_1, rank 0
1786 22:55:36.520832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1787 22:55:36.520946 ==
1788 22:55:36.521040 DQS Delay:
1789 22:55:36.524655 DQS0 = 0, DQS1 = 0
1790 22:55:36.524747 DQM Delay:
1791 22:55:36.524836 DQM0 = 81, DQM1 = 71
1792 22:55:36.527729 DQ Delay:
1793 22:55:36.530882 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =80
1794 22:55:36.533902 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1795 22:55:36.537276 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1796 22:55:36.540555 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1797 22:55:36.540649
1798 22:55:36.540735
1799 22:55:36.547498 [DQSOSCAuto] RK0, (LSB)MR18= 0x1620, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
1800 22:55:36.550989 CH1 RK0: MR19=606, MR18=1620
1801 22:55:36.557079 CH1_RK0: MR19=0x606, MR18=0x1620, DQSOSC=401, MR23=63, INC=91, DEC=61
1802 22:55:36.557182
1803 22:55:36.560335 ----->DramcWriteLeveling(PI) begin...
1804 22:55:36.560424 ==
1805 22:55:36.564143 Dram Type= 6, Freq= 0, CH_1, rank 1
1806 22:55:36.567278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1807 22:55:36.567370 ==
1808 22:55:36.570878 Write leveling (Byte 0): 26 => 26
1809 22:55:36.574081 Write leveling (Byte 1): 31 => 31
1810 22:55:36.577184 DramcWriteLeveling(PI) end<-----
1811 22:55:36.577274
1812 22:55:36.577362 ==
1813 22:55:36.580949 Dram Type= 6, Freq= 0, CH_1, rank 1
1814 22:55:36.583725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1815 22:55:36.583815 ==
1816 22:55:36.586967 [Gating] SW mode calibration
1817 22:55:36.593598 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1818 22:55:36.600407 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1819 22:55:36.603427 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1820 22:55:36.610358 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1821 22:55:36.613665 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1822 22:55:36.616872 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 22:55:36.623687 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 22:55:36.626661 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 22:55:36.629828 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 22:55:36.636684 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 22:55:36.640310 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 22:55:36.643483 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 22:55:36.649820 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 22:55:36.653108 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 22:55:36.656471 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 22:55:36.663819 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 22:55:36.666291 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 22:55:36.670053 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 22:55:36.673146 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 22:55:36.679787 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1837 22:55:36.682969 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1838 22:55:36.686544 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 22:55:36.692884 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 22:55:36.696189 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 22:55:36.699893 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 22:55:36.706275 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 22:55:36.709335 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 22:55:36.712962 0 9 4 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
1845 22:55:36.719518 0 9 8 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1846 22:55:36.723055 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 22:55:36.726183 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 22:55:36.733115 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 22:55:36.736252 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 22:55:36.739353 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 22:55:36.746175 0 10 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1852 22:55:36.749622 0 10 4 | B1->B0 | 3030 2c2c | 0 1 | (0 0) (1 1)
1853 22:55:36.752811 0 10 8 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
1854 22:55:36.759066 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 22:55:36.762366 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 22:55:36.765820 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 22:55:36.772461 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 22:55:36.775754 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 22:55:36.779329 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1860 22:55:36.786131 0 11 4 | B1->B0 | 2b2b 3939 | 0 1 | (0 0) (0 0)
1861 22:55:36.788955 0 11 8 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
1862 22:55:36.792131 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 22:55:36.798713 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 22:55:36.802264 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 22:55:36.805917 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 22:55:36.812411 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 22:55:36.815337 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 22:55:36.818488 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1869 22:55:36.825407 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 22:55:36.829082 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 22:55:36.831832 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 22:55:36.838517 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 22:55:36.841857 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 22:55:36.845271 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 22:55:36.852036 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 22:55:36.855554 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 22:55:36.859247 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 22:55:36.865477 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 22:55:36.869158 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 22:55:36.871911 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 22:55:36.875384 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 22:55:36.881840 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 22:55:36.885062 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 22:55:36.888917 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1885 22:55:36.895413 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1886 22:55:36.898667 Total UI for P1: 0, mck2ui 16
1887 22:55:36.901530 best dqsien dly found for B0: ( 0, 14, 4)
1888 22:55:36.905281 Total UI for P1: 0, mck2ui 16
1889 22:55:36.908675 best dqsien dly found for B1: ( 0, 14, 6)
1890 22:55:36.911722 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1891 22:55:36.914809 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1892 22:55:36.914946
1893 22:55:36.918163 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1894 22:55:36.922129 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1895 22:55:36.924980 [Gating] SW calibration Done
1896 22:55:36.925072 ==
1897 22:55:36.928278 Dram Type= 6, Freq= 0, CH_1, rank 1
1898 22:55:36.931696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1899 22:55:36.931788 ==
1900 22:55:36.934979 RX Vref Scan: 0
1901 22:55:36.935066
1902 22:55:36.935133 RX Vref 0 -> 0, step: 1
1903 22:55:36.938432
1904 22:55:36.938517 RX Delay -130 -> 252, step: 16
1905 22:55:36.945066 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1906 22:55:36.948195 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1907 22:55:36.951498 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1908 22:55:36.954505 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1909 22:55:36.958045 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1910 22:55:36.964668 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1911 22:55:36.967753 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1912 22:55:36.971484 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1913 22:55:36.974698 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1914 22:55:36.977714 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1915 22:55:36.984222 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1916 22:55:36.987597 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1917 22:55:36.991259 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1918 22:55:36.994197 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1919 22:55:36.997840 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1920 22:55:37.004168 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1921 22:55:37.004280 ==
1922 22:55:37.007559 Dram Type= 6, Freq= 0, CH_1, rank 1
1923 22:55:37.011263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1924 22:55:37.011365 ==
1925 22:55:37.011452 DQS Delay:
1926 22:55:37.014080 DQS0 = 0, DQS1 = 0
1927 22:55:37.014166 DQM Delay:
1928 22:55:37.017656 DQM0 = 78, DQM1 = 71
1929 22:55:37.017744 DQ Delay:
1930 22:55:37.020778 DQ0 =85, DQ1 =69, DQ2 =61, DQ3 =77
1931 22:55:37.024076 DQ4 =77, DQ5 =85, DQ6 =93, DQ7 =77
1932 22:55:37.027460 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1933 22:55:37.030782 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1934 22:55:37.030933
1935 22:55:37.031021
1936 22:55:37.031100 ==
1937 22:55:37.033820 Dram Type= 6, Freq= 0, CH_1, rank 1
1938 22:55:37.037277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1939 22:55:37.040889 ==
1940 22:55:37.040981
1941 22:55:37.041083
1942 22:55:37.041182 TX Vref Scan disable
1943 22:55:37.044120 == TX Byte 0 ==
1944 22:55:37.047631 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1945 22:55:37.050727 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1946 22:55:37.053826 == TX Byte 1 ==
1947 22:55:37.057564 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1948 22:55:37.060643 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1949 22:55:37.063986 ==
1950 22:55:37.067263 Dram Type= 6, Freq= 0, CH_1, rank 1
1951 22:55:37.070516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1952 22:55:37.070608 ==
1953 22:55:37.084008 TX Vref=22, minBit 0, minWin=28, winSum=450
1954 22:55:37.087293 TX Vref=24, minBit 1, minWin=28, winSum=457
1955 22:55:37.090130 TX Vref=26, minBit 5, minWin=28, winSum=458
1956 22:55:37.093495 TX Vref=28, minBit 1, minWin=28, winSum=461
1957 22:55:37.096800 TX Vref=30, minBit 1, minWin=28, winSum=464
1958 22:55:37.103743 TX Vref=32, minBit 1, minWin=28, winSum=464
1959 22:55:37.106373 [TxChooseVref] Worse bit 1, Min win 28, Win sum 464, Final Vref 30
1960 22:55:37.106468
1961 22:55:37.109989 Final TX Range 1 Vref 30
1962 22:55:37.110110
1963 22:55:37.110234 ==
1964 22:55:37.113010 Dram Type= 6, Freq= 0, CH_1, rank 1
1965 22:55:37.116472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1966 22:55:37.119825 ==
1967 22:55:37.119918
1968 22:55:37.119987
1969 22:55:37.120094 TX Vref Scan disable
1970 22:55:37.123376 == TX Byte 0 ==
1971 22:55:37.126864 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1972 22:55:37.130222 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1973 22:55:37.133287 == TX Byte 1 ==
1974 22:55:37.137220 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1975 22:55:37.143198 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1976 22:55:37.143303
1977 22:55:37.143372 [DATLAT]
1978 22:55:37.143433 Freq=800, CH1 RK1
1979 22:55:37.143493
1980 22:55:37.146616 DATLAT Default: 0xa
1981 22:55:37.146699 0, 0xFFFF, sum = 0
1982 22:55:37.149716 1, 0xFFFF, sum = 0
1983 22:55:37.153317 2, 0xFFFF, sum = 0
1984 22:55:37.153406 3, 0xFFFF, sum = 0
1985 22:55:37.156672 4, 0xFFFF, sum = 0
1986 22:55:37.156759 5, 0xFFFF, sum = 0
1987 22:55:37.159852 6, 0xFFFF, sum = 0
1988 22:55:37.159938 7, 0xFFFF, sum = 0
1989 22:55:37.162971 8, 0xFFFF, sum = 0
1990 22:55:37.163057 9, 0x0, sum = 1
1991 22:55:37.166413 10, 0x0, sum = 2
1992 22:55:37.166499 11, 0x0, sum = 3
1993 22:55:37.166567 12, 0x0, sum = 4
1994 22:55:37.169834 best_step = 10
1995 22:55:37.169918
1996 22:55:37.169984 ==
1997 22:55:37.173256 Dram Type= 6, Freq= 0, CH_1, rank 1
1998 22:55:37.176532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1999 22:55:37.176622 ==
2000 22:55:37.179739 RX Vref Scan: 0
2001 22:55:37.179824
2002 22:55:37.179891 RX Vref 0 -> 0, step: 1
2003 22:55:37.183236
2004 22:55:37.183319 RX Delay -111 -> 252, step: 8
2005 22:55:37.190062 iDelay=209, Bit 0, Center 84 (-39 ~ 208) 248
2006 22:55:37.193876 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2007 22:55:37.197035 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2008 22:55:37.199990 iDelay=209, Bit 3, Center 76 (-47 ~ 200) 248
2009 22:55:37.206805 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2010 22:55:37.210003 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2011 22:55:37.213294 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2012 22:55:37.216679 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2013 22:55:37.219880 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2014 22:55:37.223574 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2015 22:55:37.230060 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2016 22:55:37.233022 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2017 22:55:37.236019 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2018 22:55:37.239448 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2019 22:55:37.246073 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2020 22:55:37.249790 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2021 22:55:37.249886 ==
2022 22:55:37.252915 Dram Type= 6, Freq= 0, CH_1, rank 1
2023 22:55:37.256573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2024 22:55:37.256687 ==
2025 22:55:37.259379 DQS Delay:
2026 22:55:37.259464 DQS0 = 0, DQS1 = 0
2027 22:55:37.259530 DQM Delay:
2028 22:55:37.262766 DQM0 = 78, DQM1 = 74
2029 22:55:37.262909 DQ Delay:
2030 22:55:37.265758 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =76
2031 22:55:37.269715 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2032 22:55:37.272430 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
2033 22:55:37.276002 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =80
2034 22:55:37.276091
2035 22:55:37.276157
2036 22:55:37.286012 [DQSOSCAuto] RK1, (LSB)MR18= 0x2039, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2037 22:55:37.289281 CH1 RK1: MR19=606, MR18=2039
2038 22:55:37.292588 CH1_RK1: MR19=0x606, MR18=0x2039, DQSOSC=395, MR23=63, INC=94, DEC=63
2039 22:55:37.296235 [RxdqsGatingPostProcess] freq 800
2040 22:55:37.302504 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2041 22:55:37.305786 Pre-setting of DQS Precalculation
2042 22:55:37.308965 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2043 22:55:37.319177 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2044 22:55:37.325639 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2045 22:55:37.325749
2046 22:55:37.325813
2047 22:55:37.328715 [Calibration Summary] 1600 Mbps
2048 22:55:37.328801 CH 0, Rank 0
2049 22:55:37.332163 SW Impedance : PASS
2050 22:55:37.332274 DUTY Scan : NO K
2051 22:55:37.335136 ZQ Calibration : PASS
2052 22:55:37.338643 Jitter Meter : NO K
2053 22:55:37.338731 CBT Training : PASS
2054 22:55:37.341964 Write leveling : PASS
2055 22:55:37.345227 RX DQS gating : PASS
2056 22:55:37.345324 RX DQ/DQS(RDDQC) : PASS
2057 22:55:37.348918 TX DQ/DQS : PASS
2058 22:55:37.352190 RX DATLAT : PASS
2059 22:55:37.352277 RX DQ/DQS(Engine): PASS
2060 22:55:37.355296 TX OE : NO K
2061 22:55:37.355384 All Pass.
2062 22:55:37.355449
2063 22:55:37.358462 CH 0, Rank 1
2064 22:55:37.358545 SW Impedance : PASS
2065 22:55:37.362040 DUTY Scan : NO K
2066 22:55:37.365706 ZQ Calibration : PASS
2067 22:55:37.365794 Jitter Meter : NO K
2068 22:55:37.368500 CBT Training : PASS
2069 22:55:37.371977 Write leveling : PASS
2070 22:55:37.372066 RX DQS gating : PASS
2071 22:55:37.375180 RX DQ/DQS(RDDQC) : PASS
2072 22:55:37.375267 TX DQ/DQS : PASS
2073 22:55:37.378725 RX DATLAT : PASS
2074 22:55:37.381794 RX DQ/DQS(Engine): PASS
2075 22:55:37.381882 TX OE : NO K
2076 22:55:37.384968 All Pass.
2077 22:55:37.385053
2078 22:55:37.385132 CH 1, Rank 0
2079 22:55:37.388844 SW Impedance : PASS
2080 22:55:37.388929 DUTY Scan : NO K
2081 22:55:37.391773 ZQ Calibration : PASS
2082 22:55:37.395057 Jitter Meter : NO K
2083 22:55:37.395142 CBT Training : PASS
2084 22:55:37.398236 Write leveling : PASS
2085 22:55:37.401533 RX DQS gating : PASS
2086 22:55:37.401619 RX DQ/DQS(RDDQC) : PASS
2087 22:55:37.404755 TX DQ/DQS : PASS
2088 22:55:37.408111 RX DATLAT : PASS
2089 22:55:37.408195 RX DQ/DQS(Engine): PASS
2090 22:55:37.411317 TX OE : NO K
2091 22:55:37.411438 All Pass.
2092 22:55:37.411545
2093 22:55:37.415170 CH 1, Rank 1
2094 22:55:37.415253 SW Impedance : PASS
2095 22:55:37.418431 DUTY Scan : NO K
2096 22:55:37.421716 ZQ Calibration : PASS
2097 22:55:37.421805 Jitter Meter : NO K
2098 22:55:37.425173 CBT Training : PASS
2099 22:55:37.427998 Write leveling : PASS
2100 22:55:37.428082 RX DQS gating : PASS
2101 22:55:37.431109 RX DQ/DQS(RDDQC) : PASS
2102 22:55:37.434310 TX DQ/DQS : PASS
2103 22:55:37.434397 RX DATLAT : PASS
2104 22:55:37.437855 RX DQ/DQS(Engine): PASS
2105 22:55:37.437941 TX OE : NO K
2106 22:55:37.440953 All Pass.
2107 22:55:37.441039
2108 22:55:37.441104 DramC Write-DBI off
2109 22:55:37.444351 PER_BANK_REFRESH: Hybrid Mode
2110 22:55:37.447901 TX_TRACKING: ON
2111 22:55:37.451280 [GetDramInforAfterCalByMRR] Vendor 6.
2112 22:55:37.454762 [GetDramInforAfterCalByMRR] Revision 606.
2113 22:55:37.457658 [GetDramInforAfterCalByMRR] Revision 2 0.
2114 22:55:37.457748 MR0 0x3b3b
2115 22:55:37.460954 MR8 0x5151
2116 22:55:37.464248 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2117 22:55:37.464337
2118 22:55:37.464404 MR0 0x3b3b
2119 22:55:37.464464 MR8 0x5151
2120 22:55:37.467814 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2121 22:55:37.467901
2122 22:55:37.477922 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2123 22:55:37.480873 [FAST_K] Save calibration result to emmc
2124 22:55:37.484032 [FAST_K] Save calibration result to emmc
2125 22:55:37.487707 dram_init: config_dvfs: 1
2126 22:55:37.490864 dramc_set_vcore_voltage set vcore to 662500
2127 22:55:37.494325 Read voltage for 1200, 2
2128 22:55:37.494415 Vio18 = 0
2129 22:55:37.497651 Vcore = 662500
2130 22:55:37.497736 Vdram = 0
2131 22:55:37.497802 Vddq = 0
2132 22:55:37.497861 Vmddr = 0
2133 22:55:37.504152 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2134 22:55:37.510929 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2135 22:55:37.511117 MEM_TYPE=3, freq_sel=15
2136 22:55:37.514061 sv_algorithm_assistance_LP4_1600
2137 22:55:37.517309 ============ PULL DRAM RESETB DOWN ============
2138 22:55:37.524311 ========== PULL DRAM RESETB DOWN end =========
2139 22:55:37.527654 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2140 22:55:37.530471 ===================================
2141 22:55:37.534120 LPDDR4 DRAM CONFIGURATION
2142 22:55:37.537310 ===================================
2143 22:55:37.537413 EX_ROW_EN[0] = 0x0
2144 22:55:37.540521 EX_ROW_EN[1] = 0x0
2145 22:55:37.540607 LP4Y_EN = 0x0
2146 22:55:37.544049 WORK_FSP = 0x0
2147 22:55:37.544134 WL = 0x4
2148 22:55:37.547109 RL = 0x4
2149 22:55:37.550687 BL = 0x2
2150 22:55:37.550781 RPST = 0x0
2151 22:55:37.553808 RD_PRE = 0x0
2152 22:55:37.553894 WR_PRE = 0x1
2153 22:55:37.557072 WR_PST = 0x0
2154 22:55:37.557161 DBI_WR = 0x0
2155 22:55:37.560770 DBI_RD = 0x0
2156 22:55:37.560855 OTF = 0x1
2157 22:55:37.564169 ===================================
2158 22:55:37.567003 ===================================
2159 22:55:37.570606 ANA top config
2160 22:55:37.573859 ===================================
2161 22:55:37.573948 DLL_ASYNC_EN = 0
2162 22:55:37.576979 ALL_SLAVE_EN = 0
2163 22:55:37.580260 NEW_RANK_MODE = 1
2164 22:55:37.583367 DLL_IDLE_MODE = 1
2165 22:55:37.583464 LP45_APHY_COMB_EN = 1
2166 22:55:37.586851 TX_ODT_DIS = 1
2167 22:55:37.590433 NEW_8X_MODE = 1
2168 22:55:37.593648 ===================================
2169 22:55:37.597166 ===================================
2170 22:55:37.600389 data_rate = 2400
2171 22:55:37.603300 CKR = 1
2172 22:55:37.607236 DQ_P2S_RATIO = 8
2173 22:55:37.610043 ===================================
2174 22:55:37.610128 CA_P2S_RATIO = 8
2175 22:55:37.613905 DQ_CA_OPEN = 0
2176 22:55:37.616733 DQ_SEMI_OPEN = 0
2177 22:55:37.619872 CA_SEMI_OPEN = 0
2178 22:55:37.623778 CA_FULL_RATE = 0
2179 22:55:37.626780 DQ_CKDIV4_EN = 0
2180 22:55:37.626916 CA_CKDIV4_EN = 0
2181 22:55:37.630183 CA_PREDIV_EN = 0
2182 22:55:37.633400 PH8_DLY = 17
2183 22:55:37.636965 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2184 22:55:37.640035 DQ_AAMCK_DIV = 4
2185 22:55:37.643559 CA_AAMCK_DIV = 4
2186 22:55:37.643648 CA_ADMCK_DIV = 4
2187 22:55:37.646796 DQ_TRACK_CA_EN = 0
2188 22:55:37.649759 CA_PICK = 1200
2189 22:55:37.653329 CA_MCKIO = 1200
2190 22:55:37.656305 MCKIO_SEMI = 0
2191 22:55:37.659817 PLL_FREQ = 2366
2192 22:55:37.662957 DQ_UI_PI_RATIO = 32
2193 22:55:37.663043 CA_UI_PI_RATIO = 0
2194 22:55:37.666905 ===================================
2195 22:55:37.669775 ===================================
2196 22:55:37.672997 memory_type:LPDDR4
2197 22:55:37.676665 GP_NUM : 10
2198 22:55:37.676753 SRAM_EN : 1
2199 22:55:37.679860 MD32_EN : 0
2200 22:55:37.682778 ===================================
2201 22:55:37.686145 [ANA_INIT] >>>>>>>>>>>>>>
2202 22:55:37.689587 <<<<<< [CONFIGURE PHASE]: ANA_TX
2203 22:55:37.693125 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2204 22:55:37.696435 ===================================
2205 22:55:37.696525 data_rate = 2400,PCW = 0X5b00
2206 22:55:37.699480 ===================================
2207 22:55:37.703269 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2208 22:55:37.709679 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2209 22:55:37.716360 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2210 22:55:37.719608 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2211 22:55:37.722960 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2212 22:55:37.726333 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2213 22:55:37.729678 [ANA_INIT] flow start
2214 22:55:37.732816 [ANA_INIT] PLL >>>>>>>>
2215 22:55:37.732930 [ANA_INIT] PLL <<<<<<<<
2216 22:55:37.736349 [ANA_INIT] MIDPI >>>>>>>>
2217 22:55:37.739591 [ANA_INIT] MIDPI <<<<<<<<
2218 22:55:37.739700 [ANA_INIT] DLL >>>>>>>>
2219 22:55:37.743096 [ANA_INIT] DLL <<<<<<<<
2220 22:55:37.745807 [ANA_INIT] flow end
2221 22:55:37.749595 ============ LP4 DIFF to SE enter ============
2222 22:55:37.752497 ============ LP4 DIFF to SE exit ============
2223 22:55:37.755893 [ANA_INIT] <<<<<<<<<<<<<
2224 22:55:37.759370 [Flow] Enable top DCM control >>>>>
2225 22:55:37.762486 [Flow] Enable top DCM control <<<<<
2226 22:55:37.766077 Enable DLL master slave shuffle
2227 22:55:37.769664 ==============================================================
2228 22:55:37.772739 Gating Mode config
2229 22:55:37.779291 ==============================================================
2230 22:55:37.779394 Config description:
2231 22:55:37.789105 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2232 22:55:37.795889 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2233 22:55:37.799442 SELPH_MODE 0: By rank 1: By Phase
2234 22:55:37.806143 ==============================================================
2235 22:55:37.809229 GAT_TRACK_EN = 1
2236 22:55:37.812357 RX_GATING_MODE = 2
2237 22:55:37.816134 RX_GATING_TRACK_MODE = 2
2238 22:55:37.819367 SELPH_MODE = 1
2239 22:55:37.822665 PICG_EARLY_EN = 1
2240 22:55:37.825921 VALID_LAT_VALUE = 1
2241 22:55:37.829208 ==============================================================
2242 22:55:37.832589 Enter into Gating configuration >>>>
2243 22:55:37.835998 Exit from Gating configuration <<<<
2244 22:55:37.839071 Enter into DVFS_PRE_config >>>>>
2245 22:55:37.849233 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2246 22:55:37.852897 Exit from DVFS_PRE_config <<<<<
2247 22:55:37.855631 Enter into PICG configuration >>>>
2248 22:55:37.858834 Exit from PICG configuration <<<<
2249 22:55:37.861890 [RX_INPUT] configuration >>>>>
2250 22:55:37.865577 [RX_INPUT] configuration <<<<<
2251 22:55:37.871987 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2252 22:55:37.875270 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2253 22:55:37.881820 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2254 22:55:37.888361 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2255 22:55:37.895558 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2256 22:55:37.902092 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2257 22:55:37.905397 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2258 22:55:37.908375 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2259 22:55:37.911543 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2260 22:55:37.918445 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2261 22:55:37.921676 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2262 22:55:37.924952 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2263 22:55:37.928599 ===================================
2264 22:55:37.931729 LPDDR4 DRAM CONFIGURATION
2265 22:55:37.935177 ===================================
2266 22:55:37.935268 EX_ROW_EN[0] = 0x0
2267 22:55:37.938416 EX_ROW_EN[1] = 0x0
2268 22:55:37.941813 LP4Y_EN = 0x0
2269 22:55:37.941902 WORK_FSP = 0x0
2270 22:55:37.945014 WL = 0x4
2271 22:55:37.945109 RL = 0x4
2272 22:55:37.948189 BL = 0x2
2273 22:55:37.948277 RPST = 0x0
2274 22:55:37.951662 RD_PRE = 0x0
2275 22:55:37.951749 WR_PRE = 0x1
2276 22:55:37.955041 WR_PST = 0x0
2277 22:55:37.955126 DBI_WR = 0x0
2278 22:55:37.958663 DBI_RD = 0x0
2279 22:55:37.958749 OTF = 0x1
2280 22:55:37.961734 ===================================
2281 22:55:37.965558 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2282 22:55:37.971519 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2283 22:55:37.974570 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2284 22:55:37.978429 ===================================
2285 22:55:37.981773 LPDDR4 DRAM CONFIGURATION
2286 22:55:37.984959 ===================================
2287 22:55:37.985049 EX_ROW_EN[0] = 0x10
2288 22:55:37.987827 EX_ROW_EN[1] = 0x0
2289 22:55:37.991480 LP4Y_EN = 0x0
2290 22:55:37.991568 WORK_FSP = 0x0
2291 22:55:37.994993 WL = 0x4
2292 22:55:37.995079 RL = 0x4
2293 22:55:37.997832 BL = 0x2
2294 22:55:37.997915 RPST = 0x0
2295 22:55:38.001249 RD_PRE = 0x0
2296 22:55:38.001339 WR_PRE = 0x1
2297 22:55:38.004693 WR_PST = 0x0
2298 22:55:38.004779 DBI_WR = 0x0
2299 22:55:38.007653 DBI_RD = 0x0
2300 22:55:38.007737 OTF = 0x1
2301 22:55:38.011297 ===================================
2302 22:55:38.018138 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2303 22:55:38.018261 ==
2304 22:55:38.020964 Dram Type= 6, Freq= 0, CH_0, rank 0
2305 22:55:38.024608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2306 22:55:38.028028 ==
2307 22:55:38.028117 [Duty_Offset_Calibration]
2308 22:55:38.031360 B0:2 B1:0 CA:3
2309 22:55:38.031443
2310 22:55:38.034544 [DutyScan_Calibration_Flow] k_type=0
2311 22:55:38.042807
2312 22:55:38.042957 ==CLK 0==
2313 22:55:38.046182 Final CLK duty delay cell = 0
2314 22:55:38.050131 [0] MAX Duty = 5031%(X100), DQS PI = 12
2315 22:55:38.052918 [0] MIN Duty = 4875%(X100), DQS PI = 54
2316 22:55:38.055837 [0] AVG Duty = 4953%(X100)
2317 22:55:38.055923
2318 22:55:38.059607 CH0 CLK Duty spec in!! Max-Min= 156%
2319 22:55:38.062505 [DutyScan_Calibration_Flow] ====Done====
2320 22:55:38.062589
2321 22:55:38.066069 [DutyScan_Calibration_Flow] k_type=1
2322 22:55:38.081559
2323 22:55:38.081706 ==DQS 0 ==
2324 22:55:38.084620 Final DQS duty delay cell = 0
2325 22:55:38.087841 [0] MAX Duty = 5062%(X100), DQS PI = 12
2326 22:55:38.091975 [0] MIN Duty = 4907%(X100), DQS PI = 2
2327 22:55:38.092073 [0] AVG Duty = 4984%(X100)
2328 22:55:38.094475
2329 22:55:38.094558 ==DQS 1 ==
2330 22:55:38.098104 Final DQS duty delay cell = -4
2331 22:55:38.101399 [-4] MAX Duty = 5000%(X100), DQS PI = 36
2332 22:55:38.104652 [-4] MIN Duty = 4875%(X100), DQS PI = 16
2333 22:55:38.107497 [-4] AVG Duty = 4937%(X100)
2334 22:55:38.107582
2335 22:55:38.110852 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2336 22:55:38.110954
2337 22:55:38.114481 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2338 22:55:38.117435 [DutyScan_Calibration_Flow] ====Done====
2339 22:55:38.117524
2340 22:55:38.120805 [DutyScan_Calibration_Flow] k_type=3
2341 22:55:38.137923
2342 22:55:38.138072 ==DQM 0 ==
2343 22:55:38.141113 Final DQM duty delay cell = 0
2344 22:55:38.144861 [0] MAX Duty = 5124%(X100), DQS PI = 28
2345 22:55:38.148120 [0] MIN Duty = 4876%(X100), DQS PI = 0
2346 22:55:38.151489 [0] AVG Duty = 5000%(X100)
2347 22:55:38.151579
2348 22:55:38.151647 ==DQM 1 ==
2349 22:55:38.154638 Final DQM duty delay cell = 0
2350 22:55:38.157955 [0] MAX Duty = 4938%(X100), DQS PI = 0
2351 22:55:38.161214 [0] MIN Duty = 4876%(X100), DQS PI = 8
2352 22:55:38.164838 [0] AVG Duty = 4907%(X100)
2353 22:55:38.164929
2354 22:55:38.167738 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2355 22:55:38.167825
2356 22:55:38.171161 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2357 22:55:38.174354 [DutyScan_Calibration_Flow] ====Done====
2358 22:55:38.174441
2359 22:55:38.177876 [DutyScan_Calibration_Flow] k_type=2
2360 22:55:38.192566
2361 22:55:38.192716 ==DQ 0 ==
2362 22:55:38.196035 Final DQ duty delay cell = -4
2363 22:55:38.199881 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2364 22:55:38.202467 [-4] MIN Duty = 4907%(X100), DQS PI = 42
2365 22:55:38.205945 [-4] AVG Duty = 4969%(X100)
2366 22:55:38.206033
2367 22:55:38.206100 ==DQ 1 ==
2368 22:55:38.209315 Final DQ duty delay cell = -4
2369 22:55:38.212688 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2370 22:55:38.216251 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2371 22:55:38.219017 [-4] AVG Duty = 4938%(X100)
2372 22:55:38.219110
2373 22:55:38.222543 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2374 22:55:38.222632
2375 22:55:38.226121 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2376 22:55:38.229700 [DutyScan_Calibration_Flow] ====Done====
2377 22:55:38.229793 ==
2378 22:55:38.232554 Dram Type= 6, Freq= 0, CH_1, rank 0
2379 22:55:38.236142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2380 22:55:38.236232 ==
2381 22:55:38.239377 [Duty_Offset_Calibration]
2382 22:55:38.239463 B0:1 B1:-2 CA:0
2383 22:55:38.239530
2384 22:55:38.242698 [DutyScan_Calibration_Flow] k_type=0
2385 22:55:38.253074
2386 22:55:38.253202 ==CLK 0==
2387 22:55:38.256871 Final CLK duty delay cell = 0
2388 22:55:38.260005 [0] MAX Duty = 5031%(X100), DQS PI = 18
2389 22:55:38.263329 [0] MIN Duty = 4876%(X100), DQS PI = 60
2390 22:55:38.266444 [0] AVG Duty = 4953%(X100)
2391 22:55:38.266533
2392 22:55:38.269793 CH1 CLK Duty spec in!! Max-Min= 155%
2393 22:55:38.273410 [DutyScan_Calibration_Flow] ====Done====
2394 22:55:38.273498
2395 22:55:38.276387 [DutyScan_Calibration_Flow] k_type=1
2396 22:55:38.292092
2397 22:55:38.292238 ==DQS 0 ==
2398 22:55:38.295301 Final DQS duty delay cell = -4
2399 22:55:38.298341 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2400 22:55:38.301864 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2401 22:55:38.305817 [-4] AVG Duty = 4969%(X100)
2402 22:55:38.305910
2403 22:55:38.305978 ==DQS 1 ==
2404 22:55:38.308787 Final DQS duty delay cell = 0
2405 22:55:38.311939 [0] MAX Duty = 5093%(X100), DQS PI = 0
2406 22:55:38.314764 [0] MIN Duty = 4875%(X100), DQS PI = 26
2407 22:55:38.318155 [0] AVG Duty = 4984%(X100)
2408 22:55:38.318246
2409 22:55:38.321903 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2410 22:55:38.321996
2411 22:55:38.325021 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2412 22:55:38.328130 [DutyScan_Calibration_Flow] ====Done====
2413 22:55:38.328217
2414 22:55:38.331202 [DutyScan_Calibration_Flow] k_type=3
2415 22:55:38.349378
2416 22:55:38.349534 ==DQM 0 ==
2417 22:55:38.353002 Final DQM duty delay cell = 4
2418 22:55:38.355813 [4] MAX Duty = 5156%(X100), DQS PI = 20
2419 22:55:38.359397 [4] MIN Duty = 5031%(X100), DQS PI = 50
2420 22:55:38.362639 [4] AVG Duty = 5093%(X100)
2421 22:55:38.362728
2422 22:55:38.362795 ==DQM 1 ==
2423 22:55:38.366008 Final DQM duty delay cell = 0
2424 22:55:38.369291 [0] MAX Duty = 5031%(X100), DQS PI = 20
2425 22:55:38.372398 [0] MIN Duty = 4907%(X100), DQS PI = 4
2426 22:55:38.375568 [0] AVG Duty = 4969%(X100)
2427 22:55:38.375654
2428 22:55:38.378848 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2429 22:55:38.378946
2430 22:55:38.382687 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2431 22:55:38.385685 [DutyScan_Calibration_Flow] ====Done====
2432 22:55:38.385771
2433 22:55:38.389590 [DutyScan_Calibration_Flow] k_type=2
2434 22:55:38.405957
2435 22:55:38.406108 ==DQ 0 ==
2436 22:55:38.409237 Final DQ duty delay cell = 0
2437 22:55:38.412546 [0] MAX Duty = 5062%(X100), DQS PI = 18
2438 22:55:38.416011 [0] MIN Duty = 4938%(X100), DQS PI = 54
2439 22:55:38.416111 [0] AVG Duty = 5000%(X100)
2440 22:55:38.419287
2441 22:55:38.419374 ==DQ 1 ==
2442 22:55:38.422196 Final DQ duty delay cell = 0
2443 22:55:38.425675 [0] MAX Duty = 5125%(X100), DQS PI = 34
2444 22:55:38.429021 [0] MIN Duty = 4969%(X100), DQS PI = 26
2445 22:55:38.429112 [0] AVG Duty = 5047%(X100)
2446 22:55:38.429199
2447 22:55:38.432366 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2448 22:55:38.435792
2449 22:55:38.438792 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2450 22:55:38.442336 [DutyScan_Calibration_Flow] ====Done====
2451 22:55:38.445385 nWR fixed to 30
2452 22:55:38.445474 [ModeRegInit_LP4] CH0 RK0
2453 22:55:38.448895 [ModeRegInit_LP4] CH0 RK1
2454 22:55:38.452123 [ModeRegInit_LP4] CH1 RK0
2455 22:55:38.455647 [ModeRegInit_LP4] CH1 RK1
2456 22:55:38.455735 match AC timing 7
2457 22:55:38.458801 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2458 22:55:38.465459 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2459 22:55:38.468814 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2460 22:55:38.475358 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2461 22:55:38.478661 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2462 22:55:38.478774 ==
2463 22:55:38.481880 Dram Type= 6, Freq= 0, CH_0, rank 0
2464 22:55:38.485238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2465 22:55:38.485320 ==
2466 22:55:38.491744 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2467 22:55:38.498347 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2468 22:55:38.505592 [CA 0] Center 40 (10~71) winsize 62
2469 22:55:38.508760 [CA 1] Center 40 (10~70) winsize 61
2470 22:55:38.512216 [CA 2] Center 36 (6~66) winsize 61
2471 22:55:38.515759 [CA 3] Center 35 (5~66) winsize 62
2472 22:55:38.519465 [CA 4] Center 34 (4~65) winsize 62
2473 22:55:38.522304 [CA 5] Center 33 (3~64) winsize 62
2474 22:55:38.522393
2475 22:55:38.525545 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2476 22:55:38.525633
2477 22:55:38.528855 [CATrainingPosCal] consider 1 rank data
2478 22:55:38.532040 u2DelayCellTimex100 = 270/100 ps
2479 22:55:38.538814 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2480 22:55:38.542194 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2481 22:55:38.545250 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2482 22:55:38.548686 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2483 22:55:38.551817 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2484 22:55:38.555165 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2485 22:55:38.555258
2486 22:55:38.558383 CA PerBit enable=1, Macro0, CA PI delay=33
2487 22:55:38.558471
2488 22:55:38.561708 [CBTSetCACLKResult] CA Dly = 33
2489 22:55:38.565458 CS Dly: 7 (0~38)
2490 22:55:38.565552 ==
2491 22:55:38.568219 Dram Type= 6, Freq= 0, CH_0, rank 1
2492 22:55:38.571549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2493 22:55:38.571639 ==
2494 22:55:38.578369 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2495 22:55:38.581703 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2496 22:55:38.591977 [CA 0] Center 40 (10~70) winsize 61
2497 22:55:38.595566 [CA 1] Center 40 (10~70) winsize 61
2498 22:55:38.598410 [CA 2] Center 35 (5~66) winsize 62
2499 22:55:38.601816 [CA 3] Center 35 (5~66) winsize 62
2500 22:55:38.605424 [CA 4] Center 34 (3~65) winsize 63
2501 22:55:38.609023 [CA 5] Center 33 (3~64) winsize 62
2502 22:55:38.609114
2503 22:55:38.611906 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2504 22:55:38.611991
2505 22:55:38.615115 [CATrainingPosCal] consider 2 rank data
2506 22:55:38.618678 u2DelayCellTimex100 = 270/100 ps
2507 22:55:38.621694 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2508 22:55:38.628450 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2509 22:55:38.631644 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2510 22:55:38.634947 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2511 22:55:38.638253 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2512 22:55:38.641528 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2513 22:55:38.641620
2514 22:55:38.645278 CA PerBit enable=1, Macro0, CA PI delay=33
2515 22:55:38.645367
2516 22:55:38.648508 [CBTSetCACLKResult] CA Dly = 33
2517 22:55:38.651538 CS Dly: 8 (0~40)
2518 22:55:38.651628
2519 22:55:38.654656 ----->DramcWriteLeveling(PI) begin...
2520 22:55:38.654744 ==
2521 22:55:38.658322 Dram Type= 6, Freq= 0, CH_0, rank 0
2522 22:55:38.661593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2523 22:55:38.661685 ==
2524 22:55:38.665132 Write leveling (Byte 0): 34 => 34
2525 22:55:38.667964 Write leveling (Byte 1): 29 => 29
2526 22:55:38.671249 DramcWriteLeveling(PI) end<-----
2527 22:55:38.671339
2528 22:55:38.671405 ==
2529 22:55:38.674995 Dram Type= 6, Freq= 0, CH_0, rank 0
2530 22:55:38.678085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2531 22:55:38.678174 ==
2532 22:55:38.681429 [Gating] SW mode calibration
2533 22:55:38.688028 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2534 22:55:38.694496 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2535 22:55:38.698250 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 22:55:38.701804 0 15 4 | B1->B0 | 2626 3232 | 0 1 | (0 0) (1 1)
2537 22:55:38.708003 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 22:55:38.711153 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 22:55:38.714397 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 22:55:38.721135 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 22:55:38.724192 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2542 22:55:38.727900 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2543 22:55:38.734393 1 0 0 | B1->B0 | 3434 2e2e | 0 0 | (0 0) (0 1)
2544 22:55:38.737566 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 22:55:38.740983 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 22:55:38.747820 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 22:55:38.751022 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 22:55:38.754388 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 22:55:38.760876 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 22:55:38.764381 1 0 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2551 22:55:38.767286 1 1 0 | B1->B0 | 2727 3232 | 1 0 | (0 0) (0 0)
2552 22:55:38.774462 1 1 4 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2553 22:55:38.777342 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 22:55:38.780610 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 22:55:38.787598 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 22:55:38.790943 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 22:55:38.794217 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 22:55:38.800669 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2559 22:55:38.803796 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2560 22:55:38.807019 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 22:55:38.813624 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 22:55:38.817018 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 22:55:38.820591 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 22:55:38.827096 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 22:55:38.830243 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 22:55:38.833832 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 22:55:38.840522 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 22:55:38.843471 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 22:55:38.846817 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 22:55:38.853612 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 22:55:38.856973 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 22:55:38.860096 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 22:55:38.866751 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2574 22:55:38.870206 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 22:55:38.873407 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2576 22:55:38.879929 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2577 22:55:38.880039 Total UI for P1: 0, mck2ui 16
2578 22:55:38.883367 best dqsien dly found for B0: ( 1, 4, 0)
2579 22:55:38.889948 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2580 22:55:38.893231 Total UI for P1: 0, mck2ui 16
2581 22:55:38.896434 best dqsien dly found for B1: ( 1, 4, 4)
2582 22:55:38.899595 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2583 22:55:38.902986 best DQS1 dly(MCK, UI, PI) = (1, 4, 4)
2584 22:55:38.903076
2585 22:55:38.906720 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2586 22:55:38.910025 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 4)
2587 22:55:38.913299 [Gating] SW calibration Done
2588 22:55:38.913389 ==
2589 22:55:38.916231 Dram Type= 6, Freq= 0, CH_0, rank 0
2590 22:55:38.919373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2591 22:55:38.919506 ==
2592 22:55:38.923189 RX Vref Scan: 0
2593 22:55:38.923276
2594 22:55:38.926952 RX Vref 0 -> 0, step: 1
2595 22:55:38.927038
2596 22:55:38.927104 RX Delay -40 -> 252, step: 8
2597 22:55:38.933060 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2598 22:55:38.935986 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2599 22:55:38.939222 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2600 22:55:38.942794 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2601 22:55:38.946319 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2602 22:55:38.952959 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2603 22:55:38.956101 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2604 22:55:38.959468 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2605 22:55:38.962848 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2606 22:55:38.966192 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2607 22:55:38.969899 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2608 22:55:38.975930 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2609 22:55:38.979526 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2610 22:55:38.982443 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2611 22:55:38.986170 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2612 22:55:38.992819 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2613 22:55:38.992931 ==
2614 22:55:38.996038 Dram Type= 6, Freq= 0, CH_0, rank 0
2615 22:55:38.999562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2616 22:55:38.999653 ==
2617 22:55:38.999721 DQS Delay:
2618 22:55:39.002608 DQS0 = 0, DQS1 = 0
2619 22:55:39.002693 DQM Delay:
2620 22:55:39.005817 DQM0 = 112, DQM1 = 103
2621 22:55:39.005903 DQ Delay:
2622 22:55:39.009109 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2623 22:55:39.012565 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2624 22:55:39.015970 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =99
2625 22:55:39.019351 DQ12 =111, DQ13 =107, DQ14 =115, DQ15 =111
2626 22:55:39.019444
2627 22:55:39.019511
2628 22:55:39.019595 ==
2629 22:55:39.022629 Dram Type= 6, Freq= 0, CH_0, rank 0
2630 22:55:39.029333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2631 22:55:39.029441 ==
2632 22:55:39.029510
2633 22:55:39.029573
2634 22:55:39.029632 TX Vref Scan disable
2635 22:55:39.032388 == TX Byte 0 ==
2636 22:55:39.036011 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2637 22:55:39.042745 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2638 22:55:39.042916 == TX Byte 1 ==
2639 22:55:39.045930 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2640 22:55:39.052278 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2641 22:55:39.052385 ==
2642 22:55:39.055880 Dram Type= 6, Freq= 0, CH_0, rank 0
2643 22:55:39.058777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2644 22:55:39.058903 ==
2645 22:55:39.071021 TX Vref=22, minBit 6, minWin=25, winSum=417
2646 22:55:39.074476 TX Vref=24, minBit 0, minWin=26, winSum=422
2647 22:55:39.077484 TX Vref=26, minBit 2, minWin=26, winSum=428
2648 22:55:39.080605 TX Vref=28, minBit 0, minWin=27, winSum=433
2649 22:55:39.083843 TX Vref=30, minBit 1, minWin=26, winSum=432
2650 22:55:39.090793 TX Vref=32, minBit 1, minWin=26, winSum=432
2651 22:55:39.094003 [TxChooseVref] Worse bit 0, Min win 27, Win sum 433, Final Vref 28
2652 22:55:39.094122
2653 22:55:39.097434 Final TX Range 1 Vref 28
2654 22:55:39.097524
2655 22:55:39.097608 ==
2656 22:55:39.100821 Dram Type= 6, Freq= 0, CH_0, rank 0
2657 22:55:39.104098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2658 22:55:39.104188 ==
2659 22:55:39.107319
2660 22:55:39.107405
2661 22:55:39.107472 TX Vref Scan disable
2662 22:55:39.110572 == TX Byte 0 ==
2663 22:55:39.114129 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2664 22:55:39.120904 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2665 22:55:39.121023 == TX Byte 1 ==
2666 22:55:39.123972 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2667 22:55:39.130500 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2668 22:55:39.130612
2669 22:55:39.130683 [DATLAT]
2670 22:55:39.130745 Freq=1200, CH0 RK0
2671 22:55:39.130806
2672 22:55:39.133654 DATLAT Default: 0xd
2673 22:55:39.133739 0, 0xFFFF, sum = 0
2674 22:55:39.136965 1, 0xFFFF, sum = 0
2675 22:55:39.140638 2, 0xFFFF, sum = 0
2676 22:55:39.140731 3, 0xFFFF, sum = 0
2677 22:55:39.143398 4, 0xFFFF, sum = 0
2678 22:55:39.143486 5, 0xFFFF, sum = 0
2679 22:55:39.147247 6, 0xFFFF, sum = 0
2680 22:55:39.147336 7, 0xFFFF, sum = 0
2681 22:55:39.150283 8, 0xFFFF, sum = 0
2682 22:55:39.150372 9, 0xFFFF, sum = 0
2683 22:55:39.153828 10, 0xFFFF, sum = 0
2684 22:55:39.153928 11, 0xFFFF, sum = 0
2685 22:55:39.156916 12, 0x0, sum = 1
2686 22:55:39.157005 13, 0x0, sum = 2
2687 22:55:39.160267 14, 0x0, sum = 3
2688 22:55:39.160356 15, 0x0, sum = 4
2689 22:55:39.163716 best_step = 13
2690 22:55:39.163804
2691 22:55:39.163871 ==
2692 22:55:39.166823 Dram Type= 6, Freq= 0, CH_0, rank 0
2693 22:55:39.170049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2694 22:55:39.170140 ==
2695 22:55:39.173462 RX Vref Scan: 1
2696 22:55:39.173548
2697 22:55:39.173615 Set Vref Range= 32 -> 127
2698 22:55:39.173676
2699 22:55:39.176443 RX Vref 32 -> 127, step: 1
2700 22:55:39.176528
2701 22:55:39.180230 RX Delay -37 -> 252, step: 4
2702 22:55:39.180318
2703 22:55:39.183623 Set Vref, RX VrefLevel [Byte0]: 32
2704 22:55:39.186495 [Byte1]: 32
2705 22:55:39.186585
2706 22:55:39.189595 Set Vref, RX VrefLevel [Byte0]: 33
2707 22:55:39.193100 [Byte1]: 33
2708 22:55:39.197244
2709 22:55:39.197339 Set Vref, RX VrefLevel [Byte0]: 34
2710 22:55:39.200609 [Byte1]: 34
2711 22:55:39.205088
2712 22:55:39.205183 Set Vref, RX VrefLevel [Byte0]: 35
2713 22:55:39.208584 [Byte1]: 35
2714 22:55:39.213492
2715 22:55:39.213590 Set Vref, RX VrefLevel [Byte0]: 36
2716 22:55:39.216838 [Byte1]: 36
2717 22:55:39.221377
2718 22:55:39.221482 Set Vref, RX VrefLevel [Byte0]: 37
2719 22:55:39.224641 [Byte1]: 37
2720 22:55:39.229146
2721 22:55:39.229241 Set Vref, RX VrefLevel [Byte0]: 38
2722 22:55:39.232579 [Byte1]: 38
2723 22:55:39.237436
2724 22:55:39.237529 Set Vref, RX VrefLevel [Byte0]: 39
2725 22:55:39.240929 [Byte1]: 39
2726 22:55:39.245964
2727 22:55:39.246065 Set Vref, RX VrefLevel [Byte0]: 40
2728 22:55:39.248671 [Byte1]: 40
2729 22:55:39.253530
2730 22:55:39.253624 Set Vref, RX VrefLevel [Byte0]: 41
2731 22:55:39.256771 [Byte1]: 41
2732 22:55:39.261497
2733 22:55:39.261597 Set Vref, RX VrefLevel [Byte0]: 42
2734 22:55:39.264736 [Byte1]: 42
2735 22:55:39.269425
2736 22:55:39.269524 Set Vref, RX VrefLevel [Byte0]: 43
2737 22:55:39.272573 [Byte1]: 43
2738 22:55:39.277428
2739 22:55:39.277527 Set Vref, RX VrefLevel [Byte0]: 44
2740 22:55:39.281008 [Byte1]: 44
2741 22:55:39.285482
2742 22:55:39.285576 Set Vref, RX VrefLevel [Byte0]: 45
2743 22:55:39.289260 [Byte1]: 45
2744 22:55:39.293378
2745 22:55:39.293471 Set Vref, RX VrefLevel [Byte0]: 46
2746 22:55:39.297252 [Byte1]: 46
2747 22:55:39.301485
2748 22:55:39.301579 Set Vref, RX VrefLevel [Byte0]: 47
2749 22:55:39.304592 [Byte1]: 47
2750 22:55:39.309392
2751 22:55:39.309490 Set Vref, RX VrefLevel [Byte0]: 48
2752 22:55:39.312426 [Byte1]: 48
2753 22:55:39.317423
2754 22:55:39.317529 Set Vref, RX VrefLevel [Byte0]: 49
2755 22:55:39.320828 [Byte1]: 49
2756 22:55:39.325381
2757 22:55:39.325484 Set Vref, RX VrefLevel [Byte0]: 50
2758 22:55:39.328718 [Byte1]: 50
2759 22:55:39.333117
2760 22:55:39.333210 Set Vref, RX VrefLevel [Byte0]: 51
2761 22:55:39.336904 [Byte1]: 51
2762 22:55:39.341372
2763 22:55:39.341466 Set Vref, RX VrefLevel [Byte0]: 52
2764 22:55:39.344598 [Byte1]: 52
2765 22:55:39.349548
2766 22:55:39.349648 Set Vref, RX VrefLevel [Byte0]: 53
2767 22:55:39.352737 [Byte1]: 53
2768 22:55:39.357547
2769 22:55:39.357644 Set Vref, RX VrefLevel [Byte0]: 54
2770 22:55:39.361064 [Byte1]: 54
2771 22:55:39.365476
2772 22:55:39.365570 Set Vref, RX VrefLevel [Byte0]: 55
2773 22:55:39.368783 [Byte1]: 55
2774 22:55:39.373382
2775 22:55:39.373478 Set Vref, RX VrefLevel [Byte0]: 56
2776 22:55:39.376328 [Byte1]: 56
2777 22:55:39.381219
2778 22:55:39.381317 Set Vref, RX VrefLevel [Byte0]: 57
2779 22:55:39.384451 [Byte1]: 57
2780 22:55:39.389061
2781 22:55:39.389158 Set Vref, RX VrefLevel [Byte0]: 58
2782 22:55:39.392383 [Byte1]: 58
2783 22:55:39.397383
2784 22:55:39.397482 Set Vref, RX VrefLevel [Byte0]: 59
2785 22:55:39.400909 [Byte1]: 59
2786 22:55:39.405595
2787 22:55:39.405691 Set Vref, RX VrefLevel [Byte0]: 60
2788 22:55:39.408698 [Byte1]: 60
2789 22:55:39.413374
2790 22:55:39.413470 Set Vref, RX VrefLevel [Byte0]: 61
2791 22:55:39.416470 [Byte1]: 61
2792 22:55:39.421064
2793 22:55:39.421171 Set Vref, RX VrefLevel [Byte0]: 62
2794 22:55:39.424496 [Byte1]: 62
2795 22:55:39.429033
2796 22:55:39.429134 Set Vref, RX VrefLevel [Byte0]: 63
2797 22:55:39.432414 [Byte1]: 63
2798 22:55:39.437620
2799 22:55:39.437719 Set Vref, RX VrefLevel [Byte0]: 64
2800 22:55:39.440959 [Byte1]: 64
2801 22:55:39.445522
2802 22:55:39.445617 Set Vref, RX VrefLevel [Byte0]: 65
2803 22:55:39.449300 [Byte1]: 65
2804 22:55:39.453432
2805 22:55:39.453526 Set Vref, RX VrefLevel [Byte0]: 66
2806 22:55:39.456689 [Byte1]: 66
2807 22:55:39.461033
2808 22:55:39.461126 Set Vref, RX VrefLevel [Byte0]: 67
2809 22:55:39.464793 [Byte1]: 67
2810 22:55:39.469204
2811 22:55:39.469303 Set Vref, RX VrefLevel [Byte0]: 68
2812 22:55:39.472374 [Byte1]: 68
2813 22:55:39.477564
2814 22:55:39.477661 Set Vref, RX VrefLevel [Byte0]: 69
2815 22:55:39.480809 [Byte1]: 69
2816 22:55:39.485030
2817 22:55:39.485125 Set Vref, RX VrefLevel [Byte0]: 70
2818 22:55:39.488859 [Byte1]: 70
2819 22:55:39.493556
2820 22:55:39.493650 Set Vref, RX VrefLevel [Byte0]: 71
2821 22:55:39.496760 [Byte1]: 71
2822 22:55:39.501055
2823 22:55:39.501145 Set Vref, RX VrefLevel [Byte0]: 72
2824 22:55:39.504903 [Byte1]: 72
2825 22:55:39.509726
2826 22:55:39.509820 Set Vref, RX VrefLevel [Byte0]: 73
2827 22:55:39.512585 [Byte1]: 73
2828 22:55:39.517282
2829 22:55:39.517381 Set Vref, RX VrefLevel [Byte0]: 74
2830 22:55:39.520466 [Byte1]: 74
2831 22:55:39.525629
2832 22:55:39.525728 Set Vref, RX VrefLevel [Byte0]: 75
2833 22:55:39.528691 [Byte1]: 75
2834 22:55:39.533257
2835 22:55:39.533348 Final RX Vref Byte 0 = 62 to rank0
2836 22:55:39.536690 Final RX Vref Byte 1 = 52 to rank0
2837 22:55:39.539656 Final RX Vref Byte 0 = 62 to rank1
2838 22:55:39.543458 Final RX Vref Byte 1 = 52 to rank1==
2839 22:55:39.546818 Dram Type= 6, Freq= 0, CH_0, rank 0
2840 22:55:39.553030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2841 22:55:39.553135 ==
2842 22:55:39.553204 DQS Delay:
2843 22:55:39.556656 DQS0 = 0, DQS1 = 0
2844 22:55:39.556742 DQM Delay:
2845 22:55:39.556810 DQM0 = 112, DQM1 = 101
2846 22:55:39.560253 DQ Delay:
2847 22:55:39.563254 DQ0 =110, DQ1 =112, DQ2 =112, DQ3 =108
2848 22:55:39.566614 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2849 22:55:39.569788 DQ8 =92, DQ9 =84, DQ10 =104, DQ11 =94
2850 22:55:39.572997 DQ12 =106, DQ13 =106, DQ14 =114, DQ15 =110
2851 22:55:39.573087
2852 22:55:39.573154
2853 22:55:39.579781 [DQSOSCAuto] RK0, (LSB)MR18= 0x0, (MSB)MR19= 0x404, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
2854 22:55:39.582815 CH0 RK0: MR19=404, MR18=0
2855 22:55:39.589452 CH0_RK0: MR19=0x404, MR18=0x0, DQSOSC=410, MR23=63, INC=39, DEC=26
2856 22:55:39.589564
2857 22:55:39.592808 ----->DramcWriteLeveling(PI) begin...
2858 22:55:39.592901 ==
2859 22:55:39.596418 Dram Type= 6, Freq= 0, CH_0, rank 1
2860 22:55:39.599722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2861 22:55:39.599815 ==
2862 22:55:39.603224 Write leveling (Byte 0): 31 => 31
2863 22:55:39.606150 Write leveling (Byte 1): 31 => 31
2864 22:55:39.609432 DramcWriteLeveling(PI) end<-----
2865 22:55:39.609519
2866 22:55:39.609586 ==
2867 22:55:39.612719 Dram Type= 6, Freq= 0, CH_0, rank 1
2868 22:55:39.616114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2869 22:55:39.619394 ==
2870 22:55:39.619485 [Gating] SW mode calibration
2871 22:55:39.626160 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2872 22:55:39.632629 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2873 22:55:39.636504 0 15 0 | B1->B0 | 2626 3333 | 1 1 | (0 0) (1 1)
2874 22:55:39.643047 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2875 22:55:39.645970 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2876 22:55:39.649581 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2877 22:55:39.655856 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2878 22:55:39.659082 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2879 22:55:39.662354 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2880 22:55:39.669277 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
2881 22:55:39.672690 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2882 22:55:39.675623 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2883 22:55:39.682461 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2884 22:55:39.685884 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2885 22:55:39.689034 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2886 22:55:39.695896 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2887 22:55:39.699149 1 0 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2888 22:55:39.702298 1 0 28 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
2889 22:55:39.709017 1 1 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
2890 22:55:39.712133 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2891 22:55:39.715392 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2892 22:55:39.722160 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2893 22:55:39.725334 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2894 22:55:39.728680 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2895 22:55:39.735650 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2896 22:55:39.739245 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2897 22:55:39.741807 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2898 22:55:39.748836 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 22:55:39.751964 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 22:55:39.755532 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 22:55:39.761971 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 22:55:39.765148 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 22:55:39.768712 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 22:55:39.772081 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 22:55:39.778791 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 22:55:39.781665 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 22:55:39.785108 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 22:55:39.792172 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 22:55:39.795115 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 22:55:39.798621 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 22:55:39.804722 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2912 22:55:39.808326 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2913 22:55:39.811533 Total UI for P1: 0, mck2ui 16
2914 22:55:39.815345 best dqsien dly found for B0: ( 1, 3, 24)
2915 22:55:39.818542 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 22:55:39.821856 Total UI for P1: 0, mck2ui 16
2917 22:55:39.825170 best dqsien dly found for B1: ( 1, 3, 28)
2918 22:55:39.828588 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2919 22:55:39.831350 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2920 22:55:39.834644
2921 22:55:39.838486 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2922 22:55:39.841314 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2923 22:55:39.844613 [Gating] SW calibration Done
2924 22:55:39.844707 ==
2925 22:55:39.847909 Dram Type= 6, Freq= 0, CH_0, rank 1
2926 22:55:39.851327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2927 22:55:39.851417 ==
2928 22:55:39.851484 RX Vref Scan: 0
2929 22:55:39.854738
2930 22:55:39.854824 RX Vref 0 -> 0, step: 1
2931 22:55:39.854931
2932 22:55:39.858082 RX Delay -40 -> 252, step: 8
2933 22:55:39.861585 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2934 22:55:39.864601 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2935 22:55:39.870943 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2936 22:55:39.874769 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2937 22:55:39.878117 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2938 22:55:39.881477 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2939 22:55:39.884640 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2940 22:55:39.891229 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2941 22:55:39.894450 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2942 22:55:39.897944 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2943 22:55:39.901352 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2944 22:55:39.905078 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2945 22:55:39.910964 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2946 22:55:39.914481 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2947 22:55:39.917747 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2948 22:55:39.921006 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2949 22:55:39.921100 ==
2950 22:55:39.924351 Dram Type= 6, Freq= 0, CH_0, rank 1
2951 22:55:39.931121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2952 22:55:39.931227 ==
2953 22:55:39.931295 DQS Delay:
2954 22:55:39.931356 DQS0 = 0, DQS1 = 0
2955 22:55:39.934020 DQM Delay:
2956 22:55:39.934104 DQM0 = 112, DQM1 = 101
2957 22:55:39.937953 DQ Delay:
2958 22:55:39.940804 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2959 22:55:39.944176 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =123
2960 22:55:39.947343 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2961 22:55:39.950572 DQ12 =107, DQ13 =111, DQ14 =111, DQ15 =107
2962 22:55:39.950669
2963 22:55:39.950790
2964 22:55:39.950902 ==
2965 22:55:39.954632 Dram Type= 6, Freq= 0, CH_0, rank 1
2966 22:55:39.957236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2967 22:55:39.957324 ==
2968 22:55:39.960703
2969 22:55:39.960822
2970 22:55:39.960919 TX Vref Scan disable
2971 22:55:39.963917 == TX Byte 0 ==
2972 22:55:39.966993 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2973 22:55:39.970755 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2974 22:55:39.974108 == TX Byte 1 ==
2975 22:55:39.977403 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2976 22:55:39.980507 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2977 22:55:39.980598 ==
2978 22:55:39.984196 Dram Type= 6, Freq= 0, CH_0, rank 1
2979 22:55:39.990413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2980 22:55:39.990519 ==
2981 22:55:40.001350 TX Vref=22, minBit 0, minWin=26, winSum=422
2982 22:55:40.004374 TX Vref=24, minBit 5, minWin=26, winSum=430
2983 22:55:40.007882 TX Vref=26, minBit 5, minWin=26, winSum=436
2984 22:55:40.011198 TX Vref=28, minBit 13, minWin=26, winSum=440
2985 22:55:40.015029 TX Vref=30, minBit 1, minWin=27, winSum=440
2986 22:55:40.021045 TX Vref=32, minBit 2, minWin=27, winSum=439
2987 22:55:40.024202 [TxChooseVref] Worse bit 1, Min win 27, Win sum 440, Final Vref 30
2988 22:55:40.024302
2989 22:55:40.028003 Final TX Range 1 Vref 30
2990 22:55:40.028094
2991 22:55:40.028161 ==
2992 22:55:40.031629 Dram Type= 6, Freq= 0, CH_0, rank 1
2993 22:55:40.034095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2994 22:55:40.034182 ==
2995 22:55:40.037389
2996 22:55:40.037474
2997 22:55:40.037540 TX Vref Scan disable
2998 22:55:40.041207 == TX Byte 0 ==
2999 22:55:40.044815 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3000 22:55:40.047454 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3001 22:55:40.051141 == TX Byte 1 ==
3002 22:55:40.054020 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3003 22:55:40.060677 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3004 22:55:40.060824
3005 22:55:40.060930 [DATLAT]
3006 22:55:40.061030 Freq=1200, CH0 RK1
3007 22:55:40.061127
3008 22:55:40.063923 DATLAT Default: 0xd
3009 22:55:40.064008 0, 0xFFFF, sum = 0
3010 22:55:40.067586 1, 0xFFFF, sum = 0
3011 22:55:40.067675 2, 0xFFFF, sum = 0
3012 22:55:40.070572 3, 0xFFFF, sum = 0
3013 22:55:40.074174 4, 0xFFFF, sum = 0
3014 22:55:40.074267 5, 0xFFFF, sum = 0
3015 22:55:40.077186 6, 0xFFFF, sum = 0
3016 22:55:40.077281 7, 0xFFFF, sum = 0
3017 22:55:40.080535 8, 0xFFFF, sum = 0
3018 22:55:40.080692 9, 0xFFFF, sum = 0
3019 22:55:40.083829 10, 0xFFFF, sum = 0
3020 22:55:40.083974 11, 0xFFFF, sum = 0
3021 22:55:40.087138 12, 0x0, sum = 1
3022 22:55:40.087274 13, 0x0, sum = 2
3023 22:55:40.090406 14, 0x0, sum = 3
3024 22:55:40.090513 15, 0x0, sum = 4
3025 22:55:40.093588 best_step = 13
3026 22:55:40.093693
3027 22:55:40.093789 ==
3028 22:55:40.097282 Dram Type= 6, Freq= 0, CH_0, rank 1
3029 22:55:40.100427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3030 22:55:40.100562 ==
3031 22:55:40.100682 RX Vref Scan: 0
3032 22:55:40.103496
3033 22:55:40.103603 RX Vref 0 -> 0, step: 1
3034 22:55:40.103735
3035 22:55:40.107223 RX Delay -37 -> 252, step: 4
3036 22:55:40.113438 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3037 22:55:40.116841 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3038 22:55:40.120579 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3039 22:55:40.123838 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3040 22:55:40.127202 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3041 22:55:40.133816 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3042 22:55:40.137060 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3043 22:55:40.140804 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3044 22:55:40.143819 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3045 22:55:40.147023 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3046 22:55:40.150508 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3047 22:55:40.157030 iDelay=195, Bit 11, Center 92 (23 ~ 162) 140
3048 22:55:40.160157 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3049 22:55:40.163266 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3050 22:55:40.166707 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3051 22:55:40.173128 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3052 22:55:40.173247 ==
3053 22:55:40.176786 Dram Type= 6, Freq= 0, CH_0, rank 1
3054 22:55:40.179973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3055 22:55:40.180071 ==
3056 22:55:40.180140 DQS Delay:
3057 22:55:40.183093 DQS0 = 0, DQS1 = 0
3058 22:55:40.183171 DQM Delay:
3059 22:55:40.186624 DQM0 = 110, DQM1 = 101
3060 22:55:40.186709 DQ Delay:
3061 22:55:40.189649 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3062 22:55:40.193021 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3063 22:55:40.196458 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =92
3064 22:55:40.199547 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =110
3065 22:55:40.199641
3066 22:55:40.199707
3067 22:55:40.209778 [DQSOSCAuto] RK1, (LSB)MR18= 0x13fb, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 402 ps
3068 22:55:40.212917 CH0 RK1: MR19=403, MR18=13FB
3069 22:55:40.216456 CH0_RK1: MR19=0x403, MR18=0x13FB, DQSOSC=402, MR23=63, INC=40, DEC=27
3070 22:55:40.219534 [RxdqsGatingPostProcess] freq 1200
3071 22:55:40.226232 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3072 22:55:40.229599 best DQS0 dly(2T, 0.5T) = (0, 12)
3073 22:55:40.233048 best DQS1 dly(2T, 0.5T) = (0, 12)
3074 22:55:40.236377 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3075 22:55:40.239659 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3076 22:55:40.243388 best DQS0 dly(2T, 0.5T) = (0, 11)
3077 22:55:40.246482 best DQS1 dly(2T, 0.5T) = (0, 11)
3078 22:55:40.249675 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3079 22:55:40.253168 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3080 22:55:40.256123 Pre-setting of DQS Precalculation
3081 22:55:40.259708 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3082 22:55:40.259799 ==
3083 22:55:40.263035 Dram Type= 6, Freq= 0, CH_1, rank 0
3084 22:55:40.266540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3085 22:55:40.266631 ==
3086 22:55:40.272970 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3087 22:55:40.279428 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3088 22:55:40.287081 [CA 0] Center 37 (7~67) winsize 61
3089 22:55:40.290265 [CA 1] Center 37 (7~68) winsize 62
3090 22:55:40.293810 [CA 2] Center 34 (5~64) winsize 60
3091 22:55:40.297154 [CA 3] Center 33 (3~64) winsize 62
3092 22:55:40.300434 [CA 4] Center 34 (4~64) winsize 61
3093 22:55:40.303931 [CA 5] Center 33 (3~63) winsize 61
3094 22:55:40.304032
3095 22:55:40.306705 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3096 22:55:40.306815
3097 22:55:40.310446 [CATrainingPosCal] consider 1 rank data
3098 22:55:40.313497 u2DelayCellTimex100 = 270/100 ps
3099 22:55:40.316856 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3100 22:55:40.323594 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3101 22:55:40.326774 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3102 22:55:40.330036 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3103 22:55:40.333384 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3104 22:55:40.336358 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3105 22:55:40.336453
3106 22:55:40.340047 CA PerBit enable=1, Macro0, CA PI delay=33
3107 22:55:40.340142
3108 22:55:40.343574 [CBTSetCACLKResult] CA Dly = 33
3109 22:55:40.346801 CS Dly: 6 (0~37)
3110 22:55:40.346955 ==
3111 22:55:40.350235 Dram Type= 6, Freq= 0, CH_1, rank 1
3112 22:55:40.353340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3113 22:55:40.353431 ==
3114 22:55:40.359927 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3115 22:55:40.363295 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3116 22:55:40.372596 [CA 0] Center 37 (7~67) winsize 61
3117 22:55:40.376192 [CA 1] Center 37 (7~68) winsize 62
3118 22:55:40.379373 [CA 2] Center 34 (4~65) winsize 62
3119 22:55:40.382400 [CA 3] Center 33 (3~64) winsize 62
3120 22:55:40.385717 [CA 4] Center 34 (4~65) winsize 62
3121 22:55:40.388977 [CA 5] Center 33 (3~63) winsize 61
3122 22:55:40.389104
3123 22:55:40.392579 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3124 22:55:40.392667
3125 22:55:40.396068 [CATrainingPosCal] consider 2 rank data
3126 22:55:40.398785 u2DelayCellTimex100 = 270/100 ps
3127 22:55:40.402505 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3128 22:55:40.408988 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3129 22:55:40.412520 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3130 22:55:40.416296 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3131 22:55:40.419109 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3132 22:55:40.422416 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3133 22:55:40.422533
3134 22:55:40.425647 CA PerBit enable=1, Macro0, CA PI delay=33
3135 22:55:40.425741
3136 22:55:40.429488 [CBTSetCACLKResult] CA Dly = 33
3137 22:55:40.429578 CS Dly: 7 (0~39)
3138 22:55:40.432308
3139 22:55:40.435743 ----->DramcWriteLeveling(PI) begin...
3140 22:55:40.435832 ==
3141 22:55:40.439611 Dram Type= 6, Freq= 0, CH_1, rank 0
3142 22:55:40.441746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3143 22:55:40.441833 ==
3144 22:55:40.445321 Write leveling (Byte 0): 26 => 26
3145 22:55:40.448791 Write leveling (Byte 1): 29 => 29
3146 22:55:40.452403 DramcWriteLeveling(PI) end<-----
3147 22:55:40.452494
3148 22:55:40.452561 ==
3149 22:55:40.455278 Dram Type= 6, Freq= 0, CH_1, rank 0
3150 22:55:40.458529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3151 22:55:40.458616 ==
3152 22:55:40.461896 [Gating] SW mode calibration
3153 22:55:40.468445 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3154 22:55:40.475014 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3155 22:55:40.478234 0 15 0 | B1->B0 | 2f2f 2828 | 0 1 | (0 0) (0 0)
3156 22:55:40.481942 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3157 22:55:40.488703 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3158 22:55:40.491612 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3159 22:55:40.495021 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3160 22:55:40.502434 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3161 22:55:40.505147 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3162 22:55:40.508287 0 15 28 | B1->B0 | 3030 3131 | 0 0 | (0 1) (0 0)
3163 22:55:40.514928 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3164 22:55:40.518185 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3165 22:55:40.521430 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3166 22:55:40.528145 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3167 22:55:40.531363 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3168 22:55:40.534777 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3169 22:55:40.541545 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3170 22:55:40.544591 1 0 28 | B1->B0 | 3d3c 3838 | 1 0 | (0 0) (1 1)
3171 22:55:40.548006 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3172 22:55:40.554532 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3173 22:55:40.557895 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3174 22:55:40.561272 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3175 22:55:40.567754 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3176 22:55:40.571024 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3177 22:55:40.574708 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3178 22:55:40.581120 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3179 22:55:40.585002 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 22:55:40.588093 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 22:55:40.594350 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 22:55:40.597737 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 22:55:40.600888 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 22:55:40.607601 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 22:55:40.610669 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 22:55:40.614161 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 22:55:40.620735 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 22:55:40.624035 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 22:55:40.627245 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 22:55:40.631111 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 22:55:40.637235 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 22:55:40.640622 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 22:55:40.644127 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 22:55:40.650623 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3195 22:55:40.653953 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 22:55:40.656985 Total UI for P1: 0, mck2ui 16
3197 22:55:40.660587 best dqsien dly found for B0: ( 1, 3, 28)
3198 22:55:40.663830 Total UI for P1: 0, mck2ui 16
3199 22:55:40.667298 best dqsien dly found for B1: ( 1, 3, 28)
3200 22:55:40.670626 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3201 22:55:40.673422 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3202 22:55:40.673514
3203 22:55:40.676929 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3204 22:55:40.683901 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3205 22:55:40.684017 [Gating] SW calibration Done
3206 22:55:40.684108 ==
3207 22:55:40.686877 Dram Type= 6, Freq= 0, CH_1, rank 0
3208 22:55:40.693309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3209 22:55:40.693413 ==
3210 22:55:40.693503 RX Vref Scan: 0
3211 22:55:40.693584
3212 22:55:40.696882 RX Vref 0 -> 0, step: 1
3213 22:55:40.696970
3214 22:55:40.700263 RX Delay -40 -> 252, step: 8
3215 22:55:40.703178 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3216 22:55:40.706474 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3217 22:55:40.709808 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3218 22:55:40.716477 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3219 22:55:40.719611 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3220 22:55:40.723336 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3221 22:55:40.726583 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3222 22:55:40.729661 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3223 22:55:40.736599 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3224 22:55:40.739240 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3225 22:55:40.743030 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3226 22:55:40.745927 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3227 22:55:40.749674 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3228 22:55:40.755816 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3229 22:55:40.759378 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3230 22:55:40.763055 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3231 22:55:40.763150 ==
3232 22:55:40.765929 Dram Type= 6, Freq= 0, CH_1, rank 0
3233 22:55:40.769857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3234 22:55:40.772293 ==
3235 22:55:40.772382 DQS Delay:
3236 22:55:40.772448 DQS0 = 0, DQS1 = 0
3237 22:55:40.776205 DQM Delay:
3238 22:55:40.776295 DQM0 = 113, DQM1 = 105
3239 22:55:40.779299 DQ Delay:
3240 22:55:40.782540 DQ0 =119, DQ1 =107, DQ2 =99, DQ3 =115
3241 22:55:40.785913 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3242 22:55:40.788966 DQ8 =95, DQ9 =99, DQ10 =103, DQ11 =103
3243 22:55:40.792250 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3244 22:55:40.792339
3245 22:55:40.792403
3246 22:55:40.792464 ==
3247 22:55:40.795524 Dram Type= 6, Freq= 0, CH_1, rank 0
3248 22:55:40.798784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3249 22:55:40.798881 ==
3250 22:55:40.798947
3251 22:55:40.799009
3252 22:55:40.802655 TX Vref Scan disable
3253 22:55:40.805757 == TX Byte 0 ==
3254 22:55:40.809086 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3255 22:55:40.812260 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3256 22:55:40.815624 == TX Byte 1 ==
3257 22:55:40.819117 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3258 22:55:40.821987 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3259 22:55:40.822090 ==
3260 22:55:40.825807 Dram Type= 6, Freq= 0, CH_1, rank 0
3261 22:55:40.832049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3262 22:55:40.832158 ==
3263 22:55:40.842760 TX Vref=22, minBit 11, minWin=24, winSum=409
3264 22:55:40.846035 TX Vref=24, minBit 8, minWin=24, winSum=411
3265 22:55:40.849371 TX Vref=26, minBit 8, minWin=25, winSum=423
3266 22:55:40.852619 TX Vref=28, minBit 9, minWin=25, winSum=425
3267 22:55:40.855703 TX Vref=30, minBit 0, minWin=26, winSum=424
3268 22:55:40.862647 TX Vref=32, minBit 8, minWin=25, winSum=422
3269 22:55:40.865828 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 30
3270 22:55:40.865931
3271 22:55:40.869061 Final TX Range 1 Vref 30
3272 22:55:40.869150
3273 22:55:40.869217 ==
3274 22:55:40.872382 Dram Type= 6, Freq= 0, CH_1, rank 0
3275 22:55:40.875412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3276 22:55:40.879060 ==
3277 22:55:40.879162
3278 22:55:40.879231
3279 22:55:40.879294 TX Vref Scan disable
3280 22:55:40.882524 == TX Byte 0 ==
3281 22:55:40.885780 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3282 22:55:40.889152 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3283 22:55:40.892268 == TX Byte 1 ==
3284 22:55:40.895621 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3285 22:55:40.902100 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3286 22:55:40.902205
3287 22:55:40.902275 [DATLAT]
3288 22:55:40.902337 Freq=1200, CH1 RK0
3289 22:55:40.902398
3290 22:55:40.905404 DATLAT Default: 0xd
3291 22:55:40.905491 0, 0xFFFF, sum = 0
3292 22:55:40.908643 1, 0xFFFF, sum = 0
3293 22:55:40.912322 2, 0xFFFF, sum = 0
3294 22:55:40.912423 3, 0xFFFF, sum = 0
3295 22:55:40.915544 4, 0xFFFF, sum = 0
3296 22:55:40.915632 5, 0xFFFF, sum = 0
3297 22:55:40.918575 6, 0xFFFF, sum = 0
3298 22:55:40.918664 7, 0xFFFF, sum = 0
3299 22:55:40.922141 8, 0xFFFF, sum = 0
3300 22:55:40.922229 9, 0xFFFF, sum = 0
3301 22:55:40.925807 10, 0xFFFF, sum = 0
3302 22:55:40.925897 11, 0xFFFF, sum = 0
3303 22:55:40.928789 12, 0x0, sum = 1
3304 22:55:40.928876 13, 0x0, sum = 2
3305 22:55:40.932080 14, 0x0, sum = 3
3306 22:55:40.932170 15, 0x0, sum = 4
3307 22:55:40.935441 best_step = 13
3308 22:55:40.935526
3309 22:55:40.935591 ==
3310 22:55:40.938623 Dram Type= 6, Freq= 0, CH_1, rank 0
3311 22:55:40.942188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3312 22:55:40.942314 ==
3313 22:55:40.942414 RX Vref Scan: 1
3314 22:55:40.945304
3315 22:55:40.945387 Set Vref Range= 32 -> 127
3316 22:55:40.945453
3317 22:55:40.948505 RX Vref 32 -> 127, step: 1
3318 22:55:40.948589
3319 22:55:40.951841 RX Delay -21 -> 252, step: 4
3320 22:55:40.951924
3321 22:55:40.955013 Set Vref, RX VrefLevel [Byte0]: 32
3322 22:55:40.958320 [Byte1]: 32
3323 22:55:40.958430
3324 22:55:40.961598 Set Vref, RX VrefLevel [Byte0]: 33
3325 22:55:40.964856 [Byte1]: 33
3326 22:55:40.968800
3327 22:55:40.968892 Set Vref, RX VrefLevel [Byte0]: 34
3328 22:55:40.972031 [Byte1]: 34
3329 22:55:40.976555
3330 22:55:40.976646 Set Vref, RX VrefLevel [Byte0]: 35
3331 22:55:40.979925 [Byte1]: 35
3332 22:55:40.984570
3333 22:55:40.984658 Set Vref, RX VrefLevel [Byte0]: 36
3334 22:55:40.987905 [Byte1]: 36
3335 22:55:40.992751
3336 22:55:40.992836 Set Vref, RX VrefLevel [Byte0]: 37
3337 22:55:40.995972 [Byte1]: 37
3338 22:55:41.000869
3339 22:55:41.000963 Set Vref, RX VrefLevel [Byte0]: 38
3340 22:55:41.003797 [Byte1]: 38
3341 22:55:41.008708
3342 22:55:41.008804 Set Vref, RX VrefLevel [Byte0]: 39
3343 22:55:41.011778 [Byte1]: 39
3344 22:55:41.016391
3345 22:55:41.016483 Set Vref, RX VrefLevel [Byte0]: 40
3346 22:55:41.019576 [Byte1]: 40
3347 22:55:41.024547
3348 22:55:41.024647 Set Vref, RX VrefLevel [Byte0]: 41
3349 22:55:41.027601 [Byte1]: 41
3350 22:55:41.032162
3351 22:55:41.032253 Set Vref, RX VrefLevel [Byte0]: 42
3352 22:55:41.035401 [Byte1]: 42
3353 22:55:41.039838
3354 22:55:41.039940 Set Vref, RX VrefLevel [Byte0]: 43
3355 22:55:41.043463 [Byte1]: 43
3356 22:55:41.047950
3357 22:55:41.048049 Set Vref, RX VrefLevel [Byte0]: 44
3358 22:55:41.051069 [Byte1]: 44
3359 22:55:41.055940
3360 22:55:41.056040 Set Vref, RX VrefLevel [Byte0]: 45
3361 22:55:41.059177 [Byte1]: 45
3362 22:55:41.064119
3363 22:55:41.064219 Set Vref, RX VrefLevel [Byte0]: 46
3364 22:55:41.067461 [Byte1]: 46
3365 22:55:41.071605
3366 22:55:41.071699 Set Vref, RX VrefLevel [Byte0]: 47
3367 22:55:41.075211 [Byte1]: 47
3368 22:55:41.079670
3369 22:55:41.079766 Set Vref, RX VrefLevel [Byte0]: 48
3370 22:55:41.083129 [Byte1]: 48
3371 22:55:41.087626
3372 22:55:41.087719 Set Vref, RX VrefLevel [Byte0]: 49
3373 22:55:41.090834 [Byte1]: 49
3374 22:55:41.095602
3375 22:55:41.095701 Set Vref, RX VrefLevel [Byte0]: 50
3376 22:55:41.099171 [Byte1]: 50
3377 22:55:41.103497
3378 22:55:41.103591 Set Vref, RX VrefLevel [Byte0]: 51
3379 22:55:41.106712 [Byte1]: 51
3380 22:55:41.111608
3381 22:55:41.111698 Set Vref, RX VrefLevel [Byte0]: 52
3382 22:55:41.114665 [Byte1]: 52
3383 22:55:41.119309
3384 22:55:41.119410 Set Vref, RX VrefLevel [Byte0]: 53
3385 22:55:41.122684 [Byte1]: 53
3386 22:55:41.127141
3387 22:55:41.127236 Set Vref, RX VrefLevel [Byte0]: 54
3388 22:55:41.130822 [Byte1]: 54
3389 22:55:41.135588
3390 22:55:41.135682 Set Vref, RX VrefLevel [Byte0]: 55
3391 22:55:41.138490 [Byte1]: 55
3392 22:55:41.143146
3393 22:55:41.143239 Set Vref, RX VrefLevel [Byte0]: 56
3394 22:55:41.146378 [Byte1]: 56
3395 22:55:41.150962
3396 22:55:41.151061 Set Vref, RX VrefLevel [Byte0]: 57
3397 22:55:41.154362 [Byte1]: 57
3398 22:55:41.159013
3399 22:55:41.159108 Set Vref, RX VrefLevel [Byte0]: 58
3400 22:55:41.162380 [Byte1]: 58
3401 22:55:41.167118
3402 22:55:41.167214 Set Vref, RX VrefLevel [Byte0]: 59
3403 22:55:41.170348 [Byte1]: 59
3404 22:55:41.174673
3405 22:55:41.174766 Set Vref, RX VrefLevel [Byte0]: 60
3406 22:55:41.177838 [Byte1]: 60
3407 22:55:41.182654
3408 22:55:41.182751 Set Vref, RX VrefLevel [Byte0]: 61
3409 22:55:41.186004 [Byte1]: 61
3410 22:55:41.190607
3411 22:55:41.190700 Set Vref, RX VrefLevel [Byte0]: 62
3412 22:55:41.193811 [Byte1]: 62
3413 22:55:41.198407
3414 22:55:41.198499 Set Vref, RX VrefLevel [Byte0]: 63
3415 22:55:41.202007 [Byte1]: 63
3416 22:55:41.206632
3417 22:55:41.206729 Set Vref, RX VrefLevel [Byte0]: 64
3418 22:55:41.209835 [Byte1]: 64
3419 22:55:41.214347
3420 22:55:41.214442 Set Vref, RX VrefLevel [Byte0]: 65
3421 22:55:41.217703 [Byte1]: 65
3422 22:55:41.222503
3423 22:55:41.222606 Set Vref, RX VrefLevel [Byte0]: 66
3424 22:55:41.225393 [Byte1]: 66
3425 22:55:41.230215
3426 22:55:41.230311 Set Vref, RX VrefLevel [Byte0]: 67
3427 22:55:41.233495 [Byte1]: 67
3428 22:55:41.238964
3429 22:55:41.239062 Set Vref, RX VrefLevel [Byte0]: 68
3430 22:55:41.241266 [Byte1]: 68
3431 22:55:41.246062
3432 22:55:41.246158 Final RX Vref Byte 0 = 56 to rank0
3433 22:55:41.249677 Final RX Vref Byte 1 = 55 to rank0
3434 22:55:41.252718 Final RX Vref Byte 0 = 56 to rank1
3435 22:55:41.256106 Final RX Vref Byte 1 = 55 to rank1==
3436 22:55:41.259483 Dram Type= 6, Freq= 0, CH_1, rank 0
3437 22:55:41.266251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3438 22:55:41.266368 ==
3439 22:55:41.266439 DQS Delay:
3440 22:55:41.266501 DQS0 = 0, DQS1 = 0
3441 22:55:41.269673 DQM Delay:
3442 22:55:41.269761 DQM0 = 114, DQM1 = 107
3443 22:55:41.272859 DQ Delay:
3444 22:55:41.276268 DQ0 =118, DQ1 =110, DQ2 =104, DQ3 =112
3445 22:55:41.279470 DQ4 =112, DQ5 =122, DQ6 =126, DQ7 =112
3446 22:55:41.282643 DQ8 =92, DQ9 =98, DQ10 =106, DQ11 =100
3447 22:55:41.286012 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =116
3448 22:55:41.286106
3449 22:55:41.286174
3450 22:55:41.296019 [DQSOSCAuto] RK0, (LSB)MR18= 0xecf3, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 418 ps
3451 22:55:41.296145 CH1 RK0: MR19=303, MR18=ECF3
3452 22:55:41.302358 CH1_RK0: MR19=0x303, MR18=0xECF3, DQSOSC=415, MR23=63, INC=38, DEC=25
3453 22:55:41.302469
3454 22:55:41.305870 ----->DramcWriteLeveling(PI) begin...
3455 22:55:41.305962 ==
3456 22:55:41.308925 Dram Type= 6, Freq= 0, CH_1, rank 1
3457 22:55:41.312589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3458 22:55:41.315947 ==
3459 22:55:41.316039 Write leveling (Byte 0): 24 => 24
3460 22:55:41.319231 Write leveling (Byte 1): 28 => 28
3461 22:55:41.322640 DramcWriteLeveling(PI) end<-----
3462 22:55:41.322731
3463 22:55:41.322796 ==
3464 22:55:41.325828 Dram Type= 6, Freq= 0, CH_1, rank 1
3465 22:55:41.332755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3466 22:55:41.332867 ==
3467 22:55:41.335765 [Gating] SW mode calibration
3468 22:55:41.342314 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3469 22:55:41.346065 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3470 22:55:41.352165 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3471 22:55:41.355138 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3472 22:55:41.358530 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3473 22:55:41.365717 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3474 22:55:41.368823 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3475 22:55:41.372001 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3476 22:55:41.379127 0 15 24 | B1->B0 | 3232 2323 | 0 0 | (1 0) (1 0)
3477 22:55:41.382037 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3478 22:55:41.385501 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3479 22:55:41.392088 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3480 22:55:41.394948 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3481 22:55:41.398474 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3482 22:55:41.404851 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3483 22:55:41.408461 1 0 20 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
3484 22:55:41.411307 1 0 24 | B1->B0 | 2828 4646 | 1 0 | (0 0) (0 0)
3485 22:55:41.417935 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3486 22:55:41.421308 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3487 22:55:41.424946 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3488 22:55:41.431322 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3489 22:55:41.434819 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3490 22:55:41.437991 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3491 22:55:41.444451 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3492 22:55:41.447493 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3493 22:55:41.451303 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3494 22:55:41.457698 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 22:55:41.460775 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 22:55:41.464587 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 22:55:41.471061 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 22:55:41.474130 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 22:55:41.477948 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 22:55:41.484059 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 22:55:41.487404 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 22:55:41.490783 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 22:55:41.497316 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 22:55:41.500684 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 22:55:41.504039 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 22:55:41.510529 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 22:55:41.513666 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3508 22:55:41.516903 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3509 22:55:41.523491 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 22:55:41.523619 Total UI for P1: 0, mck2ui 16
3511 22:55:41.530561 best dqsien dly found for B0: ( 1, 3, 22)
3512 22:55:41.530673 Total UI for P1: 0, mck2ui 16
3513 22:55:41.537063 best dqsien dly found for B1: ( 1, 3, 24)
3514 22:55:41.539797 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3515 22:55:41.543131 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3516 22:55:41.543220
3517 22:55:41.546813 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3518 22:55:41.550069 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3519 22:55:41.553611 [Gating] SW calibration Done
3520 22:55:41.553702 ==
3521 22:55:41.556222 Dram Type= 6, Freq= 0, CH_1, rank 1
3522 22:55:41.560256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3523 22:55:41.560346 ==
3524 22:55:41.562988 RX Vref Scan: 0
3525 22:55:41.563076
3526 22:55:41.563152 RX Vref 0 -> 0, step: 1
3527 22:55:41.563221
3528 22:55:41.566332 RX Delay -40 -> 252, step: 8
3529 22:55:41.569941 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3530 22:55:41.576293 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3531 22:55:41.579816 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3532 22:55:41.583144 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3533 22:55:41.586261 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3534 22:55:41.589602 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3535 22:55:41.596108 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3536 22:55:41.599733 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3537 22:55:41.602771 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3538 22:55:41.606284 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3539 22:55:41.609143 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
3540 22:55:41.616088 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3541 22:55:41.618959 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3542 22:55:41.622719 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3543 22:55:41.625622 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3544 22:55:41.632267 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
3545 22:55:41.632387 ==
3546 22:55:41.635610 Dram Type= 6, Freq= 0, CH_1, rank 1
3547 22:55:41.638810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3548 22:55:41.638942 ==
3549 22:55:41.639012 DQS Delay:
3550 22:55:41.642047 DQS0 = 0, DQS1 = 0
3551 22:55:41.642134 DQM Delay:
3552 22:55:41.645860 DQM0 = 110, DQM1 = 109
3553 22:55:41.645948 DQ Delay:
3554 22:55:41.648837 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3555 22:55:41.652173 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3556 22:55:41.655461 DQ8 =95, DQ9 =99, DQ10 =107, DQ11 =103
3557 22:55:41.658537 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =115
3558 22:55:41.658624
3559 22:55:41.658692
3560 22:55:41.661836 ==
3561 22:55:41.665112 Dram Type= 6, Freq= 0, CH_1, rank 1
3562 22:55:41.668535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3563 22:55:41.668626 ==
3564 22:55:41.668694
3565 22:55:41.668754
3566 22:55:41.672111 TX Vref Scan disable
3567 22:55:41.672198 == TX Byte 0 ==
3568 22:55:41.678586 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3569 22:55:41.681650 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3570 22:55:41.681743 == TX Byte 1 ==
3571 22:55:41.688173 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3572 22:55:41.691684 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3573 22:55:41.691779 ==
3574 22:55:41.694707 Dram Type= 6, Freq= 0, CH_1, rank 1
3575 22:55:41.698122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3576 22:55:41.698213 ==
3577 22:55:41.710550 TX Vref=22, minBit 3, minWin=25, winSum=420
3578 22:55:41.714255 TX Vref=24, minBit 0, minWin=25, winSum=426
3579 22:55:41.717358 TX Vref=26, minBit 0, minWin=26, winSum=432
3580 22:55:41.720571 TX Vref=28, minBit 9, minWin=26, winSum=432
3581 22:55:41.723846 TX Vref=30, minBit 8, minWin=25, winSum=430
3582 22:55:41.730729 TX Vref=32, minBit 1, minWin=26, winSum=434
3583 22:55:41.733587 [TxChooseVref] Worse bit 1, Min win 26, Win sum 434, Final Vref 32
3584 22:55:41.733682
3585 22:55:41.737034 Final TX Range 1 Vref 32
3586 22:55:41.737120
3587 22:55:41.737185 ==
3588 22:55:41.740138 Dram Type= 6, Freq= 0, CH_1, rank 1
3589 22:55:41.743776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3590 22:55:41.746845 ==
3591 22:55:41.746949
3592 22:55:41.747014
3593 22:55:41.747073 TX Vref Scan disable
3594 22:55:41.750406 == TX Byte 0 ==
3595 22:55:41.753490 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3596 22:55:41.760358 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3597 22:55:41.760462 == TX Byte 1 ==
3598 22:55:41.763812 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3599 22:55:41.770233 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3600 22:55:41.770337
3601 22:55:41.770404 [DATLAT]
3602 22:55:41.770465 Freq=1200, CH1 RK1
3603 22:55:41.770524
3604 22:55:41.773273 DATLAT Default: 0xd
3605 22:55:41.776504 0, 0xFFFF, sum = 0
3606 22:55:41.776593 1, 0xFFFF, sum = 0
3607 22:55:41.780350 2, 0xFFFF, sum = 0
3608 22:55:41.780437 3, 0xFFFF, sum = 0
3609 22:55:41.783446 4, 0xFFFF, sum = 0
3610 22:55:41.783531 5, 0xFFFF, sum = 0
3611 22:55:41.786510 6, 0xFFFF, sum = 0
3612 22:55:41.786596 7, 0xFFFF, sum = 0
3613 22:55:41.790127 8, 0xFFFF, sum = 0
3614 22:55:41.790213 9, 0xFFFF, sum = 0
3615 22:55:41.793640 10, 0xFFFF, sum = 0
3616 22:55:41.793728 11, 0xFFFF, sum = 0
3617 22:55:41.796423 12, 0x0, sum = 1
3618 22:55:41.796508 13, 0x0, sum = 2
3619 22:55:41.799872 14, 0x0, sum = 3
3620 22:55:41.799958 15, 0x0, sum = 4
3621 22:55:41.803258 best_step = 13
3622 22:55:41.803344
3623 22:55:41.803423 ==
3624 22:55:41.806423 Dram Type= 6, Freq= 0, CH_1, rank 1
3625 22:55:41.809927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3626 22:55:41.810021 ==
3627 22:55:41.813205 RX Vref Scan: 0
3628 22:55:41.813288
3629 22:55:41.813354 RX Vref 0 -> 0, step: 1
3630 22:55:41.813414
3631 22:55:41.816838 RX Delay -21 -> 252, step: 4
3632 22:55:41.823182 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3633 22:55:41.826487 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3634 22:55:41.829714 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3635 22:55:41.832996 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3636 22:55:41.836278 iDelay=195, Bit 4, Center 110 (43 ~ 178) 136
3637 22:55:41.842784 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3638 22:55:41.845935 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3639 22:55:41.849487 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3640 22:55:41.852629 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3641 22:55:41.855914 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3642 22:55:41.862526 iDelay=195, Bit 10, Center 114 (47 ~ 182) 136
3643 22:55:41.865955 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3644 22:55:41.868867 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3645 22:55:41.872114 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3646 22:55:41.879091 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3647 22:55:41.882343 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3648 22:55:41.882444 ==
3649 22:55:41.885672 Dram Type= 6, Freq= 0, CH_1, rank 1
3650 22:55:41.888932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3651 22:55:41.889024 ==
3652 22:55:41.892009 DQS Delay:
3653 22:55:41.892096 DQS0 = 0, DQS1 = 0
3654 22:55:41.892182 DQM Delay:
3655 22:55:41.895667 DQM0 = 111, DQM1 = 111
3656 22:55:41.895760 DQ Delay:
3657 22:55:41.898664 DQ0 =114, DQ1 =110, DQ2 =100, DQ3 =108
3658 22:55:41.902120 DQ4 =110, DQ5 =120, DQ6 =122, DQ7 =110
3659 22:55:41.905581 DQ8 =98, DQ9 =100, DQ10 =114, DQ11 =106
3660 22:55:41.912021 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =120
3661 22:55:41.912133
3662 22:55:41.912223
3663 22:55:41.918433 [DQSOSCAuto] RK1, (LSB)MR18= 0xfd0d, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 411 ps
3664 22:55:41.921807 CH1 RK1: MR19=304, MR18=FD0D
3665 22:55:41.928258 CH1_RK1: MR19=0x304, MR18=0xFD0D, DQSOSC=405, MR23=63, INC=39, DEC=26
3666 22:55:41.931921 [RxdqsGatingPostProcess] freq 1200
3667 22:55:41.934984 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3668 22:55:41.938341 best DQS0 dly(2T, 0.5T) = (0, 11)
3669 22:55:41.941545 best DQS1 dly(2T, 0.5T) = (0, 11)
3670 22:55:41.945243 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3671 22:55:41.948264 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3672 22:55:41.951785 best DQS0 dly(2T, 0.5T) = (0, 11)
3673 22:55:41.954893 best DQS1 dly(2T, 0.5T) = (0, 11)
3674 22:55:41.958184 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3675 22:55:41.961751 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3676 22:55:41.964924 Pre-setting of DQS Precalculation
3677 22:55:41.967912 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3678 22:55:41.977960 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3679 22:55:41.984434 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3680 22:55:41.984550
3681 22:55:41.984641
3682 22:55:41.987727 [Calibration Summary] 2400 Mbps
3683 22:55:41.987813 CH 0, Rank 0
3684 22:55:41.991446 SW Impedance : PASS
3685 22:55:41.991534 DUTY Scan : NO K
3686 22:55:41.994687 ZQ Calibration : PASS
3687 22:55:41.997970 Jitter Meter : NO K
3688 22:55:41.998060 CBT Training : PASS
3689 22:55:42.001369 Write leveling : PASS
3690 22:55:42.004526 RX DQS gating : PASS
3691 22:55:42.004615 RX DQ/DQS(RDDQC) : PASS
3692 22:55:42.007625 TX DQ/DQS : PASS
3693 22:55:42.011748 RX DATLAT : PASS
3694 22:55:42.011843 RX DQ/DQS(Engine): PASS
3695 22:55:42.015082 TX OE : NO K
3696 22:55:42.015170 All Pass.
3697 22:55:42.015256
3698 22:55:42.017789 CH 0, Rank 1
3699 22:55:42.017875 SW Impedance : PASS
3700 22:55:42.020862 DUTY Scan : NO K
3701 22:55:42.024442 ZQ Calibration : PASS
3702 22:55:42.024540 Jitter Meter : NO K
3703 22:55:42.027477 CBT Training : PASS
3704 22:55:42.030789 Write leveling : PASS
3705 22:55:42.030905 RX DQS gating : PASS
3706 22:55:42.034283 RX DQ/DQS(RDDQC) : PASS
3707 22:55:42.037823 TX DQ/DQS : PASS
3708 22:55:42.037914 RX DATLAT : PASS
3709 22:55:42.040913 RX DQ/DQS(Engine): PASS
3710 22:55:42.044038 TX OE : NO K
3711 22:55:42.044129 All Pass.
3712 22:55:42.044215
3713 22:55:42.044294 CH 1, Rank 0
3714 22:55:42.047209 SW Impedance : PASS
3715 22:55:42.050568 DUTY Scan : NO K
3716 22:55:42.050657 ZQ Calibration : PASS
3717 22:55:42.053774 Jitter Meter : NO K
3718 22:55:42.056907 CBT Training : PASS
3719 22:55:42.056998 Write leveling : PASS
3720 22:55:42.060358 RX DQS gating : PASS
3721 22:55:42.060446 RX DQ/DQS(RDDQC) : PASS
3722 22:55:42.064006 TX DQ/DQS : PASS
3723 22:55:42.067202 RX DATLAT : PASS
3724 22:55:42.067292 RX DQ/DQS(Engine): PASS
3725 22:55:42.070433 TX OE : NO K
3726 22:55:42.070519 All Pass.
3727 22:55:42.070604
3728 22:55:42.073763 CH 1, Rank 1
3729 22:55:42.073850 SW Impedance : PASS
3730 22:55:42.077121 DUTY Scan : NO K
3731 22:55:42.080289 ZQ Calibration : PASS
3732 22:55:42.080378 Jitter Meter : NO K
3733 22:55:42.083608 CBT Training : PASS
3734 22:55:42.086781 Write leveling : PASS
3735 22:55:42.086912 RX DQS gating : PASS
3736 22:55:42.089952 RX DQ/DQS(RDDQC) : PASS
3737 22:55:42.093280 TX DQ/DQS : PASS
3738 22:55:42.093369 RX DATLAT : PASS
3739 22:55:42.096671 RX DQ/DQS(Engine): PASS
3740 22:55:42.100282 TX OE : NO K
3741 22:55:42.100374 All Pass.
3742 22:55:42.100461
3743 22:55:42.103601 DramC Write-DBI off
3744 22:55:42.103687 PER_BANK_REFRESH: Hybrid Mode
3745 22:55:42.107224 TX_TRACKING: ON
3746 22:55:42.113487 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3747 22:55:42.119899 [FAST_K] Save calibration result to emmc
3748 22:55:42.123108 dramc_set_vcore_voltage set vcore to 650000
3749 22:55:42.123214 Read voltage for 600, 5
3750 22:55:42.126268 Vio18 = 0
3751 22:55:42.126371 Vcore = 650000
3752 22:55:42.126438 Vdram = 0
3753 22:55:42.129854 Vddq = 0
3754 22:55:42.129941 Vmddr = 0
3755 22:55:42.133428 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3756 22:55:42.139644 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3757 22:55:42.143003 MEM_TYPE=3, freq_sel=19
3758 22:55:42.146122 sv_algorithm_assistance_LP4_1600
3759 22:55:42.149348 ============ PULL DRAM RESETB DOWN ============
3760 22:55:42.152609 ========== PULL DRAM RESETB DOWN end =========
3761 22:55:42.159533 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3762 22:55:42.162470 ===================================
3763 22:55:42.162569 LPDDR4 DRAM CONFIGURATION
3764 22:55:42.165909 ===================================
3765 22:55:42.169637 EX_ROW_EN[0] = 0x0
3766 22:55:42.169728 EX_ROW_EN[1] = 0x0
3767 22:55:42.172771 LP4Y_EN = 0x0
3768 22:55:42.176174 WORK_FSP = 0x0
3769 22:55:42.176263 WL = 0x2
3770 22:55:42.179513 RL = 0x2
3771 22:55:42.179600 BL = 0x2
3772 22:55:42.182823 RPST = 0x0
3773 22:55:42.182944 RD_PRE = 0x0
3774 22:55:42.186111 WR_PRE = 0x1
3775 22:55:42.186195 WR_PST = 0x0
3776 22:55:42.189343 DBI_WR = 0x0
3777 22:55:42.189426 DBI_RD = 0x0
3778 22:55:42.192529 OTF = 0x1
3779 22:55:42.195842 ===================================
3780 22:55:42.198990 ===================================
3781 22:55:42.199077 ANA top config
3782 22:55:42.202375 ===================================
3783 22:55:42.205477 DLL_ASYNC_EN = 0
3784 22:55:42.209500 ALL_SLAVE_EN = 1
3785 22:55:42.212330 NEW_RANK_MODE = 1
3786 22:55:42.212421 DLL_IDLE_MODE = 1
3787 22:55:42.215281 LP45_APHY_COMB_EN = 1
3788 22:55:42.218399 TX_ODT_DIS = 1
3789 22:55:42.221816 NEW_8X_MODE = 1
3790 22:55:42.225543 ===================================
3791 22:55:42.228635 ===================================
3792 22:55:42.231818 data_rate = 1200
3793 22:55:42.231909 CKR = 1
3794 22:55:42.235444 DQ_P2S_RATIO = 8
3795 22:55:42.238676 ===================================
3796 22:55:42.241625 CA_P2S_RATIO = 8
3797 22:55:42.244901 DQ_CA_OPEN = 0
3798 22:55:42.248235 DQ_SEMI_OPEN = 0
3799 22:55:42.251884 CA_SEMI_OPEN = 0
3800 22:55:42.251979 CA_FULL_RATE = 0
3801 22:55:42.255103 DQ_CKDIV4_EN = 1
3802 22:55:42.258662 CA_CKDIV4_EN = 1
3803 22:55:42.262114 CA_PREDIV_EN = 0
3804 22:55:42.264794 PH8_DLY = 0
3805 22:55:42.268667 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3806 22:55:42.268763 DQ_AAMCK_DIV = 4
3807 22:55:42.271724 CA_AAMCK_DIV = 4
3808 22:55:42.274788 CA_ADMCK_DIV = 4
3809 22:55:42.278431 DQ_TRACK_CA_EN = 0
3810 22:55:42.281267 CA_PICK = 600
3811 22:55:42.285072 CA_MCKIO = 600
3812 22:55:42.288262 MCKIO_SEMI = 0
3813 22:55:42.288351 PLL_FREQ = 2288
3814 22:55:42.291527 DQ_UI_PI_RATIO = 32
3815 22:55:42.294697 CA_UI_PI_RATIO = 0
3816 22:55:42.297984 ===================================
3817 22:55:42.301104 ===================================
3818 22:55:42.304275 memory_type:LPDDR4
3819 22:55:42.307880 GP_NUM : 10
3820 22:55:42.307966 SRAM_EN : 1
3821 22:55:42.311033 MD32_EN : 0
3822 22:55:42.314379 ===================================
3823 22:55:42.314481 [ANA_INIT] >>>>>>>>>>>>>>
3824 22:55:42.317427 <<<<<< [CONFIGURE PHASE]: ANA_TX
3825 22:55:42.320918 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3826 22:55:42.324419 ===================================
3827 22:55:42.327683 data_rate = 1200,PCW = 0X5800
3828 22:55:42.330944 ===================================
3829 22:55:42.334362 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3830 22:55:42.340432 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3831 22:55:42.347464 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3832 22:55:42.350628 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3833 22:55:42.353784 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3834 22:55:42.357609 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3835 22:55:42.360493 [ANA_INIT] flow start
3836 22:55:42.360574 [ANA_INIT] PLL >>>>>>>>
3837 22:55:42.363529 [ANA_INIT] PLL <<<<<<<<
3838 22:55:42.366833 [ANA_INIT] MIDPI >>>>>>>>
3839 22:55:42.370546 [ANA_INIT] MIDPI <<<<<<<<
3840 22:55:42.370628 [ANA_INIT] DLL >>>>>>>>
3841 22:55:42.373416 [ANA_INIT] flow end
3842 22:55:42.377039 ============ LP4 DIFF to SE enter ============
3843 22:55:42.380758 ============ LP4 DIFF to SE exit ============
3844 22:55:42.383909 [ANA_INIT] <<<<<<<<<<<<<
3845 22:55:42.386987 [Flow] Enable top DCM control >>>>>
3846 22:55:42.390408 [Flow] Enable top DCM control <<<<<
3847 22:55:42.393419 Enable DLL master slave shuffle
3848 22:55:42.400197 ==============================================================
3849 22:55:42.400280 Gating Mode config
3850 22:55:42.406732 ==============================================================
3851 22:55:42.406816 Config description:
3852 22:55:42.416837 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3853 22:55:42.423106 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3854 22:55:42.430094 SELPH_MODE 0: By rank 1: By Phase
3855 22:55:42.433081 ==============================================================
3856 22:55:42.436256 GAT_TRACK_EN = 1
3857 22:55:42.440086 RX_GATING_MODE = 2
3858 22:55:42.443100 RX_GATING_TRACK_MODE = 2
3859 22:55:42.446356 SELPH_MODE = 1
3860 22:55:42.449514 PICG_EARLY_EN = 1
3861 22:55:42.453045 VALID_LAT_VALUE = 1
3862 22:55:42.459773 ==============================================================
3863 22:55:42.462991 Enter into Gating configuration >>>>
3864 22:55:42.466393 Exit from Gating configuration <<<<
3865 22:55:42.466475 Enter into DVFS_PRE_config >>>>>
3866 22:55:42.479467 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3867 22:55:42.482787 Exit from DVFS_PRE_config <<<<<
3868 22:55:42.486226 Enter into PICG configuration >>>>
3869 22:55:42.488939 Exit from PICG configuration <<<<
3870 22:55:42.492413 [RX_INPUT] configuration >>>>>
3871 22:55:42.492504 [RX_INPUT] configuration <<<<<
3872 22:55:42.498908 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3873 22:55:42.505444 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3874 22:55:42.508678 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3875 22:55:42.515712 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3876 22:55:42.522123 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3877 22:55:42.528552 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3878 22:55:42.531828 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3879 22:55:42.535137 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3880 22:55:42.541645 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3881 22:55:42.544797 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3882 22:55:42.548322 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3883 22:55:42.555353 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3884 22:55:42.558322 ===================================
3885 22:55:42.558405 LPDDR4 DRAM CONFIGURATION
3886 22:55:42.561379 ===================================
3887 22:55:42.564848 EX_ROW_EN[0] = 0x0
3888 22:55:42.568104 EX_ROW_EN[1] = 0x0
3889 22:55:42.568187 LP4Y_EN = 0x0
3890 22:55:42.571309 WORK_FSP = 0x0
3891 22:55:42.571391 WL = 0x2
3892 22:55:42.575146 RL = 0x2
3893 22:55:42.575243 BL = 0x2
3894 22:55:42.577902 RPST = 0x0
3895 22:55:42.577984 RD_PRE = 0x0
3896 22:55:42.581261 WR_PRE = 0x1
3897 22:55:42.581343 WR_PST = 0x0
3898 22:55:42.584526 DBI_WR = 0x0
3899 22:55:42.584609 DBI_RD = 0x0
3900 22:55:42.588020 OTF = 0x1
3901 22:55:42.591148 ===================================
3902 22:55:42.594750 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3903 22:55:42.597916 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3904 22:55:42.604468 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3905 22:55:42.607656 ===================================
3906 22:55:42.607739 LPDDR4 DRAM CONFIGURATION
3907 22:55:42.611000 ===================================
3908 22:55:42.614281 EX_ROW_EN[0] = 0x10
3909 22:55:42.617468 EX_ROW_EN[1] = 0x0
3910 22:55:42.617549 LP4Y_EN = 0x0
3911 22:55:42.620963 WORK_FSP = 0x0
3912 22:55:42.621045 WL = 0x2
3913 22:55:42.624158 RL = 0x2
3914 22:55:42.624242 BL = 0x2
3915 22:55:42.627562 RPST = 0x0
3916 22:55:42.627646 RD_PRE = 0x0
3917 22:55:42.630769 WR_PRE = 0x1
3918 22:55:42.630891 WR_PST = 0x0
3919 22:55:42.634078 DBI_WR = 0x0
3920 22:55:42.634148 DBI_RD = 0x0
3921 22:55:42.637414 OTF = 0x1
3922 22:55:42.640600 ===================================
3923 22:55:42.647138 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3924 22:55:42.650378 nWR fixed to 30
3925 22:55:42.653933 [ModeRegInit_LP4] CH0 RK0
3926 22:55:42.654016 [ModeRegInit_LP4] CH0 RK1
3927 22:55:42.657548 [ModeRegInit_LP4] CH1 RK0
3928 22:55:42.660436 [ModeRegInit_LP4] CH1 RK1
3929 22:55:42.660519 match AC timing 17
3930 22:55:42.667014 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3931 22:55:42.670688 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3932 22:55:42.673827 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3933 22:55:42.680499 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3934 22:55:42.683564 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3935 22:55:42.683649 ==
3936 22:55:42.686733 Dram Type= 6, Freq= 0, CH_0, rank 0
3937 22:55:42.690040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3938 22:55:42.690124 ==
3939 22:55:42.696577 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3940 22:55:42.703733 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3941 22:55:42.706440 [CA 0] Center 37 (7~67) winsize 61
3942 22:55:42.709881 [CA 1] Center 37 (7~67) winsize 61
3943 22:55:42.713006 [CA 2] Center 35 (5~65) winsize 61
3944 22:55:42.716323 [CA 3] Center 35 (5~65) winsize 61
3945 22:55:42.719643 [CA 4] Center 34 (4~64) winsize 61
3946 22:55:42.722776 [CA 5] Center 34 (4~64) winsize 61
3947 22:55:42.722882
3948 22:55:42.726477 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3949 22:55:42.726561
3950 22:55:42.729944 [CATrainingPosCal] consider 1 rank data
3951 22:55:42.733332 u2DelayCellTimex100 = 270/100 ps
3952 22:55:42.736003 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3953 22:55:42.739540 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3954 22:55:42.742815 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3955 22:55:42.746135 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3956 22:55:42.752725 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3957 22:55:42.755820 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3958 22:55:42.755930
3959 22:55:42.759221 CA PerBit enable=1, Macro0, CA PI delay=34
3960 22:55:42.759331
3961 22:55:42.762441 [CBTSetCACLKResult] CA Dly = 34
3962 22:55:42.762524 CS Dly: 6 (0~37)
3963 22:55:42.762590 ==
3964 22:55:42.765858 Dram Type= 6, Freq= 0, CH_0, rank 1
3965 22:55:42.772627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3966 22:55:42.772711 ==
3967 22:55:42.776043 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3968 22:55:42.782420 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3969 22:55:42.785622 [CA 0] Center 37 (7~67) winsize 61
3970 22:55:42.788854 [CA 1] Center 37 (7~67) winsize 61
3971 22:55:42.792039 [CA 2] Center 35 (5~65) winsize 61
3972 22:55:42.795366 [CA 3] Center 35 (5~65) winsize 61
3973 22:55:42.799002 [CA 4] Center 34 (4~65) winsize 62
3974 22:55:42.802516 [CA 5] Center 34 (4~64) winsize 61
3975 22:55:42.802618
3976 22:55:42.805403 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3977 22:55:42.805504
3978 22:55:42.808601 [CATrainingPosCal] consider 2 rank data
3979 22:55:42.811931 u2DelayCellTimex100 = 270/100 ps
3980 22:55:42.815188 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3981 22:55:42.821985 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3982 22:55:42.824712 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3983 22:55:42.828616 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3984 22:55:42.831541 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3985 22:55:42.834871 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3986 22:55:42.834967
3987 22:55:42.838201 CA PerBit enable=1, Macro0, CA PI delay=34
3988 22:55:42.838282
3989 22:55:42.841830 [CBTSetCACLKResult] CA Dly = 34
3990 22:55:42.844593 CS Dly: 6 (0~38)
3991 22:55:42.844675
3992 22:55:42.847952 ----->DramcWriteLeveling(PI) begin...
3993 22:55:42.848035 ==
3994 22:55:42.851238 Dram Type= 6, Freq= 0, CH_0, rank 0
3995 22:55:42.854503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3996 22:55:42.854589 ==
3997 22:55:42.857611 Write leveling (Byte 0): 33 => 33
3998 22:55:42.860902 Write leveling (Byte 1): 32 => 32
3999 22:55:42.864397 DramcWriteLeveling(PI) end<-----
4000 22:55:42.864478
4001 22:55:42.864542 ==
4002 22:55:42.868133 Dram Type= 6, Freq= 0, CH_0, rank 0
4003 22:55:42.870945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4004 22:55:42.871028 ==
4005 22:55:42.874192 [Gating] SW mode calibration
4006 22:55:42.881191 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4007 22:55:42.887547 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4008 22:55:42.890950 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4009 22:55:42.897261 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4010 22:55:42.900925 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4011 22:55:42.904168 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4012 22:55:42.910600 0 9 16 | B1->B0 | 3333 2b2b | 1 1 | (0 1) (0 1)
4013 22:55:42.913767 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4014 22:55:42.917104 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4015 22:55:42.923780 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4016 22:55:42.927521 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4017 22:55:42.930681 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4018 22:55:42.936874 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4019 22:55:42.940033 0 10 12 | B1->B0 | 2424 2a2a | 0 0 | (0 0) (0 0)
4020 22:55:42.943291 0 10 16 | B1->B0 | 2f2f 3e3e | 0 0 | (0 0) (0 0)
4021 22:55:42.950467 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 22:55:42.953552 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 22:55:42.956813 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4024 22:55:42.959998 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 22:55:42.966433 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4026 22:55:42.969815 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 22:55:42.976713 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 22:55:42.979786 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4029 22:55:42.982927 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 22:55:42.986276 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 22:55:42.993172 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 22:55:42.996507 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 22:55:43.000002 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 22:55:43.006417 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 22:55:43.009553 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 22:55:43.013240 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 22:55:43.019617 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 22:55:43.022758 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 22:55:43.026087 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 22:55:43.032968 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 22:55:43.036453 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 22:55:43.039353 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 22:55:43.046390 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 22:55:43.049517 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 22:55:43.052673 Total UI for P1: 0, mck2ui 16
4046 22:55:43.056246 best dqsien dly found for B0: ( 0, 13, 14)
4047 22:55:43.059367 Total UI for P1: 0, mck2ui 16
4048 22:55:43.062601 best dqsien dly found for B1: ( 0, 13, 14)
4049 22:55:43.065634 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4050 22:55:43.069457 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4051 22:55:43.069541
4052 22:55:43.072819 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4053 22:55:43.078925 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4054 22:55:43.079008 [Gating] SW calibration Done
4055 22:55:43.079075 ==
4056 22:55:43.082246 Dram Type= 6, Freq= 0, CH_0, rank 0
4057 22:55:43.088771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4058 22:55:43.088855 ==
4059 22:55:43.088922 RX Vref Scan: 0
4060 22:55:43.088984
4061 22:55:43.092155 RX Vref 0 -> 0, step: 1
4062 22:55:43.092238
4063 22:55:43.095238 RX Delay -230 -> 252, step: 16
4064 22:55:43.098499 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4065 22:55:43.101915 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4066 22:55:43.108886 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4067 22:55:43.112300 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4068 22:55:43.115238 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4069 22:55:43.118603 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4070 22:55:43.124846 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4071 22:55:43.128521 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4072 22:55:43.131855 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4073 22:55:43.134884 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4074 22:55:43.138085 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4075 22:55:43.144977 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4076 22:55:43.147994 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4077 22:55:43.151278 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4078 22:55:43.154926 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4079 22:55:43.161536 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4080 22:55:43.161621 ==
4081 22:55:43.164768 Dram Type= 6, Freq= 0, CH_0, rank 0
4082 22:55:43.167993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4083 22:55:43.168076 ==
4084 22:55:43.168142 DQS Delay:
4085 22:55:43.171166 DQS0 = 0, DQS1 = 0
4086 22:55:43.171248 DQM Delay:
4087 22:55:43.174232 DQM0 = 38, DQM1 = 30
4088 22:55:43.174313 DQ Delay:
4089 22:55:43.177519 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4090 22:55:43.181405 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4091 22:55:43.184220 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4092 22:55:43.187932 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4093 22:55:43.188014
4094 22:55:43.188079
4095 22:55:43.188138 ==
4096 22:55:43.190977 Dram Type= 6, Freq= 0, CH_0, rank 0
4097 22:55:43.197597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4098 22:55:43.197680 ==
4099 22:55:43.197746
4100 22:55:43.197807
4101 22:55:43.197864 TX Vref Scan disable
4102 22:55:43.201306 == TX Byte 0 ==
4103 22:55:43.204486 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4104 22:55:43.210821 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4105 22:55:43.210925 == TX Byte 1 ==
4106 22:55:43.214295 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4107 22:55:43.220637 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4108 22:55:43.220725 ==
4109 22:55:43.223910 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 22:55:43.227656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 22:55:43.227741 ==
4112 22:55:43.227807
4113 22:55:43.227866
4114 22:55:43.230766 TX Vref Scan disable
4115 22:55:43.233832 == TX Byte 0 ==
4116 22:55:43.237031 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4117 22:55:43.240650 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4118 22:55:43.244063 == TX Byte 1 ==
4119 22:55:43.247138 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4120 22:55:43.250438 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4121 22:55:43.250521
4122 22:55:43.250587 [DATLAT]
4123 22:55:43.253978 Freq=600, CH0 RK0
4124 22:55:43.254060
4125 22:55:43.257093 DATLAT Default: 0x9
4126 22:55:43.257175 0, 0xFFFF, sum = 0
4127 22:55:43.260345 1, 0xFFFF, sum = 0
4128 22:55:43.260429 2, 0xFFFF, sum = 0
4129 22:55:43.263380 3, 0xFFFF, sum = 0
4130 22:55:43.263464 4, 0xFFFF, sum = 0
4131 22:55:43.266646 5, 0xFFFF, sum = 0
4132 22:55:43.266731 6, 0xFFFF, sum = 0
4133 22:55:43.270109 7, 0xFFFF, sum = 0
4134 22:55:43.270192 8, 0x0, sum = 1
4135 22:55:43.273195 9, 0x0, sum = 2
4136 22:55:43.273279 10, 0x0, sum = 3
4137 22:55:43.277000 11, 0x0, sum = 4
4138 22:55:43.277084 best_step = 9
4139 22:55:43.277150
4140 22:55:43.277209 ==
4141 22:55:43.279843 Dram Type= 6, Freq= 0, CH_0, rank 0
4142 22:55:43.283169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4143 22:55:43.283253 ==
4144 22:55:43.287133 RX Vref Scan: 1
4145 22:55:43.287216
4146 22:55:43.290100 RX Vref 0 -> 0, step: 1
4147 22:55:43.290183
4148 22:55:43.290247 RX Delay -195 -> 252, step: 8
4149 22:55:43.293723
4150 22:55:43.293805 Set Vref, RX VrefLevel [Byte0]: 62
4151 22:55:43.296473 [Byte1]: 52
4152 22:55:43.301220
4153 22:55:43.301303 Final RX Vref Byte 0 = 62 to rank0
4154 22:55:43.304890 Final RX Vref Byte 1 = 52 to rank0
4155 22:55:43.307793 Final RX Vref Byte 0 = 62 to rank1
4156 22:55:43.311439 Final RX Vref Byte 1 = 52 to rank1==
4157 22:55:43.314714 Dram Type= 6, Freq= 0, CH_0, rank 0
4158 22:55:43.321430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4159 22:55:43.321516 ==
4160 22:55:43.321581 DQS Delay:
4161 22:55:43.324374 DQS0 = 0, DQS1 = 0
4162 22:55:43.324457 DQM Delay:
4163 22:55:43.324523 DQM0 = 35, DQM1 = 29
4164 22:55:43.327469 DQ Delay:
4165 22:55:43.331345 DQ0 =36, DQ1 =36, DQ2 =36, DQ3 =32
4166 22:55:43.334454 DQ4 =36, DQ5 =20, DQ6 =40, DQ7 =44
4167 22:55:43.337391 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4168 22:55:43.340790 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =36
4169 22:55:43.340874
4170 22:55:43.340939
4171 22:55:43.347238 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d3d, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
4172 22:55:43.351071 CH0 RK0: MR19=808, MR18=3D3D
4173 22:55:43.357491 CH0_RK0: MR19=0x808, MR18=0x3D3D, DQSOSC=398, MR23=63, INC=165, DEC=110
4174 22:55:43.357577
4175 22:55:43.360893 ----->DramcWriteLeveling(PI) begin...
4176 22:55:43.360977 ==
4177 22:55:43.364129 Dram Type= 6, Freq= 0, CH_0, rank 1
4178 22:55:43.367276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4179 22:55:43.367360 ==
4180 22:55:43.370311 Write leveling (Byte 0): 36 => 36
4181 22:55:43.373696 Write leveling (Byte 1): 32 => 32
4182 22:55:43.376939 DramcWriteLeveling(PI) end<-----
4183 22:55:43.377023
4184 22:55:43.377087 ==
4185 22:55:43.380250 Dram Type= 6, Freq= 0, CH_0, rank 1
4186 22:55:43.386876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4187 22:55:43.386960 ==
4188 22:55:43.387026 [Gating] SW mode calibration
4189 22:55:43.396733 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4190 22:55:43.400319 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4191 22:55:43.403617 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4192 22:55:43.410623 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4193 22:55:43.413506 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4194 22:55:43.416770 0 9 12 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
4195 22:55:43.423389 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
4196 22:55:43.427283 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4197 22:55:43.429878 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4198 22:55:43.436843 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4199 22:55:43.440379 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4200 22:55:43.443186 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4201 22:55:43.449890 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4202 22:55:43.453505 0 10 12 | B1->B0 | 2a2a 3333 | 1 0 | (0 0) (0 0)
4203 22:55:43.456550 0 10 16 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
4204 22:55:43.463121 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 22:55:43.466480 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 22:55:43.469717 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4207 22:55:43.475926 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4208 22:55:43.479275 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4209 22:55:43.482345 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4210 22:55:43.489314 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4211 22:55:43.492581 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 22:55:43.495682 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 22:55:43.502365 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 22:55:43.505641 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 22:55:43.509369 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 22:55:43.515482 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 22:55:43.518988 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 22:55:43.521925 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 22:55:43.528840 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 22:55:43.531668 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 22:55:43.535349 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 22:55:43.541842 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 22:55:43.544959 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 22:55:43.548817 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 22:55:43.554912 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 22:55:43.558390 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 22:55:43.561435 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 22:55:43.564751 Total UI for P1: 0, mck2ui 16
4229 22:55:43.568424 best dqsien dly found for B0: ( 0, 13, 14)
4230 22:55:43.571631 Total UI for P1: 0, mck2ui 16
4231 22:55:43.574703 best dqsien dly found for B1: ( 0, 13, 14)
4232 22:55:43.577968 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4233 22:55:43.585150 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4234 22:55:43.585239
4235 22:55:43.587958 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4236 22:55:43.591564 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4237 22:55:43.594797 [Gating] SW calibration Done
4238 22:55:43.594910 ==
4239 22:55:43.598023 Dram Type= 6, Freq= 0, CH_0, rank 1
4240 22:55:43.601312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4241 22:55:43.601396 ==
4242 22:55:43.604491 RX Vref Scan: 0
4243 22:55:43.604573
4244 22:55:43.604638 RX Vref 0 -> 0, step: 1
4245 22:55:43.604698
4246 22:55:43.607717 RX Delay -230 -> 252, step: 16
4247 22:55:43.611017 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4248 22:55:43.617537 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4249 22:55:43.621567 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4250 22:55:43.624440 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4251 22:55:43.627167 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4252 22:55:43.633858 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4253 22:55:43.637181 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4254 22:55:43.640575 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4255 22:55:43.643859 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4256 22:55:43.650259 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4257 22:55:43.653505 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4258 22:55:43.657193 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4259 22:55:43.660437 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4260 22:55:43.667035 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4261 22:55:43.670278 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4262 22:55:43.673398 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4263 22:55:43.673483 ==
4264 22:55:43.676500 Dram Type= 6, Freq= 0, CH_0, rank 1
4265 22:55:43.679790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4266 22:55:43.683157 ==
4267 22:55:43.683240 DQS Delay:
4268 22:55:43.683306 DQS0 = 0, DQS1 = 0
4269 22:55:43.686973 DQM Delay:
4270 22:55:43.687056 DQM0 = 40, DQM1 = 30
4271 22:55:43.690475 DQ Delay:
4272 22:55:43.693300 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4273 22:55:43.693385 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4274 22:55:43.696484 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4275 22:55:43.699916 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =41
4276 22:55:43.703464
4277 22:55:43.703547
4278 22:55:43.703613 ==
4279 22:55:43.706815 Dram Type= 6, Freq= 0, CH_0, rank 1
4280 22:55:43.710115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4281 22:55:43.710198 ==
4282 22:55:43.710265
4283 22:55:43.710324
4284 22:55:43.713360 TX Vref Scan disable
4285 22:55:43.713443 == TX Byte 0 ==
4286 22:55:43.719612 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4287 22:55:43.722985 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4288 22:55:43.723070 == TX Byte 1 ==
4289 22:55:43.729537 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4290 22:55:43.732799 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4291 22:55:43.732889 ==
4292 22:55:43.736322 Dram Type= 6, Freq= 0, CH_0, rank 1
4293 22:55:43.739294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4294 22:55:43.739381 ==
4295 22:55:43.739446
4296 22:55:43.739505
4297 22:55:43.743094 TX Vref Scan disable
4298 22:55:43.746391 == TX Byte 0 ==
4299 22:55:43.749461 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4300 22:55:43.756245 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4301 22:55:43.756332 == TX Byte 1 ==
4302 22:55:43.759468 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4303 22:55:43.765924 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4304 22:55:43.766008
4305 22:55:43.766072 [DATLAT]
4306 22:55:43.766132 Freq=600, CH0 RK1
4307 22:55:43.766190
4308 22:55:43.769177 DATLAT Default: 0x9
4309 22:55:43.769259 0, 0xFFFF, sum = 0
4310 22:55:43.772844 1, 0xFFFF, sum = 0
4311 22:55:43.775851 2, 0xFFFF, sum = 0
4312 22:55:43.775933 3, 0xFFFF, sum = 0
4313 22:55:43.779417 4, 0xFFFF, sum = 0
4314 22:55:43.779499 5, 0xFFFF, sum = 0
4315 22:55:43.782429 6, 0xFFFF, sum = 0
4316 22:55:43.782510 7, 0xFFFF, sum = 0
4317 22:55:43.785591 8, 0x0, sum = 1
4318 22:55:43.785673 9, 0x0, sum = 2
4319 22:55:43.789247 10, 0x0, sum = 3
4320 22:55:43.789329 11, 0x0, sum = 4
4321 22:55:43.789393 best_step = 9
4322 22:55:43.789451
4323 22:55:43.792266 ==
4324 22:55:43.795857 Dram Type= 6, Freq= 0, CH_0, rank 1
4325 22:55:43.799381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4326 22:55:43.799462 ==
4327 22:55:43.799526 RX Vref Scan: 0
4328 22:55:43.799586
4329 22:55:43.802287 RX Vref 0 -> 0, step: 1
4330 22:55:43.802383
4331 22:55:43.805424 RX Delay -195 -> 252, step: 8
4332 22:55:43.812305 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4333 22:55:43.815517 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4334 22:55:43.818800 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4335 22:55:43.822223 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4336 22:55:43.825291 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4337 22:55:43.832043 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4338 22:55:43.835299 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4339 22:55:43.838611 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4340 22:55:43.842053 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4341 22:55:43.848466 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4342 22:55:43.851799 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4343 22:55:43.855127 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4344 22:55:43.858361 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4345 22:55:43.865196 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4346 22:55:43.868130 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4347 22:55:43.871399 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4348 22:55:43.871483 ==
4349 22:55:43.874656 Dram Type= 6, Freq= 0, CH_0, rank 1
4350 22:55:43.877905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 22:55:43.881831 ==
4352 22:55:43.881916 DQS Delay:
4353 22:55:43.881981 DQS0 = 0, DQS1 = 0
4354 22:55:43.885076 DQM Delay:
4355 22:55:43.885159 DQM0 = 34, DQM1 = 28
4356 22:55:43.888057 DQ Delay:
4357 22:55:43.888138 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4358 22:55:43.891347 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4359 22:55:43.894677 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4360 22:55:43.898032 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4361 22:55:43.898120
4362 22:55:43.901679
4363 22:55:43.908314 [DQSOSCAuto] RK1, (LSB)MR18= 0x6e3c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4364 22:55:43.911691 CH0 RK1: MR19=808, MR18=6E3C
4365 22:55:43.917658 CH0_RK1: MR19=0x808, MR18=0x6E3C, DQSOSC=389, MR23=63, INC=173, DEC=115
4366 22:55:43.921421 [RxdqsGatingPostProcess] freq 600
4367 22:55:43.924585 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4368 22:55:43.928073 Pre-setting of DQS Precalculation
4369 22:55:43.934459 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4370 22:55:43.934550 ==
4371 22:55:43.937516 Dram Type= 6, Freq= 0, CH_1, rank 0
4372 22:55:43.940843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4373 22:55:43.940928 ==
4374 22:55:43.947520 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4375 22:55:43.950619 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4376 22:55:43.955313 [CA 0] Center 35 (5~66) winsize 62
4377 22:55:43.958726 [CA 1] Center 36 (6~66) winsize 61
4378 22:55:43.961854 [CA 2] Center 34 (4~65) winsize 62
4379 22:55:43.965286 [CA 3] Center 34 (4~65) winsize 62
4380 22:55:43.968440 [CA 4] Center 34 (4~65) winsize 62
4381 22:55:43.972042 [CA 5] Center 34 (4~64) winsize 61
4382 22:55:43.972156
4383 22:55:43.975428 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4384 22:55:43.975513
4385 22:55:43.979141 [CATrainingPosCal] consider 1 rank data
4386 22:55:43.981844 u2DelayCellTimex100 = 270/100 ps
4387 22:55:43.985143 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4388 22:55:43.992131 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4389 22:55:43.994814 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4390 22:55:43.998137 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4391 22:55:44.001637 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4392 22:55:44.004817 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4393 22:55:44.004908
4394 22:55:44.008241 CA PerBit enable=1, Macro0, CA PI delay=34
4395 22:55:44.008328
4396 22:55:44.011384 [CBTSetCACLKResult] CA Dly = 34
4397 22:55:44.014797 CS Dly: 4 (0~35)
4398 22:55:44.014899 ==
4399 22:55:44.018383 Dram Type= 6, Freq= 0, CH_1, rank 1
4400 22:55:44.020987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4401 22:55:44.021092 ==
4402 22:55:44.027629 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4403 22:55:44.030962 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4404 22:55:44.035312 [CA 0] Center 36 (6~66) winsize 61
4405 22:55:44.038717 [CA 1] Center 36 (6~66) winsize 61
4406 22:55:44.041919 [CA 2] Center 34 (4~65) winsize 62
4407 22:55:44.045120 [CA 3] Center 34 (4~65) winsize 62
4408 22:55:44.048656 [CA 4] Center 34 (4~65) winsize 62
4409 22:55:44.052136 [CA 5] Center 34 (3~65) winsize 63
4410 22:55:44.052222
4411 22:55:44.054867 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4412 22:55:44.054952
4413 22:55:44.058477 [CATrainingPosCal] consider 2 rank data
4414 22:55:44.061444 u2DelayCellTimex100 = 270/100 ps
4415 22:55:44.065023 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4416 22:55:44.071428 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4417 22:55:44.075358 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4418 22:55:44.078382 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4419 22:55:44.081338 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4420 22:55:44.084890 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4421 22:55:44.084977
4422 22:55:44.088049 CA PerBit enable=1, Macro0, CA PI delay=34
4423 22:55:44.088133
4424 22:55:44.091338 [CBTSetCACLKResult] CA Dly = 34
4425 22:55:44.094566 CS Dly: 5 (0~38)
4426 22:55:44.094679
4427 22:55:44.097787 ----->DramcWriteLeveling(PI) begin...
4428 22:55:44.097872 ==
4429 22:55:44.100884 Dram Type= 6, Freq= 0, CH_1, rank 0
4430 22:55:44.104688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4431 22:55:44.104775 ==
4432 22:55:44.107781 Write leveling (Byte 0): 31 => 31
4433 22:55:44.110935 Write leveling (Byte 1): 30 => 30
4434 22:55:44.114206 DramcWriteLeveling(PI) end<-----
4435 22:55:44.114290
4436 22:55:44.114356 ==
4437 22:55:44.117887 Dram Type= 6, Freq= 0, CH_1, rank 0
4438 22:55:44.120819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4439 22:55:44.120904 ==
4440 22:55:44.124250 [Gating] SW mode calibration
4441 22:55:44.130716 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4442 22:55:44.137767 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4443 22:55:44.141188 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4444 22:55:44.144174 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4445 22:55:44.150616 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4446 22:55:44.153789 0 9 12 | B1->B0 | 3131 3030 | 1 1 | (1 1) (1 1)
4447 22:55:44.157310 0 9 16 | B1->B0 | 2828 2727 | 0 0 | (0 0) (1 0)
4448 22:55:44.164249 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4449 22:55:44.167220 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4450 22:55:44.170777 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4451 22:55:44.177215 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4452 22:55:44.180337 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4453 22:55:44.183500 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4454 22:55:44.190014 0 10 12 | B1->B0 | 2d2d 2d2d | 1 1 | (0 0) (0 0)
4455 22:55:44.193087 0 10 16 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
4456 22:55:44.196613 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 22:55:44.202835 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 22:55:44.206365 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 22:55:44.213492 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4460 22:55:44.216359 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 22:55:44.219494 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 22:55:44.226092 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4463 22:55:44.229872 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 22:55:44.232934 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 22:55:44.235845 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 22:55:44.242767 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 22:55:44.246172 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 22:55:44.252399 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 22:55:44.255743 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 22:55:44.258965 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 22:55:44.266365 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 22:55:44.269070 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 22:55:44.272055 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 22:55:44.278820 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 22:55:44.282679 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 22:55:44.285223 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 22:55:44.288902 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 22:55:44.295211 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 22:55:44.298503 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4480 22:55:44.302224 Total UI for P1: 0, mck2ui 16
4481 22:55:44.305006 best dqsien dly found for B1: ( 0, 13, 14)
4482 22:55:44.311481 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 22:55:44.311574 Total UI for P1: 0, mck2ui 16
4484 22:55:44.314777 best dqsien dly found for B0: ( 0, 13, 16)
4485 22:55:44.322076 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4486 22:55:44.324901 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4487 22:55:44.325097
4488 22:55:44.328232 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4489 22:55:44.331564 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4490 22:55:44.334962 [Gating] SW calibration Done
4491 22:55:44.335048 ==
4492 22:55:44.338055 Dram Type= 6, Freq= 0, CH_1, rank 0
4493 22:55:44.341249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4494 22:55:44.341336 ==
4495 22:55:44.344594 RX Vref Scan: 0
4496 22:55:44.344679
4497 22:55:44.344763 RX Vref 0 -> 0, step: 1
4498 22:55:44.347939
4499 22:55:44.348024 RX Delay -230 -> 252, step: 16
4500 22:55:44.354464 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4501 22:55:44.357628 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4502 22:55:44.360937 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4503 22:55:44.364111 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4504 22:55:44.371274 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4505 22:55:44.374581 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4506 22:55:44.377557 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4507 22:55:44.380822 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4508 22:55:44.384019 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4509 22:55:44.390954 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4510 22:55:44.393797 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4511 22:55:44.397276 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4512 22:55:44.400369 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4513 22:55:44.407200 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4514 22:55:44.410660 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4515 22:55:44.413742 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4516 22:55:44.413827 ==
4517 22:55:44.417079 Dram Type= 6, Freq= 0, CH_1, rank 0
4518 22:55:44.423891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4519 22:55:44.423978 ==
4520 22:55:44.424063 DQS Delay:
4521 22:55:44.424142 DQS0 = 0, DQS1 = 0
4522 22:55:44.426978 DQM Delay:
4523 22:55:44.427063 DQM0 = 39, DQM1 = 29
4524 22:55:44.430217 DQ Delay:
4525 22:55:44.433512 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4526 22:55:44.433597 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4527 22:55:44.436828 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4528 22:55:44.443252 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4529 22:55:44.443339
4530 22:55:44.443424
4531 22:55:44.443522 ==
4532 22:55:44.446585 Dram Type= 6, Freq= 0, CH_1, rank 0
4533 22:55:44.449926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4534 22:55:44.450012 ==
4535 22:55:44.450096
4536 22:55:44.450174
4537 22:55:44.453298 TX Vref Scan disable
4538 22:55:44.453382 == TX Byte 0 ==
4539 22:55:44.460178 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4540 22:55:44.463222 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4541 22:55:44.463308 == TX Byte 1 ==
4542 22:55:44.470161 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4543 22:55:44.473217 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4544 22:55:44.473306 ==
4545 22:55:44.476302 Dram Type= 6, Freq= 0, CH_1, rank 0
4546 22:55:44.479787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4547 22:55:44.479872 ==
4548 22:55:44.482760
4549 22:55:44.482884
4550 22:55:44.482987 TX Vref Scan disable
4551 22:55:44.486428 == TX Byte 0 ==
4552 22:55:44.489859 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4553 22:55:44.496914 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4554 22:55:44.497002 == TX Byte 1 ==
4555 22:55:44.499914 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4556 22:55:44.506411 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4557 22:55:44.506498
4558 22:55:44.506582 [DATLAT]
4559 22:55:44.506662 Freq=600, CH1 RK0
4560 22:55:44.506760
4561 22:55:44.509701 DATLAT Default: 0x9
4562 22:55:44.509789 0, 0xFFFF, sum = 0
4563 22:55:44.513271 1, 0xFFFF, sum = 0
4564 22:55:44.516113 2, 0xFFFF, sum = 0
4565 22:55:44.516198 3, 0xFFFF, sum = 0
4566 22:55:44.519800 4, 0xFFFF, sum = 0
4567 22:55:44.519886 5, 0xFFFF, sum = 0
4568 22:55:44.523022 6, 0xFFFF, sum = 0
4569 22:55:44.523108 7, 0xFFFF, sum = 0
4570 22:55:44.526366 8, 0x0, sum = 1
4571 22:55:44.526453 9, 0x0, sum = 2
4572 22:55:44.526538 10, 0x0, sum = 3
4573 22:55:44.529550 11, 0x0, sum = 4
4574 22:55:44.529635 best_step = 9
4575 22:55:44.529719
4576 22:55:44.532582 ==
4577 22:55:44.532666 Dram Type= 6, Freq= 0, CH_1, rank 0
4578 22:55:44.539487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4579 22:55:44.539572 ==
4580 22:55:44.539656 RX Vref Scan: 1
4581 22:55:44.539734
4582 22:55:44.542486 RX Vref 0 -> 0, step: 1
4583 22:55:44.542569
4584 22:55:44.545775 RX Delay -195 -> 252, step: 8
4585 22:55:44.545859
4586 22:55:44.549124 Set Vref, RX VrefLevel [Byte0]: 56
4587 22:55:44.552815 [Byte1]: 55
4588 22:55:44.552898
4589 22:55:44.556215 Final RX Vref Byte 0 = 56 to rank0
4590 22:55:44.559434 Final RX Vref Byte 1 = 55 to rank0
4591 22:55:44.562597 Final RX Vref Byte 0 = 56 to rank1
4592 22:55:44.565675 Final RX Vref Byte 1 = 55 to rank1==
4593 22:55:44.568919 Dram Type= 6, Freq= 0, CH_1, rank 0
4594 22:55:44.572243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4595 22:55:44.576182 ==
4596 22:55:44.576265 DQS Delay:
4597 22:55:44.576330 DQS0 = 0, DQS1 = 0
4598 22:55:44.579118 DQM Delay:
4599 22:55:44.579200 DQM0 = 39, DQM1 = 28
4600 22:55:44.582564 DQ Delay:
4601 22:55:44.585556 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4602 22:55:44.585639 DQ4 =36, DQ5 =52, DQ6 =48, DQ7 =36
4603 22:55:44.588739 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4604 22:55:44.592310 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4605 22:55:44.595763
4606 22:55:44.595845
4607 22:55:44.601965 [DQSOSCAuto] RK0, (LSB)MR18= 0x2733, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 402 ps
4608 22:55:44.605800 CH1 RK0: MR19=808, MR18=2733
4609 22:55:44.612224 CH1_RK0: MR19=0x808, MR18=0x2733, DQSOSC=400, MR23=63, INC=163, DEC=109
4610 22:55:44.612307
4611 22:55:44.615316 ----->DramcWriteLeveling(PI) begin...
4612 22:55:44.615412 ==
4613 22:55:44.618282 Dram Type= 6, Freq= 0, CH_1, rank 1
4614 22:55:44.621679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4615 22:55:44.621764 ==
4616 22:55:44.624960 Write leveling (Byte 0): 31 => 31
4617 22:55:44.628352 Write leveling (Byte 1): 30 => 30
4618 22:55:44.631919 DramcWriteLeveling(PI) end<-----
4619 22:55:44.632041
4620 22:55:44.632108 ==
4621 22:55:44.635252 Dram Type= 6, Freq= 0, CH_1, rank 1
4622 22:55:44.638286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4623 22:55:44.638374 ==
4624 22:55:44.641580 [Gating] SW mode calibration
4625 22:55:44.648127 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4626 22:55:44.654781 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4627 22:55:44.657981 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4628 22:55:44.664477 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4629 22:55:44.667766 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4630 22:55:44.670804 0 9 12 | B1->B0 | 3030 3030 | 0 0 | (0 1) (0 1)
4631 22:55:44.677859 0 9 16 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)
4632 22:55:44.681298 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4633 22:55:44.684647 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4634 22:55:44.691146 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4635 22:55:44.694394 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4636 22:55:44.697741 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4637 22:55:44.704070 0 10 8 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
4638 22:55:44.707160 0 10 12 | B1->B0 | 3333 3c3c | 0 0 | (0 0) (0 0)
4639 22:55:44.710699 0 10 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
4640 22:55:44.717236 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 22:55:44.720278 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4642 22:55:44.723504 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 22:55:44.730430 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 22:55:44.733239 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4645 22:55:44.737117 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4646 22:55:44.743420 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4647 22:55:44.747050 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 22:55:44.750115 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 22:55:44.756507 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 22:55:44.759745 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 22:55:44.763364 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 22:55:44.770144 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 22:55:44.773353 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 22:55:44.776938 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 22:55:44.783028 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 22:55:44.786374 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 22:55:44.789731 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 22:55:44.796417 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 22:55:44.799851 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 22:55:44.803237 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 22:55:44.809208 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 22:55:44.812692 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4663 22:55:44.815754 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 22:55:44.819322 Total UI for P1: 0, mck2ui 16
4665 22:55:44.822541 best dqsien dly found for B0: ( 0, 13, 12)
4666 22:55:44.825943 Total UI for P1: 0, mck2ui 16
4667 22:55:44.829245 best dqsien dly found for B1: ( 0, 13, 14)
4668 22:55:44.832446 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4669 22:55:44.835978 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4670 22:55:44.839328
4671 22:55:44.842525 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4672 22:55:44.845802 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4673 22:55:44.848900 [Gating] SW calibration Done
4674 22:55:44.848981 ==
4675 22:55:44.852206 Dram Type= 6, Freq= 0, CH_1, rank 1
4676 22:55:44.855366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4677 22:55:44.855449 ==
4678 22:55:44.855514 RX Vref Scan: 0
4679 22:55:44.858620
4680 22:55:44.858701 RX Vref 0 -> 0, step: 1
4681 22:55:44.858767
4682 22:55:44.862078 RX Delay -230 -> 252, step: 16
4683 22:55:44.865149 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4684 22:55:44.871586 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4685 22:55:44.875123 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4686 22:55:44.878838 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4687 22:55:44.881954 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4688 22:55:44.888148 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4689 22:55:44.891955 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4690 22:55:44.894733 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4691 22:55:44.898045 iDelay=218, Bit 8, Center 9 (-166 ~ 185) 352
4692 22:55:44.901733 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4693 22:55:44.907858 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4694 22:55:44.912235 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4695 22:55:44.914759 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4696 22:55:44.917852 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4697 22:55:44.924362 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4698 22:55:44.927944 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4699 22:55:44.928029 ==
4700 22:55:44.930937 Dram Type= 6, Freq= 0, CH_1, rank 1
4701 22:55:44.934167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4702 22:55:44.934249 ==
4703 22:55:44.937775 DQS Delay:
4704 22:55:44.937856 DQS0 = 0, DQS1 = 0
4705 22:55:44.940814 DQM Delay:
4706 22:55:44.940896 DQM0 = 35, DQM1 = 29
4707 22:55:44.940960 DQ Delay:
4708 22:55:44.944166 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4709 22:55:44.947504 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4710 22:55:44.950960 DQ8 =9, DQ9 =17, DQ10 =33, DQ11 =25
4711 22:55:44.954190 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =41
4712 22:55:44.954272
4713 22:55:44.954337
4714 22:55:44.957305 ==
4715 22:55:44.961133 Dram Type= 6, Freq= 0, CH_1, rank 1
4716 22:55:44.964228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4717 22:55:44.964310 ==
4718 22:55:44.964374
4719 22:55:44.964433
4720 22:55:44.967230 TX Vref Scan disable
4721 22:55:44.967312 == TX Byte 0 ==
4722 22:55:44.973762 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4723 22:55:44.977194 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4724 22:55:44.977276 == TX Byte 1 ==
4725 22:55:44.984027 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4726 22:55:44.987347 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4727 22:55:44.987429 ==
4728 22:55:44.990756 Dram Type= 6, Freq= 0, CH_1, rank 1
4729 22:55:44.994060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4730 22:55:44.994143 ==
4731 22:55:44.994208
4732 22:55:44.994267
4733 22:55:44.996877 TX Vref Scan disable
4734 22:55:45.000165 == TX Byte 0 ==
4735 22:55:45.003683 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4736 22:55:45.006881 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4737 22:55:45.010018 == TX Byte 1 ==
4738 22:55:45.013422 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4739 22:55:45.017247 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4740 22:55:45.020233
4741 22:55:45.020314 [DATLAT]
4742 22:55:45.020378 Freq=600, CH1 RK1
4743 22:55:45.020452
4744 22:55:45.023079 DATLAT Default: 0x9
4745 22:55:45.023160 0, 0xFFFF, sum = 0
4746 22:55:45.026679 1, 0xFFFF, sum = 0
4747 22:55:45.026764 2, 0xFFFF, sum = 0
4748 22:55:45.029746 3, 0xFFFF, sum = 0
4749 22:55:45.029838 4, 0xFFFF, sum = 0
4750 22:55:45.033479 5, 0xFFFF, sum = 0
4751 22:55:45.036356 6, 0xFFFF, sum = 0
4752 22:55:45.036438 7, 0xFFFF, sum = 0
4753 22:55:45.036504 8, 0x0, sum = 1
4754 22:55:45.039872 9, 0x0, sum = 2
4755 22:55:45.039956 10, 0x0, sum = 3
4756 22:55:45.043181 11, 0x0, sum = 4
4757 22:55:45.043263 best_step = 9
4758 22:55:45.043328
4759 22:55:45.043387 ==
4760 22:55:45.046534 Dram Type= 6, Freq= 0, CH_1, rank 1
4761 22:55:45.052902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4762 22:55:45.052985 ==
4763 22:55:45.053050 RX Vref Scan: 0
4764 22:55:45.053114
4765 22:55:45.056780 RX Vref 0 -> 0, step: 1
4766 22:55:45.056861
4767 22:55:45.059604 RX Delay -211 -> 252, step: 8
4768 22:55:45.062734 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4769 22:55:45.069327 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4770 22:55:45.072706 iDelay=205, Bit 2, Center 20 (-139 ~ 180) 320
4771 22:55:45.076077 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4772 22:55:45.079192 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4773 22:55:45.086214 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4774 22:55:45.089461 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4775 22:55:45.092908 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4776 22:55:45.095744 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4777 22:55:45.102443 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4778 22:55:45.105921 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4779 22:55:45.108997 iDelay=205, Bit 11, Center 24 (-139 ~ 188) 328
4780 22:55:45.112692 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4781 22:55:45.118792 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4782 22:55:45.122031 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4783 22:55:45.125758 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4784 22:55:45.125842 ==
4785 22:55:45.128850 Dram Type= 6, Freq= 0, CH_1, rank 1
4786 22:55:45.132241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4787 22:55:45.135359 ==
4788 22:55:45.135442 DQS Delay:
4789 22:55:45.135508 DQS0 = 0, DQS1 = 0
4790 22:55:45.138342 DQM Delay:
4791 22:55:45.138424 DQM0 = 35, DQM1 = 29
4792 22:55:45.141624 DQ Delay:
4793 22:55:45.141707 DQ0 =40, DQ1 =32, DQ2 =20, DQ3 =32
4794 22:55:45.145690 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =32
4795 22:55:45.148320 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =24
4796 22:55:45.152123 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4797 22:55:45.152207
4798 22:55:45.155288
4799 22:55:45.161584 [DQSOSCAuto] RK1, (LSB)MR18= 0x3555, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4800 22:55:45.165297 CH1 RK1: MR19=808, MR18=3555
4801 22:55:45.171300 CH1_RK1: MR19=0x808, MR18=0x3555, DQSOSC=393, MR23=63, INC=169, DEC=113
4802 22:55:45.174765 [RxdqsGatingPostProcess] freq 600
4803 22:55:45.178397 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4804 22:55:45.181346 Pre-setting of DQS Precalculation
4805 22:55:45.188103 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4806 22:55:45.194409 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4807 22:55:45.201515 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4808 22:55:45.201601
4809 22:55:45.201668
4810 22:55:45.204797 [Calibration Summary] 1200 Mbps
4811 22:55:45.204881 CH 0, Rank 0
4812 22:55:45.207918 SW Impedance : PASS
4813 22:55:45.211318 DUTY Scan : NO K
4814 22:55:45.211401 ZQ Calibration : PASS
4815 22:55:45.214699 Jitter Meter : NO K
4816 22:55:45.218012 CBT Training : PASS
4817 22:55:45.218094 Write leveling : PASS
4818 22:55:45.220813 RX DQS gating : PASS
4819 22:55:45.224664 RX DQ/DQS(RDDQC) : PASS
4820 22:55:45.224746 TX DQ/DQS : PASS
4821 22:55:45.228005 RX DATLAT : PASS
4822 22:55:45.231132 RX DQ/DQS(Engine): PASS
4823 22:55:45.231215 TX OE : NO K
4824 22:55:45.231281 All Pass.
4825 22:55:45.234191
4826 22:55:45.234274 CH 0, Rank 1
4827 22:55:45.237496 SW Impedance : PASS
4828 22:55:45.237579 DUTY Scan : NO K
4829 22:55:45.240766 ZQ Calibration : PASS
4830 22:55:45.240848 Jitter Meter : NO K
4831 22:55:45.243917 CBT Training : PASS
4832 22:55:45.247159 Write leveling : PASS
4833 22:55:45.247242 RX DQS gating : PASS
4834 22:55:45.250674 RX DQ/DQS(RDDQC) : PASS
4835 22:55:45.253985 TX DQ/DQS : PASS
4836 22:55:45.254068 RX DATLAT : PASS
4837 22:55:45.257328 RX DQ/DQS(Engine): PASS
4838 22:55:45.260413 TX OE : NO K
4839 22:55:45.260496 All Pass.
4840 22:55:45.260561
4841 22:55:45.260621 CH 1, Rank 0
4842 22:55:45.264000 SW Impedance : PASS
4843 22:55:45.267137 DUTY Scan : NO K
4844 22:55:45.267219 ZQ Calibration : PASS
4845 22:55:45.270446 Jitter Meter : NO K
4846 22:55:45.273531 CBT Training : PASS
4847 22:55:45.273613 Write leveling : PASS
4848 22:55:45.276951 RX DQS gating : PASS
4849 22:55:45.280235 RX DQ/DQS(RDDQC) : PASS
4850 22:55:45.280318 TX DQ/DQS : PASS
4851 22:55:45.283406 RX DATLAT : PASS
4852 22:55:45.286879 RX DQ/DQS(Engine): PASS
4853 22:55:45.286960 TX OE : NO K
4854 22:55:45.290173 All Pass.
4855 22:55:45.290255
4856 22:55:45.290319 CH 1, Rank 1
4857 22:55:45.293344 SW Impedance : PASS
4858 22:55:45.293427 DUTY Scan : NO K
4859 22:55:45.296983 ZQ Calibration : PASS
4860 22:55:45.299782 Jitter Meter : NO K
4861 22:55:45.299865 CBT Training : PASS
4862 22:55:45.303162 Write leveling : PASS
4863 22:55:45.306327 RX DQS gating : PASS
4864 22:55:45.306427 RX DQ/DQS(RDDQC) : PASS
4865 22:55:45.309748 TX DQ/DQS : PASS
4866 22:55:45.313181 RX DATLAT : PASS
4867 22:55:45.313264 RX DQ/DQS(Engine): PASS
4868 22:55:45.316387 TX OE : NO K
4869 22:55:45.316470 All Pass.
4870 22:55:45.316535
4871 22:55:45.319671 DramC Write-DBI off
4872 22:55:45.322795 PER_BANK_REFRESH: Hybrid Mode
4873 22:55:45.322918 TX_TRACKING: ON
4874 22:55:45.333309 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4875 22:55:45.336350 [FAST_K] Save calibration result to emmc
4876 22:55:45.339756 dramc_set_vcore_voltage set vcore to 662500
4877 22:55:45.342492 Read voltage for 933, 3
4878 22:55:45.342574 Vio18 = 0
4879 22:55:45.342639 Vcore = 662500
4880 22:55:45.345865 Vdram = 0
4881 22:55:45.345948 Vddq = 0
4882 22:55:45.346013 Vmddr = 0
4883 22:55:45.352826 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4884 22:55:45.355785 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4885 22:55:45.359366 MEM_TYPE=3, freq_sel=17
4886 22:55:45.362825 sv_algorithm_assistance_LP4_1600
4887 22:55:45.365831 ============ PULL DRAM RESETB DOWN ============
4888 22:55:45.368959 ========== PULL DRAM RESETB DOWN end =========
4889 22:55:45.376041 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4890 22:55:45.379288 ===================================
4891 22:55:45.379372 LPDDR4 DRAM CONFIGURATION
4892 22:55:45.382529 ===================================
4893 22:55:45.385935 EX_ROW_EN[0] = 0x0
4894 22:55:45.389119 EX_ROW_EN[1] = 0x0
4895 22:55:45.389202 LP4Y_EN = 0x0
4896 22:55:45.392733 WORK_FSP = 0x0
4897 22:55:45.392831 WL = 0x3
4898 22:55:45.395654 RL = 0x3
4899 22:55:45.395737 BL = 0x2
4900 22:55:45.398866 RPST = 0x0
4901 22:55:45.398961 RD_PRE = 0x0
4902 22:55:45.402267 WR_PRE = 0x1
4903 22:55:45.402364 WR_PST = 0x0
4904 22:55:45.405258 DBI_WR = 0x0
4905 22:55:45.405340 DBI_RD = 0x0
4906 22:55:45.408895 OTF = 0x1
4907 22:55:45.411974 ===================================
4908 22:55:45.415372 ===================================
4909 22:55:45.415455 ANA top config
4910 22:55:45.418647 ===================================
4911 22:55:45.422108 DLL_ASYNC_EN = 0
4912 22:55:45.425671 ALL_SLAVE_EN = 1
4913 22:55:45.428471 NEW_RANK_MODE = 1
4914 22:55:45.431774 DLL_IDLE_MODE = 1
4915 22:55:45.431858 LP45_APHY_COMB_EN = 1
4916 22:55:45.435087 TX_ODT_DIS = 1
4917 22:55:45.438290 NEW_8X_MODE = 1
4918 22:55:45.441559 ===================================
4919 22:55:45.445073 ===================================
4920 22:55:45.448381 data_rate = 1866
4921 22:55:45.451750 CKR = 1
4922 22:55:45.451833 DQ_P2S_RATIO = 8
4923 22:55:45.455061 ===================================
4924 22:55:45.458233 CA_P2S_RATIO = 8
4925 22:55:45.461690 DQ_CA_OPEN = 0
4926 22:55:45.464837 DQ_SEMI_OPEN = 0
4927 22:55:45.467943 CA_SEMI_OPEN = 0
4928 22:55:45.471370 CA_FULL_RATE = 0
4929 22:55:45.471453 DQ_CKDIV4_EN = 1
4930 22:55:45.474686 CA_CKDIV4_EN = 1
4931 22:55:45.477994 CA_PREDIV_EN = 0
4932 22:55:45.480995 PH8_DLY = 0
4933 22:55:45.484274 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4934 22:55:45.488065 DQ_AAMCK_DIV = 4
4935 22:55:45.488148 CA_AAMCK_DIV = 4
4936 22:55:45.491308 CA_ADMCK_DIV = 4
4937 22:55:45.494589 DQ_TRACK_CA_EN = 0
4938 22:55:45.497995 CA_PICK = 933
4939 22:55:45.501187 CA_MCKIO = 933
4940 22:55:45.504748 MCKIO_SEMI = 0
4941 22:55:45.507697 PLL_FREQ = 3732
4942 22:55:45.510679 DQ_UI_PI_RATIO = 32
4943 22:55:45.510761 CA_UI_PI_RATIO = 0
4944 22:55:45.514081 ===================================
4945 22:55:45.517601 ===================================
4946 22:55:45.520551 memory_type:LPDDR4
4947 22:55:45.524205 GP_NUM : 10
4948 22:55:45.524288 SRAM_EN : 1
4949 22:55:45.527481 MD32_EN : 0
4950 22:55:45.530476 ===================================
4951 22:55:45.534124 [ANA_INIT] >>>>>>>>>>>>>>
4952 22:55:45.537089 <<<<<< [CONFIGURE PHASE]: ANA_TX
4953 22:55:45.540577 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4954 22:55:45.543764 ===================================
4955 22:55:45.543847 data_rate = 1866,PCW = 0X8f00
4956 22:55:45.546773 ===================================
4957 22:55:45.553885 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4958 22:55:45.557161 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4959 22:55:45.563352 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4960 22:55:45.567250 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4961 22:55:45.569999 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4962 22:55:45.573504 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4963 22:55:45.576557 [ANA_INIT] flow start
4964 22:55:45.579839 [ANA_INIT] PLL >>>>>>>>
4965 22:55:45.579923 [ANA_INIT] PLL <<<<<<<<
4966 22:55:45.583110 [ANA_INIT] MIDPI >>>>>>>>
4967 22:55:45.586721 [ANA_INIT] MIDPI <<<<<<<<
4968 22:55:45.586803 [ANA_INIT] DLL >>>>>>>>
4969 22:55:45.589828 [ANA_INIT] flow end
4970 22:55:45.592964 ============ LP4 DIFF to SE enter ============
4971 22:55:45.599805 ============ LP4 DIFF to SE exit ============
4972 22:55:45.599915 [ANA_INIT] <<<<<<<<<<<<<
4973 22:55:45.603790 [Flow] Enable top DCM control >>>>>
4974 22:55:45.606300 [Flow] Enable top DCM control <<<<<
4975 22:55:45.609736 Enable DLL master slave shuffle
4976 22:55:45.616002 ==============================================================
4977 22:55:45.616089 Gating Mode config
4978 22:55:45.622651 ==============================================================
4979 22:55:45.626102 Config description:
4980 22:55:45.636214 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4981 22:55:45.642952 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4982 22:55:45.645639 SELPH_MODE 0: By rank 1: By Phase
4983 22:55:45.652646 ==============================================================
4984 22:55:45.655917 GAT_TRACK_EN = 1
4985 22:55:45.656009 RX_GATING_MODE = 2
4986 22:55:45.659390 RX_GATING_TRACK_MODE = 2
4987 22:55:45.662402 SELPH_MODE = 1
4988 22:55:45.665907 PICG_EARLY_EN = 1
4989 22:55:45.669101 VALID_LAT_VALUE = 1
4990 22:55:45.675840 ==============================================================
4991 22:55:45.679002 Enter into Gating configuration >>>>
4992 22:55:45.682324 Exit from Gating configuration <<<<
4993 22:55:45.685445 Enter into DVFS_PRE_config >>>>>
4994 22:55:45.695504 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4995 22:55:45.698594 Exit from DVFS_PRE_config <<<<<
4996 22:55:45.702055 Enter into PICG configuration >>>>
4997 22:55:45.705230 Exit from PICG configuration <<<<
4998 22:55:45.708314 [RX_INPUT] configuration >>>>>
4999 22:55:45.712194 [RX_INPUT] configuration <<<<<
5000 22:55:45.714817 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5001 22:55:45.721357 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5002 22:55:45.728242 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5003 22:55:45.735209 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5004 22:55:45.741214 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5005 22:55:45.744493 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5006 22:55:45.751145 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5007 22:55:45.754296 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5008 22:55:45.757935 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5009 22:55:45.761242 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5010 22:55:45.767870 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5011 22:55:45.770823 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5012 22:55:45.774465 ===================================
5013 22:55:45.777640 LPDDR4 DRAM CONFIGURATION
5014 22:55:45.781006 ===================================
5015 22:55:45.781091 EX_ROW_EN[0] = 0x0
5016 22:55:45.784313 EX_ROW_EN[1] = 0x0
5017 22:55:45.784397 LP4Y_EN = 0x0
5018 22:55:45.787347 WORK_FSP = 0x0
5019 22:55:45.787431 WL = 0x3
5020 22:55:45.790814 RL = 0x3
5021 22:55:45.794080 BL = 0x2
5022 22:55:45.794163 RPST = 0x0
5023 22:55:45.797657 RD_PRE = 0x0
5024 22:55:45.797740 WR_PRE = 0x1
5025 22:55:45.800972 WR_PST = 0x0
5026 22:55:45.801056 DBI_WR = 0x0
5027 22:55:45.804027 DBI_RD = 0x0
5028 22:55:45.804111 OTF = 0x1
5029 22:55:45.807760 ===================================
5030 22:55:45.810640 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5031 22:55:45.817259 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5032 22:55:45.820701 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5033 22:55:45.823845 ===================================
5034 22:55:45.827173 LPDDR4 DRAM CONFIGURATION
5035 22:55:45.830344 ===================================
5036 22:55:45.830428 EX_ROW_EN[0] = 0x10
5037 22:55:45.833718 EX_ROW_EN[1] = 0x0
5038 22:55:45.833792 LP4Y_EN = 0x0
5039 22:55:45.836890 WORK_FSP = 0x0
5040 22:55:45.836973 WL = 0x3
5041 22:55:45.840300 RL = 0x3
5042 22:55:45.843844 BL = 0x2
5043 22:55:45.843926 RPST = 0x0
5044 22:55:45.846943 RD_PRE = 0x0
5045 22:55:45.847026 WR_PRE = 0x1
5046 22:55:45.850193 WR_PST = 0x0
5047 22:55:45.850275 DBI_WR = 0x0
5048 22:55:45.853415 DBI_RD = 0x0
5049 22:55:45.853497 OTF = 0x1
5050 22:55:45.856779 ===================================
5051 22:55:45.863232 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5052 22:55:45.867460 nWR fixed to 30
5053 22:55:45.870816 [ModeRegInit_LP4] CH0 RK0
5054 22:55:45.870908 [ModeRegInit_LP4] CH0 RK1
5055 22:55:45.874019 [ModeRegInit_LP4] CH1 RK0
5056 22:55:45.877330 [ModeRegInit_LP4] CH1 RK1
5057 22:55:45.877412 match AC timing 9
5058 22:55:45.884222 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5059 22:55:45.887373 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5060 22:55:45.890331 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5061 22:55:45.897067 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5062 22:55:45.900263 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5063 22:55:45.900349 ==
5064 22:55:45.903495 Dram Type= 6, Freq= 0, CH_0, rank 0
5065 22:55:45.906806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5066 22:55:45.909941 ==
5067 22:55:45.913571 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5068 22:55:45.920213 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5069 22:55:45.923612 [CA 0] Center 38 (8~69) winsize 62
5070 22:55:45.926624 [CA 1] Center 38 (8~69) winsize 62
5071 22:55:45.929926 [CA 2] Center 35 (5~65) winsize 61
5072 22:55:45.933087 [CA 3] Center 35 (5~65) winsize 61
5073 22:55:45.936453 [CA 4] Center 34 (4~64) winsize 61
5074 22:55:45.939906 [CA 5] Center 33 (3~64) winsize 62
5075 22:55:45.939989
5076 22:55:45.942940 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5077 22:55:45.943023
5078 22:55:45.946527 [CATrainingPosCal] consider 1 rank data
5079 22:55:45.949356 u2DelayCellTimex100 = 270/100 ps
5080 22:55:45.953463 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5081 22:55:45.956458 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5082 22:55:45.962838 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5083 22:55:45.965884 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5084 22:55:45.969386 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5085 22:55:45.972641 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5086 22:55:45.972724
5087 22:55:45.975869 CA PerBit enable=1, Macro0, CA PI delay=33
5088 22:55:45.975952
5089 22:55:45.979229 [CBTSetCACLKResult] CA Dly = 33
5090 22:55:45.979311 CS Dly: 7 (0~38)
5091 22:55:45.982995 ==
5092 22:55:45.985765 Dram Type= 6, Freq= 0, CH_0, rank 1
5093 22:55:45.989179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5094 22:55:45.989262 ==
5095 22:55:45.992185 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5096 22:55:45.998949 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5097 22:55:46.002572 [CA 0] Center 38 (8~69) winsize 62
5098 22:55:46.005774 [CA 1] Center 38 (8~69) winsize 62
5099 22:55:46.009104 [CA 2] Center 35 (5~65) winsize 61
5100 22:55:46.012183 [CA 3] Center 35 (5~65) winsize 61
5101 22:55:46.015736 [CA 4] Center 34 (4~65) winsize 62
5102 22:55:46.018784 [CA 5] Center 33 (3~64) winsize 62
5103 22:55:46.018915
5104 22:55:46.022263 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5105 22:55:46.022346
5106 22:55:46.025482 [CATrainingPosCal] consider 2 rank data
5107 22:55:46.028750 u2DelayCellTimex100 = 270/100 ps
5108 22:55:46.032014 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5109 22:55:46.038971 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5110 22:55:46.042268 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5111 22:55:46.045185 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5112 22:55:46.049212 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5113 22:55:46.051858 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5114 22:55:46.051941
5115 22:55:46.055199 CA PerBit enable=1, Macro0, CA PI delay=33
5116 22:55:46.055282
5117 22:55:46.058785 [CBTSetCACLKResult] CA Dly = 33
5118 22:55:46.061975 CS Dly: 7 (0~39)
5119 22:55:46.062076
5120 22:55:46.065315 ----->DramcWriteLeveling(PI) begin...
5121 22:55:46.065398 ==
5122 22:55:46.068363 Dram Type= 6, Freq= 0, CH_0, rank 0
5123 22:55:46.071953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5124 22:55:46.072037 ==
5125 22:55:46.075301 Write leveling (Byte 0): 32 => 32
5126 22:55:46.078473 Write leveling (Byte 1): 32 => 32
5127 22:55:46.081797 DramcWriteLeveling(PI) end<-----
5128 22:55:46.081879
5129 22:55:46.081944 ==
5130 22:55:46.085008 Dram Type= 6, Freq= 0, CH_0, rank 0
5131 22:55:46.088380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5132 22:55:46.088463 ==
5133 22:55:46.092083 [Gating] SW mode calibration
5134 22:55:46.097871 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5135 22:55:46.104891 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5136 22:55:46.107942 0 14 0 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
5137 22:55:46.114451 0 14 4 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
5138 22:55:46.117756 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5139 22:55:46.121517 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5140 22:55:46.127820 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5141 22:55:46.131212 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5142 22:55:46.134519 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5143 22:55:46.140903 0 14 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5144 22:55:46.144281 0 15 0 | B1->B0 | 3131 2b2b | 1 1 | (1 1) (1 0)
5145 22:55:46.147478 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5146 22:55:46.154012 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5147 22:55:46.157504 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5148 22:55:46.160967 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5149 22:55:46.167289 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5150 22:55:46.170537 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5151 22:55:46.173773 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5152 22:55:46.180432 1 0 0 | B1->B0 | 2d2d 4141 | 1 0 | (0 0) (0 0)
5153 22:55:46.183786 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 22:55:46.187217 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 22:55:46.193333 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5156 22:55:46.196836 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5157 22:55:46.199977 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5158 22:55:46.206652 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5159 22:55:46.209728 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5160 22:55:46.213488 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5161 22:55:46.219777 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5162 22:55:46.223484 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 22:55:46.226323 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 22:55:46.233314 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 22:55:46.236304 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 22:55:46.239652 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 22:55:46.246515 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 22:55:46.249504 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 22:55:46.253004 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 22:55:46.259790 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 22:55:46.263065 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 22:55:46.266124 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 22:55:46.272717 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 22:55:46.275792 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 22:55:46.279743 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5176 22:55:46.285765 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5177 22:55:46.289452 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5178 22:55:46.292851 Total UI for P1: 0, mck2ui 16
5179 22:55:46.295997 best dqsien dly found for B0: ( 1, 2, 30)
5180 22:55:46.299258 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 22:55:46.302705 Total UI for P1: 0, mck2ui 16
5182 22:55:46.306079 best dqsien dly found for B1: ( 1, 3, 4)
5183 22:55:46.309341 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5184 22:55:46.312326 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5185 22:55:46.312410
5186 22:55:46.316011 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5187 22:55:46.322230 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5188 22:55:46.322314 [Gating] SW calibration Done
5189 22:55:46.322379 ==
5190 22:55:46.325474 Dram Type= 6, Freq= 0, CH_0, rank 0
5191 22:55:46.331899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5192 22:55:46.331994 ==
5193 22:55:46.332058 RX Vref Scan: 0
5194 22:55:46.332117
5195 22:55:46.335558 RX Vref 0 -> 0, step: 1
5196 22:55:46.335640
5197 22:55:46.338977 RX Delay -80 -> 252, step: 8
5198 22:55:46.342186 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5199 22:55:46.345455 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5200 22:55:46.348431 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5201 22:55:46.355128 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5202 22:55:46.358502 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5203 22:55:46.361765 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5204 22:55:46.364990 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5205 22:55:46.368169 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5206 22:55:46.371889 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5207 22:55:46.378343 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5208 22:55:46.381473 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5209 22:55:46.384659 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5210 22:55:46.388289 iDelay=208, Bit 12, Center 83 (-16 ~ 183) 200
5211 22:55:46.394778 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5212 22:55:46.398156 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5213 22:55:46.401841 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5214 22:55:46.401923 ==
5215 22:55:46.404746 Dram Type= 6, Freq= 0, CH_0, rank 0
5216 22:55:46.408224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5217 22:55:46.408307 ==
5218 22:55:46.411074 DQS Delay:
5219 22:55:46.411156 DQS0 = 0, DQS1 = 0
5220 22:55:46.414734 DQM Delay:
5221 22:55:46.414864 DQM0 = 95, DQM1 = 82
5222 22:55:46.414946 DQ Delay:
5223 22:55:46.417642 DQ0 =95, DQ1 =95, DQ2 =91, DQ3 =91
5224 22:55:46.421188 DQ4 =99, DQ5 =79, DQ6 =103, DQ7 =107
5225 22:55:46.424543 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5226 22:55:46.427780 DQ12 =83, DQ13 =87, DQ14 =91, DQ15 =91
5227 22:55:46.427862
5228 22:55:46.427927
5229 22:55:46.430961 ==
5230 22:55:46.431049 Dram Type= 6, Freq= 0, CH_0, rank 0
5231 22:55:46.437742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5232 22:55:46.437828 ==
5233 22:55:46.437893
5234 22:55:46.437953
5235 22:55:46.441080 TX Vref Scan disable
5236 22:55:46.441162 == TX Byte 0 ==
5237 22:55:46.444114 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5238 22:55:46.451142 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5239 22:55:46.451226 == TX Byte 1 ==
5240 22:55:46.454289 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5241 22:55:46.460790 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5242 22:55:46.460875 ==
5243 22:55:46.463955 Dram Type= 6, Freq= 0, CH_0, rank 0
5244 22:55:46.467158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5245 22:55:46.467241 ==
5246 22:55:46.467306
5247 22:55:46.467367
5248 22:55:46.470605 TX Vref Scan disable
5249 22:55:46.473805 == TX Byte 0 ==
5250 22:55:46.477153 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5251 22:55:46.480782 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5252 22:55:46.484003 == TX Byte 1 ==
5253 22:55:46.486883 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5254 22:55:46.490771 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5255 22:55:46.490860
5256 22:55:46.493845 [DATLAT]
5257 22:55:46.493927 Freq=933, CH0 RK0
5258 22:55:46.493993
5259 22:55:46.497152 DATLAT Default: 0xd
5260 22:55:46.497235 0, 0xFFFF, sum = 0
5261 22:55:46.500470 1, 0xFFFF, sum = 0
5262 22:55:46.500553 2, 0xFFFF, sum = 0
5263 22:55:46.503848 3, 0xFFFF, sum = 0
5264 22:55:46.503931 4, 0xFFFF, sum = 0
5265 22:55:46.507086 5, 0xFFFF, sum = 0
5266 22:55:46.507170 6, 0xFFFF, sum = 0
5267 22:55:46.510272 7, 0xFFFF, sum = 0
5268 22:55:46.510356 8, 0xFFFF, sum = 0
5269 22:55:46.513520 9, 0xFFFF, sum = 0
5270 22:55:46.513604 10, 0x0, sum = 1
5271 22:55:46.516886 11, 0x0, sum = 2
5272 22:55:46.516970 12, 0x0, sum = 3
5273 22:55:46.520168 13, 0x0, sum = 4
5274 22:55:46.520252 best_step = 11
5275 22:55:46.520317
5276 22:55:46.520376 ==
5277 22:55:46.523861 Dram Type= 6, Freq= 0, CH_0, rank 0
5278 22:55:46.529921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5279 22:55:46.530009 ==
5280 22:55:46.530075 RX Vref Scan: 1
5281 22:55:46.530136
5282 22:55:46.533164 RX Vref 0 -> 0, step: 1
5283 22:55:46.533247
5284 22:55:46.536823 RX Delay -69 -> 252, step: 4
5285 22:55:46.536908
5286 22:55:46.539943 Set Vref, RX VrefLevel [Byte0]: 62
5287 22:55:46.543101 [Byte1]: 52
5288 22:55:46.543183
5289 22:55:46.546619 Final RX Vref Byte 0 = 62 to rank0
5290 22:55:46.549810 Final RX Vref Byte 1 = 52 to rank0
5291 22:55:46.552857 Final RX Vref Byte 0 = 62 to rank1
5292 22:55:46.556512 Final RX Vref Byte 1 = 52 to rank1==
5293 22:55:46.559750 Dram Type= 6, Freq= 0, CH_0, rank 0
5294 22:55:46.562799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5295 22:55:46.562921 ==
5296 22:55:46.565949 DQS Delay:
5297 22:55:46.566029 DQS0 = 0, DQS1 = 0
5298 22:55:46.569625 DQM Delay:
5299 22:55:46.569706 DQM0 = 95, DQM1 = 83
5300 22:55:46.569770 DQ Delay:
5301 22:55:46.572902 DQ0 =94, DQ1 =98, DQ2 =94, DQ3 =92
5302 22:55:46.576221 DQ4 =94, DQ5 =84, DQ6 =102, DQ7 =106
5303 22:55:46.579322 DQ8 =76, DQ9 =68, DQ10 =84, DQ11 =76
5304 22:55:46.582757 DQ12 =86, DQ13 =88, DQ14 =96, DQ15 =90
5305 22:55:46.582845
5306 22:55:46.585806
5307 22:55:46.592403 [DQSOSCAuto] RK0, (LSB)MR18= 0x1616, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 414 ps
5308 22:55:46.595647 CH0 RK0: MR19=505, MR18=1616
5309 22:55:46.602422 CH0_RK0: MR19=0x505, MR18=0x1616, DQSOSC=414, MR23=63, INC=63, DEC=42
5310 22:55:46.602504
5311 22:55:46.605600 ----->DramcWriteLeveling(PI) begin...
5312 22:55:46.605682 ==
5313 22:55:46.608942 Dram Type= 6, Freq= 0, CH_0, rank 1
5314 22:55:46.612247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5315 22:55:46.612329 ==
5316 22:55:46.615988 Write leveling (Byte 0): 31 => 31
5317 22:55:46.619041 Write leveling (Byte 1): 29 => 29
5318 22:55:46.622386 DramcWriteLeveling(PI) end<-----
5319 22:55:46.622470
5320 22:55:46.622534 ==
5321 22:55:46.625515 Dram Type= 6, Freq= 0, CH_0, rank 1
5322 22:55:46.628694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5323 22:55:46.628812 ==
5324 22:55:46.631798 [Gating] SW mode calibration
5325 22:55:46.638533 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5326 22:55:46.645032 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5327 22:55:46.648310 0 14 0 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
5328 22:55:46.655015 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5329 22:55:46.658459 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5330 22:55:46.661669 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5331 22:55:46.668352 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5332 22:55:46.671882 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5333 22:55:46.674779 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5334 22:55:46.681355 0 14 28 | B1->B0 | 3131 2d2d | 1 0 | (1 0) (1 1)
5335 22:55:46.684589 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
5336 22:55:46.688091 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5337 22:55:46.694507 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5338 22:55:46.697863 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5339 22:55:46.700820 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5340 22:55:46.708466 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5341 22:55:46.710759 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5342 22:55:46.714135 0 15 28 | B1->B0 | 2828 3535 | 1 0 | (0 0) (0 0)
5343 22:55:46.720752 1 0 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5344 22:55:46.723834 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5345 22:55:46.727703 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 22:55:46.733955 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5347 22:55:46.737035 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5348 22:55:46.740504 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 22:55:46.747190 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5350 22:55:46.750341 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5351 22:55:46.753573 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5352 22:55:46.760244 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 22:55:46.763149 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 22:55:46.766887 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 22:55:46.773280 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 22:55:46.776389 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 22:55:46.779913 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 22:55:46.786160 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 22:55:46.789364 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 22:55:46.792912 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 22:55:46.799403 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 22:55:46.802691 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 22:55:46.805837 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 22:55:46.812374 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 22:55:46.815896 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 22:55:46.819024 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5367 22:55:46.825700 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 22:55:46.829230 Total UI for P1: 0, mck2ui 16
5369 22:55:46.832648 best dqsien dly found for B0: ( 1, 2, 28)
5370 22:55:46.835834 Total UI for P1: 0, mck2ui 16
5371 22:55:46.838615 best dqsien dly found for B1: ( 1, 2, 30)
5372 22:55:46.842079 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5373 22:55:46.845375 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5374 22:55:46.845458
5375 22:55:46.848646 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5376 22:55:46.852048 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5377 22:55:46.855791 [Gating] SW calibration Done
5378 22:55:46.855873 ==
5379 22:55:46.858663 Dram Type= 6, Freq= 0, CH_0, rank 1
5380 22:55:46.862478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5381 22:55:46.862561 ==
5382 22:55:46.865805 RX Vref Scan: 0
5383 22:55:46.865888
5384 22:55:46.868720 RX Vref 0 -> 0, step: 1
5385 22:55:46.868802
5386 22:55:46.868867 RX Delay -80 -> 252, step: 8
5387 22:55:46.875269 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5388 22:55:46.878997 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5389 22:55:46.882444 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5390 22:55:46.885494 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5391 22:55:46.888708 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5392 22:55:46.895214 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5393 22:55:46.898238 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5394 22:55:46.901490 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5395 22:55:46.904934 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5396 22:55:46.908368 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5397 22:55:46.914981 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5398 22:55:46.918057 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5399 22:55:46.921590 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5400 22:55:46.924430 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5401 22:55:46.928167 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5402 22:55:46.934720 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5403 22:55:46.934804 ==
5404 22:55:46.937926 Dram Type= 6, Freq= 0, CH_0, rank 1
5405 22:55:46.941194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5406 22:55:46.941277 ==
5407 22:55:46.941342 DQS Delay:
5408 22:55:46.944410 DQS0 = 0, DQS1 = 0
5409 22:55:46.944492 DQM Delay:
5410 22:55:46.947836 DQM0 = 91, DQM1 = 83
5411 22:55:46.947918 DQ Delay:
5412 22:55:46.950938 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5413 22:55:46.954537 DQ4 =91, DQ5 =79, DQ6 =103, DQ7 =103
5414 22:55:46.957555 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5415 22:55:46.960965 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =87
5416 22:55:46.961048
5417 22:55:46.961112
5418 22:55:46.961171 ==
5419 22:55:46.964051 Dram Type= 6, Freq= 0, CH_0, rank 1
5420 22:55:46.967531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5421 22:55:46.970695 ==
5422 22:55:46.970777
5423 22:55:46.970865
5424 22:55:46.970941 TX Vref Scan disable
5425 22:55:46.974221 == TX Byte 0 ==
5426 22:55:46.977169 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5427 22:55:46.981276 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5428 22:55:46.984088 == TX Byte 1 ==
5429 22:55:46.987185 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5430 22:55:46.990955 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5431 22:55:46.993866 ==
5432 22:55:46.997231 Dram Type= 6, Freq= 0, CH_0, rank 1
5433 22:55:47.000469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5434 22:55:47.000551 ==
5435 22:55:47.000617
5436 22:55:47.000677
5437 22:55:47.003732 TX Vref Scan disable
5438 22:55:47.003814 == TX Byte 0 ==
5439 22:55:47.010219 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5440 22:55:47.013688 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5441 22:55:47.013771 == TX Byte 1 ==
5442 22:55:47.020308 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5443 22:55:47.023840 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5444 22:55:47.023923
5445 22:55:47.023988 [DATLAT]
5446 22:55:47.027050 Freq=933, CH0 RK1
5447 22:55:47.027132
5448 22:55:47.027196 DATLAT Default: 0xb
5449 22:55:47.030174 0, 0xFFFF, sum = 0
5450 22:55:47.030257 1, 0xFFFF, sum = 0
5451 22:55:47.033443 2, 0xFFFF, sum = 0
5452 22:55:47.033526 3, 0xFFFF, sum = 0
5453 22:55:47.036789 4, 0xFFFF, sum = 0
5454 22:55:47.040259 5, 0xFFFF, sum = 0
5455 22:55:47.040343 6, 0xFFFF, sum = 0
5456 22:55:47.043461 7, 0xFFFF, sum = 0
5457 22:55:47.043545 8, 0xFFFF, sum = 0
5458 22:55:47.046781 9, 0xFFFF, sum = 0
5459 22:55:47.046904 10, 0x0, sum = 1
5460 22:55:47.050136 11, 0x0, sum = 2
5461 22:55:47.050220 12, 0x0, sum = 3
5462 22:55:47.053293 13, 0x0, sum = 4
5463 22:55:47.053376 best_step = 11
5464 22:55:47.053442
5465 22:55:47.053505 ==
5466 22:55:47.056561 Dram Type= 6, Freq= 0, CH_0, rank 1
5467 22:55:47.059914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5468 22:55:47.059997 ==
5469 22:55:47.062960 RX Vref Scan: 0
5470 22:55:47.063041
5471 22:55:47.066638 RX Vref 0 -> 0, step: 1
5472 22:55:47.066720
5473 22:55:47.066785 RX Delay -69 -> 252, step: 4
5474 22:55:47.074156 iDelay=199, Bit 0, Center 92 (-1 ~ 186) 188
5475 22:55:47.077922 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5476 22:55:47.080799 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5477 22:55:47.083791 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5478 22:55:47.087347 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5479 22:55:47.093823 iDelay=199, Bit 5, Center 82 (-9 ~ 174) 184
5480 22:55:47.097360 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5481 22:55:47.100729 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5482 22:55:47.103686 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5483 22:55:47.106775 iDelay=199, Bit 9, Center 70 (-17 ~ 158) 176
5484 22:55:47.113818 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5485 22:55:47.116713 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5486 22:55:47.119976 iDelay=199, Bit 12, Center 90 (-5 ~ 186) 192
5487 22:55:47.123174 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5488 22:55:47.126462 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5489 22:55:47.133299 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5490 22:55:47.133386 ==
5491 22:55:47.136606 Dram Type= 6, Freq= 0, CH_0, rank 1
5492 22:55:47.140154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5493 22:55:47.140238 ==
5494 22:55:47.140304 DQS Delay:
5495 22:55:47.143280 DQS0 = 0, DQS1 = 0
5496 22:55:47.143362 DQM Delay:
5497 22:55:47.146389 DQM0 = 93, DQM1 = 84
5498 22:55:47.146471 DQ Delay:
5499 22:55:47.150006 DQ0 =92, DQ1 =94, DQ2 =90, DQ3 =88
5500 22:55:47.152992 DQ4 =92, DQ5 =82, DQ6 =104, DQ7 =102
5501 22:55:47.156222 DQ8 =78, DQ9 =70, DQ10 =86, DQ11 =76
5502 22:55:47.159266 DQ12 =90, DQ13 =90, DQ14 =94, DQ15 =92
5503 22:55:47.159348
5504 22:55:47.159413
5505 22:55:47.169624 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e0f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 407 ps
5506 22:55:47.169709 CH0 RK1: MR19=505, MR18=2E0F
5507 22:55:47.176269 CH0_RK1: MR19=0x505, MR18=0x2E0F, DQSOSC=407, MR23=63, INC=65, DEC=43
5508 22:55:47.179738 [RxdqsGatingPostProcess] freq 933
5509 22:55:47.186397 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5510 22:55:47.189280 best DQS0 dly(2T, 0.5T) = (0, 10)
5511 22:55:47.192469 best DQS1 dly(2T, 0.5T) = (0, 11)
5512 22:55:47.195618 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5513 22:55:47.199233 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5514 22:55:47.202661 best DQS0 dly(2T, 0.5T) = (0, 10)
5515 22:55:47.205766 best DQS1 dly(2T, 0.5T) = (0, 10)
5516 22:55:47.208926 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5517 22:55:47.212133 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5518 22:55:47.212215 Pre-setting of DQS Precalculation
5519 22:55:47.218756 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5520 22:55:47.218870 ==
5521 22:55:47.222420 Dram Type= 6, Freq= 0, CH_1, rank 0
5522 22:55:47.225665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5523 22:55:47.225751 ==
5524 22:55:47.232332 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5525 22:55:47.238640 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5526 22:55:47.242011 [CA 0] Center 37 (7~68) winsize 62
5527 22:55:47.245722 [CA 1] Center 37 (7~68) winsize 62
5528 22:55:47.248759 [CA 2] Center 34 (5~64) winsize 60
5529 22:55:47.251692 [CA 3] Center 34 (4~64) winsize 61
5530 22:55:47.255202 [CA 4] Center 34 (5~64) winsize 60
5531 22:55:47.258465 [CA 5] Center 33 (4~63) winsize 60
5532 22:55:47.258628
5533 22:55:47.262459 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5534 22:55:47.262626
5535 22:55:47.265555 [CATrainingPosCal] consider 1 rank data
5536 22:55:47.268649 u2DelayCellTimex100 = 270/100 ps
5537 22:55:47.271522 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5538 22:55:47.275277 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5539 22:55:47.278395 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5540 22:55:47.281962 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5541 22:55:47.284737 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5542 22:55:47.291426 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5543 22:55:47.291613
5544 22:55:47.294672 CA PerBit enable=1, Macro0, CA PI delay=33
5545 22:55:47.294864
5546 22:55:47.297889 [CBTSetCACLKResult] CA Dly = 33
5547 22:55:47.298048 CS Dly: 5 (0~36)
5548 22:55:47.298156 ==
5549 22:55:47.301387 Dram Type= 6, Freq= 0, CH_1, rank 1
5550 22:55:47.307998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5551 22:55:47.308175 ==
5552 22:55:47.311241 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5553 22:55:47.318061 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5554 22:55:47.320954 [CA 0] Center 37 (7~68) winsize 62
5555 22:55:47.324091 [CA 1] Center 37 (7~68) winsize 62
5556 22:55:47.327331 [CA 2] Center 35 (5~65) winsize 61
5557 22:55:47.330619 [CA 3] Center 34 (4~64) winsize 61
5558 22:55:47.333869 [CA 4] Center 35 (5~65) winsize 61
5559 22:55:47.337178 [CA 5] Center 33 (3~64) winsize 62
5560 22:55:47.337287
5561 22:55:47.340918 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5562 22:55:47.341105
5563 22:55:47.344305 [CATrainingPosCal] consider 2 rank data
5564 22:55:47.347758 u2DelayCellTimex100 = 270/100 ps
5565 22:55:47.350627 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5566 22:55:47.353748 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5567 22:55:47.360731 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5568 22:55:47.363961 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5569 22:55:47.366868 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5570 22:55:47.370453 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5571 22:55:47.370574
5572 22:55:47.373677 CA PerBit enable=1, Macro0, CA PI delay=33
5573 22:55:47.373803
5574 22:55:47.376987 [CBTSetCACLKResult] CA Dly = 33
5575 22:55:47.377103 CS Dly: 6 (0~38)
5576 22:55:47.380293
5577 22:55:47.383724 ----->DramcWriteLeveling(PI) begin...
5578 22:55:47.383829 ==
5579 22:55:47.387116 Dram Type= 6, Freq= 0, CH_1, rank 0
5580 22:55:47.390438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5581 22:55:47.390528 ==
5582 22:55:47.393551 Write leveling (Byte 0): 23 => 23
5583 22:55:47.397079 Write leveling (Byte 1): 29 => 29
5584 22:55:47.399932 DramcWriteLeveling(PI) end<-----
5585 22:55:47.400023
5586 22:55:47.400090 ==
5587 22:55:47.403600 Dram Type= 6, Freq= 0, CH_1, rank 0
5588 22:55:47.406399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5589 22:55:47.406523 ==
5590 22:55:47.409972 [Gating] SW mode calibration
5591 22:55:47.416782 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5592 22:55:47.423465 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5593 22:55:47.426757 0 14 0 | B1->B0 | 3333 3232 | 1 1 | (0 0) (0 0)
5594 22:55:47.429950 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5595 22:55:47.436894 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 22:55:47.440376 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5597 22:55:47.443146 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5598 22:55:47.449483 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5599 22:55:47.453168 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5600 22:55:47.456316 0 14 28 | B1->B0 | 2d2d 2f2f | 0 1 | (1 0) (1 0)
5601 22:55:47.462766 0 15 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
5602 22:55:47.466141 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 22:55:47.469413 0 15 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5604 22:55:47.476360 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5605 22:55:47.479275 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5606 22:55:47.483015 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5607 22:55:47.488930 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5608 22:55:47.492274 0 15 28 | B1->B0 | 2b2b 2d2d | 1 0 | (0 0) (0 0)
5609 22:55:47.496107 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 22:55:47.502706 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 22:55:47.506205 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 22:55:47.508861 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 22:55:47.515495 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 22:55:47.518621 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 22:55:47.522501 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 22:55:47.529087 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5617 22:55:47.532421 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 22:55:47.535395 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 22:55:47.542042 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 22:55:47.545149 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 22:55:47.548969 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 22:55:47.555142 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 22:55:47.559131 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 22:55:47.561795 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 22:55:47.568324 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 22:55:47.572055 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 22:55:47.574781 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 22:55:47.581349 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 22:55:47.584897 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 22:55:47.588098 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 22:55:47.594789 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 22:55:47.598021 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5633 22:55:47.601120 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5634 22:55:47.604289 Total UI for P1: 0, mck2ui 16
5635 22:55:47.607696 best dqsien dly found for B0: ( 1, 2, 28)
5636 22:55:47.614299 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5637 22:55:47.614385 Total UI for P1: 0, mck2ui 16
5638 22:55:47.620913 best dqsien dly found for B1: ( 1, 2, 30)
5639 22:55:47.624304 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5640 22:55:47.627576 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5641 22:55:47.627710
5642 22:55:47.630728 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5643 22:55:47.634230 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5644 22:55:47.637720 [Gating] SW calibration Done
5645 22:55:47.637810 ==
5646 22:55:47.640663 Dram Type= 6, Freq= 0, CH_1, rank 0
5647 22:55:47.644367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5648 22:55:47.644450 ==
5649 22:55:47.647580 RX Vref Scan: 0
5650 22:55:47.647662
5651 22:55:47.647728 RX Vref 0 -> 0, step: 1
5652 22:55:47.647791
5653 22:55:47.651164 RX Delay -80 -> 252, step: 8
5654 22:55:47.654405 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5655 22:55:47.660609 iDelay=208, Bit 1, Center 87 (-16 ~ 191) 208
5656 22:55:47.663953 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5657 22:55:47.667547 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5658 22:55:47.670435 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5659 22:55:47.673766 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5660 22:55:47.680391 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5661 22:55:47.683843 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5662 22:55:47.686998 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5663 22:55:47.690353 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5664 22:55:47.693639 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5665 22:55:47.700516 iDelay=208, Bit 11, Center 79 (-24 ~ 183) 208
5666 22:55:47.703712 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5667 22:55:47.706810 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5668 22:55:47.710244 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5669 22:55:47.713284 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5670 22:55:47.713369 ==
5671 22:55:47.716591 Dram Type= 6, Freq= 0, CH_1, rank 0
5672 22:55:47.724035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5673 22:55:47.724398 ==
5674 22:55:47.724687 DQS Delay:
5675 22:55:47.726906 DQS0 = 0, DQS1 = 0
5676 22:55:47.727286 DQM Delay:
5677 22:55:47.730660 DQM0 = 94, DQM1 = 86
5678 22:55:47.731213 DQ Delay:
5679 22:55:47.733363 DQ0 =99, DQ1 =87, DQ2 =83, DQ3 =91
5680 22:55:47.736932 DQ4 =91, DQ5 =103, DQ6 =107, DQ7 =91
5681 22:55:47.740364 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =79
5682 22:55:47.743421 DQ12 =91, DQ13 =95, DQ14 =91, DQ15 =91
5683 22:55:47.743821
5684 22:55:47.744216
5685 22:55:47.744594 ==
5686 22:55:47.746921 Dram Type= 6, Freq= 0, CH_1, rank 0
5687 22:55:47.750004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5688 22:55:47.750550 ==
5689 22:55:47.751008
5690 22:55:47.751310
5691 22:55:47.753276 TX Vref Scan disable
5692 22:55:47.756719 == TX Byte 0 ==
5693 22:55:47.760186 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5694 22:55:47.762910 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5695 22:55:47.766590 == TX Byte 1 ==
5696 22:55:47.769793 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5697 22:55:47.773070 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5698 22:55:47.773461 ==
5699 22:55:47.776554 Dram Type= 6, Freq= 0, CH_1, rank 0
5700 22:55:47.782803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5701 22:55:47.783252 ==
5702 22:55:47.783591
5703 22:55:47.783885
5704 22:55:47.784214 TX Vref Scan disable
5705 22:55:47.787189 == TX Byte 0 ==
5706 22:55:47.790407 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5707 22:55:47.797332 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5708 22:55:47.797731 == TX Byte 1 ==
5709 22:55:47.800639 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5710 22:55:47.806553 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5711 22:55:47.806987
5712 22:55:47.807305 [DATLAT]
5713 22:55:47.807599 Freq=933, CH1 RK0
5714 22:55:47.807883
5715 22:55:47.810172 DATLAT Default: 0xd
5716 22:55:47.813631 0, 0xFFFF, sum = 0
5717 22:55:47.814257 1, 0xFFFF, sum = 0
5718 22:55:47.816909 2, 0xFFFF, sum = 0
5719 22:55:47.817337 3, 0xFFFF, sum = 0
5720 22:55:47.819624 4, 0xFFFF, sum = 0
5721 22:55:47.820050 5, 0xFFFF, sum = 0
5722 22:55:47.822991 6, 0xFFFF, sum = 0
5723 22:55:47.823392 7, 0xFFFF, sum = 0
5724 22:55:47.826538 8, 0xFFFF, sum = 0
5725 22:55:47.827120 9, 0xFFFF, sum = 0
5726 22:55:47.830250 10, 0x0, sum = 1
5727 22:55:47.830648 11, 0x0, sum = 2
5728 22:55:47.833331 12, 0x0, sum = 3
5729 22:55:47.833728 13, 0x0, sum = 4
5730 22:55:47.836407 best_step = 11
5731 22:55:47.836806
5732 22:55:47.837142 ==
5733 22:55:47.840131 Dram Type= 6, Freq= 0, CH_1, rank 0
5734 22:55:47.843181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5735 22:55:47.843583 ==
5736 22:55:47.843918 RX Vref Scan: 1
5737 22:55:47.846260
5738 22:55:47.846650 RX Vref 0 -> 0, step: 1
5739 22:55:47.847016
5740 22:55:47.849305 RX Delay -69 -> 252, step: 4
5741 22:55:47.849830
5742 22:55:47.853116 Set Vref, RX VrefLevel [Byte0]: 56
5743 22:55:47.855889 [Byte1]: 55
5744 22:55:47.859701
5745 22:55:47.860095 Final RX Vref Byte 0 = 56 to rank0
5746 22:55:47.862939 Final RX Vref Byte 1 = 55 to rank0
5747 22:55:47.866099 Final RX Vref Byte 0 = 56 to rank1
5748 22:55:47.869407 Final RX Vref Byte 1 = 55 to rank1==
5749 22:55:47.873032 Dram Type= 6, Freq= 0, CH_1, rank 0
5750 22:55:47.879208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5751 22:55:47.879607 ==
5752 22:55:47.879920 DQS Delay:
5753 22:55:47.882679 DQS0 = 0, DQS1 = 0
5754 22:55:47.883128 DQM Delay:
5755 22:55:47.883445 DQM0 = 96, DQM1 = 88
5756 22:55:47.885965 DQ Delay:
5757 22:55:47.889259 DQ0 =102, DQ1 =92, DQ2 =84, DQ3 =92
5758 22:55:47.892433 DQ4 =94, DQ5 =106, DQ6 =108, DQ7 =92
5759 22:55:47.895798 DQ8 =78, DQ9 =80, DQ10 =86, DQ11 =82
5760 22:55:47.898757 DQ12 =96, DQ13 =94, DQ14 =94, DQ15 =94
5761 22:55:47.899203
5762 22:55:47.899517
5763 22:55:47.905730 [DQSOSCAuto] RK0, (LSB)MR18= 0x50d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 420 ps
5764 22:55:47.909094 CH1 RK0: MR19=505, MR18=50D
5765 22:55:47.915480 CH1_RK0: MR19=0x505, MR18=0x50D, DQSOSC=417, MR23=63, INC=62, DEC=41
5766 22:55:47.915877
5767 22:55:47.918921 ----->DramcWriteLeveling(PI) begin...
5768 22:55:47.919320 ==
5769 22:55:47.922304 Dram Type= 6, Freq= 0, CH_1, rank 1
5770 22:55:47.925200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5771 22:55:47.925598 ==
5772 22:55:47.928505 Write leveling (Byte 0): 27 => 27
5773 22:55:47.931780 Write leveling (Byte 1): 29 => 29
5774 22:55:47.935339 DramcWriteLeveling(PI) end<-----
5775 22:55:47.935786
5776 22:55:47.936147 ==
5777 22:55:47.938618 Dram Type= 6, Freq= 0, CH_1, rank 1
5778 22:55:47.944981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5779 22:55:47.945559 ==
5780 22:55:47.946044 [Gating] SW mode calibration
5781 22:55:47.955165 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5782 22:55:47.958403 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5783 22:55:47.961475 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5784 22:55:47.968423 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5785 22:55:47.971319 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5786 22:55:47.975019 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5787 22:55:47.981551 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5788 22:55:47.984441 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5789 22:55:47.987707 0 14 24 | B1->B0 | 3232 2e2e | 1 1 | (1 1) (1 0)
5790 22:55:47.994501 0 14 28 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (1 0)
5791 22:55:47.997786 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5792 22:55:48.004340 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5793 22:55:48.007700 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5794 22:55:48.010957 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5795 22:55:48.017615 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5796 22:55:48.020891 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5797 22:55:48.024264 0 15 24 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)
5798 22:55:48.030518 0 15 28 | B1->B0 | 3535 4444 | 0 0 | (0 0) (0 0)
5799 22:55:48.034199 1 0 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5800 22:55:48.037067 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5801 22:55:48.043932 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 22:55:48.047312 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 22:55:48.050467 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 22:55:48.057038 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5805 22:55:48.060158 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5806 22:55:48.063385 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5807 22:55:48.069998 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 22:55:48.073864 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 22:55:48.076959 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 22:55:48.083516 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 22:55:48.086880 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 22:55:48.090242 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 22:55:48.096800 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 22:55:48.099919 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 22:55:48.103463 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 22:55:48.109517 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 22:55:48.112983 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 22:55:48.116625 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 22:55:48.122822 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 22:55:48.126187 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 22:55:48.129395 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5822 22:55:48.136198 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 22:55:48.136634 Total UI for P1: 0, mck2ui 16
5824 22:55:48.139389 best dqsien dly found for B0: ( 1, 2, 24)
5825 22:55:48.142710 Total UI for P1: 0, mck2ui 16
5826 22:55:48.146249 best dqsien dly found for B1: ( 1, 2, 24)
5827 22:55:48.149481 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5828 22:55:48.156094 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5829 22:55:48.156645
5830 22:55:48.159673 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5831 22:55:48.162601 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5832 22:55:48.165783 [Gating] SW calibration Done
5833 22:55:48.166212 ==
5834 22:55:48.168979 Dram Type= 6, Freq= 0, CH_1, rank 1
5835 22:55:48.172562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5836 22:55:48.172994 ==
5837 22:55:48.175814 RX Vref Scan: 0
5838 22:55:48.176241
5839 22:55:48.176618 RX Vref 0 -> 0, step: 1
5840 22:55:48.176942
5841 22:55:48.178726 RX Delay -80 -> 252, step: 8
5842 22:55:48.182416 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5843 22:55:48.188592 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5844 22:55:48.192540 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5845 22:55:48.195320 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5846 22:55:48.198910 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5847 22:55:48.202343 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5848 22:55:48.205696 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5849 22:55:48.212192 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5850 22:55:48.215311 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5851 22:55:48.218773 iDelay=208, Bit 9, Center 79 (-24 ~ 183) 208
5852 22:55:48.222240 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5853 22:55:48.225868 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5854 22:55:48.232359 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5855 22:55:48.234815 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5856 22:55:48.238370 iDelay=208, Bit 14, Center 95 (-8 ~ 199) 208
5857 22:55:48.241667 iDelay=208, Bit 15, Center 95 (-8 ~ 199) 208
5858 22:55:48.242096 ==
5859 22:55:48.244936 Dram Type= 6, Freq= 0, CH_1, rank 1
5860 22:55:48.251943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5861 22:55:48.252387 ==
5862 22:55:48.252726 DQS Delay:
5863 22:55:48.253045 DQS0 = 0, DQS1 = 0
5864 22:55:48.255393 DQM Delay:
5865 22:55:48.255843 DQM0 = 93, DQM1 = 89
5866 22:55:48.258443 DQ Delay:
5867 22:55:48.261851 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =91
5868 22:55:48.264686 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5869 22:55:48.268038 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5870 22:55:48.271299 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =95
5871 22:55:48.271728
5872 22:55:48.272070
5873 22:55:48.272383 ==
5874 22:55:48.274579 Dram Type= 6, Freq= 0, CH_1, rank 1
5875 22:55:48.278471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5876 22:55:48.279048 ==
5877 22:55:48.279407
5878 22:55:48.279728
5879 22:55:48.281148 TX Vref Scan disable
5880 22:55:48.284944 == TX Byte 0 ==
5881 22:55:48.288096 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5882 22:55:48.290993 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5883 22:55:48.294676 == TX Byte 1 ==
5884 22:55:48.298033 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5885 22:55:48.300892 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5886 22:55:48.301333 ==
5887 22:55:48.304180 Dram Type= 6, Freq= 0, CH_1, rank 1
5888 22:55:48.307534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5889 22:55:48.310870 ==
5890 22:55:48.311295
5891 22:55:48.311631
5892 22:55:48.311947 TX Vref Scan disable
5893 22:55:48.314311 == TX Byte 0 ==
5894 22:55:48.317667 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5895 22:55:48.324316 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5896 22:55:48.324773 == TX Byte 1 ==
5897 22:55:48.327319 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5898 22:55:48.333972 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5899 22:55:48.334400
5900 22:55:48.334764 [DATLAT]
5901 22:55:48.335400 Freq=933, CH1 RK1
5902 22:55:48.335763
5903 22:55:48.337388 DATLAT Default: 0xb
5904 22:55:48.337848 0, 0xFFFF, sum = 0
5905 22:55:48.340791 1, 0xFFFF, sum = 0
5906 22:55:48.344178 2, 0xFFFF, sum = 0
5907 22:55:48.344610 3, 0xFFFF, sum = 0
5908 22:55:48.347421 4, 0xFFFF, sum = 0
5909 22:55:48.347855 5, 0xFFFF, sum = 0
5910 22:55:48.350848 6, 0xFFFF, sum = 0
5911 22:55:48.351289 7, 0xFFFF, sum = 0
5912 22:55:48.354116 8, 0xFFFF, sum = 0
5913 22:55:48.354550 9, 0xFFFF, sum = 0
5914 22:55:48.356985 10, 0x0, sum = 1
5915 22:55:48.357422 11, 0x0, sum = 2
5916 22:55:48.360673 12, 0x0, sum = 3
5917 22:55:48.361206 13, 0x0, sum = 4
5918 22:55:48.364289 best_step = 11
5919 22:55:48.364810
5920 22:55:48.365149 ==
5921 22:55:48.367501 Dram Type= 6, Freq= 0, CH_1, rank 1
5922 22:55:48.370431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5923 22:55:48.370882 ==
5924 22:55:48.371229 RX Vref Scan: 0
5925 22:55:48.371553
5926 22:55:48.373721 RX Vref 0 -> 0, step: 1
5927 22:55:48.374148
5928 22:55:48.377189 RX Delay -69 -> 252, step: 4
5929 22:55:48.383576 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5930 22:55:48.387085 iDelay=203, Bit 1, Center 88 (-5 ~ 182) 188
5931 22:55:48.390162 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5932 22:55:48.393509 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5933 22:55:48.396925 iDelay=203, Bit 4, Center 92 (-5 ~ 190) 196
5934 22:55:48.403193 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5935 22:55:48.406627 iDelay=203, Bit 6, Center 102 (3 ~ 202) 200
5936 22:55:48.410123 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5937 22:55:48.413222 iDelay=203, Bit 8, Center 80 (-13 ~ 174) 188
5938 22:55:48.416568 iDelay=203, Bit 9, Center 84 (-5 ~ 174) 180
5939 22:55:48.420308 iDelay=203, Bit 10, Center 94 (-1 ~ 190) 192
5940 22:55:48.426226 iDelay=203, Bit 11, Center 86 (-5 ~ 178) 184
5941 22:55:48.429973 iDelay=203, Bit 12, Center 98 (3 ~ 194) 192
5942 22:55:48.432814 iDelay=203, Bit 13, Center 98 (3 ~ 194) 192
5943 22:55:48.436361 iDelay=203, Bit 14, Center 94 (-1 ~ 190) 192
5944 22:55:48.439607 iDelay=203, Bit 15, Center 96 (-1 ~ 194) 196
5945 22:55:48.443119 ==
5946 22:55:48.443547 Dram Type= 6, Freq= 0, CH_1, rank 1
5947 22:55:48.449330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5948 22:55:48.449779 ==
5949 22:55:48.450171 DQS Delay:
5950 22:55:48.452945 DQS0 = 0, DQS1 = 0
5951 22:55:48.453372 DQM Delay:
5952 22:55:48.456585 DQM0 = 92, DQM1 = 91
5953 22:55:48.457011 DQ Delay:
5954 22:55:48.459198 DQ0 =96, DQ1 =88, DQ2 =82, DQ3 =88
5955 22:55:48.462740 DQ4 =92, DQ5 =102, DQ6 =102, DQ7 =88
5956 22:55:48.466306 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =86
5957 22:55:48.469188 DQ12 =98, DQ13 =98, DQ14 =94, DQ15 =96
5958 22:55:48.469613
5959 22:55:48.469953
5960 22:55:48.475978 [DQSOSCAuto] RK1, (LSB)MR18= 0xd21, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 417 ps
5961 22:55:48.479654 CH1 RK1: MR19=505, MR18=D21
5962 22:55:48.485617 CH1_RK1: MR19=0x505, MR18=0xD21, DQSOSC=411, MR23=63, INC=64, DEC=42
5963 22:55:48.489024 [RxdqsGatingPostProcess] freq 933
5964 22:55:48.495822 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5965 22:55:48.498934 best DQS0 dly(2T, 0.5T) = (0, 10)
5966 22:55:48.499366 best DQS1 dly(2T, 0.5T) = (0, 10)
5967 22:55:48.502316 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5968 22:55:48.505664 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5969 22:55:48.508851 best DQS0 dly(2T, 0.5T) = (0, 10)
5970 22:55:48.512157 best DQS1 dly(2T, 0.5T) = (0, 10)
5971 22:55:48.515495 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5972 22:55:48.518856 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5973 22:55:48.521952 Pre-setting of DQS Precalculation
5974 22:55:48.528733 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5975 22:55:48.535208 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5976 22:55:48.541732 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5977 22:55:48.542163
5978 22:55:48.542504
5979 22:55:48.545291 [Calibration Summary] 1866 Mbps
5980 22:55:48.545718 CH 0, Rank 0
5981 22:55:48.548371 SW Impedance : PASS
5982 22:55:48.551775 DUTY Scan : NO K
5983 22:55:48.552205 ZQ Calibration : PASS
5984 22:55:48.555148 Jitter Meter : NO K
5985 22:55:48.558391 CBT Training : PASS
5986 22:55:48.558883 Write leveling : PASS
5987 22:55:48.561742 RX DQS gating : PASS
5988 22:55:48.565302 RX DQ/DQS(RDDQC) : PASS
5989 22:55:48.565827 TX DQ/DQS : PASS
5990 22:55:48.568053 RX DATLAT : PASS
5991 22:55:48.571970 RX DQ/DQS(Engine): PASS
5992 22:55:48.572544 TX OE : NO K
5993 22:55:48.572906 All Pass.
5994 22:55:48.573229
5995 22:55:48.575239 CH 0, Rank 1
5996 22:55:48.578385 SW Impedance : PASS
5997 22:55:48.578959 DUTY Scan : NO K
5998 22:55:48.581602 ZQ Calibration : PASS
5999 22:55:48.582128 Jitter Meter : NO K
6000 22:55:48.584726 CBT Training : PASS
6001 22:55:48.588119 Write leveling : PASS
6002 22:55:48.588548 RX DQS gating : PASS
6003 22:55:48.591352 RX DQ/DQS(RDDQC) : PASS
6004 22:55:48.594924 TX DQ/DQS : PASS
6005 22:55:48.595370 RX DATLAT : PASS
6006 22:55:48.598134 RX DQ/DQS(Engine): PASS
6007 22:55:48.601159 TX OE : NO K
6008 22:55:48.601599 All Pass.
6009 22:55:48.601941
6010 22:55:48.602255 CH 1, Rank 0
6011 22:55:48.604504 SW Impedance : PASS
6012 22:55:48.607857 DUTY Scan : NO K
6013 22:55:48.608324 ZQ Calibration : PASS
6014 22:55:48.611179 Jitter Meter : NO K
6015 22:55:48.614607 CBT Training : PASS
6016 22:55:48.615150 Write leveling : PASS
6017 22:55:48.617594 RX DQS gating : PASS
6018 22:55:48.621446 RX DQ/DQS(RDDQC) : PASS
6019 22:55:48.621972 TX DQ/DQS : PASS
6020 22:55:48.624410 RX DATLAT : PASS
6021 22:55:48.628374 RX DQ/DQS(Engine): PASS
6022 22:55:48.628901 TX OE : NO K
6023 22:55:48.631211 All Pass.
6024 22:55:48.631636
6025 22:55:48.631977 CH 1, Rank 1
6026 22:55:48.634210 SW Impedance : PASS
6027 22:55:48.634657 DUTY Scan : NO K
6028 22:55:48.637687 ZQ Calibration : PASS
6029 22:55:48.640987 Jitter Meter : NO K
6030 22:55:48.641412 CBT Training : PASS
6031 22:55:48.644457 Write leveling : PASS
6032 22:55:48.647342 RX DQS gating : PASS
6033 22:55:48.647766 RX DQ/DQS(RDDQC) : PASS
6034 22:55:48.650935 TX DQ/DQS : PASS
6035 22:55:48.651368 RX DATLAT : PASS
6036 22:55:48.654136 RX DQ/DQS(Engine): PASS
6037 22:55:48.657276 TX OE : NO K
6038 22:55:48.657707 All Pass.
6039 22:55:48.658049
6040 22:55:48.660748 DramC Write-DBI off
6041 22:55:48.663857 PER_BANK_REFRESH: Hybrid Mode
6042 22:55:48.664374 TX_TRACKING: ON
6043 22:55:48.673824 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6044 22:55:48.677110 [FAST_K] Save calibration result to emmc
6045 22:55:48.680512 dramc_set_vcore_voltage set vcore to 650000
6046 22:55:48.683378 Read voltage for 400, 6
6047 22:55:48.683805 Vio18 = 0
6048 22:55:48.684145 Vcore = 650000
6049 22:55:48.686973 Vdram = 0
6050 22:55:48.687505 Vddq = 0
6051 22:55:48.687850 Vmddr = 0
6052 22:55:48.693874 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6053 22:55:48.697318 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6054 22:55:48.700573 MEM_TYPE=3, freq_sel=20
6055 22:55:48.703362 sv_algorithm_assistance_LP4_800
6056 22:55:48.706960 ============ PULL DRAM RESETB DOWN ============
6057 22:55:48.709916 ========== PULL DRAM RESETB DOWN end =========
6058 22:55:48.716521 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6059 22:55:48.720095 ===================================
6060 22:55:48.720537 LPDDR4 DRAM CONFIGURATION
6061 22:55:48.723189 ===================================
6062 22:55:48.726909 EX_ROW_EN[0] = 0x0
6063 22:55:48.730276 EX_ROW_EN[1] = 0x0
6064 22:55:48.730796 LP4Y_EN = 0x0
6065 22:55:48.733230 WORK_FSP = 0x0
6066 22:55:48.733756 WL = 0x2
6067 22:55:48.736839 RL = 0x2
6068 22:55:48.737452 BL = 0x2
6069 22:55:48.739718 RPST = 0x0
6070 22:55:48.740146 RD_PRE = 0x0
6071 22:55:48.742890 WR_PRE = 0x1
6072 22:55:48.743314 WR_PST = 0x0
6073 22:55:48.746283 DBI_WR = 0x0
6074 22:55:48.746706 DBI_RD = 0x0
6075 22:55:48.749678 OTF = 0x1
6076 22:55:48.752996 ===================================
6077 22:55:48.756195 ===================================
6078 22:55:48.756623 ANA top config
6079 22:55:48.759808 ===================================
6080 22:55:48.762953 DLL_ASYNC_EN = 0
6081 22:55:48.766403 ALL_SLAVE_EN = 1
6082 22:55:48.769586 NEW_RANK_MODE = 1
6083 22:55:48.770016 DLL_IDLE_MODE = 1
6084 22:55:48.772728 LP45_APHY_COMB_EN = 1
6085 22:55:48.776516 TX_ODT_DIS = 1
6086 22:55:48.779551 NEW_8X_MODE = 1
6087 22:55:48.782466 ===================================
6088 22:55:48.785703 ===================================
6089 22:55:48.789455 data_rate = 800
6090 22:55:48.792765 CKR = 1
6091 22:55:48.793197 DQ_P2S_RATIO = 4
6092 22:55:48.796336 ===================================
6093 22:55:48.799323 CA_P2S_RATIO = 4
6094 22:55:48.802433 DQ_CA_OPEN = 0
6095 22:55:48.805718 DQ_SEMI_OPEN = 1
6096 22:55:48.808918 CA_SEMI_OPEN = 1
6097 22:55:48.812381 CA_FULL_RATE = 0
6098 22:55:48.812920 DQ_CKDIV4_EN = 0
6099 22:55:48.816219 CA_CKDIV4_EN = 1
6100 22:55:48.818890 CA_PREDIV_EN = 0
6101 22:55:48.822513 PH8_DLY = 0
6102 22:55:48.825775 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6103 22:55:48.829196 DQ_AAMCK_DIV = 0
6104 22:55:48.829720 CA_AAMCK_DIV = 0
6105 22:55:48.832703 CA_ADMCK_DIV = 4
6106 22:55:48.835129 DQ_TRACK_CA_EN = 0
6107 22:55:48.838559 CA_PICK = 800
6108 22:55:48.841606 CA_MCKIO = 400
6109 22:55:48.845241 MCKIO_SEMI = 400
6110 22:55:48.848281 PLL_FREQ = 3016
6111 22:55:48.851642 DQ_UI_PI_RATIO = 32
6112 22:55:48.852070 CA_UI_PI_RATIO = 32
6113 22:55:48.854919 ===================================
6114 22:55:48.858330 ===================================
6115 22:55:48.861799 memory_type:LPDDR4
6116 22:55:48.864996 GP_NUM : 10
6117 22:55:48.865426 SRAM_EN : 1
6118 22:55:48.868208 MD32_EN : 0
6119 22:55:48.871915 ===================================
6120 22:55:48.875042 [ANA_INIT] >>>>>>>>>>>>>>
6121 22:55:48.878445 <<<<<< [CONFIGURE PHASE]: ANA_TX
6122 22:55:48.881923 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6123 22:55:48.885130 ===================================
6124 22:55:48.885567 data_rate = 800,PCW = 0X7400
6125 22:55:48.888340 ===================================
6126 22:55:48.891432 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6127 22:55:48.898155 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6128 22:55:48.910750 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6129 22:55:48.914177 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6130 22:55:48.917539 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6131 22:55:48.920799 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6132 22:55:48.924190 [ANA_INIT] flow start
6133 22:55:48.924756 [ANA_INIT] PLL >>>>>>>>
6134 22:55:48.927387 [ANA_INIT] PLL <<<<<<<<
6135 22:55:48.930995 [ANA_INIT] MIDPI >>>>>>>>
6136 22:55:48.934309 [ANA_INIT] MIDPI <<<<<<<<
6137 22:55:48.934888 [ANA_INIT] DLL >>>>>>>>
6138 22:55:48.937238 [ANA_INIT] flow end
6139 22:55:48.940739 ============ LP4 DIFF to SE enter ============
6140 22:55:48.943642 ============ LP4 DIFF to SE exit ============
6141 22:55:48.947214 [ANA_INIT] <<<<<<<<<<<<<
6142 22:55:48.950696 [Flow] Enable top DCM control >>>>>
6143 22:55:48.953958 [Flow] Enable top DCM control <<<<<
6144 22:55:48.957047 Enable DLL master slave shuffle
6145 22:55:48.963560 ==============================================================
6146 22:55:48.963985 Gating Mode config
6147 22:55:48.970167 ==============================================================
6148 22:55:48.970630 Config description:
6149 22:55:48.980112 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6150 22:55:48.987054 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6151 22:55:48.993362 SELPH_MODE 0: By rank 1: By Phase
6152 22:55:48.996824 ==============================================================
6153 22:55:49.000115 GAT_TRACK_EN = 0
6154 22:55:49.003108 RX_GATING_MODE = 2
6155 22:55:49.006432 RX_GATING_TRACK_MODE = 2
6156 22:55:49.009723 SELPH_MODE = 1
6157 22:55:49.013070 PICG_EARLY_EN = 1
6158 22:55:49.016447 VALID_LAT_VALUE = 1
6159 22:55:49.023035 ==============================================================
6160 22:55:49.026376 Enter into Gating configuration >>>>
6161 22:55:49.029840 Exit from Gating configuration <<<<
6162 22:55:49.033201 Enter into DVFS_PRE_config >>>>>
6163 22:55:49.043139 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6164 22:55:49.046194 Exit from DVFS_PRE_config <<<<<
6165 22:55:49.049509 Enter into PICG configuration >>>>
6166 22:55:49.052671 Exit from PICG configuration <<<<
6167 22:55:49.056111 [RX_INPUT] configuration >>>>>
6168 22:55:49.056267 [RX_INPUT] configuration <<<<<
6169 22:55:49.062071 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6170 22:55:49.069096 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6171 22:55:49.075391 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6172 22:55:49.078635 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6173 22:55:49.085349 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6174 22:55:49.091815 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6175 22:55:49.095217 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6176 22:55:49.101658 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6177 22:55:49.105075 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6178 22:55:49.108483 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6179 22:55:49.111310 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6180 22:55:49.118113 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6181 22:55:49.121480 ===================================
6182 22:55:49.121564 LPDDR4 DRAM CONFIGURATION
6183 22:55:49.125050 ===================================
6184 22:55:49.128073 EX_ROW_EN[0] = 0x0
6185 22:55:49.131800 EX_ROW_EN[1] = 0x0
6186 22:55:49.131884 LP4Y_EN = 0x0
6187 22:55:49.134617 WORK_FSP = 0x0
6188 22:55:49.134699 WL = 0x2
6189 22:55:49.137992 RL = 0x2
6190 22:55:49.138076 BL = 0x2
6191 22:55:49.141356 RPST = 0x0
6192 22:55:49.141441 RD_PRE = 0x0
6193 22:55:49.144764 WR_PRE = 0x1
6194 22:55:49.144847 WR_PST = 0x0
6195 22:55:49.148140 DBI_WR = 0x0
6196 22:55:49.148223 DBI_RD = 0x0
6197 22:55:49.151351 OTF = 0x1
6198 22:55:49.154758 ===================================
6199 22:55:49.157960 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6200 22:55:49.161443 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6201 22:55:49.168072 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6202 22:55:49.170981 ===================================
6203 22:55:49.171064 LPDDR4 DRAM CONFIGURATION
6204 22:55:49.174761 ===================================
6205 22:55:49.177522 EX_ROW_EN[0] = 0x10
6206 22:55:49.180875 EX_ROW_EN[1] = 0x0
6207 22:55:49.180958 LP4Y_EN = 0x0
6208 22:55:49.184165 WORK_FSP = 0x0
6209 22:55:49.184270 WL = 0x2
6210 22:55:49.187364 RL = 0x2
6211 22:55:49.187448 BL = 0x2
6212 22:55:49.190546 RPST = 0x0
6213 22:55:49.190629 RD_PRE = 0x0
6214 22:55:49.194512 WR_PRE = 0x1
6215 22:55:49.194595 WR_PST = 0x0
6216 22:55:49.197756 DBI_WR = 0x0
6217 22:55:49.197838 DBI_RD = 0x0
6218 22:55:49.201238 OTF = 0x1
6219 22:55:49.204062 ===================================
6220 22:55:49.210348 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6221 22:55:49.213761 nWR fixed to 30
6222 22:55:49.217341 [ModeRegInit_LP4] CH0 RK0
6223 22:55:49.217424 [ModeRegInit_LP4] CH0 RK1
6224 22:55:49.220704 [ModeRegInit_LP4] CH1 RK0
6225 22:55:49.223571 [ModeRegInit_LP4] CH1 RK1
6226 22:55:49.223653 match AC timing 19
6227 22:55:49.230599 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6228 22:55:49.233979 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6229 22:55:49.236929 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6230 22:55:49.243490 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6231 22:55:49.247066 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6232 22:55:49.247152 ==
6233 22:55:49.250365 Dram Type= 6, Freq= 0, CH_0, rank 0
6234 22:55:49.253270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6235 22:55:49.253355 ==
6236 22:55:49.259981 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6237 22:55:49.267026 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6238 22:55:49.270508 [CA 0] Center 36 (8~64) winsize 57
6239 22:55:49.273626 [CA 1] Center 36 (8~64) winsize 57
6240 22:55:49.276679 [CA 2] Center 36 (8~64) winsize 57
6241 22:55:49.280330 [CA 3] Center 36 (8~64) winsize 57
6242 22:55:49.280418 [CA 4] Center 36 (8~64) winsize 57
6243 22:55:49.283470 [CA 5] Center 36 (8~64) winsize 57
6244 22:55:49.283553
6245 22:55:49.289851 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6246 22:55:49.289935
6247 22:55:49.293356 [CATrainingPosCal] consider 1 rank data
6248 22:55:49.296420 u2DelayCellTimex100 = 270/100 ps
6249 22:55:49.299996 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 22:55:49.303359 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 22:55:49.306622 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 22:55:49.310119 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 22:55:49.312737 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 22:55:49.316580 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 22:55:49.316680
6256 22:55:49.319418 CA PerBit enable=1, Macro0, CA PI delay=36
6257 22:55:49.319502
6258 22:55:49.322720 [CBTSetCACLKResult] CA Dly = 36
6259 22:55:49.326233 CS Dly: 1 (0~32)
6260 22:55:49.326316 ==
6261 22:55:49.329757 Dram Type= 6, Freq= 0, CH_0, rank 1
6262 22:55:49.332891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6263 22:55:49.332978 ==
6264 22:55:49.339330 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6265 22:55:49.345718 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6266 22:55:49.349061 [CA 0] Center 36 (8~64) winsize 57
6267 22:55:49.352332 [CA 1] Center 36 (8~64) winsize 57
6268 22:55:49.355725 [CA 2] Center 36 (8~64) winsize 57
6269 22:55:49.355808 [CA 3] Center 36 (8~64) winsize 57
6270 22:55:49.359201 [CA 4] Center 36 (8~64) winsize 57
6271 22:55:49.362326 [CA 5] Center 36 (8~64) winsize 57
6272 22:55:49.362410
6273 22:55:49.368951 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6274 22:55:49.369038
6275 22:55:49.372452 [CATrainingPosCal] consider 2 rank data
6276 22:55:49.372535 u2DelayCellTimex100 = 270/100 ps
6277 22:55:49.378773 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 22:55:49.382301 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 22:55:49.385263 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 22:55:49.388958 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 22:55:49.392088 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 22:55:49.395228 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 22:55:49.395339
6284 22:55:49.398642 CA PerBit enable=1, Macro0, CA PI delay=36
6285 22:55:49.398726
6286 22:55:49.401869 [CBTSetCACLKResult] CA Dly = 36
6287 22:55:49.405582 CS Dly: 1 (0~32)
6288 22:55:49.405666
6289 22:55:49.408578 ----->DramcWriteLeveling(PI) begin...
6290 22:55:49.408657 ==
6291 22:55:49.412019 Dram Type= 6, Freq= 0, CH_0, rank 0
6292 22:55:49.415101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6293 22:55:49.415174 ==
6294 22:55:49.418207 Write leveling (Byte 0): 40 => 8
6295 22:55:49.421887 Write leveling (Byte 1): 32 => 0
6296 22:55:49.425073 DramcWriteLeveling(PI) end<-----
6297 22:55:49.425148
6298 22:55:49.425210 ==
6299 22:55:49.428503 Dram Type= 6, Freq= 0, CH_0, rank 0
6300 22:55:49.431307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6301 22:55:49.431405 ==
6302 22:55:49.434748 [Gating] SW mode calibration
6303 22:55:49.441756 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6304 22:55:49.447823 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6305 22:55:49.451272 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6306 22:55:49.457621 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6307 22:55:49.460943 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6308 22:55:49.464486 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6309 22:55:49.471146 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6310 22:55:49.474010 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6311 22:55:49.477577 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6312 22:55:49.484427 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6313 22:55:49.487258 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6314 22:55:49.490720 Total UI for P1: 0, mck2ui 16
6315 22:55:49.493699 best dqsien dly found for B0: ( 0, 14, 24)
6316 22:55:49.497320 Total UI for P1: 0, mck2ui 16
6317 22:55:49.500875 best dqsien dly found for B1: ( 0, 14, 24)
6318 22:55:49.504047 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6319 22:55:49.507384 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6320 22:55:49.507496
6321 22:55:49.510476 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6322 22:55:49.513575 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6323 22:55:49.517120 [Gating] SW calibration Done
6324 22:55:49.517202 ==
6325 22:55:49.520433 Dram Type= 6, Freq= 0, CH_0, rank 0
6326 22:55:49.523882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6327 22:55:49.527020 ==
6328 22:55:49.527104 RX Vref Scan: 0
6329 22:55:49.527171
6330 22:55:49.530558 RX Vref 0 -> 0, step: 1
6331 22:55:49.530642
6332 22:55:49.533659 RX Delay -410 -> 252, step: 16
6333 22:55:49.537095 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6334 22:55:49.539876 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6335 22:55:49.543735 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6336 22:55:49.549914 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6337 22:55:49.553410 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6338 22:55:49.556791 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6339 22:55:49.560255 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6340 22:55:49.566550 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6341 22:55:49.569677 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6342 22:55:49.573025 iDelay=230, Bit 9, Center -67 (-330 ~ 197) 528
6343 22:55:49.579679 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6344 22:55:49.583088 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6345 22:55:49.586266 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6346 22:55:49.590072 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6347 22:55:49.596466 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6348 22:55:49.599331 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6349 22:55:49.599416 ==
6350 22:55:49.602702 Dram Type= 6, Freq= 0, CH_0, rank 0
6351 22:55:49.606252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6352 22:55:49.606337 ==
6353 22:55:49.609314 DQS Delay:
6354 22:55:49.609397 DQS0 = 59, DQS1 = 67
6355 22:55:49.613108 DQM Delay:
6356 22:55:49.613190 DQM0 = 18, DQM1 = 17
6357 22:55:49.613256 DQ Delay:
6358 22:55:49.616323 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6359 22:55:49.619678 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6360 22:55:49.622757 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6361 22:55:49.625968 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6362 22:55:49.626050
6363 22:55:49.626115
6364 22:55:49.626175 ==
6365 22:55:49.629297 Dram Type= 6, Freq= 0, CH_0, rank 0
6366 22:55:49.635952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6367 22:55:49.636036 ==
6368 22:55:49.636102
6369 22:55:49.636164
6370 22:55:49.636222 TX Vref Scan disable
6371 22:55:49.639408 == TX Byte 0 ==
6372 22:55:49.642356 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6373 22:55:49.645879 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6374 22:55:49.649036 == TX Byte 1 ==
6375 22:55:49.652419 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6376 22:55:49.658808 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6377 22:55:49.658929 ==
6378 22:55:49.662286 Dram Type= 6, Freq= 0, CH_0, rank 0
6379 22:55:49.665906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6380 22:55:49.665990 ==
6381 22:55:49.666057
6382 22:55:49.666118
6383 22:55:49.668578 TX Vref Scan disable
6384 22:55:49.668660 == TX Byte 0 ==
6385 22:55:49.672075 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6386 22:55:49.678895 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6387 22:55:49.678982 == TX Byte 1 ==
6388 22:55:49.682301 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6389 22:55:49.688339 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6390 22:55:49.688422
6391 22:55:49.688487 [DATLAT]
6392 22:55:49.691725 Freq=400, CH0 RK0
6393 22:55:49.691808
6394 22:55:49.691874 DATLAT Default: 0xf
6395 22:55:49.695077 0, 0xFFFF, sum = 0
6396 22:55:49.695162 1, 0xFFFF, sum = 0
6397 22:55:49.698861 2, 0xFFFF, sum = 0
6398 22:55:49.698958 3, 0xFFFF, sum = 0
6399 22:55:49.702002 4, 0xFFFF, sum = 0
6400 22:55:49.702090 5, 0xFFFF, sum = 0
6401 22:55:49.705291 6, 0xFFFF, sum = 0
6402 22:55:49.705374 7, 0xFFFF, sum = 0
6403 22:55:49.708826 8, 0xFFFF, sum = 0
6404 22:55:49.708911 9, 0xFFFF, sum = 0
6405 22:55:49.711726 10, 0xFFFF, sum = 0
6406 22:55:49.711810 11, 0xFFFF, sum = 0
6407 22:55:49.715128 12, 0xFFFF, sum = 0
6408 22:55:49.715212 13, 0x0, sum = 1
6409 22:55:49.718182 14, 0x0, sum = 2
6410 22:55:49.718266 15, 0x0, sum = 3
6411 22:55:49.721533 16, 0x0, sum = 4
6412 22:55:49.721617 best_step = 14
6413 22:55:49.721684
6414 22:55:49.721744 ==
6415 22:55:49.724908 Dram Type= 6, Freq= 0, CH_0, rank 0
6416 22:55:49.731273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6417 22:55:49.731357 ==
6418 22:55:49.731423 RX Vref Scan: 1
6419 22:55:49.731486
6420 22:55:49.734875 RX Vref 0 -> 0, step: 1
6421 22:55:49.734958
6422 22:55:49.738421 RX Delay -375 -> 252, step: 8
6423 22:55:49.738505
6424 22:55:49.741141 Set Vref, RX VrefLevel [Byte0]: 62
6425 22:55:49.744539 [Byte1]: 52
6426 22:55:49.748552
6427 22:55:49.748634 Final RX Vref Byte 0 = 62 to rank0
6428 22:55:49.751193 Final RX Vref Byte 1 = 52 to rank0
6429 22:55:49.754869 Final RX Vref Byte 0 = 62 to rank1
6430 22:55:49.757776 Final RX Vref Byte 1 = 52 to rank1==
6431 22:55:49.761084 Dram Type= 6, Freq= 0, CH_0, rank 0
6432 22:55:49.768026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6433 22:55:49.768110 ==
6434 22:55:49.768176 DQS Delay:
6435 22:55:49.771181 DQS0 = 60, DQS1 = 68
6436 22:55:49.771263 DQM Delay:
6437 22:55:49.771329 DQM0 = 14, DQM1 = 14
6438 22:55:49.774630 DQ Delay:
6439 22:55:49.777955 DQ0 =12, DQ1 =16, DQ2 =12, DQ3 =8
6440 22:55:49.781166 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6441 22:55:49.784008 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6442 22:55:49.787415 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6443 22:55:49.787498
6444 22:55:49.787563
6445 22:55:49.793926 [DQSOSCAuto] RK0, (LSB)MR18= 0x8785, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6446 22:55:49.797363 CH0 RK0: MR19=C0C, MR18=8785
6447 22:55:49.804433 CH0_RK0: MR19=0xC0C, MR18=0x8785, DQSOSC=392, MR23=63, INC=384, DEC=256
6448 22:55:49.804516 ==
6449 22:55:49.807695 Dram Type= 6, Freq= 0, CH_0, rank 1
6450 22:55:49.810953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6451 22:55:49.811037 ==
6452 22:55:49.813820 [Gating] SW mode calibration
6453 22:55:49.820850 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6454 22:55:49.827435 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6455 22:55:49.830749 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6456 22:55:49.833702 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6457 22:55:49.840530 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6458 22:55:49.843738 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6459 22:55:49.847015 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6460 22:55:49.853831 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6461 22:55:49.856984 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6462 22:55:49.860215 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6463 22:55:49.866782 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6464 22:55:49.870139 Total UI for P1: 0, mck2ui 16
6465 22:55:49.873500 best dqsien dly found for B0: ( 0, 14, 24)
6466 22:55:49.873584 Total UI for P1: 0, mck2ui 16
6467 22:55:49.880375 best dqsien dly found for B1: ( 0, 14, 24)
6468 22:55:49.883553 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6469 22:55:49.886416 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6470 22:55:49.886499
6471 22:55:49.889849 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6472 22:55:49.893104 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6473 22:55:49.896430 [Gating] SW calibration Done
6474 22:55:49.896512 ==
6475 22:55:49.899750 Dram Type= 6, Freq= 0, CH_0, rank 1
6476 22:55:49.903017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6477 22:55:49.903102 ==
6478 22:55:49.906379 RX Vref Scan: 0
6479 22:55:49.906462
6480 22:55:49.909746 RX Vref 0 -> 0, step: 1
6481 22:55:49.909830
6482 22:55:49.909895 RX Delay -410 -> 252, step: 16
6483 22:55:49.916636 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6484 22:55:49.919934 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6485 22:55:49.923226 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6486 22:55:49.929836 iDelay=230, Bit 3, Center -51 (-314 ~ 213) 528
6487 22:55:49.932873 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6488 22:55:49.935975 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6489 22:55:49.939485 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6490 22:55:49.946177 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6491 22:55:49.949476 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6492 22:55:49.952746 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6493 22:55:49.955874 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6494 22:55:49.962603 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6495 22:55:49.965742 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6496 22:55:49.969274 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6497 22:55:49.972346 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6498 22:55:49.979047 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6499 22:55:49.979131 ==
6500 22:55:49.982486 Dram Type= 6, Freq= 0, CH_0, rank 1
6501 22:55:49.985766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6502 22:55:49.985850 ==
6503 22:55:49.985916 DQS Delay:
6504 22:55:49.989104 DQS0 = 59, DQS1 = 59
6505 22:55:49.989188 DQM Delay:
6506 22:55:49.992506 DQM0 = 15, DQM1 = 10
6507 22:55:49.992589 DQ Delay:
6508 22:55:49.995777 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =8
6509 22:55:49.998732 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6510 22:55:50.001969 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6511 22:55:50.005240 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6512 22:55:50.005324
6513 22:55:50.005390
6514 22:55:50.005452 ==
6515 22:55:50.008716 Dram Type= 6, Freq= 0, CH_0, rank 1
6516 22:55:50.012066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6517 22:55:50.015444 ==
6518 22:55:50.015528
6519 22:55:50.015594
6520 22:55:50.015654 TX Vref Scan disable
6521 22:55:50.018717 == TX Byte 0 ==
6522 22:55:50.021886 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6523 22:55:50.025445 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6524 22:55:50.028351 == TX Byte 1 ==
6525 22:55:50.031659 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6526 22:55:50.035128 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6527 22:55:50.035211 ==
6528 22:55:50.038205 Dram Type= 6, Freq= 0, CH_0, rank 1
6529 22:55:50.045110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6530 22:55:50.045201 ==
6531 22:55:50.045268
6532 22:55:50.045328
6533 22:55:50.045386 TX Vref Scan disable
6534 22:55:50.048392 == TX Byte 0 ==
6535 22:55:50.051762 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6536 22:55:50.055010 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6537 22:55:50.058072 == TX Byte 1 ==
6538 22:55:50.061789 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6539 22:55:50.064594 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6540 22:55:50.064678
6541 22:55:50.067931 [DATLAT]
6542 22:55:50.068014 Freq=400, CH0 RK1
6543 22:55:50.068081
6544 22:55:50.071143 DATLAT Default: 0xe
6545 22:55:50.071226 0, 0xFFFF, sum = 0
6546 22:55:50.074859 1, 0xFFFF, sum = 0
6547 22:55:50.074944 2, 0xFFFF, sum = 0
6548 22:55:50.078433 3, 0xFFFF, sum = 0
6549 22:55:50.078517 4, 0xFFFF, sum = 0
6550 22:55:50.081180 5, 0xFFFF, sum = 0
6551 22:55:50.081264 6, 0xFFFF, sum = 0
6552 22:55:50.084879 7, 0xFFFF, sum = 0
6553 22:55:50.084964 8, 0xFFFF, sum = 0
6554 22:55:50.088305 9, 0xFFFF, sum = 0
6555 22:55:50.088390 10, 0xFFFF, sum = 0
6556 22:55:50.091393 11, 0xFFFF, sum = 0
6557 22:55:50.094752 12, 0xFFFF, sum = 0
6558 22:55:50.094862 13, 0x0, sum = 1
6559 22:55:50.094946 14, 0x0, sum = 2
6560 22:55:50.098176 15, 0x0, sum = 3
6561 22:55:50.098260 16, 0x0, sum = 4
6562 22:55:50.101134 best_step = 14
6563 22:55:50.101217
6564 22:55:50.101283 ==
6565 22:55:50.104398 Dram Type= 6, Freq= 0, CH_0, rank 1
6566 22:55:50.108131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6567 22:55:50.108216 ==
6568 22:55:50.111070 RX Vref Scan: 0
6569 22:55:50.111153
6570 22:55:50.111236 RX Vref 0 -> 0, step: 1
6571 22:55:50.111301
6572 22:55:50.114344 RX Delay -359 -> 252, step: 8
6573 22:55:50.122798 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6574 22:55:50.126532 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6575 22:55:50.129605 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6576 22:55:50.136241 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6577 22:55:50.139321 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6578 22:55:50.142823 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6579 22:55:50.145758 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6580 22:55:50.152621 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6581 22:55:50.156036 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6582 22:55:50.159352 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6583 22:55:50.162739 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6584 22:55:50.169178 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6585 22:55:50.172201 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6586 22:55:50.175805 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6587 22:55:50.178988 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6588 22:55:50.186005 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6589 22:55:50.186093 ==
6590 22:55:50.188783 Dram Type= 6, Freq= 0, CH_0, rank 1
6591 22:55:50.192101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6592 22:55:50.192186 ==
6593 22:55:50.192271 DQS Delay:
6594 22:55:50.195332 DQS0 = 60, DQS1 = 72
6595 22:55:50.195416 DQM Delay:
6596 22:55:50.198789 DQM0 = 11, DQM1 = 17
6597 22:55:50.198912 DQ Delay:
6598 22:55:50.202177 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6599 22:55:50.205622 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6600 22:55:50.208893 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =12
6601 22:55:50.212223 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6602 22:55:50.212308
6603 22:55:50.212393
6604 22:55:50.218868 [DQSOSCAuto] RK1, (LSB)MR18= 0xd185, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6605 22:55:50.221763 CH0 RK1: MR19=C0C, MR18=D185
6606 22:55:50.228251 CH0_RK1: MR19=0xC0C, MR18=0xD185, DQSOSC=384, MR23=63, INC=400, DEC=267
6607 22:55:50.232042 [RxdqsGatingPostProcess] freq 400
6608 22:55:50.238406 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6609 22:55:50.242045 best DQS0 dly(2T, 0.5T) = (0, 10)
6610 22:55:50.245340 best DQS1 dly(2T, 0.5T) = (0, 10)
6611 22:55:50.248112 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6612 22:55:50.251613 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6613 22:55:50.254690 best DQS0 dly(2T, 0.5T) = (0, 10)
6614 22:55:50.254776 best DQS1 dly(2T, 0.5T) = (0, 10)
6615 22:55:50.258245 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6616 22:55:50.261140 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6617 22:55:50.264915 Pre-setting of DQS Precalculation
6618 22:55:50.271505 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6619 22:55:50.271591 ==
6620 22:55:50.274389 Dram Type= 6, Freq= 0, CH_1, rank 0
6621 22:55:50.278072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6622 22:55:50.278157 ==
6623 22:55:50.284835 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6624 22:55:50.291016 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6625 22:55:50.294316 [CA 0] Center 36 (8~64) winsize 57
6626 22:55:50.297697 [CA 1] Center 36 (8~64) winsize 57
6627 22:55:50.300972 [CA 2] Center 36 (8~64) winsize 57
6628 22:55:50.301057 [CA 3] Center 36 (8~64) winsize 57
6629 22:55:50.304721 [CA 4] Center 36 (8~64) winsize 57
6630 22:55:50.307778 [CA 5] Center 36 (8~64) winsize 57
6631 22:55:50.307864
6632 22:55:50.314542 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6633 22:55:50.314628
6634 22:55:50.317762 [CATrainingPosCal] consider 1 rank data
6635 22:55:50.321004 u2DelayCellTimex100 = 270/100 ps
6636 22:55:50.323802 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 22:55:50.327268 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 22:55:50.330753 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 22:55:50.333806 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 22:55:50.337158 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 22:55:50.340521 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 22:55:50.340605
6643 22:55:50.343892 CA PerBit enable=1, Macro0, CA PI delay=36
6644 22:55:50.343978
6645 22:55:50.347187 [CBTSetCACLKResult] CA Dly = 36
6646 22:55:50.350075 CS Dly: 1 (0~32)
6647 22:55:50.350159 ==
6648 22:55:50.353965 Dram Type= 6, Freq= 0, CH_1, rank 1
6649 22:55:50.357013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6650 22:55:50.357098 ==
6651 22:55:50.363702 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6652 22:55:50.370213 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6653 22:55:50.373380 [CA 0] Center 36 (8~64) winsize 57
6654 22:55:50.376601 [CA 1] Center 36 (8~64) winsize 57
6655 22:55:50.376686 [CA 2] Center 36 (8~64) winsize 57
6656 22:55:50.379934 [CA 3] Center 36 (8~64) winsize 57
6657 22:55:50.383720 [CA 4] Center 36 (8~64) winsize 57
6658 22:55:50.386913 [CA 5] Center 36 (8~64) winsize 57
6659 22:55:50.386998
6660 22:55:50.389947 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6661 22:55:50.393234
6662 22:55:50.396588 [CATrainingPosCal] consider 2 rank data
6663 22:55:50.396673 u2DelayCellTimex100 = 270/100 ps
6664 22:55:50.403044 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 22:55:50.406274 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 22:55:50.409515 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 22:55:50.412882 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 22:55:50.416205 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 22:55:50.419858 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 22:55:50.419943
6671 22:55:50.422712 CA PerBit enable=1, Macro0, CA PI delay=36
6672 22:55:50.422797
6673 22:55:50.426055 [CBTSetCACLKResult] CA Dly = 36
6674 22:55:50.429443 CS Dly: 1 (0~32)
6675 22:55:50.429527
6676 22:55:50.432839 ----->DramcWriteLeveling(PI) begin...
6677 22:55:50.432925 ==
6678 22:55:50.436187 Dram Type= 6, Freq= 0, CH_1, rank 0
6679 22:55:50.439288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6680 22:55:50.439374 ==
6681 22:55:50.442711 Write leveling (Byte 0): 40 => 8
6682 22:55:50.445955 Write leveling (Byte 1): 40 => 8
6683 22:55:50.449233 DramcWriteLeveling(PI) end<-----
6684 22:55:50.449315
6685 22:55:50.449381 ==
6686 22:55:50.452686 Dram Type= 6, Freq= 0, CH_1, rank 0
6687 22:55:50.456061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6688 22:55:50.456143 ==
6689 22:55:50.459233 [Gating] SW mode calibration
6690 22:55:50.465909 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6691 22:55:50.472098 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6692 22:55:50.475792 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6693 22:55:50.482110 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6694 22:55:50.485430 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6695 22:55:50.488657 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6696 22:55:50.492009 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6697 22:55:50.499024 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6698 22:55:50.501985 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6699 22:55:50.505020 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6700 22:55:50.511828 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6701 22:55:50.515079 Total UI for P1: 0, mck2ui 16
6702 22:55:50.518446 best dqsien dly found for B0: ( 0, 14, 24)
6703 22:55:50.521769 Total UI for P1: 0, mck2ui 16
6704 22:55:50.525089 best dqsien dly found for B1: ( 0, 14, 24)
6705 22:55:50.528528 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6706 22:55:50.531473 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6707 22:55:50.531555
6708 22:55:50.534819 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6709 22:55:50.538081 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6710 22:55:50.541529 [Gating] SW calibration Done
6711 22:55:50.541631 ==
6712 22:55:50.544655 Dram Type= 6, Freq= 0, CH_1, rank 0
6713 22:55:50.547872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6714 22:55:50.551581 ==
6715 22:55:50.551664 RX Vref Scan: 0
6716 22:55:50.551729
6717 22:55:50.554404 RX Vref 0 -> 0, step: 1
6718 22:55:50.554487
6719 22:55:50.557893 RX Delay -410 -> 252, step: 16
6720 22:55:50.560814 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6721 22:55:50.564741 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6722 22:55:50.567841 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6723 22:55:50.574371 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6724 22:55:50.577485 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6725 22:55:50.580710 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6726 22:55:50.584091 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6727 22:55:50.590712 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6728 22:55:50.593959 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6729 22:55:50.597323 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6730 22:55:50.603818 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6731 22:55:50.606868 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6732 22:55:50.610291 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6733 22:55:50.613503 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6734 22:55:50.620019 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6735 22:55:50.623486 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6736 22:55:50.623569 ==
6737 22:55:50.627034 Dram Type= 6, Freq= 0, CH_1, rank 0
6738 22:55:50.630519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6739 22:55:50.630602 ==
6740 22:55:50.633704 DQS Delay:
6741 22:55:50.633787 DQS0 = 51, DQS1 = 67
6742 22:55:50.636522 DQM Delay:
6743 22:55:50.636604 DQM0 = 13, DQM1 = 19
6744 22:55:50.636670 DQ Delay:
6745 22:55:50.640000 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6746 22:55:50.643269 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6747 22:55:50.646380 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6748 22:55:50.649789 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =32
6749 22:55:50.649873
6750 22:55:50.649939
6751 22:55:50.650001 ==
6752 22:55:50.653696 Dram Type= 6, Freq= 0, CH_1, rank 0
6753 22:55:50.659914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6754 22:55:50.659997 ==
6755 22:55:50.660063
6756 22:55:50.660124
6757 22:55:50.660183 TX Vref Scan disable
6758 22:55:50.663078 == TX Byte 0 ==
6759 22:55:50.666174 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6760 22:55:50.669303 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6761 22:55:50.672687 == TX Byte 1 ==
6762 22:55:50.676219 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6763 22:55:50.679902 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6764 22:55:50.683088 ==
6765 22:55:50.686052 Dram Type= 6, Freq= 0, CH_1, rank 0
6766 22:55:50.689380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6767 22:55:50.689463 ==
6768 22:55:50.689529
6769 22:55:50.689591
6770 22:55:50.692752 TX Vref Scan disable
6771 22:55:50.692836 == TX Byte 0 ==
6772 22:55:50.695730 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6773 22:55:50.702277 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6774 22:55:50.702361 == TX Byte 1 ==
6775 22:55:50.705495 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6776 22:55:50.712169 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6777 22:55:50.712253
6778 22:55:50.712318 [DATLAT]
6779 22:55:50.712379 Freq=400, CH1 RK0
6780 22:55:50.712439
6781 22:55:50.715319 DATLAT Default: 0xf
6782 22:55:50.718669 0, 0xFFFF, sum = 0
6783 22:55:50.718754 1, 0xFFFF, sum = 0
6784 22:55:50.722470 2, 0xFFFF, sum = 0
6785 22:55:50.722554 3, 0xFFFF, sum = 0
6786 22:55:50.725544 4, 0xFFFF, sum = 0
6787 22:55:50.725629 5, 0xFFFF, sum = 0
6788 22:55:50.728644 6, 0xFFFF, sum = 0
6789 22:55:50.728729 7, 0xFFFF, sum = 0
6790 22:55:50.732441 8, 0xFFFF, sum = 0
6791 22:55:50.732525 9, 0xFFFF, sum = 0
6792 22:55:50.735198 10, 0xFFFF, sum = 0
6793 22:55:50.735283 11, 0xFFFF, sum = 0
6794 22:55:50.738573 12, 0xFFFF, sum = 0
6795 22:55:50.738657 13, 0x0, sum = 1
6796 22:55:50.742042 14, 0x0, sum = 2
6797 22:55:50.742129 15, 0x0, sum = 3
6798 22:55:50.744947 16, 0x0, sum = 4
6799 22:55:50.745033 best_step = 14
6800 22:55:50.745098
6801 22:55:50.745160 ==
6802 22:55:50.748360 Dram Type= 6, Freq= 0, CH_1, rank 0
6803 22:55:50.754992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6804 22:55:50.755076 ==
6805 22:55:50.755142 RX Vref Scan: 1
6806 22:55:50.755204
6807 22:55:50.758362 RX Vref 0 -> 0, step: 1
6808 22:55:50.758445
6809 22:55:50.761224 RX Delay -375 -> 252, step: 8
6810 22:55:50.761307
6811 22:55:50.765154 Set Vref, RX VrefLevel [Byte0]: 56
6812 22:55:50.767960 [Byte1]: 55
6813 22:55:50.771419
6814 22:55:50.771502 Final RX Vref Byte 0 = 56 to rank0
6815 22:55:50.775145 Final RX Vref Byte 1 = 55 to rank0
6816 22:55:50.778330 Final RX Vref Byte 0 = 56 to rank1
6817 22:55:50.781591 Final RX Vref Byte 1 = 55 to rank1==
6818 22:55:50.784764 Dram Type= 6, Freq= 0, CH_1, rank 0
6819 22:55:50.790901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6820 22:55:50.790985 ==
6821 22:55:50.791052 DQS Delay:
6822 22:55:50.794579 DQS0 = 52, DQS1 = 64
6823 22:55:50.794662 DQM Delay:
6824 22:55:50.794727 DQM0 = 9, DQM1 = 10
6825 22:55:50.797727 DQ Delay:
6826 22:55:50.800782 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6827 22:55:50.804530 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =4
6828 22:55:50.804613 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6829 22:55:50.810770 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6830 22:55:50.810859
6831 22:55:50.810926
6832 22:55:50.817364 [DQSOSCAuto] RK0, (LSB)MR18= 0x5568, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
6833 22:55:50.820650 CH1 RK0: MR19=C0C, MR18=5568
6834 22:55:50.827221 CH1_RK0: MR19=0xC0C, MR18=0x5568, DQSOSC=396, MR23=63, INC=376, DEC=251
6835 22:55:50.827320 ==
6836 22:55:50.831169 Dram Type= 6, Freq= 0, CH_1, rank 1
6837 22:55:50.833771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6838 22:55:50.833855 ==
6839 22:55:50.836941 [Gating] SW mode calibration
6840 22:55:50.843426 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6841 22:55:50.850201 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6842 22:55:50.853694 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6843 22:55:50.857065 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6844 22:55:50.863348 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6845 22:55:50.866540 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6846 22:55:50.869973 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6847 22:55:50.876356 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6848 22:55:50.879598 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6849 22:55:50.883192 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6850 22:55:50.889421 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6851 22:55:50.892830 Total UI for P1: 0, mck2ui 16
6852 22:55:50.896219 best dqsien dly found for B0: ( 0, 14, 24)
6853 22:55:50.899348 Total UI for P1: 0, mck2ui 16
6854 22:55:50.902961 best dqsien dly found for B1: ( 0, 14, 24)
6855 22:55:50.906015 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6856 22:55:50.909155 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6857 22:55:50.909239
6858 22:55:50.912697 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6859 22:55:50.916142 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6860 22:55:50.919735 [Gating] SW calibration Done
6861 22:55:50.919832 ==
6862 22:55:50.922624 Dram Type= 6, Freq= 0, CH_1, rank 1
6863 22:55:50.925979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6864 22:55:50.926072 ==
6865 22:55:50.929389 RX Vref Scan: 0
6866 22:55:50.929481
6867 22:55:50.932223 RX Vref 0 -> 0, step: 1
6868 22:55:50.932309
6869 22:55:50.935687 RX Delay -410 -> 252, step: 16
6870 22:55:50.938953 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6871 22:55:50.942167 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6872 22:55:50.945466 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6873 22:55:50.952388 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6874 22:55:50.955712 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6875 22:55:50.958986 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6876 22:55:50.962294 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6877 22:55:50.969087 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6878 22:55:50.971874 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6879 22:55:50.975145 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6880 22:55:50.978582 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6881 22:55:50.985403 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6882 22:55:50.989139 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6883 22:55:50.991824 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6884 22:55:50.998748 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6885 22:55:51.001712 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6886 22:55:51.001801 ==
6887 22:55:51.004941 Dram Type= 6, Freq= 0, CH_1, rank 1
6888 22:55:51.008516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6889 22:55:51.008620 ==
6890 22:55:51.011967 DQS Delay:
6891 22:55:51.012051 DQS0 = 59, DQS1 = 59
6892 22:55:51.012117 DQM Delay:
6893 22:55:51.015224 DQM0 = 19, DQM1 = 14
6894 22:55:51.015308 DQ Delay:
6895 22:55:51.018307 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6896 22:55:51.021288 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6897 22:55:51.024883 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6898 22:55:51.028366 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6899 22:55:51.028439
6900 22:55:51.028501
6901 22:55:51.028561 ==
6902 22:55:51.031298 Dram Type= 6, Freq= 0, CH_1, rank 1
6903 22:55:51.038051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6904 22:55:51.038137 ==
6905 22:55:51.038204
6906 22:55:51.038263
6907 22:55:51.038322 TX Vref Scan disable
6908 22:55:51.041052 == TX Byte 0 ==
6909 22:55:51.044339 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6910 22:55:51.047659 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6911 22:55:51.051026 == TX Byte 1 ==
6912 22:55:51.054629 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6913 22:55:51.057780 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6914 22:55:51.057864 ==
6915 22:55:51.061113 Dram Type= 6, Freq= 0, CH_1, rank 1
6916 22:55:51.067541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6917 22:55:51.067626 ==
6918 22:55:51.067692
6919 22:55:51.067752
6920 22:55:51.067810 TX Vref Scan disable
6921 22:55:51.071241 == TX Byte 0 ==
6922 22:55:51.074389 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6923 22:55:51.077797 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6924 22:55:51.081111 == TX Byte 1 ==
6925 22:55:51.084008 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6926 22:55:51.087354 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6927 22:55:51.087437
6928 22:55:51.090813 [DATLAT]
6929 22:55:51.090903 Freq=400, CH1 RK1
6930 22:55:51.090970
6931 22:55:51.094041 DATLAT Default: 0xe
6932 22:55:51.094124 0, 0xFFFF, sum = 0
6933 22:55:51.097329 1, 0xFFFF, sum = 0
6934 22:55:51.097413 2, 0xFFFF, sum = 0
6935 22:55:51.100696 3, 0xFFFF, sum = 0
6936 22:55:51.100780 4, 0xFFFF, sum = 0
6937 22:55:51.103912 5, 0xFFFF, sum = 0
6938 22:55:51.103997 6, 0xFFFF, sum = 0
6939 22:55:51.107336 7, 0xFFFF, sum = 0
6940 22:55:51.110524 8, 0xFFFF, sum = 0
6941 22:55:51.110608 9, 0xFFFF, sum = 0
6942 22:55:51.113728 10, 0xFFFF, sum = 0
6943 22:55:51.113812 11, 0xFFFF, sum = 0
6944 22:55:51.117054 12, 0xFFFF, sum = 0
6945 22:55:51.117138 13, 0x0, sum = 1
6946 22:55:51.120610 14, 0x0, sum = 2
6947 22:55:51.120695 15, 0x0, sum = 3
6948 22:55:51.123777 16, 0x0, sum = 4
6949 22:55:51.123862 best_step = 14
6950 22:55:51.123928
6951 22:55:51.123989 ==
6952 22:55:51.126798 Dram Type= 6, Freq= 0, CH_1, rank 1
6953 22:55:51.130424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6954 22:55:51.130508 ==
6955 22:55:51.133848 RX Vref Scan: 0
6956 22:55:51.133931
6957 22:55:51.137164 RX Vref 0 -> 0, step: 1
6958 22:55:51.137246
6959 22:55:51.137313 RX Delay -359 -> 252, step: 8
6960 22:55:51.145905 iDelay=217, Bit 0, Center -40 (-287 ~ 208) 496
6961 22:55:51.149538 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6962 22:55:51.152782 iDelay=217, Bit 2, Center -56 (-303 ~ 192) 496
6963 22:55:51.156006 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6964 22:55:51.162227 iDelay=217, Bit 4, Center -44 (-295 ~ 208) 504
6965 22:55:51.166024 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6966 22:55:51.169212 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6967 22:55:51.175404 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6968 22:55:51.178758 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6969 22:55:51.182153 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6970 22:55:51.185518 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6971 22:55:51.191852 iDelay=217, Bit 11, Center -60 (-319 ~ 200) 520
6972 22:55:51.195281 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6973 22:55:51.198534 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6974 22:55:51.201768 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6975 22:55:51.208372 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6976 22:55:51.208455 ==
6977 22:55:51.212057 Dram Type= 6, Freq= 0, CH_1, rank 1
6978 22:55:51.215614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6979 22:55:51.215698 ==
6980 22:55:51.215762 DQS Delay:
6981 22:55:51.218814 DQS0 = 56, DQS1 = 64
6982 22:55:51.218905 DQM Delay:
6983 22:55:51.222181 DQM0 = 10, DQM1 = 10
6984 22:55:51.222263 DQ Delay:
6985 22:55:51.225295 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6986 22:55:51.228551 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =4
6987 22:55:51.231768 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6988 22:55:51.234903 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6989 22:55:51.234985
6990 22:55:51.235050
6991 22:55:51.245036 [DQSOSCAuto] RK1, (LSB)MR18= 0x78a9, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
6992 22:55:51.245137 CH1 RK1: MR19=C0C, MR18=78A9
6993 22:55:51.251606 CH1_RK1: MR19=0xC0C, MR18=0x78A9, DQSOSC=388, MR23=63, INC=392, DEC=261
6994 22:55:51.254665 [RxdqsGatingPostProcess] freq 400
6995 22:55:51.261194 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6996 22:55:51.265002 best DQS0 dly(2T, 0.5T) = (0, 10)
6997 22:55:51.267873 best DQS1 dly(2T, 0.5T) = (0, 10)
6998 22:55:51.270954 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6999 22:55:51.274709 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7000 22:55:51.277507 best DQS0 dly(2T, 0.5T) = (0, 10)
7001 22:55:51.277591 best DQS1 dly(2T, 0.5T) = (0, 10)
7002 22:55:51.280934 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7003 22:55:51.284283 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7004 22:55:51.287645 Pre-setting of DQS Precalculation
7005 22:55:51.293882 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7006 22:55:51.300709 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7007 22:55:51.307369 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7008 22:55:51.307453
7009 22:55:51.307518
7010 22:55:51.310587 [Calibration Summary] 800 Mbps
7011 22:55:51.314003 CH 0, Rank 0
7012 22:55:51.314086 SW Impedance : PASS
7013 22:55:51.317299 DUTY Scan : NO K
7014 22:55:51.320542 ZQ Calibration : PASS
7015 22:55:51.320625 Jitter Meter : NO K
7016 22:55:51.324298 CBT Training : PASS
7017 22:55:51.327106 Write leveling : PASS
7018 22:55:51.327212 RX DQS gating : PASS
7019 22:55:51.330403 RX DQ/DQS(RDDQC) : PASS
7020 22:55:51.330485 TX DQ/DQS : PASS
7021 22:55:51.333888 RX DATLAT : PASS
7022 22:55:51.337083 RX DQ/DQS(Engine): PASS
7023 22:55:51.337166 TX OE : NO K
7024 22:55:51.340145 All Pass.
7025 22:55:51.340228
7026 22:55:51.340293 CH 0, Rank 1
7027 22:55:51.343665 SW Impedance : PASS
7028 22:55:51.343752 DUTY Scan : NO K
7029 22:55:51.346730 ZQ Calibration : PASS
7030 22:55:51.350490 Jitter Meter : NO K
7031 22:55:51.350580 CBT Training : PASS
7032 22:55:51.353264 Write leveling : NO K
7033 22:55:51.356902 RX DQS gating : PASS
7034 22:55:51.356995 RX DQ/DQS(RDDQC) : PASS
7035 22:55:51.359938 TX DQ/DQS : PASS
7036 22:55:51.363613 RX DATLAT : PASS
7037 22:55:51.363711 RX DQ/DQS(Engine): PASS
7038 22:55:51.366970 TX OE : NO K
7039 22:55:51.367062 All Pass.
7040 22:55:51.367129
7041 22:55:51.369992 CH 1, Rank 0
7042 22:55:51.370076 SW Impedance : PASS
7043 22:55:51.372823 DUTY Scan : NO K
7044 22:55:51.376496 ZQ Calibration : PASS
7045 22:55:51.376580 Jitter Meter : NO K
7046 22:55:51.380063 CBT Training : PASS
7047 22:55:51.383072 Write leveling : PASS
7048 22:55:51.383156 RX DQS gating : PASS
7049 22:55:51.386308 RX DQ/DQS(RDDQC) : PASS
7050 22:55:51.389727 TX DQ/DQS : PASS
7051 22:55:51.389811 RX DATLAT : PASS
7052 22:55:51.393049 RX DQ/DQS(Engine): PASS
7053 22:55:51.396274 TX OE : NO K
7054 22:55:51.396358 All Pass.
7055 22:55:51.396424
7056 22:55:51.396486 CH 1, Rank 1
7057 22:55:51.399115 SW Impedance : PASS
7058 22:55:51.402407 DUTY Scan : NO K
7059 22:55:51.402490 ZQ Calibration : PASS
7060 22:55:51.405928 Jitter Meter : NO K
7061 22:55:51.409136 CBT Training : PASS
7062 22:55:51.409219 Write leveling : NO K
7063 22:55:51.412859 RX DQS gating : PASS
7064 22:55:51.415720 RX DQ/DQS(RDDQC) : PASS
7065 22:55:51.415803 TX DQ/DQS : PASS
7066 22:55:51.419232 RX DATLAT : PASS
7067 22:55:51.419314 RX DQ/DQS(Engine): PASS
7068 22:55:51.422607 TX OE : NO K
7069 22:55:51.422691 All Pass.
7070 22:55:51.422757
7071 22:55:51.425902 DramC Write-DBI off
7072 22:55:51.429004 PER_BANK_REFRESH: Hybrid Mode
7073 22:55:51.429087 TX_TRACKING: ON
7074 22:55:51.439595 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7075 22:55:51.442416 [FAST_K] Save calibration result to emmc
7076 22:55:51.445447 dramc_set_vcore_voltage set vcore to 725000
7077 22:55:51.448941 Read voltage for 1600, 0
7078 22:55:51.449025 Vio18 = 0
7079 22:55:51.451872 Vcore = 725000
7080 22:55:51.451956 Vdram = 0
7081 22:55:51.452022 Vddq = 0
7082 22:55:51.452082 Vmddr = 0
7083 22:55:51.458459 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7084 22:55:51.465042 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7085 22:55:51.465192 MEM_TYPE=3, freq_sel=13
7086 22:55:51.468752 sv_algorithm_assistance_LP4_3733
7087 22:55:51.475143 ============ PULL DRAM RESETB DOWN ============
7088 22:55:51.478599 ========== PULL DRAM RESETB DOWN end =========
7089 22:55:51.481830 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7090 22:55:51.484845 ===================================
7091 22:55:51.488040 LPDDR4 DRAM CONFIGURATION
7092 22:55:51.491542 ===================================
7093 22:55:51.491626 EX_ROW_EN[0] = 0x0
7094 22:55:51.494993 EX_ROW_EN[1] = 0x0
7095 22:55:51.497804 LP4Y_EN = 0x0
7096 22:55:51.497886 WORK_FSP = 0x1
7097 22:55:51.501259 WL = 0x5
7098 22:55:51.501342 RL = 0x5
7099 22:55:51.504686 BL = 0x2
7100 22:55:51.504768 RPST = 0x0
7101 22:55:51.507967 RD_PRE = 0x0
7102 22:55:51.508050 WR_PRE = 0x1
7103 22:55:51.511400 WR_PST = 0x1
7104 22:55:51.511482 DBI_WR = 0x0
7105 22:55:51.514165 DBI_RD = 0x0
7106 22:55:51.514247 OTF = 0x1
7107 22:55:51.517379 ===================================
7108 22:55:51.520985 ===================================
7109 22:55:51.524437 ANA top config
7110 22:55:51.527515 ===================================
7111 22:55:51.530592 DLL_ASYNC_EN = 0
7112 22:55:51.530674 ALL_SLAVE_EN = 0
7113 22:55:51.533812 NEW_RANK_MODE = 1
7114 22:55:51.537078 DLL_IDLE_MODE = 1
7115 22:55:51.540728 LP45_APHY_COMB_EN = 1
7116 22:55:51.543659 TX_ODT_DIS = 0
7117 22:55:51.543789 NEW_8X_MODE = 1
7118 22:55:51.547358 ===================================
7119 22:55:51.550457 ===================================
7120 22:55:51.554179 data_rate = 3200
7121 22:55:51.557229 CKR = 1
7122 22:55:51.560260 DQ_P2S_RATIO = 8
7123 22:55:51.563951 ===================================
7124 22:55:51.566974 CA_P2S_RATIO = 8
7125 22:55:51.570257 DQ_CA_OPEN = 0
7126 22:55:51.570339 DQ_SEMI_OPEN = 0
7127 22:55:51.573481 CA_SEMI_OPEN = 0
7128 22:55:51.576982 CA_FULL_RATE = 0
7129 22:55:51.580132 DQ_CKDIV4_EN = 0
7130 22:55:51.583564 CA_CKDIV4_EN = 0
7131 22:55:51.586671 CA_PREDIV_EN = 0
7132 22:55:51.586754 PH8_DLY = 12
7133 22:55:51.589893 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7134 22:55:51.593512 DQ_AAMCK_DIV = 4
7135 22:55:51.596613 CA_AAMCK_DIV = 4
7136 22:55:51.600248 CA_ADMCK_DIV = 4
7137 22:55:51.603354 DQ_TRACK_CA_EN = 0
7138 22:55:51.606724 CA_PICK = 1600
7139 22:55:51.606806 CA_MCKIO = 1600
7140 22:55:51.610234 MCKIO_SEMI = 0
7141 22:55:51.613010 PLL_FREQ = 3068
7142 22:55:51.616504 DQ_UI_PI_RATIO = 32
7143 22:55:51.619524 CA_UI_PI_RATIO = 0
7144 22:55:51.622985 ===================================
7145 22:55:51.626397 ===================================
7146 22:55:51.629778 memory_type:LPDDR4
7147 22:55:51.629861 GP_NUM : 10
7148 22:55:51.633080 SRAM_EN : 1
7149 22:55:51.633162 MD32_EN : 0
7150 22:55:51.636247 ===================================
7151 22:55:51.639724 [ANA_INIT] >>>>>>>>>>>>>>
7152 22:55:51.642989 <<<<<< [CONFIGURE PHASE]: ANA_TX
7153 22:55:51.646569 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7154 22:55:51.649380 ===================================
7155 22:55:51.652879 data_rate = 3200,PCW = 0X7600
7156 22:55:51.656196 ===================================
7157 22:55:51.659335 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7158 22:55:51.666129 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7159 22:55:51.669267 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7160 22:55:51.675719 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7161 22:55:51.679368 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7162 22:55:51.682605 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7163 22:55:51.682689 [ANA_INIT] flow start
7164 22:55:51.685857 [ANA_INIT] PLL >>>>>>>>
7165 22:55:51.688652 [ANA_INIT] PLL <<<<<<<<
7166 22:55:51.692518 [ANA_INIT] MIDPI >>>>>>>>
7167 22:55:51.692602 [ANA_INIT] MIDPI <<<<<<<<
7168 22:55:51.695559 [ANA_INIT] DLL >>>>>>>>
7169 22:55:51.698742 [ANA_INIT] DLL <<<<<<<<
7170 22:55:51.698825 [ANA_INIT] flow end
7171 22:55:51.702708 ============ LP4 DIFF to SE enter ============
7172 22:55:51.708501 ============ LP4 DIFF to SE exit ============
7173 22:55:51.708585 [ANA_INIT] <<<<<<<<<<<<<
7174 22:55:51.711811 [Flow] Enable top DCM control >>>>>
7175 22:55:51.715027 [Flow] Enable top DCM control <<<<<
7176 22:55:51.718491 Enable DLL master slave shuffle
7177 22:55:51.725065 ==============================================================
7178 22:55:51.728383 Gating Mode config
7179 22:55:51.731673 ==============================================================
7180 22:55:51.734977 Config description:
7181 22:55:51.745144 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7182 22:55:51.751247 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7183 22:55:51.754981 SELPH_MODE 0: By rank 1: By Phase
7184 22:55:51.761611 ==============================================================
7185 22:55:51.764849 GAT_TRACK_EN = 1
7186 22:55:51.767849 RX_GATING_MODE = 2
7187 22:55:51.771520 RX_GATING_TRACK_MODE = 2
7188 22:55:51.774665 SELPH_MODE = 1
7189 22:55:51.774759 PICG_EARLY_EN = 1
7190 22:55:51.777769 VALID_LAT_VALUE = 1
7191 22:55:51.784351 ==============================================================
7192 22:55:51.787566 Enter into Gating configuration >>>>
7193 22:55:51.791224 Exit from Gating configuration <<<<
7194 22:55:51.794350 Enter into DVFS_PRE_config >>>>>
7195 22:55:51.804247 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7196 22:55:51.808170 Exit from DVFS_PRE_config <<<<<
7197 22:55:51.811171 Enter into PICG configuration >>>>
7198 22:55:51.814252 Exit from PICG configuration <<<<
7199 22:55:51.818164 [RX_INPUT] configuration >>>>>
7200 22:55:51.820736 [RX_INPUT] configuration <<<<<
7201 22:55:51.824372 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7202 22:55:51.831042 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7203 22:55:51.837505 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7204 22:55:51.844443 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7205 22:55:51.850467 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7206 22:55:51.857279 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7207 22:55:51.860727 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7208 22:55:51.863827 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7209 22:55:51.867363 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7210 22:55:51.873616 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7211 22:55:51.877254 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7212 22:55:51.880473 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7213 22:55:51.883431 ===================================
7214 22:55:51.886603 LPDDR4 DRAM CONFIGURATION
7215 22:55:51.890256 ===================================
7216 22:55:51.890342 EX_ROW_EN[0] = 0x0
7217 22:55:51.893364 EX_ROW_EN[1] = 0x0
7218 22:55:51.896780 LP4Y_EN = 0x0
7219 22:55:51.896865 WORK_FSP = 0x1
7220 22:55:51.899681 WL = 0x5
7221 22:55:51.899768 RL = 0x5
7222 22:55:51.903226 BL = 0x2
7223 22:55:51.903308 RPST = 0x0
7224 22:55:51.906817 RD_PRE = 0x0
7225 22:55:51.906945 WR_PRE = 0x1
7226 22:55:51.910450 WR_PST = 0x1
7227 22:55:51.910532 DBI_WR = 0x0
7228 22:55:51.913129 DBI_RD = 0x0
7229 22:55:51.913217 OTF = 0x1
7230 22:55:51.916331 ===================================
7231 22:55:51.919763 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7232 22:55:51.926552 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7233 22:55:51.929867 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7234 22:55:51.932721 ===================================
7235 22:55:51.936083 LPDDR4 DRAM CONFIGURATION
7236 22:55:51.939556 ===================================
7237 22:55:51.939639 EX_ROW_EN[0] = 0x10
7238 22:55:51.943018 EX_ROW_EN[1] = 0x0
7239 22:55:51.946312 LP4Y_EN = 0x0
7240 22:55:51.946394 WORK_FSP = 0x1
7241 22:55:51.949075 WL = 0x5
7242 22:55:51.949158 RL = 0x5
7243 22:55:51.953084 BL = 0x2
7244 22:55:51.953167 RPST = 0x0
7245 22:55:51.955880 RD_PRE = 0x0
7246 22:55:51.955962 WR_PRE = 0x1
7247 22:55:51.959482 WR_PST = 0x1
7248 22:55:51.959564 DBI_WR = 0x0
7249 22:55:51.962625 DBI_RD = 0x0
7250 22:55:51.962707 OTF = 0x1
7251 22:55:51.965985 ===================================
7252 22:55:51.972845 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7253 22:55:51.972928 ==
7254 22:55:51.976166 Dram Type= 6, Freq= 0, CH_0, rank 0
7255 22:55:51.979172 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7256 22:55:51.982605 ==
7257 22:55:51.982687 [Duty_Offset_Calibration]
7258 22:55:51.985700 B0:2 B1:0 CA:3
7259 22:55:51.985783
7260 22:55:51.988875 [DutyScan_Calibration_Flow] k_type=0
7261 22:55:51.997853
7262 22:55:51.997937 ==CLK 0==
7263 22:55:52.001446 Final CLK duty delay cell = 0
7264 22:55:52.004543 [0] MAX Duty = 5031%(X100), DQS PI = 12
7265 22:55:52.008101 [0] MIN Duty = 4907%(X100), DQS PI = 4
7266 22:55:52.011091 [0] AVG Duty = 4969%(X100)
7267 22:55:52.011173
7268 22:55:52.014365 CH0 CLK Duty spec in!! Max-Min= 124%
7269 22:55:52.017706 [DutyScan_Calibration_Flow] ====Done====
7270 22:55:52.017788
7271 22:55:52.021104 [DutyScan_Calibration_Flow] k_type=1
7272 22:55:52.038139
7273 22:55:52.038223 ==DQS 0 ==
7274 22:55:52.041523 Final DQS duty delay cell = 0
7275 22:55:52.044439 [0] MAX Duty = 5125%(X100), DQS PI = 32
7276 22:55:52.047815 [0] MIN Duty = 4875%(X100), DQS PI = 50
7277 22:55:52.051088 [0] AVG Duty = 5000%(X100)
7278 22:55:52.051170
7279 22:55:52.051235 ==DQS 1 ==
7280 22:55:52.054348 Final DQS duty delay cell = 0
7281 22:55:52.057813 [0] MAX Duty = 5156%(X100), DQS PI = 32
7282 22:55:52.061225 [0] MIN Duty = 5062%(X100), DQS PI = 0
7283 22:55:52.064652 [0] AVG Duty = 5109%(X100)
7284 22:55:52.064735
7285 22:55:52.067630 CH0 DQS 0 Duty spec in!! Max-Min= 250%
7286 22:55:52.067714
7287 22:55:52.070776 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7288 22:55:52.074018 [DutyScan_Calibration_Flow] ====Done====
7289 22:55:52.074121
7290 22:55:52.077236 [DutyScan_Calibration_Flow] k_type=3
7291 22:55:52.095193
7292 22:55:52.095280 ==DQM 0 ==
7293 22:55:52.098758 Final DQM duty delay cell = 0
7294 22:55:52.101998 [0] MAX Duty = 5156%(X100), DQS PI = 30
7295 22:55:52.105239 [0] MIN Duty = 4844%(X100), DQS PI = 50
7296 22:55:52.108400 [0] AVG Duty = 5000%(X100)
7297 22:55:52.108481
7298 22:55:52.108544 ==DQM 1 ==
7299 22:55:52.111852 Final DQM duty delay cell = 0
7300 22:55:52.115001 [0] MAX Duty = 4969%(X100), DQS PI = 62
7301 22:55:52.118364 [0] MIN Duty = 4813%(X100), DQS PI = 20
7302 22:55:52.121309 [0] AVG Duty = 4891%(X100)
7303 22:55:52.121390
7304 22:55:52.124687 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7305 22:55:52.124769
7306 22:55:52.127977 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7307 22:55:52.131238 [DutyScan_Calibration_Flow] ====Done====
7308 22:55:52.131318
7309 22:55:52.134527 [DutyScan_Calibration_Flow] k_type=2
7310 22:55:52.151355
7311 22:55:52.151453 ==DQ 0 ==
7312 22:55:52.154549 Final DQ duty delay cell = -4
7313 22:55:52.158119 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7314 22:55:52.161350 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7315 22:55:52.164695 [-4] AVG Duty = 4938%(X100)
7316 22:55:52.164776
7317 22:55:52.164840 ==DQ 1 ==
7318 22:55:52.168005 Final DQ duty delay cell = 0
7319 22:55:52.171544 [0] MAX Duty = 5156%(X100), DQS PI = 60
7320 22:55:52.174418 [0] MIN Duty = 5000%(X100), DQS PI = 16
7321 22:55:52.178122 [0] AVG Duty = 5078%(X100)
7322 22:55:52.178224
7323 22:55:52.181426 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7324 22:55:52.181506
7325 22:55:52.184725 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7326 22:55:52.188109 [DutyScan_Calibration_Flow] ====Done====
7327 22:55:52.188194 ==
7328 22:55:52.191076 Dram Type= 6, Freq= 0, CH_1, rank 0
7329 22:55:52.194315 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7330 22:55:52.194396 ==
7331 22:55:52.197895 [Duty_Offset_Calibration]
7332 22:55:52.197976 B0:1 B1:-2 CA:1
7333 22:55:52.198039
7334 22:55:52.201181 [DutyScan_Calibration_Flow] k_type=0
7335 22:55:52.211923
7336 22:55:52.212011 ==CLK 0==
7337 22:55:52.215179 Final CLK duty delay cell = 0
7338 22:55:52.219170 [0] MAX Duty = 5094%(X100), DQS PI = 22
7339 22:55:52.222154 [0] MIN Duty = 4844%(X100), DQS PI = 4
7340 22:55:52.225483 [0] AVG Duty = 4969%(X100)
7341 22:55:52.225565
7342 22:55:52.228518 CH1 CLK Duty spec in!! Max-Min= 250%
7343 22:55:52.231722 [DutyScan_Calibration_Flow] ====Done====
7344 22:55:52.231802
7345 22:55:52.235050 [DutyScan_Calibration_Flow] k_type=1
7346 22:55:52.250796
7347 22:55:52.250925 ==DQS 0 ==
7348 22:55:52.254505 Final DQS duty delay cell = -4
7349 22:55:52.257814 [-4] MAX Duty = 4969%(X100), DQS PI = 26
7350 22:55:52.260799 [-4] MIN Duty = 4844%(X100), DQS PI = 46
7351 22:55:52.264201 [-4] AVG Duty = 4906%(X100)
7352 22:55:52.264283
7353 22:55:52.264349 ==DQS 1 ==
7354 22:55:52.267714 Final DQS duty delay cell = 0
7355 22:55:52.270456 [0] MAX Duty = 5093%(X100), DQS PI = 58
7356 22:55:52.273850 [0] MIN Duty = 4844%(X100), DQS PI = 26
7357 22:55:52.277236 [0] AVG Duty = 4968%(X100)
7358 22:55:52.277318
7359 22:55:52.280476 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7360 22:55:52.280558
7361 22:55:52.283850 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7362 22:55:52.287165 [DutyScan_Calibration_Flow] ====Done====
7363 22:55:52.287246
7364 22:55:52.290025 [DutyScan_Calibration_Flow] k_type=3
7365 22:55:52.308165
7366 22:55:52.308252 ==DQM 0 ==
7367 22:55:52.311589 Final DQM duty delay cell = 0
7368 22:55:52.314937 [0] MAX Duty = 5031%(X100), DQS PI = 26
7369 22:55:52.318224 [0] MIN Duty = 4813%(X100), DQS PI = 54
7370 22:55:52.321409 [0] AVG Duty = 4922%(X100)
7371 22:55:52.321493
7372 22:55:52.321558 ==DQM 1 ==
7373 22:55:52.324945 Final DQM duty delay cell = 0
7374 22:55:52.328162 [0] MAX Duty = 5062%(X100), DQS PI = 34
7375 22:55:52.331327 [0] MIN Duty = 4875%(X100), DQS PI = 24
7376 22:55:52.334772 [0] AVG Duty = 4968%(X100)
7377 22:55:52.334893
7378 22:55:52.338050 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7379 22:55:52.338138
7380 22:55:52.341090 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7381 22:55:52.344988 [DutyScan_Calibration_Flow] ====Done====
7382 22:55:52.345072
7383 22:55:52.347826 [DutyScan_Calibration_Flow] k_type=2
7384 22:55:52.365226
7385 22:55:52.365321 ==DQ 0 ==
7386 22:55:52.368651 Final DQ duty delay cell = 0
7387 22:55:52.372063 [0] MAX Duty = 5093%(X100), DQS PI = 20
7388 22:55:52.374822 [0] MIN Duty = 4907%(X100), DQS PI = 62
7389 22:55:52.374945 [0] AVG Duty = 5000%(X100)
7390 22:55:52.378236
7391 22:55:52.378319 ==DQ 1 ==
7392 22:55:52.381553 Final DQ duty delay cell = 0
7393 22:55:52.384874 [0] MAX Duty = 5125%(X100), DQS PI = 34
7394 22:55:52.388545 [0] MIN Duty = 4969%(X100), DQS PI = 24
7395 22:55:52.388628 [0] AVG Duty = 5047%(X100)
7396 22:55:52.391489
7397 22:55:52.394845 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7398 22:55:52.394928
7399 22:55:52.398234 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7400 22:55:52.401594 [DutyScan_Calibration_Flow] ====Done====
7401 22:55:52.405135 nWR fixed to 30
7402 22:55:52.407794 [ModeRegInit_LP4] CH0 RK0
7403 22:55:52.407877 [ModeRegInit_LP4] CH0 RK1
7404 22:55:52.411395 [ModeRegInit_LP4] CH1 RK0
7405 22:55:52.414991 [ModeRegInit_LP4] CH1 RK1
7406 22:55:52.415073 match AC timing 5
7407 22:55:52.421175 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7408 22:55:52.424470 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7409 22:55:52.427536 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7410 22:55:52.434200 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7411 22:55:52.437713 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7412 22:55:52.437796 [MiockJmeterHQA]
7413 22:55:52.437862
7414 22:55:52.440608 [DramcMiockJmeter] u1RxGatingPI = 0
7415 22:55:52.443852 0 : 4363, 4137
7416 22:55:52.443937 4 : 4253, 4026
7417 22:55:52.447588 8 : 4368, 4140
7418 22:55:52.447673 12 : 4368, 4137
7419 22:55:52.450791 16 : 4255, 4027
7420 22:55:52.450906 20 : 4368, 4140
7421 22:55:52.450973 24 : 4252, 4027
7422 22:55:52.453989 28 : 4253, 4027
7423 22:55:52.454071 32 : 4254, 4027
7424 22:55:52.457860 36 : 4255, 4027
7425 22:55:52.457943 40 : 4363, 4137
7426 22:55:52.460414 44 : 4260, 4030
7427 22:55:52.460497 48 : 4366, 4138
7428 22:55:52.463818 52 : 4255, 4027
7429 22:55:52.463902 56 : 4255, 4027
7430 22:55:52.463966 60 : 4252, 4027
7431 22:55:52.467056 64 : 4365, 4137
7432 22:55:52.467139 68 : 4363, 4137
7433 22:55:52.470392 72 : 4257, 4029
7434 22:55:52.470474 76 : 4257, 4030
7435 22:55:52.473764 80 : 4257, 4029
7436 22:55:52.473846 84 : 4257, 4029
7437 22:55:52.477157 88 : 4253, 4027
7438 22:55:52.477239 92 : 4363, 4137
7439 22:55:52.477304 96 : 4257, 4030
7440 22:55:52.480520 100 : 4363, 4137
7441 22:55:52.480603 104 : 4363, 3821
7442 22:55:52.483992 108 : 4257, 4
7443 22:55:52.484074 112 : 4252, 0
7444 22:55:52.486775 116 : 4253, 0
7445 22:55:52.486866 120 : 4365, 0
7446 22:55:52.486949 124 : 4363, 0
7447 22:55:52.490581 128 : 4363, 0
7448 22:55:52.490665 132 : 4257, 0
7449 22:55:52.493402 136 : 4362, 0
7450 22:55:52.493487 140 : 4253, 0
7451 22:55:52.493555 144 : 4254, 0
7452 22:55:52.496696 148 : 4257, 0
7453 22:55:52.496781 152 : 4252, 0
7454 22:55:52.500015 156 : 4253, 0
7455 22:55:52.500105 160 : 4257, 0
7456 22:55:52.500175 164 : 4252, 0
7457 22:55:52.503373 168 : 4253, 0
7458 22:55:52.503458 172 : 4368, 0
7459 22:55:52.503525 176 : 4363, 0
7460 22:55:52.506705 180 : 4363, 0
7461 22:55:52.506789 184 : 4257, 0
7462 22:55:52.509985 188 : 4257, 0
7463 22:55:52.510068 192 : 4363, 0
7464 22:55:52.510135 196 : 4252, 0
7465 22:55:52.513238 200 : 4257, 0
7466 22:55:52.513322 204 : 4252, 0
7467 22:55:52.516725 208 : 4253, 0
7468 22:55:52.516809 212 : 4257, 0
7469 22:55:52.516877 216 : 4253, 0
7470 22:55:52.520067 220 : 4253, 0
7471 22:55:52.520152 224 : 4368, 0
7472 22:55:52.523462 228 : 4363, 0
7473 22:55:52.523546 232 : 4250, 0
7474 22:55:52.523613 236 : 4257, 1096
7475 22:55:52.526763 240 : 4253, 4027
7476 22:55:52.526868 244 : 4255, 4029
7477 22:55:52.530152 248 : 4366, 4140
7478 22:55:52.530236 252 : 4365, 4137
7479 22:55:52.533122 256 : 4252, 4026
7480 22:55:52.533206 260 : 4363, 4138
7481 22:55:52.536202 264 : 4363, 4137
7482 22:55:52.536287 268 : 4257, 4029
7483 22:55:52.539765 272 : 4257, 4030
7484 22:55:52.539849 276 : 4363, 4138
7485 22:55:52.542779 280 : 4252, 4027
7486 22:55:52.542899 284 : 4257, 4029
7487 22:55:52.546068 288 : 4257, 4030
7488 22:55:52.546178 292 : 4260, 4031
7489 22:55:52.549447 296 : 4252, 4026
7490 22:55:52.549531 300 : 4257, 4029
7491 22:55:52.552607 304 : 4368, 4140
7492 22:55:52.552691 308 : 4253, 4027
7493 22:55:52.552767 312 : 4368, 4139
7494 22:55:52.555771 316 : 4363, 4137
7495 22:55:52.555855 320 : 4257, 4029
7496 22:55:52.559171 324 : 4257, 4030
7497 22:55:52.559256 328 : 4255, 4029
7498 22:55:52.562993 332 : 4252, 4026
7499 22:55:52.563078 336 : 4257, 4029
7500 22:55:52.566073 340 : 4257, 4030
7501 22:55:52.566157 344 : 4253, 4027
7502 22:55:52.569223 348 : 4252, 4026
7503 22:55:52.569307 352 : 4257, 4026
7504 22:55:52.572468 356 : 4368, 3041
7505 22:55:52.572553 360 : 4253, 1
7506 22:55:52.572620
7507 22:55:52.575731 MIOCK jitter meter ch=0
7508 22:55:52.575814
7509 22:55:52.579161 1T = (360-108) = 252 dly cells
7510 22:55:52.582536 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7511 22:55:52.582619 ==
7512 22:55:52.585345 Dram Type= 6, Freq= 0, CH_0, rank 0
7513 22:55:52.592032 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7514 22:55:52.592120 ==
7515 22:55:52.595263 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7516 22:55:52.601867 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7517 22:55:52.605196 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7518 22:55:52.611745 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7519 22:55:52.620204 [CA 0] Center 44 (14~75) winsize 62
7520 22:55:52.623558 [CA 1] Center 43 (13~74) winsize 62
7521 22:55:52.627055 [CA 2] Center 39 (10~69) winsize 60
7522 22:55:52.630096 [CA 3] Center 39 (10~68) winsize 59
7523 22:55:52.633196 [CA 4] Center 37 (8~67) winsize 60
7524 22:55:52.636387 [CA 5] Center 37 (7~67) winsize 61
7525 22:55:52.636471
7526 22:55:52.639714 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7527 22:55:52.643029
7528 22:55:52.646199 [CATrainingPosCal] consider 1 rank data
7529 22:55:52.649308 u2DelayCellTimex100 = 258/100 ps
7530 22:55:52.652678 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7531 22:55:52.656682 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7532 22:55:52.659344 CA2 delay=39 (10~69),Diff = 2 PI (7 cell)
7533 22:55:52.662540 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7534 22:55:52.665863 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7535 22:55:52.669187 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7536 22:55:52.669262
7537 22:55:52.672688 CA PerBit enable=1, Macro0, CA PI delay=37
7538 22:55:52.675770
7539 22:55:52.675843 [CBTSetCACLKResult] CA Dly = 37
7540 22:55:52.679179 CS Dly: 11 (0~42)
7541 22:55:52.682518 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7542 22:55:52.686008 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7543 22:55:52.689262 ==
7544 22:55:52.692517 Dram Type= 6, Freq= 0, CH_0, rank 1
7545 22:55:52.695941 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7546 22:55:52.696038 ==
7547 22:55:52.699145 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7548 22:55:52.706068 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7549 22:55:52.709119 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7550 22:55:52.715783 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7551 22:55:52.723843 [CA 0] Center 44 (13~75) winsize 63
7552 22:55:52.727236 [CA 1] Center 43 (13~74) winsize 62
7553 22:55:52.730237 [CA 2] Center 39 (10~68) winsize 59
7554 22:55:52.733990 [CA 3] Center 39 (10~68) winsize 59
7555 22:55:52.737097 [CA 4] Center 37 (8~66) winsize 59
7556 22:55:52.740662 [CA 5] Center 37 (8~66) winsize 59
7557 22:55:52.740772
7558 22:55:52.743485 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7559 22:55:52.743587
7560 22:55:52.750245 [CATrainingPosCal] consider 2 rank data
7561 22:55:52.750350 u2DelayCellTimex100 = 258/100 ps
7562 22:55:52.756934 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7563 22:55:52.760702 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7564 22:55:52.763575 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7565 22:55:52.766815 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7566 22:55:52.770114 CA4 delay=37 (8~66),Diff = 0 PI (0 cell)
7567 22:55:52.773612 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
7568 22:55:52.773695
7569 22:55:52.776842 CA PerBit enable=1, Macro0, CA PI delay=37
7570 22:55:52.776930
7571 22:55:52.779802 [CBTSetCACLKResult] CA Dly = 37
7572 22:55:52.783262 CS Dly: 11 (0~42)
7573 22:55:52.786563 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7574 22:55:52.789936 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7575 22:55:52.790020
7576 22:55:52.793319 ----->DramcWriteLeveling(PI) begin...
7577 22:55:52.796346 ==
7578 22:55:52.796429 Dram Type= 6, Freq= 0, CH_0, rank 0
7579 22:55:52.803234 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7580 22:55:52.803317 ==
7581 22:55:52.806166 Write leveling (Byte 0): 36 => 36
7582 22:55:52.809775 Write leveling (Byte 1): 28 => 28
7583 22:55:52.812844 DramcWriteLeveling(PI) end<-----
7584 22:55:52.812929
7585 22:55:52.812994 ==
7586 22:55:52.816391 Dram Type= 6, Freq= 0, CH_0, rank 0
7587 22:55:52.819512 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7588 22:55:52.819645 ==
7589 22:55:52.822772 [Gating] SW mode calibration
7590 22:55:52.829431 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7591 22:55:52.836463 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7592 22:55:52.839660 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 22:55:52.842667 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7594 22:55:52.849531 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7595 22:55:52.852562 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7596 22:55:52.855775 1 4 16 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7597 22:55:52.862415 1 4 20 | B1->B0 | 2525 3434 | 1 1 | (0 0) (1 1)
7598 22:55:52.866127 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7599 22:55:52.868829 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7600 22:55:52.875547 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7601 22:55:52.878944 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7602 22:55:52.882210 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7603 22:55:52.888865 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
7604 22:55:52.892311 1 5 16 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)
7605 22:55:52.895700 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7606 22:55:52.901906 1 5 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
7607 22:55:52.905379 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7608 22:55:52.908597 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7609 22:55:52.915193 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7610 22:55:52.918141 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7611 22:55:52.921379 1 6 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7612 22:55:52.928582 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7613 22:55:52.931485 1 6 20 | B1->B0 | 2a2a 4646 | 1 0 | (0 0) (0 0)
7614 22:55:52.934698 1 6 24 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
7615 22:55:52.941529 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7616 22:55:52.944843 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7617 22:55:52.948101 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7618 22:55:52.954600 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7619 22:55:52.958128 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7620 22:55:52.961128 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7621 22:55:52.967745 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7622 22:55:52.971345 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7623 22:55:52.974241 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 22:55:52.981445 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 22:55:52.984139 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 22:55:52.987862 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 22:55:52.994353 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 22:55:52.997330 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 22:55:53.000965 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 22:55:53.007264 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 22:55:53.010730 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 22:55:53.013960 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 22:55:53.020727 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 22:55:53.023735 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 22:55:53.026928 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7636 22:55:53.033651 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7637 22:55:53.036507 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7638 22:55:53.039909 Total UI for P1: 0, mck2ui 16
7639 22:55:53.043167 best dqsien dly found for B0: ( 1, 9, 14)
7640 22:55:53.046561 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7641 22:55:53.053212 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7642 22:55:53.053302 Total UI for P1: 0, mck2ui 16
7643 22:55:53.059752 best dqsien dly found for B1: ( 1, 9, 24)
7644 22:55:53.062924 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7645 22:55:53.066289 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7646 22:55:53.066373
7647 22:55:53.069779 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7648 22:55:53.072722 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7649 22:55:53.076511 [Gating] SW calibration Done
7650 22:55:53.076596 ==
7651 22:55:53.079418 Dram Type= 6, Freq= 0, CH_0, rank 0
7652 22:55:53.082654 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7653 22:55:53.082757 ==
7654 22:55:53.086067 RX Vref Scan: 0
7655 22:55:53.086151
7656 22:55:53.089407 RX Vref 0 -> 0, step: 1
7657 22:55:53.089516
7658 22:55:53.089617 RX Delay 0 -> 252, step: 8
7659 22:55:53.095716 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7660 22:55:53.099016 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7661 22:55:53.102750 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7662 22:55:53.105898 iDelay=192, Bit 3, Center 123 (64 ~ 183) 120
7663 22:55:53.108786 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7664 22:55:53.115490 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7665 22:55:53.119389 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7666 22:55:53.122285 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7667 22:55:53.125672 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7668 22:55:53.128675 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7669 22:55:53.135286 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7670 22:55:53.138545 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
7671 22:55:53.141940 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7672 22:55:53.145258 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7673 22:55:53.151790 iDelay=192, Bit 14, Center 131 (72 ~ 191) 120
7674 22:55:53.155221 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7675 22:55:53.155307 ==
7676 22:55:53.158575 Dram Type= 6, Freq= 0, CH_0, rank 0
7677 22:55:53.161732 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7678 22:55:53.161817 ==
7679 22:55:53.165175 DQS Delay:
7680 22:55:53.165258 DQS0 = 0, DQS1 = 0
7681 22:55:53.165343 DQM Delay:
7682 22:55:53.168809 DQM0 = 128, DQM1 = 123
7683 22:55:53.168893 DQ Delay:
7684 22:55:53.171778 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7685 22:55:53.175035 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
7686 22:55:53.178378 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7687 22:55:53.185330 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
7688 22:55:53.185414
7689 22:55:53.185498
7690 22:55:53.185577 ==
7691 22:55:53.188298 Dram Type= 6, Freq= 0, CH_0, rank 0
7692 22:55:53.191599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7693 22:55:53.191684 ==
7694 22:55:53.191768
7695 22:55:53.191847
7696 22:55:53.194718 TX Vref Scan disable
7697 22:55:53.194802 == TX Byte 0 ==
7698 22:55:53.201565 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7699 22:55:53.204771 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7700 22:55:53.204855 == TX Byte 1 ==
7701 22:55:53.211122 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7702 22:55:53.215042 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7703 22:55:53.215126 ==
7704 22:55:53.217759 Dram Type= 6, Freq= 0, CH_0, rank 0
7705 22:55:53.221550 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7706 22:55:53.221651 ==
7707 22:55:53.236375
7708 22:55:53.239714 TX Vref early break, caculate TX vref
7709 22:55:53.243073 TX Vref=16, minBit 8, minWin=21, winSum=361
7710 22:55:53.246324 TX Vref=18, minBit 8, minWin=22, winSum=371
7711 22:55:53.249710 TX Vref=20, minBit 8, minWin=23, winSum=385
7712 22:55:53.252527 TX Vref=22, minBit 4, minWin=24, winSum=395
7713 22:55:53.255744 TX Vref=24, minBit 4, minWin=24, winSum=399
7714 22:55:53.262473 TX Vref=26, minBit 11, minWin=24, winSum=408
7715 22:55:53.265772 TX Vref=28, minBit 15, minWin=24, winSum=409
7716 22:55:53.269008 TX Vref=30, minBit 9, minWin=23, winSum=400
7717 22:55:53.272426 TX Vref=32, minBit 8, minWin=23, winSum=394
7718 22:55:53.276009 TX Vref=34, minBit 8, minWin=22, winSum=385
7719 22:55:53.282571 [TxChooseVref] Worse bit 15, Min win 24, Win sum 409, Final Vref 28
7720 22:55:53.282656
7721 22:55:53.285897 Final TX Range 0 Vref 28
7722 22:55:53.285981
7723 22:55:53.286047 ==
7724 22:55:53.288718 Dram Type= 6, Freq= 0, CH_0, rank 0
7725 22:55:53.292318 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7726 22:55:53.292407 ==
7727 22:55:53.292473
7728 22:55:53.295537
7729 22:55:53.295620 TX Vref Scan disable
7730 22:55:53.301920 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7731 22:55:53.302005 == TX Byte 0 ==
7732 22:55:53.305153 u2DelayCellOfst[0]=15 cells (4 PI)
7733 22:55:53.308584 u2DelayCellOfst[1]=18 cells (5 PI)
7734 22:55:53.312153 u2DelayCellOfst[2]=15 cells (4 PI)
7735 22:55:53.315252 u2DelayCellOfst[3]=15 cells (4 PI)
7736 22:55:53.318350 u2DelayCellOfst[4]=7 cells (2 PI)
7737 22:55:53.321700 u2DelayCellOfst[5]=0 cells (0 PI)
7738 22:55:53.324864 u2DelayCellOfst[6]=22 cells (6 PI)
7739 22:55:53.328120 u2DelayCellOfst[7]=18 cells (5 PI)
7740 22:55:53.331558 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7741 22:55:53.334961 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7742 22:55:53.338174 == TX Byte 1 ==
7743 22:55:53.341380 u2DelayCellOfst[8]=0 cells (0 PI)
7744 22:55:53.344910 u2DelayCellOfst[9]=3 cells (1 PI)
7745 22:55:53.348069 u2DelayCellOfst[10]=7 cells (2 PI)
7746 22:55:53.351512 u2DelayCellOfst[11]=7 cells (2 PI)
7747 22:55:53.354415 u2DelayCellOfst[12]=11 cells (3 PI)
7748 22:55:53.357716 u2DelayCellOfst[13]=11 cells (3 PI)
7749 22:55:53.361043 u2DelayCellOfst[14]=15 cells (4 PI)
7750 22:55:53.364465 u2DelayCellOfst[15]=11 cells (3 PI)
7751 22:55:53.367942 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7752 22:55:53.370964 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7753 22:55:53.374479 DramC Write-DBI on
7754 22:55:53.374563 ==
7755 22:55:53.377477 Dram Type= 6, Freq= 0, CH_0, rank 0
7756 22:55:53.381283 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7757 22:55:53.381368 ==
7758 22:55:53.381471
7759 22:55:53.381533
7760 22:55:53.384443 TX Vref Scan disable
7761 22:55:53.387792 == TX Byte 0 ==
7762 22:55:53.390775 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7763 22:55:53.390897 == TX Byte 1 ==
7764 22:55:53.397211 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7765 22:55:53.397298 DramC Write-DBI off
7766 22:55:53.397364
7767 22:55:53.397425 [DATLAT]
7768 22:55:53.400314 Freq=1600, CH0 RK0
7769 22:55:53.400398
7770 22:55:53.403935 DATLAT Default: 0xf
7771 22:55:53.404017 0, 0xFFFF, sum = 0
7772 22:55:53.407118 1, 0xFFFF, sum = 0
7773 22:55:53.407203 2, 0xFFFF, sum = 0
7774 22:55:53.410494 3, 0xFFFF, sum = 0
7775 22:55:53.410579 4, 0xFFFF, sum = 0
7776 22:55:53.413746 5, 0xFFFF, sum = 0
7777 22:55:53.413831 6, 0xFFFF, sum = 0
7778 22:55:53.416990 7, 0xFFFF, sum = 0
7779 22:55:53.417075 8, 0xFFFF, sum = 0
7780 22:55:53.420450 9, 0xFFFF, sum = 0
7781 22:55:53.420536 10, 0xFFFF, sum = 0
7782 22:55:53.423417 11, 0xFFFF, sum = 0
7783 22:55:53.423501 12, 0xFFFF, sum = 0
7784 22:55:53.426563 13, 0xEFFF, sum = 0
7785 22:55:53.430442 14, 0x0, sum = 1
7786 22:55:53.430527 15, 0x0, sum = 2
7787 22:55:53.430595 16, 0x0, sum = 3
7788 22:55:53.433400 17, 0x0, sum = 4
7789 22:55:53.433485 best_step = 15
7790 22:55:53.433551
7791 22:55:53.436966 ==
7792 22:55:53.437049 Dram Type= 6, Freq= 0, CH_0, rank 0
7793 22:55:53.443007 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7794 22:55:53.443203 ==
7795 22:55:53.443334 RX Vref Scan: 1
7796 22:55:53.443396
7797 22:55:53.446403 Set Vref Range= 24 -> 127
7798 22:55:53.446513
7799 22:55:53.449733 RX Vref 24 -> 127, step: 1
7800 22:55:53.449810
7801 22:55:53.453075 RX Delay 11 -> 252, step: 4
7802 22:55:53.453150
7803 22:55:53.456608 Set Vref, RX VrefLevel [Byte0]: 24
7804 22:55:53.459946 [Byte1]: 24
7805 22:55:53.460032
7806 22:55:53.463044 Set Vref, RX VrefLevel [Byte0]: 25
7807 22:55:53.466426 [Byte1]: 25
7808 22:55:53.466503
7809 22:55:53.469289 Set Vref, RX VrefLevel [Byte0]: 26
7810 22:55:53.472710 [Byte1]: 26
7811 22:55:53.476599
7812 22:55:53.476682 Set Vref, RX VrefLevel [Byte0]: 27
7813 22:55:53.479879 [Byte1]: 27
7814 22:55:53.483911
7815 22:55:53.483994 Set Vref, RX VrefLevel [Byte0]: 28
7816 22:55:53.487282 [Byte1]: 28
7817 22:55:53.491603
7818 22:55:53.491686 Set Vref, RX VrefLevel [Byte0]: 29
7819 22:55:53.494740 [Byte1]: 29
7820 22:55:53.499242
7821 22:55:53.499326 Set Vref, RX VrefLevel [Byte0]: 30
7822 22:55:53.502784 [Byte1]: 30
7823 22:55:53.506881
7824 22:55:53.506965 Set Vref, RX VrefLevel [Byte0]: 31
7825 22:55:53.509943 [Byte1]: 31
7826 22:55:53.514662
7827 22:55:53.514772 Set Vref, RX VrefLevel [Byte0]: 32
7828 22:55:53.517977 [Byte1]: 32
7829 22:55:53.522336
7830 22:55:53.522420 Set Vref, RX VrefLevel [Byte0]: 33
7831 22:55:53.525704 [Byte1]: 33
7832 22:55:53.529737
7833 22:55:53.529820 Set Vref, RX VrefLevel [Byte0]: 34
7834 22:55:53.533096 [Byte1]: 34
7835 22:55:53.537307
7836 22:55:53.537390 Set Vref, RX VrefLevel [Byte0]: 35
7837 22:55:53.540497 [Byte1]: 35
7838 22:55:53.545071
7839 22:55:53.545154 Set Vref, RX VrefLevel [Byte0]: 36
7840 22:55:53.548298 [Byte1]: 36
7841 22:55:53.552367
7842 22:55:53.552446 Set Vref, RX VrefLevel [Byte0]: 37
7843 22:55:53.555857 [Byte1]: 37
7844 22:55:53.560428
7845 22:55:53.560503 Set Vref, RX VrefLevel [Byte0]: 38
7846 22:55:53.563230 [Byte1]: 38
7847 22:55:53.567967
7848 22:55:53.568074 Set Vref, RX VrefLevel [Byte0]: 39
7849 22:55:53.570993 [Byte1]: 39
7850 22:55:53.575351
7851 22:55:53.575433 Set Vref, RX VrefLevel [Byte0]: 40
7852 22:55:53.578802 [Byte1]: 40
7853 22:55:53.583010
7854 22:55:53.583093 Set Vref, RX VrefLevel [Byte0]: 41
7855 22:55:53.586516 [Byte1]: 41
7856 22:55:53.590428
7857 22:55:53.590515 Set Vref, RX VrefLevel [Byte0]: 42
7858 22:55:53.594165 [Byte1]: 42
7859 22:55:53.598528
7860 22:55:53.598636 Set Vref, RX VrefLevel [Byte0]: 43
7861 22:55:53.601227 [Byte1]: 43
7862 22:55:53.605939
7863 22:55:53.606021 Set Vref, RX VrefLevel [Byte0]: 44
7864 22:55:53.609426 [Byte1]: 44
7865 22:55:53.613519
7866 22:55:53.613601 Set Vref, RX VrefLevel [Byte0]: 45
7867 22:55:53.616800 [Byte1]: 45
7868 22:55:53.621103
7869 22:55:53.621185 Set Vref, RX VrefLevel [Byte0]: 46
7870 22:55:53.624362 [Byte1]: 46
7871 22:55:53.628682
7872 22:55:53.628764 Set Vref, RX VrefLevel [Byte0]: 47
7873 22:55:53.631892 [Byte1]: 47
7874 22:55:53.636377
7875 22:55:53.636458 Set Vref, RX VrefLevel [Byte0]: 48
7876 22:55:53.639809 [Byte1]: 48
7877 22:55:53.643990
7878 22:55:53.644071 Set Vref, RX VrefLevel [Byte0]: 49
7879 22:55:53.646863 [Byte1]: 49
7880 22:55:53.651877
7881 22:55:53.651961 Set Vref, RX VrefLevel [Byte0]: 50
7882 22:55:53.655264 [Byte1]: 50
7883 22:55:53.659213
7884 22:55:53.659294 Set Vref, RX VrefLevel [Byte0]: 51
7885 22:55:53.662243 [Byte1]: 51
7886 22:55:53.666707
7887 22:55:53.666853 Set Vref, RX VrefLevel [Byte0]: 52
7888 22:55:53.670242 [Byte1]: 52
7889 22:55:53.674113
7890 22:55:53.674194 Set Vref, RX VrefLevel [Byte0]: 53
7891 22:55:53.677623 [Byte1]: 53
7892 22:55:53.682211
7893 22:55:53.682297 Set Vref, RX VrefLevel [Byte0]: 54
7894 22:55:53.685349 [Byte1]: 54
7895 22:55:53.689384
7896 22:55:53.689468 Set Vref, RX VrefLevel [Byte0]: 55
7897 22:55:53.692755 [Byte1]: 55
7898 22:55:53.697324
7899 22:55:53.697409 Set Vref, RX VrefLevel [Byte0]: 56
7900 22:55:53.700774 [Byte1]: 56
7901 22:55:53.704751
7902 22:55:53.704834 Set Vref, RX VrefLevel [Byte0]: 57
7903 22:55:53.708082 [Byte1]: 57
7904 22:55:53.712157
7905 22:55:53.712240 Set Vref, RX VrefLevel [Byte0]: 58
7906 22:55:53.716054 [Byte1]: 58
7907 22:55:53.720322
7908 22:55:53.720404 Set Vref, RX VrefLevel [Byte0]: 59
7909 22:55:53.723359 [Byte1]: 59
7910 22:55:53.727744
7911 22:55:53.727826 Set Vref, RX VrefLevel [Byte0]: 60
7912 22:55:53.730854 [Byte1]: 60
7913 22:55:53.735479
7914 22:55:53.735562 Set Vref, RX VrefLevel [Byte0]: 61
7915 22:55:53.738727 [Byte1]: 61
7916 22:55:53.743075
7917 22:55:53.743157 Set Vref, RX VrefLevel [Byte0]: 62
7918 22:55:53.745928 [Byte1]: 62
7919 22:55:53.750289
7920 22:55:53.750373 Set Vref, RX VrefLevel [Byte0]: 63
7921 22:55:53.753871 [Byte1]: 63
7922 22:55:53.758173
7923 22:55:53.758256 Set Vref, RX VrefLevel [Byte0]: 64
7924 22:55:53.762027 [Byte1]: 64
7925 22:55:53.765621
7926 22:55:53.765705 Set Vref, RX VrefLevel [Byte0]: 65
7927 22:55:53.769005 [Byte1]: 65
7928 22:55:53.773684
7929 22:55:53.773767 Set Vref, RX VrefLevel [Byte0]: 66
7930 22:55:53.776470 [Byte1]: 66
7931 22:55:53.781047
7932 22:55:53.781131 Set Vref, RX VrefLevel [Byte0]: 67
7933 22:55:53.784042 [Byte1]: 67
7934 22:55:53.788787
7935 22:55:53.788871 Set Vref, RX VrefLevel [Byte0]: 68
7936 22:55:53.791725 [Byte1]: 68
7937 22:55:53.796318
7938 22:55:53.796401 Set Vref, RX VrefLevel [Byte0]: 69
7939 22:55:53.799555 [Byte1]: 69
7940 22:55:53.803569
7941 22:55:53.803653 Set Vref, RX VrefLevel [Byte0]: 70
7942 22:55:53.807233 [Byte1]: 70
7943 22:55:53.811480
7944 22:55:53.811564 Set Vref, RX VrefLevel [Byte0]: 71
7945 22:55:53.814825 [Byte1]: 71
7946 22:55:53.819027
7947 22:55:53.819104 Set Vref, RX VrefLevel [Byte0]: 72
7948 22:55:53.822128 [Byte1]: 72
7949 22:55:53.826761
7950 22:55:53.826893 Set Vref, RX VrefLevel [Byte0]: 73
7951 22:55:53.829831 [Byte1]: 73
7952 22:55:53.834174
7953 22:55:53.834257 Set Vref, RX VrefLevel [Byte0]: 74
7954 22:55:53.837479 [Byte1]: 74
7955 22:55:53.842373
7956 22:55:53.842456 Set Vref, RX VrefLevel [Byte0]: 75
7957 22:55:53.845266 [Byte1]: 75
7958 22:55:53.849628
7959 22:55:53.849714 Set Vref, RX VrefLevel [Byte0]: 76
7960 22:55:53.852485 [Byte1]: 76
7961 22:55:53.857401
7962 22:55:53.857484 Set Vref, RX VrefLevel [Byte0]: 77
7963 22:55:53.860695 [Byte1]: 77
7964 22:55:53.864744
7965 22:55:53.864829 Final RX Vref Byte 0 = 64 to rank0
7966 22:55:53.867768 Final RX Vref Byte 1 = 62 to rank0
7967 22:55:53.870979 Final RX Vref Byte 0 = 64 to rank1
7968 22:55:53.874260 Final RX Vref Byte 1 = 62 to rank1==
7969 22:55:53.877611 Dram Type= 6, Freq= 0, CH_0, rank 0
7970 22:55:53.884734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7971 22:55:53.884821 ==
7972 22:55:53.884888 DQS Delay:
7973 22:55:53.887703 DQS0 = 0, DQS1 = 0
7974 22:55:53.887786 DQM Delay:
7975 22:55:53.887851 DQM0 = 126, DQM1 = 119
7976 22:55:53.890964 DQ Delay:
7977 22:55:53.894427 DQ0 =126, DQ1 =126, DQ2 =126, DQ3 =122
7978 22:55:53.897456 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7979 22:55:53.900730 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7980 22:55:53.904114 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =126
7981 22:55:53.904198
7982 22:55:53.904263
7983 22:55:53.904325
7984 22:55:53.907596 [DramC_TX_OE_Calibration] TA2
7985 22:55:53.911183 Original DQ_B0 (3 6) =30, OEN = 27
7986 22:55:53.913968 Original DQ_B1 (3 6) =30, OEN = 27
7987 22:55:53.917196 24, 0x0, End_B0=24 End_B1=24
7988 22:55:53.920324 25, 0x0, End_B0=25 End_B1=25
7989 22:55:53.920409 26, 0x0, End_B0=26 End_B1=26
7990 22:55:53.924167 27, 0x0, End_B0=27 End_B1=27
7991 22:55:53.927315 28, 0x0, End_B0=28 End_B1=28
7992 22:55:53.930382 29, 0x0, End_B0=29 End_B1=29
7993 22:55:53.930468 30, 0x0, End_B0=30 End_B1=30
7994 22:55:53.933951 31, 0x4141, End_B0=30 End_B1=30
7995 22:55:53.937268 Byte0 end_step=30 best_step=27
7996 22:55:53.940434 Byte1 end_step=30 best_step=27
7997 22:55:53.943569 Byte0 TX OE(2T, 0.5T) = (3, 3)
7998 22:55:53.946963 Byte1 TX OE(2T, 0.5T) = (3, 3)
7999 22:55:53.947048
8000 22:55:53.947114
8001 22:55:53.953828 [DQSOSCAuto] RK0, (LSB)MR18= 0x1212, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
8002 22:55:53.956619 CH0 RK0: MR19=303, MR18=1212
8003 22:55:53.963230 CH0_RK0: MR19=0x303, MR18=0x1212, DQSOSC=400, MR23=63, INC=23, DEC=15
8004 22:55:53.963317
8005 22:55:53.966587 ----->DramcWriteLeveling(PI) begin...
8006 22:55:53.966696 ==
8007 22:55:53.970186 Dram Type= 6, Freq= 0, CH_0, rank 1
8008 22:55:53.973570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8009 22:55:53.973655 ==
8010 22:55:53.976783 Write leveling (Byte 0): 36 => 36
8011 22:55:53.980175 Write leveling (Byte 1): 29 => 29
8012 22:55:53.982991 DramcWriteLeveling(PI) end<-----
8013 22:55:53.983075
8014 22:55:53.983158 ==
8015 22:55:53.986167 Dram Type= 6, Freq= 0, CH_0, rank 1
8016 22:55:53.992918 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8017 22:55:53.993004 ==
8018 22:55:53.993089 [Gating] SW mode calibration
8019 22:55:54.002904 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8020 22:55:54.006009 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8021 22:55:54.012666 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8022 22:55:54.016167 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8023 22:55:54.019038 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8024 22:55:54.025713 1 4 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8025 22:55:54.029115 1 4 16 | B1->B0 | 2525 3434 | 1 1 | (0 0) (1 1)
8026 22:55:54.032346 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8027 22:55:54.039086 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8028 22:55:54.042303 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8029 22:55:54.045407 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8030 22:55:54.052575 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8031 22:55:54.055556 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (1 0)
8032 22:55:54.058748 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
8033 22:55:54.065450 1 5 16 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
8034 22:55:54.069069 1 5 20 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8035 22:55:54.071745 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 22:55:54.078380 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8037 22:55:54.081621 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8038 22:55:54.085282 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8039 22:55:54.091909 1 6 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8040 22:55:54.094780 1 6 12 | B1->B0 | 2323 4242 | 0 1 | (0 0) (0 0)
8041 22:55:54.098011 1 6 16 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
8042 22:55:54.104819 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8043 22:55:54.108387 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 22:55:54.111155 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8045 22:55:54.117968 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8046 22:55:54.121320 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8047 22:55:54.124758 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8048 22:55:54.131231 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8049 22:55:54.134709 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8050 22:55:54.137674 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8051 22:55:54.144592 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 22:55:54.147705 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 22:55:54.150729 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 22:55:54.157458 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 22:55:54.161048 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 22:55:54.164168 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 22:55:54.170728 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 22:55:54.173855 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 22:55:54.177194 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 22:55:54.184060 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 22:55:54.187227 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 22:55:54.190623 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 22:55:54.196908 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8064 22:55:54.200385 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8065 22:55:54.203503 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8066 22:55:54.207008 Total UI for P1: 0, mck2ui 16
8067 22:55:54.209880 best dqsien dly found for B0: ( 1, 9, 10)
8068 22:55:54.216762 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8069 22:55:54.216847 Total UI for P1: 0, mck2ui 16
8070 22:55:54.223633 best dqsien dly found for B1: ( 1, 9, 16)
8071 22:55:54.227035 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8072 22:55:54.229828 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8073 22:55:54.229912
8074 22:55:54.233166 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8075 22:55:54.236359 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8076 22:55:54.240193 [Gating] SW calibration Done
8077 22:55:54.240272 ==
8078 22:55:54.243530 Dram Type= 6, Freq= 0, CH_0, rank 1
8079 22:55:54.246480 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8080 22:55:54.246589 ==
8081 22:55:54.250250 RX Vref Scan: 0
8082 22:55:54.250336
8083 22:55:54.250401 RX Vref 0 -> 0, step: 1
8084 22:55:54.250460
8085 22:55:54.253259 RX Delay 0 -> 252, step: 8
8086 22:55:54.256665 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8087 22:55:54.262775 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8088 22:55:54.266394 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8089 22:55:54.269970 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8090 22:55:54.272822 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8091 22:55:54.276250 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8092 22:55:54.282758 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8093 22:55:54.286306 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8094 22:55:54.289218 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8095 22:55:54.292501 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8096 22:55:54.296766 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8097 22:55:54.302589 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8098 22:55:54.306325 iDelay=200, Bit 12, Center 123 (64 ~ 183) 120
8099 22:55:54.309220 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8100 22:55:54.312583 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8101 22:55:54.318952 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8102 22:55:54.319036 ==
8103 22:55:54.322052 Dram Type= 6, Freq= 0, CH_0, rank 1
8104 22:55:54.325432 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8105 22:55:54.325515 ==
8106 22:55:54.325580 DQS Delay:
8107 22:55:54.329127 DQS0 = 0, DQS1 = 0
8108 22:55:54.329208 DQM Delay:
8109 22:55:54.331844 DQM0 = 128, DQM1 = 121
8110 22:55:54.331926 DQ Delay:
8111 22:55:54.335314 DQ0 =127, DQ1 =127, DQ2 =127, DQ3 =123
8112 22:55:54.338947 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8113 22:55:54.342160 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8114 22:55:54.348884 DQ12 =123, DQ13 =131, DQ14 =131, DQ15 =127
8115 22:55:54.349031
8116 22:55:54.349112
8117 22:55:54.349172 ==
8118 22:55:54.351898 Dram Type= 6, Freq= 0, CH_0, rank 1
8119 22:55:54.355100 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8120 22:55:54.355182 ==
8121 22:55:54.355248
8122 22:55:54.355307
8123 22:55:54.358245 TX Vref Scan disable
8124 22:55:54.358326 == TX Byte 0 ==
8125 22:55:54.365193 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8126 22:55:54.368415 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8127 22:55:54.368500 == TX Byte 1 ==
8128 22:55:54.375046 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8129 22:55:54.378525 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8130 22:55:54.378624 ==
8131 22:55:54.381822 Dram Type= 6, Freq= 0, CH_0, rank 1
8132 22:55:54.384499 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8133 22:55:54.384585 ==
8134 22:55:54.400557
8135 22:55:54.403779 TX Vref early break, caculate TX vref
8136 22:55:54.407131 TX Vref=16, minBit 8, minWin=22, winSum=373
8137 22:55:54.410378 TX Vref=18, minBit 8, minWin=22, winSum=381
8138 22:55:54.413658 TX Vref=20, minBit 9, minWin=22, winSum=391
8139 22:55:54.416976 TX Vref=22, minBit 0, minWin=24, winSum=399
8140 22:55:54.420837 TX Vref=24, minBit 8, minWin=24, winSum=404
8141 22:55:54.426862 TX Vref=26, minBit 8, minWin=24, winSum=415
8142 22:55:54.429999 TX Vref=28, minBit 8, minWin=25, winSum=417
8143 22:55:54.433345 TX Vref=30, minBit 8, minWin=24, winSum=410
8144 22:55:54.436622 TX Vref=32, minBit 8, minWin=24, winSum=408
8145 22:55:54.440098 TX Vref=34, minBit 8, minWin=22, winSum=398
8146 22:55:54.446705 TX Vref=36, minBit 8, minWin=22, winSum=389
8147 22:55:54.450022 [TxChooseVref] Worse bit 8, Min win 25, Win sum 417, Final Vref 28
8148 22:55:54.450109
8149 22:55:54.453326 Final TX Range 0 Vref 28
8150 22:55:54.453409
8151 22:55:54.453476 ==
8152 22:55:54.456347 Dram Type= 6, Freq= 0, CH_0, rank 1
8153 22:55:54.459709 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8154 22:55:54.462975 ==
8155 22:55:54.463065
8156 22:55:54.463131
8157 22:55:54.463192 TX Vref Scan disable
8158 22:55:54.469758 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8159 22:55:54.469844 == TX Byte 0 ==
8160 22:55:54.473125 u2DelayCellOfst[0]=11 cells (3 PI)
8161 22:55:54.476414 u2DelayCellOfst[1]=18 cells (5 PI)
8162 22:55:54.480042 u2DelayCellOfst[2]=11 cells (3 PI)
8163 22:55:54.483171 u2DelayCellOfst[3]=11 cells (3 PI)
8164 22:55:54.486495 u2DelayCellOfst[4]=7 cells (2 PI)
8165 22:55:54.489716 u2DelayCellOfst[5]=0 cells (0 PI)
8166 22:55:54.493099 u2DelayCellOfst[6]=18 cells (5 PI)
8167 22:55:54.496481 u2DelayCellOfst[7]=18 cells (5 PI)
8168 22:55:54.499169 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8169 22:55:54.503160 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8170 22:55:54.505746 == TX Byte 1 ==
8171 22:55:54.509002 u2DelayCellOfst[8]=0 cells (0 PI)
8172 22:55:54.512346 u2DelayCellOfst[9]=0 cells (0 PI)
8173 22:55:54.515854 u2DelayCellOfst[10]=7 cells (2 PI)
8174 22:55:54.518891 u2DelayCellOfst[11]=3 cells (1 PI)
8175 22:55:54.522219 u2DelayCellOfst[12]=11 cells (3 PI)
8176 22:55:54.525923 u2DelayCellOfst[13]=11 cells (3 PI)
8177 22:55:54.528744 u2DelayCellOfst[14]=11 cells (3 PI)
8178 22:55:54.532086 u2DelayCellOfst[15]=11 cells (3 PI)
8179 22:55:54.535559 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8180 22:55:54.538923 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8181 22:55:54.542355 DramC Write-DBI on
8182 22:55:54.542437 ==
8183 22:55:54.545070 Dram Type= 6, Freq= 0, CH_0, rank 1
8184 22:55:54.548898 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8185 22:55:54.548984 ==
8186 22:55:54.549050
8187 22:55:54.549112
8188 22:55:54.551764 TX Vref Scan disable
8189 22:55:54.555186 == TX Byte 0 ==
8190 22:55:54.558310 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8191 22:55:54.558429 == TX Byte 1 ==
8192 22:55:54.565083 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8193 22:55:54.565187 DramC Write-DBI off
8194 22:55:54.565279
8195 22:55:54.565347 [DATLAT]
8196 22:55:54.568749 Freq=1600, CH0 RK1
8197 22:55:54.568832
8198 22:55:54.571435 DATLAT Default: 0xf
8199 22:55:54.571522 0, 0xFFFF, sum = 0
8200 22:55:54.575038 1, 0xFFFF, sum = 0
8201 22:55:54.575122 2, 0xFFFF, sum = 0
8202 22:55:54.578191 3, 0xFFFF, sum = 0
8203 22:55:54.578275 4, 0xFFFF, sum = 0
8204 22:55:54.581393 5, 0xFFFF, sum = 0
8205 22:55:54.581477 6, 0xFFFF, sum = 0
8206 22:55:54.584768 7, 0xFFFF, sum = 0
8207 22:55:54.584852 8, 0xFFFF, sum = 0
8208 22:55:54.588226 9, 0xFFFF, sum = 0
8209 22:55:54.588310 10, 0xFFFF, sum = 0
8210 22:55:54.591302 11, 0xFFFF, sum = 0
8211 22:55:54.591385 12, 0xFFFF, sum = 0
8212 22:55:54.594781 13, 0xCFFF, sum = 0
8213 22:55:54.597980 14, 0x0, sum = 1
8214 22:55:54.598063 15, 0x0, sum = 2
8215 22:55:54.598132 16, 0x0, sum = 3
8216 22:55:54.601479 17, 0x0, sum = 4
8217 22:55:54.601563 best_step = 15
8218 22:55:54.601637
8219 22:55:54.601733 ==
8220 22:55:54.604917 Dram Type= 6, Freq= 0, CH_0, rank 1
8221 22:55:54.611464 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8222 22:55:54.611547 ==
8223 22:55:54.611612 RX Vref Scan: 0
8224 22:55:54.611709
8225 22:55:54.614271 RX Vref 0 -> 0, step: 1
8226 22:55:54.614353
8227 22:55:54.617566 RX Delay 3 -> 252, step: 4
8228 22:55:54.620888 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8229 22:55:54.624663 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8230 22:55:54.630910 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8231 22:55:54.634196 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8232 22:55:54.637678 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8233 22:55:54.640560 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8234 22:55:54.643832 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8235 22:55:54.650661 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8236 22:55:54.653977 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8237 22:55:54.657397 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8238 22:55:54.660808 iDelay=191, Bit 10, Center 118 (63 ~ 174) 112
8239 22:55:54.664099 iDelay=191, Bit 11, Center 110 (55 ~ 166) 112
8240 22:55:54.671025 iDelay=191, Bit 12, Center 122 (67 ~ 178) 112
8241 22:55:54.673860 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8242 22:55:54.677424 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8243 22:55:54.680451 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8244 22:55:54.680545 ==
8245 22:55:54.683706 Dram Type= 6, Freq= 0, CH_0, rank 1
8246 22:55:54.690281 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8247 22:55:54.690371 ==
8248 22:55:54.690472 DQS Delay:
8249 22:55:54.694074 DQS0 = 0, DQS1 = 0
8250 22:55:54.694157 DQM Delay:
8251 22:55:54.696911 DQM0 = 124, DQM1 = 117
8252 22:55:54.696995 DQ Delay:
8253 22:55:54.700635 DQ0 =124, DQ1 =126, DQ2 =122, DQ3 =122
8254 22:55:54.703617 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8255 22:55:54.707057 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =110
8256 22:55:54.710327 DQ12 =122, DQ13 =122, DQ14 =128, DQ15 =124
8257 22:55:54.710411
8258 22:55:54.710512
8259 22:55:54.710610
8260 22:55:54.713774 [DramC_TX_OE_Calibration] TA2
8261 22:55:54.717112 Original DQ_B0 (3 6) =30, OEN = 27
8262 22:55:54.720333 Original DQ_B1 (3 6) =30, OEN = 27
8263 22:55:54.723683 24, 0x0, End_B0=24 End_B1=24
8264 22:55:54.726873 25, 0x0, End_B0=25 End_B1=25
8265 22:55:54.726959 26, 0x0, End_B0=26 End_B1=26
8266 22:55:54.729786 27, 0x0, End_B0=27 End_B1=27
8267 22:55:54.733283 28, 0x0, End_B0=28 End_B1=28
8268 22:55:54.736678 29, 0x0, End_B0=29 End_B1=29
8269 22:55:54.740117 30, 0x0, End_B0=30 End_B1=30
8270 22:55:54.740202 31, 0x4141, End_B0=30 End_B1=30
8271 22:55:54.743398 Byte0 end_step=30 best_step=27
8272 22:55:54.746374 Byte1 end_step=30 best_step=27
8273 22:55:54.749634 Byte0 TX OE(2T, 0.5T) = (3, 3)
8274 22:55:54.753077 Byte1 TX OE(2T, 0.5T) = (3, 3)
8275 22:55:54.753162
8276 22:55:54.753246
8277 22:55:54.759524 [DQSOSCAuto] RK1, (LSB)MR18= 0x2613, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
8278 22:55:54.763034 CH0 RK1: MR19=303, MR18=2613
8279 22:55:54.769405 CH0_RK1: MR19=0x303, MR18=0x2613, DQSOSC=390, MR23=63, INC=24, DEC=16
8280 22:55:54.772879 [RxdqsGatingPostProcess] freq 1600
8281 22:55:54.779493 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8282 22:55:54.782700 best DQS0 dly(2T, 0.5T) = (1, 1)
8283 22:55:54.782809 best DQS1 dly(2T, 0.5T) = (1, 1)
8284 22:55:54.785754 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8285 22:55:54.789211 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8286 22:55:54.792725 best DQS0 dly(2T, 0.5T) = (1, 1)
8287 22:55:54.795835 best DQS1 dly(2T, 0.5T) = (1, 1)
8288 22:55:54.799147 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8289 22:55:54.802512 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8290 22:55:54.805781 Pre-setting of DQS Precalculation
8291 22:55:54.808850 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8292 22:55:54.812101 ==
8293 22:55:54.815540 Dram Type= 6, Freq= 0, CH_1, rank 0
8294 22:55:54.818768 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8295 22:55:54.818858 ==
8296 22:55:54.822563 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8297 22:55:54.828817 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8298 22:55:54.831927 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8299 22:55:54.838681 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8300 22:55:54.847021 [CA 0] Center 41 (12~71) winsize 60
8301 22:55:54.850345 [CA 1] Center 42 (12~72) winsize 61
8302 22:55:54.853948 [CA 2] Center 37 (9~66) winsize 58
8303 22:55:54.857499 [CA 3] Center 36 (7~66) winsize 60
8304 22:55:54.860636 [CA 4] Center 37 (8~66) winsize 59
8305 22:55:54.863410 [CA 5] Center 36 (7~66) winsize 60
8306 22:55:54.863491
8307 22:55:54.866760 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8308 22:55:54.866905
8309 22:55:54.870195 [CATrainingPosCal] consider 1 rank data
8310 22:55:54.873504 u2DelayCellTimex100 = 258/100 ps
8311 22:55:54.877025 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8312 22:55:54.883568 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8313 22:55:54.886762 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8314 22:55:54.890320 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8315 22:55:54.893807 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8316 22:55:54.896735 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8317 22:55:54.896816
8318 22:55:54.899918 CA PerBit enable=1, Macro0, CA PI delay=36
8319 22:55:54.899999
8320 22:55:54.903393 [CBTSetCACLKResult] CA Dly = 36
8321 22:55:54.906663 CS Dly: 9 (0~40)
8322 22:55:54.909839 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8323 22:55:54.913171 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8324 22:55:54.913251 ==
8325 22:55:54.916335 Dram Type= 6, Freq= 0, CH_1, rank 1
8326 22:55:54.923351 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8327 22:55:54.923433 ==
8328 22:55:54.926074 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8329 22:55:54.930114 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8330 22:55:54.936376 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8331 22:55:54.943104 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8332 22:55:54.950254 [CA 0] Center 41 (12~71) winsize 60
8333 22:55:54.953644 [CA 1] Center 42 (12~72) winsize 61
8334 22:55:54.956905 [CA 2] Center 37 (8~67) winsize 60
8335 22:55:54.960102 [CA 3] Center 36 (7~66) winsize 60
8336 22:55:54.963682 [CA 4] Center 37 (8~67) winsize 60
8337 22:55:54.966515 [CA 5] Center 36 (6~66) winsize 61
8338 22:55:54.966598
8339 22:55:54.969992 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8340 22:55:54.970074
8341 22:55:54.973376 [CATrainingPosCal] consider 2 rank data
8342 22:55:54.976810 u2DelayCellTimex100 = 258/100 ps
8343 22:55:54.983394 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8344 22:55:54.986448 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8345 22:55:54.989574 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8346 22:55:54.993239 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8347 22:55:54.996383 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8348 22:55:54.999475 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8349 22:55:54.999558
8350 22:55:55.002727 CA PerBit enable=1, Macro0, CA PI delay=36
8351 22:55:55.002810
8352 22:55:55.006448 [CBTSetCACLKResult] CA Dly = 36
8353 22:55:55.009407 CS Dly: 10 (0~43)
8354 22:55:55.012867 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8355 22:55:55.015919 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8356 22:55:55.016003
8357 22:55:55.019133 ----->DramcWriteLeveling(PI) begin...
8358 22:55:55.019217 ==
8359 22:55:55.022480 Dram Type= 6, Freq= 0, CH_1, rank 0
8360 22:55:55.029370 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8361 22:55:55.029455 ==
8362 22:55:55.032566 Write leveling (Byte 0): 26 => 26
8363 22:55:55.035890 Write leveling (Byte 1): 28 => 28
8364 22:55:55.035976 DramcWriteLeveling(PI) end<-----
8365 22:55:55.039261
8366 22:55:55.039343 ==
8367 22:55:55.042459 Dram Type= 6, Freq= 0, CH_1, rank 0
8368 22:55:55.045468 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8369 22:55:55.045552 ==
8370 22:55:55.048714 [Gating] SW mode calibration
8371 22:55:55.055930 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8372 22:55:55.062325 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8373 22:55:55.065083 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 22:55:55.068375 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 22:55:55.075121 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 22:55:55.078423 1 4 12 | B1->B0 | 2727 2424 | 0 1 | (0 0) (0 0)
8377 22:55:55.081695 1 4 16 | B1->B0 | 3333 3131 | 0 0 | (0 0) (0 0)
8378 22:55:55.088401 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 22:55:55.091658 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 22:55:55.094595 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8381 22:55:55.101268 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8382 22:55:55.104469 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8383 22:55:55.108452 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8384 22:55:55.114230 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8385 22:55:55.117830 1 5 16 | B1->B0 | 2525 2525 | 0 0 | (1 1) (1 0)
8386 22:55:55.120929 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 22:55:55.127968 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 22:55:55.130792 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 22:55:55.134011 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 22:55:55.140894 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8391 22:55:55.144165 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 22:55:55.147311 1 6 12 | B1->B0 | 3535 2c2c | 0 0 | (0 0) (0 0)
8393 22:55:55.154128 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 22:55:55.157455 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 22:55:55.160510 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 22:55:55.167391 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 22:55:55.170739 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 22:55:55.173449 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8399 22:55:55.180366 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8400 22:55:55.183891 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8401 22:55:55.187188 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8402 22:55:55.193343 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8403 22:55:55.196578 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 22:55:55.199921 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 22:55:55.206781 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 22:55:55.209999 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 22:55:55.213139 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 22:55:55.219869 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 22:55:55.222871 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 22:55:55.226623 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 22:55:55.233187 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 22:55:55.236773 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 22:55:55.239672 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 22:55:55.246477 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 22:55:55.249547 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 22:55:55.252794 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8417 22:55:55.259751 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8418 22:55:55.263048 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8419 22:55:55.266037 Total UI for P1: 0, mck2ui 16
8420 22:55:55.268921 best dqsien dly found for B0: ( 1, 9, 14)
8421 22:55:55.272217 Total UI for P1: 0, mck2ui 16
8422 22:55:55.275549 best dqsien dly found for B1: ( 1, 9, 14)
8423 22:55:55.278903 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8424 22:55:55.282275 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8425 22:55:55.282359
8426 22:55:55.285662 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8427 22:55:55.289044 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8428 22:55:55.292446 [Gating] SW calibration Done
8429 22:55:55.292529 ==
8430 22:55:55.295857 Dram Type= 6, Freq= 0, CH_1, rank 0
8431 22:55:55.302467 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8432 22:55:55.302552 ==
8433 22:55:55.302618 RX Vref Scan: 0
8434 22:55:55.302679
8435 22:55:55.305843 RX Vref 0 -> 0, step: 1
8436 22:55:55.305926
8437 22:55:55.308683 RX Delay 0 -> 252, step: 8
8438 22:55:55.312475 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8439 22:55:55.315280 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8440 22:55:55.318683 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8441 22:55:55.321778 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8442 22:55:55.328618 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8443 22:55:55.331783 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8444 22:55:55.335771 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8445 22:55:55.338666 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8446 22:55:55.341865 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8447 22:55:55.348487 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8448 22:55:55.351750 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8449 22:55:55.355304 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8450 22:55:55.358357 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8451 22:55:55.364799 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8452 22:55:55.368369 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8453 22:55:55.371702 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8454 22:55:55.371786 ==
8455 22:55:55.374628 Dram Type= 6, Freq= 0, CH_1, rank 0
8456 22:55:55.378434 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8457 22:55:55.378519 ==
8458 22:55:55.381277 DQS Delay:
8459 22:55:55.381360 DQS0 = 0, DQS1 = 0
8460 22:55:55.384589 DQM Delay:
8461 22:55:55.384672 DQM0 = 132, DQM1 = 125
8462 22:55:55.387881 DQ Delay:
8463 22:55:55.391197 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8464 22:55:55.394789 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8465 22:55:55.397882 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8466 22:55:55.401307 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
8467 22:55:55.401390
8468 22:55:55.401454
8469 22:55:55.401515 ==
8470 22:55:55.404749 Dram Type= 6, Freq= 0, CH_1, rank 0
8471 22:55:55.407525 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8472 22:55:55.407616 ==
8473 22:55:55.407690
8474 22:55:55.411032
8475 22:55:55.411142 TX Vref Scan disable
8476 22:55:55.414386 == TX Byte 0 ==
8477 22:55:55.417572 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8478 22:55:55.420933 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8479 22:55:55.424421 == TX Byte 1 ==
8480 22:55:55.427579 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8481 22:55:55.430751 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8482 22:55:55.430858 ==
8483 22:55:55.434239 Dram Type= 6, Freq= 0, CH_1, rank 0
8484 22:55:55.440449 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8485 22:55:55.440537 ==
8486 22:55:55.452609
8487 22:55:55.455995 TX Vref early break, caculate TX vref
8488 22:55:55.459311 TX Vref=16, minBit 10, minWin=21, winSum=362
8489 22:55:55.462232 TX Vref=18, minBit 9, minWin=22, winSum=372
8490 22:55:55.465430 TX Vref=20, minBit 11, minWin=22, winSum=381
8491 22:55:55.469218 TX Vref=22, minBit 1, minWin=23, winSum=389
8492 22:55:55.471976 TX Vref=24, minBit 0, minWin=25, winSum=404
8493 22:55:55.479009 TX Vref=26, minBit 1, minWin=25, winSum=411
8494 22:55:55.482305 TX Vref=28, minBit 1, minWin=25, winSum=415
8495 22:55:55.485241 TX Vref=30, minBit 0, minWin=24, winSum=409
8496 22:55:55.488455 TX Vref=32, minBit 1, minWin=23, winSum=404
8497 22:55:55.491960 TX Vref=34, minBit 0, minWin=23, winSum=391
8498 22:55:55.499024 [TxChooseVref] Worse bit 1, Min win 25, Win sum 415, Final Vref 28
8499 22:55:55.499113
8500 22:55:55.501631 Final TX Range 0 Vref 28
8501 22:55:55.501720
8502 22:55:55.501786 ==
8503 22:55:55.504884 Dram Type= 6, Freq= 0, CH_1, rank 0
8504 22:55:55.508176 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8505 22:55:55.508260 ==
8506 22:55:55.508325
8507 22:55:55.508386
8508 22:55:55.511476 TX Vref Scan disable
8509 22:55:55.518134 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8510 22:55:55.518220 == TX Byte 0 ==
8511 22:55:55.521464 u2DelayCellOfst[0]=22 cells (6 PI)
8512 22:55:55.525130 u2DelayCellOfst[1]=18 cells (5 PI)
8513 22:55:55.528182 u2DelayCellOfst[2]=0 cells (0 PI)
8514 22:55:55.531424 u2DelayCellOfst[3]=7 cells (2 PI)
8515 22:55:55.534785 u2DelayCellOfst[4]=7 cells (2 PI)
8516 22:55:55.537842 u2DelayCellOfst[5]=22 cells (6 PI)
8517 22:55:55.541484 u2DelayCellOfst[6]=22 cells (6 PI)
8518 22:55:55.545018 u2DelayCellOfst[7]=7 cells (2 PI)
8519 22:55:55.547943 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8520 22:55:55.551188 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8521 22:55:55.554605 == TX Byte 1 ==
8522 22:55:55.557914 u2DelayCellOfst[8]=0 cells (0 PI)
8523 22:55:55.561062 u2DelayCellOfst[9]=7 cells (2 PI)
8524 22:55:55.564660 u2DelayCellOfst[10]=15 cells (4 PI)
8525 22:55:55.564744 u2DelayCellOfst[11]=7 cells (2 PI)
8526 22:55:55.567771 u2DelayCellOfst[12]=18 cells (5 PI)
8527 22:55:55.570963 u2DelayCellOfst[13]=22 cells (6 PI)
8528 22:55:55.574749 u2DelayCellOfst[14]=22 cells (6 PI)
8529 22:55:55.577913 u2DelayCellOfst[15]=22 cells (6 PI)
8530 22:55:55.584278 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8531 22:55:55.587830 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8532 22:55:55.587914 DramC Write-DBI on
8533 22:55:55.590833 ==
8534 22:55:55.590929 Dram Type= 6, Freq= 0, CH_1, rank 0
8535 22:55:55.597418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8536 22:55:55.597503 ==
8537 22:55:55.597568
8538 22:55:55.597628
8539 22:55:55.600843 TX Vref Scan disable
8540 22:55:55.600925 == TX Byte 0 ==
8541 22:55:55.607097 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8542 22:55:55.607185 == TX Byte 1 ==
8543 22:55:55.610808 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8544 22:55:55.613702 DramC Write-DBI off
8545 22:55:55.613784
8546 22:55:55.613848 [DATLAT]
8547 22:55:55.617077 Freq=1600, CH1 RK0
8548 22:55:55.617160
8549 22:55:55.617225 DATLAT Default: 0xf
8550 22:55:55.620444 0, 0xFFFF, sum = 0
8551 22:55:55.620544 1, 0xFFFF, sum = 0
8552 22:55:55.623622 2, 0xFFFF, sum = 0
8553 22:55:55.623706 3, 0xFFFF, sum = 0
8554 22:55:55.626822 4, 0xFFFF, sum = 0
8555 22:55:55.626916 5, 0xFFFF, sum = 0
8556 22:55:55.630461 6, 0xFFFF, sum = 0
8557 22:55:55.630546 7, 0xFFFF, sum = 0
8558 22:55:55.633719 8, 0xFFFF, sum = 0
8559 22:55:55.637088 9, 0xFFFF, sum = 0
8560 22:55:55.637173 10, 0xFFFF, sum = 0
8561 22:55:55.640573 11, 0xFFFF, sum = 0
8562 22:55:55.640658 12, 0xFFFF, sum = 0
8563 22:55:55.644132 13, 0x8FFF, sum = 0
8564 22:55:55.644218 14, 0x0, sum = 1
8565 22:55:55.647174 15, 0x0, sum = 2
8566 22:55:55.647284 16, 0x0, sum = 3
8567 22:55:55.650044 17, 0x0, sum = 4
8568 22:55:55.650128 best_step = 15
8569 22:55:55.650212
8570 22:55:55.650291 ==
8571 22:55:55.653529 Dram Type= 6, Freq= 0, CH_1, rank 0
8572 22:55:55.656707 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8573 22:55:55.660276 ==
8574 22:55:55.660360 RX Vref Scan: 1
8575 22:55:55.660427
8576 22:55:55.663297 Set Vref Range= 24 -> 127
8577 22:55:55.663380
8578 22:55:55.663446 RX Vref 24 -> 127, step: 1
8579 22:55:55.666521
8580 22:55:55.666603 RX Delay 11 -> 252, step: 4
8581 22:55:55.666669
8582 22:55:55.669830 Set Vref, RX VrefLevel [Byte0]: 24
8583 22:55:55.673525 [Byte1]: 24
8584 22:55:55.676970
8585 22:55:55.677057 Set Vref, RX VrefLevel [Byte0]: 25
8586 22:55:55.680258 [Byte1]: 25
8587 22:55:55.684765
8588 22:55:55.684849 Set Vref, RX VrefLevel [Byte0]: 26
8589 22:55:55.687639 [Byte1]: 26
8590 22:55:55.692678
8591 22:55:55.692765 Set Vref, RX VrefLevel [Byte0]: 27
8592 22:55:55.695428 [Byte1]: 27
8593 22:55:55.699943
8594 22:55:55.700029 Set Vref, RX VrefLevel [Byte0]: 28
8595 22:55:55.702991 [Byte1]: 28
8596 22:55:55.707544
8597 22:55:55.707629 Set Vref, RX VrefLevel [Byte0]: 29
8598 22:55:55.710949 [Byte1]: 29
8599 22:55:55.714738
8600 22:55:55.714850 Set Vref, RX VrefLevel [Byte0]: 30
8601 22:55:55.718138 [Byte1]: 30
8602 22:55:55.722650
8603 22:55:55.722734 Set Vref, RX VrefLevel [Byte0]: 31
8604 22:55:55.726030 [Byte1]: 31
8605 22:55:55.730347
8606 22:55:55.730431 Set Vref, RX VrefLevel [Byte0]: 32
8607 22:55:55.733976 [Byte1]: 32
8608 22:55:55.737756
8609 22:55:55.737839 Set Vref, RX VrefLevel [Byte0]: 33
8610 22:55:55.740809 [Byte1]: 33
8611 22:55:55.745573
8612 22:55:55.745656 Set Vref, RX VrefLevel [Byte0]: 34
8613 22:55:55.748925 [Byte1]: 34
8614 22:55:55.753019
8615 22:55:55.753104 Set Vref, RX VrefLevel [Byte0]: 35
8616 22:55:55.756180 [Byte1]: 35
8617 22:55:55.760642
8618 22:55:55.760726 Set Vref, RX VrefLevel [Byte0]: 36
8619 22:55:55.764073 [Byte1]: 36
8620 22:55:55.768447
8621 22:55:55.768531 Set Vref, RX VrefLevel [Byte0]: 37
8622 22:55:55.771639 [Byte1]: 37
8623 22:55:55.775888
8624 22:55:55.775970 Set Vref, RX VrefLevel [Byte0]: 38
8625 22:55:55.779455 [Byte1]: 38
8626 22:55:55.783363
8627 22:55:55.783446 Set Vref, RX VrefLevel [Byte0]: 39
8628 22:55:55.786940 [Byte1]: 39
8629 22:55:55.791006
8630 22:55:55.791091 Set Vref, RX VrefLevel [Byte0]: 40
8631 22:55:55.794360 [Byte1]: 40
8632 22:55:55.798762
8633 22:55:55.798883 Set Vref, RX VrefLevel [Byte0]: 41
8634 22:55:55.802033 [Byte1]: 41
8635 22:55:55.806177
8636 22:55:55.806260 Set Vref, RX VrefLevel [Byte0]: 42
8637 22:55:55.809725 [Byte1]: 42
8638 22:55:55.814267
8639 22:55:55.814350 Set Vref, RX VrefLevel [Byte0]: 43
8640 22:55:55.817603 [Byte1]: 43
8641 22:55:55.821379
8642 22:55:55.821462 Set Vref, RX VrefLevel [Byte0]: 44
8643 22:55:55.824758 [Byte1]: 44
8644 22:55:55.829507
8645 22:55:55.829591 Set Vref, RX VrefLevel [Byte0]: 45
8646 22:55:55.832533 [Byte1]: 45
8647 22:55:55.837050
8648 22:55:55.837134 Set Vref, RX VrefLevel [Byte0]: 46
8649 22:55:55.840379 [Byte1]: 46
8650 22:55:55.844278
8651 22:55:55.844364 Set Vref, RX VrefLevel [Byte0]: 47
8652 22:55:55.847837 [Byte1]: 47
8653 22:55:55.851905
8654 22:55:55.851990 Set Vref, RX VrefLevel [Byte0]: 48
8655 22:55:55.855187 [Byte1]: 48
8656 22:55:55.859793
8657 22:55:55.859877 Set Vref, RX VrefLevel [Byte0]: 49
8658 22:55:55.862969 [Byte1]: 49
8659 22:55:55.867238
8660 22:55:55.867321 Set Vref, RX VrefLevel [Byte0]: 50
8661 22:55:55.870533 [Byte1]: 50
8662 22:55:55.874753
8663 22:55:55.874858 Set Vref, RX VrefLevel [Byte0]: 51
8664 22:55:55.878357 [Byte1]: 51
8665 22:55:55.882609
8666 22:55:55.882693 Set Vref, RX VrefLevel [Byte0]: 52
8667 22:55:55.885605 [Byte1]: 52
8668 22:55:55.890135
8669 22:55:55.890229 Set Vref, RX VrefLevel [Byte0]: 53
8670 22:55:55.893228 [Byte1]: 53
8671 22:55:55.898023
8672 22:55:55.898107 Set Vref, RX VrefLevel [Byte0]: 54
8673 22:55:55.901085 [Byte1]: 54
8674 22:55:55.905821
8675 22:55:55.905905 Set Vref, RX VrefLevel [Byte0]: 55
8676 22:55:55.908738 [Byte1]: 55
8677 22:55:55.912907
8678 22:55:55.913001 Set Vref, RX VrefLevel [Byte0]: 56
8679 22:55:55.916070 [Byte1]: 56
8680 22:55:55.920402
8681 22:55:55.920486 Set Vref, RX VrefLevel [Byte0]: 57
8682 22:55:55.923665 [Byte1]: 57
8683 22:55:55.928384
8684 22:55:55.928467 Set Vref, RX VrefLevel [Byte0]: 58
8685 22:55:55.931725 [Byte1]: 58
8686 22:55:55.935524
8687 22:55:55.935608 Set Vref, RX VrefLevel [Byte0]: 59
8688 22:55:55.938817 [Byte1]: 59
8689 22:55:55.943378
8690 22:55:55.943462 Set Vref, RX VrefLevel [Byte0]: 60
8691 22:55:55.946777 [Byte1]: 60
8692 22:55:55.950796
8693 22:55:55.950922 Set Vref, RX VrefLevel [Byte0]: 61
8694 22:55:55.954262 [Byte1]: 61
8695 22:55:55.958622
8696 22:55:55.958706 Set Vref, RX VrefLevel [Byte0]: 62
8697 22:55:55.962255 [Byte1]: 62
8698 22:55:55.966736
8699 22:55:55.966821 Set Vref, RX VrefLevel [Byte0]: 63
8700 22:55:55.969381 [Byte1]: 63
8701 22:55:55.974093
8702 22:55:55.974176 Set Vref, RX VrefLevel [Byte0]: 64
8703 22:55:55.977410 [Byte1]: 64
8704 22:55:55.981499
8705 22:55:55.981584 Set Vref, RX VrefLevel [Byte0]: 65
8706 22:55:55.984795 [Byte1]: 65
8707 22:55:55.988934
8708 22:55:55.989018 Set Vref, RX VrefLevel [Byte0]: 66
8709 22:55:55.992226 [Byte1]: 66
8710 22:55:55.996404
8711 22:55:55.996488 Set Vref, RX VrefLevel [Byte0]: 67
8712 22:55:55.999882 [Byte1]: 67
8713 22:55:56.004179
8714 22:55:56.004262 Set Vref, RX VrefLevel [Byte0]: 68
8715 22:55:56.007400 [Byte1]: 68
8716 22:55:56.011711
8717 22:55:56.011821 Set Vref, RX VrefLevel [Byte0]: 69
8718 22:55:56.015024 [Byte1]: 69
8719 22:55:56.019330
8720 22:55:56.019416 Set Vref, RX VrefLevel [Byte0]: 70
8721 22:55:56.022845 [Byte1]: 70
8722 22:55:56.027187
8723 22:55:56.027271 Final RX Vref Byte 0 = 57 to rank0
8724 22:55:56.030551 Final RX Vref Byte 1 = 53 to rank0
8725 22:55:56.033962 Final RX Vref Byte 0 = 57 to rank1
8726 22:55:56.037272 Final RX Vref Byte 1 = 53 to rank1==
8727 22:55:56.040462 Dram Type= 6, Freq= 0, CH_1, rank 0
8728 22:55:56.046723 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8729 22:55:56.046811 ==
8730 22:55:56.046926 DQS Delay:
8731 22:55:56.050110 DQS0 = 0, DQS1 = 0
8732 22:55:56.050194 DQM Delay:
8733 22:55:56.050260 DQM0 = 130, DQM1 = 123
8734 22:55:56.053469 DQ Delay:
8735 22:55:56.056817 DQ0 =136, DQ1 =128, DQ2 =120, DQ3 =126
8736 22:55:56.060033 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =126
8737 22:55:56.063349 DQ8 =110, DQ9 =112, DQ10 =122, DQ11 =116
8738 22:55:56.066795 DQ12 =134, DQ13 =132, DQ14 =132, DQ15 =132
8739 22:55:56.066920
8740 22:55:56.066986
8741 22:55:56.067048
8742 22:55:56.070141 [DramC_TX_OE_Calibration] TA2
8743 22:55:56.073525 Original DQ_B0 (3 6) =30, OEN = 27
8744 22:55:56.076855 Original DQ_B1 (3 6) =30, OEN = 27
8745 22:55:56.080154 24, 0x0, End_B0=24 End_B1=24
8746 22:55:56.080240 25, 0x0, End_B0=25 End_B1=25
8747 22:55:56.083306 26, 0x0, End_B0=26 End_B1=26
8748 22:55:56.086422 27, 0x0, End_B0=27 End_B1=27
8749 22:55:56.089805 28, 0x0, End_B0=28 End_B1=28
8750 22:55:56.092936 29, 0x0, End_B0=29 End_B1=29
8751 22:55:56.093022 30, 0x0, End_B0=30 End_B1=30
8752 22:55:56.096538 31, 0x4141, End_B0=30 End_B1=30
8753 22:55:56.099673 Byte0 end_step=30 best_step=27
8754 22:55:56.102849 Byte1 end_step=30 best_step=27
8755 22:55:56.106463 Byte0 TX OE(2T, 0.5T) = (3, 3)
8756 22:55:56.109643 Byte1 TX OE(2T, 0.5T) = (3, 3)
8757 22:55:56.109756
8758 22:55:56.109822
8759 22:55:56.116274 [DQSOSCAuto] RK0, (LSB)MR18= 0x80d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
8760 22:55:56.119802 CH1 RK0: MR19=303, MR18=80D
8761 22:55:56.126293 CH1_RK0: MR19=0x303, MR18=0x80D, DQSOSC=403, MR23=63, INC=22, DEC=15
8762 22:55:56.126378
8763 22:55:56.129683 ----->DramcWriteLeveling(PI) begin...
8764 22:55:56.129781 ==
8765 22:55:56.132721 Dram Type= 6, Freq= 0, CH_1, rank 1
8766 22:55:56.136166 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8767 22:55:56.136250 ==
8768 22:55:56.139450 Write leveling (Byte 0): 25 => 25
8769 22:55:56.142875 Write leveling (Byte 1): 27 => 27
8770 22:55:56.146168 DramcWriteLeveling(PI) end<-----
8771 22:55:56.146251
8772 22:55:56.146316 ==
8773 22:55:56.148822 Dram Type= 6, Freq= 0, CH_1, rank 1
8774 22:55:56.152327 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8775 22:55:56.152412 ==
8776 22:55:56.155842 [Gating] SW mode calibration
8777 22:55:56.162121 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8778 22:55:56.168948 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8779 22:55:56.172153 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8780 22:55:56.178981 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 22:55:56.181896 1 4 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
8782 22:55:56.185171 1 4 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8783 22:55:56.192062 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8784 22:55:56.195131 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 22:55:56.198771 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
8786 22:55:56.204887 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8787 22:55:56.208769 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8788 22:55:56.211773 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8789 22:55:56.218561 1 5 8 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 0)
8790 22:55:56.221677 1 5 12 | B1->B0 | 2626 2323 | 0 0 | (1 0) (1 0)
8791 22:55:56.224873 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 22:55:56.231268 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 22:55:56.234609 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 22:55:56.237993 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 22:55:56.244578 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 22:55:56.247838 1 6 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
8797 22:55:56.251083 1 6 8 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
8798 22:55:56.257786 1 6 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8799 22:55:56.261284 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 22:55:56.264065 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 22:55:56.270835 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 22:55:56.274184 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 22:55:56.277148 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 22:55:56.283868 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 22:55:56.287331 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8806 22:55:56.290573 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8807 22:55:56.297464 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 22:55:56.300527 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 22:55:56.303776 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 22:55:56.310414 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 22:55:56.314062 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 22:55:56.317033 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 22:55:56.323689 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 22:55:56.326990 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 22:55:56.330653 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 22:55:56.336697 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 22:55:56.340026 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 22:55:56.343312 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 22:55:56.349739 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 22:55:56.353452 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 22:55:56.356857 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8822 22:55:56.363018 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8823 22:55:56.366333 Total UI for P1: 0, mck2ui 16
8824 22:55:56.369326 best dqsien dly found for B0: ( 1, 9, 8)
8825 22:55:56.372780 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8826 22:55:56.376120 Total UI for P1: 0, mck2ui 16
8827 22:55:56.379691 best dqsien dly found for B1: ( 1, 9, 12)
8828 22:55:56.382974 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8829 22:55:56.385863 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8830 22:55:56.385948
8831 22:55:56.389368 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8832 22:55:56.395720 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8833 22:55:56.395803 [Gating] SW calibration Done
8834 22:55:56.395870 ==
8835 22:55:56.399120 Dram Type= 6, Freq= 0, CH_1, rank 1
8836 22:55:56.405938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8837 22:55:56.406021 ==
8838 22:55:56.406086 RX Vref Scan: 0
8839 22:55:56.406146
8840 22:55:56.409403 RX Vref 0 -> 0, step: 1
8841 22:55:56.409485
8842 22:55:56.412400 RX Delay 0 -> 252, step: 8
8843 22:55:56.415494 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8844 22:55:56.418725 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8845 22:55:56.422387 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8846 22:55:56.428839 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8847 22:55:56.432190 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8848 22:55:56.435399 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8849 22:55:56.438563 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8850 22:55:56.441895 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8851 22:55:56.448513 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8852 22:55:56.451965 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8853 22:55:56.455067 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8854 22:55:56.458532 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8855 22:55:56.464790 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8856 22:55:56.468172 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8857 22:55:56.471404 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8858 22:55:56.474822 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8859 22:55:56.474942 ==
8860 22:55:56.478178 Dram Type= 6, Freq= 0, CH_1, rank 1
8861 22:55:56.481675 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8862 22:55:56.484904 ==
8863 22:55:56.484986 DQS Delay:
8864 22:55:56.485052 DQS0 = 0, DQS1 = 0
8865 22:55:56.488016 DQM Delay:
8866 22:55:56.488098 DQM0 = 132, DQM1 = 128
8867 22:55:56.491172 DQ Delay:
8868 22:55:56.494534 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8869 22:55:56.498019 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8870 22:55:56.501274 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8871 22:55:56.504691 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =139
8872 22:55:56.504773
8873 22:55:56.504838
8874 22:55:56.504897 ==
8875 22:55:56.507932 Dram Type= 6, Freq= 0, CH_1, rank 1
8876 22:55:56.511626 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8877 22:55:56.514259 ==
8878 22:55:56.514341
8879 22:55:56.514406
8880 22:55:56.514466 TX Vref Scan disable
8881 22:55:56.517835 == TX Byte 0 ==
8882 22:55:56.520848 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8883 22:55:56.524278 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8884 22:55:56.527661 == TX Byte 1 ==
8885 22:55:56.530775 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8886 22:55:56.533988 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8887 22:55:56.537304 ==
8888 22:55:56.540785 Dram Type= 6, Freq= 0, CH_1, rank 1
8889 22:55:56.543833 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8890 22:55:56.543917 ==
8891 22:55:56.557442
8892 22:55:56.560852 TX Vref early break, caculate TX vref
8893 22:55:56.563780 TX Vref=16, minBit 0, minWin=23, winSum=388
8894 22:55:56.567504 TX Vref=18, minBit 0, minWin=23, winSum=390
8895 22:55:56.570254 TX Vref=20, minBit 0, minWin=24, winSum=402
8896 22:55:56.573556 TX Vref=22, minBit 0, minWin=25, winSum=413
8897 22:55:56.576947 TX Vref=24, minBit 0, minWin=23, winSum=417
8898 22:55:56.583492 TX Vref=26, minBit 0, minWin=25, winSum=427
8899 22:55:56.586752 TX Vref=28, minBit 0, minWin=25, winSum=428
8900 22:55:56.590448 TX Vref=30, minBit 0, minWin=25, winSum=422
8901 22:55:56.593765 TX Vref=32, minBit 1, minWin=24, winSum=412
8902 22:55:56.597067 TX Vref=34, minBit 0, minWin=24, winSum=408
8903 22:55:56.603156 TX Vref=36, minBit 0, minWin=23, winSum=399
8904 22:55:56.606526 [TxChooseVref] Worse bit 0, Min win 25, Win sum 428, Final Vref 28
8905 22:55:56.606610
8906 22:55:56.609886 Final TX Range 0 Vref 28
8907 22:55:56.609969
8908 22:55:56.610034 ==
8909 22:55:56.613145 Dram Type= 6, Freq= 0, CH_1, rank 1
8910 22:55:56.616405 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8911 22:55:56.619908 ==
8912 22:55:56.619994
8913 22:55:56.620059
8914 22:55:56.620121 TX Vref Scan disable
8915 22:55:56.626443 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8916 22:55:56.626526 == TX Byte 0 ==
8917 22:55:56.629898 u2DelayCellOfst[0]=18 cells (5 PI)
8918 22:55:56.632850 u2DelayCellOfst[1]=18 cells (5 PI)
8919 22:55:56.636391 u2DelayCellOfst[2]=0 cells (0 PI)
8920 22:55:56.640114 u2DelayCellOfst[3]=7 cells (2 PI)
8921 22:55:56.643167 u2DelayCellOfst[4]=11 cells (3 PI)
8922 22:55:56.646353 u2DelayCellOfst[5]=22 cells (6 PI)
8923 22:55:56.649466 u2DelayCellOfst[6]=22 cells (6 PI)
8924 22:55:56.653192 u2DelayCellOfst[7]=11 cells (3 PI)
8925 22:55:56.656270 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8926 22:55:56.659816 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8927 22:55:56.662682 == TX Byte 1 ==
8928 22:55:56.666068 u2DelayCellOfst[8]=0 cells (0 PI)
8929 22:55:56.669434 u2DelayCellOfst[9]=7 cells (2 PI)
8930 22:55:56.672963 u2DelayCellOfst[10]=11 cells (3 PI)
8931 22:55:56.676129 u2DelayCellOfst[11]=7 cells (2 PI)
8932 22:55:56.679347 u2DelayCellOfst[12]=18 cells (5 PI)
8933 22:55:56.682720 u2DelayCellOfst[13]=18 cells (5 PI)
8934 22:55:56.686040 u2DelayCellOfst[14]=18 cells (5 PI)
8935 22:55:56.686163 u2DelayCellOfst[15]=18 cells (5 PI)
8936 22:55:56.692743 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8937 22:55:56.695686 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8938 22:55:56.699044 DramC Write-DBI on
8939 22:55:56.699127 ==
8940 22:55:56.702466 Dram Type= 6, Freq= 0, CH_1, rank 1
8941 22:55:56.705737 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8942 22:55:56.705821 ==
8943 22:55:56.705886
8944 22:55:56.705947
8945 22:55:56.708965 TX Vref Scan disable
8946 22:55:56.709048 == TX Byte 0 ==
8947 22:55:56.715655 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8948 22:55:56.715737 == TX Byte 1 ==
8949 22:55:56.721946 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8950 22:55:56.722028 DramC Write-DBI off
8951 22:55:56.722095
8952 22:55:56.722155 [DATLAT]
8953 22:55:56.725191 Freq=1600, CH1 RK1
8954 22:55:56.725273
8955 22:55:56.728838 DATLAT Default: 0xf
8956 22:55:56.728920 0, 0xFFFF, sum = 0
8957 22:55:56.731921 1, 0xFFFF, sum = 0
8958 22:55:56.732032 2, 0xFFFF, sum = 0
8959 22:55:56.735129 3, 0xFFFF, sum = 0
8960 22:55:56.735212 4, 0xFFFF, sum = 0
8961 22:55:56.738658 5, 0xFFFF, sum = 0
8962 22:55:56.738742 6, 0xFFFF, sum = 0
8963 22:55:56.741842 7, 0xFFFF, sum = 0
8964 22:55:56.741926 8, 0xFFFF, sum = 0
8965 22:55:56.745019 9, 0xFFFF, sum = 0
8966 22:55:56.745103 10, 0xFFFF, sum = 0
8967 22:55:56.748280 11, 0xFFFF, sum = 0
8968 22:55:56.748363 12, 0xFFFF, sum = 0
8969 22:55:56.751487 13, 0x8FFF, sum = 0
8970 22:55:56.751571 14, 0x0, sum = 1
8971 22:55:56.755557 15, 0x0, sum = 2
8972 22:55:56.755642 16, 0x0, sum = 3
8973 22:55:56.758295 17, 0x0, sum = 4
8974 22:55:56.758378 best_step = 15
8975 22:55:56.758444
8976 22:55:56.758505 ==
8977 22:55:56.761474 Dram Type= 6, Freq= 0, CH_1, rank 1
8978 22:55:56.768235 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8979 22:55:56.768320 ==
8980 22:55:56.768386 RX Vref Scan: 0
8981 22:55:56.768447
8982 22:55:56.771547 RX Vref 0 -> 0, step: 1
8983 22:55:56.771630
8984 22:55:56.774522 RX Delay 11 -> 252, step: 4
8985 22:55:56.777757 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8986 22:55:56.781466 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
8987 22:55:56.788027 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8988 22:55:56.791373 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8989 22:55:56.794180 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8990 22:55:56.797624 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8991 22:55:56.800926 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8992 22:55:56.807173 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
8993 22:55:56.811095 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
8994 22:55:56.814195 iDelay=195, Bit 9, Center 114 (63 ~ 166) 104
8995 22:55:56.817085 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8996 22:55:56.820417 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8997 22:55:56.827011 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8998 22:55:56.830613 iDelay=195, Bit 13, Center 134 (79 ~ 190) 112
8999 22:55:56.833957 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9000 22:55:56.837026 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
9001 22:55:56.840290 ==
9002 22:55:56.840373 Dram Type= 6, Freq= 0, CH_1, rank 1
9003 22:55:56.846797 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9004 22:55:56.846920 ==
9005 22:55:56.846986 DQS Delay:
9006 22:55:56.850266 DQS0 = 0, DQS1 = 0
9007 22:55:56.850348 DQM Delay:
9008 22:55:56.853603 DQM0 = 130, DQM1 = 125
9009 22:55:56.853686 DQ Delay:
9010 22:55:56.856846 DQ0 =134, DQ1 =128, DQ2 =118, DQ3 =128
9011 22:55:56.859857 DQ4 =126, DQ5 =142, DQ6 =140, DQ7 =126
9012 22:55:56.863528 DQ8 =112, DQ9 =114, DQ10 =128, DQ11 =120
9013 22:55:56.866694 DQ12 =132, DQ13 =134, DQ14 =130, DQ15 =134
9014 22:55:56.866777
9015 22:55:56.866865
9016 22:55:56.866941
9017 22:55:56.869880 [DramC_TX_OE_Calibration] TA2
9018 22:55:56.873328 Original DQ_B0 (3 6) =30, OEN = 27
9019 22:55:56.876780 Original DQ_B1 (3 6) =30, OEN = 27
9020 22:55:56.879991 24, 0x0, End_B0=24 End_B1=24
9021 22:55:56.883323 25, 0x0, End_B0=25 End_B1=25
9022 22:55:56.883406 26, 0x0, End_B0=26 End_B1=26
9023 22:55:56.886606 27, 0x0, End_B0=27 End_B1=27
9024 22:55:56.889742 28, 0x0, End_B0=28 End_B1=28
9025 22:55:56.892814 29, 0x0, End_B0=29 End_B1=29
9026 22:55:56.896172 30, 0x0, End_B0=30 End_B1=30
9027 22:55:56.896255 31, 0x4141, End_B0=30 End_B1=30
9028 22:55:56.899649 Byte0 end_step=30 best_step=27
9029 22:55:56.903163 Byte1 end_step=30 best_step=27
9030 22:55:56.906348 Byte0 TX OE(2T, 0.5T) = (3, 3)
9031 22:55:56.909777 Byte1 TX OE(2T, 0.5T) = (3, 3)
9032 22:55:56.909860
9033 22:55:56.909924
9034 22:55:56.916312 [DQSOSCAuto] RK1, (LSB)MR18= 0x121e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
9035 22:55:56.919257 CH1 RK1: MR19=303, MR18=121E
9036 22:55:56.926008 CH1_RK1: MR19=0x303, MR18=0x121E, DQSOSC=394, MR23=63, INC=23, DEC=15
9037 22:55:56.929383 [RxdqsGatingPostProcess] freq 1600
9038 22:55:56.935750 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9039 22:55:56.939165 best DQS0 dly(2T, 0.5T) = (1, 1)
9040 22:55:56.939247 best DQS1 dly(2T, 0.5T) = (1, 1)
9041 22:55:56.942637 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9042 22:55:56.945601 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9043 22:55:56.948773 best DQS0 dly(2T, 0.5T) = (1, 1)
9044 22:55:56.952458 best DQS1 dly(2T, 0.5T) = (1, 1)
9045 22:55:56.955653 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9046 22:55:56.958809 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9047 22:55:56.962136 Pre-setting of DQS Precalculation
9048 22:55:56.968783 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9049 22:55:56.975464 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9050 22:55:56.981832 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9051 22:55:56.981916
9052 22:55:56.981981
9053 22:55:56.985132 [Calibration Summary] 3200 Mbps
9054 22:55:56.985223 CH 0, Rank 0
9055 22:55:56.988521 SW Impedance : PASS
9056 22:55:56.991700 DUTY Scan : NO K
9057 22:55:56.991782 ZQ Calibration : PASS
9058 22:55:56.995039 Jitter Meter : NO K
9059 22:55:56.998425 CBT Training : PASS
9060 22:55:56.998533 Write leveling : PASS
9061 22:55:57.002065 RX DQS gating : PASS
9062 22:55:57.004747 RX DQ/DQS(RDDQC) : PASS
9063 22:55:57.004830 TX DQ/DQS : PASS
9064 22:55:57.008088 RX DATLAT : PASS
9065 22:55:57.011410 RX DQ/DQS(Engine): PASS
9066 22:55:57.011491 TX OE : PASS
9067 22:55:57.011557 All Pass.
9068 22:55:57.014766
9069 22:55:57.014906 CH 0, Rank 1
9070 22:55:57.017781 SW Impedance : PASS
9071 22:55:57.017863 DUTY Scan : NO K
9072 22:55:57.021532 ZQ Calibration : PASS
9073 22:55:57.024314 Jitter Meter : NO K
9074 22:55:57.024396 CBT Training : PASS
9075 22:55:57.028211 Write leveling : PASS
9076 22:55:57.028294 RX DQS gating : PASS
9077 22:55:57.031050 RX DQ/DQS(RDDQC) : PASS
9078 22:55:57.034552 TX DQ/DQS : PASS
9079 22:55:57.034635 RX DATLAT : PASS
9080 22:55:57.037933 RX DQ/DQS(Engine): PASS
9081 22:55:57.040906 TX OE : PASS
9082 22:55:57.040989 All Pass.
9083 22:55:57.041053
9084 22:55:57.041112 CH 1, Rank 0
9085 22:55:57.044134 SW Impedance : PASS
9086 22:55:57.047874 DUTY Scan : NO K
9087 22:55:57.047956 ZQ Calibration : PASS
9088 22:55:57.051116 Jitter Meter : NO K
9089 22:55:57.054384 CBT Training : PASS
9090 22:55:57.054467 Write leveling : PASS
9091 22:55:57.057882 RX DQS gating : PASS
9092 22:55:57.060949 RX DQ/DQS(RDDQC) : PASS
9093 22:55:57.061031 TX DQ/DQS : PASS
9094 22:55:57.064234 RX DATLAT : PASS
9095 22:55:57.067405 RX DQ/DQS(Engine): PASS
9096 22:55:57.067488 TX OE : PASS
9097 22:55:57.070674 All Pass.
9098 22:55:57.070784
9099 22:55:57.070903 CH 1, Rank 1
9100 22:55:57.074292 SW Impedance : PASS
9101 22:55:57.074375 DUTY Scan : NO K
9102 22:55:57.077304 ZQ Calibration : PASS
9103 22:55:57.080499 Jitter Meter : NO K
9104 22:55:57.080582 CBT Training : PASS
9105 22:55:57.084142 Write leveling : PASS
9106 22:55:57.087445 RX DQS gating : PASS
9107 22:55:57.087528 RX DQ/DQS(RDDQC) : PASS
9108 22:55:57.090714 TX DQ/DQS : PASS
9109 22:55:57.094248 RX DATLAT : PASS
9110 22:55:57.094330 RX DQ/DQS(Engine): PASS
9111 22:55:57.097423 TX OE : PASS
9112 22:55:57.097506 All Pass.
9113 22:55:57.097572
9114 22:55:57.100673 DramC Write-DBI on
9115 22:55:57.103950 PER_BANK_REFRESH: Hybrid Mode
9116 22:55:57.104032 TX_TRACKING: ON
9117 22:55:57.113371 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9118 22:55:57.120310 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9119 22:55:57.126596 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9120 22:55:57.129981 [FAST_K] Save calibration result to emmc
9121 22:55:57.133406 sync common calibartion params.
9122 22:55:57.136817 sync cbt_mode0:1, 1:1
9123 22:55:57.140177 dram_init: ddr_geometry: 2
9124 22:55:57.140259 dram_init: ddr_geometry: 2
9125 22:55:57.143625 dram_init: ddr_geometry: 2
9126 22:55:57.146979 0:dram_rank_size:100000000
9127 22:55:57.149896 1:dram_rank_size:100000000
9128 22:55:57.153276 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9129 22:55:57.156707 DFS_SHUFFLE_HW_MODE: ON
9130 22:55:57.159682 dramc_set_vcore_voltage set vcore to 725000
9131 22:55:57.162963 Read voltage for 1600, 0
9132 22:55:57.163071 Vio18 = 0
9133 22:55:57.163169 Vcore = 725000
9134 22:55:57.166548 Vdram = 0
9135 22:55:57.166656 Vddq = 0
9136 22:55:57.166749 Vmddr = 0
9137 22:55:57.169413 switch to 3200 Mbps bootup
9138 22:55:57.173040 [DramcRunTimeConfig]
9139 22:55:57.173121 PHYPLL
9140 22:55:57.173187 DPM_CONTROL_AFTERK: ON
9141 22:55:57.176260 PER_BANK_REFRESH: ON
9142 22:55:57.179100 REFRESH_OVERHEAD_REDUCTION: ON
9143 22:55:57.182543 CMD_PICG_NEW_MODE: OFF
9144 22:55:57.182625 XRTWTW_NEW_MODE: ON
9145 22:55:57.185709 XRTRTR_NEW_MODE: ON
9146 22:55:57.185792 TX_TRACKING: ON
9147 22:55:57.189269 RDSEL_TRACKING: OFF
9148 22:55:57.192356 DQS Precalculation for DVFS: ON
9149 22:55:57.192456 RX_TRACKING: OFF
9150 22:55:57.195713 HW_GATING DBG: ON
9151 22:55:57.195795 ZQCS_ENABLE_LP4: ON
9152 22:55:57.199096 RX_PICG_NEW_MODE: ON
9153 22:55:57.199178 TX_PICG_NEW_MODE: ON
9154 22:55:57.201990 ENABLE_RX_DCM_DPHY: ON
9155 22:55:57.205196 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9156 22:55:57.208692 DUMMY_READ_FOR_TRACKING: OFF
9157 22:55:57.208775 !!! SPM_CONTROL_AFTERK: OFF
9158 22:55:57.212080 !!! SPM could not control APHY
9159 22:55:57.215433 IMPEDANCE_TRACKING: ON
9160 22:55:57.215514 TEMP_SENSOR: ON
9161 22:55:57.218721 HW_SAVE_FOR_SR: OFF
9162 22:55:57.222166 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9163 22:55:57.225384 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9164 22:55:57.225466 Read ODT Tracking: ON
9165 22:55:57.228749 Refresh Rate DeBounce: ON
9166 22:55:57.232100 DFS_NO_QUEUE_FLUSH: ON
9167 22:55:57.235021 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9168 22:55:57.235102 ENABLE_DFS_RUNTIME_MRW: OFF
9169 22:55:57.238435 DDR_RESERVE_NEW_MODE: ON
9170 22:55:57.241761 MR_CBT_SWITCH_FREQ: ON
9171 22:55:57.241844 =========================
9172 22:55:57.262167 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9173 22:55:57.265182 dram_init: ddr_geometry: 2
9174 22:55:57.283855 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9175 22:55:57.287122 dram_init: dram init end (result: 0)
9176 22:55:57.293605 DRAM-K: Full calibration passed in 24598 msecs
9177 22:55:57.297230 MRC: failed to locate region type 0.
9178 22:55:57.297312 DRAM rank0 size:0x100000000,
9179 22:55:57.299882 DRAM rank1 size=0x100000000
9180 22:55:57.309785 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9181 22:55:57.316577 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9182 22:55:57.323310 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9183 22:55:57.333309 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9184 22:55:57.333392 DRAM rank0 size:0x100000000,
9185 22:55:57.336218 DRAM rank1 size=0x100000000
9186 22:55:57.336301 CBMEM:
9187 22:55:57.339725 IMD: root @ 0xfffff000 254 entries.
9188 22:55:57.342944 IMD: root @ 0xffffec00 62 entries.
9189 22:55:57.346305 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9190 22:55:57.353050 WARNING: RO_VPD is uninitialized or empty.
9191 22:55:57.356471 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9192 22:55:57.364022 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9193 22:55:57.376219 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9194 22:55:57.387844 BS: romstage times (exec / console): total (unknown) / 24055 ms
9195 22:55:57.387930
9196 22:55:57.387997
9197 22:55:57.398019 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9198 22:55:57.401056 ARM64: Exception handlers installed.
9199 22:55:57.404271 ARM64: Testing exception
9200 22:55:57.407500 ARM64: Done test exception
9201 22:55:57.407585 Enumerating buses...
9202 22:55:57.411030 Show all devs... Before device enumeration.
9203 22:55:57.414159 Root Device: enabled 1
9204 22:55:57.417633 CPU_CLUSTER: 0: enabled 1
9205 22:55:57.417717 CPU: 00: enabled 1
9206 22:55:57.420871 Compare with tree...
9207 22:55:57.420976 Root Device: enabled 1
9208 22:55:57.423872 CPU_CLUSTER: 0: enabled 1
9209 22:55:57.427186 CPU: 00: enabled 1
9210 22:55:57.427269 Root Device scanning...
9211 22:55:57.430505 scan_static_bus for Root Device
9212 22:55:57.434248 CPU_CLUSTER: 0 enabled
9213 22:55:57.436957 scan_static_bus for Root Device done
9214 22:55:57.440432 scan_bus: bus Root Device finished in 8 msecs
9215 22:55:57.440519 done
9216 22:55:57.447143 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9217 22:55:57.450533 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9218 22:55:57.456752 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9219 22:55:57.463492 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9220 22:55:57.463581 Allocating resources...
9221 22:55:57.466774 Reading resources...
9222 22:55:57.469906 Root Device read_resources bus 0 link: 0
9223 22:55:57.473222 DRAM rank0 size:0x100000000,
9224 22:55:57.473303 DRAM rank1 size=0x100000000
9225 22:55:57.479992 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9226 22:55:57.480101 CPU: 00 missing read_resources
9227 22:55:57.486398 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9228 22:55:57.490031 Root Device read_resources bus 0 link: 0 done
9229 22:55:57.493128 Done reading resources.
9230 22:55:57.496464 Show resources in subtree (Root Device)...After reading.
9231 22:55:57.499624 Root Device child on link 0 CPU_CLUSTER: 0
9232 22:55:57.502955 CPU_CLUSTER: 0 child on link 0 CPU: 00
9233 22:55:57.512905 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9234 22:55:57.512997 CPU: 00
9235 22:55:57.519333 Root Device assign_resources, bus 0 link: 0
9236 22:55:57.522803 CPU_CLUSTER: 0 missing set_resources
9237 22:55:57.526121 Root Device assign_resources, bus 0 link: 0 done
9238 22:55:57.529501 Done setting resources.
9239 22:55:57.532999 Show resources in subtree (Root Device)...After assigning values.
9240 22:55:57.535842 Root Device child on link 0 CPU_CLUSTER: 0
9241 22:55:57.542480 CPU_CLUSTER: 0 child on link 0 CPU: 00
9242 22:55:57.549527 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9243 22:55:57.552226 CPU: 00
9244 22:55:57.552313 Done allocating resources.
9245 22:55:57.559067 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9246 22:55:57.559158 Enabling resources...
9247 22:55:57.562400 done.
9248 22:55:57.565920 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9249 22:55:57.568735 Initializing devices...
9250 22:55:57.568818 Root Device init
9251 22:55:57.572104 init hardware done!
9252 22:55:57.572188 0x00000018: ctrlr->caps
9253 22:55:57.575700 52.000 MHz: ctrlr->f_max
9254 22:55:57.578736 0.400 MHz: ctrlr->f_min
9255 22:55:57.582262 0x40ff8080: ctrlr->voltages
9256 22:55:57.582347 sclk: 390625
9257 22:55:57.582413 Bus Width = 1
9258 22:55:57.585281 sclk: 390625
9259 22:55:57.585365 Bus Width = 1
9260 22:55:57.588846 Early init status = 3
9261 22:55:57.592082 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9262 22:55:57.595581 in-header: 03 fc 00 00 01 00 00 00
9263 22:55:57.598677 in-data: 00
9264 22:55:57.601850 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9265 22:55:57.606508 in-header: 03 fd 00 00 00 00 00 00
9266 22:55:57.610147 in-data:
9267 22:55:57.613181 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9268 22:55:57.616496 in-header: 03 fc 00 00 01 00 00 00
9269 22:55:57.620177 in-data: 00
9270 22:55:57.623295 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9271 22:55:57.627880 in-header: 03 fd 00 00 00 00 00 00
9272 22:55:57.631330 in-data:
9273 22:55:57.634251 [SSUSB] Setting up USB HOST controller...
9274 22:55:57.638011 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9275 22:55:57.640921 [SSUSB] phy power-on done.
9276 22:55:57.644435 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9277 22:55:57.651079 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9278 22:55:57.654374 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9279 22:55:57.660669 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9280 22:55:57.667366 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9281 22:55:57.674160 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9282 22:55:57.680685 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9283 22:55:57.687200 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9284 22:55:57.690588 SPM: binary array size = 0x9dc
9285 22:55:57.694007 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9286 22:55:57.700606 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9287 22:55:57.707176 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9288 22:55:57.713557 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9289 22:55:57.716719 configure_display: Starting display init
9290 22:55:57.751097 anx7625_power_on_init: Init interface.
9291 22:55:57.754510 anx7625_disable_pd_protocol: Disabled PD feature.
9292 22:55:57.760843 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9293 22:55:57.785321 anx7625_start_dp_work: Secure OCM version=00
9294 22:55:57.788816 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9295 22:55:57.803524 sp_tx_get_edid_block: EDID Block = 1
9296 22:55:57.906144 Extracted contents:
9297 22:55:57.909873 header: 00 ff ff ff ff ff ff 00
9298 22:55:57.912632 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9299 22:55:57.916031 version: 01 04
9300 22:55:57.919229 basic params: 95 1f 11 78 0a
9301 22:55:57.922465 chroma info: 76 90 94 55 54 90 27 21 50 54
9302 22:55:57.926109 established: 00 00 00
9303 22:55:57.932425 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9304 22:55:57.939260 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9305 22:55:57.942270 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9306 22:55:57.948785 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9307 22:55:57.955513 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9308 22:55:57.958506 extensions: 00
9309 22:55:57.958609 checksum: fb
9310 22:55:57.958675
9311 22:55:57.965384 Manufacturer: IVO Model 57d Serial Number 0
9312 22:55:57.965481 Made week 0 of 2020
9313 22:55:57.968703 EDID version: 1.4
9314 22:55:57.968787 Digital display
9315 22:55:57.972088 6 bits per primary color channel
9316 22:55:57.974968 DisplayPort interface
9317 22:55:57.975060 Maximum image size: 31 cm x 17 cm
9318 22:55:57.978370 Gamma: 220%
9319 22:55:57.978457 Check DPMS levels
9320 22:55:57.984860 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9321 22:55:57.988379 First detailed timing is preferred timing
9322 22:55:57.991808 Established timings supported:
9323 22:55:57.991896 Standard timings supported:
9324 22:55:57.995107 Detailed timings
9325 22:55:57.998081 Hex of detail: 383680a07038204018303c0035ae10000019
9326 22:55:58.004763 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9327 22:55:58.008057 0780 0798 07c8 0820 hborder 0
9328 22:55:58.011326 0438 043b 0447 0458 vborder 0
9329 22:55:58.014586 -hsync -vsync
9330 22:55:58.014670 Did detailed timing
9331 22:55:58.021105 Hex of detail: 000000000000000000000000000000000000
9332 22:55:58.024426 Manufacturer-specified data, tag 0
9333 22:55:58.027697 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9334 22:55:58.031203 ASCII string: InfoVision
9335 22:55:58.034422 Hex of detail: 000000fe00523134304e574635205248200a
9336 22:55:58.037646 ASCII string: R140NWF5 RH
9337 22:55:58.037739 Checksum
9338 22:55:58.040750 Checksum: 0xfb (valid)
9339 22:55:58.044111 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9340 22:55:58.047879 DSI data_rate: 832800000 bps
9341 22:55:58.054243 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9342 22:55:58.057841 anx7625_parse_edid: pixelclock(138800).
9343 22:55:58.060860 hactive(1920), hsync(48), hfp(24), hbp(88)
9344 22:55:58.064192 vactive(1080), vsync(12), vfp(3), vbp(17)
9345 22:55:58.067559 anx7625_dsi_config: config dsi.
9346 22:55:58.073927 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9347 22:55:58.088714 anx7625_dsi_config: success to config DSI
9348 22:55:58.091795 anx7625_dp_start: MIPI phy setup OK.
9349 22:55:58.094648 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9350 22:55:58.098061 mtk_ddp_mode_set invalid vrefresh 60
9351 22:55:58.101212 main_disp_path_setup
9352 22:55:58.101297 ovl_layer_smi_id_en
9353 22:55:58.104557 ovl_layer_smi_id_en
9354 22:55:58.104644 ccorr_config
9355 22:55:58.104711 aal_config
9356 22:55:58.108314 gamma_config
9357 22:55:58.108402 postmask_config
9358 22:55:58.111287 dither_config
9359 22:55:58.114753 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9360 22:55:58.120819 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9361 22:55:58.124082 Root Device init finished in 551 msecs
9362 22:55:58.127439 CPU_CLUSTER: 0 init
9363 22:55:58.134245 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9364 22:55:58.140929 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9365 22:55:58.141022 APU_MBOX 0x190000b0 = 0x10001
9366 22:55:58.144008 APU_MBOX 0x190001b0 = 0x10001
9367 22:55:58.147599 APU_MBOX 0x190005b0 = 0x10001
9368 22:55:58.150764 APU_MBOX 0x190006b0 = 0x10001
9369 22:55:58.157418 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9370 22:55:58.167511 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9371 22:55:58.179735 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9372 22:55:58.185943 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9373 22:55:58.197879 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9374 22:55:58.207585 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9375 22:55:58.210747 CPU_CLUSTER: 0 init finished in 81 msecs
9376 22:55:58.213646 Devices initialized
9377 22:55:58.216772 Show all devs... After init.
9378 22:55:58.216869 Root Device: enabled 1
9379 22:55:58.220327 CPU_CLUSTER: 0: enabled 1
9380 22:55:58.223402 CPU: 00: enabled 1
9381 22:55:58.226854 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9382 22:55:58.230005 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9383 22:55:58.233102 ELOG: NV offset 0x57f000 size 0x1000
9384 22:55:58.239965 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9385 22:55:58.246884 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9386 22:55:58.250038 ELOG: Event(17) added with size 13 at 2023-06-05 22:55:58 UTC
9387 22:55:58.256401 out: cmd=0x121: 03 db 21 01 00 00 00 00
9388 22:55:58.259602 in-header: 03 3e 00 00 2c 00 00 00
9389 22:55:58.273162 in-data: 20 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9390 22:55:58.280110 ELOG: Event(A1) added with size 10 at 2023-06-05 22:55:58 UTC
9391 22:55:58.285957 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9392 22:55:58.289487 ELOG: Event(A0) added with size 9 at 2023-06-05 22:55:58 UTC
9393 22:55:58.292815 elog_add_boot_reason: Logged dev mode boot
9394 22:55:58.299499 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9395 22:55:58.302236 Finalize devices...
9396 22:55:58.302347 Devices finalized
9397 22:55:58.309221 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9398 22:55:58.312652 Writing coreboot table at 0xffe64000
9399 22:55:58.315503 0. 000000000010a000-0000000000113fff: RAMSTAGE
9400 22:55:58.318796 1. 0000000040000000-00000000400fffff: RAM
9401 22:55:58.322231 2. 0000000040100000-000000004032afff: RAMSTAGE
9402 22:55:58.328829 3. 000000004032b000-00000000545fffff: RAM
9403 22:55:58.332356 4. 0000000054600000-000000005465ffff: BL31
9404 22:55:58.335505 5. 0000000054660000-00000000ffe63fff: RAM
9405 22:55:58.338416 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9406 22:55:58.345585 7. 0000000100000000-000000023fffffff: RAM
9407 22:55:58.345671 Passing 5 GPIOs to payload:
9408 22:55:58.352042 NAME | PORT | POLARITY | VALUE
9409 22:55:58.355071 EC in RW | 0x000000aa | low | undefined
9410 22:55:58.361904 EC interrupt | 0x00000005 | low | undefined
9411 22:55:58.364867 TPM interrupt | 0x000000ab | high | undefined
9412 22:55:58.368570 SD card detect | 0x00000011 | high | undefined
9413 22:55:58.374844 speaker enable | 0x00000093 | high | undefined
9414 22:55:58.377938 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9415 22:55:58.381446 in-header: 03 f9 00 00 02 00 00 00
9416 22:55:58.381554 in-data: 02 00
9417 22:55:58.384812 ADC[4]: Raw value=894821 ID=7
9418 22:55:58.388236 ADC[3]: Raw value=213440 ID=1
9419 22:55:58.388339 RAM Code: 0x71
9420 22:55:58.391674 ADC[6]: Raw value=74722 ID=0
9421 22:55:58.394422 ADC[5]: Raw value=212700 ID=1
9422 22:55:58.394515 SKU Code: 0x1
9423 22:55:58.401224 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7dbf
9424 22:55:58.404594 coreboot table: 964 bytes.
9425 22:55:58.407387 IMD ROOT 0. 0xfffff000 0x00001000
9426 22:55:58.410969 IMD SMALL 1. 0xffffe000 0x00001000
9427 22:55:58.414291 RO MCACHE 2. 0xffffc000 0x00001104
9428 22:55:58.417796 CONSOLE 3. 0xfff7c000 0x00080000
9429 22:55:58.421175 FMAP 4. 0xfff7b000 0x00000452
9430 22:55:58.424389 TIME STAMP 5. 0xfff7a000 0x00000910
9431 22:55:58.427807 VBOOT WORK 6. 0xfff66000 0x00014000
9432 22:55:58.431126 RAMOOPS 7. 0xffe66000 0x00100000
9433 22:55:58.434353 COREBOOT 8. 0xffe64000 0x00002000
9434 22:55:58.434440 IMD small region:
9435 22:55:58.437852 IMD ROOT 0. 0xffffec00 0x00000400
9436 22:55:58.443826 VPD 1. 0xffffeba0 0x0000004c
9437 22:55:58.447040 MMC STATUS 2. 0xffffeb80 0x00000004
9438 22:55:58.450452 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9439 22:55:58.453805 Probing TPM: done!
9440 22:55:58.457199 Connected to device vid:did:rid of 1ae0:0028:00
9441 22:55:58.467404 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9442 22:55:58.470624 Initialized TPM device CR50 revision 0
9443 22:55:58.474117 Checking cr50 for pending updates
9444 22:55:58.477814 Reading cr50 TPM mode
9445 22:55:58.486393 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9446 22:55:58.492876 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9447 22:55:58.533519 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9448 22:55:58.536300 Checking segment from ROM address 0x40100000
9449 22:55:58.548398 Checking segment from ROM address 0x4010001c
9450 22:55:58.548504 Loading segment from ROM address 0x40100000
9451 22:55:58.548573 code (compression=0)
9452 22:55:58.556718 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9453 22:55:58.562809 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9454 22:55:58.562939 it's not compressed!
9455 22:55:58.569683 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9456 22:55:58.575958 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9457 22:55:58.593466 Loading segment from ROM address 0x4010001c
9458 22:55:58.593580 Entry Point 0x80000000
9459 22:55:58.597081 Loaded segments
9460 22:55:58.600351 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9461 22:55:58.606531 Jumping to boot code at 0x80000000(0xffe64000)
9462 22:55:58.613329 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9463 22:55:58.620032 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9464 22:55:58.627977 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9465 22:55:58.631281 Checking segment from ROM address 0x40100000
9466 22:55:58.634529 Checking segment from ROM address 0x4010001c
9467 22:55:58.641256 Loading segment from ROM address 0x40100000
9468 22:55:58.641341 code (compression=1)
9469 22:55:58.647926 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9470 22:55:58.657744 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9471 22:55:58.657833 using LZMA
9472 22:55:58.666606 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9473 22:55:58.672726 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9474 22:55:58.676274 Loading segment from ROM address 0x4010001c
9475 22:55:58.679529 Entry Point 0x54601000
9476 22:55:58.679617 Loaded segments
9477 22:55:58.683078 NOTICE: MT8192 bl31_setup
9478 22:55:58.689873 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9479 22:55:58.693384 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9480 22:55:58.696465 WARNING: region 0:
9481 22:55:58.700017 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9482 22:55:58.700103 WARNING: region 1:
9483 22:55:58.706390 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9484 22:55:58.709845 WARNING: region 2:
9485 22:55:58.713074 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9486 22:55:58.716559 WARNING: region 3:
9487 22:55:58.719833 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9488 22:55:58.723290 WARNING: region 4:
9489 22:55:58.729452 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9490 22:55:58.729542 WARNING: region 5:
9491 22:55:58.732938 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9492 22:55:58.736175 WARNING: region 6:
9493 22:55:58.739537 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9494 22:55:58.742925 WARNING: region 7:
9495 22:55:58.746293 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9496 22:55:58.752895 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9497 22:55:58.756180 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9498 22:55:58.762767 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9499 22:55:58.765884 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9500 22:55:58.769751 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9501 22:55:58.775942 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9502 22:55:58.778963 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9503 22:55:58.782710 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9504 22:55:58.788880 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9505 22:55:58.792689 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9506 22:55:58.798998 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9507 22:55:58.802739 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9508 22:55:58.805437 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9509 22:55:58.812018 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9510 22:55:58.815695 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9511 22:55:58.818551 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9512 22:55:58.825516 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9513 22:55:58.828709 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9514 22:55:58.835519 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9515 22:55:58.838804 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9516 22:55:58.842080 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9517 22:55:58.848417 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9518 22:55:58.851753 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9519 22:55:58.858589 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9520 22:55:58.862069 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9521 22:55:58.865308 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9522 22:55:58.871768 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9523 22:55:58.875033 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9524 22:55:58.881773 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9525 22:55:58.885518 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9526 22:55:58.888715 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9527 22:55:58.895200 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9528 22:55:58.898314 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9529 22:55:58.901896 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9530 22:55:58.904944 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9531 22:55:58.911965 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9532 22:55:58.914787 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9533 22:55:58.918358 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9534 22:55:58.921503 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9535 22:55:58.928162 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9536 22:55:58.931543 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9537 22:55:58.935138 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9538 22:55:58.941530 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9539 22:55:58.944656 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9540 22:55:58.948156 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9541 22:55:58.951588 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9542 22:55:58.957747 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9543 22:55:58.961534 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9544 22:55:58.964454 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9545 22:55:58.971235 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9546 22:55:58.974457 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9547 22:55:58.981230 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9548 22:55:58.984587 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9549 22:55:58.987942 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9550 22:55:58.994579 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9551 22:55:58.997693 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9552 22:55:59.004271 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9553 22:55:59.008050 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9554 22:55:59.014479 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9555 22:55:59.017774 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9556 22:55:59.024264 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9557 22:55:59.027672 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9558 22:55:59.031032 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9559 22:55:59.037850 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9560 22:55:59.041164 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9561 22:55:59.047275 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9562 22:55:59.051058 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9563 22:55:59.057282 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9564 22:55:59.060716 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9565 22:55:59.064371 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9566 22:55:59.070726 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9567 22:55:59.074497 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9568 22:55:59.080818 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9569 22:55:59.084313 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9570 22:55:59.091052 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9571 22:55:59.094366 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9572 22:55:59.100984 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9573 22:55:59.103718 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9574 22:55:59.107272 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9575 22:55:59.113980 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9576 22:55:59.117138 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9577 22:55:59.124052 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9578 22:55:59.127237 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9579 22:55:59.133735 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9580 22:55:59.136951 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9581 22:55:59.140682 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9582 22:55:59.147275 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9583 22:55:59.150675 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9584 22:55:59.157312 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9585 22:55:59.160805 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9586 22:55:59.166847 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9587 22:55:59.170149 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9588 22:55:59.177028 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9589 22:55:59.180454 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9590 22:55:59.183707 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9591 22:55:59.190460 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9592 22:55:59.193812 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9593 22:55:59.197353 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9594 22:55:59.203680 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9595 22:55:59.207201 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9596 22:55:59.210449 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9597 22:55:59.217227 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9598 22:55:59.220344 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9599 22:55:59.223601 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9600 22:55:59.230335 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9601 22:55:59.233325 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9602 22:55:59.240185 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9603 22:55:59.243230 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9604 22:55:59.247056 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9605 22:55:59.253197 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9606 22:55:59.256591 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9607 22:55:59.263324 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9608 22:55:59.266755 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9609 22:55:59.270086 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9610 22:55:59.276781 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9611 22:55:59.279692 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9612 22:55:59.283607 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9613 22:55:59.289785 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9614 22:55:59.293101 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9615 22:55:59.296377 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9616 22:55:59.303025 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9617 22:55:59.306659 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9618 22:55:59.309439 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9619 22:55:59.312711 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9620 22:55:59.319766 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9621 22:55:59.322636 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9622 22:55:59.329712 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9623 22:55:59.332892 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9624 22:55:59.336104 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9625 22:55:59.342835 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9626 22:55:59.346498 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9627 22:55:59.349764 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9628 22:55:59.356103 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9629 22:55:59.359475 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9630 22:55:59.366220 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9631 22:55:59.369242 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9632 22:55:59.376211 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9633 22:55:59.379670 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9634 22:55:59.382348 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9635 22:55:59.389028 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9636 22:55:59.392716 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9637 22:55:59.395806 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9638 22:55:59.402562 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9639 22:55:59.405811 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9640 22:55:59.412876 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9641 22:55:59.415883 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9642 22:55:59.419409 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9643 22:55:59.426146 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9644 22:55:59.429280 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9645 22:55:59.435617 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9646 22:55:59.439169 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9647 22:55:59.442657 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9648 22:55:59.449305 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9649 22:55:59.452472 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9650 22:55:59.459241 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9651 22:55:59.462248 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9652 22:55:59.465633 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9653 22:55:59.472228 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9654 22:55:59.475552 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9655 22:55:59.478839 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9656 22:55:59.485563 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9657 22:55:59.488799 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9658 22:55:59.495408 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9659 22:55:59.498311 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9660 22:55:59.505145 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9661 22:55:59.508250 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9662 22:55:59.511757 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9663 22:55:59.518263 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9664 22:55:59.521539 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9665 22:55:59.528435 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9666 22:55:59.531586 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9667 22:55:59.535015 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9668 22:55:59.541511 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9669 22:55:59.544573 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9670 22:55:59.550996 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9671 22:55:59.554547 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9672 22:55:59.557791 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9673 22:55:59.564434 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9674 22:55:59.568005 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9675 22:55:59.571106 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9676 22:55:59.577876 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9677 22:55:59.581253 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9678 22:55:59.587787 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9679 22:55:59.590676 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9680 22:55:59.597190 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9681 22:55:59.601014 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9682 22:55:59.603889 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9683 22:55:59.610589 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9684 22:55:59.613690 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9685 22:55:59.620448 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9686 22:55:59.623584 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9687 22:55:59.627302 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9688 22:55:59.633829 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9689 22:55:59.636730 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9690 22:55:59.643506 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9691 22:55:59.646680 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9692 22:55:59.653699 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9693 22:55:59.656682 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9694 22:55:59.660304 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9695 22:55:59.666349 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9696 22:55:59.669677 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9697 22:55:59.676510 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9698 22:55:59.679585 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9699 22:55:59.686501 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9700 22:55:59.689678 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9701 22:55:59.692728 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9702 22:55:59.699342 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9703 22:55:59.702721 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9704 22:55:59.709518 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9705 22:55:59.712838 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9706 22:55:59.719227 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9707 22:55:59.722603 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9708 22:55:59.725905 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9709 22:55:59.732373 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9710 22:55:59.735872 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9711 22:55:59.742591 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9712 22:55:59.745411 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9713 22:55:59.752101 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9714 22:55:59.755541 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9715 22:55:59.758732 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9716 22:55:59.765480 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9717 22:55:59.768797 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9718 22:55:59.775329 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9719 22:55:59.778489 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9720 22:55:59.785221 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9721 22:55:59.788483 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9722 22:55:59.791846 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9723 22:55:59.798574 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9724 22:55:59.801450 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9725 22:55:59.807928 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9726 22:55:59.811426 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9727 22:55:59.815127 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9728 22:55:59.818143 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9729 22:55:59.821475 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9730 22:55:59.827760 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9731 22:55:59.831096 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9732 22:55:59.837562 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9733 22:55:59.841312 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9734 22:55:59.844437 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9735 22:55:59.850639 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9736 22:55:59.853887 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9737 22:55:59.860605 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9738 22:55:59.863913 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9739 22:55:59.867227 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9740 22:55:59.874298 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9741 22:55:59.877288 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9742 22:55:59.880405 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9743 22:55:59.887110 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9744 22:55:59.890123 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9745 22:55:59.893787 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9746 22:55:59.900141 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9747 22:55:59.903877 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9748 22:55:59.910139 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9749 22:55:59.913384 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9750 22:55:59.916820 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9751 22:55:59.923564 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9752 22:55:59.926846 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9753 22:55:59.933364 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9754 22:55:59.936567 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9755 22:55:59.940054 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9756 22:55:59.946451 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9757 22:55:59.949802 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9758 22:55:59.956745 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9759 22:55:59.959859 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9760 22:55:59.962733 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9761 22:55:59.969332 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9762 22:55:59.972741 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9763 22:55:59.976096 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9764 22:55:59.982640 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9765 22:55:59.985465 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9766 22:55:59.989266 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9767 22:55:59.992429 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9768 22:55:59.999102 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9769 22:56:00.002145 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9770 22:56:00.005277 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9771 22:56:00.008790 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9772 22:56:00.015096 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9773 22:56:00.018304 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9774 22:56:00.021735 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9775 22:56:00.025194 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9776 22:56:00.031804 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9777 22:56:00.035327 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9778 22:56:00.038545 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9779 22:56:00.044827 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9780 22:56:00.048171 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9781 22:56:00.055140 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9782 22:56:00.057816 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9783 22:56:00.065042 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9784 22:56:00.067816 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9785 22:56:00.071112 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9786 22:56:00.077742 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9787 22:56:00.081155 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9788 22:56:00.087918 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9789 22:56:00.091130 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9790 22:56:00.098094 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9791 22:56:00.100864 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9792 22:56:00.103983 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9793 22:56:00.110503 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9794 22:56:00.113898 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9795 22:56:00.120635 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9796 22:56:00.124003 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9797 22:56:00.127163 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9798 22:56:00.133740 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9799 22:56:00.137208 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9800 22:56:00.143954 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9801 22:56:00.147416 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9802 22:56:00.153496 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9803 22:56:00.156837 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9804 22:56:00.160320 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9805 22:56:00.167242 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9806 22:56:00.170114 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9807 22:56:00.176841 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9808 22:56:00.180259 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9809 22:56:00.183713 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9810 22:56:00.189925 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9811 22:56:00.193718 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9812 22:56:00.199968 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9813 22:56:00.203450 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9814 22:56:00.209583 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9815 22:56:00.212799 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9816 22:56:00.216540 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9817 22:56:00.222714 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9818 22:56:00.225937 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9819 22:56:00.232925 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9820 22:56:00.236050 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9821 22:56:00.242711 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9822 22:56:00.246106 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9823 22:56:00.249802 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9824 22:56:00.255687 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9825 22:56:00.258836 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9826 22:56:00.265480 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9827 22:56:00.268925 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9828 22:56:00.272341 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9829 22:56:00.278996 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9830 22:56:00.282466 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9831 22:56:00.288685 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9832 22:56:00.292063 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9833 22:56:00.295461 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9834 22:56:00.302126 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9835 22:56:00.305338 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9836 22:56:00.311723 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9837 22:56:00.315157 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9838 22:56:00.321864 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9839 22:56:00.325159 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9840 22:56:00.332029 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9841 22:56:00.334837 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9842 22:56:00.338137 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9843 22:56:00.344981 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9844 22:56:00.348292 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9845 22:56:00.354673 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9846 22:56:00.358007 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9847 22:56:00.361613 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9848 22:56:00.367661 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9849 22:56:00.370863 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9850 22:56:00.377757 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9851 22:56:00.380981 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9852 22:56:00.387787 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9853 22:56:00.390766 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9854 22:56:00.397450 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9855 22:56:00.400704 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9856 22:56:00.403973 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9857 22:56:00.410608 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9858 22:56:00.414035 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9859 22:56:00.420494 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9860 22:56:00.423640 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9861 22:56:00.430007 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9862 22:56:00.433201 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9863 22:56:00.439861 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9864 22:56:00.443657 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9865 22:56:00.447226 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9866 22:56:00.453186 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9867 22:56:00.456652 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9868 22:56:00.463331 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9869 22:56:00.466584 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9870 22:56:00.472878 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9871 22:56:00.476179 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9872 22:56:00.482783 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9873 22:56:00.486319 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9874 22:56:00.489304 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9875 22:56:00.495869 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9876 22:56:00.499581 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9877 22:56:00.506062 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9878 22:56:00.509138 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9879 22:56:00.515754 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9880 22:56:00.519448 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9881 22:56:00.522273 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9882 22:56:00.529088 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9883 22:56:00.532100 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9884 22:56:00.538742 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9885 22:56:00.542345 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9886 22:56:00.548920 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9887 22:56:00.551944 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9888 22:56:00.558743 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9889 22:56:00.562134 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9890 22:56:00.565539 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9891 22:56:00.571763 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9892 22:56:00.575140 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9893 22:56:00.581930 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9894 22:56:00.585202 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9895 22:56:00.591860 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9896 22:56:00.595184 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9897 22:56:00.601796 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9898 22:56:00.604896 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9899 22:56:00.608173 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9900 22:56:00.614708 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9901 22:56:00.618130 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9902 22:56:00.624816 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9903 22:56:00.628083 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9904 22:56:00.634530 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9905 22:56:00.638149 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9906 22:56:00.644479 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9907 22:56:00.647715 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9908 22:56:00.654150 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9909 22:56:00.657892 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9910 22:56:00.664240 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9911 22:56:00.667536 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9912 22:56:00.674299 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9913 22:56:00.677921 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9914 22:56:00.683937 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9915 22:56:00.687279 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9916 22:56:00.693981 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9917 22:56:00.697339 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9918 22:56:00.703785 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9919 22:56:00.707224 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9920 22:56:00.713680 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9921 22:56:00.716941 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9922 22:56:00.723377 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9923 22:56:00.726986 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9924 22:56:00.733490 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9925 22:56:00.736751 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9926 22:56:00.743591 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9927 22:56:00.746591 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9928 22:56:00.753632 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9929 22:56:00.756664 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9930 22:56:00.762993 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9931 22:56:00.763103 INFO: [APUAPC] vio 0
9932 22:56:00.769660 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9933 22:56:00.773218 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9934 22:56:00.776585 INFO: [APUAPC] D0_APC_0: 0x400510
9935 22:56:00.779975 INFO: [APUAPC] D0_APC_1: 0x0
9936 22:56:00.782784 INFO: [APUAPC] D0_APC_2: 0x1540
9937 22:56:00.786181 INFO: [APUAPC] D0_APC_3: 0x0
9938 22:56:00.789411 INFO: [APUAPC] D1_APC_0: 0xffffffff
9939 22:56:00.792857 INFO: [APUAPC] D1_APC_1: 0xffffffff
9940 22:56:00.796421 INFO: [APUAPC] D1_APC_2: 0x3fffff
9941 22:56:00.799540 INFO: [APUAPC] D1_APC_3: 0x0
9942 22:56:00.802995 INFO: [APUAPC] D2_APC_0: 0xffffffff
9943 22:56:00.806330 INFO: [APUAPC] D2_APC_1: 0xffffffff
9944 22:56:00.809137 INFO: [APUAPC] D2_APC_2: 0x3fffff
9945 22:56:00.812700 INFO: [APUAPC] D2_APC_3: 0x0
9946 22:56:00.816103 INFO: [APUAPC] D3_APC_0: 0xffffffff
9947 22:56:00.819381 INFO: [APUAPC] D3_APC_1: 0xffffffff
9948 22:56:00.822278 INFO: [APUAPC] D3_APC_2: 0x3fffff
9949 22:56:00.826156 INFO: [APUAPC] D3_APC_3: 0x0
9950 22:56:00.828994 INFO: [APUAPC] D4_APC_0: 0xffffffff
9951 22:56:00.832455 INFO: [APUAPC] D4_APC_1: 0xffffffff
9952 22:56:00.835894 INFO: [APUAPC] D4_APC_2: 0x3fffff
9953 22:56:00.839146 INFO: [APUAPC] D4_APC_3: 0x0
9954 22:56:00.842519 INFO: [APUAPC] D5_APC_0: 0xffffffff
9955 22:56:00.845803 INFO: [APUAPC] D5_APC_1: 0xffffffff
9956 22:56:00.849058 INFO: [APUAPC] D5_APC_2: 0x3fffff
9957 22:56:00.852168 INFO: [APUAPC] D5_APC_3: 0x0
9958 22:56:00.855619 INFO: [APUAPC] D6_APC_0: 0xffffffff
9959 22:56:00.859127 INFO: [APUAPC] D6_APC_1: 0xffffffff
9960 22:56:00.861839 INFO: [APUAPC] D6_APC_2: 0x3fffff
9961 22:56:00.865504 INFO: [APUAPC] D6_APC_3: 0x0
9962 22:56:00.868575 INFO: [APUAPC] D7_APC_0: 0xffffffff
9963 22:56:00.871687 INFO: [APUAPC] D7_APC_1: 0xffffffff
9964 22:56:00.875404 INFO: [APUAPC] D7_APC_2: 0x3fffff
9965 22:56:00.875486 INFO: [APUAPC] D7_APC_3: 0x0
9966 22:56:00.882026 INFO: [APUAPC] D8_APC_0: 0xffffffff
9967 22:56:00.884904 INFO: [APUAPC] D8_APC_1: 0xffffffff
9968 22:56:00.888464 INFO: [APUAPC] D8_APC_2: 0x3fffff
9969 22:56:00.888546 INFO: [APUAPC] D8_APC_3: 0x0
9970 22:56:00.891590 INFO: [APUAPC] D9_APC_0: 0xffffffff
9971 22:56:00.898516 INFO: [APUAPC] D9_APC_1: 0xffffffff
9972 22:56:00.901866 INFO: [APUAPC] D9_APC_2: 0x3fffff
9973 22:56:00.901948 INFO: [APUAPC] D9_APC_3: 0x0
9974 22:56:00.904871 INFO: [APUAPC] D10_APC_0: 0xffffffff
9975 22:56:00.911070 INFO: [APUAPC] D10_APC_1: 0xffffffff
9976 22:56:00.914352 INFO: [APUAPC] D10_APC_2: 0x3fffff
9977 22:56:00.914434 INFO: [APUAPC] D10_APC_3: 0x0
9978 22:56:00.921715 INFO: [APUAPC] D11_APC_0: 0xffffffff
9979 22:56:00.924659 INFO: [APUAPC] D11_APC_1: 0xffffffff
9980 22:56:00.927782 INFO: [APUAPC] D11_APC_2: 0x3fffff
9981 22:56:00.931196 INFO: [APUAPC] D11_APC_3: 0x0
9982 22:56:00.934650 INFO: [APUAPC] D12_APC_0: 0xffffffff
9983 22:56:00.937386 INFO: [APUAPC] D12_APC_1: 0xffffffff
9984 22:56:00.940824 INFO: [APUAPC] D12_APC_2: 0x3fffff
9985 22:56:00.944374 INFO: [APUAPC] D12_APC_3: 0x0
9986 22:56:00.947727 INFO: [APUAPC] D13_APC_0: 0xffffffff
9987 22:56:00.951070 INFO: [APUAPC] D13_APC_1: 0xffffffff
9988 22:56:00.954511 INFO: [APUAPC] D13_APC_2: 0x3fffff
9989 22:56:00.957662 INFO: [APUAPC] D13_APC_3: 0x0
9990 22:56:00.960587 INFO: [APUAPC] D14_APC_0: 0xffffffff
9991 22:56:00.964253 INFO: [APUAPC] D14_APC_1: 0xffffffff
9992 22:56:00.967473 INFO: [APUAPC] D14_APC_2: 0x3fffff
9993 22:56:00.970768 INFO: [APUAPC] D14_APC_3: 0x0
9994 22:56:00.973876 INFO: [APUAPC] D15_APC_0: 0xffffffff
9995 22:56:00.977028 INFO: [APUAPC] D15_APC_1: 0xffffffff
9996 22:56:00.980757 INFO: [APUAPC] D15_APC_2: 0x3fffff
9997 22:56:00.983779 INFO: [APUAPC] D15_APC_3: 0x0
9998 22:56:00.986942 INFO: [APUAPC] APC_CON: 0x4
9999 22:56:00.987024 INFO: [NOCDAPC] D0_APC_0: 0x0
10000 22:56:00.990427 INFO: [NOCDAPC] D0_APC_1: 0x0
10001 22:56:00.993779 INFO: [NOCDAPC] D1_APC_0: 0x0
10002 22:56:00.997052 INFO: [NOCDAPC] D1_APC_1: 0xfff
10003 22:56:01.000448 INFO: [NOCDAPC] D2_APC_0: 0x0
10004 22:56:01.003345 INFO: [NOCDAPC] D2_APC_1: 0xfff
10005 22:56:01.006576 INFO: [NOCDAPC] D3_APC_0: 0x0
10006 22:56:01.009907 INFO: [NOCDAPC] D3_APC_1: 0xfff
10007 22:56:01.013294 INFO: [NOCDAPC] D4_APC_0: 0x0
10008 22:56:01.016761 INFO: [NOCDAPC] D4_APC_1: 0xfff
10009 22:56:01.019973 INFO: [NOCDAPC] D5_APC_0: 0x0
10010 22:56:01.020081 INFO: [NOCDAPC] D5_APC_1: 0xfff
10011 22:56:01.023323 INFO: [NOCDAPC] D6_APC_0: 0x0
10012 22:56:01.026690 INFO: [NOCDAPC] D6_APC_1: 0xfff
10013 22:56:01.029740 INFO: [NOCDAPC] D7_APC_0: 0x0
10014 22:56:01.033362 INFO: [NOCDAPC] D7_APC_1: 0xfff
10015 22:56:01.036728 INFO: [NOCDAPC] D8_APC_0: 0x0
10016 22:56:01.039493 INFO: [NOCDAPC] D8_APC_1: 0xfff
10017 22:56:01.042958 INFO: [NOCDAPC] D9_APC_0: 0x0
10018 22:56:01.046243 INFO: [NOCDAPC] D9_APC_1: 0xfff
10019 22:56:01.049485 INFO: [NOCDAPC] D10_APC_0: 0x0
10020 22:56:01.053019 INFO: [NOCDAPC] D10_APC_1: 0xfff
10021 22:56:01.056516 INFO: [NOCDAPC] D11_APC_0: 0x0
10022 22:56:01.059289 INFO: [NOCDAPC] D11_APC_1: 0xfff
10023 22:56:01.062526 INFO: [NOCDAPC] D12_APC_0: 0x0
10024 22:56:01.062634 INFO: [NOCDAPC] D12_APC_1: 0xfff
10025 22:56:01.065985 INFO: [NOCDAPC] D13_APC_0: 0x0
10026 22:56:01.069158 INFO: [NOCDAPC] D13_APC_1: 0xfff
10027 22:56:01.072781 INFO: [NOCDAPC] D14_APC_0: 0x0
10028 22:56:01.076053 INFO: [NOCDAPC] D14_APC_1: 0xfff
10029 22:56:01.079135 INFO: [NOCDAPC] D15_APC_0: 0x0
10030 22:56:01.082378 INFO: [NOCDAPC] D15_APC_1: 0xfff
10031 22:56:01.085506 INFO: [NOCDAPC] APC_CON: 0x4
10032 22:56:01.089675 INFO: [APUAPC] set_apusys_apc done
10033 22:56:01.092312 INFO: [DEVAPC] devapc_init done
10034 22:56:01.095692 INFO: GICv3 without legacy support detected.
10035 22:56:01.098848 INFO: ARM GICv3 driver initialized in EL3
10036 22:56:01.105673 INFO: Maximum SPI INTID supported: 639
10037 22:56:01.108788 INFO: BL31: Initializing runtime services
10038 22:56:01.115465 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10039 22:56:01.115548 INFO: SPM: enable CPC mode
10040 22:56:01.122216 INFO: mcdi ready for mcusys-off-idle and system suspend
10041 22:56:01.125366 INFO: BL31: Preparing for EL3 exit to normal world
10042 22:56:01.132033 INFO: Entry point address = 0x80000000
10043 22:56:01.132115 INFO: SPSR = 0x8
10044 22:56:01.137779
10045 22:56:01.137861
10046 22:56:01.137926
10047 22:56:01.141072 Starting depthcharge on Spherion...
10048 22:56:01.141154
10049 22:56:01.141221 Wipe memory regions:
10050 22:56:01.141281
10051 22:56:01.141893 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10052 22:56:01.141996 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10053 22:56:01.142082 Setting prompt string to ['asurada:']
10054 22:56:01.142160 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10055 22:56:01.144711 [0x00000040000000, 0x00000054600000)
10056 22:56:01.266810
10057 22:56:01.266979 [0x00000054660000, 0x00000080000000)
10058 22:56:01.527231
10059 22:56:01.527386 [0x000000821a7280, 0x000000ffe64000)
10060 22:56:02.271601
10061 22:56:02.271759 [0x00000100000000, 0x00000240000000)
10062 22:56:04.161412
10063 22:56:04.164730 Initializing XHCI USB controller at 0x11200000.
10064 22:56:05.202325
10065 22:56:05.206055 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10066 22:56:05.206167
10067 22:56:05.206233
10068 22:56:05.206323
10069 22:56:05.206637 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10071 22:56:05.307048 asurada: tftpboot 192.168.201.1 10597642/tftp-deploy-sufuthx6/kernel/image.itb 10597642/tftp-deploy-sufuthx6/kernel/cmdline
10072 22:56:05.307288 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10073 22:56:05.307452 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10074 22:56:05.311701 tftpboot 192.168.201.1 10597642/tftp-deploy-sufuthx6/kernel/image.itp-deploy-sufuthx6/kernel/cmdline
10075 22:56:05.311803
10076 22:56:05.311871 Waiting for link
10077 22:56:05.471904
10078 22:56:05.472061 R8152: Initializing
10079 22:56:05.472146
10080 22:56:05.475469 Version 6 (ocp_data = 5c30)
10081 22:56:05.475581
10082 22:56:05.478420 R8152: Done initializing
10083 22:56:05.478506
10084 22:56:05.478578 Adding net device
10085 22:56:07.381905
10086 22:56:07.382079 done.
10087 22:56:07.382177
10088 22:56:07.382268 MAC: 00:24:32:30:78:ff
10089 22:56:07.382358
10090 22:56:07.385123 Sending DHCP discover... done.
10091 22:56:07.385212
10092 22:56:07.388617 Waiting for reply... done.
10093 22:56:07.388703
10094 22:56:07.391441 Sending DHCP request... done.
10095 22:56:07.391526
10096 22:56:07.391595 Waiting for reply... done.
10097 22:56:07.391656
10098 22:56:07.394937 My ip is 192.168.201.21
10099 22:56:07.395013
10100 22:56:07.398251 The DHCP server ip is 192.168.201.1
10101 22:56:07.398330
10102 22:56:07.401762 TFTP server IP predefined by user: 192.168.201.1
10103 22:56:07.401841
10104 22:56:07.407933 Bootfile predefined by user: 10597642/tftp-deploy-sufuthx6/kernel/image.itb
10105 22:56:07.408030
10106 22:56:07.411207 Sending tftp read request... done.
10107 22:56:07.411285
10108 22:56:07.414599 Waiting for the transfer...
10109 22:56:07.414682
10110 22:56:07.952634 00000000 ################################################################
10111 22:56:07.952811
10112 22:56:08.500146 00080000 ################################################################
10113 22:56:08.500300
10114 22:56:09.042972 00100000 ################################################################
10115 22:56:09.043126
10116 22:56:09.596093 00180000 ################################################################
10117 22:56:09.596252
10118 22:56:10.133055 00200000 ################################################################
10119 22:56:10.133209
10120 22:56:10.652990 00280000 ################################################################
10121 22:56:10.653143
10122 22:56:11.207200 00300000 ################################################################
10123 22:56:11.207370
10124 22:56:11.752823 00380000 ################################################################
10125 22:56:11.752977
10126 22:56:12.316158 00400000 ################################################################
10127 22:56:12.316351
10128 22:56:12.884350 00480000 ################################################################
10129 22:56:12.884507
10130 22:56:13.490890 00500000 ################################################################
10131 22:56:13.491445
10132 22:56:14.132069 00580000 ################################################################
10133 22:56:14.132215
10134 22:56:14.728122 00600000 ################################################################
10135 22:56:14.728266
10136 22:56:15.326725 00680000 ################################################################
10137 22:56:15.326932
10138 22:56:15.924316 00700000 ################################################################
10139 22:56:15.924482
10140 22:56:16.520648 00780000 ################################################################
10141 22:56:16.520818
10142 22:56:17.117434 00800000 ################################################################
10143 22:56:17.117572
10144 22:56:17.762436 00880000 ################################################################
10145 22:56:17.763002
10146 22:56:18.390119 00900000 ################################################################
10147 22:56:18.390258
10148 22:56:18.947118 00980000 ################################################################
10149 22:56:18.947250
10150 22:56:19.498909 00a00000 ################################################################
10151 22:56:19.499045
10152 22:56:20.061069 00a80000 ################################################################
10153 22:56:20.061205
10154 22:56:20.612597 00b00000 ################################################################
10155 22:56:20.612735
10156 22:56:21.229091 00b80000 ################################################################
10157 22:56:21.229245
10158 22:56:21.853772 00c00000 ################################################################
10159 22:56:21.853922
10160 22:56:22.423889 00c80000 ################################################################
10161 22:56:22.424026
10162 22:56:22.946165 00d00000 ################################################################
10163 22:56:22.946324
10164 22:56:23.476743 00d80000 ################################################################
10165 22:56:23.476882
10166 22:56:24.026538 00e00000 ################################################################
10167 22:56:24.026673
10168 22:56:24.578056 00e80000 ################################################################
10169 22:56:24.578225
10170 22:56:25.092282 00f00000 ################################################################
10171 22:56:25.092424
10172 22:56:25.611885 00f80000 ################################################################
10173 22:56:25.612035
10174 22:56:26.148808 01000000 ################################################################
10175 22:56:26.148941
10176 22:56:26.695477 01080000 ################################################################
10177 22:56:26.695619
10178 22:56:27.247774 01100000 ################################################################
10179 22:56:27.247908
10180 22:56:27.790844 01180000 ################################################################
10181 22:56:27.791003
10182 22:56:28.326156 01200000 ################################################################
10183 22:56:28.326331
10184 22:56:28.863104 01280000 ################################################################
10185 22:56:28.863279
10186 22:56:29.409596 01300000 ################################################################
10187 22:56:29.409747
10188 22:56:29.942463 01380000 ################################################################
10189 22:56:29.942602
10190 22:56:30.492772 01400000 ################################################################
10191 22:56:30.492910
10192 22:56:31.041586 01480000 ################################################################
10193 22:56:31.041732
10194 22:56:31.593411 01500000 ################################################################
10195 22:56:31.593556
10196 22:56:32.123422 01580000 ################################################################
10197 22:56:32.123571
10198 22:56:32.655735 01600000 ################################################################
10199 22:56:32.655884
10200 22:56:33.206634 01680000 ################################################################
10201 22:56:33.206777
10202 22:56:33.745386 01700000 ################################################################
10203 22:56:33.745518
10204 22:56:34.278969 01780000 ################################################################
10205 22:56:34.279108
10206 22:56:34.831370 01800000 ################################################################
10207 22:56:34.831508
10208 22:56:35.388781 01880000 ################################################################
10209 22:56:35.388930
10210 22:56:35.942800 01900000 ################################################################
10211 22:56:35.942986
10212 22:56:36.504356 01980000 ################################################################
10213 22:56:36.504506
10214 22:56:37.158088 01a00000 ################################################################
10215 22:56:37.158653
10216 22:56:37.842267 01a80000 ################################################################
10217 22:56:37.842877
10218 22:56:38.427829 01b00000 ################################################################
10219 22:56:38.427965
10220 22:56:38.977970 01b80000 ################################################################
10221 22:56:38.978103
10222 22:56:39.516077 01c00000 ################################################################
10223 22:56:39.516208
10224 22:56:40.083212 01c80000 ################################################################
10225 22:56:40.083423
10226 22:56:40.684681 01d00000 ################################################################
10227 22:56:40.684819
10228 22:56:41.305858 01d80000 ################################################################
10229 22:56:41.305997
10230 22:56:41.883489 01e00000 ################################################################
10231 22:56:41.883627
10232 22:56:42.485611 01e80000 ################################################################
10233 22:56:42.485759
10234 22:56:43.124009 01f00000 ################################################################
10235 22:56:43.124144
10236 22:56:43.765772 01f80000 ################################################################
10237 22:56:43.765916
10238 22:56:44.410803 02000000 ################################################################
10239 22:56:44.411354
10240 22:56:45.081898 02080000 ################################################################
10241 22:56:45.082473
10242 22:56:45.670279 02100000 ################################################################
10243 22:56:45.670458
10244 22:56:46.245565 02180000 ################################################################
10245 22:56:46.245736
10246 22:56:46.811640 02200000 ################################################################
10247 22:56:46.811792
10248 22:56:47.398732 02280000 ################################################################
10249 22:56:47.398921
10250 22:56:47.947014 02300000 ################################################################
10251 22:56:47.947244
10252 22:56:48.490653 02380000 ################################################################
10253 22:56:48.490878
10254 22:56:49.029405 02400000 ################################################################
10255 22:56:49.029601
10256 22:56:49.556019 02480000 ################################################################
10257 22:56:49.556188
10258 22:56:50.082908 02500000 ################################################################
10259 22:56:50.083159
10260 22:56:50.610980 02580000 ################################################################
10261 22:56:50.611180
10262 22:56:51.133652 02600000 ################################################################
10263 22:56:51.133852
10264 22:56:51.678824 02680000 ################################################################
10265 22:56:51.679654
10266 22:56:52.215398 02700000 ################################################################
10267 22:56:52.215590
10268 22:56:52.741297 02780000 ################################################################
10269 22:56:52.741509
10270 22:56:53.264592 02800000 ################################################################
10271 22:56:53.264835
10272 22:56:53.785190 02880000 ################################################################
10273 22:56:53.785423
10274 22:56:54.307077 02900000 ################################################################
10275 22:56:54.307268
10276 22:56:54.825971 02980000 ################################################################
10277 22:56:54.826126
10278 22:56:55.348440 02a00000 ################################################################
10279 22:56:55.348643
10280 22:56:55.865979 02a80000 ################################################################
10281 22:56:55.866222
10282 22:56:56.389082 02b00000 ################################################################
10283 22:56:56.389284
10284 22:56:56.901050 02b80000 ################################################################
10285 22:56:56.901276
10286 22:56:57.409815 02c00000 ################################################################
10287 22:56:57.410023
10288 22:56:57.921287 02c80000 ################################################################
10289 22:56:57.921490
10290 22:56:58.437695 02d00000 ################################################################
10291 22:56:58.437916
10292 22:56:58.954984 02d80000 ################################################################
10293 22:56:58.955200
10294 22:56:59.468224 02e00000 ################################################################
10295 22:56:59.468445
10296 22:56:59.978490 02e80000 ################################################################
10297 22:56:59.978703
10298 22:57:00.487650 02f00000 ################################################################
10299 22:57:00.487850
10300 22:57:00.948738 02f80000 ######################################################## done.
10301 22:57:00.948903
10302 22:57:00.951717 The bootfile was 50261074 bytes long.
10303 22:57:00.951836
10304 22:57:00.955150 Sending tftp read request... done.
10305 22:57:00.955306
10306 22:57:00.955431 Waiting for the transfer...
10307 22:57:00.955547
10308 22:57:00.958080 00000000 # done.
10309 22:57:00.958168
10310 22:57:00.965473 Command line loaded dynamically from TFTP file: 10597642/tftp-deploy-sufuthx6/kernel/cmdline
10311 22:57:00.965607
10312 22:57:00.978374 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10313 22:57:00.978516
10314 22:57:00.978631 Loading FIT.
10315 22:57:00.978741
10316 22:57:00.981484 Image ramdisk-1 has 40126170 bytes.
10317 22:57:00.981617
10318 22:57:00.985006 Image fdt-1 has 46924 bytes.
10319 22:57:00.985128
10320 22:57:00.988462 Image kernel-1 has 10085945 bytes.
10321 22:57:00.988596
10322 22:57:00.994646 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10323 22:57:00.994778
10324 22:57:01.014361 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10325 22:57:01.014511
10326 22:57:01.017486 Choosing best match conf-1 for compat google,spherion-rev2.
10327 22:57:01.023033
10328 22:57:01.027426 Connected to device vid:did:rid of 1ae0:0028:00
10329 22:57:01.034668
10330 22:57:01.037531 tpm_get_response: command 0x17b, return code 0x0
10331 22:57:01.037656
10332 22:57:01.040792 ec_init: CrosEC protocol v3 supported (256, 248)
10333 22:57:01.045286
10334 22:57:01.048120 tpm_cleanup: add release locality here.
10335 22:57:01.048246
10336 22:57:01.048358 Shutting down all USB controllers.
10337 22:57:01.051396
10338 22:57:01.051522 Removing current net device
10339 22:57:01.051637
10340 22:57:01.058309 Exiting depthcharge with code 4 at timestamp: 89254695
10341 22:57:01.058446
10342 22:57:01.061828 LZMA decompressing kernel-1 to 0x821a6718
10343 22:57:01.061952
10344 22:57:01.064947 LZMA decompressing kernel-1 to 0x40000000
10345 22:57:02.331217
10346 22:57:02.331474 jumping to kernel
10347 22:57:02.332242 end: 2.2.4 bootloader-commands (duration 00:01:01) [common]
10348 22:57:02.332439 start: 2.2.5 auto-login-action (timeout 00:03:24) [common]
10349 22:57:02.332599 Setting prompt string to ['Linux version [0-9]']
10350 22:57:02.332747 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10351 22:57:02.332896 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10352 22:57:02.413050
10353 22:57:02.416265 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10354 22:57:02.419703 start: 2.2.5.1 login-action (timeout 00:03:24) [common]
10355 22:57:02.419937 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10356 22:57:02.420119 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10357 22:57:02.420278 Using line separator: #'\n'#
10358 22:57:02.420402 No login prompt set.
10359 22:57:02.420544 Parsing kernel messages
10360 22:57:02.420674 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10361 22:57:02.420913 [login-action] Waiting for messages, (timeout 00:03:24)
10362 22:57:02.439529 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1612582-arm64-gcc-10-defconfig-arm64-chromebook-7xwc5) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 22:41:02 UTC 2023
10363 22:57:02.442502 [ 0.000000] random: crng init done
10364 22:57:02.449376 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10365 22:57:02.452247 [ 0.000000] efi: UEFI not found.
10366 22:57:02.458968 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10367 22:57:02.468680 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10368 22:57:02.478394 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10369 22:57:02.484972 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10370 22:57:02.492029 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10371 22:57:02.498295 [ 0.000000] printk: bootconsole [mtk8250] enabled
10372 22:57:02.505288 [ 0.000000] NUMA: No NUMA configuration found
10373 22:57:02.511364 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10374 22:57:02.518266 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10375 22:57:02.518516 [ 0.000000] Zone ranges:
10376 22:57:02.524561 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10377 22:57:02.528214 [ 0.000000] DMA32 empty
10378 22:57:02.534695 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10379 22:57:02.537982 [ 0.000000] Movable zone start for each node
10380 22:57:02.541163 [ 0.000000] Early memory node ranges
10381 22:57:02.548119 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10382 22:57:02.554408 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10383 22:57:02.561086 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10384 22:57:02.567799 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10385 22:57:02.574582 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10386 22:57:02.580934 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10387 22:57:02.637403 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10388 22:57:02.643822 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10389 22:57:02.650061 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10390 22:57:02.653439 [ 0.000000] psci: probing for conduit method from DT.
10391 22:57:02.660219 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10392 22:57:02.663441 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10393 22:57:02.670210 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10394 22:57:02.673436 [ 0.000000] psci: SMC Calling Convention v1.2
10395 22:57:02.680195 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10396 22:57:02.682928 [ 0.000000] Detected VIPT I-cache on CPU0
10397 22:57:02.690232 [ 0.000000] CPU features: detected: GIC system register CPU interface
10398 22:57:02.696215 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10399 22:57:02.702704 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10400 22:57:02.709348 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10401 22:57:02.719437 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10402 22:57:02.726036 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10403 22:57:02.729114 [ 0.000000] alternatives: applying boot alternatives
10404 22:57:02.736111 [ 0.000000] Fallback order for Node 0: 0
10405 22:57:02.743040 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10406 22:57:02.746376 [ 0.000000] Policy zone: Normal
10407 22:57:02.759357 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10408 22:57:02.769307 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10409 22:57:02.779730 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10410 22:57:02.789606 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10411 22:57:02.796216 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10412 22:57:02.799302 <6>[ 0.000000] software IO TLB: area num 8.
10413 22:57:02.855677 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10414 22:57:03.005283 <6>[ 0.000000] Memory: 7933756K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 419012K reserved, 32768K cma-reserved)
10415 22:57:03.011223 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10416 22:57:03.018421 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10417 22:57:03.021794 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10418 22:57:03.028065 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10419 22:57:03.034663 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10420 22:57:03.037735 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10421 22:57:03.047967 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10422 22:57:03.054597 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10423 22:57:03.060881 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10424 22:57:03.067614 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10425 22:57:03.071225 <6>[ 0.000000] GICv3: 608 SPIs implemented
10426 22:57:03.074234 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10427 22:57:03.080872 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10428 22:57:03.084324 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10429 22:57:03.090461 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10430 22:57:03.103946 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10431 22:57:03.117212 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10432 22:57:03.123309 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10433 22:57:03.131728 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10434 22:57:03.144768 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10435 22:57:03.151396 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10436 22:57:03.158252 <6>[ 0.009176] Console: colour dummy device 80x25
10437 22:57:03.167770 <6>[ 0.013902] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10438 22:57:03.174375 <6>[ 0.024344] pid_max: default: 32768 minimum: 301
10439 22:57:03.177567 <6>[ 0.029217] LSM: Security Framework initializing
10440 22:57:03.184658 <6>[ 0.034156] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10441 22:57:03.194065 <6>[ 0.041970] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10442 22:57:03.204014 <6>[ 0.051442] cblist_init_generic: Setting adjustable number of callback queues.
10443 22:57:03.207754 <6>[ 0.058943] cblist_init_generic: Setting shift to 3 and lim to 1.
10444 22:57:03.213900 <6>[ 0.065281] cblist_init_generic: Setting shift to 3 and lim to 1.
10445 22:57:03.220509 <6>[ 0.071690] rcu: Hierarchical SRCU implementation.
10446 22:57:03.227543 <6>[ 0.076734] rcu: Max phase no-delay instances is 1000.
10447 22:57:03.233932 <6>[ 0.083755] EFI services will not be available.
10448 22:57:03.237780 <6>[ 0.088726] smp: Bringing up secondary CPUs ...
10449 22:57:03.245127 <6>[ 0.093778] Detected VIPT I-cache on CPU1
10450 22:57:03.251555 <6>[ 0.093850] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10451 22:57:03.258353 <6>[ 0.093882] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10452 22:57:03.261463 <6>[ 0.094217] Detected VIPT I-cache on CPU2
10453 22:57:03.271226 <6>[ 0.094265] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10454 22:57:03.277886 <6>[ 0.094280] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10455 22:57:03.281231 <6>[ 0.094537] Detected VIPT I-cache on CPU3
10456 22:57:03.287569 <6>[ 0.094583] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10457 22:57:03.294252 <6>[ 0.094597] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10458 22:57:03.300974 <6>[ 0.094901] CPU features: detected: Spectre-v4
10459 22:57:03.304546 <6>[ 0.094907] CPU features: detected: Spectre-BHB
10460 22:57:03.307799 <6>[ 0.094913] Detected PIPT I-cache on CPU4
10461 22:57:03.317604 <6>[ 0.094970] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10462 22:57:03.323726 <6>[ 0.094987] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10463 22:57:03.327120 <6>[ 0.095277] Detected PIPT I-cache on CPU5
10464 22:57:03.333781 <6>[ 0.095340] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10465 22:57:03.340495 <6>[ 0.095356] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10466 22:57:03.343725 <6>[ 0.095640] Detected PIPT I-cache on CPU6
10467 22:57:03.353473 <6>[ 0.095707] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10468 22:57:03.360107 <6>[ 0.095723] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10469 22:57:03.363418 <6>[ 0.096020] Detected PIPT I-cache on CPU7
10470 22:57:03.369633 <6>[ 0.096086] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10471 22:57:03.376944 <6>[ 0.096101] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10472 22:57:03.379998 <6>[ 0.096148] smp: Brought up 1 node, 8 CPUs
10473 22:57:03.386107 <6>[ 0.237512] SMP: Total of 8 processors activated.
10474 22:57:03.393158 <6>[ 0.242433] CPU features: detected: 32-bit EL0 Support
10475 22:57:03.399433 <6>[ 0.247796] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10476 22:57:03.406403 <6>[ 0.256596] CPU features: detected: Common not Private translations
10477 22:57:03.412536 <6>[ 0.263071] CPU features: detected: CRC32 instructions
10478 22:57:03.419700 <6>[ 0.268423] CPU features: detected: RCpc load-acquire (LDAPR)
10479 22:57:03.422249 <6>[ 0.274419] CPU features: detected: LSE atomic instructions
10480 22:57:03.429144 <6>[ 0.280201] CPU features: detected: Privileged Access Never
10481 22:57:03.435911 <6>[ 0.285980] CPU features: detected: RAS Extension Support
10482 22:57:03.441894 <6>[ 0.291589] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10483 22:57:03.448351 <6>[ 0.298811] CPU: All CPU(s) started at EL2
10484 22:57:03.452043 <6>[ 0.303154] alternatives: applying system-wide alternatives
10485 22:57:03.462896 <6>[ 0.313858] devtmpfs: initialized
10486 22:57:03.478164 <6>[ 0.322853] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10487 22:57:03.484823 <6>[ 0.332816] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10488 22:57:03.491379 <6>[ 0.340517] pinctrl core: initialized pinctrl subsystem
10489 22:57:03.494638 <6>[ 0.347159] DMI not present or invalid.
10490 22:57:03.501442 <6>[ 0.351566] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10491 22:57:03.511381 <6>[ 0.358441] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10492 22:57:03.517615 <6>[ 0.366022] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10493 22:57:03.527452 <6>[ 0.374236] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10494 22:57:03.530864 <6>[ 0.382478] audit: initializing netlink subsys (disabled)
10495 22:57:03.541254 <5>[ 0.388169] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10496 22:57:03.547642 <6>[ 0.388876] thermal_sys: Registered thermal governor 'step_wise'
10497 22:57:03.554104 <6>[ 0.396135] thermal_sys: Registered thermal governor 'power_allocator'
10498 22:57:03.557073 <6>[ 0.402391] cpuidle: using governor menu
10499 22:57:03.563936 <6>[ 0.413350] NET: Registered PF_QIPCRTR protocol family
10500 22:57:03.570383 <6>[ 0.418834] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10501 22:57:03.577490 <6>[ 0.425933] ASID allocator initialised with 32768 entries
10502 22:57:03.580437 <6>[ 0.432502] Serial: AMBA PL011 UART driver
10503 22:57:03.589766 <4>[ 0.441114] Trying to register duplicate clock ID: 134
10504 22:57:03.645983 <6>[ 0.500391] KASLR enabled
10505 22:57:03.660071 <6>[ 0.508099] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10506 22:57:03.666966 <6>[ 0.515115] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10507 22:57:03.673320 <6>[ 0.521605] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10508 22:57:03.679888 <6>[ 0.528608] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10509 22:57:03.686325 <6>[ 0.535096] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10510 22:57:03.692965 <6>[ 0.542101] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10511 22:57:03.699476 <6>[ 0.548588] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10512 22:57:03.706186 <6>[ 0.555594] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10513 22:57:03.709376 <6>[ 0.563110] ACPI: Interpreter disabled.
10514 22:57:03.718278 <6>[ 0.569519] iommu: Default domain type: Translated
10515 22:57:03.725013 <6>[ 0.574633] iommu: DMA domain TLB invalidation policy: strict mode
10516 22:57:03.728347 <5>[ 0.581291] SCSI subsystem initialized
10517 22:57:03.734700 <6>[ 0.585458] usbcore: registered new interface driver usbfs
10518 22:57:03.741396 <6>[ 0.591191] usbcore: registered new interface driver hub
10519 22:57:03.744594 <6>[ 0.596742] usbcore: registered new device driver usb
10520 22:57:03.751740 <6>[ 0.602833] pps_core: LinuxPPS API ver. 1 registered
10521 22:57:03.761351 <6>[ 0.608025] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10522 22:57:03.764796 <6>[ 0.617372] PTP clock support registered
10523 22:57:03.768089 <6>[ 0.621614] EDAC MC: Ver: 3.0.0
10524 22:57:03.775443 <6>[ 0.626730] FPGA manager framework
10525 22:57:03.782030 <6>[ 0.630413] Advanced Linux Sound Architecture Driver Initialized.
10526 22:57:03.785103 <6>[ 0.637186] vgaarb: loaded
10527 22:57:03.792364 <6>[ 0.640341] clocksource: Switched to clocksource arch_sys_counter
10528 22:57:03.795824 <5>[ 0.646784] VFS: Disk quotas dquot_6.6.0
10529 22:57:03.801672 <6>[ 0.650969] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10530 22:57:03.804929 <6>[ 0.658155] pnp: PnP ACPI: disabled
10531 22:57:03.813539 <6>[ 0.664901] NET: Registered PF_INET protocol family
10532 22:57:03.823248 <6>[ 0.670499] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10533 22:57:03.835098 <6>[ 0.682784] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10534 22:57:03.844678 <6>[ 0.691597] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10535 22:57:03.851389 <6>[ 0.699568] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10536 22:57:03.860868 <6>[ 0.708272] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10537 22:57:03.867559 <6>[ 0.718002] TCP: Hash tables configured (established 65536 bind 65536)
10538 22:57:03.874137 <6>[ 0.724857] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10539 22:57:03.884343 <6>[ 0.732055] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10540 22:57:03.890964 <6>[ 0.739755] NET: Registered PF_UNIX/PF_LOCAL protocol family
10541 22:57:03.897326 <6>[ 0.745918] RPC: Registered named UNIX socket transport module.
10542 22:57:03.900917 <6>[ 0.752071] RPC: Registered udp transport module.
10543 22:57:03.907310 <6>[ 0.757006] RPC: Registered tcp transport module.
10544 22:57:03.913820 <6>[ 0.761936] RPC: Registered tcp NFSv4.1 backchannel transport module.
10545 22:57:03.917053 <6>[ 0.768605] PCI: CLS 0 bytes, default 64
10546 22:57:03.920669 <6>[ 0.773054] Unpacking initramfs...
10547 22:57:03.930220 <6>[ 0.776782] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10548 22:57:03.937110 <6>[ 0.785444] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10549 22:57:03.943915 <6>[ 0.794288] kvm [1]: IPA Size Limit: 40 bits
10550 22:57:03.947144 <6>[ 0.798815] kvm [1]: GICv3: no GICV resource entry
10551 22:57:03.953475 <6>[ 0.803835] kvm [1]: disabling GICv2 emulation
10552 22:57:03.956868 <6>[ 0.808524] kvm [1]: GIC system register CPU interface enabled
10553 22:57:03.963699 <6>[ 0.814690] kvm [1]: vgic interrupt IRQ18
10554 22:57:03.966409 <6>[ 0.819050] kvm [1]: VHE mode initialized successfully
10555 22:57:03.974200 <5>[ 0.825491] Initialise system trusted keyrings
10556 22:57:03.980980 <6>[ 0.830275] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10557 22:57:03.989113 <6>[ 0.840522] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10558 22:57:03.996247 <5>[ 0.846933] NFS: Registering the id_resolver key type
10559 22:57:03.998963 <5>[ 0.852233] Key type id_resolver registered
10560 22:57:04.005871 <5>[ 0.856650] Key type id_legacy registered
10561 22:57:04.012354 <6>[ 0.860932] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10562 22:57:04.019326 <6>[ 0.867854] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10563 22:57:04.025458 <6>[ 0.875564] 9p: Installing v9fs 9p2000 file system support
10564 22:57:04.063034 <5>[ 0.913940] Key type asymmetric registered
10565 22:57:04.066419 <5>[ 0.918276] Asymmetric key parser 'x509' registered
10566 22:57:04.076184 <6>[ 0.923423] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10567 22:57:04.079095 <6>[ 0.931033] io scheduler mq-deadline registered
10568 22:57:04.082574 <6>[ 0.935794] io scheduler kyber registered
10569 22:57:04.101310 <6>[ 0.952858] EINJ: ACPI disabled.
10570 22:57:04.133610 <4>[ 0.977996] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10571 22:57:04.143517 <4>[ 0.988625] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10572 22:57:04.157885 <6>[ 1.009236] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10573 22:57:04.166228 <6>[ 1.017344] printk: console [ttyS0] disabled
10574 22:57:04.193908 <6>[ 1.041995] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10575 22:57:04.200958 <6>[ 1.051468] printk: console [ttyS0] enabled
10576 22:57:04.203965 <6>[ 1.051468] printk: console [ttyS0] enabled
10577 22:57:04.210617 <6>[ 1.060362] printk: bootconsole [mtk8250] disabled
10578 22:57:04.214152 <6>[ 1.060362] printk: bootconsole [mtk8250] disabled
10579 22:57:04.220853 <6>[ 1.071602] SuperH (H)SCI(F) driver initialized
10580 22:57:04.223827 <6>[ 1.076888] msm_serial: driver initialized
10581 22:57:04.237796 <6>[ 1.085859] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10582 22:57:04.247823 <6>[ 1.094407] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10583 22:57:04.254252 <6>[ 1.102950] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10584 22:57:04.264519 <6>[ 1.111578] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10585 22:57:04.273974 <6>[ 1.120286] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10586 22:57:04.280603 <6>[ 1.128999] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10587 22:57:04.290460 <6>[ 1.137540] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10588 22:57:04.297703 <6>[ 1.146351] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10589 22:57:04.306992 <6>[ 1.154896] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10590 22:57:04.320313 <6>[ 1.170763] loop: module loaded
10591 22:57:04.325992 <6>[ 1.176799] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10592 22:57:04.348694 <4>[ 1.200163] mtk-pmic-keys: Failed to locate of_node [id: -1]
10593 22:57:04.355790 <6>[ 1.206975] megasas: 07.719.03.00-rc1
10594 22:57:04.364957 <6>[ 1.216507] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10595 22:57:04.372479 <6>[ 1.223736] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10596 22:57:04.388981 <6>[ 1.240267] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10597 22:57:04.449274 <6>[ 1.293819] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10598 22:57:05.542317 <6>[ 2.393477] Freeing initrd memory: 39180K
10599 22:57:05.552709 <6>[ 2.403835] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10600 22:57:05.563451 <6>[ 2.414786] tun: Universal TUN/TAP device driver, 1.6
10601 22:57:05.566522 <6>[ 2.420847] thunder_xcv, ver 1.0
10602 22:57:05.570173 <6>[ 2.424350] thunder_bgx, ver 1.0
10603 22:57:05.573468 <6>[ 2.427842] nicpf, ver 1.0
10604 22:57:05.583530 <6>[ 2.431846] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10605 22:57:05.586796 <6>[ 2.439322] hns3: Copyright (c) 2017 Huawei Corporation.
10606 22:57:05.593552 <6>[ 2.444908] hclge is initializing
10607 22:57:05.596973 <6>[ 2.448494] e1000: Intel(R) PRO/1000 Network Driver
10608 22:57:05.603650 <6>[ 2.453623] e1000: Copyright (c) 1999-2006 Intel Corporation.
10609 22:57:05.606990 <6>[ 2.459640] e1000e: Intel(R) PRO/1000 Network Driver
10610 22:57:05.613597 <6>[ 2.464855] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10611 22:57:05.620632 <6>[ 2.471040] igb: Intel(R) Gigabit Ethernet Network Driver
10612 22:57:05.627346 <6>[ 2.476691] igb: Copyright (c) 2007-2014 Intel Corporation.
10613 22:57:05.633431 <6>[ 2.482526] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10614 22:57:05.639998 <6>[ 2.489045] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10615 22:57:05.643207 <6>[ 2.495503] sky2: driver version 1.30
10616 22:57:05.649483 <6>[ 2.500481] VFIO - User Level meta-driver version: 0.3
10617 22:57:05.657343 <6>[ 2.508693] usbcore: registered new interface driver usb-storage
10618 22:57:05.663798 <6>[ 2.515138] usbcore: registered new device driver onboard-usb-hub
10619 22:57:05.672548 <6>[ 2.524208] mt6397-rtc mt6359-rtc: registered as rtc0
10620 22:57:05.682440 <6>[ 2.529673] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T22:57:05 UTC (1686005825)
10621 22:57:05.685854 <6>[ 2.539235] i2c_dev: i2c /dev entries driver
10622 22:57:05.702811 <6>[ 2.550934] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10623 22:57:05.709492 <6>[ 2.561108] sdhci: Secure Digital Host Controller Interface driver
10624 22:57:05.716410 <6>[ 2.567547] sdhci: Copyright(c) Pierre Ossman
10625 22:57:05.723239 <6>[ 2.572958] Synopsys Designware Multimedia Card Interface Driver
10626 22:57:05.726239 <6>[ 2.579529] mmc0: CQHCI version 5.10
10627 22:57:05.732517 <6>[ 2.580108] sdhci-pltfm: SDHCI platform and OF driver helper
10628 22:57:05.739728 <6>[ 2.591380] ledtrig-cpu: registered to indicate activity on CPUs
10629 22:57:05.750646 <6>[ 2.598721] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10630 22:57:05.757089 <6>[ 2.606113] usbcore: registered new interface driver usbhid
10631 22:57:05.760522 <6>[ 2.611945] usbhid: USB HID core driver
10632 22:57:05.767111 <6>[ 2.616186] spi_master spi0: will run message pump with realtime priority
10633 22:57:05.810997 <6>[ 2.655759] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10634 22:57:05.829604 <6>[ 2.671090] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10635 22:57:05.833386 <6>[ 2.684650] mmc0: Command Queue Engine enabled
10636 22:57:05.840113 <6>[ 2.685987] cros-ec-spi spi0.0: Chrome EC device registered
10637 22:57:05.846605 <6>[ 2.689395] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10638 22:57:05.849868 <6>[ 2.702524] mmcblk0: mmc0:0001 DA4128 116 GiB
10639 22:57:05.864095 <6>[ 2.712068] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10640 22:57:05.870666 <6>[ 2.713724] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10641 22:57:05.877113 <6>[ 2.723466] NET: Registered PF_PACKET protocol family
10642 22:57:05.880648 <6>[ 2.728425] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10643 22:57:05.886893 <6>[ 2.732718] 9pnet: Installing 9P2000 support
10644 22:57:05.890675 <6>[ 2.738472] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10645 22:57:05.896939 <5>[ 2.742394] Key type dns_resolver registered
10646 22:57:05.903879 <6>[ 2.748214] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10647 22:57:05.906814 <6>[ 2.752611] registered taskstats version 1
10648 22:57:05.910183 <5>[ 2.762997] Loading compiled-in X.509 certificates
10649 22:57:05.944611 <4>[ 2.789641] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10650 22:57:05.954574 <4>[ 2.800318] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10651 22:57:05.964958 <3>[ 2.812958] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10652 22:57:05.977086 <6>[ 2.828486] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10653 22:57:05.983851 <6>[ 2.835336] xhci-mtk 11200000.usb: xHCI Host Controller
10654 22:57:05.990465 <6>[ 2.840846] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10655 22:57:06.000409 <6>[ 2.848697] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10656 22:57:06.007053 <6>[ 2.858123] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10657 22:57:06.013805 <6>[ 2.864217] xhci-mtk 11200000.usb: xHCI Host Controller
10658 22:57:06.020729 <6>[ 2.869699] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10659 22:57:06.026751 <6>[ 2.877355] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10660 22:57:06.033762 <6>[ 2.885068] hub 1-0:1.0: USB hub found
10661 22:57:06.037314 <6>[ 2.889092] hub 1-0:1.0: 1 port detected
10662 22:57:06.046782 <6>[ 2.893430] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10663 22:57:06.049918 <6>[ 2.902179] hub 2-0:1.0: USB hub found
10664 22:57:06.053179 <6>[ 2.906218] hub 2-0:1.0: 1 port detected
10665 22:57:06.061933 <6>[ 2.913544] mtk-msdc 11f70000.mmc: Got CD GPIO
10666 22:57:06.083610 <6>[ 2.931595] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10667 22:57:06.090047 <6>[ 2.939658] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10668 22:57:06.099893 <4>[ 2.947631] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10669 22:57:06.109671 <6>[ 2.957289] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10670 22:57:06.116438 <6>[ 2.965373] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10671 22:57:06.126375 <6>[ 2.973399] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10672 22:57:06.133089 <6>[ 2.981320] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10673 22:57:06.139700 <6>[ 2.989141] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10674 22:57:06.149551 <6>[ 2.996966] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10675 22:57:06.159352 <6>[ 3.007604] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10676 22:57:06.169488 <6>[ 3.015980] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10677 22:57:06.176374 <6>[ 3.024337] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10678 22:57:06.185862 <6>[ 3.032681] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10679 22:57:06.192770 <6>[ 3.041025] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10680 22:57:06.202535 <6>[ 3.049369] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10681 22:57:06.208853 <6>[ 3.057712] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10682 22:57:06.219125 <6>[ 3.066055] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10683 22:57:06.225740 <6>[ 3.074399] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10684 22:57:06.235395 <6>[ 3.082744] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10685 22:57:06.242135 <6>[ 3.091086] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10686 22:57:06.252361 <6>[ 3.099437] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10687 22:57:06.258868 <6>[ 3.107781] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10688 22:57:06.268517 <6>[ 3.116125] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10689 22:57:06.275099 <6>[ 3.124471] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10690 22:57:06.281939 <6>[ 3.133406] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10691 22:57:06.289190 <6>[ 3.140894] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10692 22:57:06.296763 <6>[ 3.147987] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10693 22:57:06.306865 <6>[ 3.155132] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10694 22:57:06.313779 <6>[ 3.162462] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10695 22:57:06.323512 <6>[ 3.169375] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10696 22:57:06.329851 <6>[ 3.178516] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10697 22:57:06.339789 <6>[ 3.187642] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10698 22:57:06.349985 <6>[ 3.196945] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10699 22:57:06.359592 <6>[ 3.206421] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10700 22:57:06.369856 <6>[ 3.215894] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10701 22:57:06.379696 <6>[ 3.225021] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10702 22:57:06.386547 <6>[ 3.234495] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10703 22:57:06.395996 <6>[ 3.243622] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10704 22:57:06.406031 <6>[ 3.252947] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10705 22:57:06.416058 <6>[ 3.263115] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10706 22:57:06.426530 <6>[ 3.274584] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10707 22:57:06.444519 <6>[ 3.292597] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10708 22:57:06.472088 <6>[ 3.322659] hub 2-1:1.0: USB hub found
10709 22:57:06.474589 <6>[ 3.327017] hub 2-1:1.0: 3 ports detected
10710 22:57:06.596450 <6>[ 3.444552] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10711 22:57:06.751226 <6>[ 3.602306] hub 1-1:1.0: USB hub found
10712 22:57:06.754248 <6>[ 3.606738] hub 1-1:1.0: 4 ports detected
10713 22:57:06.828617 <6>[ 3.676858] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10714 22:57:07.076374 <6>[ 3.924620] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10715 22:57:07.209109 <6>[ 4.060794] hub 1-1.4:1.0: USB hub found
10716 22:57:07.212320 <6>[ 4.065452] hub 1-1.4:1.0: 2 ports detected
10717 22:57:07.570643 <6>[ 4.356614] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10718 22:57:07.700260 <6>[ 4.548614] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10719 22:57:18.713498 <6>[ 15.569173] ALSA device list:
10720 22:57:18.719755 <6>[ 15.572430] No soundcards found.
10721 22:57:18.732327 <6>[ 15.584856] Freeing unused kernel memory: 8384K
10722 22:57:18.735981 <6>[ 15.589788] Run /init as init process
10723 22:57:18.766390 <6>[ 15.618601] NET: Registered PF_INET6 protocol family
10724 22:57:18.773011 <6>[ 15.624751] Segment Routing with IPv6
10725 22:57:18.775932 <6>[ 15.628690] In-situ OAM (IOAM) with IPv6
10726 22:57:18.810888 <30>[ 15.643394] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10727 22:57:18.813805 <30>[ 15.667302] systemd[1]: Detected architecture arm64.
10728 22:57:18.817608
10729 22:57:18.820896 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10730 22:57:18.821372
10731 22:57:18.836729 <30>[ 15.688740] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10732 22:57:18.987804 <30>[ 15.837197] systemd[1]: Queued start job for default target Graphical Interface.
10733 22:57:19.021098 <30>[ 15.873985] systemd[1]: Created slice system-getty.slice.
10734 22:57:19.027492 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10735 22:57:19.044059 <30>[ 15.897243] systemd[1]: Created slice system-modprobe.slice.
10736 22:57:19.050623 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10737 22:57:19.071859 <30>[ 15.921758] systemd[1]: Created slice system-serial\x2dgetty.slice.
10738 22:57:19.078655 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10739 22:57:19.092760 <30>[ 15.945084] systemd[1]: Created slice User and Session Slice.
10740 22:57:19.098790 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10741 22:57:19.119460 <30>[ 15.968837] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10742 22:57:19.128849 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10743 22:57:19.143257 <30>[ 15.992712] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10744 22:57:19.149646 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10745 22:57:19.170644 <30>[ 16.016683] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10746 22:57:19.177181 <30>[ 16.028707] systemd[1]: Reached target Local Encrypted Volumes.
10747 22:57:19.183825 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10748 22:57:19.200320 <30>[ 16.052985] systemd[1]: Reached target Paths.
10749 22:57:19.204003 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10750 22:57:19.220531 <30>[ 16.072665] systemd[1]: Reached target Remote File Systems.
10751 22:57:19.226544 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10752 22:57:19.239991 <30>[ 16.092636] systemd[1]: Reached target Slices.
10753 22:57:19.243407 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10754 22:57:19.259726 <30>[ 16.112601] systemd[1]: Reached target Swap.
10755 22:57:19.262950 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10756 22:57:19.283138 <30>[ 16.132967] systemd[1]: Listening on initctl Compatibility Named Pipe.
10757 22:57:19.290160 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10758 22:57:19.296637 <30>[ 16.147699] systemd[1]: Listening on Journal Audit Socket.
10759 22:57:19.303137 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10760 22:57:19.316064 <30>[ 16.168870] systemd[1]: Listening on Journal Socket (/dev/log).
10761 22:57:19.322489 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10762 22:57:19.340369 <30>[ 16.193406] systemd[1]: Listening on Journal Socket.
10763 22:57:19.346824 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10764 22:57:19.363239 <30>[ 16.213035] systemd[1]: Listening on Network Service Netlink Socket.
10765 22:57:19.370077 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10766 22:57:19.384328 <30>[ 16.237388] systemd[1]: Listening on udev Control Socket.
10767 22:57:19.390738 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10768 22:57:19.408781 <30>[ 16.261338] systemd[1]: Listening on udev Kernel Socket.
10769 22:57:19.415487 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10770 22:57:19.448090 <30>[ 16.300792] systemd[1]: Mounting Huge Pages File System...
10771 22:57:19.454586 Mounting [0;1;39mHuge Pages File System[0m...
10772 22:57:19.469955 <30>[ 16.322707] systemd[1]: Mounting POSIX Message Queue File System...
10773 22:57:19.476350 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10774 22:57:19.494408 <30>[ 16.346680] systemd[1]: Mounting Kernel Debug File System...
10775 22:57:19.500565 Mounting [0;1;39mKernel Debug File System[0m...
10776 22:57:19.519637 <30>[ 16.368925] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10777 22:57:19.530994 <30>[ 16.379913] systemd[1]: Starting Create list of static device nodes for the current kernel...
10778 22:57:19.537160 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10779 22:57:19.554314 <30>[ 16.406930] systemd[1]: Starting Load Kernel Module configfs...
10780 22:57:19.560679 Starting [0;1;39mLoad Kernel Module configfs[0m...
10781 22:57:19.578057 <30>[ 16.430911] systemd[1]: Starting Load Kernel Module drm...
10782 22:57:19.584609 Starting [0;1;39mLoad Kernel Module drm[0m...
10783 22:57:19.603899 <30>[ 16.452821] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10784 22:57:19.614191 <30>[ 16.466572] systemd[1]: Starting Journal Service...
10785 22:57:19.617369 Starting [0;1;39mJournal Service[0m...
10786 22:57:19.634471 <30>[ 16.487159] systemd[1]: Starting Load Kernel Modules...
10787 22:57:19.641171 Starting [0;1;39mLoad Kernel Modules[0m...
10788 22:57:19.662139 <30>[ 16.511607] systemd[1]: Starting Remount Root and Kernel File Systems...
10789 22:57:19.668696 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10790 22:57:19.686819 <30>[ 16.539126] systemd[1]: Starting Coldplug All udev Devices...
10791 22:57:19.692880 Starting [0;1;39mColdplug All udev Devices[0m...
10792 22:57:19.710481 <30>[ 16.563382] systemd[1]: Mounted Huge Pages File System.
10793 22:57:19.717385 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10794 22:57:19.732305 <30>[ 16.585118] systemd[1]: Started Journal Service.
10795 22:57:19.738821 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10796 22:57:19.753478 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10797 22:57:19.768685 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10798 22:57:19.788291 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10799 22:57:19.806007 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10800 22:57:19.821950 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10801 22:57:19.837262 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10802 22:57:19.856719 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10803 22:57:19.872327 See 'systemctl status systemd-remount-fs.service' for details.
10804 22:57:19.921599 Mounting [0;1;39mKernel Configuration File System[0m...
10805 22:57:19.942718 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10806 22:57:19.959659 <46>[ 16.809467] systemd-journald[182]: Received client request to flush runtime journal.
10807 22:57:19.988689 Starting [0;1;39mLoad/Save Random Seed[0m...
10808 22:57:20.006856 Starting [0;1;39mApply Kernel Variables[0m...
10809 22:57:20.023284 Starting [0;1;39mCreate System Users[0m...
10810 22:57:20.041553 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10811 22:57:20.060155 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10812 22:57:20.072824 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10813 22:57:20.089189 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10814 22:57:20.104556 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10815 22:57:20.120522 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10816 22:57:20.161032 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10817 22:57:20.183332 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10818 22:57:20.196293 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10819 22:57:20.215809 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10820 22:57:20.257048 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10821 22:57:20.279950 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10822 22:57:20.296906 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10823 22:57:20.316765 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10824 22:57:20.376895 Starting [0;1;39mNetwork Service[0m...
10825 22:57:20.398328 Starting [0;1;39mNetwork Time Synchronization[0m...
10826 22:57:20.424975 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10827 22:57:20.456201 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10828 22:57:20.477528 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10829 22:57:20.511126 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10830 22:57:20.535592 <6>[ 17.384834] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10831 22:57:20.545625 <6>[ 17.394879] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10832 22:57:20.549094 <6>[ 17.395446] remoteproc remoteproc0: scp is available
10833 22:57:20.558453 <3>[ 17.403823] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10834 22:57:20.561602 <6>[ 17.409789] remoteproc remoteproc0: powering up scp
10835 22:57:20.572201 <6>[ 17.411237] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10836 22:57:20.581714 <6>[ 17.411259] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10837 22:57:20.588547 <3>[ 17.418928] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10838 22:57:20.598235 <6>[ 17.421344] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10839 22:57:20.604950 <3>[ 17.432982] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10840 22:57:20.611690 <4>[ 17.434506] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10841 22:57:20.621257 <4>[ 17.436595] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10842 22:57:20.624968 <6>[ 17.438990] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10843 22:57:20.631506 <6>[ 17.450835] usbcore: registered new interface driver r8152
10844 22:57:20.641219 <3>[ 17.464824] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10845 22:57:20.647603 <3>[ 17.497512] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10846 22:57:20.657238 <3>[ 17.497528] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10847 22:57:20.663953 <3>[ 17.497539] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10848 22:57:20.670527 <3>[ 17.497547] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10849 22:57:20.680198 <3>[ 17.501994] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10850 22:57:20.693198 Starting [0;1;39mLoad/Save Screen …o<3>[ 17.540960] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10851 22:57:20.703119 f leds:white:kbd<3>[ 17.550371] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10852 22:57:20.706674 _backlight[0m..<6>[ 17.551558] mc: Linux media interface: v0.10
10853 22:57:20.706837 .
10854 22:57:20.716621 <6>[ 17.553704] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10855 22:57:20.726277 <3>[ 17.559809] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10856 22:57:20.732581 <6>[ 17.564570] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10857 22:57:20.739347 <6>[ 17.564579] pci_bus 0000:00: root bus resource [bus 00-ff]
10858 22:57:20.745681 <6>[ 17.564585] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10859 22:57:20.755948 <6>[ 17.564590] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10860 22:57:20.762379 <6>[ 17.564628] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10861 22:57:20.768964 <6>[ 17.564648] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10862 22:57:20.772414 <6>[ 17.564735] pci 0000:00:00.0: supports D1 D2
10863 22:57:20.779009 <6>[ 17.564740] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10864 22:57:20.788681 <6>[ 17.580867] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10865 22:57:20.795725 <6>[ 17.580867] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10866 22:57:20.802084 <6>[ 17.580878] remoteproc remoteproc0: remote processor scp is now up
10867 22:57:20.811708 <6>[ 17.661208] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10868 22:57:20.818469 <3>[ 17.662526] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10869 22:57:20.824710 <6>[ 17.664615] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10870 22:57:20.835155 <6>[ 17.666953] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10871 22:57:20.844423 <6>[ 17.668660] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10872 22:57:20.854655 <3>[ 17.676710] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10873 22:57:20.861199 <6>[ 17.677065] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10874 22:57:20.867942 <6>[ 17.677110] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10875 22:57:20.874270 <6>[ 17.677137] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10876 22:57:20.881207 <6>[ 17.677156] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10877 22:57:20.887998 <6>[ 17.677314] pci 0000:01:00.0: supports D1 D2
10878 22:57:20.894164 <6>[ 17.677322] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10879 22:57:20.900846 <6>[ 17.685259] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10880 22:57:20.911250 <3>[ 17.692488] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10881 22:57:20.917899 <3>[ 17.692507] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10882 22:57:20.927536 <3>[ 17.692516] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10883 22:57:20.934122 <3>[ 17.692654] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10884 22:57:20.940830 <6>[ 17.692656] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10885 22:57:20.950557 <6>[ 17.692753] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10886 22:57:20.957288 <6>[ 17.692769] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10887 22:57:20.967320 <6>[ 17.692789] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10888 22:57:20.974186 <6>[ 17.692808] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10889 22:57:20.980486 <6>[ 17.692825] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10890 22:57:20.987386 <6>[ 17.692841] pci 0000:00:00.0: PCI bridge to [bus 01]
10891 22:57:20.994567 <6>[ 17.692851] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10892 22:57:21.001541 <6>[ 17.693405] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10893 22:57:21.007888 <6>[ 17.706967] videodev: Linux video capture interface: v2.00
10894 22:57:21.017817 <4>[ 17.710976] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10895 22:57:21.023821 <4>[ 17.710989] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10896 22:57:21.033905 <4>[ 17.722733] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10897 22:57:21.036985 <4>[ 17.722733] Fallback method does not support PEC.
10898 22:57:21.043774 <6>[ 17.737230] r8152 2-1.3:1.0 eth0: v1.12.13
10899 22:57:21.050437 <6>[ 17.740162] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10900 22:57:21.054086 <6>[ 17.744916] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10901 22:57:21.064539 <3>[ 17.764599] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10902 22:57:21.068069 <6>[ 17.770764] Bluetooth: Core ver 2.22
10903 22:57:21.075543 <6>[ 17.791460] usbcore: registered new interface driver cdc_ether
10904 22:57:21.078428 <6>[ 17.795161] NET: Registered PF_BLUETOOTH protocol family
10905 22:57:21.088527 <3>[ 17.799072] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10906 22:57:21.095236 <3>[ 17.819045] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10907 22:57:21.102018 <6>[ 17.824226] Bluetooth: HCI device and connection manager initialized
10908 22:57:21.108501 <6>[ 17.825589] usbcore: registered new interface driver r8153_ecm
10909 22:57:21.118304 <3>[ 17.858106] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10910 22:57:21.121461 <6>[ 17.859867] Bluetooth: HCI socket layer initialized
10911 22:57:21.131762 <6>[ 17.867321] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10912 22:57:21.134740 <6>[ 17.874712] Bluetooth: L2CAP socket layer initialized
10913 22:57:21.148317 <6>[ 17.889223] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10914 22:57:21.155183 <6>[ 17.893091] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10915 22:57:21.158823 <6>[ 17.896472] Bluetooth: SCO socket layer initialized
10916 22:57:21.168637 <6>[ 17.898952] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10917 22:57:21.175226 <6>[ 17.900742] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10918 22:57:21.183015 <6>[ 17.901776] usbcore: registered new interface driver uvcvideo
10919 22:57:21.189230 <6>[ 17.908795] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10920 22:57:21.195807 <3>[ 17.929609] power_supply sbs-5-000b: driver failed to report `capacity' property: -6
10921 22:57:21.202917 <6>[ 17.947038] usbcore: registered new interface driver btusb
10922 22:57:21.212792 <4>[ 17.955296] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10923 22:57:21.222215 <3>[ 17.970485] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10924 22:57:21.228966 <3>[ 17.976372] Bluetooth: hci0: Failed to load firmware file (-2)
10925 22:57:21.235639 <3>[ 18.025023] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10926 22:57:21.242882 <3>[ 18.025914] Bluetooth: hci0: Failed to set up firmware (-2)
10927 22:57:21.249711 <5>[ 18.030162] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10928 22:57:21.255816 <5>[ 18.040951] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10929 22:57:21.266277 <4>[ 18.046556] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10930 22:57:21.276386 <3>[ 18.048882] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 22:57:21.286492 <4>[ 18.054779] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10932 22:57:21.293307 <3>[ 18.112835] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10933 22:57:21.300351 <6>[ 18.115205] cfg80211: failed to load regulatory.db
10934 22:57:21.307148 <3>[ 18.125893] power_supply sbs-5-000b: driver failed to report `manufacture_day' property: -6
10935 22:57:21.313410 Starting [0;1;39mNetwork Name Resolution[0m...
10936 22:57:21.329295 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10937 22:57:21.345890 <6>[ 18.195416] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10938 22:57:21.352889 <6>[ 18.202994] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10939 22:57:21.356089 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10940 22:57:21.375852 [[0;32m OK [0m] Finished [0;1;39mLoad/Save <6>[ 18.228511] mt7921e 0000:01:00.0: ASIC revision: 79610010
10941 22:57:21.382406 Screen …s of leds:white:kbd_backlight[0m.
10942 22:57:21.397812 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10943 22:57:21.481964 <4>[ 18.328413] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10944 22:57:21.569855 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10945 22:57:21.585283 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10946 22:57:21.601511 <4>[ 18.447662] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10947 22:57:21.608092 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10948 22:57:21.624103 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10949 22:57:21.646752 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10950 22:57:21.659509 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10951 22:57:21.675565 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10952 22:57:21.695450 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10953 22:57:21.709191 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10954 22:57:21.722057 <4>[ 18.567217] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10955 22:57:21.728649 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10956 22:57:21.744528 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10957 22:57:21.759730 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10958 22:57:21.779261 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10959 22:57:21.825062 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10960 22:57:21.846447 <4>[ 18.692942] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10961 22:57:21.857871 Starting [0;1;39mUser Login Management[0m...
10962 22:57:21.874502 Starting [0;1;39mPermit User Sessions[0m...
10963 22:57:21.892705 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10964 22:57:21.908437 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10965 22:57:21.924973 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10966 22:57:21.934485 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10967 22:57:21.958809 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10968 22:57:21.971627 <4>[ 18.818257] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10969 22:57:21.981993 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10970 22:57:22.000993 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10971 22:57:22.020247 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10972 22:57:22.039707 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10973 22:57:22.096016 Starting [0;1;39mUpdat<4>[ 18.940464] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10974 22:57:22.098979 e UTMP about System Runlevel Changes[0m...
10975 22:57:22.127436 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10976 22:57:22.172464
10977 22:57:22.173335
10978 22:57:22.176097 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10979 22:57:22.176646
10980 22:57:22.178897 debian-bullseye-arm64 login: root (automatic login)
10981 22:57:22.179298
10982 22:57:22.179668
10983 22:57:22.195410 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 22:41:02 UTC 2023 aarch64
10984 22:57:22.195701
10985 22:57:22.201681 The programs included with the Debian GNU/Linux system are free software;
10986 22:57:22.218469 the exact distribution terms for each program are described<4>[ 19.064298] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10987 22:57:22.218618 in the
10988 22:57:22.221507 individual files in /usr/share/doc/*/copyright.
10989 22:57:22.221613
10990 22:57:22.228672 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10991 22:57:22.231660 permitted by applicable law.
10992 22:57:22.232022 Matched prompt #10: / #
10994 22:57:22.232234 Setting prompt string to ['/ #']
10995 22:57:22.232330 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10997 22:57:22.232522 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10998 22:57:22.232609 start: 2.2.6 expect-shell-connection (timeout 00:03:04) [common]
10999 22:57:22.232683 Setting prompt string to ['/ #']
11000 22:57:22.232745 Forcing a shell prompt, looking for ['/ #']
11002 22:57:22.282963 / #
11003 22:57:22.283258 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11004 22:57:22.283446 Waiting using forced prompt support (timeout 00:02:30)
11005 22:57:22.287911
11006 22:57:22.288305 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11007 22:57:22.288518 start: 2.2.7 export-device-env (timeout 00:03:04) [common]
11008 22:57:22.288707 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11009 22:57:22.288896 end: 2.2 depthcharge-retry (duration 00:01:56) [common]
11010 22:57:22.289035 end: 2 depthcharge-action (duration 00:01:56) [common]
11011 22:57:22.289175 start: 3 lava-test-retry (timeout 00:07:42) [common]
11012 22:57:22.289348 start: 3.1 lava-test-shell (timeout 00:07:42) [common]
11013 22:57:22.289473 Using namespace: common
11015 22:57:22.389960 / # #
11016 22:57:22.390126 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11017 22:57:22.390283 <4>[ 19.186805] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11018 22:57:22.394977 #
11019 22:57:22.395370 Using /lava-10597642
11021 22:57:22.495803 / # export SHELL=/bin/sh
11022 22:57:22.496031 <4>[ 19.306438] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11023 22:57:22.500406 export SHELL=/bin/sh
11025 22:57:22.600934 / # . /lava-10597642/environment
11026 22:57:22.601217 . /lava-10597642/environment<4>[ 19.426326] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11027 22:57:22.601314 <6>[ 19.431728] IPv6: ADDRCONF(NETDEV_CHANGE): enx0024323078ff: link becomes ready
11028 22:57:22.601395 <6>[ 19.445399] r8152 2-1.3:1.0 enx0024323078ff: carrier on
11029 22:57:22.605884
11031 22:57:22.706711 / # /lava-10597642/bin/lava-test-runner /lava-10597642/0
11032 22:57:22.707253 Test shell timeout: 10s (minimum of the action and connection timeout)
11033 22:57:22.709372 /lava-10597642/bin/lava-test-runner /lava-10597642/0<3>[ 19.552702] mt7921e 0000:01:00.0: hardware init failed
11034 22:57:22.712881
11035 22:57:22.755351 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11036 22:57:22.755899 + cd /lava-10597642/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11037 22:57:22.756284 + cat uuid
11038 22:57:22.756638 + UUID=10597642_1.5.2.3.1
11039 22:57:22.756971 + set +x
11040 22:57:22.757297 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 10597642_1.5.2.3.1>
11041 22:57:22.757948 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 10597642_1.5.2.3.1
11042 22:57:22.758360 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (10597642_1.5.2.3.1)
11043 22:57:22.758798 Skipping test definition patterns.
11044 22:57:22.759472 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11045 22:57:22.761064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11046 22:57:22.761912 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11048 22:57:22.771246 device: /dev/vide<4>[ 19.619317] use of bytesused == 0 is deprecated and will be removed in the future,
11049 22:57:22.774424 <4>[ 19.627411] use the actual size instead.
11050 22:57:22.774943 o2
11051 22:57:22.781286 <4>[ 19.634082] ------------[ cut here ]------------
11052 22:57:22.787611 <4>[ 19.638966] get_vaddr_frames() cannot follow VM_IO mapping
11053 22:57:22.797552 <4>[ 19.639103] WARNING: CPU: 7 PID: 315 at drivers/media/common/videobuf2/frame_vector.c:59 get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11054 22:57:22.847206 <4>[ 19.657201] Modules linked in: mt7921e mt7921_common mt76_connac_lib mt76 mac80211 libarc4 btusb btintel btmtk btrtl btbcm mtk_vcodec_enc mtk_vcodec_common cfg80211 cros_ec_rpmsg mtk_vpu uvcvideo v4l2_mem2mem videobuf2_dma_contig videobuf2_vmalloc r8153_ecm videobuf2_memops videobuf2_v4l2 bluetooth cdc_ether videobuf2_common ecdh_generic usbnet hid_google_hammer ecc videodev rfkill crct10dif_ce mc elan_i2c sbs_battery hid_vivaldi_common cros_ec_chardev elants_i2c r8152 pcie_mediatek_gen3 cros_ec_typec mtk_scp mtk_rpmsg mtk_scp_ipi ip_tables x_tables ipv6
11055 22:57:22.857463 <4>[ 19.706589] CPU: 7 PID: 315 Comm: v4l2-compliance Not tainted 6.1.31 #1
11056 22:57:22.860582 <4>[ 19.713455] Hardware name: Google Spherion (rev0 - 3) (DT)
11057 22:57:22.867202 <4>[ 19.719189] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
11058 22:57:22.873840 <4>[ 19.726402] pc : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11059 22:57:22.880405 <4>[ 19.732501] lr : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11060 22:57:22.883422 <4>[ 19.738597] sp : ffff8000091b3850
11061 22:57:22.890228 <4>[ 19.742160] x29: ffff8000091b3850 x28: ffffa6a172428000 x27: ffffa6a172424238
11062 22:57:22.900077 <4>[ 19.749549] x26: 0000000000000000 x25: ffffa6a1b32db3b8 x24: ffff07820ddcba98
11063 22:57:22.907072 <4>[ 19.756937] x23: ffff07820c11e000 x22: ffff078200d48010 x21: 0000000000000000
11064 22:57:22.913869 <4>[ 19.764324] x20: 00000000fffffff2 x19: ffff07820da52d00 x18: fffffffffffe95b0
11065 22:57:22.920367 <4>[ 19.771711] x17: 0000000000000000 x16: ffffa6a1b148bb60 x15: 0000000000000038
11066 22:57:22.929728 <4>[ 19.779099] x14: ffffa6a1b3bc34a8 x13: 000000000000063c x12: 0000000000000214
11067 22:57:22.936675 <4>[ 19.786486] x11: fffffffffffe95b0 x10: fffffffffffe9578 x9 : 00000000fffff214
11068 22:57:22.942791 <4>[ 19.793873] x8 : ffffa6a1b3bc34a8 x7 : ffffa6a1b3c1b4a8 x6 : 00000000000018f0
11069 22:57:22.949524 <4>[ 19.801260] x5 : ffff07833efa5a18 x4 : 00000000fffff214 x3 : ffff60e18baa2000
11070 22:57:22.959199 <4>[ 19.808646] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff07820dddd880
11071 22:57:22.959456 <4>[ 19.816033] Call trace:
11072 22:57:22.966155 <4>[ 19.818730] get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11073 22:57:22.972487 <4>[ 19.824479] vb2_create_framevec+0x50/0xac [videobuf2_memops]
11074 22:57:22.978928 <4>[ 19.830488] vb2_dc_get_userptr+0x9c/0x310 [videobuf2_dma_contig]
11075 22:57:22.985600 <4>[ 19.836844] __prepare_userptr+0x280/0x410 [videobuf2_common]
11076 22:57:22.989319 <4>[ 19.842853] __buf_prepare+0x1a0/0x244 [videobuf2_common]
11077 22:57:22.995701 <4>[ 19.848515] vb2_core_prepare_buf+0x3c/0x140 [videobuf2_common]
11078 22:57:23.002791 <4>[ 19.854699] vb2_prepare_buf+0x68/0xc0 [videobuf2_v4l2]
11079 22:57:23.009178 <4>[ 19.860195] v4l2_m2m_prepare_buf+0x40/0x90 [v4l2_mem2mem]
11080 22:57:23.015585 <4>[ 19.865957] v4l2_m2m_ioctl_prepare_buf+0x18/0x24 [v4l2_mem2mem]
11081 22:57:23.018633 <4>[ 19.872227] v4l_prepare_buf+0x48/0x60 [videodev]
11082 22:57:23.025238 <4>[ 19.877256] __video_do_ioctl+0x184/0x3d0 [videodev]
11083 22:57:23.028678 <4>[ 19.882507] video_usercopy+0x358/0x680 [videodev]
11084 22:57:23.035490 <4>[ 19.887585] video_ioctl2+0x18/0x30 [videodev]
11085 22:57:23.038475 <4>[ 19.892314] v4l2_ioctl+0x40/0x60 [videodev]
11086 22:57:23.041805 <4>[ 19.896870] __arm64_sys_ioctl+0xa8/0xf0
11087 22:57:23.048505 <4>[ 19.901052] invoke_syscall+0x48/0x114
11088 22:57:23.052075 <4>[ 19.905061] el0_svc_common.constprop.0+0x44/0xec
11089 22:57:23.055118 <4>[ 19.910020] do_el0_svc+0x2c/0xd0
11090 22:57:23.058812 <4>[ 19.913588] el0_svc+0x2c/0x84
11091 22:57:23.061694 <4>[ 19.916902] el0t_64_sync_handler+0xb8/0xc0
11092 22:57:23.068372 <4>[ 19.921336] el0t_64_sync+0x18c/0x190
11093 22:57:23.071847 <4>[ 19.925250] ---[ end trace 0000000000000000 ]---
11094 22:57:23.085012 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11095 22:57:23.094145 v4l2-compliance SHA: 52926c1f2f03 2023-05-25 13:56:39
11096 22:57:23.098779
11097 22:57:23.109838 Compliance test for mtk-vcodec-enc device /dev/video2:
11098 22:57:23.115413
11099 22:57:23.123452 Driver Info:
11100 22:57:23.132705 Driver name : mtk-vcodec-enc
11101 22:57:23.144719 Card type : MT8192 video encoder
11102 22:57:23.154253 Bus info : platform:17020000.vcodec
11103 22:57:23.160470 Driver version : 6.1.31
11104 22:57:23.169608 Capabilities : 0x84204000
11105 22:57:23.179020 Video Memory-to-Memory Multiplanar
11106 22:57:23.188251 Streaming
11107 22:57:23.198072 Extended Pix Format
11108 22:57:23.207251 Device Capabilities
11109 22:57:23.217051 Device Caps : 0x04204000
11110 22:57:23.226777 Video Memory-to-Memory Multiplanar
11111 22:57:23.236595 Streaming
11112 22:57:23.246562 Extended Pix Format
11113 22:57:23.256335 Detected Stateful Encoder
11114 22:57:23.266477
11115 22:57:23.276996 Required ioctls:
11116 22:57:23.290731 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11117 22:57:23.290886 test VIDIOC_QUERYCAP: OK
11118 22:57:23.291169 Received signal: <TESTSET> START Required-ioctls
11119 22:57:23.291262 Starting test_set Required-ioctls
11120 22:57:23.313821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11121 22:57:23.314103 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11123 22:57:23.316773 test invalid ioctls: OK
11124 22:57:23.337081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11125 22:57:23.337214
11126 22:57:23.337492 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11128 22:57:23.347437 Allow for multiple opens:
11129 22:57:23.354053 <LAVA_SIGNAL_TESTSET STOP>
11130 22:57:23.354488 Received signal: <TESTSET> STOP
11131 22:57:23.354683 Closing test_set Required-ioctls
11132 22:57:23.363000 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11133 22:57:23.363492 Received signal: <TESTSET> START Allow-for-multiple-opens
11134 22:57:23.363751 Starting test_set Allow-for-multiple-opens
11135 22:57:23.366224 test second /dev/video2 open: OK
11136 22:57:23.386580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11137 22:57:23.387472 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11139 22:57:23.389921 test VIDIOC_QUERYCAP: OK
11140 22:57:23.410201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11141 22:57:23.410951 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11143 22:57:23.413861 test VIDIOC_G/S_PRIORITY: OK
11144 22:57:23.434191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11145 22:57:23.435105 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11147 22:57:23.437156 test for unlimited opens: OK
11148 22:57:23.457734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11149 22:57:23.458395
11150 22:57:23.459009 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11152 22:57:23.466666 Debug ioctls:
11153 22:57:23.473271 <LAVA_SIGNAL_TESTSET STOP>
11154 22:57:23.474004 Received signal: <TESTSET> STOP
11155 22:57:23.474366 Closing test_set Allow-for-multiple-opens
11156 22:57:23.482646 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11157 22:57:23.483485 Received signal: <TESTSET> START Debug-ioctls
11158 22:57:23.484027 Starting test_set Debug-ioctls
11159 22:57:23.485768 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11160 22:57:23.504956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11161 22:57:23.505802 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11163 22:57:23.511362 test VIDIOC_LOG_STATUS: OK (Not Supported)
11164 22:57:23.529219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11165 22:57:23.529687
11166 22:57:23.530375 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11168 22:57:23.538693 Input ioctls:
11169 22:57:23.544903 <LAVA_SIGNAL_TESTSET STOP>
11170 22:57:23.545660 Received signal: <TESTSET> STOP
11171 22:57:23.546212 Closing test_set Debug-ioctls
11172 22:57:23.554197 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11173 22:57:23.554929 Received signal: <TESTSET> START Input-ioctls
11174 22:57:23.555290 Starting test_set Input-ioctls
11175 22:57:23.557531 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11176 22:57:23.581929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11177 22:57:23.582693 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11179 22:57:23.585420 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11180 22:57:23.602425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11181 22:57:23.603333 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11183 22:57:23.608600 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11184 22:57:23.625808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11185 22:57:23.626501 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11187 22:57:23.632144 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11188 22:57:23.650104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11189 22:57:23.650868 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11191 22:57:23.653844 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11192 22:57:23.675263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11193 22:57:23.675853 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11195 22:57:23.678170 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11196 22:57:23.699230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11197 22:57:23.699584 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11199 22:57:23.702902 Inputs: 0 Audio Inputs: 0 Tuners: 0
11200 22:57:23.710286
11201 22:57:23.726132 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11202 22:57:23.746472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11203 22:57:23.746935 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11205 22:57:23.753140 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11206 22:57:23.770357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11207 22:57:23.771124 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11209 22:57:23.777036 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11210 22:57:23.794105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11211 22:57:23.794731 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11213 22:57:23.800469 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11214 22:57:23.816582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11215 22:57:23.816955 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11217 22:57:23.822727 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11218 22:57:23.841329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11219 22:57:23.841791
11220 22:57:23.842341 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11222 22:57:23.860257 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11223 22:57:23.881256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11224 22:57:23.881827 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11226 22:57:23.887869 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11227 22:57:23.908776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11228 22:57:23.909465 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11230 22:57:23.912397 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11231 22:57:23.929690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11232 22:57:23.930079 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11234 22:57:23.936473 test VIDIOC_G/S_EDID: OK (Not Supported)
11235 22:57:23.954137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11236 22:57:23.954265
11237 22:57:23.954512 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11239 22:57:23.965280 Control ioctls:
11240 22:57:23.972115 <LAVA_SIGNAL_TESTSET STOP>
11241 22:57:23.972890 Received signal: <TESTSET> STOP
11242 22:57:23.973280 Closing test_set Input-ioctls
11243 22:57:23.981597 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11244 22:57:23.982398 Received signal: <TESTSET> START Control-ioctls
11245 22:57:23.982867 Starting test_set Control-ioctls
11246 22:57:23.985424 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11247 22:57:24.009224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11248 22:57:24.009940 test VIDIOC_QUERYCTRL: OK
11249 22:57:24.010763 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11251 22:57:24.029496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11252 22:57:24.030001 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11254 22:57:24.033068 test VIDIOC_G/S_CTRL: OK
11255 22:57:24.052527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11256 22:57:24.052886 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11258 22:57:24.056088 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11259 22:57:24.078131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11260 22:57:24.078879 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11262 22:57:24.087949 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11263 22:57:24.091051 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11264 22:57:24.117399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11265 22:57:24.118289 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11267 22:57:24.119841 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11268 22:57:24.138652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11269 22:57:24.139530 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11271 22:57:24.141173 Standard Controls: 16 Private Controls: 0
11272 22:57:24.147524
11273 22:57:24.158387 Format ioctls:
11274 22:57:24.164940 <LAVA_SIGNAL_TESTSET STOP>
11275 22:57:24.165697 Received signal: <TESTSET> STOP
11276 22:57:24.166290 Closing test_set Control-ioctls
11277 22:57:24.173865 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11278 22:57:24.174614 Received signal: <TESTSET> START Format-ioctls
11279 22:57:24.175000 Starting test_set Format-ioctls
11280 22:57:24.177148 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11281 22:57:24.200597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11282 22:57:24.201324 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11284 22:57:24.203744 test VIDIOC_G/S_PARM: OK
11285 22:57:24.222806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11286 22:57:24.223623 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11288 22:57:24.226315 test VIDIOC_G_FBUF: OK (Not Supported)
11289 22:57:24.249422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11290 22:57:24.250400 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11292 22:57:24.253020 test VIDIOC_G_FMT: OK
11293 22:57:24.271797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11294 22:57:24.272556 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11296 22:57:24.274914 test VIDIOC_TRY_FMT: OK
11297 22:57:24.294104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11298 22:57:24.294857 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11300 22:57:24.304038 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11301 22:57:24.304569 test VIDIOC_S_FMT: FAIL
11302 22:57:24.326355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11303 22:57:24.327329 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11305 22:57:24.329274 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11306 22:57:24.349868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11307 22:57:24.350817 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11309 22:57:24.353118 test Cropping: OK
11310 22:57:24.374327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11311 22:57:24.375140 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11313 22:57:24.377598 test Composing: OK (Not Supported)
11314 22:57:24.398612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11315 22:57:24.399456 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11317 22:57:24.402081 test Scaling: OK (Not Supported)
11318 22:57:24.423438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11319 22:57:24.423882
11320 22:57:24.424518 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11322 22:57:24.433996 Codec ioctls:
11323 22:57:24.441332 <LAVA_SIGNAL_TESTSET STOP>
11324 22:57:24.442056 Received signal: <TESTSET> STOP
11325 22:57:24.442424 Closing test_set Format-ioctls
11326 22:57:24.450787 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11327 22:57:24.451666 Received signal: <TESTSET> START Codec-ioctls
11328 22:57:24.452169 Starting test_set Codec-ioctls
11329 22:57:24.453644 test VIDIOC_(TRY_)ENCODER_CMD: OK
11330 22:57:24.474624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11331 22:57:24.475334 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11333 22:57:24.480362 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11334 22:57:24.498792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11335 22:57:24.499544 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11337 22:57:24.505064 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11338 22:57:24.521902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11339 22:57:24.522147
11340 22:57:24.522554 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11342 22:57:24.532403 Buffer ioctls:
11343 22:57:24.539078 <LAVA_SIGNAL_TESTSET STOP>
11344 22:57:24.539372 Received signal: <TESTSET> STOP
11345 22:57:24.539468 Closing test_set Codec-ioctls
11346 22:57:24.548264 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11347 22:57:24.548611 Received signal: <TESTSET> START Buffer-ioctls
11348 22:57:24.548708 Starting test_set Buffer-ioctls
11349 22:57:24.551948 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11350 22:57:24.575907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11351 22:57:24.576641 test VIDIOC_EXPBUF: OK
11352 22:57:24.577436 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11354 22:57:24.596983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11355 22:57:24.597794 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11357 22:57:24.600528 test Requests: OK (Not Supported)
11358 22:57:24.620836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11359 22:57:24.621400
11360 22:57:24.622054 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11362 22:57:24.631336 Test input 0:
11363 22:57:24.641108
11364 22:57:24.651522 Streaming ioctls:
11365 22:57:24.658383 <LAVA_SIGNAL_TESTSET STOP>
11366 22:57:24.659393 Received signal: <TESTSET> STOP
11367 22:57:24.660029 Closing test_set Buffer-ioctls
11368 22:57:24.666794 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11369 22:57:24.667441 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11370 22:57:24.667768 Starting test_set Streaming-ioctls_Test-input-0
11371 22:57:24.669817 test read/write: OK (Not Supported)
11372 22:57:24.690039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11373 22:57:24.690537 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11375 22:57:24.696563 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2778): node->streamon(q.g_type())
11376 22:57:24.708114 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2825): testBlockingDQBuf(node, q)
11377 22:57:24.712247 test blocking wait: FAIL
11378 22:57:24.741829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11379 22:57:24.742327 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11381 22:57:24.752028 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11382 22:57:24.752444 test MMAP (select): FAIL
11383 22:57:24.780858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11384 22:57:24.781576 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11386 22:57:24.787193 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11387 22:57:24.790259 test MMAP (epoll): FAIL
11388 22:57:24.814875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11389 22:57:24.815519 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11391 22:57:24.824589 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11392 22:57:24.831424 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11393 22:57:24.834591 test USERPTR (select): FAIL
11394 22:57:24.859076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11395 22:57:24.859911 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11397 22:57:24.865670 test DMABUF: Cannot test, specify --expbuf-device
11398 22:57:24.873493
11399 22:57:24.891410 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11400 22:57:24.894423 <LAVA_TEST_RUNNER EXIT>
11401 22:57:24.895215 ok: lava_test_shell seems to have completed
11402 22:57:24.895636 Marking unfinished test run as failed
11404 22:57:24.902604 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11405 22:57:24.903676 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11406 22:57:24.904360 end: 3 lava-test-retry (duration 00:00:03) [common]
11407 22:57:24.905108 start: 4 finalize (timeout 00:07:39) [common]
11408 22:57:24.905904 start: 4.1 power-off (timeout 00:00:30) [common]
11409 22:57:24.907265 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11410 22:57:25.009812 >> Command sent successfully.
11411 22:57:25.013639 Returned 0 in 0 seconds
11412 22:57:25.114195 end: 4.1 power-off (duration 00:00:00) [common]
11414 22:57:25.114694 start: 4.2 read-feedback (timeout 00:07:39) [common]
11415 22:57:25.115167 Listened to connection for namespace 'common' for up to 1s
11416 22:57:26.116030 Finalising connection for namespace 'common'
11417 22:57:26.116216 Disconnecting from shell: Finalise
11418 22:57:26.116315 / #
11419 22:57:26.216829 end: 4.2 read-feedback (duration 00:00:01) [common]
11420 22:57:26.217309 end: 4 finalize (duration 00:00:01) [common]
11421 22:57:26.217719 Cleaning after the job
11422 22:57:26.218132 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597642/tftp-deploy-sufuthx6/ramdisk
11423 22:57:26.228124 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597642/tftp-deploy-sufuthx6/kernel
11424 22:57:26.237733 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597642/tftp-deploy-sufuthx6/dtb
11425 22:57:26.238059 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597642/tftp-deploy-sufuthx6/modules
11426 22:57:26.245032 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10597642
11427 22:57:26.300593 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10597642
11428 22:57:26.300755 Job finished correctly