Boot log: mt8192-asurada-spherion-r0
- Errors: 2
- Kernel Errors: 30
- Boot result: FAIL
- Warnings: 1
- Kernel Warnings: 22
1 22:57:47.821717 lava-dispatcher, installed at version: 2023.05.1
2 22:57:47.821920 start: 0 validate
3 22:57:47.822055 Start time: 2023-06-05 22:57:47.822048+00:00 (UTC)
4 22:57:47.822185 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:57:47.822315 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 22:57:48.107677 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:57:48.108501 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:57:48.400034 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:57:48.400765 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:57:48.691833 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:57:48.692591 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 22:57:48.983952 validate duration: 1.16
14 22:57:48.985176 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:57:48.985738 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:57:48.986194 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:57:48.986816 Not decompressing ramdisk as can be used compressed.
18 22:57:48.987299 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230527.0/arm64/rootfs.cpio.gz
19 22:57:48.987641 saving as /var/lib/lava/dispatcher/tmp/10597681/tftp-deploy-1n2if2r1/ramdisk/rootfs.cpio.gz
20 22:57:48.987959 total size: 27151647 (25MB)
21 22:57:48.992880 progress 0% (0MB)
22 22:57:49.014923 progress 5% (1MB)
23 22:57:49.026155 progress 10% (2MB)
24 22:57:49.035057 progress 15% (3MB)
25 22:57:49.042351 progress 20% (5MB)
26 22:57:49.049368 progress 25% (6MB)
27 22:57:49.056123 progress 30% (7MB)
28 22:57:49.063136 progress 35% (9MB)
29 22:57:49.069995 progress 40% (10MB)
30 22:57:49.076808 progress 45% (11MB)
31 22:57:49.083744 progress 50% (12MB)
32 22:57:49.090495 progress 55% (14MB)
33 22:57:49.097538 progress 60% (15MB)
34 22:57:49.104386 progress 65% (16MB)
35 22:57:49.111544 progress 70% (18MB)
36 22:57:49.118734 progress 75% (19MB)
37 22:57:49.125613 progress 80% (20MB)
38 22:57:49.132858 progress 85% (22MB)
39 22:57:49.139628 progress 90% (23MB)
40 22:57:49.146484 progress 95% (24MB)
41 22:57:49.153281 progress 100% (25MB)
42 22:57:49.153498 25MB downloaded in 0.17s (156.42MB/s)
43 22:57:49.153663 end: 1.1.1 http-download (duration 00:00:00) [common]
45 22:57:49.153901 end: 1.1 download-retry (duration 00:00:00) [common]
46 22:57:49.153992 start: 1.2 download-retry (timeout 00:10:00) [common]
47 22:57:49.154078 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 22:57:49.154214 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 22:57:49.154289 saving as /var/lib/lava/dispatcher/tmp/10597681/tftp-deploy-1n2if2r1/kernel/Image
50 22:57:49.154351 total size: 45746688 (43MB)
51 22:57:49.154411 No compression specified
52 22:57:49.155622 progress 0% (0MB)
53 22:57:49.167172 progress 5% (2MB)
54 22:57:49.178777 progress 10% (4MB)
55 22:57:49.190439 progress 15% (6MB)
56 22:57:49.202078 progress 20% (8MB)
57 22:57:49.213762 progress 25% (10MB)
58 22:57:49.225335 progress 30% (13MB)
59 22:57:49.236968 progress 35% (15MB)
60 22:57:49.248688 progress 40% (17MB)
61 22:57:49.260420 progress 45% (19MB)
62 22:57:49.272168 progress 50% (21MB)
63 22:57:49.283491 progress 55% (24MB)
64 22:57:49.295072 progress 60% (26MB)
65 22:57:49.306518 progress 65% (28MB)
66 22:57:49.318382 progress 70% (30MB)
67 22:57:49.330290 progress 75% (32MB)
68 22:57:49.342020 progress 80% (34MB)
69 22:57:49.353940 progress 85% (37MB)
70 22:57:49.365856 progress 90% (39MB)
71 22:57:49.377498 progress 95% (41MB)
72 22:57:49.389082 progress 100% (43MB)
73 22:57:49.389231 43MB downloaded in 0.23s (185.75MB/s)
74 22:57:49.389380 end: 1.2.1 http-download (duration 00:00:00) [common]
76 22:57:49.389607 end: 1.2 download-retry (duration 00:00:00) [common]
77 22:57:49.389694 start: 1.3 download-retry (timeout 00:10:00) [common]
78 22:57:49.389784 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 22:57:49.389922 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 22:57:49.389993 saving as /var/lib/lava/dispatcher/tmp/10597681/tftp-deploy-1n2if2r1/dtb/mt8192-asurada-spherion-r0.dtb
81 22:57:49.390054 total size: 46924 (0MB)
82 22:57:49.390114 No compression specified
83 22:57:49.391291 progress 69% (0MB)
84 22:57:49.391631 progress 100% (0MB)
85 22:57:49.391786 0MB downloaded in 0.00s (25.89MB/s)
86 22:57:49.391909 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:57:49.392132 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:57:49.392219 start: 1.4 download-retry (timeout 00:10:00) [common]
90 22:57:49.392304 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 22:57:49.392416 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 22:57:49.392484 saving as /var/lib/lava/dispatcher/tmp/10597681/tftp-deploy-1n2if2r1/modules/modules.tar
93 22:57:49.392546 total size: 8552396 (8MB)
94 22:57:49.392607 Using unxz to decompress xz
95 22:57:49.396033 progress 0% (0MB)
96 22:57:49.416763 progress 5% (0MB)
97 22:57:49.440137 progress 10% (0MB)
98 22:57:49.470712 progress 15% (1MB)
99 22:57:49.496226 progress 20% (1MB)
100 22:57:49.521108 progress 25% (2MB)
101 22:57:49.545969 progress 30% (2MB)
102 22:57:49.571826 progress 35% (2MB)
103 22:57:49.596607 progress 40% (3MB)
104 22:57:49.621836 progress 45% (3MB)
105 22:57:49.646635 progress 50% (4MB)
106 22:57:49.671489 progress 55% (4MB)
107 22:57:49.696201 progress 60% (4MB)
108 22:57:49.721799 progress 65% (5MB)
109 22:57:49.747123 progress 70% (5MB)
110 22:57:49.771937 progress 75% (6MB)
111 22:57:49.798697 progress 80% (6MB)
112 22:57:49.825426 progress 85% (6MB)
113 22:57:49.851375 progress 90% (7MB)
114 22:57:49.876075 progress 95% (7MB)
115 22:57:49.901656 progress 100% (8MB)
116 22:57:49.908343 8MB downloaded in 0.52s (15.81MB/s)
117 22:57:49.908636 end: 1.4.1 http-download (duration 00:00:01) [common]
119 22:57:49.908904 end: 1.4 download-retry (duration 00:00:01) [common]
120 22:57:49.909001 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 22:57:49.909100 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 22:57:49.909183 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:57:49.909271 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 22:57:49.909491 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10597681/lava-overlay-bhyjwxcl
125 22:57:49.909620 makedir: /var/lib/lava/dispatcher/tmp/10597681/lava-overlay-bhyjwxcl/lava-10597681/bin
126 22:57:49.909722 makedir: /var/lib/lava/dispatcher/tmp/10597681/lava-overlay-bhyjwxcl/lava-10597681/tests
127 22:57:49.909818 makedir: /var/lib/lava/dispatcher/tmp/10597681/lava-overlay-bhyjwxcl/lava-10597681/results
128 22:57:49.909934 Creating /var/lib/lava/dispatcher/tmp/10597681/lava-overlay-bhyjwxcl/lava-10597681/bin/lava-add-keys
129 22:57:49.910079 Creating /var/lib/lava/dispatcher/tmp/10597681/lava-overlay-bhyjwxcl/lava-10597681/bin/lava-add-sources
130 22:57:49.910207 Creating /var/lib/lava/dispatcher/tmp/10597681/lava-overlay-bhyjwxcl/lava-10597681/bin/lava-background-process-start
131 22:57:49.910337 Creating /var/lib/lava/dispatcher/tmp/10597681/lava-overlay-bhyjwxcl/lava-10597681/bin/lava-background-process-stop
132 22:57:49.910460 Creating /var/lib/lava/dispatcher/tmp/10597681/lava-overlay-bhyjwxcl/lava-10597681/bin/lava-common-functions
133 22:57:49.910582 Creating /var/lib/lava/dispatcher/tmp/10597681/lava-overlay-bhyjwxcl/lava-10597681/bin/lava-echo-ipv4
134 22:57:49.910708 Creating /var/lib/lava/dispatcher/tmp/10597681/lava-overlay-bhyjwxcl/lava-10597681/bin/lava-install-packages
135 22:57:49.910841 Creating /var/lib/lava/dispatcher/tmp/10597681/lava-overlay-bhyjwxcl/lava-10597681/bin/lava-installed-packages
136 22:57:49.910966 Creating /var/lib/lava/dispatcher/tmp/10597681/lava-overlay-bhyjwxcl/lava-10597681/bin/lava-os-build
137 22:57:49.911090 Creating /var/lib/lava/dispatcher/tmp/10597681/lava-overlay-bhyjwxcl/lava-10597681/bin/lava-probe-channel
138 22:57:49.911212 Creating /var/lib/lava/dispatcher/tmp/10597681/lava-overlay-bhyjwxcl/lava-10597681/bin/lava-probe-ip
139 22:57:49.911333 Creating /var/lib/lava/dispatcher/tmp/10597681/lava-overlay-bhyjwxcl/lava-10597681/bin/lava-target-ip
140 22:57:49.911454 Creating /var/lib/lava/dispatcher/tmp/10597681/lava-overlay-bhyjwxcl/lava-10597681/bin/lava-target-mac
141 22:57:49.911579 Creating /var/lib/lava/dispatcher/tmp/10597681/lava-overlay-bhyjwxcl/lava-10597681/bin/lava-target-storage
142 22:57:49.911704 Creating /var/lib/lava/dispatcher/tmp/10597681/lava-overlay-bhyjwxcl/lava-10597681/bin/lava-test-case
143 22:57:49.911825 Creating /var/lib/lava/dispatcher/tmp/10597681/lava-overlay-bhyjwxcl/lava-10597681/bin/lava-test-event
144 22:57:49.911946 Creating /var/lib/lava/dispatcher/tmp/10597681/lava-overlay-bhyjwxcl/lava-10597681/bin/lava-test-feedback
145 22:57:49.912069 Creating /var/lib/lava/dispatcher/tmp/10597681/lava-overlay-bhyjwxcl/lava-10597681/bin/lava-test-raise
146 22:57:49.912191 Creating /var/lib/lava/dispatcher/tmp/10597681/lava-overlay-bhyjwxcl/lava-10597681/bin/lava-test-reference
147 22:57:49.912313 Creating /var/lib/lava/dispatcher/tmp/10597681/lava-overlay-bhyjwxcl/lava-10597681/bin/lava-test-runner
148 22:57:49.912435 Creating /var/lib/lava/dispatcher/tmp/10597681/lava-overlay-bhyjwxcl/lava-10597681/bin/lava-test-set
149 22:57:49.912560 Creating /var/lib/lava/dispatcher/tmp/10597681/lava-overlay-bhyjwxcl/lava-10597681/bin/lava-test-shell
150 22:57:49.912714 Updating /var/lib/lava/dispatcher/tmp/10597681/lava-overlay-bhyjwxcl/lava-10597681/bin/lava-install-packages (oe)
151 22:57:49.912919 Updating /var/lib/lava/dispatcher/tmp/10597681/lava-overlay-bhyjwxcl/lava-10597681/bin/lava-installed-packages (oe)
152 22:57:49.913053 Creating /var/lib/lava/dispatcher/tmp/10597681/lava-overlay-bhyjwxcl/lava-10597681/environment
153 22:57:49.913167 LAVA metadata
154 22:57:49.913244 - LAVA_JOB_ID=10597681
155 22:57:49.913310 - LAVA_DISPATCHER_IP=192.168.201.1
156 22:57:49.913420 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 22:57:49.913489 skipped lava-vland-overlay
158 22:57:49.913566 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 22:57:49.913649 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 22:57:49.913713 skipped lava-multinode-overlay
161 22:57:49.913789 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 22:57:49.913873 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 22:57:49.913950 Loading test definitions
164 22:57:49.914044 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 22:57:49.914119 Using /lava-10597681 at stage 0
166 22:57:49.914415 uuid=10597681_1.5.2.3.1 testdef=None
167 22:57:49.914505 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 22:57:49.914594 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 22:57:49.915109 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 22:57:49.915340 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 22:57:49.915939 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 22:57:49.916177 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 22:57:49.916842 runner path: /var/lib/lava/dispatcher/tmp/10597681/lava-overlay-bhyjwxcl/lava-10597681/0/tests/0_v4l2-compliance-uvc test_uuid 10597681_1.5.2.3.1
176 22:57:49.916999 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 22:57:49.917210 Creating lava-test-runner.conf files
179 22:57:49.917275 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10597681/lava-overlay-bhyjwxcl/lava-10597681/0 for stage 0
180 22:57:49.917364 - 0_v4l2-compliance-uvc
181 22:57:49.917462 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 22:57:49.917553 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 22:57:49.924252 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 22:57:49.924370 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 22:57:49.924462 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 22:57:49.924550 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 22:57:49.924645 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 22:57:50.647510 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 22:57:50.647863 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 22:57:50.647980 extracting modules file /var/lib/lava/dispatcher/tmp/10597681/tftp-deploy-1n2if2r1/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597681/extract-overlay-ramdisk-s6cojb42/ramdisk
191 22:57:50.859588 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 22:57:50.859766 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 22:57:50.859867 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597681/compress-overlay-v2e87bqm/overlay-1.5.2.4.tar.gz to ramdisk
194 22:57:50.859940 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597681/compress-overlay-v2e87bqm/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10597681/extract-overlay-ramdisk-s6cojb42/ramdisk
195 22:57:50.866294 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 22:57:50.866416 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 22:57:50.866510 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 22:57:50.866603 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 22:57:50.866685 Building ramdisk /var/lib/lava/dispatcher/tmp/10597681/extract-overlay-ramdisk-s6cojb42/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10597681/extract-overlay-ramdisk-s6cojb42/ramdisk
200 22:57:51.401021 >> 230342 blocks
201 22:57:55.717900 rename /var/lib/lava/dispatcher/tmp/10597681/extract-overlay-ramdisk-s6cojb42/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10597681/tftp-deploy-1n2if2r1/ramdisk/ramdisk.cpio.gz
202 22:57:55.718329 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 22:57:55.718452 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 22:57:55.718556 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 22:57:55.718669 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10597681/tftp-deploy-1n2if2r1/kernel/Image'
206 22:58:09.989763 Returned 0 in 14 seconds
207 22:58:10.090421 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10597681/tftp-deploy-1n2if2r1/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10597681/tftp-deploy-1n2if2r1/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10597681/tftp-deploy-1n2if2r1/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10597681/tftp-deploy-1n2if2r1/kernel/image.itb
208 22:58:10.648641 output: FIT description: Kernel Image image with one or more FDT blobs
209 22:58:10.648992 output: Created: Mon Jun 5 23:58:10 2023
210 22:58:10.649074 output: Image 0 (kernel-1)
211 22:58:10.649142 output: Description:
212 22:58:10.649206 output: Created: Mon Jun 5 23:58:10 2023
213 22:58:10.649267 output: Type: Kernel Image
214 22:58:10.649326 output: Compression: lzma compressed
215 22:58:10.649384 output: Data Size: 10085945 Bytes = 9849.56 KiB = 9.62 MiB
216 22:58:10.649441 output: Architecture: AArch64
217 22:58:10.649500 output: OS: Linux
218 22:58:10.649556 output: Load Address: 0x00000000
219 22:58:10.649612 output: Entry Point: 0x00000000
220 22:58:10.649667 output: Hash algo: crc32
221 22:58:10.649722 output: Hash value: b2943ff2
222 22:58:10.649776 output: Image 1 (fdt-1)
223 22:58:10.649843 output: Description: mt8192-asurada-spherion-r0
224 22:58:10.649936 output: Created: Mon Jun 5 23:58:10 2023
225 22:58:10.649992 output: Type: Flat Device Tree
226 22:58:10.650045 output: Compression: uncompressed
227 22:58:10.650098 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 22:58:10.650152 output: Architecture: AArch64
229 22:58:10.650205 output: Hash algo: crc32
230 22:58:10.650258 output: Hash value: 1df858fa
231 22:58:10.650311 output: Image 2 (ramdisk-1)
232 22:58:10.650365 output: Description: unavailable
233 22:58:10.650417 output: Created: Mon Jun 5 23:58:10 2023
234 22:58:10.650470 output: Type: RAMDisk Image
235 22:58:10.650523 output: Compression: Unknown Compression
236 22:58:10.650576 output: Data Size: 40125825 Bytes = 39185.38 KiB = 38.27 MiB
237 22:58:10.650629 output: Architecture: AArch64
238 22:58:10.650682 output: OS: Linux
239 22:58:10.650734 output: Load Address: unavailable
240 22:58:10.650787 output: Entry Point: unavailable
241 22:58:10.650849 output: Hash algo: crc32
242 22:58:10.650942 output: Hash value: 086d225a
243 22:58:10.650995 output: Default Configuration: 'conf-1'
244 22:58:10.651047 output: Configuration 0 (conf-1)
245 22:58:10.651100 output: Description: mt8192-asurada-spherion-r0
246 22:58:10.651152 output: Kernel: kernel-1
247 22:58:10.651204 output: Init Ramdisk: ramdisk-1
248 22:58:10.651257 output: FDT: fdt-1
249 22:58:10.651309 output: Loadables: kernel-1
250 22:58:10.651362 output:
251 22:58:10.651556 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 22:58:10.651655 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 22:58:10.651763 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 22:58:10.651875 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 22:58:10.651954 No LXC device requested
256 22:58:10.652034 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 22:58:10.652122 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 22:58:10.652200 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 22:58:10.652267 Checking files for TFTP limit of 4294967296 bytes.
260 22:58:10.652749 end: 1 tftp-deploy (duration 00:00:22) [common]
261 22:58:10.652850 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 22:58:10.652940 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 22:58:10.653061 substitutions:
264 22:58:10.653127 - {DTB}: 10597681/tftp-deploy-1n2if2r1/dtb/mt8192-asurada-spherion-r0.dtb
265 22:58:10.653190 - {INITRD}: 10597681/tftp-deploy-1n2if2r1/ramdisk/ramdisk.cpio.gz
266 22:58:10.653251 - {KERNEL}: 10597681/tftp-deploy-1n2if2r1/kernel/Image
267 22:58:10.653309 - {LAVA_MAC}: None
268 22:58:10.653380 - {PRESEED_CONFIG}: None
269 22:58:10.653475 - {PRESEED_LOCAL}: None
270 22:58:10.653549 - {RAMDISK}: 10597681/tftp-deploy-1n2if2r1/ramdisk/ramdisk.cpio.gz
271 22:58:10.653606 - {ROOT_PART}: None
272 22:58:10.653665 - {ROOT}: None
273 22:58:10.653723 - {SERVER_IP}: 192.168.201.1
274 22:58:10.653792 - {TEE}: None
275 22:58:10.653846 Parsed boot commands:
276 22:58:10.653900 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 22:58:10.654070 Parsed boot commands: tftpboot 192.168.201.1 10597681/tftp-deploy-1n2if2r1/kernel/image.itb 10597681/tftp-deploy-1n2if2r1/kernel/cmdline
278 22:58:10.654160 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 22:58:10.654244 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 22:58:10.654341 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 22:58:10.654427 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 22:58:10.654497 Not connected, no need to disconnect.
283 22:58:10.654571 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 22:58:10.654653 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 22:58:10.654720 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-8'
286 22:58:10.657975 Setting prompt string to ['lava-test: # ']
287 22:58:10.658317 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 22:58:10.658430 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 22:58:10.658534 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 22:58:10.658625 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 22:58:10.658826 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
292 22:58:15.790113 >> Command sent successfully.
293 22:58:15.792421 Returned 0 in 5 seconds
294 22:58:15.892813 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 22:58:15.893386 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 22:58:15.893488 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 22:58:15.893579 Setting prompt string to 'Starting depthcharge on Spherion...'
299 22:58:15.893646 Changing prompt to 'Starting depthcharge on Spherion...'
300 22:58:15.893719 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 22:58:15.893977 [Enter `^Ec?' for help]
302 22:58:16.065580
303 22:58:16.065738
304 22:58:16.065815 F0: 102B 0000
305 22:58:16.065880
306 22:58:16.065942 F3: 1001 0000 [0200]
307 22:58:16.066003
308 22:58:16.069389 F3: 1001 0000
309 22:58:16.069493
310 22:58:16.069567 F7: 102D 0000
311 22:58:16.069632
312 22:58:16.069694 F1: 0000 0000
313 22:58:16.069754
314 22:58:16.073136 V0: 0000 0000 [0001]
315 22:58:16.073225
316 22:58:16.073308 00: 0007 8000
317 22:58:16.073377
318 22:58:16.076232 01: 0000 0000
319 22:58:16.076307
320 22:58:16.076373 BP: 0C00 0209 [0000]
321 22:58:16.076435
322 22:58:16.080002 G0: 1182 0000
323 22:58:16.080077
324 22:58:16.080140 EC: 0000 0021 [4000]
325 22:58:16.080205
326 22:58:16.083757 S7: 0000 0000 [0000]
327 22:58:16.083854
328 22:58:16.083933 CC: 0000 0000 [0001]
329 22:58:16.083996
330 22:58:16.086933 T0: 0000 0040 [010F]
331 22:58:16.087030
332 22:58:16.087098 Jump to BL
333 22:58:16.087162
334 22:58:16.111934
335 22:58:16.112083
336 22:58:16.112184
337 22:58:16.118802 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 22:58:16.122322 ARM64: Exception handlers installed.
339 22:58:16.125655 ARM64: Testing exception
340 22:58:16.129185 ARM64: Done test exception
341 22:58:16.136463 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 22:58:16.147363 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 22:58:16.153232 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 22:58:16.163361 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 22:58:16.169822 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 22:58:16.176505 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 22:58:16.188418 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 22:58:16.195218 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 22:58:16.214862 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 22:58:16.217978 WDT: Last reset was cold boot
351 22:58:16.221749 SPI1(PAD0) initialized at 2873684 Hz
352 22:58:16.224685 SPI5(PAD0) initialized at 992727 Hz
353 22:58:16.228277 VBOOT: Loading verstage.
354 22:58:16.234465 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 22:58:16.238118 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 22:58:16.241200 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 22:58:16.244736 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 22:58:16.251979 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 22:58:16.258458 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 22:58:16.269568 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
361 22:58:16.269658
362 22:58:16.269725
363 22:58:16.280062 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 22:58:16.283205 ARM64: Exception handlers installed.
365 22:58:16.286265 ARM64: Testing exception
366 22:58:16.286367 ARM64: Done test exception
367 22:58:16.293603 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 22:58:16.296841 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 22:58:16.310838 Probing TPM: . done!
370 22:58:16.310935 TPM ready after 0 ms
371 22:58:16.317347 Connected to device vid:did:rid of 1ae0:0028:00
372 22:58:16.324552 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 22:58:16.365925 Initialized TPM device CR50 revision 0
374 22:58:16.377635 tlcl_send_startup: Startup return code is 0
375 22:58:16.377758 TPM: setup succeeded
376 22:58:16.388660 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 22:58:16.397773 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 22:58:16.409535 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 22:58:16.418145 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 22:58:16.421653 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 22:58:16.425171 in-header: 03 07 00 00 08 00 00 00
382 22:58:16.428834 in-data: aa e4 47 04 13 02 00 00
383 22:58:16.432435 Chrome EC: UHEPI supported
384 22:58:16.439095 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 22:58:16.442777 in-header: 03 9d 00 00 08 00 00 00
386 22:58:16.446506 in-data: 10 20 20 08 00 00 00 00
387 22:58:16.446610 Phase 1
388 22:58:16.450132 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 22:58:16.457551 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 22:58:16.464706 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 22:58:16.464828 Recovery requested (1009000e)
392 22:58:16.473738 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 22:58:16.479217 tlcl_extend: response is 0
394 22:58:16.487378 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 22:58:16.492319 tlcl_extend: response is 0
396 22:58:16.498923 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 22:58:16.520093 read SPI 0x210d4 0x2173b: 15147 us, 9045 KB/s, 72.360 Mbps
398 22:58:16.527401 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 22:58:16.527487
400 22:58:16.527553
401 22:58:16.537861 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 22:58:16.537956 ARM64: Exception handlers installed.
403 22:58:16.541399 ARM64: Testing exception
404 22:58:16.544958 ARM64: Done test exception
405 22:58:16.562394 pmic_efuse_setting: Set efuses in 11 msecs
406 22:58:16.571233 pmwrap_interface_init: Select PMIF_VLD_RDY
407 22:58:16.574999 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 22:58:16.577998 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 22:58:16.585121 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 22:58:16.588771 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 22:58:16.592577 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 22:58:16.599998 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 22:58:16.603575 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 22:58:16.607331 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 22:58:16.613531 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 22:58:16.617342 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 22:58:16.620457 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 22:58:16.627609 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 22:58:16.630477 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 22:58:16.637133 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 22:58:16.644020 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 22:58:16.647273 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 22:58:16.654190 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 22:58:16.660802 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 22:58:16.667731 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 22:58:16.670966 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 22:58:16.677950 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 22:58:16.681475 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 22:58:16.687975 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 22:58:16.695407 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 22:58:16.699035 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 22:58:16.705727 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 22:58:16.708782 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 22:58:16.715757 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 22:58:16.718871 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 22:58:16.722602 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 22:58:16.729463 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 22:58:16.733209 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 22:58:16.739760 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 22:58:16.743419 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 22:58:16.750208 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 22:58:16.754318 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 22:58:16.757738 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 22:58:16.764759 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 22:58:16.767745 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 22:58:16.771428 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 22:58:16.777720 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 22:58:16.781393 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 22:58:16.784795 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 22:58:16.791437 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 22:58:16.794410 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 22:58:16.797716 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 22:58:16.804638 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 22:58:16.807744 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 22:58:16.811336 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 22:58:16.814301 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 22:58:16.821158 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 22:58:16.827441 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 22:58:16.837285 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 22:58:16.840954 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 22:58:16.850658 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 22:58:16.857480 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 22:58:16.860757 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 22:58:16.867198 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 22:58:16.870694 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 22:58:16.877721 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
467 22:58:16.884501 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 22:58:16.887559 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 22:58:16.893957 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 22:58:16.902287 [RTC]rtc_get_frequency_meter,154: input=15, output=793
471 22:58:16.905645 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 22:58:16.912277 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 22:58:16.915353 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
474 22:58:16.919087 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 22:58:16.922107 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
476 22:58:16.925869 ADC[4]: Raw value=897040 ID=7
477 22:58:16.928918 ADC[3]: Raw value=213440 ID=1
478 22:58:16.931985 RAM Code: 0x71
479 22:58:16.935724 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 22:58:16.938758 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 22:58:16.949112 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 22:58:16.955819 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 22:58:16.959555 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 22:58:16.962721 in-header: 03 07 00 00 08 00 00 00
485 22:58:16.965742 in-data: aa e4 47 04 13 02 00 00
486 22:58:16.969345 Chrome EC: UHEPI supported
487 22:58:16.973068 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 22:58:16.977294 in-header: 03 d5 00 00 08 00 00 00
489 22:58:16.980726 in-data: 98 20 60 08 00 00 00 00
490 22:58:16.984342 MRC: failed to locate region type 0.
491 22:58:16.991114 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 22:58:16.995443 DRAM-K: Running full calibration
493 22:58:17.002104 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 22:58:17.002244 header.status = 0x0
495 22:58:17.005203 header.version = 0x6 (expected: 0x6)
496 22:58:17.008880 header.size = 0xd00 (expected: 0xd00)
497 22:58:17.012334 header.flags = 0x0
498 22:58:17.015983 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 22:58:17.034938 read SPI 0x72590 0x1c583: 12503 us, 9285 KB/s, 74.280 Mbps
500 22:58:17.042464 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 22:58:17.045539 dram_init: ddr_geometry: 2
502 22:58:17.045657 [EMI] MDL number = 2
503 22:58:17.049191 [EMI] Get MDL freq = 0
504 22:58:17.049307 dram_init: ddr_type: 0
505 22:58:17.052751 is_discrete_lpddr4: 1
506 22:58:17.057068 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 22:58:17.057168
508 22:58:17.057265
509 22:58:17.060659 [Bian_co] ETT version 0.0.0.1
510 22:58:17.064392 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 22:58:17.064505
512 22:58:17.067948 dramc_set_vcore_voltage set vcore to 650000
513 22:58:17.068053 Read voltage for 800, 4
514 22:58:17.071675 Vio18 = 0
515 22:58:17.071778 Vcore = 650000
516 22:58:17.071871 Vdram = 0
517 22:58:17.075314 Vddq = 0
518 22:58:17.075399 Vmddr = 0
519 22:58:17.078511 dram_init: config_dvfs: 1
520 22:58:17.082118 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 22:58:17.088471 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 22:58:17.092037 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
523 22:58:17.094992 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
524 22:58:17.098533 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
525 22:58:17.101601 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
526 22:58:17.104711 MEM_TYPE=3, freq_sel=18
527 22:58:17.108263 sv_algorithm_assistance_LP4_1600
528 22:58:17.111360 ============ PULL DRAM RESETB DOWN ============
529 22:58:17.114745 ========== PULL DRAM RESETB DOWN end =========
530 22:58:17.121281 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 22:58:17.124796 ===================================
532 22:58:17.124883 LPDDR4 DRAM CONFIGURATION
533 22:58:17.128410 ===================================
534 22:58:17.131457 EX_ROW_EN[0] = 0x0
535 22:58:17.135116 EX_ROW_EN[1] = 0x0
536 22:58:17.135201 LP4Y_EN = 0x0
537 22:58:17.138155 WORK_FSP = 0x0
538 22:58:17.138239 WL = 0x2
539 22:58:17.141654 RL = 0x2
540 22:58:17.141739 BL = 0x2
541 22:58:17.144745 RPST = 0x0
542 22:58:17.144833 RD_PRE = 0x0
543 22:58:17.148492 WR_PRE = 0x1
544 22:58:17.148577 WR_PST = 0x0
545 22:58:17.151622 DBI_WR = 0x0
546 22:58:17.151695 DBI_RD = 0x0
547 22:58:17.154630 OTF = 0x1
548 22:58:17.158200 ===================================
549 22:58:17.161368 ===================================
550 22:58:17.161439 ANA top config
551 22:58:17.164430 ===================================
552 22:58:17.168387 DLL_ASYNC_EN = 0
553 22:58:17.171456 ALL_SLAVE_EN = 1
554 22:58:17.174466 NEW_RANK_MODE = 1
555 22:58:17.174541 DLL_IDLE_MODE = 1
556 22:58:17.178188 LP45_APHY_COMB_EN = 1
557 22:58:17.181329 TX_ODT_DIS = 1
558 22:58:17.184634 NEW_8X_MODE = 1
559 22:58:17.188110 ===================================
560 22:58:17.191452 ===================================
561 22:58:17.194419 data_rate = 1600
562 22:58:17.194494 CKR = 1
563 22:58:17.198206 DQ_P2S_RATIO = 8
564 22:58:17.201278 ===================================
565 22:58:17.204457 CA_P2S_RATIO = 8
566 22:58:17.207550 DQ_CA_OPEN = 0
567 22:58:17.211172 DQ_SEMI_OPEN = 0
568 22:58:17.211271 CA_SEMI_OPEN = 0
569 22:58:17.214745 CA_FULL_RATE = 0
570 22:58:17.217764 DQ_CKDIV4_EN = 1
571 22:58:17.221401 CA_CKDIV4_EN = 1
572 22:58:17.224358 CA_PREDIV_EN = 0
573 22:58:17.227942 PH8_DLY = 0
574 22:58:17.228028 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 22:58:17.230833 DQ_AAMCK_DIV = 4
576 22:58:17.234488 CA_AAMCK_DIV = 4
577 22:58:17.237604 CA_ADMCK_DIV = 4
578 22:58:17.241368 DQ_TRACK_CA_EN = 0
579 22:58:17.244550 CA_PICK = 800
580 22:58:17.247642 CA_MCKIO = 800
581 22:58:17.247727 MCKIO_SEMI = 0
582 22:58:17.250716 PLL_FREQ = 3068
583 22:58:17.254460 DQ_UI_PI_RATIO = 32
584 22:58:17.257609 CA_UI_PI_RATIO = 0
585 22:58:17.261113 ===================================
586 22:58:17.264217 ===================================
587 22:58:17.267938 memory_type:LPDDR4
588 22:58:17.268022 GP_NUM : 10
589 22:58:17.271255 SRAM_EN : 1
590 22:58:17.274179 MD32_EN : 0
591 22:58:17.277336 ===================================
592 22:58:17.277414 [ANA_INIT] >>>>>>>>>>>>>>
593 22:58:17.281058 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 22:58:17.284758 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 22:58:17.287924 ===================================
596 22:58:17.291531 data_rate = 1600,PCW = 0X7600
597 22:58:17.295210 ===================================
598 22:58:17.298776 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 22:58:17.301765 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 22:58:17.308732 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 22:58:17.312464 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 22:58:17.316171 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 22:58:17.319732 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 22:58:17.323470 [ANA_INIT] flow start
605 22:58:17.323580 [ANA_INIT] PLL >>>>>>>>
606 22:58:17.326802 [ANA_INIT] PLL <<<<<<<<
607 22:58:17.330772 [ANA_INIT] MIDPI >>>>>>>>
608 22:58:17.330878 [ANA_INIT] MIDPI <<<<<<<<
609 22:58:17.334458 [ANA_INIT] DLL >>>>>>>>
610 22:58:17.334540 [ANA_INIT] flow end
611 22:58:17.341395 ============ LP4 DIFF to SE enter ============
612 22:58:17.345500 ============ LP4 DIFF to SE exit ============
613 22:58:17.345587 [ANA_INIT] <<<<<<<<<<<<<
614 22:58:17.349247 [Flow] Enable top DCM control >>>>>
615 22:58:17.352321 [Flow] Enable top DCM control <<<<<
616 22:58:17.356106 Enable DLL master slave shuffle
617 22:58:17.359809 ==============================================================
618 22:58:17.363474 Gating Mode config
619 22:58:17.367024 ==============================================================
620 22:58:17.370626 Config description:
621 22:58:17.381871 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 22:58:17.385619 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 22:58:17.392433 SELPH_MODE 0: By rank 1: By Phase
624 22:58:17.396143 ==============================================================
625 22:58:17.400442 GAT_TRACK_EN = 1
626 22:58:17.403718 RX_GATING_MODE = 2
627 22:58:17.407244 RX_GATING_TRACK_MODE = 2
628 22:58:17.407436 SELPH_MODE = 1
629 22:58:17.410816 PICG_EARLY_EN = 1
630 22:58:17.414224 VALID_LAT_VALUE = 1
631 22:58:17.421668 ==============================================================
632 22:58:17.425416 Enter into Gating configuration >>>>
633 22:58:17.428854 Exit from Gating configuration <<<<
634 22:58:17.428987 Enter into DVFS_PRE_config >>>>>
635 22:58:17.443205 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 22:58:17.443302 Exit from DVFS_PRE_config <<<<<
637 22:58:17.446699 Enter into PICG configuration >>>>
638 22:58:17.450808 Exit from PICG configuration <<<<
639 22:58:17.454070 [RX_INPUT] configuration >>>>>
640 22:58:17.457807 [RX_INPUT] configuration <<<<<
641 22:58:17.461598 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 22:58:17.465499 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 22:58:17.473144 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 22:58:17.480059 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 22:58:17.483767 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 22:58:17.491366 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 22:58:17.495123 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 22:58:17.498840 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 22:58:17.502607 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 22:58:17.509311 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 22:58:17.513009 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 22:58:17.516670 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 22:58:17.520847 ===================================
654 22:58:17.520953 LPDDR4 DRAM CONFIGURATION
655 22:58:17.524509 ===================================
656 22:58:17.527849 EX_ROW_EN[0] = 0x0
657 22:58:17.527936 EX_ROW_EN[1] = 0x0
658 22:58:17.531684 LP4Y_EN = 0x0
659 22:58:17.531780 WORK_FSP = 0x0
660 22:58:17.534804 WL = 0x2
661 22:58:17.534896 RL = 0x2
662 22:58:17.538313 BL = 0x2
663 22:58:17.538427 RPST = 0x0
664 22:58:17.542269 RD_PRE = 0x0
665 22:58:17.542390 WR_PRE = 0x1
666 22:58:17.545931 WR_PST = 0x0
667 22:58:17.546037 DBI_WR = 0x0
668 22:58:17.549359 DBI_RD = 0x0
669 22:58:17.549480 OTF = 0x1
670 22:58:17.553203 ===================================
671 22:58:17.556811 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 22:58:17.560405 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 22:58:17.567338 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 22:58:17.571239 ===================================
675 22:58:17.571331 LPDDR4 DRAM CONFIGURATION
676 22:58:17.574490 ===================================
677 22:58:17.578100 EX_ROW_EN[0] = 0x10
678 22:58:17.578183 EX_ROW_EN[1] = 0x0
679 22:58:17.582016 LP4Y_EN = 0x0
680 22:58:17.582102 WORK_FSP = 0x0
681 22:58:17.585791 WL = 0x2
682 22:58:17.585877 RL = 0x2
683 22:58:17.589109 BL = 0x2
684 22:58:17.589195 RPST = 0x0
685 22:58:17.593098 RD_PRE = 0x0
686 22:58:17.593184 WR_PRE = 0x1
687 22:58:17.596368 WR_PST = 0x0
688 22:58:17.596454 DBI_WR = 0x0
689 22:58:17.596523 DBI_RD = 0x0
690 22:58:17.600168 OTF = 0x1
691 22:58:17.603706 ===================================
692 22:58:17.610534 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 22:58:17.614325 nWR fixed to 40
694 22:58:17.614434 [ModeRegInit_LP4] CH0 RK0
695 22:58:17.618300 [ModeRegInit_LP4] CH0 RK1
696 22:58:17.618410 [ModeRegInit_LP4] CH1 RK0
697 22:58:17.621988 [ModeRegInit_LP4] CH1 RK1
698 22:58:17.625497 match AC timing 13
699 22:58:17.628926 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 22:58:17.632715 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 22:58:17.635820 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 22:58:17.642649 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 22:58:17.645994 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 22:58:17.649176 [EMI DOE] emi_dcm 0
705 22:58:17.652726 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 22:58:17.652813 ==
707 22:58:17.655777 Dram Type= 6, Freq= 0, CH_0, rank 0
708 22:58:17.658900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 22:58:17.658993 ==
710 22:58:17.665784 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 22:58:17.672183 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 22:58:17.680579 [CA 0] Center 38 (7~69) winsize 63
713 22:58:17.683827 [CA 1] Center 37 (7~68) winsize 62
714 22:58:17.687133 [CA 2] Center 35 (5~66) winsize 62
715 22:58:17.690267 [CA 3] Center 35 (5~66) winsize 62
716 22:58:17.693447 [CA 4] Center 34 (4~65) winsize 62
717 22:58:17.696719 [CA 5] Center 34 (4~65) winsize 62
718 22:58:17.696807
719 22:58:17.700019 [CmdBusTrainingLP45] Vref(ca) range 1: 34
720 22:58:17.700111
721 22:58:17.703258 [CATrainingPosCal] consider 1 rank data
722 22:58:17.706407 u2DelayCellTimex100 = 270/100 ps
723 22:58:17.709699 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
724 22:58:17.716592 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
725 22:58:17.720455 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
726 22:58:17.723481 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
727 22:58:17.727003 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
728 22:58:17.730056 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
729 22:58:17.730146
730 22:58:17.733320 CA PerBit enable=1, Macro0, CA PI delay=34
731 22:58:17.733403
732 22:58:17.736117 [CBTSetCACLKResult] CA Dly = 34
733 22:58:17.739697 CS Dly: 6 (0~37)
734 22:58:17.739793 ==
735 22:58:17.742958 Dram Type= 6, Freq= 0, CH_0, rank 1
736 22:58:17.746599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 22:58:17.746682 ==
738 22:58:17.752935 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 22:58:17.756053 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 22:58:17.766610 [CA 0] Center 38 (7~69) winsize 63
741 22:58:17.769715 [CA 1] Center 38 (7~69) winsize 63
742 22:58:17.773227 [CA 2] Center 35 (5~66) winsize 62
743 22:58:17.776388 [CA 3] Center 35 (5~66) winsize 62
744 22:58:17.780207 [CA 4] Center 34 (4~65) winsize 62
745 22:58:17.783364 [CA 5] Center 34 (4~65) winsize 62
746 22:58:17.783450
747 22:58:17.786822 [CmdBusTrainingLP45] Vref(ca) range 1: 32
748 22:58:17.786908
749 22:58:17.790083 [CATrainingPosCal] consider 2 rank data
750 22:58:17.793228 u2DelayCellTimex100 = 270/100 ps
751 22:58:17.796839 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
752 22:58:17.800005 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
753 22:58:17.806771 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
754 22:58:17.809843 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
755 22:58:17.812937 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
756 22:58:17.816750 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
757 22:58:17.816835
758 22:58:17.819798 CA PerBit enable=1, Macro0, CA PI delay=34
759 22:58:17.819884
760 22:58:17.822842 [CBTSetCACLKResult] CA Dly = 34
761 22:58:17.822928 CS Dly: 6 (0~37)
762 22:58:17.826503
763 22:58:17.829541 ----->DramcWriteLeveling(PI) begin...
764 22:58:17.829627 ==
765 22:58:17.833093 Dram Type= 6, Freq= 0, CH_0, rank 0
766 22:58:17.836522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 22:58:17.836603 ==
768 22:58:17.839540 Write leveling (Byte 0): 32 => 32
769 22:58:17.842979 Write leveling (Byte 1): 30 => 30
770 22:58:17.846413 DramcWriteLeveling(PI) end<-----
771 22:58:17.846519
772 22:58:17.846617 ==
773 22:58:17.849560 Dram Type= 6, Freq= 0, CH_0, rank 0
774 22:58:17.853216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 22:58:17.853291 ==
776 22:58:17.856188 [Gating] SW mode calibration
777 22:58:17.863057 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 22:58:17.869299 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 22:58:17.872975 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 22:58:17.876226 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
781 22:58:17.883005 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
782 22:58:17.886051 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
783 22:58:17.889654 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 22:58:17.892950 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 22:58:17.899371 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 22:58:17.902641 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 22:58:17.905992 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 22:58:17.912966 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 22:58:17.916239 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 22:58:17.919507 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 22:58:17.926074 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 22:58:17.930435 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 22:58:17.933577 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 22:58:17.937300 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 22:58:17.944001 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 22:58:17.947153 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 22:58:17.950759 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
798 22:58:17.954400 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 22:58:17.961205 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 22:58:17.964218 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 22:58:17.968256 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 22:58:17.974777 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 22:58:17.977831 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 22:58:17.980965 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 22:58:17.988024 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 22:58:17.990948 0 9 12 | B1->B0 | 2828 3333 | 1 1 | (0 0) (1 1)
807 22:58:17.994065 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 22:58:18.001065 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 22:58:18.004461 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 22:58:18.007668 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 22:58:18.014266 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 22:58:18.017435 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 22:58:18.020751 0 10 8 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
814 22:58:18.027478 0 10 12 | B1->B0 | 2f2f 2626 | 0 0 | (0 1) (0 0)
815 22:58:18.031195 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 22:58:18.034276 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 22:58:18.041036 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 22:58:18.044100 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 22:58:18.047652 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 22:58:18.054244 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 22:58:18.057381 0 11 8 | B1->B0 | 2525 2e2e | 0 0 | (0 0) (0 0)
822 22:58:18.060847 0 11 12 | B1->B0 | 3131 4040 | 0 1 | (0 0) (0 0)
823 22:58:18.067245 0 11 16 | B1->B0 | 4545 4646 | 0 0 | (1 1) (0 0)
824 22:58:18.070599 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 22:58:18.074163 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 22:58:18.077338 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 22:58:18.084405 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 22:58:18.087173 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 22:58:18.090782 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
830 22:58:18.097092 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
831 22:58:18.100625 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 22:58:18.103824 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 22:58:18.110522 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 22:58:18.113658 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 22:58:18.117461 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 22:58:18.123747 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 22:58:18.127401 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 22:58:18.130555 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 22:58:18.137527 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 22:58:18.140778 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 22:58:18.144074 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 22:58:18.150320 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 22:58:18.153494 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 22:58:18.157221 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 22:58:18.163685 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
846 22:58:18.163777 Total UI for P1: 0, mck2ui 16
847 22:58:18.170638 best dqsien dly found for B0: ( 0, 14, 6)
848 22:58:18.173493 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
849 22:58:18.177021 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 22:58:18.180180 Total UI for P1: 0, mck2ui 16
851 22:58:18.184086 best dqsien dly found for B1: ( 0, 14, 10)
852 22:58:18.187228 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
853 22:58:18.190297 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
854 22:58:18.190382
855 22:58:18.193356 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
856 22:58:18.200014 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
857 22:58:18.200114 [Gating] SW calibration Done
858 22:58:18.200185 ==
859 22:58:18.203707 Dram Type= 6, Freq= 0, CH_0, rank 0
860 22:58:18.210227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
861 22:58:18.210340 ==
862 22:58:18.210452 RX Vref Scan: 0
863 22:58:18.210548
864 22:58:18.213344 RX Vref 0 -> 0, step: 1
865 22:58:18.213450
866 22:58:18.216584 RX Delay -130 -> 252, step: 16
867 22:58:18.220408 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
868 22:58:18.223862 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
869 22:58:18.227106 iDelay=206, Bit 2, Center 77 (-50 ~ 205) 256
870 22:58:18.233567 iDelay=206, Bit 3, Center 77 (-50 ~ 205) 256
871 22:58:18.236725 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
872 22:58:18.240059 iDelay=206, Bit 5, Center 61 (-66 ~ 189) 256
873 22:58:18.243352 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
874 22:58:18.247081 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
875 22:58:18.253435 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
876 22:58:18.256701 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
877 22:58:18.260225 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
878 22:58:18.263123 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
879 22:58:18.266718 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
880 22:58:18.273102 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
881 22:58:18.276670 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
882 22:58:18.280250 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
883 22:58:18.280336 ==
884 22:58:18.283431 Dram Type= 6, Freq= 0, CH_0, rank 0
885 22:58:18.286504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
886 22:58:18.286591 ==
887 22:58:18.290202 DQS Delay:
888 22:58:18.290326 DQS0 = 0, DQS1 = 0
889 22:58:18.293245 DQM Delay:
890 22:58:18.293351 DQM0 = 80, DQM1 = 69
891 22:58:18.296407 DQ Delay:
892 22:58:18.296517 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
893 22:58:18.299989 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =85
894 22:58:18.303232 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
895 22:58:18.306854 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
896 22:58:18.306969
897 22:58:18.310128
898 22:58:18.310236 ==
899 22:58:18.313051 Dram Type= 6, Freq= 0, CH_0, rank 0
900 22:58:18.316497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
901 22:58:18.316609 ==
902 22:58:18.316708
903 22:58:18.316805
904 22:58:18.319537 TX Vref Scan disable
905 22:58:18.319649 == TX Byte 0 ==
906 22:58:18.326724 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
907 22:58:18.330505 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
908 22:58:18.330629 == TX Byte 1 ==
909 22:58:18.333736 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
910 22:58:18.340365 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
911 22:58:18.340472 ==
912 22:58:18.343447 Dram Type= 6, Freq= 0, CH_0, rank 0
913 22:58:18.346547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 22:58:18.346637 ==
915 22:58:18.360109 TX Vref=22, minBit 11, minWin=26, winSum=434
916 22:58:18.363403 TX Vref=24, minBit 14, minWin=26, winSum=437
917 22:58:18.366567 TX Vref=26, minBit 0, minWin=27, winSum=440
918 22:58:18.369745 TX Vref=28, minBit 5, minWin=27, winSum=443
919 22:58:18.372966 TX Vref=30, minBit 9, minWin=27, winSum=442
920 22:58:18.379597 TX Vref=32, minBit 10, minWin=26, winSum=437
921 22:58:18.383069 [TxChooseVref] Worse bit 5, Min win 27, Win sum 443, Final Vref 28
922 22:58:18.383172
923 22:58:18.386638 Final TX Range 1 Vref 28
924 22:58:18.386729
925 22:58:18.386797 ==
926 22:58:18.389603 Dram Type= 6, Freq= 0, CH_0, rank 0
927 22:58:18.393175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 22:58:18.396217 ==
929 22:58:18.396319
930 22:58:18.396390
931 22:58:18.396453 TX Vref Scan disable
932 22:58:18.400001 == TX Byte 0 ==
933 22:58:18.403164 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
934 22:58:18.410018 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
935 22:58:18.410128 == TX Byte 1 ==
936 22:58:18.413045 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
937 22:58:18.419961 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
938 22:58:18.420069
939 22:58:18.420142 [DATLAT]
940 22:58:18.420205 Freq=800, CH0 RK0
941 22:58:18.420265
942 22:58:18.423446 DATLAT Default: 0xa
943 22:58:18.423531 0, 0xFFFF, sum = 0
944 22:58:18.426464 1, 0xFFFF, sum = 0
945 22:58:18.426578 2, 0xFFFF, sum = 0
946 22:58:18.429680 3, 0xFFFF, sum = 0
947 22:58:18.433348 4, 0xFFFF, sum = 0
948 22:58:18.433460 5, 0xFFFF, sum = 0
949 22:58:18.436697 6, 0xFFFF, sum = 0
950 22:58:18.436813 7, 0xFFFF, sum = 0
951 22:58:18.439918 8, 0xFFFF, sum = 0
952 22:58:18.440036 9, 0x0, sum = 1
953 22:58:18.443151 10, 0x0, sum = 2
954 22:58:18.443229 11, 0x0, sum = 3
955 22:58:18.446336 12, 0x0, sum = 4
956 22:58:18.446440 best_step = 10
957 22:58:18.446535
958 22:58:18.446630 ==
959 22:58:18.449579 Dram Type= 6, Freq= 0, CH_0, rank 0
960 22:58:18.452790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
961 22:58:18.452894 ==
962 22:58:18.456378 RX Vref Scan: 1
963 22:58:18.456480
964 22:58:18.460033 Set Vref Range= 32 -> 127
965 22:58:18.460138
966 22:58:18.460207 RX Vref 32 -> 127, step: 1
967 22:58:18.460271
968 22:58:18.463160 RX Delay -111 -> 252, step: 8
969 22:58:18.463263
970 22:58:18.466286 Set Vref, RX VrefLevel [Byte0]: 32
971 22:58:18.469440 [Byte1]: 32
972 22:58:18.472661
973 22:58:18.472765 Set Vref, RX VrefLevel [Byte0]: 33
974 22:58:18.476436 [Byte1]: 33
975 22:58:18.480298
976 22:58:18.480406 Set Vref, RX VrefLevel [Byte0]: 34
977 22:58:18.484174 [Byte1]: 34
978 22:58:18.488311
979 22:58:18.488421 Set Vref, RX VrefLevel [Byte0]: 35
980 22:58:18.491711 [Byte1]: 35
981 22:58:18.495863
982 22:58:18.498744 Set Vref, RX VrefLevel [Byte0]: 36
983 22:58:18.502447 [Byte1]: 36
984 22:58:18.502557
985 22:58:18.505505 Set Vref, RX VrefLevel [Byte0]: 37
986 22:58:18.509124 [Byte1]: 37
987 22:58:18.509246
988 22:58:18.512250 Set Vref, RX VrefLevel [Byte0]: 38
989 22:58:18.516001 [Byte1]: 38
990 22:58:18.516115
991 22:58:18.519195 Set Vref, RX VrefLevel [Byte0]: 39
992 22:58:18.522347 [Byte1]: 39
993 22:58:18.526781
994 22:58:18.526910 Set Vref, RX VrefLevel [Byte0]: 40
995 22:58:18.529760 [Byte1]: 40
996 22:58:18.534114
997 22:58:18.534200 Set Vref, RX VrefLevel [Byte0]: 41
998 22:58:18.537659 [Byte1]: 41
999 22:58:18.541678
1000 22:58:18.541808 Set Vref, RX VrefLevel [Byte0]: 42
1001 22:58:18.545471 [Byte1]: 42
1002 22:58:18.549398
1003 22:58:18.549513 Set Vref, RX VrefLevel [Byte0]: 43
1004 22:58:18.552466 [Byte1]: 43
1005 22:58:18.556942
1006 22:58:18.557057 Set Vref, RX VrefLevel [Byte0]: 44
1007 22:58:18.560623 [Byte1]: 44
1008 22:58:18.564805
1009 22:58:18.564919 Set Vref, RX VrefLevel [Byte0]: 45
1010 22:58:18.568049 [Byte1]: 45
1011 22:58:18.572466
1012 22:58:18.572575 Set Vref, RX VrefLevel [Byte0]: 46
1013 22:58:18.575831 [Byte1]: 46
1014 22:58:18.579831
1015 22:58:18.579935 Set Vref, RX VrefLevel [Byte0]: 47
1016 22:58:18.583560 [Byte1]: 47
1017 22:58:18.587450
1018 22:58:18.587544 Set Vref, RX VrefLevel [Byte0]: 48
1019 22:58:18.590710 [Byte1]: 48
1020 22:58:18.595580
1021 22:58:18.595679 Set Vref, RX VrefLevel [Byte0]: 49
1022 22:58:18.599088 [Byte1]: 49
1023 22:58:18.603245
1024 22:58:18.603380 Set Vref, RX VrefLevel [Byte0]: 50
1025 22:58:18.606731 [Byte1]: 50
1026 22:58:18.611125
1027 22:58:18.611235 Set Vref, RX VrefLevel [Byte0]: 51
1028 22:58:18.614136 [Byte1]: 51
1029 22:58:18.618810
1030 22:58:18.618937 Set Vref, RX VrefLevel [Byte0]: 52
1031 22:58:18.621710 [Byte1]: 52
1032 22:58:18.626046
1033 22:58:18.626137 Set Vref, RX VrefLevel [Byte0]: 53
1034 22:58:18.629191 [Byte1]: 53
1035 22:58:18.633428
1036 22:58:18.633520 Set Vref, RX VrefLevel [Byte0]: 54
1037 22:58:18.636622 [Byte1]: 54
1038 22:58:18.640887
1039 22:58:18.640970 Set Vref, RX VrefLevel [Byte0]: 55
1040 22:58:18.644175 [Byte1]: 55
1041 22:58:18.648494
1042 22:58:18.648602 Set Vref, RX VrefLevel [Byte0]: 56
1043 22:58:18.651809 [Byte1]: 56
1044 22:58:18.656390
1045 22:58:18.656488 Set Vref, RX VrefLevel [Byte0]: 57
1046 22:58:18.659646 [Byte1]: 57
1047 22:58:18.664173
1048 22:58:18.664282 Set Vref, RX VrefLevel [Byte0]: 58
1049 22:58:18.667194 [Byte1]: 58
1050 22:58:18.671670
1051 22:58:18.671781 Set Vref, RX VrefLevel [Byte0]: 59
1052 22:58:18.674772 [Byte1]: 59
1053 22:58:18.679368
1054 22:58:18.679450 Set Vref, RX VrefLevel [Byte0]: 60
1055 22:58:18.682545 [Byte1]: 60
1056 22:58:18.687054
1057 22:58:18.687150 Set Vref, RX VrefLevel [Byte0]: 61
1058 22:58:18.690078 [Byte1]: 61
1059 22:58:18.694441
1060 22:58:18.698149 Set Vref, RX VrefLevel [Byte0]: 62
1061 22:58:18.698239 [Byte1]: 62
1062 22:58:18.702568
1063 22:58:18.702693 Set Vref, RX VrefLevel [Byte0]: 63
1064 22:58:18.705531 [Byte1]: 63
1065 22:58:18.710332
1066 22:58:18.710415 Set Vref, RX VrefLevel [Byte0]: 64
1067 22:58:18.713122 [Byte1]: 64
1068 22:58:18.717450
1069 22:58:18.717536 Set Vref, RX VrefLevel [Byte0]: 65
1070 22:58:18.721007 [Byte1]: 65
1071 22:58:18.725356
1072 22:58:18.725432 Set Vref, RX VrefLevel [Byte0]: 66
1073 22:58:18.728634 [Byte1]: 66
1074 22:58:18.733271
1075 22:58:18.733349 Set Vref, RX VrefLevel [Byte0]: 67
1076 22:58:18.736447 [Byte1]: 67
1077 22:58:18.740344
1078 22:58:18.740453 Set Vref, RX VrefLevel [Byte0]: 68
1079 22:58:18.743936 [Byte1]: 68
1080 22:58:18.748241
1081 22:58:18.748324 Set Vref, RX VrefLevel [Byte0]: 69
1082 22:58:18.751465 [Byte1]: 69
1083 22:58:18.755809
1084 22:58:18.755896 Set Vref, RX VrefLevel [Byte0]: 70
1085 22:58:18.759213 [Byte1]: 70
1086 22:58:18.763610
1087 22:58:18.763686 Set Vref, RX VrefLevel [Byte0]: 71
1088 22:58:18.766796 [Byte1]: 71
1089 22:58:18.771088
1090 22:58:18.771164 Set Vref, RX VrefLevel [Byte0]: 72
1091 22:58:18.774186 [Byte1]: 72
1092 22:58:18.778594
1093 22:58:18.778698 Set Vref, RX VrefLevel [Byte0]: 73
1094 22:58:18.782523 [Byte1]: 73
1095 22:58:18.786245
1096 22:58:18.786328 Set Vref, RX VrefLevel [Byte0]: 74
1097 22:58:18.789980 [Byte1]: 74
1098 22:58:18.793871
1099 22:58:18.793942 Set Vref, RX VrefLevel [Byte0]: 75
1100 22:58:18.797157 [Byte1]: 75
1101 22:58:18.801696
1102 22:58:18.801795 Set Vref, RX VrefLevel [Byte0]: 76
1103 22:58:18.805281 [Byte1]: 76
1104 22:58:18.809593
1105 22:58:18.809665 Set Vref, RX VrefLevel [Byte0]: 77
1106 22:58:18.812872 [Byte1]: 77
1107 22:58:18.816978
1108 22:58:18.817090 Final RX Vref Byte 0 = 57 to rank0
1109 22:58:18.820296 Final RX Vref Byte 1 = 61 to rank0
1110 22:58:18.823440 Final RX Vref Byte 0 = 57 to rank1
1111 22:58:18.827011 Final RX Vref Byte 1 = 61 to rank1==
1112 22:58:18.830410 Dram Type= 6, Freq= 0, CH_0, rank 0
1113 22:58:18.836997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1114 22:58:18.837101 ==
1115 22:58:18.837198 DQS Delay:
1116 22:58:18.840085 DQS0 = 0, DQS1 = 0
1117 22:58:18.840187 DQM Delay:
1118 22:58:18.840280 DQM0 = 81, DQM1 = 68
1119 22:58:18.843091 DQ Delay:
1120 22:58:18.846734 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1121 22:58:18.849861 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =88
1122 22:58:18.853353 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1123 22:58:18.856489 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1124 22:58:18.856615
1125 22:58:18.856717
1126 22:58:18.862842 [DQSOSCAuto] RK0, (LSB)MR18= 0x2323, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
1127 22:58:18.866100 CH0 RK0: MR19=606, MR18=2323
1128 22:58:18.873227 CH0_RK0: MR19=0x606, MR18=0x2323, DQSOSC=401, MR23=63, INC=91, DEC=61
1129 22:58:18.873333
1130 22:58:18.876343 ----->DramcWriteLeveling(PI) begin...
1131 22:58:18.876426 ==
1132 22:58:18.880073 Dram Type= 6, Freq= 0, CH_0, rank 1
1133 22:58:18.883252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1134 22:58:18.883359 ==
1135 22:58:18.886634 Write leveling (Byte 0): 35 => 35
1136 22:58:18.889723 Write leveling (Byte 1): 30 => 30
1137 22:58:18.892966 DramcWriteLeveling(PI) end<-----
1138 22:58:18.893067
1139 22:58:18.893163 ==
1140 22:58:18.896195 Dram Type= 6, Freq= 0, CH_0, rank 1
1141 22:58:18.899388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1142 22:58:18.899485 ==
1143 22:58:18.903190 [Gating] SW mode calibration
1144 22:58:18.909563 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1145 22:58:18.916024 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1146 22:58:18.919850 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1147 22:58:18.925888 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1148 22:58:18.929477 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1149 22:58:18.932633 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1150 22:58:18.939250 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 22:58:18.942347 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 22:58:18.946016 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 22:58:18.952490 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 22:58:18.955684 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 22:58:18.959254 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 22:58:18.965439 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 22:58:18.969290 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 22:58:18.972534 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 22:58:18.979069 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 22:58:18.982129 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 22:58:18.985892 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 22:58:19.033246 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1163 22:58:19.033355 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1164 22:58:19.033928 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1165 22:58:19.034013 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 22:58:19.034259 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 22:58:19.034328 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 22:58:19.034400 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 22:58:19.035073 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 22:58:19.035354 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 22:58:19.035463 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 22:58:19.035555 0 9 8 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
1173 22:58:19.077165 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1174 22:58:19.077491 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1175 22:58:19.077598 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 22:58:19.077706 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 22:58:19.077799 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 22:58:19.077898 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 22:58:19.077966 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
1180 22:58:19.078042 0 10 8 | B1->B0 | 2f2f 2b2b | 0 0 | (0 0) (0 0)
1181 22:58:19.078103 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1182 22:58:19.078162 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 22:58:19.093983 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 22:58:19.094644 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 22:58:19.095455 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 22:58:19.097949 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 22:58:19.101195 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1188 22:58:19.104361 0 11 8 | B1->B0 | 3131 3939 | 0 0 | (0 0) (0 0)
1189 22:58:19.107603 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1190 22:58:19.114173 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 22:58:19.117550 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 22:58:19.120618 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 22:58:19.127684 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 22:58:19.130936 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 22:58:19.134286 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 22:58:19.140679 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1197 22:58:19.144495 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 22:58:19.147795 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 22:58:19.154019 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 22:58:19.157561 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 22:58:19.160977 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 22:58:19.167724 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 22:58:19.171431 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 22:58:19.175043 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 22:58:19.178841 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 22:58:19.185197 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 22:58:19.188773 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 22:58:19.192538 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 22:58:19.195764 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 22:58:19.202182 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 22:58:19.205447 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 22:58:19.208646 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1213 22:58:19.215723 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1214 22:58:19.218744 Total UI for P1: 0, mck2ui 16
1215 22:58:19.221941 best dqsien dly found for B0: ( 0, 14, 8)
1216 22:58:19.225269 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1217 22:58:19.229034 Total UI for P1: 0, mck2ui 16
1218 22:58:19.232361 best dqsien dly found for B1: ( 0, 14, 12)
1219 22:58:19.235521 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1220 22:58:19.238662 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
1221 22:58:19.238763
1222 22:58:19.241858 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1223 22:58:19.245185 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
1224 22:58:19.248385 [Gating] SW calibration Done
1225 22:58:19.248456 ==
1226 22:58:19.252433 Dram Type= 6, Freq= 0, CH_0, rank 1
1227 22:58:19.258590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1228 22:58:19.258693 ==
1229 22:58:19.258786 RX Vref Scan: 0
1230 22:58:19.258885
1231 22:58:19.261446 RX Vref 0 -> 0, step: 1
1232 22:58:19.261542
1233 22:58:19.265024 RX Delay -130 -> 252, step: 16
1234 22:58:19.268547 iDelay=206, Bit 0, Center 77 (-50 ~ 205) 256
1235 22:58:19.271511 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1236 22:58:19.274907 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1237 22:58:19.281609 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1238 22:58:19.284578 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1239 22:58:19.288235 iDelay=206, Bit 5, Center 61 (-66 ~ 189) 256
1240 22:58:19.291592 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1241 22:58:19.294638 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1242 22:58:19.301221 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1243 22:58:19.305196 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1244 22:58:19.308042 iDelay=206, Bit 10, Center 61 (-66 ~ 189) 256
1245 22:58:19.311322 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1246 22:58:19.314462 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1247 22:58:19.321367 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1248 22:58:19.324479 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1249 22:58:19.328230 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1250 22:58:19.328300 ==
1251 22:58:19.331455 Dram Type= 6, Freq= 0, CH_0, rank 1
1252 22:58:19.334438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1253 22:58:19.337540 ==
1254 22:58:19.337609 DQS Delay:
1255 22:58:19.337670 DQS0 = 0, DQS1 = 0
1256 22:58:19.341476 DQM Delay:
1257 22:58:19.341545 DQM0 = 76, DQM1 = 68
1258 22:58:19.344451 DQ Delay:
1259 22:58:19.344550 DQ0 =77, DQ1 =85, DQ2 =69, DQ3 =69
1260 22:58:19.347463 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =85
1261 22:58:19.351259 DQ8 =61, DQ9 =53, DQ10 =61, DQ11 =61
1262 22:58:19.354010 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1263 22:58:19.357579
1264 22:58:19.357651
1265 22:58:19.357715 ==
1266 22:58:19.361214 Dram Type= 6, Freq= 0, CH_0, rank 1
1267 22:58:19.364124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1268 22:58:19.364191 ==
1269 22:58:19.364250
1270 22:58:19.364308
1271 22:58:19.367737 TX Vref Scan disable
1272 22:58:19.367837 == TX Byte 0 ==
1273 22:58:19.374124 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1274 22:58:19.377179 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1275 22:58:19.377276 == TX Byte 1 ==
1276 22:58:19.384110 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1277 22:58:19.387581 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1278 22:58:19.387662 ==
1279 22:58:19.390761 Dram Type= 6, Freq= 0, CH_0, rank 1
1280 22:58:19.393813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1281 22:58:19.393912 ==
1282 22:58:19.408059 TX Vref=22, minBit 11, minWin=26, winSum=436
1283 22:58:19.411697 TX Vref=24, minBit 11, minWin=26, winSum=437
1284 22:58:19.414670 TX Vref=26, minBit 12, minWin=26, winSum=438
1285 22:58:19.418483 TX Vref=28, minBit 11, minWin=26, winSum=441
1286 22:58:19.421532 TX Vref=30, minBit 2, minWin=27, winSum=444
1287 22:58:19.428167 TX Vref=32, minBit 8, minWin=27, winSum=443
1288 22:58:19.431261 [TxChooseVref] Worse bit 2, Min win 27, Win sum 444, Final Vref 30
1289 22:58:19.431362
1290 22:58:19.435120 Final TX Range 1 Vref 30
1291 22:58:19.435246
1292 22:58:19.435351 ==
1293 22:58:19.438476 Dram Type= 6, Freq= 0, CH_0, rank 1
1294 22:58:19.441646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1295 22:58:19.444742 ==
1296 22:58:19.444876
1297 22:58:19.444971
1298 22:58:19.445098 TX Vref Scan disable
1299 22:58:19.448760 == TX Byte 0 ==
1300 22:58:19.452034 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1301 22:58:19.458232 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1302 22:58:19.458361 == TX Byte 1 ==
1303 22:58:19.461901 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1304 22:58:19.468128 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1305 22:58:19.468262
1306 22:58:19.468365 [DATLAT]
1307 22:58:19.468461 Freq=800, CH0 RK1
1308 22:58:19.468552
1309 22:58:19.471762 DATLAT Default: 0xa
1310 22:58:19.471882 0, 0xFFFF, sum = 0
1311 22:58:19.474944 1, 0xFFFF, sum = 0
1312 22:58:19.478400 2, 0xFFFF, sum = 0
1313 22:58:19.478514 3, 0xFFFF, sum = 0
1314 22:58:19.481528 4, 0xFFFF, sum = 0
1315 22:58:19.481632 5, 0xFFFF, sum = 0
1316 22:58:19.485104 6, 0xFFFF, sum = 0
1317 22:58:19.485188 7, 0xFFFF, sum = 0
1318 22:58:19.488084 8, 0xFFFF, sum = 0
1319 22:58:19.488168 9, 0x0, sum = 1
1320 22:58:19.491210 10, 0x0, sum = 2
1321 22:58:19.491293 11, 0x0, sum = 3
1322 22:58:19.495041 12, 0x0, sum = 4
1323 22:58:19.495125 best_step = 10
1324 22:58:19.495191
1325 22:58:19.495252 ==
1326 22:58:19.497932 Dram Type= 6, Freq= 0, CH_0, rank 1
1327 22:58:19.501746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1328 22:58:19.501858 ==
1329 22:58:19.504530 RX Vref Scan: 0
1330 22:58:19.504637
1331 22:58:19.508002 RX Vref 0 -> 0, step: 1
1332 22:58:19.508100
1333 22:58:19.508193 RX Delay -111 -> 252, step: 8
1334 22:58:19.515361 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1335 22:58:19.518697 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1336 22:58:19.521687 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1337 22:58:19.524983 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
1338 22:58:19.532104 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1339 22:58:19.535157 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1340 22:58:19.538802 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1341 22:58:19.542085 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1342 22:58:19.545266 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1343 22:58:19.548379 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1344 22:58:19.555271 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1345 22:58:19.558352 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1346 22:58:19.561851 iDelay=209, Bit 12, Center 72 (-47 ~ 192) 240
1347 22:58:19.564946 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1348 22:58:19.571759 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1349 22:58:19.575494 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1350 22:58:19.575604 ==
1351 22:58:19.578370 Dram Type= 6, Freq= 0, CH_0, rank 1
1352 22:58:19.581879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1353 22:58:19.581965 ==
1354 22:58:19.582028 DQS Delay:
1355 22:58:19.585327 DQS0 = 0, DQS1 = 0
1356 22:58:19.585436 DQM Delay:
1357 22:58:19.588282 DQM0 = 79, DQM1 = 70
1358 22:58:19.588353 DQ Delay:
1359 22:58:19.591783 DQ0 =80, DQ1 =84, DQ2 =76, DQ3 =76
1360 22:58:19.594751 DQ4 =76, DQ5 =64, DQ6 =88, DQ7 =92
1361 22:58:19.598393 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1362 22:58:19.601346 DQ12 =72, DQ13 =76, DQ14 =80, DQ15 =80
1363 22:58:19.601437
1364 22:58:19.601505
1365 22:58:19.611374 [DQSOSCAuto] RK1, (LSB)MR18= 0x4823, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
1366 22:58:19.611475 CH0 RK1: MR19=606, MR18=4823
1367 22:58:19.618395 CH0_RK1: MR19=0x606, MR18=0x4823, DQSOSC=391, MR23=63, INC=96, DEC=64
1368 22:58:19.621378 [RxdqsGatingPostProcess] freq 800
1369 22:58:19.627786 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1370 22:58:19.631576 Pre-setting of DQS Precalculation
1371 22:58:19.634691 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1372 22:58:19.634776 ==
1373 22:58:19.637746 Dram Type= 6, Freq= 0, CH_1, rank 0
1374 22:58:19.644525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1375 22:58:19.644611 ==
1376 22:58:19.647662 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1377 22:58:19.654493 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1378 22:58:19.663859 [CA 0] Center 36 (6~66) winsize 61
1379 22:58:19.666856 [CA 1] Center 36 (6~67) winsize 62
1380 22:58:19.670366 [CA 2] Center 34 (5~64) winsize 60
1381 22:58:19.673444 [CA 3] Center 34 (4~64) winsize 61
1382 22:58:19.677133 [CA 4] Center 34 (4~64) winsize 61
1383 22:58:19.680098 [CA 5] Center 34 (4~64) winsize 61
1384 22:58:19.680204
1385 22:58:19.683650 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1386 22:58:19.683757
1387 22:58:19.686721 [CATrainingPosCal] consider 1 rank data
1388 22:58:19.690222 u2DelayCellTimex100 = 270/100 ps
1389 22:58:19.693831 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1390 22:58:19.696825 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1391 22:58:19.703187 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1392 22:58:19.706788 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1393 22:58:19.709962 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1394 22:58:19.713525 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1395 22:58:19.713601
1396 22:58:19.717143 CA PerBit enable=1, Macro0, CA PI delay=34
1397 22:58:19.717226
1398 22:58:19.720043 [CBTSetCACLKResult] CA Dly = 34
1399 22:58:19.720125 CS Dly: 5 (0~36)
1400 22:58:19.723572 ==
1401 22:58:19.726487 Dram Type= 6, Freq= 0, CH_1, rank 1
1402 22:58:19.729978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1403 22:58:19.730062 ==
1404 22:58:19.733189 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1405 22:58:19.740223 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1406 22:58:19.749897 [CA 0] Center 37 (7~67) winsize 61
1407 22:58:19.753065 [CA 1] Center 36 (6~67) winsize 62
1408 22:58:19.756691 [CA 2] Center 34 (4~65) winsize 62
1409 22:58:19.759849 [CA 3] Center 34 (4~64) winsize 61
1410 22:58:19.762805 [CA 4] Center 34 (4~65) winsize 62
1411 22:58:19.766537 [CA 5] Center 33 (3~64) winsize 62
1412 22:58:19.766619
1413 22:58:19.769669 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1414 22:58:19.769753
1415 22:58:19.773221 [CATrainingPosCal] consider 2 rank data
1416 22:58:19.776382 u2DelayCellTimex100 = 270/100 ps
1417 22:58:19.779493 CA0 delay=36 (7~66),Diff = 2 PI (14 cell)
1418 22:58:19.786316 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1419 22:58:19.789342 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1420 22:58:19.792872 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1421 22:58:19.796374 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1422 22:58:19.799349 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1423 22:58:19.799432
1424 22:58:19.802775 CA PerBit enable=1, Macro0, CA PI delay=34
1425 22:58:19.802905
1426 22:58:19.806240 [CBTSetCACLKResult] CA Dly = 34
1427 22:58:19.806321 CS Dly: 6 (0~38)
1428 22:58:19.809306
1429 22:58:19.813025 ----->DramcWriteLeveling(PI) begin...
1430 22:58:19.813111 ==
1431 22:58:19.815989 Dram Type= 6, Freq= 0, CH_1, rank 0
1432 22:58:19.819402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1433 22:58:19.819529 ==
1434 22:58:19.822659 Write leveling (Byte 0): 30 => 30
1435 22:58:19.826201 Write leveling (Byte 1): 31 => 31
1436 22:58:19.829709 DramcWriteLeveling(PI) end<-----
1437 22:58:19.829792
1438 22:58:19.829858 ==
1439 22:58:19.833239 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 22:58:19.837091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 22:58:19.837175 ==
1442 22:58:19.840762 [Gating] SW mode calibration
1443 22:58:19.847059 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1444 22:58:19.850686 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1445 22:58:19.854364 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1446 22:58:19.861878 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1447 22:58:19.865177 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1448 22:58:19.868221 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 22:58:19.871440 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 22:58:19.878477 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 22:58:19.881601 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 22:58:19.884693 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 22:58:19.891604 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 22:58:19.894645 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 22:58:19.898149 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 22:58:19.904697 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 22:58:19.908195 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 22:58:19.911044 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 22:58:19.917981 0 7 24 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1460 22:58:19.921216 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 22:58:19.924766 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 22:58:19.931182 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1463 22:58:19.934605 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1464 22:58:19.937642 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 22:58:19.944434 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 22:58:19.947670 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 22:58:19.951612 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 22:58:19.957891 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 22:58:19.961076 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 22:58:19.964251 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 22:58:19.970744 0 9 8 | B1->B0 | 2a2a 2b2b | 1 0 | (1 1) (1 1)
1472 22:58:19.974113 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 22:58:19.977988 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 22:58:19.984448 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 22:58:19.987680 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 22:58:19.990908 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 22:58:19.997385 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 22:58:20.001192 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
1479 22:58:20.004205 0 10 8 | B1->B0 | 2e2e 2d2d | 1 0 | (1 0) (0 0)
1480 22:58:20.007821 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 22:58:20.014307 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 22:58:20.017476 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 22:58:20.021053 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 22:58:20.027610 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 22:58:20.030905 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 22:58:20.033975 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1487 22:58:20.040650 0 11 8 | B1->B0 | 3838 3838 | 0 0 | (1 1) (1 1)
1488 22:58:20.044282 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 22:58:20.047178 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 22:58:20.053936 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 22:58:20.057728 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 22:58:20.061058 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 22:58:20.067503 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 22:58:20.070634 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1495 22:58:20.073976 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1496 22:58:20.080289 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 22:58:20.084215 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 22:58:20.087313 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 22:58:20.093701 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 22:58:20.097180 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 22:58:20.100379 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 22:58:20.106833 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 22:58:20.110602 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 22:58:20.113706 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 22:58:20.120351 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 22:58:20.123403 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 22:58:20.127110 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 22:58:20.133533 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 22:58:20.136570 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 22:58:20.140201 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1511 22:58:20.146960 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1512 22:58:20.150080 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1513 22:58:20.153091 Total UI for P1: 0, mck2ui 16
1514 22:58:20.156625 best dqsien dly found for B0: ( 0, 14, 6)
1515 22:58:20.160157 Total UI for P1: 0, mck2ui 16
1516 22:58:20.163158 best dqsien dly found for B1: ( 0, 14, 8)
1517 22:58:20.166533 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1518 22:58:20.169678 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1519 22:58:20.169766
1520 22:58:20.173382 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1521 22:58:20.176640 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1522 22:58:20.179789 [Gating] SW calibration Done
1523 22:58:20.179872 ==
1524 22:58:20.183018 Dram Type= 6, Freq= 0, CH_1, rank 0
1525 22:58:20.186325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1526 22:58:20.189529 ==
1527 22:58:20.189635 RX Vref Scan: 0
1528 22:58:20.189732
1529 22:58:20.193362 RX Vref 0 -> 0, step: 1
1530 22:58:20.193467
1531 22:58:20.196611 RX Delay -130 -> 252, step: 16
1532 22:58:20.199801 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1533 22:58:20.202936 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1534 22:58:20.206262 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1535 22:58:20.209616 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1536 22:58:20.216445 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1537 22:58:20.219598 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1538 22:58:20.223118 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1539 22:58:20.226276 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1540 22:58:20.229340 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1541 22:58:20.236118 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1542 22:58:20.239625 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1543 22:58:20.242608 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1544 22:58:20.246234 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1545 22:58:20.249210 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1546 22:58:20.255801 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1547 22:58:20.259274 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1548 22:58:20.259356 ==
1549 22:58:20.262872 Dram Type= 6, Freq= 0, CH_1, rank 0
1550 22:58:20.265910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1551 22:58:20.266017 ==
1552 22:58:20.269516 DQS Delay:
1553 22:58:20.269628 DQS0 = 0, DQS1 = 0
1554 22:58:20.269722 DQM Delay:
1555 22:58:20.272756 DQM0 = 81, DQM1 = 70
1556 22:58:20.272830 DQ Delay:
1557 22:58:20.275995 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1558 22:58:20.279241 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1559 22:58:20.283019 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1560 22:58:20.285658 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1561 22:58:20.285730
1562 22:58:20.285791
1563 22:58:20.285849 ==
1564 22:58:20.288947 Dram Type= 6, Freq= 0, CH_1, rank 0
1565 22:58:20.295859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1566 22:58:20.295945 ==
1567 22:58:20.296014
1568 22:58:20.296077
1569 22:58:20.296137 TX Vref Scan disable
1570 22:58:20.299140 == TX Byte 0 ==
1571 22:58:20.302758 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1572 22:58:20.309223 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1573 22:58:20.309298 == TX Byte 1 ==
1574 22:58:20.312446 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1575 22:58:20.318735 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1576 22:58:20.318810 ==
1577 22:58:20.322441 Dram Type= 6, Freq= 0, CH_1, rank 0
1578 22:58:20.325449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1579 22:58:20.325531 ==
1580 22:58:20.338089 TX Vref=22, minBit 1, minWin=26, winSum=439
1581 22:58:20.341686 TX Vref=24, minBit 1, minWin=26, winSum=440
1582 22:58:20.344853 TX Vref=26, minBit 1, minWin=27, winSum=444
1583 22:58:20.348353 TX Vref=28, minBit 4, minWin=27, winSum=445
1584 22:58:20.351953 TX Vref=30, minBit 0, minWin=28, winSum=449
1585 22:58:20.358252 TX Vref=32, minBit 9, minWin=27, winSum=449
1586 22:58:20.361385 [TxChooseVref] Worse bit 0, Min win 28, Win sum 449, Final Vref 30
1587 22:58:20.361489
1588 22:58:20.365147 Final TX Range 1 Vref 30
1589 22:58:20.365250
1590 22:58:20.365342 ==
1591 22:58:20.368078 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 22:58:20.371653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 22:58:20.371769 ==
1594 22:58:20.374585
1595 22:58:20.374693
1596 22:58:20.374790 TX Vref Scan disable
1597 22:58:20.378335 == TX Byte 0 ==
1598 22:58:20.381399 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1599 22:58:20.388322 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1600 22:58:20.388429 == TX Byte 1 ==
1601 22:58:20.391502 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1602 22:58:20.397834 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1603 22:58:20.397946
1604 22:58:20.398014 [DATLAT]
1605 22:58:20.398078 Freq=800, CH1 RK0
1606 22:58:20.398171
1607 22:58:20.401737 DATLAT Default: 0xa
1608 22:58:20.401840 0, 0xFFFF, sum = 0
1609 22:58:20.404947 1, 0xFFFF, sum = 0
1610 22:58:20.405055 2, 0xFFFF, sum = 0
1611 22:58:20.408167 3, 0xFFFF, sum = 0
1612 22:58:20.408275 4, 0xFFFF, sum = 0
1613 22:58:20.411448 5, 0xFFFF, sum = 0
1614 22:58:20.411565 6, 0xFFFF, sum = 0
1615 22:58:20.414607 7, 0xFFFF, sum = 0
1616 22:58:20.418339 8, 0xFFFF, sum = 0
1617 22:58:20.418445 9, 0x0, sum = 1
1618 22:58:20.418539 10, 0x0, sum = 2
1619 22:58:20.421809 11, 0x0, sum = 3
1620 22:58:20.421916 12, 0x0, sum = 4
1621 22:58:20.424946 best_step = 10
1622 22:58:20.425047
1623 22:58:20.425138 ==
1624 22:58:20.428043 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 22:58:20.431748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 22:58:20.431851 ==
1627 22:58:20.435149 RX Vref Scan: 1
1628 22:58:20.435222
1629 22:58:20.435284 Set Vref Range= 32 -> 127
1630 22:58:20.435351
1631 22:58:20.438143 RX Vref 32 -> 127, step: 1
1632 22:58:20.438246
1633 22:58:20.441234 RX Delay -111 -> 252, step: 8
1634 22:58:20.441335
1635 22:58:20.444651 Set Vref, RX VrefLevel [Byte0]: 32
1636 22:58:20.447800 [Byte1]: 32
1637 22:58:20.447903
1638 22:58:20.451607 Set Vref, RX VrefLevel [Byte0]: 33
1639 22:58:20.454572 [Byte1]: 33
1640 22:58:20.458680
1641 22:58:20.458786 Set Vref, RX VrefLevel [Byte0]: 34
1642 22:58:20.461731 [Byte1]: 34
1643 22:58:20.466690
1644 22:58:20.466792 Set Vref, RX VrefLevel [Byte0]: 35
1645 22:58:20.469512 [Byte1]: 35
1646 22:58:20.474042
1647 22:58:20.474118 Set Vref, RX VrefLevel [Byte0]: 36
1648 22:58:20.477531 [Byte1]: 36
1649 22:58:20.481865
1650 22:58:20.481953 Set Vref, RX VrefLevel [Byte0]: 37
1651 22:58:20.485081 [Byte1]: 37
1652 22:58:20.489449
1653 22:58:20.489553 Set Vref, RX VrefLevel [Byte0]: 38
1654 22:58:20.492715 [Byte1]: 38
1655 22:58:20.497012
1656 22:58:20.497095 Set Vref, RX VrefLevel [Byte0]: 39
1657 22:58:20.500159 [Byte1]: 39
1658 22:58:20.504625
1659 22:58:20.504734 Set Vref, RX VrefLevel [Byte0]: 40
1660 22:58:20.507635 [Byte1]: 40
1661 22:58:20.512101
1662 22:58:20.512184 Set Vref, RX VrefLevel [Byte0]: 41
1663 22:58:20.515805 [Byte1]: 41
1664 22:58:20.520199
1665 22:58:20.520281 Set Vref, RX VrefLevel [Byte0]: 42
1666 22:58:20.523189 [Byte1]: 42
1667 22:58:20.527778
1668 22:58:20.527861 Set Vref, RX VrefLevel [Byte0]: 43
1669 22:58:20.530837 [Byte1]: 43
1670 22:58:20.535090
1671 22:58:20.535173 Set Vref, RX VrefLevel [Byte0]: 44
1672 22:58:20.538677 [Byte1]: 44
1673 22:58:20.543344
1674 22:58:20.543427 Set Vref, RX VrefLevel [Byte0]: 45
1675 22:58:20.546522 [Byte1]: 45
1676 22:58:20.550678
1677 22:58:20.550783 Set Vref, RX VrefLevel [Byte0]: 46
1678 22:58:20.553883 [Byte1]: 46
1679 22:58:20.557894
1680 22:58:20.557997 Set Vref, RX VrefLevel [Byte0]: 47
1681 22:58:20.561489 [Byte1]: 47
1682 22:58:20.565735
1683 22:58:20.565842 Set Vref, RX VrefLevel [Byte0]: 48
1684 22:58:20.568978 [Byte1]: 48
1685 22:58:20.573270
1686 22:58:20.573382 Set Vref, RX VrefLevel [Byte0]: 49
1687 22:58:20.577045 [Byte1]: 49
1688 22:58:20.580770
1689 22:58:20.580880 Set Vref, RX VrefLevel [Byte0]: 50
1690 22:58:20.584432 [Byte1]: 50
1691 22:58:20.588803
1692 22:58:20.588913 Set Vref, RX VrefLevel [Byte0]: 51
1693 22:58:20.591935 [Byte1]: 51
1694 22:58:20.596386
1695 22:58:20.596484 Set Vref, RX VrefLevel [Byte0]: 52
1696 22:58:20.599503 [Byte1]: 52
1697 22:58:20.603820
1698 22:58:20.603896 Set Vref, RX VrefLevel [Byte0]: 53
1699 22:58:20.607461 [Byte1]: 53
1700 22:58:20.611805
1701 22:58:20.611876 Set Vref, RX VrefLevel [Byte0]: 54
1702 22:58:20.614912 [Byte1]: 54
1703 22:58:20.619175
1704 22:58:20.619271 Set Vref, RX VrefLevel [Byte0]: 55
1705 22:58:20.622304 [Byte1]: 55
1706 22:58:20.626778
1707 22:58:20.626885 Set Vref, RX VrefLevel [Byte0]: 56
1708 22:58:20.630440 [Byte1]: 56
1709 22:58:20.634750
1710 22:58:20.634882 Set Vref, RX VrefLevel [Byte0]: 57
1711 22:58:20.637828 [Byte1]: 57
1712 22:58:20.642095
1713 22:58:20.642200 Set Vref, RX VrefLevel [Byte0]: 58
1714 22:58:20.645805 [Byte1]: 58
1715 22:58:20.649701
1716 22:58:20.649803 Set Vref, RX VrefLevel [Byte0]: 59
1717 22:58:20.653479 [Byte1]: 59
1718 22:58:20.657591
1719 22:58:20.657692 Set Vref, RX VrefLevel [Byte0]: 60
1720 22:58:20.660677 [Byte1]: 60
1721 22:58:20.665142
1722 22:58:20.665260 Set Vref, RX VrefLevel [Byte0]: 61
1723 22:58:20.668708 [Byte1]: 61
1724 22:58:20.673150
1725 22:58:20.673237 Set Vref, RX VrefLevel [Byte0]: 62
1726 22:58:20.676275 [Byte1]: 62
1727 22:58:20.680569
1728 22:58:20.680651 Set Vref, RX VrefLevel [Byte0]: 63
1729 22:58:20.683638 [Byte1]: 63
1730 22:58:20.688100
1731 22:58:20.688186 Set Vref, RX VrefLevel [Byte0]: 64
1732 22:58:20.691338 [Byte1]: 64
1733 22:58:20.695979
1734 22:58:20.696059 Set Vref, RX VrefLevel [Byte0]: 65
1735 22:58:20.699033 [Byte1]: 65
1736 22:58:20.703613
1737 22:58:20.703686 Set Vref, RX VrefLevel [Byte0]: 66
1738 22:58:20.706835 [Byte1]: 66
1739 22:58:20.711139
1740 22:58:20.711240 Set Vref, RX VrefLevel [Byte0]: 67
1741 22:58:20.714348 [Byte1]: 67
1742 22:58:20.718451
1743 22:58:20.718549 Set Vref, RX VrefLevel [Byte0]: 68
1744 22:58:20.722328 [Byte1]: 68
1745 22:58:20.726206
1746 22:58:20.726275 Set Vref, RX VrefLevel [Byte0]: 69
1747 22:58:20.729387 [Byte1]: 69
1748 22:58:20.733795
1749 22:58:20.733889 Set Vref, RX VrefLevel [Byte0]: 70
1750 22:58:20.737060 [Byte1]: 70
1751 22:58:20.741678
1752 22:58:20.741800 Set Vref, RX VrefLevel [Byte0]: 71
1753 22:58:20.744719 [Byte1]: 71
1754 22:58:20.749247
1755 22:58:20.749324 Set Vref, RX VrefLevel [Byte0]: 72
1756 22:58:20.752388 [Byte1]: 72
1757 22:58:20.756802
1758 22:58:20.756873 Set Vref, RX VrefLevel [Byte0]: 73
1759 22:58:20.760523 [Byte1]: 73
1760 22:58:20.764420
1761 22:58:20.764503 Final RX Vref Byte 0 = 63 to rank0
1762 22:58:20.767975 Final RX Vref Byte 1 = 53 to rank0
1763 22:58:20.771024 Final RX Vref Byte 0 = 63 to rank1
1764 22:58:20.774590 Final RX Vref Byte 1 = 53 to rank1==
1765 22:58:20.778038 Dram Type= 6, Freq= 0, CH_1, rank 0
1766 22:58:20.784839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1767 22:58:20.784950 ==
1768 22:58:20.785048 DQS Delay:
1769 22:58:20.787901 DQS0 = 0, DQS1 = 0
1770 22:58:20.788013 DQM Delay:
1771 22:58:20.788108 DQM0 = 79, DQM1 = 71
1772 22:58:20.791073 DQ Delay:
1773 22:58:20.794261 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =76
1774 22:58:20.798003 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
1775 22:58:20.800933 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1776 22:58:20.804551 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1777 22:58:20.804665
1778 22:58:20.804768
1779 22:58:20.811115 [DQSOSCAuto] RK0, (LSB)MR18= 0xd17, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 406 ps
1780 22:58:20.814353 CH1 RK0: MR19=606, MR18=D17
1781 22:58:20.820933 CH1_RK0: MR19=0x606, MR18=0xD17, DQSOSC=404, MR23=63, INC=90, DEC=60
1782 22:58:20.821021
1783 22:58:20.824333 ----->DramcWriteLeveling(PI) begin...
1784 22:58:20.824411 ==
1785 22:58:20.827427 Dram Type= 6, Freq= 0, CH_1, rank 1
1786 22:58:20.831167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1787 22:58:20.831275 ==
1788 22:58:20.834241 Write leveling (Byte 0): 26 => 26
1789 22:58:20.837320 Write leveling (Byte 1): 28 => 28
1790 22:58:20.840904 DramcWriteLeveling(PI) end<-----
1791 22:58:20.840978
1792 22:58:20.841056 ==
1793 22:58:20.844078 Dram Type= 6, Freq= 0, CH_1, rank 1
1794 22:58:20.847313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1795 22:58:20.847389 ==
1796 22:58:20.850979 [Gating] SW mode calibration
1797 22:58:20.857208 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1798 22:58:20.863702 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1799 22:58:20.867459 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1800 22:58:20.870673 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1801 22:58:20.877525 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1802 22:58:20.880667 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 22:58:20.883684 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 22:58:20.890150 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 22:58:20.893918 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 22:58:20.897028 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 22:58:20.903858 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 22:58:20.907245 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 22:58:20.910462 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 22:58:20.916677 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 22:58:20.920166 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 22:58:20.923239 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 22:58:20.930157 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 22:58:20.933546 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 22:58:20.936886 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1816 22:58:20.943337 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1817 22:58:20.946832 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1818 22:58:20.949961 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 22:58:20.956652 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 22:58:20.959682 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 22:58:20.963540 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 22:58:20.969718 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 22:58:20.973452 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 22:58:20.976493 0 9 4 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
1825 22:58:20.982820 0 9 8 | B1->B0 | 2d2c 3434 | 1 1 | (0 0) (1 1)
1826 22:58:20.985909 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1827 22:58:20.989644 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1828 22:58:20.995980 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 22:58:20.999509 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 22:58:21.002579 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 22:58:21.009398 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 22:58:21.012972 0 10 4 | B1->B0 | 3232 2727 | 1 0 | (0 0) (0 1)
1833 22:58:21.015757 0 10 8 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1834 22:58:21.022488 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 22:58:21.026078 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 22:58:21.029146 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 22:58:21.035859 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 22:58:21.039476 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 22:58:21.042624 0 11 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1840 22:58:21.049312 0 11 4 | B1->B0 | 2d2d 3939 | 0 0 | (0 0) (0 0)
1841 22:58:21.052411 0 11 8 | B1->B0 | 4040 4646 | 0 0 | (1 1) (0 0)
1842 22:58:21.056066 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1843 22:58:21.062296 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 22:58:21.065902 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 22:58:21.069056 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 22:58:21.075360 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 22:58:21.079117 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 22:58:21.082210 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1849 22:58:21.089328 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1850 22:58:21.092462 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 22:58:21.096000 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 22:58:21.098962 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 22:58:21.105687 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 22:58:21.109039 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 22:58:21.111842 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 22:58:21.118746 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 22:58:21.122176 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 22:58:21.125216 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 22:58:21.132075 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 22:58:21.135259 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 22:58:21.138945 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 22:58:21.145697 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 22:58:21.148879 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 22:58:21.151977 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1865 22:58:21.158449 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 22:58:21.162066 Total UI for P1: 0, mck2ui 16
1867 22:58:21.165556 best dqsien dly found for B0: ( 0, 14, 4)
1868 22:58:21.165665 Total UI for P1: 0, mck2ui 16
1869 22:58:21.171826 best dqsien dly found for B1: ( 0, 14, 4)
1870 22:58:21.175007 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1871 22:58:21.178689 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1872 22:58:21.178770
1873 22:58:21.181709 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1874 22:58:21.185448 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1875 22:58:21.188537 [Gating] SW calibration Done
1876 22:58:21.188617 ==
1877 22:58:21.191608 Dram Type= 6, Freq= 0, CH_1, rank 1
1878 22:58:21.195423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1879 22:58:21.195504 ==
1880 22:58:21.198333 RX Vref Scan: 0
1881 22:58:21.198413
1882 22:58:21.198477 RX Vref 0 -> 0, step: 1
1883 22:58:21.198536
1884 22:58:21.201977 RX Delay -130 -> 252, step: 16
1885 22:58:21.205061 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1886 22:58:21.212159 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1887 22:58:21.215124 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1888 22:58:21.218727 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1889 22:58:21.221659 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1890 22:58:21.225213 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1891 22:58:21.232150 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1892 22:58:21.235167 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1893 22:58:21.238595 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1894 22:58:21.241533 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1895 22:58:21.245509 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1896 22:58:21.251827 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1897 22:58:21.254979 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1898 22:58:21.258549 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1899 22:58:21.261623 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1900 22:58:21.268148 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1901 22:58:21.268228 ==
1902 22:58:21.271715 Dram Type= 6, Freq= 0, CH_1, rank 1
1903 22:58:21.275096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1904 22:58:21.275177 ==
1905 22:58:21.275242 DQS Delay:
1906 22:58:21.278527 DQS0 = 0, DQS1 = 0
1907 22:58:21.278607 DQM Delay:
1908 22:58:21.281653 DQM0 = 76, DQM1 = 72
1909 22:58:21.281734 DQ Delay:
1910 22:58:21.284801 DQ0 =85, DQ1 =69, DQ2 =61, DQ3 =69
1911 22:58:21.288004 DQ4 =69, DQ5 =85, DQ6 =93, DQ7 =77
1912 22:58:21.291732 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1913 22:58:21.294732 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1914 22:58:21.294833
1915 22:58:21.294911
1916 22:58:21.294970 ==
1917 22:58:21.298476 Dram Type= 6, Freq= 0, CH_1, rank 1
1918 22:58:21.301481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1919 22:58:21.301562 ==
1920 22:58:21.301627
1921 22:58:21.301686
1922 22:58:21.305137 TX Vref Scan disable
1923 22:58:21.308287 == TX Byte 0 ==
1924 22:58:21.311297 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1925 22:58:21.314974 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1926 22:58:21.317982 == TX Byte 1 ==
1927 22:58:21.321522 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1928 22:58:21.324468 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1929 22:58:21.324581 ==
1930 22:58:21.327978 Dram Type= 6, Freq= 0, CH_1, rank 1
1931 22:58:21.334535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1932 22:58:21.334617 ==
1933 22:58:21.346002 TX Vref=22, minBit 6, minWin=27, winSum=451
1934 22:58:21.349519 TX Vref=24, minBit 1, minWin=28, winSum=456
1935 22:58:21.353149 TX Vref=26, minBit 1, minWin=28, winSum=457
1936 22:58:21.356260 TX Vref=28, minBit 5, minWin=28, winSum=463
1937 22:58:21.359292 TX Vref=30, minBit 1, minWin=28, winSum=462
1938 22:58:21.365942 TX Vref=32, minBit 1, minWin=28, winSum=463
1939 22:58:21.369040 [TxChooseVref] Worse bit 5, Min win 28, Win sum 463, Final Vref 28
1940 22:58:21.369122
1941 22:58:21.372481 Final TX Range 1 Vref 28
1942 22:58:21.372565
1943 22:58:21.372631 ==
1944 22:58:21.376061 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 22:58:21.379195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 22:58:21.379295 ==
1947 22:58:21.382302
1948 22:58:21.382383
1949 22:58:21.382453 TX Vref Scan disable
1950 22:58:21.386084 == TX Byte 0 ==
1951 22:58:21.389724 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1952 22:58:21.392918 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1953 22:58:21.396028 == TX Byte 1 ==
1954 22:58:21.399127 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1955 22:58:21.405805 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1956 22:58:21.405903
1957 22:58:21.405968 [DATLAT]
1958 22:58:21.406028 Freq=800, CH1 RK1
1959 22:58:21.406114
1960 22:58:21.409446 DATLAT Default: 0xa
1961 22:58:21.409529 0, 0xFFFF, sum = 0
1962 22:58:21.412549 1, 0xFFFF, sum = 0
1963 22:58:21.412633 2, 0xFFFF, sum = 0
1964 22:58:21.415735 3, 0xFFFF, sum = 0
1965 22:58:21.419277 4, 0xFFFF, sum = 0
1966 22:58:21.419359 5, 0xFFFF, sum = 0
1967 22:58:21.422288 6, 0xFFFF, sum = 0
1968 22:58:21.422400 7, 0xFFFF, sum = 0
1969 22:58:21.426070 8, 0xFFFF, sum = 0
1970 22:58:21.426196 9, 0x0, sum = 1
1971 22:58:21.429057 10, 0x0, sum = 2
1972 22:58:21.429142 11, 0x0, sum = 3
1973 22:58:21.429210 12, 0x0, sum = 4
1974 22:58:21.432451 best_step = 10
1975 22:58:21.432534
1976 22:58:21.432600 ==
1977 22:58:21.436029 Dram Type= 6, Freq= 0, CH_1, rank 1
1978 22:58:21.439468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1979 22:58:21.439551 ==
1980 22:58:21.442371 RX Vref Scan: 0
1981 22:58:21.442452
1982 22:58:21.442530 RX Vref 0 -> 0, step: 1
1983 22:58:21.442592
1984 22:58:21.445945 RX Delay -111 -> 252, step: 8
1985 22:58:21.452658 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1986 22:58:21.456407 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
1987 22:58:21.459285 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
1988 22:58:21.462878 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1989 22:58:21.469403 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
1990 22:58:21.472592 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
1991 22:58:21.475656 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1992 22:58:21.479217 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
1993 22:58:21.482399 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
1994 22:58:21.486105 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
1995 22:58:21.492369 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
1996 22:58:21.495528 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1997 22:58:21.499238 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1998 22:58:21.502350 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1999 22:58:21.509031 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2000 22:58:21.512075 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2001 22:58:21.512159 ==
2002 22:58:21.515335 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 22:58:21.518936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 22:58:21.519019 ==
2005 22:58:21.521832 DQS Delay:
2006 22:58:21.521915 DQS0 = 0, DQS1 = 0
2007 22:58:21.521981 DQM Delay:
2008 22:58:21.525474 DQM0 = 78, DQM1 = 74
2009 22:58:21.525557 DQ Delay:
2010 22:58:21.528482 DQ0 =80, DQ1 =72, DQ2 =68, DQ3 =72
2011 22:58:21.532120 DQ4 =76, DQ5 =88, DQ6 =92, DQ7 =76
2012 22:58:21.535579 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =64
2013 22:58:21.538732 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =80
2014 22:58:21.538815
2015 22:58:21.538889
2016 22:58:21.548758 [DQSOSCAuto] RK1, (LSB)MR18= 0x2139, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2017 22:58:21.552228 CH1 RK1: MR19=606, MR18=2139
2018 22:58:21.555211 CH1_RK1: MR19=0x606, MR18=0x2139, DQSOSC=395, MR23=63, INC=94, DEC=63
2019 22:58:21.558859 [RxdqsGatingPostProcess] freq 800
2020 22:58:21.565456 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2021 22:58:21.568503 Pre-setting of DQS Precalculation
2022 22:58:21.572071 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2023 22:58:21.581657 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2024 22:58:21.588867 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2025 22:58:21.588950
2026 22:58:21.589015
2027 22:58:21.592209 [Calibration Summary] 1600 Mbps
2028 22:58:21.592306 CH 0, Rank 0
2029 22:58:21.595070 SW Impedance : PASS
2030 22:58:21.595152 DUTY Scan : NO K
2031 22:58:21.598756 ZQ Calibration : PASS
2032 22:58:21.601998 Jitter Meter : NO K
2033 22:58:21.602080 CBT Training : PASS
2034 22:58:21.605102 Write leveling : PASS
2035 22:58:21.608170 RX DQS gating : PASS
2036 22:58:21.608274 RX DQ/DQS(RDDQC) : PASS
2037 22:58:21.611897 TX DQ/DQS : PASS
2038 22:58:21.611972 RX DATLAT : PASS
2039 22:58:21.614779 RX DQ/DQS(Engine): PASS
2040 22:58:21.618520 TX OE : NO K
2041 22:58:21.618601 All Pass.
2042 22:58:21.618665
2043 22:58:21.618726 CH 0, Rank 1
2044 22:58:21.622104 SW Impedance : PASS
2045 22:58:21.625182 DUTY Scan : NO K
2046 22:58:21.625263 ZQ Calibration : PASS
2047 22:58:21.628172 Jitter Meter : NO K
2048 22:58:21.631858 CBT Training : PASS
2049 22:58:21.631940 Write leveling : PASS
2050 22:58:21.635025 RX DQS gating : PASS
2051 22:58:21.638021 RX DQ/DQS(RDDQC) : PASS
2052 22:58:21.638101 TX DQ/DQS : PASS
2053 22:58:21.641838 RX DATLAT : PASS
2054 22:58:21.644889 RX DQ/DQS(Engine): PASS
2055 22:58:21.644970 TX OE : NO K
2056 22:58:21.648224 All Pass.
2057 22:58:21.648304
2058 22:58:21.648369 CH 1, Rank 0
2059 22:58:21.651585 SW Impedance : PASS
2060 22:58:21.651666 DUTY Scan : NO K
2061 22:58:21.654720 ZQ Calibration : PASS
2062 22:58:21.658034 Jitter Meter : NO K
2063 22:58:21.658116 CBT Training : PASS
2064 22:58:21.661736 Write leveling : PASS
2065 22:58:21.664741 RX DQS gating : PASS
2066 22:58:21.664822 RX DQ/DQS(RDDQC) : PASS
2067 22:58:21.668376 TX DQ/DQS : PASS
2068 22:58:21.668471 RX DATLAT : PASS
2069 22:58:21.671318 RX DQ/DQS(Engine): PASS
2070 22:58:21.674706 TX OE : NO K
2071 22:58:21.674792 All Pass.
2072 22:58:21.674892
2073 22:58:21.678323 CH 1, Rank 1
2074 22:58:21.678407 SW Impedance : PASS
2075 22:58:21.681126 DUTY Scan : NO K
2076 22:58:21.681235 ZQ Calibration : PASS
2077 22:58:21.684767 Jitter Meter : NO K
2078 22:58:21.687619 CBT Training : PASS
2079 22:58:21.687690 Write leveling : PASS
2080 22:58:21.691384 RX DQS gating : PASS
2081 22:58:21.694504 RX DQ/DQS(RDDQC) : PASS
2082 22:58:21.694585 TX DQ/DQS : PASS
2083 22:58:21.697700 RX DATLAT : PASS
2084 22:58:21.701368 RX DQ/DQS(Engine): PASS
2085 22:58:21.701449 TX OE : NO K
2086 22:58:21.704559 All Pass.
2087 22:58:21.704640
2088 22:58:21.704704 DramC Write-DBI off
2089 22:58:21.707785 PER_BANK_REFRESH: Hybrid Mode
2090 22:58:21.707883 TX_TRACKING: ON
2091 22:58:21.710820 [GetDramInforAfterCalByMRR] Vendor 6.
2092 22:58:21.717710 [GetDramInforAfterCalByMRR] Revision 606.
2093 22:58:21.720771 [GetDramInforAfterCalByMRR] Revision 2 0.
2094 22:58:21.720852 MR0 0x3b3b
2095 22:58:21.720917 MR8 0x5151
2096 22:58:21.727483 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2097 22:58:21.727589
2098 22:58:21.727681 MR0 0x3b3b
2099 22:58:21.727769 MR8 0x5151
2100 22:58:21.731121 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2101 22:58:21.731202
2102 22:58:21.740986 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2103 22:58:21.744116 [FAST_K] Save calibration result to emmc
2104 22:58:21.747182 [FAST_K] Save calibration result to emmc
2105 22:58:21.750840 dram_init: config_dvfs: 1
2106 22:58:21.753870 dramc_set_vcore_voltage set vcore to 662500
2107 22:58:21.757192 Read voltage for 1200, 2
2108 22:58:21.757299 Vio18 = 0
2109 22:58:21.757394 Vcore = 662500
2110 22:58:21.760588 Vdram = 0
2111 22:58:21.760658 Vddq = 0
2112 22:58:21.760718 Vmddr = 0
2113 22:58:21.767643 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2114 22:58:21.770926 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2115 22:58:21.774007 MEM_TYPE=3, freq_sel=15
2116 22:58:21.777495 sv_algorithm_assistance_LP4_1600
2117 22:58:21.780640 ============ PULL DRAM RESETB DOWN ============
2118 22:58:21.784134 ========== PULL DRAM RESETB DOWN end =========
2119 22:58:21.790689 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2120 22:58:21.793729 ===================================
2121 22:58:21.797298 LPDDR4 DRAM CONFIGURATION
2122 22:58:21.800500 ===================================
2123 22:58:21.800625 EX_ROW_EN[0] = 0x0
2124 22:58:21.803611 EX_ROW_EN[1] = 0x0
2125 22:58:21.803713 LP4Y_EN = 0x0
2126 22:58:21.807290 WORK_FSP = 0x0
2127 22:58:21.807400 WL = 0x4
2128 22:58:21.810437 RL = 0x4
2129 22:58:21.810540 BL = 0x2
2130 22:58:21.813534 RPST = 0x0
2131 22:58:21.813644 RD_PRE = 0x0
2132 22:58:21.817207 WR_PRE = 0x1
2133 22:58:21.817311 WR_PST = 0x0
2134 22:58:21.820332 DBI_WR = 0x0
2135 22:58:21.823975 DBI_RD = 0x0
2136 22:58:21.824091 OTF = 0x1
2137 22:58:21.827047 ===================================
2138 22:58:21.830170 ===================================
2139 22:58:21.830284 ANA top config
2140 22:58:21.833678 ===================================
2141 22:58:21.837259 DLL_ASYNC_EN = 0
2142 22:58:21.840414 ALL_SLAVE_EN = 0
2143 22:58:21.843932 NEW_RANK_MODE = 1
2144 22:58:21.844039 DLL_IDLE_MODE = 1
2145 22:58:21.847093 LP45_APHY_COMB_EN = 1
2146 22:58:21.850177 TX_ODT_DIS = 1
2147 22:58:21.853828 NEW_8X_MODE = 1
2148 22:58:21.856761 ===================================
2149 22:58:21.860302 ===================================
2150 22:58:21.863431 data_rate = 2400
2151 22:58:21.866738 CKR = 1
2152 22:58:21.866882 DQ_P2S_RATIO = 8
2153 22:58:21.870322 ===================================
2154 22:58:21.873690 CA_P2S_RATIO = 8
2155 22:58:21.876671 DQ_CA_OPEN = 0
2156 22:58:21.880249 DQ_SEMI_OPEN = 0
2157 22:58:21.883288 CA_SEMI_OPEN = 0
2158 22:58:21.886822 CA_FULL_RATE = 0
2159 22:58:21.886977 DQ_CKDIV4_EN = 0
2160 22:58:21.890420 CA_CKDIV4_EN = 0
2161 22:58:21.893446 CA_PREDIV_EN = 0
2162 22:58:21.897010 PH8_DLY = 17
2163 22:58:21.899953 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2164 22:58:21.903509 DQ_AAMCK_DIV = 4
2165 22:58:21.903610 CA_AAMCK_DIV = 4
2166 22:58:21.906402 CA_ADMCK_DIV = 4
2167 22:58:21.910125 DQ_TRACK_CA_EN = 0
2168 22:58:21.913361 CA_PICK = 1200
2169 22:58:21.916288 CA_MCKIO = 1200
2170 22:58:21.919942 MCKIO_SEMI = 0
2171 22:58:21.923336 PLL_FREQ = 2366
2172 22:58:21.923419 DQ_UI_PI_RATIO = 32
2173 22:58:21.926480 CA_UI_PI_RATIO = 0
2174 22:58:21.930156 ===================================
2175 22:58:21.933146 ===================================
2176 22:58:21.936844 memory_type:LPDDR4
2177 22:58:21.939727 GP_NUM : 10
2178 22:58:21.939811 SRAM_EN : 1
2179 22:58:21.943537 MD32_EN : 0
2180 22:58:21.946532 ===================================
2181 22:58:21.949644 [ANA_INIT] >>>>>>>>>>>>>>
2182 22:58:21.949730 <<<<<< [CONFIGURE PHASE]: ANA_TX
2183 22:58:21.953223 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2184 22:58:21.956343 ===================================
2185 22:58:21.960015 data_rate = 2400,PCW = 0X5b00
2186 22:58:21.963026 ===================================
2187 22:58:21.966540 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2188 22:58:21.973007 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2189 22:58:21.979465 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2190 22:58:21.983115 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2191 22:58:21.986187 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2192 22:58:21.989743 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2193 22:58:21.992754 [ANA_INIT] flow start
2194 22:58:21.992842 [ANA_INIT] PLL >>>>>>>>
2195 22:58:21.996267 [ANA_INIT] PLL <<<<<<<<
2196 22:58:21.999207 [ANA_INIT] MIDPI >>>>>>>>
2197 22:58:22.002575 [ANA_INIT] MIDPI <<<<<<<<
2198 22:58:22.002679 [ANA_INIT] DLL >>>>>>>>
2199 22:58:22.006217 [ANA_INIT] DLL <<<<<<<<
2200 22:58:22.006318 [ANA_INIT] flow end
2201 22:58:22.012515 ============ LP4 DIFF to SE enter ============
2202 22:58:22.016171 ============ LP4 DIFF to SE exit ============
2203 22:58:22.019116 [ANA_INIT] <<<<<<<<<<<<<
2204 22:58:22.022754 [Flow] Enable top DCM control >>>>>
2205 22:58:22.025744 [Flow] Enable top DCM control <<<<<
2206 22:58:22.025844 Enable DLL master slave shuffle
2207 22:58:22.032467 ==============================================================
2208 22:58:22.036057 Gating Mode config
2209 22:58:22.039214 ==============================================================
2210 22:58:22.042328 Config description:
2211 22:58:22.052644 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2212 22:58:22.058760 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2213 22:58:22.062461 SELPH_MODE 0: By rank 1: By Phase
2214 22:58:22.069139 ==============================================================
2215 22:58:22.072076 GAT_TRACK_EN = 1
2216 22:58:22.075735 RX_GATING_MODE = 2
2217 22:58:22.078709 RX_GATING_TRACK_MODE = 2
2218 22:58:22.082449 SELPH_MODE = 1
2219 22:58:22.085478 PICG_EARLY_EN = 1
2220 22:58:22.085593 VALID_LAT_VALUE = 1
2221 22:58:22.092540 ==============================================================
2222 22:58:22.095165 Enter into Gating configuration >>>>
2223 22:58:22.098767 Exit from Gating configuration <<<<
2224 22:58:22.102029 Enter into DVFS_PRE_config >>>>>
2225 22:58:22.111600 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2226 22:58:22.115298 Exit from DVFS_PRE_config <<<<<
2227 22:58:22.118693 Enter into PICG configuration >>>>
2228 22:58:22.121528 Exit from PICG configuration <<<<
2229 22:58:22.125025 [RX_INPUT] configuration >>>>>
2230 22:58:22.128686 [RX_INPUT] configuration <<<<<
2231 22:58:22.134818 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2232 22:58:22.138532 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2233 22:58:22.144722 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2234 22:58:22.151721 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2235 22:58:22.157914 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2236 22:58:22.164751 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2237 22:58:22.168365 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2238 22:58:22.171461 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2239 22:58:22.175021 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2240 22:58:22.181119 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2241 22:58:22.184655 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2242 22:58:22.187760 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2243 22:58:22.191390 ===================================
2244 22:58:22.194606 LPDDR4 DRAM CONFIGURATION
2245 22:58:22.198100 ===================================
2246 22:58:22.198191 EX_ROW_EN[0] = 0x0
2247 22:58:22.201012 EX_ROW_EN[1] = 0x0
2248 22:58:22.204658 LP4Y_EN = 0x0
2249 22:58:22.204769 WORK_FSP = 0x0
2250 22:58:22.207834 WL = 0x4
2251 22:58:22.207921 RL = 0x4
2252 22:58:22.211366 BL = 0x2
2253 22:58:22.211449 RPST = 0x0
2254 22:58:22.214351 RD_PRE = 0x0
2255 22:58:22.214436 WR_PRE = 0x1
2256 22:58:22.217793 WR_PST = 0x0
2257 22:58:22.217878 DBI_WR = 0x0
2258 22:58:22.221347 DBI_RD = 0x0
2259 22:58:22.221436 OTF = 0x1
2260 22:58:22.224341 ===================================
2261 22:58:22.227836 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2262 22:58:22.234363 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2263 22:58:22.237512 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2264 22:58:22.241158 ===================================
2265 22:58:22.244180 LPDDR4 DRAM CONFIGURATION
2266 22:58:22.247253 ===================================
2267 22:58:22.247339 EX_ROW_EN[0] = 0x10
2268 22:58:22.250897 EX_ROW_EN[1] = 0x0
2269 22:58:22.254429 LP4Y_EN = 0x0
2270 22:58:22.254533 WORK_FSP = 0x0
2271 22:58:22.257577 WL = 0x4
2272 22:58:22.257686 RL = 0x4
2273 22:58:22.260681 BL = 0x2
2274 22:58:22.260784 RPST = 0x0
2275 22:58:22.264457 RD_PRE = 0x0
2276 22:58:22.264566 WR_PRE = 0x1
2277 22:58:22.267506 WR_PST = 0x0
2278 22:58:22.267608 DBI_WR = 0x0
2279 22:58:22.270564 DBI_RD = 0x0
2280 22:58:22.270668 OTF = 0x1
2281 22:58:22.274219 ===================================
2282 22:58:22.280755 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2283 22:58:22.280884 ==
2284 22:58:22.284409 Dram Type= 6, Freq= 0, CH_0, rank 0
2285 22:58:22.287526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2286 22:58:22.287634 ==
2287 22:58:22.291117 [Duty_Offset_Calibration]
2288 22:58:22.294291 B0:2 B1:0 CA:3
2289 22:58:22.294395
2290 22:58:22.297205 [DutyScan_Calibration_Flow] k_type=0
2291 22:58:22.305816
2292 22:58:22.305918 ==CLK 0==
2293 22:58:22.308684 Final CLK duty delay cell = 0
2294 22:58:22.312517 [0] MAX Duty = 5031%(X100), DQS PI = 12
2295 22:58:22.315584 [0] MIN Duty = 4906%(X100), DQS PI = 54
2296 22:58:22.315679 [0] AVG Duty = 4968%(X100)
2297 22:58:22.318700
2298 22:58:22.322430 CH0 CLK Duty spec in!! Max-Min= 125%
2299 22:58:22.325809 [DutyScan_Calibration_Flow] ====Done====
2300 22:58:22.325888
2301 22:58:22.328619 [DutyScan_Calibration_Flow] k_type=1
2302 22:58:22.343950
2303 22:58:22.344082 ==DQS 0 ==
2304 22:58:22.347664 Final DQS duty delay cell = 0
2305 22:58:22.350761 [0] MAX Duty = 5062%(X100), DQS PI = 12
2306 22:58:22.353850 [0] MIN Duty = 4907%(X100), DQS PI = 2
2307 22:58:22.357503 [0] AVG Duty = 4984%(X100)
2308 22:58:22.357590
2309 22:58:22.357655 ==DQS 1 ==
2310 22:58:22.360455 Final DQS duty delay cell = -4
2311 22:58:22.364207 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2312 22:58:22.367284 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2313 22:58:22.370420 [-4] AVG Duty = 4922%(X100)
2314 22:58:22.370502
2315 22:58:22.374075 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2316 22:58:22.374164
2317 22:58:22.377152 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2318 22:58:22.380848 [DutyScan_Calibration_Flow] ====Done====
2319 22:58:22.380933
2320 22:58:22.383817 [DutyScan_Calibration_Flow] k_type=3
2321 22:58:22.401729
2322 22:58:22.401875 ==DQM 0 ==
2323 22:58:22.404768 Final DQM duty delay cell = 0
2324 22:58:22.408549 [0] MAX Duty = 5093%(X100), DQS PI = 12
2325 22:58:22.411672 [0] MIN Duty = 4876%(X100), DQS PI = 48
2326 22:58:22.414690 [0] AVG Duty = 4984%(X100)
2327 22:58:22.414773
2328 22:58:22.414844 ==DQM 1 ==
2329 22:58:22.418364 Final DQM duty delay cell = 4
2330 22:58:22.421451 [4] MAX Duty = 5124%(X100), DQS PI = 50
2331 22:58:22.424590 [4] MIN Duty = 5000%(X100), DQS PI = 12
2332 22:58:22.428316 [4] AVG Duty = 5062%(X100)
2333 22:58:22.428413
2334 22:58:22.431258 CH0 DQM 0 Duty spec in!! Max-Min= 217%
2335 22:58:22.431374
2336 22:58:22.434585 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2337 22:58:22.438068 [DutyScan_Calibration_Flow] ====Done====
2338 22:58:22.438162
2339 22:58:22.441012 [DutyScan_Calibration_Flow] k_type=2
2340 22:58:22.456764
2341 22:58:22.456944 ==DQ 0 ==
2342 22:58:22.459814 Final DQ duty delay cell = -4
2343 22:58:22.462792 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2344 22:58:22.466537 [-4] MIN Duty = 4907%(X100), DQS PI = 42
2345 22:58:22.469636 [-4] AVG Duty = 4969%(X100)
2346 22:58:22.469743
2347 22:58:22.469833 ==DQ 1 ==
2348 22:58:22.472826 Final DQ duty delay cell = -4
2349 22:58:22.476566 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2350 22:58:22.479572 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2351 22:58:22.482677 [-4] AVG Duty = 4922%(X100)
2352 22:58:22.482783
2353 22:58:22.486288 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2354 22:58:22.486388
2355 22:58:22.489353 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2356 22:58:22.493027 [DutyScan_Calibration_Flow] ====Done====
2357 22:58:22.493126 ==
2358 22:58:22.496116 Dram Type= 6, Freq= 0, CH_1, rank 0
2359 22:58:22.499705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2360 22:58:22.499792 ==
2361 22:58:22.502689 [Duty_Offset_Calibration]
2362 22:58:22.502794 B0:1 B1:-2 CA:0
2363 22:58:22.505866
2364 22:58:22.509077 [DutyScan_Calibration_Flow] k_type=0
2365 22:58:22.516908
2366 22:58:22.517042 ==CLK 0==
2367 22:58:22.520478 Final CLK duty delay cell = 0
2368 22:58:22.523524 [0] MAX Duty = 5031%(X100), DQS PI = 16
2369 22:58:22.527162 [0] MIN Duty = 4844%(X100), DQS PI = 58
2370 22:58:22.527254 [0] AVG Duty = 4937%(X100)
2371 22:58:22.530230
2372 22:58:22.533768 CH1 CLK Duty spec in!! Max-Min= 187%
2373 22:58:22.536986 [DutyScan_Calibration_Flow] ====Done====
2374 22:58:22.537095
2375 22:58:22.539842 [DutyScan_Calibration_Flow] k_type=1
2376 22:58:22.555454
2377 22:58:22.555617 ==DQS 0 ==
2378 22:58:22.558573 Final DQS duty delay cell = -4
2379 22:58:22.562006 [-4] MAX Duty = 5000%(X100), DQS PI = 24
2380 22:58:22.565520 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2381 22:58:22.568242 [-4] AVG Duty = 4953%(X100)
2382 22:58:22.568333
2383 22:58:22.568399 ==DQS 1 ==
2384 22:58:22.571812 Final DQS duty delay cell = 0
2385 22:58:22.574950 [0] MAX Duty = 5062%(X100), DQS PI = 0
2386 22:58:22.578519 [0] MIN Duty = 4875%(X100), DQS PI = 26
2387 22:58:22.581633 [0] AVG Duty = 4968%(X100)
2388 22:58:22.581725
2389 22:58:22.584713 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2390 22:58:22.584787
2391 22:58:22.588512 CH1 DQS 1 Duty spec in!! Max-Min= 187%
2392 22:58:22.591761 [DutyScan_Calibration_Flow] ====Done====
2393 22:58:22.591851
2394 22:58:22.595176 [DutyScan_Calibration_Flow] k_type=3
2395 22:58:22.611908
2396 22:58:22.612055 ==DQM 0 ==
2397 22:58:22.615174 Final DQM duty delay cell = 0
2398 22:58:22.618736 [0] MAX Duty = 5000%(X100), DQS PI = 24
2399 22:58:22.621845 [0] MIN Duty = 4844%(X100), DQS PI = 52
2400 22:58:22.625530 [0] AVG Duty = 4922%(X100)
2401 22:58:22.625658
2402 22:58:22.625756 ==DQM 1 ==
2403 22:58:22.628558 Final DQM duty delay cell = 0
2404 22:58:22.632167 [0] MAX Duty = 5031%(X100), DQS PI = 36
2405 22:58:22.635371 [0] MIN Duty = 4907%(X100), DQS PI = 4
2406 22:58:22.638382 [0] AVG Duty = 4969%(X100)
2407 22:58:22.638473
2408 22:58:22.641409 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2409 22:58:22.641495
2410 22:58:22.645108 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2411 22:58:22.648229 [DutyScan_Calibration_Flow] ====Done====
2412 22:58:22.648316
2413 22:58:22.651988 [DutyScan_Calibration_Flow] k_type=2
2414 22:58:22.668540
2415 22:58:22.668689 ==DQ 0 ==
2416 22:58:22.671703 Final DQ duty delay cell = 0
2417 22:58:22.674906 [0] MAX Duty = 5062%(X100), DQS PI = 18
2418 22:58:22.678409 [0] MIN Duty = 4938%(X100), DQS PI = 54
2419 22:58:22.678535 [0] AVG Duty = 5000%(X100)
2420 22:58:22.682030
2421 22:58:22.682116 ==DQ 1 ==
2422 22:58:22.685089 Final DQ duty delay cell = 0
2423 22:58:22.688106 [0] MAX Duty = 5093%(X100), DQS PI = 20
2424 22:58:22.691865 [0] MIN Duty = 4969%(X100), DQS PI = 26
2425 22:58:22.691947 [0] AVG Duty = 5031%(X100)
2426 22:58:22.694766
2427 22:58:22.698422 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2428 22:58:22.698527
2429 22:58:22.701640 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2430 22:58:22.704675 [DutyScan_Calibration_Flow] ====Done====
2431 22:58:22.708403 nWR fixed to 30
2432 22:58:22.708520 [ModeRegInit_LP4] CH0 RK0
2433 22:58:22.711585 [ModeRegInit_LP4] CH0 RK1
2434 22:58:22.714946 [ModeRegInit_LP4] CH1 RK0
2435 22:58:22.718259 [ModeRegInit_LP4] CH1 RK1
2436 22:58:22.718339 match AC timing 7
2437 22:58:22.725011 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2438 22:58:22.728126 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2439 22:58:22.731489 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2440 22:58:22.737948 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2441 22:58:22.741039 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2442 22:58:22.741123 ==
2443 22:58:22.744198 Dram Type= 6, Freq= 0, CH_0, rank 0
2444 22:58:22.747760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2445 22:58:22.747840 ==
2446 22:58:22.754686 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2447 22:58:22.761093 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2448 22:58:22.768637 [CA 0] Center 40 (10~71) winsize 62
2449 22:58:22.771577 [CA 1] Center 40 (10~70) winsize 61
2450 22:58:22.775136 [CA 2] Center 36 (6~66) winsize 61
2451 22:58:22.778295 [CA 3] Center 35 (5~66) winsize 62
2452 22:58:22.781625 [CA 4] Center 34 (4~65) winsize 62
2453 22:58:22.785183 [CA 5] Center 33 (3~64) winsize 62
2454 22:58:22.785268
2455 22:58:22.788246 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2456 22:58:22.788322
2457 22:58:22.791943 [CATrainingPosCal] consider 1 rank data
2458 22:58:22.795027 u2DelayCellTimex100 = 270/100 ps
2459 22:58:22.798075 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2460 22:58:22.804830 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2461 22:58:22.807888 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2462 22:58:22.811520 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2463 22:58:22.814547 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2464 22:58:22.818262 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2465 22:58:22.818357
2466 22:58:22.821375 CA PerBit enable=1, Macro0, CA PI delay=33
2467 22:58:22.821463
2468 22:58:22.824414 [CBTSetCACLKResult] CA Dly = 33
2469 22:58:22.828012 CS Dly: 7 (0~38)
2470 22:58:22.828101 ==
2471 22:58:22.831129 Dram Type= 6, Freq= 0, CH_0, rank 1
2472 22:58:22.834800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2473 22:58:22.834908 ==
2474 22:58:22.841528 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2475 22:58:22.844516 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2476 22:58:22.854932 [CA 0] Center 40 (10~70) winsize 61
2477 22:58:22.858026 [CA 1] Center 40 (10~70) winsize 61
2478 22:58:22.861097 [CA 2] Center 35 (5~66) winsize 62
2479 22:58:22.864750 [CA 3] Center 35 (5~66) winsize 62
2480 22:58:22.867936 [CA 4] Center 34 (4~65) winsize 62
2481 22:58:22.870980 [CA 5] Center 33 (3~64) winsize 62
2482 22:58:22.871063
2483 22:58:22.874501 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2484 22:58:22.874643
2485 22:58:22.877806 [CATrainingPosCal] consider 2 rank data
2486 22:58:22.881344 u2DelayCellTimex100 = 270/100 ps
2487 22:58:22.884351 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2488 22:58:22.891015 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2489 22:58:22.894476 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2490 22:58:22.897535 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2491 22:58:22.901280 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2492 22:58:22.904232 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2493 22:58:22.904335
2494 22:58:22.907408 CA PerBit enable=1, Macro0, CA PI delay=33
2495 22:58:22.907496
2496 22:58:22.911082 [CBTSetCACLKResult] CA Dly = 33
2497 22:58:22.914233 CS Dly: 8 (0~40)
2498 22:58:22.914322
2499 22:58:22.917343 ----->DramcWriteLeveling(PI) begin...
2500 22:58:22.917447 ==
2501 22:58:22.921106 Dram Type= 6, Freq= 0, CH_0, rank 0
2502 22:58:22.924065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2503 22:58:22.924162 ==
2504 22:58:22.927156 Write leveling (Byte 0): 32 => 32
2505 22:58:22.930929 Write leveling (Byte 1): 29 => 29
2506 22:58:22.933961 DramcWriteLeveling(PI) end<-----
2507 22:58:22.934050
2508 22:58:22.934115 ==
2509 22:58:22.937078 Dram Type= 6, Freq= 0, CH_0, rank 0
2510 22:58:22.940730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2511 22:58:22.940819 ==
2512 22:58:22.943848 [Gating] SW mode calibration
2513 22:58:22.950644 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2514 22:58:22.957210 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2515 22:58:22.960218 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2516 22:58:22.967150 0 15 4 | B1->B0 | 2525 3333 | 0 0 | (0 0) (0 0)
2517 22:58:22.970133 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2518 22:58:22.974034 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2519 22:58:22.980168 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2520 22:58:22.983611 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 22:58:22.987192 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 22:58:22.990168 0 15 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2523 22:58:22.996978 1 0 0 | B1->B0 | 3333 2c2c | 0 0 | (0 0) (0 0)
2524 22:58:23.000505 1 0 4 | B1->B0 | 2525 2323 | 1 0 | (1 0) (0 0)
2525 22:58:23.003438 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 22:58:23.010068 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2527 22:58:23.013824 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 22:58:23.016891 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 22:58:23.023451 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 22:58:23.027104 1 0 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2531 22:58:23.030197 1 1 0 | B1->B0 | 2525 3232 | 0 0 | (0 0) (0 0)
2532 22:58:23.036860 1 1 4 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
2533 22:58:23.039979 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 22:58:23.043625 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2535 22:58:23.050346 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 22:58:23.053373 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 22:58:23.056726 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 22:58:23.063368 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2539 22:58:23.066551 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2540 22:58:23.070182 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2541 22:58:23.076795 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 22:58:23.079862 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 22:58:23.083021 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 22:58:23.089683 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 22:58:23.093243 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 22:58:23.096394 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 22:58:23.103031 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 22:58:23.106429 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 22:58:23.109944 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 22:58:23.113337 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 22:58:23.119846 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 22:58:23.123433 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 22:58:23.126362 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 22:58:23.132960 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2555 22:58:23.136420 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2556 22:58:23.139893 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2557 22:58:23.143019 Total UI for P1: 0, mck2ui 16
2558 22:58:23.146528 best dqsien dly found for B0: ( 1, 3, 30)
2559 22:58:23.152837 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 22:58:23.156459 Total UI for P1: 0, mck2ui 16
2561 22:58:23.159443 best dqsien dly found for B1: ( 1, 4, 4)
2562 22:58:23.163114 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2563 22:58:23.166506 best DQS1 dly(MCK, UI, PI) = (1, 4, 4)
2564 22:58:23.166604
2565 22:58:23.169505 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2566 22:58:23.172729 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 4)
2567 22:58:23.176412 [Gating] SW calibration Done
2568 22:58:23.176519 ==
2569 22:58:23.179471 Dram Type= 6, Freq= 0, CH_0, rank 0
2570 22:58:23.183065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2571 22:58:23.183169 ==
2572 22:58:23.186122 RX Vref Scan: 0
2573 22:58:23.186224
2574 22:58:23.186315 RX Vref 0 -> 0, step: 1
2575 22:58:23.186403
2576 22:58:23.189724 RX Delay -40 -> 252, step: 8
2577 22:58:23.192920 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2578 22:58:23.199414 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2579 22:58:23.202789 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2580 22:58:23.206302 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2581 22:58:23.209378 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2582 22:58:23.212806 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2583 22:58:23.219218 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2584 22:58:23.222299 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2585 22:58:23.225626 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2586 22:58:23.229183 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2587 22:58:23.232152 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2588 22:58:23.239338 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2589 22:58:23.242403 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2590 22:58:23.245447 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2591 22:58:23.249131 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2592 22:58:23.255285 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2593 22:58:23.255400 ==
2594 22:58:23.258998 Dram Type= 6, Freq= 0, CH_0, rank 0
2595 22:58:23.262112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2596 22:58:23.262228 ==
2597 22:58:23.262331 DQS Delay:
2598 22:58:23.265767 DQS0 = 0, DQS1 = 0
2599 22:58:23.265884 DQM Delay:
2600 22:58:23.268851 DQM0 = 112, DQM1 = 101
2601 22:58:23.268955 DQ Delay:
2602 22:58:23.272370 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2603 22:58:23.275853 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2604 22:58:23.278942 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2605 22:58:23.282101 DQ12 =107, DQ13 =107, DQ14 =111, DQ15 =111
2606 22:58:23.282209
2607 22:58:23.282301
2608 22:58:23.282388 ==
2609 22:58:23.285069 Dram Type= 6, Freq= 0, CH_0, rank 0
2610 22:58:23.291871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2611 22:58:23.292003 ==
2612 22:58:23.292101
2613 22:58:23.292188
2614 22:58:23.292273 TX Vref Scan disable
2615 22:58:23.295712 == TX Byte 0 ==
2616 22:58:23.298778 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2617 22:58:23.305310 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2618 22:58:23.305440 == TX Byte 1 ==
2619 22:58:23.308707 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2620 22:58:23.315317 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2621 22:58:23.315458 ==
2622 22:58:23.318943 Dram Type= 6, Freq= 0, CH_0, rank 0
2623 22:58:23.321901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2624 22:58:23.322009 ==
2625 22:58:23.334022 TX Vref=22, minBit 7, minWin=25, winSum=417
2626 22:58:23.336849 TX Vref=24, minBit 2, minWin=26, winSum=426
2627 22:58:23.340417 TX Vref=26, minBit 7, minWin=26, winSum=431
2628 22:58:23.343958 TX Vref=28, minBit 1, minWin=27, winSum=439
2629 22:58:23.346951 TX Vref=30, minBit 10, minWin=25, winSum=433
2630 22:58:23.353697 TX Vref=32, minBit 2, minWin=26, winSum=431
2631 22:58:23.357009 [TxChooseVref] Worse bit 1, Min win 27, Win sum 439, Final Vref 28
2632 22:58:23.357135
2633 22:58:23.360174 Final TX Range 1 Vref 28
2634 22:58:23.360261
2635 22:58:23.360326 ==
2636 22:58:23.363809 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 22:58:23.366976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 22:58:23.370046 ==
2639 22:58:23.370126
2640 22:58:23.370188
2641 22:58:23.370248 TX Vref Scan disable
2642 22:58:23.373625 == TX Byte 0 ==
2643 22:58:23.376636 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2644 22:58:23.383764 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2645 22:58:23.383885 == TX Byte 1 ==
2646 22:58:23.386642 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2647 22:58:23.393394 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2648 22:58:23.393509
2649 22:58:23.393600 [DATLAT]
2650 22:58:23.393679 Freq=1200, CH0 RK0
2651 22:58:23.393757
2652 22:58:23.396488 DATLAT Default: 0xd
2653 22:58:23.396573 0, 0xFFFF, sum = 0
2654 22:58:23.400240 1, 0xFFFF, sum = 0
2655 22:58:23.403398 2, 0xFFFF, sum = 0
2656 22:58:23.403491 3, 0xFFFF, sum = 0
2657 22:58:23.406362 4, 0xFFFF, sum = 0
2658 22:58:23.406476 5, 0xFFFF, sum = 0
2659 22:58:23.409734 6, 0xFFFF, sum = 0
2660 22:58:23.409877 7, 0xFFFF, sum = 0
2661 22:58:23.413273 8, 0xFFFF, sum = 0
2662 22:58:23.413353 9, 0xFFFF, sum = 0
2663 22:58:23.416342 10, 0xFFFF, sum = 0
2664 22:58:23.416421 11, 0xFFFF, sum = 0
2665 22:58:23.419998 12, 0x0, sum = 1
2666 22:58:23.420083 13, 0x0, sum = 2
2667 22:58:23.422999 14, 0x0, sum = 3
2668 22:58:23.423097 15, 0x0, sum = 4
2669 22:58:23.426490 best_step = 13
2670 22:58:23.426581
2671 22:58:23.426666 ==
2672 22:58:23.429917 Dram Type= 6, Freq= 0, CH_0, rank 0
2673 22:58:23.432982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2674 22:58:23.433059 ==
2675 22:58:23.433128 RX Vref Scan: 1
2676 22:58:23.436648
2677 22:58:23.436747 Set Vref Range= 32 -> 127
2678 22:58:23.436830
2679 22:58:23.439711 RX Vref 32 -> 127, step: 1
2680 22:58:23.439787
2681 22:58:23.443343 RX Delay -37 -> 252, step: 4
2682 22:58:23.443432
2683 22:58:23.446256 Set Vref, RX VrefLevel [Byte0]: 32
2684 22:58:23.449783 [Byte1]: 32
2685 22:58:23.449892
2686 22:58:23.452800 Set Vref, RX VrefLevel [Byte0]: 33
2687 22:58:23.456445 [Byte1]: 33
2688 22:58:23.460174
2689 22:58:23.460285 Set Vref, RX VrefLevel [Byte0]: 34
2690 22:58:23.463326 [Byte1]: 34
2691 22:58:23.468388
2692 22:58:23.468500 Set Vref, RX VrefLevel [Byte0]: 35
2693 22:58:23.471483 [Byte1]: 35
2694 22:58:23.475827
2695 22:58:23.475962 Set Vref, RX VrefLevel [Byte0]: 36
2696 22:58:23.479576 [Byte1]: 36
2697 22:58:23.484412
2698 22:58:23.484541 Set Vref, RX VrefLevel [Byte0]: 37
2699 22:58:23.487392 [Byte1]: 37
2700 22:58:23.492130
2701 22:58:23.492245 Set Vref, RX VrefLevel [Byte0]: 38
2702 22:58:23.495126 [Byte1]: 38
2703 22:58:23.500143
2704 22:58:23.500271 Set Vref, RX VrefLevel [Byte0]: 39
2705 22:58:23.503199 [Byte1]: 39
2706 22:58:23.508193
2707 22:58:23.508311 Set Vref, RX VrefLevel [Byte0]: 40
2708 22:58:23.511195 [Byte1]: 40
2709 22:58:23.516109
2710 22:58:23.516228 Set Vref, RX VrefLevel [Byte0]: 41
2711 22:58:23.519212 [Byte1]: 41
2712 22:58:23.524357
2713 22:58:23.524452 Set Vref, RX VrefLevel [Byte0]: 42
2714 22:58:23.527379 [Byte1]: 42
2715 22:58:23.532023
2716 22:58:23.532130 Set Vref, RX VrefLevel [Byte0]: 43
2717 22:58:23.535039 [Byte1]: 43
2718 22:58:23.539958
2719 22:58:23.540051 Set Vref, RX VrefLevel [Byte0]: 44
2720 22:58:23.543408 [Byte1]: 44
2721 22:58:23.548371
2722 22:58:23.548472 Set Vref, RX VrefLevel [Byte0]: 45
2723 22:58:23.551392 [Byte1]: 45
2724 22:58:23.555968
2725 22:58:23.556098 Set Vref, RX VrefLevel [Byte0]: 46
2726 22:58:23.559505 [Byte1]: 46
2727 22:58:23.563828
2728 22:58:23.563916 Set Vref, RX VrefLevel [Byte0]: 47
2729 22:58:23.567593 [Byte1]: 47
2730 22:58:23.571821
2731 22:58:23.571928 Set Vref, RX VrefLevel [Byte0]: 48
2732 22:58:23.575645 [Byte1]: 48
2733 22:58:23.580302
2734 22:58:23.580420 Set Vref, RX VrefLevel [Byte0]: 49
2735 22:58:23.583655 [Byte1]: 49
2736 22:58:23.587861
2737 22:58:23.587980 Set Vref, RX VrefLevel [Byte0]: 50
2738 22:58:23.591543 [Byte1]: 50
2739 22:58:23.595933
2740 22:58:23.596049 Set Vref, RX VrefLevel [Byte0]: 51
2741 22:58:23.599863 [Byte1]: 51
2742 22:58:23.604304
2743 22:58:23.604396 Set Vref, RX VrefLevel [Byte0]: 52
2744 22:58:23.607448 [Byte1]: 52
2745 22:58:23.612390
2746 22:58:23.612482 Set Vref, RX VrefLevel [Byte0]: 53
2747 22:58:23.615502 [Byte1]: 53
2748 22:58:23.620177
2749 22:58:23.620262 Set Vref, RX VrefLevel [Byte0]: 54
2750 22:58:23.623316 [Byte1]: 54
2751 22:58:23.628153
2752 22:58:23.628253 Set Vref, RX VrefLevel [Byte0]: 55
2753 22:58:23.631605 [Byte1]: 55
2754 22:58:23.636255
2755 22:58:23.636373 Set Vref, RX VrefLevel [Byte0]: 56
2756 22:58:23.639276 [Byte1]: 56
2757 22:58:23.644004
2758 22:58:23.644102 Set Vref, RX VrefLevel [Byte0]: 57
2759 22:58:23.647163 [Byte1]: 57
2760 22:58:23.651820
2761 22:58:23.651920 Set Vref, RX VrefLevel [Byte0]: 58
2762 22:58:23.655606 [Byte1]: 58
2763 22:58:23.660355
2764 22:58:23.660451 Set Vref, RX VrefLevel [Byte0]: 59
2765 22:58:23.663348 [Byte1]: 59
2766 22:58:23.668181
2767 22:58:23.668278 Set Vref, RX VrefLevel [Byte0]: 60
2768 22:58:23.671487 [Byte1]: 60
2769 22:58:23.676348
2770 22:58:23.676459 Set Vref, RX VrefLevel [Byte0]: 61
2771 22:58:23.679356 [Byte1]: 61
2772 22:58:23.684324
2773 22:58:23.684419 Set Vref, RX VrefLevel [Byte0]: 62
2774 22:58:23.687378 [Byte1]: 62
2775 22:58:23.692121
2776 22:58:23.692259 Set Vref, RX VrefLevel [Byte0]: 63
2777 22:58:23.695208 [Byte1]: 63
2778 22:58:23.700372
2779 22:58:23.700471 Set Vref, RX VrefLevel [Byte0]: 64
2780 22:58:23.703447 [Byte1]: 64
2781 22:58:23.708142
2782 22:58:23.708244 Set Vref, RX VrefLevel [Byte0]: 65
2783 22:58:23.711557 [Byte1]: 65
2784 22:58:23.716458
2785 22:58:23.716560 Set Vref, RX VrefLevel [Byte0]: 66
2786 22:58:23.719567 [Byte1]: 66
2787 22:58:23.724265
2788 22:58:23.724360 Set Vref, RX VrefLevel [Byte0]: 67
2789 22:58:23.727509 [Byte1]: 67
2790 22:58:23.732571
2791 22:58:23.732693 Set Vref, RX VrefLevel [Byte0]: 68
2792 22:58:23.735418 [Byte1]: 68
2793 22:58:23.740200
2794 22:58:23.740338 Set Vref, RX VrefLevel [Byte0]: 69
2795 22:58:23.746502 [Byte1]: 69
2796 22:58:23.746644
2797 22:58:23.749563 Set Vref, RX VrefLevel [Byte0]: 70
2798 22:58:23.753024 [Byte1]: 70
2799 22:58:23.753114
2800 22:58:23.756698 Set Vref, RX VrefLevel [Byte0]: 71
2801 22:58:23.759556 [Byte1]: 71
2802 22:58:23.763792
2803 22:58:23.763887 Set Vref, RX VrefLevel [Byte0]: 72
2804 22:58:23.767309 [Byte1]: 72
2805 22:58:23.772074
2806 22:58:23.772171 Set Vref, RX VrefLevel [Byte0]: 73
2807 22:58:23.775118 [Byte1]: 73
2808 22:58:23.779985
2809 22:58:23.780118 Set Vref, RX VrefLevel [Byte0]: 74
2810 22:58:23.783193 [Byte1]: 74
2811 22:58:23.788293
2812 22:58:23.788386 Final RX Vref Byte 0 = 60 to rank0
2813 22:58:23.791419 Final RX Vref Byte 1 = 47 to rank0
2814 22:58:23.794808 Final RX Vref Byte 0 = 60 to rank1
2815 22:58:23.797902 Final RX Vref Byte 1 = 47 to rank1==
2816 22:58:23.801081 Dram Type= 6, Freq= 0, CH_0, rank 0
2817 22:58:23.807864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2818 22:58:23.807989 ==
2819 22:58:23.808088 DQS Delay:
2820 22:58:23.811350 DQS0 = 0, DQS1 = 0
2821 22:58:23.811437 DQM Delay:
2822 22:58:23.811502 DQM0 = 111, DQM1 = 98
2823 22:58:23.814227 DQ Delay:
2824 22:58:23.817836 DQ0 =110, DQ1 =110, DQ2 =110, DQ3 =108
2825 22:58:23.821451 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =122
2826 22:58:23.824541 DQ8 =90, DQ9 =82, DQ10 =100, DQ11 =90
2827 22:58:23.828117 DQ12 =104, DQ13 =104, DQ14 =112, DQ15 =106
2828 22:58:23.828210
2829 22:58:23.828277
2830 22:58:23.834391 [DQSOSCAuto] RK0, (LSB)MR18= 0xfcfc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
2831 22:58:23.838008 CH0 RK0: MR19=303, MR18=FCFC
2832 22:58:23.844445 CH0_RK0: MR19=0x303, MR18=0xFCFC, DQSOSC=411, MR23=63, INC=38, DEC=25
2833 22:58:23.844583
2834 22:58:23.847926 ----->DramcWriteLeveling(PI) begin...
2835 22:58:23.848016 ==
2836 22:58:23.850988 Dram Type= 6, Freq= 0, CH_0, rank 1
2837 22:58:23.854463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2838 22:58:23.857402 ==
2839 22:58:23.857540 Write leveling (Byte 0): 34 => 34
2840 22:58:23.860987 Write leveling (Byte 1): 30 => 30
2841 22:58:23.864450 DramcWriteLeveling(PI) end<-----
2842 22:58:23.864540
2843 22:58:23.864605 ==
2844 22:58:23.867516 Dram Type= 6, Freq= 0, CH_0, rank 1
2845 22:58:23.874320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2846 22:58:23.874427 ==
2847 22:58:23.877814 [Gating] SW mode calibration
2848 22:58:23.884000 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2849 22:58:23.887687 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2850 22:58:23.894098 0 15 0 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
2851 22:58:23.897678 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2852 22:58:23.900619 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 22:58:23.907381 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 22:58:23.911121 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 22:58:23.914091 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 22:58:23.917806 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2857 22:58:23.924454 0 15 28 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
2858 22:58:23.927464 1 0 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
2859 22:58:23.931014 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 22:58:23.937271 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 22:58:23.940361 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 22:58:23.944212 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 22:58:23.950655 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 22:58:23.953659 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2865 22:58:23.957163 1 0 28 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
2866 22:58:23.963784 1 1 0 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
2867 22:58:23.966788 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 22:58:23.970529 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 22:58:23.977076 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 22:58:23.980138 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 22:58:23.983666 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 22:58:23.990303 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 22:58:23.993413 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2874 22:58:23.996506 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 22:58:24.003216 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 22:58:24.006886 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 22:58:24.010026 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 22:58:24.016724 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 22:58:24.019713 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 22:58:24.023394 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 22:58:24.030065 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 22:58:24.033167 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 22:58:24.036652 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 22:58:24.043036 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 22:58:24.046669 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 22:58:24.049618 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 22:58:24.056335 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 22:58:24.059357 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2889 22:58:24.062800 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2890 22:58:24.069808 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2891 22:58:24.069946 Total UI for P1: 0, mck2ui 16
2892 22:58:24.076115 best dqsien dly found for B0: ( 1, 3, 26)
2893 22:58:24.076262 Total UI for P1: 0, mck2ui 16
2894 22:58:24.083297 best dqsien dly found for B1: ( 1, 3, 30)
2895 22:58:24.086412 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2896 22:58:24.089392 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2897 22:58:24.089500
2898 22:58:24.092779 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2899 22:58:24.096334 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2900 22:58:24.099428 [Gating] SW calibration Done
2901 22:58:24.099534 ==
2902 22:58:24.102510 Dram Type= 6, Freq= 0, CH_0, rank 1
2903 22:58:24.106179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2904 22:58:24.106300 ==
2905 22:58:24.109183 RX Vref Scan: 0
2906 22:58:24.109302
2907 22:58:24.109397 RX Vref 0 -> 0, step: 1
2908 22:58:24.109485
2909 22:58:24.112730 RX Delay -40 -> 252, step: 8
2910 22:58:24.115758 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2911 22:58:24.122500 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2912 22:58:24.126092 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2913 22:58:24.129258 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2914 22:58:24.132338 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2915 22:58:24.135976 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2916 22:58:24.142498 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2917 22:58:24.145565 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2918 22:58:24.149295 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2919 22:58:24.152168 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2920 22:58:24.155455 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2921 22:58:24.162100 iDelay=200, Bit 11, Center 91 (16 ~ 167) 152
2922 22:58:24.165963 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2923 22:58:24.169365 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2924 22:58:24.172333 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2925 22:58:24.175633 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2926 22:58:24.179212 ==
2927 22:58:24.182103 Dram Type= 6, Freq= 0, CH_0, rank 1
2928 22:58:24.185423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2929 22:58:24.185544 ==
2930 22:58:24.185643 DQS Delay:
2931 22:58:24.189006 DQS0 = 0, DQS1 = 0
2932 22:58:24.189119 DQM Delay:
2933 22:58:24.192109 DQM0 = 112, DQM1 = 100
2934 22:58:24.192220 DQ Delay:
2935 22:58:24.195292 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2936 22:58:24.198918 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =123
2937 22:58:24.202417 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =91
2938 22:58:24.205390 DQ12 =107, DQ13 =107, DQ14 =111, DQ15 =111
2939 22:58:24.205504
2940 22:58:24.205609
2941 22:58:24.205734 ==
2942 22:58:24.208910 Dram Type= 6, Freq= 0, CH_0, rank 1
2943 22:58:24.215145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2944 22:58:24.215271 ==
2945 22:58:24.215368
2946 22:58:24.215463
2947 22:58:24.215555 TX Vref Scan disable
2948 22:58:24.218758 == TX Byte 0 ==
2949 22:58:24.221907 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2950 22:58:24.228596 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2951 22:58:24.228740 == TX Byte 1 ==
2952 22:58:24.232269 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2953 22:58:24.238480 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2954 22:58:24.238608 ==
2955 22:58:24.242150 Dram Type= 6, Freq= 0, CH_0, rank 1
2956 22:58:24.245547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2957 22:58:24.245667 ==
2958 22:58:24.256902 TX Vref=22, minBit 1, minWin=25, winSum=423
2959 22:58:24.260565 TX Vref=24, minBit 1, minWin=26, winSum=429
2960 22:58:24.263697 TX Vref=26, minBit 0, minWin=26, winSum=431
2961 22:58:24.266764 TX Vref=28, minBit 8, minWin=26, winSum=435
2962 22:58:24.270732 TX Vref=30, minBit 1, minWin=27, winSum=437
2963 22:58:24.276631 TX Vref=32, minBit 3, minWin=26, winSum=436
2964 22:58:24.280098 [TxChooseVref] Worse bit 1, Min win 27, Win sum 437, Final Vref 30
2965 22:58:24.280227
2966 22:58:24.283338 Final TX Range 1 Vref 30
2967 22:58:24.283449
2968 22:58:24.283574 ==
2969 22:58:24.287055 Dram Type= 6, Freq= 0, CH_0, rank 1
2970 22:58:24.289942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2971 22:58:24.290056 ==
2972 22:58:24.293241
2973 22:58:24.293386
2974 22:58:24.293519 TX Vref Scan disable
2975 22:58:24.296728 == TX Byte 0 ==
2976 22:58:24.299966 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2977 22:58:24.306665 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2978 22:58:24.306806 == TX Byte 1 ==
2979 22:58:24.309635 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2980 22:58:24.316682 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2981 22:58:24.316844
2982 22:58:24.316946 [DATLAT]
2983 22:58:24.317040 Freq=1200, CH0 RK1
2984 22:58:24.317130
2985 22:58:24.319698 DATLAT Default: 0xd
2986 22:58:24.319805 0, 0xFFFF, sum = 0
2987 22:58:24.323384 1, 0xFFFF, sum = 0
2988 22:58:24.326446 2, 0xFFFF, sum = 0
2989 22:58:24.326559 3, 0xFFFF, sum = 0
2990 22:58:24.329567 4, 0xFFFF, sum = 0
2991 22:58:24.329679 5, 0xFFFF, sum = 0
2992 22:58:24.333246 6, 0xFFFF, sum = 0
2993 22:58:24.333358 7, 0xFFFF, sum = 0
2994 22:58:24.336255 8, 0xFFFF, sum = 0
2995 22:58:24.336366 9, 0xFFFF, sum = 0
2996 22:58:24.339480 10, 0xFFFF, sum = 0
2997 22:58:24.339639 11, 0xFFFF, sum = 0
2998 22:58:24.343122 12, 0x0, sum = 1
2999 22:58:24.343233 13, 0x0, sum = 2
3000 22:58:24.346293 14, 0x0, sum = 3
3001 22:58:24.346402 15, 0x0, sum = 4
3002 22:58:24.349895 best_step = 13
3003 22:58:24.350003
3004 22:58:24.350097 ==
3005 22:58:24.352791 Dram Type= 6, Freq= 0, CH_0, rank 1
3006 22:58:24.356203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3007 22:58:24.356317 ==
3008 22:58:24.356412 RX Vref Scan: 0
3009 22:58:24.359412
3010 22:58:24.359520 RX Vref 0 -> 0, step: 1
3011 22:58:24.359614
3012 22:58:24.362770 RX Delay -37 -> 252, step: 4
3013 22:58:24.369401 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3014 22:58:24.372648 iDelay=195, Bit 1, Center 112 (39 ~ 186) 148
3015 22:58:24.376337 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3016 22:58:24.379476 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3017 22:58:24.382531 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3018 22:58:24.389072 iDelay=195, Bit 5, Center 102 (35 ~ 170) 136
3019 22:58:24.392667 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3020 22:58:24.396067 iDelay=195, Bit 7, Center 118 (43 ~ 194) 152
3021 22:58:24.398980 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3022 22:58:24.402375 iDelay=195, Bit 9, Center 82 (11 ~ 154) 144
3023 22:58:24.409450 iDelay=195, Bit 10, Center 102 (31 ~ 174) 144
3024 22:58:24.412401 iDelay=195, Bit 11, Center 90 (23 ~ 158) 136
3025 22:58:24.416032 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3026 22:58:24.418844 iDelay=195, Bit 13, Center 106 (35 ~ 178) 144
3027 22:58:24.422295 iDelay=195, Bit 14, Center 110 (43 ~ 178) 136
3028 22:58:24.429123 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3029 22:58:24.429270 ==
3030 22:58:24.432095 Dram Type= 6, Freq= 0, CH_0, rank 1
3031 22:58:24.435850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3032 22:58:24.435967 ==
3033 22:58:24.436062 DQS Delay:
3034 22:58:24.438811 DQS0 = 0, DQS1 = 0
3035 22:58:24.438940 DQM Delay:
3036 22:58:24.442008 DQM0 = 111, DQM1 = 99
3037 22:58:24.442138 DQ Delay:
3038 22:58:24.445079 DQ0 =108, DQ1 =112, DQ2 =108, DQ3 =108
3039 22:58:24.448815 DQ4 =112, DQ5 =102, DQ6 =120, DQ7 =118
3040 22:58:24.451881 DQ8 =90, DQ9 =82, DQ10 =102, DQ11 =90
3041 22:58:24.455037 DQ12 =108, DQ13 =106, DQ14 =110, DQ15 =108
3042 22:58:24.455167
3043 22:58:24.458458
3044 22:58:24.465224 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3045 22:58:24.468876 CH0 RK1: MR19=403, MR18=10F8
3046 22:58:24.475183 CH0_RK1: MR19=0x403, MR18=0x10F8, DQSOSC=403, MR23=63, INC=40, DEC=26
3047 22:58:24.478690 [RxdqsGatingPostProcess] freq 1200
3048 22:58:24.481776 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3049 22:58:24.484939 best DQS0 dly(2T, 0.5T) = (0, 11)
3050 22:58:24.488148 best DQS1 dly(2T, 0.5T) = (0, 12)
3051 22:58:24.491747 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3052 22:58:24.494952 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3053 22:58:24.498414 best DQS0 dly(2T, 0.5T) = (0, 11)
3054 22:58:24.501525 best DQS1 dly(2T, 0.5T) = (0, 11)
3055 22:58:24.505071 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3056 22:58:24.508485 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3057 22:58:24.511306 Pre-setting of DQS Precalculation
3058 22:58:24.514892 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3059 22:58:24.515015 ==
3060 22:58:24.517834 Dram Type= 6, Freq= 0, CH_1, rank 0
3061 22:58:24.521549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3062 22:58:24.524721 ==
3063 22:58:24.528098 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3064 22:58:24.534430 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3065 22:58:24.542792 [CA 0] Center 37 (7~67) winsize 61
3066 22:58:24.546475 [CA 1] Center 37 (7~68) winsize 62
3067 22:58:24.549560 [CA 2] Center 34 (4~64) winsize 61
3068 22:58:24.553314 [CA 3] Center 34 (4~64) winsize 61
3069 22:58:24.556427 [CA 4] Center 34 (4~64) winsize 61
3070 22:58:24.559515 [CA 5] Center 33 (3~63) winsize 61
3071 22:58:24.559628
3072 22:58:24.563017 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3073 22:58:24.563175
3074 22:58:24.566108 [CATrainingPosCal] consider 1 rank data
3075 22:58:24.569133 u2DelayCellTimex100 = 270/100 ps
3076 22:58:24.572724 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3077 22:58:24.579453 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3078 22:58:24.582544 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3079 22:58:24.586157 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3080 22:58:24.589369 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3081 22:58:24.592546 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3082 22:58:24.592663
3083 22:58:24.595592 CA PerBit enable=1, Macro0, CA PI delay=33
3084 22:58:24.595701
3085 22:58:24.599114 [CBTSetCACLKResult] CA Dly = 33
3086 22:58:24.599228 CS Dly: 5 (0~36)
3087 22:58:24.602151 ==
3088 22:58:24.605621 Dram Type= 6, Freq= 0, CH_1, rank 1
3089 22:58:24.609266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3090 22:58:24.609390 ==
3091 22:58:24.612193 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3092 22:58:24.619227 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3093 22:58:24.628443 [CA 0] Center 37 (7~67) winsize 61
3094 22:58:24.631971 [CA 1] Center 37 (7~68) winsize 62
3095 22:58:24.635052 [CA 2] Center 34 (4~65) winsize 62
3096 22:58:24.638568 [CA 3] Center 33 (3~64) winsize 62
3097 22:58:24.641552 [CA 4] Center 34 (4~65) winsize 62
3098 22:58:24.645186 [CA 5] Center 32 (2~63) winsize 62
3099 22:58:24.645303
3100 22:58:24.648176 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3101 22:58:24.648288
3102 22:58:24.651908 [CATrainingPosCal] consider 2 rank data
3103 22:58:24.655001 u2DelayCellTimex100 = 270/100 ps
3104 22:58:24.658077 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3105 22:58:24.664745 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3106 22:58:24.668405 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3107 22:58:24.671439 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3108 22:58:24.675118 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3109 22:58:24.678057 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3110 22:58:24.678254
3111 22:58:24.681462 CA PerBit enable=1, Macro0, CA PI delay=33
3112 22:58:24.681576
3113 22:58:24.684581 [CBTSetCACLKResult] CA Dly = 33
3114 22:58:24.684691 CS Dly: 6 (0~39)
3115 22:58:24.688241
3116 22:58:24.691432 ----->DramcWriteLeveling(PI) begin...
3117 22:58:24.691548 ==
3118 22:58:24.694593 Dram Type= 6, Freq= 0, CH_1, rank 0
3119 22:58:24.698228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3120 22:58:24.698341 ==
3121 22:58:24.701254 Write leveling (Byte 0): 27 => 27
3122 22:58:24.704883 Write leveling (Byte 1): 29 => 29
3123 22:58:24.707976 DramcWriteLeveling(PI) end<-----
3124 22:58:24.708093
3125 22:58:24.708189 ==
3126 22:58:24.711705 Dram Type= 6, Freq= 0, CH_1, rank 0
3127 22:58:24.714676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3128 22:58:24.714797 ==
3129 22:58:24.718207 [Gating] SW mode calibration
3130 22:58:24.724633 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3131 22:58:24.731134 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3132 22:58:24.734923 0 15 0 | B1->B0 | 3333 2b2a | 0 1 | (0 0) (0 0)
3133 22:58:24.737907 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3134 22:58:24.744890 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3135 22:58:24.748153 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 22:58:24.751144 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3137 22:58:24.758033 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 22:58:24.761172 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 22:58:24.764976 0 15 28 | B1->B0 | 2828 2c2c | 1 0 | (1 0) (0 1)
3140 22:58:24.768036 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3141 22:58:24.774658 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3142 22:58:24.777710 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 22:58:24.781127 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 22:58:24.788110 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 22:58:24.791216 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 22:58:24.794313 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3147 22:58:24.801109 1 0 28 | B1->B0 | 3e3e 3c3c | 0 1 | (0 0) (0 0)
3148 22:58:24.804784 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 22:58:24.807691 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 22:58:24.814546 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 22:58:24.817602 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 22:58:24.820964 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 22:58:24.827567 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 22:58:24.831100 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 22:58:24.833946 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3156 22:58:24.840672 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 22:58:24.844295 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 22:58:24.847347 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 22:58:24.853915 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 22:58:24.857315 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 22:58:24.860505 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 22:58:24.867272 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 22:58:24.870748 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 22:58:24.874168 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 22:58:24.880888 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 22:58:24.883919 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 22:58:24.887025 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 22:58:24.893761 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 22:58:24.897370 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 22:58:24.900470 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 22:58:24.907279 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3172 22:58:24.910369 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3173 22:58:24.913501 Total UI for P1: 0, mck2ui 16
3174 22:58:24.917189 best dqsien dly found for B0: ( 1, 3, 28)
3175 22:58:24.920224 Total UI for P1: 0, mck2ui 16
3176 22:58:24.923374 best dqsien dly found for B1: ( 1, 3, 28)
3177 22:58:24.926772 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3178 22:58:24.930207 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3179 22:58:24.930325
3180 22:58:24.933756 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3181 22:58:24.936721 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3182 22:58:24.940224 [Gating] SW calibration Done
3183 22:58:24.940339 ==
3184 22:58:24.943258 Dram Type= 6, Freq= 0, CH_1, rank 0
3185 22:58:24.946772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3186 22:58:24.950349 ==
3187 22:58:24.950466 RX Vref Scan: 0
3188 22:58:24.950635
3189 22:58:24.953417 RX Vref 0 -> 0, step: 1
3190 22:58:24.953527
3191 22:58:24.953622 RX Delay -40 -> 252, step: 8
3192 22:58:24.960469 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3193 22:58:24.963385 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3194 22:58:24.966986 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3195 22:58:24.969982 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
3196 22:58:24.973725 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3197 22:58:24.980291 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3198 22:58:24.983613 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3199 22:58:24.986464 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3200 22:58:24.990076 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3201 22:58:24.993125 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3202 22:58:25.000018 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3203 22:58:25.003647 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3204 22:58:25.006742 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3205 22:58:25.009884 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3206 22:58:25.016557 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3207 22:58:25.019626 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3208 22:58:25.019745 ==
3209 22:58:25.022776 Dram Type= 6, Freq= 0, CH_1, rank 0
3210 22:58:25.026497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3211 22:58:25.026622 ==
3212 22:58:25.029599 DQS Delay:
3213 22:58:25.029706 DQS0 = 0, DQS1 = 0
3214 22:58:25.029799 DQM Delay:
3215 22:58:25.032723 DQM0 = 113, DQM1 = 106
3216 22:58:25.032831 DQ Delay:
3217 22:58:25.036247 DQ0 =115, DQ1 =107, DQ2 =103, DQ3 =111
3218 22:58:25.039569 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3219 22:58:25.042997 DQ8 =95, DQ9 =99, DQ10 =103, DQ11 =103
3220 22:58:25.049251 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3221 22:58:25.049367
3222 22:58:25.049439
3223 22:58:25.049501 ==
3224 22:58:25.052672 Dram Type= 6, Freq= 0, CH_1, rank 0
3225 22:58:25.056207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3226 22:58:25.056296 ==
3227 22:58:25.056362
3228 22:58:25.056424
3229 22:58:25.059330 TX Vref Scan disable
3230 22:58:25.059402 == TX Byte 0 ==
3231 22:58:25.066146 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3232 22:58:25.069342 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3233 22:58:25.069433 == TX Byte 1 ==
3234 22:58:25.075661 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3235 22:58:25.079502 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3236 22:58:25.079608 ==
3237 22:58:25.082473 Dram Type= 6, Freq= 0, CH_1, rank 0
3238 22:58:25.085517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3239 22:58:25.085636 ==
3240 22:58:25.098536 TX Vref=22, minBit 8, minWin=24, winSum=408
3241 22:58:25.101728 TX Vref=24, minBit 8, minWin=24, winSum=416
3242 22:58:25.105151 TX Vref=26, minBit 8, minWin=25, winSum=420
3243 22:58:25.108205 TX Vref=28, minBit 9, minWin=25, winSum=424
3244 22:58:25.111827 TX Vref=30, minBit 9, minWin=25, winSum=427
3245 22:58:25.118585 TX Vref=32, minBit 0, minWin=26, winSum=424
3246 22:58:25.121645 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 32
3247 22:58:25.121738
3248 22:58:25.125440 Final TX Range 1 Vref 32
3249 22:58:25.125544
3250 22:58:25.125610 ==
3251 22:58:25.128400 Dram Type= 6, Freq= 0, CH_1, rank 0
3252 22:58:25.131577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3253 22:58:25.134691 ==
3254 22:58:25.134813
3255 22:58:25.134930
3256 22:58:25.135007 TX Vref Scan disable
3257 22:58:25.138419 == TX Byte 0 ==
3258 22:58:25.141479 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3259 22:58:25.147989 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3260 22:58:25.148120 == TX Byte 1 ==
3261 22:58:25.151469 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3262 22:58:25.157797 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3263 22:58:25.157906
3264 22:58:25.157976 [DATLAT]
3265 22:58:25.158037 Freq=1200, CH1 RK0
3266 22:58:25.158096
3267 22:58:25.161139 DATLAT Default: 0xd
3268 22:58:25.161225 0, 0xFFFF, sum = 0
3269 22:58:25.164695 1, 0xFFFF, sum = 0
3270 22:58:25.168434 2, 0xFFFF, sum = 0
3271 22:58:25.168526 3, 0xFFFF, sum = 0
3272 22:58:25.171513 4, 0xFFFF, sum = 0
3273 22:58:25.171600 5, 0xFFFF, sum = 0
3274 22:58:25.175034 6, 0xFFFF, sum = 0
3275 22:58:25.175153 7, 0xFFFF, sum = 0
3276 22:58:25.178211 8, 0xFFFF, sum = 0
3277 22:58:25.178302 9, 0xFFFF, sum = 0
3278 22:58:25.181649 10, 0xFFFF, sum = 0
3279 22:58:25.181772 11, 0xFFFF, sum = 0
3280 22:58:25.184788 12, 0x0, sum = 1
3281 22:58:25.184901 13, 0x0, sum = 2
3282 22:58:25.187823 14, 0x0, sum = 3
3283 22:58:25.187929 15, 0x0, sum = 4
3284 22:58:25.191474 best_step = 13
3285 22:58:25.191579
3286 22:58:25.191670 ==
3287 22:58:25.194525 Dram Type= 6, Freq= 0, CH_1, rank 0
3288 22:58:25.198186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3289 22:58:25.198294 ==
3290 22:58:25.198386 RX Vref Scan: 1
3291 22:58:25.198475
3292 22:58:25.201260 Set Vref Range= 32 -> 127
3293 22:58:25.201364
3294 22:58:25.204347 RX Vref 32 -> 127, step: 1
3295 22:58:25.204464
3296 22:58:25.208164 RX Delay -21 -> 252, step: 4
3297 22:58:25.208269
3298 22:58:25.211220 Set Vref, RX VrefLevel [Byte0]: 32
3299 22:58:25.214317 [Byte1]: 32
3300 22:58:25.214426
3301 22:58:25.218087 Set Vref, RX VrefLevel [Byte0]: 33
3302 22:58:25.221095 [Byte1]: 33
3303 22:58:25.224669
3304 22:58:25.224831 Set Vref, RX VrefLevel [Byte0]: 34
3305 22:58:25.227889 [Byte1]: 34
3306 22:58:25.232753
3307 22:58:25.232848 Set Vref, RX VrefLevel [Byte0]: 35
3308 22:58:25.235848 [Byte1]: 35
3309 22:58:25.240773
3310 22:58:25.240866 Set Vref, RX VrefLevel [Byte0]: 36
3311 22:58:25.243752 [Byte1]: 36
3312 22:58:25.248543
3313 22:58:25.248662 Set Vref, RX VrefLevel [Byte0]: 37
3314 22:58:25.251680 [Byte1]: 37
3315 22:58:25.256549
3316 22:58:25.256666 Set Vref, RX VrefLevel [Byte0]: 38
3317 22:58:25.259444 [Byte1]: 38
3318 22:58:25.264443
3319 22:58:25.264549 Set Vref, RX VrefLevel [Byte0]: 39
3320 22:58:25.267901 [Byte1]: 39
3321 22:58:25.271935
3322 22:58:25.272046 Set Vref, RX VrefLevel [Byte0]: 40
3323 22:58:25.275568 [Byte1]: 40
3324 22:58:25.280455
3325 22:58:25.280590 Set Vref, RX VrefLevel [Byte0]: 41
3326 22:58:25.283480 [Byte1]: 41
3327 22:58:25.288257
3328 22:58:25.288366 Set Vref, RX VrefLevel [Byte0]: 42
3329 22:58:25.291517 [Byte1]: 42
3330 22:58:25.295688
3331 22:58:25.295799 Set Vref, RX VrefLevel [Byte0]: 43
3332 22:58:25.299136 [Byte1]: 43
3333 22:58:25.304192
3334 22:58:25.304301 Set Vref, RX VrefLevel [Byte0]: 44
3335 22:58:25.307299 [Byte1]: 44
3336 22:58:25.311792
3337 22:58:25.311910 Set Vref, RX VrefLevel [Byte0]: 45
3338 22:58:25.314891 [Byte1]: 45
3339 22:58:25.319764
3340 22:58:25.319898 Set Vref, RX VrefLevel [Byte0]: 46
3341 22:58:25.323325 [Byte1]: 46
3342 22:58:25.327459
3343 22:58:25.327561 Set Vref, RX VrefLevel [Byte0]: 47
3344 22:58:25.331218 [Byte1]: 47
3345 22:58:25.335456
3346 22:58:25.335563 Set Vref, RX VrefLevel [Byte0]: 48
3347 22:58:25.339175 [Byte1]: 48
3348 22:58:25.343544
3349 22:58:25.343625 Set Vref, RX VrefLevel [Byte0]: 49
3350 22:58:25.346608 [Byte1]: 49
3351 22:58:25.351428
3352 22:58:25.351522 Set Vref, RX VrefLevel [Byte0]: 50
3353 22:58:25.354376 [Byte1]: 50
3354 22:58:25.359318
3355 22:58:25.359436 Set Vref, RX VrefLevel [Byte0]: 51
3356 22:58:25.362316 [Byte1]: 51
3357 22:58:25.367134
3358 22:58:25.367244 Set Vref, RX VrefLevel [Byte0]: 52
3359 22:58:25.370558 [Byte1]: 52
3360 22:58:25.375303
3361 22:58:25.375425 Set Vref, RX VrefLevel [Byte0]: 53
3362 22:58:25.378582 [Byte1]: 53
3363 22:58:25.383479
3364 22:58:25.383604 Set Vref, RX VrefLevel [Byte0]: 54
3365 22:58:25.386507 [Byte1]: 54
3366 22:58:25.390791
3367 22:58:25.390935 Set Vref, RX VrefLevel [Byte0]: 55
3368 22:58:25.394345 [Byte1]: 55
3369 22:58:25.399276
3370 22:58:25.399396 Set Vref, RX VrefLevel [Byte0]: 56
3371 22:58:25.402062 [Byte1]: 56
3372 22:58:25.406970
3373 22:58:25.407084 Set Vref, RX VrefLevel [Byte0]: 57
3374 22:58:25.410036 [Byte1]: 57
3375 22:58:25.414514
3376 22:58:25.414623 Set Vref, RX VrefLevel [Byte0]: 58
3377 22:58:25.418344 [Byte1]: 58
3378 22:58:25.422643
3379 22:58:25.422750 Set Vref, RX VrefLevel [Byte0]: 59
3380 22:58:25.426266 [Byte1]: 59
3381 22:58:25.430455
3382 22:58:25.430575 Set Vref, RX VrefLevel [Byte0]: 60
3383 22:58:25.434050 [Byte1]: 60
3384 22:58:25.438392
3385 22:58:25.438510 Set Vref, RX VrefLevel [Byte0]: 61
3386 22:58:25.441646 [Byte1]: 61
3387 22:58:25.446450
3388 22:58:25.446575 Set Vref, RX VrefLevel [Byte0]: 62
3389 22:58:25.449600 [Byte1]: 62
3390 22:58:25.454537
3391 22:58:25.454713 Set Vref, RX VrefLevel [Byte0]: 63
3392 22:58:25.457484 [Byte1]: 63
3393 22:58:25.462426
3394 22:58:25.462549 Set Vref, RX VrefLevel [Byte0]: 64
3395 22:58:25.465494 [Byte1]: 64
3396 22:58:25.470433
3397 22:58:25.470550 Set Vref, RX VrefLevel [Byte0]: 65
3398 22:58:25.473420 [Byte1]: 65
3399 22:58:25.478168
3400 22:58:25.478296 Set Vref, RX VrefLevel [Byte0]: 66
3401 22:58:25.481697 [Byte1]: 66
3402 22:58:25.486060
3403 22:58:25.486217 Final RX Vref Byte 0 = 51 to rank0
3404 22:58:25.489419 Final RX Vref Byte 1 = 55 to rank0
3405 22:58:25.492815 Final RX Vref Byte 0 = 51 to rank1
3406 22:58:25.495952 Final RX Vref Byte 1 = 55 to rank1==
3407 22:58:25.499079 Dram Type= 6, Freq= 0, CH_1, rank 0
3408 22:58:25.506512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3409 22:58:25.506734 ==
3410 22:58:25.506885 DQS Delay:
3411 22:58:25.507017 DQS0 = 0, DQS1 = 0
3412 22:58:25.509461 DQM Delay:
3413 22:58:25.509599 DQM0 = 113, DQM1 = 107
3414 22:58:25.512510 DQ Delay:
3415 22:58:25.516220 DQ0 =120, DQ1 =108, DQ2 =104, DQ3 =110
3416 22:58:25.519355 DQ4 =110, DQ5 =122, DQ6 =124, DQ7 =108
3417 22:58:25.522528 DQ8 =94, DQ9 =98, DQ10 =106, DQ11 =102
3418 22:58:25.525657 DQ12 =114, DQ13 =114, DQ14 =114, DQ15 =114
3419 22:58:25.525741
3420 22:58:25.525824
3421 22:58:25.536204 [DQSOSCAuto] RK0, (LSB)MR18= 0xecf3, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 418 ps
3422 22:58:25.536329 CH1 RK0: MR19=303, MR18=ECF3
3423 22:58:25.542599 CH1_RK0: MR19=0x303, MR18=0xECF3, DQSOSC=415, MR23=63, INC=38, DEC=25
3424 22:58:25.542708
3425 22:58:25.545595 ----->DramcWriteLeveling(PI) begin...
3426 22:58:25.545677 ==
3427 22:58:25.549318 Dram Type= 6, Freq= 0, CH_1, rank 1
3428 22:58:25.555409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3429 22:58:25.555515 ==
3430 22:58:25.559073 Write leveling (Byte 0): 24 => 24
3431 22:58:25.559166 Write leveling (Byte 1): 27 => 27
3432 22:58:25.562070 DramcWriteLeveling(PI) end<-----
3433 22:58:25.562150
3434 22:58:25.562222 ==
3435 22:58:25.565932 Dram Type= 6, Freq= 0, CH_1, rank 1
3436 22:58:25.572069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3437 22:58:25.572163 ==
3438 22:58:25.575640 [Gating] SW mode calibration
3439 22:58:25.582257 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3440 22:58:25.585280 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3441 22:58:25.592386 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3442 22:58:25.595424 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3443 22:58:25.598504 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3444 22:58:25.605119 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3445 22:58:25.608617 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3446 22:58:25.611817 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3447 22:58:25.618597 0 15 24 | B1->B0 | 3434 2424 | 1 0 | (1 0) (1 0)
3448 22:58:25.621686 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3449 22:58:25.624796 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3450 22:58:25.631768 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3451 22:58:25.634762 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3452 22:58:25.638527 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3453 22:58:25.644532 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3454 22:58:25.648088 1 0 20 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
3455 22:58:25.651175 1 0 24 | B1->B0 | 2d2d 4646 | 0 0 | (1 1) (0 0)
3456 22:58:25.658112 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3457 22:58:25.661196 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 22:58:25.664616 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 22:58:25.671427 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3460 22:58:25.674524 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 22:58:25.677757 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 22:58:25.684464 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 22:58:25.687514 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3464 22:58:25.690978 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3465 22:58:25.698011 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 22:58:25.700941 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 22:58:25.704397 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 22:58:25.711096 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 22:58:25.714259 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 22:58:25.717824 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 22:58:25.724366 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 22:58:25.727512 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 22:58:25.731154 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 22:58:25.737422 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 22:58:25.741174 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 22:58:25.744247 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 22:58:25.750401 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 22:58:25.754293 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 22:58:25.757264 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3480 22:58:25.760450 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3481 22:58:25.764183 Total UI for P1: 0, mck2ui 16
3482 22:58:25.767226 best dqsien dly found for B0: ( 1, 3, 24)
3483 22:58:25.773906 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3484 22:58:25.776822 Total UI for P1: 0, mck2ui 16
3485 22:58:25.780518 best dqsien dly found for B1: ( 1, 3, 26)
3486 22:58:25.783555 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3487 22:58:25.787060 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3488 22:58:25.787152
3489 22:58:25.790613 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3490 22:58:25.793643 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3491 22:58:25.796687 [Gating] SW calibration Done
3492 22:58:25.796770 ==
3493 22:58:25.800304 Dram Type= 6, Freq= 0, CH_1, rank 1
3494 22:58:25.803290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3495 22:58:25.803408 ==
3496 22:58:25.807006 RX Vref Scan: 0
3497 22:58:25.807084
3498 22:58:25.809834 RX Vref 0 -> 0, step: 1
3499 22:58:25.809910
3500 22:58:25.809971 RX Delay -40 -> 252, step: 8
3501 22:58:25.816426 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3502 22:58:25.819935 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3503 22:58:25.823126 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3504 22:58:25.826462 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3505 22:58:25.829768 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3506 22:58:25.836484 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3507 22:58:25.840286 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3508 22:58:25.843250 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3509 22:58:25.846388 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3510 22:58:25.849484 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3511 22:58:25.856092 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3512 22:58:25.859656 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3513 22:58:25.862638 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3514 22:58:25.866368 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3515 22:58:25.872482 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3516 22:58:25.876139 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
3517 22:58:25.876294 ==
3518 22:58:25.879190 Dram Type= 6, Freq= 0, CH_1, rank 1
3519 22:58:25.882361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3520 22:58:25.882476 ==
3521 22:58:25.886069 DQS Delay:
3522 22:58:25.886157 DQS0 = 0, DQS1 = 0
3523 22:58:25.886223 DQM Delay:
3524 22:58:25.889092 DQM0 = 110, DQM1 = 109
3525 22:58:25.889201 DQ Delay:
3526 22:58:25.892624 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3527 22:58:25.895718 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3528 22:58:25.899370 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3529 22:58:25.905601 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =115
3530 22:58:25.905707
3531 22:58:25.905780
3532 22:58:25.905860 ==
3533 22:58:25.908433 Dram Type= 6, Freq= 0, CH_1, rank 1
3534 22:58:25.912233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3535 22:58:25.912340 ==
3536 22:58:25.912428
3537 22:58:25.912488
3538 22:58:25.915270 TX Vref Scan disable
3539 22:58:25.915350 == TX Byte 0 ==
3540 22:58:25.922079 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3541 22:58:25.925080 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3542 22:58:25.928773 == TX Byte 1 ==
3543 22:58:25.931806 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3544 22:58:25.935069 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3545 22:58:25.935180 ==
3546 22:58:25.938061 Dram Type= 6, Freq= 0, CH_1, rank 1
3547 22:58:25.941582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3548 22:58:25.944681 ==
3549 22:58:25.954761 TX Vref=22, minBit 9, minWin=25, winSum=421
3550 22:58:25.958412 TX Vref=24, minBit 0, minWin=26, winSum=427
3551 22:58:25.961458 TX Vref=26, minBit 0, minWin=26, winSum=430
3552 22:58:25.965136 TX Vref=28, minBit 1, minWin=26, winSum=428
3553 22:58:25.968105 TX Vref=30, minBit 8, minWin=26, winSum=434
3554 22:58:25.974834 TX Vref=32, minBit 1, minWin=26, winSum=430
3555 22:58:25.978434 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 30
3556 22:58:25.978550
3557 22:58:25.981518 Final TX Range 1 Vref 30
3558 22:58:25.981613
3559 22:58:25.981681 ==
3560 22:58:25.984583 Dram Type= 6, Freq= 0, CH_1, rank 1
3561 22:58:25.988382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3562 22:58:25.988499 ==
3563 22:58:25.991627
3564 22:58:25.991712
3565 22:58:25.991777 TX Vref Scan disable
3566 22:58:25.995042 == TX Byte 0 ==
3567 22:58:25.998010 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3568 22:58:26.004826 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3569 22:58:26.004934 == TX Byte 1 ==
3570 22:58:26.007822 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3571 22:58:26.014465 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3572 22:58:26.014575
3573 22:58:26.014644 [DATLAT]
3574 22:58:26.014721 Freq=1200, CH1 RK1
3575 22:58:26.014781
3576 22:58:26.018056 DATLAT Default: 0xd
3577 22:58:26.021201 0, 0xFFFF, sum = 0
3578 22:58:26.021290 1, 0xFFFF, sum = 0
3579 22:58:26.024091 2, 0xFFFF, sum = 0
3580 22:58:26.024211 3, 0xFFFF, sum = 0
3581 22:58:26.027632 4, 0xFFFF, sum = 0
3582 22:58:26.027768 5, 0xFFFF, sum = 0
3583 22:58:26.030672 6, 0xFFFF, sum = 0
3584 22:58:26.030784 7, 0xFFFF, sum = 0
3585 22:58:26.034430 8, 0xFFFF, sum = 0
3586 22:58:26.034531 9, 0xFFFF, sum = 0
3587 22:58:26.037411 10, 0xFFFF, sum = 0
3588 22:58:26.037511 11, 0xFFFF, sum = 0
3589 22:58:26.040855 12, 0x0, sum = 1
3590 22:58:26.040954 13, 0x0, sum = 2
3591 22:58:26.043952 14, 0x0, sum = 3
3592 22:58:26.044032 15, 0x0, sum = 4
3593 22:58:26.047630 best_step = 13
3594 22:58:26.047719
3595 22:58:26.047784 ==
3596 22:58:26.050892 Dram Type= 6, Freq= 0, CH_1, rank 1
3597 22:58:26.053974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3598 22:58:26.054056 ==
3599 22:58:26.057159 RX Vref Scan: 0
3600 22:58:26.057237
3601 22:58:26.057302 RX Vref 0 -> 0, step: 1
3602 22:58:26.057380
3603 22:58:26.060800 RX Delay -21 -> 252, step: 4
3604 22:58:26.067476 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3605 22:58:26.070707 iDelay=195, Bit 1, Center 108 (39 ~ 178) 140
3606 22:58:26.073830 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3607 22:58:26.076846 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3608 22:58:26.080513 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3609 22:58:26.087067 iDelay=195, Bit 5, Center 118 (47 ~ 190) 144
3610 22:58:26.090173 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3611 22:58:26.093336 iDelay=195, Bit 7, Center 108 (39 ~ 178) 140
3612 22:58:26.097026 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3613 22:58:26.099919 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3614 22:58:26.106714 iDelay=195, Bit 10, Center 112 (43 ~ 182) 140
3615 22:58:26.110446 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3616 22:58:26.113539 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3617 22:58:26.116579 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3618 22:58:26.123132 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3619 22:58:26.126985 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3620 22:58:26.127087 ==
3621 22:58:26.129774 Dram Type= 6, Freq= 0, CH_1, rank 1
3622 22:58:26.133291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3623 22:58:26.133381 ==
3624 22:58:26.136822 DQS Delay:
3625 22:58:26.136908 DQS0 = 0, DQS1 = 0
3626 22:58:26.136974 DQM Delay:
3627 22:58:26.139955 DQM0 = 110, DQM1 = 110
3628 22:58:26.140034 DQ Delay:
3629 22:58:26.142961 DQ0 =114, DQ1 =108, DQ2 =100, DQ3 =108
3630 22:58:26.146608 DQ4 =108, DQ5 =118, DQ6 =122, DQ7 =108
3631 22:58:26.149623 DQ8 =96, DQ9 =102, DQ10 =112, DQ11 =104
3632 22:58:26.156454 DQ12 =118, DQ13 =116, DQ14 =116, DQ15 =120
3633 22:58:26.156566
3634 22:58:26.156638
3635 22:58:26.163109 [DQSOSCAuto] RK1, (LSB)MR18= 0xf808, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3636 22:58:26.166240 CH1 RK1: MR19=304, MR18=F808
3637 22:58:26.173073 CH1_RK1: MR19=0x304, MR18=0xF808, DQSOSC=406, MR23=63, INC=39, DEC=26
3638 22:58:26.176235 [RxdqsGatingPostProcess] freq 1200
3639 22:58:26.179826 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3640 22:58:26.182696 best DQS0 dly(2T, 0.5T) = (0, 11)
3641 22:58:26.186114 best DQS1 dly(2T, 0.5T) = (0, 11)
3642 22:58:26.189176 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3643 22:58:26.193150 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3644 22:58:26.196171 best DQS0 dly(2T, 0.5T) = (0, 11)
3645 22:58:26.199144 best DQS1 dly(2T, 0.5T) = (0, 11)
3646 22:58:26.202745 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3647 22:58:26.205760 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3648 22:58:26.209390 Pre-setting of DQS Precalculation
3649 22:58:26.212496 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3650 22:58:26.222667 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3651 22:58:26.228982 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3652 22:58:26.229098
3653 22:58:26.229171
3654 22:58:26.232153 [Calibration Summary] 2400 Mbps
3655 22:58:26.232281 CH 0, Rank 0
3656 22:58:26.235577 SW Impedance : PASS
3657 22:58:26.235663 DUTY Scan : NO K
3658 22:58:26.239142 ZQ Calibration : PASS
3659 22:58:26.242021 Jitter Meter : NO K
3660 22:58:26.242119 CBT Training : PASS
3661 22:58:26.245824 Write leveling : PASS
3662 22:58:26.248673 RX DQS gating : PASS
3663 22:58:26.248791 RX DQ/DQS(RDDQC) : PASS
3664 22:58:26.252358 TX DQ/DQS : PASS
3665 22:58:26.255535 RX DATLAT : PASS
3666 22:58:26.255626 RX DQ/DQS(Engine): PASS
3667 22:58:26.258549 TX OE : NO K
3668 22:58:26.258624 All Pass.
3669 22:58:26.258686
3670 22:58:26.261835 CH 0, Rank 1
3671 22:58:26.261908 SW Impedance : PASS
3672 22:58:26.265117 DUTY Scan : NO K
3673 22:58:26.268259 ZQ Calibration : PASS
3674 22:58:26.268352 Jitter Meter : NO K
3675 22:58:26.272028 CBT Training : PASS
3676 22:58:26.275059 Write leveling : PASS
3677 22:58:26.275150 RX DQS gating : PASS
3678 22:58:26.278227 RX DQ/DQS(RDDQC) : PASS
3679 22:58:26.281907 TX DQ/DQS : PASS
3680 22:58:26.282008 RX DATLAT : PASS
3681 22:58:26.285106 RX DQ/DQS(Engine): PASS
3682 22:58:26.287967 TX OE : NO K
3683 22:58:26.288057 All Pass.
3684 22:58:26.288125
3685 22:58:26.288186 CH 1, Rank 0
3686 22:58:26.291451 SW Impedance : PASS
3687 22:58:26.294773 DUTY Scan : NO K
3688 22:58:26.294889 ZQ Calibration : PASS
3689 22:58:26.298310 Jitter Meter : NO K
3690 22:58:26.301469 CBT Training : PASS
3691 22:58:26.301558 Write leveling : PASS
3692 22:58:26.304644 RX DQS gating : PASS
3693 22:58:26.308199 RX DQ/DQS(RDDQC) : PASS
3694 22:58:26.308289 TX DQ/DQS : PASS
3695 22:58:26.311221 RX DATLAT : PASS
3696 22:58:26.311307 RX DQ/DQS(Engine): PASS
3697 22:58:26.314347 TX OE : NO K
3698 22:58:26.314435 All Pass.
3699 22:58:26.314501
3700 22:58:26.317988 CH 1, Rank 1
3701 22:58:26.318074 SW Impedance : PASS
3702 22:58:26.320965 DUTY Scan : NO K
3703 22:58:26.324663 ZQ Calibration : PASS
3704 22:58:26.324751 Jitter Meter : NO K
3705 22:58:26.327796 CBT Training : PASS
3706 22:58:26.331221 Write leveling : PASS
3707 22:58:26.331310 RX DQS gating : PASS
3708 22:58:26.334477 RX DQ/DQS(RDDQC) : PASS
3709 22:58:26.337443 TX DQ/DQS : PASS
3710 22:58:26.337534 RX DATLAT : PASS
3711 22:58:26.341174 RX DQ/DQS(Engine): PASS
3712 22:58:26.344133 TX OE : NO K
3713 22:58:26.344229 All Pass.
3714 22:58:26.344296
3715 22:58:26.347587 DramC Write-DBI off
3716 22:58:26.347675 PER_BANK_REFRESH: Hybrid Mode
3717 22:58:26.350560 TX_TRACKING: ON
3718 22:58:26.357513 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3719 22:58:26.363734 [FAST_K] Save calibration result to emmc
3720 22:58:26.367346 dramc_set_vcore_voltage set vcore to 650000
3721 22:58:26.367448 Read voltage for 600, 5
3722 22:58:26.370459 Vio18 = 0
3723 22:58:26.370567 Vcore = 650000
3724 22:58:26.370650 Vdram = 0
3725 22:58:26.374234 Vddq = 0
3726 22:58:26.374319 Vmddr = 0
3727 22:58:26.377328 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3728 22:58:26.384236 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3729 22:58:26.387327 MEM_TYPE=3, freq_sel=19
3730 22:58:26.390503 sv_algorithm_assistance_LP4_1600
3731 22:58:26.393545 ============ PULL DRAM RESETB DOWN ============
3732 22:58:26.397064 ========== PULL DRAM RESETB DOWN end =========
3733 22:58:26.403545 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3734 22:58:26.407166 ===================================
3735 22:58:26.407270 LPDDR4 DRAM CONFIGURATION
3736 22:58:26.410160 ===================================
3737 22:58:26.413753 EX_ROW_EN[0] = 0x0
3738 22:58:26.417188 EX_ROW_EN[1] = 0x0
3739 22:58:26.417287 LP4Y_EN = 0x0
3740 22:58:26.420378 WORK_FSP = 0x0
3741 22:58:26.420467 WL = 0x2
3742 22:58:26.423543 RL = 0x2
3743 22:58:26.423626 BL = 0x2
3744 22:58:26.426615 RPST = 0x0
3745 22:58:26.426700 RD_PRE = 0x0
3746 22:58:26.430311 WR_PRE = 0x1
3747 22:58:26.430396 WR_PST = 0x0
3748 22:58:26.433540 DBI_WR = 0x0
3749 22:58:26.433625 DBI_RD = 0x0
3750 22:58:26.436731 OTF = 0x1
3751 22:58:26.439783 ===================================
3752 22:58:26.443293 ===================================
3753 22:58:26.443380 ANA top config
3754 22:58:26.446191 ===================================
3755 22:58:26.449832 DLL_ASYNC_EN = 0
3756 22:58:26.452780 ALL_SLAVE_EN = 1
3757 22:58:26.456246 NEW_RANK_MODE = 1
3758 22:58:26.456339 DLL_IDLE_MODE = 1
3759 22:58:26.459667 LP45_APHY_COMB_EN = 1
3760 22:58:26.462751 TX_ODT_DIS = 1
3761 22:58:26.466430 NEW_8X_MODE = 1
3762 22:58:26.469613 ===================================
3763 22:58:26.472654 ===================================
3764 22:58:26.476153 data_rate = 1200
3765 22:58:26.476290 CKR = 1
3766 22:58:26.479266 DQ_P2S_RATIO = 8
3767 22:58:26.482477 ===================================
3768 22:58:26.486229 CA_P2S_RATIO = 8
3769 22:58:26.489446 DQ_CA_OPEN = 0
3770 22:58:26.492534 DQ_SEMI_OPEN = 0
3771 22:58:26.495644 CA_SEMI_OPEN = 0
3772 22:58:26.495748 CA_FULL_RATE = 0
3773 22:58:26.499356 DQ_CKDIV4_EN = 1
3774 22:58:26.502319 CA_CKDIV4_EN = 1
3775 22:58:26.505984 CA_PREDIV_EN = 0
3776 22:58:26.509002 PH8_DLY = 0
3777 22:58:26.512555 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3778 22:58:26.512701 DQ_AAMCK_DIV = 4
3779 22:58:26.515687 CA_AAMCK_DIV = 4
3780 22:58:26.519160 CA_ADMCK_DIV = 4
3781 22:58:26.522344 DQ_TRACK_CA_EN = 0
3782 22:58:26.525394 CA_PICK = 600
3783 22:58:26.529126 CA_MCKIO = 600
3784 22:58:26.532272 MCKIO_SEMI = 0
3785 22:58:26.532389 PLL_FREQ = 2288
3786 22:58:26.535725 DQ_UI_PI_RATIO = 32
3787 22:58:26.538706 CA_UI_PI_RATIO = 0
3788 22:58:26.541934 ===================================
3789 22:58:26.545746 ===================================
3790 22:58:26.548744 memory_type:LPDDR4
3791 22:58:26.552192 GP_NUM : 10
3792 22:58:26.552309 SRAM_EN : 1
3793 22:58:26.555155 MD32_EN : 0
3794 22:58:26.558700 ===================================
3795 22:58:26.558840 [ANA_INIT] >>>>>>>>>>>>>>
3796 22:58:26.561776 <<<<<< [CONFIGURE PHASE]: ANA_TX
3797 22:58:26.565160 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3798 22:58:26.568104 ===================================
3799 22:58:26.571534 data_rate = 1200,PCW = 0X5800
3800 22:58:26.575215 ===================================
3801 22:58:26.578222 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3802 22:58:26.584657 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3803 22:58:26.591498 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3804 22:58:26.594663 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3805 22:58:26.597774 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3806 22:58:26.600983 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3807 22:58:26.604642 [ANA_INIT] flow start
3808 22:58:26.604758 [ANA_INIT] PLL >>>>>>>>
3809 22:58:26.607659 [ANA_INIT] PLL <<<<<<<<
3810 22:58:26.611219 [ANA_INIT] MIDPI >>>>>>>>
3811 22:58:26.614209 [ANA_INIT] MIDPI <<<<<<<<
3812 22:58:26.614327 [ANA_INIT] DLL >>>>>>>>
3813 22:58:26.617747 [ANA_INIT] flow end
3814 22:58:26.621386 ============ LP4 DIFF to SE enter ============
3815 22:58:26.624230 ============ LP4 DIFF to SE exit ============
3816 22:58:26.627827 [ANA_INIT] <<<<<<<<<<<<<
3817 22:58:26.631042 [Flow] Enable top DCM control >>>>>
3818 22:58:26.634100 [Flow] Enable top DCM control <<<<<
3819 22:58:26.637206 Enable DLL master slave shuffle
3820 22:58:26.643976 ==============================================================
3821 22:58:26.644109 Gating Mode config
3822 22:58:26.650354 ==============================================================
3823 22:58:26.650478 Config description:
3824 22:58:26.660554 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3825 22:58:26.667057 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3826 22:58:26.673513 SELPH_MODE 0: By rank 1: By Phase
3827 22:58:26.677098 ==============================================================
3828 22:58:26.680724 GAT_TRACK_EN = 1
3829 22:58:26.683850 RX_GATING_MODE = 2
3830 22:58:26.687263 RX_GATING_TRACK_MODE = 2
3831 22:58:26.690369 SELPH_MODE = 1
3832 22:58:26.693457 PICG_EARLY_EN = 1
3833 22:58:26.697203 VALID_LAT_VALUE = 1
3834 22:58:26.703446 ==============================================================
3835 22:58:26.707185 Enter into Gating configuration >>>>
3836 22:58:26.710164 Exit from Gating configuration <<<<
3837 22:58:26.713183 Enter into DVFS_PRE_config >>>>>
3838 22:58:26.723157 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3839 22:58:26.726545 Exit from DVFS_PRE_config <<<<<
3840 22:58:26.729633 Enter into PICG configuration >>>>
3841 22:58:26.733150 Exit from PICG configuration <<<<
3842 22:58:26.736168 [RX_INPUT] configuration >>>>>
3843 22:58:26.740042 [RX_INPUT] configuration <<<<<
3844 22:58:26.743226 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3845 22:58:26.749339 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3846 22:58:26.756199 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3847 22:58:26.759900 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3848 22:58:26.765929 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3849 22:58:26.772931 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3850 22:58:26.775755 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3851 22:58:26.783059 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3852 22:58:26.786543 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3853 22:58:26.789210 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3854 22:58:26.792782 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3855 22:58:26.799518 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3856 22:58:26.802307 ===================================
3857 22:58:26.802406 LPDDR4 DRAM CONFIGURATION
3858 22:58:26.806059 ===================================
3859 22:58:26.809206 EX_ROW_EN[0] = 0x0
3860 22:58:26.812305 EX_ROW_EN[1] = 0x0
3861 22:58:26.812395 LP4Y_EN = 0x0
3862 22:58:26.815374 WORK_FSP = 0x0
3863 22:58:26.815458 WL = 0x2
3864 22:58:26.819259 RL = 0x2
3865 22:58:26.819344 BL = 0x2
3866 22:58:26.822066 RPST = 0x0
3867 22:58:26.822149 RD_PRE = 0x0
3868 22:58:26.825556 WR_PRE = 0x1
3869 22:58:26.825639 WR_PST = 0x0
3870 22:58:26.828532 DBI_WR = 0x0
3871 22:58:26.828615 DBI_RD = 0x0
3872 22:58:26.832196 OTF = 0x1
3873 22:58:26.835709 ===================================
3874 22:58:26.838577 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3875 22:58:26.841570 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3876 22:58:26.848419 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3877 22:58:26.851524 ===================================
3878 22:58:26.851619 LPDDR4 DRAM CONFIGURATION
3879 22:58:26.855303 ===================================
3880 22:58:26.858395 EX_ROW_EN[0] = 0x10
3881 22:58:26.861517 EX_ROW_EN[1] = 0x0
3882 22:58:26.861607 LP4Y_EN = 0x0
3883 22:58:26.864747 WORK_FSP = 0x0
3884 22:58:26.864850 WL = 0x2
3885 22:58:26.868430 RL = 0x2
3886 22:58:26.868517 BL = 0x2
3887 22:58:26.871536 RPST = 0x0
3888 22:58:26.871636 RD_PRE = 0x0
3889 22:58:26.874520 WR_PRE = 0x1
3890 22:58:26.874606 WR_PST = 0x0
3891 22:58:26.878109 DBI_WR = 0x0
3892 22:58:26.878230 DBI_RD = 0x0
3893 22:58:26.881560 OTF = 0x1
3894 22:58:26.884574 ===================================
3895 22:58:26.891080 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3896 22:58:26.894690 nWR fixed to 30
3897 22:58:26.897729 [ModeRegInit_LP4] CH0 RK0
3898 22:58:26.897872 [ModeRegInit_LP4] CH0 RK1
3899 22:58:26.901251 [ModeRegInit_LP4] CH1 RK0
3900 22:58:26.904767 [ModeRegInit_LP4] CH1 RK1
3901 22:58:26.904903 match AC timing 17
3902 22:58:26.910986 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3903 22:58:26.914114 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3904 22:58:26.917807 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3905 22:58:26.924058 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3906 22:58:26.927737 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3907 22:58:26.927827 ==
3908 22:58:26.930704 Dram Type= 6, Freq= 0, CH_0, rank 0
3909 22:58:26.934286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3910 22:58:26.934398 ==
3911 22:58:26.940779 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3912 22:58:26.947114 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3913 22:58:26.950685 [CA 0] Center 37 (7~67) winsize 61
3914 22:58:26.953684 [CA 1] Center 36 (6~67) winsize 62
3915 22:58:26.957397 [CA 2] Center 35 (5~65) winsize 61
3916 22:58:26.960399 [CA 3] Center 35 (5~65) winsize 61
3917 22:58:26.963536 [CA 4] Center 34 (4~64) winsize 61
3918 22:58:26.966718 [CA 5] Center 33 (3~64) winsize 62
3919 22:58:26.966825
3920 22:58:26.970461 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3921 22:58:26.970563
3922 22:58:26.973490 [CATrainingPosCal] consider 1 rank data
3923 22:58:26.977196 u2DelayCellTimex100 = 270/100 ps
3924 22:58:26.980253 CA0 delay=37 (7~67),Diff = 4 PI (38 cell)
3925 22:58:26.983685 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3926 22:58:26.986765 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3927 22:58:26.993397 CA3 delay=35 (5~65),Diff = 2 PI (19 cell)
3928 22:58:26.996869 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3929 22:58:26.999852 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3930 22:58:26.999960
3931 22:58:27.003330 CA PerBit enable=1, Macro0, CA PI delay=33
3932 22:58:27.003432
3933 22:58:27.007004 [CBTSetCACLKResult] CA Dly = 33
3934 22:58:27.007096 CS Dly: 6 (0~37)
3935 22:58:27.007163 ==
3936 22:58:27.009877 Dram Type= 6, Freq= 0, CH_0, rank 1
3937 22:58:27.016560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3938 22:58:27.016663 ==
3939 22:58:27.020285 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3940 22:58:27.026457 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3941 22:58:27.030146 [CA 0] Center 37 (7~67) winsize 61
3942 22:58:27.033239 [CA 1] Center 37 (7~67) winsize 61
3943 22:58:27.037009 [CA 2] Center 35 (5~65) winsize 61
3944 22:58:27.040043 [CA 3] Center 35 (5~65) winsize 61
3945 22:58:27.043456 [CA 4] Center 34 (4~65) winsize 62
3946 22:58:27.046955 [CA 5] Center 34 (4~64) winsize 61
3947 22:58:27.047055
3948 22:58:27.049856 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3949 22:58:27.049940
3950 22:58:27.053304 [CATrainingPosCal] consider 2 rank data
3951 22:58:27.056761 u2DelayCellTimex100 = 270/100 ps
3952 22:58:27.059583 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3953 22:58:27.066352 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3954 22:58:27.069461 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3955 22:58:27.073268 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3956 22:58:27.076346 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3957 22:58:27.079438 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3958 22:58:27.079528
3959 22:58:27.083221 CA PerBit enable=1, Macro0, CA PI delay=34
3960 22:58:27.083321
3961 22:58:27.086097 [CBTSetCACLKResult] CA Dly = 34
3962 22:58:27.089763 CS Dly: 5 (0~36)
3963 22:58:27.089853
3964 22:58:27.092962 ----->DramcWriteLeveling(PI) begin...
3965 22:58:27.093049 ==
3966 22:58:27.095852 Dram Type= 6, Freq= 0, CH_0, rank 0
3967 22:58:27.099420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3968 22:58:27.099512 ==
3969 22:58:27.102678 Write leveling (Byte 0): 32 => 32
3970 22:58:27.105718 Write leveling (Byte 1): 31 => 31
3971 22:58:27.109391 DramcWriteLeveling(PI) end<-----
3972 22:58:27.109485
3973 22:58:27.109552 ==
3974 22:58:27.112738 Dram Type= 6, Freq= 0, CH_0, rank 0
3975 22:58:27.115582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3976 22:58:27.115678 ==
3977 22:58:27.119021 [Gating] SW mode calibration
3978 22:58:27.125710 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3979 22:58:27.132519 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3980 22:58:27.135553 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3981 22:58:27.138709 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3982 22:58:27.145551 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3983 22:58:27.148476 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
3984 22:58:27.152150 0 9 16 | B1->B0 | 3131 2b2b | 0 0 | (0 0) (0 0)
3985 22:58:27.158849 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3986 22:58:27.161749 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 22:58:27.165123 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 22:58:27.171864 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 22:58:27.175012 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 22:58:27.178779 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 22:58:27.184847 0 10 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
3992 22:58:27.188491 0 10 16 | B1->B0 | 3030 3c3c | 0 0 | (1 1) (0 0)
3993 22:58:27.191476 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 22:58:27.198096 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 22:58:27.201221 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 22:58:27.204831 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 22:58:27.211458 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 22:58:27.214396 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 22:58:27.218010 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4000 22:58:27.224366 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4001 22:58:27.227810 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 22:58:27.234034 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 22:58:27.237616 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 22:58:27.240697 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 22:58:27.247382 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 22:58:27.250488 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 22:58:27.254142 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 22:58:27.260788 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 22:58:27.263612 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 22:58:27.267008 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 22:58:27.273851 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 22:58:27.276811 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 22:58:27.280018 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 22:58:27.286768 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 22:58:27.289951 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4016 22:58:27.293482 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4017 22:58:27.296948 Total UI for P1: 0, mck2ui 16
4018 22:58:27.299814 best dqsien dly found for B0: ( 0, 13, 12)
4019 22:58:27.306724 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 22:58:27.306848 Total UI for P1: 0, mck2ui 16
4021 22:58:27.309871 best dqsien dly found for B1: ( 0, 13, 16)
4022 22:58:27.316536 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4023 22:58:27.319948 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4024 22:58:27.320054
4025 22:58:27.323523 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4026 22:58:27.326367 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4027 22:58:27.329839 [Gating] SW calibration Done
4028 22:58:27.329933 ==
4029 22:58:27.332737 Dram Type= 6, Freq= 0, CH_0, rank 0
4030 22:58:27.336367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4031 22:58:27.336460 ==
4032 22:58:27.339421 RX Vref Scan: 0
4033 22:58:27.339506
4034 22:58:27.339571 RX Vref 0 -> 0, step: 1
4035 22:58:27.339631
4036 22:58:27.343286 RX Delay -230 -> 252, step: 16
4037 22:58:27.349493 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4038 22:58:27.352672 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4039 22:58:27.355864 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4040 22:58:27.359472 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4041 22:58:27.366134 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4042 22:58:27.369168 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4043 22:58:27.372256 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4044 22:58:27.375777 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4045 22:58:27.379414 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4046 22:58:27.385817 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4047 22:58:27.389100 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4048 22:58:27.392108 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4049 22:58:27.395798 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4050 22:58:27.402357 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4051 22:58:27.405469 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4052 22:58:27.408553 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4053 22:58:27.408672 ==
4054 22:58:27.412268 Dram Type= 6, Freq= 0, CH_0, rank 0
4055 22:58:27.418453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4056 22:58:27.418562 ==
4057 22:58:27.418633 DQS Delay:
4058 22:58:27.418695 DQS0 = 0, DQS1 = 0
4059 22:58:27.422021 DQM Delay:
4060 22:58:27.422109 DQM0 = 38, DQM1 = 28
4061 22:58:27.424879 DQ Delay:
4062 22:58:27.428203 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4063 22:58:27.428293 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4064 22:58:27.431589 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4065 22:58:27.438068 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4066 22:58:27.438171
4067 22:58:27.438239
4068 22:58:27.438316 ==
4069 22:58:27.441703 Dram Type= 6, Freq= 0, CH_0, rank 0
4070 22:58:27.444687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4071 22:58:27.444795 ==
4072 22:58:27.444876
4073 22:58:27.444937
4074 22:58:27.448448 TX Vref Scan disable
4075 22:58:27.448535 == TX Byte 0 ==
4076 22:58:27.454641 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4077 22:58:27.457852 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4078 22:58:27.457943 == TX Byte 1 ==
4079 22:58:27.464704 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4080 22:58:27.467709 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4081 22:58:27.467819 ==
4082 22:58:27.471378 Dram Type= 6, Freq= 0, CH_0, rank 0
4083 22:58:27.474717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4084 22:58:27.474811 ==
4085 22:58:27.477898
4086 22:58:27.478013
4087 22:58:27.478109 TX Vref Scan disable
4088 22:58:27.481334 == TX Byte 0 ==
4089 22:58:27.485001 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4090 22:58:27.491302 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4091 22:58:27.491458 == TX Byte 1 ==
4092 22:58:27.495075 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4093 22:58:27.501206 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4094 22:58:27.501338
4095 22:58:27.501436 [DATLAT]
4096 22:58:27.501557 Freq=600, CH0 RK0
4097 22:58:27.501649
4098 22:58:27.504822 DATLAT Default: 0x9
4099 22:58:27.504932 0, 0xFFFF, sum = 0
4100 22:58:27.507814 1, 0xFFFF, sum = 0
4101 22:58:27.507962 2, 0xFFFF, sum = 0
4102 22:58:27.511445 3, 0xFFFF, sum = 0
4103 22:58:27.514512 4, 0xFFFF, sum = 0
4104 22:58:27.514626 5, 0xFFFF, sum = 0
4105 22:58:27.517694 6, 0xFFFF, sum = 0
4106 22:58:27.517805 7, 0xFFFF, sum = 0
4107 22:58:27.521333 8, 0x0, sum = 1
4108 22:58:27.521445 9, 0x0, sum = 2
4109 22:58:27.521542 10, 0x0, sum = 3
4110 22:58:27.524552 11, 0x0, sum = 4
4111 22:58:27.524663 best_step = 9
4112 22:58:27.524758
4113 22:58:27.524850 ==
4114 22:58:27.527522 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 22:58:27.534124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 22:58:27.534262 ==
4117 22:58:27.534362 RX Vref Scan: 1
4118 22:58:27.534454
4119 22:58:27.537603 RX Vref 0 -> 0, step: 1
4120 22:58:27.537711
4121 22:58:27.540764 RX Delay -195 -> 252, step: 8
4122 22:58:27.540879
4123 22:58:27.544286 Set Vref, RX VrefLevel [Byte0]: 60
4124 22:58:27.547921 [Byte1]: 47
4125 22:58:27.548038
4126 22:58:27.550901 Final RX Vref Byte 0 = 60 to rank0
4127 22:58:27.553945 Final RX Vref Byte 1 = 47 to rank0
4128 22:58:27.557514 Final RX Vref Byte 0 = 60 to rank1
4129 22:58:27.560580 Final RX Vref Byte 1 = 47 to rank1==
4130 22:58:27.564446 Dram Type= 6, Freq= 0, CH_0, rank 0
4131 22:58:27.567459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4132 22:58:27.570523 ==
4133 22:58:27.570642 DQS Delay:
4134 22:58:27.570754 DQS0 = 0, DQS1 = 0
4135 22:58:27.574258 DQM Delay:
4136 22:58:27.574463 DQM0 = 35, DQM1 = 29
4137 22:58:27.577338 DQ Delay:
4138 22:58:27.577479 DQ0 =36, DQ1 =36, DQ2 =32, DQ3 =32
4139 22:58:27.580716 DQ4 =32, DQ5 =24, DQ6 =40, DQ7 =48
4140 22:58:27.584207 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4141 22:58:27.587091 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =36
4142 22:58:27.587232
4143 22:58:27.590533
4144 22:58:27.596966 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c3c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
4145 22:58:27.600075 CH0 RK0: MR19=808, MR18=3C3C
4146 22:58:27.606983 CH0_RK0: MR19=0x808, MR18=0x3C3C, DQSOSC=398, MR23=63, INC=165, DEC=110
4147 22:58:27.607128
4148 22:58:27.610002 ----->DramcWriteLeveling(PI) begin...
4149 22:58:27.610116 ==
4150 22:58:27.613574 Dram Type= 6, Freq= 0, CH_0, rank 1
4151 22:58:27.616587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4152 22:58:27.616701 ==
4153 22:58:27.620266 Write leveling (Byte 0): 32 => 32
4154 22:58:27.623360 Write leveling (Byte 1): 29 => 29
4155 22:58:27.626411 DramcWriteLeveling(PI) end<-----
4156 22:58:27.626525
4157 22:58:27.626621 ==
4158 22:58:27.630152 Dram Type= 6, Freq= 0, CH_0, rank 1
4159 22:58:27.633299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4160 22:58:27.633414 ==
4161 22:58:27.637013 [Gating] SW mode calibration
4162 22:58:27.643422 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4163 22:58:27.649748 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4164 22:58:27.653150 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4165 22:58:27.659811 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4166 22:58:27.662690 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4167 22:58:27.666277 0 9 12 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 1)
4168 22:58:27.672451 0 9 16 | B1->B0 | 2e2e 2323 | 1 0 | (0 1) (0 0)
4169 22:58:27.676171 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 22:58:27.679206 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 22:58:27.686046 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 22:58:27.689172 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4173 22:58:27.692770 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 22:58:27.699146 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 22:58:27.702046 0 10 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
4176 22:58:27.705741 0 10 16 | B1->B0 | 3636 4646 | 0 0 | (1 1) (0 0)
4177 22:58:27.712429 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 22:58:27.715463 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 22:58:27.719234 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 22:58:27.725474 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 22:58:27.728557 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 22:58:27.732249 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 22:58:27.738556 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4184 22:58:27.742182 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 22:58:27.745235 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 22:58:27.751923 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 22:58:27.755426 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 22:58:27.758315 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 22:58:27.765391 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 22:58:27.768288 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 22:58:27.771822 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 22:58:27.778087 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 22:58:27.781705 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 22:58:27.784850 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 22:58:27.791539 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 22:58:27.795314 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 22:58:27.798068 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 22:58:27.804555 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 22:58:27.808076 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4200 22:58:27.811669 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4201 22:58:27.814712 Total UI for P1: 0, mck2ui 16
4202 22:58:27.817641 best dqsien dly found for B0: ( 0, 13, 12)
4203 22:58:27.821416 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4204 22:58:27.824442 Total UI for P1: 0, mck2ui 16
4205 22:58:27.828064 best dqsien dly found for B1: ( 0, 13, 16)
4206 22:58:27.834326 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4207 22:58:27.838134 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4208 22:58:27.838259
4209 22:58:27.841125 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4210 22:58:27.844275 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4211 22:58:27.847801 [Gating] SW calibration Done
4212 22:58:27.847917 ==
4213 22:58:27.850979 Dram Type= 6, Freq= 0, CH_0, rank 1
4214 22:58:27.854479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4215 22:58:27.854592 ==
4216 22:58:27.857956 RX Vref Scan: 0
4217 22:58:27.858068
4218 22:58:27.858196 RX Vref 0 -> 0, step: 1
4219 22:58:27.858289
4220 22:58:27.860969 RX Delay -230 -> 252, step: 16
4221 22:58:27.864079 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4222 22:58:27.870668 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4223 22:58:27.874213 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4224 22:58:27.877277 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4225 22:58:27.880838 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4226 22:58:27.887121 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4227 22:58:27.890833 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4228 22:58:27.893924 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4229 22:58:27.897373 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4230 22:58:27.903704 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4231 22:58:27.907147 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4232 22:58:27.910159 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4233 22:58:27.913641 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4234 22:58:27.920147 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4235 22:58:27.923735 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4236 22:58:27.926813 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4237 22:58:27.926938 ==
4238 22:58:27.930006 Dram Type= 6, Freq= 0, CH_0, rank 1
4239 22:58:27.933114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4240 22:58:27.936777 ==
4241 22:58:27.936890 DQS Delay:
4242 22:58:27.936986 DQS0 = 0, DQS1 = 0
4243 22:58:27.939996 DQM Delay:
4244 22:58:27.940103 DQM0 = 35, DQM1 = 26
4245 22:58:27.943113 DQ Delay:
4246 22:58:27.943221 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4247 22:58:27.946782 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4248 22:58:27.949806 DQ8 =17, DQ9 =9, DQ10 =33, DQ11 =17
4249 22:58:27.952839 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4250 22:58:27.952955
4251 22:58:27.956706
4252 22:58:27.956817 ==
4253 22:58:27.959749 Dram Type= 6, Freq= 0, CH_0, rank 1
4254 22:58:27.962769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4255 22:58:27.962905 ==
4256 22:58:27.963002
4257 22:58:27.963091
4258 22:58:27.966154 TX Vref Scan disable
4259 22:58:27.966260 == TX Byte 0 ==
4260 22:58:27.972861 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4261 22:58:27.976350 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4262 22:58:27.976474 == TX Byte 1 ==
4263 22:58:27.982948 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4264 22:58:27.985975 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4265 22:58:27.986100 ==
4266 22:58:27.989587 Dram Type= 6, Freq= 0, CH_0, rank 1
4267 22:58:27.992658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4268 22:58:27.992772 ==
4269 22:58:27.992866
4270 22:58:27.992956
4271 22:58:27.996341 TX Vref Scan disable
4272 22:58:27.999473 == TX Byte 0 ==
4273 22:58:28.002517 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4274 22:58:28.009492 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4275 22:58:28.009630 == TX Byte 1 ==
4276 22:58:28.012360 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4277 22:58:28.019092 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4278 22:58:28.019234
4279 22:58:28.019336 [DATLAT]
4280 22:58:28.019428 Freq=600, CH0 RK1
4281 22:58:28.019519
4282 22:58:28.022659 DATLAT Default: 0x9
4283 22:58:28.022768 0, 0xFFFF, sum = 0
4284 22:58:28.025490 1, 0xFFFF, sum = 0
4285 22:58:28.029129 2, 0xFFFF, sum = 0
4286 22:58:28.029248 3, 0xFFFF, sum = 0
4287 22:58:28.032056 4, 0xFFFF, sum = 0
4288 22:58:28.032168 5, 0xFFFF, sum = 0
4289 22:58:28.035740 6, 0xFFFF, sum = 0
4290 22:58:28.035853 7, 0xFFFF, sum = 0
4291 22:58:28.038982 8, 0x0, sum = 1
4292 22:58:28.039073 9, 0x0, sum = 2
4293 22:58:28.039139 10, 0x0, sum = 3
4294 22:58:28.042108 11, 0x0, sum = 4
4295 22:58:28.042193 best_step = 9
4296 22:58:28.042273
4297 22:58:28.042346 ==
4298 22:58:28.045743 Dram Type= 6, Freq= 0, CH_0, rank 1
4299 22:58:28.052545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4300 22:58:28.052654 ==
4301 22:58:28.052719 RX Vref Scan: 0
4302 22:58:28.052779
4303 22:58:28.055492 RX Vref 0 -> 0, step: 1
4304 22:58:28.055575
4305 22:58:28.058657 RX Delay -195 -> 252, step: 8
4306 22:58:28.065392 iDelay=205, Bit 0, Center 28 (-131 ~ 188) 320
4307 22:58:28.068563 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4308 22:58:28.071970 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4309 22:58:28.074906 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4310 22:58:28.078432 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4311 22:58:28.085009 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4312 22:58:28.088412 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4313 22:58:28.092071 iDelay=205, Bit 7, Center 40 (-115 ~ 196) 312
4314 22:58:28.095088 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4315 22:58:28.101419 iDelay=205, Bit 9, Center 12 (-139 ~ 164) 304
4316 22:58:28.104436 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4317 22:58:28.108309 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4318 22:58:28.111396 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4319 22:58:28.117968 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4320 22:58:28.120983 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4321 22:58:28.124478 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4322 22:58:28.124567 ==
4323 22:58:28.127924 Dram Type= 6, Freq= 0, CH_0, rank 1
4324 22:58:28.131452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4325 22:58:28.134268 ==
4326 22:58:28.134359 DQS Delay:
4327 22:58:28.134423 DQS0 = 0, DQS1 = 0
4328 22:58:28.137801 DQM Delay:
4329 22:58:28.137885 DQM0 = 32, DQM1 = 28
4330 22:58:28.140992 DQ Delay:
4331 22:58:28.144072 DQ0 =28, DQ1 =36, DQ2 =28, DQ3 =28
4332 22:58:28.144183 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =40
4333 22:58:28.147720 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4334 22:58:28.153850 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4335 22:58:28.153974
4336 22:58:28.154038
4337 22:58:28.160613 [DQSOSCAuto] RK1, (LSB)MR18= 0x6f3f, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 389 ps
4338 22:58:28.164295 CH0 RK1: MR19=808, MR18=6F3F
4339 22:58:28.170372 CH0_RK1: MR19=0x808, MR18=0x6F3F, DQSOSC=389, MR23=63, INC=173, DEC=115
4340 22:58:28.174045 [RxdqsGatingPostProcess] freq 600
4341 22:58:28.177023 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4342 22:58:28.180653 Pre-setting of DQS Precalculation
4343 22:58:28.186964 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4344 22:58:28.187085 ==
4345 22:58:28.190474 Dram Type= 6, Freq= 0, CH_1, rank 0
4346 22:58:28.193386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4347 22:58:28.193494 ==
4348 22:58:28.199862 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4349 22:58:28.206707 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4350 22:58:28.209776 [CA 0] Center 35 (5~66) winsize 62
4351 22:58:28.213511 [CA 1] Center 36 (6~66) winsize 61
4352 22:58:28.216686 [CA 2] Center 34 (4~65) winsize 62
4353 22:58:28.219845 [CA 3] Center 34 (3~65) winsize 63
4354 22:58:28.223275 [CA 4] Center 34 (4~65) winsize 62
4355 22:58:28.226656 [CA 5] Center 33 (3~64) winsize 62
4356 22:58:28.226737
4357 22:58:28.229732 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4358 22:58:28.229814
4359 22:58:28.233300 [CATrainingPosCal] consider 1 rank data
4360 22:58:28.236225 u2DelayCellTimex100 = 270/100 ps
4361 22:58:28.239637 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4362 22:58:28.243360 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4363 22:58:28.246422 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4364 22:58:28.249497 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4365 22:58:28.253237 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4366 22:58:28.256361 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4367 22:58:28.256449
4368 22:58:28.263011 CA PerBit enable=1, Macro0, CA PI delay=33
4369 22:58:28.263115
4370 22:58:28.266201 [CBTSetCACLKResult] CA Dly = 33
4371 22:58:28.266301 CS Dly: 4 (0~35)
4372 22:58:28.266366 ==
4373 22:58:28.269862 Dram Type= 6, Freq= 0, CH_1, rank 1
4374 22:58:28.272985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4375 22:58:28.273072 ==
4376 22:58:28.279247 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4377 22:58:28.285966 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4378 22:58:28.289313 [CA 0] Center 35 (5~66) winsize 62
4379 22:58:28.292408 [CA 1] Center 35 (5~66) winsize 62
4380 22:58:28.295852 [CA 2] Center 34 (4~65) winsize 62
4381 22:58:28.299363 [CA 3] Center 34 (3~65) winsize 63
4382 22:58:28.302388 [CA 4] Center 34 (4~65) winsize 62
4383 22:58:28.305823 [CA 5] Center 33 (3~64) winsize 62
4384 22:58:28.305916
4385 22:58:28.308822 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4386 22:58:28.308909
4387 22:58:28.312546 [CATrainingPosCal] consider 2 rank data
4388 22:58:28.315652 u2DelayCellTimex100 = 270/100 ps
4389 22:58:28.318956 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4390 22:58:28.322987 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4391 22:58:28.325360 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4392 22:58:28.329011 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4393 22:58:28.335599 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4394 22:58:28.339023 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4395 22:58:28.339112
4396 22:58:28.342083 CA PerBit enable=1, Macro0, CA PI delay=33
4397 22:58:28.342181
4398 22:58:28.345548 [CBTSetCACLKResult] CA Dly = 33
4399 22:58:28.345662 CS Dly: 4 (0~36)
4400 22:58:28.345777
4401 22:58:28.349064 ----->DramcWriteLeveling(PI) begin...
4402 22:58:28.349176 ==
4403 22:58:28.352011 Dram Type= 6, Freq= 0, CH_1, rank 0
4404 22:58:28.358343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4405 22:58:28.358469 ==
4406 22:58:28.361989 Write leveling (Byte 0): 32 => 32
4407 22:58:28.365082 Write leveling (Byte 1): 32 => 32
4408 22:58:28.365191 DramcWriteLeveling(PI) end<-----
4409 22:58:28.368618
4410 22:58:28.368742 ==
4411 22:58:28.371791 Dram Type= 6, Freq= 0, CH_1, rank 0
4412 22:58:28.374772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4413 22:58:28.374891 ==
4414 22:58:28.378493 [Gating] SW mode calibration
4415 22:58:28.384707 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4416 22:58:28.388488 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4417 22:58:28.394700 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4418 22:58:28.398306 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4419 22:58:28.401222 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4420 22:58:28.407742 0 9 12 | B1->B0 | 3131 3030 | 0 0 | (0 0) (0 0)
4421 22:58:28.411327 0 9 16 | B1->B0 | 2828 2626 | 1 0 | (0 0) (1 0)
4422 22:58:28.414779 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 22:58:28.421131 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 22:58:28.424809 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 22:58:28.427796 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 22:58:28.434137 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 22:58:28.437852 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4428 22:58:28.440676 0 10 12 | B1->B0 | 3030 3232 | 0 0 | (0 0) (0 0)
4429 22:58:28.447155 0 10 16 | B1->B0 | 4343 4141 | 0 0 | (0 0) (0 0)
4430 22:58:28.450724 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 22:58:28.454194 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 22:58:28.460868 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 22:58:28.463965 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 22:58:28.470617 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 22:58:28.473611 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 22:58:28.476804 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 22:58:28.483775 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4438 22:58:28.486810 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 22:58:28.490643 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 22:58:28.496882 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 22:58:28.500553 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 22:58:28.503356 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 22:58:28.506896 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 22:58:28.513442 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 22:58:28.516576 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 22:58:28.520136 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 22:58:28.526636 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 22:58:28.529869 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 22:58:28.532990 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 22:58:28.539773 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 22:58:28.542822 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 22:58:28.546446 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4453 22:58:28.553126 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4454 22:58:28.556080 Total UI for P1: 0, mck2ui 16
4455 22:58:28.559510 best dqsien dly found for B0: ( 0, 13, 12)
4456 22:58:28.562766 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 22:58:28.565808 Total UI for P1: 0, mck2ui 16
4458 22:58:28.568950 best dqsien dly found for B1: ( 0, 13, 16)
4459 22:58:28.572540 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4460 22:58:28.576099 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4461 22:58:28.576208
4462 22:58:28.582697 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4463 22:58:28.585776 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4464 22:58:28.585897 [Gating] SW calibration Done
4465 22:58:28.588868 ==
4466 22:58:28.592648 Dram Type= 6, Freq= 0, CH_1, rank 0
4467 22:58:28.595731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4468 22:58:28.595839 ==
4469 22:58:28.595935 RX Vref Scan: 0
4470 22:58:28.596023
4471 22:58:28.598991 RX Vref 0 -> 0, step: 1
4472 22:58:28.599065
4473 22:58:28.602569 RX Delay -230 -> 252, step: 16
4474 22:58:28.605450 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4475 22:58:28.608570 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4476 22:58:28.615736 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4477 22:58:28.618698 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4478 22:58:28.621837 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4479 22:58:28.625484 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4480 22:58:28.631780 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4481 22:58:28.635514 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4482 22:58:28.638657 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4483 22:58:28.642170 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4484 22:58:28.645320 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4485 22:58:28.651604 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4486 22:58:28.655299 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4487 22:58:28.658315 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4488 22:58:28.665149 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4489 22:58:28.668097 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4490 22:58:28.668198 ==
4491 22:58:28.671479 Dram Type= 6, Freq= 0, CH_1, rank 0
4492 22:58:28.674596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4493 22:58:28.674678 ==
4494 22:58:28.678353 DQS Delay:
4495 22:58:28.678461 DQS0 = 0, DQS1 = 0
4496 22:58:28.678552 DQM Delay:
4497 22:58:28.681423 DQM0 = 39, DQM1 = 29
4498 22:58:28.681529 DQ Delay:
4499 22:58:28.684525 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4500 22:58:28.687541 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4501 22:58:28.691381 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4502 22:58:28.694333 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4503 22:58:28.694444
4504 22:58:28.694555
4505 22:58:28.694648 ==
4506 22:58:28.697421 Dram Type= 6, Freq= 0, CH_1, rank 0
4507 22:58:28.704365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4508 22:58:28.704503 ==
4509 22:58:28.704583
4510 22:58:28.704648
4511 22:58:28.704707 TX Vref Scan disable
4512 22:58:28.708064 == TX Byte 0 ==
4513 22:58:28.711164 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4514 22:58:28.718146 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4515 22:58:28.718287 == TX Byte 1 ==
4516 22:58:28.721202 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4517 22:58:28.727725 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4518 22:58:28.727864 ==
4519 22:58:28.730822 Dram Type= 6, Freq= 0, CH_1, rank 0
4520 22:58:28.734074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4521 22:58:28.734207 ==
4522 22:58:28.734318
4523 22:58:28.734406
4524 22:58:28.737488 TX Vref Scan disable
4525 22:58:28.741029 == TX Byte 0 ==
4526 22:58:28.743881 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4527 22:58:28.747575 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4528 22:58:28.750890 == TX Byte 1 ==
4529 22:58:28.753790 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4530 22:58:28.757614 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4531 22:58:28.757704
4532 22:58:28.760777 [DATLAT]
4533 22:58:28.760860 Freq=600, CH1 RK0
4534 22:58:28.760926
4535 22:58:28.764290 DATLAT Default: 0x9
4536 22:58:28.764399 0, 0xFFFF, sum = 0
4537 22:58:28.767221 1, 0xFFFF, sum = 0
4538 22:58:28.767307 2, 0xFFFF, sum = 0
4539 22:58:28.770743 3, 0xFFFF, sum = 0
4540 22:58:28.770866 4, 0xFFFF, sum = 0
4541 22:58:28.774107 5, 0xFFFF, sum = 0
4542 22:58:28.774219 6, 0xFFFF, sum = 0
4543 22:58:28.777000 7, 0xFFFF, sum = 0
4544 22:58:28.777087 8, 0x0, sum = 1
4545 22:58:28.780525 9, 0x0, sum = 2
4546 22:58:28.780649 10, 0x0, sum = 3
4547 22:58:28.784089 11, 0x0, sum = 4
4548 22:58:28.784182 best_step = 9
4549 22:58:28.784249
4550 22:58:28.784311 ==
4551 22:58:28.787149 Dram Type= 6, Freq= 0, CH_1, rank 0
4552 22:58:28.790205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4553 22:58:28.790290 ==
4554 22:58:28.793990 RX Vref Scan: 1
4555 22:58:28.794075
4556 22:58:28.797095 RX Vref 0 -> 0, step: 1
4557 22:58:28.797179
4558 22:58:28.800150 RX Delay -195 -> 252, step: 8
4559 22:58:28.800234
4560 22:58:28.803803 Set Vref, RX VrefLevel [Byte0]: 51
4561 22:58:28.803915 [Byte1]: 55
4562 22:58:28.809058
4563 22:58:28.809141 Final RX Vref Byte 0 = 51 to rank0
4564 22:58:28.811807 Final RX Vref Byte 1 = 55 to rank0
4565 22:58:28.815083 Final RX Vref Byte 0 = 51 to rank1
4566 22:58:28.818061 Final RX Vref Byte 1 = 55 to rank1==
4567 22:58:28.821767 Dram Type= 6, Freq= 0, CH_1, rank 0
4568 22:58:28.828481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4569 22:58:28.828569 ==
4570 22:58:28.828635 DQS Delay:
4571 22:58:28.831431 DQS0 = 0, DQS1 = 0
4572 22:58:28.831513 DQM Delay:
4573 22:58:28.831578 DQM0 = 35, DQM1 = 28
4574 22:58:28.834910 DQ Delay:
4575 22:58:28.838507 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =36
4576 22:58:28.841605 DQ4 =32, DQ5 =44, DQ6 =44, DQ7 =32
4577 22:58:28.844643 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =24
4578 22:58:28.848152 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4579 22:58:28.848260
4580 22:58:28.848355
4581 22:58:28.854793 [DQSOSCAuto] RK0, (LSB)MR18= 0x2634, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 402 ps
4582 22:58:28.858027 CH1 RK0: MR19=808, MR18=2634
4583 22:58:28.864695 CH1_RK0: MR19=0x808, MR18=0x2634, DQSOSC=400, MR23=63, INC=163, DEC=109
4584 22:58:28.864827
4585 22:58:28.867735 ----->DramcWriteLeveling(PI) begin...
4586 22:58:28.867844 ==
4587 22:58:28.870775 Dram Type= 6, Freq= 0, CH_1, rank 1
4588 22:58:28.874460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 22:58:28.874555 ==
4590 22:58:28.877426 Write leveling (Byte 0): 28 => 28
4591 22:58:28.881044 Write leveling (Byte 1): 31 => 31
4592 22:58:28.884306 DramcWriteLeveling(PI) end<-----
4593 22:58:28.884443
4594 22:58:28.884554 ==
4595 22:58:28.887232 Dram Type= 6, Freq= 0, CH_1, rank 1
4596 22:58:28.894266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4597 22:58:28.894377 ==
4598 22:58:28.894474 [Gating] SW mode calibration
4599 22:58:28.904189 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4600 22:58:28.907392 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4601 22:58:28.910397 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4602 22:58:28.917343 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4603 22:58:28.920526 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4604 22:58:28.923565 0 9 12 | B1->B0 | 3333 2c2c | 0 0 | (1 1) (1 1)
4605 22:58:28.930237 0 9 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4606 22:58:28.933634 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 22:58:28.936585 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4608 22:58:28.943223 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 22:58:28.946978 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 22:58:28.950100 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4611 22:58:28.956495 0 10 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
4612 22:58:28.960124 0 10 12 | B1->B0 | 2d2d 3d3d | 0 1 | (1 1) (0 0)
4613 22:58:28.963208 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4614 22:58:28.969919 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 22:58:28.973065 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 22:58:28.976218 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 22:58:28.982723 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 22:58:28.986325 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 22:58:28.989385 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4620 22:58:28.996459 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4621 22:58:28.999386 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 22:58:29.005783 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 22:58:29.009456 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 22:58:29.012536 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 22:58:29.018806 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 22:58:29.022571 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 22:58:29.025592 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 22:58:29.032232 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 22:58:29.035303 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 22:58:29.039016 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 22:58:29.045315 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 22:58:29.048836 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 22:58:29.052406 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 22:58:29.058776 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 22:58:29.061766 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 22:58:29.065375 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 22:58:29.068539 Total UI for P1: 0, mck2ui 16
4638 22:58:29.071596 best dqsien dly found for B0: ( 0, 13, 10)
4639 22:58:29.075279 Total UI for P1: 0, mck2ui 16
4640 22:58:29.078746 best dqsien dly found for B1: ( 0, 13, 10)
4641 22:58:29.081812 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4642 22:58:29.084955 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4643 22:58:29.085038
4644 22:58:29.091496 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4645 22:58:29.095120 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4646 22:58:29.095192 [Gating] SW calibration Done
4647 22:58:29.098200 ==
4648 22:58:29.101602 Dram Type= 6, Freq= 0, CH_1, rank 1
4649 22:58:29.104796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4650 22:58:29.104894 ==
4651 22:58:29.104982 RX Vref Scan: 0
4652 22:58:29.105055
4653 22:58:29.108049 RX Vref 0 -> 0, step: 1
4654 22:58:29.108119
4655 22:58:29.111054 RX Delay -230 -> 252, step: 16
4656 22:58:29.114942 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4657 22:58:29.118103 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4658 22:58:29.124748 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4659 22:58:29.127833 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4660 22:58:29.130886 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4661 22:58:29.134583 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4662 22:58:29.141229 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4663 22:58:29.144268 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4664 22:58:29.147743 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4665 22:58:29.150664 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4666 22:58:29.157419 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4667 22:58:29.160581 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4668 22:58:29.164011 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4669 22:58:29.167798 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4670 22:58:29.173986 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4671 22:58:29.177005 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4672 22:58:29.177113 ==
4673 22:58:29.179998 Dram Type= 6, Freq= 0, CH_1, rank 1
4674 22:58:29.183640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4675 22:58:29.183723 ==
4676 22:58:29.186728 DQS Delay:
4677 22:58:29.186860 DQS0 = 0, DQS1 = 0
4678 22:58:29.186943 DQM Delay:
4679 22:58:29.190409 DQM0 = 35, DQM1 = 30
4680 22:58:29.190519 DQ Delay:
4681 22:58:29.193320 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4682 22:58:29.197007 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4683 22:58:29.200079 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4684 22:58:29.203333 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =41
4685 22:58:29.203417
4686 22:58:29.203482
4687 22:58:29.203540 ==
4688 22:58:29.206801 Dram Type= 6, Freq= 0, CH_1, rank 1
4689 22:58:29.213045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4690 22:58:29.213131 ==
4691 22:58:29.213198
4692 22:58:29.213260
4693 22:58:29.213319 TX Vref Scan disable
4694 22:58:29.216761 == TX Byte 0 ==
4695 22:58:29.220251 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4696 22:58:29.227196 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4697 22:58:29.227283 == TX Byte 1 ==
4698 22:58:29.230320 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4699 22:58:29.237008 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4700 22:58:29.237093 ==
4701 22:58:29.240074 Dram Type= 6, Freq= 0, CH_1, rank 1
4702 22:58:29.243090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4703 22:58:29.243175 ==
4704 22:58:29.243240
4705 22:58:29.243301
4706 22:58:29.246329 TX Vref Scan disable
4707 22:58:29.249891 == TX Byte 0 ==
4708 22:58:29.252894 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4709 22:58:29.256598 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4710 22:58:29.259773 == TX Byte 1 ==
4711 22:58:29.262756 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4712 22:58:29.266394 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4713 22:58:29.266477
4714 22:58:29.269328 [DATLAT]
4715 22:58:29.269406 Freq=600, CH1 RK1
4716 22:58:29.269471
4717 22:58:29.272914 DATLAT Default: 0x9
4718 22:58:29.272997 0, 0xFFFF, sum = 0
4719 22:58:29.275821 1, 0xFFFF, sum = 0
4720 22:58:29.275946 2, 0xFFFF, sum = 0
4721 22:58:29.279399 3, 0xFFFF, sum = 0
4722 22:58:29.279483 4, 0xFFFF, sum = 0
4723 22:58:29.282467 5, 0xFFFF, sum = 0
4724 22:58:29.282588 6, 0xFFFF, sum = 0
4725 22:58:29.286138 7, 0xFFFF, sum = 0
4726 22:58:29.286287 8, 0x0, sum = 1
4727 22:58:29.289129 9, 0x0, sum = 2
4728 22:58:29.289228 10, 0x0, sum = 3
4729 22:58:29.292838 11, 0x0, sum = 4
4730 22:58:29.292935 best_step = 9
4731 22:58:29.293036
4732 22:58:29.293098 ==
4733 22:58:29.295885 Dram Type= 6, Freq= 0, CH_1, rank 1
4734 22:58:29.299527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4735 22:58:29.302791 ==
4736 22:58:29.302906 RX Vref Scan: 0
4737 22:58:29.302976
4738 22:58:29.305578 RX Vref 0 -> 0, step: 1
4739 22:58:29.305658
4740 22:58:29.309197 RX Delay -195 -> 252, step: 8
4741 22:58:29.312256 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4742 22:58:29.319277 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4743 22:58:29.322236 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4744 22:58:29.325575 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4745 22:58:29.328567 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4746 22:58:29.332289 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4747 22:58:29.338483 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4748 22:58:29.341653 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4749 22:58:29.345216 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4750 22:58:29.348266 iDelay=205, Bit 9, Center 16 (-147 ~ 180) 328
4751 22:58:29.354956 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4752 22:58:29.358358 iDelay=205, Bit 11, Center 24 (-139 ~ 188) 328
4753 22:58:29.361478 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4754 22:58:29.364609 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4755 22:58:29.371262 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4756 22:58:29.374925 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4757 22:58:29.375002 ==
4758 22:58:29.377855 Dram Type= 6, Freq= 0, CH_1, rank 1
4759 22:58:29.381400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4760 22:58:29.381476 ==
4761 22:58:29.384464 DQS Delay:
4762 22:58:29.384606 DQS0 = 0, DQS1 = 0
4763 22:58:29.384749 DQM Delay:
4764 22:58:29.387920 DQM0 = 35, DQM1 = 29
4765 22:58:29.387992 DQ Delay:
4766 22:58:29.390972 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4767 22:58:29.394687 DQ4 =32, DQ5 =48, DQ6 =44, DQ7 =32
4768 22:58:29.397795 DQ8 =16, DQ9 =16, DQ10 =32, DQ11 =24
4769 22:58:29.401281 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4770 22:58:29.401384
4771 22:58:29.401473
4772 22:58:29.410899 [DQSOSCAuto] RK1, (LSB)MR18= 0x3555, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4773 22:58:29.414201 CH1 RK1: MR19=808, MR18=3555
4774 22:58:29.420891 CH1_RK1: MR19=0x808, MR18=0x3555, DQSOSC=393, MR23=63, INC=169, DEC=113
4775 22:58:29.420973 [RxdqsGatingPostProcess] freq 600
4776 22:58:29.428061 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4777 22:58:29.430414 Pre-setting of DQS Precalculation
4778 22:58:29.433949 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4779 22:58:29.443699 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4780 22:58:29.450471 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4781 22:58:29.450553
4782 22:58:29.450616
4783 22:58:29.453505 [Calibration Summary] 1200 Mbps
4784 22:58:29.453571 CH 0, Rank 0
4785 22:58:29.457090 SW Impedance : PASS
4786 22:58:29.460555 DUTY Scan : NO K
4787 22:58:29.460629 ZQ Calibration : PASS
4788 22:58:29.463721 Jitter Meter : NO K
4789 22:58:29.463788 CBT Training : PASS
4790 22:58:29.467110 Write leveling : PASS
4791 22:58:29.469983 RX DQS gating : PASS
4792 22:58:29.470052 RX DQ/DQS(RDDQC) : PASS
4793 22:58:29.473663 TX DQ/DQS : PASS
4794 22:58:29.476919 RX DATLAT : PASS
4795 22:58:29.477024 RX DQ/DQS(Engine): PASS
4796 22:58:29.480470 TX OE : NO K
4797 22:58:29.480551 All Pass.
4798 22:58:29.480638
4799 22:58:29.483433 CH 0, Rank 1
4800 22:58:29.483542 SW Impedance : PASS
4801 22:58:29.487125 DUTY Scan : NO K
4802 22:58:29.490053 ZQ Calibration : PASS
4803 22:58:29.490127 Jitter Meter : NO K
4804 22:58:29.493534 CBT Training : PASS
4805 22:58:29.496627 Write leveling : PASS
4806 22:58:29.496729 RX DQS gating : PASS
4807 22:58:29.499717 RX DQ/DQS(RDDQC) : PASS
4808 22:58:29.503259 TX DQ/DQS : PASS
4809 22:58:29.503345 RX DATLAT : PASS
4810 22:58:29.506722 RX DQ/DQS(Engine): PASS
4811 22:58:29.509859 TX OE : NO K
4812 22:58:29.509948 All Pass.
4813 22:58:29.510039
4814 22:58:29.510111 CH 1, Rank 0
4815 22:58:29.513024 SW Impedance : PASS
4816 22:58:29.516187 DUTY Scan : NO K
4817 22:58:29.516281 ZQ Calibration : PASS
4818 22:58:29.519964 Jitter Meter : NO K
4819 22:58:29.522766 CBT Training : PASS
4820 22:58:29.522887 Write leveling : PASS
4821 22:58:29.525996 RX DQS gating : PASS
4822 22:58:29.529520 RX DQ/DQS(RDDQC) : PASS
4823 22:58:29.529590 TX DQ/DQS : PASS
4824 22:58:29.532677 RX DATLAT : PASS
4825 22:58:29.536253 RX DQ/DQS(Engine): PASS
4826 22:58:29.536359 TX OE : NO K
4827 22:58:29.536451 All Pass.
4828 22:58:29.539554
4829 22:58:29.539624 CH 1, Rank 1
4830 22:58:29.542716 SW Impedance : PASS
4831 22:58:29.542812 DUTY Scan : NO K
4832 22:58:29.546204 ZQ Calibration : PASS
4833 22:58:29.546285 Jitter Meter : NO K
4834 22:58:29.549456 CBT Training : PASS
4835 22:58:29.552585 Write leveling : PASS
4836 22:58:29.552680 RX DQS gating : PASS
4837 22:58:29.556097 RX DQ/DQS(RDDQC) : PASS
4838 22:58:29.558993 TX DQ/DQS : PASS
4839 22:58:29.559111 RX DATLAT : PASS
4840 22:58:29.562655 RX DQ/DQS(Engine): PASS
4841 22:58:29.565484 TX OE : NO K
4842 22:58:29.565603 All Pass.
4843 22:58:29.565748
4844 22:58:29.569083 DramC Write-DBI off
4845 22:58:29.569236 PER_BANK_REFRESH: Hybrid Mode
4846 22:58:29.572311 TX_TRACKING: ON
4847 22:58:29.582086 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4848 22:58:29.585286 [FAST_K] Save calibration result to emmc
4849 22:58:29.588916 dramc_set_vcore_voltage set vcore to 662500
4850 22:58:29.589043 Read voltage for 933, 3
4851 22:58:29.592443 Vio18 = 0
4852 22:58:29.592524 Vcore = 662500
4853 22:58:29.592589 Vdram = 0
4854 22:58:29.595473 Vddq = 0
4855 22:58:29.595555 Vmddr = 0
4856 22:58:29.602604 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4857 22:58:29.605451 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4858 22:58:29.608434 MEM_TYPE=3, freq_sel=17
4859 22:58:29.612088 sv_algorithm_assistance_LP4_1600
4860 22:58:29.615177 ============ PULL DRAM RESETB DOWN ============
4861 22:58:29.618458 ========== PULL DRAM RESETB DOWN end =========
4862 22:58:29.625128 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4863 22:58:29.628122 ===================================
4864 22:58:29.628205 LPDDR4 DRAM CONFIGURATION
4865 22:58:29.631892 ===================================
4866 22:58:29.635017 EX_ROW_EN[0] = 0x0
4867 22:58:29.638025 EX_ROW_EN[1] = 0x0
4868 22:58:29.638107 LP4Y_EN = 0x0
4869 22:58:29.641613 WORK_FSP = 0x0
4870 22:58:29.641694 WL = 0x3
4871 22:58:29.645549 RL = 0x3
4872 22:58:29.645631 BL = 0x2
4873 22:58:29.648241 RPST = 0x0
4874 22:58:29.648322 RD_PRE = 0x0
4875 22:58:29.651293 WR_PRE = 0x1
4876 22:58:29.651404 WR_PST = 0x0
4877 22:58:29.655034 DBI_WR = 0x0
4878 22:58:29.655115 DBI_RD = 0x0
4879 22:58:29.658116 OTF = 0x1
4880 22:58:29.661177 ===================================
4881 22:58:29.664916 ===================================
4882 22:58:29.665000 ANA top config
4883 22:58:29.667948 ===================================
4884 22:58:29.670881 DLL_ASYNC_EN = 0
4885 22:58:29.674488 ALL_SLAVE_EN = 1
4886 22:58:29.678070 NEW_RANK_MODE = 1
4887 22:58:29.678155 DLL_IDLE_MODE = 1
4888 22:58:29.681192 LP45_APHY_COMB_EN = 1
4889 22:58:29.684261 TX_ODT_DIS = 1
4890 22:58:29.688127 NEW_8X_MODE = 1
4891 22:58:29.691066 ===================================
4892 22:58:29.694113 ===================================
4893 22:58:29.697624 data_rate = 1866
4894 22:58:29.697707 CKR = 1
4895 22:58:29.701034 DQ_P2S_RATIO = 8
4896 22:58:29.704524 ===================================
4897 22:58:29.707456 CA_P2S_RATIO = 8
4898 22:58:29.710925 DQ_CA_OPEN = 0
4899 22:58:29.714478 DQ_SEMI_OPEN = 0
4900 22:58:29.717381 CA_SEMI_OPEN = 0
4901 22:58:29.717486 CA_FULL_RATE = 0
4902 22:58:29.720838 DQ_CKDIV4_EN = 1
4903 22:58:29.723849 CA_CKDIV4_EN = 1
4904 22:58:29.727540 CA_PREDIV_EN = 0
4905 22:58:29.730508 PH8_DLY = 0
4906 22:58:29.734133 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4907 22:58:29.737193 DQ_AAMCK_DIV = 4
4908 22:58:29.737297 CA_AAMCK_DIV = 4
4909 22:58:29.740342 CA_ADMCK_DIV = 4
4910 22:58:29.743354 DQ_TRACK_CA_EN = 0
4911 22:58:29.746916 CA_PICK = 933
4912 22:58:29.750088 CA_MCKIO = 933
4913 22:58:29.753661 MCKIO_SEMI = 0
4914 22:58:29.757124 PLL_FREQ = 3732
4915 22:58:29.757208 DQ_UI_PI_RATIO = 32
4916 22:58:29.760206 CA_UI_PI_RATIO = 0
4917 22:58:29.763285 ===================================
4918 22:58:29.766993 ===================================
4919 22:58:29.770089 memory_type:LPDDR4
4920 22:58:29.773139 GP_NUM : 10
4921 22:58:29.773226 SRAM_EN : 1
4922 22:58:29.776703 MD32_EN : 0
4923 22:58:29.779792 ===================================
4924 22:58:29.783481 [ANA_INIT] >>>>>>>>>>>>>>
4925 22:58:29.783616 <<<<<< [CONFIGURE PHASE]: ANA_TX
4926 22:58:29.789568 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4927 22:58:29.793351 ===================================
4928 22:58:29.793472 data_rate = 1866,PCW = 0X8f00
4929 22:58:29.796547 ===================================
4930 22:58:29.799708 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4931 22:58:29.806359 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4932 22:58:29.812915 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4933 22:58:29.816224 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4934 22:58:29.820097 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4935 22:58:29.822687 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4936 22:58:29.826037 [ANA_INIT] flow start
4937 22:58:29.828993 [ANA_INIT] PLL >>>>>>>>
4938 22:58:29.829094 [ANA_INIT] PLL <<<<<<<<
4939 22:58:29.832525 [ANA_INIT] MIDPI >>>>>>>>
4940 22:58:29.836050 [ANA_INIT] MIDPI <<<<<<<<
4941 22:58:29.836156 [ANA_INIT] DLL >>>>>>>>
4942 22:58:29.839084 [ANA_INIT] flow end
4943 22:58:29.842111 ============ LP4 DIFF to SE enter ============
4944 22:58:29.845934 ============ LP4 DIFF to SE exit ============
4945 22:58:29.849030 [ANA_INIT] <<<<<<<<<<<<<
4946 22:58:29.852658 [Flow] Enable top DCM control >>>>>
4947 22:58:29.855770 [Flow] Enable top DCM control <<<<<
4948 22:58:29.858799 Enable DLL master slave shuffle
4949 22:58:29.865820 ==============================================================
4950 22:58:29.865925 Gating Mode config
4951 22:58:29.872131 ==============================================================
4952 22:58:29.872215 Config description:
4953 22:58:29.881899 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4954 22:58:29.888856 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4955 22:58:29.895064 SELPH_MODE 0: By rank 1: By Phase
4956 22:58:29.901937 ==============================================================
4957 22:58:29.902023 GAT_TRACK_EN = 1
4958 22:58:29.905029 RX_GATING_MODE = 2
4959 22:58:29.908550 RX_GATING_TRACK_MODE = 2
4960 22:58:29.911711 SELPH_MODE = 1
4961 22:58:29.915320 PICG_EARLY_EN = 1
4962 22:58:29.918280 VALID_LAT_VALUE = 1
4963 22:58:29.924822 ==============================================================
4964 22:58:29.927953 Enter into Gating configuration >>>>
4965 22:58:29.931134 Exit from Gating configuration <<<<
4966 22:58:29.934746 Enter into DVFS_PRE_config >>>>>
4967 22:58:29.944779 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4968 22:58:29.947917 Exit from DVFS_PRE_config <<<<<
4969 22:58:29.951012 Enter into PICG configuration >>>>
4970 22:58:29.954680 Exit from PICG configuration <<<<
4971 22:58:29.957645 [RX_INPUT] configuration >>>>>
4972 22:58:29.961522 [RX_INPUT] configuration <<<<<
4973 22:58:29.964370 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4974 22:58:29.970799 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4975 22:58:29.977497 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4976 22:58:29.984004 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4977 22:58:29.987063 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4978 22:58:29.993743 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4979 22:58:30.000633 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4980 22:58:30.004002 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4981 22:58:30.007159 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4982 22:58:30.010204 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4983 22:58:30.016942 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4984 22:58:30.020113 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4985 22:58:30.023378 ===================================
4986 22:58:30.026459 LPDDR4 DRAM CONFIGURATION
4987 22:58:30.030260 ===================================
4988 22:58:30.030366 EX_ROW_EN[0] = 0x0
4989 22:58:30.033190 EX_ROW_EN[1] = 0x0
4990 22:58:30.033263 LP4Y_EN = 0x0
4991 22:58:30.036833 WORK_FSP = 0x0
4992 22:58:30.036915 WL = 0x3
4993 22:58:30.039965 RL = 0x3
4994 22:58:30.040047 BL = 0x2
4995 22:58:30.043238 RPST = 0x0
4996 22:58:30.046611 RD_PRE = 0x0
4997 22:58:30.046754 WR_PRE = 0x1
4998 22:58:30.049546 WR_PST = 0x0
4999 22:58:30.049670 DBI_WR = 0x0
5000 22:58:30.053347 DBI_RD = 0x0
5001 22:58:30.053457 OTF = 0x1
5002 22:58:30.056332 ===================================
5003 22:58:30.059975 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5004 22:58:30.066600 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5005 22:58:30.069670 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5006 22:58:30.072792 ===================================
5007 22:58:30.076510 LPDDR4 DRAM CONFIGURATION
5008 22:58:30.079341 ===================================
5009 22:58:30.079449 EX_ROW_EN[0] = 0x10
5010 22:58:30.082746 EX_ROW_EN[1] = 0x0
5011 22:58:30.082880 LP4Y_EN = 0x0
5012 22:58:30.085836 WORK_FSP = 0x0
5013 22:58:30.085940 WL = 0x3
5014 22:58:30.089303 RL = 0x3
5015 22:58:30.089389 BL = 0x2
5016 22:58:30.092896 RPST = 0x0
5017 22:58:30.096087 RD_PRE = 0x0
5018 22:58:30.096196 WR_PRE = 0x1
5019 22:58:30.099257 WR_PST = 0x0
5020 22:58:30.099365 DBI_WR = 0x0
5021 22:58:30.102360 DBI_RD = 0x0
5022 22:58:30.102466 OTF = 0x1
5023 22:58:30.106072 ===================================
5024 22:58:30.112366 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5025 22:58:30.116064 nWR fixed to 30
5026 22:58:30.119739 [ModeRegInit_LP4] CH0 RK0
5027 22:58:30.119875 [ModeRegInit_LP4] CH0 RK1
5028 22:58:30.122853 [ModeRegInit_LP4] CH1 RK0
5029 22:58:30.126588 [ModeRegInit_LP4] CH1 RK1
5030 22:58:30.126698 match AC timing 9
5031 22:58:30.133170 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5032 22:58:30.136147 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5033 22:58:30.139367 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5034 22:58:30.145770 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5035 22:58:30.149180 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5036 22:58:30.149301 ==
5037 22:58:30.152570 Dram Type= 6, Freq= 0, CH_0, rank 0
5038 22:58:30.156038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5039 22:58:30.156158 ==
5040 22:58:30.162189 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5041 22:58:30.168969 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5042 22:58:30.172123 [CA 0] Center 38 (8~69) winsize 62
5043 22:58:30.175270 [CA 1] Center 38 (8~69) winsize 62
5044 22:58:30.178956 [CA 2] Center 35 (5~65) winsize 61
5045 22:58:30.182043 [CA 3] Center 34 (4~65) winsize 62
5046 22:58:30.185529 [CA 4] Center 34 (4~65) winsize 62
5047 22:58:30.188547 [CA 5] Center 33 (3~64) winsize 62
5048 22:58:30.188662
5049 22:58:30.192233 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5050 22:58:30.192341
5051 22:58:30.195143 [CATrainingPosCal] consider 1 rank data
5052 22:58:30.198562 u2DelayCellTimex100 = 270/100 ps
5053 22:58:30.202245 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5054 22:58:30.205340 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5055 22:58:30.208446 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5056 22:58:30.215216 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5057 22:58:30.218317 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5058 22:58:30.222019 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5059 22:58:30.222144
5060 22:58:30.225100 CA PerBit enable=1, Macro0, CA PI delay=33
5061 22:58:30.225214
5062 22:58:30.228211 [CBTSetCACLKResult] CA Dly = 33
5063 22:58:30.228307 CS Dly: 7 (0~38)
5064 22:58:30.228396 ==
5065 22:58:30.231929 Dram Type= 6, Freq= 0, CH_0, rank 1
5066 22:58:30.238354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5067 22:58:30.238496 ==
5068 22:58:30.241393 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5069 22:58:30.247932 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5070 22:58:30.251744 [CA 0] Center 38 (8~69) winsize 62
5071 22:58:30.254438 [CA 1] Center 38 (8~69) winsize 62
5072 22:58:30.258026 [CA 2] Center 35 (5~66) winsize 62
5073 22:58:30.261012 [CA 3] Center 35 (4~66) winsize 63
5074 22:58:30.264742 [CA 4] Center 34 (3~65) winsize 63
5075 22:58:30.267789 [CA 5] Center 33 (3~64) winsize 62
5076 22:58:30.267873
5077 22:58:30.270890 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5078 22:58:30.270969
5079 22:58:30.274724 [CATrainingPosCal] consider 2 rank data
5080 22:58:30.277753 u2DelayCellTimex100 = 270/100 ps
5081 22:58:30.280914 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5082 22:58:30.287612 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5083 22:58:30.291275 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5084 22:58:30.294173 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5085 22:58:30.297249 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5086 22:58:30.300768 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5087 22:58:30.300854
5088 22:58:30.303865 CA PerBit enable=1, Macro0, CA PI delay=33
5089 22:58:30.303946
5090 22:58:30.307596 [CBTSetCACLKResult] CA Dly = 33
5091 22:58:30.310633 CS Dly: 7 (0~39)
5092 22:58:30.310723
5093 22:58:30.313691 ----->DramcWriteLeveling(PI) begin...
5094 22:58:30.313772 ==
5095 22:58:30.317387 Dram Type= 6, Freq= 0, CH_0, rank 0
5096 22:58:30.320552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5097 22:58:30.320633 ==
5098 22:58:30.323637 Write leveling (Byte 0): 32 => 32
5099 22:58:30.327223 Write leveling (Byte 1): 32 => 32
5100 22:58:30.330341 DramcWriteLeveling(PI) end<-----
5101 22:58:30.330428
5102 22:58:30.330513 ==
5103 22:58:30.333494 Dram Type= 6, Freq= 0, CH_0, rank 0
5104 22:58:30.337173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5105 22:58:30.337260 ==
5106 22:58:30.340297 [Gating] SW mode calibration
5107 22:58:30.346938 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5108 22:58:30.353411 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5109 22:58:30.357144 0 14 0 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
5110 22:58:30.359951 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5111 22:58:30.366413 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 22:58:30.370111 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 22:58:30.373042 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5114 22:58:30.379864 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5115 22:58:30.383012 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5116 22:58:30.386622 0 14 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5117 22:58:30.393415 0 15 0 | B1->B0 | 3333 2d2d | 1 0 | (1 0) (0 0)
5118 22:58:30.396443 0 15 4 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
5119 22:58:30.399479 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 22:58:30.406216 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 22:58:30.409931 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5122 22:58:30.412771 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5123 22:58:30.419614 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5124 22:58:30.422648 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5125 22:58:30.426434 1 0 0 | B1->B0 | 2525 3d3d | 0 0 | (0 0) (0 0)
5126 22:58:30.432671 1 0 4 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5127 22:58:30.435717 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 22:58:30.439455 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 22:58:30.446245 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 22:58:30.449263 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 22:58:30.452448 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 22:58:30.459391 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5133 22:58:30.462459 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5134 22:58:30.466120 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5135 22:58:30.472728 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 22:58:30.476067 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 22:58:30.478956 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 22:58:30.485796 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 22:58:30.488768 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 22:58:30.492008 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 22:58:30.498713 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 22:58:30.502372 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 22:58:30.505489 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 22:58:30.512191 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 22:58:30.515640 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 22:58:30.518399 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 22:58:30.525290 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 22:58:30.528408 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5149 22:58:30.532185 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5150 22:58:30.538200 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 22:58:30.541995 Total UI for P1: 0, mck2ui 16
5152 22:58:30.545052 best dqsien dly found for B0: ( 1, 2, 30)
5153 22:58:30.548134 Total UI for P1: 0, mck2ui 16
5154 22:58:30.551744 best dqsien dly found for B1: ( 1, 3, 2)
5155 22:58:30.554930 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5156 22:58:30.558018 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5157 22:58:30.558115
5158 22:58:30.561462 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5159 22:58:30.564391 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5160 22:58:30.568063 [Gating] SW calibration Done
5161 22:58:30.568169 ==
5162 22:58:30.571079 Dram Type= 6, Freq= 0, CH_0, rank 0
5163 22:58:30.574141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5164 22:58:30.574224 ==
5165 22:58:30.577753 RX Vref Scan: 0
5166 22:58:30.577858
5167 22:58:30.581179 RX Vref 0 -> 0, step: 1
5168 22:58:30.581261
5169 22:58:30.581326 RX Delay -80 -> 252, step: 8
5170 22:58:30.587517 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5171 22:58:30.590607 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5172 22:58:30.594364 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5173 22:58:30.597439 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5174 22:58:30.600607 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5175 22:58:30.607289 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5176 22:58:30.610310 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5177 22:58:30.613880 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5178 22:58:30.616958 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5179 22:58:30.620011 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5180 22:58:30.626965 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5181 22:58:30.630036 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5182 22:58:30.633189 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5183 22:58:30.636845 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5184 22:58:30.643060 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5185 22:58:30.646261 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5186 22:58:30.646353 ==
5187 22:58:30.650038 Dram Type= 6, Freq= 0, CH_0, rank 0
5188 22:58:30.653146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5189 22:58:30.653264 ==
5190 22:58:30.653359 DQS Delay:
5191 22:58:30.656223 DQS0 = 0, DQS1 = 0
5192 22:58:30.656306 DQM Delay:
5193 22:58:30.659314 DQM0 = 94, DQM1 = 83
5194 22:58:30.659391 DQ Delay:
5195 22:58:30.662971 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5196 22:58:30.665915 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5197 22:58:30.669437 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =79
5198 22:58:30.672927 DQ12 =91, DQ13 =87, DQ14 =91, DQ15 =91
5199 22:58:30.673035
5200 22:58:30.673133
5201 22:58:30.673230 ==
5202 22:58:30.675843 Dram Type= 6, Freq= 0, CH_0, rank 0
5203 22:58:30.682483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5204 22:58:30.682616 ==
5205 22:58:30.682713
5206 22:58:30.682809
5207 22:58:30.682893 TX Vref Scan disable
5208 22:58:30.686128 == TX Byte 0 ==
5209 22:58:30.689031 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5210 22:58:30.695986 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5211 22:58:30.696136 == TX Byte 1 ==
5212 22:58:30.699028 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5213 22:58:30.705782 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5214 22:58:30.705927 ==
5215 22:58:30.708800 Dram Type= 6, Freq= 0, CH_0, rank 0
5216 22:58:30.712023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5217 22:58:30.712136 ==
5218 22:58:30.712231
5219 22:58:30.712326
5220 22:58:30.715739 TX Vref Scan disable
5221 22:58:30.715840 == TX Byte 0 ==
5222 22:58:30.721983 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5223 22:58:30.725651 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5224 22:58:30.728561 == TX Byte 1 ==
5225 22:58:30.732201 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5226 22:58:30.735572 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5227 22:58:30.735695
5228 22:58:30.735801 [DATLAT]
5229 22:58:30.738603 Freq=933, CH0 RK0
5230 22:58:30.738720
5231 22:58:30.738819 DATLAT Default: 0xd
5232 22:58:30.742427 0, 0xFFFF, sum = 0
5233 22:58:30.745420 1, 0xFFFF, sum = 0
5234 22:58:30.745533 2, 0xFFFF, sum = 0
5235 22:58:30.748426 3, 0xFFFF, sum = 0
5236 22:58:30.748556 4, 0xFFFF, sum = 0
5237 22:58:30.752189 5, 0xFFFF, sum = 0
5238 22:58:30.752297 6, 0xFFFF, sum = 0
5239 22:58:30.755380 7, 0xFFFF, sum = 0
5240 22:58:30.755489 8, 0xFFFF, sum = 0
5241 22:58:30.758618 9, 0xFFFF, sum = 0
5242 22:58:30.758738 10, 0x0, sum = 1
5243 22:58:30.761607 11, 0x0, sum = 2
5244 22:58:30.761707 12, 0x0, sum = 3
5245 22:58:30.765282 13, 0x0, sum = 4
5246 22:58:30.765384 best_step = 11
5247 22:58:30.765473
5248 22:58:30.765565 ==
5249 22:58:30.768435 Dram Type= 6, Freq= 0, CH_0, rank 0
5250 22:58:30.771644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5251 22:58:30.771746 ==
5252 22:58:30.775254 RX Vref Scan: 1
5253 22:58:30.775331
5254 22:58:30.778230 RX Vref 0 -> 0, step: 1
5255 22:58:30.778300
5256 22:58:30.778389 RX Delay -77 -> 252, step: 4
5257 22:58:30.781595
5258 22:58:30.781690 Set Vref, RX VrefLevel [Byte0]: 60
5259 22:58:30.785089 [Byte1]: 47
5260 22:58:30.790134
5261 22:58:30.790221 Final RX Vref Byte 0 = 60 to rank0
5262 22:58:30.793252 Final RX Vref Byte 1 = 47 to rank0
5263 22:58:30.796783 Final RX Vref Byte 0 = 60 to rank1
5264 22:58:30.799638 Final RX Vref Byte 1 = 47 to rank1==
5265 22:58:30.802960 Dram Type= 6, Freq= 0, CH_0, rank 0
5266 22:58:30.809685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 22:58:30.809805 ==
5268 22:58:30.809901 DQS Delay:
5269 22:58:30.809986 DQS0 = 0, DQS1 = 0
5270 22:58:30.813230 DQM Delay:
5271 22:58:30.813332 DQM0 = 95, DQM1 = 82
5272 22:58:30.816327 DQ Delay:
5273 22:58:30.820066 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =94
5274 22:58:30.823245 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =106
5275 22:58:30.826142 DQ8 =74, DQ9 =70, DQ10 =82, DQ11 =78
5276 22:58:30.829833 DQ12 =86, DQ13 =86, DQ14 =94, DQ15 =88
5277 22:58:30.829908
5278 22:58:30.829978
5279 22:58:30.836433 [DQSOSCAuto] RK0, (LSB)MR18= 0x1212, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 416 ps
5280 22:58:30.839520 CH0 RK0: MR19=505, MR18=1212
5281 22:58:30.846054 CH0_RK0: MR19=0x505, MR18=0x1212, DQSOSC=416, MR23=63, INC=62, DEC=41
5282 22:58:30.846178
5283 22:58:30.849708 ----->DramcWriteLeveling(PI) begin...
5284 22:58:30.849827 ==
5285 22:58:30.852752 Dram Type= 6, Freq= 0, CH_0, rank 1
5286 22:58:30.855876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 22:58:30.855988 ==
5288 22:58:30.859486 Write leveling (Byte 0): 31 => 31
5289 22:58:30.862743 Write leveling (Byte 1): 30 => 30
5290 22:58:30.865875 DramcWriteLeveling(PI) end<-----
5291 22:58:30.865949
5292 22:58:30.866011 ==
5293 22:58:30.869051 Dram Type= 6, Freq= 0, CH_0, rank 1
5294 22:58:30.872634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5295 22:58:30.875684 ==
5296 22:58:30.875788 [Gating] SW mode calibration
5297 22:58:30.885859 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5298 22:58:30.889070 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5299 22:58:30.892049 0 14 0 | B1->B0 | 2727 3434 | 1 1 | (1 1) (1 1)
5300 22:58:30.898698 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 22:58:30.901952 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 22:58:30.905593 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5303 22:58:30.912015 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5304 22:58:30.915518 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5305 22:58:30.918581 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5306 22:58:30.925133 0 14 28 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 0)
5307 22:58:30.928250 0 15 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
5308 22:58:30.931987 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 22:58:30.938759 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 22:58:30.941796 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5311 22:58:30.944867 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5312 22:58:30.951519 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5313 22:58:30.955049 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5314 22:58:30.958026 0 15 28 | B1->B0 | 2626 3535 | 0 0 | (0 0) (0 0)
5315 22:58:30.964902 1 0 0 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
5316 22:58:30.968096 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 22:58:30.971137 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 22:58:30.977930 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 22:58:30.981055 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 22:58:30.984565 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5321 22:58:30.991332 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 22:58:30.994521 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5323 22:58:30.997576 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5324 22:58:31.004505 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 22:58:31.007573 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 22:58:31.011054 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 22:58:31.017652 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 22:58:31.020971 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 22:58:31.024119 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 22:58:31.030752 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 22:58:31.034029 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 22:58:31.037154 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 22:58:31.043949 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 22:58:31.047099 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 22:58:31.050198 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 22:58:31.056833 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 22:58:31.060441 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 22:58:31.063485 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5339 22:58:31.070216 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 22:58:31.073312 Total UI for P1: 0, mck2ui 16
5341 22:58:31.076465 best dqsien dly found for B0: ( 1, 2, 28)
5342 22:58:31.080064 Total UI for P1: 0, mck2ui 16
5343 22:58:31.083170 best dqsien dly found for B1: ( 1, 2, 30)
5344 22:58:31.086758 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5345 22:58:31.089729 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5346 22:58:31.089810
5347 22:58:31.093444 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5348 22:58:31.096697 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5349 22:58:31.099898 [Gating] SW calibration Done
5350 22:58:31.099981 ==
5351 22:58:31.102982 Dram Type= 6, Freq= 0, CH_0, rank 1
5352 22:58:31.106032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5353 22:58:31.106186 ==
5354 22:58:31.109701 RX Vref Scan: 0
5355 22:58:31.109812
5356 22:58:31.112497 RX Vref 0 -> 0, step: 1
5357 22:58:31.112601
5358 22:58:31.112698 RX Delay -80 -> 252, step: 8
5359 22:58:31.119400 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5360 22:58:31.122744 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5361 22:58:31.126545 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5362 22:58:31.129415 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5363 22:58:31.133040 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5364 22:58:31.139312 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5365 22:58:31.142952 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5366 22:58:31.145866 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5367 22:58:31.149490 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5368 22:58:31.152536 iDelay=208, Bit 9, Center 67 (-24 ~ 159) 184
5369 22:58:31.159396 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5370 22:58:31.162430 iDelay=208, Bit 11, Center 71 (-24 ~ 167) 192
5371 22:58:31.165894 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5372 22:58:31.169004 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5373 22:58:31.172419 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5374 22:58:31.178679 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5375 22:58:31.178761 ==
5376 22:58:31.182383 Dram Type= 6, Freq= 0, CH_0, rank 1
5377 22:58:31.185423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5378 22:58:31.185504 ==
5379 22:58:31.185568 DQS Delay:
5380 22:58:31.189130 DQS0 = 0, DQS1 = 0
5381 22:58:31.189211 DQM Delay:
5382 22:58:31.192027 DQM0 = 92, DQM1 = 81
5383 22:58:31.192108 DQ Delay:
5384 22:58:31.195622 DQ0 =91, DQ1 =91, DQ2 =91, DQ3 =91
5385 22:58:31.198759 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =103
5386 22:58:31.201844 DQ8 =71, DQ9 =67, DQ10 =83, DQ11 =71
5387 22:58:31.205431 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =87
5388 22:58:31.205513
5389 22:58:31.205577
5390 22:58:31.205637 ==
5391 22:58:31.208537 Dram Type= 6, Freq= 0, CH_0, rank 1
5392 22:58:31.211868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5393 22:58:31.211949 ==
5394 22:58:31.215476
5395 22:58:31.215556
5396 22:58:31.215620 TX Vref Scan disable
5397 22:58:31.218583 == TX Byte 0 ==
5398 22:58:31.222175 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5399 22:58:31.225527 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5400 22:58:31.228413 == TX Byte 1 ==
5401 22:58:31.231995 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5402 22:58:31.234947 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5403 22:58:31.238568 ==
5404 22:58:31.238652 Dram Type= 6, Freq= 0, CH_0, rank 1
5405 22:58:31.244986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5406 22:58:31.245070 ==
5407 22:58:31.245137
5408 22:58:31.245197
5409 22:58:31.248035 TX Vref Scan disable
5410 22:58:31.248117 == TX Byte 0 ==
5411 22:58:31.254717 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5412 22:58:31.257839 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5413 22:58:31.257921 == TX Byte 1 ==
5414 22:58:31.264743 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5415 22:58:31.267722 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5416 22:58:31.267829
5417 22:58:31.267921 [DATLAT]
5418 22:58:31.271132 Freq=933, CH0 RK1
5419 22:58:31.271204
5420 22:58:31.271263 DATLAT Default: 0xb
5421 22:58:31.274089 0, 0xFFFF, sum = 0
5422 22:58:31.274162 1, 0xFFFF, sum = 0
5423 22:58:31.277785 2, 0xFFFF, sum = 0
5424 22:58:31.280752 3, 0xFFFF, sum = 0
5425 22:58:31.280877 4, 0xFFFF, sum = 0
5426 22:58:31.284578 5, 0xFFFF, sum = 0
5427 22:58:31.284686 6, 0xFFFF, sum = 0
5428 22:58:31.287670 7, 0xFFFF, sum = 0
5429 22:58:31.287756 8, 0xFFFF, sum = 0
5430 22:58:31.290780 9, 0xFFFF, sum = 0
5431 22:58:31.290927 10, 0x0, sum = 1
5432 22:58:31.294416 11, 0x0, sum = 2
5433 22:58:31.294525 12, 0x0, sum = 3
5434 22:58:31.297435 13, 0x0, sum = 4
5435 22:58:31.297523 best_step = 11
5436 22:58:31.297589
5437 22:58:31.297651 ==
5438 22:58:31.301000 Dram Type= 6, Freq= 0, CH_0, rank 1
5439 22:58:31.304171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5440 22:58:31.304255 ==
5441 22:58:31.307144 RX Vref Scan: 0
5442 22:58:31.307250
5443 22:58:31.310734 RX Vref 0 -> 0, step: 1
5444 22:58:31.310819
5445 22:58:31.310928 RX Delay -69 -> 252, step: 4
5446 22:58:31.318773 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5447 22:58:31.321719 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5448 22:58:31.325256 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5449 22:58:31.328441 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5450 22:58:31.331721 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5451 22:58:31.338316 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5452 22:58:31.341831 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5453 22:58:31.344873 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5454 22:58:31.348481 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5455 22:58:31.351399 iDelay=199, Bit 9, Center 66 (-21 ~ 154) 176
5456 22:58:31.358526 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5457 22:58:31.361680 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5458 22:58:31.364803 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5459 22:58:31.367900 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5460 22:58:31.371182 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5461 22:58:31.377680 iDelay=199, Bit 15, Center 92 (3 ~ 182) 180
5462 22:58:31.377766 ==
5463 22:58:31.381260 Dram Type= 6, Freq= 0, CH_0, rank 1
5464 22:58:31.384291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5465 22:58:31.384374 ==
5466 22:58:31.384440 DQS Delay:
5467 22:58:31.388144 DQS0 = 0, DQS1 = 0
5468 22:58:31.388272 DQM Delay:
5469 22:58:31.391076 DQM0 = 92, DQM1 = 83
5470 22:58:31.391163 DQ Delay:
5471 22:58:31.394306 DQ0 =90, DQ1 =94, DQ2 =88, DQ3 =88
5472 22:58:31.397380 DQ4 =90, DQ5 =80, DQ6 =104, DQ7 =104
5473 22:58:31.400990 DQ8 =76, DQ9 =66, DQ10 =86, DQ11 =76
5474 22:58:31.404176 DQ12 =90, DQ13 =90, DQ14 =94, DQ15 =92
5475 22:58:31.404258
5476 22:58:31.404321
5477 22:58:31.414423 [DQSOSCAuto] RK1, (LSB)MR18= 0x3213, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 406 ps
5478 22:58:31.414533 CH0 RK1: MR19=505, MR18=3213
5479 22:58:31.420804 CH0_RK1: MR19=0x505, MR18=0x3213, DQSOSC=406, MR23=63, INC=65, DEC=43
5480 22:58:31.423819 [RxdqsGatingPostProcess] freq 933
5481 22:58:31.430578 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5482 22:58:31.434299 best DQS0 dly(2T, 0.5T) = (0, 10)
5483 22:58:31.437272 best DQS1 dly(2T, 0.5T) = (0, 11)
5484 22:58:31.440751 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5485 22:58:31.443502 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5486 22:58:31.447096 best DQS0 dly(2T, 0.5T) = (0, 10)
5487 22:58:31.447202 best DQS1 dly(2T, 0.5T) = (0, 10)
5488 22:58:31.450129 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5489 22:58:31.453674 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5490 22:58:31.457275 Pre-setting of DQS Precalculation
5491 22:58:31.463105 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5492 22:58:31.463197 ==
5493 22:58:31.466715 Dram Type= 6, Freq= 0, CH_1, rank 0
5494 22:58:31.469816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5495 22:58:31.469924 ==
5496 22:58:31.476664 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5497 22:58:31.483013 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5498 22:58:31.486523 [CA 0] Center 37 (7~68) winsize 62
5499 22:58:31.489626 [CA 1] Center 37 (7~68) winsize 62
5500 22:58:31.492602 [CA 2] Center 34 (5~64) winsize 60
5501 22:58:31.496345 [CA 3] Center 34 (5~64) winsize 60
5502 22:58:31.499482 [CA 4] Center 34 (5~64) winsize 60
5503 22:58:31.502648 [CA 5] Center 34 (4~64) winsize 61
5504 22:58:31.502756
5505 22:58:31.506219 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5506 22:58:31.506307
5507 22:58:31.509389 [CATrainingPosCal] consider 1 rank data
5508 22:58:31.512880 u2DelayCellTimex100 = 270/100 ps
5509 22:58:31.515666 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5510 22:58:31.519160 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5511 22:58:31.522788 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5512 22:58:31.525870 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5513 22:58:31.532531 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5514 22:58:31.535683 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5515 22:58:31.535766
5516 22:58:31.539270 CA PerBit enable=1, Macro0, CA PI delay=34
5517 22:58:31.539351
5518 22:58:31.542266 [CBTSetCACLKResult] CA Dly = 34
5519 22:58:31.542372 CS Dly: 6 (0~37)
5520 22:58:31.542463 ==
5521 22:58:31.545793 Dram Type= 6, Freq= 0, CH_1, rank 1
5522 22:58:31.552288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5523 22:58:31.552370 ==
5524 22:58:31.555639 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5525 22:58:31.562061 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5526 22:58:31.565419 [CA 0] Center 38 (8~68) winsize 61
5527 22:58:31.568818 [CA 1] Center 37 (7~68) winsize 62
5528 22:58:31.572340 [CA 2] Center 35 (5~65) winsize 61
5529 22:58:31.575362 [CA 3] Center 34 (4~64) winsize 61
5530 22:58:31.578579 [CA 4] Center 35 (5~65) winsize 61
5531 22:58:31.582084 [CA 5] Center 34 (4~64) winsize 61
5532 22:58:31.582166
5533 22:58:31.585130 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5534 22:58:31.585212
5535 22:58:31.588737 [CATrainingPosCal] consider 2 rank data
5536 22:58:31.591895 u2DelayCellTimex100 = 270/100 ps
5537 22:58:31.594798 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5538 22:58:31.598200 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5539 22:58:31.604783 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5540 22:58:31.608321 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5541 22:58:31.611268 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5542 22:58:31.614426 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5543 22:58:31.614507
5544 22:58:31.618069 CA PerBit enable=1, Macro0, CA PI delay=34
5545 22:58:31.618150
5546 22:58:31.621130 [CBTSetCACLKResult] CA Dly = 34
5547 22:58:31.624602 CS Dly: 7 (0~39)
5548 22:58:31.624684
5549 22:58:31.627762 ----->DramcWriteLeveling(PI) begin...
5550 22:58:31.627845 ==
5551 22:58:31.630859 Dram Type= 6, Freq= 0, CH_1, rank 0
5552 22:58:31.634553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5553 22:58:31.634635 ==
5554 22:58:31.637499 Write leveling (Byte 0): 27 => 27
5555 22:58:31.641129 Write leveling (Byte 1): 29 => 29
5556 22:58:31.644164 DramcWriteLeveling(PI) end<-----
5557 22:58:31.644245
5558 22:58:31.644309 ==
5559 22:58:31.647813 Dram Type= 6, Freq= 0, CH_1, rank 0
5560 22:58:31.650787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5561 22:58:31.650879 ==
5562 22:58:31.654409 [Gating] SW mode calibration
5563 22:58:31.661052 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5564 22:58:31.667455 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5565 22:58:31.670487 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5566 22:58:31.674263 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 22:58:31.680525 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 22:58:31.683754 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5569 22:58:31.687426 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5570 22:58:31.693649 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5571 22:58:31.697406 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5572 22:58:31.700386 0 14 28 | B1->B0 | 2f2f 2e2e | 1 0 | (1 0) (0 1)
5573 22:58:31.706951 0 15 0 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
5574 22:58:31.710530 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 22:58:31.713455 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 22:58:31.720194 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 22:58:31.723348 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5578 22:58:31.727152 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5579 22:58:31.733118 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5580 22:58:31.736807 0 15 28 | B1->B0 | 3535 3333 | 0 0 | (0 0) (0 0)
5581 22:58:31.740003 1 0 0 | B1->B0 | 3f3f 4141 | 0 0 | (0 0) (0 0)
5582 22:58:31.746561 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 22:58:31.749727 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 22:58:31.753382 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 22:58:31.759586 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 22:58:31.763335 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 22:58:31.766280 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 22:58:31.772838 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5589 22:58:31.776471 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5590 22:58:31.779717 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 22:58:31.786074 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 22:58:31.788916 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 22:58:31.792945 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 22:58:31.799140 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 22:58:31.802762 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 22:58:31.805863 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 22:58:31.812665 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 22:58:31.815591 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 22:58:31.819197 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 22:58:31.825838 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 22:58:31.828924 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 22:58:31.832504 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 22:58:31.838597 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5604 22:58:31.842283 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5605 22:58:31.845291 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5606 22:58:31.851894 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 22:58:31.855110 Total UI for P1: 0, mck2ui 16
5608 22:58:31.858767 best dqsien dly found for B0: ( 1, 2, 28)
5609 22:58:31.858867 Total UI for P1: 0, mck2ui 16
5610 22:58:31.864805 best dqsien dly found for B1: ( 1, 2, 28)
5611 22:58:31.868579 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5612 22:58:31.871548 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5613 22:58:31.871620
5614 22:58:31.875144 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5615 22:58:31.878359 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5616 22:58:31.881431 [Gating] SW calibration Done
5617 22:58:31.881501 ==
5618 22:58:31.884837 Dram Type= 6, Freq= 0, CH_1, rank 0
5619 22:58:31.887856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5620 22:58:31.887952 ==
5621 22:58:31.891515 RX Vref Scan: 0
5622 22:58:31.891616
5623 22:58:31.894513 RX Vref 0 -> 0, step: 1
5624 22:58:31.894607
5625 22:58:31.894695 RX Delay -80 -> 252, step: 8
5626 22:58:31.901367 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5627 22:58:31.904516 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5628 22:58:31.908153 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5629 22:58:31.911280 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5630 22:58:31.914323 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5631 22:58:31.921153 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5632 22:58:31.924489 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5633 22:58:31.927500 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5634 22:58:31.931164 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5635 22:58:31.934212 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5636 22:58:31.937763 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5637 22:58:31.944603 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5638 22:58:31.947682 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5639 22:58:31.951244 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5640 22:58:31.954248 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5641 22:58:31.957252 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5642 22:58:31.961008 ==
5643 22:58:31.961109 Dram Type= 6, Freq= 0, CH_1, rank 0
5644 22:58:31.967682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5645 22:58:31.967782 ==
5646 22:58:31.967860 DQS Delay:
5647 22:58:31.970662 DQS0 = 0, DQS1 = 0
5648 22:58:31.970756 DQM Delay:
5649 22:58:31.974386 DQM0 = 94, DQM1 = 86
5650 22:58:31.974458 DQ Delay:
5651 22:58:31.977469 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5652 22:58:31.980452 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5653 22:58:31.983617 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =83
5654 22:58:31.987245 DQ12 =95, DQ13 =91, DQ14 =91, DQ15 =91
5655 22:58:31.987340
5656 22:58:31.987428
5657 22:58:31.987513 ==
5658 22:58:31.990181 Dram Type= 6, Freq= 0, CH_1, rank 0
5659 22:58:31.993729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5660 22:58:31.993827 ==
5661 22:58:31.993914
5662 22:58:31.993973
5663 22:58:31.996801 TX Vref Scan disable
5664 22:58:32.000566 == TX Byte 0 ==
5665 22:58:32.004078 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5666 22:58:32.007058 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5667 22:58:32.010122 == TX Byte 1 ==
5668 22:58:32.013875 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5669 22:58:32.016821 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5670 22:58:32.016922 ==
5671 22:58:32.019900 Dram Type= 6, Freq= 0, CH_1, rank 0
5672 22:58:32.026471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5673 22:58:32.026557 ==
5674 22:58:32.026623
5675 22:58:32.026683
5676 22:58:32.026741 TX Vref Scan disable
5677 22:58:32.030571 == TX Byte 0 ==
5678 22:58:32.034023 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5679 22:58:32.040563 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5680 22:58:32.040647 == TX Byte 1 ==
5681 22:58:32.044312 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5682 22:58:32.050653 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5683 22:58:32.050761
5684 22:58:32.050857 [DATLAT]
5685 22:58:32.050961 Freq=933, CH1 RK0
5686 22:58:32.051022
5687 22:58:32.053740 DATLAT Default: 0xd
5688 22:58:32.057075 0, 0xFFFF, sum = 0
5689 22:58:32.057144 1, 0xFFFF, sum = 0
5690 22:58:32.060408 2, 0xFFFF, sum = 0
5691 22:58:32.060476 3, 0xFFFF, sum = 0
5692 22:58:32.063634 4, 0xFFFF, sum = 0
5693 22:58:32.063717 5, 0xFFFF, sum = 0
5694 22:58:32.067335 6, 0xFFFF, sum = 0
5695 22:58:32.067444 7, 0xFFFF, sum = 0
5696 22:58:32.070307 8, 0xFFFF, sum = 0
5697 22:58:32.070418 9, 0xFFFF, sum = 0
5698 22:58:32.073873 10, 0x0, sum = 1
5699 22:58:32.073947 11, 0x0, sum = 2
5700 22:58:32.076972 12, 0x0, sum = 3
5701 22:58:32.077043 13, 0x0, sum = 4
5702 22:58:32.080530 best_step = 11
5703 22:58:32.080599
5704 22:58:32.080660 ==
5705 22:58:32.083276 Dram Type= 6, Freq= 0, CH_1, rank 0
5706 22:58:32.087024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5707 22:58:32.087123 ==
5708 22:58:32.087210 RX Vref Scan: 1
5709 22:58:32.089971
5710 22:58:32.090069 RX Vref 0 -> 0, step: 1
5711 22:58:32.090156
5712 22:58:32.093667 RX Delay -69 -> 252, step: 4
5713 22:58:32.093762
5714 22:58:32.096752 Set Vref, RX VrefLevel [Byte0]: 51
5715 22:58:32.099781 [Byte1]: 55
5716 22:58:32.103472
5717 22:58:32.103540 Final RX Vref Byte 0 = 51 to rank0
5718 22:58:32.106973 Final RX Vref Byte 1 = 55 to rank0
5719 22:58:32.110059 Final RX Vref Byte 0 = 51 to rank1
5720 22:58:32.113092 Final RX Vref Byte 1 = 55 to rank1==
5721 22:58:32.116550 Dram Type= 6, Freq= 0, CH_1, rank 0
5722 22:58:32.123193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5723 22:58:32.123266 ==
5724 22:58:32.123328 DQS Delay:
5725 22:58:32.126776 DQS0 = 0, DQS1 = 0
5726 22:58:32.126896 DQM Delay:
5727 22:58:32.126960 DQM0 = 96, DQM1 = 88
5728 22:58:32.129978 DQ Delay:
5729 22:58:32.132927 DQ0 =102, DQ1 =90, DQ2 =84, DQ3 =94
5730 22:58:32.136354 DQ4 =94, DQ5 =106, DQ6 =106, DQ7 =92
5731 22:58:32.139796 DQ8 =76, DQ9 =80, DQ10 =88, DQ11 =80
5732 22:58:32.142752 DQ12 =98, DQ13 =94, DQ14 =94, DQ15 =94
5733 22:58:32.142845
5734 22:58:32.142919
5735 22:58:32.149683 [DQSOSCAuto] RK0, (LSB)MR18= 0x40c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 420 ps
5736 22:58:32.153296 CH1 RK0: MR19=505, MR18=40C
5737 22:58:32.159422 CH1_RK0: MR19=0x505, MR18=0x40C, DQSOSC=418, MR23=63, INC=62, DEC=41
5738 22:58:32.159507
5739 22:58:32.163084 ----->DramcWriteLeveling(PI) begin...
5740 22:58:32.163165 ==
5741 22:58:32.166099 Dram Type= 6, Freq= 0, CH_1, rank 1
5742 22:58:32.169165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5743 22:58:32.169248 ==
5744 22:58:32.172896 Write leveling (Byte 0): 24 => 24
5745 22:58:32.175929 Write leveling (Byte 1): 29 => 29
5746 22:58:32.178890 DramcWriteLeveling(PI) end<-----
5747 22:58:32.178996
5748 22:58:32.179089 ==
5749 22:58:32.182654 Dram Type= 6, Freq= 0, CH_1, rank 1
5750 22:58:32.185749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5751 22:58:32.189210 ==
5752 22:58:32.189296 [Gating] SW mode calibration
5753 22:58:32.196117 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5754 22:58:32.202398 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5755 22:58:32.205856 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5756 22:58:32.212257 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5757 22:58:32.215385 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5758 22:58:32.219015 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5759 22:58:32.225518 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5760 22:58:32.228749 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5761 22:58:32.231814 0 14 24 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
5762 22:58:32.238712 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 22:58:32.241723 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 22:58:32.244839 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 22:58:32.251474 0 15 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5766 22:58:32.255024 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5767 22:58:32.258531 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5768 22:58:32.264640 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5769 22:58:32.268231 0 15 24 | B1->B0 | 2727 3333 | 0 0 | (0 0) (0 0)
5770 22:58:32.271456 0 15 28 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5771 22:58:32.278178 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5772 22:58:32.281182 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 22:58:32.284964 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 22:58:32.291030 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 22:58:32.294637 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5776 22:58:32.297610 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5777 22:58:32.304448 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5778 22:58:32.307521 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5779 22:58:32.311000 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 22:58:32.317328 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 22:58:32.321150 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 22:58:32.324116 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 22:58:32.330751 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 22:58:32.333804 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 22:58:32.337089 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 22:58:32.343810 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 22:58:32.347408 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 22:58:32.350511 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 22:58:32.357169 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 22:58:32.360100 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 22:58:32.363634 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 22:58:32.370098 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 22:58:32.373746 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5794 22:58:32.376743 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5795 22:58:32.380379 Total UI for P1: 0, mck2ui 16
5796 22:58:32.383377 best dqsien dly found for B0: ( 1, 2, 24)
5797 22:58:32.390017 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 22:58:32.390164 Total UI for P1: 0, mck2ui 16
5799 22:58:32.396849 best dqsien dly found for B1: ( 1, 2, 28)
5800 22:58:32.399926 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5801 22:58:32.402897 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5802 22:58:32.402983
5803 22:58:32.406721 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5804 22:58:32.409798 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5805 22:58:32.412928 [Gating] SW calibration Done
5806 22:58:32.413013 ==
5807 22:58:32.416520 Dram Type= 6, Freq= 0, CH_1, rank 1
5808 22:58:32.420054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5809 22:58:32.420140 ==
5810 22:58:32.423562 RX Vref Scan: 0
5811 22:58:32.423647
5812 22:58:32.423714 RX Vref 0 -> 0, step: 1
5813 22:58:32.426386
5814 22:58:32.426469 RX Delay -80 -> 252, step: 8
5815 22:58:32.432881 iDelay=200, Bit 0, Center 99 (0 ~ 199) 200
5816 22:58:32.436320 iDelay=200, Bit 1, Center 87 (-16 ~ 191) 208
5817 22:58:32.439398 iDelay=200, Bit 2, Center 79 (-16 ~ 175) 192
5818 22:58:32.443025 iDelay=200, Bit 3, Center 87 (-16 ~ 191) 208
5819 22:58:32.446075 iDelay=200, Bit 4, Center 91 (-8 ~ 191) 200
5820 22:58:32.452692 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5821 22:58:32.456003 iDelay=200, Bit 6, Center 99 (0 ~ 199) 200
5822 22:58:32.459119 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5823 22:58:32.462224 iDelay=200, Bit 8, Center 75 (-24 ~ 175) 200
5824 22:58:32.465959 iDelay=200, Bit 9, Center 75 (-24 ~ 175) 200
5825 22:58:32.469385 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5826 22:58:32.475501 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5827 22:58:32.479104 iDelay=200, Bit 12, Center 95 (-8 ~ 199) 208
5828 22:58:32.482176 iDelay=200, Bit 13, Center 95 (-8 ~ 199) 208
5829 22:58:32.485875 iDelay=200, Bit 14, Center 91 (-8 ~ 191) 200
5830 22:58:32.488896 iDelay=200, Bit 15, Center 91 (-8 ~ 191) 200
5831 22:58:32.492539 ==
5832 22:58:32.495617 Dram Type= 6, Freq= 0, CH_1, rank 1
5833 22:58:32.498934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5834 22:58:32.499015 ==
5835 22:58:32.499082 DQS Delay:
5836 22:58:32.501963 DQS0 = 0, DQS1 = 0
5837 22:58:32.502038 DQM Delay:
5838 22:58:32.505657 DQM0 = 92, DQM1 = 87
5839 22:58:32.505733 DQ Delay:
5840 22:58:32.508776 DQ0 =99, DQ1 =87, DQ2 =79, DQ3 =87
5841 22:58:32.511941 DQ4 =91, DQ5 =103, DQ6 =99, DQ7 =91
5842 22:58:32.515560 DQ8 =75, DQ9 =75, DQ10 =91, DQ11 =83
5843 22:58:32.518678 DQ12 =95, DQ13 =95, DQ14 =91, DQ15 =91
5844 22:58:32.518754
5845 22:58:32.518826
5846 22:58:32.518900 ==
5847 22:58:32.521767 Dram Type= 6, Freq= 0, CH_1, rank 1
5848 22:58:32.525533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5849 22:58:32.525610 ==
5850 22:58:32.525688
5851 22:58:32.528393
5852 22:58:32.528472 TX Vref Scan disable
5853 22:58:32.532014 == TX Byte 0 ==
5854 22:58:32.535120 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5855 22:58:32.538143 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5856 22:58:32.541723 == TX Byte 1 ==
5857 22:58:32.545118 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5858 22:58:32.548221 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5859 22:58:32.548305 ==
5860 22:58:32.552056 Dram Type= 6, Freq= 0, CH_1, rank 1
5861 22:58:32.558168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5862 22:58:32.558269 ==
5863 22:58:32.558338
5864 22:58:32.558400
5865 22:58:32.558477 TX Vref Scan disable
5866 22:58:32.562333 == TX Byte 0 ==
5867 22:58:32.566005 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5868 22:58:32.572931 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5869 22:58:32.573024 == TX Byte 1 ==
5870 22:58:32.575786 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5871 22:58:32.582169 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5872 22:58:32.582252
5873 22:58:32.582318 [DATLAT]
5874 22:58:32.582391 Freq=933, CH1 RK1
5875 22:58:32.582452
5876 22:58:32.585566 DATLAT Default: 0xb
5877 22:58:32.588678 0, 0xFFFF, sum = 0
5878 22:58:32.588753 1, 0xFFFF, sum = 0
5879 22:58:32.592216 2, 0xFFFF, sum = 0
5880 22:58:32.592306 3, 0xFFFF, sum = 0
5881 22:58:32.595743 4, 0xFFFF, sum = 0
5882 22:58:32.595831 5, 0xFFFF, sum = 0
5883 22:58:32.598781 6, 0xFFFF, sum = 0
5884 22:58:32.598918 7, 0xFFFF, sum = 0
5885 22:58:32.601886 8, 0xFFFF, sum = 0
5886 22:58:32.602006 9, 0xFFFF, sum = 0
5887 22:58:32.605579 10, 0x0, sum = 1
5888 22:58:32.605695 11, 0x0, sum = 2
5889 22:58:32.608683 12, 0x0, sum = 3
5890 22:58:32.608827 13, 0x0, sum = 4
5891 22:58:32.611721 best_step = 11
5892 22:58:32.611832
5893 22:58:32.611920 ==
5894 22:58:32.615641 Dram Type= 6, Freq= 0, CH_1, rank 1
5895 22:58:32.618555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5896 22:58:32.618680 ==
5897 22:58:32.618772 RX Vref Scan: 0
5898 22:58:32.621537
5899 22:58:32.621633 RX Vref 0 -> 0, step: 1
5900 22:58:32.621721
5901 22:58:32.625300 RX Delay -69 -> 252, step: 4
5902 22:58:32.631370 iDelay=203, Bit 0, Center 98 (3 ~ 194) 192
5903 22:58:32.635006 iDelay=203, Bit 1, Center 88 (-9 ~ 186) 196
5904 22:58:32.638536 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5905 22:58:32.641505 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5906 22:58:32.644555 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5907 22:58:32.651083 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5908 22:58:32.654527 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5909 22:58:32.658177 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5910 22:58:32.661658 iDelay=203, Bit 8, Center 78 (-17 ~ 174) 192
5911 22:58:32.664817 iDelay=203, Bit 9, Center 82 (-9 ~ 174) 184
5912 22:58:32.667842 iDelay=203, Bit 10, Center 92 (-5 ~ 190) 196
5913 22:58:32.674601 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5914 22:58:32.677626 iDelay=203, Bit 12, Center 100 (7 ~ 194) 188
5915 22:58:32.681378 iDelay=203, Bit 13, Center 100 (7 ~ 194) 188
5916 22:58:32.684484 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5917 22:58:32.687763 iDelay=203, Bit 15, Center 100 (7 ~ 194) 188
5918 22:58:32.691273 ==
5919 22:58:32.693989 Dram Type= 6, Freq= 0, CH_1, rank 1
5920 22:58:32.697556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5921 22:58:32.697641 ==
5922 22:58:32.697707 DQS Delay:
5923 22:58:32.701316 DQS0 = 0, DQS1 = 0
5924 22:58:32.701400 DQM Delay:
5925 22:58:32.704317 DQM0 = 92, DQM1 = 91
5926 22:58:32.704400 DQ Delay:
5927 22:58:32.707456 DQ0 =98, DQ1 =88, DQ2 =82, DQ3 =88
5928 22:58:32.710555 DQ4 =90, DQ5 =102, DQ6 =104, DQ7 =88
5929 22:58:32.714293 DQ8 =78, DQ9 =82, DQ10 =92, DQ11 =84
5930 22:58:32.717368 DQ12 =100, DQ13 =100, DQ14 =98, DQ15 =100
5931 22:58:32.717478
5932 22:58:32.717571
5933 22:58:32.724323 [DQSOSCAuto] RK1, (LSB)MR18= 0xd21, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 417 ps
5934 22:58:32.727392 CH1 RK1: MR19=505, MR18=D21
5935 22:58:32.733997 CH1_RK1: MR19=0x505, MR18=0xD21, DQSOSC=411, MR23=63, INC=64, DEC=42
5936 22:58:32.736922 [RxdqsGatingPostProcess] freq 933
5937 22:58:32.743600 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5938 22:58:32.747294 best DQS0 dly(2T, 0.5T) = (0, 10)
5939 22:58:32.750315 best DQS1 dly(2T, 0.5T) = (0, 10)
5940 22:58:32.750400 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5941 22:58:32.753363 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5942 22:58:32.756949 best DQS0 dly(2T, 0.5T) = (0, 10)
5943 22:58:32.760330 best DQS1 dly(2T, 0.5T) = (0, 10)
5944 22:58:32.763732 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5945 22:58:32.766578 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5946 22:58:32.770147 Pre-setting of DQS Precalculation
5947 22:58:32.776988 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5948 22:58:32.783678 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5949 22:58:32.789760 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5950 22:58:32.789868
5951 22:58:32.789958
5952 22:58:32.793462 [Calibration Summary] 1866 Mbps
5953 22:58:32.793546 CH 0, Rank 0
5954 22:58:32.796986 SW Impedance : PASS
5955 22:58:32.799703 DUTY Scan : NO K
5956 22:58:32.799793 ZQ Calibration : PASS
5957 22:58:32.803333 Jitter Meter : NO K
5958 22:58:32.806749 CBT Training : PASS
5959 22:58:32.806902 Write leveling : PASS
5960 22:58:32.809748 RX DQS gating : PASS
5961 22:58:32.813213 RX DQ/DQS(RDDQC) : PASS
5962 22:58:32.813298 TX DQ/DQS : PASS
5963 22:58:32.816349 RX DATLAT : PASS
5964 22:58:32.819476 RX DQ/DQS(Engine): PASS
5965 22:58:32.819563 TX OE : NO K
5966 22:58:32.822715 All Pass.
5967 22:58:32.822787
5968 22:58:32.822883 CH 0, Rank 1
5969 22:58:32.826423 SW Impedance : PASS
5970 22:58:32.826495 DUTY Scan : NO K
5971 22:58:32.829500 ZQ Calibration : PASS
5972 22:58:32.833170 Jitter Meter : NO K
5973 22:58:32.833244 CBT Training : PASS
5974 22:58:32.836217 Write leveling : PASS
5975 22:58:32.839334 RX DQS gating : PASS
5976 22:58:32.839450 RX DQ/DQS(RDDQC) : PASS
5977 22:58:32.842748 TX DQ/DQS : PASS
5978 22:58:32.845789 RX DATLAT : PASS
5979 22:58:32.845891 RX DQ/DQS(Engine): PASS
5980 22:58:32.849460 TX OE : NO K
5981 22:58:32.849563 All Pass.
5982 22:58:32.849655
5983 22:58:32.852598 CH 1, Rank 0
5984 22:58:32.852695 SW Impedance : PASS
5985 22:58:32.855706 DUTY Scan : NO K
5986 22:58:32.855804 ZQ Calibration : PASS
5987 22:58:32.859399 Jitter Meter : NO K
5988 22:58:32.862609 CBT Training : PASS
5989 22:58:32.862705 Write leveling : PASS
5990 22:58:32.865666 RX DQS gating : PASS
5991 22:58:32.868729 RX DQ/DQS(RDDQC) : PASS
5992 22:58:32.868828 TX DQ/DQS : PASS
5993 22:58:32.872301 RX DATLAT : PASS
5994 22:58:32.875811 RX DQ/DQS(Engine): PASS
5995 22:58:32.875896 TX OE : NO K
5996 22:58:32.879273 All Pass.
5997 22:58:32.879357
5998 22:58:32.879424 CH 1, Rank 1
5999 22:58:32.882102 SW Impedance : PASS
6000 22:58:32.882186 DUTY Scan : NO K
6001 22:58:32.885732 ZQ Calibration : PASS
6002 22:58:32.888838 Jitter Meter : NO K
6003 22:58:32.888922 CBT Training : PASS
6004 22:58:32.892001 Write leveling : PASS
6005 22:58:32.895645 RX DQS gating : PASS
6006 22:58:32.895730 RX DQ/DQS(RDDQC) : PASS
6007 22:58:32.898761 TX DQ/DQS : PASS
6008 22:58:32.902187 RX DATLAT : PASS
6009 22:58:32.902271 RX DQ/DQS(Engine): PASS
6010 22:58:32.905029 TX OE : NO K
6011 22:58:32.905114 All Pass.
6012 22:58:32.905181
6013 22:58:32.908447 DramC Write-DBI off
6014 22:58:32.912181 PER_BANK_REFRESH: Hybrid Mode
6015 22:58:32.912266 TX_TRACKING: ON
6016 22:58:32.921545 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6017 22:58:32.925121 [FAST_K] Save calibration result to emmc
6018 22:58:32.928096 dramc_set_vcore_voltage set vcore to 650000
6019 22:58:32.931772 Read voltage for 400, 6
6020 22:58:32.931856 Vio18 = 0
6021 22:58:32.931922 Vcore = 650000
6022 22:58:32.934862 Vdram = 0
6023 22:58:32.934945 Vddq = 0
6024 22:58:32.935012 Vmddr = 0
6025 22:58:32.941724 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6026 22:58:32.945226 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6027 22:58:32.948405 MEM_TYPE=3, freq_sel=20
6028 22:58:32.951442 sv_algorithm_assistance_LP4_800
6029 22:58:32.955214 ============ PULL DRAM RESETB DOWN ============
6030 22:58:32.958158 ========== PULL DRAM RESETB DOWN end =========
6031 22:58:32.964391 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6032 22:58:32.968089 ===================================
6033 22:58:32.971258 LPDDR4 DRAM CONFIGURATION
6034 22:58:32.974751 ===================================
6035 22:58:32.974842 EX_ROW_EN[0] = 0x0
6036 22:58:32.977902 EX_ROW_EN[1] = 0x0
6037 22:58:32.977986 LP4Y_EN = 0x0
6038 22:58:32.981656 WORK_FSP = 0x0
6039 22:58:32.981740 WL = 0x2
6040 22:58:32.984307 RL = 0x2
6041 22:58:32.984391 BL = 0x2
6042 22:58:32.987718 RPST = 0x0
6043 22:58:32.987806 RD_PRE = 0x0
6044 22:58:32.991286 WR_PRE = 0x1
6045 22:58:32.991373 WR_PST = 0x0
6046 22:58:32.994334 DBI_WR = 0x0
6047 22:58:32.997409 DBI_RD = 0x0
6048 22:58:32.997492 OTF = 0x1
6049 22:58:33.001089 ===================================
6050 22:58:33.004295 ===================================
6051 22:58:33.004380 ANA top config
6052 22:58:33.007902 ===================================
6053 22:58:33.010734 DLL_ASYNC_EN = 0
6054 22:58:33.013713 ALL_SLAVE_EN = 1
6055 22:58:33.017310 NEW_RANK_MODE = 1
6056 22:58:33.020724 DLL_IDLE_MODE = 1
6057 22:58:33.020823 LP45_APHY_COMB_EN = 1
6058 22:58:33.023664 TX_ODT_DIS = 1
6059 22:58:33.026967 NEW_8X_MODE = 1
6060 22:58:33.030358 ===================================
6061 22:58:33.033895 ===================================
6062 22:58:33.037069 data_rate = 800
6063 22:58:33.040199 CKR = 1
6064 22:58:33.044002 DQ_P2S_RATIO = 4
6065 22:58:33.047033 ===================================
6066 22:58:33.047117 CA_P2S_RATIO = 4
6067 22:58:33.050002 DQ_CA_OPEN = 0
6068 22:58:33.053232 DQ_SEMI_OPEN = 1
6069 22:58:33.056986 CA_SEMI_OPEN = 1
6070 22:58:33.059920 CA_FULL_RATE = 0
6071 22:58:33.063510 DQ_CKDIV4_EN = 0
6072 22:58:33.063594 CA_CKDIV4_EN = 1
6073 22:58:33.066363 CA_PREDIV_EN = 0
6074 22:58:33.070052 PH8_DLY = 0
6075 22:58:33.073058 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6076 22:58:33.076677 DQ_AAMCK_DIV = 0
6077 22:58:33.079825 CA_AAMCK_DIV = 0
6078 22:58:33.079924 CA_ADMCK_DIV = 4
6079 22:58:33.082936 DQ_TRACK_CA_EN = 0
6080 22:58:33.086031 CA_PICK = 800
6081 22:58:33.089727 CA_MCKIO = 400
6082 22:58:33.092746 MCKIO_SEMI = 400
6083 22:58:33.096165 PLL_FREQ = 3016
6084 22:58:33.099793 DQ_UI_PI_RATIO = 32
6085 22:58:33.102800 CA_UI_PI_RATIO = 32
6086 22:58:33.105950 ===================================
6087 22:58:33.109521 ===================================
6088 22:58:33.109594 memory_type:LPDDR4
6089 22:58:33.112898 GP_NUM : 10
6090 22:58:33.115983 SRAM_EN : 1
6091 22:58:33.116057 MD32_EN : 0
6092 22:58:33.119012 ===================================
6093 22:58:33.122676 [ANA_INIT] >>>>>>>>>>>>>>
6094 22:58:33.125751 <<<<<< [CONFIGURE PHASE]: ANA_TX
6095 22:58:33.128945 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6096 22:58:33.132307 ===================================
6097 22:58:33.135640 data_rate = 800,PCW = 0X7400
6098 22:58:33.139131 ===================================
6099 22:58:33.141936 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6100 22:58:33.145710 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6101 22:58:33.158430 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6102 22:58:33.162201 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6103 22:58:33.165343 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6104 22:58:33.168531 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6105 22:58:33.171989 [ANA_INIT] flow start
6106 22:58:33.175013 [ANA_INIT] PLL >>>>>>>>
6107 22:58:33.175100 [ANA_INIT] PLL <<<<<<<<
6108 22:58:33.178175 [ANA_INIT] MIDPI >>>>>>>>
6109 22:58:33.181766 [ANA_INIT] MIDPI <<<<<<<<
6110 22:58:33.181849 [ANA_INIT] DLL >>>>>>>>
6111 22:58:33.184807 [ANA_INIT] flow end
6112 22:58:33.188503 ============ LP4 DIFF to SE enter ============
6113 22:58:33.194600 ============ LP4 DIFF to SE exit ============
6114 22:58:33.194755 [ANA_INIT] <<<<<<<<<<<<<
6115 22:58:33.198376 [Flow] Enable top DCM control >>>>>
6116 22:58:33.201402 [Flow] Enable top DCM control <<<<<
6117 22:58:33.204886 Enable DLL master slave shuffle
6118 22:58:33.211028 ==============================================================
6119 22:58:33.211139 Gating Mode config
6120 22:58:33.217639 ==============================================================
6121 22:58:33.221366 Config description:
6122 22:58:33.230677 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6123 22:58:33.237340 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6124 22:58:33.241127 SELPH_MODE 0: By rank 1: By Phase
6125 22:58:33.247085 ==============================================================
6126 22:58:33.250728 GAT_TRACK_EN = 0
6127 22:58:33.253975 RX_GATING_MODE = 2
6128 22:58:33.254125 RX_GATING_TRACK_MODE = 2
6129 22:58:33.256983 SELPH_MODE = 1
6130 22:58:33.260735 PICG_EARLY_EN = 1
6131 22:58:33.263949 VALID_LAT_VALUE = 1
6132 22:58:33.270709 ==============================================================
6133 22:58:33.273811 Enter into Gating configuration >>>>
6134 22:58:33.276941 Exit from Gating configuration <<<<
6135 22:58:33.280811 Enter into DVFS_PRE_config >>>>>
6136 22:58:33.290448 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6137 22:58:33.293468 Exit from DVFS_PRE_config <<<<<
6138 22:58:33.296596 Enter into PICG configuration >>>>
6139 22:58:33.299651 Exit from PICG configuration <<<<
6140 22:58:33.303001 [RX_INPUT] configuration >>>>>
6141 22:58:33.306574 [RX_INPUT] configuration <<<<<
6142 22:58:33.309805 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6143 22:58:33.316467 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6144 22:58:33.322590 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6145 22:58:33.329519 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6146 22:58:33.336104 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6147 22:58:33.342195 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6148 22:58:33.345969 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6149 22:58:33.349009 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6150 22:58:33.352509 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6151 22:58:33.358894 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6152 22:58:33.362410 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6153 22:58:33.365509 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6154 22:58:33.368558 ===================================
6155 22:58:33.372248 LPDDR4 DRAM CONFIGURATION
6156 22:58:33.375302 ===================================
6157 22:58:33.375393 EX_ROW_EN[0] = 0x0
6158 22:58:33.378960 EX_ROW_EN[1] = 0x0
6159 22:58:33.382071 LP4Y_EN = 0x0
6160 22:58:33.382147 WORK_FSP = 0x0
6161 22:58:33.385612 WL = 0x2
6162 22:58:33.385714 RL = 0x2
6163 22:58:33.388681 BL = 0x2
6164 22:58:33.388787 RPST = 0x0
6165 22:58:33.392159 RD_PRE = 0x0
6166 22:58:33.392283 WR_PRE = 0x1
6167 22:58:33.395243 WR_PST = 0x0
6168 22:58:33.395321 DBI_WR = 0x0
6169 22:58:33.398355 DBI_RD = 0x0
6170 22:58:33.398455 OTF = 0x1
6171 22:58:33.401957 ===================================
6172 22:58:33.405098 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6173 22:58:33.411643 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6174 22:58:33.414749 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6175 22:58:33.418286 ===================================
6176 22:58:33.421386 LPDDR4 DRAM CONFIGURATION
6177 22:58:33.425030 ===================================
6178 22:58:33.428129 EX_ROW_EN[0] = 0x10
6179 22:58:33.428213 EX_ROW_EN[1] = 0x0
6180 22:58:33.431676 LP4Y_EN = 0x0
6181 22:58:33.431773 WORK_FSP = 0x0
6182 22:58:33.434713 WL = 0x2
6183 22:58:33.434798 RL = 0x2
6184 22:58:33.438369 BL = 0x2
6185 22:58:33.438466 RPST = 0x0
6186 22:58:33.441418 RD_PRE = 0x0
6187 22:58:33.441503 WR_PRE = 0x1
6188 22:58:33.444904 WR_PST = 0x0
6189 22:58:33.444987 DBI_WR = 0x0
6190 22:58:33.448070 DBI_RD = 0x0
6191 22:58:33.448157 OTF = 0x1
6192 22:58:33.451244 ===================================
6193 22:58:33.457989 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6194 22:58:33.462463 nWR fixed to 30
6195 22:58:33.465902 [ModeRegInit_LP4] CH0 RK0
6196 22:58:33.465979 [ModeRegInit_LP4] CH0 RK1
6197 22:58:33.469374 [ModeRegInit_LP4] CH1 RK0
6198 22:58:33.472147 [ModeRegInit_LP4] CH1 RK1
6199 22:58:33.472247 match AC timing 19
6200 22:58:33.478762 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6201 22:58:33.481983 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6202 22:58:33.485715 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6203 22:58:33.492324 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6204 22:58:33.495396 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6205 22:58:33.495495 ==
6206 22:58:33.499008 Dram Type= 6, Freq= 0, CH_0, rank 0
6207 22:58:33.502012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6208 22:58:33.502090 ==
6209 22:58:33.508294 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6210 22:58:33.514909 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6211 22:58:33.518630 [CA 0] Center 36 (8~64) winsize 57
6212 22:58:33.521647 [CA 1] Center 36 (8~64) winsize 57
6213 22:58:33.524596 [CA 2] Center 36 (8~64) winsize 57
6214 22:58:33.528212 [CA 3] Center 36 (8~64) winsize 57
6215 22:58:33.531648 [CA 4] Center 36 (8~64) winsize 57
6216 22:58:33.534545 [CA 5] Center 36 (8~64) winsize 57
6217 22:58:33.534660
6218 22:58:33.537721 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6219 22:58:33.537831
6220 22:58:33.541357 [CATrainingPosCal] consider 1 rank data
6221 22:58:33.544481 u2DelayCellTimex100 = 270/100 ps
6222 22:58:33.548046 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 22:58:33.551123 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 22:58:33.554303 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 22:58:33.557983 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 22:58:33.561068 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 22:58:33.564720 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 22:58:33.564818
6229 22:58:33.571073 CA PerBit enable=1, Macro0, CA PI delay=36
6230 22:58:33.571176
6231 22:58:33.571281 [CBTSetCACLKResult] CA Dly = 36
6232 22:58:33.574614 CS Dly: 1 (0~32)
6233 22:58:33.574714 ==
6234 22:58:33.577484 Dram Type= 6, Freq= 0, CH_0, rank 1
6235 22:58:33.580911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6236 22:58:33.581018 ==
6237 22:58:33.587726 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6238 22:58:33.593844 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6239 22:58:33.597561 [CA 0] Center 36 (8~64) winsize 57
6240 22:58:33.601057 [CA 1] Center 36 (8~64) winsize 57
6241 22:58:33.604155 [CA 2] Center 36 (8~64) winsize 57
6242 22:58:33.607213 [CA 3] Center 36 (8~64) winsize 57
6243 22:58:33.610824 [CA 4] Center 36 (8~64) winsize 57
6244 22:58:33.610942 [CA 5] Center 36 (8~64) winsize 57
6245 22:58:33.614110
6246 22:58:33.617159 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6247 22:58:33.617240
6248 22:58:33.620745 [CATrainingPosCal] consider 2 rank data
6249 22:58:33.623797 u2DelayCellTimex100 = 270/100 ps
6250 22:58:33.626972 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 22:58:33.630660 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 22:58:33.633506 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 22:58:33.637047 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 22:58:33.640035 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 22:58:33.643717 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 22:58:33.643798
6257 22:58:33.646788 CA PerBit enable=1, Macro0, CA PI delay=36
6258 22:58:33.650375
6259 22:58:33.650456 [CBTSetCACLKResult] CA Dly = 36
6260 22:58:33.653577 CS Dly: 1 (0~32)
6261 22:58:33.653659
6262 22:58:33.656563 ----->DramcWriteLeveling(PI) begin...
6263 22:58:33.656646 ==
6264 22:58:33.660234 Dram Type= 6, Freq= 0, CH_0, rank 0
6265 22:58:33.663296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6266 22:58:33.663379 ==
6267 22:58:33.666409 Write leveling (Byte 0): 40 => 8
6268 22:58:33.670052 Write leveling (Byte 1): 40 => 8
6269 22:58:33.673005 DramcWriteLeveling(PI) end<-----
6270 22:58:33.673086
6271 22:58:33.673150 ==
6272 22:58:33.676434 Dram Type= 6, Freq= 0, CH_0, rank 0
6273 22:58:33.679974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6274 22:58:33.682849 ==
6275 22:58:33.682975 [Gating] SW mode calibration
6276 22:58:33.693089 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6277 22:58:33.696403 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6278 22:58:33.699633 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6279 22:58:33.706238 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6280 22:58:33.709149 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6281 22:58:33.712721 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6282 22:58:33.719490 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6283 22:58:33.722491 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6284 22:58:33.726129 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6285 22:58:33.732323 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6286 22:58:33.735922 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6287 22:58:33.738954 Total UI for P1: 0, mck2ui 16
6288 22:58:33.741953 best dqsien dly found for B0: ( 0, 14, 24)
6289 22:58:33.745458 Total UI for P1: 0, mck2ui 16
6290 22:58:33.748612 best dqsien dly found for B1: ( 0, 14, 24)
6291 22:58:33.752308 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6292 22:58:33.755418 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6293 22:58:33.755516
6294 22:58:33.758487 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6295 22:58:33.765244 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6296 22:58:33.765332 [Gating] SW calibration Done
6297 22:58:33.765395 ==
6298 22:58:33.769040 Dram Type= 6, Freq= 0, CH_0, rank 0
6299 22:58:33.775399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6300 22:58:33.775488 ==
6301 22:58:33.775552 RX Vref Scan: 0
6302 22:58:33.775612
6303 22:58:33.778412 RX Vref 0 -> 0, step: 1
6304 22:58:33.778492
6305 22:58:33.782060 RX Delay -410 -> 252, step: 16
6306 22:58:33.785116 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6307 22:58:33.788949 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6308 22:58:33.795159 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6309 22:58:33.798113 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6310 22:58:33.801648 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6311 22:58:33.804815 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6312 22:58:33.811440 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6313 22:58:33.815058 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6314 22:58:33.818050 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6315 22:58:33.821508 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6316 22:58:33.828329 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6317 22:58:33.831377 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6318 22:58:33.834639 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6319 22:58:33.841398 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6320 22:58:33.844405 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6321 22:58:33.847873 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6322 22:58:33.847952 ==
6323 22:58:33.850711 Dram Type= 6, Freq= 0, CH_0, rank 0
6324 22:58:33.854473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6325 22:58:33.857662 ==
6326 22:58:33.857742 DQS Delay:
6327 22:58:33.857805 DQS0 = 59, DQS1 = 59
6328 22:58:33.860666 DQM Delay:
6329 22:58:33.860744 DQM0 = 18, DQM1 = 9
6330 22:58:33.864357 DQ Delay:
6331 22:58:33.867489 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6332 22:58:33.867569 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6333 22:58:33.870592 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6334 22:58:33.874289 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6335 22:58:33.874367
6336 22:58:33.874428
6337 22:58:33.877467 ==
6338 22:58:33.880495 Dram Type= 6, Freq= 0, CH_0, rank 0
6339 22:58:33.883987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6340 22:58:33.884071 ==
6341 22:58:33.884136
6342 22:58:33.884211
6343 22:58:33.887090 TX Vref Scan disable
6344 22:58:33.887216 == TX Byte 0 ==
6345 22:58:33.890770 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6346 22:58:33.896854 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6347 22:58:33.897071 == TX Byte 1 ==
6348 22:58:33.900488 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6349 22:58:33.906978 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6350 22:58:33.907124 ==
6351 22:58:33.910468 Dram Type= 6, Freq= 0, CH_0, rank 0
6352 22:58:33.913435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6353 22:58:33.913525 ==
6354 22:58:33.913622
6355 22:58:33.913680
6356 22:58:33.917130 TX Vref Scan disable
6357 22:58:33.917212 == TX Byte 0 ==
6358 22:58:33.920176 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6359 22:58:33.926799 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6360 22:58:33.926978 == TX Byte 1 ==
6361 22:58:33.930363 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6362 22:58:33.936836 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6363 22:58:33.936945
6364 22:58:33.937009 [DATLAT]
6365 22:58:33.937067 Freq=400, CH0 RK0
6366 22:58:33.940081
6367 22:58:33.940160 DATLAT Default: 0xf
6368 22:58:33.943731 0, 0xFFFF, sum = 0
6369 22:58:33.943812 1, 0xFFFF, sum = 0
6370 22:58:33.946755 2, 0xFFFF, sum = 0
6371 22:58:33.946877 3, 0xFFFF, sum = 0
6372 22:58:33.949809 4, 0xFFFF, sum = 0
6373 22:58:33.949889 5, 0xFFFF, sum = 0
6374 22:58:33.953596 6, 0xFFFF, sum = 0
6375 22:58:33.953680 7, 0xFFFF, sum = 0
6376 22:58:33.956386 8, 0xFFFF, sum = 0
6377 22:58:33.956466 9, 0xFFFF, sum = 0
6378 22:58:33.959999 10, 0xFFFF, sum = 0
6379 22:58:33.960079 11, 0xFFFF, sum = 0
6380 22:58:33.962993 12, 0xFFFF, sum = 0
6381 22:58:33.963074 13, 0x0, sum = 1
6382 22:58:33.966579 14, 0x0, sum = 2
6383 22:58:33.966660 15, 0x0, sum = 3
6384 22:58:33.969590 16, 0x0, sum = 4
6385 22:58:33.969670 best_step = 14
6386 22:58:33.969732
6387 22:58:33.969790 ==
6388 22:58:33.973263 Dram Type= 6, Freq= 0, CH_0, rank 0
6389 22:58:33.979483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6390 22:58:33.979565 ==
6391 22:58:33.979627 RX Vref Scan: 1
6392 22:58:33.979685
6393 22:58:33.983251 RX Vref 0 -> 0, step: 1
6394 22:58:33.983353
6395 22:58:33.986394 RX Delay -359 -> 252, step: 8
6396 22:58:33.986503
6397 22:58:33.989925 Set Vref, RX VrefLevel [Byte0]: 60
6398 22:58:33.992922 [Byte1]: 47
6399 22:58:33.996113
6400 22:58:33.996198 Final RX Vref Byte 0 = 60 to rank0
6401 22:58:33.999743 Final RX Vref Byte 1 = 47 to rank0
6402 22:58:34.002725 Final RX Vref Byte 0 = 60 to rank1
6403 22:58:34.006769 Final RX Vref Byte 1 = 47 to rank1==
6404 22:58:34.009505 Dram Type= 6, Freq= 0, CH_0, rank 0
6405 22:58:34.016434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6406 22:58:34.016536 ==
6407 22:58:34.016618 DQS Delay:
6408 22:58:34.019374 DQS0 = 60, DQS1 = 68
6409 22:58:34.019486 DQM Delay:
6410 22:58:34.019578 DQM0 = 14, DQM1 = 13
6411 22:58:34.022556 DQ Delay:
6412 22:58:34.026148 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =12
6413 22:58:34.029128 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6414 22:58:34.029210 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6415 22:58:34.032892 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6416 22:58:34.035788
6417 22:58:34.035868
6418 22:58:34.042169 [DQSOSCAuto] RK0, (LSB)MR18= 0x7f7f, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6419 22:58:34.045877 CH0 RK0: MR19=C0C, MR18=7F7F
6420 22:58:34.052869 CH0_RK0: MR19=0xC0C, MR18=0x7F7F, DQSOSC=393, MR23=63, INC=382, DEC=254
6421 22:58:34.052953 ==
6422 22:58:34.055775 Dram Type= 6, Freq= 0, CH_0, rank 1
6423 22:58:34.058746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6424 22:58:34.058840 ==
6425 22:58:34.062229 [Gating] SW mode calibration
6426 22:58:34.069240 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6427 22:58:34.075396 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6428 22:58:34.079039 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6429 22:58:34.082203 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6430 22:58:34.088885 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6431 22:58:34.092009 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6432 22:58:34.095634 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6433 22:58:34.101968 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6434 22:58:34.105439 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6435 22:58:34.108545 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6436 22:58:34.114796 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6437 22:58:34.118422 Total UI for P1: 0, mck2ui 16
6438 22:58:34.121396 best dqsien dly found for B0: ( 0, 14, 24)
6439 22:58:34.121504 Total UI for P1: 0, mck2ui 16
6440 22:58:34.127952 best dqsien dly found for B1: ( 0, 14, 24)
6441 22:58:34.131591 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6442 22:58:34.134671 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6443 22:58:34.134773
6444 22:58:34.137842 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6445 22:58:34.141186 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6446 22:58:34.144899 [Gating] SW calibration Done
6447 22:58:34.144989 ==
6448 22:58:34.147875 Dram Type= 6, Freq= 0, CH_0, rank 1
6449 22:58:34.150860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6450 22:58:34.150944 ==
6451 22:58:34.154564 RX Vref Scan: 0
6452 22:58:34.154671
6453 22:58:34.157603 RX Vref 0 -> 0, step: 1
6454 22:58:34.157709
6455 22:58:34.157803 RX Delay -410 -> 252, step: 16
6456 22:58:34.164626 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6457 22:58:34.167922 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6458 22:58:34.170977 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6459 22:58:34.177473 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6460 22:58:34.180713 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6461 22:58:34.184459 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6462 22:58:34.187550 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6463 22:58:34.194137 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6464 22:58:34.197794 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6465 22:58:34.200708 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6466 22:58:34.204464 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6467 22:58:34.210595 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6468 22:58:34.214178 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6469 22:58:34.217178 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6470 22:58:34.220266 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6471 22:58:34.226905 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6472 22:58:34.227093 ==
6473 22:58:34.230366 Dram Type= 6, Freq= 0, CH_0, rank 1
6474 22:58:34.233578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6475 22:58:34.233715 ==
6476 22:58:34.233830 DQS Delay:
6477 22:58:34.237182 DQS0 = 59, DQS1 = 59
6478 22:58:34.237308 DQM Delay:
6479 22:58:34.240438 DQM0 = 16, DQM1 = 10
6480 22:58:34.240565 DQ Delay:
6481 22:58:34.243526 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6482 22:58:34.246625 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6483 22:58:34.250549 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6484 22:58:34.253299 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6485 22:58:34.253409
6486 22:58:34.253503
6487 22:58:34.253599 ==
6488 22:58:34.256902 Dram Type= 6, Freq= 0, CH_0, rank 1
6489 22:58:34.263492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6490 22:58:34.263599 ==
6491 22:58:34.263702
6492 22:58:34.263798
6493 22:58:34.263905 TX Vref Scan disable
6494 22:58:34.266779 == TX Byte 0 ==
6495 22:58:34.269866 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6496 22:58:34.273003 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6497 22:58:34.276602 == TX Byte 1 ==
6498 22:58:34.280015 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6499 22:58:34.282968 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6500 22:58:34.283073 ==
6501 22:58:34.286146 Dram Type= 6, Freq= 0, CH_0, rank 1
6502 22:58:34.292840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6503 22:58:34.292961 ==
6504 22:58:34.293061
6505 22:58:34.293160
6506 22:58:34.293249 TX Vref Scan disable
6507 22:58:34.296479 == TX Byte 0 ==
6508 22:58:34.299701 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6509 22:58:34.302887 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6510 22:58:34.306024 == TX Byte 1 ==
6511 22:58:34.309132 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6512 22:58:34.312796 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6513 22:58:34.312879
6514 22:58:34.315970 [DATLAT]
6515 22:58:34.316053 Freq=400, CH0 RK1
6516 22:58:34.316120
6517 22:58:34.319597 DATLAT Default: 0xe
6518 22:58:34.319679 0, 0xFFFF, sum = 0
6519 22:58:34.322607 1, 0xFFFF, sum = 0
6520 22:58:34.322691 2, 0xFFFF, sum = 0
6521 22:58:34.325762 3, 0xFFFF, sum = 0
6522 22:58:34.325873 4, 0xFFFF, sum = 0
6523 22:58:34.328955 5, 0xFFFF, sum = 0
6524 22:58:34.329039 6, 0xFFFF, sum = 0
6525 22:58:34.332681 7, 0xFFFF, sum = 0
6526 22:58:34.335575 8, 0xFFFF, sum = 0
6527 22:58:34.335678 9, 0xFFFF, sum = 0
6528 22:58:34.339084 10, 0xFFFF, sum = 0
6529 22:58:34.339167 11, 0xFFFF, sum = 0
6530 22:58:34.342144 12, 0xFFFF, sum = 0
6531 22:58:34.342228 13, 0x0, sum = 1
6532 22:58:34.345844 14, 0x0, sum = 2
6533 22:58:34.345928 15, 0x0, sum = 3
6534 22:58:34.348918 16, 0x0, sum = 4
6535 22:58:34.349001 best_step = 14
6536 22:58:34.349067
6537 22:58:34.349127 ==
6538 22:58:34.352625 Dram Type= 6, Freq= 0, CH_0, rank 1
6539 22:58:34.355725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6540 22:58:34.355808 ==
6541 22:58:34.359318 RX Vref Scan: 0
6542 22:58:34.359416
6543 22:58:34.362227 RX Vref 0 -> 0, step: 1
6544 22:58:34.362309
6545 22:58:34.362375 RX Delay -359 -> 252, step: 8
6546 22:58:34.371115 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6547 22:58:34.374340 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6548 22:58:34.377472 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6549 22:58:34.384030 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6550 22:58:34.387562 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6551 22:58:34.390798 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6552 22:58:34.393890 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6553 22:58:34.400687 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6554 22:58:34.403801 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6555 22:58:34.406769 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6556 22:58:34.410613 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6557 22:58:34.416959 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6558 22:58:34.420138 iDelay=217, Bit 12, Center -48 (-295 ~ 200) 496
6559 22:58:34.423271 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6560 22:58:34.430014 iDelay=217, Bit 14, Center -48 (-295 ~ 200) 496
6561 22:58:34.433173 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6562 22:58:34.433267 ==
6563 22:58:34.436431 Dram Type= 6, Freq= 0, CH_0, rank 1
6564 22:58:34.440172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6565 22:58:34.440272 ==
6566 22:58:34.443122 DQS Delay:
6567 22:58:34.443201 DQS0 = 60, DQS1 = 72
6568 22:58:34.443282 DQM Delay:
6569 22:58:34.446624 DQM0 = 11, DQM1 = 16
6570 22:58:34.446736 DQ Delay:
6571 22:58:34.449671 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6572 22:58:34.453397 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6573 22:58:34.456576 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6574 22:58:34.459862 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6575 22:58:34.459961
6576 22:58:34.460040
6577 22:58:34.469557 [DQSOSCAuto] RK1, (LSB)MR18= 0xce83, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6578 22:58:34.469645 CH0 RK1: MR19=C0C, MR18=CE83
6579 22:58:34.475933 CH0_RK1: MR19=0xC0C, MR18=0xCE83, DQSOSC=384, MR23=63, INC=400, DEC=267
6580 22:58:34.479776 [RxdqsGatingPostProcess] freq 400
6581 22:58:34.486091 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6582 22:58:34.489141 best DQS0 dly(2T, 0.5T) = (0, 10)
6583 22:58:34.492667 best DQS1 dly(2T, 0.5T) = (0, 10)
6584 22:58:34.495749 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6585 22:58:34.498699 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6586 22:58:34.502461 best DQS0 dly(2T, 0.5T) = (0, 10)
6587 22:58:34.505601 best DQS1 dly(2T, 0.5T) = (0, 10)
6588 22:58:34.508677 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6589 22:58:34.512268 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6590 22:58:34.512350 Pre-setting of DQS Precalculation
6591 22:58:34.519107 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6592 22:58:34.519189 ==
6593 22:58:34.522236 Dram Type= 6, Freq= 0, CH_1, rank 0
6594 22:58:34.525356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6595 22:58:34.525437 ==
6596 22:58:34.532236 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6597 22:58:34.538460 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6598 22:58:34.541614 [CA 0] Center 36 (8~64) winsize 57
6599 22:58:34.545413 [CA 1] Center 36 (8~64) winsize 57
6600 22:58:34.548400 [CA 2] Center 36 (8~64) winsize 57
6601 22:58:34.551461 [CA 3] Center 36 (8~64) winsize 57
6602 22:58:34.555053 [CA 4] Center 36 (8~64) winsize 57
6603 22:58:34.558066 [CA 5] Center 36 (8~64) winsize 57
6604 22:58:34.558147
6605 22:58:34.561790 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6606 22:58:34.561897
6607 22:58:34.564902 [CATrainingPosCal] consider 1 rank data
6608 22:58:34.567992 u2DelayCellTimex100 = 270/100 ps
6609 22:58:34.571701 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 22:58:34.574634 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 22:58:34.578095 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 22:58:34.581546 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 22:58:34.584639 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 22:58:34.587766 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 22:58:34.587848
6616 22:58:34.594575 CA PerBit enable=1, Macro0, CA PI delay=36
6617 22:58:34.594658
6618 22:58:34.594723 [CBTSetCACLKResult] CA Dly = 36
6619 22:58:34.597685 CS Dly: 1 (0~32)
6620 22:58:34.597766 ==
6621 22:58:34.601467 Dram Type= 6, Freq= 0, CH_1, rank 1
6622 22:58:34.604425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6623 22:58:34.604507 ==
6624 22:58:34.610803 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6625 22:58:34.617643 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6626 22:58:34.620770 [CA 0] Center 36 (8~64) winsize 57
6627 22:58:34.623957 [CA 1] Center 36 (8~64) winsize 57
6628 22:58:34.627615 [CA 2] Center 36 (8~64) winsize 57
6629 22:58:34.630722 [CA 3] Center 36 (8~64) winsize 57
6630 22:58:34.633738 [CA 4] Center 36 (8~64) winsize 57
6631 22:58:34.633819 [CA 5] Center 36 (8~64) winsize 57
6632 22:58:34.637454
6633 22:58:34.640730 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6634 22:58:34.640811
6635 22:58:34.643827 [CATrainingPosCal] consider 2 rank data
6636 22:58:34.646951 u2DelayCellTimex100 = 270/100 ps
6637 22:58:34.650147 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 22:58:34.653647 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 22:58:34.656792 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 22:58:34.660562 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 22:58:34.663666 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 22:58:34.666637 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 22:58:34.666718
6644 22:58:34.670307 CA PerBit enable=1, Macro0, CA PI delay=36
6645 22:58:34.673544
6646 22:58:34.673624 [CBTSetCACLKResult] CA Dly = 36
6647 22:58:34.676731 CS Dly: 1 (0~32)
6648 22:58:34.676812
6649 22:58:34.679892 ----->DramcWriteLeveling(PI) begin...
6650 22:58:34.679979 ==
6651 22:58:34.683400 Dram Type= 6, Freq= 0, CH_1, rank 0
6652 22:58:34.686389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6653 22:58:34.686470 ==
6654 22:58:34.690108 Write leveling (Byte 0): 40 => 8
6655 22:58:34.693166 Write leveling (Byte 1): 40 => 8
6656 22:58:34.696236 DramcWriteLeveling(PI) end<-----
6657 22:58:34.696319
6658 22:58:34.696382 ==
6659 22:58:34.700067 Dram Type= 6, Freq= 0, CH_1, rank 0
6660 22:58:34.703220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6661 22:58:34.706470 ==
6662 22:58:34.706551 [Gating] SW mode calibration
6663 22:58:34.716275 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6664 22:58:34.719293 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6665 22:58:34.722764 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6666 22:58:34.729106 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6667 22:58:34.732682 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6668 22:58:34.735858 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6669 22:58:34.742723 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6670 22:58:34.746002 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6671 22:58:34.749238 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6672 22:58:34.755595 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6673 22:58:34.759227 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6674 22:58:34.762430 Total UI for P1: 0, mck2ui 16
6675 22:58:34.765768 best dqsien dly found for B0: ( 0, 14, 24)
6676 22:58:34.768974 Total UI for P1: 0, mck2ui 16
6677 22:58:34.771962 best dqsien dly found for B1: ( 0, 14, 24)
6678 22:58:34.775554 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6679 22:58:34.778656 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6680 22:58:34.778738
6681 22:58:34.782457 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6682 22:58:34.789053 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6683 22:58:34.789150 [Gating] SW calibration Done
6684 22:58:34.789214 ==
6685 22:58:34.791759 Dram Type= 6, Freq= 0, CH_1, rank 0
6686 22:58:34.798702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6687 22:58:34.798800 ==
6688 22:58:34.798894 RX Vref Scan: 0
6689 22:58:34.798955
6690 22:58:34.801735 RX Vref 0 -> 0, step: 1
6691 22:58:34.801816
6692 22:58:34.804812 RX Delay -410 -> 252, step: 16
6693 22:58:34.808630 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6694 22:58:34.811863 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6695 22:58:34.818558 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6696 22:58:34.821821 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6697 22:58:34.824722 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6698 22:58:34.828482 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6699 22:58:34.834961 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6700 22:58:34.838079 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6701 22:58:34.841211 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6702 22:58:34.844964 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6703 22:58:34.851107 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6704 22:58:34.854802 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6705 22:58:34.857981 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6706 22:58:34.864307 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6707 22:58:34.868034 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6708 22:58:34.871201 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6709 22:58:34.871282 ==
6710 22:58:34.874457 Dram Type= 6, Freq= 0, CH_1, rank 0
6711 22:58:34.877515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6712 22:58:34.881156 ==
6713 22:58:34.881227 DQS Delay:
6714 22:58:34.881289 DQS0 = 43, DQS1 = 67
6715 22:58:34.884324 DQM Delay:
6716 22:58:34.884406 DQM0 = 5, DQM1 = 19
6717 22:58:34.887886 DQ Delay:
6718 22:58:34.887968 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6719 22:58:34.891104 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6720 22:58:34.894304 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6721 22:58:34.897436 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6722 22:58:34.897518
6723 22:58:34.897583
6724 22:58:34.897642 ==
6725 22:58:34.900992 Dram Type= 6, Freq= 0, CH_1, rank 0
6726 22:58:34.907362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6727 22:58:34.907444 ==
6728 22:58:34.907510
6729 22:58:34.907571
6730 22:58:34.907630 TX Vref Scan disable
6731 22:58:34.911028 == TX Byte 0 ==
6732 22:58:34.914121 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6733 22:58:34.917149 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6734 22:58:34.920806 == TX Byte 1 ==
6735 22:58:34.923899 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6736 22:58:34.927183 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6737 22:58:34.930684 ==
6738 22:58:34.933736 Dram Type= 6, Freq= 0, CH_1, rank 0
6739 22:58:34.937431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6740 22:58:34.937512 ==
6741 22:58:34.937575
6742 22:58:34.937634
6743 22:58:34.940533 TX Vref Scan disable
6744 22:58:34.940613 == TX Byte 0 ==
6745 22:58:34.943526 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6746 22:58:34.950430 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6747 22:58:34.950510 == TX Byte 1 ==
6748 22:58:34.953651 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6749 22:58:34.960482 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6750 22:58:34.960563
6751 22:58:34.960626 [DATLAT]
6752 22:58:34.960685 Freq=400, CH1 RK0
6753 22:58:34.960743
6754 22:58:34.963825 DATLAT Default: 0xf
6755 22:58:34.966710 0, 0xFFFF, sum = 0
6756 22:58:34.966792 1, 0xFFFF, sum = 0
6757 22:58:34.970352 2, 0xFFFF, sum = 0
6758 22:58:34.970446 3, 0xFFFF, sum = 0
6759 22:58:34.973471 4, 0xFFFF, sum = 0
6760 22:58:34.973552 5, 0xFFFF, sum = 0
6761 22:58:34.976515 6, 0xFFFF, sum = 0
6762 22:58:34.976595 7, 0xFFFF, sum = 0
6763 22:58:34.980204 8, 0xFFFF, sum = 0
6764 22:58:34.980285 9, 0xFFFF, sum = 0
6765 22:58:34.983370 10, 0xFFFF, sum = 0
6766 22:58:34.983451 11, 0xFFFF, sum = 0
6767 22:58:34.986440 12, 0xFFFF, sum = 0
6768 22:58:34.986521 13, 0x0, sum = 1
6769 22:58:34.990122 14, 0x0, sum = 2
6770 22:58:34.990204 15, 0x0, sum = 3
6771 22:58:34.992981 16, 0x0, sum = 4
6772 22:58:34.993062 best_step = 14
6773 22:58:34.993126
6774 22:58:34.993185 ==
6775 22:58:34.996765 Dram Type= 6, Freq= 0, CH_1, rank 0
6776 22:58:35.003078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6777 22:58:35.003159 ==
6778 22:58:35.003222 RX Vref Scan: 1
6779 22:58:35.003281
6780 22:58:35.006224 RX Vref 0 -> 0, step: 1
6781 22:58:35.006303
6782 22:58:35.009683 RX Delay -375 -> 252, step: 8
6783 22:58:35.009763
6784 22:58:35.013230 Set Vref, RX VrefLevel [Byte0]: 51
6785 22:58:35.016071 [Byte1]: 55
6786 22:58:35.016211
6787 22:58:35.019632 Final RX Vref Byte 0 = 51 to rank0
6788 22:58:35.022698 Final RX Vref Byte 1 = 55 to rank0
6789 22:58:35.026383 Final RX Vref Byte 0 = 51 to rank1
6790 22:58:35.029585 Final RX Vref Byte 1 = 55 to rank1==
6791 22:58:35.032731 Dram Type= 6, Freq= 0, CH_1, rank 0
6792 22:58:35.039473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6793 22:58:35.039554 ==
6794 22:58:35.039618 DQS Delay:
6795 22:58:35.042511 DQS0 = 56, DQS1 = 68
6796 22:58:35.042592 DQM Delay:
6797 22:58:35.042656 DQM0 = 13, DQM1 = 13
6798 22:58:35.046031 DQ Delay:
6799 22:58:35.049033 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =12
6800 22:58:35.052746 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =12
6801 22:58:35.052827 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6802 22:58:35.058917 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6803 22:58:35.058999
6804 22:58:35.059062
6805 22:58:35.065454 [DQSOSCAuto] RK0, (LSB)MR18= 0x586b, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
6806 22:58:35.069195 CH1 RK0: MR19=C0C, MR18=586B
6807 22:58:35.075249 CH1_RK0: MR19=0xC0C, MR18=0x586B, DQSOSC=396, MR23=63, INC=376, DEC=251
6808 22:58:35.075331 ==
6809 22:58:35.078929 Dram Type= 6, Freq= 0, CH_1, rank 1
6810 22:58:35.082104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6811 22:58:35.082186 ==
6812 22:58:35.085259 [Gating] SW mode calibration
6813 22:58:35.092052 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6814 22:58:35.098244 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6815 22:58:35.101912 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
6816 22:58:35.105061 0 11 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
6817 22:58:35.111988 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6818 22:58:35.115087 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6819 22:58:35.118240 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6820 22:58:35.124616 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6821 22:58:35.128019 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6822 22:58:35.131585 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6823 22:58:35.137825 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6824 22:58:35.141448 Total UI for P1: 0, mck2ui 16
6825 22:58:35.144620 best dqsien dly found for B0: ( 0, 14, 24)
6826 22:58:35.148237 Total UI for P1: 0, mck2ui 16
6827 22:58:35.151103 best dqsien dly found for B1: ( 0, 14, 24)
6828 22:58:35.154631 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6829 22:58:35.157702 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6830 22:58:35.157783
6831 22:58:35.160792 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6832 22:58:35.164622 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6833 22:58:35.167922 [Gating] SW calibration Done
6834 22:58:35.168002 ==
6835 22:58:35.171074 Dram Type= 6, Freq= 0, CH_1, rank 1
6836 22:58:35.174113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6837 22:58:35.174195 ==
6838 22:58:35.177712 RX Vref Scan: 0
6839 22:58:35.177792
6840 22:58:35.180788 RX Vref 0 -> 0, step: 1
6841 22:58:35.180869
6842 22:58:35.180933 RX Delay -410 -> 252, step: 16
6843 22:58:35.187887 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6844 22:58:35.191214 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6845 22:58:35.194126 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6846 22:58:35.200979 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6847 22:58:35.204044 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6848 22:58:35.207626 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6849 22:58:35.210708 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6850 22:58:35.217504 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6851 22:58:35.220664 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6852 22:58:35.223809 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6853 22:58:35.227095 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6854 22:58:35.233484 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6855 22:58:35.237356 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6856 22:58:35.240410 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6857 22:58:35.243513 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6858 22:58:35.250405 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6859 22:58:35.250487 ==
6860 22:58:35.253518 Dram Type= 6, Freq= 0, CH_1, rank 1
6861 22:58:35.256530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6862 22:58:35.256612 ==
6863 22:58:35.260031 DQS Delay:
6864 22:58:35.260112 DQS0 = 59, DQS1 = 67
6865 22:58:35.260176 DQM Delay:
6866 22:58:35.263448 DQM0 = 20, DQM1 = 21
6867 22:58:35.263544 DQ Delay:
6868 22:58:35.266465 DQ0 =32, DQ1 =16, DQ2 =0, DQ3 =16
6869 22:58:35.269608 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6870 22:58:35.273331 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6871 22:58:35.276434 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6872 22:58:35.276515
6873 22:58:35.276579
6874 22:58:35.276638 ==
6875 22:58:35.279676 Dram Type= 6, Freq= 0, CH_1, rank 1
6876 22:58:35.286365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6877 22:58:35.286462 ==
6878 22:58:35.286542
6879 22:58:35.286603
6880 22:58:35.286661 TX Vref Scan disable
6881 22:58:35.289401 == TX Byte 0 ==
6882 22:58:35.293196 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6883 22:58:35.296310 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6884 22:58:35.299479 == TX Byte 1 ==
6885 22:58:35.302627 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6886 22:58:35.306496 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6887 22:58:35.306578 ==
6888 22:58:35.309639 Dram Type= 6, Freq= 0, CH_1, rank 1
6889 22:58:35.316419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6890 22:58:35.316530 ==
6891 22:58:35.316630
6892 22:58:35.316724
6893 22:58:35.316831 TX Vref Scan disable
6894 22:58:35.319655 == TX Byte 0 ==
6895 22:58:35.322627 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6896 22:58:35.325704 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6897 22:58:35.329069 == TX Byte 1 ==
6898 22:58:35.332898 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6899 22:58:35.336040 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6900 22:58:35.336144
6901 22:58:35.339039 [DATLAT]
6902 22:58:35.339136 Freq=400, CH1 RK1
6903 22:58:35.339231
6904 22:58:35.342093 DATLAT Default: 0xe
6905 22:58:35.342188 0, 0xFFFF, sum = 0
6906 22:58:35.345794 1, 0xFFFF, sum = 0
6907 22:58:35.345898 2, 0xFFFF, sum = 0
6908 22:58:35.348750 3, 0xFFFF, sum = 0
6909 22:58:35.348857 4, 0xFFFF, sum = 0
6910 22:58:35.352649 5, 0xFFFF, sum = 0
6911 22:58:35.352749 6, 0xFFFF, sum = 0
6912 22:58:35.355280 7, 0xFFFF, sum = 0
6913 22:58:35.359030 8, 0xFFFF, sum = 0
6914 22:58:35.359133 9, 0xFFFF, sum = 0
6915 22:58:35.362023 10, 0xFFFF, sum = 0
6916 22:58:35.362121 11, 0xFFFF, sum = 0
6917 22:58:35.365715 12, 0xFFFF, sum = 0
6918 22:58:35.365817 13, 0x0, sum = 1
6919 22:58:35.368753 14, 0x0, sum = 2
6920 22:58:35.368857 15, 0x0, sum = 3
6921 22:58:35.371761 16, 0x0, sum = 4
6922 22:58:35.371868 best_step = 14
6923 22:58:35.371976
6924 22:58:35.372068 ==
6925 22:58:35.375437 Dram Type= 6, Freq= 0, CH_1, rank 1
6926 22:58:35.378594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6927 22:58:35.381833 ==
6928 22:58:35.381937 RX Vref Scan: 0
6929 22:58:35.382028
6930 22:58:35.384994 RX Vref 0 -> 0, step: 1
6931 22:58:35.385095
6932 22:58:35.388096 RX Delay -375 -> 252, step: 8
6933 22:58:35.394942 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6934 22:58:35.398077 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6935 22:58:35.401746 iDelay=217, Bit 2, Center -56 (-303 ~ 192) 496
6936 22:58:35.404842 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6937 22:58:35.411609 iDelay=217, Bit 4, Center -44 (-295 ~ 208) 504
6938 22:58:35.414727 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6939 22:58:35.417866 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6940 22:58:35.421444 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6941 22:58:35.427588 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6942 22:58:35.431218 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6943 22:58:35.434421 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6944 22:58:35.437609 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6945 22:58:35.444458 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6946 22:58:35.447642 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6947 22:58:35.450802 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6948 22:58:35.457818 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6949 22:58:35.457902 ==
6950 22:58:35.461076 Dram Type= 6, Freq= 0, CH_1, rank 1
6951 22:58:35.463991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6952 22:58:35.464072 ==
6953 22:58:35.464137 DQS Delay:
6954 22:58:35.467079 DQS0 = 56, DQS1 = 64
6955 22:58:35.467193 DQM Delay:
6956 22:58:35.470299 DQM0 = 9, DQM1 = 10
6957 22:58:35.470372 DQ Delay:
6958 22:58:35.474071 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6959 22:58:35.477022 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =4
6960 22:58:35.480748 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6961 22:58:35.483799 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6962 22:58:35.483879
6963 22:58:35.483973
6964 22:58:35.490092 [DQSOSCAuto] RK1, (LSB)MR18= 0x7dae, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
6965 22:58:35.493792 CH1 RK1: MR19=C0C, MR18=7DAE
6966 22:58:35.500122 CH1_RK1: MR19=0xC0C, MR18=0x7DAE, DQSOSC=388, MR23=63, INC=392, DEC=261
6967 22:58:35.503385 [RxdqsGatingPostProcess] freq 400
6968 22:58:35.510000 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6969 22:58:35.513320 best DQS0 dly(2T, 0.5T) = (0, 10)
6970 22:58:35.516304 best DQS1 dly(2T, 0.5T) = (0, 10)
6971 22:58:35.519978 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6972 22:58:35.523167 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6973 22:58:35.523251 best DQS0 dly(2T, 0.5T) = (0, 10)
6974 22:58:35.526200 best DQS1 dly(2T, 0.5T) = (0, 10)
6975 22:58:35.529830 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6976 22:58:35.532855 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6977 22:58:35.536144 Pre-setting of DQS Precalculation
6978 22:58:35.542463 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6979 22:58:35.549244 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6980 22:58:35.556061 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6981 22:58:35.556148
6982 22:58:35.556243
6983 22:58:35.559257 [Calibration Summary] 800 Mbps
6984 22:58:35.559351 CH 0, Rank 0
6985 22:58:35.562307 SW Impedance : PASS
6986 22:58:35.566085 DUTY Scan : NO K
6987 22:58:35.566167 ZQ Calibration : PASS
6988 22:58:35.568901 Jitter Meter : NO K
6989 22:58:35.572459 CBT Training : PASS
6990 22:58:35.572548 Write leveling : PASS
6991 22:58:35.575545 RX DQS gating : PASS
6992 22:58:35.579241 RX DQ/DQS(RDDQC) : PASS
6993 22:58:35.579332 TX DQ/DQS : PASS
6994 22:58:35.582377 RX DATLAT : PASS
6995 22:58:35.585661 RX DQ/DQS(Engine): PASS
6996 22:58:35.585767 TX OE : NO K
6997 22:58:35.588514 All Pass.
6998 22:58:35.588606
6999 22:58:35.588672 CH 0, Rank 1
7000 22:58:35.592175 SW Impedance : PASS
7001 22:58:35.592255 DUTY Scan : NO K
7002 22:58:35.595167 ZQ Calibration : PASS
7003 22:58:35.598424 Jitter Meter : NO K
7004 22:58:35.598526 CBT Training : PASS
7005 22:58:35.602195 Write leveling : NO K
7006 22:58:35.605344 RX DQS gating : PASS
7007 22:58:35.605434 RX DQ/DQS(RDDQC) : PASS
7008 22:58:35.608565 TX DQ/DQS : PASS
7009 22:58:35.611883 RX DATLAT : PASS
7010 22:58:35.611970 RX DQ/DQS(Engine): PASS
7011 22:58:35.615010 TX OE : NO K
7012 22:58:35.615089 All Pass.
7013 22:58:35.615186
7014 22:58:35.618149 CH 1, Rank 0
7015 22:58:35.618244 SW Impedance : PASS
7016 22:58:35.621344 DUTY Scan : NO K
7017 22:58:35.624685 ZQ Calibration : PASS
7018 22:58:35.624790 Jitter Meter : NO K
7019 22:58:35.628351 CBT Training : PASS
7020 22:58:35.631558 Write leveling : PASS
7021 22:58:35.631654 RX DQS gating : PASS
7022 22:58:35.635005 RX DQ/DQS(RDDQC) : PASS
7023 22:58:35.638072 TX DQ/DQS : PASS
7024 22:58:35.638183 RX DATLAT : PASS
7025 22:58:35.641241 RX DQ/DQS(Engine): PASS
7026 22:58:35.644483 TX OE : NO K
7027 22:58:35.644564 All Pass.
7028 22:58:35.644665
7029 22:58:35.644750 CH 1, Rank 1
7030 22:58:35.648289 SW Impedance : PASS
7031 22:58:35.651313 DUTY Scan : NO K
7032 22:58:35.651419 ZQ Calibration : PASS
7033 22:58:35.654312 Jitter Meter : NO K
7034 22:58:35.654437 CBT Training : PASS
7035 22:58:35.658120 Write leveling : NO K
7036 22:58:35.661239 RX DQS gating : PASS
7037 22:58:35.661320 RX DQ/DQS(RDDQC) : PASS
7038 22:58:35.664383 TX DQ/DQS : PASS
7039 22:58:35.667540 RX DATLAT : PASS
7040 22:58:35.667620 RX DQ/DQS(Engine): PASS
7041 22:58:35.671337 TX OE : NO K
7042 22:58:35.671418 All Pass.
7043 22:58:35.671524
7044 22:58:35.674312 DramC Write-DBI off
7045 22:58:35.677865 PER_BANK_REFRESH: Hybrid Mode
7046 22:58:35.677945 TX_TRACKING: ON
7047 22:58:35.687322 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7048 22:58:35.691129 [FAST_K] Save calibration result to emmc
7049 22:58:35.694112 dramc_set_vcore_voltage set vcore to 725000
7050 22:58:35.697641 Read voltage for 1600, 0
7051 22:58:35.697755 Vio18 = 0
7052 22:58:35.700696 Vcore = 725000
7053 22:58:35.700799 Vdram = 0
7054 22:58:35.700899 Vddq = 0
7055 22:58:35.700989 Vmddr = 0
7056 22:58:35.707485 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7057 22:58:35.713754 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7058 22:58:35.713869 MEM_TYPE=3, freq_sel=13
7059 22:58:35.716994 sv_algorithm_assistance_LP4_3733
7060 22:58:35.720900 ============ PULL DRAM RESETB DOWN ============
7061 22:58:35.727175 ========== PULL DRAM RESETB DOWN end =========
7062 22:58:35.730296 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7063 22:58:35.733396 ===================================
7064 22:58:35.737150 LPDDR4 DRAM CONFIGURATION
7065 22:58:35.739964 ===================================
7066 22:58:35.740048 EX_ROW_EN[0] = 0x0
7067 22:58:35.743599 EX_ROW_EN[1] = 0x0
7068 22:58:35.743682 LP4Y_EN = 0x0
7069 22:58:35.746517 WORK_FSP = 0x1
7070 22:58:35.750345 WL = 0x5
7071 22:58:35.750430 RL = 0x5
7072 22:58:35.753485 BL = 0x2
7073 22:58:35.753597 RPST = 0x0
7074 22:58:35.756472 RD_PRE = 0x0
7075 22:58:35.756607 WR_PRE = 0x1
7076 22:58:35.760042 WR_PST = 0x1
7077 22:58:35.760160 DBI_WR = 0x0
7078 22:58:35.763088 DBI_RD = 0x0
7079 22:58:35.763208 OTF = 0x1
7080 22:58:35.766211 ===================================
7081 22:58:35.770083 ===================================
7082 22:58:35.773221 ANA top config
7083 22:58:35.776405 ===================================
7084 22:58:35.776490 DLL_ASYNC_EN = 0
7085 22:58:35.780063 ALL_SLAVE_EN = 0
7086 22:58:35.783477 NEW_RANK_MODE = 1
7087 22:58:35.786407 DLL_IDLE_MODE = 1
7088 22:58:35.789917 LP45_APHY_COMB_EN = 1
7089 22:58:35.790009 TX_ODT_DIS = 0
7090 22:58:35.792782 NEW_8X_MODE = 1
7091 22:58:35.796562 ===================================
7092 22:58:35.799491 ===================================
7093 22:58:35.802607 data_rate = 3200
7094 22:58:35.806391 CKR = 1
7095 22:58:35.809550 DQ_P2S_RATIO = 8
7096 22:58:35.813228 ===================================
7097 22:58:35.816341 CA_P2S_RATIO = 8
7098 22:58:35.816433 DQ_CA_OPEN = 0
7099 22:58:35.819545 DQ_SEMI_OPEN = 0
7100 22:58:35.822728 CA_SEMI_OPEN = 0
7101 22:58:35.825923 CA_FULL_RATE = 0
7102 22:58:35.828988 DQ_CKDIV4_EN = 0
7103 22:58:35.832165 CA_CKDIV4_EN = 0
7104 22:58:35.832246 CA_PREDIV_EN = 0
7105 22:58:35.835979 PH8_DLY = 12
7106 22:58:35.839096 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7107 22:58:35.842201 DQ_AAMCK_DIV = 4
7108 22:58:35.845741 CA_AAMCK_DIV = 4
7109 22:58:35.848733 CA_ADMCK_DIV = 4
7110 22:58:35.848812 DQ_TRACK_CA_EN = 0
7111 22:58:35.851965 CA_PICK = 1600
7112 22:58:35.855691 CA_MCKIO = 1600
7113 22:58:35.858776 MCKIO_SEMI = 0
7114 22:58:35.862658 PLL_FREQ = 3068
7115 22:58:35.865326 DQ_UI_PI_RATIO = 32
7116 22:58:35.869120 CA_UI_PI_RATIO = 0
7117 22:58:35.872257 ===================================
7118 22:58:35.875460 ===================================
7119 22:58:35.875539 memory_type:LPDDR4
7120 22:58:35.878576 GP_NUM : 10
7121 22:58:35.881604 SRAM_EN : 1
7122 22:58:35.881681 MD32_EN : 0
7123 22:58:35.885239 ===================================
7124 22:58:35.888380 [ANA_INIT] >>>>>>>>>>>>>>
7125 22:58:35.891522 <<<<<< [CONFIGURE PHASE]: ANA_TX
7126 22:58:35.895138 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7127 22:58:35.898199 ===================================
7128 22:58:35.901934 data_rate = 3200,PCW = 0X7600
7129 22:58:35.904920 ===================================
7130 22:58:35.908567 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7131 22:58:35.911598 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7132 22:58:35.918092 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7133 22:58:35.924943 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7134 22:58:35.927947 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7135 22:58:35.931106 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7136 22:58:35.931203 [ANA_INIT] flow start
7137 22:58:35.934893 [ANA_INIT] PLL >>>>>>>>
7138 22:58:35.938064 [ANA_INIT] PLL <<<<<<<<
7139 22:58:35.938142 [ANA_INIT] MIDPI >>>>>>>>
7140 22:58:35.941212 [ANA_INIT] MIDPI <<<<<<<<
7141 22:58:35.944345 [ANA_INIT] DLL >>>>>>>>
7142 22:58:35.944438 [ANA_INIT] DLL <<<<<<<<
7143 22:58:35.948098 [ANA_INIT] flow end
7144 22:58:35.951090 ============ LP4 DIFF to SE enter ============
7145 22:58:35.957636 ============ LP4 DIFF to SE exit ============
7146 22:58:35.957731 [ANA_INIT] <<<<<<<<<<<<<
7147 22:58:35.960746 [Flow] Enable top DCM control >>>>>
7148 22:58:35.963976 [Flow] Enable top DCM control <<<<<
7149 22:58:35.967503 Enable DLL master slave shuffle
7150 22:58:35.974203 ==============================================================
7151 22:58:35.974287 Gating Mode config
7152 22:58:35.980540 ==============================================================
7153 22:58:35.983659 Config description:
7154 22:58:35.993468 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7155 22:58:36.000140 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7156 22:58:36.003828 SELPH_MODE 0: By rank 1: By Phase
7157 22:58:36.010487 ==============================================================
7158 22:58:36.013603 GAT_TRACK_EN = 1
7159 22:58:36.016982 RX_GATING_MODE = 2
7160 22:58:36.017087 RX_GATING_TRACK_MODE = 2
7161 22:58:36.020027 SELPH_MODE = 1
7162 22:58:36.023568 PICG_EARLY_EN = 1
7163 22:58:36.026756 VALID_LAT_VALUE = 1
7164 22:58:36.033486 ==============================================================
7165 22:58:36.036372 Enter into Gating configuration >>>>
7166 22:58:36.040162 Exit from Gating configuration <<<<
7167 22:58:36.043115 Enter into DVFS_PRE_config >>>>>
7168 22:58:36.053337 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7169 22:58:36.056376 Exit from DVFS_PRE_config <<<<<
7170 22:58:36.059906 Enter into PICG configuration >>>>
7171 22:58:36.062838 Exit from PICG configuration <<<<
7172 22:58:36.066433 [RX_INPUT] configuration >>>>>
7173 22:58:36.069662 [RX_INPUT] configuration <<<<<
7174 22:58:36.073164 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7175 22:58:36.079407 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7176 22:58:36.086411 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7177 22:58:36.092596 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7178 22:58:36.099056 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7179 22:58:36.102602 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7180 22:58:36.109225 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7181 22:58:36.112346 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7182 22:58:36.115580 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7183 22:58:36.118613 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7184 22:58:36.125834 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7185 22:58:36.128579 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7186 22:58:36.132048 ===================================
7187 22:58:36.135555 LPDDR4 DRAM CONFIGURATION
7188 22:58:36.138870 ===================================
7189 22:58:36.138983 EX_ROW_EN[0] = 0x0
7190 22:58:36.142344 EX_ROW_EN[1] = 0x0
7191 22:58:36.142458 LP4Y_EN = 0x0
7192 22:58:36.145527 WORK_FSP = 0x1
7193 22:58:36.145636 WL = 0x5
7194 22:58:36.148713 RL = 0x5
7195 22:58:36.151979 BL = 0x2
7196 22:58:36.152088 RPST = 0x0
7197 22:58:36.155100 RD_PRE = 0x0
7198 22:58:36.155216 WR_PRE = 0x1
7199 22:58:36.158234 WR_PST = 0x1
7200 22:58:36.158355 DBI_WR = 0x0
7201 22:58:36.161929 DBI_RD = 0x0
7202 22:58:36.162049 OTF = 0x1
7203 22:58:36.165133 ===================================
7204 22:58:36.168297 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7205 22:58:36.175132 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7206 22:58:36.178594 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7207 22:58:36.181613 ===================================
7208 22:58:36.184814 LPDDR4 DRAM CONFIGURATION
7209 22:58:36.188044 ===================================
7210 22:58:36.188128 EX_ROW_EN[0] = 0x10
7211 22:58:36.191841 EX_ROW_EN[1] = 0x0
7212 22:58:36.191924 LP4Y_EN = 0x0
7213 22:58:36.195095 WORK_FSP = 0x1
7214 22:58:36.195177 WL = 0x5
7215 22:58:36.198278 RL = 0x5
7216 22:58:36.201565 BL = 0x2
7217 22:58:36.201648 RPST = 0x0
7218 22:58:36.204506 RD_PRE = 0x0
7219 22:58:36.204589 WR_PRE = 0x1
7220 22:58:36.208319 WR_PST = 0x1
7221 22:58:36.208402 DBI_WR = 0x0
7222 22:58:36.211346 DBI_RD = 0x0
7223 22:58:36.211428 OTF = 0x1
7224 22:58:36.214515 ===================================
7225 22:58:36.221262 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7226 22:58:36.221346 ==
7227 22:58:36.224529 Dram Type= 6, Freq= 0, CH_0, rank 0
7228 22:58:36.227673 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7229 22:58:36.227802 ==
7230 22:58:36.231363 [Duty_Offset_Calibration]
7231 22:58:36.234328 B0:2 B1:0 CA:3
7232 22:58:36.234411
7233 22:58:36.237862 [DutyScan_Calibration_Flow] k_type=0
7234 22:58:36.246024
7235 22:58:36.246138 ==CLK 0==
7236 22:58:36.249703 Final CLK duty delay cell = 0
7237 22:58:36.252754 [0] MAX Duty = 5031%(X100), DQS PI = 12
7238 22:58:36.255945 [0] MIN Duty = 4875%(X100), DQS PI = 58
7239 22:58:36.259669 [0] AVG Duty = 4953%(X100)
7240 22:58:36.259752
7241 22:58:36.262717 CH0 CLK Duty spec in!! Max-Min= 156%
7242 22:58:36.266027 [DutyScan_Calibration_Flow] ====Done====
7243 22:58:36.266110
7244 22:58:36.269147 [DutyScan_Calibration_Flow] k_type=1
7245 22:58:36.285879
7246 22:58:36.286031 ==DQS 0 ==
7247 22:58:36.289513 Final DQS duty delay cell = 0
7248 22:58:36.292726 [0] MAX Duty = 5094%(X100), DQS PI = 14
7249 22:58:36.296004 [0] MIN Duty = 4875%(X100), DQS PI = 48
7250 22:58:36.299195 [0] AVG Duty = 4984%(X100)
7251 22:58:36.299280
7252 22:58:36.299346 ==DQS 1 ==
7253 22:58:36.302315 Final DQS duty delay cell = 0
7254 22:58:36.305991 [0] MAX Duty = 5156%(X100), DQS PI = 32
7255 22:58:36.309196 [0] MIN Duty = 5062%(X100), DQS PI = 0
7256 22:58:36.312840 [0] AVG Duty = 5109%(X100)
7257 22:58:36.312954
7258 22:58:36.316013 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7259 22:58:36.316128
7260 22:58:36.319084 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7261 22:58:36.322688 [DutyScan_Calibration_Flow] ====Done====
7262 22:58:36.322771
7263 22:58:36.325859 [DutyScan_Calibration_Flow] k_type=3
7264 22:58:36.343693
7265 22:58:36.343816 ==DQM 0 ==
7266 22:58:36.347197 Final DQM duty delay cell = 0
7267 22:58:36.350197 [0] MAX Duty = 5156%(X100), DQS PI = 30
7268 22:58:36.353858 [0] MIN Duty = 4875%(X100), DQS PI = 0
7269 22:58:36.356688 [0] AVG Duty = 5015%(X100)
7270 22:58:36.356794
7271 22:58:36.356892 ==DQM 1 ==
7272 22:58:36.360539 Final DQM duty delay cell = 4
7273 22:58:36.363669 [4] MAX Duty = 5187%(X100), DQS PI = 62
7274 22:58:36.366823 [4] MIN Duty = 5031%(X100), DQS PI = 14
7275 22:58:36.370175 [4] AVG Duty = 5109%(X100)
7276 22:58:36.370287
7277 22:58:36.373863 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7278 22:58:36.373965
7279 22:58:36.376889 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7280 22:58:36.379997 [DutyScan_Calibration_Flow] ====Done====
7281 22:58:36.380096
7282 22:58:36.383170 [DutyScan_Calibration_Flow] k_type=2
7283 22:58:36.399961
7284 22:58:36.400099 ==DQ 0 ==
7285 22:58:36.403167 Final DQ duty delay cell = -4
7286 22:58:36.406844 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7287 22:58:36.409854 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7288 22:58:36.412889 [-4] AVG Duty = 4938%(X100)
7289 22:58:36.412962
7290 22:58:36.413026 ==DQ 1 ==
7291 22:58:36.416725 Final DQ duty delay cell = 0
7292 22:58:36.419690 [0] MAX Duty = 5156%(X100), DQS PI = 58
7293 22:58:36.422864 [0] MIN Duty = 5000%(X100), DQS PI = 16
7294 22:58:36.426070 [0] AVG Duty = 5078%(X100)
7295 22:58:36.426152
7296 22:58:36.429875 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7297 22:58:36.429956
7298 22:58:36.433073 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7299 22:58:36.436172 [DutyScan_Calibration_Flow] ====Done====
7300 22:58:36.436253 ==
7301 22:58:36.439416 Dram Type= 6, Freq= 0, CH_1, rank 0
7302 22:58:36.442569 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7303 22:58:36.442676 ==
7304 22:58:36.446296 [Duty_Offset_Calibration]
7305 22:58:36.446377 B0:1 B1:-2 CA:0
7306 22:58:36.449357
7307 22:58:36.452355 [DutyScan_Calibration_Flow] k_type=0
7308 22:58:36.460289
7309 22:58:36.460373 ==CLK 0==
7310 22:58:36.463902 Final CLK duty delay cell = 0
7311 22:58:36.467022 [0] MAX Duty = 5031%(X100), DQS PI = 52
7312 22:58:36.470633 [0] MIN Duty = 4876%(X100), DQS PI = 10
7313 22:58:36.473745 [0] AVG Duty = 4953%(X100)
7314 22:58:36.473826
7315 22:58:36.476838 CH1 CLK Duty spec in!! Max-Min= 155%
7316 22:58:36.480057 [DutyScan_Calibration_Flow] ====Done====
7317 22:58:36.480138
7318 22:58:36.483225 [DutyScan_Calibration_Flow] k_type=1
7319 22:58:36.500186
7320 22:58:36.500295 ==DQS 0 ==
7321 22:58:36.503650 Final DQS duty delay cell = 0
7322 22:58:36.506791 [0] MAX Duty = 5156%(X100), DQS PI = 0
7323 22:58:36.510020 [0] MIN Duty = 5093%(X100), DQS PI = 6
7324 22:58:36.510101 [0] AVG Duty = 5124%(X100)
7325 22:58:36.513192
7326 22:58:36.513273 ==DQS 1 ==
7327 22:58:36.516558 Final DQS duty delay cell = 0
7328 22:58:36.519671 [0] MAX Duty = 5124%(X100), DQS PI = 30
7329 22:58:36.523369 [0] MIN Duty = 4844%(X100), DQS PI = 56
7330 22:58:36.526474 [0] AVG Duty = 4984%(X100)
7331 22:58:36.526557
7332 22:58:36.529583 CH1 DQS 0 Duty spec in!! Max-Min= 63%
7333 22:58:36.529664
7334 22:58:36.533376 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7335 22:58:36.536495 [DutyScan_Calibration_Flow] ====Done====
7336 22:58:36.536578
7337 22:58:36.539441 [DutyScan_Calibration_Flow] k_type=3
7338 22:58:36.556794
7339 22:58:36.556884 ==DQM 0 ==
7340 22:58:36.560039 Final DQM duty delay cell = 0
7341 22:58:36.563052 [0] MAX Duty = 5031%(X100), DQS PI = 58
7342 22:58:36.566542 [0] MIN Duty = 4844%(X100), DQS PI = 22
7343 22:58:36.570260 [0] AVG Duty = 4937%(X100)
7344 22:58:36.570341
7345 22:58:36.570416 ==DQM 1 ==
7346 22:58:36.572911 Final DQM duty delay cell = 0
7347 22:58:36.576571 [0] MAX Duty = 5062%(X100), DQS PI = 4
7348 22:58:36.579490 [0] MIN Duty = 4875%(X100), DQS PI = 38
7349 22:58:36.582638 [0] AVG Duty = 4968%(X100)
7350 22:58:36.582742
7351 22:58:36.586432 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7352 22:58:36.586552
7353 22:58:36.589630 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7354 22:58:36.592847 [DutyScan_Calibration_Flow] ====Done====
7355 22:58:36.592964
7356 22:58:36.596017 [DutyScan_Calibration_Flow] k_type=2
7357 22:58:36.613261
7358 22:58:36.613373 ==DQ 0 ==
7359 22:58:36.616983 Final DQ duty delay cell = 0
7360 22:58:36.620184 [0] MAX Duty = 5062%(X100), DQS PI = 0
7361 22:58:36.623111 [0] MIN Duty = 4938%(X100), DQS PI = 14
7362 22:58:36.623231 [0] AVG Duty = 5000%(X100)
7363 22:58:36.626708
7364 22:58:36.626815 ==DQ 1 ==
7365 22:58:36.629731 Final DQ duty delay cell = 0
7366 22:58:36.633183 [0] MAX Duty = 5156%(X100), DQS PI = 26
7367 22:58:36.636187 [0] MIN Duty = 4907%(X100), DQS PI = 56
7368 22:58:36.636298 [0] AVG Duty = 5031%(X100)
7369 22:58:36.640062
7370 22:58:36.643117 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7371 22:58:36.643225
7372 22:58:36.646271 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7373 22:58:36.649952 [DutyScan_Calibration_Flow] ====Done====
7374 22:58:36.653038 nWR fixed to 30
7375 22:58:36.656016 [ModeRegInit_LP4] CH0 RK0
7376 22:58:36.656127 [ModeRegInit_LP4] CH0 RK1
7377 22:58:36.659317 [ModeRegInit_LP4] CH1 RK0
7378 22:58:36.663028 [ModeRegInit_LP4] CH1 RK1
7379 22:58:36.663111 match AC timing 5
7380 22:58:36.669204 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7381 22:58:36.672802 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7382 22:58:36.675786 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7383 22:58:36.682335 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7384 22:58:36.685475 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7385 22:58:36.685563 [MiockJmeterHQA]
7386 22:58:36.685630
7387 22:58:36.689052 [DramcMiockJmeter] u1RxGatingPI = 0
7388 22:58:36.692226 0 : 4260, 4031
7389 22:58:36.692299 4 : 4255, 4029
7390 22:58:36.695292 8 : 4257, 4029
7391 22:58:36.695364 12 : 4255, 4029
7392 22:58:36.699038 16 : 4257, 4030
7393 22:58:36.699132 20 : 4257, 4029
7394 22:58:36.699200 24 : 4258, 4031
7395 22:58:36.702294 28 : 4257, 4029
7396 22:58:36.702366 32 : 4254, 4029
7397 22:58:36.705767 36 : 4370, 4142
7398 22:58:36.705846 40 : 4368, 4140
7399 22:58:36.708969 44 : 4368, 4140
7400 22:58:36.709055 48 : 4368, 4140
7401 22:58:36.712089 52 : 4368, 4140
7402 22:58:36.712196 56 : 4250, 4024
7403 22:58:36.715083 60 : 4255, 4029
7404 22:58:36.715158 64 : 4252, 4029
7405 22:58:36.715229 68 : 4365, 4140
7406 22:58:36.718751 72 : 4253, 4029
7407 22:58:36.718861 76 : 4255, 4029
7408 22:58:36.721827 80 : 4252, 4029
7409 22:58:36.721938 84 : 4257, 4032
7410 22:58:36.725367 88 : 4365, 4140
7411 22:58:36.725467 92 : 4253, 4029
7412 22:58:36.725548 96 : 4254, 4029
7413 22:58:36.728345 100 : 4252, 4029
7414 22:58:36.728444 104 : 4255, 3588
7415 22:58:36.731847 108 : 4252, 3
7416 22:58:36.731933 112 : 4250, 0
7417 22:58:36.734842 116 : 4252, 0
7418 22:58:36.734947 120 : 4252, 0
7419 22:58:36.735014 124 : 4363, 0
7420 22:58:36.738761 128 : 4252, 0
7421 22:58:36.738876 132 : 4253, 0
7422 22:58:36.742007 136 : 4253, 0
7423 22:58:36.742117 140 : 4252, 0
7424 22:58:36.742216 144 : 4258, 0
7425 22:58:36.745220 148 : 4253, 0
7426 22:58:36.745325 152 : 4253, 0
7427 22:58:36.748364 156 : 4252, 0
7428 22:58:36.748475 160 : 4257, 0
7429 22:58:36.748570 164 : 4253, 0
7430 22:58:36.751568 168 : 4252, 0
7431 22:58:36.751653 172 : 4252, 0
7432 22:58:36.751720 176 : 4253, 0
7433 22:58:36.755310 180 : 4252, 0
7434 22:58:36.755394 184 : 4257, 0
7435 22:58:36.758380 188 : 4363, 0
7436 22:58:36.758464 192 : 4252, 0
7437 22:58:36.758531 196 : 4255, 0
7438 22:58:36.761467 200 : 4250, 0
7439 22:58:36.761551 204 : 4253, 0
7440 22:58:36.765123 208 : 4255, 0
7441 22:58:36.765208 212 : 4250, 0
7442 22:58:36.765275 216 : 4252, 0
7443 22:58:36.768397 220 : 4252, 0
7444 22:58:36.768481 224 : 4252, 0
7445 22:58:36.771510 228 : 4362, 0
7446 22:58:36.771594 232 : 4363, 0
7447 22:58:36.771662 236 : 4368, 1277
7448 22:58:36.774757 240 : 4252, 4030
7449 22:58:36.774849 244 : 4363, 4139
7450 22:58:36.777966 248 : 4253, 4029
7451 22:58:36.778071 252 : 4255, 4029
7452 22:58:36.780971 256 : 4255, 4029
7453 22:58:36.781055 260 : 4252, 4029
7454 22:58:36.784633 264 : 4253, 4029
7455 22:58:36.784718 268 : 4255, 4031
7456 22:58:36.787890 272 : 4255, 4029
7457 22:58:36.787974 276 : 4255, 4029
7458 22:58:36.791310 280 : 4252, 4029
7459 22:58:36.791398 284 : 4363, 4140
7460 22:58:36.794288 288 : 4255, 4029
7461 22:58:36.794371 292 : 4252, 4030
7462 22:58:36.797788 296 : 4363, 4140
7463 22:58:36.797874 300 : 4250, 4027
7464 22:58:36.797941 304 : 4253, 4029
7465 22:58:36.801097 308 : 4255, 4029
7466 22:58:36.801182 312 : 4254, 4030
7467 22:58:36.804134 316 : 4252, 4029
7468 22:58:36.804218 320 : 4257, 4032
7469 22:58:36.807897 324 : 4252, 4027
7470 22:58:36.807982 328 : 4254, 4030
7471 22:58:36.811041 332 : 4253, 4029
7472 22:58:36.811124 336 : 4253, 4029
7473 22:58:36.814165 340 : 4368, 4142
7474 22:58:36.814249 344 : 4255, 4029
7475 22:58:36.817822 348 : 4254, 4030
7476 22:58:36.817937 352 : 4253, 4006
7477 22:58:36.820655 356 : 4258, 2683
7478 22:58:36.820764 360 : 4255, 1
7479 22:58:36.820861
7480 22:58:36.823762 MIOCK jitter meter ch=0
7481 22:58:36.823880
7482 22:58:36.828157 1T = (360-108) = 252 dly cells
7483 22:58:36.830571 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7484 22:58:36.830686 ==
7485 22:58:36.833740 Dram Type= 6, Freq= 0, CH_0, rank 0
7486 22:58:36.840554 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7487 22:58:36.840667 ==
7488 22:58:36.843621 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7489 22:58:36.850367 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7490 22:58:36.853411 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7491 22:58:36.860353 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7492 22:58:36.868403 [CA 0] Center 44 (14~75) winsize 62
7493 22:58:36.871663 [CA 1] Center 43 (13~74) winsize 62
7494 22:58:36.874705 [CA 2] Center 39 (10~69) winsize 60
7495 22:58:36.877969 [CA 3] Center 39 (10~68) winsize 59
7496 22:58:36.881764 [CA 4] Center 37 (8~67) winsize 60
7497 22:58:36.884875 [CA 5] Center 37 (7~67) winsize 61
7498 22:58:36.884962
7499 22:58:36.887847 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7500 22:58:36.890958
7501 22:58:36.894688 [CATrainingPosCal] consider 1 rank data
7502 22:58:36.894802 u2DelayCellTimex100 = 258/100 ps
7503 22:58:36.901208 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7504 22:58:36.904369 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7505 22:58:36.907554 CA2 delay=39 (10~69),Diff = 2 PI (7 cell)
7506 22:58:36.910733 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7507 22:58:36.914401 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7508 22:58:36.917468 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7509 22:58:36.917543
7510 22:58:36.920652 CA PerBit enable=1, Macro0, CA PI delay=37
7511 22:58:36.920728
7512 22:58:36.924248 [CBTSetCACLKResult] CA Dly = 37
7513 22:58:36.927290 CS Dly: 11 (0~42)
7514 22:58:36.930461 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7515 22:58:36.933647 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7516 22:58:36.937345 ==
7517 22:58:36.940528 Dram Type= 6, Freq= 0, CH_0, rank 1
7518 22:58:36.943553 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7519 22:58:36.943642 ==
7520 22:58:36.946973 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7521 22:58:36.953685 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7522 22:58:36.956769 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7523 22:58:36.963140 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7524 22:58:36.972324 [CA 0] Center 44 (14~75) winsize 62
7525 22:58:36.975696 [CA 1] Center 43 (13~74) winsize 62
7526 22:58:36.978877 [CA 2] Center 39 (10~69) winsize 60
7527 22:58:36.982059 [CA 3] Center 39 (10~69) winsize 60
7528 22:58:36.985232 [CA 4] Center 37 (8~67) winsize 60
7529 22:58:36.988516 [CA 5] Center 37 (7~67) winsize 61
7530 22:58:36.988599
7531 22:58:36.992407 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7532 22:58:36.992543
7533 22:58:36.998382 [CATrainingPosCal] consider 2 rank data
7534 22:58:36.998542 u2DelayCellTimex100 = 258/100 ps
7535 22:58:37.005235 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7536 22:58:37.008300 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7537 22:58:37.011469 CA2 delay=39 (10~69),Diff = 2 PI (7 cell)
7538 22:58:37.015101 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7539 22:58:37.018070 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7540 22:58:37.021315 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7541 22:58:37.021452
7542 22:58:37.024589 CA PerBit enable=1, Macro0, CA PI delay=37
7543 22:58:37.024695
7544 22:58:37.027699 [CBTSetCACLKResult] CA Dly = 37
7545 22:58:37.031295 CS Dly: 11 (0~42)
7546 22:58:37.034368 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7547 22:58:37.037703 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7548 22:58:37.037820
7549 22:58:37.041455 ----->DramcWriteLeveling(PI) begin...
7550 22:58:37.044592 ==
7551 22:58:37.047746 Dram Type= 6, Freq= 0, CH_0, rank 0
7552 22:58:37.050895 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7553 22:58:37.050980 ==
7554 22:58:37.054479 Write leveling (Byte 0): 37 => 37
7555 22:58:37.057373 Write leveling (Byte 1): 27 => 27
7556 22:58:37.060873 DramcWriteLeveling(PI) end<-----
7557 22:58:37.060988
7558 22:58:37.061104 ==
7559 22:58:37.063879 Dram Type= 6, Freq= 0, CH_0, rank 0
7560 22:58:37.067638 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7561 22:58:37.067758 ==
7562 22:58:37.070749 [Gating] SW mode calibration
7563 22:58:37.077490 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7564 22:58:37.083857 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7565 22:58:37.087028 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7566 22:58:37.090162 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7567 22:58:37.097017 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7568 22:58:37.099967 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7569 22:58:37.103710 1 4 16 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
7570 22:58:37.110452 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7571 22:58:37.113504 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7572 22:58:37.116601 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7573 22:58:37.123209 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7574 22:58:37.126311 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7575 22:58:37.130043 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7576 22:58:37.136166 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
7577 22:58:37.139991 1 5 16 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
7578 22:58:37.143084 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7579 22:58:37.149969 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
7580 22:58:37.153140 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7581 22:58:37.156143 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7582 22:58:37.162943 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7583 22:58:37.166007 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7584 22:58:37.169549 1 6 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7585 22:58:37.176084 1 6 16 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
7586 22:58:37.179088 1 6 20 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
7587 22:58:37.182774 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7588 22:58:37.189131 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7589 22:58:37.192258 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7590 22:58:37.196009 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7591 22:58:37.202119 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7592 22:58:37.205842 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7593 22:58:37.209081 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7594 22:58:37.215823 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7595 22:58:37.218913 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7596 22:58:37.221939 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7597 22:58:37.228368 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 22:58:37.232165 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 22:58:37.235289 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 22:58:37.242029 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 22:58:37.245174 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 22:58:37.248420 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 22:58:37.254840 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 22:58:37.258006 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 22:58:37.261716 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 22:58:37.267863 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 22:58:37.271630 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 22:58:37.274864 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7609 22:58:37.281456 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7610 22:58:37.284462 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7611 22:58:37.288159 Total UI for P1: 0, mck2ui 16
7612 22:58:37.291293 best dqsien dly found for B0: ( 1, 9, 14)
7613 22:58:37.294423 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7614 22:58:37.301641 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7615 22:58:37.304116 Total UI for P1: 0, mck2ui 16
7616 22:58:37.307746 best dqsien dly found for B1: ( 1, 9, 22)
7617 22:58:37.310876 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7618 22:58:37.313970 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7619 22:58:37.314048
7620 22:58:37.317656 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7621 22:58:37.320845 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7622 22:58:37.323912 [Gating] SW calibration Done
7623 22:58:37.324019 ==
7624 22:58:37.327001 Dram Type= 6, Freq= 0, CH_0, rank 0
7625 22:58:37.330544 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7626 22:58:37.330649 ==
7627 22:58:37.334101 RX Vref Scan: 0
7628 22:58:37.334180
7629 22:58:37.337039 RX Vref 0 -> 0, step: 1
7630 22:58:37.337125
7631 22:58:37.337221 RX Delay 0 -> 252, step: 8
7632 22:58:37.344154 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
7633 22:58:37.347159 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7634 22:58:37.350363 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7635 22:58:37.353500 iDelay=200, Bit 3, Center 123 (72 ~ 175) 104
7636 22:58:37.357393 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7637 22:58:37.363604 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
7638 22:58:37.366771 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7639 22:58:37.369975 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7640 22:58:37.373061 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7641 22:58:37.376747 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7642 22:58:37.383479 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7643 22:58:37.386686 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7644 22:58:37.389750 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7645 22:58:37.393299 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7646 22:58:37.399401 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7647 22:58:37.403238 iDelay=200, Bit 15, Center 127 (72 ~ 183) 112
7648 22:58:37.403324 ==
7649 22:58:37.406658 Dram Type= 6, Freq= 0, CH_0, rank 0
7650 22:58:37.409443 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7651 22:58:37.409521 ==
7652 22:58:37.412537 DQS Delay:
7653 22:58:37.412639 DQS0 = 0, DQS1 = 0
7654 22:58:37.416354 DQM Delay:
7655 22:58:37.416445 DQM0 = 128, DQM1 = 123
7656 22:58:37.416511 DQ Delay:
7657 22:58:37.419500 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =123
7658 22:58:37.426148 DQ4 =127, DQ5 =111, DQ6 =135, DQ7 =143
7659 22:58:37.429276 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7660 22:58:37.432403 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =127
7661 22:58:37.432487
7662 22:58:37.432552
7663 22:58:37.432613 ==
7664 22:58:37.435605 Dram Type= 6, Freq= 0, CH_0, rank 0
7665 22:58:37.439382 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7666 22:58:37.439466 ==
7667 22:58:37.439531
7668 22:58:37.439591
7669 22:58:37.442375 TX Vref Scan disable
7670 22:58:37.445954 == TX Byte 0 ==
7671 22:58:37.449250 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
7672 22:58:37.452174 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7673 22:58:37.455721 == TX Byte 1 ==
7674 22:58:37.458942 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7675 22:58:37.462037 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7676 22:58:37.462120 ==
7677 22:58:37.465843 Dram Type= 6, Freq= 0, CH_0, rank 0
7678 22:58:37.468821 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7679 22:58:37.471899 ==
7680 22:58:37.484569
7681 22:58:37.487660 TX Vref early break, caculate TX vref
7682 22:58:37.491474 TX Vref=16, minBit 9, minWin=21, winSum=369
7683 22:58:37.494626 TX Vref=18, minBit 8, minWin=22, winSum=377
7684 22:58:37.497661 TX Vref=20, minBit 8, minWin=22, winSum=384
7685 22:58:37.501202 TX Vref=22, minBit 8, minWin=23, winSum=394
7686 22:58:37.504622 TX Vref=24, minBit 8, minWin=23, winSum=404
7687 22:58:37.510880 TX Vref=26, minBit 9, minWin=24, winSum=411
7688 22:58:37.514557 TX Vref=28, minBit 8, minWin=23, winSum=410
7689 22:58:37.517638 TX Vref=30, minBit 8, minWin=24, winSum=402
7690 22:58:37.520767 TX Vref=32, minBit 8, minWin=23, winSum=397
7691 22:58:37.524666 TX Vref=34, minBit 8, minWin=22, winSum=383
7692 22:58:37.530904 [TxChooseVref] Worse bit 9, Min win 24, Win sum 411, Final Vref 26
7693 22:58:37.531017
7694 22:58:37.534002 Final TX Range 0 Vref 26
7695 22:58:37.534083
7696 22:58:37.534147 ==
7697 22:58:37.537654 Dram Type= 6, Freq= 0, CH_0, rank 0
7698 22:58:37.540849 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7699 22:58:37.540955 ==
7700 22:58:37.541051
7701 22:58:37.541141
7702 22:58:37.543904 TX Vref Scan disable
7703 22:58:37.550552 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7704 22:58:37.550664 == TX Byte 0 ==
7705 22:58:37.553687 u2DelayCellOfst[0]=15 cells (4 PI)
7706 22:58:37.557324 u2DelayCellOfst[1]=18 cells (5 PI)
7707 22:58:37.560729 u2DelayCellOfst[2]=11 cells (3 PI)
7708 22:58:37.563741 u2DelayCellOfst[3]=15 cells (4 PI)
7709 22:58:37.566988 u2DelayCellOfst[4]=7 cells (2 PI)
7710 22:58:37.570701 u2DelayCellOfst[5]=0 cells (0 PI)
7711 22:58:37.573823 u2DelayCellOfst[6]=18 cells (5 PI)
7712 22:58:37.576916 u2DelayCellOfst[7]=18 cells (5 PI)
7713 22:58:37.580462 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7714 22:58:37.583576 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7715 22:58:37.587356 == TX Byte 1 ==
7716 22:58:37.590402 u2DelayCellOfst[8]=0 cells (0 PI)
7717 22:58:37.593696 u2DelayCellOfst[9]=0 cells (0 PI)
7718 22:58:37.593802 u2DelayCellOfst[10]=7 cells (2 PI)
7719 22:58:37.596749 u2DelayCellOfst[11]=3 cells (1 PI)
7720 22:58:37.600429 u2DelayCellOfst[12]=11 cells (3 PI)
7721 22:58:37.603486 u2DelayCellOfst[13]=11 cells (3 PI)
7722 22:58:37.606969 u2DelayCellOfst[14]=15 cells (4 PI)
7723 22:58:37.610224 u2DelayCellOfst[15]=11 cells (3 PI)
7724 22:58:37.616600 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7725 22:58:37.620238 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7726 22:58:37.620345 DramC Write-DBI on
7727 22:58:37.620445 ==
7728 22:58:37.623336 Dram Type= 6, Freq= 0, CH_0, rank 0
7729 22:58:37.630161 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7730 22:58:37.630240 ==
7731 22:58:37.630314
7732 22:58:37.630403
7733 22:58:37.630493 TX Vref Scan disable
7734 22:58:37.634005 == TX Byte 0 ==
7735 22:58:37.637167 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
7736 22:58:37.640879 == TX Byte 1 ==
7737 22:58:37.643870 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7738 22:58:37.647493 DramC Write-DBI off
7739 22:58:37.647599
7740 22:58:37.647697 [DATLAT]
7741 22:58:37.647787 Freq=1600, CH0 RK0
7742 22:58:37.647881
7743 22:58:37.650620 DATLAT Default: 0xf
7744 22:58:37.653610 0, 0xFFFF, sum = 0
7745 22:58:37.653693 1, 0xFFFF, sum = 0
7746 22:58:37.657437 2, 0xFFFF, sum = 0
7747 22:58:37.657540 3, 0xFFFF, sum = 0
7748 22:58:37.660446 4, 0xFFFF, sum = 0
7749 22:58:37.660565 5, 0xFFFF, sum = 0
7750 22:58:37.664059 6, 0xFFFF, sum = 0
7751 22:58:37.664166 7, 0xFFFF, sum = 0
7752 22:58:37.667139 8, 0xFFFF, sum = 0
7753 22:58:37.667217 9, 0xFFFF, sum = 0
7754 22:58:37.670149 10, 0xFFFF, sum = 0
7755 22:58:37.670239 11, 0xFFFF, sum = 0
7756 22:58:37.673785 12, 0xFFFF, sum = 0
7757 22:58:37.673896 13, 0xEFFF, sum = 0
7758 22:58:37.676941 14, 0x0, sum = 1
7759 22:58:37.677069 15, 0x0, sum = 2
7760 22:58:37.680068 16, 0x0, sum = 3
7761 22:58:37.680192 17, 0x0, sum = 4
7762 22:58:37.683686 best_step = 15
7763 22:58:37.683806
7764 22:58:37.683879 ==
7765 22:58:37.686658 Dram Type= 6, Freq= 0, CH_0, rank 0
7766 22:58:37.689871 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7767 22:58:37.689994 ==
7768 22:58:37.693530 RX Vref Scan: 1
7769 22:58:37.693656
7770 22:58:37.693778 Set Vref Range= 24 -> 127
7771 22:58:37.696566
7772 22:58:37.696684 RX Vref 24 -> 127, step: 1
7773 22:58:37.696782
7774 22:58:37.699744 RX Delay 11 -> 252, step: 4
7775 22:58:37.699864
7776 22:58:37.702885 Set Vref, RX VrefLevel [Byte0]: 24
7777 22:58:37.706693 [Byte1]: 24
7778 22:58:37.706816
7779 22:58:37.709859 Set Vref, RX VrefLevel [Byte0]: 25
7780 22:58:37.712900 [Byte1]: 25
7781 22:58:37.717245
7782 22:58:37.717362 Set Vref, RX VrefLevel [Byte0]: 26
7783 22:58:37.720411 [Byte1]: 26
7784 22:58:37.724677
7785 22:58:37.724783 Set Vref, RX VrefLevel [Byte0]: 27
7786 22:58:37.727616 [Byte1]: 27
7787 22:58:37.732046
7788 22:58:37.732150 Set Vref, RX VrefLevel [Byte0]: 28
7789 22:58:37.735872 [Byte1]: 28
7790 22:58:37.739738
7791 22:58:37.739846 Set Vref, RX VrefLevel [Byte0]: 29
7792 22:58:37.742944 [Byte1]: 29
7793 22:58:37.747284
7794 22:58:37.747392 Set Vref, RX VrefLevel [Byte0]: 30
7795 22:58:37.750994 [Byte1]: 30
7796 22:58:37.755176
7797 22:58:37.755281 Set Vref, RX VrefLevel [Byte0]: 31
7798 22:58:37.758278 [Byte1]: 31
7799 22:58:37.762484
7800 22:58:37.762590 Set Vref, RX VrefLevel [Byte0]: 32
7801 22:58:37.765600 [Byte1]: 32
7802 22:58:37.770018
7803 22:58:37.770104 Set Vref, RX VrefLevel [Byte0]: 33
7804 22:58:37.773471 [Byte1]: 33
7805 22:58:37.777827
7806 22:58:37.777908 Set Vref, RX VrefLevel [Byte0]: 34
7807 22:58:37.781373 [Byte1]: 34
7808 22:58:37.785735
7809 22:58:37.785836 Set Vref, RX VrefLevel [Byte0]: 35
7810 22:58:37.788857 [Byte1]: 35
7811 22:58:37.793310
7812 22:58:37.793421 Set Vref, RX VrefLevel [Byte0]: 36
7813 22:58:37.796447 [Byte1]: 36
7814 22:58:37.800887
7815 22:58:37.800998 Set Vref, RX VrefLevel [Byte0]: 37
7816 22:58:37.803963 [Byte1]: 37
7817 22:58:37.808317
7818 22:58:37.808413 Set Vref, RX VrefLevel [Byte0]: 38
7819 22:58:37.811419 [Byte1]: 38
7820 22:58:37.816229
7821 22:58:37.816335 Set Vref, RX VrefLevel [Byte0]: 39
7822 22:58:37.819321 [Byte1]: 39
7823 22:58:37.823617
7824 22:58:37.823722 Set Vref, RX VrefLevel [Byte0]: 40
7825 22:58:37.826876 [Byte1]: 40
7826 22:58:37.831090
7827 22:58:37.831196 Set Vref, RX VrefLevel [Byte0]: 41
7828 22:58:37.834641 [Byte1]: 41
7829 22:58:37.838986
7830 22:58:37.839094 Set Vref, RX VrefLevel [Byte0]: 42
7831 22:58:37.842057 [Byte1]: 42
7832 22:58:37.846584
7833 22:58:37.846692 Set Vref, RX VrefLevel [Byte0]: 43
7834 22:58:37.849839 [Byte1]: 43
7835 22:58:37.854105
7836 22:58:37.854184 Set Vref, RX VrefLevel [Byte0]: 44
7837 22:58:37.857059 [Byte1]: 44
7838 22:58:37.861932
7839 22:58:37.862015 Set Vref, RX VrefLevel [Byte0]: 45
7840 22:58:37.864860 [Byte1]: 45
7841 22:58:37.869405
7842 22:58:37.869516 Set Vref, RX VrefLevel [Byte0]: 46
7843 22:58:37.872581 [Byte1]: 46
7844 22:58:37.877082
7845 22:58:37.877189 Set Vref, RX VrefLevel [Byte0]: 47
7846 22:58:37.880102 [Byte1]: 47
7847 22:58:37.884204
7848 22:58:37.884318 Set Vref, RX VrefLevel [Byte0]: 48
7849 22:58:37.887651 [Byte1]: 48
7850 22:58:37.891937
7851 22:58:37.892059 Set Vref, RX VrefLevel [Byte0]: 49
7852 22:58:37.895532 [Byte1]: 49
7853 22:58:37.899888
7854 22:58:37.900011 Set Vref, RX VrefLevel [Byte0]: 50
7855 22:58:37.903038 [Byte1]: 50
7856 22:58:37.907350
7857 22:58:37.907451 Set Vref, RX VrefLevel [Byte0]: 51
7858 22:58:37.910566 [Byte1]: 51
7859 22:58:37.915034
7860 22:58:37.915134 Set Vref, RX VrefLevel [Byte0]: 52
7861 22:58:37.918363 [Byte1]: 52
7862 22:58:37.922307
7863 22:58:37.922416 Set Vref, RX VrefLevel [Byte0]: 53
7864 22:58:37.926021 [Byte1]: 53
7865 22:58:37.930438
7866 22:58:37.930542 Set Vref, RX VrefLevel [Byte0]: 54
7867 22:58:37.933332 [Byte1]: 54
7868 22:58:37.937681
7869 22:58:37.937755 Set Vref, RX VrefLevel [Byte0]: 55
7870 22:58:37.940700 [Byte1]: 55
7871 22:58:37.945583
7872 22:58:37.945703 Set Vref, RX VrefLevel [Byte0]: 56
7873 22:58:37.948747 [Byte1]: 56
7874 22:58:37.952680
7875 22:58:37.952800 Set Vref, RX VrefLevel [Byte0]: 57
7876 22:58:37.956441 [Byte1]: 57
7877 22:58:37.960728
7878 22:58:37.960835 Set Vref, RX VrefLevel [Byte0]: 58
7879 22:58:37.963830 [Byte1]: 58
7880 22:58:37.968054
7881 22:58:37.968158 Set Vref, RX VrefLevel [Byte0]: 59
7882 22:58:37.971427 [Byte1]: 59
7883 22:58:37.975939
7884 22:58:37.976044 Set Vref, RX VrefLevel [Byte0]: 60
7885 22:58:37.979064 [Byte1]: 60
7886 22:58:37.983457
7887 22:58:37.983559 Set Vref, RX VrefLevel [Byte0]: 61
7888 22:58:37.986465 [Byte1]: 61
7889 22:58:37.991281
7890 22:58:37.991389 Set Vref, RX VrefLevel [Byte0]: 62
7891 22:58:37.994169 [Byte1]: 62
7892 22:58:37.998657
7893 22:58:37.998767 Set Vref, RX VrefLevel [Byte0]: 63
7894 22:58:38.001630 [Byte1]: 63
7895 22:58:38.006528
7896 22:58:38.006644 Set Vref, RX VrefLevel [Byte0]: 64
7897 22:58:38.009880 [Byte1]: 64
7898 22:58:38.013603
7899 22:58:38.013723 Set Vref, RX VrefLevel [Byte0]: 65
7900 22:58:38.017306 [Byte1]: 65
7901 22:58:38.021825
7902 22:58:38.021907 Set Vref, RX VrefLevel [Byte0]: 66
7903 22:58:38.024742 [Byte1]: 66
7904 22:58:38.028951
7905 22:58:38.029034 Set Vref, RX VrefLevel [Byte0]: 67
7906 22:58:38.032740 [Byte1]: 67
7907 22:58:38.036562
7908 22:58:38.036649 Set Vref, RX VrefLevel [Byte0]: 68
7909 22:58:38.039711 [Byte1]: 68
7910 22:58:38.044063
7911 22:58:38.044158 Set Vref, RX VrefLevel [Byte0]: 69
7912 22:58:38.047895 [Byte1]: 69
7913 22:58:38.051985
7914 22:58:38.052064 Set Vref, RX VrefLevel [Byte0]: 70
7915 22:58:38.055491 [Byte1]: 70
7916 22:58:38.059375
7917 22:58:38.059472 Set Vref, RX VrefLevel [Byte0]: 71
7918 22:58:38.062533 [Byte1]: 71
7919 22:58:38.066904
7920 22:58:38.066986 Set Vref, RX VrefLevel [Byte0]: 72
7921 22:58:38.070527 [Byte1]: 72
7922 22:58:38.074873
7923 22:58:38.074966 Set Vref, RX VrefLevel [Byte0]: 73
7924 22:58:38.077874 [Byte1]: 73
7925 22:58:38.082455
7926 22:58:38.082548 Set Vref, RX VrefLevel [Byte0]: 74
7927 22:58:38.085580 [Byte1]: 74
7928 22:58:38.090114
7929 22:58:38.090195 Set Vref, RX VrefLevel [Byte0]: 75
7930 22:58:38.093111 [Byte1]: 75
7931 22:58:38.097679
7932 22:58:38.097781 Set Vref, RX VrefLevel [Byte0]: 76
7933 22:58:38.100605 [Byte1]: 76
7934 22:58:38.105385
7935 22:58:38.105468 Final RX Vref Byte 0 = 62 to rank0
7936 22:58:38.108345 Final RX Vref Byte 1 = 62 to rank0
7937 22:58:38.111931 Final RX Vref Byte 0 = 62 to rank1
7938 22:58:38.114935 Final RX Vref Byte 1 = 62 to rank1==
7939 22:58:38.118157 Dram Type= 6, Freq= 0, CH_0, rank 0
7940 22:58:38.125115 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7941 22:58:38.125199 ==
7942 22:58:38.125265 DQS Delay:
7943 22:58:38.128250 DQS0 = 0, DQS1 = 0
7944 22:58:38.128345 DQM Delay:
7945 22:58:38.128413 DQM0 = 126, DQM1 = 119
7946 22:58:38.131897 DQ Delay:
7947 22:58:38.135013 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7948 22:58:38.138083 DQ4 =126, DQ5 =112, DQ6 =132, DQ7 =138
7949 22:58:38.141824 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7950 22:58:38.145002 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
7951 22:58:38.145123
7952 22:58:38.145222
7953 22:58:38.145313
7954 22:58:38.148059 [DramC_TX_OE_Calibration] TA2
7955 22:58:38.151147 Original DQ_B0 (3 6) =30, OEN = 27
7956 22:58:38.154926 Original DQ_B1 (3 6) =30, OEN = 27
7957 22:58:38.158057 24, 0x0, End_B0=24 End_B1=24
7958 22:58:38.158173 25, 0x0, End_B0=25 End_B1=25
7959 22:58:38.161038 26, 0x0, End_B0=26 End_B1=26
7960 22:58:38.164828 27, 0x0, End_B0=27 End_B1=27
7961 22:58:38.168027 28, 0x0, End_B0=28 End_B1=28
7962 22:58:38.171244 29, 0x0, End_B0=29 End_B1=29
7963 22:58:38.171332 30, 0x0, End_B0=30 End_B1=30
7964 22:58:38.174323 31, 0x4141, End_B0=30 End_B1=30
7965 22:58:38.177491 Byte0 end_step=30 best_step=27
7966 22:58:38.180892 Byte1 end_step=30 best_step=27
7967 22:58:38.184361 Byte0 TX OE(2T, 0.5T) = (3, 3)
7968 22:58:38.187478 Byte1 TX OE(2T, 0.5T) = (3, 3)
7969 22:58:38.187594
7970 22:58:38.187705
7971 22:58:38.194435 [DQSOSCAuto] RK0, (LSB)MR18= 0x1211, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
7972 22:58:38.197546 CH0 RK0: MR19=303, MR18=1211
7973 22:58:38.204237 CH0_RK0: MR19=0x303, MR18=0x1211, DQSOSC=400, MR23=63, INC=23, DEC=15
7974 22:58:38.204332
7975 22:58:38.207176 ----->DramcWriteLeveling(PI) begin...
7976 22:58:38.207261 ==
7977 22:58:38.210538 Dram Type= 6, Freq= 0, CH_0, rank 1
7978 22:58:38.213702 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7979 22:58:38.213784 ==
7980 22:58:38.217311 Write leveling (Byte 0): 35 => 35
7981 22:58:38.220322 Write leveling (Byte 1): 27 => 27
7982 22:58:38.223876 DramcWriteLeveling(PI) end<-----
7983 22:58:38.223987
7984 22:58:38.224081 ==
7985 22:58:38.226898 Dram Type= 6, Freq= 0, CH_0, rank 1
7986 22:58:38.230687 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7987 22:58:38.233677 ==
7988 22:58:38.233761 [Gating] SW mode calibration
7989 22:58:38.243851 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7990 22:58:38.247098 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7991 22:58:38.250130 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7992 22:58:38.257100 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7993 22:58:38.260257 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7994 22:58:38.263279 1 4 12 | B1->B0 | 2323 2f2e | 0 1 | (0 0) (0 0)
7995 22:58:38.270129 1 4 16 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7996 22:58:38.273309 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7997 22:58:38.276519 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7998 22:58:38.283354 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7999 22:58:38.286355 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8000 22:58:38.289918 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8001 22:58:38.296656 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8002 22:58:38.299827 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
8003 22:58:38.303310 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (0 0) (0 0)
8004 22:58:38.309408 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 22:58:38.312946 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 22:58:38.316453 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 22:58:38.322456 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8008 22:58:38.326149 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 22:58:38.329356 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8010 22:58:38.336051 1 6 12 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
8011 22:58:38.338938 1 6 16 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
8012 22:58:38.342564 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8013 22:58:38.348933 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8014 22:58:38.352056 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 22:58:38.355858 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 22:58:38.362078 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8017 22:58:38.365239 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8018 22:58:38.368499 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8019 22:58:38.375136 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8020 22:58:38.379344 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8021 22:58:38.382221 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 22:58:38.388617 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 22:58:38.391826 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 22:58:38.394890 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 22:58:38.401619 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 22:58:38.405253 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 22:58:38.408403 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 22:58:38.414818 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 22:58:38.418481 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 22:58:38.421625 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 22:58:38.428182 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 22:58:38.431651 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 22:58:38.434550 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8034 22:58:38.441098 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8035 22:58:38.444651 Total UI for P1: 0, mck2ui 16
8036 22:58:38.447634 best dqsien dly found for B0: ( 1, 9, 8)
8037 22:58:38.451259 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8038 22:58:38.454439 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8039 22:58:38.457770 Total UI for P1: 0, mck2ui 16
8040 22:58:38.460892 best dqsien dly found for B1: ( 1, 9, 16)
8041 22:58:38.464490 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8042 22:58:38.470880 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8043 22:58:38.470959
8044 22:58:38.474020 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8045 22:58:38.477685 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8046 22:58:38.481129 [Gating] SW calibration Done
8047 22:58:38.481233 ==
8048 22:58:38.484333 Dram Type= 6, Freq= 0, CH_0, rank 1
8049 22:58:38.487484 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8050 22:58:38.487607 ==
8051 22:58:38.490592 RX Vref Scan: 0
8052 22:58:38.490707
8053 22:58:38.490815 RX Vref 0 -> 0, step: 1
8054 22:58:38.490927
8055 22:58:38.493741 RX Delay 0 -> 252, step: 8
8056 22:58:38.497510 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8057 22:58:38.500583 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8058 22:58:38.507245 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8059 22:58:38.510253 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8060 22:58:38.514098 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8061 22:58:38.517309 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8062 22:58:38.520393 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8063 22:58:38.527176 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8064 22:58:38.530333 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8065 22:58:38.533525 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8066 22:58:38.536616 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8067 22:58:38.543210 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8068 22:58:38.546862 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8069 22:58:38.550305 iDelay=200, Bit 13, Center 127 (72 ~ 183) 112
8070 22:58:38.553336 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8071 22:58:38.556973 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8072 22:58:38.560080 ==
8073 22:58:38.563355 Dram Type= 6, Freq= 0, CH_0, rank 1
8074 22:58:38.566385 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8075 22:58:38.566491 ==
8076 22:58:38.566559 DQS Delay:
8077 22:58:38.570071 DQS0 = 0, DQS1 = 0
8078 22:58:38.570144 DQM Delay:
8079 22:58:38.573272 DQM0 = 128, DQM1 = 121
8080 22:58:38.573358 DQ Delay:
8081 22:58:38.576440 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
8082 22:58:38.579685 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8083 22:58:38.582703 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
8084 22:58:38.586395 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8085 22:58:38.586500
8086 22:58:38.586620
8087 22:58:38.589418 ==
8088 22:58:38.592591 Dram Type= 6, Freq= 0, CH_0, rank 1
8089 22:58:38.596317 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8090 22:58:38.596433 ==
8091 22:58:38.596538
8092 22:58:38.596645
8093 22:58:38.599449 TX Vref Scan disable
8094 22:58:38.599553 == TX Byte 0 ==
8095 22:58:38.606026 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8096 22:58:38.609077 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8097 22:58:38.609183 == TX Byte 1 ==
8098 22:58:38.615671 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8099 22:58:38.618891 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8100 22:58:38.618970 ==
8101 22:58:38.622629 Dram Type= 6, Freq= 0, CH_0, rank 1
8102 22:58:38.625657 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8103 22:58:38.625786 ==
8104 22:58:38.640321
8105 22:58:38.643409 TX Vref early break, caculate TX vref
8106 22:58:38.646458 TX Vref=16, minBit 8, minWin=21, winSum=367
8107 22:58:38.650198 TX Vref=18, minBit 9, minWin=22, winSum=376
8108 22:58:38.653099 TX Vref=20, minBit 8, minWin=22, winSum=384
8109 22:58:38.656727 TX Vref=22, minBit 8, minWin=23, winSum=391
8110 22:58:38.659617 TX Vref=24, minBit 0, minWin=24, winSum=401
8111 22:58:38.666722 TX Vref=26, minBit 8, minWin=24, winSum=406
8112 22:58:38.669629 TX Vref=28, minBit 8, minWin=24, winSum=414
8113 22:58:38.673271 TX Vref=30, minBit 8, minWin=24, winSum=409
8114 22:58:38.676391 TX Vref=32, minBit 8, minWin=23, winSum=396
8115 22:58:38.679564 TX Vref=34, minBit 8, minWin=22, winSum=388
8116 22:58:38.686331 [TxChooseVref] Worse bit 8, Min win 24, Win sum 414, Final Vref 28
8117 22:58:38.686429
8118 22:58:38.689498 Final TX Range 0 Vref 28
8119 22:58:38.689586
8120 22:58:38.689651 ==
8121 22:58:38.692525 Dram Type= 6, Freq= 0, CH_0, rank 1
8122 22:58:38.696179 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8123 22:58:38.696272 ==
8124 22:58:38.696338
8125 22:58:38.696409
8126 22:58:38.699325 TX Vref Scan disable
8127 22:58:38.705634 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8128 22:58:38.705768 == TX Byte 0 ==
8129 22:58:38.709280 u2DelayCellOfst[0]=11 cells (3 PI)
8130 22:58:38.712525 u2DelayCellOfst[1]=15 cells (4 PI)
8131 22:58:38.715702 u2DelayCellOfst[2]=11 cells (3 PI)
8132 22:58:38.719147 u2DelayCellOfst[3]=11 cells (3 PI)
8133 22:58:38.722085 u2DelayCellOfst[4]=7 cells (2 PI)
8134 22:58:38.725926 u2DelayCellOfst[5]=0 cells (0 PI)
8135 22:58:38.729070 u2DelayCellOfst[6]=18 cells (5 PI)
8136 22:58:38.732060 u2DelayCellOfst[7]=18 cells (5 PI)
8137 22:58:38.735321 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8138 22:58:38.738522 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8139 22:58:38.742176 == TX Byte 1 ==
8140 22:58:38.745181 u2DelayCellOfst[8]=0 cells (0 PI)
8141 22:58:38.748443 u2DelayCellOfst[9]=0 cells (0 PI)
8142 22:58:38.752223 u2DelayCellOfst[10]=7 cells (2 PI)
8143 22:58:38.752334 u2DelayCellOfst[11]=7 cells (2 PI)
8144 22:58:38.755408 u2DelayCellOfst[12]=15 cells (4 PI)
8145 22:58:38.758432 u2DelayCellOfst[13]=15 cells (4 PI)
8146 22:58:38.762149 u2DelayCellOfst[14]=15 cells (4 PI)
8147 22:58:38.765175 u2DelayCellOfst[15]=11 cells (3 PI)
8148 22:58:38.771753 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8149 22:58:38.775236 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8150 22:58:38.775369 DramC Write-DBI on
8151 22:58:38.778395 ==
8152 22:58:38.778524 Dram Type= 6, Freq= 0, CH_0, rank 1
8153 22:58:38.784868 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8154 22:58:38.785006 ==
8155 22:58:38.785112
8156 22:58:38.785217
8157 22:58:38.788083 TX Vref Scan disable
8158 22:58:38.788192 == TX Byte 0 ==
8159 22:58:38.794985 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8160 22:58:38.795095 == TX Byte 1 ==
8161 22:58:38.798081 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8162 22:58:38.801656 DramC Write-DBI off
8163 22:58:38.801779
8164 22:58:38.801877 [DATLAT]
8165 22:58:38.804747 Freq=1600, CH0 RK1
8166 22:58:38.804824
8167 22:58:38.804907 DATLAT Default: 0xf
8168 22:58:38.807917 0, 0xFFFF, sum = 0
8169 22:58:38.807994 1, 0xFFFF, sum = 0
8170 22:58:38.811631 2, 0xFFFF, sum = 0
8171 22:58:38.811709 3, 0xFFFF, sum = 0
8172 22:58:38.814751 4, 0xFFFF, sum = 0
8173 22:58:38.814890 5, 0xFFFF, sum = 0
8174 22:58:38.818020 6, 0xFFFF, sum = 0
8175 22:58:38.821079 7, 0xFFFF, sum = 0
8176 22:58:38.821160 8, 0xFFFF, sum = 0
8177 22:58:38.824704 9, 0xFFFF, sum = 0
8178 22:58:38.824795 10, 0xFFFF, sum = 0
8179 22:58:38.827737 11, 0xFFFF, sum = 0
8180 22:58:38.827825 12, 0xFFFF, sum = 0
8181 22:58:38.830859 13, 0xCFFF, sum = 0
8182 22:58:38.830937 14, 0x0, sum = 1
8183 22:58:38.834471 15, 0x0, sum = 2
8184 22:58:38.834583 16, 0x0, sum = 3
8185 22:58:38.837692 17, 0x0, sum = 4
8186 22:58:38.837771 best_step = 15
8187 22:58:38.837846
8188 22:58:38.837910 ==
8189 22:58:38.840943 Dram Type= 6, Freq= 0, CH_0, rank 1
8190 22:58:38.844121 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8191 22:58:38.847835 ==
8192 22:58:38.847911 RX Vref Scan: 0
8193 22:58:38.847985
8194 22:58:38.850722 RX Vref 0 -> 0, step: 1
8195 22:58:38.850796
8196 22:58:38.853930 RX Delay 3 -> 252, step: 4
8197 22:58:38.857665 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8198 22:58:38.860847 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8199 22:58:38.864025 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8200 22:58:38.870509 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8201 22:58:38.873611 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8202 22:58:38.877082 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8203 22:58:38.880124 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8204 22:58:38.883756 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8205 22:58:38.890352 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8206 22:58:38.893360 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8207 22:58:38.896630 iDelay=191, Bit 10, Center 118 (63 ~ 174) 112
8208 22:58:38.900320 iDelay=191, Bit 11, Center 110 (55 ~ 166) 112
8209 22:58:38.906497 iDelay=191, Bit 12, Center 122 (67 ~ 178) 112
8210 22:58:38.909651 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8211 22:58:38.912888 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8212 22:58:38.916507 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8213 22:58:38.916580 ==
8214 22:58:38.919625 Dram Type= 6, Freq= 0, CH_0, rank 1
8215 22:58:38.926500 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8216 22:58:38.926606 ==
8217 22:58:38.926704 DQS Delay:
8218 22:58:38.929553 DQS0 = 0, DQS1 = 0
8219 22:58:38.929652 DQM Delay:
8220 22:58:38.929758 DQM0 = 124, DQM1 = 117
8221 22:58:38.933090 DQ Delay:
8222 22:58:38.936148 DQ0 =124, DQ1 =126, DQ2 =122, DQ3 =122
8223 22:58:38.939704 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8224 22:58:38.942819 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =110
8225 22:58:38.945960 DQ12 =122, DQ13 =122, DQ14 =128, DQ15 =124
8226 22:58:38.946061
8227 22:58:38.946154
8228 22:58:38.946243
8229 22:58:38.949606 [DramC_TX_OE_Calibration] TA2
8230 22:58:38.952676 Original DQ_B0 (3 6) =30, OEN = 27
8231 22:58:38.956432 Original DQ_B1 (3 6) =30, OEN = 27
8232 22:58:38.959610 24, 0x0, End_B0=24 End_B1=24
8233 22:58:38.959712 25, 0x0, End_B0=25 End_B1=25
8234 22:58:38.962755 26, 0x0, End_B0=26 End_B1=26
8235 22:58:38.965861 27, 0x0, End_B0=27 End_B1=27
8236 22:58:38.969000 28, 0x0, End_B0=28 End_B1=28
8237 22:58:38.972580 29, 0x0, End_B0=29 End_B1=29
8238 22:58:38.972684 30, 0x0, End_B0=30 End_B1=30
8239 22:58:38.975455 31, 0x4141, End_B0=30 End_B1=30
8240 22:58:38.979223 Byte0 end_step=30 best_step=27
8241 22:58:38.982541 Byte1 end_step=30 best_step=27
8242 22:58:38.985281 Byte0 TX OE(2T, 0.5T) = (3, 3)
8243 22:58:38.988942 Byte1 TX OE(2T, 0.5T) = (3, 3)
8244 22:58:38.989062
8245 22:58:38.989169
8246 22:58:38.995511 [DQSOSCAuto] RK1, (LSB)MR18= 0x2411, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
8247 22:58:38.998603 CH0 RK1: MR19=303, MR18=2411
8248 22:58:39.005615 CH0_RK1: MR19=0x303, MR18=0x2411, DQSOSC=391, MR23=63, INC=24, DEC=16
8249 22:58:39.008683 [RxdqsGatingPostProcess] freq 1600
8250 22:58:39.015418 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8251 22:58:39.015536 best DQS0 dly(2T, 0.5T) = (1, 1)
8252 22:58:39.018568 best DQS1 dly(2T, 0.5T) = (1, 1)
8253 22:58:39.021769 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8254 22:58:39.025406 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8255 22:58:39.028620 best DQS0 dly(2T, 0.5T) = (1, 1)
8256 22:58:39.031866 best DQS1 dly(2T, 0.5T) = (1, 1)
8257 22:58:39.034985 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8258 22:58:39.038680 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8259 22:58:39.041724 Pre-setting of DQS Precalculation
8260 22:58:39.044734 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8261 22:58:39.044847 ==
8262 22:58:39.048496 Dram Type= 6, Freq= 0, CH_1, rank 0
8263 22:58:39.054725 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8264 22:58:39.054833 ==
8265 22:58:39.057853 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8266 22:58:39.064683 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8267 22:58:39.067879 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8268 22:58:39.074724 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8269 22:58:39.082917 [CA 0] Center 42 (13~71) winsize 59
8270 22:58:39.086160 [CA 1] Center 42 (13~72) winsize 60
8271 22:58:39.089027 [CA 2] Center 38 (9~67) winsize 59
8272 22:58:39.092531 [CA 3] Center 37 (8~67) winsize 60
8273 22:58:39.095653 [CA 4] Center 38 (9~67) winsize 59
8274 22:58:39.098924 [CA 5] Center 36 (7~66) winsize 60
8275 22:58:39.099005
8276 22:58:39.102473 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8277 22:58:39.102581
8278 22:58:39.108788 [CATrainingPosCal] consider 1 rank data
8279 22:58:39.108898 u2DelayCellTimex100 = 258/100 ps
8280 22:58:39.115691 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8281 22:58:39.118860 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8282 22:58:39.122457 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8283 22:58:39.125472 CA3 delay=37 (8~67),Diff = 1 PI (3 cell)
8284 22:58:39.129110 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8285 22:58:39.132196 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8286 22:58:39.132304
8287 22:58:39.135337 CA PerBit enable=1, Macro0, CA PI delay=36
8288 22:58:39.135420
8289 22:58:39.138445 [CBTSetCACLKResult] CA Dly = 36
8290 22:58:39.142256 CS Dly: 10 (0~41)
8291 22:58:39.145366 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8292 22:58:39.148317 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8293 22:58:39.148410 ==
8294 22:58:39.151960 Dram Type= 6, Freq= 0, CH_1, rank 1
8295 22:58:39.158438 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8296 22:58:39.158572 ==
8297 22:58:39.162091 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8298 22:58:39.168194 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8299 22:58:39.171358 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8300 22:58:39.178313 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8301 22:58:39.185931 [CA 0] Center 41 (12~71) winsize 60
8302 22:58:39.189065 [CA 1] Center 42 (12~72) winsize 61
8303 22:58:39.192148 [CA 2] Center 37 (8~67) winsize 60
8304 22:58:39.195707 [CA 3] Center 36 (6~66) winsize 61
8305 22:58:39.198787 [CA 4] Center 37 (8~67) winsize 60
8306 22:58:39.201985 [CA 5] Center 36 (6~66) winsize 61
8307 22:58:39.202068
8308 22:58:39.205539 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8309 22:58:39.205674
8310 22:58:39.212118 [CATrainingPosCal] consider 2 rank data
8311 22:58:39.212208 u2DelayCellTimex100 = 258/100 ps
8312 22:58:39.218384 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8313 22:58:39.222094 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8314 22:58:39.225182 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8315 22:58:39.228764 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8316 22:58:39.231680 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8317 22:58:39.234955 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8318 22:58:39.235034
8319 22:58:39.238151 CA PerBit enable=1, Macro0, CA PI delay=36
8320 22:58:39.238277
8321 22:58:39.241379 [CBTSetCACLKResult] CA Dly = 36
8322 22:58:39.245122 CS Dly: 11 (0~43)
8323 22:58:39.248343 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8324 22:58:39.251453 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8325 22:58:39.251580
8326 22:58:39.254809 ----->DramcWriteLeveling(PI) begin...
8327 22:58:39.254937 ==
8328 22:58:39.258407 Dram Type= 6, Freq= 0, CH_1, rank 0
8329 22:58:39.264535 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8330 22:58:39.264661 ==
8331 22:58:39.268387 Write leveling (Byte 0): 24 => 24
8332 22:58:39.271791 Write leveling (Byte 1): 29 => 29
8333 22:58:39.271898 DramcWriteLeveling(PI) end<-----
8334 22:58:39.274461
8335 22:58:39.274578 ==
8336 22:58:39.277823 Dram Type= 6, Freq= 0, CH_1, rank 0
8337 22:58:39.281602 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8338 22:58:39.281686 ==
8339 22:58:39.284886 [Gating] SW mode calibration
8340 22:58:39.291070 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8341 22:58:39.297945 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8342 22:58:39.301447 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8343 22:58:39.304126 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8344 22:58:39.310817 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8345 22:58:39.314289 1 4 12 | B1->B0 | 2424 2322 | 0 1 | (0 0) (0 0)
8346 22:58:39.317421 1 4 16 | B1->B0 | 3434 3232 | 0 1 | (0 0) (1 1)
8347 22:58:39.324176 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8348 22:58:39.327417 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8349 22:58:39.330578 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8350 22:58:39.337327 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8351 22:58:39.340463 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8352 22:58:39.343789 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8353 22:58:39.350365 1 5 12 | B1->B0 | 3232 3434 | 0 0 | (0 1) (0 1)
8354 22:58:39.353693 1 5 16 | B1->B0 | 2424 2525 | 0 0 | (0 1) (0 1)
8355 22:58:39.357050 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 22:58:39.363268 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 22:58:39.366882 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 22:58:39.370105 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 22:58:39.376475 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 22:58:39.379855 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 22:58:39.382918 1 6 12 | B1->B0 | 2a2a 2828 | 1 0 | (0 0) (0 0)
8362 22:58:39.389652 1 6 16 | B1->B0 | 4343 4545 | 0 0 | (0 0) (0 0)
8363 22:58:39.392857 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 22:58:39.396083 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 22:58:39.403424 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 22:58:39.406309 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 22:58:39.409593 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8368 22:58:39.416371 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 22:58:39.419367 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8370 22:58:39.422499 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8371 22:58:39.429099 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8372 22:58:39.432418 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 22:58:39.435587 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 22:58:39.442434 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 22:58:39.445551 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 22:58:39.449442 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 22:58:39.455708 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 22:58:39.458916 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 22:58:39.461988 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 22:58:39.468621 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 22:58:39.472310 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 22:58:39.475278 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 22:58:39.481988 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 22:58:39.485196 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 22:58:39.488527 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8386 22:58:39.495374 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8387 22:58:39.498481 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 22:58:39.501832 Total UI for P1: 0, mck2ui 16
8389 22:58:39.505050 best dqsien dly found for B0: ( 1, 9, 16)
8390 22:58:39.508723 Total UI for P1: 0, mck2ui 16
8391 22:58:39.511846 best dqsien dly found for B1: ( 1, 9, 14)
8392 22:58:39.515042 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8393 22:58:39.518124 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8394 22:58:39.518233
8395 22:58:39.521745 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8396 22:58:39.524841 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8397 22:58:39.527943 [Gating] SW calibration Done
8398 22:58:39.528046 ==
8399 22:58:39.531139 Dram Type= 6, Freq= 0, CH_1, rank 0
8400 22:58:39.538329 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8401 22:58:39.538480 ==
8402 22:58:39.538582 RX Vref Scan: 0
8403 22:58:39.538687
8404 22:58:39.541491 RX Vref 0 -> 0, step: 1
8405 22:58:39.541598
8406 22:58:39.544643 RX Delay 0 -> 252, step: 8
8407 22:58:39.547692 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8408 22:58:39.551113 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8409 22:58:39.554849 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8410 22:58:39.558043 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8411 22:58:39.564373 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8412 22:58:39.567668 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8413 22:58:39.571301 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8414 22:58:39.574191 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8415 22:58:39.577722 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8416 22:58:39.583815 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8417 22:58:39.587750 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8418 22:58:39.590377 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8419 22:58:39.593711 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8420 22:58:39.600281 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8421 22:58:39.603936 iDelay=200, Bit 14, Center 131 (80 ~ 183) 104
8422 22:58:39.607165 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8423 22:58:39.607280 ==
8424 22:58:39.610342 Dram Type= 6, Freq= 0, CH_1, rank 0
8425 22:58:39.613952 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8426 22:58:39.614058 ==
8427 22:58:39.617082 DQS Delay:
8428 22:58:39.617193 DQS0 = 0, DQS1 = 0
8429 22:58:39.620047 DQM Delay:
8430 22:58:39.620162 DQM0 = 132, DQM1 = 125
8431 22:58:39.623664 DQ Delay:
8432 22:58:39.626960 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8433 22:58:39.630091 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =135
8434 22:58:39.633745 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8435 22:58:39.636899 DQ12 =135, DQ13 =135, DQ14 =131, DQ15 =135
8436 22:58:39.637004
8437 22:58:39.637097
8438 22:58:39.637192 ==
8439 22:58:39.640018 Dram Type= 6, Freq= 0, CH_1, rank 0
8440 22:58:39.643240 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8441 22:58:39.643343 ==
8442 22:58:39.643436
8443 22:58:39.643524
8444 22:58:39.647018 TX Vref Scan disable
8445 22:58:39.650163 == TX Byte 0 ==
8446 22:58:39.653357 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8447 22:58:39.656923 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8448 22:58:39.659856 == TX Byte 1 ==
8449 22:58:39.663459 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8450 22:58:39.666566 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8451 22:58:39.666647 ==
8452 22:58:39.669766 Dram Type= 6, Freq= 0, CH_1, rank 0
8453 22:58:39.676091 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8454 22:58:39.676199 ==
8455 22:58:39.688013
8456 22:58:39.691158 TX Vref early break, caculate TX vref
8457 22:58:39.694838 TX Vref=16, minBit 8, minWin=21, winSum=362
8458 22:58:39.698055 TX Vref=18, minBit 8, minWin=21, winSum=369
8459 22:58:39.701153 TX Vref=20, minBit 11, minWin=22, winSum=380
8460 22:58:39.704866 TX Vref=22, minBit 8, minWin=23, winSum=393
8461 22:58:39.707899 TX Vref=24, minBit 9, minWin=24, winSum=404
8462 22:58:39.714750 TX Vref=26, minBit 8, minWin=24, winSum=407
8463 22:58:39.717411 TX Vref=28, minBit 6, minWin=25, winSum=415
8464 22:58:39.721059 TX Vref=30, minBit 1, minWin=25, winSum=416
8465 22:58:39.724216 TX Vref=32, minBit 9, minWin=24, winSum=403
8466 22:58:39.727815 TX Vref=34, minBit 8, minWin=23, winSum=388
8467 22:58:39.734498 [TxChooseVref] Worse bit 1, Min win 25, Win sum 416, Final Vref 30
8468 22:58:39.734617
8469 22:58:39.737636 Final TX Range 0 Vref 30
8470 22:58:39.737749
8471 22:58:39.737845 ==
8472 22:58:39.740868 Dram Type= 6, Freq= 0, CH_1, rank 0
8473 22:58:39.743968 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8474 22:58:39.744077 ==
8475 22:58:39.744173
8476 22:58:39.744266
8477 22:58:39.747152 TX Vref Scan disable
8478 22:58:39.753801 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8479 22:58:39.753911 == TX Byte 0 ==
8480 22:58:39.756965 u2DelayCellOfst[0]=18 cells (5 PI)
8481 22:58:39.760476 u2DelayCellOfst[1]=15 cells (4 PI)
8482 22:58:39.763538 u2DelayCellOfst[2]=0 cells (0 PI)
8483 22:58:39.767269 u2DelayCellOfst[3]=7 cells (2 PI)
8484 22:58:39.770223 u2DelayCellOfst[4]=7 cells (2 PI)
8485 22:58:39.773997 u2DelayCellOfst[5]=22 cells (6 PI)
8486 22:58:39.777277 u2DelayCellOfst[6]=22 cells (6 PI)
8487 22:58:39.780264 u2DelayCellOfst[7]=7 cells (2 PI)
8488 22:58:39.783324 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8489 22:58:39.786965 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8490 22:58:39.789831 == TX Byte 1 ==
8491 22:58:39.793365 u2DelayCellOfst[8]=0 cells (0 PI)
8492 22:58:39.796460 u2DelayCellOfst[9]=7 cells (2 PI)
8493 22:58:39.799610 u2DelayCellOfst[10]=15 cells (4 PI)
8494 22:58:39.803327 u2DelayCellOfst[11]=7 cells (2 PI)
8495 22:58:39.806416 u2DelayCellOfst[12]=15 cells (4 PI)
8496 22:58:39.806521 u2DelayCellOfst[13]=18 cells (5 PI)
8497 22:58:39.810025 u2DelayCellOfst[14]=18 cells (5 PI)
8498 22:58:39.813178 u2DelayCellOfst[15]=18 cells (5 PI)
8499 22:58:39.819304 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8500 22:58:39.822549 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8501 22:58:39.826262 DramC Write-DBI on
8502 22:58:39.826369 ==
8503 22:58:39.829483 Dram Type= 6, Freq= 0, CH_1, rank 0
8504 22:58:39.832554 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8505 22:58:39.832673 ==
8506 22:58:39.832784
8507 22:58:39.832892
8508 22:58:39.836172 TX Vref Scan disable
8509 22:58:39.836293 == TX Byte 0 ==
8510 22:58:39.842494 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8511 22:58:39.842602 == TX Byte 1 ==
8512 22:58:39.845773 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8513 22:58:39.848901 DramC Write-DBI off
8514 22:58:39.849007
8515 22:58:39.849132 [DATLAT]
8516 22:58:39.852718 Freq=1600, CH1 RK0
8517 22:58:39.852838
8518 22:58:39.852959 DATLAT Default: 0xf
8519 22:58:39.855932 0, 0xFFFF, sum = 0
8520 22:58:39.856040 1, 0xFFFF, sum = 0
8521 22:58:39.858958 2, 0xFFFF, sum = 0
8522 22:58:39.862655 3, 0xFFFF, sum = 0
8523 22:58:39.862766 4, 0xFFFF, sum = 0
8524 22:58:39.865749 5, 0xFFFF, sum = 0
8525 22:58:39.865867 6, 0xFFFF, sum = 0
8526 22:58:39.869143 7, 0xFFFF, sum = 0
8527 22:58:39.869247 8, 0xFFFF, sum = 0
8528 22:58:39.872863 9, 0xFFFF, sum = 0
8529 22:58:39.872973 10, 0xFFFF, sum = 0
8530 22:58:39.875666 11, 0xFFFF, sum = 0
8531 22:58:39.875774 12, 0xFFFF, sum = 0
8532 22:58:39.878903 13, 0xCFFF, sum = 0
8533 22:58:39.879007 14, 0x0, sum = 1
8534 22:58:39.881977 15, 0x0, sum = 2
8535 22:58:39.882091 16, 0x0, sum = 3
8536 22:58:39.885306 17, 0x0, sum = 4
8537 22:58:39.885411 best_step = 15
8538 22:58:39.885502
8539 22:58:39.885596 ==
8540 22:58:39.889101 Dram Type= 6, Freq= 0, CH_1, rank 0
8541 22:58:39.895201 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8542 22:58:39.895319 ==
8543 22:58:39.895427 RX Vref Scan: 1
8544 22:58:39.895539
8545 22:58:39.898586 Set Vref Range= 24 -> 127
8546 22:58:39.898693
8547 22:58:39.902186 RX Vref 24 -> 127, step: 1
8548 22:58:39.902292
8549 22:58:39.902391 RX Delay 11 -> 252, step: 4
8550 22:58:39.902485
8551 22:58:39.905169 Set Vref, RX VrefLevel [Byte0]: 24
8552 22:58:39.908334 [Byte1]: 24
8553 22:58:39.912695
8554 22:58:39.912803 Set Vref, RX VrefLevel [Byte0]: 25
8555 22:58:39.919146 [Byte1]: 25
8556 22:58:39.919228
8557 22:58:39.922304 Set Vref, RX VrefLevel [Byte0]: 26
8558 22:58:39.925623 [Byte1]: 26
8559 22:58:39.925726
8560 22:58:39.928771 Set Vref, RX VrefLevel [Byte0]: 27
8561 22:58:39.931935 [Byte1]: 27
8562 22:58:39.935652
8563 22:58:39.935734 Set Vref, RX VrefLevel [Byte0]: 28
8564 22:58:39.938622 [Byte1]: 28
8565 22:58:39.942998
8566 22:58:39.943077 Set Vref, RX VrefLevel [Byte0]: 29
8567 22:58:39.946061 [Byte1]: 29
8568 22:58:39.950729
8569 22:58:39.950846 Set Vref, RX VrefLevel [Byte0]: 30
8570 22:58:39.954028 [Byte1]: 30
8571 22:58:39.958423
8572 22:58:39.958526 Set Vref, RX VrefLevel [Byte0]: 31
8573 22:58:39.961487 [Byte1]: 31
8574 22:58:39.966003
8575 22:58:39.966096 Set Vref, RX VrefLevel [Byte0]: 32
8576 22:58:39.969088 [Byte1]: 32
8577 22:58:39.973576
8578 22:58:39.973682 Set Vref, RX VrefLevel [Byte0]: 33
8579 22:58:39.976753 [Byte1]: 33
8580 22:58:39.981117
8581 22:58:39.981232 Set Vref, RX VrefLevel [Byte0]: 34
8582 22:58:39.984969 [Byte1]: 34
8583 22:58:39.988874
8584 22:58:39.988986 Set Vref, RX VrefLevel [Byte0]: 35
8585 22:58:39.991999 [Byte1]: 35
8586 22:58:39.996531
8587 22:58:39.996635 Set Vref, RX VrefLevel [Byte0]: 36
8588 22:58:39.999718 [Byte1]: 36
8589 22:58:40.004174
8590 22:58:40.004292 Set Vref, RX VrefLevel [Byte0]: 37
8591 22:58:40.007206 [Byte1]: 37
8592 22:58:40.011643
8593 22:58:40.011756 Set Vref, RX VrefLevel [Byte0]: 38
8594 22:58:40.018165 [Byte1]: 38
8595 22:58:40.018275
8596 22:58:40.021270 Set Vref, RX VrefLevel [Byte0]: 39
8597 22:58:40.024344 [Byte1]: 39
8598 22:58:40.024447
8599 22:58:40.028107 Set Vref, RX VrefLevel [Byte0]: 40
8600 22:58:40.031204 [Byte1]: 40
8601 22:58:40.034278
8602 22:58:40.034387 Set Vref, RX VrefLevel [Byte0]: 41
8603 22:58:40.037523 [Byte1]: 41
8604 22:58:40.042309
8605 22:58:40.042417 Set Vref, RX VrefLevel [Byte0]: 42
8606 22:58:40.045373 [Byte1]: 42
8607 22:58:40.049782
8608 22:58:40.049884 Set Vref, RX VrefLevel [Byte0]: 43
8609 22:58:40.053049 [Byte1]: 43
8610 22:58:40.057348
8611 22:58:40.057449 Set Vref, RX VrefLevel [Byte0]: 44
8612 22:58:40.060405 [Byte1]: 44
8613 22:58:40.065040
8614 22:58:40.065148 Set Vref, RX VrefLevel [Byte0]: 45
8615 22:58:40.068177 [Byte1]: 45
8616 22:58:40.072724
8617 22:58:40.072833 Set Vref, RX VrefLevel [Byte0]: 46
8618 22:58:40.075772 [Byte1]: 46
8619 22:58:40.080201
8620 22:58:40.080284 Set Vref, RX VrefLevel [Byte0]: 47
8621 22:58:40.083311 [Byte1]: 47
8622 22:58:40.087647
8623 22:58:40.087730 Set Vref, RX VrefLevel [Byte0]: 48
8624 22:58:40.091256 [Byte1]: 48
8625 22:58:40.095642
8626 22:58:40.095751 Set Vref, RX VrefLevel [Byte0]: 49
8627 22:58:40.098399 [Byte1]: 49
8628 22:58:40.102798
8629 22:58:40.102918 Set Vref, RX VrefLevel [Byte0]: 50
8630 22:58:40.105953 [Byte1]: 50
8631 22:58:40.110733
8632 22:58:40.110849 Set Vref, RX VrefLevel [Byte0]: 51
8633 22:58:40.116971 [Byte1]: 51
8634 22:58:40.117079
8635 22:58:40.120720 Set Vref, RX VrefLevel [Byte0]: 52
8636 22:58:40.123709 [Byte1]: 52
8637 22:58:40.123792
8638 22:58:40.127144 Set Vref, RX VrefLevel [Byte0]: 53
8639 22:58:40.129877 [Byte1]: 53
8640 22:58:40.133519
8641 22:58:40.133622 Set Vref, RX VrefLevel [Byte0]: 54
8642 22:58:40.136579 [Byte1]: 54
8643 22:58:40.140830
8644 22:58:40.140940 Set Vref, RX VrefLevel [Byte0]: 55
8645 22:58:40.144497 [Byte1]: 55
8646 22:58:40.148558
8647 22:58:40.148670 Set Vref, RX VrefLevel [Byte0]: 56
8648 22:58:40.151647 [Byte1]: 56
8649 22:58:40.156075
8650 22:58:40.156180 Set Vref, RX VrefLevel [Byte0]: 57
8651 22:58:40.159917 [Byte1]: 57
8652 22:58:40.163635
8653 22:58:40.163739 Set Vref, RX VrefLevel [Byte0]: 58
8654 22:58:40.166953 [Byte1]: 58
8655 22:58:40.171389
8656 22:58:40.171495 Set Vref, RX VrefLevel [Byte0]: 59
8657 22:58:40.174693 [Byte1]: 59
8658 22:58:40.178988
8659 22:58:40.179093 Set Vref, RX VrefLevel [Byte0]: 60
8660 22:58:40.182801 [Byte1]: 60
8661 22:58:40.186649
8662 22:58:40.186732 Set Vref, RX VrefLevel [Byte0]: 61
8663 22:58:40.189877 [Byte1]: 61
8664 22:58:40.194355
8665 22:58:40.194440 Set Vref, RX VrefLevel [Byte0]: 62
8666 22:58:40.197396 [Byte1]: 62
8667 22:58:40.201884
8668 22:58:40.201995 Set Vref, RX VrefLevel [Byte0]: 63
8669 22:58:40.204918 [Byte1]: 63
8670 22:58:40.209241
8671 22:58:40.209333 Set Vref, RX VrefLevel [Byte0]: 64
8672 22:58:40.212893 [Byte1]: 64
8673 22:58:40.217198
8674 22:58:40.217274 Set Vref, RX VrefLevel [Byte0]: 65
8675 22:58:40.220411 [Byte1]: 65
8676 22:58:40.224754
8677 22:58:40.224835 Set Vref, RX VrefLevel [Byte0]: 66
8678 22:58:40.228034 [Byte1]: 66
8679 22:58:40.232315
8680 22:58:40.232435 Set Vref, RX VrefLevel [Byte0]: 67
8681 22:58:40.235665 [Byte1]: 67
8682 22:58:40.239692
8683 22:58:40.239818 Set Vref, RX VrefLevel [Byte0]: 68
8684 22:58:40.243289 [Byte1]: 68
8685 22:58:40.248112
8686 22:58:40.248192 Set Vref, RX VrefLevel [Byte0]: 69
8687 22:58:40.250777 [Byte1]: 69
8688 22:58:40.254898
8689 22:58:40.254995 Set Vref, RX VrefLevel [Byte0]: 70
8690 22:58:40.258598 [Byte1]: 70
8691 22:58:40.262966
8692 22:58:40.263044 Set Vref, RX VrefLevel [Byte0]: 71
8693 22:58:40.266128 [Byte1]: 71
8694 22:58:40.270625
8695 22:58:40.270716 Set Vref, RX VrefLevel [Byte0]: 72
8696 22:58:40.273809 [Byte1]: 72
8697 22:58:40.278137
8698 22:58:40.278214 Final RX Vref Byte 0 = 60 to rank0
8699 22:58:40.281172 Final RX Vref Byte 1 = 56 to rank0
8700 22:58:40.284786 Final RX Vref Byte 0 = 60 to rank1
8701 22:58:40.287945 Final RX Vref Byte 1 = 56 to rank1==
8702 22:58:40.291607 Dram Type= 6, Freq= 0, CH_1, rank 0
8703 22:58:40.297960 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8704 22:58:40.298042 ==
8705 22:58:40.298124 DQS Delay:
8706 22:58:40.300998 DQS0 = 0, DQS1 = 0
8707 22:58:40.301071 DQM Delay:
8708 22:58:40.301148 DQM0 = 131, DQM1 = 123
8709 22:58:40.304745 DQ Delay:
8710 22:58:40.307874 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =126
8711 22:58:40.311066 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =128
8712 22:58:40.314108 DQ8 =110, DQ9 =112, DQ10 =122, DQ11 =116
8713 22:58:40.317735 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8714 22:58:40.317815
8715 22:58:40.317896
8716 22:58:40.317959
8717 22:58:40.320754 [DramC_TX_OE_Calibration] TA2
8718 22:58:40.324020 Original DQ_B0 (3 6) =30, OEN = 27
8719 22:58:40.327763 Original DQ_B1 (3 6) =30, OEN = 27
8720 22:58:40.330903 24, 0x0, End_B0=24 End_B1=24
8721 22:58:40.334058 25, 0x0, End_B0=25 End_B1=25
8722 22:58:40.334131 26, 0x0, End_B0=26 End_B1=26
8723 22:58:40.337667 27, 0x0, End_B0=27 End_B1=27
8724 22:58:40.340713 28, 0x0, End_B0=28 End_B1=28
8725 22:58:40.344233 29, 0x0, End_B0=29 End_B1=29
8726 22:58:40.344317 30, 0x0, End_B0=30 End_B1=30
8727 22:58:40.347159 31, 0x4141, End_B0=30 End_B1=30
8728 22:58:40.350615 Byte0 end_step=30 best_step=27
8729 22:58:40.354289 Byte1 end_step=30 best_step=27
8730 22:58:40.357375 Byte0 TX OE(2T, 0.5T) = (3, 3)
8731 22:58:40.360739 Byte1 TX OE(2T, 0.5T) = (3, 3)
8732 22:58:40.360817
8733 22:58:40.360883
8734 22:58:40.366861 [DQSOSCAuto] RK0, (LSB)MR18= 0x60c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
8735 22:58:40.370511 CH1 RK0: MR19=303, MR18=60C
8736 22:58:40.376807 CH1_RK0: MR19=0x303, MR18=0x60C, DQSOSC=403, MR23=63, INC=22, DEC=15
8737 22:58:40.376884
8738 22:58:40.380041 ----->DramcWriteLeveling(PI) begin...
8739 22:58:40.380123 ==
8740 22:58:40.383843 Dram Type= 6, Freq= 0, CH_1, rank 1
8741 22:58:40.386911 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8742 22:58:40.387000 ==
8743 22:58:40.389981 Write leveling (Byte 0): 24 => 24
8744 22:58:40.393958 Write leveling (Byte 1): 28 => 28
8745 22:58:40.397054 DramcWriteLeveling(PI) end<-----
8746 22:58:40.397131
8747 22:58:40.397212 ==
8748 22:58:40.400266 Dram Type= 6, Freq= 0, CH_1, rank 1
8749 22:58:40.403531 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8750 22:58:40.403643 ==
8751 22:58:40.406630 [Gating] SW mode calibration
8752 22:58:40.413357 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8753 22:58:40.419739 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8754 22:58:40.422888 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8755 22:58:40.429776 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8756 22:58:40.432947 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8757 22:58:40.436071 1 4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8758 22:58:40.443109 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8759 22:58:40.446202 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8760 22:58:40.449428 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8761 22:58:40.456141 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8762 22:58:40.459985 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8763 22:58:40.462838 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8764 22:58:40.469530 1 5 8 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (0 0)
8765 22:58:40.472474 1 5 12 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
8766 22:58:40.476049 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 22:58:40.482378 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 22:58:40.485506 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 22:58:40.489789 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 22:58:40.495808 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 22:58:40.499096 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 22:58:40.502295 1 6 8 | B1->B0 | 2727 4242 | 0 0 | (0 0) (0 0)
8773 22:58:40.508701 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8774 22:58:40.512049 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8775 22:58:40.515666 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8776 22:58:40.521948 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 22:58:40.525699 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8778 22:58:40.528815 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8779 22:58:40.535486 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8780 22:58:40.538701 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8781 22:58:40.542015 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8782 22:58:40.548332 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8783 22:58:40.551690 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 22:58:40.554981 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 22:58:40.561448 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 22:58:40.565051 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 22:58:40.568239 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 22:58:40.574872 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 22:58:40.577897 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 22:58:40.581296 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 22:58:40.587892 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 22:58:40.591526 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 22:58:40.594539 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 22:58:40.601017 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 22:58:40.604376 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 22:58:40.607671 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8797 22:58:40.614138 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8798 22:58:40.617310 Total UI for P1: 0, mck2ui 16
8799 22:58:40.621015 best dqsien dly found for B0: ( 1, 9, 8)
8800 22:58:40.624067 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 22:58:40.627243 Total UI for P1: 0, mck2ui 16
8802 22:58:40.630946 best dqsien dly found for B1: ( 1, 9, 10)
8803 22:58:40.634025 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8804 22:58:40.637522 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8805 22:58:40.637641
8806 22:58:40.640450 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8807 22:58:40.643647 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8808 22:58:40.647441 [Gating] SW calibration Done
8809 22:58:40.647543 ==
8810 22:58:40.650651 Dram Type= 6, Freq= 0, CH_1, rank 1
8811 22:58:40.657050 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8812 22:58:40.657176 ==
8813 22:58:40.657280 RX Vref Scan: 0
8814 22:58:40.657394
8815 22:58:40.660253 RX Vref 0 -> 0, step: 1
8816 22:58:40.660341
8817 22:58:40.663449 RX Delay 0 -> 252, step: 8
8818 22:58:40.667263 iDelay=200, Bit 0, Center 135 (72 ~ 199) 128
8819 22:58:40.670529 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8820 22:58:40.673220 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8821 22:58:40.676946 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8822 22:58:40.683185 iDelay=200, Bit 4, Center 123 (64 ~ 183) 120
8823 22:58:40.686898 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8824 22:58:40.690018 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8825 22:58:40.693109 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8826 22:58:40.700160 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8827 22:58:40.703213 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8828 22:58:40.706482 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8829 22:58:40.709676 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8830 22:58:40.712965 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8831 22:58:40.719409 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8832 22:58:40.722721 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8833 22:58:40.725889 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8834 22:58:40.725968 ==
8835 22:58:40.729632 Dram Type= 6, Freq= 0, CH_1, rank 1
8836 22:58:40.732653 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8837 22:58:40.736217 ==
8838 22:58:40.736305 DQS Delay:
8839 22:58:40.736394 DQS0 = 0, DQS1 = 0
8840 22:58:40.739439 DQM Delay:
8841 22:58:40.739548 DQM0 = 129, DQM1 = 128
8842 22:58:40.742468 DQ Delay:
8843 22:58:40.746265 DQ0 =135, DQ1 =127, DQ2 =115, DQ3 =127
8844 22:58:40.749556 DQ4 =123, DQ5 =139, DQ6 =139, DQ7 =127
8845 22:58:40.752594 DQ8 =111, DQ9 =115, DQ10 =135, DQ11 =123
8846 22:58:40.755752 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =139
8847 22:58:40.755841
8848 22:58:40.755908
8849 22:58:40.755969 ==
8850 22:58:40.759096 Dram Type= 6, Freq= 0, CH_1, rank 1
8851 22:58:40.762261 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8852 22:58:40.762345 ==
8853 22:58:40.765393
8854 22:58:40.765501
8855 22:58:40.765595 TX Vref Scan disable
8856 22:58:40.769228 == TX Byte 0 ==
8857 22:58:40.772470 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8858 22:58:40.775501 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8859 22:58:40.778835 == TX Byte 1 ==
8860 22:58:40.782114 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8861 22:58:40.785052 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8862 22:58:40.788759 ==
8863 22:58:40.788870 Dram Type= 6, Freq= 0, CH_1, rank 1
8864 22:58:40.795407 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8865 22:58:40.795518 ==
8866 22:58:40.808613
8867 22:58:40.811727 TX Vref early break, caculate TX vref
8868 22:58:40.814986 TX Vref=16, minBit 0, minWin=23, winSum=382
8869 22:58:40.818864 TX Vref=18, minBit 0, minWin=23, winSum=390
8870 22:58:40.822063 TX Vref=20, minBit 0, minWin=23, winSum=402
8871 22:58:40.825138 TX Vref=22, minBit 0, minWin=24, winSum=407
8872 22:58:40.828447 TX Vref=24, minBit 0, minWin=25, winSum=414
8873 22:58:40.834797 TX Vref=26, minBit 0, minWin=25, winSum=422
8874 22:58:40.838398 TX Vref=28, minBit 5, minWin=25, winSum=421
8875 22:58:40.842082 TX Vref=30, minBit 1, minWin=24, winSum=422
8876 22:58:40.845180 TX Vref=32, minBit 1, minWin=24, winSum=413
8877 22:58:40.848321 TX Vref=34, minBit 0, minWin=23, winSum=405
8878 22:58:40.851514 TX Vref=36, minBit 1, minWin=23, winSum=396
8879 22:58:40.858333 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 26
8880 22:58:40.858453
8881 22:58:40.861495 Final TX Range 0 Vref 26
8882 22:58:40.861606
8883 22:58:40.861704 ==
8884 22:58:40.864731 Dram Type= 6, Freq= 0, CH_1, rank 1
8885 22:58:40.868407 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8886 22:58:40.868518 ==
8887 22:58:40.868615
8888 22:58:40.871659
8889 22:58:40.871743 TX Vref Scan disable
8890 22:58:40.877924 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8891 22:58:40.878009 == TX Byte 0 ==
8892 22:58:40.881155 u2DelayCellOfst[0]=18 cells (5 PI)
8893 22:58:40.884987 u2DelayCellOfst[1]=11 cells (3 PI)
8894 22:58:40.888183 u2DelayCellOfst[2]=0 cells (0 PI)
8895 22:58:40.891420 u2DelayCellOfst[3]=3 cells (1 PI)
8896 22:58:40.894321 u2DelayCellOfst[4]=7 cells (2 PI)
8897 22:58:40.897883 u2DelayCellOfst[5]=18 cells (5 PI)
8898 22:58:40.901409 u2DelayCellOfst[6]=18 cells (5 PI)
8899 22:58:40.904506 u2DelayCellOfst[7]=3 cells (1 PI)
8900 22:58:40.907314 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8901 22:58:40.911203 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8902 22:58:40.914027 == TX Byte 1 ==
8903 22:58:40.917316 u2DelayCellOfst[8]=0 cells (0 PI)
8904 22:58:40.920452 u2DelayCellOfst[9]=7 cells (2 PI)
8905 22:58:40.923664 u2DelayCellOfst[10]=15 cells (4 PI)
8906 22:58:40.926947 u2DelayCellOfst[11]=7 cells (2 PI)
8907 22:58:40.930593 u2DelayCellOfst[12]=18 cells (5 PI)
8908 22:58:40.933741 u2DelayCellOfst[13]=18 cells (5 PI)
8909 22:58:40.936935 u2DelayCellOfst[14]=22 cells (6 PI)
8910 22:58:40.937040 u2DelayCellOfst[15]=18 cells (5 PI)
8911 22:58:40.943627 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8912 22:58:40.946995 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8913 22:58:40.949968 DramC Write-DBI on
8914 22:58:40.950088 ==
8915 22:58:40.953230 Dram Type= 6, Freq= 0, CH_1, rank 1
8916 22:58:40.957078 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8917 22:58:40.957187 ==
8918 22:58:40.957287
8919 22:58:40.957390
8920 22:58:40.960289 TX Vref Scan disable
8921 22:58:40.960396 == TX Byte 0 ==
8922 22:58:40.966562 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8923 22:58:40.966673 == TX Byte 1 ==
8924 22:58:40.970300 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8925 22:58:40.973342 DramC Write-DBI off
8926 22:58:40.973448
8927 22:58:40.973540 [DATLAT]
8928 22:58:40.976573 Freq=1600, CH1 RK1
8929 22:58:40.976678
8930 22:58:40.979699 DATLAT Default: 0xf
8931 22:58:40.979801 0, 0xFFFF, sum = 0
8932 22:58:40.982823 1, 0xFFFF, sum = 0
8933 22:58:40.982914 2, 0xFFFF, sum = 0
8934 22:58:40.986522 3, 0xFFFF, sum = 0
8935 22:58:40.986628 4, 0xFFFF, sum = 0
8936 22:58:40.989695 5, 0xFFFF, sum = 0
8937 22:58:40.989797 6, 0xFFFF, sum = 0
8938 22:58:40.992890 7, 0xFFFF, sum = 0
8939 22:58:40.992990 8, 0xFFFF, sum = 0
8940 22:58:40.996064 9, 0xFFFF, sum = 0
8941 22:58:40.996166 10, 0xFFFF, sum = 0
8942 22:58:40.999683 11, 0xFFFF, sum = 0
8943 22:58:40.999784 12, 0xFFFF, sum = 0
8944 22:58:41.002641 13, 0x8FFF, sum = 0
8945 22:58:41.002762 14, 0x0, sum = 1
8946 22:58:41.006440 15, 0x0, sum = 2
8947 22:58:41.006566 16, 0x0, sum = 3
8948 22:58:41.009666 17, 0x0, sum = 4
8949 22:58:41.009776 best_step = 15
8950 22:58:41.009872
8951 22:58:41.009969 ==
8952 22:58:41.012819 Dram Type= 6, Freq= 0, CH_1, rank 1
8953 22:58:41.019262 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8954 22:58:41.019373 ==
8955 22:58:41.019472 RX Vref Scan: 0
8956 22:58:41.019566
8957 22:58:41.022848 RX Vref 0 -> 0, step: 1
8958 22:58:41.022930
8959 22:58:41.025817 RX Delay 3 -> 252, step: 4
8960 22:58:41.029447 iDelay=195, Bit 0, Center 134 (79 ~ 190) 112
8961 22:58:41.032618 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8962 22:58:41.035710 iDelay=195, Bit 2, Center 114 (59 ~ 170) 112
8963 22:58:41.042770 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8964 22:58:41.045784 iDelay=195, Bit 4, Center 122 (67 ~ 178) 112
8965 22:58:41.049355 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8966 22:58:41.052338 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8967 22:58:41.055812 iDelay=195, Bit 7, Center 124 (67 ~ 182) 116
8968 22:58:41.062317 iDelay=195, Bit 8, Center 108 (51 ~ 166) 116
8969 22:58:41.065372 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8970 22:58:41.069153 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8971 22:58:41.072391 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8972 22:58:41.078517 iDelay=195, Bit 12, Center 134 (79 ~ 190) 112
8973 22:58:41.082338 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8974 22:58:41.085557 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8975 22:58:41.088706 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8976 22:58:41.088828 ==
8977 22:58:41.091846 Dram Type= 6, Freq= 0, CH_1, rank 1
8978 22:58:41.098697 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8979 22:58:41.098814 ==
8980 22:58:41.098929 DQS Delay:
8981 22:58:41.101924 DQS0 = 0, DQS1 = 0
8982 22:58:41.102038 DQM Delay:
8983 22:58:41.102142 DQM0 = 127, DQM1 = 125
8984 22:58:41.105013 DQ Delay:
8985 22:58:41.108700 DQ0 =134, DQ1 =126, DQ2 =114, DQ3 =126
8986 22:58:41.111865 DQ4 =122, DQ5 =138, DQ6 =138, DQ7 =124
8987 22:58:41.114867 DQ8 =108, DQ9 =112, DQ10 =128, DQ11 =120
8988 22:58:41.118528 DQ12 =134, DQ13 =132, DQ14 =132, DQ15 =136
8989 22:58:41.118638
8990 22:58:41.118738
8991 22:58:41.118856
8992 22:58:41.121977 [DramC_TX_OE_Calibration] TA2
8993 22:58:41.124852 Original DQ_B0 (3 6) =30, OEN = 27
8994 22:58:41.128443 Original DQ_B1 (3 6) =30, OEN = 27
8995 22:58:41.131460 24, 0x0, End_B0=24 End_B1=24
8996 22:58:41.135000 25, 0x0, End_B0=25 End_B1=25
8997 22:58:41.135113 26, 0x0, End_B0=26 End_B1=26
8998 22:58:41.137954 27, 0x0, End_B0=27 End_B1=27
8999 22:58:41.141250 28, 0x0, End_B0=28 End_B1=28
9000 22:58:41.144341 29, 0x0, End_B0=29 End_B1=29
9001 22:58:41.144474 30, 0x0, End_B0=30 End_B1=30
9002 22:58:41.148140 31, 0x4141, End_B0=30 End_B1=30
9003 22:58:41.151555 Byte0 end_step=30 best_step=27
9004 22:58:41.154485 Byte1 end_step=30 best_step=27
9005 22:58:41.157548 Byte0 TX OE(2T, 0.5T) = (3, 3)
9006 22:58:41.161168 Byte1 TX OE(2T, 0.5T) = (3, 3)
9007 22:58:41.161275
9008 22:58:41.161389
9009 22:58:41.167864 [DQSOSCAuto] RK1, (LSB)MR18= 0xe1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
9010 22:58:41.170977 CH1 RK1: MR19=303, MR18=E1A
9011 22:58:41.177463 CH1_RK1: MR19=0x303, MR18=0xE1A, DQSOSC=396, MR23=63, INC=23, DEC=15
9012 22:58:41.180653 [RxdqsGatingPostProcess] freq 1600
9013 22:58:41.187540 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9014 22:58:41.187673 best DQS0 dly(2T, 0.5T) = (1, 1)
9015 22:58:41.190685 best DQS1 dly(2T, 0.5T) = (1, 1)
9016 22:58:41.193950 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9017 22:58:41.197166 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9018 22:58:41.200467 best DQS0 dly(2T, 0.5T) = (1, 1)
9019 22:58:41.203704 best DQS1 dly(2T, 0.5T) = (1, 1)
9020 22:58:41.207403 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9021 22:58:41.210523 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9022 22:58:41.213678 Pre-setting of DQS Precalculation
9023 22:58:41.216737 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9024 22:58:41.226923 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9025 22:58:41.233894 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9026 22:58:41.234015
9027 22:58:41.234117
9028 22:58:41.236992 [Calibration Summary] 3200 Mbps
9029 22:58:41.237101 CH 0, Rank 0
9030 22:58:41.240500 SW Impedance : PASS
9031 22:58:41.240631 DUTY Scan : NO K
9032 22:58:41.243205 ZQ Calibration : PASS
9033 22:58:41.246316 Jitter Meter : NO K
9034 22:58:41.246426 CBT Training : PASS
9035 22:58:41.250113 Write leveling : PASS
9036 22:58:41.253168 RX DQS gating : PASS
9037 22:58:41.253280 RX DQ/DQS(RDDQC) : PASS
9038 22:58:41.256336 TX DQ/DQS : PASS
9039 22:58:41.260034 RX DATLAT : PASS
9040 22:58:41.260142 RX DQ/DQS(Engine): PASS
9041 22:58:41.263026 TX OE : PASS
9042 22:58:41.263134 All Pass.
9043 22:58:41.263227
9044 22:58:41.266207 CH 0, Rank 1
9045 22:58:41.266332 SW Impedance : PASS
9046 22:58:41.270024 DUTY Scan : NO K
9047 22:58:41.273210 ZQ Calibration : PASS
9048 22:58:41.273289 Jitter Meter : NO K
9049 22:58:41.276277 CBT Training : PASS
9050 22:58:41.279401 Write leveling : PASS
9051 22:58:41.279499 RX DQS gating : PASS
9052 22:58:41.283247 RX DQ/DQS(RDDQC) : PASS
9053 22:58:41.286125 TX DQ/DQS : PASS
9054 22:58:41.286216 RX DATLAT : PASS
9055 22:58:41.289344 RX DQ/DQS(Engine): PASS
9056 22:58:41.289437 TX OE : PASS
9057 22:58:41.292539 All Pass.
9058 22:58:41.292636
9059 22:58:41.292702 CH 1, Rank 0
9060 22:58:41.296279 SW Impedance : PASS
9061 22:58:41.299431 DUTY Scan : NO K
9062 22:58:41.299555 ZQ Calibration : PASS
9063 22:58:41.302693 Jitter Meter : NO K
9064 22:58:41.302822 CBT Training : PASS
9065 22:58:41.305950 Write leveling : PASS
9066 22:58:41.309057 RX DQS gating : PASS
9067 22:58:41.309149 RX DQ/DQS(RDDQC) : PASS
9068 22:58:41.312738 TX DQ/DQS : PASS
9069 22:58:41.316088 RX DATLAT : PASS
9070 22:58:41.316207 RX DQ/DQS(Engine): PASS
9071 22:58:41.319358 TX OE : PASS
9072 22:58:41.319468 All Pass.
9073 22:58:41.319563
9074 22:58:41.322642 CH 1, Rank 1
9075 22:58:41.322746 SW Impedance : PASS
9076 22:58:41.325965 DUTY Scan : NO K
9077 22:58:41.329133 ZQ Calibration : PASS
9078 22:58:41.329245 Jitter Meter : NO K
9079 22:58:41.332192 CBT Training : PASS
9080 22:58:41.335826 Write leveling : PASS
9081 22:58:41.335960 RX DQS gating : PASS
9082 22:58:41.338812 RX DQ/DQS(RDDQC) : PASS
9083 22:58:41.341970 TX DQ/DQS : PASS
9084 22:58:41.342094 RX DATLAT : PASS
9085 22:58:41.345740 RX DQ/DQS(Engine): PASS
9086 22:58:41.348858 TX OE : PASS
9087 22:58:41.348942 All Pass.
9088 22:58:41.349007
9089 22:58:41.349069 DramC Write-DBI on
9090 22:58:41.352427 PER_BANK_REFRESH: Hybrid Mode
9091 22:58:41.355588 TX_TRACKING: ON
9092 22:58:41.362013 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9093 22:58:41.371692 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9094 22:58:41.378256 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9095 22:58:41.381669 [FAST_K] Save calibration result to emmc
9096 22:58:41.385224 sync common calibartion params.
9097 22:58:41.388173 sync cbt_mode0:1, 1:1
9098 22:58:41.388256 dram_init: ddr_geometry: 2
9099 22:58:41.392077 dram_init: ddr_geometry: 2
9100 22:58:41.395241 dram_init: ddr_geometry: 2
9101 22:58:41.398342 0:dram_rank_size:100000000
9102 22:58:41.398455 1:dram_rank_size:100000000
9103 22:58:41.404797 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9104 22:58:41.408033 DFS_SHUFFLE_HW_MODE: ON
9105 22:58:41.411409 dramc_set_vcore_voltage set vcore to 725000
9106 22:58:41.411496 Read voltage for 1600, 0
9107 22:58:41.414713 Vio18 = 0
9108 22:58:41.414840 Vcore = 725000
9109 22:58:41.414913 Vdram = 0
9110 22:58:41.417942 Vddq = 0
9111 22:58:41.418053 Vmddr = 0
9112 22:58:41.421672 switch to 3200 Mbps bootup
9113 22:58:41.421754 [DramcRunTimeConfig]
9114 22:58:41.424967 PHYPLL
9115 22:58:41.425104 DPM_CONTROL_AFTERK: ON
9116 22:58:41.428199 PER_BANK_REFRESH: ON
9117 22:58:41.431300 REFRESH_OVERHEAD_REDUCTION: ON
9118 22:58:41.431410 CMD_PICG_NEW_MODE: OFF
9119 22:58:41.434431 XRTWTW_NEW_MODE: ON
9120 22:58:41.434542 XRTRTR_NEW_MODE: ON
9121 22:58:41.437588 TX_TRACKING: ON
9122 22:58:41.437704 RDSEL_TRACKING: OFF
9123 22:58:41.441300 DQS Precalculation for DVFS: ON
9124 22:58:41.444421 RX_TRACKING: OFF
9125 22:58:41.444529 HW_GATING DBG: ON
9126 22:58:41.447589 ZQCS_ENABLE_LP4: ON
9127 22:58:41.447706 RX_PICG_NEW_MODE: ON
9128 22:58:41.451304 TX_PICG_NEW_MODE: ON
9129 22:58:41.451409 ENABLE_RX_DCM_DPHY: ON
9130 22:58:41.454273 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9131 22:58:41.457937 DUMMY_READ_FOR_TRACKING: OFF
9132 22:58:41.461143 !!! SPM_CONTROL_AFTERK: OFF
9133 22:58:41.464509 !!! SPM could not control APHY
9134 22:58:41.464615 IMPEDANCE_TRACKING: ON
9135 22:58:41.467570 TEMP_SENSOR: ON
9136 22:58:41.467649 HW_SAVE_FOR_SR: OFF
9137 22:58:41.470715 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9138 22:58:41.473903 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9139 22:58:41.477668 Read ODT Tracking: ON
9140 22:58:41.481067 Refresh Rate DeBounce: ON
9141 22:58:41.481143 DFS_NO_QUEUE_FLUSH: ON
9142 22:58:41.483693 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9143 22:58:41.487510 ENABLE_DFS_RUNTIME_MRW: OFF
9144 22:58:41.490408 DDR_RESERVE_NEW_MODE: ON
9145 22:58:41.490508 MR_CBT_SWITCH_FREQ: ON
9146 22:58:41.494058 =========================
9147 22:58:41.512740 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9148 22:58:41.515954 dram_init: ddr_geometry: 2
9149 22:58:41.534358 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9150 22:58:41.537415 dram_init: dram init end (result: 0)
9151 22:58:41.544326 DRAM-K: Full calibration passed in 24538 msecs
9152 22:58:41.547706 MRC: failed to locate region type 0.
9153 22:58:41.550876 DRAM rank0 size:0x100000000,
9154 22:58:41.550989 DRAM rank1 size=0x100000000
9155 22:58:41.560609 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9156 22:58:41.570109 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9157 22:58:41.576855 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9158 22:58:41.583725 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9159 22:58:41.583841 DRAM rank0 size:0x100000000,
9160 22:58:41.586927 DRAM rank1 size=0x100000000
9161 22:58:41.587036 CBMEM:
9162 22:58:41.590240 IMD: root @ 0xfffff000 254 entries.
9163 22:58:41.593364 IMD: root @ 0xffffec00 62 entries.
9164 22:58:41.600352 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9165 22:58:41.603442 WARNING: RO_VPD is uninitialized or empty.
9166 22:58:41.606214 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9167 22:58:41.614770 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9168 22:58:41.627600 read SPI 0x42894 0xe01e: 6228 us, 9212 KB/s, 73.696 Mbps
9169 22:58:41.638394 BS: romstage times (exec / console): total (unknown) / 24006 ms
9170 22:58:41.638519
9171 22:58:41.638617
9172 22:58:41.648714 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9173 22:58:41.651896 ARM64: Exception handlers installed.
9174 22:58:41.655084 ARM64: Testing exception
9175 22:58:41.658312 ARM64: Done test exception
9176 22:58:41.658394 Enumerating buses...
9177 22:58:41.661510 Show all devs... Before device enumeration.
9178 22:58:41.665263 Root Device: enabled 1
9179 22:58:41.668494 CPU_CLUSTER: 0: enabled 1
9180 22:58:41.668607 CPU: 00: enabled 1
9181 22:58:41.671569 Compare with tree...
9182 22:58:41.671680 Root Device: enabled 1
9183 22:58:41.675052 CPU_CLUSTER: 0: enabled 1
9184 22:58:41.678002 CPU: 00: enabled 1
9185 22:58:41.678121 Root Device scanning...
9186 22:58:41.681571 scan_static_bus for Root Device
9187 22:58:41.684703 CPU_CLUSTER: 0 enabled
9188 22:58:41.687848 scan_static_bus for Root Device done
9189 22:58:41.691576 scan_bus: bus Root Device finished in 8 msecs
9190 22:58:41.691686 done
9191 22:58:41.697961 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9192 22:58:41.700959 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9193 22:58:41.707873 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9194 22:58:41.714413 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9195 22:58:41.714501 Allocating resources...
9196 22:58:41.717455 Reading resources...
9197 22:58:41.721264 Root Device read_resources bus 0 link: 0
9198 22:58:41.724110 DRAM rank0 size:0x100000000,
9199 22:58:41.724196 DRAM rank1 size=0x100000000
9200 22:58:41.730970 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9201 22:58:41.731076 CPU: 00 missing read_resources
9202 22:58:41.737234 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9203 22:58:41.740378 Root Device read_resources bus 0 link: 0 done
9204 22:58:41.743641 Done reading resources.
9205 22:58:41.747275 Show resources in subtree (Root Device)...After reading.
9206 22:58:41.750296 Root Device child on link 0 CPU_CLUSTER: 0
9207 22:58:41.754030 CPU_CLUSTER: 0 child on link 0 CPU: 00
9208 22:58:41.763479 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9209 22:58:41.763589 CPU: 00
9210 22:58:41.770445 Root Device assign_resources, bus 0 link: 0
9211 22:58:41.773587 CPU_CLUSTER: 0 missing set_resources
9212 22:58:41.776869 Root Device assign_resources, bus 0 link: 0 done
9213 22:58:41.779863 Done setting resources.
9214 22:58:41.783344 Show resources in subtree (Root Device)...After assigning values.
9215 22:58:41.786716 Root Device child on link 0 CPU_CLUSTER: 0
9216 22:58:41.793347 CPU_CLUSTER: 0 child on link 0 CPU: 00
9217 22:58:41.800226 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9218 22:58:41.803371 CPU: 00
9219 22:58:41.803472 Done allocating resources.
9220 22:58:41.809468 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9221 22:58:41.809578 Enabling resources...
9222 22:58:41.812698 done.
9223 22:58:41.816381 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9224 22:58:41.819590 Initializing devices...
9225 22:58:41.819688 Root Device init
9226 22:58:41.822728 init hardware done!
9227 22:58:41.822840 0x00000018: ctrlr->caps
9228 22:58:41.826434 52.000 MHz: ctrlr->f_max
9229 22:58:41.829506 0.400 MHz: ctrlr->f_min
9230 22:58:41.832992 0x40ff8080: ctrlr->voltages
9231 22:58:41.833099 sclk: 390625
9232 22:58:41.833192 Bus Width = 1
9233 22:58:41.835972 sclk: 390625
9234 22:58:41.836077 Bus Width = 1
9235 22:58:41.839602 Early init status = 3
9236 22:58:41.842691 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9237 22:58:41.846528 in-header: 03 fc 00 00 01 00 00 00
9238 22:58:41.849610 in-data: 00
9239 22:58:41.852724 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9240 22:58:41.858291 in-header: 03 fd 00 00 00 00 00 00
9241 22:58:41.861447 in-data:
9242 22:58:41.864658 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9243 22:58:41.869062 in-header: 03 fc 00 00 01 00 00 00
9244 22:58:41.872184 in-data: 00
9245 22:58:41.875820 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9246 22:58:41.881497 in-header: 03 fd 00 00 00 00 00 00
9247 22:58:41.884674 in-data:
9248 22:58:41.887963 [SSUSB] Setting up USB HOST controller...
9249 22:58:41.891223 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9250 22:58:41.894614 [SSUSB] phy power-on done.
9251 22:58:41.897550 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9252 22:58:41.904381 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9253 22:58:41.907479 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9254 22:58:41.914296 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9255 22:58:41.920886 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9256 22:58:41.927191 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9257 22:58:41.933977 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9258 22:58:41.940155 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9259 22:58:41.943523 SPM: binary array size = 0x9dc
9260 22:58:41.950248 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9261 22:58:41.953409 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9262 22:58:41.959988 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9263 22:58:41.966917 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9264 22:58:41.970086 configure_display: Starting display init
9265 22:58:42.004484 anx7625_power_on_init: Init interface.
9266 22:58:42.007880 anx7625_disable_pd_protocol: Disabled PD feature.
9267 22:58:42.010921 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9268 22:58:42.039168 anx7625_start_dp_work: Secure OCM version=00
9269 22:58:42.042228 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9270 22:58:42.057228 sp_tx_get_edid_block: EDID Block = 1
9271 22:58:42.159661 Extracted contents:
9272 22:58:42.162711 header: 00 ff ff ff ff ff ff 00
9273 22:58:42.166325 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9274 22:58:42.169189 version: 01 04
9275 22:58:42.172594 basic params: 95 1f 11 78 0a
9276 22:58:42.176119 chroma info: 76 90 94 55 54 90 27 21 50 54
9277 22:58:42.179295 established: 00 00 00
9278 22:58:42.185963 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9279 22:58:42.192373 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9280 22:58:42.196030 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9281 22:58:42.202402 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9282 22:58:42.209220 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9283 22:58:42.212263 extensions: 00
9284 22:58:42.212369 checksum: fb
9285 22:58:42.212446
9286 22:58:42.219068 Manufacturer: IVO Model 57d Serial Number 0
9287 22:58:42.219169 Made week 0 of 2020
9288 22:58:42.222390 EDID version: 1.4
9289 22:58:42.222483 Digital display
9290 22:58:42.225240 6 bits per primary color channel
9291 22:58:42.225341 DisplayPort interface
9292 22:58:42.228791 Maximum image size: 31 cm x 17 cm
9293 22:58:42.231734 Gamma: 220%
9294 22:58:42.231815 Check DPMS levels
9295 22:58:42.238414 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9296 22:58:42.242267 First detailed timing is preferred timing
9297 22:58:42.242375 Established timings supported:
9298 22:58:42.245360 Standard timings supported:
9299 22:58:42.248474 Detailed timings
9300 22:58:42.251680 Hex of detail: 383680a07038204018303c0035ae10000019
9301 22:58:42.258497 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9302 22:58:42.261647 0780 0798 07c8 0820 hborder 0
9303 22:58:42.264835 0438 043b 0447 0458 vborder 0
9304 22:58:42.267867 -hsync -vsync
9305 22:58:42.267988 Did detailed timing
9306 22:58:42.274744 Hex of detail: 000000000000000000000000000000000000
9307 22:58:42.278321 Manufacturer-specified data, tag 0
9308 22:58:42.281339 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9309 22:58:42.284708 ASCII string: InfoVision
9310 22:58:42.288171 Hex of detail: 000000fe00523134304e574635205248200a
9311 22:58:42.291250 ASCII string: R140NWF5 RH
9312 22:58:42.291335 Checksum
9313 22:58:42.294296 Checksum: 0xfb (valid)
9314 22:58:42.298114 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9315 22:58:42.301292 DSI data_rate: 832800000 bps
9316 22:58:42.307615 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9317 22:58:42.311348 anx7625_parse_edid: pixelclock(138800).
9318 22:58:42.314346 hactive(1920), hsync(48), hfp(24), hbp(88)
9319 22:58:42.317474 vactive(1080), vsync(12), vfp(3), vbp(17)
9320 22:58:42.321227 anx7625_dsi_config: config dsi.
9321 22:58:42.327509 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9322 22:58:42.341770 anx7625_dsi_config: success to config DSI
9323 22:58:42.345060 anx7625_dp_start: MIPI phy setup OK.
9324 22:58:42.348188 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9325 22:58:42.351222 mtk_ddp_mode_set invalid vrefresh 60
9326 22:58:42.355113 main_disp_path_setup
9327 22:58:42.355196 ovl_layer_smi_id_en
9328 22:58:42.358206 ovl_layer_smi_id_en
9329 22:58:42.358288 ccorr_config
9330 22:58:42.358352 aal_config
9331 22:58:42.361482 gamma_config
9332 22:58:42.361564 postmask_config
9333 22:58:42.364703 dither_config
9334 22:58:42.367794 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9335 22:58:42.374734 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9336 22:58:42.377714 Root Device init finished in 554 msecs
9337 22:58:42.380985 CPU_CLUSTER: 0 init
9338 22:58:42.387811 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9339 22:58:42.394451 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9340 22:58:42.394534 APU_MBOX 0x190000b0 = 0x10001
9341 22:58:42.397476 APU_MBOX 0x190001b0 = 0x10001
9342 22:58:42.400864 APU_MBOX 0x190005b0 = 0x10001
9343 22:58:42.404390 APU_MBOX 0x190006b0 = 0x10001
9344 22:58:42.410640 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9345 22:58:42.420491 read SPI 0x539f4 0xe237: 6251 us, 9264 KB/s, 74.112 Mbps
9346 22:58:42.432941 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9347 22:58:42.439695 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9348 22:58:42.451408 read SPI 0x61c74 0xe8ef: 6414 us, 9297 KB/s, 74.376 Mbps
9349 22:58:42.460250 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9350 22:58:42.464177 CPU_CLUSTER: 0 init finished in 81 msecs
9351 22:58:42.467084 Devices initialized
9352 22:58:42.470246 Show all devs... After init.
9353 22:58:42.470321 Root Device: enabled 1
9354 22:58:42.473422 CPU_CLUSTER: 0: enabled 1
9355 22:58:42.477163 CPU: 00: enabled 1
9356 22:58:42.480326 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9357 22:58:42.483705 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9358 22:58:42.486665 ELOG: NV offset 0x57f000 size 0x1000
9359 22:58:42.493613 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9360 22:58:42.499821 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9361 22:58:42.503348 ELOG: Event(17) added with size 13 at 2023-06-05 22:58:42 UTC
9362 22:58:42.509646 out: cmd=0x121: 03 db 21 01 00 00 00 00
9363 22:58:42.513337 in-header: 03 7a 00 00 2c 00 00 00
9364 22:58:42.522788 in-data: e5 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9365 22:58:42.529708 ELOG: Event(A1) added with size 10 at 2023-06-05 22:58:42 UTC
9366 22:58:42.535947 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9367 22:58:42.542639 ELOG: Event(A0) added with size 9 at 2023-06-05 22:58:42 UTC
9368 22:58:42.546621 elog_add_boot_reason: Logged dev mode boot
9369 22:58:42.552567 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9370 22:58:42.552691 Finalize devices...
9371 22:58:42.556161 Devices finalized
9372 22:58:42.559095 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9373 22:58:42.562833 Writing coreboot table at 0xffe64000
9374 22:58:42.566124 0. 000000000010a000-0000000000113fff: RAMSTAGE
9375 22:58:42.572277 1. 0000000040000000-00000000400fffff: RAM
9376 22:58:42.576023 2. 0000000040100000-000000004032afff: RAMSTAGE
9377 22:58:42.579218 3. 000000004032b000-00000000545fffff: RAM
9378 22:58:42.582365 4. 0000000054600000-000000005465ffff: BL31
9379 22:58:42.585427 5. 0000000054660000-00000000ffe63fff: RAM
9380 22:58:42.592135 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9381 22:58:42.595260 7. 0000000100000000-000000023fffffff: RAM
9382 22:58:42.598945 Passing 5 GPIOs to payload:
9383 22:58:42.601966 NAME | PORT | POLARITY | VALUE
9384 22:58:42.608740 EC in RW | 0x000000aa | low | undefined
9385 22:58:42.611899 EC interrupt | 0x00000005 | low | undefined
9386 22:58:42.618390 TPM interrupt | 0x000000ab | high | undefined
9387 22:58:42.622071 SD card detect | 0x00000011 | high | undefined
9388 22:58:42.625210 speaker enable | 0x00000093 | high | undefined
9389 22:58:42.628215 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9390 22:58:42.632040 in-header: 03 f9 00 00 02 00 00 00
9391 22:58:42.635192 in-data: 02 00
9392 22:58:42.638358 ADC[4]: Raw value=897410 ID=7
9393 22:58:42.642190 ADC[3]: Raw value=213070 ID=1
9394 22:58:42.642274 RAM Code: 0x71
9395 22:58:42.645272 ADC[6]: Raw value=74722 ID=0
9396 22:58:42.648425 ADC[5]: Raw value=212330 ID=1
9397 22:58:42.648511 SKU Code: 0x1
9398 22:58:42.655443 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7dbf
9399 22:58:42.655531 coreboot table: 964 bytes.
9400 22:58:42.658832 IMD ROOT 0. 0xfffff000 0x00001000
9401 22:58:42.661916 IMD SMALL 1. 0xffffe000 0x00001000
9402 22:58:42.664796 RO MCACHE 2. 0xffffc000 0x00001104
9403 22:58:42.668444 CONSOLE 3. 0xfff7c000 0x00080000
9404 22:58:42.671409 FMAP 4. 0xfff7b000 0x00000452
9405 22:58:42.674637 TIME STAMP 5. 0xfff7a000 0x00000910
9406 22:58:42.677830 VBOOT WORK 6. 0xfff66000 0x00014000
9407 22:58:42.681506 RAMOOPS 7. 0xffe66000 0x00100000
9408 22:58:42.684594 COREBOOT 8. 0xffe64000 0x00002000
9409 22:58:42.687846 IMD small region:
9410 22:58:42.691632 IMD ROOT 0. 0xffffec00 0x00000400
9411 22:58:42.694608 VPD 1. 0xffffeba0 0x0000004c
9412 22:58:42.697835 MMC STATUS 2. 0xffffeb80 0x00000004
9413 22:58:42.704507 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9414 22:58:42.704620 Probing TPM: done!
9415 22:58:42.711359 Connected to device vid:did:rid of 1ae0:0028:00
9416 22:58:42.717506 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9417 22:58:42.721045 Initialized TPM device CR50 revision 0
9418 22:58:42.724718 Checking cr50 for pending updates
9419 22:58:42.730328 Reading cr50 TPM mode
9420 22:58:42.738784 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9421 22:58:42.745490 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9422 22:58:42.785723 read SPI 0x3990ec 0x4f1b0: 34860 us, 9294 KB/s, 74.352 Mbps
9423 22:58:42.788953 Checking segment from ROM address 0x40100000
9424 22:58:42.792070 Checking segment from ROM address 0x4010001c
9425 22:58:42.798414 Loading segment from ROM address 0x40100000
9426 22:58:42.798521 code (compression=0)
9427 22:58:42.808373 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9428 22:58:42.815366 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9429 22:58:42.815486 it's not compressed!
9430 22:58:42.822121 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9431 22:58:42.828430 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9432 22:58:42.846121 Loading segment from ROM address 0x4010001c
9433 22:58:42.846248 Entry Point 0x80000000
9434 22:58:42.848981 Loaded segments
9435 22:58:42.852255 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9436 22:58:42.859131 Jumping to boot code at 0x80000000(0xffe64000)
9437 22:58:42.865758 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9438 22:58:42.871960 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9439 22:58:42.880340 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9440 22:58:42.883337 Checking segment from ROM address 0x40100000
9441 22:58:42.886903 Checking segment from ROM address 0x4010001c
9442 22:58:42.893129 Loading segment from ROM address 0x40100000
9443 22:58:42.893217 code (compression=1)
9444 22:58:42.900038 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9445 22:58:42.909692 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9446 22:58:42.909788 using LZMA
9447 22:58:42.918607 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9448 22:58:42.924895 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9449 22:58:42.928376 Loading segment from ROM address 0x4010001c
9450 22:58:42.931468 Entry Point 0x54601000
9451 22:58:42.931563 Loaded segments
9452 22:58:42.935066 NOTICE: MT8192 bl31_setup
9453 22:58:42.942157 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9454 22:58:42.945264 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9455 22:58:42.949081 WARNING: region 0:
9456 22:58:42.952259 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9457 22:58:42.952377 WARNING: region 1:
9458 22:58:42.958627 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9459 22:58:42.961805 WARNING: region 2:
9460 22:58:42.965429 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9461 22:58:42.968663 WARNING: region 3:
9462 22:58:42.971815 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9463 22:58:42.975617 WARNING: region 4:
9464 22:58:42.981917 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9465 22:58:42.982044 WARNING: region 5:
9466 22:58:42.985571 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9467 22:58:42.988604 WARNING: region 6:
9468 22:58:42.992177 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9469 22:58:42.995071 WARNING: region 7:
9470 22:58:42.998673 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9471 22:58:43.005112 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9472 22:58:43.008244 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9473 22:58:43.011958 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9474 22:58:43.018532 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9475 22:58:43.021665 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9476 22:58:43.028012 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9477 22:58:43.031694 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9478 22:58:43.035036 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9479 22:58:43.041511 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9480 22:58:43.045106 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9481 22:58:43.048399 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9482 22:58:43.054967 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9483 22:58:43.058144 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9484 22:58:43.065004 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9485 22:58:43.068131 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9486 22:58:43.071168 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9487 22:58:43.077844 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9488 22:58:43.081037 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9489 22:58:43.087982 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9490 22:58:43.091040 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9491 22:58:43.094805 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9492 22:58:43.101371 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9493 22:58:43.104301 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9494 22:58:43.108020 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9495 22:58:43.114271 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9496 22:58:43.117489 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9497 22:58:43.124076 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9498 22:58:43.127489 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9499 22:58:43.134314 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9500 22:58:43.137434 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9501 22:58:43.141197 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9502 22:58:43.147592 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9503 22:58:43.150686 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9504 22:58:43.153808 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9505 22:58:43.157177 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9506 22:58:43.163670 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9507 22:58:43.166866 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9508 22:58:43.170319 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9509 22:58:43.177092 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9510 22:58:43.180185 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9511 22:58:43.184032 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9512 22:58:43.187237 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9513 22:58:43.193575 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9514 22:58:43.196674 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9515 22:58:43.199840 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9516 22:58:43.203351 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9517 22:58:43.210075 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9518 22:58:43.213649 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9519 22:58:43.216737 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9520 22:58:43.223668 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9521 22:58:43.226844 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9522 22:58:43.233532 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9523 22:58:43.236712 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9524 22:58:43.243204 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9525 22:58:43.246345 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9526 22:58:43.250002 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9527 22:58:43.256741 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9528 22:58:43.259619 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9529 22:58:43.266307 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9530 22:58:43.269922 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9531 22:58:43.276212 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9532 22:58:43.279883 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9533 22:58:43.286174 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9534 22:58:43.289872 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9535 22:58:43.292945 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9536 22:58:43.299244 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9537 22:58:43.303204 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9538 22:58:43.309405 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9539 22:58:43.312412 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9540 22:58:43.319525 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9541 22:58:43.322517 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9542 22:58:43.325813 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9543 22:58:43.332192 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9544 22:58:43.335801 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9545 22:58:43.342640 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9546 22:58:43.345676 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9547 22:58:43.352496 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9548 22:58:43.355606 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9549 22:58:43.362265 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9550 22:58:43.365704 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9551 22:58:43.372175 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9552 22:58:43.375199 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9553 22:58:43.378953 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9554 22:58:43.385197 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9555 22:58:43.388917 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9556 22:58:43.395289 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9557 22:58:43.398322 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9558 22:58:43.405260 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9559 22:58:43.408502 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9560 22:58:43.411693 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9561 22:58:43.418447 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9562 22:58:43.421486 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9563 22:58:43.428601 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9564 22:58:43.431904 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9565 22:58:43.438624 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9566 22:58:43.441745 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9567 22:58:43.445373 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9568 22:58:43.451740 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9569 22:58:43.454791 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9570 22:58:43.458524 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9571 22:58:43.461703 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9572 22:58:43.468235 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9573 22:58:43.471832 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9574 22:58:43.478507 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9575 22:58:43.481342 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9576 22:58:43.484898 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9577 22:58:43.491353 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9578 22:58:43.494932 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9579 22:58:43.501351 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9580 22:58:43.504616 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9581 22:58:43.507848 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9582 22:58:43.514780 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9583 22:58:43.518191 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9584 22:58:43.524345 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9585 22:58:43.528109 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9586 22:58:43.530967 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9587 22:58:43.537849 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9588 22:58:43.540921 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9589 22:58:43.544046 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9590 22:58:43.550856 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9591 22:58:43.554668 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9592 22:58:43.557883 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9593 22:58:43.560958 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9594 22:58:43.567266 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9595 22:58:43.571021 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9596 22:58:43.574171 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9597 22:58:43.580556 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9598 22:58:43.584200 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9599 22:58:43.590351 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9600 22:58:43.593956 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9601 22:58:43.597463 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9602 22:58:43.603989 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9603 22:58:43.607136 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9604 22:58:43.613512 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9605 22:58:43.617271 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9606 22:58:43.620376 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9607 22:58:43.627120 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9608 22:58:43.630193 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9609 22:58:43.636838 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9610 22:58:43.640462 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9611 22:58:43.643619 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9612 22:58:43.649936 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9613 22:58:43.653620 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9614 22:58:43.659800 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9615 22:58:43.663495 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9616 22:58:43.666501 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9617 22:58:43.672921 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9618 22:58:43.676632 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9619 22:58:43.683292 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9620 22:58:43.686424 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9621 22:58:43.689986 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9622 22:58:43.696648 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9623 22:58:43.699725 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9624 22:58:43.706116 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9625 22:58:43.709936 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9626 22:58:43.713135 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9627 22:58:43.719979 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9628 22:58:43.723133 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9629 22:58:43.726369 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9630 22:58:43.733413 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9631 22:58:43.736316 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9632 22:58:43.742942 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9633 22:58:43.745938 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9634 22:58:43.752836 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9635 22:58:43.755923 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9636 22:58:43.759164 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9637 22:58:43.765902 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9638 22:58:43.768974 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9639 22:58:43.775938 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9640 22:58:43.779098 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9641 22:58:43.782336 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9642 22:58:43.789008 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9643 22:58:43.792164 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9644 22:58:43.798838 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9645 22:58:43.801969 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9646 22:58:43.805065 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9647 22:58:43.811711 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9648 22:58:43.814802 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9649 22:58:43.821712 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9650 22:58:43.824943 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9651 22:58:43.828123 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9652 22:58:43.835162 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9653 22:58:43.838060 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9654 22:58:43.844866 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9655 22:58:43.847984 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9656 22:58:43.851474 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9657 22:58:43.857998 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9658 22:58:43.861075 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9659 22:58:43.867848 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9660 22:58:43.870899 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9661 22:58:43.877703 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9662 22:58:43.880959 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9663 22:58:43.884132 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9664 22:58:43.891013 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9665 22:58:43.894062 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9666 22:58:43.900477 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9667 22:58:43.904187 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9668 22:58:43.910822 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9669 22:58:43.913841 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9670 22:58:43.916817 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9671 22:58:43.923544 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9672 22:58:43.927195 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9673 22:58:43.933561 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9674 22:58:43.936733 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9675 22:58:43.943664 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9676 22:58:43.946820 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9677 22:58:43.949958 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9678 22:58:43.956548 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9679 22:58:43.960134 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9680 22:58:43.966238 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9681 22:58:43.970054 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9682 22:58:43.976176 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9683 22:58:43.979814 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9684 22:58:43.982986 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9685 22:58:43.989284 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9686 22:58:43.992962 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9687 22:58:43.999515 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9688 22:58:44.002746 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9689 22:58:44.008906 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9690 22:58:44.012140 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9691 22:58:44.015718 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9692 22:58:44.022463 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9693 22:58:44.025345 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9694 22:58:44.032257 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9695 22:58:44.035428 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9696 22:58:44.042249 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9697 22:58:44.045402 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9698 22:58:44.048557 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9699 22:58:44.054997 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9700 22:58:44.058650 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9701 22:58:44.061702 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9702 22:58:44.068260 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9703 22:58:44.071725 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9704 22:58:44.074752 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9705 22:58:44.078447 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9706 22:58:44.085036 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9707 22:58:44.088023 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9708 22:58:44.095063 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9709 22:58:44.098330 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9710 22:58:44.101154 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9711 22:58:44.107823 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9712 22:58:44.111632 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9713 22:58:44.114880 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9714 22:58:44.121017 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9715 22:58:44.124591 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9716 22:58:44.131174 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9717 22:58:44.134260 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9718 22:58:44.137943 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9719 22:58:44.144233 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9720 22:58:44.147561 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9721 22:58:44.150666 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9722 22:58:44.157224 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9723 22:58:44.161139 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9724 22:58:44.164328 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9725 22:58:44.170646 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9726 22:58:44.174207 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9727 22:58:44.180706 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9728 22:58:44.183915 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9729 22:58:44.186941 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9730 22:58:44.193699 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9731 22:58:44.196866 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9732 22:58:44.203950 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9733 22:58:44.207069 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9734 22:58:44.210117 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9735 22:58:44.216541 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9736 22:58:44.219707 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9737 22:58:44.223128 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9738 22:58:44.229833 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9739 22:58:44.233382 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9740 22:58:44.236342 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9741 22:58:44.243108 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9742 22:58:44.246153 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9743 22:58:44.249904 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9744 22:58:44.253155 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9745 22:58:44.259450 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9746 22:58:44.263227 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9747 22:58:44.266327 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9748 22:58:44.269450 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9749 22:58:44.276153 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9750 22:58:44.279203 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9751 22:58:44.282290 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9752 22:58:44.288752 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9753 22:58:44.292506 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9754 22:58:44.295531 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9755 22:58:44.302153 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9756 22:58:44.305368 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9757 22:58:44.312066 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9758 22:58:44.315254 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9759 22:58:44.322210 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9760 22:58:44.325290 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9761 22:58:44.328404 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9762 22:58:44.335398 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9763 22:58:44.338212 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9764 22:58:44.344954 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9765 22:58:44.348074 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9766 22:58:44.351502 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9767 22:58:44.358436 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9768 22:58:44.361576 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9769 22:58:44.368032 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9770 22:58:44.371165 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9771 22:58:44.378345 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9772 22:58:44.381410 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9773 22:58:44.384436 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9774 22:58:44.391066 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9775 22:58:44.394579 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9776 22:58:44.400861 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9777 22:58:44.403993 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9778 22:58:44.407610 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9779 22:58:44.414179 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9780 22:58:44.417324 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9781 22:58:44.423703 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9782 22:58:44.426997 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9783 22:58:44.433662 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9784 22:58:44.436884 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9785 22:58:44.440637 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9786 22:58:44.446761 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9787 22:58:44.450440 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9788 22:58:44.456858 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9789 22:58:44.460292 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9790 22:58:44.466746 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9791 22:58:44.470012 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9792 22:58:44.473424 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9793 22:58:44.479794 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9794 22:58:44.483088 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9795 22:58:44.490194 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9796 22:58:44.493404 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9797 22:58:44.496504 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9798 22:58:44.503193 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9799 22:58:44.506645 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9800 22:58:44.512946 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9801 22:58:44.516669 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9802 22:58:44.522584 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9803 22:58:44.526174 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9804 22:58:44.529204 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9805 22:58:44.536429 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9806 22:58:44.539706 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9807 22:58:44.546413 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9808 22:58:44.549101 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9809 22:58:44.552708 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9810 22:58:44.559146 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9811 22:58:44.562194 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9812 22:58:44.569255 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9813 22:58:44.572345 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9814 22:58:44.578946 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9815 22:58:44.582078 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9816 22:58:44.585405 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9817 22:58:44.591891 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9818 22:58:44.595582 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9819 22:58:44.601830 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9820 22:58:44.604878 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9821 22:58:44.611655 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9822 22:58:44.614898 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9823 22:58:44.618004 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9824 22:58:44.624960 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9825 22:58:44.628135 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9826 22:58:44.634744 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9827 22:58:44.637852 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9828 22:58:44.644840 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9829 22:58:44.648247 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9830 22:58:44.654840 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9831 22:58:44.657611 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9832 22:58:44.661232 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9833 22:58:44.667549 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9834 22:58:44.671143 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9835 22:58:44.677384 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9836 22:58:44.680727 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9837 22:58:44.687177 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9838 22:58:44.690515 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9839 22:58:44.697098 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9840 22:58:44.700446 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9841 22:58:44.703521 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9842 22:58:44.710315 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9843 22:58:44.713917 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9844 22:58:44.720093 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9845 22:58:44.723300 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9846 22:58:44.730255 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9847 22:58:44.733473 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9848 22:58:44.736816 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9849 22:58:44.742793 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9850 22:58:44.746536 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9851 22:58:44.753126 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9852 22:58:44.755829 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9853 22:58:44.762681 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9854 22:58:44.766472 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9855 22:58:44.772945 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9856 22:58:44.775967 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9857 22:58:44.783012 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9858 22:58:44.786457 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9859 22:58:44.789003 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9860 22:58:44.795797 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9861 22:58:44.799129 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9862 22:58:44.805566 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9863 22:58:44.809325 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9864 22:58:44.815353 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9865 22:58:44.819127 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9866 22:58:44.825321 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9867 22:58:44.828624 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9868 22:58:44.835589 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9869 22:58:44.838756 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9870 22:58:44.842178 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9871 22:58:44.848332 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9872 22:58:44.851553 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9873 22:58:44.858601 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9874 22:58:44.862002 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9875 22:58:44.868023 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9876 22:58:44.871231 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9877 22:58:44.878122 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9878 22:58:44.881295 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9879 22:58:44.884497 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9880 22:58:44.891069 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9881 22:58:44.894291 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9882 22:58:44.900924 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9883 22:58:44.904125 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9884 22:58:44.911177 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9885 22:58:44.914472 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9886 22:58:44.921008 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9887 22:58:44.924393 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9888 22:58:44.930433 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9889 22:58:44.934083 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9890 22:58:44.940411 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9891 22:58:44.943723 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9892 22:58:44.950280 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9893 22:58:44.953577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9894 22:58:44.960376 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9895 22:58:44.963549 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9896 22:58:44.969826 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9897 22:58:44.973709 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9898 22:58:44.979999 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9899 22:58:44.986825 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9900 22:58:44.990073 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9901 22:58:44.996622 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9902 22:58:44.999880 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9903 22:58:45.006466 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9904 22:58:45.009718 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9905 22:58:45.012924 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9906 22:58:45.016139 INFO: [APUAPC] vio 0
9907 22:58:45.022845 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9908 22:58:45.026361 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9909 22:58:45.029260 INFO: [APUAPC] D0_APC_0: 0x400510
9910 22:58:45.032943 INFO: [APUAPC] D0_APC_1: 0x0
9911 22:58:45.036074 INFO: [APUAPC] D0_APC_2: 0x1540
9912 22:58:45.039505 INFO: [APUAPC] D0_APC_3: 0x0
9913 22:58:45.043228 INFO: [APUAPC] D1_APC_0: 0xffffffff
9914 22:58:45.046289 INFO: [APUAPC] D1_APC_1: 0xffffffff
9915 22:58:45.049499 INFO: [APUAPC] D1_APC_2: 0x3fffff
9916 22:58:45.052658 INFO: [APUAPC] D1_APC_3: 0x0
9917 22:58:45.055870 INFO: [APUAPC] D2_APC_0: 0xffffffff
9918 22:58:45.058902 INFO: [APUAPC] D2_APC_1: 0xffffffff
9919 22:58:45.062560 INFO: [APUAPC] D2_APC_2: 0x3fffff
9920 22:58:45.062633 INFO: [APUAPC] D2_APC_3: 0x0
9921 22:58:45.069338 INFO: [APUAPC] D3_APC_0: 0xffffffff
9922 22:58:45.072636 INFO: [APUAPC] D3_APC_1: 0xffffffff
9923 22:58:45.075674 INFO: [APUAPC] D3_APC_2: 0x3fffff
9924 22:58:45.075757 INFO: [APUAPC] D3_APC_3: 0x0
9925 22:58:45.079015 INFO: [APUAPC] D4_APC_0: 0xffffffff
9926 22:58:45.085718 INFO: [APUAPC] D4_APC_1: 0xffffffff
9927 22:58:45.088851 INFO: [APUAPC] D4_APC_2: 0x3fffff
9928 22:58:45.088971 INFO: [APUAPC] D4_APC_3: 0x0
9929 22:58:45.091878 INFO: [APUAPC] D5_APC_0: 0xffffffff
9930 22:58:45.095556 INFO: [APUAPC] D5_APC_1: 0xffffffff
9931 22:58:45.098679 INFO: [APUAPC] D5_APC_2: 0x3fffff
9932 22:58:45.101832 INFO: [APUAPC] D5_APC_3: 0x0
9933 22:58:45.105631 INFO: [APUAPC] D6_APC_0: 0xffffffff
9934 22:58:45.108823 INFO: [APUAPC] D6_APC_1: 0xffffffff
9935 22:58:45.112041 INFO: [APUAPC] D6_APC_2: 0x3fffff
9936 22:58:45.115179 INFO: [APUAPC] D6_APC_3: 0x0
9937 22:58:45.118323 INFO: [APUAPC] D7_APC_0: 0xffffffff
9938 22:58:45.121526 INFO: [APUAPC] D7_APC_1: 0xffffffff
9939 22:58:45.125338 INFO: [APUAPC] D7_APC_2: 0x3fffff
9940 22:58:45.128418 INFO: [APUAPC] D7_APC_3: 0x0
9941 22:58:45.131508 INFO: [APUAPC] D8_APC_0: 0xffffffff
9942 22:58:45.134639 INFO: [APUAPC] D8_APC_1: 0xffffffff
9943 22:58:45.138415 INFO: [APUAPC] D8_APC_2: 0x3fffff
9944 22:58:45.141503 INFO: [APUAPC] D8_APC_3: 0x0
9945 22:58:45.144611 INFO: [APUAPC] D9_APC_0: 0xffffffff
9946 22:58:45.148315 INFO: [APUAPC] D9_APC_1: 0xffffffff
9947 22:58:45.151382 INFO: [APUAPC] D9_APC_2: 0x3fffff
9948 22:58:45.154349 INFO: [APUAPC] D9_APC_3: 0x0
9949 22:58:45.157990 INFO: [APUAPC] D10_APC_0: 0xffffffff
9950 22:58:45.161071 INFO: [APUAPC] D10_APC_1: 0xffffffff
9951 22:58:45.164804 INFO: [APUAPC] D10_APC_2: 0x3fffff
9952 22:58:45.168034 INFO: [APUAPC] D10_APC_3: 0x0
9953 22:58:45.171048 INFO: [APUAPC] D11_APC_0: 0xffffffff
9954 22:58:45.174647 INFO: [APUAPC] D11_APC_1: 0xffffffff
9955 22:58:45.177908 INFO: [APUAPC] D11_APC_2: 0x3fffff
9956 22:58:45.180950 INFO: [APUAPC] D11_APC_3: 0x0
9957 22:58:45.184115 INFO: [APUAPC] D12_APC_0: 0xffffffff
9958 22:58:45.187343 INFO: [APUAPC] D12_APC_1: 0xffffffff
9959 22:58:45.190949 INFO: [APUAPC] D12_APC_2: 0x3fffff
9960 22:58:45.194099 INFO: [APUAPC] D12_APC_3: 0x0
9961 22:58:45.197848 INFO: [APUAPC] D13_APC_0: 0xffffffff
9962 22:58:45.201098 INFO: [APUAPC] D13_APC_1: 0xffffffff
9963 22:58:45.204462 INFO: [APUAPC] D13_APC_2: 0x3fffff
9964 22:58:45.207857 INFO: [APUAPC] D13_APC_3: 0x0
9965 22:58:45.210964 INFO: [APUAPC] D14_APC_0: 0xffffffff
9966 22:58:45.214072 INFO: [APUAPC] D14_APC_1: 0xffffffff
9967 22:58:45.217402 INFO: [APUAPC] D14_APC_2: 0x3fffff
9968 22:58:45.220801 INFO: [APUAPC] D14_APC_3: 0x0
9969 22:58:45.224145 INFO: [APUAPC] D15_APC_0: 0xffffffff
9970 22:58:45.230675 INFO: [APUAPC] D15_APC_1: 0xffffffff
9971 22:58:45.233839 INFO: [APUAPC] D15_APC_2: 0x3fffff
9972 22:58:45.233960 INFO: [APUAPC] D15_APC_3: 0x0
9973 22:58:45.237129 INFO: [APUAPC] APC_CON: 0x4
9974 22:58:45.240259 INFO: [NOCDAPC] D0_APC_0: 0x0
9975 22:58:45.243962 INFO: [NOCDAPC] D0_APC_1: 0x0
9976 22:58:45.247170 INFO: [NOCDAPC] D1_APC_0: 0x0
9977 22:58:45.250312 INFO: [NOCDAPC] D1_APC_1: 0xfff
9978 22:58:45.253387 INFO: [NOCDAPC] D2_APC_0: 0x0
9979 22:58:45.257208 INFO: [NOCDAPC] D2_APC_1: 0xfff
9980 22:58:45.260319 INFO: [NOCDAPC] D3_APC_0: 0x0
9981 22:58:45.263407 INFO: [NOCDAPC] D3_APC_1: 0xfff
9982 22:58:45.263520 INFO: [NOCDAPC] D4_APC_0: 0x0
9983 22:58:45.266723 INFO: [NOCDAPC] D4_APC_1: 0xfff
9984 22:58:45.270017 INFO: [NOCDAPC] D5_APC_0: 0x0
9985 22:58:45.273254 INFO: [NOCDAPC] D5_APC_1: 0xfff
9986 22:58:45.276515 INFO: [NOCDAPC] D6_APC_0: 0x0
9987 22:58:45.280335 INFO: [NOCDAPC] D6_APC_1: 0xfff
9988 22:58:45.283474 INFO: [NOCDAPC] D7_APC_0: 0x0
9989 22:58:45.286566 INFO: [NOCDAPC] D7_APC_1: 0xfff
9990 22:58:45.289734 INFO: [NOCDAPC] D8_APC_0: 0x0
9991 22:58:45.292996 INFO: [NOCDAPC] D8_APC_1: 0xfff
9992 22:58:45.296198 INFO: [NOCDAPC] D9_APC_0: 0x0
9993 22:58:45.299915 INFO: [NOCDAPC] D9_APC_1: 0xfff
9994 22:58:45.300037 INFO: [NOCDAPC] D10_APC_0: 0x0
9995 22:58:45.303153 INFO: [NOCDAPC] D10_APC_1: 0xfff
9996 22:58:45.306442 INFO: [NOCDAPC] D11_APC_0: 0x0
9997 22:58:45.309709 INFO: [NOCDAPC] D11_APC_1: 0xfff
9998 22:58:45.313038 INFO: [NOCDAPC] D12_APC_0: 0x0
9999 22:58:45.316488 INFO: [NOCDAPC] D12_APC_1: 0xfff
10000 22:58:45.319175 INFO: [NOCDAPC] D13_APC_0: 0x0
10001 22:58:45.323075 INFO: [NOCDAPC] D13_APC_1: 0xfff
10002 22:58:45.326470 INFO: [NOCDAPC] D14_APC_0: 0x0
10003 22:58:45.329671 INFO: [NOCDAPC] D14_APC_1: 0xfff
10004 22:58:45.332359 INFO: [NOCDAPC] D15_APC_0: 0x0
10005 22:58:45.335586 INFO: [NOCDAPC] D15_APC_1: 0xfff
10006 22:58:45.338966 INFO: [NOCDAPC] APC_CON: 0x4
10007 22:58:45.342270 INFO: [APUAPC] set_apusys_apc done
10008 22:58:45.346001 INFO: [DEVAPC] devapc_init done
10009 22:58:45.349247 INFO: GICv3 without legacy support detected.
10010 22:58:45.352358 INFO: ARM GICv3 driver initialized in EL3
10011 22:58:45.355483 INFO: Maximum SPI INTID supported: 639
10012 22:58:45.359176 INFO: BL31: Initializing runtime services
10013 22:58:45.365481 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10014 22:58:45.369004 INFO: SPM: enable CPC mode
10015 22:58:45.375444 INFO: mcdi ready for mcusys-off-idle and system suspend
10016 22:58:45.378694 INFO: BL31: Preparing for EL3 exit to normal world
10017 22:58:45.382075 INFO: Entry point address = 0x80000000
10018 22:58:45.385000 INFO: SPSR = 0x8
10019 22:58:45.390407
10020 22:58:45.390489
10021 22:58:45.390557
10022 22:58:45.393565 Starting depthcharge on Spherion...
10023 22:58:45.393638
10024 22:58:45.393699 Wipe memory regions:
10025 22:58:45.393759
10026 22:58:45.394373 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10027 22:58:45.394477 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10028 22:58:45.394563 Setting prompt string to ['asurada:']
10029 22:58:45.394639 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10030 22:58:45.396683 [0x00000040000000, 0x00000054600000)
10031 22:58:45.519318
10032 22:58:45.519454 [0x00000054660000, 0x00000080000000)
10033 22:58:45.779942
10034 22:58:45.780093 [0x000000821a7280, 0x000000ffe64000)
10035 22:58:46.524632
10036 22:58:46.524817 [0x00000100000000, 0x00000240000000)
10037 22:58:48.415146
10038 22:58:48.418070 Initializing XHCI USB controller at 0x11200000.
10039 22:58:49.456407
10040 22:58:49.459428 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10041 22:58:49.459549
10042 22:58:49.459651
10043 22:58:49.459750
10044 22:58:49.460070 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10046 22:58:49.560428 asurada: tftpboot 192.168.201.1 10597681/tftp-deploy-1n2if2r1/kernel/image.itb 10597681/tftp-deploy-1n2if2r1/kernel/cmdline
10047 22:58:49.560641 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10048 22:58:49.560768 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10049 22:58:49.564804 tftpboot 192.168.201.1 10597681/tftp-deploy-1n2if2r1/kernel/image.itp-deploy-1n2if2r1/kernel/cmdline
10050 22:58:49.564924
10051 22:58:49.565021 Waiting for link
10052 22:58:49.725208
10053 22:58:49.725393 R8152: Initializing
10054 22:58:49.725507
10055 22:58:49.728112 Version 6 (ocp_data = 5c30)
10056 22:58:49.728224
10057 22:58:49.732029 R8152: Done initializing
10058 22:58:49.732139
10059 22:58:49.732241 Adding net device
10060 22:58:51.635833
10061 22:58:51.636009 done.
10062 22:58:51.636139
10063 22:58:51.636257 MAC: 00:24:32:30:78:ff
10064 22:58:51.636373
10065 22:58:51.639122 Sending DHCP discover... done.
10066 22:58:51.639219
10067 22:58:51.642129 Waiting for reply... done.
10068 22:58:51.642241
10069 22:58:51.645560 Sending DHCP request... done.
10070 22:58:51.645671
10071 22:58:51.651059 Waiting for reply... done.
10072 22:58:51.651169
10073 22:58:51.651283 My ip is 192.168.201.21
10074 22:58:51.651377
10075 22:58:51.654291 The DHCP server ip is 192.168.201.1
10076 22:58:51.654401
10077 22:58:51.660885 TFTP server IP predefined by user: 192.168.201.1
10078 22:58:51.660998
10079 22:58:51.667728 Bootfile predefined by user: 10597681/tftp-deploy-1n2if2r1/kernel/image.itb
10080 22:58:51.667841
10081 22:58:51.670838 Sending tftp read request... done.
10082 22:58:51.670954
10083 22:58:51.674568 Waiting for the transfer...
10084 22:58:51.674674
10085 22:58:52.318456 00000000 ################################################################
10086 22:58:52.318619
10087 22:58:52.975483 00080000 ################################################################
10088 22:58:52.975644
10089 22:58:53.613309 00100000 ################################################################
10090 22:58:53.613455
10091 22:58:54.231894 00180000 ################################################################
10092 22:58:54.232173
10093 22:58:54.868522 00200000 ################################################################
10094 22:58:54.868679
10095 22:58:55.531849 00280000 ################################################################
10096 22:58:55.532002
10097 22:58:56.187039 00300000 ################################################################
10098 22:58:56.187204
10099 22:58:56.839955 00380000 ################################################################
10100 22:58:56.840134
10101 22:58:57.491699 00400000 ################################################################
10102 22:58:57.491912
10103 22:58:58.139808 00480000 ################################################################
10104 22:58:58.139965
10105 22:58:58.787642 00500000 ################################################################
10106 22:58:58.787795
10107 22:58:59.436483 00580000 ################################################################
10108 22:58:59.436658
10109 22:59:00.074978 00600000 ################################################################
10110 22:59:00.075132
10111 22:59:00.718528 00680000 ################################################################
10112 22:59:00.718671
10113 22:59:01.356432 00700000 ################################################################
10114 22:59:01.356597
10115 22:59:01.989927 00780000 ################################################################
10116 22:59:01.990079
10117 22:59:02.630635 00800000 ################################################################
10118 22:59:02.630822
10119 22:59:03.206722 00880000 ################################################################
10120 22:59:03.206899
10121 22:59:03.752205 00900000 ################################################################
10122 22:59:03.752372
10123 22:59:04.293807 00980000 ################################################################
10124 22:59:04.293953
10125 22:59:04.852267 00a00000 ################################################################
10126 22:59:04.852411
10127 22:59:05.405906 00a80000 ################################################################
10128 22:59:05.406044
10129 22:59:05.959127 00b00000 ################################################################
10130 22:59:05.959289
10131 22:59:06.518000 00b80000 ################################################################
10132 22:59:06.518142
10133 22:59:07.084098 00c00000 ################################################################
10134 22:59:07.084271
10135 22:59:07.659465 00c80000 ################################################################
10136 22:59:07.659664
10137 22:59:08.224998 00d00000 ################################################################
10138 22:59:08.225207
10139 22:59:08.813823 00d80000 ################################################################
10140 22:59:08.813991
10141 22:59:09.377098 00e00000 ################################################################
10142 22:59:09.377256
10143 22:59:09.968705 00e80000 ################################################################
10144 22:59:09.968908
10145 22:59:10.556891 00f00000 ################################################################
10146 22:59:10.557087
10147 22:59:11.159466 00f80000 ################################################################
10148 22:59:11.159664
10149 22:59:11.748433 01000000 ################################################################
10150 22:59:11.748609
10151 22:59:12.339393 01080000 ################################################################
10152 22:59:12.339569
10153 22:59:12.926832 01100000 ################################################################
10154 22:59:12.927015
10155 22:59:13.506373 01180000 ################################################################
10156 22:59:13.506548
10157 22:59:14.069256 01200000 ################################################################
10158 22:59:14.069419
10159 22:59:14.622340 01280000 ################################################################
10160 22:59:14.622494
10161 22:59:15.169774 01300000 ################################################################
10162 22:59:15.169934
10163 22:59:15.704884 01380000 ################################################################
10164 22:59:15.705035
10165 22:59:16.249397 01400000 ################################################################
10166 22:59:16.249546
10167 22:59:16.794250 01480000 ################################################################
10168 22:59:16.794402
10169 22:59:17.327417 01500000 ################################################################
10170 22:59:17.327569
10171 22:59:17.855731 01580000 ################################################################
10172 22:59:17.855945
10173 22:59:18.406557 01600000 ################################################################
10174 22:59:18.406703
10175 22:59:18.977107 01680000 ################################################################
10176 22:59:18.977284
10177 22:59:19.565915 01700000 ################################################################
10178 22:59:19.566063
10179 22:59:20.107656 01780000 ################################################################
10180 22:59:20.107804
10181 22:59:20.635319 01800000 ################################################################
10182 22:59:20.635453
10183 22:59:21.179152 01880000 ################################################################
10184 22:59:21.179315
10185 22:59:21.719688 01900000 ################################################################
10186 22:59:21.720088
10187 22:59:22.293542 01980000 ################################################################
10188 22:59:22.293722
10189 22:59:22.827382 01a00000 ################################################################
10190 22:59:22.827531
10191 22:59:23.359289 01a80000 ################################################################
10192 22:59:23.359438
10193 22:59:23.904930 01b00000 ################################################################
10194 22:59:23.905115
10195 22:59:24.443085 01b80000 ################################################################
10196 22:59:24.443234
10197 22:59:24.974442 01c00000 ################################################################
10198 22:59:24.974630
10199 22:59:25.517130 01c80000 ################################################################
10200 22:59:25.517281
10201 22:59:26.066862 01d00000 ################################################################
10202 22:59:26.067037
10203 22:59:26.612793 01d80000 ################################################################
10204 22:59:26.612955
10205 22:59:27.151482 01e00000 ################################################################
10206 22:59:27.151645
10207 22:59:27.695531 01e80000 ################################################################
10208 22:59:27.695674
10209 22:59:28.243804 01f00000 ################################################################
10210 22:59:28.243953
10211 22:59:28.787893 01f80000 ################################################################
10212 22:59:28.788070
10213 22:59:29.345423 02000000 ################################################################
10214 22:59:29.345558
10215 22:59:29.895186 02080000 ################################################################
10216 22:59:29.895363
10217 22:59:30.438661 02100000 ################################################################
10218 22:59:30.438848
10219 22:59:30.985152 02180000 ################################################################
10220 22:59:30.985318
10221 22:59:31.513132 02200000 ################################################################
10222 22:59:31.513363
10223 22:59:32.059030 02280000 ################################################################
10224 22:59:32.059209
10225 22:59:32.614169 02300000 ################################################################
10226 22:59:32.614348
10227 22:59:33.159219 02380000 ################################################################
10228 22:59:33.159370
10229 22:59:33.704483 02400000 ################################################################
10230 22:59:33.704630
10231 22:59:34.257639 02480000 ################################################################
10232 22:59:34.257828
10233 22:59:34.821793 02500000 ################################################################
10234 22:59:34.821984
10235 22:59:35.388280 02580000 ################################################################
10236 22:59:35.388464
10237 22:59:35.946744 02600000 ################################################################
10238 22:59:35.946940
10239 22:59:36.497273 02680000 ################################################################
10240 22:59:36.497456
10241 22:59:37.053543 02700000 ################################################################
10242 22:59:37.053686
10243 22:59:37.590369 02780000 ################################################################
10244 22:59:37.590545
10245 22:59:38.133675 02800000 ################################################################
10246 22:59:38.133854
10247 22:59:38.651701 02880000 ################################################################
10248 22:59:38.651896
10249 22:59:39.173954 02900000 ################################################################
10250 22:59:39.174141
10251 22:59:39.697512 02980000 ################################################################
10252 22:59:39.697705
10253 22:59:40.223160 02a00000 ################################################################
10254 22:59:40.223316
10255 22:59:40.749806 02a80000 ################################################################
10256 22:59:40.749957
10257 22:59:41.294218 02b00000 ################################################################
10258 22:59:41.294373
10259 22:59:41.858500 02b80000 ################################################################
10260 22:59:41.858756
10261 22:59:42.437552 02c00000 ################################################################
10262 22:59:42.437747
10263 22:59:43.021239 02c80000 ################################################################
10264 22:59:43.021455
10265 22:59:43.608438 02d00000 ################################################################
10266 22:59:43.608654
10267 22:59:44.194821 02d80000 ################################################################
10268 22:59:44.195077
10269 22:59:44.790331 02e00000 ################################################################
10270 22:59:44.790534
10271 22:59:45.391178 02e80000 ################################################################
10272 22:59:45.391366
10273 22:59:45.982235 02f00000 ################################################################
10274 22:59:45.982399
10275 22:59:46.487114 02f80000 ######################################################## done.
10276 22:59:46.487270
10277 22:59:46.490031 The bootfile was 50260730 bytes long.
10278 22:59:46.490124
10279 22:59:46.493354 Sending tftp read request... done.
10280 22:59:46.493443
10281 22:59:46.493531 Waiting for the transfer...
10282 22:59:46.493613
10283 22:59:46.497063 00000000 # done.
10284 22:59:46.497152
10285 22:59:46.503327 Command line loaded dynamically from TFTP file: 10597681/tftp-deploy-1n2if2r1/kernel/cmdline
10286 22:59:46.503417
10287 22:59:46.516783 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10288 22:59:46.516923
10289 22:59:46.517028 Loading FIT.
10290 22:59:46.517116
10291 22:59:46.519769 Image ramdisk-1 has 40125825 bytes.
10292 22:59:46.519861
10293 22:59:46.522805 Image fdt-1 has 46924 bytes.
10294 22:59:46.522900
10295 22:59:46.526567 Image kernel-1 has 10085945 bytes.
10296 22:59:46.526651
10297 22:59:46.532673 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10298 22:59:46.536652
10299 22:59:46.552859 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10300 22:59:46.553000
10301 22:59:46.555826 Choosing best match conf-1 for compat google,spherion-rev2.
10302 22:59:46.561349
10303 22:59:46.565625 Connected to device vid:did:rid of 1ae0:0028:00
10304 22:59:46.572865
10305 22:59:46.576475 tpm_get_response: command 0x17b, return code 0x0
10306 22:59:46.576584
10307 22:59:46.579446 ec_init: CrosEC protocol v3 supported (256, 248)
10308 22:59:46.583770
10309 22:59:46.586631 tpm_cleanup: add release locality here.
10310 22:59:46.586735
10311 22:59:46.586835 Shutting down all USB controllers.
10312 22:59:46.590012
10313 22:59:46.590117 Removing current net device
10314 22:59:46.590211
10315 22:59:46.596730 Exiting depthcharge with code 4 at timestamp: 90481065
10316 22:59:46.596840
10317 22:59:46.600162 LZMA decompressing kernel-1 to 0x821a6718
10318 22:59:46.600266
10319 22:59:46.603497 LZMA decompressing kernel-1 to 0x40000000
10320 22:59:47.869966
10321 22:59:47.870148 jumping to kernel
10322 22:59:47.870889 end: 2.2.4 bootloader-commands (duration 00:01:02) [common]
10323 22:59:47.871032 start: 2.2.5 auto-login-action (timeout 00:03:23) [common]
10324 22:59:47.871139 Setting prompt string to ['Linux version [0-9]']
10325 22:59:47.871242 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10326 22:59:47.871340 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10327 22:59:47.952373
10328 22:59:47.955890 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10329 22:59:47.959262 start: 2.2.5.1 login-action (timeout 00:03:23) [common]
10330 22:59:47.959421 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10331 22:59:47.959544 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10332 22:59:47.959652 Using line separator: #'\n'#
10333 22:59:47.959829 No login prompt set.
10334 22:59:47.959926 Parsing kernel messages
10335 22:59:47.960011 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10336 22:59:47.960262 [login-action] Waiting for messages, (timeout 00:03:23)
10337 22:59:47.978955 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1612582-arm64-gcc-10-defconfig-arm64-chromebook-7xwc5) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 22:41:02 UTC 2023
10338 22:59:47.982453 [ 0.000000] random: crng init done
10339 22:59:47.986055 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10340 22:59:47.988963 [ 0.000000] efi: UEFI not found.
10341 22:59:47.998620 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10342 22:59:48.005405 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10343 22:59:48.015436 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10344 22:59:48.025244 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10345 22:59:48.031808 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10346 22:59:48.038555 [ 0.000000] printk: bootconsole [mtk8250] enabled
10347 22:59:48.044694 [ 0.000000] NUMA: No NUMA configuration found
10348 22:59:48.051402 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10349 22:59:48.055084 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10350 22:59:48.057865 [ 0.000000] Zone ranges:
10351 22:59:48.064896 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10352 22:59:48.067654 [ 0.000000] DMA32 empty
10353 22:59:48.074325 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10354 22:59:48.078053 [ 0.000000] Movable zone start for each node
10355 22:59:48.081154 [ 0.000000] Early memory node ranges
10356 22:59:48.087700 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10357 22:59:48.094617 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10358 22:59:48.100814 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10359 22:59:48.107585 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10360 22:59:48.110680 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10361 22:59:48.120261 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10362 22:59:48.176838 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10363 22:59:48.182763 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10364 22:59:48.189903 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10365 22:59:48.192791 [ 0.000000] psci: probing for conduit method from DT.
10366 22:59:48.199717 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10367 22:59:48.202535 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10368 22:59:48.209525 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10369 22:59:48.212656 [ 0.000000] psci: SMC Calling Convention v1.2
10370 22:59:48.219541 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10371 22:59:48.222352 [ 0.000000] Detected VIPT I-cache on CPU0
10372 22:59:48.229243 [ 0.000000] CPU features: detected: GIC system register CPU interface
10373 22:59:48.235897 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10374 22:59:48.242544 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10375 22:59:48.248967 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10376 22:59:48.259024 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10377 22:59:48.265794 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10378 22:59:48.268415 [ 0.000000] alternatives: applying boot alternatives
10379 22:59:48.275809 [ 0.000000] Fallback order for Node 0: 0
10380 22:59:48.282302 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10381 22:59:48.285466 [ 0.000000] Policy zone: Normal
10382 22:59:48.298381 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10383 22:59:48.308774 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10384 22:59:48.318193 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10385 22:59:48.328320 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10386 22:59:48.335075 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10387 22:59:48.338114 <6>[ 0.000000] software IO TLB: area num 8.
10388 22:59:48.394324 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10389 22:59:48.543566 <6>[ 0.000000] Memory: 7933752K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 419016K reserved, 32768K cma-reserved)
10390 22:59:48.550000 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10391 22:59:48.556769 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10392 22:59:48.560006 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10393 22:59:48.566620 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10394 22:59:48.572991 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10395 22:59:48.576707 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10396 22:59:48.586538 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10397 22:59:48.593005 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10398 22:59:48.599596 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10399 22:59:48.606312 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10400 22:59:48.609377 <6>[ 0.000000] GICv3: 608 SPIs implemented
10401 22:59:48.612565 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10402 22:59:48.619238 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10403 22:59:48.622574 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10404 22:59:48.628964 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10405 22:59:48.642661 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10406 22:59:48.655498 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10407 22:59:48.662296 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10408 22:59:48.670373 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10409 22:59:48.683052 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10410 22:59:48.689830 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10411 22:59:48.696618 <6>[ 0.009225] Console: colour dummy device 80x25
10412 22:59:48.706520 <6>[ 0.013972] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10413 22:59:48.713212 <6>[ 0.024414] pid_max: default: 32768 minimum: 301
10414 22:59:48.716231 <6>[ 0.029288] LSM: Security Framework initializing
10415 22:59:48.722761 <6>[ 0.034226] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10416 22:59:48.732777 <6>[ 0.042040] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10417 22:59:48.742679 <6>[ 0.051465] cblist_init_generic: Setting adjustable number of callback queues.
10418 22:59:48.746093 <6>[ 0.058918] cblist_init_generic: Setting shift to 3 and lim to 1.
10419 22:59:48.752546 <6>[ 0.065257] cblist_init_generic: Setting shift to 3 and lim to 1.
10420 22:59:48.759186 <6>[ 0.071703] rcu: Hierarchical SRCU implementation.
10421 22:59:48.765764 <6>[ 0.076717] rcu: Max phase no-delay instances is 1000.
10422 22:59:48.771991 <6>[ 0.083774] EFI services will not be available.
10423 22:59:48.775928 <6>[ 0.088743] smp: Bringing up secondary CPUs ...
10424 22:59:48.783238 <6>[ 0.093796] Detected VIPT I-cache on CPU1
10425 22:59:48.790208 <6>[ 0.093868] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10426 22:59:48.796467 <6>[ 0.093898] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10427 22:59:48.800163 <6>[ 0.094227] Detected VIPT I-cache on CPU2
10428 22:59:48.806612 <6>[ 0.094273] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10429 22:59:48.816238 <6>[ 0.094290] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10430 22:59:48.819946 <6>[ 0.094537] Detected VIPT I-cache on CPU3
10431 22:59:48.826531 <6>[ 0.094578] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10432 22:59:48.832681 <6>[ 0.094592] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10433 22:59:48.836410 <6>[ 0.094897] CPU features: detected: Spectre-v4
10434 22:59:48.843100 <6>[ 0.094903] CPU features: detected: Spectre-BHB
10435 22:59:48.846091 <6>[ 0.094910] Detected PIPT I-cache on CPU4
10436 22:59:48.852562 <6>[ 0.094967] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10437 22:59:48.859153 <6>[ 0.094984] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10438 22:59:48.865888 <6>[ 0.095278] Detected PIPT I-cache on CPU5
10439 22:59:48.872811 <6>[ 0.095341] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10440 22:59:48.878845 <6>[ 0.095358] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10441 22:59:48.882455 <6>[ 0.095642] Detected PIPT I-cache on CPU6
10442 22:59:48.889062 <6>[ 0.095706] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10443 22:59:48.898804 <6>[ 0.095723] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10444 22:59:48.901794 <6>[ 0.096022] Detected PIPT I-cache on CPU7
10445 22:59:48.908808 <6>[ 0.096087] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10446 22:59:48.915537 <6>[ 0.096103] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10447 22:59:48.918531 <6>[ 0.096150] smp: Brought up 1 node, 8 CPUs
10448 22:59:48.925409 <6>[ 0.237573] SMP: Total of 8 processors activated.
10449 22:59:48.928565 <6>[ 0.242525] CPU features: detected: 32-bit EL0 Support
10450 22:59:48.938401 <6>[ 0.247921] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10451 22:59:48.945053 <6>[ 0.256721] CPU features: detected: Common not Private translations
10452 22:59:48.951240 <6>[ 0.263236] CPU features: detected: CRC32 instructions
10453 22:59:48.958500 <6>[ 0.268621] CPU features: detected: RCpc load-acquire (LDAPR)
10454 22:59:48.961318 <6>[ 0.274581] CPU features: detected: LSE atomic instructions
10455 22:59:48.967785 <6>[ 0.280362] CPU features: detected: Privileged Access Never
10456 22:59:48.974353 <6>[ 0.286177] CPU features: detected: RAS Extension Support
10457 22:59:48.981159 <6>[ 0.291786] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10458 22:59:48.984289 <6>[ 0.299008] CPU: All CPU(s) started at EL2
10459 22:59:48.990855 <6>[ 0.303324] alternatives: applying system-wide alternatives
10460 22:59:49.001081 <6>[ 0.314041] devtmpfs: initialized
10461 22:59:49.017030 <6>[ 0.323017] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10462 22:59:49.023162 <6>[ 0.332982] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10463 22:59:49.029822 <6>[ 0.341000] pinctrl core: initialized pinctrl subsystem
10464 22:59:49.033523 <6>[ 0.347640] DMI not present or invalid.
10465 22:59:49.039787 <6>[ 0.352047] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10466 22:59:49.049509 <6>[ 0.358925] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10467 22:59:49.056152 <6>[ 0.366507] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10468 22:59:49.065875 <6>[ 0.374715] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10469 22:59:49.069417 <6>[ 0.382958] audit: initializing netlink subsys (disabled)
10470 22:59:49.079680 <5>[ 0.388651] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10471 22:59:49.085679 <6>[ 0.389356] thermal_sys: Registered thermal governor 'step_wise'
10472 22:59:49.092371 <6>[ 0.396617] thermal_sys: Registered thermal governor 'power_allocator'
10473 22:59:49.095387 <6>[ 0.402873] cpuidle: using governor menu
10474 22:59:49.102071 <6>[ 0.413833] NET: Registered PF_QIPCRTR protocol family
10475 22:59:49.108636 <6>[ 0.419313] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10476 22:59:49.115185 <6>[ 0.426416] ASID allocator initialised with 32768 entries
10477 22:59:49.118863 <6>[ 0.432981] Serial: AMBA PL011 UART driver
10478 22:59:49.128621 <4>[ 0.441601] Trying to register duplicate clock ID: 134
10479 22:59:49.184587 <6>[ 0.500788] KASLR enabled
10480 22:59:49.199060 <6>[ 0.508517] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10481 22:59:49.205828 <6>[ 0.515529] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10482 22:59:49.211969 <6>[ 0.522020] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10483 22:59:49.218382 <6>[ 0.529022] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10484 22:59:49.225170 <6>[ 0.535511] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10485 22:59:49.232140 <6>[ 0.542515] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10486 22:59:49.238640 <6>[ 0.549002] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10487 22:59:49.245281 <6>[ 0.556009] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10488 22:59:49.248259 <6>[ 0.563486] ACPI: Interpreter disabled.
10489 22:59:49.256897 <6>[ 0.569866] iommu: Default domain type: Translated
10490 22:59:49.263611 <6>[ 0.575026] iommu: DMA domain TLB invalidation policy: strict mode
10491 22:59:49.266713 <5>[ 0.581684] SCSI subsystem initialized
10492 22:59:49.273596 <6>[ 0.585927] usbcore: registered new interface driver usbfs
10493 22:59:49.279922 <6>[ 0.591662] usbcore: registered new interface driver hub
10494 22:59:49.283409 <6>[ 0.597215] usbcore: registered new device driver usb
10495 22:59:49.290595 <6>[ 0.603323] pps_core: LinuxPPS API ver. 1 registered
10496 22:59:49.300220 <6>[ 0.608515] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10497 22:59:49.303772 <6>[ 0.617859] PTP clock support registered
10498 22:59:49.306993 <6>[ 0.622097] EDAC MC: Ver: 3.0.0
10499 22:59:49.314208 <6>[ 0.627266] FPGA manager framework
10500 22:59:49.320920 <6>[ 0.630945] Advanced Linux Sound Architecture Driver Initialized.
10501 22:59:49.323886 <6>[ 0.637716] vgaarb: loaded
10502 22:59:49.330625 <6>[ 0.640876] clocksource: Switched to clocksource arch_sys_counter
10503 22:59:49.334028 <5>[ 0.647307] VFS: Disk quotas dquot_6.6.0
10504 22:59:49.340711 <6>[ 0.651491] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10505 22:59:49.344163 <6>[ 0.658682] pnp: PnP ACPI: disabled
10506 22:59:49.352240 <6>[ 0.665359] NET: Registered PF_INET protocol family
10507 22:59:49.361784 <6>[ 0.670945] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10508 22:59:49.373991 <6>[ 0.683239] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10509 22:59:49.383745 <6>[ 0.692053] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10510 22:59:49.390436 <6>[ 0.700026] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10511 22:59:49.399850 <6>[ 0.708724] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10512 22:59:49.406640 <6>[ 0.718463] TCP: Hash tables configured (established 65536 bind 65536)
10513 22:59:49.412802 <6>[ 0.725325] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10514 22:59:49.423184 <6>[ 0.732522] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10515 22:59:49.429274 <6>[ 0.740222] NET: Registered PF_UNIX/PF_LOCAL protocol family
10516 22:59:49.435890 <6>[ 0.746383] RPC: Registered named UNIX socket transport module.
10517 22:59:49.439452 <6>[ 0.752535] RPC: Registered udp transport module.
10518 22:59:49.446058 <6>[ 0.757466] RPC: Registered tcp transport module.
10519 22:59:49.452683 <6>[ 0.762399] RPC: Registered tcp NFSv4.1 backchannel transport module.
10520 22:59:49.455631 <6>[ 0.769066] PCI: CLS 0 bytes, default 64
10521 22:59:49.459009 <6>[ 0.773415] Unpacking initramfs...
10522 22:59:49.480071 <6>[ 0.789560] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10523 22:59:49.489715 <6>[ 0.798186] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10524 22:59:49.493420 <6>[ 0.807023] kvm [1]: IPA Size Limit: 40 bits
10525 22:59:49.499649 <6>[ 0.811549] kvm [1]: GICv3: no GICV resource entry
10526 22:59:49.503131 <6>[ 0.816571] kvm [1]: disabling GICv2 emulation
10527 22:59:49.509431 <6>[ 0.821262] kvm [1]: GIC system register CPU interface enabled
10528 22:59:49.513201 <6>[ 0.827416] kvm [1]: vgic interrupt IRQ18
10529 22:59:49.519953 <6>[ 0.831766] kvm [1]: VHE mode initialized successfully
10530 22:59:49.526183 <5>[ 0.838171] Initialise system trusted keyrings
10531 22:59:49.533095 <6>[ 0.842969] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10532 22:59:49.540021 <6>[ 0.852989] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10533 22:59:49.546628 <5>[ 0.859389] NFS: Registering the id_resolver key type
10534 22:59:49.550147 <5>[ 0.864693] Key type id_resolver registered
10535 22:59:49.556529 <5>[ 0.869109] Key type id_legacy registered
10536 22:59:49.563274 <6>[ 0.873406] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10537 22:59:49.570006 <6>[ 0.880327] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10538 22:59:49.576147 <6>[ 0.888043] 9p: Installing v9fs 9p2000 file system support
10539 22:59:49.612385 <5>[ 0.925016] Key type asymmetric registered
10540 22:59:49.615275 <5>[ 0.929348] Asymmetric key parser 'x509' registered
10541 22:59:49.625035 <6>[ 0.934491] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10542 22:59:49.628792 <6>[ 0.942103] io scheduler mq-deadline registered
10543 22:59:49.631826 <6>[ 0.946879] io scheduler kyber registered
10544 22:59:49.651113 <6>[ 0.963978] EINJ: ACPI disabled.
10545 22:59:49.683635 <4>[ 0.989886] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10546 22:59:49.693328 <4>[ 1.000519] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10547 22:59:49.708603 <6>[ 1.021399] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10548 22:59:49.716172 <6>[ 1.029395] printk: console [ttyS0] disabled
10549 22:59:49.744327 <6>[ 1.054039] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10550 22:59:49.750950 <6>[ 1.063518] printk: console [ttyS0] enabled
10551 22:59:49.753981 <6>[ 1.063518] printk: console [ttyS0] enabled
10552 22:59:49.760671 <6>[ 1.072414] printk: bootconsole [mtk8250] disabled
10553 22:59:49.764204 <6>[ 1.072414] printk: bootconsole [mtk8250] disabled
10554 22:59:49.770507 <6>[ 1.083543] SuperH (H)SCI(F) driver initialized
10555 22:59:49.774014 <6>[ 1.088807] msm_serial: driver initialized
10556 22:59:49.787947 <6>[ 1.097724] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10557 22:59:49.797661 <6>[ 1.106270] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10558 22:59:49.804377 <6>[ 1.114813] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10559 22:59:49.814543 <6>[ 1.123441] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10560 22:59:49.823979 <6>[ 1.132147] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10561 22:59:49.830914 <6>[ 1.140869] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10562 22:59:49.840711 <6>[ 1.149410] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10563 22:59:49.850290 <6>[ 1.158231] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10564 22:59:49.856949 <6>[ 1.166780] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10565 22:59:49.869520 <6>[ 1.182326] loop: module loaded
10566 22:59:49.876063 <6>[ 1.188337] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10567 22:59:49.899059 <4>[ 1.211782] mtk-pmic-keys: Failed to locate of_node [id: -1]
10568 22:59:49.905864 <6>[ 1.218587] megasas: 07.719.03.00-rc1
10569 22:59:49.914970 <6>[ 1.228119] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10570 22:59:49.927225 <6>[ 1.240263] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10571 22:59:49.944194 <6>[ 1.256953] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10572 22:59:50.004018 <6>[ 1.310489] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10573 22:59:51.106630 <6>[ 2.419825] Freeing initrd memory: 39180K
10574 22:59:51.117233 <6>[ 2.430141] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10575 22:59:51.127802 <6>[ 2.441039] tun: Universal TUN/TAP device driver, 1.6
10576 22:59:51.131302 <6>[ 2.447087] thunder_xcv, ver 1.0
10577 22:59:51.134441 <6>[ 2.450595] thunder_bgx, ver 1.0
10578 22:59:51.137582 <6>[ 2.454088] nicpf, ver 1.0
10579 22:59:51.148527 <6>[ 2.458095] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10580 22:59:51.151646 <6>[ 2.465570] hns3: Copyright (c) 2017 Huawei Corporation.
10581 22:59:51.158158 <6>[ 2.471155] hclge is initializing
10582 22:59:51.161654 <6>[ 2.474735] e1000: Intel(R) PRO/1000 Network Driver
10583 22:59:51.168107 <6>[ 2.479864] e1000: Copyright (c) 1999-2006 Intel Corporation.
10584 22:59:51.174401 <6>[ 2.485877] e1000e: Intel(R) PRO/1000 Network Driver
10585 22:59:51.177878 <6>[ 2.491092] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10586 22:59:51.184249 <6>[ 2.497277] igb: Intel(R) Gigabit Ethernet Network Driver
10587 22:59:51.191184 <6>[ 2.502927] igb: Copyright (c) 2007-2014 Intel Corporation.
10588 22:59:51.197719 <6>[ 2.508766] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10589 22:59:51.204526 <6>[ 2.515283] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10590 22:59:51.207686 <6>[ 2.521745] sky2: driver version 1.30
10591 22:59:51.213922 <6>[ 2.526733] VFIO - User Level meta-driver version: 0.3
10592 22:59:51.222175 <6>[ 2.534961] usbcore: registered new interface driver usb-storage
10593 22:59:51.228341 <6>[ 2.541403] usbcore: registered new device driver onboard-usb-hub
10594 22:59:51.237194 <6>[ 2.550507] mt6397-rtc mt6359-rtc: registered as rtc0
10595 22:59:51.247489 <6>[ 2.555998] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T22:59:51 UTC (1686005991)
10596 22:59:51.250951 <6>[ 2.565611] i2c_dev: i2c /dev entries driver
10597 22:59:51.267547 <6>[ 2.577295] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10598 22:59:51.274678 <6>[ 2.587454] sdhci: Secure Digital Host Controller Interface driver
10599 22:59:51.280989 <6>[ 2.593891] sdhci: Copyright(c) Pierre Ossman
10600 22:59:51.287385 <6>[ 2.599286] Synopsys Designware Multimedia Card Interface Driver
10601 22:59:51.291033 <6>[ 2.605906] mmc0: CQHCI version 5.10
10602 22:59:51.297173 <6>[ 2.606436] sdhci-pltfm: SDHCI platform and OF driver helper
10603 22:59:51.304876 <6>[ 2.618082] ledtrig-cpu: registered to indicate activity on CPUs
10604 22:59:51.315229 <6>[ 2.625282] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10605 22:59:51.322075 <6>[ 2.632679] usbcore: registered new interface driver usbhid
10606 22:59:51.325179 <6>[ 2.638513] usbhid: USB HID core driver
10607 22:59:51.331753 <6>[ 2.642778] spi_master spi0: will run message pump with realtime priority
10608 22:59:51.379333 <6>[ 2.685584] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10609 22:59:51.398738 <6>[ 2.701476] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10610 22:59:51.402425 <6>[ 2.715042] mmc0: Command Queue Engine enabled
10611 22:59:51.409602 <6>[ 2.717364] cros-ec-spi spi0.0: Chrome EC device registered
10612 22:59:51.415871 <6>[ 2.719784] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10613 22:59:51.418991 <6>[ 2.732826] mmcblk0: mmc0:0001 DA4128 116 GiB
10614 22:59:51.433304 <6>[ 2.742890] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10615 22:59:51.440035 <6>[ 2.742978] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10616 22:59:51.446105 <6>[ 2.754322] NET: Registered PF_PACKET protocol family
10617 22:59:51.449649 <6>[ 2.759546] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10618 22:59:51.456297 <6>[ 2.763536] 9pnet: Installing 9P2000 support
10619 22:59:51.459333 <6>[ 2.769323] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10620 22:59:51.466001 <5>[ 2.773222] Key type dns_resolver registered
10621 22:59:51.473078 <6>[ 2.779066] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10622 22:59:51.475836 <6>[ 2.783431] registered taskstats version 1
10623 22:59:51.479431 <5>[ 2.793823] Loading compiled-in X.509 certificates
10624 22:59:51.513753 <4>[ 2.820473] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10625 22:59:51.523933 <4>[ 2.831197] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10626 22:59:51.534571 <3>[ 2.844129] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10627 22:59:51.546673 <6>[ 2.859581] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10628 22:59:51.553384 <6>[ 2.866344] xhci-mtk 11200000.usb: xHCI Host Controller
10629 22:59:51.559694 <6>[ 2.871841] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10630 22:59:51.569919 <6>[ 2.879692] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10631 22:59:51.576568 <6>[ 2.889145] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10632 22:59:51.583349 <6>[ 2.895392] xhci-mtk 11200000.usb: xHCI Host Controller
10633 22:59:51.589922 <6>[ 2.900892] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10634 22:59:51.596559 <6>[ 2.908557] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10635 22:59:51.603434 <6>[ 2.916452] hub 1-0:1.0: USB hub found
10636 22:59:51.606541 <6>[ 2.920491] hub 1-0:1.0: 1 port detected
10637 22:59:51.616854 <6>[ 2.924853] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10638 22:59:51.619683 <6>[ 2.933675] hub 2-0:1.0: USB hub found
10639 22:59:51.622987 <6>[ 2.937710] hub 2-0:1.0: 1 port detected
10640 22:59:51.631601 <6>[ 2.944778] mtk-msdc 11f70000.mmc: Got CD GPIO
10641 22:59:51.652829 <6>[ 2.962453] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10642 22:59:51.659653 <6>[ 2.970482] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10643 22:59:51.668931 <4>[ 2.978456] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10644 22:59:51.678824 <6>[ 2.988120] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10645 22:59:51.685567 <6>[ 2.996204] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10646 22:59:51.696104 <6>[ 3.004225] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10647 22:59:51.701905 <6>[ 3.012159] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10648 22:59:51.709109 <6>[ 3.019982] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10649 22:59:51.718520 <6>[ 3.027803] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10650 22:59:51.728589 <6>[ 3.038450] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10651 22:59:51.738653 <6>[ 3.046830] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10652 22:59:51.745273 <6>[ 3.055183] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10653 22:59:51.755292 <6>[ 3.063526] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10654 22:59:51.761542 <6>[ 3.071869] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10655 22:59:51.771426 <6>[ 3.080212] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10656 22:59:51.778090 <6>[ 3.088555] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10657 22:59:51.787829 <6>[ 3.096900] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10658 22:59:51.794571 <6>[ 3.105244] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10659 22:59:51.804677 <6>[ 3.113591] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10660 22:59:51.811222 <6>[ 3.121935] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10661 22:59:51.821236 <6>[ 3.130279] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10662 22:59:51.827756 <6>[ 3.138621] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10663 22:59:51.837273 <6>[ 3.146966] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10664 22:59:51.843974 <6>[ 3.155311] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10665 22:59:51.851345 <6>[ 3.164226] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10666 22:59:51.858269 <6>[ 3.171697] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10667 22:59:51.865903 <6>[ 3.178816] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10668 22:59:51.876031 <6>[ 3.185969] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10669 22:59:51.882972 <6>[ 3.193320] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10670 22:59:51.892429 <6>[ 3.200250] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10671 22:59:51.899230 <6>[ 3.209391] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10672 22:59:51.909183 <6>[ 3.218528] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10673 22:59:51.919089 <6>[ 3.227830] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10674 22:59:51.929181 <6>[ 3.237305] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10675 22:59:51.939184 <6>[ 3.246785] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10676 22:59:51.948895 <6>[ 3.255913] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10677 22:59:51.955642 <6>[ 3.265390] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10678 22:59:51.965037 <6>[ 3.274518] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10679 22:59:51.975383 <6>[ 3.283820] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10680 22:59:51.985025 <6>[ 3.293986] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10681 22:59:51.995994 <6>[ 3.305870] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10682 22:59:52.035020 <6>[ 3.345151] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10683 22:59:52.189449 <6>[ 3.502442] hub 1-1:1.0: USB hub found
10684 22:59:52.192648 <6>[ 3.506907] hub 1-1:1.0: 4 ports detected
10685 22:59:52.315561 <6>[ 3.625253] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10686 22:59:52.339825 <6>[ 3.652690] hub 2-1:1.0: USB hub found
10687 22:59:52.342688 <6>[ 3.657066] hub 2-1:1.0: 3 ports detected
10688 22:59:52.514906 <6>[ 3.825153] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10689 22:59:52.647513 <6>[ 3.960434] hub 1-1.4:1.0: USB hub found
10690 22:59:52.650648 <6>[ 3.965106] hub 1-1.4:1.0: 2 ports detected
10691 22:59:52.727582 <6>[ 4.037394] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10692 22:59:52.947005 <6>[ 4.257154] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10693 22:59:53.139074 <6>[ 4.449156] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10694 23:00:04.283789 <6>[ 15.601698] ALSA device list:
10695 23:00:04.290006 <6>[ 15.604955] No soundcards found.
10696 23:00:04.303024 <6>[ 15.617383] Freeing unused kernel memory: 8384K
10697 23:00:04.306117 <6>[ 15.622314] Run /init as init process
10698 23:00:04.335769 <6>[ 15.650622] NET: Registered PF_INET6 protocol family
10699 23:00:04.342882 <6>[ 15.656782] Segment Routing with IPv6
10700 23:00:04.345894 <6>[ 15.660717] In-situ OAM (IOAM) with IPv6
10701 23:00:04.380446 <30>[ 15.675377] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10702 23:00:04.384070 <30>[ 15.699156] systemd[1]: Detected architecture arm64.
10703 23:00:04.384193
10704 23:00:04.390655 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10705 23:00:04.390769
10706 23:00:04.406585 <30>[ 15.721344] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10707 23:00:04.553066 <30>[ 15.864689] systemd[1]: Queued start job for default target Graphical Interface.
10708 23:00:04.583750 <30>[ 15.898423] systemd[1]: Created slice system-getty.slice.
10709 23:00:04.590616 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10710 23:00:04.607498 <30>[ 15.921732] systemd[1]: Created slice system-modprobe.slice.
10711 23:00:04.613717 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10712 23:00:04.631782 <30>[ 15.946281] systemd[1]: Created slice system-serial\x2dgetty.slice.
10713 23:00:04.641666 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10714 23:00:04.654873 <30>[ 15.969656] systemd[1]: Created slice User and Session Slice.
10715 23:00:04.661526 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10716 23:00:04.682606 <30>[ 15.993708] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10717 23:00:04.692424 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10718 23:00:04.710656 <30>[ 16.021658] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10719 23:00:04.716832 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10720 23:00:04.737391 <30>[ 16.045271] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10721 23:00:04.743650 <30>[ 16.057322] systemd[1]: Reached target Local Encrypted Volumes.
10722 23:00:04.750547 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10723 23:00:04.767120 <30>[ 16.081510] systemd[1]: Reached target Paths.
10724 23:00:04.770220 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10725 23:00:04.786607 <30>[ 16.101203] systemd[1]: Reached target Remote File Systems.
10726 23:00:04.793273 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10727 23:00:04.810510 <30>[ 16.125422] systemd[1]: Reached target Slices.
10728 23:00:04.817295 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10729 23:00:04.830654 <30>[ 16.145226] systemd[1]: Reached target Swap.
10730 23:00:04.833599 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10731 23:00:04.854016 <30>[ 16.165504] systemd[1]: Listening on initctl Compatibility Named Pipe.
10732 23:00:04.860905 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10733 23:00:04.867249 <30>[ 16.180237] systemd[1]: Listening on Journal Audit Socket.
10734 23:00:04.873935 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10735 23:00:04.887074 <30>[ 16.201470] systemd[1]: Listening on Journal Socket (/dev/log).
10736 23:00:04.893333 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10737 23:00:04.911317 <30>[ 16.225938] systemd[1]: Listening on Journal Socket.
10738 23:00:04.917817 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10739 23:00:04.934287 <30>[ 16.245582] systemd[1]: Listening on Network Service Netlink Socket.
10740 23:00:04.940965 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10741 23:00:04.955225 <30>[ 16.269938] systemd[1]: Listening on udev Control Socket.
10742 23:00:04.961844 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10743 23:00:04.979315 <30>[ 16.293859] systemd[1]: Listening on udev Kernel Socket.
10744 23:00:04.985763 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10745 23:00:05.023237 <30>[ 16.337554] systemd[1]: Mounting Huge Pages File System...
10746 23:00:05.029431 Mounting [0;1;39mHuge Pages File System[0m...
10747 23:00:05.044727 <30>[ 16.359330] systemd[1]: Mounting POSIX Message Queue File System...
10748 23:00:05.051635 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10749 23:00:05.068675 <30>[ 16.383345] systemd[1]: Mounting Kernel Debug File System...
10750 23:00:05.075029 Mounting [0;1;39mKernel Debug File System[0m...
10751 23:00:05.094308 <30>[ 16.405548] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10752 23:00:05.105419 <30>[ 16.416602] systemd[1]: Starting Create list of static device nodes for the current kernel...
10753 23:00:05.111661 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10754 23:00:05.167109 <30>[ 16.481584] systemd[1]: Starting Load Kernel Module configfs...
10755 23:00:05.173719 Starting [0;1;39mLoad Kernel Module configfs[0m...
10756 23:00:05.189029 <30>[ 16.503436] systemd[1]: Starting Load Kernel Module drm...
10757 23:00:05.195530 Starting [0;1;39mLoad Kernel Module drm[0m...
10758 23:00:05.214201 <30>[ 16.525359] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10759 23:00:05.258787 <30>[ 16.573736] systemd[1]: Starting Journal Service...
10760 23:00:05.262427 Starting [0;1;39mJournal Service[0m...
10761 23:00:05.281339 <30>[ 16.595898] systemd[1]: Starting Load Kernel Modules...
10762 23:00:05.287848 Starting [0;1;39mLoad Kernel Modules[0m...
10763 23:00:05.308714 <30>[ 16.620004] systemd[1]: Starting Remount Root and Kernel File Systems...
10764 23:00:05.315061 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10765 23:00:05.371588 <30>[ 16.686174] systemd[1]: Starting Coldplug All udev Devices...
10766 23:00:05.378103 Starting [0;1;39mColdplug All udev Devices[0m...
10767 23:00:05.393025 <30>[ 16.707795] systemd[1]: Started Journal Service.
10768 23:00:05.399663 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10769 23:00:05.416792 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10770 23:00:05.422990 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10771 23:00:05.442987 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10772 23:00:05.467545 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10773 23:00:05.483918 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10774 23:00:05.499801 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10775 23:00:05.515205 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10776 23:00:05.535387 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10777 23:00:05.550517 See 'systemctl status systemd-remount-fs.service' for details.
10778 23:00:05.599028 Mounting [0;1;39mKernel Configuration File System[0m...
10779 23:00:05.616975 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10780 23:00:05.634184 <46>[ 16.945892] systemd-journald[177]: Received client request to flush runtime journal.
10781 23:00:05.643184 Starting [0;1;39mLoad/Save Random Seed[0m...
10782 23:00:05.661525 Starting [0;1;39mApply Kernel Variables[0m...
10783 23:00:05.677833 Starting [0;1;39mCreate System Users[0m...
10784 23:00:05.699025 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10785 23:00:05.719208 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10786 23:00:05.731856 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10787 23:00:05.747252 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10788 23:00:05.763562 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10789 23:00:05.779241 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10790 23:00:05.823237 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10791 23:00:05.846334 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10792 23:00:05.863117 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10793 23:00:05.878439 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10794 23:00:05.918760 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10795 23:00:05.942166 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10796 23:00:05.967247 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10797 23:00:05.987883 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10798 23:00:06.051969 Starting [0;1;39mNetwork Service[0m...
10799 23:00:06.076479 Starting [0;1;39mNetwork Time Synchronization[0m...
10800 23:00:06.099460 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10801 23:00:06.160401 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10802 23:00:06.176017 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10803 23:00:06.193216 <6>[ 17.504570] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10804 23:00:06.199809 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10805 23:00:06.210563 <6>[ 17.525015] remoteproc remoteproc0: scp is available
10806 23:00:06.216744 <6>[ 17.531396] remoteproc remoteproc0: powering up scp
10807 23:00:06.223475 <6>[ 17.532676] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10808 23:00:06.233534 <6>[ 17.536598] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10809 23:00:06.240068 <3>[ 17.542133] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10810 23:00:06.249788 <3>[ 17.542169] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10811 23:00:06.256533 <3>[ 17.542178] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10812 23:00:06.266395 <6>[ 17.544195] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10813 23:00:06.273075 <6>[ 17.553009] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10814 23:00:06.279705 <3>[ 17.560174] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10815 23:00:06.289456 <3>[ 17.560195] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10816 23:00:06.296192 <3>[ 17.560239] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10817 23:00:06.302821 <3>[ 17.560251] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10818 23:00:06.312684 <3>[ 17.560259] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10819 23:00:06.322302 <6>[ 17.561125] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10820 23:00:06.329045 <3>[ 17.562482] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10821 23:00:06.335721 <3>[ 17.565716] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10822 23:00:06.345610 <3>[ 17.565734] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10823 23:00:06.352345 <3>[ 17.565742] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10824 23:00:06.362297 <3>[ 17.611972] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10825 23:00:06.368580 <6>[ 17.616999] usbcore: registered new interface driver r8152
10826 23:00:06.375331 <3>[ 17.623892] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10827 23:00:06.385081 <3>[ 17.623902] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10828 23:00:06.391601 <3>[ 17.623915] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10829 23:00:06.398030 <3>[ 17.623923] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10830 23:00:06.404599 <6>[ 17.656987] mc: Linux media interface: v0.10
10831 23:00:06.411530 <3>[ 17.673675] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10832 23:00:06.417989 <6>[ 17.694636] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10833 23:00:06.428085 <6>[ 17.695257] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10834 23:00:06.434663 <6>[ 17.708022] usbcore: registered new interface driver cdc_ether
10835 23:00:06.440777 <4>[ 17.708063] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10836 23:00:06.447398 <4>[ 17.708443] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10837 23:00:06.454125 <6>[ 17.711412] remoteproc remoteproc0: remote processor scp is now up
10838 23:00:06.460881 <6>[ 17.713841] videodev: Linux video capture interface: v2.00
10839 23:00:06.467831 <6>[ 17.740464] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10840 23:00:06.473977 <6>[ 17.760319] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10841 23:00:06.484317 <6>[ 17.785430] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10842 23:00:06.487108 <6>[ 17.788707] pci_bus 0000:00: root bus resource [bus 00-ff]
10843 23:00:06.497632 [[0;32m OK [<6>[ 17.808914] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10844 23:00:06.507225 0m] Found device<4>[ 17.816841] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10845 23:00:06.520251 [0;1;39m/dev/t<6>[ 17.817405] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10846 23:00:06.520382 tyS0[0m.
10847 23:00:06.530653 <6>[ 17.824062] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10848 23:00:06.536738 <4>[ 17.828772] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10849 23:00:06.543489 <6>[ 17.839129] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10850 23:00:06.553194 <6>[ 17.847712] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10851 23:00:06.563557 <6>[ 17.848109] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10852 23:00:06.569751 <6>[ 17.857967] usbcore: registered new interface driver r8153_ecm
10853 23:00:06.576594 <6>[ 17.863719] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10854 23:00:06.586674 <6>[ 17.864834] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10855 23:00:06.593341 <6>[ 17.884115] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10856 23:00:06.596477 <6>[ 17.889074] pci 0000:00:00.0: supports D1 D2
10857 23:00:06.602819 <6>[ 17.890162] Bluetooth: Core ver 2.22
10858 23:00:06.606088 <6>[ 17.890232] NET: Registered PF_BLUETOOTH protocol family
10859 23:00:06.612635 <6>[ 17.890235] Bluetooth: HCI device and connection manager initialized
10860 23:00:06.619789 <6>[ 17.890263] Bluetooth: HCI socket layer initialized
10861 23:00:06.622928 <6>[ 17.890275] Bluetooth: L2CAP socket layer initialized
10862 23:00:06.629605 <6>[ 17.890294] Bluetooth: SCO socket layer initialized
10863 23:00:06.632542 <6>[ 17.897134] r8152 2-1.3:1.0 eth0: v1.12.13
10864 23:00:06.639555 <6>[ 17.904795] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10865 23:00:06.649185 <6>[ 17.914928] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10866 23:00:06.655835 <6>[ 17.919676] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10867 23:00:06.669219 <6>[ 17.923581] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10868 23:00:06.675315 <6>[ 17.927231] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10869 23:00:06.679023 <6>[ 17.928442] usbcore: registered new interface driver btusb
10870 23:00:06.685614 <6>[ 17.928619] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10871 23:00:06.692254 <6>[ 17.930320] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10872 23:00:06.702517 <4>[ 17.934366] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10873 23:00:06.709666 <6>[ 17.936575] usbcore: registered new interface driver uvcvideo
10874 23:00:06.716334 <6>[ 17.938849] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10875 23:00:06.726022 <6>[ 17.938881] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10876 23:00:06.729420 <3>[ 17.944231] Bluetooth: hci0: Failed to load firmware file (-2)
10877 23:00:06.739893 <6>[ 17.949344] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10878 23:00:06.742790 <3>[ 17.953673] Bluetooth: hci0: Failed to set up firmware (-2)
10879 23:00:06.749877 <6>[ 17.960667] pci 0000:01:00.0: supports D1 D2
10880 23:00:06.760541 <4>[ 17.967590] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10881 23:00:06.767251 <6>[ 17.975911] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10882 23:00:06.773322 <4>[ 17.977399] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10883 23:00:06.779925 <4>[ 17.977399] Fallback method does not support PEC.
10884 23:00:06.786591 <3>[ 18.025018] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10885 23:00:06.796906 <3>[ 18.026178] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10886 23:00:06.803752 <6>[ 18.045274] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10887 23:00:06.813943 <3>[ 18.054156] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10888 23:00:06.820122 <6>[ 18.058213] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10889 23:00:06.830633 <3>[ 18.079859] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10890 23:00:06.837176 <3>[ 18.082391] power_supply sbs-5-000b: driver failed to report `capacity_level' property: -6
10891 23:00:06.847008 <6>[ 18.085821] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10892 23:00:06.854103 <3>[ 18.119838] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 23:00:06.864161 <6>[ 18.123758] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10894 23:00:06.870837 <3>[ 18.152942] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10895 23:00:06.880693 <6>[ 18.157903] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10896 23:00:06.887352 <3>[ 18.187135] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 23:00:06.898274 <6>[ 18.191442] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10898 23:00:06.901286 <6>[ 18.216211] pci 0000:00:00.0: PCI bridge to [bus 01]
10899 23:00:06.911013 <6>[ 18.216219] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10900 23:00:06.914621 <6>[ 18.216429] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10901 23:00:06.924962 <3>[ 18.219213] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10902 23:00:06.935243 [[0;32m OK [<3>[ 18.241077] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10903 23:00:06.941546 <6>[ 18.245556] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10904 23:00:06.948217 0m] Created slic<6>[ 18.261555] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10905 23:00:06.951835 e [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10906 23:00:06.969354 <5>[ 18.280918] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10907 23:00:06.976268 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10908 23:00:06.989132 <5>[ 18.300678] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10909 23:00:06.995398 <4>[ 18.307617] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10910 23:00:07.002668 <6>[ 18.316596] cfg80211: failed to load regulatory.db
10911 23:00:07.008982 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10912 23:00:07.022843 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10913 23:00:07.048986 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkil<6>[ 18.360218] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10914 23:00:07.049108 l Watch[0m.
10915 23:00:07.055358 <6>[ 18.368618] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10916 23:00:07.081255 <6>[ 18.396436] mt7921e 0000:01:00.0: ASIC revision: 79610010
10917 23:00:07.098354 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10918 23:00:07.114165 Starting [0;1;39mNetwork Name Resolution[0m...
10919 23:00:07.135367 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10920 23:00:07.156165 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10921 23:00:07.176773 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10922 23:00:07.189632 <4>[ 18.496699] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10923 23:00:07.196260 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10924 23:00:07.214716 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10925 23:00:07.238384 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10926 23:00:07.254640 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10927 23:00:07.274271 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10928 23:00:07.316080 <4>[ 18.624110] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10929 23:00:07.347697 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10930 23:00:07.372817 Starting [0;1;39mUser Login Management[0m...
10931 23:00:07.388819 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10932 23:00:07.408642 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10933 23:00:07.428261 <4>[ 18.736344] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10934 23:00:07.439277 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10935 23:00:07.455548 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10936 23:00:07.473854 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10937 23:00:07.526819 Starting [0;1;39mPermit User Sessions[0m...
10938 23:00:07.553362 <4>[ 18.861578] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10939 23:00:07.560042 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10940 23:00:07.569167 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10941 23:00:07.579702 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10942 23:00:07.598176 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10943 23:00:07.614960 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10944 23:00:07.634748 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10945 23:00:07.654600 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10946 23:00:07.675196 <4>[ 18.983801] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10947 23:00:07.742467 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10948 23:00:07.770802 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10949 23:00:07.800252 <4>[ 19.108838] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10950 23:00:07.800399
10951 23:00:07.800501
10952 23:00:07.807378 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10953 23:00:07.807490
10954 23:00:07.810208 debian-bullseye-arm64 login: root (automatic login)
10955 23:00:07.810320
10956 23:00:07.810416
10957 23:00:07.835206 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 22:41:02 UTC 2023 aarch64
10958 23:00:07.835335
10959 23:00:07.841424 The programs included with the Debian GNU/Linux system are free software;
10960 23:00:07.848096 the exact distribution terms for each program are described in the
10961 23:00:07.851685 individual files in /usr/share/doc/*/copyright.
10962 23:00:07.851808
10963 23:00:07.858369 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10964 23:00:07.861522 permitted by applicable law.
10965 23:00:07.862009 Matched prompt #10: / #
10967 23:00:07.862415 Setting prompt string to ['/ #']
10968 23:00:07.862550 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10970 23:00:07.862926 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10971 23:00:07.863060 start: 2.2.6 expect-shell-connection (timeout 00:03:03) [common]
10972 23:00:07.863169 Setting prompt string to ['/ #']
10973 23:00:07.863264 Forcing a shell prompt, looking for ['/ #']
10975 23:00:07.913529 / #
10976 23:00:07.913731 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10977 23:00:07.913873 Waiting using forced prompt support (timeout 00:02:30)
10978 23:00:07.958947 <4>[ 19.231544] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10979 23:00:07.959110
10980 23:00:07.959424 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10981 23:00:07.959557 start: 2.2.7 export-device-env (timeout 00:03:03) [common]
10982 23:00:07.959697 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10983 23:00:07.959819 end: 2.2 depthcharge-retry (duration 00:01:57) [common]
10984 23:00:07.959943 end: 2 depthcharge-action (duration 00:01:57) [common]
10985 23:00:07.960070 start: 3 lava-test-retry (timeout 00:07:41) [common]
10986 23:00:07.960197 start: 3.1 lava-test-shell (timeout 00:07:41) [common]
10987 23:00:07.960305 Using namespace: common
10989 23:00:08.060668 / # #
10990 23:00:08.060892 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10991 23:00:08.061066 #<4>[ 19.351263] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10992 23:00:08.065120
10993 23:00:08.065411 Using /lava-10597681
10995 23:00:08.165796 / # export SHELL=/bin/sh
10996 23:00:08.166042 export SHELL=/bin/sh<4>[ 19.470907] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10997 23:00:08.170654
10999 23:00:08.271226 / # . /lava-10597681/environment
11000 23:00:08.282427 . /lava-10597681/environment<4>[ 19.590797] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11001 23:00:08.282537
11003 23:00:08.387022 / # /lava-10597681/bin/lava-test-runner /lava-10597681/0
11004 23:00:08.387191 Test shell timeout: 10s (minimum of the action and connection timeout)
11005 23:00:08.387521 <6>[ 19.655081] IPv6: ADDRCONF(NETDEV_CHANGE): enx0024323078ff: link becomes ready
11006 23:00:08.387601 /lava-10597681/bi<6>[ 19.663127] r8152 2-1.3:1.0 enx0024323078ff: carrier on
11007 23:00:08.390241 n/lava-test-run /lava-10597681/0<3>[ 19.705013] mt7921e 0000:01:00.0: hardware init failed
11008 23:00:08.390319
11009 23:00:08.430886 -sh: 5: /lava-10597681/bin/lava-test-run: not found
11010 23:00:34.839805 / # <6>[ 46.161231] vpu: disabling
11011 23:00:34.843430 <6>[ 46.164290] vproc2: disabling
11012 23:00:34.846358 <6>[ 46.167571] vproc1: disabling
11013 23:00:34.849897 <6>[ 46.170836] vaud18: disabling
11014 23:00:34.856663 <6>[ 46.174243] vsram_others: disabling
11015 23:00:34.859617 <6>[ 46.178119] va09: disabling
11016 23:00:34.863112 <6>[ 46.181227] vsram_md: disabling
11017 23:00:34.866030 <6>[ 46.184713] Vgpu: disabling
11019 23:07:48.961245 end: 3.1 lava-test-shell (duration 00:07:41) [common]
11021 23:07:48.962390 lava-test-retry failed: 1 of 1 attempts. 'lava-test-shell timed out after 461 seconds'
11023 23:07:48.963269 end: 3 lava-test-retry (duration 00:07:41) [common]
11025 23:07:48.964487 Cleaning after the job
11026 23:07:48.964984 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597681/tftp-deploy-1n2if2r1/ramdisk
11027 23:07:48.981466 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597681/tftp-deploy-1n2if2r1/kernel
11028 23:07:48.991803 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597681/tftp-deploy-1n2if2r1/dtb
11029 23:07:48.991975 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597681/tftp-deploy-1n2if2r1/modules
11030 23:07:48.997118 start: 4.1 power-off (timeout 00:00:30) [common]
11031 23:07:48.997282 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11032 23:07:49.075315 >> Command sent successfully.
11033 23:07:49.080446 Returned 0 in 0 seconds
11034 23:07:49.181455 end: 4.1 power-off (duration 00:00:00) [common]
11036 23:07:49.183144 start: 4.2 read-feedback (timeout 00:10:00) [common]
11037 23:07:49.184424 Listened to connection for namespace 'common' for up to 1s
11038 23:07:50.185034 Finalising connection for namespace 'common'
11039 23:07:50.185718 Disconnecting from shell: Finalise
11040 23:07:50.286808 end: 4.2 read-feedback (duration 00:00:01) [common]
11041 23:07:50.287524 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10597681
11042 23:07:50.384022 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10597681
11043 23:07:50.384215 TestError: A test failed to run, look at the error message.