Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 27
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 23
- Errors: 2
1 12:39:17.777965 lava-dispatcher, installed at version: 2023.05.1
2 12:39:17.778187 start: 0 validate
3 12:39:17.778318 Start time: 2023-06-14 12:39:17.778309+00:00 (UTC)
4 12:39:17.778452 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:39:17.778579 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230609.0%2Farm64%2Frootfs.cpio.gz exists
6 12:39:18.047109 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:39:18.047298 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:39:51.321723 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:39:51.322486 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:39:51.597150 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:39:51.597887 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:39:55.864344 validate duration: 38.09
14 12:39:55.864691 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:39:55.864822 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:39:55.864953 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:39:55.865177 Not decompressing ramdisk as can be used compressed.
18 12:39:55.865294 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230609.0/arm64/rootfs.cpio.gz
19 12:39:55.865383 saving as /var/lib/lava/dispatcher/tmp/10724861/tftp-deploy-sv2o19vw/ramdisk/rootfs.cpio.gz
20 12:39:55.865486 total size: 8200575 (7MB)
21 12:39:56.115733 progress 0% (0MB)
22 12:39:56.118236 progress 5% (0MB)
23 12:39:56.120619 progress 10% (0MB)
24 12:39:56.122827 progress 15% (1MB)
25 12:39:56.125266 progress 20% (1MB)
26 12:39:56.127420 progress 25% (1MB)
27 12:39:56.129839 progress 30% (2MB)
28 12:39:56.132033 progress 35% (2MB)
29 12:39:56.134379 progress 40% (3MB)
30 12:39:56.136571 progress 45% (3MB)
31 12:39:56.138982 progress 50% (3MB)
32 12:39:56.141146 progress 55% (4MB)
33 12:39:56.143525 progress 60% (4MB)
34 12:39:56.145689 progress 65% (5MB)
35 12:39:56.148062 progress 70% (5MB)
36 12:39:56.150251 progress 75% (5MB)
37 12:39:56.152547 progress 80% (6MB)
38 12:39:56.154690 progress 85% (6MB)
39 12:39:56.157108 progress 90% (7MB)
40 12:39:56.159233 progress 95% (7MB)
41 12:39:56.161576 progress 100% (7MB)
42 12:39:56.161753 7MB downloaded in 0.30s (26.40MB/s)
43 12:39:56.161936 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:39:56.162186 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:39:56.162274 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:39:56.162358 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:39:56.162493 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:39:56.162565 saving as /var/lib/lava/dispatcher/tmp/10724861/tftp-deploy-sv2o19vw/kernel/Image
50 12:39:56.162626 total size: 47581696 (45MB)
51 12:39:56.162686 No compression specified
52 12:39:56.163802 progress 0% (0MB)
53 12:39:56.175696 progress 5% (2MB)
54 12:39:56.187653 progress 10% (4MB)
55 12:39:56.199830 progress 15% (6MB)
56 12:39:56.212497 progress 20% (9MB)
57 12:39:56.224668 progress 25% (11MB)
58 12:39:56.236692 progress 30% (13MB)
59 12:39:56.248834 progress 35% (15MB)
60 12:39:56.260836 progress 40% (18MB)
61 12:39:56.272853 progress 45% (20MB)
62 12:39:56.284826 progress 50% (22MB)
63 12:39:56.296796 progress 55% (24MB)
64 12:39:56.309041 progress 60% (27MB)
65 12:39:56.321073 progress 65% (29MB)
66 12:39:56.333298 progress 70% (31MB)
67 12:39:56.345460 progress 75% (34MB)
68 12:39:56.357371 progress 80% (36MB)
69 12:39:56.369409 progress 85% (38MB)
70 12:39:56.381191 progress 90% (40MB)
71 12:39:56.392962 progress 95% (43MB)
72 12:39:56.404880 progress 100% (45MB)
73 12:39:56.405015 45MB downloaded in 0.24s (187.21MB/s)
74 12:39:56.405159 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:39:56.405391 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:39:56.405481 start: 1.3 download-retry (timeout 00:09:59) [common]
78 12:39:56.405567 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 12:39:56.405696 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:39:56.405794 saving as /var/lib/lava/dispatcher/tmp/10724861/tftp-deploy-sv2o19vw/dtb/mt8192-asurada-spherion-r0.dtb
81 12:39:56.405855 total size: 46924 (0MB)
82 12:39:56.405914 No compression specified
83 12:39:56.407005 progress 69% (0MB)
84 12:39:56.407272 progress 100% (0MB)
85 12:39:56.407422 0MB downloaded in 0.00s (28.59MB/s)
86 12:39:56.407540 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:39:56.407759 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:39:56.407843 start: 1.4 download-retry (timeout 00:09:59) [common]
90 12:39:56.407924 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 12:39:56.408037 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:39:56.408133 saving as /var/lib/lava/dispatcher/tmp/10724861/tftp-deploy-sv2o19vw/modules/modules.tar
93 12:39:56.408193 total size: 8536768 (8MB)
94 12:39:56.408251 Using unxz to decompress xz
95 12:39:56.412150 progress 0% (0MB)
96 12:39:56.433729 progress 5% (0MB)
97 12:39:56.461578 progress 10% (0MB)
98 12:39:56.492601 progress 15% (1MB)
99 12:39:56.516495 progress 20% (1MB)
100 12:39:56.540146 progress 25% (2MB)
101 12:39:56.564626 progress 30% (2MB)
102 12:39:56.587924 progress 35% (2MB)
103 12:39:56.614856 progress 40% (3MB)
104 12:39:56.639713 progress 45% (3MB)
105 12:39:56.665535 progress 50% (4MB)
106 12:39:56.690359 progress 55% (4MB)
107 12:39:56.715971 progress 60% (4MB)
108 12:39:56.741691 progress 65% (5MB)
109 12:39:56.766759 progress 70% (5MB)
110 12:39:56.791053 progress 75% (6MB)
111 12:39:56.815077 progress 80% (6MB)
112 12:39:56.838857 progress 85% (6MB)
113 12:39:56.863967 progress 90% (7MB)
114 12:39:56.889158 progress 95% (7MB)
115 12:39:56.911588 progress 100% (8MB)
116 12:39:56.918166 8MB downloaded in 0.51s (15.96MB/s)
117 12:39:56.918473 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:39:56.918774 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:39:56.918883 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 12:39:56.918995 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 12:39:56.919116 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:39:56.919243 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 12:39:56.919514 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10724861/lava-overlay-5unqmlrp
125 12:39:56.919684 makedir: /var/lib/lava/dispatcher/tmp/10724861/lava-overlay-5unqmlrp/lava-10724861/bin
126 12:39:56.919830 makedir: /var/lib/lava/dispatcher/tmp/10724861/lava-overlay-5unqmlrp/lava-10724861/tests
127 12:39:56.919969 makedir: /var/lib/lava/dispatcher/tmp/10724861/lava-overlay-5unqmlrp/lava-10724861/results
128 12:39:56.920163 Creating /var/lib/lava/dispatcher/tmp/10724861/lava-overlay-5unqmlrp/lava-10724861/bin/lava-add-keys
129 12:39:56.920321 Creating /var/lib/lava/dispatcher/tmp/10724861/lava-overlay-5unqmlrp/lava-10724861/bin/lava-add-sources
130 12:39:56.920468 Creating /var/lib/lava/dispatcher/tmp/10724861/lava-overlay-5unqmlrp/lava-10724861/bin/lava-background-process-start
131 12:39:56.920615 Creating /var/lib/lava/dispatcher/tmp/10724861/lava-overlay-5unqmlrp/lava-10724861/bin/lava-background-process-stop
132 12:39:56.920758 Creating /var/lib/lava/dispatcher/tmp/10724861/lava-overlay-5unqmlrp/lava-10724861/bin/lava-common-functions
133 12:39:56.920925 Creating /var/lib/lava/dispatcher/tmp/10724861/lava-overlay-5unqmlrp/lava-10724861/bin/lava-echo-ipv4
134 12:39:56.921092 Creating /var/lib/lava/dispatcher/tmp/10724861/lava-overlay-5unqmlrp/lava-10724861/bin/lava-install-packages
135 12:39:56.921258 Creating /var/lib/lava/dispatcher/tmp/10724861/lava-overlay-5unqmlrp/lava-10724861/bin/lava-installed-packages
136 12:39:56.921422 Creating /var/lib/lava/dispatcher/tmp/10724861/lava-overlay-5unqmlrp/lava-10724861/bin/lava-os-build
137 12:39:56.921585 Creating /var/lib/lava/dispatcher/tmp/10724861/lava-overlay-5unqmlrp/lava-10724861/bin/lava-probe-channel
138 12:39:56.921727 Creating /var/lib/lava/dispatcher/tmp/10724861/lava-overlay-5unqmlrp/lava-10724861/bin/lava-probe-ip
139 12:39:56.921866 Creating /var/lib/lava/dispatcher/tmp/10724861/lava-overlay-5unqmlrp/lava-10724861/bin/lava-target-ip
140 12:39:56.922005 Creating /var/lib/lava/dispatcher/tmp/10724861/lava-overlay-5unqmlrp/lava-10724861/bin/lava-target-mac
141 12:39:56.922143 Creating /var/lib/lava/dispatcher/tmp/10724861/lava-overlay-5unqmlrp/lava-10724861/bin/lava-target-storage
142 12:39:56.922289 Creating /var/lib/lava/dispatcher/tmp/10724861/lava-overlay-5unqmlrp/lava-10724861/bin/lava-test-case
143 12:39:56.922456 Creating /var/lib/lava/dispatcher/tmp/10724861/lava-overlay-5unqmlrp/lava-10724861/bin/lava-test-event
144 12:39:56.922622 Creating /var/lib/lava/dispatcher/tmp/10724861/lava-overlay-5unqmlrp/lava-10724861/bin/lava-test-feedback
145 12:39:56.922788 Creating /var/lib/lava/dispatcher/tmp/10724861/lava-overlay-5unqmlrp/lava-10724861/bin/lava-test-raise
146 12:39:56.922957 Creating /var/lib/lava/dispatcher/tmp/10724861/lava-overlay-5unqmlrp/lava-10724861/bin/lava-test-reference
147 12:39:56.923121 Creating /var/lib/lava/dispatcher/tmp/10724861/lava-overlay-5unqmlrp/lava-10724861/bin/lava-test-runner
148 12:39:56.923260 Creating /var/lib/lava/dispatcher/tmp/10724861/lava-overlay-5unqmlrp/lava-10724861/bin/lava-test-set
149 12:39:56.923401 Creating /var/lib/lava/dispatcher/tmp/10724861/lava-overlay-5unqmlrp/lava-10724861/bin/lava-test-shell
150 12:39:56.923547 Updating /var/lib/lava/dispatcher/tmp/10724861/lava-overlay-5unqmlrp/lava-10724861/bin/lava-install-packages (oe)
151 12:39:56.923732 Updating /var/lib/lava/dispatcher/tmp/10724861/lava-overlay-5unqmlrp/lava-10724861/bin/lava-installed-packages (oe)
152 12:39:56.923894 Creating /var/lib/lava/dispatcher/tmp/10724861/lava-overlay-5unqmlrp/lava-10724861/environment
153 12:39:56.924039 LAVA metadata
154 12:39:56.924155 - LAVA_JOB_ID=10724861
155 12:39:56.924259 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:39:56.924386 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 12:39:56.924484 skipped lava-vland-overlay
158 12:39:56.924604 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:39:56.924728 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 12:39:56.924832 skipped lava-multinode-overlay
161 12:39:56.924956 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:39:56.925081 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 12:39:56.925192 Loading test definitions
164 12:39:56.925330 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 12:39:56.925440 Using /lava-10724861 at stage 0
166 12:39:56.925872 uuid=10724861_1.5.2.3.1 testdef=None
167 12:39:56.925996 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:39:56.926123 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 12:39:56.926884 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:39:56.927250 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 12:39:56.928169 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:39:56.928531 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 12:39:56.929453 runner path: /var/lib/lava/dispatcher/tmp/10724861/lava-overlay-5unqmlrp/lava-10724861/0/tests/0_dmesg test_uuid 10724861_1.5.2.3.1
176 12:39:56.929652 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:39:56.930031 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:59) [common]
179 12:39:56.930137 Using /lava-10724861 at stage 1
180 12:39:56.930557 uuid=10724861_1.5.2.3.5 testdef=None
181 12:39:56.930681 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 12:39:56.930808 start: 1.5.2.3.6 test-overlay (timeout 00:09:59) [common]
183 12:39:56.931508 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 12:39:56.931873 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:59) [common]
186 12:39:56.933087 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 12:39:56.933349 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
189 12:39:56.934280 runner path: /var/lib/lava/dispatcher/tmp/10724861/lava-overlay-5unqmlrp/lava-10724861/1/tests/1_bootrr test_uuid 10724861_1.5.2.3.5
190 12:39:56.934491 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 12:39:56.934839 Creating lava-test-runner.conf files
193 12:39:56.934908 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10724861/lava-overlay-5unqmlrp/lava-10724861/0 for stage 0
194 12:39:56.935000 - 0_dmesg
195 12:39:56.935081 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10724861/lava-overlay-5unqmlrp/lava-10724861/1 for stage 1
196 12:39:56.935170 - 1_bootrr
197 12:39:56.935264 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 12:39:56.935348 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
199 12:39:56.943550 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 12:39:56.943677 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
201 12:39:56.943766 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 12:39:56.943852 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 12:39:56.943937 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
204 12:39:57.180032 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 12:39:57.180411 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
206 12:39:57.180533 extracting modules file /var/lib/lava/dispatcher/tmp/10724861/tftp-deploy-sv2o19vw/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10724861/extract-overlay-ramdisk-bnuz1wyo/ramdisk
207 12:39:57.384982 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 12:39:57.385176 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
209 12:39:57.385279 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10724861/compress-overlay-4boxd9tr/overlay-1.5.2.4.tar.gz to ramdisk
210 12:39:57.385350 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10724861/compress-overlay-4boxd9tr/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10724861/extract-overlay-ramdisk-bnuz1wyo/ramdisk
211 12:39:57.393455 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 12:39:57.393572 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
213 12:39:57.393662 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 12:39:57.393753 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
215 12:39:57.393834 Building ramdisk /var/lib/lava/dispatcher/tmp/10724861/extract-overlay-ramdisk-bnuz1wyo/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10724861/extract-overlay-ramdisk-bnuz1wyo/ramdisk
216 12:39:57.788721 >> 143719 blocks
217 12:40:00.106295 rename /var/lib/lava/dispatcher/tmp/10724861/extract-overlay-ramdisk-bnuz1wyo/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10724861/tftp-deploy-sv2o19vw/ramdisk/ramdisk.cpio.gz
218 12:40:00.106729 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 12:40:00.106866 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
220 12:40:00.106973 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
221 12:40:00.107082 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10724861/tftp-deploy-sv2o19vw/kernel/Image'
222 12:40:12.858567 Returned 0 in 12 seconds
223 12:40:12.959158 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10724861/tftp-deploy-sv2o19vw/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10724861/tftp-deploy-sv2o19vw/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10724861/tftp-deploy-sv2o19vw/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10724861/tftp-deploy-sv2o19vw/kernel/image.itb
224 12:40:13.338458 output: FIT description: Kernel Image image with one or more FDT blobs
225 12:40:13.338817 output: Created: Wed Jun 14 13:40:13 2023
226 12:40:13.338899 output: Image 0 (kernel-1)
227 12:40:13.338965 output: Description:
228 12:40:13.339027 output: Created: Wed Jun 14 13:40:13 2023
229 12:40:13.339088 output: Type: Kernel Image
230 12:40:13.339146 output: Compression: lzma compressed
231 12:40:13.339207 output: Data Size: 10442380 Bytes = 10197.64 KiB = 9.96 MiB
232 12:40:13.339269 output: Architecture: AArch64
233 12:40:13.339330 output: OS: Linux
234 12:40:13.339389 output: Load Address: 0x00000000
235 12:40:13.339448 output: Entry Point: 0x00000000
236 12:40:13.339505 output: Hash algo: crc32
237 12:40:13.339564 output: Hash value: ced21bfe
238 12:40:13.339616 output: Image 1 (fdt-1)
239 12:40:13.339674 output: Description: mt8192-asurada-spherion-r0
240 12:40:13.339728 output: Created: Wed Jun 14 13:40:13 2023
241 12:40:13.339782 output: Type: Flat Device Tree
242 12:40:13.339834 output: Compression: uncompressed
243 12:40:13.339886 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
244 12:40:13.339939 output: Architecture: AArch64
245 12:40:13.339991 output: Hash algo: crc32
246 12:40:13.340069 output: Hash value: 1df858fa
247 12:40:13.340138 output: Image 2 (ramdisk-1)
248 12:40:13.340190 output: Description: unavailable
249 12:40:13.340242 output: Created: Wed Jun 14 13:40:13 2023
250 12:40:13.340294 output: Type: RAMDisk Image
251 12:40:13.340347 output: Compression: Unknown Compression
252 12:40:13.340399 output: Data Size: 21230917 Bytes = 20733.32 KiB = 20.25 MiB
253 12:40:13.340451 output: Architecture: AArch64
254 12:40:13.340502 output: OS: Linux
255 12:40:13.340554 output: Load Address: unavailable
256 12:40:13.340606 output: Entry Point: unavailable
257 12:40:13.340658 output: Hash algo: crc32
258 12:40:13.340710 output: Hash value: 65294ae5
259 12:40:13.340766 output: Default Configuration: 'conf-1'
260 12:40:13.340818 output: Configuration 0 (conf-1)
261 12:40:13.340871 output: Description: mt8192-asurada-spherion-r0
262 12:40:13.340923 output: Kernel: kernel-1
263 12:40:13.340975 output: Init Ramdisk: ramdisk-1
264 12:40:13.341027 output: FDT: fdt-1
265 12:40:13.341078 output: Loadables: kernel-1
266 12:40:13.341130 output:
267 12:40:13.341320 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
268 12:40:13.341414 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
269 12:40:13.341519 end: 1.5 prepare-tftp-overlay (duration 00:00:16) [common]
270 12:40:13.341609 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
271 12:40:13.341701 No LXC device requested
272 12:40:13.341831 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 12:40:13.341933 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
274 12:40:13.342012 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 12:40:13.342081 Checking files for TFTP limit of 4294967296 bytes.
276 12:40:13.342566 end: 1 tftp-deploy (duration 00:00:17) [common]
277 12:40:13.342670 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 12:40:13.342760 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 12:40:13.342879 substitutions:
280 12:40:13.342945 - {DTB}: 10724861/tftp-deploy-sv2o19vw/dtb/mt8192-asurada-spherion-r0.dtb
281 12:40:13.343009 - {INITRD}: 10724861/tftp-deploy-sv2o19vw/ramdisk/ramdisk.cpio.gz
282 12:40:13.343068 - {KERNEL}: 10724861/tftp-deploy-sv2o19vw/kernel/Image
283 12:40:13.343124 - {LAVA_MAC}: None
284 12:40:13.343180 - {PRESEED_CONFIG}: None
285 12:40:13.343234 - {PRESEED_LOCAL}: None
286 12:40:13.343288 - {RAMDISK}: 10724861/tftp-deploy-sv2o19vw/ramdisk/ramdisk.cpio.gz
287 12:40:13.343341 - {ROOT_PART}: None
288 12:40:13.343395 - {ROOT}: None
289 12:40:13.343448 - {SERVER_IP}: 192.168.201.1
290 12:40:13.343501 - {TEE}: None
291 12:40:13.343555 Parsed boot commands:
292 12:40:13.343607 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 12:40:13.343815 Parsed boot commands: tftpboot 192.168.201.1 10724861/tftp-deploy-sv2o19vw/kernel/image.itb 10724861/tftp-deploy-sv2o19vw/kernel/cmdline
294 12:40:13.343904 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 12:40:13.343989 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 12:40:13.344120 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 12:40:13.344205 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 12:40:13.344278 Not connected, no need to disconnect.
299 12:40:13.344352 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 12:40:13.344436 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 12:40:13.344501 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-2'
302 12:40:13.348476 Setting prompt string to ['lava-test: # ']
303 12:40:13.349066 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 12:40:13.349189 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 12:40:13.349291 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 12:40:13.349380 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 12:40:13.349586 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
308 12:40:18.487730 >> Command sent successfully.
309 12:40:18.490060 Returned 0 in 5 seconds
310 12:40:18.590450 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 12:40:18.590793 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 12:40:18.590892 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 12:40:18.590983 Setting prompt string to 'Starting depthcharge on Spherion...'
315 12:40:18.591052 Changing prompt to 'Starting depthcharge on Spherion...'
316 12:40:18.591123 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 12:40:18.591387 [Enter `^Ec?' for help]
318 12:40:18.764584
319 12:40:18.764749
320 12:40:18.764821 F0: 102B 0000
321 12:40:18.764884
322 12:40:18.764942 F3: 1001 0000 [0200]
323 12:40:18.765001
324 12:40:18.767998 F3: 1001 0000
325 12:40:18.768117
326 12:40:18.768183 F7: 102D 0000
327 12:40:18.768245
328 12:40:18.772021 F1: 0000 0000
329 12:40:18.772127
330 12:40:18.772192 V0: 0000 0000 [0001]
331 12:40:18.772256
332 12:40:18.772315 00: 0007 8000
333 12:40:18.772375
334 12:40:18.774950 01: 0000 0000
335 12:40:18.775034
336 12:40:18.775100 BP: 0C00 0209 [0000]
337 12:40:18.775162
338 12:40:18.778638 G0: 1182 0000
339 12:40:18.778721
340 12:40:18.778786 EC: 0000 0021 [4000]
341 12:40:18.778848
342 12:40:18.782419 S7: 0000 0000 [0000]
343 12:40:18.782501
344 12:40:18.782567 CC: 0000 0000 [0001]
345 12:40:18.782628
346 12:40:18.786090 T0: 0000 0040 [010F]
347 12:40:18.786172
348 12:40:18.786238 Jump to BL
349 12:40:18.786298
350 12:40:18.811523
351 12:40:18.811609
352 12:40:18.811675
353 12:40:18.818236 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 12:40:18.821655 ARM64: Exception handlers installed.
355 12:40:18.825029 ARM64: Testing exception
356 12:40:18.829614 ARM64: Done test exception
357 12:40:18.836319 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 12:40:18.846760 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 12:40:18.853388 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 12:40:18.863135 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 12:40:18.869843 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 12:40:18.876249 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 12:40:18.888392 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 12:40:18.894910 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 12:40:18.914443 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 12:40:18.917107 WDT: Last reset was cold boot
367 12:40:18.920986 SPI1(PAD0) initialized at 2873684 Hz
368 12:40:18.924206 SPI5(PAD0) initialized at 992727 Hz
369 12:40:18.927782 VBOOT: Loading verstage.
370 12:40:18.934037 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 12:40:18.937343 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 12:40:18.940404 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 12:40:18.943896 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 12:40:18.951643 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 12:40:18.958015 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 12:40:18.969059 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
377 12:40:18.969167
378 12:40:18.969236
379 12:40:18.979095 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 12:40:18.982924 ARM64: Exception handlers installed.
381 12:40:18.986087 ARM64: Testing exception
382 12:40:18.986174 ARM64: Done test exception
383 12:40:18.992983 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 12:40:18.996606 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 12:40:19.009740 Probing TPM: . done!
386 12:40:19.009838 TPM ready after 0 ms
387 12:40:19.017146 Connected to device vid:did:rid of 1ae0:0028:00
388 12:40:19.023863 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
389 12:40:19.082357 Initialized TPM device CR50 revision 0
390 12:40:19.094154 tlcl_send_startup: Startup return code is 0
391 12:40:19.094295 TPM: setup succeeded
392 12:40:19.105909 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 12:40:19.114728 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 12:40:19.127047 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 12:40:19.136407 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 12:40:19.139802 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 12:40:19.144547 in-header: 03 07 00 00 08 00 00 00
398 12:40:19.147891 in-data: aa e4 47 04 13 02 00 00
399 12:40:19.151696 Chrome EC: UHEPI supported
400 12:40:19.159327 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 12:40:19.162827 in-header: 03 95 00 00 08 00 00 00
402 12:40:19.162932 in-data: 18 20 20 08 00 00 00 00
403 12:40:19.166878 Phase 1
404 12:40:19.170205 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 12:40:19.174371 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 12:40:19.181224 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 12:40:19.185247 Recovery requested (1009000e)
408 12:40:19.192482 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 12:40:19.197835 tlcl_extend: response is 0
410 12:40:19.207503 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 12:40:19.212741 tlcl_extend: response is 0
412 12:40:19.219958 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 12:40:19.239611 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
414 12:40:19.246357 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 12:40:19.246446
416 12:40:19.246514
417 12:40:19.256116 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 12:40:19.259579 ARM64: Exception handlers installed.
419 12:40:19.263897 ARM64: Testing exception
420 12:40:19.263981 ARM64: Done test exception
421 12:40:19.284943 pmic_efuse_setting: Set efuses in 11 msecs
422 12:40:19.288692 pmwrap_interface_init: Select PMIF_VLD_RDY
423 12:40:19.294915 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 12:40:19.298282 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 12:40:19.305510 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 12:40:19.309277 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 12:40:19.312607 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 12:40:19.319630 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 12:40:19.323511 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 12:40:19.327514 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 12:40:19.331188 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 12:40:19.338336 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 12:40:19.342004 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 12:40:19.346581 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 12:40:19.349505 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 12:40:19.357195 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 12:40:19.364275 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 12:40:19.367928 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 12:40:19.375825 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 12:40:19.379471 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 12:40:19.386618 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 12:40:19.390262 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 12:40:19.397484 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 12:40:19.401285 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 12:40:19.408797 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 12:40:19.412338 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 12:40:19.419495 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 12:40:19.426921 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 12:40:19.430112 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 12:40:19.434171 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 12:40:19.440837 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 12:40:19.445251 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 12:40:19.448317 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 12:40:19.455340 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 12:40:19.458818 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 12:40:19.462617 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 12:40:19.469943 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 12:40:19.474459 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 12:40:19.478115 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 12:40:19.485407 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 12:40:19.488653 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 12:40:19.492363 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 12:40:19.495856 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 12:40:19.503442 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 12:40:19.507302 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 12:40:19.510809 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 12:40:19.514408 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 12:40:19.517985 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 12:40:19.522181 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 12:40:19.530064 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 12:40:19.533176 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 12:40:19.535989 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 12:40:19.540055 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 12:40:19.548421 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 12:40:19.555347 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 12:40:19.562473 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 12:40:19.569722 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 12:40:19.577138 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 12:40:19.581141 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 12:40:19.588317 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 12:40:19.591797 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 12:40:19.598673 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x0
483 12:40:19.602761 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 12:40:19.610308 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
485 12:40:19.614069 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 12:40:19.623109 [RTC]rtc_get_frequency_meter,154: input=15, output=852
487 12:40:19.632439 [RTC]rtc_get_frequency_meter,154: input=7, output=723
488 12:40:19.641277 [RTC]rtc_get_frequency_meter,154: input=11, output=789
489 12:40:19.651790 [RTC]rtc_get_frequency_meter,154: input=13, output=821
490 12:40:19.661373 [RTC]rtc_get_frequency_meter,154: input=12, output=805
491 12:40:19.670028 [RTC]rtc_get_frequency_meter,154: input=11, output=789
492 12:40:19.679537 [RTC]rtc_get_frequency_meter,154: input=12, output=805
493 12:40:19.683376 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
494 12:40:19.690346 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
495 12:40:19.693692 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
496 12:40:19.698274 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
497 12:40:19.701346 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
498 12:40:19.704655 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
499 12:40:19.708780 ADC[4]: Raw value=904802 ID=7
500 12:40:19.712306 ADC[3]: Raw value=213546 ID=1
501 12:40:19.712390 RAM Code: 0x71
502 12:40:19.716468 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
503 12:40:19.723527 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
504 12:40:19.730613 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
505 12:40:19.737804 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
506 12:40:19.741064 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
507 12:40:19.745625 in-header: 03 07 00 00 08 00 00 00
508 12:40:19.748669 in-data: aa e4 47 04 13 02 00 00
509 12:40:19.748752 Chrome EC: UHEPI supported
510 12:40:19.756125 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
511 12:40:19.760019 in-header: 03 95 00 00 08 00 00 00
512 12:40:19.763481 in-data: 18 20 20 08 00 00 00 00
513 12:40:19.767619 MRC: failed to locate region type 0.
514 12:40:19.774730 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
515 12:40:19.774815 DRAM-K: Running full calibration
516 12:40:19.781868 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
517 12:40:19.785806 header.status = 0x0
518 12:40:19.789252 header.version = 0x6 (expected: 0x6)
519 12:40:19.789335 header.size = 0xd00 (expected: 0xd00)
520 12:40:19.793034 header.flags = 0x0
521 12:40:19.799950 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
522 12:40:19.817109 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
523 12:40:19.825352 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
524 12:40:19.825438 dram_init: ddr_geometry: 2
525 12:40:19.828430 [EMI] MDL number = 2
526 12:40:19.831837 [EMI] Get MDL freq = 0
527 12:40:19.831920 dram_init: ddr_type: 0
528 12:40:19.835489 is_discrete_lpddr4: 1
529 12:40:19.839036 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
530 12:40:19.839119
531 12:40:19.839185
532 12:40:19.839245 [Bian_co] ETT version 0.0.0.1
533 12:40:19.845905 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
534 12:40:19.845990
535 12:40:19.849458 dramc_set_vcore_voltage set vcore to 650000
536 12:40:19.853084 Read voltage for 800, 4
537 12:40:19.853166 Vio18 = 0
538 12:40:19.853232 Vcore = 650000
539 12:40:19.856735 Vdram = 0
540 12:40:19.856817 Vddq = 0
541 12:40:19.856883 Vmddr = 0
542 12:40:19.860046 dram_init: config_dvfs: 1
543 12:40:19.863856 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
544 12:40:19.871144 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
545 12:40:19.874770 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
546 12:40:19.878290 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
547 12:40:19.881783 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
548 12:40:19.884555 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
549 12:40:19.884637 MEM_TYPE=3, freq_sel=18
550 12:40:19.888138 sv_algorithm_assistance_LP4_1600
551 12:40:19.894816 ============ PULL DRAM RESETB DOWN ============
552 12:40:19.897939 ========== PULL DRAM RESETB DOWN end =========
553 12:40:19.901808 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
554 12:40:19.904399 ===================================
555 12:40:19.907841 LPDDR4 DRAM CONFIGURATION
556 12:40:19.911953 ===================================
557 12:40:19.914520 EX_ROW_EN[0] = 0x0
558 12:40:19.914603 EX_ROW_EN[1] = 0x0
559 12:40:19.917872 LP4Y_EN = 0x0
560 12:40:19.917954 WORK_FSP = 0x0
561 12:40:19.921419 WL = 0x2
562 12:40:19.921502 RL = 0x2
563 12:40:19.924323 BL = 0x2
564 12:40:19.924407 RPST = 0x0
565 12:40:19.928603 RD_PRE = 0x0
566 12:40:19.928686 WR_PRE = 0x1
567 12:40:19.931161 WR_PST = 0x0
568 12:40:19.931243 DBI_WR = 0x0
569 12:40:19.934358 DBI_RD = 0x0
570 12:40:19.934440 OTF = 0x1
571 12:40:19.937668 ===================================
572 12:40:19.941243 ===================================
573 12:40:19.944370 ANA top config
574 12:40:19.947586 ===================================
575 12:40:19.951338 DLL_ASYNC_EN = 0
576 12:40:19.951420 ALL_SLAVE_EN = 1
577 12:40:19.954257 NEW_RANK_MODE = 1
578 12:40:19.957602 DLL_IDLE_MODE = 1
579 12:40:19.960800 LP45_APHY_COMB_EN = 1
580 12:40:19.964296 TX_ODT_DIS = 1
581 12:40:19.964378 NEW_8X_MODE = 1
582 12:40:19.967554 ===================================
583 12:40:19.970865 ===================================
584 12:40:19.974745 data_rate = 1600
585 12:40:19.977961 CKR = 1
586 12:40:19.981084 DQ_P2S_RATIO = 8
587 12:40:19.984010 ===================================
588 12:40:19.987765 CA_P2S_RATIO = 8
589 12:40:19.987851 DQ_CA_OPEN = 0
590 12:40:19.991388 DQ_SEMI_OPEN = 0
591 12:40:19.994415 CA_SEMI_OPEN = 0
592 12:40:19.997917 CA_FULL_RATE = 0
593 12:40:20.001413 DQ_CKDIV4_EN = 1
594 12:40:20.004927 CA_CKDIV4_EN = 1
595 12:40:20.005014 CA_PREDIV_EN = 0
596 12:40:20.007974 PH8_DLY = 0
597 12:40:20.011007 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
598 12:40:20.014180 DQ_AAMCK_DIV = 4
599 12:40:20.017565 CA_AAMCK_DIV = 4
600 12:40:20.020994 CA_ADMCK_DIV = 4
601 12:40:20.021081 DQ_TRACK_CA_EN = 0
602 12:40:20.024578 CA_PICK = 800
603 12:40:20.027381 CA_MCKIO = 800
604 12:40:20.031419 MCKIO_SEMI = 0
605 12:40:20.034861 PLL_FREQ = 3068
606 12:40:20.038347 DQ_UI_PI_RATIO = 32
607 12:40:20.038458 CA_UI_PI_RATIO = 0
608 12:40:20.042140 ===================================
609 12:40:20.046217 ===================================
610 12:40:20.050139 memory_type:LPDDR4
611 12:40:20.050223 GP_NUM : 10
612 12:40:20.053000 SRAM_EN : 1
613 12:40:20.053084 MD32_EN : 0
614 12:40:20.056679 ===================================
615 12:40:20.060282 [ANA_INIT] >>>>>>>>>>>>>>
616 12:40:20.064227 <<<<<< [CONFIGURE PHASE]: ANA_TX
617 12:40:20.068326 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
618 12:40:20.071176 ===================================
619 12:40:20.071274 data_rate = 1600,PCW = 0X7600
620 12:40:20.074426 ===================================
621 12:40:20.077941 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
622 12:40:20.084296 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
623 12:40:20.091065 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
624 12:40:20.094600 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
625 12:40:20.097963 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
626 12:40:20.101065 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
627 12:40:20.104262 [ANA_INIT] flow start
628 12:40:20.107528 [ANA_INIT] PLL >>>>>>>>
629 12:40:20.107612 [ANA_INIT] PLL <<<<<<<<
630 12:40:20.111033 [ANA_INIT] MIDPI >>>>>>>>
631 12:40:20.114695 [ANA_INIT] MIDPI <<<<<<<<
632 12:40:20.114780 [ANA_INIT] DLL >>>>>>>>
633 12:40:20.117488 [ANA_INIT] flow end
634 12:40:20.120785 ============ LP4 DIFF to SE enter ============
635 12:40:20.123930 ============ LP4 DIFF to SE exit ============
636 12:40:20.127833 [ANA_INIT] <<<<<<<<<<<<<
637 12:40:20.131133 [Flow] Enable top DCM control >>>>>
638 12:40:20.134296 [Flow] Enable top DCM control <<<<<
639 12:40:20.137521 Enable DLL master slave shuffle
640 12:40:20.144133 ==============================================================
641 12:40:20.144218 Gating Mode config
642 12:40:20.150917 ==============================================================
643 12:40:20.151000 Config description:
644 12:40:20.160530 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
645 12:40:20.167669 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
646 12:40:20.174387 SELPH_MODE 0: By rank 1: By Phase
647 12:40:20.177685 ==============================================================
648 12:40:20.180844 GAT_TRACK_EN = 1
649 12:40:20.184612 RX_GATING_MODE = 2
650 12:40:20.187173 RX_GATING_TRACK_MODE = 2
651 12:40:20.190527 SELPH_MODE = 1
652 12:40:20.194218 PICG_EARLY_EN = 1
653 12:40:20.197090 VALID_LAT_VALUE = 1
654 12:40:20.203635 ==============================================================
655 12:40:20.206981 Enter into Gating configuration >>>>
656 12:40:20.210622 Exit from Gating configuration <<<<
657 12:40:20.210706 Enter into DVFS_PRE_config >>>>>
658 12:40:20.224573 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
659 12:40:20.227044 Exit from DVFS_PRE_config <<<<<
660 12:40:20.230426 Enter into PICG configuration >>>>
661 12:40:20.233822 Exit from PICG configuration <<<<
662 12:40:20.233905 [RX_INPUT] configuration >>>>>
663 12:40:20.236879 [RX_INPUT] configuration <<<<<
664 12:40:20.243401 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
665 12:40:20.246777 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
666 12:40:20.253747 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
667 12:40:20.260209 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
668 12:40:20.267199 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
669 12:40:20.273709 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
670 12:40:20.277249 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
671 12:40:20.280306 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
672 12:40:20.286984 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
673 12:40:20.290184 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
674 12:40:20.293680 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
675 12:40:20.296827 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
676 12:40:20.301068 ===================================
677 12:40:20.303626 LPDDR4 DRAM CONFIGURATION
678 12:40:20.307352 ===================================
679 12:40:20.310395 EX_ROW_EN[0] = 0x0
680 12:40:20.310479 EX_ROW_EN[1] = 0x0
681 12:40:20.313594 LP4Y_EN = 0x0
682 12:40:20.313678 WORK_FSP = 0x0
683 12:40:20.316549 WL = 0x2
684 12:40:20.316632 RL = 0x2
685 12:40:20.320478 BL = 0x2
686 12:40:20.320561 RPST = 0x0
687 12:40:20.323238 RD_PRE = 0x0
688 12:40:20.323321 WR_PRE = 0x1
689 12:40:20.326904 WR_PST = 0x0
690 12:40:20.330309 DBI_WR = 0x0
691 12:40:20.330393 DBI_RD = 0x0
692 12:40:20.333079 OTF = 0x1
693 12:40:20.336627 ===================================
694 12:40:20.340206 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
695 12:40:20.344318 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
696 12:40:20.346858 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 12:40:20.349661 ===================================
698 12:40:20.353605 LPDDR4 DRAM CONFIGURATION
699 12:40:20.356319 ===================================
700 12:40:20.359945 EX_ROW_EN[0] = 0x10
701 12:40:20.360087 EX_ROW_EN[1] = 0x0
702 12:40:20.363252 LP4Y_EN = 0x0
703 12:40:20.363335 WORK_FSP = 0x0
704 12:40:20.366500 WL = 0x2
705 12:40:20.366583 RL = 0x2
706 12:40:20.369763 BL = 0x2
707 12:40:20.369847 RPST = 0x0
708 12:40:20.372944 RD_PRE = 0x0
709 12:40:20.373027 WR_PRE = 0x1
710 12:40:20.376269 WR_PST = 0x0
711 12:40:20.376351 DBI_WR = 0x0
712 12:40:20.379804 DBI_RD = 0x0
713 12:40:20.382956 OTF = 0x1
714 12:40:20.383039 ===================================
715 12:40:20.389561 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
716 12:40:20.394580 nWR fixed to 40
717 12:40:20.398342 [ModeRegInit_LP4] CH0 RK0
718 12:40:20.398425 [ModeRegInit_LP4] CH0 RK1
719 12:40:20.401507 [ModeRegInit_LP4] CH1 RK0
720 12:40:20.404712 [ModeRegInit_LP4] CH1 RK1
721 12:40:20.404795 match AC timing 13
722 12:40:20.410967 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
723 12:40:20.414303 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
724 12:40:20.417734 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
725 12:40:20.424228 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
726 12:40:20.427528 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
727 12:40:20.431603 [EMI DOE] emi_dcm 0
728 12:40:20.434543 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
729 12:40:20.434627 ==
730 12:40:20.438177 Dram Type= 6, Freq= 0, CH_0, rank 0
731 12:40:20.441095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
732 12:40:20.441180 ==
733 12:40:20.447931 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
734 12:40:20.454154 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
735 12:40:20.462214 [CA 0] Center 38 (7~69) winsize 63
736 12:40:20.465397 [CA 1] Center 37 (6~68) winsize 63
737 12:40:20.468889 [CA 2] Center 34 (4~65) winsize 62
738 12:40:20.472271 [CA 3] Center 34 (4~65) winsize 62
739 12:40:20.475283 [CA 4] Center 33 (3~64) winsize 62
740 12:40:20.478997 [CA 5] Center 33 (3~64) winsize 62
741 12:40:20.479080
742 12:40:20.482318 [CmdBusTrainingLP45] Vref(ca) range 1: 34
743 12:40:20.482401
744 12:40:20.485712 [CATrainingPosCal] consider 1 rank data
745 12:40:20.488801 u2DelayCellTimex100 = 270/100 ps
746 12:40:20.492220 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
747 12:40:20.498347 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
748 12:40:20.501986 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
749 12:40:20.505421 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
750 12:40:20.508583 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
751 12:40:20.512154 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
752 12:40:20.512236
753 12:40:20.515031 CA PerBit enable=1, Macro0, CA PI delay=33
754 12:40:20.515113
755 12:40:20.518752 [CBTSetCACLKResult] CA Dly = 33
756 12:40:20.518835 CS Dly: 5 (0~36)
757 12:40:20.521946 ==
758 12:40:20.525237 Dram Type= 6, Freq= 0, CH_0, rank 1
759 12:40:20.528360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
760 12:40:20.528443 ==
761 12:40:20.532159 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
762 12:40:20.538141 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
763 12:40:20.548182 [CA 0] Center 38 (7~69) winsize 63
764 12:40:20.551985 [CA 1] Center 37 (7~68) winsize 62
765 12:40:20.554804 [CA 2] Center 35 (4~66) winsize 63
766 12:40:20.558081 [CA 3] Center 35 (4~66) winsize 63
767 12:40:20.561658 [CA 4] Center 34 (3~65) winsize 63
768 12:40:20.565229 [CA 5] Center 33 (3~64) winsize 62
769 12:40:20.565312
770 12:40:20.568065 [CmdBusTrainingLP45] Vref(ca) range 1: 34
771 12:40:20.568161
772 12:40:20.571344 [CATrainingPosCal] consider 2 rank data
773 12:40:20.574696 u2DelayCellTimex100 = 270/100 ps
774 12:40:20.578290 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
775 12:40:20.582194 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
776 12:40:20.588639 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
777 12:40:20.591539 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
778 12:40:20.594768 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
779 12:40:20.598117 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
780 12:40:20.598201
781 12:40:20.601958 CA PerBit enable=1, Macro0, CA PI delay=33
782 12:40:20.602042
783 12:40:20.605015 [CBTSetCACLKResult] CA Dly = 33
784 12:40:20.605099 CS Dly: 6 (0~38)
785 12:40:20.605166
786 12:40:20.608001 ----->DramcWriteLeveling(PI) begin...
787 12:40:20.611835 ==
788 12:40:20.611918 Dram Type= 6, Freq= 0, CH_0, rank 0
789 12:40:20.619060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
790 12:40:20.619177 ==
791 12:40:20.622408 Write leveling (Byte 0): 28 => 28
792 12:40:20.622492 Write leveling (Byte 1): 27 => 27
793 12:40:20.625871 DramcWriteLeveling(PI) end<-----
794 12:40:20.625955
795 12:40:20.626022 ==
796 12:40:20.629822 Dram Type= 6, Freq= 0, CH_0, rank 0
797 12:40:20.633303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
798 12:40:20.636410 ==
799 12:40:20.636494 [Gating] SW mode calibration
800 12:40:20.643502 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
801 12:40:20.649796 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
802 12:40:20.653036 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
803 12:40:20.659823 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
804 12:40:20.663172 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
805 12:40:20.666581 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 12:40:20.673072 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 12:40:20.676729 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:40:20.679870 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 12:40:20.687035 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 12:40:20.689633 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 12:40:20.693145 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 12:40:20.699522 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 12:40:20.702671 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 12:40:20.706738 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 12:40:20.712764 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 12:40:20.716158 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 12:40:20.719554 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 12:40:20.723077 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
819 12:40:20.730111 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
820 12:40:20.733173 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
821 12:40:20.735924 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 12:40:20.743012 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 12:40:20.746736 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 12:40:20.749312 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 12:40:20.756358 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 12:40:20.759509 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 12:40:20.762684 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 12:40:20.769827 0 9 8 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
829 12:40:20.772721 0 9 12 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
830 12:40:20.775989 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
831 12:40:20.782745 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
832 12:40:20.786113 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
833 12:40:20.789404 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
834 12:40:20.795672 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
835 12:40:20.799706 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
836 12:40:20.802962 0 10 8 | B1->B0 | 3333 2727 | 0 0 | (0 1) (0 0)
837 12:40:20.809253 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
838 12:40:20.812484 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 12:40:20.815812 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 12:40:20.822570 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 12:40:20.826028 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 12:40:20.829297 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 12:40:20.835766 0 11 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
844 12:40:20.839075 0 11 8 | B1->B0 | 2b2b 4444 | 0 0 | (0 0) (0 0)
845 12:40:20.842500 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
846 12:40:20.848909 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 12:40:20.852301 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
848 12:40:20.855308 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
849 12:40:20.862112 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 12:40:20.865721 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
851 12:40:20.868942 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
852 12:40:20.875956 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
853 12:40:20.878518 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 12:40:20.882699 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 12:40:20.885517 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 12:40:20.892079 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 12:40:20.895773 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 12:40:20.899019 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 12:40:20.905350 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 12:40:20.908719 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 12:40:20.911815 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 12:40:20.918663 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 12:40:20.921844 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 12:40:20.925254 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
865 12:40:20.931599 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
866 12:40:20.935011 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
867 12:40:20.938342 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
868 12:40:20.945272 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
869 12:40:20.948372 Total UI for P1: 0, mck2ui 16
870 12:40:20.951499 best dqsien dly found for B0: ( 0, 14, 4)
871 12:40:20.954812 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
872 12:40:20.958463 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
873 12:40:20.962109 Total UI for P1: 0, mck2ui 16
874 12:40:20.964971 best dqsien dly found for B1: ( 0, 14, 10)
875 12:40:20.968704 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
876 12:40:20.971542 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
877 12:40:20.971626
878 12:40:20.979034 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
879 12:40:20.981892 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
880 12:40:20.984950 [Gating] SW calibration Done
881 12:40:20.985034 ==
882 12:40:20.988544 Dram Type= 6, Freq= 0, CH_0, rank 0
883 12:40:20.992363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
884 12:40:20.992448 ==
885 12:40:20.992515 RX Vref Scan: 0
886 12:40:20.992576
887 12:40:20.995211 RX Vref 0 -> 0, step: 1
888 12:40:20.995334
889 12:40:20.998903 RX Delay -130 -> 252, step: 16
890 12:40:21.002238 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
891 12:40:21.005582 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
892 12:40:21.008849 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
893 12:40:21.015236 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
894 12:40:21.018661 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
895 12:40:21.022293 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
896 12:40:21.025568 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
897 12:40:21.028461 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
898 12:40:21.035270 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
899 12:40:21.038714 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
900 12:40:21.042090 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
901 12:40:21.045421 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
902 12:40:21.049012 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
903 12:40:21.055289 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
904 12:40:21.058910 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
905 12:40:21.062192 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
906 12:40:21.062276 ==
907 12:40:21.065518 Dram Type= 6, Freq= 0, CH_0, rank 0
908 12:40:21.068826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
909 12:40:21.068910 ==
910 12:40:21.072180 DQS Delay:
911 12:40:21.072263 DQS0 = 0, DQS1 = 0
912 12:40:21.075201 DQM Delay:
913 12:40:21.075285 DQM0 = 87, DQM1 = 75
914 12:40:21.075352 DQ Delay:
915 12:40:21.078997 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
916 12:40:21.081833 DQ4 =93, DQ5 =69, DQ6 =101, DQ7 =93
917 12:40:21.085280 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
918 12:40:21.088713 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
919 12:40:21.088797
920 12:40:21.088899
921 12:40:21.092508 ==
922 12:40:21.095302 Dram Type= 6, Freq= 0, CH_0, rank 0
923 12:40:21.098091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
924 12:40:21.098176 ==
925 12:40:21.098242
926 12:40:21.098303
927 12:40:21.101706 TX Vref Scan disable
928 12:40:21.101790 == TX Byte 0 ==
929 12:40:21.108228 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
930 12:40:21.111901 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
931 12:40:21.112011 == TX Byte 1 ==
932 12:40:21.118036 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
933 12:40:21.121755 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
934 12:40:21.121839 ==
935 12:40:21.124950 Dram Type= 6, Freq= 0, CH_0, rank 0
936 12:40:21.127907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
937 12:40:21.128018 ==
938 12:40:21.141621 TX Vref=22, minBit 1, minWin=27, winSum=440
939 12:40:21.145188 TX Vref=24, minBit 1, minWin=26, winSum=440
940 12:40:21.148394 TX Vref=26, minBit 4, minWin=27, winSum=445
941 12:40:21.151640 TX Vref=28, minBit 0, minWin=28, winSum=451
942 12:40:21.155873 TX Vref=30, minBit 1, minWin=28, winSum=452
943 12:40:21.158366 TX Vref=32, minBit 6, minWin=27, winSum=452
944 12:40:21.164641 [TxChooseVref] Worse bit 1, Min win 28, Win sum 452, Final Vref 30
945 12:40:21.164725
946 12:40:21.168449 Final TX Range 1 Vref 30
947 12:40:21.168532
948 12:40:21.168598 ==
949 12:40:21.171392 Dram Type= 6, Freq= 0, CH_0, rank 0
950 12:40:21.175531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
951 12:40:21.175615 ==
952 12:40:21.175681
953 12:40:21.178102
954 12:40:21.178185 TX Vref Scan disable
955 12:40:21.181309 == TX Byte 0 ==
956 12:40:21.185254 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
957 12:40:21.191180 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
958 12:40:21.191264 == TX Byte 1 ==
959 12:40:21.194811 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
960 12:40:21.201510 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
961 12:40:21.201594
962 12:40:21.201660 [DATLAT]
963 12:40:21.201719 Freq=800, CH0 RK0
964 12:40:21.201778
965 12:40:21.204662 DATLAT Default: 0xa
966 12:40:21.204746 0, 0xFFFF, sum = 0
967 12:40:21.208203 1, 0xFFFF, sum = 0
968 12:40:21.208288 2, 0xFFFF, sum = 0
969 12:40:21.211590 3, 0xFFFF, sum = 0
970 12:40:21.214636 4, 0xFFFF, sum = 0
971 12:40:21.214721 5, 0xFFFF, sum = 0
972 12:40:21.218285 6, 0xFFFF, sum = 0
973 12:40:21.218369 7, 0xFFFF, sum = 0
974 12:40:21.221519 8, 0xFFFF, sum = 0
975 12:40:21.221604 9, 0x0, sum = 1
976 12:40:21.221672 10, 0x0, sum = 2
977 12:40:21.224647 11, 0x0, sum = 3
978 12:40:21.224731 12, 0x0, sum = 4
979 12:40:21.228246 best_step = 10
980 12:40:21.228330
981 12:40:21.228396 ==
982 12:40:21.231230 Dram Type= 6, Freq= 0, CH_0, rank 0
983 12:40:21.235029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
984 12:40:21.235113 ==
985 12:40:21.237895 RX Vref Scan: 1
986 12:40:21.237978
987 12:40:21.241049 Set Vref Range= 32 -> 127
988 12:40:21.241162
989 12:40:21.241232 RX Vref 32 -> 127, step: 1
990 12:40:21.241294
991 12:40:21.244607 RX Delay -111 -> 252, step: 8
992 12:40:21.244691
993 12:40:21.247763 Set Vref, RX VrefLevel [Byte0]: 32
994 12:40:21.250949 [Byte1]: 32
995 12:40:21.254781
996 12:40:21.254864 Set Vref, RX VrefLevel [Byte0]: 33
997 12:40:21.258367 [Byte1]: 33
998 12:40:21.262191
999 12:40:21.262274 Set Vref, RX VrefLevel [Byte0]: 34
1000 12:40:21.265444 [Byte1]: 34
1001 12:40:21.269470
1002 12:40:21.269554 Set Vref, RX VrefLevel [Byte0]: 35
1003 12:40:21.272748 [Byte1]: 35
1004 12:40:21.277436
1005 12:40:21.277519 Set Vref, RX VrefLevel [Byte0]: 36
1006 12:40:21.280610 [Byte1]: 36
1007 12:40:21.285677
1008 12:40:21.285759 Set Vref, RX VrefLevel [Byte0]: 37
1009 12:40:21.288388 [Byte1]: 37
1010 12:40:21.293046
1011 12:40:21.293130 Set Vref, RX VrefLevel [Byte0]: 38
1012 12:40:21.296226 [Byte1]: 38
1013 12:40:21.300546
1014 12:40:21.300629 Set Vref, RX VrefLevel [Byte0]: 39
1015 12:40:21.304733 [Byte1]: 39
1016 12:40:21.307933
1017 12:40:21.308066 Set Vref, RX VrefLevel [Byte0]: 40
1018 12:40:21.311682 [Byte1]: 40
1019 12:40:21.316572
1020 12:40:21.316655 Set Vref, RX VrefLevel [Byte0]: 41
1021 12:40:21.318966 [Byte1]: 41
1022 12:40:21.323024
1023 12:40:21.323107 Set Vref, RX VrefLevel [Byte0]: 42
1024 12:40:21.326110 [Byte1]: 42
1025 12:40:21.330888
1026 12:40:21.330973 Set Vref, RX VrefLevel [Byte0]: 43
1027 12:40:21.334259 [Byte1]: 43
1028 12:40:21.338066
1029 12:40:21.338149 Set Vref, RX VrefLevel [Byte0]: 44
1030 12:40:21.342213 [Byte1]: 44
1031 12:40:21.346049
1032 12:40:21.346132 Set Vref, RX VrefLevel [Byte0]: 45
1033 12:40:21.349434 [Byte1]: 45
1034 12:40:21.353695
1035 12:40:21.353779 Set Vref, RX VrefLevel [Byte0]: 46
1036 12:40:21.356926 [Byte1]: 46
1037 12:40:21.361117
1038 12:40:21.361204 Set Vref, RX VrefLevel [Byte0]: 47
1039 12:40:21.364351 [Byte1]: 47
1040 12:40:21.368833
1041 12:40:21.368916 Set Vref, RX VrefLevel [Byte0]: 48
1042 12:40:21.371952 [Byte1]: 48
1043 12:40:21.376510
1044 12:40:21.376593 Set Vref, RX VrefLevel [Byte0]: 49
1045 12:40:21.380339 [Byte1]: 49
1046 12:40:21.384731
1047 12:40:21.384814 Set Vref, RX VrefLevel [Byte0]: 50
1048 12:40:21.387842 [Byte1]: 50
1049 12:40:21.392001
1050 12:40:21.392105 Set Vref, RX VrefLevel [Byte0]: 51
1051 12:40:21.395085 [Byte1]: 51
1052 12:40:21.399825
1053 12:40:21.399907 Set Vref, RX VrefLevel [Byte0]: 52
1054 12:40:21.402795 [Byte1]: 52
1055 12:40:21.407106
1056 12:40:21.407188 Set Vref, RX VrefLevel [Byte0]: 53
1057 12:40:21.410474 [Byte1]: 53
1058 12:40:21.415246
1059 12:40:21.415328 Set Vref, RX VrefLevel [Byte0]: 54
1060 12:40:21.418110 [Byte1]: 54
1061 12:40:21.422625
1062 12:40:21.422706 Set Vref, RX VrefLevel [Byte0]: 55
1063 12:40:21.425840 [Byte1]: 55
1064 12:40:21.430304
1065 12:40:21.430386 Set Vref, RX VrefLevel [Byte0]: 56
1066 12:40:21.433136 [Byte1]: 56
1067 12:40:21.437800
1068 12:40:21.437908 Set Vref, RX VrefLevel [Byte0]: 57
1069 12:40:21.441500 [Byte1]: 57
1070 12:40:21.445674
1071 12:40:21.445755 Set Vref, RX VrefLevel [Byte0]: 58
1072 12:40:21.448800 [Byte1]: 58
1073 12:40:21.453670
1074 12:40:21.453751 Set Vref, RX VrefLevel [Byte0]: 59
1075 12:40:21.456783 [Byte1]: 59
1076 12:40:21.461319
1077 12:40:21.461400 Set Vref, RX VrefLevel [Byte0]: 60
1078 12:40:21.464289 [Byte1]: 60
1079 12:40:21.468409
1080 12:40:21.468494 Set Vref, RX VrefLevel [Byte0]: 61
1081 12:40:21.471730 [Byte1]: 61
1082 12:40:21.475781
1083 12:40:21.475866 Set Vref, RX VrefLevel [Byte0]: 62
1084 12:40:21.479188 [Byte1]: 62
1085 12:40:21.483522
1086 12:40:21.483607 Set Vref, RX VrefLevel [Byte0]: 63
1087 12:40:21.486656 [Byte1]: 63
1088 12:40:21.491332
1089 12:40:21.491417 Set Vref, RX VrefLevel [Byte0]: 64
1090 12:40:21.494379 [Byte1]: 64
1091 12:40:21.499190
1092 12:40:21.499275 Set Vref, RX VrefLevel [Byte0]: 65
1093 12:40:21.502131 [Byte1]: 65
1094 12:40:21.507184
1095 12:40:21.507269 Set Vref, RX VrefLevel [Byte0]: 66
1096 12:40:21.509772 [Byte1]: 66
1097 12:40:21.514087
1098 12:40:21.514172 Set Vref, RX VrefLevel [Byte0]: 67
1099 12:40:21.517332 [Byte1]: 67
1100 12:40:21.521671
1101 12:40:21.521760 Set Vref, RX VrefLevel [Byte0]: 68
1102 12:40:21.524927 [Byte1]: 68
1103 12:40:21.529380
1104 12:40:21.529465 Set Vref, RX VrefLevel [Byte0]: 69
1105 12:40:21.533082 [Byte1]: 69
1106 12:40:21.537258
1107 12:40:21.537343 Set Vref, RX VrefLevel [Byte0]: 70
1108 12:40:21.540626 [Byte1]: 70
1109 12:40:21.545019
1110 12:40:21.545104 Set Vref, RX VrefLevel [Byte0]: 71
1111 12:40:21.547961 [Byte1]: 71
1112 12:40:21.552186
1113 12:40:21.555231 Set Vref, RX VrefLevel [Byte0]: 72
1114 12:40:21.558737 [Byte1]: 72
1115 12:40:21.558821
1116 12:40:21.562281 Set Vref, RX VrefLevel [Byte0]: 73
1117 12:40:21.565219 [Byte1]: 73
1118 12:40:21.565304
1119 12:40:21.568598 Final RX Vref Byte 0 = 58 to rank0
1120 12:40:21.572391 Final RX Vref Byte 1 = 57 to rank0
1121 12:40:21.574929 Final RX Vref Byte 0 = 58 to rank1
1122 12:40:21.578877 Final RX Vref Byte 1 = 57 to rank1==
1123 12:40:21.581788 Dram Type= 6, Freq= 0, CH_0, rank 0
1124 12:40:21.584911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1125 12:40:21.584997 ==
1126 12:40:21.588560 DQS Delay:
1127 12:40:21.588646 DQS0 = 0, DQS1 = 0
1128 12:40:21.591450 DQM Delay:
1129 12:40:21.591535 DQM0 = 87, DQM1 = 75
1130 12:40:21.591619 DQ Delay:
1131 12:40:21.594857 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1132 12:40:21.598188 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1133 12:40:21.601634 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =68
1134 12:40:21.605166 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1135 12:40:21.605251
1136 12:40:21.605336
1137 12:40:21.615499 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f28, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
1138 12:40:21.618203 CH0 RK0: MR19=606, MR18=2F28
1139 12:40:21.621579 CH0_RK0: MR19=0x606, MR18=0x2F28, DQSOSC=397, MR23=63, INC=93, DEC=62
1140 12:40:21.624815
1141 12:40:21.629011 ----->DramcWriteLeveling(PI) begin...
1142 12:40:21.629097 ==
1143 12:40:21.631642 Dram Type= 6, Freq= 0, CH_0, rank 1
1144 12:40:21.634491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1145 12:40:21.634576 ==
1146 12:40:21.638504 Write leveling (Byte 0): 31 => 31
1147 12:40:21.641459 Write leveling (Byte 1): 27 => 27
1148 12:40:21.644384 DramcWriteLeveling(PI) end<-----
1149 12:40:21.644505
1150 12:40:21.644590 ==
1151 12:40:21.647741 Dram Type= 6, Freq= 0, CH_0, rank 1
1152 12:40:21.651307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1153 12:40:21.651393 ==
1154 12:40:21.654112 [Gating] SW mode calibration
1155 12:40:21.660904 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1156 12:40:21.667962 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1157 12:40:21.671035 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1158 12:40:21.674176 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1159 12:40:21.721545 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1160 12:40:21.721630 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 12:40:21.721883 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 12:40:21.722132 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 12:40:21.722421 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 12:40:21.722676 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 12:40:21.722749 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 12:40:21.723283 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 12:40:21.723553 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 12:40:21.724022 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 12:40:21.765595 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 12:40:21.765693 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 12:40:21.766531 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 12:40:21.766809 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 12:40:21.767890 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 12:40:21.768155 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1175 12:40:21.768232 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1176 12:40:21.768700 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 12:40:21.769136 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 12:40:21.770036 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 12:40:21.784444 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 12:40:21.784530 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 12:40:21.784800 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 12:40:21.785056 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 12:40:21.788521 0 9 8 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
1184 12:40:21.791699 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1185 12:40:21.794935 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 12:40:21.798303 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 12:40:21.801579 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 12:40:21.807837 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 12:40:21.811344 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1190 12:40:21.814652 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1191 12:40:21.821717 0 10 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)
1192 12:40:21.825009 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 12:40:21.828330 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 12:40:21.834854 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 12:40:21.837771 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 12:40:21.841368 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 12:40:21.847991 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 12:40:21.851321 0 11 4 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
1199 12:40:21.855312 0 11 8 | B1->B0 | 3131 4545 | 0 0 | (0 0) (0 0)
1200 12:40:21.861362 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1201 12:40:21.864997 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 12:40:21.869202 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 12:40:21.872687 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 12:40:21.875853 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 12:40:21.883447 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 12:40:21.886816 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 12:40:21.889774 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1208 12:40:21.896352 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1209 12:40:21.899772 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 12:40:21.903074 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 12:40:21.909673 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 12:40:21.912880 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 12:40:21.916728 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 12:40:21.922810 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 12:40:21.926378 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 12:40:21.929650 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 12:40:21.932801 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 12:40:21.939590 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 12:40:21.942793 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 12:40:21.945957 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 12:40:21.952607 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 12:40:21.956747 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1223 12:40:21.959289 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1224 12:40:21.962569 Total UI for P1: 0, mck2ui 16
1225 12:40:21.966514 best dqsien dly found for B0: ( 0, 14, 4)
1226 12:40:21.972800 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1227 12:40:21.976156 Total UI for P1: 0, mck2ui 16
1228 12:40:21.979526 best dqsien dly found for B1: ( 0, 14, 8)
1229 12:40:21.982913 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1230 12:40:21.985967 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1231 12:40:21.986053
1232 12:40:21.990055 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1233 12:40:21.992547 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1234 12:40:21.995839 [Gating] SW calibration Done
1235 12:40:21.995924 ==
1236 12:40:21.999235 Dram Type= 6, Freq= 0, CH_0, rank 1
1237 12:40:22.002494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1238 12:40:22.002580 ==
1239 12:40:22.006290 RX Vref Scan: 0
1240 12:40:22.006375
1241 12:40:22.006460 RX Vref 0 -> 0, step: 1
1242 12:40:22.009155
1243 12:40:22.009240 RX Delay -130 -> 252, step: 16
1244 12:40:22.016269 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1245 12:40:22.019118 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1246 12:40:22.022345 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1247 12:40:22.025699 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1248 12:40:22.029088 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1249 12:40:22.035504 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1250 12:40:22.039197 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1251 12:40:22.042477 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1252 12:40:22.045475 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1253 12:40:22.048959 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1254 12:40:22.055823 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1255 12:40:22.059077 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1256 12:40:22.062272 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1257 12:40:22.065395 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1258 12:40:22.068519 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1259 12:40:22.075820 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1260 12:40:22.075929 ==
1261 12:40:22.078694 Dram Type= 6, Freq= 0, CH_0, rank 1
1262 12:40:22.081790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1263 12:40:22.081874 ==
1264 12:40:22.081940 DQS Delay:
1265 12:40:22.085504 DQS0 = 0, DQS1 = 0
1266 12:40:22.085587 DQM Delay:
1267 12:40:22.088903 DQM0 = 87, DQM1 = 78
1268 12:40:22.088987 DQ Delay:
1269 12:40:22.091995 DQ0 =85, DQ1 =93, DQ2 =77, DQ3 =85
1270 12:40:22.095412 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1271 12:40:22.098584 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =77
1272 12:40:22.101777 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1273 12:40:22.101860
1274 12:40:22.101926
1275 12:40:22.101985 ==
1276 12:40:22.105383 Dram Type= 6, Freq= 0, CH_0, rank 1
1277 12:40:22.108800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1278 12:40:22.108884 ==
1279 12:40:22.111917
1280 12:40:22.112025
1281 12:40:22.112110 TX Vref Scan disable
1282 12:40:22.115424 == TX Byte 0 ==
1283 12:40:22.118879 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1284 12:40:22.121909 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1285 12:40:22.125293 == TX Byte 1 ==
1286 12:40:22.129000 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1287 12:40:22.132288 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1288 12:40:22.132372 ==
1289 12:40:22.135827 Dram Type= 6, Freq= 0, CH_0, rank 1
1290 12:40:22.142192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1291 12:40:22.142302 ==
1292 12:40:22.154291 TX Vref=22, minBit 0, minWin=27, winSum=441
1293 12:40:22.157363 TX Vref=24, minBit 1, minWin=27, winSum=446
1294 12:40:22.161186 TX Vref=26, minBit 1, minWin=27, winSum=449
1295 12:40:22.164304 TX Vref=28, minBit 1, minWin=27, winSum=448
1296 12:40:22.167635 TX Vref=30, minBit 2, minWin=27, winSum=450
1297 12:40:22.171368 TX Vref=32, minBit 1, minWin=27, winSum=449
1298 12:40:22.177430 [TxChooseVref] Worse bit 2, Min win 27, Win sum 450, Final Vref 30
1299 12:40:22.177514
1300 12:40:22.180925 Final TX Range 1 Vref 30
1301 12:40:22.181008
1302 12:40:22.181074 ==
1303 12:40:22.184297 Dram Type= 6, Freq= 0, CH_0, rank 1
1304 12:40:22.187595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1305 12:40:22.187679 ==
1306 12:40:22.187745
1307 12:40:22.191196
1308 12:40:22.191305 TX Vref Scan disable
1309 12:40:22.193999 == TX Byte 0 ==
1310 12:40:22.197541 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1311 12:40:22.200648 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1312 12:40:22.204608 == TX Byte 1 ==
1313 12:40:22.207515 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1314 12:40:22.214315 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1315 12:40:22.214397
1316 12:40:22.214461 [DATLAT]
1317 12:40:22.214522 Freq=800, CH0 RK1
1318 12:40:22.214580
1319 12:40:22.217823 DATLAT Default: 0xa
1320 12:40:22.217904 0, 0xFFFF, sum = 0
1321 12:40:22.220965 1, 0xFFFF, sum = 0
1322 12:40:22.221047 2, 0xFFFF, sum = 0
1323 12:40:22.223886 3, 0xFFFF, sum = 0
1324 12:40:22.227247 4, 0xFFFF, sum = 0
1325 12:40:22.227330 5, 0xFFFF, sum = 0
1326 12:40:22.230782 6, 0xFFFF, sum = 0
1327 12:40:22.230864 7, 0xFFFF, sum = 0
1328 12:40:22.233783 8, 0xFFFF, sum = 0
1329 12:40:22.233866 9, 0x0, sum = 1
1330 12:40:22.233931 10, 0x0, sum = 2
1331 12:40:22.238204 11, 0x0, sum = 3
1332 12:40:22.238286 12, 0x0, sum = 4
1333 12:40:22.240785 best_step = 10
1334 12:40:22.240866
1335 12:40:22.240929 ==
1336 12:40:22.244227 Dram Type= 6, Freq= 0, CH_0, rank 1
1337 12:40:22.247503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1338 12:40:22.247585 ==
1339 12:40:22.250671 RX Vref Scan: 0
1340 12:40:22.250752
1341 12:40:22.250817 RX Vref 0 -> 0, step: 1
1342 12:40:22.254025
1343 12:40:22.254106 RX Delay -95 -> 252, step: 8
1344 12:40:22.261309 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1345 12:40:22.264399 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1346 12:40:22.267837 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1347 12:40:22.270628 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1348 12:40:22.274751 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1349 12:40:22.280605 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1350 12:40:22.283713 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1351 12:40:22.287408 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1352 12:40:22.290478 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1353 12:40:22.293736 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1354 12:40:22.301192 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1355 12:40:22.303772 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1356 12:40:22.307465 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1357 12:40:22.310773 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1358 12:40:22.317130 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1359 12:40:22.320615 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1360 12:40:22.320696 ==
1361 12:40:22.323494 Dram Type= 6, Freq= 0, CH_0, rank 1
1362 12:40:22.327072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1363 12:40:22.327155 ==
1364 12:40:22.330757 DQS Delay:
1365 12:40:22.330838 DQS0 = 0, DQS1 = 0
1366 12:40:22.330903 DQM Delay:
1367 12:40:22.333678 DQM0 = 86, DQM1 = 77
1368 12:40:22.333759 DQ Delay:
1369 12:40:22.336792 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1370 12:40:22.340287 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1371 12:40:22.343685 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =72
1372 12:40:22.346909 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1373 12:40:22.347017
1374 12:40:22.347110
1375 12:40:22.357133 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b28, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
1376 12:40:22.357225 CH0 RK1: MR19=606, MR18=2B28
1377 12:40:22.363510 CH0_RK1: MR19=0x606, MR18=0x2B28, DQSOSC=398, MR23=63, INC=93, DEC=62
1378 12:40:22.366715 [RxdqsGatingPostProcess] freq 800
1379 12:40:22.373799 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1380 12:40:22.376778 Pre-setting of DQS Precalculation
1381 12:40:22.380170 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1382 12:40:22.380253 ==
1383 12:40:22.383233 Dram Type= 6, Freq= 0, CH_1, rank 0
1384 12:40:22.389826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1385 12:40:22.389910 ==
1386 12:40:22.393291 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1387 12:40:22.399799 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1388 12:40:22.409154 [CA 0] Center 36 (6~67) winsize 62
1389 12:40:22.412479 [CA 1] Center 37 (6~68) winsize 63
1390 12:40:22.415992 [CA 2] Center 35 (5~66) winsize 62
1391 12:40:22.419474 [CA 3] Center 34 (4~65) winsize 62
1392 12:40:22.422144 [CA 4] Center 34 (4~65) winsize 62
1393 12:40:22.425771 [CA 5] Center 33 (3~64) winsize 62
1394 12:40:22.425852
1395 12:40:22.429222 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1396 12:40:22.429304
1397 12:40:22.432502 [CATrainingPosCal] consider 1 rank data
1398 12:40:22.435689 u2DelayCellTimex100 = 270/100 ps
1399 12:40:22.438890 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1400 12:40:22.445685 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1401 12:40:22.449194 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
1402 12:40:22.452046 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1403 12:40:22.455294 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1404 12:40:22.458536 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1405 12:40:22.458619
1406 12:40:22.461896 CA PerBit enable=1, Macro0, CA PI delay=33
1407 12:40:22.461978
1408 12:40:22.465746 [CBTSetCACLKResult] CA Dly = 33
1409 12:40:22.468673 CS Dly: 4 (0~35)
1410 12:40:22.468755 ==
1411 12:40:22.472591 Dram Type= 6, Freq= 0, CH_1, rank 1
1412 12:40:22.475317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1413 12:40:22.475399 ==
1414 12:40:22.482007 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1415 12:40:22.485395 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1416 12:40:22.495271 [CA 0] Center 36 (6~67) winsize 62
1417 12:40:22.498727 [CA 1] Center 36 (6~67) winsize 62
1418 12:40:22.502035 [CA 2] Center 35 (5~65) winsize 61
1419 12:40:22.505040 [CA 3] Center 34 (3~65) winsize 63
1420 12:40:22.508656 [CA 4] Center 34 (3~65) winsize 63
1421 12:40:22.512696 [CA 5] Center 33 (3~64) winsize 62
1422 12:40:22.512779
1423 12:40:22.515817 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1424 12:40:22.515901
1425 12:40:22.519221 [CATrainingPosCal] consider 2 rank data
1426 12:40:22.521987 u2DelayCellTimex100 = 270/100 ps
1427 12:40:22.525855 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1428 12:40:22.529215 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1429 12:40:22.533200 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1430 12:40:22.537351 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1431 12:40:22.540754 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1432 12:40:22.544319 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1433 12:40:22.544453
1434 12:40:22.548284 CA PerBit enable=1, Macro0, CA PI delay=33
1435 12:40:22.548368
1436 12:40:22.551376 [CBTSetCACLKResult] CA Dly = 33
1437 12:40:22.554743 CS Dly: 5 (0~37)
1438 12:40:22.554845
1439 12:40:22.558849 ----->DramcWriteLeveling(PI) begin...
1440 12:40:22.558963 ==
1441 12:40:22.562283 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 12:40:22.565092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 12:40:22.565174 ==
1444 12:40:22.568513 Write leveling (Byte 0): 26 => 26
1445 12:40:22.572067 Write leveling (Byte 1): 26 => 26
1446 12:40:22.575062 DramcWriteLeveling(PI) end<-----
1447 12:40:22.575157
1448 12:40:22.575223 ==
1449 12:40:22.578642 Dram Type= 6, Freq= 0, CH_1, rank 0
1450 12:40:22.581909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1451 12:40:22.581991 ==
1452 12:40:22.585391 [Gating] SW mode calibration
1453 12:40:22.591712 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1454 12:40:22.598262 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1455 12:40:22.601700 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1456 12:40:22.605019 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1457 12:40:22.608273 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 12:40:22.615461 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 12:40:22.618536 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 12:40:22.621683 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 12:40:22.628348 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 12:40:22.631408 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 12:40:22.634906 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 12:40:22.641353 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 12:40:22.644889 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 12:40:22.648230 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 12:40:22.654919 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 12:40:22.658902 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 12:40:22.661889 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 12:40:22.667909 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 12:40:22.671145 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1472 12:40:22.675082 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1473 12:40:22.681424 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1474 12:40:22.684483 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 12:40:22.687982 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 12:40:22.694939 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 12:40:22.697823 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 12:40:22.701275 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 12:40:22.707598 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 12:40:22.711069 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1481 12:40:22.714293 0 9 8 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1482 12:40:22.721099 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 12:40:22.724204 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 12:40:22.727519 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 12:40:22.733997 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 12:40:22.737460 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 12:40:22.740689 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1488 12:40:22.747684 0 10 4 | B1->B0 | 3232 2f2f | 1 0 | (1 0) (0 0)
1489 12:40:22.750356 0 10 8 | B1->B0 | 2a2a 2424 | 0 0 | (0 0) (0 0)
1490 12:40:22.753655 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 12:40:22.760611 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 12:40:22.763516 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 12:40:22.767255 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 12:40:22.773688 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 12:40:22.776882 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 12:40:22.780878 0 11 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1497 12:40:22.786969 0 11 8 | B1->B0 | 3939 4545 | 0 0 | (1 1) (0 0)
1498 12:40:22.790051 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 12:40:22.793430 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 12:40:22.799954 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 12:40:22.802989 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 12:40:22.807032 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 12:40:22.813086 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1504 12:40:22.816372 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 12:40:22.819750 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1506 12:40:22.826556 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 12:40:22.829650 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 12:40:22.832750 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 12:40:22.839644 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 12:40:22.842740 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 12:40:22.847429 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 12:40:22.853311 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 12:40:22.855818 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 12:40:22.859817 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 12:40:22.865747 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 12:40:22.869713 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 12:40:22.872757 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 12:40:22.878987 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 12:40:22.882304 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 12:40:22.885842 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1521 12:40:22.892733 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1522 12:40:22.892816 Total UI for P1: 0, mck2ui 16
1523 12:40:22.899295 best dqsien dly found for B0: ( 0, 14, 4)
1524 12:40:22.899378 Total UI for P1: 0, mck2ui 16
1525 12:40:22.905823 best dqsien dly found for B1: ( 0, 14, 4)
1526 12:40:22.909091 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1527 12:40:22.912390 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1528 12:40:22.912472
1529 12:40:22.915695 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1530 12:40:22.918805 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1531 12:40:22.922508 [Gating] SW calibration Done
1532 12:40:22.922590 ==
1533 12:40:22.926420 Dram Type= 6, Freq= 0, CH_1, rank 0
1534 12:40:22.929441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1535 12:40:22.929529 ==
1536 12:40:22.933635 RX Vref Scan: 0
1537 12:40:22.933756
1538 12:40:22.933821 RX Vref 0 -> 0, step: 1
1539 12:40:22.933882
1540 12:40:22.935771 RX Delay -130 -> 252, step: 16
1541 12:40:22.938861 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1542 12:40:22.946045 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1543 12:40:22.949092 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1544 12:40:22.952216 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1545 12:40:22.955751 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1546 12:40:22.958890 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1547 12:40:22.965920 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1548 12:40:22.968944 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1549 12:40:22.971945 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1550 12:40:22.975982 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1551 12:40:22.979329 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1552 12:40:22.985119 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1553 12:40:22.988817 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1554 12:40:22.991839 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1555 12:40:22.995205 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1556 12:40:23.001875 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1557 12:40:23.001957 ==
1558 12:40:23.005328 Dram Type= 6, Freq= 0, CH_1, rank 0
1559 12:40:23.008786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1560 12:40:23.008868 ==
1561 12:40:23.008932 DQS Delay:
1562 12:40:23.011638 DQS0 = 0, DQS1 = 0
1563 12:40:23.011719 DQM Delay:
1564 12:40:23.015112 DQM0 = 86, DQM1 = 78
1565 12:40:23.015193 DQ Delay:
1566 12:40:23.018647 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1567 12:40:23.021597 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1568 12:40:23.025212 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1569 12:40:23.028309 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1570 12:40:23.028429
1571 12:40:23.028545
1572 12:40:23.028607 ==
1573 12:40:23.031386 Dram Type= 6, Freq= 0, CH_1, rank 0
1574 12:40:23.035608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1575 12:40:23.035690 ==
1576 12:40:23.035755
1577 12:40:23.035816
1578 12:40:23.038067 TX Vref Scan disable
1579 12:40:23.041774 == TX Byte 0 ==
1580 12:40:23.044966 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1581 12:40:23.048025 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1582 12:40:23.051420 == TX Byte 1 ==
1583 12:40:23.055238 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1584 12:40:23.058323 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1585 12:40:23.058404 ==
1586 12:40:23.061299 Dram Type= 6, Freq= 0, CH_1, rank 0
1587 12:40:23.067666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1588 12:40:23.067748 ==
1589 12:40:23.079439 TX Vref=22, minBit 2, minWin=26, winSum=443
1590 12:40:23.083307 TX Vref=24, minBit 0, minWin=27, winSum=446
1591 12:40:23.086217 TX Vref=26, minBit 5, minWin=27, winSum=450
1592 12:40:23.089754 TX Vref=28, minBit 4, minWin=27, winSum=452
1593 12:40:23.092723 TX Vref=30, minBit 6, minWin=27, winSum=454
1594 12:40:23.099378 TX Vref=32, minBit 6, minWin=27, winSum=454
1595 12:40:23.102777 [TxChooseVref] Worse bit 6, Min win 27, Win sum 454, Final Vref 30
1596 12:40:23.102860
1597 12:40:23.107113 Final TX Range 1 Vref 30
1598 12:40:23.107195
1599 12:40:23.107260 ==
1600 12:40:23.109998 Dram Type= 6, Freq= 0, CH_1, rank 0
1601 12:40:23.112941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1602 12:40:23.113025 ==
1603 12:40:23.113091
1604 12:40:23.113167
1605 12:40:23.117148 TX Vref Scan disable
1606 12:40:23.119972 == TX Byte 0 ==
1607 12:40:23.122896 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1608 12:40:23.126605 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1609 12:40:23.129962 == TX Byte 1 ==
1610 12:40:23.132748 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1611 12:40:23.136857 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1612 12:40:23.140290
1613 12:40:23.140372 [DATLAT]
1614 12:40:23.140438 Freq=800, CH1 RK0
1615 12:40:23.140499
1616 12:40:23.143206 DATLAT Default: 0xa
1617 12:40:23.143288 0, 0xFFFF, sum = 0
1618 12:40:23.146362 1, 0xFFFF, sum = 0
1619 12:40:23.146446 2, 0xFFFF, sum = 0
1620 12:40:23.150020 3, 0xFFFF, sum = 0
1621 12:40:23.150104 4, 0xFFFF, sum = 0
1622 12:40:23.152998 5, 0xFFFF, sum = 0
1623 12:40:23.153083 6, 0xFFFF, sum = 0
1624 12:40:23.156809 7, 0xFFFF, sum = 0
1625 12:40:23.159730 8, 0xFFFF, sum = 0
1626 12:40:23.159814 9, 0x0, sum = 1
1627 12:40:23.159882 10, 0x0, sum = 2
1628 12:40:23.162866 11, 0x0, sum = 3
1629 12:40:23.162951 12, 0x0, sum = 4
1630 12:40:23.166360 best_step = 10
1631 12:40:23.166443
1632 12:40:23.166508 ==
1633 12:40:23.169636 Dram Type= 6, Freq= 0, CH_1, rank 0
1634 12:40:23.172822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1635 12:40:23.172905 ==
1636 12:40:23.176347 RX Vref Scan: 1
1637 12:40:23.176430
1638 12:40:23.176496 Set Vref Range= 32 -> 127
1639 12:40:23.176558
1640 12:40:23.179667 RX Vref 32 -> 127, step: 1
1641 12:40:23.179750
1642 12:40:23.182879 RX Delay -95 -> 252, step: 8
1643 12:40:23.182962
1644 12:40:23.186506 Set Vref, RX VrefLevel [Byte0]: 32
1645 12:40:23.189401 [Byte1]: 32
1646 12:40:23.189484
1647 12:40:23.192942 Set Vref, RX VrefLevel [Byte0]: 33
1648 12:40:23.196752 [Byte1]: 33
1649 12:40:23.200134
1650 12:40:23.200216 Set Vref, RX VrefLevel [Byte0]: 34
1651 12:40:23.203591 [Byte1]: 34
1652 12:40:23.207999
1653 12:40:23.208119 Set Vref, RX VrefLevel [Byte0]: 35
1654 12:40:23.211119 [Byte1]: 35
1655 12:40:23.215049
1656 12:40:23.215132 Set Vref, RX VrefLevel [Byte0]: 36
1657 12:40:23.218475 [Byte1]: 36
1658 12:40:23.222730
1659 12:40:23.222813 Set Vref, RX VrefLevel [Byte0]: 37
1660 12:40:23.226114 [Byte1]: 37
1661 12:40:23.230094
1662 12:40:23.230180 Set Vref, RX VrefLevel [Byte0]: 38
1663 12:40:23.233636 [Byte1]: 38
1664 12:40:23.238008
1665 12:40:23.238091 Set Vref, RX VrefLevel [Byte0]: 39
1666 12:40:23.240988 [Byte1]: 39
1667 12:40:23.245366
1668 12:40:23.245474 Set Vref, RX VrefLevel [Byte0]: 40
1669 12:40:23.248637 [Byte1]: 40
1670 12:40:23.252967
1671 12:40:23.253049 Set Vref, RX VrefLevel [Byte0]: 41
1672 12:40:23.257099 [Byte1]: 41
1673 12:40:23.260688
1674 12:40:23.260770 Set Vref, RX VrefLevel [Byte0]: 42
1675 12:40:23.264049 [Byte1]: 42
1676 12:40:23.267995
1677 12:40:23.268102 Set Vref, RX VrefLevel [Byte0]: 43
1678 12:40:23.271486 [Byte1]: 43
1679 12:40:23.276048
1680 12:40:23.276174 Set Vref, RX VrefLevel [Byte0]: 44
1681 12:40:23.279116 [Byte1]: 44
1682 12:40:23.283950
1683 12:40:23.284056 Set Vref, RX VrefLevel [Byte0]: 45
1684 12:40:23.287124 [Byte1]: 45
1685 12:40:23.291116
1686 12:40:23.291197 Set Vref, RX VrefLevel [Byte0]: 46
1687 12:40:23.294276 [Byte1]: 46
1688 12:40:23.298975
1689 12:40:23.299056 Set Vref, RX VrefLevel [Byte0]: 47
1690 12:40:23.301917 [Byte1]: 47
1691 12:40:23.306134
1692 12:40:23.306215 Set Vref, RX VrefLevel [Byte0]: 48
1693 12:40:23.309743 [Byte1]: 48
1694 12:40:23.314165
1695 12:40:23.314246 Set Vref, RX VrefLevel [Byte0]: 49
1696 12:40:23.317945 [Byte1]: 49
1697 12:40:23.321844
1698 12:40:23.321926 Set Vref, RX VrefLevel [Byte0]: 50
1699 12:40:23.324998 [Byte1]: 50
1700 12:40:23.329156
1701 12:40:23.329239 Set Vref, RX VrefLevel [Byte0]: 51
1702 12:40:23.332439 [Byte1]: 51
1703 12:40:23.337441
1704 12:40:23.337525 Set Vref, RX VrefLevel [Byte0]: 52
1705 12:40:23.340006 [Byte1]: 52
1706 12:40:23.344212
1707 12:40:23.344293 Set Vref, RX VrefLevel [Byte0]: 53
1708 12:40:23.347342 [Byte1]: 53
1709 12:40:23.351677
1710 12:40:23.351758 Set Vref, RX VrefLevel [Byte0]: 54
1711 12:40:23.355000 [Byte1]: 54
1712 12:40:23.359240
1713 12:40:23.359322 Set Vref, RX VrefLevel [Byte0]: 55
1714 12:40:23.366257 [Byte1]: 55
1715 12:40:23.366339
1716 12:40:23.369080 Set Vref, RX VrefLevel [Byte0]: 56
1717 12:40:23.372394 [Byte1]: 56
1718 12:40:23.372476
1719 12:40:23.376190 Set Vref, RX VrefLevel [Byte0]: 57
1720 12:40:23.379347 [Byte1]: 57
1721 12:40:23.379443
1722 12:40:23.382878 Set Vref, RX VrefLevel [Byte0]: 58
1723 12:40:23.385864 [Byte1]: 58
1724 12:40:23.389958
1725 12:40:23.390039 Set Vref, RX VrefLevel [Byte0]: 59
1726 12:40:23.393048 [Byte1]: 59
1727 12:40:23.397468
1728 12:40:23.397559 Set Vref, RX VrefLevel [Byte0]: 60
1729 12:40:23.400551 [Byte1]: 60
1730 12:40:23.404975
1731 12:40:23.405058 Set Vref, RX VrefLevel [Byte0]: 61
1732 12:40:23.408395 [Byte1]: 61
1733 12:40:23.412436
1734 12:40:23.412519 Set Vref, RX VrefLevel [Byte0]: 62
1735 12:40:23.415984 [Byte1]: 62
1736 12:40:23.420148
1737 12:40:23.420261 Set Vref, RX VrefLevel [Byte0]: 63
1738 12:40:23.423376 [Byte1]: 63
1739 12:40:23.427878
1740 12:40:23.428012 Set Vref, RX VrefLevel [Byte0]: 64
1741 12:40:23.431929 [Byte1]: 64
1742 12:40:23.435469
1743 12:40:23.435551 Set Vref, RX VrefLevel [Byte0]: 65
1744 12:40:23.438595 [Byte1]: 65
1745 12:40:23.442994
1746 12:40:23.443113 Set Vref, RX VrefLevel [Byte0]: 66
1747 12:40:23.446186 [Byte1]: 66
1748 12:40:23.450460
1749 12:40:23.450543 Set Vref, RX VrefLevel [Byte0]: 67
1750 12:40:23.453855 [Byte1]: 67
1751 12:40:23.458857
1752 12:40:23.458940 Set Vref, RX VrefLevel [Byte0]: 68
1753 12:40:23.461150 [Byte1]: 68
1754 12:40:23.466149
1755 12:40:23.466267 Set Vref, RX VrefLevel [Byte0]: 69
1756 12:40:23.469130 [Byte1]: 69
1757 12:40:23.473233
1758 12:40:23.473315 Set Vref, RX VrefLevel [Byte0]: 70
1759 12:40:23.476904 [Byte1]: 70
1760 12:40:23.481435
1761 12:40:23.481517 Set Vref, RX VrefLevel [Byte0]: 71
1762 12:40:23.484003 [Byte1]: 71
1763 12:40:23.488502
1764 12:40:23.488584 Set Vref, RX VrefLevel [Byte0]: 72
1765 12:40:23.491655 [Byte1]: 72
1766 12:40:23.495982
1767 12:40:23.496103 Set Vref, RX VrefLevel [Byte0]: 73
1768 12:40:23.499386 [Byte1]: 73
1769 12:40:23.504229
1770 12:40:23.504311 Final RX Vref Byte 0 = 59 to rank0
1771 12:40:23.507053 Final RX Vref Byte 1 = 59 to rank0
1772 12:40:23.510799 Final RX Vref Byte 0 = 59 to rank1
1773 12:40:23.513490 Final RX Vref Byte 1 = 59 to rank1==
1774 12:40:23.516898 Dram Type= 6, Freq= 0, CH_1, rank 0
1775 12:40:23.523823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1776 12:40:23.523922 ==
1777 12:40:23.524020 DQS Delay:
1778 12:40:23.524139 DQS0 = 0, DQS1 = 0
1779 12:40:23.526871 DQM Delay:
1780 12:40:23.526952 DQM0 = 86, DQM1 = 80
1781 12:40:23.530570 DQ Delay:
1782 12:40:23.533673 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1783 12:40:23.537395 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
1784 12:40:23.540411 DQ8 =72, DQ9 =72, DQ10 =76, DQ11 =72
1785 12:40:23.544155 DQ12 =88, DQ13 =92, DQ14 =84, DQ15 =88
1786 12:40:23.544240
1787 12:40:23.544304
1788 12:40:23.549955 [DQSOSCAuto] RK0, (LSB)MR18= 0x1629, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 404 ps
1789 12:40:23.553672 CH1 RK0: MR19=606, MR18=1629
1790 12:40:23.560233 CH1_RK0: MR19=0x606, MR18=0x1629, DQSOSC=399, MR23=63, INC=92, DEC=61
1791 12:40:23.560315
1792 12:40:23.563411 ----->DramcWriteLeveling(PI) begin...
1793 12:40:23.563518 ==
1794 12:40:23.566749 Dram Type= 6, Freq= 0, CH_1, rank 1
1795 12:40:23.570124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1796 12:40:23.570205 ==
1797 12:40:23.573639 Write leveling (Byte 0): 28 => 28
1798 12:40:23.576937 Write leveling (Byte 1): 29 => 29
1799 12:40:23.580007 DramcWriteLeveling(PI) end<-----
1800 12:40:23.580112
1801 12:40:23.580178 ==
1802 12:40:23.583271 Dram Type= 6, Freq= 0, CH_1, rank 1
1803 12:40:23.586997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1804 12:40:23.587079 ==
1805 12:40:23.590138 [Gating] SW mode calibration
1806 12:40:23.596271 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1807 12:40:23.603062 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1808 12:40:23.606818 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1809 12:40:23.612954 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1810 12:40:23.616397 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1811 12:40:23.619544 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 12:40:23.626508 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 12:40:23.629762 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 12:40:23.632689 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 12:40:23.636423 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 12:40:23.643268 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 12:40:23.646659 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 12:40:23.650081 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 12:40:23.656373 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 12:40:23.661197 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 12:40:23.663457 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 12:40:23.669351 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 12:40:23.672810 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 12:40:23.676126 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1825 12:40:23.682560 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1826 12:40:23.685976 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 12:40:23.689232 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 12:40:23.695837 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 12:40:23.699273 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 12:40:23.702634 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 12:40:23.709108 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 12:40:23.712635 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 12:40:23.716420 0 9 4 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
1834 12:40:23.723298 0 9 8 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
1835 12:40:23.725769 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 12:40:23.729677 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 12:40:23.735866 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 12:40:23.739152 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 12:40:23.742741 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 12:40:23.749373 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 12:40:23.752268 0 10 4 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 1)
1842 12:40:23.755712 0 10 8 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
1843 12:40:23.762831 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 12:40:23.766675 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 12:40:23.768859 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 12:40:23.775947 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 12:40:23.779029 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 12:40:23.782239 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 12:40:23.788616 0 11 4 | B1->B0 | 2525 3f3f | 0 1 | (0 0) (0 0)
1850 12:40:23.791947 0 11 8 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
1851 12:40:23.795287 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 12:40:23.802025 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 12:40:23.805468 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 12:40:23.808490 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 12:40:23.812043 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 12:40:23.818643 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1857 12:40:23.822549 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1858 12:40:23.824997 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1859 12:40:23.831919 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 12:40:23.835243 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 12:40:23.838526 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 12:40:23.845312 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 12:40:23.848685 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 12:40:23.851837 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 12:40:23.858411 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 12:40:23.861705 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 12:40:23.864646 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 12:40:23.871607 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 12:40:23.874605 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 12:40:23.878132 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 12:40:23.884598 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 12:40:23.887937 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1873 12:40:23.890990 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1874 12:40:23.895291 Total UI for P1: 0, mck2ui 16
1875 12:40:23.898040 best dqsien dly found for B0: ( 0, 14, 0)
1876 12:40:23.904470 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1877 12:40:23.907938 Total UI for P1: 0, mck2ui 16
1878 12:40:23.910956 best dqsien dly found for B1: ( 0, 14, 6)
1879 12:40:23.914632 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1880 12:40:23.917873 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1881 12:40:23.917957
1882 12:40:23.921144 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1883 12:40:23.924455 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1884 12:40:23.927902 [Gating] SW calibration Done
1885 12:40:23.927986 ==
1886 12:40:23.931521 Dram Type= 6, Freq= 0, CH_1, rank 1
1887 12:40:23.935042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1888 12:40:23.935127 ==
1889 12:40:23.937748 RX Vref Scan: 0
1890 12:40:23.937831
1891 12:40:23.937898 RX Vref 0 -> 0, step: 1
1892 12:40:23.937960
1893 12:40:23.941651 RX Delay -130 -> 252, step: 16
1894 12:40:23.944562 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1895 12:40:23.951407 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1896 12:40:23.954194 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1897 12:40:23.957628 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1898 12:40:23.961303 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1899 12:40:23.964746 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1900 12:40:23.971470 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1901 12:40:23.974181 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1902 12:40:23.977686 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1903 12:40:23.981170 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1904 12:40:23.984282 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1905 12:40:23.990730 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1906 12:40:23.993981 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1907 12:40:23.997461 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1908 12:40:24.000447 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1909 12:40:24.007774 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1910 12:40:24.007857 ==
1911 12:40:24.010382 Dram Type= 6, Freq= 0, CH_1, rank 1
1912 12:40:24.014021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1913 12:40:24.014112 ==
1914 12:40:24.014180 DQS Delay:
1915 12:40:24.017306 DQS0 = 0, DQS1 = 0
1916 12:40:24.017388 DQM Delay:
1917 12:40:24.020194 DQM0 = 84, DQM1 = 81
1918 12:40:24.020276 DQ Delay:
1919 12:40:24.024416 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1920 12:40:24.027132 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =85
1921 12:40:24.030541 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1922 12:40:24.033969 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1923 12:40:24.034051
1924 12:40:24.034117
1925 12:40:24.034178 ==
1926 12:40:24.037241 Dram Type= 6, Freq= 0, CH_1, rank 1
1927 12:40:24.040562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1928 12:40:24.040673 ==
1929 12:40:24.043658
1930 12:40:24.043740
1931 12:40:24.043805 TX Vref Scan disable
1932 12:40:24.047109 == TX Byte 0 ==
1933 12:40:24.050808 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1934 12:40:24.054149 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1935 12:40:24.057531 == TX Byte 1 ==
1936 12:40:24.060474 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1937 12:40:24.064014 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1938 12:40:24.064120 ==
1939 12:40:24.067163 Dram Type= 6, Freq= 0, CH_1, rank 1
1940 12:40:24.073369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1941 12:40:24.073451 ==
1942 12:40:24.085796 TX Vref=22, minBit 1, minWin=27, winSum=448
1943 12:40:24.089383 TX Vref=24, minBit 1, minWin=27, winSum=448
1944 12:40:24.092225 TX Vref=26, minBit 1, minWin=27, winSum=452
1945 12:40:24.095429 TX Vref=28, minBit 1, minWin=27, winSum=453
1946 12:40:24.098677 TX Vref=30, minBit 5, minWin=27, winSum=453
1947 12:40:24.102124 TX Vref=32, minBit 1, minWin=27, winSum=450
1948 12:40:24.108997 [TxChooseVref] Worse bit 1, Min win 27, Win sum 453, Final Vref 28
1949 12:40:24.109080
1950 12:40:24.112440 Final TX Range 1 Vref 28
1951 12:40:24.112523
1952 12:40:24.112588 ==
1953 12:40:24.115334 Dram Type= 6, Freq= 0, CH_1, rank 1
1954 12:40:24.118648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1955 12:40:24.118730 ==
1956 12:40:24.122093
1957 12:40:24.122175
1958 12:40:24.122239 TX Vref Scan disable
1959 12:40:24.125266 == TX Byte 0 ==
1960 12:40:24.128523 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1961 12:40:24.135666 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1962 12:40:24.135748 == TX Byte 1 ==
1963 12:40:24.139449 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1964 12:40:24.145268 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1965 12:40:24.145351
1966 12:40:24.145417 [DATLAT]
1967 12:40:24.145478 Freq=800, CH1 RK1
1968 12:40:24.145537
1969 12:40:24.148754 DATLAT Default: 0xa
1970 12:40:24.148835 0, 0xFFFF, sum = 0
1971 12:40:24.151924 1, 0xFFFF, sum = 0
1972 12:40:24.152023 2, 0xFFFF, sum = 0
1973 12:40:24.155503 3, 0xFFFF, sum = 0
1974 12:40:24.158945 4, 0xFFFF, sum = 0
1975 12:40:24.159029 5, 0xFFFF, sum = 0
1976 12:40:24.162322 6, 0xFFFF, sum = 0
1977 12:40:24.162406 7, 0xFFFF, sum = 0
1978 12:40:24.165472 8, 0xFFFF, sum = 0
1979 12:40:24.165555 9, 0x0, sum = 1
1980 12:40:24.168230 10, 0x0, sum = 2
1981 12:40:24.168318 11, 0x0, sum = 3
1982 12:40:24.168384 12, 0x0, sum = 4
1983 12:40:24.172179 best_step = 10
1984 12:40:24.172262
1985 12:40:24.172326 ==
1986 12:40:24.175438 Dram Type= 6, Freq= 0, CH_1, rank 1
1987 12:40:24.178988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1988 12:40:24.179071 ==
1989 12:40:24.181557 RX Vref Scan: 0
1990 12:40:24.181639
1991 12:40:24.181704 RX Vref 0 -> 0, step: 1
1992 12:40:24.184951
1993 12:40:24.185032 RX Delay -95 -> 252, step: 8
1994 12:40:24.192260 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
1995 12:40:24.195645 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1996 12:40:24.198564 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1997 12:40:24.202348 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1998 12:40:24.205493 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1999 12:40:24.211778 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2000 12:40:24.215073 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2001 12:40:24.218735 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2002 12:40:24.221981 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
2003 12:40:24.225261 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2004 12:40:24.232000 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2005 12:40:24.235394 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2006 12:40:24.238820 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2007 12:40:24.241481 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2008 12:40:24.249025 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2009 12:40:24.251749 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2010 12:40:24.251832 ==
2011 12:40:24.254955 Dram Type= 6, Freq= 0, CH_1, rank 1
2012 12:40:24.258284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2013 12:40:24.258367 ==
2014 12:40:24.258433 DQS Delay:
2015 12:40:24.262212 DQS0 = 0, DQS1 = 0
2016 12:40:24.262294 DQM Delay:
2017 12:40:24.264939 DQM0 = 86, DQM1 = 84
2018 12:40:24.265021 DQ Delay:
2019 12:40:24.268288 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =80
2020 12:40:24.271760 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2021 12:40:24.275073 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =80
2022 12:40:24.278204 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
2023 12:40:24.278286
2024 12:40:24.278351
2025 12:40:24.288399 [DQSOSCAuto] RK1, (LSB)MR18= 0x223e, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
2026 12:40:24.288510 CH1 RK1: MR19=606, MR18=223E
2027 12:40:24.294868 CH1_RK1: MR19=0x606, MR18=0x223E, DQSOSC=394, MR23=63, INC=95, DEC=63
2028 12:40:24.298176 [RxdqsGatingPostProcess] freq 800
2029 12:40:24.304754 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2030 12:40:24.308228 Pre-setting of DQS Precalculation
2031 12:40:24.311220 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2032 12:40:24.318030 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2033 12:40:24.328096 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2034 12:40:24.328181
2035 12:40:24.328247
2036 12:40:24.331923 [Calibration Summary] 1600 Mbps
2037 12:40:24.332037 CH 0, Rank 0
2038 12:40:24.334462 SW Impedance : PASS
2039 12:40:24.334545 DUTY Scan : NO K
2040 12:40:24.337895 ZQ Calibration : PASS
2041 12:40:24.337978 Jitter Meter : NO K
2042 12:40:24.341296 CBT Training : PASS
2043 12:40:24.344647 Write leveling : PASS
2044 12:40:24.344733 RX DQS gating : PASS
2045 12:40:24.348199 RX DQ/DQS(RDDQC) : PASS
2046 12:40:24.351843 TX DQ/DQS : PASS
2047 12:40:24.351951 RX DATLAT : PASS
2048 12:40:24.354681 RX DQ/DQS(Engine): PASS
2049 12:40:24.357983 TX OE : NO K
2050 12:40:24.358065 All Pass.
2051 12:40:24.358132
2052 12:40:24.358192 CH 0, Rank 1
2053 12:40:24.361135 SW Impedance : PASS
2054 12:40:24.364751 DUTY Scan : NO K
2055 12:40:24.364833 ZQ Calibration : PASS
2056 12:40:24.368459 Jitter Meter : NO K
2057 12:40:24.371033 CBT Training : PASS
2058 12:40:24.371116 Write leveling : PASS
2059 12:40:24.374742 RX DQS gating : PASS
2060 12:40:24.377790 RX DQ/DQS(RDDQC) : PASS
2061 12:40:24.377873 TX DQ/DQS : PASS
2062 12:40:24.381222 RX DATLAT : PASS
2063 12:40:24.381305 RX DQ/DQS(Engine): PASS
2064 12:40:24.384796 TX OE : NO K
2065 12:40:24.384879 All Pass.
2066 12:40:24.384945
2067 12:40:24.387982 CH 1, Rank 0
2068 12:40:24.388100 SW Impedance : PASS
2069 12:40:24.390894 DUTY Scan : NO K
2070 12:40:24.394506 ZQ Calibration : PASS
2071 12:40:24.394615 Jitter Meter : NO K
2072 12:40:24.397642 CBT Training : PASS
2073 12:40:24.400804 Write leveling : PASS
2074 12:40:24.400887 RX DQS gating : PASS
2075 12:40:24.404293 RX DQ/DQS(RDDQC) : PASS
2076 12:40:24.407627 TX DQ/DQS : PASS
2077 12:40:24.407711 RX DATLAT : PASS
2078 12:40:24.410675 RX DQ/DQS(Engine): PASS
2079 12:40:24.414469 TX OE : NO K
2080 12:40:24.414552 All Pass.
2081 12:40:24.414641
2082 12:40:24.414718 CH 1, Rank 1
2083 12:40:24.417638 SW Impedance : PASS
2084 12:40:24.421373 DUTY Scan : NO K
2085 12:40:24.421456 ZQ Calibration : PASS
2086 12:40:24.424280 Jitter Meter : NO K
2087 12:40:24.427656 CBT Training : PASS
2088 12:40:24.427738 Write leveling : PASS
2089 12:40:24.431151 RX DQS gating : PASS
2090 12:40:24.434307 RX DQ/DQS(RDDQC) : PASS
2091 12:40:24.434390 TX DQ/DQS : PASS
2092 12:40:24.437605 RX DATLAT : PASS
2093 12:40:24.437688 RX DQ/DQS(Engine): PASS
2094 12:40:24.440964 TX OE : NO K
2095 12:40:24.441047 All Pass.
2096 12:40:24.441113
2097 12:40:24.444206 DramC Write-DBI off
2098 12:40:24.447526 PER_BANK_REFRESH: Hybrid Mode
2099 12:40:24.447612 TX_TRACKING: ON
2100 12:40:24.450730 [GetDramInforAfterCalByMRR] Vendor 6.
2101 12:40:24.453770 [GetDramInforAfterCalByMRR] Revision 606.
2102 12:40:24.460598 [GetDramInforAfterCalByMRR] Revision 2 0.
2103 12:40:24.460682 MR0 0x3b3b
2104 12:40:24.460748 MR8 0x5151
2105 12:40:24.464374 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2106 12:40:24.464458
2107 12:40:24.467086 MR0 0x3b3b
2108 12:40:24.467169 MR8 0x5151
2109 12:40:24.470862 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2110 12:40:24.470945
2111 12:40:24.480498 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2112 12:40:24.483931 [FAST_K] Save calibration result to emmc
2113 12:40:24.487348 [FAST_K] Save calibration result to emmc
2114 12:40:24.490156 dram_init: config_dvfs: 1
2115 12:40:24.493514 dramc_set_vcore_voltage set vcore to 662500
2116 12:40:24.496870 Read voltage for 1200, 2
2117 12:40:24.496962 Vio18 = 0
2118 12:40:24.497037 Vcore = 662500
2119 12:40:24.500620 Vdram = 0
2120 12:40:24.500702 Vddq = 0
2121 12:40:24.500801 Vmddr = 0
2122 12:40:24.507162 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2123 12:40:24.510571 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2124 12:40:24.513545 MEM_TYPE=3, freq_sel=15
2125 12:40:24.517052 sv_algorithm_assistance_LP4_1600
2126 12:40:24.520690 ============ PULL DRAM RESETB DOWN ============
2127 12:40:24.523516 ========== PULL DRAM RESETB DOWN end =========
2128 12:40:24.530228 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2129 12:40:24.533183 ===================================
2130 12:40:24.533296 LPDDR4 DRAM CONFIGURATION
2131 12:40:24.536840 ===================================
2132 12:40:24.540417 EX_ROW_EN[0] = 0x0
2133 12:40:24.543408 EX_ROW_EN[1] = 0x0
2134 12:40:24.543491 LP4Y_EN = 0x0
2135 12:40:24.546476 WORK_FSP = 0x0
2136 12:40:24.546568 WL = 0x4
2137 12:40:24.550281 RL = 0x4
2138 12:40:24.550389 BL = 0x2
2139 12:40:24.553366 RPST = 0x0
2140 12:40:24.553449 RD_PRE = 0x0
2141 12:40:24.556660 WR_PRE = 0x1
2142 12:40:24.556775 WR_PST = 0x0
2143 12:40:24.559509 DBI_WR = 0x0
2144 12:40:24.559617 DBI_RD = 0x0
2145 12:40:24.562997 OTF = 0x1
2146 12:40:24.566485 ===================================
2147 12:40:24.569927 ===================================
2148 12:40:24.570010 ANA top config
2149 12:40:24.573434 ===================================
2150 12:40:24.576356 DLL_ASYNC_EN = 0
2151 12:40:24.579989 ALL_SLAVE_EN = 0
2152 12:40:24.583165 NEW_RANK_MODE = 1
2153 12:40:24.583248 DLL_IDLE_MODE = 1
2154 12:40:24.586311 LP45_APHY_COMB_EN = 1
2155 12:40:24.589601 TX_ODT_DIS = 1
2156 12:40:24.593202 NEW_8X_MODE = 1
2157 12:40:24.596249 ===================================
2158 12:40:24.600252 ===================================
2159 12:40:24.603458 data_rate = 2400
2160 12:40:24.603541 CKR = 1
2161 12:40:24.606496 DQ_P2S_RATIO = 8
2162 12:40:24.609301 ===================================
2163 12:40:24.613092 CA_P2S_RATIO = 8
2164 12:40:24.616859 DQ_CA_OPEN = 0
2165 12:40:24.619489 DQ_SEMI_OPEN = 0
2166 12:40:24.623025 CA_SEMI_OPEN = 0
2167 12:40:24.623109 CA_FULL_RATE = 0
2168 12:40:24.626036 DQ_CKDIV4_EN = 0
2169 12:40:24.629197 CA_CKDIV4_EN = 0
2170 12:40:24.632656 CA_PREDIV_EN = 0
2171 12:40:24.636158 PH8_DLY = 17
2172 12:40:24.639319 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2173 12:40:24.642689 DQ_AAMCK_DIV = 4
2174 12:40:24.642772 CA_AAMCK_DIV = 4
2175 12:40:24.645574 CA_ADMCK_DIV = 4
2176 12:40:24.649266 DQ_TRACK_CA_EN = 0
2177 12:40:24.653380 CA_PICK = 1200
2178 12:40:24.656214 CA_MCKIO = 1200
2179 12:40:24.659135 MCKIO_SEMI = 0
2180 12:40:24.662386 PLL_FREQ = 2366
2181 12:40:24.662469 DQ_UI_PI_RATIO = 32
2182 12:40:24.665643 CA_UI_PI_RATIO = 0
2183 12:40:24.669014 ===================================
2184 12:40:24.672025 ===================================
2185 12:40:24.675892 memory_type:LPDDR4
2186 12:40:24.679074 GP_NUM : 10
2187 12:40:24.679156 SRAM_EN : 1
2188 12:40:24.682492 MD32_EN : 0
2189 12:40:24.685915 ===================================
2190 12:40:24.689040 [ANA_INIT] >>>>>>>>>>>>>>
2191 12:40:24.689122 <<<<<< [CONFIGURE PHASE]: ANA_TX
2192 12:40:24.692226 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2193 12:40:24.695570 ===================================
2194 12:40:24.698708 data_rate = 2400,PCW = 0X5b00
2195 12:40:24.702379 ===================================
2196 12:40:24.705396 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2197 12:40:24.712157 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2198 12:40:24.718731 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2199 12:40:24.722379 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2200 12:40:24.725247 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2201 12:40:24.728684 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2202 12:40:24.732020 [ANA_INIT] flow start
2203 12:40:24.732124 [ANA_INIT] PLL >>>>>>>>
2204 12:40:24.735938 [ANA_INIT] PLL <<<<<<<<
2205 12:40:24.738745 [ANA_INIT] MIDPI >>>>>>>>
2206 12:40:24.741702 [ANA_INIT] MIDPI <<<<<<<<
2207 12:40:24.741784 [ANA_INIT] DLL >>>>>>>>
2208 12:40:24.745229 [ANA_INIT] DLL <<<<<<<<
2209 12:40:24.745312 [ANA_INIT] flow end
2210 12:40:24.751856 ============ LP4 DIFF to SE enter ============
2211 12:40:24.755262 ============ LP4 DIFF to SE exit ============
2212 12:40:24.758806 [ANA_INIT] <<<<<<<<<<<<<
2213 12:40:24.761864 [Flow] Enable top DCM control >>>>>
2214 12:40:24.764836 [Flow] Enable top DCM control <<<<<
2215 12:40:24.764951 Enable DLL master slave shuffle
2216 12:40:24.772026 ==============================================================
2217 12:40:24.774871 Gating Mode config
2218 12:40:24.778405 ==============================================================
2219 12:40:24.781894 Config description:
2220 12:40:24.791662 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2221 12:40:24.798709 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2222 12:40:24.801399 SELPH_MODE 0: By rank 1: By Phase
2223 12:40:24.808306 ==============================================================
2224 12:40:24.811614 GAT_TRACK_EN = 1
2225 12:40:24.814827 RX_GATING_MODE = 2
2226 12:40:24.818416 RX_GATING_TRACK_MODE = 2
2227 12:40:24.821964 SELPH_MODE = 1
2228 12:40:24.822046 PICG_EARLY_EN = 1
2229 12:40:24.825012 VALID_LAT_VALUE = 1
2230 12:40:24.831491 ==============================================================
2231 12:40:24.835170 Enter into Gating configuration >>>>
2232 12:40:24.838078 Exit from Gating configuration <<<<
2233 12:40:24.841426 Enter into DVFS_PRE_config >>>>>
2234 12:40:24.851884 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2235 12:40:24.854976 Exit from DVFS_PRE_config <<<<<
2236 12:40:24.858222 Enter into PICG configuration >>>>
2237 12:40:24.861163 Exit from PICG configuration <<<<
2238 12:40:24.864313 [RX_INPUT] configuration >>>>>
2239 12:40:24.868221 [RX_INPUT] configuration <<<<<
2240 12:40:24.871105 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2241 12:40:24.877678 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2242 12:40:24.884419 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2243 12:40:24.891277 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2244 12:40:24.897499 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2245 12:40:24.903970 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2246 12:40:24.907348 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2247 12:40:24.910851 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2248 12:40:24.914316 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2249 12:40:24.921567 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2250 12:40:24.923851 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2251 12:40:24.927480 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2252 12:40:24.930622 ===================================
2253 12:40:24.933705 LPDDR4 DRAM CONFIGURATION
2254 12:40:24.937343 ===================================
2255 12:40:24.937426 EX_ROW_EN[0] = 0x0
2256 12:40:24.940325 EX_ROW_EN[1] = 0x0
2257 12:40:24.943787 LP4Y_EN = 0x0
2258 12:40:24.943869 WORK_FSP = 0x0
2259 12:40:24.947108 WL = 0x4
2260 12:40:24.947189 RL = 0x4
2261 12:40:24.950235 BL = 0x2
2262 12:40:24.950317 RPST = 0x0
2263 12:40:24.953637 RD_PRE = 0x0
2264 12:40:24.953718 WR_PRE = 0x1
2265 12:40:24.957055 WR_PST = 0x0
2266 12:40:24.957137 DBI_WR = 0x0
2267 12:40:24.960587 DBI_RD = 0x0
2268 12:40:24.960670 OTF = 0x1
2269 12:40:24.963530 ===================================
2270 12:40:24.967310 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2271 12:40:24.973519 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2272 12:40:24.976764 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2273 12:40:24.980243 ===================================
2274 12:40:24.983408 LPDDR4 DRAM CONFIGURATION
2275 12:40:24.986776 ===================================
2276 12:40:24.986858 EX_ROW_EN[0] = 0x10
2277 12:40:24.989758 EX_ROW_EN[1] = 0x0
2278 12:40:24.993162 LP4Y_EN = 0x0
2279 12:40:24.993244 WORK_FSP = 0x0
2280 12:40:24.996834 WL = 0x4
2281 12:40:24.996915 RL = 0x4
2282 12:40:25.000393 BL = 0x2
2283 12:40:25.000475 RPST = 0x0
2284 12:40:25.003607 RD_PRE = 0x0
2285 12:40:25.003688 WR_PRE = 0x1
2286 12:40:25.006653 WR_PST = 0x0
2287 12:40:25.006734 DBI_WR = 0x0
2288 12:40:25.010292 DBI_RD = 0x0
2289 12:40:25.010373 OTF = 0x1
2290 12:40:25.013397 ===================================
2291 12:40:25.020626 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2292 12:40:25.020708 ==
2293 12:40:25.023813 Dram Type= 6, Freq= 0, CH_0, rank 0
2294 12:40:25.026858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2295 12:40:25.026940 ==
2296 12:40:25.029957 [Duty_Offset_Calibration]
2297 12:40:25.033042 B0:2 B1:0 CA:4
2298 12:40:25.033123
2299 12:40:25.036932 [DutyScan_Calibration_Flow] k_type=0
2300 12:40:25.043942
2301 12:40:25.044069 ==CLK 0==
2302 12:40:25.047318 Final CLK duty delay cell = -4
2303 12:40:25.050960 [-4] MAX Duty = 5062%(X100), DQS PI = 32
2304 12:40:25.054204 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2305 12:40:25.057521 [-4] AVG Duty = 4953%(X100)
2306 12:40:25.057644
2307 12:40:25.060583 CH0 CLK Duty spec in!! Max-Min= 218%
2308 12:40:25.064048 [DutyScan_Calibration_Flow] ====Done====
2309 12:40:25.064168
2310 12:40:25.066963 [DutyScan_Calibration_Flow] k_type=1
2311 12:40:25.082983
2312 12:40:25.083066 ==DQS 0 ==
2313 12:40:25.086490 Final DQS duty delay cell = -4
2314 12:40:25.089350 [-4] MAX Duty = 4969%(X100), DQS PI = 14
2315 12:40:25.093313 [-4] MIN Duty = 4876%(X100), DQS PI = 0
2316 12:40:25.096598 [-4] AVG Duty = 4922%(X100)
2317 12:40:25.096678
2318 12:40:25.096741 ==DQS 1 ==
2319 12:40:25.099460 Final DQS duty delay cell = 0
2320 12:40:25.102821 [0] MAX Duty = 5125%(X100), DQS PI = 52
2321 12:40:25.105983 [0] MIN Duty = 4969%(X100), DQS PI = 14
2322 12:40:25.109825 [0] AVG Duty = 5047%(X100)
2323 12:40:25.109904
2324 12:40:25.112777 CH0 DQS 0 Duty spec in!! Max-Min= 93%
2325 12:40:25.112856
2326 12:40:25.115967 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2327 12:40:25.119621 [DutyScan_Calibration_Flow] ====Done====
2328 12:40:25.119701
2329 12:40:25.122707 [DutyScan_Calibration_Flow] k_type=3
2330 12:40:25.139706
2331 12:40:25.139785 ==DQM 0 ==
2332 12:40:25.142880 Final DQM duty delay cell = 0
2333 12:40:25.146189 [0] MAX Duty = 5125%(X100), DQS PI = 20
2334 12:40:25.149508 [0] MIN Duty = 4844%(X100), DQS PI = 50
2335 12:40:25.153119 [0] AVG Duty = 4984%(X100)
2336 12:40:25.153199
2337 12:40:25.153261 ==DQM 1 ==
2338 12:40:25.156104 Final DQM duty delay cell = 0
2339 12:40:25.160224 [0] MAX Duty = 4969%(X100), DQS PI = 2
2340 12:40:25.163551 [0] MIN Duty = 4844%(X100), DQS PI = 20
2341 12:40:25.163657 [0] AVG Duty = 4906%(X100)
2342 12:40:25.166824
2343 12:40:25.169270 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2344 12:40:25.169349
2345 12:40:25.172655 CH0 DQM 1 Duty spec in!! Max-Min= 125%
2346 12:40:25.176377 [DutyScan_Calibration_Flow] ====Done====
2347 12:40:25.176482
2348 12:40:25.179767 [DutyScan_Calibration_Flow] k_type=2
2349 12:40:25.196241
2350 12:40:25.196321 ==DQ 0 ==
2351 12:40:25.199125 Final DQ duty delay cell = 0
2352 12:40:25.203012 [0] MAX Duty = 5156%(X100), DQS PI = 18
2353 12:40:25.206411 [0] MIN Duty = 4969%(X100), DQS PI = 58
2354 12:40:25.206491 [0] AVG Duty = 5062%(X100)
2355 12:40:25.209130
2356 12:40:25.209210 ==DQ 1 ==
2357 12:40:25.212359 Final DQ duty delay cell = 0
2358 12:40:25.215639 [0] MAX Duty = 5156%(X100), DQS PI = 6
2359 12:40:25.219462 [0] MIN Duty = 4938%(X100), DQS PI = 16
2360 12:40:25.219543 [0] AVG Duty = 5047%(X100)
2361 12:40:25.219606
2362 12:40:25.222638 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2363 12:40:25.225850
2364 12:40:25.229007 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2365 12:40:25.232411 [DutyScan_Calibration_Flow] ====Done====
2366 12:40:25.232490 ==
2367 12:40:25.236147 Dram Type= 6, Freq= 0, CH_1, rank 0
2368 12:40:25.239248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2369 12:40:25.239331 ==
2370 12:40:25.242530 [Duty_Offset_Calibration]
2371 12:40:25.242611 B0:0 B1:-1 CA:3
2372 12:40:25.242676
2373 12:40:25.246026 [DutyScan_Calibration_Flow] k_type=0
2374 12:40:25.255082
2375 12:40:25.255165 ==CLK 0==
2376 12:40:25.258476 Final CLK duty delay cell = -4
2377 12:40:25.261885 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2378 12:40:25.265175 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2379 12:40:25.268993 [-4] AVG Duty = 4938%(X100)
2380 12:40:25.269074
2381 12:40:25.271696 CH1 CLK Duty spec in!! Max-Min= 124%
2382 12:40:25.274819 [DutyScan_Calibration_Flow] ====Done====
2383 12:40:25.274902
2384 12:40:25.279031 [DutyScan_Calibration_Flow] k_type=1
2385 12:40:25.294937
2386 12:40:25.295029 ==DQS 0 ==
2387 12:40:25.298072 Final DQS duty delay cell = 0
2388 12:40:25.301774 [0] MAX Duty = 5187%(X100), DQS PI = 18
2389 12:40:25.305099 [0] MIN Duty = 4907%(X100), DQS PI = 38
2390 12:40:25.305210 [0] AVG Duty = 5047%(X100)
2391 12:40:25.308041
2392 12:40:25.308164 ==DQS 1 ==
2393 12:40:25.311413 Final DQS duty delay cell = 0
2394 12:40:25.315088 [0] MAX Duty = 5156%(X100), DQS PI = 8
2395 12:40:25.318121 [0] MIN Duty = 5031%(X100), DQS PI = 18
2396 12:40:25.318224 [0] AVG Duty = 5093%(X100)
2397 12:40:25.321255
2398 12:40:25.324852 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2399 12:40:25.324958
2400 12:40:25.328356 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2401 12:40:25.331510 [DutyScan_Calibration_Flow] ====Done====
2402 12:40:25.331620
2403 12:40:25.334400 [DutyScan_Calibration_Flow] k_type=3
2404 12:40:25.351350
2405 12:40:25.351463 ==DQM 0 ==
2406 12:40:25.355055 Final DQM duty delay cell = 0
2407 12:40:25.357831 [0] MAX Duty = 5031%(X100), DQS PI = 26
2408 12:40:25.361160 [0] MIN Duty = 4813%(X100), DQS PI = 38
2409 12:40:25.364642 [0] AVG Duty = 4922%(X100)
2410 12:40:25.364759
2411 12:40:25.364865 ==DQM 1 ==
2412 12:40:25.368036 Final DQM duty delay cell = 0
2413 12:40:25.371722 [0] MAX Duty = 5000%(X100), DQS PI = 34
2414 12:40:25.374335 [0] MIN Duty = 4844%(X100), DQS PI = 0
2415 12:40:25.377425 [0] AVG Duty = 4922%(X100)
2416 12:40:25.377507
2417 12:40:25.381210 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2418 12:40:25.381292
2419 12:40:25.384882 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2420 12:40:25.387584 [DutyScan_Calibration_Flow] ====Done====
2421 12:40:25.387666
2422 12:40:25.390754 [DutyScan_Calibration_Flow] k_type=2
2423 12:40:25.407717
2424 12:40:25.407816 ==DQ 0 ==
2425 12:40:25.410782 Final DQ duty delay cell = -4
2426 12:40:25.414012 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2427 12:40:25.417927 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2428 12:40:25.420818 [-4] AVG Duty = 4937%(X100)
2429 12:40:25.420901
2430 12:40:25.420966 ==DQ 1 ==
2431 12:40:25.423880 Final DQ duty delay cell = 4
2432 12:40:25.427226 [4] MAX Duty = 5156%(X100), DQS PI = 10
2433 12:40:25.431258 [4] MIN Duty = 5031%(X100), DQS PI = 62
2434 12:40:25.435346 [4] AVG Duty = 5093%(X100)
2435 12:40:25.435429
2436 12:40:25.437858 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2437 12:40:25.437943
2438 12:40:25.440461 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2439 12:40:25.444545 [DutyScan_Calibration_Flow] ====Done====
2440 12:40:25.447563 nWR fixed to 30
2441 12:40:25.450532 [ModeRegInit_LP4] CH0 RK0
2442 12:40:25.450616 [ModeRegInit_LP4] CH0 RK1
2443 12:40:25.453591 [ModeRegInit_LP4] CH1 RK0
2444 12:40:25.457388 [ModeRegInit_LP4] CH1 RK1
2445 12:40:25.457471 match AC timing 7
2446 12:40:25.463707 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2447 12:40:25.466907 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2448 12:40:25.470505 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2449 12:40:25.477406 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2450 12:40:25.480383 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2451 12:40:25.480467 ==
2452 12:40:25.483595 Dram Type= 6, Freq= 0, CH_0, rank 0
2453 12:40:25.487793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2454 12:40:25.487876 ==
2455 12:40:25.493475 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2456 12:40:25.500694 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2457 12:40:25.508001 [CA 0] Center 40 (10~70) winsize 61
2458 12:40:25.511288 [CA 1] Center 39 (8~70) winsize 63
2459 12:40:25.514581 [CA 2] Center 35 (5~66) winsize 62
2460 12:40:25.517878 [CA 3] Center 35 (5~66) winsize 62
2461 12:40:25.521309 [CA 4] Center 33 (3~64) winsize 62
2462 12:40:25.524530 [CA 5] Center 33 (3~64) winsize 62
2463 12:40:25.524621
2464 12:40:25.527717 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2465 12:40:25.527806
2466 12:40:25.531424 [CATrainingPosCal] consider 1 rank data
2467 12:40:25.534313 u2DelayCellTimex100 = 270/100 ps
2468 12:40:25.537797 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2469 12:40:25.544383 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2470 12:40:25.547952 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2471 12:40:25.551519 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2472 12:40:25.554516 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2473 12:40:25.557769 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2474 12:40:25.557854
2475 12:40:25.561235 CA PerBit enable=1, Macro0, CA PI delay=33
2476 12:40:25.561319
2477 12:40:25.564479 [CBTSetCACLKResult] CA Dly = 33
2478 12:40:25.567733 CS Dly: 7 (0~38)
2479 12:40:25.567820 ==
2480 12:40:25.571466 Dram Type= 6, Freq= 0, CH_0, rank 1
2481 12:40:25.574353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2482 12:40:25.574440 ==
2483 12:40:25.581200 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2484 12:40:25.584183 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2485 12:40:25.593771 [CA 0] Center 39 (9~70) winsize 62
2486 12:40:25.597494 [CA 1] Center 39 (9~70) winsize 62
2487 12:40:25.600560 [CA 2] Center 35 (5~66) winsize 62
2488 12:40:25.604321 [CA 3] Center 35 (5~66) winsize 62
2489 12:40:25.606989 [CA 4] Center 34 (4~65) winsize 62
2490 12:40:25.610642 [CA 5] Center 33 (3~64) winsize 62
2491 12:40:25.610729
2492 12:40:25.613885 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2493 12:40:25.613969
2494 12:40:25.618280 [CATrainingPosCal] consider 2 rank data
2495 12:40:25.620925 u2DelayCellTimex100 = 270/100 ps
2496 12:40:25.623994 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2497 12:40:25.630386 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2498 12:40:25.633404 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2499 12:40:25.636888 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2500 12:40:25.640796 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2501 12:40:25.643459 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2502 12:40:25.643543
2503 12:40:25.646813 CA PerBit enable=1, Macro0, CA PI delay=33
2504 12:40:25.646897
2505 12:40:25.650385 [CBTSetCACLKResult] CA Dly = 33
2506 12:40:25.653720 CS Dly: 8 (0~41)
2507 12:40:25.653803
2508 12:40:25.656940 ----->DramcWriteLeveling(PI) begin...
2509 12:40:25.657025 ==
2510 12:40:25.660306 Dram Type= 6, Freq= 0, CH_0, rank 0
2511 12:40:25.663644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2512 12:40:25.663728 ==
2513 12:40:25.666560 Write leveling (Byte 0): 32 => 32
2514 12:40:25.670083 Write leveling (Byte 1): 28 => 28
2515 12:40:25.673450 DramcWriteLeveling(PI) end<-----
2516 12:40:25.673533
2517 12:40:25.673599 ==
2518 12:40:25.676757 Dram Type= 6, Freq= 0, CH_0, rank 0
2519 12:40:25.680153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2520 12:40:25.680244 ==
2521 12:40:25.683398 [Gating] SW mode calibration
2522 12:40:25.689753 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2523 12:40:25.696475 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2524 12:40:25.699574 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2525 12:40:25.703023 0 15 4 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
2526 12:40:25.710203 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2527 12:40:25.713202 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 12:40:25.716475 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 12:40:25.723022 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 12:40:25.726230 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2531 12:40:25.729662 0 15 28 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
2532 12:40:25.736778 1 0 0 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
2533 12:40:25.739762 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2534 12:40:25.743245 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 12:40:25.749578 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 12:40:25.753205 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 12:40:25.756237 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 12:40:25.763324 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2539 12:40:25.766162 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2540 12:40:25.769812 1 1 0 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
2541 12:40:25.776734 1 1 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2542 12:40:25.779623 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 12:40:25.783186 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 12:40:25.786404 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 12:40:25.792659 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 12:40:25.795860 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2547 12:40:25.799326 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2548 12:40:25.806048 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2549 12:40:25.809346 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 12:40:25.813198 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 12:40:25.819752 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 12:40:25.823054 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 12:40:25.826168 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 12:40:25.833265 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 12:40:25.836433 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 12:40:25.839376 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 12:40:25.846221 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 12:40:25.849748 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 12:40:25.852816 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 12:40:25.859209 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 12:40:25.862877 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 12:40:25.865890 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2563 12:40:25.873141 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2564 12:40:25.875956 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2565 12:40:25.879630 Total UI for P1: 0, mck2ui 16
2566 12:40:25.882977 best dqsien dly found for B0: ( 1, 3, 26)
2567 12:40:25.885975 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2568 12:40:25.889446 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2569 12:40:25.892830 Total UI for P1: 0, mck2ui 16
2570 12:40:25.896220 best dqsien dly found for B1: ( 1, 4, 2)
2571 12:40:25.902488 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2572 12:40:25.905840 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2573 12:40:25.905924
2574 12:40:25.909204 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2575 12:40:25.913244 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2576 12:40:25.915460 [Gating] SW calibration Done
2577 12:40:25.915561 ==
2578 12:40:25.919425 Dram Type= 6, Freq= 0, CH_0, rank 0
2579 12:40:25.922638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2580 12:40:25.922721 ==
2581 12:40:25.926180 RX Vref Scan: 0
2582 12:40:25.926262
2583 12:40:25.926326 RX Vref 0 -> 0, step: 1
2584 12:40:25.926386
2585 12:40:25.929289 RX Delay -40 -> 252, step: 8
2586 12:40:25.932347 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2587 12:40:25.936274 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2588 12:40:25.942526 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2589 12:40:25.945945 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2590 12:40:25.949230 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2591 12:40:25.952254 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2592 12:40:25.955936 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2593 12:40:25.962519 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2594 12:40:25.965327 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2595 12:40:25.969038 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2596 12:40:25.972159 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2597 12:40:25.975404 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2598 12:40:25.982178 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2599 12:40:25.985344 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2600 12:40:25.989071 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2601 12:40:25.992400 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2602 12:40:25.992482 ==
2603 12:40:25.995360 Dram Type= 6, Freq= 0, CH_0, rank 0
2604 12:40:26.002515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2605 12:40:26.002598 ==
2606 12:40:26.002663 DQS Delay:
2607 12:40:26.005218 DQS0 = 0, DQS1 = 0
2608 12:40:26.005300 DQM Delay:
2609 12:40:26.005366 DQM0 = 118, DQM1 = 107
2610 12:40:26.008814 DQ Delay:
2611 12:40:26.012169 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2612 12:40:26.015888 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =127
2613 12:40:26.018404 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2614 12:40:26.022098 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2615 12:40:26.022180
2616 12:40:26.022245
2617 12:40:26.022306 ==
2618 12:40:26.025024 Dram Type= 6, Freq= 0, CH_0, rank 0
2619 12:40:26.028869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2620 12:40:26.032148 ==
2621 12:40:26.032231
2622 12:40:26.032296
2623 12:40:26.032357 TX Vref Scan disable
2624 12:40:26.035410 == TX Byte 0 ==
2625 12:40:26.039015 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2626 12:40:26.041762 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2627 12:40:26.045476 == TX Byte 1 ==
2628 12:40:26.048385 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2629 12:40:26.051591 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2630 12:40:26.055463 ==
2631 12:40:26.055545 Dram Type= 6, Freq= 0, CH_0, rank 0
2632 12:40:26.061430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2633 12:40:26.061512 ==
2634 12:40:26.073057 TX Vref=22, minBit 0, minWin=25, winSum=410
2635 12:40:26.076264 TX Vref=24, minBit 1, minWin=25, winSum=416
2636 12:40:26.079855 TX Vref=26, minBit 4, minWin=26, winSum=427
2637 12:40:26.083242 TX Vref=28, minBit 4, minWin=26, winSum=429
2638 12:40:26.086013 TX Vref=30, minBit 1, minWin=26, winSum=430
2639 12:40:26.093282 TX Vref=32, minBit 13, minWin=26, winSum=433
2640 12:40:26.096695 [TxChooseVref] Worse bit 13, Min win 26, Win sum 433, Final Vref 32
2641 12:40:26.096777
2642 12:40:26.099680 Final TX Range 1 Vref 32
2643 12:40:26.099762
2644 12:40:26.099827 ==
2645 12:40:26.102733 Dram Type= 6, Freq= 0, CH_0, rank 0
2646 12:40:26.106059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2647 12:40:26.109700 ==
2648 12:40:26.109781
2649 12:40:26.109845
2650 12:40:26.109905 TX Vref Scan disable
2651 12:40:26.113275 == TX Byte 0 ==
2652 12:40:26.115944 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2653 12:40:26.123057 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2654 12:40:26.123139 == TX Byte 1 ==
2655 12:40:26.126024 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2656 12:40:26.133070 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2657 12:40:26.133152
2658 12:40:26.133217 [DATLAT]
2659 12:40:26.133277 Freq=1200, CH0 RK0
2660 12:40:26.133336
2661 12:40:26.136389 DATLAT Default: 0xd
2662 12:40:26.136469 0, 0xFFFF, sum = 0
2663 12:40:26.139720 1, 0xFFFF, sum = 0
2664 12:40:26.143235 2, 0xFFFF, sum = 0
2665 12:40:26.143317 3, 0xFFFF, sum = 0
2666 12:40:26.145880 4, 0xFFFF, sum = 0
2667 12:40:26.145963 5, 0xFFFF, sum = 0
2668 12:40:26.149611 6, 0xFFFF, sum = 0
2669 12:40:26.149693 7, 0xFFFF, sum = 0
2670 12:40:26.152842 8, 0xFFFF, sum = 0
2671 12:40:26.152926 9, 0xFFFF, sum = 0
2672 12:40:26.155982 10, 0xFFFF, sum = 0
2673 12:40:26.156102 11, 0xFFFF, sum = 0
2674 12:40:26.159579 12, 0x0, sum = 1
2675 12:40:26.159689 13, 0x0, sum = 2
2676 12:40:26.162551 14, 0x0, sum = 3
2677 12:40:26.162634 15, 0x0, sum = 4
2678 12:40:26.165880 best_step = 13
2679 12:40:26.165961
2680 12:40:26.166025 ==
2681 12:40:26.169234 Dram Type= 6, Freq= 0, CH_0, rank 0
2682 12:40:26.172512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2683 12:40:26.172594 ==
2684 12:40:26.172658 RX Vref Scan: 1
2685 12:40:26.172718
2686 12:40:26.175982 Set Vref Range= 32 -> 127
2687 12:40:26.176104
2688 12:40:26.179375 RX Vref 32 -> 127, step: 1
2689 12:40:26.179456
2690 12:40:26.182585 RX Delay -21 -> 252, step: 4
2691 12:40:26.182666
2692 12:40:26.185816 Set Vref, RX VrefLevel [Byte0]: 32
2693 12:40:26.189415 [Byte1]: 32
2694 12:40:26.189496
2695 12:40:26.192963 Set Vref, RX VrefLevel [Byte0]: 33
2696 12:40:26.195673 [Byte1]: 33
2697 12:40:26.199483
2698 12:40:26.199564 Set Vref, RX VrefLevel [Byte0]: 34
2699 12:40:26.202789 [Byte1]: 34
2700 12:40:26.207555
2701 12:40:26.207636 Set Vref, RX VrefLevel [Byte0]: 35
2702 12:40:26.210474 [Byte1]: 35
2703 12:40:26.215496
2704 12:40:26.215576 Set Vref, RX VrefLevel [Byte0]: 36
2705 12:40:26.218400 [Byte1]: 36
2706 12:40:26.222934
2707 12:40:26.223016 Set Vref, RX VrefLevel [Byte0]: 37
2708 12:40:26.226507 [Byte1]: 37
2709 12:40:26.231470
2710 12:40:26.231551 Set Vref, RX VrefLevel [Byte0]: 38
2711 12:40:26.234183 [Byte1]: 38
2712 12:40:26.239176
2713 12:40:26.239257 Set Vref, RX VrefLevel [Byte0]: 39
2714 12:40:26.242319 [Byte1]: 39
2715 12:40:26.247389
2716 12:40:26.247470 Set Vref, RX VrefLevel [Byte0]: 40
2717 12:40:26.250339 [Byte1]: 40
2718 12:40:26.254943
2719 12:40:26.255028 Set Vref, RX VrefLevel [Byte0]: 41
2720 12:40:26.257961 [Byte1]: 41
2721 12:40:26.262863
2722 12:40:26.262951 Set Vref, RX VrefLevel [Byte0]: 42
2723 12:40:26.266267 [Byte1]: 42
2724 12:40:26.270580
2725 12:40:26.270667 Set Vref, RX VrefLevel [Byte0]: 43
2726 12:40:26.273963 [Byte1]: 43
2727 12:40:26.278706
2728 12:40:26.278792 Set Vref, RX VrefLevel [Byte0]: 44
2729 12:40:26.281782 [Byte1]: 44
2730 12:40:26.286345
2731 12:40:26.286430 Set Vref, RX VrefLevel [Byte0]: 45
2732 12:40:26.289892 [Byte1]: 45
2733 12:40:26.294355
2734 12:40:26.294439 Set Vref, RX VrefLevel [Byte0]: 46
2735 12:40:26.298121 [Byte1]: 46
2736 12:40:26.302253
2737 12:40:26.302338 Set Vref, RX VrefLevel [Byte0]: 47
2738 12:40:26.305906 [Byte1]: 47
2739 12:40:26.310596
2740 12:40:26.310679 Set Vref, RX VrefLevel [Byte0]: 48
2741 12:40:26.313894 [Byte1]: 48
2742 12:40:26.318557
2743 12:40:26.318641 Set Vref, RX VrefLevel [Byte0]: 49
2744 12:40:26.322125 [Byte1]: 49
2745 12:40:26.325993
2746 12:40:26.326077 Set Vref, RX VrefLevel [Byte0]: 50
2747 12:40:26.329166 [Byte1]: 50
2748 12:40:26.334228
2749 12:40:26.334315 Set Vref, RX VrefLevel [Byte0]: 51
2750 12:40:26.337622 [Byte1]: 51
2751 12:40:26.342295
2752 12:40:26.342378 Set Vref, RX VrefLevel [Byte0]: 52
2753 12:40:26.345647 [Byte1]: 52
2754 12:40:26.350046
2755 12:40:26.350130 Set Vref, RX VrefLevel [Byte0]: 53
2756 12:40:26.353206 [Byte1]: 53
2757 12:40:26.357866
2758 12:40:26.357954 Set Vref, RX VrefLevel [Byte0]: 54
2759 12:40:26.361386 [Byte1]: 54
2760 12:40:26.366380
2761 12:40:26.366494 Set Vref, RX VrefLevel [Byte0]: 55
2762 12:40:26.369022 [Byte1]: 55
2763 12:40:26.373615
2764 12:40:26.373720 Set Vref, RX VrefLevel [Byte0]: 56
2765 12:40:26.377443 [Byte1]: 56
2766 12:40:26.381943
2767 12:40:26.382026 Set Vref, RX VrefLevel [Byte0]: 57
2768 12:40:26.385347 [Byte1]: 57
2769 12:40:26.389878
2770 12:40:26.389961 Set Vref, RX VrefLevel [Byte0]: 58
2771 12:40:26.392678 [Byte1]: 58
2772 12:40:26.397336
2773 12:40:26.397420 Set Vref, RX VrefLevel [Byte0]: 59
2774 12:40:26.400957 [Byte1]: 59
2775 12:40:26.405229
2776 12:40:26.405312 Set Vref, RX VrefLevel [Byte0]: 60
2777 12:40:26.408778 [Byte1]: 60
2778 12:40:26.414546
2779 12:40:26.414630 Set Vref, RX VrefLevel [Byte0]: 61
2780 12:40:26.416945 [Byte1]: 61
2781 12:40:26.421346
2782 12:40:26.424407 Set Vref, RX VrefLevel [Byte0]: 62
2783 12:40:26.427626 [Byte1]: 62
2784 12:40:26.427708
2785 12:40:26.431052 Set Vref, RX VrefLevel [Byte0]: 63
2786 12:40:26.434235 [Byte1]: 63
2787 12:40:26.434318
2788 12:40:26.437621 Set Vref, RX VrefLevel [Byte0]: 64
2789 12:40:26.441068 [Byte1]: 64
2790 12:40:26.445124
2791 12:40:26.445206 Set Vref, RX VrefLevel [Byte0]: 65
2792 12:40:26.448708 [Byte1]: 65
2793 12:40:26.453731
2794 12:40:26.453813 Set Vref, RX VrefLevel [Byte0]: 66
2795 12:40:26.456277 [Byte1]: 66
2796 12:40:26.460717
2797 12:40:26.460802 Set Vref, RX VrefLevel [Byte0]: 67
2798 12:40:26.464137 [Byte1]: 67
2799 12:40:26.468855
2800 12:40:26.468938 Final RX Vref Byte 0 = 52 to rank0
2801 12:40:26.471990 Final RX Vref Byte 1 = 49 to rank0
2802 12:40:26.475532 Final RX Vref Byte 0 = 52 to rank1
2803 12:40:26.478679 Final RX Vref Byte 1 = 49 to rank1==
2804 12:40:26.481884 Dram Type= 6, Freq= 0, CH_0, rank 0
2805 12:40:26.488629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2806 12:40:26.488755 ==
2807 12:40:26.488826 DQS Delay:
2808 12:40:26.491900 DQS0 = 0, DQS1 = 0
2809 12:40:26.491986 DQM Delay:
2810 12:40:26.492078 DQM0 = 117, DQM1 = 104
2811 12:40:26.495120 DQ Delay:
2812 12:40:26.498424 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2813 12:40:26.501688 DQ4 =120, DQ5 =110, DQ6 =124, DQ7 =122
2814 12:40:26.505125 DQ8 =92, DQ9 =88, DQ10 =104, DQ11 =100
2815 12:40:26.508517 DQ12 =112, DQ13 =108, DQ14 =116, DQ15 =112
2816 12:40:26.508628
2817 12:40:26.508722
2818 12:40:26.518520 [DQSOSCAuto] RK0, (LSB)MR18= 0x601, (MSB)MR19= 0x404, tDQSOscB0 = 409 ps tDQSOscB1 = 407 ps
2819 12:40:26.518618 CH0 RK0: MR19=404, MR18=601
2820 12:40:26.525052 CH0_RK0: MR19=0x404, MR18=0x601, DQSOSC=407, MR23=63, INC=39, DEC=26
2821 12:40:26.525142
2822 12:40:26.528941 ----->DramcWriteLeveling(PI) begin...
2823 12:40:26.529028 ==
2824 12:40:26.531961 Dram Type= 6, Freq= 0, CH_0, rank 1
2825 12:40:26.538003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2826 12:40:26.538105 ==
2827 12:40:26.541595 Write leveling (Byte 0): 31 => 31
2828 12:40:26.541682 Write leveling (Byte 1): 29 => 29
2829 12:40:26.544587 DramcWriteLeveling(PI) end<-----
2830 12:40:26.544670
2831 12:40:26.544736 ==
2832 12:40:26.548466 Dram Type= 6, Freq= 0, CH_0, rank 1
2833 12:40:26.554704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2834 12:40:26.554792 ==
2835 12:40:26.557970 [Gating] SW mode calibration
2836 12:40:26.565172 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2837 12:40:26.567939 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2838 12:40:26.574557 0 15 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
2839 12:40:26.577694 0 15 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
2840 12:40:26.581245 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 12:40:26.587954 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2842 12:40:26.591597 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2843 12:40:26.594547 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2844 12:40:26.601428 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2845 12:40:26.604522 0 15 28 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
2846 12:40:26.607914 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
2847 12:40:26.614410 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 12:40:26.618106 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 12:40:26.621397 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2850 12:40:26.624270 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 12:40:26.630925 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2852 12:40:26.634616 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2853 12:40:26.638843 1 0 28 | B1->B0 | 2626 4545 | 0 0 | (0 0) (0 0)
2854 12:40:26.644724 1 1 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
2855 12:40:26.647528 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 12:40:26.651528 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 12:40:26.658217 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 12:40:26.661121 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 12:40:26.664363 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 12:40:26.671087 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2861 12:40:26.674365 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2862 12:40:26.677757 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 12:40:26.685240 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 12:40:26.687493 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 12:40:26.690852 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 12:40:26.697742 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 12:40:26.700682 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 12:40:26.704299 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 12:40:26.710791 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 12:40:26.714296 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 12:40:26.717243 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 12:40:26.724131 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 12:40:26.727309 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 12:40:26.730667 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 12:40:26.737061 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 12:40:26.740562 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2877 12:40:26.744327 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2878 12:40:26.746870 Total UI for P1: 0, mck2ui 16
2879 12:40:26.750473 best dqsien dly found for B0: ( 1, 3, 24)
2880 12:40:26.756921 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2881 12:40:26.760460 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 12:40:26.763573 Total UI for P1: 0, mck2ui 16
2883 12:40:26.767173 best dqsien dly found for B1: ( 1, 3, 30)
2884 12:40:26.770043 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2885 12:40:26.773708 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2886 12:40:26.773793
2887 12:40:26.776598 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2888 12:40:26.780192 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2889 12:40:26.783350 [Gating] SW calibration Done
2890 12:40:26.783435 ==
2891 12:40:26.786896 Dram Type= 6, Freq= 0, CH_0, rank 1
2892 12:40:26.790270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2893 12:40:26.793873 ==
2894 12:40:26.793957 RX Vref Scan: 0
2895 12:40:26.794041
2896 12:40:26.796850 RX Vref 0 -> 0, step: 1
2897 12:40:26.796934
2898 12:40:26.797019 RX Delay -40 -> 252, step: 8
2899 12:40:26.803981 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2900 12:40:26.806937 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2901 12:40:26.810208 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2902 12:40:26.813596 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2903 12:40:26.816726 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2904 12:40:26.823433 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2905 12:40:26.826666 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2906 12:40:26.830099 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2907 12:40:26.833781 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2908 12:40:26.837013 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2909 12:40:26.843303 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2910 12:40:26.846886 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2911 12:40:26.850135 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2912 12:40:26.853550 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2913 12:40:26.856805 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2914 12:40:26.863441 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2915 12:40:26.863528 ==
2916 12:40:26.866407 Dram Type= 6, Freq= 0, CH_0, rank 1
2917 12:40:26.870098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2918 12:40:26.870184 ==
2919 12:40:26.870269 DQS Delay:
2920 12:40:26.873483 DQS0 = 0, DQS1 = 0
2921 12:40:26.873567 DQM Delay:
2922 12:40:26.876505 DQM0 = 116, DQM1 = 106
2923 12:40:26.876590 DQ Delay:
2924 12:40:26.879942 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =111
2925 12:40:26.883301 DQ4 =119, DQ5 =107, DQ6 =127, DQ7 =123
2926 12:40:26.886651 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2927 12:40:26.890301 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2928 12:40:26.890388
2929 12:40:26.893075
2930 12:40:26.893159 ==
2931 12:40:26.896302 Dram Type= 6, Freq= 0, CH_0, rank 1
2932 12:40:26.899642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2933 12:40:26.899727 ==
2934 12:40:26.899811
2935 12:40:26.899910
2936 12:40:26.903234 TX Vref Scan disable
2937 12:40:26.903319 == TX Byte 0 ==
2938 12:40:26.909963 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2939 12:40:26.913298 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2940 12:40:26.913383 == TX Byte 1 ==
2941 12:40:26.919371 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2942 12:40:26.923611 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2943 12:40:26.923697 ==
2944 12:40:26.926204 Dram Type= 6, Freq= 0, CH_0, rank 1
2945 12:40:26.929662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2946 12:40:26.929747 ==
2947 12:40:26.942524 TX Vref=22, minBit 10, minWin=25, winSum=423
2948 12:40:26.945822 TX Vref=24, minBit 1, minWin=26, winSum=430
2949 12:40:26.948681 TX Vref=26, minBit 5, minWin=26, winSum=431
2950 12:40:26.952326 TX Vref=28, minBit 13, minWin=26, winSum=438
2951 12:40:26.955427 TX Vref=30, minBit 13, minWin=26, winSum=438
2952 12:40:26.962254 TX Vref=32, minBit 5, minWin=26, winSum=435
2953 12:40:26.965348 [TxChooseVref] Worse bit 13, Min win 26, Win sum 438, Final Vref 28
2954 12:40:26.965435
2955 12:40:26.968667 Final TX Range 1 Vref 28
2956 12:40:26.968751
2957 12:40:26.968817 ==
2958 12:40:26.971939 Dram Type= 6, Freq= 0, CH_0, rank 1
2959 12:40:26.975916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2960 12:40:26.978872 ==
2961 12:40:26.978955
2962 12:40:26.979021
2963 12:40:26.979081 TX Vref Scan disable
2964 12:40:26.982217 == TX Byte 0 ==
2965 12:40:26.985840 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2966 12:40:26.989421 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2967 12:40:26.992133 == TX Byte 1 ==
2968 12:40:26.995616 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2969 12:40:27.002296 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2970 12:40:27.002388
2971 12:40:27.002454 [DATLAT]
2972 12:40:27.002515 Freq=1200, CH0 RK1
2973 12:40:27.002575
2974 12:40:27.005905 DATLAT Default: 0xd
2975 12:40:27.005989 0, 0xFFFF, sum = 0
2976 12:40:27.009180 1, 0xFFFF, sum = 0
2977 12:40:27.009265 2, 0xFFFF, sum = 0
2978 12:40:27.012471 3, 0xFFFF, sum = 0
2979 12:40:27.015282 4, 0xFFFF, sum = 0
2980 12:40:27.015367 5, 0xFFFF, sum = 0
2981 12:40:27.018925 6, 0xFFFF, sum = 0
2982 12:40:27.019011 7, 0xFFFF, sum = 0
2983 12:40:27.022056 8, 0xFFFF, sum = 0
2984 12:40:27.022141 9, 0xFFFF, sum = 0
2985 12:40:27.025594 10, 0xFFFF, sum = 0
2986 12:40:27.025679 11, 0xFFFF, sum = 0
2987 12:40:27.029031 12, 0x0, sum = 1
2988 12:40:27.029115 13, 0x0, sum = 2
2989 12:40:27.031982 14, 0x0, sum = 3
2990 12:40:27.032107 15, 0x0, sum = 4
2991 12:40:27.032176 best_step = 13
2992 12:40:27.035616
2993 12:40:27.035698 ==
2994 12:40:27.038585 Dram Type= 6, Freq= 0, CH_0, rank 1
2995 12:40:27.041995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2996 12:40:27.042079 ==
2997 12:40:27.042145 RX Vref Scan: 0
2998 12:40:27.042205
2999 12:40:27.045196 RX Vref 0 -> 0, step: 1
3000 12:40:27.045278
3001 12:40:27.048982 RX Delay -21 -> 252, step: 4
3002 12:40:27.051957 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3003 12:40:27.058730 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3004 12:40:27.061647 iDelay=195, Bit 2, Center 112 (47 ~ 178) 132
3005 12:40:27.065428 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3006 12:40:27.068392 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3007 12:40:27.071915 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
3008 12:40:27.078529 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3009 12:40:27.081973 iDelay=195, Bit 7, Center 120 (55 ~ 186) 132
3010 12:40:27.085415 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3011 12:40:27.088451 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3012 12:40:27.091761 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3013 12:40:27.098268 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3014 12:40:27.101729 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3015 12:40:27.104972 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3016 12:40:27.107984 iDelay=195, Bit 14, Center 118 (51 ~ 186) 136
3017 12:40:27.111693 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3018 12:40:27.114849 ==
3019 12:40:27.118049 Dram Type= 6, Freq= 0, CH_0, rank 1
3020 12:40:27.121685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3021 12:40:27.121775 ==
3022 12:40:27.121843 DQS Delay:
3023 12:40:27.124708 DQS0 = 0, DQS1 = 0
3024 12:40:27.124792 DQM Delay:
3025 12:40:27.128246 DQM0 = 115, DQM1 = 105
3026 12:40:27.128332 DQ Delay:
3027 12:40:27.131417 DQ0 =114, DQ1 =116, DQ2 =112, DQ3 =112
3028 12:40:27.135027 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =120
3029 12:40:27.138450 DQ8 =96, DQ9 =92, DQ10 =106, DQ11 =98
3030 12:40:27.141465 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =112
3031 12:40:27.141550
3032 12:40:27.141616
3033 12:40:27.151079 [DQSOSCAuto] RK1, (LSB)MR18= 0x2ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
3034 12:40:27.151168 CH0 RK1: MR19=403, MR18=2FF
3035 12:40:27.157985 CH0_RK1: MR19=0x403, MR18=0x2FF, DQSOSC=409, MR23=63, INC=39, DEC=26
3036 12:40:27.161531 [RxdqsGatingPostProcess] freq 1200
3037 12:40:27.167724 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3038 12:40:27.171051 best DQS0 dly(2T, 0.5T) = (0, 11)
3039 12:40:27.174702 best DQS1 dly(2T, 0.5T) = (0, 12)
3040 12:40:27.177462 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3041 12:40:27.181321 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3042 12:40:27.183984 best DQS0 dly(2T, 0.5T) = (0, 11)
3043 12:40:27.187507 best DQS1 dly(2T, 0.5T) = (0, 11)
3044 12:40:27.190846 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3045 12:40:27.194628 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3046 12:40:27.194714 Pre-setting of DQS Precalculation
3047 12:40:27.200527 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3048 12:40:27.200611 ==
3049 12:40:27.203970 Dram Type= 6, Freq= 0, CH_1, rank 0
3050 12:40:27.207183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3051 12:40:27.207266 ==
3052 12:40:27.213961 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3053 12:40:27.220445 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3054 12:40:27.228229 [CA 0] Center 38 (8~68) winsize 61
3055 12:40:27.231417 [CA 1] Center 37 (7~68) winsize 62
3056 12:40:27.235404 [CA 2] Center 35 (5~65) winsize 61
3057 12:40:27.238799 [CA 3] Center 34 (4~64) winsize 61
3058 12:40:27.241703 [CA 4] Center 34 (4~65) winsize 62
3059 12:40:27.244770 [CA 5] Center 33 (3~64) winsize 62
3060 12:40:27.244867
3061 12:40:27.248044 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3062 12:40:27.248127
3063 12:40:27.251518 [CATrainingPosCal] consider 1 rank data
3064 12:40:27.254585 u2DelayCellTimex100 = 270/100 ps
3065 12:40:27.258152 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3066 12:40:27.261180 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3067 12:40:27.267917 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3068 12:40:27.271452 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3069 12:40:27.274363 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3070 12:40:27.277746 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3071 12:40:27.277828
3072 12:40:27.281201 CA PerBit enable=1, Macro0, CA PI delay=33
3073 12:40:27.281310
3074 12:40:27.284696 [CBTSetCACLKResult] CA Dly = 33
3075 12:40:27.284783 CS Dly: 4 (0~35)
3076 12:40:27.287965 ==
3077 12:40:27.288076 Dram Type= 6, Freq= 0, CH_1, rank 1
3078 12:40:27.294512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3079 12:40:27.294596 ==
3080 12:40:27.297930 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3081 12:40:27.304501 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3082 12:40:27.313628 [CA 0] Center 37 (7~68) winsize 62
3083 12:40:27.317235 [CA 1] Center 38 (8~68) winsize 61
3084 12:40:27.320224 [CA 2] Center 35 (5~65) winsize 61
3085 12:40:27.324010 [CA 3] Center 33 (3~64) winsize 62
3086 12:40:27.327114 [CA 4] Center 34 (4~64) winsize 61
3087 12:40:27.330311 [CA 5] Center 33 (3~64) winsize 62
3088 12:40:27.330398
3089 12:40:27.333384 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3090 12:40:27.333473
3091 12:40:27.337227 [CATrainingPosCal] consider 2 rank data
3092 12:40:27.340189 u2DelayCellTimex100 = 270/100 ps
3093 12:40:27.344049 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3094 12:40:27.346723 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3095 12:40:27.354026 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3096 12:40:27.357118 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3097 12:40:27.360745 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3098 12:40:27.363532 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3099 12:40:27.363619
3100 12:40:27.367025 CA PerBit enable=1, Macro0, CA PI delay=33
3101 12:40:27.367141
3102 12:40:27.370372 [CBTSetCACLKResult] CA Dly = 33
3103 12:40:27.370458 CS Dly: 6 (0~39)
3104 12:40:27.373471
3105 12:40:27.376750 ----->DramcWriteLeveling(PI) begin...
3106 12:40:27.376837 ==
3107 12:40:27.380167 Dram Type= 6, Freq= 0, CH_1, rank 0
3108 12:40:27.383571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3109 12:40:27.383662 ==
3110 12:40:27.387218 Write leveling (Byte 0): 27 => 27
3111 12:40:27.390346 Write leveling (Byte 1): 28 => 28
3112 12:40:27.393404 DramcWriteLeveling(PI) end<-----
3113 12:40:27.393488
3114 12:40:27.393554 ==
3115 12:40:27.396665 Dram Type= 6, Freq= 0, CH_1, rank 0
3116 12:40:27.400169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3117 12:40:27.400256 ==
3118 12:40:27.403510 [Gating] SW mode calibration
3119 12:40:27.409667 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3120 12:40:27.416862 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3121 12:40:27.420280 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3122 12:40:27.423252 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3123 12:40:27.430062 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3124 12:40:27.433189 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3125 12:40:27.437043 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3126 12:40:27.443037 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3127 12:40:27.446879 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
3128 12:40:27.449420 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (1 0) (1 0)
3129 12:40:27.455958 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 12:40:27.459319 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 12:40:27.462568 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 12:40:27.469358 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 12:40:27.472411 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 12:40:27.475668 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3135 12:40:27.482575 1 0 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
3136 12:40:27.486165 1 0 28 | B1->B0 | 3d3d 4545 | 0 0 | (0 0) (0 0)
3137 12:40:27.489677 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 12:40:27.495784 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 12:40:27.499345 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 12:40:27.502249 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 12:40:27.509429 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 12:40:27.512453 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 12:40:27.515688 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3144 12:40:27.518967 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3145 12:40:27.525474 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 12:40:27.529316 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 12:40:27.532646 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 12:40:27.538893 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 12:40:27.542247 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 12:40:27.545504 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 12:40:27.552000 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 12:40:27.555186 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 12:40:27.558663 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 12:40:27.565321 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 12:40:27.569650 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 12:40:27.572725 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 12:40:27.578630 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 12:40:27.582462 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 12:40:27.585726 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 12:40:27.592659 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3161 12:40:27.595741 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 12:40:27.598540 Total UI for P1: 0, mck2ui 16
3163 12:40:27.601916 best dqsien dly found for B0: ( 1, 3, 28)
3164 12:40:27.605046 Total UI for P1: 0, mck2ui 16
3165 12:40:27.608535 best dqsien dly found for B1: ( 1, 3, 28)
3166 12:40:27.612139 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3167 12:40:27.615366 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3168 12:40:27.615448
3169 12:40:27.618334 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3170 12:40:27.621491 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3171 12:40:27.624870 [Gating] SW calibration Done
3172 12:40:27.624952 ==
3173 12:40:27.628553 Dram Type= 6, Freq= 0, CH_1, rank 0
3174 12:40:27.634960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3175 12:40:27.635042 ==
3176 12:40:27.635108 RX Vref Scan: 0
3177 12:40:27.635172
3178 12:40:27.638419 RX Vref 0 -> 0, step: 1
3179 12:40:27.638501
3180 12:40:27.641449 RX Delay -40 -> 252, step: 8
3181 12:40:27.644877 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3182 12:40:27.648265 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3183 12:40:27.651468 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3184 12:40:27.654658 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3185 12:40:27.661239 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3186 12:40:27.664767 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3187 12:40:27.667934 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3188 12:40:27.671342 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3189 12:40:27.675189 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3190 12:40:27.681336 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3191 12:40:27.684310 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3192 12:40:27.687555 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3193 12:40:27.691355 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3194 12:40:27.697506 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3195 12:40:27.700856 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3196 12:40:27.704649 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3197 12:40:27.704731 ==
3198 12:40:27.707751 Dram Type= 6, Freq= 0, CH_1, rank 0
3199 12:40:27.711813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3200 12:40:27.711895 ==
3201 12:40:27.714867 DQS Delay:
3202 12:40:27.714949 DQS0 = 0, DQS1 = 0
3203 12:40:27.717667 DQM Delay:
3204 12:40:27.717748 DQM0 = 116, DQM1 = 112
3205 12:40:27.717813 DQ Delay:
3206 12:40:27.724312 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =119
3207 12:40:27.727816 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3208 12:40:27.730850 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3209 12:40:27.734224 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3210 12:40:27.734304
3211 12:40:27.734369
3212 12:40:27.734429 ==
3213 12:40:27.737540 Dram Type= 6, Freq= 0, CH_1, rank 0
3214 12:40:27.740986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3215 12:40:27.741068 ==
3216 12:40:27.741133
3217 12:40:27.741192
3218 12:40:27.743974 TX Vref Scan disable
3219 12:40:27.747222 == TX Byte 0 ==
3220 12:40:27.750655 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3221 12:40:27.754169 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3222 12:40:27.756966 == TX Byte 1 ==
3223 12:40:27.760728 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3224 12:40:27.763943 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3225 12:40:27.764089 ==
3226 12:40:27.767092 Dram Type= 6, Freq= 0, CH_1, rank 0
3227 12:40:27.770464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3228 12:40:27.773972 ==
3229 12:40:27.783435 TX Vref=22, minBit 3, minWin=25, winSum=411
3230 12:40:27.787111 TX Vref=24, minBit 8, minWin=25, winSum=420
3231 12:40:27.790215 TX Vref=26, minBit 1, minWin=26, winSum=425
3232 12:40:27.793845 TX Vref=28, minBit 1, minWin=26, winSum=426
3233 12:40:27.797161 TX Vref=30, minBit 9, minWin=26, winSum=428
3234 12:40:27.803860 TX Vref=32, minBit 10, minWin=26, winSum=427
3235 12:40:27.807025 [TxChooseVref] Worse bit 9, Min win 26, Win sum 428, Final Vref 30
3236 12:40:27.807144
3237 12:40:27.810463 Final TX Range 1 Vref 30
3238 12:40:27.810575
3239 12:40:27.810647 ==
3240 12:40:27.813934 Dram Type= 6, Freq= 0, CH_1, rank 0
3241 12:40:27.816982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3242 12:40:27.820169 ==
3243 12:40:27.820257
3244 12:40:27.820323
3245 12:40:27.820387 TX Vref Scan disable
3246 12:40:27.823401 == TX Byte 0 ==
3247 12:40:27.826841 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3248 12:40:27.833361 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3249 12:40:27.833442 == TX Byte 1 ==
3250 12:40:27.836671 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3251 12:40:27.843318 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3252 12:40:27.843403
3253 12:40:27.843469 [DATLAT]
3254 12:40:27.843530 Freq=1200, CH1 RK0
3255 12:40:27.843591
3256 12:40:27.846539 DATLAT Default: 0xd
3257 12:40:27.846625 0, 0xFFFF, sum = 0
3258 12:40:27.850097 1, 0xFFFF, sum = 0
3259 12:40:27.853351 2, 0xFFFF, sum = 0
3260 12:40:27.853436 3, 0xFFFF, sum = 0
3261 12:40:27.856635 4, 0xFFFF, sum = 0
3262 12:40:27.856723 5, 0xFFFF, sum = 0
3263 12:40:27.860165 6, 0xFFFF, sum = 0
3264 12:40:27.860249 7, 0xFFFF, sum = 0
3265 12:40:27.863185 8, 0xFFFF, sum = 0
3266 12:40:27.863269 9, 0xFFFF, sum = 0
3267 12:40:27.866453 10, 0xFFFF, sum = 0
3268 12:40:27.866538 11, 0xFFFF, sum = 0
3269 12:40:27.869942 12, 0x0, sum = 1
3270 12:40:27.870026 13, 0x0, sum = 2
3271 12:40:27.873069 14, 0x0, sum = 3
3272 12:40:27.873153 15, 0x0, sum = 4
3273 12:40:27.876476 best_step = 13
3274 12:40:27.876558
3275 12:40:27.876623 ==
3276 12:40:27.879487 Dram Type= 6, Freq= 0, CH_1, rank 0
3277 12:40:27.883328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3278 12:40:27.883412 ==
3279 12:40:27.883478 RX Vref Scan: 1
3280 12:40:27.883539
3281 12:40:27.886528 Set Vref Range= 32 -> 127
3282 12:40:27.886611
3283 12:40:27.889580 RX Vref 32 -> 127, step: 1
3284 12:40:27.889680
3285 12:40:27.893555 RX Delay -13 -> 252, step: 4
3286 12:40:27.893638
3287 12:40:27.896208 Set Vref, RX VrefLevel [Byte0]: 32
3288 12:40:27.899838 [Byte1]: 32
3289 12:40:27.899921
3290 12:40:27.903114 Set Vref, RX VrefLevel [Byte0]: 33
3291 12:40:27.906460 [Byte1]: 33
3292 12:40:27.910519
3293 12:40:27.910602 Set Vref, RX VrefLevel [Byte0]: 34
3294 12:40:27.913129 [Byte1]: 34
3295 12:40:27.918098
3296 12:40:27.918182 Set Vref, RX VrefLevel [Byte0]: 35
3297 12:40:27.920966 [Byte1]: 35
3298 12:40:27.925448
3299 12:40:27.925531 Set Vref, RX VrefLevel [Byte0]: 36
3300 12:40:27.928830 [Byte1]: 36
3301 12:40:27.933741
3302 12:40:27.933824 Set Vref, RX VrefLevel [Byte0]: 37
3303 12:40:27.936608 [Byte1]: 37
3304 12:40:27.941226
3305 12:40:27.941309 Set Vref, RX VrefLevel [Byte0]: 38
3306 12:40:27.944959 [Byte1]: 38
3307 12:40:27.949715
3308 12:40:27.949798 Set Vref, RX VrefLevel [Byte0]: 39
3309 12:40:27.953076 [Byte1]: 39
3310 12:40:27.957131
3311 12:40:27.957216 Set Vref, RX VrefLevel [Byte0]: 40
3312 12:40:27.960160 [Byte1]: 40
3313 12:40:27.964880
3314 12:40:27.964961 Set Vref, RX VrefLevel [Byte0]: 41
3315 12:40:27.968131 [Byte1]: 41
3316 12:40:27.972828
3317 12:40:27.972909 Set Vref, RX VrefLevel [Byte0]: 42
3318 12:40:27.976493 [Byte1]: 42
3319 12:40:27.980849
3320 12:40:27.980929 Set Vref, RX VrefLevel [Byte0]: 43
3321 12:40:27.983935 [Byte1]: 43
3322 12:40:27.988824
3323 12:40:27.988905 Set Vref, RX VrefLevel [Byte0]: 44
3324 12:40:27.992139 [Byte1]: 44
3325 12:40:27.996447
3326 12:40:27.996527 Set Vref, RX VrefLevel [Byte0]: 45
3327 12:40:27.999435 [Byte1]: 45
3328 12:40:28.004451
3329 12:40:28.004532 Set Vref, RX VrefLevel [Byte0]: 46
3330 12:40:28.007950 [Byte1]: 46
3331 12:40:28.012263
3332 12:40:28.012343 Set Vref, RX VrefLevel [Byte0]: 47
3333 12:40:28.015370 [Byte1]: 47
3334 12:40:28.019970
3335 12:40:28.020090 Set Vref, RX VrefLevel [Byte0]: 48
3336 12:40:28.024187 [Byte1]: 48
3337 12:40:28.028412
3338 12:40:28.028492 Set Vref, RX VrefLevel [Byte0]: 49
3339 12:40:28.031783 [Byte1]: 49
3340 12:40:28.036039
3341 12:40:28.036135 Set Vref, RX VrefLevel [Byte0]: 50
3342 12:40:28.039913 [Byte1]: 50
3343 12:40:28.043905
3344 12:40:28.044012 Set Vref, RX VrefLevel [Byte0]: 51
3345 12:40:28.046982 [Byte1]: 51
3346 12:40:28.051879
3347 12:40:28.051986 Set Vref, RX VrefLevel [Byte0]: 52
3348 12:40:28.055182 [Byte1]: 52
3349 12:40:28.059315
3350 12:40:28.059395 Set Vref, RX VrefLevel [Byte0]: 53
3351 12:40:28.063506 [Byte1]: 53
3352 12:40:28.067962
3353 12:40:28.068097 Set Vref, RX VrefLevel [Byte0]: 54
3354 12:40:28.070840 [Byte1]: 54
3355 12:40:28.075322
3356 12:40:28.075403 Set Vref, RX VrefLevel [Byte0]: 55
3357 12:40:28.078524 [Byte1]: 55
3358 12:40:28.083393
3359 12:40:28.083474 Set Vref, RX VrefLevel [Byte0]: 56
3360 12:40:28.086862 [Byte1]: 56
3361 12:40:28.090945
3362 12:40:28.091026 Set Vref, RX VrefLevel [Byte0]: 57
3363 12:40:28.094691 [Byte1]: 57
3364 12:40:28.098717
3365 12:40:28.102465 Set Vref, RX VrefLevel [Byte0]: 58
3366 12:40:28.102548 [Byte1]: 58
3367 12:40:28.106820
3368 12:40:28.106901 Set Vref, RX VrefLevel [Byte0]: 59
3369 12:40:28.109983 [Byte1]: 59
3370 12:40:28.114549
3371 12:40:28.114631 Set Vref, RX VrefLevel [Byte0]: 60
3372 12:40:28.118307 [Byte1]: 60
3373 12:40:28.122856
3374 12:40:28.122937 Set Vref, RX VrefLevel [Byte0]: 61
3375 12:40:28.126073 [Byte1]: 61
3376 12:40:28.130426
3377 12:40:28.130507 Set Vref, RX VrefLevel [Byte0]: 62
3378 12:40:28.133569 [Byte1]: 62
3379 12:40:28.138266
3380 12:40:28.138346 Set Vref, RX VrefLevel [Byte0]: 63
3381 12:40:28.141650 [Byte1]: 63
3382 12:40:28.146237
3383 12:40:28.146320 Set Vref, RX VrefLevel [Byte0]: 64
3384 12:40:28.150017 [Byte1]: 64
3385 12:40:28.156465
3386 12:40:28.156591 Set Vref, RX VrefLevel [Byte0]: 65
3387 12:40:28.157597 [Byte1]: 65
3388 12:40:28.162000
3389 12:40:28.162083 Set Vref, RX VrefLevel [Byte0]: 66
3390 12:40:28.165383 [Byte1]: 66
3391 12:40:28.170090
3392 12:40:28.170172 Final RX Vref Byte 0 = 51 to rank0
3393 12:40:28.173002 Final RX Vref Byte 1 = 50 to rank0
3394 12:40:28.176591 Final RX Vref Byte 0 = 51 to rank1
3395 12:40:28.179930 Final RX Vref Byte 1 = 50 to rank1==
3396 12:40:28.183491 Dram Type= 6, Freq= 0, CH_1, rank 0
3397 12:40:28.189557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3398 12:40:28.189640 ==
3399 12:40:28.189705 DQS Delay:
3400 12:40:28.192820 DQS0 = 0, DQS1 = 0
3401 12:40:28.192902 DQM Delay:
3402 12:40:28.192967 DQM0 = 115, DQM1 = 112
3403 12:40:28.196142 DQ Delay:
3404 12:40:28.199709 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =116
3405 12:40:28.202789 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3406 12:40:28.206432 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
3407 12:40:28.209400 DQ12 =120, DQ13 =120, DQ14 =118, DQ15 =120
3408 12:40:28.209481
3409 12:40:28.209546
3410 12:40:28.219289 [DQSOSCAuto] RK0, (LSB)MR18= 0xf1fd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 416 ps
3411 12:40:28.219379 CH1 RK0: MR19=303, MR18=F1FD
3412 12:40:28.226232 CH1_RK0: MR19=0x303, MR18=0xF1FD, DQSOSC=411, MR23=63, INC=38, DEC=25
3413 12:40:28.226318
3414 12:40:28.229660 ----->DramcWriteLeveling(PI) begin...
3415 12:40:28.229745 ==
3416 12:40:28.232837 Dram Type= 6, Freq= 0, CH_1, rank 1
3417 12:40:28.239330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3418 12:40:28.239415 ==
3419 12:40:28.242655 Write leveling (Byte 0): 25 => 25
3420 12:40:28.245800 Write leveling (Byte 1): 29 => 29
3421 12:40:28.245884 DramcWriteLeveling(PI) end<-----
3422 12:40:28.249304
3423 12:40:28.249387 ==
3424 12:40:28.252586 Dram Type= 6, Freq= 0, CH_1, rank 1
3425 12:40:28.255647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3426 12:40:28.255780 ==
3427 12:40:28.259075 [Gating] SW mode calibration
3428 12:40:28.265790 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3429 12:40:28.268971 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3430 12:40:28.275677 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
3431 12:40:28.278632 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3432 12:40:28.282282 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3433 12:40:28.288815 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3434 12:40:28.292232 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3435 12:40:28.295277 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3436 12:40:28.302480 0 15 24 | B1->B0 | 3434 2626 | 1 0 | (1 0) (1 0)
3437 12:40:28.305637 0 15 28 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
3438 12:40:28.308771 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3439 12:40:28.315221 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3440 12:40:28.318982 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3441 12:40:28.322145 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3442 12:40:28.328684 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3443 12:40:28.332638 1 0 20 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
3444 12:40:28.335587 1 0 24 | B1->B0 | 2424 4545 | 1 0 | (0 0) (0 0)
3445 12:40:28.342676 1 0 28 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
3446 12:40:28.345369 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3447 12:40:28.348588 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3448 12:40:28.355137 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3449 12:40:28.358353 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3450 12:40:28.361699 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3451 12:40:28.368575 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3452 12:40:28.372288 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3453 12:40:28.375045 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3454 12:40:28.381745 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3455 12:40:28.384890 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 12:40:28.388353 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 12:40:28.395054 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 12:40:28.398091 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 12:40:28.401870 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 12:40:28.407751 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 12:40:28.411161 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 12:40:28.414301 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 12:40:28.421642 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 12:40:28.424649 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 12:40:28.427649 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 12:40:28.434116 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 12:40:28.437569 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3468 12:40:28.441136 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3469 12:40:28.447665 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3470 12:40:28.447754 Total UI for P1: 0, mck2ui 16
3471 12:40:28.454091 best dqsien dly found for B0: ( 1, 3, 22)
3472 12:40:28.457477 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 12:40:28.460929 Total UI for P1: 0, mck2ui 16
3474 12:40:28.463724 best dqsien dly found for B1: ( 1, 3, 28)
3475 12:40:28.467793 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3476 12:40:28.470988 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3477 12:40:28.471074
3478 12:40:28.473869 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3479 12:40:28.477624 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3480 12:40:28.481091 [Gating] SW calibration Done
3481 12:40:28.481201 ==
3482 12:40:28.483893 Dram Type= 6, Freq= 0, CH_1, rank 1
3483 12:40:28.487019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3484 12:40:28.490345 ==
3485 12:40:28.490452 RX Vref Scan: 0
3486 12:40:28.490521
3487 12:40:28.493722 RX Vref 0 -> 0, step: 1
3488 12:40:28.493806
3489 12:40:28.496956 RX Delay -40 -> 252, step: 8
3490 12:40:28.500060 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3491 12:40:28.503899 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3492 12:40:28.507115 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3493 12:40:28.510361 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3494 12:40:28.516833 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3495 12:40:28.519935 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3496 12:40:28.523157 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3497 12:40:28.526216 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3498 12:40:28.529914 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3499 12:40:28.535939 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3500 12:40:28.539844 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3501 12:40:28.543381 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3502 12:40:28.545809 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3503 12:40:28.552718 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3504 12:40:28.555784 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3505 12:40:28.559064 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3506 12:40:28.559149 ==
3507 12:40:28.562387 Dram Type= 6, Freq= 0, CH_1, rank 1
3508 12:40:28.566293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3509 12:40:28.566378 ==
3510 12:40:28.568909 DQS Delay:
3511 12:40:28.568993 DQS0 = 0, DQS1 = 0
3512 12:40:28.572445 DQM Delay:
3513 12:40:28.572530 DQM0 = 115, DQM1 = 111
3514 12:40:28.576219 DQ Delay:
3515 12:40:28.579265 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3516 12:40:28.582621 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3517 12:40:28.585424 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3518 12:40:28.588941 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3519 12:40:28.589025
3520 12:40:28.589092
3521 12:40:28.589153 ==
3522 12:40:28.592325 Dram Type= 6, Freq= 0, CH_1, rank 1
3523 12:40:28.595636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3524 12:40:28.595719 ==
3525 12:40:28.595785
3526 12:40:28.595846
3527 12:40:28.599138 TX Vref Scan disable
3528 12:40:28.602739 == TX Byte 0 ==
3529 12:40:28.605111 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3530 12:40:28.608507 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3531 12:40:28.611981 == TX Byte 1 ==
3532 12:40:28.615298 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3533 12:40:28.618807 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3534 12:40:28.618890 ==
3535 12:40:28.621957 Dram Type= 6, Freq= 0, CH_1, rank 1
3536 12:40:28.628146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3537 12:40:28.628235 ==
3538 12:40:28.638837 TX Vref=22, minBit 1, minWin=26, winSum=426
3539 12:40:28.642279 TX Vref=24, minBit 1, minWin=26, winSum=428
3540 12:40:28.645556 TX Vref=26, minBit 1, minWin=26, winSum=430
3541 12:40:28.649095 TX Vref=28, minBit 1, minWin=26, winSum=431
3542 12:40:28.652875 TX Vref=30, minBit 1, minWin=26, winSum=434
3543 12:40:28.658875 TX Vref=32, minBit 1, minWin=26, winSum=432
3544 12:40:28.662120 [TxChooseVref] Worse bit 1, Min win 26, Win sum 434, Final Vref 30
3545 12:40:28.662206
3546 12:40:28.665481 Final TX Range 1 Vref 30
3547 12:40:28.665565
3548 12:40:28.665630 ==
3549 12:40:28.669746 Dram Type= 6, Freq= 0, CH_1, rank 1
3550 12:40:28.672516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3551 12:40:28.672629 ==
3552 12:40:28.675418
3553 12:40:28.675531
3554 12:40:28.675597 TX Vref Scan disable
3555 12:40:28.679155 == TX Byte 0 ==
3556 12:40:28.682369 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3557 12:40:28.689088 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3558 12:40:28.689170 == TX Byte 1 ==
3559 12:40:28.691775 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3560 12:40:28.698362 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3561 12:40:28.698445
3562 12:40:28.698510 [DATLAT]
3563 12:40:28.698572 Freq=1200, CH1 RK1
3564 12:40:28.698631
3565 12:40:28.702159 DATLAT Default: 0xd
3566 12:40:28.705143 0, 0xFFFF, sum = 0
3567 12:40:28.705226 1, 0xFFFF, sum = 0
3568 12:40:28.708407 2, 0xFFFF, sum = 0
3569 12:40:28.708491 3, 0xFFFF, sum = 0
3570 12:40:28.711853 4, 0xFFFF, sum = 0
3571 12:40:28.711963 5, 0xFFFF, sum = 0
3572 12:40:28.715227 6, 0xFFFF, sum = 0
3573 12:40:28.715311 7, 0xFFFF, sum = 0
3574 12:40:28.718040 8, 0xFFFF, sum = 0
3575 12:40:28.718124 9, 0xFFFF, sum = 0
3576 12:40:28.721395 10, 0xFFFF, sum = 0
3577 12:40:28.721479 11, 0xFFFF, sum = 0
3578 12:40:28.725179 12, 0x0, sum = 1
3579 12:40:28.725263 13, 0x0, sum = 2
3580 12:40:28.727806 14, 0x0, sum = 3
3581 12:40:28.727890 15, 0x0, sum = 4
3582 12:40:28.731034 best_step = 13
3583 12:40:28.731116
3584 12:40:28.731182 ==
3585 12:40:28.734381 Dram Type= 6, Freq= 0, CH_1, rank 1
3586 12:40:28.737928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3587 12:40:28.738012 ==
3588 12:40:28.740933 RX Vref Scan: 0
3589 12:40:28.741025
3590 12:40:28.741090 RX Vref 0 -> 0, step: 1
3591 12:40:28.741152
3592 12:40:28.744213 RX Delay -13 -> 252, step: 4
3593 12:40:28.751135 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3594 12:40:28.754286 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3595 12:40:28.757655 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3596 12:40:28.761491 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3597 12:40:28.764023 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3598 12:40:28.770725 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3599 12:40:28.774580 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3600 12:40:28.777430 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3601 12:40:28.780643 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3602 12:40:28.787103 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3603 12:40:28.790397 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3604 12:40:28.793658 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3605 12:40:28.797148 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3606 12:40:28.800793 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3607 12:40:28.807346 iDelay=195, Bit 14, Center 118 (59 ~ 178) 120
3608 12:40:28.810235 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3609 12:40:28.810318 ==
3610 12:40:28.813723 Dram Type= 6, Freq= 0, CH_1, rank 1
3611 12:40:28.816732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3612 12:40:28.816814 ==
3613 12:40:28.819951 DQS Delay:
3614 12:40:28.820052 DQS0 = 0, DQS1 = 0
3615 12:40:28.823263 DQM Delay:
3616 12:40:28.823345 DQM0 = 114, DQM1 = 112
3617 12:40:28.823410 DQ Delay:
3618 12:40:28.827115 DQ0 =116, DQ1 =112, DQ2 =106, DQ3 =114
3619 12:40:28.833430 DQ4 =112, DQ5 =124, DQ6 =122, DQ7 =112
3620 12:40:28.837020 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3621 12:40:28.840325 DQ12 =120, DQ13 =118, DQ14 =118, DQ15 =122
3622 12:40:28.840406
3623 12:40:28.840471
3624 12:40:28.846728 [DQSOSCAuto] RK1, (LSB)MR18= 0xf90b, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
3625 12:40:28.850099 CH1 RK1: MR19=304, MR18=F90B
3626 12:40:28.856242 CH1_RK1: MR19=0x304, MR18=0xF90B, DQSOSC=405, MR23=63, INC=39, DEC=26
3627 12:40:28.859608 [RxdqsGatingPostProcess] freq 1200
3628 12:40:28.866095 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3629 12:40:28.869396 best DQS0 dly(2T, 0.5T) = (0, 11)
3630 12:40:28.869481 best DQS1 dly(2T, 0.5T) = (0, 11)
3631 12:40:28.873416 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3632 12:40:28.876541 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3633 12:40:28.879446 best DQS0 dly(2T, 0.5T) = (0, 11)
3634 12:40:28.882905 best DQS1 dly(2T, 0.5T) = (0, 11)
3635 12:40:28.886620 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3636 12:40:28.889239 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3637 12:40:28.892640 Pre-setting of DQS Precalculation
3638 12:40:28.899560 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3639 12:40:28.905632 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3640 12:40:28.912362 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3641 12:40:28.912499
3642 12:40:28.912569
3643 12:40:28.915741 [Calibration Summary] 2400 Mbps
3644 12:40:28.915828 CH 0, Rank 0
3645 12:40:28.918954 SW Impedance : PASS
3646 12:40:28.922728 DUTY Scan : NO K
3647 12:40:28.922812 ZQ Calibration : PASS
3648 12:40:28.925481 Jitter Meter : NO K
3649 12:40:28.929501 CBT Training : PASS
3650 12:40:28.929585 Write leveling : PASS
3651 12:40:28.932379 RX DQS gating : PASS
3652 12:40:28.935564 RX DQ/DQS(RDDQC) : PASS
3653 12:40:28.935647 TX DQ/DQS : PASS
3654 12:40:28.938915 RX DATLAT : PASS
3655 12:40:28.941897 RX DQ/DQS(Engine): PASS
3656 12:40:28.941980 TX OE : NO K
3657 12:40:28.945542 All Pass.
3658 12:40:28.945625
3659 12:40:28.945691 CH 0, Rank 1
3660 12:40:28.948737 SW Impedance : PASS
3661 12:40:28.948820 DUTY Scan : NO K
3662 12:40:28.951926 ZQ Calibration : PASS
3663 12:40:28.955374 Jitter Meter : NO K
3664 12:40:28.955460 CBT Training : PASS
3665 12:40:28.958634 Write leveling : PASS
3666 12:40:28.961630 RX DQS gating : PASS
3667 12:40:28.961720 RX DQ/DQS(RDDQC) : PASS
3668 12:40:28.965012 TX DQ/DQS : PASS
3669 12:40:28.968049 RX DATLAT : PASS
3670 12:40:28.968147 RX DQ/DQS(Engine): PASS
3671 12:40:28.971718 TX OE : NO K
3672 12:40:28.971805 All Pass.
3673 12:40:28.971872
3674 12:40:28.975675 CH 1, Rank 0
3675 12:40:28.975759 SW Impedance : PASS
3676 12:40:28.978098 DUTY Scan : NO K
3677 12:40:28.981382 ZQ Calibration : PASS
3678 12:40:28.981467 Jitter Meter : NO K
3679 12:40:28.985259 CBT Training : PASS
3680 12:40:28.985359 Write leveling : PASS
3681 12:40:28.988357 RX DQS gating : PASS
3682 12:40:28.991250 RX DQ/DQS(RDDQC) : PASS
3683 12:40:28.991365 TX DQ/DQS : PASS
3684 12:40:28.994864 RX DATLAT : PASS
3685 12:40:28.998099 RX DQ/DQS(Engine): PASS
3686 12:40:28.998183 TX OE : NO K
3687 12:40:29.001320 All Pass.
3688 12:40:29.001403
3689 12:40:29.001468 CH 1, Rank 1
3690 12:40:29.004785 SW Impedance : PASS
3691 12:40:29.004867 DUTY Scan : NO K
3692 12:40:29.008290 ZQ Calibration : PASS
3693 12:40:29.011188 Jitter Meter : NO K
3694 12:40:29.011273 CBT Training : PASS
3695 12:40:29.014370 Write leveling : PASS
3696 12:40:29.017443 RX DQS gating : PASS
3697 12:40:29.017530 RX DQ/DQS(RDDQC) : PASS
3698 12:40:29.021031 TX DQ/DQS : PASS
3699 12:40:29.024363 RX DATLAT : PASS
3700 12:40:29.024447 RX DQ/DQS(Engine): PASS
3701 12:40:29.027629 TX OE : NO K
3702 12:40:29.027712 All Pass.
3703 12:40:29.027779
3704 12:40:29.030894 DramC Write-DBI off
3705 12:40:29.033812 PER_BANK_REFRESH: Hybrid Mode
3706 12:40:29.033896 TX_TRACKING: ON
3707 12:40:29.043701 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3708 12:40:29.047362 [FAST_K] Save calibration result to emmc
3709 12:40:29.050396 dramc_set_vcore_voltage set vcore to 650000
3710 12:40:29.053831 Read voltage for 600, 5
3711 12:40:29.053917 Vio18 = 0
3712 12:40:29.053984 Vcore = 650000
3713 12:40:29.057413 Vdram = 0
3714 12:40:29.057499 Vddq = 0
3715 12:40:29.057566 Vmddr = 0
3716 12:40:29.064007 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3717 12:40:29.067032 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3718 12:40:29.070150 MEM_TYPE=3, freq_sel=19
3719 12:40:29.074028 sv_algorithm_assistance_LP4_1600
3720 12:40:29.076813 ============ PULL DRAM RESETB DOWN ============
3721 12:40:29.084043 ========== PULL DRAM RESETB DOWN end =========
3722 12:40:29.087112 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3723 12:40:29.089996 ===================================
3724 12:40:29.093812 LPDDR4 DRAM CONFIGURATION
3725 12:40:29.096631 ===================================
3726 12:40:29.096719 EX_ROW_EN[0] = 0x0
3727 12:40:29.100334 EX_ROW_EN[1] = 0x0
3728 12:40:29.100420 LP4Y_EN = 0x0
3729 12:40:29.103956 WORK_FSP = 0x0
3730 12:40:29.104067 WL = 0x2
3731 12:40:29.106535 RL = 0x2
3732 12:40:29.106618 BL = 0x2
3733 12:40:29.110085 RPST = 0x0
3734 12:40:29.110168 RD_PRE = 0x0
3735 12:40:29.113756 WR_PRE = 0x1
3736 12:40:29.116549 WR_PST = 0x0
3737 12:40:29.116634 DBI_WR = 0x0
3738 12:40:29.119732 DBI_RD = 0x0
3739 12:40:29.119815 OTF = 0x1
3740 12:40:29.122783 ===================================
3741 12:40:29.126461 ===================================
3742 12:40:29.129788 ANA top config
3743 12:40:29.133115 ===================================
3744 12:40:29.133200 DLL_ASYNC_EN = 0
3745 12:40:29.136354 ALL_SLAVE_EN = 1
3746 12:40:29.139368 NEW_RANK_MODE = 1
3747 12:40:29.142795 DLL_IDLE_MODE = 1
3748 12:40:29.142883 LP45_APHY_COMB_EN = 1
3749 12:40:29.146396 TX_ODT_DIS = 1
3750 12:40:29.149196 NEW_8X_MODE = 1
3751 12:40:29.152811 ===================================
3752 12:40:29.155967 ===================================
3753 12:40:29.159857 data_rate = 1200
3754 12:40:29.162519 CKR = 1
3755 12:40:29.166049 DQ_P2S_RATIO = 8
3756 12:40:29.169469 ===================================
3757 12:40:29.169560 CA_P2S_RATIO = 8
3758 12:40:29.172336 DQ_CA_OPEN = 0
3759 12:40:29.175571 DQ_SEMI_OPEN = 0
3760 12:40:29.179058 CA_SEMI_OPEN = 0
3761 12:40:29.182710 CA_FULL_RATE = 0
3762 12:40:29.185566 DQ_CKDIV4_EN = 1
3763 12:40:29.185707 CA_CKDIV4_EN = 1
3764 12:40:29.188801 CA_PREDIV_EN = 0
3765 12:40:29.192480 PH8_DLY = 0
3766 12:40:29.195525 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3767 12:40:29.198771 DQ_AAMCK_DIV = 4
3768 12:40:29.202378 CA_AAMCK_DIV = 4
3769 12:40:29.202469 CA_ADMCK_DIV = 4
3770 12:40:29.205357 DQ_TRACK_CA_EN = 0
3771 12:40:29.209005 CA_PICK = 600
3772 12:40:29.211933 CA_MCKIO = 600
3773 12:40:29.215490 MCKIO_SEMI = 0
3774 12:40:29.218687 PLL_FREQ = 2288
3775 12:40:29.222310 DQ_UI_PI_RATIO = 32
3776 12:40:29.225093 CA_UI_PI_RATIO = 0
3777 12:40:29.228184 ===================================
3778 12:40:29.231745 ===================================
3779 12:40:29.231830 memory_type:LPDDR4
3780 12:40:29.235089 GP_NUM : 10
3781 12:40:29.238515 SRAM_EN : 1
3782 12:40:29.238600 MD32_EN : 0
3783 12:40:29.241601 ===================================
3784 12:40:29.245236 [ANA_INIT] >>>>>>>>>>>>>>
3785 12:40:29.248028 <<<<<< [CONFIGURE PHASE]: ANA_TX
3786 12:40:29.251826 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3787 12:40:29.254783 ===================================
3788 12:40:29.258198 data_rate = 1200,PCW = 0X5800
3789 12:40:29.261651 ===================================
3790 12:40:29.264810 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3791 12:40:29.268177 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3792 12:40:29.274653 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3793 12:40:29.278215 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3794 12:40:29.281101 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3795 12:40:29.284678 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3796 12:40:29.287572 [ANA_INIT] flow start
3797 12:40:29.291057 [ANA_INIT] PLL >>>>>>>>
3798 12:40:29.291148 [ANA_INIT] PLL <<<<<<<<
3799 12:40:29.294495 [ANA_INIT] MIDPI >>>>>>>>
3800 12:40:29.297505 [ANA_INIT] MIDPI <<<<<<<<
3801 12:40:29.301106 [ANA_INIT] DLL >>>>>>>>
3802 12:40:29.301196 [ANA_INIT] flow end
3803 12:40:29.304217 ============ LP4 DIFF to SE enter ============
3804 12:40:29.310895 ============ LP4 DIFF to SE exit ============
3805 12:40:29.310998 [ANA_INIT] <<<<<<<<<<<<<
3806 12:40:29.314248 [Flow] Enable top DCM control >>>>>
3807 12:40:29.317580 [Flow] Enable top DCM control <<<<<
3808 12:40:29.320566 Enable DLL master slave shuffle
3809 12:40:29.327369 ==============================================================
3810 12:40:29.327467 Gating Mode config
3811 12:40:29.334098 ==============================================================
3812 12:40:29.337175 Config description:
3813 12:40:29.346750 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3814 12:40:29.353696 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3815 12:40:29.357100 SELPH_MODE 0: By rank 1: By Phase
3816 12:40:29.363467 ==============================================================
3817 12:40:29.367143 GAT_TRACK_EN = 1
3818 12:40:29.369938 RX_GATING_MODE = 2
3819 12:40:29.373590 RX_GATING_TRACK_MODE = 2
3820 12:40:29.373684 SELPH_MODE = 1
3821 12:40:29.376612 PICG_EARLY_EN = 1
3822 12:40:29.380025 VALID_LAT_VALUE = 1
3823 12:40:29.386644 ==============================================================
3824 12:40:29.390258 Enter into Gating configuration >>>>
3825 12:40:29.393220 Exit from Gating configuration <<<<
3826 12:40:29.396626 Enter into DVFS_PRE_config >>>>>
3827 12:40:29.406108 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3828 12:40:29.409567 Exit from DVFS_PRE_config <<<<<
3829 12:40:29.412976 Enter into PICG configuration >>>>
3830 12:40:29.416103 Exit from PICG configuration <<<<
3831 12:40:29.419423 [RX_INPUT] configuration >>>>>
3832 12:40:29.423107 [RX_INPUT] configuration <<<<<
3833 12:40:29.426112 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3834 12:40:29.432767 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3835 12:40:29.439355 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3836 12:40:29.446171 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3837 12:40:29.452354 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3838 12:40:29.458853 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3839 12:40:29.462334 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3840 12:40:29.465906 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3841 12:40:29.468993 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3842 12:40:29.475538 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3843 12:40:29.479464 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3844 12:40:29.482307 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3845 12:40:29.485326 ===================================
3846 12:40:29.488440 LPDDR4 DRAM CONFIGURATION
3847 12:40:29.491908 ===================================
3848 12:40:29.492040 EX_ROW_EN[0] = 0x0
3849 12:40:29.495476 EX_ROW_EN[1] = 0x0
3850 12:40:29.498671 LP4Y_EN = 0x0
3851 12:40:29.498764 WORK_FSP = 0x0
3852 12:40:29.502317 WL = 0x2
3853 12:40:29.502410 RL = 0x2
3854 12:40:29.505241 BL = 0x2
3855 12:40:29.505343 RPST = 0x0
3856 12:40:29.509008 RD_PRE = 0x0
3857 12:40:29.509105 WR_PRE = 0x1
3858 12:40:29.511955 WR_PST = 0x0
3859 12:40:29.512065 DBI_WR = 0x0
3860 12:40:29.514928 DBI_RD = 0x0
3861 12:40:29.515015 OTF = 0x1
3862 12:40:29.518028 ===================================
3863 12:40:29.521539 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3864 12:40:29.528261 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3865 12:40:29.531475 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3866 12:40:29.534668 ===================================
3867 12:40:29.538807 LPDDR4 DRAM CONFIGURATION
3868 12:40:29.541372 ===================================
3869 12:40:29.541463 EX_ROW_EN[0] = 0x10
3870 12:40:29.544797 EX_ROW_EN[1] = 0x0
3871 12:40:29.548638 LP4Y_EN = 0x0
3872 12:40:29.548732 WORK_FSP = 0x0
3873 12:40:29.551283 WL = 0x2
3874 12:40:29.551368 RL = 0x2
3875 12:40:29.554843 BL = 0x2
3876 12:40:29.554930 RPST = 0x0
3877 12:40:29.558161 RD_PRE = 0x0
3878 12:40:29.558252 WR_PRE = 0x1
3879 12:40:29.561020 WR_PST = 0x0
3880 12:40:29.561107 DBI_WR = 0x0
3881 12:40:29.564231 DBI_RD = 0x0
3882 12:40:29.564319 OTF = 0x1
3883 12:40:29.568010 ===================================
3884 12:40:29.574319 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3885 12:40:29.578821 nWR fixed to 30
3886 12:40:29.582371 [ModeRegInit_LP4] CH0 RK0
3887 12:40:29.582487 [ModeRegInit_LP4] CH0 RK1
3888 12:40:29.585287 [ModeRegInit_LP4] CH1 RK0
3889 12:40:29.588479 [ModeRegInit_LP4] CH1 RK1
3890 12:40:29.588567 match AC timing 17
3891 12:40:29.595538 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3892 12:40:29.598779 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3893 12:40:29.602728 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3894 12:40:29.608866 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3895 12:40:29.611542 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3896 12:40:29.611637 ==
3897 12:40:29.614774 Dram Type= 6, Freq= 0, CH_0, rank 0
3898 12:40:29.618205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3899 12:40:29.621527 ==
3900 12:40:29.625399 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3901 12:40:29.631684 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3902 12:40:29.634851 [CA 0] Center 36 (6~67) winsize 62
3903 12:40:29.638338 [CA 1] Center 36 (5~67) winsize 63
3904 12:40:29.641409 [CA 2] Center 34 (4~65) winsize 62
3905 12:40:29.645011 [CA 3] Center 34 (3~65) winsize 63
3906 12:40:29.648300 [CA 4] Center 33 (3~64) winsize 62
3907 12:40:29.651009 [CA 5] Center 33 (3~64) winsize 62
3908 12:40:29.651096
3909 12:40:29.654947 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3910 12:40:29.655033
3911 12:40:29.657908 [CATrainingPosCal] consider 1 rank data
3912 12:40:29.661712 u2DelayCellTimex100 = 270/100 ps
3913 12:40:29.664526 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3914 12:40:29.667803 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
3915 12:40:29.671259 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3916 12:40:29.677655 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3917 12:40:29.680901 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3918 12:40:29.684426 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3919 12:40:29.684517
3920 12:40:29.687376 CA PerBit enable=1, Macro0, CA PI delay=33
3921 12:40:29.687461
3922 12:40:29.690512 [CBTSetCACLKResult] CA Dly = 33
3923 12:40:29.690599 CS Dly: 4 (0~35)
3924 12:40:29.694011 ==
3925 12:40:29.697319 Dram Type= 6, Freq= 0, CH_0, rank 1
3926 12:40:29.700515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3927 12:40:29.700612 ==
3928 12:40:29.703547 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3929 12:40:29.710527 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3930 12:40:29.714051 [CA 0] Center 36 (6~67) winsize 62
3931 12:40:29.717421 [CA 1] Center 36 (6~67) winsize 62
3932 12:40:29.720709 [CA 2] Center 34 (4~65) winsize 62
3933 12:40:29.724066 [CA 3] Center 34 (4~65) winsize 62
3934 12:40:29.727701 [CA 4] Center 33 (3~64) winsize 62
3935 12:40:29.730831 [CA 5] Center 33 (3~64) winsize 62
3936 12:40:29.730916
3937 12:40:29.734163 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3938 12:40:29.734244
3939 12:40:29.737073 [CATrainingPosCal] consider 2 rank data
3940 12:40:29.740603 u2DelayCellTimex100 = 270/100 ps
3941 12:40:29.744283 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3942 12:40:29.750267 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3943 12:40:29.753833 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3944 12:40:29.757038 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3945 12:40:29.760310 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3946 12:40:29.763725 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3947 12:40:29.763846
3948 12:40:29.766774 CA PerBit enable=1, Macro0, CA PI delay=33
3949 12:40:29.766857
3950 12:40:29.770406 [CBTSetCACLKResult] CA Dly = 33
3951 12:40:29.773733 CS Dly: 5 (0~37)
3952 12:40:29.773816
3953 12:40:29.776470 ----->DramcWriteLeveling(PI) begin...
3954 12:40:29.776550 ==
3955 12:40:29.780011 Dram Type= 6, Freq= 0, CH_0, rank 0
3956 12:40:29.783221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3957 12:40:29.783324 ==
3958 12:40:29.786551 Write leveling (Byte 0): 31 => 31
3959 12:40:29.789824 Write leveling (Byte 1): 30 => 30
3960 12:40:29.793225 DramcWriteLeveling(PI) end<-----
3961 12:40:29.793317
3962 12:40:29.793386 ==
3963 12:40:29.796409 Dram Type= 6, Freq= 0, CH_0, rank 0
3964 12:40:29.799875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3965 12:40:29.799987 ==
3966 12:40:29.803161 [Gating] SW mode calibration
3967 12:40:29.809808 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3968 12:40:29.816689 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3969 12:40:29.819478 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3970 12:40:29.823288 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3971 12:40:29.829388 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3972 12:40:29.832928 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
3973 12:40:29.836635 0 9 16 | B1->B0 | 2e2e 2525 | 0 0 | (0 0) (0 0)
3974 12:40:29.843269 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3975 12:40:29.846119 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3976 12:40:29.849423 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3977 12:40:29.855631 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3978 12:40:29.859098 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 12:40:29.862386 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 12:40:29.869051 0 10 12 | B1->B0 | 2525 3030 | 0 0 | (0 0) (1 1)
3981 12:40:29.872515 0 10 16 | B1->B0 | 3a3a 4545 | 0 0 | (0 0) (0 0)
3982 12:40:29.875488 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3983 12:40:29.882343 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 12:40:29.885367 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3985 12:40:29.888711 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 12:40:29.895907 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 12:40:29.898843 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 12:40:29.902056 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 12:40:29.908156 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3990 12:40:29.911994 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 12:40:29.916245 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 12:40:29.921914 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 12:40:29.924688 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 12:40:29.931298 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 12:40:29.934683 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 12:40:29.938239 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 12:40:29.944524 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 12:40:29.948220 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 12:40:29.951192 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 12:40:29.957669 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 12:40:29.961598 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 12:40:29.964078 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 12:40:29.971081 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 12:40:29.974114 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 12:40:29.977386 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4006 12:40:29.980915 Total UI for P1: 0, mck2ui 16
4007 12:40:29.984270 best dqsien dly found for B0: ( 0, 13, 14)
4008 12:40:29.990804 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 12:40:29.990917 Total UI for P1: 0, mck2ui 16
4010 12:40:29.993818 best dqsien dly found for B1: ( 0, 13, 16)
4011 12:40:30.001015 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4012 12:40:30.003887 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4013 12:40:30.003978
4014 12:40:30.007483 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4015 12:40:30.010723 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4016 12:40:30.014208 [Gating] SW calibration Done
4017 12:40:30.014298 ==
4018 12:40:30.017110 Dram Type= 6, Freq= 0, CH_0, rank 0
4019 12:40:30.020796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4020 12:40:30.020888 ==
4021 12:40:30.023968 RX Vref Scan: 0
4022 12:40:30.024095
4023 12:40:30.024164 RX Vref 0 -> 0, step: 1
4024 12:40:30.024233
4025 12:40:30.026917 RX Delay -230 -> 252, step: 16
4026 12:40:30.033648 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4027 12:40:30.037117 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4028 12:40:30.040566 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4029 12:40:30.043383 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4030 12:40:30.047007 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4031 12:40:30.053595 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4032 12:40:30.056597 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4033 12:40:30.060008 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4034 12:40:30.063464 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4035 12:40:30.069830 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4036 12:40:30.073243 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4037 12:40:30.076529 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4038 12:40:30.079774 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4039 12:40:30.086341 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4040 12:40:30.090435 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4041 12:40:30.093492 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4042 12:40:30.093595 ==
4043 12:40:30.095951 Dram Type= 6, Freq= 0, CH_0, rank 0
4044 12:40:30.099536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4045 12:40:30.102536 ==
4046 12:40:30.102625 DQS Delay:
4047 12:40:30.102703 DQS0 = 0, DQS1 = 0
4048 12:40:30.106150 DQM Delay:
4049 12:40:30.106237 DQM0 = 46, DQM1 = 34
4050 12:40:30.109244 DQ Delay:
4051 12:40:30.112735 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4052 12:40:30.112824 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4053 12:40:30.115863 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =33
4054 12:40:30.119204 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4055 12:40:30.123089
4056 12:40:30.123203
4057 12:40:30.123273 ==
4058 12:40:30.125936 Dram Type= 6, Freq= 0, CH_0, rank 0
4059 12:40:30.129402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4060 12:40:30.129495 ==
4061 12:40:30.129564
4062 12:40:30.129624
4063 12:40:30.132494 TX Vref Scan disable
4064 12:40:30.132579 == TX Byte 0 ==
4065 12:40:30.139181 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4066 12:40:30.142494 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4067 12:40:30.142589 == TX Byte 1 ==
4068 12:40:30.148799 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4069 12:40:30.152287 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4070 12:40:30.152384 ==
4071 12:40:30.155436 Dram Type= 6, Freq= 0, CH_0, rank 0
4072 12:40:30.158640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4073 12:40:30.158737 ==
4074 12:40:30.158836
4075 12:40:30.161969
4076 12:40:30.162059 TX Vref Scan disable
4077 12:40:30.165889 == TX Byte 0 ==
4078 12:40:30.168770 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4079 12:40:30.175402 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4080 12:40:30.175518 == TX Byte 1 ==
4081 12:40:30.178355 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4082 12:40:30.185187 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4083 12:40:30.185294
4084 12:40:30.185362 [DATLAT]
4085 12:40:30.185424 Freq=600, CH0 RK0
4086 12:40:30.185485
4087 12:40:30.188787 DATLAT Default: 0x9
4088 12:40:30.192239 0, 0xFFFF, sum = 0
4089 12:40:30.192331 1, 0xFFFF, sum = 0
4090 12:40:30.194946 2, 0xFFFF, sum = 0
4091 12:40:30.195064 3, 0xFFFF, sum = 0
4092 12:40:30.198583 4, 0xFFFF, sum = 0
4093 12:40:30.198673 5, 0xFFFF, sum = 0
4094 12:40:30.201650 6, 0xFFFF, sum = 0
4095 12:40:30.201737 7, 0xFFFF, sum = 0
4096 12:40:30.204940 8, 0x0, sum = 1
4097 12:40:30.205028 9, 0x0, sum = 2
4098 12:40:30.208242 10, 0x0, sum = 3
4099 12:40:30.208332 11, 0x0, sum = 4
4100 12:40:30.208400 best_step = 9
4101 12:40:30.208461
4102 12:40:30.211793 ==
4103 12:40:30.214687 Dram Type= 6, Freq= 0, CH_0, rank 0
4104 12:40:30.218125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4105 12:40:30.218216 ==
4106 12:40:30.218284 RX Vref Scan: 1
4107 12:40:30.218346
4108 12:40:30.221187 RX Vref 0 -> 0, step: 1
4109 12:40:30.221273
4110 12:40:30.224614 RX Delay -195 -> 252, step: 8
4111 12:40:30.224701
4112 12:40:30.227797 Set Vref, RX VrefLevel [Byte0]: 52
4113 12:40:30.231100 [Byte1]: 49
4114 12:40:30.234341
4115 12:40:30.234430 Final RX Vref Byte 0 = 52 to rank0
4116 12:40:30.237905 Final RX Vref Byte 1 = 49 to rank0
4117 12:40:30.240949 Final RX Vref Byte 0 = 52 to rank1
4118 12:40:30.245112 Final RX Vref Byte 1 = 49 to rank1==
4119 12:40:30.247623 Dram Type= 6, Freq= 0, CH_0, rank 0
4120 12:40:30.254254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4121 12:40:30.254371 ==
4122 12:40:30.254441 DQS Delay:
4123 12:40:30.254503 DQS0 = 0, DQS1 = 0
4124 12:40:30.257482 DQM Delay:
4125 12:40:30.257569 DQM0 = 41, DQM1 = 34
4126 12:40:30.260953 DQ Delay:
4127 12:40:30.264290 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =36
4128 12:40:30.267350 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =44
4129 12:40:30.270877 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4130 12:40:30.273705 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =40
4131 12:40:30.273801
4132 12:40:30.273870
4133 12:40:30.280409 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a42, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
4134 12:40:30.283778 CH0 RK0: MR19=808, MR18=4A42
4135 12:40:30.290682 CH0_RK0: MR19=0x808, MR18=0x4A42, DQSOSC=395, MR23=63, INC=168, DEC=112
4136 12:40:30.290793
4137 12:40:30.293691 ----->DramcWriteLeveling(PI) begin...
4138 12:40:30.293779 ==
4139 12:40:30.297240 Dram Type= 6, Freq= 0, CH_0, rank 1
4140 12:40:30.300309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4141 12:40:30.300397 ==
4142 12:40:30.303852 Write leveling (Byte 0): 32 => 32
4143 12:40:30.307234 Write leveling (Byte 1): 32 => 32
4144 12:40:30.309966 DramcWriteLeveling(PI) end<-----
4145 12:40:30.310056
4146 12:40:30.310122 ==
4147 12:40:30.313684 Dram Type= 6, Freq= 0, CH_0, rank 1
4148 12:40:30.316601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 12:40:30.320455 ==
4150 12:40:30.320542 [Gating] SW mode calibration
4151 12:40:30.330201 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4152 12:40:30.333704 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4153 12:40:30.336668 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4154 12:40:30.342864 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4155 12:40:30.346735 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4156 12:40:30.349896 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
4157 12:40:30.356355 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
4158 12:40:30.359452 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4159 12:40:30.362880 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4160 12:40:30.369789 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4161 12:40:30.372927 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4162 12:40:30.376144 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4163 12:40:30.382700 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4164 12:40:30.385936 0 10 12 | B1->B0 | 2525 3232 | 0 1 | (0 0) (0 0)
4165 12:40:30.389065 0 10 16 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
4166 12:40:30.395676 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4167 12:40:30.399255 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4168 12:40:30.402401 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4169 12:40:30.408792 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4170 12:40:30.412182 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4171 12:40:30.415569 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4172 12:40:30.422440 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4173 12:40:30.425607 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4174 12:40:30.428577 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 12:40:30.436314 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 12:40:30.438883 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 12:40:30.442172 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 12:40:30.448636 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 12:40:30.452348 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 12:40:30.455239 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 12:40:30.461633 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 12:40:30.465099 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 12:40:30.468680 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 12:40:30.474979 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 12:40:30.478338 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 12:40:30.481537 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 12:40:30.488665 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 12:40:30.491616 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4189 12:40:30.495052 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4190 12:40:30.497957 Total UI for P1: 0, mck2ui 16
4191 12:40:30.501796 best dqsien dly found for B0: ( 0, 13, 12)
4192 12:40:30.508238 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 12:40:30.508375 Total UI for P1: 0, mck2ui 16
4194 12:40:30.514643 best dqsien dly found for B1: ( 0, 13, 14)
4195 12:40:30.517610 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4196 12:40:30.521221 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4197 12:40:30.521319
4198 12:40:30.524288 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4199 12:40:30.527836 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4200 12:40:30.530953 [Gating] SW calibration Done
4201 12:40:30.531051 ==
4202 12:40:30.534612 Dram Type= 6, Freq= 0, CH_0, rank 1
4203 12:40:30.537657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4204 12:40:30.537763 ==
4205 12:40:30.541054 RX Vref Scan: 0
4206 12:40:30.541150
4207 12:40:30.544316 RX Vref 0 -> 0, step: 1
4208 12:40:30.544411
4209 12:40:30.544481 RX Delay -230 -> 252, step: 16
4210 12:40:30.551336 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4211 12:40:30.554507 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4212 12:40:30.557461 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4213 12:40:30.560737 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4214 12:40:30.567266 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4215 12:40:30.571493 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4216 12:40:30.574065 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4217 12:40:30.577200 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4218 12:40:30.583829 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4219 12:40:30.587036 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4220 12:40:30.590605 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4221 12:40:30.593754 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4222 12:40:30.599958 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4223 12:40:30.603784 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4224 12:40:30.607060 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4225 12:40:30.610123 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4226 12:40:30.610229 ==
4227 12:40:30.613463 Dram Type= 6, Freq= 0, CH_0, rank 1
4228 12:40:30.619634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4229 12:40:30.619761 ==
4230 12:40:30.619832 DQS Delay:
4231 12:40:30.623471 DQS0 = 0, DQS1 = 0
4232 12:40:30.623564 DQM Delay:
4233 12:40:30.626235 DQM0 = 41, DQM1 = 33
4234 12:40:30.626323 DQ Delay:
4235 12:40:30.630303 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4236 12:40:30.633168 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4237 12:40:30.636238 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4238 12:40:30.639771 DQ12 =33, DQ13 =41, DQ14 =41, DQ15 =41
4239 12:40:30.639876
4240 12:40:30.639944
4241 12:40:30.640006 ==
4242 12:40:30.643306 Dram Type= 6, Freq= 0, CH_0, rank 1
4243 12:40:30.646073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4244 12:40:30.646168 ==
4245 12:40:30.646236
4246 12:40:30.646297
4247 12:40:30.649587 TX Vref Scan disable
4248 12:40:30.653315 == TX Byte 0 ==
4249 12:40:30.656366 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4250 12:40:30.659725 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4251 12:40:30.662693 == TX Byte 1 ==
4252 12:40:30.665840 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4253 12:40:30.670040 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4254 12:40:30.670147 ==
4255 12:40:30.672976 Dram Type= 6, Freq= 0, CH_0, rank 1
4256 12:40:30.678799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4257 12:40:30.678922 ==
4258 12:40:30.678993
4259 12:40:30.679055
4260 12:40:30.679114 TX Vref Scan disable
4261 12:40:30.683241 == TX Byte 0 ==
4262 12:40:30.687113 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4263 12:40:30.693169 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4264 12:40:30.693311 == TX Byte 1 ==
4265 12:40:30.696453 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4266 12:40:30.702812 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4267 12:40:30.702948
4268 12:40:30.703053 [DATLAT]
4269 12:40:30.703150 Freq=600, CH0 RK1
4270 12:40:30.703225
4271 12:40:30.706258 DATLAT Default: 0x9
4272 12:40:30.706381 0, 0xFFFF, sum = 0
4273 12:40:30.709733 1, 0xFFFF, sum = 0
4274 12:40:30.713337 2, 0xFFFF, sum = 0
4275 12:40:30.713445 3, 0xFFFF, sum = 0
4276 12:40:30.716250 4, 0xFFFF, sum = 0
4277 12:40:30.716338 5, 0xFFFF, sum = 0
4278 12:40:30.719700 6, 0xFFFF, sum = 0
4279 12:40:30.719785 7, 0xFFFF, sum = 0
4280 12:40:30.722746 8, 0x0, sum = 1
4281 12:40:30.722834 9, 0x0, sum = 2
4282 12:40:30.726251 10, 0x0, sum = 3
4283 12:40:30.726354 11, 0x0, sum = 4
4284 12:40:30.726419 best_step = 9
4285 12:40:30.726478
4286 12:40:30.729706 ==
4287 12:40:30.732852 Dram Type= 6, Freq= 0, CH_0, rank 1
4288 12:40:30.735946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4289 12:40:30.736105 ==
4290 12:40:30.736172 RX Vref Scan: 0
4291 12:40:30.736233
4292 12:40:30.739554 RX Vref 0 -> 0, step: 1
4293 12:40:30.739650
4294 12:40:30.742573 RX Delay -179 -> 252, step: 8
4295 12:40:30.749021 iDelay=197, Bit 0, Center 40 (-107 ~ 188) 296
4296 12:40:30.752606 iDelay=197, Bit 1, Center 44 (-107 ~ 196) 304
4297 12:40:30.755966 iDelay=197, Bit 2, Center 36 (-115 ~ 188) 304
4298 12:40:30.759411 iDelay=197, Bit 3, Center 40 (-107 ~ 188) 296
4299 12:40:30.765381 iDelay=197, Bit 4, Center 44 (-107 ~ 196) 304
4300 12:40:30.768700 iDelay=197, Bit 5, Center 28 (-123 ~ 180) 304
4301 12:40:30.772209 iDelay=197, Bit 6, Center 48 (-99 ~ 196) 296
4302 12:40:30.775562 iDelay=197, Bit 7, Center 48 (-99 ~ 196) 296
4303 12:40:30.778289 iDelay=197, Bit 8, Center 24 (-131 ~ 180) 312
4304 12:40:30.785500 iDelay=197, Bit 9, Center 20 (-139 ~ 180) 320
4305 12:40:30.788514 iDelay=197, Bit 10, Center 36 (-115 ~ 188) 304
4306 12:40:30.791884 iDelay=197, Bit 11, Center 28 (-123 ~ 180) 304
4307 12:40:30.795197 iDelay=197, Bit 12, Center 36 (-123 ~ 196) 320
4308 12:40:30.801506 iDelay=197, Bit 13, Center 36 (-115 ~ 188) 304
4309 12:40:30.804801 iDelay=197, Bit 14, Center 44 (-107 ~ 196) 304
4310 12:40:30.808069 iDelay=197, Bit 15, Center 40 (-115 ~ 196) 312
4311 12:40:30.808203 ==
4312 12:40:30.811622 Dram Type= 6, Freq= 0, CH_0, rank 1
4313 12:40:30.815985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4314 12:40:30.818397 ==
4315 12:40:30.818496 DQS Delay:
4316 12:40:30.818567 DQS0 = 0, DQS1 = 0
4317 12:40:30.821917 DQM Delay:
4318 12:40:30.822013 DQM0 = 41, DQM1 = 33
4319 12:40:30.824877 DQ Delay:
4320 12:40:30.827921 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4321 12:40:30.828022 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =48
4322 12:40:30.831582 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =28
4323 12:40:30.836137 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4324 12:40:30.837961
4325 12:40:30.838054
4326 12:40:30.844630 [DQSOSCAuto] RK1, (LSB)MR18= 0x403b, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4327 12:40:30.847816 CH0 RK1: MR19=808, MR18=403B
4328 12:40:30.854183 CH0_RK1: MR19=0x808, MR18=0x403B, DQSOSC=397, MR23=63, INC=166, DEC=110
4329 12:40:30.857519 [RxdqsGatingPostProcess] freq 600
4330 12:40:30.860933 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4331 12:40:30.864231 Pre-setting of DQS Precalculation
4332 12:40:30.870888 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4333 12:40:30.871032 ==
4334 12:40:30.874211 Dram Type= 6, Freq= 0, CH_1, rank 0
4335 12:40:30.877352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4336 12:40:30.877458 ==
4337 12:40:30.883678 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4338 12:40:30.890257 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4339 12:40:30.893876 [CA 0] Center 36 (6~66) winsize 61
4340 12:40:30.896870 [CA 1] Center 35 (5~66) winsize 62
4341 12:40:30.900424 [CA 2] Center 35 (5~65) winsize 61
4342 12:40:30.903728 [CA 3] Center 34 (3~65) winsize 63
4343 12:40:30.906842 [CA 4] Center 34 (3~65) winsize 63
4344 12:40:30.910075 [CA 5] Center 34 (3~65) winsize 63
4345 12:40:30.910186
4346 12:40:30.913266 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4347 12:40:30.913367
4348 12:40:30.916698 [CATrainingPosCal] consider 1 rank data
4349 12:40:30.920232 u2DelayCellTimex100 = 270/100 ps
4350 12:40:30.923419 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4351 12:40:30.926817 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4352 12:40:30.930440 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4353 12:40:30.933565 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4354 12:40:30.937307 CA4 delay=34 (3~65),Diff = 0 PI (0 cell)
4355 12:40:30.940404 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4356 12:40:30.940515
4357 12:40:30.946522 CA PerBit enable=1, Macro0, CA PI delay=34
4358 12:40:30.946649
4359 12:40:30.949925 [CBTSetCACLKResult] CA Dly = 34
4360 12:40:30.950027 CS Dly: 4 (0~35)
4361 12:40:30.950092 ==
4362 12:40:30.953136 Dram Type= 6, Freq= 0, CH_1, rank 1
4363 12:40:30.956291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4364 12:40:30.956396 ==
4365 12:40:30.963079 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4366 12:40:30.969764 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4367 12:40:30.973008 [CA 0] Center 35 (5~66) winsize 62
4368 12:40:30.975946 [CA 1] Center 35 (5~66) winsize 62
4369 12:40:30.979301 [CA 2] Center 34 (4~65) winsize 62
4370 12:40:30.983038 [CA 3] Center 34 (3~65) winsize 63
4371 12:40:30.985988 [CA 4] Center 34 (4~65) winsize 62
4372 12:40:30.989220 [CA 5] Center 34 (3~65) winsize 63
4373 12:40:30.989334
4374 12:40:30.992441 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4375 12:40:30.992544
4376 12:40:30.995630 [CATrainingPosCal] consider 2 rank data
4377 12:40:30.999383 u2DelayCellTimex100 = 270/100 ps
4378 12:40:31.002794 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4379 12:40:31.005585 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4380 12:40:31.008905 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4381 12:40:31.015206 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4382 12:40:31.018504 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4383 12:40:31.022077 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4384 12:40:31.022200
4385 12:40:31.025017 CA PerBit enable=1, Macro0, CA PI delay=34
4386 12:40:31.025118
4387 12:40:31.028396 [CBTSetCACLKResult] CA Dly = 34
4388 12:40:31.028503 CS Dly: 5 (0~37)
4389 12:40:31.028574
4390 12:40:31.032208 ----->DramcWriteLeveling(PI) begin...
4391 12:40:31.035434 ==
4392 12:40:31.038461 Dram Type= 6, Freq= 0, CH_1, rank 0
4393 12:40:31.042040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4394 12:40:31.042162 ==
4395 12:40:31.045669 Write leveling (Byte 0): 28 => 28
4396 12:40:31.048210 Write leveling (Byte 1): 30 => 30
4397 12:40:31.051955 DramcWriteLeveling(PI) end<-----
4398 12:40:31.052114
4399 12:40:31.052189 ==
4400 12:40:31.054661 Dram Type= 6, Freq= 0, CH_1, rank 0
4401 12:40:31.058190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4402 12:40:31.058302 ==
4403 12:40:31.061875 [Gating] SW mode calibration
4404 12:40:31.068344 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4405 12:40:31.074626 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4406 12:40:31.078185 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4407 12:40:31.081091 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4408 12:40:31.087665 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4409 12:40:31.090996 0 9 12 | B1->B0 | 3131 2f2f | 0 1 | (0 1) (1 0)
4410 12:40:31.094014 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4411 12:40:31.101016 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4412 12:40:31.104178 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4413 12:40:31.107307 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 12:40:31.114113 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 12:40:31.117096 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 12:40:31.120569 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4417 12:40:31.127143 0 10 12 | B1->B0 | 2e2e 3636 | 1 0 | (0 0) (0 0)
4418 12:40:31.130419 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 12:40:31.133699 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4420 12:40:31.140510 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4421 12:40:31.143853 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 12:40:31.147490 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 12:40:31.153829 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 12:40:31.156494 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 12:40:31.160282 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4426 12:40:31.167040 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4427 12:40:31.170342 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 12:40:31.173197 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 12:40:31.180404 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 12:40:31.182806 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 12:40:31.186452 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 12:40:31.192684 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 12:40:31.196475 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 12:40:31.199119 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 12:40:31.206127 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 12:40:31.209548 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 12:40:31.212474 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 12:40:31.219417 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 12:40:31.222510 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 12:40:31.225665 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 12:40:31.232198 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4442 12:40:31.235950 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4443 12:40:31.239107 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 12:40:31.241915 Total UI for P1: 0, mck2ui 16
4445 12:40:31.245313 best dqsien dly found for B0: ( 0, 13, 14)
4446 12:40:31.248373 Total UI for P1: 0, mck2ui 16
4447 12:40:31.253194 best dqsien dly found for B1: ( 0, 13, 14)
4448 12:40:31.258245 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4449 12:40:31.261727 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4450 12:40:31.261848
4451 12:40:31.265327 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4452 12:40:31.268025 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4453 12:40:31.271466 [Gating] SW calibration Done
4454 12:40:31.271581 ==
4455 12:40:31.275480 Dram Type= 6, Freq= 0, CH_1, rank 0
4456 12:40:31.278490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4457 12:40:31.278589 ==
4458 12:40:31.281989 RX Vref Scan: 0
4459 12:40:31.282085
4460 12:40:31.282153 RX Vref 0 -> 0, step: 1
4461 12:40:31.282214
4462 12:40:31.284969 RX Delay -230 -> 252, step: 16
4463 12:40:31.291175 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4464 12:40:31.294474 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4465 12:40:31.298218 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4466 12:40:31.301318 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4467 12:40:31.304545 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4468 12:40:31.311100 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4469 12:40:31.314770 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4470 12:40:31.317561 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4471 12:40:31.321449 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4472 12:40:31.327679 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4473 12:40:31.331040 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4474 12:40:31.334153 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4475 12:40:31.338036 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4476 12:40:31.344719 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4477 12:40:31.347348 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4478 12:40:31.350889 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4479 12:40:31.351012 ==
4480 12:40:31.354149 Dram Type= 6, Freq= 0, CH_1, rank 0
4481 12:40:31.357873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4482 12:40:31.360380 ==
4483 12:40:31.360491 DQS Delay:
4484 12:40:31.360559 DQS0 = 0, DQS1 = 0
4485 12:40:31.363704 DQM Delay:
4486 12:40:31.363816 DQM0 = 42, DQM1 = 37
4487 12:40:31.366952 DQ Delay:
4488 12:40:31.370468 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4489 12:40:31.370592 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33
4490 12:40:31.373996 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4491 12:40:31.380697 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4492 12:40:31.380844
4493 12:40:31.380918
4494 12:40:31.380980 ==
4495 12:40:31.383965 Dram Type= 6, Freq= 0, CH_1, rank 0
4496 12:40:31.387358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4497 12:40:31.387468 ==
4498 12:40:31.387538
4499 12:40:31.387600
4500 12:40:31.389881 TX Vref Scan disable
4501 12:40:31.389971 == TX Byte 0 ==
4502 12:40:31.396592 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4503 12:40:31.399996 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4504 12:40:31.400159 == TX Byte 1 ==
4505 12:40:31.407122 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4506 12:40:31.410114 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4507 12:40:31.410239 ==
4508 12:40:31.413357 Dram Type= 6, Freq= 0, CH_1, rank 0
4509 12:40:31.416948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4510 12:40:31.417063 ==
4511 12:40:31.417135
4512 12:40:31.419963
4513 12:40:31.420118 TX Vref Scan disable
4514 12:40:31.423085 == TX Byte 0 ==
4515 12:40:31.426989 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4516 12:40:31.433121 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4517 12:40:31.433274 == TX Byte 1 ==
4518 12:40:31.436391 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4519 12:40:31.443046 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4520 12:40:31.443198
4521 12:40:31.443274 [DATLAT]
4522 12:40:31.443337 Freq=600, CH1 RK0
4523 12:40:31.443431
4524 12:40:31.446453 DATLAT Default: 0x9
4525 12:40:31.446555 0, 0xFFFF, sum = 0
4526 12:40:31.449426 1, 0xFFFF, sum = 0
4527 12:40:31.453280 2, 0xFFFF, sum = 0
4528 12:40:31.453401 3, 0xFFFF, sum = 0
4529 12:40:31.456282 4, 0xFFFF, sum = 0
4530 12:40:31.456385 5, 0xFFFF, sum = 0
4531 12:40:31.460424 6, 0xFFFF, sum = 0
4532 12:40:31.460570 7, 0xFFFF, sum = 0
4533 12:40:31.463233 8, 0x0, sum = 1
4534 12:40:31.463337 9, 0x0, sum = 2
4535 12:40:31.463424 10, 0x0, sum = 3
4536 12:40:31.466290 11, 0x0, sum = 4
4537 12:40:31.466421 best_step = 9
4538 12:40:31.466488
4539 12:40:31.469466 ==
4540 12:40:31.469569 Dram Type= 6, Freq= 0, CH_1, rank 0
4541 12:40:31.476270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4542 12:40:31.476413 ==
4543 12:40:31.476486 RX Vref Scan: 1
4544 12:40:31.476548
4545 12:40:31.480158 RX Vref 0 -> 0, step: 1
4546 12:40:31.480268
4547 12:40:31.483384 RX Delay -179 -> 252, step: 8
4548 12:40:31.483480
4549 12:40:31.485865 Set Vref, RX VrefLevel [Byte0]: 51
4550 12:40:31.489152 [Byte1]: 50
4551 12:40:31.489273
4552 12:40:31.492581 Final RX Vref Byte 0 = 51 to rank0
4553 12:40:31.495662 Final RX Vref Byte 1 = 50 to rank0
4554 12:40:31.499410 Final RX Vref Byte 0 = 51 to rank1
4555 12:40:31.502272 Final RX Vref Byte 1 = 50 to rank1==
4556 12:40:31.505768 Dram Type= 6, Freq= 0, CH_1, rank 0
4557 12:40:31.509165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4558 12:40:31.512327 ==
4559 12:40:31.512447 DQS Delay:
4560 12:40:31.512518 DQS0 = 0, DQS1 = 0
4561 12:40:31.515733 DQM Delay:
4562 12:40:31.515829 DQM0 = 41, DQM1 = 34
4563 12:40:31.519118 DQ Delay:
4564 12:40:31.521976 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4565 12:40:31.522081 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4566 12:40:31.525680 DQ8 =20, DQ9 =24, DQ10 =32, DQ11 =28
4567 12:40:31.528707 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =40
4568 12:40:31.532345
4569 12:40:31.532465
4570 12:40:31.538721 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d47, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
4571 12:40:31.542043 CH1 RK0: MR19=808, MR18=2D47
4572 12:40:31.548466 CH1_RK0: MR19=0x808, MR18=0x2D47, DQSOSC=396, MR23=63, INC=167, DEC=111
4573 12:40:31.548618
4574 12:40:31.551831 ----->DramcWriteLeveling(PI) begin...
4575 12:40:31.551937 ==
4576 12:40:31.555392 Dram Type= 6, Freq= 0, CH_1, rank 1
4577 12:40:31.558490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 12:40:31.558604 ==
4579 12:40:31.561431 Write leveling (Byte 0): 27 => 27
4580 12:40:31.565044 Write leveling (Byte 1): 30 => 30
4581 12:40:31.568467 DramcWriteLeveling(PI) end<-----
4582 12:40:31.568590
4583 12:40:31.568657 ==
4584 12:40:31.571473 Dram Type= 6, Freq= 0, CH_1, rank 1
4585 12:40:31.574940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4586 12:40:31.575097 ==
4587 12:40:31.578342 [Gating] SW mode calibration
4588 12:40:31.584455 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4589 12:40:31.591053 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4590 12:40:31.594644 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4591 12:40:31.600912 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4592 12:40:31.604866 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4593 12:40:31.607689 0 9 12 | B1->B0 | 3030 2c2c | 0 0 | (0 0) (0 0)
4594 12:40:31.614301 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4595 12:40:31.618003 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4596 12:40:31.620849 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4597 12:40:31.627789 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4598 12:40:31.630760 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 12:40:31.634036 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 12:40:31.640851 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4601 12:40:31.644363 0 10 12 | B1->B0 | 3333 3c3c | 0 0 | (0 0) (0 0)
4602 12:40:31.647468 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4603 12:40:31.654016 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4604 12:40:31.657333 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4605 12:40:31.660683 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 12:40:31.666604 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 12:40:31.670105 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 12:40:31.673413 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 12:40:31.680180 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4610 12:40:31.683056 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 12:40:31.686453 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 12:40:31.693035 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 12:40:31.697035 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 12:40:31.699361 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 12:40:31.706159 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 12:40:31.709401 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 12:40:31.712692 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 12:40:31.719641 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 12:40:31.722372 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 12:40:31.726275 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 12:40:31.732286 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 12:40:31.735589 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 12:40:31.739025 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 12:40:31.745720 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4625 12:40:31.749031 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4626 12:40:31.755145 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 12:40:31.755293 Total UI for P1: 0, mck2ui 16
4628 12:40:31.759001 best dqsien dly found for B0: ( 0, 13, 10)
4629 12:40:31.762320 Total UI for P1: 0, mck2ui 16
4630 12:40:31.765441 best dqsien dly found for B1: ( 0, 13, 12)
4631 12:40:31.771811 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4632 12:40:31.775024 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4633 12:40:31.775150
4634 12:40:31.779252 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4635 12:40:31.781967 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4636 12:40:31.784868 [Gating] SW calibration Done
4637 12:40:31.784982 ==
4638 12:40:31.787940 Dram Type= 6, Freq= 0, CH_1, rank 1
4639 12:40:31.791406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4640 12:40:31.791533 ==
4641 12:40:31.794705 RX Vref Scan: 0
4642 12:40:31.794811
4643 12:40:31.794879 RX Vref 0 -> 0, step: 1
4644 12:40:31.794941
4645 12:40:31.798031 RX Delay -230 -> 252, step: 16
4646 12:40:31.804691 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4647 12:40:31.807543 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4648 12:40:31.811710 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4649 12:40:31.814772 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4650 12:40:31.821263 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4651 12:40:31.824443 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4652 12:40:31.827906 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4653 12:40:31.831192 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4654 12:40:31.834131 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4655 12:40:31.840750 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4656 12:40:31.844290 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4657 12:40:31.847405 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4658 12:40:31.850838 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4659 12:40:31.857482 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4660 12:40:31.860514 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4661 12:40:31.863981 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4662 12:40:31.864181 ==
4663 12:40:31.867246 Dram Type= 6, Freq= 0, CH_1, rank 1
4664 12:40:31.873932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4665 12:40:31.874106 ==
4666 12:40:31.874244 DQS Delay:
4667 12:40:31.876872 DQS0 = 0, DQS1 = 0
4668 12:40:31.876978 DQM Delay:
4669 12:40:31.877079 DQM0 = 42, DQM1 = 39
4670 12:40:31.880442 DQ Delay:
4671 12:40:31.883749 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4672 12:40:31.886941 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4673 12:40:31.890164 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4674 12:40:31.893581 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4675 12:40:31.893702
4676 12:40:31.893770
4677 12:40:31.893831 ==
4678 12:40:31.896564 Dram Type= 6, Freq= 0, CH_1, rank 1
4679 12:40:31.900202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4680 12:40:31.900410 ==
4681 12:40:31.900544
4682 12:40:31.900624
4683 12:40:31.903034 TX Vref Scan disable
4684 12:40:31.906483 == TX Byte 0 ==
4685 12:40:31.909917 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4686 12:40:31.913144 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4687 12:40:31.916680 == TX Byte 1 ==
4688 12:40:31.919638 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4689 12:40:31.923000 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4690 12:40:31.923133 ==
4691 12:40:31.926394 Dram Type= 6, Freq= 0, CH_1, rank 1
4692 12:40:31.929409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4693 12:40:31.932793 ==
4694 12:40:31.932968
4695 12:40:31.933059
4696 12:40:31.933141 TX Vref Scan disable
4697 12:40:31.936688 == TX Byte 0 ==
4698 12:40:31.940369 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4699 12:40:31.946981 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4700 12:40:31.947129 == TX Byte 1 ==
4701 12:40:31.950019 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4702 12:40:31.956522 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4703 12:40:31.956714
4704 12:40:31.956827 [DATLAT]
4705 12:40:31.956921 Freq=600, CH1 RK1
4706 12:40:31.957013
4707 12:40:31.959679 DATLAT Default: 0x9
4708 12:40:31.963281 0, 0xFFFF, sum = 0
4709 12:40:31.963439 1, 0xFFFF, sum = 0
4710 12:40:31.966408 2, 0xFFFF, sum = 0
4711 12:40:31.966555 3, 0xFFFF, sum = 0
4712 12:40:31.969799 4, 0xFFFF, sum = 0
4713 12:40:31.969946 5, 0xFFFF, sum = 0
4714 12:40:31.973542 6, 0xFFFF, sum = 0
4715 12:40:31.973690 7, 0xFFFF, sum = 0
4716 12:40:31.976256 8, 0x0, sum = 1
4717 12:40:31.976394 9, 0x0, sum = 2
4718 12:40:31.979531 10, 0x0, sum = 3
4719 12:40:31.979691 11, 0x0, sum = 4
4720 12:40:31.979796 best_step = 9
4721 12:40:31.979890
4722 12:40:31.982953 ==
4723 12:40:31.985972 Dram Type= 6, Freq= 0, CH_1, rank 1
4724 12:40:31.989313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4725 12:40:31.989478 ==
4726 12:40:31.989589 RX Vref Scan: 0
4727 12:40:31.989683
4728 12:40:31.992755 RX Vref 0 -> 0, step: 1
4729 12:40:31.992890
4730 12:40:31.995950 RX Delay -179 -> 252, step: 8
4731 12:40:32.003135 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4732 12:40:32.005664 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4733 12:40:32.009269 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4734 12:40:32.012254 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4735 12:40:32.016235 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4736 12:40:32.022437 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4737 12:40:32.025707 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4738 12:40:32.028826 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4739 12:40:32.032634 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4740 12:40:32.039038 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4741 12:40:32.042089 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4742 12:40:32.045591 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4743 12:40:32.049749 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4744 12:40:32.055392 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4745 12:40:32.058671 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4746 12:40:32.061984 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4747 12:40:32.062165 ==
4748 12:40:32.065183 Dram Type= 6, Freq= 0, CH_1, rank 1
4749 12:40:32.071531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4750 12:40:32.071714 ==
4751 12:40:32.071822 DQS Delay:
4752 12:40:32.071915 DQS0 = 0, DQS1 = 0
4753 12:40:32.075065 DQM Delay:
4754 12:40:32.075196 DQM0 = 37, DQM1 = 35
4755 12:40:32.078857 DQ Delay:
4756 12:40:32.082022 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =36
4757 12:40:32.084629 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =32
4758 12:40:32.088276 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4759 12:40:32.091495 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =40
4760 12:40:32.091640
4761 12:40:32.091745
4762 12:40:32.098479 [DQSOSCAuto] RK1, (LSB)MR18= 0x3055, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4763 12:40:32.101588 CH1 RK1: MR19=808, MR18=3055
4764 12:40:32.108654 CH1_RK1: MR19=0x808, MR18=0x3055, DQSOSC=393, MR23=63, INC=169, DEC=113
4765 12:40:32.111165 [RxdqsGatingPostProcess] freq 600
4766 12:40:32.114821 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4767 12:40:32.117558 Pre-setting of DQS Precalculation
4768 12:40:32.124399 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4769 12:40:32.130814 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4770 12:40:32.137872 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4771 12:40:32.138068
4772 12:40:32.138177
4773 12:40:32.141147 [Calibration Summary] 1200 Mbps
4774 12:40:32.141274 CH 0, Rank 0
4775 12:40:32.144371 SW Impedance : PASS
4776 12:40:32.147484 DUTY Scan : NO K
4777 12:40:32.147621 ZQ Calibration : PASS
4778 12:40:32.150958 Jitter Meter : NO K
4779 12:40:32.154728 CBT Training : PASS
4780 12:40:32.154880 Write leveling : PASS
4781 12:40:32.157806 RX DQS gating : PASS
4782 12:40:32.161142 RX DQ/DQS(RDDQC) : PASS
4783 12:40:32.161280 TX DQ/DQS : PASS
4784 12:40:32.164155 RX DATLAT : PASS
4785 12:40:32.167263 RX DQ/DQS(Engine): PASS
4786 12:40:32.167398 TX OE : NO K
4787 12:40:32.170517 All Pass.
4788 12:40:32.170646
4789 12:40:32.170780 CH 0, Rank 1
4790 12:40:32.173914 SW Impedance : PASS
4791 12:40:32.174058 DUTY Scan : NO K
4792 12:40:32.176964 ZQ Calibration : PASS
4793 12:40:32.180464 Jitter Meter : NO K
4794 12:40:32.180602 CBT Training : PASS
4795 12:40:32.184398 Write leveling : PASS
4796 12:40:32.187298 RX DQS gating : PASS
4797 12:40:32.187429 RX DQ/DQS(RDDQC) : PASS
4798 12:40:32.190145 TX DQ/DQS : PASS
4799 12:40:32.193557 RX DATLAT : PASS
4800 12:40:32.193720 RX DQ/DQS(Engine): PASS
4801 12:40:32.197231 TX OE : NO K
4802 12:40:32.197363 All Pass.
4803 12:40:32.197464
4804 12:40:32.200364 CH 1, Rank 0
4805 12:40:32.200479 SW Impedance : PASS
4806 12:40:32.203183 DUTY Scan : NO K
4807 12:40:32.206504 ZQ Calibration : PASS
4808 12:40:32.206653 Jitter Meter : NO K
4809 12:40:32.210111 CBT Training : PASS
4810 12:40:32.213293 Write leveling : PASS
4811 12:40:32.213434 RX DQS gating : PASS
4812 12:40:32.216844 RX DQ/DQS(RDDQC) : PASS
4813 12:40:32.216969 TX DQ/DQS : PASS
4814 12:40:32.220280 RX DATLAT : PASS
4815 12:40:32.223621 RX DQ/DQS(Engine): PASS
4816 12:40:32.223762 TX OE : NO K
4817 12:40:32.227143 All Pass.
4818 12:40:32.227272
4819 12:40:32.227371 CH 1, Rank 1
4820 12:40:32.229886 SW Impedance : PASS
4821 12:40:32.229999 DUTY Scan : NO K
4822 12:40:32.233034 ZQ Calibration : PASS
4823 12:40:32.236133 Jitter Meter : NO K
4824 12:40:32.236259 CBT Training : PASS
4825 12:40:32.239484 Write leveling : PASS
4826 12:40:32.242998 RX DQS gating : PASS
4827 12:40:32.243141 RX DQ/DQS(RDDQC) : PASS
4828 12:40:32.246057 TX DQ/DQS : PASS
4829 12:40:32.249447 RX DATLAT : PASS
4830 12:40:32.249586 RX DQ/DQS(Engine): PASS
4831 12:40:32.252759 TX OE : NO K
4832 12:40:32.252887 All Pass.
4833 12:40:32.252985
4834 12:40:32.255989 DramC Write-DBI off
4835 12:40:32.259561 PER_BANK_REFRESH: Hybrid Mode
4836 12:40:32.259705 TX_TRACKING: ON
4837 12:40:32.269092 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4838 12:40:32.272612 [FAST_K] Save calibration result to emmc
4839 12:40:32.275877 dramc_set_vcore_voltage set vcore to 662500
4840 12:40:32.279498 Read voltage for 933, 3
4841 12:40:32.279631 Vio18 = 0
4842 12:40:32.279709 Vcore = 662500
4843 12:40:32.282632 Vdram = 0
4844 12:40:32.282747 Vddq = 0
4845 12:40:32.282860 Vmddr = 0
4846 12:40:32.288926 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4847 12:40:32.292479 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4848 12:40:32.295355 MEM_TYPE=3, freq_sel=17
4849 12:40:32.299185 sv_algorithm_assistance_LP4_1600
4850 12:40:32.302283 ============ PULL DRAM RESETB DOWN ============
4851 12:40:32.309106 ========== PULL DRAM RESETB DOWN end =========
4852 12:40:32.312077 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4853 12:40:32.315359 ===================================
4854 12:40:32.318306 LPDDR4 DRAM CONFIGURATION
4855 12:40:32.321711 ===================================
4856 12:40:32.321846 EX_ROW_EN[0] = 0x0
4857 12:40:32.325343 EX_ROW_EN[1] = 0x0
4858 12:40:32.325445 LP4Y_EN = 0x0
4859 12:40:32.328493 WORK_FSP = 0x0
4860 12:40:32.328590 WL = 0x3
4861 12:40:32.331798 RL = 0x3
4862 12:40:32.331893 BL = 0x2
4863 12:40:32.335334 RPST = 0x0
4864 12:40:32.338257 RD_PRE = 0x0
4865 12:40:32.338350 WR_PRE = 0x1
4866 12:40:32.341903 WR_PST = 0x0
4867 12:40:32.342020 DBI_WR = 0x0
4868 12:40:32.345293 DBI_RD = 0x0
4869 12:40:32.345421 OTF = 0x1
4870 12:40:32.348143 ===================================
4871 12:40:32.352208 ===================================
4872 12:40:32.355285 ANA top config
4873 12:40:32.358268 ===================================
4874 12:40:32.358369 DLL_ASYNC_EN = 0
4875 12:40:32.361334 ALL_SLAVE_EN = 1
4876 12:40:32.364916 NEW_RANK_MODE = 1
4877 12:40:32.368396 DLL_IDLE_MODE = 1
4878 12:40:32.368510 LP45_APHY_COMB_EN = 1
4879 12:40:32.371352 TX_ODT_DIS = 1
4880 12:40:32.374749 NEW_8X_MODE = 1
4881 12:40:32.378620 ===================================
4882 12:40:32.381375 ===================================
4883 12:40:32.384667 data_rate = 1866
4884 12:40:32.388221 CKR = 1
4885 12:40:32.391385 DQ_P2S_RATIO = 8
4886 12:40:32.394458 ===================================
4887 12:40:32.394570 CA_P2S_RATIO = 8
4888 12:40:32.397907 DQ_CA_OPEN = 0
4889 12:40:32.401172 DQ_SEMI_OPEN = 0
4890 12:40:32.404639 CA_SEMI_OPEN = 0
4891 12:40:32.407737 CA_FULL_RATE = 0
4892 12:40:32.411177 DQ_CKDIV4_EN = 1
4893 12:40:32.411289 CA_CKDIV4_EN = 1
4894 12:40:32.414809 CA_PREDIV_EN = 0
4895 12:40:32.417869 PH8_DLY = 0
4896 12:40:32.420677 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4897 12:40:32.424012 DQ_AAMCK_DIV = 4
4898 12:40:32.427428 CA_AAMCK_DIV = 4
4899 12:40:32.427550 CA_ADMCK_DIV = 4
4900 12:40:32.430778 DQ_TRACK_CA_EN = 0
4901 12:40:32.434167 CA_PICK = 933
4902 12:40:32.437387 CA_MCKIO = 933
4903 12:40:32.440634 MCKIO_SEMI = 0
4904 12:40:32.444201 PLL_FREQ = 3732
4905 12:40:32.447676 DQ_UI_PI_RATIO = 32
4906 12:40:32.447796 CA_UI_PI_RATIO = 0
4907 12:40:32.450811 ===================================
4908 12:40:32.454169 ===================================
4909 12:40:32.458104 memory_type:LPDDR4
4910 12:40:32.460588 GP_NUM : 10
4911 12:40:32.460695 SRAM_EN : 1
4912 12:40:32.463981 MD32_EN : 0
4913 12:40:32.467091 ===================================
4914 12:40:32.470297 [ANA_INIT] >>>>>>>>>>>>>>
4915 12:40:32.474107 <<<<<< [CONFIGURE PHASE]: ANA_TX
4916 12:40:32.477074 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4917 12:40:32.480213 ===================================
4918 12:40:32.483480 data_rate = 1866,PCW = 0X8f00
4919 12:40:32.486934 ===================================
4920 12:40:32.490578 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4921 12:40:32.493578 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4922 12:40:32.499806 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4923 12:40:32.503292 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4924 12:40:32.506721 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4925 12:40:32.510053 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4926 12:40:32.513366 [ANA_INIT] flow start
4927 12:40:32.516221 [ANA_INIT] PLL >>>>>>>>
4928 12:40:32.516344 [ANA_INIT] PLL <<<<<<<<
4929 12:40:32.520909 [ANA_INIT] MIDPI >>>>>>>>
4930 12:40:32.523005 [ANA_INIT] MIDPI <<<<<<<<
4931 12:40:32.526558 [ANA_INIT] DLL >>>>>>>>
4932 12:40:32.526672 [ANA_INIT] flow end
4933 12:40:32.530010 ============ LP4 DIFF to SE enter ============
4934 12:40:32.536290 ============ LP4 DIFF to SE exit ============
4935 12:40:32.536497 [ANA_INIT] <<<<<<<<<<<<<
4936 12:40:32.539770 [Flow] Enable top DCM control >>>>>
4937 12:40:32.542640 [Flow] Enable top DCM control <<<<<
4938 12:40:32.546838 Enable DLL master slave shuffle
4939 12:40:32.552580 ==============================================================
4940 12:40:32.552717 Gating Mode config
4941 12:40:32.559319 ==============================================================
4942 12:40:32.563109 Config description:
4943 12:40:32.572608 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4944 12:40:32.579177 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4945 12:40:32.582478 SELPH_MODE 0: By rank 1: By Phase
4946 12:40:32.589112 ==============================================================
4947 12:40:32.592469 GAT_TRACK_EN = 1
4948 12:40:32.596167 RX_GATING_MODE = 2
4949 12:40:32.596297 RX_GATING_TRACK_MODE = 2
4950 12:40:32.599750 SELPH_MODE = 1
4951 12:40:32.602208 PICG_EARLY_EN = 1
4952 12:40:32.606287 VALID_LAT_VALUE = 1
4953 12:40:32.611980 ==============================================================
4954 12:40:32.616064 Enter into Gating configuration >>>>
4955 12:40:32.618840 Exit from Gating configuration <<<<
4956 12:40:32.622082 Enter into DVFS_PRE_config >>>>>
4957 12:40:32.631944 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4958 12:40:32.634881 Exit from DVFS_PRE_config <<<<<
4959 12:40:32.639106 Enter into PICG configuration >>>>
4960 12:40:32.641965 Exit from PICG configuration <<<<
4961 12:40:32.644833 [RX_INPUT] configuration >>>>>
4962 12:40:32.648373 [RX_INPUT] configuration <<<<<
4963 12:40:32.651755 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4964 12:40:32.658261 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4965 12:40:32.664596 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4966 12:40:32.671005 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4967 12:40:32.677556 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4968 12:40:32.684604 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4969 12:40:32.687730 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4970 12:40:32.690930 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4971 12:40:32.694250 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4972 12:40:32.700896 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4973 12:40:32.704271 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4974 12:40:32.707240 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4975 12:40:32.710542 ===================================
4976 12:40:32.714050 LPDDR4 DRAM CONFIGURATION
4977 12:40:32.717433 ===================================
4978 12:40:32.717576 EX_ROW_EN[0] = 0x0
4979 12:40:32.720728 EX_ROW_EN[1] = 0x0
4980 12:40:32.723924 LP4Y_EN = 0x0
4981 12:40:32.724108 WORK_FSP = 0x0
4982 12:40:32.727212 WL = 0x3
4983 12:40:32.727343 RL = 0x3
4984 12:40:32.730471 BL = 0x2
4985 12:40:32.730569 RPST = 0x0
4986 12:40:32.733661 RD_PRE = 0x0
4987 12:40:32.733758 WR_PRE = 0x1
4988 12:40:32.737105 WR_PST = 0x0
4989 12:40:32.737232 DBI_WR = 0x0
4990 12:40:32.740060 DBI_RD = 0x0
4991 12:40:32.740186 OTF = 0x1
4992 12:40:32.743241 ===================================
4993 12:40:32.746641 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4994 12:40:32.753674 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4995 12:40:32.757021 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4996 12:40:32.760276 ===================================
4997 12:40:32.763408 LPDDR4 DRAM CONFIGURATION
4998 12:40:32.766903 ===================================
4999 12:40:32.767033 EX_ROW_EN[0] = 0x10
5000 12:40:32.770204 EX_ROW_EN[1] = 0x0
5001 12:40:32.773566 LP4Y_EN = 0x0
5002 12:40:32.773687 WORK_FSP = 0x0
5003 12:40:32.776466 WL = 0x3
5004 12:40:32.776569 RL = 0x3
5005 12:40:32.779987 BL = 0x2
5006 12:40:32.780125 RPST = 0x0
5007 12:40:32.783284 RD_PRE = 0x0
5008 12:40:32.783386 WR_PRE = 0x1
5009 12:40:32.786795 WR_PST = 0x0
5010 12:40:32.786898 DBI_WR = 0x0
5011 12:40:32.790004 DBI_RD = 0x0
5012 12:40:32.790101 OTF = 0x1
5013 12:40:32.793552 ===================================
5014 12:40:32.799431 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5015 12:40:32.804049 nWR fixed to 30
5016 12:40:32.807671 [ModeRegInit_LP4] CH0 RK0
5017 12:40:32.807795 [ModeRegInit_LP4] CH0 RK1
5018 12:40:32.810888 [ModeRegInit_LP4] CH1 RK0
5019 12:40:32.814444 [ModeRegInit_LP4] CH1 RK1
5020 12:40:32.814561 match AC timing 9
5021 12:40:32.821021 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5022 12:40:32.823978 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5023 12:40:32.828333 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5024 12:40:32.834205 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5025 12:40:32.837192 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5026 12:40:32.837320 ==
5027 12:40:32.840643 Dram Type= 6, Freq= 0, CH_0, rank 0
5028 12:40:32.844174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5029 12:40:32.844313 ==
5030 12:40:32.850625 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5031 12:40:32.856792 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5032 12:40:32.860095 [CA 0] Center 37 (7~68) winsize 62
5033 12:40:32.863722 [CA 1] Center 37 (7~68) winsize 62
5034 12:40:32.867181 [CA 2] Center 34 (4~65) winsize 62
5035 12:40:32.870241 [CA 3] Center 34 (4~65) winsize 62
5036 12:40:32.873442 [CA 4] Center 33 (3~63) winsize 61
5037 12:40:32.877047 [CA 5] Center 32 (2~63) winsize 62
5038 12:40:32.877178
5039 12:40:32.880194 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5040 12:40:32.880307
5041 12:40:32.883225 [CATrainingPosCal] consider 1 rank data
5042 12:40:32.886621 u2DelayCellTimex100 = 270/100 ps
5043 12:40:32.889846 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5044 12:40:32.893229 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5045 12:40:32.896898 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5046 12:40:32.902860 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5047 12:40:32.906865 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5048 12:40:32.909576 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5049 12:40:32.909689
5050 12:40:32.912747 CA PerBit enable=1, Macro0, CA PI delay=32
5051 12:40:32.912849
5052 12:40:32.916171 [CBTSetCACLKResult] CA Dly = 32
5053 12:40:32.916277 CS Dly: 6 (0~37)
5054 12:40:32.916347 ==
5055 12:40:32.919525 Dram Type= 6, Freq= 0, CH_0, rank 1
5056 12:40:32.926092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5057 12:40:32.926243 ==
5058 12:40:32.929362 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5059 12:40:32.935761 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5060 12:40:32.939572 [CA 0] Center 37 (7~68) winsize 62
5061 12:40:32.942447 [CA 1] Center 37 (7~68) winsize 62
5062 12:40:32.946031 [CA 2] Center 35 (5~65) winsize 61
5063 12:40:32.949361 [CA 3] Center 34 (3~65) winsize 63
5064 12:40:32.952390 [CA 4] Center 33 (3~64) winsize 62
5065 12:40:32.955858 [CA 5] Center 32 (2~63) winsize 62
5066 12:40:32.955981
5067 12:40:32.958933 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5068 12:40:32.959030
5069 12:40:32.962715 [CATrainingPosCal] consider 2 rank data
5070 12:40:32.965389 u2DelayCellTimex100 = 270/100 ps
5071 12:40:32.971975 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5072 12:40:32.975748 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5073 12:40:32.978672 CA2 delay=35 (5~65),Diff = 3 PI (18 cell)
5074 12:40:32.981932 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5075 12:40:32.984977 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5076 12:40:32.988529 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5077 12:40:32.988643
5078 12:40:32.991867 CA PerBit enable=1, Macro0, CA PI delay=32
5079 12:40:32.991998
5080 12:40:32.995658 [CBTSetCACLKResult] CA Dly = 32
5081 12:40:32.998101 CS Dly: 7 (0~39)
5082 12:40:32.998206
5083 12:40:33.001661 ----->DramcWriteLeveling(PI) begin...
5084 12:40:33.001764 ==
5085 12:40:33.005088 Dram Type= 6, Freq= 0, CH_0, rank 0
5086 12:40:33.008916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5087 12:40:33.009036 ==
5088 12:40:33.011910 Write leveling (Byte 0): 32 => 32
5089 12:40:33.014820 Write leveling (Byte 1): 29 => 29
5090 12:40:33.017875 DramcWriteLeveling(PI) end<-----
5091 12:40:33.017985
5092 12:40:33.018055 ==
5093 12:40:33.021455 Dram Type= 6, Freq= 0, CH_0, rank 0
5094 12:40:33.024873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5095 12:40:33.024986 ==
5096 12:40:33.028094 [Gating] SW mode calibration
5097 12:40:33.034151 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5098 12:40:33.041243 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5099 12:40:33.044100 0 14 0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
5100 12:40:33.050742 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5101 12:40:33.054033 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5102 12:40:33.057485 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5103 12:40:33.064027 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 12:40:33.067472 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 12:40:33.070543 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 12:40:33.077987 0 14 28 | B1->B0 | 3434 2c2c | 0 1 | (0 0) (1 0)
5107 12:40:33.080411 0 15 0 | B1->B0 | 3030 2424 | 0 0 | (0 1) (0 0)
5108 12:40:33.083917 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5109 12:40:33.090601 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5110 12:40:33.093709 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 12:40:33.097257 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 12:40:33.103320 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 12:40:33.107152 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5114 12:40:33.110640 0 15 28 | B1->B0 | 2424 3838 | 1 0 | (0 0) (0 0)
5115 12:40:33.116640 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5116 12:40:33.120347 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5117 12:40:33.123393 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5118 12:40:33.130123 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 12:40:33.133178 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 12:40:33.136774 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 12:40:33.143342 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5122 12:40:33.146297 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5123 12:40:33.149727 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5124 12:40:33.156247 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5125 12:40:33.159713 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 12:40:33.162885 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 12:40:33.169358 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 12:40:33.172722 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 12:40:33.175739 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 12:40:33.182412 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 12:40:33.185632 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 12:40:33.189493 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 12:40:33.196621 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 12:40:33.199527 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 12:40:33.202420 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 12:40:33.208908 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 12:40:33.212559 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 12:40:33.215751 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5139 12:40:33.222155 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5140 12:40:33.225103 Total UI for P1: 0, mck2ui 16
5141 12:40:33.228516 best dqsien dly found for B0: ( 1, 2, 28)
5142 12:40:33.231986 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 12:40:33.234940 Total UI for P1: 0, mck2ui 16
5144 12:40:33.238594 best dqsien dly found for B1: ( 1, 3, 0)
5145 12:40:33.241523 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5146 12:40:33.244798 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5147 12:40:33.244914
5148 12:40:33.248258 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5149 12:40:33.255125 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5150 12:40:33.255274 [Gating] SW calibration Done
5151 12:40:33.255350 ==
5152 12:40:33.257846 Dram Type= 6, Freq= 0, CH_0, rank 0
5153 12:40:33.264498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5154 12:40:33.264670 ==
5155 12:40:33.264748 RX Vref Scan: 0
5156 12:40:33.264813
5157 12:40:33.267700 RX Vref 0 -> 0, step: 1
5158 12:40:33.267784
5159 12:40:33.271169 RX Delay -80 -> 252, step: 8
5160 12:40:33.274684 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5161 12:40:33.278171 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5162 12:40:33.281770 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5163 12:40:33.284468 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5164 12:40:33.290893 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5165 12:40:33.294145 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5166 12:40:33.297341 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5167 12:40:33.300758 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5168 12:40:33.304191 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5169 12:40:33.310652 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5170 12:40:33.314610 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5171 12:40:33.317730 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5172 12:40:33.320662 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5173 12:40:33.323979 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5174 12:40:33.327178 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5175 12:40:33.333525 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5176 12:40:33.333666 ==
5177 12:40:33.336787 Dram Type= 6, Freq= 0, CH_0, rank 0
5178 12:40:33.340302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5179 12:40:33.340428 ==
5180 12:40:33.340529 DQS Delay:
5181 12:40:33.343931 DQS0 = 0, DQS1 = 0
5182 12:40:33.344042 DQM Delay:
5183 12:40:33.347521 DQM0 = 99, DQM1 = 88
5184 12:40:33.347624 DQ Delay:
5185 12:40:33.350385 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5186 12:40:33.354095 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =107
5187 12:40:33.357742 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5188 12:40:33.360314 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5189 12:40:33.360417
5190 12:40:33.360500
5191 12:40:33.360602 ==
5192 12:40:33.363926 Dram Type= 6, Freq= 0, CH_0, rank 0
5193 12:40:33.369978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5194 12:40:33.370121 ==
5195 12:40:33.370195
5196 12:40:33.370256
5197 12:40:33.370314 TX Vref Scan disable
5198 12:40:33.373244 == TX Byte 0 ==
5199 12:40:33.376527 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5200 12:40:33.383919 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5201 12:40:33.384109 == TX Byte 1 ==
5202 12:40:33.387180 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5203 12:40:33.393046 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5204 12:40:33.393194 ==
5205 12:40:33.396194 Dram Type= 6, Freq= 0, CH_0, rank 0
5206 12:40:33.399733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5207 12:40:33.399851 ==
5208 12:40:33.399919
5209 12:40:33.399980
5210 12:40:33.403087 TX Vref Scan disable
5211 12:40:33.406297 == TX Byte 0 ==
5212 12:40:33.409066 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5213 12:40:33.412580 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5214 12:40:33.415686 == TX Byte 1 ==
5215 12:40:33.420068 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5216 12:40:33.423157 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5217 12:40:33.423271
5218 12:40:33.423340 [DATLAT]
5219 12:40:33.426316 Freq=933, CH0 RK0
5220 12:40:33.426411
5221 12:40:33.429286 DATLAT Default: 0xd
5222 12:40:33.429387 0, 0xFFFF, sum = 0
5223 12:40:33.432355 1, 0xFFFF, sum = 0
5224 12:40:33.432451 2, 0xFFFF, sum = 0
5225 12:40:33.435975 3, 0xFFFF, sum = 0
5226 12:40:33.436118 4, 0xFFFF, sum = 0
5227 12:40:33.439231 5, 0xFFFF, sum = 0
5228 12:40:33.439331 6, 0xFFFF, sum = 0
5229 12:40:33.442697 7, 0xFFFF, sum = 0
5230 12:40:33.442798 8, 0xFFFF, sum = 0
5231 12:40:33.445780 9, 0xFFFF, sum = 0
5232 12:40:33.445880 10, 0x0, sum = 1
5233 12:40:33.449159 11, 0x0, sum = 2
5234 12:40:33.449259 12, 0x0, sum = 3
5235 12:40:33.452299 13, 0x0, sum = 4
5236 12:40:33.452395 best_step = 11
5237 12:40:33.452462
5238 12:40:33.452523 ==
5239 12:40:33.455180 Dram Type= 6, Freq= 0, CH_0, rank 0
5240 12:40:33.459044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5241 12:40:33.461817 ==
5242 12:40:33.461926 RX Vref Scan: 1
5243 12:40:33.461995
5244 12:40:33.465348 RX Vref 0 -> 0, step: 1
5245 12:40:33.465455
5246 12:40:33.468868 RX Delay -61 -> 252, step: 4
5247 12:40:33.468972
5248 12:40:33.471936 Set Vref, RX VrefLevel [Byte0]: 52
5249 12:40:33.474940 [Byte1]: 49
5250 12:40:33.475044
5251 12:40:33.478864 Final RX Vref Byte 0 = 52 to rank0
5252 12:40:33.482427 Final RX Vref Byte 1 = 49 to rank0
5253 12:40:33.484893 Final RX Vref Byte 0 = 52 to rank1
5254 12:40:33.488456 Final RX Vref Byte 1 = 49 to rank1==
5255 12:40:33.491458 Dram Type= 6, Freq= 0, CH_0, rank 0
5256 12:40:33.495091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5257 12:40:33.495217 ==
5258 12:40:33.498345 DQS Delay:
5259 12:40:33.498450 DQS0 = 0, DQS1 = 0
5260 12:40:33.498540 DQM Delay:
5261 12:40:33.501335 DQM0 = 99, DQM1 = 87
5262 12:40:33.501435 DQ Delay:
5263 12:40:33.504926 DQ0 =100, DQ1 =100, DQ2 =94, DQ3 =98
5264 12:40:33.508444 DQ4 =100, DQ5 =90, DQ6 =106, DQ7 =106
5265 12:40:33.511659 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =84
5266 12:40:33.514812 DQ12 =92, DQ13 =90, DQ14 =96, DQ15 =94
5267 12:40:33.514928
5268 12:40:33.515022
5269 12:40:33.524721 [DQSOSCAuto] RK0, (LSB)MR18= 0x1812, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
5270 12:40:33.527603 CH0 RK0: MR19=505, MR18=1812
5271 12:40:33.534796 CH0_RK0: MR19=0x505, MR18=0x1812, DQSOSC=414, MR23=63, INC=63, DEC=42
5272 12:40:33.534949
5273 12:40:33.537470 ----->DramcWriteLeveling(PI) begin...
5274 12:40:33.537568 ==
5275 12:40:33.541097 Dram Type= 6, Freq= 0, CH_0, rank 1
5276 12:40:33.544210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 12:40:33.544332 ==
5278 12:40:33.547664 Write leveling (Byte 0): 35 => 35
5279 12:40:33.550472 Write leveling (Byte 1): 25 => 25
5280 12:40:33.554063 DramcWriteLeveling(PI) end<-----
5281 12:40:33.554180
5282 12:40:33.554250 ==
5283 12:40:33.557505 Dram Type= 6, Freq= 0, CH_0, rank 1
5284 12:40:33.560701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 12:40:33.560835 ==
5286 12:40:33.564011 [Gating] SW mode calibration
5287 12:40:33.570297 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5288 12:40:33.577293 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5289 12:40:33.580646 0 14 0 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
5290 12:40:33.586764 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5291 12:40:33.590497 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5292 12:40:33.593462 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5293 12:40:33.600415 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5294 12:40:33.603974 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 12:40:33.607262 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5296 12:40:33.613649 0 14 28 | B1->B0 | 3232 2a2a | 0 0 | (0 1) (0 0)
5297 12:40:33.616872 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
5298 12:40:33.620012 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5299 12:40:33.626768 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5300 12:40:33.629996 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5301 12:40:33.633020 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5302 12:40:33.639588 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 12:40:33.642959 0 15 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5304 12:40:33.646432 0 15 28 | B1->B0 | 2828 4141 | 0 0 | (1 1) (0 0)
5305 12:40:33.652941 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5306 12:40:33.656019 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5307 12:40:33.659644 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5308 12:40:33.665901 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5309 12:40:33.669285 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 12:40:33.673023 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 12:40:33.679218 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 12:40:33.682715 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5313 12:40:33.686106 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5314 12:40:33.692160 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 12:40:33.695621 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 12:40:33.698676 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 12:40:33.705612 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 12:40:33.708793 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 12:40:33.712487 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 12:40:33.718432 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 12:40:33.721679 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 12:40:33.725444 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 12:40:33.732296 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 12:40:33.735364 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 12:40:33.738254 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 12:40:33.745107 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 12:40:33.748790 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5328 12:40:33.751381 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5329 12:40:33.754656 Total UI for P1: 0, mck2ui 16
5330 12:40:33.757735 best dqsien dly found for B0: ( 1, 2, 24)
5331 12:40:33.764823 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5332 12:40:33.767636 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5333 12:40:33.771727 Total UI for P1: 0, mck2ui 16
5334 12:40:33.774913 best dqsien dly found for B1: ( 1, 3, 0)
5335 12:40:33.777473 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5336 12:40:33.781283 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5337 12:40:33.781439
5338 12:40:33.784353 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5339 12:40:33.788192 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5340 12:40:33.790943 [Gating] SW calibration Done
5341 12:40:33.791055 ==
5342 12:40:33.794436 Dram Type= 6, Freq= 0, CH_0, rank 1
5343 12:40:33.797338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5344 12:40:33.800817 ==
5345 12:40:33.800936 RX Vref Scan: 0
5346 12:40:33.801005
5347 12:40:33.804008 RX Vref 0 -> 0, step: 1
5348 12:40:33.804131
5349 12:40:33.807742 RX Delay -80 -> 252, step: 8
5350 12:40:33.810636 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5351 12:40:33.813908 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5352 12:40:33.816956 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5353 12:40:33.820419 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5354 12:40:33.823731 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5355 12:40:33.830817 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5356 12:40:33.833267 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5357 12:40:33.836590 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5358 12:40:33.840243 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5359 12:40:33.843303 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5360 12:40:33.849858 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5361 12:40:33.852915 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5362 12:40:33.856456 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5363 12:40:33.860309 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5364 12:40:33.862958 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5365 12:40:33.869847 iDelay=200, Bit 15, Center 91 (0 ~ 183) 184
5366 12:40:33.870003 ==
5367 12:40:33.872793 Dram Type= 6, Freq= 0, CH_0, rank 1
5368 12:40:33.876275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5369 12:40:33.876387 ==
5370 12:40:33.876454 DQS Delay:
5371 12:40:33.879803 DQS0 = 0, DQS1 = 0
5372 12:40:33.879925 DQM Delay:
5373 12:40:33.883153 DQM0 = 97, DQM1 = 88
5374 12:40:33.883244 DQ Delay:
5375 12:40:33.886225 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5376 12:40:33.889541 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =103
5377 12:40:33.893136 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5378 12:40:33.895804 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =91
5379 12:40:33.895911
5380 12:40:33.895977
5381 12:40:33.896078 ==
5382 12:40:33.899163 Dram Type= 6, Freq= 0, CH_0, rank 1
5383 12:40:33.902995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5384 12:40:33.906257 ==
5385 12:40:33.906370
5386 12:40:33.906438
5387 12:40:33.906497 TX Vref Scan disable
5388 12:40:33.909263 == TX Byte 0 ==
5389 12:40:33.912800 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5390 12:40:33.916437 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5391 12:40:33.919009 == TX Byte 1 ==
5392 12:40:33.922498 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5393 12:40:33.926282 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5394 12:40:33.929033 ==
5395 12:40:33.931859 Dram Type= 6, Freq= 0, CH_0, rank 1
5396 12:40:33.935581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5397 12:40:33.935704 ==
5398 12:40:33.935778
5399 12:40:33.935839
5400 12:40:33.938797 TX Vref Scan disable
5401 12:40:33.938891 == TX Byte 0 ==
5402 12:40:33.945919 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5403 12:40:33.948773 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5404 12:40:33.952325 == TX Byte 1 ==
5405 12:40:33.955622 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5406 12:40:33.958749 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5407 12:40:33.958873
5408 12:40:33.958952 [DATLAT]
5409 12:40:33.962707 Freq=933, CH0 RK1
5410 12:40:33.962817
5411 12:40:33.962893 DATLAT Default: 0xb
5412 12:40:33.965134 0, 0xFFFF, sum = 0
5413 12:40:33.968321 1, 0xFFFF, sum = 0
5414 12:40:33.968436 2, 0xFFFF, sum = 0
5415 12:40:33.971722 3, 0xFFFF, sum = 0
5416 12:40:33.971854 4, 0xFFFF, sum = 0
5417 12:40:33.975032 5, 0xFFFF, sum = 0
5418 12:40:33.975138 6, 0xFFFF, sum = 0
5419 12:40:33.978089 7, 0xFFFF, sum = 0
5420 12:40:33.978187 8, 0xFFFF, sum = 0
5421 12:40:33.982142 9, 0xFFFF, sum = 0
5422 12:40:33.982253 10, 0x0, sum = 1
5423 12:40:33.984908 11, 0x0, sum = 2
5424 12:40:33.985003 12, 0x0, sum = 3
5425 12:40:33.988770 13, 0x0, sum = 4
5426 12:40:33.988873 best_step = 11
5427 12:40:33.988942
5428 12:40:33.989004 ==
5429 12:40:33.991611 Dram Type= 6, Freq= 0, CH_0, rank 1
5430 12:40:33.995111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5431 12:40:33.998331 ==
5432 12:40:33.998444 RX Vref Scan: 0
5433 12:40:33.998511
5434 12:40:34.001389 RX Vref 0 -> 0, step: 1
5435 12:40:34.001484
5436 12:40:34.001551 RX Delay -61 -> 252, step: 4
5437 12:40:34.009294 iDelay=195, Bit 0, Center 94 (7 ~ 182) 176
5438 12:40:34.012585 iDelay=195, Bit 1, Center 100 (11 ~ 190) 180
5439 12:40:34.015759 iDelay=195, Bit 2, Center 92 (3 ~ 182) 180
5440 12:40:34.019496 iDelay=195, Bit 3, Center 96 (7 ~ 186) 180
5441 12:40:34.022288 iDelay=195, Bit 4, Center 100 (7 ~ 194) 188
5442 12:40:34.028944 iDelay=195, Bit 5, Center 86 (-5 ~ 178) 184
5443 12:40:34.032573 iDelay=195, Bit 6, Center 104 (15 ~ 194) 180
5444 12:40:34.035754 iDelay=195, Bit 7, Center 104 (15 ~ 194) 180
5445 12:40:34.039259 iDelay=195, Bit 8, Center 80 (-9 ~ 170) 180
5446 12:40:34.042352 iDelay=195, Bit 9, Center 76 (-13 ~ 166) 180
5447 12:40:34.048841 iDelay=195, Bit 10, Center 88 (-1 ~ 178) 180
5448 12:40:34.052426 iDelay=195, Bit 11, Center 80 (-9 ~ 170) 180
5449 12:40:34.055400 iDelay=195, Bit 12, Center 92 (3 ~ 182) 180
5450 12:40:34.058993 iDelay=195, Bit 13, Center 94 (7 ~ 182) 176
5451 12:40:34.061798 iDelay=195, Bit 14, Center 96 (7 ~ 186) 180
5452 12:40:34.065567 iDelay=195, Bit 15, Center 94 (7 ~ 182) 176
5453 12:40:34.068664 ==
5454 12:40:34.072168 Dram Type= 6, Freq= 0, CH_0, rank 1
5455 12:40:34.075476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5456 12:40:34.075600 ==
5457 12:40:34.075675 DQS Delay:
5458 12:40:34.078271 DQS0 = 0, DQS1 = 0
5459 12:40:34.078367 DQM Delay:
5460 12:40:34.081974 DQM0 = 97, DQM1 = 87
5461 12:40:34.082089 DQ Delay:
5462 12:40:34.085385 DQ0 =94, DQ1 =100, DQ2 =92, DQ3 =96
5463 12:40:34.088670 DQ4 =100, DQ5 =86, DQ6 =104, DQ7 =104
5464 12:40:34.091693 DQ8 =80, DQ9 =76, DQ10 =88, DQ11 =80
5465 12:40:34.095071 DQ12 =92, DQ13 =94, DQ14 =96, DQ15 =94
5466 12:40:34.095185
5467 12:40:34.095254
5468 12:40:34.101492 [DQSOSCAuto] RK1, (LSB)MR18= 0x1411, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5469 12:40:34.105079 CH0 RK1: MR19=505, MR18=1411
5470 12:40:34.111224 CH0_RK1: MR19=0x505, MR18=0x1411, DQSOSC=415, MR23=63, INC=62, DEC=41
5471 12:40:34.114851 [RxdqsGatingPostProcess] freq 933
5472 12:40:34.121278 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5473 12:40:34.124618 best DQS0 dly(2T, 0.5T) = (0, 10)
5474 12:40:34.127873 best DQS1 dly(2T, 0.5T) = (0, 11)
5475 12:40:34.131272 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5476 12:40:34.134423 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5477 12:40:34.137655 best DQS0 dly(2T, 0.5T) = (0, 10)
5478 12:40:34.137771 best DQS1 dly(2T, 0.5T) = (0, 11)
5479 12:40:34.141136 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5480 12:40:34.144447 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5481 12:40:34.147974 Pre-setting of DQS Precalculation
5482 12:40:34.154143 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5483 12:40:34.154285 ==
5484 12:40:34.157482 Dram Type= 6, Freq= 0, CH_1, rank 0
5485 12:40:34.160637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5486 12:40:34.160754 ==
5487 12:40:34.167619 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5488 12:40:34.174403 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5489 12:40:34.177101 [CA 0] Center 36 (6~67) winsize 62
5490 12:40:34.180902 [CA 1] Center 36 (6~67) winsize 62
5491 12:40:34.183834 [CA 2] Center 34 (4~65) winsize 62
5492 12:40:34.187109 [CA 3] Center 33 (3~64) winsize 62
5493 12:40:34.190189 [CA 4] Center 34 (4~65) winsize 62
5494 12:40:34.194257 [CA 5] Center 33 (3~64) winsize 62
5495 12:40:34.194385
5496 12:40:34.197421 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5497 12:40:34.197523
5498 12:40:34.201184 [CATrainingPosCal] consider 1 rank data
5499 12:40:34.203409 u2DelayCellTimex100 = 270/100 ps
5500 12:40:34.206945 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5501 12:40:34.210323 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5502 12:40:34.213700 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5503 12:40:34.216816 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5504 12:40:34.219890 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5505 12:40:34.223575 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5506 12:40:34.227114
5507 12:40:34.229901 CA PerBit enable=1, Macro0, CA PI delay=33
5508 12:40:34.230011
5509 12:40:34.233069 [CBTSetCACLKResult] CA Dly = 33
5510 12:40:34.233175 CS Dly: 4 (0~35)
5511 12:40:34.233246 ==
5512 12:40:34.236904 Dram Type= 6, Freq= 0, CH_1, rank 1
5513 12:40:34.239747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5514 12:40:34.239848 ==
5515 12:40:34.246447 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5516 12:40:34.252831 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5517 12:40:34.256476 [CA 0] Center 36 (6~67) winsize 62
5518 12:40:34.259725 [CA 1] Center 36 (6~67) winsize 62
5519 12:40:34.262899 [CA 2] Center 34 (4~65) winsize 62
5520 12:40:34.266847 [CA 3] Center 33 (3~64) winsize 62
5521 12:40:34.269481 [CA 4] Center 34 (3~65) winsize 63
5522 12:40:34.273102 [CA 5] Center 33 (3~64) winsize 62
5523 12:40:34.273230
5524 12:40:34.276491 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5525 12:40:34.276603
5526 12:40:34.279959 [CATrainingPosCal] consider 2 rank data
5527 12:40:34.282875 u2DelayCellTimex100 = 270/100 ps
5528 12:40:34.286060 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5529 12:40:34.289644 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5530 12:40:34.292689 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5531 12:40:34.299112 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5532 12:40:34.302139 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5533 12:40:34.305759 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5534 12:40:34.305887
5535 12:40:34.308689 CA PerBit enable=1, Macro0, CA PI delay=33
5536 12:40:34.308788
5537 12:40:34.312175 [CBTSetCACLKResult] CA Dly = 33
5538 12:40:34.312278 CS Dly: 5 (0~38)
5539 12:40:34.312347
5540 12:40:34.315535 ----->DramcWriteLeveling(PI) begin...
5541 12:40:34.315628 ==
5542 12:40:34.318965 Dram Type= 6, Freq= 0, CH_1, rank 0
5543 12:40:34.325887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5544 12:40:34.326034 ==
5545 12:40:34.329264 Write leveling (Byte 0): 29 => 29
5546 12:40:34.331969 Write leveling (Byte 1): 29 => 29
5547 12:40:34.335218 DramcWriteLeveling(PI) end<-----
5548 12:40:34.335337
5549 12:40:34.335408 ==
5550 12:40:34.339027 Dram Type= 6, Freq= 0, CH_1, rank 0
5551 12:40:34.341804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5552 12:40:34.341905 ==
5553 12:40:34.345767 [Gating] SW mode calibration
5554 12:40:34.351954 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5555 12:40:34.358492 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5556 12:40:34.361575 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5557 12:40:34.365516 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5558 12:40:34.371701 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5559 12:40:34.374941 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 12:40:34.377958 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 12:40:34.384387 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 12:40:34.388253 0 14 24 | B1->B0 | 3434 3030 | 1 0 | (0 0) (0 0)
5563 12:40:34.390854 0 14 28 | B1->B0 | 2828 2323 | 1 0 | (1 0) (1 0)
5564 12:40:34.398224 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5565 12:40:34.401149 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5566 12:40:34.404201 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 12:40:34.410659 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 12:40:34.414151 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 12:40:34.417653 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 12:40:34.423814 0 15 24 | B1->B0 | 2626 2828 | 0 0 | (0 0) (0 0)
5571 12:40:34.427463 0 15 28 | B1->B0 | 3b3b 4242 | 0 0 | (0 0) (0 0)
5572 12:40:34.430901 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5573 12:40:34.437439 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 12:40:34.440209 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 12:40:34.444026 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 12:40:34.450534 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 12:40:34.453643 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 12:40:34.457117 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5579 12:40:34.463402 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5580 12:40:34.466749 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 12:40:34.470478 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 12:40:34.477200 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 12:40:34.479830 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 12:40:34.483563 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 12:40:34.490008 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 12:40:34.493160 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 12:40:34.496862 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 12:40:34.503238 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 12:40:34.506078 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 12:40:34.509479 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 12:40:34.516155 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 12:40:34.519520 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 12:40:34.522926 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 12:40:34.529173 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5595 12:40:34.532570 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 12:40:34.535855 Total UI for P1: 0, mck2ui 16
5597 12:40:34.539818 best dqsien dly found for B0: ( 1, 2, 24)
5598 12:40:34.542727 Total UI for P1: 0, mck2ui 16
5599 12:40:34.545695 best dqsien dly found for B1: ( 1, 2, 24)
5600 12:40:34.548911 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5601 12:40:34.552683 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5602 12:40:34.552830
5603 12:40:34.555746 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5604 12:40:34.558882 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5605 12:40:34.561995 [Gating] SW calibration Done
5606 12:40:34.562133 ==
5607 12:40:34.565448 Dram Type= 6, Freq= 0, CH_1, rank 0
5608 12:40:34.572316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5609 12:40:34.572507 ==
5610 12:40:34.572622 RX Vref Scan: 0
5611 12:40:34.572716
5612 12:40:34.575444 RX Vref 0 -> 0, step: 1
5613 12:40:34.575567
5614 12:40:34.578586 RX Delay -80 -> 252, step: 8
5615 12:40:34.581964 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5616 12:40:34.585382 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5617 12:40:34.588404 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5618 12:40:34.592380 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5619 12:40:34.595315 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5620 12:40:34.601802 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5621 12:40:34.605468 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5622 12:40:34.608486 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5623 12:40:34.611581 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5624 12:40:34.615447 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5625 12:40:34.621531 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5626 12:40:34.624995 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5627 12:40:34.628156 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5628 12:40:34.631813 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5629 12:40:34.634825 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5630 12:40:34.641482 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5631 12:40:34.641664 ==
5632 12:40:34.644867 Dram Type= 6, Freq= 0, CH_1, rank 0
5633 12:40:34.647874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5634 12:40:34.648008 ==
5635 12:40:34.648152 DQS Delay:
5636 12:40:34.651466 DQS0 = 0, DQS1 = 0
5637 12:40:34.651592 DQM Delay:
5638 12:40:34.654491 DQM0 = 99, DQM1 = 95
5639 12:40:34.654612 DQ Delay:
5640 12:40:34.657664 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5641 12:40:34.660871 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
5642 12:40:34.664367 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5643 12:40:34.667472 DQ12 =99, DQ13 =103, DQ14 =99, DQ15 =103
5644 12:40:34.667627
5645 12:40:34.667730
5646 12:40:34.667821 ==
5647 12:40:34.670831 Dram Type= 6, Freq= 0, CH_1, rank 0
5648 12:40:34.674045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5649 12:40:34.677269 ==
5650 12:40:34.677417
5651 12:40:34.677520
5652 12:40:34.677613 TX Vref Scan disable
5653 12:40:34.681291 == TX Byte 0 ==
5654 12:40:34.684021 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5655 12:40:34.687350 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5656 12:40:34.690850 == TX Byte 1 ==
5657 12:40:34.694927 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5658 12:40:34.697220 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5659 12:40:34.700582 ==
5660 12:40:34.703629 Dram Type= 6, Freq= 0, CH_1, rank 0
5661 12:40:34.707214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5662 12:40:34.707364 ==
5663 12:40:34.707468
5664 12:40:34.707559
5665 12:40:34.710851 TX Vref Scan disable
5666 12:40:34.710977 == TX Byte 0 ==
5667 12:40:34.717682 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5668 12:40:34.720910 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5669 12:40:34.721055 == TX Byte 1 ==
5670 12:40:34.726540 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5671 12:40:34.730143 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5672 12:40:34.730287
5673 12:40:34.730390 [DATLAT]
5674 12:40:34.733065 Freq=933, CH1 RK0
5675 12:40:34.733182
5676 12:40:34.733278 DATLAT Default: 0xd
5677 12:40:34.736724 0, 0xFFFF, sum = 0
5678 12:40:34.739751 1, 0xFFFF, sum = 0
5679 12:40:34.739885 2, 0xFFFF, sum = 0
5680 12:40:34.743705 3, 0xFFFF, sum = 0
5681 12:40:34.743848 4, 0xFFFF, sum = 0
5682 12:40:34.746837 5, 0xFFFF, sum = 0
5683 12:40:34.746964 6, 0xFFFF, sum = 0
5684 12:40:34.749510 7, 0xFFFF, sum = 0
5685 12:40:34.749629 8, 0xFFFF, sum = 0
5686 12:40:34.753048 9, 0xFFFF, sum = 0
5687 12:40:34.753179 10, 0x0, sum = 1
5688 12:40:34.756466 11, 0x0, sum = 2
5689 12:40:34.756590 12, 0x0, sum = 3
5690 12:40:34.759818 13, 0x0, sum = 4
5691 12:40:34.759944 best_step = 11
5692 12:40:34.760062
5693 12:40:34.760170 ==
5694 12:40:34.762980 Dram Type= 6, Freq= 0, CH_1, rank 0
5695 12:40:34.766064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5696 12:40:34.769165 ==
5697 12:40:34.769311 RX Vref Scan: 1
5698 12:40:34.769417
5699 12:40:34.772844 RX Vref 0 -> 0, step: 1
5700 12:40:34.772973
5701 12:40:34.776114 RX Delay -53 -> 252, step: 4
5702 12:40:34.776243
5703 12:40:34.780061 Set Vref, RX VrefLevel [Byte0]: 51
5704 12:40:34.782886 [Byte1]: 50
5705 12:40:34.783020
5706 12:40:34.786020 Final RX Vref Byte 0 = 51 to rank0
5707 12:40:34.788915 Final RX Vref Byte 1 = 50 to rank0
5708 12:40:34.792267 Final RX Vref Byte 0 = 51 to rank1
5709 12:40:34.795570 Final RX Vref Byte 1 = 50 to rank1==
5710 12:40:34.799152 Dram Type= 6, Freq= 0, CH_1, rank 0
5711 12:40:34.802049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5712 12:40:34.802194 ==
5713 12:40:34.805782 DQS Delay:
5714 12:40:34.805911 DQS0 = 0, DQS1 = 0
5715 12:40:34.806008 DQM Delay:
5716 12:40:34.809360 DQM0 = 98, DQM1 = 94
5717 12:40:34.809481 DQ Delay:
5718 12:40:34.811964 DQ0 =104, DQ1 =92, DQ2 =86, DQ3 =100
5719 12:40:34.815840 DQ4 =96, DQ5 =106, DQ6 =108, DQ7 =92
5720 12:40:34.819434 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =88
5721 12:40:34.822251 DQ12 =102, DQ13 =102, DQ14 =100, DQ15 =104
5722 12:40:34.822388
5723 12:40:34.822486
5724 12:40:34.832184 [DQSOSCAuto] RK0, (LSB)MR18= 0x515, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 420 ps
5725 12:40:34.835070 CH1 RK0: MR19=505, MR18=515
5726 12:40:34.842350 CH1_RK0: MR19=0x505, MR18=0x515, DQSOSC=415, MR23=63, INC=62, DEC=41
5727 12:40:34.842539
5728 12:40:34.845638 ----->DramcWriteLeveling(PI) begin...
5729 12:40:34.845773 ==
5730 12:40:34.848341 Dram Type= 6, Freq= 0, CH_1, rank 1
5731 12:40:34.852002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 12:40:34.852171 ==
5733 12:40:34.855142 Write leveling (Byte 0): 27 => 27
5734 12:40:34.858351 Write leveling (Byte 1): 28 => 28
5735 12:40:34.862388 DramcWriteLeveling(PI) end<-----
5736 12:40:34.862535
5737 12:40:34.862637 ==
5738 12:40:34.865034 Dram Type= 6, Freq= 0, CH_1, rank 1
5739 12:40:34.868744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 12:40:34.868893 ==
5741 12:40:34.871660 [Gating] SW mode calibration
5742 12:40:34.878042 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5743 12:40:34.884776 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5744 12:40:34.888003 0 14 0 | B1->B0 | 3433 3434 | 1 1 | (0 0) (1 1)
5745 12:40:34.891471 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5746 12:40:34.897915 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5747 12:40:34.901214 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5748 12:40:34.904708 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 12:40:34.910873 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 12:40:34.914393 0 14 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
5751 12:40:34.918017 0 14 28 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
5752 12:40:34.924142 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5753 12:40:34.927377 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5754 12:40:34.930956 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5755 12:40:34.937658 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5756 12:40:34.940516 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5757 12:40:34.944084 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 12:40:34.950452 0 15 24 | B1->B0 | 2424 3433 | 0 1 | (0 0) (0 0)
5759 12:40:34.953620 0 15 28 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5760 12:40:34.957495 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5761 12:40:34.963667 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5762 12:40:34.966817 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5763 12:40:34.970070 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 12:40:34.976710 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 12:40:34.980131 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 12:40:34.983530 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 12:40:34.990384 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 12:40:34.993349 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5769 12:40:34.996589 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 12:40:35.003047 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 12:40:35.006499 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 12:40:35.009516 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 12:40:35.016398 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 12:40:35.020160 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 12:40:35.023236 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 12:40:35.029652 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 12:40:35.033432 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 12:40:35.036756 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 12:40:35.042907 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 12:40:35.046852 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 12:40:35.049192 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 12:40:35.055768 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5783 12:40:35.059021 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5784 12:40:35.062701 Total UI for P1: 0, mck2ui 16
5785 12:40:35.065553 best dqsien dly found for B0: ( 1, 2, 24)
5786 12:40:35.069000 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5787 12:40:35.072483 Total UI for P1: 0, mck2ui 16
5788 12:40:35.075851 best dqsien dly found for B1: ( 1, 2, 30)
5789 12:40:35.078766 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5790 12:40:35.085445 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5791 12:40:35.085627
5792 12:40:35.088609 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5793 12:40:35.091905 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5794 12:40:35.095600 [Gating] SW calibration Done
5795 12:40:35.095751 ==
5796 12:40:35.099180 Dram Type= 6, Freq= 0, CH_1, rank 1
5797 12:40:35.102097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5798 12:40:35.102237 ==
5799 12:40:35.105377 RX Vref Scan: 0
5800 12:40:35.105502
5801 12:40:35.105603 RX Vref 0 -> 0, step: 1
5802 12:40:35.105697
5803 12:40:35.108398 RX Delay -80 -> 252, step: 8
5804 12:40:35.111606 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5805 12:40:35.118392 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5806 12:40:35.121393 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5807 12:40:35.125295 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5808 12:40:35.128239 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5809 12:40:35.131773 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5810 12:40:35.134706 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5811 12:40:35.141757 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5812 12:40:35.145454 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5813 12:40:35.148181 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5814 12:40:35.151496 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5815 12:40:35.154649 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5816 12:40:35.158162 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5817 12:40:35.164594 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5818 12:40:35.168236 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5819 12:40:35.171204 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5820 12:40:35.171320 ==
5821 12:40:35.174638 Dram Type= 6, Freq= 0, CH_1, rank 1
5822 12:40:35.177630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5823 12:40:35.177736 ==
5824 12:40:35.181168 DQS Delay:
5825 12:40:35.181268 DQS0 = 0, DQS1 = 0
5826 12:40:35.184241 DQM Delay:
5827 12:40:35.184332 DQM0 = 97, DQM1 = 94
5828 12:40:35.187455 DQ Delay:
5829 12:40:35.187555 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5830 12:40:35.190786 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5831 12:40:35.194267 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =87
5832 12:40:35.201628 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5833 12:40:35.201774
5834 12:40:35.201845
5835 12:40:35.201911 ==
5836 12:40:35.205176 Dram Type= 6, Freq= 0, CH_1, rank 1
5837 12:40:35.207978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5838 12:40:35.208129 ==
5839 12:40:35.208200
5840 12:40:35.208263
5841 12:40:35.211064 TX Vref Scan disable
5842 12:40:35.211158 == TX Byte 0 ==
5843 12:40:35.217701 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5844 12:40:35.220762 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5845 12:40:35.220875 == TX Byte 1 ==
5846 12:40:35.227194 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5847 12:40:35.230793 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5848 12:40:35.230922 ==
5849 12:40:35.234326 Dram Type= 6, Freq= 0, CH_1, rank 1
5850 12:40:35.237657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5851 12:40:35.237769 ==
5852 12:40:35.237841
5853 12:40:35.240267
5854 12:40:35.240354 TX Vref Scan disable
5855 12:40:35.243778 == TX Byte 0 ==
5856 12:40:35.247413 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5857 12:40:35.250377 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5858 12:40:35.253609 == TX Byte 1 ==
5859 12:40:35.256724 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5860 12:40:35.264206 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5861 12:40:35.264360
5862 12:40:35.264432 [DATLAT]
5863 12:40:35.264494 Freq=933, CH1 RK1
5864 12:40:35.264554
5865 12:40:35.267079 DATLAT Default: 0xb
5866 12:40:35.267171 0, 0xFFFF, sum = 0
5867 12:40:35.270189 1, 0xFFFF, sum = 0
5868 12:40:35.273517 2, 0xFFFF, sum = 0
5869 12:40:35.273637 3, 0xFFFF, sum = 0
5870 12:40:35.276973 4, 0xFFFF, sum = 0
5871 12:40:35.277086 5, 0xFFFF, sum = 0
5872 12:40:35.279841 6, 0xFFFF, sum = 0
5873 12:40:35.279967 7, 0xFFFF, sum = 0
5874 12:40:35.283898 8, 0xFFFF, sum = 0
5875 12:40:35.284072 9, 0xFFFF, sum = 0
5876 12:40:35.286753 10, 0x0, sum = 1
5877 12:40:35.286849 11, 0x0, sum = 2
5878 12:40:35.290026 12, 0x0, sum = 3
5879 12:40:35.290125 13, 0x0, sum = 4
5880 12:40:35.290261 best_step = 11
5881 12:40:35.293559
5882 12:40:35.293663 ==
5883 12:40:35.296196 Dram Type= 6, Freq= 0, CH_1, rank 1
5884 12:40:35.299660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5885 12:40:35.299770 ==
5886 12:40:35.299841 RX Vref Scan: 0
5887 12:40:35.299903
5888 12:40:35.302948 RX Vref 0 -> 0, step: 1
5889 12:40:35.303045
5890 12:40:35.306455 RX Delay -61 -> 252, step: 4
5891 12:40:35.312935 iDelay=203, Bit 0, Center 102 (11 ~ 194) 184
5892 12:40:35.316476 iDelay=203, Bit 1, Center 94 (-1 ~ 190) 192
5893 12:40:35.319411 iDelay=203, Bit 2, Center 86 (-5 ~ 178) 184
5894 12:40:35.323200 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5895 12:40:35.326057 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5896 12:40:35.329712 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5897 12:40:35.335811 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5898 12:40:35.339193 iDelay=203, Bit 7, Center 94 (-1 ~ 190) 192
5899 12:40:35.342831 iDelay=203, Bit 8, Center 80 (-9 ~ 170) 180
5900 12:40:35.346074 iDelay=203, Bit 9, Center 82 (-9 ~ 174) 184
5901 12:40:35.349440 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5902 12:40:35.355793 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5903 12:40:35.359648 iDelay=203, Bit 12, Center 100 (11 ~ 190) 180
5904 12:40:35.362339 iDelay=203, Bit 13, Center 100 (11 ~ 190) 180
5905 12:40:35.365940 iDelay=203, Bit 14, Center 96 (7 ~ 186) 180
5906 12:40:35.369110 iDelay=203, Bit 15, Center 102 (11 ~ 194) 184
5907 12:40:35.372439 ==
5908 12:40:35.375315 Dram Type= 6, Freq= 0, CH_1, rank 1
5909 12:40:35.378571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5910 12:40:35.378693 ==
5911 12:40:35.378786 DQS Delay:
5912 12:40:35.383026 DQS0 = 0, DQS1 = 0
5913 12:40:35.383142 DQM Delay:
5914 12:40:35.385319 DQM0 = 97, DQM1 = 92
5915 12:40:35.385415 DQ Delay:
5916 12:40:35.389211 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =94
5917 12:40:35.392324 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5918 12:40:35.395165 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =84
5919 12:40:35.398608 DQ12 =100, DQ13 =100, DQ14 =96, DQ15 =102
5920 12:40:35.398730
5921 12:40:35.398799
5922 12:40:35.408196 [DQSOSCAuto] RK1, (LSB)MR18= 0x1027, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 416 ps
5923 12:40:35.408349 CH1 RK1: MR19=505, MR18=1027
5924 12:40:35.414850 CH1_RK1: MR19=0x505, MR18=0x1027, DQSOSC=409, MR23=63, INC=64, DEC=43
5925 12:40:35.418534 [RxdqsGatingPostProcess] freq 933
5926 12:40:35.424874 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5927 12:40:35.428068 best DQS0 dly(2T, 0.5T) = (0, 10)
5928 12:40:35.431156 best DQS1 dly(2T, 0.5T) = (0, 10)
5929 12:40:35.434794 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5930 12:40:35.438286 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5931 12:40:35.441276 best DQS0 dly(2T, 0.5T) = (0, 10)
5932 12:40:35.444718 best DQS1 dly(2T, 0.5T) = (0, 10)
5933 12:40:35.448437 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5934 12:40:35.451384 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5935 12:40:35.451505 Pre-setting of DQS Precalculation
5936 12:40:35.457660 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5937 12:40:35.465004 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5938 12:40:35.470680 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5939 12:40:35.470843
5940 12:40:35.470940
5941 12:40:35.474143 [Calibration Summary] 1866 Mbps
5942 12:40:35.477509 CH 0, Rank 0
5943 12:40:35.477631 SW Impedance : PASS
5944 12:40:35.480830 DUTY Scan : NO K
5945 12:40:35.483903 ZQ Calibration : PASS
5946 12:40:35.484018 Jitter Meter : NO K
5947 12:40:35.487410 CBT Training : PASS
5948 12:40:35.490519 Write leveling : PASS
5949 12:40:35.490640 RX DQS gating : PASS
5950 12:40:35.494012 RX DQ/DQS(RDDQC) : PASS
5951 12:40:35.496857 TX DQ/DQS : PASS
5952 12:40:35.496970 RX DATLAT : PASS
5953 12:40:35.500815 RX DQ/DQS(Engine): PASS
5954 12:40:35.503609 TX OE : NO K
5955 12:40:35.503725 All Pass.
5956 12:40:35.503798
5957 12:40:35.503862 CH 0, Rank 1
5958 12:40:35.507616 SW Impedance : PASS
5959 12:40:35.510132 DUTY Scan : NO K
5960 12:40:35.510239 ZQ Calibration : PASS
5961 12:40:35.513422 Jitter Meter : NO K
5962 12:40:35.517210 CBT Training : PASS
5963 12:40:35.517335 Write leveling : PASS
5964 12:40:35.520407 RX DQS gating : PASS
5965 12:40:35.520508 RX DQ/DQS(RDDQC) : PASS
5966 12:40:35.523824 TX DQ/DQS : PASS
5967 12:40:35.527272 RX DATLAT : PASS
5968 12:40:35.527383 RX DQ/DQS(Engine): PASS
5969 12:40:35.530034 TX OE : NO K
5970 12:40:35.530133 All Pass.
5971 12:40:35.530225
5972 12:40:35.533459 CH 1, Rank 0
5973 12:40:35.533571 SW Impedance : PASS
5974 12:40:35.536857 DUTY Scan : NO K
5975 12:40:35.540316 ZQ Calibration : PASS
5976 12:40:35.540427 Jitter Meter : NO K
5977 12:40:35.543381 CBT Training : PASS
5978 12:40:35.546684 Write leveling : PASS
5979 12:40:35.546808 RX DQS gating : PASS
5980 12:40:35.549883 RX DQ/DQS(RDDQC) : PASS
5981 12:40:35.553047 TX DQ/DQS : PASS
5982 12:40:35.553159 RX DATLAT : PASS
5983 12:40:35.556780 RX DQ/DQS(Engine): PASS
5984 12:40:35.559694 TX OE : NO K
5985 12:40:35.559803 All Pass.
5986 12:40:35.559915
5987 12:40:35.560017 CH 1, Rank 1
5988 12:40:35.562962 SW Impedance : PASS
5989 12:40:35.566105 DUTY Scan : NO K
5990 12:40:35.566224 ZQ Calibration : PASS
5991 12:40:35.569337 Jitter Meter : NO K
5992 12:40:35.572855 CBT Training : PASS
5993 12:40:35.572976 Write leveling : PASS
5994 12:40:35.576369 RX DQS gating : PASS
5995 12:40:35.579284 RX DQ/DQS(RDDQC) : PASS
5996 12:40:35.579397 TX DQ/DQS : PASS
5997 12:40:35.582483 RX DATLAT : PASS
5998 12:40:35.585948 RX DQ/DQS(Engine): PASS
5999 12:40:35.586060 TX OE : NO K
6000 12:40:35.589875 All Pass.
6001 12:40:35.589984
6002 12:40:35.590054 DramC Write-DBI off
6003 12:40:35.592237 PER_BANK_REFRESH: Hybrid Mode
6004 12:40:35.592327 TX_TRACKING: ON
6005 12:40:35.602509 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6006 12:40:35.605838 [FAST_K] Save calibration result to emmc
6007 12:40:35.609346 dramc_set_vcore_voltage set vcore to 650000
6008 12:40:35.611953 Read voltage for 400, 6
6009 12:40:35.612105 Vio18 = 0
6010 12:40:35.615616 Vcore = 650000
6011 12:40:35.615728 Vdram = 0
6012 12:40:35.615797 Vddq = 0
6013 12:40:35.618874 Vmddr = 0
6014 12:40:35.621947 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6015 12:40:35.628521 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6016 12:40:35.628671 MEM_TYPE=3, freq_sel=20
6017 12:40:35.631941 sv_algorithm_assistance_LP4_800
6018 12:40:35.638873 ============ PULL DRAM RESETB DOWN ============
6019 12:40:35.641597 ========== PULL DRAM RESETB DOWN end =========
6020 12:40:35.645576 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6021 12:40:35.648418 ===================================
6022 12:40:35.651902 LPDDR4 DRAM CONFIGURATION
6023 12:40:35.655015 ===================================
6024 12:40:35.658345 EX_ROW_EN[0] = 0x0
6025 12:40:35.658466 EX_ROW_EN[1] = 0x0
6026 12:40:35.661809 LP4Y_EN = 0x0
6027 12:40:35.661920 WORK_FSP = 0x0
6028 12:40:35.664900 WL = 0x2
6029 12:40:35.665003 RL = 0x2
6030 12:40:35.668602 BL = 0x2
6031 12:40:35.668719 RPST = 0x0
6032 12:40:35.671433 RD_PRE = 0x0
6033 12:40:35.671535 WR_PRE = 0x1
6034 12:40:35.674642 WR_PST = 0x0
6035 12:40:35.674750 DBI_WR = 0x0
6036 12:40:35.678264 DBI_RD = 0x0
6037 12:40:35.678403 OTF = 0x1
6038 12:40:35.681688 ===================================
6039 12:40:35.685262 ===================================
6040 12:40:35.687937 ANA top config
6041 12:40:35.691844 ===================================
6042 12:40:35.694615 DLL_ASYNC_EN = 0
6043 12:40:35.694732 ALL_SLAVE_EN = 1
6044 12:40:35.697676 NEW_RANK_MODE = 1
6045 12:40:35.700916 DLL_IDLE_MODE = 1
6046 12:40:35.704541 LP45_APHY_COMB_EN = 1
6047 12:40:35.707721 TX_ODT_DIS = 1
6048 12:40:35.707838 NEW_8X_MODE = 1
6049 12:40:35.710968 ===================================
6050 12:40:35.714146 ===================================
6051 12:40:35.717717 data_rate = 800
6052 12:40:35.720811 CKR = 1
6053 12:40:35.723871 DQ_P2S_RATIO = 4
6054 12:40:35.727492 ===================================
6055 12:40:35.731361 CA_P2S_RATIO = 4
6056 12:40:35.734557 DQ_CA_OPEN = 0
6057 12:40:35.734671 DQ_SEMI_OPEN = 1
6058 12:40:35.737168 CA_SEMI_OPEN = 1
6059 12:40:35.740503 CA_FULL_RATE = 0
6060 12:40:35.743955 DQ_CKDIV4_EN = 0
6061 12:40:35.747054 CA_CKDIV4_EN = 1
6062 12:40:35.750907 CA_PREDIV_EN = 0
6063 12:40:35.751075 PH8_DLY = 0
6064 12:40:35.754300 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6065 12:40:35.757064 DQ_AAMCK_DIV = 0
6066 12:40:35.760670 CA_AAMCK_DIV = 0
6067 12:40:35.763249 CA_ADMCK_DIV = 4
6068 12:40:35.766935 DQ_TRACK_CA_EN = 0
6069 12:40:35.770881 CA_PICK = 800
6070 12:40:35.771015 CA_MCKIO = 400
6071 12:40:35.774175 MCKIO_SEMI = 400
6072 12:40:35.776756 PLL_FREQ = 3016
6073 12:40:35.780013 DQ_UI_PI_RATIO = 32
6074 12:40:35.783617 CA_UI_PI_RATIO = 32
6075 12:40:35.786564 ===================================
6076 12:40:35.790347 ===================================
6077 12:40:35.793179 memory_type:LPDDR4
6078 12:40:35.793289 GP_NUM : 10
6079 12:40:35.796575 SRAM_EN : 1
6080 12:40:35.800083 MD32_EN : 0
6081 12:40:35.803039 ===================================
6082 12:40:35.803154 [ANA_INIT] >>>>>>>>>>>>>>
6083 12:40:35.806555 <<<<<< [CONFIGURE PHASE]: ANA_TX
6084 12:40:35.809613 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6085 12:40:35.813296 ===================================
6086 12:40:35.816478 data_rate = 800,PCW = 0X7400
6087 12:40:35.819458 ===================================
6088 12:40:35.822425 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6089 12:40:35.829225 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6090 12:40:35.839154 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6091 12:40:35.845626 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6092 12:40:35.848981 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6093 12:40:35.852168 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6094 12:40:35.852284 [ANA_INIT] flow start
6095 12:40:35.855853 [ANA_INIT] PLL >>>>>>>>
6096 12:40:35.859124 [ANA_INIT] PLL <<<<<<<<
6097 12:40:35.859239 [ANA_INIT] MIDPI >>>>>>>>
6098 12:40:35.862234 [ANA_INIT] MIDPI <<<<<<<<
6099 12:40:35.865462 [ANA_INIT] DLL >>>>>>>>
6100 12:40:35.865572 [ANA_INIT] flow end
6101 12:40:35.872468 ============ LP4 DIFF to SE enter ============
6102 12:40:35.875332 ============ LP4 DIFF to SE exit ============
6103 12:40:35.878760 [ANA_INIT] <<<<<<<<<<<<<
6104 12:40:35.882021 [Flow] Enable top DCM control >>>>>
6105 12:40:35.885093 [Flow] Enable top DCM control <<<<<
6106 12:40:35.888958 Enable DLL master slave shuffle
6107 12:40:35.891954 ==============================================================
6108 12:40:35.895180 Gating Mode config
6109 12:40:35.898415 ==============================================================
6110 12:40:35.901626 Config description:
6111 12:40:35.911349 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6112 12:40:35.917955 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6113 12:40:35.921580 SELPH_MODE 0: By rank 1: By Phase
6114 12:40:35.928089 ==============================================================
6115 12:40:35.931067 GAT_TRACK_EN = 0
6116 12:40:35.934710 RX_GATING_MODE = 2
6117 12:40:35.937815 RX_GATING_TRACK_MODE = 2
6118 12:40:35.941227 SELPH_MODE = 1
6119 12:40:35.944400 PICG_EARLY_EN = 1
6120 12:40:35.948391 VALID_LAT_VALUE = 1
6121 12:40:35.951188 ==============================================================
6122 12:40:35.953793 Enter into Gating configuration >>>>
6123 12:40:35.957546 Exit from Gating configuration <<<<
6124 12:40:35.961026 Enter into DVFS_PRE_config >>>>>
6125 12:40:35.974154 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6126 12:40:35.977220 Exit from DVFS_PRE_config <<<<<
6127 12:40:35.981049 Enter into PICG configuration >>>>
6128 12:40:35.981183 Exit from PICG configuration <<<<
6129 12:40:35.983820 [RX_INPUT] configuration >>>>>
6130 12:40:35.987034 [RX_INPUT] configuration <<<<<
6131 12:40:35.993947 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6132 12:40:35.997308 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6133 12:40:36.003664 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6134 12:40:36.010046 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6135 12:40:36.016642 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6136 12:40:36.023432 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6137 12:40:36.026877 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6138 12:40:36.030119 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6139 12:40:36.037099 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6140 12:40:36.039747 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6141 12:40:36.042904 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6142 12:40:36.046705 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6143 12:40:36.049569 ===================================
6144 12:40:36.052739 LPDDR4 DRAM CONFIGURATION
6145 12:40:36.055980 ===================================
6146 12:40:36.059467 EX_ROW_EN[0] = 0x0
6147 12:40:36.059585 EX_ROW_EN[1] = 0x0
6148 12:40:36.063311 LP4Y_EN = 0x0
6149 12:40:36.063421 WORK_FSP = 0x0
6150 12:40:36.065810 WL = 0x2
6151 12:40:36.065904 RL = 0x2
6152 12:40:36.069208 BL = 0x2
6153 12:40:36.072545 RPST = 0x0
6154 12:40:36.072654 RD_PRE = 0x0
6155 12:40:36.076094 WR_PRE = 0x1
6156 12:40:36.076188 WR_PST = 0x0
6157 12:40:36.079474 DBI_WR = 0x0
6158 12:40:36.079568 DBI_RD = 0x0
6159 12:40:36.083091 OTF = 0x1
6160 12:40:36.086344 ===================================
6161 12:40:36.089037 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6162 12:40:36.092316 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6163 12:40:36.099159 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6164 12:40:36.099292 ===================================
6165 12:40:36.102477 LPDDR4 DRAM CONFIGURATION
6166 12:40:36.105545 ===================================
6167 12:40:36.108718 EX_ROW_EN[0] = 0x10
6168 12:40:36.108804 EX_ROW_EN[1] = 0x0
6169 12:40:36.112226 LP4Y_EN = 0x0
6170 12:40:36.112307 WORK_FSP = 0x0
6171 12:40:36.115649 WL = 0x2
6172 12:40:36.118779 RL = 0x2
6173 12:40:36.118862 BL = 0x2
6174 12:40:36.122361 RPST = 0x0
6175 12:40:36.122440 RD_PRE = 0x0
6176 12:40:36.125306 WR_PRE = 0x1
6177 12:40:36.125384 WR_PST = 0x0
6178 12:40:36.128567 DBI_WR = 0x0
6179 12:40:36.128647 DBI_RD = 0x0
6180 12:40:36.131913 OTF = 0x1
6181 12:40:36.135078 ===================================
6182 12:40:36.141848 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6183 12:40:36.145145 nWR fixed to 30
6184 12:40:36.145240 [ModeRegInit_LP4] CH0 RK0
6185 12:40:36.148447 [ModeRegInit_LP4] CH0 RK1
6186 12:40:36.151669 [ModeRegInit_LP4] CH1 RK0
6187 12:40:36.155372 [ModeRegInit_LP4] CH1 RK1
6188 12:40:36.155482 match AC timing 19
6189 12:40:36.158302 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6190 12:40:36.164803 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6191 12:40:36.168190 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6192 12:40:36.174398 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6193 12:40:36.178214 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6194 12:40:36.178332 ==
6195 12:40:36.181817 Dram Type= 6, Freq= 0, CH_0, rank 0
6196 12:40:36.184664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6197 12:40:36.184760 ==
6198 12:40:36.191657 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6199 12:40:36.197901 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6200 12:40:36.201608 [CA 0] Center 36 (8~64) winsize 57
6201 12:40:36.204229 [CA 1] Center 36 (8~64) winsize 57
6202 12:40:36.207399 [CA 2] Center 36 (8~64) winsize 57
6203 12:40:36.207500 [CA 3] Center 36 (8~64) winsize 57
6204 12:40:36.210655 [CA 4] Center 36 (8~64) winsize 57
6205 12:40:36.213871 [CA 5] Center 36 (8~64) winsize 57
6206 12:40:36.213964
6207 12:40:36.220737 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6208 12:40:36.220856
6209 12:40:36.223962 [CATrainingPosCal] consider 1 rank data
6210 12:40:36.227140 u2DelayCellTimex100 = 270/100 ps
6211 12:40:36.230845 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6212 12:40:36.233967 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6213 12:40:36.236760 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6214 12:40:36.239959 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 12:40:36.243295 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 12:40:36.246848 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 12:40:36.246950
6218 12:40:36.250452 CA PerBit enable=1, Macro0, CA PI delay=36
6219 12:40:36.250549
6220 12:40:36.253190 [CBTSetCACLKResult] CA Dly = 36
6221 12:40:36.257010 CS Dly: 1 (0~32)
6222 12:40:36.257102 ==
6223 12:40:36.260526 Dram Type= 6, Freq= 0, CH_0, rank 1
6224 12:40:36.263296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6225 12:40:36.263384 ==
6226 12:40:36.269951 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6227 12:40:36.276939 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6228 12:40:36.280201 [CA 0] Center 36 (8~64) winsize 57
6229 12:40:36.283060 [CA 1] Center 36 (8~64) winsize 57
6230 12:40:36.283155 [CA 2] Center 36 (8~64) winsize 57
6231 12:40:36.286236 [CA 3] Center 36 (8~64) winsize 57
6232 12:40:36.289883 [CA 4] Center 36 (8~64) winsize 57
6233 12:40:36.293185 [CA 5] Center 36 (8~64) winsize 57
6234 12:40:36.293284
6235 12:40:36.296951 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6236 12:40:36.299541
6237 12:40:36.303371 [CATrainingPosCal] consider 2 rank data
6238 12:40:36.306243 u2DelayCellTimex100 = 270/100 ps
6239 12:40:36.309793 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 12:40:36.313114 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 12:40:36.315869 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 12:40:36.319315 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 12:40:36.322318 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 12:40:36.325773 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 12:40:36.325872
6246 12:40:36.329116 CA PerBit enable=1, Macro0, CA PI delay=36
6247 12:40:36.329224
6248 12:40:36.332386 [CBTSetCACLKResult] CA Dly = 36
6249 12:40:36.335600 CS Dly: 1 (0~32)
6250 12:40:36.335711
6251 12:40:36.339056 ----->DramcWriteLeveling(PI) begin...
6252 12:40:36.339150 ==
6253 12:40:36.342536 Dram Type= 6, Freq= 0, CH_0, rank 0
6254 12:40:36.345799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6255 12:40:36.345896 ==
6256 12:40:36.349759 Write leveling (Byte 0): 40 => 8
6257 12:40:36.351935 Write leveling (Byte 1): 40 => 8
6258 12:40:36.355217 DramcWriteLeveling(PI) end<-----
6259 12:40:36.355313
6260 12:40:36.355382 ==
6261 12:40:36.358686 Dram Type= 6, Freq= 0, CH_0, rank 0
6262 12:40:36.361981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6263 12:40:36.362077 ==
6264 12:40:36.365486 [Gating] SW mode calibration
6265 12:40:36.371839 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6266 12:40:36.378718 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6267 12:40:36.381426 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6268 12:40:36.387897 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6269 12:40:36.391651 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6270 12:40:36.395104 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6271 12:40:36.401266 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6272 12:40:36.405224 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6273 12:40:36.408290 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6274 12:40:36.414615 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6275 12:40:36.417989 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6276 12:40:36.421467 Total UI for P1: 0, mck2ui 16
6277 12:40:36.424750 best dqsien dly found for B0: ( 0, 14, 24)
6278 12:40:36.427719 Total UI for P1: 0, mck2ui 16
6279 12:40:36.431499 best dqsien dly found for B1: ( 0, 14, 24)
6280 12:40:36.434351 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6281 12:40:36.437445 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6282 12:40:36.437538
6283 12:40:36.441242 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6284 12:40:36.444517 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6285 12:40:36.447935 [Gating] SW calibration Done
6286 12:40:36.448039 ==
6287 12:40:36.450714 Dram Type= 6, Freq= 0, CH_0, rank 0
6288 12:40:36.457527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6289 12:40:36.457641 ==
6290 12:40:36.457718 RX Vref Scan: 0
6291 12:40:36.457795
6292 12:40:36.460982 RX Vref 0 -> 0, step: 1
6293 12:40:36.461070
6294 12:40:36.463963 RX Delay -410 -> 252, step: 16
6295 12:40:36.467328 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6296 12:40:36.471417 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6297 12:40:36.477108 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6298 12:40:36.480225 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6299 12:40:36.483965 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6300 12:40:36.487262 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6301 12:40:36.493566 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6302 12:40:36.497002 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6303 12:40:36.500407 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6304 12:40:36.503412 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6305 12:40:36.510181 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6306 12:40:36.513298 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6307 12:40:36.516826 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6308 12:40:36.519868 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6309 12:40:36.526582 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6310 12:40:36.529970 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6311 12:40:36.530077 ==
6312 12:40:36.533166 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 12:40:36.536480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 12:40:36.536567 ==
6315 12:40:36.539836 DQS Delay:
6316 12:40:36.539923 DQS0 = 35, DQS1 = 59
6317 12:40:36.543079 DQM Delay:
6318 12:40:36.543163 DQM0 = 5, DQM1 = 16
6319 12:40:36.543227 DQ Delay:
6320 12:40:36.546383 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6321 12:40:36.549367 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6322 12:40:36.552820 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6323 12:40:36.556155 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6324 12:40:36.556247
6325 12:40:36.556310
6326 12:40:36.556369 ==
6327 12:40:36.559127 Dram Type= 6, Freq= 0, CH_0, rank 0
6328 12:40:36.566240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6329 12:40:36.566365 ==
6330 12:40:36.566432
6331 12:40:36.566491
6332 12:40:36.566548 TX Vref Scan disable
6333 12:40:36.569287 == TX Byte 0 ==
6334 12:40:36.572696 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6335 12:40:36.575929 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6336 12:40:36.578837 == TX Byte 1 ==
6337 12:40:36.582406 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6338 12:40:36.585470 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6339 12:40:36.589025 ==
6340 12:40:36.592647 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 12:40:36.595350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 12:40:36.595445 ==
6343 12:40:36.595508
6344 12:40:36.595567
6345 12:40:36.598537 TX Vref Scan disable
6346 12:40:36.598623 == TX Byte 0 ==
6347 12:40:36.602067 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6348 12:40:36.609165 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6349 12:40:36.609290 == TX Byte 1 ==
6350 12:40:36.611805 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6351 12:40:36.618667 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6352 12:40:36.618825
6353 12:40:36.618894 [DATLAT]
6354 12:40:36.618954 Freq=400, CH0 RK0
6355 12:40:36.619012
6356 12:40:36.621672 DATLAT Default: 0xf
6357 12:40:36.624820 0, 0xFFFF, sum = 0
6358 12:40:36.624909 1, 0xFFFF, sum = 0
6359 12:40:36.628026 2, 0xFFFF, sum = 0
6360 12:40:36.628157 3, 0xFFFF, sum = 0
6361 12:40:36.631694 4, 0xFFFF, sum = 0
6362 12:40:36.631781 5, 0xFFFF, sum = 0
6363 12:40:36.634728 6, 0xFFFF, sum = 0
6364 12:40:36.634817 7, 0xFFFF, sum = 0
6365 12:40:36.638224 8, 0xFFFF, sum = 0
6366 12:40:36.638315 9, 0xFFFF, sum = 0
6367 12:40:36.641824 10, 0xFFFF, sum = 0
6368 12:40:36.641913 11, 0xFFFF, sum = 0
6369 12:40:36.644774 12, 0xFFFF, sum = 0
6370 12:40:36.644860 13, 0x0, sum = 1
6371 12:40:36.648875 14, 0x0, sum = 2
6372 12:40:36.648969 15, 0x0, sum = 3
6373 12:40:36.651850 16, 0x0, sum = 4
6374 12:40:36.651959 best_step = 14
6375 12:40:36.652079
6376 12:40:36.652157 ==
6377 12:40:36.654479 Dram Type= 6, Freq= 0, CH_0, rank 0
6378 12:40:36.661258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6379 12:40:36.661372 ==
6380 12:40:36.661438 RX Vref Scan: 1
6381 12:40:36.661498
6382 12:40:36.664578 RX Vref 0 -> 0, step: 1
6383 12:40:36.664665
6384 12:40:36.667942 RX Delay -359 -> 252, step: 8
6385 12:40:36.668056
6386 12:40:36.671531 Set Vref, RX VrefLevel [Byte0]: 52
6387 12:40:36.674095 [Byte1]: 49
6388 12:40:36.677684
6389 12:40:36.677811 Final RX Vref Byte 0 = 52 to rank0
6390 12:40:36.681472 Final RX Vref Byte 1 = 49 to rank0
6391 12:40:36.684511 Final RX Vref Byte 0 = 52 to rank1
6392 12:40:36.687400 Final RX Vref Byte 1 = 49 to rank1==
6393 12:40:36.690826 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 12:40:36.697517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 12:40:36.697648 ==
6396 12:40:36.697744 DQS Delay:
6397 12:40:36.700516 DQS0 = 44, DQS1 = 56
6398 12:40:36.700605 DQM Delay:
6399 12:40:36.700693 DQM0 = 10, DQM1 = 13
6400 12:40:36.703761 DQ Delay:
6401 12:40:36.707023 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =4
6402 12:40:36.710598 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6403 12:40:36.710698 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6404 12:40:36.717037 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6405 12:40:36.717137
6406 12:40:36.717224
6407 12:40:36.723993 [DQSOSCAuto] RK0, (LSB)MR18= 0x9488, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6408 12:40:36.727578 CH0 RK0: MR19=C0C, MR18=9488
6409 12:40:36.733864 CH0_RK0: MR19=0xC0C, MR18=0x9488, DQSOSC=391, MR23=63, INC=386, DEC=257
6410 12:40:36.733994 ==
6411 12:40:36.737108 Dram Type= 6, Freq= 0, CH_0, rank 1
6412 12:40:36.740279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6413 12:40:36.740382 ==
6414 12:40:36.743200 [Gating] SW mode calibration
6415 12:40:36.750345 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6416 12:40:36.756375 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6417 12:40:36.759870 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6418 12:40:36.762901 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6419 12:40:36.769531 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6420 12:40:36.773091 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6421 12:40:36.776011 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6422 12:40:36.782762 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6423 12:40:36.785874 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6424 12:40:36.789358 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6425 12:40:36.795899 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6426 12:40:36.799181 Total UI for P1: 0, mck2ui 16
6427 12:40:36.802478 best dqsien dly found for B0: ( 0, 14, 24)
6428 12:40:36.806597 Total UI for P1: 0, mck2ui 16
6429 12:40:36.809108 best dqsien dly found for B1: ( 0, 14, 24)
6430 12:40:36.812487 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6431 12:40:36.816001 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6432 12:40:36.816171
6433 12:40:36.819170 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6434 12:40:36.822380 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6435 12:40:36.826110 [Gating] SW calibration Done
6436 12:40:36.826216 ==
6437 12:40:36.829027 Dram Type= 6, Freq= 0, CH_0, rank 1
6438 12:40:36.832166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6439 12:40:36.832272 ==
6440 12:40:36.835655 RX Vref Scan: 0
6441 12:40:36.835752
6442 12:40:36.839088 RX Vref 0 -> 0, step: 1
6443 12:40:36.839184
6444 12:40:36.842582 RX Delay -410 -> 252, step: 16
6445 12:40:36.845251 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6446 12:40:36.848526 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6447 12:40:36.851941 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6448 12:40:36.858645 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6449 12:40:36.861668 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6450 12:40:36.864903 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6451 12:40:36.868138 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6452 12:40:36.875036 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6453 12:40:36.878359 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6454 12:40:36.881853 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6455 12:40:36.884921 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6456 12:40:36.891363 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6457 12:40:36.894949 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6458 12:40:36.898165 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6459 12:40:36.904685 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6460 12:40:36.908515 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6461 12:40:36.908632 ==
6462 12:40:36.910928 Dram Type= 6, Freq= 0, CH_0, rank 1
6463 12:40:36.914557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 12:40:36.914665 ==
6465 12:40:36.917669 DQS Delay:
6466 12:40:36.917765 DQS0 = 35, DQS1 = 59
6467 12:40:36.920808 DQM Delay:
6468 12:40:36.920904 DQM0 = 8, DQM1 = 17
6469 12:40:36.920972 DQ Delay:
6470 12:40:36.924419 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6471 12:40:36.927659 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6472 12:40:36.930544 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6473 12:40:36.934393 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6474 12:40:36.934543
6475 12:40:36.934611
6476 12:40:36.934672 ==
6477 12:40:36.937513 Dram Type= 6, Freq= 0, CH_0, rank 1
6478 12:40:36.944410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6479 12:40:36.944542 ==
6480 12:40:36.944611
6481 12:40:36.944673
6482 12:40:36.944734 TX Vref Scan disable
6483 12:40:36.947180 == TX Byte 0 ==
6484 12:40:36.950925 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6485 12:40:36.953745 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6486 12:40:36.957375 == TX Byte 1 ==
6487 12:40:36.960871 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6488 12:40:36.963778 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6489 12:40:36.963879 ==
6490 12:40:36.967076 Dram Type= 6, Freq= 0, CH_0, rank 1
6491 12:40:36.973963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 12:40:36.974112 ==
6493 12:40:36.974185
6494 12:40:36.974262
6495 12:40:36.974324 TX Vref Scan disable
6496 12:40:36.976932 == TX Byte 0 ==
6497 12:40:36.980106 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6498 12:40:36.983790 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6499 12:40:36.986776 == TX Byte 1 ==
6500 12:40:36.989857 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6501 12:40:36.993315 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6502 12:40:36.993461
6503 12:40:36.996885 [DATLAT]
6504 12:40:36.997006 Freq=400, CH0 RK1
6505 12:40:36.997075
6506 12:40:37.000181 DATLAT Default: 0xe
6507 12:40:37.000285 0, 0xFFFF, sum = 0
6508 12:40:37.003490 1, 0xFFFF, sum = 0
6509 12:40:37.003609 2, 0xFFFF, sum = 0
6510 12:40:37.006710 3, 0xFFFF, sum = 0
6511 12:40:37.006828 4, 0xFFFF, sum = 0
6512 12:40:37.009726 5, 0xFFFF, sum = 0
6513 12:40:37.012952 6, 0xFFFF, sum = 0
6514 12:40:37.013077 7, 0xFFFF, sum = 0
6515 12:40:37.016557 8, 0xFFFF, sum = 0
6516 12:40:37.016678 9, 0xFFFF, sum = 0
6517 12:40:37.019551 10, 0xFFFF, sum = 0
6518 12:40:37.019684 11, 0xFFFF, sum = 0
6519 12:40:37.022744 12, 0xFFFF, sum = 0
6520 12:40:37.022861 13, 0x0, sum = 1
6521 12:40:37.026306 14, 0x0, sum = 2
6522 12:40:37.026425 15, 0x0, sum = 3
6523 12:40:37.029984 16, 0x0, sum = 4
6524 12:40:37.030106 best_step = 14
6525 12:40:37.030178
6526 12:40:37.030240 ==
6527 12:40:37.032931 Dram Type= 6, Freq= 0, CH_0, rank 1
6528 12:40:37.036448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6529 12:40:37.039815 ==
6530 12:40:37.039940 RX Vref Scan: 0
6531 12:40:37.040010
6532 12:40:37.043013 RX Vref 0 -> 0, step: 1
6533 12:40:37.043120
6534 12:40:37.045862 RX Delay -359 -> 252, step: 8
6535 12:40:37.052293 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6536 12:40:37.056385 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6537 12:40:37.059361 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6538 12:40:37.063228 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6539 12:40:37.069085 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6540 12:40:37.072822 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6541 12:40:37.075726 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6542 12:40:37.078901 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6543 12:40:37.085698 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6544 12:40:37.088562 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6545 12:40:37.092128 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6546 12:40:37.094927 iDelay=209, Bit 11, Center -48 (-287 ~ 192) 480
6547 12:40:37.101731 iDelay=209, Bit 12, Center -44 (-287 ~ 200) 488
6548 12:40:37.105181 iDelay=209, Bit 13, Center -40 (-279 ~ 200) 480
6549 12:40:37.108565 iDelay=209, Bit 14, Center -32 (-271 ~ 208) 480
6550 12:40:37.114904 iDelay=209, Bit 15, Center -40 (-279 ~ 200) 480
6551 12:40:37.115032 ==
6552 12:40:37.118361 Dram Type= 6, Freq= 0, CH_0, rank 1
6553 12:40:37.121813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6554 12:40:37.121939 ==
6555 12:40:37.122028 DQS Delay:
6556 12:40:37.124621 DQS0 = 44, DQS1 = 60
6557 12:40:37.124710 DQM Delay:
6558 12:40:37.128289 DQM0 = 9, DQM1 = 15
6559 12:40:37.128381 DQ Delay:
6560 12:40:37.131696 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6561 12:40:37.135074 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6562 12:40:37.137997 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6563 12:40:37.141129 DQ12 =16, DQ13 =20, DQ14 =28, DQ15 =20
6564 12:40:37.141223
6565 12:40:37.141290
6566 12:40:37.147703 [DQSOSCAuto] RK1, (LSB)MR18= 0x867f, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6567 12:40:37.150941 CH0 RK1: MR19=C0C, MR18=867F
6568 12:40:37.158014 CH0_RK1: MR19=0xC0C, MR18=0x867F, DQSOSC=393, MR23=63, INC=382, DEC=254
6569 12:40:37.160932 [RxdqsGatingPostProcess] freq 400
6570 12:40:37.167338 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6571 12:40:37.170723 best DQS0 dly(2T, 0.5T) = (0, 10)
6572 12:40:37.174427 best DQS1 dly(2T, 0.5T) = (0, 10)
6573 12:40:37.177532 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6574 12:40:37.180576 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6575 12:40:37.180675 best DQS0 dly(2T, 0.5T) = (0, 10)
6576 12:40:37.183853 best DQS1 dly(2T, 0.5T) = (0, 10)
6577 12:40:37.187644 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6578 12:40:37.190668 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6579 12:40:37.194376 Pre-setting of DQS Precalculation
6580 12:40:37.200288 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6581 12:40:37.200408 ==
6582 12:40:37.204302 Dram Type= 6, Freq= 0, CH_1, rank 0
6583 12:40:37.207001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6584 12:40:37.207099 ==
6585 12:40:37.213452 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6586 12:40:37.220750 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6587 12:40:37.223530 [CA 0] Center 36 (8~64) winsize 57
6588 12:40:37.226744 [CA 1] Center 36 (8~64) winsize 57
6589 12:40:37.226843 [CA 2] Center 36 (8~64) winsize 57
6590 12:40:37.229931 [CA 3] Center 36 (8~64) winsize 57
6591 12:40:37.233380 [CA 4] Center 36 (8~64) winsize 57
6592 12:40:37.237200 [CA 5] Center 36 (8~64) winsize 57
6593 12:40:37.237304
6594 12:40:37.239908 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6595 12:40:37.243136
6596 12:40:37.246676 [CATrainingPosCal] consider 1 rank data
6597 12:40:37.249943 u2DelayCellTimex100 = 270/100 ps
6598 12:40:37.253098 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6599 12:40:37.256878 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6600 12:40:37.259419 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6601 12:40:37.263030 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 12:40:37.266240 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 12:40:37.269693 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 12:40:37.269787
6605 12:40:37.272597 CA PerBit enable=1, Macro0, CA PI delay=36
6606 12:40:37.272691
6607 12:40:37.275839 [CBTSetCACLKResult] CA Dly = 36
6608 12:40:37.279713 CS Dly: 1 (0~32)
6609 12:40:37.279813 ==
6610 12:40:37.282835 Dram Type= 6, Freq= 0, CH_1, rank 1
6611 12:40:37.285992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6612 12:40:37.286088 ==
6613 12:40:37.293041 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6614 12:40:37.298929 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6615 12:40:37.302461 [CA 0] Center 36 (8~64) winsize 57
6616 12:40:37.302565 [CA 1] Center 36 (8~64) winsize 57
6617 12:40:37.306021 [CA 2] Center 36 (8~64) winsize 57
6618 12:40:37.308815 [CA 3] Center 36 (8~64) winsize 57
6619 12:40:37.312308 [CA 4] Center 36 (8~64) winsize 57
6620 12:40:37.315348 [CA 5] Center 36 (8~64) winsize 57
6621 12:40:37.315444
6622 12:40:37.319324 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6623 12:40:37.321959
6624 12:40:37.325354 [CATrainingPosCal] consider 2 rank data
6625 12:40:37.325447 u2DelayCellTimex100 = 270/100 ps
6626 12:40:37.332416 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 12:40:37.335003 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 12:40:37.338383 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 12:40:37.342073 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 12:40:37.345349 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 12:40:37.348265 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 12:40:37.348367
6633 12:40:37.351599 CA PerBit enable=1, Macro0, CA PI delay=36
6634 12:40:37.351694
6635 12:40:37.354975 [CBTSetCACLKResult] CA Dly = 36
6636 12:40:37.358225 CS Dly: 1 (0~32)
6637 12:40:37.358325
6638 12:40:37.361977 ----->DramcWriteLeveling(PI) begin...
6639 12:40:37.362071 ==
6640 12:40:37.364799 Dram Type= 6, Freq= 0, CH_1, rank 0
6641 12:40:37.368836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6642 12:40:37.368937 ==
6643 12:40:37.371688 Write leveling (Byte 0): 40 => 8
6644 12:40:37.375079 Write leveling (Byte 1): 40 => 8
6645 12:40:37.378546 DramcWriteLeveling(PI) end<-----
6646 12:40:37.378652
6647 12:40:37.378740 ==
6648 12:40:37.381413 Dram Type= 6, Freq= 0, CH_1, rank 0
6649 12:40:37.384700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6650 12:40:37.384799 ==
6651 12:40:37.387891 [Gating] SW mode calibration
6652 12:40:37.394535 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6653 12:40:37.401339 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6654 12:40:37.404756 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6655 12:40:37.407524 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6656 12:40:37.414295 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6657 12:40:37.417627 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6658 12:40:37.424557 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6659 12:40:37.427494 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6660 12:40:37.430853 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6661 12:40:37.437247 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6662 12:40:37.440988 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6663 12:40:37.443872 Total UI for P1: 0, mck2ui 16
6664 12:40:37.447717 best dqsien dly found for B0: ( 0, 14, 24)
6665 12:40:37.450820 Total UI for P1: 0, mck2ui 16
6666 12:40:37.453871 best dqsien dly found for B1: ( 0, 14, 24)
6667 12:40:37.457337 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6668 12:40:37.460160 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6669 12:40:37.460262
6670 12:40:37.463433 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6671 12:40:37.467061 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6672 12:40:37.470237 [Gating] SW calibration Done
6673 12:40:37.470345 ==
6674 12:40:37.473378 Dram Type= 6, Freq= 0, CH_1, rank 0
6675 12:40:37.476822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6676 12:40:37.480393 ==
6677 12:40:37.480501 RX Vref Scan: 0
6678 12:40:37.480571
6679 12:40:37.483837 RX Vref 0 -> 0, step: 1
6680 12:40:37.483957
6681 12:40:37.486858 RX Delay -410 -> 252, step: 16
6682 12:40:37.490334 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6683 12:40:37.493266 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6684 12:40:37.496467 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6685 12:40:37.503255 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6686 12:40:37.506559 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6687 12:40:37.510135 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6688 12:40:37.513116 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6689 12:40:37.519751 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6690 12:40:37.523253 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6691 12:40:37.526330 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6692 12:40:37.529743 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6693 12:40:37.536283 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6694 12:40:37.539332 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6695 12:40:37.543081 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6696 12:40:37.549823 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6697 12:40:37.552684 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6698 12:40:37.552796 ==
6699 12:40:37.555747 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 12:40:37.559044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 12:40:37.559147 ==
6702 12:40:37.562208 DQS Delay:
6703 12:40:37.562300 DQS0 = 35, DQS1 = 51
6704 12:40:37.565396 DQM Delay:
6705 12:40:37.565491 DQM0 = 6, DQM1 = 14
6706 12:40:37.565560 DQ Delay:
6707 12:40:37.568762 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6708 12:40:37.572393 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6709 12:40:37.575919 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6710 12:40:37.578812 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =16
6711 12:40:37.578920
6712 12:40:37.578987
6713 12:40:37.579049 ==
6714 12:40:37.581881 Dram Type= 6, Freq= 0, CH_1, rank 0
6715 12:40:37.588445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6716 12:40:37.588574 ==
6717 12:40:37.588644
6718 12:40:37.588707
6719 12:40:37.588765 TX Vref Scan disable
6720 12:40:37.591911 == TX Byte 0 ==
6721 12:40:37.595762 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6722 12:40:37.598496 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6723 12:40:37.601961 == TX Byte 1 ==
6724 12:40:37.605479 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6725 12:40:37.608374 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6726 12:40:37.608479 ==
6727 12:40:37.611929 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 12:40:37.618806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 12:40:37.618939 ==
6730 12:40:37.619012
6731 12:40:37.619074
6732 12:40:37.621490 TX Vref Scan disable
6733 12:40:37.621578 == TX Byte 0 ==
6734 12:40:37.624795 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6735 12:40:37.631909 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6736 12:40:37.632107 == TX Byte 1 ==
6737 12:40:37.634576 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6738 12:40:37.641333 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6739 12:40:37.641471
6740 12:40:37.641546 [DATLAT]
6741 12:40:37.641608 Freq=400, CH1 RK0
6742 12:40:37.641687
6743 12:40:37.644687 DATLAT Default: 0xf
6744 12:40:37.644780 0, 0xFFFF, sum = 0
6745 12:40:37.647861 1, 0xFFFF, sum = 0
6746 12:40:37.651154 2, 0xFFFF, sum = 0
6747 12:40:37.651257 3, 0xFFFF, sum = 0
6748 12:40:37.654586 4, 0xFFFF, sum = 0
6749 12:40:37.654688 5, 0xFFFF, sum = 0
6750 12:40:37.657820 6, 0xFFFF, sum = 0
6751 12:40:37.657916 7, 0xFFFF, sum = 0
6752 12:40:37.661520 8, 0xFFFF, sum = 0
6753 12:40:37.661624 9, 0xFFFF, sum = 0
6754 12:40:37.664360 10, 0xFFFF, sum = 0
6755 12:40:37.664448 11, 0xFFFF, sum = 0
6756 12:40:37.667405 12, 0xFFFF, sum = 0
6757 12:40:37.667494 13, 0x0, sum = 1
6758 12:40:37.670965 14, 0x0, sum = 2
6759 12:40:37.671052 15, 0x0, sum = 3
6760 12:40:37.673846 16, 0x0, sum = 4
6761 12:40:37.673958 best_step = 14
6762 12:40:37.674056
6763 12:40:37.674159 ==
6764 12:40:37.677404 Dram Type= 6, Freq= 0, CH_1, rank 0
6765 12:40:37.683895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6766 12:40:37.684010 ==
6767 12:40:37.684121 RX Vref Scan: 1
6768 12:40:37.684184
6769 12:40:37.687680 RX Vref 0 -> 0, step: 1
6770 12:40:37.687788
6771 12:40:37.690601 RX Delay -343 -> 252, step: 8
6772 12:40:37.690685
6773 12:40:37.693660 Set Vref, RX VrefLevel [Byte0]: 51
6774 12:40:37.697743 [Byte1]: 50
6775 12:40:37.697834
6776 12:40:37.700572 Final RX Vref Byte 0 = 51 to rank0
6777 12:40:37.703986 Final RX Vref Byte 1 = 50 to rank0
6778 12:40:37.707312 Final RX Vref Byte 0 = 51 to rank1
6779 12:40:37.710349 Final RX Vref Byte 1 = 50 to rank1==
6780 12:40:37.713837 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 12:40:37.716851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 12:40:37.720420 ==
6783 12:40:37.720506 DQS Delay:
6784 12:40:37.720574 DQS0 = 44, DQS1 = 56
6785 12:40:37.723833 DQM Delay:
6786 12:40:37.723919 DQM0 = 9, DQM1 = 15
6787 12:40:37.727098 DQ Delay:
6788 12:40:37.727185 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6789 12:40:37.730882 DQ4 =4, DQ5 =16, DQ6 =24, DQ7 =4
6790 12:40:37.733817 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6791 12:40:37.736663 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =20
6792 12:40:37.736752
6793 12:40:37.736818
6794 12:40:37.746797 [DQSOSCAuto] RK0, (LSB)MR18= 0x6a91, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 396 ps
6795 12:40:37.750717 CH1 RK0: MR19=C0C, MR18=6A91
6796 12:40:37.756690 CH1_RK0: MR19=0xC0C, MR18=0x6A91, DQSOSC=391, MR23=63, INC=386, DEC=257
6797 12:40:37.756829 ==
6798 12:40:37.759708 Dram Type= 6, Freq= 0, CH_1, rank 1
6799 12:40:37.763203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6800 12:40:37.763291 ==
6801 12:40:37.766322 [Gating] SW mode calibration
6802 12:40:37.772873 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6803 12:40:37.779473 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6804 12:40:37.782794 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6805 12:40:37.786143 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6806 12:40:37.792583 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6807 12:40:37.796191 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6808 12:40:37.799005 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6809 12:40:37.805838 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6810 12:40:37.809186 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6811 12:40:37.813178 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6812 12:40:37.818742 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6813 12:40:37.818839 Total UI for P1: 0, mck2ui 16
6814 12:40:37.825528 best dqsien dly found for B0: ( 0, 14, 24)
6815 12:40:37.825618 Total UI for P1: 0, mck2ui 16
6816 12:40:37.831974 best dqsien dly found for B1: ( 0, 14, 24)
6817 12:40:37.835739 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6818 12:40:37.838673 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6819 12:40:37.838763
6820 12:40:37.842237 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6821 12:40:37.845608 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6822 12:40:37.848581 [Gating] SW calibration Done
6823 12:40:37.848698 ==
6824 12:40:37.852393 Dram Type= 6, Freq= 0, CH_1, rank 1
6825 12:40:37.855084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6826 12:40:37.855172 ==
6827 12:40:37.858658 RX Vref Scan: 0
6828 12:40:37.858747
6829 12:40:37.858814 RX Vref 0 -> 0, step: 1
6830 12:40:37.861749
6831 12:40:37.861833 RX Delay -410 -> 252, step: 16
6832 12:40:37.868970 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6833 12:40:37.871515 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6834 12:40:37.875061 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6835 12:40:37.878321 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6836 12:40:37.884744 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6837 12:40:37.888215 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6838 12:40:37.891386 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6839 12:40:37.897682 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6840 12:40:37.901366 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6841 12:40:37.905349 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6842 12:40:37.907852 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6843 12:40:37.914989 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6844 12:40:37.917444 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6845 12:40:37.920654 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6846 12:40:37.924075 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6847 12:40:37.931070 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6848 12:40:37.931220 ==
6849 12:40:37.933759 Dram Type= 6, Freq= 0, CH_1, rank 1
6850 12:40:37.937521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 12:40:37.937616 ==
6852 12:40:37.937712 DQS Delay:
6853 12:40:37.940945 DQS0 = 43, DQS1 = 51
6854 12:40:37.941035 DQM Delay:
6855 12:40:37.943996 DQM0 = 10, DQM1 = 14
6856 12:40:37.944133 DQ Delay:
6857 12:40:37.947359 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6858 12:40:37.950648 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6859 12:40:37.954558 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6860 12:40:37.956988 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6861 12:40:37.957076
6862 12:40:37.957142
6863 12:40:37.957206 ==
6864 12:40:37.960777 Dram Type= 6, Freq= 0, CH_1, rank 1
6865 12:40:37.963987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6866 12:40:37.967331 ==
6867 12:40:37.967418
6868 12:40:37.967484
6869 12:40:37.967554 TX Vref Scan disable
6870 12:40:37.970066 == TX Byte 0 ==
6871 12:40:37.973331 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6872 12:40:37.976777 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6873 12:40:37.980302 == TX Byte 1 ==
6874 12:40:37.983661 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6875 12:40:37.986916 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6876 12:40:37.987004 ==
6877 12:40:37.989847 Dram Type= 6, Freq= 0, CH_1, rank 1
6878 12:40:37.996847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 12:40:37.996970 ==
6880 12:40:37.997045
6881 12:40:37.997108
6882 12:40:37.997178 TX Vref Scan disable
6883 12:40:37.999522 == TX Byte 0 ==
6884 12:40:38.002992 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6885 12:40:38.006363 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6886 12:40:38.010015 == TX Byte 1 ==
6887 12:40:38.012886 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6888 12:40:38.016383 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6889 12:40:38.016475
6890 12:40:38.019298 [DATLAT]
6891 12:40:38.019387 Freq=400, CH1 RK1
6892 12:40:38.019474
6893 12:40:38.023223 DATLAT Default: 0xe
6894 12:40:38.023311 0, 0xFFFF, sum = 0
6895 12:40:38.026234 1, 0xFFFF, sum = 0
6896 12:40:38.026325 2, 0xFFFF, sum = 0
6897 12:40:38.029367 3, 0xFFFF, sum = 0
6898 12:40:38.029455 4, 0xFFFF, sum = 0
6899 12:40:38.033171 5, 0xFFFF, sum = 0
6900 12:40:38.033258 6, 0xFFFF, sum = 0
6901 12:40:38.036550 7, 0xFFFF, sum = 0
6902 12:40:38.036639 8, 0xFFFF, sum = 0
6903 12:40:38.039347 9, 0xFFFF, sum = 0
6904 12:40:38.043044 10, 0xFFFF, sum = 0
6905 12:40:38.043134 11, 0xFFFF, sum = 0
6906 12:40:38.045838 12, 0xFFFF, sum = 0
6907 12:40:38.045926 13, 0x0, sum = 1
6908 12:40:38.048860 14, 0x0, sum = 2
6909 12:40:38.048949 15, 0x0, sum = 3
6910 12:40:38.052297 16, 0x0, sum = 4
6911 12:40:38.052409 best_step = 14
6912 12:40:38.052526
6913 12:40:38.052626 ==
6914 12:40:38.056093 Dram Type= 6, Freq= 0, CH_1, rank 1
6915 12:40:38.058863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6916 12:40:38.058965 ==
6917 12:40:38.062870 RX Vref Scan: 0
6918 12:40:38.062959
6919 12:40:38.065849 RX Vref 0 -> 0, step: 1
6920 12:40:38.065936
6921 12:40:38.066022 RX Delay -343 -> 252, step: 8
6922 12:40:38.074566 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6923 12:40:38.078276 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6924 12:40:38.080880 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6925 12:40:38.088721 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6926 12:40:38.091138 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6927 12:40:38.094081 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6928 12:40:38.097285 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6929 12:40:38.104225 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6930 12:40:38.107339 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6931 12:40:38.110391 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6932 12:40:38.114268 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6933 12:40:38.120528 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6934 12:40:38.123834 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6935 12:40:38.127731 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6936 12:40:38.130401 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6937 12:40:38.137175 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6938 12:40:38.137288 ==
6939 12:40:38.140249 Dram Type= 6, Freq= 0, CH_1, rank 1
6940 12:40:38.143543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6941 12:40:38.143655 ==
6942 12:40:38.143728 DQS Delay:
6943 12:40:38.147128 DQS0 = 48, DQS1 = 56
6944 12:40:38.147256 DQM Delay:
6945 12:40:38.150494 DQM0 = 11, DQM1 = 14
6946 12:40:38.150598 DQ Delay:
6947 12:40:38.153295 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
6948 12:40:38.156821 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6949 12:40:38.159967 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6950 12:40:38.163425 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6951 12:40:38.163587
6952 12:40:38.163658
6953 12:40:38.173068 [DQSOSCAuto] RK1, (LSB)MR18= 0x6ca5, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
6954 12:40:38.173238 CH1 RK1: MR19=C0C, MR18=6CA5
6955 12:40:38.180025 CH1_RK1: MR19=0xC0C, MR18=0x6CA5, DQSOSC=389, MR23=63, INC=390, DEC=260
6956 12:40:38.183207 [RxdqsGatingPostProcess] freq 400
6957 12:40:38.190054 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6958 12:40:38.193276 best DQS0 dly(2T, 0.5T) = (0, 10)
6959 12:40:38.196598 best DQS1 dly(2T, 0.5T) = (0, 10)
6960 12:40:38.199540 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6961 12:40:38.203296 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6962 12:40:38.206318 best DQS0 dly(2T, 0.5T) = (0, 10)
6963 12:40:38.206415 best DQS1 dly(2T, 0.5T) = (0, 10)
6964 12:40:38.209515 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6965 12:40:38.212887 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6966 12:40:38.216008 Pre-setting of DQS Precalculation
6967 12:40:38.222769 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6968 12:40:38.229494 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6969 12:40:38.235884 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6970 12:40:38.235999
6971 12:40:38.236122
6972 12:40:38.239168 [Calibration Summary] 800 Mbps
6973 12:40:38.242352 CH 0, Rank 0
6974 12:40:38.242431 SW Impedance : PASS
6975 12:40:38.245998 DUTY Scan : NO K
6976 12:40:38.249114 ZQ Calibration : PASS
6977 12:40:38.249206 Jitter Meter : NO K
6978 12:40:38.252265 CBT Training : PASS
6979 12:40:38.255583 Write leveling : PASS
6980 12:40:38.255682 RX DQS gating : PASS
6981 12:40:38.258958 RX DQ/DQS(RDDQC) : PASS
6982 12:40:38.259050 TX DQ/DQS : PASS
6983 12:40:38.262088 RX DATLAT : PASS
6984 12:40:38.265589 RX DQ/DQS(Engine): PASS
6985 12:40:38.265685 TX OE : NO K
6986 12:40:38.268803 All Pass.
6987 12:40:38.268899
6988 12:40:38.268967 CH 0, Rank 1
6989 12:40:38.272017 SW Impedance : PASS
6990 12:40:38.272142 DUTY Scan : NO K
6991 12:40:38.275077 ZQ Calibration : PASS
6992 12:40:38.279113 Jitter Meter : NO K
6993 12:40:38.279225 CBT Training : PASS
6994 12:40:38.281932 Write leveling : NO K
6995 12:40:38.285076 RX DQS gating : PASS
6996 12:40:38.285176 RX DQ/DQS(RDDQC) : PASS
6997 12:40:38.288731 TX DQ/DQS : PASS
6998 12:40:38.291676 RX DATLAT : PASS
6999 12:40:38.291870 RX DQ/DQS(Engine): PASS
7000 12:40:38.295001 TX OE : NO K
7001 12:40:38.295120 All Pass.
7002 12:40:38.295215
7003 12:40:38.298561 CH 1, Rank 0
7004 12:40:38.298724 SW Impedance : PASS
7005 12:40:38.301987 DUTY Scan : NO K
7006 12:40:38.304980 ZQ Calibration : PASS
7007 12:40:38.305103 Jitter Meter : NO K
7008 12:40:38.308217 CBT Training : PASS
7009 12:40:38.311482 Write leveling : PASS
7010 12:40:38.311608 RX DQS gating : PASS
7011 12:40:38.314579 RX DQ/DQS(RDDQC) : PASS
7012 12:40:38.317908 TX DQ/DQS : PASS
7013 12:40:38.318013 RX DATLAT : PASS
7014 12:40:38.321229 RX DQ/DQS(Engine): PASS
7015 12:40:38.324890 TX OE : NO K
7016 12:40:38.325010 All Pass.
7017 12:40:38.325082
7018 12:40:38.325144 CH 1, Rank 1
7019 12:40:38.327803 SW Impedance : PASS
7020 12:40:38.331019 DUTY Scan : NO K
7021 12:40:38.331119 ZQ Calibration : PASS
7022 12:40:38.334381 Jitter Meter : NO K
7023 12:40:38.338325 CBT Training : PASS
7024 12:40:38.338419 Write leveling : NO K
7025 12:40:38.340985 RX DQS gating : PASS
7026 12:40:38.341098 RX DQ/DQS(RDDQC) : PASS
7027 12:40:38.344832 TX DQ/DQS : PASS
7028 12:40:38.347573 RX DATLAT : PASS
7029 12:40:38.347661 RX DQ/DQS(Engine): PASS
7030 12:40:38.350991 TX OE : NO K
7031 12:40:38.351080 All Pass.
7032 12:40:38.351146
7033 12:40:38.354186 DramC Write-DBI off
7034 12:40:38.357545 PER_BANK_REFRESH: Hybrid Mode
7035 12:40:38.357637 TX_TRACKING: ON
7036 12:40:38.367652 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7037 12:40:38.371258 [FAST_K] Save calibration result to emmc
7038 12:40:38.374015 dramc_set_vcore_voltage set vcore to 725000
7039 12:40:38.377421 Read voltage for 1600, 0
7040 12:40:38.377532 Vio18 = 0
7041 12:40:38.380929 Vcore = 725000
7042 12:40:38.381038 Vdram = 0
7043 12:40:38.381126 Vddq = 0
7044 12:40:38.381209 Vmddr = 0
7045 12:40:38.387369 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7046 12:40:38.393733 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7047 12:40:38.393861 MEM_TYPE=3, freq_sel=13
7048 12:40:38.397120 sv_algorithm_assistance_LP4_3733
7049 12:40:38.400151 ============ PULL DRAM RESETB DOWN ============
7050 12:40:38.406960 ========== PULL DRAM RESETB DOWN end =========
7051 12:40:38.410202 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7052 12:40:38.413721 ===================================
7053 12:40:38.416551 LPDDR4 DRAM CONFIGURATION
7054 12:40:38.420538 ===================================
7055 12:40:38.420703 EX_ROW_EN[0] = 0x0
7056 12:40:38.423245 EX_ROW_EN[1] = 0x0
7057 12:40:38.426732 LP4Y_EN = 0x0
7058 12:40:38.426830 WORK_FSP = 0x1
7059 12:40:38.429949 WL = 0x5
7060 12:40:38.430046 RL = 0x5
7061 12:40:38.433065 BL = 0x2
7062 12:40:38.433162 RPST = 0x0
7063 12:40:38.436648 RD_PRE = 0x0
7064 12:40:38.436738 WR_PRE = 0x1
7065 12:40:38.440219 WR_PST = 0x1
7066 12:40:38.440307 DBI_WR = 0x0
7067 12:40:38.442744 DBI_RD = 0x0
7068 12:40:38.442831 OTF = 0x1
7069 12:40:38.446424 ===================================
7070 12:40:38.449332 ===================================
7071 12:40:38.453138 ANA top config
7072 12:40:38.455997 ===================================
7073 12:40:38.459265 DLL_ASYNC_EN = 0
7074 12:40:38.459360 ALL_SLAVE_EN = 0
7075 12:40:38.462413 NEW_RANK_MODE = 1
7076 12:40:38.465802 DLL_IDLE_MODE = 1
7077 12:40:38.469240 LP45_APHY_COMB_EN = 1
7078 12:40:38.472805 TX_ODT_DIS = 0
7079 12:40:38.472926 NEW_8X_MODE = 1
7080 12:40:38.475974 ===================================
7081 12:40:38.478967 ===================================
7082 12:40:38.482688 data_rate = 3200
7083 12:40:38.485480 CKR = 1
7084 12:40:38.488836 DQ_P2S_RATIO = 8
7085 12:40:38.492258 ===================================
7086 12:40:38.495651 CA_P2S_RATIO = 8
7087 12:40:38.499045 DQ_CA_OPEN = 0
7088 12:40:38.499211 DQ_SEMI_OPEN = 0
7089 12:40:38.502265 CA_SEMI_OPEN = 0
7090 12:40:38.505808 CA_FULL_RATE = 0
7091 12:40:38.508726 DQ_CKDIV4_EN = 0
7092 12:40:38.512179 CA_CKDIV4_EN = 0
7093 12:40:38.515162 CA_PREDIV_EN = 0
7094 12:40:38.515279 PH8_DLY = 12
7095 12:40:38.518526 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7096 12:40:38.522027 DQ_AAMCK_DIV = 4
7097 12:40:38.525111 CA_AAMCK_DIV = 4
7098 12:40:38.528470 CA_ADMCK_DIV = 4
7099 12:40:38.531791 DQ_TRACK_CA_EN = 0
7100 12:40:38.531924 CA_PICK = 1600
7101 12:40:38.535552 CA_MCKIO = 1600
7102 12:40:38.538275 MCKIO_SEMI = 0
7103 12:40:38.541893 PLL_FREQ = 3068
7104 12:40:38.545081 DQ_UI_PI_RATIO = 32
7105 12:40:38.548426 CA_UI_PI_RATIO = 0
7106 12:40:38.551751 ===================================
7107 12:40:38.555208 ===================================
7108 12:40:38.558505 memory_type:LPDDR4
7109 12:40:38.558601 GP_NUM : 10
7110 12:40:38.561256 SRAM_EN : 1
7111 12:40:38.561344 MD32_EN : 0
7112 12:40:38.564716 ===================================
7113 12:40:38.567977 [ANA_INIT] >>>>>>>>>>>>>>
7114 12:40:38.571538 <<<<<< [CONFIGURE PHASE]: ANA_TX
7115 12:40:38.574627 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7116 12:40:38.578506 ===================================
7117 12:40:38.581222 data_rate = 3200,PCW = 0X7600
7118 12:40:38.584665 ===================================
7119 12:40:38.587781 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7120 12:40:38.594341 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7121 12:40:38.597659 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7122 12:40:38.603886 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7123 12:40:38.607460 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7124 12:40:38.610604 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7125 12:40:38.610699 [ANA_INIT] flow start
7126 12:40:38.613902 [ANA_INIT] PLL >>>>>>>>
7127 12:40:38.617419 [ANA_INIT] PLL <<<<<<<<
7128 12:40:38.620841 [ANA_INIT] MIDPI >>>>>>>>
7129 12:40:38.620953 [ANA_INIT] MIDPI <<<<<<<<
7130 12:40:38.623954 [ANA_INIT] DLL >>>>>>>>
7131 12:40:38.627280 [ANA_INIT] DLL <<<<<<<<
7132 12:40:38.627423 [ANA_INIT] flow end
7133 12:40:38.630614 ============ LP4 DIFF to SE enter ============
7134 12:40:38.637112 ============ LP4 DIFF to SE exit ============
7135 12:40:38.637264 [ANA_INIT] <<<<<<<<<<<<<
7136 12:40:38.640683 [Flow] Enable top DCM control >>>>>
7137 12:40:38.643944 [Flow] Enable top DCM control <<<<<
7138 12:40:38.647150 Enable DLL master slave shuffle
7139 12:40:38.653704 ==============================================================
7140 12:40:38.656772 Gating Mode config
7141 12:40:38.660365 ==============================================================
7142 12:40:38.663734 Config description:
7143 12:40:38.673311 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7144 12:40:38.679917 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7145 12:40:38.683087 SELPH_MODE 0: By rank 1: By Phase
7146 12:40:38.689912 ==============================================================
7147 12:40:38.693046 GAT_TRACK_EN = 1
7148 12:40:38.696492 RX_GATING_MODE = 2
7149 12:40:38.699653 RX_GATING_TRACK_MODE = 2
7150 12:40:38.703082 SELPH_MODE = 1
7151 12:40:38.703198 PICG_EARLY_EN = 1
7152 12:40:38.706313 VALID_LAT_VALUE = 1
7153 12:40:38.713006 ==============================================================
7154 12:40:38.715950 Enter into Gating configuration >>>>
7155 12:40:38.719345 Exit from Gating configuration <<<<
7156 12:40:38.723045 Enter into DVFS_PRE_config >>>>>
7157 12:40:38.732705 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7158 12:40:38.735806 Exit from DVFS_PRE_config <<<<<
7159 12:40:38.739125 Enter into PICG configuration >>>>
7160 12:40:38.742658 Exit from PICG configuration <<<<
7161 12:40:38.745517 [RX_INPUT] configuration >>>>>
7162 12:40:38.749069 [RX_INPUT] configuration <<<<<
7163 12:40:38.755413 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7164 12:40:38.758858 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7165 12:40:38.765516 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7166 12:40:38.772111 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7167 12:40:38.778328 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7168 12:40:38.831952 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7169 12:40:38.832179 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7170 12:40:38.832309 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7171 12:40:38.832424 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7172 12:40:38.832536 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7173 12:40:38.832648 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7174 12:40:38.832759 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7175 12:40:38.832870 ===================================
7176 12:40:38.832981 LPDDR4 DRAM CONFIGURATION
7177 12:40:38.833091 ===================================
7178 12:40:38.833200 EX_ROW_EN[0] = 0x0
7179 12:40:38.833310 EX_ROW_EN[1] = 0x0
7180 12:40:38.833420 LP4Y_EN = 0x0
7181 12:40:38.833529 WORK_FSP = 0x1
7182 12:40:38.833635 WL = 0x5
7183 12:40:38.833743 RL = 0x5
7184 12:40:38.833849 BL = 0x2
7185 12:40:38.833954 RPST = 0x0
7186 12:40:38.834367 RD_PRE = 0x0
7187 12:40:38.834497 WR_PRE = 0x1
7188 12:40:38.837980 WR_PST = 0x1
7189 12:40:38.838119 DBI_WR = 0x0
7190 12:40:38.841026 DBI_RD = 0x0
7191 12:40:38.841138 OTF = 0x1
7192 12:40:38.844654 ===================================
7193 12:40:38.851059 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7194 12:40:38.853902 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7195 12:40:38.857313 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7196 12:40:38.860911 ===================================
7197 12:40:38.864128 LPDDR4 DRAM CONFIGURATION
7198 12:40:38.867151 ===================================
7199 12:40:38.870551 EX_ROW_EN[0] = 0x10
7200 12:40:38.870643 EX_ROW_EN[1] = 0x0
7201 12:40:38.874614 LP4Y_EN = 0x0
7202 12:40:38.874728 WORK_FSP = 0x1
7203 12:40:38.877258 WL = 0x5
7204 12:40:38.877340 RL = 0x5
7205 12:40:38.880551 BL = 0x2
7206 12:40:38.880632 RPST = 0x0
7207 12:40:38.884081 RD_PRE = 0x0
7208 12:40:38.884188 WR_PRE = 0x1
7209 12:40:38.887137 WR_PST = 0x1
7210 12:40:38.887214 DBI_WR = 0x0
7211 12:40:38.890158 DBI_RD = 0x0
7212 12:40:38.893769 OTF = 0x1
7213 12:40:38.896925 ===================================
7214 12:40:38.900227 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7215 12:40:38.900304 ==
7216 12:40:38.903622 Dram Type= 6, Freq= 0, CH_0, rank 0
7217 12:40:38.910087 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7218 12:40:38.910176 ==
7219 12:40:38.913698 [Duty_Offset_Calibration]
7220 12:40:38.913827 B0:2 B1:0 CA:4
7221 12:40:38.913893
7222 12:40:38.916895 [DutyScan_Calibration_Flow] k_type=0
7223 12:40:38.926095
7224 12:40:38.926245 ==CLK 0==
7225 12:40:38.928968 Final CLK duty delay cell = -4
7226 12:40:38.932244 [-4] MAX Duty = 5031%(X100), DQS PI = 32
7227 12:40:38.935874 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7228 12:40:38.939030 [-4] AVG Duty = 4922%(X100)
7229 12:40:38.939137
7230 12:40:38.941999 CH0 CLK Duty spec in!! Max-Min= 218%
7231 12:40:38.945472 [DutyScan_Calibration_Flow] ====Done====
7232 12:40:38.945560
7233 12:40:38.948398 [DutyScan_Calibration_Flow] k_type=1
7234 12:40:38.966056
7235 12:40:38.966202 ==DQS 0 ==
7236 12:40:38.968923 Final DQS duty delay cell = 0
7237 12:40:38.972931 [0] MAX Duty = 5218%(X100), DQS PI = 22
7238 12:40:38.975732 [0] MIN Duty = 5093%(X100), DQS PI = 8
7239 12:40:38.979157 [0] AVG Duty = 5155%(X100)
7240 12:40:38.979241
7241 12:40:38.979309 ==DQS 1 ==
7242 12:40:38.982886 Final DQS duty delay cell = 0
7243 12:40:38.985720 [0] MAX Duty = 5156%(X100), DQS PI = 2
7244 12:40:38.989045 [0] MIN Duty = 4969%(X100), DQS PI = 10
7245 12:40:38.992400 [0] AVG Duty = 5062%(X100)
7246 12:40:38.992478
7247 12:40:38.995720 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7248 12:40:38.995795
7249 12:40:38.998796 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7250 12:40:39.002588 [DutyScan_Calibration_Flow] ====Done====
7251 12:40:39.002664
7252 12:40:39.005127 [DutyScan_Calibration_Flow] k_type=3
7253 12:40:39.023204
7254 12:40:39.023361 ==DQM 0 ==
7255 12:40:39.026927 Final DQM duty delay cell = 0
7256 12:40:39.029515 [0] MAX Duty = 5124%(X100), DQS PI = 20
7257 12:40:39.032949 [0] MIN Duty = 4875%(X100), DQS PI = 56
7258 12:40:39.036022 [0] AVG Duty = 4999%(X100)
7259 12:40:39.036130
7260 12:40:39.036231 ==DQM 1 ==
7261 12:40:39.039396 Final DQM duty delay cell = 0
7262 12:40:39.042636 [0] MAX Duty = 4969%(X100), DQS PI = 2
7263 12:40:39.046313 [0] MIN Duty = 4844%(X100), DQS PI = 16
7264 12:40:39.049880 [0] AVG Duty = 4906%(X100)
7265 12:40:39.049981
7266 12:40:39.052838 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7267 12:40:39.052926
7268 12:40:39.055659 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7269 12:40:39.059584 [DutyScan_Calibration_Flow] ====Done====
7270 12:40:39.059674
7271 12:40:39.062173 [DutyScan_Calibration_Flow] k_type=2
7272 12:40:39.080271
7273 12:40:39.080420 ==DQ 0 ==
7274 12:40:39.083805 Final DQ duty delay cell = 0
7275 12:40:39.086764 [0] MAX Duty = 5156%(X100), DQS PI = 22
7276 12:40:39.090698 [0] MIN Duty = 4938%(X100), DQS PI = 12
7277 12:40:39.090789 [0] AVG Duty = 5047%(X100)
7278 12:40:39.093093
7279 12:40:39.093178 ==DQ 1 ==
7280 12:40:39.096579 Final DQ duty delay cell = 0
7281 12:40:39.099861 [0] MAX Duty = 5187%(X100), DQS PI = 4
7282 12:40:39.103824 [0] MIN Duty = 4938%(X100), DQS PI = 12
7283 12:40:39.103915 [0] AVG Duty = 5062%(X100)
7284 12:40:39.106443
7285 12:40:39.109763 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7286 12:40:39.109851
7287 12:40:39.113013 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7288 12:40:39.116759 [DutyScan_Calibration_Flow] ====Done====
7289 12:40:39.116846 ==
7290 12:40:39.120385 Dram Type= 6, Freq= 0, CH_1, rank 0
7291 12:40:39.122570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7292 12:40:39.122658 ==
7293 12:40:39.126267 [Duty_Offset_Calibration]
7294 12:40:39.126354 B0:0 B1:-1 CA:3
7295 12:40:39.126421
7296 12:40:39.129228 [DutyScan_Calibration_Flow] k_type=0
7297 12:40:39.139433
7298 12:40:39.139542 ==CLK 0==
7299 12:40:39.142874 Final CLK duty delay cell = -4
7300 12:40:39.146190 [-4] MAX Duty = 5000%(X100), DQS PI = 6
7301 12:40:39.149648 [-4] MIN Duty = 4844%(X100), DQS PI = 60
7302 12:40:39.152436 [-4] AVG Duty = 4922%(X100)
7303 12:40:39.152522
7304 12:40:39.156584 CH1 CLK Duty spec in!! Max-Min= 156%
7305 12:40:39.159713 [DutyScan_Calibration_Flow] ====Done====
7306 12:40:39.159802
7307 12:40:39.162488 [DutyScan_Calibration_Flow] k_type=1
7308 12:40:39.178585
7309 12:40:39.178729 ==DQS 0 ==
7310 12:40:39.182423 Final DQS duty delay cell = 0
7311 12:40:39.185259 [0] MAX Duty = 5250%(X100), DQS PI = 28
7312 12:40:39.189102 [0] MIN Duty = 4907%(X100), DQS PI = 58
7313 12:40:39.191901 [0] AVG Duty = 5078%(X100)
7314 12:40:39.191986
7315 12:40:39.192092 ==DQS 1 ==
7316 12:40:39.195587 Final DQS duty delay cell = -4
7317 12:40:39.198213 [-4] MAX Duty = 5000%(X100), DQS PI = 28
7318 12:40:39.201796 [-4] MIN Duty = 4813%(X100), DQS PI = 62
7319 12:40:39.204938 [-4] AVG Duty = 4906%(X100)
7320 12:40:39.205023
7321 12:40:39.208538 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7322 12:40:39.208622
7323 12:40:39.212206 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7324 12:40:39.215229 [DutyScan_Calibration_Flow] ====Done====
7325 12:40:39.215312
7326 12:40:39.217894 [DutyScan_Calibration_Flow] k_type=3
7327 12:40:39.235985
7328 12:40:39.236186 ==DQM 0 ==
7329 12:40:39.239421 Final DQM duty delay cell = 0
7330 12:40:39.242474 [0] MAX Duty = 5062%(X100), DQS PI = 30
7331 12:40:39.245792 [0] MIN Duty = 4782%(X100), DQS PI = 40
7332 12:40:39.249060 [0] AVG Duty = 4922%(X100)
7333 12:40:39.249147
7334 12:40:39.249210 ==DQM 1 ==
7335 12:40:39.252589 Final DQM duty delay cell = 0
7336 12:40:39.255448 [0] MAX Duty = 5000%(X100), DQS PI = 30
7337 12:40:39.258861 [0] MIN Duty = 4813%(X100), DQS PI = 0
7338 12:40:39.262168 [0] AVG Duty = 4906%(X100)
7339 12:40:39.262254
7340 12:40:39.265227 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7341 12:40:39.265312
7342 12:40:39.268563 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7343 12:40:39.272189 [DutyScan_Calibration_Flow] ====Done====
7344 12:40:39.272275
7345 12:40:39.275187 [DutyScan_Calibration_Flow] k_type=2
7346 12:40:39.292144
7347 12:40:39.292296 ==DQ 0 ==
7348 12:40:39.295785 Final DQ duty delay cell = -4
7349 12:40:39.298883 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7350 12:40:39.301790 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7351 12:40:39.305279 [-4] AVG Duty = 4891%(X100)
7352 12:40:39.305368
7353 12:40:39.305433 ==DQ 1 ==
7354 12:40:39.308917 Final DQ duty delay cell = 0
7355 12:40:39.311529 [0] MAX Duty = 5031%(X100), DQS PI = 32
7356 12:40:39.315017 [0] MIN Duty = 4875%(X100), DQS PI = 0
7357 12:40:39.318518 [0] AVG Duty = 4953%(X100)
7358 12:40:39.318605
7359 12:40:39.321565 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7360 12:40:39.321650
7361 12:40:39.324797 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7362 12:40:39.327962 [DutyScan_Calibration_Flow] ====Done====
7363 12:40:39.331930 nWR fixed to 30
7364 12:40:39.334617 [ModeRegInit_LP4] CH0 RK0
7365 12:40:39.334705 [ModeRegInit_LP4] CH0 RK1
7366 12:40:39.337974 [ModeRegInit_LP4] CH1 RK0
7367 12:40:39.341409 [ModeRegInit_LP4] CH1 RK1
7368 12:40:39.341496 match AC timing 5
7369 12:40:39.348691 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7370 12:40:39.351049 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7371 12:40:39.354410 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7372 12:40:39.361615 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7373 12:40:39.364676 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7374 12:40:39.368086 [MiockJmeterHQA]
7375 12:40:39.368173
7376 12:40:39.370858 [DramcMiockJmeter] u1RxGatingPI = 0
7377 12:40:39.370945 0 : 4253, 4027
7378 12:40:39.371014 4 : 4366, 4137
7379 12:40:39.374464 8 : 4253, 4027
7380 12:40:39.374584 12 : 4252, 4027
7381 12:40:39.377706 16 : 4363, 4137
7382 12:40:39.377796 20 : 4252, 4027
7383 12:40:39.380826 24 : 4255, 4029
7384 12:40:39.380915 28 : 4252, 4026
7385 12:40:39.380982 32 : 4363, 4138
7386 12:40:39.384227 36 : 4362, 4137
7387 12:40:39.384316 40 : 4252, 4027
7388 12:40:39.387330 44 : 4253, 4027
7389 12:40:39.387415 48 : 4252, 4027
7390 12:40:39.391785 52 : 4252, 4027
7391 12:40:39.391872 56 : 4255, 4030
7392 12:40:39.394596 60 : 4363, 4137
7393 12:40:39.394682 64 : 4252, 4027
7394 12:40:39.394749 68 : 4250, 4027
7395 12:40:39.397062 72 : 4252, 4027
7396 12:40:39.397147 76 : 4253, 4029
7397 12:40:39.400558 80 : 4250, 4027
7398 12:40:39.400647 84 : 4363, 4138
7399 12:40:39.404066 88 : 4360, 4137
7400 12:40:39.404155 92 : 4250, 4027
7401 12:40:39.407460 96 : 4250, 3482
7402 12:40:39.407574 100 : 4250, 0
7403 12:40:39.407663 104 : 4252, 0
7404 12:40:39.410557 108 : 4252, 0
7405 12:40:39.410643 112 : 4252, 0
7406 12:40:39.413797 116 : 4253, 0
7407 12:40:39.413884 120 : 4363, 0
7408 12:40:39.413952 124 : 4361, 0
7409 12:40:39.416904 128 : 4247, 0
7410 12:40:39.416990 132 : 4361, 0
7411 12:40:39.420780 136 : 4250, 0
7412 12:40:39.420868 140 : 4250, 0
7413 12:40:39.420936 144 : 4250, 0
7414 12:40:39.423983 148 : 4250, 0
7415 12:40:39.424091 152 : 4250, 0
7416 12:40:39.424160 156 : 4250, 0
7417 12:40:39.427348 160 : 4250, 0
7418 12:40:39.427436 164 : 4250, 0
7419 12:40:39.430516 168 : 4252, 0
7420 12:40:39.430602 172 : 4360, 0
7421 12:40:39.430670 176 : 4361, 0
7422 12:40:39.433969 180 : 4363, 0
7423 12:40:39.434055 184 : 4361, 0
7424 12:40:39.436867 188 : 4250, 0
7425 12:40:39.436953 192 : 4250, 0
7426 12:40:39.437022 196 : 4250, 0
7427 12:40:39.440023 200 : 4250, 0
7428 12:40:39.440173 204 : 4250, 0
7429 12:40:39.443644 208 : 4252, 0
7430 12:40:39.443734 212 : 4250, 0
7431 12:40:39.443802 216 : 4250, 0
7432 12:40:39.446560 220 : 4252, 322
7433 12:40:39.446648 224 : 4361, 4085
7434 12:40:39.450038 228 : 4252, 4029
7435 12:40:39.450126 232 : 4250, 4026
7436 12:40:39.453364 236 : 4361, 4137
7437 12:40:39.453451 240 : 4250, 4026
7438 12:40:39.456858 244 : 4250, 4027
7439 12:40:39.456945 248 : 4250, 4027
7440 12:40:39.459658 252 : 4253, 4029
7441 12:40:39.459743 256 : 4250, 4026
7442 12:40:39.463147 260 : 4250, 4027
7443 12:40:39.463233 264 : 4360, 4138
7444 12:40:39.467023 268 : 4249, 4027
7445 12:40:39.467117 272 : 4250, 4027
7446 12:40:39.467185 276 : 4361, 4137
7447 12:40:39.469817 280 : 4250, 4027
7448 12:40:39.469903 284 : 4250, 4027
7449 12:40:39.473098 288 : 4362, 4140
7450 12:40:39.473184 292 : 4250, 4026
7451 12:40:39.476225 296 : 4250, 4027
7452 12:40:39.476352 300 : 4250, 4027
7453 12:40:39.479729 304 : 4252, 4029
7454 12:40:39.479823 308 : 4250, 4026
7455 12:40:39.483129 312 : 4250, 4027
7456 12:40:39.483223 316 : 4360, 4138
7457 12:40:39.486311 320 : 4249, 4027
7458 12:40:39.486400 324 : 4250, 4026
7459 12:40:39.490287 328 : 4361, 4138
7460 12:40:39.490379 332 : 4250, 4001
7461 12:40:39.490447 336 : 4250, 1970
7462 12:40:39.492661
7463 12:40:39.492746 MIOCK jitter meter ch=0
7464 12:40:39.492813
7465 12:40:39.496607 1T = (336-100) = 236 dly cells
7466 12:40:39.502599 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7467 12:40:39.502727 ==
7468 12:40:39.506356 Dram Type= 6, Freq= 0, CH_0, rank 0
7469 12:40:39.509960 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7470 12:40:39.510049 ==
7471 12:40:39.516248 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7472 12:40:39.519221 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7473 12:40:39.522518 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7474 12:40:39.529225 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7475 12:40:39.539000 [CA 0] Center 43 (13~73) winsize 61
7476 12:40:39.541925 [CA 1] Center 42 (12~73) winsize 62
7477 12:40:39.545208 [CA 2] Center 37 (8~67) winsize 60
7478 12:40:39.548877 [CA 3] Center 37 (7~67) winsize 61
7479 12:40:39.551867 [CA 4] Center 36 (6~66) winsize 61
7480 12:40:39.555684 [CA 5] Center 35 (5~66) winsize 62
7481 12:40:39.555785
7482 12:40:39.558442 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7483 12:40:39.558526
7484 12:40:39.565413 [CATrainingPosCal] consider 1 rank data
7485 12:40:39.565505 u2DelayCellTimex100 = 275/100 ps
7486 12:40:39.571507 CA0 delay=43 (13~73),Diff = 8 PI (28 cell)
7487 12:40:39.574656 CA1 delay=42 (12~73),Diff = 7 PI (24 cell)
7488 12:40:39.578371 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7489 12:40:39.581240 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7490 12:40:39.584771 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7491 12:40:39.587702 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7492 12:40:39.587792
7493 12:40:39.591186 CA PerBit enable=1, Macro0, CA PI delay=35
7494 12:40:39.591275
7495 12:40:39.594742 [CBTSetCACLKResult] CA Dly = 35
7496 12:40:39.598046 CS Dly: 10 (0~41)
7497 12:40:39.600964 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7498 12:40:39.604723 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7499 12:40:39.604857 ==
7500 12:40:39.607727 Dram Type= 6, Freq= 0, CH_0, rank 1
7501 12:40:39.614243 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7502 12:40:39.614351 ==
7503 12:40:39.618431 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7504 12:40:39.624394 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7505 12:40:39.627765 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7506 12:40:39.633796 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7507 12:40:39.642009 [CA 0] Center 44 (14~75) winsize 62
7508 12:40:39.645253 [CA 1] Center 44 (14~74) winsize 61
7509 12:40:39.648983 [CA 2] Center 39 (10~69) winsize 60
7510 12:40:39.652643 [CA 3] Center 39 (10~68) winsize 59
7511 12:40:39.655130 [CA 4] Center 37 (7~67) winsize 61
7512 12:40:39.658527 [CA 5] Center 36 (7~66) winsize 60
7513 12:40:39.658620
7514 12:40:39.662524 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7515 12:40:39.662609
7516 12:40:39.668288 [CATrainingPosCal] consider 2 rank data
7517 12:40:39.668381 u2DelayCellTimex100 = 275/100 ps
7518 12:40:39.674973 CA0 delay=43 (14~73),Diff = 7 PI (24 cell)
7519 12:40:39.678219 CA1 delay=43 (14~73),Diff = 7 PI (24 cell)
7520 12:40:39.681516 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7521 12:40:39.685102 CA3 delay=38 (10~67),Diff = 2 PI (7 cell)
7522 12:40:39.687978 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7523 12:40:39.691272 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7524 12:40:39.691367
7525 12:40:39.694533 CA PerBit enable=1, Macro0, CA PI delay=36
7526 12:40:39.694620
7527 12:40:39.698053 [CBTSetCACLKResult] CA Dly = 36
7528 12:40:39.701147 CS Dly: 11 (0~43)
7529 12:40:39.704576 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7530 12:40:39.707968 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7531 12:40:39.708100
7532 12:40:39.711465 ----->DramcWriteLeveling(PI) begin...
7533 12:40:39.714537 ==
7534 12:40:39.718192 Dram Type= 6, Freq= 0, CH_0, rank 0
7535 12:40:39.720964 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7536 12:40:39.721053 ==
7537 12:40:39.724272 Write leveling (Byte 0): 35 => 35
7538 12:40:39.727632 Write leveling (Byte 1): 25 => 25
7539 12:40:39.731015 DramcWriteLeveling(PI) end<-----
7540 12:40:39.731099
7541 12:40:39.731181 ==
7542 12:40:39.734089 Dram Type= 6, Freq= 0, CH_0, rank 0
7543 12:40:39.738139 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7544 12:40:39.738225 ==
7545 12:40:39.740807 [Gating] SW mode calibration
7546 12:40:39.747517 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7547 12:40:39.754141 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7548 12:40:39.757422 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7549 12:40:39.760912 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7550 12:40:39.767359 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7551 12:40:39.770503 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
7552 12:40:39.773829 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7553 12:40:39.780348 1 4 20 | B1->B0 | 2c2c 3434 | 1 1 | (0 0) (1 1)
7554 12:40:39.783888 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7555 12:40:39.787050 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7556 12:40:39.793371 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7557 12:40:39.796904 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7558 12:40:39.800215 1 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
7559 12:40:39.806699 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)
7560 12:40:39.809939 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7561 12:40:39.813543 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
7562 12:40:39.819743 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7563 12:40:39.823242 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7564 12:40:39.826289 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7565 12:40:39.832820 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7566 12:40:39.836208 1 6 8 | B1->B0 | 2323 3231 | 0 1 | (0 0) (0 0)
7567 12:40:39.839470 1 6 12 | B1->B0 | 2323 4544 | 0 1 | (0 0) (0 0)
7568 12:40:39.846148 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7569 12:40:39.849355 1 6 20 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
7570 12:40:39.853014 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7571 12:40:39.859372 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7572 12:40:39.862665 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7573 12:40:39.866319 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7574 12:40:39.872715 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7575 12:40:39.875749 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7576 12:40:39.878950 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7577 12:40:39.885793 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7578 12:40:39.889515 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7579 12:40:39.892177 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 12:40:39.898991 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 12:40:39.902268 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 12:40:39.905802 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 12:40:39.912352 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 12:40:39.915453 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 12:40:39.919167 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 12:40:39.925460 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 12:40:39.928675 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 12:40:39.932045 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 12:40:39.938930 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 12:40:39.941518 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7591 12:40:39.945343 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7592 12:40:39.951231 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7593 12:40:39.955237 Total UI for P1: 0, mck2ui 16
7594 12:40:39.958478 best dqsien dly found for B0: ( 1, 9, 10)
7595 12:40:39.961131 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7596 12:40:39.965215 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7597 12:40:39.971087 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7598 12:40:39.971205 Total UI for P1: 0, mck2ui 16
7599 12:40:39.977672 best dqsien dly found for B1: ( 1, 9, 22)
7600 12:40:39.981354 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7601 12:40:39.984585 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7602 12:40:39.984712
7603 12:40:39.987427 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7604 12:40:39.991164 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7605 12:40:39.994423 [Gating] SW calibration Done
7606 12:40:39.994521 ==
7607 12:40:39.997402 Dram Type= 6, Freq= 0, CH_0, rank 0
7608 12:40:40.001205 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7609 12:40:40.001301 ==
7610 12:40:40.003846 RX Vref Scan: 0
7611 12:40:40.003936
7612 12:40:40.007146 RX Vref 0 -> 0, step: 1
7613 12:40:40.007236
7614 12:40:40.007303 RX Delay 0 -> 252, step: 8
7615 12:40:40.014255 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7616 12:40:40.016856 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7617 12:40:40.020481 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7618 12:40:40.023789 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7619 12:40:40.026952 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7620 12:40:40.033313 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7621 12:40:40.036590 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7622 12:40:40.039740 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7623 12:40:40.043151 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7624 12:40:40.049926 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7625 12:40:40.052938 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7626 12:40:40.056407 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7627 12:40:40.059720 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7628 12:40:40.063415 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7629 12:40:40.069419 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7630 12:40:40.073271 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7631 12:40:40.073371 ==
7632 12:40:40.076549 Dram Type= 6, Freq= 0, CH_0, rank 0
7633 12:40:40.079471 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7634 12:40:40.079563 ==
7635 12:40:40.082481 DQS Delay:
7636 12:40:40.082583 DQS0 = 0, DQS1 = 0
7637 12:40:40.082678 DQM Delay:
7638 12:40:40.086274 DQM0 = 131, DQM1 = 126
7639 12:40:40.086381 DQ Delay:
7640 12:40:40.089422 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7641 12:40:40.092461 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7642 12:40:40.099187 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =123
7643 12:40:40.102226 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
7644 12:40:40.102310
7645 12:40:40.102378
7646 12:40:40.102443 ==
7647 12:40:40.105665 Dram Type= 6, Freq= 0, CH_0, rank 0
7648 12:40:40.108831 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7649 12:40:40.108910 ==
7650 12:40:40.108979
7651 12:40:40.109041
7652 12:40:40.111982 TX Vref Scan disable
7653 12:40:40.115595 == TX Byte 0 ==
7654 12:40:40.118724 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7655 12:40:40.122395 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7656 12:40:40.125186 == TX Byte 1 ==
7657 12:40:40.128675 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7658 12:40:40.132175 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7659 12:40:40.132269 ==
7660 12:40:40.135222 Dram Type= 6, Freq= 0, CH_0, rank 0
7661 12:40:40.141948 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7662 12:40:40.142066 ==
7663 12:40:40.155839
7664 12:40:40.159505 TX Vref early break, caculate TX vref
7665 12:40:40.162324 TX Vref=16, minBit 8, minWin=22, winSum=371
7666 12:40:40.165262 TX Vref=18, minBit 1, minWin=23, winSum=377
7667 12:40:40.169076 TX Vref=20, minBit 1, minWin=23, winSum=386
7668 12:40:40.171893 TX Vref=22, minBit 1, minWin=23, winSum=391
7669 12:40:40.175425 TX Vref=24, minBit 0, minWin=25, winSum=406
7670 12:40:40.182011 TX Vref=26, minBit 1, minWin=25, winSum=414
7671 12:40:40.185496 TX Vref=28, minBit 1, minWin=25, winSum=414
7672 12:40:40.188448 TX Vref=30, minBit 2, minWin=25, winSum=415
7673 12:40:40.191996 TX Vref=32, minBit 1, minWin=24, winSum=406
7674 12:40:40.195265 TX Vref=34, minBit 1, minWin=24, winSum=396
7675 12:40:40.202044 TX Vref=36, minBit 2, minWin=23, winSum=386
7676 12:40:40.204967 [TxChooseVref] Worse bit 2, Min win 25, Win sum 415, Final Vref 30
7677 12:40:40.205060
7678 12:40:40.208694 Final TX Range 0 Vref 30
7679 12:40:40.208775
7680 12:40:40.208839 ==
7681 12:40:40.211521 Dram Type= 6, Freq= 0, CH_0, rank 0
7682 12:40:40.214773 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7683 12:40:40.218230 ==
7684 12:40:40.218310
7685 12:40:40.218384
7686 12:40:40.218449 TX Vref Scan disable
7687 12:40:40.224675 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7688 12:40:40.224794 == TX Byte 0 ==
7689 12:40:40.227904 u2DelayCellOfst[0]=10 cells (3 PI)
7690 12:40:40.231311 u2DelayCellOfst[1]=14 cells (4 PI)
7691 12:40:40.234885 u2DelayCellOfst[2]=10 cells (3 PI)
7692 12:40:40.237837 u2DelayCellOfst[3]=10 cells (3 PI)
7693 12:40:40.241112 u2DelayCellOfst[4]=7 cells (2 PI)
7694 12:40:40.245144 u2DelayCellOfst[5]=0 cells (0 PI)
7695 12:40:40.247982 u2DelayCellOfst[6]=14 cells (4 PI)
7696 12:40:40.251070 u2DelayCellOfst[7]=17 cells (5 PI)
7697 12:40:40.254719 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7698 12:40:40.257892 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7699 12:40:40.260921 == TX Byte 1 ==
7700 12:40:40.264010 u2DelayCellOfst[8]=0 cells (0 PI)
7701 12:40:40.268008 u2DelayCellOfst[9]=0 cells (0 PI)
7702 12:40:40.270637 u2DelayCellOfst[10]=3 cells (1 PI)
7703 12:40:40.274588 u2DelayCellOfst[11]=0 cells (0 PI)
7704 12:40:40.277619 u2DelayCellOfst[12]=7 cells (2 PI)
7705 12:40:40.280894 u2DelayCellOfst[13]=7 cells (2 PI)
7706 12:40:40.284207 u2DelayCellOfst[14]=14 cells (4 PI)
7707 12:40:40.284338 u2DelayCellOfst[15]=7 cells (2 PI)
7708 12:40:40.290568 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7709 12:40:40.293906 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7710 12:40:40.297234 DramC Write-DBI on
7711 12:40:40.297354 ==
7712 12:40:40.300636 Dram Type= 6, Freq= 0, CH_0, rank 0
7713 12:40:40.303637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7714 12:40:40.303750 ==
7715 12:40:40.303848
7716 12:40:40.303939
7717 12:40:40.307134 TX Vref Scan disable
7718 12:40:40.310432 == TX Byte 0 ==
7719 12:40:40.313528 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7720 12:40:40.313643 == TX Byte 1 ==
7721 12:40:40.319995 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7722 12:40:40.320158 DramC Write-DBI off
7723 12:40:40.320255
7724 12:40:40.320345 [DATLAT]
7725 12:40:40.323222 Freq=1600, CH0 RK0
7726 12:40:40.323329
7727 12:40:40.326990 DATLAT Default: 0xf
7728 12:40:40.327099 0, 0xFFFF, sum = 0
7729 12:40:40.329771 1, 0xFFFF, sum = 0
7730 12:40:40.329879 2, 0xFFFF, sum = 0
7731 12:40:40.333120 3, 0xFFFF, sum = 0
7732 12:40:40.333230 4, 0xFFFF, sum = 0
7733 12:40:40.336336 5, 0xFFFF, sum = 0
7734 12:40:40.336450 6, 0xFFFF, sum = 0
7735 12:40:40.339559 7, 0xFFFF, sum = 0
7736 12:40:40.339669 8, 0xFFFF, sum = 0
7737 12:40:40.342827 9, 0xFFFF, sum = 0
7738 12:40:40.342937 10, 0xFFFF, sum = 0
7739 12:40:40.346271 11, 0xFFFF, sum = 0
7740 12:40:40.349985 12, 0xFFFF, sum = 0
7741 12:40:40.350103 13, 0xFFFF, sum = 0
7742 12:40:40.352846 14, 0x0, sum = 1
7743 12:40:40.352938 15, 0x0, sum = 2
7744 12:40:40.353007 16, 0x0, sum = 3
7745 12:40:40.355874 17, 0x0, sum = 4
7746 12:40:40.355961 best_step = 15
7747 12:40:40.356029
7748 12:40:40.359232 ==
7749 12:40:40.359318 Dram Type= 6, Freq= 0, CH_0, rank 0
7750 12:40:40.366376 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7751 12:40:40.366479 ==
7752 12:40:40.366550 RX Vref Scan: 1
7753 12:40:40.366612
7754 12:40:40.369238 Set Vref Range= 24 -> 127
7755 12:40:40.369324
7756 12:40:40.372966 RX Vref 24 -> 127, step: 1
7757 12:40:40.373053
7758 12:40:40.375889 RX Delay 11 -> 252, step: 4
7759 12:40:40.375973
7760 12:40:40.378889 Set Vref, RX VrefLevel [Byte0]: 24
7761 12:40:40.382352 [Byte1]: 24
7762 12:40:40.382445
7763 12:40:40.385426 Set Vref, RX VrefLevel [Byte0]: 25
7764 12:40:40.389555 [Byte1]: 25
7765 12:40:40.389644
7766 12:40:40.392016 Set Vref, RX VrefLevel [Byte0]: 26
7767 12:40:40.395522 [Byte1]: 26
7768 12:40:40.399638
7769 12:40:40.399727 Set Vref, RX VrefLevel [Byte0]: 27
7770 12:40:40.402552 [Byte1]: 27
7771 12:40:40.406966
7772 12:40:40.407058 Set Vref, RX VrefLevel [Byte0]: 28
7773 12:40:40.410270 [Byte1]: 28
7774 12:40:40.414308
7775 12:40:40.414401 Set Vref, RX VrefLevel [Byte0]: 29
7776 12:40:40.417638 [Byte1]: 29
7777 12:40:40.422421
7778 12:40:40.422506 Set Vref, RX VrefLevel [Byte0]: 30
7779 12:40:40.425676 [Byte1]: 30
7780 12:40:40.430108
7781 12:40:40.430192 Set Vref, RX VrefLevel [Byte0]: 31
7782 12:40:40.432799 [Byte1]: 31
7783 12:40:40.437165
7784 12:40:40.437252 Set Vref, RX VrefLevel [Byte0]: 32
7785 12:40:40.440453 [Byte1]: 32
7786 12:40:40.445048
7787 12:40:40.445134 Set Vref, RX VrefLevel [Byte0]: 33
7788 12:40:40.448246 [Byte1]: 33
7789 12:40:40.452399
7790 12:40:40.452500 Set Vref, RX VrefLevel [Byte0]: 34
7791 12:40:40.455933 [Byte1]: 34
7792 12:40:40.460147
7793 12:40:40.460241 Set Vref, RX VrefLevel [Byte0]: 35
7794 12:40:40.463242 [Byte1]: 35
7795 12:40:40.467837
7796 12:40:40.467952 Set Vref, RX VrefLevel [Byte0]: 36
7797 12:40:40.470877 [Byte1]: 36
7798 12:40:40.475355
7799 12:40:40.475441 Set Vref, RX VrefLevel [Byte0]: 37
7800 12:40:40.478889 [Byte1]: 37
7801 12:40:40.483030
7802 12:40:40.483117 Set Vref, RX VrefLevel [Byte0]: 38
7803 12:40:40.486456 [Byte1]: 38
7804 12:40:40.490479
7805 12:40:40.490579 Set Vref, RX VrefLevel [Byte0]: 39
7806 12:40:40.493659 [Byte1]: 39
7807 12:40:40.498063
7808 12:40:40.498155 Set Vref, RX VrefLevel [Byte0]: 40
7809 12:40:40.501666 [Byte1]: 40
7810 12:40:40.505684
7811 12:40:40.505767 Set Vref, RX VrefLevel [Byte0]: 41
7812 12:40:40.509305 [Byte1]: 41
7813 12:40:40.513482
7814 12:40:40.513566 Set Vref, RX VrefLevel [Byte0]: 42
7815 12:40:40.516670 [Byte1]: 42
7816 12:40:40.520786
7817 12:40:40.520870 Set Vref, RX VrefLevel [Byte0]: 43
7818 12:40:40.524190 [Byte1]: 43
7819 12:40:40.528781
7820 12:40:40.528865 Set Vref, RX VrefLevel [Byte0]: 44
7821 12:40:40.532715 [Byte1]: 44
7822 12:40:40.536196
7823 12:40:40.536278 Set Vref, RX VrefLevel [Byte0]: 45
7824 12:40:40.539851 [Byte1]: 45
7825 12:40:40.543862
7826 12:40:40.543976 Set Vref, RX VrefLevel [Byte0]: 46
7827 12:40:40.547614 [Byte1]: 46
7828 12:40:40.551949
7829 12:40:40.552041 Set Vref, RX VrefLevel [Byte0]: 47
7830 12:40:40.554745 [Byte1]: 47
7831 12:40:40.559073
7832 12:40:40.559161 Set Vref, RX VrefLevel [Byte0]: 48
7833 12:40:40.562334 [Byte1]: 48
7834 12:40:40.566702
7835 12:40:40.566792 Set Vref, RX VrefLevel [Byte0]: 49
7836 12:40:40.569883 [Byte1]: 49
7837 12:40:40.573954
7838 12:40:40.574038 Set Vref, RX VrefLevel [Byte0]: 50
7839 12:40:40.577467 [Byte1]: 50
7840 12:40:40.582180
7841 12:40:40.582272 Set Vref, RX VrefLevel [Byte0]: 51
7842 12:40:40.585496 [Byte1]: 51
7843 12:40:40.589727
7844 12:40:40.589812 Set Vref, RX VrefLevel [Byte0]: 52
7845 12:40:40.596311 [Byte1]: 52
7846 12:40:40.596405
7847 12:40:40.599584 Set Vref, RX VrefLevel [Byte0]: 53
7848 12:40:40.602342 [Byte1]: 53
7849 12:40:40.602426
7850 12:40:40.605876 Set Vref, RX VrefLevel [Byte0]: 54
7851 12:40:40.608956 [Byte1]: 54
7852 12:40:40.612559
7853 12:40:40.612642 Set Vref, RX VrefLevel [Byte0]: 55
7854 12:40:40.615393 [Byte1]: 55
7855 12:40:40.619932
7856 12:40:40.620019 Set Vref, RX VrefLevel [Byte0]: 56
7857 12:40:40.623458 [Byte1]: 56
7858 12:40:40.627837
7859 12:40:40.627922 Set Vref, RX VrefLevel [Byte0]: 57
7860 12:40:40.631255 [Byte1]: 57
7861 12:40:40.635776
7862 12:40:40.635869 Set Vref, RX VrefLevel [Byte0]: 58
7863 12:40:40.638499 [Byte1]: 58
7864 12:40:40.642944
7865 12:40:40.643028 Set Vref, RX VrefLevel [Byte0]: 59
7866 12:40:40.646198 [Byte1]: 59
7867 12:40:40.650349
7868 12:40:40.650432 Set Vref, RX VrefLevel [Byte0]: 60
7869 12:40:40.653946 [Byte1]: 60
7870 12:40:40.657844
7871 12:40:40.657928 Set Vref, RX VrefLevel [Byte0]: 61
7872 12:40:40.661415 [Byte1]: 61
7873 12:40:40.665772
7874 12:40:40.665858 Set Vref, RX VrefLevel [Byte0]: 62
7875 12:40:40.668675 [Byte1]: 62
7876 12:40:40.673097
7877 12:40:40.673181 Set Vref, RX VrefLevel [Byte0]: 63
7878 12:40:40.676768 [Byte1]: 63
7879 12:40:40.680902
7880 12:40:40.680990 Set Vref, RX VrefLevel [Byte0]: 64
7881 12:40:40.684171 [Byte1]: 64
7882 12:40:40.688392
7883 12:40:40.688479 Set Vref, RX VrefLevel [Byte0]: 65
7884 12:40:40.694925 [Byte1]: 65
7885 12:40:40.695013
7886 12:40:40.698020 Set Vref, RX VrefLevel [Byte0]: 66
7887 12:40:40.701505 [Byte1]: 66
7888 12:40:40.701589
7889 12:40:40.704695 Set Vref, RX VrefLevel [Byte0]: 67
7890 12:40:40.708649 [Byte1]: 67
7891 12:40:40.711102
7892 12:40:40.711184 Set Vref, RX VrefLevel [Byte0]: 68
7893 12:40:40.714414 [Byte1]: 68
7894 12:40:40.719187
7895 12:40:40.719271 Set Vref, RX VrefLevel [Byte0]: 69
7896 12:40:40.722072 [Byte1]: 69
7897 12:40:40.726389
7898 12:40:40.726472 Set Vref, RX VrefLevel [Byte0]: 70
7899 12:40:40.729972 [Byte1]: 70
7900 12:40:40.734082
7901 12:40:40.734166 Set Vref, RX VrefLevel [Byte0]: 71
7902 12:40:40.737377 [Byte1]: 71
7903 12:40:40.741716
7904 12:40:40.741802 Set Vref, RX VrefLevel [Byte0]: 72
7905 12:40:40.744905 [Byte1]: 72
7906 12:40:40.749358
7907 12:40:40.749443 Set Vref, RX VrefLevel [Byte0]: 73
7908 12:40:40.752750 [Byte1]: 73
7909 12:40:40.757029
7910 12:40:40.757114 Set Vref, RX VrefLevel [Byte0]: 74
7911 12:40:40.760358 [Byte1]: 74
7912 12:40:40.764344
7913 12:40:40.764429 Final RX Vref Byte 0 = 59 to rank0
7914 12:40:40.768000 Final RX Vref Byte 1 = 56 to rank0
7915 12:40:40.771132 Final RX Vref Byte 0 = 59 to rank1
7916 12:40:40.774545 Final RX Vref Byte 1 = 56 to rank1==
7917 12:40:40.777657 Dram Type= 6, Freq= 0, CH_0, rank 0
7918 12:40:40.784453 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7919 12:40:40.784615 ==
7920 12:40:40.784703 DQS Delay:
7921 12:40:40.787710 DQS0 = 0, DQS1 = 0
7922 12:40:40.787801 DQM Delay:
7923 12:40:40.787868 DQM0 = 128, DQM1 = 124
7924 12:40:40.791237 DQ Delay:
7925 12:40:40.794329 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7926 12:40:40.797911 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134
7927 12:40:40.801695 DQ8 =112, DQ9 =110, DQ10 =126, DQ11 =120
7928 12:40:40.804197 DQ12 =130, DQ13 =130, DQ14 =134, DQ15 =132
7929 12:40:40.804286
7930 12:40:40.804352
7931 12:40:40.804412
7932 12:40:40.807998 [DramC_TX_OE_Calibration] TA2
7933 12:40:40.811080 Original DQ_B0 (3 6) =30, OEN = 27
7934 12:40:40.814294 Original DQ_B1 (3 6) =30, OEN = 27
7935 12:40:40.817482 24, 0x0, End_B0=24 End_B1=24
7936 12:40:40.821051 25, 0x0, End_B0=25 End_B1=25
7937 12:40:40.821138 26, 0x0, End_B0=26 End_B1=26
7938 12:40:40.823900 27, 0x0, End_B0=27 End_B1=27
7939 12:40:40.827319 28, 0x0, End_B0=28 End_B1=28
7940 12:40:40.830576 29, 0x0, End_B0=29 End_B1=29
7941 12:40:40.830663 30, 0x0, End_B0=30 End_B1=30
7942 12:40:40.833577 31, 0x4141, End_B0=30 End_B1=30
7943 12:40:40.837239 Byte0 end_step=30 best_step=27
7944 12:40:40.840492 Byte1 end_step=30 best_step=27
7945 12:40:40.843461 Byte0 TX OE(2T, 0.5T) = (3, 3)
7946 12:40:40.846588 Byte1 TX OE(2T, 0.5T) = (3, 3)
7947 12:40:40.846671
7948 12:40:40.846775
7949 12:40:40.853714 [DQSOSCAuto] RK0, (LSB)MR18= 0x1916, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
7950 12:40:40.856822 CH0 RK0: MR19=303, MR18=1916
7951 12:40:40.863359 CH0_RK0: MR19=0x303, MR18=0x1916, DQSOSC=397, MR23=63, INC=23, DEC=15
7952 12:40:40.863457
7953 12:40:40.866701 ----->DramcWriteLeveling(PI) begin...
7954 12:40:40.866788 ==
7955 12:40:40.869907 Dram Type= 6, Freq= 0, CH_0, rank 1
7956 12:40:40.873042 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7957 12:40:40.873129 ==
7958 12:40:40.876893 Write leveling (Byte 0): 35 => 35
7959 12:40:40.879940 Write leveling (Byte 1): 27 => 27
7960 12:40:40.882953 DramcWriteLeveling(PI) end<-----
7961 12:40:40.883041
7962 12:40:40.883107 ==
7963 12:40:40.886622 Dram Type= 6, Freq= 0, CH_0, rank 1
7964 12:40:40.892918 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7965 12:40:40.893032 ==
7966 12:40:40.893101 [Gating] SW mode calibration
7967 12:40:40.902823 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7968 12:40:40.906063 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7969 12:40:40.909574 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7970 12:40:40.916621 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7971 12:40:40.919185 1 4 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
7972 12:40:40.925889 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7973 12:40:40.929193 1 4 16 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
7974 12:40:40.932400 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7975 12:40:40.939375 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7976 12:40:40.942233 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7977 12:40:40.945643 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7978 12:40:40.951954 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7979 12:40:40.955613 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7980 12:40:40.958669 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
7981 12:40:40.965713 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7982 12:40:40.968889 1 5 20 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
7983 12:40:40.971818 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7984 12:40:40.978599 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7985 12:40:40.981748 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7986 12:40:40.984980 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7987 12:40:40.991864 1 6 8 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
7988 12:40:40.994957 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7989 12:40:40.998075 1 6 16 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
7990 12:40:41.005196 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7991 12:40:41.007892 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7992 12:40:41.011061 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7993 12:40:41.018285 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7994 12:40:41.021183 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7995 12:40:41.024345 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7996 12:40:41.031226 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7997 12:40:41.034621 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7998 12:40:41.037946 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7999 12:40:41.043974 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 12:40:41.047655 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 12:40:41.050806 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 12:40:41.057561 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 12:40:41.060661 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 12:40:41.063816 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 12:40:41.070577 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 12:40:41.073502 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 12:40:41.077611 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 12:40:41.083510 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 12:40:41.086717 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 12:40:41.090260 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 12:40:41.096834 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8012 12:40:41.099909 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8013 12:40:41.103355 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8014 12:40:41.106877 Total UI for P1: 0, mck2ui 16
8015 12:40:41.109683 best dqsien dly found for B0: ( 1, 9, 10)
8016 12:40:41.116339 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8017 12:40:41.120273 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8018 12:40:41.123528 Total UI for P1: 0, mck2ui 16
8019 12:40:41.126130 best dqsien dly found for B1: ( 1, 9, 18)
8020 12:40:41.129550 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8021 12:40:41.133026 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8022 12:40:41.133105
8023 12:40:41.136457 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8024 12:40:41.139640 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8025 12:40:41.142878 [Gating] SW calibration Done
8026 12:40:41.142958 ==
8027 12:40:41.146175 Dram Type= 6, Freq= 0, CH_0, rank 1
8028 12:40:41.153082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8029 12:40:41.153162 ==
8030 12:40:41.153245 RX Vref Scan: 0
8031 12:40:41.153331
8032 12:40:41.156382 RX Vref 0 -> 0, step: 1
8033 12:40:41.156458
8034 12:40:41.159414 RX Delay 0 -> 252, step: 8
8035 12:40:41.162706 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8036 12:40:41.166153 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8037 12:40:41.169146 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
8038 12:40:41.172694 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8039 12:40:41.179249 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8040 12:40:41.182698 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8041 12:40:41.185288 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8042 12:40:41.189212 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8043 12:40:41.195618 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8044 12:40:41.198957 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8045 12:40:41.201929 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8046 12:40:41.205308 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8047 12:40:41.208454 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8048 12:40:41.215149 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8049 12:40:41.218413 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8050 12:40:41.221575 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8051 12:40:41.221666 ==
8052 12:40:41.224989 Dram Type= 6, Freq= 0, CH_0, rank 1
8053 12:40:41.228783 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8054 12:40:41.231896 ==
8055 12:40:41.232004 DQS Delay:
8056 12:40:41.232117 DQS0 = 0, DQS1 = 0
8057 12:40:41.234912 DQM Delay:
8058 12:40:41.234994 DQM0 = 132, DQM1 = 127
8059 12:40:41.238664 DQ Delay:
8060 12:40:41.241709 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =127
8061 12:40:41.244992 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =143
8062 12:40:41.248414 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =123
8063 12:40:41.251991 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8064 12:40:41.252121
8065 12:40:41.252187
8066 12:40:41.252248 ==
8067 12:40:41.254956 Dram Type= 6, Freq= 0, CH_0, rank 1
8068 12:40:41.258036 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8069 12:40:41.258119 ==
8070 12:40:41.261431
8071 12:40:41.261512
8072 12:40:41.261577 TX Vref Scan disable
8073 12:40:41.264543 == TX Byte 0 ==
8074 12:40:41.268015 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8075 12:40:41.271313 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8076 12:40:41.275028 == TX Byte 1 ==
8077 12:40:41.278097 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8078 12:40:41.281162 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8079 12:40:41.281248 ==
8080 12:40:41.284627 Dram Type= 6, Freq= 0, CH_0, rank 1
8081 12:40:41.290990 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8082 12:40:41.291075 ==
8083 12:40:41.303640
8084 12:40:41.307003 TX Vref early break, caculate TX vref
8085 12:40:41.310165 TX Vref=16, minBit 9, minWin=22, winSum=381
8086 12:40:41.313683 TX Vref=18, minBit 1, minWin=24, winSum=392
8087 12:40:41.316973 TX Vref=20, minBit 2, minWin=24, winSum=399
8088 12:40:41.320270 TX Vref=22, minBit 0, minWin=25, winSum=405
8089 12:40:41.323505 TX Vref=24, minBit 2, minWin=24, winSum=411
8090 12:40:41.329844 TX Vref=26, minBit 4, minWin=25, winSum=421
8091 12:40:41.333275 TX Vref=28, minBit 3, minWin=25, winSum=423
8092 12:40:41.336236 TX Vref=30, minBit 1, minWin=25, winSum=417
8093 12:40:41.339565 TX Vref=32, minBit 0, minWin=24, winSum=406
8094 12:40:41.342973 TX Vref=34, minBit 0, minWin=24, winSum=399
8095 12:40:41.349671 [TxChooseVref] Worse bit 3, Min win 25, Win sum 423, Final Vref 28
8096 12:40:41.349760
8097 12:40:41.352924 Final TX Range 0 Vref 28
8098 12:40:41.353009
8099 12:40:41.353073 ==
8100 12:40:41.356326 Dram Type= 6, Freq= 0, CH_0, rank 1
8101 12:40:41.359596 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8102 12:40:41.359680 ==
8103 12:40:41.359745
8104 12:40:41.359805
8105 12:40:41.362653 TX Vref Scan disable
8106 12:40:41.369305 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8107 12:40:41.369391 == TX Byte 0 ==
8108 12:40:41.372679 u2DelayCellOfst[0]=10 cells (3 PI)
8109 12:40:41.375854 u2DelayCellOfst[1]=14 cells (4 PI)
8110 12:40:41.379346 u2DelayCellOfst[2]=7 cells (2 PI)
8111 12:40:41.382663 u2DelayCellOfst[3]=10 cells (3 PI)
8112 12:40:41.386246 u2DelayCellOfst[4]=7 cells (2 PI)
8113 12:40:41.389455 u2DelayCellOfst[5]=0 cells (0 PI)
8114 12:40:41.392654 u2DelayCellOfst[6]=14 cells (4 PI)
8115 12:40:41.395819 u2DelayCellOfst[7]=14 cells (4 PI)
8116 12:40:41.399046 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8117 12:40:41.402884 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8118 12:40:41.406311 == TX Byte 1 ==
8119 12:40:41.409303 u2DelayCellOfst[8]=0 cells (0 PI)
8120 12:40:41.412687 u2DelayCellOfst[9]=0 cells (0 PI)
8121 12:40:41.415455 u2DelayCellOfst[10]=7 cells (2 PI)
8122 12:40:41.418971 u2DelayCellOfst[11]=3 cells (1 PI)
8123 12:40:41.419059 u2DelayCellOfst[12]=10 cells (3 PI)
8124 12:40:41.422269 u2DelayCellOfst[13]=10 cells (3 PI)
8125 12:40:41.425988 u2DelayCellOfst[14]=17 cells (5 PI)
8126 12:40:41.428703 u2DelayCellOfst[15]=10 cells (3 PI)
8127 12:40:41.435111 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8128 12:40:41.438619 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8129 12:40:41.438711 DramC Write-DBI on
8130 12:40:41.442194 ==
8131 12:40:41.445068 Dram Type= 6, Freq= 0, CH_0, rank 1
8132 12:40:41.448465 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8133 12:40:41.448551 ==
8134 12:40:41.448619
8135 12:40:41.448683
8136 12:40:41.451757 TX Vref Scan disable
8137 12:40:41.451842 == TX Byte 0 ==
8138 12:40:41.458556 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8139 12:40:41.458650 == TX Byte 1 ==
8140 12:40:41.461577 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8141 12:40:41.464931 DramC Write-DBI off
8142 12:40:41.465024
8143 12:40:41.465091 [DATLAT]
8144 12:40:41.468495 Freq=1600, CH0 RK1
8145 12:40:41.468579
8146 12:40:41.468647 DATLAT Default: 0xf
8147 12:40:41.471557 0, 0xFFFF, sum = 0
8148 12:40:41.471642 1, 0xFFFF, sum = 0
8149 12:40:41.475068 2, 0xFFFF, sum = 0
8150 12:40:41.478110 3, 0xFFFF, sum = 0
8151 12:40:41.478195 4, 0xFFFF, sum = 0
8152 12:40:41.481379 5, 0xFFFF, sum = 0
8153 12:40:41.481466 6, 0xFFFF, sum = 0
8154 12:40:41.484491 7, 0xFFFF, sum = 0
8155 12:40:41.484574 8, 0xFFFF, sum = 0
8156 12:40:41.488336 9, 0xFFFF, sum = 0
8157 12:40:41.488422 10, 0xFFFF, sum = 0
8158 12:40:41.491409 11, 0xFFFF, sum = 0
8159 12:40:41.491493 12, 0xFFFF, sum = 0
8160 12:40:41.495051 13, 0xFFFF, sum = 0
8161 12:40:41.495137 14, 0x0, sum = 1
8162 12:40:41.498115 15, 0x0, sum = 2
8163 12:40:41.498200 16, 0x0, sum = 3
8164 12:40:41.501227 17, 0x0, sum = 4
8165 12:40:41.501312 best_step = 15
8166 12:40:41.501386
8167 12:40:41.501450 ==
8168 12:40:41.504491 Dram Type= 6, Freq= 0, CH_0, rank 1
8169 12:40:41.511193 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8170 12:40:41.511283 ==
8171 12:40:41.511351 RX Vref Scan: 0
8172 12:40:41.511414
8173 12:40:41.515059 RX Vref 0 -> 0, step: 1
8174 12:40:41.515149
8175 12:40:41.517624 RX Delay 11 -> 252, step: 4
8176 12:40:41.521023 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8177 12:40:41.525187 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8178 12:40:41.527438 iDelay=191, Bit 2, Center 124 (75 ~ 174) 100
8179 12:40:41.534442 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8180 12:40:41.537757 iDelay=191, Bit 4, Center 130 (83 ~ 178) 96
8181 12:40:41.541296 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8182 12:40:41.544004 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8183 12:40:41.547388 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8184 12:40:41.553573 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8185 12:40:41.557219 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8186 12:40:41.561010 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8187 12:40:41.563812 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8188 12:40:41.570694 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8189 12:40:41.573353 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8190 12:40:41.576877 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8191 12:40:41.579950 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8192 12:40:41.580093 ==
8193 12:40:41.583327 Dram Type= 6, Freq= 0, CH_0, rank 1
8194 12:40:41.589598 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8195 12:40:41.589687 ==
8196 12:40:41.589755 DQS Delay:
8197 12:40:41.593363 DQS0 = 0, DQS1 = 0
8198 12:40:41.593447 DQM Delay:
8199 12:40:41.597052 DQM0 = 128, DQM1 = 124
8200 12:40:41.597137 DQ Delay:
8201 12:40:41.599974 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8202 12:40:41.602776 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =134
8203 12:40:41.607017 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8204 12:40:41.609673 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =132
8205 12:40:41.609757
8206 12:40:41.609840
8207 12:40:41.609908
8208 12:40:41.612916 [DramC_TX_OE_Calibration] TA2
8209 12:40:41.616487 Original DQ_B0 (3 6) =30, OEN = 27
8210 12:40:41.619450 Original DQ_B1 (3 6) =30, OEN = 27
8211 12:40:41.623350 24, 0x0, End_B0=24 End_B1=24
8212 12:40:41.625869 25, 0x0, End_B0=25 End_B1=25
8213 12:40:41.625958 26, 0x0, End_B0=26 End_B1=26
8214 12:40:41.629414 27, 0x0, End_B0=27 End_B1=27
8215 12:40:41.632972 28, 0x0, End_B0=28 End_B1=28
8216 12:40:41.636432 29, 0x0, End_B0=29 End_B1=29
8217 12:40:41.636517 30, 0x0, End_B0=30 End_B1=30
8218 12:40:41.639032 31, 0x4141, End_B0=30 End_B1=30
8219 12:40:41.642543 Byte0 end_step=30 best_step=27
8220 12:40:41.645906 Byte1 end_step=30 best_step=27
8221 12:40:41.649277 Byte0 TX OE(2T, 0.5T) = (3, 3)
8222 12:40:41.652469 Byte1 TX OE(2T, 0.5T) = (3, 3)
8223 12:40:41.652666
8224 12:40:41.652738
8225 12:40:41.659153 [DQSOSCAuto] RK1, (LSB)MR18= 0x1110, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
8226 12:40:41.662503 CH0 RK1: MR19=303, MR18=1110
8227 12:40:41.669198 CH0_RK1: MR19=0x303, MR18=0x1110, DQSOSC=401, MR23=63, INC=22, DEC=15
8228 12:40:41.672118 [RxdqsGatingPostProcess] freq 1600
8229 12:40:41.678725 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8230 12:40:41.678847 best DQS0 dly(2T, 0.5T) = (1, 1)
8231 12:40:41.682396 best DQS1 dly(2T, 0.5T) = (1, 1)
8232 12:40:41.685441 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8233 12:40:41.688869 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8234 12:40:41.691869 best DQS0 dly(2T, 0.5T) = (1, 1)
8235 12:40:41.695537 best DQS1 dly(2T, 0.5T) = (1, 1)
8236 12:40:41.698628 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8237 12:40:41.701913 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8238 12:40:41.705050 Pre-setting of DQS Precalculation
8239 12:40:41.709244 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8240 12:40:41.709332 ==
8241 12:40:41.712470 Dram Type= 6, Freq= 0, CH_1, rank 0
8242 12:40:41.718195 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8243 12:40:41.718283 ==
8244 12:40:41.721782 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8245 12:40:41.727989 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8246 12:40:41.731733 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8247 12:40:41.738304 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8248 12:40:41.746793 [CA 0] Center 41 (11~71) winsize 61
8249 12:40:41.749704 [CA 1] Center 42 (12~72) winsize 61
8250 12:40:41.752937 [CA 2] Center 38 (9~67) winsize 59
8251 12:40:41.756171 [CA 3] Center 36 (7~66) winsize 60
8252 12:40:41.759273 [CA 4] Center 37 (7~68) winsize 62
8253 12:40:41.762471 [CA 5] Center 36 (6~66) winsize 61
8254 12:40:41.762557
8255 12:40:41.766424 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8256 12:40:41.766510
8257 12:40:41.772566 [CATrainingPosCal] consider 1 rank data
8258 12:40:41.772670 u2DelayCellTimex100 = 275/100 ps
8259 12:40:41.779593 CA0 delay=41 (11~71),Diff = 5 PI (17 cell)
8260 12:40:41.782530 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8261 12:40:41.785819 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8262 12:40:41.789160 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8263 12:40:41.792257 CA4 delay=37 (7~68),Diff = 1 PI (3 cell)
8264 12:40:41.795952 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8265 12:40:41.796083
8266 12:40:41.799182 CA PerBit enable=1, Macro0, CA PI delay=36
8267 12:40:41.799266
8268 12:40:41.802742 [CBTSetCACLKResult] CA Dly = 36
8269 12:40:41.805878 CS Dly: 8 (0~39)
8270 12:40:41.808832 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8271 12:40:41.812221 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8272 12:40:41.812308 ==
8273 12:40:41.815697 Dram Type= 6, Freq= 0, CH_1, rank 1
8274 12:40:41.822310 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8275 12:40:41.822412 ==
8276 12:40:41.825507 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8277 12:40:41.831867 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8278 12:40:41.835069 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8279 12:40:41.841425 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8280 12:40:41.849719 [CA 0] Center 42 (12~72) winsize 61
8281 12:40:41.852522 [CA 1] Center 43 (14~72) winsize 59
8282 12:40:41.856407 [CA 2] Center 38 (9~68) winsize 60
8283 12:40:41.859136 [CA 3] Center 36 (7~66) winsize 60
8284 12:40:41.862586 [CA 4] Center 37 (7~68) winsize 62
8285 12:40:41.865865 [CA 5] Center 37 (8~67) winsize 60
8286 12:40:41.865944
8287 12:40:41.869092 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8288 12:40:41.869202
8289 12:40:41.875830 [CATrainingPosCal] consider 2 rank data
8290 12:40:41.875919 u2DelayCellTimex100 = 275/100 ps
8291 12:40:41.882491 CA0 delay=41 (12~71),Diff = 5 PI (17 cell)
8292 12:40:41.885545 CA1 delay=43 (14~72),Diff = 7 PI (24 cell)
8293 12:40:41.888884 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8294 12:40:41.892537 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8295 12:40:41.895732 CA4 delay=37 (7~68),Diff = 1 PI (3 cell)
8296 12:40:41.898570 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8297 12:40:41.898654
8298 12:40:41.902018 CA PerBit enable=1, Macro0, CA PI delay=36
8299 12:40:41.902102
8300 12:40:41.905426 [CBTSetCACLKResult] CA Dly = 36
8301 12:40:41.908549 CS Dly: 10 (0~43)
8302 12:40:41.912220 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8303 12:40:41.915475 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8304 12:40:41.915563
8305 12:40:41.918928 ----->DramcWriteLeveling(PI) begin...
8306 12:40:41.919015 ==
8307 12:40:41.921738 Dram Type= 6, Freq= 0, CH_1, rank 0
8308 12:40:41.928308 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8309 12:40:41.928438 ==
8310 12:40:41.931627 Write leveling (Byte 0): 26 => 26
8311 12:40:41.934887 Write leveling (Byte 1): 28 => 28
8312 12:40:41.934971 DramcWriteLeveling(PI) end<-----
8313 12:40:41.938795
8314 12:40:41.938878 ==
8315 12:40:41.942493 Dram Type= 6, Freq= 0, CH_1, rank 0
8316 12:40:41.944862 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8317 12:40:41.944944 ==
8318 12:40:41.948182 [Gating] SW mode calibration
8319 12:40:41.954832 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8320 12:40:41.958100 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8321 12:40:41.964926 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8322 12:40:41.968150 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8323 12:40:41.971596 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8324 12:40:41.977872 1 4 12 | B1->B0 | 2525 3333 | 0 0 | (0 0) (0 0)
8325 12:40:41.981245 1 4 16 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8326 12:40:41.984736 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8327 12:40:41.991357 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8328 12:40:41.995185 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8329 12:40:41.998483 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8330 12:40:42.004310 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8331 12:40:42.007926 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8332 12:40:42.014237 1 5 12 | B1->B0 | 3030 2525 | 0 0 | (0 1) (1 0)
8333 12:40:42.017424 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8334 12:40:42.020570 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8335 12:40:42.026983 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8336 12:40:42.030745 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8337 12:40:42.034022 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8338 12:40:42.040702 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8339 12:40:42.044215 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8340 12:40:42.046917 1 6 12 | B1->B0 | 3131 4444 | 0 0 | (0 0) (0 0)
8341 12:40:42.053648 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8342 12:40:42.056636 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8343 12:40:42.060081 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8344 12:40:42.066654 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8345 12:40:42.070022 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8346 12:40:42.073544 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8347 12:40:42.079994 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8348 12:40:42.083074 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8349 12:40:42.086628 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8350 12:40:42.093209 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 12:40:42.096410 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 12:40:42.099633 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 12:40:42.106043 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 12:40:42.109169 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 12:40:42.112627 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 12:40:42.119334 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 12:40:42.122585 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 12:40:42.125930 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 12:40:42.132447 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 12:40:42.135764 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 12:40:42.139227 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 12:40:42.145996 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 12:40:42.149124 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8364 12:40:42.152183 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8365 12:40:42.155946 Total UI for P1: 0, mck2ui 16
8366 12:40:42.158688 best dqsien dly found for B0: ( 1, 9, 8)
8367 12:40:42.165293 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8368 12:40:42.168571 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 12:40:42.171940 Total UI for P1: 0, mck2ui 16
8370 12:40:42.175307 best dqsien dly found for B1: ( 1, 9, 12)
8371 12:40:42.178439 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8372 12:40:42.181552 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8373 12:40:42.181668
8374 12:40:42.185559 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8375 12:40:42.188482 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8376 12:40:42.191713 [Gating] SW calibration Done
8377 12:40:42.191790 ==
8378 12:40:42.194838 Dram Type= 6, Freq= 0, CH_1, rank 0
8379 12:40:42.198636 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8380 12:40:42.201524 ==
8381 12:40:42.201596 RX Vref Scan: 0
8382 12:40:42.201657
8383 12:40:42.204944 RX Vref 0 -> 0, step: 1
8384 12:40:42.205014
8385 12:40:42.208339 RX Delay 0 -> 252, step: 8
8386 12:40:42.211244 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8387 12:40:42.214601 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8388 12:40:42.218276 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8389 12:40:42.221010 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8390 12:40:42.227910 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8391 12:40:42.231519 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8392 12:40:42.234259 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8393 12:40:42.237977 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8394 12:40:42.241405 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8395 12:40:42.247839 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8396 12:40:42.250703 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8397 12:40:42.254394 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8398 12:40:42.257641 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8399 12:40:42.264369 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8400 12:40:42.267347 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8401 12:40:42.270635 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8402 12:40:42.270719 ==
8403 12:40:42.273899 Dram Type= 6, Freq= 0, CH_1, rank 0
8404 12:40:42.277550 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8405 12:40:42.277632 ==
8406 12:40:42.280788 DQS Delay:
8407 12:40:42.280869 DQS0 = 0, DQS1 = 0
8408 12:40:42.283760 DQM Delay:
8409 12:40:42.283872 DQM0 = 135, DQM1 = 131
8410 12:40:42.283966 DQ Delay:
8411 12:40:42.290548 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8412 12:40:42.293765 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =131
8413 12:40:42.296992 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8414 12:40:42.300847 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8415 12:40:42.300929
8416 12:40:42.300993
8417 12:40:42.301053 ==
8418 12:40:42.303622 Dram Type= 6, Freq= 0, CH_1, rank 0
8419 12:40:42.307026 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8420 12:40:42.307101 ==
8421 12:40:42.307163
8422 12:40:42.307223
8423 12:40:42.310693 TX Vref Scan disable
8424 12:40:42.313326 == TX Byte 0 ==
8425 12:40:42.316911 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8426 12:40:42.319964 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8427 12:40:42.323422 == TX Byte 1 ==
8428 12:40:42.326602 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8429 12:40:42.329903 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8430 12:40:42.329974 ==
8431 12:40:42.333053 Dram Type= 6, Freq= 0, CH_1, rank 0
8432 12:40:42.339594 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8433 12:40:42.339665 ==
8434 12:40:42.351815
8435 12:40:42.354330 TX Vref early break, caculate TX vref
8436 12:40:42.357751 TX Vref=16, minBit 8, minWin=21, winSum=371
8437 12:40:42.361257 TX Vref=18, minBit 9, minWin=22, winSum=376
8438 12:40:42.364388 TX Vref=20, minBit 1, minWin=23, winSum=384
8439 12:40:42.367823 TX Vref=22, minBit 9, minWin=23, winSum=395
8440 12:40:42.370639 TX Vref=24, minBit 8, minWin=24, winSum=407
8441 12:40:42.377394 TX Vref=26, minBit 8, minWin=24, winSum=417
8442 12:40:42.381077 TX Vref=28, minBit 0, minWin=25, winSum=420
8443 12:40:42.383888 TX Vref=30, minBit 9, minWin=25, winSum=417
8444 12:40:42.387803 TX Vref=32, minBit 0, minWin=24, winSum=407
8445 12:40:42.391045 TX Vref=34, minBit 11, minWin=23, winSum=398
8446 12:40:42.397158 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 28
8447 12:40:42.397238
8448 12:40:42.400568 Final TX Range 0 Vref 28
8449 12:40:42.400639
8450 12:40:42.400699 ==
8451 12:40:42.403902 Dram Type= 6, Freq= 0, CH_1, rank 0
8452 12:40:42.407183 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8453 12:40:42.407261 ==
8454 12:40:42.407325
8455 12:40:42.407382
8456 12:40:42.410644 TX Vref Scan disable
8457 12:40:42.417176 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8458 12:40:42.417252 == TX Byte 0 ==
8459 12:40:42.420668 u2DelayCellOfst[0]=14 cells (4 PI)
8460 12:40:42.423854 u2DelayCellOfst[1]=10 cells (3 PI)
8461 12:40:42.426768 u2DelayCellOfst[2]=0 cells (0 PI)
8462 12:40:42.429977 u2DelayCellOfst[3]=7 cells (2 PI)
8463 12:40:42.433653 u2DelayCellOfst[4]=10 cells (3 PI)
8464 12:40:42.436764 u2DelayCellOfst[5]=17 cells (5 PI)
8465 12:40:42.440334 u2DelayCellOfst[6]=14 cells (4 PI)
8466 12:40:42.443034 u2DelayCellOfst[7]=7 cells (2 PI)
8467 12:40:42.446886 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8468 12:40:42.450036 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8469 12:40:42.453341 == TX Byte 1 ==
8470 12:40:42.456775 u2DelayCellOfst[8]=0 cells (0 PI)
8471 12:40:42.459903 u2DelayCellOfst[9]=3 cells (1 PI)
8472 12:40:42.463135 u2DelayCellOfst[10]=14 cells (4 PI)
8473 12:40:42.466328 u2DelayCellOfst[11]=3 cells (1 PI)
8474 12:40:42.466411 u2DelayCellOfst[12]=14 cells (4 PI)
8475 12:40:42.469607 u2DelayCellOfst[13]=14 cells (4 PI)
8476 12:40:42.473410 u2DelayCellOfst[14]=17 cells (5 PI)
8477 12:40:42.476693 u2DelayCellOfst[15]=17 cells (5 PI)
8478 12:40:42.483047 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8479 12:40:42.486458 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8480 12:40:42.486546 DramC Write-DBI on
8481 12:40:42.489833 ==
8482 12:40:42.493450 Dram Type= 6, Freq= 0, CH_1, rank 0
8483 12:40:42.495774 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8484 12:40:42.495888 ==
8485 12:40:42.495985
8486 12:40:42.496100
8487 12:40:42.499425 TX Vref Scan disable
8488 12:40:42.499496 == TX Byte 0 ==
8489 12:40:42.506102 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8490 12:40:42.506183 == TX Byte 1 ==
8491 12:40:42.509474 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8492 12:40:42.512392 DramC Write-DBI off
8493 12:40:42.512474
8494 12:40:42.512539 [DATLAT]
8495 12:40:42.515687 Freq=1600, CH1 RK0
8496 12:40:42.515770
8497 12:40:42.515836 DATLAT Default: 0xf
8498 12:40:42.519010 0, 0xFFFF, sum = 0
8499 12:40:42.519093 1, 0xFFFF, sum = 0
8500 12:40:42.522303 2, 0xFFFF, sum = 0
8501 12:40:42.525454 3, 0xFFFF, sum = 0
8502 12:40:42.525538 4, 0xFFFF, sum = 0
8503 12:40:42.528808 5, 0xFFFF, sum = 0
8504 12:40:42.528893 6, 0xFFFF, sum = 0
8505 12:40:42.532565 7, 0xFFFF, sum = 0
8506 12:40:42.532649 8, 0xFFFF, sum = 0
8507 12:40:42.535725 9, 0xFFFF, sum = 0
8508 12:40:42.535808 10, 0xFFFF, sum = 0
8509 12:40:42.538814 11, 0xFFFF, sum = 0
8510 12:40:42.538898 12, 0xFFFF, sum = 0
8511 12:40:42.542163 13, 0xFFFF, sum = 0
8512 12:40:42.542247 14, 0x0, sum = 1
8513 12:40:42.545511 15, 0x0, sum = 2
8514 12:40:42.545594 16, 0x0, sum = 3
8515 12:40:42.548841 17, 0x0, sum = 4
8516 12:40:42.548924 best_step = 15
8517 12:40:42.548989
8518 12:40:42.549050 ==
8519 12:40:42.552057 Dram Type= 6, Freq= 0, CH_1, rank 0
8520 12:40:42.555327 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8521 12:40:42.558863 ==
8522 12:40:42.558945 RX Vref Scan: 1
8523 12:40:42.559010
8524 12:40:42.562008 Set Vref Range= 24 -> 127
8525 12:40:42.562090
8526 12:40:42.565104 RX Vref 24 -> 127, step: 1
8527 12:40:42.565186
8528 12:40:42.565251 RX Delay 19 -> 252, step: 4
8529 12:40:42.565312
8530 12:40:42.568462 Set Vref, RX VrefLevel [Byte0]: 24
8531 12:40:42.571722 [Byte1]: 24
8532 12:40:42.575725
8533 12:40:42.575806 Set Vref, RX VrefLevel [Byte0]: 25
8534 12:40:42.579033 [Byte1]: 25
8535 12:40:42.583623
8536 12:40:42.583716 Set Vref, RX VrefLevel [Byte0]: 26
8537 12:40:42.586743 [Byte1]: 26
8538 12:40:42.591173
8539 12:40:42.591256 Set Vref, RX VrefLevel [Byte0]: 27
8540 12:40:42.594215 [Byte1]: 27
8541 12:40:42.598360
8542 12:40:42.601588 Set Vref, RX VrefLevel [Byte0]: 28
8543 12:40:42.604722 [Byte1]: 28
8544 12:40:42.604805
8545 12:40:42.608389 Set Vref, RX VrefLevel [Byte0]: 29
8546 12:40:42.611793 [Byte1]: 29
8547 12:40:42.611901
8548 12:40:42.614802 Set Vref, RX VrefLevel [Byte0]: 30
8549 12:40:42.618111 [Byte1]: 30
8550 12:40:42.618193
8551 12:40:42.621453 Set Vref, RX VrefLevel [Byte0]: 31
8552 12:40:42.624772 [Byte1]: 31
8553 12:40:42.628734
8554 12:40:42.628817 Set Vref, RX VrefLevel [Byte0]: 32
8555 12:40:42.632151 [Byte1]: 32
8556 12:40:42.636510
8557 12:40:42.636593 Set Vref, RX VrefLevel [Byte0]: 33
8558 12:40:42.639915 [Byte1]: 33
8559 12:40:42.643993
8560 12:40:42.644091 Set Vref, RX VrefLevel [Byte0]: 34
8561 12:40:42.647317 [Byte1]: 34
8562 12:40:42.651468
8563 12:40:42.651549 Set Vref, RX VrefLevel [Byte0]: 35
8564 12:40:42.654794 [Byte1]: 35
8565 12:40:42.659365
8566 12:40:42.659447 Set Vref, RX VrefLevel [Byte0]: 36
8567 12:40:42.662443 [Byte1]: 36
8568 12:40:42.666640
8569 12:40:42.666721 Set Vref, RX VrefLevel [Byte0]: 37
8570 12:40:42.670302 [Byte1]: 37
8571 12:40:42.674504
8572 12:40:42.674585 Set Vref, RX VrefLevel [Byte0]: 38
8573 12:40:42.677386 [Byte1]: 38
8574 12:40:42.681669
8575 12:40:42.681754 Set Vref, RX VrefLevel [Byte0]: 39
8576 12:40:42.685248 [Byte1]: 39
8577 12:40:42.689243
8578 12:40:42.689326 Set Vref, RX VrefLevel [Byte0]: 40
8579 12:40:42.692421 [Byte1]: 40
8580 12:40:42.696869
8581 12:40:42.696951 Set Vref, RX VrefLevel [Byte0]: 41
8582 12:40:42.700240 [Byte1]: 41
8583 12:40:42.704761
8584 12:40:42.704869 Set Vref, RX VrefLevel [Byte0]: 42
8585 12:40:42.707707 [Byte1]: 42
8586 12:40:42.712419
8587 12:40:42.712501 Set Vref, RX VrefLevel [Byte0]: 43
8588 12:40:42.715563 [Byte1]: 43
8589 12:40:42.719557
8590 12:40:42.719639 Set Vref, RX VrefLevel [Byte0]: 44
8591 12:40:42.722927 [Byte1]: 44
8592 12:40:42.727206
8593 12:40:42.727287 Set Vref, RX VrefLevel [Byte0]: 45
8594 12:40:42.730373 [Byte1]: 45
8595 12:40:42.734895
8596 12:40:42.734977 Set Vref, RX VrefLevel [Byte0]: 46
8597 12:40:42.738309 [Byte1]: 46
8598 12:40:42.742200
8599 12:40:42.742282 Set Vref, RX VrefLevel [Byte0]: 47
8600 12:40:42.745727 [Byte1]: 47
8601 12:40:42.750058
8602 12:40:42.750140 Set Vref, RX VrefLevel [Byte0]: 48
8603 12:40:42.753230 [Byte1]: 48
8604 12:40:42.757561
8605 12:40:42.757642 Set Vref, RX VrefLevel [Byte0]: 49
8606 12:40:42.760890 [Byte1]: 49
8607 12:40:42.765310
8608 12:40:42.765392 Set Vref, RX VrefLevel [Byte0]: 50
8609 12:40:42.768504 [Byte1]: 50
8610 12:40:42.772895
8611 12:40:42.772977 Set Vref, RX VrefLevel [Byte0]: 51
8612 12:40:42.776238 [Byte1]: 51
8613 12:40:42.780525
8614 12:40:42.780607 Set Vref, RX VrefLevel [Byte0]: 52
8615 12:40:42.783705 [Byte1]: 52
8616 12:40:42.787975
8617 12:40:42.788110 Set Vref, RX VrefLevel [Byte0]: 53
8618 12:40:42.790919 [Byte1]: 53
8619 12:40:42.795516
8620 12:40:42.795599 Set Vref, RX VrefLevel [Byte0]: 54
8621 12:40:42.798762 [Byte1]: 54
8622 12:40:42.803029
8623 12:40:42.803111 Set Vref, RX VrefLevel [Byte0]: 55
8624 12:40:42.806500 [Byte1]: 55
8625 12:40:42.810888
8626 12:40:42.810970 Set Vref, RX VrefLevel [Byte0]: 56
8627 12:40:42.813779 [Byte1]: 56
8628 12:40:42.817975
8629 12:40:42.818057 Set Vref, RX VrefLevel [Byte0]: 57
8630 12:40:42.821427 [Byte1]: 57
8631 12:40:42.825504
8632 12:40:42.825586 Set Vref, RX VrefLevel [Byte0]: 58
8633 12:40:42.829322 [Byte1]: 58
8634 12:40:42.833200
8635 12:40:42.833282 Set Vref, RX VrefLevel [Byte0]: 59
8636 12:40:42.836596 [Byte1]: 59
8637 12:40:42.840637
8638 12:40:42.840719 Set Vref, RX VrefLevel [Byte0]: 60
8639 12:40:42.844278 [Byte1]: 60
8640 12:40:42.849008
8641 12:40:42.849090 Set Vref, RX VrefLevel [Byte0]: 61
8642 12:40:42.851536 [Byte1]: 61
8643 12:40:42.856112
8644 12:40:42.856194 Set Vref, RX VrefLevel [Byte0]: 62
8645 12:40:42.859140 [Byte1]: 62
8646 12:40:42.863778
8647 12:40:42.863860 Set Vref, RX VrefLevel [Byte0]: 63
8648 12:40:42.866665 [Byte1]: 63
8649 12:40:42.871044
8650 12:40:42.871126 Set Vref, RX VrefLevel [Byte0]: 64
8651 12:40:42.874364 [Byte1]: 64
8652 12:40:42.879188
8653 12:40:42.879270 Set Vref, RX VrefLevel [Byte0]: 65
8654 12:40:42.882053 [Byte1]: 65
8655 12:40:42.886618
8656 12:40:42.886701 Set Vref, RX VrefLevel [Byte0]: 66
8657 12:40:42.889497 [Byte1]: 66
8658 12:40:42.893639
8659 12:40:42.897259 Set Vref, RX VrefLevel [Byte0]: 67
8660 12:40:42.900193 [Byte1]: 67
8661 12:40:42.900276
8662 12:40:42.903924 Set Vref, RX VrefLevel [Byte0]: 68
8663 12:40:42.906913 [Byte1]: 68
8664 12:40:42.906996
8665 12:40:42.910715 Set Vref, RX VrefLevel [Byte0]: 69
8666 12:40:42.913609 [Byte1]: 69
8667 12:40:42.913722
8668 12:40:42.916623 Set Vref, RX VrefLevel [Byte0]: 70
8669 12:40:42.919939 [Byte1]: 70
8670 12:40:42.923941
8671 12:40:42.924025 Set Vref, RX VrefLevel [Byte0]: 71
8672 12:40:42.927466 [Byte1]: 71
8673 12:40:42.931895
8674 12:40:42.931978 Final RX Vref Byte 0 = 57 to rank0
8675 12:40:42.934952 Final RX Vref Byte 1 = 61 to rank0
8676 12:40:42.938456 Final RX Vref Byte 0 = 57 to rank1
8677 12:40:42.941442 Final RX Vref Byte 1 = 61 to rank1==
8678 12:40:42.945110 Dram Type= 6, Freq= 0, CH_1, rank 0
8679 12:40:42.951449 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8680 12:40:42.951533 ==
8681 12:40:42.951599 DQS Delay:
8682 12:40:42.955057 DQS0 = 0, DQS1 = 0
8683 12:40:42.955139 DQM Delay:
8684 12:40:42.955205 DQM0 = 133, DQM1 = 130
8685 12:40:42.958034 DQ Delay:
8686 12:40:42.962095 DQ0 =142, DQ1 =130, DQ2 =118, DQ3 =132
8687 12:40:42.964363 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =126
8688 12:40:42.967955 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =122
8689 12:40:42.971771 DQ12 =142, DQ13 =140, DQ14 =138, DQ15 =140
8690 12:40:42.971879
8691 12:40:42.971971
8692 12:40:42.972096
8693 12:40:42.974633 [DramC_TX_OE_Calibration] TA2
8694 12:40:42.978006 Original DQ_B0 (3 6) =30, OEN = 27
8695 12:40:42.981191 Original DQ_B1 (3 6) =30, OEN = 27
8696 12:40:42.984289 24, 0x0, End_B0=24 End_B1=24
8697 12:40:42.987641 25, 0x0, End_B0=25 End_B1=25
8698 12:40:42.987725 26, 0x0, End_B0=26 End_B1=26
8699 12:40:42.990988 27, 0x0, End_B0=27 End_B1=27
8700 12:40:42.994045 28, 0x0, End_B0=28 End_B1=28
8701 12:40:42.997985 29, 0x0, End_B0=29 End_B1=29
8702 12:40:42.998069 30, 0x0, End_B0=30 End_B1=30
8703 12:40:43.000561 31, 0x4141, End_B0=30 End_B1=30
8704 12:40:43.004545 Byte0 end_step=30 best_step=27
8705 12:40:43.007331 Byte1 end_step=30 best_step=27
8706 12:40:43.010886 Byte0 TX OE(2T, 0.5T) = (3, 3)
8707 12:40:43.014454 Byte1 TX OE(2T, 0.5T) = (3, 3)
8708 12:40:43.014536
8709 12:40:43.014602
8710 12:40:43.020674 [DQSOSCAuto] RK0, (LSB)MR18= 0xe17, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 402 ps
8711 12:40:43.023811 CH1 RK0: MR19=303, MR18=E17
8712 12:40:43.030709 CH1_RK0: MR19=0x303, MR18=0xE17, DQSOSC=398, MR23=63, INC=23, DEC=15
8713 12:40:43.030792
8714 12:40:43.033728 ----->DramcWriteLeveling(PI) begin...
8715 12:40:43.033811 ==
8716 12:40:43.037105 Dram Type= 6, Freq= 0, CH_1, rank 1
8717 12:40:43.040559 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8718 12:40:43.040646 ==
8719 12:40:43.043381 Write leveling (Byte 0): 22 => 22
8720 12:40:43.046805 Write leveling (Byte 1): 25 => 25
8721 12:40:43.050116 DramcWriteLeveling(PI) end<-----
8722 12:40:43.050225
8723 12:40:43.050323 ==
8724 12:40:43.053698 Dram Type= 6, Freq= 0, CH_1, rank 1
8725 12:40:43.056593 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8726 12:40:43.060479 ==
8727 12:40:43.060563 [Gating] SW mode calibration
8728 12:40:43.069964 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8729 12:40:43.073486 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8730 12:40:43.076730 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8731 12:40:43.083289 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8732 12:40:43.086585 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8733 12:40:43.089550 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8734 12:40:43.096332 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8735 12:40:43.099261 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8736 12:40:43.102876 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8737 12:40:43.110097 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8738 12:40:43.112794 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8739 12:40:43.116347 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8740 12:40:43.123079 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
8741 12:40:43.125818 1 5 12 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8742 12:40:43.129071 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8743 12:40:43.135895 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8744 12:40:43.139563 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8745 12:40:43.142596 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8746 12:40:43.149322 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8747 12:40:43.152693 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8748 12:40:43.155695 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8749 12:40:43.162083 1 6 12 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
8750 12:40:43.165384 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8751 12:40:43.169110 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8752 12:40:43.175347 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8753 12:40:43.179099 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8754 12:40:43.182234 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8755 12:40:43.188324 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8756 12:40:43.192088 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8757 12:40:43.195292 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8758 12:40:43.201491 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8759 12:40:43.204668 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8760 12:40:43.208204 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8761 12:40:43.214644 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8762 12:40:43.218250 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8763 12:40:43.221174 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8764 12:40:43.227761 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 12:40:43.231091 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 12:40:43.238207 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 12:40:43.241112 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 12:40:43.244387 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 12:40:43.250730 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 12:40:43.254506 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 12:40:43.257414 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8772 12:40:43.263812 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8773 12:40:43.267373 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8774 12:40:43.270465 Total UI for P1: 0, mck2ui 16
8775 12:40:43.274138 best dqsien dly found for B0: ( 1, 9, 6)
8776 12:40:43.277370 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 12:40:43.280170 Total UI for P1: 0, mck2ui 16
8778 12:40:43.283938 best dqsien dly found for B1: ( 1, 9, 10)
8779 12:40:43.287170 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8780 12:40:43.290517 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8781 12:40:43.290601
8782 12:40:43.293827 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8783 12:40:43.300335 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8784 12:40:43.300421 [Gating] SW calibration Done
8785 12:40:43.303621 ==
8786 12:40:43.306892 Dram Type= 6, Freq= 0, CH_1, rank 1
8787 12:40:43.310205 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8788 12:40:43.310291 ==
8789 12:40:43.310376 RX Vref Scan: 0
8790 12:40:43.310456
8791 12:40:43.313860 RX Vref 0 -> 0, step: 1
8792 12:40:43.313944
8793 12:40:43.316693 RX Delay 0 -> 252, step: 8
8794 12:40:43.319861 iDelay=200, Bit 0, Center 143 (88 ~ 199) 112
8795 12:40:43.323047 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8796 12:40:43.326638 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8797 12:40:43.333489 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8798 12:40:43.336275 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8799 12:40:43.339686 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8800 12:40:43.343136 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8801 12:40:43.346260 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8802 12:40:43.352965 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8803 12:40:43.356645 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8804 12:40:43.359800 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8805 12:40:43.362771 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8806 12:40:43.369269 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8807 12:40:43.372486 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8808 12:40:43.375936 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8809 12:40:43.379359 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8810 12:40:43.379445 ==
8811 12:40:43.382457 Dram Type= 6, Freq= 0, CH_1, rank 1
8812 12:40:43.389135 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8813 12:40:43.389227 ==
8814 12:40:43.389313 DQS Delay:
8815 12:40:43.389393 DQS0 = 0, DQS1 = 0
8816 12:40:43.392669 DQM Delay:
8817 12:40:43.392755 DQM0 = 136, DQM1 = 131
8818 12:40:43.396023 DQ Delay:
8819 12:40:43.398939 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =135
8820 12:40:43.402358 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =135
8821 12:40:43.405794 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8822 12:40:43.409038 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8823 12:40:43.409123
8824 12:40:43.409207
8825 12:40:43.409286 ==
8826 12:40:43.412013 Dram Type= 6, Freq= 0, CH_1, rank 1
8827 12:40:43.415932 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8828 12:40:43.418910 ==
8829 12:40:43.418994
8830 12:40:43.419079
8831 12:40:43.419159 TX Vref Scan disable
8832 12:40:43.422004 == TX Byte 0 ==
8833 12:40:43.425748 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8834 12:40:43.428770 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8835 12:40:43.432141 == TX Byte 1 ==
8836 12:40:43.435298 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8837 12:40:43.438616 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8838 12:40:43.442265 ==
8839 12:40:43.445174 Dram Type= 6, Freq= 0, CH_1, rank 1
8840 12:40:43.448647 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8841 12:40:43.448732 ==
8842 12:40:43.461777
8843 12:40:43.465417 TX Vref early break, caculate TX vref
8844 12:40:43.469268 TX Vref=16, minBit 9, minWin=22, winSum=378
8845 12:40:43.471955 TX Vref=18, minBit 9, minWin=22, winSum=384
8846 12:40:43.475093 TX Vref=20, minBit 9, minWin=21, winSum=388
8847 12:40:43.478440 TX Vref=22, minBit 9, minWin=23, winSum=399
8848 12:40:43.481834 TX Vref=24, minBit 9, minWin=23, winSum=407
8849 12:40:43.488531 TX Vref=26, minBit 9, minWin=24, winSum=414
8850 12:40:43.491461 TX Vref=28, minBit 9, minWin=25, winSum=420
8851 12:40:43.494678 TX Vref=30, minBit 0, minWin=25, winSum=417
8852 12:40:43.498175 TX Vref=32, minBit 0, minWin=25, winSum=411
8853 12:40:43.501929 TX Vref=34, minBit 0, minWin=24, winSum=403
8854 12:40:43.504645 TX Vref=36, minBit 9, minWin=23, winSum=394
8855 12:40:43.511308 [TxChooseVref] Worse bit 9, Min win 25, Win sum 420, Final Vref 28
8856 12:40:43.511394
8857 12:40:43.514910 Final TX Range 0 Vref 28
8858 12:40:43.514993
8859 12:40:43.515058 ==
8860 12:40:43.518634 Dram Type= 6, Freq= 0, CH_1, rank 1
8861 12:40:43.521552 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8862 12:40:43.521636 ==
8863 12:40:43.521702
8864 12:40:43.525281
8865 12:40:43.525363 TX Vref Scan disable
8866 12:40:43.531933 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8867 12:40:43.532087 == TX Byte 0 ==
8868 12:40:43.534698 u2DelayCellOfst[0]=17 cells (5 PI)
8869 12:40:43.537821 u2DelayCellOfst[1]=10 cells (3 PI)
8870 12:40:43.541243 u2DelayCellOfst[2]=0 cells (0 PI)
8871 12:40:43.544525 u2DelayCellOfst[3]=7 cells (2 PI)
8872 12:40:43.547675 u2DelayCellOfst[4]=7 cells (2 PI)
8873 12:40:43.551304 u2DelayCellOfst[5]=14 cells (4 PI)
8874 12:40:43.554462 u2DelayCellOfst[6]=14 cells (4 PI)
8875 12:40:43.558067 u2DelayCellOfst[7]=7 cells (2 PI)
8876 12:40:43.561196 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8877 12:40:43.564621 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8878 12:40:43.567637 == TX Byte 1 ==
8879 12:40:43.571463 u2DelayCellOfst[8]=0 cells (0 PI)
8880 12:40:43.574679 u2DelayCellOfst[9]=3 cells (1 PI)
8881 12:40:43.578084 u2DelayCellOfst[10]=10 cells (3 PI)
8882 12:40:43.580937 u2DelayCellOfst[11]=3 cells (1 PI)
8883 12:40:43.581025 u2DelayCellOfst[12]=14 cells (4 PI)
8884 12:40:43.584188 u2DelayCellOfst[13]=14 cells (4 PI)
8885 12:40:43.587575 u2DelayCellOfst[14]=17 cells (5 PI)
8886 12:40:43.591032 u2DelayCellOfst[15]=14 cells (4 PI)
8887 12:40:43.597393 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8888 12:40:43.600669 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8889 12:40:43.600778 DramC Write-DBI on
8890 12:40:43.603797 ==
8891 12:40:43.607271 Dram Type= 6, Freq= 0, CH_1, rank 1
8892 12:40:43.610947 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8893 12:40:43.611084 ==
8894 12:40:43.611206
8895 12:40:43.611319
8896 12:40:43.613855 TX Vref Scan disable
8897 12:40:43.613985 == TX Byte 0 ==
8898 12:40:43.620390 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8899 12:40:43.620567 == TX Byte 1 ==
8900 12:40:43.623872 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8901 12:40:43.627480 DramC Write-DBI off
8902 12:40:43.627677
8903 12:40:43.627850 [DATLAT]
8904 12:40:43.630497 Freq=1600, CH1 RK1
8905 12:40:43.630814
8906 12:40:43.631051 DATLAT Default: 0xf
8907 12:40:43.633772 0, 0xFFFF, sum = 0
8908 12:40:43.634177 1, 0xFFFF, sum = 0
8909 12:40:43.637456 2, 0xFFFF, sum = 0
8910 12:40:43.640466 3, 0xFFFF, sum = 0
8911 12:40:43.640881 4, 0xFFFF, sum = 0
8912 12:40:43.643914 5, 0xFFFF, sum = 0
8913 12:40:43.644409 6, 0xFFFF, sum = 0
8914 12:40:43.647098 7, 0xFFFF, sum = 0
8915 12:40:43.647459 8, 0xFFFF, sum = 0
8916 12:40:43.650522 9, 0xFFFF, sum = 0
8917 12:40:43.650885 10, 0xFFFF, sum = 0
8918 12:40:43.653565 11, 0xFFFF, sum = 0
8919 12:40:43.653973 12, 0xFFFF, sum = 0
8920 12:40:43.657019 13, 0xFFFF, sum = 0
8921 12:40:43.657513 14, 0x0, sum = 1
8922 12:40:43.659879 15, 0x0, sum = 2
8923 12:40:43.660309 16, 0x0, sum = 3
8924 12:40:43.663664 17, 0x0, sum = 4
8925 12:40:43.664071 best_step = 15
8926 12:40:43.664452
8927 12:40:43.664891 ==
8928 12:40:43.666365 Dram Type= 6, Freq= 0, CH_1, rank 1
8929 12:40:43.673303 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8930 12:40:43.673744 ==
8931 12:40:43.674058 RX Vref Scan: 0
8932 12:40:43.674345
8933 12:40:43.676377 RX Vref 0 -> 0, step: 1
8934 12:40:43.676759
8935 12:40:43.679737 RX Delay 19 -> 252, step: 4
8936 12:40:43.682666 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
8937 12:40:43.686520 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
8938 12:40:43.692871 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8939 12:40:43.696313 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
8940 12:40:43.699545 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8941 12:40:43.702801 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8942 12:40:43.705838 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8943 12:40:43.712830 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
8944 12:40:43.715891 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8945 12:40:43.719118 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8946 12:40:43.722661 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8947 12:40:43.725633 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8948 12:40:43.732199 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8949 12:40:43.735695 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8950 12:40:43.739210 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8951 12:40:43.742320 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8952 12:40:43.742711 ==
8953 12:40:43.745195 Dram Type= 6, Freq= 0, CH_1, rank 1
8954 12:40:43.751855 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8955 12:40:43.752242 ==
8956 12:40:43.752533 DQS Delay:
8957 12:40:43.755065 DQS0 = 0, DQS1 = 0
8958 12:40:43.755444 DQM Delay:
8959 12:40:43.759090 DQM0 = 133, DQM1 = 127
8960 12:40:43.759447 DQ Delay:
8961 12:40:43.762264 DQ0 =136, DQ1 =132, DQ2 =120, DQ3 =130
8962 12:40:43.765313 DQ4 =132, DQ5 =144, DQ6 =140, DQ7 =130
8963 12:40:43.768405 DQ8 =114, DQ9 =118, DQ10 =128, DQ11 =120
8964 12:40:43.771569 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
8965 12:40:43.771928
8966 12:40:43.772240
8967 12:40:43.772529
8968 12:40:43.775112 [DramC_TX_OE_Calibration] TA2
8969 12:40:43.778102 Original DQ_B0 (3 6) =30, OEN = 27
8970 12:40:43.781350 Original DQ_B1 (3 6) =30, OEN = 27
8971 12:40:43.784830 24, 0x0, End_B0=24 End_B1=24
8972 12:40:43.787996 25, 0x0, End_B0=25 End_B1=25
8973 12:40:43.788468 26, 0x0, End_B0=26 End_B1=26
8974 12:40:43.791290 27, 0x0, End_B0=27 End_B1=27
8975 12:40:43.794748 28, 0x0, End_B0=28 End_B1=28
8976 12:40:43.798287 29, 0x0, End_B0=29 End_B1=29
8977 12:40:43.801076 30, 0x0, End_B0=30 End_B1=30
8978 12:40:43.801479 31, 0x4141, End_B0=30 End_B1=30
8979 12:40:43.804708 Byte0 end_step=30 best_step=27
8980 12:40:43.807900 Byte1 end_step=30 best_step=27
8981 12:40:43.810951 Byte0 TX OE(2T, 0.5T) = (3, 3)
8982 12:40:43.814626 Byte1 TX OE(2T, 0.5T) = (3, 3)
8983 12:40:43.815018
8984 12:40:43.815329
8985 12:40:43.821219 [DQSOSCAuto] RK1, (LSB)MR18= 0x111e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
8986 12:40:43.824250 CH1 RK1: MR19=303, MR18=111E
8987 12:40:43.831152 CH1_RK1: MR19=0x303, MR18=0x111E, DQSOSC=394, MR23=63, INC=23, DEC=15
8988 12:40:43.833962 [RxdqsGatingPostProcess] freq 1600
8989 12:40:43.840672 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8990 12:40:43.844136 best DQS0 dly(2T, 0.5T) = (1, 1)
8991 12:40:43.844529 best DQS1 dly(2T, 0.5T) = (1, 1)
8992 12:40:43.847193 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8993 12:40:43.850488 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8994 12:40:43.854082 best DQS0 dly(2T, 0.5T) = (1, 1)
8995 12:40:43.857098 best DQS1 dly(2T, 0.5T) = (1, 1)
8996 12:40:43.860296 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8997 12:40:43.863758 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8998 12:40:43.867329 Pre-setting of DQS Precalculation
8999 12:40:43.873349 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9000 12:40:43.880285 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9001 12:40:43.886482 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9002 12:40:43.886934
9003 12:40:43.887335
9004 12:40:43.889972 [Calibration Summary] 3200 Mbps
9005 12:40:43.890305 CH 0, Rank 0
9006 12:40:43.893190 SW Impedance : PASS
9007 12:40:43.896856 DUTY Scan : NO K
9008 12:40:43.897254 ZQ Calibration : PASS
9009 12:40:43.900068 Jitter Meter : NO K
9010 12:40:43.903716 CBT Training : PASS
9011 12:40:43.904150 Write leveling : PASS
9012 12:40:43.906494 RX DQS gating : PASS
9013 12:40:43.909508 RX DQ/DQS(RDDQC) : PASS
9014 12:40:43.909908 TX DQ/DQS : PASS
9015 12:40:43.913239 RX DATLAT : PASS
9016 12:40:43.916290 RX DQ/DQS(Engine): PASS
9017 12:40:43.916690 TX OE : PASS
9018 12:40:43.917093 All Pass.
9019 12:40:43.919845
9020 12:40:43.920274 CH 0, Rank 1
9021 12:40:43.922688 SW Impedance : PASS
9022 12:40:43.923199 DUTY Scan : NO K
9023 12:40:43.926394 ZQ Calibration : PASS
9024 12:40:43.926795 Jitter Meter : NO K
9025 12:40:43.929466 CBT Training : PASS
9026 12:40:43.932791 Write leveling : PASS
9027 12:40:43.933191 RX DQS gating : PASS
9028 12:40:43.936443 RX DQ/DQS(RDDQC) : PASS
9029 12:40:43.939535 TX DQ/DQS : PASS
9030 12:40:43.939934 RX DATLAT : PASS
9031 12:40:43.942647 RX DQ/DQS(Engine): PASS
9032 12:40:43.945793 TX OE : PASS
9033 12:40:43.946161 All Pass.
9034 12:40:43.946533
9035 12:40:43.946886 CH 1, Rank 0
9036 12:40:43.949067 SW Impedance : PASS
9037 12:40:43.952269 DUTY Scan : NO K
9038 12:40:43.952637 ZQ Calibration : PASS
9039 12:40:43.955770 Jitter Meter : NO K
9040 12:40:43.958845 CBT Training : PASS
9041 12:40:43.959214 Write leveling : PASS
9042 12:40:43.962156 RX DQS gating : PASS
9043 12:40:43.965488 RX DQ/DQS(RDDQC) : PASS
9044 12:40:43.965879 TX DQ/DQS : PASS
9045 12:40:43.969092 RX DATLAT : PASS
9046 12:40:43.972151 RX DQ/DQS(Engine): PASS
9047 12:40:43.972508 TX OE : PASS
9048 12:40:43.975472 All Pass.
9049 12:40:43.975829
9050 12:40:43.976149 CH 1, Rank 1
9051 12:40:43.978712 SW Impedance : PASS
9052 12:40:43.979071 DUTY Scan : NO K
9053 12:40:43.982081 ZQ Calibration : PASS
9054 12:40:43.985260 Jitter Meter : NO K
9055 12:40:43.985616 CBT Training : PASS
9056 12:40:43.988922 Write leveling : PASS
9057 12:40:43.992136 RX DQS gating : PASS
9058 12:40:43.992495 RX DQ/DQS(RDDQC) : PASS
9059 12:40:43.995589 TX DQ/DQS : PASS
9060 12:40:43.999010 RX DATLAT : PASS
9061 12:40:43.999383 RX DQ/DQS(Engine): PASS
9062 12:40:44.002246 TX OE : PASS
9063 12:40:44.002606 All Pass.
9064 12:40:44.002892
9065 12:40:44.005352 DramC Write-DBI on
9066 12:40:44.009034 PER_BANK_REFRESH: Hybrid Mode
9067 12:40:44.009451 TX_TRACKING: ON
9068 12:40:44.018382 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9069 12:40:44.024823 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9070 12:40:44.031432 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9071 12:40:44.034637 [FAST_K] Save calibration result to emmc
9072 12:40:44.038283 sync common calibartion params.
9073 12:40:44.041648 sync cbt_mode0:1, 1:1
9074 12:40:44.044580 dram_init: ddr_geometry: 2
9075 12:40:44.044972 dram_init: ddr_geometry: 2
9076 12:40:44.047944 dram_init: ddr_geometry: 2
9077 12:40:44.051519 0:dram_rank_size:100000000
9078 12:40:44.054379 1:dram_rank_size:100000000
9079 12:40:44.057918 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9080 12:40:44.060955 DFS_SHUFFLE_HW_MODE: ON
9081 12:40:44.064207 dramc_set_vcore_voltage set vcore to 725000
9082 12:40:44.067585 Read voltage for 1600, 0
9083 12:40:44.067946 Vio18 = 0
9084 12:40:44.071322 Vcore = 725000
9085 12:40:44.071685 Vdram = 0
9086 12:40:44.072001 Vddq = 0
9087 12:40:44.072332 Vmddr = 0
9088 12:40:44.073987 switch to 3200 Mbps bootup
9089 12:40:44.077488 [DramcRunTimeConfig]
9090 12:40:44.077850 PHYPLL
9091 12:40:44.078139 DPM_CONTROL_AFTERK: ON
9092 12:40:44.081086 PER_BANK_REFRESH: ON
9093 12:40:44.083862 REFRESH_OVERHEAD_REDUCTION: ON
9094 12:40:44.087165 CMD_PICG_NEW_MODE: OFF
9095 12:40:44.087547 XRTWTW_NEW_MODE: ON
9096 12:40:44.091340 XRTRTR_NEW_MODE: ON
9097 12:40:44.091733 TX_TRACKING: ON
9098 12:40:44.093971 RDSEL_TRACKING: OFF
9099 12:40:44.097026 DQS Precalculation for DVFS: ON
9100 12:40:44.097416 RX_TRACKING: OFF
9101 12:40:44.097726 HW_GATING DBG: ON
9102 12:40:44.100490 ZQCS_ENABLE_LP4: ON
9103 12:40:44.103500 RX_PICG_NEW_MODE: ON
9104 12:40:44.103887 TX_PICG_NEW_MODE: ON
9105 12:40:44.106779 ENABLE_RX_DCM_DPHY: ON
9106 12:40:44.110538 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9107 12:40:44.113665 DUMMY_READ_FOR_TRACKING: OFF
9108 12:40:44.114090 !!! SPM_CONTROL_AFTERK: OFF
9109 12:40:44.116787 !!! SPM could not control APHY
9110 12:40:44.120005 IMPEDANCE_TRACKING: ON
9111 12:40:44.120426 TEMP_SENSOR: ON
9112 12:40:44.123375 HW_SAVE_FOR_SR: OFF
9113 12:40:44.127283 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9114 12:40:44.130561 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9115 12:40:44.130968 Read ODT Tracking: ON
9116 12:40:44.133322 Refresh Rate DeBounce: ON
9117 12:40:44.136861 DFS_NO_QUEUE_FLUSH: ON
9118 12:40:44.140535 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9119 12:40:44.140944 ENABLE_DFS_RUNTIME_MRW: OFF
9120 12:40:44.143218 DDR_RESERVE_NEW_MODE: ON
9121 12:40:44.146406 MR_CBT_SWITCH_FREQ: ON
9122 12:40:44.146790 =========================
9123 12:40:44.166508 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9124 12:40:44.169948 dram_init: ddr_geometry: 2
9125 12:40:44.188267 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9126 12:40:44.191578 dram_init: dram init end (result: 0)
9127 12:40:44.197724 DRAM-K: Full calibration passed in 24410 msecs
9128 12:40:44.201191 MRC: failed to locate region type 0.
9129 12:40:44.201306 DRAM rank0 size:0x100000000,
9130 12:40:44.204529 DRAM rank1 size=0x100000000
9131 12:40:44.214570 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9132 12:40:44.221832 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9133 12:40:44.227974 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9134 12:40:44.237837 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9135 12:40:44.238170 DRAM rank0 size:0x100000000,
9136 12:40:44.241164 DRAM rank1 size=0x100000000
9137 12:40:44.241493 CBMEM:
9138 12:40:44.244203 IMD: root @ 0xfffff000 254 entries.
9139 12:40:44.247617 IMD: root @ 0xffffec00 62 entries.
9140 12:40:44.250906 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9141 12:40:44.257726 WARNING: RO_VPD is uninitialized or empty.
9142 12:40:44.260721 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9143 12:40:44.268418 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9144 12:40:44.281584 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9145 12:40:44.292244 BS: romstage times (exec / console): total (unknown) / 23944 ms
9146 12:40:44.292497
9147 12:40:44.292690
9148 12:40:44.302007 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9149 12:40:44.305337 ARM64: Exception handlers installed.
9150 12:40:44.308704 ARM64: Testing exception
9151 12:40:44.311945 ARM64: Done test exception
9152 12:40:44.312048 Enumerating buses...
9153 12:40:44.315782 Show all devs... Before device enumeration.
9154 12:40:44.318680 Root Device: enabled 1
9155 12:40:44.322417 CPU_CLUSTER: 0: enabled 1
9156 12:40:44.322754 CPU: 00: enabled 1
9157 12:40:44.325660 Compare with tree...
9158 12:40:44.326006 Root Device: enabled 1
9159 12:40:44.328801 CPU_CLUSTER: 0: enabled 1
9160 12:40:44.331900 CPU: 00: enabled 1
9161 12:40:44.332297 Root Device scanning...
9162 12:40:44.335774 scan_static_bus for Root Device
9163 12:40:44.338314 CPU_CLUSTER: 0 enabled
9164 12:40:44.341971 scan_static_bus for Root Device done
9165 12:40:44.345430 scan_bus: bus Root Device finished in 8 msecs
9166 12:40:44.345883 done
9167 12:40:44.351821 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9168 12:40:44.354935 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9169 12:40:44.361519 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9170 12:40:44.368312 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9171 12:40:44.368751 Allocating resources...
9172 12:40:44.371346 Reading resources...
9173 12:40:44.374930 Root Device read_resources bus 0 link: 0
9174 12:40:44.378362 DRAM rank0 size:0x100000000,
9175 12:40:44.378772 DRAM rank1 size=0x100000000
9176 12:40:44.384445 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9177 12:40:44.384874 CPU: 00 missing read_resources
9178 12:40:44.391431 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9179 12:40:44.395268 Root Device read_resources bus 0 link: 0 done
9180 12:40:44.397733 Done reading resources.
9181 12:40:44.401167 Show resources in subtree (Root Device)...After reading.
9182 12:40:44.404381 Root Device child on link 0 CPU_CLUSTER: 0
9183 12:40:44.407514 CPU_CLUSTER: 0 child on link 0 CPU: 00
9184 12:40:44.417767 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9185 12:40:44.417913 CPU: 00
9186 12:40:44.424133 Root Device assign_resources, bus 0 link: 0
9187 12:40:44.427553 CPU_CLUSTER: 0 missing set_resources
9188 12:40:44.430659 Root Device assign_resources, bus 0 link: 0 done
9189 12:40:44.433921 Done setting resources.
9190 12:40:44.437465 Show resources in subtree (Root Device)...After assigning values.
9191 12:40:44.440851 Root Device child on link 0 CPU_CLUSTER: 0
9192 12:40:44.447132 CPU_CLUSTER: 0 child on link 0 CPU: 00
9193 12:40:44.453615 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9194 12:40:44.457323 CPU: 00
9195 12:40:44.457467 Done allocating resources.
9196 12:40:44.464000 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9197 12:40:44.464180 Enabling resources...
9198 12:40:44.467017 done.
9199 12:40:44.470395 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9200 12:40:44.473443 Initializing devices...
9201 12:40:44.473835 Root Device init
9202 12:40:44.477139 init hardware done!
9203 12:40:44.477571 0x00000018: ctrlr->caps
9204 12:40:44.480373 52.000 MHz: ctrlr->f_max
9205 12:40:44.484015 0.400 MHz: ctrlr->f_min
9206 12:40:44.486912 0x40ff8080: ctrlr->voltages
9207 12:40:44.487311 sclk: 390625
9208 12:40:44.487625 Bus Width = 1
9209 12:40:44.490240 sclk: 390625
9210 12:40:44.490633 Bus Width = 1
9211 12:40:44.493336 Early init status = 3
9212 12:40:44.497314 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9213 12:40:44.500084 in-header: 03 fc 00 00 01 00 00 00
9214 12:40:44.503251 in-data: 00
9215 12:40:44.506488 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9216 12:40:44.512059 in-header: 03 fd 00 00 00 00 00 00
9217 12:40:44.515414 in-data:
9218 12:40:44.518528 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9219 12:40:44.522683 in-header: 03 fc 00 00 01 00 00 00
9220 12:40:44.526391 in-data: 00
9221 12:40:44.529693 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9222 12:40:44.535061 in-header: 03 fd 00 00 00 00 00 00
9223 12:40:44.538350 in-data:
9224 12:40:44.541940 [SSUSB] Setting up USB HOST controller...
9225 12:40:44.544953 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9226 12:40:44.548300 [SSUSB] phy power-on done.
9227 12:40:44.551538 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9228 12:40:44.558683 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9229 12:40:44.561348 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9230 12:40:44.568434 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9231 12:40:44.575095 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9232 12:40:44.581642 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9233 12:40:44.587810 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9234 12:40:44.594832 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9235 12:40:44.597605 SPM: binary array size = 0x9dc
9236 12:40:44.601446 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9237 12:40:44.607490 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9238 12:40:44.614508 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9239 12:40:44.621278 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9240 12:40:44.624142 configure_display: Starting display init
9241 12:40:44.658966 anx7625_power_on_init: Init interface.
9242 12:40:44.661561 anx7625_disable_pd_protocol: Disabled PD feature.
9243 12:40:44.665072 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9244 12:40:44.692869 anx7625_start_dp_work: Secure OCM version=00
9245 12:40:44.695967 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9246 12:40:44.710921 sp_tx_get_edid_block: EDID Block = 1
9247 12:40:44.813988 Extracted contents:
9248 12:40:44.817025 header: 00 ff ff ff ff ff ff 00
9249 12:40:44.820505 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9250 12:40:44.823627 version: 01 04
9251 12:40:44.826769 basic params: 95 1f 11 78 0a
9252 12:40:44.830309 chroma info: 76 90 94 55 54 90 27 21 50 54
9253 12:40:44.833474 established: 00 00 00
9254 12:40:44.840087 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9255 12:40:44.846269 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9256 12:40:44.849544 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9257 12:40:44.856253 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9258 12:40:44.881305 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9259 12:40:44.881476 extensions: 00
9260 12:40:44.881564 checksum: fb
9261 12:40:44.881625
9262 12:40:44.881686 Manufacturer: IVO Model 57d Serial Number 0
9263 12:40:44.881784 Made week 0 of 2020
9264 12:40:44.881840 EDID version: 1.4
9265 12:40:44.881894 Digital display
9266 12:40:44.881948 6 bits per primary color channel
9267 12:40:44.882233 DisplayPort interface
9268 12:40:44.882301 Maximum image size: 31 cm x 17 cm
9269 12:40:44.885401 Gamma: 220%
9270 12:40:44.885487 Check DPMS levels
9271 12:40:44.892363 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9272 12:40:44.895456 First detailed timing is preferred timing
9273 12:40:44.898711 Established timings supported:
9274 12:40:44.898795 Standard timings supported:
9275 12:40:44.902259 Detailed timings
9276 12:40:44.905267 Hex of detail: 383680a07038204018303c0035ae10000019
9277 12:40:44.911752 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9278 12:40:44.915250 0780 0798 07c8 0820 hborder 0
9279 12:40:44.918753 0438 043b 0447 0458 vborder 0
9280 12:40:44.921885 -hsync -vsync
9281 12:40:44.921997 Did detailed timing
9282 12:40:44.928432 Hex of detail: 000000000000000000000000000000000000
9283 12:40:44.931843 Manufacturer-specified data, tag 0
9284 12:40:44.935138 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9285 12:40:44.947209 ASCII string: InfoVision
9286 12:40:44.947436 Hex of detail: 000000fe00523134304e574635205248200a
9287 12:40:44.947662 ASCII string: R140NWF5 RH
9288 12:40:44.947873 Checksum
9289 12:40:44.948616 Checksum: 0xfb (valid)
9290 12:40:44.951947 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9291 12:40:44.955082 DSI data_rate: 832800000 bps
9292 12:40:44.961282 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9293 12:40:44.964712 anx7625_parse_edid: pixelclock(138800).
9294 12:40:44.968066 hactive(1920), hsync(48), hfp(24), hbp(88)
9295 12:40:44.971563 vactive(1080), vsync(12), vfp(3), vbp(17)
9296 12:40:44.974485 anx7625_dsi_config: config dsi.
9297 12:40:44.980963 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9298 12:40:44.995124 anx7625_dsi_config: success to config DSI
9299 12:40:44.998800 anx7625_dp_start: MIPI phy setup OK.
9300 12:40:45.001805 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9301 12:40:45.005116 mtk_ddp_mode_set invalid vrefresh 60
9302 12:40:45.008289 main_disp_path_setup
9303 12:40:45.008397 ovl_layer_smi_id_en
9304 12:40:45.011800 ovl_layer_smi_id_en
9305 12:40:45.011939 ccorr_config
9306 12:40:45.012059 aal_config
9307 12:40:45.014932 gamma_config
9308 12:40:45.015029 postmask_config
9309 12:40:45.018103 dither_config
9310 12:40:45.021668 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9311 12:40:45.028143 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9312 12:40:45.031558 Root Device init finished in 554 msecs
9313 12:40:45.034740 CPU_CLUSTER: 0 init
9314 12:40:45.041126 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9315 12:40:45.047979 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9316 12:40:45.048097 APU_MBOX 0x190000b0 = 0x10001
9317 12:40:45.051697 APU_MBOX 0x190001b0 = 0x10001
9318 12:40:45.054451 APU_MBOX 0x190005b0 = 0x10001
9319 12:40:45.057557 APU_MBOX 0x190006b0 = 0x10001
9320 12:40:45.064556 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9321 12:40:45.074485 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9322 12:40:45.087117 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9323 12:40:45.093685 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9324 12:40:45.105035 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9325 12:40:45.114516 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9326 12:40:45.117558 CPU_CLUSTER: 0 init finished in 81 msecs
9327 12:40:45.121402 Devices initialized
9328 12:40:45.124641 Show all devs... After init.
9329 12:40:45.125057 Root Device: enabled 1
9330 12:40:45.127855 CPU_CLUSTER: 0: enabled 1
9331 12:40:45.131299 CPU: 00: enabled 1
9332 12:40:45.134249 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9333 12:40:45.137660 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9334 12:40:45.140478 ELOG: NV offset 0x57f000 size 0x1000
9335 12:40:45.147687 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9336 12:40:45.154177 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9337 12:40:45.157713 ELOG: Event(17) added with size 13 at 2023-06-14 12:40:45 UTC
9338 12:40:45.164291 out: cmd=0x121: 03 db 21 01 00 00 00 00
9339 12:40:45.167525 in-header: 03 3b 00 00 2c 00 00 00
9340 12:40:45.177349 in-data: 24 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9341 12:40:45.184278 ELOG: Event(A1) added with size 10 at 2023-06-14 12:40:45 UTC
9342 12:40:45.190413 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9343 12:40:45.197620 ELOG: Event(A0) added with size 9 at 2023-06-14 12:40:45 UTC
9344 12:40:45.200415 elog_add_boot_reason: Logged dev mode boot
9345 12:40:45.207342 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9346 12:40:45.207770 Finalize devices...
9347 12:40:45.210834 Devices finalized
9348 12:40:45.213522 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9349 12:40:45.216884 Writing coreboot table at 0xffe64000
9350 12:40:45.220360 0. 000000000010a000-0000000000113fff: RAMSTAGE
9351 12:40:45.227320 1. 0000000040000000-00000000400fffff: RAM
9352 12:40:45.230262 2. 0000000040100000-000000004032afff: RAMSTAGE
9353 12:40:45.233281 3. 000000004032b000-00000000545fffff: RAM
9354 12:40:45.236533 4. 0000000054600000-000000005465ffff: BL31
9355 12:40:45.239828 5. 0000000054660000-00000000ffe63fff: RAM
9356 12:40:45.246876 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9357 12:40:45.249770 7. 0000000100000000-000000023fffffff: RAM
9358 12:40:45.253279 Passing 5 GPIOs to payload:
9359 12:40:45.256446 NAME | PORT | POLARITY | VALUE
9360 12:40:45.262978 EC in RW | 0x000000aa | low | undefined
9361 12:40:45.265964 EC interrupt | 0x00000005 | low | undefined
9362 12:40:45.273404 TPM interrupt | 0x000000ab | high | undefined
9363 12:40:45.275809 SD card detect | 0x00000011 | high | undefined
9364 12:40:45.279570 speaker enable | 0x00000093 | high | undefined
9365 12:40:45.283001 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9366 12:40:45.286325 in-header: 03 f9 00 00 02 00 00 00
9367 12:40:45.289731 in-data: 02 00
9368 12:40:45.293049 ADC[4]: Raw value=902586 ID=7
9369 12:40:45.296274 ADC[3]: Raw value=213916 ID=1
9370 12:40:45.296688 RAM Code: 0x71
9371 12:40:45.300164 ADC[6]: Raw value=75000 ID=0
9372 12:40:45.303048 ADC[5]: Raw value=213546 ID=1
9373 12:40:45.303460 SKU Code: 0x1
9374 12:40:45.309429 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 951a
9375 12:40:45.309848 coreboot table: 964 bytes.
9376 12:40:45.312905 IMD ROOT 0. 0xfffff000 0x00001000
9377 12:40:45.316073 IMD SMALL 1. 0xffffe000 0x00001000
9378 12:40:45.319220 RO MCACHE 2. 0xffffc000 0x00001104
9379 12:40:45.322584 CONSOLE 3. 0xfff7c000 0x00080000
9380 12:40:45.326125 FMAP 4. 0xfff7b000 0x00000452
9381 12:40:45.329587 TIME STAMP 5. 0xfff7a000 0x00000910
9382 12:40:45.332420 VBOOT WORK 6. 0xfff66000 0x00014000
9383 12:40:45.335569 RAMOOPS 7. 0xffe66000 0x00100000
9384 12:40:45.339237 COREBOOT 8. 0xffe64000 0x00002000
9385 12:40:45.342222 IMD small region:
9386 12:40:45.345880 IMD ROOT 0. 0xffffec00 0x00000400
9387 12:40:45.349040 VPD 1. 0xffffeba0 0x0000004c
9388 12:40:45.352401 MMC STATUS 2. 0xffffeb80 0x00000004
9389 12:40:45.358706 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9390 12:40:45.359133 Probing TPM: done!
9391 12:40:45.366320 Connected to device vid:did:rid of 1ae0:0028:00
9392 12:40:45.372682 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9393 12:40:45.376172 Initialized TPM device CR50 revision 0
9394 12:40:45.378989 Checking cr50 for pending updates
9395 12:40:45.384653 Reading cr50 TPM mode
9396 12:40:45.393438 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9397 12:40:45.399786 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9398 12:40:45.439959 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9399 12:40:45.443012 Checking segment from ROM address 0x40100000
9400 12:40:45.446886 Checking segment from ROM address 0x4010001c
9401 12:40:45.452981 Loading segment from ROM address 0x40100000
9402 12:40:45.453466 code (compression=0)
9403 12:40:45.462973 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9404 12:40:45.469969 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9405 12:40:45.470394 it's not compressed!
9406 12:40:45.476442 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9407 12:40:45.482860 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9408 12:40:45.500462 Loading segment from ROM address 0x4010001c
9409 12:40:45.500959 Entry Point 0x80000000
9410 12:40:45.503622 Loaded segments
9411 12:40:45.507090 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9412 12:40:45.513949 Jumping to boot code at 0x80000000(0xffe64000)
9413 12:40:45.520122 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9414 12:40:45.526278 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9415 12:40:45.534783 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9416 12:40:45.538292 Checking segment from ROM address 0x40100000
9417 12:40:45.541821 Checking segment from ROM address 0x4010001c
9418 12:40:45.547970 Loading segment from ROM address 0x40100000
9419 12:40:45.548438 code (compression=1)
9420 12:40:45.555135 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9421 12:40:45.564599 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9422 12:40:45.565034 using LZMA
9423 12:40:45.573641 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9424 12:40:45.580058 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9425 12:40:45.583044 Loading segment from ROM address 0x4010001c
9426 12:40:45.583492 Entry Point 0x54601000
9427 12:40:45.586739 Loaded segments
9428 12:40:45.589632 NOTICE: MT8192 bl31_setup
9429 12:40:45.596755 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9430 12:40:45.600141 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9431 12:40:45.603654 WARNING: region 0:
9432 12:40:45.606775 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9433 12:40:45.607194 WARNING: region 1:
9434 12:40:45.613608 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9435 12:40:45.616915 WARNING: region 2:
9436 12:40:45.619981 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9437 12:40:45.623256 WARNING: region 3:
9438 12:40:45.626582 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9439 12:40:45.630226 WARNING: region 4:
9440 12:40:45.636635 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9441 12:40:45.637223 WARNING: region 5:
9442 12:40:45.639734 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9443 12:40:45.643060 WARNING: region 6:
9444 12:40:45.646255 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9445 12:40:45.649779 WARNING: region 7:
9446 12:40:45.653086 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9447 12:40:45.659728 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9448 12:40:45.663132 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9449 12:40:45.666511 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9450 12:40:45.672807 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9451 12:40:45.676370 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9452 12:40:45.682884 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9453 12:40:45.686168 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9454 12:40:45.690031 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9455 12:40:45.696467 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9456 12:40:45.699680 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9457 12:40:45.702814 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9458 12:40:45.709749 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9459 12:40:45.712982 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9460 12:40:45.719599 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9461 12:40:45.722957 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9462 12:40:45.726162 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9463 12:40:45.732963 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9464 12:40:45.736685 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9465 12:40:45.739489 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9466 12:40:45.746207 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9467 12:40:45.749616 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9468 12:40:45.756366 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9469 12:40:45.759239 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9470 12:40:45.762663 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9471 12:40:45.769212 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9472 12:40:45.772798 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9473 12:40:45.779569 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9474 12:40:45.782497 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9475 12:40:45.786058 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9476 12:40:45.792780 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9477 12:40:45.795925 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9478 12:40:45.802368 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9479 12:40:45.805586 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9480 12:40:45.809042 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9481 12:40:45.812120 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9482 12:40:45.818919 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9483 12:40:45.822067 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9484 12:40:45.825751 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9485 12:40:45.828694 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9486 12:40:45.836162 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9487 12:40:45.838889 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9488 12:40:45.842119 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9489 12:40:45.845728 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9490 12:40:45.852176 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9491 12:40:45.855298 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9492 12:40:45.859018 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9493 12:40:45.862229 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9494 12:40:45.868401 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9495 12:40:45.871882 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9496 12:40:45.878638 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9497 12:40:45.882137 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9498 12:40:45.885370 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9499 12:40:45.891979 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9500 12:40:45.895200 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9501 12:40:45.901904 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9502 12:40:45.904812 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9503 12:40:45.911810 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9504 12:40:45.915164 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9505 12:40:45.921810 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9506 12:40:45.925261 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9507 12:40:45.928296 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9508 12:40:45.934835 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9509 12:40:45.938302 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9510 12:40:45.944808 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9511 12:40:45.948200 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9512 12:40:45.954775 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9513 12:40:45.957967 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9514 12:40:45.961565 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9515 12:40:45.968329 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9516 12:40:45.971253 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9517 12:40:45.978033 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9518 12:40:45.981500 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9519 12:40:45.988011 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9520 12:40:45.991179 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9521 12:40:45.998367 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9522 12:40:46.001055 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9523 12:40:46.004628 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9524 12:40:46.011112 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9525 12:40:46.014238 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9526 12:40:46.021296 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9527 12:40:46.024362 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9528 12:40:46.030917 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9529 12:40:46.034788 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9530 12:40:46.037634 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9531 12:40:46.044998 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9532 12:40:46.048109 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9533 12:40:46.054258 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9534 12:40:46.057349 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9535 12:40:46.064076 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9536 12:40:46.067765 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9537 12:40:46.073789 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9538 12:40:46.077943 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9539 12:40:46.084236 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9540 12:40:46.087092 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9541 12:40:46.090921 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9542 12:40:46.097259 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9543 12:40:46.100427 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9544 12:40:46.104145 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9545 12:40:46.110370 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9546 12:40:46.113803 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9547 12:40:46.117258 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9548 12:40:46.123993 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9549 12:40:46.127051 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9550 12:40:46.130933 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9551 12:40:46.137287 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9552 12:40:46.140262 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9553 12:40:46.147242 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9554 12:40:46.150238 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9555 12:40:46.153700 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9556 12:40:46.160533 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9557 12:40:46.163724 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9558 12:40:46.170344 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9559 12:40:46.173537 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9560 12:40:46.176793 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9561 12:40:46.183494 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9562 12:40:46.187034 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9563 12:40:46.189858 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9564 12:40:46.196840 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9565 12:40:46.200221 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9566 12:40:46.203521 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9567 12:40:46.209800 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9568 12:40:46.213621 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9569 12:40:46.216540 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9570 12:40:46.220175 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9571 12:40:46.226408 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9572 12:40:46.229939 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9573 12:40:46.236312 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9574 12:40:46.239750 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9575 12:40:46.243137 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9576 12:40:46.249929 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9577 12:40:46.252998 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9578 12:40:46.256396 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9579 12:40:46.263176 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9580 12:40:46.266899 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9581 12:40:46.272904 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9582 12:40:46.277079 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9583 12:40:46.279982 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9584 12:40:46.286720 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9585 12:40:46.289740 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9586 12:40:46.296484 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9587 12:40:46.299962 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9588 12:40:46.303024 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9589 12:40:46.309737 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9590 12:40:46.313375 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9591 12:40:46.316338 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9592 12:40:46.323014 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9593 12:40:46.326074 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9594 12:40:46.332690 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9595 12:40:46.336018 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9596 12:40:46.342597 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9597 12:40:46.346260 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9598 12:40:46.349858 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9599 12:40:46.356046 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9600 12:40:46.359324 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9601 12:40:46.363052 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9602 12:40:46.369411 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9603 12:40:46.373030 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9604 12:40:46.379082 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9605 12:40:46.382637 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9606 12:40:46.386103 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9607 12:40:46.392538 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9608 12:40:46.395812 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9609 12:40:46.402182 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9610 12:40:46.405889 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9611 12:40:46.409273 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9612 12:40:46.415444 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9613 12:40:46.418660 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9614 12:40:46.425371 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9615 12:40:46.428846 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9616 12:40:46.432200 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9617 12:40:46.438592 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9618 12:40:46.442191 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9619 12:40:46.448686 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9620 12:40:46.451789 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9621 12:40:46.455355 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9622 12:40:46.461617 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9623 12:40:46.465128 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9624 12:40:46.471411 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9625 12:40:46.475344 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9626 12:40:46.478366 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9627 12:40:46.485186 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9628 12:40:46.488515 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9629 12:40:46.494487 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9630 12:40:46.498083 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9631 12:40:46.501473 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9632 12:40:46.507599 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9633 12:40:46.511042 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9634 12:40:46.517782 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9635 12:40:46.521284 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9636 12:40:46.527684 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9637 12:40:46.531287 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9638 12:40:46.534672 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9639 12:40:46.540529 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9640 12:40:46.544175 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9641 12:40:46.550887 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9642 12:40:46.554411 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9643 12:40:46.557298 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9644 12:40:46.563542 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9645 12:40:46.567143 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9646 12:40:46.573728 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9647 12:40:46.577033 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9648 12:40:46.583392 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9649 12:40:46.586761 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9650 12:40:46.590420 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9651 12:40:46.596560 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9652 12:40:46.600170 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9653 12:40:46.607110 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9654 12:40:46.609984 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9655 12:40:46.616622 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9656 12:40:46.619493 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9657 12:40:46.623207 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9658 12:40:46.629468 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9659 12:40:46.632815 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9660 12:40:46.639631 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9661 12:40:46.642828 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9662 12:40:46.649616 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9663 12:40:46.652584 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9664 12:40:46.659163 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9665 12:40:46.662295 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9666 12:40:46.665764 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9667 12:40:46.672388 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9668 12:40:46.675462 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9669 12:40:46.682036 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9670 12:40:46.685302 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9671 12:40:46.691884 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9672 12:40:46.695406 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9673 12:40:46.698446 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9674 12:40:46.705339 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9675 12:40:46.708698 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9676 12:40:46.711659 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9677 12:40:46.718244 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9678 12:40:46.722203 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9679 12:40:46.724938 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9680 12:40:46.727938 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9681 12:40:46.734781 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9682 12:40:46.738347 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9683 12:40:46.744735 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9684 12:40:46.747826 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9685 12:40:46.751377 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9686 12:40:46.757739 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9687 12:40:46.761275 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9688 12:40:46.764186 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9689 12:40:46.771010 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9690 12:40:46.774113 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9691 12:40:46.780644 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9692 12:40:46.784333 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9693 12:40:46.788113 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9694 12:40:46.794460 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9695 12:40:46.797976 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9696 12:40:46.800717 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9697 12:40:46.807093 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9698 12:40:46.810225 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9699 12:40:46.816886 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9700 12:40:46.820285 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9701 12:40:46.823660 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9702 12:40:46.830312 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9703 12:40:46.833866 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9704 12:40:46.840167 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9705 12:40:46.843458 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9706 12:40:46.847069 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9707 12:40:46.853367 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9708 12:40:46.857106 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9709 12:40:46.859778 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9710 12:40:46.866287 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9711 12:40:46.869686 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9712 12:40:46.876646 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9713 12:40:46.879893 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9714 12:40:46.883090 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9715 12:40:46.889592 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9716 12:40:46.892575 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9717 12:40:46.896010 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9718 12:40:46.899899 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9719 12:40:46.903256 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9720 12:40:46.909473 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9721 12:40:46.912363 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9722 12:40:46.915813 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9723 12:40:46.919611 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9724 12:40:46.925819 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9725 12:40:46.928805 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9726 12:40:46.932444 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9727 12:40:46.939513 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9728 12:40:46.942099 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9729 12:40:46.945489 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9730 12:40:46.951996 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9731 12:40:46.955291 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9732 12:40:46.961900 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9733 12:40:46.965206 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9734 12:40:46.972018 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9735 12:40:46.975328 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9736 12:40:46.978487 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9737 12:40:46.985180 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9738 12:40:46.988309 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9739 12:40:46.995180 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9740 12:40:46.998125 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9741 12:40:47.001594 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9742 12:40:47.007803 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9743 12:40:47.011153 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9744 12:40:47.018198 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9745 12:40:47.021268 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9746 12:40:47.027736 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9747 12:40:47.030845 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9748 12:40:47.034419 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9749 12:40:47.041330 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9750 12:40:47.043978 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9751 12:40:47.050670 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9752 12:40:47.054367 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9753 12:40:47.057873 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9754 12:40:47.064065 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9755 12:40:47.067579 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9756 12:40:47.073773 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9757 12:40:47.077401 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9758 12:40:47.084082 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9759 12:40:47.087104 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9760 12:40:47.090193 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9761 12:40:47.096875 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9762 12:40:47.099997 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9763 12:40:47.106604 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9764 12:40:47.109854 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9765 12:40:47.116109 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9766 12:40:47.119692 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9767 12:40:47.122892 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9768 12:40:47.129539 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9769 12:40:47.132707 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9770 12:40:47.139725 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9771 12:40:47.142985 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9772 12:40:47.149330 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9773 12:40:47.152481 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9774 12:40:47.155718 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9775 12:40:47.162442 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9776 12:40:47.165891 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9777 12:40:47.172434 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9778 12:40:47.175732 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9779 12:40:47.179076 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9780 12:40:47.185546 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9781 12:40:47.189222 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9782 12:40:47.195115 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9783 12:40:47.198789 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9784 12:40:47.204849 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9785 12:40:47.208460 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9786 12:40:47.211493 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9787 12:40:47.218565 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9788 12:40:47.221620 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9789 12:40:47.228348 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9790 12:40:47.231444 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9791 12:40:47.238195 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9792 12:40:47.241622 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9793 12:40:47.244685 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9794 12:40:47.251313 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9795 12:40:47.254841 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9796 12:40:47.261088 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9797 12:40:47.264611 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9798 12:40:47.270438 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9799 12:40:47.273939 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9800 12:40:47.277373 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9801 12:40:47.284268 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9802 12:40:47.287077 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9803 12:40:47.293871 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9804 12:40:47.297096 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9805 12:40:47.303390 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9806 12:40:47.306928 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9807 12:40:47.313686 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9808 12:40:47.317034 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9809 12:40:47.320088 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9810 12:40:47.326605 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9811 12:40:47.330041 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9812 12:40:47.336547 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9813 12:40:47.339815 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9814 12:40:47.347061 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9815 12:40:47.350117 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9816 12:40:47.353597 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9817 12:40:47.359919 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9818 12:40:47.363328 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9819 12:40:47.369497 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9820 12:40:47.372892 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9821 12:40:47.379758 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9822 12:40:47.382863 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9823 12:40:47.389311 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9824 12:40:47.392842 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9825 12:40:47.395901 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9826 12:40:47.402273 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9827 12:40:47.406143 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9828 12:40:47.412496 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9829 12:40:47.415535 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9830 12:40:47.422487 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9831 12:40:47.426101 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9832 12:40:47.432241 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9833 12:40:47.435242 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9834 12:40:47.442596 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9835 12:40:47.445287 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9836 12:40:47.448818 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9837 12:40:47.455578 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9838 12:40:47.458675 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9839 12:40:47.465202 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9840 12:40:47.468716 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9841 12:40:47.474787 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9842 12:40:47.478192 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9843 12:40:47.484717 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9844 12:40:47.488628 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9845 12:40:47.491358 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9846 12:40:47.498391 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9847 12:40:47.501940 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9848 12:40:47.508403 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9849 12:40:47.511256 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9850 12:40:47.514859 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9851 12:40:47.521217 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9852 12:40:47.524278 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9853 12:40:47.531120 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9854 12:40:47.534160 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9855 12:40:47.540613 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9856 12:40:47.543888 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9857 12:40:47.550929 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9858 12:40:47.553969 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9859 12:40:47.560708 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9860 12:40:47.563785 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9861 12:40:47.570580 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9862 12:40:47.573948 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9863 12:40:47.580686 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9864 12:40:47.583858 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9865 12:40:47.590548 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9866 12:40:47.593486 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9867 12:40:47.600296 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9868 12:40:47.603588 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9869 12:40:47.609881 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9870 12:40:47.613238 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9871 12:40:47.619841 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9872 12:40:47.623214 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9873 12:40:47.629300 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9874 12:40:47.632996 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9875 12:40:47.639265 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9876 12:40:47.646361 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9877 12:40:47.649521 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9878 12:40:47.656001 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9879 12:40:47.659148 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9880 12:40:47.665920 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9881 12:40:47.668913 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9882 12:40:47.669466 INFO: [APUAPC] vio 0
9883 12:40:47.676472 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9884 12:40:47.680301 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9885 12:40:47.683141 INFO: [APUAPC] D0_APC_0: 0x400510
9886 12:40:47.686386 INFO: [APUAPC] D0_APC_1: 0x0
9887 12:40:47.689533 INFO: [APUAPC] D0_APC_2: 0x1540
9888 12:40:47.692933 INFO: [APUAPC] D0_APC_3: 0x0
9889 12:40:47.696472 INFO: [APUAPC] D1_APC_0: 0xffffffff
9890 12:40:47.699553 INFO: [APUAPC] D1_APC_1: 0xffffffff
9891 12:40:47.702969 INFO: [APUAPC] D1_APC_2: 0x3fffff
9892 12:40:47.706033 INFO: [APUAPC] D1_APC_3: 0x0
9893 12:40:47.709563 INFO: [APUAPC] D2_APC_0: 0xffffffff
9894 12:40:47.712423 INFO: [APUAPC] D2_APC_1: 0xffffffff
9895 12:40:47.716288 INFO: [APUAPC] D2_APC_2: 0x3fffff
9896 12:40:47.719717 INFO: [APUAPC] D2_APC_3: 0x0
9897 12:40:47.722518 INFO: [APUAPC] D3_APC_0: 0xffffffff
9898 12:40:47.726042 INFO: [APUAPC] D3_APC_1: 0xffffffff
9899 12:40:47.729006 INFO: [APUAPC] D3_APC_2: 0x3fffff
9900 12:40:47.732756 INFO: [APUAPC] D3_APC_3: 0x0
9901 12:40:47.736476 INFO: [APUAPC] D4_APC_0: 0xffffffff
9902 12:40:47.739340 INFO: [APUAPC] D4_APC_1: 0xffffffff
9903 12:40:47.742193 INFO: [APUAPC] D4_APC_2: 0x3fffff
9904 12:40:47.745936 INFO: [APUAPC] D4_APC_3: 0x0
9905 12:40:47.749338 INFO: [APUAPC] D5_APC_0: 0xffffffff
9906 12:40:47.751975 INFO: [APUAPC] D5_APC_1: 0xffffffff
9907 12:40:47.755766 INFO: [APUAPC] D5_APC_2: 0x3fffff
9908 12:40:47.759168 INFO: [APUAPC] D5_APC_3: 0x0
9909 12:40:47.762110 INFO: [APUAPC] D6_APC_0: 0xffffffff
9910 12:40:47.765235 INFO: [APUAPC] D6_APC_1: 0xffffffff
9911 12:40:47.769125 INFO: [APUAPC] D6_APC_2: 0x3fffff
9912 12:40:47.769552 INFO: [APUAPC] D6_APC_3: 0x0
9913 12:40:47.775357 INFO: [APUAPC] D7_APC_0: 0xffffffff
9914 12:40:47.778516 INFO: [APUAPC] D7_APC_1: 0xffffffff
9915 12:40:47.781920 INFO: [APUAPC] D7_APC_2: 0x3fffff
9916 12:40:47.782344 INFO: [APUAPC] D7_APC_3: 0x0
9917 12:40:47.785319 INFO: [APUAPC] D8_APC_0: 0xffffffff
9918 12:40:47.792068 INFO: [APUAPC] D8_APC_1: 0xffffffff
9919 12:40:47.795131 INFO: [APUAPC] D8_APC_2: 0x3fffff
9920 12:40:47.795572 INFO: [APUAPC] D8_APC_3: 0x0
9921 12:40:47.798464 INFO: [APUAPC] D9_APC_0: 0xffffffff
9922 12:40:47.802443 INFO: [APUAPC] D9_APC_1: 0xffffffff
9923 12:40:47.805165 INFO: [APUAPC] D9_APC_2: 0x3fffff
9924 12:40:47.808233 INFO: [APUAPC] D9_APC_3: 0x0
9925 12:40:47.811596 INFO: [APUAPC] D10_APC_0: 0xffffffff
9926 12:40:47.815224 INFO: [APUAPC] D10_APC_1: 0xffffffff
9927 12:40:47.818271 INFO: [APUAPC] D10_APC_2: 0x3fffff
9928 12:40:47.821788 INFO: [APUAPC] D10_APC_3: 0x0
9929 12:40:47.825279 INFO: [APUAPC] D11_APC_0: 0xffffffff
9930 12:40:47.828378 INFO: [APUAPC] D11_APC_1: 0xffffffff
9931 12:40:47.834990 INFO: [APUAPC] D11_APC_2: 0x3fffff
9932 12:40:47.835536 INFO: [APUAPC] D11_APC_3: 0x0
9933 12:40:47.838063 INFO: [APUAPC] D12_APC_0: 0xffffffff
9934 12:40:47.845138 INFO: [APUAPC] D12_APC_1: 0xffffffff
9935 12:40:47.848051 INFO: [APUAPC] D12_APC_2: 0x3fffff
9936 12:40:47.848560 INFO: [APUAPC] D12_APC_3: 0x0
9937 12:40:47.855843 INFO: [APUAPC] D13_APC_0: 0xffffffff
9938 12:40:47.858417 INFO: [APUAPC] D13_APC_1: 0xffffffff
9939 12:40:47.861640 INFO: [APUAPC] D13_APC_2: 0x3fffff
9940 12:40:47.865130 INFO: [APUAPC] D13_APC_3: 0x0
9941 12:40:47.867792 INFO: [APUAPC] D14_APC_0: 0xffffffff
9942 12:40:47.871351 INFO: [APUAPC] D14_APC_1: 0xffffffff
9943 12:40:47.874412 INFO: [APUAPC] D14_APC_2: 0x3fffff
9944 12:40:47.877882 INFO: [APUAPC] D14_APC_3: 0x0
9945 12:40:47.880762 INFO: [APUAPC] D15_APC_0: 0xffffffff
9946 12:40:47.884358 INFO: [APUAPC] D15_APC_1: 0xffffffff
9947 12:40:47.887418 INFO: [APUAPC] D15_APC_2: 0x3fffff
9948 12:40:47.890988 INFO: [APUAPC] D15_APC_3: 0x0
9949 12:40:47.891410 INFO: [APUAPC] APC_CON: 0x4
9950 12:40:47.894293 INFO: [NOCDAPC] D0_APC_0: 0x0
9951 12:40:47.897447 INFO: [NOCDAPC] D0_APC_1: 0x0
9952 12:40:47.900840 INFO: [NOCDAPC] D1_APC_0: 0x0
9953 12:40:47.904137 INFO: [NOCDAPC] D1_APC_1: 0xfff
9954 12:40:47.907648 INFO: [NOCDAPC] D2_APC_0: 0x0
9955 12:40:47.910991 INFO: [NOCDAPC] D2_APC_1: 0xfff
9956 12:40:47.913806 INFO: [NOCDAPC] D3_APC_0: 0x0
9957 12:40:47.917322 INFO: [NOCDAPC] D3_APC_1: 0xfff
9958 12:40:47.920825 INFO: [NOCDAPC] D4_APC_0: 0x0
9959 12:40:47.923660 INFO: [NOCDAPC] D4_APC_1: 0xfff
9960 12:40:47.924121 INFO: [NOCDAPC] D5_APC_0: 0x0
9961 12:40:47.927307 INFO: [NOCDAPC] D5_APC_1: 0xfff
9962 12:40:47.930753 INFO: [NOCDAPC] D6_APC_0: 0x0
9963 12:40:47.933826 INFO: [NOCDAPC] D6_APC_1: 0xfff
9964 12:40:47.937065 INFO: [NOCDAPC] D7_APC_0: 0x0
9965 12:40:47.940553 INFO: [NOCDAPC] D7_APC_1: 0xfff
9966 12:40:47.943918 INFO: [NOCDAPC] D8_APC_0: 0x0
9967 12:40:47.947254 INFO: [NOCDAPC] D8_APC_1: 0xfff
9968 12:40:47.950519 INFO: [NOCDAPC] D9_APC_0: 0x0
9969 12:40:47.953695 INFO: [NOCDAPC] D9_APC_1: 0xfff
9970 12:40:47.956960 INFO: [NOCDAPC] D10_APC_0: 0x0
9971 12:40:47.960228 INFO: [NOCDAPC] D10_APC_1: 0xfff
9972 12:40:47.960654 INFO: [NOCDAPC] D11_APC_0: 0x0
9973 12:40:47.963535 INFO: [NOCDAPC] D11_APC_1: 0xfff
9974 12:40:47.967057 INFO: [NOCDAPC] D12_APC_0: 0x0
9975 12:40:47.970638 INFO: [NOCDAPC] D12_APC_1: 0xfff
9976 12:40:47.973644 INFO: [NOCDAPC] D13_APC_0: 0x0
9977 12:40:47.976588 INFO: [NOCDAPC] D13_APC_1: 0xfff
9978 12:40:47.980173 INFO: [NOCDAPC] D14_APC_0: 0x0
9979 12:40:47.983086 INFO: [NOCDAPC] D14_APC_1: 0xfff
9980 12:40:47.986658 INFO: [NOCDAPC] D15_APC_0: 0x0
9981 12:40:47.989771 INFO: [NOCDAPC] D15_APC_1: 0xfff
9982 12:40:47.993226 INFO: [NOCDAPC] APC_CON: 0x4
9983 12:40:47.996576 INFO: [APUAPC] set_apusys_apc done
9984 12:40:47.999664 INFO: [DEVAPC] devapc_init done
9985 12:40:48.003331 INFO: GICv3 without legacy support detected.
9986 12:40:48.005921 INFO: ARM GICv3 driver initialized in EL3
9987 12:40:48.009576 INFO: Maximum SPI INTID supported: 639
9988 12:40:48.016332 INFO: BL31: Initializing runtime services
9989 12:40:48.019669 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9990 12:40:48.023127 INFO: SPM: enable CPC mode
9991 12:40:48.029357 INFO: mcdi ready for mcusys-off-idle and system suspend
9992 12:40:48.032648 INFO: BL31: Preparing for EL3 exit to normal world
9993 12:40:48.035985 INFO: Entry point address = 0x80000000
9994 12:40:48.039525 INFO: SPSR = 0x8
9995 12:40:48.044637
9996 12:40:48.045058
9997 12:40:48.045394
9998 12:40:48.048091 Starting depthcharge on Spherion...
9999 12:40:48.048533
10000 12:40:48.048870 Wipe memory regions:
10001 12:40:48.049189
10002 12:40:48.051482 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10003 12:40:48.051991 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10004 12:40:48.052443 Setting prompt string to ['asurada:']
10005 12:40:48.052833 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10006 12:40:48.053497 [0x00000040000000, 0x00000054600000)
10007 12:40:48.173895
10008 12:40:48.174530 [0x00000054660000, 0x00000080000000)
10009 12:40:48.434013
10010 12:40:48.434508 [0x000000821a7280, 0x000000ffe64000)
10011 12:40:49.177242
10012 12:40:49.177741 [0x00000100000000, 0x00000240000000)
10013 12:40:51.063912
10014 12:40:51.067375 Initializing XHCI USB controller at 0x11200000.
10015 12:40:52.104830
10016 12:40:52.107546 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10017 12:40:52.107643
10018 12:40:52.107710
10019 12:40:52.107771
10020 12:40:52.108092 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10022 12:40:52.208403 asurada: tftpboot 192.168.201.1 10724861/tftp-deploy-sv2o19vw/kernel/image.itb 10724861/tftp-deploy-sv2o19vw/kernel/cmdline
10023 12:40:52.208555 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10024 12:40:52.208649 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10025 12:40:52.213347 tftpboot 192.168.201.1 10724861/tftp-deploy-sv2o19vw/kernel/image.ittp-deploy-sv2o19vw/kernel/cmdline
10026 12:40:52.213437
10027 12:40:52.213503 Waiting for link
10028 12:40:52.373577
10029 12:40:52.373703 R8152: Initializing
10030 12:40:52.373783
10031 12:40:52.376611 Version 6 (ocp_data = 5c30)
10032 12:40:52.376683
10033 12:40:52.380182 R8152: Done initializing
10034 12:40:52.380255
10035 12:40:52.380316 Adding net device
10036 12:40:54.345524
10037 12:40:54.345680 done.
10038 12:40:54.345754
10039 12:40:54.345817 MAC: 00:24:32:30:7c:7b
10040 12:40:54.345886
10041 12:40:54.349442 Sending DHCP discover... done.
10042 12:40:54.349524
10043 12:40:54.351906 Waiting for reply... done.
10044 12:40:54.352026
10045 12:40:54.355498 Sending DHCP request... done.
10046 12:40:54.355593
10047 12:40:54.355700 Waiting for reply... done.
10048 12:40:54.355779
10049 12:40:54.358920 My ip is 192.168.201.14
10050 12:40:54.358992
10051 12:40:54.362033 The DHCP server ip is 192.168.201.1
10052 12:40:54.362112
10053 12:40:54.365317 TFTP server IP predefined by user: 192.168.201.1
10054 12:40:54.365399
10055 12:40:54.372008 Bootfile predefined by user: 10724861/tftp-deploy-sv2o19vw/kernel/image.itb
10056 12:40:54.372124
10057 12:40:54.375697 Sending tftp read request... done.
10058 12:40:54.375775
10059 12:40:54.378567 Waiting for the transfer...
10060 12:40:54.378640
10061 12:40:54.891390 00000000 ################################################################
10062 12:40:54.891543
10063 12:40:55.401257 00080000 ################################################################
10064 12:40:55.401427
10065 12:40:55.911003 00100000 ################################################################
10066 12:40:55.911188
10067 12:40:56.422515 00180000 ################################################################
10068 12:40:56.422702
10069 12:40:56.932469 00200000 ################################################################
10070 12:40:56.932638
10071 12:40:57.442330 00280000 ################################################################
10072 12:40:57.442473
10073 12:40:57.954195 00300000 ################################################################
10074 12:40:57.954359
10075 12:40:58.466847 00380000 ################################################################
10076 12:40:58.466997
10077 12:40:58.976574 00400000 ################################################################
10078 12:40:58.976726
10079 12:40:59.485061 00480000 ################################################################
10080 12:40:59.485215
10081 12:40:59.995760 00500000 ################################################################
10082 12:40:59.995917
10083 12:41:00.505603 00580000 ################################################################
10084 12:41:00.505764
10085 12:41:01.014372 00600000 ################################################################
10086 12:41:01.014518
10087 12:41:01.540089 00680000 ################################################################
10088 12:41:01.540270
10089 12:41:02.069304 00700000 ################################################################
10090 12:41:02.069459
10091 12:41:02.587726 00780000 ################################################################
10092 12:41:02.587868
10093 12:41:03.131464 00800000 ################################################################
10094 12:41:03.131652
10095 12:41:03.656126 00880000 ################################################################
10096 12:41:03.656278
10097 12:41:04.196458 00900000 ################################################################
10098 12:41:04.196630
10099 12:41:04.720699 00980000 ################################################################
10100 12:41:04.720873
10101 12:41:05.242682 00a00000 ################################################################
10102 12:41:05.242847
10103 12:41:05.756357 00a80000 ################################################################
10104 12:41:05.756499
10105 12:41:06.276017 00b00000 ################################################################
10106 12:41:06.276201
10107 12:41:06.795376 00b80000 ################################################################
10108 12:41:06.795555
10109 12:41:07.373840 00c00000 ################################################################
10110 12:41:07.373980
10111 12:41:07.973953 00c80000 ################################################################
10112 12:41:07.974091
10113 12:41:08.559284 00d00000 ################################################################
10114 12:41:08.559421
10115 12:41:09.125891 00d80000 ################################################################
10116 12:41:09.126025
10117 12:41:09.682753 00e00000 ################################################################
10118 12:41:09.682893
10119 12:41:10.216974 00e80000 ################################################################
10120 12:41:10.217107
10121 12:41:10.763314 00f00000 ################################################################
10122 12:41:10.763474
10123 12:41:11.336470 00f80000 ################################################################
10124 12:41:11.336614
10125 12:41:11.906977 01000000 ################################################################
10126 12:41:11.907120
10127 12:41:12.490507 01080000 ################################################################
10128 12:41:12.490645
10129 12:41:13.056318 01100000 ################################################################
10130 12:41:13.056465
10131 12:41:13.607112 01180000 ################################################################
10132 12:41:13.607245
10133 12:41:14.238135 01200000 ################################################################
10134 12:41:14.238702
10135 12:41:14.901409 01280000 ################################################################
10136 12:41:14.901929
10137 12:41:15.570795 01300000 ################################################################
10138 12:41:15.571299
10139 12:41:16.231161 01380000 ################################################################
10140 12:41:16.231735
10141 12:41:16.900984 01400000 ################################################################
10142 12:41:16.901509
10143 12:41:17.575318 01480000 ################################################################
10144 12:41:17.575894
10145 12:41:18.156924 01500000 ################################################################
10146 12:41:18.157438
10147 12:41:18.758862 01580000 ################################################################
10148 12:41:18.759001
10149 12:41:19.307057 01600000 ################################################################
10150 12:41:19.307216
10151 12:41:19.873977 01680000 ################################################################
10152 12:41:19.874128
10153 12:41:20.482477 01700000 ################################################################
10154 12:41:20.482653
10155 12:41:21.056496 01780000 ################################################################
10156 12:41:21.056678
10157 12:41:21.610966 01800000 ################################################################
10158 12:41:21.611160
10159 12:41:22.157898 01880000 ################################################################
10160 12:41:22.158045
10161 12:41:22.692411 01900000 ################################################################
10162 12:41:22.692563
10163 12:41:23.229716 01980000 ################################################################
10164 12:41:23.229875
10165 12:41:23.760024 01a00000 ################################################################
10166 12:41:23.760191
10167 12:41:24.310483 01a80000 ################################################################
10168 12:41:24.310645
10169 12:41:24.886366 01b00000 ################################################################
10170 12:41:24.886532
10171 12:41:25.508578 01b80000 ################################################################
10172 12:41:25.508752
10173 12:41:26.111414 01c00000 ################################################################
10174 12:41:26.111563
10175 12:41:26.650412 01c80000 ################################################################
10176 12:41:26.650557
10177 12:41:27.195811 01d00000 ################################################################
10178 12:41:27.195981
10179 12:41:27.740913 01d80000 ################################################################
10180 12:41:27.741055
10181 12:41:28.034154 01e00000 ################################# done.
10182 12:41:28.034305
10183 12:41:28.037394 The bootfile was 31722254 bytes long.
10184 12:41:28.037505
10185 12:41:28.040830 Sending tftp read request... done.
10186 12:41:28.040913
10187 12:41:28.040976 Waiting for the transfer...
10188 12:41:28.041038
10189 12:41:28.044203 00000000 # done.
10190 12:41:28.044293
10191 12:41:28.050701 Command line loaded dynamically from TFTP file: 10724861/tftp-deploy-sv2o19vw/kernel/cmdline
10192 12:41:28.050798
10193 12:41:28.064201 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10194 12:41:28.064326
10195 12:41:28.064424 Loading FIT.
10196 12:41:28.064515
10197 12:41:28.067078 Image ramdisk-1 has 21230917 bytes.
10198 12:41:28.067200
10199 12:41:28.070824 Image fdt-1 has 46924 bytes.
10200 12:41:28.070959
10201 12:41:28.073772 Image kernel-1 has 10442380 bytes.
10202 12:41:28.074193
10203 12:41:28.083762 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10204 12:41:28.084205
10205 12:41:28.100155 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10206 12:41:28.100604
10207 12:41:28.103500 Choosing best match conf-1 for compat google,spherion-rev2.
10208 12:41:28.109323
10209 12:41:28.113938 Connected to device vid:did:rid of 1ae0:0028:00
10210 12:41:28.120662
10211 12:41:28.125017 tpm_get_response: command 0x17b, return code 0x0
10212 12:41:28.125441
10213 12:41:28.127629 ec_init: CrosEC protocol v3 supported (256, 248)
10214 12:41:28.132478
10215 12:41:28.136303 tpm_cleanup: add release locality here.
10216 12:41:28.136724
10217 12:41:28.137130 Shutting down all USB controllers.
10218 12:41:28.139550
10219 12:41:28.139966 Removing current net device
10220 12:41:28.140370
10221 12:41:28.146190 Exiting depthcharge with code 4 at timestamp: 69330870
10222 12:41:28.146717
10223 12:41:28.149277 LZMA decompressing kernel-1 to 0x821a6718
10224 12:41:28.149700
10225 12:41:28.152612 LZMA decompressing kernel-1 to 0x40000000
10226 12:41:29.463207
10227 12:41:29.463699 jumping to kernel
10228 12:41:29.465051 end: 2.2.4 bootloader-commands (duration 00:00:41) [common]
10229 12:41:29.465552 start: 2.2.5 auto-login-action (timeout 00:03:44) [common]
10230 12:41:29.465924 Setting prompt string to ['Linux version [0-9]']
10231 12:41:29.466269 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10232 12:41:29.466610 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10233 12:41:29.546270
10234 12:41:29.549153 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10235 12:41:29.552763 start: 2.2.5.1 login-action (timeout 00:03:44) [common]
10236 12:41:29.553213 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10237 12:41:29.553661 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10238 12:41:29.554043 Using line separator: #'\n'#
10239 12:41:29.554354 No login prompt set.
10240 12:41:29.554667 Parsing kernel messages
10241 12:41:29.554952 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10242 12:41:29.555466 [login-action] Waiting for messages, (timeout 00:03:44)
10243 12:41:29.572585 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j35827-arm64-gcc-10-defconfig-arm64-chromebook-fwl9s) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jun 14 12:30:40 UTC 2023
10244 12:41:29.575570 [ 0.000000] random: crng init done
10245 12:41:29.579053 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10246 12:41:29.582380 [ 0.000000] efi: UEFI not found.
10247 12:41:29.592320 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10248 12:41:29.598570 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10249 12:41:29.608755 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10250 12:41:29.618423 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10251 12:41:29.624974 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10252 12:41:29.631334 [ 0.000000] printk: bootconsole [mtk8250] enabled
10253 12:41:29.637678 [ 0.000000] NUMA: No NUMA configuration found
10254 12:41:29.644301 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10255 12:41:29.647730 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10256 12:41:29.650988 [ 0.000000] Zone ranges:
10257 12:41:29.657385 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10258 12:41:29.661234 [ 0.000000] DMA32 empty
10259 12:41:29.667681 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10260 12:41:29.670977 [ 0.000000] Movable zone start for each node
10261 12:41:29.673985 [ 0.000000] Early memory node ranges
10262 12:41:29.680488 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10263 12:41:29.687182 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10264 12:41:29.694243 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10265 12:41:29.700859 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10266 12:41:29.707267 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10267 12:41:29.713721 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10268 12:41:29.768762 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10269 12:41:29.775287 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10270 12:41:29.782224 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10271 12:41:29.785565 [ 0.000000] psci: probing for conduit method from DT.
10272 12:41:29.791869 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10273 12:41:29.795355 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10274 12:41:29.802218 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10275 12:41:29.805364 [ 0.000000] psci: SMC Calling Convention v1.2
10276 12:41:29.811820 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10277 12:41:29.814767 [ 0.000000] Detected VIPT I-cache on CPU0
10278 12:41:29.821706 [ 0.000000] CPU features: detected: GIC system register CPU interface
10279 12:41:29.828506 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10280 12:41:29.834953 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10281 12:41:29.841598 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10282 12:41:29.851246 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10283 12:41:29.858215 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10284 12:41:29.861392 [ 0.000000] alternatives: applying boot alternatives
10285 12:41:29.867702 [ 0.000000] Fallback order for Node 0: 0
10286 12:41:29.874637 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10287 12:41:29.877774 [ 0.000000] Policy zone: Normal
10288 12:41:29.891023 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10289 12:41:29.900985 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10290 12:41:29.911198 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10291 12:41:29.921181 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10292 12:41:29.927402 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10293 12:41:29.930954 <6>[ 0.000000] software IO TLB: area num 8.
10294 12:41:29.988532 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10295 12:41:30.138060 <6>[ 0.000000] Memory: 7950420K/8385536K available (17984K kernel code, 4098K rwdata, 15868K rodata, 8384K init, 615K bss, 402348K reserved, 32768K cma-reserved)
10296 12:41:30.144870 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10297 12:41:30.151134 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10298 12:41:30.154260 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10299 12:41:30.160840 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10300 12:41:30.167609 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10301 12:41:30.170698 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10302 12:41:30.180447 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10303 12:41:30.187585 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10304 12:41:30.193941 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10305 12:41:30.200515 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10306 12:41:30.203825 <6>[ 0.000000] GICv3: 608 SPIs implemented
10307 12:41:30.207195 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10308 12:41:30.213266 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10309 12:41:30.216906 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10310 12:41:30.223307 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10311 12:41:30.236653 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10312 12:41:30.249788 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10313 12:41:30.256636 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10314 12:41:30.264862 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10315 12:41:30.277851 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10316 12:41:30.284244 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10317 12:41:30.291179 <6>[ 0.009176] Console: colour dummy device 80x25
10318 12:41:30.300633 <6>[ 0.013932] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10319 12:41:30.307388 <6>[ 0.024373] pid_max: default: 32768 minimum: 301
10320 12:41:30.310451 <6>[ 0.029247] LSM: Security Framework initializing
10321 12:41:30.317167 <6>[ 0.034183] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10322 12:41:30.326854 <6>[ 0.041996] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10323 12:41:30.337036 <6>[ 0.051466] cblist_init_generic: Setting adjustable number of callback queues.
10324 12:41:30.340181 <6>[ 0.058921] cblist_init_generic: Setting shift to 3 and lim to 1.
10325 12:41:30.347136 <6>[ 0.065260] cblist_init_generic: Setting shift to 3 and lim to 1.
10326 12:41:30.353601 <6>[ 0.071706] rcu: Hierarchical SRCU implementation.
10327 12:41:30.360511 <6>[ 0.076719] rcu: Max phase no-delay instances is 1000.
10328 12:41:30.367239 <6>[ 0.083738] EFI services will not be available.
10329 12:41:30.370130 <6>[ 0.088704] smp: Bringing up secondary CPUs ...
10330 12:41:30.378303 <6>[ 0.093755] Detected VIPT I-cache on CPU1
10331 12:41:30.384620 <6>[ 0.093827] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10332 12:41:30.391370 <6>[ 0.093858] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10333 12:41:30.394770 <6>[ 0.094200] Detected VIPT I-cache on CPU2
10334 12:41:30.401047 <6>[ 0.094257] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10335 12:41:30.410879 <6>[ 0.094274] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10336 12:41:30.414215 <6>[ 0.094538] Detected VIPT I-cache on CPU3
10337 12:41:30.420687 <6>[ 0.094589] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10338 12:41:30.427229 <6>[ 0.094604] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10339 12:41:30.430855 <6>[ 0.094914] CPU features: detected: Spectre-v4
10340 12:41:30.437199 <6>[ 0.094921] CPU features: detected: Spectre-BHB
10341 12:41:30.440852 <6>[ 0.094927] Detected PIPT I-cache on CPU4
10342 12:41:30.447205 <6>[ 0.094985] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10343 12:41:30.453886 <6>[ 0.095001] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10344 12:41:30.460264 <6>[ 0.095297] Detected PIPT I-cache on CPU5
10345 12:41:30.466995 <6>[ 0.095360] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10346 12:41:30.473468 <6>[ 0.095376] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10347 12:41:30.476970 <6>[ 0.095655] Detected PIPT I-cache on CPU6
10348 12:41:30.483394 <6>[ 0.095720] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10349 12:41:30.489803 <6>[ 0.095736] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10350 12:41:30.496357 <6>[ 0.096037] Detected PIPT I-cache on CPU7
10351 12:41:30.503410 <6>[ 0.096103] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10352 12:41:30.510382 <6>[ 0.096118] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10353 12:41:30.513343 <6>[ 0.096166] smp: Brought up 1 node, 8 CPUs
10354 12:41:30.520057 <6>[ 0.237385] SMP: Total of 8 processors activated.
10355 12:41:30.523472 <6>[ 0.242306] CPU features: detected: 32-bit EL0 Support
10356 12:41:30.533641 <6>[ 0.247669] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10357 12:41:30.539812 <6>[ 0.256469] CPU features: detected: Common not Private translations
10358 12:41:30.546224 <6>[ 0.262985] CPU features: detected: CRC32 instructions
10359 12:41:30.549692 <6>[ 0.268347] CPU features: detected: RCpc load-acquire (LDAPR)
10360 12:41:30.556057 <6>[ 0.274307] CPU features: detected: LSE atomic instructions
10361 12:41:30.562980 <6>[ 0.280123] CPU features: detected: Privileged Access Never
10362 12:41:30.568990 <6>[ 0.285903] CPU features: detected: RAS Extension Support
10363 12:41:30.575830 <6>[ 0.291512] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10364 12:41:30.579245 <6>[ 0.298732] CPU: All CPU(s) started at EL2
10365 12:41:30.585696 <6>[ 0.303075] alternatives: applying system-wide alternatives
10366 12:41:30.595456 <6>[ 0.313780] devtmpfs: initialized
10367 12:41:30.607905 <6>[ 0.322620] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10368 12:41:30.617668 <6>[ 0.332586] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10369 12:41:30.623863 <6>[ 0.340714] pinctrl core: initialized pinctrl subsystem
10370 12:41:30.627153 <6>[ 0.347380] DMI not present or invalid.
10371 12:41:30.633932 <6>[ 0.351787] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10372 12:41:30.644186 <6>[ 0.358589] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10373 12:41:30.650584 <6>[ 0.366169] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10374 12:41:30.660545 <6>[ 0.374389] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10375 12:41:30.663509 <6>[ 0.382633] audit: initializing netlink subsys (disabled)
10376 12:41:30.673853 <5>[ 0.388330] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10377 12:41:30.680633 <6>[ 0.389038] thermal_sys: Registered thermal governor 'step_wise'
10378 12:41:30.687089 <6>[ 0.396296] thermal_sys: Registered thermal governor 'power_allocator'
10379 12:41:30.690092 <6>[ 0.402552] cpuidle: using governor menu
10380 12:41:30.696618 <6>[ 0.413507] NET: Registered PF_QIPCRTR protocol family
10381 12:41:30.703602 <6>[ 0.418984] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10382 12:41:30.709884 <6>[ 0.426085] ASID allocator initialised with 32768 entries
10383 12:41:30.712977 <6>[ 0.432653] Serial: AMBA PL011 UART driver
10384 12:41:30.722932 <4>[ 0.441329] Trying to register duplicate clock ID: 134
10385 12:41:30.777275 <6>[ 0.498820] KASLR enabled
10386 12:41:30.791647 <6>[ 0.506537] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10387 12:41:30.798302 <6>[ 0.513552] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10388 12:41:30.804892 <6>[ 0.520041] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10389 12:41:30.811340 <6>[ 0.527046] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10390 12:41:30.817785 <6>[ 0.533531] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10391 12:41:30.824236 <6>[ 0.540536] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10392 12:41:30.830972 <6>[ 0.547025] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10393 12:41:30.837635 <6>[ 0.554030] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10394 12:41:30.841095 <6>[ 0.561537] ACPI: Interpreter disabled.
10395 12:41:30.849881 <6>[ 0.567909] iommu: Default domain type: Translated
10396 12:41:30.856178 <6>[ 0.573018] iommu: DMA domain TLB invalidation policy: strict mode
10397 12:41:30.859698 <5>[ 0.579671] SCSI subsystem initialized
10398 12:41:30.865871 <6>[ 0.583836] usbcore: registered new interface driver usbfs
10399 12:41:30.872926 <6>[ 0.589568] usbcore: registered new interface driver hub
10400 12:41:30.875738 <6>[ 0.595120] usbcore: registered new device driver usb
10401 12:41:30.882963 <6>[ 0.601200] pps_core: LinuxPPS API ver. 1 registered
10402 12:41:30.892924 <6>[ 0.606392] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10403 12:41:30.895964 <6>[ 0.615736] PTP clock support registered
10404 12:41:30.899691 <6>[ 0.619978] EDAC MC: Ver: 3.0.0
10405 12:41:30.906591 <6>[ 0.625134] FPGA manager framework
10406 12:41:30.910157 <6>[ 0.628814] Advanced Linux Sound Architecture Driver Initialized.
10407 12:41:30.913769 <6>[ 0.635585] vgaarb: loaded
10408 12:41:30.920836 <6>[ 0.638747] clocksource: Switched to clocksource arch_sys_counter
10409 12:41:30.927234 <5>[ 0.645190] VFS: Disk quotas dquot_6.6.0
10410 12:41:30.933528 <6>[ 0.649374] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10411 12:41:30.936874 <6>[ 0.656558] pnp: PnP ACPI: disabled
10412 12:41:30.945065 <6>[ 0.663313] NET: Registered PF_INET protocol family
10413 12:41:30.954824 <6>[ 0.668910] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10414 12:41:30.966355 <6>[ 0.681235] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10415 12:41:30.975955 <6>[ 0.690050] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10416 12:41:30.982450 <6>[ 0.698021] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10417 12:41:30.992280 <6>[ 0.706720] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10418 12:41:30.999349 <6>[ 0.716466] TCP: Hash tables configured (established 65536 bind 65536)
10419 12:41:31.005875 <6>[ 0.723323] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10420 12:41:31.015874 <6>[ 0.730518] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10421 12:41:31.022415 <6>[ 0.738221] NET: Registered PF_UNIX/PF_LOCAL protocol family
10422 12:41:31.025484 <6>[ 0.744368] RPC: Registered named UNIX socket transport module.
10423 12:41:31.032007 <6>[ 0.750523] RPC: Registered udp transport module.
10424 12:41:31.035626 <6>[ 0.755453] RPC: Registered tcp transport module.
10425 12:41:31.045591 <6>[ 0.760384] RPC: Registered tcp NFSv4.1 backchannel transport module.
10426 12:41:31.048456 <6>[ 0.767048] PCI: CLS 0 bytes, default 64
10427 12:41:31.051649 <6>[ 0.771358] Unpacking initramfs...
10428 12:41:31.062044 <6>[ 0.775405] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10429 12:41:31.068366 <6>[ 0.784047] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10430 12:41:31.075122 <6>[ 0.792899] kvm [1]: IPA Size Limit: 40 bits
10431 12:41:31.078467 <6>[ 0.797430] kvm [1]: GICv3: no GICV resource entry
10432 12:41:31.085020 <6>[ 0.802451] kvm [1]: disabling GICv2 emulation
10433 12:41:31.091383 <6>[ 0.807140] kvm [1]: GIC system register CPU interface enabled
10434 12:41:31.094953 <6>[ 0.813308] kvm [1]: vgic interrupt IRQ18
10435 12:41:31.101357 <6>[ 0.817688] kvm [1]: VHE mode initialized successfully
10436 12:41:31.104360 <5>[ 0.824126] Initialise system trusted keyrings
10437 12:41:31.111475 <6>[ 0.828913] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10438 12:41:31.120691 <6>[ 0.839193] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10439 12:41:31.127995 <5>[ 0.845590] NFS: Registering the id_resolver key type
10440 12:41:31.130944 <5>[ 0.850892] Key type id_resolver registered
10441 12:41:31.137873 <5>[ 0.855306] Key type id_legacy registered
10442 12:41:31.144636 <6>[ 0.859586] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10443 12:41:31.150842 <6>[ 0.866510] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10444 12:41:31.157508 <6>[ 0.874213] 9p: Installing v9fs 9p2000 file system support
10445 12:41:31.193803 <5>[ 0.912093] Key type asymmetric registered
10446 12:41:31.197253 <5>[ 0.916423] Asymmetric key parser 'x509' registered
10447 12:41:31.207212 <6>[ 0.921569] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10448 12:41:31.210207 <6>[ 0.929179] io scheduler mq-deadline registered
10449 12:41:31.213698 <6>[ 0.933941] io scheduler kyber registered
10450 12:41:31.232602 <6>[ 0.950675] EINJ: ACPI disabled.
10451 12:41:31.264635 <4>[ 0.975964] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10452 12:41:31.274413 <4>[ 0.986601] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10453 12:41:31.289216 <6>[ 1.007254] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10454 12:41:31.296563 <6>[ 1.015279] printk: console [ttyS0] disabled
10455 12:41:31.325108 <6>[ 1.039930] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10456 12:41:31.331500 <6>[ 1.049403] printk: console [ttyS0] enabled
10457 12:41:31.334522 <6>[ 1.049403] printk: console [ttyS0] enabled
10458 12:41:31.341658 <6>[ 1.058296] printk: bootconsole [mtk8250] disabled
10459 12:41:31.344504 <6>[ 1.058296] printk: bootconsole [mtk8250] disabled
10460 12:41:31.351200 <6>[ 1.069570] SuperH (H)SCI(F) driver initialized
10461 12:41:31.354669 <6>[ 1.074872] msm_serial: driver initialized
10462 12:41:31.368606 <6>[ 1.083816] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10463 12:41:31.378491 <6>[ 1.092364] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10464 12:41:31.385598 <6>[ 1.100907] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10465 12:41:31.395407 <6>[ 1.109535] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10466 12:41:31.405275 <6>[ 1.118241] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10467 12:41:31.411775 <6>[ 1.126954] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10468 12:41:31.421514 <6>[ 1.135495] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10469 12:41:31.428944 <6>[ 1.144306] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10470 12:41:31.438043 <6>[ 1.152849] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10471 12:41:31.450046 <6>[ 1.168666] loop: module loaded
10472 12:41:31.456465 <6>[ 1.174684] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10473 12:41:31.479655 <4>[ 1.198170] mtk-pmic-keys: Failed to locate of_node [id: -1]
10474 12:41:31.486705 <6>[ 1.205193] megasas: 07.719.03.00-rc1
10475 12:41:31.496469 <6>[ 1.214882] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10476 12:41:31.504013 <6>[ 1.222157] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10477 12:41:31.520649 <6>[ 1.238777] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10478 12:41:31.577256 <6>[ 1.288576] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10479 12:41:31.984786 <6>[ 1.703359] Freeing initrd memory: 20728K
10480 12:41:32.001475 <6>[ 1.719934] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10481 12:41:32.012973 <6>[ 1.731082] tun: Universal TUN/TAP device driver, 1.6
10482 12:41:32.016379 <6>[ 1.737133] thunder_xcv, ver 1.0
10483 12:41:32.019278 <6>[ 1.740635] thunder_bgx, ver 1.0
10484 12:41:32.022858 <6>[ 1.744132] nicpf, ver 1.0
10485 12:41:32.033093 <6>[ 1.748142] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10486 12:41:32.036170 <6>[ 1.755618] hns3: Copyright (c) 2017 Huawei Corporation.
10487 12:41:32.039454 <6>[ 1.761205] hclge is initializing
10488 12:41:32.046164 <6>[ 1.764793] e1000: Intel(R) PRO/1000 Network Driver
10489 12:41:32.052914 <6>[ 1.769922] e1000: Copyright (c) 1999-2006 Intel Corporation.
10490 12:41:32.056083 <6>[ 1.775937] e1000e: Intel(R) PRO/1000 Network Driver
10491 12:41:32.063251 <6>[ 1.781153] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10492 12:41:32.069566 <6>[ 1.787341] igb: Intel(R) Gigabit Ethernet Network Driver
10493 12:41:32.076150 <6>[ 1.792991] igb: Copyright (c) 2007-2014 Intel Corporation.
10494 12:41:32.082581 <6>[ 1.798828] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10495 12:41:32.089614 <6>[ 1.805345] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10496 12:41:32.092970 <6>[ 1.811804] sky2: driver version 1.30
10497 12:41:32.099096 <6>[ 1.816779] VFIO - User Level meta-driver version: 0.3
10498 12:41:32.106527 <6>[ 1.824959] usbcore: registered new interface driver usb-storage
10499 12:41:32.113697 <6>[ 1.831405] usbcore: registered new device driver onboard-usb-hub
10500 12:41:32.122141 <6>[ 1.840530] mt6397-rtc mt6359-rtc: registered as rtc0
10501 12:41:32.132040 <6>[ 1.846009] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-14T12:41:32 UTC (1686746492)
10502 12:41:32.135090 <6>[ 1.855638] i2c_dev: i2c /dev entries driver
10503 12:41:32.151874 <6>[ 1.867331] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10504 12:41:32.158943 <6>[ 1.877519] sdhci: Secure Digital Host Controller Interface driver
10505 12:41:32.165657 <6>[ 1.883957] sdhci: Copyright(c) Pierre Ossman
10506 12:41:32.172310 <6>[ 1.889360] Synopsys Designware Multimedia Card Interface Driver
10507 12:41:32.175530 <6>[ 1.896003] mmc0: CQHCI version 5.10
10508 12:41:32.182355 <6>[ 1.896503] sdhci-pltfm: SDHCI platform and OF driver helper
10509 12:41:32.189724 <6>[ 1.908182] ledtrig-cpu: registered to indicate activity on CPUs
10510 12:41:32.200331 <6>[ 1.915552] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10511 12:41:32.207200 <6>[ 1.922965] usbcore: registered new interface driver usbhid
10512 12:41:32.210080 <6>[ 1.928795] usbhid: USB HID core driver
10513 12:41:32.217124 <6>[ 1.933040] spi_master spi0: will run message pump with realtime priority
10514 12:41:32.260175 <6>[ 1.971880] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10515 12:41:32.278765 <6>[ 1.987460] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10516 12:41:32.282622 <6>[ 2.001016] mmc0: Command Queue Engine enabled
10517 12:41:32.289331 <6>[ 2.005784] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10518 12:41:32.295817 <6>[ 2.012713] cros-ec-spi spi0.0: Chrome EC device registered
10519 12:41:32.298726 <6>[ 2.013037] mmcblk0: mmc0:0001 DA4128 116 GiB
10520 12:41:32.309382 <6>[ 2.027892] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10521 12:41:32.316590 <6>[ 2.035249] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10522 12:41:32.323815 <6>[ 2.041134] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10523 12:41:32.329930 <6>[ 2.047103] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10524 12:41:32.346889 <6>[ 2.061941] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10525 12:41:32.354734 <6>[ 2.073363] NET: Registered PF_PACKET protocol family
10526 12:41:32.361439 <6>[ 2.078852] 9pnet: Installing 9P2000 support
10527 12:41:32.365122 <5>[ 2.083435] Key type dns_resolver registered
10528 12:41:32.367947 <6>[ 2.088452] registered taskstats version 1
10529 12:41:32.374612 <5>[ 2.092849] Loading compiled-in X.509 certificates
10530 12:41:32.407904 <4>[ 2.119781] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10531 12:41:32.417594 <4>[ 2.130477] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10532 12:41:32.428370 <3>[ 2.143262] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10533 12:41:32.440165 <6>[ 2.158682] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10534 12:41:32.447515 <6>[ 2.165539] xhci-mtk 11200000.usb: xHCI Host Controller
10535 12:41:32.453546 <6>[ 2.171044] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10536 12:41:32.463649 <6>[ 2.178889] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10537 12:41:32.470191 <6>[ 2.188326] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10538 12:41:32.476780 <6>[ 2.194419] xhci-mtk 11200000.usb: xHCI Host Controller
10539 12:41:32.483362 <6>[ 2.200017] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10540 12:41:32.489928 <6>[ 2.207694] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10541 12:41:32.497164 <6>[ 2.215580] hub 1-0:1.0: USB hub found
10542 12:41:32.500442 <6>[ 2.219618] hub 1-0:1.0: 1 port detected
10543 12:41:32.510161 <6>[ 2.223965] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10544 12:41:32.513413 <6>[ 2.232809] hub 2-0:1.0: USB hub found
10545 12:41:32.516862 <6>[ 2.236850] hub 2-0:1.0: 1 port detected
10546 12:41:32.525621 <6>[ 2.243991] mtk-msdc 11f70000.mmc: Got CD GPIO
10547 12:41:32.541739 <6>[ 2.257138] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10548 12:41:32.548750 <6>[ 2.265303] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10549 12:41:32.558427 <4>[ 2.273286] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10550 12:41:32.568816 <6>[ 2.283002] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10551 12:41:32.574888 <6>[ 2.291093] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10552 12:41:32.585046 <6>[ 2.299147] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10553 12:41:32.591165 <6>[ 2.307066] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10554 12:41:32.598137 <6>[ 2.314926] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10555 12:41:32.607770 <6>[ 2.322752] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10556 12:41:32.618493 <6>[ 2.333452] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10557 12:41:32.628256 <6>[ 2.341818] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10558 12:41:32.634670 <6>[ 2.350208] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10559 12:41:32.644759 <6>[ 2.358554] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10560 12:41:32.651466 <6>[ 2.366924] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10561 12:41:32.661147 <6>[ 2.375270] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10562 12:41:32.667699 <6>[ 2.383639] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10563 12:41:32.677595 <6>[ 2.391984] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10564 12:41:32.684727 <6>[ 2.400348] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10565 12:41:32.694134 <6>[ 2.408693] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10566 12:41:32.700721 <6>[ 2.417036] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10567 12:41:32.710635 <6>[ 2.425380] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10568 12:41:32.717313 <6>[ 2.433722] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10569 12:41:32.726825 <6>[ 2.442066] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10570 12:41:32.733743 <6>[ 2.450410] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10571 12:41:32.740694 <6>[ 2.459282] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10572 12:41:32.748390 <6>[ 2.466724] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10573 12:41:32.755407 <6>[ 2.473810] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10574 12:41:32.765520 <6>[ 2.480951] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10575 12:41:32.771986 <6>[ 2.488264] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10576 12:41:32.782384 <6>[ 2.495184] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10577 12:41:32.788924 <6>[ 2.504324] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10578 12:41:32.798749 <6>[ 2.513484] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10579 12:41:32.808666 <6>[ 2.522797] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10580 12:41:32.818830 <6>[ 2.532275] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10581 12:41:32.828342 <6>[ 2.541749] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10582 12:41:32.838260 <6>[ 2.550875] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10583 12:41:32.845054 <6>[ 2.560348] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10584 12:41:32.854854 <6>[ 2.569475] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10585 12:41:32.864761 <6>[ 2.578778] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10586 12:41:32.874752 <6>[ 2.588943] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10587 12:41:32.885363 <6>[ 2.600425] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10588 12:41:32.907638 <6>[ 2.623121] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10589 12:41:32.934716 <6>[ 2.653391] hub 2-1:1.0: USB hub found
10590 12:41:32.938011 <6>[ 2.657796] hub 2-1:1.0: 3 ports detected
10591 12:41:33.059812 <6>[ 2.775015] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10592 12:41:33.214248 <6>[ 2.932783] hub 1-1:1.0: USB hub found
10593 12:41:33.217192 <6>[ 2.937206] hub 1-1:1.0: 4 ports detected
10594 12:41:33.295935 <6>[ 3.011269] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10595 12:41:33.539603 <6>[ 3.255020] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10596 12:41:33.671978 <6>[ 3.390623] hub 1-1.4:1.0: USB hub found
10597 12:41:33.675571 <6>[ 3.395271] hub 1-1.4:1.0: 2 ports detected
10598 12:41:33.971621 <6>[ 3.687021] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10599 12:41:34.163673 <6>[ 3.879022] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10600 12:41:45.168442 <6>[ 14.891571] ALSA device list:
10601 12:41:45.174769 <6>[ 14.894826] No soundcards found.
10602 12:41:45.187395 <6>[ 14.907181] Freeing unused kernel memory: 8384K
10603 12:41:45.190350 <6>[ 14.912087] Run /init as init process
10604 12:41:45.216318 Starting syslogd: OK
10605 12:41:45.220780 Starting klogd: OK
10606 12:41:45.229638 Running sysctl: OK
10607 12:41:45.239924 Populating /dev using udev: <30>[ 14.958630] udevd[185]: starting version 3.2.9
10608 12:41:45.246794 <27>[ 14.966785] udevd[185]: specified user 'tss' unknown
10609 12:41:45.253684 <27>[ 14.972250] udevd[185]: specified group 'tss' unknown
10610 12:41:45.256653 <30>[ 14.978703] udevd[186]: starting eudev-3.2.9
10611 12:41:45.289225 <27>[ 15.009151] udevd[186]: specified user 'tss' unknown
10612 12:41:45.295820 <27>[ 15.014516] udevd[186]: specified group 'tss' unknown
10613 12:41:45.447331 <6>[ 15.163723] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10614 12:41:45.459970 <6>[ 15.179798] remoteproc remoteproc0: scp is available
10615 12:41:45.470688 <4>[ 15.187539] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10616 12:41:45.477611 <6>[ 15.197777] remoteproc remoteproc0: powering up scp
10617 12:41:45.489900 <4>[ 15.206619] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10618 12:41:45.496752 <3>[ 15.216653] remoteproc remoteproc0: request_firmware failed: -2
10619 12:41:45.540432 <6>[ 15.257175] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10620 12:41:45.547054 <6>[ 15.264912] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10621 12:41:45.556975 <6>[ 15.273743] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10622 12:41:45.563822 <6>[ 15.283780] usbcore: registered new interface driver r8152
10623 12:41:45.574042 <3>[ 15.284941] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10624 12:41:45.597448 <3>[ 15.314208] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10625 12:41:45.604312 <3>[ 15.322475] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10626 12:41:45.613930 <6>[ 15.329157] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10627 12:41:45.624959 <6>[ 15.344180] mc: Linux media interface: v0.10
10628 12:41:45.630947 <3>[ 15.344164] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10629 12:41:45.640746 <3>[ 15.344231] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10630 12:41:45.647701 <4>[ 15.346246] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10631 12:41:45.653865 <4>[ 15.346611] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10632 12:41:45.660785 <6>[ 15.375958] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10633 12:41:45.670561 <4>[ 15.379697] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10634 12:41:45.673964 <4>[ 15.379697] Fallback method does not support PEC.
10635 12:41:45.683896 <3>[ 15.379719] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10636 12:41:45.690296 <3>[ 15.379746] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10637 12:41:45.700828 <3>[ 15.379786] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10638 12:41:45.707087 <6>[ 15.387747] videodev: Linux video capture interface: v2.00
10639 12:41:45.713999 <3>[ 15.398048] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10640 12:41:45.720073 <3>[ 15.398179] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10641 12:41:45.730633 <3>[ 15.398189] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10642 12:41:45.737544 <3>[ 15.398196] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10643 12:41:45.747643 <3>[ 15.398258] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10644 12:41:45.754364 <3>[ 15.398265] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10645 12:41:45.760519 <3>[ 15.398271] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10646 12:41:45.770688 <3>[ 15.398279] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10647 12:41:45.777308 <3>[ 15.398285] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10648 12:41:45.786944 <3>[ 15.398314] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10649 12:41:45.793995 <6>[ 15.401679] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10650 12:41:45.803689 <4>[ 15.412349] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10651 12:41:45.807244 <6>[ 15.416870] pci_bus 0000:00: root bus resource [bus 00-ff]
10652 12:41:45.817638 <6>[ 15.419432] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10653 12:41:45.827638 <6>[ 15.419885] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10654 12:41:45.834584 <4>[ 15.425073] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10655 12:41:45.844132 <6>[ 15.430730] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10656 12:41:45.850843 <6>[ 15.449986] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10657 12:41:45.860866 <6>[ 15.454970] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10658 12:41:45.867712 <6>[ 15.455008] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10659 12:41:45.877461 <3>[ 15.469314] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10660 12:41:45.884277 <6>[ 15.471176] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10661 12:41:45.891011 <6>[ 15.480270] usbcore: registered new interface driver cdc_ether
10662 12:41:45.893783 <6>[ 15.487421] pci 0000:00:00.0: supports D1 D2
10663 12:41:45.900787 <6>[ 15.503944] usbcore: registered new interface driver r8153_ecm
10664 12:41:45.907468 <6>[ 15.511660] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10665 12:41:45.910438 <6>[ 15.513091] Bluetooth: Core ver 2.22
10666 12:41:45.920494 <6>[ 15.513578] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10667 12:41:45.926784 <6>[ 15.513694] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10668 12:41:45.933766 <6>[ 15.513724] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10669 12:41:45.940022 <6>[ 15.513744] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10670 12:41:45.950314 <6>[ 15.513762] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10671 12:41:45.953557 <6>[ 15.513875] pci 0000:01:00.0: supports D1 D2
10672 12:41:45.960227 <6>[ 15.513878] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10673 12:41:45.963048 <6>[ 15.518667] r8152 2-1.3:1.0 eth0: v1.12.13
10674 12:41:45.969741 <6>[ 15.522815] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10675 12:41:45.980150 <6>[ 15.522845] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10676 12:41:45.986408 <6>[ 15.522852] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10677 12:41:45.996362 <6>[ 15.522865] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10678 12:41:46.002897 <6>[ 15.522882] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10679 12:41:46.012977 <6>[ 15.522898] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10680 12:41:46.016455 <6>[ 15.522913] pci 0000:00:00.0: PCI bridge to [bus 01]
10681 12:41:46.026384 <6>[ 15.522921] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10682 12:41:46.032788 <6>[ 15.523074] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10683 12:41:46.036117 <6>[ 15.523942] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10684 12:41:46.042669 <6>[ 15.524372] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10685 12:41:46.048940 <6>[ 15.528491] NET: Registered PF_BLUETOOTH protocol family
10686 12:41:46.055892 <6>[ 15.535541] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10687 12:41:46.066051 <3>[ 15.541954] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10688 12:41:46.072165 <6>[ 15.543667] Bluetooth: HCI device and connection manager initialized
10689 12:41:46.078920 <5>[ 15.546030] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10690 12:41:46.091896 <6>[ 15.554069] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10691 12:41:46.095404 <6>[ 15.560703] Bluetooth: HCI socket layer initialized
10692 12:41:46.102024 <6>[ 15.561504] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10693 12:41:46.108533 <6>[ 15.567181] remoteproc remoteproc0: powering up scp
10694 12:41:46.118532 <4>[ 15.567225] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10695 12:41:46.124916 <3>[ 15.567234] remoteproc remoteproc0: request_firmware failed: -2
10696 12:41:46.132170 <3>[ 15.567237] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10697 12:41:46.138490 <6>[ 15.568273] usbcore: registered new interface driver uvcvideo
10698 12:41:46.144799 <5>[ 15.569689] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10699 12:41:46.155133 <4>[ 15.569752] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10700 12:41:46.158441 <6>[ 15.569759] cfg80211: failed to load regulatory.db
10701 12:41:46.164560 <6>[ 15.577147] Bluetooth: L2CAP socket layer initialized
10702 12:41:46.167850 <6>[ 15.577169] Bluetooth: SCO socket layer initialized
10703 12:41:46.174507 <6>[ 15.663814] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10704 12:41:46.181312 <6>[ 15.705389] usbcore: registered new interface driver btusb
10705 12:41:46.191320 <4>[ 15.706077] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10706 12:41:46.197731 <3>[ 15.706088] Bluetooth: hci0: Failed to load firmware file (-2)
10707 12:41:46.204547 <3>[ 15.706092] Bluetooth: hci0: Failed to set up firmware (-2)
10708 12:41:46.214413 <4>[ 15.706096] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10709 12:41:46.220798 <6>[ 15.712733] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10710 12:41:46.243039 <6>[ 15.963060] mt7921e 0000:01:00.0: ASIC revision: 79610010
10711 12:41:46.349429 <4>[ 16.062879] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10712 12:41:46.372250 done
10713 12:41:46.380429 Saving random seed: OK
10714 12:41:46.395457 Starting network: OK
10715 12:41:46.431952 Starting dropbear sshd: <6>[ 16.151735] NET: Registered PF_INET6 protocol family
10716 12:41:46.438701 <6>[ 16.158110] Segment Routing with IPv6
10717 12:41:46.441698 <6>[ 16.162054] In-situ OAM (IOAM) with IPv6
10718 12:41:46.448648 OK
10719 12:41:46.469236 <4>[ 16.182799] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10720 12:41:46.476292 /bin/sh: can't access tty; job control turned off
10721 12:41:46.476594 Matched prompt #10: / #
10723 12:41:46.476806 Setting prompt string to ['/ #']
10724 12:41:46.476910 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10726 12:41:46.477105 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10727 12:41:46.477190 start: 2.2.6 expect-shell-connection (timeout 00:03:27) [common]
10728 12:41:46.477298 Setting prompt string to ['/ #']
10729 12:41:46.477363 Forcing a shell prompt, looking for ['/ #']
10731 12:41:46.527549 / #
10732 12:41:46.527671 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10733 12:41:46.527780 Waiting using forced prompt support (timeout 00:02:30)
10734 12:41:46.533134
10735 12:41:46.533418 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10736 12:41:46.533509 start: 2.2.7 export-device-env (timeout 00:03:27) [common]
10737 12:41:46.533601 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10738 12:41:46.533685 end: 2.2 depthcharge-retry (duration 00:01:33) [common]
10739 12:41:46.533838 end: 2 depthcharge-action (duration 00:01:33) [common]
10740 12:41:46.533938 start: 3 lava-test-retry (timeout 00:01:00) [common]
10741 12:41:46.534024 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10742 12:41:46.534098 Using namespace: common
10744 12:41:46.634386 / # #
10745 12:41:46.634543 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10746 12:41:46.634693 <4>[ 16.301539] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10747 12:41:46.639487 #
10748 12:41:46.639739 Using /lava-10724861
10750 12:41:46.740025 / # export SHELL=/bin/sh
10751 12:41:46.740260 export SHELL=/bin/sh<4>[ 16.421595] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10752 12:41:46.745791
10754 12:41:46.846287 / # . /lava-10724861/environment
10755 12:41:46.846529 . /lava-10724861/environment<4>[ 16.541335] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10756 12:41:46.851430
10758 12:41:46.951902 / # /lava-10724861/bin/lava-test-runner /lava-10724861/0
10759 12:41:46.952059 Test shell timeout: 10s (minimum of the action and connection timeout)
10760 12:41:46.952483 /lava-10724861/bin/lava-test-runner /lava-10724861/0<4>[ 16.661395] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10761 12:41:46.957511
10762 12:41:47.004101 + export 'TESTRUN_ID=0_dmesg'
10763 12:41:47.004233 + c<8>[ 16.704658] <LAVA_SIGNAL_STARTRUN 0_dmesg 10724861_1.5.2.3.1>
10764 12:41:47.004313 d /lava-10724861/0/tests/0_dmesg
10765 12:41:47.004380 + cat uuid
10766 12:41:47.004618 Received signal: <STARTRUN> 0_dmesg 10724861_1.5.2.3.1
10767 12:41:47.004693 Starting test lava.0_dmesg (10724861_1.5.2.3.1)
10768 12:41:47.004784 Skipping test definition patterns.
10769 12:41:47.004893 + UUID=10724861_1.5.2.3.1
10770 12:41:47.004959 + set +x
10771 12:41:47.005019 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10772 12:41:47.008733 <8>[ 16.724343] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10773 12:41:47.008991 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10775 12:41:47.027973 <8>[ 16.745207] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10776 12:41:47.028296 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10778 12:41:47.049337 <8>[ 16.766088] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10779 12:41:47.049609 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10781 12:41:47.058714 + set +x
10782 12:41:47.061638 Received signal: <ENDRUN> 0_dmesg 10724861_1.5.2.3.1
10783 12:41:47.061727 Ending use of test pattern.
10784 12:41:47.061793 Ending test lava.0_dmesg (10724861_1.5.2.3.1), duration 0.06
10786 12:41:47.064957 <8>[ 16.782236] <LAVA_SIGNAL_ENDRUN 0_dmesg 10724861_1.5.2.3.1>
10787 12:41:47.074892 <4>[ 16.789416] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10788 12:41:47.078293 <LAVA_TEST_RUNNER EXIT>
10789 12:41:47.078552 ok: lava_test_shell seems to have completed
10790 12:41:47.078706 alert: pass
crit: pass
emerg: pass
10791 12:41:47.078797 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10792 12:41:47.078882 end: 3 lava-test-retry (duration 00:00:01) [common]
10793 12:41:47.078966 start: 4 lava-test-retry (timeout 00:01:00) [common]
10794 12:41:47.079048 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10795 12:41:47.079113 Using namespace: common
10797 12:41:47.179426 / # #
10798 12:41:47.179584 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10799 12:41:47.179766 Using /lava-10724861
10801 12:41:47.280070 export SHELL=/bin/sh
10802 12:41:47.280262 #
10803 12:41:47.280340 / # <4>[ 16.908895] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10805 12:41:47.380798 export SHELL=/bin/sh. /lava-10724861/environment
10806 12:41:47.381050
10807 12:41:47.381157 / # <4>[ 17.029473] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10809 12:41:47.481754 . /lava-10724861/environment/lava-10724861/bin/lava-test-runner /lava-10724861/1
10810 12:41:47.481937 Test shell timeout: 10s (minimum of the action and connection timeout)
10811 12:41:47.482066
10812 12:41:47.482136 / # <4>[ 17.149244] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10813 12:41:47.486272 /lava-10724861/bin/lava-test-runner /lava-10724861/1
10814 12:41:47.528113 + export 'TESTRUN_ID=1_bootrr'
10815 12:41:47.528339 <8>[ 17.230154] <LAVA_SIGNAL_STARTRUN 1_bootrr 10724861_1.5.2.3.5>
10816 12:41:47.528431 + cd /lava-10724861/1/tests/1_bootrr
10817 12:41:47.528496 + cat uuid
10818 12:41:47.528557 + UUID=10724861_1.5.2.3.5
10819 12:41:47.528672 + set +x
10820 12:41:47.528983 Received signal: <STARTRUN> 1_bootrr 10724861_1.5.2.3.5
10821 12:41:47.529109 Starting test lava.1_bootrr (10724861_1.5.2.3.5)
10822 12:41:47.529258 Skipping test definition patterns.
10823 12:41:47.534967 + export 'PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-10724861/1/../bin:/sbin:/usr/sbin<8>[ 17.252177] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10824 12:41:47.535284 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10826 12:41:47.538040 :/bin:/usr/bin'
10827 12:41:47.538155 + cd /opt/bootrr/libexec/bootrr
10828 12:41:47.541563 + sh helpers/bootrr-auto
10829 12:41:47.544467 /lava-10724861/1/../bin/lava-test-case
10830 12:41:47.553597 <3>[ 17.274017] mt7921e 0000:01:00.0: hardware init failed
10831 12:41:47.557019 /lava-10724861/1/../bin/lava-test-case
10832 12:41:47.563856 <8>[ 17.282728] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10833 12:41:47.564274 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10835 12:41:47.570277 /usr/bin/tpm2_getcap
10836 12:41:47.602667 /lava-10724861/1/../bin/lava-test-case
10837 12:41:47.609231 <8>[ 17.326308] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
10838 12:41:47.609528 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10840 12:41:47.626504 /lava-10724861/1/../bin/lava-test-case
10841 12:41:47.633037 <8>[ 17.349975] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10842 12:41:47.633347 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10844 12:41:47.644518 /lava-10724861/1/../bin/lava-test-case
10845 12:41:47.651408 <8>[ 17.368298] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10846 12:41:47.651764 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10848 12:41:47.662994 /lava-10724861/1/../bin/lava-test-case
10849 12:41:47.669921 <8>[ 17.386056] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10850 12:41:47.670220 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10852 12:41:47.680255 /lava-10724861/1/../bin/lava-test-case
10853 12:41:47.687264 <8>[ 17.404188] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10854 12:41:47.687547 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10856 12:41:47.699267 /lava-10724861/1/../bin/lava-test-case
10857 12:41:47.705239 <8>[ 17.422020] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10858 12:41:47.705568 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10860 12:41:47.714999 /lava-10724861/1/../bin/lava-test-case
10861 12:41:47.721367 <8>[ 17.438045] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10862 12:41:47.721705 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10864 12:41:47.733350 /lava-10724861/1/../bin/lava-test-case
10865 12:41:47.739942 <8>[ 17.456757] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10866 12:41:47.740258 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10868 12:41:47.749076 /lava-10724861/1/../bin/lava-test-case
10869 12:41:47.755451 <8>[ 17.472270] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10870 12:41:47.755734 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10872 12:41:47.768212 /lava-10724861/1/../bin/lava-test-case
10873 12:41:47.774729 <8>[ 17.492157] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10874 12:41:47.775010 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10876 12:41:47.786908 /lava-10724861/1/../bin/lava-test-case
10877 12:41:47.793287 <8>[ 17.510285] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10878 12:41:47.793582 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10880 12:41:47.805602 /lava-10724861/1/../bin/lava-test-case
10881 12:41:47.811840 <8>[ 17.528880] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10882 12:41:47.812131 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10884 12:41:47.823984 /lava-10724861/1/../bin/lava-test-case
10885 12:41:47.830724 <8>[ 17.547484] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10886 12:41:47.831002 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10888 12:41:47.841159 /lava-10724861/1/../bin/lava-test-case
10889 12:41:47.847319 <8>[ 17.564492] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
10890 12:41:47.847640 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10892 12:41:47.859442 /lava-10724861/1/../bin/lava-test-case
10893 12:41:47.866177 <8>[ 17.582634] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
10894 12:41:47.866462 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10896 12:41:47.875756 /lava-10724861/1/../bin/lava-test-case
10897 12:41:47.882387 <8>[ 17.599468] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
10898 12:41:47.882671 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10900 12:41:47.894086 /lava-10724861/1/../bin/lava-test-case
10901 12:41:47.900814 <8>[ 17.617877] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
10902 12:41:47.901066 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10904 12:41:47.910346 /lava-10724861/1/../bin/lava-test-case
10905 12:41:47.916663 <8>[ 17.633874] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
10906 12:41:47.916940 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10908 12:41:47.928722 /lava-10724861/1/../bin/lava-test-case
10909 12:41:47.934920 <8>[ 17.652436] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
10910 12:41:47.935197 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10912 12:41:47.944561 /lava-10724861/1/../bin/lava-test-case
10913 12:41:47.950645 <8>[ 17.667650] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
10914 12:41:47.950919 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10916 12:41:47.963869 /lava-10724861/1/../bin/lava-test-case
10917 12:41:47.970221 <8>[ 17.687340] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
10918 12:41:47.970479 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10920 12:41:47.980145 /lava-10724861/1/../bin/lava-test-case
10921 12:41:47.986471 <8>[ 17.703591] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
10922 12:41:47.986775 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10924 12:41:47.998985 /lava-10724861/1/../bin/lava-test-case
10925 12:41:48.005295 <8>[ 17.723114] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
10926 12:41:48.005578 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
10928 12:41:48.018087 /lava-10724861/1/../bin/lava-test-case
10929 12:41:48.024471 <8>[ 17.741162] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
10930 12:41:48.024724 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
10932 12:41:48.033727 /lava-10724861/1/../bin/lava-test-case
10933 12:41:48.040494 <8>[ 17.757236] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
10934 12:41:48.040752 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
10936 12:41:48.052257 /lava-10724861/1/../bin/lava-test-case
10937 12:41:48.058946 <8>[ 17.775838] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
10938 12:41:48.059264 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
10940 12:41:48.067930 /lava-10724861/1/../bin/lava-test-case
10941 12:41:48.074729 <8>[ 17.791887] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
10942 12:41:48.075020 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
10944 12:41:48.087096 /lava-10724861/1/../bin/lava-test-case
10945 12:41:48.093541 <8>[ 17.810298] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
10946 12:41:48.093794 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
10948 12:41:48.104797 /lava-10724861/1/../bin/lava-test-case
10949 12:41:48.111672 <8>[ 17.828244] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
10950 12:41:48.111926 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
10952 12:41:48.123771 /lava-10724861/1/../bin/lava-test-case
10953 12:41:48.130063 <8>[ 17.847234] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
10954 12:41:48.130316 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
10956 12:41:48.141561 /lava-10724861/1/../bin/lava-test-case
10957 12:41:48.148297 <8>[ 17.865183] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
10958 12:41:48.148555 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
10960 12:41:48.157940 /lava-10724861/1/../bin/lava-test-case
10961 12:41:48.164138 <8>[ 17.881812] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
10962 12:41:48.164396 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
10964 12:41:48.176715 /lava-10724861/1/../bin/lava-test-case
10965 12:41:48.183056 <8>[ 17.900202] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
10966 12:41:48.183309 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
10968 12:41:48.194599 /lava-10724861/1/../bin/lava-test-case
10969 12:41:48.201003 <8>[ 17.918230] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
10970 12:41:48.201260 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
10972 12:41:48.210428 /lava-10724861/1/../bin/lava-test-case
10973 12:41:48.216947 <8>[ 17.934037] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
10974 12:41:48.217200 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
10976 12:41:48.229156 /lava-10724861/1/../bin/lava-test-case
10977 12:41:48.235353 <8>[ 17.952533] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
10978 12:41:48.235624 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
10980 12:41:48.245205 /lava-10724861/1/../bin/lava-test-case
10981 12:41:48.251769 <8>[ 17.968771] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
10982 12:41:48.252024 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
10984 12:41:48.264055 /lava-10724861/1/../bin/lava-test-case
10985 12:41:48.270488 <8>[ 17.987492] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
10986 12:41:48.270743 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
10988 12:41:48.279907 /lava-10724861/1/../bin/lava-test-case
10989 12:41:48.286421 <8>[ 18.003090] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
10990 12:41:48.286673 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
10992 12:41:48.298460 /lava-10724861/1/../bin/lava-test-case
10993 12:41:48.304515 <8>[ 18.021969] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
10994 12:41:48.304766 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
10996 12:41:48.314125 /lava-10724861/1/../bin/lava-test-case
10997 12:41:48.320604 <8>[ 18.037477] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
10998 12:41:48.320862 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11000 12:41:48.333545 /lava-10724861/1/../bin/lava-test-case
11001 12:41:48.339816 <8>[ 18.057245] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11002 12:41:48.340081 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11004 12:41:48.349432 /lava-10724861/1/../bin/lava-test-case
11005 12:41:48.356244 <8>[ 18.073472] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11006 12:41:48.356498 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11008 12:41:48.368579 /lava-10724861/1/../bin/lava-test-case
11009 12:41:48.375058 <8>[ 18.092241] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11010 12:41:48.375312 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11012 12:41:48.384617 /lava-10724861/1/../bin/lava-test-case
11013 12:41:48.390939 <8>[ 18.107724] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11014 12:41:48.391192 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11016 12:41:48.402712 /lava-10724861/1/../bin/lava-test-case
11017 12:41:48.409189 <8>[ 18.125711] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11018 12:41:48.409444 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11020 12:41:48.417897 /lava-10724861/1/../bin/lava-test-case
11021 12:41:48.424576 <8>[ 18.141611] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11022 12:41:48.424844 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11024 12:41:48.436568 /lava-10724861/1/../bin/lava-test-case
11025 12:41:48.442801 <8>[ 18.159935] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11026 12:41:48.443055 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11028 12:41:48.454354 /lava-10724861/1/../bin/lava-test-case
11029 12:41:48.460548 <8>[ 18.177888] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11030 12:41:48.460799 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11032 12:41:49.473149 /lava-10724861/1/../bin/lava-test-case
11033 12:41:49.479629 <8>[ 19.197070] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail>
11034 12:41:49.479885 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail
11036 12:41:50.491540 /lava-10724861/1/../bin/lava-test-case
11037 12:41:50.498453 <8>[ 20.215491] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked>
11038 12:41:50.499126 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked
11039 12:41:50.499545 Bad test result: blocked
11040 12:41:50.508474 /lava-10724861/1/../bin/lava-test-case
11041 12:41:50.514904 <8>[ 20.231759] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11042 12:41:50.515569 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11044 12:41:50.526815 /lava-10724861/1/../bin/lava-test-case
11045 12:41:50.532835 <8>[ 20.249620] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11046 12:41:50.533637 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11048 12:41:50.544285 /lava-10724861/1/../bin/lava-test-case
11049 12:41:50.551184 <8>[ 20.267751] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11050 12:41:50.551850 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11052 12:41:50.562088 /lava-10724861/1/../bin/lava-test-case
11053 12:41:50.568657 <8>[ 20.285450] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11054 12:41:50.569319 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11056 12:41:50.580131 /lava-10724861/1/../bin/lava-test-case
11057 12:41:50.586449 <8>[ 20.303458] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11058 12:41:50.587111 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11060 12:41:50.596807 /lava-10724861/1/../bin/lava-test-case
11061 12:41:50.603436 <8>[ 20.321086] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11062 12:41:50.604155 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11064 12:41:50.613180 /lava-10724861/1/../bin/lava-test-case
11065 12:41:50.619581 <8>[ 20.337025] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11066 12:41:50.620358 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11068 12:41:50.632067 /lava-10724861/1/../bin/lava-test-case
11069 12:41:50.638388 <8>[ 20.355541] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11070 12:41:50.639123 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11072 12:41:50.649610 /lava-10724861/1/../bin/lava-test-case
11073 12:41:50.655829 <8>[ 20.372744] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11074 12:41:50.656592 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11076 12:41:50.664341 /lava-10724861/1/../bin/lava-test-case
11077 12:41:50.671042 <8>[ 20.388067] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11078 12:41:50.671715 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11080 12:41:50.683041 /lava-10724861/1/../bin/lava-test-case
11081 12:41:50.689476 <8>[ 20.406269] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11082 12:41:50.690138 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11084 12:41:50.698690 /lava-10724861/1/../bin/lava-test-case
11085 12:41:50.704973 <8>[ 20.422053] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11086 12:41:50.705716 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11088 12:41:50.717786 /lava-10724861/1/../bin/lava-test-case
11089 12:41:50.724408 <8>[ 20.441351] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11090 12:41:50.725081 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11092 12:41:50.733729 /lava-10724861/1/../bin/lava-test-case
11093 12:41:50.740059 <8>[ 20.457332] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11094 12:41:50.740740 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11096 12:41:50.752151 /lava-10724861/1/../bin/lava-test-case
11097 12:41:50.758599 <8>[ 20.475640] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11098 12:41:50.759267 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11100 12:41:50.771296 /lava-10724861/1/../bin/lava-test-case
11101 12:41:50.777384 <8>[ 20.494589] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11102 12:41:50.778052 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11104 12:41:50.788854 /lava-10724861/1/../bin/lava-test-case
11105 12:41:50.795404 <8>[ 20.512684] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11106 12:41:50.796149 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11108 12:41:50.807047 /lava-10724861/1/../bin/lava-test-case
11109 12:41:50.813867 <8>[ 20.531018] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11110 12:41:50.814531 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11112 12:41:50.825518 /lava-10724861/1/../bin/lava-test-case
11113 12:41:50.832301 <8>[ 20.549416] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11114 12:41:50.832970 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11116 12:41:50.843439 /lava-10724861/1/../bin/lava-test-case
11117 12:41:50.849800 <8>[ 20.567238] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11118 12:41:50.850483 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11120 12:41:50.862155 /lava-10724861/1/../bin/lava-test-case
11121 12:41:50.868561 <8>[ 20.585562] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11122 12:41:50.869295 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11124 12:41:50.880288 /lava-10724861/1/../bin/lava-test-case
11125 12:41:50.886773 <8>[ 20.603625] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11126 12:41:50.887582 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11128 12:41:50.898425 /lava-10724861/1/../bin/lava-test-case
11129 12:41:50.904794 <8>[ 20.622300] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11130 12:41:50.905575 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11132 12:41:50.916326 /lava-10724861/1/../bin/lava-test-case
11133 12:41:50.922899 <8>[ 20.640254] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11134 12:41:50.923669 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11136 12:41:50.934602 /lava-10724861/1/../bin/lava-test-case
11137 12:41:50.941243 <8>[ 20.658303] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11138 12:41:50.941931 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11140 12:41:50.952116 /lava-10724861/1/../bin/lava-test-case
11141 12:41:50.959088 <8>[ 20.675940] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11142 12:41:50.959771 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11144 12:41:50.970821 /lava-10724861/1/../bin/lava-test-case
11145 12:41:50.977459 <8>[ 20.694704] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11146 12:41:50.978143 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11148 12:41:50.988677 /lava-10724861/1/../bin/lava-test-case
11149 12:41:50.995478 <8>[ 20.712158] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11150 12:41:50.996196 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11152 12:41:51.006822 /lava-10724861/1/../bin/lava-test-case
11153 12:41:51.013673 <8>[ 20.730565] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11154 12:41:51.014436 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11156 12:41:51.023366 /lava-10724861/1/../bin/lava-test-case
11157 12:41:51.029851 <8>[ 20.746972] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11158 12:41:51.030533 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11160 12:41:51.042086 /lava-10724861/1/../bin/lava-test-case
11161 12:41:51.048486 <8>[ 20.765583] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11162 12:41:51.049178 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11164 12:41:51.058166 /lava-10724861/1/../bin/lava-test-case
11165 12:41:51.064442 <8>[ 20.781361] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11166 12:41:51.065122 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11168 12:41:51.076387 /lava-10724861/1/../bin/lava-test-case
11169 12:41:51.083057 <8>[ 20.800195] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11170 12:41:51.083779 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11172 12:41:51.091728 /lava-10724861/1/../bin/lava-test-case
11173 12:41:51.098529 <8>[ 20.815904] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11174 12:41:51.099221 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11176 12:41:51.111159 /lava-10724861/1/../bin/lava-test-case
11177 12:41:51.117609 <8>[ 20.835003] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11178 12:41:51.118292 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11180 12:41:51.127633 /lava-10724861/1/../bin/lava-test-case
11181 12:41:51.133935 <8>[ 20.851506] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11182 12:41:51.134623 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11184 12:41:51.146499 /lava-10724861/1/../bin/lava-test-case
11185 12:41:51.153282 <8>[ 20.870608] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11186 12:41:51.154048 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11188 12:41:51.163135 /lava-10724861/1/../bin/lava-test-case
11189 12:41:51.169681 <8>[ 20.886577] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11190 12:41:51.170367 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11192 12:41:51.182442 /lava-10724861/1/../bin/lava-test-case
11193 12:41:51.188664 <8>[ 20.905685] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11194 12:41:51.189373 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11196 12:41:51.198093 /lava-10724861/1/../bin/lava-test-case
11197 12:41:51.204611 <8>[ 20.921482] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11198 12:41:51.205424 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11200 12:41:51.216975 /lava-10724861/1/../bin/lava-test-case
11201 12:41:51.223531 <8>[ 20.940764] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11202 12:41:51.224239 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11204 12:41:51.235749 /lava-10724861/1/../bin/lava-test-case
11205 12:41:51.242381 <8>[ 20.958793] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11206 12:41:51.243059 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11208 12:41:51.251780 /lava-10724861/1/../bin/lava-test-case
11209 12:41:51.258061 <8>[ 20.975225] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11210 12:41:51.258745 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11212 12:41:51.270110 /lava-10724861/1/../bin/lava-test-case
11213 12:41:51.276643 <8>[ 20.993271] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11214 12:41:51.277343 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11216 12:41:51.285923 /lava-10724861/1/../bin/lava-test-case
11217 12:41:51.292487 <8>[ 21.009017] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11218 12:41:51.293167 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11220 12:41:51.303491 /lava-10724861/1/../bin/lava-test-case
11221 12:41:51.309733 <8>[ 21.026403] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11222 12:41:51.310415 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11224 12:41:51.318390 /lava-10724861/1/../bin/lava-test-case
11225 12:41:51.324941 <8>[ 21.041969] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11226 12:41:51.325621 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11228 12:41:52.338360 /lava-10724861/1/../bin/lava-test-case
11229 12:41:52.344588 <8>[ 22.062365] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11230 12:41:52.345268 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11232 12:41:52.353409 /lava-10724861/1/../bin/lava-test-case
11233 12:41:52.359738 <8>[ 22.077623] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11234 12:41:52.360436 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11236 12:41:53.374337 /lava-10724861/1/../bin/lava-test-case
11237 12:41:53.381147 <8>[ 23.098616] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11238 12:41:53.381845 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11240 12:41:53.390104 /lava-10724861/1/../bin/lava-test-case
11241 12:41:53.396982 <8>[ 23.114266] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11242 12:41:53.397669 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11244 12:41:54.411237 /lava-10724861/1/../bin/lava-test-case
11245 12:41:54.417495 <8>[ 24.135429] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11246 12:41:54.418211 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11248 12:41:54.427437 /lava-10724861/1/../bin/lava-test-case
11249 12:41:54.434229 <8>[ 24.151605] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11250 12:41:54.434900 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11252 12:41:55.447549 /lava-10724861/1/../bin/lava-test-case
11253 12:41:55.453633 <8>[ 25.172593] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11254 12:41:55.454309 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11256 12:41:55.463470 /lava-10724861/1/../bin/lava-test-case
11257 12:41:55.470518 <8>[ 25.187662] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11258 12:41:55.471193 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11260 12:41:56.483265 /lava-10724861/1/../bin/lava-test-case
11261 12:41:56.489720 <8>[ 26.208075] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11262 12:41:56.490393 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11264 12:41:56.499339 /lava-10724861/1/../bin/lava-test-case
11265 12:41:56.505845 <8>[ 26.223398] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11266 12:41:56.506570 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11268 12:41:57.519693 /lava-10724861/1/../bin/lava-test-case
11269 12:41:57.526236 <8>[ 27.245086] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11270 12:41:57.526514 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11272 12:41:57.536224 /lava-10724861/1/../bin/lava-test-case
11273 12:41:57.542754 <8>[ 27.260717] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11274 12:41:57.543009 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11276 12:41:58.556163 /lava-10724861/1/../bin/lava-test-case
11277 12:41:58.563001 <8>[ 28.281615] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11278 12:41:58.563296 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11280 12:41:58.572474 /lava-10724861/1/../bin/lava-test-case
11281 12:41:58.578750 <8>[ 28.296770] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11282 12:41:58.579010 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11284 12:41:58.587924 /lava-10724861/1/../bin/lava-test-case
11285 12:41:58.594918 <8>[ 28.312821] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11286 12:41:58.595179 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11288 12:41:59.608309 /lava-10724861/1/../bin/lava-test-case
11289 12:41:59.614962 <8>[ 29.333698] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11290 12:41:59.615219 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11292 12:41:59.624417 /lava-10724861/1/../bin/lava-test-case
11293 12:41:59.631297 <8>[ 29.349824] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11294 12:41:59.631557 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11296 12:41:59.643059 /lava-10724861/1/../bin/lava-test-case
11297 12:41:59.649643 <8>[ 29.368060] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11298 12:41:59.649920 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11300 12:41:59.658869 /lava-10724861/1/../bin/lava-test-case
11301 12:41:59.665607 <8>[ 29.383695] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11302 12:41:59.665882 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11304 12:41:59.677290 /lava-10724861/1/../bin/lava-test-case
11305 12:41:59.683611 <8>[ 29.401745] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11306 12:41:59.683869 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11308 12:41:59.694970 /lava-10724861/1/../bin/lava-test-case
11309 12:41:59.701501 <8>[ 29.419622] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11310 12:41:59.701775 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11312 12:41:59.712648 /lava-10724861/1/../bin/lava-test-case
11313 12:41:59.719027 <8>[ 29.437537] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11314 12:41:59.719271 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11316 12:41:59.728899 /lava-10724861/1/../bin/lava-test-case
11317 12:41:59.735489 <8>[ 29.453699] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11318 12:41:59.735742 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11320 12:41:59.747648 /lava-10724861/1/../bin/lava-test-case
11321 12:41:59.754051 <8>[ 29.472516] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11322 12:41:59.754306 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11324 12:41:59.766465 /lava-10724861/1/../bin/lava-test-case
11325 12:41:59.772807 <8>[ 29.491151] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11326 12:41:59.773091 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11328 12:41:59.781907 /lava-10724861/1/../bin/lava-test-case
11329 12:41:59.788776 <8>[ 29.506672] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11330 12:41:59.789034 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11332 12:41:59.800725 /lava-10724861/1/../bin/lava-test-case
11333 12:41:59.806984 <8>[ 29.525072] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11334 12:41:59.807266 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11336 12:41:59.816350 /lava-10724861/1/../bin/lava-test-case
11337 12:41:59.822876 <8>[ 29.540962] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11338 12:41:59.823150 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11340 12:41:59.834292 /lava-10724861/1/../bin/lava-test-case
11341 12:41:59.841265 <8>[ 29.559386] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11342 12:41:59.841515 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11344 12:41:59.850284 /lava-10724861/1/../bin/lava-test-case
11345 12:41:59.856779 <8>[ 29.575657] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11346 12:41:59.857024 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11348 12:41:59.869457 /lava-10724861/1/../bin/lava-test-case
11349 12:41:59.875809 <8>[ 29.593823] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11350 12:41:59.876069 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11352 12:41:59.886113 /lava-10724861/1/../bin/lava-test-case
11353 12:41:59.892257 <8>[ 29.610480] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11354 12:41:59.892507 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11356 12:41:59.904206 /lava-10724861/1/../bin/lava-test-case
11357 12:41:59.910697 <8>[ 29.628935] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11358 12:41:59.910944 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11360 12:41:59.921058 /lava-10724861/1/../bin/lava-test-case
11361 12:41:59.927430 <8>[ 29.645299] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11362 12:41:59.927676 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11364 12:41:59.938197 /lava-10724861/1/../bin/lava-test-case
11365 12:41:59.945241 <8>[ 29.663336] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11366 12:41:59.945490 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11368 12:41:59.953732 /lava-10724861/1/../bin/lava-test-case
11369 12:41:59.960497 <8>[ 29.678865] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11370 12:41:59.960755 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11372 12:42:00.973669 /lava-10724861/1/../bin/lava-test-case
11373 12:42:00.980249 <8>[ 30.699812] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11374 12:42:00.980567 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11376 12:42:01.993866 /lava-10724861/1/../bin/lava-test-case
11377 12:42:02.001165 <8>[ 31.719639] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11378 12:42:02.001441 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11380 12:42:02.009589 /lava-10724861/1/../bin/lava-test-case
11381 12:42:02.016426 <8>[ 31.735537] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11382 12:42:02.016730 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11384 12:42:02.028471 /lava-10724861/1/../bin/lava-test-case
11385 12:42:02.035311 <8>[ 31.753739] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11386 12:42:02.035564 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11388 12:42:02.044540 /lava-10724861/1/../bin/lava-test-case
11389 12:42:02.050845 <8>[ 31.769419] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11390 12:42:02.051098 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11392 12:42:02.062852 /lava-10724861/1/../bin/lava-test-case
11393 12:42:02.069636 <8>[ 31.788551] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11394 12:42:02.069890 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11396 12:42:02.078714 /lava-10724861/1/../bin/lava-test-case
11397 12:42:02.085557 <8>[ 31.804373] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11398 12:42:02.085811 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11400 12:42:02.097096 /lava-10724861/1/../bin/lava-test-case
11401 12:42:02.103400 <8>[ 31.821694] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11402 12:42:02.103678 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11404 12:42:02.112193 /lava-10724861/1/../bin/lava-test-case
11405 12:42:02.118926 <8>[ 31.837799] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11406 12:42:02.119178 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11408 12:42:02.131045 /lava-10724861/1/../bin/lava-test-case
11409 12:42:02.137463 <8>[ 31.856297] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11410 12:42:02.137714 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11412 12:42:02.147116 /lava-10724861/1/../bin/lava-test-case
11413 12:42:02.153370 <8>[ 31.872527] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11414 12:42:02.153630 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11416 12:42:02.165704 /lava-10724861/1/../bin/lava-test-case
11417 12:42:02.171716 <8>[ 31.890809] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11418 12:42:02.171966 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11420 12:42:02.180236 /lava-10724861/1/../bin/lava-test-case
11421 12:42:02.186783 <8>[ 31.905966] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11422 12:42:02.187036 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11424 12:42:02.199028 /lava-10724861/1/../bin/lava-test-case
11425 12:42:02.205618 <8>[ 31.924521] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11426 12:42:02.205883 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11428 12:42:02.215661 /lava-10724861/1/../bin/lava-test-case
11429 12:42:02.221483 <8>[ 31.940773] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11430 12:42:02.221735 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11432 12:42:02.233794 /lava-10724861/1/../bin/lava-test-case
11433 12:42:02.240660 <8>[ 31.959155] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11434 12:42:02.240919 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11436 12:42:02.249554 /lava-10724861/1/../bin/lava-test-case
11437 12:42:02.256087 <8>[ 31.974602] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11438 12:42:02.256338 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11440 12:42:02.268658 /lava-10724861/1/../bin/lava-test-case
11441 12:42:02.274670 <8>[ 31.993587] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11442 12:42:02.274943 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11444 12:42:02.283655 /lava-10724861/1/../bin/lava-test-case
11445 12:42:02.289963 <8>[ 32.008897] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11446 12:42:02.290240 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11448 12:42:02.301812 /lava-10724861/1/../bin/lava-test-case
11449 12:42:02.308394 <8>[ 32.027303] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11450 12:42:02.308649 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11452 12:42:02.317774 /lava-10724861/1/../bin/lava-test-case
11453 12:42:02.324624 <8>[ 32.042893] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11454 12:42:02.324877 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11456 12:42:02.337296 /lava-10724861/1/../bin/lava-test-case
11457 12:42:02.343443 <8>[ 32.062088] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11458 12:42:02.343704 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11460 12:42:03.354562 /lava-10724861/1/../bin/lava-test-case
11461 12:42:03.361767 <8>[ 33.080479] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11462 12:42:03.362529 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11464 12:42:04.373573 /lava-10724861/1/../bin/lava-test-case
11465 12:42:04.380134 <8>[ 34.099333] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11466 12:42:04.380937 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11467 12:42:04.381383 Bad test result: blocked
11468 12:42:04.389948 /lava-10724861/1/../bin/lava-test-case
11469 12:42:04.396251 <8>[ 34.115216] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11470 12:42:04.396952 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11472 12:42:05.409578 /lava-10724861/1/../bin/lava-test-case
11473 12:42:05.416071 <8>[ 35.135691] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11474 12:42:05.416341 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11476 12:42:05.425715 /lava-10724861/1/../bin/lava-test-case
11477 12:42:05.432081 <8>[ 35.151234] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11478 12:42:05.432335 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11480 12:42:05.442705 /lava-10724861/1/../bin/lava-test-case
11481 12:42:05.449408 <8>[ 35.168699] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11482 12:42:05.449664 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11484 12:42:05.460700 /lava-10724861/1/../bin/lava-test-case
11485 12:42:05.467005 <8>[ 35.186083] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11486 12:42:05.467258 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11488 12:42:05.475417 /lava-10724861/1/../bin/lava-test-case
11489 12:42:05.482053 <8>[ 35.201739] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11490 12:42:05.482337 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11492 12:42:05.494432 /lava-10724861/1/../bin/lava-test-case
11493 12:42:05.501020 <8>[ 35.220299] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11494 12:42:05.501275 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11496 12:42:05.509927 /lava-10724861/1/../bin/lava-test-case
11497 12:42:05.516555 <8>[ 35.235707] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11498 12:42:05.516809 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11500 12:42:06.530210 /lava-10724861/1/../bin/lava-test-case
11501 12:42:06.536451 <8>[ 36.256373] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11502 12:42:06.536710 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11504 12:42:06.545810 /lava-10724861/1/../bin/lava-test-case
11505 12:42:06.552206 <8>[ 36.271989] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11506 12:42:06.552459 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11508 12:42:07.565947 /lava-10724861/1/../bin/lava-test-case
11509 12:42:07.572318 <8>[ 37.292634] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11510 12:42:07.572587 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11512 12:42:07.582107 /lava-10724861/1/../bin/lava-test-case
11513 12:42:07.588693 <8>[ 37.307730] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11514 12:42:07.588945 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11516 12:42:08.601815 /lava-10724861/1/../bin/lava-test-case
11517 12:42:08.608251 <8>[ 38.327834] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11518 12:42:08.608980 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11520 12:42:08.618125 /lava-10724861/1/../bin/lava-test-case
11521 12:42:08.624675 <8>[ 38.343677] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11522 12:42:08.625410 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11524 12:42:09.638336 /lava-10724861/1/../bin/lava-test-case
11525 12:42:09.644512 <8>[ 39.364840] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11526 12:42:09.644794 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11528 12:42:09.654688 /lava-10724861/1/../bin/lava-test-case
11529 12:42:09.661228 <8>[ 39.381135] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11530 12:42:09.661504 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11532 12:42:09.672549 /lava-10724861/1/../bin/lava-test-case
11533 12:42:09.679146 <8>[ 39.398881] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11534 12:42:09.679417 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11536 12:42:09.689460 /lava-10724861/1/../bin/lava-test-case
11537 12:42:09.696136 <8>[ 39.415702] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11538 12:42:09.696405 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11540 12:42:09.704270 /lava-10724861/1/../bin/lava-test-case
11541 12:42:09.711046 <8>[ 39.431059] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11542 12:42:09.711355 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11544 12:42:09.722567 /lava-10724861/1/../bin/lava-test-case
11545 12:42:09.729464 <8>[ 39.448548] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11546 12:42:09.729747 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11548 12:42:09.738258 /lava-10724861/1/../bin/lava-test-case
11549 12:42:09.744460 <8>[ 39.464018] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11550 12:42:09.744722 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11552 12:42:09.757080 /lava-10724861/1/../bin/lava-test-case
11553 12:42:09.763594 <8>[ 39.483110] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11554 12:42:09.763858 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11556 12:42:09.772698 /lava-10724861/1/../bin/lava-test-case
11557 12:42:09.779047 <8>[ 39.498431] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11558 12:42:09.779312 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11560 12:42:10.793211 /lava-10724861/1/../bin/lava-test-case
11561 12:42:10.799533 <8>[ 40.519929] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail>
11562 12:42:10.800246 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail
11564 12:42:10.804707 + set +x
11565 12:42:10.808118 Received signal: <ENDRUN> 1_bootrr 10724861_1.5.2.3.5
11566 12:42:10.808570 Ending use of test pattern.
11567 12:42:10.808913 Ending test lava.1_bootrr (10724861_1.5.2.3.5), duration 23.28
11569 12:42:10.810771 <8>[ 40.530348] <LAVA_SIGNAL_ENDRUN 1_bootrr 10724861_1.5.2.3.5>
11570 12:42:10.811321 <LAVA_TEST_RUNNER EXIT>
11571 12:42:10.811918 ok: lava_test_shell seems to have completed
11572 12:42:10.816923 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: fail
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: fail
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: pass
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11573 12:42:10.817631 end: 4.1 lava-test-shell (duration 00:00:24) [common]
11574 12:42:10.818068 end: 4 lava-test-retry (duration 00:00:24) [common]
11575 12:42:10.818507 start: 5 finalize (timeout 00:07:45) [common]
11576 12:42:10.818971 start: 5.1 power-off (timeout 00:00:30) [common]
11577 12:42:10.819732 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11578 12:42:10.938315 >> Command sent successfully.
11579 12:42:10.940640 Returned 0 in 0 seconds
11580 12:42:11.041349 end: 5.1 power-off (duration 00:00:00) [common]
11582 12:42:11.042762 start: 5.2 read-feedback (timeout 00:07:45) [common]
11583 12:42:11.043936 Listened to connection for namespace 'common' for up to 1s
11584 12:42:11.044801 Listened to connection for namespace 'common' for up to 1s
11585 12:42:12.044556 Finalising connection for namespace 'common'
11586 12:42:12.044753 Disconnecting from shell: Finalise
11587 12:42:12.044840 / #
11588 12:42:12.145179 end: 5.2 read-feedback (duration 00:00:01) [common]
11589 12:42:12.145360 end: 5 finalize (duration 00:00:01) [common]
11590 12:42:12.145476 Cleaning after the job
11591 12:42:12.145575 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724861/tftp-deploy-sv2o19vw/ramdisk
11592 12:42:12.147977 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724861/tftp-deploy-sv2o19vw/kernel
11593 12:42:12.154036 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724861/tftp-deploy-sv2o19vw/dtb
11594 12:42:12.154199 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724861/tftp-deploy-sv2o19vw/modules
11595 12:42:12.159516 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10724861
11596 12:42:12.196510 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10724861
11597 12:42:12.196687 Job finished correctly