Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 28
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
- Errors: 0
1 12:42:38.128858 lava-dispatcher, installed at version: 2023.05.1
2 12:42:38.129053 start: 0 validate
3 12:42:38.129183 Start time: 2023-06-14 12:42:38.129176+00:00 (UTC)
4 12:42:38.129301 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:42:38.129428 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230609.0%2Farm64%2Frootfs.cpio.gz exists
6 12:42:38.393813 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:42:38.394608 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:42:38.658807 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:42:38.659622 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:42:38.931328 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:42:38.932185 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:42:39.194600 validate duration: 1.07
14 12:42:39.194860 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:42:39.194957 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:42:39.195042 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:42:39.195164 Not decompressing ramdisk as can be used compressed.
18 12:42:39.195245 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230609.0/arm64/rootfs.cpio.gz
19 12:42:39.195308 saving as /var/lib/lava/dispatcher/tmp/10724871/tftp-deploy-y2kwtekg/ramdisk/rootfs.cpio.gz
20 12:42:39.195367 total size: 34417816 (32MB)
21 12:42:39.196434 progress 0% (0MB)
22 12:42:39.205068 progress 5% (1MB)
23 12:42:39.213857 progress 10% (3MB)
24 12:42:39.222369 progress 15% (4MB)
25 12:42:39.231205 progress 20% (6MB)
26 12:42:39.239736 progress 25% (8MB)
27 12:42:39.248474 progress 30% (9MB)
28 12:42:39.257086 progress 35% (11MB)
29 12:42:39.265861 progress 40% (13MB)
30 12:42:39.274488 progress 45% (14MB)
31 12:42:39.283420 progress 50% (16MB)
32 12:42:39.292007 progress 55% (18MB)
33 12:42:39.300761 progress 60% (19MB)
34 12:42:39.309325 progress 65% (21MB)
35 12:42:39.318031 progress 70% (23MB)
36 12:42:39.326535 progress 75% (24MB)
37 12:42:39.335214 progress 80% (26MB)
38 12:42:39.343767 progress 85% (27MB)
39 12:42:39.352411 progress 90% (29MB)
40 12:42:39.360854 progress 95% (31MB)
41 12:42:39.369475 progress 100% (32MB)
42 12:42:39.369645 32MB downloaded in 0.17s (188.34MB/s)
43 12:42:39.369800 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:42:39.370037 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:42:39.370120 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:42:39.370203 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:42:39.370332 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:42:39.370404 saving as /var/lib/lava/dispatcher/tmp/10724871/tftp-deploy-y2kwtekg/kernel/Image
50 12:42:39.370466 total size: 47581696 (45MB)
51 12:42:39.370526 No compression specified
52 12:42:39.371597 progress 0% (0MB)
53 12:42:39.383550 progress 5% (2MB)
54 12:42:39.395563 progress 10% (4MB)
55 12:42:39.407392 progress 15% (6MB)
56 12:42:39.419349 progress 20% (9MB)
57 12:42:39.431259 progress 25% (11MB)
58 12:42:39.443013 progress 30% (13MB)
59 12:42:39.454994 progress 35% (15MB)
60 12:42:39.466884 progress 40% (18MB)
61 12:42:39.478972 progress 45% (20MB)
62 12:42:39.490982 progress 50% (22MB)
63 12:42:39.502878 progress 55% (24MB)
64 12:42:39.514839 progress 60% (27MB)
65 12:42:39.526603 progress 65% (29MB)
66 12:42:39.538647 progress 70% (31MB)
67 12:42:39.550676 progress 75% (34MB)
68 12:42:39.562572 progress 80% (36MB)
69 12:42:39.574987 progress 85% (38MB)
70 12:42:39.587004 progress 90% (40MB)
71 12:42:39.598999 progress 95% (43MB)
72 12:42:39.610902 progress 100% (45MB)
73 12:42:39.611048 45MB downloaded in 0.24s (188.62MB/s)
74 12:42:39.611196 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:42:39.611423 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:42:39.611542 start: 1.3 download-retry (timeout 00:10:00) [common]
78 12:42:39.611626 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 12:42:39.611763 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:42:39.611833 saving as /var/lib/lava/dispatcher/tmp/10724871/tftp-deploy-y2kwtekg/dtb/mt8192-asurada-spherion-r0.dtb
81 12:42:39.611895 total size: 46924 (0MB)
82 12:42:39.611954 No compression specified
83 12:42:39.613083 progress 69% (0MB)
84 12:42:39.613353 progress 100% (0MB)
85 12:42:39.613550 0MB downloaded in 0.00s (27.08MB/s)
86 12:42:39.613670 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:42:39.613888 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:42:39.613971 start: 1.4 download-retry (timeout 00:10:00) [common]
90 12:42:39.614052 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 12:42:39.614158 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:42:39.614226 saving as /var/lib/lava/dispatcher/tmp/10724871/tftp-deploy-y2kwtekg/modules/modules.tar
93 12:42:39.614286 total size: 8536768 (8MB)
94 12:42:39.614345 Using unxz to decompress xz
95 12:42:39.617974 progress 0% (0MB)
96 12:42:39.638662 progress 5% (0MB)
97 12:42:39.664928 progress 10% (0MB)
98 12:42:39.695394 progress 15% (1MB)
99 12:42:39.719010 progress 20% (1MB)
100 12:42:39.742188 progress 25% (2MB)
101 12:42:39.766341 progress 30% (2MB)
102 12:42:39.789685 progress 35% (2MB)
103 12:42:39.816356 progress 40% (3MB)
104 12:42:39.840836 progress 45% (3MB)
105 12:42:39.866502 progress 50% (4MB)
106 12:42:39.890976 progress 55% (4MB)
107 12:42:39.915879 progress 60% (4MB)
108 12:42:39.940798 progress 65% (5MB)
109 12:42:39.965409 progress 70% (5MB)
110 12:42:39.989470 progress 75% (6MB)
111 12:42:40.013054 progress 80% (6MB)
112 12:42:40.037665 progress 85% (6MB)
113 12:42:40.062835 progress 90% (7MB)
114 12:42:40.087297 progress 95% (7MB)
115 12:42:40.109534 progress 100% (8MB)
116 12:42:40.115982 8MB downloaded in 0.50s (16.23MB/s)
117 12:42:40.116267 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:42:40.116526 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:42:40.116618 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 12:42:40.116711 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 12:42:40.116793 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:42:40.116875 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 12:42:40.117094 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10724871/lava-overlay-cqkqjrtm
125 12:42:40.117219 makedir: /var/lib/lava/dispatcher/tmp/10724871/lava-overlay-cqkqjrtm/lava-10724871/bin
126 12:42:40.117320 makedir: /var/lib/lava/dispatcher/tmp/10724871/lava-overlay-cqkqjrtm/lava-10724871/tests
127 12:42:40.117414 makedir: /var/lib/lava/dispatcher/tmp/10724871/lava-overlay-cqkqjrtm/lava-10724871/results
128 12:42:40.117529 Creating /var/lib/lava/dispatcher/tmp/10724871/lava-overlay-cqkqjrtm/lava-10724871/bin/lava-add-keys
129 12:42:40.117667 Creating /var/lib/lava/dispatcher/tmp/10724871/lava-overlay-cqkqjrtm/lava-10724871/bin/lava-add-sources
130 12:42:40.117794 Creating /var/lib/lava/dispatcher/tmp/10724871/lava-overlay-cqkqjrtm/lava-10724871/bin/lava-background-process-start
131 12:42:40.117920 Creating /var/lib/lava/dispatcher/tmp/10724871/lava-overlay-cqkqjrtm/lava-10724871/bin/lava-background-process-stop
132 12:42:40.118039 Creating /var/lib/lava/dispatcher/tmp/10724871/lava-overlay-cqkqjrtm/lava-10724871/bin/lava-common-functions
133 12:42:40.118156 Creating /var/lib/lava/dispatcher/tmp/10724871/lava-overlay-cqkqjrtm/lava-10724871/bin/lava-echo-ipv4
134 12:42:40.118277 Creating /var/lib/lava/dispatcher/tmp/10724871/lava-overlay-cqkqjrtm/lava-10724871/bin/lava-install-packages
135 12:42:40.118397 Creating /var/lib/lava/dispatcher/tmp/10724871/lava-overlay-cqkqjrtm/lava-10724871/bin/lava-installed-packages
136 12:42:40.118514 Creating /var/lib/lava/dispatcher/tmp/10724871/lava-overlay-cqkqjrtm/lava-10724871/bin/lava-os-build
137 12:42:40.118632 Creating /var/lib/lava/dispatcher/tmp/10724871/lava-overlay-cqkqjrtm/lava-10724871/bin/lava-probe-channel
138 12:42:40.118749 Creating /var/lib/lava/dispatcher/tmp/10724871/lava-overlay-cqkqjrtm/lava-10724871/bin/lava-probe-ip
139 12:42:40.118865 Creating /var/lib/lava/dispatcher/tmp/10724871/lava-overlay-cqkqjrtm/lava-10724871/bin/lava-target-ip
140 12:42:40.118983 Creating /var/lib/lava/dispatcher/tmp/10724871/lava-overlay-cqkqjrtm/lava-10724871/bin/lava-target-mac
141 12:42:40.119098 Creating /var/lib/lava/dispatcher/tmp/10724871/lava-overlay-cqkqjrtm/lava-10724871/bin/lava-target-storage
142 12:42:40.119218 Creating /var/lib/lava/dispatcher/tmp/10724871/lava-overlay-cqkqjrtm/lava-10724871/bin/lava-test-case
143 12:42:40.119336 Creating /var/lib/lava/dispatcher/tmp/10724871/lava-overlay-cqkqjrtm/lava-10724871/bin/lava-test-event
144 12:42:40.119452 Creating /var/lib/lava/dispatcher/tmp/10724871/lava-overlay-cqkqjrtm/lava-10724871/bin/lava-test-feedback
145 12:42:40.119568 Creating /var/lib/lava/dispatcher/tmp/10724871/lava-overlay-cqkqjrtm/lava-10724871/bin/lava-test-raise
146 12:42:40.119686 Creating /var/lib/lava/dispatcher/tmp/10724871/lava-overlay-cqkqjrtm/lava-10724871/bin/lava-test-reference
147 12:42:40.119802 Creating /var/lib/lava/dispatcher/tmp/10724871/lava-overlay-cqkqjrtm/lava-10724871/bin/lava-test-runner
148 12:42:40.119919 Creating /var/lib/lava/dispatcher/tmp/10724871/lava-overlay-cqkqjrtm/lava-10724871/bin/lava-test-set
149 12:42:40.120046 Creating /var/lib/lava/dispatcher/tmp/10724871/lava-overlay-cqkqjrtm/lava-10724871/bin/lava-test-shell
150 12:42:40.120172 Updating /var/lib/lava/dispatcher/tmp/10724871/lava-overlay-cqkqjrtm/lava-10724871/bin/lava-install-packages (oe)
151 12:42:40.120318 Updating /var/lib/lava/dispatcher/tmp/10724871/lava-overlay-cqkqjrtm/lava-10724871/bin/lava-installed-packages (oe)
152 12:42:40.120435 Creating /var/lib/lava/dispatcher/tmp/10724871/lava-overlay-cqkqjrtm/lava-10724871/environment
153 12:42:40.120540 LAVA metadata
154 12:42:40.120612 - LAVA_JOB_ID=10724871
155 12:42:40.120677 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:42:40.120777 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 12:42:40.120846 skipped lava-vland-overlay
158 12:42:40.120919 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:42:40.120998 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 12:42:40.121058 skipped lava-multinode-overlay
161 12:42:40.121132 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:42:40.121214 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 12:42:40.121286 Loading test definitions
164 12:42:40.121376 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 12:42:40.121452 Using /lava-10724871 at stage 0
166 12:42:40.121737 uuid=10724871_1.5.2.3.1 testdef=None
167 12:42:40.121824 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:42:40.121912 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 12:42:40.122397 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:42:40.122611 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 12:42:40.123200 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:42:40.123429 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 12:42:40.124001 runner path: /var/lib/lava/dispatcher/tmp/10724871/lava-overlay-cqkqjrtm/lava-10724871/0/tests/0_cros-ec test_uuid 10724871_1.5.2.3.1
176 12:42:40.124189 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:42:40.124396 Creating lava-test-runner.conf files
179 12:42:40.124458 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10724871/lava-overlay-cqkqjrtm/lava-10724871/0 for stage 0
180 12:42:40.124543 - 0_cros-ec
181 12:42:40.124636 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 12:42:40.124718 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 12:42:40.131143 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 12:42:40.131247 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 12:42:40.131335 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 12:42:40.131418 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 12:42:40.131507 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 12:42:41.073759 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 12:42:41.074232 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 12:42:41.074410 extracting modules file /var/lib/lava/dispatcher/tmp/10724871/tftp-deploy-y2kwtekg/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10724871/extract-overlay-ramdisk-yme8dj15/ramdisk
191 12:42:41.308038 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 12:42:41.308208 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 12:42:41.308321 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10724871/compress-overlay-581yuhd8/overlay-1.5.2.4.tar.gz to ramdisk
194 12:42:41.308428 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10724871/compress-overlay-581yuhd8/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10724871/extract-overlay-ramdisk-yme8dj15/ramdisk
195 12:42:41.314751 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 12:42:41.314866 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 12:42:41.314958 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 12:42:41.315046 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 12:42:41.315128 Building ramdisk /var/lib/lava/dispatcher/tmp/10724871/extract-overlay-ramdisk-yme8dj15/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10724871/extract-overlay-ramdisk-yme8dj15/ramdisk
200 12:42:42.015329 >> 269475 blocks
201 12:42:46.623822 rename /var/lib/lava/dispatcher/tmp/10724871/extract-overlay-ramdisk-yme8dj15/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10724871/tftp-deploy-y2kwtekg/ramdisk/ramdisk.cpio.gz
202 12:42:46.624259 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 12:42:46.624391 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 12:42:46.624487 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 12:42:46.624593 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10724871/tftp-deploy-y2kwtekg/kernel/Image'
206 12:42:58.884211 Returned 0 in 12 seconds
207 12:42:58.984841 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10724871/tftp-deploy-y2kwtekg/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10724871/tftp-deploy-y2kwtekg/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10724871/tftp-deploy-y2kwtekg/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10724871/tftp-deploy-y2kwtekg/kernel/image.itb
208 12:42:59.672060 output: FIT description: Kernel Image image with one or more FDT blobs
209 12:42:59.672410 output: Created: Wed Jun 14 13:42:59 2023
210 12:42:59.672492 output: Image 0 (kernel-1)
211 12:42:59.672560 output: Description:
212 12:42:59.672626 output: Created: Wed Jun 14 13:42:59 2023
213 12:42:59.672710 output: Type: Kernel Image
214 12:42:59.672775 output: Compression: lzma compressed
215 12:42:59.672833 output: Data Size: 10442380 Bytes = 10197.64 KiB = 9.96 MiB
216 12:42:59.672891 output: Architecture: AArch64
217 12:42:59.672948 output: OS: Linux
218 12:42:59.673003 output: Load Address: 0x00000000
219 12:42:59.673059 output: Entry Point: 0x00000000
220 12:42:59.673116 output: Hash algo: crc32
221 12:42:59.673169 output: Hash value: ced21bfe
222 12:42:59.673221 output: Image 1 (fdt-1)
223 12:42:59.673273 output: Description: mt8192-asurada-spherion-r0
224 12:42:59.673326 output: Created: Wed Jun 14 13:42:59 2023
225 12:42:59.673379 output: Type: Flat Device Tree
226 12:42:59.673432 output: Compression: uncompressed
227 12:42:59.673484 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 12:42:59.673537 output: Architecture: AArch64
229 12:42:59.673590 output: Hash algo: crc32
230 12:42:59.673642 output: Hash value: 1df858fa
231 12:42:59.673695 output: Image 2 (ramdisk-1)
232 12:42:59.673747 output: Description: unavailable
233 12:42:59.673799 output: Created: Wed Jun 14 13:42:59 2023
234 12:42:59.673875 output: Type: RAMDisk Image
235 12:42:59.673939 output: Compression: Unknown Compression
236 12:42:59.673993 output: Data Size: 47375532 Bytes = 46265.17 KiB = 45.18 MiB
237 12:42:59.674046 output: Architecture: AArch64
238 12:42:59.674100 output: OS: Linux
239 12:42:59.674152 output: Load Address: unavailable
240 12:42:59.674205 output: Entry Point: unavailable
241 12:42:59.674257 output: Hash algo: crc32
242 12:42:59.674309 output: Hash value: 6d8a6b15
243 12:42:59.674361 output: Default Configuration: 'conf-1'
244 12:42:59.674414 output: Configuration 0 (conf-1)
245 12:42:59.674466 output: Description: mt8192-asurada-spherion-r0
246 12:42:59.674519 output: Kernel: kernel-1
247 12:42:59.674571 output: Init Ramdisk: ramdisk-1
248 12:42:59.674623 output: FDT: fdt-1
249 12:42:59.674675 output: Loadables: kernel-1
250 12:42:59.674741 output:
251 12:42:59.674937 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 12:42:59.675039 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 12:42:59.675143 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 12:42:59.675237 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:40) [common]
255 12:42:59.675314 No LXC device requested
256 12:42:59.675395 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 12:42:59.675482 start: 1.7 deploy-device-env (timeout 00:09:40) [common]
258 12:42:59.675558 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 12:42:59.675624 Checking files for TFTP limit of 4294967296 bytes.
260 12:42:59.676123 end: 1 tftp-deploy (duration 00:00:20) [common]
261 12:42:59.676227 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 12:42:59.676315 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 12:42:59.676438 substitutions:
264 12:42:59.676506 - {DTB}: 10724871/tftp-deploy-y2kwtekg/dtb/mt8192-asurada-spherion-r0.dtb
265 12:42:59.676572 - {INITRD}: 10724871/tftp-deploy-y2kwtekg/ramdisk/ramdisk.cpio.gz
266 12:42:59.676632 - {KERNEL}: 10724871/tftp-deploy-y2kwtekg/kernel/Image
267 12:42:59.676695 - {LAVA_MAC}: None
268 12:42:59.676752 - {PRESEED_CONFIG}: None
269 12:42:59.676808 - {PRESEED_LOCAL}: None
270 12:42:59.676864 - {RAMDISK}: 10724871/tftp-deploy-y2kwtekg/ramdisk/ramdisk.cpio.gz
271 12:42:59.676919 - {ROOT_PART}: None
272 12:42:59.676974 - {ROOT}: None
273 12:42:59.677029 - {SERVER_IP}: 192.168.201.1
274 12:42:59.677082 - {TEE}: None
275 12:42:59.677136 Parsed boot commands:
276 12:42:59.677190 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 12:42:59.677359 Parsed boot commands: tftpboot 192.168.201.1 10724871/tftp-deploy-y2kwtekg/kernel/image.itb 10724871/tftp-deploy-y2kwtekg/kernel/cmdline
278 12:42:59.677451 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 12:42:59.677534 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 12:42:59.677623 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 12:42:59.677708 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 12:42:59.677778 Not connected, no need to disconnect.
283 12:42:59.677850 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 12:42:59.677929 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 12:42:59.677996 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-2'
286 12:42:59.681387 Setting prompt string to ['lava-test: # ']
287 12:42:59.681718 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 12:42:59.681825 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 12:42:59.681926 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 12:42:59.682019 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 12:42:59.682215 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
292 12:43:04.828275 >> Command sent successfully.
293 12:43:04.837967 Returned 0 in 5 seconds
294 12:43:04.939155 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 12:43:04.941820 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 12:43:04.942306 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 12:43:04.942748 Setting prompt string to 'Starting depthcharge on Spherion...'
299 12:43:04.943324 Changing prompt to 'Starting depthcharge on Spherion...'
300 12:43:04.943886 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 12:43:04.945162 [Enter `^Ec?' for help]
302 12:43:05.105685
303 12:43:05.106237
304 12:43:05.106594 F0: 102B 0000
305 12:43:05.106908
306 12:43:05.107210 F3: 1001 0000 [0200]
307 12:43:05.107524
308 12:43:05.108705 F3: 1001 0000
309 12:43:05.109134
310 12:43:05.109529 F7: 102D 0000
311 12:43:05.109844
312 12:43:05.112243 F1: 0000 0000
313 12:43:05.112674
314 12:43:05.113178 V0: 0000 0000 [0001]
315 12:43:05.113641
316 12:43:05.115841 00: 0007 8000
317 12:43:05.116335
318 12:43:05.116680 01: 0000 0000
319 12:43:05.117011
320 12:43:05.118566 BP: 0C00 0209 [0000]
321 12:43:05.118998
322 12:43:05.119338 G0: 1182 0000
323 12:43:05.119658
324 12:43:05.122308 EC: 0000 0021 [4000]
325 12:43:05.122738
326 12:43:05.123081 S7: 0000 0000 [0000]
327 12:43:05.123401
328 12:43:05.125614 CC: 0000 0000 [0001]
329 12:43:05.126045
330 12:43:05.126388 T0: 0000 0040 [010F]
331 12:43:05.126709
332 12:43:05.128802 Jump to BL
333 12:43:05.129230
334 12:43:05.152751
335 12:43:05.153249
336 12:43:05.153644
337 12:43:05.160027 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 12:43:05.163856 ARM64: Exception handlers installed.
339 12:43:05.167554 ARM64: Testing exception
340 12:43:05.170244 ARM64: Done test exception
341 12:43:05.177056 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 12:43:05.187491 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 12:43:05.193942 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 12:43:05.204148 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 12:43:05.210670 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 12:43:05.220060 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 12:43:05.231057 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 12:43:05.237899 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 12:43:05.255816 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 12:43:05.258917 WDT: Last reset was cold boot
351 12:43:05.262598 SPI1(PAD0) initialized at 2873684 Hz
352 12:43:05.265294 SPI5(PAD0) initialized at 992727 Hz
353 12:43:05.268606 VBOOT: Loading verstage.
354 12:43:05.275365 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 12:43:05.279175 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 12:43:05.281570 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 12:43:05.284996 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 12:43:05.292968 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 12:43:05.299527 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 12:43:05.311166 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 12:43:05.311755
362 12:43:05.312266
363 12:43:05.320755 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 12:43:05.323638 ARM64: Exception handlers installed.
365 12:43:05.326815 ARM64: Testing exception
366 12:43:05.327262 ARM64: Done test exception
367 12:43:05.334306 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 12:43:05.337883 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 12:43:05.351710 Probing TPM: . done!
370 12:43:05.352366 TPM ready after 0 ms
371 12:43:05.359370 Connected to device vid:did:rid of 1ae0:0028:00
372 12:43:05.365937 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
373 12:43:05.423421 Initialized TPM device CR50 revision 0
374 12:43:05.435259 tlcl_send_startup: Startup return code is 0
375 12:43:05.435762 TPM: setup succeeded
376 12:43:05.446661 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 12:43:05.455984 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 12:43:05.467978 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 12:43:05.477622 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 12:43:05.481553 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 12:43:05.485488 in-header: 03 07 00 00 08 00 00 00
382 12:43:05.489329 in-data: aa e4 47 04 13 02 00 00
383 12:43:05.492974 Chrome EC: UHEPI supported
384 12:43:05.499871 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 12:43:05.503378 in-header: 03 95 00 00 08 00 00 00
386 12:43:05.507279 in-data: 18 20 20 08 00 00 00 00
387 12:43:05.507832 Phase 1
388 12:43:05.511157 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 12:43:05.518323 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 12:43:05.522097 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 12:43:05.525832 Recovery requested (1009000e)
392 12:43:05.535068 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 12:43:05.541176 tlcl_extend: response is 0
394 12:43:05.549690 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 12:43:05.555182 tlcl_extend: response is 0
396 12:43:05.562094 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 12:43:05.582249 read SPI 0x210d4 0x2173b: 15141 us, 9049 KB/s, 72.392 Mbps
398 12:43:05.589221 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 12:43:05.589758
400 12:43:05.590105
401 12:43:05.599025 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 12:43:05.602461 ARM64: Exception handlers installed.
403 12:43:05.606028 ARM64: Testing exception
404 12:43:05.606546 ARM64: Done test exception
405 12:43:05.627523 pmic_efuse_setting: Set efuses in 11 msecs
406 12:43:05.630988 pmwrap_interface_init: Select PMIF_VLD_RDY
407 12:43:05.637977 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 12:43:05.640848 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 12:43:05.647551 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 12:43:05.651718 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 12:43:05.654821 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 12:43:05.662346 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 12:43:05.665701 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 12:43:05.669709 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 12:43:05.676551 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 12:43:05.680319 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 12:43:05.684721 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 12:43:05.688153 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 12:43:05.694795 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 12:43:05.698538 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 12:43:05.706121 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 12:43:05.709938 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 12:43:05.717663 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 12:43:05.724130 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 12:43:05.728006 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 12:43:05.735857 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 12:43:05.739632 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 12:43:05.743803 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 12:43:05.750963 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 12:43:05.757909 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 12:43:05.760960 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 12:43:05.768162 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 12:43:05.772520 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 12:43:05.775368 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 12:43:05.782652 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 12:43:05.786337 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 12:43:05.790422 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 12:43:05.797705 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 12:43:05.800894 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 12:43:05.808390 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 12:43:05.812076 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 12:43:05.815939 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 12:43:05.823188 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 12:43:05.826796 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 12:43:05.831156 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 12:43:05.834341 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 12:43:05.837976 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 12:43:05.845563 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 12:43:05.848953 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 12:43:05.852799 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 12:43:05.857287 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 12:43:05.860694 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 12:43:05.864431 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 12:43:05.871138 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 12:43:05.874548 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 12:43:05.878269 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 12:43:05.882740 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 12:43:05.889447 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 12:43:05.900390 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 12:43:05.903923 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 12:43:05.910935 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 12:43:05.922395 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 12:43:05.926338 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 12:43:05.929421 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 12:43:05.933264 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 12:43:05.940430 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x0
467 12:43:05.947849 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 12:43:05.951369 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
469 12:43:05.954767 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 12:43:05.964663 [RTC]rtc_get_frequency_meter,154: input=15, output=852
471 12:43:05.975176 [RTC]rtc_get_frequency_meter,154: input=7, output=724
472 12:43:05.984149 [RTC]rtc_get_frequency_meter,154: input=11, output=788
473 12:43:05.993383 [RTC]rtc_get_frequency_meter,154: input=13, output=820
474 12:43:06.002737 [RTC]rtc_get_frequency_meter,154: input=12, output=804
475 12:43:06.012930 [RTC]rtc_get_frequency_meter,154: input=11, output=789
476 12:43:06.022941 [RTC]rtc_get_frequency_meter,154: input=12, output=804
477 12:43:06.027022 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
478 12:43:06.030095 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
479 12:43:06.034018 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 12:43:06.040564 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 12:43:06.045496 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 12:43:06.047972 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 12:43:06.052005 ADC[4]: Raw value=902955 ID=7
484 12:43:06.052472 ADC[3]: Raw value=213177 ID=1
485 12:43:06.056337 RAM Code: 0x71
486 12:43:06.060346 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 12:43:06.063000 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 12:43:06.073975 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 12:43:06.081802 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 12:43:06.082396 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 12:43:06.085291 in-header: 03 07 00 00 08 00 00 00
492 12:43:06.089881 in-data: aa e4 47 04 13 02 00 00
493 12:43:06.093107 Chrome EC: UHEPI supported
494 12:43:06.100335 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 12:43:06.103976 in-header: 03 95 00 00 08 00 00 00
496 12:43:06.107449 in-data: 18 20 20 08 00 00 00 00
497 12:43:06.111599 MRC: failed to locate region type 0.
498 12:43:06.118845 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 12:43:06.119282 DRAM-K: Running full calibration
500 12:43:06.126033 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 12:43:06.126465 header.status = 0x0
502 12:43:06.129736 header.version = 0x6 (expected: 0x6)
503 12:43:06.133610 header.size = 0xd00 (expected: 0xd00)
504 12:43:06.137094 header.flags = 0x0
505 12:43:06.144325 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 12:43:06.161191 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 12:43:06.168301 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 12:43:06.168808 dram_init: ddr_geometry: 2
509 12:43:06.172167 [EMI] MDL number = 2
510 12:43:06.175349 [EMI] Get MDL freq = 0
511 12:43:06.175778 dram_init: ddr_type: 0
512 12:43:06.179013 is_discrete_lpddr4: 1
513 12:43:06.182951 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 12:43:06.183380
515 12:43:06.183721
516 12:43:06.184080 [Bian_co] ETT version 0.0.0.1
517 12:43:06.190004 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 12:43:06.190434
519 12:43:06.194212 dramc_set_vcore_voltage set vcore to 650000
520 12:43:06.194729 Read voltage for 800, 4
521 12:43:06.197421 Vio18 = 0
522 12:43:06.197869 Vcore = 650000
523 12:43:06.198214 Vdram = 0
524 12:43:06.198534 Vddq = 0
525 12:43:06.201219 Vmddr = 0
526 12:43:06.201752 dram_init: config_dvfs: 1
527 12:43:06.207966 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 12:43:06.211452 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 12:43:06.214739 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 12:43:06.221670 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 12:43:06.224739 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 12:43:06.228421 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 12:43:06.228858 MEM_TYPE=3, freq_sel=18
534 12:43:06.231927 sv_algorithm_assistance_LP4_1600
535 12:43:06.236020 ============ PULL DRAM RESETB DOWN ============
536 12:43:06.243361 ========== PULL DRAM RESETB DOWN end =========
537 12:43:06.246976 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 12:43:06.250512 ===================================
539 12:43:06.253037 LPDDR4 DRAM CONFIGURATION
540 12:43:06.256826 ===================================
541 12:43:06.257359 EX_ROW_EN[0] = 0x0
542 12:43:06.260011 EX_ROW_EN[1] = 0x0
543 12:43:06.260451 LP4Y_EN = 0x0
544 12:43:06.263327 WORK_FSP = 0x0
545 12:43:06.263749 WL = 0x2
546 12:43:06.266949 RL = 0x2
547 12:43:06.267472 BL = 0x2
548 12:43:06.269983 RPST = 0x0
549 12:43:06.270521 RD_PRE = 0x0
550 12:43:06.273186 WR_PRE = 0x1
551 12:43:06.273755 WR_PST = 0x0
552 12:43:06.276137 DBI_WR = 0x0
553 12:43:06.276559 DBI_RD = 0x0
554 12:43:06.279444 OTF = 0x1
555 12:43:06.282927 ===================================
556 12:43:06.286753 ===================================
557 12:43:06.287176 ANA top config
558 12:43:06.289291 ===================================
559 12:43:06.292550 DLL_ASYNC_EN = 0
560 12:43:06.296058 ALL_SLAVE_EN = 1
561 12:43:06.299235 NEW_RANK_MODE = 1
562 12:43:06.299663 DLL_IDLE_MODE = 1
563 12:43:06.303310 LP45_APHY_COMB_EN = 1
564 12:43:06.306142 TX_ODT_DIS = 1
565 12:43:06.309229 NEW_8X_MODE = 1
566 12:43:06.312598 ===================================
567 12:43:06.316571 ===================================
568 12:43:06.319232 data_rate = 1600
569 12:43:06.322673 CKR = 1
570 12:43:06.323107 DQ_P2S_RATIO = 8
571 12:43:06.325994 ===================================
572 12:43:06.329768 CA_P2S_RATIO = 8
573 12:43:06.333089 DQ_CA_OPEN = 0
574 12:43:06.336442 DQ_SEMI_OPEN = 0
575 12:43:06.336883 CA_SEMI_OPEN = 0
576 12:43:06.340471 CA_FULL_RATE = 0
577 12:43:06.343021 DQ_CKDIV4_EN = 1
578 12:43:06.347298 CA_CKDIV4_EN = 1
579 12:43:06.349685 CA_PREDIV_EN = 0
580 12:43:06.352900 PH8_DLY = 0
581 12:43:06.353459 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 12:43:06.356594 DQ_AAMCK_DIV = 4
583 12:43:06.360157 CA_AAMCK_DIV = 4
584 12:43:06.363353 CA_ADMCK_DIV = 4
585 12:43:06.366564 DQ_TRACK_CA_EN = 0
586 12:43:06.370864 CA_PICK = 800
587 12:43:06.373085 CA_MCKIO = 800
588 12:43:06.373572 MCKIO_SEMI = 0
589 12:43:06.376704 PLL_FREQ = 3068
590 12:43:06.380374 DQ_UI_PI_RATIO = 32
591 12:43:06.384448 CA_UI_PI_RATIO = 0
592 12:43:06.387963 ===================================
593 12:43:06.388625 ===================================
594 12:43:06.392007 memory_type:LPDDR4
595 12:43:06.395504 GP_NUM : 10
596 12:43:06.396098 SRAM_EN : 1
597 12:43:06.399266 MD32_EN : 0
598 12:43:06.402717 ===================================
599 12:43:06.403152 [ANA_INIT] >>>>>>>>>>>>>>
600 12:43:06.406914 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 12:43:06.410906 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 12:43:06.413716 ===================================
603 12:43:06.416939 data_rate = 1600,PCW = 0X7600
604 12:43:06.420400 ===================================
605 12:43:06.424084 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 12:43:06.426897 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 12:43:06.433767 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 12:43:06.436570 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 12:43:06.443746 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 12:43:06.446595 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 12:43:06.447023 [ANA_INIT] flow start
612 12:43:06.450248 [ANA_INIT] PLL >>>>>>>>
613 12:43:06.450674 [ANA_INIT] PLL <<<<<<<<
614 12:43:06.453473 [ANA_INIT] MIDPI >>>>>>>>
615 12:43:06.456933 [ANA_INIT] MIDPI <<<<<<<<
616 12:43:06.460461 [ANA_INIT] DLL >>>>>>>>
617 12:43:06.460984 [ANA_INIT] flow end
618 12:43:06.463715 ============ LP4 DIFF to SE enter ============
619 12:43:06.470622 ============ LP4 DIFF to SE exit ============
620 12:43:06.471152 [ANA_INIT] <<<<<<<<<<<<<
621 12:43:06.474145 [Flow] Enable top DCM control >>>>>
622 12:43:06.476914 [Flow] Enable top DCM control <<<<<
623 12:43:06.480412 Enable DLL master slave shuffle
624 12:43:06.487464 ==============================================================
625 12:43:06.487992 Gating Mode config
626 12:43:06.493290 ==============================================================
627 12:43:06.496847 Config description:
628 12:43:06.506933 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 12:43:06.513672 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 12:43:06.517110 SELPH_MODE 0: By rank 1: By Phase
631 12:43:06.523814 ==============================================================
632 12:43:06.527689 GAT_TRACK_EN = 1
633 12:43:06.528318 RX_GATING_MODE = 2
634 12:43:06.530351 RX_GATING_TRACK_MODE = 2
635 12:43:06.533063 SELPH_MODE = 1
636 12:43:06.536999 PICG_EARLY_EN = 1
637 12:43:06.539940 VALID_LAT_VALUE = 1
638 12:43:06.546749 ==============================================================
639 12:43:06.549514 Enter into Gating configuration >>>>
640 12:43:06.553113 Exit from Gating configuration <<<<
641 12:43:06.557514 Enter into DVFS_PRE_config >>>>>
642 12:43:06.567008 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 12:43:06.569553 Exit from DVFS_PRE_config <<<<<
644 12:43:06.572550 Enter into PICG configuration >>>>
645 12:43:06.575889 Exit from PICG configuration <<<<
646 12:43:06.579438 [RX_INPUT] configuration >>>>>
647 12:43:06.582760 [RX_INPUT] configuration <<<<<
648 12:43:06.586345 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 12:43:06.592675 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 12:43:06.598961 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 12:43:06.606145 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 12:43:06.609483 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 12:43:06.615994 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 12:43:06.618963 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 12:43:06.626149 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 12:43:06.628978 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 12:43:06.632380 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 12:43:06.635705 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 12:43:06.642438 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 12:43:06.646172 ===================================
661 12:43:06.646718 LPDDR4 DRAM CONFIGURATION
662 12:43:06.649053 ===================================
663 12:43:06.652664 EX_ROW_EN[0] = 0x0
664 12:43:06.656327 EX_ROW_EN[1] = 0x0
665 12:43:06.656827 LP4Y_EN = 0x0
666 12:43:06.658929 WORK_FSP = 0x0
667 12:43:06.659364 WL = 0x2
668 12:43:06.662953 RL = 0x2
669 12:43:06.663408 BL = 0x2
670 12:43:06.666414 RPST = 0x0
671 12:43:06.666955 RD_PRE = 0x0
672 12:43:06.669146 WR_PRE = 0x1
673 12:43:06.669577 WR_PST = 0x0
674 12:43:06.672446 DBI_WR = 0x0
675 12:43:06.672878 DBI_RD = 0x0
676 12:43:06.676100 OTF = 0x1
677 12:43:06.679334 ===================================
678 12:43:06.682801 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 12:43:06.685668 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 12:43:06.692248 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 12:43:06.695400 ===================================
682 12:43:06.695905 LPDDR4 DRAM CONFIGURATION
683 12:43:06.699426 ===================================
684 12:43:06.702606 EX_ROW_EN[0] = 0x10
685 12:43:06.705449 EX_ROW_EN[1] = 0x0
686 12:43:06.705970 LP4Y_EN = 0x0
687 12:43:06.708773 WORK_FSP = 0x0
688 12:43:06.709199 WL = 0x2
689 12:43:06.712175 RL = 0x2
690 12:43:06.712619 BL = 0x2
691 12:43:06.715681 RPST = 0x0
692 12:43:06.716147 RD_PRE = 0x0
693 12:43:06.718924 WR_PRE = 0x1
694 12:43:06.719431 WR_PST = 0x0
695 12:43:06.721901 DBI_WR = 0x0
696 12:43:06.722354 DBI_RD = 0x0
697 12:43:06.725577 OTF = 0x1
698 12:43:06.728914 ===================================
699 12:43:06.735667 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 12:43:06.739040 nWR fixed to 40
701 12:43:06.739568 [ModeRegInit_LP4] CH0 RK0
702 12:43:06.742384 [ModeRegInit_LP4] CH0 RK1
703 12:43:06.745453 [ModeRegInit_LP4] CH1 RK0
704 12:43:06.748711 [ModeRegInit_LP4] CH1 RK1
705 12:43:06.749139 match AC timing 13
706 12:43:06.755459 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 12:43:06.758957 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 12:43:06.761501 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 12:43:06.769375 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 12:43:06.772246 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 12:43:06.772691 [EMI DOE] emi_dcm 0
712 12:43:06.778194 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 12:43:06.778676 ==
714 12:43:06.781346 Dram Type= 6, Freq= 0, CH_0, rank 0
715 12:43:06.784949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 12:43:06.785502 ==
717 12:43:06.791853 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 12:43:06.798303 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 12:43:06.805531 [CA 0] Center 37 (7~68) winsize 62
720 12:43:06.809203 [CA 1] Center 37 (6~68) winsize 63
721 12:43:06.812547 [CA 2] Center 34 (4~65) winsize 62
722 12:43:06.815406 [CA 3] Center 35 (4~66) winsize 63
723 12:43:06.818916 [CA 4] Center 33 (3~64) winsize 62
724 12:43:06.822573 [CA 5] Center 33 (3~64) winsize 62
725 12:43:06.823003
726 12:43:06.826058 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 12:43:06.826486
728 12:43:06.828803 [CATrainingPosCal] consider 1 rank data
729 12:43:06.831870 u2DelayCellTimex100 = 270/100 ps
730 12:43:06.835714 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 12:43:06.841813 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 12:43:06.845160 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 12:43:06.848709 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
734 12:43:06.852107 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 12:43:06.855603 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 12:43:06.856186
737 12:43:06.858877 CA PerBit enable=1, Macro0, CA PI delay=33
738 12:43:06.859448
739 12:43:06.862861 [CBTSetCACLKResult] CA Dly = 33
740 12:43:06.865971 CS Dly: 5 (0~36)
741 12:43:06.866496 ==
742 12:43:06.868750 Dram Type= 6, Freq= 0, CH_0, rank 1
743 12:43:06.873213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 12:43:06.873665 ==
745 12:43:06.878776 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 12:43:06.881708 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 12:43:06.891872 [CA 0] Center 38 (7~69) winsize 63
748 12:43:06.895582 [CA 1] Center 37 (7~68) winsize 62
749 12:43:06.898580 [CA 2] Center 35 (4~66) winsize 63
750 12:43:06.901841 [CA 3] Center 35 (4~66) winsize 63
751 12:43:06.905087 [CA 4] Center 34 (3~65) winsize 63
752 12:43:06.908549 [CA 5] Center 33 (3~64) winsize 62
753 12:43:06.908972
754 12:43:06.912139 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 12:43:06.912641
756 12:43:06.915387 [CATrainingPosCal] consider 2 rank data
757 12:43:06.918668 u2DelayCellTimex100 = 270/100 ps
758 12:43:06.921731 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 12:43:06.928209 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 12:43:06.931711 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
761 12:43:06.935236 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
762 12:43:06.938615 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 12:43:06.941647 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 12:43:06.942168
765 12:43:06.945100 CA PerBit enable=1, Macro0, CA PI delay=33
766 12:43:06.945533
767 12:43:06.948131 [CBTSetCACLKResult] CA Dly = 33
768 12:43:06.948554 CS Dly: 6 (0~38)
769 12:43:06.951801
770 12:43:06.955244 ----->DramcWriteLeveling(PI) begin...
771 12:43:06.955775 ==
772 12:43:06.958397 Dram Type= 6, Freq= 0, CH_0, rank 0
773 12:43:06.961960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 12:43:06.962396 ==
775 12:43:06.966255 Write leveling (Byte 0): 30 => 30
776 12:43:06.969900 Write leveling (Byte 1): 27 => 27
777 12:43:06.970331 DramcWriteLeveling(PI) end<-----
778 12:43:06.970777
779 12:43:06.971174 ==
780 12:43:06.973578 Dram Type= 6, Freq= 0, CH_0, rank 0
781 12:43:06.980749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 12:43:06.981330 ==
783 12:43:06.981684 [Gating] SW mode calibration
784 12:43:06.987007 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 12:43:06.993491 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 12:43:06.996897 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 12:43:07.003835 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 12:43:07.007467 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
789 12:43:07.010405 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 12:43:07.016663 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 12:43:07.020314 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 12:43:07.023583 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 12:43:07.030131 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 12:43:07.033647 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 12:43:07.036452 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:43:07.043156 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:43:07.046581 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 12:43:07.049506 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 12:43:07.056805 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:43:07.059922 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 12:43:07.063475 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 12:43:07.069618 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:43:07.072852 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 12:43:07.076746 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 12:43:07.079728 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 12:43:07.087602 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 12:43:07.089998 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:43:07.093765 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 12:43:07.099781 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 12:43:07.103119 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 12:43:07.106656 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 12:43:07.113424 0 9 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
813 12:43:07.116260 0 9 12 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
814 12:43:07.120079 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 12:43:07.126052 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 12:43:07.129581 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 12:43:07.133311 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 12:43:07.139514 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 12:43:07.142825 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
820 12:43:07.146995 0 10 8 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
821 12:43:07.152798 0 10 12 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
822 12:43:07.155958 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 12:43:07.159694 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 12:43:07.165977 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 12:43:07.169341 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 12:43:07.173034 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 12:43:07.179949 0 11 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
828 12:43:07.183367 0 11 8 | B1->B0 | 2626 3f3f | 0 0 | (0 0) (0 0)
829 12:43:07.186295 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
830 12:43:07.192889 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 12:43:07.196652 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 12:43:07.201561 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 12:43:07.205862 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 12:43:07.209728 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 12:43:07.212852 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 12:43:07.216228 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 12:43:07.222477 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 12:43:07.225801 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 12:43:07.229428 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 12:43:07.236169 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 12:43:07.239710 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 12:43:07.242423 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 12:43:07.248979 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:43:07.252206 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:43:07.256411 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 12:43:07.262885 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 12:43:07.265729 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 12:43:07.269219 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 12:43:07.276278 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 12:43:07.279219 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 12:43:07.282556 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 12:43:07.288934 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 12:43:07.289467 Total UI for P1: 0, mck2ui 16
854 12:43:07.296161 best dqsien dly found for B0: ( 0, 14, 6)
855 12:43:07.299362 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 12:43:07.302279 Total UI for P1: 0, mck2ui 16
857 12:43:07.305493 best dqsien dly found for B1: ( 0, 14, 8)
858 12:43:07.309113 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
859 12:43:07.312068 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 12:43:07.312496
861 12:43:07.315294 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
862 12:43:07.319110 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 12:43:07.322036 [Gating] SW calibration Done
864 12:43:07.322462 ==
865 12:43:07.325815 Dram Type= 6, Freq= 0, CH_0, rank 0
866 12:43:07.329994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 12:43:07.330508 ==
868 12:43:07.333376 RX Vref Scan: 0
869 12:43:07.333931
870 12:43:07.334421 RX Vref 0 -> 0, step: 1
871 12:43:07.334889
872 12:43:07.336619 RX Delay -130 -> 252, step: 16
873 12:43:07.339746 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
874 12:43:07.346119 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
875 12:43:07.349548 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
876 12:43:07.353320 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
877 12:43:07.356298 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
878 12:43:07.359476 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 12:43:07.366247 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
880 12:43:07.370228 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
881 12:43:07.373494 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 12:43:07.376263 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
883 12:43:07.379532 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
884 12:43:07.386589 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 12:43:07.389609 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 12:43:07.393099 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 12:43:07.396164 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 12:43:07.403020 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 12:43:07.403547 ==
890 12:43:07.406060 Dram Type= 6, Freq= 0, CH_0, rank 0
891 12:43:07.409496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 12:43:07.409990 ==
893 12:43:07.410332 DQS Delay:
894 12:43:07.412611 DQS0 = 0, DQS1 = 0
895 12:43:07.413032 DQM Delay:
896 12:43:07.415707 DQM0 = 92, DQM1 = 76
897 12:43:07.416322 DQ Delay:
898 12:43:07.419605 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
899 12:43:07.423014 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
900 12:43:07.426494 DQ8 =69, DQ9 =53, DQ10 =77, DQ11 =69
901 12:43:07.429198 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
902 12:43:07.429622
903 12:43:07.429960
904 12:43:07.430341 ==
905 12:43:07.432599 Dram Type= 6, Freq= 0, CH_0, rank 0
906 12:43:07.435763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 12:43:07.436219 ==
908 12:43:07.438723
909 12:43:07.439144
910 12:43:07.439482 TX Vref Scan disable
911 12:43:07.442316 == TX Byte 0 ==
912 12:43:07.445997 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
913 12:43:07.449278 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
914 12:43:07.452538 == TX Byte 1 ==
915 12:43:07.455375 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
916 12:43:07.458921 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
917 12:43:07.459347 ==
918 12:43:07.462212 Dram Type= 6, Freq= 0, CH_0, rank 0
919 12:43:07.468776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 12:43:07.469206 ==
921 12:43:07.481281 TX Vref=22, minBit 7, minWin=26, winSum=440
922 12:43:07.484456 TX Vref=24, minBit 5, minWin=26, winSum=441
923 12:43:07.487510 TX Vref=26, minBit 0, minWin=27, winSum=443
924 12:43:07.490965 TX Vref=28, minBit 1, minWin=27, winSum=447
925 12:43:07.494649 TX Vref=30, minBit 1, minWin=27, winSum=450
926 12:43:07.500811 TX Vref=32, minBit 2, minWin=27, winSum=445
927 12:43:07.504394 [TxChooseVref] Worse bit 1, Min win 27, Win sum 450, Final Vref 30
928 12:43:07.504908
929 12:43:07.507678 Final TX Range 1 Vref 30
930 12:43:07.508247
931 12:43:07.508605 ==
932 12:43:07.510954 Dram Type= 6, Freq= 0, CH_0, rank 0
933 12:43:07.514218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 12:43:07.514650 ==
935 12:43:07.517860
936 12:43:07.518277
937 12:43:07.518646 TX Vref Scan disable
938 12:43:07.520726 == TX Byte 0 ==
939 12:43:07.524145 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
940 12:43:07.527672 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
941 12:43:07.531748 == TX Byte 1 ==
942 12:43:07.534452 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
943 12:43:07.540951 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
944 12:43:07.541383
945 12:43:07.541717 [DATLAT]
946 12:43:07.542029 Freq=800, CH0 RK0
947 12:43:07.542328
948 12:43:07.544097 DATLAT Default: 0xa
949 12:43:07.544534 0, 0xFFFF, sum = 0
950 12:43:07.547805 1, 0xFFFF, sum = 0
951 12:43:07.548327 2, 0xFFFF, sum = 0
952 12:43:07.550886 3, 0xFFFF, sum = 0
953 12:43:07.554196 4, 0xFFFF, sum = 0
954 12:43:07.554621 5, 0xFFFF, sum = 0
955 12:43:07.557572 6, 0xFFFF, sum = 0
956 12:43:07.558088 7, 0xFFFF, sum = 0
957 12:43:07.560688 8, 0xFFFF, sum = 0
958 12:43:07.561115 9, 0x0, sum = 1
959 12:43:07.564491 10, 0x0, sum = 2
960 12:43:07.564919 11, 0x0, sum = 3
961 12:43:07.565349 12, 0x0, sum = 4
962 12:43:07.567380 best_step = 10
963 12:43:07.567964
964 12:43:07.568372 ==
965 12:43:07.570775 Dram Type= 6, Freq= 0, CH_0, rank 0
966 12:43:07.574036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 12:43:07.574593 ==
968 12:43:07.577248 RX Vref Scan: 1
969 12:43:07.577812
970 12:43:07.580851 Set Vref Range= 32 -> 127
971 12:43:07.581364
972 12:43:07.581711 RX Vref 32 -> 127, step: 1
973 12:43:07.582028
974 12:43:07.584574 RX Delay -111 -> 252, step: 8
975 12:43:07.585068
976 12:43:07.587731 Set Vref, RX VrefLevel [Byte0]: 32
977 12:43:07.592101 [Byte1]: 32
978 12:43:07.593588
979 12:43:07.594020 Set Vref, RX VrefLevel [Byte0]: 33
980 12:43:07.597054 [Byte1]: 33
981 12:43:07.601452
982 12:43:07.601942 Set Vref, RX VrefLevel [Byte0]: 34
983 12:43:07.604605 [Byte1]: 34
984 12:43:07.609214
985 12:43:07.609730 Set Vref, RX VrefLevel [Byte0]: 35
986 12:43:07.612354 [Byte1]: 35
987 12:43:07.616609
988 12:43:07.617040 Set Vref, RX VrefLevel [Byte0]: 36
989 12:43:07.620408 [Byte1]: 36
990 12:43:07.624631
991 12:43:07.625052 Set Vref, RX VrefLevel [Byte0]: 37
992 12:43:07.628368 [Byte1]: 37
993 12:43:07.631993
994 12:43:07.632453 Set Vref, RX VrefLevel [Byte0]: 38
995 12:43:07.635615 [Byte1]: 38
996 12:43:07.640421
997 12:43:07.640843 Set Vref, RX VrefLevel [Byte0]: 39
998 12:43:07.643506 [Byte1]: 39
999 12:43:07.647596
1000 12:43:07.648018 Set Vref, RX VrefLevel [Byte0]: 40
1001 12:43:07.651296 [Byte1]: 40
1002 12:43:07.655326
1003 12:43:07.655750 Set Vref, RX VrefLevel [Byte0]: 41
1004 12:43:07.658514 [Byte1]: 41
1005 12:43:07.662383
1006 12:43:07.662806 Set Vref, RX VrefLevel [Byte0]: 42
1007 12:43:07.665743 [Byte1]: 42
1008 12:43:07.671469
1009 12:43:07.671894 Set Vref, RX VrefLevel [Byte0]: 43
1010 12:43:07.673653 [Byte1]: 43
1011 12:43:07.678084
1012 12:43:07.678507 Set Vref, RX VrefLevel [Byte0]: 44
1013 12:43:07.681722 [Byte1]: 44
1014 12:43:07.685698
1015 12:43:07.686233 Set Vref, RX VrefLevel [Byte0]: 45
1016 12:43:07.688879 [Byte1]: 45
1017 12:43:07.693577
1018 12:43:07.694007 Set Vref, RX VrefLevel [Byte0]: 46
1019 12:43:07.696381 [Byte1]: 46
1020 12:43:07.700757
1021 12:43:07.701179 Set Vref, RX VrefLevel [Byte0]: 47
1022 12:43:07.704327 [Byte1]: 47
1023 12:43:07.708391
1024 12:43:07.708916 Set Vref, RX VrefLevel [Byte0]: 48
1025 12:43:07.712135 [Byte1]: 48
1026 12:43:07.716550
1027 12:43:07.716967 Set Vref, RX VrefLevel [Byte0]: 49
1028 12:43:07.719813 [Byte1]: 49
1029 12:43:07.724088
1030 12:43:07.724625 Set Vref, RX VrefLevel [Byte0]: 50
1031 12:43:07.727425 [Byte1]: 50
1032 12:43:07.731432
1033 12:43:07.731851 Set Vref, RX VrefLevel [Byte0]: 51
1034 12:43:07.735179 [Byte1]: 51
1035 12:43:07.739054
1036 12:43:07.739573 Set Vref, RX VrefLevel [Byte0]: 52
1037 12:43:07.742915 [Byte1]: 52
1038 12:43:07.746687
1039 12:43:07.747109 Set Vref, RX VrefLevel [Byte0]: 53
1040 12:43:07.750202 [Byte1]: 53
1041 12:43:07.755154
1042 12:43:07.755676 Set Vref, RX VrefLevel [Byte0]: 54
1043 12:43:07.757677 [Byte1]: 54
1044 12:43:07.761749
1045 12:43:07.762184 Set Vref, RX VrefLevel [Byte0]: 55
1046 12:43:07.765699 [Byte1]: 55
1047 12:43:07.770390
1048 12:43:07.770914 Set Vref, RX VrefLevel [Byte0]: 56
1049 12:43:07.773359 [Byte1]: 56
1050 12:43:07.777949
1051 12:43:07.778480 Set Vref, RX VrefLevel [Byte0]: 57
1052 12:43:07.781093 [Byte1]: 57
1053 12:43:07.784699
1054 12:43:07.785114 Set Vref, RX VrefLevel [Byte0]: 58
1055 12:43:07.788815 [Byte1]: 58
1056 12:43:07.793242
1057 12:43:07.793764 Set Vref, RX VrefLevel [Byte0]: 59
1058 12:43:07.796284 [Byte1]: 59
1059 12:43:07.800420
1060 12:43:07.801034 Set Vref, RX VrefLevel [Byte0]: 60
1061 12:43:07.803805 [Byte1]: 60
1062 12:43:07.808082
1063 12:43:07.808637 Set Vref, RX VrefLevel [Byte0]: 61
1064 12:43:07.811340 [Byte1]: 61
1065 12:43:07.815721
1066 12:43:07.816327 Set Vref, RX VrefLevel [Byte0]: 62
1067 12:43:07.819359 [Byte1]: 62
1068 12:43:07.823309
1069 12:43:07.823865 Set Vref, RX VrefLevel [Byte0]: 63
1070 12:43:07.826520 [Byte1]: 63
1071 12:43:07.830949
1072 12:43:07.831525 Set Vref, RX VrefLevel [Byte0]: 64
1073 12:43:07.834489 [Byte1]: 64
1074 12:43:07.838329
1075 12:43:07.838787 Set Vref, RX VrefLevel [Byte0]: 65
1076 12:43:07.841928 [Byte1]: 65
1077 12:43:07.847791
1078 12:43:07.848387 Set Vref, RX VrefLevel [Byte0]: 66
1079 12:43:07.849720 [Byte1]: 66
1080 12:43:07.853985
1081 12:43:07.854443 Set Vref, RX VrefLevel [Byte0]: 67
1082 12:43:07.857176 [Byte1]: 67
1083 12:43:07.861222
1084 12:43:07.861634 Set Vref, RX VrefLevel [Byte0]: 68
1085 12:43:07.865085 [Byte1]: 68
1086 12:43:07.869665
1087 12:43:07.870176 Set Vref, RX VrefLevel [Byte0]: 69
1088 12:43:07.872599 [Byte1]: 69
1089 12:43:07.877109
1090 12:43:07.877630 Set Vref, RX VrefLevel [Byte0]: 70
1091 12:43:07.880624 [Byte1]: 70
1092 12:43:07.884010
1093 12:43:07.884491 Set Vref, RX VrefLevel [Byte0]: 71
1094 12:43:07.887913 [Byte1]: 71
1095 12:43:07.892174
1096 12:43:07.892697 Set Vref, RX VrefLevel [Byte0]: 72
1097 12:43:07.899700 [Byte1]: 72
1098 12:43:07.900267
1099 12:43:07.901897 Set Vref, RX VrefLevel [Byte0]: 73
1100 12:43:07.905409 [Byte1]: 73
1101 12:43:07.905945
1102 12:43:07.908663 Final RX Vref Byte 0 = 56 to rank0
1103 12:43:07.911716 Final RX Vref Byte 1 = 59 to rank0
1104 12:43:07.915807 Final RX Vref Byte 0 = 56 to rank1
1105 12:43:07.918645 Final RX Vref Byte 1 = 59 to rank1==
1106 12:43:07.921481 Dram Type= 6, Freq= 0, CH_0, rank 0
1107 12:43:07.925228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1108 12:43:07.925780 ==
1109 12:43:07.928166 DQS Delay:
1110 12:43:07.928588 DQS0 = 0, DQS1 = 0
1111 12:43:07.931481 DQM Delay:
1112 12:43:07.932016 DQM0 = 87, DQM1 = 76
1113 12:43:07.932419 DQ Delay:
1114 12:43:07.935053 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1115 12:43:07.938460 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1116 12:43:07.942137 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =72
1117 12:43:07.945308 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1118 12:43:07.945831
1119 12:43:07.946169
1120 12:43:07.955006 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d26, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
1121 12:43:07.958580 CH0 RK0: MR19=606, MR18=2D26
1122 12:43:07.961522 CH0_RK0: MR19=0x606, MR18=0x2D26, DQSOSC=398, MR23=63, INC=93, DEC=62
1123 12:43:07.964251
1124 12:43:07.967934 ----->DramcWriteLeveling(PI) begin...
1125 12:43:07.968402 ==
1126 12:43:07.971860 Dram Type= 6, Freq= 0, CH_0, rank 1
1127 12:43:07.975051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1128 12:43:07.975611 ==
1129 12:43:07.977829 Write leveling (Byte 0): 29 => 29
1130 12:43:07.981237 Write leveling (Byte 1): 27 => 27
1131 12:43:07.984419 DramcWriteLeveling(PI) end<-----
1132 12:43:07.984878
1133 12:43:07.985255 ==
1134 12:43:07.988162 Dram Type= 6, Freq= 0, CH_0, rank 1
1135 12:43:07.991494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1136 12:43:07.992062 ==
1137 12:43:07.994985 [Gating] SW mode calibration
1138 12:43:08.001433 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1139 12:43:08.007268 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1140 12:43:08.011483 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1141 12:43:08.014397 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1142 12:43:08.061863 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1143 12:43:08.062476 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1144 12:43:08.063249 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1145 12:43:08.063726 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1146 12:43:08.064273 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1147 12:43:08.064641 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 12:43:08.064975 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 12:43:08.065301 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 12:43:08.065756 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 12:43:08.066095 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 12:43:08.106058 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 12:43:08.107027 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 12:43:08.108360 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 12:43:08.109173 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 12:43:08.109875 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 12:43:08.110616 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1158 12:43:08.111296 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1159 12:43:08.112091 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 12:43:08.112788 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 12:43:08.113503 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 12:43:08.125952 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 12:43:08.126424 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 12:43:08.127165 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 12:43:08.127681 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
1166 12:43:08.129890 0 9 8 | B1->B0 | 2322 3333 | 1 1 | (0 0) (1 1)
1167 12:43:08.130407 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1168 12:43:08.133074 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1169 12:43:08.139470 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1170 12:43:08.143156 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1171 12:43:08.147238 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1172 12:43:08.152751 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1173 12:43:08.156258 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
1174 12:43:08.160168 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
1175 12:43:08.166277 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 12:43:08.169592 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 12:43:08.173051 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 12:43:08.176186 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 12:43:08.183224 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 12:43:08.185972 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 12:43:08.189376 0 11 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1182 12:43:08.195974 0 11 8 | B1->B0 | 3333 4343 | 0 0 | (0 0) (0 0)
1183 12:43:08.199705 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1184 12:43:08.203086 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1185 12:43:08.211394 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1186 12:43:08.213625 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 12:43:08.217265 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 12:43:08.221443 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 12:43:08.224207 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1190 12:43:08.231359 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1191 12:43:08.235798 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1192 12:43:08.238941 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 12:43:08.245215 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 12:43:08.248774 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 12:43:08.251676 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 12:43:08.258666 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 12:43:08.261893 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 12:43:08.265063 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 12:43:08.268541 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 12:43:08.274811 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 12:43:08.278111 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 12:43:08.282486 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 12:43:08.289266 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 12:43:08.292933 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 12:43:08.295339 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1206 12:43:08.302358 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1207 12:43:08.305933 Total UI for P1: 0, mck2ui 16
1208 12:43:08.308196 best dqsien dly found for B0: ( 0, 14, 4)
1209 12:43:08.311940 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 12:43:08.314931 Total UI for P1: 0, mck2ui 16
1211 12:43:08.318667 best dqsien dly found for B1: ( 0, 14, 8)
1212 12:43:08.321442 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1213 12:43:08.324992 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1214 12:43:08.325519
1215 12:43:08.327944 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1216 12:43:08.331149 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1217 12:43:08.334485 [Gating] SW calibration Done
1218 12:43:08.334961 ==
1219 12:43:08.338235 Dram Type= 6, Freq= 0, CH_0, rank 1
1220 12:43:08.341089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1221 12:43:08.344599 ==
1222 12:43:08.345013 RX Vref Scan: 0
1223 12:43:08.345339
1224 12:43:08.348671 RX Vref 0 -> 0, step: 1
1225 12:43:08.349187
1226 12:43:08.351304 RX Delay -130 -> 252, step: 16
1227 12:43:08.355061 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1228 12:43:08.358341 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1229 12:43:08.361187 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1230 12:43:08.364886 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1231 12:43:08.371341 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1232 12:43:08.374574 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1233 12:43:08.377718 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1234 12:43:08.381316 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1235 12:43:08.383970 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1236 12:43:08.391400 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1237 12:43:08.393899 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1238 12:43:08.397821 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1239 12:43:08.400744 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1240 12:43:08.407809 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1241 12:43:08.410737 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1242 12:43:08.414017 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1243 12:43:08.414538 ==
1244 12:43:08.417827 Dram Type= 6, Freq= 0, CH_0, rank 1
1245 12:43:08.421243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1246 12:43:08.421757 ==
1247 12:43:08.424169 DQS Delay:
1248 12:43:08.424581 DQS0 = 0, DQS1 = 0
1249 12:43:08.427056 DQM Delay:
1250 12:43:08.427502 DQM0 = 88, DQM1 = 77
1251 12:43:08.427841 DQ Delay:
1252 12:43:08.430462 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
1253 12:43:08.433611 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1254 12:43:08.437520 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1255 12:43:08.440353 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1256 12:43:08.440781
1257 12:43:08.441116
1258 12:43:08.443480 ==
1259 12:43:08.447362 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 12:43:08.450517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 12:43:08.451068 ==
1262 12:43:08.451412
1263 12:43:08.451725
1264 12:43:08.453461 TX Vref Scan disable
1265 12:43:08.453883 == TX Byte 0 ==
1266 12:43:08.456752 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1267 12:43:08.463711 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1268 12:43:08.464277 == TX Byte 1 ==
1269 12:43:08.470299 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1270 12:43:08.473891 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1271 12:43:08.474422 ==
1272 12:43:08.476723 Dram Type= 6, Freq= 0, CH_0, rank 1
1273 12:43:08.480061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1274 12:43:08.480594 ==
1275 12:43:08.493575 TX Vref=22, minBit 0, minWin=27, winSum=440
1276 12:43:08.496847 TX Vref=24, minBit 0, minWin=27, winSum=445
1277 12:43:08.500681 TX Vref=26, minBit 3, minWin=27, winSum=448
1278 12:43:08.503994 TX Vref=28, minBit 1, minWin=27, winSum=447
1279 12:43:08.507265 TX Vref=30, minBit 3, minWin=27, winSum=448
1280 12:43:08.513789 TX Vref=32, minBit 7, minWin=27, winSum=451
1281 12:43:08.516986 [TxChooseVref] Worse bit 7, Min win 27, Win sum 451, Final Vref 32
1282 12:43:08.517515
1283 12:43:08.519937 Final TX Range 1 Vref 32
1284 12:43:08.520506
1285 12:43:08.520843 ==
1286 12:43:08.523894 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 12:43:08.526674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 12:43:08.529449 ==
1289 12:43:08.529867
1290 12:43:08.530200
1291 12:43:08.530509 TX Vref Scan disable
1292 12:43:08.533012 == TX Byte 0 ==
1293 12:43:08.536686 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1294 12:43:08.543482 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1295 12:43:08.543896 == TX Byte 1 ==
1296 12:43:08.546403 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1297 12:43:08.552859 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1298 12:43:08.553283
1299 12:43:08.553607 [DATLAT]
1300 12:43:08.553908 Freq=800, CH0 RK1
1301 12:43:08.554201
1302 12:43:08.556713 DATLAT Default: 0xa
1303 12:43:08.557122 0, 0xFFFF, sum = 0
1304 12:43:08.559745 1, 0xFFFF, sum = 0
1305 12:43:08.560187 2, 0xFFFF, sum = 0
1306 12:43:08.562850 3, 0xFFFF, sum = 0
1307 12:43:08.566764 4, 0xFFFF, sum = 0
1308 12:43:08.567278 5, 0xFFFF, sum = 0
1309 12:43:08.570122 6, 0xFFFF, sum = 0
1310 12:43:08.570689 7, 0xFFFF, sum = 0
1311 12:43:08.573630 8, 0xFFFF, sum = 0
1312 12:43:08.574041 9, 0x0, sum = 1
1313 12:43:08.576561 10, 0x0, sum = 2
1314 12:43:08.576972 11, 0x0, sum = 3
1315 12:43:08.577385 12, 0x0, sum = 4
1316 12:43:08.580365 best_step = 10
1317 12:43:08.580771
1318 12:43:08.581087 ==
1319 12:43:08.582689 Dram Type= 6, Freq= 0, CH_0, rank 1
1320 12:43:08.586583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1321 12:43:08.586991 ==
1322 12:43:08.589567 RX Vref Scan: 0
1323 12:43:08.589979
1324 12:43:08.590300 RX Vref 0 -> 0, step: 1
1325 12:43:08.593541
1326 12:43:08.594040 RX Delay -95 -> 252, step: 8
1327 12:43:08.599985 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1328 12:43:08.603514 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1329 12:43:08.607071 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1330 12:43:08.609982 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1331 12:43:08.613059 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1332 12:43:08.620600 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1333 12:43:08.623291 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1334 12:43:08.626744 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1335 12:43:08.629871 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1336 12:43:08.633131 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1337 12:43:08.639495 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1338 12:43:08.643114 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1339 12:43:08.646407 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1340 12:43:08.649547 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1341 12:43:08.656190 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1342 12:43:08.660185 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1343 12:43:08.660697 ==
1344 12:43:08.663716 Dram Type= 6, Freq= 0, CH_0, rank 1
1345 12:43:08.665945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1346 12:43:08.666361 ==
1347 12:43:08.669115 DQS Delay:
1348 12:43:08.669516 DQS0 = 0, DQS1 = 0
1349 12:43:08.669834 DQM Delay:
1350 12:43:08.673122 DQM0 = 86, DQM1 = 77
1351 12:43:08.673525 DQ Delay:
1352 12:43:08.675966 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1353 12:43:08.679670 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1354 12:43:08.682547 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1355 12:43:08.686982 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =84
1356 12:43:08.687491
1357 12:43:08.687815
1358 12:43:08.696267 [DQSOSCAuto] RK1, (LSB)MR18= 0x2520, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
1359 12:43:08.699066 CH0 RK1: MR19=606, MR18=2520
1360 12:43:08.702673 CH0_RK1: MR19=0x606, MR18=0x2520, DQSOSC=400, MR23=63, INC=92, DEC=61
1361 12:43:08.706029 [RxdqsGatingPostProcess] freq 800
1362 12:43:08.712225 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1363 12:43:08.715677 Pre-setting of DQS Precalculation
1364 12:43:08.718994 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1365 12:43:08.719516 ==
1366 12:43:08.722217 Dram Type= 6, Freq= 0, CH_1, rank 0
1367 12:43:08.728738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1368 12:43:08.729376 ==
1369 12:43:08.731906 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1370 12:43:08.738912 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1371 12:43:08.748316 [CA 0] Center 36 (6~67) winsize 62
1372 12:43:08.752794 [CA 1] Center 37 (6~68) winsize 63
1373 12:43:08.754892 [CA 2] Center 35 (5~65) winsize 61
1374 12:43:08.759742 [CA 3] Center 34 (4~65) winsize 62
1375 12:43:08.763132 [CA 4] Center 34 (4~65) winsize 62
1376 12:43:08.764837 [CA 5] Center 33 (3~64) winsize 62
1377 12:43:08.765263
1378 12:43:08.768166 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1379 12:43:08.768593
1380 12:43:08.771886 [CATrainingPosCal] consider 1 rank data
1381 12:43:08.774807 u2DelayCellTimex100 = 270/100 ps
1382 12:43:08.778277 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1383 12:43:08.781864 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1384 12:43:08.788062 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1385 12:43:08.792108 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1386 12:43:08.795144 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1387 12:43:08.798552 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1388 12:43:08.799072
1389 12:43:08.801834 CA PerBit enable=1, Macro0, CA PI delay=33
1390 12:43:08.802273
1391 12:43:08.805283 [CBTSetCACLKResult] CA Dly = 33
1392 12:43:08.805803 CS Dly: 4 (0~35)
1393 12:43:08.808203 ==
1394 12:43:08.811476 Dram Type= 6, Freq= 0, CH_1, rank 1
1395 12:43:08.815601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1396 12:43:08.816175 ==
1397 12:43:08.818361 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1398 12:43:08.824767 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1399 12:43:08.834535 [CA 0] Center 36 (6~67) winsize 62
1400 12:43:08.837942 [CA 1] Center 36 (6~67) winsize 62
1401 12:43:08.841497 [CA 2] Center 34 (4~65) winsize 62
1402 12:43:08.844757 [CA 3] Center 34 (3~65) winsize 63
1403 12:43:08.848714 [CA 4] Center 34 (3~65) winsize 63
1404 12:43:08.851026 [CA 5] Center 33 (3~64) winsize 62
1405 12:43:08.851580
1406 12:43:08.854856 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1407 12:43:08.855321
1408 12:43:08.857745 [CATrainingPosCal] consider 2 rank data
1409 12:43:08.862680 u2DelayCellTimex100 = 270/100 ps
1410 12:43:08.864210 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1411 12:43:08.871493 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1412 12:43:08.875699 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1413 12:43:08.878435 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1414 12:43:08.882060 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1415 12:43:08.882478 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1416 12:43:08.886329
1417 12:43:08.889814 CA PerBit enable=1, Macro0, CA PI delay=33
1418 12:43:08.890232
1419 12:43:08.890564 [CBTSetCACLKResult] CA Dly = 33
1420 12:43:08.893674 CS Dly: 5 (0~37)
1421 12:43:08.894202
1422 12:43:08.898608 ----->DramcWriteLeveling(PI) begin...
1423 12:43:08.899144 ==
1424 12:43:08.900753 Dram Type= 6, Freq= 0, CH_1, rank 0
1425 12:43:08.904539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1426 12:43:08.904978 ==
1427 12:43:08.907984 Write leveling (Byte 0): 24 => 24
1428 12:43:08.911343 Write leveling (Byte 1): 29 => 29
1429 12:43:08.914154 DramcWriteLeveling(PI) end<-----
1430 12:43:08.914671
1431 12:43:08.915005 ==
1432 12:43:08.918274 Dram Type= 6, Freq= 0, CH_1, rank 0
1433 12:43:08.921538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1434 12:43:08.922064 ==
1435 12:43:08.924360 [Gating] SW mode calibration
1436 12:43:08.931175 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1437 12:43:08.937550 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1438 12:43:08.940828 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1439 12:43:08.944219 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1440 12:43:08.951585 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1441 12:43:08.954063 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1442 12:43:08.957457 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 12:43:08.964280 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 12:43:08.967981 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 12:43:08.971245 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 12:43:08.977259 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 12:43:08.980728 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 12:43:08.983801 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 12:43:08.990588 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 12:43:08.993575 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 12:43:08.997062 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 12:43:09.004133 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 12:43:09.007662 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 12:43:09.010652 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1455 12:43:09.013681 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1456 12:43:09.020157 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1457 12:43:09.024190 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 12:43:09.026997 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 12:43:09.033303 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 12:43:09.036806 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 12:43:09.040108 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 12:43:09.047086 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 12:43:09.049782 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 12:43:09.054077 0 9 8 | B1->B0 | 2d2d 3131 | 0 1 | (0 0) (1 1)
1465 12:43:09.060113 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1466 12:43:09.063093 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1467 12:43:09.066745 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1468 12:43:09.072980 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1469 12:43:09.076259 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1470 12:43:09.079679 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1471 12:43:09.086308 0 10 4 | B1->B0 | 3030 2f2f | 1 1 | (1 1) (1 0)
1472 12:43:09.089733 0 10 8 | B1->B0 | 2929 2424 | 1 0 | (1 0) (1 0)
1473 12:43:09.092847 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 12:43:09.100193 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 12:43:09.102815 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 12:43:09.107560 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 12:43:09.113808 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 12:43:09.115985 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 12:43:09.119624 0 11 4 | B1->B0 | 2828 2d2d | 0 0 | (0 0) (0 0)
1480 12:43:09.126604 0 11 8 | B1->B0 | 3939 4141 | 0 0 | (0 0) (0 0)
1481 12:43:09.130042 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1482 12:43:09.133794 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1483 12:43:09.139750 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1484 12:43:09.142992 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1485 12:43:09.146779 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1486 12:43:09.152738 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1487 12:43:09.156249 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1488 12:43:09.159790 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1489 12:43:09.166078 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1490 12:43:09.169412 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1491 12:43:09.172659 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1492 12:43:09.179181 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1493 12:43:09.182327 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 12:43:09.185908 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 12:43:09.192563 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 12:43:09.195637 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 12:43:09.198816 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 12:43:09.205318 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 12:43:09.208931 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 12:43:09.212130 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 12:43:09.218997 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 12:43:09.221874 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 12:43:09.225206 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1504 12:43:09.228876 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 12:43:09.231901 Total UI for P1: 0, mck2ui 16
1506 12:43:09.235631 best dqsien dly found for B0: ( 0, 14, 4)
1507 12:43:09.238759 Total UI for P1: 0, mck2ui 16
1508 12:43:09.241652 best dqsien dly found for B1: ( 0, 14, 4)
1509 12:43:09.245411 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1510 12:43:09.251897 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1511 12:43:09.252339
1512 12:43:09.255644 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1513 12:43:09.258916 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1514 12:43:09.262083 [Gating] SW calibration Done
1515 12:43:09.262495 ==
1516 12:43:09.264878 Dram Type= 6, Freq= 0, CH_1, rank 0
1517 12:43:09.268982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1518 12:43:09.269405 ==
1519 12:43:09.269754 RX Vref Scan: 0
1520 12:43:09.271469
1521 12:43:09.271879 RX Vref 0 -> 0, step: 1
1522 12:43:09.272243
1523 12:43:09.274871 RX Delay -130 -> 252, step: 16
1524 12:43:09.278169 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1525 12:43:09.284921 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1526 12:43:09.288168 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1527 12:43:09.291537 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1528 12:43:09.294453 iDelay=222, Bit 4, Center 77 (-34 ~ 189) 224
1529 12:43:09.298551 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1530 12:43:09.304498 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1531 12:43:09.308360 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1532 12:43:09.311599 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1533 12:43:09.314907 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1534 12:43:09.317884 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1535 12:43:09.325133 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1536 12:43:09.327680 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1537 12:43:09.331158 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1538 12:43:09.334674 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1539 12:43:09.337493 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1540 12:43:09.341073 ==
1541 12:43:09.344708 Dram Type= 6, Freq= 0, CH_1, rank 0
1542 12:43:09.347782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1543 12:43:09.348363 ==
1544 12:43:09.348717 DQS Delay:
1545 12:43:09.351248 DQS0 = 0, DQS1 = 0
1546 12:43:09.351650 DQM Delay:
1547 12:43:09.354315 DQM0 = 86, DQM1 = 79
1548 12:43:09.354859 DQ Delay:
1549 12:43:09.357782 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1550 12:43:09.361293 DQ4 =77, DQ5 =101, DQ6 =101, DQ7 =85
1551 12:43:09.364003 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1552 12:43:09.368138 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1553 12:43:09.368695
1554 12:43:09.369188
1555 12:43:09.369625 ==
1556 12:43:09.371150 Dram Type= 6, Freq= 0, CH_1, rank 0
1557 12:43:09.373933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1558 12:43:09.374384 ==
1559 12:43:09.374879
1560 12:43:09.377494
1561 12:43:09.378064 TX Vref Scan disable
1562 12:43:09.380521 == TX Byte 0 ==
1563 12:43:09.384101 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1564 12:43:09.387057 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1565 12:43:09.390797 == TX Byte 1 ==
1566 12:43:09.394044 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1567 12:43:09.398047 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1568 12:43:09.398443 ==
1569 12:43:09.400457 Dram Type= 6, Freq= 0, CH_1, rank 0
1570 12:43:09.407018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1571 12:43:09.407428 ==
1572 12:43:09.419349 TX Vref=22, minBit 2, minWin=26, winSum=438
1573 12:43:09.423338 TX Vref=24, minBit 0, minWin=27, winSum=443
1574 12:43:09.425992 TX Vref=26, minBit 1, minWin=27, winSum=448
1575 12:43:09.429990 TX Vref=28, minBit 0, minWin=27, winSum=453
1576 12:43:09.432738 TX Vref=30, minBit 2, minWin=27, winSum=454
1577 12:43:09.439516 TX Vref=32, minBit 0, minWin=27, winSum=450
1578 12:43:09.443196 [TxChooseVref] Worse bit 2, Min win 27, Win sum 454, Final Vref 30
1579 12:43:09.443622
1580 12:43:09.446045 Final TX Range 1 Vref 30
1581 12:43:09.446470
1582 12:43:09.446799 ==
1583 12:43:09.449711 Dram Type= 6, Freq= 0, CH_1, rank 0
1584 12:43:09.454152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1585 12:43:09.454613 ==
1586 12:43:09.454982
1587 12:43:09.455303
1588 12:43:09.456910 TX Vref Scan disable
1589 12:43:09.460286 == TX Byte 0 ==
1590 12:43:09.463185 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1591 12:43:09.466565 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1592 12:43:09.470265 == TX Byte 1 ==
1593 12:43:09.473933 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1594 12:43:09.476786 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1595 12:43:09.477210
1596 12:43:09.479834 [DATLAT]
1597 12:43:09.480303 Freq=800, CH1 RK0
1598 12:43:09.480641
1599 12:43:09.483482 DATLAT Default: 0xa
1600 12:43:09.483902 0, 0xFFFF, sum = 0
1601 12:43:09.486720 1, 0xFFFF, sum = 0
1602 12:43:09.487146 2, 0xFFFF, sum = 0
1603 12:43:09.489921 3, 0xFFFF, sum = 0
1604 12:43:09.490397 4, 0xFFFF, sum = 0
1605 12:43:09.493462 5, 0xFFFF, sum = 0
1606 12:43:09.493891 6, 0xFFFF, sum = 0
1607 12:43:09.496459 7, 0xFFFF, sum = 0
1608 12:43:09.496887 8, 0xFFFF, sum = 0
1609 12:43:09.500126 9, 0x0, sum = 1
1610 12:43:09.500550 10, 0x0, sum = 2
1611 12:43:09.503305 11, 0x0, sum = 3
1612 12:43:09.503734 12, 0x0, sum = 4
1613 12:43:09.506400 best_step = 10
1614 12:43:09.506868
1615 12:43:09.507207 ==
1616 12:43:09.509981 Dram Type= 6, Freq= 0, CH_1, rank 0
1617 12:43:09.513033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1618 12:43:09.513458 ==
1619 12:43:09.516458 RX Vref Scan: 1
1620 12:43:09.516922
1621 12:43:09.517328 Set Vref Range= 32 -> 127
1622 12:43:09.517701
1623 12:43:09.519774 RX Vref 32 -> 127, step: 1
1624 12:43:09.520291
1625 12:43:09.522890 RX Delay -95 -> 252, step: 8
1626 12:43:09.523310
1627 12:43:09.526246 Set Vref, RX VrefLevel [Byte0]: 32
1628 12:43:09.529677 [Byte1]: 32
1629 12:43:09.530100
1630 12:43:09.532860 Set Vref, RX VrefLevel [Byte0]: 33
1631 12:43:09.536352 [Byte1]: 33
1632 12:43:09.539901
1633 12:43:09.540365 Set Vref, RX VrefLevel [Byte0]: 34
1634 12:43:09.542857 [Byte1]: 34
1635 12:43:09.547256
1636 12:43:09.547675 Set Vref, RX VrefLevel [Byte0]: 35
1637 12:43:09.551074 [Byte1]: 35
1638 12:43:09.555475
1639 12:43:09.555897 Set Vref, RX VrefLevel [Byte0]: 36
1640 12:43:09.558334 [Byte1]: 36
1641 12:43:09.562619
1642 12:43:09.563041 Set Vref, RX VrefLevel [Byte0]: 37
1643 12:43:09.566616 [Byte1]: 37
1644 12:43:09.570073
1645 12:43:09.570642 Set Vref, RX VrefLevel [Byte0]: 38
1646 12:43:09.573673 [Byte1]: 38
1647 12:43:09.577699
1648 12:43:09.578118 Set Vref, RX VrefLevel [Byte0]: 39
1649 12:43:09.581262 [Byte1]: 39
1650 12:43:09.586160
1651 12:43:09.586581 Set Vref, RX VrefLevel [Byte0]: 40
1652 12:43:09.588403 [Byte1]: 40
1653 12:43:09.593257
1654 12:43:09.593678 Set Vref, RX VrefLevel [Byte0]: 41
1655 12:43:09.596436 [Byte1]: 41
1656 12:43:09.600844
1657 12:43:09.601262 Set Vref, RX VrefLevel [Byte0]: 42
1658 12:43:09.604019 [Byte1]: 42
1659 12:43:09.607995
1660 12:43:09.608624 Set Vref, RX VrefLevel [Byte0]: 43
1661 12:43:09.611578 [Byte1]: 43
1662 12:43:09.615961
1663 12:43:09.616469 Set Vref, RX VrefLevel [Byte0]: 44
1664 12:43:09.619191 [Byte1]: 44
1665 12:43:09.623587
1666 12:43:09.624002 Set Vref, RX VrefLevel [Byte0]: 45
1667 12:43:09.626657 [Byte1]: 45
1668 12:43:09.631023
1669 12:43:09.631421 Set Vref, RX VrefLevel [Byte0]: 46
1670 12:43:09.634079 [Byte1]: 46
1671 12:43:09.638409
1672 12:43:09.638820 Set Vref, RX VrefLevel [Byte0]: 47
1673 12:43:09.641994 [Byte1]: 47
1674 12:43:09.645938
1675 12:43:09.646348 Set Vref, RX VrefLevel [Byte0]: 48
1676 12:43:09.649332 [Byte1]: 48
1677 12:43:09.653558
1678 12:43:09.653970 Set Vref, RX VrefLevel [Byte0]: 49
1679 12:43:09.656757 [Byte1]: 49
1680 12:43:09.662195
1681 12:43:09.662716 Set Vref, RX VrefLevel [Byte0]: 50
1682 12:43:09.664828 [Byte1]: 50
1683 12:43:09.669359
1684 12:43:09.669773 Set Vref, RX VrefLevel [Byte0]: 51
1685 12:43:09.672086 [Byte1]: 51
1686 12:43:09.676394
1687 12:43:09.676846 Set Vref, RX VrefLevel [Byte0]: 52
1688 12:43:09.679907 [Byte1]: 52
1689 12:43:09.684231
1690 12:43:09.684641 Set Vref, RX VrefLevel [Byte0]: 53
1691 12:43:09.687296 [Byte1]: 53
1692 12:43:09.692121
1693 12:43:09.692534 Set Vref, RX VrefLevel [Byte0]: 54
1694 12:43:09.695223 [Byte1]: 54
1695 12:43:09.699209
1696 12:43:09.699622 Set Vref, RX VrefLevel [Byte0]: 55
1697 12:43:09.703082 [Byte1]: 55
1698 12:43:09.706983
1699 12:43:09.707395 Set Vref, RX VrefLevel [Byte0]: 56
1700 12:43:09.710153 [Byte1]: 56
1701 12:43:09.714494
1702 12:43:09.714905 Set Vref, RX VrefLevel [Byte0]: 57
1703 12:43:09.718248 [Byte1]: 57
1704 12:43:09.722343
1705 12:43:09.722755 Set Vref, RX VrefLevel [Byte0]: 58
1706 12:43:09.725571 [Byte1]: 58
1707 12:43:09.729881
1708 12:43:09.730291 Set Vref, RX VrefLevel [Byte0]: 59
1709 12:43:09.732936 [Byte1]: 59
1710 12:43:09.737580
1711 12:43:09.738021 Set Vref, RX VrefLevel [Byte0]: 60
1712 12:43:09.740853 [Byte1]: 60
1713 12:43:09.744821
1714 12:43:09.745234 Set Vref, RX VrefLevel [Byte0]: 61
1715 12:43:09.748213 [Byte1]: 61
1716 12:43:09.753032
1717 12:43:09.753441 Set Vref, RX VrefLevel [Byte0]: 62
1718 12:43:09.756140 [Byte1]: 62
1719 12:43:09.760154
1720 12:43:09.760563 Set Vref, RX VrefLevel [Byte0]: 63
1721 12:43:09.763549 [Byte1]: 63
1722 12:43:09.767555
1723 12:43:09.768154 Set Vref, RX VrefLevel [Byte0]: 64
1724 12:43:09.770857 [Byte1]: 64
1725 12:43:09.775442
1726 12:43:09.775854 Set Vref, RX VrefLevel [Byte0]: 65
1727 12:43:09.779593 [Byte1]: 65
1728 12:43:09.783399
1729 12:43:09.783809 Set Vref, RX VrefLevel [Byte0]: 66
1730 12:43:09.786574 [Byte1]: 66
1731 12:43:09.790725
1732 12:43:09.791156 Set Vref, RX VrefLevel [Byte0]: 67
1733 12:43:09.793892 [Byte1]: 67
1734 12:43:09.798330
1735 12:43:09.798816 Set Vref, RX VrefLevel [Byte0]: 68
1736 12:43:09.804753 [Byte1]: 68
1737 12:43:09.805174
1738 12:43:09.808300 Set Vref, RX VrefLevel [Byte0]: 69
1739 12:43:09.811124 [Byte1]: 69
1740 12:43:09.811542
1741 12:43:09.814635 Set Vref, RX VrefLevel [Byte0]: 70
1742 12:43:09.817719 [Byte1]: 70
1743 12:43:09.821268
1744 12:43:09.821685 Set Vref, RX VrefLevel [Byte0]: 71
1745 12:43:09.824004 [Byte1]: 71
1746 12:43:09.828310
1747 12:43:09.829063 Set Vref, RX VrefLevel [Byte0]: 72
1748 12:43:09.832139 [Byte1]: 72
1749 12:43:09.835795
1750 12:43:09.836344 Set Vref, RX VrefLevel [Byte0]: 73
1751 12:43:09.839282 [Byte1]: 73
1752 12:43:09.844638
1753 12:43:09.844941 Set Vref, RX VrefLevel [Byte0]: 74
1754 12:43:09.846758 [Byte1]: 74
1755 12:43:09.851124
1756 12:43:09.851436 Final RX Vref Byte 0 = 56 to rank0
1757 12:43:09.854556 Final RX Vref Byte 1 = 54 to rank0
1758 12:43:09.857513 Final RX Vref Byte 0 = 56 to rank1
1759 12:43:09.861294 Final RX Vref Byte 1 = 54 to rank1==
1760 12:43:09.865013 Dram Type= 6, Freq= 0, CH_1, rank 0
1761 12:43:09.871240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1762 12:43:09.871498 ==
1763 12:43:09.871722 DQS Delay:
1764 12:43:09.871933 DQS0 = 0, DQS1 = 0
1765 12:43:09.874485 DQM Delay:
1766 12:43:09.874789 DQM0 = 85, DQM1 = 80
1767 12:43:09.877492 DQ Delay:
1768 12:43:09.881467 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1769 12:43:09.883972 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =80
1770 12:43:09.887332 DQ8 =64, DQ9 =72, DQ10 =80, DQ11 =76
1771 12:43:09.890835 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1772 12:43:09.891042
1773 12:43:09.891226
1774 12:43:09.897413 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c2f, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
1775 12:43:09.900819 CH1 RK0: MR19=606, MR18=1C2F
1776 12:43:09.907502 CH1_RK0: MR19=0x606, MR18=0x1C2F, DQSOSC=397, MR23=63, INC=93, DEC=62
1777 12:43:09.907587
1778 12:43:09.910818 ----->DramcWriteLeveling(PI) begin...
1779 12:43:09.910902 ==
1780 12:43:09.913944 Dram Type= 6, Freq= 0, CH_1, rank 1
1781 12:43:09.917434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1782 12:43:09.917518 ==
1783 12:43:09.920530 Write leveling (Byte 0): 26 => 26
1784 12:43:09.923978 Write leveling (Byte 1): 27 => 27
1785 12:43:09.927321 DramcWriteLeveling(PI) end<-----
1786 12:43:09.927403
1787 12:43:09.927486 ==
1788 12:43:09.930460 Dram Type= 6, Freq= 0, CH_1, rank 1
1789 12:43:09.934094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1790 12:43:09.934178 ==
1791 12:43:09.937409 [Gating] SW mode calibration
1792 12:43:09.943834 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1793 12:43:09.950338 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1794 12:43:09.953492 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1795 12:43:09.956997 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1796 12:43:09.963788 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1797 12:43:09.967013 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1798 12:43:09.970385 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1799 12:43:09.977313 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1800 12:43:09.980385 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 12:43:09.984027 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 12:43:09.990271 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 12:43:09.993488 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 12:43:09.996733 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 12:43:10.003268 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 12:43:10.007235 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 12:43:10.010169 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 12:43:10.017144 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 12:43:10.020479 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 12:43:10.023485 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1811 12:43:10.029912 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1812 12:43:10.033355 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1813 12:43:10.036800 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 12:43:10.043554 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 12:43:10.046547 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 12:43:10.050144 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 12:43:10.056829 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 12:43:10.059680 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 12:43:10.062997 0 9 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1820 12:43:10.070454 0 9 8 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
1821 12:43:10.073833 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1822 12:43:10.076385 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1823 12:43:10.082825 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1824 12:43:10.086207 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1825 12:43:10.090032 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1826 12:43:10.096702 0 10 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
1827 12:43:10.100001 0 10 4 | B1->B0 | 3333 3030 | 1 0 | (1 0) (1 1)
1828 12:43:10.103262 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1829 12:43:10.109920 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 12:43:10.112937 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 12:43:10.116316 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 12:43:10.122986 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 12:43:10.126326 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 12:43:10.129949 0 11 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1835 12:43:10.132945 0 11 4 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 0)
1836 12:43:10.139945 0 11 8 | B1->B0 | 3939 4646 | 0 0 | (1 1) (0 0)
1837 12:43:10.142921 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1838 12:43:10.146560 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1839 12:43:10.153311 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1840 12:43:10.156686 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1841 12:43:10.159694 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1842 12:43:10.165981 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1843 12:43:10.169582 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1844 12:43:10.172698 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1845 12:43:10.179560 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1846 12:43:10.182538 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1847 12:43:10.185910 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1848 12:43:10.192682 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1849 12:43:10.196343 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 12:43:10.199123 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 12:43:10.206240 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 12:43:10.209065 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 12:43:10.212337 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 12:43:10.219293 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 12:43:10.222564 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 12:43:10.226447 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 12:43:10.232844 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 12:43:10.235869 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1859 12:43:10.239403 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1860 12:43:10.245439 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 12:43:10.245521 Total UI for P1: 0, mck2ui 16
1862 12:43:10.252371 best dqsien dly found for B0: ( 0, 14, 2)
1863 12:43:10.252453 Total UI for P1: 0, mck2ui 16
1864 12:43:10.255957 best dqsien dly found for B1: ( 0, 14, 6)
1865 12:43:10.262344 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1866 12:43:10.265334 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1867 12:43:10.265415
1868 12:43:10.268761 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1869 12:43:10.271891 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1870 12:43:10.276251 [Gating] SW calibration Done
1871 12:43:10.276332 ==
1872 12:43:10.278914 Dram Type= 6, Freq= 0, CH_1, rank 1
1873 12:43:10.282980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1874 12:43:10.283062 ==
1875 12:43:10.285466 RX Vref Scan: 0
1876 12:43:10.285547
1877 12:43:10.285611 RX Vref 0 -> 0, step: 1
1878 12:43:10.285671
1879 12:43:10.288659 RX Delay -130 -> 252, step: 16
1880 12:43:10.292145 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1881 12:43:10.299264 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1882 12:43:10.302661 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1883 12:43:10.305468 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1884 12:43:10.308630 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1885 12:43:10.311970 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1886 12:43:10.318559 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1887 12:43:10.321955 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1888 12:43:10.325361 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1889 12:43:10.328257 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1890 12:43:10.331858 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1891 12:43:10.338605 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1892 12:43:10.341788 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1893 12:43:10.344848 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1894 12:43:10.348644 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1895 12:43:10.351758 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1896 12:43:10.355079 ==
1897 12:43:10.358230 Dram Type= 6, Freq= 0, CH_1, rank 1
1898 12:43:10.361421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1899 12:43:10.361504 ==
1900 12:43:10.361569 DQS Delay:
1901 12:43:10.364865 DQS0 = 0, DQS1 = 0
1902 12:43:10.364947 DQM Delay:
1903 12:43:10.367916 DQM0 = 85, DQM1 = 86
1904 12:43:10.367998 DQ Delay:
1905 12:43:10.371996 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1906 12:43:10.375337 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1907 12:43:10.378686 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1908 12:43:10.381496 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1909 12:43:10.381578
1910 12:43:10.381643
1911 12:43:10.381703 ==
1912 12:43:10.384524 Dram Type= 6, Freq= 0, CH_1, rank 1
1913 12:43:10.387821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1914 12:43:10.387904 ==
1915 12:43:10.387985
1916 12:43:10.388069
1917 12:43:10.391554 TX Vref Scan disable
1918 12:43:10.394762 == TX Byte 0 ==
1919 12:43:10.398372 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1920 12:43:10.401557 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1921 12:43:10.404982 == TX Byte 1 ==
1922 12:43:10.408191 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1923 12:43:10.411355 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1924 12:43:10.411437 ==
1925 12:43:10.414742 Dram Type= 6, Freq= 0, CH_1, rank 1
1926 12:43:10.421312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1927 12:43:10.421395 ==
1928 12:43:10.433189 TX Vref=22, minBit 0, minWin=27, winSum=447
1929 12:43:10.436183 TX Vref=24, minBit 1, minWin=27, winSum=446
1930 12:43:10.439821 TX Vref=26, minBit 1, minWin=27, winSum=452
1931 12:43:10.443666 TX Vref=28, minBit 5, minWin=27, winSum=453
1932 12:43:10.446478 TX Vref=30, minBit 5, minWin=27, winSum=455
1933 12:43:10.449311 TX Vref=32, minBit 0, minWin=28, winSum=457
1934 12:43:10.455962 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 32
1935 12:43:10.456080
1936 12:43:10.459409 Final TX Range 1 Vref 32
1937 12:43:10.459491
1938 12:43:10.459556 ==
1939 12:43:10.462639 Dram Type= 6, Freq= 0, CH_1, rank 1
1940 12:43:10.465681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1941 12:43:10.465764 ==
1942 12:43:10.469205
1943 12:43:10.469286
1944 12:43:10.469350 TX Vref Scan disable
1945 12:43:10.472865 == TX Byte 0 ==
1946 12:43:10.476230 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1947 12:43:10.482711 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1948 12:43:10.482826 == TX Byte 1 ==
1949 12:43:10.485780 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1950 12:43:10.492486 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1951 12:43:10.492594
1952 12:43:10.492686 [DATLAT]
1953 12:43:10.492773 Freq=800, CH1 RK1
1954 12:43:10.492869
1955 12:43:10.496157 DATLAT Default: 0xa
1956 12:43:10.496262 0, 0xFFFF, sum = 0
1957 12:43:10.499212 1, 0xFFFF, sum = 0
1958 12:43:10.502022 2, 0xFFFF, sum = 0
1959 12:43:10.502119 3, 0xFFFF, sum = 0
1960 12:43:10.505629 4, 0xFFFF, sum = 0
1961 12:43:10.505702 5, 0xFFFF, sum = 0
1962 12:43:10.508733 6, 0xFFFF, sum = 0
1963 12:43:10.508803 7, 0xFFFF, sum = 0
1964 12:43:10.512183 8, 0xFFFF, sum = 0
1965 12:43:10.512254 9, 0x0, sum = 1
1966 12:43:10.515923 10, 0x0, sum = 2
1967 12:43:10.516040 11, 0x0, sum = 3
1968 12:43:10.516167 12, 0x0, sum = 4
1969 12:43:10.518714 best_step = 10
1970 12:43:10.518806
1971 12:43:10.518893 ==
1972 12:43:10.521929 Dram Type= 6, Freq= 0, CH_1, rank 1
1973 12:43:10.526046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1974 12:43:10.526146 ==
1975 12:43:10.528749 RX Vref Scan: 0
1976 12:43:10.528844
1977 12:43:10.532262 RX Vref 0 -> 0, step: 1
1978 12:43:10.532333
1979 12:43:10.532411 RX Delay -95 -> 252, step: 8
1980 12:43:10.540333 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
1981 12:43:10.542337 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
1982 12:43:10.545674 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1983 12:43:10.549223 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1984 12:43:10.552676 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1985 12:43:10.559272 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
1986 12:43:10.562716 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1987 12:43:10.566058 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
1988 12:43:10.569064 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1989 12:43:10.573184 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
1990 12:43:10.578801 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1991 12:43:10.582349 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1992 12:43:10.585806 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1993 12:43:10.589015 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1994 12:43:10.595769 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1995 12:43:10.598873 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1996 12:43:10.598972 ==
1997 12:43:10.601944 Dram Type= 6, Freq= 0, CH_1, rank 1
1998 12:43:10.605918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1999 12:43:10.606019 ==
2000 12:43:10.608627 DQS Delay:
2001 12:43:10.608695 DQS0 = 0, DQS1 = 0
2002 12:43:10.608755 DQM Delay:
2003 12:43:10.612313 DQM0 = 86, DQM1 = 81
2004 12:43:10.612394 DQ Delay:
2005 12:43:10.615367 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2006 12:43:10.618893 DQ4 =88, DQ5 =96, DQ6 =92, DQ7 =84
2007 12:43:10.622264 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
2008 12:43:10.625301 DQ12 =88, DQ13 =92, DQ14 =88, DQ15 =88
2009 12:43:10.625383
2010 12:43:10.625447
2011 12:43:10.635807 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a36, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
2012 12:43:10.635889 CH1 RK1: MR19=606, MR18=1A36
2013 12:43:10.642518 CH1_RK1: MR19=0x606, MR18=0x1A36, DQSOSC=396, MR23=63, INC=94, DEC=62
2014 12:43:10.645807 [RxdqsGatingPostProcess] freq 800
2015 12:43:10.652190 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2016 12:43:10.655192 Pre-setting of DQS Precalculation
2017 12:43:10.658287 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2018 12:43:10.665234 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2019 12:43:10.674780 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2020 12:43:10.674861
2021 12:43:10.674925
2022 12:43:10.678827 [Calibration Summary] 1600 Mbps
2023 12:43:10.678907 CH 0, Rank 0
2024 12:43:10.681517 SW Impedance : PASS
2025 12:43:10.681598 DUTY Scan : NO K
2026 12:43:10.684894 ZQ Calibration : PASS
2027 12:43:10.688167 Jitter Meter : NO K
2028 12:43:10.688259 CBT Training : PASS
2029 12:43:10.691624 Write leveling : PASS
2030 12:43:10.695473 RX DQS gating : PASS
2031 12:43:10.695554 RX DQ/DQS(RDDQC) : PASS
2032 12:43:10.697927 TX DQ/DQS : PASS
2033 12:43:10.698008 RX DATLAT : PASS
2034 12:43:10.701934 RX DQ/DQS(Engine): PASS
2035 12:43:10.705326 TX OE : NO K
2036 12:43:10.705407 All Pass.
2037 12:43:10.705471
2038 12:43:10.705530 CH 0, Rank 1
2039 12:43:10.708255 SW Impedance : PASS
2040 12:43:10.711162 DUTY Scan : NO K
2041 12:43:10.711242 ZQ Calibration : PASS
2042 12:43:10.714558 Jitter Meter : NO K
2043 12:43:10.717897 CBT Training : PASS
2044 12:43:10.717977 Write leveling : PASS
2045 12:43:10.721792 RX DQS gating : PASS
2046 12:43:10.724646 RX DQ/DQS(RDDQC) : PASS
2047 12:43:10.724727 TX DQ/DQS : PASS
2048 12:43:10.727733 RX DATLAT : PASS
2049 12:43:10.731310 RX DQ/DQS(Engine): PASS
2050 12:43:10.731391 TX OE : NO K
2051 12:43:10.735021 All Pass.
2052 12:43:10.735106
2053 12:43:10.735170 CH 1, Rank 0
2054 12:43:10.738536 SW Impedance : PASS
2055 12:43:10.738618 DUTY Scan : NO K
2056 12:43:10.741005 ZQ Calibration : PASS
2057 12:43:10.744114 Jitter Meter : NO K
2058 12:43:10.744191 CBT Training : PASS
2059 12:43:10.747623 Write leveling : PASS
2060 12:43:10.751578 RX DQS gating : PASS
2061 12:43:10.751658 RX DQ/DQS(RDDQC) : PASS
2062 12:43:10.754782 TX DQ/DQS : PASS
2063 12:43:10.754881 RX DATLAT : PASS
2064 12:43:10.757628 RX DQ/DQS(Engine): PASS
2065 12:43:10.760755 TX OE : NO K
2066 12:43:10.760825 All Pass.
2067 12:43:10.760885
2068 12:43:10.764004 CH 1, Rank 1
2069 12:43:10.764117 SW Impedance : PASS
2070 12:43:10.767469 DUTY Scan : NO K
2071 12:43:10.767549 ZQ Calibration : PASS
2072 12:43:10.771144 Jitter Meter : NO K
2073 12:43:10.774689 CBT Training : PASS
2074 12:43:10.774759 Write leveling : PASS
2075 12:43:10.778006 RX DQS gating : PASS
2076 12:43:10.781023 RX DQ/DQS(RDDQC) : PASS
2077 12:43:10.781091 TX DQ/DQS : PASS
2078 12:43:10.784253 RX DATLAT : PASS
2079 12:43:10.787674 RX DQ/DQS(Engine): PASS
2080 12:43:10.787747 TX OE : NO K
2081 12:43:10.790745 All Pass.
2082 12:43:10.790838
2083 12:43:10.790932 DramC Write-DBI off
2084 12:43:10.794042 PER_BANK_REFRESH: Hybrid Mode
2085 12:43:10.797409 TX_TRACKING: ON
2086 12:43:10.800488 [GetDramInforAfterCalByMRR] Vendor 6.
2087 12:43:10.803828 [GetDramInforAfterCalByMRR] Revision 606.
2088 12:43:10.807641 [GetDramInforAfterCalByMRR] Revision 2 0.
2089 12:43:10.807742 MR0 0x3b3b
2090 12:43:10.807838 MR8 0x5151
2091 12:43:10.813882 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2092 12:43:10.813954
2093 12:43:10.814014 MR0 0x3b3b
2094 12:43:10.814072 MR8 0x5151
2095 12:43:10.817533 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2096 12:43:10.817609
2097 12:43:10.827362 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2098 12:43:10.830243 [FAST_K] Save calibration result to emmc
2099 12:43:10.833526 [FAST_K] Save calibration result to emmc
2100 12:43:10.837175 dram_init: config_dvfs: 1
2101 12:43:10.840546 dramc_set_vcore_voltage set vcore to 662500
2102 12:43:10.843467 Read voltage for 1200, 2
2103 12:43:10.843547 Vio18 = 0
2104 12:43:10.843610 Vcore = 662500
2105 12:43:10.847203 Vdram = 0
2106 12:43:10.847284 Vddq = 0
2107 12:43:10.847348 Vmddr = 0
2108 12:43:10.853380 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2109 12:43:10.856859 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2110 12:43:10.860536 MEM_TYPE=3, freq_sel=15
2111 12:43:10.863639 sv_algorithm_assistance_LP4_1600
2112 12:43:10.866614 ============ PULL DRAM RESETB DOWN ============
2113 12:43:10.873645 ========== PULL DRAM RESETB DOWN end =========
2114 12:43:10.876465 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2115 12:43:10.880152 ===================================
2116 12:43:10.883031 LPDDR4 DRAM CONFIGURATION
2117 12:43:10.886399 ===================================
2118 12:43:10.886480 EX_ROW_EN[0] = 0x0
2119 12:43:10.889878 EX_ROW_EN[1] = 0x0
2120 12:43:10.889958 LP4Y_EN = 0x0
2121 12:43:10.893090 WORK_FSP = 0x0
2122 12:43:10.893170 WL = 0x4
2123 12:43:10.896327 RL = 0x4
2124 12:43:10.896407 BL = 0x2
2125 12:43:10.899965 RPST = 0x0
2126 12:43:10.900078 RD_PRE = 0x0
2127 12:43:10.903069 WR_PRE = 0x1
2128 12:43:10.903149 WR_PST = 0x0
2129 12:43:10.906840 DBI_WR = 0x0
2130 12:43:10.909992 DBI_RD = 0x0
2131 12:43:10.910072 OTF = 0x1
2132 12:43:10.913294 ===================================
2133 12:43:10.916825 ===================================
2134 12:43:10.916906 ANA top config
2135 12:43:10.920228 ===================================
2136 12:43:10.923194 DLL_ASYNC_EN = 0
2137 12:43:10.927974 ALL_SLAVE_EN = 0
2138 12:43:10.929955 NEW_RANK_MODE = 1
2139 12:43:10.933211 DLL_IDLE_MODE = 1
2140 12:43:10.933291 LP45_APHY_COMB_EN = 1
2141 12:43:10.936631 TX_ODT_DIS = 1
2142 12:43:10.939783 NEW_8X_MODE = 1
2143 12:43:10.943131 ===================================
2144 12:43:10.946501 ===================================
2145 12:43:10.949785 data_rate = 2400
2146 12:43:10.953308 CKR = 1
2147 12:43:10.953395 DQ_P2S_RATIO = 8
2148 12:43:10.956633 ===================================
2149 12:43:10.960300 CA_P2S_RATIO = 8
2150 12:43:10.963782 DQ_CA_OPEN = 0
2151 12:43:10.966258 DQ_SEMI_OPEN = 0
2152 12:43:10.969803 CA_SEMI_OPEN = 0
2153 12:43:10.969902 CA_FULL_RATE = 0
2154 12:43:10.973261 DQ_CKDIV4_EN = 0
2155 12:43:10.976759 CA_CKDIV4_EN = 0
2156 12:43:10.979443 CA_PREDIV_EN = 0
2157 12:43:10.983897 PH8_DLY = 17
2158 12:43:10.986523 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2159 12:43:10.989574 DQ_AAMCK_DIV = 4
2160 12:43:10.989645 CA_AAMCK_DIV = 4
2161 12:43:10.993113 CA_ADMCK_DIV = 4
2162 12:43:10.996323 DQ_TRACK_CA_EN = 0
2163 12:43:10.999915 CA_PICK = 1200
2164 12:43:11.002811 CA_MCKIO = 1200
2165 12:43:11.006150 MCKIO_SEMI = 0
2166 12:43:11.009979 PLL_FREQ = 2366
2167 12:43:11.010048 DQ_UI_PI_RATIO = 32
2168 12:43:11.013240 CA_UI_PI_RATIO = 0
2169 12:43:11.016530 ===================================
2170 12:43:11.019389 ===================================
2171 12:43:11.023248 memory_type:LPDDR4
2172 12:43:11.026070 GP_NUM : 10
2173 12:43:11.026150 SRAM_EN : 1
2174 12:43:11.029597 MD32_EN : 0
2175 12:43:11.032573 ===================================
2176 12:43:11.036145 [ANA_INIT] >>>>>>>>>>>>>>
2177 12:43:11.036267 <<<<<< [CONFIGURE PHASE]: ANA_TX
2178 12:43:11.039331 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2179 12:43:11.043512 ===================================
2180 12:43:11.046110 data_rate = 2400,PCW = 0X5b00
2181 12:43:11.049416 ===================================
2182 12:43:11.052510 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2183 12:43:11.059337 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2184 12:43:11.066410 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2185 12:43:11.069177 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2186 12:43:11.072260 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2187 12:43:11.075825 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2188 12:43:11.078810 [ANA_INIT] flow start
2189 12:43:11.078907 [ANA_INIT] PLL >>>>>>>>
2190 12:43:11.082982 [ANA_INIT] PLL <<<<<<<<
2191 12:43:11.085546 [ANA_INIT] MIDPI >>>>>>>>
2192 12:43:11.089362 [ANA_INIT] MIDPI <<<<<<<<
2193 12:43:11.089433 [ANA_INIT] DLL >>>>>>>>
2194 12:43:11.092180 [ANA_INIT] DLL <<<<<<<<
2195 12:43:11.092274 [ANA_INIT] flow end
2196 12:43:11.099033 ============ LP4 DIFF to SE enter ============
2197 12:43:11.103229 ============ LP4 DIFF to SE exit ============
2198 12:43:11.106272 [ANA_INIT] <<<<<<<<<<<<<
2199 12:43:11.109027 [Flow] Enable top DCM control >>>>>
2200 12:43:11.112139 [Flow] Enable top DCM control <<<<<
2201 12:43:11.112208 Enable DLL master slave shuffle
2202 12:43:11.118703 ==============================================================
2203 12:43:11.122336 Gating Mode config
2204 12:43:11.126330 ==============================================================
2205 12:43:11.129180 Config description:
2206 12:43:11.138859 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2207 12:43:11.145712 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2208 12:43:11.148650 SELPH_MODE 0: By rank 1: By Phase
2209 12:43:11.155619 ==============================================================
2210 12:43:11.158437 GAT_TRACK_EN = 1
2211 12:43:11.161696 RX_GATING_MODE = 2
2212 12:43:11.165210 RX_GATING_TRACK_MODE = 2
2213 12:43:11.168519 SELPH_MODE = 1
2214 12:43:11.171675 PICG_EARLY_EN = 1
2215 12:43:11.171760 VALID_LAT_VALUE = 1
2216 12:43:11.178431 ==============================================================
2217 12:43:11.182168 Enter into Gating configuration >>>>
2218 12:43:11.185380 Exit from Gating configuration <<<<
2219 12:43:11.189538 Enter into DVFS_PRE_config >>>>>
2220 12:43:11.198702 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2221 12:43:11.201634 Exit from DVFS_PRE_config <<<<<
2222 12:43:11.206204 Enter into PICG configuration >>>>
2223 12:43:11.208238 Exit from PICG configuration <<<<
2224 12:43:11.211966 [RX_INPUT] configuration >>>>>
2225 12:43:11.215088 [RX_INPUT] configuration <<<<<
2226 12:43:11.221641 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2227 12:43:11.225288 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2228 12:43:11.231667 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2229 12:43:11.238068 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2230 12:43:11.244621 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2231 12:43:11.251197 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2232 12:43:11.254718 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2233 12:43:11.258773 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2234 12:43:11.261253 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2235 12:43:11.267981 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2236 12:43:11.271732 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2237 12:43:11.276146 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2238 12:43:11.278161 ===================================
2239 12:43:11.281231 LPDDR4 DRAM CONFIGURATION
2240 12:43:11.284503 ===================================
2241 12:43:11.284583 EX_ROW_EN[0] = 0x0
2242 12:43:11.288357 EX_ROW_EN[1] = 0x0
2243 12:43:11.288436 LP4Y_EN = 0x0
2244 12:43:11.291258 WORK_FSP = 0x0
2245 12:43:11.294236 WL = 0x4
2246 12:43:11.294316 RL = 0x4
2247 12:43:11.297760 BL = 0x2
2248 12:43:11.297871 RPST = 0x0
2249 12:43:11.301081 RD_PRE = 0x0
2250 12:43:11.301162 WR_PRE = 0x1
2251 12:43:11.305170 WR_PST = 0x0
2252 12:43:11.305250 DBI_WR = 0x0
2253 12:43:11.307604 DBI_RD = 0x0
2254 12:43:11.307685 OTF = 0x1
2255 12:43:11.310812 ===================================
2256 12:43:11.314422 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2257 12:43:11.320931 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2258 12:43:11.324459 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2259 12:43:11.327780 ===================================
2260 12:43:11.331007 LPDDR4 DRAM CONFIGURATION
2261 12:43:11.333912 ===================================
2262 12:43:11.333992 EX_ROW_EN[0] = 0x10
2263 12:43:11.337324 EX_ROW_EN[1] = 0x0
2264 12:43:11.337404 LP4Y_EN = 0x0
2265 12:43:11.340924 WORK_FSP = 0x0
2266 12:43:11.341004 WL = 0x4
2267 12:43:11.344348 RL = 0x4
2268 12:43:11.347317 BL = 0x2
2269 12:43:11.347396 RPST = 0x0
2270 12:43:11.350663 RD_PRE = 0x0
2271 12:43:11.350743 WR_PRE = 0x1
2272 12:43:11.354049 WR_PST = 0x0
2273 12:43:11.354163 DBI_WR = 0x0
2274 12:43:11.357506 DBI_RD = 0x0
2275 12:43:11.357586 OTF = 0x1
2276 12:43:11.360922 ===================================
2277 12:43:11.367272 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2278 12:43:11.367352 ==
2279 12:43:11.370398 Dram Type= 6, Freq= 0, CH_0, rank 0
2280 12:43:11.374049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2281 12:43:11.374146 ==
2282 12:43:11.377361 [Duty_Offset_Calibration]
2283 12:43:11.380405 B0:2 B1:0 CA:4
2284 12:43:11.380485
2285 12:43:11.383760 [DutyScan_Calibration_Flow] k_type=0
2286 12:43:11.390901
2287 12:43:11.390981 ==CLK 0==
2288 12:43:11.394188 Final CLK duty delay cell = -4
2289 12:43:11.398297 [-4] MAX Duty = 5062%(X100), DQS PI = 32
2290 12:43:11.400796 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2291 12:43:11.404149 [-4] AVG Duty = 4953%(X100)
2292 12:43:11.404260
2293 12:43:11.407438 CH0 CLK Duty spec in!! Max-Min= 218%
2294 12:43:11.411511 [DutyScan_Calibration_Flow] ====Done====
2295 12:43:11.411583
2296 12:43:11.414254 [DutyScan_Calibration_Flow] k_type=1
2297 12:43:11.430814
2298 12:43:11.430920 ==DQS 0 ==
2299 12:43:11.434001 Final DQS duty delay cell = 0
2300 12:43:11.437498 [0] MAX Duty = 5156%(X100), DQS PI = 18
2301 12:43:11.440663 [0] MIN Duty = 5093%(X100), DQS PI = 0
2302 12:43:11.443701 [0] AVG Duty = 5124%(X100)
2303 12:43:11.443779
2304 12:43:11.443840 ==DQS 1 ==
2305 12:43:11.447501 Final DQS duty delay cell = 0
2306 12:43:11.450732 [0] MAX Duty = 5125%(X100), DQS PI = 4
2307 12:43:11.453884 [0] MIN Duty = 5000%(X100), DQS PI = 0
2308 12:43:11.457314 [0] AVG Duty = 5062%(X100)
2309 12:43:11.457393
2310 12:43:11.460613 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2311 12:43:11.460691
2312 12:43:11.463684 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2313 12:43:11.467335 [DutyScan_Calibration_Flow] ====Done====
2314 12:43:11.467413
2315 12:43:11.470387 [DutyScan_Calibration_Flow] k_type=3
2316 12:43:11.487175
2317 12:43:11.487252 ==DQM 0 ==
2318 12:43:11.490535 Final DQM duty delay cell = 0
2319 12:43:11.494277 [0] MAX Duty = 5125%(X100), DQS PI = 20
2320 12:43:11.497284 [0] MIN Duty = 4875%(X100), DQS PI = 52
2321 12:43:11.497363 [0] AVG Duty = 5000%(X100)
2322 12:43:11.500266
2323 12:43:11.500343 ==DQM 1 ==
2324 12:43:11.503881 Final DQM duty delay cell = 0
2325 12:43:11.507031 [0] MAX Duty = 4969%(X100), DQS PI = 2
2326 12:43:11.510401 [0] MIN Duty = 4876%(X100), DQS PI = 20
2327 12:43:11.510479 [0] AVG Duty = 4922%(X100)
2328 12:43:11.510541
2329 12:43:11.517028 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2330 12:43:11.517106
2331 12:43:11.520784 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2332 12:43:11.523902 [DutyScan_Calibration_Flow] ====Done====
2333 12:43:11.523980
2334 12:43:11.526867 [DutyScan_Calibration_Flow] k_type=2
2335 12:43:11.543091
2336 12:43:11.543171 ==DQ 0 ==
2337 12:43:11.546600 Final DQ duty delay cell = 0
2338 12:43:11.550176 [0] MAX Duty = 5125%(X100), DQS PI = 18
2339 12:43:11.554126 [0] MIN Duty = 5000%(X100), DQS PI = 10
2340 12:43:11.554204 [0] AVG Duty = 5062%(X100)
2341 12:43:11.557034
2342 12:43:11.557112 ==DQ 1 ==
2343 12:43:11.559868 Final DQ duty delay cell = 0
2344 12:43:11.563382 [0] MAX Duty = 5125%(X100), DQS PI = 6
2345 12:43:11.566591 [0] MIN Duty = 4938%(X100), DQS PI = 16
2346 12:43:11.566669 [0] AVG Duty = 5031%(X100)
2347 12:43:11.566731
2348 12:43:11.569960 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2349 12:43:11.573721
2350 12:43:11.576458 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2351 12:43:11.579526 [DutyScan_Calibration_Flow] ====Done====
2352 12:43:11.579599 ==
2353 12:43:11.582678 Dram Type= 6, Freq= 0, CH_1, rank 0
2354 12:43:11.586482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2355 12:43:11.586554 ==
2356 12:43:11.589397 [Duty_Offset_Calibration]
2357 12:43:11.589467 B0:0 B1:-1 CA:3
2358 12:43:11.589526
2359 12:43:11.592870 [DutyScan_Calibration_Flow] k_type=0
2360 12:43:11.602555
2361 12:43:11.602634 ==CLK 0==
2362 12:43:11.605777 Final CLK duty delay cell = -4
2363 12:43:11.609596 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2364 12:43:11.612544 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2365 12:43:11.615882 [-4] AVG Duty = 4938%(X100)
2366 12:43:11.615962
2367 12:43:11.619150 CH1 CLK Duty spec in!! Max-Min= 124%
2368 12:43:11.622103 [DutyScan_Calibration_Flow] ====Done====
2369 12:43:11.622201
2370 12:43:11.625813 [DutyScan_Calibration_Flow] k_type=1
2371 12:43:11.642492
2372 12:43:11.642574 ==DQS 0 ==
2373 12:43:11.645561 Final DQS duty delay cell = 0
2374 12:43:11.649119 [0] MAX Duty = 5187%(X100), DQS PI = 18
2375 12:43:11.651774 [0] MIN Duty = 4907%(X100), DQS PI = 38
2376 12:43:11.655313 [0] AVG Duty = 5047%(X100)
2377 12:43:11.655384
2378 12:43:11.655455 ==DQS 1 ==
2379 12:43:11.658364 Final DQS duty delay cell = 0
2380 12:43:11.662007 [0] MAX Duty = 5156%(X100), DQS PI = 8
2381 12:43:11.665368 [0] MIN Duty = 5000%(X100), DQS PI = 26
2382 12:43:11.668789 [0] AVG Duty = 5078%(X100)
2383 12:43:11.668859
2384 12:43:11.671952 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2385 12:43:11.672072
2386 12:43:11.675004 CH1 DQS 1 Duty spec in!! Max-Min= 156%
2387 12:43:11.678188 [DutyScan_Calibration_Flow] ====Done====
2388 12:43:11.678257
2389 12:43:11.681792 [DutyScan_Calibration_Flow] k_type=3
2390 12:43:11.698763
2391 12:43:11.698844 ==DQM 0 ==
2392 12:43:11.701891 Final DQM duty delay cell = 0
2393 12:43:11.705622 [0] MAX Duty = 5031%(X100), DQS PI = 28
2394 12:43:11.708781 [0] MIN Duty = 4813%(X100), DQS PI = 38
2395 12:43:11.711762 [0] AVG Duty = 4922%(X100)
2396 12:43:11.711842
2397 12:43:11.711906 ==DQM 1 ==
2398 12:43:11.715024 Final DQM duty delay cell = 0
2399 12:43:11.719213 [0] MAX Duty = 5000%(X100), DQS PI = 34
2400 12:43:11.722265 [0] MIN Duty = 4844%(X100), DQS PI = 0
2401 12:43:11.725304 [0] AVG Duty = 4922%(X100)
2402 12:43:11.725384
2403 12:43:11.728449 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2404 12:43:11.728530
2405 12:43:11.731866 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2406 12:43:11.734938 [DutyScan_Calibration_Flow] ====Done====
2407 12:43:11.735018
2408 12:43:11.739222 [DutyScan_Calibration_Flow] k_type=2
2409 12:43:11.754743
2410 12:43:11.754823 ==DQ 0 ==
2411 12:43:11.757935 Final DQ duty delay cell = -4
2412 12:43:11.760723 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2413 12:43:11.764397 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2414 12:43:11.767567 [-4] AVG Duty = 4922%(X100)
2415 12:43:11.767647
2416 12:43:11.767710 ==DQ 1 ==
2417 12:43:11.771349 Final DQ duty delay cell = 0
2418 12:43:11.774620 [0] MAX Duty = 5031%(X100), DQS PI = 34
2419 12:43:11.777561 [0] MIN Duty = 4844%(X100), DQS PI = 0
2420 12:43:11.777641 [0] AVG Duty = 4937%(X100)
2421 12:43:11.781429
2422 12:43:11.784280 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2423 12:43:11.784359
2424 12:43:11.787286 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2425 12:43:11.790841 [DutyScan_Calibration_Flow] ====Done====
2426 12:43:11.794098 nWR fixed to 30
2427 12:43:11.794200 [ModeRegInit_LP4] CH0 RK0
2428 12:43:11.797566 [ModeRegInit_LP4] CH0 RK1
2429 12:43:11.800729 [ModeRegInit_LP4] CH1 RK0
2430 12:43:11.803925 [ModeRegInit_LP4] CH1 RK1
2431 12:43:11.804005 match AC timing 7
2432 12:43:11.810681 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2433 12:43:11.814185 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2434 12:43:11.817375 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2435 12:43:11.823943 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2436 12:43:11.828217 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2437 12:43:11.828297 ==
2438 12:43:11.830956 Dram Type= 6, Freq= 0, CH_0, rank 0
2439 12:43:11.834185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2440 12:43:11.834266 ==
2441 12:43:11.841010 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2442 12:43:11.847076 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2443 12:43:11.854702 [CA 0] Center 39 (9~70) winsize 62
2444 12:43:11.858211 [CA 1] Center 39 (9~70) winsize 62
2445 12:43:11.861420 [CA 2] Center 35 (5~66) winsize 62
2446 12:43:11.864449 [CA 3] Center 35 (5~66) winsize 62
2447 12:43:11.868045 [CA 4] Center 33 (3~64) winsize 62
2448 12:43:11.871030 [CA 5] Center 33 (3~64) winsize 62
2449 12:43:11.871109
2450 12:43:11.874371 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2451 12:43:11.874452
2452 12:43:11.877437 [CATrainingPosCal] consider 1 rank data
2453 12:43:11.881134 u2DelayCellTimex100 = 270/100 ps
2454 12:43:11.884870 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2455 12:43:11.891354 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2456 12:43:11.894404 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2457 12:43:11.897973 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2458 12:43:11.901175 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2459 12:43:11.904439 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2460 12:43:11.904519
2461 12:43:11.907997 CA PerBit enable=1, Macro0, CA PI delay=33
2462 12:43:11.908115
2463 12:43:11.911268 [CBTSetCACLKResult] CA Dly = 33
2464 12:43:11.911349 CS Dly: 7 (0~38)
2465 12:43:11.914530 ==
2466 12:43:11.917370 Dram Type= 6, Freq= 0, CH_0, rank 1
2467 12:43:11.921057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2468 12:43:11.921138 ==
2469 12:43:11.924203 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2470 12:43:11.930735 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2471 12:43:11.940879 [CA 0] Center 39 (9~70) winsize 62
2472 12:43:11.943824 [CA 1] Center 39 (9~70) winsize 62
2473 12:43:11.947380 [CA 2] Center 35 (5~66) winsize 62
2474 12:43:11.950166 [CA 3] Center 35 (5~66) winsize 62
2475 12:43:11.953919 [CA 4] Center 34 (4~65) winsize 62
2476 12:43:11.956600 [CA 5] Center 33 (3~64) winsize 62
2477 12:43:11.956681
2478 12:43:11.960376 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2479 12:43:11.960457
2480 12:43:11.963530 [CATrainingPosCal] consider 2 rank data
2481 12:43:11.967232 u2DelayCellTimex100 = 270/100 ps
2482 12:43:11.970401 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2483 12:43:11.976808 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2484 12:43:11.980754 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2485 12:43:11.983284 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2486 12:43:11.986514 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2487 12:43:11.990083 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2488 12:43:11.990164
2489 12:43:11.993158 CA PerBit enable=1, Macro0, CA PI delay=33
2490 12:43:11.993240
2491 12:43:11.996585 [CBTSetCACLKResult] CA Dly = 33
2492 12:43:11.996666 CS Dly: 8 (0~41)
2493 12:43:11.999803
2494 12:43:12.003068 ----->DramcWriteLeveling(PI) begin...
2495 12:43:12.003151 ==
2496 12:43:12.006656 Dram Type= 6, Freq= 0, CH_0, rank 0
2497 12:43:12.009798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2498 12:43:12.009880 ==
2499 12:43:12.013277 Write leveling (Byte 0): 31 => 31
2500 12:43:12.016906 Write leveling (Byte 1): 28 => 28
2501 12:43:12.019831 DramcWriteLeveling(PI) end<-----
2502 12:43:12.019912
2503 12:43:12.019975 ==
2504 12:43:12.023365 Dram Type= 6, Freq= 0, CH_0, rank 0
2505 12:43:12.026357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2506 12:43:12.026438 ==
2507 12:43:12.029770 [Gating] SW mode calibration
2508 12:43:12.036522 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2509 12:43:12.043277 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2510 12:43:12.046629 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2511 12:43:12.050447 0 15 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
2512 12:43:12.057092 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2513 12:43:12.059678 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2514 12:43:12.063710 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2515 12:43:12.069596 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2516 12:43:12.074127 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2517 12:43:12.076446 0 15 28 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
2518 12:43:12.079578 1 0 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
2519 12:43:12.086074 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2520 12:43:12.089601 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2521 12:43:12.093176 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2522 12:43:12.099903 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2523 12:43:12.102784 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2524 12:43:12.106087 1 0 24 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
2525 12:43:12.113199 1 0 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
2526 12:43:12.116212 1 1 0 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
2527 12:43:12.119798 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2528 12:43:12.126056 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2529 12:43:12.129287 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2530 12:43:12.132435 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2531 12:43:12.139073 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2532 12:43:12.142848 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2533 12:43:12.146238 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2534 12:43:12.152459 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2535 12:43:12.156014 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2536 12:43:12.159256 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2537 12:43:12.165622 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2538 12:43:12.169584 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2539 12:43:12.172141 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2540 12:43:12.179479 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 12:43:12.183024 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 12:43:12.185953 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 12:43:12.192202 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 12:43:12.195705 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 12:43:12.198904 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 12:43:12.205306 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 12:43:12.208827 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 12:43:12.212265 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 12:43:12.218620 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2550 12:43:12.221763 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2551 12:43:12.225425 Total UI for P1: 0, mck2ui 16
2552 12:43:12.228627 best dqsien dly found for B0: ( 1, 3, 28)
2553 12:43:12.231855 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 12:43:12.235111 Total UI for P1: 0, mck2ui 16
2555 12:43:12.239185 best dqsien dly found for B1: ( 1, 4, 0)
2556 12:43:12.241769 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2557 12:43:12.245315 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2558 12:43:12.245397
2559 12:43:12.252234 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2560 12:43:12.255009 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2561 12:43:12.255099 [Gating] SW calibration Done
2562 12:43:12.258530 ==
2563 12:43:12.258612 Dram Type= 6, Freq= 0, CH_0, rank 0
2564 12:43:12.265894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2565 12:43:12.265977 ==
2566 12:43:12.266042 RX Vref Scan: 0
2567 12:43:12.266103
2568 12:43:12.268163 RX Vref 0 -> 0, step: 1
2569 12:43:12.268245
2570 12:43:12.271826 RX Delay -40 -> 252, step: 8
2571 12:43:12.275229 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2572 12:43:12.277922 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2573 12:43:12.284985 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2574 12:43:12.288163 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2575 12:43:12.291561 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2576 12:43:12.294682 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2577 12:43:12.298992 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2578 12:43:12.301251 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2579 12:43:12.308349 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2580 12:43:12.311343 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2581 12:43:12.314779 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2582 12:43:12.318621 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2583 12:43:12.321269 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2584 12:43:12.328312 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2585 12:43:12.331430 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2586 12:43:12.334304 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2587 12:43:12.334387 ==
2588 12:43:12.337730 Dram Type= 6, Freq= 0, CH_0, rank 0
2589 12:43:12.340997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2590 12:43:12.344766 ==
2591 12:43:12.344848 DQS Delay:
2592 12:43:12.344913 DQS0 = 0, DQS1 = 0
2593 12:43:12.347667 DQM Delay:
2594 12:43:12.347749 DQM0 = 118, DQM1 = 107
2595 12:43:12.351329 DQ Delay:
2596 12:43:12.354721 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =115
2597 12:43:12.357854 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2598 12:43:12.361186 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2599 12:43:12.364606 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =111
2600 12:43:12.364687
2601 12:43:12.364752
2602 12:43:12.364814 ==
2603 12:43:12.367634 Dram Type= 6, Freq= 0, CH_0, rank 0
2604 12:43:12.371086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2605 12:43:12.371193 ==
2606 12:43:12.371288
2607 12:43:12.374300
2608 12:43:12.374381 TX Vref Scan disable
2609 12:43:12.377384 == TX Byte 0 ==
2610 12:43:12.380890 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2611 12:43:12.384299 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2612 12:43:12.387352 == TX Byte 1 ==
2613 12:43:12.390417 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2614 12:43:12.393858 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2615 12:43:12.393966 ==
2616 12:43:12.397097 Dram Type= 6, Freq= 0, CH_0, rank 0
2617 12:43:12.403602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2618 12:43:12.403685 ==
2619 12:43:12.414678 TX Vref=22, minBit 0, minWin=25, winSum=410
2620 12:43:12.418280 TX Vref=24, minBit 3, minWin=25, winSum=417
2621 12:43:12.421224 TX Vref=26, minBit 8, minWin=25, winSum=419
2622 12:43:12.424694 TX Vref=28, minBit 0, minWin=26, winSum=425
2623 12:43:12.427669 TX Vref=30, minBit 1, minWin=26, winSum=428
2624 12:43:12.434455 TX Vref=32, minBit 4, minWin=26, winSum=428
2625 12:43:12.437770 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 30
2626 12:43:12.437852
2627 12:43:12.441576 Final TX Range 1 Vref 30
2628 12:43:12.441658
2629 12:43:12.441723 ==
2630 12:43:12.444319 Dram Type= 6, Freq= 0, CH_0, rank 0
2631 12:43:12.448123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2632 12:43:12.448205 ==
2633 12:43:12.448275
2634 12:43:12.451831
2635 12:43:12.451912 TX Vref Scan disable
2636 12:43:12.454721 == TX Byte 0 ==
2637 12:43:12.458151 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2638 12:43:12.461118 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2639 12:43:12.464758 == TX Byte 1 ==
2640 12:43:12.467981 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2641 12:43:12.471342 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2642 12:43:12.474330
2643 12:43:12.474412 [DATLAT]
2644 12:43:12.474477 Freq=1200, CH0 RK0
2645 12:43:12.474536
2646 12:43:12.477724 DATLAT Default: 0xd
2647 12:43:12.477806 0, 0xFFFF, sum = 0
2648 12:43:12.481672 1, 0xFFFF, sum = 0
2649 12:43:12.481756 2, 0xFFFF, sum = 0
2650 12:43:12.485005 3, 0xFFFF, sum = 0
2651 12:43:12.487664 4, 0xFFFF, sum = 0
2652 12:43:12.487747 5, 0xFFFF, sum = 0
2653 12:43:12.490975 6, 0xFFFF, sum = 0
2654 12:43:12.491058 7, 0xFFFF, sum = 0
2655 12:43:12.494478 8, 0xFFFF, sum = 0
2656 12:43:12.494562 9, 0xFFFF, sum = 0
2657 12:43:12.498009 10, 0xFFFF, sum = 0
2658 12:43:12.498092 11, 0xFFFF, sum = 0
2659 12:43:12.501085 12, 0x0, sum = 1
2660 12:43:12.501168 13, 0x0, sum = 2
2661 12:43:12.504720 14, 0x0, sum = 3
2662 12:43:12.504803 15, 0x0, sum = 4
2663 12:43:12.507416 best_step = 13
2664 12:43:12.507498
2665 12:43:12.507562 ==
2666 12:43:12.510822 Dram Type= 6, Freq= 0, CH_0, rank 0
2667 12:43:12.514114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2668 12:43:12.514197 ==
2669 12:43:12.514261 RX Vref Scan: 1
2670 12:43:12.514321
2671 12:43:12.517331 Set Vref Range= 32 -> 127
2672 12:43:12.517413
2673 12:43:12.520488 RX Vref 32 -> 127, step: 1
2674 12:43:12.520570
2675 12:43:12.523853 RX Delay -21 -> 252, step: 4
2676 12:43:12.523935
2677 12:43:12.527344 Set Vref, RX VrefLevel [Byte0]: 32
2678 12:43:12.531377 [Byte1]: 32
2679 12:43:12.531459
2680 12:43:12.533955 Set Vref, RX VrefLevel [Byte0]: 33
2681 12:43:12.538131 [Byte1]: 33
2682 12:43:12.541297
2683 12:43:12.541378 Set Vref, RX VrefLevel [Byte0]: 34
2684 12:43:12.544360 [Byte1]: 34
2685 12:43:12.549302
2686 12:43:12.549399 Set Vref, RX VrefLevel [Byte0]: 35
2687 12:43:12.552394 [Byte1]: 35
2688 12:43:12.556873
2689 12:43:12.556954 Set Vref, RX VrefLevel [Byte0]: 36
2690 12:43:12.560351 [Byte1]: 36
2691 12:43:12.564972
2692 12:43:12.568304 Set Vref, RX VrefLevel [Byte0]: 37
2693 12:43:12.570957 [Byte1]: 37
2694 12:43:12.571064
2695 12:43:12.574358 Set Vref, RX VrefLevel [Byte0]: 38
2696 12:43:12.577533 [Byte1]: 38
2697 12:43:12.577615
2698 12:43:12.581233 Set Vref, RX VrefLevel [Byte0]: 39
2699 12:43:12.584608 [Byte1]: 39
2700 12:43:12.588255
2701 12:43:12.588336 Set Vref, RX VrefLevel [Byte0]: 40
2702 12:43:12.591661 [Byte1]: 40
2703 12:43:12.596426
2704 12:43:12.599741 Set Vref, RX VrefLevel [Byte0]: 41
2705 12:43:12.603020 [Byte1]: 41
2706 12:43:12.603102
2707 12:43:12.606442 Set Vref, RX VrefLevel [Byte0]: 42
2708 12:43:12.609545 [Byte1]: 42
2709 12:43:12.609632
2710 12:43:12.613143 Set Vref, RX VrefLevel [Byte0]: 43
2711 12:43:12.615846 [Byte1]: 43
2712 12:43:12.620779
2713 12:43:12.620861 Set Vref, RX VrefLevel [Byte0]: 44
2714 12:43:12.623611 [Byte1]: 44
2715 12:43:12.628191
2716 12:43:12.628272 Set Vref, RX VrefLevel [Byte0]: 45
2717 12:43:12.631284 [Byte1]: 45
2718 12:43:12.635904
2719 12:43:12.636012 Set Vref, RX VrefLevel [Byte0]: 46
2720 12:43:12.639356 [Byte1]: 46
2721 12:43:12.644250
2722 12:43:12.644332 Set Vref, RX VrefLevel [Byte0]: 47
2723 12:43:12.647123 [Byte1]: 47
2724 12:43:12.651706
2725 12:43:12.651788 Set Vref, RX VrefLevel [Byte0]: 48
2726 12:43:12.655053 [Byte1]: 48
2727 12:43:12.659665
2728 12:43:12.659746 Set Vref, RX VrefLevel [Byte0]: 49
2729 12:43:12.663119 [Byte1]: 49
2730 12:43:12.667862
2731 12:43:12.667969 Set Vref, RX VrefLevel [Byte0]: 50
2732 12:43:12.671015 [Byte1]: 50
2733 12:43:12.675591
2734 12:43:12.675697 Set Vref, RX VrefLevel [Byte0]: 51
2735 12:43:12.679103 [Byte1]: 51
2736 12:43:12.683441
2737 12:43:12.683548 Set Vref, RX VrefLevel [Byte0]: 52
2738 12:43:12.687135 [Byte1]: 52
2739 12:43:12.691232
2740 12:43:12.691316 Set Vref, RX VrefLevel [Byte0]: 53
2741 12:43:12.694987 [Byte1]: 53
2742 12:43:12.699859
2743 12:43:12.699933 Set Vref, RX VrefLevel [Byte0]: 54
2744 12:43:12.702565 [Byte1]: 54
2745 12:43:12.707437
2746 12:43:12.707518 Set Vref, RX VrefLevel [Byte0]: 55
2747 12:43:12.711359 [Byte1]: 55
2748 12:43:12.715439
2749 12:43:12.715518 Set Vref, RX VrefLevel [Byte0]: 56
2750 12:43:12.718735 [Byte1]: 56
2751 12:43:12.723522
2752 12:43:12.723602 Set Vref, RX VrefLevel [Byte0]: 57
2753 12:43:12.726519 [Byte1]: 57
2754 12:43:12.731234
2755 12:43:12.731313 Set Vref, RX VrefLevel [Byte0]: 58
2756 12:43:12.734326 [Byte1]: 58
2757 12:43:12.739121
2758 12:43:12.739201 Set Vref, RX VrefLevel [Byte0]: 59
2759 12:43:12.742370 [Byte1]: 59
2760 12:43:12.746757
2761 12:43:12.746837 Set Vref, RX VrefLevel [Byte0]: 60
2762 12:43:12.750717 [Byte1]: 60
2763 12:43:12.754672
2764 12:43:12.754752 Set Vref, RX VrefLevel [Byte0]: 61
2765 12:43:12.758169 [Byte1]: 61
2766 12:43:12.762950
2767 12:43:12.763032 Set Vref, RX VrefLevel [Byte0]: 62
2768 12:43:12.766065 [Byte1]: 62
2769 12:43:12.770635
2770 12:43:12.770714 Set Vref, RX VrefLevel [Byte0]: 63
2771 12:43:12.774116 [Byte1]: 63
2772 12:43:12.778554
2773 12:43:12.778634 Set Vref, RX VrefLevel [Byte0]: 64
2774 12:43:12.782226 [Byte1]: 64
2775 12:43:12.786958
2776 12:43:12.787038 Set Vref, RX VrefLevel [Byte0]: 65
2777 12:43:12.789839 [Byte1]: 65
2778 12:43:12.794528
2779 12:43:12.794608 Set Vref, RX VrefLevel [Byte0]: 66
2780 12:43:12.797811 [Byte1]: 66
2781 12:43:12.802484
2782 12:43:12.802564 Set Vref, RX VrefLevel [Byte0]: 67
2783 12:43:12.805547 [Byte1]: 67
2784 12:43:12.810133
2785 12:43:12.810213 Set Vref, RX VrefLevel [Byte0]: 68
2786 12:43:12.813515 [Byte1]: 68
2787 12:43:12.818453
2788 12:43:12.818533 Set Vref, RX VrefLevel [Byte0]: 69
2789 12:43:12.821451 [Byte1]: 69
2790 12:43:12.826614
2791 12:43:12.826694 Set Vref, RX VrefLevel [Byte0]: 70
2792 12:43:12.829551 [Byte1]: 70
2793 12:43:12.834499
2794 12:43:12.834579 Final RX Vref Byte 0 = 52 to rank0
2795 12:43:12.837789 Final RX Vref Byte 1 = 60 to rank0
2796 12:43:12.840668 Final RX Vref Byte 0 = 52 to rank1
2797 12:43:12.844000 Final RX Vref Byte 1 = 60 to rank1==
2798 12:43:12.847507 Dram Type= 6, Freq= 0, CH_0, rank 0
2799 12:43:12.853860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2800 12:43:12.853941 ==
2801 12:43:12.854005 DQS Delay:
2802 12:43:12.854063 DQS0 = 0, DQS1 = 0
2803 12:43:12.857929 DQM Delay:
2804 12:43:12.858009 DQM0 = 117, DQM1 = 105
2805 12:43:12.860511 DQ Delay:
2806 12:43:12.864242 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2807 12:43:12.867596 DQ4 =118, DQ5 =110, DQ6 =126, DQ7 =122
2808 12:43:12.870699 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2809 12:43:12.873675 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2810 12:43:12.873755
2811 12:43:12.873818
2812 12:43:12.883484 [DQSOSCAuto] RK0, (LSB)MR18= 0x500, (MSB)MR19= 0x404, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
2813 12:43:12.883599 CH0 RK0: MR19=404, MR18=500
2814 12:43:12.890197 CH0_RK0: MR19=0x404, MR18=0x500, DQSOSC=408, MR23=63, INC=39, DEC=26
2815 12:43:12.890278
2816 12:43:12.893661 ----->DramcWriteLeveling(PI) begin...
2817 12:43:12.893758 ==
2818 12:43:12.896909 Dram Type= 6, Freq= 0, CH_0, rank 1
2819 12:43:12.900476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2820 12:43:12.904224 ==
2821 12:43:12.906758 Write leveling (Byte 0): 30 => 30
2822 12:43:12.906841 Write leveling (Byte 1): 25 => 25
2823 12:43:12.910314 DramcWriteLeveling(PI) end<-----
2824 12:43:12.910395
2825 12:43:12.910458 ==
2826 12:43:12.913801 Dram Type= 6, Freq= 0, CH_0, rank 1
2827 12:43:12.920236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2828 12:43:12.920316 ==
2829 12:43:12.923606 [Gating] SW mode calibration
2830 12:43:12.930106 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2831 12:43:12.933296 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2832 12:43:12.939904 0 15 0 | B1->B0 | 2524 3434 | 1 1 | (0 0) (1 1)
2833 12:43:12.943548 0 15 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2834 12:43:12.947229 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2835 12:43:12.953514 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2836 12:43:12.956774 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2837 12:43:12.960347 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2838 12:43:12.966487 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2839 12:43:12.970309 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
2840 12:43:12.973516 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
2841 12:43:12.980208 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2842 12:43:12.983667 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2843 12:43:12.986381 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2844 12:43:12.993611 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2845 12:43:12.996158 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2846 12:43:12.999539 1 0 24 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
2847 12:43:13.003380 1 0 28 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
2848 12:43:13.009796 1 1 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2849 12:43:13.012920 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2850 12:43:13.016285 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2851 12:43:13.023240 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2852 12:43:13.026267 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2853 12:43:13.029786 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 12:43:13.036147 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2855 12:43:13.039219 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2856 12:43:13.042789 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2857 12:43:13.049676 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2858 12:43:13.052930 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 12:43:13.056292 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 12:43:13.062694 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 12:43:13.066191 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 12:43:13.069917 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 12:43:13.076007 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 12:43:13.079779 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 12:43:13.083252 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 12:43:13.089133 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 12:43:13.092639 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 12:43:13.095844 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 12:43:13.102236 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 12:43:13.105992 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2871 12:43:13.109115 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2872 12:43:13.115662 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2873 12:43:13.115742 Total UI for P1: 0, mck2ui 16
2874 12:43:13.122610 best dqsien dly found for B0: ( 1, 3, 26)
2875 12:43:13.126096 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 12:43:13.128841 Total UI for P1: 0, mck2ui 16
2877 12:43:13.132278 best dqsien dly found for B1: ( 1, 4, 0)
2878 12:43:13.135248 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2879 12:43:13.138645 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2880 12:43:13.138725
2881 12:43:13.142066 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2882 12:43:13.145495 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2883 12:43:13.148984 [Gating] SW calibration Done
2884 12:43:13.149065 ==
2885 12:43:13.152392 Dram Type= 6, Freq= 0, CH_0, rank 1
2886 12:43:13.155235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2887 12:43:13.159026 ==
2888 12:43:13.159106 RX Vref Scan: 0
2889 12:43:13.159170
2890 12:43:13.161759 RX Vref 0 -> 0, step: 1
2891 12:43:13.161839
2892 12:43:13.164968 RX Delay -40 -> 252, step: 8
2893 12:43:13.168349 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2894 12:43:13.172417 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2895 12:43:13.175287 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2896 12:43:13.179223 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2897 12:43:13.185305 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2898 12:43:13.188874 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2899 12:43:13.191945 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2900 12:43:13.194761 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2901 12:43:13.198669 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2902 12:43:13.202182 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2903 12:43:13.208179 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2904 12:43:13.211621 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2905 12:43:13.214973 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2906 12:43:13.218358 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2907 12:43:13.224862 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2908 12:43:13.228193 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2909 12:43:13.228274 ==
2910 12:43:13.231965 Dram Type= 6, Freq= 0, CH_0, rank 1
2911 12:43:13.234861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2912 12:43:13.234942 ==
2913 12:43:13.238333 DQS Delay:
2914 12:43:13.238414 DQS0 = 0, DQS1 = 0
2915 12:43:13.238477 DQM Delay:
2916 12:43:13.241648 DQM0 = 115, DQM1 = 109
2917 12:43:13.241729 DQ Delay:
2918 12:43:13.244488 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =111
2919 12:43:13.247988 DQ4 =119, DQ5 =107, DQ6 =127, DQ7 =119
2920 12:43:13.251176 DQ8 =99, DQ9 =91, DQ10 =111, DQ11 =103
2921 12:43:13.258359 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =115
2922 12:43:13.258443
2923 12:43:13.258507
2924 12:43:13.258565 ==
2925 12:43:13.261127 Dram Type= 6, Freq= 0, CH_0, rank 1
2926 12:43:13.264813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2927 12:43:13.264894 ==
2928 12:43:13.264957
2929 12:43:13.265015
2930 12:43:13.267912 TX Vref Scan disable
2931 12:43:13.268018 == TX Byte 0 ==
2932 12:43:13.274261 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2933 12:43:13.278227 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2934 12:43:13.278308 == TX Byte 1 ==
2935 12:43:13.284409 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2936 12:43:13.287488 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2937 12:43:13.287569 ==
2938 12:43:13.291581 Dram Type= 6, Freq= 0, CH_0, rank 1
2939 12:43:13.294430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2940 12:43:13.294511 ==
2941 12:43:13.307465 TX Vref=22, minBit 2, minWin=25, winSum=416
2942 12:43:13.310877 TX Vref=24, minBit 4, minWin=25, winSum=419
2943 12:43:13.314474 TX Vref=26, minBit 3, minWin=25, winSum=419
2944 12:43:13.317495 TX Vref=28, minBit 2, minWin=26, winSum=429
2945 12:43:13.320910 TX Vref=30, minBit 1, minWin=26, winSum=426
2946 12:43:13.328012 TX Vref=32, minBit 10, minWin=25, winSum=423
2947 12:43:13.330678 [TxChooseVref] Worse bit 2, Min win 26, Win sum 429, Final Vref 28
2948 12:43:13.330759
2949 12:43:13.333962 Final TX Range 1 Vref 28
2950 12:43:13.334043
2951 12:43:13.334106 ==
2952 12:43:13.337505 Dram Type= 6, Freq= 0, CH_0, rank 1
2953 12:43:13.340717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2954 12:43:13.343544 ==
2955 12:43:13.343623
2956 12:43:13.343687
2957 12:43:13.343745 TX Vref Scan disable
2958 12:43:13.347582 == TX Byte 0 ==
2959 12:43:13.350522 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2960 12:43:13.357741 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2961 12:43:13.357822 == TX Byte 1 ==
2962 12:43:13.360730 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2963 12:43:13.367432 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2964 12:43:13.367513
2965 12:43:13.367577 [DATLAT]
2966 12:43:13.367636 Freq=1200, CH0 RK1
2967 12:43:13.367693
2968 12:43:13.370737 DATLAT Default: 0xd
2969 12:43:13.370817 0, 0xFFFF, sum = 0
2970 12:43:13.374273 1, 0xFFFF, sum = 0
2971 12:43:13.377459 2, 0xFFFF, sum = 0
2972 12:43:13.377541 3, 0xFFFF, sum = 0
2973 12:43:13.380694 4, 0xFFFF, sum = 0
2974 12:43:13.380776 5, 0xFFFF, sum = 0
2975 12:43:13.384154 6, 0xFFFF, sum = 0
2976 12:43:13.384236 7, 0xFFFF, sum = 0
2977 12:43:13.387593 8, 0xFFFF, sum = 0
2978 12:43:13.387674 9, 0xFFFF, sum = 0
2979 12:43:13.390979 10, 0xFFFF, sum = 0
2980 12:43:13.391060 11, 0xFFFF, sum = 0
2981 12:43:13.394306 12, 0x0, sum = 1
2982 12:43:13.394388 13, 0x0, sum = 2
2983 12:43:13.397460 14, 0x0, sum = 3
2984 12:43:13.397542 15, 0x0, sum = 4
2985 12:43:13.400287 best_step = 13
2986 12:43:13.400366
2987 12:43:13.400429 ==
2988 12:43:13.403913 Dram Type= 6, Freq= 0, CH_0, rank 1
2989 12:43:13.407475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2990 12:43:13.407556 ==
2991 12:43:13.407620 RX Vref Scan: 0
2992 12:43:13.407678
2993 12:43:13.410209 RX Vref 0 -> 0, step: 1
2994 12:43:13.410290
2995 12:43:13.413686 RX Delay -21 -> 252, step: 4
2996 12:43:13.417351 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
2997 12:43:13.423692 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
2998 12:43:13.427357 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
2999 12:43:13.430676 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3000 12:43:13.433800 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3001 12:43:13.437001 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
3002 12:43:13.443724 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3003 12:43:13.446795 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3004 12:43:13.450064 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3005 12:43:13.453519 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3006 12:43:13.456708 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3007 12:43:13.463470 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3008 12:43:13.466908 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3009 12:43:13.469757 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3010 12:43:13.473144 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3011 12:43:13.480002 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3012 12:43:13.480097 ==
3013 12:43:13.483103 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 12:43:13.486674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 12:43:13.486756 ==
3016 12:43:13.486821 DQS Delay:
3017 12:43:13.490049 DQS0 = 0, DQS1 = 0
3018 12:43:13.490130 DQM Delay:
3019 12:43:13.493105 DQM0 = 115, DQM1 = 106
3020 12:43:13.493185 DQ Delay:
3021 12:43:13.496775 DQ0 =114, DQ1 =116, DQ2 =110, DQ3 =112
3022 12:43:13.499622 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =122
3023 12:43:13.502935 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =102
3024 12:43:13.506766 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3025 12:43:13.506847
3026 12:43:13.506911
3027 12:43:13.516448 [DQSOSCAuto] RK1, (LSB)MR18= 0xfaf8, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 412 ps
3028 12:43:13.519925 CH0 RK1: MR19=303, MR18=FAF8
3029 12:43:13.523515 CH0_RK1: MR19=0x303, MR18=0xFAF8, DQSOSC=412, MR23=63, INC=38, DEC=25
3030 12:43:13.526682 [RxdqsGatingPostProcess] freq 1200
3031 12:43:13.532910 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3032 12:43:13.536180 best DQS0 dly(2T, 0.5T) = (0, 11)
3033 12:43:13.539265 best DQS1 dly(2T, 0.5T) = (0, 12)
3034 12:43:13.543273 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3035 12:43:13.546466 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3036 12:43:13.549745 best DQS0 dly(2T, 0.5T) = (0, 11)
3037 12:43:13.552823 best DQS1 dly(2T, 0.5T) = (0, 12)
3038 12:43:13.556160 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3039 12:43:13.559819 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3040 12:43:13.562957 Pre-setting of DQS Precalculation
3041 12:43:13.566242 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3042 12:43:13.566323 ==
3043 12:43:13.569795 Dram Type= 6, Freq= 0, CH_1, rank 0
3044 12:43:13.572627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3045 12:43:13.572710 ==
3046 12:43:13.579062 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3047 12:43:13.585699 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3048 12:43:13.593576 [CA 0] Center 38 (8~68) winsize 61
3049 12:43:13.597045 [CA 1] Center 37 (7~68) winsize 62
3050 12:43:13.600719 [CA 2] Center 35 (5~65) winsize 61
3051 12:43:13.603836 [CA 3] Center 34 (4~64) winsize 61
3052 12:43:13.606949 [CA 4] Center 34 (4~64) winsize 61
3053 12:43:13.610024 [CA 5] Center 33 (4~63) winsize 60
3054 12:43:13.610106
3055 12:43:13.613507 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3056 12:43:13.613588
3057 12:43:13.617173 [CATrainingPosCal] consider 1 rank data
3058 12:43:13.620275 u2DelayCellTimex100 = 270/100 ps
3059 12:43:13.623731 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3060 12:43:13.627368 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3061 12:43:13.634335 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3062 12:43:13.637197 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3063 12:43:13.640655 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3064 12:43:13.643518 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3065 12:43:13.643621
3066 12:43:13.646737 CA PerBit enable=1, Macro0, CA PI delay=33
3067 12:43:13.646832
3068 12:43:13.650240 [CBTSetCACLKResult] CA Dly = 33
3069 12:43:13.650333 CS Dly: 5 (0~36)
3070 12:43:13.653056 ==
3071 12:43:13.656529 Dram Type= 6, Freq= 0, CH_1, rank 1
3072 12:43:13.659915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3073 12:43:13.659995 ==
3074 12:43:13.663241 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3075 12:43:13.669627 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3076 12:43:13.679518 [CA 0] Center 37 (7~68) winsize 62
3077 12:43:13.682501 [CA 1] Center 38 (8~68) winsize 61
3078 12:43:13.686197 [CA 2] Center 35 (5~65) winsize 61
3079 12:43:13.689087 [CA 3] Center 33 (3~64) winsize 62
3080 12:43:13.692314 [CA 4] Center 34 (4~64) winsize 61
3081 12:43:13.695673 [CA 5] Center 33 (3~63) winsize 61
3082 12:43:13.695753
3083 12:43:13.699218 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3084 12:43:13.699299
3085 12:43:13.702900 [CATrainingPosCal] consider 2 rank data
3086 12:43:13.705722 u2DelayCellTimex100 = 270/100 ps
3087 12:43:13.709223 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3088 12:43:13.715634 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3089 12:43:13.718839 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3090 12:43:13.722213 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3091 12:43:13.726226 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3092 12:43:13.729228 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3093 12:43:13.729308
3094 12:43:13.732464 CA PerBit enable=1, Macro0, CA PI delay=33
3095 12:43:13.732544
3096 12:43:13.736338 [CBTSetCACLKResult] CA Dly = 33
3097 12:43:13.736419 CS Dly: 6 (0~39)
3098 12:43:13.739134
3099 12:43:13.742144 ----->DramcWriteLeveling(PI) begin...
3100 12:43:13.742225 ==
3101 12:43:13.746529 Dram Type= 6, Freq= 0, CH_1, rank 0
3102 12:43:13.749074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3103 12:43:13.749155 ==
3104 12:43:13.752490 Write leveling (Byte 0): 25 => 25
3105 12:43:13.755899 Write leveling (Byte 1): 25 => 25
3106 12:43:13.759136 DramcWriteLeveling(PI) end<-----
3107 12:43:13.759217
3108 12:43:13.759279 ==
3109 12:43:13.762274 Dram Type= 6, Freq= 0, CH_1, rank 0
3110 12:43:13.765443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3111 12:43:13.765525 ==
3112 12:43:13.769121 [Gating] SW mode calibration
3113 12:43:13.775326 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3114 12:43:13.782182 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3115 12:43:13.785337 0 15 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
3116 12:43:13.788897 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3117 12:43:13.795600 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3118 12:43:13.799195 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3119 12:43:13.802219 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3120 12:43:13.808501 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3121 12:43:13.812062 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
3122 12:43:13.815142 0 15 28 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (1 0)
3123 12:43:13.821827 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3124 12:43:13.825349 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3125 12:43:13.828967 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3126 12:43:13.834780 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 12:43:13.838287 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 12:43:13.842182 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 12:43:13.845476 1 0 24 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (1 1)
3130 12:43:13.852189 1 0 28 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
3131 12:43:13.855456 1 1 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3132 12:43:13.858494 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3133 12:43:13.865492 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 12:43:13.868643 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 12:43:13.871964 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 12:43:13.878513 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 12:43:13.881649 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3138 12:43:13.884674 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3139 12:43:13.891769 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3140 12:43:13.895018 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 12:43:13.898374 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 12:43:13.904718 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 12:43:13.908288 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 12:43:13.912151 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 12:43:13.918436 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 12:43:13.921266 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 12:43:13.925209 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 12:43:13.931853 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 12:43:13.934475 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 12:43:13.938311 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 12:43:13.944231 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 12:43:13.948242 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 12:43:13.951020 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3154 12:43:13.957740 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3155 12:43:13.957834 Total UI for P1: 0, mck2ui 16
3156 12:43:13.964582 best dqsien dly found for B0: ( 1, 3, 24)
3157 12:43:13.967775 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 12:43:13.971350 Total UI for P1: 0, mck2ui 16
3159 12:43:13.974126 best dqsien dly found for B1: ( 1, 3, 28)
3160 12:43:13.977630 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3161 12:43:13.981045 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3162 12:43:13.981127
3163 12:43:13.984202 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3164 12:43:13.987309 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3165 12:43:13.990867 [Gating] SW calibration Done
3166 12:43:13.990948 ==
3167 12:43:13.994457 Dram Type= 6, Freq= 0, CH_1, rank 0
3168 12:43:13.997866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3169 12:43:14.000565 ==
3170 12:43:14.000646 RX Vref Scan: 0
3171 12:43:14.000711
3172 12:43:14.004379 RX Vref 0 -> 0, step: 1
3173 12:43:14.004460
3174 12:43:14.007461 RX Delay -40 -> 252, step: 8
3175 12:43:14.011149 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3176 12:43:14.014185 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3177 12:43:14.017707 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3178 12:43:14.020602 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3179 12:43:14.027318 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3180 12:43:14.030693 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3181 12:43:14.034167 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3182 12:43:14.037482 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3183 12:43:14.040869 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3184 12:43:14.044015 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3185 12:43:14.050286 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3186 12:43:14.053915 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3187 12:43:14.057192 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3188 12:43:14.060409 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3189 12:43:14.067399 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3190 12:43:14.070592 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3191 12:43:14.070673 ==
3192 12:43:14.073777 Dram Type= 6, Freq= 0, CH_1, rank 0
3193 12:43:14.077817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3194 12:43:14.077899 ==
3195 12:43:14.081124 DQS Delay:
3196 12:43:14.081205 DQS0 = 0, DQS1 = 0
3197 12:43:14.081269 DQM Delay:
3198 12:43:14.083790 DQM0 = 116, DQM1 = 113
3199 12:43:14.083871 DQ Delay:
3200 12:43:14.086911 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =119
3201 12:43:14.090456 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3202 12:43:14.093823 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3203 12:43:14.100686 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3204 12:43:14.100768
3205 12:43:14.100832
3206 12:43:14.100892 ==
3207 12:43:14.103510 Dram Type= 6, Freq= 0, CH_1, rank 0
3208 12:43:14.107291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3209 12:43:14.107372 ==
3210 12:43:14.107437
3211 12:43:14.107497
3212 12:43:14.110238 TX Vref Scan disable
3213 12:43:14.110319 == TX Byte 0 ==
3214 12:43:14.117435 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3215 12:43:14.120215 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3216 12:43:14.120297 == TX Byte 1 ==
3217 12:43:14.126985 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3218 12:43:14.129716 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3219 12:43:14.129797 ==
3220 12:43:14.133668 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 12:43:14.136556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 12:43:14.136638 ==
3223 12:43:14.149084 TX Vref=22, minBit 9, minWin=23, winSum=404
3224 12:43:14.152954 TX Vref=24, minBit 9, minWin=24, winSum=409
3225 12:43:14.156228 TX Vref=26, minBit 9, minWin=24, winSum=416
3226 12:43:14.159301 TX Vref=28, minBit 9, minWin=24, winSum=422
3227 12:43:14.162622 TX Vref=30, minBit 9, minWin=25, winSum=425
3228 12:43:14.169887 TX Vref=32, minBit 9, minWin=25, winSum=420
3229 12:43:14.172515 [TxChooseVref] Worse bit 9, Min win 25, Win sum 425, Final Vref 30
3230 12:43:14.172598
3231 12:43:14.175784 Final TX Range 1 Vref 30
3232 12:43:14.175866
3233 12:43:14.175930 ==
3234 12:43:14.178984 Dram Type= 6, Freq= 0, CH_1, rank 0
3235 12:43:14.182101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3236 12:43:14.182213 ==
3237 12:43:14.185597
3238 12:43:14.185678
3239 12:43:14.185743 TX Vref Scan disable
3240 12:43:14.188799 == TX Byte 0 ==
3241 12:43:14.192158 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3242 12:43:14.195731 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3243 12:43:14.198778 == TX Byte 1 ==
3244 12:43:14.202364 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3245 12:43:14.208647 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3246 12:43:14.208729
3247 12:43:14.208793 [DATLAT]
3248 12:43:14.208852 Freq=1200, CH1 RK0
3249 12:43:14.208909
3250 12:43:14.211995 DATLAT Default: 0xd
3251 12:43:14.212081 0, 0xFFFF, sum = 0
3252 12:43:14.215487 1, 0xFFFF, sum = 0
3253 12:43:14.215569 2, 0xFFFF, sum = 0
3254 12:43:14.218863 3, 0xFFFF, sum = 0
3255 12:43:14.222728 4, 0xFFFF, sum = 0
3256 12:43:14.222810 5, 0xFFFF, sum = 0
3257 12:43:14.225646 6, 0xFFFF, sum = 0
3258 12:43:14.225727 7, 0xFFFF, sum = 0
3259 12:43:14.228941 8, 0xFFFF, sum = 0
3260 12:43:14.229022 9, 0xFFFF, sum = 0
3261 12:43:14.231888 10, 0xFFFF, sum = 0
3262 12:43:14.231970 11, 0xFFFF, sum = 0
3263 12:43:14.235291 12, 0x0, sum = 1
3264 12:43:14.235372 13, 0x0, sum = 2
3265 12:43:14.238678 14, 0x0, sum = 3
3266 12:43:14.238759 15, 0x0, sum = 4
3267 12:43:14.241735 best_step = 13
3268 12:43:14.241814
3269 12:43:14.241877 ==
3270 12:43:14.245890 Dram Type= 6, Freq= 0, CH_1, rank 0
3271 12:43:14.248662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3272 12:43:14.248742 ==
3273 12:43:14.248806 RX Vref Scan: 1
3274 12:43:14.251820
3275 12:43:14.251900 Set Vref Range= 32 -> 127
3276 12:43:14.251963
3277 12:43:14.254989 RX Vref 32 -> 127, step: 1
3278 12:43:14.255069
3279 12:43:14.258522 RX Delay -13 -> 252, step: 4
3280 12:43:14.258602
3281 12:43:14.261585 Set Vref, RX VrefLevel [Byte0]: 32
3282 12:43:14.264906 [Byte1]: 32
3283 12:43:14.264985
3284 12:43:14.268355 Set Vref, RX VrefLevel [Byte0]: 33
3285 12:43:14.271473 [Byte1]: 33
3286 12:43:14.275212
3287 12:43:14.275292 Set Vref, RX VrefLevel [Byte0]: 34
3288 12:43:14.278866 [Byte1]: 34
3289 12:43:14.283415
3290 12:43:14.283505 Set Vref, RX VrefLevel [Byte0]: 35
3291 12:43:14.286960 [Byte1]: 35
3292 12:43:14.291293
3293 12:43:14.291370 Set Vref, RX VrefLevel [Byte0]: 36
3294 12:43:14.294357 [Byte1]: 36
3295 12:43:14.298920
3296 12:43:14.298999 Set Vref, RX VrefLevel [Byte0]: 37
3297 12:43:14.302374 [Byte1]: 37
3298 12:43:14.306625
3299 12:43:14.306706 Set Vref, RX VrefLevel [Byte0]: 38
3300 12:43:14.309932 [Byte1]: 38
3301 12:43:14.315561
3302 12:43:14.315639 Set Vref, RX VrefLevel [Byte0]: 39
3303 12:43:14.318419 [Byte1]: 39
3304 12:43:14.322797
3305 12:43:14.322874 Set Vref, RX VrefLevel [Byte0]: 40
3306 12:43:14.326417 [Byte1]: 40
3307 12:43:14.330364
3308 12:43:14.330441 Set Vref, RX VrefLevel [Byte0]: 41
3309 12:43:14.333582 [Byte1]: 41
3310 12:43:14.338627
3311 12:43:14.338705 Set Vref, RX VrefLevel [Byte0]: 42
3312 12:43:14.341925 [Byte1]: 42
3313 12:43:14.346077
3314 12:43:14.346155 Set Vref, RX VrefLevel [Byte0]: 43
3315 12:43:14.349544 [Byte1]: 43
3316 12:43:14.354107
3317 12:43:14.354185 Set Vref, RX VrefLevel [Byte0]: 44
3318 12:43:14.357332 [Byte1]: 44
3319 12:43:14.362016
3320 12:43:14.362094 Set Vref, RX VrefLevel [Byte0]: 45
3321 12:43:14.365483 [Byte1]: 45
3322 12:43:14.370682
3323 12:43:14.370760 Set Vref, RX VrefLevel [Byte0]: 46
3324 12:43:14.373546 [Byte1]: 46
3325 12:43:14.379103
3326 12:43:14.379181 Set Vref, RX VrefLevel [Byte0]: 47
3327 12:43:14.381306 [Byte1]: 47
3328 12:43:14.385651
3329 12:43:14.385729 Set Vref, RX VrefLevel [Byte0]: 48
3330 12:43:14.389204 [Byte1]: 48
3331 12:43:14.393523
3332 12:43:14.393601 Set Vref, RX VrefLevel [Byte0]: 49
3333 12:43:14.396695 [Byte1]: 49
3334 12:43:14.401498
3335 12:43:14.401576 Set Vref, RX VrefLevel [Byte0]: 50
3336 12:43:14.404369 [Byte1]: 50
3337 12:43:14.409494
3338 12:43:14.409572 Set Vref, RX VrefLevel [Byte0]: 51
3339 12:43:14.413204 [Byte1]: 51
3340 12:43:14.417048
3341 12:43:14.417126 Set Vref, RX VrefLevel [Byte0]: 52
3342 12:43:14.420765 [Byte1]: 52
3343 12:43:14.426148
3344 12:43:14.426226 Set Vref, RX VrefLevel [Byte0]: 53
3345 12:43:14.428939 [Byte1]: 53
3346 12:43:14.433960
3347 12:43:14.434038 Set Vref, RX VrefLevel [Byte0]: 54
3348 12:43:14.436006 [Byte1]: 54
3349 12:43:14.440546
3350 12:43:14.440624 Set Vref, RX VrefLevel [Byte0]: 55
3351 12:43:14.444159 [Byte1]: 55
3352 12:43:14.448540
3353 12:43:14.448620 Set Vref, RX VrefLevel [Byte0]: 56
3354 12:43:14.451910 [Byte1]: 56
3355 12:43:14.456254
3356 12:43:14.456334 Set Vref, RX VrefLevel [Byte0]: 57
3357 12:43:14.459939 [Byte1]: 57
3358 12:43:14.464335
3359 12:43:14.464414 Set Vref, RX VrefLevel [Byte0]: 58
3360 12:43:14.467808 [Byte1]: 58
3361 12:43:14.472426
3362 12:43:14.472506 Set Vref, RX VrefLevel [Byte0]: 59
3363 12:43:14.475576 [Byte1]: 59
3364 12:43:14.480615
3365 12:43:14.480695 Set Vref, RX VrefLevel [Byte0]: 60
3366 12:43:14.483681 [Byte1]: 60
3367 12:43:14.487978
3368 12:43:14.488079 Set Vref, RX VrefLevel [Byte0]: 61
3369 12:43:14.491378 [Byte1]: 61
3370 12:43:14.495912
3371 12:43:14.496018 Set Vref, RX VrefLevel [Byte0]: 62
3372 12:43:14.498991 [Byte1]: 62
3373 12:43:14.504186
3374 12:43:14.504266 Set Vref, RX VrefLevel [Byte0]: 63
3375 12:43:14.506799 [Byte1]: 63
3376 12:43:14.511524
3377 12:43:14.511604 Set Vref, RX VrefLevel [Byte0]: 64
3378 12:43:14.514669 [Byte1]: 64
3379 12:43:14.519932
3380 12:43:14.520061 Set Vref, RX VrefLevel [Byte0]: 65
3381 12:43:14.522794 [Byte1]: 65
3382 12:43:14.527497
3383 12:43:14.527577 Final RX Vref Byte 0 = 53 to rank0
3384 12:43:14.530888 Final RX Vref Byte 1 = 48 to rank0
3385 12:43:14.534016 Final RX Vref Byte 0 = 53 to rank1
3386 12:43:14.537503 Final RX Vref Byte 1 = 48 to rank1==
3387 12:43:14.540687 Dram Type= 6, Freq= 0, CH_1, rank 0
3388 12:43:14.547128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3389 12:43:14.547209 ==
3390 12:43:14.547274 DQS Delay:
3391 12:43:14.547333 DQS0 = 0, DQS1 = 0
3392 12:43:14.550735 DQM Delay:
3393 12:43:14.550803 DQM0 = 115, DQM1 = 111
3394 12:43:14.553990 DQ Delay:
3395 12:43:14.557451 DQ0 =122, DQ1 =112, DQ2 =106, DQ3 =114
3396 12:43:14.560806 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3397 12:43:14.564068 DQ8 =96, DQ9 =102, DQ10 =112, DQ11 =106
3398 12:43:14.567059 DQ12 =120, DQ13 =118, DQ14 =118, DQ15 =120
3399 12:43:14.567138
3400 12:43:14.567201
3401 12:43:14.577447 [DQSOSCAuto] RK0, (LSB)MR18= 0xf501, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 414 ps
3402 12:43:14.577529 CH1 RK0: MR19=304, MR18=F501
3403 12:43:14.583720 CH1_RK0: MR19=0x304, MR18=0xF501, DQSOSC=409, MR23=63, INC=39, DEC=26
3404 12:43:14.583801
3405 12:43:14.587298 ----->DramcWriteLeveling(PI) begin...
3406 12:43:14.587405 ==
3407 12:43:14.590914 Dram Type= 6, Freq= 0, CH_1, rank 1
3408 12:43:14.597116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3409 12:43:14.597206 ==
3410 12:43:14.600264 Write leveling (Byte 0): 24 => 24
3411 12:43:14.600345 Write leveling (Byte 1): 28 => 28
3412 12:43:14.603760 DramcWriteLeveling(PI) end<-----
3413 12:43:14.603840
3414 12:43:14.603903 ==
3415 12:43:14.607035 Dram Type= 6, Freq= 0, CH_1, rank 1
3416 12:43:14.614280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3417 12:43:14.614361 ==
3418 12:43:14.617120 [Gating] SW mode calibration
3419 12:43:14.623527 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3420 12:43:14.626974 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3421 12:43:14.633326 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3422 12:43:14.636660 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3423 12:43:14.640306 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3424 12:43:14.646656 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3425 12:43:14.650423 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3426 12:43:14.653344 0 15 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
3427 12:43:14.660197 0 15 24 | B1->B0 | 3434 2424 | 0 0 | (0 0) (0 0)
3428 12:43:14.663243 0 15 28 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
3429 12:43:14.666705 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3430 12:43:14.673594 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3431 12:43:14.677735 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3432 12:43:14.680001 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3433 12:43:14.683127 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3434 12:43:14.690037 1 0 20 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
3435 12:43:14.694200 1 0 24 | B1->B0 | 2424 4646 | 0 0 | (1 1) (0 0)
3436 12:43:14.696961 1 0 28 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
3437 12:43:14.703349 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3438 12:43:14.706726 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3439 12:43:14.710243 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3440 12:43:14.716919 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3441 12:43:14.719611 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3442 12:43:14.723090 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3443 12:43:14.729697 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3444 12:43:14.732925 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3445 12:43:14.736582 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3446 12:43:14.742604 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3447 12:43:14.746068 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3448 12:43:14.752634 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3449 12:43:14.755929 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3450 12:43:14.759276 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3451 12:43:14.765969 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3452 12:43:14.770004 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3453 12:43:14.772526 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3454 12:43:14.778825 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3455 12:43:14.782155 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 12:43:14.785523 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 12:43:14.791699 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 12:43:14.795394 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3459 12:43:14.798365 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3460 12:43:14.801834 Total UI for P1: 0, mck2ui 16
3461 12:43:14.805216 best dqsien dly found for B0: ( 1, 3, 20)
3462 12:43:14.808568 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3463 12:43:14.814976 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 12:43:14.819117 Total UI for P1: 0, mck2ui 16
3465 12:43:14.821406 best dqsien dly found for B1: ( 1, 3, 26)
3466 12:43:14.824849 best DQS0 dly(MCK, UI, PI) = (1, 3, 20)
3467 12:43:14.828405 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3468 12:43:14.828486
3469 12:43:14.831686 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 20)
3470 12:43:14.834903 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3471 12:43:14.838533 [Gating] SW calibration Done
3472 12:43:14.838653 ==
3473 12:43:14.841390 Dram Type= 6, Freq= 0, CH_1, rank 1
3474 12:43:14.844701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3475 12:43:14.844786 ==
3476 12:43:14.847853 RX Vref Scan: 0
3477 12:43:14.847959
3478 12:43:14.851269 RX Vref 0 -> 0, step: 1
3479 12:43:14.851349
3480 12:43:14.851413 RX Delay -40 -> 252, step: 8
3481 12:43:14.857879 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3482 12:43:14.861470 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3483 12:43:14.864908 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3484 12:43:14.867717 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3485 12:43:14.875377 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3486 12:43:14.878198 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3487 12:43:14.880790 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3488 12:43:14.884363 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3489 12:43:14.887578 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3490 12:43:14.890678 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3491 12:43:14.897561 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3492 12:43:14.900973 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3493 12:43:14.904164 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3494 12:43:14.907902 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3495 12:43:14.913913 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3496 12:43:14.917777 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3497 12:43:14.917858 ==
3498 12:43:14.920331 Dram Type= 6, Freq= 0, CH_1, rank 1
3499 12:43:14.923603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3500 12:43:14.923685 ==
3501 12:43:14.927332 DQS Delay:
3502 12:43:14.927414 DQS0 = 0, DQS1 = 0
3503 12:43:14.930414 DQM Delay:
3504 12:43:14.930495 DQM0 = 115, DQM1 = 111
3505 12:43:14.930577 DQ Delay:
3506 12:43:14.934144 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3507 12:43:14.939916 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3508 12:43:14.943540 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3509 12:43:14.946708 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3510 12:43:14.946852
3511 12:43:14.946948
3512 12:43:14.947040 ==
3513 12:43:14.949709 Dram Type= 6, Freq= 0, CH_1, rank 1
3514 12:43:14.953144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3515 12:43:14.953252 ==
3516 12:43:14.953344
3517 12:43:14.953432
3518 12:43:14.956349 TX Vref Scan disable
3519 12:43:14.960141 == TX Byte 0 ==
3520 12:43:14.963694 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3521 12:43:14.966455 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3522 12:43:14.969699 == TX Byte 1 ==
3523 12:43:14.972727 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3524 12:43:14.975991 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3525 12:43:14.976157 ==
3526 12:43:14.979967 Dram Type= 6, Freq= 0, CH_1, rank 1
3527 12:43:14.986781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3528 12:43:14.986885 ==
3529 12:43:14.996481 TX Vref=22, minBit 2, minWin=25, winSum=419
3530 12:43:14.999940 TX Vref=24, minBit 2, minWin=25, winSum=423
3531 12:43:15.003158 TX Vref=26, minBit 3, minWin=26, winSum=429
3532 12:43:15.006378 TX Vref=28, minBit 3, minWin=26, winSum=430
3533 12:43:15.009616 TX Vref=30, minBit 9, minWin=26, winSum=433
3534 12:43:15.016267 TX Vref=32, minBit 8, minWin=26, winSum=432
3535 12:43:15.019856 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 30
3536 12:43:15.019954
3537 12:43:15.022744 Final TX Range 1 Vref 30
3538 12:43:15.022822
3539 12:43:15.022884 ==
3540 12:43:15.026372 Dram Type= 6, Freq= 0, CH_1, rank 1
3541 12:43:15.029325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3542 12:43:15.032646 ==
3543 12:43:15.032752
3544 12:43:15.032829
3545 12:43:15.032890 TX Vref Scan disable
3546 12:43:15.036286 == TX Byte 0 ==
3547 12:43:15.039457 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3548 12:43:15.046208 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3549 12:43:15.046424 == TX Byte 1 ==
3550 12:43:15.049144 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3551 12:43:15.056348 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3552 12:43:15.056460
3553 12:43:15.056554 [DATLAT]
3554 12:43:15.056644 Freq=1200, CH1 RK1
3555 12:43:15.056732
3556 12:43:15.059592 DATLAT Default: 0xd
3557 12:43:15.062718 0, 0xFFFF, sum = 0
3558 12:43:15.062829 1, 0xFFFF, sum = 0
3559 12:43:15.065705 2, 0xFFFF, sum = 0
3560 12:43:15.065805 3, 0xFFFF, sum = 0
3561 12:43:15.069293 4, 0xFFFF, sum = 0
3562 12:43:15.069370 5, 0xFFFF, sum = 0
3563 12:43:15.072117 6, 0xFFFF, sum = 0
3564 12:43:15.072219 7, 0xFFFF, sum = 0
3565 12:43:15.075782 8, 0xFFFF, sum = 0
3566 12:43:15.075882 9, 0xFFFF, sum = 0
3567 12:43:15.078776 10, 0xFFFF, sum = 0
3568 12:43:15.078876 11, 0xFFFF, sum = 0
3569 12:43:15.082395 12, 0x0, sum = 1
3570 12:43:15.082477 13, 0x0, sum = 2
3571 12:43:15.085516 14, 0x0, sum = 3
3572 12:43:15.085614 15, 0x0, sum = 4
3573 12:43:15.089115 best_step = 13
3574 12:43:15.089205
3575 12:43:15.089294 ==
3576 12:43:15.092055 Dram Type= 6, Freq= 0, CH_1, rank 1
3577 12:43:15.095708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3578 12:43:15.095824 ==
3579 12:43:15.098488 RX Vref Scan: 0
3580 12:43:15.098576
3581 12:43:15.098637 RX Vref 0 -> 0, step: 1
3582 12:43:15.098695
3583 12:43:15.102016 RX Delay -13 -> 252, step: 4
3584 12:43:15.108821 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3585 12:43:15.112561 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3586 12:43:15.115413 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3587 12:43:15.118329 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3588 12:43:15.124667 iDelay=195, Bit 4, Center 114 (43 ~ 186) 144
3589 12:43:15.128432 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3590 12:43:15.131817 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3591 12:43:15.134500 iDelay=195, Bit 7, Center 110 (39 ~ 182) 144
3592 12:43:15.138273 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3593 12:43:15.144807 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3594 12:43:15.148040 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3595 12:43:15.151725 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3596 12:43:15.154736 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3597 12:43:15.157746 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3598 12:43:15.164179 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3599 12:43:15.167373 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3600 12:43:15.167450 ==
3601 12:43:15.171106 Dram Type= 6, Freq= 0, CH_1, rank 1
3602 12:43:15.174179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3603 12:43:15.174277 ==
3604 12:43:15.177531 DQS Delay:
3605 12:43:15.177632 DQS0 = 0, DQS1 = 0
3606 12:43:15.180824 DQM Delay:
3607 12:43:15.180894 DQM0 = 115, DQM1 = 111
3608 12:43:15.180957 DQ Delay:
3609 12:43:15.187706 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =114
3610 12:43:15.190883 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3611 12:43:15.194259 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3612 12:43:15.197864 DQ12 =118, DQ13 =118, DQ14 =116, DQ15 =120
3613 12:43:15.197961
3614 12:43:15.198051
3615 12:43:15.204294 [DQSOSCAuto] RK1, (LSB)MR18= 0xf507, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
3616 12:43:15.207169 CH1 RK1: MR19=304, MR18=F507
3617 12:43:15.213582 CH1_RK1: MR19=0x304, MR18=0xF507, DQSOSC=407, MR23=63, INC=39, DEC=26
3618 12:43:15.217001 [RxdqsGatingPostProcess] freq 1200
3619 12:43:15.223476 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3620 12:43:15.226665 best DQS0 dly(2T, 0.5T) = (0, 11)
3621 12:43:15.230011 best DQS1 dly(2T, 0.5T) = (0, 11)
3622 12:43:15.233388 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3623 12:43:15.233465 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3624 12:43:15.236637 best DQS0 dly(2T, 0.5T) = (0, 11)
3625 12:43:15.239789 best DQS1 dly(2T, 0.5T) = (0, 11)
3626 12:43:15.243862 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3627 12:43:15.246549 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3628 12:43:15.249895 Pre-setting of DQS Precalculation
3629 12:43:15.256144 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3630 12:43:15.262667 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3631 12:43:15.269438 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3632 12:43:15.269520
3633 12:43:15.269585
3634 12:43:15.272687 [Calibration Summary] 2400 Mbps
3635 12:43:15.276219 CH 0, Rank 0
3636 12:43:15.276301 SW Impedance : PASS
3637 12:43:15.279343 DUTY Scan : NO K
3638 12:43:15.279425 ZQ Calibration : PASS
3639 12:43:15.282667 Jitter Meter : NO K
3640 12:43:15.286146 CBT Training : PASS
3641 12:43:15.286254 Write leveling : PASS
3642 12:43:15.289030 RX DQS gating : PASS
3643 12:43:15.292904 RX DQ/DQS(RDDQC) : PASS
3644 12:43:15.292985 TX DQ/DQS : PASS
3645 12:43:15.295544 RX DATLAT : PASS
3646 12:43:15.299081 RX DQ/DQS(Engine): PASS
3647 12:43:15.299161 TX OE : NO K
3648 12:43:15.302321 All Pass.
3649 12:43:15.302401
3650 12:43:15.302464 CH 0, Rank 1
3651 12:43:15.305969 SW Impedance : PASS
3652 12:43:15.306048 DUTY Scan : NO K
3653 12:43:15.308872 ZQ Calibration : PASS
3654 12:43:15.312155 Jitter Meter : NO K
3655 12:43:15.312235 CBT Training : PASS
3656 12:43:15.315510 Write leveling : PASS
3657 12:43:15.318715 RX DQS gating : PASS
3658 12:43:15.318824 RX DQ/DQS(RDDQC) : PASS
3659 12:43:15.322732 TX DQ/DQS : PASS
3660 12:43:15.325921 RX DATLAT : PASS
3661 12:43:15.326001 RX DQ/DQS(Engine): PASS
3662 12:43:15.329600 TX OE : NO K
3663 12:43:15.329681 All Pass.
3664 12:43:15.329745
3665 12:43:15.332193 CH 1, Rank 0
3666 12:43:15.332273 SW Impedance : PASS
3667 12:43:15.335529 DUTY Scan : NO K
3668 12:43:15.339426 ZQ Calibration : PASS
3669 12:43:15.339507 Jitter Meter : NO K
3670 12:43:15.342116 CBT Training : PASS
3671 12:43:15.345364 Write leveling : PASS
3672 12:43:15.345460 RX DQS gating : PASS
3673 12:43:15.348983 RX DQ/DQS(RDDQC) : PASS
3674 12:43:15.349089 TX DQ/DQS : PASS
3675 12:43:15.352141 RX DATLAT : PASS
3676 12:43:15.355113 RX DQ/DQS(Engine): PASS
3677 12:43:15.355220 TX OE : NO K
3678 12:43:15.358668 All Pass.
3679 12:43:15.358741
3680 12:43:15.358801 CH 1, Rank 1
3681 12:43:15.361848 SW Impedance : PASS
3682 12:43:15.361922 DUTY Scan : NO K
3683 12:43:15.365335 ZQ Calibration : PASS
3684 12:43:15.368296 Jitter Meter : NO K
3685 12:43:15.368367 CBT Training : PASS
3686 12:43:15.371775 Write leveling : PASS
3687 12:43:15.375042 RX DQS gating : PASS
3688 12:43:15.375117 RX DQ/DQS(RDDQC) : PASS
3689 12:43:15.378474 TX DQ/DQS : PASS
3690 12:43:15.381419 RX DATLAT : PASS
3691 12:43:15.381527 RX DQ/DQS(Engine): PASS
3692 12:43:15.385157 TX OE : NO K
3693 12:43:15.385238 All Pass.
3694 12:43:15.385301
3695 12:43:15.387971 DramC Write-DBI off
3696 12:43:15.392152 PER_BANK_REFRESH: Hybrid Mode
3697 12:43:15.392232 TX_TRACKING: ON
3698 12:43:15.402407 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3699 12:43:15.404685 [FAST_K] Save calibration result to emmc
3700 12:43:15.408027 dramc_set_vcore_voltage set vcore to 650000
3701 12:43:15.411238 Read voltage for 600, 5
3702 12:43:15.411318 Vio18 = 0
3703 12:43:15.411381 Vcore = 650000
3704 12:43:15.414716 Vdram = 0
3705 12:43:15.414795 Vddq = 0
3706 12:43:15.414859 Vmddr = 0
3707 12:43:15.421135 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3708 12:43:15.424331 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3709 12:43:15.427967 MEM_TYPE=3, freq_sel=19
3710 12:43:15.431011 sv_algorithm_assistance_LP4_1600
3711 12:43:15.434963 ============ PULL DRAM RESETB DOWN ============
3712 12:43:15.441045 ========== PULL DRAM RESETB DOWN end =========
3713 12:43:15.444786 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3714 12:43:15.448142 ===================================
3715 12:43:15.451167 LPDDR4 DRAM CONFIGURATION
3716 12:43:15.454582 ===================================
3717 12:43:15.454663 EX_ROW_EN[0] = 0x0
3718 12:43:15.458338 EX_ROW_EN[1] = 0x0
3719 12:43:15.458418 LP4Y_EN = 0x0
3720 12:43:15.461199 WORK_FSP = 0x0
3721 12:43:15.461279 WL = 0x2
3722 12:43:15.464328 RL = 0x2
3723 12:43:15.464408 BL = 0x2
3724 12:43:15.468101 RPST = 0x0
3725 12:43:15.471332 RD_PRE = 0x0
3726 12:43:15.471412 WR_PRE = 0x1
3727 12:43:15.473950 WR_PST = 0x0
3728 12:43:15.474030 DBI_WR = 0x0
3729 12:43:15.477029 DBI_RD = 0x0
3730 12:43:15.477110 OTF = 0x1
3731 12:43:15.480342 ===================================
3732 12:43:15.483648 ===================================
3733 12:43:15.487155 ANA top config
3734 12:43:15.490521 ===================================
3735 12:43:15.490601 DLL_ASYNC_EN = 0
3736 12:43:15.493700 ALL_SLAVE_EN = 1
3737 12:43:15.497057 NEW_RANK_MODE = 1
3738 12:43:15.500174 DLL_IDLE_MODE = 1
3739 12:43:15.500255 LP45_APHY_COMB_EN = 1
3740 12:43:15.503440 TX_ODT_DIS = 1
3741 12:43:15.506861 NEW_8X_MODE = 1
3742 12:43:15.510473 ===================================
3743 12:43:15.513255 ===================================
3744 12:43:15.517317 data_rate = 1200
3745 12:43:15.520367 CKR = 1
3746 12:43:15.523410 DQ_P2S_RATIO = 8
3747 12:43:15.526673 ===================================
3748 12:43:15.526754 CA_P2S_RATIO = 8
3749 12:43:15.529659 DQ_CA_OPEN = 0
3750 12:43:15.533054 DQ_SEMI_OPEN = 0
3751 12:43:15.536522 CA_SEMI_OPEN = 0
3752 12:43:15.539993 CA_FULL_RATE = 0
3753 12:43:15.543369 DQ_CKDIV4_EN = 1
3754 12:43:15.543480 CA_CKDIV4_EN = 1
3755 12:43:15.547309 CA_PREDIV_EN = 0
3756 12:43:15.549904 PH8_DLY = 0
3757 12:43:15.552728 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3758 12:43:15.556253 DQ_AAMCK_DIV = 4
3759 12:43:15.559352 CA_AAMCK_DIV = 4
3760 12:43:15.562995 CA_ADMCK_DIV = 4
3761 12:43:15.563076 DQ_TRACK_CA_EN = 0
3762 12:43:15.566384 CA_PICK = 600
3763 12:43:15.569444 CA_MCKIO = 600
3764 12:43:15.573239 MCKIO_SEMI = 0
3765 12:43:15.575822 PLL_FREQ = 2288
3766 12:43:15.579377 DQ_UI_PI_RATIO = 32
3767 12:43:15.582370 CA_UI_PI_RATIO = 0
3768 12:43:15.585738 ===================================
3769 12:43:15.589106 ===================================
3770 12:43:15.589188 memory_type:LPDDR4
3771 12:43:15.592509 GP_NUM : 10
3772 12:43:15.595807 SRAM_EN : 1
3773 12:43:15.595888 MD32_EN : 0
3774 12:43:15.598913 ===================================
3775 12:43:15.602544 [ANA_INIT] >>>>>>>>>>>>>>
3776 12:43:15.605740 <<<<<< [CONFIGURE PHASE]: ANA_TX
3777 12:43:15.608603 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3778 12:43:15.611967 ===================================
3779 12:43:15.615317 data_rate = 1200,PCW = 0X5800
3780 12:43:15.618829 ===================================
3781 12:43:15.622393 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3782 12:43:15.625325 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3783 12:43:15.631985 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3784 12:43:15.636117 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3785 12:43:15.638684 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3786 12:43:15.642064 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3787 12:43:15.645352 [ANA_INIT] flow start
3788 12:43:15.648449 [ANA_INIT] PLL >>>>>>>>
3789 12:43:15.648530 [ANA_INIT] PLL <<<<<<<<
3790 12:43:15.651925 [ANA_INIT] MIDPI >>>>>>>>
3791 12:43:15.655333 [ANA_INIT] MIDPI <<<<<<<<
3792 12:43:15.658545 [ANA_INIT] DLL >>>>>>>>
3793 12:43:15.658626 [ANA_INIT] flow end
3794 12:43:15.661832 ============ LP4 DIFF to SE enter ============
3795 12:43:15.667958 ============ LP4 DIFF to SE exit ============
3796 12:43:15.668078 [ANA_INIT] <<<<<<<<<<<<<
3797 12:43:15.671608 [Flow] Enable top DCM control >>>>>
3798 12:43:15.674631 [Flow] Enable top DCM control <<<<<
3799 12:43:15.677890 Enable DLL master slave shuffle
3800 12:43:15.684925 ==============================================================
3801 12:43:15.687823 Gating Mode config
3802 12:43:15.691129 ==============================================================
3803 12:43:15.694616 Config description:
3804 12:43:15.704207 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3805 12:43:15.711146 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3806 12:43:15.714231 SELPH_MODE 0: By rank 1: By Phase
3807 12:43:15.720829 ==============================================================
3808 12:43:15.724306 GAT_TRACK_EN = 1
3809 12:43:15.727673 RX_GATING_MODE = 2
3810 12:43:15.730782 RX_GATING_TRACK_MODE = 2
3811 12:43:15.730863 SELPH_MODE = 1
3812 12:43:15.734393 PICG_EARLY_EN = 1
3813 12:43:15.737066 VALID_LAT_VALUE = 1
3814 12:43:15.743700 ==============================================================
3815 12:43:15.747022 Enter into Gating configuration >>>>
3816 12:43:15.750846 Exit from Gating configuration <<<<
3817 12:43:15.754028 Enter into DVFS_PRE_config >>>>>
3818 12:43:15.764314 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3819 12:43:15.767119 Exit from DVFS_PRE_config <<<<<
3820 12:43:15.770646 Enter into PICG configuration >>>>
3821 12:43:15.773570 Exit from PICG configuration <<<<
3822 12:43:15.777040 [RX_INPUT] configuration >>>>>
3823 12:43:15.780380 [RX_INPUT] configuration <<<<<
3824 12:43:15.783338 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3825 12:43:15.790445 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3826 12:43:15.796459 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3827 12:43:15.803196 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3828 12:43:15.809721 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3829 12:43:15.816267 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3830 12:43:15.819733 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3831 12:43:15.822779 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3832 12:43:15.826234 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3833 12:43:15.832814 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3834 12:43:15.837608 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3835 12:43:15.839170 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3836 12:43:15.842734 ===================================
3837 12:43:15.846018 LPDDR4 DRAM CONFIGURATION
3838 12:43:15.849802 ===================================
3839 12:43:15.849876 EX_ROW_EN[0] = 0x0
3840 12:43:15.852656 EX_ROW_EN[1] = 0x0
3841 12:43:15.855637 LP4Y_EN = 0x0
3842 12:43:15.855706 WORK_FSP = 0x0
3843 12:43:15.859423 WL = 0x2
3844 12:43:15.859495 RL = 0x2
3845 12:43:15.862720 BL = 0x2
3846 12:43:15.862789 RPST = 0x0
3847 12:43:15.866100 RD_PRE = 0x0
3848 12:43:15.866167 WR_PRE = 0x1
3849 12:43:15.869230 WR_PST = 0x0
3850 12:43:15.869294 DBI_WR = 0x0
3851 12:43:15.872247 DBI_RD = 0x0
3852 12:43:15.872328 OTF = 0x1
3853 12:43:15.875622 ===================================
3854 12:43:15.882370 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3855 12:43:15.885612 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3856 12:43:15.888995 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3857 12:43:15.892486 ===================================
3858 12:43:15.895609 LPDDR4 DRAM CONFIGURATION
3859 12:43:15.899008 ===================================
3860 12:43:15.901902 EX_ROW_EN[0] = 0x10
3861 12:43:15.901984 EX_ROW_EN[1] = 0x0
3862 12:43:15.905265 LP4Y_EN = 0x0
3863 12:43:15.905346 WORK_FSP = 0x0
3864 12:43:15.908684 WL = 0x2
3865 12:43:15.908764 RL = 0x2
3866 12:43:15.911811 BL = 0x2
3867 12:43:15.911891 RPST = 0x0
3868 12:43:15.915039 RD_PRE = 0x0
3869 12:43:15.915119 WR_PRE = 0x1
3870 12:43:15.919214 WR_PST = 0x0
3871 12:43:15.919295 DBI_WR = 0x0
3872 12:43:15.922378 DBI_RD = 0x0
3873 12:43:15.922459 OTF = 0x1
3874 12:43:15.925430 ===================================
3875 12:43:15.931994 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3876 12:43:15.936611 nWR fixed to 30
3877 12:43:15.940418 [ModeRegInit_LP4] CH0 RK0
3878 12:43:15.940524 [ModeRegInit_LP4] CH0 RK1
3879 12:43:15.942979 [ModeRegInit_LP4] CH1 RK0
3880 12:43:15.946197 [ModeRegInit_LP4] CH1 RK1
3881 12:43:15.946301 match AC timing 17
3882 12:43:15.953304 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3883 12:43:15.956026 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3884 12:43:15.959739 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3885 12:43:15.966266 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3886 12:43:15.969934 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3887 12:43:15.970013 ==
3888 12:43:15.972917 Dram Type= 6, Freq= 0, CH_0, rank 0
3889 12:43:15.975913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3890 12:43:15.976026 ==
3891 12:43:15.982607 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3892 12:43:15.989569 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3893 12:43:15.992510 [CA 0] Center 36 (6~67) winsize 62
3894 12:43:15.995816 [CA 1] Center 36 (6~67) winsize 62
3895 12:43:15.999949 [CA 2] Center 34 (4~65) winsize 62
3896 12:43:16.002813 [CA 3] Center 34 (4~65) winsize 62
3897 12:43:16.006114 [CA 4] Center 34 (3~65) winsize 63
3898 12:43:16.009463 [CA 5] Center 33 (3~64) winsize 62
3899 12:43:16.009537
3900 12:43:16.012372 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3901 12:43:16.012444
3902 12:43:16.015415 [CATrainingPosCal] consider 1 rank data
3903 12:43:16.018784 u2DelayCellTimex100 = 270/100 ps
3904 12:43:16.022585 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3905 12:43:16.025709 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3906 12:43:16.028863 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3907 12:43:16.035150 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3908 12:43:16.038362 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3909 12:43:16.041798 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3910 12:43:16.041898
3911 12:43:16.045088 CA PerBit enable=1, Macro0, CA PI delay=33
3912 12:43:16.045190
3913 12:43:16.048390 [CBTSetCACLKResult] CA Dly = 33
3914 12:43:16.048462 CS Dly: 4 (0~35)
3915 12:43:16.048523 ==
3916 12:43:16.052428 Dram Type= 6, Freq= 0, CH_0, rank 1
3917 12:43:16.059263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3918 12:43:16.059337 ==
3919 12:43:16.061554 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3920 12:43:16.068665 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3921 12:43:16.071994 [CA 0] Center 36 (6~67) winsize 62
3922 12:43:16.075061 [CA 1] Center 36 (6~67) winsize 62
3923 12:43:16.078279 [CA 2] Center 34 (4~65) winsize 62
3924 12:43:16.081297 [CA 3] Center 34 (4~65) winsize 62
3925 12:43:16.084682 [CA 4] Center 34 (3~65) winsize 63
3926 12:43:16.087889 [CA 5] Center 33 (3~64) winsize 62
3927 12:43:16.087986
3928 12:43:16.091432 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3929 12:43:16.091526
3930 12:43:16.097691 [CATrainingPosCal] consider 2 rank data
3931 12:43:16.097766 u2DelayCellTimex100 = 270/100 ps
3932 12:43:16.104432 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3933 12:43:16.108265 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3934 12:43:16.110860 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3935 12:43:16.114347 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3936 12:43:16.118018 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3937 12:43:16.121501 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3938 12:43:16.121573
3939 12:43:16.124262 CA PerBit enable=1, Macro0, CA PI delay=33
3940 12:43:16.124329
3941 12:43:16.128211 [CBTSetCACLKResult] CA Dly = 33
3942 12:43:16.130711 CS Dly: 5 (0~37)
3943 12:43:16.130808
3944 12:43:16.134246 ----->DramcWriteLeveling(PI) begin...
3945 12:43:16.134343 ==
3946 12:43:16.137943 Dram Type= 6, Freq= 0, CH_0, rank 0
3947 12:43:16.140875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3948 12:43:16.140970 ==
3949 12:43:16.143961 Write leveling (Byte 0): 32 => 32
3950 12:43:16.147483 Write leveling (Byte 1): 32 => 32
3951 12:43:16.150568 DramcWriteLeveling(PI) end<-----
3952 12:43:16.150669
3953 12:43:16.150768 ==
3954 12:43:16.154483 Dram Type= 6, Freq= 0, CH_0, rank 0
3955 12:43:16.157043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3956 12:43:16.157141 ==
3957 12:43:16.161324 [Gating] SW mode calibration
3958 12:43:16.167454 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3959 12:43:16.174130 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3960 12:43:16.177671 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3961 12:43:16.183506 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3962 12:43:16.186502 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3963 12:43:16.190068 0 9 12 | B1->B0 | 3434 3232 | 0 1 | (0 0) (1 0)
3964 12:43:16.197110 0 9 16 | B1->B0 | 2f2f 2727 | 0 0 | (0 1) (0 0)
3965 12:43:16.200142 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3966 12:43:16.203234 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3967 12:43:16.209616 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3968 12:43:16.213428 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3969 12:43:16.216253 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3970 12:43:16.222806 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3971 12:43:16.226266 0 10 12 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (0 0)
3972 12:43:16.229821 0 10 16 | B1->B0 | 3f3f 4444 | 0 0 | (0 0) (0 0)
3973 12:43:16.236258 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3974 12:43:16.239467 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3975 12:43:16.242960 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3976 12:43:16.248917 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3977 12:43:16.252640 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3978 12:43:16.255556 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3979 12:43:16.262328 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3980 12:43:16.265350 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3981 12:43:16.269468 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3982 12:43:16.275362 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3983 12:43:16.278566 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3984 12:43:16.282530 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3985 12:43:16.288478 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3986 12:43:16.292227 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 12:43:16.295215 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 12:43:16.301782 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 12:43:16.305091 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 12:43:16.308162 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 12:43:16.314741 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 12:43:16.317979 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 12:43:16.321367 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 12:43:16.328022 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 12:43:16.331450 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 12:43:16.334669 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 12:43:16.338166 Total UI for P1: 0, mck2ui 16
3998 12:43:16.341227 best dqsien dly found for B0: ( 0, 13, 14)
3999 12:43:16.344534 Total UI for P1: 0, mck2ui 16
4000 12:43:16.347937 best dqsien dly found for B1: ( 0, 13, 14)
4001 12:43:16.350900 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4002 12:43:16.354268 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4003 12:43:16.358652
4004 12:43:16.361032 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4005 12:43:16.364421 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4006 12:43:16.367887 [Gating] SW calibration Done
4007 12:43:16.367969 ==
4008 12:43:16.371237 Dram Type= 6, Freq= 0, CH_0, rank 0
4009 12:43:16.374008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4010 12:43:16.374091 ==
4011 12:43:16.374156 RX Vref Scan: 0
4012 12:43:16.377540
4013 12:43:16.377622 RX Vref 0 -> 0, step: 1
4014 12:43:16.377692
4015 12:43:16.380825 RX Delay -230 -> 252, step: 16
4016 12:43:16.384447 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4017 12:43:16.390543 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4018 12:43:16.393806 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4019 12:43:16.397222 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4020 12:43:16.400531 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4021 12:43:16.403692 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4022 12:43:16.410456 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4023 12:43:16.413591 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4024 12:43:16.416853 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4025 12:43:16.420511 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4026 12:43:16.426921 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4027 12:43:16.430588 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4028 12:43:16.433248 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4029 12:43:16.436558 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4030 12:43:16.443423 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4031 12:43:16.446184 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4032 12:43:16.446266 ==
4033 12:43:16.449739 Dram Type= 6, Freq= 0, CH_0, rank 0
4034 12:43:16.453372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4035 12:43:16.453455 ==
4036 12:43:16.456579 DQS Delay:
4037 12:43:16.456661 DQS0 = 0, DQS1 = 0
4038 12:43:16.460395 DQM Delay:
4039 12:43:16.460477 DQM0 = 41, DQM1 = 33
4040 12:43:16.460541 DQ Delay:
4041 12:43:16.462645 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4042 12:43:16.465984 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4043 12:43:16.469441 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4044 12:43:16.472973 DQ12 =41, DQ13 =33, DQ14 =41, DQ15 =41
4045 12:43:16.473054
4046 12:43:16.475746
4047 12:43:16.475831 ==
4048 12:43:16.479500 Dram Type= 6, Freq= 0, CH_0, rank 0
4049 12:43:16.482430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4050 12:43:16.482536 ==
4051 12:43:16.482633
4052 12:43:16.482727
4053 12:43:16.485846 TX Vref Scan disable
4054 12:43:16.485943 == TX Byte 0 ==
4055 12:43:16.492617 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4056 12:43:16.495870 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4057 12:43:16.495951 == TX Byte 1 ==
4058 12:43:16.503003 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4059 12:43:16.505789 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4060 12:43:16.505870 ==
4061 12:43:16.508904 Dram Type= 6, Freq= 0, CH_0, rank 0
4062 12:43:16.512255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4063 12:43:16.512336 ==
4064 12:43:16.512400
4065 12:43:16.512458
4066 12:43:16.515806 TX Vref Scan disable
4067 12:43:16.518847 == TX Byte 0 ==
4068 12:43:16.522244 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4069 12:43:16.525219 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4070 12:43:16.528480 == TX Byte 1 ==
4071 12:43:16.531863 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4072 12:43:16.538867 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4073 12:43:16.538947
4074 12:43:16.539011 [DATLAT]
4075 12:43:16.539071 Freq=600, CH0 RK0
4076 12:43:16.539128
4077 12:43:16.542790 DATLAT Default: 0x9
4078 12:43:16.542870 0, 0xFFFF, sum = 0
4079 12:43:16.545515 1, 0xFFFF, sum = 0
4080 12:43:16.545599 2, 0xFFFF, sum = 0
4081 12:43:16.548562 3, 0xFFFF, sum = 0
4082 12:43:16.551639 4, 0xFFFF, sum = 0
4083 12:43:16.551753 5, 0xFFFF, sum = 0
4084 12:43:16.554891 6, 0xFFFF, sum = 0
4085 12:43:16.554972 7, 0xFFFF, sum = 0
4086 12:43:16.558255 8, 0x0, sum = 1
4087 12:43:16.558361 9, 0x0, sum = 2
4088 12:43:16.558453 10, 0x0, sum = 3
4089 12:43:16.562354 11, 0x0, sum = 4
4090 12:43:16.562450 best_step = 9
4091 12:43:16.562537
4092 12:43:16.564992 ==
4093 12:43:16.565059 Dram Type= 6, Freq= 0, CH_0, rank 0
4094 12:43:16.571250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4095 12:43:16.571345 ==
4096 12:43:16.571432 RX Vref Scan: 1
4097 12:43:16.571525
4098 12:43:16.574585 RX Vref 0 -> 0, step: 1
4099 12:43:16.574660
4100 12:43:16.578326 RX Delay -195 -> 252, step: 8
4101 12:43:16.578414
4102 12:43:16.581164 Set Vref, RX VrefLevel [Byte0]: 52
4103 12:43:16.584431 [Byte1]: 60
4104 12:43:16.584527
4105 12:43:16.588332 Final RX Vref Byte 0 = 52 to rank0
4106 12:43:16.591512 Final RX Vref Byte 1 = 60 to rank0
4107 12:43:16.595462 Final RX Vref Byte 0 = 52 to rank1
4108 12:43:16.597650 Final RX Vref Byte 1 = 60 to rank1==
4109 12:43:16.601123 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 12:43:16.604252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 12:43:16.607381 ==
4112 12:43:16.607460 DQS Delay:
4113 12:43:16.607548 DQS0 = 0, DQS1 = 0
4114 12:43:16.611183 DQM Delay:
4115 12:43:16.611256 DQM0 = 41, DQM1 = 33
4116 12:43:16.614256 DQ Delay:
4117 12:43:16.617847 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =36
4118 12:43:16.617915 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =44
4119 12:43:16.620931 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =28
4120 12:43:16.627477 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4121 12:43:16.627571
4122 12:43:16.627666
4123 12:43:16.633792 [DQSOSCAuto] RK0, (LSB)MR18= 0x443c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
4124 12:43:16.637576 CH0 RK0: MR19=808, MR18=443C
4125 12:43:16.643851 CH0_RK0: MR19=0x808, MR18=0x443C, DQSOSC=396, MR23=63, INC=167, DEC=111
4126 12:43:16.643922
4127 12:43:16.646911 ----->DramcWriteLeveling(PI) begin...
4128 12:43:16.646998 ==
4129 12:43:16.650234 Dram Type= 6, Freq= 0, CH_0, rank 1
4130 12:43:16.654097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4131 12:43:16.654168 ==
4132 12:43:16.656914 Write leveling (Byte 0): 31 => 31
4133 12:43:16.660233 Write leveling (Byte 1): 30 => 30
4134 12:43:16.663538 DramcWriteLeveling(PI) end<-----
4135 12:43:16.663642
4136 12:43:16.663729 ==
4137 12:43:16.666850 Dram Type= 6, Freq= 0, CH_0, rank 1
4138 12:43:16.670105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4139 12:43:16.673373 ==
4140 12:43:16.673446 [Gating] SW mode calibration
4141 12:43:16.683268 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4142 12:43:16.686250 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4143 12:43:16.689449 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4144 12:43:16.696493 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4145 12:43:16.699707 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4146 12:43:16.703054 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
4147 12:43:16.709612 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
4148 12:43:16.713480 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4149 12:43:16.715904 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4150 12:43:16.722515 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4151 12:43:16.726604 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4152 12:43:16.729106 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4153 12:43:16.736743 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4154 12:43:16.738958 0 10 12 | B1->B0 | 2525 3434 | 0 1 | (0 0) (0 0)
4155 12:43:16.741984 0 10 16 | B1->B0 | 3535 4545 | 1 0 | (0 0) (0 0)
4156 12:43:16.748909 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4157 12:43:16.752562 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4158 12:43:16.755605 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4159 12:43:16.762688 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4160 12:43:16.765480 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4161 12:43:16.768662 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4162 12:43:16.775057 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4163 12:43:16.778469 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4164 12:43:16.781907 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4165 12:43:16.788199 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4166 12:43:16.791729 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4167 12:43:16.795148 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4168 12:43:16.801426 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4169 12:43:16.804884 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4170 12:43:16.808461 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4171 12:43:16.815228 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4172 12:43:16.818090 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 12:43:16.821552 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4174 12:43:16.828012 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 12:43:16.831582 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 12:43:16.835027 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 12:43:16.841122 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 12:43:16.844387 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4179 12:43:16.847682 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4180 12:43:16.851095 Total UI for P1: 0, mck2ui 16
4181 12:43:16.854120 best dqsien dly found for B0: ( 0, 13, 12)
4182 12:43:16.861065 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 12:43:16.863950 Total UI for P1: 0, mck2ui 16
4184 12:43:16.867565 best dqsien dly found for B1: ( 0, 13, 14)
4185 12:43:16.870855 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4186 12:43:16.874683 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4187 12:43:16.874763
4188 12:43:16.877625 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4189 12:43:16.880466 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4190 12:43:16.883949 [Gating] SW calibration Done
4191 12:43:16.884035 ==
4192 12:43:16.887025 Dram Type= 6, Freq= 0, CH_0, rank 1
4193 12:43:16.890513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4194 12:43:16.893843 ==
4195 12:43:16.893923 RX Vref Scan: 0
4196 12:43:16.893987
4197 12:43:16.897396 RX Vref 0 -> 0, step: 1
4198 12:43:16.897476
4199 12:43:16.900271 RX Delay -230 -> 252, step: 16
4200 12:43:16.903500 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4201 12:43:16.906906 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4202 12:43:16.910059 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4203 12:43:16.916513 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4204 12:43:16.919739 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4205 12:43:16.922971 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4206 12:43:16.927023 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4207 12:43:16.932916 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4208 12:43:16.936917 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4209 12:43:16.940358 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4210 12:43:16.943112 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4211 12:43:16.946302 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4212 12:43:16.952657 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4213 12:43:16.955771 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4214 12:43:16.959274 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4215 12:43:16.965641 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4216 12:43:16.965722 ==
4217 12:43:16.969552 Dram Type= 6, Freq= 0, CH_0, rank 1
4218 12:43:16.972390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4219 12:43:16.972470 ==
4220 12:43:16.972533 DQS Delay:
4221 12:43:16.975920 DQS0 = 0, DQS1 = 0
4222 12:43:16.976017 DQM Delay:
4223 12:43:16.979163 DQM0 = 42, DQM1 = 32
4224 12:43:16.979242 DQ Delay:
4225 12:43:16.982325 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4226 12:43:16.985801 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4227 12:43:16.988775 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4228 12:43:16.992257 DQ12 =41, DQ13 =33, DQ14 =41, DQ15 =41
4229 12:43:16.992337
4230 12:43:16.992399
4231 12:43:16.992456 ==
4232 12:43:16.996014 Dram Type= 6, Freq= 0, CH_0, rank 1
4233 12:43:16.998627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4234 12:43:16.998708 ==
4235 12:43:16.998771
4236 12:43:17.002224
4237 12:43:17.002304 TX Vref Scan disable
4238 12:43:17.005766 == TX Byte 0 ==
4239 12:43:17.008559 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4240 12:43:17.012893 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4241 12:43:17.015528 == TX Byte 1 ==
4242 12:43:17.019065 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4243 12:43:17.022222 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4244 12:43:17.025217 ==
4245 12:43:17.028291 Dram Type= 6, Freq= 0, CH_0, rank 1
4246 12:43:17.032410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4247 12:43:17.032490 ==
4248 12:43:17.032554
4249 12:43:17.032611
4250 12:43:17.035261 TX Vref Scan disable
4251 12:43:17.035340 == TX Byte 0 ==
4252 12:43:17.042101 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4253 12:43:17.044767 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4254 12:43:17.044848 == TX Byte 1 ==
4255 12:43:17.051855 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4256 12:43:17.054545 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4257 12:43:17.054626
4258 12:43:17.054689 [DATLAT]
4259 12:43:17.058269 Freq=600, CH0 RK1
4260 12:43:17.058349
4261 12:43:17.058412 DATLAT Default: 0x9
4262 12:43:17.061275 0, 0xFFFF, sum = 0
4263 12:43:17.064509 1, 0xFFFF, sum = 0
4264 12:43:17.064591 2, 0xFFFF, sum = 0
4265 12:43:17.067725 3, 0xFFFF, sum = 0
4266 12:43:17.067807 4, 0xFFFF, sum = 0
4267 12:43:17.071144 5, 0xFFFF, sum = 0
4268 12:43:17.071225 6, 0xFFFF, sum = 0
4269 12:43:17.074316 7, 0xFFFF, sum = 0
4270 12:43:17.074397 8, 0x0, sum = 1
4271 12:43:17.078073 9, 0x0, sum = 2
4272 12:43:17.078154 10, 0x0, sum = 3
4273 12:43:17.078218 11, 0x0, sum = 4
4274 12:43:17.081065 best_step = 9
4275 12:43:17.081146
4276 12:43:17.081210 ==
4277 12:43:17.084925 Dram Type= 6, Freq= 0, CH_0, rank 1
4278 12:43:17.088484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4279 12:43:17.088565 ==
4280 12:43:17.091133 RX Vref Scan: 0
4281 12:43:17.091213
4282 12:43:17.091275 RX Vref 0 -> 0, step: 1
4283 12:43:17.094257
4284 12:43:17.094337 RX Delay -195 -> 252, step: 8
4285 12:43:17.101863 iDelay=197, Bit 0, Center 40 (-107 ~ 188) 296
4286 12:43:17.105354 iDelay=197, Bit 1, Center 44 (-107 ~ 196) 304
4287 12:43:17.108668 iDelay=197, Bit 2, Center 36 (-115 ~ 188) 304
4288 12:43:17.111507 iDelay=197, Bit 3, Center 40 (-107 ~ 188) 296
4289 12:43:17.118922 iDelay=197, Bit 4, Center 44 (-107 ~ 196) 304
4290 12:43:17.122013 iDelay=197, Bit 5, Center 32 (-115 ~ 180) 296
4291 12:43:17.124920 iDelay=197, Bit 6, Center 48 (-99 ~ 196) 296
4292 12:43:17.128147 iDelay=197, Bit 7, Center 48 (-99 ~ 196) 296
4293 12:43:17.134624 iDelay=197, Bit 8, Center 24 (-131 ~ 180) 312
4294 12:43:17.137890 iDelay=197, Bit 9, Center 16 (-139 ~ 172) 312
4295 12:43:17.141226 iDelay=197, Bit 10, Center 36 (-123 ~ 196) 320
4296 12:43:17.145262 iDelay=197, Bit 11, Center 28 (-123 ~ 180) 304
4297 12:43:17.151532 iDelay=197, Bit 12, Center 40 (-115 ~ 196) 312
4298 12:43:17.154491 iDelay=197, Bit 13, Center 40 (-115 ~ 196) 312
4299 12:43:17.157764 iDelay=197, Bit 14, Center 44 (-107 ~ 196) 304
4300 12:43:17.161077 iDelay=197, Bit 15, Center 40 (-115 ~ 196) 312
4301 12:43:17.161156 ==
4302 12:43:17.164691 Dram Type= 6, Freq= 0, CH_0, rank 1
4303 12:43:17.170827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4304 12:43:17.170907 ==
4305 12:43:17.170969 DQS Delay:
4306 12:43:17.174393 DQS0 = 0, DQS1 = 0
4307 12:43:17.174471 DQM Delay:
4308 12:43:17.174533 DQM0 = 41, DQM1 = 33
4309 12:43:17.177702 DQ Delay:
4310 12:43:17.180431 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4311 12:43:17.183762 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4312 12:43:17.187059 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =28
4313 12:43:17.190687 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4314 12:43:17.190766
4315 12:43:17.190828
4316 12:43:17.197455 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c36, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
4317 12:43:17.200672 CH0 RK1: MR19=808, MR18=3C36
4318 12:43:17.207375 CH0_RK1: MR19=0x808, MR18=0x3C36, DQSOSC=398, MR23=63, INC=165, DEC=110
4319 12:43:17.210387 [RxdqsGatingPostProcess] freq 600
4320 12:43:17.216770 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4321 12:43:17.216849 Pre-setting of DQS Precalculation
4322 12:43:17.223727 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4323 12:43:17.223806 ==
4324 12:43:17.226793 Dram Type= 6, Freq= 0, CH_1, rank 0
4325 12:43:17.229872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4326 12:43:17.229951 ==
4327 12:43:17.236511 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4328 12:43:17.243241 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4329 12:43:17.246493 [CA 0] Center 36 (6~66) winsize 61
4330 12:43:17.250097 [CA 1] Center 35 (5~66) winsize 62
4331 12:43:17.253161 [CA 2] Center 34 (4~65) winsize 62
4332 12:43:17.256724 [CA 3] Center 34 (3~65) winsize 63
4333 12:43:17.259785 [CA 4] Center 34 (4~65) winsize 62
4334 12:43:17.263243 [CA 5] Center 34 (3~65) winsize 63
4335 12:43:17.263321
4336 12:43:17.266096 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4337 12:43:17.266173
4338 12:43:17.270012 [CATrainingPosCal] consider 1 rank data
4339 12:43:17.273219 u2DelayCellTimex100 = 270/100 ps
4340 12:43:17.276484 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4341 12:43:17.279442 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4342 12:43:17.282831 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4343 12:43:17.286384 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4344 12:43:17.289297 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4345 12:43:17.295952 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4346 12:43:17.296036
4347 12:43:17.299140 CA PerBit enable=1, Macro0, CA PI delay=34
4348 12:43:17.299218
4349 12:43:17.302510 [CBTSetCACLKResult] CA Dly = 34
4350 12:43:17.302588 CS Dly: 4 (0~35)
4351 12:43:17.302649 ==
4352 12:43:17.305860 Dram Type= 6, Freq= 0, CH_1, rank 1
4353 12:43:17.309733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4354 12:43:17.312463 ==
4355 12:43:17.315522 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4356 12:43:17.322363 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4357 12:43:17.325904 [CA 0] Center 35 (5~66) winsize 62
4358 12:43:17.329330 [CA 1] Center 35 (5~66) winsize 62
4359 12:43:17.332206 [CA 2] Center 34 (4~65) winsize 62
4360 12:43:17.335184 [CA 3] Center 34 (3~65) winsize 63
4361 12:43:17.338781 [CA 4] Center 34 (4~65) winsize 62
4362 12:43:17.341935 [CA 5] Center 34 (3~65) winsize 63
4363 12:43:17.342014
4364 12:43:17.345184 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4365 12:43:17.345262
4366 12:43:17.348692 [CATrainingPosCal] consider 2 rank data
4367 12:43:17.351874 u2DelayCellTimex100 = 270/100 ps
4368 12:43:17.355428 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4369 12:43:17.362493 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4370 12:43:17.365203 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4371 12:43:17.368678 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4372 12:43:17.371720 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4373 12:43:17.375131 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4374 12:43:17.375209
4375 12:43:17.378222 CA PerBit enable=1, Macro0, CA PI delay=34
4376 12:43:17.378301
4377 12:43:17.381464 [CBTSetCACLKResult] CA Dly = 34
4378 12:43:17.381542 CS Dly: 4 (0~36)
4379 12:43:17.385197
4380 12:43:17.388015 ----->DramcWriteLeveling(PI) begin...
4381 12:43:17.388119 ==
4382 12:43:17.391864 Dram Type= 6, Freq= 0, CH_1, rank 0
4383 12:43:17.395184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4384 12:43:17.395265 ==
4385 12:43:17.398859 Write leveling (Byte 0): 28 => 28
4386 12:43:17.401453 Write leveling (Byte 1): 31 => 31
4387 12:43:17.404872 DramcWriteLeveling(PI) end<-----
4388 12:43:17.404952
4389 12:43:17.405014 ==
4390 12:43:17.407645 Dram Type= 6, Freq= 0, CH_1, rank 0
4391 12:43:17.411505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4392 12:43:17.411586 ==
4393 12:43:17.414821 [Gating] SW mode calibration
4394 12:43:17.420976 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4395 12:43:17.427762 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4396 12:43:17.431011 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4397 12:43:17.434277 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4398 12:43:17.440529 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4399 12:43:17.444471 0 9 12 | B1->B0 | 3232 2f2f | 0 0 | (0 0) (0 0)
4400 12:43:17.447321 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4401 12:43:17.454520 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4402 12:43:17.457696 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4403 12:43:17.460493 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4404 12:43:17.467102 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4405 12:43:17.470114 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4406 12:43:17.474084 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4407 12:43:17.480249 0 10 12 | B1->B0 | 3535 3838 | 1 1 | (0 0) (0 0)
4408 12:43:17.483612 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4409 12:43:17.486699 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4410 12:43:17.493288 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4411 12:43:17.497256 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4412 12:43:17.500239 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4413 12:43:17.506368 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4414 12:43:17.509600 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4415 12:43:17.514001 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4416 12:43:17.520051 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4417 12:43:17.523405 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4418 12:43:17.527058 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4419 12:43:17.533424 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 12:43:17.536065 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 12:43:17.539657 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 12:43:17.546113 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 12:43:17.549478 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 12:43:17.552929 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 12:43:17.559201 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 12:43:17.562716 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 12:43:17.566269 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 12:43:17.572412 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 12:43:17.575764 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 12:43:17.578931 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 12:43:17.585877 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4432 12:43:17.589064 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 12:43:17.591994 Total UI for P1: 0, mck2ui 16
4434 12:43:17.595482 best dqsien dly found for B0: ( 0, 13, 12)
4435 12:43:17.598726 Total UI for P1: 0, mck2ui 16
4436 12:43:17.602188 best dqsien dly found for B1: ( 0, 13, 12)
4437 12:43:17.605628 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4438 12:43:17.608573 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4439 12:43:17.608653
4440 12:43:17.612009 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4441 12:43:17.618549 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4442 12:43:17.618630 [Gating] SW calibration Done
4443 12:43:17.621700 ==
4444 12:43:17.621781 Dram Type= 6, Freq= 0, CH_1, rank 0
4445 12:43:17.628236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4446 12:43:17.628317 ==
4447 12:43:17.628381 RX Vref Scan: 0
4448 12:43:17.628440
4449 12:43:17.631477 RX Vref 0 -> 0, step: 1
4450 12:43:17.631556
4451 12:43:17.635032 RX Delay -230 -> 252, step: 16
4452 12:43:17.638088 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4453 12:43:17.642152 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4454 12:43:17.648405 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4455 12:43:17.651384 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4456 12:43:17.655298 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4457 12:43:17.658056 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4458 12:43:17.664310 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4459 12:43:17.668009 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4460 12:43:17.671166 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4461 12:43:17.674163 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4462 12:43:17.681356 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4463 12:43:17.684206 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4464 12:43:17.687738 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4465 12:43:17.691592 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4466 12:43:17.697301 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4467 12:43:17.700698 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4468 12:43:17.700779 ==
4469 12:43:17.704270 Dram Type= 6, Freq= 0, CH_1, rank 0
4470 12:43:17.707329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4471 12:43:17.707412 ==
4472 12:43:17.710737 DQS Delay:
4473 12:43:17.710818 DQS0 = 0, DQS1 = 0
4474 12:43:17.710882 DQM Delay:
4475 12:43:17.713554 DQM0 = 43, DQM1 = 37
4476 12:43:17.713634 DQ Delay:
4477 12:43:17.717040 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4478 12:43:17.720544 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4479 12:43:17.723879 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4480 12:43:17.727688 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4481 12:43:17.727768
4482 12:43:17.727832
4483 12:43:17.727890 ==
4484 12:43:17.730171 Dram Type= 6, Freq= 0, CH_1, rank 0
4485 12:43:17.736763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4486 12:43:17.736873 ==
4487 12:43:17.736963
4488 12:43:17.737024
4489 12:43:17.737081 TX Vref Scan disable
4490 12:43:17.740783 == TX Byte 0 ==
4491 12:43:17.744248 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4492 12:43:17.750940 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4493 12:43:17.751026 == TX Byte 1 ==
4494 12:43:17.753694 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4495 12:43:17.760218 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4496 12:43:17.760321 ==
4497 12:43:17.764210 Dram Type= 6, Freq= 0, CH_1, rank 0
4498 12:43:17.766963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4499 12:43:17.767059 ==
4500 12:43:17.767147
4501 12:43:17.767227
4502 12:43:17.770314 TX Vref Scan disable
4503 12:43:17.773298 == TX Byte 0 ==
4504 12:43:17.776917 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4505 12:43:17.779862 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4506 12:43:17.783511 == TX Byte 1 ==
4507 12:43:17.786701 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4508 12:43:17.790327 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4509 12:43:17.790410
4510 12:43:17.793375 [DATLAT]
4511 12:43:17.793471 Freq=600, CH1 RK0
4512 12:43:17.793576
4513 12:43:17.796482 DATLAT Default: 0x9
4514 12:43:17.796564 0, 0xFFFF, sum = 0
4515 12:43:17.799727 1, 0xFFFF, sum = 0
4516 12:43:17.799811 2, 0xFFFF, sum = 0
4517 12:43:17.803222 3, 0xFFFF, sum = 0
4518 12:43:17.803305 4, 0xFFFF, sum = 0
4519 12:43:17.806142 5, 0xFFFF, sum = 0
4520 12:43:17.806228 6, 0xFFFF, sum = 0
4521 12:43:17.809564 7, 0xFFFF, sum = 0
4522 12:43:17.809672 8, 0x0, sum = 1
4523 12:43:17.812729 9, 0x0, sum = 2
4524 12:43:17.812811 10, 0x0, sum = 3
4525 12:43:17.815968 11, 0x0, sum = 4
4526 12:43:17.816104 best_step = 9
4527 12:43:17.816198
4528 12:43:17.816258 ==
4529 12:43:17.819434 Dram Type= 6, Freq= 0, CH_1, rank 0
4530 12:43:17.822407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4531 12:43:17.826698 ==
4532 12:43:17.826769 RX Vref Scan: 1
4533 12:43:17.826828
4534 12:43:17.829027 RX Vref 0 -> 0, step: 1
4535 12:43:17.829120
4536 12:43:17.833418 RX Delay -179 -> 252, step: 8
4537 12:43:17.833497
4538 12:43:17.835589 Set Vref, RX VrefLevel [Byte0]: 53
4539 12:43:17.838986 [Byte1]: 48
4540 12:43:17.839066
4541 12:43:17.842361 Final RX Vref Byte 0 = 53 to rank0
4542 12:43:17.845894 Final RX Vref Byte 1 = 48 to rank0
4543 12:43:17.848847 Final RX Vref Byte 0 = 53 to rank1
4544 12:43:17.852215 Final RX Vref Byte 1 = 48 to rank1==
4545 12:43:17.855830 Dram Type= 6, Freq= 0, CH_1, rank 0
4546 12:43:17.858670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4547 12:43:17.858751 ==
4548 12:43:17.862316 DQS Delay:
4549 12:43:17.862395 DQS0 = 0, DQS1 = 0
4550 12:43:17.862459 DQM Delay:
4551 12:43:17.865624 DQM0 = 41, DQM1 = 34
4552 12:43:17.865704 DQ Delay:
4553 12:43:17.868525 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4554 12:43:17.871716 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4555 12:43:17.875118 DQ8 =20, DQ9 =24, DQ10 =32, DQ11 =24
4556 12:43:17.878183 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =44
4557 12:43:17.878267
4558 12:43:17.878350
4559 12:43:17.888535 [DQSOSCAuto] RK0, (LSB)MR18= 0x2741, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
4560 12:43:17.891514 CH1 RK0: MR19=808, MR18=2741
4561 12:43:17.898510 CH1_RK0: MR19=0x808, MR18=0x2741, DQSOSC=397, MR23=63, INC=166, DEC=110
4562 12:43:17.898594
4563 12:43:17.901433 ----->DramcWriteLeveling(PI) begin...
4564 12:43:17.901522 ==
4565 12:43:17.904833 Dram Type= 6, Freq= 0, CH_1, rank 1
4566 12:43:17.908973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4567 12:43:17.909057 ==
4568 12:43:17.911286 Write leveling (Byte 0): 29 => 29
4569 12:43:17.914839 Write leveling (Byte 1): 32 => 32
4570 12:43:17.917915 DramcWriteLeveling(PI) end<-----
4571 12:43:17.917998
4572 12:43:17.918082 ==
4573 12:43:17.922477 Dram Type= 6, Freq= 0, CH_1, rank 1
4574 12:43:17.924833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 12:43:17.924916 ==
4576 12:43:17.927730 [Gating] SW mode calibration
4577 12:43:17.934820 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4578 12:43:17.941409 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4579 12:43:17.944186 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4580 12:43:17.947489 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4581 12:43:17.954500 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4582 12:43:17.957929 0 9 12 | B1->B0 | 3030 2d2d | 1 0 | (1 0) (0 0)
4583 12:43:17.961498 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
4584 12:43:17.967298 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4585 12:43:17.970588 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4586 12:43:17.974814 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4587 12:43:17.980729 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4588 12:43:17.983801 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4589 12:43:17.987202 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4590 12:43:17.993945 0 10 12 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
4591 12:43:17.997257 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4592 12:43:18.000699 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4593 12:43:18.006796 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4594 12:43:18.010499 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4595 12:43:18.013990 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4596 12:43:18.021218 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4597 12:43:18.023633 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4598 12:43:18.026804 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4599 12:43:18.033675 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4600 12:43:18.037149 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4601 12:43:18.039937 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4602 12:43:18.046990 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4603 12:43:18.050918 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4604 12:43:18.053293 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4605 12:43:18.060359 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4606 12:43:18.063065 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4607 12:43:18.066356 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 12:43:18.072856 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 12:43:18.076304 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 12:43:18.079672 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 12:43:18.085924 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 12:43:18.089355 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 12:43:18.092986 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 12:43:18.099269 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4615 12:43:18.102390 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 12:43:18.105644 Total UI for P1: 0, mck2ui 16
4617 12:43:18.108949 best dqsien dly found for B0: ( 0, 13, 12)
4618 12:43:18.112601 Total UI for P1: 0, mck2ui 16
4619 12:43:18.116156 best dqsien dly found for B1: ( 0, 13, 14)
4620 12:43:18.119342 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4621 12:43:18.121996 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4622 12:43:18.122079
4623 12:43:18.126484 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4624 12:43:18.131749 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4625 12:43:18.131832 [Gating] SW calibration Done
4626 12:43:18.131934 ==
4627 12:43:18.135276 Dram Type= 6, Freq= 0, CH_1, rank 1
4628 12:43:18.141911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4629 12:43:18.142030 ==
4630 12:43:18.142100 RX Vref Scan: 0
4631 12:43:18.142161
4632 12:43:18.145496 RX Vref 0 -> 0, step: 1
4633 12:43:18.145577
4634 12:43:18.148158 RX Delay -230 -> 252, step: 16
4635 12:43:18.152069 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4636 12:43:18.155047 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4637 12:43:18.161654 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4638 12:43:18.165237 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4639 12:43:18.167907 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4640 12:43:18.171387 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4641 12:43:18.177787 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4642 12:43:18.181626 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4643 12:43:18.185184 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4644 12:43:18.188147 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4645 12:43:18.190983 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4646 12:43:18.198222 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4647 12:43:18.201541 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4648 12:43:18.204253 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4649 12:43:18.210937 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4650 12:43:18.214355 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4651 12:43:18.214467 ==
4652 12:43:18.217255 Dram Type= 6, Freq= 0, CH_1, rank 1
4653 12:43:18.220879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4654 12:43:18.220961 ==
4655 12:43:18.224020 DQS Delay:
4656 12:43:18.224121 DQS0 = 0, DQS1 = 0
4657 12:43:18.224186 DQM Delay:
4658 12:43:18.226930 DQM0 = 39, DQM1 = 39
4659 12:43:18.227011 DQ Delay:
4660 12:43:18.230399 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4661 12:43:18.234155 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4662 12:43:18.237867 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4663 12:43:18.240925 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4664 12:43:18.241008
4665 12:43:18.241072
4666 12:43:18.241132 ==
4667 12:43:18.243506 Dram Type= 6, Freq= 0, CH_1, rank 1
4668 12:43:18.250231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4669 12:43:18.250314 ==
4670 12:43:18.250379
4671 12:43:18.250439
4672 12:43:18.250498 TX Vref Scan disable
4673 12:43:18.253642 == TX Byte 0 ==
4674 12:43:18.257142 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4675 12:43:18.263656 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4676 12:43:18.263738 == TX Byte 1 ==
4677 12:43:18.267585 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4678 12:43:18.273552 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4679 12:43:18.273634 ==
4680 12:43:18.277112 Dram Type= 6, Freq= 0, CH_1, rank 1
4681 12:43:18.280513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4682 12:43:18.280596 ==
4683 12:43:18.280661
4684 12:43:18.280722
4685 12:43:18.283467 TX Vref Scan disable
4686 12:43:18.286912 == TX Byte 0 ==
4687 12:43:18.289993 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4688 12:43:18.293563 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4689 12:43:18.297138 == TX Byte 1 ==
4690 12:43:18.300269 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4691 12:43:18.303238 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4692 12:43:18.303320
4693 12:43:18.306381 [DATLAT]
4694 12:43:18.306463 Freq=600, CH1 RK1
4695 12:43:18.306529
4696 12:43:18.309771 DATLAT Default: 0x9
4697 12:43:18.309852 0, 0xFFFF, sum = 0
4698 12:43:18.313144 1, 0xFFFF, sum = 0
4699 12:43:18.313228 2, 0xFFFF, sum = 0
4700 12:43:18.316650 3, 0xFFFF, sum = 0
4701 12:43:18.316733 4, 0xFFFF, sum = 0
4702 12:43:18.319999 5, 0xFFFF, sum = 0
4703 12:43:18.320126 6, 0xFFFF, sum = 0
4704 12:43:18.323312 7, 0xFFFF, sum = 0
4705 12:43:18.323395 8, 0x0, sum = 1
4706 12:43:18.326192 9, 0x0, sum = 2
4707 12:43:18.326276 10, 0x0, sum = 3
4708 12:43:18.330083 11, 0x0, sum = 4
4709 12:43:18.330206 best_step = 9
4710 12:43:18.330273
4711 12:43:18.330334 ==
4712 12:43:18.333151 Dram Type= 6, Freq= 0, CH_1, rank 1
4713 12:43:18.336283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4714 12:43:18.340203 ==
4715 12:43:18.340285 RX Vref Scan: 0
4716 12:43:18.340350
4717 12:43:18.343454 RX Vref 0 -> 0, step: 1
4718 12:43:18.343534
4719 12:43:18.346415 RX Delay -179 -> 252, step: 8
4720 12:43:18.349138 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4721 12:43:18.353213 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4722 12:43:18.359322 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4723 12:43:18.363138 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4724 12:43:18.366093 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4725 12:43:18.369650 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4726 12:43:18.375918 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4727 12:43:18.379154 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4728 12:43:18.382868 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4729 12:43:18.385836 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4730 12:43:18.388831 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4731 12:43:18.395814 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4732 12:43:18.398863 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4733 12:43:18.402360 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4734 12:43:18.409103 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4735 12:43:18.412009 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4736 12:43:18.412116 ==
4737 12:43:18.415759 Dram Type= 6, Freq= 0, CH_1, rank 1
4738 12:43:18.418563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4739 12:43:18.418632 ==
4740 12:43:18.421825 DQS Delay:
4741 12:43:18.421891 DQS0 = 0, DQS1 = 0
4742 12:43:18.421950 DQM Delay:
4743 12:43:18.425026 DQM0 = 39, DQM1 = 35
4744 12:43:18.425091 DQ Delay:
4745 12:43:18.429180 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =36
4746 12:43:18.432027 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36
4747 12:43:18.434862 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4748 12:43:18.438601 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4749 12:43:18.438681
4750 12:43:18.438742
4751 12:43:18.449212 [DQSOSCAuto] RK1, (LSB)MR18= 0x3459, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4752 12:43:18.449292 CH1 RK1: MR19=808, MR18=3459
4753 12:43:18.455202 CH1_RK1: MR19=0x808, MR18=0x3459, DQSOSC=393, MR23=63, INC=169, DEC=113
4754 12:43:18.458215 [RxdqsGatingPostProcess] freq 600
4755 12:43:18.465282 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4756 12:43:18.468023 Pre-setting of DQS Precalculation
4757 12:43:18.471512 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4758 12:43:18.481567 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4759 12:43:18.488425 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4760 12:43:18.488506
4761 12:43:18.488570
4762 12:43:18.491061 [Calibration Summary] 1200 Mbps
4763 12:43:18.491142 CH 0, Rank 0
4764 12:43:18.494903 SW Impedance : PASS
4765 12:43:18.494984 DUTY Scan : NO K
4766 12:43:18.498185 ZQ Calibration : PASS
4767 12:43:18.500831 Jitter Meter : NO K
4768 12:43:18.500912 CBT Training : PASS
4769 12:43:18.504413 Write leveling : PASS
4770 12:43:18.507579 RX DQS gating : PASS
4771 12:43:18.507659 RX DQ/DQS(RDDQC) : PASS
4772 12:43:18.510847 TX DQ/DQS : PASS
4773 12:43:18.513911 RX DATLAT : PASS
4774 12:43:18.513992 RX DQ/DQS(Engine): PASS
4775 12:43:18.517323 TX OE : NO K
4776 12:43:18.517405 All Pass.
4777 12:43:18.517469
4778 12:43:18.520924 CH 0, Rank 1
4779 12:43:18.521005 SW Impedance : PASS
4780 12:43:18.524013 DUTY Scan : NO K
4781 12:43:18.527342 ZQ Calibration : PASS
4782 12:43:18.527423 Jitter Meter : NO K
4783 12:43:18.530379 CBT Training : PASS
4784 12:43:18.533712 Write leveling : PASS
4785 12:43:18.533793 RX DQS gating : PASS
4786 12:43:18.537655 RX DQ/DQS(RDDQC) : PASS
4787 12:43:18.540602 TX DQ/DQS : PASS
4788 12:43:18.540683 RX DATLAT : PASS
4789 12:43:18.543679 RX DQ/DQS(Engine): PASS
4790 12:43:18.546723 TX OE : NO K
4791 12:43:18.546804 All Pass.
4792 12:43:18.546868
4793 12:43:18.546926 CH 1, Rank 0
4794 12:43:18.550873 SW Impedance : PASS
4795 12:43:18.554216 DUTY Scan : NO K
4796 12:43:18.554297 ZQ Calibration : PASS
4797 12:43:18.557064 Jitter Meter : NO K
4798 12:43:18.557145 CBT Training : PASS
4799 12:43:18.560206 Write leveling : PASS
4800 12:43:18.563470 RX DQS gating : PASS
4801 12:43:18.563551 RX DQ/DQS(RDDQC) : PASS
4802 12:43:18.566772 TX DQ/DQS : PASS
4803 12:43:18.570133 RX DATLAT : PASS
4804 12:43:18.570215 RX DQ/DQS(Engine): PASS
4805 12:43:18.573591 TX OE : NO K
4806 12:43:18.573673 All Pass.
4807 12:43:18.573737
4808 12:43:18.576276 CH 1, Rank 1
4809 12:43:18.576395 SW Impedance : PASS
4810 12:43:18.580015 DUTY Scan : NO K
4811 12:43:18.583251 ZQ Calibration : PASS
4812 12:43:18.583332 Jitter Meter : NO K
4813 12:43:18.586445 CBT Training : PASS
4814 12:43:18.589825 Write leveling : PASS
4815 12:43:18.589906 RX DQS gating : PASS
4816 12:43:18.592990 RX DQ/DQS(RDDQC) : PASS
4817 12:43:18.596258 TX DQ/DQS : PASS
4818 12:43:18.596340 RX DATLAT : PASS
4819 12:43:18.599758 RX DQ/DQS(Engine): PASS
4820 12:43:18.602851 TX OE : NO K
4821 12:43:18.602933 All Pass.
4822 12:43:18.602997
4823 12:43:18.606093 DramC Write-DBI off
4824 12:43:18.606174 PER_BANK_REFRESH: Hybrid Mode
4825 12:43:18.609248 TX_TRACKING: ON
4826 12:43:18.616248 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4827 12:43:18.622810 [FAST_K] Save calibration result to emmc
4828 12:43:18.626103 dramc_set_vcore_voltage set vcore to 662500
4829 12:43:18.626184 Read voltage for 933, 3
4830 12:43:18.629113 Vio18 = 0
4831 12:43:18.629194 Vcore = 662500
4832 12:43:18.629258 Vdram = 0
4833 12:43:18.632745 Vddq = 0
4834 12:43:18.632826 Vmddr = 0
4835 12:43:18.636126 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4836 12:43:18.642800 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4837 12:43:18.645524 MEM_TYPE=3, freq_sel=17
4838 12:43:18.649198 sv_algorithm_assistance_LP4_1600
4839 12:43:18.652018 ============ PULL DRAM RESETB DOWN ============
4840 12:43:18.655541 ========== PULL DRAM RESETB DOWN end =========
4841 12:43:18.661949 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4842 12:43:18.665374 ===================================
4843 12:43:18.665455 LPDDR4 DRAM CONFIGURATION
4844 12:43:18.668719 ===================================
4845 12:43:18.672672 EX_ROW_EN[0] = 0x0
4846 12:43:18.675808 EX_ROW_EN[1] = 0x0
4847 12:43:18.675914 LP4Y_EN = 0x0
4848 12:43:18.678812 WORK_FSP = 0x0
4849 12:43:18.678892 WL = 0x3
4850 12:43:18.682287 RL = 0x3
4851 12:43:18.682369 BL = 0x2
4852 12:43:18.685474 RPST = 0x0
4853 12:43:18.685547 RD_PRE = 0x0
4854 12:43:18.688456 WR_PRE = 0x1
4855 12:43:18.688536 WR_PST = 0x0
4856 12:43:18.691851 DBI_WR = 0x0
4857 12:43:18.691958 DBI_RD = 0x0
4858 12:43:18.695112 OTF = 0x1
4859 12:43:18.698253 ===================================
4860 12:43:18.701576 ===================================
4861 12:43:18.701657 ANA top config
4862 12:43:18.705043 ===================================
4863 12:43:18.708341 DLL_ASYNC_EN = 0
4864 12:43:18.711490 ALL_SLAVE_EN = 1
4865 12:43:18.714917 NEW_RANK_MODE = 1
4866 12:43:18.715000 DLL_IDLE_MODE = 1
4867 12:43:18.718412 LP45_APHY_COMB_EN = 1
4868 12:43:18.721133 TX_ODT_DIS = 1
4869 12:43:18.724810 NEW_8X_MODE = 1
4870 12:43:18.728310 ===================================
4871 12:43:18.731373 ===================================
4872 12:43:18.734531 data_rate = 1866
4873 12:43:18.734611 CKR = 1
4874 12:43:18.738525 DQ_P2S_RATIO = 8
4875 12:43:18.741291 ===================================
4876 12:43:18.744323 CA_P2S_RATIO = 8
4877 12:43:18.747825 DQ_CA_OPEN = 0
4878 12:43:18.751002 DQ_SEMI_OPEN = 0
4879 12:43:18.754124 CA_SEMI_OPEN = 0
4880 12:43:18.754205 CA_FULL_RATE = 0
4881 12:43:18.757564 DQ_CKDIV4_EN = 1
4882 12:43:18.761496 CA_CKDIV4_EN = 1
4883 12:43:18.764060 CA_PREDIV_EN = 0
4884 12:43:18.767395 PH8_DLY = 0
4885 12:43:18.770949 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4886 12:43:18.771031 DQ_AAMCK_DIV = 4
4887 12:43:18.774150 CA_AAMCK_DIV = 4
4888 12:43:18.777178 CA_ADMCK_DIV = 4
4889 12:43:18.780616 DQ_TRACK_CA_EN = 0
4890 12:43:18.783585 CA_PICK = 933
4891 12:43:18.787037 CA_MCKIO = 933
4892 12:43:18.790142 MCKIO_SEMI = 0
4893 12:43:18.793851 PLL_FREQ = 3732
4894 12:43:18.793932 DQ_UI_PI_RATIO = 32
4895 12:43:18.796981 CA_UI_PI_RATIO = 0
4896 12:43:18.800282 ===================================
4897 12:43:18.803351 ===================================
4898 12:43:18.807519 memory_type:LPDDR4
4899 12:43:18.810073 GP_NUM : 10
4900 12:43:18.810153 SRAM_EN : 1
4901 12:43:18.813356 MD32_EN : 0
4902 12:43:18.816580 ===================================
4903 12:43:18.820423 [ANA_INIT] >>>>>>>>>>>>>>
4904 12:43:18.820504 <<<<<< [CONFIGURE PHASE]: ANA_TX
4905 12:43:18.826777 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4906 12:43:18.829771 ===================================
4907 12:43:18.829852 data_rate = 1866,PCW = 0X8f00
4908 12:43:18.833805 ===================================
4909 12:43:18.836789 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4910 12:43:18.842864 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4911 12:43:18.849481 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4912 12:43:18.852700 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4913 12:43:18.856314 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4914 12:43:18.859389 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4915 12:43:18.862726 [ANA_INIT] flow start
4916 12:43:18.862806 [ANA_INIT] PLL >>>>>>>>
4917 12:43:18.865999 [ANA_INIT] PLL <<<<<<<<
4918 12:43:18.870267 [ANA_INIT] MIDPI >>>>>>>>
4919 12:43:18.872550 [ANA_INIT] MIDPI <<<<<<<<
4920 12:43:18.872630 [ANA_INIT] DLL >>>>>>>>
4921 12:43:18.876248 [ANA_INIT] flow end
4922 12:43:18.879278 ============ LP4 DIFF to SE enter ============
4923 12:43:18.882652 ============ LP4 DIFF to SE exit ============
4924 12:43:18.885649 [ANA_INIT] <<<<<<<<<<<<<
4925 12:43:18.888976 [Flow] Enable top DCM control >>>>>
4926 12:43:18.892273 [Flow] Enable top DCM control <<<<<
4927 12:43:18.895430 Enable DLL master slave shuffle
4928 12:43:18.902766 ==============================================================
4929 12:43:18.902879 Gating Mode config
4930 12:43:18.908981 ==============================================================
4931 12:43:18.911808 Config description:
4932 12:43:18.918702 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4933 12:43:18.925045 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4934 12:43:18.931553 SELPH_MODE 0: By rank 1: By Phase
4935 12:43:18.938260 ==============================================================
4936 12:43:18.941815 GAT_TRACK_EN = 1
4937 12:43:18.941887 RX_GATING_MODE = 2
4938 12:43:18.944890 RX_GATING_TRACK_MODE = 2
4939 12:43:18.948145 SELPH_MODE = 1
4940 12:43:18.951268 PICG_EARLY_EN = 1
4941 12:43:18.954515 VALID_LAT_VALUE = 1
4942 12:43:18.962105 ==============================================================
4943 12:43:18.964700 Enter into Gating configuration >>>>
4944 12:43:18.967694 Exit from Gating configuration <<<<
4945 12:43:18.972421 Enter into DVFS_PRE_config >>>>>
4946 12:43:18.981504 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4947 12:43:18.984499 Exit from DVFS_PRE_config <<<<<
4948 12:43:18.987935 Enter into PICG configuration >>>>
4949 12:43:18.991089 Exit from PICG configuration <<<<
4950 12:43:18.994399 [RX_INPUT] configuration >>>>>
4951 12:43:18.997874 [RX_INPUT] configuration <<<<<
4952 12:43:19.001100 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4953 12:43:19.007769 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4954 12:43:19.014355 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4955 12:43:19.020728 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4956 12:43:19.027301 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4957 12:43:19.030881 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4958 12:43:19.036884 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4959 12:43:19.040268 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4960 12:43:19.043605 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4961 12:43:19.046982 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4962 12:43:19.054253 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4963 12:43:19.056635 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4964 12:43:19.060278 ===================================
4965 12:43:19.063421 LPDDR4 DRAM CONFIGURATION
4966 12:43:19.066528 ===================================
4967 12:43:19.066625 EX_ROW_EN[0] = 0x0
4968 12:43:19.069923 EX_ROW_EN[1] = 0x0
4969 12:43:19.069994 LP4Y_EN = 0x0
4970 12:43:19.073613 WORK_FSP = 0x0
4971 12:43:19.073711 WL = 0x3
4972 12:43:19.076946 RL = 0x3
4973 12:43:19.077044 BL = 0x2
4974 12:43:19.079906 RPST = 0x0
4975 12:43:19.083027 RD_PRE = 0x0
4976 12:43:19.083123 WR_PRE = 0x1
4977 12:43:19.086268 WR_PST = 0x0
4978 12:43:19.086362 DBI_WR = 0x0
4979 12:43:19.089664 DBI_RD = 0x0
4980 12:43:19.089758 OTF = 0x1
4981 12:43:19.093033 ===================================
4982 12:43:19.096116 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4983 12:43:19.102658 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4984 12:43:19.105974 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4985 12:43:19.109184 ===================================
4986 12:43:19.112304 LPDDR4 DRAM CONFIGURATION
4987 12:43:19.115795 ===================================
4988 12:43:19.115895 EX_ROW_EN[0] = 0x10
4989 12:43:19.118903 EX_ROW_EN[1] = 0x0
4990 12:43:19.122320 LP4Y_EN = 0x0
4991 12:43:19.122414 WORK_FSP = 0x0
4992 12:43:19.125631 WL = 0x3
4993 12:43:19.125702 RL = 0x3
4994 12:43:19.129180 BL = 0x2
4995 12:43:19.129247 RPST = 0x0
4996 12:43:19.132676 RD_PRE = 0x0
4997 12:43:19.132743 WR_PRE = 0x1
4998 12:43:19.135342 WR_PST = 0x0
4999 12:43:19.135433 DBI_WR = 0x0
5000 12:43:19.138526 DBI_RD = 0x0
5001 12:43:19.138593 OTF = 0x1
5002 12:43:19.142059 ===================================
5003 12:43:19.148611 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5004 12:43:19.153241 nWR fixed to 30
5005 12:43:19.156533 [ModeRegInit_LP4] CH0 RK0
5006 12:43:19.156604 [ModeRegInit_LP4] CH0 RK1
5007 12:43:19.159761 [ModeRegInit_LP4] CH1 RK0
5008 12:43:19.163230 [ModeRegInit_LP4] CH1 RK1
5009 12:43:19.163300 match AC timing 9
5010 12:43:19.169653 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5011 12:43:19.172740 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5012 12:43:19.176284 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5013 12:43:19.182986 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5014 12:43:19.186175 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5015 12:43:19.186246 ==
5016 12:43:19.189167 Dram Type= 6, Freq= 0, CH_0, rank 0
5017 12:43:19.192386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5018 12:43:19.192461 ==
5019 12:43:19.199581 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5020 12:43:19.205722 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5021 12:43:19.209322 [CA 0] Center 37 (7~68) winsize 62
5022 12:43:19.212267 [CA 1] Center 37 (7~68) winsize 62
5023 12:43:19.215229 [CA 2] Center 34 (4~64) winsize 61
5024 12:43:19.218805 [CA 3] Center 34 (4~65) winsize 62
5025 12:43:19.222107 [CA 4] Center 33 (3~64) winsize 62
5026 12:43:19.225620 [CA 5] Center 32 (2~63) winsize 62
5027 12:43:19.225719
5028 12:43:19.228551 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5029 12:43:19.228651
5030 12:43:19.231816 [CATrainingPosCal] consider 1 rank data
5031 12:43:19.234991 u2DelayCellTimex100 = 270/100 ps
5032 12:43:19.238835 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5033 12:43:19.241755 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5034 12:43:19.245197 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5035 12:43:19.251877 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5036 12:43:19.254973 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5037 12:43:19.258510 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5038 12:43:19.258591
5039 12:43:19.262344 CA PerBit enable=1, Macro0, CA PI delay=32
5040 12:43:19.262424
5041 12:43:19.264968 [CBTSetCACLKResult] CA Dly = 32
5042 12:43:19.265048 CS Dly: 5 (0~36)
5043 12:43:19.265112 ==
5044 12:43:19.268191 Dram Type= 6, Freq= 0, CH_0, rank 1
5045 12:43:19.275175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5046 12:43:19.275257 ==
5047 12:43:19.278044 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5048 12:43:19.285371 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5049 12:43:19.288254 [CA 0] Center 37 (7~68) winsize 62
5050 12:43:19.291742 [CA 1] Center 37 (7~68) winsize 62
5051 12:43:19.294602 [CA 2] Center 35 (5~65) winsize 61
5052 12:43:19.298150 [CA 3] Center 34 (4~65) winsize 62
5053 12:43:19.301166 [CA 4] Center 33 (3~64) winsize 62
5054 12:43:19.304599 [CA 5] Center 32 (2~63) winsize 62
5055 12:43:19.304680
5056 12:43:19.307824 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5057 12:43:19.307904
5058 12:43:19.311163 [CATrainingPosCal] consider 2 rank data
5059 12:43:19.314882 u2DelayCellTimex100 = 270/100 ps
5060 12:43:19.317728 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5061 12:43:19.324479 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5062 12:43:19.327545 CA2 delay=34 (5~64),Diff = 2 PI (12 cell)
5063 12:43:19.330754 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5064 12:43:19.334779 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5065 12:43:19.337566 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5066 12:43:19.337647
5067 12:43:19.341165 CA PerBit enable=1, Macro0, CA PI delay=32
5068 12:43:19.341245
5069 12:43:19.344317 [CBTSetCACLKResult] CA Dly = 32
5070 12:43:19.347512 CS Dly: 6 (0~39)
5071 12:43:19.347592
5072 12:43:19.350630 ----->DramcWriteLeveling(PI) begin...
5073 12:43:19.350712 ==
5074 12:43:19.354106 Dram Type= 6, Freq= 0, CH_0, rank 0
5075 12:43:19.357292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5076 12:43:19.357373 ==
5077 12:43:19.361078 Write leveling (Byte 0): 32 => 32
5078 12:43:19.363846 Write leveling (Byte 1): 27 => 27
5079 12:43:19.367378 DramcWriteLeveling(PI) end<-----
5080 12:43:19.367458
5081 12:43:19.367522 ==
5082 12:43:19.370453 Dram Type= 6, Freq= 0, CH_0, rank 0
5083 12:43:19.373559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5084 12:43:19.373640 ==
5085 12:43:19.376936 [Gating] SW mode calibration
5086 12:43:19.383610 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5087 12:43:19.390080 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5088 12:43:19.393122 0 14 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
5089 12:43:19.400508 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5090 12:43:19.403133 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5091 12:43:19.406550 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5092 12:43:19.413377 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5093 12:43:19.416643 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5094 12:43:19.419546 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5095 12:43:19.426023 0 14 28 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)
5096 12:43:19.429471 0 15 0 | B1->B0 | 3030 2626 | 1 0 | (1 1) (1 0)
5097 12:43:19.432802 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5098 12:43:19.440158 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5099 12:43:19.442600 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5100 12:43:19.446692 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5101 12:43:19.452290 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5102 12:43:19.455857 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5103 12:43:19.459618 0 15 28 | B1->B0 | 2323 3737 | 0 0 | (0 0) (1 1)
5104 12:43:19.465377 1 0 0 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
5105 12:43:19.468718 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5106 12:43:19.472150 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5107 12:43:19.479331 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5108 12:43:19.482316 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5109 12:43:19.485639 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5110 12:43:19.491959 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5111 12:43:19.494856 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5112 12:43:19.498347 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5113 12:43:19.505105 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5114 12:43:19.507908 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5115 12:43:19.511392 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5116 12:43:19.518335 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5117 12:43:19.521361 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 12:43:19.524908 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 12:43:19.531619 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 12:43:19.534472 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 12:43:19.537568 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 12:43:19.544611 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 12:43:19.547596 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 12:43:19.551088 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 12:43:19.557321 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 12:43:19.560675 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 12:43:19.563890 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5128 12:43:19.571028 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5129 12:43:19.574029 Total UI for P1: 0, mck2ui 16
5130 12:43:19.577797 best dqsien dly found for B0: ( 1, 2, 28)
5131 12:43:19.580608 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 12:43:19.583861 Total UI for P1: 0, mck2ui 16
5133 12:43:19.587109 best dqsien dly found for B1: ( 1, 3, 2)
5134 12:43:19.590646 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5135 12:43:19.594314 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5136 12:43:19.594396
5137 12:43:19.597159 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5138 12:43:19.603494 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5139 12:43:19.603574 [Gating] SW calibration Done
5140 12:43:19.603642 ==
5141 12:43:19.606678 Dram Type= 6, Freq= 0, CH_0, rank 0
5142 12:43:19.613713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5143 12:43:19.613794 ==
5144 12:43:19.613859 RX Vref Scan: 0
5145 12:43:19.613918
5146 12:43:19.617406 RX Vref 0 -> 0, step: 1
5147 12:43:19.617487
5148 12:43:19.620268 RX Delay -80 -> 252, step: 8
5149 12:43:19.623573 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5150 12:43:19.626840 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5151 12:43:19.630086 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5152 12:43:19.633075 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5153 12:43:19.640018 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5154 12:43:19.643916 iDelay=208, Bit 5, Center 91 (-8 ~ 191) 200
5155 12:43:19.646422 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5156 12:43:19.650504 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5157 12:43:19.652893 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5158 12:43:19.659889 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5159 12:43:19.662816 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5160 12:43:19.666116 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5161 12:43:19.669328 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5162 12:43:19.673381 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5163 12:43:19.676641 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5164 12:43:19.682869 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5165 12:43:19.682952 ==
5166 12:43:19.686351 Dram Type= 6, Freq= 0, CH_0, rank 0
5167 12:43:19.689097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5168 12:43:19.689180 ==
5169 12:43:19.689244 DQS Delay:
5170 12:43:19.692751 DQS0 = 0, DQS1 = 0
5171 12:43:19.692833 DQM Delay:
5172 12:43:19.695540 DQM0 = 100, DQM1 = 88
5173 12:43:19.695622 DQ Delay:
5174 12:43:19.699088 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5175 12:43:19.702704 DQ4 =103, DQ5 =91, DQ6 =111, DQ7 =107
5176 12:43:19.705766 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5177 12:43:19.708650 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5178 12:43:19.708732
5179 12:43:19.708797
5180 12:43:19.708856 ==
5181 12:43:19.711986 Dram Type= 6, Freq= 0, CH_0, rank 0
5182 12:43:19.718596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5183 12:43:19.718678 ==
5184 12:43:19.718744
5185 12:43:19.718804
5186 12:43:19.718863 TX Vref Scan disable
5187 12:43:19.722540 == TX Byte 0 ==
5188 12:43:19.726127 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5189 12:43:19.732338 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5190 12:43:19.732420 == TX Byte 1 ==
5191 12:43:19.735783 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5192 12:43:19.742766 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5193 12:43:19.742849 ==
5194 12:43:19.745232 Dram Type= 6, Freq= 0, CH_0, rank 0
5195 12:43:19.748902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5196 12:43:19.748984 ==
5197 12:43:19.749050
5198 12:43:19.749111
5199 12:43:19.752046 TX Vref Scan disable
5200 12:43:19.752141 == TX Byte 0 ==
5201 12:43:19.758826 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5202 12:43:19.762191 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5203 12:43:19.765355 == TX Byte 1 ==
5204 12:43:19.768588 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5205 12:43:19.771919 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5206 12:43:19.772026
5207 12:43:19.772106 [DATLAT]
5208 12:43:19.775572 Freq=933, CH0 RK0
5209 12:43:19.775654
5210 12:43:19.775718 DATLAT Default: 0xd
5211 12:43:19.778183 0, 0xFFFF, sum = 0
5212 12:43:19.781666 1, 0xFFFF, sum = 0
5213 12:43:19.781749 2, 0xFFFF, sum = 0
5214 12:43:19.785293 3, 0xFFFF, sum = 0
5215 12:43:19.785376 4, 0xFFFF, sum = 0
5216 12:43:19.788280 5, 0xFFFF, sum = 0
5217 12:43:19.788363 6, 0xFFFF, sum = 0
5218 12:43:19.791622 7, 0xFFFF, sum = 0
5219 12:43:19.791705 8, 0xFFFF, sum = 0
5220 12:43:19.794867 9, 0xFFFF, sum = 0
5221 12:43:19.794950 10, 0x0, sum = 1
5222 12:43:19.798745 11, 0x0, sum = 2
5223 12:43:19.798828 12, 0x0, sum = 3
5224 12:43:19.801960 13, 0x0, sum = 4
5225 12:43:19.802043 best_step = 11
5226 12:43:19.802107
5227 12:43:19.802167 ==
5228 12:43:19.804709 Dram Type= 6, Freq= 0, CH_0, rank 0
5229 12:43:19.808417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5230 12:43:19.808499 ==
5231 12:43:19.811451 RX Vref Scan: 1
5232 12:43:19.811532
5233 12:43:19.814451 RX Vref 0 -> 0, step: 1
5234 12:43:19.814533
5235 12:43:19.814597 RX Delay -61 -> 252, step: 4
5236 12:43:19.817933
5237 12:43:19.818015 Set Vref, RX VrefLevel [Byte0]: 52
5238 12:43:19.821665 [Byte1]: 60
5239 12:43:19.826560
5240 12:43:19.826641 Final RX Vref Byte 0 = 52 to rank0
5241 12:43:19.829981 Final RX Vref Byte 1 = 60 to rank0
5242 12:43:19.832815 Final RX Vref Byte 0 = 52 to rank1
5243 12:43:19.836058 Final RX Vref Byte 1 = 60 to rank1==
5244 12:43:19.839786 Dram Type= 6, Freq= 0, CH_0, rank 0
5245 12:43:19.845740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5246 12:43:19.845822 ==
5247 12:43:19.845888 DQS Delay:
5248 12:43:19.849220 DQS0 = 0, DQS1 = 0
5249 12:43:19.849327 DQM Delay:
5250 12:43:19.849421 DQM0 = 98, DQM1 = 88
5251 12:43:19.852390 DQ Delay:
5252 12:43:19.855770 DQ0 =100, DQ1 =100, DQ2 =94, DQ3 =96
5253 12:43:19.858842 DQ4 =100, DQ5 =90, DQ6 =106, DQ7 =104
5254 12:43:19.862304 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =84
5255 12:43:19.865705 DQ12 =96, DQ13 =94, DQ14 =98, DQ15 =94
5256 12:43:19.865788
5257 12:43:19.865852
5258 12:43:19.872276 [DQSOSCAuto] RK0, (LSB)MR18= 0x1813, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 414 ps
5259 12:43:19.875688 CH0 RK0: MR19=505, MR18=1813
5260 12:43:19.882131 CH0_RK0: MR19=0x505, MR18=0x1813, DQSOSC=414, MR23=63, INC=63, DEC=42
5261 12:43:19.882214
5262 12:43:19.885317 ----->DramcWriteLeveling(PI) begin...
5263 12:43:19.885400 ==
5264 12:43:19.888248 Dram Type= 6, Freq= 0, CH_0, rank 1
5265 12:43:19.891752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5266 12:43:19.895756 ==
5267 12:43:19.898351 Write leveling (Byte 0): 35 => 35
5268 12:43:19.898432 Write leveling (Byte 1): 27 => 27
5269 12:43:19.901536 DramcWriteLeveling(PI) end<-----
5270 12:43:19.901618
5271 12:43:19.905145 ==
5272 12:43:19.905227 Dram Type= 6, Freq= 0, CH_0, rank 1
5273 12:43:19.911405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5274 12:43:19.911488 ==
5275 12:43:19.914597 [Gating] SW mode calibration
5276 12:43:19.921321 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5277 12:43:19.924376 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5278 12:43:19.931061 0 14 0 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
5279 12:43:19.934443 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5280 12:43:19.937437 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5281 12:43:19.944058 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5282 12:43:19.947308 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5283 12:43:19.950446 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5284 12:43:19.957298 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5285 12:43:19.960562 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
5286 12:43:19.963687 0 15 0 | B1->B0 | 2e2e 2424 | 0 0 | (0 0) (0 0)
5287 12:43:19.970161 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5288 12:43:19.973483 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5289 12:43:19.977135 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5290 12:43:19.983376 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5291 12:43:19.987020 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5292 12:43:19.989919 0 15 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
5293 12:43:19.996747 0 15 28 | B1->B0 | 2b2b 3f3f | 0 1 | (0 0) (0 0)
5294 12:43:20.000013 1 0 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5295 12:43:20.003074 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5296 12:43:20.010322 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5297 12:43:20.012846 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5298 12:43:20.016137 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5299 12:43:20.023447 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5300 12:43:20.026121 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5301 12:43:20.029613 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5302 12:43:20.036029 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5303 12:43:20.039377 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5304 12:43:20.045692 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5305 12:43:20.049499 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5306 12:43:20.052468 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5307 12:43:20.059776 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5308 12:43:20.062591 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5309 12:43:20.066387 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5310 12:43:20.068893 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 12:43:20.075596 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 12:43:20.078821 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 12:43:20.085312 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 12:43:20.088852 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 12:43:20.091859 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 12:43:20.098769 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5317 12:43:20.101739 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5318 12:43:20.105194 Total UI for P1: 0, mck2ui 16
5319 12:43:20.108429 best dqsien dly found for B0: ( 1, 2, 24)
5320 12:43:20.111852 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5321 12:43:20.115163 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 12:43:20.118610 Total UI for P1: 0, mck2ui 16
5323 12:43:20.121597 best dqsien dly found for B1: ( 1, 2, 30)
5324 12:43:20.125016 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5325 12:43:20.131972 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5326 12:43:20.132050
5327 12:43:20.134993 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5328 12:43:20.138301 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5329 12:43:20.141855 [Gating] SW calibration Done
5330 12:43:20.141927 ==
5331 12:43:20.144599 Dram Type= 6, Freq= 0, CH_0, rank 1
5332 12:43:20.148149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5333 12:43:20.148218 ==
5334 12:43:20.151228 RX Vref Scan: 0
5335 12:43:20.151299
5336 12:43:20.151368 RX Vref 0 -> 0, step: 1
5337 12:43:20.151426
5338 12:43:20.155215 RX Delay -80 -> 252, step: 8
5339 12:43:20.158164 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5340 12:43:20.164582 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5341 12:43:20.167663 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5342 12:43:20.171346 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5343 12:43:20.174642 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5344 12:43:20.177731 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5345 12:43:20.181171 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5346 12:43:20.187779 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5347 12:43:20.190944 iDelay=200, Bit 8, Center 79 (-8 ~ 167) 176
5348 12:43:20.194001 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5349 12:43:20.197446 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5350 12:43:20.200659 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5351 12:43:20.207294 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5352 12:43:20.210494 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5353 12:43:20.214441 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5354 12:43:20.217146 iDelay=200, Bit 15, Center 99 (8 ~ 191) 184
5355 12:43:20.217219 ==
5356 12:43:20.220536 Dram Type= 6, Freq= 0, CH_0, rank 1
5357 12:43:20.223637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5358 12:43:20.223705 ==
5359 12:43:20.226779 DQS Delay:
5360 12:43:20.226843 DQS0 = 0, DQS1 = 0
5361 12:43:20.231025 DQM Delay:
5362 12:43:20.231092 DQM0 = 98, DQM1 = 89
5363 12:43:20.233626 DQ Delay:
5364 12:43:20.233697 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5365 12:43:20.236581 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =107
5366 12:43:20.240145 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5367 12:43:20.247006 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =99
5368 12:43:20.247080
5369 12:43:20.247140
5370 12:43:20.247206 ==
5371 12:43:20.250104 Dram Type= 6, Freq= 0, CH_0, rank 1
5372 12:43:20.253249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5373 12:43:20.253339 ==
5374 12:43:20.253403
5375 12:43:20.253462
5376 12:43:20.256636 TX Vref Scan disable
5377 12:43:20.256703 == TX Byte 0 ==
5378 12:43:20.263067 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5379 12:43:20.266238 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5380 12:43:20.266347 == TX Byte 1 ==
5381 12:43:20.272886 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5382 12:43:20.276385 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5383 12:43:20.276465 ==
5384 12:43:20.279450 Dram Type= 6, Freq= 0, CH_0, rank 1
5385 12:43:20.283190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5386 12:43:20.283271 ==
5387 12:43:20.285994
5388 12:43:20.286074
5389 12:43:20.286138 TX Vref Scan disable
5390 12:43:20.289685 == TX Byte 0 ==
5391 12:43:20.293132 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5392 12:43:20.299373 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5393 12:43:20.299454 == TX Byte 1 ==
5394 12:43:20.303166 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5395 12:43:20.309461 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5396 12:43:20.309544
5397 12:43:20.309608 [DATLAT]
5398 12:43:20.309667 Freq=933, CH0 RK1
5399 12:43:20.309723
5400 12:43:20.312454 DATLAT Default: 0xb
5401 12:43:20.315626 0, 0xFFFF, sum = 0
5402 12:43:20.315708 1, 0xFFFF, sum = 0
5403 12:43:20.319588 2, 0xFFFF, sum = 0
5404 12:43:20.319670 3, 0xFFFF, sum = 0
5405 12:43:20.322725 4, 0xFFFF, sum = 0
5406 12:43:20.322807 5, 0xFFFF, sum = 0
5407 12:43:20.325926 6, 0xFFFF, sum = 0
5408 12:43:20.326007 7, 0xFFFF, sum = 0
5409 12:43:20.329279 8, 0xFFFF, sum = 0
5410 12:43:20.329361 9, 0xFFFF, sum = 0
5411 12:43:20.332306 10, 0x0, sum = 1
5412 12:43:20.332391 11, 0x0, sum = 2
5413 12:43:20.335506 12, 0x0, sum = 3
5414 12:43:20.335587 13, 0x0, sum = 4
5415 12:43:20.338610 best_step = 11
5416 12:43:20.338717
5417 12:43:20.338792 ==
5418 12:43:20.341972 Dram Type= 6, Freq= 0, CH_0, rank 1
5419 12:43:20.345364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5420 12:43:20.345445 ==
5421 12:43:20.345509 RX Vref Scan: 0
5422 12:43:20.348966
5423 12:43:20.349047 RX Vref 0 -> 0, step: 1
5424 12:43:20.349111
5425 12:43:20.352069 RX Delay -53 -> 252, step: 4
5426 12:43:20.359352 iDelay=195, Bit 0, Center 96 (11 ~ 182) 172
5427 12:43:20.362328 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5428 12:43:20.365312 iDelay=195, Bit 2, Center 90 (-1 ~ 182) 184
5429 12:43:20.368616 iDelay=195, Bit 3, Center 96 (7 ~ 186) 180
5430 12:43:20.372377 iDelay=195, Bit 4, Center 98 (7 ~ 190) 184
5431 12:43:20.375221 iDelay=195, Bit 5, Center 86 (-5 ~ 178) 184
5432 12:43:20.382174 iDelay=195, Bit 6, Center 106 (19 ~ 194) 176
5433 12:43:20.384690 iDelay=195, Bit 7, Center 106 (19 ~ 194) 176
5434 12:43:20.388666 iDelay=195, Bit 8, Center 80 (-5 ~ 166) 172
5435 12:43:20.391851 iDelay=195, Bit 9, Center 76 (-9 ~ 162) 172
5436 12:43:20.395177 iDelay=195, Bit 10, Center 90 (-1 ~ 182) 184
5437 12:43:20.401104 iDelay=195, Bit 11, Center 84 (-5 ~ 174) 180
5438 12:43:20.404799 iDelay=195, Bit 12, Center 94 (7 ~ 182) 176
5439 12:43:20.408231 iDelay=195, Bit 13, Center 96 (7 ~ 186) 180
5440 12:43:20.411033 iDelay=195, Bit 14, Center 98 (11 ~ 186) 176
5441 12:43:20.414352 iDelay=195, Bit 15, Center 94 (7 ~ 182) 176
5442 12:43:20.414433 ==
5443 12:43:20.417812 Dram Type= 6, Freq= 0, CH_0, rank 1
5444 12:43:20.424376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5445 12:43:20.424457 ==
5446 12:43:20.424520 DQS Delay:
5447 12:43:20.427912 DQS0 = 0, DQS1 = 0
5448 12:43:20.428042 DQM Delay:
5449 12:43:20.430683 DQM0 = 97, DQM1 = 89
5450 12:43:20.430763 DQ Delay:
5451 12:43:20.433951 DQ0 =96, DQ1 =98, DQ2 =90, DQ3 =96
5452 12:43:20.438139 DQ4 =98, DQ5 =86, DQ6 =106, DQ7 =106
5453 12:43:20.440669 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =84
5454 12:43:20.444924 DQ12 =94, DQ13 =96, DQ14 =98, DQ15 =94
5455 12:43:20.445003
5456 12:43:20.445066
5457 12:43:20.450526 [DQSOSCAuto] RK1, (LSB)MR18= 0x1411, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5458 12:43:20.454030 CH0 RK1: MR19=505, MR18=1411
5459 12:43:20.460406 CH0_RK1: MR19=0x505, MR18=0x1411, DQSOSC=415, MR23=63, INC=62, DEC=41
5460 12:43:20.463470 [RxdqsGatingPostProcess] freq 933
5461 12:43:20.470528 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5462 12:43:20.473409 best DQS0 dly(2T, 0.5T) = (0, 10)
5463 12:43:20.476716 best DQS1 dly(2T, 0.5T) = (0, 11)
5464 12:43:20.480281 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5465 12:43:20.483949 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5466 12:43:20.484029 best DQS0 dly(2T, 0.5T) = (0, 10)
5467 12:43:20.486825 best DQS1 dly(2T, 0.5T) = (0, 10)
5468 12:43:20.489714 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5469 12:43:20.492932 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5470 12:43:20.496515 Pre-setting of DQS Precalculation
5471 12:43:20.503830 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5472 12:43:20.503911 ==
5473 12:43:20.506341 Dram Type= 6, Freq= 0, CH_1, rank 0
5474 12:43:20.509993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5475 12:43:20.510074 ==
5476 12:43:20.516269 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5477 12:43:20.522817 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5478 12:43:20.526672 [CA 0] Center 36 (6~67) winsize 62
5479 12:43:20.529403 [CA 1] Center 36 (6~67) winsize 62
5480 12:43:20.532508 [CA 2] Center 34 (4~65) winsize 62
5481 12:43:20.536086 [CA 3] Center 34 (3~65) winsize 63
5482 12:43:20.539284 [CA 4] Center 34 (4~65) winsize 62
5483 12:43:20.542934 [CA 5] Center 33 (3~64) winsize 62
5484 12:43:20.543015
5485 12:43:20.545775 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5486 12:43:20.545855
5487 12:43:20.550065 [CATrainingPosCal] consider 1 rank data
5488 12:43:20.552817 u2DelayCellTimex100 = 270/100 ps
5489 12:43:20.555946 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5490 12:43:20.559325 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5491 12:43:20.562408 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5492 12:43:20.565617 CA3 delay=34 (3~65),Diff = 1 PI (6 cell)
5493 12:43:20.568721 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5494 12:43:20.572891 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5495 12:43:20.572972
5496 12:43:20.578954 CA PerBit enable=1, Macro0, CA PI delay=33
5497 12:43:20.579035
5498 12:43:20.582686 [CBTSetCACLKResult] CA Dly = 33
5499 12:43:20.582768 CS Dly: 4 (0~35)
5500 12:43:20.582832 ==
5501 12:43:20.585481 Dram Type= 6, Freq= 0, CH_1, rank 1
5502 12:43:20.589072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5503 12:43:20.589154 ==
5504 12:43:20.595229 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5505 12:43:20.601775 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5506 12:43:20.605190 [CA 0] Center 36 (6~67) winsize 62
5507 12:43:20.608512 [CA 1] Center 36 (6~67) winsize 62
5508 12:43:20.612183 [CA 2] Center 34 (4~65) winsize 62
5509 12:43:20.615198 [CA 3] Center 33 (3~64) winsize 62
5510 12:43:20.618494 [CA 4] Center 34 (4~65) winsize 62
5511 12:43:20.621788 [CA 5] Center 33 (3~64) winsize 62
5512 12:43:20.621869
5513 12:43:20.625153 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5514 12:43:20.625234
5515 12:43:20.628666 [CATrainingPosCal] consider 2 rank data
5516 12:43:20.631443 u2DelayCellTimex100 = 270/100 ps
5517 12:43:20.634709 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5518 12:43:20.638521 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5519 12:43:20.641537 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5520 12:43:20.644575 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5521 12:43:20.651097 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5522 12:43:20.654307 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5523 12:43:20.654388
5524 12:43:20.658584 CA PerBit enable=1, Macro0, CA PI delay=33
5525 12:43:20.658665
5526 12:43:20.660953 [CBTSetCACLKResult] CA Dly = 33
5527 12:43:20.661035 CS Dly: 5 (0~38)
5528 12:43:20.661099
5529 12:43:20.664567 ----->DramcWriteLeveling(PI) begin...
5530 12:43:20.664649 ==
5531 12:43:20.667536 Dram Type= 6, Freq= 0, CH_1, rank 0
5532 12:43:20.674413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5533 12:43:20.674495 ==
5534 12:43:20.677748 Write leveling (Byte 0): 27 => 27
5535 12:43:20.681134 Write leveling (Byte 1): 30 => 30
5536 12:43:20.681215 DramcWriteLeveling(PI) end<-----
5537 12:43:20.684808
5538 12:43:20.684887 ==
5539 12:43:20.687825 Dram Type= 6, Freq= 0, CH_1, rank 0
5540 12:43:20.690682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5541 12:43:20.690764 ==
5542 12:43:20.694328 [Gating] SW mode calibration
5543 12:43:20.700969 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5544 12:43:20.707070 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5545 12:43:20.710384 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5546 12:43:20.713715 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5547 12:43:20.720225 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5548 12:43:20.723670 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5549 12:43:20.727220 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5550 12:43:20.733378 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5551 12:43:20.737139 0 14 24 | B1->B0 | 3434 3333 | 0 0 | (0 1) (0 0)
5552 12:43:20.740133 0 14 28 | B1->B0 | 2929 2626 | 0 0 | (1 1) (1 1)
5553 12:43:20.746818 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5554 12:43:20.749688 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5555 12:43:20.752897 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5556 12:43:20.759605 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5557 12:43:20.764008 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5558 12:43:20.766612 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5559 12:43:20.772965 0 15 24 | B1->B0 | 2424 2929 | 0 0 | (0 0) (0 0)
5560 12:43:20.776113 0 15 28 | B1->B0 | 3636 3b3b | 0 0 | (0 0) (0 0)
5561 12:43:20.779975 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5562 12:43:20.786529 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5563 12:43:20.789367 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5564 12:43:20.792854 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5565 12:43:20.799710 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5566 12:43:20.802518 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5567 12:43:20.805974 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5568 12:43:20.812323 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5569 12:43:20.816055 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 12:43:20.819412 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 12:43:20.825814 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 12:43:20.828836 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 12:43:20.832553 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 12:43:20.838719 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 12:43:20.842601 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 12:43:20.845214 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 12:43:20.851589 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 12:43:20.855118 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 12:43:20.858429 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 12:43:20.864905 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 12:43:20.868252 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 12:43:20.871503 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 12:43:20.878136 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5584 12:43:20.881306 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5585 12:43:20.884676 Total UI for P1: 0, mck2ui 16
5586 12:43:20.887996 best dqsien dly found for B1: ( 1, 2, 26)
5587 12:43:20.891379 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 12:43:20.894789 Total UI for P1: 0, mck2ui 16
5589 12:43:20.897757 best dqsien dly found for B0: ( 1, 2, 26)
5590 12:43:20.901009 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5591 12:43:20.904505 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5592 12:43:20.904578
5593 12:43:20.911390 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5594 12:43:20.914477 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5595 12:43:20.917982 [Gating] SW calibration Done
5596 12:43:20.918071 ==
5597 12:43:20.921317 Dram Type= 6, Freq= 0, CH_1, rank 0
5598 12:43:20.924208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5599 12:43:20.924303 ==
5600 12:43:20.924392 RX Vref Scan: 0
5601 12:43:20.924479
5602 12:43:20.927438 RX Vref 0 -> 0, step: 1
5603 12:43:20.927507
5604 12:43:20.930790 RX Delay -80 -> 252, step: 8
5605 12:43:20.933883 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5606 12:43:20.937938 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5607 12:43:20.944006 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5608 12:43:20.947689 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5609 12:43:20.950663 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5610 12:43:20.954045 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5611 12:43:20.957002 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5612 12:43:20.960267 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5613 12:43:20.967038 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5614 12:43:20.970065 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5615 12:43:20.974092 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5616 12:43:20.976489 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5617 12:43:20.980387 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5618 12:43:20.986569 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5619 12:43:20.989727 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5620 12:43:20.993032 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5621 12:43:20.993104 ==
5622 12:43:20.996822 Dram Type= 6, Freq= 0, CH_1, rank 0
5623 12:43:20.999492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5624 12:43:21.002997 ==
5625 12:43:21.003095 DQS Delay:
5626 12:43:21.003185 DQS0 = 0, DQS1 = 0
5627 12:43:21.006599 DQM Delay:
5628 12:43:21.006673 DQM0 = 99, DQM1 = 95
5629 12:43:21.009575 DQ Delay:
5630 12:43:21.012753 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5631 12:43:21.016665 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =99
5632 12:43:21.019183 DQ8 =79, DQ9 =87, DQ10 =95, DQ11 =87
5633 12:43:21.022803 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5634 12:43:21.022875
5635 12:43:21.022935
5636 12:43:21.022991 ==
5637 12:43:21.026049 Dram Type= 6, Freq= 0, CH_1, rank 0
5638 12:43:21.029902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5639 12:43:21.029996 ==
5640 12:43:21.030085
5641 12:43:21.030170
5642 12:43:21.033175 TX Vref Scan disable
5643 12:43:21.033262 == TX Byte 0 ==
5644 12:43:21.039668 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5645 12:43:21.042530 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5646 12:43:21.045800 == TX Byte 1 ==
5647 12:43:21.049258 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5648 12:43:21.052795 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5649 12:43:21.052908 ==
5650 12:43:21.055514 Dram Type= 6, Freq= 0, CH_1, rank 0
5651 12:43:21.059043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5652 12:43:21.062063 ==
5653 12:43:21.062169
5654 12:43:21.062260
5655 12:43:21.062357 TX Vref Scan disable
5656 12:43:21.065970 == TX Byte 0 ==
5657 12:43:21.069131 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5658 12:43:21.075962 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5659 12:43:21.076102 == TX Byte 1 ==
5660 12:43:21.078764 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5661 12:43:21.085398 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5662 12:43:21.085470
5663 12:43:21.085566 [DATLAT]
5664 12:43:21.085652 Freq=933, CH1 RK0
5665 12:43:21.085740
5666 12:43:21.089082 DATLAT Default: 0xd
5667 12:43:21.092644 0, 0xFFFF, sum = 0
5668 12:43:21.092724 1, 0xFFFF, sum = 0
5669 12:43:21.095161 2, 0xFFFF, sum = 0
5670 12:43:21.095263 3, 0xFFFF, sum = 0
5671 12:43:21.099265 4, 0xFFFF, sum = 0
5672 12:43:21.099336 5, 0xFFFF, sum = 0
5673 12:43:21.102679 6, 0xFFFF, sum = 0
5674 12:43:21.102776 7, 0xFFFF, sum = 0
5675 12:43:21.105212 8, 0xFFFF, sum = 0
5676 12:43:21.105282 9, 0xFFFF, sum = 0
5677 12:43:21.108271 10, 0x0, sum = 1
5678 12:43:21.108341 11, 0x0, sum = 2
5679 12:43:21.111515 12, 0x0, sum = 3
5680 12:43:21.111585 13, 0x0, sum = 4
5681 12:43:21.114911 best_step = 11
5682 12:43:21.115011
5683 12:43:21.115096 ==
5684 12:43:21.117908 Dram Type= 6, Freq= 0, CH_1, rank 0
5685 12:43:21.121172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5686 12:43:21.121256 ==
5687 12:43:21.124455 RX Vref Scan: 1
5688 12:43:21.124523
5689 12:43:21.124579 RX Vref 0 -> 0, step: 1
5690 12:43:21.124633
5691 12:43:21.127950 RX Delay -61 -> 252, step: 4
5692 12:43:21.128048
5693 12:43:21.131303 Set Vref, RX VrefLevel [Byte0]: 53
5694 12:43:21.134402 [Byte1]: 48
5695 12:43:21.138994
5696 12:43:21.139089 Final RX Vref Byte 0 = 53 to rank0
5697 12:43:21.141606 Final RX Vref Byte 1 = 48 to rank0
5698 12:43:21.144709 Final RX Vref Byte 0 = 53 to rank1
5699 12:43:21.147951 Final RX Vref Byte 1 = 48 to rank1==
5700 12:43:21.151682 Dram Type= 6, Freq= 0, CH_1, rank 0
5701 12:43:21.158117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5702 12:43:21.158219 ==
5703 12:43:21.158309 DQS Delay:
5704 12:43:21.161560 DQS0 = 0, DQS1 = 0
5705 12:43:21.161640 DQM Delay:
5706 12:43:21.161729 DQM0 = 98, DQM1 = 94
5707 12:43:21.164446 DQ Delay:
5708 12:43:21.167796 DQ0 =104, DQ1 =92, DQ2 =88, DQ3 =98
5709 12:43:21.171158 DQ4 =96, DQ5 =106, DQ6 =108, DQ7 =94
5710 12:43:21.174356 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =86
5711 12:43:21.177486 DQ12 =102, DQ13 =104, DQ14 =100, DQ15 =104
5712 12:43:21.177591
5713 12:43:21.177683
5714 12:43:21.184230 [DQSOSCAuto] RK0, (LSB)MR18= 0xa1a, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 418 ps
5715 12:43:21.187369 CH1 RK0: MR19=505, MR18=A1A
5716 12:43:21.194162 CH1_RK0: MR19=0x505, MR18=0xA1A, DQSOSC=413, MR23=63, INC=63, DEC=42
5717 12:43:21.194243
5718 12:43:21.197865 ----->DramcWriteLeveling(PI) begin...
5719 12:43:21.197946 ==
5720 12:43:21.200706 Dram Type= 6, Freq= 0, CH_1, rank 1
5721 12:43:21.204069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 12:43:21.207743 ==
5723 12:43:21.207823 Write leveling (Byte 0): 26 => 26
5724 12:43:21.211103 Write leveling (Byte 1): 28 => 28
5725 12:43:21.214138 DramcWriteLeveling(PI) end<-----
5726 12:43:21.214219
5727 12:43:21.214283 ==
5728 12:43:21.217021 Dram Type= 6, Freq= 0, CH_1, rank 1
5729 12:43:21.223705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5730 12:43:21.223786 ==
5731 12:43:21.223851 [Gating] SW mode calibration
5732 12:43:21.233629 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5733 12:43:21.236823 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5734 12:43:21.243777 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5735 12:43:21.247307 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5736 12:43:21.250132 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5737 12:43:21.256877 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5738 12:43:21.260189 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5739 12:43:21.263131 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5740 12:43:21.270268 0 14 24 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
5741 12:43:21.273177 0 14 28 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
5742 12:43:21.276644 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5743 12:43:21.283187 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5744 12:43:21.287068 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5745 12:43:21.289358 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5746 12:43:21.296088 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5747 12:43:21.300101 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5748 12:43:21.302708 0 15 24 | B1->B0 | 2525 3333 | 1 0 | (0 0) (0 0)
5749 12:43:21.309136 0 15 28 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
5750 12:43:21.312725 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5751 12:43:21.315807 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5752 12:43:21.322348 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5753 12:43:21.325481 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5754 12:43:21.329047 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5755 12:43:21.335498 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5756 12:43:21.338725 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5757 12:43:21.342203 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5758 12:43:21.348884 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5759 12:43:21.352089 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5760 12:43:21.355047 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5761 12:43:21.362423 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5762 12:43:21.365285 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5763 12:43:21.368387 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 12:43:21.374765 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 12:43:21.378328 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 12:43:21.381941 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 12:43:21.388003 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 12:43:21.391783 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 12:43:21.394932 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 12:43:21.401164 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 12:43:21.404358 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 12:43:21.407936 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5773 12:43:21.415023 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5774 12:43:21.417428 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 12:43:21.420899 Total UI for P1: 0, mck2ui 16
5776 12:43:21.424246 best dqsien dly found for B0: ( 1, 2, 26)
5777 12:43:21.427777 Total UI for P1: 0, mck2ui 16
5778 12:43:21.431423 best dqsien dly found for B1: ( 1, 2, 28)
5779 12:43:21.434669 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5780 12:43:21.438312 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5781 12:43:21.438383
5782 12:43:21.440950 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5783 12:43:21.444147 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5784 12:43:21.447469 [Gating] SW calibration Done
5785 12:43:21.447536 ==
5786 12:43:21.451024 Dram Type= 6, Freq= 0, CH_1, rank 1
5787 12:43:21.457635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5788 12:43:21.457711 ==
5789 12:43:21.457773 RX Vref Scan: 0
5790 12:43:21.457832
5791 12:43:21.460296 RX Vref 0 -> 0, step: 1
5792 12:43:21.460367
5793 12:43:21.464470 RX Delay -80 -> 252, step: 8
5794 12:43:21.467471 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5795 12:43:21.470365 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5796 12:43:21.474043 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5797 12:43:21.476874 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5798 12:43:21.483422 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5799 12:43:21.486884 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5800 12:43:21.489909 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5801 12:43:21.493920 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5802 12:43:21.496754 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5803 12:43:21.501127 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5804 12:43:21.506588 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5805 12:43:21.509864 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5806 12:43:21.513361 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5807 12:43:21.516671 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5808 12:43:21.520047 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5809 12:43:21.526321 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5810 12:43:21.526397 ==
5811 12:43:21.529504 Dram Type= 6, Freq= 0, CH_1, rank 1
5812 12:43:21.532978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5813 12:43:21.533051 ==
5814 12:43:21.533111 DQS Delay:
5815 12:43:21.537011 DQS0 = 0, DQS1 = 0
5816 12:43:21.537081 DQM Delay:
5817 12:43:21.539699 DQM0 = 97, DQM1 = 94
5818 12:43:21.539767 DQ Delay:
5819 12:43:21.542785 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5820 12:43:21.546103 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5821 12:43:21.549223 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =87
5822 12:43:21.553056 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5823 12:43:21.553134
5824 12:43:21.553197
5825 12:43:21.553255 ==
5826 12:43:21.556066 Dram Type= 6, Freq= 0, CH_1, rank 1
5827 12:43:21.562499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5828 12:43:21.562569 ==
5829 12:43:21.562630
5830 12:43:21.562690
5831 12:43:21.562745 TX Vref Scan disable
5832 12:43:21.566485 == TX Byte 0 ==
5833 12:43:21.569417 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5834 12:43:21.576025 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5835 12:43:21.576138 == TX Byte 1 ==
5836 12:43:21.579191 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5837 12:43:21.586340 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5838 12:43:21.586415 ==
5839 12:43:21.589180 Dram Type= 6, Freq= 0, CH_1, rank 1
5840 12:43:21.592151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5841 12:43:21.592219 ==
5842 12:43:21.592281
5843 12:43:21.592338
5844 12:43:21.595682 TX Vref Scan disable
5845 12:43:21.598709 == TX Byte 0 ==
5846 12:43:21.602331 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5847 12:43:21.605741 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5848 12:43:21.608725 == TX Byte 1 ==
5849 12:43:21.612665 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5850 12:43:21.615557 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5851 12:43:21.615624
5852 12:43:21.615686 [DATLAT]
5853 12:43:21.618894 Freq=933, CH1 RK1
5854 12:43:21.618961
5855 12:43:21.621917 DATLAT Default: 0xb
5856 12:43:21.622027 0, 0xFFFF, sum = 0
5857 12:43:21.625648 1, 0xFFFF, sum = 0
5858 12:43:21.625715 2, 0xFFFF, sum = 0
5859 12:43:21.628432 3, 0xFFFF, sum = 0
5860 12:43:21.628500 4, 0xFFFF, sum = 0
5861 12:43:21.631773 5, 0xFFFF, sum = 0
5862 12:43:21.631838 6, 0xFFFF, sum = 0
5863 12:43:21.635589 7, 0xFFFF, sum = 0
5864 12:43:21.635660 8, 0xFFFF, sum = 0
5865 12:43:21.638478 9, 0xFFFF, sum = 0
5866 12:43:21.638548 10, 0x0, sum = 1
5867 12:43:21.641913 11, 0x0, sum = 2
5868 12:43:21.641982 12, 0x0, sum = 3
5869 12:43:21.645286 13, 0x0, sum = 4
5870 12:43:21.645353 best_step = 11
5871 12:43:21.645413
5872 12:43:21.645468 ==
5873 12:43:21.648462 Dram Type= 6, Freq= 0, CH_1, rank 1
5874 12:43:21.651537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5875 12:43:21.654764 ==
5876 12:43:21.654838 RX Vref Scan: 0
5877 12:43:21.654898
5878 12:43:21.658401 RX Vref 0 -> 0, step: 1
5879 12:43:21.658467
5880 12:43:21.661299 RX Delay -61 -> 252, step: 4
5881 12:43:21.664898 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5882 12:43:21.667964 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5883 12:43:21.674543 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5884 12:43:21.678218 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5885 12:43:21.681013 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5886 12:43:21.685152 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5887 12:43:21.687486 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5888 12:43:21.694111 iDelay=199, Bit 7, Center 92 (-1 ~ 186) 188
5889 12:43:21.697674 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5890 12:43:21.701038 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5891 12:43:21.704058 iDelay=199, Bit 10, Center 90 (-1 ~ 182) 184
5892 12:43:21.707364 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5893 12:43:21.713815 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5894 12:43:21.717368 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5895 12:43:21.720869 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5896 12:43:21.723828 iDelay=199, Bit 15, Center 100 (7 ~ 194) 188
5897 12:43:21.723895 ==
5898 12:43:21.727379 Dram Type= 6, Freq= 0, CH_1, rank 1
5899 12:43:21.733618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5900 12:43:21.733688 ==
5901 12:43:21.733748 DQS Delay:
5902 12:43:21.733809 DQS0 = 0, DQS1 = 0
5903 12:43:21.737165 DQM Delay:
5904 12:43:21.737231 DQM0 = 96, DQM1 = 91
5905 12:43:21.740617 DQ Delay:
5906 12:43:21.743492 DQ0 =102, DQ1 =94, DQ2 =88, DQ3 =92
5907 12:43:21.746865 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =92
5908 12:43:21.750354 DQ8 =78, DQ9 =82, DQ10 =90, DQ11 =86
5909 12:43:21.754031 DQ12 =100, DQ13 =100, DQ14 =96, DQ15 =100
5910 12:43:21.754105
5911 12:43:21.754167
5912 12:43:21.759981 [DQSOSCAuto] RK1, (LSB)MR18= 0xf26, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 417 ps
5913 12:43:21.763434 CH1 RK1: MR19=505, MR18=F26
5914 12:43:21.770153 CH1_RK1: MR19=0x505, MR18=0xF26, DQSOSC=409, MR23=63, INC=64, DEC=43
5915 12:43:21.773279 [RxdqsGatingPostProcess] freq 933
5916 12:43:21.776600 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5917 12:43:21.780390 best DQS0 dly(2T, 0.5T) = (0, 10)
5918 12:43:21.783425 best DQS1 dly(2T, 0.5T) = (0, 10)
5919 12:43:21.786627 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5920 12:43:21.790216 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5921 12:43:21.792812 best DQS0 dly(2T, 0.5T) = (0, 10)
5922 12:43:21.796301 best DQS1 dly(2T, 0.5T) = (0, 10)
5923 12:43:21.799497 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5924 12:43:21.802991 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5925 12:43:21.806152 Pre-setting of DQS Precalculation
5926 12:43:21.812952 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5927 12:43:21.819643 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5928 12:43:21.826145 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5929 12:43:21.826226
5930 12:43:21.826289
5931 12:43:21.829304 [Calibration Summary] 1866 Mbps
5932 12:43:21.829384 CH 0, Rank 0
5933 12:43:21.832210 SW Impedance : PASS
5934 12:43:21.835915 DUTY Scan : NO K
5935 12:43:21.836025 ZQ Calibration : PASS
5936 12:43:21.839422 Jitter Meter : NO K
5937 12:43:21.842297 CBT Training : PASS
5938 12:43:21.842377 Write leveling : PASS
5939 12:43:21.845526 RX DQS gating : PASS
5940 12:43:21.849094 RX DQ/DQS(RDDQC) : PASS
5941 12:43:21.849181 TX DQ/DQS : PASS
5942 12:43:21.851970 RX DATLAT : PASS
5943 12:43:21.852086 RX DQ/DQS(Engine): PASS
5944 12:43:21.855531 TX OE : NO K
5945 12:43:21.855611 All Pass.
5946 12:43:21.855674
5947 12:43:21.859347 CH 0, Rank 1
5948 12:43:21.861997 SW Impedance : PASS
5949 12:43:21.862077 DUTY Scan : NO K
5950 12:43:21.865018 ZQ Calibration : PASS
5951 12:43:21.865097 Jitter Meter : NO K
5952 12:43:21.868391 CBT Training : PASS
5953 12:43:21.872257 Write leveling : PASS
5954 12:43:21.872337 RX DQS gating : PASS
5955 12:43:21.874794 RX DQ/DQS(RDDQC) : PASS
5956 12:43:21.878379 TX DQ/DQS : PASS
5957 12:43:21.878459 RX DATLAT : PASS
5958 12:43:21.882162 RX DQ/DQS(Engine): PASS
5959 12:43:21.885174 TX OE : NO K
5960 12:43:21.885254 All Pass.
5961 12:43:21.885318
5962 12:43:21.885377 CH 1, Rank 0
5963 12:43:21.888299 SW Impedance : PASS
5964 12:43:21.891479 DUTY Scan : NO K
5965 12:43:21.891590 ZQ Calibration : PASS
5966 12:43:21.895096 Jitter Meter : NO K
5967 12:43:21.898107 CBT Training : PASS
5968 12:43:21.898188 Write leveling : PASS
5969 12:43:21.901287 RX DQS gating : PASS
5970 12:43:21.905229 RX DQ/DQS(RDDQC) : PASS
5971 12:43:21.905310 TX DQ/DQS : PASS
5972 12:43:21.908336 RX DATLAT : PASS
5973 12:43:21.911359 RX DQ/DQS(Engine): PASS
5974 12:43:21.911439 TX OE : NO K
5975 12:43:21.914966 All Pass.
5976 12:43:21.915072
5977 12:43:21.915154 CH 1, Rank 1
5978 12:43:21.917832 SW Impedance : PASS
5979 12:43:21.917913 DUTY Scan : NO K
5980 12:43:21.921069 ZQ Calibration : PASS
5981 12:43:21.924137 Jitter Meter : NO K
5982 12:43:21.924218 CBT Training : PASS
5983 12:43:21.927849 Write leveling : PASS
5984 12:43:21.931050 RX DQS gating : PASS
5985 12:43:21.931131 RX DQ/DQS(RDDQC) : PASS
5986 12:43:21.934074 TX DQ/DQS : PASS
5987 12:43:21.937248 RX DATLAT : PASS
5988 12:43:21.937329 RX DQ/DQS(Engine): PASS
5989 12:43:21.940661 TX OE : NO K
5990 12:43:21.940741 All Pass.
5991 12:43:21.940806
5992 12:43:21.943911 DramC Write-DBI off
5993 12:43:21.947484 PER_BANK_REFRESH: Hybrid Mode
5994 12:43:21.947565 TX_TRACKING: ON
5995 12:43:21.957111 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5996 12:43:21.960488 [FAST_K] Save calibration result to emmc
5997 12:43:21.963878 dramc_set_vcore_voltage set vcore to 650000
5998 12:43:21.967066 Read voltage for 400, 6
5999 12:43:21.967172 Vio18 = 0
6000 12:43:21.967266 Vcore = 650000
6001 12:43:21.970637 Vdram = 0
6002 12:43:21.970717 Vddq = 0
6003 12:43:21.970782 Vmddr = 0
6004 12:43:21.976832 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6005 12:43:21.979990 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6006 12:43:21.983403 MEM_TYPE=3, freq_sel=20
6007 12:43:21.987080 sv_algorithm_assistance_LP4_800
6008 12:43:21.989872 ============ PULL DRAM RESETB DOWN ============
6009 12:43:21.993184 ========== PULL DRAM RESETB DOWN end =========
6010 12:43:22.000948 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6011 12:43:22.003517 ===================================
6012 12:43:22.006683 LPDDR4 DRAM CONFIGURATION
6013 12:43:22.009966 ===================================
6014 12:43:22.010048 EX_ROW_EN[0] = 0x0
6015 12:43:22.013294 EX_ROW_EN[1] = 0x0
6016 12:43:22.013375 LP4Y_EN = 0x0
6017 12:43:22.016531 WORK_FSP = 0x0
6018 12:43:22.016611 WL = 0x2
6019 12:43:22.020174 RL = 0x2
6020 12:43:22.020255 BL = 0x2
6021 12:43:22.022862 RPST = 0x0
6022 12:43:22.022943 RD_PRE = 0x0
6023 12:43:22.026196 WR_PRE = 0x1
6024 12:43:22.030169 WR_PST = 0x0
6025 12:43:22.030250 DBI_WR = 0x0
6026 12:43:22.033275 DBI_RD = 0x0
6027 12:43:22.033383 OTF = 0x1
6028 12:43:22.036208 ===================================
6029 12:43:22.039522 ===================================
6030 12:43:22.042887 ANA top config
6031 12:43:22.042967 ===================================
6032 12:43:22.047163 DLL_ASYNC_EN = 0
6033 12:43:22.049079 ALL_SLAVE_EN = 1
6034 12:43:22.052587 NEW_RANK_MODE = 1
6035 12:43:22.055670 DLL_IDLE_MODE = 1
6036 12:43:22.055751 LP45_APHY_COMB_EN = 1
6037 12:43:22.059367 TX_ODT_DIS = 1
6038 12:43:22.062087 NEW_8X_MODE = 1
6039 12:43:22.065796 ===================================
6040 12:43:22.068782 ===================================
6041 12:43:22.072056 data_rate = 800
6042 12:43:22.076254 CKR = 1
6043 12:43:22.079060 DQ_P2S_RATIO = 4
6044 12:43:22.082346 ===================================
6045 12:43:22.082427 CA_P2S_RATIO = 4
6046 12:43:22.085701 DQ_CA_OPEN = 0
6047 12:43:22.088652 DQ_SEMI_OPEN = 1
6048 12:43:22.092024 CA_SEMI_OPEN = 1
6049 12:43:22.095382 CA_FULL_RATE = 0
6050 12:43:22.099051 DQ_CKDIV4_EN = 0
6051 12:43:22.099132 CA_CKDIV4_EN = 1
6052 12:43:22.101752 CA_PREDIV_EN = 0
6053 12:43:22.105080 PH8_DLY = 0
6054 12:43:22.108328 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6055 12:43:22.111659 DQ_AAMCK_DIV = 0
6056 12:43:22.114986 CA_AAMCK_DIV = 0
6057 12:43:22.115067 CA_ADMCK_DIV = 4
6058 12:43:22.118351 DQ_TRACK_CA_EN = 0
6059 12:43:22.121785 CA_PICK = 800
6060 12:43:22.125128 CA_MCKIO = 400
6061 12:43:22.128254 MCKIO_SEMI = 400
6062 12:43:22.131350 PLL_FREQ = 3016
6063 12:43:22.134997 DQ_UI_PI_RATIO = 32
6064 12:43:22.138265 CA_UI_PI_RATIO = 32
6065 12:43:22.141736 ===================================
6066 12:43:22.144755 ===================================
6067 12:43:22.144836 memory_type:LPDDR4
6068 12:43:22.147751 GP_NUM : 10
6069 12:43:22.151044 SRAM_EN : 1
6070 12:43:22.151124 MD32_EN : 0
6071 12:43:22.154669 ===================================
6072 12:43:22.158052 [ANA_INIT] >>>>>>>>>>>>>>
6073 12:43:22.161245 <<<<<< [CONFIGURE PHASE]: ANA_TX
6074 12:43:22.164190 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6075 12:43:22.167754 ===================================
6076 12:43:22.170670 data_rate = 800,PCW = 0X7400
6077 12:43:22.174451 ===================================
6078 12:43:22.177915 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6079 12:43:22.180685 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6080 12:43:22.194669 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6081 12:43:22.197244 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6082 12:43:22.200486 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6083 12:43:22.204049 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6084 12:43:22.206897 [ANA_INIT] flow start
6085 12:43:22.210544 [ANA_INIT] PLL >>>>>>>>
6086 12:43:22.210627 [ANA_INIT] PLL <<<<<<<<
6087 12:43:22.213552 [ANA_INIT] MIDPI >>>>>>>>
6088 12:43:22.217547 [ANA_INIT] MIDPI <<<<<<<<
6089 12:43:22.220623 [ANA_INIT] DLL >>>>>>>>
6090 12:43:22.220717 [ANA_INIT] flow end
6091 12:43:22.223642 ============ LP4 DIFF to SE enter ============
6092 12:43:22.230137 ============ LP4 DIFF to SE exit ============
6093 12:43:22.230220 [ANA_INIT] <<<<<<<<<<<<<
6094 12:43:22.233470 [Flow] Enable top DCM control >>>>>
6095 12:43:22.237180 [Flow] Enable top DCM control <<<<<
6096 12:43:22.239670 Enable DLL master slave shuffle
6097 12:43:22.246512 ==============================================================
6098 12:43:22.246595 Gating Mode config
6099 12:43:22.253046 ==============================================================
6100 12:43:22.256658 Config description:
6101 12:43:22.266298 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6102 12:43:22.272811 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6103 12:43:22.276579 SELPH_MODE 0: By rank 1: By Phase
6104 12:43:22.282662 ==============================================================
6105 12:43:22.285757 GAT_TRACK_EN = 0
6106 12:43:22.289087 RX_GATING_MODE = 2
6107 12:43:22.292609 RX_GATING_TRACK_MODE = 2
6108 12:43:22.292690 SELPH_MODE = 1
6109 12:43:22.295915 PICG_EARLY_EN = 1
6110 12:43:22.299142 VALID_LAT_VALUE = 1
6111 12:43:22.305413 ==============================================================
6112 12:43:22.308693 Enter into Gating configuration >>>>
6113 12:43:22.312629 Exit from Gating configuration <<<<
6114 12:43:22.315565 Enter into DVFS_PRE_config >>>>>
6115 12:43:22.325338 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6116 12:43:22.329090 Exit from DVFS_PRE_config <<<<<
6117 12:43:22.332027 Enter into PICG configuration >>>>
6118 12:43:22.334921 Exit from PICG configuration <<<<
6119 12:43:22.338646 [RX_INPUT] configuration >>>>>
6120 12:43:22.341748 [RX_INPUT] configuration <<<<<
6121 12:43:22.344998 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6122 12:43:22.351537 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6123 12:43:22.358456 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6124 12:43:22.365017 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6125 12:43:22.371733 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6126 12:43:22.378329 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6127 12:43:22.381120 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6128 12:43:22.384565 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6129 12:43:22.388430 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6130 12:43:22.394789 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6131 12:43:22.397688 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6132 12:43:22.400822 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6133 12:43:22.404552 ===================================
6134 12:43:22.407520 LPDDR4 DRAM CONFIGURATION
6135 12:43:22.410895 ===================================
6136 12:43:22.410980 EX_ROW_EN[0] = 0x0
6137 12:43:22.414456 EX_ROW_EN[1] = 0x0
6138 12:43:22.417655 LP4Y_EN = 0x0
6139 12:43:22.417751 WORK_FSP = 0x0
6140 12:43:22.420736 WL = 0x2
6141 12:43:22.420806 RL = 0x2
6142 12:43:22.424228 BL = 0x2
6143 12:43:22.424296 RPST = 0x0
6144 12:43:22.427644 RD_PRE = 0x0
6145 12:43:22.427738 WR_PRE = 0x1
6146 12:43:22.430500 WR_PST = 0x0
6147 12:43:22.430594 DBI_WR = 0x0
6148 12:43:22.434034 DBI_RD = 0x0
6149 12:43:22.434102 OTF = 0x1
6150 12:43:22.436958 ===================================
6151 12:43:22.440303 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6152 12:43:22.447092 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6153 12:43:22.450602 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6154 12:43:22.453765 ===================================
6155 12:43:22.456771 LPDDR4 DRAM CONFIGURATION
6156 12:43:22.460598 ===================================
6157 12:43:22.464269 EX_ROW_EN[0] = 0x10
6158 12:43:22.464350 EX_ROW_EN[1] = 0x0
6159 12:43:22.466696 LP4Y_EN = 0x0
6160 12:43:22.466777 WORK_FSP = 0x0
6161 12:43:22.470139 WL = 0x2
6162 12:43:22.470221 RL = 0x2
6163 12:43:22.473449 BL = 0x2
6164 12:43:22.473521 RPST = 0x0
6165 12:43:22.476995 RD_PRE = 0x0
6166 12:43:22.477064 WR_PRE = 0x1
6167 12:43:22.480200 WR_PST = 0x0
6168 12:43:22.480267 DBI_WR = 0x0
6169 12:43:22.483370 DBI_RD = 0x0
6170 12:43:22.483435 OTF = 0x1
6171 12:43:22.486825 ===================================
6172 12:43:22.492973 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6173 12:43:22.498465 nWR fixed to 30
6174 12:43:22.501487 [ModeRegInit_LP4] CH0 RK0
6175 12:43:22.501557 [ModeRegInit_LP4] CH0 RK1
6176 12:43:22.504286 [ModeRegInit_LP4] CH1 RK0
6177 12:43:22.507859 [ModeRegInit_LP4] CH1 RK1
6178 12:43:22.507930 match AC timing 19
6179 12:43:22.514205 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6180 12:43:22.517656 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6181 12:43:22.520970 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6182 12:43:22.527462 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6183 12:43:22.530949 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6184 12:43:22.531019 ==
6185 12:43:22.533944 Dram Type= 6, Freq= 0, CH_0, rank 0
6186 12:43:22.537238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6187 12:43:22.537307 ==
6188 12:43:22.544468 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6189 12:43:22.550799 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6190 12:43:22.553755 [CA 0] Center 36 (8~64) winsize 57
6191 12:43:22.556893 [CA 1] Center 36 (8~64) winsize 57
6192 12:43:22.560522 [CA 2] Center 36 (8~64) winsize 57
6193 12:43:22.563460 [CA 3] Center 36 (8~64) winsize 57
6194 12:43:22.567778 [CA 4] Center 36 (8~64) winsize 57
6195 12:43:22.570283 [CA 5] Center 36 (8~64) winsize 57
6196 12:43:22.570360
6197 12:43:22.573350 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6198 12:43:22.573419
6199 12:43:22.576905 [CATrainingPosCal] consider 1 rank data
6200 12:43:22.579843 u2DelayCellTimex100 = 270/100 ps
6201 12:43:22.583736 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6202 12:43:22.587272 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6203 12:43:22.590154 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6204 12:43:22.593253 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6205 12:43:22.596213 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6206 12:43:22.600264 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6207 12:43:22.600333
6208 12:43:22.606060 CA PerBit enable=1, Macro0, CA PI delay=36
6209 12:43:22.606129
6210 12:43:22.609589 [CBTSetCACLKResult] CA Dly = 36
6211 12:43:22.609659 CS Dly: 1 (0~32)
6212 12:43:22.609720 ==
6213 12:43:22.612955 Dram Type= 6, Freq= 0, CH_0, rank 1
6214 12:43:22.616510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6215 12:43:22.616581 ==
6216 12:43:22.623185 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6217 12:43:22.629461 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6218 12:43:22.632801 [CA 0] Center 36 (8~64) winsize 57
6219 12:43:22.636685 [CA 1] Center 36 (8~64) winsize 57
6220 12:43:22.639746 [CA 2] Center 36 (8~64) winsize 57
6221 12:43:22.642256 [CA 3] Center 36 (8~64) winsize 57
6222 12:43:22.645761 [CA 4] Center 36 (8~64) winsize 57
6223 12:43:22.648959 [CA 5] Center 36 (8~64) winsize 57
6224 12:43:22.649026
6225 12:43:22.652418 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6226 12:43:22.652499
6227 12:43:22.655847 [CATrainingPosCal] consider 2 rank data
6228 12:43:22.659073 u2DelayCellTimex100 = 270/100 ps
6229 12:43:22.662745 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 12:43:22.665280 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 12:43:22.668694 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 12:43:22.671994 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 12:43:22.675588 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 12:43:22.678528 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 12:43:22.678608
6236 12:43:22.685275 CA PerBit enable=1, Macro0, CA PI delay=36
6237 12:43:22.685361
6238 12:43:22.685426 [CBTSetCACLKResult] CA Dly = 36
6239 12:43:22.688925 CS Dly: 1 (0~32)
6240 12:43:22.689004
6241 12:43:22.692706 ----->DramcWriteLeveling(PI) begin...
6242 12:43:22.692787 ==
6243 12:43:22.695388 Dram Type= 6, Freq= 0, CH_0, rank 0
6244 12:43:22.698814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6245 12:43:22.698895 ==
6246 12:43:22.701840 Write leveling (Byte 0): 40 => 8
6247 12:43:22.705155 Write leveling (Byte 1): 40 => 8
6248 12:43:22.708810 DramcWriteLeveling(PI) end<-----
6249 12:43:22.708890
6250 12:43:22.708952 ==
6251 12:43:22.711878 Dram Type= 6, Freq= 0, CH_0, rank 0
6252 12:43:22.714822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6253 12:43:22.718411 ==
6254 12:43:22.718491 [Gating] SW mode calibration
6255 12:43:22.728213 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6256 12:43:22.731406 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6257 12:43:22.735173 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6258 12:43:22.741209 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6259 12:43:22.745181 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6260 12:43:22.748318 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6261 12:43:22.754300 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6262 12:43:22.757741 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6263 12:43:22.760925 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6264 12:43:22.768134 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6265 12:43:22.770879 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6266 12:43:22.774607 Total UI for P1: 0, mck2ui 16
6267 12:43:22.777394 best dqsien dly found for B0: ( 0, 14, 24)
6268 12:43:22.780841 Total UI for P1: 0, mck2ui 16
6269 12:43:22.784027 best dqsien dly found for B1: ( 0, 14, 24)
6270 12:43:22.787563 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6271 12:43:22.790837 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6272 12:43:22.790918
6273 12:43:22.793970 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6274 12:43:22.800724 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6275 12:43:22.800804 [Gating] SW calibration Done
6276 12:43:22.800868 ==
6277 12:43:22.804015 Dram Type= 6, Freq= 0, CH_0, rank 0
6278 12:43:22.810195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6279 12:43:22.810276 ==
6280 12:43:22.810338 RX Vref Scan: 0
6281 12:43:22.810396
6282 12:43:22.813915 RX Vref 0 -> 0, step: 1
6283 12:43:22.813995
6284 12:43:22.817249 RX Delay -410 -> 252, step: 16
6285 12:43:22.820449 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6286 12:43:22.823956 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6287 12:43:22.830291 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6288 12:43:22.833690 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6289 12:43:22.836814 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6290 12:43:22.840758 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6291 12:43:22.846514 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6292 12:43:22.850617 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6293 12:43:22.853523 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6294 12:43:22.856977 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6295 12:43:22.863240 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6296 12:43:22.866424 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6297 12:43:22.869875 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6298 12:43:22.876351 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6299 12:43:22.880392 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6300 12:43:22.883022 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6301 12:43:22.883101 ==
6302 12:43:22.886484 Dram Type= 6, Freq= 0, CH_0, rank 0
6303 12:43:22.889370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6304 12:43:22.893058 ==
6305 12:43:22.893136 DQS Delay:
6306 12:43:22.893198 DQS0 = 35, DQS1 = 51
6307 12:43:22.896206 DQM Delay:
6308 12:43:22.896285 DQM0 = 6, DQM1 = 11
6309 12:43:22.899625 DQ Delay:
6310 12:43:22.899703 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6311 12:43:22.903245 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6312 12:43:22.906159 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6313 12:43:22.909290 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6314 12:43:22.909368
6315 12:43:22.909430
6316 12:43:22.909488 ==
6317 12:43:22.912821 Dram Type= 6, Freq= 0, CH_0, rank 0
6318 12:43:22.919543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6319 12:43:22.919637 ==
6320 12:43:22.919701
6321 12:43:22.919759
6322 12:43:22.919830 TX Vref Scan disable
6323 12:43:22.923145 == TX Byte 0 ==
6324 12:43:22.927227 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6325 12:43:22.929155 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6326 12:43:22.932474 == TX Byte 1 ==
6327 12:43:22.936627 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6328 12:43:22.939135 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6329 12:43:22.942749 ==
6330 12:43:22.945677 Dram Type= 6, Freq= 0, CH_0, rank 0
6331 12:43:22.949062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6332 12:43:22.949142 ==
6333 12:43:22.949203
6334 12:43:22.949262
6335 12:43:22.951979 TX Vref Scan disable
6336 12:43:22.952109 == TX Byte 0 ==
6337 12:43:22.955472 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6338 12:43:22.962089 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6339 12:43:22.962168 == TX Byte 1 ==
6340 12:43:22.965290 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6341 12:43:22.972537 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6342 12:43:22.972616
6343 12:43:22.972679 [DATLAT]
6344 12:43:22.972737 Freq=400, CH0 RK0
6345 12:43:22.975077
6346 12:43:22.975156 DATLAT Default: 0xf
6347 12:43:22.978518 0, 0xFFFF, sum = 0
6348 12:43:22.978599 1, 0xFFFF, sum = 0
6349 12:43:22.981866 2, 0xFFFF, sum = 0
6350 12:43:22.981945 3, 0xFFFF, sum = 0
6351 12:43:22.985094 4, 0xFFFF, sum = 0
6352 12:43:22.985174 5, 0xFFFF, sum = 0
6353 12:43:22.988818 6, 0xFFFF, sum = 0
6354 12:43:22.988899 7, 0xFFFF, sum = 0
6355 12:43:22.991414 8, 0xFFFF, sum = 0
6356 12:43:22.991494 9, 0xFFFF, sum = 0
6357 12:43:22.994878 10, 0xFFFF, sum = 0
6358 12:43:22.994958 11, 0xFFFF, sum = 0
6359 12:43:22.998267 12, 0xFFFF, sum = 0
6360 12:43:22.998347 13, 0x0, sum = 1
6361 12:43:23.001207 14, 0x0, sum = 2
6362 12:43:23.001286 15, 0x0, sum = 3
6363 12:43:23.004736 16, 0x0, sum = 4
6364 12:43:23.004817 best_step = 14
6365 12:43:23.004880
6366 12:43:23.004939 ==
6367 12:43:23.007943 Dram Type= 6, Freq= 0, CH_0, rank 0
6368 12:43:23.014245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6369 12:43:23.014326 ==
6370 12:43:23.014389 RX Vref Scan: 1
6371 12:43:23.014447
6372 12:43:23.017643 RX Vref 0 -> 0, step: 1
6373 12:43:23.017727
6374 12:43:23.020775 RX Delay -343 -> 252, step: 8
6375 12:43:23.020854
6376 12:43:23.023953 Set Vref, RX VrefLevel [Byte0]: 52
6377 12:43:23.027484 [Byte1]: 60
6378 12:43:23.031553
6379 12:43:23.031632 Final RX Vref Byte 0 = 52 to rank0
6380 12:43:23.034262 Final RX Vref Byte 1 = 60 to rank0
6381 12:43:23.037532 Final RX Vref Byte 0 = 52 to rank1
6382 12:43:23.041438 Final RX Vref Byte 1 = 60 to rank1==
6383 12:43:23.044062 Dram Type= 6, Freq= 0, CH_0, rank 0
6384 12:43:23.050700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6385 12:43:23.050781 ==
6386 12:43:23.050844 DQS Delay:
6387 12:43:23.054497 DQS0 = 40, DQS1 = 60
6388 12:43:23.054577 DQM Delay:
6389 12:43:23.057387 DQM0 = 6, DQM1 = 16
6390 12:43:23.057467 DQ Delay:
6391 12:43:23.060824 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6392 12:43:23.063763 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6393 12:43:23.063845 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6394 12:43:23.070315 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6395 12:43:23.070395
6396 12:43:23.070462
6397 12:43:23.076905 [DQSOSCAuto] RK0, (LSB)MR18= 0x8d81, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6398 12:43:23.080910 CH0 RK0: MR19=C0C, MR18=8D81
6399 12:43:23.086589 CH0_RK0: MR19=0xC0C, MR18=0x8D81, DQSOSC=392, MR23=63, INC=384, DEC=256
6400 12:43:23.086670 ==
6401 12:43:23.089923 Dram Type= 6, Freq= 0, CH_0, rank 1
6402 12:43:23.093307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6403 12:43:23.093388 ==
6404 12:43:23.096870 [Gating] SW mode calibration
6405 12:43:23.103228 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6406 12:43:23.109781 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6407 12:43:23.113104 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6408 12:43:23.116426 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6409 12:43:23.122711 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6410 12:43:23.126052 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6411 12:43:23.129518 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6412 12:43:23.135913 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6413 12:43:23.139934 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6414 12:43:23.142547 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6415 12:43:23.149272 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6416 12:43:23.152453 Total UI for P1: 0, mck2ui 16
6417 12:43:23.155602 best dqsien dly found for B0: ( 0, 14, 24)
6418 12:43:23.159027 Total UI for P1: 0, mck2ui 16
6419 12:43:23.162696 best dqsien dly found for B1: ( 0, 14, 24)
6420 12:43:23.165420 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6421 12:43:23.169258 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6422 12:43:23.169338
6423 12:43:23.172011 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6424 12:43:23.175697 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6425 12:43:23.178459 [Gating] SW calibration Done
6426 12:43:23.178543 ==
6427 12:43:23.181722 Dram Type= 6, Freq= 0, CH_0, rank 1
6428 12:43:23.185357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6429 12:43:23.188830 ==
6430 12:43:23.188909 RX Vref Scan: 0
6431 12:43:23.188973
6432 12:43:23.191893 RX Vref 0 -> 0, step: 1
6433 12:43:23.191973
6434 12:43:23.195180 RX Delay -410 -> 252, step: 16
6435 12:43:23.198572 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6436 12:43:23.202030 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6437 12:43:23.205554 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6438 12:43:23.211545 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6439 12:43:23.214613 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6440 12:43:23.218219 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6441 12:43:23.225613 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6442 12:43:23.228188 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6443 12:43:23.230996 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6444 12:43:23.234760 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6445 12:43:23.241006 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6446 12:43:23.244142 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6447 12:43:23.247524 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6448 12:43:23.251627 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6449 12:43:23.257593 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6450 12:43:23.260568 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6451 12:43:23.260648 ==
6452 12:43:23.264200 Dram Type= 6, Freq= 0, CH_0, rank 1
6453 12:43:23.267191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6454 12:43:23.267272 ==
6455 12:43:23.270471 DQS Delay:
6456 12:43:23.270552 DQS0 = 35, DQS1 = 51
6457 12:43:23.273994 DQM Delay:
6458 12:43:23.274073 DQM0 = 7, DQM1 = 9
6459 12:43:23.274136 DQ Delay:
6460 12:43:23.277769 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6461 12:43:23.280911 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6462 12:43:23.284007 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6463 12:43:23.287691 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6464 12:43:23.287771
6465 12:43:23.287834
6466 12:43:23.287892 ==
6467 12:43:23.290275 Dram Type= 6, Freq= 0, CH_0, rank 1
6468 12:43:23.297223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6469 12:43:23.297304 ==
6470 12:43:23.297367
6471 12:43:23.297425
6472 12:43:23.297482 TX Vref Scan disable
6473 12:43:23.300238 == TX Byte 0 ==
6474 12:43:23.303506 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6475 12:43:23.307218 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6476 12:43:23.310145 == TX Byte 1 ==
6477 12:43:23.313666 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6478 12:43:23.317280 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6479 12:43:23.317359 ==
6480 12:43:23.319937 Dram Type= 6, Freq= 0, CH_0, rank 1
6481 12:43:23.326505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6482 12:43:23.326586 ==
6483 12:43:23.326650
6484 12:43:23.326708
6485 12:43:23.326764 TX Vref Scan disable
6486 12:43:23.330707 == TX Byte 0 ==
6487 12:43:23.333363 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6488 12:43:23.336649 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6489 12:43:23.340482 == TX Byte 1 ==
6490 12:43:23.343100 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6491 12:43:23.346133 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6492 12:43:23.346214
6493 12:43:23.349662 [DATLAT]
6494 12:43:23.349743 Freq=400, CH0 RK1
6495 12:43:23.349807
6496 12:43:23.352760 DATLAT Default: 0xe
6497 12:43:23.352840 0, 0xFFFF, sum = 0
6498 12:43:23.356139 1, 0xFFFF, sum = 0
6499 12:43:23.356222 2, 0xFFFF, sum = 0
6500 12:43:23.359688 3, 0xFFFF, sum = 0
6501 12:43:23.359771 4, 0xFFFF, sum = 0
6502 12:43:23.362712 5, 0xFFFF, sum = 0
6503 12:43:23.366348 6, 0xFFFF, sum = 0
6504 12:43:23.366430 7, 0xFFFF, sum = 0
6505 12:43:23.369380 8, 0xFFFF, sum = 0
6506 12:43:23.369462 9, 0xFFFF, sum = 0
6507 12:43:23.372974 10, 0xFFFF, sum = 0
6508 12:43:23.373056 11, 0xFFFF, sum = 0
6509 12:43:23.376062 12, 0xFFFF, sum = 0
6510 12:43:23.376157 13, 0x0, sum = 1
6511 12:43:23.378966 14, 0x0, sum = 2
6512 12:43:23.379049 15, 0x0, sum = 3
6513 12:43:23.383301 16, 0x0, sum = 4
6514 12:43:23.383383 best_step = 14
6515 12:43:23.383447
6516 12:43:23.383506 ==
6517 12:43:23.386088 Dram Type= 6, Freq= 0, CH_0, rank 1
6518 12:43:23.389215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6519 12:43:23.392491 ==
6520 12:43:23.392573 RX Vref Scan: 0
6521 12:43:23.392637
6522 12:43:23.395570 RX Vref 0 -> 0, step: 1
6523 12:43:23.395651
6524 12:43:23.399001 RX Delay -343 -> 252, step: 8
6525 12:43:23.405201 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6526 12:43:23.409179 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6527 12:43:23.411753 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6528 12:43:23.415554 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6529 12:43:23.421743 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6530 12:43:23.425398 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6531 12:43:23.428761 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6532 12:43:23.432095 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6533 12:43:23.438606 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6534 12:43:23.441281 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6535 12:43:23.445051 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6536 12:43:23.448199 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6537 12:43:23.454904 iDelay=209, Bit 12, Center -36 (-279 ~ 208) 488
6538 12:43:23.458436 iDelay=209, Bit 13, Center -36 (-279 ~ 208) 488
6539 12:43:23.461446 iDelay=209, Bit 14, Center -36 (-279 ~ 208) 488
6540 12:43:23.467909 iDelay=209, Bit 15, Center -36 (-279 ~ 208) 488
6541 12:43:23.467991 ==
6542 12:43:23.471566 Dram Type= 6, Freq= 0, CH_0, rank 1
6543 12:43:23.475025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6544 12:43:23.475107 ==
6545 12:43:23.475172 DQS Delay:
6546 12:43:23.477964 DQS0 = 44, DQS1 = 60
6547 12:43:23.478045 DQM Delay:
6548 12:43:23.481130 DQM0 = 9, DQM1 = 16
6549 12:43:23.481211 DQ Delay:
6550 12:43:23.484638 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6551 12:43:23.487841 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6552 12:43:23.490902 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6553 12:43:23.494099 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6554 12:43:23.494180
6555 12:43:23.494245
6556 12:43:23.500647 [DQSOSCAuto] RK1, (LSB)MR18= 0x8a84, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6557 12:43:23.504057 CH0 RK1: MR19=C0C, MR18=8A84
6558 12:43:23.510677 CH0_RK1: MR19=0xC0C, MR18=0x8A84, DQSOSC=392, MR23=63, INC=384, DEC=256
6559 12:43:23.514014 [RxdqsGatingPostProcess] freq 400
6560 12:43:23.520661 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6561 12:43:23.523958 best DQS0 dly(2T, 0.5T) = (0, 10)
6562 12:43:23.526739 best DQS1 dly(2T, 0.5T) = (0, 10)
6563 12:43:23.530180 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6564 12:43:23.533769 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6565 12:43:23.533850 best DQS0 dly(2T, 0.5T) = (0, 10)
6566 12:43:23.537397 best DQS1 dly(2T, 0.5T) = (0, 10)
6567 12:43:23.540206 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6568 12:43:23.543725 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6569 12:43:23.546987 Pre-setting of DQS Precalculation
6570 12:43:23.553217 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6571 12:43:23.553299 ==
6572 12:43:23.556429 Dram Type= 6, Freq= 0, CH_1, rank 0
6573 12:43:23.559845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6574 12:43:23.559927 ==
6575 12:43:23.566460 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6576 12:43:23.573193 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6577 12:43:23.576275 [CA 0] Center 36 (8~64) winsize 57
6578 12:43:23.576356 [CA 1] Center 36 (8~64) winsize 57
6579 12:43:23.579908 [CA 2] Center 36 (8~64) winsize 57
6580 12:43:23.582832 [CA 3] Center 36 (8~64) winsize 57
6581 12:43:23.586610 [CA 4] Center 36 (8~64) winsize 57
6582 12:43:23.589847 [CA 5] Center 36 (8~64) winsize 57
6583 12:43:23.589927
6584 12:43:23.593376 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6585 12:43:23.593457
6586 12:43:23.599595 [CATrainingPosCal] consider 1 rank data
6587 12:43:23.599676 u2DelayCellTimex100 = 270/100 ps
6588 12:43:23.606173 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6589 12:43:23.609147 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6590 12:43:23.612468 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6591 12:43:23.616282 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6592 12:43:23.619529 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6593 12:43:23.622945 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6594 12:43:23.623026
6595 12:43:23.626204 CA PerBit enable=1, Macro0, CA PI delay=36
6596 12:43:23.626285
6597 12:43:23.629058 [CBTSetCACLKResult] CA Dly = 36
6598 12:43:23.632296 CS Dly: 1 (0~32)
6599 12:43:23.632376 ==
6600 12:43:23.635406 Dram Type= 6, Freq= 0, CH_1, rank 1
6601 12:43:23.638672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6602 12:43:23.638753 ==
6603 12:43:23.645446 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6604 12:43:23.652509 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6605 12:43:23.655455 [CA 0] Center 36 (8~64) winsize 57
6606 12:43:23.655536 [CA 1] Center 36 (8~64) winsize 57
6607 12:43:23.658426 [CA 2] Center 36 (8~64) winsize 57
6608 12:43:23.662102 [CA 3] Center 36 (8~64) winsize 57
6609 12:43:23.665058 [CA 4] Center 36 (8~64) winsize 57
6610 12:43:23.668610 [CA 5] Center 36 (8~64) winsize 57
6611 12:43:23.668692
6612 12:43:23.671779 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6613 12:43:23.671860
6614 12:43:23.678222 [CATrainingPosCal] consider 2 rank data
6615 12:43:23.678303 u2DelayCellTimex100 = 270/100 ps
6616 12:43:23.684691 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 12:43:23.687984 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 12:43:23.691317 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 12:43:23.694895 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 12:43:23.697813 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 12:43:23.701089 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 12:43:23.701170
6623 12:43:23.704816 CA PerBit enable=1, Macro0, CA PI delay=36
6624 12:43:23.704898
6625 12:43:23.707742 [CBTSetCACLKResult] CA Dly = 36
6626 12:43:23.711281 CS Dly: 1 (0~32)
6627 12:43:23.711363
6628 12:43:23.714626 ----->DramcWriteLeveling(PI) begin...
6629 12:43:23.714709 ==
6630 12:43:23.717582 Dram Type= 6, Freq= 0, CH_1, rank 0
6631 12:43:23.721106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6632 12:43:23.721188 ==
6633 12:43:23.724811 Write leveling (Byte 0): 40 => 8
6634 12:43:23.727676 Write leveling (Byte 1): 40 => 8
6635 12:43:23.730771 DramcWriteLeveling(PI) end<-----
6636 12:43:23.730851
6637 12:43:23.730916 ==
6638 12:43:23.734506 Dram Type= 6, Freq= 0, CH_1, rank 0
6639 12:43:23.737724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6640 12:43:23.737805 ==
6641 12:43:23.741138 [Gating] SW mode calibration
6642 12:43:23.747374 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6643 12:43:23.754533 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6644 12:43:23.757453 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6645 12:43:23.760906 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6646 12:43:23.767184 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6647 12:43:23.771056 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6648 12:43:23.773806 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6649 12:43:23.780258 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6650 12:43:23.784163 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6651 12:43:23.787171 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6652 12:43:23.793781 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6653 12:43:23.796618 Total UI for P1: 0, mck2ui 16
6654 12:43:23.800226 best dqsien dly found for B0: ( 0, 14, 24)
6655 12:43:23.803563 Total UI for P1: 0, mck2ui 16
6656 12:43:23.806550 best dqsien dly found for B1: ( 0, 14, 24)
6657 12:43:23.810293 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6658 12:43:23.813139 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6659 12:43:23.813220
6660 12:43:23.816533 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6661 12:43:23.820230 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6662 12:43:23.823066 [Gating] SW calibration Done
6663 12:43:23.823147 ==
6664 12:43:23.826417 Dram Type= 6, Freq= 0, CH_1, rank 0
6665 12:43:23.829767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6666 12:43:23.833012 ==
6667 12:43:23.833093 RX Vref Scan: 0
6668 12:43:23.833157
6669 12:43:23.836212 RX Vref 0 -> 0, step: 1
6670 12:43:23.836293
6671 12:43:23.839312 RX Delay -410 -> 252, step: 16
6672 12:43:23.842763 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6673 12:43:23.845991 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6674 12:43:23.849524 iDelay=230, Bit 2, Center -43 (-282 ~ 197) 480
6675 12:43:23.855687 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6676 12:43:23.859449 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6677 12:43:23.862336 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6678 12:43:23.869593 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6679 12:43:23.872781 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6680 12:43:23.875629 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6681 12:43:23.878698 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6682 12:43:23.885835 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6683 12:43:23.888672 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6684 12:43:23.892298 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6685 12:43:23.895670 iDelay=230, Bit 13, Center -19 (-266 ~ 229) 496
6686 12:43:23.901994 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6687 12:43:23.905401 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6688 12:43:23.905482 ==
6689 12:43:23.909147 Dram Type= 6, Freq= 0, CH_1, rank 0
6690 12:43:23.911909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6691 12:43:23.911991 ==
6692 12:43:23.915224 DQS Delay:
6693 12:43:23.915304 DQS0 = 43, DQS1 = 51
6694 12:43:23.918531 DQM Delay:
6695 12:43:23.918611 DQM0 = 13, DQM1 = 15
6696 12:43:23.921709 DQ Delay:
6697 12:43:23.921790 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6698 12:43:23.925144 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6699 12:43:23.928054 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6700 12:43:23.931359 DQ12 =32, DQ13 =32, DQ14 =16, DQ15 =16
6701 12:43:23.931439
6702 12:43:23.931536
6703 12:43:23.931626 ==
6704 12:43:23.934889 Dram Type= 6, Freq= 0, CH_1, rank 0
6705 12:43:23.941189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6706 12:43:23.941270 ==
6707 12:43:23.941335
6708 12:43:23.941394
6709 12:43:23.941451 TX Vref Scan disable
6710 12:43:23.944432 == TX Byte 0 ==
6711 12:43:23.947869 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6712 12:43:23.951175 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6713 12:43:23.954709 == TX Byte 1 ==
6714 12:43:23.957705 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6715 12:43:23.961188 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6716 12:43:23.964518 ==
6717 12:43:23.968150 Dram Type= 6, Freq= 0, CH_1, rank 0
6718 12:43:23.970801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6719 12:43:23.970882 ==
6720 12:43:23.970946
6721 12:43:23.971047
6722 12:43:23.974254 TX Vref Scan disable
6723 12:43:23.974335 == TX Byte 0 ==
6724 12:43:23.977373 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6725 12:43:23.984036 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6726 12:43:23.984131 == TX Byte 1 ==
6727 12:43:23.987105 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6728 12:43:23.994194 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6729 12:43:23.994275
6730 12:43:23.994339 [DATLAT]
6731 12:43:23.994399 Freq=400, CH1 RK0
6732 12:43:23.994457
6733 12:43:23.996982 DATLAT Default: 0xf
6734 12:43:24.000993 0, 0xFFFF, sum = 0
6735 12:43:24.001075 1, 0xFFFF, sum = 0
6736 12:43:24.004149 2, 0xFFFF, sum = 0
6737 12:43:24.004230 3, 0xFFFF, sum = 0
6738 12:43:24.007823 4, 0xFFFF, sum = 0
6739 12:43:24.007905 5, 0xFFFF, sum = 0
6740 12:43:24.010322 6, 0xFFFF, sum = 0
6741 12:43:24.010404 7, 0xFFFF, sum = 0
6742 12:43:24.013852 8, 0xFFFF, sum = 0
6743 12:43:24.013962 9, 0xFFFF, sum = 0
6744 12:43:24.016800 10, 0xFFFF, sum = 0
6745 12:43:24.016882 11, 0xFFFF, sum = 0
6746 12:43:24.020348 12, 0xFFFF, sum = 0
6747 12:43:24.020430 13, 0x0, sum = 1
6748 12:43:24.023597 14, 0x0, sum = 2
6749 12:43:24.023680 15, 0x0, sum = 3
6750 12:43:24.027751 16, 0x0, sum = 4
6751 12:43:24.027834 best_step = 14
6752 12:43:24.027898
6753 12:43:24.027958 ==
6754 12:43:24.030000 Dram Type= 6, Freq= 0, CH_1, rank 0
6755 12:43:24.036739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6756 12:43:24.036820 ==
6757 12:43:24.036885 RX Vref Scan: 1
6758 12:43:24.036944
6759 12:43:24.040158 RX Vref 0 -> 0, step: 1
6760 12:43:24.040239
6761 12:43:24.043237 RX Delay -343 -> 252, step: 8
6762 12:43:24.043318
6763 12:43:24.046676 Set Vref, RX VrefLevel [Byte0]: 53
6764 12:43:24.049727 [Byte1]: 48
6765 12:43:24.054030
6766 12:43:24.054110 Final RX Vref Byte 0 = 53 to rank0
6767 12:43:24.056561 Final RX Vref Byte 1 = 48 to rank0
6768 12:43:24.059766 Final RX Vref Byte 0 = 53 to rank1
6769 12:43:24.062789 Final RX Vref Byte 1 = 48 to rank1==
6770 12:43:24.066105 Dram Type= 6, Freq= 0, CH_1, rank 0
6771 12:43:24.073704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6772 12:43:24.073812 ==
6773 12:43:24.073910 DQS Delay:
6774 12:43:24.076183 DQS0 = 44, DQS1 = 56
6775 12:43:24.076263 DQM Delay:
6776 12:43:24.076328 DQM0 = 10, DQM1 = 14
6777 12:43:24.079506 DQ Delay:
6778 12:43:24.083521 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =12
6779 12:43:24.086724 DQ4 =4, DQ5 =16, DQ6 =20, DQ7 =4
6780 12:43:24.086805 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6781 12:43:24.089584 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =20
6782 12:43:24.093040
6783 12:43:24.093160
6784 12:43:24.099197 [DQSOSCAuto] RK0, (LSB)MR18= 0x648b, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 397 ps
6785 12:43:24.103011 CH1 RK0: MR19=C0C, MR18=648B
6786 12:43:24.109415 CH1_RK0: MR19=0xC0C, MR18=0x648B, DQSOSC=392, MR23=63, INC=384, DEC=256
6787 12:43:24.109497 ==
6788 12:43:24.112898 Dram Type= 6, Freq= 0, CH_1, rank 1
6789 12:43:24.115741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6790 12:43:24.115822 ==
6791 12:43:24.118763 [Gating] SW mode calibration
6792 12:43:24.125874 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6793 12:43:24.132074 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6794 12:43:24.135353 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6795 12:43:24.139273 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6796 12:43:24.145522 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6797 12:43:24.148732 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6798 12:43:24.152225 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6799 12:43:24.158488 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6800 12:43:24.161904 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6801 12:43:24.165616 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6802 12:43:24.171363 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6803 12:43:24.174706 Total UI for P1: 0, mck2ui 16
6804 12:43:24.178376 best dqsien dly found for B0: ( 0, 14, 24)
6805 12:43:24.181719 Total UI for P1: 0, mck2ui 16
6806 12:43:24.184368 best dqsien dly found for B1: ( 0, 14, 24)
6807 12:43:24.188111 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6808 12:43:24.191764 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6809 12:43:24.191845
6810 12:43:24.194683 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6811 12:43:24.198309 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6812 12:43:24.201337 [Gating] SW calibration Done
6813 12:43:24.201418 ==
6814 12:43:24.205054 Dram Type= 6, Freq= 0, CH_1, rank 1
6815 12:43:24.207796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6816 12:43:24.207878 ==
6817 12:43:24.211108 RX Vref Scan: 0
6818 12:43:24.211189
6819 12:43:24.214659 RX Vref 0 -> 0, step: 1
6820 12:43:24.214739
6821 12:43:24.214803 RX Delay -410 -> 252, step: 16
6822 12:43:24.221800 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6823 12:43:24.224915 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6824 12:43:24.227754 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6825 12:43:24.234563 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6826 12:43:24.237716 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6827 12:43:24.240934 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6828 12:43:24.244497 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6829 12:43:24.250815 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6830 12:43:24.254539 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6831 12:43:24.257228 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6832 12:43:24.260604 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6833 12:43:24.267017 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6834 12:43:24.270555 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6835 12:43:24.274236 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6836 12:43:24.277513 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6837 12:43:24.283766 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6838 12:43:24.283848 ==
6839 12:43:24.287140 Dram Type= 6, Freq= 0, CH_1, rank 1
6840 12:43:24.290254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6841 12:43:24.290336 ==
6842 12:43:24.294008 DQS Delay:
6843 12:43:24.294088 DQS0 = 43, DQS1 = 51
6844 12:43:24.294154 DQM Delay:
6845 12:43:24.296735 DQM0 = 10, DQM1 = 13
6846 12:43:24.296815 DQ Delay:
6847 12:43:24.300326 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6848 12:43:24.303612 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6849 12:43:24.306563 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6850 12:43:24.310301 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6851 12:43:24.310383
6852 12:43:24.310447
6853 12:43:24.310506 ==
6854 12:43:24.313073 Dram Type= 6, Freq= 0, CH_1, rank 1
6855 12:43:24.316680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6856 12:43:24.319739 ==
6857 12:43:24.319820
6858 12:43:24.319883
6859 12:43:24.319942 TX Vref Scan disable
6860 12:43:24.323136 == TX Byte 0 ==
6861 12:43:24.326606 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6862 12:43:24.329441 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6863 12:43:24.333121 == TX Byte 1 ==
6864 12:43:24.336464 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6865 12:43:24.339657 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6866 12:43:24.339738 ==
6867 12:43:24.342826 Dram Type= 6, Freq= 0, CH_1, rank 1
6868 12:43:24.349547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6869 12:43:24.349628 ==
6870 12:43:24.349692
6871 12:43:24.349752
6872 12:43:24.349809 TX Vref Scan disable
6873 12:43:24.352995 == TX Byte 0 ==
6874 12:43:24.356505 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6875 12:43:24.359349 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6876 12:43:24.362535 == TX Byte 1 ==
6877 12:43:24.366019 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6878 12:43:24.369194 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6879 12:43:24.369275
6880 12:43:24.373109 [DATLAT]
6881 12:43:24.373190 Freq=400, CH1 RK1
6882 12:43:24.373255
6883 12:43:24.376283 DATLAT Default: 0xe
6884 12:43:24.376364 0, 0xFFFF, sum = 0
6885 12:43:24.378850 1, 0xFFFF, sum = 0
6886 12:43:24.378933 2, 0xFFFF, sum = 0
6887 12:43:24.382202 3, 0xFFFF, sum = 0
6888 12:43:24.382284 4, 0xFFFF, sum = 0
6889 12:43:24.385974 5, 0xFFFF, sum = 0
6890 12:43:24.386056 6, 0xFFFF, sum = 0
6891 12:43:24.389334 7, 0xFFFF, sum = 0
6892 12:43:24.389417 8, 0xFFFF, sum = 0
6893 12:43:24.392269 9, 0xFFFF, sum = 0
6894 12:43:24.395280 10, 0xFFFF, sum = 0
6895 12:43:24.395362 11, 0xFFFF, sum = 0
6896 12:43:24.399163 12, 0xFFFF, sum = 0
6897 12:43:24.399245 13, 0x0, sum = 1
6898 12:43:24.402189 14, 0x0, sum = 2
6899 12:43:24.402271 15, 0x0, sum = 3
6900 12:43:24.405443 16, 0x0, sum = 4
6901 12:43:24.405525 best_step = 14
6902 12:43:24.405598
6903 12:43:24.405659 ==
6904 12:43:24.409040 Dram Type= 6, Freq= 0, CH_1, rank 1
6905 12:43:24.412021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6906 12:43:24.412111 ==
6907 12:43:24.414994 RX Vref Scan: 0
6908 12:43:24.415074
6909 12:43:24.418645 RX Vref 0 -> 0, step: 1
6910 12:43:24.418725
6911 12:43:24.418790 RX Delay -343 -> 252, step: 8
6912 12:43:24.427245 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6913 12:43:24.430538 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6914 12:43:24.433634 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6915 12:43:24.440451 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6916 12:43:24.443702 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6917 12:43:24.446902 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6918 12:43:24.450116 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6919 12:43:24.456657 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6920 12:43:24.460205 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6921 12:43:24.463537 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6922 12:43:24.466723 iDelay=217, Bit 10, Center -40 (-279 ~ 200) 480
6923 12:43:24.473258 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6924 12:43:24.476713 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6925 12:43:24.480152 iDelay=217, Bit 13, Center -32 (-271 ~ 208) 480
6926 12:43:24.483388 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6927 12:43:24.489796 iDelay=217, Bit 15, Center -32 (-271 ~ 208) 480
6928 12:43:24.489877 ==
6929 12:43:24.492915 Dram Type= 6, Freq= 0, CH_1, rank 1
6930 12:43:24.496357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6931 12:43:24.496439 ==
6932 12:43:24.499766 DQS Delay:
6933 12:43:24.499848 DQS0 = 48, DQS1 = 56
6934 12:43:24.499912 DQM Delay:
6935 12:43:24.503162 DQM0 = 11, DQM1 = 15
6936 12:43:24.503241 DQ Delay:
6937 12:43:24.506082 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
6938 12:43:24.509308 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6939 12:43:24.512764 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6940 12:43:24.515963 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =24
6941 12:43:24.516073
6942 12:43:24.516161
6943 12:43:24.525865 [DQSOSCAuto] RK1, (LSB)MR18= 0x6ca4, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
6944 12:43:24.525965 CH1 RK1: MR19=C0C, MR18=6CA4
6945 12:43:24.533472 CH1_RK1: MR19=0xC0C, MR18=0x6CA4, DQSOSC=389, MR23=63, INC=390, DEC=260
6946 12:43:24.535958 [RxdqsGatingPostProcess] freq 400
6947 12:43:24.542139 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6948 12:43:24.545742 best DQS0 dly(2T, 0.5T) = (0, 10)
6949 12:43:24.549025 best DQS1 dly(2T, 0.5T) = (0, 10)
6950 12:43:24.552329 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6951 12:43:24.555637 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6952 12:43:24.558786 best DQS0 dly(2T, 0.5T) = (0, 10)
6953 12:43:24.562521 best DQS1 dly(2T, 0.5T) = (0, 10)
6954 12:43:24.565289 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6955 12:43:24.568823 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6956 12:43:24.568894 Pre-setting of DQS Precalculation
6957 12:43:24.575294 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6958 12:43:24.581789 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6959 12:43:24.588420 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6960 12:43:24.588493
6961 12:43:24.588553
6962 12:43:24.591698 [Calibration Summary] 800 Mbps
6963 12:43:24.595220 CH 0, Rank 0
6964 12:43:24.595298 SW Impedance : PASS
6965 12:43:24.598300 DUTY Scan : NO K
6966 12:43:24.601780 ZQ Calibration : PASS
6967 12:43:24.601850 Jitter Meter : NO K
6968 12:43:24.605211 CBT Training : PASS
6969 12:43:24.608425 Write leveling : PASS
6970 12:43:24.608506 RX DQS gating : PASS
6971 12:43:24.611668 RX DQ/DQS(RDDQC) : PASS
6972 12:43:24.611738 TX DQ/DQS : PASS
6973 12:43:24.615076 RX DATLAT : PASS
6974 12:43:24.618704 RX DQ/DQS(Engine): PASS
6975 12:43:24.618804 TX OE : NO K
6976 12:43:24.621648 All Pass.
6977 12:43:24.621727
6978 12:43:24.621791 CH 0, Rank 1
6979 12:43:24.624887 SW Impedance : PASS
6980 12:43:24.624967 DUTY Scan : NO K
6981 12:43:24.628575 ZQ Calibration : PASS
6982 12:43:24.631970 Jitter Meter : NO K
6983 12:43:24.632088 CBT Training : PASS
6984 12:43:24.634742 Write leveling : NO K
6985 12:43:24.637821 RX DQS gating : PASS
6986 12:43:24.637904 RX DQ/DQS(RDDQC) : PASS
6987 12:43:24.641750 TX DQ/DQS : PASS
6988 12:43:24.644862 RX DATLAT : PASS
6989 12:43:24.644945 RX DQ/DQS(Engine): PASS
6990 12:43:24.648281 TX OE : NO K
6991 12:43:24.648365 All Pass.
6992 12:43:24.648449
6993 12:43:24.651735 CH 1, Rank 0
6994 12:43:24.651818 SW Impedance : PASS
6995 12:43:24.654328 DUTY Scan : NO K
6996 12:43:24.658333 ZQ Calibration : PASS
6997 12:43:24.658417 Jitter Meter : NO K
6998 12:43:24.660979 CBT Training : PASS
6999 12:43:24.664253 Write leveling : PASS
7000 12:43:24.664336 RX DQS gating : PASS
7001 12:43:24.667993 RX DQ/DQS(RDDQC) : PASS
7002 12:43:24.670723 TX DQ/DQS : PASS
7003 12:43:24.670806 RX DATLAT : PASS
7004 12:43:24.674060 RX DQ/DQS(Engine): PASS
7005 12:43:24.677543 TX OE : NO K
7006 12:43:24.677626 All Pass.
7007 12:43:24.677711
7008 12:43:24.677790 CH 1, Rank 1
7009 12:43:24.680849 SW Impedance : PASS
7010 12:43:24.684048 DUTY Scan : NO K
7011 12:43:24.684146 ZQ Calibration : PASS
7012 12:43:24.687842 Jitter Meter : NO K
7013 12:43:24.690439 CBT Training : PASS
7014 12:43:24.690522 Write leveling : NO K
7015 12:43:24.693988 RX DQS gating : PASS
7016 12:43:24.697463 RX DQ/DQS(RDDQC) : PASS
7017 12:43:24.697547 TX DQ/DQS : PASS
7018 12:43:24.700194 RX DATLAT : PASS
7019 12:43:24.704286 RX DQ/DQS(Engine): PASS
7020 12:43:24.704369 TX OE : NO K
7021 12:43:24.704454 All Pass.
7022 12:43:24.707389
7023 12:43:24.707472 DramC Write-DBI off
7024 12:43:24.710115 PER_BANK_REFRESH: Hybrid Mode
7025 12:43:24.710197 TX_TRACKING: ON
7026 12:43:24.720238 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7027 12:43:24.723730 [FAST_K] Save calibration result to emmc
7028 12:43:24.726600 dramc_set_vcore_voltage set vcore to 725000
7029 12:43:24.729827 Read voltage for 1600, 0
7030 12:43:24.729943 Vio18 = 0
7031 12:43:24.733443 Vcore = 725000
7032 12:43:24.733525 Vdram = 0
7033 12:43:24.733589 Vddq = 0
7034 12:43:24.736610 Vmddr = 0
7035 12:43:24.739744 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7036 12:43:24.746211 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7037 12:43:24.746294 MEM_TYPE=3, freq_sel=13
7038 12:43:24.749481 sv_algorithm_assistance_LP4_3733
7039 12:43:24.756160 ============ PULL DRAM RESETB DOWN ============
7040 12:43:24.759575 ========== PULL DRAM RESETB DOWN end =========
7041 12:43:24.763188 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7042 12:43:24.766297 ===================================
7043 12:43:24.769888 LPDDR4 DRAM CONFIGURATION
7044 12:43:24.773156 ===================================
7045 12:43:24.776127 EX_ROW_EN[0] = 0x0
7046 12:43:24.776209 EX_ROW_EN[1] = 0x0
7047 12:43:24.779828 LP4Y_EN = 0x0
7048 12:43:24.779910 WORK_FSP = 0x1
7049 12:43:24.782482 WL = 0x5
7050 12:43:24.782563 RL = 0x5
7051 12:43:24.785741 BL = 0x2
7052 12:43:24.785823 RPST = 0x0
7053 12:43:24.789073 RD_PRE = 0x0
7054 12:43:24.789154 WR_PRE = 0x1
7055 12:43:24.792688 WR_PST = 0x1
7056 12:43:24.792770 DBI_WR = 0x0
7057 12:43:24.796002 DBI_RD = 0x0
7058 12:43:24.796115 OTF = 0x1
7059 12:43:24.799397 ===================================
7060 12:43:24.802703 ===================================
7061 12:43:24.805576 ANA top config
7062 12:43:24.808806 ===================================
7063 12:43:24.812184 DLL_ASYNC_EN = 0
7064 12:43:24.812266 ALL_SLAVE_EN = 0
7065 12:43:24.815730 NEW_RANK_MODE = 1
7066 12:43:24.818752 DLL_IDLE_MODE = 1
7067 12:43:24.822022 LP45_APHY_COMB_EN = 1
7068 12:43:24.825480 TX_ODT_DIS = 0
7069 12:43:24.825562 NEW_8X_MODE = 1
7070 12:43:24.829107 ===================================
7071 12:43:24.831757 ===================================
7072 12:43:24.835178 data_rate = 3200
7073 12:43:24.840201 CKR = 1
7074 12:43:24.841907 DQ_P2S_RATIO = 8
7075 12:43:24.844811 ===================================
7076 12:43:24.848248 CA_P2S_RATIO = 8
7077 12:43:24.851599 DQ_CA_OPEN = 0
7078 12:43:24.851681 DQ_SEMI_OPEN = 0
7079 12:43:24.855321 CA_SEMI_OPEN = 0
7080 12:43:24.858168 CA_FULL_RATE = 0
7081 12:43:24.861513 DQ_CKDIV4_EN = 0
7082 12:43:24.865094 CA_CKDIV4_EN = 0
7083 12:43:24.868156 CA_PREDIV_EN = 0
7084 12:43:24.871482 PH8_DLY = 12
7085 12:43:24.871567 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7086 12:43:24.874529 DQ_AAMCK_DIV = 4
7087 12:43:24.877745 CA_AAMCK_DIV = 4
7088 12:43:24.881481 CA_ADMCK_DIV = 4
7089 12:43:24.884626 DQ_TRACK_CA_EN = 0
7090 12:43:24.888001 CA_PICK = 1600
7091 12:43:24.891206 CA_MCKIO = 1600
7092 12:43:24.891279 MCKIO_SEMI = 0
7093 12:43:24.893994 PLL_FREQ = 3068
7094 12:43:24.897886 DQ_UI_PI_RATIO = 32
7095 12:43:24.901135 CA_UI_PI_RATIO = 0
7096 12:43:24.904243 ===================================
7097 12:43:24.907616 ===================================
7098 12:43:24.910520 memory_type:LPDDR4
7099 12:43:24.910593 GP_NUM : 10
7100 12:43:24.914520 SRAM_EN : 1
7101 12:43:24.917360 MD32_EN : 0
7102 12:43:24.920762 ===================================
7103 12:43:24.920842 [ANA_INIT] >>>>>>>>>>>>>>
7104 12:43:24.923790 <<<<<< [CONFIGURE PHASE]: ANA_TX
7105 12:43:24.926931 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7106 12:43:24.930758 ===================================
7107 12:43:24.933982 data_rate = 3200,PCW = 0X7600
7108 12:43:24.937272 ===================================
7109 12:43:24.940141 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7110 12:43:24.947094 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7111 12:43:24.950468 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7112 12:43:24.956798 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7113 12:43:24.960434 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7114 12:43:24.963004 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7115 12:43:24.966229 [ANA_INIT] flow start
7116 12:43:24.966311 [ANA_INIT] PLL >>>>>>>>
7117 12:43:24.969902 [ANA_INIT] PLL <<<<<<<<
7118 12:43:24.973072 [ANA_INIT] MIDPI >>>>>>>>
7119 12:43:24.973156 [ANA_INIT] MIDPI <<<<<<<<
7120 12:43:24.976239 [ANA_INIT] DLL >>>>>>>>
7121 12:43:24.979580 [ANA_INIT] DLL <<<<<<<<
7122 12:43:24.979661 [ANA_INIT] flow end
7123 12:43:24.986869 ============ LP4 DIFF to SE enter ============
7124 12:43:24.989304 ============ LP4 DIFF to SE exit ============
7125 12:43:24.992721 [ANA_INIT] <<<<<<<<<<<<<
7126 12:43:24.996059 [Flow] Enable top DCM control >>>>>
7127 12:43:24.999705 [Flow] Enable top DCM control <<<<<
7128 12:43:24.999785 Enable DLL master slave shuffle
7129 12:43:25.006585 ==============================================================
7130 12:43:25.009572 Gating Mode config
7131 12:43:25.012754 ==============================================================
7132 12:43:25.015924 Config description:
7133 12:43:25.025750 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7134 12:43:25.032949 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7135 12:43:25.035674 SELPH_MODE 0: By rank 1: By Phase
7136 12:43:25.042862 ==============================================================
7137 12:43:25.045195 GAT_TRACK_EN = 1
7138 12:43:25.048450 RX_GATING_MODE = 2
7139 12:43:25.052154 RX_GATING_TRACK_MODE = 2
7140 12:43:25.055422 SELPH_MODE = 1
7141 12:43:25.058654 PICG_EARLY_EN = 1
7142 12:43:25.062149 VALID_LAT_VALUE = 1
7143 12:43:25.065443 ==============================================================
7144 12:43:25.068416 Enter into Gating configuration >>>>
7145 12:43:25.071890 Exit from Gating configuration <<<<
7146 12:43:25.075282 Enter into DVFS_PRE_config >>>>>
7147 12:43:25.088274 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7148 12:43:25.088358 Exit from DVFS_PRE_config <<<<<
7149 12:43:25.091907 Enter into PICG configuration >>>>
7150 12:43:25.094945 Exit from PICG configuration <<<<
7151 12:43:25.097862 [RX_INPUT] configuration >>>>>
7152 12:43:25.101468 [RX_INPUT] configuration <<<<<
7153 12:43:25.107848 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7154 12:43:25.111436 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7155 12:43:25.117692 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7156 12:43:25.124475 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7157 12:43:25.130741 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7158 12:43:25.137682 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7159 12:43:25.141604 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7160 12:43:25.144240 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7161 12:43:25.150816 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7162 12:43:25.154263 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7163 12:43:25.157778 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7164 12:43:25.160902 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7165 12:43:25.164178 ===================================
7166 12:43:25.167151 LPDDR4 DRAM CONFIGURATION
7167 12:43:25.170738 ===================================
7168 12:43:25.173632 EX_ROW_EN[0] = 0x0
7169 12:43:25.173729 EX_ROW_EN[1] = 0x0
7170 12:43:25.177221 LP4Y_EN = 0x0
7171 12:43:25.177314 WORK_FSP = 0x1
7172 12:43:25.180734 WL = 0x5
7173 12:43:25.180802 RL = 0x5
7174 12:43:25.183944 BL = 0x2
7175 12:43:25.184045 RPST = 0x0
7176 12:43:25.187611 RD_PRE = 0x0
7177 12:43:25.190076 WR_PRE = 0x1
7178 12:43:25.190171 WR_PST = 0x1
7179 12:43:25.193876 DBI_WR = 0x0
7180 12:43:25.193945 DBI_RD = 0x0
7181 12:43:25.197360 OTF = 0x1
7182 12:43:25.200324 ===================================
7183 12:43:25.203314 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7184 12:43:25.206508 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7185 12:43:25.209845 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7186 12:43:25.213484 ===================================
7187 12:43:25.216627 LPDDR4 DRAM CONFIGURATION
7188 12:43:25.220623 ===================================
7189 12:43:25.223606 EX_ROW_EN[0] = 0x10
7190 12:43:25.223700 EX_ROW_EN[1] = 0x0
7191 12:43:25.227016 LP4Y_EN = 0x0
7192 12:43:25.227110 WORK_FSP = 0x1
7193 12:43:25.230114 WL = 0x5
7194 12:43:25.230207 RL = 0x5
7195 12:43:25.233460 BL = 0x2
7196 12:43:25.236508 RPST = 0x0
7197 12:43:25.236581 RD_PRE = 0x0
7198 12:43:25.239714 WR_PRE = 0x1
7199 12:43:25.239810 WR_PST = 0x1
7200 12:43:25.242947 DBI_WR = 0x0
7201 12:43:25.243041 DBI_RD = 0x0
7202 12:43:25.246082 OTF = 0x1
7203 12:43:25.249485 ===================================
7204 12:43:25.256322 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7205 12:43:25.256444 ==
7206 12:43:25.259199 Dram Type= 6, Freq= 0, CH_0, rank 0
7207 12:43:25.262672 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7208 12:43:25.262773 ==
7209 12:43:25.266173 [Duty_Offset_Calibration]
7210 12:43:25.266270 B0:2 B1:0 CA:4
7211 12:43:25.266358
7212 12:43:25.269552 [DutyScan_Calibration_Flow] k_type=0
7213 12:43:25.278880
7214 12:43:25.278976 ==CLK 0==
7215 12:43:25.281928 Final CLK duty delay cell = -4
7216 12:43:25.285710 [-4] MAX Duty = 5031%(X100), DQS PI = 32
7217 12:43:25.288707 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7218 12:43:25.292638 [-4] AVG Duty = 4922%(X100)
7219 12:43:25.292710
7220 12:43:25.295051 CH0 CLK Duty spec in!! Max-Min= 218%
7221 12:43:25.298397 [DutyScan_Calibration_Flow] ====Done====
7222 12:43:25.298466
7223 12:43:25.302054 [DutyScan_Calibration_Flow] k_type=1
7224 12:43:25.318935
7225 12:43:25.319034 ==DQS 0 ==
7226 12:43:25.321496 Final DQS duty delay cell = -4
7227 12:43:25.324753 [-4] MAX Duty = 4938%(X100), DQS PI = 46
7228 12:43:25.328324 [-4] MIN Duty = 4782%(X100), DQS PI = 2
7229 12:43:25.331290 [-4] AVG Duty = 4860%(X100)
7230 12:43:25.331385
7231 12:43:25.331472 ==DQS 1 ==
7232 12:43:25.335183 Final DQS duty delay cell = 0
7233 12:43:25.338175 [0] MAX Duty = 5187%(X100), DQS PI = 2
7234 12:43:25.340996 [0] MIN Duty = 4969%(X100), DQS PI = 10
7235 12:43:25.344713 [0] AVG Duty = 5078%(X100)
7236 12:43:25.344785
7237 12:43:25.347633 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7238 12:43:25.347727
7239 12:43:25.351093 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7240 12:43:25.354362 [DutyScan_Calibration_Flow] ====Done====
7241 12:43:25.354459
7242 12:43:25.357733 [DutyScan_Calibration_Flow] k_type=3
7243 12:43:25.375941
7244 12:43:25.376050 ==DQM 0 ==
7245 12:43:25.379656 Final DQM duty delay cell = 0
7246 12:43:25.381945 [0] MAX Duty = 5124%(X100), DQS PI = 22
7247 12:43:25.385176 [0] MIN Duty = 4875%(X100), DQS PI = 54
7248 12:43:25.388377 [0] AVG Duty = 4999%(X100)
7249 12:43:25.388473
7250 12:43:25.388561 ==DQM 1 ==
7251 12:43:25.391987 Final DQM duty delay cell = 0
7252 12:43:25.395444 [0] MAX Duty = 4969%(X100), DQS PI = 2
7253 12:43:25.398529 [0] MIN Duty = 4813%(X100), DQS PI = 16
7254 12:43:25.401797 [0] AVG Duty = 4891%(X100)
7255 12:43:25.401893
7256 12:43:25.405636 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7257 12:43:25.405709
7258 12:43:25.408365 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7259 12:43:25.412256 [DutyScan_Calibration_Flow] ====Done====
7260 12:43:25.412328
7261 12:43:25.414897 [DutyScan_Calibration_Flow] k_type=2
7262 12:43:25.432678
7263 12:43:25.432752 ==DQ 0 ==
7264 12:43:25.436232 Final DQ duty delay cell = 0
7265 12:43:25.439586 [0] MAX Duty = 5156%(X100), DQS PI = 22
7266 12:43:25.442268 [0] MIN Duty = 4938%(X100), DQS PI = 12
7267 12:43:25.445852 [0] AVG Duty = 5047%(X100)
7268 12:43:25.445949
7269 12:43:25.446041 ==DQ 1 ==
7270 12:43:25.449320 Final DQ duty delay cell = 0
7271 12:43:25.452424 [0] MAX Duty = 5187%(X100), DQS PI = 2
7272 12:43:25.455744 [0] MIN Duty = 4907%(X100), DQS PI = 32
7273 12:43:25.455818 [0] AVG Duty = 5047%(X100)
7274 12:43:25.458959
7275 12:43:25.462521 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7276 12:43:25.462621
7277 12:43:25.465362 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7278 12:43:25.468911 [DutyScan_Calibration_Flow] ====Done====
7279 12:43:25.468982 ==
7280 12:43:25.471838 Dram Type= 6, Freq= 0, CH_1, rank 0
7281 12:43:25.475184 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7282 12:43:25.475271 ==
7283 12:43:25.478817 [Duty_Offset_Calibration]
7284 12:43:25.478912 B0:0 B1:-1 CA:3
7285 12:43:25.478992
7286 12:43:25.481601 [DutyScan_Calibration_Flow] k_type=0
7287 12:43:25.492019
7288 12:43:25.492131 ==CLK 0==
7289 12:43:25.495274 Final CLK duty delay cell = -4
7290 12:43:25.498983 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7291 12:43:25.501944 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7292 12:43:25.505101 [-4] AVG Duty = 4922%(X100)
7293 12:43:25.505171
7294 12:43:25.508731 CH1 CLK Duty spec in!! Max-Min= 156%
7295 12:43:25.512438 [DutyScan_Calibration_Flow] ====Done====
7296 12:43:25.512518
7297 12:43:25.515292 [DutyScan_Calibration_Flow] k_type=1
7298 12:43:25.531548
7299 12:43:25.531637 ==DQS 0 ==
7300 12:43:25.534330 Final DQS duty delay cell = 0
7301 12:43:25.537551 [0] MAX Duty = 5250%(X100), DQS PI = 30
7302 12:43:25.541285 [0] MIN Duty = 4907%(X100), DQS PI = 40
7303 12:43:25.544165 [0] AVG Duty = 5078%(X100)
7304 12:43:25.544256
7305 12:43:25.544320 ==DQS 1 ==
7306 12:43:25.547472 Final DQS duty delay cell = -4
7307 12:43:25.550829 [-4] MAX Duty = 5000%(X100), DQS PI = 28
7308 12:43:25.554357 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7309 12:43:25.557605 [-4] AVG Duty = 4922%(X100)
7310 12:43:25.557684
7311 12:43:25.560895 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7312 12:43:25.560975
7313 12:43:25.564022 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7314 12:43:25.567321 [DutyScan_Calibration_Flow] ====Done====
7315 12:43:25.567400
7316 12:43:25.571091 [DutyScan_Calibration_Flow] k_type=3
7317 12:43:25.588647
7318 12:43:25.588727 ==DQM 0 ==
7319 12:43:25.592566 Final DQM duty delay cell = 0
7320 12:43:25.595504 [0] MAX Duty = 5062%(X100), DQS PI = 30
7321 12:43:25.599079 [0] MIN Duty = 4782%(X100), DQS PI = 40
7322 12:43:25.601526 [0] AVG Duty = 4922%(X100)
7323 12:43:25.601606
7324 12:43:25.601669 ==DQM 1 ==
7325 12:43:25.605091 Final DQM duty delay cell = 0
7326 12:43:25.607995 [0] MAX Duty = 5000%(X100), DQS PI = 32
7327 12:43:25.611537 [0] MIN Duty = 4813%(X100), DQS PI = 0
7328 12:43:25.614897 [0] AVG Duty = 4906%(X100)
7329 12:43:25.615001
7330 12:43:25.617950 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7331 12:43:25.618022
7332 12:43:25.621471 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7333 12:43:25.624504 [DutyScan_Calibration_Flow] ====Done====
7334 12:43:25.624577
7335 12:43:25.627780 [DutyScan_Calibration_Flow] k_type=2
7336 12:43:25.644287
7337 12:43:25.644385 ==DQ 0 ==
7338 12:43:25.647650 Final DQ duty delay cell = -4
7339 12:43:25.651040 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7340 12:43:25.654410 [-4] MIN Duty = 4813%(X100), DQS PI = 38
7341 12:43:25.657843 [-4] AVG Duty = 4891%(X100)
7342 12:43:25.657942
7343 12:43:25.658044 ==DQ 1 ==
7344 12:43:25.660717 Final DQ duty delay cell = 0
7345 12:43:25.664490 [0] MAX Duty = 5031%(X100), DQS PI = 30
7346 12:43:25.667325 [0] MIN Duty = 4875%(X100), DQS PI = 52
7347 12:43:25.671439 [0] AVG Duty = 4953%(X100)
7348 12:43:25.671541
7349 12:43:25.673816 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7350 12:43:25.673918
7351 12:43:25.677697 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7352 12:43:25.680888 [DutyScan_Calibration_Flow] ====Done====
7353 12:43:25.683747 nWR fixed to 30
7354 12:43:25.687527 [ModeRegInit_LP4] CH0 RK0
7355 12:43:25.687625 [ModeRegInit_LP4] CH0 RK1
7356 12:43:25.690705 [ModeRegInit_LP4] CH1 RK0
7357 12:43:25.693818 [ModeRegInit_LP4] CH1 RK1
7358 12:43:25.693891 match AC timing 5
7359 12:43:25.700582 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7360 12:43:25.703711 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7361 12:43:25.706979 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7362 12:43:25.713839 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7363 12:43:25.717153 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7364 12:43:25.720257 [MiockJmeterHQA]
7365 12:43:25.720329
7366 12:43:25.723366 [DramcMiockJmeter] u1RxGatingPI = 0
7367 12:43:25.723461 0 : 4255, 4030
7368 12:43:25.723550 4 : 4253, 4026
7369 12:43:25.727101 8 : 4252, 4027
7370 12:43:25.727183 12 : 4254, 4029
7371 12:43:25.730022 16 : 4252, 4027
7372 12:43:25.730104 20 : 4252, 4027
7373 12:43:25.733238 24 : 4257, 4029
7374 12:43:25.733320 28 : 4253, 4027
7375 12:43:25.733386 32 : 4255, 4029
7376 12:43:25.736495 36 : 4252, 4027
7377 12:43:25.736577 40 : 4257, 4029
7378 12:43:25.739694 44 : 4257, 4029
7379 12:43:25.739775 48 : 4252, 4027
7380 12:43:25.743598 52 : 4255, 4029
7381 12:43:25.743679 56 : 4253, 4026
7382 12:43:25.747082 60 : 4363, 4137
7383 12:43:25.747164 64 : 4363, 4138
7384 12:43:25.747229 68 : 4252, 4027
7385 12:43:25.749647 72 : 4252, 4027
7386 12:43:25.749728 76 : 4253, 4027
7387 12:43:25.753110 80 : 4252, 4027
7388 12:43:25.753218 84 : 4252, 4027
7389 12:43:25.756226 88 : 4253, 4026
7390 12:43:25.756307 92 : 4250, 4027
7391 12:43:25.760554 96 : 4250, 3171
7392 12:43:25.760636 100 : 4249, 0
7393 12:43:25.760702 104 : 4363, 0
7394 12:43:25.762946 108 : 4363, 0
7395 12:43:25.763029 112 : 4255, 0
7396 12:43:25.766548 116 : 4250, 0
7397 12:43:25.766630 120 : 4255, 0
7398 12:43:25.766694 124 : 4255, 0
7399 12:43:25.769556 128 : 4250, 0
7400 12:43:25.769636 132 : 4361, 0
7401 12:43:25.772734 136 : 4250, 0
7402 12:43:25.772816 140 : 4360, 0
7403 12:43:25.772881 144 : 4250, 0
7404 12:43:25.776265 148 : 4250, 0
7405 12:43:25.776346 152 : 4253, 0
7406 12:43:25.776411 156 : 4250, 0
7407 12:43:25.779595 160 : 4363, 0
7408 12:43:25.779676 164 : 4250, 0
7409 12:43:25.782637 168 : 4250, 0
7410 12:43:25.782719 172 : 4250, 0
7411 12:43:25.782783 176 : 4252, 0
7412 12:43:25.786120 180 : 4250, 0
7413 12:43:25.786202 184 : 4250, 0
7414 12:43:25.789297 188 : 4250, 0
7415 12:43:25.789378 192 : 4363, 0
7416 12:43:25.789443 196 : 4250, 0
7417 12:43:25.793265 200 : 4252, 0
7418 12:43:25.793346 204 : 4255, 0
7419 12:43:25.795983 208 : 4250, 0
7420 12:43:25.796110 212 : 4364, 0
7421 12:43:25.796176 216 : 4255, 0
7422 12:43:25.799120 220 : 4250, 533
7423 12:43:25.799212 224 : 4254, 3981
7424 12:43:25.802286 228 : 4250, 4027
7425 12:43:25.802368 232 : 4361, 4137
7426 12:43:25.805453 236 : 4253, 4029
7427 12:43:25.805535 240 : 4250, 4027
7428 12:43:25.810301 244 : 4250, 4026
7429 12:43:25.810383 248 : 4250, 4026
7430 12:43:25.812816 252 : 4250, 4027
7431 12:43:25.812897 256 : 4250, 4026
7432 12:43:25.815521 260 : 4252, 4030
7433 12:43:25.815601 264 : 4250, 4027
7434 12:43:25.815666 268 : 4250, 4027
7435 12:43:25.819069 272 : 4360, 4137
7436 12:43:25.819151 276 : 4250, 4027
7437 12:43:25.822260 280 : 4361, 4138
7438 12:43:25.822342 284 : 4250, 4027
7439 12:43:25.825854 288 : 4250, 4027
7440 12:43:25.825936 292 : 4250, 4027
7441 12:43:25.829020 296 : 4250, 4027
7442 12:43:25.829101 300 : 4250, 4026
7443 12:43:25.832335 304 : 4250, 4027
7444 12:43:25.832417 308 : 4252, 4029
7445 12:43:25.835271 312 : 4253, 4030
7446 12:43:25.835353 316 : 4250, 4027
7447 12:43:25.838716 320 : 4250, 4027
7448 12:43:25.838798 324 : 4360, 4137
7449 12:43:25.841811 328 : 4250, 4027
7450 12:43:25.841892 332 : 4361, 4131
7451 12:43:25.841957 336 : 4250, 2198
7452 12:43:25.845521 340 : 4250, 11
7453 12:43:25.845603
7454 12:43:25.848590 MIOCK jitter meter ch=0
7455 12:43:25.848670
7456 12:43:25.851899 1T = (340-100) = 240 dly cells
7457 12:43:25.855500 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7458 12:43:25.855581 ==
7459 12:43:25.858272 Dram Type= 6, Freq= 0, CH_0, rank 0
7460 12:43:25.865149 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7461 12:43:25.865230 ==
7462 12:43:25.868342 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7463 12:43:25.874788 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7464 12:43:25.878681 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7465 12:43:25.884884 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7466 12:43:25.892331 [CA 0] Center 43 (13~73) winsize 61
7467 12:43:25.895968 [CA 1] Center 43 (13~73) winsize 61
7468 12:43:25.899174 [CA 2] Center 38 (9~67) winsize 59
7469 12:43:25.902609 [CA 3] Center 37 (8~67) winsize 60
7470 12:43:25.905938 [CA 4] Center 35 (6~65) winsize 60
7471 12:43:25.908820 [CA 5] Center 35 (5~66) winsize 62
7472 12:43:25.908919
7473 12:43:25.911909 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7474 12:43:25.912041
7475 12:43:25.918796 [CATrainingPosCal] consider 1 rank data
7476 12:43:25.918878 u2DelayCellTimex100 = 271/100 ps
7477 12:43:25.925345 CA0 delay=43 (13~73),Diff = 8 PI (28 cell)
7478 12:43:25.928548 CA1 delay=43 (13~73),Diff = 8 PI (28 cell)
7479 12:43:25.932004 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7480 12:43:25.935105 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7481 12:43:25.939227 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7482 12:43:25.942671 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7483 12:43:25.942770
7484 12:43:25.945154 CA PerBit enable=1, Macro0, CA PI delay=35
7485 12:43:25.945235
7486 12:43:25.947986 [CBTSetCACLKResult] CA Dly = 35
7487 12:43:25.951654 CS Dly: 11 (0~42)
7488 12:43:25.954723 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7489 12:43:25.958694 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7490 12:43:25.958800 ==
7491 12:43:25.961591 Dram Type= 6, Freq= 0, CH_0, rank 1
7492 12:43:25.967852 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7493 12:43:25.967926 ==
7494 12:43:25.971362 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7495 12:43:25.977828 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7496 12:43:25.981559 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7497 12:43:25.987540 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7498 12:43:25.996608 [CA 0] Center 43 (13~74) winsize 62
7499 12:43:25.999261 [CA 1] Center 43 (13~73) winsize 61
7500 12:43:26.002331 [CA 2] Center 38 (9~68) winsize 60
7501 12:43:26.005601 [CA 3] Center 38 (9~68) winsize 60
7502 12:43:26.009149 [CA 4] Center 36 (7~66) winsize 60
7503 12:43:26.012115 [CA 5] Center 36 (6~66) winsize 61
7504 12:43:26.012186
7505 12:43:26.015408 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7506 12:43:26.015509
7507 12:43:26.022292 [CATrainingPosCal] consider 2 rank data
7508 12:43:26.022364 u2DelayCellTimex100 = 271/100 ps
7509 12:43:26.029626 CA0 delay=43 (13~73),Diff = 7 PI (25 cell)
7510 12:43:26.033148 CA1 delay=43 (13~73),Diff = 7 PI (25 cell)
7511 12:43:26.035944 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
7512 12:43:26.038599 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7513 12:43:26.041862 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7514 12:43:26.045031 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7515 12:43:26.045112
7516 12:43:26.049144 CA PerBit enable=1, Macro0, CA PI delay=36
7517 12:43:26.049226
7518 12:43:26.051772 [CBTSetCACLKResult] CA Dly = 36
7519 12:43:26.055191 CS Dly: 12 (0~44)
7520 12:43:26.058583 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7521 12:43:26.061859 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7522 12:43:26.061947
7523 12:43:26.065027 ----->DramcWriteLeveling(PI) begin...
7524 12:43:26.065099 ==
7525 12:43:26.068786 Dram Type= 6, Freq= 0, CH_0, rank 0
7526 12:43:26.075061 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7527 12:43:26.075169 ==
7528 12:43:26.078526 Write leveling (Byte 0): 34 => 34
7529 12:43:26.082021 Write leveling (Byte 1): 27 => 27
7530 12:43:26.082091 DramcWriteLeveling(PI) end<-----
7531 12:43:26.085014
7532 12:43:26.085109 ==
7533 12:43:26.088646 Dram Type= 6, Freq= 0, CH_0, rank 0
7534 12:43:26.091704 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7535 12:43:26.091799 ==
7536 12:43:26.095123 [Gating] SW mode calibration
7537 12:43:26.101178 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7538 12:43:26.108287 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7539 12:43:26.111454 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7540 12:43:26.114336 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7541 12:43:26.120866 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7542 12:43:26.124168 1 4 12 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
7543 12:43:26.127660 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7544 12:43:26.134333 1 4 20 | B1->B0 | 2b2a 3434 | 1 1 | (0 0) (1 1)
7545 12:43:26.137950 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7546 12:43:26.140861 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7547 12:43:26.147382 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7548 12:43:26.150302 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7549 12:43:26.153865 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7550 12:43:26.160940 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 1)
7551 12:43:26.163740 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7552 12:43:26.166786 1 5 20 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
7553 12:43:26.173738 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7554 12:43:26.176748 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7555 12:43:26.180365 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7556 12:43:26.186825 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7557 12:43:26.189901 1 6 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
7558 12:43:26.193298 1 6 12 | B1->B0 | 2323 4242 | 0 1 | (0 0) (0 0)
7559 12:43:26.200291 1 6 16 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
7560 12:43:26.202937 1 6 20 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
7561 12:43:26.207020 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7562 12:43:26.213209 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7563 12:43:26.216621 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7564 12:43:26.219684 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7565 12:43:26.226486 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7566 12:43:26.229680 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7567 12:43:26.232846 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7568 12:43:26.239609 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7569 12:43:26.242543 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7570 12:43:26.247131 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 12:43:26.252764 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 12:43:26.256158 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 12:43:26.259310 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 12:43:26.265475 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 12:43:26.269041 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 12:43:26.271918 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 12:43:26.278606 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 12:43:26.282456 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 12:43:26.284970 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 12:43:26.291741 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 12:43:26.295273 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7582 12:43:26.298124 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7583 12:43:26.305423 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7584 12:43:26.308175 Total UI for P1: 0, mck2ui 16
7585 12:43:26.312162 best dqsien dly found for B0: ( 1, 9, 10)
7586 12:43:26.315072 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7587 12:43:26.318128 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7588 12:43:26.321539 Total UI for P1: 0, mck2ui 16
7589 12:43:26.324791 best dqsien dly found for B1: ( 1, 9, 20)
7590 12:43:26.328601 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7591 12:43:26.332316 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7592 12:43:26.332388
7593 12:43:26.337902 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7594 12:43:26.341662 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7595 12:43:26.344530 [Gating] SW calibration Done
7596 12:43:26.344602 ==
7597 12:43:26.347884 Dram Type= 6, Freq= 0, CH_0, rank 0
7598 12:43:26.351043 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7599 12:43:26.351120 ==
7600 12:43:26.354907 RX Vref Scan: 0
7601 12:43:26.355009
7602 12:43:26.355099 RX Vref 0 -> 0, step: 1
7603 12:43:26.355184
7604 12:43:26.357915 RX Delay 0 -> 252, step: 8
7605 12:43:26.360838 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7606 12:43:26.363967 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7607 12:43:26.371173 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7608 12:43:26.374161 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7609 12:43:26.377740 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7610 12:43:26.380759 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7611 12:43:26.383792 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7612 12:43:26.390415 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7613 12:43:26.394368 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7614 12:43:26.397382 iDelay=192, Bit 9, Center 115 (64 ~ 167) 104
7615 12:43:26.400166 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7616 12:43:26.407067 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7617 12:43:26.410200 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7618 12:43:26.413335 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7619 12:43:26.416890 iDelay=192, Bit 14, Center 139 (88 ~ 191) 104
7620 12:43:26.420180 iDelay=192, Bit 15, Center 131 (80 ~ 183) 104
7621 12:43:26.423815 ==
7622 12:43:26.426801 Dram Type= 6, Freq= 0, CH_0, rank 0
7623 12:43:26.430201 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7624 12:43:26.430272 ==
7625 12:43:26.430332 DQS Delay:
7626 12:43:26.433552 DQS0 = 0, DQS1 = 0
7627 12:43:26.433620 DQM Delay:
7628 12:43:26.436259 DQM0 = 131, DQM1 = 127
7629 12:43:26.436359 DQ Delay:
7630 12:43:26.440333 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7631 12:43:26.443289 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7632 12:43:26.446448 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
7633 12:43:26.450274 DQ12 =135, DQ13 =131, DQ14 =139, DQ15 =131
7634 12:43:26.450342
7635 12:43:26.450401
7636 12:43:26.452851 ==
7637 12:43:26.456012 Dram Type= 6, Freq= 0, CH_0, rank 0
7638 12:43:26.459339 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7639 12:43:26.459426 ==
7640 12:43:26.459486
7641 12:43:26.459541
7642 12:43:26.462977 TX Vref Scan disable
7643 12:43:26.463075 == TX Byte 0 ==
7644 12:43:26.466584 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7645 12:43:26.472345 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7646 12:43:26.472429 == TX Byte 1 ==
7647 12:43:26.479545 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7648 12:43:26.482667 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7649 12:43:26.482743 ==
7650 12:43:26.485782 Dram Type= 6, Freq= 0, CH_0, rank 0
7651 12:43:26.488884 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7652 12:43:26.488961 ==
7653 12:43:26.504586
7654 12:43:26.507448 TX Vref early break, caculate TX vref
7655 12:43:26.511172 TX Vref=16, minBit 1, minWin=21, winSum=362
7656 12:43:26.514294 TX Vref=18, minBit 1, minWin=21, winSum=370
7657 12:43:26.517973 TX Vref=20, minBit 0, minWin=22, winSum=380
7658 12:43:26.520918 TX Vref=22, minBit 3, minWin=22, winSum=389
7659 12:43:26.524315 TX Vref=24, minBit 3, minWin=23, winSum=399
7660 12:43:26.530655 TX Vref=26, minBit 2, minWin=24, winSum=408
7661 12:43:26.533906 TX Vref=28, minBit 0, minWin=24, winSum=411
7662 12:43:26.537002 TX Vref=30, minBit 4, minWin=23, winSum=410
7663 12:43:26.540468 TX Vref=32, minBit 0, minWin=23, winSum=397
7664 12:43:26.543991 TX Vref=34, minBit 4, minWin=22, winSum=390
7665 12:43:26.546896 TX Vref=36, minBit 0, minWin=22, winSum=376
7666 12:43:26.553451 [TxChooseVref] Worse bit 0, Min win 24, Win sum 411, Final Vref 28
7667 12:43:26.553524
7668 12:43:26.557321 Final TX Range 0 Vref 28
7669 12:43:26.557392
7670 12:43:26.557453 ==
7671 12:43:26.560389 Dram Type= 6, Freq= 0, CH_0, rank 0
7672 12:43:26.564762 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7673 12:43:26.564844 ==
7674 12:43:26.566703
7675 12:43:26.566785
7676 12:43:26.566850 TX Vref Scan disable
7677 12:43:26.573507 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7678 12:43:26.573588 == TX Byte 0 ==
7679 12:43:26.577758 u2DelayCellOfst[0]=14 cells (4 PI)
7680 12:43:26.580304 u2DelayCellOfst[1]=18 cells (5 PI)
7681 12:43:26.583281 u2DelayCellOfst[2]=14 cells (4 PI)
7682 12:43:26.586714 u2DelayCellOfst[3]=10 cells (3 PI)
7683 12:43:26.590057 u2DelayCellOfst[4]=7 cells (2 PI)
7684 12:43:26.593521 u2DelayCellOfst[5]=0 cells (0 PI)
7685 12:43:26.596532 u2DelayCellOfst[6]=18 cells (5 PI)
7686 12:43:26.599836 u2DelayCellOfst[7]=18 cells (5 PI)
7687 12:43:26.603267 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7688 12:43:26.606388 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7689 12:43:26.609537 == TX Byte 1 ==
7690 12:43:26.613067 u2DelayCellOfst[8]=0 cells (0 PI)
7691 12:43:26.616935 u2DelayCellOfst[9]=0 cells (0 PI)
7692 12:43:26.619592 u2DelayCellOfst[10]=7 cells (2 PI)
7693 12:43:26.622799 u2DelayCellOfst[11]=3 cells (1 PI)
7694 12:43:26.626240 u2DelayCellOfst[12]=10 cells (3 PI)
7695 12:43:26.629425 u2DelayCellOfst[13]=10 cells (3 PI)
7696 12:43:26.633025 u2DelayCellOfst[14]=14 cells (4 PI)
7697 12:43:26.636080 u2DelayCellOfst[15]=10 cells (3 PI)
7698 12:43:26.639482 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7699 12:43:26.642903 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7700 12:43:26.646113 DramC Write-DBI on
7701 12:43:26.646197 ==
7702 12:43:26.649444 Dram Type= 6, Freq= 0, CH_0, rank 0
7703 12:43:26.652325 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7704 12:43:26.652407 ==
7705 12:43:26.652471
7706 12:43:26.652530
7707 12:43:26.655631 TX Vref Scan disable
7708 12:43:26.659204 == TX Byte 0 ==
7709 12:43:26.662296 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7710 12:43:26.662378 == TX Byte 1 ==
7711 12:43:26.669164 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7712 12:43:26.669269 DramC Write-DBI off
7713 12:43:26.669361
7714 12:43:26.669456 [DATLAT]
7715 12:43:26.672384 Freq=1600, CH0 RK0
7716 12:43:26.672487
7717 12:43:26.675835 DATLAT Default: 0xf
7718 12:43:26.675936 0, 0xFFFF, sum = 0
7719 12:43:26.678824 1, 0xFFFF, sum = 0
7720 12:43:26.678929 2, 0xFFFF, sum = 0
7721 12:43:26.683071 3, 0xFFFF, sum = 0
7722 12:43:26.683177 4, 0xFFFF, sum = 0
7723 12:43:26.685877 5, 0xFFFF, sum = 0
7724 12:43:26.685976 6, 0xFFFF, sum = 0
7725 12:43:26.688936 7, 0xFFFF, sum = 0
7726 12:43:26.689006 8, 0xFFFF, sum = 0
7727 12:43:26.692571 9, 0xFFFF, sum = 0
7728 12:43:26.692669 10, 0xFFFF, sum = 0
7729 12:43:26.695822 11, 0xFFFF, sum = 0
7730 12:43:26.695921 12, 0xFFFF, sum = 0
7731 12:43:26.698310 13, 0xFFFF, sum = 0
7732 12:43:26.698381 14, 0x0, sum = 1
7733 12:43:26.701881 15, 0x0, sum = 2
7734 12:43:26.701986 16, 0x0, sum = 3
7735 12:43:26.704747 17, 0x0, sum = 4
7736 12:43:26.704829 best_step = 15
7737 12:43:26.704894
7738 12:43:26.704954 ==
7739 12:43:26.708083 Dram Type= 6, Freq= 0, CH_0, rank 0
7740 12:43:26.714589 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7741 12:43:26.714672 ==
7742 12:43:26.714737 RX Vref Scan: 1
7743 12:43:26.714797
7744 12:43:26.718491 Set Vref Range= 24 -> 127
7745 12:43:26.718573
7746 12:43:26.721255 RX Vref 24 -> 127, step: 1
7747 12:43:26.721336
7748 12:43:26.724885 RX Delay 19 -> 252, step: 4
7749 12:43:26.724967
7750 12:43:26.728293 Set Vref, RX VrefLevel [Byte0]: 24
7751 12:43:26.731823 [Byte1]: 24
7752 12:43:26.731904
7753 12:43:26.735207 Set Vref, RX VrefLevel [Byte0]: 25
7754 12:43:26.738524 [Byte1]: 25
7755 12:43:26.738606
7756 12:43:26.741518 Set Vref, RX VrefLevel [Byte0]: 26
7757 12:43:26.744702 [Byte1]: 26
7758 12:43:26.747701
7759 12:43:26.747783 Set Vref, RX VrefLevel [Byte0]: 27
7760 12:43:26.751102 [Byte1]: 27
7761 12:43:26.755877
7762 12:43:26.755958 Set Vref, RX VrefLevel [Byte0]: 28
7763 12:43:26.758867 [Byte1]: 28
7764 12:43:26.763270
7765 12:43:26.763351 Set Vref, RX VrefLevel [Byte0]: 29
7766 12:43:26.766334 [Byte1]: 29
7767 12:43:26.770761
7768 12:43:26.770842 Set Vref, RX VrefLevel [Byte0]: 30
7769 12:43:26.773828 [Byte1]: 30
7770 12:43:26.778402
7771 12:43:26.778483 Set Vref, RX VrefLevel [Byte0]: 31
7772 12:43:26.781405 [Byte1]: 31
7773 12:43:26.785564
7774 12:43:26.785645 Set Vref, RX VrefLevel [Byte0]: 32
7775 12:43:26.789398 [Byte1]: 32
7776 12:43:26.793502
7777 12:43:26.793583 Set Vref, RX VrefLevel [Byte0]: 33
7778 12:43:26.796764 [Byte1]: 33
7779 12:43:26.801744
7780 12:43:26.801825 Set Vref, RX VrefLevel [Byte0]: 34
7781 12:43:26.804452 [Byte1]: 34
7782 12:43:26.808423
7783 12:43:26.808505 Set Vref, RX VrefLevel [Byte0]: 35
7784 12:43:26.811878 [Byte1]: 35
7785 12:43:26.816037
7786 12:43:26.816133 Set Vref, RX VrefLevel [Byte0]: 36
7787 12:43:26.819330 [Byte1]: 36
7788 12:43:26.823411
7789 12:43:26.823492 Set Vref, RX VrefLevel [Byte0]: 37
7790 12:43:26.826836 [Byte1]: 37
7791 12:43:26.831037
7792 12:43:26.831118 Set Vref, RX VrefLevel [Byte0]: 38
7793 12:43:26.834160 [Byte1]: 38
7794 12:43:26.838893
7795 12:43:26.838974 Set Vref, RX VrefLevel [Byte0]: 39
7796 12:43:26.842471 [Byte1]: 39
7797 12:43:26.846486
7798 12:43:26.846567 Set Vref, RX VrefLevel [Byte0]: 40
7799 12:43:26.849375 [Byte1]: 40
7800 12:43:26.853881
7801 12:43:26.853962 Set Vref, RX VrefLevel [Byte0]: 41
7802 12:43:26.856908 [Byte1]: 41
7803 12:43:26.861667
7804 12:43:26.861753 Set Vref, RX VrefLevel [Byte0]: 42
7805 12:43:26.864609 [Byte1]: 42
7806 12:43:26.868762
7807 12:43:26.868842 Set Vref, RX VrefLevel [Byte0]: 43
7808 12:43:26.872282 [Byte1]: 43
7809 12:43:26.876663
7810 12:43:26.876744 Set Vref, RX VrefLevel [Byte0]: 44
7811 12:43:26.880080 [Byte1]: 44
7812 12:43:26.884276
7813 12:43:26.884358 Set Vref, RX VrefLevel [Byte0]: 45
7814 12:43:26.887182 [Byte1]: 45
7815 12:43:26.891810
7816 12:43:26.891891 Set Vref, RX VrefLevel [Byte0]: 46
7817 12:43:26.895079 [Byte1]: 46
7818 12:43:26.899197
7819 12:43:26.899278 Set Vref, RX VrefLevel [Byte0]: 47
7820 12:43:26.902398 [Byte1]: 47
7821 12:43:26.907228
7822 12:43:26.907309 Set Vref, RX VrefLevel [Byte0]: 48
7823 12:43:26.910218 [Byte1]: 48
7824 12:43:26.914476
7825 12:43:26.914557 Set Vref, RX VrefLevel [Byte0]: 49
7826 12:43:26.917942 [Byte1]: 49
7827 12:43:26.921868
7828 12:43:26.921949 Set Vref, RX VrefLevel [Byte0]: 50
7829 12:43:26.925275 [Byte1]: 50
7830 12:43:26.930189
7831 12:43:26.930270 Set Vref, RX VrefLevel [Byte0]: 51
7832 12:43:26.932649 [Byte1]: 51
7833 12:43:26.937382
7834 12:43:26.937463 Set Vref, RX VrefLevel [Byte0]: 52
7835 12:43:26.940513 [Byte1]: 52
7836 12:43:26.944696
7837 12:43:26.944777 Set Vref, RX VrefLevel [Byte0]: 53
7838 12:43:26.948345 [Byte1]: 53
7839 12:43:26.952228
7840 12:43:26.952309 Set Vref, RX VrefLevel [Byte0]: 54
7841 12:43:26.955991 [Byte1]: 54
7842 12:43:26.959608
7843 12:43:26.959689 Set Vref, RX VrefLevel [Byte0]: 55
7844 12:43:26.962868 [Byte1]: 55
7845 12:43:26.967368
7846 12:43:26.967449 Set Vref, RX VrefLevel [Byte0]: 56
7847 12:43:26.970970 [Byte1]: 56
7848 12:43:26.975759
7849 12:43:26.975840 Set Vref, RX VrefLevel [Byte0]: 57
7850 12:43:26.978454 [Byte1]: 57
7851 12:43:26.982692
7852 12:43:26.982774 Set Vref, RX VrefLevel [Byte0]: 58
7853 12:43:26.985662 [Byte1]: 58
7854 12:43:26.990320
7855 12:43:26.990401 Set Vref, RX VrefLevel [Byte0]: 59
7856 12:43:26.993124 [Byte1]: 59
7857 12:43:26.997780
7858 12:43:26.997861 Set Vref, RX VrefLevel [Byte0]: 60
7859 12:43:27.000936 [Byte1]: 60
7860 12:43:27.006231
7861 12:43:27.006312 Set Vref, RX VrefLevel [Byte0]: 61
7862 12:43:27.008652 [Byte1]: 61
7863 12:43:27.013043
7864 12:43:27.013125 Set Vref, RX VrefLevel [Byte0]: 62
7865 12:43:27.016374 [Byte1]: 62
7866 12:43:27.020387
7867 12:43:27.020471 Set Vref, RX VrefLevel [Byte0]: 63
7868 12:43:27.023749 [Byte1]: 63
7869 12:43:27.028511
7870 12:43:27.028592 Set Vref, RX VrefLevel [Byte0]: 64
7871 12:43:27.030924 [Byte1]: 64
7872 12:43:27.035385
7873 12:43:27.035466 Set Vref, RX VrefLevel [Byte0]: 65
7874 12:43:27.038674 [Byte1]: 65
7875 12:43:27.043338
7876 12:43:27.043419 Set Vref, RX VrefLevel [Byte0]: 66
7877 12:43:27.046260 [Byte1]: 66
7878 12:43:27.050959
7879 12:43:27.051040 Set Vref, RX VrefLevel [Byte0]: 67
7880 12:43:27.053794 [Byte1]: 67
7881 12:43:27.058200
7882 12:43:27.058282 Set Vref, RX VrefLevel [Byte0]: 68
7883 12:43:27.061732 [Byte1]: 68
7884 12:43:27.066159
7885 12:43:27.066240 Set Vref, RX VrefLevel [Byte0]: 69
7886 12:43:27.069529 [Byte1]: 69
7887 12:43:27.073932
7888 12:43:27.074013 Set Vref, RX VrefLevel [Byte0]: 70
7889 12:43:27.076482 [Byte1]: 70
7890 12:43:27.081133
7891 12:43:27.081214 Set Vref, RX VrefLevel [Byte0]: 71
7892 12:43:27.084194 [Byte1]: 71
7893 12:43:27.088600
7894 12:43:27.088707 Set Vref, RX VrefLevel [Byte0]: 72
7895 12:43:27.092252 [Byte1]: 72
7896 12:43:27.095806
7897 12:43:27.095887 Set Vref, RX VrefLevel [Byte0]: 73
7898 12:43:27.099250 [Byte1]: 73
7899 12:43:27.103999
7900 12:43:27.104119 Set Vref, RX VrefLevel [Byte0]: 74
7901 12:43:27.106976 [Byte1]: 74
7902 12:43:27.111299
7903 12:43:27.111380 Set Vref, RX VrefLevel [Byte0]: 75
7904 12:43:27.114238 [Byte1]: 75
7905 12:43:27.119479
7906 12:43:27.119560 Final RX Vref Byte 0 = 56 to rank0
7907 12:43:27.121891 Final RX Vref Byte 1 = 60 to rank0
7908 12:43:27.125409 Final RX Vref Byte 0 = 56 to rank1
7909 12:43:27.128840 Final RX Vref Byte 1 = 60 to rank1==
7910 12:43:27.131956 Dram Type= 6, Freq= 0, CH_0, rank 0
7911 12:43:27.138511 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7912 12:43:27.138594 ==
7913 12:43:27.138659 DQS Delay:
7914 12:43:27.142392 DQS0 = 0, DQS1 = 0
7915 12:43:27.142473 DQM Delay:
7916 12:43:27.142538 DQM0 = 128, DQM1 = 123
7917 12:43:27.145083 DQ Delay:
7918 12:43:27.149191 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7919 12:43:27.151770 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =134
7920 12:43:27.155385 DQ8 =112, DQ9 =112, DQ10 =124, DQ11 =120
7921 12:43:27.158160 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =130
7922 12:43:27.158241
7923 12:43:27.158305
7924 12:43:27.158364
7925 12:43:27.161984 [DramC_TX_OE_Calibration] TA2
7926 12:43:27.164874 Original DQ_B0 (3 6) =30, OEN = 27
7927 12:43:27.168416 Original DQ_B1 (3 6) =30, OEN = 27
7928 12:43:27.171453 24, 0x0, End_B0=24 End_B1=24
7929 12:43:27.174514 25, 0x0, End_B0=25 End_B1=25
7930 12:43:27.174597 26, 0x0, End_B0=26 End_B1=26
7931 12:43:27.178120 27, 0x0, End_B0=27 End_B1=27
7932 12:43:27.181886 28, 0x0, End_B0=28 End_B1=28
7933 12:43:27.185174 29, 0x0, End_B0=29 End_B1=29
7934 12:43:27.185257 30, 0x0, End_B0=30 End_B1=30
7935 12:43:27.188183 31, 0x4141, End_B0=30 End_B1=30
7936 12:43:27.191416 Byte0 end_step=30 best_step=27
7937 12:43:27.194225 Byte1 end_step=30 best_step=27
7938 12:43:27.198119 Byte0 TX OE(2T, 0.5T) = (3, 3)
7939 12:43:27.201010 Byte1 TX OE(2T, 0.5T) = (3, 3)
7940 12:43:27.201092
7941 12:43:27.201156
7942 12:43:27.208466 [DQSOSCAuto] RK0, (LSB)MR18= 0x1411, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 399 ps
7943 12:43:27.210646 CH0 RK0: MR19=303, MR18=1411
7944 12:43:27.218138 CH0_RK0: MR19=0x303, MR18=0x1411, DQSOSC=399, MR23=63, INC=23, DEC=15
7945 12:43:27.218219
7946 12:43:27.220983 ----->DramcWriteLeveling(PI) begin...
7947 12:43:27.221066 ==
7948 12:43:27.224393 Dram Type= 6, Freq= 0, CH_0, rank 1
7949 12:43:27.227956 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7950 12:43:27.228096 ==
7951 12:43:27.230445 Write leveling (Byte 0): 33 => 33
7952 12:43:27.234120 Write leveling (Byte 1): 27 => 27
7953 12:43:27.237110 DramcWriteLeveling(PI) end<-----
7954 12:43:27.237192
7955 12:43:27.237256 ==
7956 12:43:27.240652 Dram Type= 6, Freq= 0, CH_0, rank 1
7957 12:43:27.247356 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7958 12:43:27.247438 ==
7959 12:43:27.247503 [Gating] SW mode calibration
7960 12:43:27.257561 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7961 12:43:27.260690 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7962 12:43:27.266723 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7963 12:43:27.269895 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7964 12:43:27.273507 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7965 12:43:27.280445 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
7966 12:43:27.283236 1 4 16 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
7967 12:43:27.286480 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7968 12:43:27.292949 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7969 12:43:27.296183 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7970 12:43:27.299622 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7971 12:43:27.305719 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7972 12:43:27.309307 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7973 12:43:27.312627 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
7974 12:43:27.318724 1 5 16 | B1->B0 | 3333 2323 | 0 0 | (1 0) (0 0)
7975 12:43:27.322130 1 5 20 | B1->B0 | 2929 2323 | 0 0 | (0 1) (0 0)
7976 12:43:27.326410 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7977 12:43:27.332225 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7978 12:43:27.335421 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7979 12:43:27.339002 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7980 12:43:27.345685 1 6 8 | B1->B0 | 2323 3938 | 0 1 | (0 0) (0 0)
7981 12:43:27.348939 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7982 12:43:27.351928 1 6 16 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
7983 12:43:27.358762 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7984 12:43:27.361683 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7985 12:43:27.365007 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7986 12:43:27.371463 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7987 12:43:27.374948 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7988 12:43:27.378003 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7989 12:43:27.385092 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7990 12:43:27.388362 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7991 12:43:27.391939 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7992 12:43:27.398284 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7993 12:43:27.401435 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 12:43:27.404422 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 12:43:27.411326 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 12:43:27.414218 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 12:43:27.417975 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 12:43:27.424445 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 12:43:27.427472 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 12:43:27.430775 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 12:43:27.437393 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 12:43:27.440672 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 12:43:27.444060 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8004 12:43:27.450482 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8005 12:43:27.453690 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8006 12:43:27.457322 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8007 12:43:27.460246 Total UI for P1: 0, mck2ui 16
8008 12:43:27.463992 best dqsien dly found for B0: ( 1, 9, 8)
8009 12:43:27.470156 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8010 12:43:27.473600 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8011 12:43:27.477266 Total UI for P1: 0, mck2ui 16
8012 12:43:27.480733 best dqsien dly found for B1: ( 1, 9, 18)
8013 12:43:27.483509 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8014 12:43:27.487198 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8015 12:43:27.487280
8016 12:43:27.489983 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8017 12:43:27.496816 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8018 12:43:27.496897 [Gating] SW calibration Done
8019 12:43:27.496962 ==
8020 12:43:27.499957 Dram Type= 6, Freq= 0, CH_0, rank 1
8021 12:43:27.506651 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8022 12:43:27.506733 ==
8023 12:43:27.506798 RX Vref Scan: 0
8024 12:43:27.506860
8025 12:43:27.510005 RX Vref 0 -> 0, step: 1
8026 12:43:27.510086
8027 12:43:27.513108 RX Delay 0 -> 252, step: 8
8028 12:43:27.516548 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8029 12:43:27.520406 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8030 12:43:27.523035 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8031 12:43:27.529603 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8032 12:43:27.533657 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8033 12:43:27.536490 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8034 12:43:27.539838 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8035 12:43:27.543160 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8036 12:43:27.549817 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8037 12:43:27.552940 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8038 12:43:27.556377 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8039 12:43:27.559057 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8040 12:43:27.565659 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8041 12:43:27.569208 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8042 12:43:27.572105 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8043 12:43:27.576144 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8044 12:43:27.576226 ==
8045 12:43:27.579047 Dram Type= 6, Freq= 0, CH_0, rank 1
8046 12:43:27.585128 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8047 12:43:27.585210 ==
8048 12:43:27.585276 DQS Delay:
8049 12:43:27.588572 DQS0 = 0, DQS1 = 0
8050 12:43:27.588654 DQM Delay:
8051 12:43:27.588719 DQM0 = 131, DQM1 = 128
8052 12:43:27.592149 DQ Delay:
8053 12:43:27.595920 DQ0 =127, DQ1 =135, DQ2 =127, DQ3 =127
8054 12:43:27.598555 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8055 12:43:27.602102 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =119
8056 12:43:27.605252 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8057 12:43:27.605334
8058 12:43:27.605398
8059 12:43:27.605457 ==
8060 12:43:27.608482 Dram Type= 6, Freq= 0, CH_0, rank 1
8061 12:43:27.612037 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8062 12:43:27.615109 ==
8063 12:43:27.615190
8064 12:43:27.615253
8065 12:43:27.615312 TX Vref Scan disable
8066 12:43:27.618459 == TX Byte 0 ==
8067 12:43:27.621678 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8068 12:43:27.625004 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8069 12:43:27.628412 == TX Byte 1 ==
8070 12:43:27.631410 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8071 12:43:27.634607 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8072 12:43:27.638296 ==
8073 12:43:27.641727 Dram Type= 6, Freq= 0, CH_0, rank 1
8074 12:43:27.644662 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8075 12:43:27.644744 ==
8076 12:43:27.657719
8077 12:43:27.661032 TX Vref early break, caculate TX vref
8078 12:43:27.663947 TX Vref=16, minBit 3, minWin=22, winSum=375
8079 12:43:27.667987 TX Vref=18, minBit 3, minWin=22, winSum=386
8080 12:43:27.670537 TX Vref=20, minBit 9, minWin=23, winSum=391
8081 12:43:27.674107 TX Vref=22, minBit 1, minWin=24, winSum=403
8082 12:43:27.677225 TX Vref=24, minBit 2, minWin=24, winSum=407
8083 12:43:27.684682 TX Vref=26, minBit 0, minWin=25, winSum=416
8084 12:43:27.687014 TX Vref=28, minBit 0, minWin=25, winSum=419
8085 12:43:27.690554 TX Vref=30, minBit 1, minWin=24, winSum=412
8086 12:43:27.693566 TX Vref=32, minBit 0, minWin=24, winSum=402
8087 12:43:27.697027 TX Vref=34, minBit 0, minWin=23, winSum=394
8088 12:43:27.703668 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 28
8089 12:43:27.703751
8090 12:43:27.707456 Final TX Range 0 Vref 28
8091 12:43:27.707538
8092 12:43:27.707603 ==
8093 12:43:27.710048 Dram Type= 6, Freq= 0, CH_0, rank 1
8094 12:43:27.713307 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8095 12:43:27.713389 ==
8096 12:43:27.713454
8097 12:43:27.713512
8098 12:43:27.717323 TX Vref Scan disable
8099 12:43:27.722930 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8100 12:43:27.723012 == TX Byte 0 ==
8101 12:43:27.726772 u2DelayCellOfst[0]=14 cells (4 PI)
8102 12:43:27.730036 u2DelayCellOfst[1]=18 cells (5 PI)
8103 12:43:27.733126 u2DelayCellOfst[2]=10 cells (3 PI)
8104 12:43:27.736672 u2DelayCellOfst[3]=14 cells (4 PI)
8105 12:43:27.739591 u2DelayCellOfst[4]=7 cells (2 PI)
8106 12:43:27.743257 u2DelayCellOfst[5]=0 cells (0 PI)
8107 12:43:27.746631 u2DelayCellOfst[6]=18 cells (5 PI)
8108 12:43:27.749929 u2DelayCellOfst[7]=18 cells (5 PI)
8109 12:43:27.753590 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8110 12:43:27.756208 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8111 12:43:27.760028 == TX Byte 1 ==
8112 12:43:27.762899 u2DelayCellOfst[8]=0 cells (0 PI)
8113 12:43:27.766003 u2DelayCellOfst[9]=0 cells (0 PI)
8114 12:43:27.769253 u2DelayCellOfst[10]=3 cells (1 PI)
8115 12:43:27.772473 u2DelayCellOfst[11]=0 cells (0 PI)
8116 12:43:27.775708 u2DelayCellOfst[12]=10 cells (3 PI)
8117 12:43:27.779383 u2DelayCellOfst[13]=10 cells (3 PI)
8118 12:43:27.779452 u2DelayCellOfst[14]=14 cells (4 PI)
8119 12:43:27.782771 u2DelayCellOfst[15]=10 cells (3 PI)
8120 12:43:27.789212 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8121 12:43:27.792502 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8122 12:43:27.795636 DramC Write-DBI on
8123 12:43:27.795708 ==
8124 12:43:27.798978 Dram Type= 6, Freq= 0, CH_0, rank 1
8125 12:43:27.802862 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8126 12:43:27.802931 ==
8127 12:43:27.802997
8128 12:43:27.803056
8129 12:43:27.806079 TX Vref Scan disable
8130 12:43:27.806143 == TX Byte 0 ==
8131 12:43:27.812535 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8132 12:43:27.812618 == TX Byte 1 ==
8133 12:43:27.815353 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8134 12:43:27.818476 DramC Write-DBI off
8135 12:43:27.818547
8136 12:43:27.818609 [DATLAT]
8137 12:43:27.822618 Freq=1600, CH0 RK1
8138 12:43:27.822699
8139 12:43:27.822762 DATLAT Default: 0xf
8140 12:43:27.825553 0, 0xFFFF, sum = 0
8141 12:43:27.828713 1, 0xFFFF, sum = 0
8142 12:43:27.828795 2, 0xFFFF, sum = 0
8143 12:43:27.832542 3, 0xFFFF, sum = 0
8144 12:43:27.832624 4, 0xFFFF, sum = 0
8145 12:43:27.835080 5, 0xFFFF, sum = 0
8146 12:43:27.835163 6, 0xFFFF, sum = 0
8147 12:43:27.838755 7, 0xFFFF, sum = 0
8148 12:43:27.838836 8, 0xFFFF, sum = 0
8149 12:43:27.841882 9, 0xFFFF, sum = 0
8150 12:43:27.841963 10, 0xFFFF, sum = 0
8151 12:43:27.845214 11, 0xFFFF, sum = 0
8152 12:43:27.845299 12, 0xFFFF, sum = 0
8153 12:43:27.848680 13, 0xFFFF, sum = 0
8154 12:43:27.848761 14, 0x0, sum = 1
8155 12:43:27.851983 15, 0x0, sum = 2
8156 12:43:27.852084 16, 0x0, sum = 3
8157 12:43:27.855020 17, 0x0, sum = 4
8158 12:43:27.855101 best_step = 15
8159 12:43:27.855165
8160 12:43:27.855223 ==
8161 12:43:27.858359 Dram Type= 6, Freq= 0, CH_0, rank 1
8162 12:43:27.864771 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8163 12:43:27.864852 ==
8164 12:43:27.864917 RX Vref Scan: 0
8165 12:43:27.864975
8166 12:43:27.868285 RX Vref 0 -> 0, step: 1
8167 12:43:27.868366
8168 12:43:27.871304 RX Delay 19 -> 252, step: 4
8169 12:43:27.874450 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8170 12:43:27.878320 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8171 12:43:27.881137 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8172 12:43:27.887908 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8173 12:43:27.891187 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8174 12:43:27.894301 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8175 12:43:27.897639 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8176 12:43:27.904739 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8177 12:43:27.907688 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8178 12:43:27.910905 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8179 12:43:27.914125 iDelay=191, Bit 10, Center 126 (71 ~ 182) 112
8180 12:43:27.917601 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8181 12:43:27.923903 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8182 12:43:27.927545 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8183 12:43:27.930397 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8184 12:43:27.933652 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8185 12:43:27.933749 ==
8186 12:43:27.937372 Dram Type= 6, Freq= 0, CH_0, rank 1
8187 12:43:27.943871 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8188 12:43:27.943969 ==
8189 12:43:27.944096 DQS Delay:
8190 12:43:27.947611 DQS0 = 0, DQS1 = 0
8191 12:43:27.947706 DQM Delay:
8192 12:43:27.950234 DQM0 = 128, DQM1 = 123
8193 12:43:27.950330 DQ Delay:
8194 12:43:27.953407 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8195 12:43:27.957068 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =134
8196 12:43:27.960518 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8197 12:43:27.963674 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =130
8198 12:43:27.963782
8199 12:43:27.963890
8200 12:43:27.963985
8201 12:43:27.966624 [DramC_TX_OE_Calibration] TA2
8202 12:43:27.970094 Original DQ_B0 (3 6) =30, OEN = 27
8203 12:43:27.973591 Original DQ_B1 (3 6) =30, OEN = 27
8204 12:43:27.976626 24, 0x0, End_B0=24 End_B1=24
8205 12:43:27.979942 25, 0x0, End_B0=25 End_B1=25
8206 12:43:27.980077 26, 0x0, End_B0=26 End_B1=26
8207 12:43:27.983263 27, 0x0, End_B0=27 End_B1=27
8208 12:43:27.986334 28, 0x0, End_B0=28 End_B1=28
8209 12:43:27.989602 29, 0x0, End_B0=29 End_B1=29
8210 12:43:27.989705 30, 0x0, End_B0=30 End_B1=30
8211 12:43:27.993265 31, 0x4545, End_B0=30 End_B1=30
8212 12:43:27.996905 Byte0 end_step=30 best_step=27
8213 12:43:28.000004 Byte1 end_step=30 best_step=27
8214 12:43:28.003429 Byte0 TX OE(2T, 0.5T) = (3, 3)
8215 12:43:28.006494 Byte1 TX OE(2T, 0.5T) = (3, 3)
8216 12:43:28.006591
8217 12:43:28.006680
8218 12:43:28.013074 [DQSOSCAuto] RK1, (LSB)MR18= 0x1613, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
8219 12:43:28.016385 CH0 RK1: MR19=303, MR18=1613
8220 12:43:28.022882 CH0_RK1: MR19=0x303, MR18=0x1613, DQSOSC=398, MR23=63, INC=23, DEC=15
8221 12:43:28.026071 [RxdqsGatingPostProcess] freq 1600
8222 12:43:28.032601 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8223 12:43:28.036254 best DQS0 dly(2T, 0.5T) = (1, 1)
8224 12:43:28.036328 best DQS1 dly(2T, 0.5T) = (1, 1)
8225 12:43:28.039018 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8226 12:43:28.042501 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8227 12:43:28.045686 best DQS0 dly(2T, 0.5T) = (1, 1)
8228 12:43:28.049330 best DQS1 dly(2T, 0.5T) = (1, 1)
8229 12:43:28.052692 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8230 12:43:28.055568 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8231 12:43:28.059073 Pre-setting of DQS Precalculation
8232 12:43:28.062521 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8233 12:43:28.065619 ==
8234 12:43:28.068495 Dram Type= 6, Freq= 0, CH_1, rank 0
8235 12:43:28.072911 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8236 12:43:28.073014 ==
8237 12:43:28.078507 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8238 12:43:28.081862 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8239 12:43:28.085155 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8240 12:43:28.091651 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8241 12:43:28.100543 [CA 0] Center 41 (11~72) winsize 62
8242 12:43:28.103731 [CA 1] Center 42 (12~72) winsize 61
8243 12:43:28.106800 [CA 2] Center 38 (9~67) winsize 59
8244 12:43:28.110097 [CA 3] Center 37 (8~66) winsize 59
8245 12:43:28.113786 [CA 4] Center 38 (8~68) winsize 61
8246 12:43:28.116995 [CA 5] Center 36 (6~66) winsize 61
8247 12:43:28.117078
8248 12:43:28.120275 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8249 12:43:28.120345
8250 12:43:28.123303 [CATrainingPosCal] consider 1 rank data
8251 12:43:28.126929 u2DelayCellTimex100 = 271/100 ps
8252 12:43:28.133155 CA0 delay=41 (11~72),Diff = 5 PI (18 cell)
8253 12:43:28.136498 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8254 12:43:28.139897 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8255 12:43:28.142741 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8256 12:43:28.146593 CA4 delay=38 (8~68),Diff = 2 PI (7 cell)
8257 12:43:28.150040 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8258 12:43:28.150111
8259 12:43:28.153064 CA PerBit enable=1, Macro0, CA PI delay=36
8260 12:43:28.153135
8261 12:43:28.156454 [CBTSetCACLKResult] CA Dly = 36
8262 12:43:28.159473 CS Dly: 8 (0~39)
8263 12:43:28.162449 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8264 12:43:28.165844 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8265 12:43:28.165949 ==
8266 12:43:28.168926 Dram Type= 6, Freq= 0, CH_1, rank 1
8267 12:43:28.176973 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8268 12:43:28.177079 ==
8269 12:43:28.179214 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8270 12:43:28.185827 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8271 12:43:28.188599 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8272 12:43:28.195200 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8273 12:43:28.203688 [CA 0] Center 42 (12~72) winsize 61
8274 12:43:28.206725 [CA 1] Center 42 (12~72) winsize 61
8275 12:43:28.209955 [CA 2] Center 38 (8~68) winsize 61
8276 12:43:28.213438 [CA 3] Center 37 (8~67) winsize 60
8277 12:43:28.216948 [CA 4] Center 37 (8~67) winsize 60
8278 12:43:28.219606 [CA 5] Center 37 (7~67) winsize 61
8279 12:43:28.219703
8280 12:43:28.222951 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8281 12:43:28.223047
8282 12:43:28.229596 [CATrainingPosCal] consider 2 rank data
8283 12:43:28.229671 u2DelayCellTimex100 = 271/100 ps
8284 12:43:28.236758 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8285 12:43:28.239521 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8286 12:43:28.242805 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8287 12:43:28.246513 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8288 12:43:28.249472 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8289 12:43:28.253213 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8290 12:43:28.253311
8291 12:43:28.256438 CA PerBit enable=1, Macro0, CA PI delay=36
8292 12:43:28.256508
8293 12:43:28.259438 [CBTSetCACLKResult] CA Dly = 36
8294 12:43:28.262474 CS Dly: 10 (0~43)
8295 12:43:28.266038 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8296 12:43:28.269731 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8297 12:43:28.269830
8298 12:43:28.272791 ----->DramcWriteLeveling(PI) begin...
8299 12:43:28.272888 ==
8300 12:43:28.275604 Dram Type= 6, Freq= 0, CH_1, rank 0
8301 12:43:28.283228 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8302 12:43:28.283330 ==
8303 12:43:28.285885 Write leveling (Byte 0): 27 => 27
8304 12:43:28.288962 Write leveling (Byte 1): 27 => 27
8305 12:43:28.289038 DramcWriteLeveling(PI) end<-----
8306 12:43:28.292422
8307 12:43:28.292488 ==
8308 12:43:28.295508 Dram Type= 6, Freq= 0, CH_1, rank 0
8309 12:43:28.298662 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8310 12:43:28.298755 ==
8311 12:43:28.302571 [Gating] SW mode calibration
8312 12:43:28.308558 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8313 12:43:28.315697 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8314 12:43:28.318862 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8315 12:43:28.321919 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8316 12:43:28.324906 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8317 12:43:28.331523 1 4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
8318 12:43:28.335289 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8319 12:43:28.338274 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8320 12:43:28.345490 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8321 12:43:28.348215 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8322 12:43:28.355221 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8323 12:43:28.357960 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8324 12:43:28.361369 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8325 12:43:28.367928 1 5 12 | B1->B0 | 3333 2a2a | 1 0 | (1 0) (1 0)
8326 12:43:28.371999 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8327 12:43:28.374252 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8328 12:43:28.380952 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8329 12:43:28.384449 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8330 12:43:28.387596 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8331 12:43:28.393930 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8332 12:43:28.397515 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8333 12:43:28.400928 1 6 12 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
8334 12:43:28.407588 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8335 12:43:28.410670 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8336 12:43:28.414139 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8337 12:43:28.420696 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8338 12:43:28.423733 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8339 12:43:28.427632 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8340 12:43:28.434203 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8341 12:43:28.437093 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8342 12:43:28.440700 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8343 12:43:28.447421 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 12:43:28.450068 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 12:43:28.453516 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 12:43:28.460372 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 12:43:28.463672 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 12:43:28.466498 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 12:43:28.473303 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 12:43:28.476881 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 12:43:28.479464 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 12:43:28.486395 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 12:43:28.489692 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 12:43:28.493004 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 12:43:28.501103 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 12:43:28.502888 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 12:43:28.506311 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8358 12:43:28.512465 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8359 12:43:28.512562 Total UI for P1: 0, mck2ui 16
8360 12:43:28.519026 best dqsien dly found for B0: ( 1, 9, 12)
8361 12:43:28.522640 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8362 12:43:28.525758 Total UI for P1: 0, mck2ui 16
8363 12:43:28.529576 best dqsien dly found for B1: ( 1, 9, 14)
8364 12:43:28.532196 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8365 12:43:28.536181 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8366 12:43:28.536253
8367 12:43:28.538680 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8368 12:43:28.542113 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8369 12:43:28.545604 [Gating] SW calibration Done
8370 12:43:28.545671 ==
8371 12:43:28.549285 Dram Type= 6, Freq= 0, CH_1, rank 0
8372 12:43:28.554972 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8373 12:43:28.555067 ==
8374 12:43:28.555155 RX Vref Scan: 0
8375 12:43:28.555240
8376 12:43:28.558553 RX Vref 0 -> 0, step: 1
8377 12:43:28.558646
8378 12:43:28.561575 RX Delay 0 -> 252, step: 8
8379 12:43:28.565459 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8380 12:43:28.569058 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8381 12:43:28.572591 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8382 12:43:28.574870 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8383 12:43:28.581476 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8384 12:43:28.584992 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8385 12:43:28.588440 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8386 12:43:28.591756 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8387 12:43:28.598203 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8388 12:43:28.601156 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8389 12:43:28.604550 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8390 12:43:28.608117 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8391 12:43:28.611109 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8392 12:43:28.617783 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8393 12:43:28.621300 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8394 12:43:28.624803 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8395 12:43:28.624884 ==
8396 12:43:28.627737 Dram Type= 6, Freq= 0, CH_1, rank 0
8397 12:43:28.631369 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8398 12:43:28.634385 ==
8399 12:43:28.634468 DQS Delay:
8400 12:43:28.634534 DQS0 = 0, DQS1 = 0
8401 12:43:28.637442 DQM Delay:
8402 12:43:28.637523 DQM0 = 134, DQM1 = 131
8403 12:43:28.640805 DQ Delay:
8404 12:43:28.643961 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8405 12:43:28.647725 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =127
8406 12:43:28.650718 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8407 12:43:28.654428 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8408 12:43:28.654509
8409 12:43:28.654572
8410 12:43:28.654631 ==
8411 12:43:28.657798 Dram Type= 6, Freq= 0, CH_1, rank 0
8412 12:43:28.660623 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8413 12:43:28.660705 ==
8414 12:43:28.663992
8415 12:43:28.664110
8416 12:43:28.664175 TX Vref Scan disable
8417 12:43:28.667627 == TX Byte 0 ==
8418 12:43:28.670590 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8419 12:43:28.673808 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8420 12:43:28.677133 == TX Byte 1 ==
8421 12:43:28.680578 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8422 12:43:28.684333 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8423 12:43:28.686807 ==
8424 12:43:28.686888 Dram Type= 6, Freq= 0, CH_1, rank 0
8425 12:43:28.693700 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8426 12:43:28.693781 ==
8427 12:43:28.706475
8428 12:43:28.710194 TX Vref early break, caculate TX vref
8429 12:43:28.713131 TX Vref=16, minBit 8, minWin=21, winSum=369
8430 12:43:28.716531 TX Vref=18, minBit 8, minWin=21, winSum=375
8431 12:43:28.719195 TX Vref=20, minBit 8, minWin=23, winSum=385
8432 12:43:28.722572 TX Vref=22, minBit 8, minWin=23, winSum=393
8433 12:43:28.726148 TX Vref=24, minBit 8, minWin=24, winSum=404
8434 12:43:28.732562 TX Vref=26, minBit 8, minWin=24, winSum=412
8435 12:43:28.735847 TX Vref=28, minBit 0, minWin=25, winSum=415
8436 12:43:28.739205 TX Vref=30, minBit 0, minWin=25, winSum=413
8437 12:43:28.742521 TX Vref=32, minBit 11, minWin=23, winSum=406
8438 12:43:28.746186 TX Vref=34, minBit 9, minWin=23, winSum=396
8439 12:43:28.752834 TX Vref=36, minBit 9, minWin=23, winSum=386
8440 12:43:28.755583 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 28
8441 12:43:28.755665
8442 12:43:28.759262 Final TX Range 0 Vref 28
8443 12:43:28.759343
8444 12:43:28.759406 ==
8445 12:43:28.762325 Dram Type= 6, Freq= 0, CH_1, rank 0
8446 12:43:28.765944 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8447 12:43:28.769539 ==
8448 12:43:28.769619
8449 12:43:28.769683
8450 12:43:28.769742 TX Vref Scan disable
8451 12:43:28.775406 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8452 12:43:28.775487 == TX Byte 0 ==
8453 12:43:28.778956 u2DelayCellOfst[0]=18 cells (5 PI)
8454 12:43:28.782143 u2DelayCellOfst[1]=10 cells (3 PI)
8455 12:43:28.785371 u2DelayCellOfst[2]=0 cells (0 PI)
8456 12:43:28.788949 u2DelayCellOfst[3]=7 cells (2 PI)
8457 12:43:28.791981 u2DelayCellOfst[4]=10 cells (3 PI)
8458 12:43:28.795398 u2DelayCellOfst[5]=14 cells (4 PI)
8459 12:43:28.798632 u2DelayCellOfst[6]=14 cells (4 PI)
8460 12:43:28.801641 u2DelayCellOfst[7]=7 cells (2 PI)
8461 12:43:28.805531 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8462 12:43:28.808155 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8463 12:43:28.811753 == TX Byte 1 ==
8464 12:43:28.815747 u2DelayCellOfst[8]=0 cells (0 PI)
8465 12:43:28.818871 u2DelayCellOfst[9]=7 cells (2 PI)
8466 12:43:28.821672 u2DelayCellOfst[10]=10 cells (3 PI)
8467 12:43:28.824702 u2DelayCellOfst[11]=7 cells (2 PI)
8468 12:43:28.829237 u2DelayCellOfst[12]=14 cells (4 PI)
8469 12:43:28.831294 u2DelayCellOfst[13]=14 cells (4 PI)
8470 12:43:28.834406 u2DelayCellOfst[14]=18 cells (5 PI)
8471 12:43:28.838020 u2DelayCellOfst[15]=18 cells (5 PI)
8472 12:43:28.841019 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8473 12:43:28.844636 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8474 12:43:28.847801 DramC Write-DBI on
8475 12:43:28.847881 ==
8476 12:43:28.851379 Dram Type= 6, Freq= 0, CH_1, rank 0
8477 12:43:28.854118 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8478 12:43:28.854200 ==
8479 12:43:28.854264
8480 12:43:28.854327
8481 12:43:28.857521 TX Vref Scan disable
8482 12:43:28.861093 == TX Byte 0 ==
8483 12:43:28.864444 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8484 12:43:28.864521 == TX Byte 1 ==
8485 12:43:28.870815 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8486 12:43:28.870914 DramC Write-DBI off
8487 12:43:28.871010
8488 12:43:28.871098 [DATLAT]
8489 12:43:28.874151 Freq=1600, CH1 RK0
8490 12:43:28.874221
8491 12:43:28.877646 DATLAT Default: 0xf
8492 12:43:28.877716 0, 0xFFFF, sum = 0
8493 12:43:28.880724 1, 0xFFFF, sum = 0
8494 12:43:28.880803 2, 0xFFFF, sum = 0
8495 12:43:28.883909 3, 0xFFFF, sum = 0
8496 12:43:28.883978 4, 0xFFFF, sum = 0
8497 12:43:28.887596 5, 0xFFFF, sum = 0
8498 12:43:28.887666 6, 0xFFFF, sum = 0
8499 12:43:28.890744 7, 0xFFFF, sum = 0
8500 12:43:28.890825 8, 0xFFFF, sum = 0
8501 12:43:28.894304 9, 0xFFFF, sum = 0
8502 12:43:28.894386 10, 0xFFFF, sum = 0
8503 12:43:28.897735 11, 0xFFFF, sum = 0
8504 12:43:28.897851 12, 0xFFFF, sum = 0
8505 12:43:28.900816 13, 0xFFFF, sum = 0
8506 12:43:28.900897 14, 0x0, sum = 1
8507 12:43:28.904132 15, 0x0, sum = 2
8508 12:43:28.904219 16, 0x0, sum = 3
8509 12:43:28.907285 17, 0x0, sum = 4
8510 12:43:28.907389 best_step = 15
8511 12:43:28.907476
8512 12:43:28.907568 ==
8513 12:43:28.910465 Dram Type= 6, Freq= 0, CH_1, rank 0
8514 12:43:28.917230 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8515 12:43:28.917304 ==
8516 12:43:28.917376 RX Vref Scan: 1
8517 12:43:28.917435
8518 12:43:28.920660 Set Vref Range= 24 -> 127
8519 12:43:28.920737
8520 12:43:28.923568 RX Vref 24 -> 127, step: 1
8521 12:43:28.923637
8522 12:43:28.927245 RX Delay 19 -> 252, step: 4
8523 12:43:28.927351
8524 12:43:28.930338 Set Vref, RX VrefLevel [Byte0]: 24
8525 12:43:28.933051 [Byte1]: 24
8526 12:43:28.933135
8527 12:43:28.936556 Set Vref, RX VrefLevel [Byte0]: 25
8528 12:43:28.939994 [Byte1]: 25
8529 12:43:28.940117
8530 12:43:28.942937 Set Vref, RX VrefLevel [Byte0]: 26
8531 12:43:28.946594 [Byte1]: 26
8532 12:43:28.949783
8533 12:43:28.949891 Set Vref, RX VrefLevel [Byte0]: 27
8534 12:43:28.953159 [Byte1]: 27
8535 12:43:28.957228
8536 12:43:28.957310 Set Vref, RX VrefLevel [Byte0]: 28
8537 12:43:28.960909 [Byte1]: 28
8538 12:43:28.964828
8539 12:43:28.964908 Set Vref, RX VrefLevel [Byte0]: 29
8540 12:43:28.968479 [Byte1]: 29
8541 12:43:28.972594
8542 12:43:28.972674 Set Vref, RX VrefLevel [Byte0]: 30
8543 12:43:28.976214 [Byte1]: 30
8544 12:43:28.980322
8545 12:43:28.980402 Set Vref, RX VrefLevel [Byte0]: 31
8546 12:43:28.983306 [Byte1]: 31
8547 12:43:28.987460
8548 12:43:28.987540 Set Vref, RX VrefLevel [Byte0]: 32
8549 12:43:28.991533 [Byte1]: 32
8550 12:43:28.995292
8551 12:43:28.995372 Set Vref, RX VrefLevel [Byte0]: 33
8552 12:43:28.999105 [Byte1]: 33
8553 12:43:29.002915
8554 12:43:29.002995 Set Vref, RX VrefLevel [Byte0]: 34
8555 12:43:29.006502 [Byte1]: 34
8556 12:43:29.011026
8557 12:43:29.011106 Set Vref, RX VrefLevel [Byte0]: 35
8558 12:43:29.014787 [Byte1]: 35
8559 12:43:29.017914
8560 12:43:29.017994 Set Vref, RX VrefLevel [Byte0]: 36
8561 12:43:29.021437 [Byte1]: 36
8562 12:43:29.025957
8563 12:43:29.026036 Set Vref, RX VrefLevel [Byte0]: 37
8564 12:43:29.029190 [Byte1]: 37
8565 12:43:29.033579
8566 12:43:29.033659 Set Vref, RX VrefLevel [Byte0]: 38
8567 12:43:29.036764 [Byte1]: 38
8568 12:43:29.041266
8569 12:43:29.041345 Set Vref, RX VrefLevel [Byte0]: 39
8570 12:43:29.044113 [Byte1]: 39
8571 12:43:29.048354
8572 12:43:29.048435 Set Vref, RX VrefLevel [Byte0]: 40
8573 12:43:29.051540 [Byte1]: 40
8574 12:43:29.055587
8575 12:43:29.055667 Set Vref, RX VrefLevel [Byte0]: 41
8576 12:43:29.059325 [Byte1]: 41
8577 12:43:29.063344
8578 12:43:29.063424 Set Vref, RX VrefLevel [Byte0]: 42
8579 12:43:29.067045 [Byte1]: 42
8580 12:43:29.071151
8581 12:43:29.071232 Set Vref, RX VrefLevel [Byte0]: 43
8582 12:43:29.074309 [Byte1]: 43
8583 12:43:29.078764
8584 12:43:29.078844 Set Vref, RX VrefLevel [Byte0]: 44
8585 12:43:29.081594 [Byte1]: 44
8586 12:43:29.086309
8587 12:43:29.086389 Set Vref, RX VrefLevel [Byte0]: 45
8588 12:43:29.089835 [Byte1]: 45
8589 12:43:29.093985
8590 12:43:29.094065 Set Vref, RX VrefLevel [Byte0]: 46
8591 12:43:29.096864 [Byte1]: 46
8592 12:43:29.101809
8593 12:43:29.101889 Set Vref, RX VrefLevel [Byte0]: 47
8594 12:43:29.104645 [Byte1]: 47
8595 12:43:29.109101
8596 12:43:29.109182 Set Vref, RX VrefLevel [Byte0]: 48
8597 12:43:29.112460 [Byte1]: 48
8598 12:43:29.117246
8599 12:43:29.117326 Set Vref, RX VrefLevel [Byte0]: 49
8600 12:43:29.119780 [Byte1]: 49
8601 12:43:29.124343
8602 12:43:29.124424 Set Vref, RX VrefLevel [Byte0]: 50
8603 12:43:29.127469 [Byte1]: 50
8604 12:43:29.131417
8605 12:43:29.131497 Set Vref, RX VrefLevel [Byte0]: 51
8606 12:43:29.135197 [Byte1]: 51
8607 12:43:29.140255
8608 12:43:29.140335 Set Vref, RX VrefLevel [Byte0]: 52
8609 12:43:29.142623 [Byte1]: 52
8610 12:43:29.147988
8611 12:43:29.148101 Set Vref, RX VrefLevel [Byte0]: 53
8612 12:43:29.150329 [Byte1]: 53
8613 12:43:29.154860
8614 12:43:29.154941 Set Vref, RX VrefLevel [Byte0]: 54
8615 12:43:29.157885 [Byte1]: 54
8616 12:43:29.162345
8617 12:43:29.162425 Set Vref, RX VrefLevel [Byte0]: 55
8618 12:43:29.165447 [Byte1]: 55
8619 12:43:29.169537
8620 12:43:29.169617 Set Vref, RX VrefLevel [Byte0]: 56
8621 12:43:29.173070 [Byte1]: 56
8622 12:43:29.176937
8623 12:43:29.177018 Set Vref, RX VrefLevel [Byte0]: 57
8624 12:43:29.180469 [Byte1]: 57
8625 12:43:29.184911
8626 12:43:29.184991 Set Vref, RX VrefLevel [Byte0]: 58
8627 12:43:29.187731 [Byte1]: 58
8628 12:43:29.192527
8629 12:43:29.192608 Set Vref, RX VrefLevel [Byte0]: 59
8630 12:43:29.195208 [Byte1]: 59
8631 12:43:29.200250
8632 12:43:29.200330 Set Vref, RX VrefLevel [Byte0]: 60
8633 12:43:29.203645 [Byte1]: 60
8634 12:43:29.207124
8635 12:43:29.207203 Set Vref, RX VrefLevel [Byte0]: 61
8636 12:43:29.210677 [Byte1]: 61
8637 12:43:29.214956
8638 12:43:29.215036 Set Vref, RX VrefLevel [Byte0]: 62
8639 12:43:29.218223 [Byte1]: 62
8640 12:43:29.222687
8641 12:43:29.222768 Set Vref, RX VrefLevel [Byte0]: 63
8642 12:43:29.225743 [Byte1]: 63
8643 12:43:29.230204
8644 12:43:29.230285 Set Vref, RX VrefLevel [Byte0]: 64
8645 12:43:29.233170 [Byte1]: 64
8646 12:43:29.237514
8647 12:43:29.237594 Set Vref, RX VrefLevel [Byte0]: 65
8648 12:43:29.241044 [Byte1]: 65
8649 12:43:29.245306
8650 12:43:29.245409 Set Vref, RX VrefLevel [Byte0]: 66
8651 12:43:29.249317 [Byte1]: 66
8652 12:43:29.253079
8653 12:43:29.253159 Set Vref, RX VrefLevel [Byte0]: 67
8654 12:43:29.256001 [Byte1]: 67
8655 12:43:29.260240
8656 12:43:29.260320 Set Vref, RX VrefLevel [Byte0]: 68
8657 12:43:29.263579 [Byte1]: 68
8658 12:43:29.267994
8659 12:43:29.268098 Set Vref, RX VrefLevel [Byte0]: 69
8660 12:43:29.271060 [Byte1]: 69
8661 12:43:29.275547
8662 12:43:29.275627 Final RX Vref Byte 0 = 58 to rank0
8663 12:43:29.278450 Final RX Vref Byte 1 = 62 to rank0
8664 12:43:29.281981 Final RX Vref Byte 0 = 58 to rank1
8665 12:43:29.285327 Final RX Vref Byte 1 = 62 to rank1==
8666 12:43:29.288703 Dram Type= 6, Freq= 0, CH_1, rank 0
8667 12:43:29.294927 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8668 12:43:29.295008 ==
8669 12:43:29.295072 DQS Delay:
8670 12:43:29.298591 DQS0 = 0, DQS1 = 0
8671 12:43:29.298671 DQM Delay:
8672 12:43:29.298735 DQM0 = 132, DQM1 = 130
8673 12:43:29.301739 DQ Delay:
8674 12:43:29.305133 DQ0 =140, DQ1 =128, DQ2 =118, DQ3 =132
8675 12:43:29.308931 DQ4 =128, DQ5 =142, DQ6 =144, DQ7 =126
8676 12:43:29.311615 DQ8 =114, DQ9 =118, DQ10 =130, DQ11 =122
8677 12:43:29.315525 DQ12 =140, DQ13 =140, DQ14 =138, DQ15 =138
8678 12:43:29.315636
8679 12:43:29.315699
8680 12:43:29.315777
8681 12:43:29.317970 [DramC_TX_OE_Calibration] TA2
8682 12:43:29.322028 Original DQ_B0 (3 6) =30, OEN = 27
8683 12:43:29.324885 Original DQ_B1 (3 6) =30, OEN = 27
8684 12:43:29.328287 24, 0x0, End_B0=24 End_B1=24
8685 12:43:29.331229 25, 0x0, End_B0=25 End_B1=25
8686 12:43:29.331311 26, 0x0, End_B0=26 End_B1=26
8687 12:43:29.335243 27, 0x0, End_B0=27 End_B1=27
8688 12:43:29.337690 28, 0x0, End_B0=28 End_B1=28
8689 12:43:29.340912 29, 0x0, End_B0=29 End_B1=29
8690 12:43:29.344500 30, 0x0, End_B0=30 End_B1=30
8691 12:43:29.344581 31, 0x4545, End_B0=30 End_B1=30
8692 12:43:29.347610 Byte0 end_step=30 best_step=27
8693 12:43:29.351439 Byte1 end_step=30 best_step=27
8694 12:43:29.354223 Byte0 TX OE(2T, 0.5T) = (3, 3)
8695 12:43:29.357761 Byte1 TX OE(2T, 0.5T) = (3, 3)
8696 12:43:29.357841
8697 12:43:29.357904
8698 12:43:29.364120 [DQSOSCAuto] RK0, (LSB)MR18= 0xc15, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 403 ps
8699 12:43:29.367656 CH1 RK0: MR19=303, MR18=C15
8700 12:43:29.374058 CH1_RK0: MR19=0x303, MR18=0xC15, DQSOSC=399, MR23=63, INC=23, DEC=15
8701 12:43:29.374163
8702 12:43:29.377439 ----->DramcWriteLeveling(PI) begin...
8703 12:43:29.377537 ==
8704 12:43:29.380815 Dram Type= 6, Freq= 0, CH_1, rank 1
8705 12:43:29.383889 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8706 12:43:29.383995 ==
8707 12:43:29.386926 Write leveling (Byte 0): 23 => 23
8708 12:43:29.390174 Write leveling (Byte 1): 26 => 26
8709 12:43:29.393784 DramcWriteLeveling(PI) end<-----
8710 12:43:29.393864
8711 12:43:29.393928 ==
8712 12:43:29.397099 Dram Type= 6, Freq= 0, CH_1, rank 1
8713 12:43:29.403456 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8714 12:43:29.403537 ==
8715 12:43:29.403602 [Gating] SW mode calibration
8716 12:43:29.413246 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8717 12:43:29.417079 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8718 12:43:29.423081 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8719 12:43:29.426826 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8720 12:43:29.429806 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8721 12:43:29.436175 1 4 12 | B1->B0 | 2626 3434 | 0 1 | (1 1) (1 1)
8722 12:43:29.439682 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8723 12:43:29.443109 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8724 12:43:29.446559 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8725 12:43:29.452940 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8726 12:43:29.456720 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8727 12:43:29.460291 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8728 12:43:29.466522 1 5 8 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (1 0)
8729 12:43:29.469914 1 5 12 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
8730 12:43:29.473246 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8731 12:43:29.479807 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8732 12:43:29.482649 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8733 12:43:29.486425 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8734 12:43:29.492997 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8735 12:43:29.495826 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8736 12:43:29.499904 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8737 12:43:29.505916 1 6 12 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
8738 12:43:29.509465 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8739 12:43:29.512910 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8740 12:43:29.519316 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8741 12:43:29.522482 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8742 12:43:29.525577 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8743 12:43:29.532206 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8744 12:43:29.535596 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8745 12:43:29.539016 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8746 12:43:29.545977 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8747 12:43:29.548843 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8748 12:43:29.552074 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8749 12:43:29.558907 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8750 12:43:29.562131 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8751 12:43:29.568319 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8752 12:43:29.571855 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8753 12:43:29.575367 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8754 12:43:29.578409 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8755 12:43:29.585715 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8756 12:43:29.588258 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8757 12:43:29.591415 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8758 12:43:29.598155 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8759 12:43:29.601106 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8760 12:43:29.604591 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8761 12:43:29.611435 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8762 12:43:29.614714 Total UI for P1: 0, mck2ui 16
8763 12:43:29.618043 best dqsien dly found for B0: ( 1, 9, 6)
8764 12:43:29.621395 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8765 12:43:29.624044 Total UI for P1: 0, mck2ui 16
8766 12:43:29.627367 best dqsien dly found for B1: ( 1, 9, 12)
8767 12:43:29.631034 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8768 12:43:29.634079 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8769 12:43:29.634150
8770 12:43:29.637837 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8771 12:43:29.643701 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8772 12:43:29.643777 [Gating] SW calibration Done
8773 12:43:29.647019 ==
8774 12:43:29.647090 Dram Type= 6, Freq= 0, CH_1, rank 1
8775 12:43:29.654288 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8776 12:43:29.654364 ==
8777 12:43:29.654426 RX Vref Scan: 0
8778 12:43:29.654484
8779 12:43:29.657171 RX Vref 0 -> 0, step: 1
8780 12:43:29.657240
8781 12:43:29.660261 RX Delay 0 -> 252, step: 8
8782 12:43:29.663655 iDelay=200, Bit 0, Center 143 (88 ~ 199) 112
8783 12:43:29.666809 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8784 12:43:29.670238 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8785 12:43:29.676647 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8786 12:43:29.680439 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8787 12:43:29.683777 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8788 12:43:29.686545 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8789 12:43:29.690525 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8790 12:43:29.696518 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8791 12:43:29.700122 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8792 12:43:29.703483 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8793 12:43:29.706631 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8794 12:43:29.713073 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8795 12:43:29.716868 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8796 12:43:29.719771 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8797 12:43:29.722678 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8798 12:43:29.722760 ==
8799 12:43:29.726552 Dram Type= 6, Freq= 0, CH_1, rank 1
8800 12:43:29.732990 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8801 12:43:29.733073 ==
8802 12:43:29.733139 DQS Delay:
8803 12:43:29.735997 DQS0 = 0, DQS1 = 0
8804 12:43:29.736122 DQM Delay:
8805 12:43:29.736188 DQM0 = 136, DQM1 = 131
8806 12:43:29.739228 DQ Delay:
8807 12:43:29.742798 DQ0 =143, DQ1 =135, DQ2 =119, DQ3 =135
8808 12:43:29.745735 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =135
8809 12:43:29.749435 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8810 12:43:29.752616 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =143
8811 12:43:29.752698
8812 12:43:29.752763
8813 12:43:29.752824 ==
8814 12:43:29.756595 Dram Type= 6, Freq= 0, CH_1, rank 1
8815 12:43:29.762771 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8816 12:43:29.762857 ==
8817 12:43:29.762923
8818 12:43:29.762984
8819 12:43:29.763046 TX Vref Scan disable
8820 12:43:29.765846 == TX Byte 0 ==
8821 12:43:29.769573 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8822 12:43:29.775979 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8823 12:43:29.776083 == TX Byte 1 ==
8824 12:43:29.779304 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8825 12:43:29.785691 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8826 12:43:29.785773 ==
8827 12:43:29.789024 Dram Type= 6, Freq= 0, CH_1, rank 1
8828 12:43:29.791841 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8829 12:43:29.791953 ==
8830 12:43:29.805559
8831 12:43:29.808937 TX Vref early break, caculate TX vref
8832 12:43:29.812587 TX Vref=16, minBit 9, minWin=22, winSum=381
8833 12:43:29.815604 TX Vref=18, minBit 9, minWin=22, winSum=387
8834 12:43:29.818783 TX Vref=20, minBit 9, minWin=22, winSum=393
8835 12:43:29.822466 TX Vref=22, minBit 9, minWin=23, winSum=403
8836 12:43:29.825838 TX Vref=24, minBit 9, minWin=24, winSum=413
8837 12:43:29.832540 TX Vref=26, minBit 9, minWin=25, winSum=419
8838 12:43:29.835321 TX Vref=28, minBit 9, minWin=25, winSum=422
8839 12:43:29.838622 TX Vref=30, minBit 9, minWin=25, winSum=417
8840 12:43:29.841730 TX Vref=32, minBit 9, minWin=24, winSum=404
8841 12:43:29.845175 TX Vref=34, minBit 8, minWin=23, winSum=401
8842 12:43:29.852010 TX Vref=36, minBit 9, minWin=23, winSum=397
8843 12:43:29.855208 [TxChooseVref] Worse bit 9, Min win 25, Win sum 422, Final Vref 28
8844 12:43:29.855289
8845 12:43:29.858513 Final TX Range 0 Vref 28
8846 12:43:29.858586
8847 12:43:29.858665 ==
8848 12:43:29.861473 Dram Type= 6, Freq= 0, CH_1, rank 1
8849 12:43:29.864619 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8850 12:43:29.867925 ==
8851 12:43:29.868027
8852 12:43:29.868152
8853 12:43:29.868229 TX Vref Scan disable
8854 12:43:29.874673 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8855 12:43:29.874776 == TX Byte 0 ==
8856 12:43:29.878337 u2DelayCellOfst[0]=14 cells (4 PI)
8857 12:43:29.881503 u2DelayCellOfst[1]=10 cells (3 PI)
8858 12:43:29.884730 u2DelayCellOfst[2]=0 cells (0 PI)
8859 12:43:29.888194 u2DelayCellOfst[3]=7 cells (2 PI)
8860 12:43:29.891548 u2DelayCellOfst[4]=7 cells (2 PI)
8861 12:43:29.894402 u2DelayCellOfst[5]=14 cells (4 PI)
8862 12:43:29.897839 u2DelayCellOfst[6]=18 cells (5 PI)
8863 12:43:29.900892 u2DelayCellOfst[7]=7 cells (2 PI)
8864 12:43:29.904329 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8865 12:43:29.907863 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8866 12:43:29.911555 == TX Byte 1 ==
8867 12:43:29.914486 u2DelayCellOfst[8]=0 cells (0 PI)
8868 12:43:29.917465 u2DelayCellOfst[9]=3 cells (1 PI)
8869 12:43:29.920846 u2DelayCellOfst[10]=10 cells (3 PI)
8870 12:43:29.924193 u2DelayCellOfst[11]=7 cells (2 PI)
8871 12:43:29.927312 u2DelayCellOfst[12]=14 cells (4 PI)
8872 12:43:29.931199 u2DelayCellOfst[13]=14 cells (4 PI)
8873 12:43:29.933819 u2DelayCellOfst[14]=18 cells (5 PI)
8874 12:43:29.937360 u2DelayCellOfst[15]=18 cells (5 PI)
8875 12:43:29.940579 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8876 12:43:29.943931 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8877 12:43:29.947490 DramC Write-DBI on
8878 12:43:29.947571 ==
8879 12:43:29.950768 Dram Type= 6, Freq= 0, CH_1, rank 1
8880 12:43:29.954132 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8881 12:43:29.954215 ==
8882 12:43:29.954280
8883 12:43:29.954341
8884 12:43:29.957224 TX Vref Scan disable
8885 12:43:29.957304 == TX Byte 0 ==
8886 12:43:29.963868 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8887 12:43:29.963949 == TX Byte 1 ==
8888 12:43:29.970656 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8889 12:43:29.970737 DramC Write-DBI off
8890 12:43:29.970802
8891 12:43:29.970862 [DATLAT]
8892 12:43:29.973577 Freq=1600, CH1 RK1
8893 12:43:29.973658
8894 12:43:29.976627 DATLAT Default: 0xf
8895 12:43:29.976708 0, 0xFFFF, sum = 0
8896 12:43:29.980540 1, 0xFFFF, sum = 0
8897 12:43:29.980622 2, 0xFFFF, sum = 0
8898 12:43:29.983180 3, 0xFFFF, sum = 0
8899 12:43:29.983262 4, 0xFFFF, sum = 0
8900 12:43:29.986725 5, 0xFFFF, sum = 0
8901 12:43:29.986808 6, 0xFFFF, sum = 0
8902 12:43:29.989812 7, 0xFFFF, sum = 0
8903 12:43:29.989895 8, 0xFFFF, sum = 0
8904 12:43:29.993767 9, 0xFFFF, sum = 0
8905 12:43:29.993850 10, 0xFFFF, sum = 0
8906 12:43:29.996654 11, 0xFFFF, sum = 0
8907 12:43:29.996737 12, 0xFFFF, sum = 0
8908 12:43:29.999841 13, 0xFFFF, sum = 0
8909 12:43:29.999923 14, 0x0, sum = 1
8910 12:43:30.003415 15, 0x0, sum = 2
8911 12:43:30.003498 16, 0x0, sum = 3
8912 12:43:30.006275 17, 0x0, sum = 4
8913 12:43:30.006357 best_step = 15
8914 12:43:30.006422
8915 12:43:30.006482 ==
8916 12:43:30.009665 Dram Type= 6, Freq= 0, CH_1, rank 1
8917 12:43:30.016853 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8918 12:43:30.016935 ==
8919 12:43:30.017000 RX Vref Scan: 0
8920 12:43:30.017061
8921 12:43:30.019554 RX Vref 0 -> 0, step: 1
8922 12:43:30.019635
8923 12:43:30.022775 RX Delay 11 -> 252, step: 4
8924 12:43:30.026305 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
8925 12:43:30.029633 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
8926 12:43:30.036092 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8927 12:43:30.039403 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
8928 12:43:30.042485 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8929 12:43:30.046251 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8930 12:43:30.049266 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
8931 12:43:30.055902 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
8932 12:43:30.059883 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8933 12:43:30.062600 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8934 12:43:30.065952 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8935 12:43:30.069446 iDelay=195, Bit 11, Center 122 (71 ~ 174) 104
8936 12:43:30.076087 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8937 12:43:30.079397 iDelay=195, Bit 13, Center 134 (79 ~ 190) 112
8938 12:43:30.081926 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8939 12:43:30.085298 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8940 12:43:30.085387 ==
8941 12:43:30.088669 Dram Type= 6, Freq= 0, CH_1, rank 1
8942 12:43:30.095513 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8943 12:43:30.095595 ==
8944 12:43:30.095661 DQS Delay:
8945 12:43:30.098849 DQS0 = 0, DQS1 = 0
8946 12:43:30.098931 DQM Delay:
8947 12:43:30.102221 DQM0 = 133, DQM1 = 127
8948 12:43:30.102301 DQ Delay:
8949 12:43:30.105127 DQ0 =136, DQ1 =132, DQ2 =122, DQ3 =130
8950 12:43:30.108777 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =130
8951 12:43:30.112595 DQ8 =114, DQ9 =118, DQ10 =128, DQ11 =122
8952 12:43:30.114845 DQ12 =136, DQ13 =134, DQ14 =132, DQ15 =138
8953 12:43:30.114927
8954 12:43:30.114992
8955 12:43:30.115052
8956 12:43:30.118164 [DramC_TX_OE_Calibration] TA2
8957 12:43:30.121599 Original DQ_B0 (3 6) =30, OEN = 27
8958 12:43:30.124963 Original DQ_B1 (3 6) =30, OEN = 27
8959 12:43:30.128672 24, 0x0, End_B0=24 End_B1=24
8960 12:43:30.131621 25, 0x0, End_B0=25 End_B1=25
8961 12:43:30.131703 26, 0x0, End_B0=26 End_B1=26
8962 12:43:30.135290 27, 0x0, End_B0=27 End_B1=27
8963 12:43:30.138795 28, 0x0, End_B0=28 End_B1=28
8964 12:43:30.141576 29, 0x0, End_B0=29 End_B1=29
8965 12:43:30.144645 30, 0x0, End_B0=30 End_B1=30
8966 12:43:30.144728 31, 0x5151, End_B0=30 End_B1=30
8967 12:43:30.148282 Byte0 end_step=30 best_step=27
8968 12:43:30.151575 Byte1 end_step=30 best_step=27
8969 12:43:30.155033 Byte0 TX OE(2T, 0.5T) = (3, 3)
8970 12:43:30.157914 Byte1 TX OE(2T, 0.5T) = (3, 3)
8971 12:43:30.157995
8972 12:43:30.158060
8973 12:43:30.164358 [DQSOSCAuto] RK1, (LSB)MR18= 0xd1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
8974 12:43:30.168062 CH1 RK1: MR19=303, MR18=D1B
8975 12:43:30.174432 CH1_RK1: MR19=0x303, MR18=0xD1B, DQSOSC=396, MR23=63, INC=23, DEC=15
8976 12:43:30.178173 [RxdqsGatingPostProcess] freq 1600
8977 12:43:30.184046 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8978 12:43:30.187637 best DQS0 dly(2T, 0.5T) = (1, 1)
8979 12:43:30.187718 best DQS1 dly(2T, 0.5T) = (1, 1)
8980 12:43:30.190678 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8981 12:43:30.194152 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8982 12:43:30.197014 best DQS0 dly(2T, 0.5T) = (1, 1)
8983 12:43:30.201419 best DQS1 dly(2T, 0.5T) = (1, 1)
8984 12:43:30.204394 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8985 12:43:30.206943 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8986 12:43:30.210637 Pre-setting of DQS Precalculation
8987 12:43:30.213796 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8988 12:43:30.224152 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8989 12:43:30.230640 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8990 12:43:30.230742
8991 12:43:30.230837
8992 12:43:30.233826 [Calibration Summary] 3200 Mbps
8993 12:43:30.233926 CH 0, Rank 0
8994 12:43:30.236828 SW Impedance : PASS
8995 12:43:30.240261 DUTY Scan : NO K
8996 12:43:30.240334 ZQ Calibration : PASS
8997 12:43:30.243578 Jitter Meter : NO K
8998 12:43:30.243653 CBT Training : PASS
8999 12:43:30.247054 Write leveling : PASS
9000 12:43:30.249894 RX DQS gating : PASS
9001 12:43:30.249992 RX DQ/DQS(RDDQC) : PASS
9002 12:43:30.254135 TX DQ/DQS : PASS
9003 12:43:30.256353 RX DATLAT : PASS
9004 12:43:30.256425 RX DQ/DQS(Engine): PASS
9005 12:43:30.260136 TX OE : PASS
9006 12:43:30.260236 All Pass.
9007 12:43:30.260334
9008 12:43:30.263262 CH 0, Rank 1
9009 12:43:30.263335 SW Impedance : PASS
9010 12:43:30.266383 DUTY Scan : NO K
9011 12:43:30.269920 ZQ Calibration : PASS
9012 12:43:30.270020 Jitter Meter : NO K
9013 12:43:30.272821 CBT Training : PASS
9014 12:43:30.276313 Write leveling : PASS
9015 12:43:30.276400 RX DQS gating : PASS
9016 12:43:30.279387 RX DQ/DQS(RDDQC) : PASS
9017 12:43:30.282924 TX DQ/DQS : PASS
9018 12:43:30.283023 RX DATLAT : PASS
9019 12:43:30.286079 RX DQ/DQS(Engine): PASS
9020 12:43:30.289466 TX OE : PASS
9021 12:43:30.289567 All Pass.
9022 12:43:30.289656
9023 12:43:30.289744 CH 1, Rank 0
9024 12:43:30.292861 SW Impedance : PASS
9025 12:43:30.296171 DUTY Scan : NO K
9026 12:43:30.296310 ZQ Calibration : PASS
9027 12:43:30.299641 Jitter Meter : NO K
9028 12:43:30.302525 CBT Training : PASS
9029 12:43:30.302625 Write leveling : PASS
9030 12:43:30.306040 RX DQS gating : PASS
9031 12:43:30.309301 RX DQ/DQS(RDDQC) : PASS
9032 12:43:30.309377 TX DQ/DQS : PASS
9033 12:43:30.312288 RX DATLAT : PASS
9034 12:43:30.316247 RX DQ/DQS(Engine): PASS
9035 12:43:30.316320 TX OE : PASS
9036 12:43:30.318894 All Pass.
9037 12:43:30.318990
9038 12:43:30.319078 CH 1, Rank 1
9039 12:43:30.322497 SW Impedance : PASS
9040 12:43:30.322593 DUTY Scan : NO K
9041 12:43:30.325573 ZQ Calibration : PASS
9042 12:43:30.329264 Jitter Meter : NO K
9043 12:43:30.329337 CBT Training : PASS
9044 12:43:30.331875 Write leveling : PASS
9045 12:43:30.335258 RX DQS gating : PASS
9046 12:43:30.335332 RX DQ/DQS(RDDQC) : PASS
9047 12:43:30.339201 TX DQ/DQS : PASS
9048 12:43:30.341754 RX DATLAT : PASS
9049 12:43:30.341853 RX DQ/DQS(Engine): PASS
9050 12:43:30.345337 TX OE : PASS
9051 12:43:30.345412 All Pass.
9052 12:43:30.345476
9053 12:43:30.348281 DramC Write-DBI on
9054 12:43:30.351768 PER_BANK_REFRESH: Hybrid Mode
9055 12:43:30.351869 TX_TRACKING: ON
9056 12:43:30.361554 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9057 12:43:30.368171 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9058 12:43:30.374746 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9059 12:43:30.378174 [FAST_K] Save calibration result to emmc
9060 12:43:30.381999 sync common calibartion params.
9061 12:43:30.384799 sync cbt_mode0:1, 1:1
9062 12:43:30.387909 dram_init: ddr_geometry: 2
9063 12:43:30.388008 dram_init: ddr_geometry: 2
9064 12:43:30.391522 dram_init: ddr_geometry: 2
9065 12:43:30.394768 0:dram_rank_size:100000000
9066 12:43:30.398396 1:dram_rank_size:100000000
9067 12:43:30.401523 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9068 12:43:30.404243 DFS_SHUFFLE_HW_MODE: ON
9069 12:43:30.407607 dramc_set_vcore_voltage set vcore to 725000
9070 12:43:30.410979 Read voltage for 1600, 0
9071 12:43:30.411087 Vio18 = 0
9072 12:43:30.411178 Vcore = 725000
9073 12:43:30.414231 Vdram = 0
9074 12:43:30.414328 Vddq = 0
9075 12:43:30.414418 Vmddr = 0
9076 12:43:30.417504 switch to 3200 Mbps bootup
9077 12:43:30.421496 [DramcRunTimeConfig]
9078 12:43:30.421593 PHYPLL
9079 12:43:30.421686 DPM_CONTROL_AFTERK: ON
9080 12:43:30.424420 PER_BANK_REFRESH: ON
9081 12:43:30.427795 REFRESH_OVERHEAD_REDUCTION: ON
9082 12:43:30.427893 CMD_PICG_NEW_MODE: OFF
9083 12:43:30.431120 XRTWTW_NEW_MODE: ON
9084 12:43:30.434148 XRTRTR_NEW_MODE: ON
9085 12:43:30.434247 TX_TRACKING: ON
9086 12:43:30.437185 RDSEL_TRACKING: OFF
9087 12:43:30.437288 DQS Precalculation for DVFS: ON
9088 12:43:30.440764 RX_TRACKING: OFF
9089 12:43:30.440851 HW_GATING DBG: ON
9090 12:43:30.443964 ZQCS_ENABLE_LP4: ON
9091 12:43:30.447295 RX_PICG_NEW_MODE: ON
9092 12:43:30.447372 TX_PICG_NEW_MODE: ON
9093 12:43:30.450640 ENABLE_RX_DCM_DPHY: ON
9094 12:43:30.453582 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9095 12:43:30.453659 DUMMY_READ_FOR_TRACKING: OFF
9096 12:43:30.456990 !!! SPM_CONTROL_AFTERK: OFF
9097 12:43:30.460687 !!! SPM could not control APHY
9098 12:43:30.463969 IMPEDANCE_TRACKING: ON
9099 12:43:30.464087 TEMP_SENSOR: ON
9100 12:43:30.466994 HW_SAVE_FOR_SR: OFF
9101 12:43:30.470627 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9102 12:43:30.473493 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9103 12:43:30.473595 Read ODT Tracking: ON
9104 12:43:30.476928 Refresh Rate DeBounce: ON
9105 12:43:30.480113 DFS_NO_QUEUE_FLUSH: ON
9106 12:43:30.483532 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9107 12:43:30.483632 ENABLE_DFS_RUNTIME_MRW: OFF
9108 12:43:30.486767 DDR_RESERVE_NEW_MODE: ON
9109 12:43:30.489999 MR_CBT_SWITCH_FREQ: ON
9110 12:43:30.490081 =========================
9111 12:43:30.510004 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9112 12:43:30.513182 dram_init: ddr_geometry: 2
9113 12:43:30.531715 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9114 12:43:30.535183 dram_init: dram init end (result: 0)
9115 12:43:30.541814 DRAM-K: Full calibration passed in 24410 msecs
9116 12:43:30.545111 MRC: failed to locate region type 0.
9117 12:43:30.545202 DRAM rank0 size:0x100000000,
9118 12:43:30.548238 DRAM rank1 size=0x100000000
9119 12:43:30.558118 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9120 12:43:30.564538 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9121 12:43:30.574468 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9122 12:43:30.581006 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9123 12:43:30.581094 DRAM rank0 size:0x100000000,
9124 12:43:30.583919 DRAM rank1 size=0x100000000
9125 12:43:30.584036 CBMEM:
9126 12:43:30.587698 IMD: root @ 0xfffff000 254 entries.
9127 12:43:30.590738 IMD: root @ 0xffffec00 62 entries.
9128 12:43:30.594184 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9129 12:43:30.600824 WARNING: RO_VPD is uninitialized or empty.
9130 12:43:30.604184 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9131 12:43:30.611405 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9132 12:43:30.624626 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9133 12:43:30.635504 BS: romstage times (exec / console): total (unknown) / 23944 ms
9134 12:43:30.635580
9135 12:43:30.635648
9136 12:43:30.645738 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9137 12:43:30.649856 ARM64: Exception handlers installed.
9138 12:43:30.651877 ARM64: Testing exception
9139 12:43:30.655384 ARM64: Done test exception
9140 12:43:30.655459 Enumerating buses...
9141 12:43:30.658916 Show all devs... Before device enumeration.
9142 12:43:30.661905 Root Device: enabled 1
9143 12:43:30.665248 CPU_CLUSTER: 0: enabled 1
9144 12:43:30.665322 CPU: 00: enabled 1
9145 12:43:30.668521 Compare with tree...
9146 12:43:30.668595 Root Device: enabled 1
9147 12:43:30.671883 CPU_CLUSTER: 0: enabled 1
9148 12:43:30.675142 CPU: 00: enabled 1
9149 12:43:30.675262 Root Device scanning...
9150 12:43:30.678465 scan_static_bus for Root Device
9151 12:43:30.682016 CPU_CLUSTER: 0 enabled
9152 12:43:30.685097 scan_static_bus for Root Device done
9153 12:43:30.688096 scan_bus: bus Root Device finished in 8 msecs
9154 12:43:30.688171 done
9155 12:43:30.694565 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9156 12:43:30.698304 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9157 12:43:30.704770 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9158 12:43:30.712524 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9159 12:43:30.712632 Allocating resources...
9160 12:43:30.714291 Reading resources...
9161 12:43:30.718076 Root Device read_resources bus 0 link: 0
9162 12:43:30.721608 DRAM rank0 size:0x100000000,
9163 12:43:30.721676 DRAM rank1 size=0x100000000
9164 12:43:30.727573 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9165 12:43:30.727641 CPU: 00 missing read_resources
9166 12:43:30.734349 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9167 12:43:30.737828 Root Device read_resources bus 0 link: 0 done
9168 12:43:30.741010 Done reading resources.
9169 12:43:30.744290 Show resources in subtree (Root Device)...After reading.
9170 12:43:30.747850 Root Device child on link 0 CPU_CLUSTER: 0
9171 12:43:30.750947 CPU_CLUSTER: 0 child on link 0 CPU: 00
9172 12:43:30.760696 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9173 12:43:30.760773 CPU: 00
9174 12:43:30.767835 Root Device assign_resources, bus 0 link: 0
9175 12:43:30.770638 CPU_CLUSTER: 0 missing set_resources
9176 12:43:30.773792 Root Device assign_resources, bus 0 link: 0 done
9177 12:43:30.777202 Done setting resources.
9178 12:43:30.780390 Show resources in subtree (Root Device)...After assigning values.
9179 12:43:30.784234 Root Device child on link 0 CPU_CLUSTER: 0
9180 12:43:30.790478 CPU_CLUSTER: 0 child on link 0 CPU: 00
9181 12:43:30.797333 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9182 12:43:30.800424 CPU: 00
9183 12:43:30.800495 Done allocating resources.
9184 12:43:30.806663 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9185 12:43:30.806737 Enabling resources...
9186 12:43:30.810337 done.
9187 12:43:30.813191 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9188 12:43:30.816907 Initializing devices...
9189 12:43:30.816980 Root Device init
9190 12:43:30.820132 init hardware done!
9191 12:43:30.820204 0x00000018: ctrlr->caps
9192 12:43:30.823437 52.000 MHz: ctrlr->f_max
9193 12:43:30.826374 0.400 MHz: ctrlr->f_min
9194 12:43:30.829988 0x40ff8080: ctrlr->voltages
9195 12:43:30.830057 sclk: 390625
9196 12:43:30.830118 Bus Width = 1
9197 12:43:30.833249 sclk: 390625
9198 12:43:30.833315 Bus Width = 1
9199 12:43:30.836599 Early init status = 3
9200 12:43:30.840403 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9201 12:43:30.844330 in-header: 03 fc 00 00 01 00 00 00
9202 12:43:30.847753 in-data: 00
9203 12:43:30.850943 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9204 12:43:30.856790 in-header: 03 fd 00 00 00 00 00 00
9205 12:43:30.860872 in-data:
9206 12:43:30.863259 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9207 12:43:30.867930 in-header: 03 fc 00 00 01 00 00 00
9208 12:43:30.870879 in-data: 00
9209 12:43:30.873948 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9210 12:43:30.879802 in-header: 03 fd 00 00 00 00 00 00
9211 12:43:30.883542 in-data:
9212 12:43:30.886513 [SSUSB] Setting up USB HOST controller...
9213 12:43:30.890131 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9214 12:43:30.893290 [SSUSB] phy power-on done.
9215 12:43:30.897009 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9216 12:43:30.902635 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9217 12:43:30.905928 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9218 12:43:30.912854 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9219 12:43:30.920662 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9220 12:43:30.925842 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9221 12:43:30.932607 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9222 12:43:30.939176 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9223 12:43:30.942725 SPM: binary array size = 0x9dc
9224 12:43:30.945502 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9225 12:43:30.952738 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9226 12:43:30.958714 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9227 12:43:30.965849 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9228 12:43:30.968552 configure_display: Starting display init
9229 12:43:31.003263 anx7625_power_on_init: Init interface.
9230 12:43:31.006364 anx7625_disable_pd_protocol: Disabled PD feature.
9231 12:43:31.009738 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9232 12:43:31.037538 anx7625_start_dp_work: Secure OCM version=00
9233 12:43:31.041474 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9234 12:43:31.056024 sp_tx_get_edid_block: EDID Block = 1
9235 12:43:31.158364 Extracted contents:
9236 12:43:31.161943 header: 00 ff ff ff ff ff ff 00
9237 12:43:31.165094 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9238 12:43:31.167857 version: 01 04
9239 12:43:31.171232 basic params: 95 1f 11 78 0a
9240 12:43:31.174859 chroma info: 76 90 94 55 54 90 27 21 50 54
9241 12:43:31.177799 established: 00 00 00
9242 12:43:31.184287 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9243 12:43:31.190777 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9244 12:43:31.194286 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9245 12:43:31.200869 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9246 12:43:31.207286 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9247 12:43:31.210667 extensions: 00
9248 12:43:31.210747 checksum: fb
9249 12:43:31.210811
9250 12:43:31.217374 Manufacturer: IVO Model 57d Serial Number 0
9251 12:43:31.217455 Made week 0 of 2020
9252 12:43:31.220806 EDID version: 1.4
9253 12:43:31.220886 Digital display
9254 12:43:31.223823 6 bits per primary color channel
9255 12:43:31.227608 DisplayPort interface
9256 12:43:31.227693 Maximum image size: 31 cm x 17 cm
9257 12:43:31.230688 Gamma: 220%
9258 12:43:31.230768 Check DPMS levels
9259 12:43:31.237554 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9260 12:43:31.240790 First detailed timing is preferred timing
9261 12:43:31.243457 Established timings supported:
9262 12:43:31.243538 Standard timings supported:
9263 12:43:31.247026 Detailed timings
9264 12:43:31.250162 Hex of detail: 383680a07038204018303c0035ae10000019
9265 12:43:31.256976 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9266 12:43:31.260087 0780 0798 07c8 0820 hborder 0
9267 12:43:31.262977 0438 043b 0447 0458 vborder 0
9268 12:43:31.266553 -hsync -vsync
9269 12:43:31.266633 Did detailed timing
9270 12:43:31.273128 Hex of detail: 000000000000000000000000000000000000
9271 12:43:31.276936 Manufacturer-specified data, tag 0
9272 12:43:31.280230 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9273 12:43:31.282754 ASCII string: InfoVision
9274 12:43:31.286192 Hex of detail: 000000fe00523134304e574635205248200a
9275 12:43:31.289838 ASCII string: R140NWF5 RH
9276 12:43:31.289918 Checksum
9277 12:43:31.293054 Checksum: 0xfb (valid)
9278 12:43:31.296880 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9279 12:43:31.299243 DSI data_rate: 832800000 bps
9280 12:43:31.306377 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9281 12:43:31.308878 anx7625_parse_edid: pixelclock(138800).
9282 12:43:31.312163 hactive(1920), hsync(48), hfp(24), hbp(88)
9283 12:43:31.315868 vactive(1080), vsync(12), vfp(3), vbp(17)
9284 12:43:31.318821 anx7625_dsi_config: config dsi.
9285 12:43:31.325991 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9286 12:43:31.340277 anx7625_dsi_config: success to config DSI
9287 12:43:31.343350 anx7625_dp_start: MIPI phy setup OK.
9288 12:43:31.346950 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9289 12:43:31.350137 mtk_ddp_mode_set invalid vrefresh 60
9290 12:43:31.353414 main_disp_path_setup
9291 12:43:31.353512 ovl_layer_smi_id_en
9292 12:43:31.356912 ovl_layer_smi_id_en
9293 12:43:31.356982 ccorr_config
9294 12:43:31.357042 aal_config
9295 12:43:31.360193 gamma_config
9296 12:43:31.360262 postmask_config
9297 12:43:31.363083 dither_config
9298 12:43:31.366364 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9299 12:43:31.373078 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9300 12:43:31.376386 Root Device init finished in 555 msecs
9301 12:43:31.379695 CPU_CLUSTER: 0 init
9302 12:43:31.386462 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9303 12:43:31.393137 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9304 12:43:31.393237 APU_MBOX 0x190000b0 = 0x10001
9305 12:43:31.396701 APU_MBOX 0x190001b0 = 0x10001
9306 12:43:31.399981 APU_MBOX 0x190005b0 = 0x10001
9307 12:43:31.402808 APU_MBOX 0x190006b0 = 0x10001
9308 12:43:31.410137 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9309 12:43:31.419218 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9310 12:43:31.431641 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9311 12:43:31.438139 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9312 12:43:31.450242 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9313 12:43:31.458955 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9314 12:43:31.462194 CPU_CLUSTER: 0 init finished in 81 msecs
9315 12:43:31.465542 Devices initialized
9316 12:43:31.468898 Show all devs... After init.
9317 12:43:31.468971 Root Device: enabled 1
9318 12:43:31.471921 CPU_CLUSTER: 0: enabled 1
9319 12:43:31.475167 CPU: 00: enabled 1
9320 12:43:31.478638 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9321 12:43:31.482027 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9322 12:43:31.485792 ELOG: NV offset 0x57f000 size 0x1000
9323 12:43:31.492615 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9324 12:43:31.498689 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9325 12:43:31.501879 ELOG: Event(17) added with size 13 at 2023-06-14 12:43:32 UTC
9326 12:43:31.508813 out: cmd=0x121: 03 db 21 01 00 00 00 00
9327 12:43:31.511692 in-header: 03 36 00 00 2c 00 00 00
9328 12:43:31.521637 in-data: 29 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9329 12:43:31.528608 ELOG: Event(A1) added with size 10 at 2023-06-14 12:43:32 UTC
9330 12:43:31.535084 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9331 12:43:31.542137 ELOG: Event(A0) added with size 9 at 2023-06-14 12:43:32 UTC
9332 12:43:31.544895 elog_add_boot_reason: Logged dev mode boot
9333 12:43:31.551574 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9334 12:43:31.551648 Finalize devices...
9335 12:43:31.554784 Devices finalized
9336 12:43:31.558639 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9337 12:43:31.561900 Writing coreboot table at 0xffe64000
9338 12:43:31.564756 0. 000000000010a000-0000000000113fff: RAMSTAGE
9339 12:43:31.571197 1. 0000000040000000-00000000400fffff: RAM
9340 12:43:31.574587 2. 0000000040100000-000000004032afff: RAMSTAGE
9341 12:43:31.578079 3. 000000004032b000-00000000545fffff: RAM
9342 12:43:31.581636 4. 0000000054600000-000000005465ffff: BL31
9343 12:43:31.584362 5. 0000000054660000-00000000ffe63fff: RAM
9344 12:43:31.591420 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9345 12:43:31.594249 7. 0000000100000000-000000023fffffff: RAM
9346 12:43:31.598652 Passing 5 GPIOs to payload:
9347 12:43:31.601146 NAME | PORT | POLARITY | VALUE
9348 12:43:31.608387 EC in RW | 0x000000aa | low | undefined
9349 12:43:31.610897 EC interrupt | 0x00000005 | low | undefined
9350 12:43:31.614347 TPM interrupt | 0x000000ab | high | undefined
9351 12:43:31.620520 SD card detect | 0x00000011 | high | undefined
9352 12:43:31.623956 speaker enable | 0x00000093 | high | undefined
9353 12:43:31.628255 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9354 12:43:31.630567 in-header: 03 f9 00 00 02 00 00 00
9355 12:43:31.633774 in-data: 02 00
9356 12:43:31.637506 ADC[4]: Raw value=901847 ID=7
9357 12:43:31.637588 ADC[3]: Raw value=213546 ID=1
9358 12:43:31.640643 RAM Code: 0x71
9359 12:43:31.644235 ADC[6]: Raw value=75000 ID=0
9360 12:43:31.647027 ADC[5]: Raw value=213546 ID=1
9361 12:43:31.647109 SKU Code: 0x1
9362 12:43:31.653723 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 951a
9363 12:43:31.653803 coreboot table: 964 bytes.
9364 12:43:31.657642 IMD ROOT 0. 0xfffff000 0x00001000
9365 12:43:31.660258 IMD SMALL 1. 0xffffe000 0x00001000
9366 12:43:31.664043 RO MCACHE 2. 0xffffc000 0x00001104
9367 12:43:31.667142 CONSOLE 3. 0xfff7c000 0x00080000
9368 12:43:31.669947 FMAP 4. 0xfff7b000 0x00000452
9369 12:43:31.673550 TIME STAMP 5. 0xfff7a000 0x00000910
9370 12:43:31.676991 VBOOT WORK 6. 0xfff66000 0x00014000
9371 12:43:31.680185 RAMOOPS 7. 0xffe66000 0x00100000
9372 12:43:31.683661 COREBOOT 8. 0xffe64000 0x00002000
9373 12:43:31.686770 IMD small region:
9374 12:43:31.689751 IMD ROOT 0. 0xffffec00 0x00000400
9375 12:43:31.693259 VPD 1. 0xffffeba0 0x0000004c
9376 12:43:31.696425 MMC STATUS 2. 0xffffeb80 0x00000004
9377 12:43:31.703020 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9378 12:43:31.703121 Probing TPM: done!
9379 12:43:31.710102 Connected to device vid:did:rid of 1ae0:0028:00
9380 12:43:31.716522 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9381 12:43:31.719813 Initialized TPM device CR50 revision 0
9382 12:43:31.723409 Checking cr50 for pending updates
9383 12:43:31.728620 Reading cr50 TPM mode
9384 12:43:31.737553 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9385 12:43:31.744141 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9386 12:43:31.784367 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9387 12:43:31.787121 Checking segment from ROM address 0x40100000
9388 12:43:31.790550 Checking segment from ROM address 0x4010001c
9389 12:43:31.797749 Loading segment from ROM address 0x40100000
9390 12:43:31.797858 code (compression=0)
9391 12:43:31.806925 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9392 12:43:31.813555 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9393 12:43:31.813629 it's not compressed!
9394 12:43:31.820240 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9395 12:43:31.827366 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9396 12:43:31.844394 Loading segment from ROM address 0x4010001c
9397 12:43:31.844470 Entry Point 0x80000000
9398 12:43:31.847619 Loaded segments
9399 12:43:31.852149 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9400 12:43:31.857971 Jumping to boot code at 0x80000000(0xffe64000)
9401 12:43:31.864392 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9402 12:43:31.870955 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9403 12:43:31.879496 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9404 12:43:31.882063 Checking segment from ROM address 0x40100000
9405 12:43:31.885486 Checking segment from ROM address 0x4010001c
9406 12:43:31.891867 Loading segment from ROM address 0x40100000
9407 12:43:31.891948 code (compression=1)
9408 12:43:31.899424 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9409 12:43:31.908630 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9410 12:43:31.908712 using LZMA
9411 12:43:31.917451 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9412 12:43:31.923850 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9413 12:43:31.927200 Loading segment from ROM address 0x4010001c
9414 12:43:31.927282 Entry Point 0x54601000
9415 12:43:31.930670 Loaded segments
9416 12:43:31.934170 NOTICE: MT8192 bl31_setup
9417 12:43:31.940610 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9418 12:43:31.944611 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9419 12:43:31.947397 WARNING: region 0:
9420 12:43:31.951307 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9421 12:43:31.951388 WARNING: region 1:
9422 12:43:31.957249 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9423 12:43:31.960608 WARNING: region 2:
9424 12:43:31.964306 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9425 12:43:31.967358 WARNING: region 3:
9426 12:43:31.970615 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9427 12:43:31.973896 WARNING: region 4:
9428 12:43:31.980707 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9429 12:43:31.980817 WARNING: region 5:
9430 12:43:31.983951 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9431 12:43:31.987130 WARNING: region 6:
9432 12:43:31.990667 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9433 12:43:31.993744 WARNING: region 7:
9434 12:43:31.997223 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9435 12:43:32.003812 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9436 12:43:32.007150 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9437 12:43:32.010604 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9438 12:43:32.017731 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9439 12:43:32.020148 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9440 12:43:32.026632 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9441 12:43:32.030659 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9442 12:43:32.033902 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9443 12:43:32.040235 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9444 12:43:32.043724 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9445 12:43:32.050043 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9446 12:43:32.053164 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9447 12:43:32.056696 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9448 12:43:32.063017 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9449 12:43:32.066923 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9450 12:43:32.069900 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9451 12:43:32.076639 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9452 12:43:32.079696 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9453 12:43:32.086552 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9454 12:43:32.090292 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9455 12:43:32.093354 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9456 12:43:32.099351 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9457 12:43:32.103138 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9458 12:43:32.109487 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9459 12:43:32.112526 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9460 12:43:32.116222 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9461 12:43:32.122645 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9462 12:43:32.126011 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9463 12:43:32.132561 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9464 12:43:32.136843 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9465 12:43:32.138948 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9466 12:43:32.145925 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9467 12:43:32.149217 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9468 12:43:32.153256 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9469 12:43:32.159023 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9470 12:43:32.162276 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9471 12:43:32.165596 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9472 12:43:32.168744 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9473 12:43:32.175567 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9474 12:43:32.178796 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9475 12:43:32.182159 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9476 12:43:32.185832 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9477 12:43:32.192262 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9478 12:43:32.196890 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9479 12:43:32.198712 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9480 12:43:32.202134 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9481 12:43:32.208761 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9482 12:43:32.211887 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9483 12:43:32.215136 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9484 12:43:32.221675 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9485 12:43:32.225045 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9486 12:43:32.232234 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9487 12:43:32.235083 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9488 12:43:32.241444 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9489 12:43:32.245331 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9490 12:43:32.248154 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9491 12:43:32.254996 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9492 12:43:32.257951 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9493 12:43:32.264763 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9494 12:43:32.268217 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9495 12:43:32.274825 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9496 12:43:32.277884 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9497 12:43:32.284467 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9498 12:43:32.287955 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9499 12:43:32.294763 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9500 12:43:32.298212 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9501 12:43:32.301033 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9502 12:43:32.308349 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9503 12:43:32.311661 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9504 12:43:32.317783 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9505 12:43:32.321068 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9506 12:43:32.327525 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9507 12:43:32.331763 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9508 12:43:32.334432 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9509 12:43:32.341624 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9510 12:43:32.344205 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9511 12:43:32.351325 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9512 12:43:32.354439 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9513 12:43:32.361237 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9514 12:43:32.364460 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9515 12:43:32.371355 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9516 12:43:32.374166 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9517 12:43:32.377687 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9518 12:43:32.383938 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9519 12:43:32.387358 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9520 12:43:32.394224 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9521 12:43:32.397607 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9522 12:43:32.403940 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9523 12:43:32.406980 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9524 12:43:32.410498 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9525 12:43:32.417016 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9526 12:43:32.420514 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9527 12:43:32.427126 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9528 12:43:32.430277 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9529 12:43:32.437153 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9530 12:43:32.439952 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9531 12:43:32.443710 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9532 12:43:32.450399 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9533 12:43:32.453645 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9534 12:43:32.456709 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9535 12:43:32.460995 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9536 12:43:32.466928 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9537 12:43:32.470355 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9538 12:43:32.477195 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9539 12:43:32.480194 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9540 12:43:32.484007 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9541 12:43:32.490391 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9542 12:43:32.493243 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9543 12:43:32.500315 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9544 12:43:32.503438 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9545 12:43:32.506813 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9546 12:43:32.513280 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9547 12:43:32.516497 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9548 12:43:32.523359 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9549 12:43:32.526767 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9550 12:43:32.530451 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9551 12:43:32.536391 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9552 12:43:32.539952 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9553 12:43:32.543471 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9554 12:43:32.549824 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9555 12:43:32.553024 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9556 12:43:32.556190 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9557 12:43:32.559800 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9558 12:43:32.566430 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9559 12:43:32.569584 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9560 12:43:32.573381 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9561 12:43:32.579389 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9562 12:43:32.583420 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9563 12:43:32.590017 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9564 12:43:32.593038 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9565 12:43:32.596404 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9566 12:43:32.602713 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9567 12:43:32.606334 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9568 12:43:32.613056 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9569 12:43:32.616007 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9570 12:43:32.619409 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9571 12:43:32.626360 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9572 12:43:32.629417 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9573 12:43:32.633116 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9574 12:43:32.639590 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9575 12:43:32.643140 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9576 12:43:32.649147 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9577 12:43:32.652993 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9578 12:43:32.656212 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9579 12:43:32.662856 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9580 12:43:32.666150 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9581 12:43:32.672749 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9582 12:43:32.675730 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9583 12:43:32.679393 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9584 12:43:32.685839 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9585 12:43:32.689086 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9586 12:43:32.695883 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9587 12:43:32.698944 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9588 12:43:32.702346 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9589 12:43:32.709629 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9590 12:43:32.712289 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9591 12:43:32.719236 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9592 12:43:32.722223 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9593 12:43:32.725391 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9594 12:43:32.732143 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9595 12:43:32.735285 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9596 12:43:32.741751 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9597 12:43:32.745980 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9598 12:43:32.750132 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9599 12:43:32.755130 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9600 12:43:32.758462 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9601 12:43:32.764702 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9602 12:43:32.768202 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9603 12:43:32.771393 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9604 12:43:32.777858 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9605 12:43:32.781256 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9606 12:43:32.788341 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9607 12:43:32.791153 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9608 12:43:32.794408 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9609 12:43:32.801080 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9610 12:43:32.804285 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9611 12:43:32.811868 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9612 12:43:32.814336 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9613 12:43:32.820665 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9614 12:43:32.824199 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9615 12:43:32.827252 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9616 12:43:32.833608 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9617 12:43:32.836939 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9618 12:43:32.843774 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9619 12:43:32.846872 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9620 12:43:32.850362 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9621 12:43:32.856678 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9622 12:43:32.860078 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9623 12:43:32.867071 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9624 12:43:32.870371 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9625 12:43:32.873280 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9626 12:43:32.880165 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9627 12:43:32.883449 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9628 12:43:32.889564 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9629 12:43:32.893058 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9630 12:43:32.899603 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9631 12:43:32.902937 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9632 12:43:32.906223 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9633 12:43:32.912610 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9634 12:43:32.916634 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9635 12:43:32.922797 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9636 12:43:32.926359 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9637 12:43:32.932539 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9638 12:43:32.935637 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9639 12:43:32.939731 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9640 12:43:32.946137 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9641 12:43:32.948948 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9642 12:43:32.955515 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9643 12:43:32.959226 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9644 12:43:32.966656 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9645 12:43:32.968740 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9646 12:43:32.972473 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9647 12:43:32.978774 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9648 12:43:32.981936 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9649 12:43:32.988210 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9650 12:43:32.992050 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9651 12:43:32.998426 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9652 12:43:33.002047 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9653 12:43:33.008514 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9654 12:43:33.011707 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9655 12:43:33.014510 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9656 12:43:33.020926 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9657 12:43:33.024538 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9658 12:43:33.031529 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9659 12:43:33.034197 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9660 12:43:33.040751 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9661 12:43:33.044227 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9662 12:43:33.047553 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9663 12:43:33.053956 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9664 12:43:33.057441 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9665 12:43:33.060761 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9666 12:43:33.065180 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9667 12:43:33.070418 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9668 12:43:33.073826 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9669 12:43:33.078037 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9670 12:43:33.083990 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9671 12:43:33.086731 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9672 12:43:33.093471 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9673 12:43:33.096794 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9674 12:43:33.100174 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9675 12:43:33.107024 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9676 12:43:33.110354 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9677 12:43:33.113360 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9678 12:43:33.119661 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9679 12:43:33.123241 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9680 12:43:33.130078 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9681 12:43:33.132856 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9682 12:43:33.136715 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9683 12:43:33.143498 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9684 12:43:33.146595 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9685 12:43:33.149571 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9686 12:43:33.156007 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9687 12:43:33.159434 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9688 12:43:33.162652 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9689 12:43:33.169176 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9690 12:43:33.172777 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9691 12:43:33.179140 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9692 12:43:33.182859 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9693 12:43:33.185999 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9694 12:43:33.192525 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9695 12:43:33.195518 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9696 12:43:33.202000 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9697 12:43:33.205465 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9698 12:43:33.208853 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9699 12:43:33.215272 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9700 12:43:33.218276 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9701 12:43:33.222130 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9702 12:43:33.228318 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9703 12:43:33.232414 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9704 12:43:33.235106 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9705 12:43:33.242010 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9706 12:43:33.245345 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9707 12:43:33.248006 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9708 12:43:33.251706 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9709 12:43:33.258229 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9710 12:43:33.261447 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9711 12:43:33.265527 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9712 12:43:33.267911 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9713 12:43:33.274321 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9714 12:43:33.277918 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9715 12:43:33.281496 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9716 12:43:33.287628 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9717 12:43:33.291214 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9718 12:43:33.294628 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9719 12:43:33.300682 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9720 12:43:33.303932 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9721 12:43:33.310608 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9722 12:43:33.314234 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9723 12:43:33.320519 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9724 12:43:33.323895 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9725 12:43:33.327033 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9726 12:43:33.333746 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9727 12:43:33.336941 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9728 12:43:33.343448 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9729 12:43:33.347074 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9730 12:43:33.353383 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9731 12:43:33.356990 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9732 12:43:33.360355 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9733 12:43:33.366889 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9734 12:43:33.370054 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9735 12:43:33.377566 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9736 12:43:33.379645 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9737 12:43:33.383729 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9738 12:43:33.389907 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9739 12:43:33.393275 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9740 12:43:33.399696 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9741 12:43:33.402963 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9742 12:43:33.409694 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9743 12:43:33.412676 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9744 12:43:33.415679 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9745 12:43:33.422686 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9746 12:43:33.425891 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9747 12:43:33.432240 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9748 12:43:33.435849 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9749 12:43:33.439181 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9750 12:43:33.445728 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9751 12:43:33.449229 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9752 12:43:33.455198 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9753 12:43:33.458322 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9754 12:43:33.465791 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9755 12:43:33.468432 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9756 12:43:33.471915 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9757 12:43:33.478608 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9758 12:43:33.481553 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9759 12:43:33.488420 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9760 12:43:33.491449 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9761 12:43:33.498228 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9762 12:43:33.501453 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9763 12:43:33.504779 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9764 12:43:33.511055 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9765 12:43:33.514853 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9766 12:43:33.521324 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9767 12:43:33.524552 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9768 12:43:33.527692 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9769 12:43:33.534436 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9770 12:43:33.538214 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9771 12:43:33.544151 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9772 12:43:33.547584 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9773 12:43:33.554624 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9774 12:43:33.557677 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9775 12:43:33.560767 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9776 12:43:33.567671 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9777 12:43:33.570573 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9778 12:43:33.577248 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9779 12:43:33.580652 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9780 12:43:33.583959 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9781 12:43:33.590251 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9782 12:43:33.593878 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9783 12:43:33.600482 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9784 12:43:33.603304 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9785 12:43:33.610366 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9786 12:43:33.613690 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9787 12:43:33.619992 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9788 12:43:33.623289 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9789 12:43:33.626627 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9790 12:43:33.633327 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9791 12:43:33.635989 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9792 12:43:33.643377 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9793 12:43:33.646154 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9794 12:43:33.652921 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9795 12:43:33.656303 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9796 12:43:33.659124 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9797 12:43:33.666082 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9798 12:43:33.669114 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9799 12:43:33.675638 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9800 12:43:33.679173 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9801 12:43:33.685860 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9802 12:43:33.689109 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9803 12:43:33.695797 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9804 12:43:33.698706 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9805 12:43:33.702160 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9806 12:43:33.709257 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9807 12:43:33.712272 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9808 12:43:33.718717 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9809 12:43:33.722036 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9810 12:43:33.728660 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9811 12:43:33.731654 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9812 12:43:33.738235 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9813 12:43:33.741592 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9814 12:43:33.745240 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9815 12:43:33.751495 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9816 12:43:33.754618 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9817 12:43:33.761499 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9818 12:43:33.765173 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9819 12:43:33.771186 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9820 12:43:33.774806 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9821 12:43:33.781085 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9822 12:43:33.784393 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9823 12:43:33.791303 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9824 12:43:33.795059 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9825 12:43:33.797569 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9826 12:43:33.804749 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9827 12:43:33.807755 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9828 12:43:33.813959 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9829 12:43:33.817263 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9830 12:43:33.823935 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9831 12:43:33.826895 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9832 12:43:33.834260 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9833 12:43:33.836715 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9834 12:43:33.843570 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9835 12:43:33.846943 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9836 12:43:33.850479 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9837 12:43:33.856669 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9838 12:43:33.860122 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9839 12:43:33.866408 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9840 12:43:33.871279 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9841 12:43:33.876652 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9842 12:43:33.879603 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9843 12:43:33.886675 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9844 12:43:33.890015 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9845 12:43:33.897396 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9846 12:43:33.899332 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9847 12:43:33.906182 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9848 12:43:33.909645 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9849 12:43:33.916075 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9850 12:43:33.919619 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9851 12:43:33.922491 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9852 12:43:33.929623 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9853 12:43:33.933557 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9854 12:43:33.938994 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9855 12:43:33.942519 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9856 12:43:33.948732 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9857 12:43:33.952141 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9858 12:43:33.958564 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9859 12:43:33.965409 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9860 12:43:33.968451 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9861 12:43:33.975438 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9862 12:43:33.978866 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9863 12:43:33.985474 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9864 12:43:33.988328 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9865 12:43:33.994959 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9866 12:43:33.998154 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9867 12:43:34.004851 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9868 12:43:34.008024 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9869 12:43:34.011308 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9870 12:43:34.015145 INFO: [APUAPC] vio 0
9871 12:43:34.021273 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9872 12:43:34.024383 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9873 12:43:34.028310 INFO: [APUAPC] D0_APC_0: 0x400510
9874 12:43:34.031844 INFO: [APUAPC] D0_APC_1: 0x0
9875 12:43:34.034676 INFO: [APUAPC] D0_APC_2: 0x1540
9876 12:43:34.037671 INFO: [APUAPC] D0_APC_3: 0x0
9877 12:43:34.041020 INFO: [APUAPC] D1_APC_0: 0xffffffff
9878 12:43:34.044259 INFO: [APUAPC] D1_APC_1: 0xffffffff
9879 12:43:34.047736 INFO: [APUAPC] D1_APC_2: 0x3fffff
9880 12:43:34.050968 INFO: [APUAPC] D1_APC_3: 0x0
9881 12:43:34.054052 INFO: [APUAPC] D2_APC_0: 0xffffffff
9882 12:43:34.057367 INFO: [APUAPC] D2_APC_1: 0xffffffff
9883 12:43:34.061041 INFO: [APUAPC] D2_APC_2: 0x3fffff
9884 12:43:34.064973 INFO: [APUAPC] D2_APC_3: 0x0
9885 12:43:34.067107 INFO: [APUAPC] D3_APC_0: 0xffffffff
9886 12:43:34.071719 INFO: [APUAPC] D3_APC_1: 0xffffffff
9887 12:43:34.073792 INFO: [APUAPC] D3_APC_2: 0x3fffff
9888 12:43:34.077825 INFO: [APUAPC] D3_APC_3: 0x0
9889 12:43:34.080483 INFO: [APUAPC] D4_APC_0: 0xffffffff
9890 12:43:34.084596 INFO: [APUAPC] D4_APC_1: 0xffffffff
9891 12:43:34.086905 INFO: [APUAPC] D4_APC_2: 0x3fffff
9892 12:43:34.090247 INFO: [APUAPC] D4_APC_3: 0x0
9893 12:43:34.093347 INFO: [APUAPC] D5_APC_0: 0xffffffff
9894 12:43:34.097146 INFO: [APUAPC] D5_APC_1: 0xffffffff
9895 12:43:34.100286 INFO: [APUAPC] D5_APC_2: 0x3fffff
9896 12:43:34.100368 INFO: [APUAPC] D5_APC_3: 0x0
9897 12:43:34.107776 INFO: [APUAPC] D6_APC_0: 0xffffffff
9898 12:43:34.110006 INFO: [APUAPC] D6_APC_1: 0xffffffff
9899 12:43:34.113193 INFO: [APUAPC] D6_APC_2: 0x3fffff
9900 12:43:34.113274 INFO: [APUAPC] D6_APC_3: 0x0
9901 12:43:34.116806 INFO: [APUAPC] D7_APC_0: 0xffffffff
9902 12:43:34.123323 INFO: [APUAPC] D7_APC_1: 0xffffffff
9903 12:43:34.126621 INFO: [APUAPC] D7_APC_2: 0x3fffff
9904 12:43:34.126702 INFO: [APUAPC] D7_APC_3: 0x0
9905 12:43:34.130015 INFO: [APUAPC] D8_APC_0: 0xffffffff
9906 12:43:34.133949 INFO: [APUAPC] D8_APC_1: 0xffffffff
9907 12:43:34.136380 INFO: [APUAPC] D8_APC_2: 0x3fffff
9908 12:43:34.139601 INFO: [APUAPC] D8_APC_3: 0x0
9909 12:43:34.143478 INFO: [APUAPC] D9_APC_0: 0xffffffff
9910 12:43:34.146425 INFO: [APUAPC] D9_APC_1: 0xffffffff
9911 12:43:34.149536 INFO: [APUAPC] D9_APC_2: 0x3fffff
9912 12:43:34.153564 INFO: [APUAPC] D9_APC_3: 0x0
9913 12:43:34.155854 INFO: [APUAPC] D10_APC_0: 0xffffffff
9914 12:43:34.159267 INFO: [APUAPC] D10_APC_1: 0xffffffff
9915 12:43:34.162626 INFO: [APUAPC] D10_APC_2: 0x3fffff
9916 12:43:34.165958 INFO: [APUAPC] D10_APC_3: 0x0
9917 12:43:34.169579 INFO: [APUAPC] D11_APC_0: 0xffffffff
9918 12:43:34.172694 INFO: [APUAPC] D11_APC_1: 0xffffffff
9919 12:43:34.179417 INFO: [APUAPC] D11_APC_2: 0x3fffff
9920 12:43:34.179497 INFO: [APUAPC] D11_APC_3: 0x0
9921 12:43:34.182605 INFO: [APUAPC] D12_APC_0: 0xffffffff
9922 12:43:34.188782 INFO: [APUAPC] D12_APC_1: 0xffffffff
9923 12:43:34.192232 INFO: [APUAPC] D12_APC_2: 0x3fffff
9924 12:43:34.192305 INFO: [APUAPC] D12_APC_3: 0x0
9925 12:43:34.195846 INFO: [APUAPC] D13_APC_0: 0xffffffff
9926 12:43:34.202008 INFO: [APUAPC] D13_APC_1: 0xffffffff
9927 12:43:34.205817 INFO: [APUAPC] D13_APC_2: 0x3fffff
9928 12:43:34.205891 INFO: [APUAPC] D13_APC_3: 0x0
9929 12:43:34.212364 INFO: [APUAPC] D14_APC_0: 0xffffffff
9930 12:43:34.216262 INFO: [APUAPC] D14_APC_1: 0xffffffff
9931 12:43:34.219041 INFO: [APUAPC] D14_APC_2: 0x3fffff
9932 12:43:34.222080 INFO: [APUAPC] D14_APC_3: 0x0
9933 12:43:34.225511 INFO: [APUAPC] D15_APC_0: 0xffffffff
9934 12:43:34.229253 INFO: [APUAPC] D15_APC_1: 0xffffffff
9935 12:43:34.232058 INFO: [APUAPC] D15_APC_2: 0x3fffff
9936 12:43:34.235865 INFO: [APUAPC] D15_APC_3: 0x0
9937 12:43:34.235933 INFO: [APUAPC] APC_CON: 0x4
9938 12:43:34.238702 INFO: [NOCDAPC] D0_APC_0: 0x0
9939 12:43:34.242077 INFO: [NOCDAPC] D0_APC_1: 0x0
9940 12:43:34.245264 INFO: [NOCDAPC] D1_APC_0: 0x0
9941 12:43:34.248939 INFO: [NOCDAPC] D1_APC_1: 0xfff
9942 12:43:34.252140 INFO: [NOCDAPC] D2_APC_0: 0x0
9943 12:43:34.255197 INFO: [NOCDAPC] D2_APC_1: 0xfff
9944 12:43:34.258350 INFO: [NOCDAPC] D3_APC_0: 0x0
9945 12:43:34.261509 INFO: [NOCDAPC] D3_APC_1: 0xfff
9946 12:43:34.264941 INFO: [NOCDAPC] D4_APC_0: 0x0
9947 12:43:34.267985 INFO: [NOCDAPC] D4_APC_1: 0xfff
9948 12:43:34.268110 INFO: [NOCDAPC] D5_APC_0: 0x0
9949 12:43:34.271728 INFO: [NOCDAPC] D5_APC_1: 0xfff
9950 12:43:34.274634 INFO: [NOCDAPC] D6_APC_0: 0x0
9951 12:43:34.278116 INFO: [NOCDAPC] D6_APC_1: 0xfff
9952 12:43:34.281242 INFO: [NOCDAPC] D7_APC_0: 0x0
9953 12:43:34.284562 INFO: [NOCDAPC] D7_APC_1: 0xfff
9954 12:43:34.288365 INFO: [NOCDAPC] D8_APC_0: 0x0
9955 12:43:34.290888 INFO: [NOCDAPC] D8_APC_1: 0xfff
9956 12:43:34.294611 INFO: [NOCDAPC] D9_APC_0: 0x0
9957 12:43:34.297385 INFO: [NOCDAPC] D9_APC_1: 0xfff
9958 12:43:34.301210 INFO: [NOCDAPC] D10_APC_0: 0x0
9959 12:43:34.304172 INFO: [NOCDAPC] D10_APC_1: 0xfff
9960 12:43:34.307525 INFO: [NOCDAPC] D11_APC_0: 0x0
9961 12:43:34.307599 INFO: [NOCDAPC] D11_APC_1: 0xfff
9962 12:43:34.310791 INFO: [NOCDAPC] D12_APC_0: 0x0
9963 12:43:34.314030 INFO: [NOCDAPC] D12_APC_1: 0xfff
9964 12:43:34.317644 INFO: [NOCDAPC] D13_APC_0: 0x0
9965 12:43:34.320654 INFO: [NOCDAPC] D13_APC_1: 0xfff
9966 12:43:34.324185 INFO: [NOCDAPC] D14_APC_0: 0x0
9967 12:43:34.327367 INFO: [NOCDAPC] D14_APC_1: 0xfff
9968 12:43:34.330773 INFO: [NOCDAPC] D15_APC_0: 0x0
9969 12:43:34.334102 INFO: [NOCDAPC] D15_APC_1: 0xfff
9970 12:43:34.337875 INFO: [NOCDAPC] APC_CON: 0x4
9971 12:43:34.340508 INFO: [APUAPC] set_apusys_apc done
9972 12:43:34.344024 INFO: [DEVAPC] devapc_init done
9973 12:43:34.347047 INFO: GICv3 without legacy support detected.
9974 12:43:34.350423 INFO: ARM GICv3 driver initialized in EL3
9975 12:43:34.354121 INFO: Maximum SPI INTID supported: 639
9976 12:43:34.360578 INFO: BL31: Initializing runtime services
9977 12:43:34.363817 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9978 12:43:34.367348 INFO: SPM: enable CPC mode
9979 12:43:34.373426 INFO: mcdi ready for mcusys-off-idle and system suspend
9980 12:43:34.376588 INFO: BL31: Preparing for EL3 exit to normal world
9981 12:43:34.380192 INFO: Entry point address = 0x80000000
9982 12:43:34.383237 INFO: SPSR = 0x8
9983 12:43:34.390277
9984 12:43:34.390357
9985 12:43:34.390421
9986 12:43:34.391959 Starting depthcharge on Spherion...
9987 12:43:34.392048
9988 12:43:34.392127 Wipe memory regions:
9989 12:43:34.392184
9990 12:43:34.392805 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
9991 12:43:34.392903 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
9992 12:43:34.392983 Setting prompt string to ['asurada:']
9993 12:43:34.393058 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
9994 12:43:34.395288 [0x00000040000000, 0x00000054600000)
9995 12:43:34.517807
9996 12:43:34.517924 [0x00000054660000, 0x00000080000000)
9997 12:43:34.778420
9998 12:43:34.778555 [0x000000821a7280, 0x000000ffe64000)
9999 12:43:35.523648
10000 12:43:35.523816 [0x00000100000000, 0x00000240000000)
10001 12:43:37.414094
10002 12:43:37.416773 Initializing XHCI USB controller at 0x11200000.
10003 12:43:38.455701
10004 12:43:38.458422 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10005 12:43:38.458860
10006 12:43:38.459192
10007 12:43:38.459496
10008 12:43:38.460229 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10010 12:43:38.561695 asurada: tftpboot 192.168.201.1 10724871/tftp-deploy-y2kwtekg/kernel/image.itb 10724871/tftp-deploy-y2kwtekg/kernel/cmdline
10011 12:43:38.562232 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10012 12:43:38.562657 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10013 12:43:38.566889 tftpboot 192.168.201.1 10724871/tftp-deploy-y2kwtekg/kernel/image.itp-deploy-y2kwtekg/kernel/cmdline
10014 12:43:38.567247
10015 12:43:38.567313 Waiting for link
10016 12:43:38.727657
10017 12:43:38.727789 R8152: Initializing
10018 12:43:38.727865
10019 12:43:38.730324 Version 6 (ocp_data = 5c30)
10020 12:43:38.730407
10021 12:43:38.734113 R8152: Done initializing
10022 12:43:38.734195
10023 12:43:38.734260 Adding net device
10024 12:43:40.822483
10025 12:43:40.822632 done.
10026 12:43:40.822703
10027 12:43:40.822763 MAC: 00:24:32:30:7c:7b
10028 12:43:40.822821
10029 12:43:40.824993 Sending DHCP discover... done.
10030 12:43:40.825076
10031 12:43:40.828981 Waiting for reply... done.
10032 12:43:40.829064
10033 12:43:40.831435 Sending DHCP request... done.
10034 12:43:40.831515
10035 12:43:40.831580 Waiting for reply... done.
10036 12:43:40.831640
10037 12:43:40.835199 My ip is 192.168.201.14
10038 12:43:40.835279
10039 12:43:40.838248 The DHCP server ip is 192.168.201.1
10040 12:43:40.838329
10041 12:43:40.841991 TFTP server IP predefined by user: 192.168.201.1
10042 12:43:40.842072
10043 12:43:40.848507 Bootfile predefined by user: 10724871/tftp-deploy-y2kwtekg/kernel/image.itb
10044 12:43:40.848589
10045 12:43:40.851479 Sending tftp read request... done.
10046 12:43:40.851559
10047 12:43:40.854809 Waiting for the transfer...
10048 12:43:40.854920
10049 12:43:41.403080 00000000 ################################################################
10050 12:43:41.403231
10051 12:43:41.949709 00080000 ################################################################
10052 12:43:41.949855
10053 12:43:42.491753 00100000 ################################################################
10054 12:43:42.491922
10055 12:43:43.052274 00180000 ################################################################
10056 12:43:43.052411
10057 12:43:43.597520 00200000 ################################################################
10058 12:43:43.597650
10059 12:43:44.120647 00280000 ################################################################
10060 12:43:44.120786
10061 12:43:44.645451 00300000 ################################################################
10062 12:43:44.645603
10063 12:43:45.185015 00380000 ################################################################
10064 12:43:45.185163
10065 12:43:45.714560 00400000 ################################################################
10066 12:43:45.714697
10067 12:43:46.253759 00480000 ################################################################
10068 12:43:46.253895
10069 12:43:46.809209 00500000 ################################################################
10070 12:43:46.809360
10071 12:43:47.373248 00580000 ################################################################
10072 12:43:47.373396
10073 12:43:47.920752 00600000 ################################################################
10074 12:43:47.920900
10075 12:43:48.479145 00680000 ################################################################
10076 12:43:48.479301
10077 12:43:49.016065 00700000 ################################################################
10078 12:43:49.016216
10079 12:43:49.580796 00780000 ################################################################
10080 12:43:49.580953
10081 12:43:50.154120 00800000 ################################################################
10082 12:43:50.154273
10083 12:43:50.731076 00880000 ################################################################
10084 12:43:50.731229
10085 12:43:51.317365 00900000 ################################################################
10086 12:43:51.317517
10087 12:43:51.899794 00980000 ################################################################
10088 12:43:51.899974
10089 12:43:52.481331 00a00000 ################################################################
10090 12:43:52.481488
10091 12:43:53.050950 00a80000 ################################################################
10092 12:43:53.051103
10093 12:43:53.621350 00b00000 ################################################################
10094 12:43:53.621510
10095 12:43:54.197767 00b80000 ################################################################
10096 12:43:54.197920
10097 12:43:54.746583 00c00000 ################################################################
10098 12:43:54.746739
10099 12:43:55.305115 00c80000 ################################################################
10100 12:43:55.305275
10101 12:43:55.847243 00d00000 ################################################################
10102 12:43:55.847393
10103 12:43:56.377952 00d80000 ################################################################
10104 12:43:56.378104
10105 12:43:56.918567 00e00000 ################################################################
10106 12:43:56.918723
10107 12:43:57.445989 00e80000 ################################################################
10108 12:43:57.446136
10109 12:43:57.985774 00f00000 ################################################################
10110 12:43:57.985926
10111 12:43:58.556287 00f80000 ################################################################
10112 12:43:58.556438
10113 12:43:59.128661 01000000 ################################################################
10114 12:43:59.128813
10115 12:43:59.699774 01080000 ################################################################
10116 12:43:59.699936
10117 12:44:00.268213 01100000 ################################################################
10118 12:44:00.268457
10119 12:44:00.808798 01180000 ################################################################
10120 12:44:00.808935
10121 12:44:01.427137 01200000 ################################################################
10122 12:44:01.427268
10123 12:44:02.031478 01280000 ################################################################
10124 12:44:02.031612
10125 12:44:02.670106 01300000 ################################################################
10126 12:44:02.670599
10127 12:44:03.348877 01380000 ################################################################
10128 12:44:03.349414
10129 12:44:04.020532 01400000 ################################################################
10130 12:44:04.021052
10131 12:44:04.705669 01480000 ################################################################
10132 12:44:04.706264
10133 12:44:05.391201 01500000 ################################################################
10134 12:44:05.391738
10135 12:44:06.055744 01580000 ################################################################
10136 12:44:06.055906
10137 12:44:06.635924 01600000 ################################################################
10138 12:44:06.636133
10139 12:44:07.189535 01680000 ################################################################
10140 12:44:07.189672
10141 12:44:07.741350 01700000 ################################################################
10142 12:44:07.741487
10143 12:44:08.327993 01780000 ################################################################
10144 12:44:08.328157
10145 12:44:08.938795 01800000 ################################################################
10146 12:44:08.938941
10147 12:44:09.585736 01880000 ################################################################
10148 12:44:09.585885
10149 12:44:10.137018 01900000 ################################################################
10150 12:44:10.137169
10151 12:44:10.650346 01980000 ################################################################
10152 12:44:10.650480
10153 12:44:11.189378 01a00000 ################################################################
10154 12:44:11.189508
10155 12:44:11.728808 01a80000 ################################################################
10156 12:44:11.728942
10157 12:44:12.242698 01b00000 ################################################################
10158 12:44:12.242834
10159 12:44:12.797383 01b80000 ################################################################
10160 12:44:12.797522
10161 12:44:13.349004 01c00000 ################################################################
10162 12:44:13.349146
10163 12:44:13.901273 01c80000 ################################################################
10164 12:44:13.901415
10165 12:44:14.444075 01d00000 ################################################################
10166 12:44:14.444212
10167 12:44:14.984609 01d80000 ################################################################
10168 12:44:14.984774
10169 12:44:15.514295 01e00000 ################################################################
10170 12:44:15.514438
10171 12:44:16.068018 01e80000 ################################################################
10172 12:44:16.068178
10173 12:44:16.628062 01f00000 ################################################################
10174 12:44:16.628210
10175 12:44:17.151870 01f80000 ################################################################
10176 12:44:17.152007
10177 12:44:17.687766 02000000 ################################################################
10178 12:44:17.687911
10179 12:44:18.248640 02080000 ################################################################
10180 12:44:18.248778
10181 12:44:18.804670 02100000 ################################################################
10182 12:44:18.804803
10183 12:44:19.357224 02180000 ################################################################
10184 12:44:19.357371
10185 12:44:19.913241 02200000 ################################################################
10186 12:44:19.913383
10187 12:44:20.486679 02280000 ################################################################
10188 12:44:20.486823
10189 12:44:21.046118 02300000 ################################################################
10190 12:44:21.046265
10191 12:44:21.617807 02380000 ################################################################
10192 12:44:21.617982
10193 12:44:22.186299 02400000 ################################################################
10194 12:44:22.186448
10195 12:44:22.768086 02480000 ################################################################
10196 12:44:22.768266
10197 12:44:23.328513 02500000 ################################################################
10198 12:44:23.328664
10199 12:44:23.899057 02580000 ################################################################
10200 12:44:23.899195
10201 12:44:24.439792 02600000 ################################################################
10202 12:44:24.439931
10203 12:44:25.009132 02680000 ################################################################
10204 12:44:25.009271
10205 12:44:25.585646 02700000 ################################################################
10206 12:44:25.585785
10207 12:44:26.159125 02780000 ################################################################
10208 12:44:26.159264
10209 12:44:26.698681 02800000 ################################################################
10210 12:44:26.698823
10211 12:44:27.245394 02880000 ################################################################
10212 12:44:27.245571
10213 12:44:27.798640 02900000 ################################################################
10214 12:44:27.798788
10215 12:44:28.360941 02980000 ################################################################
10216 12:44:28.361108
10217 12:44:28.911687 02a00000 ################################################################
10218 12:44:28.911824
10219 12:44:29.440149 02a80000 ################################################################
10220 12:44:29.440293
10221 12:44:29.964586 02b00000 ################################################################
10222 12:44:29.964729
10223 12:44:30.486120 02b80000 ################################################################
10224 12:44:30.486265
10225 12:44:31.020404 02c00000 ################################################################
10226 12:44:31.020549
10227 12:44:31.531396 02c80000 ################################################################
10228 12:44:31.531539
10229 12:44:32.049567 02d00000 ################################################################
10230 12:44:32.049700
10231 12:44:32.569753 02d80000 ################################################################
10232 12:44:32.569921
10233 12:44:33.096552 02e00000 ################################################################
10234 12:44:33.096697
10235 12:44:33.636394 02e80000 ################################################################
10236 12:44:33.636581
10237 12:44:34.175683 02f00000 ################################################################
10238 12:44:34.175854
10239 12:44:34.690306 02f80000 ################################################################
10240 12:44:34.690445
10241 12:44:35.217957 03000000 ################################################################
10242 12:44:35.218110
10243 12:44:35.757305 03080000 ################################################################
10244 12:44:35.757443
10245 12:44:36.273722 03100000 ################################################################
10246 12:44:36.273854
10247 12:44:36.813859 03180000 ################################################################
10248 12:44:36.814002
10249 12:44:37.348084 03200000 ################################################################
10250 12:44:37.348226
10251 12:44:37.883077 03280000 ################################################################
10252 12:44:37.883221
10253 12:44:38.429702 03300000 ################################################################
10254 12:44:38.429837
10255 12:44:38.951859 03380000 ################################################################
10256 12:44:38.952050
10257 12:44:39.479135 03400000 ################################################################
10258 12:44:39.479290
10259 12:44:40.020827 03480000 ################################################################
10260 12:44:40.020983
10261 12:44:40.574090 03500000 ################################################################
10262 12:44:40.574231
10263 12:44:41.123141 03580000 ################################################################
10264 12:44:41.123287
10265 12:44:41.664377 03600000 ################################################################
10266 12:44:41.664528
10267 12:44:42.200535 03680000 ################################################################
10268 12:44:42.200715
10269 12:44:42.399590 03700000 ######################## done.
10270 12:44:42.399741
10271 12:44:42.403248 The bootfile was 57866866 bytes long.
10272 12:44:42.403347
10273 12:44:42.406481 Sending tftp read request... done.
10274 12:44:42.406621
10275 12:44:42.406736 Waiting for the transfer...
10276 12:44:42.409621
10277 12:44:42.409707 00000000 # done.
10278 12:44:42.409776
10279 12:44:42.415984 Command line loaded dynamically from TFTP file: 10724871/tftp-deploy-y2kwtekg/kernel/cmdline
10280 12:44:42.416116
10281 12:44:42.429739 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10282 12:44:42.429875
10283 12:44:42.429945 Loading FIT.
10284 12:44:42.430007
10285 12:44:42.432613 Image ramdisk-1 has 47375532 bytes.
10286 12:44:42.432699
10287 12:44:42.436107 Image fdt-1 has 46924 bytes.
10288 12:44:42.436201
10289 12:44:42.439235 Image kernel-1 has 10442380 bytes.
10290 12:44:42.439322
10291 12:44:42.449464 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10292 12:44:42.449580
10293 12:44:42.465614 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10294 12:44:42.465758
10295 12:44:42.469228 Choosing best match conf-1 for compat google,spherion-rev2.
10296 12:44:42.472753
10297 12:44:42.475968 Connected to device vid:did:rid of 1ae0:0028:00
10298 12:44:42.487250
10299 12:44:42.489787 tpm_get_response: command 0x17b, return code 0x0
10300 12:44:42.489894
10301 12:44:42.492735 ec_init: CrosEC protocol v3 supported (256, 248)
10302 12:44:42.496834
10303 12:44:42.500713 tpm_cleanup: add release locality here.
10304 12:44:42.500805
10305 12:44:42.500871 Shutting down all USB controllers.
10306 12:44:42.504337
10307 12:44:42.504415 Removing current net device
10308 12:44:42.504477
10309 12:44:42.509964 Exiting depthcharge with code 4 at timestamp: 97354456
10310 12:44:42.510053
10311 12:44:42.513379 LZMA decompressing kernel-1 to 0x821a6718
10312 12:44:42.513463
10313 12:44:42.516532 LZMA decompressing kernel-1 to 0x40000000
10314 12:44:43.827691
10315 12:44:43.827847 jumping to kernel
10316 12:44:43.828286 end: 2.2.4 bootloader-commands (duration 00:01:09) [common]
10317 12:44:43.828390 start: 2.2.5 auto-login-action (timeout 00:03:16) [common]
10318 12:44:43.828467 Setting prompt string to ['Linux version [0-9]']
10319 12:44:43.828535 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10320 12:44:43.828603 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10321 12:44:43.909277
10322 12:44:43.912508 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10323 12:44:43.916078 start: 2.2.5.1 login-action (timeout 00:03:16) [common]
10324 12:44:43.916204 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10325 12:44:43.916308 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10326 12:44:43.916384 Using line separator: #'\n'#
10327 12:44:43.916444 No login prompt set.
10328 12:44:43.916503 Parsing kernel messages
10329 12:44:43.916558 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10330 12:44:43.916660 [login-action] Waiting for messages, (timeout 00:03:16)
10331 12:44:43.935621 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j35827-arm64-gcc-10-defconfig-arm64-chromebook-fwl9s) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jun 14 12:30:40 UTC 2023
10332 12:44:43.939164 [ 0.000000] random: crng init done
10333 12:44:43.942013 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10334 12:44:43.945342 [ 0.000000] efi: UEFI not found.
10335 12:44:43.955907 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10336 12:44:43.961825 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10337 12:44:43.972090 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10338 12:44:43.981852 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10339 12:44:43.989197 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10340 12:44:43.995240 [ 0.000000] printk: bootconsole [mtk8250] enabled
10341 12:44:44.001422 [ 0.000000] NUMA: No NUMA configuration found
10342 12:44:44.007991 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10343 12:44:44.011481 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10344 12:44:44.014601 [ 0.000000] Zone ranges:
10345 12:44:44.021152 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10346 12:44:44.024388 [ 0.000000] DMA32 empty
10347 12:44:44.031248 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10348 12:44:44.034059 [ 0.000000] Movable zone start for each node
10349 12:44:44.038504 [ 0.000000] Early memory node ranges
10350 12:44:44.044439 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10351 12:44:44.050535 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10352 12:44:44.057375 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10353 12:44:44.064200 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10354 12:44:44.071027 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10355 12:44:44.077202 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10356 12:44:44.132851 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10357 12:44:44.140083 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10358 12:44:44.146258 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10359 12:44:44.149690 [ 0.000000] psci: probing for conduit method from DT.
10360 12:44:44.156488 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10361 12:44:44.159693 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10362 12:44:44.166565 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10363 12:44:44.169462 [ 0.000000] psci: SMC Calling Convention v1.2
10364 12:44:44.175869 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10365 12:44:44.179488 [ 0.000000] Detected VIPT I-cache on CPU0
10366 12:44:44.186124 [ 0.000000] CPU features: detected: GIC system register CPU interface
10367 12:44:44.192831 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10368 12:44:44.199184 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10369 12:44:44.205604 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10370 12:44:44.215754 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10371 12:44:44.222459 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10372 12:44:44.225138 [ 0.000000] alternatives: applying boot alternatives
10373 12:44:44.232112 [ 0.000000] Fallback order for Node 0: 0
10374 12:44:44.238851 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10375 12:44:44.242114 [ 0.000000] Policy zone: Normal
10376 12:44:44.251680 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10377 12:44:44.265441 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10378 12:44:44.275172 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10379 12:44:44.284855 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10380 12:44:44.291932 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10381 12:44:44.295291 <6>[ 0.000000] software IO TLB: area num 8.
10382 12:44:44.352159 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10383 12:44:44.501241 <6>[ 0.000000] Memory: 7924892K/8385536K available (17984K kernel code, 4098K rwdata, 15868K rodata, 8384K init, 615K bss, 427876K reserved, 32768K cma-reserved)
10384 12:44:44.507631 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10385 12:44:44.514746 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10386 12:44:44.517971 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10387 12:44:44.524457 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10388 12:44:44.530700 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10389 12:44:44.534144 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10390 12:44:44.543867 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10391 12:44:44.550606 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10392 12:44:44.557670 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10393 12:44:44.564048 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10394 12:44:44.567665 <6>[ 0.000000] GICv3: 608 SPIs implemented
10395 12:44:44.570983 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10396 12:44:44.577614 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10397 12:44:44.580665 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10398 12:44:44.587286 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10399 12:44:44.600305 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10400 12:44:44.613903 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10401 12:44:44.620230 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10402 12:44:44.628209 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10403 12:44:44.641061 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10404 12:44:44.647664 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10405 12:44:44.655435 <6>[ 0.009209] Console: colour dummy device 80x25
10406 12:44:44.664469 <6>[ 0.013933] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10407 12:44:44.671142 <6>[ 0.024440] pid_max: default: 32768 minimum: 301
10408 12:44:44.674045 <6>[ 0.029344] LSM: Security Framework initializing
10409 12:44:44.680815 <6>[ 0.034284] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10410 12:44:44.690683 <6>[ 0.042098] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10411 12:44:44.700623 <6>[ 0.051539] cblist_init_generic: Setting adjustable number of callback queues.
10412 12:44:44.703796 <6>[ 0.059038] cblist_init_generic: Setting shift to 3 and lim to 1.
10413 12:44:44.710837 <6>[ 0.065415] cblist_init_generic: Setting shift to 3 and lim to 1.
10414 12:44:44.717251 <6>[ 0.071864] rcu: Hierarchical SRCU implementation.
10415 12:44:44.724319 <6>[ 0.076878] rcu: Max phase no-delay instances is 1000.
10416 12:44:44.730798 <6>[ 0.083888] EFI services will not be available.
10417 12:44:44.733636 <6>[ 0.088854] smp: Bringing up secondary CPUs ...
10418 12:44:44.741790 <6>[ 0.093905] Detected VIPT I-cache on CPU1
10419 12:44:44.748267 <6>[ 0.093976] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10420 12:44:44.754487 <6>[ 0.094006] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10421 12:44:44.758620 <6>[ 0.094350] Detected VIPT I-cache on CPU2
10422 12:44:44.768350 <6>[ 0.094407] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10423 12:44:44.774888 <6>[ 0.094425] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10424 12:44:44.777695 <6>[ 0.094689] Detected VIPT I-cache on CPU3
10425 12:44:44.784258 <6>[ 0.094737] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10426 12:44:44.790920 <6>[ 0.094752] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10427 12:44:44.794285 <6>[ 0.095059] CPU features: detected: Spectre-v4
10428 12:44:44.801424 <6>[ 0.095066] CPU features: detected: Spectre-BHB
10429 12:44:44.804412 <6>[ 0.095072] Detected PIPT I-cache on CPU4
10430 12:44:44.810562 <6>[ 0.095130] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10431 12:44:44.817296 <6>[ 0.095147] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10432 12:44:44.823975 <6>[ 0.095438] Detected PIPT I-cache on CPU5
10433 12:44:44.830892 <6>[ 0.095501] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10434 12:44:44.837281 <6>[ 0.095517] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10435 12:44:44.840719 <6>[ 0.095800] Detected PIPT I-cache on CPU6
10436 12:44:44.847311 <6>[ 0.095865] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10437 12:44:44.854114 <6>[ 0.095881] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10438 12:44:44.860814 <6>[ 0.096176] Detected PIPT I-cache on CPU7
10439 12:44:44.867092 <6>[ 0.096240] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10440 12:44:44.874285 <6>[ 0.096256] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10441 12:44:44.876823 <6>[ 0.096303] smp: Brought up 1 node, 8 CPUs
10442 12:44:44.884112 <6>[ 0.237582] SMP: Total of 8 processors activated.
10443 12:44:44.886474 <6>[ 0.242503] CPU features: detected: 32-bit EL0 Support
10444 12:44:44.896445 <6>[ 0.247900] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10445 12:44:44.903307 <6>[ 0.256754] CPU features: detected: Common not Private translations
10446 12:44:44.910051 <6>[ 0.263230] CPU features: detected: CRC32 instructions
10447 12:44:44.916870 <6>[ 0.268581] CPU features: detected: RCpc load-acquire (LDAPR)
10448 12:44:44.919831 <6>[ 0.274541] CPU features: detected: LSE atomic instructions
10449 12:44:44.926049 <6>[ 0.280323] CPU features: detected: Privileged Access Never
10450 12:44:44.932727 <6>[ 0.286138] CPU features: detected: RAS Extension Support
10451 12:44:44.939105 <6>[ 0.291747] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10452 12:44:44.942644 <6>[ 0.298967] CPU: All CPU(s) started at EL2
10453 12:44:44.949258 <6>[ 0.303284] alternatives: applying system-wide alternatives
10454 12:44:44.959130 <6>[ 0.313985] devtmpfs: initialized
10455 12:44:44.974861 <6>[ 0.322823] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10456 12:44:44.981075 <6>[ 0.332782] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10457 12:44:44.987923 <6>[ 0.340509] pinctrl core: initialized pinctrl subsystem
10458 12:44:44.991132 <6>[ 0.347175] DMI not present or invalid.
10459 12:44:44.997634 <6>[ 0.351581] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10460 12:44:45.007438 <6>[ 0.358458] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10461 12:44:45.014509 <6>[ 0.366040] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10462 12:44:45.024721 <6>[ 0.374252] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10463 12:44:45.027529 <6>[ 0.382498] audit: initializing netlink subsys (disabled)
10464 12:44:45.037327 <5>[ 0.388194] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10465 12:44:45.044251 <6>[ 0.388907] thermal_sys: Registered thermal governor 'step_wise'
10466 12:44:45.050427 <6>[ 0.396160] thermal_sys: Registered thermal governor 'power_allocator'
10467 12:44:45.053497 <6>[ 0.402417] cpuidle: using governor menu
10468 12:44:45.060592 <6>[ 0.413376] NET: Registered PF_QIPCRTR protocol family
10469 12:44:45.067567 <6>[ 0.418859] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10470 12:44:45.070686 <6>[ 0.425960] ASID allocator initialised with 32768 entries
10471 12:44:45.077791 <6>[ 0.432531] Serial: AMBA PL011 UART driver
10472 12:44:45.086555 <4>[ 0.441177] Trying to register duplicate clock ID: 134
10473 12:44:45.140807 <6>[ 0.498677] KASLR enabled
10474 12:44:45.154670 <6>[ 0.506394] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10475 12:44:45.161509 <6>[ 0.513408] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10476 12:44:45.168175 <6>[ 0.519896] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10477 12:44:45.174642 <6>[ 0.526900] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10478 12:44:45.181559 <6>[ 0.533386] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10479 12:44:45.187980 <6>[ 0.540392] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10480 12:44:45.194519 <6>[ 0.546876] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10481 12:44:45.201813 <6>[ 0.553879] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10482 12:44:45.204323 <6>[ 0.561397] ACPI: Interpreter disabled.
10483 12:44:45.213265 <6>[ 0.567790] iommu: Default domain type: Translated
10484 12:44:45.219722 <6>[ 0.572899] iommu: DMA domain TLB invalidation policy: strict mode
10485 12:44:45.222789 <5>[ 0.579554] SCSI subsystem initialized
10486 12:44:45.229719 <6>[ 0.583721] usbcore: registered new interface driver usbfs
10487 12:44:45.235767 <6>[ 0.589451] usbcore: registered new interface driver hub
10488 12:44:45.239317 <6>[ 0.595005] usbcore: registered new device driver usb
10489 12:44:45.246179 <6>[ 0.601092] pps_core: LinuxPPS API ver. 1 registered
10490 12:44:45.255970 <6>[ 0.606286] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10491 12:44:45.259441 <6>[ 0.615632] PTP clock support registered
10492 12:44:45.262606 <6>[ 0.619875] EDAC MC: Ver: 3.0.0
10493 12:44:45.270053 <6>[ 0.625021] FPGA manager framework
10494 12:44:45.276686 <6>[ 0.628704] Advanced Linux Sound Architecture Driver Initialized.
10495 12:44:45.279846 <6>[ 0.635474] vgaarb: loaded
10496 12:44:45.286375 <6>[ 0.638630] clocksource: Switched to clocksource arch_sys_counter
10497 12:44:45.289899 <5>[ 0.645074] VFS: Disk quotas dquot_6.6.0
10498 12:44:45.296221 <6>[ 0.649260] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10499 12:44:45.300282 <6>[ 0.656445] pnp: PnP ACPI: disabled
10500 12:44:45.308624 <6>[ 0.663172] NET: Registered PF_INET protocol family
10501 12:44:45.318347 <6>[ 0.668774] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10502 12:44:45.329362 <6>[ 0.681094] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10503 12:44:45.339759 <6>[ 0.689909] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10504 12:44:45.346054 <6>[ 0.697880] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10505 12:44:45.355979 <6>[ 0.706578] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10506 12:44:45.363005 <6>[ 0.716319] TCP: Hash tables configured (established 65536 bind 65536)
10507 12:44:45.369415 <6>[ 0.723180] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10508 12:44:45.378661 <6>[ 0.730373] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10509 12:44:45.385516 <6>[ 0.738078] NET: Registered PF_UNIX/PF_LOCAL protocol family
10510 12:44:45.391924 <6>[ 0.744230] RPC: Registered named UNIX socket transport module.
10511 12:44:45.395114 <6>[ 0.750383] RPC: Registered udp transport module.
10512 12:44:45.401644 <6>[ 0.755316] RPC: Registered tcp transport module.
10513 12:44:45.408519 <6>[ 0.760246] RPC: Registered tcp NFSv4.1 backchannel transport module.
10514 12:44:45.411494 <6>[ 0.766910] PCI: CLS 0 bytes, default 64
10515 12:44:45.415043 <6>[ 0.771200] Unpacking initramfs...
10516 12:44:45.431519 <6>[ 0.783198] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10517 12:44:45.441362 <6>[ 0.791848] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10518 12:44:45.445308 <6>[ 0.800691] kvm [1]: IPA Size Limit: 40 bits
10519 12:44:45.451179 <6>[ 0.805219] kvm [1]: GICv3: no GICV resource entry
10520 12:44:45.454466 <6>[ 0.810240] kvm [1]: disabling GICv2 emulation
10521 12:44:45.461519 <6>[ 0.814924] kvm [1]: GIC system register CPU interface enabled
10522 12:44:45.465115 <6>[ 0.821099] kvm [1]: vgic interrupt IRQ18
10523 12:44:45.470965 <6>[ 0.825491] kvm [1]: VHE mode initialized successfully
10524 12:44:45.477854 <5>[ 0.831955] Initialise system trusted keyrings
10525 12:44:45.484416 <6>[ 0.836800] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10526 12:44:45.491645 <6>[ 0.846797] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10527 12:44:45.498470 <5>[ 0.853188] NFS: Registering the id_resolver key type
10528 12:44:45.502034 <5>[ 0.858493] Key type id_resolver registered
10529 12:44:45.508629 <5>[ 0.862911] Key type id_legacy registered
10530 12:44:45.514952 <6>[ 0.867197] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10531 12:44:45.522122 <6>[ 0.874119] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10532 12:44:45.528282 <6>[ 0.881852] 9p: Installing v9fs 9p2000 file system support
10533 12:44:45.565350 <5>[ 0.920113] Key type asymmetric registered
10534 12:44:45.568479 <5>[ 0.924443] Asymmetric key parser 'x509' registered
10535 12:44:45.579029 <6>[ 0.929591] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10536 12:44:45.582232 <6>[ 0.937206] io scheduler mq-deadline registered
10537 12:44:45.585240 <6>[ 0.941981] io scheduler kyber registered
10538 12:44:45.604271 <6>[ 0.958791] EINJ: ACPI disabled.
10539 12:44:45.635723 <4>[ 0.983902] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10540 12:44:45.645297 <4>[ 0.994524] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10541 12:44:45.660650 <6>[ 1.015152] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10542 12:44:45.668045 <6>[ 1.023178] printk: console [ttyS0] disabled
10543 12:44:45.696359 <6>[ 1.047813] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10544 12:44:45.702808 <6>[ 1.057294] printk: console [ttyS0] enabled
10545 12:44:45.706013 <6>[ 1.057294] printk: console [ttyS0] enabled
10546 12:44:45.712665 <6>[ 1.066189] printk: bootconsole [mtk8250] disabled
10547 12:44:45.716164 <6>[ 1.066189] printk: bootconsole [mtk8250] disabled
10548 12:44:45.722688 <6>[ 1.077362] SuperH (H)SCI(F) driver initialized
10549 12:44:45.726168 <6>[ 1.082643] msm_serial: driver initialized
10550 12:44:45.740528 <6>[ 1.091520] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10551 12:44:45.750259 <6>[ 1.100066] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10552 12:44:45.756595 <6>[ 1.108609] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10553 12:44:45.766476 <6>[ 1.117237] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10554 12:44:45.777229 <6>[ 1.125943] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10555 12:44:45.782655 <6>[ 1.134657] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10556 12:44:45.792642 <6>[ 1.143196] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10557 12:44:45.799671 <6>[ 1.152001] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10558 12:44:45.809388 <6>[ 1.160544] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10559 12:44:45.821115 <6>[ 1.176063] loop: module loaded
10560 12:44:45.827702 <6>[ 1.182060] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10561 12:44:45.850504 <4>[ 1.205352] mtk-pmic-keys: Failed to locate of_node [id: -1]
10562 12:44:45.856964 <6>[ 1.211986] megasas: 07.719.03.00-rc1
10563 12:44:45.866568 <6>[ 1.221498] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10564 12:44:45.875255 <6>[ 1.230024] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10565 12:44:45.891947 <6>[ 1.246859] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10566 12:44:45.948673 <6>[ 1.297190] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10567 12:44:47.422394 <6>[ 2.777895] Freeing initrd memory: 46260K
10568 12:44:47.433281 <6>[ 2.788141] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10569 12:44:47.443932 <6>[ 2.799062] tun: Universal TUN/TAP device driver, 1.6
10570 12:44:47.446979 <6>[ 2.805105] thunder_xcv, ver 1.0
10571 12:44:47.450798 <6>[ 2.808612] thunder_bgx, ver 1.0
10572 12:44:47.453592 <6>[ 2.812106] nicpf, ver 1.0
10573 12:44:47.464380 <6>[ 2.816111] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10574 12:44:47.467734 <6>[ 2.823587] hns3: Copyright (c) 2017 Huawei Corporation.
10575 12:44:47.474443 <6>[ 2.829172] hclge is initializing
10576 12:44:47.478133 <6>[ 2.832753] e1000: Intel(R) PRO/1000 Network Driver
10577 12:44:47.484506 <6>[ 2.837883] e1000: Copyright (c) 1999-2006 Intel Corporation.
10578 12:44:47.487954 <6>[ 2.843895] e1000e: Intel(R) PRO/1000 Network Driver
10579 12:44:47.494365 <6>[ 2.849111] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10580 12:44:47.501459 <6>[ 2.855294] igb: Intel(R) Gigabit Ethernet Network Driver
10581 12:44:47.507368 <6>[ 2.860945] igb: Copyright (c) 2007-2014 Intel Corporation.
10582 12:44:47.515150 <6>[ 2.866783] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10583 12:44:47.520676 <6>[ 2.873301] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10584 12:44:47.523786 <6>[ 2.879762] sky2: driver version 1.30
10585 12:44:47.530440 <6>[ 2.884735] VFIO - User Level meta-driver version: 0.3
10586 12:44:47.538027 <6>[ 2.892933] usbcore: registered new interface driver usb-storage
10587 12:44:47.544357 <6>[ 2.899377] usbcore: registered new device driver onboard-usb-hub
10588 12:44:47.553751 <6>[ 2.908475] mt6397-rtc mt6359-rtc: registered as rtc0
10589 12:44:47.562955 <6>[ 2.913943] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-14T12:44:48 UTC (1686746688)
10590 12:44:47.566478 <6>[ 2.923497] i2c_dev: i2c /dev entries driver
10591 12:44:47.583066 <6>[ 2.935164] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10592 12:44:47.590223 <6>[ 2.945335] sdhci: Secure Digital Host Controller Interface driver
10593 12:44:47.596694 <6>[ 2.951773] sdhci: Copyright(c) Pierre Ossman
10594 12:44:47.603285 <6>[ 2.957157] Synopsys Designware Multimedia Card Interface Driver
10595 12:44:47.607259 <6>[ 2.963777] mmc0: CQHCI version 5.10
10596 12:44:47.613257 <6>[ 2.964298] sdhci-pltfm: SDHCI platform and OF driver helper
10597 12:44:47.620639 <6>[ 2.975629] ledtrig-cpu: registered to indicate activity on CPUs
10598 12:44:47.631663 <6>[ 2.982974] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10599 12:44:47.634609 <6>[ 2.990365] usbcore: registered new interface driver usbhid
10600 12:44:47.641346 <6>[ 2.996200] usbhid: USB HID core driver
10601 12:44:47.647415 <6>[ 3.000452] spi_master spi0: will run message pump with realtime priority
10602 12:44:47.693399 <6>[ 3.041879] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10603 12:44:47.712325 <6>[ 3.057276] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10604 12:44:47.715858 <6>[ 3.070861] mmc0: Command Queue Engine enabled
10605 12:44:47.722703 <6>[ 3.072469] cros-ec-spi spi0.0: Chrome EC device registered
10606 12:44:47.729521 <6>[ 3.075619] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10607 12:44:47.732597 <6>[ 3.088673] mmcblk0: mmc0:0001 DA4128 116 GiB
10608 12:44:47.747406 <6>[ 3.098335] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10609 12:44:47.753085 <6>[ 3.101364] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10610 12:44:47.759644 <6>[ 3.109787] NET: Registered PF_PACKET protocol family
10611 12:44:47.763014 <6>[ 3.114734] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10612 12:44:47.769629 <6>[ 3.119000] 9pnet: Installing 9P2000 support
10613 12:44:47.773555 <6>[ 3.124766] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10614 12:44:47.779351 <5>[ 3.128665] Key type dns_resolver registered
10615 12:44:47.786334 <6>[ 3.134551] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10616 12:44:47.789486 <6>[ 3.138888] registered taskstats version 1
10617 12:44:47.793191 <5>[ 3.149263] Loading compiled-in X.509 certificates
10618 12:44:47.828800 <4>[ 3.176993] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10619 12:44:47.838773 <4>[ 3.187686] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10620 12:44:47.849260 <3>[ 3.200783] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10621 12:44:47.861731 <6>[ 3.216364] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10622 12:44:47.867869 <6>[ 3.223178] xhci-mtk 11200000.usb: xHCI Host Controller
10623 12:44:47.874401 <6>[ 3.228682] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10624 12:44:47.884589 <6>[ 3.236528] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10625 12:44:47.891852 <6>[ 3.245954] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10626 12:44:47.898068 <6>[ 3.252039] xhci-mtk 11200000.usb: xHCI Host Controller
10627 12:44:47.904941 <6>[ 3.257521] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10628 12:44:47.911302 <6>[ 3.265174] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10629 12:44:47.917903 <6>[ 3.272870] hub 1-0:1.0: USB hub found
10630 12:44:47.921518 <6>[ 3.276894] hub 1-0:1.0: 1 port detected
10631 12:44:47.927883 <6>[ 3.281233] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10632 12:44:47.934990 <6>[ 3.289942] hub 2-0:1.0: USB hub found
10633 12:44:47.938177 <6>[ 3.293974] hub 2-0:1.0: 1 port detected
10634 12:44:47.946291 <6>[ 3.301238] mtk-msdc 11f70000.mmc: Got CD GPIO
10635 12:44:47.963548 <6>[ 3.315437] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10636 12:44:47.970029 <6>[ 3.323460] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10637 12:44:47.980166 <4>[ 3.331446] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10638 12:44:47.990109 <6>[ 3.341103] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10639 12:44:47.997146 <6>[ 3.349188] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10640 12:44:48.003493 <6>[ 3.357190] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10641 12:44:48.013556 <6>[ 3.365110] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10642 12:44:48.019644 <6>[ 3.372932] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10643 12:44:48.029595 <6>[ 3.380754] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10644 12:44:48.039452 <6>[ 3.391327] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10645 12:44:48.046540 <6>[ 3.399705] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10646 12:44:48.056168 <6>[ 3.408055] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10647 12:44:48.065925 <6>[ 3.416398] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10648 12:44:48.072732 <6>[ 3.424741] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10649 12:44:48.082873 <6>[ 3.433085] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10650 12:44:48.089258 <6>[ 3.441428] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10651 12:44:48.099138 <6>[ 3.449771] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10652 12:44:48.105868 <6>[ 3.458114] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10653 12:44:48.116128 <6>[ 3.466458] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10654 12:44:48.122247 <6>[ 3.474802] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10655 12:44:48.132566 <6>[ 3.483147] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10656 12:44:48.139007 <6>[ 3.491495] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10657 12:44:48.149252 <6>[ 3.499840] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10658 12:44:48.155546 <6>[ 3.508187] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10659 12:44:48.162180 <6>[ 3.517107] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10660 12:44:48.169587 <6>[ 3.524549] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10661 12:44:48.176561 <6>[ 3.531643] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10662 12:44:48.186771 <6>[ 3.538805] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10663 12:44:48.193900 <6>[ 3.546127] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10664 12:44:48.203629 <6>[ 3.553077] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10665 12:44:48.210006 <6>[ 3.562230] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10666 12:44:48.219816 <6>[ 3.571357] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10667 12:44:48.230339 <6>[ 3.580659] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10668 12:44:48.239840 <6>[ 3.590133] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10669 12:44:48.250002 <6>[ 3.599608] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10670 12:44:48.260231 <6>[ 3.608737] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10671 12:44:48.266180 <6>[ 3.618212] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10672 12:44:48.276182 <6>[ 3.627340] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10673 12:44:48.286250 <6>[ 3.636643] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10674 12:44:48.296389 <6>[ 3.646809] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10675 12:44:48.306173 <6>[ 3.658244] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10676 12:44:48.327552 <6>[ 3.679059] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10677 12:44:48.355943 <6>[ 3.711093] hub 2-1:1.0: USB hub found
10678 12:44:48.359040 <6>[ 3.715574] hub 2-1:1.0: 3 ports detected
10679 12:44:48.479668 <6>[ 3.830876] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10680 12:44:48.632020 <6>[ 3.987239] hub 1-1:1.0: USB hub found
10681 12:44:48.635264 <6>[ 3.991590] hub 1-1:1.0: 4 ports detected
10682 12:44:48.712554 <6>[ 4.063153] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10683 12:44:48.955422 <6>[ 4.306902] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10684 12:44:49.087872 <6>[ 4.443197] hub 1-1.4:1.0: USB hub found
10685 12:44:49.091323 <6>[ 4.447859] hub 1-1.4:1.0: 2 ports detected
10686 12:44:49.386788 <6>[ 4.738902] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10687 12:44:49.578546 <6>[ 4.930932] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10688 12:45:00.587939 <6>[ 15.947457] ALSA device list:
10689 12:45:00.594630 <6>[ 15.950714] No soundcards found.
10690 12:45:00.607142 <6>[ 15.963118] Freeing unused kernel memory: 8384K
10691 12:45:00.610460 <6>[ 15.968037] Run /init as init process
10692 12:45:00.640952 <6>[ 15.996972] NET: Registered PF_INET6 protocol family
10693 12:45:00.647394 <6>[ 16.003484] Segment Routing with IPv6
10694 12:45:00.650621 <6>[ 16.007481] In-situ OAM (IOAM) with IPv6
10695 12:45:00.685836 <30>[ 16.022306] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10696 12:45:00.689245 <30>[ 16.046296] systemd[1]: Detected architecture arm64.
10697 12:45:00.692643
10698 12:45:00.695635 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10699 12:45:00.696096
10700 12:45:00.711352 <30>[ 16.067089] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10701 12:45:00.842573 <30>[ 16.195081] systemd[1]: Queued start job for default target Graphical Interface.
10702 12:45:00.883989 <30>[ 16.240306] systemd[1]: Created slice system-getty.slice.
10703 12:45:00.890904 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10704 12:45:00.907576 <30>[ 16.263500] systemd[1]: Created slice system-modprobe.slice.
10705 12:45:00.913611 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10706 12:45:00.931805 <30>[ 16.288020] systemd[1]: Created slice system-serial\x2dgetty.slice.
10707 12:45:00.941852 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10708 12:45:00.955428 <30>[ 16.311375] systemd[1]: Created slice User and Session Slice.
10709 12:45:00.961949 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10710 12:45:00.983058 <30>[ 16.335473] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10711 12:45:00.992632 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10712 12:45:01.010530 <30>[ 16.363033] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10713 12:45:01.016645 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10714 12:45:01.037184 <30>[ 16.386950] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10715 12:45:01.043886 <30>[ 16.398984] systemd[1]: Reached target Local Encrypted Volumes.
10716 12:45:01.050590 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10717 12:45:01.067747 <30>[ 16.423288] systemd[1]: Reached target Paths.
10718 12:45:01.070830 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10719 12:45:01.087327 <30>[ 16.442947] systemd[1]: Reached target Remote File Systems.
10720 12:45:01.093646 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10721 12:45:01.107001 <30>[ 16.462880] systemd[1]: Reached target Slices.
10722 12:45:01.110645 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10723 12:45:01.127089 <30>[ 16.482956] systemd[1]: Reached target Swap.
10724 12:45:01.130340 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10725 12:45:01.150292 <30>[ 16.503182] systemd[1]: Listening on initctl Compatibility Named Pipe.
10726 12:45:01.156567 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10727 12:45:01.163523 <30>[ 16.517890] systemd[1]: Listening on Journal Audit Socket.
10728 12:45:01.170233 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10729 12:45:01.183803 <30>[ 16.539203] systemd[1]: Listening on Journal Socket (/dev/log).
10730 12:45:01.189852 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10731 12:45:01.208008 <30>[ 16.563696] systemd[1]: Listening on Journal Socket.
10732 12:45:01.213760 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10733 12:45:01.230470 <30>[ 16.583313] systemd[1]: Listening on Network Service Netlink Socket.
10734 12:45:01.236540 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10735 12:45:01.251355 <30>[ 16.607690] systemd[1]: Listening on udev Control Socket.
10736 12:45:01.258398 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10737 12:45:01.275710 <30>[ 16.631621] systemd[1]: Listening on udev Kernel Socket.
10738 12:45:01.281661 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10739 12:45:01.314849 <30>[ 16.671170] systemd[1]: Mounting Huge Pages File System...
10740 12:45:01.321746 Mounting [0;1;39mHuge Pages File System[0m...
10741 12:45:01.337451 <30>[ 16.693050] systemd[1]: Mounting POSIX Message Queue File System...
10742 12:45:01.343597 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10743 12:45:01.360651 <30>[ 16.716994] systemd[1]: Mounting Kernel Debug File System...
10744 12:45:01.367277 Mounting [0;1;39mKernel Debug File System[0m...
10745 12:45:01.386341 <30>[ 16.739215] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10746 12:45:01.397003 <30>[ 16.750219] systemd[1]: Starting Create list of static device nodes for the current kernel...
10747 12:45:01.403719 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10748 12:45:01.420971 <30>[ 16.777166] systemd[1]: Starting Load Kernel Module configfs...
10749 12:45:01.427592 Starting [0;1;39mLoad Kernel Module configfs[0m...
10750 12:45:01.444700 <30>[ 16.801230] systemd[1]: Starting Load Kernel Module drm...
10751 12:45:01.451420 Starting [0;1;39mLoad Kernel Module drm[0m...
10752 12:45:01.470191 <30>[ 16.823055] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10753 12:45:01.480366 <30>[ 16.836784] systemd[1]: Starting Journal Service...
10754 12:45:01.483688 Starting [0;1;39mJournal Service[0m...
10755 12:45:01.501567 <30>[ 16.857624] systemd[1]: Starting Load Kernel Modules...
10756 12:45:01.507720 Starting [0;1;39mLoad Kernel Modules[0m...
10757 12:45:01.528668 <30>[ 16.881658] systemd[1]: Starting Remount Root and Kernel File Systems...
10758 12:45:01.535505 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10759 12:45:01.549160 <30>[ 16.905465] systemd[1]: Starting Coldplug All udev Devices...
10760 12:45:01.555672 Starting [0;1;39mColdplug All udev Devices[0m...
10761 12:45:01.573716 <30>[ 16.929485] systemd[1]: Mounted Huge Pages File System.
10762 12:45:01.579667 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10763 12:45:01.595431 <30>[ 16.951736] systemd[1]: Started Journal Service.
10764 12:45:01.602147 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10765 12:45:01.616420 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10766 12:45:01.631240 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10767 12:45:01.650913 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10768 12:45:01.668662 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10769 12:45:01.684150 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10770 12:45:01.700083 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10771 12:45:01.720095 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10772 12:45:01.734606 See 'systemctl status systemd-remount-fs.service' for details.
10773 12:45:01.788524 Mounting [0;1;39mKernel Configuration File System[0m...
10774 12:45:01.809399 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10775 12:45:01.826810 <46>[ 17.179694] systemd-journald[176]: Received client request to flush runtime journal.
10776 12:45:01.835443 Starting [0;1;39mLoad/Save Random Seed[0m...
10777 12:45:01.858043 Starting [0;1;39mApply Kernel Variables[0m...
10778 12:45:01.877363 Starting [0;1;39mCreate System Users[0m...
10779 12:45:01.899286 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10780 12:45:01.918964 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10781 12:45:01.932415 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10782 12:45:01.947882 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10783 12:45:01.968281 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10784 12:45:01.987710 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10785 12:45:02.039462 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10786 12:45:02.061544 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10787 12:45:02.074730 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10788 12:45:02.090758 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10789 12:45:02.147002 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10790 12:45:02.171179 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10791 12:45:02.191498 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10792 12:45:02.210823 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10793 12:45:02.256138 Starting [0;1;39mNetwork Service[0m...
10794 12:45:02.282215 Starting [0;1;39mNetwork Time Synchronization[0m...
10795 12:45:02.304889 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10796 12:45:02.342963 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10797 12:45:02.360633 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10798 12:45:02.397691 <6>[ 17.750655] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10799 12:45:02.407913 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbac<6>[ 17.763798] remoteproc remoteproc0: scp is available
10800 12:45:02.420660 klight.slice[0m<4>[ 17.770233] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10801 12:45:02.421197 .
10802 12:45:02.424364 <6>[ 17.780938] remoteproc remoteproc0: powering up scp
10803 12:45:02.433685 <4>[ 17.786362] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10804 12:45:02.440518 <3>[ 17.796188] remoteproc remoteproc0: request_firmware failed: -2
10805 12:45:02.451585 <6>[ 17.804654] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10806 12:45:02.461710 <6>[ 17.812682] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10807 12:45:02.468639 <6>[ 17.821416] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10808 12:45:02.482968 <4>[ 17.835038] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10809 12:45:02.492634 Starting [0;1;39mLoad/<3>[ 17.844890] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10810 12:45:02.502291 Save Screen …o<3>[ 17.853676] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10811 12:45:02.512291 f leds:white:kbd<3>[ 17.863079] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10812 12:45:02.512827 _backlight[0m...
10813 12:45:02.521721 <4>[ 17.874222] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10814 12:45:02.528232 <6>[ 17.874653] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10815 12:45:02.539412 <3>[ 17.892460] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10816 12:45:02.546014 <3>[ 17.900646] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10817 12:45:02.555760 <3>[ 17.908755] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10818 12:45:02.562523 <3>[ 17.916926] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10819 12:45:02.569144 <6>[ 17.922762] mc: Linux media interface: v0.10
10820 12:45:02.575812 <3>[ 17.925127] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10821 12:45:02.582682 Starting [0;1;39mNetwork Name Resolution[0m...
10822 12:45:02.589240 <4>[ 17.942011] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10823 12:45:02.595998 <4>[ 17.942011] Fallback method does not support PEC.
10824 12:45:02.605443 <3>[ 17.958121] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10825 12:45:02.613333 <3>[ 17.967128] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10826 12:45:02.623471 <3>[ 17.974360] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10827 12:45:02.629761 <3>[ 17.975262] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10828 12:45:02.636337 <6>[ 17.978827] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10829 12:45:02.642940 <6>[ 17.978841] pci_bus 0000:00: root bus resource [bus 00-ff]
10830 12:45:02.649266 <6>[ 17.978852] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10831 12:45:02.660090 <6>[ 17.978859] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10832 12:45:02.666761 <6>[ 17.978908] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10833 12:45:02.673799 <6>[ 17.978931] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10834 12:45:02.680410 <6>[ 17.979024] pci 0000:00:00.0: supports D1 D2
10835 12:45:02.687089 <6>[ 17.979029] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10836 12:45:02.690145 <6>[ 17.990533] usbcore: registered new interface driver r8152
10837 12:45:02.704069 <6>[ 17.991165] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10838 12:45:02.710968 <3>[ 17.992118] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10839 12:45:02.720938 <6>[ 18.003014] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10840 12:45:02.727313 <3>[ 18.005152] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10841 12:45:02.737041 <6>[ 18.012274] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10842 12:45:02.743515 <3>[ 18.021815] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10843 12:45:02.754092 <3>[ 18.026431] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10844 12:45:02.759904 <3>[ 18.027262] power_supply sbs-5-000b: driver failed to report `status' property: -6
10845 12:45:02.770146 <6>[ 18.033690] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10846 12:45:02.776611 <3>[ 18.035613] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10847 12:45:02.783171 <6>[ 18.043717] videodev: Linux video capture interface: v2.00
10848 12:45:02.789924 <3>[ 18.047247] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10849 12:45:02.796322 <6>[ 18.054205] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10850 12:45:02.806384 <3>[ 18.062923] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10851 12:45:02.812948 <6>[ 18.071462] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10852 12:45:02.819321 <3>[ 18.072025] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10853 12:45:02.830228 <6>[ 18.080667] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10854 12:45:02.836305 <3>[ 18.090138] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10855 12:45:02.846341 <6>[ 18.097553] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10856 12:45:02.852518 <6>[ 18.097574] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10857 12:45:02.859621 <6>[ 18.118128] usbcore: registered new interface driver cdc_ether
10858 12:45:02.863063 <6>[ 18.122542] pci 0000:01:00.0: supports D1 D2
10859 12:45:02.873277 <4>[ 18.148679] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10860 12:45:02.879539 <6>[ 18.152424] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10861 12:45:02.882817 <6>[ 18.167439] Bluetooth: Core ver 2.22
10862 12:45:02.889958 <4>[ 18.174958] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10863 12:45:02.896217 <6>[ 18.190705] NET: Registered PF_BLUETOOTH protocol family
10864 12:45:02.902980 <6>[ 18.200379] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10865 12:45:02.909317 <6>[ 18.206124] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10866 12:45:02.916381 <6>[ 18.206386] Bluetooth: HCI device and connection manager initialized
10867 12:45:02.923305 <6>[ 18.206415] Bluetooth: HCI socket layer initialized
10868 12:45:02.929369 <6>[ 18.206477] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10869 12:45:02.940099 <6>[ 18.206488] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10870 12:45:02.946048 <6>[ 18.206510] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10871 12:45:02.952785 <6>[ 18.206527] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10872 12:45:02.962909 <6>[ 18.206543] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10873 12:45:02.966033 <6>[ 18.206572] pci 0000:00:00.0: PCI bridge to [bus 01]
10874 12:45:02.975579 <6>[ 18.206580] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10875 12:45:02.985622 <3>[ 18.220010] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10876 12:45:02.988650 <6>[ 18.222463] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10877 12:45:02.995366 <6>[ 18.224497] Bluetooth: L2CAP socket layer initialized
10878 12:45:03.002137 <6>[ 18.224564] Bluetooth: SCO socket layer initialized
10879 12:45:03.005062 <6>[ 18.229819] usbcore: registered new interface driver r8153_ecm
10880 12:45:03.018501 <6>[ 18.241373] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10881 12:45:03.025357 <6>[ 18.260201] r8152 2-1.3:1.0 eth0: v1.12.13
10882 12:45:03.028643 <6>[ 18.271701] usbcore: registered new interface driver uvcvideo
10883 12:45:03.038507 <3>[ 18.281451] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10884 12:45:03.044877 <6>[ 18.282952] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10885 12:45:03.051591 <6>[ 18.283107] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10886 12:45:03.057999 <6>[ 18.283405] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10887 12:45:03.064571 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10888 12:45:03.081500 <3>[ 18.434801] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10889 12:45:03.087932 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10890 12:45:03.103730 <6>[ 18.460679] remoteproc remoteproc0: powering up scp
10891 12:45:03.113712 <4>[ 18.466331] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10892 12:45:03.120583 <6>[ 18.473262] usbcore: registered new interface driver btusb
10893 12:45:03.127448 [[0;32m OK [<3>[ 18.476556] remoteproc remoteproc0: request_firmware failed: -2
10894 12:45:03.134090 0m] Finished [0<6>[ 18.479698] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10895 12:45:03.146971 ;1;39mLoad/Save <4>[ 18.482122] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10896 12:45:03.153836 <3>[ 18.489791] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10897 12:45:03.161358 Screen …s of l<3>[ 18.497130] Bluetooth: hci0: Failed to load firmware file (-2)
10898 12:45:03.171241 eds:white:kbd_ba<3>[ 18.521471] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10899 12:45:03.174777 cklight[0m.
10900 12:45:03.181972 <3>[ 18.522263] power_supply sbs-5-000b: driver failed to report `health' property: -6
10901 12:45:03.188324 <3>[ 18.524059] Bluetooth: hci0: Failed to set up firmware (-2)
10902 12:45:03.194732 <3>[ 18.545757] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10903 12:45:03.208152 <4>[ 18.549094] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10904 12:45:03.215659 <5>[ 18.562098] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10905 12:45:03.218620 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10906 12:45:03.236813 <5>[ 18.589216] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10907 12:45:03.243142 <4>[ 18.596209] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10908 12:45:03.249438 <6>[ 18.605191] cfg80211: failed to load regulatory.db
10909 12:45:03.296693 <6>[ 18.649101] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10910 12:45:03.302796 <6>[ 18.656610] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10911 12:45:03.326595 <6>[ 18.683323] mt7921e 0000:01:00.0: ASIC revision: 79610010
10912 12:45:03.398262 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10913 12:45:03.419564 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10914 12:45:03.434082 <4>[ 18.783503] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10915 12:45:03.440013 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10916 12:45:03.459326 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10917 12:45:03.478151 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10918 12:45:03.490689 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10919 12:45:03.506755 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10920 12:45:03.526137 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10921 12:45:03.540274 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10922 12:45:03.555956 <4>[ 18.905734] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10923 12:45:03.565870 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10924 12:45:03.578884 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10925 12:45:03.594425 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10926 12:45:03.614049 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10927 12:45:03.651191 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10928 12:45:03.677137 <4>[ 19.027119] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10929 12:45:03.687749 Starting [0;1;39mUser Login Management[0m...
10930 12:45:03.705722 Starting [0;1;39mPermit User Sessions[0m...
10931 12:45:03.723957 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10932 12:45:03.739012 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10933 12:45:03.755795 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10934 12:45:03.777560 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10935 12:45:03.800552 <4>[ 19.150405] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10936 12:45:03.859791 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10937 12:45:03.879009 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10938 12:45:03.896315 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10939 12:45:03.919995 <4>[ 19.269558] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10940 12:45:03.929282 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10941 12:45:03.946704 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10942 12:45:03.998865 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10943 12:45:04.023825 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10944 12:45:04.040116 <4>[ 19.389971] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10945 12:45:04.067319
10946 12:45:04.067858
10947 12:45:04.070635 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10948 12:45:04.071218
10949 12:45:04.074186 debian-bullseye-arm64 login: root (automatic login)
10950 12:45:04.074717
10951 12:45:04.075059
10952 12:45:04.089738 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Wed Jun 14 12:30:40 UTC 2023 aarch64
10953 12:45:04.090251
10954 12:45:04.097460 The programs included with the Debian GNU/Linux system are free software;
10955 12:45:04.103007 the exact distribution terms for each program are described in the
10956 12:45:04.106352 individual files in /usr/share/doc/*/copyright.
10957 12:45:04.106875
10958 12:45:04.113385 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10959 12:45:04.116171 permitted by applicable law.
10960 12:45:04.118005 Matched prompt #10: / #
10962 12:45:04.119417 Setting prompt string to ['/ #']
10963 12:45:04.119856 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10965 12:45:04.120888 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10966 12:45:04.121323 start: 2.2.6 expect-shell-connection (timeout 00:02:56) [common]
10967 12:45:04.121681 Setting prompt string to ['/ #']
10968 12:45:04.121994 Forcing a shell prompt, looking for ['/ #']
10970 12:45:04.172801 / #
10971 12:45:04.173445 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10972 12:45:04.173894 Waiting using forced prompt support (timeout 00:02:30)
10973 12:45:04.174376 <4>[ 19.509586] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10974 12:45:04.179416
10975 12:45:04.180187 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10976 12:45:04.180656 start: 2.2.7 export-device-env (timeout 00:02:55) [common]
10977 12:45:04.181117 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10978 12:45:04.181552 end: 2.2 depthcharge-retry (duration 00:02:05) [common]
10979 12:45:04.181956 end: 2 depthcharge-action (duration 00:02:05) [common]
10980 12:45:04.182384 start: 3 lava-test-retry (timeout 00:05:00) [common]
10981 12:45:04.182816 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
10982 12:45:04.183172 Using namespace: common
10984 12:45:04.284219 / # #
10985 12:45:04.284802 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
10986 12:45:04.285381 #<4>[ 19.629245] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10987 12:45:04.290789
10988 12:45:04.332733 Using /lava-10724871
10990 12:45:04.433925 / # export SHELL=/bin/sh
10991 12:45:04.434651 <4>[ 19.749335] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10992 12:45:04.439799 export SHELL=/bin/sh
10994 12:45:04.541285 / # . /lava-10724871/environment
10995 12:45:04.541962 . /lava-10724871/environment<4>[ 19.869247] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10996 12:45:04.547047
10998 12:45:04.648495 / # /lava-10724871/bin/lava-test-runner /lava-10724871/0
10999 12:45:04.649042 Test shell timeout: 10s (minimum of the action and connection timeout)
11000 12:45:04.650598 /lava-10724871/bin/lava-test-runner /lava-10724871/0<3>[ 19.986767] mt7921e 0000:01:00.0: hardware init failed
11001 12:45:04.650988 <6>[ 19.995797] IPv6: ADDRCONF(NETDEV_CHANGE): enx002432307c7b: link becomes ready
11002 12:45:04.651325 <6>[ 20.003929] r8152 2-1.3:1.0 enx002432307c7b: carrier on
11003 12:45:04.654025
11004 12:45:04.696457 + export TESTRUN_ID=0_cros-ec
11005 12:45:04.696898 + c<8>[ 20.035169] <LAVA_SIGNAL_STARTRUN 0_cros-ec 10724871_1.5.2.3.1>
11006 12:45:04.697242 d /lava-10724871/0/tests/0_cros-ec
11007 12:45:04.697835 Received signal: <STARTRUN> 0_cros-ec 10724871_1.5.2.3.1
11008 12:45:04.698189 Starting test lava.0_cros-ec (10724871_1.5.2.3.1)
11009 12:45:04.698581 Skipping test definition patterns.
11010 12:45:04.699116 + cat uuid
11011 12:45:04.699446 + UUID=10724871_1.5.2.3.1
11012 12:45:04.699746 + set +x
11013 12:45:04.700071 + python3 -m cros.runners.lava_runner -v
11014 12:45:05.395672 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
11015 12:45:05.401813 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11016 12:45:05.405275
11017 12:45:05.411463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11018 12:45:05.412151 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11020 12:45:05.418021 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
11021 12:45:05.424841 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11022 12:45:05.428112
11023 12:45:05.434686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip>
11024 12:45:05.435358 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip
11026 12:45:05.441183 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
11027 12:45:05.447766 Checks t<8>[ 20.801645] <LAVA_SIGNAL_ENDRUN 0_cros-ec 10724871_1.5.2.3.1>
11028 12:45:05.448581 Received signal: <ENDRUN> 0_cros-ec 10724871_1.5.2.3.1
11029 12:45:05.449015 Ending use of test pattern.
11030 12:45:05.449339 Ending test lava.0_cros-ec (10724871_1.5.2.3.1), duration 0.75
11032 12:45:05.451039 he cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11033 12:45:05.451561
11034 12:45:05.457551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11035 12:45:05.458215 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11037 12:45:05.464066 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11038 12:45:05.471374 Checks the standard ABI for the main Embedded Controller. ... ok
11039 12:45:05.471817
11040 12:45:05.474317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11041 12:45:05.474990 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11043 12:45:05.481308 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
11044 12:45:05.488279 Checks the main Embedded controller character device. ... ok
11045 12:45:05.488703
11046 12:45:05.490606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11047 12:45:05.491278 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11049 12:45:05.497593 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11050 12:45:05.504111 Checks basic comunication with the main Embedded controller. ... ok
11051 12:45:05.504556
11052 12:45:05.510682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11053 12:45:05.511350 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11055 12:45:05.513977 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11056 12:45:05.524281 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11057 12:45:05.524702
11058 12:45:05.527144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11059 12:45:05.527809 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11061 12:45:05.534170 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11062 12:45:05.540289 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11063 12:45:05.540713
11064 12:45:05.546762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11065 12:45:05.547488 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11067 12:45:05.553708 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
11068 12:45:05.560634 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11069 12:45:05.561057
11070 12:45:05.566542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11071 12:45:05.567236 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11073 12:45:05.570020 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11074 12:45:05.580508 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11075 12:45:05.580949
11076 12:45:05.582927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11077 12:45:05.583588 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11079 12:45:05.589846 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11080 12:45:05.599783 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11081 12:45:05.600240
11082 12:45:05.602983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11083 12:45:05.603647 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11085 12:45:05.609861 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11086 12:45:05.616124 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11087 12:45:05.616539
11088 12:45:05.622565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11089 12:45:05.623220 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11091 12:45:05.629565 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11092 12:45:05.636286 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11093 12:45:05.636742
11094 12:45:05.642383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11095 12:45:05.643042 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11097 12:45:05.649645 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
11098 12:45:05.655559 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11099 12:45:05.655970
11100 12:45:05.662208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11101 12:45:05.662866 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11103 12:45:05.669142 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
11104 12:45:05.676062 Check the cros battery ABI. ... skipped 'No BAT found'
11105 12:45:05.676475
11106 12:45:05.682512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11107 12:45:05.683174 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11109 12:45:05.688989 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
11110 12:45:05.695482 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11111 12:45:05.695899
11112 12:45:05.701995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11113 12:45:05.702649 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11115 12:45:05.705127 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
11116 12:45:05.712213 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11117 12:45:05.715403
11118 12:45:05.718678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11119 12:45:05.719404 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11121 12:45:05.724875 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
11122 12:45:05.731727 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11123 12:45:05.732172
11124 12:45:05.738950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11125 12:45:05.739367
11126 12:45:05.739992 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11128 12:45:05.745261 ----------------------------------------------------------------------
11129 12:45:05.748219 Ran 18 tests in 0.010s
11130 12:45:05.748635
11131 12:45:05.748963 OK (skipped=15)
11132 12:45:05.751373 + set +x
11133 12:45:05.751791 <LAVA_TEST_RUNNER EXIT>
11134 12:45:05.752417 ok: lava_test_shell seems to have completed
11135 12:45:05.753272 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_accel_iio_data_is_valid: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11136 12:45:05.753703 end: 3.1 lava-test-shell (duration 00:00:02) [common]
11137 12:45:05.754226 end: 3 lava-test-retry (duration 00:00:02) [common]
11138 12:45:05.754724 start: 4 finalize (timeout 00:07:33) [common]
11139 12:45:05.755175 start: 4.1 power-off (timeout 00:00:30) [common]
11140 12:45:05.755912 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11141 12:45:05.872130 >> Command sent successfully.
11142 12:45:05.876734 Returned 0 in 0 seconds
11143 12:45:05.977654 end: 4.1 power-off (duration 00:00:00) [common]
11145 12:45:05.979044 start: 4.2 read-feedback (timeout 00:07:33) [common]
11146 12:45:05.980278 Listened to connection for namespace 'common' for up to 1s
11147 12:45:06.980289 Finalising connection for namespace 'common'
11148 12:45:06.980939 Disconnecting from shell: Finalise
11149 12:45:06.981365 / #
11150 12:45:07.082360 end: 4.2 read-feedback (duration 00:00:01) [common]
11151 12:45:07.083049 end: 4 finalize (duration 00:00:01) [common]
11152 12:45:07.083756 Cleaning after the job
11153 12:45:07.084344 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724871/tftp-deploy-y2kwtekg/ramdisk
11154 12:45:07.107403 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724871/tftp-deploy-y2kwtekg/kernel
11155 12:45:07.121405 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724871/tftp-deploy-y2kwtekg/dtb
11156 12:45:07.121711 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724871/tftp-deploy-y2kwtekg/modules
11157 12:45:07.130179 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10724871
11158 12:45:07.232378 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10724871
11159 12:45:07.232539 Job finished correctly