Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 31
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 23
- Errors: 0
1 12:39:11.383476 lava-dispatcher, installed at version: 2023.05.1
2 12:39:11.383685 start: 0 validate
3 12:39:11.383815 Start time: 2023-06-14 12:39:11.383808+00:00 (UTC)
4 12:39:11.383942 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:39:11.384079 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230609.0%2Farm64%2Frootfs.cpio.gz exists
6 12:39:11.646520 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:39:11.647353 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:39:49.928700 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:39:49.929455 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:39:50.201675 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:39:50.202607 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:39:53.467354 validate duration: 42.08
14 12:39:53.467613 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:39:53.467709 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:39:53.467791 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:39:53.467917 Not decompressing ramdisk as can be used compressed.
18 12:39:53.467998 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230609.0/arm64/rootfs.cpio.gz
19 12:39:53.468061 saving as /var/lib/lava/dispatcher/tmp/10724838/tftp-deploy-mckrragc/ramdisk/rootfs.cpio.gz
20 12:39:53.468120 total size: 43386660 (41MB)
21 12:39:53.727050 progress 0% (0MB)
22 12:39:53.738129 progress 5% (2MB)
23 12:39:53.748980 progress 10% (4MB)
24 12:39:53.759987 progress 15% (6MB)
25 12:39:53.770888 progress 20% (8MB)
26 12:39:53.781863 progress 25% (10MB)
27 12:39:53.792848 progress 30% (12MB)
28 12:39:53.803926 progress 35% (14MB)
29 12:39:53.814983 progress 40% (16MB)
30 12:39:53.826008 progress 45% (18MB)
31 12:39:53.837132 progress 50% (20MB)
32 12:39:53.847945 progress 55% (22MB)
33 12:39:53.858841 progress 60% (24MB)
34 12:39:53.869757 progress 65% (26MB)
35 12:39:53.880622 progress 70% (28MB)
36 12:39:53.891559 progress 75% (31MB)
37 12:39:53.902412 progress 80% (33MB)
38 12:39:53.913253 progress 85% (35MB)
39 12:39:53.924194 progress 90% (37MB)
40 12:39:53.935280 progress 95% (39MB)
41 12:39:53.946261 progress 100% (41MB)
42 12:39:53.946404 41MB downloaded in 0.48s (86.51MB/s)
43 12:39:53.946556 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:39:53.946793 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:39:53.946920 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:39:53.947005 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:39:53.947124 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:39:53.947195 saving as /var/lib/lava/dispatcher/tmp/10724838/tftp-deploy-mckrragc/kernel/Image
50 12:39:53.947304 total size: 47581696 (45MB)
51 12:39:53.947379 No compression specified
52 12:39:53.948435 progress 0% (0MB)
53 12:39:53.960285 progress 5% (2MB)
54 12:39:53.972279 progress 10% (4MB)
55 12:39:53.984057 progress 15% (6MB)
56 12:39:53.995993 progress 20% (9MB)
57 12:39:54.007823 progress 25% (11MB)
58 12:39:54.019789 progress 30% (13MB)
59 12:39:54.031885 progress 35% (15MB)
60 12:39:54.043849 progress 40% (18MB)
61 12:39:54.055889 progress 45% (20MB)
62 12:39:54.067905 progress 50% (22MB)
63 12:39:54.079694 progress 55% (24MB)
64 12:39:54.091583 progress 60% (27MB)
65 12:39:54.103206 progress 65% (29MB)
66 12:39:54.115012 progress 70% (31MB)
67 12:39:54.126833 progress 75% (34MB)
68 12:39:54.138627 progress 80% (36MB)
69 12:39:54.150786 progress 85% (38MB)
70 12:39:54.162714 progress 90% (40MB)
71 12:39:54.174577 progress 95% (43MB)
72 12:39:54.186347 progress 100% (45MB)
73 12:39:54.186501 45MB downloaded in 0.24s (189.71MB/s)
74 12:39:54.186650 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:39:54.186929 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:39:54.187017 start: 1.3 download-retry (timeout 00:09:59) [common]
78 12:39:54.187104 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 12:39:54.187230 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:39:54.187303 saving as /var/lib/lava/dispatcher/tmp/10724838/tftp-deploy-mckrragc/dtb/mt8192-asurada-spherion-r0.dtb
81 12:39:54.187365 total size: 46924 (0MB)
82 12:39:54.187424 No compression specified
83 12:39:54.188545 progress 69% (0MB)
84 12:39:54.188851 progress 100% (0MB)
85 12:39:54.189020 0MB downloaded in 0.00s (27.07MB/s)
86 12:39:54.189159 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:39:54.189394 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:39:54.189479 start: 1.4 download-retry (timeout 00:09:59) [common]
90 12:39:54.189563 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 12:39:54.189671 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:39:54.189739 saving as /var/lib/lava/dispatcher/tmp/10724838/tftp-deploy-mckrragc/modules/modules.tar
93 12:39:54.189799 total size: 8536768 (8MB)
94 12:39:54.189858 Using unxz to decompress xz
95 12:39:54.193405 progress 0% (0MB)
96 12:39:54.214075 progress 5% (0MB)
97 12:39:54.240519 progress 10% (0MB)
98 12:39:54.271609 progress 15% (1MB)
99 12:39:54.295270 progress 20% (1MB)
100 12:39:54.318574 progress 25% (2MB)
101 12:39:54.342607 progress 30% (2MB)
102 12:39:54.366235 progress 35% (2MB)
103 12:39:54.393235 progress 40% (3MB)
104 12:39:54.417710 progress 45% (3MB)
105 12:39:54.443142 progress 50% (4MB)
106 12:39:54.468153 progress 55% (4MB)
107 12:39:54.493508 progress 60% (4MB)
108 12:39:54.518384 progress 65% (5MB)
109 12:39:54.543212 progress 70% (5MB)
110 12:39:54.567565 progress 75% (6MB)
111 12:39:54.591993 progress 80% (6MB)
112 12:39:54.615747 progress 85% (6MB)
113 12:39:54.640481 progress 90% (7MB)
114 12:39:54.665501 progress 95% (7MB)
115 12:39:54.687960 progress 100% (8MB)
116 12:39:54.694486 8MB downloaded in 0.50s (16.13MB/s)
117 12:39:54.694886 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:39:54.695346 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:39:54.695483 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 12:39:54.695620 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 12:39:54.695749 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:39:54.695882 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 12:39:54.696157 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10724838/lava-overlay-v63jwade
125 12:39:54.696340 makedir: /var/lib/lava/dispatcher/tmp/10724838/lava-overlay-v63jwade/lava-10724838/bin
126 12:39:54.696492 makedir: /var/lib/lava/dispatcher/tmp/10724838/lava-overlay-v63jwade/lava-10724838/tests
127 12:39:54.696645 makedir: /var/lib/lava/dispatcher/tmp/10724838/lava-overlay-v63jwade/lava-10724838/results
128 12:39:54.696807 Creating /var/lib/lava/dispatcher/tmp/10724838/lava-overlay-v63jwade/lava-10724838/bin/lava-add-keys
129 12:39:54.697015 Creating /var/lib/lava/dispatcher/tmp/10724838/lava-overlay-v63jwade/lava-10724838/bin/lava-add-sources
130 12:39:54.697208 Creating /var/lib/lava/dispatcher/tmp/10724838/lava-overlay-v63jwade/lava-10724838/bin/lava-background-process-start
131 12:39:54.697405 Creating /var/lib/lava/dispatcher/tmp/10724838/lava-overlay-v63jwade/lava-10724838/bin/lava-background-process-stop
132 12:39:54.697591 Creating /var/lib/lava/dispatcher/tmp/10724838/lava-overlay-v63jwade/lava-10724838/bin/lava-common-functions
133 12:39:54.697779 Creating /var/lib/lava/dispatcher/tmp/10724838/lava-overlay-v63jwade/lava-10724838/bin/lava-echo-ipv4
134 12:39:54.697993 Creating /var/lib/lava/dispatcher/tmp/10724838/lava-overlay-v63jwade/lava-10724838/bin/lava-install-packages
135 12:39:54.698124 Creating /var/lib/lava/dispatcher/tmp/10724838/lava-overlay-v63jwade/lava-10724838/bin/lava-installed-packages
136 12:39:54.698245 Creating /var/lib/lava/dispatcher/tmp/10724838/lava-overlay-v63jwade/lava-10724838/bin/lava-os-build
137 12:39:54.698366 Creating /var/lib/lava/dispatcher/tmp/10724838/lava-overlay-v63jwade/lava-10724838/bin/lava-probe-channel
138 12:39:54.698487 Creating /var/lib/lava/dispatcher/tmp/10724838/lava-overlay-v63jwade/lava-10724838/bin/lava-probe-ip
139 12:39:54.698608 Creating /var/lib/lava/dispatcher/tmp/10724838/lava-overlay-v63jwade/lava-10724838/bin/lava-target-ip
140 12:39:54.698747 Creating /var/lib/lava/dispatcher/tmp/10724838/lava-overlay-v63jwade/lava-10724838/bin/lava-target-mac
141 12:39:54.698936 Creating /var/lib/lava/dispatcher/tmp/10724838/lava-overlay-v63jwade/lava-10724838/bin/lava-target-storage
142 12:39:54.699060 Creating /var/lib/lava/dispatcher/tmp/10724838/lava-overlay-v63jwade/lava-10724838/bin/lava-test-case
143 12:39:54.699212 Creating /var/lib/lava/dispatcher/tmp/10724838/lava-overlay-v63jwade/lava-10724838/bin/lava-test-event
144 12:39:54.699331 Creating /var/lib/lava/dispatcher/tmp/10724838/lava-overlay-v63jwade/lava-10724838/bin/lava-test-feedback
145 12:39:54.699456 Creating /var/lib/lava/dispatcher/tmp/10724838/lava-overlay-v63jwade/lava-10724838/bin/lava-test-raise
146 12:39:54.699576 Creating /var/lib/lava/dispatcher/tmp/10724838/lava-overlay-v63jwade/lava-10724838/bin/lava-test-reference
147 12:39:54.699695 Creating /var/lib/lava/dispatcher/tmp/10724838/lava-overlay-v63jwade/lava-10724838/bin/lava-test-runner
148 12:39:54.699813 Creating /var/lib/lava/dispatcher/tmp/10724838/lava-overlay-v63jwade/lava-10724838/bin/lava-test-set
149 12:39:54.699935 Creating /var/lib/lava/dispatcher/tmp/10724838/lava-overlay-v63jwade/lava-10724838/bin/lava-test-shell
150 12:39:54.700056 Updating /var/lib/lava/dispatcher/tmp/10724838/lava-overlay-v63jwade/lava-10724838/bin/lava-install-packages (oe)
151 12:39:54.700200 Updating /var/lib/lava/dispatcher/tmp/10724838/lava-overlay-v63jwade/lava-10724838/bin/lava-installed-packages (oe)
152 12:39:54.700320 Creating /var/lib/lava/dispatcher/tmp/10724838/lava-overlay-v63jwade/lava-10724838/environment
153 12:39:54.700421 LAVA metadata
154 12:39:54.700493 - LAVA_JOB_ID=10724838
155 12:39:54.700557 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:39:54.700663 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 12:39:54.700729 skipped lava-vland-overlay
158 12:39:54.700803 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:39:54.700880 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 12:39:54.700941 skipped lava-multinode-overlay
161 12:39:54.701013 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:39:54.701122 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 12:39:54.701244 Loading test definitions
164 12:39:54.701373 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 12:39:54.701448 Using /lava-10724838 at stage 0
166 12:39:54.701743 uuid=10724838_1.5.2.3.1 testdef=None
167 12:39:54.701830 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:39:54.701915 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 12:39:54.702424 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:39:54.702644 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 12:39:54.703312 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:39:54.703541 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 12:39:54.704184 runner path: /var/lib/lava/dispatcher/tmp/10724838/lava-overlay-v63jwade/lava-10724838/0/tests/0_igt-kms-mediatek test_uuid 10724838_1.5.2.3.1
176 12:39:54.704336 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:39:54.704545 Creating lava-test-runner.conf files
179 12:39:54.704608 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10724838/lava-overlay-v63jwade/lava-10724838/0 for stage 0
180 12:39:54.704692 - 0_igt-kms-mediatek
181 12:39:54.704785 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 12:39:54.704866 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 12:39:54.711331 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 12:39:54.711434 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 12:39:54.711518 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 12:39:54.711602 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 12:39:54.711691 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 12:39:56.034687 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 12:39:56.035090 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 12:39:56.035202 extracting modules file /var/lib/lava/dispatcher/tmp/10724838/tftp-deploy-mckrragc/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10724838/extract-overlay-ramdisk-wrsndx5g/ramdisk
191 12:39:56.238283 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 12:39:56.238452 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 12:39:56.238549 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10724838/compress-overlay-2lexy64b/overlay-1.5.2.4.tar.gz to ramdisk
194 12:39:56.238622 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10724838/compress-overlay-2lexy64b/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10724838/extract-overlay-ramdisk-wrsndx5g/ramdisk
195 12:39:56.244906 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 12:39:56.245020 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 12:39:56.245114 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 12:39:56.245203 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 12:39:56.245283 Building ramdisk /var/lib/lava/dispatcher/tmp/10724838/extract-overlay-ramdisk-wrsndx5g/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10724838/extract-overlay-ramdisk-wrsndx5g/ramdisk
200 12:39:57.187775 >> 369088 blocks
201 12:40:03.024459 rename /var/lib/lava/dispatcher/tmp/10724838/extract-overlay-ramdisk-wrsndx5g/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10724838/tftp-deploy-mckrragc/ramdisk/ramdisk.cpio.gz
202 12:40:03.024882 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 12:40:03.025003 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 12:40:03.025106 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 12:40:03.025210 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10724838/tftp-deploy-mckrragc/kernel/Image'
206 12:40:15.015824 Returned 0 in 11 seconds
207 12:40:15.116450 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10724838/tftp-deploy-mckrragc/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10724838/tftp-deploy-mckrragc/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10724838/tftp-deploy-mckrragc/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10724838/tftp-deploy-mckrragc/kernel/image.itb
208 12:40:15.870434 output: FIT description: Kernel Image image with one or more FDT blobs
209 12:40:15.870783 output: Created: Wed Jun 14 13:40:15 2023
210 12:40:15.870940 output: Image 0 (kernel-1)
211 12:40:15.871031 output: Description:
212 12:40:15.871117 output: Created: Wed Jun 14 13:40:15 2023
213 12:40:15.871201 output: Type: Kernel Image
214 12:40:15.871285 output: Compression: lzma compressed
215 12:40:15.871367 output: Data Size: 10442380 Bytes = 10197.64 KiB = 9.96 MiB
216 12:40:15.871465 output: Architecture: AArch64
217 12:40:15.871565 output: OS: Linux
218 12:40:15.871665 output: Load Address: 0x00000000
219 12:40:15.871763 output: Entry Point: 0x00000000
220 12:40:15.871860 output: Hash algo: crc32
221 12:40:15.871957 output: Hash value: ced21bfe
222 12:40:15.872052 output: Image 1 (fdt-1)
223 12:40:15.872146 output: Description: mt8192-asurada-spherion-r0
224 12:40:15.872240 output: Created: Wed Jun 14 13:40:15 2023
225 12:40:15.872334 output: Type: Flat Device Tree
226 12:40:15.872428 output: Compression: uncompressed
227 12:40:15.872521 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 12:40:15.872615 output: Architecture: AArch64
229 12:40:15.872707 output: Hash algo: crc32
230 12:40:15.872801 output: Hash value: 1df858fa
231 12:40:15.872894 output: Image 2 (ramdisk-1)
232 12:40:15.873019 output: Description: unavailable
233 12:40:15.873119 output: Created: Wed Jun 14 13:40:15 2023
234 12:40:15.873210 output: Type: RAMDisk Image
235 12:40:15.873305 output: Compression: Unknown Compression
236 12:40:15.873399 output: Data Size: 56362433 Bytes = 55041.44 KiB = 53.75 MiB
237 12:40:15.873495 output: Architecture: AArch64
238 12:40:15.873581 output: OS: Linux
239 12:40:15.873666 output: Load Address: unavailable
240 12:40:15.873751 output: Entry Point: unavailable
241 12:40:15.873834 output: Hash algo: crc32
242 12:40:15.873918 output: Hash value: 5cdd0d39
243 12:40:15.874001 output: Default Configuration: 'conf-1'
244 12:40:15.874085 output: Configuration 0 (conf-1)
245 12:40:15.874168 output: Description: mt8192-asurada-spherion-r0
246 12:40:15.874252 output: Kernel: kernel-1
247 12:40:15.874340 output: Init Ramdisk: ramdisk-1
248 12:40:15.874423 output: FDT: fdt-1
249 12:40:15.874505 output: Loadables: kernel-1
250 12:40:15.874588 output:
251 12:40:15.874821 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 12:40:15.874965 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 12:40:15.875076 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 12:40:15.875177 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 12:40:15.875256 No LXC device requested
256 12:40:15.875339 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 12:40:15.875427 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 12:40:15.875506 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 12:40:15.875577 Checking files for TFTP limit of 4294967296 bytes.
260 12:40:15.876098 end: 1 tftp-deploy (duration 00:00:22) [common]
261 12:40:15.876235 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 12:40:15.876362 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 12:40:15.876498 substitutions:
264 12:40:15.876598 - {DTB}: 10724838/tftp-deploy-mckrragc/dtb/mt8192-asurada-spherion-r0.dtb
265 12:40:15.876697 - {INITRD}: 10724838/tftp-deploy-mckrragc/ramdisk/ramdisk.cpio.gz
266 12:40:15.876775 - {KERNEL}: 10724838/tftp-deploy-mckrragc/kernel/Image
267 12:40:15.876865 - {LAVA_MAC}: None
268 12:40:15.876938 - {PRESEED_CONFIG}: None
269 12:40:15.877027 - {PRESEED_LOCAL}: None
270 12:40:15.877101 - {RAMDISK}: 10724838/tftp-deploy-mckrragc/ramdisk/ramdisk.cpio.gz
271 12:40:15.877190 - {ROOT_PART}: None
272 12:40:15.877259 - {ROOT}: None
273 12:40:15.877330 - {SERVER_IP}: 192.168.201.1
274 12:40:15.877429 - {TEE}: None
275 12:40:15.877484 Parsed boot commands:
276 12:40:15.877538 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 12:40:15.877713 Parsed boot commands: tftpboot 192.168.201.1 10724838/tftp-deploy-mckrragc/kernel/image.itb 10724838/tftp-deploy-mckrragc/kernel/cmdline
278 12:40:15.877834 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 12:40:15.877920 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 12:40:15.878018 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 12:40:15.878104 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 12:40:15.878178 Not connected, no need to disconnect.
283 12:40:15.878283 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 12:40:15.878364 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 12:40:15.878434 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-8'
286 12:40:15.882124 Setting prompt string to ['lava-test: # ']
287 12:40:15.882538 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 12:40:15.882654 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 12:40:15.882773 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 12:40:15.882899 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 12:40:15.883101 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
292 12:40:21.019860 >> Command sent successfully.
293 12:40:21.022303 Returned 0 in 5 seconds
294 12:40:21.122673 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 12:40:21.123261 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 12:40:21.123362 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 12:40:21.123456 Setting prompt string to 'Starting depthcharge on Spherion...'
299 12:40:21.123523 Changing prompt to 'Starting depthcharge on Spherion...'
300 12:40:21.123594 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 12:40:21.123853 [Enter `^Ec?' for help]
302 12:40:21.295412
303 12:40:21.295596
304 12:40:21.295669 F0: 102B 0000
305 12:40:21.295733
306 12:40:21.295836 F3: 1001 0000 [0200]
307 12:40:21.298327
308 12:40:21.298409 F3: 1001 0000
309 12:40:21.298477
310 12:40:21.298539 F7: 102D 0000
311 12:40:21.298599
312 12:40:21.301766 F1: 0000 0000
313 12:40:21.301876
314 12:40:21.301958 V0: 0000 0000 [0001]
315 12:40:21.302023
316 12:40:21.305585 00: 0007 8000
317 12:40:21.305673
318 12:40:21.305739 01: 0000 0000
319 12:40:21.305802
320 12:40:21.308476 BP: 0C00 0209 [0000]
321 12:40:21.308621
322 12:40:21.308748 G0: 1182 0000
323 12:40:21.308822
324 12:40:21.312085 EC: 0000 0021 [4000]
325 12:40:21.312170
326 12:40:21.312238 S7: 0000 0000 [0000]
327 12:40:21.312299
328 12:40:21.315655 CC: 0000 0000 [0001]
329 12:40:21.315740
330 12:40:21.315807 T0: 0000 0040 [010F]
331 12:40:21.315872
332 12:40:21.315931 Jump to BL
333 12:40:21.315989
334 12:40:21.341969
335 12:40:21.342117
336 12:40:21.342190
337 12:40:21.349005 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 12:40:21.352354 ARM64: Exception handlers installed.
339 12:40:21.355617 ARM64: Testing exception
340 12:40:21.359158 ARM64: Done test exception
341 12:40:21.365829 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 12:40:21.375839 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 12:40:21.382753 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 12:40:21.392761 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 12:40:21.399771 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 12:40:21.409830 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 12:40:21.420019 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 12:40:21.426270 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 12:40:21.445193 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 12:40:21.448192 WDT: Last reset was cold boot
351 12:40:21.451758 SPI1(PAD0) initialized at 2873684 Hz
352 12:40:21.454809 SPI5(PAD0) initialized at 992727 Hz
353 12:40:21.458250 VBOOT: Loading verstage.
354 12:40:21.464857 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 12:40:21.468306 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 12:40:21.471658 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 12:40:21.474495 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 12:40:21.482744 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 12:40:21.488872 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 12:40:21.500164 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 12:40:21.500295
362 12:40:21.500381
363 12:40:21.510184 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 12:40:21.513911 ARM64: Exception handlers installed.
365 12:40:21.516900 ARM64: Testing exception
366 12:40:21.516996 ARM64: Done test exception
367 12:40:21.523556 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 12:40:21.527201 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 12:40:21.541364 Probing TPM: . done!
370 12:40:21.541513 TPM ready after 0 ms
371 12:40:21.548509 Connected to device vid:did:rid of 1ae0:0028:00
372 12:40:21.554894 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 12:40:21.559075 Initialized TPM device CR50 revision 0
374 12:40:21.607553 tlcl_send_startup: Startup return code is 0
375 12:40:21.607698 TPM: setup succeeded
376 12:40:21.619169 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 12:40:21.627675 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 12:40:21.634968 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 12:40:21.646746 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 12:40:21.650270 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 12:40:21.653957 in-header: 03 07 00 00 08 00 00 00
382 12:40:21.657026 in-data: aa e4 47 04 13 02 00 00
383 12:40:21.660560 Chrome EC: UHEPI supported
384 12:40:21.667720 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 12:40:21.670389 in-header: 03 ad 00 00 08 00 00 00
386 12:40:21.673650 in-data: 00 20 20 08 00 00 00 00
387 12:40:21.673762 Phase 1
388 12:40:21.680548 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 12:40:21.683970 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 12:40:21.690223 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 12:40:21.693624 Recovery requested (1009000e)
392 12:40:21.697798 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 12:40:21.706315 tlcl_extend: response is 0
394 12:40:21.714636 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 12:40:21.720162 tlcl_extend: response is 0
396 12:40:21.726401 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 12:40:21.747174 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 12:40:21.754289 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 12:40:21.754450
400 12:40:21.754523
401 12:40:21.765029 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 12:40:21.768654 ARM64: Exception handlers installed.
403 12:40:21.768806 ARM64: Testing exception
404 12:40:21.771557 ARM64: Done test exception
405 12:40:21.790195 pmic_efuse_setting: Set efuses in 11 msecs
406 12:40:21.798373 pmwrap_interface_init: Select PMIF_VLD_RDY
407 12:40:21.802317 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 12:40:21.805671 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 12:40:21.813259 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 12:40:21.816501 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 12:40:21.820023 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 12:40:21.827474 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 12:40:21.831225 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 12:40:21.834773 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 12:40:21.842143 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 12:40:21.845669 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 12:40:21.849294 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 12:40:21.852782 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 12:40:21.859463 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 12:40:21.866195 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 12:40:21.869896 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 12:40:21.877062 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 12:40:21.880184 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 12:40:21.886977 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 12:40:21.894760 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 12:40:21.898158 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 12:40:21.905865 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 12:40:21.909588 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 12:40:21.916790 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 12:40:21.920226 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 12:40:21.927288 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 12:40:21.931066 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 12:40:21.938813 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 12:40:21.942592 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 12:40:21.946090 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 12:40:21.953491 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 12:40:21.957095 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 12:40:21.960647 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 12:40:21.967192 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 12:40:21.970893 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 12:40:21.975119 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 12:40:21.982283 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 12:40:21.985336 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 12:40:21.992916 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 12:40:21.996539 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 12:40:21.999947 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 12:40:22.003538 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 12:40:22.009916 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 12:40:22.013550 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 12:40:22.017256 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 12:40:22.023587 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 12:40:22.026948 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 12:40:22.030172 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 12:40:22.033570 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 12:40:22.040136 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 12:40:22.043650 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 12:40:22.046733 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 12:40:22.057033 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 12:40:22.063479 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 12:40:22.070135 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 12:40:22.076696 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 12:40:22.086309 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 12:40:22.090009 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 12:40:22.093652 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 12:40:22.097266 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 12:40:22.105693 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
467 12:40:22.112482 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 12:40:22.116865 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 12:40:22.119399 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 12:40:22.129683 [RTC]rtc_get_frequency_meter,154: input=15, output=794
471 12:40:22.133220 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 12:40:22.139724 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 12:40:22.143112 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
474 12:40:22.146427 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 12:40:22.149845 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
476 12:40:22.153428 ADC[4]: Raw value=898150 ID=7
477 12:40:22.156355 ADC[3]: Raw value=212700 ID=1
478 12:40:22.159911 RAM Code: 0x71
479 12:40:22.163073 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 12:40:22.166488 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 12:40:22.176100 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 12:40:22.182776 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 12:40:22.186445 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 12:40:22.189531 in-header: 03 07 00 00 08 00 00 00
485 12:40:22.193030 in-data: aa e4 47 04 13 02 00 00
486 12:40:22.196061 Chrome EC: UHEPI supported
487 12:40:22.202775 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 12:40:22.206185 in-header: 03 d5 00 00 08 00 00 00
489 12:40:22.209730 in-data: 98 20 60 08 00 00 00 00
490 12:40:22.212941 MRC: failed to locate region type 0.
491 12:40:22.219199 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 12:40:22.223001 DRAM-K: Running full calibration
493 12:40:22.225980 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 12:40:22.229425 header.status = 0x0
495 12:40:22.232963 header.version = 0x6 (expected: 0x6)
496 12:40:22.235842 header.size = 0xd00 (expected: 0xd00)
497 12:40:22.239439 header.flags = 0x0
498 12:40:22.242907 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 12:40:22.261809 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
500 12:40:22.267909 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 12:40:22.271808 dram_init: ddr_geometry: 2
502 12:40:22.274777 [EMI] MDL number = 2
503 12:40:22.274945 [EMI] Get MDL freq = 0
504 12:40:22.278476 dram_init: ddr_type: 0
505 12:40:22.278632 is_discrete_lpddr4: 1
506 12:40:22.281299 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 12:40:22.281457
508 12:40:22.281601
509 12:40:22.284891 [Bian_co] ETT version 0.0.0.1
510 12:40:22.291621 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 12:40:22.291792
512 12:40:22.294522 dramc_set_vcore_voltage set vcore to 650000
513 12:40:22.298055 Read voltage for 800, 4
514 12:40:22.298216 Vio18 = 0
515 12:40:22.298364 Vcore = 650000
516 12:40:22.301681 Vdram = 0
517 12:40:22.301839 Vddq = 0
518 12:40:22.301982 Vmddr = 0
519 12:40:22.304684 dram_init: config_dvfs: 1
520 12:40:22.308362 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 12:40:22.315000 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 12:40:22.317845 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
523 12:40:22.321607 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
524 12:40:22.324923 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
525 12:40:22.331022 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
526 12:40:22.331223 MEM_TYPE=3, freq_sel=18
527 12:40:22.334495 sv_algorithm_assistance_LP4_1600
528 12:40:22.337895 ============ PULL DRAM RESETB DOWN ============
529 12:40:22.344793 ========== PULL DRAM RESETB DOWN end =========
530 12:40:22.348337 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 12:40:22.351749 ===================================
532 12:40:22.351946 LPDDR4 DRAM CONFIGURATION
533 12:40:22.355061 ===================================
534 12:40:22.358179 EX_ROW_EN[0] = 0x0
535 12:40:22.361454 EX_ROW_EN[1] = 0x0
536 12:40:22.361621 LP4Y_EN = 0x0
537 12:40:22.364958 WORK_FSP = 0x0
538 12:40:22.365119 WL = 0x2
539 12:40:22.368451 RL = 0x2
540 12:40:22.368610 BL = 0x2
541 12:40:22.371327 RPST = 0x0
542 12:40:22.371483 RD_PRE = 0x0
543 12:40:22.375313 WR_PRE = 0x1
544 12:40:22.375470 WR_PST = 0x0
545 12:40:22.379026 DBI_WR = 0x0
546 12:40:22.379187 DBI_RD = 0x0
547 12:40:22.381978 OTF = 0x1
548 12:40:22.385571 ===================================
549 12:40:22.389045 ===================================
550 12:40:22.389212 ANA top config
551 12:40:22.392042 ===================================
552 12:40:22.395644 DLL_ASYNC_EN = 0
553 12:40:22.398744 ALL_SLAVE_EN = 1
554 12:40:22.398910 NEW_RANK_MODE = 1
555 12:40:22.402296 DLL_IDLE_MODE = 1
556 12:40:22.405271 LP45_APHY_COMB_EN = 1
557 12:40:22.408872 TX_ODT_DIS = 1
558 12:40:22.411879 NEW_8X_MODE = 1
559 12:40:22.415572 ===================================
560 12:40:22.419109 ===================================
561 12:40:22.419279 data_rate = 1600
562 12:40:22.421973 CKR = 1
563 12:40:22.425542 DQ_P2S_RATIO = 8
564 12:40:22.429100 ===================================
565 12:40:22.432128 CA_P2S_RATIO = 8
566 12:40:22.435532 DQ_CA_OPEN = 0
567 12:40:22.438806 DQ_SEMI_OPEN = 0
568 12:40:22.439027 CA_SEMI_OPEN = 0
569 12:40:22.441640 CA_FULL_RATE = 0
570 12:40:22.445085 DQ_CKDIV4_EN = 1
571 12:40:22.448507 CA_CKDIV4_EN = 1
572 12:40:22.451611 CA_PREDIV_EN = 0
573 12:40:22.455138 PH8_DLY = 0
574 12:40:22.455308 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 12:40:22.458655 DQ_AAMCK_DIV = 4
576 12:40:22.461500 CA_AAMCK_DIV = 4
577 12:40:22.464876 CA_ADMCK_DIV = 4
578 12:40:22.468029 DQ_TRACK_CA_EN = 0
579 12:40:22.471749 CA_PICK = 800
580 12:40:22.471930 CA_MCKIO = 800
581 12:40:22.475243 MCKIO_SEMI = 0
582 12:40:22.478238 PLL_FREQ = 3068
583 12:40:22.481782 DQ_UI_PI_RATIO = 32
584 12:40:22.485274 CA_UI_PI_RATIO = 0
585 12:40:22.488225 ===================================
586 12:40:22.491662 ===================================
587 12:40:22.495205 memory_type:LPDDR4
588 12:40:22.495371 GP_NUM : 10
589 12:40:22.498302 SRAM_EN : 1
590 12:40:22.498466 MD32_EN : 0
591 12:40:22.501278 ===================================
592 12:40:22.504979 [ANA_INIT] >>>>>>>>>>>>>>
593 12:40:22.508061 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 12:40:22.511575 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 12:40:22.514667 ===================================
596 12:40:22.518184 data_rate = 1600,PCW = 0X7600
597 12:40:22.521866 ===================================
598 12:40:22.525522 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 12:40:22.528907 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 12:40:22.536013 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 12:40:22.539571 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 12:40:22.543212 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 12:40:22.547248 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 12:40:22.551335 [ANA_INIT] flow start
605 12:40:22.551582 [ANA_INIT] PLL >>>>>>>>
606 12:40:22.554468 [ANA_INIT] PLL <<<<<<<<
607 12:40:22.554643 [ANA_INIT] MIDPI >>>>>>>>
608 12:40:22.557943 [ANA_INIT] MIDPI <<<<<<<<
609 12:40:22.561465 [ANA_INIT] DLL >>>>>>>>
610 12:40:22.561637 [ANA_INIT] flow end
611 12:40:22.568640 ============ LP4 DIFF to SE enter ============
612 12:40:22.571944 ============ LP4 DIFF to SE exit ============
613 12:40:22.572115 [ANA_INIT] <<<<<<<<<<<<<
614 12:40:22.575876 [Flow] Enable top DCM control >>>>>
615 12:40:22.579120 [Flow] Enable top DCM control <<<<<
616 12:40:22.583424 Enable DLL master slave shuffle
617 12:40:22.586767 ==============================================================
618 12:40:22.590164 Gating Mode config
619 12:40:22.594387 ==============================================================
620 12:40:22.597930 Config description:
621 12:40:22.608990 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 12:40:22.612528 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 12:40:22.619836 SELPH_MODE 0: By rank 1: By Phase
624 12:40:22.623523 ==============================================================
625 12:40:22.626496 GAT_TRACK_EN = 1
626 12:40:22.630702 RX_GATING_MODE = 2
627 12:40:22.634087 RX_GATING_TRACK_MODE = 2
628 12:40:22.637760 SELPH_MODE = 1
629 12:40:22.637965 PICG_EARLY_EN = 1
630 12:40:22.641780 VALID_LAT_VALUE = 1
631 12:40:22.648766 ==============================================================
632 12:40:22.652192 Enter into Gating configuration >>>>
633 12:40:22.655600 Exit from Gating configuration <<<<
634 12:40:22.658710 Enter into DVFS_PRE_config >>>>>
635 12:40:22.668719 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 12:40:22.671898 Exit from DVFS_PRE_config <<<<<
637 12:40:22.675334 Enter into PICG configuration >>>>
638 12:40:22.678714 Exit from PICG configuration <<<<
639 12:40:22.681605 [RX_INPUT] configuration >>>>>
640 12:40:22.681782 [RX_INPUT] configuration <<<<<
641 12:40:22.688430 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 12:40:22.695286 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 12:40:22.701596 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 12:40:22.705202 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 12:40:22.711901 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 12:40:22.718398 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 12:40:22.721910 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 12:40:22.725136 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 12:40:22.731622 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 12:40:22.735239 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 12:40:22.738062 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 12:40:22.744762 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 12:40:22.748283 ===================================
654 12:40:22.748458 LPDDR4 DRAM CONFIGURATION
655 12:40:22.751732 ===================================
656 12:40:22.754659 EX_ROW_EN[0] = 0x0
657 12:40:22.754820 EX_ROW_EN[1] = 0x0
658 12:40:22.758311 LP4Y_EN = 0x0
659 12:40:22.762164 WORK_FSP = 0x0
660 12:40:22.762327 WL = 0x2
661 12:40:22.762475 RL = 0x2
662 12:40:22.765722 BL = 0x2
663 12:40:22.765882 RPST = 0x0
664 12:40:22.769139 RD_PRE = 0x0
665 12:40:22.769301 WR_PRE = 0x1
666 12:40:22.772365 WR_PST = 0x0
667 12:40:22.772524 DBI_WR = 0x0
668 12:40:22.775925 DBI_RD = 0x0
669 12:40:22.776085 OTF = 0x1
670 12:40:22.778775 ===================================
671 12:40:22.785661 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 12:40:22.789127 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 12:40:22.792372 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 12:40:22.795656 ===================================
675 12:40:22.798748 LPDDR4 DRAM CONFIGURATION
676 12:40:22.802294 ===================================
677 12:40:22.805709 EX_ROW_EN[0] = 0x10
678 12:40:22.805896 EX_ROW_EN[1] = 0x0
679 12:40:22.808788 LP4Y_EN = 0x0
680 12:40:22.808948 WORK_FSP = 0x0
681 12:40:22.812288 WL = 0x2
682 12:40:22.812463 RL = 0x2
683 12:40:22.815258 BL = 0x2
684 12:40:22.815414 RPST = 0x0
685 12:40:22.818801 RD_PRE = 0x0
686 12:40:22.818985 WR_PRE = 0x1
687 12:40:22.821758 WR_PST = 0x0
688 12:40:22.821908 DBI_WR = 0x0
689 12:40:22.825398 DBI_RD = 0x0
690 12:40:22.825556 OTF = 0x1
691 12:40:22.828961 ===================================
692 12:40:22.835537 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 12:40:22.840160 nWR fixed to 40
694 12:40:22.843645 [ModeRegInit_LP4] CH0 RK0
695 12:40:22.843739 [ModeRegInit_LP4] CH0 RK1
696 12:40:22.846671 [ModeRegInit_LP4] CH1 RK0
697 12:40:22.849639 [ModeRegInit_LP4] CH1 RK1
698 12:40:22.849776 match AC timing 13
699 12:40:22.856623 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 12:40:22.859590 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 12:40:22.863222 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 12:40:22.870650 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 12:40:22.873965 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 12:40:22.874069 [EMI DOE] emi_dcm 0
705 12:40:22.880722 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 12:40:22.880869 ==
707 12:40:22.884148 Dram Type= 6, Freq= 0, CH_0, rank 0
708 12:40:22.887708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 12:40:22.887803 ==
710 12:40:22.893891 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 12:40:22.897299 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 12:40:22.907856 [CA 0] Center 38 (7~69) winsize 63
713 12:40:22.911124 [CA 1] Center 37 (7~68) winsize 62
714 12:40:22.914133 [CA 2] Center 35 (5~66) winsize 62
715 12:40:22.917548 [CA 3] Center 35 (5~66) winsize 62
716 12:40:22.920797 [CA 4] Center 34 (4~65) winsize 62
717 12:40:22.924398 [CA 5] Center 34 (4~65) winsize 62
718 12:40:22.924492
719 12:40:22.927316 [CmdBusTrainingLP45] Vref(ca) range 1: 34
720 12:40:22.927407
721 12:40:22.930817 [CATrainingPosCal] consider 1 rank data
722 12:40:22.934386 u2DelayCellTimex100 = 270/100 ps
723 12:40:22.937429 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
724 12:40:22.940992 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
725 12:40:22.947310 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
726 12:40:22.950902 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
727 12:40:22.953878 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
728 12:40:22.957557 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
729 12:40:22.957648
730 12:40:22.960884 CA PerBit enable=1, Macro0, CA PI delay=34
731 12:40:22.960975
732 12:40:22.963978 [CBTSetCACLKResult] CA Dly = 34
733 12:40:22.964068 CS Dly: 6 (0~37)
734 12:40:22.967121 ==
735 12:40:22.967211 Dram Type= 6, Freq= 0, CH_0, rank 1
736 12:40:22.974182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 12:40:22.974276 ==
738 12:40:22.977474 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 12:40:22.983752 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 12:40:22.994038 [CA 0] Center 38 (7~69) winsize 63
741 12:40:22.997238 [CA 1] Center 38 (7~69) winsize 63
742 12:40:23.000678 [CA 2] Center 35 (5~66) winsize 62
743 12:40:23.003552 [CA 3] Center 35 (5~66) winsize 62
744 12:40:23.006913 [CA 4] Center 34 (4~65) winsize 62
745 12:40:23.010316 [CA 5] Center 34 (4~64) winsize 61
746 12:40:23.010407
747 12:40:23.013628 [CmdBusTrainingLP45] Vref(ca) range 1: 30
748 12:40:23.013725
749 12:40:23.017434 [CATrainingPosCal] consider 2 rank data
750 12:40:23.020707 u2DelayCellTimex100 = 270/100 ps
751 12:40:23.023812 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
752 12:40:23.030576 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
753 12:40:23.033622 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
754 12:40:23.036658 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
755 12:40:23.040352 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
756 12:40:23.043355 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
757 12:40:23.043447
758 12:40:23.047037 CA PerBit enable=1, Macro0, CA PI delay=34
759 12:40:23.047151
760 12:40:23.049961 [CBTSetCACLKResult] CA Dly = 34
761 12:40:23.050062 CS Dly: 6 (0~38)
762 12:40:23.053376
763 12:40:23.057016 ----->DramcWriteLeveling(PI) begin...
764 12:40:23.057130 ==
765 12:40:23.059996 Dram Type= 6, Freq= 0, CH_0, rank 0
766 12:40:23.063146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 12:40:23.063225 ==
768 12:40:23.066681 Write leveling (Byte 0): 30 => 30
769 12:40:23.070156 Write leveling (Byte 1): 29 => 29
770 12:40:23.073694 DramcWriteLeveling(PI) end<-----
771 12:40:23.073800
772 12:40:23.073894 ==
773 12:40:23.076670 Dram Type= 6, Freq= 0, CH_0, rank 0
774 12:40:23.080177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 12:40:23.080256 ==
776 12:40:23.084408 [Gating] SW mode calibration
777 12:40:23.091457 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 12:40:23.095019 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 12:40:23.098997 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 12:40:23.105980 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
781 12:40:23.109427 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
782 12:40:23.113369 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
783 12:40:23.117218 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 12:40:23.120667 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 12:40:23.128070 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 12:40:23.131345 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 12:40:23.135168 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 12:40:23.138764 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 12:40:23.142463 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 12:40:23.149690 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 12:40:23.153290 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 12:40:23.157520 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 12:40:23.160510 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 12:40:23.164737 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 12:40:23.172012 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:40:23.175605 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:40:23.178957 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
798 12:40:23.182559 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
799 12:40:23.190029 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:40:23.193591 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 12:40:23.197020 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 12:40:23.201065 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:40:23.204491 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 12:40:23.211864 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 12:40:23.215878 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 12:40:23.219227 0 9 12 | B1->B0 | 2424 3333 | 1 1 | (1 1) (1 1)
807 12:40:23.222671 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 12:40:23.226049 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 12:40:23.233177 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 12:40:23.237427 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 12:40:23.241025 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 12:40:23.244717 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 12:40:23.248316 0 10 8 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
814 12:40:23.251984 0 10 12 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
815 12:40:23.259228 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 12:40:23.262744 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 12:40:23.266324 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 12:40:23.270180 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 12:40:23.277355 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 12:40:23.280929 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 12:40:23.284787 0 11 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
822 12:40:23.288514 0 11 12 | B1->B0 | 3232 3f3f | 0 0 | (0 0) (0 0)
823 12:40:23.292120 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 12:40:23.299495 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 12:40:23.303323 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 12:40:23.306692 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 12:40:23.310489 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 12:40:23.314049 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 12:40:23.321625 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
830 12:40:23.325023 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
831 12:40:23.328503 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 12:40:23.332450 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 12:40:23.336465 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 12:40:23.343841 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 12:40:23.347163 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 12:40:23.351056 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 12:40:23.354406 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 12:40:23.358113 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 12:40:23.365280 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 12:40:23.368881 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 12:40:23.372483 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 12:40:23.376172 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 12:40:23.379878 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:40:23.387561 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
845 12:40:23.391062 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
846 12:40:23.394675 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 12:40:23.398320 Total UI for P1: 0, mck2ui 16
848 12:40:23.401917 best dqsien dly found for B0: ( 0, 14, 6)
849 12:40:23.402313 Total UI for P1: 0, mck2ui 16
850 12:40:23.409245 best dqsien dly found for B1: ( 0, 14, 10)
851 12:40:23.412259 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
852 12:40:23.415455 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
853 12:40:23.415876
854 12:40:23.418793 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
855 12:40:23.422080 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
856 12:40:23.425547 [Gating] SW calibration Done
857 12:40:23.425941 ==
858 12:40:23.428440 Dram Type= 6, Freq= 0, CH_0, rank 0
859 12:40:23.431941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
860 12:40:23.432342 ==
861 12:40:23.435248 RX Vref Scan: 0
862 12:40:23.435638
863 12:40:23.435984 RX Vref 0 -> 0, step: 1
864 12:40:23.436390
865 12:40:23.438698 RX Delay -130 -> 252, step: 16
866 12:40:23.441582 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
867 12:40:23.448504 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
868 12:40:23.451489 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
869 12:40:23.455079 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
870 12:40:23.458074 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
871 12:40:23.461790 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
872 12:40:23.468174 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
873 12:40:23.471262 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
874 12:40:23.474842 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
875 12:40:23.478435 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
876 12:40:23.481444 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
877 12:40:23.488263 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
878 12:40:23.491355 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
879 12:40:23.494784 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
880 12:40:23.498230 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
881 12:40:23.501246 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
882 12:40:23.504699 ==
883 12:40:23.507784 Dram Type= 6, Freq= 0, CH_0, rank 0
884 12:40:23.511436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
885 12:40:23.511519 ==
886 12:40:23.511587 DQS Delay:
887 12:40:23.514361 DQS0 = 0, DQS1 = 0
888 12:40:23.514443 DQM Delay:
889 12:40:23.517780 DQM0 = 82, DQM1 = 69
890 12:40:23.517863 DQ Delay:
891 12:40:23.521126 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
892 12:40:23.524426 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
893 12:40:23.527975 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
894 12:40:23.531296 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
895 12:40:23.531371
896 12:40:23.531436
897 12:40:23.531496 ==
898 12:40:23.534214 Dram Type= 6, Freq= 0, CH_0, rank 0
899 12:40:23.537633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
900 12:40:23.537709 ==
901 12:40:23.537773
902 12:40:23.537831
903 12:40:23.541190 TX Vref Scan disable
904 12:40:23.544329 == TX Byte 0 ==
905 12:40:23.547644 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
906 12:40:23.551007 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
907 12:40:23.554376 == TX Byte 1 ==
908 12:40:23.557999 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
909 12:40:23.560893 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
910 12:40:23.561000 ==
911 12:40:23.564538 Dram Type= 6, Freq= 0, CH_0, rank 0
912 12:40:23.571144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 12:40:23.571223 ==
914 12:40:23.582416 TX Vref=22, minBit 0, minWin=26, winSum=429
915 12:40:23.585991 TX Vref=24, minBit 11, minWin=26, winSum=435
916 12:40:23.589127 TX Vref=26, minBit 1, minWin=27, winSum=443
917 12:40:23.592241 TX Vref=28, minBit 1, minWin=27, winSum=442
918 12:40:23.595737 TX Vref=30, minBit 2, minWin=27, winSum=442
919 12:40:23.602278 TX Vref=32, minBit 10, minWin=26, winSum=440
920 12:40:23.605832 [TxChooseVref] Worse bit 1, Min win 27, Win sum 443, Final Vref 26
921 12:40:23.605909
922 12:40:23.608906 Final TX Range 1 Vref 26
923 12:40:23.609007
924 12:40:23.609102 ==
925 12:40:23.612559 Dram Type= 6, Freq= 0, CH_0, rank 0
926 12:40:23.615601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 12:40:23.618706 ==
928 12:40:23.618811
929 12:40:23.618921
930 12:40:23.618983 TX Vref Scan disable
931 12:40:23.622295 == TX Byte 0 ==
932 12:40:23.625819 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
933 12:40:23.632351 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
934 12:40:23.632456 == TX Byte 1 ==
935 12:40:23.635764 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
936 12:40:23.642901 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
937 12:40:23.642980
938 12:40:23.643065 [DATLAT]
939 12:40:23.643129 Freq=800, CH0 RK0
940 12:40:23.643189
941 12:40:23.645655 DATLAT Default: 0xa
942 12:40:23.645755 0, 0xFFFF, sum = 0
943 12:40:23.648985 1, 0xFFFF, sum = 0
944 12:40:23.649092 2, 0xFFFF, sum = 0
945 12:40:23.652360 3, 0xFFFF, sum = 0
946 12:40:23.655802 4, 0xFFFF, sum = 0
947 12:40:23.655916 5, 0xFFFF, sum = 0
948 12:40:23.659163 6, 0xFFFF, sum = 0
949 12:40:23.659245 7, 0xFFFF, sum = 0
950 12:40:23.662627 8, 0xFFFF, sum = 0
951 12:40:23.662705 9, 0x0, sum = 1
952 12:40:23.665564 10, 0x0, sum = 2
953 12:40:23.665644 11, 0x0, sum = 3
954 12:40:23.665708 12, 0x0, sum = 4
955 12:40:23.669097 best_step = 10
956 12:40:23.669207
957 12:40:23.669307 ==
958 12:40:23.672099 Dram Type= 6, Freq= 0, CH_0, rank 0
959 12:40:23.675673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 12:40:23.675749 ==
961 12:40:23.679122 RX Vref Scan: 1
962 12:40:23.679199
963 12:40:23.682132 Set Vref Range= 32 -> 127
964 12:40:23.682230
965 12:40:23.682321 RX Vref 32 -> 127, step: 1
966 12:40:23.682414
967 12:40:23.685828 RX Delay -111 -> 252, step: 8
968 12:40:23.685944
969 12:40:23.689206 Set Vref, RX VrefLevel [Byte0]: 32
970 12:40:23.692144 [Byte1]: 32
971 12:40:23.695161
972 12:40:23.695237 Set Vref, RX VrefLevel [Byte0]: 33
973 12:40:23.698702 [Byte1]: 33
974 12:40:23.702907
975 12:40:23.702991 Set Vref, RX VrefLevel [Byte0]: 34
976 12:40:23.706534 [Byte1]: 34
977 12:40:23.710628
978 12:40:23.710730 Set Vref, RX VrefLevel [Byte0]: 35
979 12:40:23.714013 [Byte1]: 35
980 12:40:23.718227
981 12:40:23.718303 Set Vref, RX VrefLevel [Byte0]: 36
982 12:40:23.721848 [Byte1]: 36
983 12:40:23.725938
984 12:40:23.726013 Set Vref, RX VrefLevel [Byte0]: 37
985 12:40:23.728958 [Byte1]: 37
986 12:40:23.733576
987 12:40:23.733676 Set Vref, RX VrefLevel [Byte0]: 38
988 12:40:23.737056 [Byte1]: 38
989 12:40:23.741536
990 12:40:23.741640 Set Vref, RX VrefLevel [Byte0]: 39
991 12:40:23.744720 [Byte1]: 39
992 12:40:23.749160
993 12:40:23.749272 Set Vref, RX VrefLevel [Byte0]: 40
994 12:40:23.752441 [Byte1]: 40
995 12:40:23.757020
996 12:40:23.757110 Set Vref, RX VrefLevel [Byte0]: 41
997 12:40:23.760394 [Byte1]: 41
998 12:40:23.764344
999 12:40:23.764432 Set Vref, RX VrefLevel [Byte0]: 42
1000 12:40:23.767798 [Byte1]: 42
1001 12:40:23.771752
1002 12:40:23.771826 Set Vref, RX VrefLevel [Byte0]: 43
1003 12:40:23.774804 [Byte1]: 43
1004 12:40:23.779665
1005 12:40:23.779743 Set Vref, RX VrefLevel [Byte0]: 44
1006 12:40:23.783064 [Byte1]: 44
1007 12:40:23.787384
1008 12:40:23.787501 Set Vref, RX VrefLevel [Byte0]: 45
1009 12:40:23.790411 [Byte1]: 45
1010 12:40:23.794702
1011 12:40:23.794810 Set Vref, RX VrefLevel [Byte0]: 46
1012 12:40:23.798362 [Byte1]: 46
1013 12:40:23.802553
1014 12:40:23.802664 Set Vref, RX VrefLevel [Byte0]: 47
1015 12:40:23.806225 [Byte1]: 47
1016 12:40:23.810321
1017 12:40:23.810425 Set Vref, RX VrefLevel [Byte0]: 48
1018 12:40:23.814202 [Byte1]: 48
1019 12:40:23.817928
1020 12:40:23.818005 Set Vref, RX VrefLevel [Byte0]: 49
1021 12:40:23.821754 [Byte1]: 49
1022 12:40:23.825241
1023 12:40:23.828267 Set Vref, RX VrefLevel [Byte0]: 50
1024 12:40:23.832083 [Byte1]: 50
1025 12:40:23.832190
1026 12:40:23.835654 Set Vref, RX VrefLevel [Byte0]: 51
1027 12:40:23.839225 [Byte1]: 51
1028 12:40:23.839300
1029 12:40:23.842105 Set Vref, RX VrefLevel [Byte0]: 52
1030 12:40:23.845586 [Byte1]: 52
1031 12:40:23.845687
1032 12:40:23.849147 Set Vref, RX VrefLevel [Byte0]: 53
1033 12:40:23.851999 [Byte1]: 53
1034 12:40:23.855930
1035 12:40:23.856033 Set Vref, RX VrefLevel [Byte0]: 54
1036 12:40:23.859352 [Byte1]: 54
1037 12:40:23.863506
1038 12:40:23.863590 Set Vref, RX VrefLevel [Byte0]: 55
1039 12:40:23.866817 [Byte1]: 55
1040 12:40:23.871525
1041 12:40:23.871606 Set Vref, RX VrefLevel [Byte0]: 56
1042 12:40:23.874263 [Byte1]: 56
1043 12:40:23.878716
1044 12:40:23.878797 Set Vref, RX VrefLevel [Byte0]: 57
1045 12:40:23.882151 [Byte1]: 57
1046 12:40:23.886583
1047 12:40:23.886664 Set Vref, RX VrefLevel [Byte0]: 58
1048 12:40:23.889624 [Byte1]: 58
1049 12:40:23.894028
1050 12:40:23.894108 Set Vref, RX VrefLevel [Byte0]: 59
1051 12:40:23.897705 [Byte1]: 59
1052 12:40:23.902066
1053 12:40:23.902147 Set Vref, RX VrefLevel [Byte0]: 60
1054 12:40:23.905021 [Byte1]: 60
1055 12:40:23.909235
1056 12:40:23.909342 Set Vref, RX VrefLevel [Byte0]: 61
1057 12:40:23.912857 [Byte1]: 61
1058 12:40:23.917169
1059 12:40:23.917252 Set Vref, RX VrefLevel [Byte0]: 62
1060 12:40:23.920783 [Byte1]: 62
1061 12:40:23.924765
1062 12:40:23.924847 Set Vref, RX VrefLevel [Byte0]: 63
1063 12:40:23.928153 [Byte1]: 63
1064 12:40:23.932437
1065 12:40:23.932517 Set Vref, RX VrefLevel [Byte0]: 64
1066 12:40:23.935570 [Byte1]: 64
1067 12:40:23.939784
1068 12:40:23.939891 Set Vref, RX VrefLevel [Byte0]: 65
1069 12:40:23.943399 [Byte1]: 65
1070 12:40:23.947532
1071 12:40:23.947651 Set Vref, RX VrefLevel [Byte0]: 66
1072 12:40:23.950797 [Byte1]: 66
1073 12:40:23.955654
1074 12:40:23.955730 Set Vref, RX VrefLevel [Byte0]: 67
1075 12:40:23.958590 [Byte1]: 67
1076 12:40:23.963181
1077 12:40:23.963258 Set Vref, RX VrefLevel [Byte0]: 68
1078 12:40:23.966553 [Byte1]: 68
1079 12:40:23.970779
1080 12:40:23.970891 Set Vref, RX VrefLevel [Byte0]: 69
1081 12:40:23.973745 [Byte1]: 69
1082 12:40:23.978487
1083 12:40:23.978559 Set Vref, RX VrefLevel [Byte0]: 70
1084 12:40:23.981574 [Byte1]: 70
1085 12:40:23.986012
1086 12:40:23.986082 Set Vref, RX VrefLevel [Byte0]: 71
1087 12:40:23.989280 [Byte1]: 71
1088 12:40:23.993734
1089 12:40:23.993805 Set Vref, RX VrefLevel [Byte0]: 72
1090 12:40:23.996820 [Byte1]: 72
1091 12:40:24.001021
1092 12:40:24.001091 Set Vref, RX VrefLevel [Byte0]: 73
1093 12:40:24.004210 [Byte1]: 73
1094 12:40:24.009105
1095 12:40:24.009178 Set Vref, RX VrefLevel [Byte0]: 74
1096 12:40:24.012185 [Byte1]: 74
1097 12:40:24.016274
1098 12:40:24.016345 Set Vref, RX VrefLevel [Byte0]: 75
1099 12:40:24.019880 [Byte1]: 75
1100 12:40:24.024165
1101 12:40:24.024239 Set Vref, RX VrefLevel [Byte0]: 76
1102 12:40:24.027166 [Byte1]: 76
1103 12:40:24.031529
1104 12:40:24.031606 Set Vref, RX VrefLevel [Byte0]: 77
1105 12:40:24.035163 [Byte1]: 77
1106 12:40:24.039276
1107 12:40:24.039349 Set Vref, RX VrefLevel [Byte0]: 78
1108 12:40:24.043087 [Byte1]: 78
1109 12:40:24.047110
1110 12:40:24.047188 Set Vref, RX VrefLevel [Byte0]: 79
1111 12:40:24.050114 [Byte1]: 79
1112 12:40:24.054692
1113 12:40:24.054798 Final RX Vref Byte 0 = 61 to rank0
1114 12:40:24.058223 Final RX Vref Byte 1 = 59 to rank0
1115 12:40:24.061334 Final RX Vref Byte 0 = 61 to rank1
1116 12:40:24.064821 Final RX Vref Byte 1 = 59 to rank1==
1117 12:40:24.068261 Dram Type= 6, Freq= 0, CH_0, rank 0
1118 12:40:24.074566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1119 12:40:24.074670 ==
1120 12:40:24.074771 DQS Delay:
1121 12:40:24.077509 DQS0 = 0, DQS1 = 0
1122 12:40:24.077587 DQM Delay:
1123 12:40:24.077651 DQM0 = 81, DQM1 = 67
1124 12:40:24.081339 DQ Delay:
1125 12:40:24.084576 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1126 12:40:24.087644 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1127 12:40:24.091074 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1128 12:40:24.094420 DQ12 =72, DQ13 =72, DQ14 =76, DQ15 =76
1129 12:40:24.094515
1130 12:40:24.094608
1131 12:40:24.100714 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a28, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
1132 12:40:24.104404 CH0 RK0: MR19=606, MR18=2A28
1133 12:40:24.111080 CH0_RK0: MR19=0x606, MR18=0x2A28, DQSOSC=399, MR23=63, INC=92, DEC=61
1134 12:40:24.111161
1135 12:40:24.114109 ----->DramcWriteLeveling(PI) begin...
1136 12:40:24.114202 ==
1137 12:40:24.117640 Dram Type= 6, Freq= 0, CH_0, rank 1
1138 12:40:24.120614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1139 12:40:24.120699 ==
1140 12:40:24.124231 Write leveling (Byte 0): 31 => 31
1141 12:40:24.127235 Write leveling (Byte 1): 30 => 30
1142 12:40:24.130757 DramcWriteLeveling(PI) end<-----
1143 12:40:24.130872
1144 12:40:24.130940 ==
1145 12:40:24.134355 Dram Type= 6, Freq= 0, CH_0, rank 1
1146 12:40:24.137249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1147 12:40:24.137329 ==
1148 12:40:24.140933 [Gating] SW mode calibration
1149 12:40:24.147515 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1150 12:40:24.154128 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1151 12:40:24.157631 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1152 12:40:24.163917 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1153 12:40:24.167029 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1154 12:40:24.170444 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 12:40:24.177246 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 12:40:24.180708 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 12:40:24.183610 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 12:40:24.187248 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 12:40:24.194163 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 12:40:24.197086 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 12:40:24.200603 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 12:40:24.206776 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 12:40:24.210296 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 12:40:24.213595 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 12:40:24.220249 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 12:40:24.264280 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 12:40:24.264554 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 12:40:24.264629 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1169 12:40:24.264741 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1170 12:40:24.264868 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 12:40:24.264956 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 12:40:24.265733 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 12:40:24.265802 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 12:40:24.266060 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 12:40:24.266213 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 12:40:24.269154 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 12:40:24.272773 0 9 8 | B1->B0 | 2424 2c2c | 1 1 | (1 1) (1 1)
1178 12:40:24.275689 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1179 12:40:24.282457 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 12:40:24.285756 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 12:40:24.289181 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 12:40:24.295808 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 12:40:24.298655 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 12:40:24.302190 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
1185 12:40:24.308589 0 10 8 | B1->B0 | 2f2f 2525 | 0 0 | (0 1) (0 0)
1186 12:40:24.311821 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
1187 12:40:24.315372 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 12:40:24.322113 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 12:40:24.325130 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 12:40:24.328679 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 12:40:24.335411 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 12:40:24.338536 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1193 12:40:24.341488 0 11 8 | B1->B0 | 3434 3c3c | 1 1 | (0 0) (0 0)
1194 12:40:24.348367 0 11 12 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
1195 12:40:24.351805 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 12:40:24.354892 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 12:40:24.361779 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 12:40:24.364842 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 12:40:24.368229 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 12:40:24.374749 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1201 12:40:24.378362 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1202 12:40:24.381901 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1203 12:40:24.385344 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 12:40:24.392555 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 12:40:24.396500 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 12:40:24.399569 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 12:40:24.403035 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 12:40:24.410066 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 12:40:24.413553 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 12:40:24.416931 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 12:40:24.419913 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 12:40:24.426610 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 12:40:24.430279 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 12:40:24.433385 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 12:40:24.440074 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 12:40:24.443169 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 12:40:24.446809 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1218 12:40:24.453406 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 12:40:24.456708 Total UI for P1: 0, mck2ui 16
1220 12:40:24.459642 best dqsien dly found for B0: ( 0, 14, 8)
1221 12:40:24.463128 Total UI for P1: 0, mck2ui 16
1222 12:40:24.466721 best dqsien dly found for B1: ( 0, 14, 8)
1223 12:40:24.469781 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1224 12:40:24.473225 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1225 12:40:24.473308
1226 12:40:24.476200 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1227 12:40:24.479790 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1228 12:40:24.482816 [Gating] SW calibration Done
1229 12:40:24.482938 ==
1230 12:40:24.486501 Dram Type= 6, Freq= 0, CH_0, rank 1
1231 12:40:24.489403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1232 12:40:24.489501 ==
1233 12:40:24.492905 RX Vref Scan: 0
1234 12:40:24.492988
1235 12:40:24.493053 RX Vref 0 -> 0, step: 1
1236 12:40:24.493112
1237 12:40:24.496187 RX Delay -130 -> 252, step: 16
1238 12:40:24.503242 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1239 12:40:24.506496 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1240 12:40:24.509310 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1241 12:40:24.512709 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1242 12:40:24.516148 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1243 12:40:24.522975 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1244 12:40:24.526225 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1245 12:40:24.529626 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1246 12:40:24.532672 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1247 12:40:24.535743 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1248 12:40:24.542426 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1249 12:40:24.546009 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1250 12:40:24.549113 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1251 12:40:24.552757 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1252 12:40:24.555915 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1253 12:40:24.562295 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1254 12:40:24.562378 ==
1255 12:40:24.565744 Dram Type= 6, Freq= 0, CH_0, rank 1
1256 12:40:24.569163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1257 12:40:24.569276 ==
1258 12:40:24.569358 DQS Delay:
1259 12:40:24.572310 DQS0 = 0, DQS1 = 0
1260 12:40:24.572393 DQM Delay:
1261 12:40:24.575738 DQM0 = 80, DQM1 = 69
1262 12:40:24.575835 DQ Delay:
1263 12:40:24.578729 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =69
1264 12:40:24.582372 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
1265 12:40:24.585968 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1266 12:40:24.589156 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1267 12:40:24.589245
1268 12:40:24.589349
1269 12:40:24.589409 ==
1270 12:40:24.592183 Dram Type= 6, Freq= 0, CH_0, rank 1
1271 12:40:24.595682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1272 12:40:24.595757 ==
1273 12:40:24.599209
1274 12:40:24.599290
1275 12:40:24.599355 TX Vref Scan disable
1276 12:40:24.602155 == TX Byte 0 ==
1277 12:40:24.605662 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1278 12:40:24.609123 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1279 12:40:24.612419 == TX Byte 1 ==
1280 12:40:24.615323 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1281 12:40:24.618821 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1282 12:40:24.618939 ==
1283 12:40:24.622357 Dram Type= 6, Freq= 0, CH_0, rank 1
1284 12:40:24.628533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1285 12:40:24.628613 ==
1286 12:40:24.640492 TX Vref=22, minBit 11, minWin=26, winSum=433
1287 12:40:24.644208 TX Vref=24, minBit 1, minWin=26, winSum=436
1288 12:40:24.647643 TX Vref=26, minBit 1, minWin=27, winSum=440
1289 12:40:24.650694 TX Vref=28, minBit 1, minWin=27, winSum=443
1290 12:40:24.654187 TX Vref=30, minBit 1, minWin=27, winSum=442
1291 12:40:24.660794 TX Vref=32, minBit 1, minWin=27, winSum=441
1292 12:40:24.663864 [TxChooseVref] Worse bit 1, Min win 27, Win sum 443, Final Vref 28
1293 12:40:24.663962
1294 12:40:24.667231 Final TX Range 1 Vref 28
1295 12:40:24.667337
1296 12:40:24.667403 ==
1297 12:40:24.670709 Dram Type= 6, Freq= 0, CH_0, rank 1
1298 12:40:24.673716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1299 12:40:24.673797 ==
1300 12:40:24.677383
1301 12:40:24.677463
1302 12:40:24.677526 TX Vref Scan disable
1303 12:40:24.680789 == TX Byte 0 ==
1304 12:40:24.684278 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1305 12:40:24.690514 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1306 12:40:24.690595 == TX Byte 1 ==
1307 12:40:24.694181 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1308 12:40:24.700735 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1309 12:40:24.700815
1310 12:40:24.700879 [DATLAT]
1311 12:40:24.700938 Freq=800, CH0 RK1
1312 12:40:24.700995
1313 12:40:24.704174 DATLAT Default: 0xa
1314 12:40:24.704254 0, 0xFFFF, sum = 0
1315 12:40:24.707156 1, 0xFFFF, sum = 0
1316 12:40:24.707238 2, 0xFFFF, sum = 0
1317 12:40:24.710714 3, 0xFFFF, sum = 0
1318 12:40:24.713660 4, 0xFFFF, sum = 0
1319 12:40:24.713775 5, 0xFFFF, sum = 0
1320 12:40:24.716961 6, 0xFFFF, sum = 0
1321 12:40:24.717071 7, 0xFFFF, sum = 0
1322 12:40:24.720516 8, 0xFFFF, sum = 0
1323 12:40:24.720597 9, 0x0, sum = 1
1324 12:40:24.723535 10, 0x0, sum = 2
1325 12:40:24.723617 11, 0x0, sum = 3
1326 12:40:24.723682 12, 0x0, sum = 4
1327 12:40:24.727161 best_step = 10
1328 12:40:24.727240
1329 12:40:24.727303 ==
1330 12:40:24.730620 Dram Type= 6, Freq= 0, CH_0, rank 1
1331 12:40:24.733626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1332 12:40:24.733707 ==
1333 12:40:24.736916 RX Vref Scan: 0
1334 12:40:24.737025
1335 12:40:24.740384 RX Vref 0 -> 0, step: 1
1336 12:40:24.740464
1337 12:40:24.740528 RX Delay -111 -> 252, step: 8
1338 12:40:24.747783 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1339 12:40:24.750759 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1340 12:40:24.754545 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1341 12:40:24.757470 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1342 12:40:24.760590 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1343 12:40:24.767243 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1344 12:40:24.770887 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1345 12:40:24.773896 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1346 12:40:24.777331 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1347 12:40:24.781036 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1348 12:40:24.787166 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1349 12:40:24.790570 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1350 12:40:24.794103 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1351 12:40:24.797645 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1352 12:40:24.804220 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1353 12:40:24.807091 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1354 12:40:24.807171 ==
1355 12:40:24.810665 Dram Type= 6, Freq= 0, CH_0, rank 1
1356 12:40:24.813719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1357 12:40:24.813825 ==
1358 12:40:24.813892 DQS Delay:
1359 12:40:24.817307 DQS0 = 0, DQS1 = 0
1360 12:40:24.817403 DQM Delay:
1361 12:40:24.820868 DQM0 = 78, DQM1 = 71
1362 12:40:24.820948 DQ Delay:
1363 12:40:24.823894 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1364 12:40:24.827294 DQ4 =76, DQ5 =64, DQ6 =88, DQ7 =88
1365 12:40:24.830722 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1366 12:40:24.833632 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =80
1367 12:40:24.833742
1368 12:40:24.833834
1369 12:40:24.843793 [DQSOSCAuto] RK1, (LSB)MR18= 0x4a25, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
1370 12:40:24.843875 CH0 RK1: MR19=606, MR18=4A25
1371 12:40:24.850523 CH0_RK1: MR19=0x606, MR18=0x4A25, DQSOSC=391, MR23=63, INC=96, DEC=64
1372 12:40:24.853547 [RxdqsGatingPostProcess] freq 800
1373 12:40:24.860102 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1374 12:40:24.863657 Pre-setting of DQS Precalculation
1375 12:40:24.866618 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1376 12:40:24.866716 ==
1377 12:40:24.870183 Dram Type= 6, Freq= 0, CH_1, rank 0
1378 12:40:24.876844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1379 12:40:24.876929 ==
1380 12:40:24.879812 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1381 12:40:24.886658 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1382 12:40:24.895973 [CA 0] Center 36 (6~67) winsize 62
1383 12:40:24.899093 [CA 1] Center 36 (6~67) winsize 62
1384 12:40:24.902203 [CA 2] Center 34 (5~64) winsize 60
1385 12:40:24.905800 [CA 3] Center 34 (4~64) winsize 61
1386 12:40:24.909211 [CA 4] Center 34 (4~65) winsize 62
1387 12:40:24.912634 [CA 5] Center 33 (3~64) winsize 62
1388 12:40:24.912706
1389 12:40:24.915725 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1390 12:40:24.915804
1391 12:40:24.919280 [CATrainingPosCal] consider 1 rank data
1392 12:40:24.922711 u2DelayCellTimex100 = 270/100 ps
1393 12:40:24.925735 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1394 12:40:24.929520 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1395 12:40:24.935800 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1396 12:40:24.939138 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1397 12:40:24.942596 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1398 12:40:24.946152 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1399 12:40:24.946233
1400 12:40:24.948940 CA PerBit enable=1, Macro0, CA PI delay=33
1401 12:40:24.949063
1402 12:40:24.952523 [CBTSetCACLKResult] CA Dly = 33
1403 12:40:24.952653 CS Dly: 5 (0~36)
1404 12:40:24.952773 ==
1405 12:40:24.955751 Dram Type= 6, Freq= 0, CH_1, rank 1
1406 12:40:24.962334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1407 12:40:24.962419 ==
1408 12:40:24.965430 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1409 12:40:24.972382 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1410 12:40:24.982079 [CA 0] Center 36 (6~66) winsize 61
1411 12:40:24.985170 [CA 1] Center 36 (6~67) winsize 62
1412 12:40:24.988238 [CA 2] Center 35 (5~65) winsize 61
1413 12:40:24.991521 [CA 3] Center 33 (3~64) winsize 62
1414 12:40:24.995126 [CA 4] Center 34 (4~65) winsize 62
1415 12:40:24.998641 [CA 5] Center 33 (3~64) winsize 62
1416 12:40:24.998714
1417 12:40:25.002069 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1418 12:40:25.002154
1419 12:40:25.005115 [CATrainingPosCal] consider 2 rank data
1420 12:40:25.008207 u2DelayCellTimex100 = 270/100 ps
1421 12:40:25.011829 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1422 12:40:25.018184 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1423 12:40:25.021861 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1424 12:40:25.024983 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1425 12:40:25.028431 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1426 12:40:25.031469 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1427 12:40:25.031551
1428 12:40:25.035122 CA PerBit enable=1, Macro0, CA PI delay=33
1429 12:40:25.035204
1430 12:40:25.038129 [CBTSetCACLKResult] CA Dly = 33
1431 12:40:25.041505 CS Dly: 6 (0~38)
1432 12:40:25.041587
1433 12:40:25.041652 ----->DramcWriteLeveling(PI) begin...
1434 12:40:25.045507 ==
1435 12:40:25.045591 Dram Type= 6, Freq= 0, CH_1, rank 0
1436 12:40:25.053311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1437 12:40:25.053395 ==
1438 12:40:25.053461 Write leveling (Byte 0): 26 => 26
1439 12:40:25.056805 Write leveling (Byte 1): 30 => 30
1440 12:40:25.060128 DramcWriteLeveling(PI) end<-----
1441 12:40:25.060206
1442 12:40:25.060275 ==
1443 12:40:25.063875 Dram Type= 6, Freq= 0, CH_1, rank 0
1444 12:40:25.067537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1445 12:40:25.067617 ==
1446 12:40:25.070508 [Gating] SW mode calibration
1447 12:40:25.077829 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1448 12:40:25.084670 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1449 12:40:25.087711 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1450 12:40:25.091338 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1451 12:40:25.097964 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1452 12:40:25.101464 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 12:40:25.104864 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 12:40:25.111271 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 12:40:25.114799 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 12:40:25.117887 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 12:40:25.124336 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 12:40:25.127997 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 12:40:25.130940 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 12:40:25.134484 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 12:40:25.141371 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 12:40:25.144310 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 12:40:25.148021 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 12:40:25.154266 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 12:40:25.157610 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 12:40:25.161088 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1467 12:40:25.167971 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1468 12:40:25.171286 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 12:40:25.174085 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 12:40:25.181124 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 12:40:25.184112 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 12:40:25.187746 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 12:40:25.194543 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 12:40:25.197635 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 12:40:25.200746 0 9 8 | B1->B0 | 2525 2626 | 0 0 | (0 0) (0 0)
1476 12:40:25.207694 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 12:40:25.211098 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 12:40:25.213977 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 12:40:25.221061 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 12:40:25.223974 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 12:40:25.227501 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 12:40:25.233937 0 10 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
1483 12:40:25.237331 0 10 8 | B1->B0 | 2d2d 2c2c | 0 0 | (1 0) (1 0)
1484 12:40:25.240479 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 12:40:25.247148 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 12:40:25.250686 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 12:40:25.253781 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 12:40:25.260635 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 12:40:25.264095 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 12:40:25.267169 0 11 4 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
1491 12:40:25.274036 0 11 8 | B1->B0 | 3737 3a3a | 0 1 | (0 0) (0 0)
1492 12:40:25.277260 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 12:40:25.280764 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 12:40:25.287462 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 12:40:25.290396 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 12:40:25.294010 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 12:40:25.297218 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 12:40:25.303893 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1499 12:40:25.307047 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1500 12:40:25.310311 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 12:40:25.316670 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 12:40:25.320163 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 12:40:25.323671 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 12:40:25.330097 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 12:40:25.333697 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 12:40:25.336760 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 12:40:25.343391 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 12:40:25.346939 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 12:40:25.349972 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 12:40:25.356867 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 12:40:25.359803 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 12:40:25.363431 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 12:40:25.369857 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 12:40:25.373434 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1515 12:40:25.376244 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1516 12:40:25.379592 Total UI for P1: 0, mck2ui 16
1517 12:40:25.383058 best dqsien dly found for B0: ( 0, 14, 4)
1518 12:40:25.386276 Total UI for P1: 0, mck2ui 16
1519 12:40:25.389846 best dqsien dly found for B1: ( 0, 14, 6)
1520 12:40:25.392785 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1521 12:40:25.396372 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1522 12:40:25.396444
1523 12:40:25.403140 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1524 12:40:25.406720 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1525 12:40:25.406819 [Gating] SW calibration Done
1526 12:40:25.409819 ==
1527 12:40:25.412909 Dram Type= 6, Freq= 0, CH_1, rank 0
1528 12:40:25.416293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1529 12:40:25.416369 ==
1530 12:40:25.416430 RX Vref Scan: 0
1531 12:40:25.416488
1532 12:40:25.419762 RX Vref 0 -> 0, step: 1
1533 12:40:25.419844
1534 12:40:25.422699 RX Delay -130 -> 252, step: 16
1535 12:40:25.426213 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1536 12:40:25.429684 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1537 12:40:25.436248 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1538 12:40:25.439221 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1539 12:40:25.442752 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1540 12:40:25.446431 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1541 12:40:25.449503 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1542 12:40:25.456159 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1543 12:40:25.459291 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1544 12:40:25.462756 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1545 12:40:25.466288 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1546 12:40:25.469265 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1547 12:40:25.475725 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1548 12:40:25.479189 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1549 12:40:25.482692 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1550 12:40:25.486143 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1551 12:40:25.486225 ==
1552 12:40:25.488946 Dram Type= 6, Freq= 0, CH_1, rank 0
1553 12:40:25.495651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1554 12:40:25.495750 ==
1555 12:40:25.495832 DQS Delay:
1556 12:40:25.495893 DQS0 = 0, DQS1 = 0
1557 12:40:25.499266 DQM Delay:
1558 12:40:25.499347 DQM0 = 81, DQM1 = 70
1559 12:40:25.502161 DQ Delay:
1560 12:40:25.505713 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1561 12:40:25.509381 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1562 12:40:25.512382 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1563 12:40:25.515458 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1564 12:40:25.515540
1565 12:40:25.515605
1566 12:40:25.515724 ==
1567 12:40:25.519086 Dram Type= 6, Freq= 0, CH_1, rank 0
1568 12:40:25.522600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1569 12:40:25.522683 ==
1570 12:40:25.522748
1571 12:40:25.522836
1572 12:40:25.525606 TX Vref Scan disable
1573 12:40:25.525718 == TX Byte 0 ==
1574 12:40:25.532155 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1575 12:40:25.535681 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1576 12:40:25.535781 == TX Byte 1 ==
1577 12:40:25.542203 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1578 12:40:25.545670 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1579 12:40:25.545767 ==
1580 12:40:25.549154 Dram Type= 6, Freq= 0, CH_1, rank 0
1581 12:40:25.552151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1582 12:40:25.552249 ==
1583 12:40:25.566502 TX Vref=22, minBit 1, minWin=27, winSum=445
1584 12:40:25.569533 TX Vref=24, minBit 1, minWin=27, winSum=443
1585 12:40:25.573275 TX Vref=26, minBit 5, minWin=27, winSum=447
1586 12:40:25.576295 TX Vref=28, minBit 1, minWin=27, winSum=450
1587 12:40:25.579317 TX Vref=30, minBit 5, minWin=27, winSum=450
1588 12:40:25.586410 TX Vref=32, minBit 5, minWin=27, winSum=448
1589 12:40:25.589241 [TxChooseVref] Worse bit 1, Min win 27, Win sum 450, Final Vref 28
1590 12:40:25.589340
1591 12:40:25.592717 Final TX Range 1 Vref 28
1592 12:40:25.592821
1593 12:40:25.592911 ==
1594 12:40:25.596111 Dram Type= 6, Freq= 0, CH_1, rank 0
1595 12:40:25.599686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1596 12:40:25.602991 ==
1597 12:40:25.603064
1598 12:40:25.603142
1599 12:40:25.603215 TX Vref Scan disable
1600 12:40:25.606409 == TX Byte 0 ==
1601 12:40:25.609450 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1602 12:40:25.616183 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1603 12:40:25.616258 == TX Byte 1 ==
1604 12:40:25.619829 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1605 12:40:25.623656 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1606 12:40:25.626676
1607 12:40:25.626772 [DATLAT]
1608 12:40:25.626892 Freq=800, CH1 RK0
1609 12:40:25.626954
1610 12:40:25.629626 DATLAT Default: 0xa
1611 12:40:25.629720 0, 0xFFFF, sum = 0
1612 12:40:25.633118 1, 0xFFFF, sum = 0
1613 12:40:25.633216 2, 0xFFFF, sum = 0
1614 12:40:25.636327 3, 0xFFFF, sum = 0
1615 12:40:25.636423 4, 0xFFFF, sum = 0
1616 12:40:25.639814 5, 0xFFFF, sum = 0
1617 12:40:25.639886 6, 0xFFFF, sum = 0
1618 12:40:25.643232 7, 0xFFFF, sum = 0
1619 12:40:25.646021 8, 0xFFFF, sum = 0
1620 12:40:25.646092 9, 0x0, sum = 1
1621 12:40:25.646157 10, 0x0, sum = 2
1622 12:40:25.649450 11, 0x0, sum = 3
1623 12:40:25.649523 12, 0x0, sum = 4
1624 12:40:25.652925 best_step = 10
1625 12:40:25.652995
1626 12:40:25.653055 ==
1627 12:40:25.655969 Dram Type= 6, Freq= 0, CH_1, rank 0
1628 12:40:25.659510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1629 12:40:25.659581 ==
1630 12:40:25.662580 RX Vref Scan: 1
1631 12:40:25.662650
1632 12:40:25.666270 Set Vref Range= 32 -> 127
1633 12:40:25.666337
1634 12:40:25.666397 RX Vref 32 -> 127, step: 1
1635 12:40:25.666454
1636 12:40:25.669276 RX Delay -111 -> 252, step: 8
1637 12:40:25.669370
1638 12:40:25.672853 Set Vref, RX VrefLevel [Byte0]: 32
1639 12:40:25.675891 [Byte1]: 32
1640 12:40:25.679435
1641 12:40:25.679501 Set Vref, RX VrefLevel [Byte0]: 33
1642 12:40:25.682519 [Byte1]: 33
1643 12:40:25.686681
1644 12:40:25.686793 Set Vref, RX VrefLevel [Byte0]: 34
1645 12:40:25.690170 [Byte1]: 34
1646 12:40:25.694912
1647 12:40:25.694983 Set Vref, RX VrefLevel [Byte0]: 35
1648 12:40:25.697839 [Byte1]: 35
1649 12:40:25.702444
1650 12:40:25.702515 Set Vref, RX VrefLevel [Byte0]: 36
1651 12:40:25.705686 [Byte1]: 36
1652 12:40:25.709790
1653 12:40:25.709886 Set Vref, RX VrefLevel [Byte0]: 37
1654 12:40:25.713357 [Byte1]: 37
1655 12:40:25.717684
1656 12:40:25.717783 Set Vref, RX VrefLevel [Byte0]: 38
1657 12:40:25.720696 [Byte1]: 38
1658 12:40:25.725024
1659 12:40:25.725121 Set Vref, RX VrefLevel [Byte0]: 39
1660 12:40:25.728634 [Byte1]: 39
1661 12:40:25.732941
1662 12:40:25.733036 Set Vref, RX VrefLevel [Byte0]: 40
1663 12:40:25.735917 [Byte1]: 40
1664 12:40:25.740558
1665 12:40:25.740655 Set Vref, RX VrefLevel [Byte0]: 41
1666 12:40:25.743524 [Byte1]: 41
1667 12:40:25.748234
1668 12:40:25.748335 Set Vref, RX VrefLevel [Byte0]: 42
1669 12:40:25.751100 [Byte1]: 42
1670 12:40:25.755479
1671 12:40:25.755589 Set Vref, RX VrefLevel [Byte0]: 43
1672 12:40:25.758779 [Byte1]: 43
1673 12:40:25.763585
1674 12:40:25.763653 Set Vref, RX VrefLevel [Byte0]: 44
1675 12:40:25.766574 [Byte1]: 44
1676 12:40:25.770812
1677 12:40:25.770924 Set Vref, RX VrefLevel [Byte0]: 45
1678 12:40:25.774444 [Byte1]: 45
1679 12:40:25.778592
1680 12:40:25.778687 Set Vref, RX VrefLevel [Byte0]: 46
1681 12:40:25.782191 [Byte1]: 46
1682 12:40:25.786482
1683 12:40:25.786549 Set Vref, RX VrefLevel [Byte0]: 47
1684 12:40:25.789561 [Byte1]: 47
1685 12:40:25.793632
1686 12:40:25.793730 Set Vref, RX VrefLevel [Byte0]: 48
1687 12:40:25.797104 [Byte1]: 48
1688 12:40:25.801686
1689 12:40:25.801783 Set Vref, RX VrefLevel [Byte0]: 49
1690 12:40:25.804875 [Byte1]: 49
1691 12:40:25.809034
1692 12:40:25.809102 Set Vref, RX VrefLevel [Byte0]: 50
1693 12:40:25.812704 [Byte1]: 50
1694 12:40:25.816670
1695 12:40:25.816768 Set Vref, RX VrefLevel [Byte0]: 51
1696 12:40:25.820244 [Byte1]: 51
1697 12:40:25.824508
1698 12:40:25.824606 Set Vref, RX VrefLevel [Byte0]: 52
1699 12:40:25.827613 [Byte1]: 52
1700 12:40:25.832368
1701 12:40:25.832443 Set Vref, RX VrefLevel [Byte0]: 53
1702 12:40:25.835520 [Byte1]: 53
1703 12:40:25.839733
1704 12:40:25.839807 Set Vref, RX VrefLevel [Byte0]: 54
1705 12:40:25.843279 [Byte1]: 54
1706 12:40:25.847281
1707 12:40:25.847352 Set Vref, RX VrefLevel [Byte0]: 55
1708 12:40:25.850704 [Byte1]: 55
1709 12:40:25.854799
1710 12:40:25.854887 Set Vref, RX VrefLevel [Byte0]: 56
1711 12:40:25.858124 [Byte1]: 56
1712 12:40:25.862696
1713 12:40:25.862806 Set Vref, RX VrefLevel [Byte0]: 57
1714 12:40:25.866169 [Byte1]: 57
1715 12:40:25.870554
1716 12:40:25.870651 Set Vref, RX VrefLevel [Byte0]: 58
1717 12:40:25.873568 [Byte1]: 58
1718 12:40:25.877911
1719 12:40:25.878005 Set Vref, RX VrefLevel [Byte0]: 59
1720 12:40:25.881465 [Byte1]: 59
1721 12:40:25.885647
1722 12:40:25.885740 Set Vref, RX VrefLevel [Byte0]: 60
1723 12:40:25.888717 [Byte1]: 60
1724 12:40:25.893590
1725 12:40:25.893687 Set Vref, RX VrefLevel [Byte0]: 61
1726 12:40:25.896638 [Byte1]: 61
1727 12:40:25.900842
1728 12:40:25.900916 Set Vref, RX VrefLevel [Byte0]: 62
1729 12:40:25.904099 [Byte1]: 62
1730 12:40:25.908724
1731 12:40:25.908801 Set Vref, RX VrefLevel [Byte0]: 63
1732 12:40:25.912280 [Byte1]: 63
1733 12:40:25.916260
1734 12:40:25.916358 Set Vref, RX VrefLevel [Byte0]: 64
1735 12:40:25.919554 [Byte1]: 64
1736 12:40:25.924174
1737 12:40:25.924273 Set Vref, RX VrefLevel [Byte0]: 65
1738 12:40:25.927181 [Byte1]: 65
1739 12:40:25.931329
1740 12:40:25.931424 Set Vref, RX VrefLevel [Byte0]: 66
1741 12:40:25.934921 [Byte1]: 66
1742 12:40:25.939183
1743 12:40:25.939262 Set Vref, RX VrefLevel [Byte0]: 67
1744 12:40:25.942729 [Byte1]: 67
1745 12:40:25.947054
1746 12:40:25.947122 Set Vref, RX VrefLevel [Byte0]: 68
1747 12:40:25.950001 [Byte1]: 68
1748 12:40:25.954691
1749 12:40:25.954861 Set Vref, RX VrefLevel [Byte0]: 69
1750 12:40:25.957807 [Byte1]: 69
1751 12:40:25.962477
1752 12:40:25.962578 Set Vref, RX VrefLevel [Byte0]: 70
1753 12:40:25.965172 [Byte1]: 70
1754 12:40:25.969523
1755 12:40:25.969599 Set Vref, RX VrefLevel [Byte0]: 71
1756 12:40:25.973055 [Byte1]: 71
1757 12:40:25.977331
1758 12:40:25.977431 Set Vref, RX VrefLevel [Byte0]: 72
1759 12:40:25.980967 [Byte1]: 72
1760 12:40:25.985130
1761 12:40:25.985229 Set Vref, RX VrefLevel [Byte0]: 73
1762 12:40:25.988672 [Byte1]: 73
1763 12:40:25.992981
1764 12:40:25.993088 Set Vref, RX VrefLevel [Byte0]: 74
1765 12:40:25.996003 [Byte1]: 74
1766 12:40:26.000631
1767 12:40:26.000704 Final RX Vref Byte 0 = 59 to rank0
1768 12:40:26.003692 Final RX Vref Byte 1 = 55 to rank0
1769 12:40:26.007217 Final RX Vref Byte 0 = 59 to rank1
1770 12:40:26.010251 Final RX Vref Byte 1 = 55 to rank1==
1771 12:40:26.013613 Dram Type= 6, Freq= 0, CH_1, rank 0
1772 12:40:26.020008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1773 12:40:26.020114 ==
1774 12:40:26.020209 DQS Delay:
1775 12:40:26.023411 DQS0 = 0, DQS1 = 0
1776 12:40:26.023487 DQM Delay:
1777 12:40:26.023549 DQM0 = 81, DQM1 = 71
1778 12:40:26.027072 DQ Delay:
1779 12:40:26.030076 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1780 12:40:26.033605 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1781 12:40:26.033705 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1782 12:40:26.040048 DQ12 =80, DQ13 =76, DQ14 =80, DQ15 =76
1783 12:40:26.040126
1784 12:40:26.040189
1785 12:40:26.046710 [DQSOSCAuto] RK0, (LSB)MR18= 0xc16, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 406 ps
1786 12:40:26.050438 CH1 RK0: MR19=606, MR18=C16
1787 12:40:26.056497 CH1_RK0: MR19=0x606, MR18=0xC16, DQSOSC=404, MR23=63, INC=90, DEC=60
1788 12:40:26.056568
1789 12:40:26.060129 ----->DramcWriteLeveling(PI) begin...
1790 12:40:26.060204 ==
1791 12:40:26.063518 Dram Type= 6, Freq= 0, CH_1, rank 1
1792 12:40:26.066890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1793 12:40:26.066999 ==
1794 12:40:26.069874 Write leveling (Byte 0): 27 => 27
1795 12:40:26.073189 Write leveling (Byte 1): 27 => 27
1796 12:40:26.076874 DramcWriteLeveling(PI) end<-----
1797 12:40:26.076950
1798 12:40:26.077014 ==
1799 12:40:26.079745 Dram Type= 6, Freq= 0, CH_1, rank 1
1800 12:40:26.083227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1801 12:40:26.083303 ==
1802 12:40:26.086233 [Gating] SW mode calibration
1803 12:40:26.093185 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1804 12:40:26.099611 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1805 12:40:26.103358 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1806 12:40:26.106377 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1807 12:40:26.113064 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 12:40:26.116495 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 12:40:26.119419 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 12:40:26.126254 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 12:40:26.129650 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 12:40:26.133062 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 12:40:26.139847 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 12:40:26.142701 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 12:40:26.145988 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 12:40:26.152636 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 12:40:26.156320 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 12:40:26.159337 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 12:40:26.166018 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 12:40:26.169638 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 12:40:26.172568 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 12:40:26.179379 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1823 12:40:26.182627 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1824 12:40:26.185949 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 12:40:26.192457 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 12:40:26.196091 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 12:40:26.199094 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 12:40:26.205769 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 12:40:26.209348 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 12:40:26.212569 0 9 4 | B1->B0 | 2323 2e2e | 0 0 | (1 1) (0 0)
1831 12:40:26.219265 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1832 12:40:26.222169 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 12:40:26.225614 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 12:40:26.232172 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 12:40:26.235597 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 12:40:26.239241 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 12:40:26.245515 0 10 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
1838 12:40:26.248981 0 10 4 | B1->B0 | 3333 2e2e | 0 1 | (0 1) (1 1)
1839 12:40:26.252155 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
1840 12:40:26.259231 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 12:40:26.262306 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 12:40:26.265349 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 12:40:26.269022 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 12:40:26.275656 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 12:40:26.278615 0 11 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1846 12:40:26.281916 0 11 4 | B1->B0 | 2a2a 3b3b | 0 0 | (0 0) (0 0)
1847 12:40:26.288546 0 11 8 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
1848 12:40:26.291867 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 12:40:26.295171 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 12:40:26.301906 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 12:40:26.305522 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 12:40:26.308498 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 12:40:26.315122 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1854 12:40:26.318668 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1855 12:40:26.321776 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1856 12:40:26.328768 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 12:40:26.331753 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 12:40:26.335240 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 12:40:26.341669 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 12:40:26.345424 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 12:40:26.348355 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 12:40:26.354967 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 12:40:26.358434 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 12:40:26.361666 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 12:40:26.368199 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 12:40:26.372062 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 12:40:26.375060 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 12:40:26.381653 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 12:40:26.384643 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 12:40:26.388242 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1871 12:40:26.394542 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1872 12:40:26.394647 Total UI for P1: 0, mck2ui 16
1873 12:40:26.401294 best dqsien dly found for B0: ( 0, 14, 4)
1874 12:40:26.401373 Total UI for P1: 0, mck2ui 16
1875 12:40:26.407946 best dqsien dly found for B1: ( 0, 14, 4)
1876 12:40:26.411180 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1877 12:40:26.414790 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1878 12:40:26.414945
1879 12:40:26.417947 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1880 12:40:26.421008 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1881 12:40:26.424518 [Gating] SW calibration Done
1882 12:40:26.424606 ==
1883 12:40:26.428228 Dram Type= 6, Freq= 0, CH_1, rank 1
1884 12:40:26.431223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1885 12:40:26.431296 ==
1886 12:40:26.434282 RX Vref Scan: 0
1887 12:40:26.434379
1888 12:40:26.434467 RX Vref 0 -> 0, step: 1
1889 12:40:26.434561
1890 12:40:26.437784 RX Delay -130 -> 252, step: 16
1891 12:40:26.441229 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1892 12:40:26.447768 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1893 12:40:26.450663 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1894 12:40:26.454541 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1895 12:40:26.457455 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1896 12:40:26.461033 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1897 12:40:26.467825 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1898 12:40:26.470721 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1899 12:40:26.474277 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1900 12:40:26.477265 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1901 12:40:26.480798 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1902 12:40:26.487530 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1903 12:40:26.490550 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1904 12:40:26.494194 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1905 12:40:26.497071 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1906 12:40:26.503993 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1907 12:40:26.504093 ==
1908 12:40:26.507050 Dram Type= 6, Freq= 0, CH_1, rank 1
1909 12:40:26.510395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1910 12:40:26.510508 ==
1911 12:40:26.510637 DQS Delay:
1912 12:40:26.513783 DQS0 = 0, DQS1 = 0
1913 12:40:26.513854 DQM Delay:
1914 12:40:26.517212 DQM0 = 80, DQM1 = 71
1915 12:40:26.517284 DQ Delay:
1916 12:40:26.520756 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1917 12:40:26.523800 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1918 12:40:26.527421 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1919 12:40:26.530491 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1920 12:40:26.530587
1921 12:40:26.530668
1922 12:40:26.530730 ==
1923 12:40:26.534088 Dram Type= 6, Freq= 0, CH_1, rank 1
1924 12:40:26.537088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1925 12:40:26.537172 ==
1926 12:40:26.537239
1927 12:40:26.537300
1928 12:40:26.540680 TX Vref Scan disable
1929 12:40:26.544030 == TX Byte 0 ==
1930 12:40:26.546999 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1931 12:40:26.550502 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1932 12:40:26.553914 == TX Byte 1 ==
1933 12:40:26.556976 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1934 12:40:26.560515 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1935 12:40:26.560598 ==
1936 12:40:26.563715 Dram Type= 6, Freq= 0, CH_1, rank 1
1937 12:40:26.570178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1938 12:40:26.570261 ==
1939 12:40:26.582035 TX Vref=22, minBit 7, minWin=27, winSum=450
1940 12:40:26.584975 TX Vref=24, minBit 0, minWin=28, winSum=454
1941 12:40:26.588577 TX Vref=26, minBit 1, minWin=28, winSum=457
1942 12:40:26.591604 TX Vref=28, minBit 1, minWin=28, winSum=460
1943 12:40:26.595286 TX Vref=30, minBit 1, minWin=28, winSum=459
1944 12:40:26.601805 TX Vref=32, minBit 1, minWin=27, winSum=455
1945 12:40:26.604801 [TxChooseVref] Worse bit 1, Min win 28, Win sum 460, Final Vref 28
1946 12:40:26.604911
1947 12:40:26.608272 Final TX Range 1 Vref 28
1948 12:40:26.608355
1949 12:40:26.608420 ==
1950 12:40:26.611576 Dram Type= 6, Freq= 0, CH_1, rank 1
1951 12:40:26.615061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1952 12:40:26.618313 ==
1953 12:40:26.618400
1954 12:40:26.618465
1955 12:40:26.618525 TX Vref Scan disable
1956 12:40:26.621684 == TX Byte 0 ==
1957 12:40:26.625044 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1958 12:40:26.631800 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1959 12:40:26.631883 == TX Byte 1 ==
1960 12:40:26.634812 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1961 12:40:26.641526 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1962 12:40:26.641609
1963 12:40:26.641675 [DATLAT]
1964 12:40:26.641736 Freq=800, CH1 RK1
1965 12:40:26.641796
1966 12:40:26.644561 DATLAT Default: 0xa
1967 12:40:26.644643 0, 0xFFFF, sum = 0
1968 12:40:26.648594 1, 0xFFFF, sum = 0
1969 12:40:26.651138 2, 0xFFFF, sum = 0
1970 12:40:26.651222 3, 0xFFFF, sum = 0
1971 12:40:26.654589 4, 0xFFFF, sum = 0
1972 12:40:26.654672 5, 0xFFFF, sum = 0
1973 12:40:26.657980 6, 0xFFFF, sum = 0
1974 12:40:26.658092 7, 0xFFFF, sum = 0
1975 12:40:26.661510 8, 0xFFFF, sum = 0
1976 12:40:26.661594 9, 0x0, sum = 1
1977 12:40:26.664607 10, 0x0, sum = 2
1978 12:40:26.664691 11, 0x0, sum = 3
1979 12:40:26.664757 12, 0x0, sum = 4
1980 12:40:26.667711 best_step = 10
1981 12:40:26.667794
1982 12:40:26.667860 ==
1983 12:40:26.671518 Dram Type= 6, Freq= 0, CH_1, rank 1
1984 12:40:26.674454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1985 12:40:26.674583 ==
1986 12:40:26.678002 RX Vref Scan: 0
1987 12:40:26.678084
1988 12:40:26.678149 RX Vref 0 -> 0, step: 1
1989 12:40:26.681545
1990 12:40:26.681627 RX Delay -111 -> 252, step: 8
1991 12:40:26.688136 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1992 12:40:26.691894 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
1993 12:40:26.694796 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
1994 12:40:26.698384 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1995 12:40:26.705065 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
1996 12:40:26.708114 iDelay=209, Bit 5, Center 84 (-39 ~ 208) 248
1997 12:40:26.711704 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1998 12:40:26.714695 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
1999 12:40:26.718002 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2000 12:40:26.721573 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2001 12:40:26.728125 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2002 12:40:26.731555 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2003 12:40:26.734395 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2004 12:40:26.737997 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2005 12:40:26.744661 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2006 12:40:26.747711 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2007 12:40:26.747785 ==
2008 12:40:26.751337 Dram Type= 6, Freq= 0, CH_1, rank 1
2009 12:40:26.754425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2010 12:40:26.754543 ==
2011 12:40:26.757974 DQS Delay:
2012 12:40:26.758068 DQS0 = 0, DQS1 = 0
2013 12:40:26.758148 DQM Delay:
2014 12:40:26.761252 DQM0 = 77, DQM1 = 73
2015 12:40:26.761354 DQ Delay:
2016 12:40:26.764467 DQ0 =80, DQ1 =72, DQ2 =68, DQ3 =72
2017 12:40:26.767954 DQ4 =76, DQ5 =84, DQ6 =88, DQ7 =76
2018 12:40:26.771008 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
2019 12:40:26.774635 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2020 12:40:26.774717
2021 12:40:26.774781
2022 12:40:26.784654 [DQSOSCAuto] RK1, (LSB)MR18= 0x223a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2023 12:40:26.784737 CH1 RK1: MR19=606, MR18=223A
2024 12:40:26.791134 CH1_RK1: MR19=0x606, MR18=0x223A, DQSOSC=395, MR23=63, INC=94, DEC=63
2025 12:40:26.794101 [RxdqsGatingPostProcess] freq 800
2026 12:40:26.800721 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2027 12:40:26.804321 Pre-setting of DQS Precalculation
2028 12:40:26.807861 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2029 12:40:26.814352 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2030 12:40:26.824260 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2031 12:40:26.824343
2032 12:40:26.824411
2033 12:40:26.827728 [Calibration Summary] 1600 Mbps
2034 12:40:26.827817 CH 0, Rank 0
2035 12:40:26.830455 SW Impedance : PASS
2036 12:40:26.830536 DUTY Scan : NO K
2037 12:40:26.833790 ZQ Calibration : PASS
2038 12:40:26.837135 Jitter Meter : NO K
2039 12:40:26.837218 CBT Training : PASS
2040 12:40:26.840641 Write leveling : PASS
2041 12:40:26.843660 RX DQS gating : PASS
2042 12:40:26.843742 RX DQ/DQS(RDDQC) : PASS
2043 12:40:26.847253 TX DQ/DQS : PASS
2044 12:40:26.850328 RX DATLAT : PASS
2045 12:40:26.850409 RX DQ/DQS(Engine): PASS
2046 12:40:26.853939 TX OE : NO K
2047 12:40:26.854037 All Pass.
2048 12:40:26.854129
2049 12:40:26.857026 CH 0, Rank 1
2050 12:40:26.857107 SW Impedance : PASS
2051 12:40:26.860658 DUTY Scan : NO K
2052 12:40:26.860740 ZQ Calibration : PASS
2053 12:40:26.864184 Jitter Meter : NO K
2054 12:40:26.867180 CBT Training : PASS
2055 12:40:26.867261 Write leveling : PASS
2056 12:40:26.870567 RX DQS gating : PASS
2057 12:40:26.873909 RX DQ/DQS(RDDQC) : PASS
2058 12:40:26.873991 TX DQ/DQS : PASS
2059 12:40:26.877558 RX DATLAT : PASS
2060 12:40:26.880443 RX DQ/DQS(Engine): PASS
2061 12:40:26.880545 TX OE : NO K
2062 12:40:26.883793 All Pass.
2063 12:40:26.883865
2064 12:40:26.883926 CH 1, Rank 0
2065 12:40:26.886737 SW Impedance : PASS
2066 12:40:26.886808 DUTY Scan : NO K
2067 12:40:26.890488 ZQ Calibration : PASS
2068 12:40:26.893913 Jitter Meter : NO K
2069 12:40:26.893995 CBT Training : PASS
2070 12:40:26.896934 Write leveling : PASS
2071 12:40:26.900244 RX DQS gating : PASS
2072 12:40:26.900345 RX DQ/DQS(RDDQC) : PASS
2073 12:40:26.904000 TX DQ/DQS : PASS
2074 12:40:26.904083 RX DATLAT : PASS
2075 12:40:26.907024 RX DQ/DQS(Engine): PASS
2076 12:40:26.910040 TX OE : NO K
2077 12:40:26.910122 All Pass.
2078 12:40:26.910187
2079 12:40:26.910246 CH 1, Rank 1
2080 12:40:26.913556 SW Impedance : PASS
2081 12:40:26.916525 DUTY Scan : NO K
2082 12:40:26.916606 ZQ Calibration : PASS
2083 12:40:26.920124 Jitter Meter : NO K
2084 12:40:26.923178 CBT Training : PASS
2085 12:40:26.923260 Write leveling : PASS
2086 12:40:26.926767 RX DQS gating : PASS
2087 12:40:26.930061 RX DQ/DQS(RDDQC) : PASS
2088 12:40:26.930157 TX DQ/DQS : PASS
2089 12:40:26.933525 RX DATLAT : PASS
2090 12:40:26.936436 RX DQ/DQS(Engine): PASS
2091 12:40:26.936517 TX OE : NO K
2092 12:40:26.939891 All Pass.
2093 12:40:26.939972
2094 12:40:26.940036 DramC Write-DBI off
2095 12:40:26.943034 PER_BANK_REFRESH: Hybrid Mode
2096 12:40:26.943116 TX_TRACKING: ON
2097 12:40:26.946797 [GetDramInforAfterCalByMRR] Vendor 6.
2098 12:40:26.953089 [GetDramInforAfterCalByMRR] Revision 606.
2099 12:40:26.956638 [GetDramInforAfterCalByMRR] Revision 2 0.
2100 12:40:26.956735 MR0 0x3b3b
2101 12:40:26.956802 MR8 0x5151
2102 12:40:26.959771 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2103 12:40:26.963335
2104 12:40:26.963416 MR0 0x3b3b
2105 12:40:26.963480 MR8 0x5151
2106 12:40:26.966329 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2107 12:40:26.966453
2108 12:40:26.976505 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2109 12:40:26.979949 [FAST_K] Save calibration result to emmc
2110 12:40:26.983075 [FAST_K] Save calibration result to emmc
2111 12:40:26.986501 dram_init: config_dvfs: 1
2112 12:40:26.989483 dramc_set_vcore_voltage set vcore to 662500
2113 12:40:26.992481 Read voltage for 1200, 2
2114 12:40:26.992562 Vio18 = 0
2115 12:40:26.992627 Vcore = 662500
2116 12:40:26.996109 Vdram = 0
2117 12:40:26.996212 Vddq = 0
2118 12:40:26.996319 Vmddr = 0
2119 12:40:27.003246 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2120 12:40:27.005908 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2121 12:40:27.009537 MEM_TYPE=3, freq_sel=15
2122 12:40:27.012554 sv_algorithm_assistance_LP4_1600
2123 12:40:27.015984 ============ PULL DRAM RESETB DOWN ============
2124 12:40:27.019526 ========== PULL DRAM RESETB DOWN end =========
2125 12:40:27.026193 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2126 12:40:27.029235 ===================================
2127 12:40:27.032813 LPDDR4 DRAM CONFIGURATION
2128 12:40:27.035781 ===================================
2129 12:40:27.035870 EX_ROW_EN[0] = 0x0
2130 12:40:27.039160 EX_ROW_EN[1] = 0x0
2131 12:40:27.039241 LP4Y_EN = 0x0
2132 12:40:27.042679 WORK_FSP = 0x0
2133 12:40:27.042761 WL = 0x4
2134 12:40:27.046138 RL = 0x4
2135 12:40:27.046220 BL = 0x2
2136 12:40:27.049641 RPST = 0x0
2137 12:40:27.049723 RD_PRE = 0x0
2138 12:40:27.052518 WR_PRE = 0x1
2139 12:40:27.052625 WR_PST = 0x0
2140 12:40:27.056180 DBI_WR = 0x0
2141 12:40:27.056263 DBI_RD = 0x0
2142 12:40:27.059295 OTF = 0x1
2143 12:40:27.062465 ===================================
2144 12:40:27.066024 ===================================
2145 12:40:27.066106 ANA top config
2146 12:40:27.069143 ===================================
2147 12:40:27.072681 DLL_ASYNC_EN = 0
2148 12:40:27.075691 ALL_SLAVE_EN = 0
2149 12:40:27.079491 NEW_RANK_MODE = 1
2150 12:40:27.079574 DLL_IDLE_MODE = 1
2151 12:40:27.082365 LP45_APHY_COMB_EN = 1
2152 12:40:27.085792 TX_ODT_DIS = 1
2153 12:40:27.089267 NEW_8X_MODE = 1
2154 12:40:27.092488 ===================================
2155 12:40:27.095753 ===================================
2156 12:40:27.098947 data_rate = 2400
2157 12:40:27.099021 CKR = 1
2158 12:40:27.102634 DQ_P2S_RATIO = 8
2159 12:40:27.105520 ===================================
2160 12:40:27.109078 CA_P2S_RATIO = 8
2161 12:40:27.112986 DQ_CA_OPEN = 0
2162 12:40:27.115778 DQ_SEMI_OPEN = 0
2163 12:40:27.119340 CA_SEMI_OPEN = 0
2164 12:40:27.119423 CA_FULL_RATE = 0
2165 12:40:27.122238 DQ_CKDIV4_EN = 0
2166 12:40:27.125787 CA_CKDIV4_EN = 0
2167 12:40:27.128874 CA_PREDIV_EN = 0
2168 12:40:27.132546 PH8_DLY = 17
2169 12:40:27.135565 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2170 12:40:27.135648 DQ_AAMCK_DIV = 4
2171 12:40:27.139208 CA_AAMCK_DIV = 4
2172 12:40:27.141976 CA_ADMCK_DIV = 4
2173 12:40:27.145385 DQ_TRACK_CA_EN = 0
2174 12:40:27.148762 CA_PICK = 1200
2175 12:40:27.152523 CA_MCKIO = 1200
2176 12:40:27.155577 MCKIO_SEMI = 0
2177 12:40:27.158953 PLL_FREQ = 2366
2178 12:40:27.159036 DQ_UI_PI_RATIO = 32
2179 12:40:27.161834 CA_UI_PI_RATIO = 0
2180 12:40:27.165445 ===================================
2181 12:40:27.168461 ===================================
2182 12:40:27.172050 memory_type:LPDDR4
2183 12:40:27.175137 GP_NUM : 10
2184 12:40:27.175223 SRAM_EN : 1
2185 12:40:27.178688 MD32_EN : 0
2186 12:40:27.181779 ===================================
2187 12:40:27.185031 [ANA_INIT] >>>>>>>>>>>>>>
2188 12:40:27.185115 <<<<<< [CONFIGURE PHASE]: ANA_TX
2189 12:40:27.188642 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2190 12:40:27.192247 ===================================
2191 12:40:27.195192 data_rate = 2400,PCW = 0X5b00
2192 12:40:27.198647 ===================================
2193 12:40:27.201850 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2194 12:40:27.208236 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2195 12:40:27.214732 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2196 12:40:27.218166 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2197 12:40:27.221693 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2198 12:40:27.224627 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2199 12:40:27.228152 [ANA_INIT] flow start
2200 12:40:27.228233 [ANA_INIT] PLL >>>>>>>>
2201 12:40:27.231740 [ANA_INIT] PLL <<<<<<<<
2202 12:40:27.234752 [ANA_INIT] MIDPI >>>>>>>>
2203 12:40:27.237735 [ANA_INIT] MIDPI <<<<<<<<
2204 12:40:27.237816 [ANA_INIT] DLL >>>>>>>>
2205 12:40:27.241345 [ANA_INIT] DLL <<<<<<<<
2206 12:40:27.241425 [ANA_INIT] flow end
2207 12:40:27.247779 ============ LP4 DIFF to SE enter ============
2208 12:40:27.251158 ============ LP4 DIFF to SE exit ============
2209 12:40:27.254916 [ANA_INIT] <<<<<<<<<<<<<
2210 12:40:27.257988 [Flow] Enable top DCM control >>>>>
2211 12:40:27.261206 [Flow] Enable top DCM control <<<<<
2212 12:40:27.261288 Enable DLL master slave shuffle
2213 12:40:27.268137 ==============================================================
2214 12:40:27.271136 Gating Mode config
2215 12:40:27.274800 ==============================================================
2216 12:40:27.277850 Config description:
2217 12:40:27.288084 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2218 12:40:27.294610 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2219 12:40:27.297730 SELPH_MODE 0: By rank 1: By Phase
2220 12:40:27.304302 ==============================================================
2221 12:40:27.307690 GAT_TRACK_EN = 1
2222 12:40:27.310954 RX_GATING_MODE = 2
2223 12:40:27.314224 RX_GATING_TRACK_MODE = 2
2224 12:40:27.317914 SELPH_MODE = 1
2225 12:40:27.318024 PICG_EARLY_EN = 1
2226 12:40:27.320863 VALID_LAT_VALUE = 1
2227 12:40:27.327527 ==============================================================
2228 12:40:27.330913 Enter into Gating configuration >>>>
2229 12:40:27.334476 Exit from Gating configuration <<<<
2230 12:40:27.337580 Enter into DVFS_PRE_config >>>>>
2231 12:40:27.347950 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2232 12:40:27.350850 Exit from DVFS_PRE_config <<<<<
2233 12:40:27.354490 Enter into PICG configuration >>>>
2234 12:40:27.357441 Exit from PICG configuration <<<<
2235 12:40:27.360902 [RX_INPUT] configuration >>>>>
2236 12:40:27.364252 [RX_INPUT] configuration <<<<<
2237 12:40:27.367358 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2238 12:40:27.373939 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2239 12:40:27.380726 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2240 12:40:27.387489 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2241 12:40:27.394226 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2242 12:40:27.400969 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2243 12:40:27.403821 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2244 12:40:27.407484 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2245 12:40:27.411092 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2246 12:40:27.417189 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2247 12:40:27.420762 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2248 12:40:27.423754 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2249 12:40:27.427427 ===================================
2250 12:40:27.430405 LPDDR4 DRAM CONFIGURATION
2251 12:40:27.433854 ===================================
2252 12:40:27.433936 EX_ROW_EN[0] = 0x0
2253 12:40:27.436801 EX_ROW_EN[1] = 0x0
2254 12:40:27.436883 LP4Y_EN = 0x0
2255 12:40:27.440232 WORK_FSP = 0x0
2256 12:40:27.440314 WL = 0x4
2257 12:40:27.443733 RL = 0x4
2258 12:40:27.447349 BL = 0x2
2259 12:40:27.447431 RPST = 0x0
2260 12:40:27.450409 RD_PRE = 0x0
2261 12:40:27.450491 WR_PRE = 0x1
2262 12:40:27.454023 WR_PST = 0x0
2263 12:40:27.454106 DBI_WR = 0x0
2264 12:40:27.456983 DBI_RD = 0x0
2265 12:40:27.457066 OTF = 0x1
2266 12:40:27.460130 ===================================
2267 12:40:27.463777 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2268 12:40:27.470170 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2269 12:40:27.473601 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2270 12:40:27.477068 ===================================
2271 12:40:27.480369 LPDDR4 DRAM CONFIGURATION
2272 12:40:27.483701 ===================================
2273 12:40:27.483784 EX_ROW_EN[0] = 0x10
2274 12:40:27.487151 EX_ROW_EN[1] = 0x0
2275 12:40:27.487233 LP4Y_EN = 0x0
2276 12:40:27.490148 WORK_FSP = 0x0
2277 12:40:27.490231 WL = 0x4
2278 12:40:27.493333 RL = 0x4
2279 12:40:27.493415 BL = 0x2
2280 12:40:27.496941 RPST = 0x0
2281 12:40:27.499873 RD_PRE = 0x0
2282 12:40:27.499955 WR_PRE = 0x1
2283 12:40:27.503510 WR_PST = 0x0
2284 12:40:27.503592 DBI_WR = 0x0
2285 12:40:27.506546 DBI_RD = 0x0
2286 12:40:27.506629 OTF = 0x1
2287 12:40:27.510141 ===================================
2288 12:40:27.516575 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2289 12:40:27.516658 ==
2290 12:40:27.520067 Dram Type= 6, Freq= 0, CH_0, rank 0
2291 12:40:27.523084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2292 12:40:27.523168 ==
2293 12:40:27.526607 [Duty_Offset_Calibration]
2294 12:40:27.529595 B0:2 B1:0 CA:3
2295 12:40:27.529676
2296 12:40:27.533232 [DutyScan_Calibration_Flow] k_type=0
2297 12:40:27.541080
2298 12:40:27.541160 ==CLK 0==
2299 12:40:27.544647 Final CLK duty delay cell = 0
2300 12:40:27.547490 [0] MAX Duty = 5062%(X100), DQS PI = 20
2301 12:40:27.551006 [0] MIN Duty = 4875%(X100), DQS PI = 58
2302 12:40:27.551087 [0] AVG Duty = 4968%(X100)
2303 12:40:27.554575
2304 12:40:27.557443 CH0 CLK Duty spec in!! Max-Min= 187%
2305 12:40:27.561045 [DutyScan_Calibration_Flow] ====Done====
2306 12:40:27.561126
2307 12:40:27.564158 [DutyScan_Calibration_Flow] k_type=1
2308 12:40:27.579530
2309 12:40:27.579611 ==DQS 0 ==
2310 12:40:27.582982 Final DQS duty delay cell = 0
2311 12:40:27.586338 [0] MAX Duty = 5062%(X100), DQS PI = 12
2312 12:40:27.589667 [0] MIN Duty = 4907%(X100), DQS PI = 46
2313 12:40:27.589774 [0] AVG Duty = 4984%(X100)
2314 12:40:27.593047
2315 12:40:27.593128 ==DQS 1 ==
2316 12:40:27.596079 Final DQS duty delay cell = -4
2317 12:40:27.599764 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2318 12:40:27.602795 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2319 12:40:27.606370 [-4] AVG Duty = 4922%(X100)
2320 12:40:27.606453
2321 12:40:27.609487 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2322 12:40:27.609600
2323 12:40:27.612591 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2324 12:40:27.616202 [DutyScan_Calibration_Flow] ====Done====
2325 12:40:27.616283
2326 12:40:27.619136 [DutyScan_Calibration_Flow] k_type=3
2327 12:40:27.637000
2328 12:40:27.637082 ==DQM 0 ==
2329 12:40:27.640643 Final DQM duty delay cell = 0
2330 12:40:27.643713 [0] MAX Duty = 5124%(X100), DQS PI = 28
2331 12:40:27.647322 [0] MIN Duty = 4876%(X100), DQS PI = 0
2332 12:40:27.647403 [0] AVG Duty = 5000%(X100)
2333 12:40:27.650428
2334 12:40:27.650509 ==DQM 1 ==
2335 12:40:27.653991 Final DQM duty delay cell = 4
2336 12:40:27.657349 [4] MAX Duty = 5124%(X100), DQS PI = 50
2337 12:40:27.660662 [4] MIN Duty = 5000%(X100), DQS PI = 14
2338 12:40:27.663727 [4] AVG Duty = 5062%(X100)
2339 12:40:27.663808
2340 12:40:27.667403 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2341 12:40:27.667485
2342 12:40:27.670485 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2343 12:40:27.673489 [DutyScan_Calibration_Flow] ====Done====
2344 12:40:27.673571
2345 12:40:27.676886 [DutyScan_Calibration_Flow] k_type=2
2346 12:40:27.692304
2347 12:40:27.692386 ==DQ 0 ==
2348 12:40:27.695211 Final DQ duty delay cell = -4
2349 12:40:27.698543 [-4] MAX Duty = 5000%(X100), DQS PI = 10
2350 12:40:27.702023 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2351 12:40:27.705043 [-4] AVG Duty = 4953%(X100)
2352 12:40:27.705123
2353 12:40:27.705188 ==DQ 1 ==
2354 12:40:27.708546 Final DQ duty delay cell = -4
2355 12:40:27.712095 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2356 12:40:27.715090 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2357 12:40:27.718710 [-4] AVG Duty = 4922%(X100)
2358 12:40:27.718791
2359 12:40:27.721863 CH0 DQ 0 Duty spec in!! Max-Min= 93%
2360 12:40:27.721944
2361 12:40:27.725269 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2362 12:40:27.728157 [DutyScan_Calibration_Flow] ====Done====
2363 12:40:27.728238 ==
2364 12:40:27.731700 Dram Type= 6, Freq= 0, CH_1, rank 0
2365 12:40:27.735371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2366 12:40:27.735456 ==
2367 12:40:27.738223 [Duty_Offset_Calibration]
2368 12:40:27.738305 B0:1 B1:-2 CA:0
2369 12:40:27.741779
2370 12:40:27.741864 [DutyScan_Calibration_Flow] k_type=0
2371 12:40:27.752592
2372 12:40:27.752674 ==CLK 0==
2373 12:40:27.755641 Final CLK duty delay cell = 0
2374 12:40:27.759231 [0] MAX Duty = 5031%(X100), DQS PI = 16
2375 12:40:27.762098 [0] MIN Duty = 4876%(X100), DQS PI = 58
2376 12:40:27.765590 [0] AVG Duty = 4953%(X100)
2377 12:40:27.765672
2378 12:40:27.768771 CH1 CLK Duty spec in!! Max-Min= 155%
2379 12:40:27.772307 [DutyScan_Calibration_Flow] ====Done====
2380 12:40:27.772420
2381 12:40:27.775283 [DutyScan_Calibration_Flow] k_type=1
2382 12:40:27.790649
2383 12:40:27.790731 ==DQS 0 ==
2384 12:40:27.794039 Final DQS duty delay cell = -4
2385 12:40:27.797615 [-4] MAX Duty = 5000%(X100), DQS PI = 24
2386 12:40:27.801024 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2387 12:40:27.803819 [-4] AVG Duty = 4953%(X100)
2388 12:40:27.803900
2389 12:40:27.803965 ==DQS 1 ==
2390 12:40:27.807206 Final DQS duty delay cell = 0
2391 12:40:27.810798 [0] MAX Duty = 5093%(X100), DQS PI = 0
2392 12:40:27.813811 [0] MIN Duty = 4875%(X100), DQS PI = 26
2393 12:40:27.817470 [0] AVG Duty = 4984%(X100)
2394 12:40:27.817552
2395 12:40:27.820575 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2396 12:40:27.820658
2397 12:40:27.823639 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2398 12:40:27.827254 [DutyScan_Calibration_Flow] ====Done====
2399 12:40:27.827335
2400 12:40:27.830582 [DutyScan_Calibration_Flow] k_type=3
2401 12:40:27.847698
2402 12:40:27.847781 ==DQM 0 ==
2403 12:40:27.850669 Final DQM duty delay cell = 0
2404 12:40:27.854161 [0] MAX Duty = 5000%(X100), DQS PI = 22
2405 12:40:27.857201 [0] MIN Duty = 4844%(X100), DQS PI = 52
2406 12:40:27.860869 [0] AVG Duty = 4922%(X100)
2407 12:40:27.860951
2408 12:40:27.861015 ==DQM 1 ==
2409 12:40:27.863772 Final DQM duty delay cell = 0
2410 12:40:27.867246 [0] MAX Duty = 5031%(X100), DQS PI = 36
2411 12:40:27.870766 [0] MIN Duty = 4907%(X100), DQS PI = 2
2412 12:40:27.873671 [0] AVG Duty = 4969%(X100)
2413 12:40:27.873790
2414 12:40:27.877277 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2415 12:40:27.877358
2416 12:40:27.880261 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2417 12:40:27.883876 [DutyScan_Calibration_Flow] ====Done====
2418 12:40:27.883958
2419 12:40:27.887258 [DutyScan_Calibration_Flow] k_type=2
2420 12:40:27.904014
2421 12:40:27.904096 ==DQ 0 ==
2422 12:40:27.906738 Final DQ duty delay cell = 0
2423 12:40:27.910442 [0] MAX Duty = 5093%(X100), DQS PI = 18
2424 12:40:27.913652 [0] MIN Duty = 4907%(X100), DQS PI = 56
2425 12:40:27.917102 [0] AVG Duty = 5000%(X100)
2426 12:40:27.917183
2427 12:40:27.917248 ==DQ 1 ==
2428 12:40:27.920322 Final DQ duty delay cell = 0
2429 12:40:27.923307 [0] MAX Duty = 5125%(X100), DQS PI = 36
2430 12:40:27.926954 [0] MIN Duty = 5000%(X100), DQS PI = 26
2431 12:40:27.929994 [0] AVG Duty = 5062%(X100)
2432 12:40:27.930075
2433 12:40:27.933607 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2434 12:40:27.933689
2435 12:40:27.936651 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2436 12:40:27.940180 [DutyScan_Calibration_Flow] ====Done====
2437 12:40:27.943190 nWR fixed to 30
2438 12:40:27.946767 [ModeRegInit_LP4] CH0 RK0
2439 12:40:27.946885 [ModeRegInit_LP4] CH0 RK1
2440 12:40:27.949702 [ModeRegInit_LP4] CH1 RK0
2441 12:40:27.953126 [ModeRegInit_LP4] CH1 RK1
2442 12:40:27.953207 match AC timing 7
2443 12:40:27.959847 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2444 12:40:27.962843 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2445 12:40:27.966534 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2446 12:40:27.973118 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2447 12:40:27.976665 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2448 12:40:27.976747 ==
2449 12:40:27.979789 Dram Type= 6, Freq= 0, CH_0, rank 0
2450 12:40:27.983291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2451 12:40:27.983373 ==
2452 12:40:27.989639 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2453 12:40:27.996081 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2454 12:40:28.003887 [CA 0] Center 40 (10~71) winsize 62
2455 12:40:28.007685 [CA 1] Center 39 (9~70) winsize 62
2456 12:40:28.010394 [CA 2] Center 36 (6~66) winsize 61
2457 12:40:28.013833 [CA 3] Center 35 (5~66) winsize 62
2458 12:40:28.017131 [CA 4] Center 34 (4~65) winsize 62
2459 12:40:28.020655 [CA 5] Center 33 (3~63) winsize 61
2460 12:40:28.020737
2461 12:40:28.024113 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2462 12:40:28.024196
2463 12:40:28.027130 [CATrainingPosCal] consider 1 rank data
2464 12:40:28.030743 u2DelayCellTimex100 = 270/100 ps
2465 12:40:28.033969 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2466 12:40:28.040638 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2467 12:40:28.043665 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2468 12:40:28.047273 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2469 12:40:28.050391 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2470 12:40:28.053979 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2471 12:40:28.054061
2472 12:40:28.056869 CA PerBit enable=1, Macro0, CA PI delay=33
2473 12:40:28.056951
2474 12:40:28.060370 [CBTSetCACLKResult] CA Dly = 33
2475 12:40:28.063401 CS Dly: 7 (0~38)
2476 12:40:28.063482 ==
2477 12:40:28.066966 Dram Type= 6, Freq= 0, CH_0, rank 1
2478 12:40:28.070614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2479 12:40:28.070697 ==
2480 12:40:28.077006 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2481 12:40:28.079938 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2482 12:40:28.090057 [CA 0] Center 40 (10~70) winsize 61
2483 12:40:28.093066 [CA 1] Center 39 (9~70) winsize 62
2484 12:40:28.096513 [CA 2] Center 35 (5~66) winsize 62
2485 12:40:28.099705 [CA 3] Center 35 (5~66) winsize 62
2486 12:40:28.102794 [CA 4] Center 34 (4~65) winsize 62
2487 12:40:28.106510 [CA 5] Center 33 (3~63) winsize 61
2488 12:40:28.106670
2489 12:40:28.109575 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2490 12:40:28.109657
2491 12:40:28.113142 [CATrainingPosCal] consider 2 rank data
2492 12:40:28.116705 u2DelayCellTimex100 = 270/100 ps
2493 12:40:28.119609 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2494 12:40:28.126253 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2495 12:40:28.129814 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2496 12:40:28.133102 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2497 12:40:28.136191 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2498 12:40:28.139545 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2499 12:40:28.139716
2500 12:40:28.143023 CA PerBit enable=1, Macro0, CA PI delay=33
2501 12:40:28.143135
2502 12:40:28.146057 [CBTSetCACLKResult] CA Dly = 33
2503 12:40:28.149682 CS Dly: 8 (0~40)
2504 12:40:28.149816
2505 12:40:28.152667 ----->DramcWriteLeveling(PI) begin...
2506 12:40:28.152757 ==
2507 12:40:28.156306 Dram Type= 6, Freq= 0, CH_0, rank 0
2508 12:40:28.159315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2509 12:40:28.159437 ==
2510 12:40:28.163089 Write leveling (Byte 0): 33 => 33
2511 12:40:28.165991 Write leveling (Byte 1): 29 => 29
2512 12:40:28.169444 DramcWriteLeveling(PI) end<-----
2513 12:40:28.169560
2514 12:40:28.169631 ==
2515 12:40:28.172449 Dram Type= 6, Freq= 0, CH_0, rank 0
2516 12:40:28.176104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 12:40:28.176227 ==
2518 12:40:28.179105 [Gating] SW mode calibration
2519 12:40:28.185857 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2520 12:40:28.192401 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2521 12:40:28.195882 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2522 12:40:28.198891 0 15 4 | B1->B0 | 2727 3333 | 0 1 | (0 0) (1 1)
2523 12:40:28.205721 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2524 12:40:28.208884 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2525 12:40:28.212920 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2526 12:40:28.218898 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2527 12:40:28.222540 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 12:40:28.225873 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2529 12:40:28.232427 1 0 0 | B1->B0 | 3434 2d2d | 0 0 | (0 0) (1 0)
2530 12:40:28.235865 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2531 12:40:28.238798 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 12:40:28.245556 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 12:40:28.249267 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 12:40:28.252270 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 12:40:28.258840 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 12:40:28.262465 1 0 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2537 12:40:28.265540 1 1 0 | B1->B0 | 2525 3030 | 0 0 | (0 0) (0 0)
2538 12:40:28.272606 1 1 4 | B1->B0 | 3b3b 4545 | 0 0 | (0 0) (0 0)
2539 12:40:28.276007 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 12:40:28.278709 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 12:40:28.282197 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 12:40:28.288713 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 12:40:28.292411 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 12:40:28.295272 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2545 12:40:28.301836 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2546 12:40:28.305350 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 12:40:28.308916 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 12:40:28.315591 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 12:40:28.318716 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 12:40:28.321779 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 12:40:28.328969 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 12:40:28.331864 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 12:40:28.335265 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 12:40:28.341990 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 12:40:28.345543 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 12:40:28.348583 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 12:40:28.355146 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 12:40:28.358918 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 12:40:28.361874 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 12:40:28.368612 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2561 12:40:28.371723 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2562 12:40:28.375397 Total UI for P1: 0, mck2ui 16
2563 12:40:28.378345 best dqsien dly found for B0: ( 1, 3, 28)
2564 12:40:28.381842 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2565 12:40:28.385117 Total UI for P1: 0, mck2ui 16
2566 12:40:28.388698 best dqsien dly found for B1: ( 1, 4, 0)
2567 12:40:28.391915 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2568 12:40:28.395139 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2569 12:40:28.395251
2570 12:40:28.401827 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2571 12:40:28.404740 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2572 12:40:28.404827 [Gating] SW calibration Done
2573 12:40:28.408218 ==
2574 12:40:28.408328 Dram Type= 6, Freq= 0, CH_0, rank 0
2575 12:40:28.414812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2576 12:40:28.414909 ==
2577 12:40:28.414978 RX Vref Scan: 0
2578 12:40:28.415042
2579 12:40:28.418082 RX Vref 0 -> 0, step: 1
2580 12:40:28.418165
2581 12:40:28.421782 RX Delay -40 -> 252, step: 8
2582 12:40:28.424965 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2583 12:40:28.428086 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2584 12:40:28.431705 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2585 12:40:28.437876 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2586 12:40:28.441375 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2587 12:40:28.444849 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2588 12:40:28.448071 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2589 12:40:28.451598 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2590 12:40:28.457935 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2591 12:40:28.461093 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2592 12:40:28.464496 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2593 12:40:28.467938 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2594 12:40:28.470982 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2595 12:40:28.477617 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2596 12:40:28.481253 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2597 12:40:28.484278 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2598 12:40:28.484355 ==
2599 12:40:28.487647 Dram Type= 6, Freq= 0, CH_0, rank 0
2600 12:40:28.491199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2601 12:40:28.491284 ==
2602 12:40:28.494591 DQS Delay:
2603 12:40:28.494700 DQS0 = 0, DQS1 = 0
2604 12:40:28.497551 DQM Delay:
2605 12:40:28.497642 DQM0 = 112, DQM1 = 102
2606 12:40:28.500921 DQ Delay:
2607 12:40:28.504649 DQ0 =111, DQ1 =115, DQ2 =111, DQ3 =107
2608 12:40:28.507817 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2609 12:40:28.510788 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2610 12:40:28.514328 DQ12 =111, DQ13 =107, DQ14 =115, DQ15 =111
2611 12:40:28.514409
2612 12:40:28.514475
2613 12:40:28.514536 ==
2614 12:40:28.517691 Dram Type= 6, Freq= 0, CH_0, rank 0
2615 12:40:28.520773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2616 12:40:28.520853 ==
2617 12:40:28.520928
2618 12:40:28.520990
2619 12:40:28.524494 TX Vref Scan disable
2620 12:40:28.527555 == TX Byte 0 ==
2621 12:40:28.531138 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2622 12:40:28.534150 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2623 12:40:28.537125 == TX Byte 1 ==
2624 12:40:28.540723 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2625 12:40:28.544234 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2626 12:40:28.544313 ==
2627 12:40:28.547451 Dram Type= 6, Freq= 0, CH_0, rank 0
2628 12:40:28.550993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2629 12:40:28.554066 ==
2630 12:40:28.564373 TX Vref=22, minBit 6, minWin=25, winSum=418
2631 12:40:28.567423 TX Vref=24, minBit 0, minWin=26, winSum=423
2632 12:40:28.571175 TX Vref=26, minBit 10, minWin=26, winSum=432
2633 12:40:28.574259 TX Vref=28, minBit 14, minWin=26, winSum=433
2634 12:40:28.577217 TX Vref=30, minBit 8, minWin=26, winSum=434
2635 12:40:28.584050 TX Vref=32, minBit 2, minWin=26, winSum=432
2636 12:40:28.587721 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 30
2637 12:40:28.587796
2638 12:40:28.590756 Final TX Range 1 Vref 30
2639 12:40:28.590889
2640 12:40:28.590951 ==
2641 12:40:28.594308 Dram Type= 6, Freq= 0, CH_0, rank 0
2642 12:40:28.597331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2643 12:40:28.600946 ==
2644 12:40:28.601060
2645 12:40:28.601124
2646 12:40:28.601185 TX Vref Scan disable
2647 12:40:28.604409 == TX Byte 0 ==
2648 12:40:28.607951 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2649 12:40:28.614201 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2650 12:40:28.614284 == TX Byte 1 ==
2651 12:40:28.617620 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2652 12:40:28.624033 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2653 12:40:28.624117
2654 12:40:28.624181 [DATLAT]
2655 12:40:28.624245 Freq=1200, CH0 RK0
2656 12:40:28.624303
2657 12:40:28.627747 DATLAT Default: 0xd
2658 12:40:28.627827 0, 0xFFFF, sum = 0
2659 12:40:28.630737 1, 0xFFFF, sum = 0
2660 12:40:28.633847 2, 0xFFFF, sum = 0
2661 12:40:28.633955 3, 0xFFFF, sum = 0
2662 12:40:28.637394 4, 0xFFFF, sum = 0
2663 12:40:28.637499 5, 0xFFFF, sum = 0
2664 12:40:28.640454 6, 0xFFFF, sum = 0
2665 12:40:28.640573 7, 0xFFFF, sum = 0
2666 12:40:28.644148 8, 0xFFFF, sum = 0
2667 12:40:28.644244 9, 0xFFFF, sum = 0
2668 12:40:28.647030 10, 0xFFFF, sum = 0
2669 12:40:28.647124 11, 0xFFFF, sum = 0
2670 12:40:28.650591 12, 0x0, sum = 1
2671 12:40:28.650694 13, 0x0, sum = 2
2672 12:40:28.653866 14, 0x0, sum = 3
2673 12:40:28.653943 15, 0x0, sum = 4
2674 12:40:28.657418 best_step = 13
2675 12:40:28.657517
2676 12:40:28.657607 ==
2677 12:40:28.660191 Dram Type= 6, Freq= 0, CH_0, rank 0
2678 12:40:28.663810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2679 12:40:28.663917 ==
2680 12:40:28.667237 RX Vref Scan: 1
2681 12:40:28.667356
2682 12:40:28.667445 Set Vref Range= 32 -> 127
2683 12:40:28.667506
2684 12:40:28.670416 RX Vref 32 -> 127, step: 1
2685 12:40:28.670518
2686 12:40:28.673573 RX Delay -37 -> 252, step: 4
2687 12:40:28.673644
2688 12:40:28.677151 Set Vref, RX VrefLevel [Byte0]: 32
2689 12:40:28.680192 [Byte1]: 32
2690 12:40:28.680276
2691 12:40:28.683327 Set Vref, RX VrefLevel [Byte0]: 33
2692 12:40:28.687112 [Byte1]: 33
2693 12:40:28.690704
2694 12:40:28.690813 Set Vref, RX VrefLevel [Byte0]: 34
2695 12:40:28.693926 [Byte1]: 34
2696 12:40:28.698778
2697 12:40:28.698882 Set Vref, RX VrefLevel [Byte0]: 35
2698 12:40:28.702501 [Byte1]: 35
2699 12:40:28.706997
2700 12:40:28.707104 Set Vref, RX VrefLevel [Byte0]: 36
2701 12:40:28.709977 [Byte1]: 36
2702 12:40:28.714955
2703 12:40:28.715043 Set Vref, RX VrefLevel [Byte0]: 37
2704 12:40:28.718335 [Byte1]: 37
2705 12:40:28.722959
2706 12:40:28.723045 Set Vref, RX VrefLevel [Byte0]: 38
2707 12:40:28.726009 [Byte1]: 38
2708 12:40:28.731013
2709 12:40:28.731107 Set Vref, RX VrefLevel [Byte0]: 39
2710 12:40:28.734029 [Byte1]: 39
2711 12:40:28.738975
2712 12:40:28.739058 Set Vref, RX VrefLevel [Byte0]: 40
2713 12:40:28.742054 [Byte1]: 40
2714 12:40:28.747054
2715 12:40:28.747169 Set Vref, RX VrefLevel [Byte0]: 41
2716 12:40:28.750632 [Byte1]: 41
2717 12:40:28.755037
2718 12:40:28.755143 Set Vref, RX VrefLevel [Byte0]: 42
2719 12:40:28.757917 [Byte1]: 42
2720 12:40:28.763110
2721 12:40:28.763224 Set Vref, RX VrefLevel [Byte0]: 43
2722 12:40:28.766081 [Byte1]: 43
2723 12:40:28.770716
2724 12:40:28.770835 Set Vref, RX VrefLevel [Byte0]: 44
2725 12:40:28.774115 [Byte1]: 44
2726 12:40:28.779035
2727 12:40:28.779117 Set Vref, RX VrefLevel [Byte0]: 45
2728 12:40:28.782031 [Byte1]: 45
2729 12:40:28.786740
2730 12:40:28.786823 Set Vref, RX VrefLevel [Byte0]: 46
2731 12:40:28.790008 [Byte1]: 46
2732 12:40:28.794949
2733 12:40:28.795033 Set Vref, RX VrefLevel [Byte0]: 47
2734 12:40:28.798085 [Byte1]: 47
2735 12:40:28.803087
2736 12:40:28.803168 Set Vref, RX VrefLevel [Byte0]: 48
2737 12:40:28.806180 [Byte1]: 48
2738 12:40:28.810952
2739 12:40:28.811033 Set Vref, RX VrefLevel [Byte0]: 49
2740 12:40:28.814423 [Byte1]: 49
2741 12:40:28.819175
2742 12:40:28.819283 Set Vref, RX VrefLevel [Byte0]: 50
2743 12:40:28.822069 [Byte1]: 50
2744 12:40:28.826718
2745 12:40:28.826802 Set Vref, RX VrefLevel [Byte0]: 51
2746 12:40:28.830349 [Byte1]: 51
2747 12:40:28.835108
2748 12:40:28.835190 Set Vref, RX VrefLevel [Byte0]: 52
2749 12:40:28.838137 [Byte1]: 52
2750 12:40:28.843056
2751 12:40:28.843168 Set Vref, RX VrefLevel [Byte0]: 53
2752 12:40:28.846070 [Byte1]: 53
2753 12:40:28.850782
2754 12:40:28.850921 Set Vref, RX VrefLevel [Byte0]: 54
2755 12:40:28.853921 [Byte1]: 54
2756 12:40:28.858611
2757 12:40:28.858692 Set Vref, RX VrefLevel [Byte0]: 55
2758 12:40:28.862062 [Byte1]: 55
2759 12:40:28.867028
2760 12:40:28.867161 Set Vref, RX VrefLevel [Byte0]: 56
2761 12:40:28.869940 [Byte1]: 56
2762 12:40:28.875066
2763 12:40:28.875203 Set Vref, RX VrefLevel [Byte0]: 57
2764 12:40:28.877913 [Byte1]: 57
2765 12:40:28.883148
2766 12:40:28.883249 Set Vref, RX VrefLevel [Byte0]: 58
2767 12:40:28.886255 [Byte1]: 58
2768 12:40:28.890688
2769 12:40:28.890772 Set Vref, RX VrefLevel [Byte0]: 59
2770 12:40:28.894298 [Byte1]: 59
2771 12:40:28.899305
2772 12:40:28.899386 Set Vref, RX VrefLevel [Byte0]: 60
2773 12:40:28.902290 [Byte1]: 60
2774 12:40:28.907096
2775 12:40:28.907178 Set Vref, RX VrefLevel [Byte0]: 61
2776 12:40:28.910081 [Byte1]: 61
2777 12:40:28.914848
2778 12:40:28.914946 Set Vref, RX VrefLevel [Byte0]: 62
2779 12:40:28.918450 [Byte1]: 62
2780 12:40:28.923171
2781 12:40:28.923310 Set Vref, RX VrefLevel [Byte0]: 63
2782 12:40:28.926624 [Byte1]: 63
2783 12:40:28.931138
2784 12:40:28.931238 Set Vref, RX VrefLevel [Byte0]: 64
2785 12:40:28.933911 [Byte1]: 64
2786 12:40:28.939173
2787 12:40:28.939254 Set Vref, RX VrefLevel [Byte0]: 65
2788 12:40:28.942088 [Byte1]: 65
2789 12:40:28.946821
2790 12:40:28.946937 Set Vref, RX VrefLevel [Byte0]: 66
2791 12:40:28.949941 [Byte1]: 66
2792 12:40:28.954800
2793 12:40:28.954920 Set Vref, RX VrefLevel [Byte0]: 67
2794 12:40:28.958447 [Byte1]: 67
2795 12:40:28.962723
2796 12:40:28.966262 Set Vref, RX VrefLevel [Byte0]: 68
2797 12:40:28.969129 [Byte1]: 68
2798 12:40:28.969227
2799 12:40:28.972603 Set Vref, RX VrefLevel [Byte0]: 69
2800 12:40:28.976143 [Byte1]: 69
2801 12:40:28.976244
2802 12:40:28.979078 Set Vref, RX VrefLevel [Byte0]: 70
2803 12:40:28.982418 [Byte1]: 70
2804 12:40:28.986882
2805 12:40:28.987031 Set Vref, RX VrefLevel [Byte0]: 71
2806 12:40:28.990000 [Byte1]: 71
2807 12:40:28.995027
2808 12:40:28.995127 Set Vref, RX VrefLevel [Byte0]: 72
2809 12:40:28.998077 [Byte1]: 72
2810 12:40:29.003032
2811 12:40:29.003114 Set Vref, RX VrefLevel [Byte0]: 73
2812 12:40:29.006039 [Byte1]: 73
2813 12:40:29.011137
2814 12:40:29.011246 Final RX Vref Byte 0 = 60 to rank0
2815 12:40:29.014110 Final RX Vref Byte 1 = 46 to rank0
2816 12:40:29.017837 Final RX Vref Byte 0 = 60 to rank1
2817 12:40:29.021047 Final RX Vref Byte 1 = 46 to rank1==
2818 12:40:29.024155 Dram Type= 6, Freq= 0, CH_0, rank 0
2819 12:40:29.031099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2820 12:40:29.031183 ==
2821 12:40:29.031249 DQS Delay:
2822 12:40:29.034084 DQS0 = 0, DQS1 = 0
2823 12:40:29.034167 DQM Delay:
2824 12:40:29.034232 DQM0 = 111, DQM1 = 98
2825 12:40:29.036996 DQ Delay:
2826 12:40:29.040542 DQ0 =110, DQ1 =112, DQ2 =110, DQ3 =108
2827 12:40:29.043597 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2828 12:40:29.046956 DQ8 =90, DQ9 =82, DQ10 =100, DQ11 =90
2829 12:40:29.050581 DQ12 =104, DQ13 =104, DQ14 =112, DQ15 =106
2830 12:40:29.050689
2831 12:40:29.050783
2832 12:40:29.060325 [DQSOSCAuto] RK0, (LSB)MR18= 0xfefd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
2833 12:40:29.060414 CH0 RK0: MR19=303, MR18=FEFD
2834 12:40:29.066647 CH0_RK0: MR19=0x303, MR18=0xFEFD, DQSOSC=410, MR23=63, INC=39, DEC=26
2835 12:40:29.066774
2836 12:40:29.070343 ----->DramcWriteLeveling(PI) begin...
2837 12:40:29.070428 ==
2838 12:40:29.074038 Dram Type= 6, Freq= 0, CH_0, rank 1
2839 12:40:29.080077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2840 12:40:29.080161 ==
2841 12:40:29.083514 Write leveling (Byte 0): 34 => 34
2842 12:40:29.087052 Write leveling (Byte 1): 32 => 32
2843 12:40:29.087135 DramcWriteLeveling(PI) end<-----
2844 12:40:29.087200
2845 12:40:29.089907 ==
2846 12:40:29.093335 Dram Type= 6, Freq= 0, CH_0, rank 1
2847 12:40:29.096849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2848 12:40:29.096933 ==
2849 12:40:29.099903 [Gating] SW mode calibration
2850 12:40:29.106615 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2851 12:40:29.109680 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2852 12:40:29.116442 0 15 0 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
2853 12:40:29.120193 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 12:40:29.123270 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 12:40:29.129986 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 12:40:29.132924 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 12:40:29.136391 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 12:40:29.143301 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2859 12:40:29.146147 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 0)
2860 12:40:29.149720 1 0 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
2861 12:40:29.156022 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 12:40:29.159561 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 12:40:29.163186 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 12:40:29.169870 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 12:40:29.172871 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 12:40:29.175902 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2867 12:40:29.182848 1 0 28 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
2868 12:40:29.186587 1 1 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2869 12:40:29.189196 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 12:40:29.196077 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 12:40:29.199462 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 12:40:29.202274 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 12:40:29.209483 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 12:40:29.212458 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 12:40:29.215962 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2876 12:40:29.222339 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2877 12:40:29.226079 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 12:40:29.228992 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 12:40:29.235928 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 12:40:29.239024 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 12:40:29.242593 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 12:40:29.245885 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 12:40:29.252405 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 12:40:29.255899 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 12:40:29.258888 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 12:40:29.265686 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 12:40:29.268753 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 12:40:29.272486 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 12:40:29.278810 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 12:40:29.282045 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2891 12:40:29.285543 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2892 12:40:29.291901 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2893 12:40:29.295437 Total UI for P1: 0, mck2ui 16
2894 12:40:29.298933 best dqsien dly found for B0: ( 1, 3, 26)
2895 12:40:29.301798 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2896 12:40:29.305173 Total UI for P1: 0, mck2ui 16
2897 12:40:29.308812 best dqsien dly found for B1: ( 1, 4, 0)
2898 12:40:29.311692 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2899 12:40:29.315339 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2900 12:40:29.315427
2901 12:40:29.318323 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2902 12:40:29.322115 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2903 12:40:29.325179 [Gating] SW calibration Done
2904 12:40:29.325261 ==
2905 12:40:29.328387 Dram Type= 6, Freq= 0, CH_0, rank 1
2906 12:40:29.335228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2907 12:40:29.335311 ==
2908 12:40:29.335380 RX Vref Scan: 0
2909 12:40:29.335442
2910 12:40:29.338266 RX Vref 0 -> 0, step: 1
2911 12:40:29.338348
2912 12:40:29.341544 RX Delay -40 -> 252, step: 8
2913 12:40:29.345268 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2914 12:40:29.348249 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2915 12:40:29.351997 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2916 12:40:29.354759 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2917 12:40:29.361159 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2918 12:40:29.364797 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2919 12:40:29.367875 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2920 12:40:29.371603 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2921 12:40:29.374687 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2922 12:40:29.381517 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2923 12:40:29.384613 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2924 12:40:29.387740 iDelay=200, Bit 11, Center 91 (16 ~ 167) 152
2925 12:40:29.391466 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2926 12:40:29.394773 iDelay=200, Bit 13, Center 103 (32 ~ 175) 144
2927 12:40:29.401264 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2928 12:40:29.404497 iDelay=200, Bit 15, Center 107 (40 ~ 175) 136
2929 12:40:29.404575 ==
2930 12:40:29.407916 Dram Type= 6, Freq= 0, CH_0, rank 1
2931 12:40:29.411208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2932 12:40:29.411283 ==
2933 12:40:29.414554 DQS Delay:
2934 12:40:29.414627 DQS0 = 0, DQS1 = 0
2935 12:40:29.417510 DQM Delay:
2936 12:40:29.417612 DQM0 = 112, DQM1 = 99
2937 12:40:29.417708 DQ Delay:
2938 12:40:29.420983 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2939 12:40:29.424322 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =123
2940 12:40:29.427470 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =91
2941 12:40:29.434218 DQ12 =107, DQ13 =103, DQ14 =111, DQ15 =107
2942 12:40:29.434325
2943 12:40:29.434422
2944 12:40:29.434513 ==
2945 12:40:29.438001 Dram Type= 6, Freq= 0, CH_0, rank 1
2946 12:40:29.441010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2947 12:40:29.441084 ==
2948 12:40:29.441147
2949 12:40:29.441206
2950 12:40:29.444089 TX Vref Scan disable
2951 12:40:29.444160 == TX Byte 0 ==
2952 12:40:29.450852 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2953 12:40:29.453793 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2954 12:40:29.453896 == TX Byte 1 ==
2955 12:40:29.460948 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2956 12:40:29.463703 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2957 12:40:29.463784 ==
2958 12:40:29.467342 Dram Type= 6, Freq= 0, CH_0, rank 1
2959 12:40:29.470601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2960 12:40:29.470682 ==
2961 12:40:29.483899 TX Vref=22, minBit 1, minWin=26, winSum=428
2962 12:40:29.486961 TX Vref=24, minBit 12, minWin=26, winSum=431
2963 12:40:29.490133 TX Vref=26, minBit 12, minWin=26, winSum=433
2964 12:40:29.493274 TX Vref=28, minBit 1, minWin=27, winSum=440
2965 12:40:29.496977 TX Vref=30, minBit 13, minWin=26, winSum=436
2966 12:40:29.503613 TX Vref=32, minBit 13, minWin=26, winSum=437
2967 12:40:29.506546 [TxChooseVref] Worse bit 1, Min win 27, Win sum 440, Final Vref 28
2968 12:40:29.506650
2969 12:40:29.510211 Final TX Range 1 Vref 28
2970 12:40:29.510300
2971 12:40:29.510381 ==
2972 12:40:29.513306 Dram Type= 6, Freq= 0, CH_0, rank 1
2973 12:40:29.516991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2974 12:40:29.520157 ==
2975 12:40:29.520263
2976 12:40:29.520355
2977 12:40:29.520449 TX Vref Scan disable
2978 12:40:29.523504 == TX Byte 0 ==
2979 12:40:29.526808 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2980 12:40:29.533581 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2981 12:40:29.533690 == TX Byte 1 ==
2982 12:40:29.537157 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2983 12:40:29.543430 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2984 12:40:29.543530
2985 12:40:29.543597 [DATLAT]
2986 12:40:29.543659 Freq=1200, CH0 RK1
2987 12:40:29.543720
2988 12:40:29.546547 DATLAT Default: 0xd
2989 12:40:29.550276 0, 0xFFFF, sum = 0
2990 12:40:29.550363 1, 0xFFFF, sum = 0
2991 12:40:29.553447 2, 0xFFFF, sum = 0
2992 12:40:29.553533 3, 0xFFFF, sum = 0
2993 12:40:29.556563 4, 0xFFFF, sum = 0
2994 12:40:29.556648 5, 0xFFFF, sum = 0
2995 12:40:29.560091 6, 0xFFFF, sum = 0
2996 12:40:29.560177 7, 0xFFFF, sum = 0
2997 12:40:29.563306 8, 0xFFFF, sum = 0
2998 12:40:29.563392 9, 0xFFFF, sum = 0
2999 12:40:29.566655 10, 0xFFFF, sum = 0
3000 12:40:29.566776 11, 0xFFFF, sum = 0
3001 12:40:29.569675 12, 0x0, sum = 1
3002 12:40:29.569773 13, 0x0, sum = 2
3003 12:40:29.573228 14, 0x0, sum = 3
3004 12:40:29.573314 15, 0x0, sum = 4
3005 12:40:29.576713 best_step = 13
3006 12:40:29.576791
3007 12:40:29.576856 ==
3008 12:40:29.580292 Dram Type= 6, Freq= 0, CH_0, rank 1
3009 12:40:29.583330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3010 12:40:29.583409 ==
3011 12:40:29.583474 RX Vref Scan: 0
3012 12:40:29.586473
3013 12:40:29.586544 RX Vref 0 -> 0, step: 1
3014 12:40:29.586605
3015 12:40:29.590158 RX Delay -37 -> 252, step: 4
3016 12:40:29.596367 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3017 12:40:29.599511 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3018 12:40:29.603218 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3019 12:40:29.606290 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3020 12:40:29.609484 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3021 12:40:29.616506 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3022 12:40:29.619913 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3023 12:40:29.623280 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3024 12:40:29.626225 iDelay=195, Bit 8, Center 88 (19 ~ 158) 140
3025 12:40:29.629545 iDelay=195, Bit 9, Center 80 (11 ~ 150) 140
3026 12:40:29.632872 iDelay=195, Bit 10, Center 100 (31 ~ 170) 140
3027 12:40:29.639643 iDelay=195, Bit 11, Center 90 (23 ~ 158) 136
3028 12:40:29.643177 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3029 12:40:29.646142 iDelay=195, Bit 13, Center 106 (35 ~ 178) 144
3030 12:40:29.649961 iDelay=195, Bit 14, Center 112 (47 ~ 178) 132
3031 12:40:29.656128 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3032 12:40:29.656236 ==
3033 12:40:29.659736 Dram Type= 6, Freq= 0, CH_0, rank 1
3034 12:40:29.662703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3035 12:40:29.662804 ==
3036 12:40:29.662887 DQS Delay:
3037 12:40:29.666056 DQS0 = 0, DQS1 = 0
3038 12:40:29.666141 DQM Delay:
3039 12:40:29.669609 DQM0 = 110, DQM1 = 99
3040 12:40:29.669710 DQ Delay:
3041 12:40:29.673018 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3042 12:40:29.675913 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3043 12:40:29.679234 DQ8 =88, DQ9 =80, DQ10 =100, DQ11 =90
3044 12:40:29.682733 DQ12 =108, DQ13 =106, DQ14 =112, DQ15 =108
3045 12:40:29.682838
3046 12:40:29.682904
3047 12:40:29.692654 [DQSOSCAuto] RK1, (LSB)MR18= 0x14fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 402 ps
3048 12:40:29.695675 CH0 RK1: MR19=403, MR18=14FC
3049 12:40:29.699259 CH0_RK1: MR19=0x403, MR18=0x14FC, DQSOSC=402, MR23=63, INC=40, DEC=27
3050 12:40:29.702281 [RxdqsGatingPostProcess] freq 1200
3051 12:40:29.709003 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3052 12:40:29.712554 best DQS0 dly(2T, 0.5T) = (0, 11)
3053 12:40:29.715604 best DQS1 dly(2T, 0.5T) = (0, 12)
3054 12:40:29.718986 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3055 12:40:29.722575 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3056 12:40:29.725573 best DQS0 dly(2T, 0.5T) = (0, 11)
3057 12:40:29.728943 best DQS1 dly(2T, 0.5T) = (0, 12)
3058 12:40:29.732369 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3059 12:40:29.735701 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3060 12:40:29.738699 Pre-setting of DQS Precalculation
3061 12:40:29.742156 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3062 12:40:29.742238 ==
3063 12:40:29.745441 Dram Type= 6, Freq= 0, CH_1, rank 0
3064 12:40:29.748581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3065 12:40:29.748687 ==
3066 12:40:29.755826 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3067 12:40:29.761907 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3068 12:40:29.769730 [CA 0] Center 37 (7~67) winsize 61
3069 12:40:29.773424 [CA 1] Center 37 (7~68) winsize 62
3070 12:40:29.776271 [CA 2] Center 34 (5~64) winsize 60
3071 12:40:29.779518 [CA 3] Center 33 (3~64) winsize 62
3072 12:40:29.783250 [CA 4] Center 34 (4~64) winsize 61
3073 12:40:29.786066 [CA 5] Center 33 (3~63) winsize 61
3074 12:40:29.786177
3075 12:40:29.789636 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3076 12:40:29.789735
3077 12:40:29.792941 [CATrainingPosCal] consider 1 rank data
3078 12:40:29.796237 u2DelayCellTimex100 = 270/100 ps
3079 12:40:29.799819 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3080 12:40:29.803338 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3081 12:40:29.809908 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3082 12:40:29.812937 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3083 12:40:29.816566 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3084 12:40:29.819552 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3085 12:40:29.819651
3086 12:40:29.823061 CA PerBit enable=1, Macro0, CA PI delay=33
3087 12:40:29.823141
3088 12:40:29.826540 [CBTSetCACLKResult] CA Dly = 33
3089 12:40:29.826647 CS Dly: 5 (0~36)
3090 12:40:29.829611 ==
3091 12:40:29.829720 Dram Type= 6, Freq= 0, CH_1, rank 1
3092 12:40:29.836349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3093 12:40:29.836472 ==
3094 12:40:29.839797 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3095 12:40:29.846041 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3096 12:40:29.855712 [CA 0] Center 37 (7~67) winsize 61
3097 12:40:29.858697 [CA 1] Center 37 (7~68) winsize 62
3098 12:40:29.862269 [CA 2] Center 34 (4~65) winsize 62
3099 12:40:29.865274 [CA 3] Center 33 (3~64) winsize 62
3100 12:40:29.868950 [CA 4] Center 34 (4~65) winsize 62
3101 12:40:29.872084 [CA 5] Center 32 (2~63) winsize 62
3102 12:40:29.872188
3103 12:40:29.875184 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3104 12:40:29.875285
3105 12:40:29.878379 [CATrainingPosCal] consider 2 rank data
3106 12:40:29.881896 u2DelayCellTimex100 = 270/100 ps
3107 12:40:29.885475 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3108 12:40:29.891747 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3109 12:40:29.895129 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3110 12:40:29.898123 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3111 12:40:29.901534 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3112 12:40:29.905058 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3113 12:40:29.905133
3114 12:40:29.908079 CA PerBit enable=1, Macro0, CA PI delay=33
3115 12:40:29.908151
3116 12:40:29.911569 [CBTSetCACLKResult] CA Dly = 33
3117 12:40:29.914599 CS Dly: 6 (0~39)
3118 12:40:29.914705
3119 12:40:29.918141 ----->DramcWriteLeveling(PI) begin...
3120 12:40:29.918241 ==
3121 12:40:29.921298 Dram Type= 6, Freq= 0, CH_1, rank 0
3122 12:40:29.924879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3123 12:40:29.924958 ==
3124 12:40:29.927723 Write leveling (Byte 0): 25 => 25
3125 12:40:29.931571 Write leveling (Byte 1): 28 => 28
3126 12:40:29.934986 DramcWriteLeveling(PI) end<-----
3127 12:40:29.935060
3128 12:40:29.935122 ==
3129 12:40:29.937988 Dram Type= 6, Freq= 0, CH_1, rank 0
3130 12:40:29.941376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3131 12:40:29.941481 ==
3132 12:40:29.944431 [Gating] SW mode calibration
3133 12:40:29.951252 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3134 12:40:29.957771 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3135 12:40:29.961326 0 15 0 | B1->B0 | 3131 2f2e | 0 1 | (0 0) (0 0)
3136 12:40:29.964446 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3137 12:40:29.971310 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 12:40:29.974570 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 12:40:29.977674 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 12:40:29.984360 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 12:40:29.987419 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 12:40:29.991048 0 15 28 | B1->B0 | 2d2d 2f2f | 0 1 | (0 0) (1 0)
3143 12:40:29.997393 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 12:40:30.000923 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 12:40:30.004481 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 12:40:30.010761 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 12:40:30.014363 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 12:40:30.017497 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 12:40:30.024354 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3150 12:40:30.027400 1 0 28 | B1->B0 | 3838 3636 | 1 0 | (0 0) (0 0)
3151 12:40:30.030454 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3152 12:40:30.037465 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 12:40:30.040494 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 12:40:30.043813 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 12:40:30.050429 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 12:40:30.053962 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 12:40:30.057258 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 12:40:30.063587 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3159 12:40:30.067030 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3160 12:40:30.070003 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 12:40:30.076739 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 12:40:30.080536 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 12:40:30.083609 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 12:40:30.090057 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 12:40:30.093584 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 12:40:30.096647 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 12:40:30.103237 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 12:40:30.106729 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 12:40:30.110207 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 12:40:30.116474 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 12:40:30.120015 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 12:40:30.123692 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 12:40:30.126846 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 12:40:30.133074 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3175 12:40:30.136665 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3176 12:40:30.140183 Total UI for P1: 0, mck2ui 16
3177 12:40:30.143330 best dqsien dly found for B0: ( 1, 3, 28)
3178 12:40:30.146961 Total UI for P1: 0, mck2ui 16
3179 12:40:30.149977 best dqsien dly found for B1: ( 1, 3, 30)
3180 12:40:30.153020 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3181 12:40:30.156605 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3182 12:40:30.156698
3183 12:40:30.159901 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3184 12:40:30.166229 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3185 12:40:30.166318 [Gating] SW calibration Done
3186 12:40:30.166387 ==
3187 12:40:30.169631 Dram Type= 6, Freq= 0, CH_1, rank 0
3188 12:40:30.176643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3189 12:40:30.176725 ==
3190 12:40:30.176790 RX Vref Scan: 0
3191 12:40:30.176851
3192 12:40:30.179841 RX Vref 0 -> 0, step: 1
3193 12:40:30.179913
3194 12:40:30.182810 RX Delay -40 -> 252, step: 8
3195 12:40:30.186577 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3196 12:40:30.189634 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3197 12:40:30.192793 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3198 12:40:30.199490 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3199 12:40:30.202464 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3200 12:40:30.206233 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3201 12:40:30.209689 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3202 12:40:30.212610 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3203 12:40:30.219827 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3204 12:40:30.222522 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3205 12:40:30.226140 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3206 12:40:30.229203 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3207 12:40:30.232840 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3208 12:40:30.239084 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3209 12:40:30.242659 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3210 12:40:30.245526 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3211 12:40:30.245613 ==
3212 12:40:30.249205 Dram Type= 6, Freq= 0, CH_1, rank 0
3213 12:40:30.252418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3214 12:40:30.252529 ==
3215 12:40:30.255508 DQS Delay:
3216 12:40:30.255610 DQS0 = 0, DQS1 = 0
3217 12:40:30.259205 DQM Delay:
3218 12:40:30.259314 DQM0 = 114, DQM1 = 106
3219 12:40:30.262246 DQ Delay:
3220 12:40:30.265892 DQ0 =123, DQ1 =107, DQ2 =103, DQ3 =115
3221 12:40:30.268851 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3222 12:40:30.272217 DQ8 =95, DQ9 =99, DQ10 =103, DQ11 =103
3223 12:40:30.275696 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3224 12:40:30.275820
3225 12:40:30.275918
3226 12:40:30.276010 ==
3227 12:40:30.279137 Dram Type= 6, Freq= 0, CH_1, rank 0
3228 12:40:30.282177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3229 12:40:30.282255 ==
3230 12:40:30.282320
3231 12:40:30.282381
3232 12:40:30.285344 TX Vref Scan disable
3233 12:40:30.288979 == TX Byte 0 ==
3234 12:40:30.292161 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3235 12:40:30.295740 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3236 12:40:30.298763 == TX Byte 1 ==
3237 12:40:30.302005 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3238 12:40:30.305583 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3239 12:40:30.305667 ==
3240 12:40:30.309314 Dram Type= 6, Freq= 0, CH_1, rank 0
3241 12:40:30.312328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3242 12:40:30.315223 ==
3243 12:40:30.325624 TX Vref=22, minBit 8, minWin=24, winSum=409
3244 12:40:30.329300 TX Vref=24, minBit 8, minWin=24, winSum=409
3245 12:40:30.332418 TX Vref=26, minBit 9, minWin=25, winSum=418
3246 12:40:30.335712 TX Vref=28, minBit 9, minWin=25, winSum=421
3247 12:40:30.338776 TX Vref=30, minBit 9, minWin=25, winSum=420
3248 12:40:30.345634 TX Vref=32, minBit 9, minWin=25, winSum=422
3249 12:40:30.348636 [TxChooseVref] Worse bit 9, Min win 25, Win sum 422, Final Vref 32
3250 12:40:30.348821
3251 12:40:30.352065 Final TX Range 1 Vref 32
3252 12:40:30.352150
3253 12:40:30.352216 ==
3254 12:40:30.355646 Dram Type= 6, Freq= 0, CH_1, rank 0
3255 12:40:30.358717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3256 12:40:30.358832 ==
3257 12:40:30.361921
3258 12:40:30.362003
3259 12:40:30.362069 TX Vref Scan disable
3260 12:40:30.364997 == TX Byte 0 ==
3261 12:40:30.368683 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3262 12:40:30.371962 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3263 12:40:30.375232 == TX Byte 1 ==
3264 12:40:30.378619 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3265 12:40:30.385127 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3266 12:40:30.385212
3267 12:40:30.385278 [DATLAT]
3268 12:40:30.385340 Freq=1200, CH1 RK0
3269 12:40:30.385400
3270 12:40:30.388617 DATLAT Default: 0xd
3271 12:40:30.388689 0, 0xFFFF, sum = 0
3272 12:40:30.391634 1, 0xFFFF, sum = 0
3273 12:40:30.391719 2, 0xFFFF, sum = 0
3274 12:40:30.395263 3, 0xFFFF, sum = 0
3275 12:40:30.398330 4, 0xFFFF, sum = 0
3276 12:40:30.398415 5, 0xFFFF, sum = 0
3277 12:40:30.402068 6, 0xFFFF, sum = 0
3278 12:40:30.402158 7, 0xFFFF, sum = 0
3279 12:40:30.405105 8, 0xFFFF, sum = 0
3280 12:40:30.405215 9, 0xFFFF, sum = 0
3281 12:40:30.408819 10, 0xFFFF, sum = 0
3282 12:40:30.408931 11, 0xFFFF, sum = 0
3283 12:40:30.411989 12, 0x0, sum = 1
3284 12:40:30.412074 13, 0x0, sum = 2
3285 12:40:30.415156 14, 0x0, sum = 3
3286 12:40:30.415241 15, 0x0, sum = 4
3287 12:40:30.415308 best_step = 13
3288 12:40:30.418280
3289 12:40:30.418362 ==
3290 12:40:30.421552 Dram Type= 6, Freq= 0, CH_1, rank 0
3291 12:40:30.425224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3292 12:40:30.425350 ==
3293 12:40:30.425462 RX Vref Scan: 1
3294 12:40:30.425556
3295 12:40:30.428028 Set Vref Range= 32 -> 127
3296 12:40:30.428127
3297 12:40:30.431616 RX Vref 32 -> 127, step: 1
3298 12:40:30.431698
3299 12:40:30.435242 RX Delay -21 -> 252, step: 4
3300 12:40:30.435356
3301 12:40:30.438009 Set Vref, RX VrefLevel [Byte0]: 32
3302 12:40:30.441641 [Byte1]: 32
3303 12:40:30.441783
3304 12:40:30.445181 Set Vref, RX VrefLevel [Byte0]: 33
3305 12:40:30.448212 [Byte1]: 33
3306 12:40:30.451881
3307 12:40:30.451970 Set Vref, RX VrefLevel [Byte0]: 34
3308 12:40:30.454748 [Byte1]: 34
3309 12:40:30.459609
3310 12:40:30.459690 Set Vref, RX VrefLevel [Byte0]: 35
3311 12:40:30.463115 [Byte1]: 35
3312 12:40:30.467625
3313 12:40:30.467708 Set Vref, RX VrefLevel [Byte0]: 36
3314 12:40:30.470646 [Byte1]: 36
3315 12:40:30.475654
3316 12:40:30.475745 Set Vref, RX VrefLevel [Byte0]: 37
3317 12:40:30.478666 [Byte1]: 37
3318 12:40:30.483421
3319 12:40:30.483504 Set Vref, RX VrefLevel [Byte0]: 38
3320 12:40:30.486712 [Byte1]: 38
3321 12:40:30.491640
3322 12:40:30.491723 Set Vref, RX VrefLevel [Byte0]: 39
3323 12:40:30.494479 [Byte1]: 39
3324 12:40:30.499082
3325 12:40:30.499193 Set Vref, RX VrefLevel [Byte0]: 40
3326 12:40:30.502756 [Byte1]: 40
3327 12:40:30.507225
3328 12:40:30.507307 Set Vref, RX VrefLevel [Byte0]: 41
3329 12:40:30.510260 [Byte1]: 41
3330 12:40:30.515006
3331 12:40:30.515101 Set Vref, RX VrefLevel [Byte0]: 42
3332 12:40:30.518535 [Byte1]: 42
3333 12:40:30.522880
3334 12:40:30.522962 Set Vref, RX VrefLevel [Byte0]: 43
3335 12:40:30.526557 [Byte1]: 43
3336 12:40:30.531182
3337 12:40:30.531263 Set Vref, RX VrefLevel [Byte0]: 44
3338 12:40:30.534308 [Byte1]: 44
3339 12:40:30.538851
3340 12:40:30.538975 Set Vref, RX VrefLevel [Byte0]: 45
3341 12:40:30.542498 [Byte1]: 45
3342 12:40:30.546763
3343 12:40:30.546875 Set Vref, RX VrefLevel [Byte0]: 46
3344 12:40:30.550202 [Byte1]: 46
3345 12:40:30.554688
3346 12:40:30.554870 Set Vref, RX VrefLevel [Byte0]: 47
3347 12:40:30.558458 [Byte1]: 47
3348 12:40:30.562322
3349 12:40:30.562436 Set Vref, RX VrefLevel [Byte0]: 48
3350 12:40:30.566218 [Byte1]: 48
3351 12:40:30.570792
3352 12:40:30.571473 Set Vref, RX VrefLevel [Byte0]: 49
3353 12:40:30.574419 [Byte1]: 49
3354 12:40:30.578643
3355 12:40:30.579313 Set Vref, RX VrefLevel [Byte0]: 50
3356 12:40:30.582260 [Byte1]: 50
3357 12:40:30.586926
3358 12:40:30.587497 Set Vref, RX VrefLevel [Byte0]: 51
3359 12:40:30.589887 [Byte1]: 51
3360 12:40:30.594860
3361 12:40:30.595411 Set Vref, RX VrefLevel [Byte0]: 52
3362 12:40:30.598114 [Byte1]: 52
3363 12:40:30.602513
3364 12:40:30.603082 Set Vref, RX VrefLevel [Byte0]: 53
3365 12:40:30.605524 [Byte1]: 53
3366 12:40:30.610282
3367 12:40:30.610505 Set Vref, RX VrefLevel [Byte0]: 54
3368 12:40:30.613414 [Byte1]: 54
3369 12:40:30.618018
3370 12:40:30.618197 Set Vref, RX VrefLevel [Byte0]: 55
3371 12:40:30.621841 [Byte1]: 55
3372 12:40:30.626069
3373 12:40:30.626311 Set Vref, RX VrefLevel [Byte0]: 56
3374 12:40:30.629171 [Byte1]: 56
3375 12:40:30.633970
3376 12:40:30.634146 Set Vref, RX VrefLevel [Byte0]: 57
3377 12:40:30.637435 [Byte1]: 57
3378 12:40:30.641690
3379 12:40:30.641938 Set Vref, RX VrefLevel [Byte0]: 58
3380 12:40:30.645199 [Byte1]: 58
3381 12:40:30.649594
3382 12:40:30.649842 Set Vref, RX VrefLevel [Byte0]: 59
3383 12:40:30.653236 [Byte1]: 59
3384 12:40:30.657791
3385 12:40:30.657969 Set Vref, RX VrefLevel [Byte0]: 60
3386 12:40:30.661274 [Byte1]: 60
3387 12:40:30.666013
3388 12:40:30.666257 Set Vref, RX VrefLevel [Byte0]: 61
3389 12:40:30.668853 [Byte1]: 61
3390 12:40:30.673491
3391 12:40:30.673713 Set Vref, RX VrefLevel [Byte0]: 62
3392 12:40:30.677195 [Byte1]: 62
3393 12:40:30.681576
3394 12:40:30.682198 Set Vref, RX VrefLevel [Byte0]: 63
3395 12:40:30.685189 [Byte1]: 63
3396 12:40:30.689405
3397 12:40:30.689886 Set Vref, RX VrefLevel [Byte0]: 64
3398 12:40:30.692858 [Byte1]: 64
3399 12:40:30.697577
3400 12:40:30.698002 Set Vref, RX VrefLevel [Byte0]: 65
3401 12:40:30.701170 [Byte1]: 65
3402 12:40:30.705760
3403 12:40:30.706229 Set Vref, RX VrefLevel [Byte0]: 66
3404 12:40:30.708900 [Byte1]: 66
3405 12:40:30.713298
3406 12:40:30.713727 Final RX Vref Byte 0 = 57 to rank0
3407 12:40:30.716993 Final RX Vref Byte 1 = 47 to rank0
3408 12:40:30.720122 Final RX Vref Byte 0 = 57 to rank1
3409 12:40:30.723618 Final RX Vref Byte 1 = 47 to rank1==
3410 12:40:30.726574 Dram Type= 6, Freq= 0, CH_1, rank 0
3411 12:40:30.733256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3412 12:40:30.733701 ==
3413 12:40:30.734041 DQS Delay:
3414 12:40:30.736307 DQS0 = 0, DQS1 = 0
3415 12:40:30.736903 DQM Delay:
3416 12:40:30.737413 DQM0 = 114, DQM1 = 104
3417 12:40:30.739707 DQ Delay:
3418 12:40:30.743386 DQ0 =116, DQ1 =110, DQ2 =104, DQ3 =112
3419 12:40:30.746396 DQ4 =112, DQ5 =122, DQ6 =124, DQ7 =112
3420 12:40:30.750016 DQ8 =92, DQ9 =96, DQ10 =104, DQ11 =100
3421 12:40:30.752905 DQ12 =112, DQ13 =110, DQ14 =114, DQ15 =110
3422 12:40:30.753335
3423 12:40:30.753675
3424 12:40:30.763157 [DQSOSCAuto] RK0, (LSB)MR18= 0xecf3, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 418 ps
3425 12:40:30.763406 CH1 RK0: MR19=303, MR18=ECF3
3426 12:40:30.769404 CH1_RK0: MR19=0x303, MR18=0xECF3, DQSOSC=415, MR23=63, INC=38, DEC=25
3427 12:40:30.769605
3428 12:40:30.772912 ----->DramcWriteLeveling(PI) begin...
3429 12:40:30.773074 ==
3430 12:40:30.775744 Dram Type= 6, Freq= 0, CH_1, rank 1
3431 12:40:30.782558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3432 12:40:30.782692 ==
3433 12:40:30.786155 Write leveling (Byte 0): 24 => 24
3434 12:40:30.786268 Write leveling (Byte 1): 29 => 29
3435 12:40:30.789099 DramcWriteLeveling(PI) end<-----
3436 12:40:30.789204
3437 12:40:30.789287 ==
3438 12:40:30.792737 Dram Type= 6, Freq= 0, CH_1, rank 1
3439 12:40:30.799253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3440 12:40:30.799377 ==
3441 12:40:30.802849 [Gating] SW mode calibration
3442 12:40:30.809460 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3443 12:40:30.812471 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3444 12:40:30.819054 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3445 12:40:30.822560 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3446 12:40:30.826023 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3447 12:40:30.832356 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3448 12:40:30.836030 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3449 12:40:30.839087 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3450 12:40:30.845532 0 15 24 | B1->B0 | 3434 2626 | 0 0 | (0 1) (1 0)
3451 12:40:30.849024 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
3452 12:40:30.852721 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3453 12:40:30.859348 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3454 12:40:30.862537 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3455 12:40:30.866032 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3456 12:40:30.872288 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3457 12:40:30.875806 1 0 20 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
3458 12:40:30.879209 1 0 24 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
3459 12:40:30.885360 1 0 28 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3460 12:40:30.888998 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 12:40:30.891901 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 12:40:30.898481 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 12:40:30.902159 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 12:40:30.905734 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 12:40:30.912163 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 12:40:30.915187 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3467 12:40:30.918712 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 12:40:30.925160 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 12:40:30.928539 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 12:40:30.931301 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 12:40:30.937982 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 12:40:30.941425 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 12:40:30.945352 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 12:40:30.951874 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 12:40:30.955005 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 12:40:30.958461 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 12:40:30.961435 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 12:40:30.968310 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 12:40:30.971667 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 12:40:30.974938 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 12:40:30.981354 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3482 12:40:30.984889 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3483 12:40:30.988138 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3484 12:40:30.991272 Total UI for P1: 0, mck2ui 16
3485 12:40:30.994296 best dqsien dly found for B0: ( 1, 3, 22)
3486 12:40:31.000723 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3487 12:40:31.004549 Total UI for P1: 0, mck2ui 16
3488 12:40:31.007373 best dqsien dly found for B1: ( 1, 3, 26)
3489 12:40:31.010790 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3490 12:40:31.013840 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3491 12:40:31.014025
3492 12:40:31.017451 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3493 12:40:31.020494 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3494 12:40:31.024049 [Gating] SW calibration Done
3495 12:40:31.024181 ==
3496 12:40:31.027101 Dram Type= 6, Freq= 0, CH_1, rank 1
3497 12:40:31.030539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3498 12:40:31.030673 ==
3499 12:40:31.033870 RX Vref Scan: 0
3500 12:40:31.033996
3501 12:40:31.037390 RX Vref 0 -> 0, step: 1
3502 12:40:31.037519
3503 12:40:31.037661 RX Delay -40 -> 252, step: 8
3504 12:40:31.043527 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3505 12:40:31.048127 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3506 12:40:31.049992 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3507 12:40:31.053527 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3508 12:40:31.056607 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3509 12:40:31.063376 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3510 12:40:31.067345 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3511 12:40:31.070020 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3512 12:40:31.073541 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
3513 12:40:31.076688 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3514 12:40:31.083180 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3515 12:40:31.086807 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3516 12:40:31.090217 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3517 12:40:31.093107 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3518 12:40:31.099819 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3519 12:40:31.103168 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3520 12:40:31.103254 ==
3521 12:40:31.106774 Dram Type= 6, Freq= 0, CH_1, rank 1
3522 12:40:31.109790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3523 12:40:31.109954 ==
3524 12:40:31.110021 DQS Delay:
3525 12:40:31.113055 DQS0 = 0, DQS1 = 0
3526 12:40:31.113141 DQM Delay:
3527 12:40:31.116628 DQM0 = 110, DQM1 = 106
3528 12:40:31.116718 DQ Delay:
3529 12:40:31.119595 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3530 12:40:31.123108 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3531 12:40:31.126129 DQ8 =91, DQ9 =95, DQ10 =111, DQ11 =99
3532 12:40:31.129776 DQ12 =115, DQ13 =111, DQ14 =115, DQ15 =115
3533 12:40:31.132835
3534 12:40:31.132919
3535 12:40:31.132991 ==
3536 12:40:31.136185 Dram Type= 6, Freq= 0, CH_1, rank 1
3537 12:40:31.139621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3538 12:40:31.139708 ==
3539 12:40:31.139776
3540 12:40:31.139838
3541 12:40:31.142469 TX Vref Scan disable
3542 12:40:31.142554 == TX Byte 0 ==
3543 12:40:31.149132 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3544 12:40:31.152564 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3545 12:40:31.152651 == TX Byte 1 ==
3546 12:40:31.159003 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3547 12:40:31.162693 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3548 12:40:31.162782 ==
3549 12:40:31.165751 Dram Type= 6, Freq= 0, CH_1, rank 1
3550 12:40:31.168722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3551 12:40:31.168809 ==
3552 12:40:31.182023 TX Vref=22, minBit 1, minWin=26, winSum=425
3553 12:40:31.185580 TX Vref=24, minBit 1, minWin=26, winSum=430
3554 12:40:31.188457 TX Vref=26, minBit 0, minWin=26, winSum=436
3555 12:40:31.192118 TX Vref=28, minBit 7, minWin=26, winSum=435
3556 12:40:31.195089 TX Vref=30, minBit 9, minWin=26, winSum=437
3557 12:40:31.201461 TX Vref=32, minBit 2, minWin=26, winSum=433
3558 12:40:31.204917 [TxChooseVref] Worse bit 9, Min win 26, Win sum 437, Final Vref 30
3559 12:40:31.205003
3560 12:40:31.208353 Final TX Range 1 Vref 30
3561 12:40:31.208440
3562 12:40:31.208506 ==
3563 12:40:31.211860 Dram Type= 6, Freq= 0, CH_1, rank 1
3564 12:40:31.214750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3565 12:40:31.218197 ==
3566 12:40:31.218281
3567 12:40:31.218347
3568 12:40:31.218407 TX Vref Scan disable
3569 12:40:31.221758 == TX Byte 0 ==
3570 12:40:31.225419 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3571 12:40:31.231583 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3572 12:40:31.231675 == TX Byte 1 ==
3573 12:40:31.235196 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3574 12:40:31.241753 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3575 12:40:31.241848
3576 12:40:31.241915 [DATLAT]
3577 12:40:31.241978 Freq=1200, CH1 RK1
3578 12:40:31.242039
3579 12:40:31.244566 DATLAT Default: 0xd
3580 12:40:31.247971 0, 0xFFFF, sum = 0
3581 12:40:31.248057 1, 0xFFFF, sum = 0
3582 12:40:31.251311 2, 0xFFFF, sum = 0
3583 12:40:31.251396 3, 0xFFFF, sum = 0
3584 12:40:31.254738 4, 0xFFFF, sum = 0
3585 12:40:31.254823 5, 0xFFFF, sum = 0
3586 12:40:31.258196 6, 0xFFFF, sum = 0
3587 12:40:31.258280 7, 0xFFFF, sum = 0
3588 12:40:31.261096 8, 0xFFFF, sum = 0
3589 12:40:31.261182 9, 0xFFFF, sum = 0
3590 12:40:31.264672 10, 0xFFFF, sum = 0
3591 12:40:31.264762 11, 0xFFFF, sum = 0
3592 12:40:31.268245 12, 0x0, sum = 1
3593 12:40:31.268330 13, 0x0, sum = 2
3594 12:40:31.271326 14, 0x0, sum = 3
3595 12:40:31.271409 15, 0x0, sum = 4
3596 12:40:31.274864 best_step = 13
3597 12:40:31.274971
3598 12:40:31.275062 ==
3599 12:40:31.277792 Dram Type= 6, Freq= 0, CH_1, rank 1
3600 12:40:31.281392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3601 12:40:31.281475 ==
3602 12:40:31.284458 RX Vref Scan: 0
3603 12:40:31.284541
3604 12:40:31.284607 RX Vref 0 -> 0, step: 1
3605 12:40:31.284667
3606 12:40:31.288153 RX Delay -21 -> 252, step: 4
3607 12:40:31.294327 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3608 12:40:31.298000 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3609 12:40:31.301008 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3610 12:40:31.304108 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3611 12:40:31.307680 iDelay=195, Bit 4, Center 110 (39 ~ 182) 144
3612 12:40:31.314291 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3613 12:40:31.317115 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3614 12:40:31.320469 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3615 12:40:31.323852 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
3616 12:40:31.327350 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3617 12:40:31.334113 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3618 12:40:31.337061 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3619 12:40:31.340781 iDelay=195, Bit 12, Center 116 (55 ~ 178) 124
3620 12:40:31.343838 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
3621 12:40:31.350695 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3622 12:40:31.353735 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3623 12:40:31.353859 ==
3624 12:40:31.356871 Dram Type= 6, Freq= 0, CH_1, rank 1
3625 12:40:31.360047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3626 12:40:31.360130 ==
3627 12:40:31.363426 DQS Delay:
3628 12:40:31.363522 DQS0 = 0, DQS1 = 0
3629 12:40:31.363600 DQM Delay:
3630 12:40:31.366728 DQM0 = 112, DQM1 = 108
3631 12:40:31.366812 DQ Delay:
3632 12:40:31.369952 DQ0 =114, DQ1 =110, DQ2 =100, DQ3 =108
3633 12:40:31.373550 DQ4 =110, DQ5 =120, DQ6 =122, DQ7 =112
3634 12:40:31.376654 DQ8 =94, DQ9 =100, DQ10 =110, DQ11 =102
3635 12:40:31.383299 DQ12 =116, DQ13 =114, DQ14 =116, DQ15 =116
3636 12:40:31.383382
3637 12:40:31.383447
3638 12:40:31.389908 [DQSOSCAuto] RK1, (LSB)MR18= 0xf707, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 413 ps
3639 12:40:31.393583 CH1 RK1: MR19=304, MR18=F707
3640 12:40:31.399965 CH1_RK1: MR19=0x304, MR18=0xF707, DQSOSC=407, MR23=63, INC=39, DEC=26
3641 12:40:31.402951 [RxdqsGatingPostProcess] freq 1200
3642 12:40:31.406605 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3643 12:40:31.409622 best DQS0 dly(2T, 0.5T) = (0, 11)
3644 12:40:31.413150 best DQS1 dly(2T, 0.5T) = (0, 11)
3645 12:40:31.416553 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3646 12:40:31.419894 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3647 12:40:31.423254 best DQS0 dly(2T, 0.5T) = (0, 11)
3648 12:40:31.426411 best DQS1 dly(2T, 0.5T) = (0, 11)
3649 12:40:31.429793 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3650 12:40:31.433078 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3651 12:40:31.436551 Pre-setting of DQS Precalculation
3652 12:40:31.439549 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3653 12:40:31.449785 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3654 12:40:31.455886 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3655 12:40:31.455974
3656 12:40:31.456040
3657 12:40:31.459370 [Calibration Summary] 2400 Mbps
3658 12:40:31.459453 CH 0, Rank 0
3659 12:40:31.462774 SW Impedance : PASS
3660 12:40:31.462894 DUTY Scan : NO K
3661 12:40:31.465766 ZQ Calibration : PASS
3662 12:40:31.469382 Jitter Meter : NO K
3663 12:40:31.469465 CBT Training : PASS
3664 12:40:31.472248 Write leveling : PASS
3665 12:40:31.475919 RX DQS gating : PASS
3666 12:40:31.476049 RX DQ/DQS(RDDQC) : PASS
3667 12:40:31.479306 TX DQ/DQS : PASS
3668 12:40:31.482526 RX DATLAT : PASS
3669 12:40:31.482619 RX DQ/DQS(Engine): PASS
3670 12:40:31.485382 TX OE : NO K
3671 12:40:31.485468 All Pass.
3672 12:40:31.485533
3673 12:40:31.488950 CH 0, Rank 1
3674 12:40:31.489033 SW Impedance : PASS
3675 12:40:31.491999 DUTY Scan : NO K
3676 12:40:31.495663 ZQ Calibration : PASS
3677 12:40:31.495746 Jitter Meter : NO K
3678 12:40:31.498681 CBT Training : PASS
3679 12:40:31.502349 Write leveling : PASS
3680 12:40:31.502432 RX DQS gating : PASS
3681 12:40:31.505203 RX DQ/DQS(RDDQC) : PASS
3682 12:40:31.508826 TX DQ/DQS : PASS
3683 12:40:31.508908 RX DATLAT : PASS
3684 12:40:31.511852 RX DQ/DQS(Engine): PASS
3685 12:40:31.515367 TX OE : NO K
3686 12:40:31.515449 All Pass.
3687 12:40:31.515514
3688 12:40:31.515575 CH 1, Rank 0
3689 12:40:31.518408 SW Impedance : PASS
3690 12:40:31.521904 DUTY Scan : NO K
3691 12:40:31.521986 ZQ Calibration : PASS
3692 12:40:31.525445 Jitter Meter : NO K
3693 12:40:31.528736 CBT Training : PASS
3694 12:40:31.528820 Write leveling : PASS
3695 12:40:31.531645 RX DQS gating : PASS
3696 12:40:31.534821 RX DQ/DQS(RDDQC) : PASS
3697 12:40:31.534941 TX DQ/DQS : PASS
3698 12:40:31.538246 RX DATLAT : PASS
3699 12:40:31.538328 RX DQ/DQS(Engine): PASS
3700 12:40:31.541553 TX OE : NO K
3701 12:40:31.541636 All Pass.
3702 12:40:31.541700
3703 12:40:31.544940 CH 1, Rank 1
3704 12:40:31.548444 SW Impedance : PASS
3705 12:40:31.548526 DUTY Scan : NO K
3706 12:40:31.551538 ZQ Calibration : PASS
3707 12:40:31.551621 Jitter Meter : NO K
3708 12:40:31.554510 CBT Training : PASS
3709 12:40:31.558181 Write leveling : PASS
3710 12:40:31.558263 RX DQS gating : PASS
3711 12:40:31.561179 RX DQ/DQS(RDDQC) : PASS
3712 12:40:31.564728 TX DQ/DQS : PASS
3713 12:40:31.564811 RX DATLAT : PASS
3714 12:40:31.568306 RX DQ/DQS(Engine): PASS
3715 12:40:31.571306 TX OE : NO K
3716 12:40:31.571388 All Pass.
3717 12:40:31.571454
3718 12:40:31.574646 DramC Write-DBI off
3719 12:40:31.574728 PER_BANK_REFRESH: Hybrid Mode
3720 12:40:31.577838 TX_TRACKING: ON
3721 12:40:31.584951 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3722 12:40:31.591373 [FAST_K] Save calibration result to emmc
3723 12:40:31.594610 dramc_set_vcore_voltage set vcore to 650000
3724 12:40:31.594692 Read voltage for 600, 5
3725 12:40:31.598154 Vio18 = 0
3726 12:40:31.598236 Vcore = 650000
3727 12:40:31.598302 Vdram = 0
3728 12:40:31.601238 Vddq = 0
3729 12:40:31.601319 Vmddr = 0
3730 12:40:31.604327 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3731 12:40:31.611293 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3732 12:40:31.614203 MEM_TYPE=3, freq_sel=19
3733 12:40:31.617952 sv_algorithm_assistance_LP4_1600
3734 12:40:31.621008 ============ PULL DRAM RESETB DOWN ============
3735 12:40:31.624107 ========== PULL DRAM RESETB DOWN end =========
3736 12:40:31.631120 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3737 12:40:31.633955 ===================================
3738 12:40:31.634037 LPDDR4 DRAM CONFIGURATION
3739 12:40:31.637546 ===================================
3740 12:40:31.640806 EX_ROW_EN[0] = 0x0
3741 12:40:31.644195 EX_ROW_EN[1] = 0x0
3742 12:40:31.644277 LP4Y_EN = 0x0
3743 12:40:31.647121 WORK_FSP = 0x0
3744 12:40:31.647203 WL = 0x2
3745 12:40:31.650568 RL = 0x2
3746 12:40:31.650650 BL = 0x2
3747 12:40:31.654144 RPST = 0x0
3748 12:40:31.654226 RD_PRE = 0x0
3749 12:40:31.657272 WR_PRE = 0x1
3750 12:40:31.657353 WR_PST = 0x0
3751 12:40:31.660351 DBI_WR = 0x0
3752 12:40:31.660433 DBI_RD = 0x0
3753 12:40:31.663866 OTF = 0x1
3754 12:40:31.666948 ===================================
3755 12:40:31.670766 ===================================
3756 12:40:31.670856 ANA top config
3757 12:40:31.673530 ===================================
3758 12:40:31.677057 DLL_ASYNC_EN = 0
3759 12:40:31.680429 ALL_SLAVE_EN = 1
3760 12:40:31.683693 NEW_RANK_MODE = 1
3761 12:40:31.683776 DLL_IDLE_MODE = 1
3762 12:40:31.687169 LP45_APHY_COMB_EN = 1
3763 12:40:31.690211 TX_ODT_DIS = 1
3764 12:40:31.693792 NEW_8X_MODE = 1
3765 12:40:31.696727 ===================================
3766 12:40:31.700041 ===================================
3767 12:40:31.703428 data_rate = 1200
3768 12:40:31.703510 CKR = 1
3769 12:40:31.706444 DQ_P2S_RATIO = 8
3770 12:40:31.710061 ===================================
3771 12:40:31.713112 CA_P2S_RATIO = 8
3772 12:40:31.716724 DQ_CA_OPEN = 0
3773 12:40:31.719584 DQ_SEMI_OPEN = 0
3774 12:40:31.723181 CA_SEMI_OPEN = 0
3775 12:40:31.723263 CA_FULL_RATE = 0
3776 12:40:31.726293 DQ_CKDIV4_EN = 1
3777 12:40:31.729868 CA_CKDIV4_EN = 1
3778 12:40:31.732980 CA_PREDIV_EN = 0
3779 12:40:31.736036 PH8_DLY = 0
3780 12:40:31.739672 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3781 12:40:31.739754 DQ_AAMCK_DIV = 4
3782 12:40:31.743347 CA_AAMCK_DIV = 4
3783 12:40:31.746128 CA_ADMCK_DIV = 4
3784 12:40:31.749512 DQ_TRACK_CA_EN = 0
3785 12:40:31.752942 CA_PICK = 600
3786 12:40:31.756383 CA_MCKIO = 600
3787 12:40:31.759245 MCKIO_SEMI = 0
3788 12:40:31.759327 PLL_FREQ = 2288
3789 12:40:31.762841 DQ_UI_PI_RATIO = 32
3790 12:40:31.765865 CA_UI_PI_RATIO = 0
3791 12:40:31.769543 ===================================
3792 12:40:31.772562 ===================================
3793 12:40:31.776145 memory_type:LPDDR4
3794 12:40:31.779367 GP_NUM : 10
3795 12:40:31.779449 SRAM_EN : 1
3796 12:40:31.782724 MD32_EN : 0
3797 12:40:31.785567 ===================================
3798 12:40:31.785649 [ANA_INIT] >>>>>>>>>>>>>>
3799 12:40:31.789204 <<<<<< [CONFIGURE PHASE]: ANA_TX
3800 12:40:31.792208 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3801 12:40:31.795674 ===================================
3802 12:40:31.798584 data_rate = 1200,PCW = 0X5800
3803 12:40:31.802315 ===================================
3804 12:40:31.805647 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3805 12:40:31.812117 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3806 12:40:31.818778 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3807 12:40:31.821956 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3808 12:40:31.825081 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3809 12:40:31.828768 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3810 12:40:31.831783 [ANA_INIT] flow start
3811 12:40:31.831865 [ANA_INIT] PLL >>>>>>>>
3812 12:40:31.835403 [ANA_INIT] PLL <<<<<<<<
3813 12:40:31.838519 [ANA_INIT] MIDPI >>>>>>>>
3814 12:40:31.841531 [ANA_INIT] MIDPI <<<<<<<<
3815 12:40:31.841613 [ANA_INIT] DLL >>>>>>>>
3816 12:40:31.845154 [ANA_INIT] flow end
3817 12:40:31.848216 ============ LP4 DIFF to SE enter ============
3818 12:40:31.851792 ============ LP4 DIFF to SE exit ============
3819 12:40:31.854606 [ANA_INIT] <<<<<<<<<<<<<
3820 12:40:31.857968 [Flow] Enable top DCM control >>>>>
3821 12:40:31.861350 [Flow] Enable top DCM control <<<<<
3822 12:40:31.864729 Enable DLL master slave shuffle
3823 12:40:31.871676 ==============================================================
3824 12:40:31.871759 Gating Mode config
3825 12:40:31.877891 ==============================================================
3826 12:40:31.877973 Config description:
3827 12:40:31.887906 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3828 12:40:31.894428 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3829 12:40:31.901241 SELPH_MODE 0: By rank 1: By Phase
3830 12:40:31.904829 ==============================================================
3831 12:40:31.907601 GAT_TRACK_EN = 1
3832 12:40:31.911156 RX_GATING_MODE = 2
3833 12:40:31.914055 RX_GATING_TRACK_MODE = 2
3834 12:40:31.917610 SELPH_MODE = 1
3835 12:40:31.920682 PICG_EARLY_EN = 1
3836 12:40:31.924296 VALID_LAT_VALUE = 1
3837 12:40:31.930391 ==============================================================
3838 12:40:31.933619 Enter into Gating configuration >>>>
3839 12:40:31.937233 Exit from Gating configuration <<<<
3840 12:40:31.940282 Enter into DVFS_PRE_config >>>>>
3841 12:40:31.950477 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3842 12:40:31.953454 Exit from DVFS_PRE_config <<<<<
3843 12:40:31.957037 Enter into PICG configuration >>>>
3844 12:40:31.959959 Exit from PICG configuration <<<<
3845 12:40:31.963596 [RX_INPUT] configuration >>>>>
3846 12:40:31.966848 [RX_INPUT] configuration <<<<<
3847 12:40:31.969955 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3848 12:40:31.976310 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3849 12:40:31.982725 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3850 12:40:31.989827 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3851 12:40:31.993043 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3852 12:40:31.999505 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3853 12:40:32.002453 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3854 12:40:32.009646 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3855 12:40:32.012609 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3856 12:40:32.016188 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3857 12:40:32.019746 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3858 12:40:32.026069 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3859 12:40:32.029101 ===================================
3860 12:40:32.032626 LPDDR4 DRAM CONFIGURATION
3861 12:40:32.036188 ===================================
3862 12:40:32.036268 EX_ROW_EN[0] = 0x0
3863 12:40:32.038950 EX_ROW_EN[1] = 0x0
3864 12:40:32.039031 LP4Y_EN = 0x0
3865 12:40:32.042439 WORK_FSP = 0x0
3866 12:40:32.042519 WL = 0x2
3867 12:40:32.046024 RL = 0x2
3868 12:40:32.046104 BL = 0x2
3869 12:40:32.049093 RPST = 0x0
3870 12:40:32.049173 RD_PRE = 0x0
3871 12:40:32.052815 WR_PRE = 0x1
3872 12:40:32.052895 WR_PST = 0x0
3873 12:40:32.055765 DBI_WR = 0x0
3874 12:40:32.055845 DBI_RD = 0x0
3875 12:40:32.059391 OTF = 0x1
3876 12:40:32.062389 ===================================
3877 12:40:32.065371 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3878 12:40:32.068988 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3879 12:40:32.075568 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3880 12:40:32.079100 ===================================
3881 12:40:32.079182 LPDDR4 DRAM CONFIGURATION
3882 12:40:32.082686 ===================================
3883 12:40:32.085829 EX_ROW_EN[0] = 0x10
3884 12:40:32.088652 EX_ROW_EN[1] = 0x0
3885 12:40:32.088734 LP4Y_EN = 0x0
3886 12:40:32.092273 WORK_FSP = 0x0
3887 12:40:32.092355 WL = 0x2
3888 12:40:32.095266 RL = 0x2
3889 12:40:32.095348 BL = 0x2
3890 12:40:32.098700 RPST = 0x0
3891 12:40:32.098785 RD_PRE = 0x0
3892 12:40:32.102186 WR_PRE = 0x1
3893 12:40:32.102268 WR_PST = 0x0
3894 12:40:32.105297 DBI_WR = 0x0
3895 12:40:32.105379 DBI_RD = 0x0
3896 12:40:32.108923 OTF = 0x1
3897 12:40:32.111790 ===================================
3898 12:40:32.118316 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3899 12:40:32.121902 nWR fixed to 30
3900 12:40:32.125315 [ModeRegInit_LP4] CH0 RK0
3901 12:40:32.125397 [ModeRegInit_LP4] CH0 RK1
3902 12:40:32.128287 [ModeRegInit_LP4] CH1 RK0
3903 12:40:32.131884 [ModeRegInit_LP4] CH1 RK1
3904 12:40:32.131966 match AC timing 17
3905 12:40:32.138541 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3906 12:40:32.141431 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3907 12:40:32.144935 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3908 12:40:32.151383 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3909 12:40:32.155016 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3910 12:40:32.155098 ==
3911 12:40:32.158086 Dram Type= 6, Freq= 0, CH_0, rank 0
3912 12:40:32.161696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3913 12:40:32.161778 ==
3914 12:40:32.168271 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3915 12:40:32.174311 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3916 12:40:32.177660 [CA 0] Center 37 (7~67) winsize 61
3917 12:40:32.181120 [CA 1] Center 36 (6~67) winsize 62
3918 12:40:32.184684 [CA 2] Center 35 (5~65) winsize 61
3919 12:40:32.187621 [CA 3] Center 35 (5~65) winsize 61
3920 12:40:32.191039 [CA 4] Center 34 (4~65) winsize 62
3921 12:40:32.194284 [CA 5] Center 34 (4~64) winsize 61
3922 12:40:32.194365
3923 12:40:32.197668 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3924 12:40:32.197749
3925 12:40:32.200886 [CATrainingPosCal] consider 1 rank data
3926 12:40:32.204510 u2DelayCellTimex100 = 270/100 ps
3927 12:40:32.207942 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3928 12:40:32.210815 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
3929 12:40:32.214433 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3930 12:40:32.217442 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3931 12:40:32.224111 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3932 12:40:32.227574 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3933 12:40:32.227656
3934 12:40:32.230915 CA PerBit enable=1, Macro0, CA PI delay=34
3935 12:40:32.230997
3936 12:40:32.233774 [CBTSetCACLKResult] CA Dly = 34
3937 12:40:32.233856 CS Dly: 6 (0~37)
3938 12:40:32.233922 ==
3939 12:40:32.237152 Dram Type= 6, Freq= 0, CH_0, rank 1
3940 12:40:32.243806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3941 12:40:32.243888 ==
3942 12:40:32.247428 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3943 12:40:32.253736 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3944 12:40:32.257254 [CA 0] Center 37 (7~67) winsize 61
3945 12:40:32.260377 [CA 1] Center 37 (7~67) winsize 61
3946 12:40:32.264080 [CA 2] Center 35 (5~65) winsize 61
3947 12:40:32.267158 [CA 3] Center 35 (5~65) winsize 61
3948 12:40:32.270158 [CA 4] Center 34 (3~65) winsize 63
3949 12:40:32.273690 [CA 5] Center 33 (3~64) winsize 62
3950 12:40:32.273772
3951 12:40:32.277206 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3952 12:40:32.277288
3953 12:40:32.280212 [CATrainingPosCal] consider 2 rank data
3954 12:40:32.283701 u2DelayCellTimex100 = 270/100 ps
3955 12:40:32.286701 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3956 12:40:32.293270 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3957 12:40:32.296945 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3958 12:40:32.299950 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3959 12:40:32.303302 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3960 12:40:32.306675 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3961 12:40:32.306756
3962 12:40:32.310013 CA PerBit enable=1, Macro0, CA PI delay=34
3963 12:40:32.310094
3964 12:40:32.313328 [CBTSetCACLKResult] CA Dly = 34
3965 12:40:32.316842 CS Dly: 6 (0~37)
3966 12:40:32.316960
3967 12:40:32.319624 ----->DramcWriteLeveling(PI) begin...
3968 12:40:32.319728 ==
3969 12:40:32.323308 Dram Type= 6, Freq= 0, CH_0, rank 0
3970 12:40:32.327162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3971 12:40:32.327275 ==
3972 12:40:32.329625 Write leveling (Byte 0): 30 => 30
3973 12:40:32.333107 Write leveling (Byte 1): 30 => 30
3974 12:40:32.336618 DramcWriteLeveling(PI) end<-----
3975 12:40:32.336727
3976 12:40:32.336819 ==
3977 12:40:32.339552 Dram Type= 6, Freq= 0, CH_0, rank 0
3978 12:40:32.343142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3979 12:40:32.343226 ==
3980 12:40:32.346199 [Gating] SW mode calibration
3981 12:40:32.352990 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3982 12:40:32.359597 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3983 12:40:32.362520 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3984 12:40:32.366081 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3985 12:40:32.372734 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3986 12:40:32.375713 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3987 12:40:32.379336 0 9 16 | B1->B0 | 3434 2828 | 1 1 | (1 0) (1 0)
3988 12:40:32.385829 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 12:40:32.389270 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 12:40:32.392386 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 12:40:32.398754 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 12:40:32.402080 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3993 12:40:32.405622 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3994 12:40:32.411872 0 10 12 | B1->B0 | 2424 2b2b | 0 1 | (0 0) (0 0)
3995 12:40:32.415158 0 10 16 | B1->B0 | 2e2e 4141 | 1 0 | (0 0) (0 0)
3996 12:40:32.418593 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 12:40:32.425167 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 12:40:32.428147 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 12:40:32.431845 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 12:40:32.438116 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 12:40:32.441422 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 12:40:32.444983 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 12:40:32.451687 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4004 12:40:32.454756 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 12:40:32.458374 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 12:40:32.464529 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 12:40:32.467833 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 12:40:32.471437 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 12:40:32.477582 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 12:40:32.481176 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 12:40:32.484164 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 12:40:32.491290 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 12:40:32.494244 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 12:40:32.497846 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 12:40:32.504386 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 12:40:32.507300 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 12:40:32.511005 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 12:40:32.517375 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4019 12:40:32.520980 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 12:40:32.524451 Total UI for P1: 0, mck2ui 16
4021 12:40:32.527110 best dqsien dly found for B0: ( 0, 13, 12)
4022 12:40:32.530596 Total UI for P1: 0, mck2ui 16
4023 12:40:32.534097 best dqsien dly found for B1: ( 0, 13, 14)
4024 12:40:32.537113 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4025 12:40:32.540796 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4026 12:40:32.540879
4027 12:40:32.543793 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4028 12:40:32.550165 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4029 12:40:32.550248 [Gating] SW calibration Done
4030 12:40:32.550314 ==
4031 12:40:32.553641 Dram Type= 6, Freq= 0, CH_0, rank 0
4032 12:40:32.560332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4033 12:40:32.560416 ==
4034 12:40:32.560483 RX Vref Scan: 0
4035 12:40:32.560543
4036 12:40:32.563292 RX Vref 0 -> 0, step: 1
4037 12:40:32.563375
4038 12:40:32.567006 RX Delay -230 -> 252, step: 16
4039 12:40:32.569980 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4040 12:40:32.573357 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4041 12:40:32.580225 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4042 12:40:32.583213 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4043 12:40:32.586741 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4044 12:40:32.589738 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4045 12:40:32.596387 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4046 12:40:32.600030 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4047 12:40:32.603052 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4048 12:40:32.606000 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4049 12:40:32.609529 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4050 12:40:32.616121 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4051 12:40:32.619173 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4052 12:40:32.622794 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4053 12:40:32.629305 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4054 12:40:32.632917 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4055 12:40:32.633002 ==
4056 12:40:32.635673 Dram Type= 6, Freq= 0, CH_0, rank 0
4057 12:40:32.639063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4058 12:40:32.639147 ==
4059 12:40:32.642399 DQS Delay:
4060 12:40:32.642484 DQS0 = 0, DQS1 = 0
4061 12:40:32.642569 DQM Delay:
4062 12:40:32.646018 DQM0 = 40, DQM1 = 31
4063 12:40:32.646102 DQ Delay:
4064 12:40:32.648923 DQ0 =33, DQ1 =41, DQ2 =41, DQ3 =41
4065 12:40:32.652633 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4066 12:40:32.655634 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4067 12:40:32.658868 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4068 12:40:32.658979
4069 12:40:32.659084
4070 12:40:32.659219 ==
4071 12:40:32.662473 Dram Type= 6, Freq= 0, CH_0, rank 0
4072 12:40:32.668760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4073 12:40:32.668876 ==
4074 12:40:32.668960
4075 12:40:32.669021
4076 12:40:32.669092 TX Vref Scan disable
4077 12:40:32.672332 == TX Byte 0 ==
4078 12:40:32.675934 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4079 12:40:32.682374 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4080 12:40:32.682479 == TX Byte 1 ==
4081 12:40:32.685408 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4082 12:40:32.692362 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4083 12:40:32.692440 ==
4084 12:40:32.695257 Dram Type= 6, Freq= 0, CH_0, rank 0
4085 12:40:32.698778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4086 12:40:32.698915 ==
4087 12:40:32.699010
4088 12:40:32.699084
4089 12:40:32.701832 TX Vref Scan disable
4090 12:40:32.705127 == TX Byte 0 ==
4091 12:40:32.708701 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4092 12:40:32.711620 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4093 12:40:32.715129 == TX Byte 1 ==
4094 12:40:32.718176 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4095 12:40:32.721974 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4096 12:40:32.722099
4097 12:40:32.722211 [DATLAT]
4098 12:40:32.724975 Freq=600, CH0 RK0
4099 12:40:32.725075
4100 12:40:32.728511 DATLAT Default: 0x9
4101 12:40:32.728629 0, 0xFFFF, sum = 0
4102 12:40:32.731502 1, 0xFFFF, sum = 0
4103 12:40:32.731580 2, 0xFFFF, sum = 0
4104 12:40:32.734539 3, 0xFFFF, sum = 0
4105 12:40:32.734656 4, 0xFFFF, sum = 0
4106 12:40:32.738130 5, 0xFFFF, sum = 0
4107 12:40:32.738207 6, 0xFFFF, sum = 0
4108 12:40:32.741130 7, 0xFFFF, sum = 0
4109 12:40:32.741268 8, 0x0, sum = 1
4110 12:40:32.744586 9, 0x0, sum = 2
4111 12:40:32.744728 10, 0x0, sum = 3
4112 12:40:32.747981 11, 0x0, sum = 4
4113 12:40:32.748067 best_step = 9
4114 12:40:32.748155
4115 12:40:32.748231 ==
4116 12:40:32.751093 Dram Type= 6, Freq= 0, CH_0, rank 0
4117 12:40:32.754617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4118 12:40:32.754737 ==
4119 12:40:32.757681 RX Vref Scan: 1
4120 12:40:32.757758
4121 12:40:32.761489 RX Vref 0 -> 0, step: 1
4122 12:40:32.761564
4123 12:40:32.761626 RX Delay -195 -> 252, step: 8
4124 12:40:32.764519
4125 12:40:32.764601 Set Vref, RX VrefLevel [Byte0]: 60
4126 12:40:32.768011 [Byte1]: 46
4127 12:40:32.772576
4128 12:40:32.772660 Final RX Vref Byte 0 = 60 to rank0
4129 12:40:32.775982 Final RX Vref Byte 1 = 46 to rank0
4130 12:40:32.779527 Final RX Vref Byte 0 = 60 to rank1
4131 12:40:32.782493 Final RX Vref Byte 1 = 46 to rank1==
4132 12:40:32.785879 Dram Type= 6, Freq= 0, CH_0, rank 0
4133 12:40:32.792590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 12:40:32.792676 ==
4135 12:40:32.792743 DQS Delay:
4136 12:40:32.796180 DQS0 = 0, DQS1 = 0
4137 12:40:32.796264 DQM Delay:
4138 12:40:32.796331 DQM0 = 36, DQM1 = 29
4139 12:40:32.799166 DQ Delay:
4140 12:40:32.802613 DQ0 =36, DQ1 =40, DQ2 =36, DQ3 =32
4141 12:40:32.805623 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4142 12:40:32.809193 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =24
4143 12:40:32.812269 DQ12 =36, DQ13 =32, DQ14 =40, DQ15 =36
4144 12:40:32.812353
4145 12:40:32.812420
4146 12:40:32.818709 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d3c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
4147 12:40:32.822390 CH0 RK0: MR19=808, MR18=3D3C
4148 12:40:32.828500 CH0_RK0: MR19=0x808, MR18=0x3D3C, DQSOSC=398, MR23=63, INC=165, DEC=110
4149 12:40:32.828586
4150 12:40:32.832143 ----->DramcWriteLeveling(PI) begin...
4151 12:40:32.832230 ==
4152 12:40:32.835183 Dram Type= 6, Freq= 0, CH_0, rank 1
4153 12:40:32.838818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4154 12:40:32.838911 ==
4155 12:40:32.842009 Write leveling (Byte 0): 32 => 32
4156 12:40:32.845074 Write leveling (Byte 1): 31 => 31
4157 12:40:32.848583 DramcWriteLeveling(PI) end<-----
4158 12:40:32.848695
4159 12:40:32.848795 ==
4160 12:40:32.851988 Dram Type= 6, Freq= 0, CH_0, rank 1
4161 12:40:32.858626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 12:40:32.858712 ==
4163 12:40:32.858780 [Gating] SW mode calibration
4164 12:40:32.868190 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4165 12:40:32.871777 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4166 12:40:32.875275 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4167 12:40:32.881708 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4168 12:40:32.884671 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4169 12:40:32.888307 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
4170 12:40:32.894630 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (0 0)
4171 12:40:32.898304 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 12:40:32.901116 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4173 12:40:32.907662 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 12:40:32.911328 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 12:40:32.914138 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4176 12:40:32.921259 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4177 12:40:32.924397 0 10 12 | B1->B0 | 2c2c 3030 | 0 0 | (0 0) (0 0)
4178 12:40:32.927615 0 10 16 | B1->B0 | 3737 4141 | 1 0 | (0 0) (1 1)
4179 12:40:32.934105 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 12:40:32.937111 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 12:40:32.940726 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 12:40:32.947557 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 12:40:32.950768 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 12:40:32.953839 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 12:40:32.960596 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4186 12:40:32.963999 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 12:40:32.967271 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 12:40:32.973738 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 12:40:32.976796 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 12:40:32.980178 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 12:40:32.986955 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 12:40:32.990224 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 12:40:32.993333 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 12:40:32.999749 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 12:40:33.003083 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 12:40:33.006590 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 12:40:33.012970 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 12:40:33.016513 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 12:40:33.023071 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 12:40:33.026543 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 12:40:33.029343 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 12:40:33.036029 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4203 12:40:33.036127 Total UI for P1: 0, mck2ui 16
4204 12:40:33.039105 best dqsien dly found for B0: ( 0, 13, 14)
4205 12:40:33.045856 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 12:40:33.049533 Total UI for P1: 0, mck2ui 16
4207 12:40:33.052686 best dqsien dly found for B1: ( 0, 13, 16)
4208 12:40:33.055783 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4209 12:40:33.058872 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4210 12:40:33.058975
4211 12:40:33.062471 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4212 12:40:33.065968 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4213 12:40:33.068764 [Gating] SW calibration Done
4214 12:40:33.068868 ==
4215 12:40:33.072219 Dram Type= 6, Freq= 0, CH_0, rank 1
4216 12:40:33.075545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4217 12:40:33.079043 ==
4218 12:40:33.079127 RX Vref Scan: 0
4219 12:40:33.079193
4220 12:40:33.082004 RX Vref 0 -> 0, step: 1
4221 12:40:33.082087
4222 12:40:33.085585 RX Delay -230 -> 252, step: 16
4223 12:40:33.088904 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4224 12:40:33.091897 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4225 12:40:33.095529 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4226 12:40:33.102133 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4227 12:40:33.105070 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4228 12:40:33.108446 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4229 12:40:33.111709 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4230 12:40:33.115105 iDelay=218, Bit 7, Center 41 (-134 ~ 217) 352
4231 12:40:33.122015 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4232 12:40:33.124975 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4233 12:40:33.128549 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4234 12:40:33.131959 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4235 12:40:33.138026 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4236 12:40:33.141772 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4237 12:40:33.144845 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4238 12:40:33.147852 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4239 12:40:33.151497 ==
4240 12:40:33.154457 Dram Type= 6, Freq= 0, CH_0, rank 1
4241 12:40:33.158100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4242 12:40:33.158189 ==
4243 12:40:33.158255 DQS Delay:
4244 12:40:33.161209 DQS0 = 0, DQS1 = 0
4245 12:40:33.161295 DQM Delay:
4246 12:40:33.164696 DQM0 = 34, DQM1 = 28
4247 12:40:33.164776 DQ Delay:
4248 12:40:33.167846 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4249 12:40:33.171544 DQ4 =33, DQ5 =25, DQ6 =41, DQ7 =41
4250 12:40:33.174499 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4251 12:40:33.178107 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4252 12:40:33.178183
4253 12:40:33.178247
4254 12:40:33.178306 ==
4255 12:40:33.180857 Dram Type= 6, Freq= 0, CH_0, rank 1
4256 12:40:33.184180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4257 12:40:33.184265 ==
4258 12:40:33.184331
4259 12:40:33.184390
4260 12:40:33.187631 TX Vref Scan disable
4261 12:40:33.191163 == TX Byte 0 ==
4262 12:40:33.194207 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4263 12:40:33.197719 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4264 12:40:33.201225 == TX Byte 1 ==
4265 12:40:33.203944 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4266 12:40:33.207581 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4267 12:40:33.207665 ==
4268 12:40:33.210602 Dram Type= 6, Freq= 0, CH_0, rank 1
4269 12:40:33.217067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4270 12:40:33.217151 ==
4271 12:40:33.217216
4272 12:40:33.217278
4273 12:40:33.217337 TX Vref Scan disable
4274 12:40:33.221885 == TX Byte 0 ==
4275 12:40:33.224836 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4276 12:40:33.231816 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4277 12:40:33.231904 == TX Byte 1 ==
4278 12:40:33.234766 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4279 12:40:33.241588 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4280 12:40:33.241672
4281 12:40:33.241737 [DATLAT]
4282 12:40:33.241798 Freq=600, CH0 RK1
4283 12:40:33.241858
4284 12:40:33.244623 DATLAT Default: 0x9
4285 12:40:33.244705 0, 0xFFFF, sum = 0
4286 12:40:33.248273 1, 0xFFFF, sum = 0
4287 12:40:33.251260 2, 0xFFFF, sum = 0
4288 12:40:33.251343 3, 0xFFFF, sum = 0
4289 12:40:33.254917 4, 0xFFFF, sum = 0
4290 12:40:33.255001 5, 0xFFFF, sum = 0
4291 12:40:33.257840 6, 0xFFFF, sum = 0
4292 12:40:33.257923 7, 0xFFFF, sum = 0
4293 12:40:33.260945 8, 0x0, sum = 1
4294 12:40:33.261027 9, 0x0, sum = 2
4295 12:40:33.264632 10, 0x0, sum = 3
4296 12:40:33.264714 11, 0x0, sum = 4
4297 12:40:33.264779 best_step = 9
4298 12:40:33.264838
4299 12:40:33.267713 ==
4300 12:40:33.267794 Dram Type= 6, Freq= 0, CH_0, rank 1
4301 12:40:33.274296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4302 12:40:33.274377 ==
4303 12:40:33.274451 RX Vref Scan: 0
4304 12:40:33.274512
4305 12:40:33.277652 RX Vref 0 -> 0, step: 1
4306 12:40:33.277733
4307 12:40:33.281193 RX Delay -195 -> 252, step: 8
4308 12:40:33.287780 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4309 12:40:33.291185 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4310 12:40:33.294523 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4311 12:40:33.297457 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4312 12:40:33.300803 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4313 12:40:33.307278 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4314 12:40:33.310643 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4315 12:40:33.314278 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4316 12:40:33.317277 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4317 12:40:33.324010 iDelay=205, Bit 9, Center 12 (-139 ~ 164) 304
4318 12:40:33.327524 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4319 12:40:33.330774 iDelay=205, Bit 11, Center 16 (-139 ~ 172) 312
4320 12:40:33.334247 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4321 12:40:33.340655 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4322 12:40:33.343791 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4323 12:40:33.347456 iDelay=205, Bit 15, Center 32 (-123 ~ 188) 312
4324 12:40:33.347537 ==
4325 12:40:33.350491 Dram Type= 6, Freq= 0, CH_0, rank 1
4326 12:40:33.353581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4327 12:40:33.357166 ==
4328 12:40:33.357246 DQS Delay:
4329 12:40:33.357309 DQS0 = 0, DQS1 = 0
4330 12:40:33.360203 DQM Delay:
4331 12:40:33.360283 DQM0 = 34, DQM1 = 27
4332 12:40:33.363685 DQ Delay:
4333 12:40:33.363779 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4334 12:40:33.366793 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4335 12:40:33.370564 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =16
4336 12:40:33.373602 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =32
4337 12:40:33.373683
4338 12:40:33.377251
4339 12:40:33.383725 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b3a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4340 12:40:33.386750 CH0 RK1: MR19=808, MR18=6B3A
4341 12:40:33.393360 CH0_RK1: MR19=0x808, MR18=0x6B3A, DQSOSC=389, MR23=63, INC=173, DEC=115
4342 12:40:33.396921 [RxdqsGatingPostProcess] freq 600
4343 12:40:33.399728 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4344 12:40:33.403211 Pre-setting of DQS Precalculation
4345 12:40:33.410061 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4346 12:40:33.410145 ==
4347 12:40:33.413032 Dram Type= 6, Freq= 0, CH_1, rank 0
4348 12:40:33.416581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4349 12:40:33.416695 ==
4350 12:40:33.423029 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4351 12:40:33.426126 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4352 12:40:33.430769 [CA 0] Center 36 (6~66) winsize 61
4353 12:40:33.433759 [CA 1] Center 36 (6~66) winsize 61
4354 12:40:33.437376 [CA 2] Center 34 (4~65) winsize 62
4355 12:40:33.440329 [CA 3] Center 34 (4~65) winsize 62
4356 12:40:33.443765 [CA 4] Center 34 (4~65) winsize 62
4357 12:40:33.447185 [CA 5] Center 33 (3~64) winsize 62
4358 12:40:33.447267
4359 12:40:33.450602 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4360 12:40:33.450719
4361 12:40:33.453602 [CATrainingPosCal] consider 1 rank data
4362 12:40:33.457325 u2DelayCellTimex100 = 270/100 ps
4363 12:40:33.460471 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4364 12:40:33.467092 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4365 12:40:33.470140 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4366 12:40:33.473156 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4367 12:40:33.476810 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4368 12:40:33.479654 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4369 12:40:33.479735
4370 12:40:33.483262 CA PerBit enable=1, Macro0, CA PI delay=33
4371 12:40:33.483356
4372 12:40:33.486744 [CBTSetCACLKResult] CA Dly = 33
4373 12:40:33.489933 CS Dly: 4 (0~35)
4374 12:40:33.490014 ==
4375 12:40:33.492987 Dram Type= 6, Freq= 0, CH_1, rank 1
4376 12:40:33.496536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4377 12:40:33.496626 ==
4378 12:40:33.502865 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4379 12:40:33.506422 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4380 12:40:33.510523 [CA 0] Center 36 (6~66) winsize 61
4381 12:40:33.514182 [CA 1] Center 35 (5~66) winsize 62
4382 12:40:33.517503 [CA 2] Center 34 (4~65) winsize 62
4383 12:40:33.520503 [CA 3] Center 34 (3~65) winsize 63
4384 12:40:33.523982 [CA 4] Center 34 (4~65) winsize 62
4385 12:40:33.527514 [CA 5] Center 34 (3~65) winsize 63
4386 12:40:33.527592
4387 12:40:33.530439 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4388 12:40:33.530520
4389 12:40:33.533938 [CATrainingPosCal] consider 2 rank data
4390 12:40:33.536924 u2DelayCellTimex100 = 270/100 ps
4391 12:40:33.540551 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4392 12:40:33.547149 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4393 12:40:33.550582 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4394 12:40:33.553428 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4395 12:40:33.556977 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4396 12:40:33.560589 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4397 12:40:33.560674
4398 12:40:33.563585 CA PerBit enable=1, Macro0, CA PI delay=33
4399 12:40:33.563668
4400 12:40:33.566698 [CBTSetCACLKResult] CA Dly = 33
4401 12:40:33.570304 CS Dly: 4 (0~36)
4402 12:40:33.570387
4403 12:40:33.573849 ----->DramcWriteLeveling(PI) begin...
4404 12:40:33.573933 ==
4405 12:40:33.576897 Dram Type= 6, Freq= 0, CH_1, rank 0
4406 12:40:33.579882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4407 12:40:33.579967 ==
4408 12:40:33.583495 Write leveling (Byte 0): 29 => 29
4409 12:40:33.586668 Write leveling (Byte 1): 32 => 32
4410 12:40:33.590231 DramcWriteLeveling(PI) end<-----
4411 12:40:33.590314
4412 12:40:33.590380 ==
4413 12:40:33.593174 Dram Type= 6, Freq= 0, CH_1, rank 0
4414 12:40:33.596291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4415 12:40:33.596375 ==
4416 12:40:33.599988 [Gating] SW mode calibration
4417 12:40:33.606393 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4418 12:40:33.612637 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4419 12:40:33.616248 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4420 12:40:33.619424 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4421 12:40:33.626207 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4422 12:40:33.629109 0 9 12 | B1->B0 | 3131 3131 | 0 0 | (0 0) (0 0)
4423 12:40:33.632576 0 9 16 | B1->B0 | 2a2a 2828 | 0 0 | (1 1) (0 0)
4424 12:40:33.638973 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 12:40:33.642443 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 12:40:33.646052 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 12:40:33.652086 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4428 12:40:33.655632 0 10 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4429 12:40:33.659034 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4430 12:40:33.665876 0 10 12 | B1->B0 | 2f2f 2b2b | 0 1 | (0 0) (0 0)
4431 12:40:33.668811 0 10 16 | B1->B0 | 4545 4444 | 0 0 | (0 0) (1 1)
4432 12:40:33.672313 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 12:40:33.678494 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 12:40:33.682223 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 12:40:33.688806 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 12:40:33.691845 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 12:40:33.695400 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 12:40:33.698411 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4439 12:40:33.705171 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4440 12:40:33.708111 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 12:40:33.715203 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 12:40:33.718267 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 12:40:33.721313 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 12:40:33.728247 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 12:40:33.731231 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 12:40:33.734599 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 12:40:33.741397 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 12:40:33.744324 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 12:40:33.747762 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 12:40:33.754078 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 12:40:33.757810 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 12:40:33.761022 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 12:40:33.767431 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 12:40:33.770742 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4455 12:40:33.773907 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 12:40:33.777090 Total UI for P1: 0, mck2ui 16
4457 12:40:33.780366 best dqsien dly found for B0: ( 0, 13, 12)
4458 12:40:33.784155 Total UI for P1: 0, mck2ui 16
4459 12:40:33.787193 best dqsien dly found for B1: ( 0, 13, 12)
4460 12:40:33.790182 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4461 12:40:33.794035 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4462 12:40:33.794114
4463 12:40:33.800597 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4464 12:40:33.803925 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4465 12:40:33.806755 [Gating] SW calibration Done
4466 12:40:33.806891 ==
4467 12:40:33.810036 Dram Type= 6, Freq= 0, CH_1, rank 0
4468 12:40:33.813577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4469 12:40:33.813689 ==
4470 12:40:33.813788 RX Vref Scan: 0
4471 12:40:33.813879
4472 12:40:33.816651 RX Vref 0 -> 0, step: 1
4473 12:40:33.816763
4474 12:40:33.819697 RX Delay -230 -> 252, step: 16
4475 12:40:33.823169 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4476 12:40:33.829955 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4477 12:40:33.833003 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4478 12:40:33.836106 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4479 12:40:33.839691 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4480 12:40:33.843466 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4481 12:40:33.849402 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4482 12:40:33.852798 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4483 12:40:33.856250 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4484 12:40:33.859146 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4485 12:40:33.865733 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4486 12:40:33.869489 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4487 12:40:33.872506 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4488 12:40:33.875939 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4489 12:40:33.882367 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4490 12:40:33.885869 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4491 12:40:33.885954 ==
4492 12:40:33.888927 Dram Type= 6, Freq= 0, CH_1, rank 0
4493 12:40:33.892597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4494 12:40:33.892691 ==
4495 12:40:33.895865 DQS Delay:
4496 12:40:33.895982 DQS0 = 0, DQS1 = 0
4497 12:40:33.896071 DQM Delay:
4498 12:40:33.898928 DQM0 = 38, DQM1 = 28
4499 12:40:33.899014 DQ Delay:
4500 12:40:33.902563 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4501 12:40:33.905543 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4502 12:40:33.908659 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4503 12:40:33.912299 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4504 12:40:33.912383
4505 12:40:33.912449
4506 12:40:33.912510 ==
4507 12:40:33.915402 Dram Type= 6, Freq= 0, CH_1, rank 0
4508 12:40:33.921888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4509 12:40:33.921974 ==
4510 12:40:33.922041
4511 12:40:33.922103
4512 12:40:33.925316 TX Vref Scan disable
4513 12:40:33.925401 == TX Byte 0 ==
4514 12:40:33.931524 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4515 12:40:33.935174 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4516 12:40:33.935259 == TX Byte 1 ==
4517 12:40:33.941719 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4518 12:40:33.944608 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4519 12:40:33.944687 ==
4520 12:40:33.948152 Dram Type= 6, Freq= 0, CH_1, rank 0
4521 12:40:33.951953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4522 12:40:33.952039 ==
4523 12:40:33.952107
4524 12:40:33.952170
4525 12:40:33.954534 TX Vref Scan disable
4526 12:40:33.958128 == TX Byte 0 ==
4527 12:40:33.961033 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4528 12:40:33.964602 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4529 12:40:33.967564 == TX Byte 1 ==
4530 12:40:33.971262 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4531 12:40:33.977737 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4532 12:40:33.977835
4533 12:40:33.977912 [DATLAT]
4534 12:40:33.977977 Freq=600, CH1 RK0
4535 12:40:33.978037
4536 12:40:33.980801 DATLAT Default: 0x9
4537 12:40:33.980885 0, 0xFFFF, sum = 0
4538 12:40:33.984457 1, 0xFFFF, sum = 0
4539 12:40:33.984541 2, 0xFFFF, sum = 0
4540 12:40:33.987339 3, 0xFFFF, sum = 0
4541 12:40:33.990604 4, 0xFFFF, sum = 0
4542 12:40:33.990719 5, 0xFFFF, sum = 0
4543 12:40:33.994241 6, 0xFFFF, sum = 0
4544 12:40:33.994350 7, 0xFFFF, sum = 0
4545 12:40:33.997439 8, 0x0, sum = 1
4546 12:40:33.997545 9, 0x0, sum = 2
4547 12:40:33.997644 10, 0x0, sum = 3
4548 12:40:34.000425 11, 0x0, sum = 4
4549 12:40:34.000505 best_step = 9
4550 12:40:34.000573
4551 12:40:34.000633 ==
4552 12:40:34.004109 Dram Type= 6, Freq= 0, CH_1, rank 0
4553 12:40:34.010644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4554 12:40:34.010804 ==
4555 12:40:34.010968 RX Vref Scan: 1
4556 12:40:34.011067
4557 12:40:34.013810 RX Vref 0 -> 0, step: 1
4558 12:40:34.013938
4559 12:40:34.016866 RX Delay -195 -> 252, step: 8
4560 12:40:34.016975
4561 12:40:34.020511 Set Vref, RX VrefLevel [Byte0]: 57
4562 12:40:34.023526 [Byte1]: 47
4563 12:40:34.023612
4564 12:40:34.027061 Final RX Vref Byte 0 = 57 to rank0
4565 12:40:34.030668 Final RX Vref Byte 1 = 47 to rank0
4566 12:40:34.033794 Final RX Vref Byte 0 = 57 to rank1
4567 12:40:34.037053 Final RX Vref Byte 1 = 47 to rank1==
4568 12:40:34.040153 Dram Type= 6, Freq= 0, CH_1, rank 0
4569 12:40:34.043465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 12:40:34.046989 ==
4571 12:40:34.047111 DQS Delay:
4572 12:40:34.047204 DQS0 = 0, DQS1 = 0
4573 12:40:34.050696 DQM Delay:
4574 12:40:34.050806 DQM0 = 39, DQM1 = 29
4575 12:40:34.053539 DQ Delay:
4576 12:40:34.053630 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4577 12:40:34.056804 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4578 12:40:34.060152 DQ8 =16, DQ9 =20, DQ10 =28, DQ11 =20
4579 12:40:34.063529 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4580 12:40:34.066407
4581 12:40:34.066511
4582 12:40:34.073476 [DQSOSCAuto] RK0, (LSB)MR18= 0x2633, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 402 ps
4583 12:40:34.076581 CH1 RK0: MR19=808, MR18=2633
4584 12:40:34.083155 CH1_RK0: MR19=0x808, MR18=0x2633, DQSOSC=400, MR23=63, INC=163, DEC=109
4585 12:40:34.083274
4586 12:40:34.086244 ----->DramcWriteLeveling(PI) begin...
4587 12:40:34.086332 ==
4588 12:40:34.089995 Dram Type= 6, Freq= 0, CH_1, rank 1
4589 12:40:34.092780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4590 12:40:34.092865 ==
4591 12:40:34.096148 Write leveling (Byte 0): 28 => 28
4592 12:40:34.099789 Write leveling (Byte 1): 31 => 31
4593 12:40:34.102782 DramcWriteLeveling(PI) end<-----
4594 12:40:34.102884
4595 12:40:34.102980 ==
4596 12:40:34.105868 Dram Type= 6, Freq= 0, CH_1, rank 1
4597 12:40:34.109572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4598 12:40:34.109657 ==
4599 12:40:34.112478 [Gating] SW mode calibration
4600 12:40:34.119186 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4601 12:40:34.125795 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4602 12:40:34.129290 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4603 12:40:34.135770 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4604 12:40:34.138814 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4605 12:40:34.142520 0 9 12 | B1->B0 | 3232 2d2d | 0 0 | (1 1) (0 0)
4606 12:40:34.149210 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4607 12:40:34.152116 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4608 12:40:34.155550 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 12:40:34.161963 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 12:40:34.165484 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4611 12:40:34.168436 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4612 12:40:34.175298 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4613 12:40:34.178660 0 10 12 | B1->B0 | 2e2e 3a3a | 1 0 | (0 0) (0 0)
4614 12:40:34.181869 0 10 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
4615 12:40:34.188555 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 12:40:34.191556 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 12:40:34.195241 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 12:40:34.201761 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 12:40:34.204796 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4620 12:40:34.208542 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 12:40:34.215094 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4622 12:40:34.217982 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 12:40:34.221682 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 12:40:34.227816 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 12:40:34.231443 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 12:40:34.234843 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 12:40:34.241453 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 12:40:34.244646 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 12:40:34.247783 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 12:40:34.254350 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 12:40:34.258286 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 12:40:34.260814 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 12:40:34.267745 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 12:40:34.270583 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 12:40:34.274020 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 12:40:34.280775 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 12:40:34.284099 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4638 12:40:34.287143 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 12:40:34.290692 Total UI for P1: 0, mck2ui 16
4640 12:40:34.293636 best dqsien dly found for B0: ( 0, 13, 12)
4641 12:40:34.297201 Total UI for P1: 0, mck2ui 16
4642 12:40:34.300216 best dqsien dly found for B1: ( 0, 13, 12)
4643 12:40:34.303948 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4644 12:40:34.306789 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4645 12:40:34.310388
4646 12:40:34.313371 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4647 12:40:34.316887 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4648 12:40:34.319924 [Gating] SW calibration Done
4649 12:40:34.320009 ==
4650 12:40:34.323477 Dram Type= 6, Freq= 0, CH_1, rank 1
4651 12:40:34.326530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4652 12:40:34.326616 ==
4653 12:40:34.326717 RX Vref Scan: 0
4654 12:40:34.330158
4655 12:40:34.330242 RX Vref 0 -> 0, step: 1
4656 12:40:34.330327
4657 12:40:34.333112 RX Delay -230 -> 252, step: 16
4658 12:40:34.336743 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4659 12:40:34.343165 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4660 12:40:34.346296 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4661 12:40:34.350140 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4662 12:40:34.353079 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4663 12:40:34.356124 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4664 12:40:34.362850 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4665 12:40:34.366419 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4666 12:40:34.369508 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4667 12:40:34.372643 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4668 12:40:34.379149 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4669 12:40:34.382707 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4670 12:40:34.385691 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4671 12:40:34.389010 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4672 12:40:34.395967 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4673 12:40:34.399119 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4674 12:40:34.399203 ==
4675 12:40:34.402086 Dram Type= 6, Freq= 0, CH_1, rank 1
4676 12:40:34.405712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4677 12:40:34.405798 ==
4678 12:40:34.408847 DQS Delay:
4679 12:40:34.408928 DQS0 = 0, DQS1 = 0
4680 12:40:34.412353 DQM Delay:
4681 12:40:34.412432 DQM0 = 35, DQM1 = 29
4682 12:40:34.412498 DQ Delay:
4683 12:40:34.415618 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4684 12:40:34.419025 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4685 12:40:34.422138 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4686 12:40:34.425601 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4687 12:40:34.425678
4688 12:40:34.425741
4689 12:40:34.428505 ==
4690 12:40:34.432032 Dram Type= 6, Freq= 0, CH_1, rank 1
4691 12:40:34.435115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4692 12:40:34.435194 ==
4693 12:40:34.435259
4694 12:40:34.435320
4695 12:40:34.438644 TX Vref Scan disable
4696 12:40:34.438747 == TX Byte 0 ==
4697 12:40:34.445099 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4698 12:40:34.448197 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4699 12:40:34.448276 == TX Byte 1 ==
4700 12:40:34.455283 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4701 12:40:34.458327 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4702 12:40:34.458410 ==
4703 12:40:34.462000 Dram Type= 6, Freq= 0, CH_1, rank 1
4704 12:40:34.465053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4705 12:40:34.465136 ==
4706 12:40:34.465202
4707 12:40:34.465260
4708 12:40:34.468165 TX Vref Scan disable
4709 12:40:34.471767 == TX Byte 0 ==
4710 12:40:34.474737 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4711 12:40:34.478249 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4712 12:40:34.481683 == TX Byte 1 ==
4713 12:40:34.484673 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4714 12:40:34.488155 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4715 12:40:34.491634
4716 12:40:34.491719 [DATLAT]
4717 12:40:34.491800 Freq=600, CH1 RK1
4718 12:40:34.491914
4719 12:40:34.494460 DATLAT Default: 0x9
4720 12:40:34.494541 0, 0xFFFF, sum = 0
4721 12:40:34.497922 1, 0xFFFF, sum = 0
4722 12:40:34.498006 2, 0xFFFF, sum = 0
4723 12:40:34.501428 3, 0xFFFF, sum = 0
4724 12:40:34.504574 4, 0xFFFF, sum = 0
4725 12:40:34.504658 5, 0xFFFF, sum = 0
4726 12:40:34.507608 6, 0xFFFF, sum = 0
4727 12:40:34.507691 7, 0xFFFF, sum = 0
4728 12:40:34.511324 8, 0x0, sum = 1
4729 12:40:34.511408 9, 0x0, sum = 2
4730 12:40:34.511474 10, 0x0, sum = 3
4731 12:40:34.514206 11, 0x0, sum = 4
4732 12:40:34.514289 best_step = 9
4733 12:40:34.514355
4734 12:40:34.514416 ==
4735 12:40:34.517788 Dram Type= 6, Freq= 0, CH_1, rank 1
4736 12:40:34.524243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4737 12:40:34.524329 ==
4738 12:40:34.524395 RX Vref Scan: 0
4739 12:40:34.524459
4740 12:40:34.527265 RX Vref 0 -> 0, step: 1
4741 12:40:34.527345
4742 12:40:34.530735 RX Delay -195 -> 252, step: 8
4743 12:40:34.537225 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4744 12:40:34.540793 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4745 12:40:34.543751 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4746 12:40:34.547455 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4747 12:40:34.550452 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4748 12:40:34.557089 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4749 12:40:34.560128 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4750 12:40:34.563988 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4751 12:40:34.567113 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4752 12:40:34.573962 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4753 12:40:34.576843 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4754 12:40:34.580434 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4755 12:40:34.583384 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4756 12:40:34.589814 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4757 12:40:34.593201 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4758 12:40:34.596763 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4759 12:40:34.596849 ==
4760 12:40:34.599625 Dram Type= 6, Freq= 0, CH_1, rank 1
4761 12:40:34.603070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4762 12:40:34.606404 ==
4763 12:40:34.606489 DQS Delay:
4764 12:40:34.606576 DQS0 = 0, DQS1 = 0
4765 12:40:34.609877 DQM Delay:
4766 12:40:34.609961 DQM0 = 36, DQM1 = 29
4767 12:40:34.612902 DQ Delay:
4768 12:40:34.612987 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4769 12:40:34.616597 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4770 12:40:34.619658 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =20
4771 12:40:34.623228 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4772 12:40:34.626119
4773 12:40:34.626204
4774 12:40:34.632646 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c5b, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
4775 12:40:34.636044 CH1 RK1: MR19=808, MR18=3C5B
4776 12:40:34.642772 CH1_RK1: MR19=0x808, MR18=0x3C5B, DQSOSC=392, MR23=63, INC=170, DEC=113
4777 12:40:34.645946 [RxdqsGatingPostProcess] freq 600
4778 12:40:34.649927 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4779 12:40:34.652402 Pre-setting of DQS Precalculation
4780 12:40:34.659589 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4781 12:40:34.665658 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4782 12:40:34.672302 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4783 12:40:34.672385
4784 12:40:34.672450
4785 12:40:34.675880 [Calibration Summary] 1200 Mbps
4786 12:40:34.675962 CH 0, Rank 0
4787 12:40:34.679053 SW Impedance : PASS
4788 12:40:34.682012 DUTY Scan : NO K
4789 12:40:34.682095 ZQ Calibration : PASS
4790 12:40:34.685563 Jitter Meter : NO K
4791 12:40:34.688596 CBT Training : PASS
4792 12:40:34.688677 Write leveling : PASS
4793 12:40:34.692323 RX DQS gating : PASS
4794 12:40:34.695137 RX DQ/DQS(RDDQC) : PASS
4795 12:40:34.695219 TX DQ/DQS : PASS
4796 12:40:34.698756 RX DATLAT : PASS
4797 12:40:34.702125 RX DQ/DQS(Engine): PASS
4798 12:40:34.702234 TX OE : NO K
4799 12:40:34.705593 All Pass.
4800 12:40:34.705670
4801 12:40:34.705732 CH 0, Rank 1
4802 12:40:34.708414 SW Impedance : PASS
4803 12:40:34.708488 DUTY Scan : NO K
4804 12:40:34.711806 ZQ Calibration : PASS
4805 12:40:34.715161 Jitter Meter : NO K
4806 12:40:34.715244 CBT Training : PASS
4807 12:40:34.718305 Write leveling : PASS
4808 12:40:34.722002 RX DQS gating : PASS
4809 12:40:34.722086 RX DQ/DQS(RDDQC) : PASS
4810 12:40:34.725098 TX DQ/DQS : PASS
4811 12:40:34.728630 RX DATLAT : PASS
4812 12:40:34.728705 RX DQ/DQS(Engine): PASS
4813 12:40:34.731542 TX OE : NO K
4814 12:40:34.731630 All Pass.
4815 12:40:34.731692
4816 12:40:34.731781 CH 1, Rank 0
4817 12:40:34.734920 SW Impedance : PASS
4818 12:40:34.738411 DUTY Scan : NO K
4819 12:40:34.738494 ZQ Calibration : PASS
4820 12:40:34.741294 Jitter Meter : NO K
4821 12:40:34.744944 CBT Training : PASS
4822 12:40:34.745025 Write leveling : PASS
4823 12:40:34.748007 RX DQS gating : PASS
4824 12:40:34.751224 RX DQ/DQS(RDDQC) : PASS
4825 12:40:34.751306 TX DQ/DQS : PASS
4826 12:40:34.754584 RX DATLAT : PASS
4827 12:40:34.757625 RX DQ/DQS(Engine): PASS
4828 12:40:34.757709 TX OE : NO K
4829 12:40:34.761080 All Pass.
4830 12:40:34.761163
4831 12:40:34.761247 CH 1, Rank 1
4832 12:40:34.764185 SW Impedance : PASS
4833 12:40:34.764268 DUTY Scan : NO K
4834 12:40:34.767845 ZQ Calibration : PASS
4835 12:40:34.770821 Jitter Meter : NO K
4836 12:40:34.770944 CBT Training : PASS
4837 12:40:34.774542 Write leveling : PASS
4838 12:40:34.777414 RX DQS gating : PASS
4839 12:40:34.777498 RX DQ/DQS(RDDQC) : PASS
4840 12:40:34.781029 TX DQ/DQS : PASS
4841 12:40:34.784015 RX DATLAT : PASS
4842 12:40:34.784098 RX DQ/DQS(Engine): PASS
4843 12:40:34.787217 TX OE : NO K
4844 12:40:34.787298 All Pass.
4845 12:40:34.787363
4846 12:40:34.790769 DramC Write-DBI off
4847 12:40:34.793840 PER_BANK_REFRESH: Hybrid Mode
4848 12:40:34.793922 TX_TRACKING: ON
4849 12:40:34.803819 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4850 12:40:34.807236 [FAST_K] Save calibration result to emmc
4851 12:40:34.810631 dramc_set_vcore_voltage set vcore to 662500
4852 12:40:34.813468 Read voltage for 933, 3
4853 12:40:34.813550 Vio18 = 0
4854 12:40:34.813616 Vcore = 662500
4855 12:40:34.816974 Vdram = 0
4856 12:40:34.817055 Vddq = 0
4857 12:40:34.817120 Vmddr = 0
4858 12:40:34.823375 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4859 12:40:34.827061 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4860 12:40:34.830063 MEM_TYPE=3, freq_sel=17
4861 12:40:34.833701 sv_algorithm_assistance_LP4_1600
4862 12:40:34.836711 ============ PULL DRAM RESETB DOWN ============
4863 12:40:34.843177 ========== PULL DRAM RESETB DOWN end =========
4864 12:40:34.846461 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4865 12:40:34.850021 ===================================
4866 12:40:34.853034 LPDDR4 DRAM CONFIGURATION
4867 12:40:34.856621 ===================================
4868 12:40:34.856704 EX_ROW_EN[0] = 0x0
4869 12:40:34.859570 EX_ROW_EN[1] = 0x0
4870 12:40:34.859653 LP4Y_EN = 0x0
4871 12:40:34.862939 WORK_FSP = 0x0
4872 12:40:34.863026 WL = 0x3
4873 12:40:34.866407 RL = 0x3
4874 12:40:34.866485 BL = 0x2
4875 12:40:34.869576 RPST = 0x0
4876 12:40:34.873179 RD_PRE = 0x0
4877 12:40:34.873257 WR_PRE = 0x1
4878 12:40:34.876212 WR_PST = 0x0
4879 12:40:34.876291 DBI_WR = 0x0
4880 12:40:34.879829 DBI_RD = 0x0
4881 12:40:34.879904 OTF = 0x1
4882 12:40:34.882695 ===================================
4883 12:40:34.886442 ===================================
4884 12:40:34.889542 ANA top config
4885 12:40:34.892560 ===================================
4886 12:40:34.892634 DLL_ASYNC_EN = 0
4887 12:40:34.896131 ALL_SLAVE_EN = 1
4888 12:40:34.899206 NEW_RANK_MODE = 1
4889 12:40:34.902809 DLL_IDLE_MODE = 1
4890 12:40:34.902894 LP45_APHY_COMB_EN = 1
4891 12:40:34.905968 TX_ODT_DIS = 1
4892 12:40:34.909303 NEW_8X_MODE = 1
4893 12:40:34.912586 ===================================
4894 12:40:34.916045 ===================================
4895 12:40:34.919408 data_rate = 1866
4896 12:40:34.922612 CKR = 1
4897 12:40:34.925514 DQ_P2S_RATIO = 8
4898 12:40:34.928873 ===================================
4899 12:40:34.928970 CA_P2S_RATIO = 8
4900 12:40:34.932554 DQ_CA_OPEN = 0
4901 12:40:34.935750 DQ_SEMI_OPEN = 0
4902 12:40:34.938710 CA_SEMI_OPEN = 0
4903 12:40:34.942296 CA_FULL_RATE = 0
4904 12:40:34.945505 DQ_CKDIV4_EN = 1
4905 12:40:34.945583 CA_CKDIV4_EN = 1
4906 12:40:34.949005 CA_PREDIV_EN = 0
4907 12:40:34.951762 PH8_DLY = 0
4908 12:40:34.955433 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4909 12:40:34.958535 DQ_AAMCK_DIV = 4
4910 12:40:34.962145 CA_AAMCK_DIV = 4
4911 12:40:34.962227 CA_ADMCK_DIV = 4
4912 12:40:34.964943 DQ_TRACK_CA_EN = 0
4913 12:40:34.968423 CA_PICK = 933
4914 12:40:34.972076 CA_MCKIO = 933
4915 12:40:34.975126 MCKIO_SEMI = 0
4916 12:40:34.978213 PLL_FREQ = 3732
4917 12:40:34.981783 DQ_UI_PI_RATIO = 32
4918 12:40:34.984882 CA_UI_PI_RATIO = 0
4919 12:40:34.988006 ===================================
4920 12:40:34.991542 ===================================
4921 12:40:34.991625 memory_type:LPDDR4
4922 12:40:34.994583 GP_NUM : 10
4923 12:40:34.997806 SRAM_EN : 1
4924 12:40:34.997888 MD32_EN : 0
4925 12:40:35.001471 ===================================
4926 12:40:35.004490 [ANA_INIT] >>>>>>>>>>>>>>
4927 12:40:35.008042 <<<<<< [CONFIGURE PHASE]: ANA_TX
4928 12:40:35.011038 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4929 12:40:35.014572 ===================================
4930 12:40:35.017430 data_rate = 1866,PCW = 0X8f00
4931 12:40:35.020909 ===================================
4932 12:40:35.024246 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4933 12:40:35.027591 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4934 12:40:35.034240 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4935 12:40:35.037733 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4936 12:40:35.040565 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4937 12:40:35.047278 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4938 12:40:35.047362 [ANA_INIT] flow start
4939 12:40:35.050991 [ANA_INIT] PLL >>>>>>>>
4940 12:40:35.053938 [ANA_INIT] PLL <<<<<<<<
4941 12:40:35.054020 [ANA_INIT] MIDPI >>>>>>>>
4942 12:40:35.057412 [ANA_INIT] MIDPI <<<<<<<<
4943 12:40:35.060820 [ANA_INIT] DLL >>>>>>>>
4944 12:40:35.060917 [ANA_INIT] flow end
4945 12:40:35.064195 ============ LP4 DIFF to SE enter ============
4946 12:40:35.070656 ============ LP4 DIFF to SE exit ============
4947 12:40:35.070796 [ANA_INIT] <<<<<<<<<<<<<
4948 12:40:35.073488 [Flow] Enable top DCM control >>>>>
4949 12:40:35.077136 [Flow] Enable top DCM control <<<<<
4950 12:40:35.080172 Enable DLL master slave shuffle
4951 12:40:35.086935 ==============================================================
4952 12:40:35.087018 Gating Mode config
4953 12:40:35.093597 ==============================================================
4954 12:40:35.097291 Config description:
4955 12:40:35.106997 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4956 12:40:35.113150 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4957 12:40:35.116824 SELPH_MODE 0: By rank 1: By Phase
4958 12:40:35.123579 ==============================================================
4959 12:40:35.126278 GAT_TRACK_EN = 1
4960 12:40:35.129848 RX_GATING_MODE = 2
4961 12:40:35.133200 RX_GATING_TRACK_MODE = 2
4962 12:40:35.133284 SELPH_MODE = 1
4963 12:40:35.136549 PICG_EARLY_EN = 1
4964 12:40:35.140035 VALID_LAT_VALUE = 1
4965 12:40:35.146473 ==============================================================
4966 12:40:35.149436 Enter into Gating configuration >>>>
4967 12:40:35.152994 Exit from Gating configuration <<<<
4968 12:40:35.156066 Enter into DVFS_PRE_config >>>>>
4969 12:40:35.166254 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4970 12:40:35.169465 Exit from DVFS_PRE_config <<<<<
4971 12:40:35.172918 Enter into PICG configuration >>>>
4972 12:40:35.176239 Exit from PICG configuration <<<<
4973 12:40:35.179146 [RX_INPUT] configuration >>>>>
4974 12:40:35.182462 [RX_INPUT] configuration <<<<<
4975 12:40:35.185819 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4976 12:40:35.193332 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4977 12:40:35.199385 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4978 12:40:35.205426 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4979 12:40:35.211937 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4980 12:40:35.218566 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4981 12:40:35.222021 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4982 12:40:35.225778 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4983 12:40:35.228533 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4984 12:40:35.235125 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4985 12:40:35.238504 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4986 12:40:35.241697 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4987 12:40:35.244954 ===================================
4988 12:40:35.248302 LPDDR4 DRAM CONFIGURATION
4989 12:40:35.251605 ===================================
4990 12:40:35.251688 EX_ROW_EN[0] = 0x0
4991 12:40:35.255223 EX_ROW_EN[1] = 0x0
4992 12:40:35.258234 LP4Y_EN = 0x0
4993 12:40:35.258316 WORK_FSP = 0x0
4994 12:40:35.261837 WL = 0x3
4995 12:40:35.261919 RL = 0x3
4996 12:40:35.264910 BL = 0x2
4997 12:40:35.264992 RPST = 0x0
4998 12:40:35.268524 RD_PRE = 0x0
4999 12:40:35.268611 WR_PRE = 0x1
5000 12:40:35.271868 WR_PST = 0x0
5001 12:40:35.271950 DBI_WR = 0x0
5002 12:40:35.274778 DBI_RD = 0x0
5003 12:40:35.274881 OTF = 0x1
5004 12:40:35.278341 ===================================
5005 12:40:35.281687 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5006 12:40:35.288035 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5007 12:40:35.291397 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5008 12:40:35.294611 ===================================
5009 12:40:35.298105 LPDDR4 DRAM CONFIGURATION
5010 12:40:35.301489 ===================================
5011 12:40:35.301577 EX_ROW_EN[0] = 0x10
5012 12:40:35.304482 EX_ROW_EN[1] = 0x0
5013 12:40:35.307968 LP4Y_EN = 0x0
5014 12:40:35.308053 WORK_FSP = 0x0
5015 12:40:35.310985 WL = 0x3
5016 12:40:35.311069 RL = 0x3
5017 12:40:35.314527 BL = 0x2
5018 12:40:35.314611 RPST = 0x0
5019 12:40:35.317505 RD_PRE = 0x0
5020 12:40:35.317588 WR_PRE = 0x1
5021 12:40:35.321039 WR_PST = 0x0
5022 12:40:35.321122 DBI_WR = 0x0
5023 12:40:35.324067 DBI_RD = 0x0
5024 12:40:35.324157 OTF = 0x1
5025 12:40:35.327640 ===================================
5026 12:40:35.334122 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5027 12:40:35.338508 nWR fixed to 30
5028 12:40:35.341839 [ModeRegInit_LP4] CH0 RK0
5029 12:40:35.341960 [ModeRegInit_LP4] CH0 RK1
5030 12:40:35.345265 [ModeRegInit_LP4] CH1 RK0
5031 12:40:35.348630 [ModeRegInit_LP4] CH1 RK1
5032 12:40:35.348736 match AC timing 9
5033 12:40:35.355219 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5034 12:40:35.358675 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5035 12:40:35.361652 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5036 12:40:35.368322 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5037 12:40:35.371874 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5038 12:40:35.371955 ==
5039 12:40:35.374756 Dram Type= 6, Freq= 0, CH_0, rank 0
5040 12:40:35.378191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5041 12:40:35.378270 ==
5042 12:40:35.384742 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5043 12:40:35.391175 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5044 12:40:35.395075 [CA 0] Center 38 (8~69) winsize 62
5045 12:40:35.397816 [CA 1] Center 38 (7~69) winsize 63
5046 12:40:35.401168 [CA 2] Center 35 (5~65) winsize 61
5047 12:40:35.404601 [CA 3] Center 35 (5~65) winsize 61
5048 12:40:35.407799 [CA 4] Center 34 (4~65) winsize 62
5049 12:40:35.411498 [CA 5] Center 33 (3~64) winsize 62
5050 12:40:35.411582
5051 12:40:35.414410 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5052 12:40:35.414493
5053 12:40:35.417979 [CATrainingPosCal] consider 1 rank data
5054 12:40:35.421094 u2DelayCellTimex100 = 270/100 ps
5055 12:40:35.424580 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5056 12:40:35.427699 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5057 12:40:35.431052 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5058 12:40:35.437674 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5059 12:40:35.440651 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5060 12:40:35.444181 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5061 12:40:35.444265
5062 12:40:35.447527 CA PerBit enable=1, Macro0, CA PI delay=33
5063 12:40:35.447612
5064 12:40:35.451056 [CBTSetCACLKResult] CA Dly = 33
5065 12:40:35.451141 CS Dly: 7 (0~38)
5066 12:40:35.451226 ==
5067 12:40:35.453766 Dram Type= 6, Freq= 0, CH_0, rank 1
5068 12:40:35.460448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5069 12:40:35.460541 ==
5070 12:40:35.463847 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5071 12:40:35.470288 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5072 12:40:35.473885 [CA 0] Center 38 (8~69) winsize 62
5073 12:40:35.477445 [CA 1] Center 38 (7~69) winsize 63
5074 12:40:35.480264 [CA 2] Center 35 (5~66) winsize 62
5075 12:40:35.483929 [CA 3] Center 35 (5~66) winsize 62
5076 12:40:35.487450 [CA 4] Center 34 (3~65) winsize 63
5077 12:40:35.490309 [CA 5] Center 34 (4~64) winsize 61
5078 12:40:35.490406
5079 12:40:35.493799 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5080 12:40:35.493887
5081 12:40:35.496757 [CATrainingPosCal] consider 2 rank data
5082 12:40:35.500214 u2DelayCellTimex100 = 270/100 ps
5083 12:40:35.503664 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5084 12:40:35.510041 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5085 12:40:35.513504 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5086 12:40:35.516988 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5087 12:40:35.519965 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5088 12:40:35.523615 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5089 12:40:35.523692
5090 12:40:35.526693 CA PerBit enable=1, Macro0, CA PI delay=34
5091 12:40:35.526770
5092 12:40:35.529707 [CBTSetCACLKResult] CA Dly = 34
5093 12:40:35.533077 CS Dly: 7 (0~38)
5094 12:40:35.533199
5095 12:40:35.536628 ----->DramcWriteLeveling(PI) begin...
5096 12:40:35.536718 ==
5097 12:40:35.539691 Dram Type= 6, Freq= 0, CH_0, rank 0
5098 12:40:35.543269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5099 12:40:35.543383 ==
5100 12:40:35.546627 Write leveling (Byte 0): 31 => 31
5101 12:40:35.549495 Write leveling (Byte 1): 29 => 29
5102 12:40:35.553185 DramcWriteLeveling(PI) end<-----
5103 12:40:35.553282
5104 12:40:35.553348 ==
5105 12:40:35.555961 Dram Type= 6, Freq= 0, CH_0, rank 0
5106 12:40:35.559343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5107 12:40:35.559427 ==
5108 12:40:35.563077 [Gating] SW mode calibration
5109 12:40:35.569896 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5110 12:40:35.576056 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5111 12:40:35.579706 0 14 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5112 12:40:35.582650 0 14 4 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
5113 12:40:35.589693 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5114 12:40:35.593072 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5115 12:40:35.596124 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5116 12:40:35.602445 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5117 12:40:35.606043 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5118 12:40:35.609082 0 14 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
5119 12:40:35.615863 0 15 0 | B1->B0 | 3232 2c2c | 1 0 | (1 0) (0 0)
5120 12:40:35.619248 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5121 12:40:35.622196 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5122 12:40:35.629272 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5123 12:40:35.632173 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5124 12:40:35.635779 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5125 12:40:35.642100 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5126 12:40:35.645608 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5127 12:40:35.648569 1 0 0 | B1->B0 | 2d2d 3939 | 1 0 | (0 0) (0 0)
5128 12:40:35.655644 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5129 12:40:35.658976 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 12:40:35.661941 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 12:40:35.669118 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 12:40:35.671690 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 12:40:35.674997 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5134 12:40:35.682035 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 12:40:35.685013 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5136 12:40:35.688489 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 12:40:35.695207 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 12:40:35.698518 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 12:40:35.701500 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 12:40:35.708548 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 12:40:35.711571 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 12:40:35.715093 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 12:40:35.721314 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 12:40:35.724678 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 12:40:35.728168 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 12:40:35.734705 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 12:40:35.737719 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 12:40:35.741206 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 12:40:35.747700 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 12:40:35.751304 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 12:40:35.754317 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5152 12:40:35.757907 Total UI for P1: 0, mck2ui 16
5153 12:40:35.760905 best dqsien dly found for B0: ( 1, 2, 30)
5154 12:40:35.767762 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5155 12:40:35.771044 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5156 12:40:35.774256 Total UI for P1: 0, mck2ui 16
5157 12:40:35.777492 best dqsien dly found for B1: ( 1, 3, 4)
5158 12:40:35.780869 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5159 12:40:35.784108 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5160 12:40:35.784192
5161 12:40:35.787415 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5162 12:40:35.790724 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5163 12:40:35.794122 [Gating] SW calibration Done
5164 12:40:35.794206 ==
5165 12:40:35.797181 Dram Type= 6, Freq= 0, CH_0, rank 0
5166 12:40:35.803547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5167 12:40:35.803640 ==
5168 12:40:35.803707 RX Vref Scan: 0
5169 12:40:35.803768
5170 12:40:35.807059 RX Vref 0 -> 0, step: 1
5171 12:40:35.807170
5172 12:40:35.810506 RX Delay -80 -> 252, step: 8
5173 12:40:35.813496 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5174 12:40:35.816710 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5175 12:40:35.820279 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5176 12:40:35.823329 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5177 12:40:35.830326 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5178 12:40:35.833460 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5179 12:40:35.836385 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5180 12:40:35.839910 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5181 12:40:35.843367 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5182 12:40:35.849752 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5183 12:40:35.853301 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5184 12:40:35.856165 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5185 12:40:35.859809 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5186 12:40:35.862730 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5187 12:40:35.869827 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5188 12:40:35.872730 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5189 12:40:35.872813 ==
5190 12:40:35.876249 Dram Type= 6, Freq= 0, CH_0, rank 0
5191 12:40:35.879770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5192 12:40:35.879854 ==
5193 12:40:35.882633 DQS Delay:
5194 12:40:35.882716 DQS0 = 0, DQS1 = 0
5195 12:40:35.882782 DQM Delay:
5196 12:40:35.886142 DQM0 = 95, DQM1 = 84
5197 12:40:35.886224 DQ Delay:
5198 12:40:35.889555 DQ0 =95, DQ1 =95, DQ2 =91, DQ3 =91
5199 12:40:35.892818 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =111
5200 12:40:35.896103 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =79
5201 12:40:35.899270 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5202 12:40:35.899353
5203 12:40:35.899419
5204 12:40:35.899479 ==
5205 12:40:35.902553 Dram Type= 6, Freq= 0, CH_0, rank 0
5206 12:40:35.909059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5207 12:40:35.909143 ==
5208 12:40:35.909209
5209 12:40:35.909269
5210 12:40:35.909328 TX Vref Scan disable
5211 12:40:35.912634 == TX Byte 0 ==
5212 12:40:35.916198 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5213 12:40:35.922476 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5214 12:40:35.922562 == TX Byte 1 ==
5215 12:40:35.925865 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5216 12:40:35.932477 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5217 12:40:35.932613 ==
5218 12:40:35.935813 Dram Type= 6, Freq= 0, CH_0, rank 0
5219 12:40:35.939185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5220 12:40:35.939322 ==
5221 12:40:35.939392
5222 12:40:35.939453
5223 12:40:35.942643 TX Vref Scan disable
5224 12:40:35.946079 == TX Byte 0 ==
5225 12:40:35.948958 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5226 12:40:35.952454 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5227 12:40:35.955374 == TX Byte 1 ==
5228 12:40:35.958994 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5229 12:40:35.962667 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5230 12:40:35.962769
5231 12:40:35.962893 [DATLAT]
5232 12:40:35.965600 Freq=933, CH0 RK0
5233 12:40:35.965673
5234 12:40:35.968598 DATLAT Default: 0xd
5235 12:40:35.968669 0, 0xFFFF, sum = 0
5236 12:40:35.972236 1, 0xFFFF, sum = 0
5237 12:40:35.972310 2, 0xFFFF, sum = 0
5238 12:40:35.975638 3, 0xFFFF, sum = 0
5239 12:40:35.975710 4, 0xFFFF, sum = 0
5240 12:40:35.978983 5, 0xFFFF, sum = 0
5241 12:40:35.979085 6, 0xFFFF, sum = 0
5242 12:40:35.982090 7, 0xFFFF, sum = 0
5243 12:40:35.982189 8, 0xFFFF, sum = 0
5244 12:40:35.985662 9, 0xFFFF, sum = 0
5245 12:40:35.985771 10, 0x0, sum = 1
5246 12:40:35.988543 11, 0x0, sum = 2
5247 12:40:35.988647 12, 0x0, sum = 3
5248 12:40:35.991929 13, 0x0, sum = 4
5249 12:40:35.992039 best_step = 11
5250 12:40:35.992130
5251 12:40:35.992223 ==
5252 12:40:35.995364 Dram Type= 6, Freq= 0, CH_0, rank 0
5253 12:40:35.998696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5254 12:40:36.001726 ==
5255 12:40:36.001824 RX Vref Scan: 1
5256 12:40:36.001914
5257 12:40:36.005199 RX Vref 0 -> 0, step: 1
5258 12:40:36.005281
5259 12:40:36.008525 RX Delay -69 -> 252, step: 4
5260 12:40:36.008607
5261 12:40:36.011930 Set Vref, RX VrefLevel [Byte0]: 60
5262 12:40:36.014812 [Byte1]: 46
5263 12:40:36.014936
5264 12:40:36.017878 Final RX Vref Byte 0 = 60 to rank0
5265 12:40:36.021562 Final RX Vref Byte 1 = 46 to rank0
5266 12:40:36.024535 Final RX Vref Byte 0 = 60 to rank1
5267 12:40:36.028081 Final RX Vref Byte 1 = 46 to rank1==
5268 12:40:36.031694 Dram Type= 6, Freq= 0, CH_0, rank 0
5269 12:40:36.034501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5270 12:40:36.034584 ==
5271 12:40:36.037936 DQS Delay:
5272 12:40:36.038018 DQS0 = 0, DQS1 = 0
5273 12:40:36.038083 DQM Delay:
5274 12:40:36.041312 DQM0 = 95, DQM1 = 83
5275 12:40:36.041394 DQ Delay:
5276 12:40:36.044295 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5277 12:40:36.047635 DQ4 =96, DQ5 =86, DQ6 =104, DQ7 =106
5278 12:40:36.051037 DQ8 =74, DQ9 =68, DQ10 =84, DQ11 =76
5279 12:40:36.054073 DQ12 =86, DQ13 =88, DQ14 =96, DQ15 =92
5280 12:40:36.054155
5281 12:40:36.054220
5282 12:40:36.064507 [DQSOSCAuto] RK0, (LSB)MR18= 0x1615, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 414 ps
5283 12:40:36.067496 CH0 RK0: MR19=505, MR18=1615
5284 12:40:36.070957 CH0_RK0: MR19=0x505, MR18=0x1615, DQSOSC=414, MR23=63, INC=63, DEC=42
5285 12:40:36.074019
5286 12:40:36.077576 ----->DramcWriteLeveling(PI) begin...
5287 12:40:36.077666 ==
5288 12:40:36.080408 Dram Type= 6, Freq= 0, CH_0, rank 1
5289 12:40:36.084000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5290 12:40:36.084084 ==
5291 12:40:36.087544 Write leveling (Byte 0): 34 => 34
5292 12:40:36.090497 Write leveling (Byte 1): 29 => 29
5293 12:40:36.093977 DramcWriteLeveling(PI) end<-----
5294 12:40:36.094059
5295 12:40:36.094123 ==
5296 12:40:36.096745 Dram Type= 6, Freq= 0, CH_0, rank 1
5297 12:40:36.100292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5298 12:40:36.100374 ==
5299 12:40:36.103501 [Gating] SW mode calibration
5300 12:40:36.109988 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5301 12:40:36.117021 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5302 12:40:36.120031 0 14 0 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
5303 12:40:36.123311 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5304 12:40:36.129847 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5305 12:40:36.132861 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5306 12:40:36.139823 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5307 12:40:36.142544 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5308 12:40:36.145944 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5309 12:40:36.152845 0 14 28 | B1->B0 | 3434 2929 | 1 1 | (1 1) (1 0)
5310 12:40:36.155836 0 15 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
5311 12:40:36.159339 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5312 12:40:36.165903 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5313 12:40:36.169477 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5314 12:40:36.172523 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5315 12:40:36.175979 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5316 12:40:36.182371 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5317 12:40:36.185909 0 15 28 | B1->B0 | 2828 3737 | 0 1 | (0 0) (0 0)
5318 12:40:36.188968 1 0 0 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
5319 12:40:36.195572 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 12:40:36.199089 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5321 12:40:36.202491 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 12:40:36.209062 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 12:40:36.211958 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5324 12:40:36.215343 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 12:40:36.221972 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5326 12:40:36.225127 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 12:40:36.228797 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5328 12:40:36.235160 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 12:40:36.238752 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 12:40:36.241591 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 12:40:36.248661 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 12:40:36.251451 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 12:40:36.254802 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 12:40:36.261833 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 12:40:36.264631 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 12:40:36.268150 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 12:40:36.274651 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 12:40:36.278215 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 12:40:36.281050 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 12:40:36.288161 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 12:40:36.290924 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5342 12:40:36.294487 Total UI for P1: 0, mck2ui 16
5343 12:40:36.298085 best dqsien dly found for B0: ( 1, 2, 26)
5344 12:40:36.301040 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5345 12:40:36.307638 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 12:40:36.311279 Total UI for P1: 0, mck2ui 16
5347 12:40:36.314171 best dqsien dly found for B1: ( 1, 2, 30)
5348 12:40:36.317837 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5349 12:40:36.320657 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5350 12:40:36.320739
5351 12:40:36.324189 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5352 12:40:36.327303 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5353 12:40:36.330517 [Gating] SW calibration Done
5354 12:40:36.330598 ==
5355 12:40:36.334144 Dram Type= 6, Freq= 0, CH_0, rank 1
5356 12:40:36.337448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5357 12:40:36.337558 ==
5358 12:40:36.340669 RX Vref Scan: 0
5359 12:40:36.340770
5360 12:40:36.343594 RX Vref 0 -> 0, step: 1
5361 12:40:36.343695
5362 12:40:36.343791 RX Delay -80 -> 252, step: 8
5363 12:40:36.350463 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5364 12:40:36.353783 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5365 12:40:36.357183 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5366 12:40:36.360721 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5367 12:40:36.363857 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5368 12:40:36.370307 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5369 12:40:36.373751 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5370 12:40:36.376958 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5371 12:40:36.380064 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5372 12:40:36.383591 iDelay=208, Bit 9, Center 63 (-32 ~ 159) 192
5373 12:40:36.390079 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5374 12:40:36.393668 iDelay=208, Bit 11, Center 71 (-24 ~ 167) 192
5375 12:40:36.396579 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5376 12:40:36.400378 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5377 12:40:36.403139 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5378 12:40:36.410114 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5379 12:40:36.410213 ==
5380 12:40:36.413106 Dram Type= 6, Freq= 0, CH_0, rank 1
5381 12:40:36.416693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5382 12:40:36.416786 ==
5383 12:40:36.416876 DQS Delay:
5384 12:40:36.420135 DQS0 = 0, DQS1 = 0
5385 12:40:36.420212 DQM Delay:
5386 12:40:36.423026 DQM0 = 91, DQM1 = 81
5387 12:40:36.423097 DQ Delay:
5388 12:40:36.426470 DQ0 =91, DQ1 =91, DQ2 =91, DQ3 =87
5389 12:40:36.429484 DQ4 =91, DQ5 =75, DQ6 =99, DQ7 =103
5390 12:40:36.432914 DQ8 =71, DQ9 =63, DQ10 =87, DQ11 =71
5391 12:40:36.436557 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =87
5392 12:40:36.436655
5393 12:40:36.436743
5394 12:40:36.436837 ==
5395 12:40:36.439890 Dram Type= 6, Freq= 0, CH_0, rank 1
5396 12:40:36.443160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5397 12:40:36.443257 ==
5398 12:40:36.446306
5399 12:40:36.446406
5400 12:40:36.446536 TX Vref Scan disable
5401 12:40:36.449539 == TX Byte 0 ==
5402 12:40:36.452907 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5403 12:40:36.456274 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5404 12:40:36.459577 == TX Byte 1 ==
5405 12:40:36.462798 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5406 12:40:36.466283 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5407 12:40:36.466366 ==
5408 12:40:36.469661 Dram Type= 6, Freq= 0, CH_0, rank 1
5409 12:40:36.476231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5410 12:40:36.476315 ==
5411 12:40:36.476380
5412 12:40:36.476441
5413 12:40:36.479201 TX Vref Scan disable
5414 12:40:36.479283 == TX Byte 0 ==
5415 12:40:36.486136 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5416 12:40:36.489317 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5417 12:40:36.489400 == TX Byte 1 ==
5418 12:40:36.495833 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5419 12:40:36.499346 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5420 12:40:36.499428
5421 12:40:36.499491 [DATLAT]
5422 12:40:36.502383 Freq=933, CH0 RK1
5423 12:40:36.502533
5424 12:40:36.502598 DATLAT Default: 0xb
5425 12:40:36.505339 0, 0xFFFF, sum = 0
5426 12:40:36.505423 1, 0xFFFF, sum = 0
5427 12:40:36.508930 2, 0xFFFF, sum = 0
5428 12:40:36.509014 3, 0xFFFF, sum = 0
5429 12:40:36.512475 4, 0xFFFF, sum = 0
5430 12:40:36.512584 5, 0xFFFF, sum = 0
5431 12:40:36.515426 6, 0xFFFF, sum = 0
5432 12:40:36.519028 7, 0xFFFF, sum = 0
5433 12:40:36.519110 8, 0xFFFF, sum = 0
5434 12:40:36.522343 9, 0xFFFF, sum = 0
5435 12:40:36.522427 10, 0x0, sum = 1
5436 12:40:36.525293 11, 0x0, sum = 2
5437 12:40:36.525376 12, 0x0, sum = 3
5438 12:40:36.525443 13, 0x0, sum = 4
5439 12:40:36.528705 best_step = 11
5440 12:40:36.528787
5441 12:40:36.528851 ==
5442 12:40:36.532341 Dram Type= 6, Freq= 0, CH_0, rank 1
5443 12:40:36.535290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5444 12:40:36.535374 ==
5445 12:40:36.538851 RX Vref Scan: 0
5446 12:40:36.538948
5447 12:40:36.541835 RX Vref 0 -> 0, step: 1
5448 12:40:36.541916
5449 12:40:36.541980 RX Delay -77 -> 252, step: 4
5450 12:40:36.549448 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5451 12:40:36.552775 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5452 12:40:36.556058 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5453 12:40:36.559291 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5454 12:40:36.562598 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5455 12:40:36.569651 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5456 12:40:36.572495 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5457 12:40:36.576178 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5458 12:40:36.579247 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5459 12:40:36.582789 iDelay=199, Bit 9, Center 68 (-17 ~ 154) 172
5460 12:40:36.589465 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5461 12:40:36.592645 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5462 12:40:36.595695 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5463 12:40:36.599221 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5464 12:40:36.602080 iDelay=199, Bit 14, Center 96 (11 ~ 182) 172
5465 12:40:36.609172 iDelay=199, Bit 15, Center 92 (3 ~ 182) 180
5466 12:40:36.609254 ==
5467 12:40:36.612129 Dram Type= 6, Freq= 0, CH_0, rank 1
5468 12:40:36.615575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5469 12:40:36.615657 ==
5470 12:40:36.615722 DQS Delay:
5471 12:40:36.619104 DQS0 = 0, DQS1 = 0
5472 12:40:36.619185 DQM Delay:
5473 12:40:36.622094 DQM0 = 92, DQM1 = 84
5474 12:40:36.622175 DQ Delay:
5475 12:40:36.625157 DQ0 =90, DQ1 =94, DQ2 =88, DQ3 =88
5476 12:40:36.628535 DQ4 =90, DQ5 =80, DQ6 =104, DQ7 =104
5477 12:40:36.632229 DQ8 =76, DQ9 =68, DQ10 =86, DQ11 =76
5478 12:40:36.635517 DQ12 =90, DQ13 =90, DQ14 =96, DQ15 =92
5479 12:40:36.635599
5480 12:40:36.635664
5481 12:40:36.644945 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c0e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 408 ps
5482 12:40:36.645028 CH0 RK1: MR19=505, MR18=2C0E
5483 12:40:36.651929 CH0_RK1: MR19=0x505, MR18=0x2C0E, DQSOSC=408, MR23=63, INC=65, DEC=43
5484 12:40:36.655267 [RxdqsGatingPostProcess] freq 933
5485 12:40:36.661492 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5486 12:40:36.665124 best DQS0 dly(2T, 0.5T) = (0, 10)
5487 12:40:36.668000 best DQS1 dly(2T, 0.5T) = (0, 11)
5488 12:40:36.671602 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5489 12:40:36.675058 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5490 12:40:36.678168 best DQS0 dly(2T, 0.5T) = (0, 10)
5491 12:40:36.678250 best DQS1 dly(2T, 0.5T) = (0, 10)
5492 12:40:36.681584 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5493 12:40:36.684541 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5494 12:40:36.688105 Pre-setting of DQS Precalculation
5495 12:40:36.694724 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5496 12:40:36.694806 ==
5497 12:40:36.698256 Dram Type= 6, Freq= 0, CH_1, rank 0
5498 12:40:36.701369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5499 12:40:36.701451 ==
5500 12:40:36.707684 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5501 12:40:36.714136 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5502 12:40:36.717735 [CA 0] Center 37 (7~67) winsize 61
5503 12:40:36.721192 [CA 1] Center 37 (7~68) winsize 62
5504 12:40:36.724265 [CA 2] Center 34 (5~64) winsize 60
5505 12:40:36.727803 [CA 3] Center 34 (4~64) winsize 61
5506 12:40:36.731031 [CA 4] Center 34 (5~64) winsize 60
5507 12:40:36.734470 [CA 5] Center 34 (4~64) winsize 61
5508 12:40:36.734563
5509 12:40:36.737799 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5510 12:40:36.737881
5511 12:40:36.740720 [CATrainingPosCal] consider 1 rank data
5512 12:40:36.744281 u2DelayCellTimex100 = 270/100 ps
5513 12:40:36.747767 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5514 12:40:36.750640 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5515 12:40:36.754262 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5516 12:40:36.757242 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5517 12:40:36.760599 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5518 12:40:36.767161 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5519 12:40:36.767248
5520 12:40:36.770373 CA PerBit enable=1, Macro0, CA PI delay=34
5521 12:40:36.770449
5522 12:40:36.773658 [CBTSetCACLKResult] CA Dly = 34
5523 12:40:36.773741 CS Dly: 6 (0~37)
5524 12:40:36.773806 ==
5525 12:40:36.777196 Dram Type= 6, Freq= 0, CH_1, rank 1
5526 12:40:36.780259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5527 12:40:36.783245 ==
5528 12:40:36.786616 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5529 12:40:36.793647 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5530 12:40:36.796711 [CA 0] Center 38 (8~68) winsize 61
5531 12:40:36.800220 [CA 1] Center 37 (7~68) winsize 62
5532 12:40:36.803634 [CA 2] Center 35 (5~65) winsize 61
5533 12:40:36.806756 [CA 3] Center 34 (4~64) winsize 61
5534 12:40:36.810058 [CA 4] Center 34 (4~65) winsize 62
5535 12:40:36.813696 [CA 5] Center 33 (3~64) winsize 62
5536 12:40:36.813779
5537 12:40:36.816771 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5538 12:40:36.816853
5539 12:40:36.819723 [CATrainingPosCal] consider 2 rank data
5540 12:40:36.823171 u2DelayCellTimex100 = 270/100 ps
5541 12:40:36.826589 CA0 delay=37 (8~67),Diff = 3 PI (18 cell)
5542 12:40:36.829557 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5543 12:40:36.833086 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5544 12:40:36.839790 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5545 12:40:36.843067 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5546 12:40:36.845969 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5547 12:40:36.846051
5548 12:40:36.849569 CA PerBit enable=1, Macro0, CA PI delay=34
5549 12:40:36.849652
5550 12:40:36.852533 [CBTSetCACLKResult] CA Dly = 34
5551 12:40:36.852615 CS Dly: 7 (0~39)
5552 12:40:36.852680
5553 12:40:36.856114 ----->DramcWriteLeveling(PI) begin...
5554 12:40:36.858999 ==
5555 12:40:36.862694 Dram Type= 6, Freq= 0, CH_1, rank 0
5556 12:40:36.865601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5557 12:40:36.865685 ==
5558 12:40:36.868892 Write leveling (Byte 0): 25 => 25
5559 12:40:36.872352 Write leveling (Byte 1): 30 => 30
5560 12:40:36.875734 DramcWriteLeveling(PI) end<-----
5561 12:40:36.875818
5562 12:40:36.875901 ==
5563 12:40:36.879170 Dram Type= 6, Freq= 0, CH_1, rank 0
5564 12:40:36.882175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5565 12:40:36.882259 ==
5566 12:40:36.885642 [Gating] SW mode calibration
5567 12:40:36.892005 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5568 12:40:36.898440 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5569 12:40:36.902053 0 14 0 | B1->B0 | 3131 3333 | 1 0 | (1 1) (0 0)
5570 12:40:36.904951 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5571 12:40:36.911795 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5572 12:40:36.915298 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5573 12:40:36.918147 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5574 12:40:36.925051 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5575 12:40:36.928024 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5576 12:40:36.931484 0 14 28 | B1->B0 | 3232 3131 | 1 0 | (1 0) (0 0)
5577 12:40:36.938058 0 15 0 | B1->B0 | 2626 2424 | 0 0 | (1 1) (0 0)
5578 12:40:36.941379 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5579 12:40:36.944991 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5580 12:40:36.951147 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5581 12:40:36.954707 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5582 12:40:36.957686 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5583 12:40:36.964554 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 12:40:36.967931 0 15 28 | B1->B0 | 2f2f 3131 | 0 1 | (0 0) (0 0)
5585 12:40:36.970795 1 0 0 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
5586 12:40:36.977433 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 12:40:36.980773 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 12:40:36.984109 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 12:40:36.990922 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5590 12:40:36.993904 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 12:40:36.997456 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 12:40:37.004247 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5593 12:40:37.007222 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5594 12:40:37.010746 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 12:40:37.017031 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 12:40:37.020543 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 12:40:37.023540 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 12:40:37.030510 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 12:40:37.033865 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 12:40:37.036795 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 12:40:37.043450 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 12:40:37.046603 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 12:40:37.050285 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 12:40:37.056593 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 12:40:37.060122 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 12:40:37.063060 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 12:40:37.069726 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 12:40:37.073257 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 12:40:37.076236 Total UI for P1: 0, mck2ui 16
5610 12:40:37.079810 best dqsien dly found for B0: ( 1, 2, 26)
5611 12:40:37.083153 Total UI for P1: 0, mck2ui 16
5612 12:40:37.086023 best dqsien dly found for B1: ( 1, 2, 26)
5613 12:40:37.089474 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5614 12:40:37.092722 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5615 12:40:37.092806
5616 12:40:37.095968 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5617 12:40:37.102556 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5618 12:40:37.102639 [Gating] SW calibration Done
5619 12:40:37.102741 ==
5620 12:40:37.105898 Dram Type= 6, Freq= 0, CH_1, rank 0
5621 12:40:37.112724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5622 12:40:37.112809 ==
5623 12:40:37.112893 RX Vref Scan: 0
5624 12:40:37.112972
5625 12:40:37.115681 RX Vref 0 -> 0, step: 1
5626 12:40:37.115764
5627 12:40:37.119264 RX Delay -80 -> 252, step: 8
5628 12:40:37.122653 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5629 12:40:37.125613 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5630 12:40:37.129013 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5631 12:40:37.135776 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5632 12:40:37.138840 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5633 12:40:37.142475 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5634 12:40:37.145552 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5635 12:40:37.148900 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5636 12:40:37.152332 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5637 12:40:37.158693 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5638 12:40:37.162468 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5639 12:40:37.165428 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5640 12:40:37.168507 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5641 12:40:37.172040 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5642 12:40:37.178476 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5643 12:40:37.182106 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5644 12:40:37.182188 ==
5645 12:40:37.185030 Dram Type= 6, Freq= 0, CH_1, rank 0
5646 12:40:37.188236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5647 12:40:37.188347 ==
5648 12:40:37.191709 DQS Delay:
5649 12:40:37.191790 DQS0 = 0, DQS1 = 0
5650 12:40:37.191854 DQM Delay:
5651 12:40:37.195094 DQM0 = 94, DQM1 = 86
5652 12:40:37.195175 DQ Delay:
5653 12:40:37.198304 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5654 12:40:37.201604 DQ4 =91, DQ5 =103, DQ6 =107, DQ7 =91
5655 12:40:37.204878 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =83
5656 12:40:37.208418 DQ12 =95, DQ13 =91, DQ14 =91, DQ15 =91
5657 12:40:37.208499
5658 12:40:37.208563
5659 12:40:37.208622 ==
5660 12:40:37.211812 Dram Type= 6, Freq= 0, CH_1, rank 0
5661 12:40:37.218105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5662 12:40:37.218213 ==
5663 12:40:37.218290
5664 12:40:37.218351
5665 12:40:37.218409 TX Vref Scan disable
5666 12:40:37.221672 == TX Byte 0 ==
5667 12:40:37.225150 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5668 12:40:37.231540 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5669 12:40:37.231621 == TX Byte 1 ==
5670 12:40:37.235161 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5671 12:40:37.241685 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5672 12:40:37.241767 ==
5673 12:40:37.245110 Dram Type= 6, Freq= 0, CH_1, rank 0
5674 12:40:37.248093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5675 12:40:37.248176 ==
5676 12:40:37.248241
5677 12:40:37.248300
5678 12:40:37.251666 TX Vref Scan disable
5679 12:40:37.254485 == TX Byte 0 ==
5680 12:40:37.258187 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5681 12:40:37.261578 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5682 12:40:37.264493 == TX Byte 1 ==
5683 12:40:37.268131 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5684 12:40:37.271183 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5685 12:40:37.271265
5686 12:40:37.271328 [DATLAT]
5687 12:40:37.274710 Freq=933, CH1 RK0
5688 12:40:37.274791
5689 12:40:37.274896 DATLAT Default: 0xd
5690 12:40:37.277764 0, 0xFFFF, sum = 0
5691 12:40:37.281265 1, 0xFFFF, sum = 0
5692 12:40:37.281350 2, 0xFFFF, sum = 0
5693 12:40:37.284854 3, 0xFFFF, sum = 0
5694 12:40:37.284937 4, 0xFFFF, sum = 0
5695 12:40:37.287886 5, 0xFFFF, sum = 0
5696 12:40:37.287968 6, 0xFFFF, sum = 0
5697 12:40:37.290786 7, 0xFFFF, sum = 0
5698 12:40:37.290908 8, 0xFFFF, sum = 0
5699 12:40:37.294264 9, 0xFFFF, sum = 0
5700 12:40:37.294346 10, 0x0, sum = 1
5701 12:40:37.297618 11, 0x0, sum = 2
5702 12:40:37.297701 12, 0x0, sum = 3
5703 12:40:37.301037 13, 0x0, sum = 4
5704 12:40:37.301120 best_step = 11
5705 12:40:37.301184
5706 12:40:37.301242 ==
5707 12:40:37.304145 Dram Type= 6, Freq= 0, CH_1, rank 0
5708 12:40:37.307518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5709 12:40:37.310913 ==
5710 12:40:37.310995 RX Vref Scan: 1
5711 12:40:37.311060
5712 12:40:37.313891 RX Vref 0 -> 0, step: 1
5713 12:40:37.313972
5714 12:40:37.314037 RX Delay -69 -> 252, step: 4
5715 12:40:37.317337
5716 12:40:37.317418 Set Vref, RX VrefLevel [Byte0]: 57
5717 12:40:37.320871 [Byte1]: 47
5718 12:40:37.326046
5719 12:40:37.326130 Final RX Vref Byte 0 = 57 to rank0
5720 12:40:37.329041 Final RX Vref Byte 1 = 47 to rank0
5721 12:40:37.332677 Final RX Vref Byte 0 = 57 to rank1
5722 12:40:37.335519 Final RX Vref Byte 1 = 47 to rank1==
5723 12:40:37.339118 Dram Type= 6, Freq= 0, CH_1, rank 0
5724 12:40:37.345298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 12:40:37.345382 ==
5726 12:40:37.345447 DQS Delay:
5727 12:40:37.348676 DQS0 = 0, DQS1 = 0
5728 12:40:37.348758 DQM Delay:
5729 12:40:37.348823 DQM0 = 97, DQM1 = 88
5730 12:40:37.352382 DQ Delay:
5731 12:40:37.355253 DQ0 =102, DQ1 =92, DQ2 =86, DQ3 =94
5732 12:40:37.358222 DQ4 =94, DQ5 =106, DQ6 =110, DQ7 =94
5733 12:40:37.361612 DQ8 =74, DQ9 =80, DQ10 =86, DQ11 =82
5734 12:40:37.365322 DQ12 =100, DQ13 =94, DQ14 =94, DQ15 =94
5735 12:40:37.365428
5736 12:40:37.365499
5737 12:40:37.371690 [DQSOSCAuto] RK0, (LSB)MR18= 0xff08, (MSB)MR19= 0x405, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5738 12:40:37.375316 CH1 RK0: MR19=405, MR18=FF08
5739 12:40:37.381362 CH1_RK0: MR19=0x405, MR18=0xFF08, DQSOSC=419, MR23=63, INC=61, DEC=41
5740 12:40:37.381445
5741 12:40:37.385053 ----->DramcWriteLeveling(PI) begin...
5742 12:40:37.385135 ==
5743 12:40:37.388071 Dram Type= 6, Freq= 0, CH_1, rank 1
5744 12:40:37.391631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5745 12:40:37.394599 ==
5746 12:40:37.394680 Write leveling (Byte 0): 26 => 26
5747 12:40:37.398072 Write leveling (Byte 1): 29 => 29
5748 12:40:37.401512 DramcWriteLeveling(PI) end<-----
5749 12:40:37.401594
5750 12:40:37.401658 ==
5751 12:40:37.404694 Dram Type= 6, Freq= 0, CH_1, rank 1
5752 12:40:37.410955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5753 12:40:37.411042 ==
5754 12:40:37.414760 [Gating] SW mode calibration
5755 12:40:37.421002 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5756 12:40:37.424446 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5757 12:40:37.431233 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5758 12:40:37.434215 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5759 12:40:37.437754 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5760 12:40:37.444153 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5761 12:40:37.447613 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5762 12:40:37.450731 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5763 12:40:37.457576 0 14 24 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 0)
5764 12:40:37.460479 0 14 28 | B1->B0 | 2727 2323 | 1 0 | (0 0) (1 0)
5765 12:40:37.463918 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5766 12:40:37.470714 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5767 12:40:37.473590 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5768 12:40:37.477288 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5769 12:40:37.483686 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5770 12:40:37.487199 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5771 12:40:37.490106 0 15 24 | B1->B0 | 2424 3434 | 0 1 | (0 0) (0 0)
5772 12:40:37.496708 0 15 28 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
5773 12:40:37.500368 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 12:40:37.503826 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 12:40:37.509982 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5776 12:40:37.513356 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5777 12:40:37.516689 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 12:40:37.523318 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5779 12:40:37.526795 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5780 12:40:37.529715 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 12:40:37.536679 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 12:40:37.539698 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 12:40:37.543304 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 12:40:37.549537 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 12:40:37.553044 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 12:40:37.555822 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 12:40:37.562497 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 12:40:37.565920 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 12:40:37.569196 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 12:40:37.576119 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 12:40:37.579116 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 12:40:37.582178 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 12:40:37.588824 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 12:40:37.592356 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5795 12:40:37.595308 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5796 12:40:37.602599 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5797 12:40:37.602683 Total UI for P1: 0, mck2ui 16
5798 12:40:37.609055 best dqsien dly found for B0: ( 1, 2, 22)
5799 12:40:37.612511 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5800 12:40:37.615791 Total UI for P1: 0, mck2ui 16
5801 12:40:37.618628 best dqsien dly found for B1: ( 1, 2, 26)
5802 12:40:37.621870 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5803 12:40:37.625355 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5804 12:40:37.625438
5805 12:40:37.628842 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5806 12:40:37.631779 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5807 12:40:37.635371 [Gating] SW calibration Done
5808 12:40:37.635453 ==
5809 12:40:37.638814 Dram Type= 6, Freq= 0, CH_1, rank 1
5810 12:40:37.642162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5811 12:40:37.645114 ==
5812 12:40:37.645191 RX Vref Scan: 0
5813 12:40:37.645263
5814 12:40:37.648739 RX Vref 0 -> 0, step: 1
5815 12:40:37.648814
5816 12:40:37.651623 RX Delay -80 -> 252, step: 8
5817 12:40:37.655204 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5818 12:40:37.658633 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5819 12:40:37.661562 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5820 12:40:37.664811 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5821 12:40:37.668238 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5822 12:40:37.674954 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5823 12:40:37.678356 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5824 12:40:37.681896 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5825 12:40:37.684829 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5826 12:40:37.688568 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5827 12:40:37.695137 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5828 12:40:37.697982 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5829 12:40:37.701587 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5830 12:40:37.704576 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5831 12:40:37.708212 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5832 12:40:37.714773 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5833 12:40:37.714877 ==
5834 12:40:37.717645 Dram Type= 6, Freq= 0, CH_1, rank 1
5835 12:40:37.720942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5836 12:40:37.721025 ==
5837 12:40:37.721090 DQS Delay:
5838 12:40:37.724336 DQS0 = 0, DQS1 = 0
5839 12:40:37.724417 DQM Delay:
5840 12:40:37.727604 DQM0 = 93, DQM1 = 88
5841 12:40:37.727685 DQ Delay:
5842 12:40:37.730861 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =91
5843 12:40:37.734106 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5844 12:40:37.737845 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =79
5845 12:40:37.740767 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5846 12:40:37.740868
5847 12:40:37.740960
5848 12:40:37.741049 ==
5849 12:40:37.744262 Dram Type= 6, Freq= 0, CH_1, rank 1
5850 12:40:37.747748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5851 12:40:37.747854 ==
5852 12:40:37.750685
5853 12:40:37.750790
5854 12:40:37.750918 TX Vref Scan disable
5855 12:40:37.754331 == TX Byte 0 ==
5856 12:40:37.757796 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5857 12:40:37.760628 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5858 12:40:37.764076 == TX Byte 1 ==
5859 12:40:37.767559 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5860 12:40:37.770798 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5861 12:40:37.773717 ==
5862 12:40:37.773821 Dram Type= 6, Freq= 0, CH_1, rank 1
5863 12:40:37.781008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5864 12:40:37.781109 ==
5865 12:40:37.781209
5866 12:40:37.781303
5867 12:40:37.783691 TX Vref Scan disable
5868 12:40:37.783791 == TX Byte 0 ==
5869 12:40:37.790656 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5870 12:40:37.793705 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5871 12:40:37.793813 == TX Byte 1 ==
5872 12:40:37.800370 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5873 12:40:37.803895 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5874 12:40:37.803994
5875 12:40:37.804085 [DATLAT]
5876 12:40:37.806947 Freq=933, CH1 RK1
5877 12:40:37.807045
5878 12:40:37.807146 DATLAT Default: 0xb
5879 12:40:37.810581 0, 0xFFFF, sum = 0
5880 12:40:37.810681 1, 0xFFFF, sum = 0
5881 12:40:37.813513 2, 0xFFFF, sum = 0
5882 12:40:37.813613 3, 0xFFFF, sum = 0
5883 12:40:37.817017 4, 0xFFFF, sum = 0
5884 12:40:37.817088 5, 0xFFFF, sum = 0
5885 12:40:37.819960 6, 0xFFFF, sum = 0
5886 12:40:37.823468 7, 0xFFFF, sum = 0
5887 12:40:37.823545 8, 0xFFFF, sum = 0
5888 12:40:37.826957 9, 0xFFFF, sum = 0
5889 12:40:37.827035 10, 0x0, sum = 1
5890 12:40:37.827099 11, 0x0, sum = 2
5891 12:40:37.830157 12, 0x0, sum = 3
5892 12:40:37.830260 13, 0x0, sum = 4
5893 12:40:37.833460 best_step = 11
5894 12:40:37.833560
5895 12:40:37.833661 ==
5896 12:40:37.836721 Dram Type= 6, Freq= 0, CH_1, rank 1
5897 12:40:37.840056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5898 12:40:37.840161 ==
5899 12:40:37.843324 RX Vref Scan: 0
5900 12:40:37.843432
5901 12:40:37.843527 RX Vref 0 -> 0, step: 1
5902 12:40:37.846745
5903 12:40:37.846870 RX Delay -69 -> 252, step: 4
5904 12:40:37.853660 iDelay=203, Bit 0, Center 94 (-5 ~ 194) 200
5905 12:40:37.857180 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5906 12:40:37.860691 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5907 12:40:37.863617 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5908 12:40:37.867055 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5909 12:40:37.873341 iDelay=203, Bit 5, Center 100 (3 ~ 198) 196
5910 12:40:37.876697 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5911 12:40:37.880031 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5912 12:40:37.883486 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5913 12:40:37.886777 iDelay=203, Bit 9, Center 82 (-13 ~ 178) 192
5914 12:40:37.893605 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5915 12:40:37.897025 iDelay=203, Bit 11, Center 82 (-13 ~ 178) 192
5916 12:40:37.900040 iDelay=203, Bit 12, Center 98 (11 ~ 186) 176
5917 12:40:37.903093 iDelay=203, Bit 13, Center 98 (7 ~ 190) 184
5918 12:40:37.906740 iDelay=203, Bit 14, Center 98 (11 ~ 186) 176
5919 12:40:37.913485 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5920 12:40:37.913587 ==
5921 12:40:37.916482 Dram Type= 6, Freq= 0, CH_1, rank 1
5922 12:40:37.919537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5923 12:40:37.919637 ==
5924 12:40:37.919727 DQS Delay:
5925 12:40:37.923306 DQS0 = 0, DQS1 = 0
5926 12:40:37.923378 DQM Delay:
5927 12:40:37.926468 DQM0 = 91, DQM1 = 90
5928 12:40:37.926573 DQ Delay:
5929 12:40:37.929499 DQ0 =94, DQ1 =86, DQ2 =82, DQ3 =88
5930 12:40:37.933084 DQ4 =90, DQ5 =100, DQ6 =104, DQ7 =88
5931 12:40:37.935950 DQ8 =76, DQ9 =82, DQ10 =92, DQ11 =82
5932 12:40:37.939639 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =94
5933 12:40:37.939743
5934 12:40:37.939839
5935 12:40:37.949255 [DQSOSCAuto] RK1, (LSB)MR18= 0xb1f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 418 ps
5936 12:40:37.949371 CH1 RK1: MR19=505, MR18=B1F
5937 12:40:37.955970 CH1_RK1: MR19=0x505, MR18=0xB1F, DQSOSC=412, MR23=63, INC=63, DEC=42
5938 12:40:37.959394 [RxdqsGatingPostProcess] freq 933
5939 12:40:37.965811 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5940 12:40:37.968873 best DQS0 dly(2T, 0.5T) = (0, 10)
5941 12:40:37.972483 best DQS1 dly(2T, 0.5T) = (0, 10)
5942 12:40:37.976157 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5943 12:40:37.979009 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5944 12:40:37.982386 best DQS0 dly(2T, 0.5T) = (0, 10)
5945 12:40:37.982482 best DQS1 dly(2T, 0.5T) = (0, 10)
5946 12:40:37.985619 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5947 12:40:37.989003 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5948 12:40:37.992175 Pre-setting of DQS Precalculation
5949 12:40:37.998775 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5950 12:40:38.005035 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5951 12:40:38.012139 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5952 12:40:38.012242
5953 12:40:38.012339
5954 12:40:38.015051 [Calibration Summary] 1866 Mbps
5955 12:40:38.018610 CH 0, Rank 0
5956 12:40:38.018708 SW Impedance : PASS
5957 12:40:38.021741 DUTY Scan : NO K
5958 12:40:38.025238 ZQ Calibration : PASS
5959 12:40:38.025344 Jitter Meter : NO K
5960 12:40:38.028375 CBT Training : PASS
5961 12:40:38.031777 Write leveling : PASS
5962 12:40:38.031860 RX DQS gating : PASS
5963 12:40:38.034755 RX DQ/DQS(RDDQC) : PASS
5964 12:40:38.034880 TX DQ/DQS : PASS
5965 12:40:38.038392 RX DATLAT : PASS
5966 12:40:38.041431 RX DQ/DQS(Engine): PASS
5967 12:40:38.041514 TX OE : NO K
5968 12:40:38.044914 All Pass.
5969 12:40:38.044997
5970 12:40:38.045061 CH 0, Rank 1
5971 12:40:38.048146 SW Impedance : PASS
5972 12:40:38.048229 DUTY Scan : NO K
5973 12:40:38.051554 ZQ Calibration : PASS
5974 12:40:38.054653 Jitter Meter : NO K
5975 12:40:38.054761 CBT Training : PASS
5976 12:40:38.057795 Write leveling : PASS
5977 12:40:38.061061 RX DQS gating : PASS
5978 12:40:38.061143 RX DQ/DQS(RDDQC) : PASS
5979 12:40:38.064504 TX DQ/DQS : PASS
5980 12:40:38.067931 RX DATLAT : PASS
5981 12:40:38.068013 RX DQ/DQS(Engine): PASS
5982 12:40:38.070799 TX OE : NO K
5983 12:40:38.070909 All Pass.
5984 12:40:38.070975
5985 12:40:38.074547 CH 1, Rank 0
5986 12:40:38.074658 SW Impedance : PASS
5987 12:40:38.077615 DUTY Scan : NO K
5988 12:40:38.081077 ZQ Calibration : PASS
5989 12:40:38.081158 Jitter Meter : NO K
5990 12:40:38.084377 CBT Training : PASS
5991 12:40:38.087993 Write leveling : PASS
5992 12:40:38.088075 RX DQS gating : PASS
5993 12:40:38.090770 RX DQ/DQS(RDDQC) : PASS
5994 12:40:38.094549 TX DQ/DQS : PASS
5995 12:40:38.094632 RX DATLAT : PASS
5996 12:40:38.097821 RX DQ/DQS(Engine): PASS
5997 12:40:38.100566 TX OE : NO K
5998 12:40:38.100648 All Pass.
5999 12:40:38.100714
6000 12:40:38.100773 CH 1, Rank 1
6001 12:40:38.103925 SW Impedance : PASS
6002 12:40:38.107696 DUTY Scan : NO K
6003 12:40:38.107778 ZQ Calibration : PASS
6004 12:40:38.111010 Jitter Meter : NO K
6005 12:40:38.114393 CBT Training : PASS
6006 12:40:38.114475 Write leveling : PASS
6007 12:40:38.117526 RX DQS gating : PASS
6008 12:40:38.117608 RX DQ/DQS(RDDQC) : PASS
6009 12:40:38.120520 TX DQ/DQS : PASS
6010 12:40:38.124192 RX DATLAT : PASS
6011 12:40:38.124274 RX DQ/DQS(Engine): PASS
6012 12:40:38.127100 TX OE : NO K
6013 12:40:38.127183 All Pass.
6014 12:40:38.127248
6015 12:40:38.130593 DramC Write-DBI off
6016 12:40:38.133514 PER_BANK_REFRESH: Hybrid Mode
6017 12:40:38.133596 TX_TRACKING: ON
6018 12:40:38.143776 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6019 12:40:38.146772 [FAST_K] Save calibration result to emmc
6020 12:40:38.150361 dramc_set_vcore_voltage set vcore to 650000
6021 12:40:38.153823 Read voltage for 400, 6
6022 12:40:38.153904 Vio18 = 0
6023 12:40:38.156606 Vcore = 650000
6024 12:40:38.156688 Vdram = 0
6025 12:40:38.156753 Vddq = 0
6026 12:40:38.156813 Vmddr = 0
6027 12:40:38.163797 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6028 12:40:38.170218 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6029 12:40:38.170304 MEM_TYPE=3, freq_sel=20
6030 12:40:38.173665 sv_algorithm_assistance_LP4_800
6031 12:40:38.177086 ============ PULL DRAM RESETB DOWN ============
6032 12:40:38.183641 ========== PULL DRAM RESETB DOWN end =========
6033 12:40:38.186658 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6034 12:40:38.190453 ===================================
6035 12:40:38.193605 LPDDR4 DRAM CONFIGURATION
6036 12:40:38.196801 ===================================
6037 12:40:38.196884 EX_ROW_EN[0] = 0x0
6038 12:40:38.199787 EX_ROW_EN[1] = 0x0
6039 12:40:38.199869 LP4Y_EN = 0x0
6040 12:40:38.203324 WORK_FSP = 0x0
6041 12:40:38.203409 WL = 0x2
6042 12:40:38.206567 RL = 0x2
6043 12:40:38.206649 BL = 0x2
6044 12:40:38.209744 RPST = 0x0
6045 12:40:38.212968 RD_PRE = 0x0
6046 12:40:38.213075 WR_PRE = 0x1
6047 12:40:38.216593 WR_PST = 0x0
6048 12:40:38.216675 DBI_WR = 0x0
6049 12:40:38.219512 DBI_RD = 0x0
6050 12:40:38.219594 OTF = 0x1
6051 12:40:38.223088 ===================================
6052 12:40:38.226536 ===================================
6053 12:40:38.229531 ANA top config
6054 12:40:38.233170 ===================================
6055 12:40:38.233252 DLL_ASYNC_EN = 0
6056 12:40:38.236182 ALL_SLAVE_EN = 1
6057 12:40:38.239742 NEW_RANK_MODE = 1
6058 12:40:38.242692 DLL_IDLE_MODE = 1
6059 12:40:38.242774 LP45_APHY_COMB_EN = 1
6060 12:40:38.246235 TX_ODT_DIS = 1
6061 12:40:38.249813 NEW_8X_MODE = 1
6062 12:40:38.252792 ===================================
6063 12:40:38.256372 ===================================
6064 12:40:38.259325 data_rate = 800
6065 12:40:38.262941 CKR = 1
6066 12:40:38.265851 DQ_P2S_RATIO = 4
6067 12:40:38.269219 ===================================
6068 12:40:38.269301 CA_P2S_RATIO = 4
6069 12:40:38.272497 DQ_CA_OPEN = 0
6070 12:40:38.276198 DQ_SEMI_OPEN = 1
6071 12:40:38.279118 CA_SEMI_OPEN = 1
6072 12:40:38.282413 CA_FULL_RATE = 0
6073 12:40:38.285846 DQ_CKDIV4_EN = 0
6074 12:40:38.285923 CA_CKDIV4_EN = 1
6075 12:40:38.289469 CA_PREDIV_EN = 0
6076 12:40:38.292392 PH8_DLY = 0
6077 12:40:38.295891 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6078 12:40:38.298927 DQ_AAMCK_DIV = 0
6079 12:40:38.302529 CA_AAMCK_DIV = 0
6080 12:40:38.302611 CA_ADMCK_DIV = 4
6081 12:40:38.305351 DQ_TRACK_CA_EN = 0
6082 12:40:38.308796 CA_PICK = 800
6083 12:40:38.312104 CA_MCKIO = 400
6084 12:40:38.315526 MCKIO_SEMI = 400
6085 12:40:38.319253 PLL_FREQ = 3016
6086 12:40:38.322170 DQ_UI_PI_RATIO = 32
6087 12:40:38.325678 CA_UI_PI_RATIO = 32
6088 12:40:38.328792 ===================================
6089 12:40:38.331882 ===================================
6090 12:40:38.331964 memory_type:LPDDR4
6091 12:40:38.335401 GP_NUM : 10
6092 12:40:38.338363 SRAM_EN : 1
6093 12:40:38.338445 MD32_EN : 0
6094 12:40:38.341918 ===================================
6095 12:40:38.345531 [ANA_INIT] >>>>>>>>>>>>>>
6096 12:40:38.348582 <<<<<< [CONFIGURE PHASE]: ANA_TX
6097 12:40:38.351990 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6098 12:40:38.354837 ===================================
6099 12:40:38.358349 data_rate = 800,PCW = 0X7400
6100 12:40:38.361821 ===================================
6101 12:40:38.364764 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6102 12:40:38.368279 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6103 12:40:38.381698 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6104 12:40:38.384911 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6105 12:40:38.387886 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6106 12:40:38.391059 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6107 12:40:38.394750 [ANA_INIT] flow start
6108 12:40:38.394840 [ANA_INIT] PLL >>>>>>>>
6109 12:40:38.398173 [ANA_INIT] PLL <<<<<<<<
6110 12:40:38.401080 [ANA_INIT] MIDPI >>>>>>>>
6111 12:40:38.404688 [ANA_INIT] MIDPI <<<<<<<<
6112 12:40:38.404797 [ANA_INIT] DLL >>>>>>>>
6113 12:40:38.407726 [ANA_INIT] flow end
6114 12:40:38.411185 ============ LP4 DIFF to SE enter ============
6115 12:40:38.414627 ============ LP4 DIFF to SE exit ============
6116 12:40:38.417920 [ANA_INIT] <<<<<<<<<<<<<
6117 12:40:38.421142 [Flow] Enable top DCM control >>>>>
6118 12:40:38.424161 [Flow] Enable top DCM control <<<<<
6119 12:40:38.427540 Enable DLL master slave shuffle
6120 12:40:38.434504 ==============================================================
6121 12:40:38.434587 Gating Mode config
6122 12:40:38.440968 ==============================================================
6123 12:40:38.441052 Config description:
6124 12:40:38.450566 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6125 12:40:38.457188 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6126 12:40:38.464084 SELPH_MODE 0: By rank 1: By Phase
6127 12:40:38.470573 ==============================================================
6128 12:40:38.470655 GAT_TRACK_EN = 0
6129 12:40:38.473585 RX_GATING_MODE = 2
6130 12:40:38.477115 RX_GATING_TRACK_MODE = 2
6131 12:40:38.480501 SELPH_MODE = 1
6132 12:40:38.483416 PICG_EARLY_EN = 1
6133 12:40:38.486680 VALID_LAT_VALUE = 1
6134 12:40:38.493488 ==============================================================
6135 12:40:38.496902 Enter into Gating configuration >>>>
6136 12:40:38.500310 Exit from Gating configuration <<<<
6137 12:40:38.503251 Enter into DVFS_PRE_config >>>>>
6138 12:40:38.513139 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6139 12:40:38.516741 Exit from DVFS_PRE_config <<<<<
6140 12:40:38.519603 Enter into PICG configuration >>>>
6141 12:40:38.522993 Exit from PICG configuration <<<<
6142 12:40:38.526290 [RX_INPUT] configuration >>>>>
6143 12:40:38.529578 [RX_INPUT] configuration <<<<<
6144 12:40:38.532832 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6145 12:40:38.539698 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6146 12:40:38.546120 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6147 12:40:38.552624 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6148 12:40:38.556151 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6149 12:40:38.562754 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6150 12:40:38.565659 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6151 12:40:38.572794 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6152 12:40:38.575724 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6153 12:40:38.579222 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6154 12:40:38.582289 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6155 12:40:38.588948 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6156 12:40:38.592303 ===================================
6157 12:40:38.595619 LPDDR4 DRAM CONFIGURATION
6158 12:40:38.599256 ===================================
6159 12:40:38.599363 EX_ROW_EN[0] = 0x0
6160 12:40:38.602036 EX_ROW_EN[1] = 0x0
6161 12:40:38.602133 LP4Y_EN = 0x0
6162 12:40:38.605501 WORK_FSP = 0x0
6163 12:40:38.605575 WL = 0x2
6164 12:40:38.608858 RL = 0x2
6165 12:40:38.608932 BL = 0x2
6166 12:40:38.611782 RPST = 0x0
6167 12:40:38.611863 RD_PRE = 0x0
6168 12:40:38.615475 WR_PRE = 0x1
6169 12:40:38.618817 WR_PST = 0x0
6170 12:40:38.618905 DBI_WR = 0x0
6171 12:40:38.621953 DBI_RD = 0x0
6172 12:40:38.622034 OTF = 0x1
6173 12:40:38.624865 ===================================
6174 12:40:38.628339 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6175 12:40:38.635021 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6176 12:40:38.638472 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6177 12:40:38.641756 ===================================
6178 12:40:38.645301 LPDDR4 DRAM CONFIGURATION
6179 12:40:38.648429 ===================================
6180 12:40:38.648511 EX_ROW_EN[0] = 0x10
6181 12:40:38.651438 EX_ROW_EN[1] = 0x0
6182 12:40:38.651520 LP4Y_EN = 0x0
6183 12:40:38.655061 WORK_FSP = 0x0
6184 12:40:38.655142 WL = 0x2
6185 12:40:38.658077 RL = 0x2
6186 12:40:38.658158 BL = 0x2
6187 12:40:38.661688 RPST = 0x0
6188 12:40:38.661769 RD_PRE = 0x0
6189 12:40:38.664608 WR_PRE = 0x1
6190 12:40:38.668089 WR_PST = 0x0
6191 12:40:38.668171 DBI_WR = 0x0
6192 12:40:38.671621 DBI_RD = 0x0
6193 12:40:38.671703 OTF = 0x1
6194 12:40:38.674528 ===================================
6195 12:40:38.681036 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6196 12:40:38.684686 nWR fixed to 30
6197 12:40:38.688275 [ModeRegInit_LP4] CH0 RK0
6198 12:40:38.688357 [ModeRegInit_LP4] CH0 RK1
6199 12:40:38.691703 [ModeRegInit_LP4] CH1 RK0
6200 12:40:38.694520 [ModeRegInit_LP4] CH1 RK1
6201 12:40:38.694602 match AC timing 19
6202 12:40:38.701173 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6203 12:40:38.704510 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6204 12:40:38.708096 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6205 12:40:38.714856 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6206 12:40:38.717855 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6207 12:40:38.717938 ==
6208 12:40:38.720981 Dram Type= 6, Freq= 0, CH_0, rank 0
6209 12:40:38.724344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6210 12:40:38.724427 ==
6211 12:40:38.730790 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6212 12:40:38.737685 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6213 12:40:38.740838 [CA 0] Center 36 (8~64) winsize 57
6214 12:40:38.744368 [CA 1] Center 36 (8~64) winsize 57
6215 12:40:38.747876 [CA 2] Center 36 (8~64) winsize 57
6216 12:40:38.751018 [CA 3] Center 36 (8~64) winsize 57
6217 12:40:38.754312 [CA 4] Center 36 (8~64) winsize 57
6218 12:40:38.757362 [CA 5] Center 36 (8~64) winsize 57
6219 12:40:38.757444
6220 12:40:38.760736 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6221 12:40:38.760822
6222 12:40:38.763752 [CATrainingPosCal] consider 1 rank data
6223 12:40:38.767204 u2DelayCellTimex100 = 270/100 ps
6224 12:40:38.770885 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 12:40:38.773805 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 12:40:38.777327 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 12:40:38.780283 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 12:40:38.783849 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 12:40:38.786784 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 12:40:38.786906
6231 12:40:38.793912 CA PerBit enable=1, Macro0, CA PI delay=36
6232 12:40:38.794017
6233 12:40:38.794113 [CBTSetCACLKResult] CA Dly = 36
6234 12:40:38.796891 CS Dly: 1 (0~32)
6235 12:40:38.796994 ==
6236 12:40:38.800331 Dram Type= 6, Freq= 0, CH_0, rank 1
6237 12:40:38.803734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6238 12:40:38.803841 ==
6239 12:40:38.810044 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6240 12:40:38.816853 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6241 12:40:38.820075 [CA 0] Center 36 (8~64) winsize 57
6242 12:40:38.823652 [CA 1] Center 36 (8~64) winsize 57
6243 12:40:38.826581 [CA 2] Center 36 (8~64) winsize 57
6244 12:40:38.830157 [CA 3] Center 36 (8~64) winsize 57
6245 12:40:38.830264 [CA 4] Center 36 (8~64) winsize 57
6246 12:40:38.833127 [CA 5] Center 36 (8~64) winsize 57
6247 12:40:38.833231
6248 12:40:38.840048 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6249 12:40:38.840160
6250 12:40:38.842819 [CATrainingPosCal] consider 2 rank data
6251 12:40:38.846551 u2DelayCellTimex100 = 270/100 ps
6252 12:40:38.849427 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 12:40:38.853460 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 12:40:38.856135 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 12:40:38.859586 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 12:40:38.863121 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 12:40:38.866195 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 12:40:38.866297
6259 12:40:38.869634 CA PerBit enable=1, Macro0, CA PI delay=36
6260 12:40:38.869734
6261 12:40:38.872774 [CBTSetCACLKResult] CA Dly = 36
6262 12:40:38.876327 CS Dly: 1 (0~32)
6263 12:40:38.876427
6264 12:40:38.879122 ----->DramcWriteLeveling(PI) begin...
6265 12:40:38.879199 ==
6266 12:40:38.882703 Dram Type= 6, Freq= 0, CH_0, rank 0
6267 12:40:38.885709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6268 12:40:38.885793 ==
6269 12:40:38.889318 Write leveling (Byte 0): 40 => 8
6270 12:40:38.892481 Write leveling (Byte 1): 40 => 8
6271 12:40:38.895917 DramcWriteLeveling(PI) end<-----
6272 12:40:38.895993
6273 12:40:38.896056 ==
6274 12:40:38.899419 Dram Type= 6, Freq= 0, CH_0, rank 0
6275 12:40:38.902477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6276 12:40:38.902582 ==
6277 12:40:38.905824 [Gating] SW mode calibration
6278 12:40:38.912155 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6279 12:40:38.919078 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6280 12:40:38.921939 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6281 12:40:38.928923 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6282 12:40:38.932288 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6283 12:40:38.935704 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6284 12:40:38.942509 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6285 12:40:38.945073 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6286 12:40:38.948336 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6287 12:40:38.955015 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6288 12:40:38.958489 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6289 12:40:38.961893 Total UI for P1: 0, mck2ui 16
6290 12:40:38.965215 best dqsien dly found for B0: ( 0, 14, 24)
6291 12:40:38.968038 Total UI for P1: 0, mck2ui 16
6292 12:40:38.971689 best dqsien dly found for B1: ( 0, 14, 24)
6293 12:40:38.974678 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6294 12:40:38.978222 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6295 12:40:38.978323
6296 12:40:38.981760 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6297 12:40:38.984607 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6298 12:40:38.988151 [Gating] SW calibration Done
6299 12:40:38.988250 ==
6300 12:40:38.991793 Dram Type= 6, Freq= 0, CH_0, rank 0
6301 12:40:38.997874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6302 12:40:38.997977 ==
6303 12:40:38.998070 RX Vref Scan: 0
6304 12:40:38.998165
6305 12:40:39.001393 RX Vref 0 -> 0, step: 1
6306 12:40:39.001488
6307 12:40:39.004877 RX Delay -410 -> 252, step: 16
6308 12:40:39.007840 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6309 12:40:39.011302 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6310 12:40:39.017827 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6311 12:40:39.021098 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6312 12:40:39.024335 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6313 12:40:39.028073 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6314 12:40:39.034249 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6315 12:40:39.037739 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6316 12:40:39.041081 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6317 12:40:39.044030 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6318 12:40:39.050576 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6319 12:40:39.054047 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6320 12:40:39.057455 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6321 12:40:39.060529 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6322 12:40:39.067280 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6323 12:40:39.070990 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6324 12:40:39.071070 ==
6325 12:40:39.074190 Dram Type= 6, Freq= 0, CH_0, rank 0
6326 12:40:39.077142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6327 12:40:39.077223 ==
6328 12:40:39.080749 DQS Delay:
6329 12:40:39.080829 DQS0 = 59, DQS1 = 59
6330 12:40:39.083771 DQM Delay:
6331 12:40:39.083851 DQM0 = 18, DQM1 = 10
6332 12:40:39.083916 DQ Delay:
6333 12:40:39.087228 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6334 12:40:39.090772 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6335 12:40:39.093821 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6336 12:40:39.097355 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6337 12:40:39.097439
6338 12:40:39.097502
6339 12:40:39.097560 ==
6340 12:40:39.100350 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 12:40:39.106753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 12:40:39.106898 ==
6343 12:40:39.106964
6344 12:40:39.107024
6345 12:40:39.110314 TX Vref Scan disable
6346 12:40:39.110394 == TX Byte 0 ==
6347 12:40:39.113365 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6348 12:40:39.120239 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6349 12:40:39.120326 == TX Byte 1 ==
6350 12:40:39.123440 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6351 12:40:39.130149 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6352 12:40:39.130236 ==
6353 12:40:39.133029 Dram Type= 6, Freq= 0, CH_0, rank 0
6354 12:40:39.136569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6355 12:40:39.136654 ==
6356 12:40:39.136720
6357 12:40:39.136780
6358 12:40:39.140117 TX Vref Scan disable
6359 12:40:39.140201 == TX Byte 0 ==
6360 12:40:39.143087 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6361 12:40:39.150014 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6362 12:40:39.150100 == TX Byte 1 ==
6363 12:40:39.152895 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6364 12:40:39.159876 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6365 12:40:39.159960
6366 12:40:39.160025 [DATLAT]
6367 12:40:39.160085 Freq=400, CH0 RK0
6368 12:40:39.160144
6369 12:40:39.162669 DATLAT Default: 0xf
6370 12:40:39.166009 0, 0xFFFF, sum = 0
6371 12:40:39.166098 1, 0xFFFF, sum = 0
6372 12:40:39.169378 2, 0xFFFF, sum = 0
6373 12:40:39.169463 3, 0xFFFF, sum = 0
6374 12:40:39.172709 4, 0xFFFF, sum = 0
6375 12:40:39.172840 5, 0xFFFF, sum = 0
6376 12:40:39.176227 6, 0xFFFF, sum = 0
6377 12:40:39.176311 7, 0xFFFF, sum = 0
6378 12:40:39.179640 8, 0xFFFF, sum = 0
6379 12:40:39.179725 9, 0xFFFF, sum = 0
6380 12:40:39.182582 10, 0xFFFF, sum = 0
6381 12:40:39.182665 11, 0xFFFF, sum = 0
6382 12:40:39.185630 12, 0xFFFF, sum = 0
6383 12:40:39.185714 13, 0x0, sum = 1
6384 12:40:39.189239 14, 0x0, sum = 2
6385 12:40:39.189324 15, 0x0, sum = 3
6386 12:40:39.192608 16, 0x0, sum = 4
6387 12:40:39.192693 best_step = 14
6388 12:40:39.192759
6389 12:40:39.192820 ==
6390 12:40:39.195557 Dram Type= 6, Freq= 0, CH_0, rank 0
6391 12:40:39.202783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6392 12:40:39.202906 ==
6393 12:40:39.202973 RX Vref Scan: 1
6394 12:40:39.203034
6395 12:40:39.205674 RX Vref 0 -> 0, step: 1
6396 12:40:39.205756
6397 12:40:39.208738 RX Delay -359 -> 252, step: 8
6398 12:40:39.208822
6399 12:40:39.212334 Set Vref, RX VrefLevel [Byte0]: 60
6400 12:40:39.215290 [Byte1]: 46
6401 12:40:39.218707
6402 12:40:39.218788 Final RX Vref Byte 0 = 60 to rank0
6403 12:40:39.222406 Final RX Vref Byte 1 = 46 to rank0
6404 12:40:39.225283 Final RX Vref Byte 0 = 60 to rank1
6405 12:40:39.228591 Final RX Vref Byte 1 = 46 to rank1==
6406 12:40:39.231989 Dram Type= 6, Freq= 0, CH_0, rank 0
6407 12:40:39.238734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6408 12:40:39.238819 ==
6409 12:40:39.238909 DQS Delay:
6410 12:40:39.242234 DQS0 = 60, DQS1 = 68
6411 12:40:39.242366 DQM Delay:
6412 12:40:39.242435 DQM0 = 14, DQM1 = 13
6413 12:40:39.245190 DQ Delay:
6414 12:40:39.248833 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =16
6415 12:40:39.251615 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6416 12:40:39.251698 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6417 12:40:39.255254 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6418 12:40:39.258259
6419 12:40:39.258341
6420 12:40:39.265153 [DQSOSCAuto] RK0, (LSB)MR18= 0x7c7a, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
6421 12:40:39.268609 CH0 RK0: MR19=C0C, MR18=7C7A
6422 12:40:39.274781 CH0_RK0: MR19=0xC0C, MR18=0x7C7A, DQSOSC=394, MR23=63, INC=380, DEC=253
6423 12:40:39.274889 ==
6424 12:40:39.278169 Dram Type= 6, Freq= 0, CH_0, rank 1
6425 12:40:39.281381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6426 12:40:39.281464 ==
6427 12:40:39.284808 [Gating] SW mode calibration
6428 12:40:39.291347 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6429 12:40:39.298484 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6430 12:40:39.301452 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6431 12:40:39.304442 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6432 12:40:39.310967 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6433 12:40:39.314520 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6434 12:40:39.317993 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6435 12:40:39.324657 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6436 12:40:39.327706 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6437 12:40:39.331136 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6438 12:40:39.337249 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6439 12:40:39.340633 Total UI for P1: 0, mck2ui 16
6440 12:40:39.344252 best dqsien dly found for B0: ( 0, 14, 24)
6441 12:40:39.344335 Total UI for P1: 0, mck2ui 16
6442 12:40:39.350646 best dqsien dly found for B1: ( 0, 14, 24)
6443 12:40:39.354132 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6444 12:40:39.357533 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6445 12:40:39.357615
6446 12:40:39.360550 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6447 12:40:39.364055 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6448 12:40:39.367021 [Gating] SW calibration Done
6449 12:40:39.367103 ==
6450 12:40:39.370310 Dram Type= 6, Freq= 0, CH_0, rank 1
6451 12:40:39.373720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6452 12:40:39.373803 ==
6453 12:40:39.377172 RX Vref Scan: 0
6454 12:40:39.377255
6455 12:40:39.380491 RX Vref 0 -> 0, step: 1
6456 12:40:39.380573
6457 12:40:39.380638 RX Delay -410 -> 252, step: 16
6458 12:40:39.387218 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6459 12:40:39.390471 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6460 12:40:39.393555 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6461 12:40:39.400030 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6462 12:40:39.403572 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6463 12:40:39.407467 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6464 12:40:39.410107 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6465 12:40:39.413755 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6466 12:40:39.420186 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6467 12:40:39.423711 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6468 12:40:39.426771 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6469 12:40:39.433246 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6470 12:40:39.436770 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6471 12:40:39.440149 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6472 12:40:39.443339 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6473 12:40:39.449936 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6474 12:40:39.450014 ==
6475 12:40:39.453418 Dram Type= 6, Freq= 0, CH_0, rank 1
6476 12:40:39.456332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6477 12:40:39.456409 ==
6478 12:40:39.456479 DQS Delay:
6479 12:40:39.459888 DQS0 = 59, DQS1 = 59
6480 12:40:39.459960 DQM Delay:
6481 12:40:39.462784 DQM0 = 16, DQM1 = 10
6482 12:40:39.462935 DQ Delay:
6483 12:40:39.466352 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6484 12:40:39.469930 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6485 12:40:39.472953 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6486 12:40:39.476389 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6487 12:40:39.476462
6488 12:40:39.476524
6489 12:40:39.476592 ==
6490 12:40:39.479575 Dram Type= 6, Freq= 0, CH_0, rank 1
6491 12:40:39.483006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 12:40:39.486217 ==
6493 12:40:39.486299
6494 12:40:39.486381
6495 12:40:39.486445 TX Vref Scan disable
6496 12:40:39.489783 == TX Byte 0 ==
6497 12:40:39.492834 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6498 12:40:39.496302 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6499 12:40:39.499277 == TX Byte 1 ==
6500 12:40:39.502689 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6501 12:40:39.505668 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6502 12:40:39.505749 ==
6503 12:40:39.509263 Dram Type= 6, Freq= 0, CH_0, rank 1
6504 12:40:39.515864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6505 12:40:39.515941 ==
6506 12:40:39.516004
6507 12:40:39.516071
6508 12:40:39.516131 TX Vref Scan disable
6509 12:40:39.518895 == TX Byte 0 ==
6510 12:40:39.522469 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6511 12:40:39.525595 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6512 12:40:39.529112 == TX Byte 1 ==
6513 12:40:39.532082 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6514 12:40:39.535632 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6515 12:40:39.535713
6516 12:40:39.539046 [DATLAT]
6517 12:40:39.539129 Freq=400, CH0 RK1
6518 12:40:39.539196
6519 12:40:39.542017 DATLAT Default: 0xe
6520 12:40:39.542096 0, 0xFFFF, sum = 0
6521 12:40:39.545360 1, 0xFFFF, sum = 0
6522 12:40:39.545443 2, 0xFFFF, sum = 0
6523 12:40:39.548710 3, 0xFFFF, sum = 0
6524 12:40:39.548785 4, 0xFFFF, sum = 0
6525 12:40:39.551985 5, 0xFFFF, sum = 0
6526 12:40:39.552066 6, 0xFFFF, sum = 0
6527 12:40:39.555223 7, 0xFFFF, sum = 0
6528 12:40:39.555302 8, 0xFFFF, sum = 0
6529 12:40:39.558549 9, 0xFFFF, sum = 0
6530 12:40:39.561998 10, 0xFFFF, sum = 0
6531 12:40:39.562073 11, 0xFFFF, sum = 0
6532 12:40:39.565012 12, 0xFFFF, sum = 0
6533 12:40:39.565093 13, 0x0, sum = 1
6534 12:40:39.568378 14, 0x0, sum = 2
6535 12:40:39.568453 15, 0x0, sum = 3
6536 12:40:39.571791 16, 0x0, sum = 4
6537 12:40:39.571871 best_step = 14
6538 12:40:39.571934
6539 12:40:39.571993 ==
6540 12:40:39.574674 Dram Type= 6, Freq= 0, CH_0, rank 1
6541 12:40:39.578365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6542 12:40:39.578441 ==
6543 12:40:39.581394 RX Vref Scan: 0
6544 12:40:39.581472
6545 12:40:39.584737 RX Vref 0 -> 0, step: 1
6546 12:40:39.584809
6547 12:40:39.584876 RX Delay -359 -> 252, step: 8
6548 12:40:39.593695 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6549 12:40:39.597082 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6550 12:40:39.600362 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6551 12:40:39.606630 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6552 12:40:39.610056 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6553 12:40:39.613479 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6554 12:40:39.616439 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6555 12:40:39.623084 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6556 12:40:39.626661 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6557 12:40:39.629725 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6558 12:40:39.633036 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6559 12:40:39.639812 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6560 12:40:39.642794 iDelay=217, Bit 12, Center -48 (-295 ~ 200) 496
6561 12:40:39.646428 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6562 12:40:39.649784 iDelay=217, Bit 14, Center -48 (-295 ~ 200) 496
6563 12:40:39.656349 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6564 12:40:39.656435 ==
6565 12:40:39.659799 Dram Type= 6, Freq= 0, CH_0, rank 1
6566 12:40:39.662522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6567 12:40:39.662607 ==
6568 12:40:39.662673 DQS Delay:
6569 12:40:39.666334 DQS0 = 60, DQS1 = 72
6570 12:40:39.666417 DQM Delay:
6571 12:40:39.669170 DQM0 = 11, DQM1 = 16
6572 12:40:39.669253 DQ Delay:
6573 12:40:39.672800 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6574 12:40:39.676260 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6575 12:40:39.679194 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6576 12:40:39.682797 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6577 12:40:39.682904
6578 12:40:39.682971
6579 12:40:39.689363 [DQSOSCAuto] RK1, (LSB)MR18= 0xc87e, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 385 ps
6580 12:40:39.692857 CH0 RK1: MR19=C0C, MR18=C87E
6581 12:40:39.698932 CH0_RK1: MR19=0xC0C, MR18=0xC87E, DQSOSC=385, MR23=63, INC=398, DEC=265
6582 12:40:39.702344 [RxdqsGatingPostProcess] freq 400
6583 12:40:39.709042 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6584 12:40:39.712499 best DQS0 dly(2T, 0.5T) = (0, 10)
6585 12:40:39.716006 best DQS1 dly(2T, 0.5T) = (0, 10)
6586 12:40:39.719021 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6587 12:40:39.722504 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6588 12:40:39.722587 best DQS0 dly(2T, 0.5T) = (0, 10)
6589 12:40:39.725559 best DQS1 dly(2T, 0.5T) = (0, 10)
6590 12:40:39.729008 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6591 12:40:39.732024 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6592 12:40:39.735707 Pre-setting of DQS Precalculation
6593 12:40:39.742258 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6594 12:40:39.742360 ==
6595 12:40:39.745237 Dram Type= 6, Freq= 0, CH_1, rank 0
6596 12:40:39.748737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6597 12:40:39.748820 ==
6598 12:40:39.755327 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6599 12:40:39.761908 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6600 12:40:39.765200 [CA 0] Center 36 (8~64) winsize 57
6601 12:40:39.768756 [CA 1] Center 36 (8~64) winsize 57
6602 12:40:39.768840 [CA 2] Center 36 (8~64) winsize 57
6603 12:40:39.771844 [CA 3] Center 36 (8~64) winsize 57
6604 12:40:39.775254 [CA 4] Center 36 (8~64) winsize 57
6605 12:40:39.778221 [CA 5] Center 36 (8~64) winsize 57
6606 12:40:39.778303
6607 12:40:39.781747 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6608 12:40:39.781845
6609 12:40:39.788577 [CATrainingPosCal] consider 1 rank data
6610 12:40:39.788664 u2DelayCellTimex100 = 270/100 ps
6611 12:40:39.795090 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 12:40:39.797988 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 12:40:39.801326 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 12:40:39.804628 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 12:40:39.808113 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 12:40:39.811268 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 12:40:39.811350
6618 12:40:39.814537 CA PerBit enable=1, Macro0, CA PI delay=36
6619 12:40:39.814613
6620 12:40:39.817952 [CBTSetCACLKResult] CA Dly = 36
6621 12:40:39.821349 CS Dly: 1 (0~32)
6622 12:40:39.821432 ==
6623 12:40:39.824859 Dram Type= 6, Freq= 0, CH_1, rank 1
6624 12:40:39.827968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6625 12:40:39.828051 ==
6626 12:40:39.834435 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6627 12:40:39.840949 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6628 12:40:39.841053 [CA 0] Center 36 (8~64) winsize 57
6629 12:40:39.844482 [CA 1] Center 36 (8~64) winsize 57
6630 12:40:39.847530 [CA 2] Center 36 (8~64) winsize 57
6631 12:40:39.850588 [CA 3] Center 36 (8~64) winsize 57
6632 12:40:39.854153 [CA 4] Center 36 (8~64) winsize 57
6633 12:40:39.857736 [CA 5] Center 36 (8~64) winsize 57
6634 12:40:39.857819
6635 12:40:39.860676 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6636 12:40:39.860760
6637 12:40:39.864083 [CATrainingPosCal] consider 2 rank data
6638 12:40:39.867174 u2DelayCellTimex100 = 270/100 ps
6639 12:40:39.870780 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 12:40:39.877445 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 12:40:39.880271 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 12:40:39.883676 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 12:40:39.887074 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 12:40:39.890590 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 12:40:39.890672
6646 12:40:39.893931 CA PerBit enable=1, Macro0, CA PI delay=36
6647 12:40:39.894013
6648 12:40:39.896932 [CBTSetCACLKResult] CA Dly = 36
6649 12:40:39.900513 CS Dly: 1 (0~32)
6650 12:40:39.900596
6651 12:40:39.904000 ----->DramcWriteLeveling(PI) begin...
6652 12:40:39.904084 ==
6653 12:40:39.906683 Dram Type= 6, Freq= 0, CH_1, rank 0
6654 12:40:39.910028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6655 12:40:39.910126 ==
6656 12:40:39.913335 Write leveling (Byte 0): 40 => 8
6657 12:40:39.916659 Write leveling (Byte 1): 40 => 8
6658 12:40:39.920255 DramcWriteLeveling(PI) end<-----
6659 12:40:39.920338
6660 12:40:39.920403 ==
6661 12:40:39.923318 Dram Type= 6, Freq= 0, CH_1, rank 0
6662 12:40:39.926699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6663 12:40:39.926784 ==
6664 12:40:39.929738 [Gating] SW mode calibration
6665 12:40:39.936351 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6666 12:40:39.942948 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6667 12:40:39.946461 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6668 12:40:39.949518 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6669 12:40:39.956123 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6670 12:40:39.959689 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6671 12:40:39.962772 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6672 12:40:39.969709 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6673 12:40:39.972847 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6674 12:40:39.975826 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6675 12:40:39.982614 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6676 12:40:39.986042 Total UI for P1: 0, mck2ui 16
6677 12:40:39.988972 best dqsien dly found for B0: ( 0, 14, 24)
6678 12:40:39.992431 Total UI for P1: 0, mck2ui 16
6679 12:40:39.995891 best dqsien dly found for B1: ( 0, 14, 24)
6680 12:40:39.999297 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6681 12:40:40.002253 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6682 12:40:40.002337
6683 12:40:40.005771 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6684 12:40:40.009165 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6685 12:40:40.012628 [Gating] SW calibration Done
6686 12:40:40.012712 ==
6687 12:40:40.015444 Dram Type= 6, Freq= 0, CH_1, rank 0
6688 12:40:40.019342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6689 12:40:40.019426 ==
6690 12:40:40.022340 RX Vref Scan: 0
6691 12:40:40.022470
6692 12:40:40.025973 RX Vref 0 -> 0, step: 1
6693 12:40:40.026055
6694 12:40:40.026119 RX Delay -410 -> 252, step: 16
6695 12:40:40.032437 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6696 12:40:40.035460 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6697 12:40:40.039129 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6698 12:40:40.045585 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6699 12:40:40.048555 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6700 12:40:40.052248 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6701 12:40:40.055130 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6702 12:40:40.061849 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6703 12:40:40.065326 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6704 12:40:40.068269 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6705 12:40:40.071967 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6706 12:40:40.078378 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6707 12:40:40.081602 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6708 12:40:40.084820 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6709 12:40:40.088248 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6710 12:40:40.095141 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6711 12:40:40.095255 ==
6712 12:40:40.098590 Dram Type= 6, Freq= 0, CH_1, rank 0
6713 12:40:40.101611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6714 12:40:40.101695 ==
6715 12:40:40.101761 DQS Delay:
6716 12:40:40.104993 DQS0 = 51, DQS1 = 67
6717 12:40:40.105076 DQM Delay:
6718 12:40:40.108536 DQM0 = 12, DQM1 = 17
6719 12:40:40.108619 DQ Delay:
6720 12:40:40.111365 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6721 12:40:40.114872 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6722 12:40:40.117866 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6723 12:40:40.121297 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6724 12:40:40.121380
6725 12:40:40.121445
6726 12:40:40.121504 ==
6727 12:40:40.124840 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 12:40:40.128046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 12:40:40.128173 ==
6730 12:40:40.128237
6731 12:40:40.131446
6732 12:40:40.131528 TX Vref Scan disable
6733 12:40:40.134983 == TX Byte 0 ==
6734 12:40:40.137998 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6735 12:40:40.141095 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6736 12:40:40.144826 == TX Byte 1 ==
6737 12:40:40.147775 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6738 12:40:40.151344 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6739 12:40:40.151428 ==
6740 12:40:40.154198 Dram Type= 6, Freq= 0, CH_1, rank 0
6741 12:40:40.157720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6742 12:40:40.161230 ==
6743 12:40:40.161336
6744 12:40:40.161429
6745 12:40:40.161518 TX Vref Scan disable
6746 12:40:40.164173 == TX Byte 0 ==
6747 12:40:40.167745 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6748 12:40:40.170756 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6749 12:40:40.174297 == TX Byte 1 ==
6750 12:40:40.177284 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6751 12:40:40.180983 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6752 12:40:40.181071
6753 12:40:40.184046 [DATLAT]
6754 12:40:40.184128 Freq=400, CH1 RK0
6755 12:40:40.184195
6756 12:40:40.187358 DATLAT Default: 0xf
6757 12:40:40.187441 0, 0xFFFF, sum = 0
6758 12:40:40.190658 1, 0xFFFF, sum = 0
6759 12:40:40.190742 2, 0xFFFF, sum = 0
6760 12:40:40.193788 3, 0xFFFF, sum = 0
6761 12:40:40.193872 4, 0xFFFF, sum = 0
6762 12:40:40.197048 5, 0xFFFF, sum = 0
6763 12:40:40.197132 6, 0xFFFF, sum = 0
6764 12:40:40.201187 7, 0xFFFF, sum = 0
6765 12:40:40.201271 8, 0xFFFF, sum = 0
6766 12:40:40.204154 9, 0xFFFF, sum = 0
6767 12:40:40.204238 10, 0xFFFF, sum = 0
6768 12:40:40.207138 11, 0xFFFF, sum = 0
6769 12:40:40.210541 12, 0xFFFF, sum = 0
6770 12:40:40.210624 13, 0x0, sum = 1
6771 12:40:40.210690 14, 0x0, sum = 2
6772 12:40:40.213500 15, 0x0, sum = 3
6773 12:40:40.213584 16, 0x0, sum = 4
6774 12:40:40.217059 best_step = 14
6775 12:40:40.217166
6776 12:40:40.217266 ==
6777 12:40:40.220636 Dram Type= 6, Freq= 0, CH_1, rank 0
6778 12:40:40.224008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6779 12:40:40.224091 ==
6780 12:40:40.226648 RX Vref Scan: 1
6781 12:40:40.226725
6782 12:40:40.226788 RX Vref 0 -> 0, step: 1
6783 12:40:40.230534
6784 12:40:40.230622 RX Delay -375 -> 252, step: 8
6785 12:40:40.230689
6786 12:40:40.233311 Set Vref, RX VrefLevel [Byte0]: 57
6787 12:40:40.236668 [Byte1]: 47
6788 12:40:40.241963
6789 12:40:40.242045 Final RX Vref Byte 0 = 57 to rank0
6790 12:40:40.245365 Final RX Vref Byte 1 = 47 to rank0
6791 12:40:40.248943 Final RX Vref Byte 0 = 57 to rank1
6792 12:40:40.251760 Final RX Vref Byte 1 = 47 to rank1==
6793 12:40:40.255318 Dram Type= 6, Freq= 0, CH_1, rank 0
6794 12:40:40.262093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6795 12:40:40.262176 ==
6796 12:40:40.262242 DQS Delay:
6797 12:40:40.264897 DQS0 = 52, DQS1 = 68
6798 12:40:40.264978 DQM Delay:
6799 12:40:40.265043 DQM0 = 9, DQM1 = 14
6800 12:40:40.268470 DQ Delay:
6801 12:40:40.271482 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6802 12:40:40.274763 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =4
6803 12:40:40.274905 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6804 12:40:40.278560 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6805 12:40:40.281500
6806 12:40:40.281604
6807 12:40:40.288056 [DQSOSCAuto] RK0, (LSB)MR18= 0x5568, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
6808 12:40:40.291787 CH1 RK0: MR19=C0C, MR18=5568
6809 12:40:40.298255 CH1_RK0: MR19=0xC0C, MR18=0x5568, DQSOSC=396, MR23=63, INC=376, DEC=251
6810 12:40:40.298333 ==
6811 12:40:40.301655 Dram Type= 6, Freq= 0, CH_1, rank 1
6812 12:40:40.304405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6813 12:40:40.304481 ==
6814 12:40:40.307692 [Gating] SW mode calibration
6815 12:40:40.314796 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6816 12:40:40.321169 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6817 12:40:40.324173 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6818 12:40:40.327814 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6819 12:40:40.334354 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6820 12:40:40.337685 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6821 12:40:40.340960 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6822 12:40:40.347781 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6823 12:40:40.350939 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6824 12:40:40.354254 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6825 12:40:40.360816 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6826 12:40:40.360928 Total UI for P1: 0, mck2ui 16
6827 12:40:40.367532 best dqsien dly found for B0: ( 0, 14, 24)
6828 12:40:40.367644 Total UI for P1: 0, mck2ui 16
6829 12:40:40.374173 best dqsien dly found for B1: ( 0, 14, 24)
6830 12:40:40.377043 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6831 12:40:40.380513 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6832 12:40:40.380622
6833 12:40:40.383519 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6834 12:40:40.387137 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6835 12:40:40.390042 [Gating] SW calibration Done
6836 12:40:40.390150 ==
6837 12:40:40.393756 Dram Type= 6, Freq= 0, CH_1, rank 1
6838 12:40:40.396699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6839 12:40:40.396807 ==
6840 12:40:40.400143 RX Vref Scan: 0
6841 12:40:40.400253
6842 12:40:40.403546 RX Vref 0 -> 0, step: 1
6843 12:40:40.403656
6844 12:40:40.403751 RX Delay -410 -> 252, step: 16
6845 12:40:40.410266 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6846 12:40:40.413559 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6847 12:40:40.416613 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6848 12:40:40.423216 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6849 12:40:40.426699 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6850 12:40:40.429689 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6851 12:40:40.433382 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6852 12:40:40.439828 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6853 12:40:40.443295 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6854 12:40:40.446559 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6855 12:40:40.449892 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6856 12:40:40.455944 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6857 12:40:40.459629 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6858 12:40:40.463266 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6859 12:40:40.465823 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6860 12:40:40.472491 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6861 12:40:40.472575 ==
6862 12:40:40.475992 Dram Type= 6, Freq= 0, CH_1, rank 1
6863 12:40:40.479049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6864 12:40:40.479132 ==
6865 12:40:40.479197 DQS Delay:
6866 12:40:40.482470 DQS0 = 59, DQS1 = 59
6867 12:40:40.482600 DQM Delay:
6868 12:40:40.485527 DQM0 = 19, DQM1 = 12
6869 12:40:40.485627 DQ Delay:
6870 12:40:40.489192 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6871 12:40:40.492125 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6872 12:40:40.495778 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6873 12:40:40.498720 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6874 12:40:40.498823
6875 12:40:40.498959
6876 12:40:40.499050 ==
6877 12:40:40.502397 Dram Type= 6, Freq= 0, CH_1, rank 1
6878 12:40:40.505398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 12:40:40.508742 ==
6880 12:40:40.508816
6881 12:40:40.508912
6882 12:40:40.508999 TX Vref Scan disable
6883 12:40:40.511955 == TX Byte 0 ==
6884 12:40:40.515328 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6885 12:40:40.518610 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6886 12:40:40.521878 == TX Byte 1 ==
6887 12:40:40.525363 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6888 12:40:40.528776 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6889 12:40:40.528880 ==
6890 12:40:40.532193 Dram Type= 6, Freq= 0, CH_1, rank 1
6891 12:40:40.538673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6892 12:40:40.538775 ==
6893 12:40:40.538913
6894 12:40:40.539001
6895 12:40:40.539096 TX Vref Scan disable
6896 12:40:40.541627 == TX Byte 0 ==
6897 12:40:40.545549 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6898 12:40:40.548511 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6899 12:40:40.551767 == TX Byte 1 ==
6900 12:40:40.555084 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6901 12:40:40.558443 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6902 12:40:40.558529
6903 12:40:40.561267 [DATLAT]
6904 12:40:40.561365 Freq=400, CH1 RK1
6905 12:40:40.561433
6906 12:40:40.564526 DATLAT Default: 0xe
6907 12:40:40.564646 0, 0xFFFF, sum = 0
6908 12:40:40.567925 1, 0xFFFF, sum = 0
6909 12:40:40.567998 2, 0xFFFF, sum = 0
6910 12:40:40.571183 3, 0xFFFF, sum = 0
6911 12:40:40.571256 4, 0xFFFF, sum = 0
6912 12:40:40.574693 5, 0xFFFF, sum = 0
6913 12:40:40.574794 6, 0xFFFF, sum = 0
6914 12:40:40.578295 7, 0xFFFF, sum = 0
6915 12:40:40.578368 8, 0xFFFF, sum = 0
6916 12:40:40.581450 9, 0xFFFF, sum = 0
6917 12:40:40.585323 10, 0xFFFF, sum = 0
6918 12:40:40.585406 11, 0xFFFF, sum = 0
6919 12:40:40.587853 12, 0xFFFF, sum = 0
6920 12:40:40.587935 13, 0x0, sum = 1
6921 12:40:40.590792 14, 0x0, sum = 2
6922 12:40:40.590923 15, 0x0, sum = 3
6923 12:40:40.594517 16, 0x0, sum = 4
6924 12:40:40.594600 best_step = 14
6925 12:40:40.594665
6926 12:40:40.594726 ==
6927 12:40:40.597541 Dram Type= 6, Freq= 0, CH_1, rank 1
6928 12:40:40.601131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6929 12:40:40.601214 ==
6930 12:40:40.604205 RX Vref Scan: 0
6931 12:40:40.604286
6932 12:40:40.607838 RX Vref 0 -> 0, step: 1
6933 12:40:40.607919
6934 12:40:40.607984 RX Delay -359 -> 252, step: 8
6935 12:40:40.616706 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6936 12:40:40.619575 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6937 12:40:40.623069 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6938 12:40:40.629735 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6939 12:40:40.633068 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6940 12:40:40.635886 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6941 12:40:40.639317 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6942 12:40:40.645909 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6943 12:40:40.649467 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6944 12:40:40.652509 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6945 12:40:40.655947 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6946 12:40:40.662573 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6947 12:40:40.666290 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6948 12:40:40.669119 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6949 12:40:40.675855 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6950 12:40:40.679060 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6951 12:40:40.679142 ==
6952 12:40:40.682008 Dram Type= 6, Freq= 0, CH_1, rank 1
6953 12:40:40.685608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6954 12:40:40.685690 ==
6955 12:40:40.688554 DQS Delay:
6956 12:40:40.688635 DQS0 = 60, DQS1 = 64
6957 12:40:40.688700 DQM Delay:
6958 12:40:40.692054 DQM0 = 12, DQM1 = 11
6959 12:40:40.692136 DQ Delay:
6960 12:40:40.695059 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6961 12:40:40.698727 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6962 12:40:40.701849 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6963 12:40:40.705272 DQ12 =16, DQ13 =20, DQ14 =16, DQ15 =16
6964 12:40:40.705354
6965 12:40:40.705418
6966 12:40:40.715018 [DQSOSCAuto] RK1, (LSB)MR18= 0x77a8, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
6967 12:40:40.715101 CH1 RK1: MR19=C0C, MR18=77A8
6968 12:40:40.721924 CH1_RK1: MR19=0xC0C, MR18=0x77A8, DQSOSC=388, MR23=63, INC=392, DEC=261
6969 12:40:40.725185 [RxdqsGatingPostProcess] freq 400
6970 12:40:40.731213 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6971 12:40:40.734633 best DQS0 dly(2T, 0.5T) = (0, 10)
6972 12:40:40.737969 best DQS1 dly(2T, 0.5T) = (0, 10)
6973 12:40:40.741493 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6974 12:40:40.744931 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6975 12:40:40.747790 best DQS0 dly(2T, 0.5T) = (0, 10)
6976 12:40:40.751468 best DQS1 dly(2T, 0.5T) = (0, 10)
6977 12:40:40.754484 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6978 12:40:40.758033 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6979 12:40:40.758114 Pre-setting of DQS Precalculation
6980 12:40:40.764242 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6981 12:40:40.770853 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6982 12:40:40.777986 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6983 12:40:40.778069
6984 12:40:40.778134
6985 12:40:40.781280 [Calibration Summary] 800 Mbps
6986 12:40:40.784203 CH 0, Rank 0
6987 12:40:40.784285 SW Impedance : PASS
6988 12:40:40.787511 DUTY Scan : NO K
6989 12:40:40.791041 ZQ Calibration : PASS
6990 12:40:40.791123 Jitter Meter : NO K
6991 12:40:40.794284 CBT Training : PASS
6992 12:40:40.797248 Write leveling : PASS
6993 12:40:40.797330 RX DQS gating : PASS
6994 12:40:40.800943 RX DQ/DQS(RDDQC) : PASS
6995 12:40:40.804327 TX DQ/DQS : PASS
6996 12:40:40.804409 RX DATLAT : PASS
6997 12:40:40.807323 RX DQ/DQS(Engine): PASS
6998 12:40:40.807405 TX OE : NO K
6999 12:40:40.810922 All Pass.
7000 12:40:40.811003
7001 12:40:40.811067 CH 0, Rank 1
7002 12:40:40.813854 SW Impedance : PASS
7003 12:40:40.813935 DUTY Scan : NO K
7004 12:40:40.817288 ZQ Calibration : PASS
7005 12:40:40.820911 Jitter Meter : NO K
7006 12:40:40.820992 CBT Training : PASS
7007 12:40:40.823856 Write leveling : NO K
7008 12:40:40.827403 RX DQS gating : PASS
7009 12:40:40.827484 RX DQ/DQS(RDDQC) : PASS
7010 12:40:40.830658 TX DQ/DQS : PASS
7011 12:40:40.834057 RX DATLAT : PASS
7012 12:40:40.834156 RX DQ/DQS(Engine): PASS
7013 12:40:40.836783 TX OE : NO K
7014 12:40:40.836866 All Pass.
7015 12:40:40.836931
7016 12:40:40.840178 CH 1, Rank 0
7017 12:40:40.840264 SW Impedance : PASS
7018 12:40:40.843353 DUTY Scan : NO K
7019 12:40:40.846773 ZQ Calibration : PASS
7020 12:40:40.846940 Jitter Meter : NO K
7021 12:40:40.850195 CBT Training : PASS
7022 12:40:40.853697 Write leveling : PASS
7023 12:40:40.853787 RX DQS gating : PASS
7024 12:40:40.856687 RX DQ/DQS(RDDQC) : PASS
7025 12:40:40.859723 TX DQ/DQS : PASS
7026 12:40:40.859824 RX DATLAT : PASS
7027 12:40:40.863378 RX DQ/DQS(Engine): PASS
7028 12:40:40.866365 TX OE : NO K
7029 12:40:40.866482 All Pass.
7030 12:40:40.866576
7031 12:40:40.866664 CH 1, Rank 1
7032 12:40:40.869944 SW Impedance : PASS
7033 12:40:40.873370 DUTY Scan : NO K
7034 12:40:40.873452 ZQ Calibration : PASS
7035 12:40:40.876319 Jitter Meter : NO K
7036 12:40:40.879681 CBT Training : PASS
7037 12:40:40.879763 Write leveling : NO K
7038 12:40:40.883073 RX DQS gating : PASS
7039 12:40:40.886420 RX DQ/DQS(RDDQC) : PASS
7040 12:40:40.886501 TX DQ/DQS : PASS
7041 12:40:40.889676 RX DATLAT : PASS
7042 12:40:40.892471 RX DQ/DQS(Engine): PASS
7043 12:40:40.892560 TX OE : NO K
7044 12:40:40.895859 All Pass.
7045 12:40:40.895940
7046 12:40:40.896005 DramC Write-DBI off
7047 12:40:40.899171 PER_BANK_REFRESH: Hybrid Mode
7048 12:40:40.899252 TX_TRACKING: ON
7049 12:40:40.909100 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7050 12:40:40.912488 [FAST_K] Save calibration result to emmc
7051 12:40:40.915536 dramc_set_vcore_voltage set vcore to 725000
7052 12:40:40.919100 Read voltage for 1600, 0
7053 12:40:40.919182 Vio18 = 0
7054 12:40:40.921997 Vcore = 725000
7055 12:40:40.922077 Vdram = 0
7056 12:40:40.922142 Vddq = 0
7057 12:40:40.925627 Vmddr = 0
7058 12:40:40.928856 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7059 12:40:40.935495 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7060 12:40:40.935577 MEM_TYPE=3, freq_sel=13
7061 12:40:40.939056 sv_algorithm_assistance_LP4_3733
7062 12:40:40.945395 ============ PULL DRAM RESETB DOWN ============
7063 12:40:40.948597 ========== PULL DRAM RESETB DOWN end =========
7064 12:40:40.952184 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7065 12:40:40.955577 ===================================
7066 12:40:40.958800 LPDDR4 DRAM CONFIGURATION
7067 12:40:40.962015 ===================================
7068 12:40:40.965096 EX_ROW_EN[0] = 0x0
7069 12:40:40.965178 EX_ROW_EN[1] = 0x0
7070 12:40:40.968775 LP4Y_EN = 0x0
7071 12:40:40.968856 WORK_FSP = 0x1
7072 12:40:40.971778 WL = 0x5
7073 12:40:40.971859 RL = 0x5
7074 12:40:40.975448 BL = 0x2
7075 12:40:40.975529 RPST = 0x0
7076 12:40:40.978302 RD_PRE = 0x0
7077 12:40:40.978383 WR_PRE = 0x1
7078 12:40:40.981980 WR_PST = 0x1
7079 12:40:40.982060 DBI_WR = 0x0
7080 12:40:40.984828 DBI_RD = 0x0
7081 12:40:40.984910 OTF = 0x1
7082 12:40:40.988286 ===================================
7083 12:40:40.991889 ===================================
7084 12:40:40.995468 ANA top config
7085 12:40:40.998136 ===================================
7086 12:40:41.001831 DLL_ASYNC_EN = 0
7087 12:40:41.001912 ALL_SLAVE_EN = 0
7088 12:40:41.005114 NEW_RANK_MODE = 1
7089 12:40:41.008423 DLL_IDLE_MODE = 1
7090 12:40:41.011382 LP45_APHY_COMB_EN = 1
7091 12:40:41.011463 TX_ODT_DIS = 0
7092 12:40:41.015016 NEW_8X_MODE = 1
7093 12:40:41.018121 ===================================
7094 12:40:41.021679 ===================================
7095 12:40:41.024731 data_rate = 3200
7096 12:40:41.027703 CKR = 1
7097 12:40:41.031326 DQ_P2S_RATIO = 8
7098 12:40:41.034440 ===================================
7099 12:40:41.037594 CA_P2S_RATIO = 8
7100 12:40:41.041217 DQ_CA_OPEN = 0
7101 12:40:41.041300 DQ_SEMI_OPEN = 0
7102 12:40:41.044715 CA_SEMI_OPEN = 0
7103 12:40:41.047585 CA_FULL_RATE = 0
7104 12:40:41.050876 DQ_CKDIV4_EN = 0
7105 12:40:41.054463 CA_CKDIV4_EN = 0
7106 12:40:41.057735 CA_PREDIV_EN = 0
7107 12:40:41.057817 PH8_DLY = 12
7108 12:40:41.060699 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7109 12:40:41.064153 DQ_AAMCK_DIV = 4
7110 12:40:41.067642 CA_AAMCK_DIV = 4
7111 12:40:41.070672 CA_ADMCK_DIV = 4
7112 12:40:41.074330 DQ_TRACK_CA_EN = 0
7113 12:40:41.077324 CA_PICK = 1600
7114 12:40:41.077406 CA_MCKIO = 1600
7115 12:40:41.080891 MCKIO_SEMI = 0
7116 12:40:41.084018 PLL_FREQ = 3068
7117 12:40:41.087353 DQ_UI_PI_RATIO = 32
7118 12:40:41.090347 CA_UI_PI_RATIO = 0
7119 12:40:41.093873 ===================================
7120 12:40:41.097140 ===================================
7121 12:40:41.100466 memory_type:LPDDR4
7122 12:40:41.100548 GP_NUM : 10
7123 12:40:41.103868 SRAM_EN : 1
7124 12:40:41.103952 MD32_EN : 0
7125 12:40:41.106810 ===================================
7126 12:40:41.110218 [ANA_INIT] >>>>>>>>>>>>>>
7127 12:40:41.113661 <<<<<< [CONFIGURE PHASE]: ANA_TX
7128 12:40:41.116604 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7129 12:40:41.120097 ===================================
7130 12:40:41.123165 data_rate = 3200,PCW = 0X7600
7131 12:40:41.126769 ===================================
7132 12:40:41.129820 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7133 12:40:41.136661 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7134 12:40:41.139682 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7135 12:40:41.146789 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7136 12:40:41.149729 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7137 12:40:41.153119 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7138 12:40:41.153223 [ANA_INIT] flow start
7139 12:40:41.156647 [ANA_INIT] PLL >>>>>>>>
7140 12:40:41.159731 [ANA_INIT] PLL <<<<<<<<
7141 12:40:41.159837 [ANA_INIT] MIDPI >>>>>>>>
7142 12:40:41.163142 [ANA_INIT] MIDPI <<<<<<<<
7143 12:40:41.166647 [ANA_INIT] DLL >>>>>>>>
7144 12:40:41.170256 [ANA_INIT] DLL <<<<<<<<
7145 12:40:41.170363 [ANA_INIT] flow end
7146 12:40:41.172959 ============ LP4 DIFF to SE enter ============
7147 12:40:41.179625 ============ LP4 DIFF to SE exit ============
7148 12:40:41.179732 [ANA_INIT] <<<<<<<<<<<<<
7149 12:40:41.182640 [Flow] Enable top DCM control >>>>>
7150 12:40:41.186152 [Flow] Enable top DCM control <<<<<
7151 12:40:41.189158 Enable DLL master slave shuffle
7152 12:40:41.196176 ==============================================================
7153 12:40:41.196284 Gating Mode config
7154 12:40:41.202731 ==============================================================
7155 12:40:41.206285 Config description:
7156 12:40:41.216059 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7157 12:40:41.222747 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7158 12:40:41.225746 SELPH_MODE 0: By rank 1: By Phase
7159 12:40:41.232267 ==============================================================
7160 12:40:41.235431 GAT_TRACK_EN = 1
7161 12:40:41.239021 RX_GATING_MODE = 2
7162 12:40:41.239125 RX_GATING_TRACK_MODE = 2
7163 12:40:41.241993 SELPH_MODE = 1
7164 12:40:41.245702 PICG_EARLY_EN = 1
7165 12:40:41.248724 VALID_LAT_VALUE = 1
7166 12:40:41.255681 ==============================================================
7167 12:40:41.258456 Enter into Gating configuration >>>>
7168 12:40:41.262113 Exit from Gating configuration <<<<
7169 12:40:41.265599 Enter into DVFS_PRE_config >>>>>
7170 12:40:41.275013 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7171 12:40:41.278791 Exit from DVFS_PRE_config <<<<<
7172 12:40:41.282158 Enter into PICG configuration >>>>
7173 12:40:41.284891 Exit from PICG configuration <<<<
7174 12:40:41.288464 [RX_INPUT] configuration >>>>>
7175 12:40:41.292010 [RX_INPUT] configuration <<<<<
7176 12:40:41.294996 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7177 12:40:41.301629 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7178 12:40:41.308255 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7179 12:40:41.314524 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7180 12:40:41.321441 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7181 12:40:41.328137 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7182 12:40:41.331018 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7183 12:40:41.334578 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7184 12:40:41.337694 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7185 12:40:41.344304 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7186 12:40:41.347349 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7187 12:40:41.351062 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7188 12:40:41.354486 ===================================
7189 12:40:41.357751 LPDDR4 DRAM CONFIGURATION
7190 12:40:41.360749 ===================================
7191 12:40:41.360853 EX_ROW_EN[0] = 0x0
7192 12:40:41.364249 EX_ROW_EN[1] = 0x0
7193 12:40:41.367319 LP4Y_EN = 0x0
7194 12:40:41.367421 WORK_FSP = 0x1
7195 12:40:41.370424 WL = 0x5
7196 12:40:41.370526 RL = 0x5
7197 12:40:41.373857 BL = 0x2
7198 12:40:41.373960 RPST = 0x0
7199 12:40:41.377591 RD_PRE = 0x0
7200 12:40:41.377697 WR_PRE = 0x1
7201 12:40:41.380565 WR_PST = 0x1
7202 12:40:41.380668 DBI_WR = 0x0
7203 12:40:41.384082 DBI_RD = 0x0
7204 12:40:41.384187 OTF = 0x1
7205 12:40:41.387292 ===================================
7206 12:40:41.390288 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7207 12:40:41.397126 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7208 12:40:41.399973 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7209 12:40:41.403642 ===================================
7210 12:40:41.406619 LPDDR4 DRAM CONFIGURATION
7211 12:40:41.410221 ===================================
7212 12:40:41.410331 EX_ROW_EN[0] = 0x10
7213 12:40:41.413742 EX_ROW_EN[1] = 0x0
7214 12:40:41.416694 LP4Y_EN = 0x0
7215 12:40:41.416798 WORK_FSP = 0x1
7216 12:40:41.420007 WL = 0x5
7217 12:40:41.420120 RL = 0x5
7218 12:40:41.423612 BL = 0x2
7219 12:40:41.423714 RPST = 0x0
7220 12:40:41.426282 RD_PRE = 0x0
7221 12:40:41.426383 WR_PRE = 0x1
7222 12:40:41.430149 WR_PST = 0x1
7223 12:40:41.430262 DBI_WR = 0x0
7224 12:40:41.433049 DBI_RD = 0x0
7225 12:40:41.433156 OTF = 0x1
7226 12:40:41.436637 ===================================
7227 12:40:41.442972 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7228 12:40:41.443088 ==
7229 12:40:41.446225 Dram Type= 6, Freq= 0, CH_0, rank 0
7230 12:40:41.452842 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7231 12:40:41.452946 ==
7232 12:40:41.453042 [Duty_Offset_Calibration]
7233 12:40:41.456391 B0:2 B1:0 CA:3
7234 12:40:41.456491
7235 12:40:41.459345 [DutyScan_Calibration_Flow] k_type=0
7236 12:40:41.468884
7237 12:40:41.468988 ==CLK 0==
7238 12:40:41.471921 Final CLK duty delay cell = 0
7239 12:40:41.475579 [0] MAX Duty = 5031%(X100), DQS PI = 12
7240 12:40:41.478802 [0] MIN Duty = 4907%(X100), DQS PI = 6
7241 12:40:41.478918 [0] AVG Duty = 4969%(X100)
7242 12:40:41.481742
7243 12:40:41.485501 CH0 CLK Duty spec in!! Max-Min= 124%
7244 12:40:41.488369 [DutyScan_Calibration_Flow] ====Done====
7245 12:40:41.488472
7246 12:40:41.491735 [DutyScan_Calibration_Flow] k_type=1
7247 12:40:41.508882
7248 12:40:41.508989 ==DQS 0 ==
7249 12:40:41.511909 Final DQS duty delay cell = 0
7250 12:40:41.515524 [0] MAX Duty = 5125%(X100), DQS PI = 30
7251 12:40:41.518676 [0] MIN Duty = 4875%(X100), DQS PI = 48
7252 12:40:41.521691 [0] AVG Duty = 5000%(X100)
7253 12:40:41.521798
7254 12:40:41.521889 ==DQS 1 ==
7255 12:40:41.525333 Final DQS duty delay cell = 0
7256 12:40:41.528639 [0] MAX Duty = 5156%(X100), DQS PI = 32
7257 12:40:41.532093 [0] MIN Duty = 5031%(X100), DQS PI = 14
7258 12:40:41.535220 [0] AVG Duty = 5093%(X100)
7259 12:40:41.535321
7260 12:40:41.538508 CH0 DQS 0 Duty spec in!! Max-Min= 250%
7261 12:40:41.538619
7262 12:40:41.541483 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7263 12:40:41.545010 [DutyScan_Calibration_Flow] ====Done====
7264 12:40:41.545119
7265 12:40:41.547952 [DutyScan_Calibration_Flow] k_type=3
7266 12:40:41.565929
7267 12:40:41.566036 ==DQM 0 ==
7268 12:40:41.569480 Final DQM duty delay cell = 0
7269 12:40:41.572361 [0] MAX Duty = 5156%(X100), DQS PI = 30
7270 12:40:41.575965 [0] MIN Duty = 4875%(X100), DQS PI = 0
7271 12:40:41.578974 [0] AVG Duty = 5015%(X100)
7272 12:40:41.579072
7273 12:40:41.579167 ==DQM 1 ==
7274 12:40:41.582132 Final DQM duty delay cell = 0
7275 12:40:41.585530 [0] MAX Duty = 4938%(X100), DQS PI = 60
7276 12:40:41.589214 [0] MIN Duty = 4813%(X100), DQS PI = 12
7277 12:40:41.592277 [0] AVG Duty = 4875%(X100)
7278 12:40:41.592382
7279 12:40:41.595288 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7280 12:40:41.595390
7281 12:40:41.598632 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7282 12:40:41.602290 [DutyScan_Calibration_Flow] ====Done====
7283 12:40:41.602392
7284 12:40:41.605268 [DutyScan_Calibration_Flow] k_type=2
7285 12:40:41.622251
7286 12:40:41.622368 ==DQ 0 ==
7287 12:40:41.625258 Final DQ duty delay cell = -4
7288 12:40:41.628805 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7289 12:40:41.631741 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7290 12:40:41.635275 [-4] AVG Duty = 4938%(X100)
7291 12:40:41.635386
7292 12:40:41.635483 ==DQ 1 ==
7293 12:40:41.638675 Final DQ duty delay cell = 0
7294 12:40:41.642178 [0] MAX Duty = 5156%(X100), DQS PI = 60
7295 12:40:41.645109 [0] MIN Duty = 5000%(X100), DQS PI = 16
7296 12:40:41.648391 [0] AVG Duty = 5078%(X100)
7297 12:40:41.648496
7298 12:40:41.651870 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7299 12:40:41.651972
7300 12:40:41.655522 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7301 12:40:41.658628 [DutyScan_Calibration_Flow] ====Done====
7302 12:40:41.658732 ==
7303 12:40:41.661515 Dram Type= 6, Freq= 0, CH_1, rank 0
7304 12:40:41.665168 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7305 12:40:41.665272 ==
7306 12:40:41.668125 [Duty_Offset_Calibration]
7307 12:40:41.668226 B0:1 B1:-2 CA:0
7308 12:40:41.668323
7309 12:40:41.671741 [DutyScan_Calibration_Flow] k_type=0
7310 12:40:41.682910
7311 12:40:41.683000 ==CLK 0==
7312 12:40:41.685937 Final CLK duty delay cell = 0
7313 12:40:41.689660 [0] MAX Duty = 5031%(X100), DQS PI = 50
7314 12:40:41.692644 [0] MIN Duty = 4907%(X100), DQS PI = 10
7315 12:40:41.695632 [0] AVG Duty = 4969%(X100)
7316 12:40:41.695735
7317 12:40:41.699190 CH1 CLK Duty spec in!! Max-Min= 124%
7318 12:40:41.702266 [DutyScan_Calibration_Flow] ====Done====
7319 12:40:41.702367
7320 12:40:41.705541 [DutyScan_Calibration_Flow] k_type=1
7321 12:40:41.721781
7322 12:40:41.721893 ==DQS 0 ==
7323 12:40:41.725274 Final DQS duty delay cell = -4
7324 12:40:41.728188 [-4] MAX Duty = 4938%(X100), DQS PI = 56
7325 12:40:41.731599 [-4] MIN Duty = 4844%(X100), DQS PI = 14
7326 12:40:41.735198 [-4] AVG Duty = 4891%(X100)
7327 12:40:41.735301
7328 12:40:41.735393 ==DQS 1 ==
7329 12:40:41.738128 Final DQS duty delay cell = 0
7330 12:40:41.741620 [0] MAX Duty = 5125%(X100), DQS PI = 30
7331 12:40:41.744938 [0] MIN Duty = 4844%(X100), DQS PI = 56
7332 12:40:41.747902 [0] AVG Duty = 4984%(X100)
7333 12:40:41.748013
7334 12:40:41.751379 CH1 DQS 0 Duty spec in!! Max-Min= 94%
7335 12:40:41.751483
7336 12:40:41.754733 CH1 DQS 1 Duty spec in!! Max-Min= 281%
7337 12:40:41.757763 [DutyScan_Calibration_Flow] ====Done====
7338 12:40:41.757863
7339 12:40:41.761348 [DutyScan_Calibration_Flow] k_type=3
7340 12:40:41.778763
7341 12:40:41.778919 ==DQM 0 ==
7342 12:40:41.782172 Final DQM duty delay cell = 0
7343 12:40:41.785326 [0] MAX Duty = 5000%(X100), DQS PI = 58
7344 12:40:41.788860 [0] MIN Duty = 4813%(X100), DQS PI = 28
7345 12:40:41.792343 [0] AVG Duty = 4906%(X100)
7346 12:40:41.792451
7347 12:40:41.792544 ==DQM 1 ==
7348 12:40:41.795306 Final DQM duty delay cell = 0
7349 12:40:41.798990 [0] MAX Duty = 5062%(X100), DQS PI = 4
7350 12:40:41.801958 [0] MIN Duty = 4844%(X100), DQS PI = 56
7351 12:40:41.805560 [0] AVG Duty = 4953%(X100)
7352 12:40:41.805668
7353 12:40:41.808449 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7354 12:40:41.808553
7355 12:40:41.812177 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7356 12:40:41.815186 [DutyScan_Calibration_Flow] ====Done====
7357 12:40:41.815296
7358 12:40:41.818266 [DutyScan_Calibration_Flow] k_type=2
7359 12:40:41.835888
7360 12:40:41.835996 ==DQ 0 ==
7361 12:40:41.838930 Final DQ duty delay cell = 0
7362 12:40:41.842515 [0] MAX Duty = 5062%(X100), DQS PI = 0
7363 12:40:41.846002 [0] MIN Duty = 4938%(X100), DQS PI = 24
7364 12:40:41.846110 [0] AVG Duty = 5000%(X100)
7365 12:40:41.846211
7366 12:40:41.849254 ==DQ 1 ==
7367 12:40:41.852235 Final DQ duty delay cell = 0
7368 12:40:41.855591 [0] MAX Duty = 5156%(X100), DQS PI = 24
7369 12:40:41.858779 [0] MIN Duty = 4938%(X100), DQS PI = 56
7370 12:40:41.858924 [0] AVG Duty = 5047%(X100)
7371 12:40:41.859018
7372 12:40:41.865710 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7373 12:40:41.865816
7374 12:40:41.868790 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7375 12:40:41.871781 [DutyScan_Calibration_Flow] ====Done====
7376 12:40:41.875496 nWR fixed to 30
7377 12:40:41.875601 [ModeRegInit_LP4] CH0 RK0
7378 12:40:41.878501 [ModeRegInit_LP4] CH0 RK1
7379 12:40:41.882082 [ModeRegInit_LP4] CH1 RK0
7380 12:40:41.885527 [ModeRegInit_LP4] CH1 RK1
7381 12:40:41.885627 match AC timing 5
7382 12:40:41.891526 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7383 12:40:41.895263 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7384 12:40:41.898105 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7385 12:40:41.904800 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7386 12:40:41.908388 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7387 12:40:41.908496 [MiockJmeterHQA]
7388 12:40:41.908591
7389 12:40:41.911490 [DramcMiockJmeter] u1RxGatingPI = 0
7390 12:40:41.914820 0 : 4363, 4138
7391 12:40:41.914964 4 : 4253, 4026
7392 12:40:41.918231 8 : 4252, 4027
7393 12:40:41.918336 12 : 4252, 4027
7394 12:40:41.921323 16 : 4254, 4029
7395 12:40:41.921431 20 : 4363, 4138
7396 12:40:41.921531 24 : 4253, 4026
7397 12:40:41.924920 28 : 4252, 4027
7398 12:40:41.925024 32 : 4252, 4027
7399 12:40:41.927870 36 : 4255, 4029
7400 12:40:41.927977 40 : 4252, 4027
7401 12:40:41.931442 44 : 4365, 4140
7402 12:40:41.931545 48 : 4363, 4137
7403 12:40:41.934494 52 : 4252, 4027
7404 12:40:41.934598 56 : 4253, 4026
7405 12:40:41.934697 60 : 4253, 4027
7406 12:40:41.938153 64 : 4252, 4030
7407 12:40:41.938257 68 : 4255, 4029
7408 12:40:41.941594 72 : 4361, 4137
7409 12:40:41.941701 76 : 4250, 4026
7410 12:40:41.944423 80 : 4250, 4027
7411 12:40:41.944533 84 : 4249, 4027
7412 12:40:41.948079 88 : 4253, 4029
7413 12:40:41.948188 92 : 4250, 4027
7414 12:40:41.948286 96 : 4360, 4137
7415 12:40:41.950981 100 : 4361, 4137
7416 12:40:41.951084 104 : 4250, 3662
7417 12:40:41.954459 108 : 4249, 2
7418 12:40:41.954560 112 : 4250, 0
7419 12:40:41.958049 116 : 4252, 0
7420 12:40:41.958152 120 : 4250, 0
7421 12:40:41.958254 124 : 4250, 0
7422 12:40:41.960946 128 : 4252, 0
7423 12:40:41.961054 132 : 4360, 0
7424 12:40:41.961151 136 : 4360, 0
7425 12:40:41.964443 140 : 4363, 0
7426 12:40:41.964547 144 : 4250, 0
7427 12:40:41.967721 148 : 4249, 0
7428 12:40:41.967822 152 : 4250, 0
7429 12:40:41.967918 156 : 4250, 0
7430 12:40:41.971077 160 : 4252, 0
7431 12:40:41.971181 164 : 4250, 0
7432 12:40:41.974214 168 : 4252, 0
7433 12:40:41.974325 172 : 4250, 0
7434 12:40:41.974421 176 : 4250, 0
7435 12:40:41.977806 180 : 4253, 0
7436 12:40:41.977890 184 : 4252, 0
7437 12:40:41.980865 188 : 4249, 0
7438 12:40:41.980966 192 : 4363, 0
7439 12:40:41.981047 196 : 4250, 0
7440 12:40:41.983844 200 : 4361, 0
7441 12:40:41.983928 204 : 4363, 0
7442 12:40:41.987532 208 : 4252, 0
7443 12:40:41.987616 212 : 4249, 0
7444 12:40:41.987684 216 : 4250, 0
7445 12:40:41.991037 220 : 4250, 0
7446 12:40:41.991149 224 : 4249, 0
7447 12:40:41.993911 228 : 4250, 0
7448 12:40:41.993995 232 : 4253, 1
7449 12:40:41.994062 236 : 4360, 1237
7450 12:40:41.997544 240 : 4250, 4027
7451 12:40:41.997628 244 : 4365, 4142
7452 12:40:42.000407 248 : 4360, 4138
7453 12:40:42.000491 252 : 4250, 4027
7454 12:40:42.004040 256 : 4250, 4026
7455 12:40:42.004125 260 : 4363, 4140
7456 12:40:42.007222 264 : 4250, 4027
7457 12:40:42.007333 268 : 4250, 4027
7458 12:40:42.010249 272 : 4250, 4026
7459 12:40:42.010333 276 : 4253, 4029
7460 12:40:42.013476 280 : 4250, 4027
7461 12:40:42.013560 284 : 4249, 4027
7462 12:40:42.017064 288 : 4360, 4137
7463 12:40:42.017149 292 : 4250, 4026
7464 12:40:42.017215 296 : 4250, 4027
7465 12:40:42.020214 300 : 4360, 4138
7466 12:40:42.020310 304 : 4249, 4027
7467 12:40:42.023476 308 : 4250, 4026
7468 12:40:42.023560 312 : 4363, 4140
7469 12:40:42.026748 316 : 4250, 4027
7470 12:40:42.026861 320 : 4249, 4027
7471 12:40:42.030222 324 : 4250, 4026
7472 12:40:42.030300 328 : 4253, 4029
7473 12:40:42.033480 332 : 4250, 4027
7474 12:40:42.033566 336 : 4249, 4027
7475 12:40:42.036870 340 : 4360, 4137
7476 12:40:42.036979 344 : 4250, 4027
7477 12:40:42.040006 348 : 4250, 4027
7478 12:40:42.040108 352 : 4360, 4136
7479 12:40:42.043465 356 : 4249, 2977
7480 12:40:42.043570 360 : 4250, 1
7481 12:40:42.043664
7482 12:40:42.046971 MIOCK jitter meter ch=0
7483 12:40:42.047049
7484 12:40:42.049767 1T = (360-108) = 252 dly cells
7485 12:40:42.053498 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7486 12:40:42.053605 ==
7487 12:40:42.056532 Dram Type= 6, Freq= 0, CH_0, rank 0
7488 12:40:42.063261 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7489 12:40:42.063371 ==
7490 12:40:42.066664 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7491 12:40:42.073211 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7492 12:40:42.076475 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7493 12:40:42.082877 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7494 12:40:42.090570 [CA 0] Center 44 (14~75) winsize 62
7495 12:40:42.093951 [CA 1] Center 43 (13~74) winsize 62
7496 12:40:42.097078 [CA 2] Center 40 (11~69) winsize 59
7497 12:40:42.100721 [CA 3] Center 39 (10~68) winsize 59
7498 12:40:42.103719 [CA 4] Center 37 (8~67) winsize 60
7499 12:40:42.107272 [CA 5] Center 37 (7~67) winsize 61
7500 12:40:42.107380
7501 12:40:42.110346 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7502 12:40:42.113417
7503 12:40:42.116947 [CATrainingPosCal] consider 1 rank data
7504 12:40:42.117030 u2DelayCellTimex100 = 258/100 ps
7505 12:40:42.123654 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7506 12:40:42.126763 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7507 12:40:42.130161 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7508 12:40:42.133366 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7509 12:40:42.136592 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7510 12:40:42.139737 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7511 12:40:42.139812
7512 12:40:42.143123 CA PerBit enable=1, Macro0, CA PI delay=37
7513 12:40:42.146526
7514 12:40:42.146627 [CBTSetCACLKResult] CA Dly = 37
7515 12:40:42.149531 CS Dly: 11 (0~42)
7516 12:40:42.153140 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7517 12:40:42.156649 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7518 12:40:42.159709 ==
7519 12:40:42.162674 Dram Type= 6, Freq= 0, CH_0, rank 1
7520 12:40:42.166077 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7521 12:40:42.166160 ==
7522 12:40:42.169766 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7523 12:40:42.176307 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7524 12:40:42.179306 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7525 12:40:42.186300 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7526 12:40:42.194807 [CA 0] Center 44 (13~75) winsize 63
7527 12:40:42.197784 [CA 1] Center 43 (13~74) winsize 62
7528 12:40:42.201308 [CA 2] Center 39 (10~69) winsize 60
7529 12:40:42.204359 [CA 3] Center 39 (10~68) winsize 59
7530 12:40:42.208022 [CA 4] Center 37 (8~67) winsize 60
7531 12:40:42.210985 [CA 5] Center 37 (8~66) winsize 59
7532 12:40:42.211067
7533 12:40:42.214049 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7534 12:40:42.217664
7535 12:40:42.220701 [CATrainingPosCal] consider 2 rank data
7536 12:40:42.220783 u2DelayCellTimex100 = 258/100 ps
7537 12:40:42.227336 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7538 12:40:42.231075 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7539 12:40:42.234104 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7540 12:40:42.237611 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7541 12:40:42.240503 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7542 12:40:42.244190 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
7543 12:40:42.244273
7544 12:40:42.247299 CA PerBit enable=1, Macro0, CA PI delay=37
7545 12:40:42.247408
7546 12:40:42.250649 [CBTSetCACLKResult] CA Dly = 37
7547 12:40:42.254018 CS Dly: 11 (0~43)
7548 12:40:42.257085 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7549 12:40:42.260562 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7550 12:40:42.260663
7551 12:40:42.264209 ----->DramcWriteLeveling(PI) begin...
7552 12:40:42.267145 ==
7553 12:40:42.267220 Dram Type= 6, Freq= 0, CH_0, rank 0
7554 12:40:42.274015 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7555 12:40:42.274114 ==
7556 12:40:42.276936 Write leveling (Byte 0): 36 => 36
7557 12:40:42.280520 Write leveling (Byte 1): 28 => 28
7558 12:40:42.283535 DramcWriteLeveling(PI) end<-----
7559 12:40:42.283609
7560 12:40:42.283671 ==
7561 12:40:42.287046 Dram Type= 6, Freq= 0, CH_0, rank 0
7562 12:40:42.290532 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7563 12:40:42.290606 ==
7564 12:40:42.293667 [Gating] SW mode calibration
7565 12:40:42.300336 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7566 12:40:42.306762 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7567 12:40:42.309750 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7568 12:40:42.313514 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7569 12:40:42.319734 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7570 12:40:42.323151 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7571 12:40:42.326205 1 4 16 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
7572 12:40:42.332974 1 4 20 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
7573 12:40:42.336504 1 4 24 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
7574 12:40:42.339559 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7575 12:40:42.346516 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7576 12:40:42.349533 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7577 12:40:42.352902 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7578 12:40:42.359197 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7579 12:40:42.362743 1 5 16 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
7580 12:40:42.365788 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7581 12:40:42.372753 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
7582 12:40:42.375515 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7583 12:40:42.378826 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7584 12:40:42.385685 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7585 12:40:42.388902 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 12:40:42.392121 1 6 12 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
7587 12:40:42.398991 1 6 16 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
7588 12:40:42.401875 1 6 20 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
7589 12:40:42.405187 1 6 24 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
7590 12:40:42.411899 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7591 12:40:42.414764 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7592 12:40:42.418410 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7593 12:40:42.425273 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7594 12:40:42.428152 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7595 12:40:42.431939 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7596 12:40:42.437946 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7597 12:40:42.441730 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7598 12:40:42.444558 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 12:40:42.451102 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 12:40:42.454777 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 12:40:42.457584 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 12:40:42.464351 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 12:40:42.467795 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 12:40:42.470838 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 12:40:42.477837 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 12:40:42.481196 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 12:40:42.484183 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 12:40:42.490814 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 12:40:42.493743 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 12:40:42.497396 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 12:40:42.503890 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7612 12:40:42.507534 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7613 12:40:42.510621 Total UI for P1: 0, mck2ui 16
7614 12:40:42.513997 best dqsien dly found for B0: ( 1, 9, 16)
7615 12:40:42.517055 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7616 12:40:42.523902 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7617 12:40:42.527233 1 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7618 12:40:42.530260 Total UI for P1: 0, mck2ui 16
7619 12:40:42.533921 best dqsien dly found for B1: ( 1, 9, 26)
7620 12:40:42.536942 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7621 12:40:42.540086 best DQS1 dly(MCK, UI, PI) = (1, 9, 26)
7622 12:40:42.540169
7623 12:40:42.543794 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7624 12:40:42.550492 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 26)
7625 12:40:42.550601 [Gating] SW calibration Done
7626 12:40:42.550694 ==
7627 12:40:42.553347 Dram Type= 6, Freq= 0, CH_0, rank 0
7628 12:40:42.560125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7629 12:40:42.560211 ==
7630 12:40:42.560277 RX Vref Scan: 0
7631 12:40:42.560337
7632 12:40:42.563615 RX Vref 0 -> 0, step: 1
7633 12:40:42.563687
7634 12:40:42.566982 RX Delay 0 -> 252, step: 8
7635 12:40:42.570406 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7636 12:40:42.573193 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7637 12:40:42.576786 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7638 12:40:42.583069 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7639 12:40:42.586580 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7640 12:40:42.589594 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7641 12:40:42.593209 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7642 12:40:42.596195 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7643 12:40:42.602651 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7644 12:40:42.606118 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7645 12:40:42.609291 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7646 12:40:42.612813 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
7647 12:40:42.616291 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7648 12:40:42.622456 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7649 12:40:42.625964 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7650 12:40:42.629224 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7651 12:40:42.629306 ==
7652 12:40:42.632769 Dram Type= 6, Freq= 0, CH_0, rank 0
7653 12:40:42.635685 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7654 12:40:42.639118 ==
7655 12:40:42.639200 DQS Delay:
7656 12:40:42.639265 DQS0 = 0, DQS1 = 0
7657 12:40:42.642510 DQM Delay:
7658 12:40:42.642617 DQM0 = 128, DQM1 = 123
7659 12:40:42.645674 DQ Delay:
7660 12:40:42.649155 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7661 12:40:42.652128 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
7662 12:40:42.655706 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7663 12:40:42.658577 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7664 12:40:42.658684
7665 12:40:42.658777
7666 12:40:42.658901 ==
7667 12:40:42.662276 Dram Type= 6, Freq= 0, CH_0, rank 0
7668 12:40:42.665310 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7669 12:40:42.665392 ==
7670 12:40:42.668899
7671 12:40:42.668980
7672 12:40:42.669045 TX Vref Scan disable
7673 12:40:42.671829 == TX Byte 0 ==
7674 12:40:42.675263 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7675 12:40:42.678471 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7676 12:40:42.681706 == TX Byte 1 ==
7677 12:40:42.685082 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7678 12:40:42.688553 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7679 12:40:42.691854 ==
7680 12:40:42.691936 Dram Type= 6, Freq= 0, CH_0, rank 0
7681 12:40:42.698189 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7682 12:40:42.698272 ==
7683 12:40:42.711651
7684 12:40:42.714858 TX Vref early break, caculate TX vref
7685 12:40:42.717814 TX Vref=16, minBit 8, minWin=21, winSum=363
7686 12:40:42.721315 TX Vref=18, minBit 8, minWin=22, winSum=373
7687 12:40:42.724491 TX Vref=20, minBit 8, minWin=23, winSum=383
7688 12:40:42.728047 TX Vref=22, minBit 8, minWin=23, winSum=393
7689 12:40:42.731016 TX Vref=24, minBit 8, minWin=24, winSum=402
7690 12:40:42.737511 TX Vref=26, minBit 8, minWin=25, winSum=412
7691 12:40:42.740997 TX Vref=28, minBit 8, minWin=24, winSum=410
7692 12:40:42.744471 TX Vref=30, minBit 8, minWin=24, winSum=402
7693 12:40:42.747516 TX Vref=32, minBit 8, minWin=24, winSum=398
7694 12:40:42.751179 TX Vref=34, minBit 8, minWin=22, winSum=389
7695 12:40:42.757809 [TxChooseVref] Worse bit 8, Min win 25, Win sum 412, Final Vref 26
7696 12:40:42.757892
7697 12:40:42.760603 Final TX Range 0 Vref 26
7698 12:40:42.760685
7699 12:40:42.760750 ==
7700 12:40:42.764227 Dram Type= 6, Freq= 0, CH_0, rank 0
7701 12:40:42.767769 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7702 12:40:42.767857 ==
7703 12:40:42.767922
7704 12:40:42.767981
7705 12:40:42.770968 TX Vref Scan disable
7706 12:40:42.777607 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7707 12:40:42.777690 == TX Byte 0 ==
7708 12:40:42.780496 u2DelayCellOfst[0]=11 cells (3 PI)
7709 12:40:42.783980 u2DelayCellOfst[1]=15 cells (4 PI)
7710 12:40:42.787343 u2DelayCellOfst[2]=7 cells (2 PI)
7711 12:40:42.790698 u2DelayCellOfst[3]=7 cells (2 PI)
7712 12:40:42.794026 u2DelayCellOfst[4]=7 cells (2 PI)
7713 12:40:42.796971 u2DelayCellOfst[5]=0 cells (0 PI)
7714 12:40:42.800289 u2DelayCellOfst[6]=15 cells (4 PI)
7715 12:40:42.803708 u2DelayCellOfst[7]=15 cells (4 PI)
7716 12:40:42.807475 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7717 12:40:42.810209 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7718 12:40:42.813737 == TX Byte 1 ==
7719 12:40:42.817264 u2DelayCellOfst[8]=0 cells (0 PI)
7720 12:40:42.817346 u2DelayCellOfst[9]=3 cells (1 PI)
7721 12:40:42.820306 u2DelayCellOfst[10]=7 cells (2 PI)
7722 12:40:42.823845 u2DelayCellOfst[11]=7 cells (2 PI)
7723 12:40:42.826774 u2DelayCellOfst[12]=11 cells (3 PI)
7724 12:40:42.830443 u2DelayCellOfst[13]=11 cells (3 PI)
7725 12:40:42.833506 u2DelayCellOfst[14]=15 cells (4 PI)
7726 12:40:42.837018 u2DelayCellOfst[15]=11 cells (3 PI)
7727 12:40:42.839999 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7728 12:40:42.846516 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7729 12:40:42.846599 DramC Write-DBI on
7730 12:40:42.846670 ==
7731 12:40:42.850134 Dram Type= 6, Freq= 0, CH_0, rank 0
7732 12:40:42.856723 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7733 12:40:42.856806 ==
7734 12:40:42.856872
7735 12:40:42.856935
7736 12:40:42.856993 TX Vref Scan disable
7737 12:40:42.860974 == TX Byte 0 ==
7738 12:40:42.864010 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7739 12:40:42.867544 == TX Byte 1 ==
7740 12:40:42.870613 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7741 12:40:42.873605 DramC Write-DBI off
7742 12:40:42.873687
7743 12:40:42.873752 [DATLAT]
7744 12:40:42.873811 Freq=1600, CH0 RK0
7745 12:40:42.873870
7746 12:40:42.877293 DATLAT Default: 0xf
7747 12:40:42.880426 0, 0xFFFF, sum = 0
7748 12:40:42.880515 1, 0xFFFF, sum = 0
7749 12:40:42.883516 2, 0xFFFF, sum = 0
7750 12:40:42.883599 3, 0xFFFF, sum = 0
7751 12:40:42.886998 4, 0xFFFF, sum = 0
7752 12:40:42.887081 5, 0xFFFF, sum = 0
7753 12:40:42.890289 6, 0xFFFF, sum = 0
7754 12:40:42.890372 7, 0xFFFF, sum = 0
7755 12:40:42.893923 8, 0xFFFF, sum = 0
7756 12:40:42.894007 9, 0xFFFF, sum = 0
7757 12:40:42.896948 10, 0xFFFF, sum = 0
7758 12:40:42.897038 11, 0xFFFF, sum = 0
7759 12:40:42.900343 12, 0xFFFF, sum = 0
7760 12:40:42.900426 13, 0xEFFF, sum = 0
7761 12:40:42.903252 14, 0x0, sum = 1
7762 12:40:42.903336 15, 0x0, sum = 2
7763 12:40:42.906688 16, 0x0, sum = 3
7764 12:40:42.906771 17, 0x0, sum = 4
7765 12:40:42.910012 best_step = 15
7766 12:40:42.910094
7767 12:40:42.910159 ==
7768 12:40:42.913208 Dram Type= 6, Freq= 0, CH_0, rank 0
7769 12:40:42.916562 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7770 12:40:42.916648 ==
7771 12:40:42.920003 RX Vref Scan: 1
7772 12:40:42.920111
7773 12:40:42.920204 Set Vref Range= 24 -> 127
7774 12:40:42.920301
7775 12:40:42.922930 RX Vref 24 -> 127, step: 1
7776 12:40:42.923012
7777 12:40:42.926498 RX Delay 11 -> 252, step: 4
7778 12:40:42.926608
7779 12:40:42.930038 Set Vref, RX VrefLevel [Byte0]: 24
7780 12:40:42.932842 [Byte1]: 24
7781 12:40:42.932939
7782 12:40:42.936449 Set Vref, RX VrefLevel [Byte0]: 25
7783 12:40:42.939821 [Byte1]: 25
7784 12:40:42.943444
7785 12:40:42.943526 Set Vref, RX VrefLevel [Byte0]: 26
7786 12:40:42.947214 [Byte1]: 26
7787 12:40:42.951113
7788 12:40:42.951195 Set Vref, RX VrefLevel [Byte0]: 27
7789 12:40:42.954110 [Byte1]: 27
7790 12:40:42.958585
7791 12:40:42.958666 Set Vref, RX VrefLevel [Byte0]: 28
7792 12:40:42.962277 [Byte1]: 28
7793 12:40:42.966659
7794 12:40:42.966741 Set Vref, RX VrefLevel [Byte0]: 29
7795 12:40:42.969552 [Byte1]: 29
7796 12:40:42.974160
7797 12:40:42.974242 Set Vref, RX VrefLevel [Byte0]: 30
7798 12:40:42.977133 [Byte1]: 30
7799 12:40:42.981648
7800 12:40:42.981730 Set Vref, RX VrefLevel [Byte0]: 31
7801 12:40:42.984655 [Byte1]: 31
7802 12:40:42.989418
7803 12:40:42.989500 Set Vref, RX VrefLevel [Byte0]: 32
7804 12:40:42.992343 [Byte1]: 32
7805 12:40:42.997077
7806 12:40:42.997160 Set Vref, RX VrefLevel [Byte0]: 33
7807 12:40:43.000171 [Byte1]: 33
7808 12:40:43.004086
7809 12:40:43.004182 Set Vref, RX VrefLevel [Byte0]: 34
7810 12:40:43.007739 [Byte1]: 34
7811 12:40:43.012081
7812 12:40:43.012164 Set Vref, RX VrefLevel [Byte0]: 35
7813 12:40:43.014981 [Byte1]: 35
7814 12:40:43.019501
7815 12:40:43.019582 Set Vref, RX VrefLevel [Byte0]: 36
7816 12:40:43.022867 [Byte1]: 36
7817 12:40:43.027233
7818 12:40:43.027315 Set Vref, RX VrefLevel [Byte0]: 37
7819 12:40:43.030626 [Byte1]: 37
7820 12:40:43.034732
7821 12:40:43.034813 Set Vref, RX VrefLevel [Byte0]: 38
7822 12:40:43.038413 [Byte1]: 38
7823 12:40:43.042618
7824 12:40:43.042700 Set Vref, RX VrefLevel [Byte0]: 39
7825 12:40:43.045435 [Byte1]: 39
7826 12:40:43.050352
7827 12:40:43.050460 Set Vref, RX VrefLevel [Byte0]: 40
7828 12:40:43.053272 [Byte1]: 40
7829 12:40:43.057472
7830 12:40:43.057549 Set Vref, RX VrefLevel [Byte0]: 41
7831 12:40:43.061041 [Byte1]: 41
7832 12:40:43.065010
7833 12:40:43.065113 Set Vref, RX VrefLevel [Byte0]: 42
7834 12:40:43.068669 [Byte1]: 42
7835 12:40:43.072917
7836 12:40:43.073002 Set Vref, RX VrefLevel [Byte0]: 43
7837 12:40:43.076308 [Byte1]: 43
7838 12:40:43.080557
7839 12:40:43.080638 Set Vref, RX VrefLevel [Byte0]: 44
7840 12:40:43.083513 [Byte1]: 44
7841 12:40:43.088202
7842 12:40:43.088283 Set Vref, RX VrefLevel [Byte0]: 45
7843 12:40:43.091324 [Byte1]: 45
7844 12:40:43.095481
7845 12:40:43.095563 Set Vref, RX VrefLevel [Byte0]: 46
7846 12:40:43.098810 [Byte1]: 46
7847 12:40:43.103182
7848 12:40:43.103268 Set Vref, RX VrefLevel [Byte0]: 47
7849 12:40:43.106739 [Byte1]: 47
7850 12:40:43.110722
7851 12:40:43.110804 Set Vref, RX VrefLevel [Byte0]: 48
7852 12:40:43.114161 [Byte1]: 48
7853 12:40:43.118613
7854 12:40:43.118695 Set Vref, RX VrefLevel [Byte0]: 49
7855 12:40:43.121675 [Byte1]: 49
7856 12:40:43.126256
7857 12:40:43.126338 Set Vref, RX VrefLevel [Byte0]: 50
7858 12:40:43.129748 [Byte1]: 50
7859 12:40:43.133885
7860 12:40:43.133966 Set Vref, RX VrefLevel [Byte0]: 51
7861 12:40:43.137333 [Byte1]: 51
7862 12:40:43.141288
7863 12:40:43.141369 Set Vref, RX VrefLevel [Byte0]: 52
7864 12:40:43.144808 [Byte1]: 52
7865 12:40:43.148936
7866 12:40:43.149018 Set Vref, RX VrefLevel [Byte0]: 53
7867 12:40:43.152591 [Byte1]: 53
7868 12:40:43.156714
7869 12:40:43.156796 Set Vref, RX VrefLevel [Byte0]: 54
7870 12:40:43.159561 [Byte1]: 54
7871 12:40:43.164373
7872 12:40:43.164454 Set Vref, RX VrefLevel [Byte0]: 55
7873 12:40:43.167456 [Byte1]: 55
7874 12:40:43.172059
7875 12:40:43.172141 Set Vref, RX VrefLevel [Byte0]: 56
7876 12:40:43.175085 [Byte1]: 56
7877 12:40:43.179255
7878 12:40:43.179336 Set Vref, RX VrefLevel [Byte0]: 57
7879 12:40:43.182871 [Byte1]: 57
7880 12:40:43.187110
7881 12:40:43.187217 Set Vref, RX VrefLevel [Byte0]: 58
7882 12:40:43.190340 [Byte1]: 58
7883 12:40:43.194558
7884 12:40:43.194640 Set Vref, RX VrefLevel [Byte0]: 59
7885 12:40:43.198098 [Byte1]: 59
7886 12:40:43.202286
7887 12:40:43.202369 Set Vref, RX VrefLevel [Byte0]: 60
7888 12:40:43.205282 [Byte1]: 60
7889 12:40:43.210140
7890 12:40:43.210234 Set Vref, RX VrefLevel [Byte0]: 61
7891 12:40:43.213126 [Byte1]: 61
7892 12:40:43.217330
7893 12:40:43.217412 Set Vref, RX VrefLevel [Byte0]: 62
7894 12:40:43.220653 [Byte1]: 62
7895 12:40:43.225321
7896 12:40:43.225403 Set Vref, RX VrefLevel [Byte0]: 63
7897 12:40:43.228128 [Byte1]: 63
7898 12:40:43.233002
7899 12:40:43.233089 Set Vref, RX VrefLevel [Byte0]: 64
7900 12:40:43.236106 [Byte1]: 64
7901 12:40:43.240973
7902 12:40:43.241055 Set Vref, RX VrefLevel [Byte0]: 65
7903 12:40:43.243565 [Byte1]: 65
7904 12:40:43.247841
7905 12:40:43.247927 Set Vref, RX VrefLevel [Byte0]: 66
7906 12:40:43.251072 [Byte1]: 66
7907 12:40:43.255682
7908 12:40:43.255785 Set Vref, RX VrefLevel [Byte0]: 67
7909 12:40:43.258731 [Byte1]: 67
7910 12:40:43.262843
7911 12:40:43.262932 Set Vref, RX VrefLevel [Byte0]: 68
7912 12:40:43.266494 [Byte1]: 68
7913 12:40:43.270699
7914 12:40:43.270769 Set Vref, RX VrefLevel [Byte0]: 69
7915 12:40:43.273834 [Byte1]: 69
7916 12:40:43.278800
7917 12:40:43.278912 Set Vref, RX VrefLevel [Byte0]: 70
7918 12:40:43.281817 [Byte1]: 70
7919 12:40:43.286039
7920 12:40:43.286115 Set Vref, RX VrefLevel [Byte0]: 71
7921 12:40:43.288995 [Byte1]: 71
7922 12:40:43.293284
7923 12:40:43.293371 Set Vref, RX VrefLevel [Byte0]: 72
7924 12:40:43.297008 [Byte1]: 72
7925 12:40:43.301126
7926 12:40:43.301216 Set Vref, RX VrefLevel [Byte0]: 73
7927 12:40:43.304167 [Byte1]: 73
7928 12:40:43.309025
7929 12:40:43.309113 Set Vref, RX VrefLevel [Byte0]: 74
7930 12:40:43.312108 [Byte1]: 74
7931 12:40:43.316479
7932 12:40:43.316564 Set Vref, RX VrefLevel [Byte0]: 75
7933 12:40:43.319483 [Byte1]: 75
7934 12:40:43.324301
7935 12:40:43.324378 Final RX Vref Byte 0 = 64 to rank0
7936 12:40:43.327110 Final RX Vref Byte 1 = 62 to rank0
7937 12:40:43.330707 Final RX Vref Byte 0 = 64 to rank1
7938 12:40:43.334231 Final RX Vref Byte 1 = 62 to rank1==
7939 12:40:43.337075 Dram Type= 6, Freq= 0, CH_0, rank 0
7940 12:40:43.343759 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7941 12:40:43.343842 ==
7942 12:40:43.343908 DQS Delay:
7943 12:40:43.347307 DQS0 = 0, DQS1 = 0
7944 12:40:43.347389 DQM Delay:
7945 12:40:43.347454 DQM0 = 126, DQM1 = 119
7946 12:40:43.350316 DQ Delay:
7947 12:40:43.353632 DQ0 =126, DQ1 =126, DQ2 =126, DQ3 =122
7948 12:40:43.357158 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7949 12:40:43.360203 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7950 12:40:43.363805 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =126
7951 12:40:43.363887
7952 12:40:43.363952
7953 12:40:43.364028
7954 12:40:43.366680 [DramC_TX_OE_Calibration] TA2
7955 12:40:43.370189 Original DQ_B0 (3 6) =30, OEN = 27
7956 12:40:43.373091 Original DQ_B1 (3 6) =30, OEN = 27
7957 12:40:43.376774 24, 0x0, End_B0=24 End_B1=24
7958 12:40:43.379778 25, 0x0, End_B0=25 End_B1=25
7959 12:40:43.379861 26, 0x0, End_B0=26 End_B1=26
7960 12:40:43.383366 27, 0x0, End_B0=27 End_B1=27
7961 12:40:43.386984 28, 0x0, End_B0=28 End_B1=28
7962 12:40:43.389677 29, 0x0, End_B0=29 End_B1=29
7963 12:40:43.389791 30, 0x0, End_B0=30 End_B1=30
7964 12:40:43.393381 31, 0x5151, End_B0=30 End_B1=30
7965 12:40:43.396400 Byte0 end_step=30 best_step=27
7966 12:40:43.400097 Byte1 end_step=30 best_step=27
7967 12:40:43.403010 Byte0 TX OE(2T, 0.5T) = (3, 3)
7968 12:40:43.406630 Byte1 TX OE(2T, 0.5T) = (3, 3)
7969 12:40:43.406712
7970 12:40:43.406777
7971 12:40:43.413154 [DQSOSCAuto] RK0, (LSB)MR18= 0x1313, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
7972 12:40:43.416215 CH0 RK0: MR19=303, MR18=1313
7973 12:40:43.422781 CH0_RK0: MR19=0x303, MR18=0x1313, DQSOSC=400, MR23=63, INC=23, DEC=15
7974 12:40:43.422897
7975 12:40:43.425914 ----->DramcWriteLeveling(PI) begin...
7976 12:40:43.425998 ==
7977 12:40:43.429349 Dram Type= 6, Freq= 0, CH_0, rank 1
7978 12:40:43.432718 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7979 12:40:43.432801 ==
7980 12:40:43.436268 Write leveling (Byte 0): 32 => 32
7981 12:40:43.439270 Write leveling (Byte 1): 29 => 29
7982 12:40:43.442674 DramcWriteLeveling(PI) end<-----
7983 12:40:43.442756
7984 12:40:43.442820 ==
7985 12:40:43.445770 Dram Type= 6, Freq= 0, CH_0, rank 1
7986 12:40:43.452268 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7987 12:40:43.452351 ==
7988 12:40:43.452417 [Gating] SW mode calibration
7989 12:40:43.462149 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7990 12:40:43.465438 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7991 12:40:43.469146 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7992 12:40:43.475698 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7993 12:40:43.478666 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7994 12:40:43.485238 1 4 12 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
7995 12:40:43.488827 1 4 16 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
7996 12:40:43.491915 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7997 12:40:43.498219 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7998 12:40:43.502183 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7999 12:40:43.505128 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8000 12:40:43.511754 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8001 12:40:43.515205 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8002 12:40:43.518146 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
8003 12:40:43.524718 1 5 16 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
8004 12:40:43.528352 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 12:40:43.531344 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 12:40:43.537783 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 12:40:43.541277 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8008 12:40:43.544573 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 12:40:43.551322 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8010 12:40:43.554350 1 6 12 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
8011 12:40:43.557779 1 6 16 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
8012 12:40:43.564637 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8013 12:40:43.567444 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8014 12:40:43.570741 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 12:40:43.577648 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 12:40:43.580987 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8017 12:40:43.584027 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8018 12:40:43.590739 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8019 12:40:43.593703 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8020 12:40:43.597284 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8021 12:40:43.603522 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8022 12:40:43.607007 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 12:40:43.610480 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 12:40:43.616942 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 12:40:43.620309 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 12:40:43.623279 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 12:40:43.629992 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 12:40:43.633067 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 12:40:43.636690 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 12:40:43.643432 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 12:40:43.646535 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 12:40:43.649884 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 12:40:43.656397 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8034 12:40:43.659494 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8035 12:40:43.663122 Total UI for P1: 0, mck2ui 16
8036 12:40:43.666039 best dqsien dly found for B0: ( 1, 9, 8)
8037 12:40:43.669651 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8038 12:40:43.676238 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8039 12:40:43.676323 Total UI for P1: 0, mck2ui 16
8040 12:40:43.682780 best dqsien dly found for B1: ( 1, 9, 16)
8041 12:40:43.686070 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8042 12:40:43.689520 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8043 12:40:43.689605
8044 12:40:43.692483 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8045 12:40:43.696016 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8046 12:40:43.699113 [Gating] SW calibration Done
8047 12:40:43.699196 ==
8048 12:40:43.702726 Dram Type= 6, Freq= 0, CH_0, rank 1
8049 12:40:43.705782 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8050 12:40:43.705867 ==
8051 12:40:43.709224 RX Vref Scan: 0
8052 12:40:43.709307
8053 12:40:43.709391 RX Vref 0 -> 0, step: 1
8054 12:40:43.709470
8055 12:40:43.712182 RX Delay 0 -> 252, step: 8
8056 12:40:43.715557 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8057 12:40:43.722429 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8058 12:40:43.725778 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8059 12:40:43.728814 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8060 12:40:43.731842 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8061 12:40:43.735579 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8062 12:40:43.741688 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8063 12:40:43.745313 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8064 12:40:43.748360 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8065 12:40:43.751735 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8066 12:40:43.758652 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8067 12:40:43.761690 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8068 12:40:43.765244 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8069 12:40:43.768206 iDelay=200, Bit 13, Center 127 (72 ~ 183) 112
8070 12:40:43.771661 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8071 12:40:43.778186 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8072 12:40:43.778270 ==
8073 12:40:43.781550 Dram Type= 6, Freq= 0, CH_0, rank 1
8074 12:40:43.784470 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8075 12:40:43.784579 ==
8076 12:40:43.784663 DQS Delay:
8077 12:40:43.788297 DQS0 = 0, DQS1 = 0
8078 12:40:43.788380 DQM Delay:
8079 12:40:43.791228 DQM0 = 127, DQM1 = 121
8080 12:40:43.791312 DQ Delay:
8081 12:40:43.794639 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8082 12:40:43.798147 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8083 12:40:43.801051 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8084 12:40:43.804669 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8085 12:40:43.807623
8086 12:40:43.807706
8087 12:40:43.807788 ==
8088 12:40:43.811303 Dram Type= 6, Freq= 0, CH_0, rank 1
8089 12:40:43.814240 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8090 12:40:43.814324 ==
8091 12:40:43.814408
8092 12:40:43.814506
8093 12:40:43.817686 TX Vref Scan disable
8094 12:40:43.817769 == TX Byte 0 ==
8095 12:40:43.824105 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8096 12:40:43.827657 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8097 12:40:43.827741 == TX Byte 1 ==
8098 12:40:43.834041 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8099 12:40:43.837707 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8100 12:40:43.837791 ==
8101 12:40:43.840674 Dram Type= 6, Freq= 0, CH_0, rank 1
8102 12:40:43.844472 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8103 12:40:43.844556 ==
8104 12:40:43.859007
8105 12:40:43.862344 TX Vref early break, caculate TX vref
8106 12:40:43.865954 TX Vref=16, minBit 0, minWin=22, winSum=368
8107 12:40:43.869011 TX Vref=18, minBit 8, minWin=22, winSum=374
8108 12:40:43.872593 TX Vref=20, minBit 1, minWin=23, winSum=386
8109 12:40:43.875667 TX Vref=22, minBit 0, minWin=24, winSum=391
8110 12:40:43.879398 TX Vref=24, minBit 1, minWin=24, winSum=404
8111 12:40:43.885959 TX Vref=26, minBit 1, minWin=24, winSum=405
8112 12:40:43.888703 TX Vref=28, minBit 13, minWin=24, winSum=412
8113 12:40:43.892293 TX Vref=30, minBit 8, minWin=24, winSum=406
8114 12:40:43.895695 TX Vref=32, minBit 8, minWin=23, winSum=398
8115 12:40:43.898944 TX Vref=34, minBit 8, minWin=23, winSum=395
8116 12:40:43.902459 TX Vref=36, minBit 8, minWin=22, winSum=380
8117 12:40:43.908444 [TxChooseVref] Worse bit 13, Min win 24, Win sum 412, Final Vref 28
8118 12:40:43.908529
8119 12:40:43.912006 Final TX Range 0 Vref 28
8120 12:40:43.912090
8121 12:40:43.912174 ==
8122 12:40:43.915610 Dram Type= 6, Freq= 0, CH_0, rank 1
8123 12:40:43.918481 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8124 12:40:43.922006 ==
8125 12:40:43.922107
8126 12:40:43.922205
8127 12:40:43.922302 TX Vref Scan disable
8128 12:40:43.928518 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8129 12:40:43.928602 == TX Byte 0 ==
8130 12:40:43.931948 u2DelayCellOfst[0]=11 cells (3 PI)
8131 12:40:43.935378 u2DelayCellOfst[1]=18 cells (5 PI)
8132 12:40:43.938318 u2DelayCellOfst[2]=7 cells (2 PI)
8133 12:40:43.941923 u2DelayCellOfst[3]=11 cells (3 PI)
8134 12:40:43.944922 u2DelayCellOfst[4]=7 cells (2 PI)
8135 12:40:43.948540 u2DelayCellOfst[5]=0 cells (0 PI)
8136 12:40:43.951579 u2DelayCellOfst[6]=18 cells (5 PI)
8137 12:40:43.955082 u2DelayCellOfst[7]=18 cells (5 PI)
8138 12:40:43.958144 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8139 12:40:43.961887 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8140 12:40:43.964531 == TX Byte 1 ==
8141 12:40:43.968178 u2DelayCellOfst[8]=0 cells (0 PI)
8142 12:40:43.971727 u2DelayCellOfst[9]=0 cells (0 PI)
8143 12:40:43.974714 u2DelayCellOfst[10]=3 cells (1 PI)
8144 12:40:43.977770 u2DelayCellOfst[11]=3 cells (1 PI)
8145 12:40:43.981464 u2DelayCellOfst[12]=11 cells (3 PI)
8146 12:40:43.984492 u2DelayCellOfst[13]=11 cells (3 PI)
8147 12:40:43.984576 u2DelayCellOfst[14]=11 cells (3 PI)
8148 12:40:43.988274 u2DelayCellOfst[15]=11 cells (3 PI)
8149 12:40:43.994545 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8150 12:40:43.997903 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8151 12:40:44.001324 DramC Write-DBI on
8152 12:40:44.001408 ==
8153 12:40:44.004147 Dram Type= 6, Freq= 0, CH_0, rank 1
8154 12:40:44.007561 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8155 12:40:44.007650 ==
8156 12:40:44.007734
8157 12:40:44.007812
8158 12:40:44.010996 TX Vref Scan disable
8159 12:40:44.011078 == TX Byte 0 ==
8160 12:40:44.017228 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8161 12:40:44.017338 == TX Byte 1 ==
8162 12:40:44.023888 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8163 12:40:44.023974 DramC Write-DBI off
8164 12:40:44.024041
8165 12:40:44.024100 [DATLAT]
8166 12:40:44.027490 Freq=1600, CH0 RK1
8167 12:40:44.027573
8168 12:40:44.030395 DATLAT Default: 0xf
8169 12:40:44.030480 0, 0xFFFF, sum = 0
8170 12:40:44.033824 1, 0xFFFF, sum = 0
8171 12:40:44.033908 2, 0xFFFF, sum = 0
8172 12:40:44.037353 3, 0xFFFF, sum = 0
8173 12:40:44.037437 4, 0xFFFF, sum = 0
8174 12:40:44.040254 5, 0xFFFF, sum = 0
8175 12:40:44.040338 6, 0xFFFF, sum = 0
8176 12:40:44.043646 7, 0xFFFF, sum = 0
8177 12:40:44.043730 8, 0xFFFF, sum = 0
8178 12:40:44.046839 9, 0xFFFF, sum = 0
8179 12:40:44.046982 10, 0xFFFF, sum = 0
8180 12:40:44.050276 11, 0xFFFF, sum = 0
8181 12:40:44.050384 12, 0xFFFF, sum = 0
8182 12:40:44.053332 13, 0xCFFF, sum = 0
8183 12:40:44.053438 14, 0x0, sum = 1
8184 12:40:44.056794 15, 0x0, sum = 2
8185 12:40:44.056897 16, 0x0, sum = 3
8186 12:40:44.059855 17, 0x0, sum = 4
8187 12:40:44.059958 best_step = 15
8188 12:40:44.060051
8189 12:40:44.060140 ==
8190 12:40:44.063645 Dram Type= 6, Freq= 0, CH_0, rank 1
8191 12:40:44.069596 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8192 12:40:44.069703 ==
8193 12:40:44.069801 RX Vref Scan: 0
8194 12:40:44.069891
8195 12:40:44.072993 RX Vref 0 -> 0, step: 1
8196 12:40:44.073096
8197 12:40:44.076217 RX Delay 3 -> 252, step: 4
8198 12:40:44.079629 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8199 12:40:44.082709 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8200 12:40:44.089217 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8201 12:40:44.092761 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8202 12:40:44.095840 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8203 12:40:44.099368 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8204 12:40:44.102401 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8205 12:40:44.109343 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8206 12:40:44.112751 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8207 12:40:44.115778 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8208 12:40:44.119087 iDelay=191, Bit 10, Center 118 (63 ~ 174) 112
8209 12:40:44.125919 iDelay=191, Bit 11, Center 110 (55 ~ 166) 112
8210 12:40:44.129042 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8211 12:40:44.132638 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8212 12:40:44.135529 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8213 12:40:44.139107 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8214 12:40:44.139186 ==
8215 12:40:44.142454 Dram Type= 6, Freq= 0, CH_0, rank 1
8216 12:40:44.148785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8217 12:40:44.148911 ==
8218 12:40:44.148978 DQS Delay:
8219 12:40:44.152403 DQS0 = 0, DQS1 = 0
8220 12:40:44.152478 DQM Delay:
8221 12:40:44.155435 DQM0 = 124, DQM1 = 117
8222 12:40:44.155536 DQ Delay:
8223 12:40:44.158615 DQ0 =124, DQ1 =124, DQ2 =122, DQ3 =122
8224 12:40:44.162093 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8225 12:40:44.165694 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =110
8226 12:40:44.168610 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8227 12:40:44.168708
8228 12:40:44.168800
8229 12:40:44.168894
8230 12:40:44.172270 [DramC_TX_OE_Calibration] TA2
8231 12:40:44.175165 Original DQ_B0 (3 6) =30, OEN = 27
8232 12:40:44.178629 Original DQ_B1 (3 6) =30, OEN = 27
8233 12:40:44.181958 24, 0x0, End_B0=24 End_B1=24
8234 12:40:44.185112 25, 0x0, End_B0=25 End_B1=25
8235 12:40:44.185187 26, 0x0, End_B0=26 End_B1=26
8236 12:40:44.188644 27, 0x0, End_B0=27 End_B1=27
8237 12:40:44.192123 28, 0x0, End_B0=28 End_B1=28
8238 12:40:44.195151 29, 0x0, End_B0=29 End_B1=29
8239 12:40:44.198775 30, 0x0, End_B0=30 End_B1=30
8240 12:40:44.198917 31, 0x4141, End_B0=30 End_B1=30
8241 12:40:44.201581 Byte0 end_step=30 best_step=27
8242 12:40:44.205161 Byte1 end_step=30 best_step=27
8243 12:40:44.208101 Byte0 TX OE(2T, 0.5T) = (3, 3)
8244 12:40:44.211749 Byte1 TX OE(2T, 0.5T) = (3, 3)
8245 12:40:44.211833
8246 12:40:44.211898
8247 12:40:44.217964 [DQSOSCAuto] RK1, (LSB)MR18= 0x2210, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
8248 12:40:44.221361 CH0 RK1: MR19=303, MR18=2210
8249 12:40:44.227760 CH0_RK1: MR19=0x303, MR18=0x2210, DQSOSC=392, MR23=63, INC=24, DEC=16
8250 12:40:44.231163 [RxdqsGatingPostProcess] freq 1600
8251 12:40:44.238138 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8252 12:40:44.241199 best DQS0 dly(2T, 0.5T) = (1, 1)
8253 12:40:44.241272 best DQS1 dly(2T, 0.5T) = (1, 1)
8254 12:40:44.244798 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8255 12:40:44.247646 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8256 12:40:44.251017 best DQS0 dly(2T, 0.5T) = (1, 1)
8257 12:40:44.254677 best DQS1 dly(2T, 0.5T) = (1, 1)
8258 12:40:44.257663 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8259 12:40:44.261190 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8260 12:40:44.264324 Pre-setting of DQS Precalculation
8261 12:40:44.267846 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8262 12:40:44.270814 ==
8263 12:40:44.274507 Dram Type= 6, Freq= 0, CH_1, rank 0
8264 12:40:44.277462 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8265 12:40:44.277536 ==
8266 12:40:44.281143 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8267 12:40:44.287748 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8268 12:40:44.290528 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8269 12:40:44.297241 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8270 12:40:44.305628 [CA 0] Center 41 (12~71) winsize 60
8271 12:40:44.309128 [CA 1] Center 42 (13~72) winsize 60
8272 12:40:44.312169 [CA 2] Center 38 (9~67) winsize 59
8273 12:40:44.315771 [CA 3] Center 37 (8~66) winsize 59
8274 12:40:44.318802 [CA 4] Center 37 (8~67) winsize 60
8275 12:40:44.322522 [CA 5] Center 36 (7~66) winsize 60
8276 12:40:44.322597
8277 12:40:44.325306 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8278 12:40:44.325381
8279 12:40:44.328637 [CATrainingPosCal] consider 1 rank data
8280 12:40:44.332184 u2DelayCellTimex100 = 258/100 ps
8281 12:40:44.338796 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8282 12:40:44.341647 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8283 12:40:44.345171 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8284 12:40:44.348799 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8285 12:40:44.351715 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8286 12:40:44.355068 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8287 12:40:44.355170
8288 12:40:44.358648 CA PerBit enable=1, Macro0, CA PI delay=36
8289 12:40:44.358736
8290 12:40:44.361510 [CBTSetCACLKResult] CA Dly = 36
8291 12:40:44.364982 CS Dly: 9 (0~40)
8292 12:40:44.368418 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8293 12:40:44.371431 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8294 12:40:44.371506 ==
8295 12:40:44.375020 Dram Type= 6, Freq= 0, CH_1, rank 1
8296 12:40:44.381641 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8297 12:40:44.381719 ==
8298 12:40:44.384690 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8299 12:40:44.391314 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8300 12:40:44.394730 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8301 12:40:44.400772 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8302 12:40:44.408428 [CA 0] Center 42 (13~71) winsize 59
8303 12:40:44.411950 [CA 1] Center 42 (12~72) winsize 61
8304 12:40:44.415423 [CA 2] Center 37 (8~67) winsize 60
8305 12:40:44.418572 [CA 3] Center 36 (7~66) winsize 60
8306 12:40:44.421520 [CA 4] Center 37 (8~67) winsize 60
8307 12:40:44.425260 [CA 5] Center 36 (6~66) winsize 61
8308 12:40:44.425336
8309 12:40:44.428124 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8310 12:40:44.428208
8311 12:40:44.435009 [CATrainingPosCal] consider 2 rank data
8312 12:40:44.435085 u2DelayCellTimex100 = 258/100 ps
8313 12:40:44.442075 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8314 12:40:44.445142 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8315 12:40:44.447997 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8316 12:40:44.451504 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8317 12:40:44.455065 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8318 12:40:44.457960 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8319 12:40:44.458042
8320 12:40:44.461496 CA PerBit enable=1, Macro0, CA PI delay=36
8321 12:40:44.461574
8322 12:40:44.464628 [CBTSetCACLKResult] CA Dly = 36
8323 12:40:44.467636 CS Dly: 10 (0~43)
8324 12:40:44.471162 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8325 12:40:44.474414 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8326 12:40:44.474520
8327 12:40:44.477961 ----->DramcWriteLeveling(PI) begin...
8328 12:40:44.478039 ==
8329 12:40:44.480935 Dram Type= 6, Freq= 0, CH_1, rank 0
8330 12:40:44.487632 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8331 12:40:44.487736 ==
8332 12:40:44.491260 Write leveling (Byte 0): 24 => 24
8333 12:40:44.494210 Write leveling (Byte 1): 28 => 28
8334 12:40:44.497409 DramcWriteLeveling(PI) end<-----
8335 12:40:44.497510
8336 12:40:44.497617 ==
8337 12:40:44.500802 Dram Type= 6, Freq= 0, CH_1, rank 0
8338 12:40:44.504362 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8339 12:40:44.504469 ==
8340 12:40:44.507279 [Gating] SW mode calibration
8341 12:40:44.514119 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8342 12:40:44.520498 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8343 12:40:44.524143 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8344 12:40:44.527191 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8345 12:40:44.533899 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 12:40:44.537135 1 4 12 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8347 12:40:44.540302 1 4 16 | B1->B0 | 3333 3232 | 1 1 | (1 1) (1 1)
8348 12:40:44.546995 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8349 12:40:44.550572 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8350 12:40:44.553439 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8351 12:40:44.560324 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8352 12:40:44.563244 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8353 12:40:44.566800 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8354 12:40:44.573695 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8355 12:40:44.576473 1 5 16 | B1->B0 | 2828 2828 | 0 0 | (1 0) (1 0)
8356 12:40:44.579864 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8357 12:40:44.586392 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 12:40:44.589975 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 12:40:44.593011 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 12:40:44.599576 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 12:40:44.603180 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 12:40:44.606697 1 6 12 | B1->B0 | 2525 2424 | 1 0 | (0 0) (0 0)
8363 12:40:44.612616 1 6 16 | B1->B0 | 4645 4646 | 1 0 | (0 0) (0 0)
8364 12:40:44.616070 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 12:40:44.619721 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 12:40:44.625916 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 12:40:44.629655 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8368 12:40:44.632729 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 12:40:44.639056 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8370 12:40:44.642618 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8371 12:40:44.645667 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8372 12:40:44.652396 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 12:40:44.655844 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 12:40:44.659217 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 12:40:44.665448 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 12:40:44.669018 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 12:40:44.672527 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 12:40:44.678562 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 12:40:44.682012 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 12:40:44.685562 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 12:40:44.692026 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 12:40:44.695162 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 12:40:44.698331 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 12:40:44.705164 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 12:40:44.708261 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 12:40:44.711891 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8387 12:40:44.718620 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8388 12:40:44.721885 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 12:40:44.724884 Total UI for P1: 0, mck2ui 16
8390 12:40:44.728292 best dqsien dly found for B0: ( 1, 9, 16)
8391 12:40:44.731216 Total UI for P1: 0, mck2ui 16
8392 12:40:44.734821 best dqsien dly found for B1: ( 1, 9, 14)
8393 12:40:44.737798 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8394 12:40:44.741250 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8395 12:40:44.741332
8396 12:40:44.744792 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8397 12:40:44.747627 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8398 12:40:44.751209 [Gating] SW calibration Done
8399 12:40:44.751292 ==
8400 12:40:44.754748 Dram Type= 6, Freq= 0, CH_1, rank 0
8401 12:40:44.757782 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8402 12:40:44.761141 ==
8403 12:40:44.761250 RX Vref Scan: 0
8404 12:40:44.761349
8405 12:40:44.764231 RX Vref 0 -> 0, step: 1
8406 12:40:44.764312
8407 12:40:44.767614 RX Delay 0 -> 252, step: 8
8408 12:40:44.770845 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8409 12:40:44.774472 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8410 12:40:44.777298 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8411 12:40:44.780906 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8412 12:40:44.787470 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8413 12:40:44.791000 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8414 12:40:44.793855 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8415 12:40:44.797458 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8416 12:40:44.800499 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8417 12:40:44.807095 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8418 12:40:44.810581 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8419 12:40:44.814029 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8420 12:40:44.817329 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8421 12:40:44.820320 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8422 12:40:44.826842 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8423 12:40:44.830207 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8424 12:40:44.830289 ==
8425 12:40:44.833689 Dram Type= 6, Freq= 0, CH_1, rank 0
8426 12:40:44.836581 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8427 12:40:44.836665 ==
8428 12:40:44.840205 DQS Delay:
8429 12:40:44.840287 DQS0 = 0, DQS1 = 0
8430 12:40:44.843297 DQM Delay:
8431 12:40:44.843379 DQM0 = 131, DQM1 = 126
8432 12:40:44.843445 DQ Delay:
8433 12:40:44.850163 DQ0 =135, DQ1 =123, DQ2 =123, DQ3 =131
8434 12:40:44.853610 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =127
8435 12:40:44.856621 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8436 12:40:44.859676 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8437 12:40:44.859759
8438 12:40:44.859823
8439 12:40:44.859882 ==
8440 12:40:44.863243 Dram Type= 6, Freq= 0, CH_1, rank 0
8441 12:40:44.866853 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8442 12:40:44.866951 ==
8443 12:40:44.867017
8444 12:40:44.867077
8445 12:40:44.869606 TX Vref Scan disable
8446 12:40:44.873233 == TX Byte 0 ==
8447 12:40:44.876490 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8448 12:40:44.879930 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8449 12:40:44.882719 == TX Byte 1 ==
8450 12:40:44.886467 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8451 12:40:44.889429 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8452 12:40:44.889512 ==
8453 12:40:44.892817 Dram Type= 6, Freq= 0, CH_1, rank 0
8454 12:40:44.899298 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8455 12:40:44.899381 ==
8456 12:40:44.911974
8457 12:40:44.915568 TX Vref early break, caculate TX vref
8458 12:40:44.918579 TX Vref=16, minBit 9, minWin=21, winSum=357
8459 12:40:44.921995 TX Vref=18, minBit 9, minWin=21, winSum=373
8460 12:40:44.925636 TX Vref=20, minBit 1, minWin=23, winSum=380
8461 12:40:44.928642 TX Vref=22, minBit 0, minWin=24, winSum=392
8462 12:40:44.931797 TX Vref=24, minBit 5, minWin=25, winSum=408
8463 12:40:44.938701 TX Vref=26, minBit 0, minWin=25, winSum=414
8464 12:40:44.942045 TX Vref=28, minBit 0, minWin=25, winSum=414
8465 12:40:44.945494 TX Vref=30, minBit 0, minWin=24, winSum=409
8466 12:40:44.948482 TX Vref=32, minBit 0, minWin=24, winSum=406
8467 12:40:44.951880 TX Vref=34, minBit 0, minWin=24, winSum=398
8468 12:40:44.955280 TX Vref=36, minBit 6, minWin=22, winSum=381
8469 12:40:44.962035 [TxChooseVref] Worse bit 0, Min win 25, Win sum 414, Final Vref 26
8470 12:40:44.962146
8471 12:40:44.965117 Final TX Range 0 Vref 26
8472 12:40:44.965224
8473 12:40:44.965320 ==
8474 12:40:44.968616 Dram Type= 6, Freq= 0, CH_1, rank 0
8475 12:40:44.971429 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8476 12:40:44.971536 ==
8477 12:40:44.971629
8478 12:40:44.974817
8479 12:40:44.974939 TX Vref Scan disable
8480 12:40:44.981703 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8481 12:40:44.981807 == TX Byte 0 ==
8482 12:40:44.984599 u2DelayCellOfst[0]=18 cells (5 PI)
8483 12:40:44.988143 u2DelayCellOfst[1]=18 cells (5 PI)
8484 12:40:44.991551 u2DelayCellOfst[2]=0 cells (0 PI)
8485 12:40:44.994608 u2DelayCellOfst[3]=7 cells (2 PI)
8486 12:40:44.998084 u2DelayCellOfst[4]=11 cells (3 PI)
8487 12:40:45.001053 u2DelayCellOfst[5]=22 cells (6 PI)
8488 12:40:45.005142 u2DelayCellOfst[6]=22 cells (6 PI)
8489 12:40:45.007638 u2DelayCellOfst[7]=7 cells (2 PI)
8490 12:40:45.011243 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8491 12:40:45.014207 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8492 12:40:45.017778 == TX Byte 1 ==
8493 12:40:45.020919 u2DelayCellOfst[8]=0 cells (0 PI)
8494 12:40:45.024242 u2DelayCellOfst[9]=7 cells (2 PI)
8495 12:40:45.027736 u2DelayCellOfst[10]=15 cells (4 PI)
8496 12:40:45.030787 u2DelayCellOfst[11]=7 cells (2 PI)
8497 12:40:45.034428 u2DelayCellOfst[12]=18 cells (5 PI)
8498 12:40:45.037368 u2DelayCellOfst[13]=22 cells (6 PI)
8499 12:40:45.037475 u2DelayCellOfst[14]=22 cells (6 PI)
8500 12:40:45.040914 u2DelayCellOfst[15]=22 cells (6 PI)
8501 12:40:45.047230 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8502 12:40:45.050565 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8503 12:40:45.054085 DramC Write-DBI on
8504 12:40:45.054190 ==
8505 12:40:45.057562 Dram Type= 6, Freq= 0, CH_1, rank 0
8506 12:40:45.060406 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8507 12:40:45.060516 ==
8508 12:40:45.060609
8509 12:40:45.060707
8510 12:40:45.064077 TX Vref Scan disable
8511 12:40:45.064177 == TX Byte 0 ==
8512 12:40:45.070644 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8513 12:40:45.070753 == TX Byte 1 ==
8514 12:40:45.073734 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8515 12:40:45.077213 DramC Write-DBI off
8516 12:40:45.077311
8517 12:40:45.077411 [DATLAT]
8518 12:40:45.080648 Freq=1600, CH1 RK0
8519 12:40:45.080749
8520 12:40:45.080846 DATLAT Default: 0xf
8521 12:40:45.083530 0, 0xFFFF, sum = 0
8522 12:40:45.083606 1, 0xFFFF, sum = 0
8523 12:40:45.086958 2, 0xFFFF, sum = 0
8524 12:40:45.090453 3, 0xFFFF, sum = 0
8525 12:40:45.090566 4, 0xFFFF, sum = 0
8526 12:40:45.093450 5, 0xFFFF, sum = 0
8527 12:40:45.093554 6, 0xFFFF, sum = 0
8528 12:40:45.096835 7, 0xFFFF, sum = 0
8529 12:40:45.096941 8, 0xFFFF, sum = 0
8530 12:40:45.100269 9, 0xFFFF, sum = 0
8531 12:40:45.100370 10, 0xFFFF, sum = 0
8532 12:40:45.103244 11, 0xFFFF, sum = 0
8533 12:40:45.103351 12, 0xFFFF, sum = 0
8534 12:40:45.106854 13, 0x8FFF, sum = 0
8535 12:40:45.106945 14, 0x0, sum = 1
8536 12:40:45.109736 15, 0x0, sum = 2
8537 12:40:45.109840 16, 0x0, sum = 3
8538 12:40:45.113206 17, 0x0, sum = 4
8539 12:40:45.113316 best_step = 15
8540 12:40:45.113408
8541 12:40:45.113498 ==
8542 12:40:45.116822 Dram Type= 6, Freq= 0, CH_1, rank 0
8543 12:40:45.122904 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8544 12:40:45.123011 ==
8545 12:40:45.123110 RX Vref Scan: 1
8546 12:40:45.123202
8547 12:40:45.126404 Set Vref Range= 24 -> 127
8548 12:40:45.126514
8549 12:40:45.129732 RX Vref 24 -> 127, step: 1
8550 12:40:45.129836
8551 12:40:45.129932 RX Delay 11 -> 252, step: 4
8552 12:40:45.132760
8553 12:40:45.132859 Set Vref, RX VrefLevel [Byte0]: 24
8554 12:40:45.136263 [Byte1]: 24
8555 12:40:45.140636
8556 12:40:45.140740 Set Vref, RX VrefLevel [Byte0]: 25
8557 12:40:45.143707 [Byte1]: 25
8558 12:40:45.148438
8559 12:40:45.148556 Set Vref, RX VrefLevel [Byte0]: 26
8560 12:40:45.151496 [Byte1]: 26
8561 12:40:45.155969
8562 12:40:45.156079 Set Vref, RX VrefLevel [Byte0]: 27
8563 12:40:45.158913 [Byte1]: 27
8564 12:40:45.163235
8565 12:40:45.163349 Set Vref, RX VrefLevel [Byte0]: 28
8566 12:40:45.166801 [Byte1]: 28
8567 12:40:45.170835
8568 12:40:45.170946 Set Vref, RX VrefLevel [Byte0]: 29
8569 12:40:45.173974 [Byte1]: 29
8570 12:40:45.178807
8571 12:40:45.178954 Set Vref, RX VrefLevel [Byte0]: 30
8572 12:40:45.181840 [Byte1]: 30
8573 12:40:45.186634
8574 12:40:45.186745 Set Vref, RX VrefLevel [Byte0]: 31
8575 12:40:45.189291 [Byte1]: 31
8576 12:40:45.194042
8577 12:40:45.194145 Set Vref, RX VrefLevel [Byte0]: 32
8578 12:40:45.196978 [Byte1]: 32
8579 12:40:45.201578
8580 12:40:45.201673 Set Vref, RX VrefLevel [Byte0]: 33
8581 12:40:45.204454 [Byte1]: 33
8582 12:40:45.209238
8583 12:40:45.209348 Set Vref, RX VrefLevel [Byte0]: 34
8584 12:40:45.212260 [Byte1]: 34
8585 12:40:45.216563
8586 12:40:45.216665 Set Vref, RX VrefLevel [Byte0]: 35
8587 12:40:45.220022 [Byte1]: 35
8588 12:40:45.224176
8589 12:40:45.224286 Set Vref, RX VrefLevel [Byte0]: 36
8590 12:40:45.227271 [Byte1]: 36
8591 12:40:45.231885
8592 12:40:45.231997 Set Vref, RX VrefLevel [Byte0]: 37
8593 12:40:45.234862 [Byte1]: 37
8594 12:40:45.239202
8595 12:40:45.239307 Set Vref, RX VrefLevel [Byte0]: 38
8596 12:40:45.242703 [Byte1]: 38
8597 12:40:45.246952
8598 12:40:45.247058 Set Vref, RX VrefLevel [Byte0]: 39
8599 12:40:45.250531 [Byte1]: 39
8600 12:40:45.254958
8601 12:40:45.255065 Set Vref, RX VrefLevel [Byte0]: 40
8602 12:40:45.257869 [Byte1]: 40
8603 12:40:45.262603
8604 12:40:45.262715 Set Vref, RX VrefLevel [Byte0]: 41
8605 12:40:45.265484 [Byte1]: 41
8606 12:40:45.269981
8607 12:40:45.270083 Set Vref, RX VrefLevel [Byte0]: 42
8608 12:40:45.273457 [Byte1]: 42
8609 12:40:45.277614
8610 12:40:45.277720 Set Vref, RX VrefLevel [Byte0]: 43
8611 12:40:45.280687 [Byte1]: 43
8612 12:40:45.284888
8613 12:40:45.284992 Set Vref, RX VrefLevel [Byte0]: 44
8614 12:40:45.288760 [Byte1]: 44
8615 12:40:45.292498
8616 12:40:45.292602 Set Vref, RX VrefLevel [Byte0]: 45
8617 12:40:45.296007 [Byte1]: 45
8618 12:40:45.300612
8619 12:40:45.300720 Set Vref, RX VrefLevel [Byte0]: 46
8620 12:40:45.303658 [Byte1]: 46
8621 12:40:45.308037
8622 12:40:45.308141 Set Vref, RX VrefLevel [Byte0]: 47
8623 12:40:45.310966 [Byte1]: 47
8624 12:40:45.315702
8625 12:40:45.318708 Set Vref, RX VrefLevel [Byte0]: 48
8626 12:40:45.322326 [Byte1]: 48
8627 12:40:45.322428
8628 12:40:45.325174 Set Vref, RX VrefLevel [Byte0]: 49
8629 12:40:45.328601 [Byte1]: 49
8630 12:40:45.328704
8631 12:40:45.331638 Set Vref, RX VrefLevel [Byte0]: 50
8632 12:40:45.335241 [Byte1]: 50
8633 12:40:45.338636
8634 12:40:45.338761 Set Vref, RX VrefLevel [Byte0]: 51
8635 12:40:45.341533 [Byte1]: 51
8636 12:40:45.346338
8637 12:40:45.346446 Set Vref, RX VrefLevel [Byte0]: 52
8638 12:40:45.349362 [Byte1]: 52
8639 12:40:45.353586
8640 12:40:45.353692 Set Vref, RX VrefLevel [Byte0]: 53
8641 12:40:45.357177 [Byte1]: 53
8642 12:40:45.361206
8643 12:40:45.361309 Set Vref, RX VrefLevel [Byte0]: 54
8644 12:40:45.364733 [Byte1]: 54
8645 12:40:45.368904
8646 12:40:45.369007 Set Vref, RX VrefLevel [Byte0]: 55
8647 12:40:45.372026 [Byte1]: 55
8648 12:40:45.376450
8649 12:40:45.376560 Set Vref, RX VrefLevel [Byte0]: 56
8650 12:40:45.379661 [Byte1]: 56
8651 12:40:45.384358
8652 12:40:45.384450 Set Vref, RX VrefLevel [Byte0]: 57
8653 12:40:45.387457 [Byte1]: 57
8654 12:40:45.391689
8655 12:40:45.391788 Set Vref, RX VrefLevel [Byte0]: 58
8656 12:40:45.395246 [Byte1]: 58
8657 12:40:45.399245
8658 12:40:45.399320 Set Vref, RX VrefLevel [Byte0]: 59
8659 12:40:45.402683 [Byte1]: 59
8660 12:40:45.406969
8661 12:40:45.407043 Set Vref, RX VrefLevel [Byte0]: 60
8662 12:40:45.410240 [Byte1]: 60
8663 12:40:45.414640
8664 12:40:45.417966 Set Vref, RX VrefLevel [Byte0]: 61
8665 12:40:45.420867 [Byte1]: 61
8666 12:40:45.420942
8667 12:40:45.424556 Set Vref, RX VrefLevel [Byte0]: 62
8668 12:40:45.427470 [Byte1]: 62
8669 12:40:45.427548
8670 12:40:45.431065 Set Vref, RX VrefLevel [Byte0]: 63
8671 12:40:45.434121 [Byte1]: 63
8672 12:40:45.437213
8673 12:40:45.437286 Set Vref, RX VrefLevel [Byte0]: 64
8674 12:40:45.440511 [Byte1]: 64
8675 12:40:45.445202
8676 12:40:45.445299 Set Vref, RX VrefLevel [Byte0]: 65
8677 12:40:45.448251 [Byte1]: 65
8678 12:40:45.452577
8679 12:40:45.452678 Set Vref, RX VrefLevel [Byte0]: 66
8680 12:40:45.455629 [Byte1]: 66
8681 12:40:45.460313
8682 12:40:45.460411 Set Vref, RX VrefLevel [Byte0]: 67
8683 12:40:45.463426 [Byte1]: 67
8684 12:40:45.468384
8685 12:40:45.468482 Set Vref, RX VrefLevel [Byte0]: 68
8686 12:40:45.470996 [Byte1]: 68
8687 12:40:45.475730
8688 12:40:45.475833 Set Vref, RX VrefLevel [Byte0]: 69
8689 12:40:45.478759 [Byte1]: 69
8690 12:40:45.483113
8691 12:40:45.483196 Set Vref, RX VrefLevel [Byte0]: 70
8692 12:40:45.486143 [Byte1]: 70
8693 12:40:45.490958
8694 12:40:45.491055 Set Vref, RX VrefLevel [Byte0]: 71
8695 12:40:45.493901 [Byte1]: 71
8696 12:40:45.498206
8697 12:40:45.498313 Final RX Vref Byte 0 = 57 to rank0
8698 12:40:45.501730 Final RX Vref Byte 1 = 56 to rank0
8699 12:40:45.504706 Final RX Vref Byte 0 = 57 to rank1
8700 12:40:45.508094 Final RX Vref Byte 1 = 56 to rank1==
8701 12:40:45.511428 Dram Type= 6, Freq= 0, CH_1, rank 0
8702 12:40:45.517725 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8703 12:40:45.517803 ==
8704 12:40:45.517868 DQS Delay:
8705 12:40:45.521050 DQS0 = 0, DQS1 = 0
8706 12:40:45.521132 DQM Delay:
8707 12:40:45.521197 DQM0 = 131, DQM1 = 123
8708 12:40:45.524518 DQ Delay:
8709 12:40:45.528120 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =128
8710 12:40:45.531127 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =128
8711 12:40:45.534952 DQ8 =108, DQ9 =114, DQ10 =122, DQ11 =116
8712 12:40:45.537722 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8713 12:40:45.537821
8714 12:40:45.537918
8715 12:40:45.538006
8716 12:40:45.541307 [DramC_TX_OE_Calibration] TA2
8717 12:40:45.544254 Original DQ_B0 (3 6) =30, OEN = 27
8718 12:40:45.547723 Original DQ_B1 (3 6) =30, OEN = 27
8719 12:40:45.551224 24, 0x0, End_B0=24 End_B1=24
8720 12:40:45.554250 25, 0x0, End_B0=25 End_B1=25
8721 12:40:45.554359 26, 0x0, End_B0=26 End_B1=26
8722 12:40:45.557312 27, 0x0, End_B0=27 End_B1=27
8723 12:40:45.561002 28, 0x0, End_B0=28 End_B1=28
8724 12:40:45.563955 29, 0x0, End_B0=29 End_B1=29
8725 12:40:45.564027 30, 0x0, End_B0=30 End_B1=30
8726 12:40:45.567595 31, 0x4141, End_B0=30 End_B1=30
8727 12:40:45.571111 Byte0 end_step=30 best_step=27
8728 12:40:45.573981 Byte1 end_step=30 best_step=27
8729 12:40:45.577581 Byte0 TX OE(2T, 0.5T) = (3, 3)
8730 12:40:45.580545 Byte1 TX OE(2T, 0.5T) = (3, 3)
8731 12:40:45.580616
8732 12:40:45.580687
8733 12:40:45.587203 [DQSOSCAuto] RK0, (LSB)MR18= 0x90d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
8734 12:40:45.590643 CH1 RK0: MR19=303, MR18=90D
8735 12:40:45.597272 CH1_RK0: MR19=0x303, MR18=0x90D, DQSOSC=403, MR23=63, INC=22, DEC=15
8736 12:40:45.597374
8737 12:40:45.600563 ----->DramcWriteLeveling(PI) begin...
8738 12:40:45.600662 ==
8739 12:40:45.603542 Dram Type= 6, Freq= 0, CH_1, rank 1
8740 12:40:45.607117 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8741 12:40:45.607200 ==
8742 12:40:45.610290 Write leveling (Byte 0): 24 => 24
8743 12:40:45.613828 Write leveling (Byte 1): 28 => 28
8744 12:40:45.616697 DramcWriteLeveling(PI) end<-----
8745 12:40:45.616779
8746 12:40:45.616844 ==
8747 12:40:45.619903 Dram Type= 6, Freq= 0, CH_1, rank 1
8748 12:40:45.623315 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8749 12:40:45.626699 ==
8750 12:40:45.626807 [Gating] SW mode calibration
8751 12:40:45.636978 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8752 12:40:45.639984 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8753 12:40:45.643494 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8754 12:40:45.649806 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8755 12:40:45.653322 1 4 8 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
8756 12:40:45.656358 1 4 12 | B1->B0 | 3131 3434 | 0 1 | (1 1) (1 1)
8757 12:40:45.662966 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8758 12:40:45.666538 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8759 12:40:45.669614 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8760 12:40:45.676089 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8761 12:40:45.679502 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8762 12:40:45.682687 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8763 12:40:45.689194 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8764 12:40:45.692806 1 5 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8765 12:40:45.695814 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8766 12:40:45.702768 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 12:40:45.705551 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 12:40:45.709105 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 12:40:45.715770 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 12:40:45.718699 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8771 12:40:45.722187 1 6 8 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
8772 12:40:45.729001 1 6 12 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
8773 12:40:45.732459 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8774 12:40:45.735251 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8775 12:40:45.741784 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8776 12:40:45.745469 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 12:40:45.748544 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8778 12:40:45.755258 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8779 12:40:45.758279 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8780 12:40:45.761546 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8781 12:40:45.768314 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 12:40:45.771482 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 12:40:45.778027 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 12:40:45.781700 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 12:40:45.784344 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 12:40:45.791027 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 12:40:45.794159 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 12:40:45.797806 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 12:40:45.804303 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 12:40:45.807379 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 12:40:45.810289 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 12:40:45.817229 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 12:40:45.820216 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 12:40:45.823811 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8795 12:40:45.830252 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8796 12:40:45.834105 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8797 12:40:45.837266 Total UI for P1: 0, mck2ui 16
8798 12:40:45.840053 best dqsien dly found for B0: ( 1, 9, 6)
8799 12:40:45.843472 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8800 12:40:45.850034 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 12:40:45.850119 Total UI for P1: 0, mck2ui 16
8802 12:40:45.856641 best dqsien dly found for B1: ( 1, 9, 14)
8803 12:40:45.860250 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8804 12:40:45.863620 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8805 12:40:45.863704
8806 12:40:45.866433 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8807 12:40:45.869670 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8808 12:40:45.873340 [Gating] SW calibration Done
8809 12:40:45.873424 ==
8810 12:40:45.876333 Dram Type= 6, Freq= 0, CH_1, rank 1
8811 12:40:45.879897 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8812 12:40:45.879982 ==
8813 12:40:45.882996 RX Vref Scan: 0
8814 12:40:45.883085
8815 12:40:45.883169 RX Vref 0 -> 0, step: 1
8816 12:40:45.883249
8817 12:40:45.886775 RX Delay 0 -> 252, step: 8
8818 12:40:45.890036 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8819 12:40:45.896721 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8820 12:40:45.899693 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8821 12:40:45.902729 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8822 12:40:45.906268 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8823 12:40:45.909674 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8824 12:40:45.916228 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8825 12:40:45.919553 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8826 12:40:45.922572 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8827 12:40:45.926172 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8828 12:40:45.929318 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8829 12:40:45.935909 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8830 12:40:45.938979 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8831 12:40:45.942464 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8832 12:40:45.945378 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8833 12:40:45.952118 iDelay=200, Bit 15, Center 135 (72 ~ 199) 128
8834 12:40:45.952202 ==
8835 12:40:45.956008 Dram Type= 6, Freq= 0, CH_1, rank 1
8836 12:40:45.959342 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8837 12:40:45.959425 ==
8838 12:40:45.959491 DQS Delay:
8839 12:40:45.962325 DQS0 = 0, DQS1 = 0
8840 12:40:45.962406 DQM Delay:
8841 12:40:45.965349 DQM0 = 132, DQM1 = 127
8842 12:40:45.965437 DQ Delay:
8843 12:40:45.968961 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8844 12:40:45.972648 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =131
8845 12:40:45.975301 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8846 12:40:45.978981 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8847 12:40:45.981710
8848 12:40:45.981791
8849 12:40:45.981856 ==
8850 12:40:45.985354 Dram Type= 6, Freq= 0, CH_1, rank 1
8851 12:40:45.988982 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8852 12:40:45.989066 ==
8853 12:40:45.989131
8854 12:40:45.989192
8855 12:40:45.991865 TX Vref Scan disable
8856 12:40:45.991948 == TX Byte 0 ==
8857 12:40:45.998330 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8858 12:40:46.002001 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8859 12:40:46.002084 == TX Byte 1 ==
8860 12:40:46.008142 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8861 12:40:46.011608 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8862 12:40:46.011704 ==
8863 12:40:46.014560 Dram Type= 6, Freq= 0, CH_1, rank 1
8864 12:40:46.018290 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8865 12:40:46.018373 ==
8866 12:40:46.031957
8867 12:40:46.035481 TX Vref early break, caculate TX vref
8868 12:40:46.038481 TX Vref=16, minBit 0, minWin=23, winSum=386
8869 12:40:46.042062 TX Vref=18, minBit 0, minWin=23, winSum=391
8870 12:40:46.045148 TX Vref=20, minBit 0, minWin=24, winSum=403
8871 12:40:46.048741 TX Vref=22, minBit 0, minWin=24, winSum=411
8872 12:40:46.051699 TX Vref=24, minBit 0, minWin=25, winSum=419
8873 12:40:46.058167 TX Vref=26, minBit 0, minWin=26, winSum=426
8874 12:40:46.061612 TX Vref=28, minBit 0, minWin=26, winSum=424
8875 12:40:46.064994 TX Vref=30, minBit 0, minWin=25, winSum=419
8876 12:40:46.068095 TX Vref=32, minBit 1, minWin=24, winSum=412
8877 12:40:46.071472 TX Vref=34, minBit 1, minWin=23, winSum=401
8878 12:40:46.078405 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 26
8879 12:40:46.078491
8880 12:40:46.081471 Final TX Range 0 Vref 26
8881 12:40:46.081557
8882 12:40:46.081657 ==
8883 12:40:46.084743 Dram Type= 6, Freq= 0, CH_1, rank 1
8884 12:40:46.088205 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8885 12:40:46.088290 ==
8886 12:40:46.088374
8887 12:40:46.088453
8888 12:40:46.091248 TX Vref Scan disable
8889 12:40:46.097653 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8890 12:40:46.097738 == TX Byte 0 ==
8891 12:40:46.101225 u2DelayCellOfst[0]=18 cells (5 PI)
8892 12:40:46.104298 u2DelayCellOfst[1]=15 cells (4 PI)
8893 12:40:46.107361 u2DelayCellOfst[2]=0 cells (0 PI)
8894 12:40:46.111024 u2DelayCellOfst[3]=3 cells (1 PI)
8895 12:40:46.114021 u2DelayCellOfst[4]=7 cells (2 PI)
8896 12:40:46.117406 u2DelayCellOfst[5]=22 cells (6 PI)
8897 12:40:46.120914 u2DelayCellOfst[6]=22 cells (6 PI)
8898 12:40:46.124084 u2DelayCellOfst[7]=7 cells (2 PI)
8899 12:40:46.127629 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8900 12:40:46.130619 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8901 12:40:46.133836 == TX Byte 1 ==
8902 12:40:46.137496 u2DelayCellOfst[8]=0 cells (0 PI)
8903 12:40:46.140416 u2DelayCellOfst[9]=7 cells (2 PI)
8904 12:40:46.144091 u2DelayCellOfst[10]=15 cells (4 PI)
8905 12:40:46.144175 u2DelayCellOfst[11]=7 cells (2 PI)
8906 12:40:46.147164 u2DelayCellOfst[12]=18 cells (5 PI)
8907 12:40:46.150623 u2DelayCellOfst[13]=18 cells (5 PI)
8908 12:40:46.153604 u2DelayCellOfst[14]=22 cells (6 PI)
8909 12:40:46.157287 u2DelayCellOfst[15]=18 cells (5 PI)
8910 12:40:46.163821 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8911 12:40:46.166934 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8912 12:40:46.167041 DramC Write-DBI on
8913 12:40:46.170393 ==
8914 12:40:46.173529 Dram Type= 6, Freq= 0, CH_1, rank 1
8915 12:40:46.176988 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8916 12:40:46.177073 ==
8917 12:40:46.177141
8918 12:40:46.177211
8919 12:40:46.179852 TX Vref Scan disable
8920 12:40:46.179929 == TX Byte 0 ==
8921 12:40:46.186866 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8922 12:40:46.186961 == TX Byte 1 ==
8923 12:40:46.190153 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8924 12:40:46.193665 DramC Write-DBI off
8925 12:40:46.193747
8926 12:40:46.193844 [DATLAT]
8927 12:40:46.196828 Freq=1600, CH1 RK1
8928 12:40:46.196901
8929 12:40:46.196963 DATLAT Default: 0xf
8930 12:40:46.200186 0, 0xFFFF, sum = 0
8931 12:40:46.200274 1, 0xFFFF, sum = 0
8932 12:40:46.203081 2, 0xFFFF, sum = 0
8933 12:40:46.203168 3, 0xFFFF, sum = 0
8934 12:40:46.206214 4, 0xFFFF, sum = 0
8935 12:40:46.206291 5, 0xFFFF, sum = 0
8936 12:40:46.210048 6, 0xFFFF, sum = 0
8937 12:40:46.212920 7, 0xFFFF, sum = 0
8938 12:40:46.213007 8, 0xFFFF, sum = 0
8939 12:40:46.215990 9, 0xFFFF, sum = 0
8940 12:40:46.216075 10, 0xFFFF, sum = 0
8941 12:40:46.219445 11, 0xFFFF, sum = 0
8942 12:40:46.219532 12, 0xFFFF, sum = 0
8943 12:40:46.222915 13, 0x8FFF, sum = 0
8944 12:40:46.222994 14, 0x0, sum = 1
8945 12:40:46.225922 15, 0x0, sum = 2
8946 12:40:46.225999 16, 0x0, sum = 3
8947 12:40:46.229487 17, 0x0, sum = 4
8948 12:40:46.229576 best_step = 15
8949 12:40:46.229640
8950 12:40:46.229699 ==
8951 12:40:46.232537 Dram Type= 6, Freq= 0, CH_1, rank 1
8952 12:40:46.236109 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8953 12:40:46.239689 ==
8954 12:40:46.239770 RX Vref Scan: 0
8955 12:40:46.239850
8956 12:40:46.242392 RX Vref 0 -> 0, step: 1
8957 12:40:46.242466
8958 12:40:46.245934 RX Delay 11 -> 252, step: 4
8959 12:40:46.248983 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8960 12:40:46.252587 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
8961 12:40:46.256008 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8962 12:40:46.262702 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8963 12:40:46.265684 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8964 12:40:46.269347 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8965 12:40:46.272149 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
8966 12:40:46.275594 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
8967 12:40:46.282341 iDelay=195, Bit 8, Center 110 (55 ~ 166) 112
8968 12:40:46.285822 iDelay=195, Bit 9, Center 114 (63 ~ 166) 104
8969 12:40:46.288831 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8970 12:40:46.292512 iDelay=195, Bit 11, Center 118 (63 ~ 174) 112
8971 12:40:46.295519 iDelay=195, Bit 12, Center 134 (79 ~ 190) 112
8972 12:40:46.302270 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8973 12:40:46.305462 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
8974 12:40:46.308569 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8975 12:40:46.308651 ==
8976 12:40:46.312202 Dram Type= 6, Freq= 0, CH_1, rank 1
8977 12:40:46.315288 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8978 12:40:46.318494 ==
8979 12:40:46.318576 DQS Delay:
8980 12:40:46.318639 DQS0 = 0, DQS1 = 0
8981 12:40:46.321962 DQM Delay:
8982 12:40:46.322061 DQM0 = 130, DQM1 = 125
8983 12:40:46.325404 DQ Delay:
8984 12:40:46.328234 DQ0 =134, DQ1 =128, DQ2 =118, DQ3 =128
8985 12:40:46.331869 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =126
8986 12:40:46.334961 DQ8 =110, DQ9 =114, DQ10 =128, DQ11 =118
8987 12:40:46.338282 DQ12 =134, DQ13 =132, DQ14 =130, DQ15 =136
8988 12:40:46.338364
8989 12:40:46.338429
8990 12:40:46.338489
8991 12:40:46.341912 [DramC_TX_OE_Calibration] TA2
8992 12:40:46.345034 Original DQ_B0 (3 6) =30, OEN = 27
8993 12:40:46.348500 Original DQ_B1 (3 6) =30, OEN = 27
8994 12:40:46.351480 24, 0x0, End_B0=24 End_B1=24
8995 12:40:46.351595 25, 0x0, End_B0=25 End_B1=25
8996 12:40:46.354526 26, 0x0, End_B0=26 End_B1=26
8997 12:40:46.358210 27, 0x0, End_B0=27 End_B1=27
8998 12:40:46.361621 28, 0x0, End_B0=28 End_B1=28
8999 12:40:46.364873 29, 0x0, End_B0=29 End_B1=29
9000 12:40:46.364953 30, 0x0, End_B0=30 End_B1=30
9001 12:40:46.368174 31, 0x4141, End_B0=30 End_B1=30
9002 12:40:46.371292 Byte0 end_step=30 best_step=27
9003 12:40:46.374729 Byte1 end_step=30 best_step=27
9004 12:40:46.377667 Byte0 TX OE(2T, 0.5T) = (3, 3)
9005 12:40:46.381059 Byte1 TX OE(2T, 0.5T) = (3, 3)
9006 12:40:46.381145
9007 12:40:46.381211
9008 12:40:46.387471 [DQSOSCAuto] RK1, (LSB)MR18= 0xe1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
9009 12:40:46.390739 CH1 RK1: MR19=303, MR18=E1A
9010 12:40:46.397454 CH1_RK1: MR19=0x303, MR18=0xE1A, DQSOSC=396, MR23=63, INC=23, DEC=15
9011 12:40:46.401015 [RxdqsGatingPostProcess] freq 1600
9012 12:40:46.404021 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9013 12:40:46.407507 best DQS0 dly(2T, 0.5T) = (1, 1)
9014 12:40:46.410538 best DQS1 dly(2T, 0.5T) = (1, 1)
9015 12:40:46.414070 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9016 12:40:46.417061 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9017 12:40:46.420719 best DQS0 dly(2T, 0.5T) = (1, 1)
9018 12:40:46.423786 best DQS1 dly(2T, 0.5T) = (1, 1)
9019 12:40:46.427282 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9020 12:40:46.430727 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9021 12:40:46.433614 Pre-setting of DQS Precalculation
9022 12:40:46.437222 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9023 12:40:46.443823 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9024 12:40:46.453513 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9025 12:40:46.453601
9026 12:40:46.453669
9027 12:40:46.456630 [Calibration Summary] 3200 Mbps
9028 12:40:46.456712 CH 0, Rank 0
9029 12:40:46.460139 SW Impedance : PASS
9030 12:40:46.460221 DUTY Scan : NO K
9031 12:40:46.463136 ZQ Calibration : PASS
9032 12:40:46.466464 Jitter Meter : NO K
9033 12:40:46.466589 CBT Training : PASS
9034 12:40:46.469978 Write leveling : PASS
9035 12:40:46.473148 RX DQS gating : PASS
9036 12:40:46.473231 RX DQ/DQS(RDDQC) : PASS
9037 12:40:46.476758 TX DQ/DQS : PASS
9038 12:40:46.479832 RX DATLAT : PASS
9039 12:40:46.479915 RX DQ/DQS(Engine): PASS
9040 12:40:46.483307 TX OE : PASS
9041 12:40:46.483391 All Pass.
9042 12:40:46.483456
9043 12:40:46.486129 CH 0, Rank 1
9044 12:40:46.486238 SW Impedance : PASS
9045 12:40:46.489655 DUTY Scan : NO K
9046 12:40:46.489750 ZQ Calibration : PASS
9047 12:40:46.492991 Jitter Meter : NO K
9048 12:40:46.496543 CBT Training : PASS
9049 12:40:46.496626 Write leveling : PASS
9050 12:40:46.499721 RX DQS gating : PASS
9051 12:40:46.503493 RX DQ/DQS(RDDQC) : PASS
9052 12:40:46.503575 TX DQ/DQS : PASS
9053 12:40:46.506405 RX DATLAT : PASS
9054 12:40:46.509438 RX DQ/DQS(Engine): PASS
9055 12:40:46.509521 TX OE : PASS
9056 12:40:46.512863 All Pass.
9057 12:40:46.512938
9058 12:40:46.513015 CH 1, Rank 0
9059 12:40:46.516257 SW Impedance : PASS
9060 12:40:46.516337 DUTY Scan : NO K
9061 12:40:46.519369 ZQ Calibration : PASS
9062 12:40:46.522871 Jitter Meter : NO K
9063 12:40:46.522959 CBT Training : PASS
9064 12:40:46.525846 Write leveling : PASS
9065 12:40:46.529454 RX DQS gating : PASS
9066 12:40:46.529533 RX DQ/DQS(RDDQC) : PASS
9067 12:40:46.532438 TX DQ/DQS : PASS
9068 12:40:46.535958 RX DATLAT : PASS
9069 12:40:46.536043 RX DQ/DQS(Engine): PASS
9070 12:40:46.539032 TX OE : PASS
9071 12:40:46.539107 All Pass.
9072 12:40:46.539177
9073 12:40:46.542063 CH 1, Rank 1
9074 12:40:46.542145 SW Impedance : PASS
9075 12:40:46.545600 DUTY Scan : NO K
9076 12:40:46.548662 ZQ Calibration : PASS
9077 12:40:46.548748 Jitter Meter : NO K
9078 12:40:46.552269 CBT Training : PASS
9079 12:40:46.555628 Write leveling : PASS
9080 12:40:46.555709 RX DQS gating : PASS
9081 12:40:46.559223 RX DQ/DQS(RDDQC) : PASS
9082 12:40:46.561892 TX DQ/DQS : PASS
9083 12:40:46.562003 RX DATLAT : PASS
9084 12:40:46.565452 RX DQ/DQS(Engine): PASS
9085 12:40:46.565554 TX OE : PASS
9086 12:40:46.568432 All Pass.
9087 12:40:46.568507
9088 12:40:46.568570 DramC Write-DBI on
9089 12:40:46.571844 PER_BANK_REFRESH: Hybrid Mode
9090 12:40:46.575547 TX_TRACKING: ON
9091 12:40:46.581622 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9092 12:40:46.591446 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9093 12:40:46.598152 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9094 12:40:46.601585 [FAST_K] Save calibration result to emmc
9095 12:40:46.604839 sync common calibartion params.
9096 12:40:46.608302 sync cbt_mode0:1, 1:1
9097 12:40:46.608384 dram_init: ddr_geometry: 2
9098 12:40:46.611331 dram_init: ddr_geometry: 2
9099 12:40:46.614971 dram_init: ddr_geometry: 2
9100 12:40:46.615053 0:dram_rank_size:100000000
9101 12:40:46.617937 1:dram_rank_size:100000000
9102 12:40:46.624783 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9103 12:40:46.628170 DFS_SHUFFLE_HW_MODE: ON
9104 12:40:46.631149 dramc_set_vcore_voltage set vcore to 725000
9105 12:40:46.631233 Read voltage for 1600, 0
9106 12:40:46.634736 Vio18 = 0
9107 12:40:46.634820 Vcore = 725000
9108 12:40:46.634928 Vdram = 0
9109 12:40:46.637601 Vddq = 0
9110 12:40:46.637683 Vmddr = 0
9111 12:40:46.641138 switch to 3200 Mbps bootup
9112 12:40:46.641222 [DramcRunTimeConfig]
9113 12:40:46.641287 PHYPLL
9114 12:40:46.644231 DPM_CONTROL_AFTERK: ON
9115 12:40:46.647786 PER_BANK_REFRESH: ON
9116 12:40:46.647868 REFRESH_OVERHEAD_REDUCTION: ON
9117 12:40:46.651268 CMD_PICG_NEW_MODE: OFF
9118 12:40:46.654221 XRTWTW_NEW_MODE: ON
9119 12:40:46.654303 XRTRTR_NEW_MODE: ON
9120 12:40:46.657923 TX_TRACKING: ON
9121 12:40:46.658006 RDSEL_TRACKING: OFF
9122 12:40:46.661230 DQS Precalculation for DVFS: ON
9123 12:40:46.664045 RX_TRACKING: OFF
9124 12:40:46.664127 HW_GATING DBG: ON
9125 12:40:46.667529 ZQCS_ENABLE_LP4: ON
9126 12:40:46.667611 RX_PICG_NEW_MODE: ON
9127 12:40:46.670796 TX_PICG_NEW_MODE: ON
9128 12:40:46.670918 ENABLE_RX_DCM_DPHY: ON
9129 12:40:46.674352 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9130 12:40:46.677297 DUMMY_READ_FOR_TRACKING: OFF
9131 12:40:46.680957 !!! SPM_CONTROL_AFTERK: OFF
9132 12:40:46.684095 !!! SPM could not control APHY
9133 12:40:46.684178 IMPEDANCE_TRACKING: ON
9134 12:40:46.687035 TEMP_SENSOR: ON
9135 12:40:46.687139 HW_SAVE_FOR_SR: OFF
9136 12:40:46.690670 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9137 12:40:46.693688 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9138 12:40:46.697104 Read ODT Tracking: ON
9139 12:40:46.700560 Refresh Rate DeBounce: ON
9140 12:40:46.700678 DFS_NO_QUEUE_FLUSH: ON
9141 12:40:46.703967 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9142 12:40:46.707332 ENABLE_DFS_RUNTIME_MRW: OFF
9143 12:40:46.710137 DDR_RESERVE_NEW_MODE: ON
9144 12:40:46.710266 MR_CBT_SWITCH_FREQ: ON
9145 12:40:46.713520 =========================
9146 12:40:46.732820 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9147 12:40:46.735679 dram_init: ddr_geometry: 2
9148 12:40:46.754324 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9149 12:40:46.757394 dram_init: dram init end (result: 0)
9150 12:40:46.764105 DRAM-K: Full calibration passed in 24530 msecs
9151 12:40:46.767170 MRC: failed to locate region type 0.
9152 12:40:46.767268 DRAM rank0 size:0x100000000,
9153 12:40:46.770461 DRAM rank1 size=0x100000000
9154 12:40:46.780291 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9155 12:40:46.787087 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9156 12:40:46.793806 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9157 12:40:46.803660 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9158 12:40:46.803746 DRAM rank0 size:0x100000000,
9159 12:40:46.806626 DRAM rank1 size=0x100000000
9160 12:40:46.806710 CBMEM:
9161 12:40:46.809940 IMD: root @ 0xfffff000 254 entries.
9162 12:40:46.813288 IMD: root @ 0xffffec00 62 entries.
9163 12:40:46.816712 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9164 12:40:46.823683 WARNING: RO_VPD is uninitialized or empty.
9165 12:40:46.826633 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9166 12:40:46.837512 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9167 12:40:46.846736 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9168 12:40:46.858191 BS: romstage times (exec / console): total (unknown) / 24000 ms
9169 12:40:46.858279
9170 12:40:46.858364
9171 12:40:46.868473 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9172 12:40:46.871540 ARM64: Exception handlers installed.
9173 12:40:46.874446 ARM64: Testing exception
9174 12:40:46.877897 ARM64: Done test exception
9175 12:40:46.877982 Enumerating buses...
9176 12:40:46.881246 Show all devs... Before device enumeration.
9177 12:40:46.884786 Root Device: enabled 1
9178 12:40:46.887949 CPU_CLUSTER: 0: enabled 1
9179 12:40:46.888033 CPU: 00: enabled 1
9180 12:40:46.891066 Compare with tree...
9181 12:40:46.891166 Root Device: enabled 1
9182 12:40:46.894683 CPU_CLUSTER: 0: enabled 1
9183 12:40:46.897725 CPU: 00: enabled 1
9184 12:40:46.897839 Root Device scanning...
9185 12:40:46.901261 scan_static_bus for Root Device
9186 12:40:46.904312 CPU_CLUSTER: 0 enabled
9187 12:40:46.907810 scan_static_bus for Root Device done
9188 12:40:46.910754 scan_bus: bus Root Device finished in 8 msecs
9189 12:40:46.910899 done
9190 12:40:46.917624 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9191 12:40:46.920849 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9192 12:40:46.927494 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9193 12:40:46.930866 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9194 12:40:46.933967 Allocating resources...
9195 12:40:46.937328 Reading resources...
9196 12:40:46.940913 Root Device read_resources bus 0 link: 0
9197 12:40:46.943849 DRAM rank0 size:0x100000000,
9198 12:40:46.943951 DRAM rank1 size=0x100000000
9199 12:40:46.950752 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9200 12:40:46.950905 CPU: 00 missing read_resources
9201 12:40:46.957275 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9202 12:40:46.960214 Root Device read_resources bus 0 link: 0 done
9203 12:40:46.963828 Done reading resources.
9204 12:40:46.966955 Show resources in subtree (Root Device)...After reading.
9205 12:40:46.969940 Root Device child on link 0 CPU_CLUSTER: 0
9206 12:40:46.973506 CPU_CLUSTER: 0 child on link 0 CPU: 00
9207 12:40:46.983037 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9208 12:40:46.983174 CPU: 00
9209 12:40:46.989837 Root Device assign_resources, bus 0 link: 0
9210 12:40:46.993072 CPU_CLUSTER: 0 missing set_resources
9211 12:40:46.996478 Root Device assign_resources, bus 0 link: 0 done
9212 12:40:46.999756 Done setting resources.
9213 12:40:47.002795 Show resources in subtree (Root Device)...After assigning values.
9214 12:40:47.009543 Root Device child on link 0 CPU_CLUSTER: 0
9215 12:40:47.013104 CPU_CLUSTER: 0 child on link 0 CPU: 00
9216 12:40:47.019478 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9217 12:40:47.022778 CPU: 00
9218 12:40:47.022917 Done allocating resources.
9219 12:40:47.029170 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9220 12:40:47.032671 Enabling resources...
9221 12:40:47.032773 done.
9222 12:40:47.035736 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9223 12:40:47.038760 Initializing devices...
9224 12:40:47.038896 Root Device init
9225 12:40:47.042344 init hardware done!
9226 12:40:47.045911 0x00000018: ctrlr->caps
9227 12:40:47.046016 52.000 MHz: ctrlr->f_max
9228 12:40:47.048927 0.400 MHz: ctrlr->f_min
9229 12:40:47.052491 0x40ff8080: ctrlr->voltages
9230 12:40:47.052602 sclk: 390625
9231 12:40:47.052700 Bus Width = 1
9232 12:40:47.055424 sclk: 390625
9233 12:40:47.055529 Bus Width = 1
9234 12:40:47.058764 Early init status = 3
9235 12:40:47.061745 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9236 12:40:47.066578 in-header: 03 fc 00 00 01 00 00 00
9237 12:40:47.070213 in-data: 00
9238 12:40:47.073288 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9239 12:40:47.078703 in-header: 03 fd 00 00 00 00 00 00
9240 12:40:47.082228 in-data:
9241 12:40:47.085828 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9242 12:40:47.089693 in-header: 03 fc 00 00 01 00 00 00
9243 12:40:47.093491 in-data: 00
9244 12:40:47.096448 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9245 12:40:47.102504 in-header: 03 fd 00 00 00 00 00 00
9246 12:40:47.105392 in-data:
9247 12:40:47.108696 [SSUSB] Setting up USB HOST controller...
9248 12:40:47.111740 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9249 12:40:47.115416 [SSUSB] phy power-on done.
9250 12:40:47.118564 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9251 12:40:47.125390 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9252 12:40:47.128570 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9253 12:40:47.135385 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9254 12:40:47.141960 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9255 12:40:47.148421 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9256 12:40:47.155103 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9257 12:40:47.161527 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9258 12:40:47.164872 SPM: binary array size = 0x9dc
9259 12:40:47.168469 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9260 12:40:47.174512 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9261 12:40:47.181184 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9262 12:40:47.187752 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9263 12:40:47.191213 configure_display: Starting display init
9264 12:40:47.225507 anx7625_power_on_init: Init interface.
9265 12:40:47.228993 anx7625_disable_pd_protocol: Disabled PD feature.
9266 12:40:47.231683 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9267 12:40:47.260125 anx7625_start_dp_work: Secure OCM version=00
9268 12:40:47.263129 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9269 12:40:47.277722 sp_tx_get_edid_block: EDID Block = 1
9270 12:40:47.380697 Extracted contents:
9271 12:40:47.383529 header: 00 ff ff ff ff ff ff 00
9272 12:40:47.387227 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9273 12:40:47.390136 version: 01 04
9274 12:40:47.393962 basic params: 95 1f 11 78 0a
9275 12:40:47.396912 chroma info: 76 90 94 55 54 90 27 21 50 54
9276 12:40:47.400449 established: 00 00 00
9277 12:40:47.406963 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9278 12:40:47.413607 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9279 12:40:47.416567 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9280 12:40:47.423377 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9281 12:40:47.429697 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9282 12:40:47.433250 extensions: 00
9283 12:40:47.433334 checksum: fb
9284 12:40:47.433400
9285 12:40:47.439365 Manufacturer: IVO Model 57d Serial Number 0
9286 12:40:47.439448 Made week 0 of 2020
9287 12:40:47.443010 EDID version: 1.4
9288 12:40:47.443092 Digital display
9289 12:40:47.446006 6 bits per primary color channel
9290 12:40:47.449548 DisplayPort interface
9291 12:40:47.449630 Maximum image size: 31 cm x 17 cm
9292 12:40:47.453030 Gamma: 220%
9293 12:40:47.453113 Check DPMS levels
9294 12:40:47.459335 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9295 12:40:47.462707 First detailed timing is preferred timing
9296 12:40:47.466295 Established timings supported:
9297 12:40:47.466376 Standard timings supported:
9298 12:40:47.469231 Detailed timings
9299 12:40:47.472653 Hex of detail: 383680a07038204018303c0035ae10000019
9300 12:40:47.479229 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9301 12:40:47.482195 0780 0798 07c8 0820 hborder 0
9302 12:40:47.485722 0438 043b 0447 0458 vborder 0
9303 12:40:47.489332 -hsync -vsync
9304 12:40:47.489412 Did detailed timing
9305 12:40:47.495830 Hex of detail: 000000000000000000000000000000000000
9306 12:40:47.498818 Manufacturer-specified data, tag 0
9307 12:40:47.501969 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9308 12:40:47.505403 ASCII string: InfoVision
9309 12:40:47.508853 Hex of detail: 000000fe00523134304e574635205248200a
9310 12:40:47.511925 ASCII string: R140NWF5 RH
9311 12:40:47.512006 Checksum
9312 12:40:47.515602 Checksum: 0xfb (valid)
9313 12:40:47.518411 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9314 12:40:47.522048 DSI data_rate: 832800000 bps
9315 12:40:47.528722 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9316 12:40:47.531474 anx7625_parse_edid: pixelclock(138800).
9317 12:40:47.535195 hactive(1920), hsync(48), hfp(24), hbp(88)
9318 12:40:47.538296 vactive(1080), vsync(12), vfp(3), vbp(17)
9319 12:40:47.542003 anx7625_dsi_config: config dsi.
9320 12:40:47.548555 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9321 12:40:47.562467 anx7625_dsi_config: success to config DSI
9322 12:40:47.565771 anx7625_dp_start: MIPI phy setup OK.
9323 12:40:47.569104 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9324 12:40:47.572505 mtk_ddp_mode_set invalid vrefresh 60
9325 12:40:47.575866 main_disp_path_setup
9326 12:40:47.575948 ovl_layer_smi_id_en
9327 12:40:47.578800 ovl_layer_smi_id_en
9328 12:40:47.578915 ccorr_config
9329 12:40:47.578980 aal_config
9330 12:40:47.582433 gamma_config
9331 12:40:47.582514 postmask_config
9332 12:40:47.585248 dither_config
9333 12:40:47.588842 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9334 12:40:47.595522 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9335 12:40:47.598450 Root Device init finished in 555 msecs
9336 12:40:47.602022 CPU_CLUSTER: 0 init
9337 12:40:47.608619 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9338 12:40:47.615053 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9339 12:40:47.615135 APU_MBOX 0x190000b0 = 0x10001
9340 12:40:47.618605 APU_MBOX 0x190001b0 = 0x10001
9341 12:40:47.621664 APU_MBOX 0x190005b0 = 0x10001
9342 12:40:47.624666 APU_MBOX 0x190006b0 = 0x10001
9343 12:40:47.631421 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9344 12:40:47.641399 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9345 12:40:47.654196 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9346 12:40:47.660654 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9347 12:40:47.672219 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9348 12:40:47.681247 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9349 12:40:47.684470 CPU_CLUSTER: 0 init finished in 81 msecs
9350 12:40:47.687875 Devices initialized
9351 12:40:47.691481 Show all devs... After init.
9352 12:40:47.691563 Root Device: enabled 1
9353 12:40:47.694328 CPU_CLUSTER: 0: enabled 1
9354 12:40:47.698027 CPU: 00: enabled 1
9355 12:40:47.700933 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9356 12:40:47.704446 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9357 12:40:47.707476 ELOG: NV offset 0x57f000 size 0x1000
9358 12:40:47.714133 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9359 12:40:47.721233 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9360 12:40:47.724357 ELOG: Event(17) added with size 13 at 2023-06-14 12:40:48 UTC
9361 12:40:47.730956 out: cmd=0x121: 03 db 21 01 00 00 00 00
9362 12:40:47.734075 in-header: 03 86 00 00 2c 00 00 00
9363 12:40:47.743884 in-data: d9 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9364 12:40:47.750702 ELOG: Event(A1) added with size 10 at 2023-06-14 12:40:48 UTC
9365 12:40:47.757265 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9366 12:40:47.763711 ELOG: Event(A0) added with size 9 at 2023-06-14 12:40:48 UTC
9367 12:40:47.766633 elog_add_boot_reason: Logged dev mode boot
9368 12:40:47.773280 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9369 12:40:47.773362 Finalize devices...
9370 12:40:47.776664 Devices finalized
9371 12:40:47.780221 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9372 12:40:47.783106 Writing coreboot table at 0xffe64000
9373 12:40:47.786594 0. 000000000010a000-0000000000113fff: RAMSTAGE
9374 12:40:47.793252 1. 0000000040000000-00000000400fffff: RAM
9375 12:40:47.796520 2. 0000000040100000-000000004032afff: RAMSTAGE
9376 12:40:47.800027 3. 000000004032b000-00000000545fffff: RAM
9377 12:40:47.803390 4. 0000000054600000-000000005465ffff: BL31
9378 12:40:47.806312 5. 0000000054660000-00000000ffe63fff: RAM
9379 12:40:47.812804 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9380 12:40:47.816406 7. 0000000100000000-000000023fffffff: RAM
9381 12:40:47.819909 Passing 5 GPIOs to payload:
9382 12:40:47.822791 NAME | PORT | POLARITY | VALUE
9383 12:40:47.829396 EC in RW | 0x000000aa | low | undefined
9384 12:40:47.832899 EC interrupt | 0x00000005 | low | undefined
9385 12:40:47.839617 TPM interrupt | 0x000000ab | high | undefined
9386 12:40:47.842561 SD card detect | 0x00000011 | high | undefined
9387 12:40:47.846157 speaker enable | 0x00000093 | high | undefined
9388 12:40:47.849172 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9389 12:40:47.852819 in-header: 03 f9 00 00 02 00 00 00
9390 12:40:47.855655 in-data: 02 00
9391 12:40:47.859346 ADC[4]: Raw value=894821 ID=7
9392 12:40:47.862413 ADC[3]: Raw value=212700 ID=1
9393 12:40:47.862485 RAM Code: 0x71
9394 12:40:47.865966 ADC[6]: Raw value=74722 ID=0
9395 12:40:47.868975 ADC[5]: Raw value=212330 ID=1
9396 12:40:47.869048 SKU Code: 0x1
9397 12:40:47.875697 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7dbf
9398 12:40:47.875810 coreboot table: 964 bytes.
9399 12:40:47.879138 IMD ROOT 0. 0xfffff000 0x00001000
9400 12:40:47.882175 IMD SMALL 1. 0xffffe000 0x00001000
9401 12:40:47.885379 RO MCACHE 2. 0xffffc000 0x00001104
9402 12:40:47.888865 CONSOLE 3. 0xfff7c000 0x00080000
9403 12:40:47.892210 FMAP 4. 0xfff7b000 0x00000452
9404 12:40:47.895594 TIME STAMP 5. 0xfff7a000 0x00000910
9405 12:40:47.899055 VBOOT WORK 6. 0xfff66000 0x00014000
9406 12:40:47.902129 RAMOOPS 7. 0xffe66000 0x00100000
9407 12:40:47.905442 COREBOOT 8. 0xffe64000 0x00002000
9408 12:40:47.908450 IMD small region:
9409 12:40:47.912048 IMD ROOT 0. 0xffffec00 0x00000400
9410 12:40:47.915110 VPD 1. 0xffffeba0 0x0000004c
9411 12:40:47.918654 MMC STATUS 2. 0xffffeb80 0x00000004
9412 12:40:47.925468 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9413 12:40:47.925557 Probing TPM: done!
9414 12:40:47.932178 Connected to device vid:did:rid of 1ae0:0028:00
9415 12:40:47.938592 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9416 12:40:47.942061 Initialized TPM device CR50 revision 0
9417 12:40:47.945115 Checking cr50 for pending updates
9418 12:40:47.951094 Reading cr50 TPM mode
9419 12:40:47.959348 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9420 12:40:47.966250 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9421 12:40:48.006267 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9422 12:40:48.009374 Checking segment from ROM address 0x40100000
9423 12:40:48.012846 Checking segment from ROM address 0x4010001c
9424 12:40:48.019384 Loading segment from ROM address 0x40100000
9425 12:40:48.019469 code (compression=0)
9426 12:40:48.029155 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9427 12:40:48.035760 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9428 12:40:48.035843 it's not compressed!
9429 12:40:48.042303 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9430 12:40:48.049028 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9431 12:40:48.066494 Loading segment from ROM address 0x4010001c
9432 12:40:48.066578 Entry Point 0x80000000
9433 12:40:48.069863 Loaded segments
9434 12:40:48.072806 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9435 12:40:48.079458 Jumping to boot code at 0x80000000(0xffe64000)
9436 12:40:48.086225 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9437 12:40:48.093076 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9438 12:40:48.100813 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9439 12:40:48.104281 Checking segment from ROM address 0x40100000
9440 12:40:48.107217 Checking segment from ROM address 0x4010001c
9441 12:40:48.114062 Loading segment from ROM address 0x40100000
9442 12:40:48.114147 code (compression=1)
9443 12:40:48.120841 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9444 12:40:48.130428 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9445 12:40:48.130518 using LZMA
9446 12:40:48.139181 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9447 12:40:48.146247 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9448 12:40:48.149220 Loading segment from ROM address 0x4010001c
9449 12:40:48.149295 Entry Point 0x54601000
9450 12:40:48.152885 Loaded segments
9451 12:40:48.155947 NOTICE: MT8192 bl31_setup
9452 12:40:48.162614 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9453 12:40:48.166186 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9454 12:40:48.169725 WARNING: region 0:
9455 12:40:48.172602 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9456 12:40:48.172687 WARNING: region 1:
9457 12:40:48.179254 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9458 12:40:48.182963 WARNING: region 2:
9459 12:40:48.186012 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9460 12:40:48.189526 WARNING: region 3:
9461 12:40:48.192980 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9462 12:40:48.195896 WARNING: region 4:
9463 12:40:48.202624 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9464 12:40:48.202706 WARNING: region 5:
9465 12:40:48.205757 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9466 12:40:48.209252 WARNING: region 6:
9467 12:40:48.212568 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9468 12:40:48.216004 WARNING: region 7:
9469 12:40:48.219270 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9470 12:40:48.226056 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9471 12:40:48.229529 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9472 12:40:48.232603 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9473 12:40:48.239013 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9474 12:40:48.242383 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9475 12:40:48.249186 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9476 12:40:48.252678 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9477 12:40:48.256109 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9478 12:40:48.262693 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9479 12:40:48.265660 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9480 12:40:48.268701 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9481 12:40:48.275317 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9482 12:40:48.278788 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9483 12:40:48.285518 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9484 12:40:48.289116 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9485 12:40:48.292119 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9486 12:40:48.298786 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9487 12:40:48.302231 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9488 12:40:48.308952 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9489 12:40:48.311907 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9490 12:40:48.315509 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9491 12:40:48.321767 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9492 12:40:48.325257 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9493 12:40:48.328780 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9494 12:40:48.334917 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9495 12:40:48.338661 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9496 12:40:48.345141 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9497 12:40:48.348535 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9498 12:40:48.354816 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9499 12:40:48.358197 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9500 12:40:48.361703 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9501 12:40:48.368239 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9502 12:40:48.371879 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9503 12:40:48.374825 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9504 12:40:48.378444 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9505 12:40:48.385137 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9506 12:40:48.388053 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9507 12:40:48.391430 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9508 12:40:48.394705 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9509 12:40:48.401760 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9510 12:40:48.404785 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9511 12:40:48.408451 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9512 12:40:48.411485 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9513 12:40:48.418092 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9514 12:40:48.421661 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9515 12:40:48.424609 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9516 12:40:48.427993 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9517 12:40:48.434685 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9518 12:40:48.438065 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9519 12:40:48.444697 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9520 12:40:48.448283 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9521 12:40:48.451178 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9522 12:40:48.458331 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9523 12:40:48.461231 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9524 12:40:48.467758 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9525 12:40:48.471383 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9526 12:40:48.477935 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9527 12:40:48.481682 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9528 12:40:48.484660 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9529 12:40:48.491238 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9530 12:40:48.494744 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9531 12:40:48.501101 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9532 12:40:48.504603 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9533 12:40:48.511272 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9534 12:40:48.514286 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9535 12:40:48.520888 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9536 12:40:48.524530 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9537 12:40:48.527473 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9538 12:40:48.534506 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9539 12:40:48.537450 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9540 12:40:48.544435 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9541 12:40:48.547804 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9542 12:40:48.554255 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9543 12:40:48.557475 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9544 12:40:48.560987 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9545 12:40:48.567592 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9546 12:40:48.571047 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9547 12:40:48.577194 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9548 12:40:48.580812 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9549 12:40:48.587551 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9550 12:40:48.590974 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9551 12:40:48.597286 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9552 12:40:48.600713 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9553 12:40:48.607243 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9554 12:40:48.610348 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9555 12:40:48.613701 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9556 12:40:48.620734 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9557 12:40:48.623740 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9558 12:40:48.630486 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9559 12:40:48.633476 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9560 12:40:48.640461 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9561 12:40:48.643644 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9562 12:40:48.646988 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9563 12:40:48.653302 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9564 12:40:48.656908 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9565 12:40:48.663298 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9566 12:40:48.666806 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9567 12:40:48.670409 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9568 12:40:48.676909 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9569 12:40:48.680379 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9570 12:40:48.683252 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9571 12:40:48.686815 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9572 12:40:48.693054 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9573 12:40:48.696676 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9574 12:40:48.703113 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9575 12:40:48.706612 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9576 12:40:48.713292 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9577 12:40:48.716343 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9578 12:40:48.719578 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9579 12:40:48.726490 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9580 12:40:48.729501 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9581 12:40:48.736212 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9582 12:40:48.739840 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9583 12:40:48.742673 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9584 12:40:48.749448 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9585 12:40:48.752773 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9586 12:40:48.756316 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9587 12:40:48.762917 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9588 12:40:48.765869 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9589 12:40:48.769346 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9590 12:40:48.775914 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9591 12:40:48.779527 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9592 12:40:48.782591 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9593 12:40:48.785834 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9594 12:40:48.792576 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9595 12:40:48.795641 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9596 12:40:48.802710 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9597 12:40:48.805644 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9598 12:40:48.809112 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9599 12:40:48.815831 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9600 12:40:48.819326 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9601 12:40:48.822276 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9602 12:40:48.828799 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9603 12:40:48.832125 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9604 12:40:48.838728 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9605 12:40:48.842438 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9606 12:40:48.845453 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9607 12:40:48.852471 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9608 12:40:48.855840 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9609 12:40:48.862110 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9610 12:40:48.865904 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9611 12:40:48.869188 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9612 12:40:48.875605 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9613 12:40:48.878638 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9614 12:40:48.885351 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9615 12:40:48.888930 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9616 12:40:48.891858 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9617 12:40:48.898613 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9618 12:40:48.901813 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9619 12:40:48.908529 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9620 12:40:48.911964 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9621 12:40:48.915492 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9622 12:40:48.921594 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9623 12:40:48.925231 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9624 12:40:48.931949 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9625 12:40:48.935221 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9626 12:40:48.938216 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9627 12:40:48.944801 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9628 12:40:48.948478 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9629 12:40:48.955107 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9630 12:40:48.958009 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9631 12:40:48.961280 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9632 12:40:48.968277 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9633 12:40:48.971306 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9634 12:40:48.977906 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9635 12:40:48.981296 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9636 12:40:48.984679 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9637 12:40:48.991307 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9638 12:40:48.994238 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9639 12:40:49.001337 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9640 12:40:49.004375 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9641 12:40:49.007722 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9642 12:40:49.014144 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9643 12:40:49.017703 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9644 12:40:49.024271 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9645 12:40:49.027265 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9646 12:40:49.030350 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9647 12:40:49.037493 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9648 12:40:49.040433 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9649 12:40:49.047014 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9650 12:40:49.050543 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9651 12:40:49.053617 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9652 12:40:49.060408 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9653 12:40:49.063427 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9654 12:40:49.070017 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9655 12:40:49.073253 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9656 12:40:49.076599 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9657 12:40:49.083275 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9658 12:40:49.086739 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9659 12:40:49.093552 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9660 12:40:49.096568 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9661 12:40:49.103202 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9662 12:40:49.106082 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9663 12:40:49.109396 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9664 12:40:49.116212 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9665 12:40:49.119646 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9666 12:40:49.126090 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9667 12:40:49.129157 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9668 12:40:49.135759 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9669 12:40:49.139681 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9670 12:40:49.142574 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9671 12:40:49.149224 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9672 12:40:49.152394 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9673 12:40:49.158750 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9674 12:40:49.162527 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9675 12:40:49.168648 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9676 12:40:49.172513 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9677 12:40:49.175698 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9678 12:40:49.182054 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9679 12:40:49.185353 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9680 12:40:49.192189 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9681 12:40:49.194972 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9682 12:40:49.202135 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9683 12:40:49.205187 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9684 12:40:49.208307 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9685 12:40:49.215139 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9686 12:40:49.218055 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9687 12:40:49.224847 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9688 12:40:49.228235 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9689 12:40:49.231814 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9690 12:40:49.238369 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9691 12:40:49.241500 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9692 12:40:49.248102 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9693 12:40:49.251248 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9694 12:40:49.258202 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9695 12:40:49.261207 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9696 12:40:49.264486 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9697 12:40:49.271088 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9698 12:40:49.274716 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9699 12:40:49.277678 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9700 12:40:49.284145 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9701 12:40:49.287648 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9702 12:40:49.291136 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9703 12:40:49.294376 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9704 12:40:49.300770 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9705 12:40:49.304074 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9706 12:40:49.310577 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9707 12:40:49.314122 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9708 12:40:49.317095 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9709 12:40:49.323524 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9710 12:40:49.326992 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9711 12:40:49.333577 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9712 12:40:49.337198 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9713 12:40:49.340189 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9714 12:40:49.346766 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9715 12:40:49.350525 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9716 12:40:49.353544 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9717 12:40:49.360140 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9718 12:40:49.363657 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9719 12:40:49.366515 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9720 12:40:49.373367 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9721 12:40:49.376964 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9722 12:40:49.383408 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9723 12:40:49.386432 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9724 12:40:49.390225 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9725 12:40:49.396673 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9726 12:40:49.399493 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9727 12:40:49.402789 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9728 12:40:49.409835 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9729 12:40:49.413164 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9730 12:40:49.419657 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9731 12:40:49.423120 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9732 12:40:49.426136 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9733 12:40:49.432692 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9734 12:40:49.436228 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9735 12:40:49.439247 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9736 12:40:49.445866 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9737 12:40:49.449580 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9738 12:40:49.452691 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9739 12:40:49.459224 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9740 12:40:49.462419 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9741 12:40:49.465830 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9742 12:40:49.468864 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9743 12:40:49.472555 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9744 12:40:49.478739 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9745 12:40:49.482649 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9746 12:40:49.485601 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9747 12:40:49.491870 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9748 12:40:49.495428 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9749 12:40:49.499084 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9750 12:40:49.504990 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9751 12:40:49.508749 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9752 12:40:49.511988 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9753 12:40:49.518398 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9754 12:40:49.521598 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9755 12:40:49.528496 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9756 12:40:49.531664 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9757 12:40:49.534678 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9758 12:40:49.541801 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9759 12:40:49.544878 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9760 12:40:49.551592 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9761 12:40:49.554680 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9762 12:40:49.558282 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9763 12:40:49.564512 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9764 12:40:49.567561 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9765 12:40:49.574633 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9766 12:40:49.577614 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9767 12:40:49.584546 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9768 12:40:49.587736 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9769 12:40:49.590718 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9770 12:40:49.597606 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9771 12:40:49.600761 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9772 12:40:49.607295 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9773 12:40:49.610500 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9774 12:40:49.617304 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9775 12:40:49.620808 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9776 12:40:49.623414 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9777 12:40:49.630294 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9778 12:40:49.633786 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9779 12:40:49.640121 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9780 12:40:49.643482 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9781 12:40:49.650182 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9782 12:40:49.653199 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9783 12:40:49.657015 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9784 12:40:49.663600 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9785 12:40:49.666648 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9786 12:40:49.673541 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9787 12:40:49.676443 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9788 12:40:49.680003 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9789 12:40:49.686656 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9790 12:40:49.689708 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9791 12:40:49.696112 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9792 12:40:49.699584 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9793 12:40:49.702620 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9794 12:40:49.709237 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9795 12:40:49.712801 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9796 12:40:49.719513 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9797 12:40:49.722455 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9798 12:40:49.728898 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9799 12:40:49.732178 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9800 12:40:49.735503 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9801 12:40:49.742395 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9802 12:40:49.745999 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9803 12:40:49.752069 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9804 12:40:49.755502 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9805 12:40:49.762216 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9806 12:40:49.765164 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9807 12:40:49.768771 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9808 12:40:49.775337 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9809 12:40:49.778280 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9810 12:40:49.784790 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9811 12:40:49.788479 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9812 12:40:49.795107 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9813 12:40:49.797976 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9814 12:40:49.801347 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9815 12:40:49.808255 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9816 12:40:49.811340 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9817 12:40:49.818103 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9818 12:40:49.821093 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9819 12:40:49.824766 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9820 12:40:49.831524 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9821 12:40:49.834499 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9822 12:40:49.841085 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9823 12:40:49.844168 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9824 12:40:49.850423 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9825 12:40:49.853934 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9826 12:40:49.857716 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9827 12:40:49.863709 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9828 12:40:49.867262 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9829 12:40:49.874010 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9830 12:40:49.877126 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9831 12:40:49.883542 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9832 12:40:49.886992 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9833 12:40:49.893686 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9834 12:40:49.897309 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9835 12:40:49.900963 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9836 12:40:49.907169 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9837 12:40:49.910595 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9838 12:40:49.917115 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9839 12:40:49.920054 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9840 12:40:49.926782 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9841 12:40:49.929854 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9842 12:40:49.936456 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9843 12:40:49.940088 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9844 12:40:49.943592 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9845 12:40:49.950175 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9846 12:40:49.953034 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9847 12:40:49.959780 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9848 12:40:49.963216 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9849 12:40:49.969527 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9850 12:40:49.972819 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9851 12:40:49.979671 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9852 12:40:49.982641 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9853 12:40:49.986358 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9854 12:40:49.992337 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9855 12:40:49.996029 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9856 12:40:50.002738 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9857 12:40:50.005742 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9858 12:40:50.012283 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9859 12:40:50.015786 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9860 12:40:50.022218 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9861 12:40:50.025252 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9862 12:40:50.032151 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9863 12:40:50.035709 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9864 12:40:50.038748 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9865 12:40:50.044939 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9866 12:40:50.048413 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9867 12:40:50.054796 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9868 12:40:50.058470 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9869 12:40:50.064789 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9870 12:40:50.068109 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9871 12:40:50.071542 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9872 12:40:50.077964 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9873 12:40:50.081457 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9874 12:40:50.087794 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9875 12:40:50.091395 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9876 12:40:50.098132 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9877 12:40:50.101203 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9878 12:40:50.107743 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9879 12:40:50.111414 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9880 12:40:50.117848 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9881 12:40:50.121216 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9882 12:40:50.127431 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9883 12:40:50.131071 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9884 12:40:50.137095 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9885 12:40:50.140659 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9886 12:40:50.147254 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9887 12:40:50.150270 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9888 12:40:50.156955 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9889 12:40:50.160628 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9890 12:40:50.167132 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9891 12:40:50.170101 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9892 12:40:50.176990 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9893 12:40:50.180340 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9894 12:40:50.186405 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9895 12:40:50.189844 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9896 12:40:50.196769 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9897 12:40:50.199555 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9898 12:40:50.205972 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9899 12:40:50.209551 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9900 12:40:50.216276 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9901 12:40:50.219444 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9902 12:40:50.226044 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9903 12:40:50.229632 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9904 12:40:50.236231 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9905 12:40:50.236341 INFO: [APUAPC] vio 0
9906 12:40:50.242703 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9907 12:40:50.246201 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9908 12:40:50.249271 INFO: [APUAPC] D0_APC_0: 0x400510
9909 12:40:50.252783 INFO: [APUAPC] D0_APC_1: 0x0
9910 12:40:50.255645 INFO: [APUAPC] D0_APC_2: 0x1540
9911 12:40:50.259261 INFO: [APUAPC] D0_APC_3: 0x0
9912 12:40:50.262374 INFO: [APUAPC] D1_APC_0: 0xffffffff
9913 12:40:50.265880 INFO: [APUAPC] D1_APC_1: 0xffffffff
9914 12:40:50.268895 INFO: [APUAPC] D1_APC_2: 0x3fffff
9915 12:40:50.272498 INFO: [APUAPC] D1_APC_3: 0x0
9916 12:40:50.275516 INFO: [APUAPC] D2_APC_0: 0xffffffff
9917 12:40:50.279111 INFO: [APUAPC] D2_APC_1: 0xffffffff
9918 12:40:50.281927 INFO: [APUAPC] D2_APC_2: 0x3fffff
9919 12:40:50.285378 INFO: [APUAPC] D2_APC_3: 0x0
9920 12:40:50.288736 INFO: [APUAPC] D3_APC_0: 0xffffffff
9921 12:40:50.292258 INFO: [APUAPC] D3_APC_1: 0xffffffff
9922 12:40:50.295634 INFO: [APUAPC] D3_APC_2: 0x3fffff
9923 12:40:50.298632 INFO: [APUAPC] D3_APC_3: 0x0
9924 12:40:50.301979 INFO: [APUAPC] D4_APC_0: 0xffffffff
9925 12:40:50.305575 INFO: [APUAPC] D4_APC_1: 0xffffffff
9926 12:40:50.308344 INFO: [APUAPC] D4_APC_2: 0x3fffff
9927 12:40:50.311841 INFO: [APUAPC] D4_APC_3: 0x0
9928 12:40:50.315429 INFO: [APUAPC] D5_APC_0: 0xffffffff
9929 12:40:50.318611 INFO: [APUAPC] D5_APC_1: 0xffffffff
9930 12:40:50.321954 INFO: [APUAPC] D5_APC_2: 0x3fffff
9931 12:40:50.325012 INFO: [APUAPC] D5_APC_3: 0x0
9932 12:40:50.328685 INFO: [APUAPC] D6_APC_0: 0xffffffff
9933 12:40:50.331761 INFO: [APUAPC] D6_APC_1: 0xffffffff
9934 12:40:50.335171 INFO: [APUAPC] D6_APC_2: 0x3fffff
9935 12:40:50.335283 INFO: [APUAPC] D6_APC_3: 0x0
9936 12:40:50.341313 INFO: [APUAPC] D7_APC_0: 0xffffffff
9937 12:40:50.345055 INFO: [APUAPC] D7_APC_1: 0xffffffff
9938 12:40:50.348035 INFO: [APUAPC] D7_APC_2: 0x3fffff
9939 12:40:50.348197 INFO: [APUAPC] D7_APC_3: 0x0
9940 12:40:50.351763 INFO: [APUAPC] D8_APC_0: 0xffffffff
9941 12:40:50.358351 INFO: [APUAPC] D8_APC_1: 0xffffffff
9942 12:40:50.361301 INFO: [APUAPC] D8_APC_2: 0x3fffff
9943 12:40:50.361384 INFO: [APUAPC] D8_APC_3: 0x0
9944 12:40:50.364943 INFO: [APUAPC] D9_APC_0: 0xffffffff
9945 12:40:50.368003 INFO: [APUAPC] D9_APC_1: 0xffffffff
9946 12:40:50.371100 INFO: [APUAPC] D9_APC_2: 0x3fffff
9947 12:40:50.374748 INFO: [APUAPC] D9_APC_3: 0x0
9948 12:40:50.377780 INFO: [APUAPC] D10_APC_0: 0xffffffff
9949 12:40:50.380874 INFO: [APUAPC] D10_APC_1: 0xffffffff
9950 12:40:50.384598 INFO: [APUAPC] D10_APC_2: 0x3fffff
9951 12:40:50.387517 INFO: [APUAPC] D10_APC_3: 0x0
9952 12:40:50.390716 INFO: [APUAPC] D11_APC_0: 0xffffffff
9953 12:40:50.394461 INFO: [APUAPC] D11_APC_1: 0xffffffff
9954 12:40:50.400754 INFO: [APUAPC] D11_APC_2: 0x3fffff
9955 12:40:50.400837 INFO: [APUAPC] D11_APC_3: 0x0
9956 12:40:50.404078 INFO: [APUAPC] D12_APC_0: 0xffffffff
9957 12:40:50.411247 INFO: [APUAPC] D12_APC_1: 0xffffffff
9958 12:40:50.414023 INFO: [APUAPC] D12_APC_2: 0x3fffff
9959 12:40:50.414109 INFO: [APUAPC] D12_APC_3: 0x0
9960 12:40:50.420801 INFO: [APUAPC] D13_APC_0: 0xffffffff
9961 12:40:50.424048 INFO: [APUAPC] D13_APC_1: 0xffffffff
9962 12:40:50.427118 INFO: [APUAPC] D13_APC_2: 0x3fffff
9963 12:40:50.430803 INFO: [APUAPC] D13_APC_3: 0x0
9964 12:40:50.433799 INFO: [APUAPC] D14_APC_0: 0xffffffff
9965 12:40:50.437464 INFO: [APUAPC] D14_APC_1: 0xffffffff
9966 12:40:50.440876 INFO: [APUAPC] D14_APC_2: 0x3fffff
9967 12:40:50.443913 INFO: [APUAPC] D14_APC_3: 0x0
9968 12:40:50.447309 INFO: [APUAPC] D15_APC_0: 0xffffffff
9969 12:40:50.450647 INFO: [APUAPC] D15_APC_1: 0xffffffff
9970 12:40:50.453897 INFO: [APUAPC] D15_APC_2: 0x3fffff
9971 12:40:50.456991 INFO: [APUAPC] D15_APC_3: 0x0
9972 12:40:50.457073 INFO: [APUAPC] APC_CON: 0x4
9973 12:40:50.460672 INFO: [NOCDAPC] D0_APC_0: 0x0
9974 12:40:50.463977 INFO: [NOCDAPC] D0_APC_1: 0x0
9975 12:40:50.466677 INFO: [NOCDAPC] D1_APC_0: 0x0
9976 12:40:50.470298 INFO: [NOCDAPC] D1_APC_1: 0xfff
9977 12:40:50.473288 INFO: [NOCDAPC] D2_APC_0: 0x0
9978 12:40:50.476893 INFO: [NOCDAPC] D2_APC_1: 0xfff
9979 12:40:50.480527 INFO: [NOCDAPC] D3_APC_0: 0x0
9980 12:40:50.483584 INFO: [NOCDAPC] D3_APC_1: 0xfff
9981 12:40:50.486669 INFO: [NOCDAPC] D4_APC_0: 0x0
9982 12:40:50.489732 INFO: [NOCDAPC] D4_APC_1: 0xfff
9983 12:40:50.489836 INFO: [NOCDAPC] D5_APC_0: 0x0
9984 12:40:50.493462 INFO: [NOCDAPC] D5_APC_1: 0xfff
9985 12:40:50.496412 INFO: [NOCDAPC] D6_APC_0: 0x0
9986 12:40:50.499638 INFO: [NOCDAPC] D6_APC_1: 0xfff
9987 12:40:50.503046 INFO: [NOCDAPC] D7_APC_0: 0x0
9988 12:40:50.506438 INFO: [NOCDAPC] D7_APC_1: 0xfff
9989 12:40:50.509808 INFO: [NOCDAPC] D8_APC_0: 0x0
9990 12:40:50.512751 INFO: [NOCDAPC] D8_APC_1: 0xfff
9991 12:40:50.516230 INFO: [NOCDAPC] D9_APC_0: 0x0
9992 12:40:50.519810 INFO: [NOCDAPC] D9_APC_1: 0xfff
9993 12:40:50.522716 INFO: [NOCDAPC] D10_APC_0: 0x0
9994 12:40:50.526116 INFO: [NOCDAPC] D10_APC_1: 0xfff
9995 12:40:50.530002 INFO: [NOCDAPC] D11_APC_0: 0x0
9996 12:40:50.530078 INFO: [NOCDAPC] D11_APC_1: 0xfff
9997 12:40:50.532684 INFO: [NOCDAPC] D12_APC_0: 0x0
9998 12:40:50.536234 INFO: [NOCDAPC] D12_APC_1: 0xfff
9999 12:40:50.539316 INFO: [NOCDAPC] D13_APC_0: 0x0
10000 12:40:50.542763 INFO: [NOCDAPC] D13_APC_1: 0xfff
10001 12:40:50.545750 INFO: [NOCDAPC] D14_APC_0: 0x0
10002 12:40:50.549424 INFO: [NOCDAPC] D14_APC_1: 0xfff
10003 12:40:50.552285 INFO: [NOCDAPC] D15_APC_0: 0x0
10004 12:40:50.555902 INFO: [NOCDAPC] D15_APC_1: 0xfff
10005 12:40:50.559238 INFO: [NOCDAPC] APC_CON: 0x4
10006 12:40:50.562270 INFO: [APUAPC] set_apusys_apc done
10007 12:40:50.565423 INFO: [DEVAPC] devapc_init done
10008 12:40:50.568999 INFO: GICv3 without legacy support detected.
10009 12:40:50.572496 INFO: ARM GICv3 driver initialized in EL3
10010 12:40:50.575529 INFO: Maximum SPI INTID supported: 639
10011 12:40:50.582189 INFO: BL31: Initializing runtime services
10012 12:40:50.585289 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10013 12:40:50.588998 INFO: SPM: enable CPC mode
10014 12:40:50.595207 INFO: mcdi ready for mcusys-off-idle and system suspend
10015 12:40:50.598771 INFO: BL31: Preparing for EL3 exit to normal world
10016 12:40:50.601678 INFO: Entry point address = 0x80000000
10017 12:40:50.605210 INFO: SPSR = 0x8
10018 12:40:50.610778
10019 12:40:50.610910
10020 12:40:50.610978
10021 12:40:50.614253 Starting depthcharge on Spherion...
10022 12:40:50.614336
10023 12:40:50.614403 Wipe memory regions:
10024 12:40:50.614481
10025 12:40:50.615134 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10026 12:40:50.615234 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10027 12:40:50.615315 Setting prompt string to ['asurada:']
10028 12:40:50.615391 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10029 12:40:50.617082 [0x00000040000000, 0x00000054600000)
10030 12:40:50.739806
10031 12:40:50.739938 [0x00000054660000, 0x00000080000000)
10032 12:40:51.000223
10033 12:40:51.000364 [0x000000821a7280, 0x000000ffe64000)
10034 12:40:51.745281
10035 12:40:51.745421 [0x00000100000000, 0x00000240000000)
10036 12:40:53.636094
10037 12:40:53.638821 Initializing XHCI USB controller at 0x11200000.
10038 12:40:54.677754
10039 12:40:54.681295 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10040 12:40:54.681387
10041 12:40:54.681454
10042 12:40:54.681515
10043 12:40:54.681790 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10045 12:40:54.782139 asurada: tftpboot 192.168.201.1 10724838/tftp-deploy-mckrragc/kernel/image.itb 10724838/tftp-deploy-mckrragc/kernel/cmdline
10046 12:40:54.782269 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10047 12:40:54.782376 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10048 12:40:54.786367 tftpboot 192.168.201.1 10724838/tftp-deploy-mckrragc/kernel/image.ittp-deploy-mckrragc/kernel/cmdline
10049 12:40:54.786453
10050 12:40:54.786519 Waiting for link
10051 12:40:54.946744
10052 12:40:54.946921 R8152: Initializing
10053 12:40:54.946990
10054 12:40:54.950315 Version 6 (ocp_data = 5c30)
10055 12:40:54.950398
10056 12:40:54.953755 R8152: Done initializing
10057 12:40:54.953838
10058 12:40:54.953903 Adding net device
10059 12:40:56.810147
10060 12:40:56.810280 done.
10061 12:40:56.810350
10062 12:40:56.810413 MAC: 00:24:32:30:78:ff
10063 12:40:56.810474
10064 12:40:56.813012 Sending DHCP discover... done.
10065 12:40:56.813097
10066 12:40:56.816448 Waiting for reply... done.
10067 12:40:56.816535
10068 12:40:56.819709 Sending DHCP request... done.
10069 12:40:56.819807
10070 12:40:56.834630 Waiting for reply... done.
10071 12:40:56.834716
10072 12:40:56.834782 My ip is 192.168.201.21
10073 12:40:56.834873
10074 12:40:56.837498 The DHCP server ip is 192.168.201.1
10075 12:40:56.837581
10076 12:40:56.844500 TFTP server IP predefined by user: 192.168.201.1
10077 12:40:56.844590
10078 12:40:56.851040 Bootfile predefined by user: 10724838/tftp-deploy-mckrragc/kernel/image.itb
10079 12:40:56.851124
10080 12:40:56.854111 Sending tftp read request... done.
10081 12:40:56.854193
10082 12:40:56.858162 Waiting for the transfer...
10083 12:40:56.858243
10084 12:40:57.412456 00000000 ################################################################
10085 12:40:57.412594
10086 12:40:57.982984 00080000 ################################################################
10087 12:40:57.983117
10088 12:40:58.550575 00100000 ################################################################
10089 12:40:58.550718
10090 12:40:59.112361 00180000 ################################################################
10091 12:40:59.112509
10092 12:40:59.687803 00200000 ################################################################
10093 12:40:59.687949
10094 12:41:00.260301 00280000 ################################################################
10095 12:41:00.260440
10096 12:41:00.818596 00300000 ################################################################
10097 12:41:00.818736
10098 12:41:01.376822 00380000 ################################################################
10099 12:41:01.376968
10100 12:41:01.916748 00400000 ################################################################
10101 12:41:01.916906
10102 12:41:02.473355 00480000 ################################################################
10103 12:41:02.473533
10104 12:41:03.035244 00500000 ################################################################
10105 12:41:03.035376
10106 12:41:03.600050 00580000 ################################################################
10107 12:41:03.600191
10108 12:41:04.165493 00600000 ################################################################
10109 12:41:04.165637
10110 12:41:04.706220 00680000 ################################################################
10111 12:41:04.706367
10112 12:41:05.270073 00700000 ################################################################
10113 12:41:05.270213
10114 12:41:05.828915 00780000 ################################################################
10115 12:41:05.829063
10116 12:41:06.391082 00800000 ################################################################
10117 12:41:06.391232
10118 12:41:06.962402 00880000 ################################################################
10119 12:41:06.962569
10120 12:41:07.518337 00900000 ################################################################
10121 12:41:07.518482
10122 12:41:08.088548 00980000 ################################################################
10123 12:41:08.088692
10124 12:41:08.652985 00a00000 ################################################################
10125 12:41:08.653133
10126 12:41:09.210033 00a80000 ################################################################
10127 12:41:09.210215
10128 12:41:09.763179 00b00000 ################################################################
10129 12:41:09.763337
10130 12:41:10.331995 00b80000 ################################################################
10131 12:41:10.332144
10132 12:41:10.889483 00c00000 ################################################################
10133 12:41:10.889629
10134 12:41:11.436768 00c80000 ################################################################
10135 12:41:11.436982
10136 12:41:11.995622 00d00000 ################################################################
10137 12:41:11.995782
10138 12:41:12.552752 00d80000 ################################################################
10139 12:41:12.552912
10140 12:41:13.106810 00e00000 ################################################################
10141 12:41:13.106973
10142 12:41:13.639207 00e80000 ################################################################
10143 12:41:13.639347
10144 12:41:14.183953 00f00000 ################################################################
10145 12:41:14.184116
10146 12:41:14.711748 00f80000 ################################################################
10147 12:41:14.711939
10148 12:41:15.238105 01000000 ################################################################
10149 12:41:15.238305
10150 12:41:15.774421 01080000 ################################################################
10151 12:41:15.774620
10152 12:41:16.302510 01100000 ################################################################
10153 12:41:16.302729
10154 12:41:16.828749 01180000 ################################################################
10155 12:41:16.828959
10156 12:41:17.357259 01200000 ################################################################
10157 12:41:17.357450
10158 12:41:17.884556 01280000 ################################################################
10159 12:41:17.884710
10160 12:41:18.406151 01300000 ################################################################
10161 12:41:18.406300
10162 12:41:18.943517 01380000 ################################################################
10163 12:41:18.943665
10164 12:41:19.471302 01400000 ################################################################
10165 12:41:19.471449
10166 12:41:20.000951 01480000 ################################################################
10167 12:41:20.001118
10168 12:41:20.532237 01500000 ################################################################
10169 12:41:20.532392
10170 12:41:21.064319 01580000 ################################################################
10171 12:41:21.064463
10172 12:41:21.589745 01600000 ################################################################
10173 12:41:21.589891
10174 12:41:22.118169 01680000 ################################################################
10175 12:41:22.118314
10176 12:41:22.661528 01700000 ################################################################
10177 12:41:22.661687
10178 12:41:23.179465 01780000 ################################################################
10179 12:41:23.179623
10180 12:41:23.722169 01800000 ################################################################
10181 12:41:23.722360
10182 12:41:24.256187 01880000 ################################################################
10183 12:41:24.256372
10184 12:41:24.795527 01900000 ################################################################
10185 12:41:24.795671
10186 12:41:25.348433 01980000 ################################################################
10187 12:41:25.348616
10188 12:41:25.874536 01a00000 ################################################################
10189 12:41:25.874717
10190 12:41:26.419853 01a80000 ################################################################
10191 12:41:26.420043
10192 12:41:26.956072 01b00000 ################################################################
10193 12:41:26.956228
10194 12:41:27.493746 01b80000 ################################################################
10195 12:41:27.493937
10196 12:41:28.034126 01c00000 ################################################################
10197 12:41:28.034300
10198 12:41:28.620805 01c80000 ################################################################
10199 12:41:28.620954
10200 12:41:29.196090 01d00000 ################################################################
10201 12:41:29.196229
10202 12:41:29.774303 01d80000 ################################################################
10203 12:41:29.774440
10204 12:41:30.342637 01e00000 ################################################################
10205 12:41:30.342805
10206 12:41:30.842409 01e80000 ################################################################
10207 12:41:30.842574
10208 12:41:31.386970 01f00000 ################################################################
10209 12:41:31.387115
10210 12:41:32.047843 01f80000 ################################################################
10211 12:41:32.048523
10212 12:41:32.676013 02000000 ################################################################
10213 12:41:32.676147
10214 12:41:33.255196 02080000 ################################################################
10215 12:41:33.255338
10216 12:41:33.818467 02100000 ################################################################
10217 12:41:33.818603
10218 12:41:34.371592 02180000 ################################################################
10219 12:41:34.371757
10220 12:41:34.934331 02200000 ################################################################
10221 12:41:34.934490
10222 12:41:35.485503 02280000 ################################################################
10223 12:41:35.485666
10224 12:41:36.032631 02300000 ################################################################
10225 12:41:36.032776
10226 12:41:36.569654 02380000 ################################################################
10227 12:41:36.569797
10228 12:41:37.107675 02400000 ################################################################
10229 12:41:37.107812
10230 12:41:37.636583 02480000 ################################################################
10231 12:41:37.636750
10232 12:41:38.156246 02500000 ################################################################
10233 12:41:38.156388
10234 12:41:38.675344 02580000 ################################################################
10235 12:41:38.675479
10236 12:41:39.220964 02600000 ################################################################
10237 12:41:39.221098
10238 12:41:39.742675 02680000 ################################################################
10239 12:41:39.742843
10240 12:41:40.282290 02700000 ################################################################
10241 12:41:40.282434
10242 12:41:40.831871 02780000 ################################################################
10243 12:41:40.832006
10244 12:41:41.386236 02800000 ################################################################
10245 12:41:41.386370
10246 12:41:41.935503 02880000 ################################################################
10247 12:41:41.935636
10248 12:41:42.490229 02900000 ################################################################
10249 12:41:42.490366
10250 12:41:43.043267 02980000 ################################################################
10251 12:41:43.043405
10252 12:41:43.584591 02a00000 ################################################################
10253 12:41:43.584731
10254 12:41:44.129060 02a80000 ################################################################
10255 12:41:44.129195
10256 12:41:44.667742 02b00000 ################################################################
10257 12:41:44.667899
10258 12:41:45.197027 02b80000 ################################################################
10259 12:41:45.197158
10260 12:41:45.729723 02c00000 ################################################################
10261 12:41:45.729858
10262 12:41:46.260450 02c80000 ################################################################
10263 12:41:46.260595
10264 12:41:46.791103 02d00000 ################################################################
10265 12:41:46.791237
10266 12:41:47.331316 02d80000 ################################################################
10267 12:41:47.331453
10268 12:41:47.861377 02e00000 ################################################################
10269 12:41:47.861541
10270 12:41:48.391900 02e80000 ################################################################
10271 12:41:48.392040
10272 12:41:48.916870 02f00000 ################################################################
10273 12:41:48.917029
10274 12:41:49.437724 02f80000 ################################################################
10275 12:41:49.437864
10276 12:41:49.966151 03000000 ################################################################
10277 12:41:49.966296
10278 12:41:50.491818 03080000 ################################################################
10279 12:41:50.491967
10280 12:41:51.023755 03100000 ################################################################
10281 12:41:51.023895
10282 12:41:51.543121 03180000 ################################################################
10283 12:41:51.543255
10284 12:41:52.060035 03200000 ################################################################
10285 12:41:52.060170
10286 12:41:52.586232 03280000 ################################################################
10287 12:41:52.586392
10288 12:41:53.118701 03300000 ################################################################
10289 12:41:53.118895
10290 12:41:53.647542 03380000 ################################################################
10291 12:41:53.647685
10292 12:41:54.174407 03400000 ################################################################
10293 12:41:54.174574
10294 12:41:54.694635 03480000 ################################################################
10295 12:41:54.694796
10296 12:41:55.248072 03500000 ################################################################
10297 12:41:55.248206
10298 12:41:55.823707 03580000 ################################################################
10299 12:41:55.823845
10300 12:41:56.431462 03600000 ################################################################
10301 12:41:56.432044
10302 12:41:57.087829 03680000 ################################################################
10303 12:41:57.088459
10304 12:41:57.711141 03700000 ################################################################
10305 12:41:57.711302
10306 12:41:58.239735 03780000 ################################################################
10307 12:41:58.239874
10308 12:41:59.579783 03800000 ################################################################
10309 12:41:59.580923
10310 12:41:59.581876 03880000 ################################################################
10311 12:41:59.582573
10312 12:42:00.023279 03900000 ################################################################
10313 12:42:00.023415
10314 12:42:00.599887 03980000 ################################################################
10315 12:42:00.600115
10316 12:42:01.162549 03a00000 ################################################################
10317 12:42:01.162714
10318 12:42:01.726745 03a80000 ################################################################
10319 12:42:01.726944
10320 12:42:02.250627 03b00000 ################################################################
10321 12:42:02.250763
10322 12:42:02.780135 03b80000 ################################################################
10323 12:42:02.780289
10324 12:42:03.310691 03c00000 ################################################################
10325 12:42:03.310893
10326 12:42:03.848802 03c80000 ################################################################
10327 12:42:03.848934
10328 12:42:04.376416 03d00000 ################################################################
10329 12:42:04.376554
10330 12:42:04.901562 03d80000 ################################################################
10331 12:42:04.901727
10332 12:42:05.419978 03e00000 ################################################################
10333 12:42:05.420162
10334 12:42:05.951034 03e80000 ################################################################
10335 12:42:05.951170
10336 12:42:06.465716 03f00000 ################################################################
10337 12:42:06.465883
10338 12:42:06.733947 03f80000 ################################# done.
10339 12:42:06.734119
10340 12:42:06.737472 The bootfile was 66853770 bytes long.
10341 12:42:06.737578
10342 12:42:06.740359 Sending tftp read request... done.
10343 12:42:06.740464
10344 12:42:06.740555 Waiting for the transfer...
10345 12:42:06.740650
10346 12:42:06.743803 00000000 # done.
10347 12:42:06.743911
10348 12:42:06.750550 Command line loaded dynamically from TFTP file: 10724838/tftp-deploy-mckrragc/kernel/cmdline
10349 12:42:06.750671
10350 12:42:06.763981 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10351 12:42:06.764068
10352 12:42:06.764153 Loading FIT.
10353 12:42:06.764243
10354 12:42:06.767198 Image ramdisk-1 has 56362433 bytes.
10355 12:42:06.767273
10356 12:42:06.770328 Image fdt-1 has 46924 bytes.
10357 12:42:06.770428
10358 12:42:06.773430 Image kernel-1 has 10442380 bytes.
10359 12:42:06.773530
10360 12:42:06.783645 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10361 12:42:06.783724
10362 12:42:06.800176 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10363 12:42:06.800356
10364 12:42:06.803661 Choosing best match conf-1 for compat google,spherion-rev2.
10365 12:42:06.808702
10366 12:42:06.813154 Connected to device vid:did:rid of 1ae0:0028:00
10367 12:42:06.820379
10368 12:42:06.823587 tpm_get_response: command 0x17b, return code 0x0
10369 12:42:06.823720
10370 12:42:06.830098 ec_init: CrosEC protocol v3 supported (256, 248)
10371 12:42:06.830175
10372 12:42:06.833839 tpm_cleanup: add release locality here.
10373 12:42:06.833948
10374 12:42:06.836814 Shutting down all USB controllers.
10375 12:42:06.836889
10376 12:42:06.840403 Removing current net device
10377 12:42:06.840558
10378 12:42:06.846479 Exiting depthcharge with code 4 at timestamp: 105500102
10379 12:42:06.846580
10380 12:42:06.849995 LZMA decompressing kernel-1 to 0x821a6718
10381 12:42:06.850100
10382 12:42:06.852908 LZMA decompressing kernel-1 to 0x40000000
10383 12:42:08.163751
10384 12:42:08.163885 jumping to kernel
10385 12:42:08.164320 end: 2.2.4 bootloader-commands (duration 00:01:18) [common]
10386 12:42:08.164435 start: 2.2.5 auto-login-action (timeout 00:03:08) [common]
10387 12:42:08.164545 Setting prompt string to ['Linux version [0-9]']
10388 12:42:08.164619 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10389 12:42:08.164688 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10390 12:42:08.245104
10391 12:42:08.248517 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10392 12:42:08.252324 start: 2.2.5.1 login-action (timeout 00:03:08) [common]
10393 12:42:08.252414 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10394 12:42:08.252501 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10395 12:42:08.252579 Using line separator: #'\n'#
10396 12:42:08.252640 No login prompt set.
10397 12:42:08.252703 Parsing kernel messages
10398 12:42:08.252759 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10399 12:42:08.252862 [login-action] Waiting for messages, (timeout 00:03:08)
10400 12:42:08.271824 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j35827-arm64-gcc-10-defconfig-arm64-chromebook-fwl9s) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jun 14 12:30:40 UTC 2023
10401 12:42:08.274872 [ 0.000000] random: crng init done
10402 12:42:08.278196 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10403 12:42:08.281203 [ 0.000000] efi: UEFI not found.
10404 12:42:08.291446 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10405 12:42:08.298515 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10406 12:42:08.307784 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10407 12:42:08.317755 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10408 12:42:08.324381 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10409 12:42:08.331482 [ 0.000000] printk: bootconsole [mtk8250] enabled
10410 12:42:08.337834 [ 0.000000] NUMA: No NUMA configuration found
10411 12:42:08.344515 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10412 12:42:08.347643 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10413 12:42:08.351174 [ 0.000000] Zone ranges:
10414 12:42:08.357303 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10415 12:42:08.360832 [ 0.000000] DMA32 empty
10416 12:42:08.367527 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10417 12:42:08.370700 [ 0.000000] Movable zone start for each node
10418 12:42:08.373872 [ 0.000000] Early memory node ranges
10419 12:42:08.380216 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10420 12:42:08.387018 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10421 12:42:08.393812 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10422 12:42:08.400171 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10423 12:42:08.403328 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10424 12:42:08.413314 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10425 12:42:08.468795 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10426 12:42:08.475816 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10427 12:42:08.482275 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10428 12:42:08.485605 [ 0.000000] psci: probing for conduit method from DT.
10429 12:42:08.492440 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10430 12:42:08.495626 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10431 12:42:08.502140 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10432 12:42:08.505381 [ 0.000000] psci: SMC Calling Convention v1.2
10433 12:42:08.511794 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10434 12:42:08.515084 [ 0.000000] Detected VIPT I-cache on CPU0
10435 12:42:08.521862 [ 0.000000] CPU features: detected: GIC system register CPU interface
10436 12:42:08.528247 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10437 12:42:08.534709 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10438 12:42:08.541367 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10439 12:42:08.551480 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10440 12:42:08.557598 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10441 12:42:08.561246 [ 0.000000] alternatives: applying boot alternatives
10442 12:42:08.567751 [ 0.000000] Fallback order for Node 0: 0
10443 12:42:08.574754 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10444 12:42:08.577819 [ 0.000000] Policy zone: Normal
10445 12:42:08.590731 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10446 12:42:08.600780 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10447 12:42:08.611026 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10448 12:42:08.620772 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10449 12:42:08.627711 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10450 12:42:08.630880 <6>[ 0.000000] software IO TLB: area num 8.
10451 12:42:08.687517 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10452 12:42:08.836762 <6>[ 0.000000] Memory: 7916116K/8385536K available (17984K kernel code, 4098K rwdata, 15868K rodata, 8384K init, 615K bss, 436652K reserved, 32768K cma-reserved)
10453 12:42:08.843334 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10454 12:42:08.849762 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10455 12:42:08.852988 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10456 12:42:08.859766 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10457 12:42:08.866085 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10458 12:42:08.869244 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10459 12:42:08.879273 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10460 12:42:08.885943 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10461 12:42:08.892592 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10462 12:42:08.899137 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10463 12:42:08.902138 <6>[ 0.000000] GICv3: 608 SPIs implemented
10464 12:42:08.905734 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10465 12:42:08.911819 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10466 12:42:08.915666 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10467 12:42:08.921950 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10468 12:42:08.935397 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10469 12:42:08.948473 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10470 12:42:08.954744 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10471 12:42:08.963164 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10472 12:42:08.976452 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10473 12:42:08.982500 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10474 12:42:08.989419 <6>[ 0.009180] Console: colour dummy device 80x25
10475 12:42:08.999479 <6>[ 0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10476 12:42:09.006215 <6>[ 0.024350] pid_max: default: 32768 minimum: 301
10477 12:42:09.009312 <6>[ 0.029223] LSM: Security Framework initializing
10478 12:42:09.015902 <6>[ 0.034162] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10479 12:42:09.026087 <6>[ 0.041976] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10480 12:42:09.035826 <6>[ 0.051450] cblist_init_generic: Setting adjustable number of callback queues.
10481 12:42:09.038976 <6>[ 0.058947] cblist_init_generic: Setting shift to 3 and lim to 1.
10482 12:42:09.045633 <6>[ 0.065287] cblist_init_generic: Setting shift to 3 and lim to 1.
10483 12:42:09.051948 <6>[ 0.071692] rcu: Hierarchical SRCU implementation.
10484 12:42:09.058768 <6>[ 0.076737] rcu: Max phase no-delay instances is 1000.
10485 12:42:09.065172 <6>[ 0.083758] EFI services will not be available.
10486 12:42:09.068356 <6>[ 0.088731] smp: Bringing up secondary CPUs ...
10487 12:42:09.076318 <6>[ 0.093810] Detected VIPT I-cache on CPU1
10488 12:42:09.083353 <6>[ 0.093881] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10489 12:42:09.089436 <6>[ 0.093912] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10490 12:42:09.092699 <6>[ 0.094249] Detected VIPT I-cache on CPU2
10491 12:42:09.103076 <6>[ 0.094298] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10492 12:42:09.109503 <6>[ 0.094313] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10493 12:42:09.112553 <6>[ 0.094573] Detected VIPT I-cache on CPU3
10494 12:42:09.119350 <6>[ 0.094620] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10495 12:42:09.126106 <6>[ 0.094635] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10496 12:42:09.132463 <6>[ 0.094938] CPU features: detected: Spectre-v4
10497 12:42:09.135766 <6>[ 0.094945] CPU features: detected: Spectre-BHB
10498 12:42:09.138983 <6>[ 0.094951] Detected PIPT I-cache on CPU4
10499 12:42:09.145698 <6>[ 0.095009] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10500 12:42:09.155176 <6>[ 0.095025] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10501 12:42:09.158428 <6>[ 0.095318] Detected PIPT I-cache on CPU5
10502 12:42:09.165527 <6>[ 0.095381] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10503 12:42:09.171983 <6>[ 0.095398] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10504 12:42:09.175178 <6>[ 0.095678] Detected PIPT I-cache on CPU6
10505 12:42:09.185304 <6>[ 0.095743] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10506 12:42:09.192118 <6>[ 0.095759] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10507 12:42:09.195194 <6>[ 0.096058] Detected PIPT I-cache on CPU7
10508 12:42:09.201621 <6>[ 0.096123] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10509 12:42:09.208419 <6>[ 0.096139] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10510 12:42:09.211510 <6>[ 0.096188] smp: Brought up 1 node, 8 CPUs
10511 12:42:09.218356 <6>[ 0.237509] SMP: Total of 8 processors activated.
10512 12:42:09.224997 <6>[ 0.242461] CPU features: detected: 32-bit EL0 Support
10513 12:42:09.230977 <6>[ 0.247824] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10514 12:42:09.238185 <6>[ 0.256624] CPU features: detected: Common not Private translations
10515 12:42:09.244443 <6>[ 0.263140] CPU features: detected: CRC32 instructions
10516 12:42:09.250740 <6>[ 0.268491] CPU features: detected: RCpc load-acquire (LDAPR)
10517 12:42:09.254549 <6>[ 0.274451] CPU features: detected: LSE atomic instructions
10518 12:42:09.260923 <6>[ 0.280232] CPU features: detected: Privileged Access Never
10519 12:42:09.267410 <6>[ 0.286048] CPU features: detected: RAS Extension Support
10520 12:42:09.274085 <6>[ 0.291657] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10521 12:42:09.277264 <6>[ 0.298876] CPU: All CPU(s) started at EL2
10522 12:42:09.284139 <6>[ 0.303219] alternatives: applying system-wide alternatives
10523 12:42:09.294230 <6>[ 0.313923] devtmpfs: initialized
10524 12:42:09.309803 <6>[ 0.322692] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10525 12:42:09.316159 <6>[ 0.332653] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10526 12:42:09.322942 <6>[ 0.340888] pinctrl core: initialized pinctrl subsystem
10527 12:42:09.325976 <6>[ 0.347554] DMI not present or invalid.
10528 12:42:09.332792 <6>[ 0.351961] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10529 12:42:09.342297 <6>[ 0.358833] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10530 12:42:09.349415 <6>[ 0.366411] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10531 12:42:09.359070 <6>[ 0.374639] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10532 12:42:09.362187 <6>[ 0.382880] audit: initializing netlink subsys (disabled)
10533 12:42:09.372511 <5>[ 0.388576] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10534 12:42:09.378965 <6>[ 0.389276] thermal_sys: Registered thermal governor 'step_wise'
10535 12:42:09.385448 <6>[ 0.396539] thermal_sys: Registered thermal governor 'power_allocator'
10536 12:42:09.388746 <6>[ 0.402795] cpuidle: using governor menu
10537 12:42:09.395506 <6>[ 0.413751] NET: Registered PF_QIPCRTR protocol family
10538 12:42:09.401789 <6>[ 0.419227] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10539 12:42:09.408290 <6>[ 0.426330] ASID allocator initialised with 32768 entries
10540 12:42:09.411430 <6>[ 0.432896] Serial: AMBA PL011 UART driver
10541 12:42:09.421791 <4>[ 0.441549] Trying to register duplicate clock ID: 134
10542 12:42:09.475972 <6>[ 0.498813] KASLR enabled
10543 12:42:09.490127 <6>[ 0.506455] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10544 12:42:09.496457 <6>[ 0.513466] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10545 12:42:09.503233 <6>[ 0.519956] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10546 12:42:09.510230 <6>[ 0.526960] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10547 12:42:09.516516 <6>[ 0.533446] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10548 12:42:09.522938 <6>[ 0.540451] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10549 12:42:09.529511 <6>[ 0.546942] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10550 12:42:09.536086 <6>[ 0.553946] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10551 12:42:09.539183 <6>[ 0.561406] ACPI: Interpreter disabled.
10552 12:42:09.548196 <6>[ 0.567817] iommu: Default domain type: Translated
10553 12:42:09.555123 <6>[ 0.572928] iommu: DMA domain TLB invalidation policy: strict mode
10554 12:42:09.558294 <5>[ 0.579580] SCSI subsystem initialized
10555 12:42:09.564537 <6>[ 0.583817] usbcore: registered new interface driver usbfs
10556 12:42:09.571344 <6>[ 0.589545] usbcore: registered new interface driver hub
10557 12:42:09.574545 <6>[ 0.595096] usbcore: registered new device driver usb
10558 12:42:09.581509 <6>[ 0.601196] pps_core: LinuxPPS API ver. 1 registered
10559 12:42:09.591343 <6>[ 0.606391] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10560 12:42:09.594483 <6>[ 0.615734] PTP clock support registered
10561 12:42:09.597729 <6>[ 0.619974] EDAC MC: Ver: 3.0.0
10562 12:42:09.605201 <6>[ 0.625149] FPGA manager framework
10563 12:42:09.608676 <6>[ 0.628827] Advanced Linux Sound Architecture Driver Initialized.
10564 12:42:09.612283 <6>[ 0.635590] vgaarb: loaded
10565 12:42:09.619500 <6>[ 0.638751] clocksource: Switched to clocksource arch_sys_counter
10566 12:42:09.625906 <5>[ 0.645196] VFS: Disk quotas dquot_6.6.0
10567 12:42:09.632378 <6>[ 0.649380] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10568 12:42:09.635251 <6>[ 0.656568] pnp: PnP ACPI: disabled
10569 12:42:09.643836 <6>[ 0.663349] NET: Registered PF_INET protocol family
10570 12:42:09.653556 <6>[ 0.668953] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10571 12:42:09.665080 <6>[ 0.681255] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10572 12:42:09.674408 <6>[ 0.690068] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10573 12:42:09.681311 <6>[ 0.698039] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10574 12:42:09.691087 <6>[ 0.706696] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10575 12:42:09.697433 <6>[ 0.716438] TCP: Hash tables configured (established 65536 bind 65536)
10576 12:42:09.704326 <6>[ 0.723239] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10577 12:42:09.714193 <6>[ 0.730433] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10578 12:42:09.720499 <6>[ 0.738135] NET: Registered PF_UNIX/PF_LOCAL protocol family
10579 12:42:09.726820 <6>[ 0.744212] RPC: Registered named UNIX socket transport module.
10580 12:42:09.730164 <6>[ 0.750360] RPC: Registered udp transport module.
10581 12:42:09.737204 <6>[ 0.755292] RPC: Registered tcp transport module.
10582 12:42:09.743803 <6>[ 0.760223] RPC: Registered tcp NFSv4.1 backchannel transport module.
10583 12:42:09.746716 <6>[ 0.766890] PCI: CLS 0 bytes, default 64
10584 12:42:09.750355 <6>[ 0.771236] Unpacking initramfs...
10585 12:42:09.766776 <6>[ 0.783269] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10586 12:42:09.776679 <6>[ 0.791942] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10587 12:42:09.779739 <6>[ 0.800779] kvm [1]: IPA Size Limit: 40 bits
10588 12:42:09.786580 <6>[ 0.805303] kvm [1]: GICv3: no GICV resource entry
10589 12:42:09.789830 <6>[ 0.810323] kvm [1]: disabling GICv2 emulation
10590 12:42:09.796359 <6>[ 0.815008] kvm [1]: GIC system register CPU interface enabled
10591 12:42:09.799630 <6>[ 0.821175] kvm [1]: vgic interrupt IRQ18
10592 12:42:09.805984 <6>[ 0.825542] kvm [1]: VHE mode initialized successfully
10593 12:42:09.813068 <5>[ 0.831908] Initialise system trusted keyrings
10594 12:42:09.819343 <6>[ 0.836709] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10595 12:42:09.827042 <6>[ 0.846673] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10596 12:42:09.833280 <5>[ 0.853074] NFS: Registering the id_resolver key type
10597 12:42:09.836638 <5>[ 0.858377] Key type id_resolver registered
10598 12:42:09.843664 <5>[ 0.862793] Key type id_legacy registered
10599 12:42:09.849900 <6>[ 0.867072] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10600 12:42:09.856796 <6>[ 0.873995] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10601 12:42:09.862822 <6>[ 0.881715] 9p: Installing v9fs 9p2000 file system support
10602 12:42:09.899463 <5>[ 0.919251] Key type asymmetric registered
10603 12:42:09.902658 <5>[ 0.923588] Asymmetric key parser 'x509' registered
10604 12:42:09.912374 <6>[ 0.928734] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10605 12:42:09.916144 <6>[ 0.936346] io scheduler mq-deadline registered
10606 12:42:09.919321 <6>[ 0.941106] io scheduler kyber registered
10607 12:42:09.938166 <6>[ 0.957862] EINJ: ACPI disabled.
10608 12:42:09.970223 <4>[ 0.983345] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10609 12:42:09.979791 <4>[ 0.993985] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10610 12:42:09.994926 <6>[ 1.014524] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10611 12:42:10.002963 <6>[ 1.022558] printk: console [ttyS0] disabled
10612 12:42:10.030474 <6>[ 1.047206] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10613 12:42:10.037322 <6>[ 1.056697] printk: console [ttyS0] enabled
10614 12:42:10.040483 <6>[ 1.056697] printk: console [ttyS0] enabled
10615 12:42:10.047386 <6>[ 1.065614] printk: bootconsole [mtk8250] disabled
10616 12:42:10.050717 <6>[ 1.065614] printk: bootconsole [mtk8250] disabled
10617 12:42:10.057174 <6>[ 1.076880] SuperH (H)SCI(F) driver initialized
10618 12:42:10.060269 <6>[ 1.082162] msm_serial: driver initialized
10619 12:42:10.074651 <6>[ 1.091137] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10620 12:42:10.084837 <6>[ 1.099681] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10621 12:42:10.091482 <6>[ 1.108223] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10622 12:42:10.101224 <6>[ 1.116852] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10623 12:42:10.111391 <6>[ 1.125557] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10624 12:42:10.117865 <6>[ 1.134270] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10625 12:42:10.127345 <6>[ 1.142811] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10626 12:42:10.134490 <6>[ 1.151614] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10627 12:42:10.143980 <6>[ 1.160156] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10628 12:42:10.155826 <6>[ 1.175795] loop: module loaded
10629 12:42:10.162715 <6>[ 1.181784] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10630 12:42:10.185539 <4>[ 1.205280] mtk-pmic-keys: Failed to locate of_node [id: -1]
10631 12:42:10.192175 <6>[ 1.212066] megasas: 07.719.03.00-rc1
10632 12:42:10.202047 <6>[ 1.221969] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10633 12:42:10.214162 <6>[ 1.234155] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10634 12:42:10.230349 <6>[ 1.250040] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10635 12:42:10.288212 <6>[ 1.301743] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10636 12:42:12.150048 <6>[ 3.170067] Freeing initrd memory: 55036K
10637 12:42:12.160450 <6>[ 3.180441] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10638 12:42:12.171416 <6>[ 3.191404] tun: Universal TUN/TAP device driver, 1.6
10639 12:42:12.174595 <6>[ 3.197453] thunder_xcv, ver 1.0
10640 12:42:12.177776 <6>[ 3.200958] thunder_bgx, ver 1.0
10641 12:42:12.180955 <6>[ 3.204453] nicpf, ver 1.0
10642 12:42:12.191742 <6>[ 3.208462] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10643 12:42:12.195156 <6>[ 3.215941] hns3: Copyright (c) 2017 Huawei Corporation.
10644 12:42:12.202097 <6>[ 3.221526] hclge is initializing
10645 12:42:12.205142 <6>[ 3.225109] e1000: Intel(R) PRO/1000 Network Driver
10646 12:42:12.211576 <6>[ 3.230238] e1000: Copyright (c) 1999-2006 Intel Corporation.
10647 12:42:12.214743 <6>[ 3.236253] e1000e: Intel(R) PRO/1000 Network Driver
10648 12:42:12.221723 <6>[ 3.241468] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10649 12:42:12.228122 <6>[ 3.247652] igb: Intel(R) Gigabit Ethernet Network Driver
10650 12:42:12.234952 <6>[ 3.253302] igb: Copyright (c) 2007-2014 Intel Corporation.
10651 12:42:12.241698 <6>[ 3.259138] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10652 12:42:12.248069 <6>[ 3.265656] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10653 12:42:12.251508 <6>[ 3.272115] sky2: driver version 1.30
10654 12:42:12.257680 <6>[ 3.277086] VFIO - User Level meta-driver version: 0.3
10655 12:42:12.265320 <6>[ 3.285316] usbcore: registered new interface driver usb-storage
10656 12:42:12.271753 <6>[ 3.291759] usbcore: registered new device driver onboard-usb-hub
10657 12:42:12.280815 <6>[ 3.300858] mt6397-rtc mt6359-rtc: registered as rtc0
10658 12:42:12.291085 <6>[ 3.306328] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-14T12:42:12 UTC (1686746532)
10659 12:42:12.293844 <6>[ 3.315893] i2c_dev: i2c /dev entries driver
10660 12:42:12.311107 <6>[ 3.327661] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10661 12:42:12.317632 <6>[ 3.337818] sdhci: Secure Digital Host Controller Interface driver
10662 12:42:12.324619 <6>[ 3.344256] sdhci: Copyright(c) Pierre Ossman
10663 12:42:12.330809 <6>[ 3.349648] Synopsys Designware Multimedia Card Interface Driver
10664 12:42:12.334083 <6>[ 3.356278] mmc0: CQHCI version 5.10
10665 12:42:12.340514 <6>[ 3.356791] sdhci-pltfm: SDHCI platform and OF driver helper
10666 12:42:12.348623 <6>[ 3.368491] ledtrig-cpu: registered to indicate activity on CPUs
10667 12:42:12.359418 <6>[ 3.375937] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10668 12:42:12.365800 <6>[ 3.383328] usbcore: registered new interface driver usbhid
10669 12:42:12.369070 <6>[ 3.389161] usbhid: USB HID core driver
10670 12:42:12.375235 <6>[ 3.393415] spi_master spi0: will run message pump with realtime priority
10671 12:42:12.422037 <6>[ 3.435090] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10672 12:42:12.441453 <6>[ 3.450997] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10673 12:42:12.444638 <6>[ 3.464568] mmc0: Command Queue Engine enabled
10674 12:42:12.451503 <6>[ 3.466089] cros-ec-spi spi0.0: Chrome EC device registered
10675 12:42:12.457993 <6>[ 3.469319] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10676 12:42:12.461036 <6>[ 3.482322] mmcblk0: mmc0:0001 DA4128 116 GiB
10677 12:42:12.475892 <6>[ 3.492611] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10678 12:42:12.482265 <6>[ 3.493918] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10679 12:42:12.489297 <6>[ 3.504030] NET: Registered PF_PACKET protocol family
10680 12:42:12.492263 <6>[ 3.509295] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10681 12:42:12.499051 <6>[ 3.513290] 9pnet: Installing 9P2000 support
10682 12:42:12.502283 <6>[ 3.519021] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10683 12:42:12.509024 <5>[ 3.522950] Key type dns_resolver registered
10684 12:42:12.515717 <6>[ 3.528799] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10685 12:42:12.518777 <6>[ 3.533255] registered taskstats version 1
10686 12:42:12.521867 <5>[ 3.543551] Loading compiled-in X.509 certificates
10687 12:42:12.557576 <4>[ 3.571200] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10688 12:42:12.567663 <4>[ 3.581907] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10689 12:42:12.578184 <3>[ 3.594725] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10690 12:42:12.590295 <6>[ 3.610323] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10691 12:42:12.597311 <6>[ 3.617198] xhci-mtk 11200000.usb: xHCI Host Controller
10692 12:42:12.603702 <6>[ 3.622721] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10693 12:42:12.613769 <6>[ 3.630651] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10694 12:42:12.620562 <6>[ 3.640100] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10695 12:42:12.627125 <6>[ 3.646195] xhci-mtk 11200000.usb: xHCI Host Controller
10696 12:42:12.633521 <6>[ 3.651677] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10697 12:42:12.640341 <6>[ 3.659328] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10698 12:42:12.647341 <6>[ 3.667223] hub 1-0:1.0: USB hub found
10699 12:42:12.650638 <6>[ 3.671255] hub 1-0:1.0: 1 port detected
10700 12:42:12.660074 <6>[ 3.675603] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10701 12:42:12.663332 <6>[ 3.684388] hub 2-0:1.0: USB hub found
10702 12:42:12.666541 <6>[ 3.688423] hub 2-0:1.0: 1 port detected
10703 12:42:12.675524 <6>[ 3.695686] mtk-msdc 11f70000.mmc: Got CD GPIO
10704 12:42:12.692785 <6>[ 3.709611] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10705 12:42:12.699450 <6>[ 3.717662] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10706 12:42:12.709404 <4>[ 3.725654] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10707 12:42:12.719626 <6>[ 3.735320] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10708 12:42:12.725734 <6>[ 3.743404] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10709 12:42:12.735916 <6>[ 3.751443] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10710 12:42:12.742221 <6>[ 3.759358] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10711 12:42:12.748802 <6>[ 3.767178] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10712 12:42:12.758555 <6>[ 3.775000] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10713 12:42:12.768908 <6>[ 3.785730] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10714 12:42:12.779089 <6>[ 3.794099] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10715 12:42:12.785531 <6>[ 3.802457] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10716 12:42:12.795326 <6>[ 3.810801] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10717 12:42:12.801799 <6>[ 3.819146] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10718 12:42:12.812410 <6>[ 3.827490] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10719 12:42:12.818403 <6>[ 3.835833] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10720 12:42:12.828709 <6>[ 3.844177] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10721 12:42:12.835371 <6>[ 3.852521] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10722 12:42:12.845206 <6>[ 3.860865] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10723 12:42:12.851461 <6>[ 3.869208] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10724 12:42:12.861733 <6>[ 3.877551] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10725 12:42:12.868225 <6>[ 3.885895] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10726 12:42:12.877952 <6>[ 3.894239] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10727 12:42:12.884827 <6>[ 3.902584] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10728 12:42:12.891243 <6>[ 3.911467] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10729 12:42:12.898521 <6>[ 3.918889] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10730 12:42:12.905721 <6>[ 3.925934] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10731 12:42:12.916206 <6>[ 3.933036] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10732 12:42:12.922686 <6>[ 3.940317] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10733 12:42:12.932839 <6>[ 3.947306] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10734 12:42:12.939259 <6>[ 3.956460] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10735 12:42:12.948915 <6>[ 3.965587] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10736 12:42:12.958757 <6>[ 3.974888] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10737 12:42:12.969106 <6>[ 3.984375] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10738 12:42:12.978810 <6>[ 3.993851] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10739 12:42:12.988833 <6>[ 4.002977] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10740 12:42:12.995369 <6>[ 4.012455] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10741 12:42:13.005170 <6>[ 4.021586] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10742 12:42:13.015072 <6>[ 4.030889] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10743 12:42:13.024845 <6>[ 4.041054] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10744 12:42:13.036454 <6>[ 4.053079] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10745 12:42:13.058352 <6>[ 4.075092] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10746 12:42:13.087122 <6>[ 4.107024] hub 2-1:1.0: USB hub found
10747 12:42:13.089789 <6>[ 4.111501] hub 2-1:1.0: 3 ports detected
10748 12:42:13.210430 <6>[ 4.226996] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10749 12:42:13.363271 <6>[ 4.383168] hub 1-1:1.0: USB hub found
10750 12:42:13.366055 <6>[ 4.387530] hub 1-1:1.0: 4 ports detected
10751 12:42:13.442304 <6>[ 4.459275] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10752 12:42:13.686319 <6>[ 4.703021] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10753 12:42:13.818818 <6>[ 4.839306] hub 1-1.4:1.0: USB hub found
10754 12:42:13.822021 <6>[ 4.843956] hub 1-1.4:1.0: 2 ports detected
10755 12:42:14.117755 <6>[ 5.134882] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10756 12:42:14.310005 <6>[ 5.327023] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10757 12:42:25.338823 <6>[ 16.363587] ALSA device list:
10758 12:42:25.345182 <6>[ 16.366844] No soundcards found.
10759 12:42:25.358062 <6>[ 16.379211] Freeing unused kernel memory: 8384K
10760 12:42:25.361010 <6>[ 16.384116] Run /init as init process
10761 12:42:25.391597 <6>[ 16.413186] NET: Registered PF_INET6 protocol family
10762 12:42:25.398434 <6>[ 16.419740] Segment Routing with IPv6
10763 12:42:25.401532 <6>[ 16.423685] In-situ OAM (IOAM) with IPv6
10764 12:42:25.436211 <30>[ 16.438165] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10765 12:42:25.439427 <30>[ 16.461990] systemd[1]: Detected architecture arm64.
10766 12:42:25.443159
10767 12:42:25.446201 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10768 12:42:25.446283
10769 12:42:25.461456 <30>[ 16.483174] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10770 12:42:25.592266 <30>[ 16.610397] systemd[1]: Queued start job for default target Graphical Interface.
10771 12:42:25.635117 <30>[ 16.656438] systemd[1]: Created slice system-getty.slice.
10772 12:42:25.641619 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10773 12:42:25.657778 <30>[ 16.679620] systemd[1]: Created slice system-modprobe.slice.
10774 12:42:25.664774 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10775 12:42:25.682787 <30>[ 16.704163] systemd[1]: Created slice system-serial\x2dgetty.slice.
10776 12:42:25.692994 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10777 12:42:25.706196 <30>[ 16.727511] systemd[1]: Created slice User and Session Slice.
10778 12:42:25.712863 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10779 12:42:25.733454 <30>[ 16.751588] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10780 12:42:25.743416 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10781 12:42:25.761155 <30>[ 16.779189] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10782 12:42:25.767632 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10783 12:42:25.788198 <30>[ 16.803107] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10784 12:42:25.794774 <30>[ 16.815135] systemd[1]: Reached target Local Encrypted Volumes.
10785 12:42:25.801352 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10786 12:42:25.817659 <30>[ 16.839100] systemd[1]: Reached target Paths.
10787 12:42:25.820812 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10788 12:42:25.837255 <30>[ 16.859056] systemd[1]: Reached target Remote File Systems.
10789 12:42:25.844419 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10790 12:42:25.861949 <30>[ 16.883296] systemd[1]: Reached target Slices.
10791 12:42:25.868235 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10792 12:42:25.881369 <30>[ 16.903071] systemd[1]: Reached target Swap.
10793 12:42:25.884568 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10794 12:42:25.905215 <30>[ 16.923382] systemd[1]: Listening on initctl Compatibility Named Pipe.
10795 12:42:25.911755 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10796 12:42:25.918348 <30>[ 16.938141] systemd[1]: Listening on Journal Audit Socket.
10797 12:42:25.924558 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10798 12:42:25.937954 <30>[ 16.959317] systemd[1]: Listening on Journal Socket (/dev/log).
10799 12:42:25.944238 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10800 12:42:25.962095 <30>[ 16.983338] systemd[1]: Listening on Journal Socket.
10801 12:42:25.968418 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10802 12:42:25.981638 <30>[ 17.003329] systemd[1]: Listening on udev Control Socket.
10803 12:42:25.988410 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10804 12:42:26.006076 <30>[ 17.027707] systemd[1]: Listening on udev Kernel Socket.
10805 12:42:26.012623 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10806 12:42:26.049549 <30>[ 17.071342] systemd[1]: Mounting Huge Pages File System...
10807 12:42:26.056211 Mounting [0;1;39mHuge Pages File System[0m...
10808 12:42:26.071568 <30>[ 17.093060] systemd[1]: Mounting POSIX Message Queue File System...
10809 12:42:26.078487 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10810 12:42:26.095436 <30>[ 17.117006] systemd[1]: Mounting Kernel Debug File System...
10811 12:42:26.101850 Mounting [0;1;39mKernel Debug File System[0m...
10812 12:42:26.120937 <30>[ 17.139336] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10813 12:42:26.131712 <30>[ 17.150262] systemd[1]: Starting Create list of static device nodes for the current kernel...
10814 12:42:26.138406 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10815 12:42:26.155540 <30>[ 17.177519] systemd[1]: Starting Load Kernel Module configfs...
10816 12:42:26.162290 Starting [0;1;39mLoad Kernel Module configfs[0m...
10817 12:42:26.179404 <30>[ 17.201322] systemd[1]: Starting Load Kernel Module drm...
10818 12:42:26.186252 Starting [0;1;39mLoad Kernel Module drm[0m...
10819 12:42:26.204856 <30>[ 17.223235] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10820 12:42:26.246378 <30>[ 17.267765] systemd[1]: Starting Journal Service...
10821 12:42:26.249430 Starting [0;1;39mJournal Service[0m...
10822 12:42:26.268292 <30>[ 17.289781] systemd[1]: Starting Load Kernel Modules...
10823 12:42:26.274581 Starting [0;1;39mLoad Kernel Modules[0m...
10824 12:42:26.295351 <30>[ 17.313760] systemd[1]: Starting Remount Root and Kernel File Systems...
10825 12:42:26.301853 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10826 12:42:26.316036 <30>[ 17.337674] systemd[1]: Starting Coldplug All udev Devices...
10827 12:42:26.322422 Starting [0;1;39mColdplug All udev Devices[0m...
10828 12:42:26.340272 <30>[ 17.361980] systemd[1]: Mounted Huge Pages File System.
10829 12:42:26.346728 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10830 12:42:26.361653 <30>[ 17.383533] systemd[1]: Started Journal Service.
10831 12:42:26.368502 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10832 12:42:26.387340 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10833 12:42:26.406031 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10834 12:42:26.430064 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10835 12:42:26.451620 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10836 12:42:26.467546 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10837 12:42:26.482994 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10838 12:42:26.506566 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10839 12:42:26.521788 See 'systemctl status systemd-remount-fs.service' for details.
10840 12:42:26.570647 Mounting [0;1;39mKernel Configuration File System[0m...
10841 12:42:26.588010 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10842 12:42:26.605686 <46>[ 17.623813] systemd-journald[182]: Received client request to flush runtime journal.
10843 12:42:26.614247 Starting [0;1;39mLoad/Save Random Seed[0m...
10844 12:42:26.633082 Starting [0;1;39mApply Kernel Variables[0m...
10845 12:42:26.652360 Starting [0;1;39mCreate System Users[0m...
10846 12:42:26.674522 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10847 12:42:26.697732 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10848 12:42:26.714406 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10849 12:42:26.731047 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10850 12:42:26.746413 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10851 12:42:26.762732 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10852 12:42:26.818340 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10853 12:42:26.842112 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10854 12:42:26.857645 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10855 12:42:26.873388 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10856 12:42:26.922059 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10857 12:42:26.945099 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10858 12:42:26.962814 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10859 12:42:26.982439 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10860 12:42:27.038603 Starting [0;1;39mNetwork Time Synchronization[0m...
10861 12:42:27.058715 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10862 12:42:27.098646 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10863 12:42:27.140391 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10864 12:42:27.162479 <6>[ 18.180742] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10865 12:42:27.175524 <6>[ 18.197215] remoteproc remoteproc0: scp is available
10866 12:42:27.185328 <4>[ 18.202847] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10867 12:42:27.191829 <6>[ 18.213404] remoteproc remoteproc0: powering up scp
10868 12:42:27.202036 <4>[ 18.218671] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10869 12:42:27.208630 <6>[ 18.220444] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10870 12:42:27.215331 <3>[ 18.228506] remoteproc remoteproc0: request_firmware failed: -2
10871 12:42:27.225189 <6>[ 18.242628] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10872 12:42:27.235079 Startin<6>[ 18.251827] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10873 12:42:27.241180 g [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10874 12:42:27.259716 <4>[ 18.278136] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10875 12:42:27.266232 <3>[ 18.283493] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10876 12:42:27.276181 <3>[ 18.293612] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10877 12:42:27.283064 <4>[ 18.294571] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10878 12:42:27.289378 <3>[ 18.301718] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10879 12:42:27.298994 [[0;32m OK [<3>[ 18.306827] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10880 12:42:27.309200 0m] Started [0;<3>[ 18.326916] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10881 12:42:27.318742 1;39mNetwork Tim<3>[ 18.336169] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10882 12:42:27.328997 e Synchronizatio<6>[ 18.337389] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10883 12:42:27.329121 n[0m.
10884 12:42:27.335172 <3>[ 18.345561] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10885 12:42:27.345206 <3>[ 18.363371] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10886 12:42:27.348319 <6>[ 18.363908] mc: Linux media interface: v0.10
10887 12:42:27.355272 [[0;32m OK [<6>[ 18.377604] usbcore: registered new interface driver r8152
10888 12:42:27.365014 0m] Finished [0<3>[ 18.379719] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10889 12:42:27.375211 ;1;39mLoad/Save Screen …s of l<6>[ 18.395162] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10890 12:42:27.381654 eds:white:kbd_ba<6>[ 18.402878] pci_bus 0000:00: root bus resource [bus 00-ff]
10891 12:42:27.384783 cklight[0m.
10892 12:42:27.391644 <4>[ 18.403146] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10893 12:42:27.398302 <4>[ 18.403146] Fallback method does not support PEC.
10894 12:42:27.404576 <3>[ 18.404299] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10895 12:42:27.414853 <3>[ 18.404329] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10896 12:42:27.421484 <3>[ 18.404337] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10897 12:42:27.431015 <3>[ 18.405189] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10898 12:42:27.437750 <3>[ 18.405212] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10899 12:42:27.447621 <3>[ 18.405221] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10900 12:42:27.454387 <3>[ 18.405231] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10901 12:42:27.464109 <3>[ 18.405238] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10902 12:42:27.471068 <3>[ 18.405288] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10903 12:42:27.477595 <6>[ 18.409933] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10904 12:42:27.487489 <6>[ 18.409944] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10905 12:42:27.497421 <6>[ 18.439440] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10906 12:42:27.504188 <6>[ 18.441004] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10907 12:42:27.513744 <3>[ 18.455009] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10908 12:42:27.520294 <6>[ 18.457622] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10909 12:42:27.530477 <6>[ 18.479427] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10910 12:42:27.533750 <6>[ 18.481812] pci 0000:00:00.0: supports D1 D2
10911 12:42:27.540933 <6>[ 18.489960] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10912 12:42:27.550862 <6>[ 18.491788] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10913 12:42:27.557563 <6>[ 18.498773] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10914 12:42:27.563828 <6>[ 18.519243] videodev: Linux video capture interface: v2.00
10915 12:42:27.567468 <6>[ 18.525893] Bluetooth: Core ver 2.22
10916 12:42:27.576962 <4>[ 18.526246] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10917 12:42:27.583734 <4>[ 18.526256] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10918 12:42:27.594053 <6>[ 18.526912] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10919 12:42:27.600730 <6>[ 18.527035] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10920 12:42:27.606988 <6>[ 18.527066] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10921 12:42:27.614150 <6>[ 18.527089] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10922 12:42:27.620591 <6>[ 18.527108] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10923 12:42:27.627869 <6>[ 18.527223] pci 0000:01:00.0: supports D1 D2
10924 12:42:27.634491 <6>[ 18.527227] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10925 12:42:27.641048 <6>[ 18.538939] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10926 12:42:27.644605 <6>[ 18.539934] NET: Registered PF_BLUETOOTH protocol family
10927 12:42:27.655012 <6>[ 18.547360] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10928 12:42:27.658798 <6>[ 18.548200] usbcore: registered new interface driver cdc_ether
10929 12:42:27.665145 <6>[ 18.557491] Bluetooth: HCI device and connection manager initialized
10930 12:42:27.671823 <6>[ 18.557616] usbcore: registered new interface driver r8153_ecm
10931 12:42:27.679107 <6>[ 18.561952] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10932 12:42:27.685414 <6>[ 18.569091] Bluetooth: HCI socket layer initialized
10933 12:42:27.695570 <3>[ 18.570172] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10934 12:42:27.702398 <3>[ 18.572234] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10935 12:42:27.712451 <6>[ 18.578121] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10936 12:42:27.716157 <6>[ 18.578178] r8152 2-1.3:1.0 eth0: v1.12.13
10937 12:42:27.722599 <6>[ 18.584985] Bluetooth: L2CAP socket layer initialized
10938 12:42:27.726187 <6>[ 18.589885] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10939 12:42:27.736263 <6>[ 18.590730] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10940 12:42:27.739862 <6>[ 18.594575] Bluetooth: SCO socket layer initialized
10941 12:42:27.749628 <6>[ 18.603602] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10942 12:42:27.756396 <6>[ 18.605216] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10943 12:42:27.769691 <6>[ 18.606369] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10944 12:42:27.772791 <6>[ 18.606530] usbcore: registered new interface driver uvcvideo
10945 12:42:27.779427 <6>[ 18.649864] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10946 12:42:27.785658 <6>[ 18.653163] pci 0000:00:00.0: PCI bridge to [bus 01]
10947 12:42:27.792546 <6>[ 18.653847] usbcore: registered new interface driver btusb
10948 12:42:27.802291 <4>[ 18.654412] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10949 12:42:27.809191 <3>[ 18.654423] Bluetooth: hci0: Failed to load firmware file (-2)
10950 12:42:27.812426 <3>[ 18.654426] Bluetooth: hci0: Failed to set up firmware (-2)
10951 12:42:27.825338 <4>[ 18.654430] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10952 12:42:27.832269 <3>[ 18.661728] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10953 12:42:27.841741 <3>[ 18.662542] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10954 12:42:27.845584 <6>[ 18.664844] remoteproc remoteproc0: powering up scp
10955 12:42:27.855213 <4>[ 18.664892] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10956 12:42:27.861780 <3>[ 18.664900] remoteproc remoteproc0: request_firmware failed: -2
10957 12:42:27.871944 <3>[ 18.664904] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10958 12:42:27.878725 <6>[ 18.666895] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10959 12:42:27.888198 <3>[ 18.677930] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10960 12:42:27.894985 <6>[ 18.680727] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10961 12:42:27.901629 <3>[ 18.706886] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10962 12:42:27.908444 <6>[ 18.708186] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10963 12:42:27.918325 <3>[ 18.736958] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10964 12:42:27.924542 <6>[ 18.738529] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10965 12:42:27.931159 <3>[ 18.762266] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10966 12:42:27.941278 <5>[ 18.797756] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10967 12:42:27.944173 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10968 12:42:27.957935 <5>[ 18.979174] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10969 12:42:27.967549 <4>[ 18.986079] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10970 12:42:27.977244 <3>[ 18.986848] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10971 12:42:27.980950 <6>[ 18.994963] cfg80211: failed to load regulatory.db
10972 12:42:28.030384 <6>[ 19.048398] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10973 12:42:28.036640 <6>[ 19.055920] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10974 12:42:28.060795 <6>[ 19.082646] mt7921e 0000:01:00.0: ASIC revision: 79610010
10975 12:42:28.151232 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10976 12:42:28.167964 <4>[ 19.183104] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10977 12:42:28.174559 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10978 12:42:28.193048 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10979 12:42:28.209384 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10980 12:42:28.225431 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10981 12:42:28.245210 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10982 12:42:28.257243 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10983 12:42:28.286135 [[0;32m OK [0m] Listening on [0;1;39mD-Bus <4>[ 19.302220] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10984 12:42:28.289689 System Message Bus Socket[0m.
10985 12:42:28.306587 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10986 12:42:28.321399 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10987 12:42:28.341022 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10988 12:42:28.382015 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10989 12:42:28.409475 <4>[ 19.424669] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10990 12:42:28.420272 Starting [0;1;39mUser Login Management[0m...
10991 12:42:28.439537 Starting [0;1;39mPermit User Sessions[0m...
10992 12:42:28.457602 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10993 12:42:28.473889 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10994 12:42:28.490540 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10995 12:42:28.500583 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10996 12:42:28.536812 [[0;32m OK [0m] Started [0;<4>[ 19.550513] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10997 12:42:28.539956 1;39mSerial Getty on ttyS0[0m.
10998 12:42:28.546177 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10999 12:42:28.562841 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11000 12:42:28.578301 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11001 12:42:28.593782 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11002 12:42:28.658432 <4>[ 19.673653] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11003 12:42:28.665208 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11004 12:42:28.694435 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11005 12:42:28.733589
11006 12:42:28.733735
11007 12:42:28.737343 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11008 12:42:28.737460
11009 12:42:28.740577 debian-bullseye-arm64 login: root (automatic login)
11010 12:42:28.740661
11011 12:42:28.740727
11012 12:42:28.757002 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Wed Jun 14 12:30:40 UTC 2023 aarch64
11013 12:42:28.757089
11014 12:42:28.763147 The programs included with the Debian GNU/Linux system are free software;
11015 12:42:28.770334 the exact distribution terms for each program are described in the
11016 12:42:28.783460 individual files in /usr/share/doc/*/co<4>[ 19.798239] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11017 12:42:28.783552 pyright.
11018 12:42:28.783620
11019 12:42:28.789885 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11020 12:42:28.793038 permitted by applicable law.
11021 12:42:28.793384 Matched prompt #10: / #
11023 12:42:28.793603 Setting prompt string to ['/ #']
11024 12:42:28.793730 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11026 12:42:28.794044 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11027 12:42:28.794171 start: 2.2.6 expect-shell-connection (timeout 00:02:47) [common]
11028 12:42:28.794248 Setting prompt string to ['/ #']
11029 12:42:28.794310 Forcing a shell prompt, looking for ['/ #']
11031 12:42:28.844551 / #
11032 12:42:28.844734 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11033 12:42:28.844835 Waiting using forced prompt support (timeout 00:02:30)
11034 12:42:28.849599
11035 12:42:28.849906 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11036 12:42:28.850005 start: 2.2.7 export-device-env (timeout 00:02:47) [common]
11037 12:42:28.850101 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11038 12:42:28.850186 end: 2.2 depthcharge-retry (duration 00:02:13) [common]
11039 12:42:28.850272 end: 2 depthcharge-action (duration 00:02:13) [common]
11040 12:42:28.850359 start: 3 lava-test-retry (timeout 00:07:25) [common]
11041 12:42:28.850442 start: 3.1 lava-test-shell (timeout 00:07:25) [common]
11042 12:42:28.850517 Using namespace: common
11044 12:42:28.950842 / # #
11045 12:42:28.951039 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11046 12:42:28.951157 <4>[ 19.917294] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11047 12:42:28.956006 #
11048 12:42:28.956281 Using /lava-10724838
11050 12:42:29.056575 / # export SHELL=/bin/sh
11051 12:42:29.056772 export SHELL=<4>[ 20.037109] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11052 12:42:29.061704 /bin/sh
11054 12:42:29.162251 / # . /lava-10724838/environment
11055 12:42:29.162479 . /lava-10724838/environment<4>[ 20.157005] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11056 12:42:29.167603
11058 12:42:29.268210 / # /lava-10724838/bin/lava-test-runner /lava-10724838/0
11059 12:42:29.268453 Test shell timeout: 10s (minimum of the action and connection timeout)
11060 12:42:29.268939 /lava-10724838/bin/lava-test-runner /lava-10724838/0<4>[ 20.276761] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11061 12:42:29.273780
11062 12:42:29.314913 + export TESTRUN_ID=0_igt-kms-medi<8>[ 20.323374] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 10724838_1.5.2.3.1>
11063 12:42:29.315068 atek
11064 12:42:29.315168 + cd /lava-10724838/0/tests/0_igt-kms-mediatek
11065 12:42:29.315261 + cat uuid
11066 12:42:29.315361 + UUID=10724838_1.5.2.3.1
11067 12:42:29.315451 + set +x
11068 12:42:29.315724 Received signal: <STARTRUN> 0_igt-kms-mediatek 10724838_1.5.2.3.1
11069 12:42:29.315833 Starting test lava.0_igt-kms-mediatek (10724838_1.5.2.3.1)
11070 12:42:29.315946 Skipping test definition patterns.
11071 12:42:29.332513 + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getstats core_getversion core_setmaster_vs_auth drm_read kms_addfb_basic kms_atomic kms_<8>[ 20.354453] <LAVA_SIGNAL_TESTSET START core_auth>
11072 12:42:29.332841 Received signal: <TESTSET> START core_auth
11073 12:42:29.332954 Starting test_set core_auth
11074 12:42:29.338989 flip_event_leak kms_prop_blob kms_setmode kms_vblank
11075 12:42:29.355768 <14>[ 20.377903] [IGT] core_auth: executing
11076 12:42:29.362641 IGT-Version: 1.2<14>[ 20.382330] [IGT] core_auth: starting subtest getclient-simple
11077 12:42:29.369236 7.1-g2dd77d6 (aa<14>[ 20.390719] [IGT] core_auth: exiting, ret=0
11078 12:42:29.375586 <3>[ 20.395618] mt7921e 0000:01:00.0: hardware init failed
11079 12:42:29.375671 rch64) (Linux: 6.1.31 aarch64)
11080 12:42:29.378979 Starting subtest: getclient-simple
11081 12:42:29.388698 Opened devic<8>[ 20.407646] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
11082 12:42:29.388814 e: /dev/dri/card0
11083 12:42:29.389074 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
11085 12:42:29.395022 [1mSubtest getclient-simple: SUCCESS (0.000s)[0m
11086 12:42:29.411721 <14>[ 20.433606] [IGT] core_auth: executing
11087 12:42:29.418012 IGT-Version: 1.2<14>[ 20.438221] [IGT] core_auth: starting subtest getclient-master-drop
11088 12:42:29.424932 7.1-g2dd77d6 (aa<14>[ 20.446360] [IGT] core_auth: exiting, ret=0
11089 12:42:29.428063 rch64) (Linux: 6.1.31 aarch64)
11090 12:42:29.431237 Starting subtest: getclient-master-drop
11091 12:42:29.437864 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
11093 12:42:29.441248 Opened <8>[ 20.457904] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
11094 12:42:29.441350 device: /dev/dri/card0
11095 12:42:29.447662 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
11096 12:42:29.462033 <14>[ 20.484198] [IGT] core_auth: executing
11097 12:42:29.468844 IGT-Version: 1.2<14>[ 20.488678] [IGT] core_auth: starting subtest basic-auth
11098 12:42:29.475560 7.1-g2dd77d6 (aa<14>[ 20.495725] [IGT] core_auth: exiting, ret=0
11099 12:42:29.478517 rch64) (Linux: 6.1.31 aarch64)
11100 12:42:29.478622 Opened device: /dev/dri/card0
11101 12:42:29.488483 Starting subtest:<8>[ 20.507364] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
11102 12:42:29.488598 basic-auth
11103 12:42:29.488875 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
11105 12:42:29.491496 [1mSubtest basic-auth: SUCCESS (0.000s)[0m
11106 12:42:29.510615 <14>[ 20.532669] [IGT] core_auth: executing
11107 12:42:29.517485 IGT-Version: 1.2<14>[ 20.537204] [IGT] core_auth: starting subtest many-magics
11108 12:42:29.520318 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11109 12:42:29.524099 Opened device: /dev/dri/card0
11110 12:42:29.527330 Starting subtest: many-magics
11111 12:42:29.530532 Reopening device failed after 1020 opens
11112 12:42:29.536846 [1mSubtest many<14>[ 20.558018] [IGT] core_auth: exiting, ret=0
11113 12:42:29.540542 -magics: SUCCESS (0.014s)[0m
11114 12:42:29.550907 <8>[ 20.569963] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
11115 12:42:29.551192 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
11117 12:42:29.554392 <8>[ 20.578478] <LAVA_SIGNAL_TESTSET STOP>
11118 12:42:29.554670 Received signal: <TESTSET> STOP
11119 12:42:29.554773 Closing test_set core_auth
11120 12:42:29.597841 <14>[ 20.619567] [IGT] core_getclient: executing
11121 12:42:29.603972 IGT-Version: 1.2<14>[ 20.624490] [IGT] core_getclient: exiting, ret=0
11122 12:42:29.607201 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11123 12:42:29.610969 Opened device: /dev/dri/card0
11124 12:42:29.611077 SUCCESS (0.006s)
11125 12:42:29.617416 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
11127 12:42:29.620255 <8>[ 20.637509] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
11128 12:42:29.620332
11129 12:42:29.660305 <14>[ 20.682501] [IGT] core_getstats: executing
11130 12:42:29.667266 IGT-Version: 1.2<14>[ 20.687320] [IGT] core_getstats: exiting, ret=0
11131 12:42:29.670446 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11132 12:42:29.673556 Opened device: /dev/dri/card0
11133 12:42:29.680304 S<8>[ 20.699505] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
11134 12:42:29.680409 UCCESS (0.006s)
11135 12:42:29.680686 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
11137 12:42:29.721998 <14>[ 20.744075] [IGT] core_getversion: executing
11138 12:42:29.728436 IGT-Version: 1.2<14>[ 20.749089] [IGT] core_getversion: exiting, ret=0
11139 12:42:29.732041 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11140 12:42:29.735151 Opened device: /dev/dri/card0
11141 12:42:29.741524 S<8>[ 20.761519] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
11142 12:42:29.741804 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
11144 12:42:29.744710 UCCESS (0.006s)
11145 12:42:29.784023 <14>[ 20.806339] [IGT] core_setmaster_vs_auth: executing
11146 12:42:29.790792 IGT-Version: 1.2<14>[ 20.812055] [IGT] core_setmaster_vs_auth: exiting, ret=0
11147 12:42:29.797376 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11148 12:42:29.797495 Opened device: /dev/dri/card0
11149 12:42:29.800851 SUCCESS (0.007s)
11150 12:42:29.807308 <8>[ 20.825758] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
11151 12:42:29.807435
11152 12:42:29.807718 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
11154 12:42:29.835178 <8>[ 20.856856] <LAVA_SIGNAL_TESTSET START drm_read>
11155 12:42:29.835456 Received signal: <TESTSET> START drm_read
11156 12:42:29.835536 Starting test_set drm_read
11157 12:42:29.857820 <14>[ 20.879623] [IGT] drm_read: executing
11158 12:42:29.864076 IGT-Version: 1.2<14>[ 20.884258] [IGT] drm_read: exiting, ret=77
11159 12:42:29.867243 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11160 12:42:29.870822 Opened device: /dev/dri/card0
11161 12:42:29.877471 N<8>[ 20.896242] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
11162 12:42:29.877760 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
11164 12:42:29.880410 o KMS driver or no outputs, pipes: 8, outputs: 0
11165 12:42:29.883879 [1mSubtest invalid-buffer: SKIP (0.000s)[0m
11166 12:42:29.899904 <14>[ 20.921757] [IGT] drm_read: executing
11167 12:42:29.906194 IGT-Version: 1.2<14>[ 20.926421] [IGT] drm_read: exiting, ret=77
11168 12:42:29.909525 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11169 12:42:29.913201 Opened device: /dev/dri/card0
11170 12:42:29.919569 N<8>[ 20.938323] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
11171 12:42:29.919859 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
11173 12:42:29.923115 o KMS driver or no outputs, pipes: 8, outputs: 0
11174 12:42:29.926130 [1mSubtest fault-buffer: SKIP (0.000s)[0m
11175 12:42:29.942132 <14>[ 20.963827] [IGT] drm_read: executing
11176 12:42:29.948737 IGT-Version: 1.2<14>[ 20.968436] [IGT] drm_read: exiting, ret=77
11177 12:42:29.951781 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11178 12:42:29.954953 Opened device: /dev/dri/card0
11179 12:42:29.961318 N<8>[ 20.980435] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
11180 12:42:29.961577 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
11182 12:42:29.965053 o KMS driver or no outputs, pipes: 8, outputs: 0
11183 12:42:29.968218 [1mSubtest empty-block: SKIP (0.000s)[0m
11184 12:42:29.983677 <14>[ 21.005792] [IGT] drm_read: executing
11185 12:42:29.990198 IGT-Version: 1.2<14>[ 21.010506] [IGT] drm_read: exiting, ret=77
11186 12:42:29.993631 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11187 12:42:29.996680 Opened device: /dev/dri/card0
11188 12:42:30.003156 N<8>[ 21.022437] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
11189 12:42:30.003413 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
11191 12:42:30.006728 o KMS driver or no outputs, pipes: 8, outputs: 0
11192 12:42:30.009776 [1mSubtest empty-nonblock: SKIP (0.000s)[0m
11193 12:42:30.025420 <14>[ 21.047509] [IGT] drm_read: executing
11194 12:42:30.031710 IGT-Version: 1.2<14>[ 21.052060] [IGT] drm_read: exiting, ret=77
11195 12:42:30.035444 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11196 12:42:30.038595 Opened device: /dev/dri/card0
11197 12:42:30.045068 N<8>[ 21.064101] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
11198 12:42:30.045366 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
11200 12:42:30.048827 o KMS driver or no outputs, pipes: 8, outputs: 0
11201 12:42:30.054837 [1mSubtest short-buffer-block: SKIP (0.000s)[0m
11202 12:42:30.068377 <14>[ 21.090265] [IGT] drm_read: executing
11203 12:42:30.074627 IGT-Version: 1.2<14>[ 21.094926] [IGT] drm_read: exiting, ret=77
11204 12:42:30.078297 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11205 12:42:30.081253 Opened device: /dev/dri/card0
11206 12:42:30.088131 N<8>[ 21.106674] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
11207 12:42:30.088432 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11209 12:42:30.091065 o KMS driver or no outputs, pipes: 8, outputs: 0
11210 12:42:30.097907 [1mSubtest short-buffer-nonblock: SKIP (0.000s)[0m
11211 12:42:30.110773 <14>[ 21.132591] [IGT] drm_read: executing
11212 12:42:30.117061 IGT-Version: 1.2<14>[ 21.137166] [IGT] drm_read: exiting, ret=77
11213 12:42:30.120221 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11214 12:42:30.123912 Opened device: /dev/dri/card0
11215 12:42:30.129966 N<8>[ 21.149242] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
11216 12:42:30.130271 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11218 12:42:30.136996 o KMS driver or no outputs, pipe<8>[ 21.159057] <LAVA_SIGNAL_TESTSET STOP>
11219 12:42:30.137083 s: 8, outputs: 0
11220 12:42:30.137321 Received signal: <TESTSET> STOP
11221 12:42:30.137389 Closing test_set drm_read
11222 12:42:30.143771 [1mSubtest short-buffer-wakeup: SKIP (0.000s)[0m
11223 12:42:30.162818 <8>[ 21.185164] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
11224 12:42:30.163131 Received signal: <TESTSET> START kms_addfb_basic
11225 12:42:30.163211 Starting test_set kms_addfb_basic
11226 12:42:30.186231 <14>[ 21.207917] [IGT] kms_addfb_basic: executing
11227 12:42:30.192320 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11228 12:42:30.198722 <14>[ 21.217529] [IGT] kms_addfb_basic: starting subtest unused-handle
11229 12:42:30.198853 Opened device: /dev/dri/card0
11230 12:42:30.202355 Starting subtest: unused-handle
11231 12:42:30.208643 [1mSubtest unused-handle: SUCCESS (0.000s)[0m
11232 12:42:30.215226 Test requirement<14>[ 21.235327] [IGT] kms_addfb_basic: exiting, ret=0
11233 12:42:30.218976 not met in function igt_require_i915, file ../lib/drmtest.c:721:
11234 12:42:30.228842 Test requirem<8>[ 21.248073] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
11235 12:42:30.229112 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11237 12:42:30.232036 ent: is_i915_device(fd)
11238 12:42:30.238422 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11239 12:42:30.241940 Test requirement: is_i915_device(fd)
11240 12:42:30.244976 No KMS driver or no outputs, pipes: 8, outputs: 0
11241 12:42:30.251898 <14>[ 21.273622] [IGT] kms_addfb_basic: executing
11242 12:42:30.258111 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11243 12:42:30.264978 <14>[ 21.283416] [IGT] kms_addfb_basic: starting subtest unused-pitches
11244 12:42:30.265063 Opened device: /dev/dri/card0
11245 12:42:30.268105 Starting subtest: unused-pitches
11246 12:42:30.274950 [1mSubtest unused-pitches: SUCCESS (0.000s)[0m
11247 12:42:30.278083 Test requirem<14>[ 21.300511] [IGT] kms_addfb_basic: exiting, ret=0
11248 12:42:30.284999 ent not met in function igt_require_i915, file ../lib/drmtest.c:721:
11249 12:42:30.294703 Test requirement: is_i915_<8>[ 21.313552] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
11250 12:42:30.294788 device(fd)
11251 12:42:30.295037 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11253 12:42:30.304711 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11254 12:42:30.307816 Test requirement: is_i915_device(fd)
11255 12:42:30.310816 No KMS driver or no outputs, pipes: 8, outputs: 0
11256 12:42:30.317692 <14>[ 21.339726] [IGT] kms_addfb_basic: executing
11257 12:42:30.324065 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11258 12:42:30.330541 <14>[ 21.349139] [IGT] kms_addfb_basic: starting subtest unused-offsets
11259 12:42:30.330658 Opened device: /dev/dri/card0
11260 12:42:30.334266 Starting subtest: unused-offsets
11261 12:42:30.340471 [1mSubtest unused-offsets: SUCCESS (0.000s)[0m
11262 12:42:30.347409 Test requirem<14>[ 21.366840] [IGT] kms_addfb_basic: exiting, ret=0
11263 12:42:30.350792 ent not met in function igt_require_i915, file ../lib/drmtest.c:721:
11264 12:42:30.360583 Test requi<8>[ 21.379416] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
11265 12:42:30.360874 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11267 12:42:30.363799 rement: is_i915_device(fd)
11268 12:42:30.370369 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11269 12:42:30.373349 Test requirement: is_i915_device(fd)
11270 12:42:30.376601 No KMS driver or no outputs, pipes: 8, outputs: 0
11271 12:42:30.383244 <14>[ 21.404429] [IGT] kms_addfb_basic: executing
11272 12:42:30.386965 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11273 12:42:30.393173 <14>[ 21.413751] [IGT] kms_addfb_basic: starting subtest unused-modifier
11274 12:42:30.396804 Opened device: /dev/dri/card0
11275 12:42:30.400013 Starting subtest: unused-modifier
11276 12:42:30.403127 [1mSubtest unused-modifier: SUCCESS (0.000s)[0m
11277 12:42:30.409527 <14>[ 21.431439] [IGT] kms_addfb_basic: exiting, ret=0
11278 12:42:30.422809 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721<8>[ 21.443204] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
11279 12:42:30.422933 :
11280 12:42:30.423207 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11282 12:42:30.426411 Test requirement: is_i915_device(fd)
11283 12:42:30.436351 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11284 12:42:30.439154 Test requirement: is_i915_device(fd)
11285 12:42:30.442684 No KMS driver or no outputs, pipes: 8, outputs: 0
11286 12:42:30.445799 <14>[ 21.469038] [IGT] kms_addfb_basic: executing
11287 12:42:30.452476 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11288 12:42:30.459329 <14>[ 21.478993] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
11289 12:42:30.462151 Opened device: /dev/dri/card0
11290 12:42:30.466059 Starting subtest: clobberred-modifier
11291 12:42:30.475727 Test requirement not met in function igt_require_i915, fil<14>[ 21.496729] [IGT] kms_addfb_basic: exiting, ret=77
11292 12:42:30.478784 e ../lib/drmtest.c:721:
11293 12:42:30.481958 Test requirement: is_i915_device(fd)
11294 12:42:30.488825 [1mSubtest clobb<8>[ 21.509717] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11295 12:42:30.489115 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11297 12:42:30.492098 erred-modifier: SKIP (0.000s)[0m
11298 12:42:30.501708 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11299 12:42:30.505301 Test requirement: is_i915_device(fd)
11300 12:42:30.514778 Test requirement not met in function igt_require_i915, file ../lib/d<14>[ 21.535725] [IGT] kms_addfb_basic: executing
11301 12:42:30.514881 rmtest.c:721:
11302 12:42:30.518476 Test requirement: is_i915_device(fd)
11303 12:42:30.528515 No KMS driv<14>[ 21.545958] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11304 12:42:30.531607 er or no outputs, pipes: 8, outputs: 0
11305 12:42:30.537751 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11306 12:42:30.544426 Opened device: /dev/dri/<14>[ 21.565020] [IGT] kms_addfb_basic: exiting, ret=77
11307 12:42:30.544550 card0
11308 12:42:30.547549 Starting subtest: invalid-smem-bo-on-discrete
11309 12:42:30.557376 Test requirement not met i<8>[ 21.577556] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11310 12:42:30.557663 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11312 12:42:30.564175 n function igt_require_intel, file ../lib/drmtest.c:716:
11313 12:42:30.567564 Test requirement: is_intel_device(fd)
11314 12:42:30.574316 [1mSubtest invalid-smem-bo-on-discrete: SKIP (0.000s)[0m
11315 12:42:30.584223 Test requirement not met in function igt_require_i915, file ../lib/<14>[ 21.604438] [IGT] kms_addfb_basic: executing
11316 12:42:30.584306 drmtest.c:721:
11317 12:42:30.587311 Test requirement: is_i915_device(fd)
11318 12:42:30.593976 Test requi<14>[ 21.615398] [IGT] kms_addfb_basic: starting subtest legacy-format
11319 12:42:30.600261 rement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11320 12:42:30.603805 Test requirement: is_i915_device(fd)
11321 12:42:30.610016 No KMS driver or no outputs, pipes: 8, outputs: 0
11322 12:42:30.613220 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11323 12:42:30.616926 Opened device: /dev/dri/card0
11324 12:42:30.623158 Starting subtes<14>[ 21.645141] [IGT] kms_addfb_basic: exiting, ret=0
11325 12:42:30.626801 t: legacy-format
11326 12:42:30.629761 Successfully fuzzed 10000 {bpp, depth} variations
11327 12:42:30.636324 [1mSubtest<8>[ 21.657753] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11328 12:42:30.636618 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11330 12:42:30.639489 legacy-format: SUCCESS (0.013s)[0m
11331 12:42:30.649962 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11332 12:42:30.652955 Test requirement: is_i915_device(fd)
11333 12:42:30.662684 Test requirement not met in function igt_require_i915, file ../li<14>[ 21.683758] [IGT] kms_addfb_basic: executing
11334 12:42:30.662797 b/drmtest.c:721:
11335 12:42:30.665934 Test requirement: is_i915_device(fd)
11336 12:42:30.676346 No KMS driver or no outputs, pipes: 8, o<14>[ 21.696908] [IGT] kms_addfb_basic: starting subtest no-handle
11337 12:42:30.676431 utputs: 0
11338 12:42:30.682439 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11339 12:42:30.689116 Opened device: /dev/d<14>[ 21.711009] [IGT] kms_addfb_basic: exiting, ret=0
11340 12:42:30.689212 ri/card0
11341 12:42:30.692691 Starting subtest: no-handle
11342 12:42:30.702456 [1mSubtest no-handle: SUCCESS (0.000s)[<8>[ 21.723756] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11343 12:42:30.702566 0m
11344 12:42:30.702858 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11346 12:42:30.712105 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11347 12:42:30.715940 Test requirement: is_i915_device(fd)
11348 12:42:30.722244 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11349 12:42:30.728920 Test requirement<14>[ 21.749132] [IGT] kms_addfb_basic: executing
11350 12:42:30.729059 : is_i915_device(fd)
11351 12:42:30.735673 No KMS driver or no outputs, pipes: 8, outputs: 0
11352 12:42:30.741827 IGT-Version: 1.27.1-g2d<14>[ 21.762541] [IGT] kms_addfb_basic: starting subtest basic
11353 12:42:30.744961 d77d6 (aarch64) (Linux: 6.1.31 aarch64)
11354 12:42:30.748697 Opened device: /dev/dri/card0
11355 12:42:30.748834 Starting subtest: basic
11356 12:42:30.755360 <14>[ 21.776274] [IGT] kms_addfb_basic: exiting, ret=0
11357 12:42:30.755461
11358 12:42:30.758334 [1mSubtest basic: SUCCESS (0.000s)[0m
11359 12:42:30.768550 Test requirement not met in function i<8>[ 21.788886] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11360 12:42:30.768871 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11362 12:42:30.771723 gt_require_i915, file ../lib/drmtest.c:721:
11363 12:42:30.774937 Test requirement: is_i915_device(fd)
11364 12:42:30.781419 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11365 12:42:30.784948 Test requirement: is_i915_device(fd)
11366 12:42:30.791128 No KMS driver or no <14>[ 21.813992] [IGT] kms_addfb_basic: executing
11367 12:42:30.794598 outputs, pipes: 8, outputs: 0
11368 12:42:30.801141 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11369 12:42:30.807945 O<14>[ 21.826731] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11370 12:42:30.810962 pened device: /dev/dri/card0
11371 12:42:30.811037 Starting subtest: bad-pitch-0
11372 12:42:30.821380 [1mSubtest bad-pitch-0: SUCCESS (0<14>[ 21.841937] [IGT] kms_addfb_basic: exiting, ret=0
11373 12:42:30.821486 .000s)[0m
11374 12:42:30.834012 Test requirement not met in function igt_require_i915, file ../lib/d<8>[ 21.854274] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11375 12:42:30.834124 rmtest.c:721:
11376 12:42:30.834385 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11378 12:42:30.837577 Test requirement: is_i915_device(fd)
11379 12:42:30.847305 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11380 12:42:30.851004 Test requirement: is_i915_device(fd)
11381 12:42:30.857225 No KMS driver or no outputs, pipes<14>[ 21.879148] [IGT] kms_addfb_basic: executing
11382 12:42:30.857331 : 8, outputs: 0
11383 12:42:30.864154 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11384 12:42:30.870485 Opened device: <14>[ 21.891863] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11385 12:42:30.873763 /dev/dri/card0
11386 12:42:30.876820 Starting subtest: bad-pitch-32
11387 12:42:30.880560 [1mSubtest bad-pitch-32: SUCCESS (0.000s)[0m
11388 12:42:30.883594 <14>[ 21.906495] [IGT] kms_addfb_basic: exiting, ret=0
11389 12:42:30.899988 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721<8>[ 21.918834] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11390 12:42:30.900110 :
11391 12:42:30.900388 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11393 12:42:30.903584 Test requirement: is_i915_device(fd)
11394 12:42:30.909988 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11395 12:42:30.913109 Test requirement: is_i915_device(fd)
11396 12:42:30.916908 No KMS driver or no outputs, pipes: 8, outputs: 0
11397 12:42:30.923093 <14>[ 21.944832] [IGT] kms_addfb_basic: executing
11398 12:42:30.926740 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11399 12:42:30.929860 Opened device: /dev/dri/card0
11400 12:42:30.936148 <14>[ 21.957173] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11401 12:42:30.940009 Starting subtest: bad-pitch-63
11402 12:42:30.943167 [1mSubtest bad-pitch-63: SUCCESS (0.000s)[0m
11403 12:42:30.949712 Test requirement<14>[ 21.971613] [IGT] kms_addfb_basic: exiting, ret=0
11404 12:42:30.955837 not met in function igt_require_i915, file ../lib/drmtest.c:721:
11405 12:42:30.963009 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11407 12:42:30.965982 Test requirem<8>[ 21.984476] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11408 12:42:30.966064 ent: is_i915_device(fd)
11409 12:42:30.972830 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11410 12:42:30.976007 Test requirement: is_i915_device(fd)
11411 12:42:30.982397 No KMS driver or no outputs, pipes: 8, outputs: 0
11412 12:42:30.985849 <14>[ 22.009169] [IGT] kms_addfb_basic: executing
11413 12:42:30.992067 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11414 12:42:30.995838 Opened device: /dev/dri/card0
11415 12:42:31.002110 <14>[ 22.021219] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11416 12:42:31.005366 Starting subtest: bad-pitch-128
11417 12:42:31.008654 [1mSubtest bad-pitch-128: SUCCESS (0.000s)[0m
11418 12:42:31.015515 Test requireme<14>[ 22.036209] [IGT] kms_addfb_basic: exiting, ret=0
11419 12:42:31.022171 nt not met in function igt_require_i915, file ../lib/drmtest.c:721:
11420 12:42:31.028453 Test requir<8>[ 22.049164] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11421 12:42:31.028720 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11423 12:42:31.032143 ement: is_i915_device(fd)
11424 12:42:31.038580 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11425 12:42:31.041808 Test requirement: is_i915_device(fd)
11426 12:42:31.044786 No KMS driver or no outputs, pipes: 8, outputs: 0
11427 12:42:31.052157 <14>[ 22.074055] [IGT] kms_addfb_basic: executing
11428 12:42:31.058217 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11429 12:42:31.058332 Opened device: /dev/dri/card0
11430 12:42:31.065243 <14>[ 22.086205] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11431 12:42:31.068322 Starting subtest: bad-pitch-256
11432 12:42:31.075359 [1mSubtest bad-pitch-256: SUCCESS (0.000s)[0m
11433 12:42:31.078595 Test requireme<14>[ 22.101014] [IGT] kms_addfb_basic: exiting, ret=0
11434 12:42:31.085290 nt not met in function igt_require_i915, file ../lib/drmtest.c:721:
11435 12:42:31.094611 Test requir<8>[ 22.113767] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11436 12:42:31.094733 ement: is_i915_device(fd)
11437 12:42:31.095026 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11439 12:42:31.104402 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11440 12:42:31.108152 Test requirement: is_i915_device(fd)
11441 12:42:31.111233 No KMS driver or no outputs, pipes: 8, outputs: 0
11442 12:42:31.114305 <14>[ 22.138679] [IGT] kms_addfb_basic: executing
11443 12:42:31.121381 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11444 12:42:31.124449 Opened device: /dev/dri/card0
11445 12:42:31.131283 <14>[ 22.150995] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11446 12:42:31.134254 Starting subtest: bad-pitch-1024
11447 12:42:31.137886 [1mSubtest bad-pitch-1024: SUCCESS (0.000s)[0m
11448 12:42:31.144131 Test require<14>[ 22.165873] [IGT] kms_addfb_basic: exiting, ret=0
11449 12:42:31.150972 ment not met in function igt_require_i915, file ../lib/drmtest.c:721:
11450 12:42:31.157646 Test requ<8>[ 22.178315] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11451 12:42:31.157934 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11453 12:42:31.160728 irement: is_i915_device(fd)
11454 12:42:31.167753 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11455 12:42:31.170934 Test requirement: is_i915_device(fd)
11456 12:42:31.177246 No KMS driver or no outputs, pipes: 8, outputs: 0
11457 12:42:31.180961 <14>[ 22.204400] [IGT] kms_addfb_basic: executing
11458 12:42:31.187450 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11459 12:42:31.190574 Opened device: /dev/dri/card0
11460 12:42:31.196969 <14>[ 22.216752] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11461 12:42:31.200472 Starting subtest: bad-pitch-999
11462 12:42:31.203603 [1mSubtest bad-pitch-999: SUCCESS (0.000s)[0m
11463 12:42:31.210372 Test requireme<14>[ 22.231486] [IGT] kms_addfb_basic: exiting, ret=0
11464 12:42:31.216646 nt not met in function igt_require_i915, file ../lib/drmtest.c:721:
11465 12:42:31.223336 Test requir<8>[ 22.244345] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11466 12:42:31.223611 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11468 12:42:31.227028 ement: is_i915_device(fd)
11469 12:42:31.233260 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11470 12:42:31.237023 Test requirement: is_i915_device(fd)
11471 12:42:31.239826 No KMS driver or no outputs, pipes: 8, outputs: 0
11472 12:42:31.247887 <14>[ 22.270074] [IGT] kms_addfb_basic: executing
11473 12:42:31.254314 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11474 12:42:31.257490 Opened device: /dev/dri/card0
11475 12:42:31.264155 <14>[ 22.282458] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11476 12:42:31.264252 Starting subtest: bad-pitch-65536
11477 12:42:31.271072 [1mSubtest bad-pitch-65536: SUCCESS (0.000s)[0m
11478 12:42:31.277330 Test requi<14>[ 22.297374] [IGT] kms_addfb_basic: exiting, ret=0
11479 12:42:31.284246 rement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11480 12:42:31.290422 Test re<8>[ 22.310168] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11481 12:42:31.290685 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11483 12:42:31.294088 quirement: is_i915_device(fd)
11484 12:42:31.300926 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11485 12:42:31.303874 Test requirement: is_i915_device(fd)
11486 12:42:31.307357 No KMS driver or no outputs, pipes: 8, outputs: 0
11487 12:42:31.313796 <14>[ 22.335288] [IGT] kms_addfb_basic: executing
11488 12:42:31.317096 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11489 12:42:31.320193 Opened device: /dev/dri/card0
11490 12:42:31.331204 <14>[ 22.349914] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11491 12:42:31.334234 Starting subtest: invalid-get-prop-any
11492 12:42:31.340604 [1mSubtest invalid-get-<14>[ 22.362129] [IGT] kms_addfb_basic: exiting, ret=0
11493 12:42:31.344249 prop-any: SUCCESS (0.000s)[0m
11494 12:42:31.353776 Test requirement not met in function igt_require<8>[ 22.374388] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11495 12:42:31.354066 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11497 12:42:31.357164 _i915, file ../lib/drmtest.c:721:
11498 12:42:31.360748 Test requirement: is_i915_device(fd)
11499 12:42:31.370044 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11500 12:42:31.373677 Test requirement: is_i915_device(fd)
11501 12:42:31.376787 No KMS driver <14>[ 22.399946] [IGT] kms_addfb_basic: executing
11502 12:42:31.379954 or no outputs, pipes: 8, outputs: 0
11503 12:42:31.386702 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11504 12:42:31.396457 Opened device: /dev/dri/car<14>[ 22.414874] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11505 12:42:31.396543 d0
11506 12:42:31.399584 Starting subtest: invalid-get-prop
11507 12:42:31.406459 [1mSubtest invalid-get-prop<14>[ 22.428008] [IGT] kms_addfb_basic: exiting, ret=0
11508 12:42:31.409491 : SUCCESS (0.000s)[0m
11509 12:42:31.419533 Test requirement not met in function igt_require_i915, f<8>[ 22.440586] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11510 12:42:31.419795 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11512 12:42:31.422575 ile ../lib/drmtest.c:721:
11513 12:42:31.426432 Test requirement: is_i915_device(fd)
11514 12:42:31.432645 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11515 12:42:31.436103 Test requirement: is_i915_device(fd)
11516 12:42:31.442436 No KMS driver or no ou<14>[ 22.465733] [IGT] kms_addfb_basic: executing
11517 12:42:31.445612 tputs, pipes: 8, outputs: 0
11518 12:42:31.452758 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11519 12:42:31.455960 Opened device: /dev/dri/card0
11520 12:42:31.462281 <14>[ 22.480548] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11521 12:42:31.465739 Starting subtest: invalid-set-prop-any
11522 12:42:31.471775 [1mSubtest invalid-set-<14>[ 22.493800] [IGT] kms_addfb_basic: exiting, ret=0
11523 12:42:31.475500 prop-any: SUCCESS (0.000s)[0m
11524 12:42:31.485108 Test requirement not met in function igt_require<8>[ 22.506079] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11525 12:42:31.485358 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11527 12:42:31.488207 _i915, file ../lib/drmtest.c:721:
11528 12:42:31.491981 Test requirement: is_i915_device(fd)
11529 12:42:31.501659 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11530 12:42:31.504830 Test requirement: is_i915_device(fd)
11531 12:42:31.511699 No KMS driver or no outputs, p<14>[ 22.532304] [IGT] kms_addfb_basic: executing
11532 12:42:31.511801 ipes: 8, outputs: 0
11533 12:42:31.517861 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11534 12:42:31.521653 Opened device: /dev/dri/card0
11535 12:42:31.528093 <14>[ 22.548206] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11536 12:42:31.531419 Starting subtest: invalid-set-prop
11537 12:42:31.538158 [1mSubtest invalid-set-prop<14>[ 22.560194] [IGT] kms_addfb_basic: exiting, ret=0
11538 12:42:31.541224 : SUCCESS (0.000s)[0m
11539 12:42:31.551519 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11541 12:42:31.554418 Test requirement not met in function igt_require_i915, f<8>[ 22.572286] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11542 12:42:31.554492 ile ../lib/drmtest.c:721:
11543 12:42:31.558004 Test requirement: is_i915_device(fd)
11544 12:42:31.564167 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11545 12:42:31.567339 Test requirement: is_i915_device(fd)
11546 12:42:31.573950 No KMS driver or no ou<14>[ 22.597426] [IGT] kms_addfb_basic: executing
11547 12:42:31.577592 tputs, pipes: 8, outputs: 0
11548 12:42:31.583777 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11549 12:42:31.587049 Opened device: /dev/dri/card0
11550 12:42:31.593915 <14>[ 22.615044] [IGT] kms_addfb_basic: starting subtest master-rmfb
11551 12:42:31.597178 Starting subtest: master-rmfb
11552 12:42:31.603784 [1mSubtest maste<14>[ 22.624323] [IGT] kms_addfb_basic: exiting, ret=0
11553 12:42:31.606716 r-rmfb: SUCCESS (0.000s)[0m
11554 12:42:31.616727 Test requirement not met in function igt_require_i<8>[ 22.637321] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11555 12:42:31.616981 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11557 12:42:31.620364 915, file ../lib/drmtest.c:721:
11558 12:42:31.623480 Test requirement: is_i915_device(fd)
11559 12:42:31.630443 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11560 12:42:31.633441 Test requirement: is_i915_device(fd)
11561 12:42:31.640139 No KMS driver or no outputs, pip<14>[ 22.663151] [IGT] kms_addfb_basic: executing
11562 12:42:31.643122 es: 8, outputs: 0
11563 12:42:31.650288 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11564 12:42:31.650404 Opened device: /dev/dri/card0
11565 12:42:31.663600 <14>[ 22.682976] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11566 12:42:31.670588 Starting subtest<14>[ 22.690932] [IGT] kms_addfb_basic: exiting, ret=0
11567 12:42:31.670708 : addfb25-modifier-no-flag
11568 12:42:31.683774 [1mSubtest addfb25-modifier-no-flag: SUCCESS (0.000<8>[ 22.703768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11569 12:42:31.683885 s)[0m
11570 12:42:31.684171 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11572 12:42:31.693610 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11573 12:42:31.696726 Test requirement: is_i915_device(fd)
11574 12:42:31.703808 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11575 12:42:31.710025 Test require<14>[ 22.730522] [IGT] kms_addfb_basic: executing
11576 12:42:31.710132 ment: is_i915_device(fd)
11577 12:42:31.716999 No KMS driver or no outputs, pipes: 8, outputs: 0
11578 12:42:31.720100 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11579 12:42:31.723898 Opened device: /dev/dri/card0
11580 12:42:31.730185 <14>[ 22.750427] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11581 12:42:31.733381 Starting subtest: addfb25-bad-modifier
11582 12:42:31.746243 (kms_addfb_basic:439) CRITICAL: Test assertion failure function addfb25_tests, file ../t<14>[ 22.767882] [IGT] kms_addfb_basic: exiting, ret=98
11583 12:42:31.749327 ests/kms_addfb_basic.c:662:
11584 12:42:31.762706 (kms_addfb_basic:439) CRITICAL: Failed assertion: i<8>[ 22.781338] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11585 12:42:31.763003 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11587 12:42:31.775741 gt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11588 12:42:31.778971 (kms_addfb_basic:439) CRITICAL: error: 0 != -1
11589 12:42:31.779080 Stack trace:
11590 12:42:31.785917 #0 ..<14>[ 22.807645] [IGT] kms_addfb_basic: executing
11591 12:42:31.788933 /lib/igt_core.c:1963 __igt_fail_assert()
11592 12:42:31.792531 #1 [<unknown>+0xb6d647e0]
11593 12:42:31.795593 #2 [<unknown>+0xb6d66278]
11594 12:42:31.795691 #3 [<unknown>+0xb6d6167c]
11595 12:42:31.798821 #4 [__libc_start_main+0xe8]
11596 12:42:31.805797 #5 [<unknown>+<14>[ 22.828169] [IGT] kms_addfb_basic: exiting, ret=77
11597 12:42:31.808963 0xb6d616b4]
11598 12:42:31.809064 #6 [<unknown>+0xb6d616b4]
11599 12:42:31.811989 Subtest addfb25-bad-modifier failed.
11600 12:42:31.822048 <8>[ 22.840316] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11601 12:42:31.822144 **** DEBUG ****
11602 12:42:31.822394 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11604 12:42:31.831606 (kms_addfb_basic:439) ioctl_wrappers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
11605 12:42:31.844732 (kms_addfb_basic:439) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:6<14>[ 22.867745] [IGT] kms_addfb_basic: executing
11606 12:42:31.844831 62:
11607 12:42:31.867811 (kms_addfb_basic:439) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2<14>[ 22.888190] [IGT] kms_addfb_basic: exiting, ret=77
11608 12:42:31.867929 )))) << ((0+8)+8)))), (&f)) == -1
11609 12:42:31.880923 (kms_addfb_basic:439) CRITICAL: error: 0 != -<8>[ 22.900500] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11610 12:42:31.881058 1
11611 12:42:31.881343 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11613 12:42:31.884670 (kms_addfb_basic:439) igt_core-INFO: Stack trace:
11614 12:42:31.894081 (kms_addfb_basic:439) igt_core-INFO: #0 ../lib/igt_core.c:1963 __igt_fail_assert()
11615 12:42:31.897728 (kms_addfb_basic:439) igt_core-INFO: #1 [<unknown>+0xb6d647e0]
11616 12:42:31.904393 (kms_addfb_basic:4<14>[ 22.927109] [IGT] kms_addfb_basic: executing
11617 12:42:31.910940 39) igt_core-INFO: #2 [<unknown>+0xb6d66278]
11618 12:42:31.914161 (kms_addfb_basic:439) igt_core-INFO: #3 [<unknown>+0xb6d6167c]
11619 12:42:31.924129 (kms_addfb_basic:439) igt_core-INFO: #4 [__libc_start_main+0<14>[ 22.947527] [IGT] kms_addfb_basic: exiting, ret=77
11620 12:42:31.927250 xe8]
11621 12:42:31.930933 (kms_addfb_basic:439) igt_core-INFO: #5 [<unknown>+0xb6d616b4]
11622 12:42:31.940575 (kms_add<8>[ 22.959736] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11623 12:42:31.940836 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11625 12:42:31.947065 fb_basic:439) igt_core-INFO: #6 [<unknown>+0xb6d616b4]
11626 12:42:31.947148 **** END ****
11627 12:42:31.954076 [1mSubtest addfb25-bad-modifier: FAIL (0.009s)[0m
11628 12:42:31.963707 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721<14>[ 22.986282] [IGT] kms_addfb_basic: executing
11629 12:42:31.963794 :
11630 12:42:31.967213 Test requirement: is_i915_device(fd)
11631 12:42:31.974138 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11632 12:42:31.977023 Test requirement: is_i915_device(fd)
11633 12:42:31.983707 No KMS driver <14>[ 23.006214] [IGT] kms_addfb_basic: exiting, ret=77
11634 12:42:31.986559 or no outputs, pipes: 8, outputs: 0
11635 12:42:31.999862 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Lin<8>[ 23.018391] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11636 12:42:31.999948 ux: 6.1.31 aarch64)
11637 12:42:32.000187 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11639 12:42:32.003621 Opened device: /dev/dri/card0
11640 12:42:32.010249 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11641 12:42:32.013239 Test requirement: is_i915_device(fd)
11642 12:42:32.023114 [1mSubtest addfb25-x-tiled-mismatc<14>[ 23.044236] [IGT] kms_addfb_basic: executing
11643 12:42:32.023199 h-legacy: SKIP (0.000s)[0m
11644 12:42:32.033079 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11645 12:42:32.036157 Test requirement: is_i915_device(fd)
11646 12:42:32.042964 No KMS driver or no output<14>[ 23.063832] [IGT] kms_addfb_basic: exiting, ret=77
11647 12:42:32.046121 s, pipes: 8, outputs: 0
11648 12:42:32.056300 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 a<8>[ 23.076328] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11649 12:42:32.056558 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11651 12:42:32.059446 arch64)
11652 12:42:32.059541 Opened device: /dev/dri/card0
11653 12:42:32.069155 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11654 12:42:32.072635 Test requirement: is_i915_device(fd)
11655 12:42:32.079270 [1mSubtest addfb25-x-tiled-legacy: SKIP (0.000<14>[ 23.102339] [IGT] kms_addfb_basic: executing
11656 12:42:32.082312 s)[0m
11657 12:42:32.088863 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11658 12:42:32.092363 Test requirement: is_i915_device(fd)
11659 12:42:32.102121 No KMS driver or no outputs, pipes: 8, outputs:<14>[ 23.122240] [IGT] kms_addfb_basic: exiting, ret=77
11660 12:42:32.102212 0
11661 12:42:32.105246 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11662 12:42:32.115656 Opened devic<8>[ 23.134535] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11663 12:42:32.115782 e: /dev/dri/card0
11664 12:42:32.116069 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11666 12:42:32.125115 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11667 12:42:32.128813 Test requirement: is_i915_device(fd)
11668 12:42:32.132135 [1mSubtest addfb25-framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11669 12:42:32.138776 Te<14>[ 23.160112] [IGT] kms_addfb_basic: executing
11670 12:42:32.145290 st requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11671 12:42:32.148554 Test requirement: is_i915_device(fd)
11672 12:42:32.151994 No KMS driver or no outputs, pipes: 8, outputs: 0
11673 12:42:32.158305 IGT-Ve<14>[ 23.179975] [IGT] kms_addfb_basic: exiting, ret=77
11674 12:42:32.164628 rsion: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11675 12:42:32.171597 Opened device: /dev/dr<8>[ 23.192514] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11676 12:42:32.171890 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11678 12:42:32.175045 i/card0
11679 12:42:32.181624 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11680 12:42:32.184667 Test requirement: is_i915_device(fd)
11681 12:42:32.194305 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:7<14>[ 23.217815] [IGT] kms_addfb_basic: executing
11682 12:42:32.197941 21:
11683 12:42:32.200950 Test requirement: is_i915_device(fd)
11684 12:42:32.204697 [1mSubtest basic-x-tiled-legacy: SKIP (0.000s)[0m
11685 12:42:32.207833 No KMS driver or no outputs, pipes: 8, outputs: 0
11686 12:42:32.217717 IGT-Version: 1.27.1-g2dd77d6 <14>[ 23.237736] [IGT] kms_addfb_basic: exiting, ret=77
11687 12:42:32.220821 (aarch64) (Linux: 6.1.31 aarch64)
11688 12:42:32.220906 Opened device: /dev/dri/card0
11689 12:42:32.230482 Test requireme<8>[ 23.250164] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11690 12:42:32.230741 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11692 12:42:32.237425 nt not met in function igt_require_i915, file ../lib/drmtest.c:721:
11693 12:42:32.240646 Test requirement: is_i915_device(fd)
11694 12:42:32.247128 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11695 12:42:32.253851 Test requirement: is_i915_device(f<14>[ 23.275568] [IGT] kms_addfb_basic: executing
11696 12:42:32.253962 d)
11697 12:42:32.260295 [1mSubtest framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11698 12:42:32.263553 No KMS driver or no outputs, pipes: 8, outputs: 0
11699 12:42:32.270527 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11700 12:42:32.273648 <14>[ 23.296217] [IGT] kms_addfb_basic: exiting, ret=77
11701 12:42:32.273732
11702 12:42:32.276768 Opened device: /dev/dri/card0
11703 12:42:32.289907 Test requirement not met in function igt_require_i915, file ../l<8>[ 23.308625] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11704 12:42:32.289993 ib/drmtest.c:721:
11705 12:42:32.290233 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11707 12:42:32.293388 Test requirement: is_i915_device(fd)
11708 12:42:32.300042 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11709 12:42:32.302978 Test requirement: is_i915_device(fd)
11710 12:42:32.313383 [1mSubtest tile-pitch-mismatch: SKIP (0.000s)<14>[ 23.335277] [IGT] kms_addfb_basic: executing
11711 12:42:32.313467 [0m
11712 12:42:32.319525 No KMS driver or no outputs, pipes: 8, outputs: 0
11713 12:42:32.322658 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11714 12:42:32.326457 Opened device: /dev/dri/card0
11715 12:42:32.332656 Test requirement not met<14>[ 23.355478] [IGT] kms_addfb_basic: exiting, ret=77
11716 12:42:32.339213 in function igt_require_i915, file ../lib/drmtest.c:721:
11717 12:42:32.342600 Test requirement: is_i915_device(fd)
11718 12:42:32.349378 <8>[ 23.368108] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11719 12:42:32.349463
11720 12:42:32.349702 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11722 12:42:32.356063 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11723 12:42:32.359270 Test requirement: is_i915_device(fd)
11724 12:42:32.362305 [1mSubtest basic-y-tiled-legacy: SKIP (0.000s)[0m
11725 12:42:32.372381 No KMS driver or no outputs, pipes: 8, outputs: 0<14>[ 23.394531] [IGT] kms_addfb_basic: executing
11726 12:42:32.372466
11727 12:42:32.378676 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11728 12:42:32.382518 Opened device: /dev/dri/card0
11729 12:42:32.391966 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:72<14>[ 23.415101] [IGT] kms_addfb_basic: exiting, ret=77
11730 12:42:32.392052 1:
11731 12:42:32.395592 Test requirement: is_i915_device(fd)
11732 12:42:32.408723 Test requirement not met in function i<8>[ 23.427318] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11733 12:42:32.409024 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11735 12:42:32.411801 gt_require_i915, file ../lib/drmtest.c:721:
11736 12:42:32.414782 Test requirement: is_i915_device(fd)
11737 12:42:32.418574 No KMS driver or no outputs, pipes: 8, outputs: 0
11738 12:42:32.421662 [1mSubtest size-max: SKIP (0.000s)[0m
11739 12:42:32.428501 IGT-Version: 1.27.1-g2dd77d6 (aar<14>[ 23.452335] [IGT] kms_addfb_basic: executing
11740 12:42:32.431580 ch64) (Linux: 6.1.31 aarch64)
11741 12:42:32.434742 Opened device: /dev/dri/card0
11742 12:42:32.441632 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11743 12:42:32.451169 Test requirement: is_i915_devic<14>[ 23.472046] [IGT] kms_addfb_basic: exiting, ret=77
11744 12:42:32.451289 e(fd)
11745 12:42:32.464701 Test requirement not met in function igt_require_i915, file ../lib/drmtes<8>[ 23.484202] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
11746 12:42:32.464820 t.c:721:
11747 12:42:32.465093 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11749 12:42:32.467893 Test requirement: is_i915_device(fd)
11750 12:42:32.470804 No KMS driver or no outputs, pipes: 8, outputs: 0
11751 12:42:32.477748 [1mSubtest too-wide: SKIP (0.000s)[0m
11752 12:42:32.480834 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11753 12:42:32.487689 Opened device: /dev/<14>[ 23.509530] [IGT] kms_addfb_basic: executing
11754 12:42:32.487799 dri/card0
11755 12:42:32.497580 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11756 12:42:32.500470 Test requirement: is_i915_device(fd)
11757 12:42:32.507693 Test requirement not met in function igt_req<14>[ 23.530048] [IGT] kms_addfb_basic: exiting, ret=77
11758 12:42:32.510697 uire_i915, file ../lib/drmtest.c:721:
11759 12:42:32.513726 Test requirement: is_i915_device(fd)
11760 12:42:32.524130 No <8>[ 23.542186] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
11761 12:42:32.524461 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11763 12:42:32.527355 KMS driver or no outputs, pipes: 8, outputs: 0
11764 12:42:32.530381 [1mSubtest too-high: SKIP (0.000s)[0m
11765 12:42:32.537275 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11766 12:42:32.540359 Opened device: /dev/dri/card0
11767 12:42:32.546990 Test requirement not met<14>[ 23.568556] [IGT] kms_addfb_basic: executing
11768 12:42:32.550188 in function igt_require_i915, file ../lib/drmtest.c:721:
11769 12:42:32.553214 Test requirement: is_i915_device(fd)
11770 12:42:32.566464 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:72<14>[ 23.588657] [IGT] kms_addfb_basic: exiting, ret=77
11771 12:42:32.566552 1:
11772 12:42:32.570367 Test requirement: is_i915_device(fd)
11773 12:42:32.580316 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11775 12:42:32.583407 No KMS driver or no outputs, pipes: 8,<8>[ 23.600619] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
11776 12:42:32.583520 outputs: 0
11777 12:42:32.586533 [1mSubtest bo-too-small: SKIP (0.000s)[0m
11778 12:42:32.592924 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11779 12:42:32.596245 Opened device: /dev/dri/card0
11780 12:42:32.606183 Test requirement not met in function igt_require_i915, file ../lib/drmt<14>[ 23.627470] [IGT] kms_addfb_basic: executing
11781 12:42:32.606300 est.c:721:
11782 12:42:32.609726 Test requirement: is_i915_device(fd)
11783 12:42:32.616515 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11784 12:42:32.619578 Test requirement: is_i915_device(fd)
11785 12:42:32.626260 No KM<14>[ 23.647979] [IGT] kms_addfb_basic: exiting, ret=77
11786 12:42:32.629343 S driver or no outputs, pipes: 8, outputs: 0
11787 12:42:32.639380 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
11789 12:42:32.642793 [1mSubtest small-bo: SKIP (0.000s<8>[ 23.660369] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
11790 12:42:32.642916 )[0m
11791 12:42:32.645990 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11792 12:42:32.649014 Opened device: /dev/dri/card0
11793 12:42:32.655793 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11794 12:42:32.662666 Test requirement: is_i9<14>[ 23.685913] [IGT] kms_addfb_basic: executing
11795 12:42:32.665557 15_device(fd)
11796 12:42:32.672202 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11797 12:42:32.675405 Test requirement: is_i915_device(fd)
11798 12:42:32.685477 No KMS driver or no outputs, pipes: 8, o<14>[ 23.705790] [IGT] kms_addfb_basic: exiting, ret=77
11799 12:42:32.685563 utputs: 0
11800 12:42:32.688582 [1mSubtest bo-too-small-due-to-tiling: SKIP (0.000s)[0m
11801 12:42:32.698852 IGT-Versio<8>[ 23.718389] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
11802 12:42:32.699113 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
11804 12:42:32.705097 n: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11805 12:42:32.705179 Opened device: /dev/dri/card0
11806 12:42:32.715591 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11807 12:42:32.718595 Test requirement: is_i915_device(fd)
11808 12:42:32.725131 Test requirement n<14>[ 23.745326] [IGT] kms_addfb_basic: executing
11809 12:42:32.728594 ot met in function igt_require_i915, file ../lib/drmtest.c:721:
11810 12:42:32.731716 Test requirement: is_i915_device(fd)
11811 12:42:32.738243 No KMS driver or no outputs, pipes: 8, outputs: 0
11812 12:42:32.744973 [1mSubtest addfb25-y-<14>[ 23.765826] [IGT] kms_addfb_basic: exiting, ret=77
11813 12:42:32.748059 tiled-legacy: SKIP (0.000s)[0m
11814 12:42:32.757655 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: <8>[ 23.778041] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
11815 12:42:32.757938 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
11817 12:42:32.761424 6.1.31 aarch64)
11818 12:42:32.764642 Opened device: <8>[ 23.787508] <LAVA_SIGNAL_TESTSET STOP>
11819 12:42:32.764921 Received signal: <TESTSET> STOP
11820 12:42:32.765023 Closing test_set kms_addfb_basic
11821 12:42:32.767759 /dev/dri/card0
11822 12:42:32.774128 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11823 12:42:32.777793 Test requirement: is_i915_device(fd)
11824 12:42:32.784001 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11825 12:42:32.790805 Test requirement: is_i915_device(fd)<8>[ 23.813911] <LAVA_SIGNAL_TESTSET START kms_atomic>
11826 12:42:32.791098 Received signal: <TESTSET> START kms_atomic
11827 12:42:32.791240 Starting test_set kms_atomic
11828 12:42:32.794023
11829 12:42:32.797715 No KMS driver or no outputs, pipes: 8, outputs: 0
11830 12:42:32.800948 [1mSubtest addfb25-yf-tiled-legacy: SKIP (0.000s)[0m
11831 12:42:32.807264 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11832 12:42:32.810480 Opened device: /dev/dri/card0
11833 12:42:32.814265 Test<14>[ 23.837094] [IGT] kms_atomic: executing
11834 12:42:32.820178 requirement not<14>[ 23.842769] [IGT] kms_atomic: exiting, ret=77
11835 12:42:32.827105 met in function igt_require_i915, file ../lib/drmtest.c:721:
11836 12:42:32.833775 Test requirement:<8>[ 23.854481] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
11837 12:42:32.834055 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
11839 12:42:32.837312 is_i915_device(fd)
11840 12:42:32.843745 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11841 12:42:32.846910 Test requirement: is_i915_device(fd)
11842 12:42:32.853736 No KMS driver or no outputs, pipes: 8, outputs: 0
11843 12:42:32.860387 [1mSubtest addfb25-y-tiled-sma<14>[ 23.881239] [IGT] kms_atomic: executing
11844 12:42:32.863442 ll-legacy: SKIP <14>[ 23.887303] [IGT] kms_atomic: exiting, ret=77
11845 12:42:32.866605 (0.000s)[0m
11846 12:42:32.873469 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11847 12:42:32.880110 Op<8>[ 23.899176] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
11848 12:42:32.880397 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
11850 12:42:32.883525 ened device: /dev/dri/card0
11851 12:42:32.889744 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11852 12:42:32.893011 Test requirement: is_i915_device(fd)
11853 12:42:32.903004 Test requirement not met in function igt_require_i915, fil<14>[ 23.924596] [IGT] kms_atomic: executing
11854 12:42:32.909981 e ../lib/drmtest<14>[ 23.929934] [IGT] kms_atomic: exiting, ret=77
11855 12:42:32.910093 .c:721:
11856 12:42:32.913059 Test requirement: is_i915_device(fd)
11857 12:42:32.922625 No KMS driver or no outputs, pipe<8>[ 23.941442] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
11858 12:42:32.922881 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
11860 12:42:32.926322 s: 8, outputs: 0
11861 12:42:32.929476 [1mSubtest addfb25-4-tiled: SKIP (0.000s)[0m
11862 12:42:32.935769 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11863 12:42:32.939339 Opened device: /dev/dri/card0
11864 12:42:32.942369 No KMS driver or no outputs, pipes: 8, outputs: 0
11865 12:42:32.945835 [1mSubtest <14>[ 23.969440] [IGT] kms_atomic: executing
11866 12:42:32.952658 plane-overlay-le<14>[ 23.975530] [IGT] kms_atomic: exiting, ret=77
11867 12:42:32.955761 gacy: SKIP (0.000s)[0m
11868 12:42:32.968900 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 a<8>[ 23.987833] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
11869 12:42:32.969012 arch64)
11870 12:42:32.969281 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
11872 12:42:32.972586 Opened device: /dev/dri/card0
11873 12:42:32.975744 No KMS driver or no outputs, pipes: 8, outputs: 0
11874 12:42:32.982049 [1mSubtest plane-primary-legacy: SKIP (0.000s)[0m
11875 12:42:32.985662 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11876 12:42:32.992289 Opened device: /<14>[ 24.013852] [IGT] kms_atomic: executing
11877 12:42:32.992400 dev/dri/card0
11878 12:42:32.998809 N<14>[ 24.019867] [IGT] kms_atomic: exiting, ret=77
11879 12:42:33.002050 o KMS driver or no outputs, pipes: 8, outputs: 0
11880 12:42:33.011608 [1mSubtest plane-primary-over<8>[ 24.032287] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
11881 12:42:33.011890 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
11883 12:42:33.015337 lay-mutable-zpos: SKIP (0.000s)[0m
11884 12:42:33.021708 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11885 12:42:33.021811 Opened device: /dev/dri/card0
11886 12:42:33.028428 No KMS driver or no outputs, pipes: 8, outputs: 0
11887 12:42:33.034727 [1mSubtest plane-immutab<14>[ 24.056747] [IGT] kms_atomic: executing
11888 12:42:33.041380 le-zpos: SKIP (0<14>[ 24.061926] [IGT] kms_atomic: exiting, ret=77
11889 12:42:33.041488 .000s)[0m
11890 12:42:33.047864 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11891 12:42:33.054907 Open<8>[ 24.074018] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
11892 12:42:33.055162 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
11894 12:42:33.057757 ed device: /dev/dri/card0
11895 12:42:33.061372 No KMS driver or no outputs, pipes: 8, outputs: 0
11896 12:42:33.064474 [1mSubtest test-only: SKIP (0.000s)[0m
11897 12:42:33.071087 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11898 12:42:33.074783 Opened device: /dev/dri/card0
11899 12:42:33.078056 No KMS dr<14>[ 24.100110] [IGT] kms_atomic: executing
11900 12:42:33.084384 iver or no outpu<14>[ 24.106351] [IGT] kms_atomic: exiting, ret=77
11901 12:42:33.087622 ts, pipes: 8, outputs: 0
11902 12:42:33.091227 [1mSubtest plane-cursor-legacy: SKIP (0.000s)[0m
11903 12:42:33.097576 IG<8>[ 24.118487] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
11904 12:42:33.097856 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
11906 12:42:33.104325 T-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11907 12:42:33.107516 Opened device: /dev/dri/card0
11908 12:42:33.110707 No KMS driver or no outputs, pipes: 8, outputs: 0
11909 12:42:33.117702 [1mSubtest plane-invalid-params: SKIP (0.000s)[0m
11910 12:42:33.120826 <14>[ 24.144905] [IGT] kms_atomic: executing
11911 12:42:33.127213 IGT-Version: 1.2<14>[ 24.149630] [IGT] kms_atomic: exiting, ret=77
11912 12:42:33.130429 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11913 12:42:33.134356 Opened device: /dev/dri/card0
11914 12:42:33.143647 N<8>[ 24.162050] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
11915 12:42:33.143946 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
11917 12:42:33.147313 o KMS driver or no outputs, pipes: 8, outputs: 0
11918 12:42:33.153911 [1mSubtest plane-invalid-params-fence: SKIP (0.000s)[0m
11919 12:42:33.166581 <14>[ 24.188855] [IGT] kms_atomic: executing
11920 12:42:33.173001 IGT-Version: 1.2<14>[ 24.193587] [IGT] kms_atomic: exiting, ret=77
11921 12:42:33.176008 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11922 12:42:33.179743 Opened device: /dev/dri/card0
11923 12:42:33.185986 N<8>[ 24.206030] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
11924 12:42:33.186293 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
11926 12:42:33.189760 o KMS driver or no outputs, pipes: 8, outputs: 0
11927 12:42:33.196094 [1mSubtest crtc-invalid-params: SKIP (0.000s)[0m
11928 12:42:33.209753 <14>[ 24.232130] [IGT] kms_atomic: executing
11929 12:42:33.216678 IGT-Version: 1.2<14>[ 24.236892] [IGT] kms_atomic: exiting, ret=77
11930 12:42:33.219902 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11931 12:42:33.223056 Opened device: /dev/dri/card0
11932 12:42:33.232880 No KMS driver or <8>[ 24.249944] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
11933 12:42:33.232967 no outputs, pipes: 8, outputs: 0
11934 12:42:33.233211 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
11936 12:42:33.239285 [1mSubtest crtc-invalid-params-fence: SKIP (0.000s)[0m
11937 12:42:33.254941 <14>[ 24.277352] [IGT] kms_atomic: executing
11938 12:42:33.261615 IGT-Version: 1.2<14>[ 24.282162] [IGT] kms_atomic: exiting, ret=77
11939 12:42:33.265136 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11940 12:42:33.268050 Opened device: /dev/dri/card0
11941 12:42:33.274745 N<8>[ 24.294377] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
11942 12:42:33.275062 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
11944 12:42:33.278200 o KMS driver or no outputs, pipes: 8, outputs: 0
11945 12:42:33.284735 [1mSubtest atomic-invalid-params: SKIP (0.000s)[0m
11946 12:42:33.297768 <14>[ 24.320223] [IGT] kms_atomic: executing
11947 12:42:33.304624 IGT-Version: 1.2<14>[ 24.324950] [IGT] kms_atomic: exiting, ret=77
11948 12:42:33.307858 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11949 12:42:33.310619 Opened device: /dev/dri/card0
11950 12:42:33.317663 N<8>[ 24.337297] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic_plane_damage RESULT=skip>
11951 12:42:33.317944 Received signal: <TESTCASE> TEST_CASE_ID=atomic_plane_damage RESULT=skip
11953 12:42:33.324505 o KMS driver or no outputs, pipe<8>[ 24.347216] <LAVA_SIGNAL_TESTSET STOP>
11954 12:42:33.324750 Received signal: <TESTSET> STOP
11955 12:42:33.324819 Closing test_set kms_atomic
11956 12:42:33.327641 s: 8, outputs: 0
11957 12:42:33.330663 [1mSubtest atomic_plane_damage: SKIP (0.000s)[0m
11958 12:42:33.350621 <8>[ 24.373029] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
11959 12:42:33.350887 Received signal: <TESTSET> START kms_flip_event_leak
11960 12:42:33.350958 Starting test_set kms_flip_event_leak
11961 12:42:33.374452 <14>[ 24.397063] [IGT] kms_flip_event_leak: executing
11962 12:42:33.381046 IGT-Version: 1.2<14>[ 24.402604] [IGT] kms_flip_event_leak: exiting, ret=77
11963 12:42:33.384776 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11964 12:42:33.387704 Opened device: /dev/dri/card0
11965 12:42:33.394153 N<8>[ 24.415873] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
11966 12:42:33.394406 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
11968 12:42:33.401158 o KMS driver or no outputs, pipe<8>[ 24.424369] <LAVA_SIGNAL_TESTSET STOP>
11969 12:42:33.401406 Received signal: <TESTSET> STOP
11970 12:42:33.401474 Closing test_set kms_flip_event_leak
11971 12:42:33.404307 s: 8, outputs: 0
11972 12:42:33.407361 [1mSubtest basic: SKIP (0.000s)[0m
11973 12:42:33.428746 <8>[ 24.450937] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
11974 12:42:33.429010 Received signal: <TESTSET> START kms_prop_blob
11975 12:42:33.429083 Starting test_set kms_prop_blob
11976 12:42:33.452095 <14>[ 24.474220] [IGT] kms_prop_blob: executing
11977 12:42:33.458063 IGT-Version: 1.2<14>[ 24.479579] [IGT] kms_prop_blob: starting subtest basic
11978 12:42:33.464849 7.1-g2dd77d6 (aa<14>[ 24.485951] [IGT] kms_prop_blob: exiting, ret=0
11979 12:42:33.468089 rch64) (Linux: 6.1.31 aarch64)
11980 12:42:33.471838 Opened device: /dev/dri/card0
11981 12:42:33.471923 Starting subtest: basic
11982 12:42:33.478311 [1mSubt<8>[ 24.499539] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11983 12:42:33.478569 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11985 12:42:33.481256 est basic: SUCCESS (0.000s)[0m
11986 12:42:33.503071 <14>[ 24.525271] [IGT] kms_prop_blob: executing
11987 12:42:33.509344 IGT-Version: 1.2<14>[ 24.530139] [IGT] kms_prop_blob: starting subtest blob-prop-core
11988 12:42:33.516118 7.1-g2dd77d6 (aa<14>[ 24.537809] [IGT] kms_prop_blob: exiting, ret=0
11989 12:42:33.519153 rch64) (Linux: 6.1.31 aarch64)
11990 12:42:33.522798 Opened device: /dev/dri/card0
11991 12:42:33.529431 Starting subtest:<8>[ 24.550317] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
11992 12:42:33.529690 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
11994 12:42:33.532454 blob-prop-core
11995 12:42:33.536026 [1mSubtest blob-prop-core: SUCCESS (0.000s)[0m
11996 12:42:33.554052 <14>[ 24.575880] [IGT] kms_prop_blob: executing
11997 12:42:33.560358 IGT-Version: 1.2<14>[ 24.580834] [IGT] kms_prop_blob: starting subtest blob-prop-validate
11998 12:42:33.566927 7.1-g2dd77d6 (aa<14>[ 24.588978] [IGT] kms_prop_blob: exiting, ret=0
11999 12:42:33.570539 rch64) (Linux: 6.1.31 aarch64)
12000 12:42:33.573741 Opened device: /dev/dri/card0
12001 12:42:33.583696 Starting subtest:<8>[ 24.601552] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
12002 12:42:33.584189 blob-prop-validate
12003 12:42:33.584824 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
12005 12:42:33.590057 [1mSubtest blob-prop-validate: SUCCESS (0.000s)[0m
12006 12:42:33.605499 <14>[ 24.627486] [IGT] kms_prop_blob: executing
12007 12:42:33.612150 IGT-Version: 1.2<14>[ 24.632333] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
12008 12:42:33.618110 7.1-g2dd77d6 (aa<14>[ 24.640820] [IGT] kms_prop_blob: exiting, ret=0
12009 12:42:33.621967 rch64) (Linux: 6.1.31 aarch64)
12010 12:42:33.625067 Opened device: /dev/dri/card0
12011 12:42:33.634726 Starting subtest:<8>[ 24.652940] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
12012 12:42:33.635455 blob-prop-lifetime
12013 12:42:33.636350 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
12015 12:42:33.641219 [1mSubtest blob-prop-lifetime: SUCCESS (0.000s)[0m
12016 12:42:33.656774 <14>[ 24.679062] [IGT] kms_prop_blob: executing
12017 12:42:33.663817 IGT-Version: 1.2<14>[ 24.683900] [IGT] kms_prop_blob: starting subtest blob-multiple
12018 12:42:33.669758 7.1-g2dd77d6 (aa<14>[ 24.691913] [IGT] kms_prop_blob: exiting, ret=0
12019 12:42:33.673579 rch64) (Linux: 6.1.31 aarch64)
12020 12:42:33.676564 Opened device: /dev/dri/card0
12021 12:42:33.683538 Starting subtest:<8>[ 24.704240] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
12022 12:42:33.684273 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
12024 12:42:33.686698 blob-multiple
12025 12:42:33.689687 [1mSubtest blob-multiple: SUCCESS (0.000s)[0m
12026 12:42:33.707581 <14>[ 24.729639] [IGT] kms_prop_blob: executing
12027 12:42:33.714206 IGT-Version: 1.2<14>[ 24.734717] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
12028 12:42:33.720777 7.1-g2dd77d6 (aa<14>[ 24.742944] [IGT] kms_prop_blob: exiting, ret=0
12029 12:42:33.723760 rch64) (Linux: 6.1.31 aarch64)
12030 12:42:33.726936 Opened device: /dev/dri/card0
12031 12:42:33.736800 Starting subtest:<8>[ 24.755703] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
12032 12:42:33.736886 invalid-get-prop-any
12033 12:42:33.737127 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
12035 12:42:33.743322 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
12036 12:42:33.759331 <14>[ 24.781819] [IGT] kms_prop_blob: executing
12037 12:42:33.765704 IGT-Version: 1.2<14>[ 24.786766] [IGT] kms_prop_blob: starting subtest invalid-get-prop
12038 12:42:33.772477 7.1-g2dd77d6 (aa<14>[ 24.794662] [IGT] kms_prop_blob: exiting, ret=0
12039 12:42:33.775743 rch64) (Linux: 6.1.31 aarch64)
12040 12:42:33.779013 Opened device: /dev/dri/card0
12041 12:42:33.785882 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
12043 12:42:33.788817 Starting subtest:<8>[ 24.807185] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
12044 12:42:33.788894 invalid-get-prop
12045 12:42:33.791950 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
12046 12:42:33.810544 <14>[ 24.833341] [IGT] kms_prop_blob: executing
12047 12:42:33.817349 IGT-Version: 1.2<14>[ 24.838214] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
12048 12:42:33.823816 7.1-g2dd77d6 (aa<14>[ 24.846614] [IGT] kms_prop_blob: exiting, ret=0
12049 12:42:33.827322 rch64) (Linux: 6.1.31 aarch64)
12050 12:42:33.830302 Opened device: /dev/dri/card0
12051 12:42:33.840344 Starting subtest:<8>[ 24.858643] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
12052 12:42:33.840458 invalid-set-prop-any
12053 12:42:33.840728 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
12055 12:42:33.846762 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
12056 12:42:33.863019 <14>[ 24.885392] [IGT] kms_prop_blob: executing
12057 12:42:33.869168 IGT-Version: 1.2<14>[ 24.890284] [IGT] kms_prop_blob: starting subtest invalid-set-prop
12058 12:42:33.875842 7.1-g2dd77d6 (aa<14>[ 24.898443] [IGT] kms_prop_blob: exiting, ret=0
12059 12:42:33.879001 rch64) (Linux: 6.1.31 aarch64)
12060 12:42:33.882275 Opened device: /dev/dri/card0
12061 12:42:33.892096 Starting subtest:<8>[ 24.910364] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
12062 12:42:33.892186 invalid-set-prop
12063 12:42:33.892426 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
12065 12:42:33.899109 [1mSubtest i<8>[ 24.920200] <LAVA_SIGNAL_TESTSET STOP>
12066 12:42:33.899370 Received signal: <TESTSET> STOP
12067 12:42:33.899440 Closing test_set kms_prop_blob
12068 12:42:33.902091 nvalid-set-prop: SUCCESS (0.000s)[0m
12069 12:42:33.923803 <8>[ 24.946245] <LAVA_SIGNAL_TESTSET START kms_setmode>
12070 12:42:33.924096 Received signal: <TESTSET> START kms_setmode
12071 12:42:33.924167 Starting test_set kms_setmode
12072 12:42:33.946405 <14>[ 24.968840] [IGT] kms_setmode: executing
12073 12:42:33.952700 IGT-Version: 1.2<14>[ 24.973661] [IGT] kms_setmode: starting subtest basic
12074 12:42:33.959450 7.1-g2dd77d6 (aa<14>[ 24.980377] [IGT] kms_setmode: exiting, ret=77
12075 12:42:33.962730 rch64) (Linux: 6.1.31 aarch64)
12076 12:42:33.962861 Opened device: /dev/dri/card0
12077 12:42:33.972914 Starting subtest:<8>[ 24.992540] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12078 12:42:33.972997 basic
12079 12:42:33.973264 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12081 12:42:33.976068 No dynamic tests executed.
12082 12:42:33.979063 [1mSubtest basic: SKIP (0.000s)[0m
12083 12:42:33.995317 <14>[ 25.017700] [IGT] kms_setmode: executing
12084 12:42:34.001649 IGT-Version: 1.2<14>[ 25.022586] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
12085 12:42:34.008550 7.1-g2dd77d6 (aa<14>[ 25.031015] [IGT] kms_setmode: exiting, ret=77
12086 12:42:34.011591 rch64) (Linux: 6.1.31 aarch64)
12087 12:42:34.015212 Opened device: /dev/dri/card0
12088 12:42:34.024859 Starting subtest:<8>[ 25.043471] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
12089 12:42:34.025110 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
12091 12:42:34.027893 basic-clone-single-crtc
12092 12:42:34.027968 No dynamic tests executed.
12093 12:42:34.034288 [1mSubtest basic-clone-single-crtc: SKIP (0.000s)[0m
12094 12:42:34.047432 <14>[ 25.070121] [IGT] kms_setmode: executing
12095 12:42:34.054377 IGT-Version: 1.2<14>[ 25.075010] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
12096 12:42:34.060628 7.1-g2dd77d6 (aa<14>[ 25.083455] [IGT] kms_setmode: exiting, ret=77
12097 12:42:34.064258 rch64) (Linux: 6.1.31 aarch64)
12098 12:42:34.067231 Opened device: /dev/dri/card0
12099 12:42:34.077038 Starting subtest:<8>[ 25.095898] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
12100 12:42:34.077322 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
12102 12:42:34.080242 invalid-clone-single-crtc
12103 12:42:34.080315 No dynamic tests executed.
12104 12:42:34.086891 [1mSubtest invalid-clone-single-crtc: SKIP (0.000s)[0m
12105 12:42:34.100573 <14>[ 25.122917] [IGT] kms_setmode: executing
12106 12:42:34.106754 IGT-Version: 1.2<14>[ 25.127844] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
12107 12:42:34.113645 7.1-g2dd77d6 (aa<14>[ 25.136230] [IGT] kms_setmode: exiting, ret=77
12108 12:42:34.116853 rch64) (Linux: 6.1.31 aarch64)
12109 12:42:34.120458 Opened device: /dev/dri/card0
12110 12:42:34.130095 Starting subtest:<8>[ 25.148749] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
12111 12:42:34.130371 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
12113 12:42:34.133572 invalid-clone-exclusive-crtc
12114 12:42:34.136885 No dynamic tests executed.
12115 12:42:34.139742 [1mSubtest invalid-clone-exclusive-crtc: SKIP (0.000s)[0m
12116 12:42:34.153188 <14>[ 25.175920] [IGT] kms_setmode: executing
12117 12:42:34.159961 IGT-Version: 1.2<14>[ 25.180789] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
12118 12:42:34.166214 7.1-g2dd77d6 (aa<14>[ 25.188886] [IGT] kms_setmode: exiting, ret=77
12119 12:42:34.169907 rch64) (Linux: 6.1.31 aarch64)
12120 12:42:34.172790 Opened device: /dev/dri/card0
12121 12:42:34.182737 Starting subtest:<8>[ 25.201443] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
12122 12:42:34.182864 clone-exclusive-crtc
12123 12:42:34.183136 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
12125 12:42:34.186429 No dynamic tests executed.
12126 12:42:34.189499 [1mSubtest clone-exclusive-crtc: SKIP (0.000s)[0m
12127 12:42:34.205168 <14>[ 25.227922] [IGT] kms_setmode: executing
12128 12:42:34.215141 IGT-Version: 1.2<14>[ 25.232842] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
12129 12:42:34.222046 7.1-g2dd77d6 (aa<14>[ 25.241945] [IGT] kms_setmode: exiting, ret=77
12130 12:42:34.222168 rch64) (Linux: 6.1.31 aarch64)
12131 12:42:34.225218 Opened device: /dev/dri/card0
12132 12:42:34.234865 Starting subtest:<8>[ 25.254413] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
12133 12:42:34.235141 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12135 12:42:34.241616 invalid-clone-single-crtc-steal<8>[ 25.265631] <LAVA_SIGNAL_TESTSET STOP>
12136 12:42:34.241901 Received signal: <TESTSET> STOP
12137 12:42:34.241998 Closing test_set kms_setmode
12138 12:42:34.245161 ing
12139 12:42:34.245266 No dynamic tests executed.
12140 12:42:34.251431 [1mSubtest invalid-clone-single-crtc-stealing: SKIP (0.000s)[0m
12141 12:42:34.269512 <8>[ 25.291946] <LAVA_SIGNAL_TESTSET START kms_vblank>
12142 12:42:34.269810 Received signal: <TESTSET> START kms_vblank
12143 12:42:34.269912 Starting test_set kms_vblank
12144 12:42:34.292813 <14>[ 25.315276] [IGT] kms_vblank: executing
12145 12:42:34.299519 IGT-Version: 1.2<14>[ 25.320301] [IGT] kms_vblank: exiting, ret=77
12146 12:42:34.302699 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12147 12:42:34.305767 Opened device: /dev/dri/card0
12148 12:42:34.312623 N<8>[ 25.332273] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
12149 12:42:34.312908 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12151 12:42:34.315894 o KMS driver or no outputs, pipes: 8, outputs: 0
12152 12:42:34.319061 [1mSubtest invalid: SKIP (0.000s)[0m
12153 12:42:34.334643 <14>[ 25.357307] [IGT] kms_vblank: executing
12154 12:42:34.341384 IGT-Version: 1.2<14>[ 25.362350] [IGT] kms_vblank: exiting, ret=77
12155 12:42:34.344307 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12156 12:42:34.347669 Opened device: /dev/dri/card0
12157 12:42:34.354614 N<8>[ 25.374284] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
12158 12:42:34.354920 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12160 12:42:34.357672 o KMS driver or no outputs, pipes: 8, outputs: 0
12161 12:42:34.361124 [1mSubtest crtc-id: SKIP (0.000s)[0m
12162 12:42:34.377121 <14>[ 25.399437] [IGT] kms_vblank: executing
12163 12:42:34.383322 IGT-Version: 1.2<14>[ 25.404524] [IGT] kms_vblank: exiting, ret=77
12164 12:42:34.387140 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12165 12:42:34.389909 Opened device: /dev/dri/card0
12166 12:42:34.396848 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip
12168 12:42:34.399777 No KMS driver or <8>[ 25.416907] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip>
12169 12:42:34.399887 no outputs, pipes: 8, outputs: 0
12170 12:42:34.406621 [1mSubtest pipe-A-accuracy-idle: SKIP (0.000s)[0m
12171 12:42:34.421110 <14>[ 25.443915] [IGT] kms_vblank: executing
12172 12:42:34.427997 IGT-Version: 1.2<14>[ 25.448887] [IGT] kms_vblank: exiting, ret=77
12173 12:42:34.431124 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12174 12:42:34.434740 Opened device: /dev/dri/card0
12175 12:42:34.441005 N<8>[ 25.460984] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle RESULT=skip>
12176 12:42:34.441271 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle RESULT=skip
12178 12:42:34.444167 o KMS driver or no outputs, pipes: 8, outputs: 0
12179 12:42:34.450814 [1mSubtest pipe-A-query-idle: SKIP (0.000s)[0m
12180 12:42:34.464276 <14>[ 25.486845] [IGT] kms_vblank: executing
12181 12:42:34.470733 IGT-Version: 1.2<14>[ 25.491868] [IGT] kms_vblank: exiting, ret=77
12182 12:42:34.474340 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12183 12:42:34.477212 Opened device: /dev/dri/card0
12184 12:42:34.483835 N<8>[ 25.504107] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip>
12185 12:42:34.484099 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip
12187 12:42:34.487443 o KMS driver or no outputs, pipes: 8, outputs: 0
12188 12:42:34.493728 [1mSubtest pipe-A-query-idle-hang: SKIP (0.000s)[0m
12189 12:42:34.507767 <14>[ 25.530465] [IGT] kms_vblank: executing
12190 12:42:34.514620 IGT-Version: 1.2<14>[ 25.535788] [IGT] kms_vblank: exiting, ret=77
12191 12:42:34.517751 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12192 12:42:34.520907 Opened device: /dev/dri/card0
12193 12:42:34.527676 N<8>[ 25.547708] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked RESULT=skip>
12194 12:42:34.527939 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked RESULT=skip
12196 12:42:34.530747 o KMS driver or no outputs, pipes: 8, outputs: 0
12197 12:42:34.537041 [1mSubtest pipe-A-query-forked: SKIP (0.000s)[0m
12198 12:42:34.550276 <14>[ 25.572918] [IGT] kms_vblank: executing
12199 12:42:34.556626 IGT-Version: 1.2<14>[ 25.577908] [IGT] kms_vblank: exiting, ret=77
12200 12:42:34.560266 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12201 12:42:34.563230 Opened device: /dev/dri/card0
12202 12:42:34.569763 N<8>[ 25.590045] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip>
12203 12:42:34.570017 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip
12205 12:42:34.576395 o KMS driver or no outputs, pipes: 8, outputs: 0
12206 12:42:34.580096 [1mSubtest pipe-A-query-forked-hang: SKIP (0.000s)[0m
12207 12:42:34.593004 <14>[ 25.615666] [IGT] kms_vblank: executing
12208 12:42:34.599714 IGT-Version: 1.2<14>[ 25.620689] [IGT] kms_vblank: exiting, ret=77
12209 12:42:34.602640 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12210 12:42:34.606182 Opened device: /dev/dri/card0
12211 12:42:34.612936 N<8>[ 25.632662] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy RESULT=skip>
12212 12:42:34.613195 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy RESULT=skip
12214 12:42:34.615941 o KMS driver or no outputs, pipes: 8, outputs: 0
12215 12:42:34.622902 [1mSubtest pipe-A-query-busy: SKIP (0.000s)[0m
12216 12:42:34.635288 <14>[ 25.657911] [IGT] kms_vblank: executing
12217 12:42:34.641446 IGT-Version: 1.2<14>[ 25.662942] [IGT] kms_vblank: exiting, ret=77
12218 12:42:34.645308 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12219 12:42:34.648491 Opened device: /dev/dri/card0
12220 12:42:34.654773 N<8>[ 25.674701] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip>
12221 12:42:34.655058 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip
12223 12:42:34.658054 o KMS driver or no outputs, pipes: 8, outputs: 0
12224 12:42:34.665005 [1mSubtest pipe-A-query-busy-hang: SKIP (0.000s)[0m
12225 12:42:34.678186 <14>[ 25.700773] [IGT] kms_vblank: executing
12226 12:42:34.684805 IGT-Version: 1.2<14>[ 25.705746] [IGT] kms_vblank: exiting, ret=77
12227 12:42:34.687941 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12228 12:42:34.691516 Opened device: /dev/dri/card0
12229 12:42:34.697986 N<8>[ 25.717699] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip>
12230 12:42:34.698273 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip
12232 12:42:34.704236 o KMS driver or no outputs, pipes: 8, outputs: 0
12233 12:42:34.707885 [1mSubtest pipe-A-query-forked-busy: SKIP (0.000s)[0m
12234 12:42:34.721696 <14>[ 25.744152] [IGT] kms_vblank: executing
12235 12:42:34.728004 IGT-Version: 1.2<14>[ 25.749323] [IGT] kms_vblank: exiting, ret=77
12236 12:42:34.731799 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12237 12:42:34.734944 Opened device: /dev/dri/card0
12238 12:42:34.741341 N<8>[ 25.761130] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip>
12239 12:42:34.741633 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip
12241 12:42:34.748241 o KMS driver or no outputs, pipes: 8, outputs: 0
12242 12:42:34.751390 [1mSubtest pipe-A-query-forked-busy-hang: SKIP (0.000s)[0m
12243 12:42:34.765190 <14>[ 25.787859] [IGT] kms_vblank: executing
12244 12:42:34.772068 IGT-Version: 1.2<14>[ 25.792811] [IGT] kms_vblank: exiting, ret=77
12245 12:42:34.775130 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12246 12:42:34.778580 Opened device: /dev/dri/card0
12247 12:42:34.785150 N<8>[ 25.804713] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle RESULT=skip>
12248 12:42:34.785407 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle RESULT=skip
12250 12:42:34.788098 o KMS driver or no outputs, pipes: 8, outputs: 0
12251 12:42:34.794734 [1mSubtest pipe-A-wait-idle: SKIP (0.000s)[0m
12252 12:42:34.808194 <14>[ 25.830908] [IGT] kms_vblank: executing
12253 12:42:34.814736 IGT-Version: 1.2<14>[ 25.835975] [IGT] kms_vblank: exiting, ret=77
12254 12:42:34.818351 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12255 12:42:34.821393 Opened device: /dev/dri/card0
12256 12:42:34.828086 N<8>[ 25.848165] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip>
12257 12:42:34.828363 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip
12259 12:42:34.831203 o KMS driver or no outputs, pipes: 8, outputs: 0
12260 12:42:34.838027 [1mSubtest pipe-A-wait-idle-hang: SKIP (0.000s)[0m
12261 12:42:34.852050 <14>[ 25.874321] [IGT] kms_vblank: executing
12262 12:42:34.858163 IGT-Version: 1.2<14>[ 25.879439] [IGT] kms_vblank: exiting, ret=77
12263 12:42:34.861375 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12264 12:42:34.865115 Opened device: /dev/dri/card0
12265 12:42:34.871358 N<8>[ 25.891155] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked RESULT=skip>
12266 12:42:34.871608 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked RESULT=skip
12268 12:42:34.874562 o KMS driver or no outputs, pipes: 8, outputs: 0
12269 12:42:34.881307 [1mSubtest pipe-A-wait-forked: SKIP (0.000s)[0m
12270 12:42:34.893975 <14>[ 25.916604] [IGT] kms_vblank: executing
12271 12:42:34.900588 IGT-Version: 1.2<14>[ 25.921588] [IGT] kms_vblank: exiting, ret=77
12272 12:42:34.904148 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12273 12:42:34.907035 Opened device: /dev/dri/card0
12274 12:42:34.913627 N<8>[ 25.933527] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip>
12275 12:42:34.913922 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip
12277 12:42:34.917368 o KMS driver or no outputs, pipes: 8, outputs: 0
12278 12:42:34.923810 [1mSubtest pipe-A-wait-forked-hang: SKIP (0.000s)[0m
12279 12:42:34.937237 <14>[ 25.959777] [IGT] kms_vblank: executing
12280 12:42:34.943572 IGT-Version: 1.2<14>[ 25.964945] [IGT] kms_vblank: exiting, ret=77
12281 12:42:34.947383 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12282 12:42:34.950507 Opened device: /dev/dri/card0
12283 12:42:34.956695 N<8>[ 25.977039] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy RESULT=skip>
12284 12:42:34.956953 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy RESULT=skip
12286 12:42:34.960424 o KMS driver or no outputs, pipes: 8, outputs: 0
12287 12:42:34.966519 [1mSubtest pipe-A-wait-busy: SKIP (0.000s)[0m
12288 12:42:34.980306 <14>[ 26.002906] [IGT] kms_vblank: executing
12289 12:42:34.987218 IGT-Version: 1.2<14>[ 26.007922] [IGT] kms_vblank: exiting, ret=77
12290 12:42:34.990342 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12291 12:42:34.993499 Opened device: /dev/dri/card0
12292 12:42:35.000010 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip
12294 12:42:35.003145 No KMS driver or <8>[ 26.020488] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip>
12295 12:42:35.003234 no outputs, pipes: 8, outputs: 0
12296 12:42:35.009649 [1mSubtest pipe-A-wait-busy-hang: SKIP (0.000s)[0m
12297 12:42:35.024645 <14>[ 26.046996] [IGT] kms_vblank: executing
12298 12:42:35.030687 IGT-Version: 1.2<14>[ 26.051985] [IGT] kms_vblank: exiting, ret=77
12299 12:42:35.034284 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12300 12:42:35.037431 Opened device: /dev/dri/card0
12301 12:42:35.044034 N<8>[ 26.063970] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip>
12302 12:42:35.044299 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip
12304 12:42:35.050353 o KMS driver or no outputs, pipes: 8, outputs: 0
12305 12:42:35.053487 [1mSubtest pipe-A-wait-forked-busy: SKIP (0.000s)[0m
12306 12:42:35.067831 <14>[ 26.090203] [IGT] kms_vblank: executing
12307 12:42:35.074070 IGT-Version: 1.2<14>[ 26.095532] [IGT] kms_vblank: exiting, ret=77
12308 12:42:35.077213 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12309 12:42:35.081018 Opened device: /dev/dri/card0
12310 12:42:35.087366 N<8>[ 26.107352] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip>
12311 12:42:35.087623 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip
12313 12:42:35.093524 o KMS driver or no outputs, pipes: 8, outputs: 0
12314 12:42:35.096681 [1mSubtest pipe-A-wait-forked-busy-hang: SKIP (0.000s)[0m
12315 12:42:35.111604 <14>[ 26.134274] [IGT] kms_vblank: executing
12316 12:42:35.118339 IGT-Version: 1.2<14>[ 26.139528] [IGT] kms_vblank: exiting, ret=77
12317 12:42:35.121297 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12318 12:42:35.124652 Opened device: /dev/dri/card0
12319 12:42:35.131304 N<8>[ 26.151494] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip>
12320 12:42:35.131561 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip
12322 12:42:35.137773 o KMS driver or no outputs, pipes: 8, outputs: 0
12323 12:42:35.141456 [1mSubtest pipe-A-ts-continuation-idle: SKIP (0.000s)[0m
12324 12:42:35.154809 <14>[ 26.177490] [IGT] kms_vblank: executing
12325 12:42:35.161570 IGT-Version: 1.2<14>[ 26.182491] [IGT] kms_vblank: exiting, ret=77
12326 12:42:35.164541 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12327 12:42:35.168403 Opened device: /dev/dri/card0
12328 12:42:35.174672 N<8>[ 26.194407] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip>
12329 12:42:35.174958 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip
12331 12:42:35.181143 o KMS driver or no outputs, pipes: 8, outputs: 0
12332 12:42:35.184774 [1mSubtest pipe-A-ts-continuation-idle-hang: SKIP (0.000s)[0m
12333 12:42:35.199211 <14>[ 26.221711] [IGT] kms_vblank: executing
12334 12:42:35.205456 IGT-Version: 1.2<14>[ 26.226812] [IGT] kms_vblank: exiting, ret=77
12335 12:42:35.209097 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12336 12:42:35.212253 Opened device: /dev/dri/card0
12337 12:42:35.218799 N<8>[ 26.238885] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip>
12338 12:42:35.219082 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip
12340 12:42:35.225075 o KMS driver or no outputs, pipes: 8, outputs: 0
12341 12:42:35.228416 [1mSubtest pipe-A-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12342 12:42:35.242346 <14>[ 26.265267] [IGT] kms_vblank: executing
12343 12:42:35.249405 IGT-Version: 1.2<14>[ 26.270347] [IGT] kms_vblank: exiting, ret=77
12344 12:42:35.252502 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12345 12:42:35.255652 Opened device: /dev/dri/card0
12346 12:42:35.262498 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip
12348 12:42:35.265493 N<8>[ 26.282301] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip>
12349 12:42:35.268618 o KMS driver or no outputs, pipes: 8, outputs: 0
12350 12:42:35.275569 [1mSubtest pipe-A-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12351 12:42:35.286746 <14>[ 26.309325] [IGT] kms_vblank: executing
12352 12:42:35.293069 IGT-Version: 1.2<14>[ 26.314328] [IGT] kms_vblank: exiting, ret=77
12353 12:42:35.296224 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12354 12:42:35.299923 Opened device: /dev/dri/card0
12355 12:42:35.306416 N<8>[ 26.326341] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip>
12356 12:42:35.306705 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip
12358 12:42:35.312931 o KMS driver or no outputs, pipes: 8, outputs: 0
12359 12:42:35.316104 [1mSubtest pipe-A-ts-continuation-suspend: SKIP (0.000s)[0m
12360 12:42:35.330079 <14>[ 26.352752] [IGT] kms_vblank: executing
12361 12:42:35.336621 IGT-Version: 1.2<14>[ 26.357745] [IGT] kms_vblank: exiting, ret=77
12362 12:42:35.340197 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12363 12:42:35.343022 Opened device: /dev/dri/card0
12364 12:42:35.350026 N<8>[ 26.369763] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip>
12365 12:42:35.350291 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip
12367 12:42:35.356301 o KMS driver or no outputs, pipes: 8, outputs: 0
12368 12:42:35.359753 [1mSubtest pipe-A-ts-continuation-modeset: SKIP (0.000s)[0m
12369 12:42:35.373589 <14>[ 26.396279] [IGT] kms_vblank: executing
12370 12:42:35.380371 IGT-Version: 1.2<14>[ 26.401278] [IGT] kms_vblank: exiting, ret=77
12371 12:42:35.383464 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12372 12:42:35.386748 Opened device: /dev/dri/card0
12373 12:42:35.393652 N<8>[ 26.413483] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip>
12374 12:42:35.393936 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip
12376 12:42:35.399819 o KMS driver or no outputs, pipes: 8, outputs: 0
12377 12:42:35.406770 [1mSubtest pipe-A-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12378 12:42:35.418536 <14>[ 26.441123] [IGT] kms_vblank: executing
12379 12:42:35.425297 IGT-Version: 1.2<14>[ 26.446191] [IGT] kms_vblank: exiting, ret=77
12380 12:42:35.428364 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12381 12:42:35.431387 Opened device: /dev/dri/card0
12382 12:42:35.438126 N<8>[ 26.458373] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip>
12383 12:42:35.438406 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip
12385 12:42:35.444762 o KMS driver or no outputs, pipes: 8, outputs: 0
12386 12:42:35.451173 [1mSubtest pipe-A-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12387 12:42:35.462418 <14>[ 26.484725] [IGT] kms_vblank: executing
12388 12:42:35.468429 IGT-Version: 1.2<14>[ 26.489830] [IGT] kms_vblank: exiting, ret=77
12389 12:42:35.471797 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12390 12:42:35.475272 Opened device: /dev/dri/card0
12391 12:42:35.481581 N<8>[ 26.501785] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip>
12392 12:42:35.481864 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip
12394 12:42:35.485469 o KMS driver or no outputs, pipes: 8, outputs: 0
12395 12:42:35.491735 [1mSubtest pipe-B-accuracy-idle: SKIP (0.000s)[0m
12396 12:42:35.504406 <14>[ 26.527238] [IGT] kms_vblank: executing
12397 12:42:35.511396 IGT-Version: 1.2<14>[ 26.532351] [IGT] kms_vblank: exiting, ret=77
12398 12:42:35.514345 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12399 12:42:35.518063 Opened device: /dev/dri/card0
12400 12:42:35.524256 N<8>[ 26.544462] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle RESULT=skip>
12401 12:42:35.524510 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle RESULT=skip
12403 12:42:35.527330 o KMS driver or no outputs, pipes: 8, outputs: 0
12404 12:42:35.533943 [1mSubtest pipe-B-query-idle: SKIP (0.000s)[0m
12405 12:42:35.547565 <14>[ 26.570360] [IGT] kms_vblank: executing
12406 12:42:35.554473 IGT-Version: 1.2<14>[ 26.575546] [IGT] kms_vblank: exiting, ret=77
12407 12:42:35.557343 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12408 12:42:35.560813 Opened device: /dev/dri/card0
12409 12:42:35.567601 N<8>[ 26.587273] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip>
12410 12:42:35.567871 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip
12412 12:42:35.570592 o KMS driver or no outputs, pipes: 8, outputs: 0
12413 12:42:35.577195 [1mSubtest pipe-B-query-idle-hang: SKIP (0.000s)[0m
12414 12:42:35.590102 <14>[ 26.612948] [IGT] kms_vblank: executing
12415 12:42:35.596936 IGT-Version: 1.2<14>[ 26.617917] [IGT] kms_vblank: exiting, ret=77
12416 12:42:35.600004 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12417 12:42:35.603717 Opened device: /dev/dri/card0
12418 12:42:35.610074 N<8>[ 26.629963] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked RESULT=skip>
12419 12:42:35.610328 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked RESULT=skip
12421 12:42:35.613207 o KMS driver or no outputs, pipes: 8, outputs: 0
12422 12:42:35.619551 [1mSubtest pipe-B-query-forked: SKIP (0.000s)[0m
12423 12:42:35.633229 <14>[ 26.655903] [IGT] kms_vblank: executing
12424 12:42:35.639785 IGT-Version: 1.2<14>[ 26.660873] [IGT] kms_vblank: exiting, ret=77
12425 12:42:35.643004 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12426 12:42:35.646130 Opened device: /dev/dri/card0
12427 12:42:35.653109 N<8>[ 26.673163] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip>
12428 12:42:35.653364 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip
12430 12:42:35.659790 o KMS driver or no outputs, pipes: 8, outputs: 0
12431 12:42:35.663123 [1mSubtest pipe-B-query-forked-hang: SKIP (0.000s)[0m
12432 12:42:35.676031 <14>[ 26.698685] [IGT] kms_vblank: executing
12433 12:42:35.682381 IGT-Version: 1.2<14>[ 26.703792] [IGT] kms_vblank: exiting, ret=77
12434 12:42:35.685978 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12435 12:42:35.689019 Opened device: /dev/dri/card0
12436 12:42:35.696060 N<8>[ 26.715715] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy RESULT=skip>
12437 12:42:35.696320 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy RESULT=skip
12439 12:42:35.699039 o KMS driver or no outputs, pipes: 8, outputs: 0
12440 12:42:35.705696 [1mSubtest pipe-B-query-busy: SKIP (0.000s)[0m
12441 12:42:35.718490 <14>[ 26.741204] [IGT] kms_vblank: executing
12442 12:42:35.725080 IGT-Version: 1.2<14>[ 26.746183] [IGT] kms_vblank: exiting, ret=77
12443 12:42:35.728099 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12444 12:42:35.731825 Opened device: /dev/dri/card0
12445 12:42:35.738172 N<8>[ 26.757998] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip>
12446 12:42:35.738428 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip
12448 12:42:35.741761 o KMS driver or no outputs, pipes: 8, outputs: 0
12449 12:42:35.747976 [1mSubtest pipe-B-query-busy-hang: SKIP (0.000s)[0m
12450 12:42:35.761247 <14>[ 26.783902] [IGT] kms_vblank: executing
12451 12:42:35.767989 IGT-Version: 1.2<14>[ 26.788934] [IGT] kms_vblank: exiting, ret=77
12452 12:42:35.770839 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12453 12:42:35.774191 Opened device: /dev/dri/card0
12454 12:42:35.780824 N<8>[ 26.800562] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip>
12455 12:42:35.781083 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip
12457 12:42:35.787789 o KMS driver or no outputs, pipes: 8, outputs: 0
12458 12:42:35.790742 [1mSubtest pipe-B-query-forked-busy: SKIP (0.000s)[0m
12459 12:42:35.803842 <14>[ 26.826650] [IGT] kms_vblank: executing
12460 12:42:35.810506 IGT-Version: 1.2<14>[ 26.831833] [IGT] kms_vblank: exiting, ret=77
12461 12:42:35.813669 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12462 12:42:35.817513 Opened device: /dev/dri/card0
12463 12:42:35.823673 N<8>[ 26.843622] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip>
12464 12:42:35.823929 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip
12466 12:42:35.830684 o KMS driver or no outputs, pipes: 8, outputs: 0
12467 12:42:35.833665 [1mSubtest pipe-B-query-forked-busy-hang: SKIP (0.000s)[0m
12468 12:42:35.847893 <14>[ 26.870521] [IGT] kms_vblank: executing
12469 12:42:35.854679 IGT-Version: 1.2<14>[ 26.875669] [IGT] kms_vblank: exiting, ret=77
12470 12:42:35.857966 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12471 12:42:35.861132 Opened device: /dev/dri/card0
12472 12:42:35.867476 N<8>[ 26.887578] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle RESULT=skip>
12473 12:42:35.867757 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle RESULT=skip
12475 12:42:35.871223 o KMS driver or no outputs, pipes: 8, outputs: 0
12476 12:42:35.877784 [1mSubtest pipe-B-wait-idle: SKIP (0.000s)[0m
12477 12:42:35.890614 <14>[ 26.913524] [IGT] kms_vblank: executing
12478 12:42:35.897427 IGT-Version: 1.2<14>[ 26.918480] [IGT] kms_vblank: exiting, ret=77
12479 12:42:35.900776 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12480 12:42:35.904388 Opened device: /dev/dri/card0
12481 12:42:35.910508 N<8>[ 26.930176] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip>
12482 12:42:35.911097 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip
12484 12:42:35.913986 o KMS driver or no outputs, pipes: 8, outputs: 0
12485 12:42:35.920811 [1mSubtest pipe-B-wait-idle-hang: SKIP (0.000s)[0m
12486 12:42:35.934354 <14>[ 26.956888] [IGT] kms_vblank: executing
12487 12:42:35.940612 IGT-Version: 1.2<14>[ 26.961864] [IGT] kms_vblank: exiting, ret=77
12488 12:42:35.943839 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12489 12:42:35.947598 Opened device: /dev/dri/card0
12490 12:42:35.953692 N<8>[ 26.973752] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked RESULT=skip>
12491 12:42:35.953990 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked RESULT=skip
12493 12:42:35.957422 o KMS driver or no outputs, pipes: 8, outputs: 0
12494 12:42:35.963766 [1mSubtest pipe-B-wait-forked: SKIP (0.000s)[0m
12495 12:42:35.977544 <14>[ 26.999976] [IGT] kms_vblank: executing
12496 12:42:35.983989 IGT-Version: 1.2<14>[ 27.005036] [IGT] kms_vblank: exiting, ret=77
12497 12:42:35.987082 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12498 12:42:35.990230 Opened device: /dev/dri/card0
12499 12:42:35.996724 N<8>[ 27.017175] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip>
12500 12:42:35.996986 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip
12502 12:42:36.003404 o KMS driver or no outputs, pipes: 8, outputs: 0
12503 12:42:36.007069 [1mSubtest pipe-B-wait-forked-hang: SKIP (0.000s)[0m
12504 12:42:36.020724 <14>[ 27.043481] [IGT] kms_vblank: executing
12505 12:42:36.026970 IGT-Version: 1.2<14>[ 27.048591] [IGT] kms_vblank: exiting, ret=77
12506 12:42:36.030930 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12507 12:42:36.033991 Opened device: /dev/dri/card0
12508 12:42:36.040081 N<8>[ 27.060640] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy RESULT=skip>
12509 12:42:36.040355 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy RESULT=skip
12511 12:42:36.043801 o KMS driver or no outputs, pipes: 8, outputs: 0
12512 12:42:36.050199 [1mSubtest pipe-B-wait-busy: SKIP (0.000s)[0m
12513 12:42:36.064027 <14>[ 27.086460] [IGT] kms_vblank: executing
12514 12:42:36.070117 IGT-Version: 1.2<14>[ 27.091569] [IGT] kms_vblank: exiting, ret=77
12515 12:42:36.073925 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12516 12:42:36.076994 Opened device: /dev/dri/card0
12517 12:42:36.083922 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip
12519 12:42:36.086708 No KMS driver or <8>[ 27.103821] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip>
12520 12:42:36.086782 no outputs, pipes: 8, outputs: 0
12521 12:42:36.093351 [1mSubtest pipe-B-wait-busy-hang: SKIP (0.000s)[0m
12522 12:42:36.108805 <14>[ 27.131333] [IGT] kms_vblank: executing
12523 12:42:36.115495 IGT-Version: 1.2<14>[ 27.136392] [IGT] kms_vblank: exiting, ret=77
12524 12:42:36.118277 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12525 12:42:36.121813 Opened device: /dev/dri/card0
12526 12:42:36.128474 N<8>[ 27.148321] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip>
12527 12:42:36.128724 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip
12529 12:42:36.135176 o KMS driver or no outputs, pipes: 8, outputs: 0
12530 12:42:36.138190 [1mSubtest pipe-B-wait-forked-busy: SKIP (0.000s)[0m
12531 12:42:36.152570 <14>[ 27.175120] [IGT] kms_vblank: executing
12532 12:42:36.158722 IGT-Version: 1.2<14>[ 27.180190] [IGT] kms_vblank: exiting, ret=77
12533 12:42:36.162505 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12534 12:42:36.165701 Opened device: /dev/dri/card0
12535 12:42:36.171986 N<8>[ 27.192557] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip>
12536 12:42:36.172240 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip
12538 12:42:36.178844 o KMS driver or no outputs, pipes: 8, outputs: 0
12539 12:42:36.181999 [1mSubtest pipe-B-wait-forked-busy-hang: SKIP (0.000s)[0m
12540 12:42:36.196582 <14>[ 27.219203] [IGT] kms_vblank: executing
12541 12:42:36.202904 IGT-Version: 1.2<14>[ 27.224435] [IGT] kms_vblank: exiting, ret=77
12542 12:42:36.206274 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12543 12:42:36.209988 Opened device: /dev/dri/card0
12544 12:42:36.215983 N<8>[ 27.236382] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip>
12545 12:42:36.216244 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip
12547 12:42:36.222591 o KMS driver or no outputs, pipes: 8, outputs: 0
12548 12:42:36.226089 [1mSubtest pipe-B-ts-continuation-idle: SKIP (0.000s)[0m
12549 12:42:36.240729 <14>[ 27.263599] [IGT] kms_vblank: executing
12550 12:42:36.247492 IGT-Version: 1.2<14>[ 27.268808] [IGT] kms_vblank: exiting, ret=77
12551 12:42:36.250522 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12552 12:42:36.254242 Opened device: /dev/dri/card0
12553 12:42:36.260453 N<8>[ 27.280662] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip>
12554 12:42:36.260732 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip
12556 12:42:36.267182 o KMS driver or no outputs, pipes: 8, outputs: 0
12557 12:42:36.273689 [1mSubtest pipe-B-ts-continuation-idle-hang: SKIP (0.000s)[0m
12558 12:42:36.285623 <14>[ 27.308192] [IGT] kms_vblank: executing
12559 12:42:36.291991 IGT-Version: 1.2<14>[ 27.313390] [IGT] kms_vblank: exiting, ret=77
12560 12:42:36.295130 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12561 12:42:36.298786 Opened device: /dev/dri/card0
12562 12:42:36.305469 N<8>[ 27.325152] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip>
12563 12:42:36.305759 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip
12565 12:42:36.311812 o KMS driver or no outputs, pipes: 8, outputs: 0
12566 12:42:36.314759 [1mSubtest pipe-B-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12567 12:42:36.329070 <14>[ 27.351895] [IGT] kms_vblank: executing
12568 12:42:36.335823 IGT-Version: 1.2<14>[ 27.356904] [IGT] kms_vblank: exiting, ret=77
12569 12:42:36.338808 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12570 12:42:36.342447 Opened device: /dev/dri/card0
12571 12:42:36.348798 N<8>[ 27.368529] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip>
12572 12:42:36.349059 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip
12574 12:42:36.355381 o KMS driver or no outputs, pipes: 8, outputs: 0
12575 12:42:36.362154 [1mSubtest pipe-B-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12576 12:42:36.373181 <14>[ 27.396003] [IGT] kms_vblank: executing
12577 12:42:36.379600 IGT-Version: 1.2<14>[ 27.401089] [IGT] kms_vblank: exiting, ret=77
12578 12:42:36.383588 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12579 12:42:36.386507 Opened device: /dev/dri/card0
12580 12:42:36.392795 N<8>[ 27.413076] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip>
12581 12:42:36.393045 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip
12583 12:42:36.399746 o KMS driver or no outputs, pipes: 8, outputs: 0
12584 12:42:36.402741 [1mSubtest pipe-B-ts-continuation-suspend: SKIP (0.000s)[0m
12585 12:42:36.417330 <14>[ 27.440197] [IGT] kms_vblank: executing
12586 12:42:36.424103 IGT-Version: 1.2<14>[ 27.445389] [IGT] kms_vblank: exiting, ret=77
12587 12:42:36.426872 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12588 12:42:36.430403 Opened device: /dev/dri/card0
12589 12:42:36.436980 N<8>[ 27.457158] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip>
12590 12:42:36.437240 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip
12592 12:42:36.443540 o KMS driver or no outputs, pipes: 8, outputs: 0
12593 12:42:36.446642 [1mSubtest pipe-B-ts-continuation-modeset: SKIP (0.000s)[0m
12594 12:42:36.461723 <14>[ 27.484405] [IGT] kms_vblank: executing
12595 12:42:36.467902 IGT-Version: 1.2<14>[ 27.489393] [IGT] kms_vblank: exiting, ret=77
12596 12:42:36.471662 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12597 12:42:36.474633 Opened device: /dev/dri/card0
12598 12:42:36.481551 N<8>[ 27.501513] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip>
12599 12:42:36.481829 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip
12601 12:42:36.487802 o KMS driver or no outputs, pipes: 8, outputs: 0
12602 12:42:36.494514 [1mSubtest pipe-B-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12603 12:42:36.506336 <14>[ 27.529156] [IGT] kms_vblank: executing
12604 12:42:36.513055 IGT-Version: 1.2<14>[ 27.534131] [IGT] kms_vblank: exiting, ret=77
12605 12:42:36.516261 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12606 12:42:36.519341 Opened device: /dev/dri/card0
12607 12:42:36.526301 N<8>[ 27.545778] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip>
12608 12:42:36.526592 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip
12610 12:42:36.532400 o KMS driver or no outputs, pipes: 8, outputs: 0
12611 12:42:36.538819 [1mSubtest pipe-B-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12612 12:42:36.550486 <14>[ 27.573400] [IGT] kms_vblank: executing
12613 12:42:36.557184 IGT-Version: 1.2<14>[ 27.578450] [IGT] kms_vblank: exiting, ret=77
12614 12:42:36.560306 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12615 12:42:36.563778 Opened device: /dev/dri/card0
12616 12:42:36.570068 N<8>[ 27.590346] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip>
12617 12:42:36.570352 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip
12619 12:42:36.573738 o KMS driver or no outputs, pipes: 8, outputs: 0
12620 12:42:36.579910 [1mSubtest pipe-C-accuracy-idle: SKIP (0.000s)[0m
12621 12:42:36.593633 <14>[ 27.616624] [IGT] kms_vblank: executing
12622 12:42:36.600582 IGT-Version: 1.2<14>[ 27.621704] [IGT] kms_vblank: exiting, ret=77
12623 12:42:36.603686 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12624 12:42:36.606811 Opened device: /dev/dri/card0
12625 12:42:36.613397 N<8>[ 27.633991] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle RESULT=skip>
12626 12:42:36.613670 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle RESULT=skip
12628 12:42:36.617081 o KMS driver or no outputs, pipes: 8, outputs: 0
12629 12:42:36.623156 [1mSubtest pipe-C-query-idle: SKIP (0.000s)[0m
12630 12:42:36.637050 <14>[ 27.659712] [IGT] kms_vblank: executing
12631 12:42:36.643711 IGT-Version: 1.2<14>[ 27.664882] [IGT] kms_vblank: exiting, ret=77
12632 12:42:36.646634 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12633 12:42:36.650137 Opened device: /dev/dri/card0
12634 12:42:36.656842 N<8>[ 27.676718] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip>
12635 12:42:36.657120 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip
12637 12:42:36.663179 o KMS driver or no outputs, pipes: 8, outputs: 0
12638 12:42:36.666261 [1mSubtest pipe-C-query-idle-hang: SKIP (0.000s)[0m
12639 12:42:36.680553 <14>[ 27.703489] [IGT] kms_vblank: executing
12640 12:42:36.687324 IGT-Version: 1.2<14>[ 27.708455] [IGT] kms_vblank: exiting, ret=77
12641 12:42:36.690559 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12642 12:42:36.693624 Opened device: /dev/dri/card0
12643 12:42:36.700529 N<8>[ 27.720455] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked RESULT=skip>
12644 12:42:36.700809 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked RESULT=skip
12646 12:42:36.703693 o KMS driver or no outputs, pipes: 8, outputs: 0
12647 12:42:36.709944 [1mSubtest pipe-C-query-forked: SKIP (0.000s)[0m
12648 12:42:36.723749 <14>[ 27.746649] [IGT] kms_vblank: executing
12649 12:42:36.730098 IGT-Version: 1.2<14>[ 27.751972] [IGT] kms_vblank: exiting, ret=77
12650 12:42:36.733702 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12651 12:42:36.736798 Opened device: /dev/dri/card0
12652 12:42:36.743632 N<8>[ 27.763802] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip>
12653 12:42:36.743915 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip
12655 12:42:36.750296 o KMS driver or no outputs, pipes: 8, outputs: 0
12656 12:42:36.753313 [1mSubtest pipe-C-query-forked-hang: SKIP (0.000s)[0m
12657 12:42:36.767513 <14>[ 27.790443] [IGT] kms_vblank: executing
12658 12:42:36.774065 IGT-Version: 1.2<14>[ 27.795591] [IGT] kms_vblank: exiting, ret=77
12659 12:42:36.777231 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12660 12:42:36.781003 Opened device: /dev/dri/card0
12661 12:42:36.787063 No KMS driver or <8>[ 27.807917] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy RESULT=skip>
12662 12:42:36.787340 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy RESULT=skip
12664 12:42:36.790309 no outputs, pipes: 8, outputs: 0
12665 12:42:36.797060 [1mSubtest pipe-C-query-busy: SKIP (0.000s)[0m
12666 12:42:36.811432 <14>[ 27.834088] [IGT] kms_vblank: executing
12667 12:42:36.817816 IGT-Version: 1.2<14>[ 27.839243] [IGT] kms_vblank: exiting, ret=77
12668 12:42:36.821295 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12669 12:42:36.824320 Opened device: /dev/dri/card0
12670 12:42:36.831407 N<8>[ 27.851254] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip>
12671 12:42:36.831691 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip
12673 12:42:36.834467 o KMS driver or no outputs, pipes: 8, outputs: 0
12674 12:42:36.840795 [1mSubtest pipe-C-query-busy-hang: SKIP (0.000s)[0m
12675 12:42:36.853727 <14>[ 27.876844] [IGT] kms_vblank: executing
12676 12:42:36.860657 IGT-Version: 1.2<14>[ 27.881990] [IGT] kms_vblank: exiting, ret=77
12677 12:42:36.863693 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12678 12:42:36.867264 Opened device: /dev/dri/card0
12679 12:42:36.873739 N<8>[ 27.893827] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip>
12680 12:42:36.874020 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip
12682 12:42:36.880143 o KMS driver or no outputs, pipes: 8, outputs: 0
12683 12:42:36.883733 [1mSubtest pipe-C-query-forked-busy: SKIP (0.000s)[0m
12684 12:42:36.896747 <14>[ 27.919821] [IGT] kms_vblank: executing
12685 12:42:36.903718 IGT-Version: 1.2<14>[ 27.924837] [IGT] kms_vblank: exiting, ret=77
12686 12:42:36.906807 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12687 12:42:36.909926 Opened device: /dev/dri/card0
12688 12:42:36.916653 N<8>[ 27.936818] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip>
12689 12:42:36.916934 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip
12691 12:42:36.923528 o KMS driver or no outputs, pipes: 8, outputs: 0
12692 12:42:36.926424 [1mSubtest pipe-C-query-forked-busy-hang: SKIP (0.000s)[0m
12693 12:42:36.940135 <14>[ 27.963157] [IGT] kms_vblank: executing
12694 12:42:36.947092 IGT-Version: 1.2<14>[ 27.968128] [IGT] kms_vblank: exiting, ret=77
12695 12:42:36.950214 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12696 12:42:36.953314 Opened device: /dev/dri/card0
12697 12:42:36.959812 N<8>[ 27.980360] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle RESULT=skip>
12698 12:42:36.960115 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle RESULT=skip
12700 12:42:36.963598 o KMS driver or no outputs, pipes: 8, outputs: 0
12701 12:42:36.969826 [1mSubtest pipe-C-wait-idle: SKIP (0.000s)[0m
12702 12:42:36.982538 <14>[ 28.005483] [IGT] kms_vblank: executing
12703 12:42:36.989480 IGT-Version: 1.2<14>[ 28.010460] [IGT] kms_vblank: exiting, ret=77
12704 12:42:36.992570 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12705 12:42:36.995691 Opened device: /dev/dri/card0
12706 12:42:37.002104 N<8>[ 28.022338] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip>
12707 12:42:37.002365 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip
12709 12:42:37.005303 o KMS driver or no outputs, pipes: 8, outputs: 0
12710 12:42:37.012234 [1mSubtest pipe-C-wait-idle-hang: SKIP (0.000s)[0m
12711 12:42:37.025426 <14>[ 28.048186] [IGT] kms_vblank: executing
12712 12:42:37.031939 IGT-Version: 1.2<14>[ 28.053326] [IGT] kms_vblank: exiting, ret=77
12713 12:42:37.035506 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12714 12:42:37.038682 Opened device: /dev/dri/card0
12715 12:42:37.045053 N<8>[ 28.065164] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked RESULT=skip>
12716 12:42:37.045318 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked RESULT=skip
12718 12:42:37.048176 o KMS driver or no outputs, pipes: 8, outputs: 0
12719 12:42:37.055056 [1mSubtest pipe-C-wait-forked: SKIP (0.000s)[0m
12720 12:42:37.069048 <14>[ 28.091578] [IGT] kms_vblank: executing
12721 12:42:37.075367 IGT-Version: 1.2<14>[ 28.096557] [IGT] kms_vblank: exiting, ret=77
12722 12:42:37.078508 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12723 12:42:37.081985 Opened device: /dev/dri/card0
12724 12:42:37.088711 N<8>[ 28.108671] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip>
12725 12:42:37.088969 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip
12727 12:42:37.091832 o KMS driver or no outputs, pipes: 8, outputs: 0
12728 12:42:37.098405 [1mSubtest pipe-C-wait-forked-hang: SKIP (0.000s)[0m
12729 12:42:37.112397 <14>[ 28.135381] [IGT] kms_vblank: executing
12730 12:42:37.119300 IGT-Version: 1.2<14>[ 28.140591] [IGT] kms_vblank: exiting, ret=77
12731 12:42:37.122317 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12732 12:42:37.125489 Opened device: /dev/dri/card0
12733 12:42:37.132336 N<8>[ 28.152722] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy RESULT=skip>
12734 12:42:37.132594 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy RESULT=skip
12736 12:42:37.135845 o KMS driver or no outputs, pipes: 8, outputs: 0
12737 12:42:37.142063 [1mSubtest pipe-C-wait-busy: SKIP (0.000s)[0m
12738 12:42:37.155874 <14>[ 28.178677] [IGT] kms_vblank: executing
12739 12:42:37.162197 IGT-Version: 1.2<14>[ 28.183681] [IGT] kms_vblank: exiting, ret=77
12740 12:42:37.165908 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12741 12:42:37.168901 Opened device: /dev/dri/card0
12742 12:42:37.175494 N<8>[ 28.195695] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip>
12743 12:42:37.175751 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip
12745 12:42:37.178957 o KMS driver or no outputs, pipes: 8, outputs: 0
12746 12:42:37.185648 [1mSubtest pipe-C-wait-busy-hang: SKIP (0.000s)[0m
12747 12:42:37.199448 <14>[ 28.222068] [IGT] kms_vblank: executing
12748 12:42:37.206044 IGT-Version: 1.2<14>[ 28.227327] [IGT] kms_vblank: exiting, ret=77
12749 12:42:37.209349 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12750 12:42:37.212486 Opened device: /dev/dri/card0
12751 12:42:37.219407 N<8>[ 28.238845] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip>
12752 12:42:37.219657 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip
12754 12:42:37.222664 o KMS driver or no outputs, pipes: 8, outputs: 0
12755 12:42:37.228826 [1mSubtest pipe-C-wait-forked-busy: SKIP (0.000s)[0m
12756 12:42:37.242703 <14>[ 28.265535] [IGT] kms_vblank: executing
12757 12:42:37.249050 IGT-Version: 1.2<14>[ 28.270487] [IGT] kms_vblank: exiting, ret=77
12758 12:42:37.253185 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12759 12:42:37.256046 Opened device: /dev/dri/card0
12760 12:42:37.262345 N<8>[ 28.282547] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip>
12761 12:42:37.262611 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip
12763 12:42:37.269260 o KMS driver or no outputs, pipes: 8, outputs: 0
12764 12:42:37.272479 [1mSubtest pipe-C-wait-forked-busy-hang: SKIP (0.000s)[0m
12765 12:42:37.285833 <14>[ 28.308781] [IGT] kms_vblank: executing
12766 12:42:37.292550 IGT-Version: 1.2<14>[ 28.313778] [IGT] kms_vblank: exiting, ret=77
12767 12:42:37.295602 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12768 12:42:37.298945 Opened device: /dev/dri/card0
12769 12:42:37.305522 N<8>[ 28.325431] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip>
12770 12:42:37.305775 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip
12772 12:42:37.312385 o KMS driver or no outputs, pipes: 8, outputs: 0
12773 12:42:37.315439 [1mSubtest pipe-C-ts-continuation-idle: SKIP (0.000s)[0m
12774 12:42:37.329074 <14>[ 28.351927] [IGT] kms_vblank: executing
12775 12:42:37.335302 IGT-Version: 1.2<14>[ 28.357000] [IGT] kms_vblank: exiting, ret=77
12776 12:42:37.339096 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12777 12:42:37.342005 Opened device: /dev/dri/card0
12778 12:42:37.348690 N<8>[ 28.368768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip>
12779 12:42:37.348960 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip
12781 12:42:37.355554 o KMS driver or no outputs, pipes: 8, outputs: 0
12782 12:42:37.358632 [1mSubtest pipe-C-ts-continuation-idle-hang: SKIP (0.000s)[0m
12783 12:42:37.372586 <14>[ 28.395429] [IGT] kms_vblank: executing
12784 12:42:37.378999 IGT-Version: 1.2<14>[ 28.400427] [IGT] kms_vblank: exiting, ret=77
12785 12:42:37.382184 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12786 12:42:37.385726 Opened device: /dev/dri/card0
12787 12:42:37.392153 N<8>[ 28.412284] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip>
12788 12:42:37.392419 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip
12790 12:42:37.398571 o KMS driver or no outputs, pipes: 8, outputs: 0
12791 12:42:37.402435 [1mSubtest pipe-C-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12792 12:42:37.417056 <14>[ 28.439674] [IGT] kms_vblank: executing
12793 12:42:37.423121 IGT-Version: 1.2<14>[ 28.444952] [IGT] kms_vblank: exiting, ret=77
12794 12:42:37.426740 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12795 12:42:37.429982 Opened device: /dev/dri/card0
12796 12:42:37.436667 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip
12798 12:42:37.439666 N<8>[ 28.456564] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip>
12799 12:42:37.443390 o KMS driver or no outputs, pipes: 8, outputs: 0
12800 12:42:37.450073 [1mSubtest pipe-C-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12801 12:42:37.461222 <14>[ 28.484239] [IGT] kms_vblank: executing
12802 12:42:37.468167 IGT-Version: 1.2<14>[ 28.489210] [IGT] kms_vblank: exiting, ret=77
12803 12:42:37.471300 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12804 12:42:37.474405 Opened device: /dev/dri/card0
12805 12:42:37.484610 No KMS driver or <8>[ 28.501622] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip>
12806 12:42:37.484868 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip
12808 12:42:37.487650 no outputs, pipes: 8, outputs: 0
12809 12:42:37.490745 [1mSubtest pipe-C-ts-continuation-suspend: SKIP (0.000s)[0m
12810 12:42:37.506664 <14>[ 28.529701] [IGT] kms_vblank: executing
12811 12:42:37.513240 IGT-Version: 1.2<14>[ 28.534943] [IGT] kms_vblank: exiting, ret=77
12812 12:42:37.516614 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12813 12:42:37.520159 Opened device: /dev/dri/card0
12814 12:42:37.526629 N<8>[ 28.546422] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip>
12815 12:42:37.526851 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip
12817 12:42:37.533046 o KMS driver or no outputs, pipes: 8, outputs: 0
12818 12:42:37.536247 [1mSubtest pipe-C-ts-continuation-modeset: SKIP (0.000s)[0m
12819 12:42:37.551198 <14>[ 28.573891] [IGT] kms_vblank: executing
12820 12:42:37.557774 IGT-Version: 1.2<14>[ 28.579202] [IGT] kms_vblank: exiting, ret=77
12821 12:42:37.560869 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12822 12:42:37.564076 Opened device: /dev/dri/card0
12823 12:42:37.570589 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip
12825 12:42:37.574222 N<8>[ 28.590878] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip>
12826 12:42:37.577306 o KMS driver or no outputs, pipes: 8, outputs: 0
12827 12:42:37.583597 [1mSubtest pipe-C-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12828 12:42:37.595337 <14>[ 28.618447] [IGT] kms_vblank: executing
12829 12:42:37.602281 IGT-Version: 1.2<14>[ 28.623949] [IGT] kms_vblank: exiting, ret=77
12830 12:42:37.605383 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12831 12:42:37.608807 Opened device: /dev/dri/card0
12832 12:42:37.618601 No KMS driver or <8>[ 28.635967] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip>
12833 12:42:37.618880 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip
12835 12:42:37.621978 no outputs, pipes: 8, outputs: 0
12836 12:42:37.628529 [1mSubtest pipe-C-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12837 12:42:37.641743 <14>[ 28.664303] [IGT] kms_vblank: executing
12838 12:42:37.647851 IGT-Version: 1.2<14>[ 28.669264] [IGT] kms_vblank: exiting, ret=77
12839 12:42:37.651021 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12840 12:42:37.654783 Opened device: /dev/dri/card0
12841 12:42:37.660859 N<8>[ 28.681469] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip>
12842 12:42:37.661116 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip
12844 12:42:37.664368 o KMS driver or no outputs, pipes: 8, outputs: 0
12845 12:42:37.670562 [1mSubtest pipe-D-accuracy-idle: SKIP (0.000s)[0m
12846 12:42:37.684899 <14>[ 28.707648] [IGT] kms_vblank: executing
12847 12:42:37.691691 IGT-Version: 1.2<14>[ 28.712618] [IGT] kms_vblank: exiting, ret=77
12848 12:42:37.694864 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12849 12:42:37.698142 Opened device: /dev/dri/card0
12850 12:42:37.704379 N<8>[ 28.724775] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle RESULT=skip>
12851 12:42:37.704679 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle RESULT=skip
12853 12:42:37.708144 o KMS driver or no outputs, pipes: 8, outputs: 0
12854 12:42:37.714220 [1mSubtest pipe-D-query-idle: SKIP (0.000s)[0m
12855 12:42:37.728461 <14>[ 28.751148] [IGT] kms_vblank: executing
12856 12:42:37.735070 IGT-Version: 1.2<14>[ 28.756143] [IGT] kms_vblank: exiting, ret=77
12857 12:42:37.738288 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12858 12:42:37.741206 Opened device: /dev/dri/card0
12859 12:42:37.748373 N<8>[ 28.768444] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip>
12860 12:42:37.748640 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip
12862 12:42:37.751342 o KMS driver or no outputs, pipes: 8, outputs: 0
12863 12:42:37.758095 [1mSubtest pipe-D-query-idle-hang: SKIP (0.000s)[0m
12864 12:42:37.771705 <14>[ 28.794636] [IGT] kms_vblank: executing
12865 12:42:37.778239 IGT-Version: 1.2<14>[ 28.799767] [IGT] kms_vblank: exiting, ret=77
12866 12:42:37.781363 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12867 12:42:37.784668 Opened device: /dev/dri/card0
12868 12:42:37.791734 N<8>[ 28.811746] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked RESULT=skip>
12869 12:42:37.791992 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked RESULT=skip
12871 12:42:37.795034 o KMS driver or no outputs, pipes: 8, outputs: 0
12872 12:42:37.801353 [1mSubtest pipe-D-query-forked: SKIP (0.000s)[0m
12873 12:42:37.815087 <14>[ 28.838024] [IGT] kms_vblank: executing
12874 12:42:37.821826 IGT-Version: 1.2<14>[ 28.843158] [IGT] kms_vblank: exiting, ret=77
12875 12:42:37.825108 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12876 12:42:37.828339 Opened device: /dev/dri/card0
12877 12:42:37.835077 N<8>[ 28.854579] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip>
12878 12:42:37.835384 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip
12880 12:42:37.841772 o KMS driver or no outputs, pipes: 8, outputs: 0
12881 12:42:37.844899 [1mSubtest pipe-D-query-forked-hang: SKIP (0.000s)[0m
12882 12:42:37.858589 <14>[ 28.881573] [IGT] kms_vblank: executing
12883 12:42:37.865464 IGT-Version: 1.2<14>[ 28.886774] [IGT] kms_vblank: exiting, ret=77
12884 12:42:37.868562 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12885 12:42:37.871691 Opened device: /dev/dri/card0
12886 12:42:37.878515 N<8>[ 28.897790] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy RESULT=skip>
12887 12:42:37.878821 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy RESULT=skip
12889 12:42:37.881814 o KMS driver or no outputs, pipes: 8, outputs: 0
12890 12:42:37.888247 [1mSubtest pipe-D-query-busy: SKIP (0.000s)[0m
12891 12:42:37.900939 <14>[ 28.923958] [IGT] kms_vblank: executing
12892 12:42:37.907810 IGT-Version: 1.2<14>[ 28.928977] [IGT] kms_vblank: exiting, ret=77
12893 12:42:37.911104 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12894 12:42:37.914326 Opened device: /dev/dri/card0
12895 12:42:37.921163 N<8>[ 28.940430] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip>
12896 12:42:37.921422 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip
12898 12:42:37.924285 o KMS driver or no outputs, pipes: 8, outputs: 0
12899 12:42:37.930412 [1mSubtest pipe-D-query-busy-hang: SKIP (0.000s)[0m
12900 12:42:37.944088 <14>[ 28.966669] [IGT] kms_vblank: executing
12901 12:42:37.950221 IGT-Version: 1.2<14>[ 28.971763] [IGT] kms_vblank: exiting, ret=77
12902 12:42:37.953406 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12903 12:42:37.957097 Opened device: /dev/dri/card0
12904 12:42:37.963095 N<8>[ 28.983729] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip>
12905 12:42:37.963387 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip
12907 12:42:37.969766 o KMS driver or no outputs, pipes: 8, outputs: 0
12908 12:42:37.973316 [1mSubtest pipe-D-query-forked-busy: SKIP (0.000s)[0m
12909 12:42:37.987025 <14>[ 29.009834] [IGT] kms_vblank: executing
12910 12:42:37.993363 IGT-Version: 1.2<14>[ 29.014983] [IGT] kms_vblank: exiting, ret=77
12911 12:42:37.996549 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12912 12:42:38.000366 Opened device: /dev/dri/card0
12913 12:42:38.006748 N<8>[ 29.026151] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip>
12914 12:42:38.007040 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip
12916 12:42:38.013037 o KMS driver or no outputs, pipes: 8, outputs: 0
12917 12:42:38.016126 [1mSubtest pipe-D-query-forked-busy-hang: SKIP (0.000s)[0m
12918 12:42:38.030537 <14>[ 29.053817] [IGT] kms_vblank: executing
12919 12:42:38.037040 IGT-Version: 1.2<14>[ 29.058955] [IGT] kms_vblank: exiting, ret=77
12920 12:42:38.040586 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12921 12:42:38.043697 Opened device: /dev/dri/card0
12922 12:42:38.050597 N<8>[ 29.070868] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle RESULT=skip>
12923 12:42:38.050858 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle RESULT=skip
12925 12:42:38.053538 o KMS driver or no outputs, pipes: 8, outputs: 0
12926 12:42:38.060208 [1mSubtest pipe-D-wait-idle: SKIP (0.000s)[0m
12927 12:42:38.073866 <14>[ 29.096974] [IGT] kms_vblank: executing
12928 12:42:38.080556 IGT-Version: 1.2<14>[ 29.101935] [IGT] kms_vblank: exiting, ret=77
12929 12:42:38.084103 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12930 12:42:38.087261 Opened device: /dev/dri/card0
12931 12:42:38.093608 N<8>[ 29.114115] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip>
12932 12:42:38.093888 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip
12934 12:42:38.096716 o KMS driver or no outputs, pipes: 8, outputs: 0
12935 12:42:38.103515 [1mSubtest pipe-D-wait-idle-hang: SKIP (0.000s)[0m
12936 12:42:38.117465 <14>[ 29.140297] [IGT] kms_vblank: executing
12937 12:42:38.123762 IGT-Version: 1.2<14>[ 29.145269] [IGT] kms_vblank: exiting, ret=77
12938 12:42:38.127259 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12939 12:42:38.130405 Opened device: /dev/dri/card0
12940 12:42:38.137292 N<8>[ 29.157539] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked RESULT=skip>
12941 12:42:38.137570 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked RESULT=skip
12943 12:42:38.140231 o KMS driver or no outputs, pipes: 8, outputs: 0
12944 12:42:38.146708 [1mSubtest pipe-D-wait-forked: SKIP (0.000s)[0m
12945 12:42:38.160861 <14>[ 29.183733] [IGT] kms_vblank: executing
12946 12:42:38.167605 IGT-Version: 1.2<14>[ 29.188811] [IGT] kms_vblank: exiting, ret=77
12947 12:42:38.170569 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12948 12:42:38.173777 Opened device: /dev/dri/card0
12949 12:42:38.180554 N<8>[ 29.201035] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip>
12950 12:42:38.180813 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip
12952 12:42:38.187145 o KMS driver or no outputs, pipes: 8, outputs: 0
12953 12:42:38.190284 [1mSubtest pipe-D-wait-forked-hang: SKIP (0.000s)[0m
12954 12:42:38.204556 <14>[ 29.227541] [IGT] kms_vblank: executing
12955 12:42:38.210919 IGT-Version: 1.2<14>[ 29.232607] [IGT] kms_vblank: exiting, ret=77
12956 12:42:38.214265 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12957 12:42:38.217914 Opened device: /dev/dri/card0
12958 12:42:38.224115 N<8>[ 29.244648] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy RESULT=skip>
12959 12:42:38.224371 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy RESULT=skip
12961 12:42:38.227845 o KMS driver or no outputs, pipes: 8, outputs: 0
12962 12:42:38.233923 [1mSubtest pipe-D-wait-busy: SKIP (0.000s)[0m
12963 12:42:38.248166 <14>[ 29.271189] [IGT] kms_vblank: executing
12964 12:42:38.255029 IGT-Version: 1.2<14>[ 29.276347] [IGT] kms_vblank: exiting, ret=77
12965 12:42:38.258419 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12966 12:42:38.261656 Opened device: /dev/dri/card0
12967 12:42:38.267872 N<8>[ 29.288340] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip>
12968 12:42:38.268130 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip
12970 12:42:38.271253 o KMS driver or no outputs, pipes: 8, outputs: 0
12971 12:42:38.277932 [1mSubtest pipe-D-wait-busy-hang: SKIP (0.000s)[0m
12972 12:42:38.290741 <14>[ 29.313942] [IGT] kms_vblank: executing
12973 12:42:38.297442 IGT-Version: 1.2<14>[ 29.318965] [IGT] kms_vblank: exiting, ret=77
12974 12:42:38.300498 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12975 12:42:38.304146 Opened device: /dev/dri/card0
12976 12:42:38.310430 N<8>[ 29.330625] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip>
12977 12:42:38.310688 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip
12979 12:42:38.317197 o KMS driver or no outputs, pipes: 8, outputs: 0
12980 12:42:38.320291 [1mSubtest pipe-D-wait-forked-busy: SKIP (0.000s)[0m
12981 12:42:38.334062 <14>[ 29.356900] [IGT] kms_vblank: executing
12982 12:42:38.340476 IGT-Version: 1.2<14>[ 29.361912] [IGT] kms_vblank: exiting, ret=77
12983 12:42:38.344229 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12984 12:42:38.347297 Opened device: /dev/dri/card0
12985 12:42:38.353695 N<8>[ 29.373694] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip>
12986 12:42:38.353951 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip
12988 12:42:38.360388 o KMS driver or no outputs, pipes: 8, outputs: 0
12989 12:42:38.363766 [1mSubtest pipe-D-wait-forked-busy-hang: SKIP (0.000s)[0m
12990 12:42:38.377355 <14>[ 29.400131] [IGT] kms_vblank: executing
12991 12:42:38.383522 IGT-Version: 1.2<14>[ 29.405239] [IGT] kms_vblank: exiting, ret=77
12992 12:42:38.387263 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12993 12:42:38.390234 Opened device: /dev/dri/card0
12994 12:42:38.396957 N<8>[ 29.417202] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip>
12995 12:42:38.397215 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip
12997 12:42:38.403567 o KMS driver or no outputs, pipes: 8, outputs: 0
12998 12:42:38.406639 [1mSubtest pipe-D-ts-continuation-idle: SKIP (0.000s)[0m
12999 12:42:38.421185 <14>[ 29.443956] [IGT] kms_vblank: executing
13000 12:42:38.427314 IGT-Version: 1.2<14>[ 29.448926] [IGT] kms_vblank: exiting, ret=77
13001 12:42:38.431011 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13002 12:42:38.434096 Opened device: /dev/dri/card0
13003 12:42:38.440645 N<8>[ 29.461158] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip>
13004 12:42:38.440902 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip
13006 12:42:38.447456 o KMS driver or no outputs, pipes: 8, outputs: 0
13007 12:42:38.450648 [1mSubtest pipe-D-ts-continuation-idle-hang: SKIP (0.000s)[0m
13008 12:42:38.465325 <14>[ 29.488181] [IGT] kms_vblank: executing
13009 12:42:38.471635 IGT-Version: 1.2<14>[ 29.493248] [IGT] kms_vblank: exiting, ret=77
13010 12:42:38.475037 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13011 12:42:38.478547 Opened device: /dev/dri/card0
13012 12:42:38.485076 N<8>[ 29.505579] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip>
13013 12:42:38.485364 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip
13015 12:42:38.491254 o KMS driver or no outputs, pipes: 8, outputs: 0
13016 12:42:38.494762 [1mSubtest pipe-D-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13017 12:42:38.509142 <14>[ 29.532386] [IGT] kms_vblank: executing
13018 12:42:38.515936 IGT-Version: 1.2<14>[ 29.537370] [IGT] kms_vblank: exiting, ret=77
13019 12:42:38.519736 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13020 12:42:38.522682 Opened device: /dev/dri/card0
13021 12:42:38.528843 N<8>[ 29.549431] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip>
13022 12:42:38.529111 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip
13024 12:42:38.535522 o KMS driver or no outputs, pipes: 8, outputs: 0
13025 12:42:38.542237 [1mSubtest pipe-D-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13026 12:42:38.553165 <14>[ 29.576124] [IGT] kms_vblank: executing
13027 12:42:38.560043 IGT-Version: 1.2<14>[ 29.581127] [IGT] kms_vblank: exiting, ret=77
13028 12:42:38.563077 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13029 12:42:38.566153 Opened device: /dev/dri/card0
13030 12:42:38.572860 N<8>[ 29.592979] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip>
13031 12:42:38.573163 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip
13033 12:42:38.579413 o KMS driver or no outputs, pipes: 8, outputs: 0
13034 12:42:38.582950 [1mSubtest pipe-D-ts-continuation-suspend: SKIP (0.000s)[0m
13035 12:42:38.596275 <14>[ 29.619151] [IGT] kms_vblank: executing
13036 12:42:38.602674 IGT-Version: 1.2<14>[ 29.624127] [IGT] kms_vblank: exiting, ret=77
13037 12:42:38.606159 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13038 12:42:38.609168 Opened device: /dev/dri/card0
13039 12:42:38.615920 N<8>[ 29.636038] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip>
13040 12:42:38.616209 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip
13042 12:42:38.622704 o KMS driver or no outputs, pipes: 8, outputs: 0
13043 12:42:38.625684 [1mSubtest pipe-D-ts-continuation-modeset: SKIP (0.000s)[0m
13044 12:42:38.639185 <14>[ 29.662481] [IGT] kms_vblank: executing
13045 12:42:38.645928 IGT-Version: 1.2<14>[ 29.667663] [IGT] kms_vblank: exiting, ret=77
13046 12:42:38.649446 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13047 12:42:38.652539 Opened device: /dev/dri/card0
13048 12:42:38.659319 N<8>[ 29.679566] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip>
13049 12:42:38.659586 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip
13051 12:42:38.666066 o KMS driver or no outputs, pipes: 8, outputs: 0
13052 12:42:38.672179 [1mSubtest pipe-D-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13053 12:42:38.683994 <14>[ 29.707066] [IGT] kms_vblank: executing
13054 12:42:38.690375 IGT-Version: 1.2<14>[ 29.712266] [IGT] kms_vblank: exiting, ret=77
13055 12:42:38.693901 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13056 12:42:38.697366 Opened device: /dev/dri/card0
13057 12:42:38.704100 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip
13059 12:42:38.706763 N<8>[ 29.724432] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip>
13060 12:42:38.710526 o KMS driver or no outputs, pipes: 8, outputs: 0
13061 12:42:38.716758 [1mSubtest pipe-D-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13062 12:42:38.727715 <14>[ 29.750829] [IGT] kms_vblank: executing
13063 12:42:38.734263 IGT-Version: 1.2<14>[ 29.755804] [IGT] kms_vblank: exiting, ret=77
13064 12:42:38.737973 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13065 12:42:38.740987 Opened device: /dev/dri/card0
13066 12:42:38.747709 N<8>[ 29.767666] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip>
13067 12:42:38.747969 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip
13069 12:42:38.750661 o KMS driver or no outputs, pipes: 8, outputs: 0
13070 12:42:38.757105 [1mSubtest pipe-E-accuracy-idle: SKIP (0.000s)[0m
13071 12:42:38.770569 <14>[ 29.793551] [IGT] kms_vblank: executing
13072 12:42:38.777245 IGT-Version: 1.2<14>[ 29.798549] [IGT] kms_vblank: exiting, ret=77
13073 12:42:38.780323 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13074 12:42:38.784045 Opened device: /dev/dri/card0
13075 12:42:38.790231 N<8>[ 29.810260] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle RESULT=skip>
13076 12:42:38.790484 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle RESULT=skip
13078 12:42:38.793199 o KMS driver or no outputs, pipes: 8, outputs: 0
13079 12:42:38.800163 [1mSubtest pipe-E-query-idle: SKIP (0.000s)[0m
13080 12:42:38.813824 <14>[ 29.836551] [IGT] kms_vblank: executing
13081 12:42:38.820306 IGT-Version: 1.2<14>[ 29.841728] [IGT] kms_vblank: exiting, ret=77
13082 12:42:38.823131 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13083 12:42:38.826695 Opened device: /dev/dri/card0
13084 12:42:38.833314 N<8>[ 29.853573] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip>
13085 12:42:38.833568 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip
13087 12:42:38.839669 o KMS driver or no outputs, pipes: 8, outputs: 0
13088 12:42:38.842721 [1mSubtest pipe-E-query-idle-hang: SKIP (0.000s)[0m
13089 12:42:38.857229 <14>[ 29.880020] [IGT] kms_vblank: executing
13090 12:42:38.863859 IGT-Version: 1.2<14>[ 29.885105] [IGT] kms_vblank: exiting, ret=77
13091 12:42:38.867008 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13092 12:42:38.870065 Opened device: /dev/dri/card0
13093 12:42:38.876578 N<8>[ 29.897222] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked RESULT=skip>
13094 12:42:38.876832 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked RESULT=skip
13096 12:42:38.880184 o KMS driver or no outputs, pipes: 8, outputs: 0
13097 12:42:38.886744 [1mSubtest pipe-E-query-forked: SKIP (0.000s)[0m
13098 12:42:38.900276 <14>[ 29.923379] [IGT] kms_vblank: executing
13099 12:42:38.907108 IGT-Version: 1.2<14>[ 29.928331] [IGT] kms_vblank: exiting, ret=77
13100 12:42:38.910141 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13101 12:42:38.913605 Opened device: /dev/dri/card0
13102 12:42:38.920027 N<8>[ 29.940678] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip>
13103 12:42:38.920288 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip
13105 12:42:38.927078 o KMS driver or no outputs, pipes: 8, outputs: 0
13106 12:42:38.930122 [1mSubtest pipe-E-query-forked-hang: SKIP (0.000s)[0m
13107 12:42:38.944154 <14>[ 29.967297] [IGT] kms_vblank: executing
13108 12:42:38.950706 IGT-Version: 1.2<14>[ 29.972377] [IGT] kms_vblank: exiting, ret=77
13109 12:42:38.954488 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13110 12:42:38.957456 Opened device: /dev/dri/card0
13111 12:42:38.964093 No KMS driver or <8>[ 29.984834] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy RESULT=skip>
13112 12:42:38.964350 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy RESULT=skip
13114 12:42:38.967134 no outputs, pipes: 8, outputs: 0
13115 12:42:38.973817 [1mSubtest pipe-E-query-busy: SKIP (0.000s)[0m
13116 12:42:38.989035 <14>[ 30.011905] [IGT] kms_vblank: executing
13117 12:42:38.995761 IGT-Version: 1.2<14>[ 30.016872] [IGT] kms_vblank: exiting, ret=77
13118 12:42:38.998852 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13119 12:42:39.001999 Opened device: /dev/dri/card0
13120 12:42:39.009003 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip
13122 12:42:39.011793 No KMS driver or <8>[ 30.029583] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip>
13123 12:42:39.011876 no outputs, pipes: 8, outputs: 0
13124 12:42:39.018664 [1mSubtest pipe-E-query-busy-hang: SKIP (0.000s)[0m
13125 12:42:39.032623 <14>[ 30.055948] [IGT] kms_vblank: executing
13126 12:42:39.039394 IGT-Version: 1.2<14>[ 30.060943] [IGT] kms_vblank: exiting, ret=77
13127 12:42:39.043092 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13128 12:42:39.046030 Opened device: /dev/dri/card0
13129 12:42:39.052377 N<8>[ 30.072775] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip>
13130 12:42:39.052630 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip
13132 12:42:39.059068 o KMS driver or no outputs, pipes: 8, outputs: 0
13133 12:42:39.062162 [1mSubtest pipe-E-query-forked-busy: SKIP (0.000s)[0m
13134 12:42:39.076152 <14>[ 30.099464] [IGT] kms_vblank: executing
13135 12:42:39.082854 IGT-Version: 1.2<14>[ 30.104426] [IGT] kms_vblank: exiting, ret=77
13136 12:42:39.086534 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13137 12:42:39.089492 Opened device: /dev/dri/card0
13138 12:42:39.096180 N<8>[ 30.116684] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip>
13139 12:42:39.096430 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip
13141 12:42:39.103179 o KMS driver or no outputs, pipes: 8, outputs: 0
13142 12:42:39.106312 [1mSubtest pipe-E-query-forked-busy-hang: SKIP (0.000s)[0m
13143 12:42:39.119590 <14>[ 30.142720] [IGT] kms_vblank: executing
13144 12:42:39.126148 IGT-Version: 1.2<14>[ 30.147765] [IGT] kms_vblank: exiting, ret=77
13145 12:42:39.129696 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13146 12:42:39.132710 Opened device: /dev/dri/card0
13147 12:42:39.139333 N<8>[ 30.159875] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle RESULT=skip>
13148 12:42:39.139583 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle RESULT=skip
13150 12:42:39.142453 o KMS driver or no outputs, pipes: 8, outputs: 0
13151 12:42:39.149206 [1mSubtest pipe-E-wait-idle: SKIP (0.000s)[0m
13152 12:42:39.162554 <14>[ 30.185547] [IGT] kms_vblank: executing
13153 12:42:39.168912 IGT-Version: 1.2<14>[ 30.190671] [IGT] kms_vblank: exiting, ret=77
13154 12:42:39.172588 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13155 12:42:39.175587 Opened device: /dev/dri/card0
13156 12:42:39.182261 N<8>[ 30.202756] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip>
13157 12:42:39.182515 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip
13159 12:42:39.188672 o KMS driver or no outputs, pipes: 8, outputs: 0
13160 12:42:39.192324 [1mSubtest pipe-E-wait-idle-hang: SKIP (0.000s)[0m
13161 12:42:39.206209 <14>[ 30.229153] [IGT] kms_vblank: executing
13162 12:42:39.212356 IGT-Version: 1.2<14>[ 30.234180] [IGT] kms_vblank: exiting, ret=77
13163 12:42:39.216010 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13164 12:42:39.219161 Opened device: /dev/dri/card0
13165 12:42:39.225862 N<8>[ 30.246412] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked RESULT=skip>
13166 12:42:39.226114 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked RESULT=skip
13168 12:42:39.229360 o KMS driver or no outputs, pipes: 8, outputs: 0
13169 12:42:39.235560 [1mSubtest pipe-E-wait-forked: SKIP (0.000s)[0m
13170 12:42:39.248667 <14>[ 30.271450] [IGT] kms_vblank: executing
13171 12:42:39.255259 IGT-Version: 1.2<14>[ 30.276562] [IGT] kms_vblank: exiting, ret=77
13172 12:42:39.258367 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13173 12:42:39.262159 Opened device: /dev/dri/card0
13174 12:42:39.268394 N<8>[ 30.288524] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip>
13175 12:42:39.268654 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip
13177 12:42:39.274430 o KMS driver or no outputs, pipes: 8, outputs: 0
13178 12:42:39.277816 [1mSubtest pipe-E-wait-forked-hang: SKIP (0.000s)[0m
13179 12:42:39.291484 <14>[ 30.314608] [IGT] kms_vblank: executing
13180 12:42:39.298283 IGT-Version: 1.2<14>[ 30.319627] [IGT] kms_vblank: exiting, ret=77
13181 12:42:39.301386 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13182 12:42:39.304466 Opened device: /dev/dri/card0
13183 12:42:39.311270 N<8>[ 30.331868] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy RESULT=skip>
13184 12:42:39.311523 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy RESULT=skip
13186 12:42:39.314759 o KMS driver or no outputs, pipes: 8, outputs: 0
13187 12:42:39.320984 [1mSubtest pipe-E-wait-busy: SKIP (0.000s)[0m
13188 12:42:39.333661 <14>[ 30.356772] [IGT] kms_vblank: executing
13189 12:42:39.340271 IGT-Version: 1.2<14>[ 30.361780] [IGT] kms_vblank: exiting, ret=77
13190 12:42:39.343736 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13191 12:42:39.346720 Opened device: /dev/dri/card0
13192 12:42:39.353229 N<8>[ 30.373856] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip>
13193 12:42:39.353482 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip
13195 12:42:39.356697 o KMS driver or no outputs, pipes: 8, outputs: 0
13196 12:42:39.362963 [1mSubtest pipe-E-wait-busy-hang: SKIP (0.000s)[0m
13197 12:42:39.376029 <14>[ 30.399325] [IGT] kms_vblank: executing
13198 12:42:39.382912 IGT-Version: 1.2<14>[ 30.404297] [IGT] kms_vblank: exiting, ret=77
13199 12:42:39.386152 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13200 12:42:39.389375 Opened device: /dev/dri/card0
13201 12:42:39.396301 N<8>[ 30.416424] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip>
13202 12:42:39.396555 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip
13204 12:42:39.399358 o KMS driver or no outputs, pipes: 8, outputs: 0
13205 12:42:39.406072 [1mSubtest pipe-E-wait-forked-busy: SKIP (0.000s)[0m
13206 12:42:39.418804 <14>[ 30.442018] [IGT] kms_vblank: executing
13207 12:42:39.425609 IGT-Version: 1.2<14>[ 30.447045] [IGT] kms_vblank: exiting, ret=77
13208 12:42:39.428588 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13209 12:42:39.432239 Opened device: /dev/dri/card0
13210 12:42:39.438654 N<8>[ 30.458712] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip>
13211 12:42:39.438906 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip
13213 12:42:39.445291 o KMS driver or no outputs, pipes: 8, outputs: 0
13214 12:42:39.448682 [1mSubtest pipe-E-wait-forked-busy-hang: SKIP (0.000s)[0m
13215 12:42:39.461804 <14>[ 30.485109] [IGT] kms_vblank: executing
13216 12:42:39.468487 IGT-Version: 1.2<14>[ 30.490105] [IGT] kms_vblank: exiting, ret=77
13217 12:42:39.471528 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13218 12:42:39.475251 Opened device: /dev/dri/card0
13219 12:42:39.481860 N<8>[ 30.502101] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip>
13220 12:42:39.482114 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip
13222 12:42:39.488208 o KMS driver or no outputs, pipes: 8, outputs: 0
13223 12:42:39.491730 [1mSubtest pipe-E-ts-continuation-idle: SKIP (0.000s)[0m
13224 12:42:39.505151 <14>[ 30.528386] [IGT] kms_vblank: executing
13225 12:42:39.511947 IGT-Version: 1.2<14>[ 30.533411] [IGT] kms_vblank: exiting, ret=77
13226 12:42:39.515001 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13227 12:42:39.518582 Opened device: /dev/dri/card0
13228 12:42:39.524826 N<8>[ 30.545556] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip>
13229 12:42:39.525079 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip
13231 12:42:39.531637 o KMS driver or no outputs, pipes: 8, outputs: 0
13232 12:42:39.534752 [1mSubtest pipe-E-ts-continuation-idle-hang: SKIP (0.000s)[0m
13233 12:42:39.549568 <14>[ 30.572958] [IGT] kms_vblank: executing
13234 12:42:39.556704 IGT-Version: 1.2<14>[ 30.577960] [IGT] kms_vblank: exiting, ret=77
13235 12:42:39.559528 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13236 12:42:39.563067 Opened device: /dev/dri/card0
13237 12:42:39.569355 N<8>[ 30.590034] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip>
13238 12:42:39.569629 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip
13240 12:42:39.576108 o KMS driver or no outputs, pipes: 8, outputs: 0
13241 12:42:39.579222 [1mSubtest pipe-E-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13242 12:42:39.593203 <14>[ 30.616519] [IGT] kms_vblank: executing
13243 12:42:39.600183 IGT-Version: 1.2<14>[ 30.621513] [IGT] kms_vblank: exiting, ret=77
13244 12:42:39.603511 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13245 12:42:39.606518 Opened device: /dev/dri/card0
13246 12:42:39.613057 N<8>[ 30.633656] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip>
13247 12:42:39.613312 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip
13249 12:42:39.619695 o KMS driver or no outputs, pipes: 8, outputs: 0
13250 12:42:39.626447 [1mSubtest pipe-E-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13251 12:42:39.637492 <14>[ 30.660311] [IGT] kms_vblank: executing
13252 12:42:39.644040 IGT-Version: 1.2<14>[ 30.665415] [IGT] kms_vblank: exiting, ret=77
13253 12:42:39.646799 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13254 12:42:39.650583 Opened device: /dev/dri/card0
13255 12:42:39.656901 N<8>[ 30.677547] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip>
13256 12:42:39.657148 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip
13258 12:42:39.663289 o KMS driver or no outputs, pipes: 8, outputs: 0
13259 12:42:39.666581 [1mSubtest pipe-E-ts-continuation-suspend: SKIP (0.000s)[0m
13260 12:42:39.680635 <14>[ 30.703675] [IGT] kms_vblank: executing
13261 12:42:39.687349 IGT-Version: 1.2<14>[ 30.708652] [IGT] kms_vblank: exiting, ret=77
13262 12:42:39.690533 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13263 12:42:39.693503 Opened device: /dev/dri/card0
13264 12:42:39.700173 N<8>[ 30.720726] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip>
13265 12:42:39.700458 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip
13267 12:42:39.706611 o KMS driver or no outputs, pipes: 8, outputs: 0
13268 12:42:39.710112 [1mSubtest pipe-E-ts-continuation-modeset: SKIP (0.000s)[0m
13269 12:42:39.724338 <14>[ 30.747179] [IGT] kms_vblank: executing
13270 12:42:39.730380 IGT-Version: 1.2<14>[ 30.752188] [IGT] kms_vblank: exiting, ret=77
13271 12:42:39.734069 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13272 12:42:39.737273 Opened device: /dev/dri/card0
13273 12:42:39.743854 N<8>[ 30.764368] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip>
13274 12:42:39.744140 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip
13276 12:42:39.750441 o KMS driver or no outputs, pipes: 8, outputs: 0
13277 12:42:39.756546 [1mSubtest pipe-E-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13278 12:42:39.768939 <14>[ 30.791809] [IGT] kms_vblank: executing
13279 12:42:39.775179 IGT-Version: 1.2<14>[ 30.796802] [IGT] kms_vblank: exiting, ret=77
13280 12:42:39.778609 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13281 12:42:39.781630 Opened device: /dev/dri/card0
13282 12:42:39.788698 N<8>[ 30.808996] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip>
13283 12:42:39.788992 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip
13285 12:42:39.795037 o KMS driver or no outputs, pipes: 8, outputs: 0
13286 12:42:39.801684 [1mSubtest pipe-E-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13287 12:42:39.812129 <14>[ 30.835277] [IGT] kms_vblank: executing
13288 12:42:39.818401 IGT-Version: 1.2<14>[ 30.840339] [IGT] kms_vblank: exiting, ret=77
13289 12:42:39.822014 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13290 12:42:39.825383 Opened device: /dev/dri/card0
13291 12:42:39.831850 N<8>[ 30.852287] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip>
13292 12:42:39.832106 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip
13294 12:42:39.835057 o KMS driver or no outputs, pipes: 8, outputs: 0
13295 12:42:39.841629 [1mSubtest pipe-F-accuracy-idle: SKIP (0.000s)[0m
13296 12:42:39.855129 <14>[ 30.878146] [IGT] kms_vblank: executing
13297 12:42:39.861820 IGT-Version: 1.2<14>[ 30.883353] [IGT] kms_vblank: exiting, ret=77
13298 12:42:39.864863 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13299 12:42:39.868566 Opened device: /dev/dri/card0
13300 12:42:39.874661 N<8>[ 30.894849] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle RESULT=skip>
13301 12:42:39.874939 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle RESULT=skip
13303 12:42:39.878263 o KMS driver or no outputs, pipes: 8, outputs: 0
13304 12:42:39.884793 [1mSubtest pipe-F-query-idle: SKIP (0.000s)[0m
13305 12:42:39.898005 <14>[ 30.921196] [IGT] kms_vblank: executing
13306 12:42:39.904463 IGT-Version: 1.2<14>[ 30.926144] [IGT] kms_vblank: exiting, ret=77
13307 12:42:39.908084 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13308 12:42:39.911187 Opened device: /dev/dri/card0
13309 12:42:39.917771 N<8>[ 30.937954] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip>
13310 12:42:39.918046 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip
13312 12:42:39.921295 o KMS driver or no outputs, pipes: 8, outputs: 0
13313 12:42:39.927593 [1mSubtest pipe-F-query-idle-hang: SKIP (0.000s)[0m
13314 12:42:39.941013 <14>[ 30.963799] [IGT] kms_vblank: executing
13315 12:42:39.947107 IGT-Version: 1.2<14>[ 30.968767] [IGT] kms_vblank: exiting, ret=77
13316 12:42:39.950676 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13317 12:42:39.953794 Opened device: /dev/dri/card0
13318 12:42:39.960091 N<8>[ 30.980829] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked RESULT=skip>
13319 12:42:39.960369 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked RESULT=skip
13321 12:42:39.963739 o KMS driver or no outputs, pipes: 8, outputs: 0
13322 12:42:39.970332 [1mSubtest pipe-F-query-forked: SKIP (0.000s)[0m
13323 12:42:39.983365 <14>[ 31.006548] [IGT] kms_vblank: executing
13324 12:42:39.989950 IGT-Version: 1.2<14>[ 31.011589] [IGT] kms_vblank: exiting, ret=77
13325 12:42:39.993384 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13326 12:42:39.996312 Opened device: /dev/dri/card0
13327 12:42:40.003371 N<8>[ 31.023673] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip>
13328 12:42:40.003648 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip
13330 12:42:40.009497 o KMS driver or no outputs, pipes: 8, outputs: 0
13331 12:42:40.013280 [1mSubtest pipe-F-query-forked-hang: SKIP (0.000s)[0m
13332 12:42:40.026792 <14>[ 31.050093] [IGT] kms_vblank: executing
13333 12:42:40.033562 IGT-Version: 1.2<14>[ 31.055382] [IGT] kms_vblank: exiting, ret=77
13334 12:42:40.036908 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13335 12:42:40.040261 Opened device: /dev/dri/card0
13336 12:42:40.046514 N<8>[ 31.067119] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy RESULT=skip>
13337 12:42:40.046806 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy RESULT=skip
13339 12:42:40.050026 o KMS driver or no outputs, pipes: 8, outputs: 0
13340 12:42:40.056802 [1mSubtest pipe-F-query-busy: SKIP (0.000s)[0m
13341 12:42:40.070129 <14>[ 31.093148] [IGT] kms_vblank: executing
13342 12:42:40.076281 IGT-Version: 1.2<14>[ 31.098246] [IGT] kms_vblank: exiting, ret=77
13343 12:42:40.080022 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13344 12:42:40.083249 Opened device: /dev/dri/card0
13345 12:42:40.089739 N<8>[ 31.110307] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip>
13346 12:42:40.090029 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip
13348 12:42:40.092777 o KMS driver or no outputs, pipes: 8, outputs: 0
13349 12:42:40.099285 [1mSubtest pipe-F-query-busy-hang: SKIP (0.000s)[0m
13350 12:42:40.113277 <14>[ 31.136622] [IGT] kms_vblank: executing
13351 12:42:40.120018 IGT-Version: 1.2<14>[ 31.141577] [IGT] kms_vblank: exiting, ret=77
13352 12:42:40.123113 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13353 12:42:40.126677 Opened device: /dev/dri/card0
13354 12:42:40.136272 No KMS driver or <8>[ 31.154153] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip>
13355 12:42:40.136565 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip
13357 12:42:40.139634 no outputs, pipes: 8, outputs: 0
13358 12:42:40.142545 [1mSubtest pipe-F-query-forked-busy: SKIP (0.000s)[0m
13359 12:42:40.158533 <14>[ 31.182012] [IGT] kms_vblank: executing
13360 12:42:40.165241 IGT-Version: 1.2<14>[ 31.187183] [IGT] kms_vblank: exiting, ret=77
13361 12:42:40.168743 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13362 12:42:40.171892 Opened device: /dev/dri/card0
13363 12:42:40.178807 N<8>[ 31.198884] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip>
13364 12:42:40.179118 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip
13366 12:42:40.185042 o KMS driver or no outputs, pipes: 8, outputs: 0
13367 12:42:40.188155 [1mSubtest pipe-F-query-forked-busy-hang: SKIP (0.000s)[0m
13368 12:42:40.202569 <14>[ 31.226075] [IGT] kms_vblank: executing
13369 12:42:40.209605 IGT-Version: 1.2<14>[ 31.231349] [IGT] kms_vblank: exiting, ret=77
13370 12:42:40.212906 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13371 12:42:40.215782 Opened device: /dev/dri/card0
13372 12:42:40.222374 N<8>[ 31.243183] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle RESULT=skip>
13373 12:42:40.222659 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle RESULT=skip
13375 12:42:40.226082 o KMS driver or no outputs, pipes: 8, outputs: 0
13376 12:42:40.232409 [1mSubtest pipe-F-wait-idle: SKIP (0.000s)[0m
13377 12:42:40.246096 <14>[ 31.269120] [IGT] kms_vblank: executing
13378 12:42:40.252700 IGT-Version: 1.2<14>[ 31.274100] [IGT] kms_vblank: exiting, ret=77
13379 12:42:40.255522 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13380 12:42:40.258975 Opened device: /dev/dri/card0
13381 12:42:40.265837 N<8>[ 31.286310] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip>
13382 12:42:40.266095 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip
13384 12:42:40.268803 o KMS driver or no outputs, pipes: 8, outputs: 0
13385 12:42:40.275521 [1mSubtest pipe-F-wait-idle-hang: SKIP (0.000s)[0m
13386 12:42:40.289609 <14>[ 31.312502] [IGT] kms_vblank: executing
13387 12:42:40.295672 IGT-Version: 1.2<14>[ 31.317596] [IGT] kms_vblank: exiting, ret=77
13388 12:42:40.299099 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13389 12:42:40.302235 Opened device: /dev/dri/card0
13390 12:42:40.309183 N<8>[ 31.329770] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked RESULT=skip>
13391 12:42:40.309464 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked RESULT=skip
13393 12:42:40.312480 o KMS driver or no outputs, pipes: 8, outputs: 0
13394 12:42:40.318930 [1mSubtest pipe-F-wait-forked: SKIP (0.000s)[0m
13395 12:42:40.332384 <14>[ 31.355702] [IGT] kms_vblank: executing
13396 12:42:40.339116 IGT-Version: 1.2<14>[ 31.360651] [IGT] kms_vblank: exiting, ret=77
13397 12:42:40.342089 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13398 12:42:40.345353 Opened device: /dev/dri/card0
13399 12:42:40.352130 N<8>[ 31.372808] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip>
13400 12:42:40.352409 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip
13402 12:42:40.358611 o KMS driver or no outputs, pipes: 8, outputs: 0
13403 12:42:40.362171 [1mSubtest pipe-F-wait-forked-hang: SKIP (0.000s)[0m
13404 12:42:40.376183 <14>[ 31.399281] [IGT] kms_vblank: executing
13405 12:42:40.382798 IGT-Version: 1.2<14>[ 31.404335] [IGT] kms_vblank: exiting, ret=77
13406 12:42:40.385951 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13407 12:42:40.389019 Opened device: /dev/dri/card0
13408 12:42:40.395812 N<8>[ 31.416524] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy RESULT=skip>
13409 12:42:40.396086 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy RESULT=skip
13411 12:42:40.398973 o KMS driver or no outputs, pipes: 8, outputs: 0
13412 12:42:40.405369 [1mSubtest pipe-F-wait-busy: SKIP (0.000s)[0m
13413 12:42:40.418130 <14>[ 31.441673] [IGT] kms_vblank: executing
13414 12:42:40.425219 IGT-Version: 1.2<14>[ 31.446769] [IGT] kms_vblank: exiting, ret=77
13415 12:42:40.428106 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13416 12:42:40.432043 Opened device: /dev/dri/card0
13417 12:42:40.438135 N<8>[ 31.458472] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip>
13418 12:42:40.438417 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip
13420 12:42:40.441177 o KMS driver or no outputs, pipes: 8, outputs: 0
13421 12:42:40.447724 [1mSubtest pipe-F-wait-busy-hang: SKIP (0.000s)[0m
13422 12:42:40.462228 <14>[ 31.485154] [IGT] kms_vblank: executing
13423 12:42:40.468550 IGT-Version: 1.2<14>[ 31.490127] [IGT] kms_vblank: exiting, ret=77
13424 12:42:40.471654 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13425 12:42:40.474986 Opened device: /dev/dri/card0
13426 12:42:40.481779 N<8>[ 31.502299] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip>
13427 12:42:40.482060 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip
13429 12:42:40.484962 o KMS driver or no outputs, pipes: 8, outputs: 0
13430 12:42:40.491735 [1mSubtest pipe-F-wait-forked-busy: SKIP (0.000s)[0m
13431 12:42:40.504590 <14>[ 31.527914] [IGT] kms_vblank: executing
13432 12:42:40.511130 IGT-Version: 1.2<14>[ 31.532931] [IGT] kms_vblank: exiting, ret=77
13433 12:42:40.514766 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13434 12:42:40.517936 Opened device: /dev/dri/card0
13435 12:42:40.524597 N<8>[ 31.544834] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip>
13436 12:42:40.524849 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip
13438 12:42:40.531015 o KMS driver or no outputs, pipes: 8, outputs: 0
13439 12:42:40.534008 [1mSubtest pipe-F-wait-forked-busy-hang: SKIP (0.000s)[0m
13440 12:42:40.547981 <14>[ 31.571229] [IGT] kms_vblank: executing
13441 12:42:40.554564 IGT-Version: 1.2<14>[ 31.576298] [IGT] kms_vblank: exiting, ret=77
13442 12:42:40.558166 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13443 12:42:40.561289 Opened device: /dev/dri/card0
13444 12:42:40.567939 N<8>[ 31.588198] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip>
13445 12:42:40.568194 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip
13447 12:42:40.574784 o KMS driver or no outputs, pipes: 8, outputs: 0
13448 12:42:40.577498 [1mSubtest pipe-F-ts-continuation-idle: SKIP (0.000s)[0m
13449 12:42:40.591780 <14>[ 31.615374] [IGT] kms_vblank: executing
13450 12:42:40.598626 IGT-Version: 1.2<14>[ 31.620350] [IGT] kms_vblank: exiting, ret=77
13451 12:42:40.601682 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13452 12:42:40.605308 Opened device: /dev/dri/card0
13453 12:42:40.611997 N<8>[ 31.632502] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip>
13454 12:42:40.612254 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip
13456 12:42:40.618139 o KMS driver or no outputs, pipes: 8, outputs: 0
13457 12:42:40.621738 [1mSubtest pipe-F-ts-continuation-idle-hang: SKIP (0.000s)[0m
13458 12:42:40.635564 <14>[ 31.658940] [IGT] kms_vblank: executing
13459 12:42:40.642252 IGT-Version: 1.2<14>[ 31.663946] [IGT] kms_vblank: exiting, ret=77
13460 12:42:40.645346 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13461 12:42:40.648774 Opened device: /dev/dri/card0
13462 12:42:40.655332 N<8>[ 31.675944] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip>
13463 12:42:40.655633 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip
13465 12:42:40.662220 o KMS driver or no outputs, pipes: 8, outputs: 0
13466 12:42:40.665121 [1mSubtest pipe-F-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13467 12:42:40.680216 <14>[ 31.703276] [IGT] kms_vblank: executing
13468 12:42:40.686590 IGT-Version: 1.2<14>[ 31.708373] [IGT] kms_vblank: exiting, ret=77
13469 12:42:40.690124 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13470 12:42:40.693579 Opened device: /dev/dri/card0
13471 12:42:40.699761 N<8>[ 31.720426] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip>
13472 12:42:40.700018 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip
13474 12:42:40.706286 o KMS driver or no outputs, pipes: 8, outputs: 0
13475 12:42:40.713057 [1mSubtest pipe-F-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13476 12:42:40.724331 <14>[ 31.747832] [IGT] kms_vblank: executing
13477 12:42:40.731119 IGT-Version: 1.2<14>[ 31.752809] [IGT] kms_vblank: exiting, ret=77
13478 12:42:40.734150 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13479 12:42:40.737864 Opened device: /dev/dri/card0
13480 12:42:40.744430 N<8>[ 31.764708] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip>
13481 12:42:40.744686 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip
13483 12:42:40.751209 o KMS driver or no outputs, pipes: 8, outputs: 0
13484 12:42:40.754057 [1mSubtest pipe-F-ts-continuation-suspend: SKIP (0.000s)[0m
13485 12:42:40.768047 <14>[ 31.791112] [IGT] kms_vblank: executing
13486 12:42:40.774392 IGT-Version: 1.2<14>[ 31.796091] [IGT] kms_vblank: exiting, ret=77
13487 12:42:40.778069 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13488 12:42:40.781083 Opened device: /dev/dri/card0
13489 12:42:40.787720 N<8>[ 31.808134] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip>
13490 12:42:40.787978 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip
13492 12:42:40.794044 o KMS driver or no outputs, pipes: 8, outputs: 0
13493 12:42:40.797312 [1mSubtest pipe-F-ts-continuation-modeset: SKIP (0.000s)[0m
13494 12:42:40.812230 <14>[ 31.835460] [IGT] kms_vblank: executing
13495 12:42:40.818915 IGT-Version: 1.2<14>[ 31.840446] [IGT] kms_vblank: exiting, ret=77
13496 12:42:40.822071 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13497 12:42:40.825215 Opened device: /dev/dri/card0
13498 12:42:40.831821 N<8>[ 31.852585] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip>
13499 12:42:40.832080 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip
13501 12:42:40.838508 o KMS driver or no outputs, pipes: 8, outputs: 0
13502 12:42:40.845231 [1mSubtest pipe-F-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13503 12:42:40.855661 <14>[ 31.878993] [IGT] kms_vblank: executing
13504 12:42:40.862166 IGT-Version: 1.2<14>[ 31.884030] [IGT] kms_vblank: exiting, ret=77
13505 12:42:40.865331 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13506 12:42:40.869028 Opened device: /dev/dri/card0
13507 12:42:40.875263 N<8>[ 31.896035] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip>
13508 12:42:40.875530 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip
13510 12:42:40.882184 o KMS driver or no outputs, pipes: 8, outputs: 0
13511 12:42:40.888453 [1mSubtest pipe-F-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13512 12:42:40.900233 <14>[ 31.923470] [IGT] kms_vblank: executing
13513 12:42:40.907000 IGT-Version: 1.2<14>[ 31.928449] [IGT] kms_vblank: exiting, ret=77
13514 12:42:40.909830 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13515 12:42:40.913553 Opened device: /dev/dri/card0
13516 12:42:40.919673 N<8>[ 31.940425] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip>
13517 12:42:40.919933 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip
13519 12:42:40.923285 o KMS driver or no outputs, pipes: 8, outputs: 0
13520 12:42:40.929900 [1mSubtest pipe-G-accuracy-idle: SKIP (0.000s)[0m
13521 12:42:40.942791 <14>[ 31.965824] [IGT] kms_vblank: executing
13522 12:42:40.949118 IGT-Version: 1.2<14>[ 31.970961] [IGT] kms_vblank: exiting, ret=77
13523 12:42:40.952610 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13524 12:42:40.956012 Opened device: /dev/dri/card0
13525 12:42:40.962066 N<8>[ 31.982702] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle RESULT=skip>
13526 12:42:40.962323 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle RESULT=skip
13528 12:42:40.965559 o KMS driver or no outputs, pipes: 8, outputs: 0
13529 12:42:40.972356 [1mSubtest pipe-G-query-idle: SKIP (0.000s)[0m
13530 12:42:40.984577 <14>[ 32.008051] [IGT] kms_vblank: executing
13531 12:42:40.991154 IGT-Version: 1.2<14>[ 32.013078] [IGT] kms_vblank: exiting, ret=77
13532 12:42:40.994696 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13533 12:42:40.997713 Opened device: /dev/dri/card0
13534 12:42:41.004533 N<8>[ 32.025301] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip>
13535 12:42:41.004830 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip
13537 12:42:41.007503 o KMS driver or no outputs, pipes: 8, outputs: 0
13538 12:42:41.014416 [1mSubtest pipe-G-query-idle-hang: SKIP (0.000s)[0m
13539 12:42:41.027581 <14>[ 32.050947] [IGT] kms_vblank: executing
13540 12:42:41.034235 IGT-Version: 1.2<14>[ 32.055957] [IGT] kms_vblank: exiting, ret=77
13541 12:42:41.037404 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13542 12:42:41.041055 Opened device: /dev/dri/card0
13543 12:42:41.047362 N<8>[ 32.067979] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked RESULT=skip>
13544 12:42:41.047638 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked RESULT=skip
13546 12:42:41.050992 o KMS driver or no outputs, pipes: 8, outputs: 0
13547 12:42:41.057166 [1mSubtest pipe-G-query-forked: SKIP (0.000s)[0m
13548 12:42:41.069557 <14>[ 32.093325] [IGT] kms_vblank: executing
13549 12:42:41.076234 IGT-Version: 1.2<14>[ 32.098314] [IGT] kms_vblank: exiting, ret=77
13550 12:42:41.080047 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13551 12:42:41.083392 Opened device: /dev/dri/card0
13552 12:42:41.089556 N<8>[ 32.110310] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip>
13553 12:42:41.089813 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip
13555 12:42:41.095972 o KMS driver or no outputs, pipes: 8, outputs: 0
13556 12:42:41.099032 [1mSubtest pipe-G-query-forked-hang: SKIP (0.000s)[0m
13557 12:42:41.112558 <14>[ 32.136204] [IGT] kms_vblank: executing
13558 12:42:41.119482 IGT-Version: 1.2<14>[ 32.141274] [IGT] kms_vblank: exiting, ret=77
13559 12:42:41.122715 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13560 12:42:41.125853 Opened device: /dev/dri/card0
13561 12:42:41.129468 No KMS driver or no outputs, pipes: 8, outputs: 0
13562 12:42:41.132433 [1mSubtest pipe-G-query-busy: SKIP (0.000s)[0m
13563 12:42:41.143082 <8>[ 32.163277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy RESULT=skip>
13564 12:42:41.143339 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy RESULT=skip
13566 12:42:41.165888 <14>[ 32.189253] [IGT] kms_vblank: executing
13567 12:42:41.172323 IGT-Version: 1.2<14>[ 32.194257] [IGT] kms_vblank: exiting, ret=77
13568 12:42:41.175784 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13569 12:42:41.179483 Opened device: /dev/dri/card0
13570 12:42:41.185497 N<8>[ 32.206469] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip>
13571 12:42:41.185782 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip
13573 12:42:41.189271 o KMS driver or no outputs, pipes: 8, outputs: 0
13574 12:42:41.195349 [1mSubtest pipe-G-query-busy-hang: SKIP (0.000s)[0m
13575 12:42:41.209399 <14>[ 32.232711] [IGT] kms_vblank: executing
13576 12:42:41.215802 IGT-Version: 1.2<14>[ 32.237927] [IGT] kms_vblank: exiting, ret=77
13577 12:42:41.219167 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13578 12:42:41.222767 Opened device: /dev/dri/card0
13579 12:42:41.228896 N<8>[ 32.249699] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip>
13580 12:42:41.229154 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip
13582 12:42:41.235611 o KMS driver or no outputs, pipes: 8, outputs: 0
13583 12:42:41.239218 [1mSubtest pipe-G-query-forked-busy: SKIP (0.000s)[0m
13584 12:42:41.253376 <14>[ 32.276563] [IGT] kms_vblank: executing
13585 12:42:41.259587 IGT-Version: 1.2<14>[ 32.281649] [IGT] kms_vblank: exiting, ret=77
13586 12:42:41.263241 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13587 12:42:41.266212 Opened device: /dev/dri/card0
13588 12:42:41.273032 N<8>[ 32.293631] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip>
13589 12:42:41.273317 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip
13591 12:42:41.279465 o KMS driver or no outputs, pipes: 8, outputs: 0
13592 12:42:41.282523 [1mSubtest pipe-G-query-forked-busy-hang: SKIP (0.000s)[0m
13593 12:42:41.296995 <14>[ 32.320793] [IGT] kms_vblank: executing
13594 12:42:41.303584 IGT-Version: 1.2<14>[ 32.325812] [IGT] kms_vblank: exiting, ret=77
13595 12:42:41.307076 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13596 12:42:41.310484 Opened device: /dev/dri/card0
13597 12:42:41.316835 No KMS driver or <8>[ 32.338326] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle RESULT=skip>
13598 12:42:41.317105 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle RESULT=skip
13600 12:42:41.320404 no outputs, pipes: 8, outputs: 0
13601 12:42:41.326586 [1mSubtest pipe-G-wait-idle: SKIP (0.000s)[0m
13602 12:42:41.340965 <14>[ 32.364305] [IGT] kms_vblank: executing
13603 12:42:41.347452 IGT-Version: 1.2<14>[ 32.369323] [IGT] kms_vblank: exiting, ret=77
13604 12:42:41.350600 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13605 12:42:41.354248 Opened device: /dev/dri/card0
13606 12:42:41.360471 N<8>[ 32.380805] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip>
13607 12:42:41.360728 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip
13609 12:42:41.364124 o KMS driver or no outputs, pipes: 8, outputs: 0
13610 12:42:41.370796 [1mSubtest pipe-G-wait-idle-hang: SKIP (0.000s)[0m
13611 12:42:41.383684 <14>[ 32.406965] [IGT] kms_vblank: executing
13612 12:42:41.390171 IGT-Version: 1.2<14>[ 32.412043] [IGT] kms_vblank: exiting, ret=77
13613 12:42:41.393550 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13614 12:42:41.396597 Opened device: /dev/dri/card0
13615 12:42:41.403246 N<8>[ 32.423910] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked RESULT=skip>
13616 12:42:41.403516 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked RESULT=skip
13618 12:42:41.406730 o KMS driver or no outputs, pipes: 8, outputs: 0
13619 12:42:41.413279 [1mSubtest pipe-G-wait-forked: SKIP (0.000s)[0m
13620 12:42:41.425772 <14>[ 32.449250] [IGT] kms_vblank: executing
13621 12:42:41.432598 IGT-Version: 1.2<14>[ 32.454253] [IGT] kms_vblank: exiting, ret=77
13622 12:42:41.435635 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13623 12:42:41.439020 Opened device: /dev/dri/card0
13624 12:42:41.445572 N<8>[ 32.466122] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip>
13625 12:42:41.445831 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip
13627 12:42:41.452201 o KMS driver or no outputs, pipes: 8, outputs: 0
13628 12:42:41.455222 [1mSubtest pipe-G-wait-forked-hang: SKIP (0.000s)[0m
13629 12:42:41.469454 <14>[ 32.492814] [IGT] kms_vblank: executing
13630 12:42:41.476024 IGT-Version: 1.2<14>[ 32.497900] [IGT] kms_vblank: exiting, ret=77
13631 12:42:41.479187 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13632 12:42:41.482813 Opened device: /dev/dri/card0
13633 12:42:41.489261 N<8>[ 32.509894] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy RESULT=skip>
13634 12:42:41.489521 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy RESULT=skip
13636 12:42:41.492578 o KMS driver or no outputs, pipes: 8, outputs: 0
13637 12:42:41.498958 [1mSubtest pipe-G-wait-busy: SKIP (0.000s)[0m
13638 12:42:41.512714 <14>[ 32.535819] [IGT] kms_vblank: executing
13639 12:42:41.519119 IGT-Version: 1.2<14>[ 32.540802] [IGT] kms_vblank: exiting, ret=77
13640 12:42:41.522545 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13641 12:42:41.525818 Opened device: /dev/dri/card0
13642 12:42:41.532025 N<8>[ 32.553022] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip>
13643 12:42:41.532283 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip
13645 12:42:41.535571 o KMS driver or no outputs, pipes: 8, outputs: 0
13646 12:42:41.541758 [1mSubtest pipe-G-wait-busy-hang: SKIP (0.000s)[0m
13647 12:42:41.555028 <14>[ 32.578272] [IGT] kms_vblank: executing
13648 12:42:41.561610 IGT-Version: 1.2<14>[ 32.583524] [IGT] kms_vblank: exiting, ret=77
13649 12:42:41.564692 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13650 12:42:41.567788 Opened device: /dev/dri/card0
13651 12:42:41.574605 N<8>[ 32.595290] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip>
13652 12:42:41.574887 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip
13654 12:42:41.581607 o KMS driver or no outputs, pipes: 8, outputs: 0
13655 12:42:41.584623 [1mSubtest pipe-G-wait-forked-busy: SKIP (0.000s)[0m
13656 12:42:41.597539 <14>[ 32.621039] [IGT] kms_vblank: executing
13657 12:42:41.604073 IGT-Version: 1.2<14>[ 32.626047] [IGT] kms_vblank: exiting, ret=77
13658 12:42:41.607695 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13659 12:42:41.610793 Opened device: /dev/dri/card0
13660 12:42:41.617360 N<8>[ 32.637783] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip>
13661 12:42:41.617608 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip
13663 12:42:41.623965 o KMS driver or no outputs, pipes: 8, outputs: 0
13664 12:42:41.626987 [1mSubtest pipe-G-wait-forked-busy-hang: SKIP (0.000s)[0m
13665 12:42:41.641057 <14>[ 32.664381] [IGT] kms_vblank: executing
13666 12:42:41.647783 IGT-Version: 1.2<14>[ 32.669367] [IGT] kms_vblank: exiting, ret=77
13667 12:42:41.650700 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13668 12:42:41.654021 Opened device: /dev/dri/card0
13669 12:42:41.660733 N<8>[ 32.680902] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip>
13670 12:42:41.660991 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip
13672 12:42:41.667571 o KMS driver or no outputs, pipes: 8, outputs: 0
13673 12:42:41.670711 [1mSubtest pipe-G-ts-continuation-idle: SKIP (0.000s)[0m
13674 12:42:41.684138 <14>[ 32.707454] [IGT] kms_vblank: executing
13675 12:42:41.690395 IGT-Version: 1.2<14>[ 32.712480] [IGT] kms_vblank: exiting, ret=77
13676 12:42:41.693971 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13677 12:42:41.696992 Opened device: /dev/dri/card0
13678 12:42:41.703778 N<8>[ 32.724492] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip>
13679 12:42:41.704036 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip
13681 12:42:41.710289 o KMS driver or no outputs, pipes: 8, outputs: 0
13682 12:42:41.713933 [1mSubtest pipe-G-ts-continuation-idle-hang: SKIP (0.000s)[0m
13683 12:42:41.727277 <14>[ 32.750688] [IGT] kms_vblank: executing
13684 12:42:41.733973 IGT-Version: 1.2<14>[ 32.755671] [IGT] kms_vblank: exiting, ret=77
13685 12:42:41.737288 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13686 12:42:41.740343 Opened device: /dev/dri/card0
13687 12:42:41.746954 N<8>[ 32.767671] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip>
13688 12:42:41.747239 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip
13690 12:42:41.753582 o KMS driver or no outputs, pipes: 8, outputs: 0
13691 12:42:41.756581 [1mSubtest pipe-G-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13692 12:42:41.770192 <14>[ 32.793751] [IGT] kms_vblank: executing
13693 12:42:41.777154 IGT-Version: 1.2<14>[ 32.798721] [IGT] kms_vblank: exiting, ret=77
13694 12:42:41.780038 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13695 12:42:41.783761 Opened device: /dev/dri/card0
13696 12:42:41.789803 N<8>[ 32.810549] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip>
13697 12:42:41.790059 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip
13699 12:42:41.796598 o KMS driver or no outputs, pipes: 8, outputs: 0
13700 12:42:41.803335 [1mSubtest pipe-G-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13701 12:42:41.813973 <14>[ 32.837684] [IGT] kms_vblank: executing
13702 12:42:41.820602 IGT-Version: 1.2<14>[ 32.842692] [IGT] kms_vblank: exiting, ret=77
13703 12:42:41.824151 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13704 12:42:41.827652 Opened device: /dev/dri/card0
13705 12:42:41.833677 N<8>[ 32.854363] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip>
13706 12:42:41.833929 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip
13708 12:42:41.840388 o KMS driver or no outputs, pipes: 8, outputs: 0
13709 12:42:41.843877 [1mSubtest pipe-G-ts-continuation-suspend: SKIP (0.000s)[0m
13710 12:42:41.857739 <14>[ 32.881281] [IGT] kms_vblank: executing
13711 12:42:41.864410 IGT-Version: 1.2<14>[ 32.886415] [IGT] kms_vblank: exiting, ret=77
13712 12:42:41.867898 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13713 12:42:41.871313 Opened device: /dev/dri/card0
13714 12:42:41.877453 N<8>[ 32.898009] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip>
13715 12:42:41.877738 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip
13717 12:42:41.884469 o KMS driver or no outputs, pipes: 8, outputs: 0
13718 12:42:41.887677 [1mSubtest pipe-G-ts-continuation-modeset: SKIP (0.000s)[0m
13719 12:42:41.901126 <14>[ 32.924565] [IGT] kms_vblank: executing
13720 12:42:41.907845 IGT-Version: 1.2<14>[ 32.929595] [IGT] kms_vblank: exiting, ret=77
13721 12:42:41.910844 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13722 12:42:41.914572 Opened device: /dev/dri/card0
13723 12:42:41.921184 N<8>[ 32.941465] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip>
13724 12:42:41.921453 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip
13726 12:42:41.927188 o KMS driver or no outputs, pipes: 8, outputs: 0
13727 12:42:41.933933 [1mSubtest pipe-G-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13728 12:42:41.946130 <14>[ 32.969272] [IGT] kms_vblank: executing
13729 12:42:41.952511 IGT-Version: 1.2<14>[ 32.974278] [IGT] kms_vblank: exiting, ret=77
13730 12:42:41.956126 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13731 12:42:41.959039 Opened device: /dev/dri/card0
13732 12:42:41.965722 N<8>[ 32.986413] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip>
13733 12:42:41.965972 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip
13735 12:42:41.972633 o KMS driver or no outputs, pipes: 8, outputs: 0
13736 12:42:41.979125 [1mSubtest pipe-G-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13737 12:42:41.990464 <14>[ 33.013979] [IGT] kms_vblank: executing
13738 12:42:41.997323 IGT-Version: 1.2<14>[ 33.019164] [IGT] kms_vblank: exiting, ret=77
13739 12:42:42.000401 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13740 12:42:42.004014 Opened device: /dev/dri/card0
13741 12:42:42.010292 N<8>[ 33.030597] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip>
13742 12:42:42.010548 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip
13744 12:42:42.013474 o KMS driver or no outputs, pipes: 8, outputs: 0
13745 12:42:42.020389 [1mSubtest pipe-H-accuracy-idle: SKIP (0.000s)[0m
13746 12:42:42.033455 <14>[ 33.057027] [IGT] kms_vblank: executing
13747 12:42:42.040617 IGT-Version: 1.2<14>[ 33.062172] [IGT] kms_vblank: exiting, ret=77
13748 12:42:42.043584 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13749 12:42:42.046635 Opened device: /dev/dri/card0
13750 12:42:42.053234 N<8>[ 33.074267] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle RESULT=skip>
13751 12:42:42.053490 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle RESULT=skip
13753 12:42:42.056716 o KMS driver or no outputs, pipes: 8, outputs: 0
13754 12:42:42.062980 [1mSubtest pipe-H-query-idle: SKIP (0.000s)[0m
13755 12:42:42.076804 <14>[ 33.099852] [IGT] kms_vblank: executing
13756 12:42:42.083363 IGT-Version: 1.2<14>[ 33.104851] [IGT] kms_vblank: exiting, ret=77
13757 12:42:42.086550 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13758 12:42:42.089562 Opened device: /dev/dri/card0
13759 12:42:42.096507 N<8>[ 33.116684] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip>
13760 12:42:42.096762 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip
13762 12:42:42.099352 o KMS driver or no outputs, pipes: 8, outputs: 0
13763 12:42:42.106030 [1mSubtest pipe-H-query-idle-hang: SKIP (0.000s)[0m
13764 12:42:42.120226 <14>[ 33.143482] [IGT] kms_vblank: executing
13765 12:42:42.126339 IGT-Version: 1.2<14>[ 33.148428] [IGT] kms_vblank: exiting, ret=77
13766 12:42:42.129998 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13767 12:42:42.132939 Opened device: /dev/dri/card0
13768 12:42:42.139589 N<8>[ 33.160430] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked RESULT=skip>
13769 12:42:42.139845 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked RESULT=skip
13771 12:42:42.143014 o KMS driver or no outputs, pipes: 8, outputs: 0
13772 12:42:42.149707 [1mSubtest pipe-H-query-forked: SKIP (0.000s)[0m
13773 12:42:42.163030 <14>[ 33.186451] [IGT] kms_vblank: executing
13774 12:42:42.169751 IGT-Version: 1.2<14>[ 33.191785] [IGT] kms_vblank: exiting, ret=77
13775 12:42:42.172778 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13776 12:42:42.176481 Opened device: /dev/dri/card0
13777 12:42:42.182587 N<8>[ 33.203413] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip>
13778 12:42:42.182879 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip
13780 12:42:42.189590 o KMS driver or no outputs, pipes: 8, outputs: 0
13781 12:42:42.192578 [1mSubtest pipe-H-query-forked-hang: SKIP (0.000s)[0m
13782 12:42:42.206686 <14>[ 33.229846] [IGT] kms_vblank: executing
13783 12:42:42.213119 IGT-Version: 1.2<14>[ 33.235217] [IGT] kms_vblank: exiting, ret=77
13784 12:42:42.216302 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13785 12:42:42.219455 Opened device: /dev/dri/card0
13786 12:42:42.226197 N<8>[ 33.246732] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy RESULT=skip>
13787 12:42:42.226454 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy RESULT=skip
13789 12:42:42.229749 o KMS driver or no outputs, pipes: 8, outputs: 0
13790 12:42:42.235697 [1mSubtest pipe-H-query-busy: SKIP (0.000s)[0m
13791 12:42:42.249832 <14>[ 33.273119] [IGT] kms_vblank: executing
13792 12:42:42.256552 IGT-Version: 1.2<14>[ 33.278199] [IGT] kms_vblank: exiting, ret=77
13793 12:42:42.259688 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13794 12:42:42.262692 Opened device: /dev/dri/card0
13795 12:42:42.269408 N<8>[ 33.290347] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip>
13796 12:42:42.269681 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip
13798 12:42:42.273032 o KMS driver or no outputs, pipes: 8, outputs: 0
13799 12:42:42.279060 [1mSubtest pipe-H-query-busy-hang: SKIP (0.000s)[0m
13800 12:42:42.292368 <14>[ 33.315951] [IGT] kms_vblank: executing
13801 12:42:42.299135 IGT-Version: 1.2<14>[ 33.320935] [IGT] kms_vblank: exiting, ret=77
13802 12:42:42.302120 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13803 12:42:42.305712 Opened device: /dev/dri/card0
13804 12:42:42.312476 N<8>[ 33.332740] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip>
13805 12:42:42.312765 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip
13807 12:42:42.319016 o KMS driver or no outputs, pipes: 8, outputs: 0
13808 12:42:42.322167 [1mSubtest pipe-H-query-forked-busy: SKIP (0.000s)[0m
13809 12:42:42.336751 <14>[ 33.359708] [IGT] kms_vblank: executing
13810 12:42:42.342595 IGT-Version: 1.2<14>[ 33.364686] [IGT] kms_vblank: exiting, ret=77
13811 12:42:42.346235 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13812 12:42:42.349758 Opened device: /dev/dri/card0
13813 12:42:42.359403 No KMS driver or <8>[ 33.377033] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip>
13814 12:42:42.359662 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip
13816 12:42:42.362378 no outputs, pipes: 8, outputs: 0
13817 12:42:42.366089 [1mSubtest pipe-H-query-forked-busy-hang: SKIP (0.000s)[0m
13818 12:42:42.380462 <14>[ 33.404213] [IGT] kms_vblank: executing
13819 12:42:42.387077 IGT-Version: 1.2<14>[ 33.409191] [IGT] kms_vblank: exiting, ret=77
13820 12:42:42.390716 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13821 12:42:42.393705 Opened device: /dev/dri/card0
13822 12:42:42.400236 N<8>[ 33.420930] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle RESULT=skip>
13823 12:42:42.400489 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle RESULT=skip
13825 12:42:42.403947 o KMS driver or no outputs, pipes: 8, outputs: 0
13826 12:42:42.409990 [1mSubtest pipe-H-wait-idle: SKIP (0.000s)[0m
13827 12:42:42.423011 <14>[ 33.446390] [IGT] kms_vblank: executing
13828 12:42:42.429530 IGT-Version: 1.2<14>[ 33.451574] [IGT] kms_vblank: exiting, ret=77
13829 12:42:42.432607 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13830 12:42:42.436206 Opened device: /dev/dri/card0
13831 12:42:42.442895 N<8>[ 33.463323] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip>
13832 12:42:42.443150 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip
13834 12:42:42.445949 o KMS driver or no outputs, pipes: 8, outputs: 0
13835 12:42:42.452615 [1mSubtest pipe-H-wait-idle-hang: SKIP (0.000s)[0m
13836 12:42:42.465456 <14>[ 33.488895] [IGT] kms_vblank: executing
13837 12:42:42.472123 IGT-Version: 1.2<14>[ 33.493872] [IGT] kms_vblank: exiting, ret=77
13838 12:42:42.475379 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13839 12:42:42.478491 Opened device: /dev/dri/card0
13840 12:42:42.485204 N<8>[ 33.505713] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked RESULT=skip>
13841 12:42:42.485460 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked RESULT=skip
13843 12:42:42.488171 o KMS driver or no outputs, pipes: 8, outputs: 0
13844 12:42:42.495057 [1mSubtest pipe-H-wait-forked: SKIP (0.000s)[0m
13845 12:42:42.507566 <14>[ 33.531093] [IGT] kms_vblank: executing
13846 12:42:42.514206 IGT-Version: 1.2<14>[ 33.536106] [IGT] kms_vblank: exiting, ret=77
13847 12:42:42.517191 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13848 12:42:42.520641 Opened device: /dev/dri/card0
13849 12:42:42.527115 N<8>[ 33.548050] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip>
13850 12:42:42.527366 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip
13852 12:42:42.533935 o KMS driver or no outputs, pipes: 8, outputs: 0
13853 12:42:42.536921 [1mSubtest pipe-H-wait-forked-hang: SKIP (0.000s)[0m
13854 12:42:42.550123 <14>[ 33.573679] [IGT] kms_vblank: executing
13855 12:42:42.556555 IGT-Version: 1.2<14>[ 33.578681] [IGT] kms_vblank: exiting, ret=77
13856 12:42:42.560136 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13857 12:42:42.563601 Opened device: /dev/dri/card0
13858 12:42:42.569773 N<8>[ 33.590430] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy RESULT=skip>
13859 12:42:42.570027 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy RESULT=skip
13861 12:42:42.573347 o KMS driver or no outputs, pipes: 8, outputs: 0
13862 12:42:42.579895 [1mSubtest pipe-H-wait-busy: SKIP (0.000s)[0m
13863 12:42:42.592134 <14>[ 33.615685] [IGT] kms_vblank: executing
13864 12:42:42.598710 IGT-Version: 1.2<14>[ 33.620660] [IGT] kms_vblank: exiting, ret=77
13865 12:42:42.602372 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13866 12:42:42.605023 Opened device: /dev/dri/card0
13867 12:42:42.612192 N<8>[ 33.632446] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip>
13868 12:42:42.612449 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip
13870 12:42:42.615252 o KMS driver or no outputs, pipes: 8, outputs: 0
13871 12:42:42.621494 [1mSubtest pipe-H-wait-busy-hang: SKIP (0.000s)[0m
13872 12:42:42.634412 <14>[ 33.658220] [IGT] kms_vblank: executing
13873 12:42:42.641254 IGT-Version: 1.2<14>[ 33.663313] [IGT] kms_vblank: exiting, ret=77
13874 12:42:42.644906 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13875 12:42:42.648024 Opened device: /dev/dri/card0
13876 12:42:42.654706 N<8>[ 33.674835] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip>
13877 12:42:42.654963 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip
13879 12:42:42.660767 o KMS driver or no outputs, pipes: 8, outputs: 0
13880 12:42:42.664558 [1mSubtest pipe-H-wait-forked-busy: SKIP (0.000s)[0m
13881 12:42:42.677525 <14>[ 33.700831] [IGT] kms_vblank: executing
13882 12:42:42.683961 IGT-Version: 1.2<14>[ 33.705849] [IGT] kms_vblank: exiting, ret=77
13883 12:42:42.687009 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13884 12:42:42.690198 Opened device: /dev/dri/card0
13885 12:42:42.697119 N<8>[ 33.717696] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip>
13886 12:42:42.697375 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip
13888 12:42:42.703744 o KMS driver or no outputs, pipes: 8, outputs: 0
13889 12:42:42.706785 [1mSubtest pipe-H-wait-forked-busy-hang: SKIP (0.000s)[0m
13890 12:42:42.720436 <14>[ 33.743891] [IGT] kms_vblank: executing
13891 12:42:42.727068 IGT-Version: 1.2<14>[ 33.748874] [IGT] kms_vblank: exiting, ret=77
13892 12:42:42.730582 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13893 12:42:42.733546 Opened device: /dev/dri/card0
13894 12:42:42.740280 N<8>[ 33.760610] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip>
13895 12:42:42.740568 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip
13897 12:42:42.746620 o KMS driver or no outputs, pipes: 8, outputs: 0
13898 12:42:42.750153 [1mSubtest pipe-H-ts-continuation-idle: SKIP (0.000s)[0m
13899 12:42:42.763118 <14>[ 33.786633] [IGT] kms_vblank: executing
13900 12:42:42.769870 IGT-Version: 1.2<14>[ 33.791675] [IGT] kms_vblank: exiting, ret=77
13901 12:42:42.772878 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13902 12:42:42.776322 Opened device: /dev/dri/card0
13903 12:42:42.782630 N<8>[ 33.803644] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip>
13904 12:42:42.782929 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip
13906 12:42:42.789602 o KMS driver or no outputs, pipes: 8, outputs: 0
13907 12:42:42.792675 [1mSubtest pipe-H-ts-continuation-idle-hang: SKIP (0.000s)[0m
13908 12:42:42.806588 <14>[ 33.830173] [IGT] kms_vblank: executing
13909 12:42:42.813271 IGT-Version: 1.2<14>[ 33.835322] [IGT] kms_vblank: exiting, ret=77
13910 12:42:42.816386 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13911 12:42:42.819796 Opened device: /dev/dri/card0
13912 12:42:42.826126 N<8>[ 33.846776] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip>
13913 12:42:42.826388 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip
13915 12:42:42.832721 o KMS driver or no outputs, pipes: 8, outputs: 0
13916 12:42:42.836320 [1mSubtest pipe-H-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13917 12:42:42.850156 <14>[ 33.873589] [IGT] kms_vblank: executing
13918 12:42:42.856452 IGT-Version: 1.2<14>[ 33.878622] [IGT] kms_vblank: exiting, ret=77
13919 12:42:42.860046 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13920 12:42:42.863122 Opened device: /dev/dri/card0
13921 12:42:42.869823 N<8>[ 33.890323] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip>
13922 12:42:42.870084 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip
13924 12:42:42.876589 o KMS driver or no outputs, pipes: 8, outputs: 0
13925 12:42:42.883188 [1mSubtest pipe-H-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13926 12:42:42.893739 <14>[ 33.917336] [IGT] kms_vblank: executing
13927 12:42:42.900245 IGT-Version: 1.2<14>[ 33.922353] [IGT] kms_vblank: exiting, ret=77
13928 12:42:42.903807 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13929 12:42:42.906755 Opened device: /dev/dri/card0
13930 12:42:42.913541 N<8>[ 33.934088] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip>
13931 12:42:42.913797 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip
13933 12:42:42.919627 o KMS driver or no outputs, pipes: 8, outputs: 0
13934 12:42:42.923340 [1mSubtest pipe-H-ts-continuation-suspend: SKIP (0.000s)[0m
13935 12:42:42.936795 <14>[ 33.960572] [IGT] kms_vblank: executing
13936 12:42:42.943602 IGT-Version: 1.2<14>[ 33.965649] [IGT] kms_vblank: exiting, ret=77
13937 12:42:42.946675 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13938 12:42:42.950331 Opened device: /dev/dri/card0
13939 12:42:42.957011 N<8>[ 33.977203] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip>
13940 12:42:42.957271 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip
13942 12:42:42.963554 o KMS driver or no outputs, pipes: 8, outputs: 0
13943 12:42:42.966675 [1mSubtest pipe-H-ts-continuation-modeset: SKIP (0.000s)[0m
13944 12:42:42.980253 <14>[ 34.003833] [IGT] kms_vblank: executing
13945 12:42:42.987222 IGT-Version: 1.2<14>[ 34.008958] [IGT] kms_vblank: exiting, ret=77
13946 12:42:42.990154 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13947 12:42:42.993678 Opened device: /dev/dri/card0
13948 12:42:43.000222 N<8>[ 34.020641] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip>
13949 12:42:43.000488 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip
13951 12:42:43.006941 o KMS driver or no outputs, pipes: 8, outputs: 0
13952 12:42:43.013125 [1mSubtest pipe-H-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13953 12:42:43.024274 <14>[ 34.047668] [IGT] kms_vblank: executing
13954 12:42:43.030575 IGT-Version: 1.2<14>[ 34.052662] [IGT] kms_vblank: exiting, ret=77
13955 12:42:43.034158 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13956 12:42:43.036937 Opened device: /dev/dri/card0
13957 12:42:43.043849 N<8>[ 34.064393] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip>
13958 12:42:43.044129 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip
13960 12:42:43.050530 Received signal: <TESTSET> STOP
13961 12:42:43.050613 Closing test_set kms_vblank
13962 12:42:43.053994 o KMS driver or no outputs, pipe<8>[ 34.075588] <LAVA_SIGNAL_TESTSET STOP>
13963 12:42:43.060518 s: 8, outputs: 0<8>[ 34.081531] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 10724838_1.5.2.3.1>
13964 12:42:43.060604
13965 12:42:43.060842 Received signal: <ENDRUN> 0_igt-kms-mediatek 10724838_1.5.2.3.1
13966 12:42:43.060930 Ending use of test pattern.
13967 12:42:43.060992 Ending test lava.0_igt-kms-mediatek (10724838_1.5.2.3.1), duration 13.75
13969 12:42:43.066683 [1mSubtest pipe-H-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13970 12:42:43.066767 + set +x
13971 12:42:43.070233 <LAVA_TEST_RUNNER EXIT>
13972 12:42:43.070487 ok: lava_test_shell seems to have completed
13973 12:42:43.074462 addfb25-4-tiled:
result: skip
set: kms_addfb_basic
addfb25-bad-modifier:
result: fail
set: kms_addfb_basic
addfb25-framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
addfb25-modifier-no-flag:
result: pass
set: kms_addfb_basic
addfb25-x-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-x-tiled-mismatch-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-small-legacy:
result: skip
set: kms_addfb_basic
addfb25-yf-tiled-legacy:
result: skip
set: kms_addfb_basic
atomic-invalid-params:
result: skip
set: kms_atomic
atomic_plane_damage:
result: skip
set: kms_atomic
bad-pitch-0:
result: pass
set: kms_addfb_basic
bad-pitch-1024:
result: pass
set: kms_addfb_basic
bad-pitch-128:
result: pass
set: kms_addfb_basic
bad-pitch-256:
result: pass
set: kms_addfb_basic
bad-pitch-32:
result: pass
set: kms_addfb_basic
bad-pitch-63:
result: pass
set: kms_addfb_basic
bad-pitch-65536:
result: pass
set: kms_addfb_basic
bad-pitch-999:
result: pass
set: kms_addfb_basic
basic:
result: skip
set: kms_setmode
basic-auth:
result: pass
set: core_auth
basic-clone-single-crtc:
result: skip
set: kms_setmode
basic-x-tiled-legacy:
result: skip
set: kms_addfb_basic
basic-y-tiled-legacy:
result: skip
set: kms_addfb_basic
blob-multiple:
result: pass
set: kms_prop_blob
blob-prop-core:
result: pass
set: kms_prop_blob
blob-prop-lifetime:
result: pass
set: kms_prop_blob
blob-prop-validate:
result: pass
set: kms_prop_blob
bo-too-small:
result: skip
set: kms_addfb_basic
bo-too-small-due-to-tiling:
result: skip
set: kms_addfb_basic
clobberred-modifier:
result: skip
set: kms_addfb_basic
clone-exclusive-crtc:
result: skip
set: kms_setmode
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
crtc-id:
result: skip
set: kms_vblank
crtc-invalid-params:
result: skip
set: kms_atomic
crtc-invalid-params-fence:
result: skip
set: kms_atomic
empty-block:
result: skip
set: drm_read
empty-nonblock:
result: skip
set: drm_read
fault-buffer:
result: skip
set: drm_read
framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
getclient-master-drop:
result: pass
set: core_auth
getclient-simple:
result: pass
set: core_auth
invalid:
result: skip
set: kms_vblank
invalid-buffer:
result: skip
set: drm_read
invalid-clone-exclusive-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc-stealing:
result: skip
set: kms_setmode
invalid-get-prop:
result: pass
set: kms_prop_blob
invalid-get-prop-any:
result: pass
set: kms_prop_blob
invalid-set-prop:
result: pass
set: kms_prop_blob
invalid-set-prop-any:
result: pass
set: kms_prop_blob
invalid-smem-bo-on-discrete:
result: skip
set: kms_addfb_basic
legacy-format:
result: pass
set: kms_addfb_basic
many-magics:
result: pass
set: core_auth
master-rmfb:
result: pass
set: kms_addfb_basic
no-handle:
result: pass
set: kms_addfb_basic
pipe-A-accuracy-idle:
result: skip
set: kms_vblank
pipe-A-query-busy:
result: skip
set: kms_vblank
pipe-A-query-busy-hang:
result: skip
set: kms_vblank
pipe-A-query-forked:
result: skip
set: kms_vblank
pipe-A-query-forked-busy:
result: skip
set: kms_vblank
pipe-A-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-A-query-forked-hang:
result: skip
set: kms_vblank
pipe-A-query-idle:
result: skip
set: kms_vblank
pipe-A-query-idle-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-A-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-A-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-A-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-A-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-A-wait-busy:
result: skip
set: kms_vblank
pipe-A-wait-busy-hang:
result: skip
set: kms_vblank
pipe-A-wait-forked:
result: skip
set: kms_vblank
pipe-A-wait-forked-busy:
result: skip
set: kms_vblank
pipe-A-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-A-wait-forked-hang:
result: skip
set: kms_vblank
pipe-A-wait-idle:
result: skip
set: kms_vblank
pipe-A-wait-idle-hang:
result: skip
set: kms_vblank
pipe-B-accuracy-idle:
result: skip
set: kms_vblank
pipe-B-query-busy:
result: skip
set: kms_vblank
pipe-B-query-busy-hang:
result: skip
set: kms_vblank
pipe-B-query-forked:
result: skip
set: kms_vblank
pipe-B-query-forked-busy:
result: skip
set: kms_vblank
pipe-B-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-B-query-forked-hang:
result: skip
set: kms_vblank
pipe-B-query-idle:
result: skip
set: kms_vblank
pipe-B-query-idle-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-B-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-B-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-B-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-B-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-B-wait-busy:
result: skip
set: kms_vblank
pipe-B-wait-busy-hang:
result: skip
set: kms_vblank
pipe-B-wait-forked:
result: skip
set: kms_vblank
pipe-B-wait-forked-busy:
result: skip
set: kms_vblank
pipe-B-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-B-wait-forked-hang:
result: skip
set: kms_vblank
pipe-B-wait-idle:
result: skip
set: kms_vblank
pipe-B-wait-idle-hang:
result: skip
set: kms_vblank
pipe-C-accuracy-idle:
result: skip
set: kms_vblank
pipe-C-query-busy:
result: skip
set: kms_vblank
pipe-C-query-busy-hang:
result: skip
set: kms_vblank
pipe-C-query-forked:
result: skip
set: kms_vblank
pipe-C-query-forked-busy:
result: skip
set: kms_vblank
pipe-C-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-C-query-forked-hang:
result: skip
set: kms_vblank
pipe-C-query-idle:
result: skip
set: kms_vblank
pipe-C-query-idle-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-C-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-C-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-C-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-C-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-C-wait-busy:
result: skip
set: kms_vblank
pipe-C-wait-busy-hang:
result: skip
set: kms_vblank
pipe-C-wait-forked:
result: skip
set: kms_vblank
pipe-C-wait-forked-busy:
result: skip
set: kms_vblank
pipe-C-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-C-wait-forked-hang:
result: skip
set: kms_vblank
pipe-C-wait-idle:
result: skip
set: kms_vblank
pipe-C-wait-idle-hang:
result: skip
set: kms_vblank
pipe-D-accuracy-idle:
result: skip
set: kms_vblank
pipe-D-query-busy:
result: skip
set: kms_vblank
pipe-D-query-busy-hang:
result: skip
set: kms_vblank
pipe-D-query-forked:
result: skip
set: kms_vblank
pipe-D-query-forked-busy:
result: skip
set: kms_vblank
pipe-D-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-D-query-forked-hang:
result: skip
set: kms_vblank
pipe-D-query-idle:
result: skip
set: kms_vblank
pipe-D-query-idle-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-D-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-D-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-D-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-D-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-D-wait-busy:
result: skip
set: kms_vblank
pipe-D-wait-busy-hang:
result: skip
set: kms_vblank
pipe-D-wait-forked:
result: skip
set: kms_vblank
pipe-D-wait-forked-busy:
result: skip
set: kms_vblank
pipe-D-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-D-wait-forked-hang:
result: skip
set: kms_vblank
pipe-D-wait-idle:
result: skip
set: kms_vblank
pipe-D-wait-idle-hang:
result: skip
set: kms_vblank
pipe-E-accuracy-idle:
result: skip
set: kms_vblank
pipe-E-query-busy:
result: skip
set: kms_vblank
pipe-E-query-busy-hang:
result: skip
set: kms_vblank
pipe-E-query-forked:
result: skip
set: kms_vblank
pipe-E-query-forked-busy:
result: skip
set: kms_vblank
pipe-E-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-E-query-forked-hang:
result: skip
set: kms_vblank
pipe-E-query-idle:
result: skip
set: kms_vblank
pipe-E-query-idle-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-E-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-E-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-E-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-E-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-E-wait-busy:
result: skip
set: kms_vblank
pipe-E-wait-busy-hang:
result: skip
set: kms_vblank
pipe-E-wait-forked:
result: skip
set: kms_vblank
pipe-E-wait-forked-busy:
result: skip
set: kms_vblank
pipe-E-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-E-wait-forked-hang:
result: skip
set: kms_vblank
pipe-E-wait-idle:
result: skip
set: kms_vblank
pipe-E-wait-idle-hang:
result: skip
set: kms_vblank
pipe-F-accuracy-idle:
result: skip
set: kms_vblank
pipe-F-query-busy:
result: skip
set: kms_vblank
pipe-F-query-busy-hang:
result: skip
set: kms_vblank
pipe-F-query-forked:
result: skip
set: kms_vblank
pipe-F-query-forked-busy:
result: skip
set: kms_vblank
pipe-F-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-F-query-forked-hang:
result: skip
set: kms_vblank
pipe-F-query-idle:
result: skip
set: kms_vblank
pipe-F-query-idle-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-F-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-F-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-F-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-F-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-F-wait-busy:
result: skip
set: kms_vblank
pipe-F-wait-busy-hang:
result: skip
set: kms_vblank
pipe-F-wait-forked:
result: skip
set: kms_vblank
pipe-F-wait-forked-busy:
result: skip
set: kms_vblank
pipe-F-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-F-wait-forked-hang:
result: skip
set: kms_vblank
pipe-F-wait-idle:
result: skip
set: kms_vblank
pipe-F-wait-idle-hang:
result: skip
set: kms_vblank
pipe-G-accuracy-idle:
result: skip
set: kms_vblank
pipe-G-query-busy:
result: skip
set: kms_vblank
pipe-G-query-busy-hang:
result: skip
set: kms_vblank
pipe-G-query-forked:
result: skip
set: kms_vblank
pipe-G-query-forked-busy:
result: skip
set: kms_vblank
pipe-G-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-G-query-forked-hang:
result: skip
set: kms_vblank
pipe-G-query-idle:
result: skip
set: kms_vblank
pipe-G-query-idle-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-G-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-G-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-G-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-G-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-G-wait-busy:
result: skip
set: kms_vblank
pipe-G-wait-busy-hang:
result: skip
set: kms_vblank
pipe-G-wait-forked:
result: skip
set: kms_vblank
pipe-G-wait-forked-busy:
result: skip
set: kms_vblank
pipe-G-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-G-wait-forked-hang:
result: skip
set: kms_vblank
pipe-G-wait-idle:
result: skip
set: kms_vblank
pipe-G-wait-idle-hang:
result: skip
set: kms_vblank
pipe-H-accuracy-idle:
result: skip
set: kms_vblank
pipe-H-query-busy:
result: skip
set: kms_vblank
pipe-H-query-busy-hang:
result: skip
set: kms_vblank
pipe-H-query-forked:
result: skip
set: kms_vblank
pipe-H-query-forked-busy:
result: skip
set: kms_vblank
pipe-H-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-H-query-forked-hang:
result: skip
set: kms_vblank
pipe-H-query-idle:
result: skip
set: kms_vblank
pipe-H-query-idle-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-H-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-H-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-H-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-H-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-H-wait-busy:
result: skip
set: kms_vblank
pipe-H-wait-busy-hang:
result: skip
set: kms_vblank
pipe-H-wait-forked:
result: skip
set: kms_vblank
pipe-H-wait-forked-busy:
result: skip
set: kms_vblank
pipe-H-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-H-wait-forked-hang:
result: skip
set: kms_vblank
pipe-H-wait-idle:
result: skip
set: kms_vblank
pipe-H-wait-idle-hang:
result: skip
set: kms_vblank
plane-cursor-legacy:
result: skip
set: kms_atomic
plane-immutable-zpos:
result: skip
set: kms_atomic
plane-invalid-params:
result: skip
set: kms_atomic
plane-invalid-params-fence:
result: skip
set: kms_atomic
plane-overlay-legacy:
result: skip
set: kms_atomic
plane-primary-legacy:
result: skip
set: kms_atomic
plane-primary-overlay-mutable-zpos:
result: skip
set: kms_atomic
short-buffer-block:
result: skip
set: drm_read
short-buffer-nonblock:
result: skip
set: drm_read
short-buffer-wakeup:
result: skip
set: drm_read
size-max:
result: skip
set: kms_addfb_basic
small-bo:
result: skip
set: kms_addfb_basic
test-only:
result: skip
set: kms_atomic
tile-pitch-mismatch:
result: skip
set: kms_addfb_basic
too-high:
result: skip
set: kms_addfb_basic
too-wide:
result: skip
set: kms_addfb_basic
unused-handle:
result: pass
set: kms_addfb_basic
unused-modifier:
result: pass
set: kms_addfb_basic
unused-offsets:
result: pass
set: kms_addfb_basic
unused-pitches:
result: pass
set: kms_addfb_basic
13974 12:42:43.074706 end: 3.1 lava-test-shell (duration 00:00:14) [common]
13975 12:42:43.074801 end: 3 lava-test-retry (duration 00:00:14) [common]
13976 12:42:43.074910 start: 4 finalize (timeout 00:07:10) [common]
13977 12:42:43.075007 start: 4.1 power-off (timeout 00:00:30) [common]
13978 12:42:43.075163 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
13979 12:42:43.150494 >> Command sent successfully.
13980 12:42:43.153035 Returned 0 in 0 seconds
13981 12:42:43.253420 end: 4.1 power-off (duration 00:00:00) [common]
13983 12:42:43.253755 start: 4.2 read-feedback (timeout 00:07:10) [common]
13984 12:42:43.254038 Listened to connection for namespace 'common' for up to 1s
13985 12:42:44.254928 Finalising connection for namespace 'common'
13986 12:42:44.255104 Disconnecting from shell: Finalise
13987 12:42:44.255188 / #
13988 12:42:44.355492 end: 4.2 read-feedback (duration 00:00:01) [common]
13989 12:42:44.355662 end: 4 finalize (duration 00:00:01) [common]
13990 12:42:44.355789 Cleaning after the job
13991 12:42:44.355891 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724838/tftp-deploy-mckrragc/ramdisk
13992 12:42:44.361927 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724838/tftp-deploy-mckrragc/kernel
13993 12:42:44.368053 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724838/tftp-deploy-mckrragc/dtb
13994 12:42:44.368224 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724838/tftp-deploy-mckrragc/modules
13995 12:42:44.373575 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10724838
13996 12:42:44.470716 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10724838
13997 12:42:44.471097 Job finished correctly