Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 34
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 30
- Errors: 0
1 12:40:45.187328 lava-dispatcher, installed at version: 2023.05.1
2 12:40:45.187539 start: 0 validate
3 12:40:45.187669 Start time: 2023-06-14 12:40:45.187662+00:00 (UTC)
4 12:40:45.187787 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:40:45.187916 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230609.0%2Farm64%2Finitrd.cpio.gz exists
6 12:40:45.459234 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:40:45.459460 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:40:45.713679 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:40:45.713868 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:40:45.975856 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:40:45.976040 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230609.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:40:48.346792 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:40:48.346945 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:40:48.607772 validate duration: 3.42
16 12:40:48.608037 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:40:48.608135 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:40:48.608226 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:40:48.608348 Not decompressing ramdisk as can be used compressed.
20 12:40:48.608436 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230609.0/arm64/initrd.cpio.gz
21 12:40:48.608501 saving as /var/lib/lava/dispatcher/tmp/10724845/tftp-deploy-toqeg7bi/ramdisk/initrd.cpio.gz
22 12:40:48.608564 total size: 5625704 (5MB)
23 12:40:48.609575 progress 0% (0MB)
24 12:40:48.611166 progress 5% (0MB)
25 12:40:48.612762 progress 10% (0MB)
26 12:40:48.614143 progress 15% (0MB)
27 12:40:48.615813 progress 20% (1MB)
28 12:40:48.617201 progress 25% (1MB)
29 12:40:48.618735 progress 30% (1MB)
30 12:40:48.620366 progress 35% (1MB)
31 12:40:48.621731 progress 40% (2MB)
32 12:40:48.623275 progress 45% (2MB)
33 12:40:48.624676 progress 50% (2MB)
34 12:40:48.626216 progress 55% (2MB)
35 12:40:48.627851 progress 60% (3MB)
36 12:40:48.629209 progress 65% (3MB)
37 12:40:48.630724 progress 70% (3MB)
38 12:40:48.632145 progress 75% (4MB)
39 12:40:48.633674 progress 80% (4MB)
40 12:40:48.635065 progress 85% (4MB)
41 12:40:48.636617 progress 90% (4MB)
42 12:40:48.638152 progress 95% (5MB)
43 12:40:48.639696 progress 100% (5MB)
44 12:40:48.639889 5MB downloaded in 0.03s (171.29MB/s)
45 12:40:48.640034 end: 1.1.1 http-download (duration 00:00:00) [common]
47 12:40:48.640271 end: 1.1 download-retry (duration 00:00:00) [common]
48 12:40:48.640358 start: 1.2 download-retry (timeout 00:10:00) [common]
49 12:40:48.640443 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 12:40:48.640572 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:40:48.640645 saving as /var/lib/lava/dispatcher/tmp/10724845/tftp-deploy-toqeg7bi/kernel/Image
52 12:40:48.640708 total size: 47581696 (45MB)
53 12:40:48.640767 No compression specified
54 12:40:48.641887 progress 0% (0MB)
55 12:40:48.654241 progress 5% (2MB)
56 12:40:48.666573 progress 10% (4MB)
57 12:40:48.678793 progress 15% (6MB)
58 12:40:48.690833 progress 20% (9MB)
59 12:40:48.702913 progress 25% (11MB)
60 12:40:48.714958 progress 30% (13MB)
61 12:40:48.727066 progress 35% (15MB)
62 12:40:48.739004 progress 40% (18MB)
63 12:40:48.751095 progress 45% (20MB)
64 12:40:48.763242 progress 50% (22MB)
65 12:40:48.775238 progress 55% (24MB)
66 12:40:48.787265 progress 60% (27MB)
67 12:40:48.799103 progress 65% (29MB)
68 12:40:48.811174 progress 70% (31MB)
69 12:40:48.823270 progress 75% (34MB)
70 12:40:48.835184 progress 80% (36MB)
71 12:40:48.847363 progress 85% (38MB)
72 12:40:48.859537 progress 90% (40MB)
73 12:40:48.871757 progress 95% (43MB)
74 12:40:48.883754 progress 100% (45MB)
75 12:40:48.883887 45MB downloaded in 0.24s (186.60MB/s)
76 12:40:48.884032 end: 1.2.1 http-download (duration 00:00:00) [common]
78 12:40:48.884269 end: 1.2 download-retry (duration 00:00:00) [common]
79 12:40:48.884360 start: 1.3 download-retry (timeout 00:10:00) [common]
80 12:40:48.884449 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 12:40:48.884583 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:40:48.884652 saving as /var/lib/lava/dispatcher/tmp/10724845/tftp-deploy-toqeg7bi/dtb/mt8192-asurada-spherion-r0.dtb
83 12:40:48.884714 total size: 46924 (0MB)
84 12:40:48.884774 No compression specified
85 12:40:48.885847 progress 69% (0MB)
86 12:40:48.886129 progress 100% (0MB)
87 12:40:48.886286 0MB downloaded in 0.00s (28.51MB/s)
88 12:40:48.886406 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:40:48.886662 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:40:48.886746 start: 1.4 download-retry (timeout 00:10:00) [common]
92 12:40:48.886829 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 12:40:48.886939 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230609.0/arm64/full.rootfs.tar.xz
94 12:40:48.887007 saving as /var/lib/lava/dispatcher/tmp/10724845/tftp-deploy-toqeg7bi/nfsrootfs/full.rootfs.tar
95 12:40:48.887068 total size: 195135828 (186MB)
96 12:40:48.887127 Using unxz to decompress xz
97 12:40:48.890716 progress 0% (0MB)
98 12:40:49.438981 progress 5% (9MB)
99 12:40:49.932031 progress 10% (18MB)
100 12:40:50.531882 progress 15% (27MB)
101 12:40:50.823288 progress 20% (37MB)
102 12:40:51.288378 progress 25% (46MB)
103 12:40:51.865905 progress 30% (55MB)
104 12:40:52.409283 progress 35% (65MB)
105 12:40:52.955482 progress 40% (74MB)
106 12:40:53.510415 progress 45% (83MB)
107 12:40:54.105253 progress 50% (93MB)
108 12:40:54.694397 progress 55% (102MB)
109 12:40:55.330316 progress 60% (111MB)
110 12:40:55.709244 progress 65% (120MB)
111 12:40:55.792470 progress 70% (130MB)
112 12:40:55.939607 progress 75% (139MB)
113 12:40:56.014812 progress 80% (148MB)
114 12:40:56.064422 progress 85% (158MB)
115 12:40:56.158400 progress 90% (167MB)
116 12:40:56.524509 progress 95% (176MB)
117 12:40:57.092924 progress 100% (186MB)
118 12:40:57.097564 186MB downloaded in 8.21s (22.67MB/s)
119 12:40:57.097862 end: 1.4.1 http-download (duration 00:00:08) [common]
121 12:40:57.098169 end: 1.4 download-retry (duration 00:00:08) [common]
122 12:40:57.098271 start: 1.5 download-retry (timeout 00:09:52) [common]
123 12:40:57.098363 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 12:40:57.098520 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:40:57.098592 saving as /var/lib/lava/dispatcher/tmp/10724845/tftp-deploy-toqeg7bi/modules/modules.tar
126 12:40:57.098655 total size: 8536768 (8MB)
127 12:40:57.098726 Using unxz to decompress xz
128 12:40:57.102347 progress 0% (0MB)
129 12:40:57.123308 progress 5% (0MB)
130 12:40:57.149592 progress 10% (0MB)
131 12:40:57.180610 progress 15% (1MB)
132 12:40:57.205093 progress 20% (1MB)
133 12:40:57.228740 progress 25% (2MB)
134 12:40:57.252975 progress 30% (2MB)
135 12:40:57.276417 progress 35% (2MB)
136 12:40:57.303405 progress 40% (3MB)
137 12:40:57.327614 progress 45% (3MB)
138 12:40:57.353584 progress 50% (4MB)
139 12:40:57.379379 progress 55% (4MB)
140 12:40:57.404981 progress 60% (4MB)
141 12:40:57.430516 progress 65% (5MB)
142 12:40:57.455163 progress 70% (5MB)
143 12:40:57.479614 progress 75% (6MB)
144 12:40:57.503727 progress 80% (6MB)
145 12:40:57.527301 progress 85% (6MB)
146 12:40:57.552154 progress 90% (7MB)
147 12:40:57.577181 progress 95% (7MB)
148 12:40:57.599791 progress 100% (8MB)
149 12:40:57.606411 8MB downloaded in 0.51s (16.03MB/s)
150 12:40:57.606746 end: 1.5.1 http-download (duration 00:00:01) [common]
152 12:40:57.607181 end: 1.5 download-retry (duration 00:00:01) [common]
153 12:40:57.607326 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 12:40:57.607510 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 12:41:01.750189 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10724845/extract-nfsrootfs-wc08wldn
156 12:41:01.750410 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 12:41:01.750554 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 12:41:01.750744 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b
159 12:41:01.750871 makedir: /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b/lava-10724845/bin
160 12:41:01.750969 makedir: /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b/lava-10724845/tests
161 12:41:01.751064 makedir: /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b/lava-10724845/results
162 12:41:01.751166 Creating /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b/lava-10724845/bin/lava-add-keys
163 12:41:01.751305 Creating /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b/lava-10724845/bin/lava-add-sources
164 12:41:01.751442 Creating /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b/lava-10724845/bin/lava-background-process-start
165 12:41:01.751568 Creating /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b/lava-10724845/bin/lava-background-process-stop
166 12:41:01.751692 Creating /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b/lava-10724845/bin/lava-common-functions
167 12:41:01.751813 Creating /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b/lava-10724845/bin/lava-echo-ipv4
168 12:41:01.751936 Creating /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b/lava-10724845/bin/lava-install-packages
169 12:41:01.752056 Creating /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b/lava-10724845/bin/lava-installed-packages
170 12:41:01.752175 Creating /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b/lava-10724845/bin/lava-os-build
171 12:41:01.752295 Creating /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b/lava-10724845/bin/lava-probe-channel
172 12:41:01.752415 Creating /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b/lava-10724845/bin/lava-probe-ip
173 12:41:01.752533 Creating /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b/lava-10724845/bin/lava-target-ip
174 12:41:01.752652 Creating /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b/lava-10724845/bin/lava-target-mac
175 12:41:01.752770 Creating /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b/lava-10724845/bin/lava-target-storage
176 12:41:01.752892 Creating /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b/lava-10724845/bin/lava-test-case
177 12:41:01.753016 Creating /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b/lava-10724845/bin/lava-test-event
178 12:41:01.753136 Creating /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b/lava-10724845/bin/lava-test-feedback
179 12:41:01.753254 Creating /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b/lava-10724845/bin/lava-test-raise
180 12:41:01.753373 Creating /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b/lava-10724845/bin/lava-test-reference
181 12:41:01.753497 Creating /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b/lava-10724845/bin/lava-test-runner
182 12:41:01.753618 Creating /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b/lava-10724845/bin/lava-test-set
183 12:41:01.753738 Creating /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b/lava-10724845/bin/lava-test-shell
184 12:41:01.753868 Updating /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b/lava-10724845/bin/lava-add-keys (debian)
185 12:41:01.757462 Updating /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b/lava-10724845/bin/lava-add-sources (debian)
186 12:41:01.757770 Updating /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b/lava-10724845/bin/lava-install-packages (debian)
187 12:41:01.758045 Updating /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b/lava-10724845/bin/lava-installed-packages (debian)
188 12:41:01.758258 Updating /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b/lava-10724845/bin/lava-os-build (debian)
189 12:41:01.758753 Creating /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b/lava-10724845/environment
190 12:41:01.758870 LAVA metadata
191 12:41:01.758945 - LAVA_JOB_ID=10724845
192 12:41:01.759013 - LAVA_DISPATCHER_IP=192.168.201.1
193 12:41:01.759119 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 12:41:01.759187 skipped lava-vland-overlay
195 12:41:01.759265 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 12:41:01.759532 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 12:41:01.759602 skipped lava-multinode-overlay
198 12:41:01.759677 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 12:41:01.759759 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 12:41:01.759837 Loading test definitions
201 12:41:01.759930 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 12:41:01.760002 Using /lava-10724845 at stage 0
203 12:41:01.760275 uuid=10724845_1.6.2.3.1 testdef=None
204 12:41:01.760362 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 12:41:01.760447 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 12:41:01.760893 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 12:41:01.761138 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 12:41:01.761691 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 12:41:01.761923 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 12:41:01.762453 runner path: /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b/lava-10724845/0/tests/0_timesync-off test_uuid 10724845_1.6.2.3.1
213 12:41:01.762605 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 12:41:01.762983 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 12:41:01.763060 Using /lava-10724845 at stage 0
217 12:41:01.763157 Fetching tests from https://github.com/kernelci/test-definitions.git
218 12:41:01.763234 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b/lava-10724845/0/tests/1_kselftest-alsa'
219 12:41:08.293835 Running '/usr/bin/git checkout kernelci.org
220 12:41:08.453648 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b/lava-10724845/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 12:41:08.454396 uuid=10724845_1.6.2.3.5 testdef=None
222 12:41:08.454559 end: 1.6.2.3.5 git-repo-action (duration 00:00:07) [common]
224 12:41:08.454858 start: 1.6.2.3.6 test-overlay (timeout 00:09:40) [common]
225 12:41:08.455631 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 12:41:08.455862 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:40) [common]
228 12:41:08.456957 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 12:41:08.457193 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:40) [common]
231 12:41:08.458108 runner path: /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b/lava-10724845/0/tests/1_kselftest-alsa test_uuid 10724845_1.6.2.3.5
232 12:41:08.458202 BOARD='mt8192-asurada-spherion-r0'
233 12:41:08.458268 BRANCH='cip'
234 12:41:08.458329 SKIPFILE='/dev/null'
235 12:41:08.458388 SKIP_INSTALL='True'
236 12:41:08.458445 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 12:41:08.458504 TST_CASENAME=''
238 12:41:08.458559 TST_CMDFILES='alsa'
239 12:41:08.458698 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 12:41:08.458904 Creating lava-test-runner.conf files
242 12:41:08.458969 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10724845/lava-overlay-zpz7fr6b/lava-10724845/0 for stage 0
243 12:41:08.459060 - 0_timesync-off
244 12:41:08.459131 - 1_kselftest-alsa
245 12:41:08.459226 end: 1.6.2.3 test-definition (duration 00:00:07) [common]
246 12:41:08.459317 start: 1.6.2.4 compress-overlay (timeout 00:09:40) [common]
247 12:41:15.953718 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 12:41:15.953883 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:33) [common]
249 12:41:15.954028 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 12:41:15.954137 end: 1.6.2 lava-overlay (duration 00:00:14) [common]
251 12:41:15.954227 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:33) [common]
252 12:41:16.124979 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 12:41:16.125362 start: 1.6.4 extract-modules (timeout 00:09:32) [common]
254 12:41:16.125483 extracting modules file /var/lib/lava/dispatcher/tmp/10724845/tftp-deploy-toqeg7bi/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10724845/extract-nfsrootfs-wc08wldn
255 12:41:16.328690 extracting modules file /var/lib/lava/dispatcher/tmp/10724845/tftp-deploy-toqeg7bi/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10724845/extract-overlay-ramdisk-_r42r7tz/ramdisk
256 12:41:16.535184 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 12:41:16.535488 start: 1.6.5 apply-overlay-tftp (timeout 00:09:32) [common]
258 12:41:16.535591 [common] Applying overlay to NFS
259 12:41:16.535661 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10724845/compress-overlay-oooyvlnm/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10724845/extract-nfsrootfs-wc08wldn
260 12:41:17.441689 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 12:41:17.441863 start: 1.6.6 configure-preseed-file (timeout 00:09:31) [common]
262 12:41:17.441960 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 12:41:17.442050 start: 1.6.7 compress-ramdisk (timeout 00:09:31) [common]
264 12:41:17.442138 Building ramdisk /var/lib/lava/dispatcher/tmp/10724845/extract-overlay-ramdisk-_r42r7tz/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10724845/extract-overlay-ramdisk-_r42r7tz/ramdisk
265 12:41:17.776862 >> 128929 blocks
266 12:41:19.877849 rename /var/lib/lava/dispatcher/tmp/10724845/extract-overlay-ramdisk-_r42r7tz/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10724845/tftp-deploy-toqeg7bi/ramdisk/ramdisk.cpio.gz
267 12:41:19.878327 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 12:41:19.878471 start: 1.6.8 prepare-kernel (timeout 00:09:29) [common]
269 12:41:19.878573 start: 1.6.8.1 prepare-fit (timeout 00:09:29) [common]
270 12:41:19.878710 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10724845/tftp-deploy-toqeg7bi/kernel/Image'
271 12:41:32.050199 Returned 0 in 12 seconds
272 12:41:32.150791 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10724845/tftp-deploy-toqeg7bi/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10724845/tftp-deploy-toqeg7bi/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10724845/tftp-deploy-toqeg7bi/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10724845/tftp-deploy-toqeg7bi/kernel/image.itb
273 12:41:32.488180 output: FIT description: Kernel Image image with one or more FDT blobs
274 12:41:32.488535 output: Created: Wed Jun 14 13:41:32 2023
275 12:41:32.488614 output: Image 0 (kernel-1)
276 12:41:32.488682 output: Description:
277 12:41:32.488745 output: Created: Wed Jun 14 13:41:32 2023
278 12:41:32.488828 output: Type: Kernel Image
279 12:41:32.488893 output: Compression: lzma compressed
280 12:41:32.488954 output: Data Size: 10442380 Bytes = 10197.64 KiB = 9.96 MiB
281 12:41:32.489013 output: Architecture: AArch64
282 12:41:32.489071 output: OS: Linux
283 12:41:32.489129 output: Load Address: 0x00000000
284 12:41:32.489189 output: Entry Point: 0x00000000
285 12:41:32.489245 output: Hash algo: crc32
286 12:41:32.489298 output: Hash value: ced21bfe
287 12:41:32.489366 output: Image 1 (fdt-1)
288 12:41:32.489428 output: Description: mt8192-asurada-spherion-r0
289 12:41:32.489483 output: Created: Wed Jun 14 13:41:32 2023
290 12:41:32.489537 output: Type: Flat Device Tree
291 12:41:32.489590 output: Compression: uncompressed
292 12:41:32.489643 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 12:41:32.489696 output: Architecture: AArch64
294 12:41:32.489768 output: Hash algo: crc32
295 12:41:32.489822 output: Hash value: 1df858fa
296 12:41:32.489875 output: Image 2 (ramdisk-1)
297 12:41:32.489928 output: Description: unavailable
298 12:41:32.489981 output: Created: Wed Jun 14 13:41:32 2023
299 12:41:32.490033 output: Type: RAMDisk Image
300 12:41:32.490086 output: Compression: Unknown Compression
301 12:41:32.490149 output: Data Size: 18601629 Bytes = 18165.65 KiB = 17.74 MiB
302 12:41:32.490237 output: Architecture: AArch64
303 12:41:32.490322 output: OS: Linux
304 12:41:32.490404 output: Load Address: unavailable
305 12:41:32.490492 output: Entry Point: unavailable
306 12:41:32.490549 output: Hash algo: crc32
307 12:41:32.490602 output: Hash value: 290263c3
308 12:41:32.490669 output: Default Configuration: 'conf-1'
309 12:41:32.490735 output: Configuration 0 (conf-1)
310 12:41:32.490787 output: Description: mt8192-asurada-spherion-r0
311 12:41:32.490840 output: Kernel: kernel-1
312 12:41:32.490898 output: Init Ramdisk: ramdisk-1
313 12:41:32.491025 output: FDT: fdt-1
314 12:41:32.491158 output: Loadables: kernel-1
315 12:41:32.491243 output:
316 12:41:32.491496 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 12:41:32.491604 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 12:41:32.491754 end: 1.6 prepare-tftp-overlay (duration 00:00:35) [common]
319 12:41:32.491855 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:16) [common]
320 12:41:32.491969 No LXC device requested
321 12:41:32.492059 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 12:41:32.492165 start: 1.8 deploy-device-env (timeout 00:09:16) [common]
323 12:41:32.492271 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 12:41:32.492356 Checking files for TFTP limit of 4294967296 bytes.
325 12:41:32.492972 end: 1 tftp-deploy (duration 00:00:44) [common]
326 12:41:32.493093 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 12:41:32.493218 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 12:41:32.493346 substitutions:
329 12:41:32.493431 - {DTB}: 10724845/tftp-deploy-toqeg7bi/dtb/mt8192-asurada-spherion-r0.dtb
330 12:41:32.493538 - {INITRD}: 10724845/tftp-deploy-toqeg7bi/ramdisk/ramdisk.cpio.gz
331 12:41:32.493628 - {KERNEL}: 10724845/tftp-deploy-toqeg7bi/kernel/Image
332 12:41:32.493752 - {LAVA_MAC}: None
333 12:41:32.493841 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10724845/extract-nfsrootfs-wc08wldn
334 12:41:32.493963 - {NFS_SERVER_IP}: 192.168.201.1
335 12:41:32.494052 - {PRESEED_CONFIG}: None
336 12:41:32.494137 - {PRESEED_LOCAL}: None
337 12:41:32.494248 - {RAMDISK}: 10724845/tftp-deploy-toqeg7bi/ramdisk/ramdisk.cpio.gz
338 12:41:32.494335 - {ROOT_PART}: None
339 12:41:32.494445 - {ROOT}: None
340 12:41:32.494558 - {SERVER_IP}: 192.168.201.1
341 12:41:32.494656 - {TEE}: None
342 12:41:32.494782 Parsed boot commands:
343 12:41:32.494867 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 12:41:32.495115 Parsed boot commands: tftpboot 192.168.201.1 10724845/tftp-deploy-toqeg7bi/kernel/image.itb 10724845/tftp-deploy-toqeg7bi/kernel/cmdline
345 12:41:32.495252 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 12:41:32.495388 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 12:41:32.495514 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 12:41:32.495629 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 12:41:32.495729 Not connected, no need to disconnect.
350 12:41:32.495834 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 12:41:32.495982 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 12:41:32.496079 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-3'
353 12:41:32.499965 Setting prompt string to ['lava-test: # ']
354 12:41:32.500352 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 12:41:32.500472 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 12:41:32.500573 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 12:41:32.500671 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 12:41:32.500899 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
359 12:41:37.634888 >> Command sent successfully.
360 12:41:37.637295 Returned 0 in 5 seconds
361 12:41:37.737689 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 12:41:37.738023 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 12:41:37.738126 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 12:41:37.738216 Setting prompt string to 'Starting depthcharge on Spherion...'
366 12:41:37.738284 Changing prompt to 'Starting depthcharge on Spherion...'
367 12:41:37.738355 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 12:41:37.738622 [Enter `^Ec?' for help]
369 12:41:37.914510
370 12:41:37.914651
371 12:41:37.914726 F0: 102B 0000
372 12:41:37.914789
373 12:41:37.914849 F3: 1001 0000 [0200]
374 12:41:37.918051
375 12:41:37.918135 F3: 1001 0000
376 12:41:37.918203
377 12:41:37.918266 F7: 102D 0000
378 12:41:37.918326
379 12:41:37.921273 F1: 0000 0000
380 12:41:37.921358
381 12:41:37.921424 V0: 0000 0000 [0001]
382 12:41:37.921489
383 12:41:37.925269 00: 0007 8000
384 12:41:37.925357
385 12:41:37.925424 01: 0000 0000
386 12:41:37.925488
387 12:41:37.928141 BP: 0C00 0209 [0000]
388 12:41:37.928224
389 12:41:37.928290 G0: 1182 0000
390 12:41:37.928353
391 12:41:37.931474 EC: 0000 0021 [4000]
392 12:41:37.931558
393 12:41:37.931624 S7: 0000 0000 [0000]
394 12:41:37.931686
395 12:41:37.934926 CC: 0000 0000 [0001]
396 12:41:37.935010
397 12:41:37.935075 T0: 0000 0040 [010F]
398 12:41:37.935138
399 12:41:37.937898 Jump to BL
400 12:41:37.937981
401 12:41:37.961245
402 12:41:37.961335
403 12:41:37.961402
404 12:41:37.968243 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 12:41:37.971598 ARM64: Exception handlers installed.
406 12:41:37.975495 ARM64: Testing exception
407 12:41:37.978565 ARM64: Done test exception
408 12:41:37.985364 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 12:41:37.995510 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 12:41:38.002234 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 12:41:38.012694 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 12:41:38.018972 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 12:41:38.029378 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 12:41:38.040097 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 12:41:38.046725 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 12:41:38.064369 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 12:41:38.067771 WDT: Last reset was cold boot
418 12:41:38.071723 SPI1(PAD0) initialized at 2873684 Hz
419 12:41:38.074321 SPI5(PAD0) initialized at 992727 Hz
420 12:41:38.077723 VBOOT: Loading verstage.
421 12:41:38.084728 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 12:41:38.088059 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 12:41:38.090943 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 12:41:38.094665 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 12:41:38.101666 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 12:41:38.108616 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 12:41:38.119399 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 12:41:38.119485
429 12:41:38.119553
430 12:41:38.129529 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 12:41:38.132971 ARM64: Exception handlers installed.
432 12:41:38.136662 ARM64: Testing exception
433 12:41:38.136747 ARM64: Done test exception
434 12:41:38.142992 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 12:41:38.146054 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 12:41:38.161400 Probing TPM: . done!
437 12:41:38.161511 TPM ready after 0 ms
438 12:41:38.168979 Connected to device vid:did:rid of 1ae0:0028:00
439 12:41:38.175523 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 12:41:38.234500 Initialized TPM device CR50 revision 0
441 12:41:38.245097 tlcl_send_startup: Startup return code is 0
442 12:41:38.245233 TPM: setup succeeded
443 12:41:38.256747 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 12:41:38.265581 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 12:41:38.277292 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 12:41:38.287413 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 12:41:38.291253 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 12:41:38.294666 in-header: 03 07 00 00 08 00 00 00
449 12:41:38.298532 in-data: aa e4 47 04 13 02 00 00
450 12:41:38.301828 Chrome EC: UHEPI supported
451 12:41:38.308801 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 12:41:38.312953 in-header: 03 ad 00 00 08 00 00 00
453 12:41:38.316725 in-data: 00 20 20 08 00 00 00 00
454 12:41:38.316808 Phase 1
455 12:41:38.320332 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 12:41:38.327556 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 12:41:38.331550 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 12:41:38.334367 Recovery requested (1009000e)
459 12:41:38.344305 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 12:41:38.350112 tlcl_extend: response is 0
461 12:41:38.360195 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 12:41:38.366123 tlcl_extend: response is 0
463 12:41:38.372980 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 12:41:38.393150 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 12:41:38.399612 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 12:41:38.399723
467 12:41:38.399817
468 12:41:38.410700 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 12:41:38.413827 ARM64: Exception handlers installed.
470 12:41:38.413911 ARM64: Testing exception
471 12:41:38.417493 ARM64: Done test exception
472 12:41:38.438969 pmic_efuse_setting: Set efuses in 11 msecs
473 12:41:38.442574 pmwrap_interface_init: Select PMIF_VLD_RDY
474 12:41:38.449019 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 12:41:38.452204 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 12:41:38.459218 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 12:41:38.462733 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 12:41:38.466097 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 12:41:38.473251 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 12:41:38.476709 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 12:41:38.480819 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 12:41:38.487631 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 12:41:38.491858 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 12:41:38.495305 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 12:41:38.499142 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 12:41:38.502624 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 12:41:38.510671 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 12:41:38.517604 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 12:41:38.521519 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 12:41:38.528741 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 12:41:38.532295 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 12:41:38.540147 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 12:41:38.543949 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 12:41:38.550782 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 12:41:38.554885 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 12:41:38.562020 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 12:41:38.565617 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 12:41:38.573425 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 12:41:38.576993 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 12:41:38.584283 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 12:41:38.587784 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 12:41:38.591503 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 12:41:38.598658 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 12:41:38.602587 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 12:41:38.605861 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 12:41:38.613119 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 12:41:38.617118 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 12:41:38.624381 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 12:41:38.628000 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 12:41:38.631817 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 12:41:38.639634 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 12:41:38.642915 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 12:41:38.646437 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 12:41:38.650157 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 12:41:38.653750 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 12:41:38.661442 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 12:41:38.664930 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 12:41:38.668805 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 12:41:38.672393 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 12:41:38.676012 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 12:41:38.679515 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 12:41:38.687090 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 12:41:38.690865 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 12:41:38.694541 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 12:41:38.701672 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 12:41:38.708954 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 12:41:38.712740 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 12:41:38.723540 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 12:41:38.731437 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 12:41:38.734794 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 12:41:38.742335 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 12:41:38.745433 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 12:41:38.753490 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x28
534 12:41:38.756583 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 12:41:38.760291 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 12:41:38.767590 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 12:41:38.775648 [RTC]rtc_get_frequency_meter,154: input=15, output=789
538 12:41:38.785910 [RTC]rtc_get_frequency_meter,154: input=23, output=978
539 12:41:38.795038 [RTC]rtc_get_frequency_meter,154: input=19, output=883
540 12:41:38.804225 [RTC]rtc_get_frequency_meter,154: input=17, output=837
541 12:41:38.813887 [RTC]rtc_get_frequency_meter,154: input=16, output=814
542 12:41:38.823493 [RTC]rtc_get_frequency_meter,154: input=15, output=788
543 12:41:38.833719 [RTC]rtc_get_frequency_meter,154: input=16, output=813
544 12:41:38.837010 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
545 12:41:38.840925 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
546 12:41:38.844841 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 12:41:38.851834 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 12:41:38.855433 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 12:41:38.859785 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 12:41:38.862959 ADC[4]: Raw value=900959 ID=7
551 12:41:38.863058 ADC[3]: Raw value=213336 ID=1
552 12:41:38.866984 RAM Code: 0x71
553 12:41:38.870755 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 12:41:38.874520 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 12:41:38.884360 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 12:41:38.892000 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 12:41:38.895868 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 12:41:38.898854 in-header: 03 07 00 00 08 00 00 00
559 12:41:38.902209 in-data: aa e4 47 04 13 02 00 00
560 12:41:38.902310 Chrome EC: UHEPI supported
561 12:41:38.909413 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 12:41:38.913603 in-header: 03 ed 00 00 08 00 00 00
563 12:41:38.917442 in-data: 80 20 60 08 00 00 00 00
564 12:41:38.921004 MRC: failed to locate region type 0.
565 12:41:38.928134 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 12:41:38.932215 DRAM-K: Running full calibration
567 12:41:38.935744 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 12:41:38.939675 header.status = 0x0
569 12:41:38.943488 header.version = 0x6 (expected: 0x6)
570 12:41:38.947319 header.size = 0xd00 (expected: 0xd00)
571 12:41:38.947475 header.flags = 0x0
572 12:41:38.954072 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 12:41:38.971619 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 12:41:38.978810 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 12:41:38.981861 dram_init: ddr_geometry: 2
576 12:41:38.981950 [EMI] MDL number = 2
577 12:41:38.985600 [EMI] Get MDL freq = 0
578 12:41:38.985682 dram_init: ddr_type: 0
579 12:41:38.989442 is_discrete_lpddr4: 1
580 12:41:38.993537 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 12:41:38.993620
582 12:41:38.993688
583 12:41:38.996956 [Bian_co] ETT version 0.0.0.1
584 12:41:39.000616 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 12:41:39.000697
586 12:41:39.004181 dramc_set_vcore_voltage set vcore to 650000
587 12:41:39.004259 Read voltage for 800, 4
588 12:41:39.007814 Vio18 = 0
589 12:41:39.007895 Vcore = 650000
590 12:41:39.007969 Vdram = 0
591 12:41:39.011253 Vddq = 0
592 12:41:39.011334 Vmddr = 0
593 12:41:39.015082 dram_init: config_dvfs: 1
594 12:41:39.018869 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 12:41:39.022591 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 12:41:39.029073 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
597 12:41:39.032542 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
598 12:41:39.035867 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
599 12:41:39.038560 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
600 12:41:39.041937 MEM_TYPE=3, freq_sel=18
601 12:41:39.045240 sv_algorithm_assistance_LP4_1600
602 12:41:39.048755 ============ PULL DRAM RESETB DOWN ============
603 12:41:39.052441 ========== PULL DRAM RESETB DOWN end =========
604 12:41:39.058673 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 12:41:39.062035 ===================================
606 12:41:39.062116 LPDDR4 DRAM CONFIGURATION
607 12:41:39.065755 ===================================
608 12:41:39.068559 EX_ROW_EN[0] = 0x0
609 12:41:39.068635 EX_ROW_EN[1] = 0x0
610 12:41:39.072519 LP4Y_EN = 0x0
611 12:41:39.072599 WORK_FSP = 0x0
612 12:41:39.075717 WL = 0x2
613 12:41:39.075801 RL = 0x2
614 12:41:39.079245 BL = 0x2
615 12:41:39.079324 RPST = 0x0
616 12:41:39.082226 RD_PRE = 0x0
617 12:41:39.082300 WR_PRE = 0x1
618 12:41:39.085469 WR_PST = 0x0
619 12:41:39.085546 DBI_WR = 0x0
620 12:41:39.088988 DBI_RD = 0x0
621 12:41:39.092549 OTF = 0x1
622 12:41:39.095594 ===================================
623 12:41:39.095678 ===================================
624 12:41:39.099121 ANA top config
625 12:41:39.102333 ===================================
626 12:41:39.105999 DLL_ASYNC_EN = 0
627 12:41:39.106078 ALL_SLAVE_EN = 1
628 12:41:39.109108 NEW_RANK_MODE = 1
629 12:41:39.112670 DLL_IDLE_MODE = 1
630 12:41:39.115751 LP45_APHY_COMB_EN = 1
631 12:41:39.115832 TX_ODT_DIS = 1
632 12:41:39.119129 NEW_8X_MODE = 1
633 12:41:39.122383 ===================================
634 12:41:39.125843 ===================================
635 12:41:39.129038 data_rate = 1600
636 12:41:39.132374 CKR = 1
637 12:41:39.135984 DQ_P2S_RATIO = 8
638 12:41:39.139511 ===================================
639 12:41:39.142815 CA_P2S_RATIO = 8
640 12:41:39.142888 DQ_CA_OPEN = 0
641 12:41:39.146067 DQ_SEMI_OPEN = 0
642 12:41:39.149501 CA_SEMI_OPEN = 0
643 12:41:39.152738 CA_FULL_RATE = 0
644 12:41:39.156317 DQ_CKDIV4_EN = 1
645 12:41:39.159241 CA_CKDIV4_EN = 1
646 12:41:39.159332 CA_PREDIV_EN = 0
647 12:41:39.162521 PH8_DLY = 0
648 12:41:39.165866 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 12:41:39.169217 DQ_AAMCK_DIV = 4
650 12:41:39.172888 CA_AAMCK_DIV = 4
651 12:41:39.172963 CA_ADMCK_DIV = 4
652 12:41:39.176316 DQ_TRACK_CA_EN = 0
653 12:41:39.179367 CA_PICK = 800
654 12:41:39.182999 CA_MCKIO = 800
655 12:41:39.186889 MCKIO_SEMI = 0
656 12:41:39.189820 PLL_FREQ = 3068
657 12:41:39.193186 DQ_UI_PI_RATIO = 32
658 12:41:39.193297 CA_UI_PI_RATIO = 0
659 12:41:39.196690 ===================================
660 12:41:39.200538 ===================================
661 12:41:39.204669 memory_type:LPDDR4
662 12:41:39.204750 GP_NUM : 10
663 12:41:39.208463 SRAM_EN : 1
664 12:41:39.208545 MD32_EN : 0
665 12:41:39.211840 ===================================
666 12:41:39.215936 [ANA_INIT] >>>>>>>>>>>>>>
667 12:41:39.219834 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 12:41:39.222373 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 12:41:39.225676 ===================================
670 12:41:39.225761 data_rate = 1600,PCW = 0X7600
671 12:41:39.229064 ===================================
672 12:41:39.232305 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 12:41:39.239221 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 12:41:39.245862 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 12:41:39.249238 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 12:41:39.252721 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 12:41:39.256150 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 12:41:39.259382 [ANA_INIT] flow start
679 12:41:39.259479 [ANA_INIT] PLL >>>>>>>>
680 12:41:39.262465 [ANA_INIT] PLL <<<<<<<<
681 12:41:39.265727 [ANA_INIT] MIDPI >>>>>>>>
682 12:41:39.269187 [ANA_INIT] MIDPI <<<<<<<<
683 12:41:39.269271 [ANA_INIT] DLL >>>>>>>>
684 12:41:39.272402 [ANA_INIT] flow end
685 12:41:39.276047 ============ LP4 DIFF to SE enter ============
686 12:41:39.279613 ============ LP4 DIFF to SE exit ============
687 12:41:39.282498 [ANA_INIT] <<<<<<<<<<<<<
688 12:41:39.285791 [Flow] Enable top DCM control >>>>>
689 12:41:39.289653 [Flow] Enable top DCM control <<<<<
690 12:41:39.292394 Enable DLL master slave shuffle
691 12:41:39.296311 ==============================================================
692 12:41:39.299262 Gating Mode config
693 12:41:39.306329 ==============================================================
694 12:41:39.306413 Config description:
695 12:41:39.316308 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 12:41:39.323273 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 12:41:39.329399 SELPH_MODE 0: By rank 1: By Phase
698 12:41:39.332701 ==============================================================
699 12:41:39.335957 GAT_TRACK_EN = 1
700 12:41:39.339255 RX_GATING_MODE = 2
701 12:41:39.343184 RX_GATING_TRACK_MODE = 2
702 12:41:39.345940 SELPH_MODE = 1
703 12:41:39.349553 PICG_EARLY_EN = 1
704 12:41:39.353075 VALID_LAT_VALUE = 1
705 12:41:39.356186 ==============================================================
706 12:41:39.359378 Enter into Gating configuration >>>>
707 12:41:39.363218 Exit from Gating configuration <<<<
708 12:41:39.366358 Enter into DVFS_PRE_config >>>>>
709 12:41:39.379300 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 12:41:39.379460 Exit from DVFS_PRE_config <<<<<
711 12:41:39.383129 Enter into PICG configuration >>>>
712 12:41:39.386093 Exit from PICG configuration <<<<
713 12:41:39.389646 [RX_INPUT] configuration >>>>>
714 12:41:39.393122 [RX_INPUT] configuration <<<<<
715 12:41:39.399746 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 12:41:39.403261 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 12:41:39.410029 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 12:41:39.416670 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 12:41:39.423667 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 12:41:39.427529 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 12:41:39.433754 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 12:41:39.437148 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 12:41:39.440139 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 12:41:39.443602 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 12:41:39.447033 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 12:41:39.453675 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 12:41:39.457433 ===================================
728 12:41:39.460852 LPDDR4 DRAM CONFIGURATION
729 12:41:39.460927 ===================================
730 12:41:39.464003 EX_ROW_EN[0] = 0x0
731 12:41:39.466768 EX_ROW_EN[1] = 0x0
732 12:41:39.466845 LP4Y_EN = 0x0
733 12:41:39.470514 WORK_FSP = 0x0
734 12:41:39.470617 WL = 0x2
735 12:41:39.473483 RL = 0x2
736 12:41:39.473586 BL = 0x2
737 12:41:39.477107 RPST = 0x0
738 12:41:39.477211 RD_PRE = 0x0
739 12:41:39.480450 WR_PRE = 0x1
740 12:41:39.480552 WR_PST = 0x0
741 12:41:39.483709 DBI_WR = 0x0
742 12:41:39.483787 DBI_RD = 0x0
743 12:41:39.487436 OTF = 0x1
744 12:41:39.490258 ===================================
745 12:41:39.494147 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 12:41:39.496942 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 12:41:39.503975 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 12:41:39.506955 ===================================
749 12:41:39.507057 LPDDR4 DRAM CONFIGURATION
750 12:41:39.510154 ===================================
751 12:41:39.513789 EX_ROW_EN[0] = 0x10
752 12:41:39.517142 EX_ROW_EN[1] = 0x0
753 12:41:39.517217 LP4Y_EN = 0x0
754 12:41:39.520676 WORK_FSP = 0x0
755 12:41:39.520752 WL = 0x2
756 12:41:39.523880 RL = 0x2
757 12:41:39.523955 BL = 0x2
758 12:41:39.526787 RPST = 0x0
759 12:41:39.526859 RD_PRE = 0x0
760 12:41:39.531331 WR_PRE = 0x1
761 12:41:39.531429 WR_PST = 0x0
762 12:41:39.533672 DBI_WR = 0x0
763 12:41:39.533773 DBI_RD = 0x0
764 12:41:39.537110 OTF = 0x1
765 12:41:39.540300 ===================================
766 12:41:39.547070 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 12:41:39.550490 nWR fixed to 40
768 12:41:39.550595 [ModeRegInit_LP4] CH0 RK0
769 12:41:39.553786 [ModeRegInit_LP4] CH0 RK1
770 12:41:39.556985 [ModeRegInit_LP4] CH1 RK0
771 12:41:39.557070 [ModeRegInit_LP4] CH1 RK1
772 12:41:39.560592 match AC timing 13
773 12:41:39.563484 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 12:41:39.567252 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 12:41:39.574101 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 12:41:39.577267 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 12:41:39.584172 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 12:41:39.584260 [EMI DOE] emi_dcm 0
779 12:41:39.587038 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 12:41:39.590988 ==
781 12:41:39.593608 Dram Type= 6, Freq= 0, CH_0, rank 0
782 12:41:39.596940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 12:41:39.597042 ==
784 12:41:39.600602 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 12:41:39.606867 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 12:41:39.616987 [CA 0] Center 37 (7~68) winsize 62
787 12:41:39.620108 [CA 1] Center 37 (6~68) winsize 63
788 12:41:39.623573 [CA 2] Center 35 (5~66) winsize 62
789 12:41:39.626870 [CA 3] Center 34 (4~65) winsize 62
790 12:41:39.630202 [CA 4] Center 34 (4~65) winsize 62
791 12:41:39.633296 [CA 5] Center 34 (4~64) winsize 61
792 12:41:39.633372
793 12:41:39.636616 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 12:41:39.636713
795 12:41:39.639942 [CATrainingPosCal] consider 1 rank data
796 12:41:39.643547 u2DelayCellTimex100 = 270/100 ps
797 12:41:39.646381 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
798 12:41:39.653486 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
799 12:41:39.656713 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
800 12:41:39.660101 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
801 12:41:39.663413 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
802 12:41:39.666894 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
803 12:41:39.667008
804 12:41:39.670227 CA PerBit enable=1, Macro0, CA PI delay=34
805 12:41:39.670307
806 12:41:39.673568 [CBTSetCACLKResult] CA Dly = 34
807 12:41:39.673646 CS Dly: 5 (0~36)
808 12:41:39.676828 ==
809 12:41:39.676905 Dram Type= 6, Freq= 0, CH_0, rank 1
810 12:41:39.683294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 12:41:39.683419 ==
812 12:41:39.686402 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 12:41:39.693421 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 12:41:39.703076 [CA 0] Center 37 (6~68) winsize 63
815 12:41:39.706577 [CA 1] Center 37 (6~68) winsize 63
816 12:41:39.709882 [CA 2] Center 35 (4~66) winsize 63
817 12:41:39.713004 [CA 3] Center 35 (4~66) winsize 63
818 12:41:39.716474 [CA 4] Center 34 (3~65) winsize 63
819 12:41:39.720121 [CA 5] Center 33 (3~64) winsize 62
820 12:41:39.720199
821 12:41:39.723713 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 12:41:39.723788
823 12:41:39.726435 [CATrainingPosCal] consider 2 rank data
824 12:41:39.729837 u2DelayCellTimex100 = 270/100 ps
825 12:41:39.733268 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
826 12:41:39.736776 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
827 12:41:39.739962 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
828 12:41:39.746806 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
829 12:41:39.750221 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
830 12:41:39.753542 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
831 12:41:39.753657
832 12:41:39.756787 CA PerBit enable=1, Macro0, CA PI delay=34
833 12:41:39.756889
834 12:41:39.760340 [CBTSetCACLKResult] CA Dly = 34
835 12:41:39.760428 CS Dly: 6 (0~38)
836 12:41:39.760495
837 12:41:39.763341 ----->DramcWriteLeveling(PI) begin...
838 12:41:39.763439 ==
839 12:41:39.767310 Dram Type= 6, Freq= 0, CH_0, rank 0
840 12:41:39.773954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 12:41:39.774066 ==
842 12:41:39.774160 Write leveling (Byte 0): 28 => 28
843 12:41:39.777906 Write leveling (Byte 1): 27 => 27
844 12:41:39.781444 DramcWriteLeveling(PI) end<-----
845 12:41:39.781545
846 12:41:39.781644 ==
847 12:41:39.785305 Dram Type= 6, Freq= 0, CH_0, rank 0
848 12:41:39.788440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 12:41:39.788541 ==
850 12:41:39.791509 [Gating] SW mode calibration
851 12:41:39.799544 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 12:41:39.806116 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 12:41:39.809229 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 12:41:39.812379 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 12:41:39.819533 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
856 12:41:39.822400 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
857 12:41:39.826440 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 12:41:39.832839 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 12:41:39.835731 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 12:41:39.839084 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 12:41:39.842433 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 12:41:39.849386 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 12:41:39.852643 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 12:41:39.856107 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 12:41:39.862817 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 12:41:39.865848 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 12:41:39.869054 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 12:41:39.876080 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 12:41:39.879381 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 12:41:39.882847 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 12:41:39.889091 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
872 12:41:39.892768 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 12:41:39.896047 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 12:41:39.902704 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 12:41:39.906217 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 12:41:39.909162 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 12:41:39.912717 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 12:41:39.919553 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 12:41:39.922815 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
880 12:41:39.926580 0 9 12 | B1->B0 | 2727 3131 | 0 0 | (0 0) (0 0)
881 12:41:39.932760 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 12:41:39.936274 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 12:41:39.939295 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 12:41:39.946226 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 12:41:39.949377 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 12:41:39.952634 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
887 12:41:39.959379 0 10 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
888 12:41:39.962762 0 10 12 | B1->B0 | 2929 2525 | 0 0 | (1 1) (0 0)
889 12:41:39.965926 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 12:41:39.972594 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 12:41:39.975876 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 12:41:39.979532 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 12:41:39.985962 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 12:41:39.989637 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
895 12:41:39.992803 0 11 8 | B1->B0 | 2929 3131 | 0 0 | (0 0) (0 0)
896 12:41:39.999433 0 11 12 | B1->B0 | 3939 4040 | 1 0 | (0 0) (0 0)
897 12:41:40.002518 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 12:41:40.006306 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 12:41:40.012518 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 12:41:40.016074 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 12:41:40.019371 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 12:41:40.022461 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 12:41:40.029142 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
904 12:41:40.032806 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 12:41:40.036365 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 12:41:40.042674 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 12:41:40.045611 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 12:41:40.049124 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 12:41:40.056239 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 12:41:40.059588 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 12:41:40.062942 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 12:41:40.069658 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 12:41:40.072538 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 12:41:40.076182 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 12:41:40.082805 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 12:41:40.086253 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 12:41:40.089148 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 12:41:40.095953 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 12:41:40.099386 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
920 12:41:40.102430 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
921 12:41:40.105603 Total UI for P1: 0, mck2ui 16
922 12:41:40.109129 best dqsien dly found for B0: ( 0, 14, 8)
923 12:41:40.112197 Total UI for P1: 0, mck2ui 16
924 12:41:40.116339 best dqsien dly found for B1: ( 0, 14, 8)
925 12:41:40.119185 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
926 12:41:40.122531 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 12:41:40.122607
928 12:41:40.125881 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
929 12:41:40.132300 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 12:41:40.132384 [Gating] SW calibration Done
931 12:41:40.132453 ==
932 12:41:40.135656 Dram Type= 6, Freq= 0, CH_0, rank 0
933 12:41:40.143119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 12:41:40.143206 ==
935 12:41:40.143311 RX Vref Scan: 0
936 12:41:40.143438
937 12:41:40.146192 RX Vref 0 -> 0, step: 1
938 12:41:40.146267
939 12:41:40.148915 RX Delay -130 -> 252, step: 16
940 12:41:40.152667 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 12:41:40.155785 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 12:41:40.159590 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 12:41:40.162874 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 12:41:40.169059 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
945 12:41:40.172558 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
946 12:41:40.175813 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
947 12:41:40.179518 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
948 12:41:40.182721 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
949 12:41:40.189404 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
950 12:41:40.192253 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
951 12:41:40.195922 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
952 12:41:40.199106 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
953 12:41:40.206078 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
954 12:41:40.208928 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
955 12:41:40.212623 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 12:41:40.212707 ==
957 12:41:40.215953 Dram Type= 6, Freq= 0, CH_0, rank 0
958 12:41:40.219114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 12:41:40.219199 ==
960 12:41:40.222628 DQS Delay:
961 12:41:40.222712 DQS0 = 0, DQS1 = 0
962 12:41:40.225980 DQM Delay:
963 12:41:40.226064 DQM0 = 86, DQM1 = 79
964 12:41:40.226131 DQ Delay:
965 12:41:40.228733 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 12:41:40.232262 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
967 12:41:40.235656 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =77
968 12:41:40.238958 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
969 12:41:40.239042
970 12:41:40.239107
971 12:41:40.241926 ==
972 12:41:40.242009 Dram Type= 6, Freq= 0, CH_0, rank 0
973 12:41:40.249276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 12:41:40.249365 ==
975 12:41:40.249468
976 12:41:40.249529
977 12:41:40.249589 TX Vref Scan disable
978 12:41:40.252728 == TX Byte 0 ==
979 12:41:40.256239 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
980 12:41:40.259641 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
981 12:41:40.262849 == TX Byte 1 ==
982 12:41:40.265906 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
983 12:41:40.273069 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
984 12:41:40.273153 ==
985 12:41:40.275742 Dram Type= 6, Freq= 0, CH_0, rank 0
986 12:41:40.279187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 12:41:40.279271 ==
988 12:41:40.291960 TX Vref=22, minBit 12, minWin=26, winSum=437
989 12:41:40.295338 TX Vref=24, minBit 5, minWin=26, winSum=436
990 12:41:40.298895 TX Vref=26, minBit 5, minWin=27, winSum=443
991 12:41:40.301979 TX Vref=28, minBit 8, minWin=27, winSum=447
992 12:41:40.305292 TX Vref=30, minBit 3, minWin=27, winSum=448
993 12:41:40.308686 TX Vref=32, minBit 3, minWin=27, winSum=447
994 12:41:40.315529 [TxChooseVref] Worse bit 3, Min win 27, Win sum 448, Final Vref 30
995 12:41:40.315614
996 12:41:40.318601 Final TX Range 1 Vref 30
997 12:41:40.318686
998 12:41:40.318751 ==
999 12:41:40.322414 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 12:41:40.325533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 12:41:40.325618 ==
1002 12:41:40.325685
1003 12:41:40.329082
1004 12:41:40.329165 TX Vref Scan disable
1005 12:41:40.331935 == TX Byte 0 ==
1006 12:41:40.335276 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1007 12:41:40.342284 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1008 12:41:40.342368 == TX Byte 1 ==
1009 12:41:40.345166 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1010 12:41:40.351662 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1011 12:41:40.351748
1012 12:41:40.351815 [DATLAT]
1013 12:41:40.351879 Freq=800, CH0 RK0
1014 12:41:40.351940
1015 12:41:40.355189 DATLAT Default: 0xa
1016 12:41:40.355272 0, 0xFFFF, sum = 0
1017 12:41:40.358822 1, 0xFFFF, sum = 0
1018 12:41:40.358907 2, 0xFFFF, sum = 0
1019 12:41:40.362172 3, 0xFFFF, sum = 0
1020 12:41:40.362257 4, 0xFFFF, sum = 0
1021 12:41:40.365253 5, 0xFFFF, sum = 0
1022 12:41:40.368442 6, 0xFFFF, sum = 0
1023 12:41:40.368543 7, 0xFFFF, sum = 0
1024 12:41:40.371592 8, 0xFFFF, sum = 0
1025 12:41:40.371680 9, 0x0, sum = 1
1026 12:41:40.371748 10, 0x0, sum = 2
1027 12:41:40.375087 11, 0x0, sum = 3
1028 12:41:40.375160 12, 0x0, sum = 4
1029 12:41:40.378600 best_step = 10
1030 12:41:40.378708
1031 12:41:40.378800 ==
1032 12:41:40.381671 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 12:41:40.385032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 12:41:40.385133 ==
1035 12:41:40.388324 RX Vref Scan: 1
1036 12:41:40.388424
1037 12:41:40.388524 Set Vref Range= 32 -> 127
1038 12:41:40.392296
1039 12:41:40.392405 RX Vref 32 -> 127, step: 1
1040 12:41:40.392498
1041 12:41:40.395236 RX Delay -111 -> 252, step: 8
1042 12:41:40.395321
1043 12:41:40.399154 Set Vref, RX VrefLevel [Byte0]: 32
1044 12:41:40.402161 [Byte1]: 32
1045 12:41:40.402244
1046 12:41:40.405344 Set Vref, RX VrefLevel [Byte0]: 33
1047 12:41:40.408859 [Byte1]: 33
1048 12:41:40.412638
1049 12:41:40.412721 Set Vref, RX VrefLevel [Byte0]: 34
1050 12:41:40.415692 [Byte1]: 34
1051 12:41:40.420362
1052 12:41:40.420445 Set Vref, RX VrefLevel [Byte0]: 35
1053 12:41:40.423612 [Byte1]: 35
1054 12:41:40.427914
1055 12:41:40.427997 Set Vref, RX VrefLevel [Byte0]: 36
1056 12:41:40.430986 [Byte1]: 36
1057 12:41:40.435700
1058 12:41:40.435782 Set Vref, RX VrefLevel [Byte0]: 37
1059 12:41:40.439018 [Byte1]: 37
1060 12:41:40.443679
1061 12:41:40.443762 Set Vref, RX VrefLevel [Byte0]: 38
1062 12:41:40.446677 [Byte1]: 38
1063 12:41:40.451070
1064 12:41:40.451153 Set Vref, RX VrefLevel [Byte0]: 39
1065 12:41:40.454827 [Byte1]: 39
1066 12:41:40.458863
1067 12:41:40.458946 Set Vref, RX VrefLevel [Byte0]: 40
1068 12:41:40.462398 [Byte1]: 40
1069 12:41:40.466360
1070 12:41:40.466443 Set Vref, RX VrefLevel [Byte0]: 41
1071 12:41:40.469685 [Byte1]: 41
1072 12:41:40.473863
1073 12:41:40.473945 Set Vref, RX VrefLevel [Byte0]: 42
1074 12:41:40.477256 [Byte1]: 42
1075 12:41:40.481597
1076 12:41:40.481680 Set Vref, RX VrefLevel [Byte0]: 43
1077 12:41:40.484707 [Byte1]: 43
1078 12:41:40.489268
1079 12:41:40.489351 Set Vref, RX VrefLevel [Byte0]: 44
1080 12:41:40.492767 [Byte1]: 44
1081 12:41:40.496495
1082 12:41:40.496578 Set Vref, RX VrefLevel [Byte0]: 45
1083 12:41:40.499865 [Byte1]: 45
1084 12:41:40.504417
1085 12:41:40.504500 Set Vref, RX VrefLevel [Byte0]: 46
1086 12:41:40.507751 [Byte1]: 46
1087 12:41:40.511727
1088 12:41:40.511810 Set Vref, RX VrefLevel [Byte0]: 47
1089 12:41:40.515777 [Byte1]: 47
1090 12:41:40.519822
1091 12:41:40.519905 Set Vref, RX VrefLevel [Byte0]: 48
1092 12:41:40.523306 [Byte1]: 48
1093 12:41:40.527299
1094 12:41:40.527401 Set Vref, RX VrefLevel [Byte0]: 49
1095 12:41:40.531131 [Byte1]: 49
1096 12:41:40.534750
1097 12:41:40.534832 Set Vref, RX VrefLevel [Byte0]: 50
1098 12:41:40.538687 [Byte1]: 50
1099 12:41:40.542558
1100 12:41:40.542641 Set Vref, RX VrefLevel [Byte0]: 51
1101 12:41:40.546000 [Byte1]: 51
1102 12:41:40.550220
1103 12:41:40.550303 Set Vref, RX VrefLevel [Byte0]: 52
1104 12:41:40.553419 [Byte1]: 52
1105 12:41:40.558172
1106 12:41:40.558255 Set Vref, RX VrefLevel [Byte0]: 53
1107 12:41:40.560981 [Byte1]: 53
1108 12:41:40.566006
1109 12:41:40.566089 Set Vref, RX VrefLevel [Byte0]: 54
1110 12:41:40.569346 [Byte1]: 54
1111 12:41:40.573031
1112 12:41:40.573113 Set Vref, RX VrefLevel [Byte0]: 55
1113 12:41:40.576248 [Byte1]: 55
1114 12:41:40.580781
1115 12:41:40.580864 Set Vref, RX VrefLevel [Byte0]: 56
1116 12:41:40.583925 [Byte1]: 56
1117 12:41:40.588777
1118 12:41:40.588876 Set Vref, RX VrefLevel [Byte0]: 57
1119 12:41:40.591821 [Byte1]: 57
1120 12:41:40.596371
1121 12:41:40.596454 Set Vref, RX VrefLevel [Byte0]: 58
1122 12:41:40.599869 [Byte1]: 58
1123 12:41:40.603973
1124 12:41:40.604056 Set Vref, RX VrefLevel [Byte0]: 59
1125 12:41:40.607185 [Byte1]: 59
1126 12:41:40.611694
1127 12:41:40.611777 Set Vref, RX VrefLevel [Byte0]: 60
1128 12:41:40.614622 [Byte1]: 60
1129 12:41:40.619028
1130 12:41:40.619111 Set Vref, RX VrefLevel [Byte0]: 61
1131 12:41:40.622142 [Byte1]: 61
1132 12:41:40.626632
1133 12:41:40.626715 Set Vref, RX VrefLevel [Byte0]: 62
1134 12:41:40.630431 [Byte1]: 62
1135 12:41:40.634315
1136 12:41:40.634424 Set Vref, RX VrefLevel [Byte0]: 63
1137 12:41:40.637641 [Byte1]: 63
1138 12:41:40.642156
1139 12:41:40.642239 Set Vref, RX VrefLevel [Byte0]: 64
1140 12:41:40.645166 [Byte1]: 64
1141 12:41:40.649514
1142 12:41:40.649625 Set Vref, RX VrefLevel [Byte0]: 65
1143 12:41:40.652987 [Byte1]: 65
1144 12:41:40.656983
1145 12:41:40.657081 Set Vref, RX VrefLevel [Byte0]: 66
1146 12:41:40.660608 [Byte1]: 66
1147 12:41:40.665188
1148 12:41:40.665293 Set Vref, RX VrefLevel [Byte0]: 67
1149 12:41:40.668229 [Byte1]: 67
1150 12:41:40.673033
1151 12:41:40.673107 Set Vref, RX VrefLevel [Byte0]: 68
1152 12:41:40.676031 [Byte1]: 68
1153 12:41:40.680361
1154 12:41:40.680444 Set Vref, RX VrefLevel [Byte0]: 69
1155 12:41:40.683358 [Byte1]: 69
1156 12:41:40.687516
1157 12:41:40.687599 Set Vref, RX VrefLevel [Byte0]: 70
1158 12:41:40.691226 [Byte1]: 70
1159 12:41:40.695304
1160 12:41:40.695424 Set Vref, RX VrefLevel [Byte0]: 71
1161 12:41:40.698942 [Byte1]: 71
1162 12:41:40.703295
1163 12:41:40.703415 Set Vref, RX VrefLevel [Byte0]: 72
1164 12:41:40.706537 [Byte1]: 72
1165 12:41:40.710549
1166 12:41:40.710631 Set Vref, RX VrefLevel [Byte0]: 73
1167 12:41:40.713834 [Byte1]: 73
1168 12:41:40.718336
1169 12:41:40.718419 Set Vref, RX VrefLevel [Byte0]: 74
1170 12:41:40.721807 [Byte1]: 74
1171 12:41:40.726327
1172 12:41:40.726410 Set Vref, RX VrefLevel [Byte0]: 75
1173 12:41:40.729665 [Byte1]: 75
1174 12:41:40.733371
1175 12:41:40.733454 Set Vref, RX VrefLevel [Byte0]: 76
1176 12:41:40.737115 [Byte1]: 76
1177 12:41:40.741097
1178 12:41:40.741179 Final RX Vref Byte 0 = 62 to rank0
1179 12:41:40.744770 Final RX Vref Byte 1 = 60 to rank0
1180 12:41:40.748147 Final RX Vref Byte 0 = 62 to rank1
1181 12:41:40.751259 Final RX Vref Byte 1 = 60 to rank1==
1182 12:41:40.755018 Dram Type= 6, Freq= 0, CH_0, rank 0
1183 12:41:40.757915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1184 12:41:40.761198 ==
1185 12:41:40.761281 DQS Delay:
1186 12:41:40.761347 DQS0 = 0, DQS1 = 0
1187 12:41:40.764803 DQM Delay:
1188 12:41:40.764886 DQM0 = 88, DQM1 = 79
1189 12:41:40.768074 DQ Delay:
1190 12:41:40.771308 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1191 12:41:40.771421 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1192 12:41:40.774766 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1193 12:41:40.781343 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1194 12:41:40.781425
1195 12:41:40.781491
1196 12:41:40.787845 [DQSOSCAuto] RK0, (LSB)MR18= 0x230a, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 401 ps
1197 12:41:40.790998 CH0 RK0: MR19=606, MR18=230A
1198 12:41:40.797992 CH0_RK0: MR19=0x606, MR18=0x230A, DQSOSC=401, MR23=63, INC=91, DEC=61
1199 12:41:40.798076
1200 12:41:40.800902 ----->DramcWriteLeveling(PI) begin...
1201 12:41:40.800987 ==
1202 12:41:40.804208 Dram Type= 6, Freq= 0, CH_0, rank 1
1203 12:41:40.807861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1204 12:41:40.807993 ==
1205 12:41:40.811136 Write leveling (Byte 0): 31 => 31
1206 12:41:40.814562 Write leveling (Byte 1): 31 => 31
1207 12:41:40.818176 DramcWriteLeveling(PI) end<-----
1208 12:41:40.818251
1209 12:41:40.818315 ==
1210 12:41:40.820944 Dram Type= 6, Freq= 0, CH_0, rank 1
1211 12:41:40.824422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1212 12:41:40.824514 ==
1213 12:41:40.827819 [Gating] SW mode calibration
1214 12:41:40.834381 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1215 12:41:40.841126 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1216 12:41:40.844551 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1217 12:41:40.848032 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1218 12:41:40.892038 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 12:41:40.892487 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 12:41:40.892897 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 12:41:40.893743 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 12:41:40.893816 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 12:41:40.894219 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 12:41:40.894640 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 12:41:40.895143 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 12:41:40.895537 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 12:41:40.895642 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 12:41:40.936214 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 12:41:40.936535 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 12:41:40.936791 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 12:41:40.937039 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 12:41:40.937106 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 12:41:40.937634 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1234 12:41:40.938297 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1235 12:41:40.938578 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1236 12:41:40.939374 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 12:41:40.939446 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 12:41:40.980027 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 12:41:40.980297 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 12:41:40.980575 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 12:41:40.980704 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 12:41:40.980809 0 9 8 | B1->B0 | 2323 3131 | 0 0 | (1 1) (0 0)
1243 12:41:40.980919 0 9 12 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1244 12:41:40.981008 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 12:41:40.982105 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 12:41:40.982385 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 12:41:40.982480 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 12:41:41.002687 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 12:41:41.003158 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
1250 12:41:41.003468 0 10 8 | B1->B0 | 3030 2424 | 0 0 | (0 1) (0 0)
1251 12:41:41.003542 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1252 12:41:41.003781 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 12:41:41.006511 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 12:41:41.013736 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 12:41:41.016506 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 12:41:41.019710 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 12:41:41.023354 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1258 12:41:41.031027 0 11 8 | B1->B0 | 2727 3c3c | 0 0 | (0 0) (0 0)
1259 12:41:41.034727 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1260 12:41:41.038113 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 12:41:41.041429 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 12:41:41.048635 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 12:41:41.052030 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 12:41:41.055266 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1265 12:41:41.058658 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1266 12:41:41.065158 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1267 12:41:41.068586 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 12:41:41.072245 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 12:41:41.079168 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 12:41:41.082148 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 12:41:41.085650 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 12:41:41.092347 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 12:41:41.095383 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 12:41:41.099168 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 12:41:41.105934 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 12:41:41.108764 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 12:41:41.112110 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 12:41:41.118750 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 12:41:41.122071 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 12:41:41.125335 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 12:41:41.128689 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1282 12:41:41.135198 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1283 12:41:41.138474 Total UI for P1: 0, mck2ui 16
1284 12:41:41.142426 best dqsien dly found for B0: ( 0, 14, 4)
1285 12:41:41.145506 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1286 12:41:41.148633 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1287 12:41:41.152350 Total UI for P1: 0, mck2ui 16
1288 12:41:41.155270 best dqsien dly found for B1: ( 0, 14, 10)
1289 12:41:41.159127 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1290 12:41:41.162231 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1291 12:41:41.162308
1292 12:41:41.168731 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1293 12:41:41.172239 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1294 12:41:41.172314 [Gating] SW calibration Done
1295 12:41:41.175749 ==
1296 12:41:41.179147 Dram Type= 6, Freq= 0, CH_0, rank 1
1297 12:41:41.182200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1298 12:41:41.182279 ==
1299 12:41:41.182343 RX Vref Scan: 0
1300 12:41:41.182404
1301 12:41:41.185509 RX Vref 0 -> 0, step: 1
1302 12:41:41.185581
1303 12:41:41.188642 RX Delay -130 -> 252, step: 16
1304 12:41:41.192313 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1305 12:41:41.195520 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1306 12:41:41.198891 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1307 12:41:41.205614 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1308 12:41:41.209046 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1309 12:41:41.212241 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1310 12:41:41.215554 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1311 12:41:41.221929 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1312 12:41:41.225185 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1313 12:41:41.228744 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1314 12:41:41.231862 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1315 12:41:41.235333 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1316 12:41:41.241572 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1317 12:41:41.245166 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1318 12:41:41.248537 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1319 12:41:41.251635 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1320 12:41:41.251719 ==
1321 12:41:41.255318 Dram Type= 6, Freq= 0, CH_0, rank 1
1322 12:41:41.261694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1323 12:41:41.261779 ==
1324 12:41:41.261846 DQS Delay:
1325 12:41:41.261908 DQS0 = 0, DQS1 = 0
1326 12:41:41.265261 DQM Delay:
1327 12:41:41.265336 DQM0 = 86, DQM1 = 75
1328 12:41:41.268574 DQ Delay:
1329 12:41:41.272021 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1330 12:41:41.274872 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
1331 12:41:41.278279 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1332 12:41:41.281847 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1333 12:41:41.281925
1334 12:41:41.281989
1335 12:41:41.282078 ==
1336 12:41:41.284879 Dram Type= 6, Freq= 0, CH_0, rank 1
1337 12:41:41.288158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1338 12:41:41.288233 ==
1339 12:41:41.288296
1340 12:41:41.288355
1341 12:41:41.291551 TX Vref Scan disable
1342 12:41:41.291625 == TX Byte 0 ==
1343 12:41:41.298183 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1344 12:41:41.301584 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1345 12:41:41.301659 == TX Byte 1 ==
1346 12:41:41.308424 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1347 12:41:41.311639 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1348 12:41:41.311726 ==
1349 12:41:41.315063 Dram Type= 6, Freq= 0, CH_0, rank 1
1350 12:41:41.318910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1351 12:41:41.318991 ==
1352 12:41:41.332214 TX Vref=22, minBit 8, minWin=27, winSum=447
1353 12:41:41.335704 TX Vref=24, minBit 8, minWin=27, winSum=446
1354 12:41:41.338692 TX Vref=26, minBit 3, minWin=28, winSum=453
1355 12:41:41.342225 TX Vref=28, minBit 5, minWin=28, winSum=458
1356 12:41:41.345968 TX Vref=30, minBit 5, minWin=28, winSum=458
1357 12:41:41.348902 TX Vref=32, minBit 4, minWin=28, winSum=458
1358 12:41:41.355722 [TxChooseVref] Worse bit 5, Min win 28, Win sum 458, Final Vref 28
1359 12:41:41.355828
1360 12:41:41.358885 Final TX Range 1 Vref 28
1361 12:41:41.358959
1362 12:41:41.359025 ==
1363 12:41:41.362423 Dram Type= 6, Freq= 0, CH_0, rank 1
1364 12:41:41.365482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1365 12:41:41.365559 ==
1366 12:41:41.365622
1367 12:41:41.365689
1368 12:41:41.368817 TX Vref Scan disable
1369 12:41:41.372090 == TX Byte 0 ==
1370 12:41:41.375622 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1371 12:41:41.379078 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1372 12:41:41.382486 == TX Byte 1 ==
1373 12:41:41.385408 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1374 12:41:41.388803 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1375 12:41:41.388886
1376 12:41:41.392493 [DATLAT]
1377 12:41:41.392615 Freq=800, CH0 RK1
1378 12:41:41.392708
1379 12:41:41.395821 DATLAT Default: 0xa
1380 12:41:41.395898 0, 0xFFFF, sum = 0
1381 12:41:41.398785 1, 0xFFFF, sum = 0
1382 12:41:41.398861 2, 0xFFFF, sum = 0
1383 12:41:41.402152 3, 0xFFFF, sum = 0
1384 12:41:41.402245 4, 0xFFFF, sum = 0
1385 12:41:41.405623 5, 0xFFFF, sum = 0
1386 12:41:41.405699 6, 0xFFFF, sum = 0
1387 12:41:41.408761 7, 0xFFFF, sum = 0
1388 12:41:41.408837 8, 0x0, sum = 1
1389 12:41:41.411972 9, 0x0, sum = 2
1390 12:41:41.412048 10, 0x0, sum = 3
1391 12:41:41.415877 11, 0x0, sum = 4
1392 12:41:41.415955 best_step = 9
1393 12:41:41.416016
1394 12:41:41.416074 ==
1395 12:41:41.418877 Dram Type= 6, Freq= 0, CH_0, rank 1
1396 12:41:41.422400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1397 12:41:41.425829 ==
1398 12:41:41.425905 RX Vref Scan: 0
1399 12:41:41.425972
1400 12:41:41.429053 RX Vref 0 -> 0, step: 1
1401 12:41:41.429125
1402 12:41:41.432525 RX Delay -95 -> 252, step: 8
1403 12:41:41.435589 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1404 12:41:41.438870 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1405 12:41:41.442190 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1406 12:41:41.449164 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1407 12:41:41.452339 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1408 12:41:41.455332 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1409 12:41:41.458677 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1410 12:41:41.462187 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1411 12:41:41.469007 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1412 12:41:41.472297 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1413 12:41:41.475856 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1414 12:41:41.478994 iDelay=209, Bit 11, Center 72 (-31 ~ 176) 208
1415 12:41:41.482613 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1416 12:41:41.488796 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1417 12:41:41.492466 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1418 12:41:41.495718 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1419 12:41:41.495801 ==
1420 12:41:41.498568 Dram Type= 6, Freq= 0, CH_0, rank 1
1421 12:41:41.502148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1422 12:41:41.502235 ==
1423 12:41:41.505645 DQS Delay:
1424 12:41:41.505727 DQS0 = 0, DQS1 = 0
1425 12:41:41.508695 DQM Delay:
1426 12:41:41.508779 DQM0 = 87, DQM1 = 79
1427 12:41:41.508843 DQ Delay:
1428 12:41:41.512350 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1429 12:41:41.515354 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1430 12:41:41.518950 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =72
1431 12:41:41.522298 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88
1432 12:41:41.522379
1433 12:41:41.522442
1434 12:41:41.532168 [DQSOSCAuto] RK1, (LSB)MR18= 0x321b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1435 12:41:41.535493 CH0 RK1: MR19=606, MR18=321B
1436 12:41:41.538825 CH0_RK1: MR19=0x606, MR18=0x321B, DQSOSC=397, MR23=63, INC=93, DEC=62
1437 12:41:41.542079 [RxdqsGatingPostProcess] freq 800
1438 12:41:41.548686 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1439 12:41:41.552034 Pre-setting of DQS Precalculation
1440 12:41:41.555461 [DualRankRxdatlatCal] RK0: 10, RK1: 9, Final_Datlat 10
1441 12:41:41.555543 ==
1442 12:41:41.559128 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 12:41:41.565572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 12:41:41.565655 ==
1445 12:41:41.569471 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1446 12:41:41.575523 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1447 12:41:41.584798 [CA 0] Center 36 (6~66) winsize 61
1448 12:41:41.588133 [CA 1] Center 36 (6~66) winsize 61
1449 12:41:41.591631 [CA 2] Center 34 (4~65) winsize 62
1450 12:41:41.595633 [CA 3] Center 34 (3~65) winsize 63
1451 12:41:41.598480 [CA 4] Center 34 (4~65) winsize 62
1452 12:41:41.601203 [CA 5] Center 33 (3~64) winsize 62
1453 12:41:41.601287
1454 12:41:41.605129 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1455 12:41:41.605212
1456 12:41:41.608388 [CATrainingPosCal] consider 1 rank data
1457 12:41:41.611873 u2DelayCellTimex100 = 270/100 ps
1458 12:41:41.615328 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1459 12:41:41.618102 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1460 12:41:41.624741 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1461 12:41:41.628639 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1462 12:41:41.631245 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1463 12:41:41.634926 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1464 12:41:41.635010
1465 12:41:41.638491 CA PerBit enable=1, Macro0, CA PI delay=33
1466 12:41:41.638573
1467 12:41:41.641547 [CBTSetCACLKResult] CA Dly = 33
1468 12:41:41.641630 CS Dly: 5 (0~36)
1469 12:41:41.641696 ==
1470 12:41:41.644862 Dram Type= 6, Freq= 0, CH_1, rank 1
1471 12:41:41.651942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1472 12:41:41.652041 ==
1473 12:41:41.654602 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1474 12:41:41.661186 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1475 12:41:41.670857 [CA 0] Center 36 (6~66) winsize 61
1476 12:41:41.674487 [CA 1] Center 36 (6~66) winsize 61
1477 12:41:41.677363 [CA 2] Center 34 (3~65) winsize 63
1478 12:41:41.680973 [CA 3] Center 34 (3~65) winsize 63
1479 12:41:41.684803 [CA 4] Center 34 (4~65) winsize 62
1480 12:41:41.688252 [CA 5] Center 33 (3~64) winsize 62
1481 12:41:41.688356
1482 12:41:41.692343 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1483 12:41:41.692425
1484 12:41:41.695463 [CATrainingPosCal] consider 2 rank data
1485 12:41:41.698880 u2DelayCellTimex100 = 270/100 ps
1486 12:41:41.702003 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1487 12:41:41.706240 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1488 12:41:41.709493 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1489 12:41:41.712888 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1490 12:41:41.717020 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1491 12:41:41.720652 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1492 12:41:41.720734
1493 12:41:41.723899 CA PerBit enable=1, Macro0, CA PI delay=33
1494 12:41:41.723999
1495 12:41:41.727159 [CBTSetCACLKResult] CA Dly = 33
1496 12:41:41.730454 CS Dly: 5 (0~36)
1497 12:41:41.730535
1498 12:41:41.733557 ----->DramcWriteLeveling(PI) begin...
1499 12:41:41.733677 ==
1500 12:41:41.737278 Dram Type= 6, Freq= 0, CH_1, rank 0
1501 12:41:41.740648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1502 12:41:41.740731 ==
1503 12:41:41.743694 Write leveling (Byte 0): 26 => 26
1504 12:41:41.747234 Write leveling (Byte 1): 27 => 27
1505 12:41:41.750435 DramcWriteLeveling(PI) end<-----
1506 12:41:41.750517
1507 12:41:41.750582 ==
1508 12:41:41.753789 Dram Type= 6, Freq= 0, CH_1, rank 0
1509 12:41:41.757407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1510 12:41:41.757490 ==
1511 12:41:41.760293 [Gating] SW mode calibration
1512 12:41:41.767012 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1513 12:41:41.773705 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1514 12:41:41.777161 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1515 12:41:41.780764 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (1 1) (1 1)
1516 12:41:41.787041 0 6 8 | B1->B0 | 2323 2323 | 1 0 | (0 0) (1 0)
1517 12:41:41.790210 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 12:41:41.794078 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 12:41:41.797197 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 12:41:41.803984 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 12:41:41.807491 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 12:41:41.810417 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 12:41:41.817141 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 12:41:41.820454 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 12:41:41.824033 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 12:41:41.830374 0 7 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1527 12:41:41.834173 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1528 12:41:41.837001 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 12:41:41.843976 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 12:41:41.847294 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1531 12:41:41.850572 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1532 12:41:41.857115 0 8 8 | B1->B0 | 2424 2323 | 0 0 | (0 1) (0 0)
1533 12:41:41.860670 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 12:41:41.863889 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 12:41:41.870606 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 12:41:41.873954 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 12:41:41.876878 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 12:41:41.883603 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 12:41:41.886897 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 12:41:41.890560 0 9 8 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
1541 12:41:41.893789 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 12:41:41.900751 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1543 12:41:41.903597 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1544 12:41:41.906886 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 12:41:41.913710 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 12:41:41.917405 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 12:41:41.920247 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 12:41:41.926872 0 10 8 | B1->B0 | 2a2a 2c2c | 0 0 | (0 0) (1 1)
1549 12:41:41.930432 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 12:41:41.933509 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 12:41:41.941108 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 12:41:41.943594 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1553 12:41:41.947211 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 12:41:41.953456 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 12:41:41.956677 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 12:41:41.960715 0 11 8 | B1->B0 | 3131 2b2b | 0 0 | (0 0) (0 0)
1557 12:41:41.967235 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 12:41:41.970638 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 12:41:41.973383 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 12:41:41.980109 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 12:41:41.983434 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 12:41:41.987311 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 12:41:41.990205 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 12:41:41.997152 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1565 12:41:42.000607 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 12:41:42.003521 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 12:41:42.010309 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 12:41:42.013925 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 12:41:42.017022 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 12:41:42.024092 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 12:41:42.027226 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 12:41:42.030476 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 12:41:42.037044 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 12:41:42.040682 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 12:41:42.044173 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 12:41:42.050149 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 12:41:42.053896 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 12:41:42.056749 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 12:41:42.063745 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 12:41:42.067100 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1581 12:41:42.070497 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1582 12:41:42.073421 Total UI for P1: 0, mck2ui 16
1583 12:41:42.076922 best dqsien dly found for B0: ( 0, 14, 8)
1584 12:41:42.080501 Total UI for P1: 0, mck2ui 16
1585 12:41:42.083798 best dqsien dly found for B1: ( 0, 14, 8)
1586 12:41:42.086789 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1587 12:41:42.090511 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1588 12:41:42.090612
1589 12:41:42.093802 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1590 12:41:42.097229 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1591 12:41:42.100480 [Gating] SW calibration Done
1592 12:41:42.100553 ==
1593 12:41:42.103863 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 12:41:42.110724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 12:41:42.110804 ==
1596 12:41:42.110877 RX Vref Scan: 0
1597 12:41:42.110944
1598 12:41:42.113909 RX Vref 0 -> 0, step: 1
1599 12:41:42.114005
1600 12:41:42.116885 RX Delay -130 -> 252, step: 16
1601 12:41:42.120656 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1602 12:41:42.123904 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1603 12:41:42.126992 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1604 12:41:42.130651 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1605 12:41:42.137474 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1606 12:41:42.141016 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1607 12:41:42.144286 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1608 12:41:42.147845 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1609 12:41:42.150665 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1610 12:41:42.157171 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1611 12:41:42.160649 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1612 12:41:42.163767 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1613 12:41:42.167474 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1614 12:41:42.170304 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1615 12:41:42.177131 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1616 12:41:42.180602 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1617 12:41:42.180678 ==
1618 12:41:42.183738 Dram Type= 6, Freq= 0, CH_1, rank 0
1619 12:41:42.187415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1620 12:41:42.187491 ==
1621 12:41:42.190746 DQS Delay:
1622 12:41:42.190842 DQS0 = 0, DQS1 = 0
1623 12:41:42.190930 DQM Delay:
1624 12:41:42.194032 DQM0 = 81, DQM1 = 77
1625 12:41:42.194102 DQ Delay:
1626 12:41:42.197026 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1627 12:41:42.200312 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =69
1628 12:41:42.203754 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1629 12:41:42.207285 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1630 12:41:42.207389
1631 12:41:42.207478
1632 12:41:42.207565 ==
1633 12:41:42.210640 Dram Type= 6, Freq= 0, CH_1, rank 0
1634 12:41:42.216926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1635 12:41:42.217030 ==
1636 12:41:42.217122
1637 12:41:42.217209
1638 12:41:42.217300 TX Vref Scan disable
1639 12:41:42.220383 == TX Byte 0 ==
1640 12:41:42.223776 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1641 12:41:42.227109 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1642 12:41:42.230452 == TX Byte 1 ==
1643 12:41:42.233938 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1644 12:41:42.240866 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1645 12:41:42.240939 ==
1646 12:41:42.243693 Dram Type= 6, Freq= 0, CH_1, rank 0
1647 12:41:42.246713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1648 12:41:42.246809 ==
1649 12:41:42.259642 TX Vref=22, minBit 0, minWin=27, winSum=436
1650 12:41:42.262904 TX Vref=24, minBit 0, minWin=27, winSum=441
1651 12:41:42.266405 TX Vref=26, minBit 0, minWin=27, winSum=445
1652 12:41:42.270131 TX Vref=28, minBit 0, minWin=27, winSum=445
1653 12:41:42.273454 TX Vref=30, minBit 15, minWin=27, winSum=450
1654 12:41:42.276779 TX Vref=32, minBit 11, minWin=27, winSum=450
1655 12:41:42.283661 [TxChooseVref] Worse bit 15, Min win 27, Win sum 450, Final Vref 30
1656 12:41:42.283744
1657 12:41:42.287000 Final TX Range 1 Vref 30
1658 12:41:42.287098
1659 12:41:42.287189 ==
1660 12:41:42.290198 Dram Type= 6, Freq= 0, CH_1, rank 0
1661 12:41:42.293515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1662 12:41:42.293591 ==
1663 12:41:42.293658
1664 12:41:42.293718
1665 12:41:42.296865 TX Vref Scan disable
1666 12:41:42.300262 == TX Byte 0 ==
1667 12:41:42.303748 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1668 12:41:42.306753 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1669 12:41:42.309936 == TX Byte 1 ==
1670 12:41:42.313772 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1671 12:41:42.316533 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1672 12:41:42.316613
1673 12:41:42.320177 [DATLAT]
1674 12:41:42.320274 Freq=800, CH1 RK0
1675 12:41:42.320363
1676 12:41:42.323660 DATLAT Default: 0xa
1677 12:41:42.323732 0, 0xFFFF, sum = 0
1678 12:41:42.326554 1, 0xFFFF, sum = 0
1679 12:41:42.326653 2, 0xFFFF, sum = 0
1680 12:41:42.329912 3, 0xFFFF, sum = 0
1681 12:41:42.330012 4, 0xFFFF, sum = 0
1682 12:41:42.333477 5, 0xFFFF, sum = 0
1683 12:41:42.333562 6, 0xFFFF, sum = 0
1684 12:41:42.336960 7, 0xFFFF, sum = 0
1685 12:41:42.337032 8, 0xFFFF, sum = 0
1686 12:41:42.339845 9, 0x0, sum = 1
1687 12:41:42.339914 10, 0x0, sum = 2
1688 12:41:42.343541 11, 0x0, sum = 3
1689 12:41:42.343641 12, 0x0, sum = 4
1690 12:41:42.346618 best_step = 10
1691 12:41:42.346685
1692 12:41:42.346744 ==
1693 12:41:42.349815 Dram Type= 6, Freq= 0, CH_1, rank 0
1694 12:41:42.353152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1695 12:41:42.353229 ==
1696 12:41:42.356299 RX Vref Scan: 1
1697 12:41:42.356398
1698 12:41:42.356488 Set Vref Range= 32 -> 127
1699 12:41:42.356575
1700 12:41:42.359911 RX Vref 32 -> 127, step: 1
1701 12:41:42.359995
1702 12:41:42.363762 RX Delay -95 -> 252, step: 8
1703 12:41:42.363845
1704 12:41:42.366424 Set Vref, RX VrefLevel [Byte0]: 32
1705 12:41:42.370176 [Byte1]: 32
1706 12:41:42.370258
1707 12:41:42.373278 Set Vref, RX VrefLevel [Byte0]: 33
1708 12:41:42.376524 [Byte1]: 33
1709 12:41:42.379922
1710 12:41:42.380004 Set Vref, RX VrefLevel [Byte0]: 34
1711 12:41:42.383461 [Byte1]: 34
1712 12:41:42.387643
1713 12:41:42.387725 Set Vref, RX VrefLevel [Byte0]: 35
1714 12:41:42.390699 [Byte1]: 35
1715 12:41:42.395228
1716 12:41:42.395309 Set Vref, RX VrefLevel [Byte0]: 36
1717 12:41:42.398597 [Byte1]: 36
1718 12:41:42.402957
1719 12:41:42.403039 Set Vref, RX VrefLevel [Byte0]: 37
1720 12:41:42.406280 [Byte1]: 37
1721 12:41:42.410340
1722 12:41:42.410424 Set Vref, RX VrefLevel [Byte0]: 38
1723 12:41:42.413494 [Byte1]: 38
1724 12:41:42.417673
1725 12:41:42.417755 Set Vref, RX VrefLevel [Byte0]: 39
1726 12:41:42.421086 [Byte1]: 39
1727 12:41:42.425715
1728 12:41:42.425798 Set Vref, RX VrefLevel [Byte0]: 40
1729 12:41:42.428763 [Byte1]: 40
1730 12:41:42.433216
1731 12:41:42.433298 Set Vref, RX VrefLevel [Byte0]: 41
1732 12:41:42.436243 [Byte1]: 41
1733 12:41:42.440940
1734 12:41:42.441021 Set Vref, RX VrefLevel [Byte0]: 42
1735 12:41:42.444485 [Byte1]: 42
1736 12:41:42.448297
1737 12:41:42.448379 Set Vref, RX VrefLevel [Byte0]: 43
1738 12:41:42.451882 [Byte1]: 43
1739 12:41:42.456014
1740 12:41:42.456096 Set Vref, RX VrefLevel [Byte0]: 44
1741 12:41:42.459004 [Byte1]: 44
1742 12:41:42.463484
1743 12:41:42.463569 Set Vref, RX VrefLevel [Byte0]: 45
1744 12:41:42.466853 [Byte1]: 45
1745 12:41:42.471173
1746 12:41:42.471282 Set Vref, RX VrefLevel [Byte0]: 46
1747 12:41:42.474215 [Byte1]: 46
1748 12:41:42.478671
1749 12:41:42.478756 Set Vref, RX VrefLevel [Byte0]: 47
1750 12:41:42.481961 [Byte1]: 47
1751 12:41:42.486542
1752 12:41:42.486627 Set Vref, RX VrefLevel [Byte0]: 48
1753 12:41:42.489536 [Byte1]: 48
1754 12:41:42.493984
1755 12:41:42.494069 Set Vref, RX VrefLevel [Byte0]: 49
1756 12:41:42.497171 [Byte1]: 49
1757 12:41:42.501771
1758 12:41:42.501856 Set Vref, RX VrefLevel [Byte0]: 50
1759 12:41:42.504710 [Byte1]: 50
1760 12:41:42.508965
1761 12:41:42.509050 Set Vref, RX VrefLevel [Byte0]: 51
1762 12:41:42.512524 [Byte1]: 51
1763 12:41:42.516823
1764 12:41:42.516908 Set Vref, RX VrefLevel [Byte0]: 52
1765 12:41:42.519745 [Byte1]: 52
1766 12:41:42.524132
1767 12:41:42.524217 Set Vref, RX VrefLevel [Byte0]: 53
1768 12:41:42.527694 [Byte1]: 53
1769 12:41:42.531761
1770 12:41:42.531846 Set Vref, RX VrefLevel [Byte0]: 54
1771 12:41:42.535078 [Byte1]: 54
1772 12:41:42.539244
1773 12:41:42.539375 Set Vref, RX VrefLevel [Byte0]: 55
1774 12:41:42.542886 [Byte1]: 55
1775 12:41:42.547467
1776 12:41:42.547553 Set Vref, RX VrefLevel [Byte0]: 56
1777 12:41:42.550374 [Byte1]: 56
1778 12:41:42.555122
1779 12:41:42.555232 Set Vref, RX VrefLevel [Byte0]: 57
1780 12:41:42.558054 [Byte1]: 57
1781 12:41:42.562425
1782 12:41:42.562510 Set Vref, RX VrefLevel [Byte0]: 58
1783 12:41:42.565610 [Byte1]: 58
1784 12:41:42.569674
1785 12:41:42.569750 Set Vref, RX VrefLevel [Byte0]: 59
1786 12:41:42.573196 [Byte1]: 59
1787 12:41:42.577471
1788 12:41:42.577553 Set Vref, RX VrefLevel [Byte0]: 60
1789 12:41:42.581153 [Byte1]: 60
1790 12:41:42.585162
1791 12:41:42.585245 Set Vref, RX VrefLevel [Byte0]: 61
1792 12:41:42.588259 [Byte1]: 61
1793 12:41:42.592471
1794 12:41:42.592554 Set Vref, RX VrefLevel [Byte0]: 62
1795 12:41:42.598889 [Byte1]: 62
1796 12:41:42.598972
1797 12:41:42.602424 Set Vref, RX VrefLevel [Byte0]: 63
1798 12:41:42.605584 [Byte1]: 63
1799 12:41:42.605667
1800 12:41:42.609458 Set Vref, RX VrefLevel [Byte0]: 64
1801 12:41:42.612243 [Byte1]: 64
1802 12:41:42.612326
1803 12:41:42.616228 Set Vref, RX VrefLevel [Byte0]: 65
1804 12:41:42.619285 [Byte1]: 65
1805 12:41:42.623156
1806 12:41:42.623237 Set Vref, RX VrefLevel [Byte0]: 66
1807 12:41:42.626238 [Byte1]: 66
1808 12:41:42.630993
1809 12:41:42.631075 Set Vref, RX VrefLevel [Byte0]: 67
1810 12:41:42.634187 [Byte1]: 67
1811 12:41:42.637900
1812 12:41:42.637982 Set Vref, RX VrefLevel [Byte0]: 68
1813 12:41:42.641452 [Byte1]: 68
1814 12:41:42.645615
1815 12:41:42.645697 Set Vref, RX VrefLevel [Byte0]: 69
1816 12:41:42.649301 [Byte1]: 69
1817 12:41:42.653392
1818 12:41:42.653475 Set Vref, RX VrefLevel [Byte0]: 70
1819 12:41:42.656497 [Byte1]: 70
1820 12:41:42.661209
1821 12:41:42.661293 Set Vref, RX VrefLevel [Byte0]: 71
1822 12:41:42.664368 [Byte1]: 71
1823 12:41:42.668901
1824 12:41:42.668984 Set Vref, RX VrefLevel [Byte0]: 72
1825 12:41:42.671802 [Byte1]: 72
1826 12:41:42.676345
1827 12:41:42.676427 Set Vref, RX VrefLevel [Byte0]: 73
1828 12:41:42.679717 [Byte1]: 73
1829 12:41:42.683649
1830 12:41:42.683731 Set Vref, RX VrefLevel [Byte0]: 74
1831 12:41:42.687083 [Byte1]: 74
1832 12:41:42.691337
1833 12:41:42.691460 Set Vref, RX VrefLevel [Byte0]: 75
1834 12:41:42.694757 [Byte1]: 75
1835 12:41:42.699204
1836 12:41:42.699287 Set Vref, RX VrefLevel [Byte0]: 76
1837 12:41:42.702075 [Byte1]: 76
1838 12:41:42.706318
1839 12:41:42.706401 Set Vref, RX VrefLevel [Byte0]: 77
1840 12:41:42.709847 [Byte1]: 77
1841 12:41:42.714165
1842 12:41:42.714247 Final RX Vref Byte 0 = 61 to rank0
1843 12:41:42.717509 Final RX Vref Byte 1 = 61 to rank0
1844 12:41:42.720849 Final RX Vref Byte 0 = 61 to rank1
1845 12:41:42.724429 Final RX Vref Byte 1 = 61 to rank1==
1846 12:41:42.727326 Dram Type= 6, Freq= 0, CH_1, rank 0
1847 12:41:42.733930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1848 12:41:42.734014 ==
1849 12:41:42.734080 DQS Delay:
1850 12:41:42.734140 DQS0 = 0, DQS1 = 0
1851 12:41:42.737603 DQM Delay:
1852 12:41:42.737686 DQM0 = 83, DQM1 = 74
1853 12:41:42.740481 DQ Delay:
1854 12:41:42.744326 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =84
1855 12:41:42.747486 DQ4 =80, DQ5 =92, DQ6 =96, DQ7 =80
1856 12:41:42.747570 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1857 12:41:42.753920 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =80
1858 12:41:42.754004
1859 12:41:42.754069
1860 12:41:42.760588 [DQSOSCAuto] RK0, (LSB)MR18= 0x26fb, (MSB)MR19= 0x605, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
1861 12:41:42.764338 CH1 RK0: MR19=605, MR18=26FB
1862 12:41:42.770697 CH1_RK0: MR19=0x605, MR18=0x26FB, DQSOSC=400, MR23=63, INC=92, DEC=61
1863 12:41:42.770774
1864 12:41:42.774829 ----->DramcWriteLeveling(PI) begin...
1865 12:41:42.774906 ==
1866 12:41:42.777334 Dram Type= 6, Freq= 0, CH_1, rank 1
1867 12:41:42.780814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1868 12:41:42.780891 ==
1869 12:41:42.784099 Write leveling (Byte 0): 28 => 28
1870 12:41:42.787560 Write leveling (Byte 1): 26 => 26
1871 12:41:42.790944 DramcWriteLeveling(PI) end<-----
1872 12:41:42.791016
1873 12:41:42.791081 ==
1874 12:41:42.794106 Dram Type= 6, Freq= 0, CH_1, rank 1
1875 12:41:42.797477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1876 12:41:42.797550 ==
1877 12:41:42.800529 [Gating] SW mode calibration
1878 12:41:42.807578 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1879 12:41:42.814383 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1880 12:41:42.817577 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1881 12:41:42.821166 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1882 12:41:42.827598 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 12:41:42.830670 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 12:41:42.834077 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 12:41:42.840729 0 6 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1886 12:41:42.844077 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 12:41:42.847573 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 12:41:42.853904 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 12:41:42.857461 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 12:41:42.860662 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 12:41:42.867270 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1892 12:41:42.870651 0 7 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1893 12:41:42.874228 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 12:41:42.877521 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1895 12:41:42.884493 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 1)
1896 12:41:42.887346 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 1)
1897 12:41:42.891222 0 8 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 1)
1898 12:41:42.897441 0 8 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1899 12:41:42.901154 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 12:41:42.904010 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 12:41:42.911095 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 12:41:42.914190 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 12:41:42.917315 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 12:41:42.924074 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 12:41:42.927792 0 9 4 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
1906 12:41:42.930964 0 9 8 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
1907 12:41:42.937191 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1908 12:41:42.940508 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1909 12:41:42.943937 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1910 12:41:42.950617 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1911 12:41:42.954029 0 9 28 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1912 12:41:42.957672 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1913 12:41:42.964083 0 10 4 | B1->B0 | 3030 2f2f | 1 1 | (1 1) (1 0)
1914 12:41:42.967320 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1915 12:41:42.970642 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1916 12:41:42.974134 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 12:41:42.981092 0 10 20 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1918 12:41:42.984402 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1919 12:41:42.987463 0 10 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1920 12:41:42.994158 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 12:41:42.997667 0 11 4 | B1->B0 | 2b2b 3535 | 0 0 | (0 0) (0 0)
1922 12:41:43.000693 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1923 12:41:43.007617 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 12:41:43.010885 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 12:41:43.013912 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 12:41:43.020885 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 12:41:43.024132 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 12:41:43.027434 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 12:41:43.033973 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1930 12:41:43.037570 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 12:41:43.040957 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 12:41:43.047974 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 12:41:43.050598 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 12:41:43.054043 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 12:41:43.060470 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 12:41:43.063959 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 12:41:43.067406 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 12:41:43.074282 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 12:41:43.077212 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 12:41:43.080586 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 12:41:43.083956 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 12:41:43.090375 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 12:41:43.094234 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 12:41:43.097716 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1945 12:41:43.103909 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1946 12:41:43.107311 Total UI for P1: 0, mck2ui 16
1947 12:41:43.110424 best dqsien dly found for B0: ( 0, 14, 0)
1948 12:41:43.113658 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1949 12:41:43.116838 Total UI for P1: 0, mck2ui 16
1950 12:41:43.120222 best dqsien dly found for B1: ( 0, 14, 4)
1951 12:41:43.123737 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1952 12:41:43.127055 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1953 12:41:43.127127
1954 12:41:43.130274 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1955 12:41:43.133849 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1956 12:41:43.136856 [Gating] SW calibration Done
1957 12:41:43.136940 ==
1958 12:41:43.140291 Dram Type= 6, Freq= 0, CH_1, rank 1
1959 12:41:43.143801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1960 12:41:43.147451 ==
1961 12:41:43.147534 RX Vref Scan: 0
1962 12:41:43.147599
1963 12:41:43.150550 RX Vref 0 -> 0, step: 1
1964 12:41:43.150633
1965 12:41:43.153900 RX Delay -130 -> 252, step: 16
1966 12:41:43.157285 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1967 12:41:43.160161 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1968 12:41:43.163382 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1969 12:41:43.167111 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1970 12:41:43.173566 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1971 12:41:43.176971 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1972 12:41:43.180825 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1973 12:41:43.183420 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1974 12:41:43.186856 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1975 12:41:43.193843 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1976 12:41:43.197240 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1977 12:41:43.200523 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1978 12:41:43.203892 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1979 12:41:43.206783 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1980 12:41:43.213453 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1981 12:41:43.217298 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1982 12:41:43.217381 ==
1983 12:41:43.220043 Dram Type= 6, Freq= 0, CH_1, rank 1
1984 12:41:43.223424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1985 12:41:43.223508 ==
1986 12:41:43.226881 DQS Delay:
1987 12:41:43.226964 DQS0 = 0, DQS1 = 0
1988 12:41:43.227030 DQM Delay:
1989 12:41:43.230180 DQM0 = 82, DQM1 = 77
1990 12:41:43.230263 DQ Delay:
1991 12:41:43.233193 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1992 12:41:43.236766 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1993 12:41:43.239778 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1994 12:41:43.243699 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1995 12:41:43.243782
1996 12:41:43.243847
1997 12:41:43.243906 ==
1998 12:41:43.247385 Dram Type= 6, Freq= 0, CH_1, rank 1
1999 12:41:43.253274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2000 12:41:43.253357 ==
2001 12:41:43.253420
2002 12:41:43.253480
2003 12:41:43.253539 TX Vref Scan disable
2004 12:41:43.257124 == TX Byte 0 ==
2005 12:41:43.260045 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2006 12:41:43.266469 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2007 12:41:43.266551 == TX Byte 1 ==
2008 12:41:43.270098 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2009 12:41:43.276761 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2010 12:41:43.276844 ==
2011 12:41:43.279984 Dram Type= 6, Freq= 0, CH_1, rank 1
2012 12:41:43.283541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2013 12:41:43.283625 ==
2014 12:41:43.296643 TX Vref=22, minBit 1, minWin=27, winSum=439
2015 12:41:43.299595 TX Vref=24, minBit 9, minWin=27, winSum=446
2016 12:41:43.302826 TX Vref=26, minBit 1, minWin=27, winSum=444
2017 12:41:43.306125 TX Vref=28, minBit 9, minWin=27, winSum=447
2018 12:41:43.309281 TX Vref=30, minBit 12, minWin=27, winSum=449
2019 12:41:43.316236 TX Vref=32, minBit 9, minWin=27, winSum=448
2020 12:41:43.319312 [TxChooseVref] Worse bit 12, Min win 27, Win sum 449, Final Vref 30
2021 12:41:43.319415
2022 12:41:43.322805 Final TX Range 1 Vref 30
2023 12:41:43.322887
2024 12:41:43.322952 ==
2025 12:41:43.326085 Dram Type= 6, Freq= 0, CH_1, rank 1
2026 12:41:43.329596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2027 12:41:43.329679 ==
2028 12:41:43.332796
2029 12:41:43.332877
2030 12:41:43.332943 TX Vref Scan disable
2031 12:41:43.336005 == TX Byte 0 ==
2032 12:41:43.339594 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2033 12:41:43.343053 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2034 12:41:43.346382 == TX Byte 1 ==
2035 12:41:43.349377 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2036 12:41:43.352853 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2037 12:41:43.356297
2038 12:41:43.356380 [DATLAT]
2039 12:41:43.356446 Freq=800, CH1 RK1
2040 12:41:43.356509
2041 12:41:43.359576 DATLAT Default: 0xa
2042 12:41:43.359659 0, 0xFFFF, sum = 0
2043 12:41:43.362975 1, 0xFFFF, sum = 0
2044 12:41:43.363061 2, 0xFFFF, sum = 0
2045 12:41:43.366365 3, 0xFFFF, sum = 0
2046 12:41:43.366449 4, 0xFFFF, sum = 0
2047 12:41:43.369803 5, 0xFFFF, sum = 0
2048 12:41:43.373218 6, 0xFFFF, sum = 0
2049 12:41:43.373303 7, 0xFFFF, sum = 0
2050 12:41:43.375830 8, 0xFFFF, sum = 0
2051 12:41:43.375915 9, 0x0, sum = 1
2052 12:41:43.375981 10, 0x0, sum = 2
2053 12:41:43.379275 11, 0x0, sum = 3
2054 12:41:43.379416 12, 0x0, sum = 4
2055 12:41:43.382645 best_step = 10
2056 12:41:43.382727
2057 12:41:43.382793 ==
2058 12:41:43.386155 Dram Type= 6, Freq= 0, CH_1, rank 1
2059 12:41:43.389647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2060 12:41:43.389756 ==
2061 12:41:43.392489 RX Vref Scan: 0
2062 12:41:43.392572
2063 12:41:43.392638 RX Vref 0 -> 0, step: 1
2064 12:41:43.392699
2065 12:41:43.396073 RX Delay -95 -> 252, step: 8
2066 12:41:43.402690 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2067 12:41:43.406342 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
2068 12:41:43.409689 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2069 12:41:43.412770 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2070 12:41:43.416148 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
2071 12:41:43.422611 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2072 12:41:43.426549 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2073 12:41:43.429656 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2074 12:41:43.433189 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
2075 12:41:43.436033 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2076 12:41:43.443029 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2077 12:41:43.446007 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2078 12:41:43.449658 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
2079 12:41:43.452845 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2080 12:41:43.456261 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2081 12:41:43.462627 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2082 12:41:43.462711 ==
2083 12:41:43.466176 Dram Type= 6, Freq= 0, CH_1, rank 1
2084 12:41:43.469423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2085 12:41:43.469507 ==
2086 12:41:43.469572 DQS Delay:
2087 12:41:43.472824 DQS0 = 0, DQS1 = 0
2088 12:41:43.472906 DQM Delay:
2089 12:41:43.476158 DQM0 = 81, DQM1 = 76
2090 12:41:43.476241 DQ Delay:
2091 12:41:43.479710 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2092 12:41:43.482765 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =76
2093 12:41:43.486234 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
2094 12:41:43.489606 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
2095 12:41:43.489689
2096 12:41:43.489755
2097 12:41:43.496403 [DQSOSCAuto] RK1, (LSB)MR18= 0x202c, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
2098 12:41:43.499258 CH1 RK1: MR19=606, MR18=202C
2099 12:41:43.505875 CH1_RK1: MR19=0x606, MR18=0x202C, DQSOSC=398, MR23=63, INC=93, DEC=62
2100 12:41:43.509339 [RxdqsGatingPostProcess] freq 800
2101 12:41:43.516163 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2102 12:41:43.519124 Pre-setting of DQS Precalculation
2103 12:41:43.522706 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2104 12:41:43.529465 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2105 12:41:43.536212 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2106 12:41:43.536296
2107 12:41:43.536361
2108 12:41:43.539676 [Calibration Summary] 1600 Mbps
2109 12:41:43.542829 CH 0, Rank 0
2110 12:41:43.542912 SW Impedance : PASS
2111 12:41:43.546352 DUTY Scan : NO K
2112 12:41:43.549481 ZQ Calibration : PASS
2113 12:41:43.549565 Jitter Meter : NO K
2114 12:41:43.552560 CBT Training : PASS
2115 12:41:43.556167 Write leveling : PASS
2116 12:41:43.556254 RX DQS gating : PASS
2117 12:41:43.559372 RX DQ/DQS(RDDQC) : PASS
2118 12:41:43.562799 TX DQ/DQS : PASS
2119 12:41:43.562882 RX DATLAT : PASS
2120 12:41:43.566186 RX DQ/DQS(Engine): PASS
2121 12:41:43.566269 TX OE : NO K
2122 12:41:43.569435 All Pass.
2123 12:41:43.569521
2124 12:41:43.569588 CH 0, Rank 1
2125 12:41:43.572700 SW Impedance : PASS
2126 12:41:43.572783 DUTY Scan : NO K
2127 12:41:43.576154 ZQ Calibration : PASS
2128 12:41:43.579139 Jitter Meter : NO K
2129 12:41:43.579221 CBT Training : PASS
2130 12:41:43.582608 Write leveling : PASS
2131 12:41:43.585942 RX DQS gating : PASS
2132 12:41:43.586025 RX DQ/DQS(RDDQC) : PASS
2133 12:41:43.589572 TX DQ/DQS : PASS
2134 12:41:43.593179 RX DATLAT : PASS
2135 12:41:43.593262 RX DQ/DQS(Engine): PASS
2136 12:41:43.596196 TX OE : NO K
2137 12:41:43.596279 All Pass.
2138 12:41:43.596345
2139 12:41:43.599194 CH 1, Rank 0
2140 12:41:43.599277 SW Impedance : PASS
2141 12:41:43.602804 DUTY Scan : NO K
2142 12:41:43.606003 ZQ Calibration : PASS
2143 12:41:43.606086 Jitter Meter : NO K
2144 12:41:43.609443 CBT Training : PASS
2145 12:41:43.609526 Write leveling : PASS
2146 12:41:43.613215 RX DQS gating : PASS
2147 12:41:43.616349 RX DQ/DQS(RDDQC) : PASS
2148 12:41:43.616441 TX DQ/DQS : PASS
2149 12:41:43.619384 RX DATLAT : PASS
2150 12:41:43.623098 RX DQ/DQS(Engine): PASS
2151 12:41:43.623180 TX OE : NO K
2152 12:41:43.626091 All Pass.
2153 12:41:43.626174
2154 12:41:43.626239 CH 1, Rank 1
2155 12:41:43.629437 SW Impedance : PASS
2156 12:41:43.629519 DUTY Scan : NO K
2157 12:41:43.632683 ZQ Calibration : PASS
2158 12:41:43.635950 Jitter Meter : NO K
2159 12:41:43.636033 CBT Training : PASS
2160 12:41:43.639668 Write leveling : PASS
2161 12:41:43.642504 RX DQS gating : PASS
2162 12:41:43.642587 RX DQ/DQS(RDDQC) : PASS
2163 12:41:43.646064 TX DQ/DQS : PASS
2164 12:41:43.649783 RX DATLAT : PASS
2165 12:41:43.649866 RX DQ/DQS(Engine): PASS
2166 12:41:43.653090 TX OE : NO K
2167 12:41:43.653174 All Pass.
2168 12:41:43.653241
2169 12:41:43.656367 DramC Write-DBI off
2170 12:41:43.659255 PER_BANK_REFRESH: Hybrid Mode
2171 12:41:43.659398 TX_TRACKING: ON
2172 12:41:43.662883 [GetDramInforAfterCalByMRR] Vendor 6.
2173 12:41:43.665622 [GetDramInforAfterCalByMRR] Revision 606.
2174 12:41:43.669417 [GetDramInforAfterCalByMRR] Revision 2 0.
2175 12:41:43.672711 MR0 0x3b3b
2176 12:41:43.672811 MR8 0x5151
2177 12:41:43.675789 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2178 12:41:43.675873
2179 12:41:43.675939 MR0 0x3b3b
2180 12:41:43.679172 MR8 0x5151
2181 12:41:43.682848 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2182 12:41:43.682931
2183 12:41:43.689364 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2184 12:41:43.696049 [FAST_K] Save calibration result to emmc
2185 12:41:43.699131 [FAST_K] Save calibration result to emmc
2186 12:41:43.699214 dram_init: config_dvfs: 1
2187 12:41:43.702758 dramc_set_vcore_voltage set vcore to 662500
2188 12:41:43.706250 Read voltage for 1200, 2
2189 12:41:43.706334 Vio18 = 0
2190 12:41:43.709063 Vcore = 662500
2191 12:41:43.709146 Vdram = 0
2192 12:41:43.709212 Vddq = 0
2193 12:41:43.712492 Vmddr = 0
2194 12:41:43.715695 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2195 12:41:43.722538 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2196 12:41:43.722622 MEM_TYPE=3, freq_sel=15
2197 12:41:43.725829 sv_algorithm_assistance_LP4_1600
2198 12:41:43.732369 ============ PULL DRAM RESETB DOWN ============
2199 12:41:43.735468 ========== PULL DRAM RESETB DOWN end =========
2200 12:41:43.739048 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2201 12:41:43.742269 ===================================
2202 12:41:43.745914 LPDDR4 DRAM CONFIGURATION
2203 12:41:43.749158 ===================================
2204 12:41:43.752456 EX_ROW_EN[0] = 0x0
2205 12:41:43.752539 EX_ROW_EN[1] = 0x0
2206 12:41:43.755842 LP4Y_EN = 0x0
2207 12:41:43.755926 WORK_FSP = 0x0
2208 12:41:43.759248 WL = 0x4
2209 12:41:43.759334 RL = 0x4
2210 12:41:43.762247 BL = 0x2
2211 12:41:43.762330 RPST = 0x0
2212 12:41:43.765648 RD_PRE = 0x0
2213 12:41:43.765731 WR_PRE = 0x1
2214 12:41:43.768770 WR_PST = 0x0
2215 12:41:43.768853 DBI_WR = 0x0
2216 12:41:43.772374 DBI_RD = 0x0
2217 12:41:43.772457 OTF = 0x1
2218 12:41:43.775764 ===================================
2219 12:41:43.779117 ===================================
2220 12:41:43.782533 ANA top config
2221 12:41:43.785730 ===================================
2222 12:41:43.789288 DLL_ASYNC_EN = 0
2223 12:41:43.789371 ALL_SLAVE_EN = 0
2224 12:41:43.792465 NEW_RANK_MODE = 1
2225 12:41:43.795670 DLL_IDLE_MODE = 1
2226 12:41:43.799094 LP45_APHY_COMB_EN = 1
2227 12:41:43.799176 TX_ODT_DIS = 1
2228 12:41:43.802173 NEW_8X_MODE = 1
2229 12:41:43.805586 ===================================
2230 12:41:43.809241 ===================================
2231 12:41:43.812502 data_rate = 2400
2232 12:41:43.815604 CKR = 1
2233 12:41:43.819010 DQ_P2S_RATIO = 8
2234 12:41:43.822188 ===================================
2235 12:41:43.822271 CA_P2S_RATIO = 8
2236 12:41:43.825672 DQ_CA_OPEN = 0
2237 12:41:43.829378 DQ_SEMI_OPEN = 0
2238 12:41:43.832493 CA_SEMI_OPEN = 0
2239 12:41:43.835892 CA_FULL_RATE = 0
2240 12:41:43.838808 DQ_CKDIV4_EN = 0
2241 12:41:43.838892 CA_CKDIV4_EN = 0
2242 12:41:43.842387 CA_PREDIV_EN = 0
2243 12:41:43.846003 PH8_DLY = 17
2244 12:41:43.848739 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2245 12:41:43.852953 DQ_AAMCK_DIV = 4
2246 12:41:43.855645 CA_AAMCK_DIV = 4
2247 12:41:43.855732 CA_ADMCK_DIV = 4
2248 12:41:43.858973 DQ_TRACK_CA_EN = 0
2249 12:41:43.862312 CA_PICK = 1200
2250 12:41:43.865518 CA_MCKIO = 1200
2251 12:41:43.868724 MCKIO_SEMI = 0
2252 12:41:43.872125 PLL_FREQ = 2366
2253 12:41:43.875830 DQ_UI_PI_RATIO = 32
2254 12:41:43.879241 CA_UI_PI_RATIO = 0
2255 12:41:43.882118 ===================================
2256 12:41:43.882202 ===================================
2257 12:41:43.885455 memory_type:LPDDR4
2258 12:41:43.889305 GP_NUM : 10
2259 12:41:43.889388 SRAM_EN : 1
2260 12:41:43.892028 MD32_EN : 0
2261 12:41:43.895268 ===================================
2262 12:41:43.898931 [ANA_INIT] >>>>>>>>>>>>>>
2263 12:41:43.901951 <<<<<< [CONFIGURE PHASE]: ANA_TX
2264 12:41:43.905446 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2265 12:41:43.908955 ===================================
2266 12:41:43.909067 data_rate = 2400,PCW = 0X5b00
2267 12:41:43.912430 ===================================
2268 12:41:43.915906 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2269 12:41:43.921946 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2270 12:41:43.928959 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2271 12:41:43.931952 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2272 12:41:43.935331 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2273 12:41:43.938756 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2274 12:41:43.942009 [ANA_INIT] flow start
2275 12:41:43.945408 [ANA_INIT] PLL >>>>>>>>
2276 12:41:43.945492 [ANA_INIT] PLL <<<<<<<<
2277 12:41:43.948682 [ANA_INIT] MIDPI >>>>>>>>
2278 12:41:43.952127 [ANA_INIT] MIDPI <<<<<<<<
2279 12:41:43.952210 [ANA_INIT] DLL >>>>>>>>
2280 12:41:43.955145 [ANA_INIT] DLL <<<<<<<<
2281 12:41:43.958807 [ANA_INIT] flow end
2282 12:41:43.962250 ============ LP4 DIFF to SE enter ============
2283 12:41:43.965497 ============ LP4 DIFF to SE exit ============
2284 12:41:43.968581 [ANA_INIT] <<<<<<<<<<<<<
2285 12:41:43.972007 [Flow] Enable top DCM control >>>>>
2286 12:41:43.975462 [Flow] Enable top DCM control <<<<<
2287 12:41:43.978775 Enable DLL master slave shuffle
2288 12:41:43.982331 ==============================================================
2289 12:41:43.985575 Gating Mode config
2290 12:41:43.988754 ==============================================================
2291 12:41:43.992369 Config description:
2292 12:41:44.001904 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2293 12:41:44.008660 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2294 12:41:44.011938 SELPH_MODE 0: By rank 1: By Phase
2295 12:41:44.018453 ==============================================================
2296 12:41:44.021885 GAT_TRACK_EN = 1
2297 12:41:44.025502 RX_GATING_MODE = 2
2298 12:41:44.028380 RX_GATING_TRACK_MODE = 2
2299 12:41:44.031806 SELPH_MODE = 1
2300 12:41:44.035273 PICG_EARLY_EN = 1
2301 12:41:44.035377 VALID_LAT_VALUE = 1
2302 12:41:44.042211 ==============================================================
2303 12:41:44.045320 Enter into Gating configuration >>>>
2304 12:41:44.048614 Exit from Gating configuration <<<<
2305 12:41:44.051774 Enter into DVFS_PRE_config >>>>>
2306 12:41:44.062160 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2307 12:41:44.065201 Exit from DVFS_PRE_config <<<<<
2308 12:41:44.068397 Enter into PICG configuration >>>>
2309 12:41:44.071877 Exit from PICG configuration <<<<
2310 12:41:44.075274 [RX_INPUT] configuration >>>>>
2311 12:41:44.078791 [RX_INPUT] configuration <<<<<
2312 12:41:44.082183 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2313 12:41:44.088473 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2314 12:41:44.095262 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2315 12:41:44.101588 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2316 12:41:44.108509 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2317 12:41:44.115019 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2318 12:41:44.118308 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2319 12:41:44.122054 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2320 12:41:44.125595 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2321 12:41:44.128338 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2322 12:41:44.135426 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2323 12:41:44.138564 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2324 12:41:44.141591 ===================================
2325 12:41:44.144893 LPDDR4 DRAM CONFIGURATION
2326 12:41:44.148982 ===================================
2327 12:41:44.149055 EX_ROW_EN[0] = 0x0
2328 12:41:44.151564 EX_ROW_EN[1] = 0x0
2329 12:41:44.151640 LP4Y_EN = 0x0
2330 12:41:44.155264 WORK_FSP = 0x0
2331 12:41:44.155389 WL = 0x4
2332 12:41:44.158368 RL = 0x4
2333 12:41:44.158473 BL = 0x2
2334 12:41:44.161886 RPST = 0x0
2335 12:41:44.161963 RD_PRE = 0x0
2336 12:41:44.165291 WR_PRE = 0x1
2337 12:41:44.168524 WR_PST = 0x0
2338 12:41:44.168625 DBI_WR = 0x0
2339 12:41:44.171589 DBI_RD = 0x0
2340 12:41:44.171662 OTF = 0x1
2341 12:41:44.175300 ===================================
2342 12:41:44.178299 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2343 12:41:44.181602 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2344 12:41:44.188311 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2345 12:41:44.191790 ===================================
2346 12:41:44.195163 LPDDR4 DRAM CONFIGURATION
2347 12:41:44.198377 ===================================
2348 12:41:44.198475 EX_ROW_EN[0] = 0x10
2349 12:41:44.201457 EX_ROW_EN[1] = 0x0
2350 12:41:44.201562 LP4Y_EN = 0x0
2351 12:41:44.205169 WORK_FSP = 0x0
2352 12:41:44.205241 WL = 0x4
2353 12:41:44.208008 RL = 0x4
2354 12:41:44.208113 BL = 0x2
2355 12:41:44.211662 RPST = 0x0
2356 12:41:44.211766 RD_PRE = 0x0
2357 12:41:44.215179 WR_PRE = 0x1
2358 12:41:44.215283 WR_PST = 0x0
2359 12:41:44.218086 DBI_WR = 0x0
2360 12:41:44.218169 DBI_RD = 0x0
2361 12:41:44.221390 OTF = 0x1
2362 12:41:44.224770 ===================================
2363 12:41:44.231717 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2364 12:41:44.231792 ==
2365 12:41:44.234844 Dram Type= 6, Freq= 0, CH_0, rank 0
2366 12:41:44.238135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2367 12:41:44.238231 ==
2368 12:41:44.241290 [Duty_Offset_Calibration]
2369 12:41:44.241385 B0:2 B1:-1 CA:1
2370 12:41:44.241481
2371 12:41:44.244692 [DutyScan_Calibration_Flow] k_type=0
2372 12:41:44.254700
2373 12:41:44.254822 ==CLK 0==
2374 12:41:44.258004 Final CLK duty delay cell = -4
2375 12:41:44.261978 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2376 12:41:44.264861 [-4] MIN Duty = 4875%(X100), DQS PI = 32
2377 12:41:44.268137 [-4] AVG Duty = 4953%(X100)
2378 12:41:44.268232
2379 12:41:44.271559 CH0 CLK Duty spec in!! Max-Min= 156%
2380 12:41:44.274841 [DutyScan_Calibration_Flow] ====Done====
2381 12:41:44.274943
2382 12:41:44.277748 [DutyScan_Calibration_Flow] k_type=1
2383 12:41:44.292940
2384 12:41:44.293038 ==DQS 0 ==
2385 12:41:44.296176 Final DQS duty delay cell = -4
2386 12:41:44.299666 [-4] MAX Duty = 5000%(X100), DQS PI = 42
2387 12:41:44.302561 [-4] MIN Duty = 4876%(X100), DQS PI = 10
2388 12:41:44.306037 [-4] AVG Duty = 4938%(X100)
2389 12:41:44.306132
2390 12:41:44.306220 ==DQS 1 ==
2391 12:41:44.309457 Final DQS duty delay cell = -4
2392 12:41:44.312857 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2393 12:41:44.315827 [-4] MIN Duty = 5000%(X100), DQS PI = 50
2394 12:41:44.319289 [-4] AVG Duty = 5062%(X100)
2395 12:41:44.319386
2396 12:41:44.322810 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2397 12:41:44.322877
2398 12:41:44.325944 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2399 12:41:44.329437 [DutyScan_Calibration_Flow] ====Done====
2400 12:41:44.329504
2401 12:41:44.332584 [DutyScan_Calibration_Flow] k_type=3
2402 12:41:44.349742
2403 12:41:44.349824 ==DQM 0 ==
2404 12:41:44.353080 Final DQM duty delay cell = 0
2405 12:41:44.356715 [0] MAX Duty = 5031%(X100), DQS PI = 54
2406 12:41:44.360171 [0] MIN Duty = 4876%(X100), DQS PI = 22
2407 12:41:44.360247 [0] AVG Duty = 4953%(X100)
2408 12:41:44.363681
2409 12:41:44.363753 ==DQM 1 ==
2410 12:41:44.366598 Final DQM duty delay cell = 0
2411 12:41:44.369940 [0] MAX Duty = 5124%(X100), DQS PI = 0
2412 12:41:44.373599 [0] MIN Duty = 4969%(X100), DQS PI = 10
2413 12:41:44.373705 [0] AVG Duty = 5046%(X100)
2414 12:41:44.376711
2415 12:41:44.379979 CH0 DQM 0 Duty spec in!! Max-Min= 155%
2416 12:41:44.380077
2417 12:41:44.383243 CH0 DQM 1 Duty spec in!! Max-Min= 155%
2418 12:41:44.386806 [DutyScan_Calibration_Flow] ====Done====
2419 12:41:44.386904
2420 12:41:44.390016 [DutyScan_Calibration_Flow] k_type=2
2421 12:41:44.405693
2422 12:41:44.405776 ==DQ 0 ==
2423 12:41:44.409338 Final DQ duty delay cell = -4
2424 12:41:44.412290 [-4] MAX Duty = 5031%(X100), DQS PI = 38
2425 12:41:44.415790 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2426 12:41:44.418969 [-4] AVG Duty = 4953%(X100)
2427 12:41:44.419042
2428 12:41:44.419110 ==DQ 1 ==
2429 12:41:44.422228 Final DQ duty delay cell = 0
2430 12:41:44.425512 [0] MAX Duty = 5031%(X100), DQS PI = 26
2431 12:41:44.429113 [0] MIN Duty = 4907%(X100), DQS PI = 46
2432 12:41:44.432396 [0] AVG Duty = 4969%(X100)
2433 12:41:44.432478
2434 12:41:44.435971 CH0 DQ 0 Duty spec in!! Max-Min= 155%
2435 12:41:44.436054
2436 12:41:44.439241 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2437 12:41:44.442229 [DutyScan_Calibration_Flow] ====Done====
2438 12:41:44.442311 ==
2439 12:41:44.446229 Dram Type= 6, Freq= 0, CH_1, rank 0
2440 12:41:44.449047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2441 12:41:44.449134 ==
2442 12:41:44.452262 [Duty_Offset_Calibration]
2443 12:41:44.452344 B0:1 B1:1 CA:2
2444 12:41:44.452409
2445 12:41:44.455751 [DutyScan_Calibration_Flow] k_type=0
2446 12:41:44.465983
2447 12:41:44.466066 ==CLK 0==
2448 12:41:44.469272 Final CLK duty delay cell = 0
2449 12:41:44.472915 [0] MAX Duty = 5094%(X100), DQS PI = 48
2450 12:41:44.475980 [0] MIN Duty = 4969%(X100), DQS PI = 8
2451 12:41:44.476062 [0] AVG Duty = 5031%(X100)
2452 12:41:44.476127
2453 12:41:44.479985 CH1 CLK Duty spec in!! Max-Min= 125%
2454 12:41:44.486646 [DutyScan_Calibration_Flow] ====Done====
2455 12:41:44.486729
2456 12:41:44.489456 [DutyScan_Calibration_Flow] k_type=1
2457 12:41:44.505381
2458 12:41:44.505460 ==DQS 0 ==
2459 12:41:44.508716 Final DQS duty delay cell = 0
2460 12:41:44.511796 [0] MAX Duty = 5062%(X100), DQS PI = 50
2461 12:41:44.515297 [0] MIN Duty = 4875%(X100), DQS PI = 16
2462 12:41:44.518579 [0] AVG Duty = 4968%(X100)
2463 12:41:44.518655
2464 12:41:44.518723 ==DQS 1 ==
2465 12:41:44.522053 Final DQS duty delay cell = 0
2466 12:41:44.525280 [0] MAX Duty = 5062%(X100), DQS PI = 22
2467 12:41:44.528730 [0] MIN Duty = 4907%(X100), DQS PI = 0
2468 12:41:44.531822 [0] AVG Duty = 4984%(X100)
2469 12:41:44.531896
2470 12:41:44.535260 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2471 12:41:44.535345
2472 12:41:44.538707 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2473 12:41:44.542117 [DutyScan_Calibration_Flow] ====Done====
2474 12:41:44.542189
2475 12:41:44.545297 [DutyScan_Calibration_Flow] k_type=3
2476 12:41:44.562071
2477 12:41:44.562155 ==DQM 0 ==
2478 12:41:44.565482 Final DQM duty delay cell = 0
2479 12:41:44.568392 [0] MAX Duty = 5093%(X100), DQS PI = 6
2480 12:41:44.571605 [0] MIN Duty = 4907%(X100), DQS PI = 18
2481 12:41:44.571678 [0] AVG Duty = 5000%(X100)
2482 12:41:44.575186
2483 12:41:44.575257 ==DQM 1 ==
2484 12:41:44.578567 Final DQM duty delay cell = 0
2485 12:41:44.581878 [0] MAX Duty = 5156%(X100), DQS PI = 30
2486 12:41:44.585276 [0] MIN Duty = 4938%(X100), DQS PI = 56
2487 12:41:44.585348 [0] AVG Duty = 5047%(X100)
2488 12:41:44.588730
2489 12:41:44.592004 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2490 12:41:44.592077
2491 12:41:44.595163 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2492 12:41:44.598306 [DutyScan_Calibration_Flow] ====Done====
2493 12:41:44.598379
2494 12:41:44.601500 [DutyScan_Calibration_Flow] k_type=2
2495 12:41:44.618274
2496 12:41:44.618355 ==DQ 0 ==
2497 12:41:44.621549 Final DQ duty delay cell = 0
2498 12:41:44.624806 [0] MAX Duty = 5093%(X100), DQS PI = 50
2499 12:41:44.628542 [0] MIN Duty = 4969%(X100), DQS PI = 18
2500 12:41:44.628623 [0] AVG Duty = 5031%(X100)
2501 12:41:44.628689
2502 12:41:44.631403 ==DQ 1 ==
2503 12:41:44.634725 Final DQ duty delay cell = 0
2504 12:41:44.638147 [0] MAX Duty = 5124%(X100), DQS PI = 26
2505 12:41:44.641630 [0] MIN Duty = 5031%(X100), DQS PI = 2
2506 12:41:44.641703 [0] AVG Duty = 5077%(X100)
2507 12:41:44.641766
2508 12:41:44.645269 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2509 12:41:44.645340
2510 12:41:44.648056 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2511 12:41:44.654845 [DutyScan_Calibration_Flow] ====Done====
2512 12:41:44.658204 nWR fixed to 30
2513 12:41:44.658288 [ModeRegInit_LP4] CH0 RK0
2514 12:41:44.662130 [ModeRegInit_LP4] CH0 RK1
2515 12:41:44.665301 [ModeRegInit_LP4] CH1 RK0
2516 12:41:44.665383 [ModeRegInit_LP4] CH1 RK1
2517 12:41:44.668147 match AC timing 7
2518 12:41:44.671717 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2519 12:41:44.675266 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2520 12:41:44.681552 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2521 12:41:44.685084 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2522 12:41:44.691800 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2523 12:41:44.691883 ==
2524 12:41:44.695501 Dram Type= 6, Freq= 0, CH_0, rank 0
2525 12:41:44.698289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2526 12:41:44.698373 ==
2527 12:41:44.704884 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2528 12:41:44.708160 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2529 12:41:44.718119 [CA 0] Center 40 (10~71) winsize 62
2530 12:41:44.721236 [CA 1] Center 39 (9~70) winsize 62
2531 12:41:44.725117 [CA 2] Center 36 (6~67) winsize 62
2532 12:41:44.728261 [CA 3] Center 36 (5~67) winsize 63
2533 12:41:44.731523 [CA 4] Center 35 (5~65) winsize 61
2534 12:41:44.734938 [CA 5] Center 34 (4~64) winsize 61
2535 12:41:44.735021
2536 12:41:44.738393 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2537 12:41:44.738476
2538 12:41:44.741417 [CATrainingPosCal] consider 1 rank data
2539 12:41:44.744872 u2DelayCellTimex100 = 270/100 ps
2540 12:41:44.748175 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2541 12:41:44.754736 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2542 12:41:44.758220 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2543 12:41:44.761385 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2544 12:41:44.764423 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2545 12:41:44.768314 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2546 12:41:44.768397
2547 12:41:44.771376 CA PerBit enable=1, Macro0, CA PI delay=34
2548 12:41:44.771474
2549 12:41:44.775045 [CBTSetCACLKResult] CA Dly = 34
2550 12:41:44.775129 CS Dly: 7 (0~38)
2551 12:41:44.778367 ==
2552 12:41:44.781280 Dram Type= 6, Freq= 0, CH_0, rank 1
2553 12:41:44.784507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2554 12:41:44.784594 ==
2555 12:41:44.788444 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2556 12:41:44.794438 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2557 12:41:44.804166 [CA 0] Center 39 (9~70) winsize 62
2558 12:41:44.807446 [CA 1] Center 40 (10~70) winsize 61
2559 12:41:44.810744 [CA 2] Center 36 (6~67) winsize 62
2560 12:41:44.814387 [CA 3] Center 36 (5~67) winsize 63
2561 12:41:44.817416 [CA 4] Center 34 (4~65) winsize 62
2562 12:41:44.820586 [CA 5] Center 34 (4~64) winsize 61
2563 12:41:44.820669
2564 12:41:44.824386 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2565 12:41:44.824469
2566 12:41:44.827144 [CATrainingPosCal] consider 2 rank data
2567 12:41:44.830791 u2DelayCellTimex100 = 270/100 ps
2568 12:41:44.834360 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2569 12:41:44.840904 CA1 delay=40 (10~70),Diff = 6 PI (28 cell)
2570 12:41:44.844145 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2571 12:41:44.847532 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2572 12:41:44.850475 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2573 12:41:44.853860 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2574 12:41:44.853943
2575 12:41:44.857392 CA PerBit enable=1, Macro0, CA PI delay=34
2576 12:41:44.857475
2577 12:41:44.860752 [CBTSetCACLKResult] CA Dly = 34
2578 12:41:44.860836 CS Dly: 8 (0~41)
2579 12:41:44.860902
2580 12:41:44.864267 ----->DramcWriteLeveling(PI) begin...
2581 12:41:44.867285 ==
2582 12:41:44.870568 Dram Type= 6, Freq= 0, CH_0, rank 0
2583 12:41:44.874337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2584 12:41:44.874421 ==
2585 12:41:44.877513 Write leveling (Byte 0): 31 => 31
2586 12:41:44.880966 Write leveling (Byte 1): 31 => 31
2587 12:41:44.884264 DramcWriteLeveling(PI) end<-----
2588 12:41:44.884347
2589 12:41:44.884412 ==
2590 12:41:44.887746 Dram Type= 6, Freq= 0, CH_0, rank 0
2591 12:41:44.890910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2592 12:41:44.891020 ==
2593 12:41:44.893916 [Gating] SW mode calibration
2594 12:41:44.900836 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2595 12:41:44.903944 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2596 12:41:44.911102 0 15 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
2597 12:41:44.914240 0 15 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2598 12:41:44.917649 0 15 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2599 12:41:44.924548 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2600 12:41:44.927217 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2601 12:41:44.930778 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2602 12:41:44.937289 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2603 12:41:44.940796 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2604 12:41:44.944599 1 0 0 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
2605 12:41:44.951092 1 0 4 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
2606 12:41:44.953921 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2607 12:41:44.957465 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2608 12:41:44.964386 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2609 12:41:44.967372 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2610 12:41:44.970774 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2611 12:41:44.977258 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2612 12:41:44.980587 1 1 0 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
2613 12:41:44.983985 1 1 4 | B1->B0 | 3838 4141 | 0 1 | (0 0) (0 0)
2614 12:41:44.990839 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2615 12:41:44.994175 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2616 12:41:44.997409 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2617 12:41:45.000969 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2618 12:41:45.007941 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 12:41:45.011301 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 12:41:45.014224 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2621 12:41:45.020817 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2622 12:41:45.024240 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 12:41:45.027541 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 12:41:45.033924 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 12:41:45.037405 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 12:41:45.040726 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 12:41:45.047449 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 12:41:45.050787 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 12:41:45.053662 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 12:41:45.060704 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 12:41:45.064089 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 12:41:45.067232 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 12:41:45.074352 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 12:41:45.077558 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 12:41:45.080597 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2636 12:41:45.087053 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2637 12:41:45.090464 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2638 12:41:45.093957 Total UI for P1: 0, mck2ui 16
2639 12:41:45.097282 best dqsien dly found for B0: ( 1, 3, 30)
2640 12:41:45.100299 Total UI for P1: 0, mck2ui 16
2641 12:41:45.103729 best dqsien dly found for B1: ( 1, 4, 0)
2642 12:41:45.107471 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2643 12:41:45.110613 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2644 12:41:45.110687
2645 12:41:45.113881 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2646 12:41:45.117138 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2647 12:41:45.120611 [Gating] SW calibration Done
2648 12:41:45.120684 ==
2649 12:41:45.123774 Dram Type= 6, Freq= 0, CH_0, rank 0
2650 12:41:45.127205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2651 12:41:45.127278 ==
2652 12:41:45.130593 RX Vref Scan: 0
2653 12:41:45.130661
2654 12:41:45.134220 RX Vref 0 -> 0, step: 1
2655 12:41:45.134307
2656 12:41:45.134393 RX Delay -40 -> 252, step: 8
2657 12:41:45.140392 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2658 12:41:45.143668 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2659 12:41:45.147083 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2660 12:41:45.150448 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2661 12:41:45.153743 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2662 12:41:45.160486 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2663 12:41:45.163886 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2664 12:41:45.167128 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2665 12:41:45.170802 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2666 12:41:45.173632 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2667 12:41:45.177036 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2668 12:41:45.183929 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2669 12:41:45.187113 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2670 12:41:45.190473 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2671 12:41:45.193761 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2672 12:41:45.200223 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2673 12:41:45.200308 ==
2674 12:41:45.203726 Dram Type= 6, Freq= 0, CH_0, rank 0
2675 12:41:45.207100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2676 12:41:45.207186 ==
2677 12:41:45.207290 DQS Delay:
2678 12:41:45.210232 DQS0 = 0, DQS1 = 0
2679 12:41:45.210317 DQM Delay:
2680 12:41:45.213387 DQM0 = 115, DQM1 = 107
2681 12:41:45.213473 DQ Delay:
2682 12:41:45.217259 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111
2683 12:41:45.220204 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2684 12:41:45.223508 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2685 12:41:45.227176 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2686 12:41:45.227262
2687 12:41:45.227353
2688 12:41:45.227469 ==
2689 12:41:45.230680 Dram Type= 6, Freq= 0, CH_0, rank 0
2690 12:41:45.236739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2691 12:41:45.236826 ==
2692 12:41:45.236911
2693 12:41:45.236992
2694 12:41:45.237070 TX Vref Scan disable
2695 12:41:45.240537 == TX Byte 0 ==
2696 12:41:45.244170 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2697 12:41:45.247271 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2698 12:41:45.250818 == TX Byte 1 ==
2699 12:41:45.253905 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2700 12:41:45.260478 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2701 12:41:45.260564 ==
2702 12:41:45.264095 Dram Type= 6, Freq= 0, CH_0, rank 0
2703 12:41:45.267665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2704 12:41:45.267766 ==
2705 12:41:45.278520 TX Vref=22, minBit 1, minWin=24, winSum=409
2706 12:41:45.281388 TX Vref=24, minBit 1, minWin=25, winSum=421
2707 12:41:45.285366 TX Vref=26, minBit 3, minWin=25, winSum=420
2708 12:41:45.288318 TX Vref=28, minBit 0, minWin=26, winSum=427
2709 12:41:45.291835 TX Vref=30, minBit 1, minWin=26, winSum=429
2710 12:41:45.298077 TX Vref=32, minBit 12, minWin=25, winSum=425
2711 12:41:45.301452 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 30
2712 12:41:45.301539
2713 12:41:45.305484 Final TX Range 1 Vref 30
2714 12:41:45.305570
2715 12:41:45.305657 ==
2716 12:41:45.308281 Dram Type= 6, Freq= 0, CH_0, rank 0
2717 12:41:45.311619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2718 12:41:45.311705 ==
2719 12:41:45.315296
2720 12:41:45.315401
2721 12:41:45.315486 TX Vref Scan disable
2722 12:41:45.318345 == TX Byte 0 ==
2723 12:41:45.321387 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2724 12:41:45.324999 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2725 12:41:45.328170 == TX Byte 1 ==
2726 12:41:45.331797 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2727 12:41:45.334844 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2728 12:41:45.334930
2729 12:41:45.338715 [DATLAT]
2730 12:41:45.338800 Freq=1200, CH0 RK0
2731 12:41:45.338887
2732 12:41:45.341581 DATLAT Default: 0xd
2733 12:41:45.341667 0, 0xFFFF, sum = 0
2734 12:41:45.344915 1, 0xFFFF, sum = 0
2735 12:41:45.345002 2, 0xFFFF, sum = 0
2736 12:41:45.348685 3, 0xFFFF, sum = 0
2737 12:41:45.348771 4, 0xFFFF, sum = 0
2738 12:41:45.351697 5, 0xFFFF, sum = 0
2739 12:41:45.351784 6, 0xFFFF, sum = 0
2740 12:41:45.355104 7, 0xFFFF, sum = 0
2741 12:41:45.355191 8, 0xFFFF, sum = 0
2742 12:41:45.358152 9, 0xFFFF, sum = 0
2743 12:41:45.361474 10, 0xFFFF, sum = 0
2744 12:41:45.361561 11, 0xFFFF, sum = 0
2745 12:41:45.365112 12, 0x0, sum = 1
2746 12:41:45.365198 13, 0x0, sum = 2
2747 12:41:45.365285 14, 0x0, sum = 3
2748 12:41:45.368783 15, 0x0, sum = 4
2749 12:41:45.368870 best_step = 13
2750 12:41:45.368956
2751 12:41:45.369036 ==
2752 12:41:45.371936 Dram Type= 6, Freq= 0, CH_0, rank 0
2753 12:41:45.378367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2754 12:41:45.378453 ==
2755 12:41:45.378539 RX Vref Scan: 1
2756 12:41:45.378620
2757 12:41:45.382028 Set Vref Range= 32 -> 127
2758 12:41:45.382113
2759 12:41:45.384997 RX Vref 32 -> 127, step: 1
2760 12:41:45.385082
2761 12:41:45.388307 RX Delay -21 -> 252, step: 4
2762 12:41:45.388392
2763 12:41:45.391540 Set Vref, RX VrefLevel [Byte0]: 32
2764 12:41:45.395244 [Byte1]: 32
2765 12:41:45.395330
2766 12:41:45.398178 Set Vref, RX VrefLevel [Byte0]: 33
2767 12:41:45.402040 [Byte1]: 33
2768 12:41:45.402125
2769 12:41:45.405325 Set Vref, RX VrefLevel [Byte0]: 34
2770 12:41:45.408486 [Byte1]: 34
2771 12:41:45.412454
2772 12:41:45.412539 Set Vref, RX VrefLevel [Byte0]: 35
2773 12:41:45.415907 [Byte1]: 35
2774 12:41:45.420457
2775 12:41:45.420542 Set Vref, RX VrefLevel [Byte0]: 36
2776 12:41:45.424071 [Byte1]: 36
2777 12:41:45.428122
2778 12:41:45.428208 Set Vref, RX VrefLevel [Byte0]: 37
2779 12:41:45.431667 [Byte1]: 37
2780 12:41:45.436312
2781 12:41:45.436397 Set Vref, RX VrefLevel [Byte0]: 38
2782 12:41:45.439830 [Byte1]: 38
2783 12:41:45.444225
2784 12:41:45.444348 Set Vref, RX VrefLevel [Byte0]: 39
2785 12:41:45.447485 [Byte1]: 39
2786 12:41:45.452225
2787 12:41:45.452310 Set Vref, RX VrefLevel [Byte0]: 40
2788 12:41:45.455449 [Byte1]: 40
2789 12:41:45.460315
2790 12:41:45.460401 Set Vref, RX VrefLevel [Byte0]: 41
2791 12:41:45.463521 [Byte1]: 41
2792 12:41:45.468070
2793 12:41:45.468155 Set Vref, RX VrefLevel [Byte0]: 42
2794 12:41:45.471279 [Byte1]: 42
2795 12:41:45.475663
2796 12:41:45.475748 Set Vref, RX VrefLevel [Byte0]: 43
2797 12:41:45.479039 [Byte1]: 43
2798 12:41:45.483597
2799 12:41:45.483682 Set Vref, RX VrefLevel [Byte0]: 44
2800 12:41:45.487337 [Byte1]: 44
2801 12:41:45.491970
2802 12:41:45.492055 Set Vref, RX VrefLevel [Byte0]: 45
2803 12:41:45.494809 [Byte1]: 45
2804 12:41:45.499621
2805 12:41:45.499706 Set Vref, RX VrefLevel [Byte0]: 46
2806 12:41:45.503072 [Byte1]: 46
2807 12:41:45.507616
2808 12:41:45.507702 Set Vref, RX VrefLevel [Byte0]: 47
2809 12:41:45.510807 [Byte1]: 47
2810 12:41:45.515674
2811 12:41:45.515759 Set Vref, RX VrefLevel [Byte0]: 48
2812 12:41:45.518596 [Byte1]: 48
2813 12:41:45.523228
2814 12:41:45.523313 Set Vref, RX VrefLevel [Byte0]: 49
2815 12:41:45.526803 [Byte1]: 49
2816 12:41:45.531809
2817 12:41:45.531893 Set Vref, RX VrefLevel [Byte0]: 50
2818 12:41:45.534800 [Byte1]: 50
2819 12:41:45.539442
2820 12:41:45.539524 Set Vref, RX VrefLevel [Byte0]: 51
2821 12:41:45.542675 [Byte1]: 51
2822 12:41:45.547295
2823 12:41:45.547398 Set Vref, RX VrefLevel [Byte0]: 52
2824 12:41:45.550598 [Byte1]: 52
2825 12:41:45.555303
2826 12:41:45.555404 Set Vref, RX VrefLevel [Byte0]: 53
2827 12:41:45.558375 [Byte1]: 53
2828 12:41:45.563585
2829 12:41:45.563667 Set Vref, RX VrefLevel [Byte0]: 54
2830 12:41:45.566385 [Byte1]: 54
2831 12:41:45.571222
2832 12:41:45.571334 Set Vref, RX VrefLevel [Byte0]: 55
2833 12:41:45.574322 [Byte1]: 55
2834 12:41:45.578776
2835 12:41:45.578859 Set Vref, RX VrefLevel [Byte0]: 56
2836 12:41:45.582007 [Byte1]: 56
2837 12:41:45.586648
2838 12:41:45.586730 Set Vref, RX VrefLevel [Byte0]: 57
2839 12:41:45.590068 [Byte1]: 57
2840 12:41:45.595075
2841 12:41:45.595157 Set Vref, RX VrefLevel [Byte0]: 58
2842 12:41:45.597758 [Byte1]: 58
2843 12:41:45.602841
2844 12:41:45.602923 Set Vref, RX VrefLevel [Byte0]: 59
2845 12:41:45.606067 [Byte1]: 59
2846 12:41:45.610891
2847 12:41:45.610973 Set Vref, RX VrefLevel [Byte0]: 60
2848 12:41:45.614106 [Byte1]: 60
2849 12:41:45.618147
2850 12:41:45.621588 Set Vref, RX VrefLevel [Byte0]: 61
2851 12:41:45.624893 [Byte1]: 61
2852 12:41:45.624976
2853 12:41:45.628385 Set Vref, RX VrefLevel [Byte0]: 62
2854 12:41:45.631931 [Byte1]: 62
2855 12:41:45.632014
2856 12:41:45.635147 Set Vref, RX VrefLevel [Byte0]: 63
2857 12:41:45.638543 [Byte1]: 63
2858 12:41:45.642105
2859 12:41:45.642216 Set Vref, RX VrefLevel [Byte0]: 64
2860 12:41:45.645666 [Byte1]: 64
2861 12:41:45.650055
2862 12:41:45.650140 Set Vref, RX VrefLevel [Byte0]: 65
2863 12:41:45.653418 [Byte1]: 65
2864 12:41:45.658315
2865 12:41:45.658401 Set Vref, RX VrefLevel [Byte0]: 66
2866 12:41:45.661600 [Byte1]: 66
2867 12:41:45.666130
2868 12:41:45.666216 Set Vref, RX VrefLevel [Byte0]: 67
2869 12:41:45.669373 [Byte1]: 67
2870 12:41:45.673794
2871 12:41:45.673879 Set Vref, RX VrefLevel [Byte0]: 68
2872 12:41:45.677413 [Byte1]: 68
2873 12:41:45.681994
2874 12:41:45.682079 Set Vref, RX VrefLevel [Byte0]: 69
2875 12:41:45.688351 [Byte1]: 69
2876 12:41:45.688436
2877 12:41:45.692213 Final RX Vref Byte 0 = 55 to rank0
2878 12:41:45.695170 Final RX Vref Byte 1 = 51 to rank0
2879 12:41:45.698804 Final RX Vref Byte 0 = 55 to rank1
2880 12:41:45.701610 Final RX Vref Byte 1 = 51 to rank1==
2881 12:41:45.705504 Dram Type= 6, Freq= 0, CH_0, rank 0
2882 12:41:45.708533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2883 12:41:45.708619 ==
2884 12:41:45.708704 DQS Delay:
2885 12:41:45.711482 DQS0 = 0, DQS1 = 0
2886 12:41:45.711591 DQM Delay:
2887 12:41:45.714992 DQM0 = 114, DQM1 = 105
2888 12:41:45.715074 DQ Delay:
2889 12:41:45.718587 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =112
2890 12:41:45.721538 DQ4 =114, DQ5 =110, DQ6 =120, DQ7 =122
2891 12:41:45.725127 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =98
2892 12:41:45.728620 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2893 12:41:45.728702
2894 12:41:45.728767
2895 12:41:45.738232 [DQSOSCAuto] RK0, (LSB)MR18= 0xfeed, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 410 ps
2896 12:41:45.741633 CH0 RK0: MR19=303, MR18=FEED
2897 12:41:45.748729 CH0_RK0: MR19=0x303, MR18=0xFEED, DQSOSC=410, MR23=63, INC=39, DEC=26
2898 12:41:45.748837
2899 12:41:45.751477 ----->DramcWriteLeveling(PI) begin...
2900 12:41:45.751580 ==
2901 12:41:45.754877 Dram Type= 6, Freq= 0, CH_0, rank 1
2902 12:41:45.757891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2903 12:41:45.757974 ==
2904 12:41:45.761460 Write leveling (Byte 0): 30 => 30
2905 12:41:45.764816 Write leveling (Byte 1): 29 => 29
2906 12:41:45.768150 DramcWriteLeveling(PI) end<-----
2907 12:41:45.768237
2908 12:41:45.768305 ==
2909 12:41:45.771915 Dram Type= 6, Freq= 0, CH_0, rank 1
2910 12:41:45.774968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2911 12:41:45.775071 ==
2912 12:41:45.778415 [Gating] SW mode calibration
2913 12:41:45.784757 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2914 12:41:45.791632 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2915 12:41:45.794630 0 15 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2916 12:41:45.798350 0 15 4 | B1->B0 | 2c2c 3434 | 0 1 | (1 1) (1 1)
2917 12:41:45.804471 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2918 12:41:45.807754 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2919 12:41:45.811448 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2920 12:41:45.817776 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2921 12:41:45.821224 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)
2922 12:41:45.824599 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
2923 12:41:45.831342 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
2924 12:41:45.834474 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2925 12:41:45.837822 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2926 12:41:45.844672 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2927 12:41:45.848080 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2928 12:41:45.851256 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2929 12:41:45.857870 1 0 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2930 12:41:45.861232 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2931 12:41:45.864003 1 1 0 | B1->B0 | 3838 4545 | 0 0 | (0 0) (0 0)
2932 12:41:45.871156 1 1 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2933 12:41:45.874380 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2934 12:41:45.877519 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 12:41:45.883993 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 12:41:45.887534 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 12:41:45.890451 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2938 12:41:45.894169 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2939 12:41:45.900973 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2940 12:41:45.904059 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2941 12:41:45.907464 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 12:41:45.914316 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 12:41:45.917412 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 12:41:45.921049 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 12:41:45.927454 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 12:41:45.930863 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 12:41:45.933976 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 12:41:45.940967 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 12:41:45.944024 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 12:41:45.947794 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 12:41:45.954443 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 12:41:45.957281 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 12:41:45.960640 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2954 12:41:45.967223 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2955 12:41:45.970977 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2956 12:41:45.974264 Total UI for P1: 0, mck2ui 16
2957 12:41:45.977213 best dqsien dly found for B0: ( 1, 3, 26)
2958 12:41:45.981078 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2959 12:41:45.983747 Total UI for P1: 0, mck2ui 16
2960 12:41:45.987082 best dqsien dly found for B1: ( 1, 4, 0)
2961 12:41:45.990624 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2962 12:41:45.994068 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2963 12:41:45.994167
2964 12:41:45.997296 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2965 12:41:46.000784 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2966 12:41:46.004430 [Gating] SW calibration Done
2967 12:41:46.004514 ==
2968 12:41:46.007578 Dram Type= 6, Freq= 0, CH_0, rank 1
2969 12:41:46.014143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2970 12:41:46.014228 ==
2971 12:41:46.014295 RX Vref Scan: 0
2972 12:41:46.014355
2973 12:41:46.017487 RX Vref 0 -> 0, step: 1
2974 12:41:46.017571
2975 12:41:46.020691 RX Delay -40 -> 252, step: 8
2976 12:41:46.023845 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2977 12:41:46.027609 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2978 12:41:46.030730 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2979 12:41:46.034077 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2980 12:41:46.040760 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2981 12:41:46.044089 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2982 12:41:46.047770 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2983 12:41:46.050700 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2984 12:41:46.053684 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2985 12:41:46.060550 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2986 12:41:46.063932 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2987 12:41:46.067585 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2988 12:41:46.070726 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2989 12:41:46.073870 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2990 12:41:46.080542 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2991 12:41:46.083804 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2992 12:41:46.083921 ==
2993 12:41:46.087357 Dram Type= 6, Freq= 0, CH_0, rank 1
2994 12:41:46.090471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2995 12:41:46.090555 ==
2996 12:41:46.093915 DQS Delay:
2997 12:41:46.093998 DQS0 = 0, DQS1 = 0
2998 12:41:46.094064 DQM Delay:
2999 12:41:46.097233 DQM0 = 116, DQM1 = 106
3000 12:41:46.097329 DQ Delay:
3001 12:41:46.100786 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
3002 12:41:46.103849 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
3003 12:41:46.107336 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
3004 12:41:46.110666 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =111
3005 12:41:46.114107
3006 12:41:46.114185
3007 12:41:46.114251 ==
3008 12:41:46.117132 Dram Type= 6, Freq= 0, CH_0, rank 1
3009 12:41:46.120286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3010 12:41:46.120363 ==
3011 12:41:46.120430
3012 12:41:46.120492
3013 12:41:46.124136 TX Vref Scan disable
3014 12:41:46.124203 == TX Byte 0 ==
3015 12:41:46.130680 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3016 12:41:46.133999 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3017 12:41:46.134071 == TX Byte 1 ==
3018 12:41:46.140900 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3019 12:41:46.143771 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3020 12:41:46.143851 ==
3021 12:41:46.147130 Dram Type= 6, Freq= 0, CH_0, rank 1
3022 12:41:46.150594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3023 12:41:46.150671 ==
3024 12:41:46.162977 TX Vref=22, minBit 5, minWin=25, winSum=425
3025 12:41:46.166095 TX Vref=24, minBit 1, minWin=26, winSum=431
3026 12:41:46.169603 TX Vref=26, minBit 5, minWin=26, winSum=434
3027 12:41:46.173327 TX Vref=28, minBit 1, minWin=26, winSum=437
3028 12:41:46.176075 TX Vref=30, minBit 5, minWin=26, winSum=435
3029 12:41:46.179846 TX Vref=32, minBit 4, minWin=26, winSum=435
3030 12:41:46.186120 [TxChooseVref] Worse bit 1, Min win 26, Win sum 437, Final Vref 28
3031 12:41:46.186197
3032 12:41:46.189511 Final TX Range 1 Vref 28
3033 12:41:46.189586
3034 12:41:46.189649 ==
3035 12:41:46.193883 Dram Type= 6, Freq= 0, CH_0, rank 1
3036 12:41:46.196406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3037 12:41:46.196475 ==
3038 12:41:46.196537
3039 12:41:46.196599
3040 12:41:46.199870 TX Vref Scan disable
3041 12:41:46.203056 == TX Byte 0 ==
3042 12:41:46.206412 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3043 12:41:46.209976 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3044 12:41:46.212668 == TX Byte 1 ==
3045 12:41:46.216361 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3046 12:41:46.219458 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3047 12:41:46.222993
3048 12:41:46.223070 [DATLAT]
3049 12:41:46.223132 Freq=1200, CH0 RK1
3050 12:41:46.223196
3051 12:41:46.226294 DATLAT Default: 0xd
3052 12:41:46.226367 0, 0xFFFF, sum = 0
3053 12:41:46.229237 1, 0xFFFF, sum = 0
3054 12:41:46.229308 2, 0xFFFF, sum = 0
3055 12:41:46.232789 3, 0xFFFF, sum = 0
3056 12:41:46.232857 4, 0xFFFF, sum = 0
3057 12:41:46.236069 5, 0xFFFF, sum = 0
3058 12:41:46.239642 6, 0xFFFF, sum = 0
3059 12:41:46.239714 7, 0xFFFF, sum = 0
3060 12:41:46.242547 8, 0xFFFF, sum = 0
3061 12:41:46.242614 9, 0xFFFF, sum = 0
3062 12:41:46.246215 10, 0xFFFF, sum = 0
3063 12:41:46.246291 11, 0xFFFF, sum = 0
3064 12:41:46.249156 12, 0x0, sum = 1
3065 12:41:46.249228 13, 0x0, sum = 2
3066 12:41:46.252756 14, 0x0, sum = 3
3067 12:41:46.252827 15, 0x0, sum = 4
3068 12:41:46.252893 best_step = 13
3069 12:41:46.252951
3070 12:41:46.256314 ==
3071 12:41:46.259253 Dram Type= 6, Freq= 0, CH_0, rank 1
3072 12:41:46.262705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3073 12:41:46.262776 ==
3074 12:41:46.262838 RX Vref Scan: 0
3075 12:41:46.262900
3076 12:41:46.266126 RX Vref 0 -> 0, step: 1
3077 12:41:46.266193
3078 12:41:46.269627 RX Delay -21 -> 252, step: 4
3079 12:41:46.273081 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3080 12:41:46.279089 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3081 12:41:46.282662 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3082 12:41:46.285801 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3083 12:41:46.289039 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3084 12:41:46.292292 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3085 12:41:46.299072 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3086 12:41:46.302871 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3087 12:41:46.305559 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3088 12:41:46.309127 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3089 12:41:46.312433 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3090 12:41:46.318682 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3091 12:41:46.322601 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3092 12:41:46.325447 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3093 12:41:46.329235 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3094 12:41:46.332753 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3095 12:41:46.332832 ==
3096 12:41:46.335709 Dram Type= 6, Freq= 0, CH_0, rank 1
3097 12:41:46.342798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3098 12:41:46.342882 ==
3099 12:41:46.342948 DQS Delay:
3100 12:41:46.345818 DQS0 = 0, DQS1 = 0
3101 12:41:46.345901 DQM Delay:
3102 12:41:46.345966 DQM0 = 113, DQM1 = 105
3103 12:41:46.349104 DQ Delay:
3104 12:41:46.352082 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3105 12:41:46.356181 DQ4 =112, DQ5 =104, DQ6 =120, DQ7 =122
3106 12:41:46.359261 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3107 12:41:46.362649 DQ12 =110, DQ13 =112, DQ14 =118, DQ15 =114
3108 12:41:46.362733
3109 12:41:46.362798
3110 12:41:46.372453 [DQSOSCAuto] RK1, (LSB)MR18= 0xfff1, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 410 ps
3111 12:41:46.372537 CH0 RK1: MR19=303, MR18=FFF1
3112 12:41:46.379183 CH0_RK1: MR19=0x303, MR18=0xFFF1, DQSOSC=410, MR23=63, INC=39, DEC=26
3113 12:41:46.381942 [RxdqsGatingPostProcess] freq 1200
3114 12:41:46.388900 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3115 12:41:46.391950 best DQS0 dly(2T, 0.5T) = (0, 11)
3116 12:41:46.395762 best DQS1 dly(2T, 0.5T) = (0, 12)
3117 12:41:46.398884 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3118 12:41:46.401830 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3119 12:41:46.405435 best DQS0 dly(2T, 0.5T) = (0, 11)
3120 12:41:46.405519 best DQS1 dly(2T, 0.5T) = (0, 12)
3121 12:41:46.408713 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3122 12:41:46.412431 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3123 12:41:46.415195 Pre-setting of DQS Precalculation
3124 12:41:46.421802 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3125 12:41:46.421886 ==
3126 12:41:46.425034 Dram Type= 6, Freq= 0, CH_1, rank 0
3127 12:41:46.428780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3128 12:41:46.428854 ==
3129 12:41:46.435528 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3130 12:41:46.442027 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3131 12:41:46.448793 [CA 0] Center 38 (9~68) winsize 60
3132 12:41:46.452060 [CA 1] Center 38 (9~68) winsize 60
3133 12:41:46.455299 [CA 2] Center 35 (6~65) winsize 60
3134 12:41:46.458725 [CA 3] Center 34 (4~65) winsize 62
3135 12:41:46.462371 [CA 4] Center 34 (4~65) winsize 62
3136 12:41:46.465181 [CA 5] Center 34 (4~64) winsize 61
3137 12:41:46.465264
3138 12:41:46.468766 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3139 12:41:46.468849
3140 12:41:46.472473 [CATrainingPosCal] consider 1 rank data
3141 12:41:46.475499 u2DelayCellTimex100 = 270/100 ps
3142 12:41:46.478844 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3143 12:41:46.485175 CA1 delay=38 (9~68),Diff = 4 PI (19 cell)
3144 12:41:46.488877 CA2 delay=35 (6~65),Diff = 1 PI (4 cell)
3145 12:41:46.492216 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3146 12:41:46.495375 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3147 12:41:46.498509 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3148 12:41:46.498592
3149 12:41:46.501788 CA PerBit enable=1, Macro0, CA PI delay=34
3150 12:41:46.501871
3151 12:41:46.505433 [CBTSetCACLKResult] CA Dly = 34
3152 12:41:46.505516 CS Dly: 6 (0~37)
3153 12:41:46.508435 ==
3154 12:41:46.508519 Dram Type= 6, Freq= 0, CH_1, rank 1
3155 12:41:46.516136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3156 12:41:46.516220 ==
3157 12:41:46.518885 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3158 12:41:46.525425 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3159 12:41:46.534155 [CA 0] Center 38 (8~68) winsize 61
3160 12:41:46.537578 [CA 1] Center 38 (9~68) winsize 60
3161 12:41:46.541060 [CA 2] Center 35 (5~65) winsize 61
3162 12:41:46.544429 [CA 3] Center 34 (4~65) winsize 62
3163 12:41:46.547516 [CA 4] Center 34 (4~65) winsize 62
3164 12:41:46.551104 [CA 5] Center 33 (3~64) winsize 62
3165 12:41:46.551187
3166 12:41:46.554169 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3167 12:41:46.554249
3168 12:41:46.557936 [CATrainingPosCal] consider 2 rank data
3169 12:41:46.561034 u2DelayCellTimex100 = 270/100 ps
3170 12:41:46.564325 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3171 12:41:46.568318 CA1 delay=38 (9~68),Diff = 4 PI (19 cell)
3172 12:41:46.574411 CA2 delay=35 (6~65),Diff = 1 PI (4 cell)
3173 12:41:46.577727 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3174 12:41:46.580775 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3175 12:41:46.584166 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3176 12:41:46.584240
3177 12:41:46.587755 CA PerBit enable=1, Macro0, CA PI delay=34
3178 12:41:46.587831
3179 12:41:46.591091 [CBTSetCACLKResult] CA Dly = 34
3180 12:41:46.591173 CS Dly: 8 (0~41)
3181 12:41:46.591237
3182 12:41:46.594533 ----->DramcWriteLeveling(PI) begin...
3183 12:41:46.597820 ==
3184 12:41:46.600727 Dram Type= 6, Freq= 0, CH_1, rank 0
3185 12:41:46.604319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3186 12:41:46.604403 ==
3187 12:41:46.607520 Write leveling (Byte 0): 25 => 25
3188 12:41:46.610734 Write leveling (Byte 1): 28 => 28
3189 12:41:46.614167 DramcWriteLeveling(PI) end<-----
3190 12:41:46.614250
3191 12:41:46.614317 ==
3192 12:41:46.617862 Dram Type= 6, Freq= 0, CH_1, rank 0
3193 12:41:46.620788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3194 12:41:46.620872 ==
3195 12:41:46.624371 [Gating] SW mode calibration
3196 12:41:46.630877 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3197 12:41:46.634026 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3198 12:41:46.640644 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3199 12:41:46.644228 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3200 12:41:46.647402 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3201 12:41:46.653887 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3202 12:41:46.657262 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3203 12:41:46.660765 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3204 12:41:46.667785 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3205 12:41:46.671041 0 15 28 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 0)
3206 12:41:46.674432 1 0 0 | B1->B0 | 2525 2d2d | 0 1 | (1 0) (1 0)
3207 12:41:46.680538 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3208 12:41:46.684464 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3209 12:41:46.687695 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3210 12:41:46.693849 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3211 12:41:46.697279 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3212 12:41:46.701060 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3213 12:41:46.707545 1 0 28 | B1->B0 | 2727 2424 | 1 0 | (0 0) (0 0)
3214 12:41:46.710804 1 1 0 | B1->B0 | 4040 3737 | 0 0 | (1 1) (0 0)
3215 12:41:46.713774 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3216 12:41:46.720791 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 12:41:46.723844 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3218 12:41:46.727269 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 12:41:46.733910 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 12:41:46.737622 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3221 12:41:46.741304 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 12:41:46.744310 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3223 12:41:46.751024 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 12:41:46.754191 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 12:41:46.757336 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 12:41:46.764108 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 12:41:46.767533 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 12:41:46.770722 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 12:41:46.777043 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 12:41:46.780527 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 12:41:46.783705 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 12:41:46.790656 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 12:41:46.793884 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 12:41:46.797254 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 12:41:46.803819 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 12:41:46.807286 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 12:41:46.810627 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3238 12:41:46.817157 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3239 12:41:46.817248 Total UI for P1: 0, mck2ui 16
3240 12:41:46.824162 best dqsien dly found for B0: ( 1, 3, 28)
3241 12:41:46.824273 Total UI for P1: 0, mck2ui 16
3242 12:41:46.827130 best dqsien dly found for B1: ( 1, 3, 28)
3243 12:41:46.833835 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3244 12:41:46.837405 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3245 12:41:46.837491
3246 12:41:46.841004 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3247 12:41:46.843859 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3248 12:41:46.847159 [Gating] SW calibration Done
3249 12:41:46.847270 ==
3250 12:41:46.850813 Dram Type= 6, Freq= 0, CH_1, rank 0
3251 12:41:46.853805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3252 12:41:46.853944 ==
3253 12:41:46.857285 RX Vref Scan: 0
3254 12:41:46.857387
3255 12:41:46.857479 RX Vref 0 -> 0, step: 1
3256 12:41:46.857568
3257 12:41:46.860417 RX Delay -40 -> 252, step: 8
3258 12:41:46.864178 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3259 12:41:46.870712 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3260 12:41:46.873565 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3261 12:41:46.877050 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3262 12:41:46.880625 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3263 12:41:46.883558 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3264 12:41:46.886981 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3265 12:41:46.893836 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3266 12:41:46.897110 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3267 12:41:46.900595 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3268 12:41:46.903937 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3269 12:41:46.907227 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3270 12:41:46.913577 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3271 12:41:46.917089 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3272 12:41:46.920261 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3273 12:41:46.923655 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3274 12:41:46.923740 ==
3275 12:41:46.926970 Dram Type= 6, Freq= 0, CH_1, rank 0
3276 12:41:46.933935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3277 12:41:46.934074 ==
3278 12:41:46.934206 DQS Delay:
3279 12:41:46.934331 DQS0 = 0, DQS1 = 0
3280 12:41:46.937748 DQM Delay:
3281 12:41:46.937859 DQM0 = 116, DQM1 = 110
3282 12:41:46.940623 DQ Delay:
3283 12:41:46.944124 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3284 12:41:46.947342 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3285 12:41:46.950655 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3286 12:41:46.953761 DQ12 =123, DQ13 =115, DQ14 =111, DQ15 =115
3287 12:41:46.953848
3288 12:41:46.953925
3289 12:41:46.954020 ==
3290 12:41:46.957077 Dram Type= 6, Freq= 0, CH_1, rank 0
3291 12:41:46.960557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3292 12:41:46.960643 ==
3293 12:41:46.963525
3294 12:41:46.963609
3295 12:41:46.963675 TX Vref Scan disable
3296 12:41:46.966843 == TX Byte 0 ==
3297 12:41:46.970674 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3298 12:41:46.974021 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3299 12:41:46.977097 == TX Byte 1 ==
3300 12:41:46.980790 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3301 12:41:46.983620 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3302 12:41:46.983703 ==
3303 12:41:46.986947 Dram Type= 6, Freq= 0, CH_1, rank 0
3304 12:41:46.993852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3305 12:41:46.993939 ==
3306 12:41:47.004716 TX Vref=22, minBit 1, minWin=24, winSum=408
3307 12:41:47.008011 TX Vref=24, minBit 1, minWin=24, winSum=412
3308 12:41:47.011232 TX Vref=26, minBit 3, minWin=25, winSum=420
3309 12:41:47.014347 TX Vref=28, minBit 0, minWin=26, winSum=427
3310 12:41:47.017522 TX Vref=30, minBit 1, minWin=25, winSum=428
3311 12:41:47.021087 TX Vref=32, minBit 0, minWin=26, winSum=429
3312 12:41:47.027650 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 32
3313 12:41:47.027740
3314 12:41:47.031034 Final TX Range 1 Vref 32
3315 12:41:47.031119
3316 12:41:47.031187 ==
3317 12:41:47.034696 Dram Type= 6, Freq= 0, CH_1, rank 0
3318 12:41:47.038295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3319 12:41:47.038383 ==
3320 12:41:47.038452
3321 12:41:47.040887
3322 12:41:47.041000 TX Vref Scan disable
3323 12:41:47.044298 == TX Byte 0 ==
3324 12:41:47.048153 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3325 12:41:47.051148 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3326 12:41:47.054471 == TX Byte 1 ==
3327 12:41:47.058127 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3328 12:41:47.060956 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3329 12:41:47.061065
3330 12:41:47.064586 [DATLAT]
3331 12:41:47.064694 Freq=1200, CH1 RK0
3332 12:41:47.064789
3333 12:41:47.067981 DATLAT Default: 0xd
3334 12:41:47.068065 0, 0xFFFF, sum = 0
3335 12:41:47.071155 1, 0xFFFF, sum = 0
3336 12:41:47.071267 2, 0xFFFF, sum = 0
3337 12:41:47.074723 3, 0xFFFF, sum = 0
3338 12:41:47.074810 4, 0xFFFF, sum = 0
3339 12:41:47.078081 5, 0xFFFF, sum = 0
3340 12:41:47.078188 6, 0xFFFF, sum = 0
3341 12:41:47.081290 7, 0xFFFF, sum = 0
3342 12:41:47.081400 8, 0xFFFF, sum = 0
3343 12:41:47.084534 9, 0xFFFF, sum = 0
3344 12:41:47.087763 10, 0xFFFF, sum = 0
3345 12:41:47.087842 11, 0xFFFF, sum = 0
3346 12:41:47.091461 12, 0x0, sum = 1
3347 12:41:47.091539 13, 0x0, sum = 2
3348 12:41:47.091613 14, 0x0, sum = 3
3349 12:41:47.094653 15, 0x0, sum = 4
3350 12:41:47.094762 best_step = 13
3351 12:41:47.094857
3352 12:41:47.098048 ==
3353 12:41:47.098153 Dram Type= 6, Freq= 0, CH_1, rank 0
3354 12:41:47.104406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3355 12:41:47.104515 ==
3356 12:41:47.104587 RX Vref Scan: 1
3357 12:41:47.104652
3358 12:41:47.107564 Set Vref Range= 32 -> 127
3359 12:41:47.107640
3360 12:41:47.111453 RX Vref 32 -> 127, step: 1
3361 12:41:47.111531
3362 12:41:47.114509 RX Delay -13 -> 252, step: 4
3363 12:41:47.114620
3364 12:41:47.118154 Set Vref, RX VrefLevel [Byte0]: 32
3365 12:41:47.121056 [Byte1]: 32
3366 12:41:47.121157
3367 12:41:47.124320 Set Vref, RX VrefLevel [Byte0]: 33
3368 12:41:47.127566 [Byte1]: 33
3369 12:41:47.127653
3370 12:41:47.130956 Set Vref, RX VrefLevel [Byte0]: 34
3371 12:41:47.134344 [Byte1]: 34
3372 12:41:47.138195
3373 12:41:47.138295 Set Vref, RX VrefLevel [Byte0]: 35
3374 12:41:47.141720 [Byte1]: 35
3375 12:41:47.146480
3376 12:41:47.146557 Set Vref, RX VrefLevel [Byte0]: 36
3377 12:41:47.149839 [Byte1]: 36
3378 12:41:47.153871
3379 12:41:47.153946 Set Vref, RX VrefLevel [Byte0]: 37
3380 12:41:47.157578 [Byte1]: 37
3381 12:41:47.162050
3382 12:41:47.162154 Set Vref, RX VrefLevel [Byte0]: 38
3383 12:41:47.165143 [Byte1]: 38
3384 12:41:47.169961
3385 12:41:47.170070 Set Vref, RX VrefLevel [Byte0]: 39
3386 12:41:47.173357 [Byte1]: 39
3387 12:41:47.177770
3388 12:41:47.177871 Set Vref, RX VrefLevel [Byte0]: 40
3389 12:41:47.180877 [Byte1]: 40
3390 12:41:47.185820
3391 12:41:47.185918 Set Vref, RX VrefLevel [Byte0]: 41
3392 12:41:47.188714 [Byte1]: 41
3393 12:41:47.193791
3394 12:41:47.193890 Set Vref, RX VrefLevel [Byte0]: 42
3395 12:41:47.196997 [Byte1]: 42
3396 12:41:47.201701
3397 12:41:47.201808 Set Vref, RX VrefLevel [Byte0]: 43
3398 12:41:47.205162 [Byte1]: 43
3399 12:41:47.209160
3400 12:41:47.209234 Set Vref, RX VrefLevel [Byte0]: 44
3401 12:41:47.212424 [Byte1]: 44
3402 12:41:47.217488
3403 12:41:47.217567 Set Vref, RX VrefLevel [Byte0]: 45
3404 12:41:47.220841 [Byte1]: 45
3405 12:41:47.225380
3406 12:41:47.225481 Set Vref, RX VrefLevel [Byte0]: 46
3407 12:41:47.228510 [Byte1]: 46
3408 12:41:47.232895
3409 12:41:47.232981 Set Vref, RX VrefLevel [Byte0]: 47
3410 12:41:47.236967 [Byte1]: 47
3411 12:41:47.241214
3412 12:41:47.241288 Set Vref, RX VrefLevel [Byte0]: 48
3413 12:41:47.244633 [Byte1]: 48
3414 12:41:47.248721
3415 12:41:47.248806 Set Vref, RX VrefLevel [Byte0]: 49
3416 12:41:47.251986 [Byte1]: 49
3417 12:41:47.256432
3418 12:41:47.256531 Set Vref, RX VrefLevel [Byte0]: 50
3419 12:41:47.260110 [Byte1]: 50
3420 12:41:47.264452
3421 12:41:47.264528 Set Vref, RX VrefLevel [Byte0]: 51
3422 12:41:47.267761 [Byte1]: 51
3423 12:41:47.272760
3424 12:41:47.272835 Set Vref, RX VrefLevel [Byte0]: 52
3425 12:41:47.275580 [Byte1]: 52
3426 12:41:47.280236
3427 12:41:47.280313 Set Vref, RX VrefLevel [Byte0]: 53
3428 12:41:47.283753 [Byte1]: 53
3429 12:41:47.288056
3430 12:41:47.288130 Set Vref, RX VrefLevel [Byte0]: 54
3431 12:41:47.291540 [Byte1]: 54
3432 12:41:47.296375
3433 12:41:47.296448 Set Vref, RX VrefLevel [Byte0]: 55
3434 12:41:47.299715 [Byte1]: 55
3435 12:41:47.303704
3436 12:41:47.303778 Set Vref, RX VrefLevel [Byte0]: 56
3437 12:41:47.307130 [Byte1]: 56
3438 12:41:47.311641
3439 12:41:47.311719 Set Vref, RX VrefLevel [Byte0]: 57
3440 12:41:47.315123 [Byte1]: 57
3441 12:41:47.319664
3442 12:41:47.319767 Set Vref, RX VrefLevel [Byte0]: 58
3443 12:41:47.322958 [Byte1]: 58
3444 12:41:47.327607
3445 12:41:47.327685 Set Vref, RX VrefLevel [Byte0]: 59
3446 12:41:47.330840 [Byte1]: 59
3447 12:41:47.335332
3448 12:41:47.335450 Set Vref, RX VrefLevel [Byte0]: 60
3449 12:41:47.338820 [Byte1]: 60
3450 12:41:47.343232
3451 12:41:47.343339 Set Vref, RX VrefLevel [Byte0]: 61
3452 12:41:47.346991 [Byte1]: 61
3453 12:41:47.351174
3454 12:41:47.351247 Set Vref, RX VrefLevel [Byte0]: 62
3455 12:41:47.354623 [Byte1]: 62
3456 12:41:47.358784
3457 12:41:47.358882 Set Vref, RX VrefLevel [Byte0]: 63
3458 12:41:47.362425 [Byte1]: 63
3459 12:41:47.367213
3460 12:41:47.367359 Set Vref, RX VrefLevel [Byte0]: 64
3461 12:41:47.370279 [Byte1]: 64
3462 12:41:47.374885
3463 12:41:47.374988 Set Vref, RX VrefLevel [Byte0]: 65
3464 12:41:47.378268 [Byte1]: 65
3465 12:41:47.382588
3466 12:41:47.382665 Set Vref, RX VrefLevel [Byte0]: 66
3467 12:41:47.386222 [Byte1]: 66
3468 12:41:47.390547
3469 12:41:47.390621 Set Vref, RX VrefLevel [Byte0]: 67
3470 12:41:47.394047 [Byte1]: 67
3471 12:41:47.398827
3472 12:41:47.398926 Set Vref, RX VrefLevel [Byte0]: 68
3473 12:41:47.401685 [Byte1]: 68
3474 12:41:47.406318
3475 12:41:47.406393 Set Vref, RX VrefLevel [Byte0]: 69
3476 12:41:47.409512 [Byte1]: 69
3477 12:41:47.414124
3478 12:41:47.414234 Set Vref, RX VrefLevel [Byte0]: 70
3479 12:41:47.417372 [Byte1]: 70
3480 12:41:47.422054
3481 12:41:47.422139 Final RX Vref Byte 0 = 52 to rank0
3482 12:41:47.425669 Final RX Vref Byte 1 = 51 to rank0
3483 12:41:47.429118 Final RX Vref Byte 0 = 52 to rank1
3484 12:41:47.431927 Final RX Vref Byte 1 = 51 to rank1==
3485 12:41:47.435223 Dram Type= 6, Freq= 0, CH_1, rank 0
3486 12:41:47.442147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3487 12:41:47.442244 ==
3488 12:41:47.442319 DQS Delay:
3489 12:41:47.442386 DQS0 = 0, DQS1 = 0
3490 12:41:47.445385 DQM Delay:
3491 12:41:47.445482 DQM0 = 115, DQM1 = 108
3492 12:41:47.448602 DQ Delay:
3493 12:41:47.452172 DQ0 =116, DQ1 =108, DQ2 =106, DQ3 =114
3494 12:41:47.455705 DQ4 =116, DQ5 =124, DQ6 =128, DQ7 =112
3495 12:41:47.458503 DQ8 =96, DQ9 =96, DQ10 =110, DQ11 =104
3496 12:41:47.462165 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =114
3497 12:41:47.462330
3498 12:41:47.462470
3499 12:41:47.468570 [DQSOSCAuto] RK0, (LSB)MR18= 0xffe3, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
3500 12:41:47.472007 CH1 RK0: MR19=303, MR18=FFE3
3501 12:41:47.478958 CH1_RK0: MR19=0x303, MR18=0xFFE3, DQSOSC=410, MR23=63, INC=39, DEC=26
3502 12:41:47.479043
3503 12:41:47.482074 ----->DramcWriteLeveling(PI) begin...
3504 12:41:47.482160 ==
3505 12:41:47.485313 Dram Type= 6, Freq= 0, CH_1, rank 1
3506 12:41:47.488668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3507 12:41:47.492067 ==
3508 12:41:47.492152 Write leveling (Byte 0): 26 => 26
3509 12:41:47.495631 Write leveling (Byte 1): 28 => 28
3510 12:41:47.498507 DramcWriteLeveling(PI) end<-----
3511 12:41:47.498594
3512 12:41:47.498661 ==
3513 12:41:47.502339 Dram Type= 6, Freq= 0, CH_1, rank 1
3514 12:41:47.508849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3515 12:41:47.508933 ==
3516 12:41:47.509001 [Gating] SW mode calibration
3517 12:41:47.518751 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3518 12:41:47.522190 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3519 12:41:47.528372 0 15 0 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
3520 12:41:47.532378 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3521 12:41:47.535671 0 15 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3522 12:41:47.538579 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3523 12:41:47.544832 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3524 12:41:47.548487 0 15 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3525 12:41:47.552265 0 15 24 | B1->B0 | 3333 2d2d | 0 0 | (0 0) (0 1)
3526 12:41:47.558518 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3527 12:41:47.562137 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3528 12:41:47.565293 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3529 12:41:47.571799 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3530 12:41:47.575574 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3531 12:41:47.578895 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3532 12:41:47.585372 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3533 12:41:47.588812 1 0 24 | B1->B0 | 2727 4040 | 0 0 | (0 0) (0 0)
3534 12:41:47.591846 1 0 28 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
3535 12:41:47.598611 1 1 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3536 12:41:47.602340 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3537 12:41:47.605483 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3538 12:41:47.612337 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3539 12:41:47.615608 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3540 12:41:47.618572 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3541 12:41:47.625392 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3542 12:41:47.628515 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3543 12:41:47.631744 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 12:41:47.638959 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 12:41:47.641863 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 12:41:47.645690 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 12:41:47.651779 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 12:41:47.655144 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 12:41:47.659024 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 12:41:47.662036 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 12:41:47.668618 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 12:41:47.671996 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 12:41:47.675054 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 12:41:47.681739 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 12:41:47.685084 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 12:41:47.688337 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 12:41:47.694857 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3558 12:41:47.698262 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3559 12:41:47.701585 Total UI for P1: 0, mck2ui 16
3560 12:41:47.705265 best dqsien dly found for B0: ( 1, 3, 24)
3561 12:41:47.708207 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3562 12:41:47.711586 Total UI for P1: 0, mck2ui 16
3563 12:41:47.715038 best dqsien dly found for B1: ( 1, 3, 28)
3564 12:41:47.718497 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3565 12:41:47.721542 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3566 12:41:47.721978
3567 12:41:47.728326 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3568 12:41:47.731675 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3569 12:41:47.734849 [Gating] SW calibration Done
3570 12:41:47.735282 ==
3571 12:41:47.738183 Dram Type= 6, Freq= 0, CH_1, rank 1
3572 12:41:47.741747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3573 12:41:47.742185 ==
3574 12:41:47.742530 RX Vref Scan: 0
3575 12:41:47.742850
3576 12:41:47.744579 RX Vref 0 -> 0, step: 1
3577 12:41:47.745012
3578 12:41:47.748259 RX Delay -40 -> 252, step: 8
3579 12:41:47.751373 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
3580 12:41:47.754687 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3581 12:41:47.761173 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3582 12:41:47.764911 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3583 12:41:47.767921 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3584 12:41:47.771327 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3585 12:41:47.774831 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3586 12:41:47.781131 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3587 12:41:47.784840 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
3588 12:41:47.787902 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3589 12:41:47.791191 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3590 12:41:47.794933 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3591 12:41:47.801339 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3592 12:41:47.804200 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3593 12:41:47.807708 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3594 12:41:47.810996 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3595 12:41:47.811573 ==
3596 12:41:47.814407 Dram Type= 6, Freq= 0, CH_1, rank 1
3597 12:41:47.821018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3598 12:41:47.821528 ==
3599 12:41:47.821937 DQS Delay:
3600 12:41:47.824385 DQS0 = 0, DQS1 = 0
3601 12:41:47.824820 DQM Delay:
3602 12:41:47.825167 DQM0 = 113, DQM1 = 110
3603 12:41:47.827710 DQ Delay:
3604 12:41:47.831677 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =111
3605 12:41:47.834552 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =111
3606 12:41:47.837490 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3607 12:41:47.841101 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3608 12:41:47.841560
3609 12:41:47.841925
3610 12:41:47.842273 ==
3611 12:41:47.844278 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 12:41:47.847756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 12:41:47.848296 ==
3614 12:41:47.850932
3615 12:41:47.851396
3616 12:41:47.851785 TX Vref Scan disable
3617 12:41:47.854275 == TX Byte 0 ==
3618 12:41:47.857767 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3619 12:41:47.860842 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3620 12:41:47.864100 == TX Byte 1 ==
3621 12:41:47.867779 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3622 12:41:47.870937 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3623 12:41:47.871396 ==
3624 12:41:47.874516 Dram Type= 6, Freq= 0, CH_1, rank 1
3625 12:41:47.880679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3626 12:41:47.881117 ==
3627 12:41:47.891601 TX Vref=22, minBit 0, minWin=25, winSum=414
3628 12:41:47.894647 TX Vref=24, minBit 0, minWin=25, winSum=422
3629 12:41:47.898085 TX Vref=26, minBit 0, minWin=25, winSum=424
3630 12:41:47.901837 TX Vref=28, minBit 3, minWin=25, winSum=429
3631 12:41:47.904871 TX Vref=30, minBit 4, minWin=26, winSum=434
3632 12:41:47.908321 TX Vref=32, minBit 3, minWin=25, winSum=426
3633 12:41:47.914776 [TxChooseVref] Worse bit 4, Min win 26, Win sum 434, Final Vref 30
3634 12:41:47.915239
3635 12:41:47.917876 Final TX Range 1 Vref 30
3636 12:41:47.918385
3637 12:41:47.918753 ==
3638 12:41:47.921351 Dram Type= 6, Freq= 0, CH_1, rank 1
3639 12:41:47.924878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3640 12:41:47.925335 ==
3641 12:41:47.927864
3642 12:41:47.928349
3643 12:41:47.928690 TX Vref Scan disable
3644 12:41:47.931549 == TX Byte 0 ==
3645 12:41:47.934553 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3646 12:41:47.938477 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3647 12:41:47.941850 == TX Byte 1 ==
3648 12:41:47.944752 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3649 12:41:47.948188 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3650 12:41:47.948615
3651 12:41:47.951513 [DATLAT]
3652 12:41:47.951954 Freq=1200, CH1 RK1
3653 12:41:47.952389
3654 12:41:47.954779 DATLAT Default: 0xd
3655 12:41:47.955218 0, 0xFFFF, sum = 0
3656 12:41:47.958043 1, 0xFFFF, sum = 0
3657 12:41:47.958489 2, 0xFFFF, sum = 0
3658 12:41:47.961638 3, 0xFFFF, sum = 0
3659 12:41:47.962224 4, 0xFFFF, sum = 0
3660 12:41:47.964995 5, 0xFFFF, sum = 0
3661 12:41:47.965548 6, 0xFFFF, sum = 0
3662 12:41:47.967978 7, 0xFFFF, sum = 0
3663 12:41:47.971462 8, 0xFFFF, sum = 0
3664 12:41:47.971931 9, 0xFFFF, sum = 0
3665 12:41:47.974551 10, 0xFFFF, sum = 0
3666 12:41:47.975208 11, 0xFFFF, sum = 0
3667 12:41:47.978051 12, 0x0, sum = 1
3668 12:41:47.978491 13, 0x0, sum = 2
3669 12:41:47.981470 14, 0x0, sum = 3
3670 12:41:47.982036 15, 0x0, sum = 4
3671 12:41:47.982440 best_step = 13
3672 12:41:47.982828
3673 12:41:47.984975 ==
3674 12:41:47.988631 Dram Type= 6, Freq= 0, CH_1, rank 1
3675 12:41:47.991289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3676 12:41:47.991822 ==
3677 12:41:47.992173 RX Vref Scan: 0
3678 12:41:47.992552
3679 12:41:47.994896 RX Vref 0 -> 0, step: 1
3680 12:41:47.995333
3681 12:41:47.998486 RX Delay -21 -> 252, step: 4
3682 12:41:48.001209 iDelay=195, Bit 0, Center 112 (43 ~ 182) 140
3683 12:41:48.007574 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3684 12:41:48.011674 iDelay=195, Bit 2, Center 104 (39 ~ 170) 132
3685 12:41:48.014929 iDelay=195, Bit 3, Center 110 (43 ~ 178) 136
3686 12:41:48.018153 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3687 12:41:48.021348 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3688 12:41:48.027637 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3689 12:41:48.031511 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3690 12:41:48.034734 iDelay=195, Bit 8, Center 98 (31 ~ 166) 136
3691 12:41:48.038069 iDelay=195, Bit 9, Center 98 (35 ~ 162) 128
3692 12:41:48.041412 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3693 12:41:48.047902 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3694 12:41:48.051298 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3695 12:41:48.054850 iDelay=195, Bit 13, Center 120 (55 ~ 186) 132
3696 12:41:48.057758 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3697 12:41:48.060825 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3698 12:41:48.064382 ==
3699 12:41:48.064869 Dram Type= 6, Freq= 0, CH_1, rank 1
3700 12:41:48.070850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3701 12:41:48.071304 ==
3702 12:41:48.071730 DQS Delay:
3703 12:41:48.074154 DQS0 = 0, DQS1 = 0
3704 12:41:48.074593 DQM Delay:
3705 12:41:48.077223 DQM0 = 113, DQM1 = 109
3706 12:41:48.077727 DQ Delay:
3707 12:41:48.081172 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =110
3708 12:41:48.084137 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3709 12:41:48.087415 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =102
3710 12:41:48.090568 DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =116
3711 12:41:48.091089
3712 12:41:48.091580
3713 12:41:48.100789 [DQSOSCAuto] RK1, (LSB)MR18= 0xf4fc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 415 ps
3714 12:41:48.101223 CH1 RK1: MR19=303, MR18=F4FC
3715 12:41:48.107460 CH1_RK1: MR19=0x303, MR18=0xF4FC, DQSOSC=411, MR23=63, INC=38, DEC=25
3716 12:41:48.110878 [RxdqsGatingPostProcess] freq 1200
3717 12:41:48.117803 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3718 12:41:48.120736 best DQS0 dly(2T, 0.5T) = (0, 11)
3719 12:41:48.123782 best DQS1 dly(2T, 0.5T) = (0, 11)
3720 12:41:48.126918 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3721 12:41:48.130408 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3722 12:41:48.133630 best DQS0 dly(2T, 0.5T) = (0, 11)
3723 12:41:48.136977 best DQS1 dly(2T, 0.5T) = (0, 11)
3724 12:41:48.140556 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3725 12:41:48.143956 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3726 12:41:48.144388 Pre-setting of DQS Precalculation
3727 12:41:48.150198 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3728 12:41:48.156671 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3729 12:41:48.163420 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3730 12:41:48.163899
3731 12:41:48.164278
3732 12:41:48.167121 [Calibration Summary] 2400 Mbps
3733 12:41:48.169952 CH 0, Rank 0
3734 12:41:48.170354 SW Impedance : PASS
3735 12:41:48.173573 DUTY Scan : NO K
3736 12:41:48.177074 ZQ Calibration : PASS
3737 12:41:48.177504 Jitter Meter : NO K
3738 12:41:48.180279 CBT Training : PASS
3739 12:41:48.183203 Write leveling : PASS
3740 12:41:48.183737 RX DQS gating : PASS
3741 12:41:48.186549 RX DQ/DQS(RDDQC) : PASS
3742 12:41:48.189877 TX DQ/DQS : PASS
3743 12:41:48.190336 RX DATLAT : PASS
3744 12:41:48.193235 RX DQ/DQS(Engine): PASS
3745 12:41:48.196375 TX OE : NO K
3746 12:41:48.196829 All Pass.
3747 12:41:48.197171
3748 12:41:48.197512 CH 0, Rank 1
3749 12:41:48.199956 SW Impedance : PASS
3750 12:41:48.203222 DUTY Scan : NO K
3751 12:41:48.203867 ZQ Calibration : PASS
3752 12:41:48.206436 Jitter Meter : NO K
3753 12:41:48.206949 CBT Training : PASS
3754 12:41:48.209756 Write leveling : PASS
3755 12:41:48.212925 RX DQS gating : PASS
3756 12:41:48.213382 RX DQ/DQS(RDDQC) : PASS
3757 12:41:48.216276 TX DQ/DQS : PASS
3758 12:41:48.219665 RX DATLAT : PASS
3759 12:41:48.220156 RX DQ/DQS(Engine): PASS
3760 12:41:48.223434 TX OE : NO K
3761 12:41:48.223946 All Pass.
3762 12:41:48.224341
3763 12:41:48.226900 CH 1, Rank 0
3764 12:41:48.227324 SW Impedance : PASS
3765 12:41:48.229922 DUTY Scan : NO K
3766 12:41:48.233076 ZQ Calibration : PASS
3767 12:41:48.233563 Jitter Meter : NO K
3768 12:41:48.236599 CBT Training : PASS
3769 12:41:48.239952 Write leveling : PASS
3770 12:41:48.240415 RX DQS gating : PASS
3771 12:41:48.243533 RX DQ/DQS(RDDQC) : PASS
3772 12:41:48.246153 TX DQ/DQS : PASS
3773 12:41:48.246618 RX DATLAT : PASS
3774 12:41:48.250054 RX DQ/DQS(Engine): PASS
3775 12:41:48.250588 TX OE : NO K
3776 12:41:48.253497 All Pass.
3777 12:41:48.253921
3778 12:41:48.254336 CH 1, Rank 1
3779 12:41:48.256206 SW Impedance : PASS
3780 12:41:48.256661 DUTY Scan : NO K
3781 12:41:48.259532 ZQ Calibration : PASS
3782 12:41:48.262959 Jitter Meter : NO K
3783 12:41:48.263432 CBT Training : PASS
3784 12:41:48.266601 Write leveling : PASS
3785 12:41:48.269380 RX DQS gating : PASS
3786 12:41:48.269853 RX DQ/DQS(RDDQC) : PASS
3787 12:41:48.272599 TX DQ/DQS : PASS
3788 12:41:48.276060 RX DATLAT : PASS
3789 12:41:48.276486 RX DQ/DQS(Engine): PASS
3790 12:41:48.279505 TX OE : NO K
3791 12:41:48.279964 All Pass.
3792 12:41:48.280345
3793 12:41:48.283187 DramC Write-DBI off
3794 12:41:48.285780 PER_BANK_REFRESH: Hybrid Mode
3795 12:41:48.286203 TX_TRACKING: ON
3796 12:41:48.296332 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3797 12:41:48.299409 [FAST_K] Save calibration result to emmc
3798 12:41:48.302596 dramc_set_vcore_voltage set vcore to 650000
3799 12:41:48.305604 Read voltage for 600, 5
3800 12:41:48.306038 Vio18 = 0
3801 12:41:48.306466 Vcore = 650000
3802 12:41:48.308949 Vdram = 0
3803 12:41:48.309381 Vddq = 0
3804 12:41:48.309803 Vmddr = 0
3805 12:41:48.316010 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3806 12:41:48.319240 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3807 12:41:48.322572 MEM_TYPE=3, freq_sel=19
3808 12:41:48.325498 sv_algorithm_assistance_LP4_1600
3809 12:41:48.329064 ============ PULL DRAM RESETB DOWN ============
3810 12:41:48.332496 ========== PULL DRAM RESETB DOWN end =========
3811 12:41:48.339140 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3812 12:41:48.342586 ===================================
3813 12:41:48.345467 LPDDR4 DRAM CONFIGURATION
3814 12:41:48.349448 ===================================
3815 12:41:48.349888 EX_ROW_EN[0] = 0x0
3816 12:41:48.352450 EX_ROW_EN[1] = 0x0
3817 12:41:48.352890 LP4Y_EN = 0x0
3818 12:41:48.355857 WORK_FSP = 0x0
3819 12:41:48.356393 WL = 0x2
3820 12:41:48.359258 RL = 0x2
3821 12:41:48.359908 BL = 0x2
3822 12:41:48.362658 RPST = 0x0
3823 12:41:48.363175 RD_PRE = 0x0
3824 12:41:48.365807 WR_PRE = 0x1
3825 12:41:48.366344 WR_PST = 0x0
3826 12:41:48.369131 DBI_WR = 0x0
3827 12:41:48.369564 DBI_RD = 0x0
3828 12:41:48.372411 OTF = 0x1
3829 12:41:48.375590 ===================================
3830 12:41:48.379249 ===================================
3831 12:41:48.379741 ANA top config
3832 12:41:48.382316 ===================================
3833 12:41:48.385673 DLL_ASYNC_EN = 0
3834 12:41:48.388691 ALL_SLAVE_EN = 1
3835 12:41:48.392365 NEW_RANK_MODE = 1
3836 12:41:48.395816 DLL_IDLE_MODE = 1
3837 12:41:48.396249 LP45_APHY_COMB_EN = 1
3838 12:41:48.398475 TX_ODT_DIS = 1
3839 12:41:48.401792 NEW_8X_MODE = 1
3840 12:41:48.405094 ===================================
3841 12:41:48.408826 ===================================
3842 12:41:48.412258 data_rate = 1200
3843 12:41:48.415440 CKR = 1
3844 12:41:48.415875 DQ_P2S_RATIO = 8
3845 12:41:48.418786 ===================================
3846 12:41:48.422097 CA_P2S_RATIO = 8
3847 12:41:48.425079 DQ_CA_OPEN = 0
3848 12:41:48.428730 DQ_SEMI_OPEN = 0
3849 12:41:48.431568 CA_SEMI_OPEN = 0
3850 12:41:48.435021 CA_FULL_RATE = 0
3851 12:41:48.435583 DQ_CKDIV4_EN = 1
3852 12:41:48.438290 CA_CKDIV4_EN = 1
3853 12:41:48.442153 CA_PREDIV_EN = 0
3854 12:41:48.445424 PH8_DLY = 0
3855 12:41:48.448451 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3856 12:41:48.451737 DQ_AAMCK_DIV = 4
3857 12:41:48.452169 CA_AAMCK_DIV = 4
3858 12:41:48.455407 CA_ADMCK_DIV = 4
3859 12:41:48.458653 DQ_TRACK_CA_EN = 0
3860 12:41:48.461898 CA_PICK = 600
3861 12:41:48.465482 CA_MCKIO = 600
3862 12:41:48.468946 MCKIO_SEMI = 0
3863 12:41:48.471696 PLL_FREQ = 2288
3864 12:41:48.472130 DQ_UI_PI_RATIO = 32
3865 12:41:48.475448 CA_UI_PI_RATIO = 0
3866 12:41:48.478432 ===================================
3867 12:41:48.481490 ===================================
3868 12:41:48.485096 memory_type:LPDDR4
3869 12:41:48.488440 GP_NUM : 10
3870 12:41:48.488899 SRAM_EN : 1
3871 12:41:48.491701 MD32_EN : 0
3872 12:41:48.495012 ===================================
3873 12:41:48.495516 [ANA_INIT] >>>>>>>>>>>>>>
3874 12:41:48.498240 <<<<<< [CONFIGURE PHASE]: ANA_TX
3875 12:41:48.501848 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3876 12:41:48.504695 ===================================
3877 12:41:48.508515 data_rate = 1200,PCW = 0X5800
3878 12:41:48.511920 ===================================
3879 12:41:48.515444 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3880 12:41:48.521847 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3881 12:41:48.528533 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3882 12:41:48.531578 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3883 12:41:48.534673 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3884 12:41:48.537729 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3885 12:41:48.541568 [ANA_INIT] flow start
3886 12:41:48.542002 [ANA_INIT] PLL >>>>>>>>
3887 12:41:48.544312 [ANA_INIT] PLL <<<<<<<<
3888 12:41:48.547721 [ANA_INIT] MIDPI >>>>>>>>
3889 12:41:48.548153 [ANA_INIT] MIDPI <<<<<<<<
3890 12:41:48.550962 [ANA_INIT] DLL >>>>>>>>
3891 12:41:48.554214 [ANA_INIT] flow end
3892 12:41:48.557747 ============ LP4 DIFF to SE enter ============
3893 12:41:48.560824 ============ LP4 DIFF to SE exit ============
3894 12:41:48.564282 [ANA_INIT] <<<<<<<<<<<<<
3895 12:41:48.567865 [Flow] Enable top DCM control >>>>>
3896 12:41:48.571315 [Flow] Enable top DCM control <<<<<
3897 12:41:48.574277 Enable DLL master slave shuffle
3898 12:41:48.577821 ==============================================================
3899 12:41:48.580730 Gating Mode config
3900 12:41:48.587595 ==============================================================
3901 12:41:48.588036 Config description:
3902 12:41:48.597561 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3903 12:41:48.604085 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3904 12:41:48.611477 SELPH_MODE 0: By rank 1: By Phase
3905 12:41:48.614081 ==============================================================
3906 12:41:48.617308 GAT_TRACK_EN = 1
3907 12:41:48.620645 RX_GATING_MODE = 2
3908 12:41:48.624274 RX_GATING_TRACK_MODE = 2
3909 12:41:48.627666 SELPH_MODE = 1
3910 12:41:48.630812 PICG_EARLY_EN = 1
3911 12:41:48.633873 VALID_LAT_VALUE = 1
3912 12:41:48.637857 ==============================================================
3913 12:41:48.640652 Enter into Gating configuration >>>>
3914 12:41:48.644149 Exit from Gating configuration <<<<
3915 12:41:48.647016 Enter into DVFS_PRE_config >>>>>
3916 12:41:48.660631 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3917 12:41:48.664171 Exit from DVFS_PRE_config <<<<<
3918 12:41:48.667451 Enter into PICG configuration >>>>
3919 12:41:48.667890 Exit from PICG configuration <<<<
3920 12:41:48.670425 [RX_INPUT] configuration >>>>>
3921 12:41:48.674115 [RX_INPUT] configuration <<<<<
3922 12:41:48.680545 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3923 12:41:48.683471 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3924 12:41:48.690549 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3925 12:41:48.696741 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3926 12:41:48.703909 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3927 12:41:48.710021 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3928 12:41:48.713126 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3929 12:41:48.716849 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3930 12:41:48.722926 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3931 12:41:48.726462 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3932 12:41:48.729734 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3933 12:41:48.733020 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3934 12:41:48.736418 ===================================
3935 12:41:48.739613 LPDDR4 DRAM CONFIGURATION
3936 12:41:48.742882 ===================================
3937 12:41:48.746193 EX_ROW_EN[0] = 0x0
3938 12:41:48.746626 EX_ROW_EN[1] = 0x0
3939 12:41:48.750117 LP4Y_EN = 0x0
3940 12:41:48.750554 WORK_FSP = 0x0
3941 12:41:48.752945 WL = 0x2
3942 12:41:48.753380 RL = 0x2
3943 12:41:48.756828 BL = 0x2
3944 12:41:48.757262 RPST = 0x0
3945 12:41:48.759986 RD_PRE = 0x0
3946 12:41:48.760522 WR_PRE = 0x1
3947 12:41:48.763249 WR_PST = 0x0
3948 12:41:48.763713 DBI_WR = 0x0
3949 12:41:48.766781 DBI_RD = 0x0
3950 12:41:48.769726 OTF = 0x1
3951 12:41:48.773222 ===================================
3952 12:41:48.776149 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3953 12:41:48.779465 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3954 12:41:48.782862 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3955 12:41:48.786534 ===================================
3956 12:41:48.790190 LPDDR4 DRAM CONFIGURATION
3957 12:41:48.792982 ===================================
3958 12:41:48.795975 EX_ROW_EN[0] = 0x10
3959 12:41:48.796521 EX_ROW_EN[1] = 0x0
3960 12:41:48.799298 LP4Y_EN = 0x0
3961 12:41:48.799785 WORK_FSP = 0x0
3962 12:41:48.802957 WL = 0x2
3963 12:41:48.803428 RL = 0x2
3964 12:41:48.806184 BL = 0x2
3965 12:41:48.806653 RPST = 0x0
3966 12:41:48.809512 RD_PRE = 0x0
3967 12:41:48.809947 WR_PRE = 0x1
3968 12:41:48.812933 WR_PST = 0x0
3969 12:41:48.813387 DBI_WR = 0x0
3970 12:41:48.815796 DBI_RD = 0x0
3971 12:41:48.816229 OTF = 0x1
3972 12:41:48.819397 ===================================
3973 12:41:48.825873 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3974 12:41:48.830891 nWR fixed to 30
3975 12:41:48.834410 [ModeRegInit_LP4] CH0 RK0
3976 12:41:48.834942 [ModeRegInit_LP4] CH0 RK1
3977 12:41:48.837813 [ModeRegInit_LP4] CH1 RK0
3978 12:41:48.840929 [ModeRegInit_LP4] CH1 RK1
3979 12:41:48.841367 match AC timing 17
3980 12:41:48.847678 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3981 12:41:48.850672 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3982 12:41:48.854215 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3983 12:41:48.861290 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3984 12:41:48.864146 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3985 12:41:48.864582 ==
3986 12:41:48.867341 Dram Type= 6, Freq= 0, CH_0, rank 0
3987 12:41:48.870980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3988 12:41:48.871452 ==
3989 12:41:48.877948 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3990 12:41:48.883818 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3991 12:41:48.887203 [CA 0] Center 36 (6~66) winsize 61
3992 12:41:48.890444 [CA 1] Center 35 (5~66) winsize 62
3993 12:41:48.894352 [CA 2] Center 34 (4~65) winsize 62
3994 12:41:48.897344 [CA 3] Center 34 (4~65) winsize 62
3995 12:41:48.900405 [CA 4] Center 33 (3~64) winsize 62
3996 12:41:48.903693 [CA 5] Center 33 (3~64) winsize 62
3997 12:41:48.904130
3998 12:41:48.907461 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3999 12:41:48.907902
4000 12:41:48.910797 [CATrainingPosCal] consider 1 rank data
4001 12:41:48.914025 u2DelayCellTimex100 = 270/100 ps
4002 12:41:48.916864 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4003 12:41:48.920524 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4004 12:41:48.924068 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4005 12:41:48.927061 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4006 12:41:48.931296 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4007 12:41:48.937363 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4008 12:41:48.937796
4009 12:41:48.940547 CA PerBit enable=1, Macro0, CA PI delay=33
4010 12:41:48.940977
4011 12:41:48.943738 [CBTSetCACLKResult] CA Dly = 33
4012 12:41:48.944170 CS Dly: 4 (0~35)
4013 12:41:48.944512 ==
4014 12:41:48.946852 Dram Type= 6, Freq= 0, CH_0, rank 1
4015 12:41:48.950528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4016 12:41:48.953849 ==
4017 12:41:48.957093 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4018 12:41:48.963731 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4019 12:41:48.966785 [CA 0] Center 36 (6~66) winsize 61
4020 12:41:48.970155 [CA 1] Center 36 (6~66) winsize 61
4021 12:41:48.973403 [CA 2] Center 34 (4~65) winsize 62
4022 12:41:48.976983 [CA 3] Center 34 (4~65) winsize 62
4023 12:41:48.980468 [CA 4] Center 33 (3~64) winsize 62
4024 12:41:48.983410 [CA 5] Center 33 (3~64) winsize 62
4025 12:41:48.983848
4026 12:41:48.986419 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4027 12:41:48.986854
4028 12:41:48.989935 [CATrainingPosCal] consider 2 rank data
4029 12:41:48.993065 u2DelayCellTimex100 = 270/100 ps
4030 12:41:48.996349 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4031 12:41:48.999913 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4032 12:41:49.003479 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4033 12:41:49.009440 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4034 12:41:49.012900 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4035 12:41:49.016585 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4036 12:41:49.017020
4037 12:41:49.019514 CA PerBit enable=1, Macro0, CA PI delay=33
4038 12:41:49.019951
4039 12:41:49.023132 [CBTSetCACLKResult] CA Dly = 33
4040 12:41:49.023622 CS Dly: 4 (0~36)
4041 12:41:49.023985
4042 12:41:49.026297 ----->DramcWriteLeveling(PI) begin...
4043 12:41:49.026735 ==
4044 12:41:49.029639 Dram Type= 6, Freq= 0, CH_0, rank 0
4045 12:41:49.036158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4046 12:41:49.036640 ==
4047 12:41:49.039651 Write leveling (Byte 0): 31 => 31
4048 12:41:49.042801 Write leveling (Byte 1): 31 => 31
4049 12:41:49.046273 DramcWriteLeveling(PI) end<-----
4050 12:41:49.046874
4051 12:41:49.047458 ==
4052 12:41:49.049740 Dram Type= 6, Freq= 0, CH_0, rank 0
4053 12:41:49.053014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4054 12:41:49.053577 ==
4055 12:41:49.056222 [Gating] SW mode calibration
4056 12:41:49.062852 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4057 12:41:49.066795 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4058 12:41:49.072850 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4059 12:41:49.076587 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4060 12:41:49.080087 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4061 12:41:49.086465 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4062 12:41:49.089606 0 9 16 | B1->B0 | 3232 2c2c | 0 1 | (0 1) (0 0)
4063 12:41:49.093070 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4064 12:41:49.099712 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4065 12:41:49.103343 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4066 12:41:49.106225 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4067 12:41:49.113023 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4068 12:41:49.116452 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4069 12:41:49.119793 0 10 12 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
4070 12:41:49.126328 0 10 16 | B1->B0 | 3030 4444 | 0 0 | (0 0) (0 0)
4071 12:41:49.129772 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4072 12:41:49.133222 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 12:41:49.139865 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4074 12:41:49.142823 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4075 12:41:49.145991 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4076 12:41:49.149318 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4077 12:41:49.155930 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4078 12:41:49.159506 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4079 12:41:49.162860 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 12:41:49.169512 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 12:41:49.172857 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 12:41:49.176037 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 12:41:49.182794 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 12:41:49.186330 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 12:41:49.189050 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 12:41:49.196189 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 12:41:49.199119 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 12:41:49.202573 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 12:41:49.209094 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 12:41:49.212497 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 12:41:49.215937 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 12:41:49.222638 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 12:41:49.225918 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4094 12:41:49.229454 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4095 12:41:49.232177 Total UI for P1: 0, mck2ui 16
4096 12:41:49.236257 best dqsien dly found for B0: ( 0, 13, 14)
4097 12:41:49.243207 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4098 12:41:49.243702 Total UI for P1: 0, mck2ui 16
4099 12:41:49.249461 best dqsien dly found for B1: ( 0, 13, 14)
4100 12:41:49.252863 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4101 12:41:49.255602 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4102 12:41:49.256035
4103 12:41:49.259472 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4104 12:41:49.262145 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4105 12:41:49.265627 [Gating] SW calibration Done
4106 12:41:49.266095 ==
4107 12:41:49.268779 Dram Type= 6, Freq= 0, CH_0, rank 0
4108 12:41:49.272044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4109 12:41:49.272549 ==
4110 12:41:49.275669 RX Vref Scan: 0
4111 12:41:49.276129
4112 12:41:49.276497 RX Vref 0 -> 0, step: 1
4113 12:41:49.276929
4114 12:41:49.278911 RX Delay -230 -> 252, step: 16
4115 12:41:49.285661 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4116 12:41:49.288763 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4117 12:41:49.292069 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4118 12:41:49.295642 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4119 12:41:49.298599 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4120 12:41:49.305574 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4121 12:41:49.308761 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4122 12:41:49.312331 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4123 12:41:49.315682 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4124 12:41:49.321918 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4125 12:41:49.325228 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4126 12:41:49.328617 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4127 12:41:49.332127 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4128 12:41:49.338389 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4129 12:41:49.341962 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4130 12:41:49.345489 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4131 12:41:49.346021 ==
4132 12:41:49.348604 Dram Type= 6, Freq= 0, CH_0, rank 0
4133 12:41:49.351661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 12:41:49.352304 ==
4135 12:41:49.354958 DQS Delay:
4136 12:41:49.355485 DQS0 = 0, DQS1 = 0
4137 12:41:49.358495 DQM Delay:
4138 12:41:49.359026 DQM0 = 44, DQM1 = 33
4139 12:41:49.359560 DQ Delay:
4140 12:41:49.361538 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4141 12:41:49.365511 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4142 12:41:49.368044 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4143 12:41:49.371760 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =49
4144 12:41:49.372307
4145 12:41:49.372734
4146 12:41:49.376019 ==
4147 12:41:49.378418 Dram Type= 6, Freq= 0, CH_0, rank 0
4148 12:41:49.381963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 12:41:49.382643 ==
4150 12:41:49.383067
4151 12:41:49.383437
4152 12:41:49.385086 TX Vref Scan disable
4153 12:41:49.385591 == TX Byte 0 ==
4154 12:41:49.388344 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4155 12:41:49.394802 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4156 12:41:49.395229 == TX Byte 1 ==
4157 12:41:49.401785 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4158 12:41:49.404814 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4159 12:41:49.405245 ==
4160 12:41:49.408344 Dram Type= 6, Freq= 0, CH_0, rank 0
4161 12:41:49.411633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 12:41:49.412102 ==
4163 12:41:49.412545
4164 12:41:49.412875
4165 12:41:49.414727 TX Vref Scan disable
4166 12:41:49.418296 == TX Byte 0 ==
4167 12:41:49.421489 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4168 12:41:49.425123 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4169 12:41:49.428007 == TX Byte 1 ==
4170 12:41:49.431455 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4171 12:41:49.434891 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4172 12:41:49.435323
4173 12:41:49.437775 [DATLAT]
4174 12:41:49.438204 Freq=600, CH0 RK0
4175 12:41:49.438549
4176 12:41:49.441639 DATLAT Default: 0x9
4177 12:41:49.442068 0, 0xFFFF, sum = 0
4178 12:41:49.444923 1, 0xFFFF, sum = 0
4179 12:41:49.445361 2, 0xFFFF, sum = 0
4180 12:41:49.447590 3, 0xFFFF, sum = 0
4181 12:41:49.448026 4, 0xFFFF, sum = 0
4182 12:41:49.451322 5, 0xFFFF, sum = 0
4183 12:41:49.451824 6, 0xFFFF, sum = 0
4184 12:41:49.454262 7, 0xFFFF, sum = 0
4185 12:41:49.454699 8, 0x0, sum = 1
4186 12:41:49.457493 9, 0x0, sum = 2
4187 12:41:49.457935 10, 0x0, sum = 3
4188 12:41:49.461043 11, 0x0, sum = 4
4189 12:41:49.461487 best_step = 9
4190 12:41:49.461832
4191 12:41:49.462159 ==
4192 12:41:49.464435 Dram Type= 6, Freq= 0, CH_0, rank 0
4193 12:41:49.467779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4194 12:41:49.470790 ==
4195 12:41:49.471283 RX Vref Scan: 1
4196 12:41:49.471798
4197 12:41:49.474108 RX Vref 0 -> 0, step: 1
4198 12:41:49.474593
4199 12:41:49.478133 RX Delay -195 -> 252, step: 8
4200 12:41:49.478563
4201 12:41:49.481367 Set Vref, RX VrefLevel [Byte0]: 55
4202 12:41:49.484078 [Byte1]: 51
4203 12:41:49.484507
4204 12:41:49.487932 Final RX Vref Byte 0 = 55 to rank0
4205 12:41:49.490916 Final RX Vref Byte 1 = 51 to rank0
4206 12:41:49.494338 Final RX Vref Byte 0 = 55 to rank1
4207 12:41:49.497382 Final RX Vref Byte 1 = 51 to rank1==
4208 12:41:49.500970 Dram Type= 6, Freq= 0, CH_0, rank 0
4209 12:41:49.504376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4210 12:41:49.504807 ==
4211 12:41:49.507150 DQS Delay:
4212 12:41:49.507607 DQS0 = 0, DQS1 = 0
4213 12:41:49.507952 DQM Delay:
4214 12:41:49.511049 DQM0 = 43, DQM1 = 33
4215 12:41:49.511515 DQ Delay:
4216 12:41:49.514538 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4217 12:41:49.517446 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4218 12:41:49.520431 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4219 12:41:49.523839 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4220 12:41:49.524270
4221 12:41:49.524611
4222 12:41:49.534157 [DQSOSCAuto] RK0, (LSB)MR18= 0x4220, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
4223 12:41:49.534598 CH0 RK0: MR19=808, MR18=4220
4224 12:41:49.540660 CH0_RK0: MR19=0x808, MR18=0x4220, DQSOSC=397, MR23=63, INC=166, DEC=110
4225 12:41:49.541098
4226 12:41:49.543913 ----->DramcWriteLeveling(PI) begin...
4227 12:41:49.547384 ==
4228 12:41:49.550798 Dram Type= 6, Freq= 0, CH_0, rank 1
4229 12:41:49.554231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4230 12:41:49.554672 ==
4231 12:41:49.557662 Write leveling (Byte 0): 31 => 31
4232 12:41:49.561164 Write leveling (Byte 1): 30 => 30
4233 12:41:49.564460 DramcWriteLeveling(PI) end<-----
4234 12:41:49.564902
4235 12:41:49.565348 ==
4236 12:41:49.567457 Dram Type= 6, Freq= 0, CH_0, rank 1
4237 12:41:49.570470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4238 12:41:49.570936 ==
4239 12:41:49.573473 [Gating] SW mode calibration
4240 12:41:49.580020 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4241 12:41:49.587130 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4242 12:41:49.590293 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4243 12:41:49.593565 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4244 12:41:49.600173 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4245 12:41:49.603487 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 0) (1 0)
4246 12:41:49.607254 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
4247 12:41:49.610110 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4248 12:41:49.616986 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4249 12:41:49.620166 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4250 12:41:49.623728 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4251 12:41:49.630131 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4252 12:41:49.633436 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4253 12:41:49.636966 0 10 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
4254 12:41:49.643400 0 10 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4255 12:41:49.646696 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 12:41:49.650236 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 12:41:49.656754 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4258 12:41:49.660265 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4259 12:41:49.663754 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4260 12:41:49.669695 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4261 12:41:49.673148 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4262 12:41:49.676623 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4263 12:41:49.683185 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 12:41:49.686327 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 12:41:49.690338 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 12:41:49.696430 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 12:41:49.699339 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 12:41:49.702782 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 12:41:49.709358 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 12:41:49.712779 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 12:41:49.716359 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 12:41:49.723190 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 12:41:49.726097 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 12:41:49.729889 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 12:41:49.736334 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 12:41:49.739728 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 12:41:49.742904 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4278 12:41:49.749829 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4279 12:41:49.750383 Total UI for P1: 0, mck2ui 16
4280 12:41:49.752683 best dqsien dly found for B0: ( 0, 13, 12)
4281 12:41:49.756021 Total UI for P1: 0, mck2ui 16
4282 12:41:49.759499 best dqsien dly found for B1: ( 0, 13, 14)
4283 12:41:49.766120 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4284 12:41:49.769669 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4285 12:41:49.770105
4286 12:41:49.773099 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4287 12:41:49.776348 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4288 12:41:49.779708 [Gating] SW calibration Done
4289 12:41:49.780308 ==
4290 12:41:49.782986 Dram Type= 6, Freq= 0, CH_0, rank 1
4291 12:41:49.786172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4292 12:41:49.786686 ==
4293 12:41:49.789923 RX Vref Scan: 0
4294 12:41:49.790421
4295 12:41:49.790781 RX Vref 0 -> 0, step: 1
4296 12:41:49.791226
4297 12:41:49.792890 RX Delay -230 -> 252, step: 16
4298 12:41:49.796291 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4299 12:41:49.802529 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4300 12:41:49.805860 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4301 12:41:49.809135 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4302 12:41:49.812464 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4303 12:41:49.819577 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4304 12:41:49.822633 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4305 12:41:49.825748 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4306 12:41:49.829031 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4307 12:41:49.832665 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4308 12:41:49.839268 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4309 12:41:49.842529 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4310 12:41:49.845699 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4311 12:41:49.849160 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4312 12:41:49.855929 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4313 12:41:49.859274 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4314 12:41:49.859756 ==
4315 12:41:49.862942 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 12:41:49.866240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 12:41:49.866741 ==
4318 12:41:49.868722 DQS Delay:
4319 12:41:49.869152 DQS0 = 0, DQS1 = 0
4320 12:41:49.869584 DQM Delay:
4321 12:41:49.872195 DQM0 = 39, DQM1 = 32
4322 12:41:49.872621 DQ Delay:
4323 12:41:49.876236 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4324 12:41:49.878813 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4325 12:41:49.882531 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4326 12:41:49.885651 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4327 12:41:49.886118
4328 12:41:49.886568
4329 12:41:49.886912 ==
4330 12:41:49.888811 Dram Type= 6, Freq= 0, CH_0, rank 1
4331 12:41:49.895237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4332 12:41:49.895722 ==
4333 12:41:49.896070
4334 12:41:49.896407
4335 12:41:49.896712 TX Vref Scan disable
4336 12:41:49.899513 == TX Byte 0 ==
4337 12:41:49.902503 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4338 12:41:49.909465 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4339 12:41:49.909897 == TX Byte 1 ==
4340 12:41:49.912765 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4341 12:41:49.919454 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4342 12:41:49.920059 ==
4343 12:41:49.922209 Dram Type= 6, Freq= 0, CH_0, rank 1
4344 12:41:49.925723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4345 12:41:49.926259 ==
4346 12:41:49.926811
4347 12:41:49.927228
4348 12:41:49.929084 TX Vref Scan disable
4349 12:41:49.932505 == TX Byte 0 ==
4350 12:41:49.935808 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4351 12:41:49.939377 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4352 12:41:49.942255 == TX Byte 1 ==
4353 12:41:49.945641 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4354 12:41:49.948832 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4355 12:41:49.949304
4356 12:41:49.949723 [DATLAT]
4357 12:41:49.952248 Freq=600, CH0 RK1
4358 12:41:49.952789
4359 12:41:49.955575 DATLAT Default: 0x9
4360 12:41:49.956147 0, 0xFFFF, sum = 0
4361 12:41:49.958765 1, 0xFFFF, sum = 0
4362 12:41:49.959281 2, 0xFFFF, sum = 0
4363 12:41:49.962452 3, 0xFFFF, sum = 0
4364 12:41:49.962957 4, 0xFFFF, sum = 0
4365 12:41:49.965248 5, 0xFFFF, sum = 0
4366 12:41:49.965748 6, 0xFFFF, sum = 0
4367 12:41:49.968595 7, 0xFFFF, sum = 0
4368 12:41:49.969104 8, 0x0, sum = 1
4369 12:41:49.972241 9, 0x0, sum = 2
4370 12:41:49.972751 10, 0x0, sum = 3
4371 12:41:49.973206 11, 0x0, sum = 4
4372 12:41:49.975335 best_step = 9
4373 12:41:49.975708
4374 12:41:49.976027 ==
4375 12:41:49.978851 Dram Type= 6, Freq= 0, CH_0, rank 1
4376 12:41:49.982197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4377 12:41:49.982424 ==
4378 12:41:49.985037 RX Vref Scan: 0
4379 12:41:49.985262
4380 12:41:49.985440 RX Vref 0 -> 0, step: 1
4381 12:41:49.988487
4382 12:41:49.988712 RX Delay -195 -> 252, step: 8
4383 12:41:49.996568 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4384 12:41:49.999242 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4385 12:41:50.002638 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4386 12:41:50.006381 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4387 12:41:50.012816 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4388 12:41:50.015769 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4389 12:41:50.019304 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4390 12:41:50.022634 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4391 12:41:50.026078 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4392 12:41:50.032797 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4393 12:41:50.036506 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4394 12:41:50.039892 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4395 12:41:50.042618 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4396 12:41:50.049409 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4397 12:41:50.052699 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4398 12:41:50.055963 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4399 12:41:50.056284 ==
4400 12:41:50.059172 Dram Type= 6, Freq= 0, CH_0, rank 1
4401 12:41:50.062536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4402 12:41:50.065724 ==
4403 12:41:50.065807 DQS Delay:
4404 12:41:50.065873 DQS0 = 0, DQS1 = 0
4405 12:41:50.069155 DQM Delay:
4406 12:41:50.069237 DQM0 = 40, DQM1 = 33
4407 12:41:50.072233 DQ Delay:
4408 12:41:50.075754 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =40
4409 12:41:50.075839 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48
4410 12:41:50.079440 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4411 12:41:50.082703 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4412 12:41:50.085596
4413 12:41:50.085706
4414 12:41:50.092818 [DQSOSCAuto] RK1, (LSB)MR18= 0x4729, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4415 12:41:50.095992 CH0 RK1: MR19=808, MR18=4729
4416 12:41:50.102668 CH0_RK1: MR19=0x808, MR18=0x4729, DQSOSC=396, MR23=63, INC=167, DEC=111
4417 12:41:50.105845 [RxdqsGatingPostProcess] freq 600
4418 12:41:50.108959 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4419 12:41:50.112114 Pre-setting of DQS Precalculation
4420 12:41:50.118728 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4421 12:41:50.118812 ==
4422 12:41:50.122043 Dram Type= 6, Freq= 0, CH_1, rank 0
4423 12:41:50.126055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4424 12:41:50.126198 ==
4425 12:41:50.132434 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4426 12:41:50.135382 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4427 12:41:50.140076 [CA 0] Center 35 (5~66) winsize 62
4428 12:41:50.142859 [CA 1] Center 35 (5~66) winsize 62
4429 12:41:50.146178 [CA 2] Center 33 (3~64) winsize 62
4430 12:41:50.149379 [CA 3] Center 33 (3~64) winsize 62
4431 12:41:50.153008 [CA 4] Center 34 (3~65) winsize 63
4432 12:41:50.156312 [CA 5] Center 33 (3~64) winsize 62
4433 12:41:50.156393
4434 12:41:50.159561 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4435 12:41:50.159643
4436 12:41:50.163059 [CATrainingPosCal] consider 1 rank data
4437 12:41:50.166353 u2DelayCellTimex100 = 270/100 ps
4438 12:41:50.169475 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4439 12:41:50.175981 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4440 12:41:50.179384 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4441 12:41:50.182589 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4442 12:41:50.185670 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4443 12:41:50.189158 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4444 12:41:50.189272
4445 12:41:50.192471 CA PerBit enable=1, Macro0, CA PI delay=33
4446 12:41:50.192554
4447 12:41:50.196124 [CBTSetCACLKResult] CA Dly = 33
4448 12:41:50.199278 CS Dly: 4 (0~35)
4449 12:41:50.199402 ==
4450 12:41:50.202449 Dram Type= 6, Freq= 0, CH_1, rank 1
4451 12:41:50.205630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4452 12:41:50.205757 ==
4453 12:41:50.212320 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4454 12:41:50.215588 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4455 12:41:50.219723 [CA 0] Center 35 (5~66) winsize 62
4456 12:41:50.223001 [CA 1] Center 35 (5~66) winsize 62
4457 12:41:50.226349 [CA 2] Center 34 (4~65) winsize 62
4458 12:41:50.229422 [CA 3] Center 34 (3~65) winsize 63
4459 12:41:50.233037 [CA 4] Center 34 (3~65) winsize 63
4460 12:41:50.236242 [CA 5] Center 33 (3~64) winsize 62
4461 12:41:50.236364
4462 12:41:50.239949 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4463 12:41:50.240034
4464 12:41:50.242909 [CATrainingPosCal] consider 2 rank data
4465 12:41:50.246391 u2DelayCellTimex100 = 270/100 ps
4466 12:41:50.249653 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4467 12:41:50.256484 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4468 12:41:50.259629 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4469 12:41:50.262835 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4470 12:41:50.266197 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4471 12:41:50.269688 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4472 12:41:50.269772
4473 12:41:50.272829 CA PerBit enable=1, Macro0, CA PI delay=33
4474 12:41:50.272915
4475 12:41:50.276302 [CBTSetCACLKResult] CA Dly = 33
4476 12:41:50.276388 CS Dly: 4 (0~35)
4477 12:41:50.276486
4478 12:41:50.279384 ----->DramcWriteLeveling(PI) begin...
4479 12:41:50.282537 ==
4480 12:41:50.286283 Dram Type= 6, Freq= 0, CH_1, rank 0
4481 12:41:50.289367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4482 12:41:50.289454 ==
4483 12:41:50.292795 Write leveling (Byte 0): 30 => 30
4484 12:41:50.295791 Write leveling (Byte 1): 30 => 30
4485 12:41:50.299316 DramcWriteLeveling(PI) end<-----
4486 12:41:50.299431
4487 12:41:50.299511 ==
4488 12:41:50.303043 Dram Type= 6, Freq= 0, CH_1, rank 0
4489 12:41:50.305956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4490 12:41:50.306041 ==
4491 12:41:50.309179 [Gating] SW mode calibration
4492 12:41:50.315854 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4493 12:41:50.322535 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4494 12:41:50.325982 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4495 12:41:50.329172 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4496 12:41:50.335901 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4497 12:41:50.338887 0 9 12 | B1->B0 | 3333 3232 | 0 0 | (0 0) (0 0)
4498 12:41:50.342607 0 9 16 | B1->B0 | 2929 2727 | 0 0 | (0 0) (1 1)
4499 12:41:50.348729 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4500 12:41:50.352181 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4501 12:41:50.355541 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4502 12:41:50.362631 0 10 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4503 12:41:50.365591 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4504 12:41:50.368624 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4505 12:41:50.375464 0 10 12 | B1->B0 | 2727 2e2e | 0 0 | (0 0) (0 0)
4506 12:41:50.378920 0 10 16 | B1->B0 | 4242 4242 | 1 0 | (0 0) (0 0)
4507 12:41:50.382188 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4508 12:41:50.388659 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 12:41:50.392058 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 12:41:50.395473 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4511 12:41:50.398591 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4512 12:41:50.405048 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4513 12:41:50.408803 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4514 12:41:50.412046 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 12:41:50.418765 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 12:41:50.421913 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 12:41:50.425556 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 12:41:50.432398 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 12:41:50.435020 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 12:41:50.438701 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 12:41:50.445029 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 12:41:50.448388 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 12:41:50.451533 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 12:41:50.458384 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 12:41:50.461391 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 12:41:50.465430 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 12:41:50.472164 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 12:41:50.475137 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 12:41:50.478071 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4530 12:41:50.484835 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4531 12:41:50.484932 Total UI for P1: 0, mck2ui 16
4532 12:41:50.491567 best dqsien dly found for B0: ( 0, 13, 14)
4533 12:41:50.495172 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4534 12:41:50.498085 Total UI for P1: 0, mck2ui 16
4535 12:41:50.502028 best dqsien dly found for B1: ( 0, 13, 16)
4536 12:41:50.505072 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4537 12:41:50.508603 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4538 12:41:50.508715
4539 12:41:50.511276 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4540 12:41:50.514964 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4541 12:41:50.518184 [Gating] SW calibration Done
4542 12:41:50.518268 ==
4543 12:41:50.521653 Dram Type= 6, Freq= 0, CH_1, rank 0
4544 12:41:50.525033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4545 12:41:50.528146 ==
4546 12:41:50.528230 RX Vref Scan: 0
4547 12:41:50.528297
4548 12:41:50.531561 RX Vref 0 -> 0, step: 1
4549 12:41:50.531644
4550 12:41:50.535013 RX Delay -230 -> 252, step: 16
4551 12:41:50.538327 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4552 12:41:50.541291 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4553 12:41:50.544958 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4554 12:41:50.547901 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4555 12:41:50.554743 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4556 12:41:50.558256 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4557 12:41:50.560985 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4558 12:41:50.564974 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4559 12:41:50.571396 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4560 12:41:50.574616 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4561 12:41:50.577795 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4562 12:41:50.580774 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4563 12:41:50.587643 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4564 12:41:50.590818 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4565 12:41:50.594129 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4566 12:41:50.597533 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4567 12:41:50.597676 ==
4568 12:41:50.600694 Dram Type= 6, Freq= 0, CH_1, rank 0
4569 12:41:50.607664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 12:41:50.607748 ==
4571 12:41:50.607815 DQS Delay:
4572 12:41:50.610574 DQS0 = 0, DQS1 = 0
4573 12:41:50.610677 DQM Delay:
4574 12:41:50.613847 DQM0 = 44, DQM1 = 36
4575 12:41:50.613955 DQ Delay:
4576 12:41:50.617769 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4577 12:41:50.620497 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4578 12:41:50.623990 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =33
4579 12:41:50.627495 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4580 12:41:50.627581
4581 12:41:50.627649
4582 12:41:50.627712 ==
4583 12:41:50.630413 Dram Type= 6, Freq= 0, CH_1, rank 0
4584 12:41:50.633548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4585 12:41:50.633623 ==
4586 12:41:50.633687
4587 12:41:50.633755
4588 12:41:50.637083 TX Vref Scan disable
4589 12:41:50.640445 == TX Byte 0 ==
4590 12:41:50.643973 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4591 12:41:50.647091 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4592 12:41:50.650568 == TX Byte 1 ==
4593 12:41:50.653680 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4594 12:41:50.657332 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4595 12:41:50.657438 ==
4596 12:41:50.660393 Dram Type= 6, Freq= 0, CH_1, rank 0
4597 12:41:50.666971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4598 12:41:50.667079 ==
4599 12:41:50.667221
4600 12:41:50.667339
4601 12:41:50.667454 TX Vref Scan disable
4602 12:41:50.671053 == TX Byte 0 ==
4603 12:41:50.674583 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4604 12:41:50.681350 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4605 12:41:50.681461 == TX Byte 1 ==
4606 12:41:50.684166 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4607 12:41:50.691226 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4608 12:41:50.691362
4609 12:41:50.691476 [DATLAT]
4610 12:41:50.691573 Freq=600, CH1 RK0
4611 12:41:50.691668
4612 12:41:50.694590 DATLAT Default: 0x9
4613 12:41:50.694698 0, 0xFFFF, sum = 0
4614 12:41:50.697633 1, 0xFFFF, sum = 0
4615 12:41:50.697740 2, 0xFFFF, sum = 0
4616 12:41:50.700793 3, 0xFFFF, sum = 0
4617 12:41:50.704535 4, 0xFFFF, sum = 0
4618 12:41:50.704620 5, 0xFFFF, sum = 0
4619 12:41:50.707304 6, 0xFFFF, sum = 0
4620 12:41:50.707435 7, 0xFFFF, sum = 0
4621 12:41:50.711155 8, 0x0, sum = 1
4622 12:41:50.711277 9, 0x0, sum = 2
4623 12:41:50.711400 10, 0x0, sum = 3
4624 12:41:50.714422 11, 0x0, sum = 4
4625 12:41:50.714522 best_step = 9
4626 12:41:50.714620
4627 12:41:50.714709 ==
4628 12:41:50.717157 Dram Type= 6, Freq= 0, CH_1, rank 0
4629 12:41:50.723723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4630 12:41:50.723833 ==
4631 12:41:50.723932 RX Vref Scan: 1
4632 12:41:50.724015
4633 12:41:50.727107 RX Vref 0 -> 0, step: 1
4634 12:41:50.727216
4635 12:41:50.730936 RX Delay -195 -> 252, step: 8
4636 12:41:50.731021
4637 12:41:50.733828 Set Vref, RX VrefLevel [Byte0]: 52
4638 12:41:50.737103 [Byte1]: 51
4639 12:41:50.737184
4640 12:41:50.740723 Final RX Vref Byte 0 = 52 to rank0
4641 12:41:50.743936 Final RX Vref Byte 1 = 51 to rank0
4642 12:41:50.747156 Final RX Vref Byte 0 = 52 to rank1
4643 12:41:50.750316 Final RX Vref Byte 1 = 51 to rank1==
4644 12:41:50.753653 Dram Type= 6, Freq= 0, CH_1, rank 0
4645 12:41:50.757440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4646 12:41:50.757552 ==
4647 12:41:50.760763 DQS Delay:
4648 12:41:50.760846 DQS0 = 0, DQS1 = 0
4649 12:41:50.763632 DQM Delay:
4650 12:41:50.763718 DQM0 = 41, DQM1 = 33
4651 12:41:50.763784 DQ Delay:
4652 12:41:50.767439 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4653 12:41:50.770289 DQ4 =44, DQ5 =52, DQ6 =52, DQ7 =36
4654 12:41:50.773397 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =28
4655 12:41:50.777304 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4656 12:41:50.777411
4657 12:41:50.777481
4658 12:41:50.786851 [DQSOSCAuto] RK0, (LSB)MR18= 0x440a, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 396 ps
4659 12:41:50.790221 CH1 RK0: MR19=808, MR18=440A
4660 12:41:50.797062 CH1_RK0: MR19=0x808, MR18=0x440A, DQSOSC=396, MR23=63, INC=167, DEC=111
4661 12:41:50.797156
4662 12:41:50.800213 ----->DramcWriteLeveling(PI) begin...
4663 12:41:50.800306 ==
4664 12:41:50.803793 Dram Type= 6, Freq= 0, CH_1, rank 1
4665 12:41:50.806607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4666 12:41:50.806708 ==
4667 12:41:50.809800 Write leveling (Byte 0): 29 => 29
4668 12:41:50.812994 Write leveling (Byte 1): 32 => 32
4669 12:41:50.816791 DramcWriteLeveling(PI) end<-----
4670 12:41:50.816889
4671 12:41:50.816980 ==
4672 12:41:50.819700 Dram Type= 6, Freq= 0, CH_1, rank 1
4673 12:41:50.823151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4674 12:41:50.823236 ==
4675 12:41:50.826223 [Gating] SW mode calibration
4676 12:41:50.832951 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4677 12:41:50.839789 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4678 12:41:50.843276 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4679 12:41:50.846573 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4680 12:41:50.852733 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4681 12:41:50.856127 0 9 12 | B1->B0 | 3333 2e2e | 0 0 | (1 0) (1 1)
4682 12:41:50.859465 0 9 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4683 12:41:50.866029 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4684 12:41:50.869535 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4685 12:41:50.872672 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4686 12:41:50.879495 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4687 12:41:50.883077 0 10 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4688 12:41:50.886171 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4689 12:41:50.893116 0 10 12 | B1->B0 | 2e2e 3c3c | 0 0 | (0 0) (0 0)
4690 12:41:50.896423 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4691 12:41:50.899792 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4692 12:41:50.906205 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4693 12:41:50.909220 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4694 12:41:50.912646 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4695 12:41:50.919058 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4696 12:41:50.922565 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4697 12:41:50.926155 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4698 12:41:50.932729 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 12:41:50.936136 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 12:41:50.939228 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 12:41:50.946160 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 12:41:50.948984 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 12:41:50.952678 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 12:41:50.959511 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 12:41:50.962388 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 12:41:50.965931 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 12:41:50.969196 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 12:41:50.976382 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 12:41:50.979047 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 12:41:50.982619 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 12:41:50.989438 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 12:41:50.992284 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4713 12:41:50.995868 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4714 12:41:50.999581 Total UI for P1: 0, mck2ui 16
4715 12:41:51.002473 best dqsien dly found for B0: ( 0, 13, 8)
4716 12:41:51.008920 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4717 12:41:51.009037 Total UI for P1: 0, mck2ui 16
4718 12:41:51.015460 best dqsien dly found for B1: ( 0, 13, 12)
4719 12:41:51.018735 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4720 12:41:51.022266 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4721 12:41:51.022368
4722 12:41:51.025540 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4723 12:41:51.028928 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4724 12:41:51.032254 [Gating] SW calibration Done
4725 12:41:51.032338 ==
4726 12:41:51.035547 Dram Type= 6, Freq= 0, CH_1, rank 1
4727 12:41:51.038865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4728 12:41:51.038966 ==
4729 12:41:51.041969 RX Vref Scan: 0
4730 12:41:51.042074
4731 12:41:51.042145 RX Vref 0 -> 0, step: 1
4732 12:41:51.042209
4733 12:41:51.045615 RX Delay -230 -> 252, step: 16
4734 12:41:51.052232 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4735 12:41:51.055579 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4736 12:41:51.058799 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4737 12:41:51.061775 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4738 12:41:51.065682 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4739 12:41:51.071980 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4740 12:41:51.075521 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4741 12:41:51.078513 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4742 12:41:51.081886 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4743 12:41:51.088595 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4744 12:41:51.092015 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4745 12:41:51.095173 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4746 12:41:51.098696 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4747 12:41:51.105264 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4748 12:41:51.108335 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4749 12:41:51.111761 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4750 12:41:51.111853 ==
4751 12:41:51.115467 Dram Type= 6, Freq= 0, CH_1, rank 1
4752 12:41:51.118512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4753 12:41:51.118631 ==
4754 12:41:51.122233 DQS Delay:
4755 12:41:51.122333 DQS0 = 0, DQS1 = 0
4756 12:41:51.125117 DQM Delay:
4757 12:41:51.125235 DQM0 = 40, DQM1 = 36
4758 12:41:51.125305 DQ Delay:
4759 12:41:51.128452 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4760 12:41:51.132070 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4761 12:41:51.135253 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4762 12:41:51.138403 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4763 12:41:51.138520
4764 12:41:51.138586
4765 12:41:51.141625 ==
4766 12:41:51.144731 Dram Type= 6, Freq= 0, CH_1, rank 1
4767 12:41:51.148608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4768 12:41:51.148692 ==
4769 12:41:51.148758
4770 12:41:51.148821
4771 12:41:51.151414 TX Vref Scan disable
4772 12:41:51.151497 == TX Byte 0 ==
4773 12:41:51.158587 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4774 12:41:51.161749 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4775 12:41:51.161832 == TX Byte 1 ==
4776 12:41:51.167776 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4777 12:41:51.171378 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4778 12:41:51.171527 ==
4779 12:41:51.174783 Dram Type= 6, Freq= 0, CH_1, rank 1
4780 12:41:51.177949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4781 12:41:51.178063 ==
4782 12:41:51.178188
4783 12:41:51.178249
4784 12:41:51.181238 TX Vref Scan disable
4785 12:41:51.184518 == TX Byte 0 ==
4786 12:41:51.188278 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4787 12:41:51.191052 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4788 12:41:51.194297 == TX Byte 1 ==
4789 12:41:51.198319 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4790 12:41:51.201255 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4791 12:41:51.204573
4792 12:41:51.204657 [DATLAT]
4793 12:41:51.204723 Freq=600, CH1 RK1
4794 12:41:51.204786
4795 12:41:51.207644 DATLAT Default: 0x9
4796 12:41:51.207730 0, 0xFFFF, sum = 0
4797 12:41:51.210964 1, 0xFFFF, sum = 0
4798 12:41:51.211050 2, 0xFFFF, sum = 0
4799 12:41:51.214227 3, 0xFFFF, sum = 0
4800 12:41:51.214311 4, 0xFFFF, sum = 0
4801 12:41:51.217564 5, 0xFFFF, sum = 0
4802 12:41:51.220860 6, 0xFFFF, sum = 0
4803 12:41:51.220977 7, 0xFFFF, sum = 0
4804 12:41:51.221068 8, 0x0, sum = 1
4805 12:41:51.224559 9, 0x0, sum = 2
4806 12:41:51.224693 10, 0x0, sum = 3
4807 12:41:51.227764 11, 0x0, sum = 4
4808 12:41:51.227849 best_step = 9
4809 12:41:51.227931
4810 12:41:51.228020 ==
4811 12:41:51.230723 Dram Type= 6, Freq= 0, CH_1, rank 1
4812 12:41:51.237654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4813 12:41:51.237743 ==
4814 12:41:51.237840 RX Vref Scan: 0
4815 12:41:51.237937
4816 12:41:51.240771 RX Vref 0 -> 0, step: 1
4817 12:41:51.240872
4818 12:41:51.244205 RX Delay -179 -> 252, step: 8
4819 12:41:51.247208 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4820 12:41:51.254525 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4821 12:41:51.257181 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4822 12:41:51.260789 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4823 12:41:51.264129 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4824 12:41:51.267397 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4825 12:41:51.274010 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4826 12:41:51.277750 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4827 12:41:51.281322 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4828 12:41:51.284109 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4829 12:41:51.290424 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4830 12:41:51.293964 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4831 12:41:51.297314 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4832 12:41:51.300663 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4833 12:41:51.307327 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4834 12:41:51.310694 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4835 12:41:51.310778 ==
4836 12:41:51.314073 Dram Type= 6, Freq= 0, CH_1, rank 1
4837 12:41:51.317942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4838 12:41:51.318046 ==
4839 12:41:51.318139 DQS Delay:
4840 12:41:51.320739 DQS0 = 0, DQS1 = 0
4841 12:41:51.320828 DQM Delay:
4842 12:41:51.324087 DQM0 = 38, DQM1 = 32
4843 12:41:51.324169 DQ Delay:
4844 12:41:51.327707 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4845 12:41:51.331012 DQ4 =40, DQ5 =48, DQ6 =44, DQ7 =36
4846 12:41:51.334277 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4847 12:41:51.337394 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4848 12:41:51.337497
4849 12:41:51.337578
4850 12:41:51.347409 [DQSOSCAuto] RK1, (LSB)MR18= 0x3949, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
4851 12:41:51.347534 CH1 RK1: MR19=808, MR18=3949
4852 12:41:51.354301 CH1_RK1: MR19=0x808, MR18=0x3949, DQSOSC=396, MR23=63, INC=167, DEC=111
4853 12:41:51.357301 [RxdqsGatingPostProcess] freq 600
4854 12:41:51.364145 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4855 12:41:51.367496 Pre-setting of DQS Precalculation
4856 12:41:51.370491 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4857 12:41:51.377122 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4858 12:41:51.387052 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4859 12:41:51.387511
4860 12:41:51.387914
4861 12:41:51.390617 [Calibration Summary] 1200 Mbps
4862 12:41:51.390934 CH 0, Rank 0
4863 12:41:51.394223 SW Impedance : PASS
4864 12:41:51.394542 DUTY Scan : NO K
4865 12:41:51.397657 ZQ Calibration : PASS
4866 12:41:51.397976 Jitter Meter : NO K
4867 12:41:51.400385 CBT Training : PASS
4868 12:41:51.403822 Write leveling : PASS
4869 12:41:51.404133 RX DQS gating : PASS
4870 12:41:51.407590 RX DQ/DQS(RDDQC) : PASS
4871 12:41:51.410708 TX DQ/DQS : PASS
4872 12:41:51.411020 RX DATLAT : PASS
4873 12:41:51.414252 RX DQ/DQS(Engine): PASS
4874 12:41:51.417269 TX OE : NO K
4875 12:41:51.417697 All Pass.
4876 12:41:51.417950
4877 12:41:51.418178 CH 0, Rank 1
4878 12:41:51.420421 SW Impedance : PASS
4879 12:41:51.423641 DUTY Scan : NO K
4880 12:41:51.423971 ZQ Calibration : PASS
4881 12:41:51.426970 Jitter Meter : NO K
4882 12:41:51.430433 CBT Training : PASS
4883 12:41:51.430797 Write leveling : PASS
4884 12:41:51.433685 RX DQS gating : PASS
4885 12:41:51.436587 RX DQ/DQS(RDDQC) : PASS
4886 12:41:51.436670 TX DQ/DQS : PASS
4887 12:41:51.440116 RX DATLAT : PASS
4888 12:41:51.443281 RX DQ/DQS(Engine): PASS
4889 12:41:51.443386 TX OE : NO K
4890 12:41:51.443453 All Pass.
4891 12:41:51.446694
4892 12:41:51.446777 CH 1, Rank 0
4893 12:41:51.449941 SW Impedance : PASS
4894 12:41:51.450023 DUTY Scan : NO K
4895 12:41:51.453168 ZQ Calibration : PASS
4896 12:41:51.456928 Jitter Meter : NO K
4897 12:41:51.457012 CBT Training : PASS
4898 12:41:51.459668 Write leveling : PASS
4899 12:41:51.459763 RX DQS gating : PASS
4900 12:41:51.463081 RX DQ/DQS(RDDQC) : PASS
4901 12:41:51.466717 TX DQ/DQS : PASS
4902 12:41:51.466793 RX DATLAT : PASS
4903 12:41:51.469709 RX DQ/DQS(Engine): PASS
4904 12:41:51.473128 TX OE : NO K
4905 12:41:51.473204 All Pass.
4906 12:41:51.473268
4907 12:41:51.473326 CH 1, Rank 1
4908 12:41:51.476401 SW Impedance : PASS
4909 12:41:51.479887 DUTY Scan : NO K
4910 12:41:51.479981 ZQ Calibration : PASS
4911 12:41:51.483299 Jitter Meter : NO K
4912 12:41:51.486653 CBT Training : PASS
4913 12:41:51.486738 Write leveling : PASS
4914 12:41:51.490212 RX DQS gating : PASS
4915 12:41:51.492973 RX DQ/DQS(RDDQC) : PASS
4916 12:41:51.493057 TX DQ/DQS : PASS
4917 12:41:51.496670 RX DATLAT : PASS
4918 12:41:51.499653 RX DQ/DQS(Engine): PASS
4919 12:41:51.499737 TX OE : NO K
4920 12:41:51.499805 All Pass.
4921 12:41:51.503657
4922 12:41:51.503744 DramC Write-DBI off
4923 12:41:51.506613 PER_BANK_REFRESH: Hybrid Mode
4924 12:41:51.506723 TX_TRACKING: ON
4925 12:41:51.516166 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4926 12:41:51.519725 [FAST_K] Save calibration result to emmc
4927 12:41:51.523044 dramc_set_vcore_voltage set vcore to 662500
4928 12:41:51.526107 Read voltage for 933, 3
4929 12:41:51.526191 Vio18 = 0
4930 12:41:51.529720 Vcore = 662500
4931 12:41:51.529804 Vdram = 0
4932 12:41:51.529870 Vddq = 0
4933 12:41:51.529932 Vmddr = 0
4934 12:41:51.536279 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4935 12:41:51.542828 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4936 12:41:51.542916 MEM_TYPE=3, freq_sel=17
4937 12:41:51.546075 sv_algorithm_assistance_LP4_1600
4938 12:41:51.549933 ============ PULL DRAM RESETB DOWN ============
4939 12:41:51.556134 ========== PULL DRAM RESETB DOWN end =========
4940 12:41:51.559693 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4941 12:41:51.562914 ===================================
4942 12:41:51.566294 LPDDR4 DRAM CONFIGURATION
4943 12:41:51.569769 ===================================
4944 12:41:51.569856 EX_ROW_EN[0] = 0x0
4945 12:41:51.572809 EX_ROW_EN[1] = 0x0
4946 12:41:51.572904 LP4Y_EN = 0x0
4947 12:41:51.576182 WORK_FSP = 0x0
4948 12:41:51.576269 WL = 0x3
4949 12:41:51.579567 RL = 0x3
4950 12:41:51.582713 BL = 0x2
4951 12:41:51.582799 RPST = 0x0
4952 12:41:51.586016 RD_PRE = 0x0
4953 12:41:51.586103 WR_PRE = 0x1
4954 12:41:51.589538 WR_PST = 0x0
4955 12:41:51.589624 DBI_WR = 0x0
4956 12:41:51.592294 DBI_RD = 0x0
4957 12:41:51.592380 OTF = 0x1
4958 12:41:51.595956 ===================================
4959 12:41:51.599434 ===================================
4960 12:41:51.602844 ANA top config
4961 12:41:51.605640 ===================================
4962 12:41:51.605728 DLL_ASYNC_EN = 0
4963 12:41:51.609205 ALL_SLAVE_EN = 1
4964 12:41:51.612592 NEW_RANK_MODE = 1
4965 12:41:51.616130 DLL_IDLE_MODE = 1
4966 12:41:51.616217 LP45_APHY_COMB_EN = 1
4967 12:41:51.619368 TX_ODT_DIS = 1
4968 12:41:51.622409 NEW_8X_MODE = 1
4969 12:41:51.625648 ===================================
4970 12:41:51.628932 ===================================
4971 12:41:51.632291 data_rate = 1866
4972 12:41:51.635797 CKR = 1
4973 12:41:51.638792 DQ_P2S_RATIO = 8
4974 12:41:51.642024 ===================================
4975 12:41:51.642126 CA_P2S_RATIO = 8
4976 12:41:51.645466 DQ_CA_OPEN = 0
4977 12:41:51.649143 DQ_SEMI_OPEN = 0
4978 12:41:51.652414 CA_SEMI_OPEN = 0
4979 12:41:51.655729 CA_FULL_RATE = 0
4980 12:41:51.659243 DQ_CKDIV4_EN = 1
4981 12:41:51.659336 CA_CKDIV4_EN = 1
4982 12:41:51.662849 CA_PREDIV_EN = 0
4983 12:41:51.665536 PH8_DLY = 0
4984 12:41:51.669031 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4985 12:41:51.672479 DQ_AAMCK_DIV = 4
4986 12:41:51.672651 CA_AAMCK_DIV = 4
4987 12:41:51.675455 CA_ADMCK_DIV = 4
4988 12:41:51.679148 DQ_TRACK_CA_EN = 0
4989 12:41:51.682104 CA_PICK = 933
4990 12:41:51.685617 CA_MCKIO = 933
4991 12:41:51.688885 MCKIO_SEMI = 0
4992 12:41:51.692107 PLL_FREQ = 3732
4993 12:41:51.692286 DQ_UI_PI_RATIO = 32
4994 12:41:51.695393 CA_UI_PI_RATIO = 0
4995 12:41:51.698743 ===================================
4996 12:41:51.702311 ===================================
4997 12:41:51.705764 memory_type:LPDDR4
4998 12:41:51.708806 GP_NUM : 10
4999 12:41:51.709115 SRAM_EN : 1
5000 12:41:51.712684 MD32_EN : 0
5001 12:41:51.715879 ===================================
5002 12:41:51.718581 [ANA_INIT] >>>>>>>>>>>>>>
5003 12:41:51.722241 <<<<<< [CONFIGURE PHASE]: ANA_TX
5004 12:41:51.725477 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5005 12:41:51.729047 ===================================
5006 12:41:51.729635 data_rate = 1866,PCW = 0X8f00
5007 12:41:51.731874 ===================================
5008 12:41:51.735539 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5009 12:41:51.741900 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5010 12:41:51.748890 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5011 12:41:51.752486 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5012 12:41:51.755711 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5013 12:41:51.758768 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5014 12:41:51.762080 [ANA_INIT] flow start
5015 12:41:51.762515 [ANA_INIT] PLL >>>>>>>>
5016 12:41:51.766033 [ANA_INIT] PLL <<<<<<<<
5017 12:41:51.768968 [ANA_INIT] MIDPI >>>>>>>>
5018 12:41:51.772301 [ANA_INIT] MIDPI <<<<<<<<
5019 12:41:51.772742 [ANA_INIT] DLL >>>>>>>>
5020 12:41:51.775489 [ANA_INIT] flow end
5021 12:41:51.778432 ============ LP4 DIFF to SE enter ============
5022 12:41:51.782379 ============ LP4 DIFF to SE exit ============
5023 12:41:51.785277 [ANA_INIT] <<<<<<<<<<<<<
5024 12:41:51.788511 [Flow] Enable top DCM control >>>>>
5025 12:41:51.791691 [Flow] Enable top DCM control <<<<<
5026 12:41:51.795025 Enable DLL master slave shuffle
5027 12:41:51.801976 ==============================================================
5028 12:41:51.802412 Gating Mode config
5029 12:41:51.808300 ==============================================================
5030 12:41:51.808735 Config description:
5031 12:41:51.818013 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5032 12:41:51.825260 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5033 12:41:51.831691 SELPH_MODE 0: By rank 1: By Phase
5034 12:41:51.835168 ==============================================================
5035 12:41:51.838465 GAT_TRACK_EN = 1
5036 12:41:51.841829 RX_GATING_MODE = 2
5037 12:41:51.845130 RX_GATING_TRACK_MODE = 2
5038 12:41:51.848361 SELPH_MODE = 1
5039 12:41:51.851650 PICG_EARLY_EN = 1
5040 12:41:51.855425 VALID_LAT_VALUE = 1
5041 12:41:51.858293 ==============================================================
5042 12:41:51.861712 Enter into Gating configuration >>>>
5043 12:41:51.865308 Exit from Gating configuration <<<<
5044 12:41:51.868420 Enter into DVFS_PRE_config >>>>>
5045 12:41:51.881500 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5046 12:41:51.884946 Exit from DVFS_PRE_config <<<<<
5047 12:41:51.888136 Enter into PICG configuration >>>>
5048 12:41:51.888568 Exit from PICG configuration <<<<
5049 12:41:51.891608 [RX_INPUT] configuration >>>>>
5050 12:41:51.894980 [RX_INPUT] configuration <<<<<
5051 12:41:51.901543 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5052 12:41:51.904776 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5053 12:41:51.911572 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5054 12:41:51.918337 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5055 12:41:51.925093 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5056 12:41:51.931567 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5057 12:41:51.935117 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5058 12:41:51.937934 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5059 12:41:51.941447 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5060 12:41:51.948252 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5061 12:41:51.951682 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5062 12:41:51.954457 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5063 12:41:51.957835 ===================================
5064 12:41:51.961025 LPDDR4 DRAM CONFIGURATION
5065 12:41:51.964594 ===================================
5066 12:41:51.967826 EX_ROW_EN[0] = 0x0
5067 12:41:51.968379 EX_ROW_EN[1] = 0x0
5068 12:41:51.971262 LP4Y_EN = 0x0
5069 12:41:51.971841 WORK_FSP = 0x0
5070 12:41:51.974924 WL = 0x3
5071 12:41:51.975528 RL = 0x3
5072 12:41:51.977881 BL = 0x2
5073 12:41:51.978338 RPST = 0x0
5074 12:41:51.981238 RD_PRE = 0x0
5075 12:41:51.981671 WR_PRE = 0x1
5076 12:41:51.984445 WR_PST = 0x0
5077 12:41:51.984881 DBI_WR = 0x0
5078 12:41:51.988144 DBI_RD = 0x0
5079 12:41:51.988619 OTF = 0x1
5080 12:41:51.991227 ===================================
5081 12:41:51.997605 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5082 12:41:52.001317 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5083 12:41:52.004129 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5084 12:41:52.008231 ===================================
5085 12:41:52.010895 LPDDR4 DRAM CONFIGURATION
5086 12:41:52.014552 ===================================
5087 12:41:52.018327 EX_ROW_EN[0] = 0x10
5088 12:41:52.018809 EX_ROW_EN[1] = 0x0
5089 12:41:52.021246 LP4Y_EN = 0x0
5090 12:41:52.021720 WORK_FSP = 0x0
5091 12:41:52.024779 WL = 0x3
5092 12:41:52.025203 RL = 0x3
5093 12:41:52.027594 BL = 0x2
5094 12:41:52.028020 RPST = 0x0
5095 12:41:52.031153 RD_PRE = 0x0
5096 12:41:52.031680 WR_PRE = 0x1
5097 12:41:52.034380 WR_PST = 0x0
5098 12:41:52.034824 DBI_WR = 0x0
5099 12:41:52.037717 DBI_RD = 0x0
5100 12:41:52.038143 OTF = 0x1
5101 12:41:52.041084 ===================================
5102 12:41:52.047552 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5103 12:41:52.052013 nWR fixed to 30
5104 12:41:52.055768 [ModeRegInit_LP4] CH0 RK0
5105 12:41:52.056216 [ModeRegInit_LP4] CH0 RK1
5106 12:41:52.058966 [ModeRegInit_LP4] CH1 RK0
5107 12:41:52.062167 [ModeRegInit_LP4] CH1 RK1
5108 12:41:52.062651 match AC timing 9
5109 12:41:52.068466 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5110 12:41:52.071760 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5111 12:41:52.075030 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5112 12:41:52.081675 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5113 12:41:52.085213 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5114 12:41:52.085821 ==
5115 12:41:52.088710 Dram Type= 6, Freq= 0, CH_0, rank 0
5116 12:41:52.091595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5117 12:41:52.092064 ==
5118 12:41:52.098874 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5119 12:41:52.105172 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5120 12:41:52.108534 [CA 0] Center 38 (8~69) winsize 62
5121 12:41:52.111658 [CA 1] Center 38 (8~69) winsize 62
5122 12:41:52.115089 [CA 2] Center 35 (5~66) winsize 62
5123 12:41:52.118399 [CA 3] Center 35 (5~65) winsize 61
5124 12:41:52.122080 [CA 4] Center 34 (4~64) winsize 61
5125 12:41:52.124885 [CA 5] Center 34 (4~64) winsize 61
5126 12:41:52.125388
5127 12:41:52.128267 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5128 12:41:52.128697
5129 12:41:52.131664 [CATrainingPosCal] consider 1 rank data
5130 12:41:52.135072 u2DelayCellTimex100 = 270/100 ps
5131 12:41:52.138419 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5132 12:41:52.141167 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5133 12:41:52.144832 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5134 12:41:52.148429 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5135 12:41:52.151253 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5136 12:41:52.158065 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5137 12:41:52.158509
5138 12:41:52.161216 CA PerBit enable=1, Macro0, CA PI delay=34
5139 12:41:52.161690
5140 12:41:52.164505 [CBTSetCACLKResult] CA Dly = 34
5141 12:41:52.164934 CS Dly: 6 (0~37)
5142 12:41:52.165278 ==
5143 12:41:52.168376 Dram Type= 6, Freq= 0, CH_0, rank 1
5144 12:41:52.171576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5145 12:41:52.174547 ==
5146 12:41:52.177825 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5147 12:41:52.184397 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5148 12:41:52.188121 [CA 0] Center 38 (7~69) winsize 63
5149 12:41:52.191417 [CA 1] Center 38 (8~69) winsize 62
5150 12:41:52.194945 [CA 2] Center 35 (5~66) winsize 62
5151 12:41:52.197613 [CA 3] Center 35 (5~66) winsize 62
5152 12:41:52.201088 [CA 4] Center 34 (3~65) winsize 63
5153 12:41:52.204127 [CA 5] Center 33 (3~64) winsize 62
5154 12:41:52.204778
5155 12:41:52.207585 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5156 12:41:52.208041
5157 12:41:52.210993 [CATrainingPosCal] consider 2 rank data
5158 12:41:52.213983 u2DelayCellTimex100 = 270/100 ps
5159 12:41:52.217916 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5160 12:41:52.220783 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5161 12:41:52.224330 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5162 12:41:52.230597 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5163 12:41:52.234217 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5164 12:41:52.237238 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5165 12:41:52.237546
5166 12:41:52.240456 CA PerBit enable=1, Macro0, CA PI delay=34
5167 12:41:52.240763
5168 12:41:52.244366 [CBTSetCACLKResult] CA Dly = 34
5169 12:41:52.244670 CS Dly: 7 (0~39)
5170 12:41:52.244914
5171 12:41:52.247229 ----->DramcWriteLeveling(PI) begin...
5172 12:41:52.247606 ==
5173 12:41:52.250734 Dram Type= 6, Freq= 0, CH_0, rank 0
5174 12:41:52.257021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5175 12:41:52.257416 ==
5176 12:41:52.260261 Write leveling (Byte 0): 30 => 30
5177 12:41:52.263541 Write leveling (Byte 1): 30 => 30
5178 12:41:52.267081 DramcWriteLeveling(PI) end<-----
5179 12:41:52.267406
5180 12:41:52.267655 ==
5181 12:41:52.270338 Dram Type= 6, Freq= 0, CH_0, rank 0
5182 12:41:52.273679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5183 12:41:52.273987 ==
5184 12:41:52.276673 [Gating] SW mode calibration
5185 12:41:52.283824 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5186 12:41:52.289866 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5187 12:41:52.293292 0 14 0 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
5188 12:41:52.296777 0 14 4 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
5189 12:41:52.303186 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5190 12:41:52.306728 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5191 12:41:52.310232 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5192 12:41:52.316767 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5193 12:41:52.319527 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5194 12:41:52.322973 0 14 28 | B1->B0 | 3434 3131 | 0 0 | (0 1) (0 1)
5195 12:41:52.329927 0 15 0 | B1->B0 | 2f2f 2b2b | 1 0 | (1 1) (0 0)
5196 12:41:52.333310 0 15 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5197 12:41:52.336527 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5198 12:41:52.343080 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5199 12:41:52.346204 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5200 12:41:52.349819 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5201 12:41:52.352685 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5202 12:41:52.360014 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5203 12:41:52.363059 1 0 0 | B1->B0 | 3333 4141 | 0 1 | (0 0) (0 0)
5204 12:41:52.366423 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5205 12:41:52.372679 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5206 12:41:52.376097 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5207 12:41:52.379295 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5208 12:41:52.386186 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5209 12:41:52.389342 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5210 12:41:52.392597 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5211 12:41:52.399474 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5212 12:41:52.402688 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 12:41:52.406351 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 12:41:52.412513 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 12:41:52.415939 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 12:41:52.419712 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 12:41:52.426057 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 12:41:52.429343 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 12:41:52.432447 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 12:41:52.439642 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 12:41:52.443334 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 12:41:52.446328 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 12:41:52.452761 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 12:41:52.455681 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5225 12:41:52.459074 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5226 12:41:52.465612 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5227 12:41:52.469412 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5228 12:41:52.472577 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5229 12:41:52.476054 Total UI for P1: 0, mck2ui 16
5230 12:41:52.479035 best dqsien dly found for B0: ( 1, 2, 30)
5231 12:41:52.485251 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5232 12:41:52.485752 Total UI for P1: 0, mck2ui 16
5233 12:41:52.492166 best dqsien dly found for B1: ( 1, 3, 2)
5234 12:41:52.495652 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5235 12:41:52.498492 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5236 12:41:52.498944
5237 12:41:52.502158 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5238 12:41:52.505192 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5239 12:41:52.508738 [Gating] SW calibration Done
5240 12:41:52.509175 ==
5241 12:41:52.511805 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 12:41:52.515509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 12:41:52.515946 ==
5244 12:41:52.518342 RX Vref Scan: 0
5245 12:41:52.518897
5246 12:41:52.519412 RX Vref 0 -> 0, step: 1
5247 12:41:52.519755
5248 12:41:52.521941 RX Delay -80 -> 252, step: 8
5249 12:41:52.524681 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5250 12:41:52.531829 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5251 12:41:52.534870 iDelay=200, Bit 2, Center 91 (-8 ~ 191) 200
5252 12:41:52.538272 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5253 12:41:52.541607 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5254 12:41:52.544978 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5255 12:41:52.548365 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5256 12:41:52.554856 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5257 12:41:52.558565 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5258 12:41:52.561487 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5259 12:41:52.564661 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5260 12:41:52.567833 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5261 12:41:52.575008 iDelay=200, Bit 12, Center 91 (-8 ~ 191) 200
5262 12:41:52.578117 iDelay=200, Bit 13, Center 91 (-8 ~ 191) 200
5263 12:41:52.581541 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5264 12:41:52.585265 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5265 12:41:52.585778 ==
5266 12:41:52.588309 Dram Type= 6, Freq= 0, CH_0, rank 0
5267 12:41:52.591322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5268 12:41:52.594619 ==
5269 12:41:52.595118 DQS Delay:
5270 12:41:52.595586 DQS0 = 0, DQS1 = 0
5271 12:41:52.598207 DQM Delay:
5272 12:41:52.598764 DQM0 = 97, DQM1 = 86
5273 12:41:52.601023 DQ Delay:
5274 12:41:52.604866 DQ0 =95, DQ1 =103, DQ2 =91, DQ3 =91
5275 12:41:52.607955 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5276 12:41:52.611378 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5277 12:41:52.614805 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5278 12:41:52.615333
5279 12:41:52.615724
5280 12:41:52.616040 ==
5281 12:41:52.618471 Dram Type= 6, Freq= 0, CH_0, rank 0
5282 12:41:52.621419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5283 12:41:52.621871 ==
5284 12:41:52.622212
5285 12:41:52.622520
5286 12:41:52.624989 TX Vref Scan disable
5287 12:41:52.625498 == TX Byte 0 ==
5288 12:41:52.631061 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5289 12:41:52.634452 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5290 12:41:52.635051 == TX Byte 1 ==
5291 12:41:52.640698 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5292 12:41:52.644754 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5293 12:41:52.645182 ==
5294 12:41:52.647659 Dram Type= 6, Freq= 0, CH_0, rank 0
5295 12:41:52.651000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5296 12:41:52.651574 ==
5297 12:41:52.651921
5298 12:41:52.652235
5299 12:41:52.654548 TX Vref Scan disable
5300 12:41:52.657575 == TX Byte 0 ==
5301 12:41:52.661040 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5302 12:41:52.664032 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5303 12:41:52.667830 == TX Byte 1 ==
5304 12:41:52.670796 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5305 12:41:52.674096 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5306 12:41:52.674535
5307 12:41:52.677493 [DATLAT]
5308 12:41:52.678001 Freq=933, CH0 RK0
5309 12:41:52.678493
5310 12:41:52.681159 DATLAT Default: 0xd
5311 12:41:52.681594 0, 0xFFFF, sum = 0
5312 12:41:52.684065 1, 0xFFFF, sum = 0
5313 12:41:52.684500 2, 0xFFFF, sum = 0
5314 12:41:52.687208 3, 0xFFFF, sum = 0
5315 12:41:52.687697 4, 0xFFFF, sum = 0
5316 12:41:52.690659 5, 0xFFFF, sum = 0
5317 12:41:52.691096 6, 0xFFFF, sum = 0
5318 12:41:52.693948 7, 0xFFFF, sum = 0
5319 12:41:52.694384 8, 0xFFFF, sum = 0
5320 12:41:52.697501 9, 0xFFFF, sum = 0
5321 12:41:52.697937 10, 0x0, sum = 1
5322 12:41:52.700909 11, 0x0, sum = 2
5323 12:41:52.701363 12, 0x0, sum = 3
5324 12:41:52.704531 13, 0x0, sum = 4
5325 12:41:52.704968 best_step = 11
5326 12:41:52.705308
5327 12:41:52.705657 ==
5328 12:41:52.707619 Dram Type= 6, Freq= 0, CH_0, rank 0
5329 12:41:52.714193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5330 12:41:52.714648 ==
5331 12:41:52.714994 RX Vref Scan: 1
5332 12:41:52.715320
5333 12:41:52.717552 RX Vref 0 -> 0, step: 1
5334 12:41:52.717986
5335 12:41:52.720833 RX Delay -61 -> 252, step: 4
5336 12:41:52.721301
5337 12:41:52.724163 Set Vref, RX VrefLevel [Byte0]: 55
5338 12:41:52.727324 [Byte1]: 51
5339 12:41:52.727803
5340 12:41:52.730734 Final RX Vref Byte 0 = 55 to rank0
5341 12:41:52.733991 Final RX Vref Byte 1 = 51 to rank0
5342 12:41:52.736983 Final RX Vref Byte 0 = 55 to rank1
5343 12:41:52.740173 Final RX Vref Byte 1 = 51 to rank1==
5344 12:41:52.743963 Dram Type= 6, Freq= 0, CH_0, rank 0
5345 12:41:52.747060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5346 12:41:52.747519 ==
5347 12:41:52.750587 DQS Delay:
5348 12:41:52.751011 DQS0 = 0, DQS1 = 0
5349 12:41:52.753941 DQM Delay:
5350 12:41:52.754365 DQM0 = 96, DQM1 = 88
5351 12:41:52.754701 DQ Delay:
5352 12:41:52.756991 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =92
5353 12:41:52.760227 DQ4 =100, DQ5 =88, DQ6 =106, DQ7 =102
5354 12:41:52.763892 DQ8 =78, DQ9 =76, DQ10 =88, DQ11 =80
5355 12:41:52.767473 DQ12 =96, DQ13 =94, DQ14 =98, DQ15 =98
5356 12:41:52.768003
5357 12:41:52.770587
5358 12:41:52.776611 [DQSOSCAuto] RK0, (LSB)MR18= 0x13fe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 415 ps
5359 12:41:52.779892 CH0 RK0: MR19=504, MR18=13FE
5360 12:41:52.787012 CH0_RK0: MR19=0x504, MR18=0x13FE, DQSOSC=415, MR23=63, INC=62, DEC=41
5361 12:41:52.787475
5362 12:41:52.790190 ----->DramcWriteLeveling(PI) begin...
5363 12:41:52.790619 ==
5364 12:41:52.793114 Dram Type= 6, Freq= 0, CH_0, rank 1
5365 12:41:52.797134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5366 12:41:52.797561 ==
5367 12:41:52.799819 Write leveling (Byte 0): 28 => 28
5368 12:41:52.803284 Write leveling (Byte 1): 28 => 28
5369 12:41:52.806972 DramcWriteLeveling(PI) end<-----
5370 12:41:52.807535
5371 12:41:52.807875 ==
5372 12:41:52.810128 Dram Type= 6, Freq= 0, CH_0, rank 1
5373 12:41:52.813764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5374 12:41:52.814297 ==
5375 12:41:52.816998 [Gating] SW mode calibration
5376 12:41:52.823527 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5377 12:41:52.830140 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5378 12:41:52.833305 0 14 0 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
5379 12:41:52.836833 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5380 12:41:52.843088 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5381 12:41:52.846696 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5382 12:41:52.849989 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5383 12:41:52.857094 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5384 12:41:52.859826 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (1 0)
5385 12:41:52.864056 0 14 28 | B1->B0 | 3333 2e2e | 0 1 | (0 0) (1 0)
5386 12:41:52.870469 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
5387 12:41:52.873698 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5388 12:41:52.876582 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5389 12:41:52.883444 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5390 12:41:52.887048 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5391 12:41:52.889507 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5392 12:41:52.896219 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5393 12:41:52.899957 0 15 28 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
5394 12:41:52.903525 1 0 0 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
5395 12:41:52.910074 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5396 12:41:52.913596 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5397 12:41:52.916369 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5398 12:41:52.923042 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5399 12:41:52.926471 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5400 12:41:52.929322 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5401 12:41:52.936233 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5402 12:41:52.939728 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5403 12:41:52.942848 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 12:41:52.950036 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 12:41:52.953174 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 12:41:52.956711 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 12:41:52.959451 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 12:41:52.966694 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 12:41:52.969824 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 12:41:52.972954 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 12:41:52.979638 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 12:41:52.982979 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 12:41:52.986870 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 12:41:52.993575 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 12:41:52.995999 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 12:41:52.999942 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 12:41:53.006245 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5418 12:41:53.006758 Total UI for P1: 0, mck2ui 16
5419 12:41:53.012883 best dqsien dly found for B0: ( 1, 2, 26)
5420 12:41:53.016048 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5421 12:41:53.019381 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5422 12:41:53.022558 Total UI for P1: 0, mck2ui 16
5423 12:41:53.026225 best dqsien dly found for B1: ( 1, 3, 0)
5424 12:41:53.029128 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5425 12:41:53.032415 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5426 12:41:53.032891
5427 12:41:53.036163 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5428 12:41:53.043199 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5429 12:41:53.043822 [Gating] SW calibration Done
5430 12:41:53.044209 ==
5431 12:41:53.045743 Dram Type= 6, Freq= 0, CH_0, rank 1
5432 12:41:53.052867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5433 12:41:53.053437 ==
5434 12:41:53.054024 RX Vref Scan: 0
5435 12:41:53.054459
5436 12:41:53.056051 RX Vref 0 -> 0, step: 1
5437 12:41:53.056526
5438 12:41:53.059330 RX Delay -80 -> 252, step: 8
5439 12:41:53.062646 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5440 12:41:53.066354 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5441 12:41:53.069286 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5442 12:41:53.072850 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5443 12:41:53.079198 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5444 12:41:53.082271 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5445 12:41:53.085475 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5446 12:41:53.089109 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5447 12:41:53.092036 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5448 12:41:53.095490 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5449 12:41:53.102315 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5450 12:41:53.105715 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5451 12:41:53.108746 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5452 12:41:53.111904 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5453 12:41:53.115665 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5454 12:41:53.122136 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5455 12:41:53.122712 ==
5456 12:41:53.125994 Dram Type= 6, Freq= 0, CH_0, rank 1
5457 12:41:53.128977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5458 12:41:53.129566 ==
5459 12:41:53.129950 DQS Delay:
5460 12:41:53.131993 DQS0 = 0, DQS1 = 0
5461 12:41:53.132471 DQM Delay:
5462 12:41:53.136145 DQM0 = 97, DQM1 = 87
5463 12:41:53.136735 DQ Delay:
5464 12:41:53.139073 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =91
5465 12:41:53.141900 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =103
5466 12:41:53.145653 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =75
5467 12:41:53.149016 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5468 12:41:53.149448
5469 12:41:53.149866
5470 12:41:53.150196 ==
5471 12:41:53.152107 Dram Type= 6, Freq= 0, CH_0, rank 1
5472 12:41:53.155512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5473 12:41:53.155950 ==
5474 12:41:53.158747
5475 12:41:53.159287
5476 12:41:53.159704 TX Vref Scan disable
5477 12:41:53.161618 == TX Byte 0 ==
5478 12:41:53.165174 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5479 12:41:53.168426 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5480 12:41:53.172215 == TX Byte 1 ==
5481 12:41:53.175226 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5482 12:41:53.178999 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5483 12:41:53.179591 ==
5484 12:41:53.181882 Dram Type= 6, Freq= 0, CH_0, rank 1
5485 12:41:53.188727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5486 12:41:53.189273 ==
5487 12:41:53.189624
5488 12:41:53.189948
5489 12:41:53.191969 TX Vref Scan disable
5490 12:41:53.192403 == TX Byte 0 ==
5491 12:41:53.198362 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5492 12:41:53.202192 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5493 12:41:53.202739 == TX Byte 1 ==
5494 12:41:53.208217 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5495 12:41:53.211485 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5496 12:41:53.211923
5497 12:41:53.212270 [DATLAT]
5498 12:41:53.214827 Freq=933, CH0 RK1
5499 12:41:53.215261
5500 12:41:53.215669 DATLAT Default: 0xb
5501 12:41:53.218513 0, 0xFFFF, sum = 0
5502 12:41:53.219085 1, 0xFFFF, sum = 0
5503 12:41:53.221419 2, 0xFFFF, sum = 0
5504 12:41:53.221862 3, 0xFFFF, sum = 0
5505 12:41:53.224794 4, 0xFFFF, sum = 0
5506 12:41:53.225235 5, 0xFFFF, sum = 0
5507 12:41:53.228210 6, 0xFFFF, sum = 0
5508 12:41:53.228762 7, 0xFFFF, sum = 0
5509 12:41:53.231641 8, 0xFFFF, sum = 0
5510 12:41:53.234751 9, 0xFFFF, sum = 0
5511 12:41:53.235287 10, 0x0, sum = 1
5512 12:41:53.235755 11, 0x0, sum = 2
5513 12:41:53.238059 12, 0x0, sum = 3
5514 12:41:53.238592 13, 0x0, sum = 4
5515 12:41:53.241381 best_step = 11
5516 12:41:53.241836
5517 12:41:53.242204 ==
5518 12:41:53.244856 Dram Type= 6, Freq= 0, CH_0, rank 1
5519 12:41:53.248240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5520 12:41:53.248773 ==
5521 12:41:53.251533 RX Vref Scan: 0
5522 12:41:53.251968
5523 12:41:53.252409 RX Vref 0 -> 0, step: 1
5524 12:41:53.252909
5525 12:41:53.254759 RX Delay -61 -> 252, step: 4
5526 12:41:53.261832 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5527 12:41:53.265040 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5528 12:41:53.268895 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5529 12:41:53.271868 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5530 12:41:53.275055 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5531 12:41:53.278395 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5532 12:41:53.285014 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5533 12:41:53.288179 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5534 12:41:53.291322 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5535 12:41:53.294888 iDelay=199, Bit 9, Center 78 (-9 ~ 166) 176
5536 12:41:53.298547 iDelay=199, Bit 10, Center 90 (3 ~ 178) 176
5537 12:41:53.304632 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5538 12:41:53.308281 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5539 12:41:53.311954 iDelay=199, Bit 13, Center 94 (7 ~ 182) 176
5540 12:41:53.314428 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5541 12:41:53.318146 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5542 12:41:53.318628 ==
5543 12:41:53.321388 Dram Type= 6, Freq= 0, CH_0, rank 1
5544 12:41:53.327976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 12:41:53.328558 ==
5546 12:41:53.328941 DQS Delay:
5547 12:41:53.331441 DQS0 = 0, DQS1 = 0
5548 12:41:53.332031 DQM Delay:
5549 12:41:53.335008 DQM0 = 95, DQM1 = 88
5550 12:41:53.335610 DQ Delay:
5551 12:41:53.337970 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5552 12:41:53.341032 DQ4 =94, DQ5 =84, DQ6 =106, DQ7 =102
5553 12:41:53.344306 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =78
5554 12:41:53.347958 DQ12 =94, DQ13 =94, DQ14 =100, DQ15 =94
5555 12:41:53.348527
5556 12:41:53.348913
5557 12:41:53.354184 [DQSOSCAuto] RK1, (LSB)MR18= 0x1806, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 414 ps
5558 12:41:53.357497 CH0 RK1: MR19=505, MR18=1806
5559 12:41:53.364420 CH0_RK1: MR19=0x505, MR18=0x1806, DQSOSC=414, MR23=63, INC=63, DEC=42
5560 12:41:53.367468 [RxdqsGatingPostProcess] freq 933
5561 12:41:53.374188 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5562 12:41:53.374746 best DQS0 dly(2T, 0.5T) = (0, 10)
5563 12:41:53.377311 best DQS1 dly(2T, 0.5T) = (0, 11)
5564 12:41:53.381023 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5565 12:41:53.384296 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5566 12:41:53.387729 best DQS0 dly(2T, 0.5T) = (0, 10)
5567 12:41:53.390764 best DQS1 dly(2T, 0.5T) = (0, 11)
5568 12:41:53.394117 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5569 12:41:53.397367 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5570 12:41:53.400246 Pre-setting of DQS Precalculation
5571 12:41:53.407279 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5572 12:41:53.407746 ==
5573 12:41:53.410753 Dram Type= 6, Freq= 0, CH_1, rank 0
5574 12:41:53.414284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5575 12:41:53.414816 ==
5576 12:41:53.420330 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5577 12:41:53.424106 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5578 12:41:53.427462 [CA 0] Center 36 (6~67) winsize 62
5579 12:41:53.430889 [CA 1] Center 36 (6~67) winsize 62
5580 12:41:53.434211 [CA 2] Center 34 (4~64) winsize 61
5581 12:41:53.437327 [CA 3] Center 33 (3~64) winsize 62
5582 12:41:53.441501 [CA 4] Center 33 (3~64) winsize 62
5583 12:41:53.444357 [CA 5] Center 33 (3~64) winsize 62
5584 12:41:53.444884
5585 12:41:53.448059 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5586 12:41:53.448589
5587 12:41:53.450783 [CATrainingPosCal] consider 1 rank data
5588 12:41:53.454188 u2DelayCellTimex100 = 270/100 ps
5589 12:41:53.457796 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5590 12:41:53.464107 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5591 12:41:53.467707 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5592 12:41:53.470466 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5593 12:41:53.473837 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5594 12:41:53.477615 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5595 12:41:53.478095
5596 12:41:53.480853 CA PerBit enable=1, Macro0, CA PI delay=33
5597 12:41:53.481293
5598 12:41:53.483751 [CBTSetCACLKResult] CA Dly = 33
5599 12:41:53.484189 CS Dly: 4 (0~35)
5600 12:41:53.486973 ==
5601 12:41:53.490838 Dram Type= 6, Freq= 0, CH_1, rank 1
5602 12:41:53.493814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5603 12:41:53.494190 ==
5604 12:41:53.497552 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5605 12:41:53.504021 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5606 12:41:53.508085 [CA 0] Center 36 (6~67) winsize 62
5607 12:41:53.511094 [CA 1] Center 37 (7~67) winsize 61
5608 12:41:53.514139 [CA 2] Center 33 (3~64) winsize 62
5609 12:41:53.517426 [CA 3] Center 33 (2~64) winsize 63
5610 12:41:53.521031 [CA 4] Center 34 (4~64) winsize 61
5611 12:41:53.524566 [CA 5] Center 32 (2~63) winsize 62
5612 12:41:53.525046
5613 12:41:53.527333 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5614 12:41:53.527845
5615 12:41:53.530548 [CATrainingPosCal] consider 2 rank data
5616 12:41:53.534067 u2DelayCellTimex100 = 270/100 ps
5617 12:41:53.537480 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5618 12:41:53.544272 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5619 12:41:53.548061 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5620 12:41:53.550612 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5621 12:41:53.554727 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5622 12:41:53.557448 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5623 12:41:53.558020
5624 12:41:53.560607 CA PerBit enable=1, Macro0, CA PI delay=33
5625 12:41:53.561189
5626 12:41:53.563596 [CBTSetCACLKResult] CA Dly = 33
5627 12:41:53.564077 CS Dly: 5 (0~37)
5628 12:41:53.566814
5629 12:41:53.570594 ----->DramcWriteLeveling(PI) begin...
5630 12:41:53.571189 ==
5631 12:41:53.573923 Dram Type= 6, Freq= 0, CH_1, rank 0
5632 12:41:53.576853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5633 12:41:53.577367 ==
5634 12:41:53.580215 Write leveling (Byte 0): 28 => 28
5635 12:41:53.583971 Write leveling (Byte 1): 29 => 29
5636 12:41:53.587181 DramcWriteLeveling(PI) end<-----
5637 12:41:53.587703
5638 12:41:53.588085 ==
5639 12:41:53.590025 Dram Type= 6, Freq= 0, CH_1, rank 0
5640 12:41:53.593626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5641 12:41:53.594338 ==
5642 12:41:53.597257 [Gating] SW mode calibration
5643 12:41:53.603398 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5644 12:41:53.610014 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5645 12:41:53.613606 0 14 0 | B1->B0 | 2e2e 3131 | 0 0 | (0 0) (0 0)
5646 12:41:53.616416 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5647 12:41:53.623113 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5648 12:41:53.626631 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5649 12:41:53.630072 0 14 16 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
5650 12:41:53.636224 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5651 12:41:53.639829 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5652 12:41:53.642804 0 14 28 | B1->B0 | 3333 3131 | 0 0 | (0 0) (1 0)
5653 12:41:53.649550 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5654 12:41:53.653044 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5655 12:41:53.657130 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5656 12:41:53.662875 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5657 12:41:53.666690 0 15 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5658 12:41:53.670040 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5659 12:41:53.676014 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5660 12:41:53.679576 0 15 28 | B1->B0 | 2e2e 2e2e | 1 0 | (0 0) (0 0)
5661 12:41:53.682709 1 0 0 | B1->B0 | 4444 3c3c | 0 0 | (0 0) (0 0)
5662 12:41:53.689940 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5663 12:41:53.692526 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5664 12:41:53.695687 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5665 12:41:53.702822 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5666 12:41:53.705995 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5667 12:41:53.709689 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5668 12:41:53.716386 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5669 12:41:53.719596 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 12:41:53.722332 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 12:41:53.729331 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 12:41:53.732610 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 12:41:53.735919 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 12:41:53.739668 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 12:41:53.746029 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 12:41:53.749456 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 12:41:53.753301 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 12:41:53.759193 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 12:41:53.762686 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 12:41:53.765457 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5681 12:41:53.772715 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 12:41:53.775641 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5683 12:41:53.778867 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5684 12:41:53.785473 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5685 12:41:53.789284 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5686 12:41:53.792227 Total UI for P1: 0, mck2ui 16
5687 12:41:53.795856 best dqsien dly found for B0: ( 1, 2, 26)
5688 12:41:53.799115 Total UI for P1: 0, mck2ui 16
5689 12:41:53.802409 best dqsien dly found for B1: ( 1, 2, 28)
5690 12:41:53.805471 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5691 12:41:53.809139 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5692 12:41:53.809566
5693 12:41:53.812017 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5694 12:41:53.815659 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5695 12:41:53.819414 [Gating] SW calibration Done
5696 12:41:53.819946 ==
5697 12:41:53.822906 Dram Type= 6, Freq= 0, CH_1, rank 0
5698 12:41:53.828600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5699 12:41:53.829128 ==
5700 12:41:53.829471 RX Vref Scan: 0
5701 12:41:53.829788
5702 12:41:53.832554 RX Vref 0 -> 0, step: 1
5703 12:41:53.833089
5704 12:41:53.835639 RX Delay -80 -> 252, step: 8
5705 12:41:53.838469 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5706 12:41:53.841905 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5707 12:41:53.845180 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5708 12:41:53.848916 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5709 12:41:53.852133 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5710 12:41:53.858857 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5711 12:41:53.862653 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5712 12:41:53.865301 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5713 12:41:53.868594 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5714 12:41:53.872232 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5715 12:41:53.878629 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5716 12:41:53.881893 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5717 12:41:53.885430 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5718 12:41:53.888627 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5719 12:41:53.891790 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5720 12:41:53.895434 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5721 12:41:53.898886 ==
5722 12:41:53.899478 Dram Type= 6, Freq= 0, CH_1, rank 0
5723 12:41:53.905109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5724 12:41:53.905654 ==
5725 12:41:53.906012 DQS Delay:
5726 12:41:53.908705 DQS0 = 0, DQS1 = 0
5727 12:41:53.909141 DQM Delay:
5728 12:41:53.911829 DQM0 = 95, DQM1 = 88
5729 12:41:53.912262 DQ Delay:
5730 12:41:53.915728 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95
5731 12:41:53.918869 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =91
5732 12:41:53.922009 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5733 12:41:53.925404 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5734 12:41:53.926010
5735 12:41:53.926391
5736 12:41:53.926752 ==
5737 12:41:53.928763 Dram Type= 6, Freq= 0, CH_1, rank 0
5738 12:41:53.931538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5739 12:41:53.931978 ==
5740 12:41:53.932324
5741 12:41:53.932643
5742 12:41:53.935118 TX Vref Scan disable
5743 12:41:53.938581 == TX Byte 0 ==
5744 12:41:53.941748 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5745 12:41:53.945203 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5746 12:41:53.948484 == TX Byte 1 ==
5747 12:41:53.951842 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5748 12:41:53.954987 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5749 12:41:53.955570 ==
5750 12:41:53.958141 Dram Type= 6, Freq= 0, CH_1, rank 0
5751 12:41:53.961732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5752 12:41:53.965163 ==
5753 12:41:53.965606
5754 12:41:53.966052
5755 12:41:53.966470 TX Vref Scan disable
5756 12:41:53.968620 == TX Byte 0 ==
5757 12:41:53.971885 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5758 12:41:53.978100 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5759 12:41:53.978545 == TX Byte 1 ==
5760 12:41:53.981527 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5761 12:41:53.988181 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5762 12:41:53.988670
5763 12:41:53.989239 [DATLAT]
5764 12:41:53.989804 Freq=933, CH1 RK0
5765 12:41:53.990340
5766 12:41:53.991430 DATLAT Default: 0xd
5767 12:41:53.994794 0, 0xFFFF, sum = 0
5768 12:41:53.995229 1, 0xFFFF, sum = 0
5769 12:41:53.998495 2, 0xFFFF, sum = 0
5770 12:41:53.998928 3, 0xFFFF, sum = 0
5771 12:41:54.001336 4, 0xFFFF, sum = 0
5772 12:41:54.001768 5, 0xFFFF, sum = 0
5773 12:41:54.004616 6, 0xFFFF, sum = 0
5774 12:41:54.005060 7, 0xFFFF, sum = 0
5775 12:41:54.007810 8, 0xFFFF, sum = 0
5776 12:41:54.008244 9, 0xFFFF, sum = 0
5777 12:41:54.011177 10, 0x0, sum = 1
5778 12:41:54.011660 11, 0x0, sum = 2
5779 12:41:54.014680 12, 0x0, sum = 3
5780 12:41:54.015115 13, 0x0, sum = 4
5781 12:41:54.015510 best_step = 11
5782 12:41:54.018091
5783 12:41:54.018520 ==
5784 12:41:54.020992 Dram Type= 6, Freq= 0, CH_1, rank 0
5785 12:41:54.024174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5786 12:41:54.024610 ==
5787 12:41:54.024955 RX Vref Scan: 1
5788 12:41:54.025279
5789 12:41:54.028052 RX Vref 0 -> 0, step: 1
5790 12:41:54.028488
5791 12:41:54.031441 RX Delay -61 -> 252, step: 4
5792 12:41:54.031875
5793 12:41:54.034053 Set Vref, RX VrefLevel [Byte0]: 52
5794 12:41:54.037794 [Byte1]: 51
5795 12:41:54.040591
5796 12:41:54.041022 Final RX Vref Byte 0 = 52 to rank0
5797 12:41:54.044320 Final RX Vref Byte 1 = 51 to rank0
5798 12:41:54.047752 Final RX Vref Byte 0 = 52 to rank1
5799 12:41:54.051000 Final RX Vref Byte 1 = 51 to rank1==
5800 12:41:54.054347 Dram Type= 6, Freq= 0, CH_1, rank 0
5801 12:41:54.060545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5802 12:41:54.060983 ==
5803 12:41:54.061328 DQS Delay:
5804 12:41:54.064063 DQS0 = 0, DQS1 = 0
5805 12:41:54.064499 DQM Delay:
5806 12:41:54.064898 DQM0 = 97, DQM1 = 90
5807 12:41:54.067465 DQ Delay:
5808 12:41:54.070811 DQ0 =102, DQ1 =90, DQ2 =86, DQ3 =98
5809 12:41:54.073831 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5810 12:41:54.077358 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =86
5811 12:41:54.080473 DQ12 =98, DQ13 =96, DQ14 =96, DQ15 =94
5812 12:41:54.080908
5813 12:41:54.081252
5814 12:41:54.087075 [DQSOSCAuto] RK0, (LSB)MR18= 0x10ec, (MSB)MR19= 0x504, tDQSOscB0 = 428 ps tDQSOscB1 = 416 ps
5815 12:41:54.090845 CH1 RK0: MR19=504, MR18=10EC
5816 12:41:54.097652 CH1_RK0: MR19=0x504, MR18=0x10EC, DQSOSC=416, MR23=63, INC=62, DEC=41
5817 12:41:54.098223
5818 12:41:54.100299 ----->DramcWriteLeveling(PI) begin...
5819 12:41:54.100715 ==
5820 12:41:54.103833 Dram Type= 6, Freq= 0, CH_1, rank 1
5821 12:41:54.107229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5822 12:41:54.107708 ==
5823 12:41:54.110637 Write leveling (Byte 0): 28 => 28
5824 12:41:54.113782 Write leveling (Byte 1): 28 => 28
5825 12:41:54.116890 DramcWriteLeveling(PI) end<-----
5826 12:41:54.117296
5827 12:41:54.117638 ==
5828 12:41:54.120815 Dram Type= 6, Freq= 0, CH_1, rank 1
5829 12:41:54.123670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5830 12:41:54.127053 ==
5831 12:41:54.127675 [Gating] SW mode calibration
5832 12:41:54.133446 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5833 12:41:54.140634 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5834 12:41:54.143422 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5835 12:41:54.150340 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5836 12:41:54.153567 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5837 12:41:54.156983 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5838 12:41:54.163303 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5839 12:41:54.167059 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5840 12:41:54.169782 0 14 24 | B1->B0 | 3232 2e2e | 1 1 | (1 1) (1 0)
5841 12:41:54.176416 0 14 28 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
5842 12:41:54.179351 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5843 12:41:54.183178 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5844 12:41:54.189587 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5845 12:41:54.192810 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5846 12:41:54.196138 0 15 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5847 12:41:54.202629 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5848 12:41:54.205989 0 15 24 | B1->B0 | 2626 3636 | 0 0 | (0 0) (0 0)
5849 12:41:54.209521 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
5850 12:41:54.216136 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5851 12:41:54.219307 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5852 12:41:54.222580 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5853 12:41:54.229286 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5854 12:41:54.232576 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5855 12:41:54.235640 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5856 12:41:54.242812 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5857 12:41:54.245877 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5858 12:41:54.248874 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 12:41:54.252880 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 12:41:54.259310 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 12:41:54.262313 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 12:41:54.265894 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 12:41:54.272410 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 12:41:54.276437 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 12:41:54.278786 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 12:41:54.286117 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 12:41:54.288915 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 12:41:54.292309 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 12:41:54.298985 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 12:41:54.302509 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5871 12:41:54.305296 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5872 12:41:54.312110 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5873 12:41:54.315504 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5874 12:41:54.318772 Total UI for P1: 0, mck2ui 16
5875 12:41:54.322123 best dqsien dly found for B0: ( 1, 2, 24)
5876 12:41:54.325510 Total UI for P1: 0, mck2ui 16
5877 12:41:54.328784 best dqsien dly found for B1: ( 1, 2, 26)
5878 12:41:54.332324 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5879 12:41:54.335920 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5880 12:41:54.335994
5881 12:41:54.338544 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5882 12:41:54.342081 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5883 12:41:54.345579 [Gating] SW calibration Done
5884 12:41:54.345655 ==
5885 12:41:54.348532 Dram Type= 6, Freq= 0, CH_1, rank 1
5886 12:41:54.351846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5887 12:41:54.355747 ==
5888 12:41:54.355824 RX Vref Scan: 0
5889 12:41:54.355900
5890 12:41:54.358550 RX Vref 0 -> 0, step: 1
5891 12:41:54.358623
5892 12:41:54.362048 RX Delay -80 -> 252, step: 8
5893 12:41:54.365124 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5894 12:41:54.368837 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5895 12:41:54.371801 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5896 12:41:54.375195 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5897 12:41:54.378783 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5898 12:41:54.385042 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5899 12:41:54.389173 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5900 12:41:54.392322 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5901 12:41:54.394970 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5902 12:41:54.398300 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5903 12:41:54.401678 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5904 12:41:54.408711 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5905 12:41:54.412176 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5906 12:41:54.414926 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5907 12:41:54.418227 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5908 12:41:54.421558 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5909 12:41:54.421659 ==
5910 12:41:54.425332 Dram Type= 6, Freq= 0, CH_1, rank 1
5911 12:41:54.432093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5912 12:41:54.432173 ==
5913 12:41:54.432243 DQS Delay:
5914 12:41:54.435437 DQS0 = 0, DQS1 = 0
5915 12:41:54.435533 DQM Delay:
5916 12:41:54.435623 DQM0 = 95, DQM1 = 89
5917 12:41:54.438135 DQ Delay:
5918 12:41:54.441875 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =95
5919 12:41:54.445289 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =91
5920 12:41:54.448592 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5921 12:41:54.451752 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =95
5922 12:41:54.451825
5923 12:41:54.451888
5924 12:41:54.451955 ==
5925 12:41:54.454968 Dram Type= 6, Freq= 0, CH_1, rank 1
5926 12:41:54.458807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5927 12:41:54.458910 ==
5928 12:41:54.459013
5929 12:41:54.459100
5930 12:41:54.462080 TX Vref Scan disable
5931 12:41:54.465481 == TX Byte 0 ==
5932 12:41:54.468643 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5933 12:41:54.471677 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5934 12:41:54.471753 == TX Byte 1 ==
5935 12:41:54.478286 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5936 12:41:54.481370 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5937 12:41:54.481474 ==
5938 12:41:54.484948 Dram Type= 6, Freq= 0, CH_1, rank 1
5939 12:41:54.487829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5940 12:41:54.491466 ==
5941 12:41:54.491537
5942 12:41:54.491600
5943 12:41:54.491659 TX Vref Scan disable
5944 12:41:54.494836 == TX Byte 0 ==
5945 12:41:54.498475 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5946 12:41:54.504505 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5947 12:41:54.504582 == TX Byte 1 ==
5948 12:41:54.508257 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5949 12:41:54.514874 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5950 12:41:54.514947
5951 12:41:54.515010 [DATLAT]
5952 12:41:54.515070 Freq=933, CH1 RK1
5953 12:41:54.515129
5954 12:41:54.517799 DATLAT Default: 0xb
5955 12:41:54.517892 0, 0xFFFF, sum = 0
5956 12:41:54.521766 1, 0xFFFF, sum = 0
5957 12:41:54.521864 2, 0xFFFF, sum = 0
5958 12:41:54.524904 3, 0xFFFF, sum = 0
5959 12:41:54.524992 4, 0xFFFF, sum = 0
5960 12:41:54.528380 5, 0xFFFF, sum = 0
5961 12:41:54.531600 6, 0xFFFF, sum = 0
5962 12:41:54.531677 7, 0xFFFF, sum = 0
5963 12:41:54.534470 8, 0xFFFF, sum = 0
5964 12:41:54.534569 9, 0xFFFF, sum = 0
5965 12:41:54.538161 10, 0x0, sum = 1
5966 12:41:54.538258 11, 0x0, sum = 2
5967 12:41:54.541580 12, 0x0, sum = 3
5968 12:41:54.541676 13, 0x0, sum = 4
5969 12:41:54.541766 best_step = 11
5970 12:41:54.541851
5971 12:41:54.544717 ==
5972 12:41:54.547869 Dram Type= 6, Freq= 0, CH_1, rank 1
5973 12:41:54.551381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5974 12:41:54.551477 ==
5975 12:41:54.551540 RX Vref Scan: 0
5976 12:41:54.551598
5977 12:41:54.554823 RX Vref 0 -> 0, step: 1
5978 12:41:54.554913
5979 12:41:54.557671 RX Delay -61 -> 252, step: 4
5980 12:41:54.561035 iDelay=199, Bit 0, Center 96 (7 ~ 186) 180
5981 12:41:54.568212 iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184
5982 12:41:54.571095 iDelay=199, Bit 2, Center 84 (-9 ~ 178) 188
5983 12:41:54.574406 iDelay=199, Bit 3, Center 92 (3 ~ 182) 180
5984 12:41:54.577667 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5985 12:41:54.580892 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5986 12:41:54.587601 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5987 12:41:54.590842 iDelay=199, Bit 7, Center 90 (-1 ~ 182) 184
5988 12:41:54.594558 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5989 12:41:54.597580 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5990 12:41:54.601172 iDelay=199, Bit 10, Center 90 (-1 ~ 182) 184
5991 12:41:54.603892 iDelay=199, Bit 11, Center 84 (-5 ~ 174) 180
5992 12:41:54.610882 iDelay=199, Bit 12, Center 98 (11 ~ 186) 176
5993 12:41:54.613903 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
5994 12:41:54.617346 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
5995 12:41:54.620901 iDelay=199, Bit 15, Center 100 (11 ~ 190) 180
5996 12:41:54.620985 ==
5997 12:41:54.624106 Dram Type= 6, Freq= 0, CH_1, rank 1
5998 12:41:54.630754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5999 12:41:54.630863 ==
6000 12:41:54.630966 DQS Delay:
6001 12:41:54.631058 DQS0 = 0, DQS1 = 0
6002 12:41:54.633957 DQM Delay:
6003 12:41:54.634040 DQM0 = 94, DQM1 = 91
6004 12:41:54.637109 DQ Delay:
6005 12:41:54.640654 DQ0 =96, DQ1 =90, DQ2 =84, DQ3 =92
6006 12:41:54.644108 DQ4 =94, DQ5 =106, DQ6 =104, DQ7 =90
6007 12:41:54.647250 DQ8 =80, DQ9 =80, DQ10 =90, DQ11 =84
6008 12:41:54.650336 DQ12 =98, DQ13 =98, DQ14 =100, DQ15 =100
6009 12:41:54.650405
6010 12:41:54.650467
6011 12:41:54.656973 [DQSOSCAuto] RK1, (LSB)MR18= 0xf18, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
6012 12:41:54.660769 CH1 RK1: MR19=505, MR18=F18
6013 12:41:54.667151 CH1_RK1: MR19=0x505, MR18=0xF18, DQSOSC=414, MR23=63, INC=63, DEC=42
6014 12:41:54.670722 [RxdqsGatingPostProcess] freq 933
6015 12:41:54.674159 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6016 12:41:54.677480 best DQS0 dly(2T, 0.5T) = (0, 10)
6017 12:41:54.680701 best DQS1 dly(2T, 0.5T) = (0, 10)
6018 12:41:54.683471 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6019 12:41:54.686972 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6020 12:41:54.690515 best DQS0 dly(2T, 0.5T) = (0, 10)
6021 12:41:54.693704 best DQS1 dly(2T, 0.5T) = (0, 10)
6022 12:41:54.697167 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6023 12:41:54.700168 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6024 12:41:54.703476 Pre-setting of DQS Precalculation
6025 12:41:54.707294 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6026 12:41:54.713674 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6027 12:41:54.723762 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6028 12:41:54.723849
6029 12:41:54.723935
6030 12:41:54.727551 [Calibration Summary] 1866 Mbps
6031 12:41:54.727638 CH 0, Rank 0
6032 12:41:54.730374 SW Impedance : PASS
6033 12:41:54.730460 DUTY Scan : NO K
6034 12:41:54.733590 ZQ Calibration : PASS
6035 12:41:54.736840 Jitter Meter : NO K
6036 12:41:54.736927 CBT Training : PASS
6037 12:41:54.740597 Write leveling : PASS
6038 12:41:54.740683 RX DQS gating : PASS
6039 12:41:54.743740 RX DQ/DQS(RDDQC) : PASS
6040 12:41:54.746964 TX DQ/DQS : PASS
6041 12:41:54.747050 RX DATLAT : PASS
6042 12:41:54.750136 RX DQ/DQS(Engine): PASS
6043 12:41:54.753351 TX OE : NO K
6044 12:41:54.753437 All Pass.
6045 12:41:54.753522
6046 12:41:54.753603 CH 0, Rank 1
6047 12:41:54.757046 SW Impedance : PASS
6048 12:41:54.759829 DUTY Scan : NO K
6049 12:41:54.759915 ZQ Calibration : PASS
6050 12:41:54.763459 Jitter Meter : NO K
6051 12:41:54.766596 CBT Training : PASS
6052 12:41:54.766679 Write leveling : PASS
6053 12:41:54.770165 RX DQS gating : PASS
6054 12:41:54.773677 RX DQ/DQS(RDDQC) : PASS
6055 12:41:54.773760 TX DQ/DQS : PASS
6056 12:41:54.776540 RX DATLAT : PASS
6057 12:41:54.780066 RX DQ/DQS(Engine): PASS
6058 12:41:54.780149 TX OE : NO K
6059 12:41:54.780216 All Pass.
6060 12:41:54.783476
6061 12:41:54.783559 CH 1, Rank 0
6062 12:41:54.786671 SW Impedance : PASS
6063 12:41:54.786787 DUTY Scan : NO K
6064 12:41:54.790044 ZQ Calibration : PASS
6065 12:41:54.793110 Jitter Meter : NO K
6066 12:41:54.793193 CBT Training : PASS
6067 12:41:54.796441 Write leveling : PASS
6068 12:41:54.796524 RX DQS gating : PASS
6069 12:41:54.800051 RX DQ/DQS(RDDQC) : PASS
6070 12:41:54.803252 TX DQ/DQS : PASS
6071 12:41:54.803337 RX DATLAT : PASS
6072 12:41:54.806570 RX DQ/DQS(Engine): PASS
6073 12:41:54.809927 TX OE : NO K
6074 12:41:54.810011 All Pass.
6075 12:41:54.810077
6076 12:41:54.810138 CH 1, Rank 1
6077 12:41:54.813301 SW Impedance : PASS
6078 12:41:54.816504 DUTY Scan : NO K
6079 12:41:54.816588 ZQ Calibration : PASS
6080 12:41:54.819963 Jitter Meter : NO K
6081 12:41:54.823485 CBT Training : PASS
6082 12:41:54.823569 Write leveling : PASS
6083 12:41:54.826328 RX DQS gating : PASS
6084 12:41:54.830279 RX DQ/DQS(RDDQC) : PASS
6085 12:41:54.830363 TX DQ/DQS : PASS
6086 12:41:54.833418 RX DATLAT : PASS
6087 12:41:54.836614 RX DQ/DQS(Engine): PASS
6088 12:41:54.836697 TX OE : NO K
6089 12:41:54.836764 All Pass.
6090 12:41:54.839787
6091 12:41:54.839870 DramC Write-DBI off
6092 12:41:54.842905 PER_BANK_REFRESH: Hybrid Mode
6093 12:41:54.842988 TX_TRACKING: ON
6094 12:41:54.853092 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6095 12:41:54.856516 [FAST_K] Save calibration result to emmc
6096 12:41:54.859738 dramc_set_vcore_voltage set vcore to 650000
6097 12:41:54.863417 Read voltage for 400, 6
6098 12:41:54.863500 Vio18 = 0
6099 12:41:54.866161 Vcore = 650000
6100 12:41:54.866244 Vdram = 0
6101 12:41:54.866310 Vddq = 0
6102 12:41:54.866371 Vmddr = 0
6103 12:41:54.873215 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6104 12:41:54.879470 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6105 12:41:54.879581 MEM_TYPE=3, freq_sel=20
6106 12:41:54.882937 sv_algorithm_assistance_LP4_800
6107 12:41:54.886443 ============ PULL DRAM RESETB DOWN ============
6108 12:41:54.892822 ========== PULL DRAM RESETB DOWN end =========
6109 12:41:54.896252 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6110 12:41:54.899739 ===================================
6111 12:41:54.902922 LPDDR4 DRAM CONFIGURATION
6112 12:41:54.906649 ===================================
6113 12:41:54.906733 EX_ROW_EN[0] = 0x0
6114 12:41:54.909431 EX_ROW_EN[1] = 0x0
6115 12:41:54.909514 LP4Y_EN = 0x0
6116 12:41:54.913119 WORK_FSP = 0x0
6117 12:41:54.913202 WL = 0x2
6118 12:41:54.916304 RL = 0x2
6119 12:41:54.916388 BL = 0x2
6120 12:41:54.919486 RPST = 0x0
6121 12:41:54.923083 RD_PRE = 0x0
6122 12:41:54.923167 WR_PRE = 0x1
6123 12:41:54.926445 WR_PST = 0x0
6124 12:41:54.926528 DBI_WR = 0x0
6125 12:41:54.929265 DBI_RD = 0x0
6126 12:41:54.929348 OTF = 0x1
6127 12:41:54.932575 ===================================
6128 12:41:54.935786 ===================================
6129 12:41:54.939501 ANA top config
6130 12:41:54.942880 ===================================
6131 12:41:54.942964 DLL_ASYNC_EN = 0
6132 12:41:54.945945 ALL_SLAVE_EN = 1
6133 12:41:54.949314 NEW_RANK_MODE = 1
6134 12:41:54.952592 DLL_IDLE_MODE = 1
6135 12:41:54.952676 LP45_APHY_COMB_EN = 1
6136 12:41:54.956147 TX_ODT_DIS = 1
6137 12:41:54.959184 NEW_8X_MODE = 1
6138 12:41:54.962734 ===================================
6139 12:41:54.966085 ===================================
6140 12:41:54.969839 data_rate = 800
6141 12:41:54.972952 CKR = 1
6142 12:41:54.973024 DQ_P2S_RATIO = 4
6143 12:41:54.975850 ===================================
6144 12:41:54.979280 CA_P2S_RATIO = 4
6145 12:41:54.982824 DQ_CA_OPEN = 0
6146 12:41:54.986375 DQ_SEMI_OPEN = 1
6147 12:41:54.989415 CA_SEMI_OPEN = 1
6148 12:41:54.992960 CA_FULL_RATE = 0
6149 12:41:54.993061 DQ_CKDIV4_EN = 0
6150 12:41:54.996257 CA_CKDIV4_EN = 1
6151 12:41:54.999264 CA_PREDIV_EN = 0
6152 12:41:55.003228 PH8_DLY = 0
6153 12:41:55.005878 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6154 12:41:55.009311 DQ_AAMCK_DIV = 0
6155 12:41:55.009410 CA_AAMCK_DIV = 0
6156 12:41:55.012479 CA_ADMCK_DIV = 4
6157 12:41:55.016022 DQ_TRACK_CA_EN = 0
6158 12:41:55.019240 CA_PICK = 800
6159 12:41:55.022417 CA_MCKIO = 400
6160 12:41:55.025680 MCKIO_SEMI = 400
6161 12:41:55.029032 PLL_FREQ = 3016
6162 12:41:55.029110 DQ_UI_PI_RATIO = 32
6163 12:41:55.032779 CA_UI_PI_RATIO = 32
6164 12:41:55.035528 ===================================
6165 12:41:55.038965 ===================================
6166 12:41:55.042559 memory_type:LPDDR4
6167 12:41:55.046299 GP_NUM : 10
6168 12:41:55.046399 SRAM_EN : 1
6169 12:41:55.048984 MD32_EN : 0
6170 12:41:55.052339 ===================================
6171 12:41:55.056173 [ANA_INIT] >>>>>>>>>>>>>>
6172 12:41:55.056251 <<<<<< [CONFIGURE PHASE]: ANA_TX
6173 12:41:55.059320 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6174 12:41:55.062611 ===================================
6175 12:41:55.065548 data_rate = 800,PCW = 0X7400
6176 12:41:55.069156 ===================================
6177 12:41:55.072638 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6178 12:41:55.079067 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6179 12:41:55.088776 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6180 12:41:55.095522 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6181 12:41:55.098700 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6182 12:41:55.102081 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6183 12:41:55.102159 [ANA_INIT] flow start
6184 12:41:55.105760 [ANA_INIT] PLL >>>>>>>>
6185 12:41:55.109428 [ANA_INIT] PLL <<<<<<<<
6186 12:41:55.111964 [ANA_INIT] MIDPI >>>>>>>>
6187 12:41:55.112039 [ANA_INIT] MIDPI <<<<<<<<
6188 12:41:55.115465 [ANA_INIT] DLL >>>>>>>>
6189 12:41:55.118987 [ANA_INIT] flow end
6190 12:41:55.122195 ============ LP4 DIFF to SE enter ============
6191 12:41:55.125591 ============ LP4 DIFF to SE exit ============
6192 12:41:55.128853 [ANA_INIT] <<<<<<<<<<<<<
6193 12:41:55.131764 [Flow] Enable top DCM control >>>>>
6194 12:41:55.135251 [Flow] Enable top DCM control <<<<<
6195 12:41:55.138482 Enable DLL master slave shuffle
6196 12:41:55.141797 ==============================================================
6197 12:41:55.145256 Gating Mode config
6198 12:41:55.148487 ==============================================================
6199 12:41:55.152063 Config description:
6200 12:41:55.161756 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6201 12:41:55.168828 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6202 12:41:55.171871 SELPH_MODE 0: By rank 1: By Phase
6203 12:41:55.178928 ==============================================================
6204 12:41:55.182063 GAT_TRACK_EN = 0
6205 12:41:55.185550 RX_GATING_MODE = 2
6206 12:41:55.188379 RX_GATING_TRACK_MODE = 2
6207 12:41:55.191672 SELPH_MODE = 1
6208 12:41:55.194879 PICG_EARLY_EN = 1
6209 12:41:55.198250 VALID_LAT_VALUE = 1
6210 12:41:55.201424 ==============================================================
6211 12:41:55.204875 Enter into Gating configuration >>>>
6212 12:41:55.208586 Exit from Gating configuration <<<<
6213 12:41:55.211578 Enter into DVFS_PRE_config >>>>>
6214 12:41:55.221987 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6215 12:41:55.225444 Exit from DVFS_PRE_config <<<<<
6216 12:41:55.229065 Enter into PICG configuration >>>>
6217 12:41:55.231494 Exit from PICG configuration <<<<
6218 12:41:55.234859 [RX_INPUT] configuration >>>>>
6219 12:41:55.238342 [RX_INPUT] configuration <<<<<
6220 12:41:55.245063 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6221 12:41:55.248390 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6222 12:41:55.254749 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6223 12:41:55.261481 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6224 12:41:55.268237 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6225 12:41:55.275029 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6226 12:41:55.278166 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6227 12:41:55.281326 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6228 12:41:55.284876 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6229 12:41:55.291225 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6230 12:41:55.294437 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6231 12:41:55.298580 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6232 12:41:55.301422 ===================================
6233 12:41:55.304259 LPDDR4 DRAM CONFIGURATION
6234 12:41:55.308119 ===================================
6235 12:41:55.308214 EX_ROW_EN[0] = 0x0
6236 12:41:55.311402 EX_ROW_EN[1] = 0x0
6237 12:41:55.311504 LP4Y_EN = 0x0
6238 12:41:55.314655 WORK_FSP = 0x0
6239 12:41:55.317825 WL = 0x2
6240 12:41:55.317907 RL = 0x2
6241 12:41:55.321169 BL = 0x2
6242 12:41:55.321251 RPST = 0x0
6243 12:41:55.324361 RD_PRE = 0x0
6244 12:41:55.324443 WR_PRE = 0x1
6245 12:41:55.327765 WR_PST = 0x0
6246 12:41:55.327848 DBI_WR = 0x0
6247 12:41:55.331210 DBI_RD = 0x0
6248 12:41:55.331293 OTF = 0x1
6249 12:41:55.334306 ===================================
6250 12:41:55.337892 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6251 12:41:55.344490 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6252 12:41:55.348043 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6253 12:41:55.351291 ===================================
6254 12:41:55.354558 LPDDR4 DRAM CONFIGURATION
6255 12:41:55.357866 ===================================
6256 12:41:55.357949 EX_ROW_EN[0] = 0x10
6257 12:41:55.361504 EX_ROW_EN[1] = 0x0
6258 12:41:55.361592 LP4Y_EN = 0x0
6259 12:41:55.364829 WORK_FSP = 0x0
6260 12:41:55.364904 WL = 0x2
6261 12:41:55.367783 RL = 0x2
6262 12:41:55.367855 BL = 0x2
6263 12:41:55.370978 RPST = 0x0
6264 12:41:55.371074 RD_PRE = 0x0
6265 12:41:55.374835 WR_PRE = 0x1
6266 12:41:55.378003 WR_PST = 0x0
6267 12:41:55.378102 DBI_WR = 0x0
6268 12:41:55.380940 DBI_RD = 0x0
6269 12:41:55.381027 OTF = 0x1
6270 12:41:55.384451 ===================================
6271 12:41:55.390716 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6272 12:41:55.394729 nWR fixed to 30
6273 12:41:55.397655 [ModeRegInit_LP4] CH0 RK0
6274 12:41:55.397758 [ModeRegInit_LP4] CH0 RK1
6275 12:41:55.401261 [ModeRegInit_LP4] CH1 RK0
6276 12:41:55.404333 [ModeRegInit_LP4] CH1 RK1
6277 12:41:55.404412 match AC timing 19
6278 12:41:55.411071 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6279 12:41:55.414527 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6280 12:41:55.417676 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6281 12:41:55.424396 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6282 12:41:55.427715 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6283 12:41:55.427796 ==
6284 12:41:55.431497 Dram Type= 6, Freq= 0, CH_0, rank 0
6285 12:41:55.434150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6286 12:41:55.434231 ==
6287 12:41:55.440961 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6288 12:41:55.448066 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6289 12:41:55.450813 [CA 0] Center 36 (8~64) winsize 57
6290 12:41:55.454319 [CA 1] Center 36 (8~64) winsize 57
6291 12:41:55.457762 [CA 2] Center 36 (8~64) winsize 57
6292 12:41:55.461128 [CA 3] Center 36 (8~64) winsize 57
6293 12:41:55.461207 [CA 4] Center 36 (8~64) winsize 57
6294 12:41:55.464509 [CA 5] Center 36 (8~64) winsize 57
6295 12:41:55.464590
6296 12:41:55.470592 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6297 12:41:55.470675
6298 12:41:55.474303 [CATrainingPosCal] consider 1 rank data
6299 12:41:55.477501 u2DelayCellTimex100 = 270/100 ps
6300 12:41:55.480863 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 12:41:55.483834 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 12:41:55.487326 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 12:41:55.490918 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 12:41:55.494282 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 12:41:55.497509 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 12:41:55.497594
6307 12:41:55.500588 CA PerBit enable=1, Macro0, CA PI delay=36
6308 12:41:55.500672
6309 12:41:55.504002 [CBTSetCACLKResult] CA Dly = 36
6310 12:41:55.507585 CS Dly: 1 (0~32)
6311 12:41:55.507660 ==
6312 12:41:55.510795 Dram Type= 6, Freq= 0, CH_0, rank 1
6313 12:41:55.513910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 12:41:55.513995 ==
6315 12:41:55.520573 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6316 12:41:55.523715 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6317 12:41:55.527170 [CA 0] Center 36 (8~64) winsize 57
6318 12:41:55.530727 [CA 1] Center 36 (8~64) winsize 57
6319 12:41:55.534168 [CA 2] Center 36 (8~64) winsize 57
6320 12:41:55.537263 [CA 3] Center 36 (8~64) winsize 57
6321 12:41:55.540524 [CA 4] Center 36 (8~64) winsize 57
6322 12:41:55.543936 [CA 5] Center 36 (8~64) winsize 57
6323 12:41:55.544040
6324 12:41:55.547871 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6325 12:41:55.547946
6326 12:41:55.550837 [CATrainingPosCal] consider 2 rank data
6327 12:41:55.554228 u2DelayCellTimex100 = 270/100 ps
6328 12:41:55.557298 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6329 12:41:55.560448 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6330 12:41:55.567088 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6331 12:41:55.570832 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6332 12:41:55.573794 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6333 12:41:55.577009 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6334 12:41:55.577081
6335 12:41:55.580242 CA PerBit enable=1, Macro0, CA PI delay=36
6336 12:41:55.580345
6337 12:41:55.584042 [CBTSetCACLKResult] CA Dly = 36
6338 12:41:55.584117 CS Dly: 1 (0~32)
6339 12:41:55.584186
6340 12:41:55.587103 ----->DramcWriteLeveling(PI) begin...
6341 12:41:55.590537 ==
6342 12:41:55.593636 Dram Type= 6, Freq= 0, CH_0, rank 0
6343 12:41:55.597249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6344 12:41:55.597353 ==
6345 12:41:55.600706 Write leveling (Byte 0): 40 => 8
6346 12:41:55.604109 Write leveling (Byte 1): 32 => 0
6347 12:41:55.604212 DramcWriteLeveling(PI) end<-----
6348 12:41:55.607095
6349 12:41:55.607172 ==
6350 12:41:55.610600 Dram Type= 6, Freq= 0, CH_0, rank 0
6351 12:41:55.613924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6352 12:41:55.614002 ==
6353 12:41:55.616793 [Gating] SW mode calibration
6354 12:41:55.623791 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6355 12:41:55.627051 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6356 12:41:55.634257 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6357 12:41:55.636693 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6358 12:41:55.640172 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6359 12:41:55.647207 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6360 12:41:55.650327 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6361 12:41:55.653436 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6362 12:41:55.660093 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6363 12:41:55.663581 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6364 12:41:55.667011 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6365 12:41:55.669803 Total UI for P1: 0, mck2ui 16
6366 12:41:55.673129 best dqsien dly found for B0: ( 0, 14, 24)
6367 12:41:55.676521 Total UI for P1: 0, mck2ui 16
6368 12:41:55.679750 best dqsien dly found for B1: ( 0, 14, 24)
6369 12:41:55.683539 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6370 12:41:55.686834 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6371 12:41:55.690017
6372 12:41:55.693163 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6373 12:41:55.696584 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6374 12:41:55.700019 [Gating] SW calibration Done
6375 12:41:55.700095 ==
6376 12:41:55.703097 Dram Type= 6, Freq= 0, CH_0, rank 0
6377 12:41:55.706633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6378 12:41:55.706709 ==
6379 12:41:55.706777 RX Vref Scan: 0
6380 12:41:55.706837
6381 12:41:55.709753 RX Vref 0 -> 0, step: 1
6382 12:41:55.709829
6383 12:41:55.713090 RX Delay -410 -> 252, step: 16
6384 12:41:55.716836 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6385 12:41:55.723245 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6386 12:41:55.726623 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6387 12:41:55.729433 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6388 12:41:55.733418 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6389 12:41:55.739553 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6390 12:41:55.742942 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6391 12:41:55.746392 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6392 12:41:55.749581 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6393 12:41:55.756007 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6394 12:41:55.759402 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6395 12:41:55.762699 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6396 12:41:55.766032 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6397 12:41:55.773128 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6398 12:41:55.776083 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6399 12:41:55.779180 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6400 12:41:55.779279 ==
6401 12:41:55.783070 Dram Type= 6, Freq= 0, CH_0, rank 0
6402 12:41:55.789221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6403 12:41:55.789297 ==
6404 12:41:55.789365 DQS Delay:
6405 12:41:55.792562 DQS0 = 35, DQS1 = 51
6406 12:41:55.792660 DQM Delay:
6407 12:41:55.792725 DQM0 = 7, DQM1 = 10
6408 12:41:55.795780 DQ Delay:
6409 12:41:55.799316 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6410 12:41:55.799460 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6411 12:41:55.802301 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6412 12:41:55.805765 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6413 12:41:55.805867
6414 12:41:55.805949
6415 12:41:55.808852 ==
6416 12:41:55.812811 Dram Type= 6, Freq= 0, CH_0, rank 0
6417 12:41:55.816027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6418 12:41:55.816107 ==
6419 12:41:55.816196
6420 12:41:55.816275
6421 12:41:55.819546 TX Vref Scan disable
6422 12:41:55.819624 == TX Byte 0 ==
6423 12:41:55.822269 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6424 12:41:55.829061 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6425 12:41:55.829142 == TX Byte 1 ==
6426 12:41:55.832525 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6427 12:41:55.838827 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6428 12:41:55.838932 ==
6429 12:41:55.842621 Dram Type= 6, Freq= 0, CH_0, rank 0
6430 12:41:55.846000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6431 12:41:55.846081 ==
6432 12:41:55.846165
6433 12:41:55.846265
6434 12:41:55.848819 TX Vref Scan disable
6435 12:41:55.848895 == TX Byte 0 ==
6436 12:41:55.852263 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6437 12:41:55.859018 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6438 12:41:55.859101 == TX Byte 1 ==
6439 12:41:55.862477 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6440 12:41:55.868824 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6441 12:41:55.868905
6442 12:41:55.868988 [DATLAT]
6443 12:41:55.872686 Freq=400, CH0 RK0
6444 12:41:55.872766
6445 12:41:55.872864 DATLAT Default: 0xf
6446 12:41:55.875962 0, 0xFFFF, sum = 0
6447 12:41:55.876042 1, 0xFFFF, sum = 0
6448 12:41:55.879055 2, 0xFFFF, sum = 0
6449 12:41:55.879161 3, 0xFFFF, sum = 0
6450 12:41:55.882254 4, 0xFFFF, sum = 0
6451 12:41:55.882334 5, 0xFFFF, sum = 0
6452 12:41:55.885952 6, 0xFFFF, sum = 0
6453 12:41:55.886037 7, 0xFFFF, sum = 0
6454 12:41:55.888855 8, 0xFFFF, sum = 0
6455 12:41:55.888937 9, 0xFFFF, sum = 0
6456 12:41:55.892042 10, 0xFFFF, sum = 0
6457 12:41:55.892150 11, 0xFFFF, sum = 0
6458 12:41:55.895615 12, 0xFFFF, sum = 0
6459 12:41:55.895694 13, 0x0, sum = 1
6460 12:41:55.899097 14, 0x0, sum = 2
6461 12:41:55.899205 15, 0x0, sum = 3
6462 12:41:55.902132 16, 0x0, sum = 4
6463 12:41:55.902211 best_step = 14
6464 12:41:55.902298
6465 12:41:55.902377 ==
6466 12:41:55.905506 Dram Type= 6, Freq= 0, CH_0, rank 0
6467 12:41:55.912050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6468 12:41:55.912132 ==
6469 12:41:55.912214 RX Vref Scan: 1
6470 12:41:55.912297
6471 12:41:55.915467 RX Vref 0 -> 0, step: 1
6472 12:41:55.915545
6473 12:41:55.918364 RX Delay -343 -> 252, step: 8
6474 12:41:55.918446
6475 12:41:55.922044 Set Vref, RX VrefLevel [Byte0]: 55
6476 12:41:55.925543 [Byte1]: 51
6477 12:41:55.925645
6478 12:41:55.928518 Final RX Vref Byte 0 = 55 to rank0
6479 12:41:55.931985 Final RX Vref Byte 1 = 51 to rank0
6480 12:41:55.934868 Final RX Vref Byte 0 = 55 to rank1
6481 12:41:55.938748 Final RX Vref Byte 1 = 51 to rank1==
6482 12:41:55.942175 Dram Type= 6, Freq= 0, CH_0, rank 0
6483 12:41:55.948442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6484 12:41:55.948526 ==
6485 12:41:55.948610 DQS Delay:
6486 12:41:55.948690 DQS0 = 44, DQS1 = 60
6487 12:41:55.951560 DQM Delay:
6488 12:41:55.951637 DQM0 = 11, DQM1 = 14
6489 12:41:55.955125 DQ Delay:
6490 12:41:55.958523 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6491 12:41:55.958625 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6492 12:41:55.961536 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6493 12:41:55.964874 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6494 12:41:55.964954
6495 12:41:55.968169
6496 12:41:55.974846 [DQSOSCAuto] RK0, (LSB)MR18= 0x7c49, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 394 ps
6497 12:41:55.978025 CH0 RK0: MR19=C0C, MR18=7C49
6498 12:41:55.984879 CH0_RK0: MR19=0xC0C, MR18=0x7C49, DQSOSC=394, MR23=63, INC=380, DEC=253
6499 12:41:55.984956 ==
6500 12:41:55.988501 Dram Type= 6, Freq= 0, CH_0, rank 1
6501 12:41:55.992096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6502 12:41:55.992198 ==
6503 12:41:55.994936 [Gating] SW mode calibration
6504 12:41:56.001811 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6505 12:41:56.008136 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6506 12:41:56.011669 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6507 12:41:56.015152 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6508 12:41:56.018061 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6509 12:41:56.024723 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6510 12:41:56.028373 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6511 12:41:56.031611 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6512 12:41:56.038044 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6513 12:41:56.041698 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6514 12:41:56.044899 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6515 12:41:56.048401 Total UI for P1: 0, mck2ui 16
6516 12:41:56.051536 best dqsien dly found for B0: ( 0, 14, 24)
6517 12:41:56.054484 Total UI for P1: 0, mck2ui 16
6518 12:41:56.058054 best dqsien dly found for B1: ( 0, 14, 24)
6519 12:41:56.061464 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6520 12:41:56.067874 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6521 12:41:56.067948
6522 12:41:56.071861 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6523 12:41:56.074742 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6524 12:41:56.078108 [Gating] SW calibration Done
6525 12:41:56.078206 ==
6526 12:41:56.080925 Dram Type= 6, Freq= 0, CH_0, rank 1
6527 12:41:56.084617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6528 12:41:56.084715 ==
6529 12:41:56.087955 RX Vref Scan: 0
6530 12:41:56.088033
6531 12:41:56.088094 RX Vref 0 -> 0, step: 1
6532 12:41:56.088153
6533 12:41:56.091214 RX Delay -410 -> 252, step: 16
6534 12:41:56.094354 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6535 12:41:56.101071 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6536 12:41:56.104310 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6537 12:41:56.107658 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6538 12:41:56.111270 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6539 12:41:56.117895 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6540 12:41:56.120762 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6541 12:41:56.124235 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6542 12:41:56.127323 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6543 12:41:56.134292 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6544 12:41:56.137669 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6545 12:41:56.140641 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6546 12:41:56.144049 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6547 12:41:56.150839 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6548 12:41:56.153977 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6549 12:41:56.157488 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6550 12:41:56.157587 ==
6551 12:41:56.161076 Dram Type= 6, Freq= 0, CH_0, rank 1
6552 12:41:56.167602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6553 12:41:56.167704 ==
6554 12:41:56.167797 DQS Delay:
6555 12:41:56.171174 DQS0 = 35, DQS1 = 51
6556 12:41:56.171271 DQM Delay:
6557 12:41:56.171369 DQM0 = 4, DQM1 = 10
6558 12:41:56.174358 DQ Delay:
6559 12:41:56.177384 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6560 12:41:56.177461 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6561 12:41:56.180793 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6562 12:41:56.184059 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6563 12:41:56.184134
6564 12:41:56.184196
6565 12:41:56.187294 ==
6566 12:41:56.191048 Dram Type= 6, Freq= 0, CH_0, rank 1
6567 12:41:56.193736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6568 12:41:56.193843 ==
6569 12:41:56.193934
6570 12:41:56.194027
6571 12:41:56.197215 TX Vref Scan disable
6572 12:41:56.197312 == TX Byte 0 ==
6573 12:41:56.200653 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6574 12:41:56.207336 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6575 12:41:56.207474 == TX Byte 1 ==
6576 12:41:56.210675 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6577 12:41:56.217021 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6578 12:41:56.217121 ==
6579 12:41:56.220229 Dram Type= 6, Freq= 0, CH_0, rank 1
6580 12:41:56.224101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6581 12:41:56.224174 ==
6582 12:41:56.224237
6583 12:41:56.224301
6584 12:41:56.226937 TX Vref Scan disable
6585 12:41:56.227007 == TX Byte 0 ==
6586 12:41:56.230331 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6587 12:41:56.236871 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6588 12:41:56.236972 == TX Byte 1 ==
6589 12:41:56.240493 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6590 12:41:56.247260 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6591 12:41:56.247389
6592 12:41:56.247457 [DATLAT]
6593 12:41:56.247519 Freq=400, CH0 RK1
6594 12:41:56.247579
6595 12:41:56.250422 DATLAT Default: 0xe
6596 12:41:56.253775 0, 0xFFFF, sum = 0
6597 12:41:56.253851 1, 0xFFFF, sum = 0
6598 12:41:56.256985 2, 0xFFFF, sum = 0
6599 12:41:56.257060 3, 0xFFFF, sum = 0
6600 12:41:56.260285 4, 0xFFFF, sum = 0
6601 12:41:56.260360 5, 0xFFFF, sum = 0
6602 12:41:56.263496 6, 0xFFFF, sum = 0
6603 12:41:56.263609 7, 0xFFFF, sum = 0
6604 12:41:56.267123 8, 0xFFFF, sum = 0
6605 12:41:56.267229 9, 0xFFFF, sum = 0
6606 12:41:56.269964 10, 0xFFFF, sum = 0
6607 12:41:56.270065 11, 0xFFFF, sum = 0
6608 12:41:56.273574 12, 0xFFFF, sum = 0
6609 12:41:56.273673 13, 0x0, sum = 1
6610 12:41:56.276678 14, 0x0, sum = 2
6611 12:41:56.276749 15, 0x0, sum = 3
6612 12:41:56.280296 16, 0x0, sum = 4
6613 12:41:56.280368 best_step = 14
6614 12:41:56.280428
6615 12:41:56.280494 ==
6616 12:41:56.283503 Dram Type= 6, Freq= 0, CH_0, rank 1
6617 12:41:56.286853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6618 12:41:56.290190 ==
6619 12:41:56.290306 RX Vref Scan: 0
6620 12:41:56.290411
6621 12:41:56.293444 RX Vref 0 -> 0, step: 1
6622 12:41:56.293519
6623 12:41:56.296678 RX Delay -343 -> 252, step: 8
6624 12:41:56.303275 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6625 12:41:56.306710 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6626 12:41:56.309922 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6627 12:41:56.313100 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6628 12:41:56.319581 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6629 12:41:56.323203 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6630 12:41:56.326379 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6631 12:41:56.329885 iDelay=217, Bit 7, Center -24 (-263 ~ 216) 480
6632 12:41:56.336577 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6633 12:41:56.339968 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6634 12:41:56.342856 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6635 12:41:56.346629 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6636 12:41:56.353141 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6637 12:41:56.356570 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6638 12:41:56.359762 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6639 12:41:56.363280 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6640 12:41:56.363387 ==
6641 12:41:56.366351 Dram Type= 6, Freq= 0, CH_0, rank 1
6642 12:41:56.372854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6643 12:41:56.372938 ==
6644 12:41:56.373003 DQS Delay:
6645 12:41:56.376139 DQS0 = 48, DQS1 = 60
6646 12:41:56.376226 DQM Delay:
6647 12:41:56.379569 DQM0 = 13, DQM1 = 14
6648 12:41:56.379652 DQ Delay:
6649 12:41:56.382925 DQ0 =16, DQ1 =12, DQ2 =8, DQ3 =12
6650 12:41:56.386165 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =24
6651 12:41:56.389229 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =4
6652 12:41:56.392567 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6653 12:41:56.392651
6654 12:41:56.392718
6655 12:41:56.399165 [DQSOSCAuto] RK1, (LSB)MR18= 0x8c5e, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 392 ps
6656 12:41:56.402565 CH0 RK1: MR19=C0C, MR18=8C5E
6657 12:41:56.409428 CH0_RK1: MR19=0xC0C, MR18=0x8C5E, DQSOSC=392, MR23=63, INC=384, DEC=256
6658 12:41:56.412548 [RxdqsGatingPostProcess] freq 400
6659 12:41:56.419259 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6660 12:41:56.419344 best DQS0 dly(2T, 0.5T) = (0, 10)
6661 12:41:56.423125 best DQS1 dly(2T, 0.5T) = (0, 10)
6662 12:41:56.425473 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6663 12:41:56.428823 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6664 12:41:56.432495 best DQS0 dly(2T, 0.5T) = (0, 10)
6665 12:41:56.436049 best DQS1 dly(2T, 0.5T) = (0, 10)
6666 12:41:56.438781 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6667 12:41:56.442374 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6668 12:41:56.445635 Pre-setting of DQS Precalculation
6669 12:41:56.449166 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6670 12:41:56.452494 ==
6671 12:41:56.455505 Dram Type= 6, Freq= 0, CH_1, rank 0
6672 12:41:56.458786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6673 12:41:56.458870 ==
6674 12:41:56.462195 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6675 12:41:56.469061 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6676 12:41:56.472146 [CA 0] Center 36 (8~64) winsize 57
6677 12:41:56.475606 [CA 1] Center 36 (8~64) winsize 57
6678 12:41:56.479107 [CA 2] Center 36 (8~64) winsize 57
6679 12:41:56.482108 [CA 3] Center 36 (8~64) winsize 57
6680 12:41:56.485725 [CA 4] Center 36 (8~64) winsize 57
6681 12:41:56.489189 [CA 5] Center 36 (8~64) winsize 57
6682 12:41:56.489273
6683 12:41:56.492270 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6684 12:41:56.492355
6685 12:41:56.495462 [CATrainingPosCal] consider 1 rank data
6686 12:41:56.499207 u2DelayCellTimex100 = 270/100 ps
6687 12:41:56.502097 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 12:41:56.505319 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 12:41:56.508841 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 12:41:56.512081 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 12:41:56.518489 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 12:41:56.521935 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 12:41:56.522039
6694 12:41:56.525602 CA PerBit enable=1, Macro0, CA PI delay=36
6695 12:41:56.525675
6696 12:41:56.528524 [CBTSetCACLKResult] CA Dly = 36
6697 12:41:56.528596 CS Dly: 1 (0~32)
6698 12:41:56.528659 ==
6699 12:41:56.531824 Dram Type= 6, Freq= 0, CH_1, rank 1
6700 12:41:56.538362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 12:41:56.538440 ==
6702 12:41:56.542391 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6703 12:41:56.548766 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6704 12:41:56.551840 [CA 0] Center 36 (8~64) winsize 57
6705 12:41:56.555274 [CA 1] Center 36 (8~64) winsize 57
6706 12:41:56.558642 [CA 2] Center 36 (8~64) winsize 57
6707 12:41:56.561691 [CA 3] Center 36 (8~64) winsize 57
6708 12:41:56.565615 [CA 4] Center 36 (8~64) winsize 57
6709 12:41:56.569031 [CA 5] Center 36 (8~64) winsize 57
6710 12:41:56.569104
6711 12:41:56.572118 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6712 12:41:56.572190
6713 12:41:56.575073 [CATrainingPosCal] consider 2 rank data
6714 12:41:56.578442 u2DelayCellTimex100 = 270/100 ps
6715 12:41:56.581638 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6716 12:41:56.585410 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6717 12:41:56.588609 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6718 12:41:56.591885 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6719 12:41:56.594981 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6720 12:41:56.598405 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6721 12:41:56.598483
6722 12:41:56.605326 CA PerBit enable=1, Macro0, CA PI delay=36
6723 12:41:56.605429
6724 12:41:56.605522 [CBTSetCACLKResult] CA Dly = 36
6725 12:41:56.608196 CS Dly: 1 (0~32)
6726 12:41:56.608297
6727 12:41:56.611607 ----->DramcWriteLeveling(PI) begin...
6728 12:41:56.611685 ==
6729 12:41:56.615112 Dram Type= 6, Freq= 0, CH_1, rank 0
6730 12:41:56.618241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6731 12:41:56.618339 ==
6732 12:41:56.621427 Write leveling (Byte 0): 40 => 8
6733 12:41:56.625064 Write leveling (Byte 1): 40 => 8
6734 12:41:56.628217 DramcWriteLeveling(PI) end<-----
6735 12:41:56.628347
6736 12:41:56.628498 ==
6737 12:41:56.631460 Dram Type= 6, Freq= 0, CH_1, rank 0
6738 12:41:56.635112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6739 12:41:56.637950 ==
6740 12:41:56.638051 [Gating] SW mode calibration
6741 12:41:56.648002 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6742 12:41:56.651509 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6743 12:41:56.654799 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6744 12:41:56.661863 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6745 12:41:56.664597 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6746 12:41:56.668206 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6747 12:41:56.674625 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6748 12:41:56.678274 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6749 12:41:56.681651 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6750 12:41:56.687712 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6751 12:41:56.691534 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6752 12:41:56.694415 Total UI for P1: 0, mck2ui 16
6753 12:41:56.697756 best dqsien dly found for B0: ( 0, 14, 24)
6754 12:41:56.701029 Total UI for P1: 0, mck2ui 16
6755 12:41:56.704492 best dqsien dly found for B1: ( 0, 14, 24)
6756 12:41:56.707469 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6757 12:41:56.711071 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6758 12:41:56.711176
6759 12:41:56.714290 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6760 12:41:56.717622 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6761 12:41:56.720994 [Gating] SW calibration Done
6762 12:41:56.721116 ==
6763 12:41:56.724560 Dram Type= 6, Freq= 0, CH_1, rank 0
6764 12:41:56.727647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6765 12:41:56.730873 ==
6766 12:41:56.730953 RX Vref Scan: 0
6767 12:41:56.731048
6768 12:41:56.734099 RX Vref 0 -> 0, step: 1
6769 12:41:56.734201
6770 12:41:56.737683 RX Delay -410 -> 252, step: 16
6771 12:41:56.740616 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6772 12:41:56.744112 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6773 12:41:56.747563 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6774 12:41:56.754256 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6775 12:41:56.757263 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6776 12:41:56.760620 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6777 12:41:56.764121 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6778 12:41:56.770506 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6779 12:41:56.773706 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6780 12:41:56.777389 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6781 12:41:56.780560 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6782 12:41:56.787558 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6783 12:41:56.790766 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6784 12:41:56.794188 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6785 12:41:56.801004 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6786 12:41:56.804189 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6787 12:41:56.804292 ==
6788 12:41:56.807519 Dram Type= 6, Freq= 0, CH_1, rank 0
6789 12:41:56.810435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6790 12:41:56.810522 ==
6791 12:41:56.813806 DQS Delay:
6792 12:41:56.813905 DQS0 = 51, DQS1 = 59
6793 12:41:56.813995 DQM Delay:
6794 12:41:56.817055 DQM0 = 19, DQM1 = 16
6795 12:41:56.817157 DQ Delay:
6796 12:41:56.820451 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6797 12:41:56.823532 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6798 12:41:56.826770 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6799 12:41:56.830133 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6800 12:41:56.830232
6801 12:41:56.830325
6802 12:41:56.830412 ==
6803 12:41:56.833830 Dram Type= 6, Freq= 0, CH_1, rank 0
6804 12:41:56.840128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6805 12:41:56.840206 ==
6806 12:41:56.840270
6807 12:41:56.840329
6808 12:41:56.840390 TX Vref Scan disable
6809 12:41:56.843377 == TX Byte 0 ==
6810 12:41:56.847024 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6811 12:41:56.850045 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6812 12:41:56.853308 == TX Byte 1 ==
6813 12:41:56.856882 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6814 12:41:56.860107 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6815 12:41:56.860178 ==
6816 12:41:56.863175 Dram Type= 6, Freq= 0, CH_1, rank 0
6817 12:41:56.870043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6818 12:41:56.870146 ==
6819 12:41:56.870237
6820 12:41:56.870325
6821 12:41:56.870423 TX Vref Scan disable
6822 12:41:56.873203 == TX Byte 0 ==
6823 12:41:56.876355 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6824 12:41:56.879965 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6825 12:41:56.883095 == TX Byte 1 ==
6826 12:41:56.886411 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6827 12:41:56.889966 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6828 12:41:56.890070
6829 12:41:56.893413 [DATLAT]
6830 12:41:56.893511 Freq=400, CH1 RK0
6831 12:41:56.893601
6832 12:41:56.896714 DATLAT Default: 0xf
6833 12:41:56.896815 0, 0xFFFF, sum = 0
6834 12:41:56.899664 1, 0xFFFF, sum = 0
6835 12:41:56.899767 2, 0xFFFF, sum = 0
6836 12:41:56.903141 3, 0xFFFF, sum = 0
6837 12:41:56.903243 4, 0xFFFF, sum = 0
6838 12:41:56.906401 5, 0xFFFF, sum = 0
6839 12:41:56.906475 6, 0xFFFF, sum = 0
6840 12:41:56.909790 7, 0xFFFF, sum = 0
6841 12:41:56.909892 8, 0xFFFF, sum = 0
6842 12:41:56.912830 9, 0xFFFF, sum = 0
6843 12:41:56.916576 10, 0xFFFF, sum = 0
6844 12:41:56.916677 11, 0xFFFF, sum = 0
6845 12:41:56.919707 12, 0xFFFF, sum = 0
6846 12:41:56.919783 13, 0x0, sum = 1
6847 12:41:56.923109 14, 0x0, sum = 2
6848 12:41:56.923208 15, 0x0, sum = 3
6849 12:41:56.926488 16, 0x0, sum = 4
6850 12:41:56.926560 best_step = 14
6851 12:41:56.926623
6852 12:41:56.926681 ==
6853 12:41:56.929225 Dram Type= 6, Freq= 0, CH_1, rank 0
6854 12:41:56.932600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6855 12:41:56.932701 ==
6856 12:41:56.936279 RX Vref Scan: 1
6857 12:41:56.936380
6858 12:41:56.939320 RX Vref 0 -> 0, step: 1
6859 12:41:56.939447
6860 12:41:56.939508 RX Delay -359 -> 252, step: 8
6861 12:41:56.939596
6862 12:41:56.942884 Set Vref, RX VrefLevel [Byte0]: 52
6863 12:41:56.946124 [Byte1]: 51
6864 12:41:56.951408
6865 12:41:56.951511 Final RX Vref Byte 0 = 52 to rank0
6866 12:41:56.954880 Final RX Vref Byte 1 = 51 to rank0
6867 12:41:56.958487 Final RX Vref Byte 0 = 52 to rank1
6868 12:41:56.961262 Final RX Vref Byte 1 = 51 to rank1==
6869 12:41:56.965197 Dram Type= 6, Freq= 0, CH_1, rank 0
6870 12:41:56.971654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6871 12:41:56.971729 ==
6872 12:41:56.971791 DQS Delay:
6873 12:41:56.974407 DQS0 = 48, DQS1 = 60
6874 12:41:56.974502 DQM Delay:
6875 12:41:56.974591 DQM0 = 12, DQM1 = 13
6876 12:41:56.978102 DQ Delay:
6877 12:41:56.981383 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6878 12:41:56.984688 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
6879 12:41:56.984788 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6880 12:41:56.988233 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6881 12:41:56.991559
6882 12:41:56.991636
6883 12:41:56.997966 [DQSOSCAuto] RK0, (LSB)MR18= 0x8128, (MSB)MR19= 0xc0c, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
6884 12:41:57.001077 CH1 RK0: MR19=C0C, MR18=8128
6885 12:41:57.007939 CH1_RK0: MR19=0xC0C, MR18=0x8128, DQSOSC=393, MR23=63, INC=382, DEC=254
6886 12:41:57.008024 ==
6887 12:41:57.011331 Dram Type= 6, Freq= 0, CH_1, rank 1
6888 12:41:57.014611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6889 12:41:57.014694 ==
6890 12:41:57.017940 [Gating] SW mode calibration
6891 12:41:57.024416 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6892 12:41:57.031187 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6893 12:41:57.034243 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6894 12:41:57.037669 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6895 12:41:57.044229 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6896 12:41:57.047860 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6897 12:41:57.051026 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6898 12:41:57.057406 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6899 12:41:57.060569 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6900 12:41:57.064091 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6901 12:41:57.070708 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6902 12:41:57.070791 Total UI for P1: 0, mck2ui 16
6903 12:41:57.077311 best dqsien dly found for B0: ( 0, 14, 24)
6904 12:41:57.077395 Total UI for P1: 0, mck2ui 16
6905 12:41:57.080782 best dqsien dly found for B1: ( 0, 14, 24)
6906 12:41:57.087458 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6907 12:41:57.090879 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6908 12:41:57.090962
6909 12:41:57.094484 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6910 12:41:57.097600 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6911 12:41:57.101368 [Gating] SW calibration Done
6912 12:41:57.101450 ==
6913 12:41:57.104078 Dram Type= 6, Freq= 0, CH_1, rank 1
6914 12:41:57.108035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6915 12:41:57.108117 ==
6916 12:41:57.110533 RX Vref Scan: 0
6917 12:41:57.110615
6918 12:41:57.110681 RX Vref 0 -> 0, step: 1
6919 12:41:57.110740
6920 12:41:57.114007 RX Delay -410 -> 252, step: 16
6921 12:41:57.120388 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6922 12:41:57.123900 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6923 12:41:57.126946 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6924 12:41:57.130302 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6925 12:41:57.136839 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6926 12:41:57.140811 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6927 12:41:57.143726 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6928 12:41:57.147119 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6929 12:41:57.150651 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6930 12:41:57.156998 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6931 12:41:57.160473 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6932 12:41:57.164071 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6933 12:41:57.170627 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6934 12:41:57.174073 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6935 12:41:57.176716 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6936 12:41:57.180575 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6937 12:41:57.180661 ==
6938 12:41:57.184318 Dram Type= 6, Freq= 0, CH_1, rank 1
6939 12:41:57.190653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6940 12:41:57.190740 ==
6941 12:41:57.190842 DQS Delay:
6942 12:41:57.193462 DQS0 = 51, DQS1 = 51
6943 12:41:57.193548 DQM Delay:
6944 12:41:57.196754 DQM0 = 17, DQM1 = 11
6945 12:41:57.196839 DQ Delay:
6946 12:41:57.200017 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6947 12:41:57.203540 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6948 12:41:57.207030 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6949 12:41:57.210088 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6950 12:41:57.210172
6951 12:41:57.210239
6952 12:41:57.210301 ==
6953 12:41:57.213666 Dram Type= 6, Freq= 0, CH_1, rank 1
6954 12:41:57.217119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6955 12:41:57.217203 ==
6956 12:41:57.217270
6957 12:41:57.217331
6958 12:41:57.220232 TX Vref Scan disable
6959 12:41:57.220316 == TX Byte 0 ==
6960 12:41:57.226664 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6961 12:41:57.230279 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6962 12:41:57.230364 == TX Byte 1 ==
6963 12:41:57.233452 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6964 12:41:57.240168 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6965 12:41:57.240252 ==
6966 12:41:57.243240 Dram Type= 6, Freq= 0, CH_1, rank 1
6967 12:41:57.246611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6968 12:41:57.246697 ==
6969 12:41:57.246764
6970 12:41:57.246825
6971 12:41:57.250148 TX Vref Scan disable
6972 12:41:57.250232 == TX Byte 0 ==
6973 12:41:57.256797 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6974 12:41:57.259855 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6975 12:41:57.259940 == TX Byte 1 ==
6976 12:41:57.263541 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6977 12:41:57.270243 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6978 12:41:57.270328
6979 12:41:57.270395 [DATLAT]
6980 12:41:57.273659 Freq=400, CH1 RK1
6981 12:41:57.273744
6982 12:41:57.273811 DATLAT Default: 0xe
6983 12:41:57.276861 0, 0xFFFF, sum = 0
6984 12:41:57.276947 1, 0xFFFF, sum = 0
6985 12:41:57.280192 2, 0xFFFF, sum = 0
6986 12:41:57.280278 3, 0xFFFF, sum = 0
6987 12:41:57.283722 4, 0xFFFF, sum = 0
6988 12:41:57.283808 5, 0xFFFF, sum = 0
6989 12:41:57.286638 6, 0xFFFF, sum = 0
6990 12:41:57.286724 7, 0xFFFF, sum = 0
6991 12:41:57.290033 8, 0xFFFF, sum = 0
6992 12:41:57.290119 9, 0xFFFF, sum = 0
6993 12:41:57.293425 10, 0xFFFF, sum = 0
6994 12:41:57.293510 11, 0xFFFF, sum = 0
6995 12:41:57.296899 12, 0xFFFF, sum = 0
6996 12:41:57.296994 13, 0x0, sum = 1
6997 12:41:57.299848 14, 0x0, sum = 2
6998 12:41:57.299933 15, 0x0, sum = 3
6999 12:41:57.303000 16, 0x0, sum = 4
7000 12:41:57.303085 best_step = 14
7001 12:41:57.303152
7002 12:41:57.303214 ==
7003 12:41:57.306315 Dram Type= 6, Freq= 0, CH_1, rank 1
7004 12:41:57.313515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7005 12:41:57.313600 ==
7006 12:41:57.313668 RX Vref Scan: 0
7007 12:41:57.313730
7008 12:41:57.316285 RX Vref 0 -> 0, step: 1
7009 12:41:57.316369
7010 12:41:57.319854 RX Delay -343 -> 252, step: 8
7011 12:41:57.326191 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
7012 12:41:57.329673 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
7013 12:41:57.333212 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
7014 12:41:57.336222 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
7015 12:41:57.343060 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
7016 12:41:57.346456 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
7017 12:41:57.349434 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
7018 12:41:57.352932 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
7019 12:41:57.359637 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
7020 12:41:57.362837 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
7021 12:41:57.366166 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
7022 12:41:57.369559 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
7023 12:41:57.376135 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
7024 12:41:57.379684 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
7025 12:41:57.383195 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
7026 12:41:57.389437 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
7027 12:41:57.389521 ==
7028 12:41:57.392771 Dram Type= 6, Freq= 0, CH_1, rank 1
7029 12:41:57.396263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7030 12:41:57.396342 ==
7031 12:41:57.396412 DQS Delay:
7032 12:41:57.399286 DQS0 = 52, DQS1 = 60
7033 12:41:57.399389 DQM Delay:
7034 12:41:57.402791 DQM0 = 13, DQM1 = 12
7035 12:41:57.402867 DQ Delay:
7036 12:41:57.406340 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =12
7037 12:41:57.409475 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
7038 12:41:57.412879 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
7039 12:41:57.415711 DQ12 =16, DQ13 =20, DQ14 =20, DQ15 =20
7040 12:41:57.415785
7041 12:41:57.415847
7042 12:41:57.422547 [DQSOSCAuto] RK1, (LSB)MR18= 0x6f84, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 395 ps
7043 12:41:57.426012 CH1 RK1: MR19=C0C, MR18=6F84
7044 12:41:57.432536 CH1_RK1: MR19=0xC0C, MR18=0x6F84, DQSOSC=393, MR23=63, INC=382, DEC=254
7045 12:41:57.435957 [RxdqsGatingPostProcess] freq 400
7046 12:41:57.442656 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7047 12:41:57.442736 best DQS0 dly(2T, 0.5T) = (0, 10)
7048 12:41:57.446104 best DQS1 dly(2T, 0.5T) = (0, 10)
7049 12:41:57.449483 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7050 12:41:57.453077 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7051 12:41:57.456462 best DQS0 dly(2T, 0.5T) = (0, 10)
7052 12:41:57.459454 best DQS1 dly(2T, 0.5T) = (0, 10)
7053 12:41:57.462451 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7054 12:41:57.466370 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7055 12:41:57.469534 Pre-setting of DQS Precalculation
7056 12:41:57.472663 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7057 12:41:57.483089 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7058 12:41:57.489353 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7059 12:41:57.489436
7060 12:41:57.489503
7061 12:41:57.492426 [Calibration Summary] 800 Mbps
7062 12:41:57.492506 CH 0, Rank 0
7063 12:41:57.495835 SW Impedance : PASS
7064 12:41:57.495913 DUTY Scan : NO K
7065 12:41:57.499591 ZQ Calibration : PASS
7066 12:41:57.502249 Jitter Meter : NO K
7067 12:41:57.502326 CBT Training : PASS
7068 12:41:57.506239 Write leveling : PASS
7069 12:41:57.509059 RX DQS gating : PASS
7070 12:41:57.509129 RX DQ/DQS(RDDQC) : PASS
7071 12:41:57.512355 TX DQ/DQS : PASS
7072 12:41:57.515874 RX DATLAT : PASS
7073 12:41:57.515951 RX DQ/DQS(Engine): PASS
7074 12:41:57.518970 TX OE : NO K
7075 12:41:57.519044 All Pass.
7076 12:41:57.519105
7077 12:41:57.522564 CH 0, Rank 1
7078 12:41:57.522648 SW Impedance : PASS
7079 12:41:57.525443 DUTY Scan : NO K
7080 12:41:57.529102 ZQ Calibration : PASS
7081 12:41:57.529185 Jitter Meter : NO K
7082 12:41:57.532178 CBT Training : PASS
7083 12:41:57.535523 Write leveling : NO K
7084 12:41:57.535606 RX DQS gating : PASS
7085 12:41:57.538753 RX DQ/DQS(RDDQC) : PASS
7086 12:41:57.538836 TX DQ/DQS : PASS
7087 12:41:57.542245 RX DATLAT : PASS
7088 12:41:57.545879 RX DQ/DQS(Engine): PASS
7089 12:41:57.545963 TX OE : NO K
7090 12:41:57.549082 All Pass.
7091 12:41:57.549165
7092 12:41:57.549229 CH 1, Rank 0
7093 12:41:57.552012 SW Impedance : PASS
7094 12:41:57.552122 DUTY Scan : NO K
7095 12:41:57.555322 ZQ Calibration : PASS
7096 12:41:57.559019 Jitter Meter : NO K
7097 12:41:57.559102 CBT Training : PASS
7098 12:41:57.562230 Write leveling : PASS
7099 12:41:57.565700 RX DQS gating : PASS
7100 12:41:57.565783 RX DQ/DQS(RDDQC) : PASS
7101 12:41:57.568775 TX DQ/DQS : PASS
7102 12:41:57.572287 RX DATLAT : PASS
7103 12:41:57.572371 RX DQ/DQS(Engine): PASS
7104 12:41:57.575470 TX OE : NO K
7105 12:41:57.575553 All Pass.
7106 12:41:57.575619
7107 12:41:57.578890 CH 1, Rank 1
7108 12:41:57.578973 SW Impedance : PASS
7109 12:41:57.581910 DUTY Scan : NO K
7110 12:41:57.585104 ZQ Calibration : PASS
7111 12:41:57.585186 Jitter Meter : NO K
7112 12:41:57.588469 CBT Training : PASS
7113 12:41:57.591849 Write leveling : NO K
7114 12:41:57.591932 RX DQS gating : PASS
7115 12:41:57.595329 RX DQ/DQS(RDDQC) : PASS
7116 12:41:57.595455 TX DQ/DQS : PASS
7117 12:41:57.598809 RX DATLAT : PASS
7118 12:41:57.602004 RX DQ/DQS(Engine): PASS
7119 12:41:57.602087 TX OE : NO K
7120 12:41:57.605389 All Pass.
7121 12:41:57.605471
7122 12:41:57.605537 DramC Write-DBI off
7123 12:41:57.608399 PER_BANK_REFRESH: Hybrid Mode
7124 12:41:57.612241 TX_TRACKING: ON
7125 12:41:57.618283 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7126 12:41:57.621612 [FAST_K] Save calibration result to emmc
7127 12:41:57.625753 dramc_set_vcore_voltage set vcore to 725000
7128 12:41:57.628397 Read voltage for 1600, 0
7129 12:41:57.628516 Vio18 = 0
7130 12:41:57.631575 Vcore = 725000
7131 12:41:57.631684 Vdram = 0
7132 12:41:57.631778 Vddq = 0
7133 12:41:57.635068 Vmddr = 0
7134 12:41:57.638097 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7135 12:41:57.644887 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7136 12:41:57.644972 MEM_TYPE=3, freq_sel=13
7137 12:41:57.648422 sv_algorithm_assistance_LP4_3733
7138 12:41:57.655120 ============ PULL DRAM RESETB DOWN ============
7139 12:41:57.658566 ========== PULL DRAM RESETB DOWN end =========
7140 12:41:57.662057 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7141 12:41:57.664943 ===================================
7142 12:41:57.668079 LPDDR4 DRAM CONFIGURATION
7143 12:41:57.671641 ===================================
7144 12:41:57.674711 EX_ROW_EN[0] = 0x0
7145 12:41:57.674795 EX_ROW_EN[1] = 0x0
7146 12:41:57.678510 LP4Y_EN = 0x0
7147 12:41:57.678593 WORK_FSP = 0x1
7148 12:41:57.681557 WL = 0x5
7149 12:41:57.681640 RL = 0x5
7150 12:41:57.684713 BL = 0x2
7151 12:41:57.684798 RPST = 0x0
7152 12:41:57.688480 RD_PRE = 0x0
7153 12:41:57.688565 WR_PRE = 0x1
7154 12:41:57.691322 WR_PST = 0x1
7155 12:41:57.691460 DBI_WR = 0x0
7156 12:41:57.694534 DBI_RD = 0x0
7157 12:41:57.694619 OTF = 0x1
7158 12:41:57.698252 ===================================
7159 12:41:57.701101 ===================================
7160 12:41:57.704526 ANA top config
7161 12:41:57.707846 ===================================
7162 12:41:57.711030 DLL_ASYNC_EN = 0
7163 12:41:57.711136 ALL_SLAVE_EN = 0
7164 12:41:57.714810 NEW_RANK_MODE = 1
7165 12:41:57.717500 DLL_IDLE_MODE = 1
7166 12:41:57.720940 LP45_APHY_COMB_EN = 1
7167 12:41:57.724476 TX_ODT_DIS = 0
7168 12:41:57.724576 NEW_8X_MODE = 1
7169 12:41:57.727455 ===================================
7170 12:41:57.731119 ===================================
7171 12:41:57.734331 data_rate = 3200
7172 12:41:57.737616 CKR = 1
7173 12:41:57.740964 DQ_P2S_RATIO = 8
7174 12:41:57.744245 ===================================
7175 12:41:57.747961 CA_P2S_RATIO = 8
7176 12:41:57.748036 DQ_CA_OPEN = 0
7177 12:41:57.751102 DQ_SEMI_OPEN = 0
7178 12:41:57.754316 CA_SEMI_OPEN = 0
7179 12:41:57.757600 CA_FULL_RATE = 0
7180 12:41:57.760715 DQ_CKDIV4_EN = 0
7181 12:41:57.764331 CA_CKDIV4_EN = 0
7182 12:41:57.764432 CA_PREDIV_EN = 0
7183 12:41:57.767381 PH8_DLY = 12
7184 12:41:57.771164 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7185 12:41:57.774079 DQ_AAMCK_DIV = 4
7186 12:41:57.777752 CA_AAMCK_DIV = 4
7187 12:41:57.780555 CA_ADMCK_DIV = 4
7188 12:41:57.784379 DQ_TRACK_CA_EN = 0
7189 12:41:57.784454 CA_PICK = 1600
7190 12:41:57.787248 CA_MCKIO = 1600
7191 12:41:57.790619 MCKIO_SEMI = 0
7192 12:41:57.794156 PLL_FREQ = 3068
7193 12:41:57.797013 DQ_UI_PI_RATIO = 32
7194 12:41:57.801321 CA_UI_PI_RATIO = 0
7195 12:41:57.804050 ===================================
7196 12:41:57.807268 ===================================
7197 12:41:57.807376 memory_type:LPDDR4
7198 12:41:57.810326 GP_NUM : 10
7199 12:41:57.813909 SRAM_EN : 1
7200 12:41:57.814012 MD32_EN : 0
7201 12:41:57.817521 ===================================
7202 12:41:57.820641 [ANA_INIT] >>>>>>>>>>>>>>
7203 12:41:57.824005 <<<<<< [CONFIGURE PHASE]: ANA_TX
7204 12:41:57.827722 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7205 12:41:57.830565 ===================================
7206 12:41:57.834134 data_rate = 3200,PCW = 0X7600
7207 12:41:57.837605 ===================================
7208 12:41:57.841171 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7209 12:41:57.844204 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7210 12:41:57.850644 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7211 12:41:57.853701 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7212 12:41:57.857322 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7213 12:41:57.860373 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7214 12:41:57.864021 [ANA_INIT] flow start
7215 12:41:57.866930 [ANA_INIT] PLL >>>>>>>>
7216 12:41:57.867029 [ANA_INIT] PLL <<<<<<<<
7217 12:41:57.870201 [ANA_INIT] MIDPI >>>>>>>>
7218 12:41:57.873509 [ANA_INIT] MIDPI <<<<<<<<
7219 12:41:57.876826 [ANA_INIT] DLL >>>>>>>>
7220 12:41:57.876913 [ANA_INIT] DLL <<<<<<<<
7221 12:41:57.880423 [ANA_INIT] flow end
7222 12:41:57.883786 ============ LP4 DIFF to SE enter ============
7223 12:41:57.887427 ============ LP4 DIFF to SE exit ============
7224 12:41:57.890267 [ANA_INIT] <<<<<<<<<<<<<
7225 12:41:57.893462 [Flow] Enable top DCM control >>>>>
7226 12:41:57.896714 [Flow] Enable top DCM control <<<<<
7227 12:41:57.900121 Enable DLL master slave shuffle
7228 12:41:57.906584 ==============================================================
7229 12:41:57.906665 Gating Mode config
7230 12:41:57.913817 ==============================================================
7231 12:41:57.913924 Config description:
7232 12:41:57.923183 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7233 12:41:57.929805 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7234 12:41:57.936998 SELPH_MODE 0: By rank 1: By Phase
7235 12:41:57.939728 ==============================================================
7236 12:41:57.943150 GAT_TRACK_EN = 1
7237 12:41:57.946806 RX_GATING_MODE = 2
7238 12:41:57.950366 RX_GATING_TRACK_MODE = 2
7239 12:41:57.953549 SELPH_MODE = 1
7240 12:41:57.956548 PICG_EARLY_EN = 1
7241 12:41:57.960127 VALID_LAT_VALUE = 1
7242 12:41:57.966485 ==============================================================
7243 12:41:57.966562 Enter into Gating configuration >>>>
7244 12:41:57.969808 Exit from Gating configuration <<<<
7245 12:41:57.973582 Enter into DVFS_PRE_config >>>>>
7246 12:41:57.987165 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7247 12:41:57.990481 Exit from DVFS_PRE_config <<<<<
7248 12:41:57.993682 Enter into PICG configuration >>>>
7249 12:41:57.996352 Exit from PICG configuration <<<<
7250 12:41:57.996450 [RX_INPUT] configuration >>>>>
7251 12:41:57.999971 [RX_INPUT] configuration <<<<<
7252 12:41:58.006309 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7253 12:41:58.009754 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7254 12:41:58.016595 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7255 12:41:58.023104 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7256 12:41:58.030166 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7257 12:41:58.036493 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7258 12:41:58.039803 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7259 12:41:58.043237 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7260 12:41:58.049560 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7261 12:41:58.053053 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7262 12:41:58.056948 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7263 12:41:58.060018 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7264 12:41:58.063242 ===================================
7265 12:41:58.066465 LPDDR4 DRAM CONFIGURATION
7266 12:41:58.069706 ===================================
7267 12:41:58.072929 EX_ROW_EN[0] = 0x0
7268 12:41:58.073037 EX_ROW_EN[1] = 0x0
7269 12:41:58.076060 LP4Y_EN = 0x0
7270 12:41:58.076157 WORK_FSP = 0x1
7271 12:41:58.079480 WL = 0x5
7272 12:41:58.079589 RL = 0x5
7273 12:41:58.082934 BL = 0x2
7274 12:41:58.083011 RPST = 0x0
7275 12:41:58.086323 RD_PRE = 0x0
7276 12:41:58.086400 WR_PRE = 0x1
7277 12:41:58.089672 WR_PST = 0x1
7278 12:41:58.089758 DBI_WR = 0x0
7279 12:41:58.092814 DBI_RD = 0x0
7280 12:41:58.092926 OTF = 0x1
7281 12:41:58.096025 ===================================
7282 12:41:58.102882 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7283 12:41:58.106219 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7284 12:41:58.109403 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7285 12:41:58.113111 ===================================
7286 12:41:58.116217 LPDDR4 DRAM CONFIGURATION
7287 12:41:58.119474 ===================================
7288 12:41:58.122549 EX_ROW_EN[0] = 0x10
7289 12:41:58.122632 EX_ROW_EN[1] = 0x0
7290 12:41:58.126425 LP4Y_EN = 0x0
7291 12:41:58.126529 WORK_FSP = 0x1
7292 12:41:58.129172 WL = 0x5
7293 12:41:58.129254 RL = 0x5
7294 12:41:58.132690 BL = 0x2
7295 12:41:58.132794 RPST = 0x0
7296 12:41:58.136329 RD_PRE = 0x0
7297 12:41:58.136411 WR_PRE = 0x1
7298 12:41:58.139563 WR_PST = 0x1
7299 12:41:58.139664 DBI_WR = 0x0
7300 12:41:58.143209 DBI_RD = 0x0
7301 12:41:58.143280 OTF = 0x1
7302 12:41:58.146557 ===================================
7303 12:41:58.153394 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7304 12:41:58.153497 ==
7305 12:41:58.156212 Dram Type= 6, Freq= 0, CH_0, rank 0
7306 12:41:58.162570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7307 12:41:58.162671 ==
7308 12:41:58.162766 [Duty_Offset_Calibration]
7309 12:41:58.166125 B0:2 B1:-1 CA:1
7310 12:41:58.166227
7311 12:41:58.169431 [DutyScan_Calibration_Flow] k_type=0
7312 12:41:58.177567
7313 12:41:58.177649 ==CLK 0==
7314 12:41:58.180871 Final CLK duty delay cell = -4
7315 12:41:58.184082 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7316 12:41:58.187715 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7317 12:41:58.190979 [-4] AVG Duty = 4937%(X100)
7318 12:41:58.191061
7319 12:41:58.194564 CH0 CLK Duty spec in!! Max-Min= 187%
7320 12:41:58.197791 [DutyScan_Calibration_Flow] ====Done====
7321 12:41:58.197875
7322 12:41:58.200777 [DutyScan_Calibration_Flow] k_type=1
7323 12:41:58.217286
7324 12:41:58.217369 ==DQS 0 ==
7325 12:41:58.220697 Final DQS duty delay cell = 0
7326 12:41:58.224457 [0] MAX Duty = 5125%(X100), DQS PI = 20
7327 12:41:58.227212 [0] MIN Duty = 5000%(X100), DQS PI = 16
7328 12:41:58.230657 [0] AVG Duty = 5062%(X100)
7329 12:41:58.230742
7330 12:41:58.230808 ==DQS 1 ==
7331 12:41:58.234150 Final DQS duty delay cell = -4
7332 12:41:58.236987 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7333 12:41:58.240647 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7334 12:41:58.243945 [-4] AVG Duty = 5046%(X100)
7335 12:41:58.244030
7336 12:41:58.247300 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7337 12:41:58.247393
7338 12:41:58.250261 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7339 12:41:58.253992 [DutyScan_Calibration_Flow] ====Done====
7340 12:41:58.254076
7341 12:41:58.256947 [DutyScan_Calibration_Flow] k_type=3
7342 12:41:58.275053
7343 12:41:58.275136 ==DQM 0 ==
7344 12:41:58.278009 Final DQM duty delay cell = 0
7345 12:41:58.281128 [0] MAX Duty = 5000%(X100), DQS PI = 20
7346 12:41:58.284811 [0] MIN Duty = 4875%(X100), DQS PI = 4
7347 12:41:58.287855 [0] AVG Duty = 4937%(X100)
7348 12:41:58.287928
7349 12:41:58.287992 ==DQM 1 ==
7350 12:41:58.291076 Final DQM duty delay cell = 0
7351 12:41:58.294527 [0] MAX Duty = 5218%(X100), DQS PI = 60
7352 12:41:58.298024 [0] MIN Duty = 4969%(X100), DQS PI = 20
7353 12:41:58.301229 [0] AVG Duty = 5093%(X100)
7354 12:41:58.301312
7355 12:41:58.304568 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7356 12:41:58.304651
7357 12:41:58.307587 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7358 12:41:58.311009 [DutyScan_Calibration_Flow] ====Done====
7359 12:41:58.311091
7360 12:41:58.314470 [DutyScan_Calibration_Flow] k_type=2
7361 12:41:58.330919
7362 12:41:58.331001 ==DQ 0 ==
7363 12:41:58.334123 Final DQ duty delay cell = -4
7364 12:41:58.337528 [-4] MAX Duty = 5031%(X100), DQS PI = 56
7365 12:41:58.340764 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7366 12:41:58.344164 [-4] AVG Duty = 4937%(X100)
7367 12:41:58.344244
7368 12:41:58.344308 ==DQ 1 ==
7369 12:41:58.347461 Final DQ duty delay cell = 0
7370 12:41:58.351000 [0] MAX Duty = 5031%(X100), DQS PI = 14
7371 12:41:58.354395 [0] MIN Duty = 4938%(X100), DQS PI = 2
7372 12:41:58.357747 [0] AVG Duty = 4984%(X100)
7373 12:41:58.357828
7374 12:41:58.361123 CH0 DQ 0 Duty spec in!! Max-Min= 187%
7375 12:41:58.361206
7376 12:41:58.364133 CH0 DQ 1 Duty spec in!! Max-Min= 93%
7377 12:41:58.367456 [DutyScan_Calibration_Flow] ====Done====
7378 12:41:58.367551 ==
7379 12:41:58.371064 Dram Type= 6, Freq= 0, CH_1, rank 0
7380 12:41:58.374180 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7381 12:41:58.374262 ==
7382 12:41:58.377218 [Duty_Offset_Calibration]
7383 12:41:58.377299 B0:1 B1:1 CA:2
7384 12:41:58.377363
7385 12:41:58.380464 [DutyScan_Calibration_Flow] k_type=0
7386 12:41:58.391412
7387 12:41:58.391494 ==CLK 0==
7388 12:41:58.394589 Final CLK duty delay cell = 0
7389 12:41:58.398032 [0] MAX Duty = 5218%(X100), DQS PI = 24
7390 12:41:58.401586 [0] MIN Duty = 4938%(X100), DQS PI = 48
7391 12:41:58.404592 [0] AVG Duty = 5078%(X100)
7392 12:41:58.404674
7393 12:41:58.407855 CH1 CLK Duty spec in!! Max-Min= 280%
7394 12:41:58.411605 [DutyScan_Calibration_Flow] ====Done====
7395 12:41:58.411686
7396 12:41:58.414322 [DutyScan_Calibration_Flow] k_type=1
7397 12:41:58.430932
7398 12:41:58.431013 ==DQS 0 ==
7399 12:41:58.434275 Final DQS duty delay cell = 0
7400 12:41:58.437610 [0] MAX Duty = 5062%(X100), DQS PI = 22
7401 12:41:58.441019 [0] MIN Duty = 4813%(X100), DQS PI = 52
7402 12:41:58.444700 [0] AVG Duty = 4937%(X100)
7403 12:41:58.444821
7404 12:41:58.444903 ==DQS 1 ==
7405 12:41:58.447415 Final DQS duty delay cell = 0
7406 12:41:58.451046 [0] MAX Duty = 5031%(X100), DQS PI = 34
7407 12:41:58.454377 [0] MIN Duty = 4938%(X100), DQS PI = 28
7408 12:41:58.457803 [0] AVG Duty = 4984%(X100)
7409 12:41:58.457885
7410 12:41:58.460612 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7411 12:41:58.460694
7412 12:41:58.464107 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7413 12:41:58.467497 [DutyScan_Calibration_Flow] ====Done====
7414 12:41:58.467578
7415 12:41:58.470792 [DutyScan_Calibration_Flow] k_type=3
7416 12:41:58.488048
7417 12:41:58.488129 ==DQM 0 ==
7418 12:41:58.491500 Final DQM duty delay cell = 0
7419 12:41:58.494359 [0] MAX Duty = 5187%(X100), DQS PI = 22
7420 12:41:58.498387 [0] MIN Duty = 4844%(X100), DQS PI = 50
7421 12:41:58.501081 [0] AVG Duty = 5015%(X100)
7422 12:41:58.501168
7423 12:41:58.501238 ==DQM 1 ==
7424 12:41:58.504622 Final DQM duty delay cell = 0
7425 12:41:58.508027 [0] MAX Duty = 5156%(X100), DQS PI = 60
7426 12:41:58.511040 [0] MIN Duty = 4875%(X100), DQS PI = 22
7427 12:41:58.514684 [0] AVG Duty = 5015%(X100)
7428 12:41:58.514765
7429 12:41:58.517697 CH1 DQM 0 Duty spec in!! Max-Min= 343%
7430 12:41:58.517778
7431 12:41:58.521094 CH1 DQM 1 Duty spec in!! Max-Min= 281%
7432 12:41:58.524363 [DutyScan_Calibration_Flow] ====Done====
7433 12:41:58.524444
7434 12:41:58.527637 [DutyScan_Calibration_Flow] k_type=2
7435 12:41:58.545322
7436 12:41:58.545404 ==DQ 0 ==
7437 12:41:58.547983 Final DQ duty delay cell = 0
7438 12:41:58.551682 [0] MAX Duty = 5156%(X100), DQS PI = 20
7439 12:41:58.554870 [0] MIN Duty = 4907%(X100), DQS PI = 52
7440 12:41:58.554951 [0] AVG Duty = 5031%(X100)
7441 12:41:58.558279
7442 12:41:58.558386 ==DQ 1 ==
7443 12:41:58.561580 Final DQ duty delay cell = 0
7444 12:41:58.564843 [0] MAX Duty = 5093%(X100), DQS PI = 6
7445 12:41:58.568260 [0] MIN Duty = 5031%(X100), DQS PI = 0
7446 12:41:58.568343 [0] AVG Duty = 5062%(X100)
7447 12:41:58.568409
7448 12:41:58.571204 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7449 12:41:58.574649
7450 12:41:58.577975 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7451 12:41:58.581082 [DutyScan_Calibration_Flow] ====Done====
7452 12:41:58.584508 nWR fixed to 30
7453 12:41:58.584591 [ModeRegInit_LP4] CH0 RK0
7454 12:41:58.588313 [ModeRegInit_LP4] CH0 RK1
7455 12:41:58.591233 [ModeRegInit_LP4] CH1 RK0
7456 12:41:58.594616 [ModeRegInit_LP4] CH1 RK1
7457 12:41:58.594700 match AC timing 5
7458 12:41:58.597666 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7459 12:41:58.604603 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7460 12:41:58.607668 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7461 12:41:58.614541 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7462 12:41:58.617664 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7463 12:41:58.617781 [MiockJmeterHQA]
7464 12:41:58.617846
7465 12:41:58.620918 [DramcMiockJmeter] u1RxGatingPI = 0
7466 12:41:58.623925 0 : 4254, 4029
7467 12:41:58.624012 4 : 4252, 4027
7468 12:41:58.627518 8 : 4255, 4029
7469 12:41:58.627604 12 : 4252, 4027
7470 12:41:58.627672 16 : 4253, 4026
7471 12:41:58.630797 20 : 4363, 4138
7472 12:41:58.630882 24 : 4252, 4026
7473 12:41:58.634269 28 : 4363, 4137
7474 12:41:58.634354 32 : 4252, 4027
7475 12:41:58.637961 36 : 4253, 4027
7476 12:41:58.638046 40 : 4252, 4027
7477 12:41:58.638114 44 : 4360, 4137
7478 12:41:58.640769 48 : 4363, 4137
7479 12:41:58.640854 52 : 4249, 4027
7480 12:41:58.643992 56 : 4253, 4026
7481 12:41:58.644076 60 : 4252, 4027
7482 12:41:58.647481 64 : 4249, 4027
7483 12:41:58.647566 68 : 4253, 4029
7484 12:41:58.651037 72 : 4361, 4137
7485 12:41:58.651122 76 : 4250, 4026
7486 12:41:58.651189 80 : 4249, 4027
7487 12:41:58.654400 84 : 4250, 4027
7488 12:41:58.654485 88 : 4253, 4029
7489 12:41:58.657752 92 : 4249, 4027
7490 12:41:58.657837 96 : 4360, 3464
7491 12:41:58.661180 100 : 4361, 0
7492 12:41:58.661266 104 : 4361, 0
7493 12:41:58.661334 108 : 4363, 0
7494 12:41:58.664582 112 : 4360, 0
7495 12:41:58.664668 116 : 4250, 0
7496 12:41:58.667602 120 : 4250, 0
7497 12:41:58.667687 124 : 4249, 0
7498 12:41:58.667755 128 : 4253, 0
7499 12:41:58.671112 132 : 4249, 0
7500 12:41:58.671197 136 : 4249, 0
7501 12:41:58.671265 140 : 4252, 0
7502 12:41:58.674684 144 : 4360, 0
7503 12:41:58.674769 148 : 4360, 0
7504 12:41:58.677324 152 : 4363, 0
7505 12:41:58.677410 156 : 4361, 0
7506 12:41:58.677478 160 : 4360, 0
7507 12:41:58.681243 164 : 4250, 0
7508 12:41:58.681328 168 : 4250, 0
7509 12:41:58.683955 172 : 4250, 0
7510 12:41:58.684040 176 : 4250, 0
7511 12:41:58.684108 180 : 4253, 0
7512 12:41:58.687556 184 : 4250, 0
7513 12:41:58.687667 188 : 4250, 0
7514 12:41:58.687764 192 : 4253, 0
7515 12:41:58.690774 196 : 4250, 0
7516 12:41:58.690860 200 : 4249, 0
7517 12:41:58.694282 204 : 4363, 0
7518 12:41:58.694368 208 : 4361, 0
7519 12:41:58.694448 212 : 4249, 66
7520 12:41:58.697435 216 : 4250, 3524
7521 12:41:58.697548 220 : 4250, 4027
7522 12:41:58.700668 224 : 4252, 4027
7523 12:41:58.700774 228 : 4360, 4137
7524 12:41:58.704295 232 : 4250, 4027
7525 12:41:58.704380 236 : 4250, 4027
7526 12:41:58.707234 240 : 4360, 4138
7527 12:41:58.707335 244 : 4250, 4027
7528 12:41:58.710839 248 : 4253, 4026
7529 12:41:58.710914 252 : 4363, 4140
7530 12:41:58.714061 256 : 4250, 4027
7531 12:41:58.714169 260 : 4249, 4027
7532 12:41:58.717563 264 : 4250, 4026
7533 12:41:58.717643 268 : 4253, 4029
7534 12:41:58.717708 272 : 4250, 4027
7535 12:41:58.720738 276 : 4250, 4027
7536 12:41:58.720810 280 : 4360, 4137
7537 12:41:58.724217 284 : 4250, 4027
7538 12:41:58.724290 288 : 4250, 4027
7539 12:41:58.727160 292 : 4361, 4138
7540 12:41:58.727270 296 : 4249, 4027
7541 12:41:58.730490 300 : 4250, 4026
7542 12:41:58.730563 304 : 4363, 4140
7543 12:41:58.734192 308 : 4250, 4027
7544 12:41:58.734295 312 : 4250, 4027
7545 12:41:58.737086 316 : 4250, 4026
7546 12:41:58.737185 320 : 4253, 4029
7547 12:41:58.740425 324 : 4250, 4027
7548 12:41:58.740506 328 : 4250, 4027
7549 12:41:58.740571 332 : 4360, 2932
7550 12:41:58.743751 336 : 4250, 84
7551 12:41:58.743822
7552 12:41:58.747442 MIOCK jitter meter ch=0
7553 12:41:58.747544
7554 12:41:58.747635 1T = (336-100) = 236 dly cells
7555 12:41:58.753692 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7556 12:41:58.753769 ==
7557 12:41:58.757202 Dram Type= 6, Freq= 0, CH_0, rank 0
7558 12:41:58.760763 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7559 12:41:58.763909 ==
7560 12:41:58.767351 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7561 12:41:58.770536 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7562 12:41:58.776937 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7563 12:41:58.783539 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7564 12:41:58.791492 [CA 0] Center 44 (14~75) winsize 62
7565 12:41:58.794350 [CA 1] Center 44 (13~75) winsize 63
7566 12:41:58.797940 [CA 2] Center 40 (11~69) winsize 59
7567 12:41:58.801080 [CA 3] Center 39 (10~69) winsize 60
7568 12:41:58.804481 [CA 4] Center 38 (8~68) winsize 61
7569 12:41:58.807454 [CA 5] Center 37 (7~67) winsize 61
7570 12:41:58.807554
7571 12:41:58.811076 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7572 12:41:58.811174
7573 12:41:58.817674 [CATrainingPosCal] consider 1 rank data
7574 12:41:58.817775 u2DelayCellTimex100 = 275/100 ps
7575 12:41:58.824342 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7576 12:41:58.827482 CA1 delay=44 (13~75),Diff = 7 PI (24 cell)
7577 12:41:58.831024 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7578 12:41:58.834376 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7579 12:41:58.837406 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
7580 12:41:58.840846 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7581 12:41:58.840924
7582 12:41:58.844373 CA PerBit enable=1, Macro0, CA PI delay=37
7583 12:41:58.844446
7584 12:41:58.847863 [CBTSetCACLKResult] CA Dly = 37
7585 12:41:58.850744 CS Dly: 10 (0~41)
7586 12:41:58.854242 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7587 12:41:58.857506 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7588 12:41:58.857606 ==
7589 12:41:58.860486 Dram Type= 6, Freq= 0, CH_0, rank 1
7590 12:41:58.867562 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7591 12:41:58.867640 ==
7592 12:41:58.870940 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7593 12:41:58.877235 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7594 12:41:58.880835 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7595 12:41:58.886972 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7596 12:41:58.895131 [CA 0] Center 43 (13~74) winsize 62
7597 12:41:58.898213 [CA 1] Center 43 (13~74) winsize 62
7598 12:41:58.901818 [CA 2] Center 39 (10~69) winsize 60
7599 12:41:58.905264 [CA 3] Center 38 (9~68) winsize 60
7600 12:41:58.908130 [CA 4] Center 37 (7~67) winsize 61
7601 12:41:58.911754 [CA 5] Center 37 (7~67) winsize 61
7602 12:41:58.911830
7603 12:41:58.914735 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7604 12:41:58.914833
7605 12:41:58.921215 [CATrainingPosCal] consider 2 rank data
7606 12:41:58.921323 u2DelayCellTimex100 = 275/100 ps
7607 12:41:58.928170 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7608 12:41:58.931253 CA1 delay=43 (13~74),Diff = 6 PI (21 cell)
7609 12:41:58.934773 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7610 12:41:58.937795 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7611 12:41:58.941616 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7612 12:41:58.944940 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7613 12:41:58.945011
7614 12:41:58.947748 CA PerBit enable=1, Macro0, CA PI delay=37
7615 12:41:58.947840
7616 12:41:58.951278 [CBTSetCACLKResult] CA Dly = 37
7617 12:41:58.954642 CS Dly: 11 (0~44)
7618 12:41:58.958182 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7619 12:41:58.961189 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7620 12:41:58.961263
7621 12:41:58.964432 ----->DramcWriteLeveling(PI) begin...
7622 12:41:58.964505 ==
7623 12:41:58.967809 Dram Type= 6, Freq= 0, CH_0, rank 0
7624 12:41:58.974251 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7625 12:41:58.974357 ==
7626 12:41:58.977587 Write leveling (Byte 0): 33 => 33
7627 12:41:58.981756 Write leveling (Byte 1): 28 => 28
7628 12:41:58.981834 DramcWriteLeveling(PI) end<-----
7629 12:41:58.984341
7630 12:41:58.984424 ==
7631 12:41:58.987789 Dram Type= 6, Freq= 0, CH_0, rank 0
7632 12:41:58.991311 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7633 12:41:58.991411 ==
7634 12:41:58.994668 [Gating] SW mode calibration
7635 12:41:59.000647 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7636 12:41:59.004123 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7637 12:41:59.010701 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7638 12:41:59.014281 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7639 12:41:59.017833 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7640 12:41:59.024545 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7641 12:41:59.027810 1 4 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7642 12:41:59.031004 1 4 20 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
7643 12:41:59.037332 1 4 24 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
7644 12:41:59.040677 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7645 12:41:59.044255 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7646 12:41:59.050379 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7647 12:41:59.053824 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7648 12:41:59.057099 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7649 12:41:59.063493 1 5 16 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
7650 12:41:59.067210 1 5 20 | B1->B0 | 3434 2626 | 1 0 | (1 0) (0 0)
7651 12:41:59.070356 1 5 24 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
7652 12:41:59.077003 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7653 12:41:59.080204 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7654 12:41:59.083614 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7655 12:41:59.090574 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7656 12:41:59.093309 1 6 12 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
7657 12:41:59.096726 1 6 16 | B1->B0 | 2323 3837 | 0 1 | (0 0) (0 0)
7658 12:41:59.103655 1 6 20 | B1->B0 | 2626 4444 | 0 0 | (0 0) (0 0)
7659 12:41:59.107077 1 6 24 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
7660 12:41:59.109970 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7661 12:41:59.116781 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7662 12:41:59.120180 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7663 12:41:59.123282 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7664 12:41:59.129916 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7665 12:41:59.133655 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7666 12:41:59.136847 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7667 12:41:59.143514 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 12:41:59.146513 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 12:41:59.150282 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 12:41:59.156537 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 12:41:59.159949 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 12:41:59.163307 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7673 12:41:59.170056 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7674 12:41:59.173061 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7675 12:41:59.176558 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7676 12:41:59.183103 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 12:41:59.186420 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7678 12:41:59.189976 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7679 12:41:59.192971 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7680 12:41:59.200120 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7681 12:41:59.203124 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7682 12:41:59.206589 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7683 12:41:59.213394 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7684 12:41:59.216661 Total UI for P1: 0, mck2ui 16
7685 12:41:59.220023 best dqsien dly found for B0: ( 1, 9, 18)
7686 12:41:59.223184 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7687 12:41:59.226280 Total UI for P1: 0, mck2ui 16
7688 12:41:59.229970 best dqsien dly found for B1: ( 1, 9, 22)
7689 12:41:59.232870 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
7690 12:41:59.236241 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7691 12:41:59.236313
7692 12:41:59.239499 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
7693 12:41:59.246047 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7694 12:41:59.246150 [Gating] SW calibration Done
7695 12:41:59.246240 ==
7696 12:41:59.249467 Dram Type= 6, Freq= 0, CH_0, rank 0
7697 12:41:59.256273 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7698 12:41:59.256376 ==
7699 12:41:59.256475 RX Vref Scan: 0
7700 12:41:59.256565
7701 12:41:59.259113 RX Vref 0 -> 0, step: 1
7702 12:41:59.259209
7703 12:41:59.262669 RX Delay 0 -> 252, step: 8
7704 12:41:59.265919 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7705 12:41:59.269620 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7706 12:41:59.272997 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7707 12:41:59.275838 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7708 12:41:59.282509 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7709 12:41:59.285967 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7710 12:41:59.289464 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7711 12:41:59.292933 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7712 12:41:59.296001 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7713 12:41:59.302380 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7714 12:41:59.306046 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7715 12:41:59.309427 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7716 12:41:59.312682 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7717 12:41:59.316057 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7718 12:41:59.322557 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7719 12:41:59.326089 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7720 12:41:59.326162 ==
7721 12:41:59.329577 Dram Type= 6, Freq= 0, CH_0, rank 0
7722 12:41:59.332774 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7723 12:41:59.332858 ==
7724 12:41:59.335572 DQS Delay:
7725 12:41:59.335681 DQS0 = 0, DQS1 = 0
7726 12:41:59.335774 DQM Delay:
7727 12:41:59.339123 DQM0 = 132, DQM1 = 125
7728 12:41:59.339231 DQ Delay:
7729 12:41:59.342275 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7730 12:41:59.345830 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7731 12:41:59.349367 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
7732 12:41:59.355936 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7733 12:41:59.356010
7734 12:41:59.356084
7735 12:41:59.356144 ==
7736 12:41:59.359152 Dram Type= 6, Freq= 0, CH_0, rank 0
7737 12:41:59.362369 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7738 12:41:59.362468 ==
7739 12:41:59.362565
7740 12:41:59.362652
7741 12:41:59.365851 TX Vref Scan disable
7742 12:41:59.365953 == TX Byte 0 ==
7743 12:41:59.372827 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7744 12:41:59.376282 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7745 12:41:59.376380 == TX Byte 1 ==
7746 12:41:59.382595 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7747 12:41:59.385794 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7748 12:41:59.385877 ==
7749 12:41:59.389257 Dram Type= 6, Freq= 0, CH_0, rank 0
7750 12:41:59.392292 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7751 12:41:59.392391 ==
7752 12:41:59.407996
7753 12:41:59.411668 TX Vref early break, caculate TX vref
7754 12:41:59.414494 TX Vref=16, minBit 1, minWin=21, winSum=359
7755 12:41:59.418102 TX Vref=18, minBit 4, minWin=21, winSum=371
7756 12:41:59.421097 TX Vref=20, minBit 1, minWin=22, winSum=375
7757 12:41:59.424315 TX Vref=22, minBit 1, minWin=23, winSum=394
7758 12:41:59.427738 TX Vref=24, minBit 7, minWin=23, winSum=400
7759 12:41:59.434246 TX Vref=26, minBit 1, minWin=24, winSum=411
7760 12:41:59.437722 TX Vref=28, minBit 4, minWin=24, winSum=417
7761 12:41:59.441478 TX Vref=30, minBit 0, minWin=25, winSum=417
7762 12:41:59.444824 TX Vref=32, minBit 2, minWin=24, winSum=411
7763 12:41:59.448053 TX Vref=34, minBit 0, minWin=24, winSum=402
7764 12:41:59.451107 TX Vref=36, minBit 0, minWin=23, winSum=386
7765 12:41:59.457895 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 30
7766 12:41:59.457993
7767 12:41:59.461240 Final TX Range 0 Vref 30
7768 12:41:59.461312
7769 12:41:59.461378 ==
7770 12:41:59.464589 Dram Type= 6, Freq= 0, CH_0, rank 0
7771 12:41:59.467841 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7772 12:41:59.467915 ==
7773 12:41:59.467998
7774 12:41:59.468085
7775 12:41:59.471284 TX Vref Scan disable
7776 12:41:59.477864 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7777 12:41:59.477969 == TX Byte 0 ==
7778 12:41:59.481307 u2DelayCellOfst[0]=14 cells (4 PI)
7779 12:41:59.484634 u2DelayCellOfst[1]=17 cells (5 PI)
7780 12:41:59.487892 u2DelayCellOfst[2]=10 cells (3 PI)
7781 12:41:59.490835 u2DelayCellOfst[3]=14 cells (4 PI)
7782 12:41:59.494420 u2DelayCellOfst[4]=7 cells (2 PI)
7783 12:41:59.497710 u2DelayCellOfst[5]=0 cells (0 PI)
7784 12:41:59.501166 u2DelayCellOfst[6]=17 cells (5 PI)
7785 12:41:59.504482 u2DelayCellOfst[7]=17 cells (5 PI)
7786 12:41:59.507928 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7787 12:41:59.510663 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7788 12:41:59.514277 == TX Byte 1 ==
7789 12:41:59.517606 u2DelayCellOfst[8]=3 cells (1 PI)
7790 12:41:59.520959 u2DelayCellOfst[9]=0 cells (0 PI)
7791 12:41:59.524431 u2DelayCellOfst[10]=10 cells (3 PI)
7792 12:41:59.524514 u2DelayCellOfst[11]=3 cells (1 PI)
7793 12:41:59.527360 u2DelayCellOfst[12]=14 cells (4 PI)
7794 12:41:59.530640 u2DelayCellOfst[13]=10 cells (3 PI)
7795 12:41:59.534093 u2DelayCellOfst[14]=17 cells (5 PI)
7796 12:41:59.537629 u2DelayCellOfst[15]=10 cells (3 PI)
7797 12:41:59.544013 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7798 12:41:59.547793 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7799 12:41:59.547875 DramC Write-DBI on
7800 12:41:59.547941 ==
7801 12:41:59.550970 Dram Type= 6, Freq= 0, CH_0, rank 0
7802 12:41:59.557373 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7803 12:41:59.557456 ==
7804 12:41:59.557521
7805 12:41:59.557581
7806 12:41:59.557638 TX Vref Scan disable
7807 12:41:59.561430 == TX Byte 0 ==
7808 12:41:59.564810 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7809 12:41:59.567916 == TX Byte 1 ==
7810 12:41:59.571826 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7811 12:41:59.574829 DramC Write-DBI off
7812 12:41:59.574911
7813 12:41:59.574976 [DATLAT]
7814 12:41:59.575036 Freq=1600, CH0 RK0
7815 12:41:59.575094
7816 12:41:59.578103 DATLAT Default: 0xf
7817 12:41:59.578185 0, 0xFFFF, sum = 0
7818 12:41:59.581574 1, 0xFFFF, sum = 0
7819 12:41:59.584616 2, 0xFFFF, sum = 0
7820 12:41:59.584700 3, 0xFFFF, sum = 0
7821 12:41:59.587798 4, 0xFFFF, sum = 0
7822 12:41:59.587882 5, 0xFFFF, sum = 0
7823 12:41:59.591335 6, 0xFFFF, sum = 0
7824 12:41:59.591457 7, 0xFFFF, sum = 0
7825 12:41:59.594553 8, 0xFFFF, sum = 0
7826 12:41:59.594637 9, 0xFFFF, sum = 0
7827 12:41:59.597837 10, 0xFFFF, sum = 0
7828 12:41:59.597921 11, 0xFFFF, sum = 0
7829 12:41:59.601122 12, 0xFFFF, sum = 0
7830 12:41:59.601209 13, 0xFFFF, sum = 0
7831 12:41:59.604512 14, 0x0, sum = 1
7832 12:41:59.604595 15, 0x0, sum = 2
7833 12:41:59.607631 16, 0x0, sum = 3
7834 12:41:59.607715 17, 0x0, sum = 4
7835 12:41:59.611480 best_step = 15
7836 12:41:59.611564
7837 12:41:59.611630 ==
7838 12:41:59.615042 Dram Type= 6, Freq= 0, CH_0, rank 0
7839 12:41:59.617851 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7840 12:41:59.617945 ==
7841 12:41:59.621305 RX Vref Scan: 1
7842 12:41:59.621397
7843 12:41:59.621465 Set Vref Range= 24 -> 127
7844 12:41:59.621528
7845 12:41:59.624576 RX Vref 24 -> 127, step: 1
7846 12:41:59.624653
7847 12:41:59.628094 RX Delay 11 -> 252, step: 4
7848 12:41:59.628170
7849 12:41:59.631519 Set Vref, RX VrefLevel [Byte0]: 24
7850 12:41:59.634515 [Byte1]: 24
7851 12:41:59.634593
7852 12:41:59.637834 Set Vref, RX VrefLevel [Byte0]: 25
7853 12:41:59.640888 [Byte1]: 25
7854 12:41:59.644389
7855 12:41:59.644464 Set Vref, RX VrefLevel [Byte0]: 26
7856 12:41:59.647609 [Byte1]: 26
7857 12:41:59.651949
7858 12:41:59.652029 Set Vref, RX VrefLevel [Byte0]: 27
7859 12:41:59.655205 [Byte1]: 27
7860 12:41:59.660258
7861 12:41:59.660332 Set Vref, RX VrefLevel [Byte0]: 28
7862 12:41:59.662618 [Byte1]: 28
7863 12:41:59.667097
7864 12:41:59.667171 Set Vref, RX VrefLevel [Byte0]: 29
7865 12:41:59.670597 [Byte1]: 29
7866 12:41:59.674963
7867 12:41:59.675045 Set Vref, RX VrefLevel [Byte0]: 30
7868 12:41:59.677766 [Byte1]: 30
7869 12:41:59.682230
7870 12:41:59.682334 Set Vref, RX VrefLevel [Byte0]: 31
7871 12:41:59.685730 [Byte1]: 31
7872 12:41:59.690403
7873 12:41:59.690482 Set Vref, RX VrefLevel [Byte0]: 32
7874 12:41:59.692981 [Byte1]: 32
7875 12:41:59.697512
7876 12:41:59.697594 Set Vref, RX VrefLevel [Byte0]: 33
7877 12:41:59.701002 [Byte1]: 33
7878 12:41:59.705087
7879 12:41:59.705193 Set Vref, RX VrefLevel [Byte0]: 34
7880 12:41:59.708369 [Byte1]: 34
7881 12:41:59.712557
7882 12:41:59.712635 Set Vref, RX VrefLevel [Byte0]: 35
7883 12:41:59.716380 [Byte1]: 35
7884 12:41:59.720397
7885 12:41:59.720478 Set Vref, RX VrefLevel [Byte0]: 36
7886 12:41:59.724010 [Byte1]: 36
7887 12:41:59.727826
7888 12:41:59.727904 Set Vref, RX VrefLevel [Byte0]: 37
7889 12:41:59.731310 [Byte1]: 37
7890 12:41:59.735754
7891 12:41:59.735833 Set Vref, RX VrefLevel [Byte0]: 38
7892 12:41:59.738692 [Byte1]: 38
7893 12:41:59.743061
7894 12:41:59.743140 Set Vref, RX VrefLevel [Byte0]: 39
7895 12:41:59.746350 [Byte1]: 39
7896 12:41:59.750923
7897 12:41:59.751001 Set Vref, RX VrefLevel [Byte0]: 40
7898 12:41:59.754432 [Byte1]: 40
7899 12:41:59.758242
7900 12:41:59.758345 Set Vref, RX VrefLevel [Byte0]: 41
7901 12:41:59.761569 [Byte1]: 41
7902 12:41:59.765961
7903 12:41:59.766041 Set Vref, RX VrefLevel [Byte0]: 42
7904 12:41:59.769264 [Byte1]: 42
7905 12:41:59.773536
7906 12:41:59.773614 Set Vref, RX VrefLevel [Byte0]: 43
7907 12:41:59.776750 [Byte1]: 43
7908 12:41:59.781144
7909 12:41:59.781230 Set Vref, RX VrefLevel [Byte0]: 44
7910 12:41:59.784829 [Byte1]: 44
7911 12:41:59.789104
7912 12:41:59.789179 Set Vref, RX VrefLevel [Byte0]: 45
7913 12:41:59.792507 [Byte1]: 45
7914 12:41:59.796370
7915 12:41:59.796463 Set Vref, RX VrefLevel [Byte0]: 46
7916 12:41:59.799857 [Byte1]: 46
7917 12:41:59.803859
7918 12:41:59.803934 Set Vref, RX VrefLevel [Byte0]: 47
7919 12:41:59.807521 [Byte1]: 47
7920 12:41:59.811583
7921 12:41:59.811659 Set Vref, RX VrefLevel [Byte0]: 48
7922 12:41:59.815122 [Byte1]: 48
7923 12:41:59.819653
7924 12:41:59.819754 Set Vref, RX VrefLevel [Byte0]: 49
7925 12:41:59.822812 [Byte1]: 49
7926 12:41:59.826673
7927 12:41:59.826749 Set Vref, RX VrefLevel [Byte0]: 50
7928 12:41:59.830309 [Byte1]: 50
7929 12:41:59.834476
7930 12:41:59.834559 Set Vref, RX VrefLevel [Byte0]: 51
7931 12:41:59.838052 [Byte1]: 51
7932 12:41:59.842665
7933 12:41:59.842748 Set Vref, RX VrefLevel [Byte0]: 52
7934 12:41:59.845517 [Byte1]: 52
7935 12:41:59.849763
7936 12:41:59.849847 Set Vref, RX VrefLevel [Byte0]: 53
7937 12:41:59.853080 [Byte1]: 53
7938 12:41:59.857450
7939 12:41:59.857533 Set Vref, RX VrefLevel [Byte0]: 54
7940 12:41:59.860871 [Byte1]: 54
7941 12:41:59.865159
7942 12:41:59.865241 Set Vref, RX VrefLevel [Byte0]: 55
7943 12:41:59.868506 [Byte1]: 55
7944 12:41:59.872845
7945 12:41:59.872928 Set Vref, RX VrefLevel [Byte0]: 56
7946 12:41:59.875676 [Byte1]: 56
7947 12:41:59.880443
7948 12:41:59.883708 Set Vref, RX VrefLevel [Byte0]: 57
7949 12:41:59.883792 [Byte1]: 57
7950 12:41:59.887678
7951 12:41:59.887760 Set Vref, RX VrefLevel [Byte0]: 58
7952 12:41:59.890959 [Byte1]: 58
7953 12:41:59.895561
7954 12:41:59.895645 Set Vref, RX VrefLevel [Byte0]: 59
7955 12:41:59.898696 [Byte1]: 59
7956 12:41:59.903029
7957 12:41:59.903112 Set Vref, RX VrefLevel [Byte0]: 60
7958 12:41:59.906351 [Byte1]: 60
7959 12:41:59.910747
7960 12:41:59.910830 Set Vref, RX VrefLevel [Byte0]: 61
7961 12:41:59.913826 [Byte1]: 61
7962 12:41:59.918116
7963 12:41:59.918199 Set Vref, RX VrefLevel [Byte0]: 62
7964 12:41:59.921488 [Byte1]: 62
7965 12:41:59.926192
7966 12:41:59.926274 Set Vref, RX VrefLevel [Byte0]: 63
7967 12:41:59.929495 [Byte1]: 63
7968 12:41:59.933808
7969 12:41:59.933890 Set Vref, RX VrefLevel [Byte0]: 64
7970 12:41:59.936685 [Byte1]: 64
7971 12:41:59.941183
7972 12:41:59.941270 Set Vref, RX VrefLevel [Byte0]: 65
7973 12:41:59.944539 [Byte1]: 65
7974 12:41:59.948763
7975 12:41:59.948846 Set Vref, RX VrefLevel [Byte0]: 66
7976 12:41:59.952402 [Byte1]: 66
7977 12:41:59.956305
7978 12:41:59.956388 Set Vref, RX VrefLevel [Byte0]: 67
7979 12:41:59.959691 [Byte1]: 67
7980 12:41:59.964117
7981 12:41:59.964199 Set Vref, RX VrefLevel [Byte0]: 68
7982 12:41:59.967151 [Byte1]: 68
7983 12:41:59.971338
7984 12:41:59.971460 Set Vref, RX VrefLevel [Byte0]: 69
7985 12:41:59.974762 [Byte1]: 69
7986 12:41:59.979369
7987 12:41:59.982596 Set Vref, RX VrefLevel [Byte0]: 70
7988 12:41:59.985543 [Byte1]: 70
7989 12:41:59.985626
7990 12:41:59.988958 Set Vref, RX VrefLevel [Byte0]: 71
7991 12:41:59.992174 [Byte1]: 71
7992 12:41:59.992257
7993 12:41:59.995687 Set Vref, RX VrefLevel [Byte0]: 72
7994 12:41:59.999006 [Byte1]: 72
7995 12:41:59.999089
7996 12:42:00.002506 Set Vref, RX VrefLevel [Byte0]: 73
7997 12:42:00.005749 [Byte1]: 73
7998 12:42:00.009609
7999 12:42:00.009692 Set Vref, RX VrefLevel [Byte0]: 74
8000 12:42:00.012876 [Byte1]: 74
8001 12:42:00.016974
8002 12:42:00.017057 Set Vref, RX VrefLevel [Byte0]: 75
8003 12:42:00.020512 [Byte1]: 75
8004 12:42:00.025308
8005 12:42:00.025391 Set Vref, RX VrefLevel [Byte0]: 76
8006 12:42:00.028254 [Byte1]: 76
8007 12:42:00.032621
8008 12:42:00.032740 Set Vref, RX VrefLevel [Byte0]: 77
8009 12:42:00.035945 [Byte1]: 77
8010 12:42:00.040125
8011 12:42:00.040208 Final RX Vref Byte 0 = 56 to rank0
8012 12:42:00.043649 Final RX Vref Byte 1 = 63 to rank0
8013 12:42:00.046929 Final RX Vref Byte 0 = 56 to rank1
8014 12:42:00.049963 Final RX Vref Byte 1 = 63 to rank1==
8015 12:42:00.053310 Dram Type= 6, Freq= 0, CH_0, rank 0
8016 12:42:00.059824 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8017 12:42:00.059909 ==
8018 12:42:00.059976 DQS Delay:
8019 12:42:00.060037 DQS0 = 0, DQS1 = 0
8020 12:42:00.063440 DQM Delay:
8021 12:42:00.063523 DQM0 = 129, DQM1 = 122
8022 12:42:00.066867 DQ Delay:
8023 12:42:00.070323 DQ0 =130, DQ1 =132, DQ2 =124, DQ3 =126
8024 12:42:00.073293 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
8025 12:42:00.076406 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8026 12:42:00.079849 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =132
8027 12:42:00.079933
8028 12:42:00.080000
8029 12:42:00.080061
8030 12:42:00.083210 [DramC_TX_OE_Calibration] TA2
8031 12:42:00.086621 Original DQ_B0 (3 6) =30, OEN = 27
8032 12:42:00.089777 Original DQ_B1 (3 6) =30, OEN = 27
8033 12:42:00.093000 24, 0x0, End_B0=24 End_B1=24
8034 12:42:00.093086 25, 0x0, End_B0=25 End_B1=25
8035 12:42:00.096797 26, 0x0, End_B0=26 End_B1=26
8036 12:42:00.099664 27, 0x0, End_B0=27 End_B1=27
8037 12:42:00.103269 28, 0x0, End_B0=28 End_B1=28
8038 12:42:00.106519 29, 0x0, End_B0=29 End_B1=29
8039 12:42:00.106604 30, 0x0, End_B0=30 End_B1=30
8040 12:42:00.109892 31, 0x4545, End_B0=30 End_B1=30
8041 12:42:00.113193 Byte0 end_step=30 best_step=27
8042 12:42:00.116325 Byte1 end_step=30 best_step=27
8043 12:42:00.119752 Byte0 TX OE(2T, 0.5T) = (3, 3)
8044 12:42:00.123249 Byte1 TX OE(2T, 0.5T) = (3, 3)
8045 12:42:00.123334
8046 12:42:00.123440
8047 12:42:00.129919 [DQSOSCAuto] RK0, (LSB)MR18= 0x1307, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
8048 12:42:00.133156 CH0 RK0: MR19=303, MR18=1307
8049 12:42:00.139767 CH0_RK0: MR19=0x303, MR18=0x1307, DQSOSC=400, MR23=63, INC=23, DEC=15
8050 12:42:00.139851
8051 12:42:00.143049 ----->DramcWriteLeveling(PI) begin...
8052 12:42:00.143134 ==
8053 12:42:00.146394 Dram Type= 6, Freq= 0, CH_0, rank 1
8054 12:42:00.149603 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8055 12:42:00.149687 ==
8056 12:42:00.153238 Write leveling (Byte 0): 33 => 33
8057 12:42:00.156142 Write leveling (Byte 1): 27 => 27
8058 12:42:00.159436 DramcWriteLeveling(PI) end<-----
8059 12:42:00.159524
8060 12:42:00.159591 ==
8061 12:42:00.163072 Dram Type= 6, Freq= 0, CH_0, rank 1
8062 12:42:00.166053 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8063 12:42:00.166137 ==
8064 12:42:00.169371 [Gating] SW mode calibration
8065 12:42:00.176055 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8066 12:42:00.182703 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8067 12:42:00.185728 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8068 12:42:00.192382 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8069 12:42:00.195711 1 4 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8070 12:42:00.198991 1 4 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8071 12:42:00.205824 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8072 12:42:00.209095 1 4 20 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
8073 12:42:00.212820 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8074 12:42:00.215670 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8075 12:42:00.222493 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8076 12:42:00.225577 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8077 12:42:00.229200 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8078 12:42:00.236024 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 1)
8079 12:42:00.239128 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8080 12:42:00.242600 1 5 20 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
8081 12:42:00.248717 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8082 12:42:00.252131 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8083 12:42:00.255461 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8084 12:42:00.262013 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8085 12:42:00.265569 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8086 12:42:00.268614 1 6 12 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
8087 12:42:00.275336 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8088 12:42:00.278735 1 6 20 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
8089 12:42:00.282098 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8090 12:42:00.288580 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8091 12:42:00.292069 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8092 12:42:00.295378 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8093 12:42:00.302003 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8094 12:42:00.305399 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8095 12:42:00.308626 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8096 12:42:00.314983 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8097 12:42:00.318854 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8098 12:42:00.322205 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 12:42:00.329013 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 12:42:00.331858 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 12:42:00.335220 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 12:42:00.341745 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 12:42:00.345060 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 12:42:00.348541 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 12:42:00.355583 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 12:42:00.358465 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 12:42:00.361843 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8108 12:42:00.368316 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8109 12:42:00.371609 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8110 12:42:00.375137 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8111 12:42:00.381190 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8112 12:42:00.381264 Total UI for P1: 0, mck2ui 16
8113 12:42:00.384666 best dqsien dly found for B0: ( 1, 9, 8)
8114 12:42:00.391594 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8115 12:42:00.394684 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8116 12:42:00.397991 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8117 12:42:00.401524 Total UI for P1: 0, mck2ui 16
8118 12:42:00.404514 best dqsien dly found for B1: ( 1, 9, 22)
8119 12:42:00.407756 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8120 12:42:00.414323 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
8121 12:42:00.414425
8122 12:42:00.417767 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8123 12:42:00.421033 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
8124 12:42:00.424335 [Gating] SW calibration Done
8125 12:42:00.424433 ==
8126 12:42:00.427579 Dram Type= 6, Freq= 0, CH_0, rank 1
8127 12:42:00.431460 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8128 12:42:00.431544 ==
8129 12:42:00.434705 RX Vref Scan: 0
8130 12:42:00.434801
8131 12:42:00.434897 RX Vref 0 -> 0, step: 1
8132 12:42:00.434985
8133 12:42:00.437739 RX Delay 0 -> 252, step: 8
8134 12:42:00.441099 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8135 12:42:00.444529 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8136 12:42:00.451182 iDelay=200, Bit 2, Center 127 (64 ~ 191) 128
8137 12:42:00.454540 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8138 12:42:00.458062 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8139 12:42:00.460801 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8140 12:42:00.464389 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8141 12:42:00.470960 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8142 12:42:00.475248 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8143 12:42:00.477653 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8144 12:42:00.481173 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8145 12:42:00.484063 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8146 12:42:00.491318 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8147 12:42:00.494112 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8148 12:42:00.497276 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8149 12:42:00.500656 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8150 12:42:00.500728 ==
8151 12:42:00.504158 Dram Type= 6, Freq= 0, CH_0, rank 1
8152 12:42:00.510663 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8153 12:42:00.510765 ==
8154 12:42:00.510860 DQS Delay:
8155 12:42:00.513961 DQS0 = 0, DQS1 = 0
8156 12:42:00.514057 DQM Delay:
8157 12:42:00.517073 DQM0 = 131, DQM1 = 126
8158 12:42:00.517173 DQ Delay:
8159 12:42:00.520795 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =131
8160 12:42:00.524363 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8161 12:42:00.527242 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =119
8162 12:42:00.530519 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =131
8163 12:42:00.530623
8164 12:42:00.530711
8165 12:42:00.530797 ==
8166 12:42:00.533804 Dram Type= 6, Freq= 0, CH_0, rank 1
8167 12:42:00.540523 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8168 12:42:00.540622 ==
8169 12:42:00.540710
8170 12:42:00.540803
8171 12:42:00.540889 TX Vref Scan disable
8172 12:42:00.543985 == TX Byte 0 ==
8173 12:42:00.547344 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8174 12:42:00.554004 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8175 12:42:00.554102 == TX Byte 1 ==
8176 12:42:00.557417 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8177 12:42:00.563565 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8178 12:42:00.563639 ==
8179 12:42:00.567216 Dram Type= 6, Freq= 0, CH_0, rank 1
8180 12:42:00.570294 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8181 12:42:00.570396 ==
8182 12:42:00.584585
8183 12:42:00.587731 TX Vref early break, caculate TX vref
8184 12:42:00.591126 TX Vref=16, minBit 0, minWin=22, winSum=369
8185 12:42:00.594577 TX Vref=18, minBit 9, minWin=22, winSum=377
8186 12:42:00.597982 TX Vref=20, minBit 1, minWin=23, winSum=386
8187 12:42:00.601138 TX Vref=22, minBit 1, minWin=24, winSum=397
8188 12:42:00.604691 TX Vref=24, minBit 4, minWin=24, winSum=400
8189 12:42:00.611180 TX Vref=26, minBit 4, minWin=24, winSum=415
8190 12:42:00.614343 TX Vref=28, minBit 0, minWin=25, winSum=417
8191 12:42:00.617603 TX Vref=30, minBit 0, minWin=25, winSum=413
8192 12:42:00.621007 TX Vref=32, minBit 0, minWin=24, winSum=407
8193 12:42:00.624468 TX Vref=34, minBit 13, minWin=23, winSum=398
8194 12:42:00.627735 TX Vref=36, minBit 4, minWin=23, winSum=389
8195 12:42:00.634540 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 28
8196 12:42:00.634640
8197 12:42:00.637473 Final TX Range 0 Vref 28
8198 12:42:00.637570
8199 12:42:00.637658 ==
8200 12:42:00.640904 Dram Type= 6, Freq= 0, CH_0, rank 1
8201 12:42:00.644378 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8202 12:42:00.644449 ==
8203 12:42:00.644510
8204 12:42:00.647732
8205 12:42:00.647802 TX Vref Scan disable
8206 12:42:00.654382 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8207 12:42:00.654463 == TX Byte 0 ==
8208 12:42:00.657521 u2DelayCellOfst[0]=14 cells (4 PI)
8209 12:42:00.660830 u2DelayCellOfst[1]=17 cells (5 PI)
8210 12:42:00.664069 u2DelayCellOfst[2]=10 cells (3 PI)
8211 12:42:00.667891 u2DelayCellOfst[3]=10 cells (3 PI)
8212 12:42:00.671067 u2DelayCellOfst[4]=10 cells (3 PI)
8213 12:42:00.674107 u2DelayCellOfst[5]=0 cells (0 PI)
8214 12:42:00.677599 u2DelayCellOfst[6]=17 cells (5 PI)
8215 12:42:00.680611 u2DelayCellOfst[7]=17 cells (5 PI)
8216 12:42:00.684045 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8217 12:42:00.687381 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8218 12:42:00.690596 == TX Byte 1 ==
8219 12:42:00.694129 u2DelayCellOfst[8]=0 cells (0 PI)
8220 12:42:00.697383 u2DelayCellOfst[9]=0 cells (0 PI)
8221 12:42:00.700828 u2DelayCellOfst[10]=7 cells (2 PI)
8222 12:42:00.700900 u2DelayCellOfst[11]=0 cells (0 PI)
8223 12:42:00.704320 u2DelayCellOfst[12]=10 cells (3 PI)
8224 12:42:00.707629 u2DelayCellOfst[13]=10 cells (3 PI)
8225 12:42:00.711130 u2DelayCellOfst[14]=14 cells (4 PI)
8226 12:42:00.714065 u2DelayCellOfst[15]=10 cells (3 PI)
8227 12:42:00.720423 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8228 12:42:00.724124 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8229 12:42:00.724241 DramC Write-DBI on
8230 12:42:00.724336 ==
8231 12:42:00.727222 Dram Type= 6, Freq= 0, CH_0, rank 1
8232 12:42:00.733695 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8233 12:42:00.733806 ==
8234 12:42:00.733898
8235 12:42:00.733987
8236 12:42:00.734083 TX Vref Scan disable
8237 12:42:00.738079 == TX Byte 0 ==
8238 12:42:00.741120 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8239 12:42:00.744709 == TX Byte 1 ==
8240 12:42:00.747773 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8241 12:42:00.751295 DramC Write-DBI off
8242 12:42:00.751397
8243 12:42:00.751468 [DATLAT]
8244 12:42:00.751528 Freq=1600, CH0 RK1
8245 12:42:00.751587
8246 12:42:00.755075 DATLAT Default: 0xf
8247 12:42:00.758425 0, 0xFFFF, sum = 0
8248 12:42:00.758525 1, 0xFFFF, sum = 0
8249 12:42:00.761325 2, 0xFFFF, sum = 0
8250 12:42:00.761424 3, 0xFFFF, sum = 0
8251 12:42:00.764468 4, 0xFFFF, sum = 0
8252 12:42:00.764543 5, 0xFFFF, sum = 0
8253 12:42:00.767831 6, 0xFFFF, sum = 0
8254 12:42:00.767904 7, 0xFFFF, sum = 0
8255 12:42:00.771454 8, 0xFFFF, sum = 0
8256 12:42:00.771554 9, 0xFFFF, sum = 0
8257 12:42:00.774684 10, 0xFFFF, sum = 0
8258 12:42:00.774792 11, 0xFFFF, sum = 0
8259 12:42:00.777556 12, 0xFFFF, sum = 0
8260 12:42:00.777663 13, 0xFFFF, sum = 0
8261 12:42:00.781080 14, 0x0, sum = 1
8262 12:42:00.781154 15, 0x0, sum = 2
8263 12:42:00.784759 16, 0x0, sum = 3
8264 12:42:00.784859 17, 0x0, sum = 4
8265 12:42:00.787569 best_step = 15
8266 12:42:00.787641
8267 12:42:00.787702 ==
8268 12:42:00.791649 Dram Type= 6, Freq= 0, CH_0, rank 1
8269 12:42:00.794460 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8270 12:42:00.794556 ==
8271 12:42:00.797670 RX Vref Scan: 0
8272 12:42:00.797766
8273 12:42:00.797833 RX Vref 0 -> 0, step: 1
8274 12:42:00.797895
8275 12:42:00.800858 RX Delay 11 -> 252, step: 4
8276 12:42:00.804825 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8277 12:42:00.810774 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8278 12:42:00.814373 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8279 12:42:00.817830 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8280 12:42:00.821009 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8281 12:42:00.824051 iDelay=191, Bit 5, Center 114 (59 ~ 170) 112
8282 12:42:00.830650 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8283 12:42:00.833832 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8284 12:42:00.837398 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8285 12:42:00.840798 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8286 12:42:00.844228 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8287 12:42:00.850533 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8288 12:42:00.854139 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8289 12:42:00.857529 iDelay=191, Bit 13, Center 130 (75 ~ 186) 112
8290 12:42:00.860419 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8291 12:42:00.867764 iDelay=191, Bit 15, Center 132 (75 ~ 190) 116
8292 12:42:00.867863 ==
8293 12:42:00.870684 Dram Type= 6, Freq= 0, CH_0, rank 1
8294 12:42:00.874015 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8295 12:42:00.874112 ==
8296 12:42:00.874209 DQS Delay:
8297 12:42:00.877732 DQS0 = 0, DQS1 = 0
8298 12:42:00.877827 DQM Delay:
8299 12:42:00.880630 DQM0 = 126, DQM1 = 123
8300 12:42:00.880700 DQ Delay:
8301 12:42:00.883597 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8302 12:42:00.887131 DQ4 =124, DQ5 =114, DQ6 =134, DQ7 =134
8303 12:42:00.890618 DQ8 =114, DQ9 =112, DQ10 =122, DQ11 =116
8304 12:42:00.894052 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =132
8305 12:42:00.894148
8306 12:42:00.894243
8307 12:42:00.897379
8308 12:42:00.897450 [DramC_TX_OE_Calibration] TA2
8309 12:42:00.900477 Original DQ_B0 (3 6) =30, OEN = 27
8310 12:42:00.903901 Original DQ_B1 (3 6) =30, OEN = 27
8311 12:42:00.907558 24, 0x0, End_B0=24 End_B1=24
8312 12:42:00.910358 25, 0x0, End_B0=25 End_B1=25
8313 12:42:00.913588 26, 0x0, End_B0=26 End_B1=26
8314 12:42:00.913660 27, 0x0, End_B0=27 End_B1=27
8315 12:42:00.917163 28, 0x0, End_B0=28 End_B1=28
8316 12:42:00.920308 29, 0x0, End_B0=29 End_B1=29
8317 12:42:00.924022 30, 0x0, End_B0=30 End_B1=30
8318 12:42:00.924126 31, 0x4141, End_B0=30 End_B1=30
8319 12:42:00.927041 Byte0 end_step=30 best_step=27
8320 12:42:00.930380 Byte1 end_step=30 best_step=27
8321 12:42:00.933740 Byte0 TX OE(2T, 0.5T) = (3, 3)
8322 12:42:00.937179 Byte1 TX OE(2T, 0.5T) = (3, 3)
8323 12:42:00.937277
8324 12:42:00.937373
8325 12:42:00.943641 [DQSOSCAuto] RK1, (LSB)MR18= 0x180c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
8326 12:42:00.946981 CH0 RK1: MR19=303, MR18=180C
8327 12:42:00.953504 CH0_RK1: MR19=0x303, MR18=0x180C, DQSOSC=397, MR23=63, INC=23, DEC=15
8328 12:42:00.957183 [RxdqsGatingPostProcess] freq 1600
8329 12:42:00.963563 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8330 12:42:00.966989 best DQS0 dly(2T, 0.5T) = (1, 1)
8331 12:42:00.967087 best DQS1 dly(2T, 0.5T) = (1, 1)
8332 12:42:00.969977 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8333 12:42:00.973539 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8334 12:42:00.976679 best DQS0 dly(2T, 0.5T) = (1, 1)
8335 12:42:00.980034 best DQS1 dly(2T, 0.5T) = (1, 1)
8336 12:42:00.983647 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8337 12:42:00.987072 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8338 12:42:00.990302 Pre-setting of DQS Precalculation
8339 12:42:00.993640 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8340 12:42:00.993739 ==
8341 12:42:00.996668 Dram Type= 6, Freq= 0, CH_1, rank 0
8342 12:42:01.003625 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8343 12:42:01.003724 ==
8344 12:42:01.006838 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8345 12:42:01.013236 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8346 12:42:01.016853 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8347 12:42:01.022974 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8348 12:42:01.031305 [CA 0] Center 43 (15~72) winsize 58
8349 12:42:01.034599 [CA 1] Center 43 (14~72) winsize 59
8350 12:42:01.037663 [CA 2] Center 39 (11~67) winsize 57
8351 12:42:01.041140 [CA 3] Center 37 (8~67) winsize 60
8352 12:42:01.044668 [CA 4] Center 38 (9~68) winsize 60
8353 12:42:01.048009 [CA 5] Center 37 (8~66) winsize 59
8354 12:42:01.048084
8355 12:42:01.051551 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8356 12:42:01.051621
8357 12:42:01.054639 [CATrainingPosCal] consider 1 rank data
8358 12:42:01.057809 u2DelayCellTimex100 = 275/100 ps
8359 12:42:01.061254 CA0 delay=43 (15~72),Diff = 6 PI (21 cell)
8360 12:42:01.068357 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8361 12:42:01.070945 CA2 delay=39 (11~67),Diff = 2 PI (7 cell)
8362 12:42:01.074480 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8363 12:42:01.077902 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8364 12:42:01.080871 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8365 12:42:01.080953
8366 12:42:01.084688 CA PerBit enable=1, Macro0, CA PI delay=37
8367 12:42:01.084759
8368 12:42:01.087489 [CBTSetCACLKResult] CA Dly = 37
8369 12:42:01.091145 CS Dly: 8 (0~39)
8370 12:42:01.094375 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8371 12:42:01.098125 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8372 12:42:01.098227 ==
8373 12:42:01.101302 Dram Type= 6, Freq= 0, CH_1, rank 1
8374 12:42:01.104874 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8375 12:42:01.104951 ==
8376 12:42:01.111074 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8377 12:42:01.114417 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8378 12:42:01.120947 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8379 12:42:01.124385 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8380 12:42:01.134441 [CA 0] Center 43 (15~72) winsize 58
8381 12:42:01.138066 [CA 1] Center 43 (14~72) winsize 59
8382 12:42:01.141132 [CA 2] Center 38 (9~67) winsize 59
8383 12:42:01.144444 [CA 3] Center 37 (8~67) winsize 60
8384 12:42:01.147882 [CA 4] Center 38 (8~68) winsize 61
8385 12:42:01.151618 [CA 5] Center 37 (8~66) winsize 59
8386 12:42:01.151689
8387 12:42:01.154718 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8388 12:42:01.154786
8389 12:42:01.157817 [CATrainingPosCal] consider 2 rank data
8390 12:42:01.161040 u2DelayCellTimex100 = 275/100 ps
8391 12:42:01.164844 CA0 delay=43 (15~72),Diff = 6 PI (21 cell)
8392 12:42:01.171525 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8393 12:42:01.174265 CA2 delay=39 (11~67),Diff = 2 PI (7 cell)
8394 12:42:01.177687 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8395 12:42:01.181035 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8396 12:42:01.184164 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8397 12:42:01.184260
8398 12:42:01.187588 CA PerBit enable=1, Macro0, CA PI delay=37
8399 12:42:01.187658
8400 12:42:01.191039 [CBTSetCACLKResult] CA Dly = 37
8401 12:42:01.194396 CS Dly: 10 (0~44)
8402 12:42:01.198075 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8403 12:42:01.201397 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8404 12:42:01.201499
8405 12:42:01.204289 ----->DramcWriteLeveling(PI) begin...
8406 12:42:01.204385 ==
8407 12:42:01.207533 Dram Type= 6, Freq= 0, CH_1, rank 0
8408 12:42:01.214232 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8409 12:42:01.214328 ==
8410 12:42:01.217719 Write leveling (Byte 0): 25 => 25
8411 12:42:01.217821 Write leveling (Byte 1): 28 => 28
8412 12:42:01.220861 DramcWriteLeveling(PI) end<-----
8413 12:42:01.220955
8414 12:42:01.221049 ==
8415 12:42:01.224389 Dram Type= 6, Freq= 0, CH_1, rank 0
8416 12:42:01.230918 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8417 12:42:01.231015 ==
8418 12:42:01.234361 [Gating] SW mode calibration
8419 12:42:01.241029 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8420 12:42:01.244135 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8421 12:42:01.250679 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8422 12:42:01.253838 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8423 12:42:01.257082 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8424 12:42:01.263872 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8425 12:42:01.267225 1 4 16 | B1->B0 | 3131 2828 | 1 0 | (0 0) (0 0)
8426 12:42:01.270632 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8427 12:42:01.277048 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8428 12:42:01.280628 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8429 12:42:01.284124 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8430 12:42:01.290495 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8431 12:42:01.293714 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8432 12:42:01.296988 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8433 12:42:01.303532 1 5 16 | B1->B0 | 3333 3434 | 0 1 | (0 1) (1 0)
8434 12:42:01.307175 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8435 12:42:01.310360 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8436 12:42:01.313618 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8437 12:42:01.320543 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8438 12:42:01.323610 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8439 12:42:01.326999 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8440 12:42:01.333445 1 6 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8441 12:42:01.336904 1 6 16 | B1->B0 | 3f3f 3333 | 0 0 | (0 0) (0 0)
8442 12:42:01.340203 1 6 20 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8443 12:42:01.346782 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8444 12:42:01.349850 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8445 12:42:01.353661 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8446 12:42:01.360187 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8447 12:42:01.363063 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8448 12:42:01.366682 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8449 12:42:01.373334 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8450 12:42:01.376674 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8451 12:42:01.379833 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 12:42:01.387008 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 12:42:01.389630 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 12:42:01.393142 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 12:42:01.400193 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 12:42:01.403051 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 12:42:01.406530 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8458 12:42:01.413180 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8459 12:42:01.416796 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8460 12:42:01.420226 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8461 12:42:01.426464 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8462 12:42:01.429564 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8463 12:42:01.432720 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8464 12:42:01.439469 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8465 12:42:01.442912 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8466 12:42:01.445948 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8467 12:42:01.449802 Total UI for P1: 0, mck2ui 16
8468 12:42:01.452910 best dqsien dly found for B0: ( 1, 9, 14)
8469 12:42:01.456252 Total UI for P1: 0, mck2ui 16
8470 12:42:01.459206 best dqsien dly found for B1: ( 1, 9, 16)
8471 12:42:01.462755 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8472 12:42:01.466146 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8473 12:42:01.466256
8474 12:42:01.472401 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8475 12:42:01.476163 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8476 12:42:01.476236 [Gating] SW calibration Done
8477 12:42:01.479340 ==
8478 12:42:01.482703 Dram Type= 6, Freq= 0, CH_1, rank 0
8479 12:42:01.486320 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8480 12:42:01.486435 ==
8481 12:42:01.486529 RX Vref Scan: 0
8482 12:42:01.486627
8483 12:42:01.489114 RX Vref 0 -> 0, step: 1
8484 12:42:01.489197
8485 12:42:01.492460 RX Delay 0 -> 252, step: 8
8486 12:42:01.495809 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8487 12:42:01.499011 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8488 12:42:01.502576 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8489 12:42:01.508952 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8490 12:42:01.512531 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8491 12:42:01.515660 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8492 12:42:01.518846 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8493 12:42:01.522332 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8494 12:42:01.528984 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8495 12:42:01.532265 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8496 12:42:01.535325 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8497 12:42:01.538569 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8498 12:42:01.545243 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8499 12:42:01.548534 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8500 12:42:01.551876 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8501 12:42:01.555203 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8502 12:42:01.555287 ==
8503 12:42:01.558460 Dram Type= 6, Freq= 0, CH_1, rank 0
8504 12:42:01.561861 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8505 12:42:01.565414 ==
8506 12:42:01.565497 DQS Delay:
8507 12:42:01.565563 DQS0 = 0, DQS1 = 0
8508 12:42:01.569005 DQM Delay:
8509 12:42:01.569088 DQM0 = 133, DQM1 = 127
8510 12:42:01.571748 DQ Delay:
8511 12:42:01.575127 DQ0 =139, DQ1 =127, DQ2 =119, DQ3 =135
8512 12:42:01.578383 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =127
8513 12:42:01.581614 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8514 12:42:01.585016 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8515 12:42:01.585100
8516 12:42:01.585165
8517 12:42:01.585226 ==
8518 12:42:01.588280 Dram Type= 6, Freq= 0, CH_1, rank 0
8519 12:42:01.591943 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8520 12:42:01.595248 ==
8521 12:42:01.595330
8522 12:42:01.595404
8523 12:42:01.595484 TX Vref Scan disable
8524 12:42:01.598686 == TX Byte 0 ==
8525 12:42:01.601541 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8526 12:42:01.605027 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8527 12:42:01.608442 == TX Byte 1 ==
8528 12:42:01.611514 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8529 12:42:01.615005 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8530 12:42:01.615088 ==
8531 12:42:01.618355 Dram Type= 6, Freq= 0, CH_1, rank 0
8532 12:42:01.624810 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8533 12:42:01.624893 ==
8534 12:42:01.636748
8535 12:42:01.639917 TX Vref early break, caculate TX vref
8536 12:42:01.643238 TX Vref=16, minBit 8, minWin=21, winSum=365
8537 12:42:01.646723 TX Vref=18, minBit 8, minWin=21, winSum=370
8538 12:42:01.649705 TX Vref=20, minBit 5, minWin=22, winSum=381
8539 12:42:01.653063 TX Vref=22, minBit 8, minWin=23, winSum=395
8540 12:42:01.656200 TX Vref=24, minBit 5, minWin=24, winSum=404
8541 12:42:01.663115 TX Vref=26, minBit 8, minWin=24, winSum=412
8542 12:42:01.666652 TX Vref=28, minBit 5, minWin=25, winSum=416
8543 12:42:01.669999 TX Vref=30, minBit 8, minWin=25, winSum=418
8544 12:42:01.672873 TX Vref=32, minBit 8, minWin=24, winSum=409
8545 12:42:01.676043 TX Vref=34, minBit 11, minWin=23, winSum=396
8546 12:42:01.683248 [TxChooseVref] Worse bit 8, Min win 25, Win sum 418, Final Vref 30
8547 12:42:01.683336
8548 12:42:01.686214 Final TX Range 0 Vref 30
8549 12:42:01.686298
8550 12:42:01.686363 ==
8551 12:42:01.689964 Dram Type= 6, Freq= 0, CH_1, rank 0
8552 12:42:01.692654 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8553 12:42:01.692738 ==
8554 12:42:01.692804
8555 12:42:01.692878
8556 12:42:01.695963 TX Vref Scan disable
8557 12:42:01.702933 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8558 12:42:01.703043 == TX Byte 0 ==
8559 12:42:01.705914 u2DelayCellOfst[0]=17 cells (5 PI)
8560 12:42:01.709470 u2DelayCellOfst[1]=14 cells (4 PI)
8561 12:42:01.713214 u2DelayCellOfst[2]=0 cells (0 PI)
8562 12:42:01.716050 u2DelayCellOfst[3]=7 cells (2 PI)
8563 12:42:01.719329 u2DelayCellOfst[4]=7 cells (2 PI)
8564 12:42:01.722731 u2DelayCellOfst[5]=17 cells (5 PI)
8565 12:42:01.725969 u2DelayCellOfst[6]=17 cells (5 PI)
8566 12:42:01.729383 u2DelayCellOfst[7]=7 cells (2 PI)
8567 12:42:01.732533 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8568 12:42:01.735895 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8569 12:42:01.739778 == TX Byte 1 ==
8570 12:42:01.739884 u2DelayCellOfst[8]=0 cells (0 PI)
8571 12:42:01.742980 u2DelayCellOfst[9]=3 cells (1 PI)
8572 12:42:01.745996 u2DelayCellOfst[10]=10 cells (3 PI)
8573 12:42:01.749348 u2DelayCellOfst[11]=7 cells (2 PI)
8574 12:42:01.752490 u2DelayCellOfst[12]=14 cells (4 PI)
8575 12:42:01.755891 u2DelayCellOfst[13]=17 cells (5 PI)
8576 12:42:01.759671 u2DelayCellOfst[14]=17 cells (5 PI)
8577 12:42:01.762704 u2DelayCellOfst[15]=17 cells (5 PI)
8578 12:42:01.765993 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8579 12:42:01.772360 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8580 12:42:01.772454 DramC Write-DBI on
8581 12:42:01.772524 ==
8582 12:42:01.776112 Dram Type= 6, Freq= 0, CH_1, rank 0
8583 12:42:01.782396 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8584 12:42:01.782493 ==
8585 12:42:01.782569
8586 12:42:01.782640
8587 12:42:01.782707 TX Vref Scan disable
8588 12:42:01.786198 == TX Byte 0 ==
8589 12:42:01.789246 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8590 12:42:01.792664 == TX Byte 1 ==
8591 12:42:01.795914 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8592 12:42:01.799257 DramC Write-DBI off
8593 12:42:01.799401
8594 12:42:01.799501 [DATLAT]
8595 12:42:01.799593 Freq=1600, CH1 RK0
8596 12:42:01.799682
8597 12:42:01.802649 DATLAT Default: 0xf
8598 12:42:01.802786 0, 0xFFFF, sum = 0
8599 12:42:01.806169 1, 0xFFFF, sum = 0
8600 12:42:01.809866 2, 0xFFFF, sum = 0
8601 12:42:01.810023 3, 0xFFFF, sum = 0
8602 12:42:01.813043 4, 0xFFFF, sum = 0
8603 12:42:01.813250 5, 0xFFFF, sum = 0
8604 12:42:01.815808 6, 0xFFFF, sum = 0
8605 12:42:01.815985 7, 0xFFFF, sum = 0
8606 12:42:01.819270 8, 0xFFFF, sum = 0
8607 12:42:01.819492 9, 0xFFFF, sum = 0
8608 12:42:01.822817 10, 0xFFFF, sum = 0
8609 12:42:01.823067 11, 0xFFFF, sum = 0
8610 12:42:01.826648 12, 0xFFFF, sum = 0
8611 12:42:01.827058 13, 0xFFFF, sum = 0
8612 12:42:01.829509 14, 0x0, sum = 1
8613 12:42:01.829822 15, 0x0, sum = 2
8614 12:42:01.832630 16, 0x0, sum = 3
8615 12:42:01.833030 17, 0x0, sum = 4
8616 12:42:01.837194 best_step = 15
8617 12:42:01.837713
8618 12:42:01.838053 ==
8619 12:42:01.839246 Dram Type= 6, Freq= 0, CH_1, rank 0
8620 12:42:01.842804 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8621 12:42:01.843238 ==
8622 12:42:01.845780 RX Vref Scan: 1
8623 12:42:01.846207
8624 12:42:01.846545 Set Vref Range= 24 -> 127
8625 12:42:01.846864
8626 12:42:01.849076 RX Vref 24 -> 127, step: 1
8627 12:42:01.849505
8628 12:42:01.852351 RX Delay 19 -> 252, step: 4
8629 12:42:01.852780
8630 12:42:01.856065 Set Vref, RX VrefLevel [Byte0]: 24
8631 12:42:01.859507 [Byte1]: 24
8632 12:42:01.860091
8633 12:42:01.863080 Set Vref, RX VrefLevel [Byte0]: 25
8634 12:42:01.866595 [Byte1]: 25
8635 12:42:01.869100
8636 12:42:01.869576 Set Vref, RX VrefLevel [Byte0]: 26
8637 12:42:01.872676 [Byte1]: 26
8638 12:42:01.876633
8639 12:42:01.877218 Set Vref, RX VrefLevel [Byte0]: 27
8640 12:42:01.880548 [Byte1]: 27
8641 12:42:01.884621
8642 12:42:01.885204 Set Vref, RX VrefLevel [Byte0]: 28
8643 12:42:01.887836 [Byte1]: 28
8644 12:42:01.892041
8645 12:42:01.892519 Set Vref, RX VrefLevel [Byte0]: 29
8646 12:42:01.895311 [Byte1]: 29
8647 12:42:01.899620
8648 12:42:01.900097 Set Vref, RX VrefLevel [Byte0]: 30
8649 12:42:01.902634 [Byte1]: 30
8650 12:42:01.907302
8651 12:42:01.907812 Set Vref, RX VrefLevel [Byte0]: 31
8652 12:42:01.910916 [Byte1]: 31
8653 12:42:01.914674
8654 12:42:01.915267 Set Vref, RX VrefLevel [Byte0]: 32
8655 12:42:01.918619 [Byte1]: 32
8656 12:42:01.922634
8657 12:42:01.923204 Set Vref, RX VrefLevel [Byte0]: 33
8658 12:42:01.925350 [Byte1]: 33
8659 12:42:01.930078
8660 12:42:01.930643 Set Vref, RX VrefLevel [Byte0]: 34
8661 12:42:01.933605 [Byte1]: 34
8662 12:42:01.937712
8663 12:42:01.938281 Set Vref, RX VrefLevel [Byte0]: 35
8664 12:42:01.940878 [Byte1]: 35
8665 12:42:01.944838
8666 12:42:01.945411 Set Vref, RX VrefLevel [Byte0]: 36
8667 12:42:01.948299 [Byte1]: 36
8668 12:42:01.952900
8669 12:42:01.953469 Set Vref, RX VrefLevel [Byte0]: 37
8670 12:42:01.955866 [Byte1]: 37
8671 12:42:01.960317
8672 12:42:01.960885 Set Vref, RX VrefLevel [Byte0]: 38
8673 12:42:01.963346 [Byte1]: 38
8674 12:42:01.968157
8675 12:42:01.968729 Set Vref, RX VrefLevel [Byte0]: 39
8676 12:42:01.971037 [Byte1]: 39
8677 12:42:01.975216
8678 12:42:01.975874 Set Vref, RX VrefLevel [Byte0]: 40
8679 12:42:01.978790 [Byte1]: 40
8680 12:42:01.983233
8681 12:42:01.983855 Set Vref, RX VrefLevel [Byte0]: 41
8682 12:42:01.986611 [Byte1]: 41
8683 12:42:01.990410
8684 12:42:01.990881 Set Vref, RX VrefLevel [Byte0]: 42
8685 12:42:01.993512 [Byte1]: 42
8686 12:42:01.997952
8687 12:42:01.998587 Set Vref, RX VrefLevel [Byte0]: 43
8688 12:42:02.000930 [Byte1]: 43
8689 12:42:02.005621
8690 12:42:02.006191 Set Vref, RX VrefLevel [Byte0]: 44
8691 12:42:02.008974 [Byte1]: 44
8692 12:42:02.013246
8693 12:42:02.013714 Set Vref, RX VrefLevel [Byte0]: 45
8694 12:42:02.016100 [Byte1]: 45
8695 12:42:02.020987
8696 12:42:02.021550 Set Vref, RX VrefLevel [Byte0]: 46
8697 12:42:02.024191 [Byte1]: 46
8698 12:42:02.028629
8699 12:42:02.029195 Set Vref, RX VrefLevel [Byte0]: 47
8700 12:42:02.032282 [Byte1]: 47
8701 12:42:02.035553
8702 12:42:02.036018 Set Vref, RX VrefLevel [Byte0]: 48
8703 12:42:02.039731 [Byte1]: 48
8704 12:42:02.043340
8705 12:42:02.043952 Set Vref, RX VrefLevel [Byte0]: 49
8706 12:42:02.046981 [Byte1]: 49
8707 12:42:02.051037
8708 12:42:02.051649 Set Vref, RX VrefLevel [Byte0]: 50
8709 12:42:02.054593 [Byte1]: 50
8710 12:42:02.058872
8711 12:42:02.059485 Set Vref, RX VrefLevel [Byte0]: 51
8712 12:42:02.061749 [Byte1]: 51
8713 12:42:02.066563
8714 12:42:02.067138 Set Vref, RX VrefLevel [Byte0]: 52
8715 12:42:02.069510 [Byte1]: 52
8716 12:42:02.073377
8717 12:42:02.073849 Set Vref, RX VrefLevel [Byte0]: 53
8718 12:42:02.076811 [Byte1]: 53
8719 12:42:02.081558
8720 12:42:02.082126 Set Vref, RX VrefLevel [Byte0]: 54
8721 12:42:02.084665 [Byte1]: 54
8722 12:42:02.089079
8723 12:42:02.089659 Set Vref, RX VrefLevel [Byte0]: 55
8724 12:42:02.092676 [Byte1]: 55
8725 12:42:02.096670
8726 12:42:02.097324 Set Vref, RX VrefLevel [Byte0]: 56
8727 12:42:02.099829 [Byte1]: 56
8728 12:42:02.104158
8729 12:42:02.104737 Set Vref, RX VrefLevel [Byte0]: 57
8730 12:42:02.107193 [Byte1]: 57
8731 12:42:02.111818
8732 12:42:02.112397 Set Vref, RX VrefLevel [Byte0]: 58
8733 12:42:02.114794 [Byte1]: 58
8734 12:42:02.119054
8735 12:42:02.119689 Set Vref, RX VrefLevel [Byte0]: 59
8736 12:42:02.122777 [Byte1]: 59
8737 12:42:02.127151
8738 12:42:02.127886 Set Vref, RX VrefLevel [Byte0]: 60
8739 12:42:02.130290 [Byte1]: 60
8740 12:42:02.134230
8741 12:42:02.134708 Set Vref, RX VrefLevel [Byte0]: 61
8742 12:42:02.137241 [Byte1]: 61
8743 12:42:02.142038
8744 12:42:02.142524 Set Vref, RX VrefLevel [Byte0]: 62
8745 12:42:02.145249 [Byte1]: 62
8746 12:42:02.149843
8747 12:42:02.150439 Set Vref, RX VrefLevel [Byte0]: 63
8748 12:42:02.152923 [Byte1]: 63
8749 12:42:02.157084
8750 12:42:02.157703 Set Vref, RX VrefLevel [Byte0]: 64
8751 12:42:02.160807 [Byte1]: 64
8752 12:42:02.164212
8753 12:42:02.164689 Set Vref, RX VrefLevel [Byte0]: 65
8754 12:42:02.171132 [Byte1]: 65
8755 12:42:02.171754
8756 12:42:02.174344 Set Vref, RX VrefLevel [Byte0]: 66
8757 12:42:02.177461 [Byte1]: 66
8758 12:42:02.177940
8759 12:42:02.181229 Set Vref, RX VrefLevel [Byte0]: 67
8760 12:42:02.184356 [Byte1]: 67
8761 12:42:02.184938
8762 12:42:02.187635 Set Vref, RX VrefLevel [Byte0]: 68
8763 12:42:02.190637 [Byte1]: 68
8764 12:42:02.195399
8765 12:42:02.195985 Set Vref, RX VrefLevel [Byte0]: 69
8766 12:42:02.197846 [Byte1]: 69
8767 12:42:02.202234
8768 12:42:02.202708 Set Vref, RX VrefLevel [Byte0]: 70
8769 12:42:02.205587 [Byte1]: 70
8770 12:42:02.210309
8771 12:42:02.210887 Set Vref, RX VrefLevel [Byte0]: 71
8772 12:42:02.213147 [Byte1]: 71
8773 12:42:02.217672
8774 12:42:02.218144 Set Vref, RX VrefLevel [Byte0]: 72
8775 12:42:02.220491 [Byte1]: 72
8776 12:42:02.224751
8777 12:42:02.225228 Set Vref, RX VrefLevel [Byte0]: 73
8778 12:42:02.228093 [Byte1]: 73
8779 12:42:02.232843
8780 12:42:02.233377 Set Vref, RX VrefLevel [Byte0]: 74
8781 12:42:02.236189 [Byte1]: 74
8782 12:42:02.240431
8783 12:42:02.240866 Final RX Vref Byte 0 = 61 to rank0
8784 12:42:02.243298 Final RX Vref Byte 1 = 55 to rank0
8785 12:42:02.246571 Final RX Vref Byte 0 = 61 to rank1
8786 12:42:02.250612 Final RX Vref Byte 1 = 55 to rank1==
8787 12:42:02.253367 Dram Type= 6, Freq= 0, CH_1, rank 0
8788 12:42:02.260174 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8789 12:42:02.260715 ==
8790 12:42:02.261065 DQS Delay:
8791 12:42:02.263759 DQS0 = 0, DQS1 = 0
8792 12:42:02.264341 DQM Delay:
8793 12:42:02.264703 DQM0 = 131, DQM1 = 124
8794 12:42:02.267059 DQ Delay:
8795 12:42:02.270149 DQ0 =138, DQ1 =126, DQ2 =120, DQ3 =130
8796 12:42:02.273161 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8797 12:42:02.276650 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
8798 12:42:02.280062 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8799 12:42:02.280613
8800 12:42:02.280962
8801 12:42:02.281282
8802 12:42:02.283668 [DramC_TX_OE_Calibration] TA2
8803 12:42:02.286552 Original DQ_B0 (3 6) =30, OEN = 27
8804 12:42:02.290181 Original DQ_B1 (3 6) =30, OEN = 27
8805 12:42:02.293052 24, 0x0, End_B0=24 End_B1=24
8806 12:42:02.293596 25, 0x0, End_B0=25 End_B1=25
8807 12:42:02.296957 26, 0x0, End_B0=26 End_B1=26
8808 12:42:02.299755 27, 0x0, End_B0=27 End_B1=27
8809 12:42:02.302991 28, 0x0, End_B0=28 End_B1=28
8810 12:42:02.306338 29, 0x0, End_B0=29 End_B1=29
8811 12:42:02.306777 30, 0x0, End_B0=30 End_B1=30
8812 12:42:02.310130 31, 0x4545, End_B0=30 End_B1=30
8813 12:42:02.313147 Byte0 end_step=30 best_step=27
8814 12:42:02.316303 Byte1 end_step=30 best_step=27
8815 12:42:02.319909 Byte0 TX OE(2T, 0.5T) = (3, 3)
8816 12:42:02.323213 Byte1 TX OE(2T, 0.5T) = (3, 3)
8817 12:42:02.323786
8818 12:42:02.324137
8819 12:42:02.329619 [DQSOSCAuto] RK0, (LSB)MR18= 0x13fe, (MSB)MR19= 0x302, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
8820 12:42:02.333423 CH1 RK0: MR19=302, MR18=13FE
8821 12:42:02.340137 CH1_RK0: MR19=0x302, MR18=0x13FE, DQSOSC=400, MR23=63, INC=23, DEC=15
8822 12:42:02.340681
8823 12:42:02.342868 ----->DramcWriteLeveling(PI) begin...
8824 12:42:02.343312 ==
8825 12:42:02.346214 Dram Type= 6, Freq= 0, CH_1, rank 1
8826 12:42:02.349892 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8827 12:42:02.350442 ==
8828 12:42:02.353313 Write leveling (Byte 0): 23 => 23
8829 12:42:02.356206 Write leveling (Byte 1): 27 => 27
8830 12:42:02.359835 DramcWriteLeveling(PI) end<-----
8831 12:42:02.360377
8832 12:42:02.360725 ==
8833 12:42:02.362811 Dram Type= 6, Freq= 0, CH_1, rank 1
8834 12:42:02.366154 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8835 12:42:02.366591 ==
8836 12:42:02.369871 [Gating] SW mode calibration
8837 12:42:02.375898 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8838 12:42:02.382974 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8839 12:42:02.386224 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8840 12:42:02.393203 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8841 12:42:02.395879 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8842 12:42:02.399096 1 4 12 | B1->B0 | 2625 3434 | 1 1 | (0 0) (1 1)
8843 12:42:02.405855 1 4 16 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
8844 12:42:02.409599 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8845 12:42:02.412741 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8846 12:42:02.418958 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8847 12:42:02.422671 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8848 12:42:02.425579 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8849 12:42:02.432824 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
8850 12:42:02.435966 1 5 12 | B1->B0 | 2e2e 2323 | 1 0 | (0 1) (0 0)
8851 12:42:02.439331 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8852 12:42:02.442038 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8853 12:42:02.448955 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8854 12:42:02.452223 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8855 12:42:02.455744 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8856 12:42:02.462110 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8857 12:42:02.465724 1 6 8 | B1->B0 | 2424 3737 | 0 0 | (0 0) (1 1)
8858 12:42:02.469348 1 6 12 | B1->B0 | 3333 4545 | 0 0 | (0 0) (0 0)
8859 12:42:02.475745 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8860 12:42:02.479029 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8861 12:42:02.482201 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8862 12:42:02.488536 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8863 12:42:02.492048 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8864 12:42:02.495456 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8865 12:42:02.502033 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8866 12:42:02.505402 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8867 12:42:02.509145 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8868 12:42:02.515393 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 12:42:02.518846 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 12:42:02.521896 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8871 12:42:02.528241 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8872 12:42:02.532062 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8873 12:42:02.535390 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8874 12:42:02.541993 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8875 12:42:02.544973 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8876 12:42:02.548443 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8877 12:42:02.555102 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8878 12:42:02.558595 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8879 12:42:02.561493 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8880 12:42:02.568217 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8881 12:42:02.571763 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8882 12:42:02.575486 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8883 12:42:02.578688 Total UI for P1: 0, mck2ui 16
8884 12:42:02.581808 best dqsien dly found for B0: ( 1, 9, 6)
8885 12:42:02.585103 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8886 12:42:02.591954 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8887 12:42:02.594845 Total UI for P1: 0, mck2ui 16
8888 12:42:02.597960 best dqsien dly found for B1: ( 1, 9, 14)
8889 12:42:02.601693 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8890 12:42:02.605221 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8891 12:42:02.605532
8892 12:42:02.608072 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8893 12:42:02.611373 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8894 12:42:02.615022 [Gating] SW calibration Done
8895 12:42:02.615427 ==
8896 12:42:02.617850 Dram Type= 6, Freq= 0, CH_1, rank 1
8897 12:42:02.621396 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8898 12:42:02.621701 ==
8899 12:42:02.624636 RX Vref Scan: 0
8900 12:42:02.624938
8901 12:42:02.628182 RX Vref 0 -> 0, step: 1
8902 12:42:02.628483
8903 12:42:02.628721 RX Delay 0 -> 252, step: 8
8904 12:42:02.634496 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8905 12:42:02.638066 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8906 12:42:02.641124 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8907 12:42:02.644357 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8908 12:42:02.647847 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8909 12:42:02.654703 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8910 12:42:02.658138 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8911 12:42:02.660896 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8912 12:42:02.664402 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8913 12:42:02.667790 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8914 12:42:02.674591 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8915 12:42:02.677363 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8916 12:42:02.680789 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8917 12:42:02.684108 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8918 12:42:02.687292 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8919 12:42:02.694037 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8920 12:42:02.694164 ==
8921 12:42:02.697256 Dram Type= 6, Freq= 0, CH_1, rank 1
8922 12:42:02.700823 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8923 12:42:02.700933 ==
8924 12:42:02.701041 DQS Delay:
8925 12:42:02.704091 DQS0 = 0, DQS1 = 0
8926 12:42:02.704195 DQM Delay:
8927 12:42:02.707386 DQM0 = 132, DQM1 = 128
8928 12:42:02.707483 DQ Delay:
8929 12:42:02.710834 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8930 12:42:02.714020 DQ4 =135, DQ5 =147, DQ6 =139, DQ7 =127
8931 12:42:02.717235 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8932 12:42:02.720668 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8933 12:42:02.720758
8934 12:42:02.723670
8935 12:42:02.723759 ==
8936 12:42:02.727388 Dram Type= 6, Freq= 0, CH_1, rank 1
8937 12:42:02.730888 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8938 12:42:02.730978 ==
8939 12:42:02.731066
8940 12:42:02.731169
8941 12:42:02.733665 TX Vref Scan disable
8942 12:42:02.733767 == TX Byte 0 ==
8943 12:42:02.740267 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8944 12:42:02.743614 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8945 12:42:02.743707 == TX Byte 1 ==
8946 12:42:02.750279 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8947 12:42:02.753458 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8948 12:42:02.753582 ==
8949 12:42:02.756932 Dram Type= 6, Freq= 0, CH_1, rank 1
8950 12:42:02.760665 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8951 12:42:02.760774 ==
8952 12:42:02.775253
8953 12:42:02.778496 TX Vref early break, caculate TX vref
8954 12:42:02.781534 TX Vref=16, minBit 8, minWin=22, winSum=381
8955 12:42:02.784752 TX Vref=18, minBit 0, minWin=23, winSum=389
8956 12:42:02.788389 TX Vref=20, minBit 8, minWin=23, winSum=398
8957 12:42:02.791734 TX Vref=22, minBit 10, minWin=24, winSum=404
8958 12:42:02.794765 TX Vref=24, minBit 15, minWin=24, winSum=413
8959 12:42:02.801493 TX Vref=26, minBit 15, minWin=25, winSum=424
8960 12:42:02.805068 TX Vref=28, minBit 9, minWin=25, winSum=424
8961 12:42:02.808103 TX Vref=30, minBit 5, minWin=25, winSum=424
8962 12:42:02.811436 TX Vref=32, minBit 0, minWin=24, winSum=415
8963 12:42:02.814684 TX Vref=34, minBit 0, minWin=25, winSum=410
8964 12:42:02.818105 TX Vref=36, minBit 0, minWin=24, winSum=397
8965 12:42:02.824953 [TxChooseVref] Worse bit 15, Min win 25, Win sum 424, Final Vref 26
8966 12:42:02.825132
8967 12:42:02.827842 Final TX Range 0 Vref 26
8968 12:42:02.827987
8969 12:42:02.828107 ==
8970 12:42:02.831391 Dram Type= 6, Freq= 0, CH_1, rank 1
8971 12:42:02.834686 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8972 12:42:02.834904 ==
8973 12:42:02.838232
8974 12:42:02.838446
8975 12:42:02.838588 TX Vref Scan disable
8976 12:42:02.844600 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8977 12:42:02.844834 == TX Byte 0 ==
8978 12:42:02.848033 u2DelayCellOfst[0]=17 cells (5 PI)
8979 12:42:02.851186 u2DelayCellOfst[1]=14 cells (4 PI)
8980 12:42:02.854769 u2DelayCellOfst[2]=0 cells (0 PI)
8981 12:42:02.857699 u2DelayCellOfst[3]=7 cells (2 PI)
8982 12:42:02.861009 u2DelayCellOfst[4]=7 cells (2 PI)
8983 12:42:02.864696 u2DelayCellOfst[5]=17 cells (5 PI)
8984 12:42:02.867722 u2DelayCellOfst[6]=17 cells (5 PI)
8985 12:42:02.870983 u2DelayCellOfst[7]=7 cells (2 PI)
8986 12:42:02.874631 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8987 12:42:02.877847 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8988 12:42:02.881387 == TX Byte 1 ==
8989 12:42:02.884691 u2DelayCellOfst[8]=0 cells (0 PI)
8990 12:42:02.888040 u2DelayCellOfst[9]=7 cells (2 PI)
8991 12:42:02.891000 u2DelayCellOfst[10]=14 cells (4 PI)
8992 12:42:02.894655 u2DelayCellOfst[11]=10 cells (3 PI)
8993 12:42:02.895098 u2DelayCellOfst[12]=17 cells (5 PI)
8994 12:42:02.897642 u2DelayCellOfst[13]=21 cells (6 PI)
8995 12:42:02.900833 u2DelayCellOfst[14]=21 cells (6 PI)
8996 12:42:02.904359 u2DelayCellOfst[15]=21 cells (6 PI)
8997 12:42:02.910927 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8998 12:42:02.914636 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8999 12:42:02.915226 DramC Write-DBI on
9000 12:42:02.917683 ==
9001 12:42:02.918126 Dram Type= 6, Freq= 0, CH_1, rank 1
9002 12:42:02.924620 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9003 12:42:02.925095 ==
9004 12:42:02.925538
9005 12:42:02.925986
9006 12:42:02.927775 TX Vref Scan disable
9007 12:42:02.928206 == TX Byte 0 ==
9008 12:42:02.934757 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
9009 12:42:02.935323 == TX Byte 1 ==
9010 12:42:02.937660 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9011 12:42:02.940819 DramC Write-DBI off
9012 12:42:02.941278
9013 12:42:02.941623 [DATLAT]
9014 12:42:02.944282 Freq=1600, CH1 RK1
9015 12:42:02.944721
9016 12:42:02.945061 DATLAT Default: 0xf
9017 12:42:02.947512 0, 0xFFFF, sum = 0
9018 12:42:02.947956 1, 0xFFFF, sum = 0
9019 12:42:02.951401 2, 0xFFFF, sum = 0
9020 12:42:02.951836 3, 0xFFFF, sum = 0
9021 12:42:02.954464 4, 0xFFFF, sum = 0
9022 12:42:02.954898 5, 0xFFFF, sum = 0
9023 12:42:02.957801 6, 0xFFFF, sum = 0
9024 12:42:02.958310 7, 0xFFFF, sum = 0
9025 12:42:02.961120 8, 0xFFFF, sum = 0
9026 12:42:02.961552 9, 0xFFFF, sum = 0
9027 12:42:02.964631 10, 0xFFFF, sum = 0
9028 12:42:02.968013 11, 0xFFFF, sum = 0
9029 12:42:02.968453 12, 0xFFFF, sum = 0
9030 12:42:02.970839 13, 0xFFFF, sum = 0
9031 12:42:02.971294 14, 0x0, sum = 1
9032 12:42:02.974375 15, 0x0, sum = 2
9033 12:42:02.974810 16, 0x0, sum = 3
9034 12:42:02.977853 17, 0x0, sum = 4
9035 12:42:02.978294 best_step = 15
9036 12:42:02.978637
9037 12:42:02.979021 ==
9038 12:42:02.980679 Dram Type= 6, Freq= 0, CH_1, rank 1
9039 12:42:02.984166 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9040 12:42:02.984601 ==
9041 12:42:02.987552 RX Vref Scan: 0
9042 12:42:02.987982
9043 12:42:02.990426 RX Vref 0 -> 0, step: 1
9044 12:42:02.990854
9045 12:42:02.991196 RX Delay 11 -> 252, step: 4
9046 12:42:02.997808 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
9047 12:42:03.000870 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
9048 12:42:03.004505 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
9049 12:42:03.007236 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
9050 12:42:03.014254 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
9051 12:42:03.017620 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
9052 12:42:03.020626 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
9053 12:42:03.023964 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
9054 12:42:03.027180 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
9055 12:42:03.033934 iDelay=195, Bit 9, Center 114 (59 ~ 170) 112
9056 12:42:03.037107 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9057 12:42:03.040666 iDelay=195, Bit 11, Center 118 (67 ~ 170) 104
9058 12:42:03.044014 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
9059 12:42:03.047645 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
9060 12:42:03.053612 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
9061 12:42:03.057060 iDelay=195, Bit 15, Center 134 (83 ~ 186) 104
9062 12:42:03.057494 ==
9063 12:42:03.060510 Dram Type= 6, Freq= 0, CH_1, rank 1
9064 12:42:03.063728 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9065 12:42:03.064163 ==
9066 12:42:03.066914 DQS Delay:
9067 12:42:03.067341 DQS0 = 0, DQS1 = 0
9068 12:42:03.067729 DQM Delay:
9069 12:42:03.070338 DQM0 = 130, DQM1 = 126
9070 12:42:03.070766 DQ Delay:
9071 12:42:03.073488 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =130
9072 12:42:03.076879 DQ4 =128, DQ5 =144, DQ6 =138, DQ7 =126
9073 12:42:03.080454 DQ8 =114, DQ9 =114, DQ10 =128, DQ11 =118
9074 12:42:03.086907 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =134
9075 12:42:03.087337
9076 12:42:03.087706
9077 12:42:03.088023
9078 12:42:03.090237 [DramC_TX_OE_Calibration] TA2
9079 12:42:03.093466 Original DQ_B0 (3 6) =30, OEN = 27
9080 12:42:03.093901 Original DQ_B1 (3 6) =30, OEN = 27
9081 12:42:03.097102 24, 0x0, End_B0=24 End_B1=24
9082 12:42:03.100269 25, 0x0, End_B0=25 End_B1=25
9083 12:42:03.103569 26, 0x0, End_B0=26 End_B1=26
9084 12:42:03.106802 27, 0x0, End_B0=27 End_B1=27
9085 12:42:03.107446 28, 0x0, End_B0=28 End_B1=28
9086 12:42:03.110087 29, 0x0, End_B0=29 End_B1=29
9087 12:42:03.113576 30, 0x0, End_B0=30 End_B1=30
9088 12:42:03.116864 31, 0x4141, End_B0=30 End_B1=30
9089 12:42:03.119887 Byte0 end_step=30 best_step=27
9090 12:42:03.123497 Byte1 end_step=30 best_step=27
9091 12:42:03.124074 Byte0 TX OE(2T, 0.5T) = (3, 3)
9092 12:42:03.126812 Byte1 TX OE(2T, 0.5T) = (3, 3)
9093 12:42:03.127424
9094 12:42:03.127970
9095 12:42:03.136712 [DQSOSCAuto] RK1, (LSB)MR18= 0xd12, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
9096 12:42:03.137167 CH1 RK1: MR19=303, MR18=D12
9097 12:42:03.143494 CH1_RK1: MR19=0x303, MR18=0xD12, DQSOSC=400, MR23=63, INC=23, DEC=15
9098 12:42:03.146721 [RxdqsGatingPostProcess] freq 1600
9099 12:42:03.153418 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9100 12:42:03.156391 best DQS0 dly(2T, 0.5T) = (1, 1)
9101 12:42:03.160052 best DQS1 dly(2T, 0.5T) = (1, 1)
9102 12:42:03.163285 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9103 12:42:03.166919 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9104 12:42:03.167444 best DQS0 dly(2T, 0.5T) = (1, 1)
9105 12:42:03.169775 best DQS1 dly(2T, 0.5T) = (1, 1)
9106 12:42:03.173492 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9107 12:42:03.176337 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9108 12:42:03.179902 Pre-setting of DQS Precalculation
9109 12:42:03.186785 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9110 12:42:03.193381 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9111 12:42:03.199789 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9112 12:42:03.200224
9113 12:42:03.200565
9114 12:42:03.202661 [Calibration Summary] 3200 Mbps
9115 12:42:03.203123 CH 0, Rank 0
9116 12:42:03.206100 SW Impedance : PASS
9117 12:42:03.209486 DUTY Scan : NO K
9118 12:42:03.210062 ZQ Calibration : PASS
9119 12:42:03.212973 Jitter Meter : NO K
9120 12:42:03.216352 CBT Training : PASS
9121 12:42:03.216780 Write leveling : PASS
9122 12:42:03.219524 RX DQS gating : PASS
9123 12:42:03.223131 RX DQ/DQS(RDDQC) : PASS
9124 12:42:03.223640 TX DQ/DQS : PASS
9125 12:42:03.226179 RX DATLAT : PASS
9126 12:42:03.229114 RX DQ/DQS(Engine): PASS
9127 12:42:03.229666 TX OE : PASS
9128 12:42:03.230184 All Pass.
9129 12:42:03.232459
9130 12:42:03.232988 CH 0, Rank 1
9131 12:42:03.236128 SW Impedance : PASS
9132 12:42:03.236703 DUTY Scan : NO K
9133 12:42:03.239543 ZQ Calibration : PASS
9134 12:42:03.239973 Jitter Meter : NO K
9135 12:42:03.242896 CBT Training : PASS
9136 12:42:03.246292 Write leveling : PASS
9137 12:42:03.246847 RX DQS gating : PASS
9138 12:42:03.249231 RX DQ/DQS(RDDQC) : PASS
9139 12:42:03.252465 TX DQ/DQS : PASS
9140 12:42:03.252938 RX DATLAT : PASS
9141 12:42:03.255773 RX DQ/DQS(Engine): PASS
9142 12:42:03.259184 TX OE : PASS
9143 12:42:03.259696 All Pass.
9144 12:42:03.260213
9145 12:42:03.260704 CH 1, Rank 0
9146 12:42:03.262204 SW Impedance : PASS
9147 12:42:03.266304 DUTY Scan : NO K
9148 12:42:03.266903 ZQ Calibration : PASS
9149 12:42:03.268853 Jitter Meter : NO K
9150 12:42:03.272639 CBT Training : PASS
9151 12:42:03.273235 Write leveling : PASS
9152 12:42:03.275599 RX DQS gating : PASS
9153 12:42:03.278991 RX DQ/DQS(RDDQC) : PASS
9154 12:42:03.279582 TX DQ/DQS : PASS
9155 12:42:03.282306 RX DATLAT : PASS
9156 12:42:03.285370 RX DQ/DQS(Engine): PASS
9157 12:42:03.285801 TX OE : PASS
9158 12:42:03.288915 All Pass.
9159 12:42:03.289340
9160 12:42:03.289679 CH 1, Rank 1
9161 12:42:03.292239 SW Impedance : PASS
9162 12:42:03.292669 DUTY Scan : NO K
9163 12:42:03.295830 ZQ Calibration : PASS
9164 12:42:03.298805 Jitter Meter : NO K
9165 12:42:03.299234 CBT Training : PASS
9166 12:42:03.302057 Write leveling : PASS
9167 12:42:03.305197 RX DQS gating : PASS
9168 12:42:03.305629 RX DQ/DQS(RDDQC) : PASS
9169 12:42:03.308514 TX DQ/DQS : PASS
9170 12:42:03.308946 RX DATLAT : PASS
9171 12:42:03.311886 RX DQ/DQS(Engine): PASS
9172 12:42:03.315064 TX OE : PASS
9173 12:42:03.315531 All Pass.
9174 12:42:03.315905
9175 12:42:03.318659 DramC Write-DBI on
9176 12:42:03.319092 PER_BANK_REFRESH: Hybrid Mode
9177 12:42:03.322220 TX_TRACKING: ON
9178 12:42:03.332071 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9179 12:42:03.338480 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9180 12:42:03.345302 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9181 12:42:03.348035 [FAST_K] Save calibration result to emmc
9182 12:42:03.351471 sync common calibartion params.
9183 12:42:03.354830 sync cbt_mode0:1, 1:1
9184 12:42:03.358191 dram_init: ddr_geometry: 2
9185 12:42:03.358618 dram_init: ddr_geometry: 2
9186 12:42:03.361745 dram_init: ddr_geometry: 2
9187 12:42:03.364947 0:dram_rank_size:100000000
9188 12:42:03.365385 1:dram_rank_size:100000000
9189 12:42:03.371408 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9190 12:42:03.374798 DFS_SHUFFLE_HW_MODE: ON
9191 12:42:03.378073 dramc_set_vcore_voltage set vcore to 725000
9192 12:42:03.381505 Read voltage for 1600, 0
9193 12:42:03.382126 Vio18 = 0
9194 12:42:03.382610 Vcore = 725000
9195 12:42:03.384533 Vdram = 0
9196 12:42:03.384960 Vddq = 0
9197 12:42:03.385413 Vmddr = 0
9198 12:42:03.388408 switch to 3200 Mbps bootup
9199 12:42:03.388950 [DramcRunTimeConfig]
9200 12:42:03.391582 PHYPLL
9201 12:42:03.392045 DPM_CONTROL_AFTERK: ON
9202 12:42:03.394575 PER_BANK_REFRESH: ON
9203 12:42:03.397800 REFRESH_OVERHEAD_REDUCTION: ON
9204 12:42:03.398329 CMD_PICG_NEW_MODE: OFF
9205 12:42:03.401039 XRTWTW_NEW_MODE: ON
9206 12:42:03.401501 XRTRTR_NEW_MODE: ON
9207 12:42:03.404103 TX_TRACKING: ON
9208 12:42:03.404624 RDSEL_TRACKING: OFF
9209 12:42:03.407509 DQS Precalculation for DVFS: ON
9210 12:42:03.411066 RX_TRACKING: OFF
9211 12:42:03.411656 HW_GATING DBG: ON
9212 12:42:03.414577 ZQCS_ENABLE_LP4: ON
9213 12:42:03.415006 RX_PICG_NEW_MODE: ON
9214 12:42:03.417813 TX_PICG_NEW_MODE: ON
9215 12:42:03.421112 ENABLE_RX_DCM_DPHY: ON
9216 12:42:03.421543 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9217 12:42:03.424455 DUMMY_READ_FOR_TRACKING: OFF
9218 12:42:03.427886 !!! SPM_CONTROL_AFTERK: OFF
9219 12:42:03.430590 !!! SPM could not control APHY
9220 12:42:03.434606 IMPEDANCE_TRACKING: ON
9221 12:42:03.435037 TEMP_SENSOR: ON
9222 12:42:03.435399 HW_SAVE_FOR_SR: OFF
9223 12:42:03.437754 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9224 12:42:03.440733 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9225 12:42:03.444192 Read ODT Tracking: ON
9226 12:42:03.447949 Refresh Rate DeBounce: ON
9227 12:42:03.448442 DFS_NO_QUEUE_FLUSH: ON
9228 12:42:03.450797 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9229 12:42:03.454525 ENABLE_DFS_RUNTIME_MRW: OFF
9230 12:42:03.457727 DDR_RESERVE_NEW_MODE: ON
9231 12:42:03.458260 MR_CBT_SWITCH_FREQ: ON
9232 12:42:03.460719 =========================
9233 12:42:03.480349 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9234 12:42:03.483474 dram_init: ddr_geometry: 2
9235 12:42:03.501152 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9236 12:42:03.505199 dram_init: dram init end (result: 0)
9237 12:42:03.511164 DRAM-K: Full calibration passed in 24568 msecs
9238 12:42:03.515041 MRC: failed to locate region type 0.
9239 12:42:03.515508 DRAM rank0 size:0x100000000,
9240 12:42:03.518187 DRAM rank1 size=0x100000000
9241 12:42:03.527771 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9242 12:42:03.534608 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9243 12:42:03.541120 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9244 12:42:03.548088 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9245 12:42:03.551258 DRAM rank0 size:0x100000000,
9246 12:42:03.554497 DRAM rank1 size=0x100000000
9247 12:42:03.554993 CBMEM:
9248 12:42:03.557616 IMD: root @ 0xfffff000 254 entries.
9249 12:42:03.561038 IMD: root @ 0xffffec00 62 entries.
9250 12:42:03.564350 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9251 12:42:03.571153 WARNING: RO_VPD is uninitialized or empty.
9252 12:42:03.574207 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9253 12:42:03.581842 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9254 12:42:03.594372 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9255 12:42:03.605735 BS: romstage times (exec / console): total (unknown) / 24078 ms
9256 12:42:03.606252
9257 12:42:03.606750
9258 12:42:03.615632 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9259 12:42:03.619180 ARM64: Exception handlers installed.
9260 12:42:03.622334 ARM64: Testing exception
9261 12:42:03.625605 ARM64: Done test exception
9262 12:42:03.626050 Enumerating buses...
9263 12:42:03.629042 Show all devs... Before device enumeration.
9264 12:42:03.632240 Root Device: enabled 1
9265 12:42:03.635534 CPU_CLUSTER: 0: enabled 1
9266 12:42:03.636095 CPU: 00: enabled 1
9267 12:42:03.639037 Compare with tree...
9268 12:42:03.639505 Root Device: enabled 1
9269 12:42:03.642213 CPU_CLUSTER: 0: enabled 1
9270 12:42:03.645758 CPU: 00: enabled 1
9271 12:42:03.646187 Root Device scanning...
9272 12:42:03.649119 scan_static_bus for Root Device
9273 12:42:03.652459 CPU_CLUSTER: 0 enabled
9274 12:42:03.655527 scan_static_bus for Root Device done
9275 12:42:03.658779 scan_bus: bus Root Device finished in 8 msecs
9276 12:42:03.659111 done
9277 12:42:03.665464 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9278 12:42:03.668830 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9279 12:42:03.675500 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9280 12:42:03.678887 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9281 12:42:03.682364 Allocating resources...
9282 12:42:03.685553 Reading resources...
9283 12:42:03.688634 Root Device read_resources bus 0 link: 0
9284 12:42:03.688869 DRAM rank0 size:0x100000000,
9285 12:42:03.692104 DRAM rank1 size=0x100000000
9286 12:42:03.695295 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9287 12:42:03.698999 CPU: 00 missing read_resources
9288 12:42:03.701952 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9289 12:42:03.708294 Root Device read_resources bus 0 link: 0 done
9290 12:42:03.708619 Done reading resources.
9291 12:42:03.715388 Show resources in subtree (Root Device)...After reading.
9292 12:42:03.718883 Root Device child on link 0 CPU_CLUSTER: 0
9293 12:42:03.721497 CPU_CLUSTER: 0 child on link 0 CPU: 00
9294 12:42:03.731530 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9295 12:42:03.731762 CPU: 00
9296 12:42:03.735084 Root Device assign_resources, bus 0 link: 0
9297 12:42:03.738683 CPU_CLUSTER: 0 missing set_resources
9298 12:42:03.745619 Root Device assign_resources, bus 0 link: 0 done
9299 12:42:03.746049 Done setting resources.
9300 12:42:03.751680 Show resources in subtree (Root Device)...After assigning values.
9301 12:42:03.755317 Root Device child on link 0 CPU_CLUSTER: 0
9302 12:42:03.758675 CPU_CLUSTER: 0 child on link 0 CPU: 00
9303 12:42:03.768261 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9304 12:42:03.768691 CPU: 00
9305 12:42:03.771596 Done allocating resources.
9306 12:42:03.774852 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9307 12:42:03.778851 Enabling resources...
9308 12:42:03.779312 done.
9309 12:42:03.784775 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9310 12:42:03.785201 Initializing devices...
9311 12:42:03.788293 Root Device init
9312 12:42:03.788715 init hardware done!
9313 12:42:03.791716 0x00000018: ctrlr->caps
9314 12:42:03.795128 52.000 MHz: ctrlr->f_max
9315 12:42:03.795671 0.400 MHz: ctrlr->f_min
9316 12:42:03.798314 0x40ff8080: ctrlr->voltages
9317 12:42:03.798749 sclk: 390625
9318 12:42:03.801727 Bus Width = 1
9319 12:42:03.802151 sclk: 390625
9320 12:42:03.804658 Bus Width = 1
9321 12:42:03.805083 Early init status = 3
9322 12:42:03.811200 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9323 12:42:03.814971 in-header: 03 fb 00 00 01 00 00 00
9324 12:42:03.817720 in-data: 01
9325 12:42:03.821336 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9326 12:42:03.828527 in-header: 03 fb 00 00 01 00 00 00
9327 12:42:03.829144 in-data: 01
9328 12:42:03.831468 [SSUSB] Setting up USB HOST controller...
9329 12:42:03.834927 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9330 12:42:03.838553 [SSUSB] phy power-on done.
9331 12:42:03.841310 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9332 12:42:03.848368 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9333 12:42:03.851606 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9334 12:42:03.857720 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9335 12:42:03.864400 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9336 12:42:03.871183 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9337 12:42:03.877846 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9338 12:42:03.884502 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9339 12:42:03.887623 SPM: binary array size = 0x9dc
9340 12:42:03.890617 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9341 12:42:03.897417 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9342 12:42:03.904197 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9343 12:42:03.910939 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9344 12:42:03.914357 configure_display: Starting display init
9345 12:42:03.948869 anx7625_power_on_init: Init interface.
9346 12:42:03.952351 anx7625_disable_pd_protocol: Disabled PD feature.
9347 12:42:03.955462 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9348 12:42:03.983113 anx7625_start_dp_work: Secure OCM version=00
9349 12:42:03.986474 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9350 12:42:04.001037 sp_tx_get_edid_block: EDID Block = 1
9351 12:42:04.103920 Extracted contents:
9352 12:42:04.107325 header: 00 ff ff ff ff ff ff 00
9353 12:42:04.110708 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9354 12:42:04.113671 version: 01 04
9355 12:42:04.117077 basic params: 95 1f 11 78 0a
9356 12:42:04.120034 chroma info: 76 90 94 55 54 90 27 21 50 54
9357 12:42:04.123573 established: 00 00 00
9358 12:42:04.130560 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9359 12:42:04.133809 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9360 12:42:04.139901 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9361 12:42:04.146653 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9362 12:42:04.153625 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9363 12:42:04.156361 extensions: 00
9364 12:42:04.156655 checksum: fb
9365 12:42:04.156887
9366 12:42:04.159739 Manufacturer: IVO Model 57d Serial Number 0
9367 12:42:04.162888 Made week 0 of 2020
9368 12:42:04.163183 EDID version: 1.4
9369 12:42:04.166324 Digital display
9370 12:42:04.169701 6 bits per primary color channel
9371 12:42:04.170060 DisplayPort interface
9372 12:42:04.173188 Maximum image size: 31 cm x 17 cm
9373 12:42:04.176196 Gamma: 220%
9374 12:42:04.176567 Check DPMS levels
9375 12:42:04.180134 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9376 12:42:04.186330 First detailed timing is preferred timing
9377 12:42:04.186628 Established timings supported:
9378 12:42:04.189732 Standard timings supported:
9379 12:42:04.192886 Detailed timings
9380 12:42:04.196460 Hex of detail: 383680a07038204018303c0035ae10000019
9381 12:42:04.202943 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9382 12:42:04.206318 0780 0798 07c8 0820 hborder 0
9383 12:42:04.209691 0438 043b 0447 0458 vborder 0
9384 12:42:04.213226 -hsync -vsync
9385 12:42:04.213598 Did detailed timing
9386 12:42:04.219420 Hex of detail: 000000000000000000000000000000000000
9387 12:42:04.219726 Manufacturer-specified data, tag 0
9388 12:42:04.226757 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9389 12:42:04.229569 ASCII string: InfoVision
9390 12:42:04.232766 Hex of detail: 000000fe00523134304e574635205248200a
9391 12:42:04.236214 ASCII string: R140NWF5 RH
9392 12:42:04.236629 Checksum
9393 12:42:04.239126 Checksum: 0xfb (valid)
9394 12:42:04.242810 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9395 12:42:04.246431 DSI data_rate: 832800000 bps
9396 12:42:04.252642 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9397 12:42:04.255742 anx7625_parse_edid: pixelclock(138800).
9398 12:42:04.259415 hactive(1920), hsync(48), hfp(24), hbp(88)
9399 12:42:04.262645 vactive(1080), vsync(12), vfp(3), vbp(17)
9400 12:42:04.266145 anx7625_dsi_config: config dsi.
9401 12:42:04.272252 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9402 12:42:04.286061 anx7625_dsi_config: success to config DSI
9403 12:42:04.289296 anx7625_dp_start: MIPI phy setup OK.
9404 12:42:04.291966 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9405 12:42:04.295396 mtk_ddp_mode_set invalid vrefresh 60
9406 12:42:04.298882 main_disp_path_setup
9407 12:42:04.299178 ovl_layer_smi_id_en
9408 12:42:04.302537 ovl_layer_smi_id_en
9409 12:42:04.302837 ccorr_config
9410 12:42:04.303073 aal_config
9411 12:42:04.305622 gamma_config
9412 12:42:04.306063 postmask_config
9413 12:42:04.309058 dither_config
9414 12:42:04.312469 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9415 12:42:04.318825 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9416 12:42:04.322359 Root Device init finished in 531 msecs
9417 12:42:04.325321 CPU_CLUSTER: 0 init
9418 12:42:04.332159 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9419 12:42:04.335074 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9420 12:42:04.338828 APU_MBOX 0x190000b0 = 0x10001
9421 12:42:04.341892 APU_MBOX 0x190001b0 = 0x10001
9422 12:42:04.345524 APU_MBOX 0x190005b0 = 0x10001
9423 12:42:04.349138 APU_MBOX 0x190006b0 = 0x10001
9424 12:42:04.351908 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9425 12:42:04.364836 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9426 12:42:04.377281 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9427 12:42:04.383301 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9428 12:42:04.394891 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9429 12:42:04.404053 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9430 12:42:04.408065 CPU_CLUSTER: 0 init finished in 81 msecs
9431 12:42:04.410716 Devices initialized
9432 12:42:04.414718 Show all devs... After init.
9433 12:42:04.414802 Root Device: enabled 1
9434 12:42:04.417564 CPU_CLUSTER: 0: enabled 1
9435 12:42:04.420691 CPU: 00: enabled 1
9436 12:42:04.424245 BS: BS_DEV_INIT run times (exec / console): 208 / 428 ms
9437 12:42:04.427281 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9438 12:42:04.431107 ELOG: NV offset 0x57f000 size 0x1000
9439 12:42:04.437503 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9440 12:42:04.444762 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9441 12:42:04.447857 ELOG: Event(17) added with size 13 at 2023-06-14 12:42:04 UTC
9442 12:42:04.450853 out: cmd=0x121: 03 db 21 01 00 00 00 00
9443 12:42:04.454917 in-header: 03 ee 00 00 2c 00 00 00
9444 12:42:04.468242 in-data: 71 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9445 12:42:04.475232 ELOG: Event(A1) added with size 10 at 2023-06-14 12:42:05 UTC
9446 12:42:04.481453 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9447 12:42:04.487977 ELOG: Event(A0) added with size 9 at 2023-06-14 12:42:05 UTC
9448 12:42:04.491431 elog_add_boot_reason: Logged dev mode boot
9449 12:42:04.494963 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9450 12:42:04.497822 Finalize devices...
9451 12:42:04.498149 Devices finalized
9452 12:42:04.504779 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9453 12:42:04.507920 Writing coreboot table at 0xffe64000
9454 12:42:04.511452 0. 000000000010a000-0000000000113fff: RAMSTAGE
9455 12:42:04.514544 1. 0000000040000000-00000000400fffff: RAM
9456 12:42:04.521364 2. 0000000040100000-000000004032afff: RAMSTAGE
9457 12:42:04.524439 3. 000000004032b000-00000000545fffff: RAM
9458 12:42:04.527453 4. 0000000054600000-000000005465ffff: BL31
9459 12:42:04.530681 5. 0000000054660000-00000000ffe63fff: RAM
9460 12:42:04.537892 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9461 12:42:04.540673 7. 0000000100000000-000000023fffffff: RAM
9462 12:42:04.544091 Passing 5 GPIOs to payload:
9463 12:42:04.547752 NAME | PORT | POLARITY | VALUE
9464 12:42:04.550718 EC in RW | 0x000000aa | low | undefined
9465 12:42:04.557576 EC interrupt | 0x00000005 | low | undefined
9466 12:42:04.561016 TPM interrupt | 0x000000ab | high | undefined
9467 12:42:04.567513 SD card detect | 0x00000011 | high | undefined
9468 12:42:04.571459 speaker enable | 0x00000093 | high | undefined
9469 12:42:04.574390 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9470 12:42:04.577706 in-header: 03 f9 00 00 02 00 00 00
9471 12:42:04.578142 in-data: 02 00
9472 12:42:04.580735 ADC[4]: Raw value=900221 ID=7
9473 12:42:04.584349 ADC[3]: Raw value=213336 ID=1
9474 12:42:04.587305 RAM Code: 0x71
9475 12:42:04.587807 ADC[6]: Raw value=74557 ID=0
9476 12:42:04.590613 ADC[5]: Raw value=212598 ID=1
9477 12:42:04.594187 SKU Code: 0x1
9478 12:42:04.597396 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ded1
9479 12:42:04.600757 coreboot table: 964 bytes.
9480 12:42:04.603835 IMD ROOT 0. 0xfffff000 0x00001000
9481 12:42:04.607339 IMD SMALL 1. 0xffffe000 0x00001000
9482 12:42:04.610330 RO MCACHE 2. 0xffffc000 0x00001104
9483 12:42:04.614110 CONSOLE 3. 0xfff7c000 0x00080000
9484 12:42:04.617087 FMAP 4. 0xfff7b000 0x00000452
9485 12:42:04.620733 TIME STAMP 5. 0xfff7a000 0x00000910
9486 12:42:04.624023 VBOOT WORK 6. 0xfff66000 0x00014000
9487 12:42:04.627614 RAMOOPS 7. 0xffe66000 0x00100000
9488 12:42:04.630897 COREBOOT 8. 0xffe64000 0x00002000
9489 12:42:04.631498 IMD small region:
9490 12:42:04.633891 IMD ROOT 0. 0xffffec00 0x00000400
9491 12:42:04.637840 VPD 1. 0xffffeba0 0x0000004c
9492 12:42:04.640925 MMC STATUS 2. 0xffffeb80 0x00000004
9493 12:42:04.647054 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9494 12:42:04.650701 Probing TPM: done!
9495 12:42:04.653978 Connected to device vid:did:rid of 1ae0:0028:00
9496 12:42:04.664087 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9497 12:42:04.667191 Initialized TPM device CR50 revision 0
9498 12:42:04.671419 Checking cr50 for pending updates
9499 12:42:04.674585 Reading cr50 TPM mode
9500 12:42:04.683375 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9501 12:42:04.689642 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9502 12:42:04.729956 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9503 12:42:04.732991 Checking segment from ROM address 0x40100000
9504 12:42:04.736862 Checking segment from ROM address 0x4010001c
9505 12:42:04.743084 Loading segment from ROM address 0x40100000
9506 12:42:04.743620 code (compression=0)
9507 12:42:04.750225 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9508 12:42:04.759911 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9509 12:42:04.760375 it's not compressed!
9510 12:42:04.767060 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9511 12:42:04.770161 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9512 12:42:04.789925 Loading segment from ROM address 0x4010001c
9513 12:42:04.790523 Entry Point 0x80000000
9514 12:42:04.793932 Loaded segments
9515 12:42:04.796959 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9516 12:42:04.803687 Jumping to boot code at 0x80000000(0xffe64000)
9517 12:42:04.810412 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9518 12:42:04.816825 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9519 12:42:04.824451 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9520 12:42:04.827994 Checking segment from ROM address 0x40100000
9521 12:42:04.831426 Checking segment from ROM address 0x4010001c
9522 12:42:04.838031 Loading segment from ROM address 0x40100000
9523 12:42:04.838463 code (compression=1)
9524 12:42:04.845091 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9525 12:42:04.855082 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9526 12:42:04.855584 using LZMA
9527 12:42:04.863403 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9528 12:42:04.869763 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9529 12:42:04.873110 Loading segment from ROM address 0x4010001c
9530 12:42:04.873534 Entry Point 0x54601000
9531 12:42:04.876356 Loaded segments
9532 12:42:04.879247 NOTICE: MT8192 bl31_setup
9533 12:42:04.886383 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9534 12:42:04.889664 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9535 12:42:04.893106 WARNING: region 0:
9536 12:42:04.896710 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9537 12:42:04.897140 WARNING: region 1:
9538 12:42:04.903010 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9539 12:42:04.906333 WARNING: region 2:
9540 12:42:04.909998 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9541 12:42:04.913231 WARNING: region 3:
9542 12:42:04.916647 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9543 12:42:04.919759 WARNING: region 4:
9544 12:42:04.926336 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9545 12:42:04.926772 WARNING: region 5:
9546 12:42:04.930057 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9547 12:42:04.933298 WARNING: region 6:
9548 12:42:04.936885 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9549 12:42:04.937337 WARNING: region 7:
9550 12:42:04.943106 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9551 12:42:04.950134 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9552 12:42:04.953132 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9553 12:42:04.956668 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9554 12:42:04.963177 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9555 12:42:04.966360 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9556 12:42:04.969832 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9557 12:42:04.976682 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9558 12:42:04.979726 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9559 12:42:04.983322 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9560 12:42:04.990749 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9561 12:42:04.993502 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9562 12:42:04.999995 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9563 12:42:05.003580 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9564 12:42:05.006605 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9565 12:42:05.013495 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9566 12:42:05.016921 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9567 12:42:05.019975 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9568 12:42:05.026823 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9569 12:42:05.030051 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9570 12:42:05.033262 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9571 12:42:05.040254 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9572 12:42:05.043315 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9573 12:42:05.049971 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9574 12:42:05.053305 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9575 12:42:05.056581 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9576 12:42:05.063328 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9577 12:42:05.066610 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9578 12:42:05.073282 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9579 12:42:05.076348 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9580 12:42:05.080028 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9581 12:42:05.086154 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9582 12:42:05.089717 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9583 12:42:05.093207 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9584 12:42:05.099829 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9585 12:42:05.103225 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9586 12:42:05.106590 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9587 12:42:05.110148 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9588 12:42:05.116229 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9589 12:42:05.119542 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9590 12:42:05.122868 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9591 12:42:05.126552 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9592 12:42:05.132796 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9593 12:42:05.136291 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9594 12:42:05.139923 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9595 12:42:05.143318 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9596 12:42:05.149878 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9597 12:42:05.152796 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9598 12:42:05.156234 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9599 12:42:05.163172 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9600 12:42:05.166689 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9601 12:42:05.172979 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9602 12:42:05.176661 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9603 12:42:05.180096 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9604 12:42:05.186586 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9605 12:42:05.189749 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9606 12:42:05.196608 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9607 12:42:05.199837 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9608 12:42:05.203230 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9609 12:42:05.210357 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9610 12:42:05.213137 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9611 12:42:05.220134 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9612 12:42:05.223644 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9613 12:42:05.230162 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9614 12:42:05.233261 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9615 12:42:05.239849 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9616 12:42:05.243659 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9617 12:42:05.246498 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9618 12:42:05.253267 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9619 12:42:05.256829 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9620 12:42:05.263137 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9621 12:42:05.266657 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9622 12:42:05.270052 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9623 12:42:05.276778 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9624 12:42:05.279845 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9625 12:42:05.286518 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9626 12:42:05.289910 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9627 12:42:05.296614 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9628 12:42:05.300054 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9629 12:42:05.306870 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9630 12:42:05.310047 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9631 12:42:05.313413 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9632 12:42:05.320134 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9633 12:42:05.322989 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9634 12:42:05.329790 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9635 12:42:05.333596 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9636 12:42:05.340047 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9637 12:42:05.343218 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9638 12:42:05.346476 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9639 12:42:05.352988 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9640 12:42:05.356330 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9641 12:42:05.363893 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9642 12:42:05.366891 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9643 12:42:05.373194 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9644 12:42:05.376603 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9645 12:42:05.383210 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9646 12:42:05.387149 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9647 12:42:05.390090 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9648 12:42:05.393469 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9649 12:42:05.400364 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9650 12:42:05.403806 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9651 12:42:05.406886 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9652 12:42:05.413216 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9653 12:42:05.416770 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9654 12:42:05.420146 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9655 12:42:05.427015 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9656 12:42:05.429902 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9657 12:42:05.436565 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9658 12:42:05.440013 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9659 12:42:05.443346 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9660 12:42:05.449971 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9661 12:42:05.453567 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9662 12:42:05.460080 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9663 12:42:05.463141 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9664 12:42:05.466545 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9665 12:42:05.473716 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9666 12:42:05.476491 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9667 12:42:05.479842 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9668 12:42:05.486776 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9669 12:42:05.490279 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9670 12:42:05.493756 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9671 12:42:05.500209 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9672 12:42:05.503121 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9673 12:42:05.507019 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9674 12:42:05.510507 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9675 12:42:05.516885 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9676 12:42:05.520036 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9677 12:42:05.523063 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9678 12:42:05.529814 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9679 12:42:05.533154 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9680 12:42:05.540247 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9681 12:42:05.543511 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9682 12:42:05.546762 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9683 12:42:05.553210 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9684 12:42:05.556717 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9685 12:42:05.563511 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9686 12:42:05.566632 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9687 12:42:05.570065 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9688 12:42:05.576316 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9689 12:42:05.580106 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9690 12:42:05.583136 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9691 12:42:05.589959 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9692 12:42:05.593097 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9693 12:42:05.600089 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9694 12:42:05.602865 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9695 12:42:05.606219 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9696 12:42:05.613384 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9697 12:42:05.616732 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9698 12:42:05.623143 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9699 12:42:05.626001 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9700 12:42:05.629744 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9701 12:42:05.636577 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9702 12:42:05.639878 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9703 12:42:05.643341 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9704 12:42:05.649356 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9705 12:42:05.653246 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9706 12:42:05.659753 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9707 12:42:05.663068 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9708 12:42:05.666024 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9709 12:42:05.673176 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9710 12:42:05.676318 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9711 12:42:05.682981 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9712 12:42:05.685817 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9713 12:42:05.689449 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9714 12:42:05.696252 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9715 12:42:05.699658 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9716 12:42:05.702726 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9717 12:42:05.709494 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9718 12:42:05.712449 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9719 12:42:05.719393 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9720 12:42:05.722777 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9721 12:42:05.726272 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9722 12:42:05.732488 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9723 12:42:05.735773 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9724 12:42:05.742542 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9725 12:42:05.746444 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9726 12:42:05.749869 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9727 12:42:05.756406 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9728 12:42:05.759833 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9729 12:42:05.766227 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9730 12:42:05.769594 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9731 12:42:05.772920 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9732 12:42:05.779577 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9733 12:42:05.782414 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9734 12:42:05.788973 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9735 12:42:05.792840 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9736 12:42:05.795688 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9737 12:42:05.802431 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9738 12:42:05.806039 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9739 12:42:05.812124 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9740 12:42:05.815679 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9741 12:42:05.819072 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9742 12:42:05.825365 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9743 12:42:05.828718 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9744 12:42:05.835338 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9745 12:42:05.838899 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9746 12:42:05.845451 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9747 12:42:05.848345 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9748 12:42:05.852326 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9749 12:42:05.858284 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9750 12:42:05.861627 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9751 12:42:05.868348 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9752 12:42:05.871723 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9753 12:42:05.875244 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9754 12:42:05.881629 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9755 12:42:05.885807 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9756 12:42:05.891278 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9757 12:42:05.894848 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9758 12:42:05.902210 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9759 12:42:05.904906 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9760 12:42:05.908321 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9761 12:42:05.914681 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9762 12:42:05.918043 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9763 12:42:05.924785 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9764 12:42:05.927641 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9765 12:42:05.934977 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9766 12:42:05.938204 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9767 12:42:05.941115 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9768 12:42:05.947643 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9769 12:42:05.951716 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9770 12:42:05.957948 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9771 12:42:05.961572 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9772 12:42:05.964356 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9773 12:42:05.971553 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9774 12:42:05.974648 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9775 12:42:05.980869 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9776 12:42:05.984331 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9777 12:42:05.991278 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9778 12:42:05.994066 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9779 12:42:05.997413 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9780 12:42:06.004381 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9781 12:42:06.007750 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9782 12:42:06.010848 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9783 12:42:06.014358 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9784 12:42:06.017979 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9785 12:42:06.024064 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9786 12:42:06.027823 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9787 12:42:06.033787 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9788 12:42:06.037111 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9789 12:42:06.041046 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9790 12:42:06.047207 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9791 12:42:06.050439 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9792 12:42:06.056915 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9793 12:42:06.060895 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9794 12:42:06.063979 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9795 12:42:06.070484 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9796 12:42:06.073758 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9797 12:42:06.077236 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9798 12:42:06.083967 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9799 12:42:06.086779 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9800 12:42:06.090319 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9801 12:42:06.097162 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9802 12:42:06.100388 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9803 12:42:06.106773 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9804 12:42:06.110279 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9805 12:42:06.113817 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9806 12:42:06.120088 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9807 12:42:06.123732 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9808 12:42:06.127034 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9809 12:42:06.133994 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9810 12:42:06.136925 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9811 12:42:06.140309 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9812 12:42:06.147265 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9813 12:42:06.150125 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9814 12:42:06.153860 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9815 12:42:06.160566 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9816 12:42:06.163557 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9817 12:42:06.170517 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9818 12:42:06.173315 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9819 12:42:06.176771 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9820 12:42:06.183846 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9821 12:42:06.186666 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9822 12:42:06.190248 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9823 12:42:06.193902 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9824 12:42:06.196854 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9825 12:42:06.203523 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9826 12:42:06.206608 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9827 12:42:06.210698 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9828 12:42:06.213547 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9829 12:42:06.220030 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9830 12:42:06.223102 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9831 12:42:06.226654 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9832 12:42:06.233198 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9833 12:42:06.236893 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9834 12:42:06.239652 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9835 12:42:06.246624 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9836 12:42:06.249548 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9837 12:42:06.256369 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9838 12:42:06.259706 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9839 12:42:06.266805 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9840 12:42:06.269561 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9841 12:42:06.273152 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9842 12:42:06.279641 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9843 12:42:06.282705 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9844 12:42:06.289801 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9845 12:42:06.292787 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9846 12:42:06.295900 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9847 12:42:06.303802 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9848 12:42:06.306152 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9849 12:42:06.312561 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9850 12:42:06.315586 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9851 12:42:06.319591 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9852 12:42:06.325905 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9853 12:42:06.329188 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9854 12:42:06.336129 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9855 12:42:06.339653 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9856 12:42:06.342546 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9857 12:42:06.348840 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9858 12:42:06.352381 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9859 12:42:06.359096 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9860 12:42:06.362394 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9861 12:42:06.369387 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9862 12:42:06.372885 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9863 12:42:06.376472 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9864 12:42:06.382310 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9865 12:42:06.385452 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9866 12:42:06.392481 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9867 12:42:06.395598 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9868 12:42:06.399893 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9869 12:42:06.406049 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9870 12:42:06.409083 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9871 12:42:06.415102 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9872 12:42:06.418425 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9873 12:42:06.425704 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9874 12:42:06.428239 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9875 12:42:06.431609 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9876 12:42:06.438648 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9877 12:42:06.441872 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9878 12:42:06.448398 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9879 12:42:06.451442 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9880 12:42:06.454814 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9881 12:42:06.461260 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9882 12:42:06.464964 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9883 12:42:06.472088 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9884 12:42:06.475218 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9885 12:42:06.481715 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9886 12:42:06.485054 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9887 12:42:06.488312 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9888 12:42:06.494426 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9889 12:42:06.497974 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9890 12:42:06.504598 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9891 12:42:06.507641 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9892 12:42:06.511245 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9893 12:42:06.517880 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9894 12:42:06.521422 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9895 12:42:06.527553 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9896 12:42:06.531523 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9897 12:42:06.534498 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9898 12:42:06.541784 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9899 12:42:06.544736 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9900 12:42:06.551067 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9901 12:42:06.554750 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9902 12:42:06.560990 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9903 12:42:06.564612 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9904 12:42:06.567496 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9905 12:42:06.574663 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9906 12:42:06.578144 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9907 12:42:06.583992 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9908 12:42:06.588096 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9909 12:42:06.594430 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9910 12:42:06.598096 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9911 12:42:06.601000 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9912 12:42:06.607087 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9913 12:42:06.610896 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9914 12:42:06.617513 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9915 12:42:06.620883 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9916 12:42:06.624326 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9917 12:42:06.630890 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9918 12:42:06.634526 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9919 12:42:06.640891 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9920 12:42:06.644388 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9921 12:42:06.650641 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9922 12:42:06.654124 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9923 12:42:06.658187 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9924 12:42:06.663666 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9925 12:42:06.667008 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9926 12:42:06.674457 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9927 12:42:06.677251 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9928 12:42:06.683873 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9929 12:42:06.687412 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9930 12:42:06.694012 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9931 12:42:06.697958 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9932 12:42:06.700789 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9933 12:42:06.707503 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9934 12:42:06.711033 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9935 12:42:06.717433 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9936 12:42:06.720431 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9937 12:42:06.727522 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9938 12:42:06.730363 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9939 12:42:06.733709 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9940 12:42:06.740574 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9941 12:42:06.743506 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9942 12:42:06.749925 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9943 12:42:06.754187 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9944 12:42:06.760464 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9945 12:42:06.763740 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9946 12:42:06.766849 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9947 12:42:06.773453 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9948 12:42:06.776863 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9949 12:42:06.783574 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9950 12:42:06.786915 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9951 12:42:06.793848 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9952 12:42:06.796869 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9953 12:42:06.799969 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9954 12:42:06.806588 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9955 12:42:06.810139 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9956 12:42:06.816534 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9957 12:42:06.819851 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9958 12:42:06.826285 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9959 12:42:06.829853 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9960 12:42:06.836558 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9961 12:42:06.840045 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9962 12:42:06.846849 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9963 12:42:06.849855 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9964 12:42:06.856733 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9965 12:42:06.859813 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9966 12:42:06.866323 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9967 12:42:06.870190 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9968 12:42:06.873233 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9969 12:42:06.879912 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9970 12:42:06.883117 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9971 12:42:06.889759 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9972 12:42:06.892855 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9973 12:42:06.899918 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9974 12:42:06.903564 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9975 12:42:06.909814 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9976 12:42:06.913557 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9977 12:42:06.919954 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9978 12:42:06.923279 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9979 12:42:06.930065 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9980 12:42:06.933482 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9981 12:42:06.939786 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9982 12:42:06.942651 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9983 12:42:06.949653 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9984 12:42:06.952752 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9985 12:42:06.959695 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9986 12:42:06.960238 INFO: [APUAPC] vio 0
9987 12:42:06.966769 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9988 12:42:06.970158 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9989 12:42:06.973551 INFO: [APUAPC] D0_APC_0: 0x400510
9990 12:42:06.976758 INFO: [APUAPC] D0_APC_1: 0x0
9991 12:42:06.979987 INFO: [APUAPC] D0_APC_2: 0x1540
9992 12:42:06.983131 INFO: [APUAPC] D0_APC_3: 0x0
9993 12:42:06.986832 INFO: [APUAPC] D1_APC_0: 0xffffffff
9994 12:42:06.989780 INFO: [APUAPC] D1_APC_1: 0xffffffff
9995 12:42:06.993248 INFO: [APUAPC] D1_APC_2: 0x3fffff
9996 12:42:06.996492 INFO: [APUAPC] D1_APC_3: 0x0
9997 12:42:06.999918 INFO: [APUAPC] D2_APC_0: 0xffffffff
9998 12:42:07.003288 INFO: [APUAPC] D2_APC_1: 0xffffffff
9999 12:42:07.006652 INFO: [APUAPC] D2_APC_2: 0x3fffff
10000 12:42:07.009592 INFO: [APUAPC] D2_APC_3: 0x0
10001 12:42:07.013065 INFO: [APUAPC] D3_APC_0: 0xffffffff
10002 12:42:07.015669 INFO: [APUAPC] D3_APC_1: 0xffffffff
10003 12:42:07.019332 INFO: [APUAPC] D3_APC_2: 0x3fffff
10004 12:42:07.022201 INFO: [APUAPC] D3_APC_3: 0x0
10005 12:42:07.025842 INFO: [APUAPC] D4_APC_0: 0xffffffff
10006 12:42:07.029261 INFO: [APUAPC] D4_APC_1: 0xffffffff
10007 12:42:07.032106 INFO: [APUAPC] D4_APC_2: 0x3fffff
10008 12:42:07.035770 INFO: [APUAPC] D4_APC_3: 0x0
10009 12:42:07.038968 INFO: [APUAPC] D5_APC_0: 0xffffffff
10010 12:42:07.042296 INFO: [APUAPC] D5_APC_1: 0xffffffff
10011 12:42:07.045281 INFO: [APUAPC] D5_APC_2: 0x3fffff
10012 12:42:07.045377 INFO: [APUAPC] D5_APC_3: 0x0
10013 12:42:07.051676 INFO: [APUAPC] D6_APC_0: 0xffffffff
10014 12:42:07.055341 INFO: [APUAPC] D6_APC_1: 0xffffffff
10015 12:42:07.058588 INFO: [APUAPC] D6_APC_2: 0x3fffff
10016 12:42:07.058674 INFO: [APUAPC] D6_APC_3: 0x0
10017 12:42:07.062129 INFO: [APUAPC] D7_APC_0: 0xffffffff
10018 12:42:07.068454 INFO: [APUAPC] D7_APC_1: 0xffffffff
10019 12:42:07.068540 INFO: [APUAPC] D7_APC_2: 0x3fffff
10020 12:42:07.071920 INFO: [APUAPC] D7_APC_3: 0x0
10021 12:42:07.074947 INFO: [APUAPC] D8_APC_0: 0xffffffff
10022 12:42:07.078766 INFO: [APUAPC] D8_APC_1: 0xffffffff
10023 12:42:07.081529 INFO: [APUAPC] D8_APC_2: 0x3fffff
10024 12:42:07.085257 INFO: [APUAPC] D8_APC_3: 0x0
10025 12:42:07.088492 INFO: [APUAPC] D9_APC_0: 0xffffffff
10026 12:42:07.092109 INFO: [APUAPC] D9_APC_1: 0xffffffff
10027 12:42:07.095599 INFO: [APUAPC] D9_APC_2: 0x3fffff
10028 12:42:07.098671 INFO: [APUAPC] D9_APC_3: 0x0
10029 12:42:07.101272 INFO: [APUAPC] D10_APC_0: 0xffffffff
10030 12:42:07.104820 INFO: [APUAPC] D10_APC_1: 0xffffffff
10031 12:42:07.108011 INFO: [APUAPC] D10_APC_2: 0x3fffff
10032 12:42:07.111593 INFO: [APUAPC] D10_APC_3: 0x0
10033 12:42:07.114952 INFO: [APUAPC] D11_APC_0: 0xffffffff
10034 12:42:07.118295 INFO: [APUAPC] D11_APC_1: 0xffffffff
10035 12:42:07.121750 INFO: [APUAPC] D11_APC_2: 0x3fffff
10036 12:42:07.125076 INFO: [APUAPC] D11_APC_3: 0x0
10037 12:42:07.128265 INFO: [APUAPC] D12_APC_0: 0xffffffff
10038 12:42:07.131294 INFO: [APUAPC] D12_APC_1: 0xffffffff
10039 12:42:07.135043 INFO: [APUAPC] D12_APC_2: 0x3fffff
10040 12:42:07.138465 INFO: [APUAPC] D12_APC_3: 0x0
10041 12:42:07.141621 INFO: [APUAPC] D13_APC_0: 0xffffffff
10042 12:42:07.145263 INFO: [APUAPC] D13_APC_1: 0xffffffff
10043 12:42:07.148098 INFO: [APUAPC] D13_APC_2: 0x3fffff
10044 12:42:07.151772 INFO: [APUAPC] D13_APC_3: 0x0
10045 12:42:07.154486 INFO: [APUAPC] D14_APC_0: 0xffffffff
10046 12:42:07.158166 INFO: [APUAPC] D14_APC_1: 0xffffffff
10047 12:42:07.161537 INFO: [APUAPC] D14_APC_2: 0x3fffff
10048 12:42:07.164454 INFO: [APUAPC] D14_APC_3: 0x0
10049 12:42:07.167869 INFO: [APUAPC] D15_APC_0: 0xffffffff
10050 12:42:07.171233 INFO: [APUAPC] D15_APC_1: 0xffffffff
10051 12:42:07.174893 INFO: [APUAPC] D15_APC_2: 0x3fffff
10052 12:42:07.177930 INFO: [APUAPC] D15_APC_3: 0x0
10053 12:42:07.181269 INFO: [APUAPC] APC_CON: 0x4
10054 12:42:07.184472 INFO: [NOCDAPC] D0_APC_0: 0x0
10055 12:42:07.188059 INFO: [NOCDAPC] D0_APC_1: 0x0
10056 12:42:07.191531 INFO: [NOCDAPC] D1_APC_0: 0x0
10057 12:42:07.195299 INFO: [NOCDAPC] D1_APC_1: 0xfff
10058 12:42:07.197711 INFO: [NOCDAPC] D2_APC_0: 0x0
10059 12:42:07.200860 INFO: [NOCDAPC] D2_APC_1: 0xfff
10060 12:42:07.200946 INFO: [NOCDAPC] D3_APC_0: 0x0
10061 12:42:07.204854 INFO: [NOCDAPC] D3_APC_1: 0xfff
10062 12:42:07.207756 INFO: [NOCDAPC] D4_APC_0: 0x0
10063 12:42:07.211103 INFO: [NOCDAPC] D4_APC_1: 0xfff
10064 12:42:07.214621 INFO: [NOCDAPC] D5_APC_0: 0x0
10065 12:42:07.218260 INFO: [NOCDAPC] D5_APC_1: 0xfff
10066 12:42:07.221070 INFO: [NOCDAPC] D6_APC_0: 0x0
10067 12:42:07.224482 INFO: [NOCDAPC] D6_APC_1: 0xfff
10068 12:42:07.228298 INFO: [NOCDAPC] D7_APC_0: 0x0
10069 12:42:07.231591 INFO: [NOCDAPC] D7_APC_1: 0xfff
10070 12:42:07.234756 INFO: [NOCDAPC] D8_APC_0: 0x0
10071 12:42:07.234842 INFO: [NOCDAPC] D8_APC_1: 0xfff
10072 12:42:07.237708 INFO: [NOCDAPC] D9_APC_0: 0x0
10073 12:42:07.240898 INFO: [NOCDAPC] D9_APC_1: 0xfff
10074 12:42:07.244471 INFO: [NOCDAPC] D10_APC_0: 0x0
10075 12:42:07.247854 INFO: [NOCDAPC] D10_APC_1: 0xfff
10076 12:42:07.251272 INFO: [NOCDAPC] D11_APC_0: 0x0
10077 12:42:07.254427 INFO: [NOCDAPC] D11_APC_1: 0xfff
10078 12:42:07.258011 INFO: [NOCDAPC] D12_APC_0: 0x0
10079 12:42:07.260861 INFO: [NOCDAPC] D12_APC_1: 0xfff
10080 12:42:07.264141 INFO: [NOCDAPC] D13_APC_0: 0x0
10081 12:42:07.267778 INFO: [NOCDAPC] D13_APC_1: 0xfff
10082 12:42:07.270896 INFO: [NOCDAPC] D14_APC_0: 0x0
10083 12:42:07.274365 INFO: [NOCDAPC] D14_APC_1: 0xfff
10084 12:42:07.277794 INFO: [NOCDAPC] D15_APC_0: 0x0
10085 12:42:07.281431 INFO: [NOCDAPC] D15_APC_1: 0xfff
10086 12:42:07.281566 INFO: [NOCDAPC] APC_CON: 0x4
10087 12:42:07.284301 INFO: [APUAPC] set_apusys_apc done
10088 12:42:07.287394 INFO: [DEVAPC] devapc_init done
10089 12:42:07.294620 INFO: GICv3 without legacy support detected.
10090 12:42:07.297565 INFO: ARM GICv3 driver initialized in EL3
10091 12:42:07.300874 INFO: Maximum SPI INTID supported: 639
10092 12:42:07.304302 INFO: BL31: Initializing runtime services
10093 12:42:07.310634 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10094 12:42:07.313813 INFO: SPM: enable CPC mode
10095 12:42:07.317676 INFO: mcdi ready for mcusys-off-idle and system suspend
10096 12:42:07.324279 INFO: BL31: Preparing for EL3 exit to normal world
10097 12:42:07.327834 INFO: Entry point address = 0x80000000
10098 12:42:07.328129 INFO: SPSR = 0x8
10099 12:42:07.334365
10100 12:42:07.334632
10101 12:42:07.334829
10102 12:42:07.337677 Starting depthcharge on Spherion...
10103 12:42:07.337988
10104 12:42:07.338232 Wipe memory regions:
10105 12:42:07.338460
10106 12:42:07.340257 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10107 12:42:07.340633 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10108 12:42:07.340977 Setting prompt string to ['asurada:']
10109 12:42:07.341339 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10110 12:42:07.342050 [0x00000040000000, 0x00000054600000)
10111 12:42:07.463647
10112 12:42:07.464169 [0x00000054660000, 0x00000080000000)
10113 12:42:07.724106
10114 12:42:07.724706 [0x000000821a7280, 0x000000ffe64000)
10115 12:42:08.468847
10116 12:42:08.468990 [0x00000100000000, 0x00000240000000)
10117 12:42:10.358666
10118 12:42:10.362073 Initializing XHCI USB controller at 0x11200000.
10119 12:42:11.400959
10120 12:42:11.404497 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10121 12:42:11.405134
10122 12:42:11.405498
10123 12:42:11.405907
10124 12:42:11.406671 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10126 12:42:11.507842 asurada: tftpboot 192.168.201.1 10724845/tftp-deploy-toqeg7bi/kernel/image.itb 10724845/tftp-deploy-toqeg7bi/kernel/cmdline
10127 12:42:11.508036 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10128 12:42:11.508140 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10129 12:42:11.512781 tftpboot 192.168.201.1 10724845/tftp-deploy-toqeg7bi/kernel/image.ittp-deploy-toqeg7bi/kernel/cmdline
10130 12:42:11.512908
10131 12:42:11.512979 Waiting for link
10132 12:42:11.673537
10133 12:42:11.674006 R8152: Initializing
10134 12:42:11.674308
10135 12:42:11.676523 Version 6 (ocp_data = 5c30)
10136 12:42:11.676891
10137 12:42:11.679870 R8152: Done initializing
10138 12:42:11.680235
10139 12:42:11.680524 Adding net device
10140 12:42:13.547773
10141 12:42:13.548072 done.
10142 12:42:13.548266
10143 12:42:13.548438 MAC: 00:24:32:30:78:52
10144 12:42:13.548603
10145 12:42:13.550915 Sending DHCP discover... done.
10146 12:42:13.551100
10147 12:42:16.560453 Waiting for reply... done.
10148 12:42:16.560622
10149 12:42:16.560697 Sending DHCP request... done.
10150 12:42:16.563609
10151 12:42:16.570098 Waiting for reply... done.
10152 12:42:16.570196
10153 12:42:16.570263 My ip is 192.168.201.14
10154 12:42:16.570324
10155 12:42:16.573637 The DHCP server ip is 192.168.201.1
10156 12:42:16.573722
10157 12:42:16.579850 TFTP server IP predefined by user: 192.168.201.1
10158 12:42:16.579974
10159 12:42:16.586617 Bootfile predefined by user: 10724845/tftp-deploy-toqeg7bi/kernel/image.itb
10160 12:42:16.586708
10161 12:42:16.586774 Sending tftp read request... done.
10162 12:42:16.589838
10163 12:42:16.593891 Waiting for the transfer...
10164 12:42:16.593981
10165 12:42:17.135753 00000000 ################################################################
10166 12:42:17.135924
10167 12:42:17.673796 00080000 ################################################################
10168 12:42:17.673980
10169 12:42:18.213116 00100000 ################################################################
10170 12:42:18.213263
10171 12:42:18.763933 00180000 ################################################################
10172 12:42:18.764106
10173 12:42:19.334094 00200000 ################################################################
10174 12:42:19.334255
10175 12:42:19.881252 00280000 ################################################################
10176 12:42:19.881412
10177 12:42:20.421648 00300000 ################################################################
10178 12:42:20.421808
10179 12:42:20.944361 00380000 ################################################################
10180 12:42:20.944548
10181 12:42:21.466713 00400000 ################################################################
10182 12:42:21.466902
10183 12:42:22.003533 00480000 ################################################################
10184 12:42:22.003696
10185 12:42:22.550807 00500000 ################################################################
10186 12:42:22.550949
10187 12:42:23.094933 00580000 ################################################################
10188 12:42:23.095087
10189 12:42:23.627502 00600000 ################################################################
10190 12:42:23.627657
10191 12:42:24.167084 00680000 ################################################################
10192 12:42:24.167261
10193 12:42:24.712337 00700000 ################################################################
10194 12:42:24.712473
10195 12:42:25.251608 00780000 ################################################################
10196 12:42:25.251748
10197 12:42:25.789348 00800000 ################################################################
10198 12:42:25.789502
10199 12:42:26.342302 00880000 ################################################################
10200 12:42:26.342457
10201 12:42:26.890291 00900000 ################################################################
10202 12:42:26.890442
10203 12:42:27.466420 00980000 ################################################################
10204 12:42:27.466576
10205 12:42:28.127707 00a00000 ################################################################
10206 12:42:28.128218
10207 12:42:28.816835 00a80000 ################################################################
10208 12:42:28.817342
10209 12:42:29.510754 00b00000 ################################################################
10210 12:42:29.511279
10211 12:42:30.206914 00b80000 ################################################################
10212 12:42:30.207495
10213 12:42:30.904789 00c00000 ################################################################
10214 12:42:30.905315
10215 12:42:31.601349 00c80000 ################################################################
10216 12:42:31.601870
10217 12:42:32.299220 00d00000 ################################################################
10218 12:42:32.299816
10219 12:42:32.996402 00d80000 ################################################################
10220 12:42:32.996922
10221 12:42:33.696090 00e00000 ################################################################
10222 12:42:33.696591
10223 12:42:34.383148 00e80000 ################################################################
10224 12:42:34.383733
10225 12:42:35.072039 00f00000 ################################################################
10226 12:42:35.072415
10227 12:42:35.754052 00f80000 ################################################################
10228 12:42:35.754635
10229 12:42:36.444103 01000000 ################################################################
10230 12:42:36.444254
10231 12:42:37.100399 01080000 ################################################################
10232 12:42:37.100945
10233 12:42:37.658868 01100000 ################################################################
10234 12:42:37.659021
10235 12:42:38.183322 01180000 ################################################################
10236 12:42:38.183513
10237 12:42:38.694175 01200000 ################################################################
10238 12:42:38.694326
10239 12:42:39.199401 01280000 ################################################################
10240 12:42:39.199545
10241 12:42:39.704831 01300000 ################################################################
10242 12:42:39.704983
10243 12:42:40.212825 01380000 ################################################################
10244 12:42:40.212984
10245 12:42:40.719358 01400000 ################################################################
10246 12:42:40.719502
10247 12:42:41.224096 01480000 ################################################################
10248 12:42:41.224230
10249 12:42:41.728769 01500000 ################################################################
10250 12:42:41.728903
10251 12:42:42.238944 01580000 ################################################################
10252 12:42:42.239073
10253 12:42:42.743260 01600000 ################################################################
10254 12:42:42.743436
10255 12:42:43.246479 01680000 ################################################################
10256 12:42:43.246613
10257 12:42:43.751820 01700000 ################################################################
10258 12:42:43.751966
10259 12:42:44.258568 01780000 ################################################################
10260 12:42:44.258733
10261 12:42:44.769069 01800000 ################################################################
10262 12:42:44.769233
10263 12:42:45.276132 01880000 ################################################################
10264 12:42:45.276294
10265 12:42:45.783038 01900000 ################################################################
10266 12:42:45.783176
10267 12:42:46.287482 01980000 ################################################################
10268 12:42:46.287618
10269 12:42:46.792255 01a00000 ################################################################
10270 12:42:46.792398
10271 12:42:47.297508 01a80000 ################################################################
10272 12:42:47.297645
10273 12:42:47.800888 01b00000 ################################################################
10274 12:42:47.801026
10275 12:42:48.048450 01b80000 ################################ done.
10276 12:42:48.048584
10277 12:42:48.051882 The bootfile was 29092966 bytes long.
10278 12:42:48.051967
10279 12:42:48.055149 Sending tftp read request... done.
10280 12:42:48.055246
10281 12:42:48.055313 Waiting for the transfer...
10282 12:42:48.055398
10283 12:42:48.058426 00000000 # done.
10284 12:42:48.058510
10285 12:42:48.064882 Command line loaded dynamically from TFTP file: 10724845/tftp-deploy-toqeg7bi/kernel/cmdline
10286 12:42:48.064981
10287 12:42:48.084780 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10724845/extract-nfsrootfs-wc08wldn,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10288 12:42:48.084871
10289 12:42:48.088272 Loading FIT.
10290 12:42:48.088353
10291 12:42:48.088418 Image ramdisk-1 has 18601629 bytes.
10292 12:42:48.091196
10293 12:42:48.091311 Image fdt-1 has 46924 bytes.
10294 12:42:48.091427
10295 12:42:48.094702 Image kernel-1 has 10442380 bytes.
10296 12:42:48.094784
10297 12:42:48.104392 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10298 12:42:48.104503
10299 12:42:48.121163 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10300 12:42:48.121251
10301 12:42:48.127826 Choosing best match conf-1 for compat google,spherion-rev2.
10302 12:42:48.131191
10303 12:42:48.135702 Connected to device vid:did:rid of 1ae0:0028:00
10304 12:42:48.142830
10305 12:42:48.145987 tpm_get_response: command 0x17b, return code 0x0
10306 12:42:48.146071
10307 12:42:48.149549 ec_init: CrosEC protocol v3 supported (256, 248)
10308 12:42:48.153494
10309 12:42:48.156962 tpm_cleanup: add release locality here.
10310 12:42:48.157045
10311 12:42:48.157114 Shutting down all USB controllers.
10312 12:42:48.159991
10313 12:42:48.160073 Removing current net device
10314 12:42:48.160138
10315 12:42:48.167041 Exiting depthcharge with code 4 at timestamp: 70201512
10316 12:42:48.167124
10317 12:42:48.170068 LZMA decompressing kernel-1 to 0x821a6718
10318 12:42:48.170151
10319 12:42:48.173254 LZMA decompressing kernel-1 to 0x40000000
10320 12:42:49.483324
10321 12:42:49.483506 jumping to kernel
10322 12:42:49.483917 end: 2.2.4 bootloader-commands (duration 00:00:42) [common]
10323 12:42:49.484019 start: 2.2.5 auto-login-action (timeout 00:03:43) [common]
10324 12:42:49.484094 Setting prompt string to ['Linux version [0-9]']
10325 12:42:49.484162 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10326 12:42:49.484230 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10327 12:42:49.565211
10328 12:42:49.568951 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10329 12:42:49.572529 start: 2.2.5.1 login-action (timeout 00:03:43) [common]
10330 12:42:49.572621 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10331 12:42:49.572711 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10332 12:42:49.572790 Using line separator: #'\n'#
10333 12:42:49.572852 No login prompt set.
10334 12:42:49.572916 Parsing kernel messages
10335 12:42:49.572973 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10336 12:42:49.573079 [login-action] Waiting for messages, (timeout 00:03:43)
10337 12:42:49.591829 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j35827-arm64-gcc-10-defconfig-arm64-chromebook-fwl9s) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jun 14 12:30:40 UTC 2023
10338 12:42:49.595149 [ 0.000000] random: crng init done
10339 12:42:49.599114 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10340 12:42:49.601952 [ 0.000000] efi: UEFI not found.
10341 12:42:49.611802 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10342 12:42:49.618001 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10343 12:42:49.628437 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10344 12:42:49.638355 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10345 12:42:49.645377 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10346 12:42:49.648031 [ 0.000000] printk: bootconsole [mtk8250] enabled
10347 12:42:49.656891 [ 0.000000] NUMA: No NUMA configuration found
10348 12:42:49.663144 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10349 12:42:49.669829 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10350 12:42:49.669912 [ 0.000000] Zone ranges:
10351 12:42:49.676461 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10352 12:42:49.679708 [ 0.000000] DMA32 empty
10353 12:42:49.686251 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10354 12:42:49.690361 [ 0.000000] Movable zone start for each node
10355 12:42:49.693209 [ 0.000000] Early memory node ranges
10356 12:42:49.699602 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10357 12:42:49.706785 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10358 12:42:49.712780 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10359 12:42:49.720197 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10360 12:42:49.726127 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10361 12:42:49.732997 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10362 12:42:49.789585 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10363 12:42:49.796120 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10364 12:42:49.803021 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10365 12:42:49.806326 [ 0.000000] psci: probing for conduit method from DT.
10366 12:42:49.812607 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10367 12:42:49.816282 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10368 12:42:49.822322 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10369 12:42:49.825922 [ 0.000000] psci: SMC Calling Convention v1.2
10370 12:42:49.832490 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10371 12:42:49.836046 [ 0.000000] Detected VIPT I-cache on CPU0
10372 12:42:49.842342 [ 0.000000] CPU features: detected: GIC system register CPU interface
10373 12:42:49.849126 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10374 12:42:49.856233 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10375 12:42:49.862655 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10376 12:42:49.868982 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10377 12:42:49.875719 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10378 12:42:49.881964 [ 0.000000] alternatives: applying boot alternatives
10379 12:42:49.888785 [ 0.000000] Fallback order for Node 0: 0
10380 12:42:49.895275 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10381 12:42:49.898783 [ 0.000000] Policy zone: Normal
10382 12:42:49.919191 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10724845/extract-nfsrootfs-wc08wldn,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10383 12:42:49.928466 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10384 12:42:49.939903 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10385 12:42:49.950047 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10386 12:42:49.956548 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10387 12:42:49.959756 <6>[ 0.000000] software IO TLB: area num 8.
10388 12:42:50.016955 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10389 12:42:50.166125 <6>[ 0.000000] Memory: 7952996K/8385536K available (17984K kernel code, 4098K rwdata, 15868K rodata, 8384K init, 615K bss, 399772K reserved, 32768K cma-reserved)
10390 12:42:50.173294 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10391 12:42:50.179361 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10392 12:42:50.183062 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10393 12:42:50.189884 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10394 12:42:50.196105 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10395 12:42:50.199543 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10396 12:42:50.209156 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10397 12:42:50.215751 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10398 12:42:50.222702 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10399 12:42:50.229052 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10400 12:42:50.232102 <6>[ 0.000000] GICv3: 608 SPIs implemented
10401 12:42:50.235707 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10402 12:42:50.242179 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10403 12:42:50.245328 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10404 12:42:50.252142 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10405 12:42:50.265219 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10406 12:42:50.278587 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10407 12:42:50.285219 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10408 12:42:50.292858 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10409 12:42:50.305925 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10410 12:42:50.312520 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10411 12:42:50.319290 <6>[ 0.009228] Console: colour dummy device 80x25
10412 12:42:50.329541 <6>[ 0.013954] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10413 12:42:50.336049 <6>[ 0.024396] pid_max: default: 32768 minimum: 301
10414 12:42:50.339693 <6>[ 0.029270] LSM: Security Framework initializing
10415 12:42:50.345900 <6>[ 0.034239] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10416 12:42:50.356119 <6>[ 0.042053] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10417 12:42:50.362961 <6>[ 0.051485] cblist_init_generic: Setting adjustable number of callback queues.
10418 12:42:50.369113 <6>[ 0.058939] cblist_init_generic: Setting shift to 3 and lim to 1.
10419 12:42:50.376141 <6>[ 0.065279] cblist_init_generic: Setting shift to 3 and lim to 1.
10420 12:42:50.382613 <6>[ 0.071724] rcu: Hierarchical SRCU implementation.
10421 12:42:50.386726 <6>[ 0.076769] rcu: Max phase no-delay instances is 1000.
10422 12:42:50.394357 <6>[ 0.083781] EFI services will not be available.
10423 12:42:50.397073 <6>[ 0.088753] smp: Bringing up secondary CPUs ...
10424 12:42:50.406752 <6>[ 0.093837] Detected VIPT I-cache on CPU1
10425 12:42:50.413136 <6>[ 0.093907] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10426 12:42:50.419789 <6>[ 0.093939] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10427 12:42:50.422933 <6>[ 0.094278] Detected VIPT I-cache on CPU2
10428 12:42:50.429670 <6>[ 0.094330] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10429 12:42:50.439936 <6>[ 0.094346] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10430 12:42:50.442768 <6>[ 0.094608] Detected VIPT I-cache on CPU3
10431 12:42:50.449609 <6>[ 0.094654] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10432 12:42:50.456184 <6>[ 0.094669] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10433 12:42:50.459658 <6>[ 0.094974] CPU features: detected: Spectre-v4
10434 12:42:50.466291 <6>[ 0.094981] CPU features: detected: Spectre-BHB
10435 12:42:50.469626 <6>[ 0.094987] Detected PIPT I-cache on CPU4
10436 12:42:50.476070 <6>[ 0.095044] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10437 12:42:50.482792 <6>[ 0.095060] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10438 12:42:50.489298 <6>[ 0.095354] Detected PIPT I-cache on CPU5
10439 12:42:50.495651 <6>[ 0.095416] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10440 12:42:50.502263 <6>[ 0.095433] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10441 12:42:50.506106 <6>[ 0.095716] Detected PIPT I-cache on CPU6
10442 12:42:50.512701 <6>[ 0.095781] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10443 12:42:50.519298 <6>[ 0.095797] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10444 12:42:50.525922 <6>[ 0.096096] Detected PIPT I-cache on CPU7
10445 12:42:50.532385 <6>[ 0.096160] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10446 12:42:50.538878 <6>[ 0.096176] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10447 12:42:50.542723 <6>[ 0.096223] smp: Brought up 1 node, 8 CPUs
10448 12:42:50.549421 <6>[ 0.237711] SMP: Total of 8 processors activated.
10449 12:42:50.553070 <6>[ 0.242632] CPU features: detected: 32-bit EL0 Support
10450 12:42:50.562620 <6>[ 0.247996] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10451 12:42:50.569081 <6>[ 0.256851] CPU features: detected: Common not Private translations
10452 12:42:50.572644 <6>[ 0.263327] CPU features: detected: CRC32 instructions
10453 12:42:50.578744 <6>[ 0.268678] CPU features: detected: RCpc load-acquire (LDAPR)
10454 12:42:50.585345 <6>[ 0.274675] CPU features: detected: LSE atomic instructions
10455 12:42:50.592270 <6>[ 0.280456] CPU features: detected: Privileged Access Never
10456 12:42:50.598920 <6>[ 0.286236] CPU features: detected: RAS Extension Support
10457 12:42:50.605455 <6>[ 0.291879] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10458 12:42:50.608439 <6>[ 0.299101] CPU: All CPU(s) started at EL2
10459 12:42:50.615118 <6>[ 0.303417] alternatives: applying system-wide alternatives
10460 12:42:50.624057 <6>[ 0.314130] devtmpfs: initialized
10461 12:42:50.637020 <6>[ 0.322960] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10462 12:42:50.646666 <6>[ 0.332924] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10463 12:42:50.649711 <6>[ 0.340531] pinctrl core: initialized pinctrl subsystem
10464 12:42:50.658019 <6>[ 0.347200] DMI not present or invalid.
10465 12:42:50.664498 <6>[ 0.351605] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10466 12:42:50.671213 <6>[ 0.358483] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10467 12:42:50.681482 <6>[ 0.366063] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10468 12:42:50.687582 <6>[ 0.374275] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10469 12:42:50.694358 <6>[ 0.382513] audit: initializing netlink subsys (disabled)
10470 12:42:50.701100 <5>[ 0.388209] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10471 12:42:50.707588 <6>[ 0.388925] thermal_sys: Registered thermal governor 'step_wise'
10472 12:42:50.714645 <6>[ 0.396175] thermal_sys: Registered thermal governor 'power_allocator'
10473 12:42:50.717750 <6>[ 0.402428] cpuidle: using governor menu
10474 12:42:50.724732 <6>[ 0.413388] NET: Registered PF_QIPCRTR protocol family
10475 12:42:50.730578 <6>[ 0.418876] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10476 12:42:50.737243 <6>[ 0.425978] ASID allocator initialised with 32768 entries
10477 12:42:50.743758 <6>[ 0.432545] Serial: AMBA PL011 UART driver
10478 12:42:50.751762 <4>[ 0.441211] Trying to register duplicate clock ID: 134
10479 12:42:50.806210 <6>[ 0.498642] KASLR enabled
10480 12:42:50.820075 <6>[ 0.506363] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10481 12:42:50.827045 <6>[ 0.513374] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10482 12:42:50.833291 <6>[ 0.519861] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10483 12:42:50.840860 <6>[ 0.526864] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10484 12:42:50.846965 <6>[ 0.533349] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10485 12:42:50.853869 <6>[ 0.540352] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10486 12:42:50.860254 <6>[ 0.546840] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10487 12:42:50.866591 <6>[ 0.553844] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10488 12:42:50.870537 <6>[ 0.561353] ACPI: Interpreter disabled.
10489 12:42:50.878555 <6>[ 0.567734] iommu: Default domain type: Translated
10490 12:42:50.884927 <6>[ 0.572846] iommu: DMA domain TLB invalidation policy: strict mode
10491 12:42:50.888849 <5>[ 0.579499] SCSI subsystem initialized
10492 12:42:50.894773 <6>[ 0.583664] usbcore: registered new interface driver usbfs
10493 12:42:50.901508 <6>[ 0.589398] usbcore: registered new interface driver hub
10494 12:42:50.904698 <6>[ 0.594951] usbcore: registered new device driver usb
10495 12:42:50.912003 <6>[ 0.601025] pps_core: LinuxPPS API ver. 1 registered
10496 12:42:50.921624 <6>[ 0.606218] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10497 12:42:50.924748 <6>[ 0.615561] PTP clock support registered
10498 12:42:50.928188 <6>[ 0.619801] EDAC MC: Ver: 3.0.0
10499 12:42:50.935689 <6>[ 0.624940] FPGA manager framework
10500 12:42:50.942810 <6>[ 0.628619] Advanced Linux Sound Architecture Driver Initialized.
10501 12:42:50.945306 <6>[ 0.635384] vgaarb: loaded
10502 12:42:50.952272 <6>[ 0.638557] clocksource: Switched to clocksource arch_sys_counter
10503 12:42:50.955465 <5>[ 0.644995] VFS: Disk quotas dquot_6.6.0
10504 12:42:50.962492 <6>[ 0.649181] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10505 12:42:50.965063 <6>[ 0.656365] pnp: PnP ACPI: disabled
10506 12:42:50.974274 <6>[ 0.663068] NET: Registered PF_INET protocol family
10507 12:42:50.983542 <6>[ 0.668650] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10508 12:42:50.994895 <6>[ 0.680945] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10509 12:42:51.005033 <6>[ 0.689758] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10510 12:42:51.011993 <6>[ 0.697730] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10511 12:42:51.018239 <6>[ 0.706428] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10512 12:42:51.030099 <6>[ 0.716173] TCP: Hash tables configured (established 65536 bind 65536)
10513 12:42:51.037077 <6>[ 0.723026] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10514 12:42:51.043305 <6>[ 0.730223] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10515 12:42:51.050246 <6>[ 0.737919] NET: Registered PF_UNIX/PF_LOCAL protocol family
10516 12:42:51.056967 <6>[ 0.744091] RPC: Registered named UNIX socket transport module.
10517 12:42:51.059658 <6>[ 0.750246] RPC: Registered udp transport module.
10518 12:42:51.066905 <6>[ 0.755180] RPC: Registered tcp transport module.
10519 12:42:51.073015 <6>[ 0.760112] RPC: Registered tcp NFSv4.1 backchannel transport module.
10520 12:42:51.076257 <6>[ 0.766775] PCI: CLS 0 bytes, default 64
10521 12:42:51.079837 <6>[ 0.771129] Unpacking initramfs...
10522 12:42:51.090187 <6>[ 0.775385] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10523 12:42:51.099329 <6>[ 0.784043] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10524 12:42:51.102655 <6>[ 0.792812] kvm [1]: IPA Size Limit: 40 bits
10525 12:42:51.109588 <6>[ 0.797336] kvm [1]: GICv3: no GICV resource entry
10526 12:42:51.112422 <6>[ 0.802355] kvm [1]: disabling GICv2 emulation
10527 12:42:51.119107 <6>[ 0.807058] kvm [1]: GIC system register CPU interface enabled
10528 12:42:51.122433 <6>[ 0.813218] kvm [1]: vgic interrupt IRQ18
10529 12:42:51.129196 <6>[ 0.817569] kvm [1]: VHE mode initialized successfully
10530 12:42:51.135676 <5>[ 0.824044] Initialise system trusted keyrings
10531 12:42:51.142477 <6>[ 0.828866] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10532 12:42:51.149787 <6>[ 0.838901] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10533 12:42:51.156812 <5>[ 0.845321] NFS: Registering the id_resolver key type
10534 12:42:51.159992 <5>[ 0.850636] Key type id_resolver registered
10535 12:42:51.166300 <5>[ 0.855054] Key type id_legacy registered
10536 12:42:51.173239 <6>[ 0.859338] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10537 12:42:51.179988 <6>[ 0.866262] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10538 12:42:51.186012 <6>[ 0.874005] 9p: Installing v9fs 9p2000 file system support
10539 12:42:51.222911 <5>[ 0.912102] Key type asymmetric registered
10540 12:42:51.226270 <5>[ 0.916435] Asymmetric key parser 'x509' registered
10541 12:42:51.235920 <6>[ 0.921580] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10542 12:42:51.239114 <6>[ 0.929200] io scheduler mq-deadline registered
10543 12:42:51.243127 <6>[ 0.933957] io scheduler kyber registered
10544 12:42:51.261339 <6>[ 0.950867] EINJ: ACPI disabled.
10545 12:42:51.293606 <4>[ 0.975981] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10546 12:42:51.303424 <4>[ 0.986641] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10547 12:42:51.318446 <6>[ 1.007500] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10548 12:42:51.326654 <6>[ 1.015596] printk: console [ttyS0] disabled
10549 12:42:51.354325 <6>[ 1.040243] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10550 12:42:51.361238 <6>[ 1.049713] printk: console [ttyS0] enabled
10551 12:42:51.364594 <6>[ 1.049713] printk: console [ttyS0] enabled
10552 12:42:51.371191 <6>[ 1.058606] printk: bootconsole [mtk8250] disabled
10553 12:42:51.374595 <6>[ 1.058606] printk: bootconsole [mtk8250] disabled
10554 12:42:51.380552 <6>[ 1.069980] SuperH (H)SCI(F) driver initialized
10555 12:42:51.384310 <6>[ 1.075257] msm_serial: driver initialized
10556 12:42:51.398542 <6>[ 1.084196] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10557 12:42:51.408469 <6>[ 1.092746] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10558 12:42:51.415436 <6>[ 1.101287] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10559 12:42:51.424925 <6>[ 1.109915] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10560 12:42:51.434388 <6>[ 1.118621] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10561 12:42:51.441548 <6>[ 1.127342] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10562 12:42:51.451521 <6>[ 1.135885] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10563 12:42:51.457809 <6>[ 1.144682] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10564 12:42:51.468023 <6>[ 1.153225] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10565 12:42:51.479888 <6>[ 1.168898] loop: module loaded
10566 12:42:51.486453 <6>[ 1.174813] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10567 12:42:51.508839 <4>[ 1.198192] mtk-pmic-keys: Failed to locate of_node [id: -1]
10568 12:42:51.515642 <6>[ 1.205004] megasas: 07.719.03.00-rc1
10569 12:42:51.524761 <6>[ 1.214349] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10570 12:42:51.532604 <6>[ 1.221939] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10571 12:42:51.549693 <6>[ 1.238515] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10572 12:42:51.609781 <6>[ 1.292274] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10573 12:42:51.904259 <6>[ 1.593500] Freeing initrd memory: 18160K
10574 12:42:51.915589 <6>[ 1.605080] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10575 12:42:51.926983 <6>[ 1.615910] tun: Universal TUN/TAP device driver, 1.6
10576 12:42:51.929715 <6>[ 1.621957] thunder_xcv, ver 1.0
10577 12:42:51.933831 <6>[ 1.625465] thunder_bgx, ver 1.0
10578 12:42:51.936189 <6>[ 1.628959] nicpf, ver 1.0
10579 12:42:51.947145 <6>[ 1.632951] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10580 12:42:51.950579 <6>[ 1.640427] hns3: Copyright (c) 2017 Huawei Corporation.
10581 12:42:51.954188 <6>[ 1.646022] hclge is initializing
10582 12:42:51.960182 <6>[ 1.649602] e1000: Intel(R) PRO/1000 Network Driver
10583 12:42:51.967309 <6>[ 1.654731] e1000: Copyright (c) 1999-2006 Intel Corporation.
10584 12:42:51.970905 <6>[ 1.660745] e1000e: Intel(R) PRO/1000 Network Driver
10585 12:42:51.976624 <6>[ 1.665961] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10586 12:42:51.983464 <6>[ 1.672144] igb: Intel(R) Gigabit Ethernet Network Driver
10587 12:42:51.990042 <6>[ 1.677795] igb: Copyright (c) 2007-2014 Intel Corporation.
10588 12:42:51.996814 <6>[ 1.683634] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10589 12:42:52.003846 <6>[ 1.690156] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10590 12:42:52.006876 <6>[ 1.696612] sky2: driver version 1.30
10591 12:42:52.013449 <6>[ 1.701578] VFIO - User Level meta-driver version: 0.3
10592 12:42:52.020361 <6>[ 1.709724] usbcore: registered new interface driver usb-storage
10593 12:42:52.027024 <6>[ 1.716172] usbcore: registered new device driver onboard-usb-hub
10594 12:42:52.035750 <6>[ 1.725268] mt6397-rtc mt6359-rtc: registered as rtc0
10595 12:42:52.046194 <6>[ 1.730734] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-14T12:42:52 UTC (1686746572)
10596 12:42:52.049593 <6>[ 1.740284] i2c_dev: i2c /dev entries driver
10597 12:42:52.065931 <6>[ 1.751863] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10598 12:42:52.073571 <6>[ 1.762010] sdhci: Secure Digital Host Controller Interface driver
10599 12:42:52.079404 <6>[ 1.768450] sdhci: Copyright(c) Pierre Ossman
10600 12:42:52.085945 <6>[ 1.773832] Synopsys Designware Multimedia Card Interface Driver
10601 12:42:52.089397 <6>[ 1.780481] mmc0: CQHCI version 5.10
10602 12:42:52.096267 <6>[ 1.780969] sdhci-pltfm: SDHCI platform and OF driver helper
10603 12:42:52.102971 <6>[ 1.792344] ledtrig-cpu: registered to indicate activity on CPUs
10604 12:42:52.113531 <6>[ 1.799682] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10605 12:42:52.116535 <6>[ 1.807080] usbcore: registered new interface driver usbhid
10606 12:42:52.123574 <6>[ 1.812912] usbhid: USB HID core driver
10607 12:42:52.130194 <6>[ 1.817151] spi_master spi0: will run message pump with realtime priority
10608 12:42:52.171321 <6>[ 1.853817] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10609 12:42:52.189640 <6>[ 1.868801] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10610 12:42:52.192751 <6>[ 1.882319] mmc0: Command Queue Engine enabled
10611 12:42:52.199668 <6>[ 1.887054] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10612 12:42:52.206598 <6>[ 1.893942] cros-ec-spi spi0.0: Chrome EC device registered
10613 12:42:52.209785 <6>[ 1.894341] mmcblk0: mmc0:0001 DA4128 116 GiB
10614 12:42:52.220310 <6>[ 1.909697] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10615 12:42:52.227438 <6>[ 1.916969] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10616 12:42:52.233961 <6>[ 1.922943] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10617 12:42:52.240897 <6>[ 1.928866] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10618 12:42:52.251345 <6>[ 1.930473] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10619 12:42:52.257524 <6>[ 1.946853] NET: Registered PF_PACKET protocol family
10620 12:42:52.261617 <6>[ 1.952307] 9pnet: Installing 9P2000 support
10621 12:42:52.268314 <5>[ 1.956884] Key type dns_resolver registered
10622 12:42:52.270948 <6>[ 1.961942] registered taskstats version 1
10623 12:42:52.277514 <5>[ 1.966342] Loading compiled-in X.509 certificates
10624 12:42:52.310055 <4>[ 1.992993] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10625 12:42:52.320168 <4>[ 2.003740] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10626 12:42:52.330437 <3>[ 2.016373] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10627 12:42:52.342749 <6>[ 2.031780] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10628 12:42:52.349729 <6>[ 2.038621] xhci-mtk 11200000.usb: xHCI Host Controller
10629 12:42:52.355862 <6>[ 2.044122] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10630 12:42:52.366172 <6>[ 2.051987] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10631 12:42:52.372811 <6>[ 2.061424] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10632 12:42:52.379319 <6>[ 2.067656] xhci-mtk 11200000.usb: xHCI Host Controller
10633 12:42:52.385844 <6>[ 2.073151] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10634 12:42:52.392163 <6>[ 2.080812] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10635 12:42:52.399172 <6>[ 2.088708] hub 1-0:1.0: USB hub found
10636 12:42:52.402521 <6>[ 2.092757] hub 1-0:1.0: 1 port detected
10637 12:42:52.412712 <6>[ 2.097111] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10638 12:42:52.416087 <6>[ 2.105933] hub 2-0:1.0: USB hub found
10639 12:42:52.418831 <6>[ 2.109970] hub 2-0:1.0: 1 port detected
10640 12:42:52.427379 <6>[ 2.116868] mtk-msdc 11f70000.mmc: Got CD GPIO
10641 12:42:52.445796 <6>[ 2.131748] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10642 12:42:52.453001 <6>[ 2.139774] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10643 12:42:52.462861 <4>[ 2.147777] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10644 12:42:52.472786 <6>[ 2.157438] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10645 12:42:52.478949 <6>[ 2.165519] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10646 12:42:52.486130 <6>[ 2.173548] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10647 12:42:52.495586 <6>[ 2.181463] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10648 12:42:52.502295 <6>[ 2.189284] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10649 12:42:52.512613 <6>[ 2.197107] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10650 12:42:52.522633 <6>[ 2.207803] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10651 12:42:52.529174 <6>[ 2.216177] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10652 12:42:52.538750 <6>[ 2.224526] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10653 12:42:52.545758 <6>[ 2.232871] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10654 12:42:52.555600 <6>[ 2.241216] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10655 12:42:52.562149 <6>[ 2.249563] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10656 12:42:52.571968 <6>[ 2.257907] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10657 12:42:52.578571 <6>[ 2.266249] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10658 12:42:52.588401 <6>[ 2.274593] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10659 12:42:52.595299 <6>[ 2.282937] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10660 12:42:52.605167 <6>[ 2.291281] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10661 12:42:52.612452 <6>[ 2.299624] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10662 12:42:52.621985 <6>[ 2.307968] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10663 12:42:52.631751 <6>[ 2.316312] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10664 12:42:52.638516 <6>[ 2.324660] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10665 12:42:52.645440 <6>[ 2.333557] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10666 12:42:52.651657 <6>[ 2.340991] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10667 12:42:52.658291 <6>[ 2.348010] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10668 12:42:52.668803 <6>[ 2.355092] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10669 12:42:52.675571 <6>[ 2.362353] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10670 12:42:52.685592 <6>[ 2.369299] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10671 12:42:52.691915 <6>[ 2.378450] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10672 12:42:52.701663 <6>[ 2.387585] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10673 12:42:52.711490 <6>[ 2.396886] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10674 12:42:52.721736 <6>[ 2.406361] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10675 12:42:52.731907 <6>[ 2.415835] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10676 12:42:52.738005 <6>[ 2.424962] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10677 12:42:52.748231 <6>[ 2.434435] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10678 12:42:52.758100 <6>[ 2.443562] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10679 12:42:52.767755 <6>[ 2.452865] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10680 12:42:52.778065 <6>[ 2.463030] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10681 12:42:52.788284 <6>[ 2.474521] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10682 12:42:52.794649 <6>[ 2.484438] Trying to probe devices needed for running init ...
10683 12:42:52.808494 <6>[ 2.494905] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10684 12:42:52.837235 <6>[ 2.526919] hub 2-1:1.0: USB hub found
10685 12:42:52.840365 <6>[ 2.531456] hub 2-1:1.0: 3 ports detected
10686 12:42:52.960414 <6>[ 2.646683] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10687 12:42:53.113877 <6>[ 2.803105] hub 1-1:1.0: USB hub found
10688 12:42:53.117219 <6>[ 2.807460] hub 1-1:1.0: 4 ports detected
10689 12:42:53.192744 <6>[ 2.879072] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10690 12:42:53.436219 <6>[ 3.122830] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10691 12:42:53.569096 <6>[ 3.258887] hub 1-1.4:1.0: USB hub found
10692 12:42:53.572245 <6>[ 3.263541] hub 1-1.4:1.0: 2 ports detected
10693 12:42:53.868504 <6>[ 3.554832] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10694 12:42:54.060473 <6>[ 3.746829] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10695 12:43:05.068878 <6>[ 14.763384] ALSA device list:
10696 12:43:05.075976 <6>[ 14.766641] No soundcards found.
10697 12:43:05.088240 <6>[ 14.779028] Freeing unused kernel memory: 8384K
10698 12:43:05.091121 <6>[ 14.783956] Run /init as init process
10699 12:43:05.102628 Loading, please wait...
10700 12:43:05.130757 Starting systemd-udevd version 252.6-1
10701 12:43:05.536061 <6>[ 15.223683] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10702 12:43:05.545313 <6>[ 15.236318] remoteproc remoteproc0: scp is available
10703 12:43:05.555511 <4>[ 15.242325] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10704 12:43:05.562142 <6>[ 15.252255] remoteproc remoteproc0: powering up scp
10705 12:43:05.572158 <4>[ 15.257418] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10706 12:43:05.578316 <3>[ 15.267254] remoteproc remoteproc0: request_firmware failed: -2
10707 12:43:05.596659 <6>[ 15.284319] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10708 12:43:05.602918 <3>[ 15.284805] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10709 12:43:05.612832 <6>[ 15.286397] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10710 12:43:05.619500 <6>[ 15.292420] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10711 12:43:05.626831 <6>[ 15.292579] mc: Linux media interface: v0.10
10712 12:43:05.633695 <3>[ 15.300098] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10713 12:43:05.640077 <3>[ 15.300124] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10714 12:43:05.650650 <3>[ 15.300286] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10715 12:43:05.656757 <4>[ 15.301174] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10716 12:43:05.663799 <4>[ 15.301323] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10717 12:43:05.669969 <6>[ 15.301381] videodev: Linux video capture interface: v2.00
10718 12:43:05.676912 <6>[ 15.311290] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10719 12:43:05.687269 <4>[ 15.312802] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10720 12:43:05.693551 <4>[ 15.312802] Fallback method does not support PEC.
10721 12:43:05.700216 <3>[ 15.316508] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10722 12:43:05.706289 <3>[ 15.316515] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10723 12:43:05.716593 <3>[ 15.328265] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10724 12:43:05.726246 <3>[ 15.329493] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10725 12:43:05.732618 <3>[ 15.367213] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10726 12:43:05.742563 <3>[ 15.374559] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10727 12:43:05.749162 <6>[ 15.399062] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10728 12:43:05.755715 <3>[ 15.404312] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10729 12:43:05.765845 <6>[ 15.422465] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10730 12:43:05.775730 <3>[ 15.429937] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10731 12:43:05.785607 <6>[ 15.431174] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10732 12:43:05.792194 <6>[ 15.431572] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10733 12:43:05.799175 <6>[ 15.443316] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10734 12:43:05.809322 <3>[ 15.445126] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10735 12:43:05.815219 <6>[ 15.453207] pci_bus 0000:00: root bus resource [bus 00-ff]
10736 12:43:05.822239 <4>[ 15.456535] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10737 12:43:05.832080 <4>[ 15.456544] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10738 12:43:05.838485 <3>[ 15.462500] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10739 12:43:05.845471 <6>[ 15.470608] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10740 12:43:05.855273 <3>[ 15.480896] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10741 12:43:05.865233 <6>[ 15.489771] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10742 12:43:05.868408 <6>[ 15.490801] Bluetooth: Core ver 2.22
10743 12:43:05.874991 <6>[ 15.490859] NET: Registered PF_BLUETOOTH protocol family
10744 12:43:05.881801 <6>[ 15.490863] Bluetooth: HCI device and connection manager initialized
10745 12:43:05.884934 <6>[ 15.490878] Bluetooth: HCI socket layer initialized
10746 12:43:05.891559 <6>[ 15.490883] Bluetooth: L2CAP socket layer initialized
10747 12:43:05.895410 <6>[ 15.490893] Bluetooth: SCO socket layer initialized
10748 12:43:05.905025 <3>[ 15.496647] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10749 12:43:05.912455 <6>[ 15.497754] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10750 12:43:05.915444 <6>[ 15.498656] r8152 2-1.3:1.0 eth0: v1.12.13
10751 12:43:05.922619 <6>[ 15.498858] usbcore: registered new interface driver r8152
10752 12:43:05.935311 <6>[ 15.498958] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10753 12:43:05.938656 <6>[ 15.499113] usbcore: registered new interface driver uvcvideo
10754 12:43:05.945028 <6>[ 15.504779] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10755 12:43:05.955209 <3>[ 15.510482] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10756 12:43:05.961889 <6>[ 15.519532] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10757 12:43:05.968215 <6>[ 15.519910] usbcore: registered new interface driver cdc_ether
10758 12:43:05.974853 <3>[ 15.527620] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10759 12:43:05.985334 <3>[ 15.527630] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10760 12:43:05.991232 <3>[ 15.527682] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10761 12:43:05.998170 <6>[ 15.528590] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10762 12:43:06.004981 <6>[ 15.535925] pci 0000:00:00.0: supports D1 D2
10763 12:43:06.007617 <6>[ 15.536377] usbcore: registered new interface driver r8153_ecm
10764 12:43:06.014654 <6>[ 15.544209] usbcore: registered new interface driver btusb
10765 12:43:06.024939 <4>[ 15.544970] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10766 12:43:06.031165 <3>[ 15.544981] Bluetooth: hci0: Failed to load firmware file (-2)
10767 12:43:06.037510 <3>[ 15.544984] Bluetooth: hci0: Failed to set up firmware (-2)
10768 12:43:06.047960 <4>[ 15.544989] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10769 12:43:06.054611 <6>[ 15.547324] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10770 12:43:06.060687 <6>[ 15.551054] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10771 12:43:06.067918 <6>[ 15.552835] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10772 12:43:06.074534 <6>[ 15.765239] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10773 12:43:06.084207 <6>[ 15.771532] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10774 12:43:06.090904 <6>[ 15.779028] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10775 12:43:06.097674 <6>[ 15.786516] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10776 12:43:06.104301 <6>[ 15.794101] pci 0000:01:00.0: supports D1 D2
10777 12:43:06.110441 <6>[ 15.798624] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10778 12:43:06.131390 <6>[ 15.818764] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10779 12:43:06.137395 <6>[ 15.825676] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10780 12:43:06.144121 <6>[ 15.833763] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10781 12:43:06.154650 <6>[ 15.841771] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10782 12:43:06.161013 <6>[ 15.849782] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10783 12:43:06.170862 <6>[ 15.857795] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10784 12:43:06.174207 <6>[ 15.865802] pci 0000:00:00.0: PCI bridge to [bus 01]
10785 12:43:06.184131 <6>[ 15.871024] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10786 12:43:06.190611 <6>[ 15.879194] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10787 12:43:06.197719 <6>[ 15.886496] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10788 12:43:06.203963 <6>[ 15.893266] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10789 12:43:06.220586 <5>[ 15.908503] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10790 12:43:06.242420 <5>[ 15.930295] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10791 12:43:06.249681 <4>[ 15.937204] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10792 12:43:06.255997 <6>[ 15.946085] cfg80211: failed to load regulatory.db
10793 12:43:06.299936 <6>[ 15.987430] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10794 12:43:06.306558 <6>[ 15.994941] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10795 12:43:06.330607 <6>[ 16.021668] mt7921e 0000:01:00.0: ASIC revision: 79610010
10796 12:43:06.437884 <4>[ 16.122697] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10797 12:43:06.450775 Begin: Loading essential drivers ... done.
10798 12:43:06.453103 Begin: Running /scripts/init-premount ... done.
10799 12:43:06.460110 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10800 12:43:06.470174 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10801 12:43:06.473587 Device /sys/class/net/enx002432307852 found
10802 12:43:06.474118 done.
10803 12:43:06.499790 Begin: Waiting up to 180 secs for any network device to become available ... done.
10804 12:43:06.556975 <4>[ 16.241334] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10805 12:43:06.563779 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10806 12:43:06.676257 <4>[ 16.360471] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10807 12:43:06.792170 <4>[ 16.476308] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10808 12:43:06.907655 <4>[ 16.592222] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10809 12:43:07.023809 <4>[ 16.708172] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10810 12:43:07.139050 <4>[ 16.824079] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10811 12:43:07.254899 <4>[ 16.940024] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10812 12:43:07.370731 <4>[ 17.056009] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10813 12:43:07.486834 <4>[ 17.171930] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10814 12:43:07.583874 <6>[ 17.275118] r8152 2-1.3:1.0 enx002432307852: carrier on
10815 12:43:07.594270 <3>[ 17.285880] mt7921e 0000:01:00.0: hardware init failed
10816 12:43:08.539519 IP-Config: no response after 2 secs - giving up
10817 12:43:08.582737 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10818 12:43:08.586015 IP-Config: enx002432307852 complete (dhcp from 192.168.201.1):
10819 12:43:08.592807 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10820 12:43:08.599375 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10821 12:43:08.606113 host : mt8192-asurada-spherion-r0-cbg-3
10822 12:43:08.612169 domain : lava-rack
10823 12:43:08.615622 rootserver: 192.168.201.1 rootpath:
10824 12:43:08.618783 filename :
10825 12:43:08.681683 done.
10826 12:43:08.691092 Begin: Running /scripts/nfs-bottom ... done.
10827 12:43:08.712188 Begin: Running /scripts/init-bottom ... done.
10828 12:43:10.020927 <6>[ 19.712633] NET: Registered PF_INET6 protocol family
10829 12:43:10.027735 <6>[ 19.719174] Segment Routing with IPv6
10830 12:43:10.031044 <6>[ 19.723145] In-situ OAM (IOAM) with IPv6
10831 12:43:10.217092 <30>[ 19.882404] systemd[1]: systemd 252.6-1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10832 12:43:10.223636 <30>[ 19.914850] systemd[1]: Detected architecture arm64.
10833 12:43:10.234236
10834 12:43:10.237274 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10835 12:43:10.237570
10836 12:43:10.265544 <30>[ 19.956945] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10837 12:43:11.091718 <30>[ 20.780268] systemd[1]: Queued start job for default target graphical.target.
10838 12:43:11.140725 <30>[ 20.828795] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10839 12:43:11.146902 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10840 12:43:11.167016 <30>[ 20.855626] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10841 12:43:11.176925 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10842 12:43:11.196568 <30>[ 20.884287] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10843 12:43:11.205741 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10844 12:43:11.223246 <30>[ 20.911467] systemd[1]: Created slice user.slice - User and Session Slice.
10845 12:43:11.229477 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10846 12:43:11.250493 <30>[ 20.935062] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10847 12:43:11.256410 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10848 12:43:11.277915 <30>[ 20.963009] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10849 12:43:11.284779 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10850 12:43:11.312311 <30>[ 20.990924] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10851 12:43:11.322368 <30>[ 21.010681] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10852 12:43:11.329253 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10853 12:43:11.346482 <30>[ 21.034917] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10854 12:43:11.356353 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10855 12:43:11.371728 <30>[ 21.062935] systemd[1]: Reached target paths.target - Path Units.
10856 12:43:11.378064 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10857 12:43:11.398319 <30>[ 21.086884] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10858 12:43:11.404865 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10859 12:43:11.419078 <30>[ 21.110860] systemd[1]: Reached target slices.target - Slice Units.
10860 12:43:11.429169 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10861 12:43:11.443770 <30>[ 21.135188] systemd[1]: Reached target swap.target - Swaps.
10862 12:43:11.450651 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10863 12:43:11.470559 <30>[ 21.158940] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10864 12:43:11.480321 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10865 12:43:11.499090 <30>[ 21.187511] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10866 12:43:11.508589 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10867 12:43:11.527659 <30>[ 21.216413] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10868 12:43:11.538131 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10869 12:43:11.556725 <30>[ 21.244795] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10870 12:43:11.566105 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10871 12:43:11.582869 <30>[ 21.271730] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10872 12:43:11.589473 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10873 12:43:11.608114 <30>[ 21.296454] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10874 12:43:11.617469 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10875 12:43:11.637964 <30>[ 21.326620] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10876 12:43:11.647831 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10877 12:43:11.662326 <30>[ 21.351157] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10878 12:43:11.672120 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10879 12:43:11.722176 <30>[ 21.411096] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10880 12:43:11.729126 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10881 12:43:11.748282 <30>[ 21.437231] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10882 12:43:11.754996 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10883 12:43:11.776372 <30>[ 21.465387] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10884 12:43:11.782723 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10885 12:43:11.809470 <30>[ 21.491164] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10886 12:43:11.821387 <30>[ 21.510288] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10887 12:43:11.830966 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10888 12:43:11.852502 <30>[ 21.541603] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10889 12:43:11.859316 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10890 12:43:11.926610 <30>[ 21.615227] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10891 12:43:11.932921 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10892 12:43:11.957084 <30>[ 21.645678] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10893 12:43:11.970207 Starting [0;1;39mmodprobe@drm.service[0m - Load Kerne<6>[ 21.658999] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10894 12:43:11.973434 l Module drm...
10895 12:43:11.994031 <30>[ 21.681908] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10896 12:43:12.000189 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10897 12:43:12.021148 <30>[ 21.709642] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10898 12:43:12.027496 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10899 12:43:12.049356 <30>[ 21.737748] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10900 12:43:12.058754 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop..<6>[ 21.751691] fuse: init (API version 7.37)
10901 12:43:12.059184 .
10902 12:43:12.083221 <30>[ 21.771949] systemd[1]: Starting systemd-journald.service - Journal Service...
10903 12:43:12.090017 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10904 12:43:12.117193 <30>[ 21.805930] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10905 12:43:12.123760 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10906 12:43:12.148221 <30>[ 21.833772] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10907 12:43:12.155135 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10908 12:43:12.177940 <30>[ 21.866891] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10909 12:43:12.187987 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10910 12:43:12.247800 <30>[ 21.935474] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10911 12:43:12.257672 Startin<3>[ 21.944802] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10912 12:43:12.264382 g [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10913 12:43:12.286277 <30>[ 21.974968] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10914 12:43:12.293214 <3>[ 21.978187] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10915 12:43:12.302680 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10916 12:43:12.318957 <30>[ 22.007285] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10917 12:43:12.325564 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10918 12:43:12.342404 <3>[ 22.030966] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10919 12:43:12.351887 <30>[ 22.031256] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10920 12:43:12.359070 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10921 12:43:12.373971 <3>[ 22.062830] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10922 12:43:12.383849 <30>[ 22.072513] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10923 12:43:12.394462 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10924 12:43:12.404260 <3>[ 22.092674] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 12:43:12.415049 <30>[ 22.103988] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10926 12:43:12.421935 <30>[ 22.111872] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10927 12:43:12.435527 [[0;32m OK [0m] Finished [0<3>[ 22.123353] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10928 12:43:12.441765 ;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10929 12:43:12.456760 <30>[ 22.147835] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10930 12:43:12.466709 <3>[ 22.155020] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 12:43:12.476803 <30>[ 22.155486] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10932 12:43:12.483393 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10933 12:43:12.497322 <3>[ 22.185680] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10934 12:43:12.507514 <30>[ 22.196057] systemd[1]: modprobe@drm.service: Deactivated successfully.
10935 12:43:12.514429 <30>[ 22.203473] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10936 12:43:12.527466 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m -<3>[ 22.215556] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10937 12:43:12.530806 Load Kernel Module drm.
10938 12:43:12.551715 <30>[ 22.239932] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10939 12:43:12.558618 <3>[ 22.247395] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10940 12:43:12.568725 <30>[ 22.247915] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10941 12:43:12.575051 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10942 12:43:12.596895 <30>[ 22.288083] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10943 12:43:12.607474 <30>[ 22.295570] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10944 12:43:12.614419 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10945 12:43:12.634794 <30>[ 22.323441] systemd[1]: Started systemd-journald.service - Journal Service.
10946 12:43:12.641297 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10947 12:43:12.661135 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10948 12:43:12.679405 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10949 12:43:12.703416 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10950 12:43:12.723436 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10951 12:43:12.747662 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10952 12:43:12.802828 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10953 12:43:12.825300 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10954 12:43:12.853963 <4>[ 22.535897] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10955 12:43:12.863939 <3>[ 22.551574] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10956 12:43:12.888093 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10957 12:43:12.913688 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10958 12:43:12.941057 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10959 12:43:12.962357 <46>[ 22.651584] systemd-journald[297]: Received client request to flush runtime journal.
10960 12:43:12.969066 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10961 12:43:13.001576 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10962 12:43:13.022744 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10963 12:43:13.042201 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10964 12:43:13.058597 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10965 12:43:13.074720 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10966 12:43:14.069402 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10967 12:43:14.122790 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10968 12:43:14.360864 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10969 12:43:14.441054 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10970 12:43:14.462173 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10971 12:43:14.477493 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10972 12:43:14.533701 Starting [0;1;39msystemd-binfmt.se…et Up Additional Binary Formats...
10973 12:43:14.552336 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10974 12:43:14.575806 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10975 12:43:14.598317 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-bi… Set Up Additional Binary Formats.
10976 12:43:14.610590 See 'systemctl status systemd-binfmt.service' for details.
10977 12:43:14.846001 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10978 12:43:14.903552 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10979 12:43:14.949627 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10980 12:43:14.998950 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10981 12:43:15.088936 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10982 12:43:15.115375 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10983 12:43:15.355834 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10984 12:43:15.404568 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10985 12:43:15.425475 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10986 12:43:15.435353 <6>[ 25.128178] remoteproc remoteproc0: powering up scp
10987 12:43:15.448690 <4>[ 25.138283] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10988 12:43:15.456011 <3>[ 25.148579] remoteproc remoteproc0: request_firmware failed: -2
10989 12:43:15.465989 [[0;32m OK [<3>[ 25.155926] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10990 12:43:15.472596 0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10991 12:43:15.504987 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10992 12:43:15.523053 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10993 12:43:15.542067 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10994 12:43:15.557749 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10995 12:43:15.571622 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10996 12:43:15.597051 [[0;32m OK [0m] Reached target [0;1;39msysi<46>[ 25.286051] systemd-journald[297]: Time jumped backwards, rotating.
10997 12:43:15.600012 nit.target[0m - System Initialization.
10998 12:43:15.617356 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10999 12:43:15.633708 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11000 12:43:15.659325 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11001 12:43:15.859279 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11002 12:43:15.877704 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11003 12:43:16.304518 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11004 12:43:16.396126 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11005 12:43:16.413780 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11006 12:43:16.673761 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11007 12:43:16.689640 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11008 12:43:16.705613 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11009 12:43:16.755385 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11010 12:43:17.122348 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11011 12:43:17.522222 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11012 12:43:17.551598 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11013 12:43:17.606547 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11014 12:43:17.745446 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11015 12:43:17.765792 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11016 12:43:17.806125 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11017 12:43:17.838093 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11018 12:43:17.857722 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11019 12:43:17.875662 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11020 12:43:17.894503 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11021 12:43:17.925276 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11022 12:43:17.951312 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11023 12:43:17.969486 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11024 12:43:18.010880 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
11025 12:43:18.029357 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11026 12:43:18.072948 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11027 12:43:18.173490 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11028 12:43:18.254622
11029 12:43:18.254940
11030 12:43:18.257734 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11031 12:43:18.258023
11032 12:43:18.261306 debian-bookworm-arm64 login: root (automatic login)
11033 12:43:18.261670
11034 12:43:18.261962
11035 12:43:18.569942 Linux debian-bookworm-arm64 6.1.31 #1 SMP PREEMPT Wed Jun 14 12:30:40 UTC 2023 aarch64
11036 12:43:18.570152
11037 12:43:18.576789 The programs included with the Debian GNU/Linux system are free software;
11038 12:43:18.582955 the exact distribution terms for each program are described in the
11039 12:43:18.586771 individual files in /usr/share/doc/*/copyright.
11040 12:43:18.587055
11041 12:43:18.593171 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11042 12:43:18.596742 permitted by applicable law.
11043 12:43:19.694547 Matched prompt #10: / #
11045 12:43:19.695792 Setting prompt string to ['/ #']
11046 12:43:19.696245 end: 2.2.5.1 login-action (duration 00:00:30) [common]
11048 12:43:19.697282 end: 2.2.5 auto-login-action (duration 00:00:30) [common]
11049 12:43:19.697728 start: 2.2.6 expect-shell-connection (timeout 00:03:13) [common]
11050 12:43:19.698086 Setting prompt string to ['/ #']
11051 12:43:19.698431 Forcing a shell prompt, looking for ['/ #']
11053 12:43:19.749369 / #
11054 12:43:19.749985 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11055 12:43:19.750439 Waiting using forced prompt support (timeout 00:02:30)
11056 12:43:19.755808
11057 12:43:19.756721 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11058 12:43:19.757221 start: 2.2.7 export-device-env (timeout 00:03:13) [common]
11060 12:43:19.858428 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10724845/extract-nfsrootfs-wc08wldn'
11061 12:43:19.864428 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10724845/extract-nfsrootfs-wc08wldn'
11063 12:43:19.965798 / # export NFS_SERVER_IP='192.168.201.1'
11064 12:43:19.971871 export NFS_SERVER_IP='192.168.201.1'
11065 12:43:19.972647 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11066 12:43:19.973167 end: 2.2 depthcharge-retry (duration 00:01:47) [common]
11067 12:43:19.973641 end: 2 depthcharge-action (duration 00:01:47) [common]
11068 12:43:19.974123 start: 3 lava-test-retry (timeout 00:07:29) [common]
11069 12:43:19.974568 start: 3.1 lava-test-shell (timeout 00:07:29) [common]
11070 12:43:19.974974 Using namespace: common
11072 12:43:20.076178 / # #
11073 12:43:20.076849 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11074 12:43:20.082848 #
11075 12:43:20.083747 Using /lava-10724845
11077 12:43:20.184969 / # export SHELL=/bin/bash
11078 12:43:20.191310 export SHELL=/bin/bash
11080 12:43:20.293001 / # . /lava-10724845/environment
11081 12:43:20.299685 . /lava-10724845/environment
11083 12:43:20.406993 / # /lava-10724845/bin/lava-test-runner /lava-10724845/0
11084 12:43:20.407573 Test shell timeout: 10s (minimum of the action and connection timeout)
11085 12:43:20.412588 /lava-10724845/bin/lava-test-runner /lava-10724845/0
11086 12:43:20.702738 + export TESTRUN_ID=0_timesync-off
11087 12:43:20.705602 + TESTRUN_ID=0_timesync-off
11088 12:43:20.708883 + cd /lava-10724845/0/tests/0_timesync-off
11089 12:43:20.712213 ++ cat uuid
11090 12:43:20.717736 + UUID=10724845_1.6.2.3.1
11091 12:43:20.717820 + set +x
11092 12:43:20.724767 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10724845_1.6.2.3.1>
11093 12:43:20.725032 Received signal: <STARTRUN> 0_timesync-off 10724845_1.6.2.3.1
11094 12:43:20.725110 Starting test lava.0_timesync-off (10724845_1.6.2.3.1)
11095 12:43:20.725194 Skipping test definition patterns.
11096 12:43:20.727716 + systemctl stop systemd-timesyncd
11097 12:43:20.783599 + set +x
11098 12:43:20.786801 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10724845_1.6.2.3.1>
11099 12:43:20.787212 Received signal: <ENDRUN> 0_timesync-off 10724845_1.6.2.3.1
11100 12:43:20.787450 Ending use of test pattern.
11101 12:43:20.787613 Ending test lava.0_timesync-off (10724845_1.6.2.3.1), duration 0.06
11103 12:43:20.860068 + export TESTRUN_ID=1_kselftest-alsa
11104 12:43:20.863354 + TESTRUN_ID=1_kselftest-alsa
11105 12:43:20.869929 + cd /lava-10724845/0/tests/1_kselftest-alsa
11106 12:43:20.870028 ++ cat uuid
11107 12:43:20.876530 + UUID=10724845_1.6.2.3.5
11108 12:43:20.876640 + set +x
11109 12:43:20.883599 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 10724845_1.6.2.3.5>
11110 12:43:20.883899 Received signal: <STARTRUN> 1_kselftest-alsa 10724845_1.6.2.3.5
11111 12:43:20.884032 Starting test lava.1_kselftest-alsa (10724845_1.6.2.3.5)
11112 12:43:20.884152 Skipping test definition patterns.
11113 12:43:20.886855 + cd ./automated/linux/kselftest/
11114 12:43:20.912904 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11115 12:43:20.957899 INFO: install_deps skipped
11116 12:43:21.451709 --2023-06-14 12:43:21-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11117 12:43:21.454911 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11118 12:43:21.585507 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11119 12:43:21.718760 HTTP request sent, awaiting response... 200 OK
11120 12:43:21.722172 Length: 2878416 (2.7M) [application/octet-stream]
11121 12:43:21.725719 Saving to: 'kselftest.tar.xz'
11122 12:43:21.725803
11123 12:43:21.725870
11124 12:43:21.987025 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11125 12:43:22.255265 kselftest.tar.xz 1%[ ] 47.81K 179KB/s
11126 12:43:22.569667 kselftest.tar.xz 7%[> ] 217.50K 407KB/s
11127 12:43:22.844384 kselftest.tar.xz 28%[====> ] 808.57K 952KB/s
11128 12:43:22.976149 kselftest.tar.xz 67%[============> ] 1.85M 1.65MB/s
11129 12:43:22.982431 kselftest.tar.xz 100%[===================>] 2.74M 2.19MB/s in 1.3s
11130 12:43:22.982554
11131 12:43:23.237185 2023-06-14 12:43:23 (2.19 MB/s) - 'kselftest.tar.xz' saved [2878416/2878416]
11132 12:43:23.237366
11133 12:43:29.215277 skiplist:
11134 12:43:29.218442 ========================================
11135 12:43:29.221415 ========================================
11136 12:43:29.269374 alsa:mixer-test
11137 12:43:29.290608 ============== Tests to run ===============
11138 12:43:29.290755 alsa:mixer-test
11139 12:43:29.293842 ===========End Tests to run ===============
11140 12:43:29.396815 <12>[ 39.090851] kselftest: Running tests in alsa
11141 12:43:29.406278 TAP version 13
11142 12:43:29.421556 1..1
11143 12:43:29.437406 # selftests: alsa: mixer-test
11144 12:43:29.882669 # TAP version 13
11145 12:43:29.882825 # 1..0
11146 12:43:29.890164 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11147 12:43:29.892659 ok 1 selftests: alsa: mixer-test
11148 12:43:30.554659 alsa_mixer-test pass
11149 12:43:30.586999 + ../../utils/send-to-lava.sh ./output/result.txt
11150 12:43:30.661829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11151 12:43:30.661982 + set +x
11152 12:43:30.662227 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11154 12:43:30.668355 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 10724845_1.6.2.3.5>
11155 12:43:30.668612 Received signal: <ENDRUN> 1_kselftest-alsa 10724845_1.6.2.3.5
11156 12:43:30.668687 Ending use of test pattern.
11157 12:43:30.668749 Ending test lava.1_kselftest-alsa (10724845_1.6.2.3.5), duration 9.78
11159 12:43:30.671721 <LAVA_TEST_RUNNER EXIT>
11160 12:43:30.671972 ok: lava_test_shell seems to have completed
11161 12:43:30.672070 alsa_mixer-test: pass
11162 12:43:30.672161 end: 3.1 lava-test-shell (duration 00:00:11) [common]
11163 12:43:30.672247 end: 3 lava-test-retry (duration 00:00:11) [common]
11164 12:43:30.672334 start: 4 finalize (timeout 00:07:18) [common]
11165 12:43:30.672425 start: 4.1 power-off (timeout 00:00:30) [common]
11166 12:43:30.672579 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11167 12:43:30.748610 >> Command sent successfully.
11168 12:43:30.751150 Returned 0 in 0 seconds
11169 12:43:30.851525 end: 4.1 power-off (duration 00:00:00) [common]
11171 12:43:30.851862 start: 4.2 read-feedback (timeout 00:07:18) [common]
11172 12:43:30.852134 Listened to connection for namespace 'common' for up to 1s
11173 12:43:31.853092 Finalising connection for namespace 'common'
11174 12:43:31.853264 Disconnecting from shell: Finalise
11175 12:43:31.853344 / #
11176 12:43:31.953684 end: 4.2 read-feedback (duration 00:00:01) [common]
11177 12:43:31.953876 end: 4 finalize (duration 00:00:01) [common]
11178 12:43:31.953994 Cleaning after the job
11179 12:43:31.954096 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724845/tftp-deploy-toqeg7bi/ramdisk
11180 12:43:31.956461 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724845/tftp-deploy-toqeg7bi/kernel
11181 12:43:31.965657 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724845/tftp-deploy-toqeg7bi/dtb
11182 12:43:31.965830 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724845/tftp-deploy-toqeg7bi/nfsrootfs
11183 12:43:32.039883 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724845/tftp-deploy-toqeg7bi/modules
11184 12:43:32.045293 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10724845
11185 12:43:32.582821 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10724845
11186 12:43:32.583005 Job finished correctly