Boot log: mt8192-asurada-spherion-r0

    1 12:39:26.575062  lava-dispatcher, installed at version: 2023.05.1
    2 12:39:26.575277  start: 0 validate
    3 12:39:26.575413  Start time: 2023-06-14 12:39:26.575405+00:00 (UTC)
    4 12:39:26.575544  Using caching service: 'http://localhost/cache/?uri=%s'
    5 12:39:26.575673  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230609.0%2Farm64%2Finitrd.cpio.gz exists
    6 12:39:26.834825  Using caching service: 'http://localhost/cache/?uri=%s'
    7 12:39:26.835125  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
    8 12:39:52.897025  Using caching service: 'http://localhost/cache/?uri=%s'
    9 12:39:52.897243  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
   10 12:39:53.166219  Using caching service: 'http://localhost/cache/?uri=%s'
   11 12:39:53.166391  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230609.0%2Farm64%2Ffull.rootfs.tar.xz exists
   12 12:39:53.688321  Using caching service: 'http://localhost/cache/?uri=%s'
   13 12:39:53.688522  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
   14 12:39:55.692095  validate duration: 29.12
   16 12:39:55.692355  start: 1 tftp-deploy (timeout 00:10:00) [common]
   17 12:39:55.692459  start: 1.1 download-retry (timeout 00:10:00) [common]
   18 12:39:55.692548  start: 1.1.1 http-download (timeout 00:10:00) [common]
   19 12:39:55.692676  Not decompressing ramdisk as can be used compressed.
   20 12:39:55.692792  downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230609.0/arm64/initrd.cpio.gz
   21 12:39:55.692933  saving as /var/lib/lava/dispatcher/tmp/10724866/tftp-deploy-7g8zvg_1/ramdisk/initrd.cpio.gz
   22 12:39:55.693003  total size: 4665598 (4MB)
   23 12:39:55.953361  progress   0% (0MB)
   24 12:39:55.954847  progress   5% (0MB)
   25 12:39:55.956192  progress  10% (0MB)
   26 12:39:55.957499  progress  15% (0MB)
   27 12:39:55.958775  progress  20% (0MB)
   28 12:39:55.960055  progress  25% (1MB)
   29 12:39:55.961345  progress  30% (1MB)
   30 12:39:55.962567  progress  35% (1MB)
   31 12:39:55.963791  progress  40% (1MB)
   32 12:39:55.965259  progress  45% (2MB)
   33 12:39:55.966519  progress  50% (2MB)
   34 12:39:55.967822  progress  55% (2MB)
   35 12:39:55.969182  progress  60% (2MB)
   36 12:39:55.970431  progress  65% (2MB)
   37 12:39:55.971716  progress  70% (3MB)
   38 12:39:55.972990  progress  75% (3MB)
   39 12:39:55.974205  progress  80% (3MB)
   40 12:39:55.975627  progress  85% (3MB)
   41 12:39:55.976891  progress  90% (4MB)
   42 12:39:55.978139  progress  95% (4MB)
   43 12:39:55.979427  progress 100% (4MB)
   44 12:39:55.979607  4MB downloaded in 0.29s (15.53MB/s)
   45 12:39:55.979806  end: 1.1.1 http-download (duration 00:00:00) [common]
   47 12:39:55.980054  end: 1.1 download-retry (duration 00:00:00) [common]
   48 12:39:55.980141  start: 1.2 download-retry (timeout 00:10:00) [common]
   49 12:39:55.980228  start: 1.2.1 http-download (timeout 00:10:00) [common]
   50 12:39:55.980363  downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
   51 12:39:55.980456  saving as /var/lib/lava/dispatcher/tmp/10724866/tftp-deploy-7g8zvg_1/kernel/Image
   52 12:39:55.980545  total size: 47581696 (45MB)
   53 12:39:55.980634  No compression specified
   54 12:39:55.981806  progress   0% (0MB)
   55 12:39:55.994149  progress   5% (2MB)
   56 12:39:56.007218  progress  10% (4MB)
   57 12:39:56.020134  progress  15% (6MB)
   58 12:39:56.033815  progress  20% (9MB)
   59 12:39:56.047157  progress  25% (11MB)
   60 12:39:56.060244  progress  30% (13MB)
   61 12:39:56.073213  progress  35% (15MB)
   62 12:39:56.086031  progress  40% (18MB)
   63 12:39:56.099004  progress  45% (20MB)
   64 12:39:56.112014  progress  50% (22MB)
   65 12:39:56.125015  progress  55% (24MB)
   66 12:39:56.138153  progress  60% (27MB)
   67 12:39:56.151061  progress  65% (29MB)
   68 12:39:56.164176  progress  70% (31MB)
   69 12:39:56.177351  progress  75% (34MB)
   70 12:39:56.190145  progress  80% (36MB)
   71 12:39:56.202957  progress  85% (38MB)
   72 12:39:56.215362  progress  90% (40MB)
   73 12:39:56.228036  progress  95% (43MB)
   74 12:39:56.240736  progress 100% (45MB)
   75 12:39:56.240966  45MB downloaded in 0.26s (174.25MB/s)
   76 12:39:56.241125  end: 1.2.1 http-download (duration 00:00:00) [common]
   78 12:39:56.241367  end: 1.2 download-retry (duration 00:00:00) [common]
   79 12:39:56.241456  start: 1.3 download-retry (timeout 00:09:59) [common]
   80 12:39:56.241545  start: 1.3.1 http-download (timeout 00:09:59) [common]
   81 12:39:56.241684  downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
   82 12:39:56.241759  saving as /var/lib/lava/dispatcher/tmp/10724866/tftp-deploy-7g8zvg_1/dtb/mt8192-asurada-spherion-r0.dtb
   83 12:39:56.241824  total size: 46924 (0MB)
   84 12:39:56.241884  No compression specified
   85 12:39:56.243000  progress  69% (0MB)
   86 12:39:56.243283  progress 100% (0MB)
   87 12:39:56.243469  0MB downloaded in 0.00s (27.25MB/s)
   88 12:39:56.243639  end: 1.3.1 http-download (duration 00:00:00) [common]
   90 12:39:56.243996  end: 1.3 download-retry (duration 00:00:00) [common]
   91 12:39:56.244109  start: 1.4 download-retry (timeout 00:09:59) [common]
   92 12:39:56.244224  start: 1.4.1 http-download (timeout 00:09:59) [common]
   93 12:39:56.244371  downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230609.0/arm64/full.rootfs.tar.xz
   94 12:39:56.244466  saving as /var/lib/lava/dispatcher/tmp/10724866/tftp-deploy-7g8zvg_1/nfsrootfs/full.rootfs.tar
   95 12:39:56.244590  total size: 125248124 (119MB)
   96 12:39:56.244678  Using unxz to decompress xz
   97 12:39:56.248721  progress   0% (0MB)
   98 12:39:56.573994  progress   5% (6MB)
   99 12:39:56.908665  progress  10% (11MB)
  100 12:39:57.250871  progress  15% (17MB)
  101 12:39:57.442820  progress  20% (23MB)
  102 12:39:57.630894  progress  25% (29MB)
  103 12:39:58.009042  progress  30% (35MB)
  104 12:39:58.382915  progress  35% (41MB)
  105 12:39:58.779643  progress  40% (47MB)
  106 12:39:59.175651  progress  45% (53MB)
  107 12:39:59.587973  progress  50% (59MB)
  108 12:39:59.967657  progress  55% (65MB)
  109 12:40:00.362688  progress  60% (71MB)
  110 12:40:00.741978  progress  65% (77MB)
  111 12:40:01.149903  progress  70% (83MB)
  112 12:40:01.565289  progress  75% (89MB)
  113 12:40:02.014977  progress  80% (95MB)
  114 12:40:02.464957  progress  85% (101MB)
  115 12:40:02.724231  progress  90% (107MB)
  116 12:40:03.060700  progress  95% (113MB)
  117 12:40:03.432488  progress 100% (119MB)
  118 12:40:03.437642  119MB downloaded in 7.19s (16.61MB/s)
  119 12:40:03.438009  end: 1.4.1 http-download (duration 00:00:07) [common]
  121 12:40:03.438402  end: 1.4 download-retry (duration 00:00:07) [common]
  122 12:40:03.438530  start: 1.5 download-retry (timeout 00:09:52) [common]
  123 12:40:03.438656  start: 1.5.1 http-download (timeout 00:09:52) [common]
  124 12:40:03.438853  downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
  125 12:40:03.438961  saving as /var/lib/lava/dispatcher/tmp/10724866/tftp-deploy-7g8zvg_1/modules/modules.tar
  126 12:40:03.439057  total size: 8536768 (8MB)
  127 12:40:03.439153  Using unxz to decompress xz
  128 12:40:03.443343  progress   0% (0MB)
  129 12:40:03.465369  progress   5% (0MB)
  130 12:40:03.492483  progress  10% (0MB)
  131 12:40:03.524817  progress  15% (1MB)
  132 12:40:03.549474  progress  20% (1MB)
  133 12:40:03.574152  progress  25% (2MB)
  134 12:40:03.599438  progress  30% (2MB)
  135 12:40:03.624918  progress  35% (2MB)
  136 12:40:03.653665  progress  40% (3MB)
  137 12:40:03.680140  progress  45% (3MB)
  138 12:40:03.706739  progress  50% (4MB)
  139 12:40:03.732543  progress  55% (4MB)
  140 12:40:03.758976  progress  60% (4MB)
  141 12:40:03.785141  progress  65% (5MB)
  142 12:40:03.811369  progress  70% (5MB)
  143 12:40:03.837431  progress  75% (6MB)
  144 12:40:03.863682  progress  80% (6MB)
  145 12:40:03.889645  progress  85% (6MB)
  146 12:40:03.917874  progress  90% (7MB)
  147 12:40:03.945375  progress  95% (7MB)
  148 12:40:03.970080  progress 100% (8MB)
  149 12:40:03.977297  8MB downloaded in 0.54s (15.13MB/s)
  150 12:40:03.977575  end: 1.5.1 http-download (duration 00:00:01) [common]
  152 12:40:03.977843  end: 1.5 download-retry (duration 00:00:01) [common]
  153 12:40:03.977934  start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
  154 12:40:03.978028  start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
  155 12:40:05.982654  Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10724866/extract-nfsrootfs-176kw0_e
  156 12:40:05.982842  end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
  157 12:40:05.982944  start: 1.6.2 lava-overlay (timeout 00:09:50) [common]
  158 12:40:05.983109  [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10724866/lava-overlay-lh7g_n7h
  159 12:40:05.983274  makedir: /var/lib/lava/dispatcher/tmp/10724866/lava-overlay-lh7g_n7h/lava-10724866/bin
  160 12:40:05.983409  makedir: /var/lib/lava/dispatcher/tmp/10724866/lava-overlay-lh7g_n7h/lava-10724866/tests
  161 12:40:05.983508  makedir: /var/lib/lava/dispatcher/tmp/10724866/lava-overlay-lh7g_n7h/lava-10724866/results
  162 12:40:05.983609  Creating /var/lib/lava/dispatcher/tmp/10724866/lava-overlay-lh7g_n7h/lava-10724866/bin/lava-add-keys
  163 12:40:05.983747  Creating /var/lib/lava/dispatcher/tmp/10724866/lava-overlay-lh7g_n7h/lava-10724866/bin/lava-add-sources
  164 12:40:05.983871  Creating /var/lib/lava/dispatcher/tmp/10724866/lava-overlay-lh7g_n7h/lava-10724866/bin/lava-background-process-start
  165 12:40:05.983995  Creating /var/lib/lava/dispatcher/tmp/10724866/lava-overlay-lh7g_n7h/lava-10724866/bin/lava-background-process-stop
  166 12:40:05.984115  Creating /var/lib/lava/dispatcher/tmp/10724866/lava-overlay-lh7g_n7h/lava-10724866/bin/lava-common-functions
  167 12:40:05.984235  Creating /var/lib/lava/dispatcher/tmp/10724866/lava-overlay-lh7g_n7h/lava-10724866/bin/lava-echo-ipv4
  168 12:40:05.984355  Creating /var/lib/lava/dispatcher/tmp/10724866/lava-overlay-lh7g_n7h/lava-10724866/bin/lava-install-packages
  169 12:40:05.984473  Creating /var/lib/lava/dispatcher/tmp/10724866/lava-overlay-lh7g_n7h/lava-10724866/bin/lava-installed-packages
  170 12:40:05.984591  Creating /var/lib/lava/dispatcher/tmp/10724866/lava-overlay-lh7g_n7h/lava-10724866/bin/lava-os-build
  171 12:40:05.984709  Creating /var/lib/lava/dispatcher/tmp/10724866/lava-overlay-lh7g_n7h/lava-10724866/bin/lava-probe-channel
  172 12:40:05.984862  Creating /var/lib/lava/dispatcher/tmp/10724866/lava-overlay-lh7g_n7h/lava-10724866/bin/lava-probe-ip
  173 12:40:05.984997  Creating /var/lib/lava/dispatcher/tmp/10724866/lava-overlay-lh7g_n7h/lava-10724866/bin/lava-target-ip
  174 12:40:05.985115  Creating /var/lib/lava/dispatcher/tmp/10724866/lava-overlay-lh7g_n7h/lava-10724866/bin/lava-target-mac
  175 12:40:05.985232  Creating /var/lib/lava/dispatcher/tmp/10724866/lava-overlay-lh7g_n7h/lava-10724866/bin/lava-target-storage
  176 12:40:05.985355  Creating /var/lib/lava/dispatcher/tmp/10724866/lava-overlay-lh7g_n7h/lava-10724866/bin/lava-test-case
  177 12:40:05.985474  Creating /var/lib/lava/dispatcher/tmp/10724866/lava-overlay-lh7g_n7h/lava-10724866/bin/lava-test-event
  178 12:40:05.985633  Creating /var/lib/lava/dispatcher/tmp/10724866/lava-overlay-lh7g_n7h/lava-10724866/bin/lava-test-feedback
  179 12:40:05.985751  Creating /var/lib/lava/dispatcher/tmp/10724866/lava-overlay-lh7g_n7h/lava-10724866/bin/lava-test-raise
  180 12:40:05.985900  Creating /var/lib/lava/dispatcher/tmp/10724866/lava-overlay-lh7g_n7h/lava-10724866/bin/lava-test-reference
  181 12:40:05.986019  Creating /var/lib/lava/dispatcher/tmp/10724866/lava-overlay-lh7g_n7h/lava-10724866/bin/lava-test-runner
  182 12:40:05.986138  Creating /var/lib/lava/dispatcher/tmp/10724866/lava-overlay-lh7g_n7h/lava-10724866/bin/lava-test-set
  183 12:40:05.986257  Creating /var/lib/lava/dispatcher/tmp/10724866/lava-overlay-lh7g_n7h/lava-10724866/bin/lava-test-shell
  184 12:40:05.986377  Updating /var/lib/lava/dispatcher/tmp/10724866/lava-overlay-lh7g_n7h/lava-10724866/bin/lava-install-packages (oe)
  185 12:40:05.986519  Updating /var/lib/lava/dispatcher/tmp/10724866/lava-overlay-lh7g_n7h/lava-10724866/bin/lava-installed-packages (oe)
  186 12:40:05.986674  Creating /var/lib/lava/dispatcher/tmp/10724866/lava-overlay-lh7g_n7h/lava-10724866/environment
  187 12:40:05.986771  LAVA metadata
  188 12:40:05.986840  - LAVA_JOB_ID=10724866
  189 12:40:05.986903  - LAVA_DISPATCHER_IP=192.168.201.1
  190 12:40:05.986999  start: 1.6.2.1 lava-vland-overlay (timeout 00:09:50) [common]
  191 12:40:05.987065  skipped lava-vland-overlay
  192 12:40:05.987139  end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
  193 12:40:05.987218  start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:50) [common]
  194 12:40:05.987309  skipped lava-multinode-overlay
  195 12:40:05.987383  end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
  196 12:40:05.987461  start: 1.6.2.3 test-definition (timeout 00:09:50) [common]
  197 12:40:05.987533  Loading test definitions
  198 12:40:05.987624  start: 1.6.2.3.1 inline-repo-action (timeout 00:09:50) [common]
  199 12:40:05.987698  Using /lava-10724866 at stage 0
  200 12:40:05.988005  uuid=10724866_1.6.2.3.1 testdef=None
  201 12:40:05.988106  end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
  202 12:40:05.988190  start: 1.6.2.3.2 test-overlay (timeout 00:09:50) [common]
  203 12:40:05.988677  end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
  205 12:40:05.988992  start: 1.6.2.3.3 test-install-overlay (timeout 00:09:50) [common]
  206 12:40:05.989679  end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
  208 12:40:05.989943  start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:50) [common]
  209 12:40:05.990579  runner path: /var/lib/lava/dispatcher/tmp/10724866/lava-overlay-lh7g_n7h/lava-10724866/0/tests/0_dmesg test_uuid 10724866_1.6.2.3.1
  210 12:40:05.990734  end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
  212 12:40:05.990956  start: 1.6.2.3.5 inline-repo-action (timeout 00:09:50) [common]
  213 12:40:05.991028  Using /lava-10724866 at stage 1
  214 12:40:05.991348  uuid=10724866_1.6.2.3.5 testdef=None
  215 12:40:05.991436  end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
  216 12:40:05.991527  start: 1.6.2.3.6 test-overlay (timeout 00:09:50) [common]
  217 12:40:05.991978  end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
  219 12:40:05.992192  start: 1.6.2.3.7 test-install-overlay (timeout 00:09:50) [common]
  220 12:40:05.992835  end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
  222 12:40:05.993082  start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:50) [common]
  223 12:40:05.993737  runner path: /var/lib/lava/dispatcher/tmp/10724866/lava-overlay-lh7g_n7h/lava-10724866/1/tests/1_bootrr test_uuid 10724866_1.6.2.3.5
  224 12:40:05.993886  end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
  226 12:40:05.994090  Creating lava-test-runner.conf files
  227 12:40:05.994186  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10724866/lava-overlay-lh7g_n7h/lava-10724866/0 for stage 0
  228 12:40:05.994274  - 0_dmesg
  229 12:40:05.994350  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10724866/lava-overlay-lh7g_n7h/lava-10724866/1 for stage 1
  230 12:40:05.994438  - 1_bootrr
  231 12:40:05.994530  end: 1.6.2.3 test-definition (duration 00:00:00) [common]
  232 12:40:05.994614  start: 1.6.2.4 compress-overlay (timeout 00:09:50) [common]
  233 12:40:06.001973  end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
  234 12:40:06.002077  start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:50) [common]
  235 12:40:06.002162  end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
  236 12:40:06.002244  end: 1.6.2 lava-overlay (duration 00:00:00) [common]
  237 12:40:06.002328  start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:50) [common]
  238 12:40:06.118359  end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
  239 12:40:06.118709  start: 1.6.4 extract-modules (timeout 00:09:50) [common]
  240 12:40:06.118821  extracting modules file /var/lib/lava/dispatcher/tmp/10724866/tftp-deploy-7g8zvg_1/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10724866/extract-nfsrootfs-176kw0_e
  241 12:40:06.326900  extracting modules file /var/lib/lava/dispatcher/tmp/10724866/tftp-deploy-7g8zvg_1/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10724866/extract-overlay-ramdisk-1gk4lxbf/ramdisk
  242 12:40:06.537239  end: 1.6.4 extract-modules (duration 00:00:00) [common]
  243 12:40:06.537406  start: 1.6.5 apply-overlay-tftp (timeout 00:09:49) [common]
  244 12:40:06.537498  [common] Applying overlay to NFS
  245 12:40:06.537567  [common] Applying overlay /var/lib/lava/dispatcher/tmp/10724866/compress-overlay-ejthgve8/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10724866/extract-nfsrootfs-176kw0_e
  246 12:40:06.545317  end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
  247 12:40:06.545453  start: 1.6.6 configure-preseed-file (timeout 00:09:49) [common]
  248 12:40:06.545545  end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
  249 12:40:06.545637  start: 1.6.7 compress-ramdisk (timeout 00:09:49) [common]
  250 12:40:06.545721  Building ramdisk /var/lib/lava/dispatcher/tmp/10724866/extract-overlay-ramdisk-1gk4lxbf/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10724866/extract-overlay-ramdisk-1gk4lxbf/ramdisk
  251 12:40:06.818072  >> 117806 blocks

  252 12:40:08.795467  rename /var/lib/lava/dispatcher/tmp/10724866/extract-overlay-ramdisk-1gk4lxbf/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10724866/tftp-deploy-7g8zvg_1/ramdisk/ramdisk.cpio.gz
  253 12:40:08.795875  end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
  254 12:40:08.796002  start: 1.6.8 prepare-kernel (timeout 00:09:47) [common]
  255 12:40:08.796101  start: 1.6.8.1 prepare-fit (timeout 00:09:47) [common]
  256 12:40:08.796205  Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10724866/tftp-deploy-7g8zvg_1/kernel/Image'
  257 12:40:21.398435  Returned 0 in 12 seconds
  258 12:40:21.499017  mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10724866/tftp-deploy-7g8zvg_1/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10724866/tftp-deploy-7g8zvg_1/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10724866/tftp-deploy-7g8zvg_1/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10724866/tftp-deploy-7g8zvg_1/kernel/image.itb
  259 12:40:21.818301  output: FIT description: Kernel Image image with one or more FDT blobs
  260 12:40:21.818655  output: Created:         Wed Jun 14 13:40:21 2023
  261 12:40:21.818734  output:  Image 0 (kernel-1)
  262 12:40:21.818801  output:   Description:  
  263 12:40:21.818875  output:   Created:      Wed Jun 14 13:40:21 2023
  264 12:40:21.818937  output:   Type:         Kernel Image
  265 12:40:21.819000  output:   Compression:  lzma compressed
  266 12:40:21.819060  output:   Data Size:    10442380 Bytes = 10197.64 KiB = 9.96 MiB
  267 12:40:21.819128  output:   Architecture: AArch64
  268 12:40:21.819189  output:   OS:           Linux
  269 12:40:21.819248  output:   Load Address: 0x00000000
  270 12:40:21.819307  output:   Entry Point:  0x00000000
  271 12:40:21.819369  output:   Hash algo:    crc32
  272 12:40:21.819427  output:   Hash value:   ced21bfe
  273 12:40:21.819481  output:  Image 1 (fdt-1)
  274 12:40:21.819535  output:   Description:  mt8192-asurada-spherion-r0
  275 12:40:21.819596  output:   Created:      Wed Jun 14 13:40:21 2023
  276 12:40:21.819651  output:   Type:         Flat Device Tree
  277 12:40:21.819705  output:   Compression:  uncompressed
  278 12:40:21.819758  output:   Data Size:    46924 Bytes = 45.82 KiB = 0.04 MiB
  279 12:40:21.819818  output:   Architecture: AArch64
  280 12:40:21.819901  output:   Hash algo:    crc32
  281 12:40:21.819983  output:   Hash value:   1df858fa
  282 12:40:21.820067  output:  Image 2 (ramdisk-1)
  283 12:40:21.820151  output:   Description:  unavailable
  284 12:40:21.820233  output:   Created:      Wed Jun 14 13:40:21 2023
  285 12:40:21.820320  output:   Type:         RAMDisk Image
  286 12:40:21.820408  output:   Compression:  Unknown Compression
  287 12:40:21.820493  output:   Data Size:    17639016 Bytes = 17225.60 KiB = 16.82 MiB
  288 12:40:21.820590  output:   Architecture: AArch64
  289 12:40:21.820674  output:   OS:           Linux
  290 12:40:21.820756  output:   Load Address: unavailable
  291 12:40:21.820910  output:   Entry Point:  unavailable
  292 12:40:21.820994  output:   Hash algo:    crc32
  293 12:40:21.821081  output:   Hash value:   ba65401d
  294 12:40:21.821163  output:  Default Configuration: 'conf-1'
  295 12:40:21.821245  output:  Configuration 0 (conf-1)
  296 12:40:21.821330  output:   Description:  mt8192-asurada-spherion-r0
  297 12:40:21.821412  output:   Kernel:       kernel-1
  298 12:40:21.821493  output:   Init Ramdisk: ramdisk-1
  299 12:40:21.821582  output:   FDT:          fdt-1
  300 12:40:21.821664  output:   Loadables:    kernel-1
  301 12:40:21.821745  output: 
  302 12:40:21.821981  end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
  303 12:40:21.822114  end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
  304 12:40:21.822244  end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
  305 12:40:21.822371  start: 1.7 lxc-create-udev-rule-action (timeout 00:09:34) [common]
  306 12:40:21.822520  No LXC device requested
  307 12:40:21.822630  end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
  308 12:40:21.822745  start: 1.8 deploy-device-env (timeout 00:09:34) [common]
  309 12:40:21.822863  end: 1.8 deploy-device-env (duration 00:00:00) [common]
  310 12:40:21.822961  Checking files for TFTP limit of 4294967296 bytes.
  311 12:40:21.823614  end: 1 tftp-deploy (duration 00:00:26) [common]
  312 12:40:21.823747  start: 2 depthcharge-action (timeout 00:05:00) [common]
  313 12:40:21.823876  start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
  314 12:40:21.824046  substitutions:
  315 12:40:21.824143  - {DTB}: 10724866/tftp-deploy-7g8zvg_1/dtb/mt8192-asurada-spherion-r0.dtb
  316 12:40:21.824237  - {INITRD}: 10724866/tftp-deploy-7g8zvg_1/ramdisk/ramdisk.cpio.gz
  317 12:40:21.824327  - {KERNEL}: 10724866/tftp-deploy-7g8zvg_1/kernel/Image
  318 12:40:21.824447  - {LAVA_MAC}: None
  319 12:40:21.824532  - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10724866/extract-nfsrootfs-176kw0_e
  320 12:40:21.824607  - {NFS_SERVER_IP}: 192.168.201.1
  321 12:40:21.824663  - {PRESEED_CONFIG}: None
  322 12:40:21.824720  - {PRESEED_LOCAL}: None
  323 12:40:21.824812  - {RAMDISK}: 10724866/tftp-deploy-7g8zvg_1/ramdisk/ramdisk.cpio.gz
  324 12:40:21.824898  - {ROOT_PART}: None
  325 12:40:21.824985  - {ROOT}: None
  326 12:40:21.825071  - {SERVER_IP}: 192.168.201.1
  327 12:40:21.825154  - {TEE}: None
  328 12:40:21.825241  Parsed boot commands:
  329 12:40:21.825327  - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
  330 12:40:21.825550  Parsed boot commands: tftpboot 192.168.201.1 10724866/tftp-deploy-7g8zvg_1/kernel/image.itb 10724866/tftp-deploy-7g8zvg_1/kernel/cmdline 
  331 12:40:21.825669  end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
  332 12:40:21.825793  start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
  333 12:40:21.825917  start: 2.2.1 reset-connection (timeout 00:05:00) [common]
  334 12:40:21.826037  start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
  335 12:40:21.826135  Not connected, no need to disconnect.
  336 12:40:21.826243  end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
  337 12:40:21.826328  start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
  338 12:40:21.826399  [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-0'
  339 12:40:21.829818  Setting prompt string to ['lava-test: # ']
  340 12:40:21.830221  end: 2.2.1.2 connect-device (duration 00:00:00) [common]
  341 12:40:21.830335  end: 2.2.1 reset-connection (duration 00:00:00) [common]
  342 12:40:21.830446  start: 2.2.2 reset-device (timeout 00:05:00) [common]
  343 12:40:21.830543  start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
  344 12:40:21.830735  Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
  345 12:40:26.961415  >> Command sent successfully.

  346 12:40:26.963856  Returned 0 in 5 seconds
  347 12:40:27.064283  end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
  349 12:40:27.064735  end: 2.2.2 reset-device (duration 00:00:05) [common]
  350 12:40:27.064917  start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
  351 12:40:27.065013  Setting prompt string to 'Starting depthcharge on Spherion...'
  352 12:40:27.065090  Changing prompt to 'Starting depthcharge on Spherion...'
  353 12:40:27.065194  depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
  354 12:40:27.065578  [Enter `^Ec?' for help]

  355 12:40:27.236062  

  356 12:40:27.236258  

  357 12:40:27.236387  F0: 102B 0000

  358 12:40:27.236490  

  359 12:40:27.236608  F3: 1001 0000 [0200]

  360 12:40:27.239160  

  361 12:40:27.239304  F3: 1001 0000

  362 12:40:27.239431  

  363 12:40:27.239542  F7: 102D 0000

  364 12:40:27.239643  

  365 12:40:27.242405  F1: 0000 0000

  366 12:40:27.242513  

  367 12:40:27.242606  V0: 0000 0000 [0001]

  368 12:40:27.242715  

  369 12:40:27.245588  00: 0007 8000

  370 12:40:27.245700  

  371 12:40:27.245803  01: 0000 0000

  372 12:40:27.245903  

  373 12:40:27.249451  BP: 0C00 0209 [0000]

  374 12:40:27.249570  

  375 12:40:27.249667  G0: 1182 0000

  376 12:40:27.249772  

  377 12:40:27.252444  EC: 0000 0021 [4000]

  378 12:40:27.252553  

  379 12:40:27.252652  S7: 0000 0000 [0000]

  380 12:40:27.252756  

  381 12:40:27.256158  CC: 0000 0000 [0001]

  382 12:40:27.256264  

  383 12:40:27.256380  T0: 0000 0040 [010F]

  384 12:40:27.256489  

  385 12:40:27.256579  Jump to BL

  386 12:40:27.259920  

  387 12:40:27.282854  

  388 12:40:27.283001  

  389 12:40:27.283074  

  390 12:40:27.290447  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...

  391 12:40:27.294231  ARM64: Exception handlers installed.

  392 12:40:27.297972  ARM64: Testing exception

  393 12:40:27.301158  ARM64: Done test exception

  394 12:40:27.307751  Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000

  395 12:40:27.318226  Mapping address range [0x00000000:0x200000000) as     cacheable | read-write |     secure | device

  396 12:40:27.325251  Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000

  397 12:40:27.335135  Mapping address range [0x00100000:0x00120000) as     cacheable | read-write |     secure | normal

  398 12:40:27.341394  Backing address range [0x00000000:0x40000000) with new page table @0x0010f000

  399 12:40:27.348446  Backing address range [0x00000000:0x00200000) with new page table @0x00110000

  400 12:40:27.359663  Mapping address range [0x00200000:0x00300000) as     cacheable | read-write |     secure | normal

  401 12:40:27.366583  Backing address range [0x00200000:0x00400000) with new page table @0x00111000

  402 12:40:27.385606  Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write |     secure | normal

  403 12:40:27.389422  WDT: Last reset was cold boot

  404 12:40:27.392540  SPI1(PAD0) initialized at 2873684 Hz

  405 12:40:27.395626  SPI5(PAD0) initialized at 992727 Hz

  406 12:40:27.398892  VBOOT: Loading verstage.

  407 12:40:27.406175  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  408 12:40:27.409224  FMAP: Found "FLASH" version 1.1 at 0x20000.

  409 12:40:27.412738  FMAP: base = 0x0 size = 0x800000 #areas = 25

  410 12:40:27.415724  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

  411 12:40:27.423189  CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes

  412 12:40:27.429621  CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150

  413 12:40:27.440912  read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps

  414 12:40:27.441088  

  415 12:40:27.441163  

  416 12:40:27.451188  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...

  417 12:40:27.454449  ARM64: Exception handlers installed.

  418 12:40:27.457701  ARM64: Testing exception

  419 12:40:27.457826  ARM64: Done test exception

  420 12:40:27.464704  FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)

  421 12:40:27.468341  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  422 12:40:27.481968  Probing TPM: . done!

  423 12:40:27.482078  TPM ready after 0 ms

  424 12:40:27.489605  Connected to device vid:did:rid of 1ae0:0028:00

  425 12:40:27.496048  Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523

  426 12:40:27.556976  Initialized TPM device CR50 revision 0

  427 12:40:27.569522  tlcl_send_startup: Startup return code is 0

  428 12:40:27.569666  TPM: setup succeeded

  429 12:40:27.580579  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0

  430 12:40:27.589134  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

  431 12:40:27.604571  VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)

  432 12:40:27.611740  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

  433 12:40:27.615539  out: cmd=0xd: 03 f0 0d 00 00 00 00 00 

  434 12:40:27.619317  in-header: 03 07 00 00 08 00 00 00 

  435 12:40:27.619406  in-data: aa e4 47 04 13 02 00 00 

  436 12:40:27.623167  Chrome EC: UHEPI supported

  437 12:40:27.630442  out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 

  438 12:40:27.634242  in-header: 03 95 00 00 08 00 00 00 

  439 12:40:27.638091  in-data: 18 20 20 08 00 00 00 00 

  440 12:40:27.638185  Phase 1

  441 12:40:27.641443  FMAP: area GBB found @ 3f5000 (12032 bytes)

  442 12:40:27.648467  VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7

  443 12:40:27.652582  VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7

  444 12:40:27.656359  Recovery requested (1009000e)

  445 12:40:27.666524  TPM: Extending digest for VBOOT: boot mode into PCR 0

  446 12:40:27.671510  tlcl_extend: response is 0

  447 12:40:27.682737  TPM: Extending digest for VBOOT: GBB HWID into PCR 1

  448 12:40:27.686398  tlcl_extend: response is 0

  449 12:40:27.693728  CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c

  450 12:40:27.713096  read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps

  451 12:40:27.720356  BS: bootblock times (exec / console): total (unknown) / 149 ms

  452 12:40:27.720480  

  453 12:40:27.720548  

  454 12:40:27.729618  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...

  455 12:40:27.733631  ARM64: Exception handlers installed.

  456 12:40:27.736427  ARM64: Testing exception

  457 12:40:27.736535  ARM64: Done test exception

  458 12:40:27.758922  pmic_efuse_setting: Set efuses in 11 msecs

  459 12:40:27.762563  pmwrap_interface_init: Select PMIF_VLD_RDY

  460 12:40:27.768751  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a

  461 12:40:27.772836  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a

  462 12:40:27.776604  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a

  463 12:40:27.783579  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a

  464 12:40:27.787343  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a

  465 12:40:27.791109  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a

  466 12:40:27.798391  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a

  467 12:40:27.802179  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a

  468 12:40:27.806101  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c

  469 12:40:27.809796  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a

  470 12:40:27.816835  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a

  471 12:40:27.820765  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c

  472 12:40:27.824617  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c

  473 12:40:27.830891  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a

  474 12:40:27.838506  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a

  475 12:40:27.842315  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a

  476 12:40:27.849632  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a

  477 12:40:27.853859  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a

  478 12:40:27.860645  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a

  479 12:40:27.864790  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a

  480 12:40:27.872084  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c

  481 12:40:27.875161  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a

  482 12:40:27.882291  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a

  483 12:40:27.886174  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c

  484 12:40:27.893826  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c

  485 12:40:27.897181  [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa

  486 12:40:27.904927  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92

  487 12:40:27.908724  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2

  488 12:40:27.911907  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82

  489 12:40:27.919486  [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10

  490 12:40:27.923335  [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425

  491 12:40:27.926516  [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010

  492 12:40:27.934527  [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f

  493 12:40:27.937532  [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000

  494 12:40:27.941198  [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8

  495 12:40:27.948301  [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb

  496 12:40:27.952493  [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698

  497 12:40:27.956234  [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3

  498 12:40:27.963934  [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92

  499 12:40:27.967804  [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a

  500 12:40:27.971579  [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2

  501 12:40:27.974999  [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a

  502 12:40:27.978645  [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a

  503 12:40:27.986242  [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a

  504 12:40:27.990206  [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a

  505 12:40:27.993526  [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82

  506 12:40:27.997253  [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c

  507 12:40:28.000994  [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a

  508 12:40:28.004795  [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a

  509 12:40:28.008321  [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c

  510 12:40:28.012185  [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c

  511 12:40:28.023615  [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248

  512 12:40:28.030863  [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1

  513 12:40:28.034837  [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0

  514 12:40:28.042102  [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248

  515 12:40:28.053132  [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0

  516 12:40:28.056724  [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0

  517 12:40:28.060766  [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1

  518 12:40:28.063773  [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1

  519 12:40:28.072255  [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0

  520 12:40:28.075436  [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2

  521 12:40:28.084033  [RTC]rtc_osc_init,62: osc32con val = 0xde70

  522 12:40:28.087043  [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a

  523 12:40:28.096562  [RTC]rtc_get_frequency_meter,154: input=15, output=760

  524 12:40:28.106052  [RTC]rtc_get_frequency_meter,154: input=23, output=943

  525 12:40:28.115471  [RTC]rtc_get_frequency_meter,154: input=19, output=851

  526 12:40:28.124570  [RTC]rtc_get_frequency_meter,154: input=17, output=804

  527 12:40:28.134393  [RTC]rtc_get_frequency_meter,154: input=16, output=782

  528 12:40:28.144092  [RTC]rtc_get_frequency_meter,154: input=16, output=783

  529 12:40:28.153158  [RTC]rtc_get_frequency_meter,154: input=17, output=805

  530 12:40:28.156908  [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17

  531 12:40:28.164403  [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70

  532 12:40:28.168053  [RTC]rtc_boot_common,202: RTC_STATE_REBOOT

  533 12:40:28.172118  [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486

  534 12:40:28.175829  [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1

  535 12:40:28.179659  [RTC]rtc_bbpu_power_on,300: done BBPU=0x81

  536 12:40:28.182888  ADC[4]: Raw value=905834 ID=7

  537 12:40:28.186676  ADC[3]: Raw value=213441 ID=1

  538 12:40:28.186787  RAM Code: 0x71

  539 12:40:28.190493  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

  540 12:40:28.198275  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  541 12:40:28.205509  CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014

  542 12:40:28.212504  DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE

  543 12:40:28.216282  out: cmd=0xd: 03 f0 0d 00 00 00 00 00 

  544 12:40:28.219898  in-header: 03 07 00 00 08 00 00 00 

  545 12:40:28.219996  in-data: aa e4 47 04 13 02 00 00 

  546 12:40:28.223463  Chrome EC: UHEPI supported

  547 12:40:28.231072  out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 

  548 12:40:28.234323  in-header: 03 95 00 00 08 00 00 00 

  549 12:40:28.238163  in-data: 18 20 20 08 00 00 00 00 

  550 12:40:28.242052  MRC: failed to locate region type 0.

  551 12:40:28.249345  DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)

  552 12:40:28.253127  DRAM-K: Running full calibration

  553 12:40:28.257180  DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE

  554 12:40:28.260437  header.status = 0x0

  555 12:40:28.264209  header.version = 0x6 (expected: 0x6)

  556 12:40:28.264327  header.size = 0xd00 (expected: 0xd00)

  557 12:40:28.268201  header.flags = 0x0

  558 12:40:28.275403  CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40

  559 12:40:28.292892  read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps

  560 12:40:28.300195  dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6

  561 12:40:28.300326  dram_init: ddr_geometry: 2

  562 12:40:28.303779  [EMI] MDL number = 2

  563 12:40:28.303894  [EMI] Get MDL freq = 0

  564 12:40:28.307521  dram_init: ddr_type: 0

  565 12:40:28.311484  is_discrete_lpddr4: 1

  566 12:40:28.311603  [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0

  567 12:40:28.314728  

  568 12:40:28.314843  

  569 12:40:28.314947  [Bian_co] ETT version 0.0.0.1

  570 12:40:28.318380   dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6

  571 12:40:28.322757  

  572 12:40:28.326376  dramc_set_vcore_voltage set vcore to 650000

  573 12:40:28.326487  Read voltage for 800, 4

  574 12:40:28.326582  Vio18 = 0

  575 12:40:28.330032  Vcore = 650000

  576 12:40:28.330117  Vdram = 0

  577 12:40:28.330321  Vddq = 0

  578 12:40:28.330386  Vmddr = 0

  579 12:40:28.334164  dram_init: config_dvfs: 1

  580 12:40:28.337387  [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0

  581 12:40:28.345057  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

  582 12:40:28.349024  [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9

  583 12:40:28.352236  freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9

  584 12:40:28.356151  [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9

  585 12:40:28.360182  freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9

  586 12:40:28.363402  MEM_TYPE=3, freq_sel=18

  587 12:40:28.366628  sv_algorithm_assistance_LP4_1600 

  588 12:40:28.369667  ============ PULL DRAM RESETB DOWN ============

  589 12:40:28.373089  ========== PULL DRAM RESETB DOWN end =========

  590 12:40:28.376199  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  591 12:40:28.380084  =================================== 

  592 12:40:28.383615  LPDDR4 DRAM CONFIGURATION

  593 12:40:28.387346  =================================== 

  594 12:40:28.387486  EX_ROW_EN[0]    = 0x0

  595 12:40:28.391027  EX_ROW_EN[1]    = 0x0

  596 12:40:28.391131  LP4Y_EN      = 0x0

  597 12:40:28.394630  WORK_FSP     = 0x0

  598 12:40:28.394740  WL           = 0x2

  599 12:40:28.397908  RL           = 0x2

  600 12:40:28.398002  BL           = 0x2

  601 12:40:28.402272  RPST         = 0x0

  602 12:40:28.402441  RD_PRE       = 0x0

  603 12:40:28.405505  WR_PRE       = 0x1

  604 12:40:28.405591  WR_PST       = 0x0

  605 12:40:28.408711  DBI_WR       = 0x0

  606 12:40:28.408798  DBI_RD       = 0x0

  607 12:40:28.412437  OTF          = 0x1

  608 12:40:28.415126  =================================== 

  609 12:40:28.419003  =================================== 

  610 12:40:28.419081  ANA top config

  611 12:40:28.422136  =================================== 

  612 12:40:28.425240  DLL_ASYNC_EN            =  0

  613 12:40:28.428964  ALL_SLAVE_EN            =  1

  614 12:40:28.429044  NEW_RANK_MODE           =  1

  615 12:40:28.431906  DLL_IDLE_MODE           =  1

  616 12:40:28.435567  LP45_APHY_COMB_EN       =  1

  617 12:40:28.439147  TX_ODT_DIS              =  1

  618 12:40:28.439235  NEW_8X_MODE             =  1

  619 12:40:28.443310  =================================== 

  620 12:40:28.446499  =================================== 

  621 12:40:28.449806  data_rate                  = 1600

  622 12:40:28.452959  CKR                        = 1

  623 12:40:28.456223  DQ_P2S_RATIO               = 8

  624 12:40:28.459538  =================================== 

  625 12:40:28.462733  CA_P2S_RATIO               = 8

  626 12:40:28.462821  DQ_CA_OPEN                 = 0

  627 12:40:28.466568  DQ_SEMI_OPEN               = 0

  628 12:40:28.469678  CA_SEMI_OPEN               = 0

  629 12:40:28.472920  CA_FULL_RATE               = 0

  630 12:40:28.476156  DQ_CKDIV4_EN               = 1

  631 12:40:28.480012  CA_CKDIV4_EN               = 1

  632 12:40:28.480095  CA_PREDIV_EN               = 0

  633 12:40:28.483089  PH8_DLY                    = 0

  634 12:40:28.486130  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

  635 12:40:28.489925  DQ_AAMCK_DIV               = 4

  636 12:40:28.492918  CA_AAMCK_DIV               = 4

  637 12:40:28.496567  CA_ADMCK_DIV               = 4

  638 12:40:28.496689  DQ_TRACK_CA_EN             = 0

  639 12:40:28.499913  CA_PICK                    = 800

  640 12:40:28.503668  CA_MCKIO                   = 800

  641 12:40:28.506862  MCKIO_SEMI                 = 0

  642 12:40:28.510785  PLL_FREQ                   = 3068

  643 12:40:28.510904  DQ_UI_PI_RATIO             = 32

  644 12:40:28.514609  CA_UI_PI_RATIO             = 0

  645 12:40:28.517608  =================================== 

  646 12:40:28.522038  =================================== 

  647 12:40:28.525225  memory_type:LPDDR4         

  648 12:40:28.525313  GP_NUM     : 10       

  649 12:40:28.529074  SRAM_EN    : 1       

  650 12:40:28.529158  MD32_EN    : 0       

  651 12:40:28.532345  =================================== 

  652 12:40:28.535983  [ANA_INIT] >>>>>>>>>>>>>> 

  653 12:40:28.539612  <<<<<< [CONFIGURE PHASE]: ANA_TX

  654 12:40:28.543269  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

  655 12:40:28.546878  =================================== 

  656 12:40:28.546962  data_rate = 1600,PCW = 0X7600

  657 12:40:28.549846  =================================== 

  658 12:40:28.553030  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

  659 12:40:28.560206  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

  660 12:40:28.566698  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

  661 12:40:28.569967  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

  662 12:40:28.573147  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

  663 12:40:28.577012  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

  664 12:40:28.580059  [ANA_INIT] flow start 

  665 12:40:28.580131  [ANA_INIT] PLL >>>>>>>> 

  666 12:40:28.583258  [ANA_INIT] PLL <<<<<<<< 

  667 12:40:28.586963  [ANA_INIT] MIDPI >>>>>>>> 

  668 12:40:28.590088  [ANA_INIT] MIDPI <<<<<<<< 

  669 12:40:28.590179  [ANA_INIT] DLL >>>>>>>> 

  670 12:40:28.593480  [ANA_INIT] flow end 

  671 12:40:28.596778  ============ LP4 DIFF to SE enter ============

  672 12:40:28.600394  ============ LP4 DIFF to SE exit  ============

  673 12:40:28.603367  [ANA_INIT] <<<<<<<<<<<<< 

  674 12:40:28.607070  [Flow] Enable top DCM control >>>>> 

  675 12:40:28.610109  [Flow] Enable top DCM control <<<<< 

  676 12:40:28.613851  Enable DLL master slave shuffle 

  677 12:40:28.617149  ============================================================== 

  678 12:40:28.620283  Gating Mode config

  679 12:40:28.627074  ============================================================== 

  680 12:40:28.627163  Config description: 

  681 12:40:28.636621  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

  682 12:40:28.643520  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

  683 12:40:28.646769  SELPH_MODE            0: By rank         1: By Phase 

  684 12:40:28.653832  ============================================================== 

  685 12:40:28.656637  GAT_TRACK_EN                 =  1

  686 12:40:28.660205  RX_GATING_MODE               =  2

  687 12:40:28.663375  RX_GATING_TRACK_MODE         =  2

  688 12:40:28.666674  SELPH_MODE                   =  1

  689 12:40:28.670528  PICG_EARLY_EN                =  1

  690 12:40:28.673825  VALID_LAT_VALUE              =  1

  691 12:40:28.676715  ============================================================== 

  692 12:40:28.680414  Enter into Gating configuration >>>> 

  693 12:40:28.683403  Exit from Gating configuration <<<< 

  694 12:40:28.687148  Enter into  DVFS_PRE_config >>>>> 

  695 12:40:28.697050  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

  696 12:40:28.700597  Exit from  DVFS_PRE_config <<<<< 

  697 12:40:28.703630  Enter into PICG configuration >>>> 

  698 12:40:28.707294  Exit from PICG configuration <<<< 

  699 12:40:28.710126  [RX_INPUT] configuration >>>>> 

  700 12:40:28.713521  [RX_INPUT] configuration <<<<< 

  701 12:40:28.717236  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

  702 12:40:28.723857  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

  703 12:40:28.730825  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

  704 12:40:28.737267  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

  705 12:40:28.744136  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

  706 12:40:28.747479  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

  707 12:40:28.754043  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

  708 12:40:28.757669  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

  709 12:40:28.760555  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

  710 12:40:28.764284  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

  711 12:40:28.770874  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

  712 12:40:28.774076  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  713 12:40:28.777357  =================================== 

  714 12:40:28.780475  LPDDR4 DRAM CONFIGURATION

  715 12:40:28.783796  =================================== 

  716 12:40:28.783882  EX_ROW_EN[0]    = 0x0

  717 12:40:28.787686  EX_ROW_EN[1]    = 0x0

  718 12:40:28.787769  LP4Y_EN      = 0x0

  719 12:40:28.790784  WORK_FSP     = 0x0

  720 12:40:28.790868  WL           = 0x2

  721 12:40:28.794000  RL           = 0x2

  722 12:40:28.794083  BL           = 0x2

  723 12:40:28.797825  RPST         = 0x0

  724 12:40:28.797909  RD_PRE       = 0x0

  725 12:40:28.801126  WR_PRE       = 0x1

  726 12:40:28.801209  WR_PST       = 0x0

  727 12:40:28.804025  DBI_WR       = 0x0

  728 12:40:28.804139  DBI_RD       = 0x0

  729 12:40:28.807995  OTF          = 0x1

  730 12:40:28.810936  =================================== 

  731 12:40:28.814038  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

  732 12:40:28.817548  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

  733 12:40:28.824290  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  734 12:40:28.827230  =================================== 

  735 12:40:28.827332  LPDDR4 DRAM CONFIGURATION

  736 12:40:28.831025  =================================== 

  737 12:40:28.834599  EX_ROW_EN[0]    = 0x10

  738 12:40:28.837691  EX_ROW_EN[1]    = 0x0

  739 12:40:28.837774  LP4Y_EN      = 0x0

  740 12:40:28.840833  WORK_FSP     = 0x0

  741 12:40:28.840931  WL           = 0x2

  742 12:40:28.844124  RL           = 0x2

  743 12:40:28.844207  BL           = 0x2

  744 12:40:28.847913  RPST         = 0x0

  745 12:40:28.847998  RD_PRE       = 0x0

  746 12:40:28.851256  WR_PRE       = 0x1

  747 12:40:28.851339  WR_PST       = 0x0

  748 12:40:28.854434  DBI_WR       = 0x0

  749 12:40:28.854517  DBI_RD       = 0x0

  750 12:40:28.857723  OTF          = 0x1

  751 12:40:28.860945  =================================== 

  752 12:40:28.864586  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

  753 12:40:28.869859  nWR fixed to 40

  754 12:40:28.873544  [ModeRegInit_LP4] CH0 RK0

  755 12:40:28.873627  [ModeRegInit_LP4] CH0 RK1

  756 12:40:28.877162  [ModeRegInit_LP4] CH1 RK0

  757 12:40:28.880362  [ModeRegInit_LP4] CH1 RK1

  758 12:40:28.880446  match AC timing 13

  759 12:40:28.886668  dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1

  760 12:40:28.890030  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

  761 12:40:28.893826  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

  762 12:40:28.900144  [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17

  763 12:40:28.903390  [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)

  764 12:40:28.903476  [EMI DOE] emi_dcm 0

  765 12:40:28.910524  [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600

  766 12:40:28.910636  ==

  767 12:40:28.913783  Dram Type= 6, Freq= 0, CH_0, rank 0

  768 12:40:28.917119  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  769 12:40:28.917221  ==

  770 12:40:28.923645  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

  771 12:40:28.926816  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

  772 12:40:28.937352  [CA 0] Center 36 (6~67) winsize 62

  773 12:40:28.940525  [CA 1] Center 36 (6~67) winsize 62

  774 12:40:28.944108  [CA 2] Center 34 (4~65) winsize 62

  775 12:40:28.947310  [CA 3] Center 33 (3~64) winsize 62

  776 12:40:28.951141  [CA 4] Center 33 (3~64) winsize 62

  777 12:40:28.954356  [CA 5] Center 32 (2~62) winsize 61

  778 12:40:28.954441  

  779 12:40:28.957470  [CmdBusTrainingLP45] Vref(ca) range 1: 34

  780 12:40:28.957554  

  781 12:40:28.961298  [CATrainingPosCal] consider 1 rank data

  782 12:40:28.963985  u2DelayCellTimex100 = 270/100 ps

  783 12:40:28.967866  CA0 delay=36 (6~67),Diff = 4 PI (28 cell)

  784 12:40:28.971024  CA1 delay=36 (6~67),Diff = 4 PI (28 cell)

  785 12:40:28.977610  CA2 delay=34 (4~65),Diff = 2 PI (14 cell)

  786 12:40:28.981212  CA3 delay=33 (3~64),Diff = 1 PI (7 cell)

  787 12:40:28.984295  CA4 delay=33 (3~64),Diff = 1 PI (7 cell)

  788 12:40:28.987806  CA5 delay=32 (2~62),Diff = 0 PI (0 cell)

  789 12:40:28.987890  

  790 12:40:28.991014  CA PerBit enable=1, Macro0, CA PI delay=32

  791 12:40:28.991098  

  792 12:40:28.994884  [CBTSetCACLKResult] CA Dly = 32

  793 12:40:28.994968  CS Dly: 4 (0~35)

  794 12:40:28.995036  ==

  795 12:40:28.997712  Dram Type= 6, Freq= 0, CH_0, rank 1

  796 12:40:29.004623  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  797 12:40:29.004709  ==

  798 12:40:29.007907  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

  799 12:40:29.014263  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

  800 12:40:29.023931  [CA 0] Center 36 (6~67) winsize 62

  801 12:40:29.027351  [CA 1] Center 36 (6~67) winsize 62

  802 12:40:29.030181  [CA 2] Center 34 (4~65) winsize 62

  803 12:40:29.033865  [CA 3] Center 34 (3~65) winsize 63

  804 12:40:29.036750  [CA 4] Center 33 (3~64) winsize 62

  805 12:40:29.040421  [CA 5] Center 32 (2~63) winsize 62

  806 12:40:29.040505  

  807 12:40:29.044273  [CmdBusTrainingLP45] Vref(ca) range 1: 34

  808 12:40:29.044357  

  809 12:40:29.047299  [CATrainingPosCal] consider 2 rank data

  810 12:40:29.050456  u2DelayCellTimex100 = 270/100 ps

  811 12:40:29.053732  CA0 delay=36 (6~67),Diff = 4 PI (28 cell)

  812 12:40:29.056920  CA1 delay=36 (6~67),Diff = 4 PI (28 cell)

  813 12:40:29.063948  CA2 delay=34 (4~65),Diff = 2 PI (14 cell)

  814 12:40:29.067122  CA3 delay=33 (3~64),Diff = 1 PI (7 cell)

  815 12:40:29.070429  CA4 delay=33 (3~64),Diff = 1 PI (7 cell)

  816 12:40:29.073781  CA5 delay=32 (2~62),Diff = 0 PI (0 cell)

  817 12:40:29.073857  

  818 12:40:29.077070  CA PerBit enable=1, Macro0, CA PI delay=32

  819 12:40:29.077145  

  820 12:40:29.080750  [CBTSetCACLKResult] CA Dly = 32

  821 12:40:29.080872  CS Dly: 4 (0~36)

  822 12:40:29.080937  

  823 12:40:29.083877  ----->DramcWriteLeveling(PI) begin...

  824 12:40:29.083953  ==

  825 12:40:29.087983  Dram Type= 6, Freq= 0, CH_0, rank 0

  826 12:40:29.091033  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  827 12:40:29.095028  ==

  828 12:40:29.095112  Write leveling (Byte 0): 33 => 33

  829 12:40:29.099016  Write leveling (Byte 1): 30 => 30

  830 12:40:29.102902  DramcWriteLeveling(PI) end<-----

  831 12:40:29.102988  

  832 12:40:29.103055  ==

  833 12:40:29.105864  Dram Type= 6, Freq= 0, CH_0, rank 0

  834 12:40:29.109216  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  835 12:40:29.109300  ==

  836 12:40:29.113066  [Gating] SW mode calibration

  837 12:40:29.120662  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

  838 12:40:29.124168  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

  839 12:40:29.130289   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

  840 12:40:29.133998   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)

  841 12:40:29.136888   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)

  842 12:40:29.143960   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

  843 12:40:29.147256   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  844 12:40:29.150702   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  845 12:40:29.157177   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  846 12:40:29.160355   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  847 12:40:29.163514   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  848 12:40:29.170541   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  849 12:40:29.173892   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  850 12:40:29.176934   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  851 12:40:29.183470   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  852 12:40:29.187087   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  853 12:40:29.190351   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  854 12:40:29.196866   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  855 12:40:29.200731   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  856 12:40:29.203795   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)

  857 12:40:29.207666   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)

  858 12:40:29.213784   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  859 12:40:29.216936   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  860 12:40:29.220657   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  861 12:40:29.227091   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  862 12:40:29.230396   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  863 12:40:29.234286   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  864 12:40:29.240514   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)

  865 12:40:29.244354   0  9  8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)

  866 12:40:29.247249   0  9 12 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)

  867 12:40:29.253876   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  868 12:40:29.257682   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  869 12:40:29.260748   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  870 12:40:29.267492   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  871 12:40:29.270459   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  872 12:40:29.274354   0 10  4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)

  873 12:40:29.277592   0 10  8 | B1->B0 | 3333 2525 | 1 0 | (1 1) (0 0)

  874 12:40:29.284235   0 10 12 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)

  875 12:40:29.287377   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  876 12:40:29.290585   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  877 12:40:29.297585   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  878 12:40:29.300732   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  879 12:40:29.303755   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  880 12:40:29.310842   0 11  4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

  881 12:40:29.313830   0 11  8 | B1->B0 | 2d2d 4545 | 0 0 | (1 1) (0 0)

  882 12:40:29.317462   0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)

  883 12:40:29.324550   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  884 12:40:29.327402   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  885 12:40:29.330756   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  886 12:40:29.337856   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  887 12:40:29.340818   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  888 12:40:29.344026   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

  889 12:40:29.351097   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

  890 12:40:29.354003   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  891 12:40:29.357506   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  892 12:40:29.361238   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  893 12:40:29.367753   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  894 12:40:29.370769   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  895 12:40:29.374301   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  896 12:40:29.380615   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  897 12:40:29.384617   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  898 12:40:29.387925   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  899 12:40:29.394313   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  900 12:40:29.397443   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  901 12:40:29.401273   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  902 12:40:29.407920   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  903 12:40:29.410799   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  904 12:40:29.414382   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

  905 12:40:29.420981   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

  906 12:40:29.421066  Total UI for P1: 0, mck2ui 16

  907 12:40:29.427693  best dqsien dly found for B0: ( 0, 14,  4)

  908 12:40:29.430856   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

  909 12:40:29.434623   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  910 12:40:29.437798  Total UI for P1: 0, mck2ui 16

  911 12:40:29.441617  best dqsien dly found for B1: ( 0, 14, 10)

  912 12:40:29.445392  best DQS0 dly(MCK, UI, PI) = (0, 14, 4)

  913 12:40:29.448738  best DQS1 dly(MCK, UI, PI) = (0, 14, 10)

  914 12:40:29.448910  

  915 12:40:29.452021  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)

  916 12:40:29.455242  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)

  917 12:40:29.458456  [Gating] SW calibration Done

  918 12:40:29.458566  ==

  919 12:40:29.462311  Dram Type= 6, Freq= 0, CH_0, rank 0

  920 12:40:29.465284  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  921 12:40:29.465367  ==

  922 12:40:29.468447  RX Vref Scan: 0

  923 12:40:29.468529  

  924 12:40:29.472061  RX Vref 0 -> 0, step: 1

  925 12:40:29.472170  

  926 12:40:29.472268  RX Delay -130 -> 252, step: 16

  927 12:40:29.478641  iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240

  928 12:40:29.482315  iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224

  929 12:40:29.485559  iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240

  930 12:40:29.488757  iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240

  931 12:40:29.491948  iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224

  932 12:40:29.498872  iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224

  933 12:40:29.501962  iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224

  934 12:40:29.505878  iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240

  935 12:40:29.509180  iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224

  936 12:40:29.512325  iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240

  937 12:40:29.515644  iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224

  938 12:40:29.522441  iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224

  939 12:40:29.525387  iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240

  940 12:40:29.528938  iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240

  941 12:40:29.532498  iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240

  942 12:40:29.539321  iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240

  943 12:40:29.539406  ==

  944 12:40:29.542457  Dram Type= 6, Freq= 0, CH_0, rank 0

  945 12:40:29.545701  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  946 12:40:29.545785  ==

  947 12:40:29.545851  DQS Delay:

  948 12:40:29.548723  DQS0 = 0, DQS1 = 0

  949 12:40:29.548866  DQM Delay:

  950 12:40:29.551898  DQM0 = 89, DQM1 = 80

  951 12:40:29.552006  DQ Delay:

  952 12:40:29.555925  DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85

  953 12:40:29.558993  DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101

  954 12:40:29.562149  DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77

  955 12:40:29.565381  DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85

  956 12:40:29.565464  

  957 12:40:29.565530  

  958 12:40:29.565591  ==

  959 12:40:29.569153  Dram Type= 6, Freq= 0, CH_0, rank 0

  960 12:40:29.572070  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  961 12:40:29.572158  ==

  962 12:40:29.572223  

  963 12:40:29.572284  

  964 12:40:29.575810  	TX Vref Scan disable

  965 12:40:29.578730   == TX Byte 0 ==

  966 12:40:29.581842  Update DQ  dly =584 (2 ,1, 40)  DQ  OEN =(1 ,6)

  967 12:40:29.585499  Update DQM dly =584 (2 ,1, 40)  DQM OEN =(1 ,6)

  968 12:40:29.588562   == TX Byte 1 ==

  969 12:40:29.592363  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

  970 12:40:29.595556  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

  971 12:40:29.595641  ==

  972 12:40:29.598941  Dram Type= 6, Freq= 0, CH_0, rank 0

  973 12:40:29.605207  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  974 12:40:29.605297  ==

  975 12:40:29.617625  TX Vref=22, minBit 4, minWin=27, winSum=446

  976 12:40:29.621036  TX Vref=24, minBit 8, minWin=27, winSum=452

  977 12:40:29.624076  TX Vref=26, minBit 4, minWin=28, winSum=455

  978 12:40:29.627227  TX Vref=28, minBit 4, minWin=28, winSum=455

  979 12:40:29.631112  TX Vref=30, minBit 9, minWin=27, winSum=453

  980 12:40:29.633983  TX Vref=32, minBit 8, minWin=27, winSum=453

  981 12:40:29.640935  [TxChooseVref] Worse bit 4, Min win 28, Win sum 455, Final Vref 26

  982 12:40:29.641014  

  983 12:40:29.643926  Final TX Range 1 Vref 26

  984 12:40:29.644005  

  985 12:40:29.644069  ==

  986 12:40:29.647709  Dram Type= 6, Freq= 0, CH_0, rank 0

  987 12:40:29.650596  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  988 12:40:29.650674  ==

  989 12:40:29.650736  

  990 12:40:29.650797  

  991 12:40:29.654471  	TX Vref Scan disable

  992 12:40:29.657606   == TX Byte 0 ==

  993 12:40:29.660724  Update DQ  dly =584 (2 ,1, 40)  DQ  OEN =(1 ,6)

  994 12:40:29.663993  Update DQM dly =584 (2 ,1, 40)  DQM OEN =(1 ,6)

  995 12:40:29.667284   == TX Byte 1 ==

  996 12:40:29.670508  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

  997 12:40:29.673768  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

  998 12:40:29.677403  

  999 12:40:29.677475  [DATLAT]

 1000 12:40:29.677536  Freq=800, CH0 RK0

 1001 12:40:29.677596  

 1002 12:40:29.680527  DATLAT Default: 0xa

 1003 12:40:29.680596  0, 0xFFFF, sum = 0

 1004 12:40:29.684201  1, 0xFFFF, sum = 0

 1005 12:40:29.684277  2, 0xFFFF, sum = 0

 1006 12:40:29.687053  3, 0xFFFF, sum = 0

 1007 12:40:29.687125  4, 0xFFFF, sum = 0

 1008 12:40:29.690732  5, 0xFFFF, sum = 0

 1009 12:40:29.690808  6, 0xFFFF, sum = 0

 1010 12:40:29.693891  7, 0xFFFF, sum = 0

 1011 12:40:29.696988  8, 0xFFFF, sum = 0

 1012 12:40:29.697091  9, 0x0, sum = 1

 1013 12:40:29.697189  10, 0x0, sum = 2

 1014 12:40:29.700763  11, 0x0, sum = 3

 1015 12:40:29.700866  12, 0x0, sum = 4

 1016 12:40:29.704114  best_step = 10

 1017 12:40:29.704189  

 1018 12:40:29.704251  ==

 1019 12:40:29.707758  Dram Type= 6, Freq= 0, CH_0, rank 0

 1020 12:40:29.710947  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1021 12:40:29.711025  ==

 1022 12:40:29.714094  RX Vref Scan: 1

 1023 12:40:29.714165  

 1024 12:40:29.714226  Set Vref Range= 32 -> 127

 1025 12:40:29.714293  

 1026 12:40:29.717448  RX Vref 32 -> 127, step: 1

 1027 12:40:29.717523  

 1028 12:40:29.720687  RX Delay -95 -> 252, step: 8

 1029 12:40:29.720779  

 1030 12:40:29.723920  Set Vref, RX VrefLevel [Byte0]: 32

 1031 12:40:29.727902                           [Byte1]: 32

 1032 12:40:29.727973  

 1033 12:40:29.731191  Set Vref, RX VrefLevel [Byte0]: 33

 1034 12:40:29.734213                           [Byte1]: 33

 1035 12:40:29.737459  

 1036 12:40:29.737532  Set Vref, RX VrefLevel [Byte0]: 34

 1037 12:40:29.740603                           [Byte1]: 34

 1038 12:40:29.745472  

 1039 12:40:29.745543  Set Vref, RX VrefLevel [Byte0]: 35

 1040 12:40:29.748518                           [Byte1]: 35

 1041 12:40:29.752974  

 1042 12:40:29.753049  Set Vref, RX VrefLevel [Byte0]: 36

 1043 12:40:29.756015                           [Byte1]: 36

 1044 12:40:29.760199  

 1045 12:40:29.760277  Set Vref, RX VrefLevel [Byte0]: 37

 1046 12:40:29.763917                           [Byte1]: 37

 1047 12:40:29.768335  

 1048 12:40:29.768423  Set Vref, RX VrefLevel [Byte0]: 38

 1049 12:40:29.771499                           [Byte1]: 38

 1050 12:40:29.776084  

 1051 12:40:29.776161  Set Vref, RX VrefLevel [Byte0]: 39

 1052 12:40:29.779338                           [Byte1]: 39

 1053 12:40:29.782871  

 1054 12:40:29.782944  Set Vref, RX VrefLevel [Byte0]: 40

 1055 12:40:29.786656                           [Byte1]: 40

 1056 12:40:29.790955  

 1057 12:40:29.791033  Set Vref, RX VrefLevel [Byte0]: 41

 1058 12:40:29.793805                           [Byte1]: 41

 1059 12:40:29.798131  

 1060 12:40:29.798210  Set Vref, RX VrefLevel [Byte0]: 42

 1061 12:40:29.801733                           [Byte1]: 42

 1062 12:40:29.805649  

 1063 12:40:29.805727  Set Vref, RX VrefLevel [Byte0]: 43

 1064 12:40:29.808885                           [Byte1]: 43

 1065 12:40:29.813385  

 1066 12:40:29.813463  Set Vref, RX VrefLevel [Byte0]: 44

 1067 12:40:29.817094                           [Byte1]: 44

 1068 12:40:29.821172  

 1069 12:40:29.821246  Set Vref, RX VrefLevel [Byte0]: 45

 1070 12:40:29.824433                           [Byte1]: 45

 1071 12:40:29.828907  

 1072 12:40:29.828984  Set Vref, RX VrefLevel [Byte0]: 46

 1073 12:40:29.832107                           [Byte1]: 46

 1074 12:40:29.836460  

 1075 12:40:29.836531  Set Vref, RX VrefLevel [Byte0]: 47

 1076 12:40:29.839587                           [Byte1]: 47

 1077 12:40:29.844103  

 1078 12:40:29.844177  Set Vref, RX VrefLevel [Byte0]: 48

 1079 12:40:29.847153                           [Byte1]: 48

 1080 12:40:29.851741  

 1081 12:40:29.851825  Set Vref, RX VrefLevel [Byte0]: 49

 1082 12:40:29.854635                           [Byte1]: 49

 1083 12:40:29.859135  

 1084 12:40:29.859239  Set Vref, RX VrefLevel [Byte0]: 50

 1085 12:40:29.862533                           [Byte1]: 50

 1086 12:40:29.867191  

 1087 12:40:29.867265  Set Vref, RX VrefLevel [Byte0]: 51

 1088 12:40:29.869858                           [Byte1]: 51

 1089 12:40:29.874238  

 1090 12:40:29.874313  Set Vref, RX VrefLevel [Byte0]: 52

 1091 12:40:29.877487                           [Byte1]: 52

 1092 12:40:29.881984  

 1093 12:40:29.882057  Set Vref, RX VrefLevel [Byte0]: 53

 1094 12:40:29.885372                           [Byte1]: 53

 1095 12:40:29.889671  

 1096 12:40:29.889745  Set Vref, RX VrefLevel [Byte0]: 54

 1097 12:40:29.892726                           [Byte1]: 54

 1098 12:40:29.896906  

 1099 12:40:29.897021  Set Vref, RX VrefLevel [Byte0]: 55

 1100 12:40:29.900499                           [Byte1]: 55

 1101 12:40:29.904720  

 1102 12:40:29.904797  Set Vref, RX VrefLevel [Byte0]: 56

 1103 12:40:29.908292                           [Byte1]: 56

 1104 12:40:29.912073  

 1105 12:40:29.912145  Set Vref, RX VrefLevel [Byte0]: 57

 1106 12:40:29.916039                           [Byte1]: 57

 1107 12:40:29.920236  

 1108 12:40:29.920310  Set Vref, RX VrefLevel [Byte0]: 58

 1109 12:40:29.923479                           [Byte1]: 58

 1110 12:40:29.927349  

 1111 12:40:29.927424  Set Vref, RX VrefLevel [Byte0]: 59

 1112 12:40:29.930575                           [Byte1]: 59

 1113 12:40:29.935482  

 1114 12:40:29.935575  Set Vref, RX VrefLevel [Byte0]: 60

 1115 12:40:29.938418                           [Byte1]: 60

 1116 12:40:29.942978  

 1117 12:40:29.943054  Set Vref, RX VrefLevel [Byte0]: 61

 1118 12:40:29.946181                           [Byte1]: 61

 1119 12:40:29.950043  

 1120 12:40:29.950114  Set Vref, RX VrefLevel [Byte0]: 62

 1121 12:40:29.953711                           [Byte1]: 62

 1122 12:40:29.957970  

 1123 12:40:29.958049  Set Vref, RX VrefLevel [Byte0]: 63

 1124 12:40:29.960987                           [Byte1]: 63

 1125 12:40:29.965715  

 1126 12:40:29.965788  Set Vref, RX VrefLevel [Byte0]: 64

 1127 12:40:29.968905                           [Byte1]: 64

 1128 12:40:29.973189  

 1129 12:40:29.973262  Set Vref, RX VrefLevel [Byte0]: 65

 1130 12:40:29.976169                           [Byte1]: 65

 1131 12:40:29.980592  

 1132 12:40:29.980668  Set Vref, RX VrefLevel [Byte0]: 66

 1133 12:40:29.983763                           [Byte1]: 66

 1134 12:40:29.988516  

 1135 12:40:29.988587  Set Vref, RX VrefLevel [Byte0]: 67

 1136 12:40:29.991484                           [Byte1]: 67

 1137 12:40:29.996017  

 1138 12:40:29.996090  Set Vref, RX VrefLevel [Byte0]: 68

 1139 12:40:29.999168                           [Byte1]: 68

 1140 12:40:30.003212  

 1141 12:40:30.003292  Set Vref, RX VrefLevel [Byte0]: 69

 1142 12:40:30.006898                           [Byte1]: 69

 1143 12:40:30.011106  

 1144 12:40:30.011222  Set Vref, RX VrefLevel [Byte0]: 70

 1145 12:40:30.014607                           [Byte1]: 70

 1146 12:40:30.018863  

 1147 12:40:30.018957  Set Vref, RX VrefLevel [Byte0]: 71

 1148 12:40:30.021883                           [Byte1]: 71

 1149 12:40:30.026104  

 1150 12:40:30.026193  Set Vref, RX VrefLevel [Byte0]: 72

 1151 12:40:30.029330                           [Byte1]: 72

 1152 12:40:30.033932  

 1153 12:40:30.034027  Set Vref, RX VrefLevel [Byte0]: 73

 1154 12:40:30.037208                           [Byte1]: 73

 1155 12:40:30.041805  

 1156 12:40:30.041896  Set Vref, RX VrefLevel [Byte0]: 74

 1157 12:40:30.044843                           [Byte1]: 74

 1158 12:40:30.049406  

 1159 12:40:30.049476  Set Vref, RX VrefLevel [Byte0]: 75

 1160 12:40:30.052643                           [Byte1]: 75

 1161 12:40:30.057123  

 1162 12:40:30.057196  Set Vref, RX VrefLevel [Byte0]: 76

 1163 12:40:30.060095                           [Byte1]: 76

 1164 12:40:30.064410  

 1165 12:40:30.064477  Final RX Vref Byte 0 = 61 to rank0

 1166 12:40:30.067538  Final RX Vref Byte 1 = 60 to rank0

 1167 12:40:30.071052  Final RX Vref Byte 0 = 61 to rank1

 1168 12:40:30.074198  Final RX Vref Byte 1 = 60 to rank1==

 1169 12:40:30.077903  Dram Type= 6, Freq= 0, CH_0, rank 0

 1170 12:40:30.084033  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1171 12:40:30.084106  ==

 1172 12:40:30.084170  DQS Delay:

 1173 12:40:30.084228  DQS0 = 0, DQS1 = 0

 1174 12:40:30.087825  DQM Delay:

 1175 12:40:30.087894  DQM0 = 92, DQM1 = 86

 1176 12:40:30.091087  DQ Delay:

 1177 12:40:30.094441  DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88

 1178 12:40:30.094517  DQ4 =96, DQ5 =80, DQ6 =96, DQ7 =100

 1179 12:40:30.097624  DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =80

 1180 12:40:30.101030  DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92

 1181 12:40:30.104195  

 1182 12:40:30.104269  

 1183 12:40:30.110925  [DQSOSCAuto] RK0, (LSB)MR18= 0x4c42, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps

 1184 12:40:30.114446  CH0 RK0: MR19=606, MR18=4C42

 1185 12:40:30.120987  CH0_RK0: MR19=0x606, MR18=0x4C42, DQSOSC=390, MR23=63, INC=97, DEC=64

 1186 12:40:30.121094  

 1187 12:40:30.124595  ----->DramcWriteLeveling(PI) begin...

 1188 12:40:30.124710  ==

 1189 12:40:30.127621  Dram Type= 6, Freq= 0, CH_0, rank 1

 1190 12:40:30.130743  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1191 12:40:30.130821  ==

 1192 12:40:30.134339  Write leveling (Byte 0): 34 => 34

 1193 12:40:30.137950  Write leveling (Byte 1): 31 => 31

 1194 12:40:30.141023  DramcWriteLeveling(PI) end<-----

 1195 12:40:30.141097  

 1196 12:40:30.141161  ==

 1197 12:40:30.144249  Dram Type= 6, Freq= 0, CH_0, rank 1

 1198 12:40:30.147493  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1199 12:40:30.147574  ==

 1200 12:40:30.150807  [Gating] SW mode calibration

 1201 12:40:30.157769  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1202 12:40:30.201590  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1203 12:40:30.201956   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1204 12:40:30.202067   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)

 1205 12:40:30.202191   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)

 1206 12:40:30.202298   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1207 12:40:30.202404   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1208 12:40:30.202498   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1209 12:40:30.202584   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1210 12:40:30.202683   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1211 12:40:30.202779   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1212 12:40:30.246357   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1213 12:40:30.246687   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1214 12:40:30.246808   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1215 12:40:30.246916   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1216 12:40:30.247058   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1217 12:40:30.247160   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1218 12:40:30.247249   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1219 12:40:30.247755   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1220 12:40:30.248582   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1221 12:40:30.248688   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1222 12:40:30.272742   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1223 12:40:30.273061   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1224 12:40:30.273148   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1225 12:40:30.273227   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1226 12:40:30.273292   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1227 12:40:30.276268   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1228 12:40:30.280026   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1229 12:40:30.282945   0  9  8 | B1->B0 | 2e2e 3030 | 1 0 | (0 0) (0 0)

 1230 12:40:30.286515   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1231 12:40:30.290061   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1232 12:40:30.296927   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1233 12:40:30.300118   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1234 12:40:30.303430   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1235 12:40:30.309958   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1236 12:40:30.313043   0 10  4 | B1->B0 | 3333 3333 | 1 1 | (1 1) (1 1)

 1237 12:40:30.316761   0 10  8 | B1->B0 | 2b2b 2b2b | 0 0 | (1 0) (0 0)

 1238 12:40:30.323229   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1239 12:40:30.326333   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1240 12:40:30.329831   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1241 12:40:30.333769   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1242 12:40:30.337503   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1243 12:40:30.345504   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1244 12:40:30.348696   0 11  4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)

 1245 12:40:30.351816   0 11  8 | B1->B0 | 3e3e 4545 | 0 0 | (0 0) (0 0)

 1246 12:40:30.355386   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1247 12:40:30.362976   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1248 12:40:30.366233   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1249 12:40:30.369454   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1250 12:40:30.372752   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1251 12:40:30.379120   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1252 12:40:30.382706   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 1253 12:40:30.385731   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 1254 12:40:30.392825   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1255 12:40:30.396028   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1256 12:40:30.399496   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1257 12:40:30.406455   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1258 12:40:30.409768   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1259 12:40:30.412984   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1260 12:40:30.419286   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1261 12:40:30.422576   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1262 12:40:30.425877   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1263 12:40:30.432945   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1264 12:40:30.436016   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1265 12:40:30.439656   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1266 12:40:30.446238   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1267 12:40:30.449432   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1268 12:40:30.452579   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1269 12:40:30.455947   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 1270 12:40:30.462502   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1271 12:40:30.466298  Total UI for P1: 0, mck2ui 16

 1272 12:40:30.469243  best dqsien dly found for B0: ( 0, 14,  8)

 1273 12:40:30.472578  Total UI for P1: 0, mck2ui 16

 1274 12:40:30.476376  best dqsien dly found for B1: ( 0, 14, 10)

 1275 12:40:30.479656  best DQS0 dly(MCK, UI, PI) = (0, 14, 8)

 1276 12:40:30.482732  best DQS1 dly(MCK, UI, PI) = (0, 14, 10)

 1277 12:40:30.482847  

 1278 12:40:30.486516  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)

 1279 12:40:30.489505  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)

 1280 12:40:30.493118  [Gating] SW calibration Done

 1281 12:40:30.493200  ==

 1282 12:40:30.496178  Dram Type= 6, Freq= 0, CH_0, rank 1

 1283 12:40:30.499876  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1284 12:40:30.500004  ==

 1285 12:40:30.502927  RX Vref Scan: 0

 1286 12:40:30.503024  

 1287 12:40:30.503089  RX Vref 0 -> 0, step: 1

 1288 12:40:30.503153  

 1289 12:40:30.506626  RX Delay -130 -> 252, step: 16

 1290 12:40:30.513053  iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224

 1291 12:40:30.516197  iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224

 1292 12:40:30.519485  iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224

 1293 12:40:30.522728  iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224

 1294 12:40:30.525904  iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224

 1295 12:40:30.529647  iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240

 1296 12:40:30.536099  iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224

 1297 12:40:30.539790  iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240

 1298 12:40:30.542925  iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224

 1299 12:40:30.546120  iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224

 1300 12:40:30.549687  iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208

 1301 12:40:30.556827  iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224

 1302 12:40:30.559775  iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224

 1303 12:40:30.562769  iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224

 1304 12:40:30.566450  iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224

 1305 12:40:30.569434  iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224

 1306 12:40:30.573096  ==

 1307 12:40:30.576046  Dram Type= 6, Freq= 0, CH_0, rank 1

 1308 12:40:30.579831  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1309 12:40:30.579910  ==

 1310 12:40:30.579979  DQS Delay:

 1311 12:40:30.583122  DQS0 = 0, DQS1 = 0

 1312 12:40:30.583195  DQM Delay:

 1313 12:40:30.586304  DQM0 = 93, DQM1 = 86

 1314 12:40:30.586392  DQ Delay:

 1315 12:40:30.589437  DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93

 1316 12:40:30.593143  DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101

 1317 12:40:30.596259  DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77

 1318 12:40:30.600067  DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93

 1319 12:40:30.600185  

 1320 12:40:30.600281  

 1321 12:40:30.600376  ==

 1322 12:40:30.603081  Dram Type= 6, Freq= 0, CH_0, rank 1

 1323 12:40:30.606002  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1324 12:40:30.606093  ==

 1325 12:40:30.606189  

 1326 12:40:30.606296  

 1327 12:40:30.609569  	TX Vref Scan disable

 1328 12:40:30.612723   == TX Byte 0 ==

 1329 12:40:30.616409  Update DQ  dly =585 (2 ,1, 41)  DQ  OEN =(1 ,6)

 1330 12:40:30.619704  Update DQM dly =585 (2 ,1, 41)  DQM OEN =(1 ,6)

 1331 12:40:30.622944   == TX Byte 1 ==

 1332 12:40:30.626034  Update DQ  dly =581 (2 ,1, 37)  DQ  OEN =(1 ,6)

 1333 12:40:30.629837  Update DQM dly =581 (2 ,1, 37)  DQM OEN =(1 ,6)

 1334 12:40:30.629924  ==

 1335 12:40:30.633159  Dram Type= 6, Freq= 0, CH_0, rank 1

 1336 12:40:30.636359  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1337 12:40:30.639687  ==

 1338 12:40:30.650935  TX Vref=22, minBit 8, minWin=27, winSum=446

 1339 12:40:30.654842  TX Vref=24, minBit 1, minWin=28, winSum=451

 1340 12:40:30.657796  TX Vref=26, minBit 1, minWin=28, winSum=456

 1341 12:40:30.661333  TX Vref=28, minBit 4, minWin=28, winSum=458

 1342 12:40:30.664906  TX Vref=30, minBit 1, minWin=28, winSum=458

 1343 12:40:30.668089  TX Vref=32, minBit 1, minWin=28, winSum=450

 1344 12:40:30.674971  [TxChooseVref] Worse bit 4, Min win 28, Win sum 458, Final Vref 28

 1345 12:40:30.675057  

 1346 12:40:30.678228  Final TX Range 1 Vref 28

 1347 12:40:30.678314  

 1348 12:40:30.678379  ==

 1349 12:40:30.681808  Dram Type= 6, Freq= 0, CH_0, rank 1

 1350 12:40:30.684756  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1351 12:40:30.684860  ==

 1352 12:40:30.684928  

 1353 12:40:30.684989  

 1354 12:40:30.687965  	TX Vref Scan disable

 1355 12:40:30.691820   == TX Byte 0 ==

 1356 12:40:30.695010  Update DQ  dly =585 (2 ,1, 41)  DQ  OEN =(1 ,6)

 1357 12:40:30.698018  Update DQM dly =585 (2 ,1, 41)  DQM OEN =(1 ,6)

 1358 12:40:30.701205   == TX Byte 1 ==

 1359 12:40:30.704940  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1360 12:40:30.708190  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1361 12:40:30.708310  

 1362 12:40:30.711226  [DATLAT]

 1363 12:40:30.711310  Freq=800, CH0 RK1

 1364 12:40:30.711375  

 1365 12:40:30.714621  DATLAT Default: 0xa

 1366 12:40:30.714705  0, 0xFFFF, sum = 0

 1367 12:40:30.718298  1, 0xFFFF, sum = 0

 1368 12:40:30.718399  2, 0xFFFF, sum = 0

 1369 12:40:30.721369  3, 0xFFFF, sum = 0

 1370 12:40:30.721453  4, 0xFFFF, sum = 0

 1371 12:40:30.724510  5, 0xFFFF, sum = 0

 1372 12:40:30.724594  6, 0xFFFF, sum = 0

 1373 12:40:30.728364  7, 0xFFFF, sum = 0

 1374 12:40:30.728448  8, 0xFFFF, sum = 0

 1375 12:40:30.731397  9, 0x0, sum = 1

 1376 12:40:30.731481  10, 0x0, sum = 2

 1377 12:40:30.734590  11, 0x0, sum = 3

 1378 12:40:30.734691  12, 0x0, sum = 4

 1379 12:40:30.738000  best_step = 10

 1380 12:40:30.738108  

 1381 12:40:30.738184  ==

 1382 12:40:30.741590  Dram Type= 6, Freq= 0, CH_0, rank 1

 1383 12:40:30.744819  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1384 12:40:30.744897  ==

 1385 12:40:30.747857  RX Vref Scan: 0

 1386 12:40:30.747994  

 1387 12:40:30.748089  RX Vref 0 -> 0, step: 1

 1388 12:40:30.748194  

 1389 12:40:30.751847  RX Delay -79 -> 252, step: 8

 1390 12:40:30.758086  iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216

 1391 12:40:30.761316  iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216

 1392 12:40:30.764910  iDelay=209, Bit 2, Center 92 (-15 ~ 200) 216

 1393 12:40:30.767921  iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224

 1394 12:40:30.771604  iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216

 1395 12:40:30.774884  iDelay=209, Bit 5, Center 84 (-31 ~ 200) 232

 1396 12:40:30.781487  iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216

 1397 12:40:30.784850  iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216

 1398 12:40:30.788456  iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224

 1399 12:40:30.791559  iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216

 1400 12:40:30.794779  iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216

 1401 12:40:30.801894  iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216

 1402 12:40:30.805102  iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216

 1403 12:40:30.808230  iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208

 1404 12:40:30.811932  iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216

 1405 12:40:30.815117  iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216

 1406 12:40:30.818645  ==

 1407 12:40:30.818740  Dram Type= 6, Freq= 0, CH_0, rank 1

 1408 12:40:30.825335  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1409 12:40:30.825458  ==

 1410 12:40:30.825528  DQS Delay:

 1411 12:40:30.828643  DQS0 = 0, DQS1 = 0

 1412 12:40:30.828771  DQM Delay:

 1413 12:40:30.831830  DQM0 = 92, DQM1 = 83

 1414 12:40:30.831913  DQ Delay:

 1415 12:40:30.835142  DQ0 =92, DQ1 =92, DQ2 =92, DQ3 =88

 1416 12:40:30.838286  DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100

 1417 12:40:30.842022  DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =76

 1418 12:40:30.845333  DQ12 =92, DQ13 =88, DQ14 =92, DQ15 =92

 1419 12:40:30.845410  

 1420 12:40:30.845510  

 1421 12:40:30.851805  [DQSOSCAuto] RK1, (LSB)MR18= 0x4718, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps

 1422 12:40:30.854975  CH0 RK1: MR19=606, MR18=4718

 1423 12:40:30.861887  CH0_RK1: MR19=0x606, MR18=0x4718, DQSOSC=392, MR23=63, INC=96, DEC=64

 1424 12:40:30.864962  [RxdqsGatingPostProcess] freq 800

 1425 12:40:30.868868  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 1426 12:40:30.872090  Pre-setting of DQS Precalculation

 1427 12:40:30.878780  [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10

 1428 12:40:30.878859  ==

 1429 12:40:30.882508  Dram Type= 6, Freq= 0, CH_1, rank 0

 1430 12:40:30.885459  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1431 12:40:30.885583  ==

 1432 12:40:30.891716  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 1433 12:40:30.898643  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

 1434 12:40:30.906440  [CA 0] Center 36 (6~67) winsize 62

 1435 12:40:30.909534  [CA 1] Center 36 (6~67) winsize 62

 1436 12:40:30.913104  [CA 2] Center 35 (5~66) winsize 62

 1437 12:40:30.916171  [CA 3] Center 34 (4~65) winsize 62

 1438 12:40:30.919797  [CA 4] Center 34 (4~65) winsize 62

 1439 12:40:30.922857  [CA 5] Center 34 (4~64) winsize 61

 1440 12:40:30.922970  

 1441 12:40:30.925924  [CmdBusTrainingLP45] Vref(ca) range 1: 32

 1442 12:40:30.926011  

 1443 12:40:30.929600  [CATrainingPosCal] consider 1 rank data

 1444 12:40:30.932780  u2DelayCellTimex100 = 270/100 ps

 1445 12:40:30.936137  CA0 delay=36 (6~67),Diff = 2 PI (14 cell)

 1446 12:40:30.939832  CA1 delay=36 (6~67),Diff = 2 PI (14 cell)

 1447 12:40:30.946151  CA2 delay=35 (5~66),Diff = 1 PI (7 cell)

 1448 12:40:30.949278  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 1449 12:40:30.953130  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 1450 12:40:30.956310  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 1451 12:40:30.956413  

 1452 12:40:30.959465  CA PerBit enable=1, Macro0, CA PI delay=34

 1453 12:40:30.959551  

 1454 12:40:30.962706  [CBTSetCACLKResult] CA Dly = 34

 1455 12:40:30.962790  CS Dly: 6 (0~37)

 1456 12:40:30.962857  ==

 1457 12:40:30.966419  Dram Type= 6, Freq= 0, CH_1, rank 1

 1458 12:40:30.972830  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1459 12:40:30.972915  ==

 1460 12:40:30.976080  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 1461 12:40:30.983033  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

 1462 12:40:30.993037  [CA 0] Center 36 (6~67) winsize 62

 1463 12:40:30.995949  [CA 1] Center 37 (6~68) winsize 63

 1464 12:40:30.999818  [CA 2] Center 35 (5~66) winsize 62

 1465 12:40:31.003486  [CA 3] Center 34 (4~65) winsize 62

 1466 12:40:31.006862  [CA 4] Center 35 (4~66) winsize 63

 1467 12:40:31.010847  [CA 5] Center 34 (4~65) winsize 62

 1468 12:40:31.010937  

 1469 12:40:31.014050  [CmdBusTrainingLP45] Vref(ca) range 1: 34

 1470 12:40:31.014130  

 1471 12:40:31.017854  [CATrainingPosCal] consider 2 rank data

 1472 12:40:31.021966  u2DelayCellTimex100 = 270/100 ps

 1473 12:40:31.025700  CA0 delay=36 (6~67),Diff = 2 PI (14 cell)

 1474 12:40:31.029385  CA1 delay=36 (6~67),Diff = 2 PI (14 cell)

 1475 12:40:31.032376  CA2 delay=35 (5~66),Diff = 1 PI (7 cell)

 1476 12:40:31.035948  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 1477 12:40:31.039472  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 1478 12:40:31.042610  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 1479 12:40:31.042695  

 1480 12:40:31.045885  CA PerBit enable=1, Macro0, CA PI delay=34

 1481 12:40:31.045981  

 1482 12:40:31.048977  [CBTSetCACLKResult] CA Dly = 34

 1483 12:40:31.049074  CS Dly: 6 (0~38)

 1484 12:40:31.049143  

 1485 12:40:31.052705  ----->DramcWriteLeveling(PI) begin...

 1486 12:40:31.056062  ==

 1487 12:40:31.056147  Dram Type= 6, Freq= 0, CH_1, rank 0

 1488 12:40:31.062523  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1489 12:40:31.062614  ==

 1490 12:40:31.065531  Write leveling (Byte 0): 26 => 26

 1491 12:40:31.068679  Write leveling (Byte 1): 30 => 30

 1492 12:40:31.072567  DramcWriteLeveling(PI) end<-----

 1493 12:40:31.072646  

 1494 12:40:31.072711  ==

 1495 12:40:31.075931  Dram Type= 6, Freq= 0, CH_1, rank 0

 1496 12:40:31.078991  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1497 12:40:31.079070  ==

 1498 12:40:31.082192  [Gating] SW mode calibration

 1499 12:40:31.089265  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1500 12:40:31.092445  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1501 12:40:31.099367   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1502 12:40:31.102248   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 1503 12:40:31.105420   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1504 12:40:31.112288   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1505 12:40:31.115647   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1506 12:40:31.118890   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1507 12:40:31.125861   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1508 12:40:31.129316   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1509 12:40:31.132317   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1510 12:40:31.139521   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1511 12:40:31.142471   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1512 12:40:31.145931   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1513 12:40:31.152450   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1514 12:40:31.155500   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1515 12:40:31.158802   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1516 12:40:31.165912   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1517 12:40:31.169069   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)

 1518 12:40:31.172172   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)

 1519 12:40:31.176016   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1520 12:40:31.182516   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1521 12:40:31.185891   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1522 12:40:31.189076   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1523 12:40:31.196123   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1524 12:40:31.199260   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1525 12:40:31.202266   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1526 12:40:31.209559   0  9  4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)

 1527 12:40:31.212649   0  9  8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)

 1528 12:40:31.215740   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1529 12:40:31.222863   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1530 12:40:31.226088   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1531 12:40:31.229270   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1532 12:40:31.232919   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1533 12:40:31.239818   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)

 1534 12:40:31.242549   0 10  4 | B1->B0 | 3434 2e2e | 1 1 | (1 0) (1 1)

 1535 12:40:31.246136   0 10  8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)

 1536 12:40:31.252716   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1537 12:40:31.256222   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1538 12:40:31.259195   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1539 12:40:31.265704   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1540 12:40:31.269122   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1541 12:40:31.272717   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1542 12:40:31.279065   0 11  4 | B1->B0 | 2828 3b3b | 0 0 | (0 0) (0 0)

 1543 12:40:31.282299   0 11  8 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)

 1544 12:40:31.285558   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1545 12:40:31.292618   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1546 12:40:31.295991   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1547 12:40:31.298967   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1548 12:40:31.305846   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1549 12:40:31.308934   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 1550 12:40:31.312576   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 1551 12:40:31.319119   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1552 12:40:31.322835   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1553 12:40:31.325949   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1554 12:40:31.332450   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1555 12:40:31.335781   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1556 12:40:31.339016   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1557 12:40:31.345907   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1558 12:40:31.349082   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1559 12:40:31.352706   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1560 12:40:31.355697   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1561 12:40:31.362472   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1562 12:40:31.366088   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1563 12:40:31.369475   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1564 12:40:31.375720   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1565 12:40:31.379357   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1566 12:40:31.382545   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 1567 12:40:31.389132   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1568 12:40:31.389239  Total UI for P1: 0, mck2ui 16

 1569 12:40:31.396058  best dqsien dly found for B0: ( 0, 14,  4)

 1570 12:40:31.396163  Total UI for P1: 0, mck2ui 16

 1571 12:40:31.402978  best dqsien dly found for B1: ( 0, 14,  4)

 1572 12:40:31.406414  best DQS0 dly(MCK, UI, PI) = (0, 14, 4)

 1573 12:40:31.409615  best DQS1 dly(MCK, UI, PI) = (0, 14, 4)

 1574 12:40:31.409702  

 1575 12:40:31.412798  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1576 12:40:31.416050  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1577 12:40:31.419522  [Gating] SW calibration Done

 1578 12:40:31.419622  ==

 1579 12:40:31.422702  Dram Type= 6, Freq= 0, CH_1, rank 0

 1580 12:40:31.426204  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1581 12:40:31.426311  ==

 1582 12:40:31.426407  RX Vref Scan: 0

 1583 12:40:31.429135  

 1584 12:40:31.429209  RX Vref 0 -> 0, step: 1

 1585 12:40:31.429272  

 1586 12:40:31.432874  RX Delay -130 -> 252, step: 16

 1587 12:40:31.436089  iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224

 1588 12:40:31.439337  iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208

 1589 12:40:31.446005  iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208

 1590 12:40:31.449220  iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224

 1591 12:40:31.453047  iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224

 1592 12:40:31.455989  iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224

 1593 12:40:31.459677  iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240

 1594 12:40:31.465858  iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224

 1595 12:40:31.469303  iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208

 1596 12:40:31.473031  iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208

 1597 12:40:31.475974  iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208

 1598 12:40:31.479615  iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208

 1599 12:40:31.486432  iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224

 1600 12:40:31.489789  iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224

 1601 12:40:31.493204  iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224

 1602 12:40:31.496394  iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208

 1603 12:40:31.496490  ==

 1604 12:40:31.499975  Dram Type= 6, Freq= 0, CH_1, rank 0

 1605 12:40:31.506263  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1606 12:40:31.506368  ==

 1607 12:40:31.506434  DQS Delay:

 1608 12:40:31.509423  DQS0 = 0, DQS1 = 0

 1609 12:40:31.509507  DQM Delay:

 1610 12:40:31.509573  DQM0 = 94, DQM1 = 90

 1611 12:40:31.513125  DQ Delay:

 1612 12:40:31.516444  DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93

 1613 12:40:31.519686  DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93

 1614 12:40:31.522881  DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85

 1615 12:40:31.526588  DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =101

 1616 12:40:31.526692  

 1617 12:40:31.526791  

 1618 12:40:31.526867  ==

 1619 12:40:31.529815  Dram Type= 6, Freq= 0, CH_1, rank 0

 1620 12:40:31.532727  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1621 12:40:31.532844  ==

 1622 12:40:31.532913  

 1623 12:40:31.532988  

 1624 12:40:31.536527  	TX Vref Scan disable

 1625 12:40:31.536603   == TX Byte 0 ==

 1626 12:40:31.542817  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1627 12:40:31.546809  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1628 12:40:31.546888   == TX Byte 1 ==

 1629 12:40:31.552800  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1630 12:40:31.556663  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1631 12:40:31.556741  ==

 1632 12:40:31.559781  Dram Type= 6, Freq= 0, CH_1, rank 0

 1633 12:40:31.562839  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1634 12:40:31.562926  ==

 1635 12:40:31.574874  TX Vref=22, minBit 1, minWin=26, winSum=431

 1636 12:40:31.581393  TX Vref=24, minBit 0, minWin=26, winSum=432

 1637 12:40:31.585027  TX Vref=26, minBit 0, minWin=26, winSum=436

 1638 12:40:31.588020  TX Vref=28, minBit 0, minWin=26, winSum=439

 1639 12:40:31.591843  TX Vref=30, minBit 3, minWin=26, winSum=440

 1640 12:40:31.595159  TX Vref=32, minBit 3, minWin=26, winSum=445

 1641 12:40:31.601522  [TxChooseVref] Worse bit 3, Min win 26, Win sum 445, Final Vref 32

 1642 12:40:31.601620  

 1643 12:40:31.604923  Final TX Range 1 Vref 32

 1644 12:40:31.605011  

 1645 12:40:31.605079  ==

 1646 12:40:31.608023  Dram Type= 6, Freq= 0, CH_1, rank 0

 1647 12:40:31.611785  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1648 12:40:31.611873  ==

 1649 12:40:31.611942  

 1650 12:40:31.612005  

 1651 12:40:31.615070  	TX Vref Scan disable

 1652 12:40:31.618266   == TX Byte 0 ==

 1653 12:40:31.621396  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 1654 12:40:31.624677  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 1655 12:40:31.628378   == TX Byte 1 ==

 1656 12:40:31.631550  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1657 12:40:31.634792  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1658 12:40:31.634877  

 1659 12:40:31.634944  [DATLAT]

 1660 12:40:31.638600  Freq=800, CH1 RK0

 1661 12:40:31.638685  

 1662 12:40:31.641623  DATLAT Default: 0xa

 1663 12:40:31.641708  0, 0xFFFF, sum = 0

 1664 12:40:31.644704  1, 0xFFFF, sum = 0

 1665 12:40:31.644824  2, 0xFFFF, sum = 0

 1666 12:40:31.647890  3, 0xFFFF, sum = 0

 1667 12:40:31.647976  4, 0xFFFF, sum = 0

 1668 12:40:31.651452  5, 0xFFFF, sum = 0

 1669 12:40:31.651538  6, 0xFFFF, sum = 0

 1670 12:40:31.655167  7, 0xFFFF, sum = 0

 1671 12:40:31.655254  8, 0xFFFF, sum = 0

 1672 12:40:31.658459  9, 0x0, sum = 1

 1673 12:40:31.658545  10, 0x0, sum = 2

 1674 12:40:31.661597  11, 0x0, sum = 3

 1675 12:40:31.661683  12, 0x0, sum = 4

 1676 12:40:31.661752  best_step = 10

 1677 12:40:31.661815  

 1678 12:40:31.664791  ==

 1679 12:40:31.668631  Dram Type= 6, Freq= 0, CH_1, rank 0

 1680 12:40:31.671420  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1681 12:40:31.671508  ==

 1682 12:40:31.671577  RX Vref Scan: 1

 1683 12:40:31.671640  

 1684 12:40:31.674754  Set Vref Range= 32 -> 127

 1685 12:40:31.674840  

 1686 12:40:31.678439  RX Vref 32 -> 127, step: 1

 1687 12:40:31.678524  

 1688 12:40:31.681515  RX Delay -63 -> 252, step: 8

 1689 12:40:31.681600  

 1690 12:40:31.685477  Set Vref, RX VrefLevel [Byte0]: 32

 1691 12:40:31.688439                           [Byte1]: 32

 1692 12:40:31.688526  

 1693 12:40:31.691751  Set Vref, RX VrefLevel [Byte0]: 33

 1694 12:40:31.694538                           [Byte1]: 33

 1695 12:40:31.694625  

 1696 12:40:31.698089  Set Vref, RX VrefLevel [Byte0]: 34

 1697 12:40:31.701194                           [Byte1]: 34

 1698 12:40:31.704435  

 1699 12:40:31.704541  Set Vref, RX VrefLevel [Byte0]: 35

 1700 12:40:31.708207                           [Byte1]: 35

 1701 12:40:31.712206  

 1702 12:40:31.712312  Set Vref, RX VrefLevel [Byte0]: 36

 1703 12:40:31.715851                           [Byte1]: 36

 1704 12:40:31.719755  

 1705 12:40:31.719862  Set Vref, RX VrefLevel [Byte0]: 37

 1706 12:40:31.723017                           [Byte1]: 37

 1707 12:40:31.727513  

 1708 12:40:31.727619  Set Vref, RX VrefLevel [Byte0]: 38

 1709 12:40:31.730861                           [Byte1]: 38

 1710 12:40:31.734770  

 1711 12:40:31.734882  Set Vref, RX VrefLevel [Byte0]: 39

 1712 12:40:31.737919                           [Byte1]: 39

 1713 12:40:31.742282  

 1714 12:40:31.742390  Set Vref, RX VrefLevel [Byte0]: 40

 1715 12:40:31.745422                           [Byte1]: 40

 1716 12:40:31.749676  

 1717 12:40:31.749783  Set Vref, RX VrefLevel [Byte0]: 41

 1718 12:40:31.752787                           [Byte1]: 41

 1719 12:40:31.757319  

 1720 12:40:31.757430  Set Vref, RX VrefLevel [Byte0]: 42

 1721 12:40:31.760459                           [Byte1]: 42

 1722 12:40:31.764824  

 1723 12:40:31.764909  Set Vref, RX VrefLevel [Byte0]: 43

 1724 12:40:31.768124                           [Byte1]: 43

 1725 12:40:31.772200  

 1726 12:40:31.772306  Set Vref, RX VrefLevel [Byte0]: 44

 1727 12:40:31.775688                           [Byte1]: 44

 1728 12:40:31.779377  

 1729 12:40:31.779483  Set Vref, RX VrefLevel [Byte0]: 45

 1730 12:40:31.782914                           [Byte1]: 45

 1731 12:40:31.787214  

 1732 12:40:31.787325  Set Vref, RX VrefLevel [Byte0]: 46

 1733 12:40:31.793608                           [Byte1]: 46

 1734 12:40:31.793700  

 1735 12:40:31.796891  Set Vref, RX VrefLevel [Byte0]: 47

 1736 12:40:31.799989                           [Byte1]: 47

 1737 12:40:31.800106  

 1738 12:40:31.803749  Set Vref, RX VrefLevel [Byte0]: 48

 1739 12:40:31.806961                           [Byte1]: 48

 1740 12:40:31.807084  

 1741 12:40:31.810037  Set Vref, RX VrefLevel [Byte0]: 49

 1742 12:40:31.813804                           [Byte1]: 49

 1743 12:40:31.817008  

 1744 12:40:31.817094  Set Vref, RX VrefLevel [Byte0]: 50

 1745 12:40:31.820194                           [Byte1]: 50

 1746 12:40:31.824700  

 1747 12:40:31.824811  Set Vref, RX VrefLevel [Byte0]: 51

 1748 12:40:31.828049                           [Byte1]: 51

 1749 12:40:31.831892  

 1750 12:40:31.832008  Set Vref, RX VrefLevel [Byte0]: 52

 1751 12:40:31.835133                           [Byte1]: 52

 1752 12:40:31.839496  

 1753 12:40:31.839602  Set Vref, RX VrefLevel [Byte0]: 53

 1754 12:40:31.842746                           [Byte1]: 53

 1755 12:40:31.846762  

 1756 12:40:31.846865  Set Vref, RX VrefLevel [Byte0]: 54

 1757 12:40:31.850407                           [Byte1]: 54

 1758 12:40:31.854874  

 1759 12:40:31.854978  Set Vref, RX VrefLevel [Byte0]: 55

 1760 12:40:31.857954                           [Byte1]: 55

 1761 12:40:31.862052  

 1762 12:40:31.862135  Set Vref, RX VrefLevel [Byte0]: 56

 1763 12:40:31.865330                           [Byte1]: 56

 1764 12:40:31.869914  

 1765 12:40:31.869997  Set Vref, RX VrefLevel [Byte0]: 57

 1766 12:40:31.873050                           [Byte1]: 57

 1767 12:40:31.876876  

 1768 12:40:31.876984  Set Vref, RX VrefLevel [Byte0]: 58

 1769 12:40:31.880650                           [Byte1]: 58

 1770 12:40:31.884408  

 1771 12:40:31.884521  Set Vref, RX VrefLevel [Byte0]: 59

 1772 12:40:31.888116                           [Byte1]: 59

 1773 12:40:31.892218  

 1774 12:40:31.892342  Set Vref, RX VrefLevel [Byte0]: 60

 1775 12:40:31.895262                           [Byte1]: 60

 1776 12:40:31.899444  

 1777 12:40:31.899561  Set Vref, RX VrefLevel [Byte0]: 61

 1778 12:40:31.903067                           [Byte1]: 61

 1779 12:40:31.907167  

 1780 12:40:31.907276  Set Vref, RX VrefLevel [Byte0]: 62

 1781 12:40:31.910240                           [Byte1]: 62

 1782 12:40:31.914911  

 1783 12:40:31.915019  Set Vref, RX VrefLevel [Byte0]: 63

 1784 12:40:31.918062                           [Byte1]: 63

 1785 12:40:31.921841  

 1786 12:40:31.921947  Set Vref, RX VrefLevel [Byte0]: 64

 1787 12:40:31.925710                           [Byte1]: 64

 1788 12:40:31.929833  

 1789 12:40:31.929915  Set Vref, RX VrefLevel [Byte0]: 65

 1790 12:40:31.932906                           [Byte1]: 65

 1791 12:40:31.936903  

 1792 12:40:31.936977  Set Vref, RX VrefLevel [Byte0]: 66

 1793 12:40:31.940689                           [Byte1]: 66

 1794 12:40:31.944433  

 1795 12:40:31.944535  Set Vref, RX VrefLevel [Byte0]: 67

 1796 12:40:31.948301                           [Byte1]: 67

 1797 12:40:31.952206  

 1798 12:40:31.952304  Set Vref, RX VrefLevel [Byte0]: 68

 1799 12:40:31.955203                           [Byte1]: 68

 1800 12:40:31.959536  

 1801 12:40:31.959640  Set Vref, RX VrefLevel [Byte0]: 69

 1802 12:40:31.963178                           [Byte1]: 69

 1803 12:40:31.966806  

 1804 12:40:31.966910  Set Vref, RX VrefLevel [Byte0]: 70

 1805 12:40:31.970727                           [Byte1]: 70

 1806 12:40:31.974575  

 1807 12:40:31.974681  Set Vref, RX VrefLevel [Byte0]: 71

 1808 12:40:31.977601                           [Byte1]: 71

 1809 12:40:31.982112  

 1810 12:40:31.982200  Set Vref, RX VrefLevel [Byte0]: 72

 1811 12:40:31.985424                           [Byte1]: 72

 1812 12:40:31.989690  

 1813 12:40:31.989768  Final RX Vref Byte 0 = 60 to rank0

 1814 12:40:31.992712  Final RX Vref Byte 1 = 54 to rank0

 1815 12:40:31.996591  Final RX Vref Byte 0 = 60 to rank1

 1816 12:40:31.999798  Final RX Vref Byte 1 = 54 to rank1==

 1817 12:40:32.003161  Dram Type= 6, Freq= 0, CH_1, rank 0

 1818 12:40:32.006210  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1819 12:40:32.010001  ==

 1820 12:40:32.010104  DQS Delay:

 1821 12:40:32.010176  DQS0 = 0, DQS1 = 0

 1822 12:40:32.012825  DQM Delay:

 1823 12:40:32.012912  DQM0 = 96, DQM1 = 90

 1824 12:40:32.016555  DQ Delay:

 1825 12:40:32.019539  DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =88

 1826 12:40:32.022774  DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =96

 1827 12:40:32.022873  DQ8 =80, DQ9 =76, DQ10 =92, DQ11 =84

 1828 12:40:32.029764  DQ12 =96, DQ13 =100, DQ14 =96, DQ15 =100

 1829 12:40:32.029858  

 1830 12:40:32.029926  

 1831 12:40:32.036145  [DQSOSCAuto] RK0, (LSB)MR18= 0x314d, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps

 1832 12:40:32.039493  CH1 RK0: MR19=606, MR18=314D

 1833 12:40:32.046616  CH1_RK0: MR19=0x606, MR18=0x314D, DQSOSC=390, MR23=63, INC=97, DEC=64

 1834 12:40:32.046724  

 1835 12:40:32.049841  ----->DramcWriteLeveling(PI) begin...

 1836 12:40:32.049926  ==

 1837 12:40:32.053108  Dram Type= 6, Freq= 0, CH_1, rank 1

 1838 12:40:32.056386  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1839 12:40:32.056476  ==

 1840 12:40:32.059541  Write leveling (Byte 0): 25 => 25

 1841 12:40:32.063152  Write leveling (Byte 1): 28 => 28

 1842 12:40:32.066199  DramcWriteLeveling(PI) end<-----

 1843 12:40:32.066287  

 1844 12:40:32.066352  ==

 1845 12:40:32.070018  Dram Type= 6, Freq= 0, CH_1, rank 1

 1846 12:40:32.073336  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1847 12:40:32.073429  ==

 1848 12:40:32.076658  [Gating] SW mode calibration

 1849 12:40:32.083505  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1850 12:40:32.090084  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1851 12:40:32.093367   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)

 1852 12:40:32.096454   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)

 1853 12:40:32.103530   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1854 12:40:32.106996   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1855 12:40:32.110054   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1856 12:40:32.116504   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1857 12:40:32.120135   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1858 12:40:32.123149   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1859 12:40:32.129915   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1860 12:40:32.133073   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1861 12:40:32.136381   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1862 12:40:32.143508   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1863 12:40:32.146920   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1864 12:40:32.149958   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1865 12:40:32.153150   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1866 12:40:32.160294   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1867 12:40:32.163433   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)

 1868 12:40:32.166707   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)

 1869 12:40:32.173429   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1870 12:40:32.176953   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1871 12:40:32.179833   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1872 12:40:32.186447   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1873 12:40:32.189743   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1874 12:40:32.193045   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1875 12:40:32.200009   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1876 12:40:32.203647   0  9  4 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)

 1877 12:40:32.206673   0  9  8 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 0)

 1878 12:40:32.213832   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1879 12:40:32.216589   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1880 12:40:32.220019   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1881 12:40:32.223580   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1882 12:40:32.230192   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1883 12:40:32.233253   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1884 12:40:32.237102   0 10  4 | B1->B0 | 2e2e 3131 | 1 1 | (1 0) (1 0)

 1885 12:40:32.243545   0 10  8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 1886 12:40:32.246781   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1887 12:40:32.249980   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1888 12:40:32.256724   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1889 12:40:32.260017   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1890 12:40:32.263459   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1891 12:40:32.270381   0 11  0 | B1->B0 | 2525 2323 | 1 0 | (0 0) (0 0)

 1892 12:40:32.273375   0 11  4 | B1->B0 | 4141 2b2b | 0 1 | (0 0) (0 0)

 1893 12:40:32.277172   0 11  8 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (1 1)

 1894 12:40:32.283486   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1895 12:40:32.287164   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1896 12:40:32.290174   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1897 12:40:32.297242   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1898 12:40:32.300472   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1899 12:40:32.303628   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1900 12:40:32.307392   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 1901 12:40:32.313586   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1902 12:40:32.317288   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1903 12:40:32.320502   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1904 12:40:32.327179   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1905 12:40:32.330854   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1906 12:40:32.333862   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1907 12:40:32.340562   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1908 12:40:32.343863   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1909 12:40:32.347036   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1910 12:40:32.354025   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1911 12:40:32.357144   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1912 12:40:32.360348   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1913 12:40:32.367470   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1914 12:40:32.370836   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1915 12:40:32.374006   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 1916 12:40:32.380823   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 1917 12:40:32.384018   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1918 12:40:32.387202  Total UI for P1: 0, mck2ui 16

 1919 12:40:32.391005  best dqsien dly found for B0: ( 0, 14,  4)

 1920 12:40:32.394131  Total UI for P1: 0, mck2ui 16

 1921 12:40:32.397333  best dqsien dly found for B1: ( 0, 14,  2)

 1922 12:40:32.400382  best DQS0 dly(MCK, UI, PI) = (0, 14, 4)

 1923 12:40:32.404193  best DQS1 dly(MCK, UI, PI) = (0, 14, 2)

 1924 12:40:32.404293  

 1925 12:40:32.407588  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1926 12:40:32.410821  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)

 1927 12:40:32.413962  [Gating] SW calibration Done

 1928 12:40:32.414047  ==

 1929 12:40:32.417238  Dram Type= 6, Freq= 0, CH_1, rank 1

 1930 12:40:32.420748  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1931 12:40:32.420857  ==

 1932 12:40:32.424448  RX Vref Scan: 0

 1933 12:40:32.424538  

 1934 12:40:32.424606  RX Vref 0 -> 0, step: 1

 1935 12:40:32.424668  

 1936 12:40:32.427155  RX Delay -130 -> 252, step: 16

 1937 12:40:32.430811  iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208

 1938 12:40:32.437174  iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208

 1939 12:40:32.441043  iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208

 1940 12:40:32.443970  iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208

 1941 12:40:32.447726  iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208

 1942 12:40:32.450798  iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224

 1943 12:40:32.457228  iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208

 1944 12:40:32.461156  iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224

 1945 12:40:32.464171  iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224

 1946 12:40:32.467525  iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224

 1947 12:40:32.470800  iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224

 1948 12:40:32.477931  iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224

 1949 12:40:32.481194  iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224

 1950 12:40:32.484459  iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208

 1951 12:40:32.487293  iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224

 1952 12:40:32.491065  iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208

 1953 12:40:32.494397  ==

 1954 12:40:32.494481  Dram Type= 6, Freq= 0, CH_1, rank 1

 1955 12:40:32.500707  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1956 12:40:32.500792  ==

 1957 12:40:32.500897  DQS Delay:

 1958 12:40:32.504459  DQS0 = 0, DQS1 = 0

 1959 12:40:32.504546  DQM Delay:

 1960 12:40:32.507447  DQM0 = 93, DQM1 = 89

 1961 12:40:32.507565  DQ Delay:

 1962 12:40:32.510763  DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85

 1963 12:40:32.514119  DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93

 1964 12:40:32.517928  DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77

 1965 12:40:32.521229  DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =101

 1966 12:40:32.521380  

 1967 12:40:32.521477  

 1968 12:40:32.521572  ==

 1969 12:40:32.524309  Dram Type= 6, Freq= 0, CH_1, rank 1

 1970 12:40:32.527958  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1971 12:40:32.528043  ==

 1972 12:40:32.528109  

 1973 12:40:32.528170  

 1974 12:40:32.531033  	TX Vref Scan disable

 1975 12:40:32.534764   == TX Byte 0 ==

 1976 12:40:32.537591  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 1977 12:40:32.540933  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 1978 12:40:32.544380   == TX Byte 1 ==

 1979 12:40:32.547957  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1980 12:40:32.551143  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1981 12:40:32.551231  ==

 1982 12:40:32.554814  Dram Type= 6, Freq= 0, CH_1, rank 1

 1983 12:40:32.557996  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1984 12:40:32.561193  ==

 1985 12:40:32.572127  TX Vref=22, minBit 3, minWin=25, winSum=433

 1986 12:40:32.576042  TX Vref=24, minBit 3, minWin=25, winSum=440

 1987 12:40:32.579257  TX Vref=26, minBit 1, minWin=26, winSum=443

 1988 12:40:32.582505  TX Vref=28, minBit 4, minWin=26, winSum=446

 1989 12:40:32.585672  TX Vref=30, minBit 0, minWin=26, winSum=447

 1990 12:40:32.588819  TX Vref=32, minBit 0, minWin=26, winSum=441

 1991 12:40:32.595577  [TxChooseVref] Worse bit 0, Min win 26, Win sum 447, Final Vref 30

 1992 12:40:32.595667  

 1993 12:40:32.599179  Final TX Range 1 Vref 30

 1994 12:40:32.599267  

 1995 12:40:32.599334  ==

 1996 12:40:32.602421  Dram Type= 6, Freq= 0, CH_1, rank 1

 1997 12:40:32.605541  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1998 12:40:32.605654  ==

 1999 12:40:32.605759  

 2000 12:40:32.608711  

 2001 12:40:32.608859  	TX Vref Scan disable

 2002 12:40:32.612367   == TX Byte 0 ==

 2003 12:40:32.615430  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 2004 12:40:32.621906  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 2005 12:40:32.622014   == TX Byte 1 ==

 2006 12:40:32.625172  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 2007 12:40:32.631906  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 2008 12:40:32.632011  

 2009 12:40:32.632107  [DATLAT]

 2010 12:40:32.632196  Freq=800, CH1 RK1

 2011 12:40:32.632296  

 2012 12:40:32.635665  DATLAT Default: 0xa

 2013 12:40:32.635774  0, 0xFFFF, sum = 0

 2014 12:40:32.639234  1, 0xFFFF, sum = 0

 2015 12:40:32.639352  2, 0xFFFF, sum = 0

 2016 12:40:32.642339  3, 0xFFFF, sum = 0

 2017 12:40:32.642473  4, 0xFFFF, sum = 0

 2018 12:40:32.645740  5, 0xFFFF, sum = 0

 2019 12:40:32.645830  6, 0xFFFF, sum = 0

 2020 12:40:32.649106  7, 0xFFFF, sum = 0

 2021 12:40:32.649212  8, 0xFFFF, sum = 0

 2022 12:40:32.652216  9, 0x0, sum = 1

 2023 12:40:32.652320  10, 0x0, sum = 2

 2024 12:40:32.655664  11, 0x0, sum = 3

 2025 12:40:32.655775  12, 0x0, sum = 4

 2026 12:40:32.659335  best_step = 10

 2027 12:40:32.659436  

 2028 12:40:32.659532  ==

 2029 12:40:32.662342  Dram Type= 6, Freq= 0, CH_1, rank 1

 2030 12:40:32.665669  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2031 12:40:32.665746  ==

 2032 12:40:32.668878  RX Vref Scan: 0

 2033 12:40:32.668974  

 2034 12:40:32.669041  RX Vref 0 -> 0, step: 1

 2035 12:40:32.669106  

 2036 12:40:32.672567  RX Delay -79 -> 252, step: 8

 2037 12:40:32.678992  iDelay=209, Bit 0, Center 104 (9 ~ 200) 192

 2038 12:40:32.682309  iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200

 2039 12:40:32.685585  iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200

 2040 12:40:32.688887  iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200

 2041 12:40:32.692764  iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200

 2042 12:40:32.696069  iDelay=209, Bit 5, Center 112 (17 ~ 208) 192

 2043 12:40:32.702666  iDelay=209, Bit 6, Center 112 (17 ~ 208) 192

 2044 12:40:32.705801  iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208

 2045 12:40:32.708955  iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208

 2046 12:40:32.712738  iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208

 2047 12:40:32.715759  iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208

 2048 12:40:32.722530  iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208

 2049 12:40:32.725733  iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216

 2050 12:40:32.729774  iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208

 2051 12:40:32.732814  iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208

 2052 12:40:32.736128  iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208

 2053 12:40:32.736206  ==

 2054 12:40:32.739239  Dram Type= 6, Freq= 0, CH_1, rank 1

 2055 12:40:32.746377  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2056 12:40:32.746458  ==

 2057 12:40:32.746527  DQS Delay:

 2058 12:40:32.746588  DQS0 = 0, DQS1 = 0

 2059 12:40:32.749180  DQM Delay:

 2060 12:40:32.749265  DQM0 = 98, DQM1 = 91

 2061 12:40:32.752873  DQ Delay:

 2062 12:40:32.756376  DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92

 2063 12:40:32.759420  DQ4 =92, DQ5 =112, DQ6 =112, DQ7 =96

 2064 12:40:32.763248  DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =88

 2065 12:40:32.766069  DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96

 2066 12:40:32.766150  

 2067 12:40:32.766213  

 2068 12:40:32.772687  [DQSOSCAuto] RK1, (LSB)MR18= 0x4b14, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 391 ps

 2069 12:40:32.776452  CH1 RK1: MR19=606, MR18=4B14

 2070 12:40:32.782827  CH1_RK1: MR19=0x606, MR18=0x4B14, DQSOSC=391, MR23=63, INC=96, DEC=64

 2071 12:40:32.786059  [RxdqsGatingPostProcess] freq 800

 2072 12:40:32.790014  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 2073 12:40:32.793174  Pre-setting of DQS Precalculation

 2074 12:40:32.799419  [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10

 2075 12:40:32.806361  sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4

 2076 12:40:32.812455  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 2077 12:40:32.812580  

 2078 12:40:32.812676  

 2079 12:40:32.815995  [Calibration Summary] 1600 Mbps

 2080 12:40:32.816098  CH 0, Rank 0

 2081 12:40:32.819161  SW Impedance     : PASS

 2082 12:40:32.823058  DUTY Scan        : NO K

 2083 12:40:32.823167  ZQ Calibration   : PASS

 2084 12:40:32.826137  Jitter Meter     : NO K

 2085 12:40:32.829734  CBT Training     : PASS

 2086 12:40:32.829841  Write leveling   : PASS

 2087 12:40:32.833079  RX DQS gating    : PASS

 2088 12:40:32.836451  RX DQ/DQS(RDDQC) : PASS

 2089 12:40:32.836556  TX DQ/DQS        : PASS

 2090 12:40:32.839666  RX DATLAT        : PASS

 2091 12:40:32.839766  RX DQ/DQS(Engine): PASS

 2092 12:40:32.842798  TX OE            : NO K

 2093 12:40:32.842874  All Pass.

 2094 12:40:32.842941  

 2095 12:40:32.846228  CH 0, Rank 1

 2096 12:40:32.846310  SW Impedance     : PASS

 2097 12:40:32.849849  DUTY Scan        : NO K

 2098 12:40:32.852880  ZQ Calibration   : PASS

 2099 12:40:32.852986  Jitter Meter     : NO K

 2100 12:40:32.856798  CBT Training     : PASS

 2101 12:40:32.859537  Write leveling   : PASS

 2102 12:40:32.859623  RX DQS gating    : PASS

 2103 12:40:32.863085  RX DQ/DQS(RDDQC) : PASS

 2104 12:40:32.866519  TX DQ/DQS        : PASS

 2105 12:40:32.866599  RX DATLAT        : PASS

 2106 12:40:32.869644  RX DQ/DQS(Engine): PASS

 2107 12:40:32.872675  TX OE            : NO K

 2108 12:40:32.872778  All Pass.

 2109 12:40:32.872881  

 2110 12:40:32.872971  CH 1, Rank 0

 2111 12:40:32.876244  SW Impedance     : PASS

 2112 12:40:32.876365  DUTY Scan        : NO K

 2113 12:40:32.879733  ZQ Calibration   : PASS

 2114 12:40:32.882834  Jitter Meter     : NO K

 2115 12:40:32.882940  CBT Training     : PASS

 2116 12:40:32.886074  Write leveling   : PASS

 2117 12:40:32.890002  RX DQS gating    : PASS

 2118 12:40:32.890077  RX DQ/DQS(RDDQC) : PASS

 2119 12:40:32.892640  TX DQ/DQS        : PASS

 2120 12:40:32.896440  RX DATLAT        : PASS

 2121 12:40:32.896544  RX DQ/DQS(Engine): PASS

 2122 12:40:32.899682  TX OE            : NO K

 2123 12:40:32.899788  All Pass.

 2124 12:40:32.899892  

 2125 12:40:32.902901  CH 1, Rank 1

 2126 12:40:32.903003  SW Impedance     : PASS

 2127 12:40:32.906115  DUTY Scan        : NO K

 2128 12:40:32.909449  ZQ Calibration   : PASS

 2129 12:40:32.909538  Jitter Meter     : NO K

 2130 12:40:32.913259  CBT Training     : PASS

 2131 12:40:32.916196  Write leveling   : PASS

 2132 12:40:32.916287  RX DQS gating    : PASS

 2133 12:40:32.919873  RX DQ/DQS(RDDQC) : PASS

 2134 12:40:32.919971  TX DQ/DQS        : PASS

 2135 12:40:32.923286  RX DATLAT        : PASS

 2136 12:40:32.926507  RX DQ/DQS(Engine): PASS

 2137 12:40:32.926610  TX OE            : NO K

 2138 12:40:32.929854  All Pass.

 2139 12:40:32.929971  

 2140 12:40:32.930089  DramC Write-DBI off

 2141 12:40:32.933099  	PER_BANK_REFRESH: Hybrid Mode

 2142 12:40:32.936004  TX_TRACKING: ON

 2143 12:40:32.939771  [GetDramInforAfterCalByMRR] Vendor 6.

 2144 12:40:32.942936  [GetDramInforAfterCalByMRR] Revision 606.

 2145 12:40:32.946036  [GetDramInforAfterCalByMRR] Revision 2 0.

 2146 12:40:32.946163  MR0 0x3b3b

 2147 12:40:32.946269  MR8 0x5151

 2148 12:40:32.953083  RK0, DieNum 2, Density 16Gb, RKsize 32Gb.

 2149 12:40:32.953166  

 2150 12:40:32.953232  MR0 0x3b3b

 2151 12:40:32.953302  MR8 0x5151

 2152 12:40:32.956102  RK1, DieNum 2, Density 16Gb, RKsize 32Gb.

 2153 12:40:32.956216  

 2154 12:40:32.966794  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0

 2155 12:40:32.969786  [FAST_K] Save calibration result to emmc

 2156 12:40:32.972855  [FAST_K] Save calibration result to emmc

 2157 12:40:32.976814  dram_init: config_dvfs: 1

 2158 12:40:32.979978  dramc_set_vcore_voltage set vcore to 662500

 2159 12:40:32.982928  Read voltage for 1200, 2

 2160 12:40:32.983008  Vio18 = 0

 2161 12:40:32.983087  Vcore = 662500

 2162 12:40:32.986600  Vdram = 0

 2163 12:40:32.986685  Vddq = 0

 2164 12:40:32.986750  Vmddr = 0

 2165 12:40:32.993058  [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0

 2166 12:40:32.996256  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 2167 12:40:33.000094  MEM_TYPE=3, freq_sel=15

 2168 12:40:33.003324  sv_algorithm_assistance_LP4_1600 

 2169 12:40:33.006504  ============ PULL DRAM RESETB DOWN ============

 2170 12:40:33.009991  ========== PULL DRAM RESETB DOWN end =========

 2171 12:40:33.016969  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2172 12:40:33.020085  =================================== 

 2173 12:40:33.020222  LPDDR4 DRAM CONFIGURATION

 2174 12:40:33.023113  =================================== 

 2175 12:40:33.026751  EX_ROW_EN[0]    = 0x0

 2176 12:40:33.030263  EX_ROW_EN[1]    = 0x0

 2177 12:40:33.030379  LP4Y_EN      = 0x0

 2178 12:40:33.033151  WORK_FSP     = 0x0

 2179 12:40:33.033242  WL           = 0x4

 2180 12:40:33.037048  RL           = 0x4

 2181 12:40:33.037138  BL           = 0x2

 2182 12:40:33.040002  RPST         = 0x0

 2183 12:40:33.040086  RD_PRE       = 0x0

 2184 12:40:33.043008  WR_PRE       = 0x1

 2185 12:40:33.043086  WR_PST       = 0x0

 2186 12:40:33.046801  DBI_WR       = 0x0

 2187 12:40:33.046916  DBI_RD       = 0x0

 2188 12:40:33.049929  OTF          = 0x1

 2189 12:40:33.053142  =================================== 

 2190 12:40:33.056414  =================================== 

 2191 12:40:33.056534  ANA top config

 2192 12:40:33.060032  =================================== 

 2193 12:40:33.063195  DLL_ASYNC_EN            =  0

 2194 12:40:33.066813  ALL_SLAVE_EN            =  0

 2195 12:40:33.066921  NEW_RANK_MODE           =  1

 2196 12:40:33.070197  DLL_IDLE_MODE           =  1

 2197 12:40:33.073029  LP45_APHY_COMB_EN       =  1

 2198 12:40:33.076872  TX_ODT_DIS              =  1

 2199 12:40:33.079917  NEW_8X_MODE             =  1

 2200 12:40:33.083379  =================================== 

 2201 12:40:33.086387  =================================== 

 2202 12:40:33.086500  data_rate                  = 2400

 2203 12:40:33.090135  CKR                        = 1

 2204 12:40:33.093176  DQ_P2S_RATIO               = 8

 2205 12:40:33.096220  =================================== 

 2206 12:40:33.100155  CA_P2S_RATIO               = 8

 2207 12:40:33.103320  DQ_CA_OPEN                 = 0

 2208 12:40:33.106474  DQ_SEMI_OPEN               = 0

 2209 12:40:33.106585  CA_SEMI_OPEN               = 0

 2210 12:40:33.109731  CA_FULL_RATE               = 0

 2211 12:40:33.113668  DQ_CKDIV4_EN               = 0

 2212 12:40:33.116882  CA_CKDIV4_EN               = 0

 2213 12:40:33.120063  CA_PREDIV_EN               = 0

 2214 12:40:33.123292  PH8_DLY                    = 17

 2215 12:40:33.123401  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 2216 12:40:33.126543  DQ_AAMCK_DIV               = 4

 2217 12:40:33.129686  CA_AAMCK_DIV               = 4

 2218 12:40:33.133182  CA_ADMCK_DIV               = 4

 2219 12:40:33.136596  DQ_TRACK_CA_EN             = 0

 2220 12:40:33.140165  CA_PICK                    = 1200

 2221 12:40:33.140278  CA_MCKIO                   = 1200

 2222 12:40:33.143477  MCKIO_SEMI                 = 0

 2223 12:40:33.146667  PLL_FREQ                   = 2366

 2224 12:40:33.150261  DQ_UI_PI_RATIO             = 32

 2225 12:40:33.153503  CA_UI_PI_RATIO             = 0

 2226 12:40:33.156722  =================================== 

 2227 12:40:33.159933  =================================== 

 2228 12:40:33.163125  memory_type:LPDDR4         

 2229 12:40:33.163236  GP_NUM     : 10       

 2230 12:40:33.166933  SRAM_EN    : 1       

 2231 12:40:33.167041  MD32_EN    : 0       

 2232 12:40:33.170083  =================================== 

 2233 12:40:33.173750  [ANA_INIT] >>>>>>>>>>>>>> 

 2234 12:40:33.176969  <<<<<< [CONFIGURE PHASE]: ANA_TX

 2235 12:40:33.180466  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 2236 12:40:33.183492  =================================== 

 2237 12:40:33.187030  data_rate = 2400,PCW = 0X5b00

 2238 12:40:33.190081  =================================== 

 2239 12:40:33.193738  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 2240 12:40:33.196852  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 2241 12:40:33.203853  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 2242 12:40:33.207056  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 2243 12:40:33.210311  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 2244 12:40:33.213643  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 2245 12:40:33.216789  [ANA_INIT] flow start 

 2246 12:40:33.220658  [ANA_INIT] PLL >>>>>>>> 

 2247 12:40:33.220746  [ANA_INIT] PLL <<<<<<<< 

 2248 12:40:33.223926  [ANA_INIT] MIDPI >>>>>>>> 

 2249 12:40:33.227117  [ANA_INIT] MIDPI <<<<<<<< 

 2250 12:40:33.227194  [ANA_INIT] DLL >>>>>>>> 

 2251 12:40:33.230323  [ANA_INIT] DLL <<<<<<<< 

 2252 12:40:33.234117  [ANA_INIT] flow end 

 2253 12:40:33.237427  ============ LP4 DIFF to SE enter ============

 2254 12:40:33.240608  ============ LP4 DIFF to SE exit  ============

 2255 12:40:33.244216  [ANA_INIT] <<<<<<<<<<<<< 

 2256 12:40:33.247134  [Flow] Enable top DCM control >>>>> 

 2257 12:40:33.250746  [Flow] Enable top DCM control <<<<< 

 2258 12:40:33.253726  Enable DLL master slave shuffle 

 2259 12:40:33.257373  ============================================================== 

 2260 12:40:33.261003  Gating Mode config

 2261 12:40:33.267428  ============================================================== 

 2262 12:40:33.267514  Config description: 

 2263 12:40:33.277579  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 2264 12:40:33.283886  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 2265 12:40:33.287570  SELPH_MODE            0: By rank         1: By Phase 

 2266 12:40:33.294259  ============================================================== 

 2267 12:40:33.297711  GAT_TRACK_EN                 =  1

 2268 12:40:33.300534  RX_GATING_MODE               =  2

 2269 12:40:33.304288  RX_GATING_TRACK_MODE         =  2

 2270 12:40:33.307229  SELPH_MODE                   =  1

 2271 12:40:33.310771  PICG_EARLY_EN                =  1

 2272 12:40:33.314024  VALID_LAT_VALUE              =  1

 2273 12:40:33.317192  ============================================================== 

 2274 12:40:33.321083  Enter into Gating configuration >>>> 

 2275 12:40:33.324249  Exit from Gating configuration <<<< 

 2276 12:40:33.327467  Enter into  DVFS_PRE_config >>>>> 

 2277 12:40:33.337763  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 2278 12:40:33.340960  Exit from  DVFS_PRE_config <<<<< 

 2279 12:40:33.344184  Enter into PICG configuration >>>> 

 2280 12:40:33.347447  Exit from PICG configuration <<<< 

 2281 12:40:33.350771  [RX_INPUT] configuration >>>>> 

 2282 12:40:33.354175  [RX_INPUT] configuration <<<<< 

 2283 12:40:33.357607  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 2284 12:40:33.364316  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 2285 12:40:33.370962  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 2286 12:40:33.377369  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 2287 12:40:33.384527  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 2288 12:40:33.387806  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 2289 12:40:33.394547  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 2290 12:40:33.397618  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 2291 12:40:33.400993  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 2292 12:40:33.404116  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 2293 12:40:33.411193  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 2294 12:40:33.414401  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2295 12:40:33.417856  =================================== 

 2296 12:40:33.421035  LPDDR4 DRAM CONFIGURATION

 2297 12:40:33.424395  =================================== 

 2298 12:40:33.424481  EX_ROW_EN[0]    = 0x0

 2299 12:40:33.427697  EX_ROW_EN[1]    = 0x0

 2300 12:40:33.427782  LP4Y_EN      = 0x0

 2301 12:40:33.430879  WORK_FSP     = 0x0

 2302 12:40:33.430964  WL           = 0x4

 2303 12:40:33.434170  RL           = 0x4

 2304 12:40:33.434256  BL           = 0x2

 2305 12:40:33.437996  RPST         = 0x0

 2306 12:40:33.438080  RD_PRE       = 0x0

 2307 12:40:33.441230  WR_PRE       = 0x1

 2308 12:40:33.441314  WR_PST       = 0x0

 2309 12:40:33.444487  DBI_WR       = 0x0

 2310 12:40:33.444572  DBI_RD       = 0x0

 2311 12:40:33.447710  OTF          = 0x1

 2312 12:40:33.450923  =================================== 

 2313 12:40:33.454201  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 2314 12:40:33.458015  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 2315 12:40:33.464666  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2316 12:40:33.467558  =================================== 

 2317 12:40:33.467671  LPDDR4 DRAM CONFIGURATION

 2318 12:40:33.471170  =================================== 

 2319 12:40:33.474217  EX_ROW_EN[0]    = 0x10

 2320 12:40:33.477823  EX_ROW_EN[1]    = 0x0

 2321 12:40:33.477936  LP4Y_EN      = 0x0

 2322 12:40:33.481400  WORK_FSP     = 0x0

 2323 12:40:33.481510  WL           = 0x4

 2324 12:40:33.484466  RL           = 0x4

 2325 12:40:33.484570  BL           = 0x2

 2326 12:40:33.487865  RPST         = 0x0

 2327 12:40:33.487951  RD_PRE       = 0x0

 2328 12:40:33.490963  WR_PRE       = 0x1

 2329 12:40:33.491071  WR_PST       = 0x0

 2330 12:40:33.494188  DBI_WR       = 0x0

 2331 12:40:33.494292  DBI_RD       = 0x0

 2332 12:40:33.497874  OTF          = 0x1

 2333 12:40:33.501194  =================================== 

 2334 12:40:33.507591  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 2335 12:40:33.507721  ==

 2336 12:40:33.511190  Dram Type= 6, Freq= 0, CH_0, rank 0

 2337 12:40:33.514691  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2338 12:40:33.514778  ==

 2339 12:40:33.517742  [Duty_Offset_Calibration]

 2340 12:40:33.517860  	B0:2	B1:1	CA:1

 2341 12:40:33.517960  

 2342 12:40:33.521141  [DutyScan_Calibration_Flow] k_type=0

 2343 12:40:33.530899  

 2344 12:40:33.531020  ==CLK 0==

 2345 12:40:33.534701  Final CLK duty delay cell = 0

 2346 12:40:33.537437  [0] MAX Duty = 5218%(X100), DQS PI = 24

 2347 12:40:33.541156  [0] MIN Duty = 4875%(X100), DQS PI = 0

 2348 12:40:33.541270  [0] AVG Duty = 5046%(X100)

 2349 12:40:33.544403  

 2350 12:40:33.544505  CH0 CLK Duty spec in!! Max-Min= 343%

 2351 12:40:33.550850  [DutyScan_Calibration_Flow] ====Done====

 2352 12:40:33.550969  

 2353 12:40:33.554060  [DutyScan_Calibration_Flow] k_type=1

 2354 12:40:33.568924  

 2355 12:40:33.569047  ==DQS 0 ==

 2356 12:40:33.571854  Final DQS duty delay cell = -4

 2357 12:40:33.575424  [-4] MAX Duty = 5156%(X100), DQS PI = 24

 2358 12:40:33.579004  [-4] MIN Duty = 4782%(X100), DQS PI = 0

 2359 12:40:33.582229  [-4] AVG Duty = 4969%(X100)

 2360 12:40:33.582332  

 2361 12:40:33.582418  ==DQS 1 ==

 2362 12:40:33.585689  Final DQS duty delay cell = -4

 2363 12:40:33.588769  [-4] MAX Duty = 4969%(X100), DQS PI = 0

 2364 12:40:33.591941  [-4] MIN Duty = 4844%(X100), DQS PI = 32

 2365 12:40:33.595926  [-4] AVG Duty = 4906%(X100)

 2366 12:40:33.596010  

 2367 12:40:33.599093  CH0 DQS 0 Duty spec in!! Max-Min= 374%

 2368 12:40:33.599176  

 2369 12:40:33.602142  CH0 DQS 1 Duty spec in!! Max-Min= 125%

 2370 12:40:33.605398  [DutyScan_Calibration_Flow] ====Done====

 2371 12:40:33.605483  

 2372 12:40:33.608594  [DutyScan_Calibration_Flow] k_type=3

 2373 12:40:33.625953  

 2374 12:40:33.626058  ==DQM 0 ==

 2375 12:40:33.629457  Final DQM duty delay cell = 0

 2376 12:40:33.632745  [0] MAX Duty = 5156%(X100), DQS PI = 32

 2377 12:40:33.635970  [0] MIN Duty = 4906%(X100), DQS PI = 56

 2378 12:40:33.639150  [0] AVG Duty = 5031%(X100)

 2379 12:40:33.639235  

 2380 12:40:33.639299  ==DQM 1 ==

 2381 12:40:33.642364  Final DQM duty delay cell = 0

 2382 12:40:33.645627  [0] MAX Duty = 5156%(X100), DQS PI = 60

 2383 12:40:33.649398  [0] MIN Duty = 5031%(X100), DQS PI = 34

 2384 12:40:33.652679  [0] AVG Duty = 5093%(X100)

 2385 12:40:33.652761  

 2386 12:40:33.655989  CH0 DQM 0 Duty spec in!! Max-Min= 250%

 2387 12:40:33.656072  

 2388 12:40:33.659475  CH0 DQM 1 Duty spec in!! Max-Min= 125%

 2389 12:40:33.662543  [DutyScan_Calibration_Flow] ====Done====

 2390 12:40:33.662626  

 2391 12:40:33.665763  [DutyScan_Calibration_Flow] k_type=2

 2392 12:40:33.682771  

 2393 12:40:33.682874  ==DQ 0 ==

 2394 12:40:33.685713  Final DQ duty delay cell = 0

 2395 12:40:33.689228  [0] MAX Duty = 5031%(X100), DQS PI = 24

 2396 12:40:33.692350  [0] MIN Duty = 4875%(X100), DQS PI = 0

 2397 12:40:33.692433  [0] AVG Duty = 4953%(X100)

 2398 12:40:33.692498  

 2399 12:40:33.695994  ==DQ 1 ==

 2400 12:40:33.699115  Final DQ duty delay cell = 0

 2401 12:40:33.702286  [0] MAX Duty = 5093%(X100), DQS PI = 44

 2402 12:40:33.706058  [0] MIN Duty = 4938%(X100), DQS PI = 36

 2403 12:40:33.706144  [0] AVG Duty = 5015%(X100)

 2404 12:40:33.706209  

 2405 12:40:33.709233  CH0 DQ 0 Duty spec in!! Max-Min= 156%

 2406 12:40:33.709316  

 2407 12:40:33.712510  CH0 DQ 1 Duty spec in!! Max-Min= 155%

 2408 12:40:33.719506  [DutyScan_Calibration_Flow] ====Done====

 2409 12:40:33.719589  ==

 2410 12:40:33.722796  Dram Type= 6, Freq= 0, CH_1, rank 0

 2411 12:40:33.725768  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2412 12:40:33.725850  ==

 2413 12:40:33.729388  [Duty_Offset_Calibration]

 2414 12:40:33.729470  	B0:1	B1:0	CA:0

 2415 12:40:33.729535  

 2416 12:40:33.732325  [DutyScan_Calibration_Flow] k_type=0

 2417 12:40:33.741394  

 2418 12:40:33.741481  ==CLK 0==

 2419 12:40:33.745047  Final CLK duty delay cell = -4

 2420 12:40:33.748006  [-4] MAX Duty = 5031%(X100), DQS PI = 20

 2421 12:40:33.751840  [-4] MIN Duty = 4907%(X100), DQS PI = 50

 2422 12:40:33.755150  [-4] AVG Duty = 4969%(X100)

 2423 12:40:33.755233  

 2424 12:40:33.758482  CH1 CLK Duty spec in!! Max-Min= 124%

 2425 12:40:33.761911  [DutyScan_Calibration_Flow] ====Done====

 2426 12:40:33.761993  

 2427 12:40:33.764941  [DutyScan_Calibration_Flow] k_type=1

 2428 12:40:33.780551  

 2429 12:40:33.780644  ==DQS 0 ==

 2430 12:40:33.784200  Final DQS duty delay cell = 0

 2431 12:40:33.787734  [0] MAX Duty = 5094%(X100), DQS PI = 24

 2432 12:40:33.790626  [0] MIN Duty = 4875%(X100), DQS PI = 0

 2433 12:40:33.790724  [0] AVG Duty = 4984%(X100)

 2434 12:40:33.794123  

 2435 12:40:33.794202  ==DQS 1 ==

 2436 12:40:33.797180  Final DQS duty delay cell = -4

 2437 12:40:33.801037  [-4] MAX Duty = 5000%(X100), DQS PI = 18

 2438 12:40:33.804187  [-4] MIN Duty = 4813%(X100), DQS PI = 8

 2439 12:40:33.807429  [-4] AVG Duty = 4906%(X100)

 2440 12:40:33.807514  

 2441 12:40:33.811105  CH1 DQS 0 Duty spec in!! Max-Min= 219%

 2442 12:40:33.811205  

 2443 12:40:33.814276  CH1 DQS 1 Duty spec in!! Max-Min= 187%

 2444 12:40:33.817482  [DutyScan_Calibration_Flow] ====Done====

 2445 12:40:33.817560  

 2446 12:40:33.820640  [DutyScan_Calibration_Flow] k_type=3

 2447 12:40:33.837426  

 2448 12:40:33.837527  ==DQM 0 ==

 2449 12:40:33.840543  Final DQM duty delay cell = 0

 2450 12:40:33.844038  [0] MAX Duty = 5156%(X100), DQS PI = 4

 2451 12:40:33.847094  [0] MIN Duty = 5031%(X100), DQS PI = 0

 2452 12:40:33.847226  [0] AVG Duty = 5093%(X100)

 2453 12:40:33.850793  

 2454 12:40:33.850880  ==DQM 1 ==

 2455 12:40:33.853912  Final DQM duty delay cell = 0

 2456 12:40:33.857286  [0] MAX Duty = 5031%(X100), DQS PI = 16

 2457 12:40:33.860510  [0] MIN Duty = 4907%(X100), DQS PI = 36

 2458 12:40:33.860592  [0] AVG Duty = 4969%(X100)

 2459 12:40:33.864484  

 2460 12:40:33.867467  CH1 DQM 0 Duty spec in!! Max-Min= 125%

 2461 12:40:33.867556  

 2462 12:40:33.870824  CH1 DQM 1 Duty spec in!! Max-Min= 124%

 2463 12:40:33.874109  [DutyScan_Calibration_Flow] ====Done====

 2464 12:40:33.874181  

 2465 12:40:33.877340  [DutyScan_Calibration_Flow] k_type=2

 2466 12:40:33.893024  

 2467 12:40:33.893109  ==DQ 0 ==

 2468 12:40:33.896534  Final DQ duty delay cell = -4

 2469 12:40:33.900094  [-4] MAX Duty = 5062%(X100), DQS PI = 8

 2470 12:40:33.903053  [-4] MIN Duty = 4938%(X100), DQS PI = 0

 2471 12:40:33.903139  [-4] AVG Duty = 5000%(X100)

 2472 12:40:33.906770  

 2473 12:40:33.906871  ==DQ 1 ==

 2474 12:40:33.909895  Final DQ duty delay cell = 0

 2475 12:40:33.912926  [0] MAX Duty = 5125%(X100), DQS PI = 20

 2476 12:40:33.916744  [0] MIN Duty = 4969%(X100), DQS PI = 12

 2477 12:40:33.916848  [0] AVG Duty = 5047%(X100)

 2478 12:40:33.916914  

 2479 12:40:33.920049  CH1 DQ 0 Duty spec in!! Max-Min= 124%

 2480 12:40:33.923305  

 2481 12:40:33.927011  CH1 DQ 1 Duty spec in!! Max-Min= 156%

 2482 12:40:33.930228  [DutyScan_Calibration_Flow] ====Done====

 2483 12:40:33.933502  nWR fixed to 30

 2484 12:40:33.933637  [ModeRegInit_LP4] CH0 RK0

 2485 12:40:33.936692  [ModeRegInit_LP4] CH0 RK1

 2486 12:40:33.939915  [ModeRegInit_LP4] CH1 RK0

 2487 12:40:33.943009  [ModeRegInit_LP4] CH1 RK1

 2488 12:40:33.943098  match AC timing 7

 2489 12:40:33.946412  dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1

 2490 12:40:33.952936  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 2491 12:40:33.956485  [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12

 2492 12:40:33.959997  [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25

 2493 12:40:33.966521  [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)

 2494 12:40:33.966613  ==

 2495 12:40:33.969657  Dram Type= 6, Freq= 0, CH_0, rank 0

 2496 12:40:33.972855  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2497 12:40:33.972937  ==

 2498 12:40:33.979923  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 2499 12:40:33.986528  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 2500 12:40:33.993679  [CA 0] Center 39 (8~70) winsize 63

 2501 12:40:33.996732  [CA 1] Center 39 (8~70) winsize 63

 2502 12:40:33.999813  [CA 2] Center 35 (5~66) winsize 62

 2503 12:40:34.003560  [CA 3] Center 34 (4~65) winsize 62

 2504 12:40:34.006722  [CA 4] Center 33 (3~64) winsize 62

 2505 12:40:34.010121  [CA 5] Center 32 (3~62) winsize 60

 2506 12:40:34.010207  

 2507 12:40:34.013857  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 2508 12:40:34.013942  

 2509 12:40:34.016793  [CATrainingPosCal] consider 1 rank data

 2510 12:40:34.020414  u2DelayCellTimex100 = 270/100 ps

 2511 12:40:34.023755  CA0 delay=39 (8~70),Diff = 7 PI (33 cell)

 2512 12:40:34.026974  CA1 delay=39 (8~70),Diff = 7 PI (33 cell)

 2513 12:40:34.029921  CA2 delay=35 (5~66),Diff = 3 PI (14 cell)

 2514 12:40:34.037083  CA3 delay=34 (4~65),Diff = 2 PI (9 cell)

 2515 12:40:34.040403  CA4 delay=33 (3~64),Diff = 1 PI (4 cell)

 2516 12:40:34.043751  CA5 delay=32 (3~62),Diff = 0 PI (0 cell)

 2517 12:40:34.043835  

 2518 12:40:34.046899  CA PerBit enable=1, Macro0, CA PI delay=32

 2519 12:40:34.046984  

 2520 12:40:34.050003  [CBTSetCACLKResult] CA Dly = 32

 2521 12:40:34.050088  CS Dly: 6 (0~37)

 2522 12:40:34.050155  ==

 2523 12:40:34.053444  Dram Type= 6, Freq= 0, CH_0, rank 1

 2524 12:40:34.060239  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2525 12:40:34.060324  ==

 2526 12:40:34.063823  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 2527 12:40:34.070112  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 2528 12:40:34.078956  [CA 0] Center 38 (8~69) winsize 62

 2529 12:40:34.082826  [CA 1] Center 38 (8~69) winsize 62

 2530 12:40:34.086064  [CA 2] Center 35 (4~66) winsize 63

 2531 12:40:34.089398  [CA 3] Center 34 (4~65) winsize 62

 2532 12:40:34.092610  [CA 4] Center 33 (3~64) winsize 62

 2533 12:40:34.095753  [CA 5] Center 32 (3~62) winsize 60

 2534 12:40:34.095838  

 2535 12:40:34.099582  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 2536 12:40:34.099664  

 2537 12:40:34.102748  [CATrainingPosCal] consider 2 rank data

 2538 12:40:34.105807  u2DelayCellTimex100 = 270/100 ps

 2539 12:40:34.109443  CA0 delay=38 (8~69),Diff = 6 PI (28 cell)

 2540 12:40:34.112539  CA1 delay=38 (8~69),Diff = 6 PI (28 cell)

 2541 12:40:34.116089  CA2 delay=35 (5~66),Diff = 3 PI (14 cell)

 2542 12:40:34.123037  CA3 delay=34 (4~65),Diff = 2 PI (9 cell)

 2543 12:40:34.125940  CA4 delay=33 (3~64),Diff = 1 PI (4 cell)

 2544 12:40:34.129606  CA5 delay=32 (3~62),Diff = 0 PI (0 cell)

 2545 12:40:34.129689  

 2546 12:40:34.132815  CA PerBit enable=1, Macro0, CA PI delay=32

 2547 12:40:34.132958  

 2548 12:40:34.135878  [CBTSetCACLKResult] CA Dly = 32

 2549 12:40:34.136020  CS Dly: 6 (0~38)

 2550 12:40:34.136086  

 2551 12:40:34.139215  ----->DramcWriteLeveling(PI) begin...

 2552 12:40:34.139301  ==

 2553 12:40:34.142501  Dram Type= 6, Freq= 0, CH_0, rank 0

 2554 12:40:34.149491  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2555 12:40:34.149575  ==

 2556 12:40:34.152620  Write leveling (Byte 0): 34 => 34

 2557 12:40:34.155896  Write leveling (Byte 1): 30 => 30

 2558 12:40:34.155979  DramcWriteLeveling(PI) end<-----

 2559 12:40:34.159589  

 2560 12:40:34.159673  ==

 2561 12:40:34.162716  Dram Type= 6, Freq= 0, CH_0, rank 0

 2562 12:40:34.165829  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2563 12:40:34.165940  ==

 2564 12:40:34.169456  [Gating] SW mode calibration

 2565 12:40:34.176001  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 2566 12:40:34.179685  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 2567 12:40:34.186550   0 15  0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)

 2568 12:40:34.189700   0 15  4 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)

 2569 12:40:34.192906   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2570 12:40:34.199405   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2571 12:40:34.202576   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2572 12:40:34.205846   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2573 12:40:34.212754   0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)

 2574 12:40:34.216441   0 15 28 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)

 2575 12:40:34.219401   1  0  0 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)

 2576 12:40:34.223096   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2577 12:40:34.230019   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2578 12:40:34.233046   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2579 12:40:34.236511   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2580 12:40:34.243227   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2581 12:40:34.246391   1  0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)

 2582 12:40:34.249899   1  0 28 | B1->B0 | 2f2f 4646 | 1 0 | (0 0) (0 0)

 2583 12:40:34.256092   1  1  0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)

 2584 12:40:34.259340   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2585 12:40:34.263029   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2586 12:40:34.269479   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2587 12:40:34.272771   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2588 12:40:34.276410   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2589 12:40:34.283003   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2590 12:40:34.285986   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 2591 12:40:34.289566   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 2592 12:40:34.296210   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2593 12:40:34.299403   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2594 12:40:34.303237   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2595 12:40:34.309825   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2596 12:40:34.313039   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2597 12:40:34.316305   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2598 12:40:34.319833   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2599 12:40:34.326654   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2600 12:40:34.329769   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2601 12:40:34.332950   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2602 12:40:34.339785   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2603 12:40:34.342951   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2604 12:40:34.346659   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2605 12:40:34.353509   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2606 12:40:34.356589   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 2607 12:40:34.359885   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 2608 12:40:34.363232  Total UI for P1: 0, mck2ui 16

 2609 12:40:34.366245  best dqsien dly found for B0: ( 1,  3, 28)

 2610 12:40:34.373243   1  4  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2611 12:40:34.373323  Total UI for P1: 0, mck2ui 16

 2612 12:40:34.376491  best dqsien dly found for B1: ( 1,  4,  0)

 2613 12:40:34.382890  best DQS0 dly(MCK, UI, PI) = (1, 3, 28)

 2614 12:40:34.386620  best DQS1 dly(MCK, UI, PI) = (1, 4, 0)

 2615 12:40:34.386698  

 2616 12:40:34.389728  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)

 2617 12:40:34.393266  best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)

 2618 12:40:34.396358  [Gating] SW calibration Done

 2619 12:40:34.396467  ==

 2620 12:40:34.399932  Dram Type= 6, Freq= 0, CH_0, rank 0

 2621 12:40:34.402942  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2622 12:40:34.403044  ==

 2623 12:40:34.403136  RX Vref Scan: 0

 2624 12:40:34.406950  

 2625 12:40:34.407063  RX Vref 0 -> 0, step: 1

 2626 12:40:34.407152  

 2627 12:40:34.410166  RX Delay -40 -> 252, step: 8

 2628 12:40:34.413475  iDelay=200, Bit 0, Center 119 (48 ~ 191) 144

 2629 12:40:34.416708  iDelay=200, Bit 1, Center 123 (48 ~ 199) 152

 2630 12:40:34.423068  iDelay=200, Bit 2, Center 119 (48 ~ 191) 144

 2631 12:40:34.426591  iDelay=200, Bit 3, Center 119 (48 ~ 191) 144

 2632 12:40:34.429967  iDelay=200, Bit 4, Center 119 (48 ~ 191) 144

 2633 12:40:34.433045  iDelay=200, Bit 5, Center 115 (48 ~ 183) 136

 2634 12:40:34.436727  iDelay=200, Bit 6, Center 127 (56 ~ 199) 144

 2635 12:40:34.443171  iDelay=200, Bit 7, Center 127 (56 ~ 199) 144

 2636 12:40:34.446376  iDelay=200, Bit 8, Center 99 (32 ~ 167) 136

 2637 12:40:34.450149  iDelay=200, Bit 9, Center 107 (40 ~ 175) 136

 2638 12:40:34.453208  iDelay=200, Bit 10, Center 115 (48 ~ 183) 136

 2639 12:40:34.456607  iDelay=200, Bit 11, Center 107 (40 ~ 175) 136

 2640 12:40:34.463002  iDelay=200, Bit 12, Center 119 (48 ~ 191) 144

 2641 12:40:34.466632  iDelay=200, Bit 13, Center 123 (56 ~ 191) 136

 2642 12:40:34.469772  iDelay=200, Bit 14, Center 123 (56 ~ 191) 136

 2643 12:40:34.473390  iDelay=200, Bit 15, Center 119 (48 ~ 191) 144

 2644 12:40:34.473498  ==

 2645 12:40:34.476596  Dram Type= 6, Freq= 0, CH_0, rank 0

 2646 12:40:34.482966  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2647 12:40:34.483093  ==

 2648 12:40:34.483160  DQS Delay:

 2649 12:40:34.483222  DQS0 = 0, DQS1 = 0

 2650 12:40:34.486848  DQM Delay:

 2651 12:40:34.486931  DQM0 = 121, DQM1 = 114

 2652 12:40:34.490056  DQ Delay:

 2653 12:40:34.493093  DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119

 2654 12:40:34.496715  DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127

 2655 12:40:34.499819  DQ8 =99, DQ9 =107, DQ10 =115, DQ11 =107

 2656 12:40:34.503473  DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119

 2657 12:40:34.503559  

 2658 12:40:34.503645  

 2659 12:40:34.503709  ==

 2660 12:40:34.506561  Dram Type= 6, Freq= 0, CH_0, rank 0

 2661 12:40:34.510065  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2662 12:40:34.510188  ==

 2663 12:40:34.510285  

 2664 12:40:34.510391  

 2665 12:40:34.513160  	TX Vref Scan disable

 2666 12:40:34.517074   == TX Byte 0 ==

 2667 12:40:34.520253  Update DQ  dly =852 (3 ,2, 20)  DQ  OEN =(2 ,7)

 2668 12:40:34.523453  Update DQM dly =852 (3 ,2, 20)  DQM OEN =(2 ,7)

 2669 12:40:34.526721   == TX Byte 1 ==

 2670 12:40:34.529797  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 2671 12:40:34.533427  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 2672 12:40:34.533564  ==

 2673 12:40:34.536917  Dram Type= 6, Freq= 0, CH_0, rank 0

 2674 12:40:34.540468  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2675 12:40:34.543393  ==

 2676 12:40:34.553998  TX Vref=22, minBit 0, minWin=24, winSum=402

 2677 12:40:34.557044  TX Vref=24, minBit 4, minWin=25, winSum=414

 2678 12:40:34.560811  TX Vref=26, minBit 2, minWin=25, winSum=419

 2679 12:40:34.564024  TX Vref=28, minBit 7, minWin=25, winSum=421

 2680 12:40:34.567177  TX Vref=30, minBit 0, minWin=26, winSum=424

 2681 12:40:34.570290  TX Vref=32, minBit 0, minWin=26, winSum=422

 2682 12:40:34.577115  [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 30

 2683 12:40:34.577250  

 2684 12:40:34.580337  Final TX Range 1 Vref 30

 2685 12:40:34.580443  

 2686 12:40:34.580554  ==

 2687 12:40:34.584354  Dram Type= 6, Freq= 0, CH_0, rank 0

 2688 12:40:34.587353  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2689 12:40:34.587462  ==

 2690 12:40:34.587571  

 2691 12:40:34.587671  

 2692 12:40:34.590542  	TX Vref Scan disable

 2693 12:40:34.593812   == TX Byte 0 ==

 2694 12:40:34.597575  Update DQ  dly =852 (3 ,2, 20)  DQ  OEN =(2 ,7)

 2695 12:40:34.600655  Update DQM dly =852 (3 ,2, 20)  DQM OEN =(2 ,7)

 2696 12:40:34.604244   == TX Byte 1 ==

 2697 12:40:34.607280  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 2698 12:40:34.610471  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 2699 12:40:34.610551  

 2700 12:40:34.614300  [DATLAT]

 2701 12:40:34.614390  Freq=1200, CH0 RK0

 2702 12:40:34.614468  

 2703 12:40:34.617345  DATLAT Default: 0xd

 2704 12:40:34.617427  0, 0xFFFF, sum = 0

 2705 12:40:34.620570  1, 0xFFFF, sum = 0

 2706 12:40:34.620642  2, 0xFFFF, sum = 0

 2707 12:40:34.623844  3, 0xFFFF, sum = 0

 2708 12:40:34.623927  4, 0xFFFF, sum = 0

 2709 12:40:34.627787  5, 0xFFFF, sum = 0

 2710 12:40:34.627866  6, 0xFFFF, sum = 0

 2711 12:40:34.630483  7, 0xFFFF, sum = 0

 2712 12:40:34.630566  8, 0xFFFF, sum = 0

 2713 12:40:34.634389  9, 0xFFFF, sum = 0

 2714 12:40:34.634473  10, 0xFFFF, sum = 0

 2715 12:40:34.637531  11, 0xFFFF, sum = 0

 2716 12:40:34.637604  12, 0x0, sum = 1

 2717 12:40:34.640554  13, 0x0, sum = 2

 2718 12:40:34.640629  14, 0x0, sum = 3

 2719 12:40:34.644044  15, 0x0, sum = 4

 2720 12:40:34.644126  best_step = 13

 2721 12:40:34.644191  

 2722 12:40:34.644251  ==

 2723 12:40:34.647523  Dram Type= 6, Freq= 0, CH_0, rank 0

 2724 12:40:34.654119  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2725 12:40:34.654218  ==

 2726 12:40:34.654299  RX Vref Scan: 1

 2727 12:40:34.654363  

 2728 12:40:34.657729  Set Vref Range= 32 -> 127

 2729 12:40:34.657810  

 2730 12:40:34.660796  RX Vref 32 -> 127, step: 1

 2731 12:40:34.660879  

 2732 12:40:34.663877  RX Delay -13 -> 252, step: 4

 2733 12:40:34.663975  

 2734 12:40:34.664041  Set Vref, RX VrefLevel [Byte0]: 32

 2735 12:40:34.667524                           [Byte1]: 32

 2736 12:40:34.671876  

 2737 12:40:34.671952  Set Vref, RX VrefLevel [Byte0]: 33

 2738 12:40:34.675652                           [Byte1]: 33

 2739 12:40:34.680068  

 2740 12:40:34.680153  Set Vref, RX VrefLevel [Byte0]: 34

 2741 12:40:34.683397                           [Byte1]: 34

 2742 12:40:34.687918  

 2743 12:40:34.687996  Set Vref, RX VrefLevel [Byte0]: 35

 2744 12:40:34.690936                           [Byte1]: 35

 2745 12:40:34.695441  

 2746 12:40:34.695524  Set Vref, RX VrefLevel [Byte0]: 36

 2747 12:40:34.699268                           [Byte1]: 36

 2748 12:40:34.703726  

 2749 12:40:34.703812  Set Vref, RX VrefLevel [Byte0]: 37

 2750 12:40:34.706935                           [Byte1]: 37

 2751 12:40:34.711235  

 2752 12:40:34.711323  Set Vref, RX VrefLevel [Byte0]: 38

 2753 12:40:34.714923                           [Byte1]: 38

 2754 12:40:34.719362  

 2755 12:40:34.719480  Set Vref, RX VrefLevel [Byte0]: 39

 2756 12:40:34.722438                           [Byte1]: 39

 2757 12:40:34.727536  

 2758 12:40:34.727617  Set Vref, RX VrefLevel [Byte0]: 40

 2759 12:40:34.730718                           [Byte1]: 40

 2760 12:40:34.735320  

 2761 12:40:34.735398  Set Vref, RX VrefLevel [Byte0]: 41

 2762 12:40:34.738530                           [Byte1]: 41

 2763 12:40:34.743125  

 2764 12:40:34.743213  Set Vref, RX VrefLevel [Byte0]: 42

 2765 12:40:34.746228                           [Byte1]: 42

 2766 12:40:34.751097  

 2767 12:40:34.751186  Set Vref, RX VrefLevel [Byte0]: 43

 2768 12:40:34.754306                           [Byte1]: 43

 2769 12:40:34.758509  

 2770 12:40:34.758625  Set Vref, RX VrefLevel [Byte0]: 44

 2771 12:40:34.762123                           [Byte1]: 44

 2772 12:40:34.766463  

 2773 12:40:34.766548  Set Vref, RX VrefLevel [Byte0]: 45

 2774 12:40:34.770154                           [Byte1]: 45

 2775 12:40:34.774721  

 2776 12:40:34.774799  Set Vref, RX VrefLevel [Byte0]: 46

 2777 12:40:34.777881                           [Byte1]: 46

 2778 12:40:34.782902  

 2779 12:40:34.782982  Set Vref, RX VrefLevel [Byte0]: 47

 2780 12:40:34.786083                           [Byte1]: 47

 2781 12:40:34.790215  

 2782 12:40:34.790297  Set Vref, RX VrefLevel [Byte0]: 48

 2783 12:40:34.793382                           [Byte1]: 48

 2784 12:40:34.798522  

 2785 12:40:34.798607  Set Vref, RX VrefLevel [Byte0]: 49

 2786 12:40:34.801751                           [Byte1]: 49

 2787 12:40:34.806175  

 2788 12:40:34.806294  Set Vref, RX VrefLevel [Byte0]: 50

 2789 12:40:34.809338                           [Byte1]: 50

 2790 12:40:34.813824  

 2791 12:40:34.813914  Set Vref, RX VrefLevel [Byte0]: 51

 2792 12:40:34.817065                           [Byte1]: 51

 2793 12:40:34.821968  

 2794 12:40:34.822057  Set Vref, RX VrefLevel [Byte0]: 52

 2795 12:40:34.825003                           [Byte1]: 52

 2796 12:40:34.829873  

 2797 12:40:34.829972  Set Vref, RX VrefLevel [Byte0]: 53

 2798 12:40:34.833149                           [Byte1]: 53

 2799 12:40:34.837573  

 2800 12:40:34.837681  Set Vref, RX VrefLevel [Byte0]: 54

 2801 12:40:34.840835                           [Byte1]: 54

 2802 12:40:34.845445  

 2803 12:40:34.845533  Set Vref, RX VrefLevel [Byte0]: 55

 2804 12:40:34.849195                           [Byte1]: 55

 2805 12:40:34.853457  

 2806 12:40:34.853537  Set Vref, RX VrefLevel [Byte0]: 56

 2807 12:40:34.856939                           [Byte1]: 56

 2808 12:40:34.861330  

 2809 12:40:34.861405  Set Vref, RX VrefLevel [Byte0]: 57

 2810 12:40:34.864953                           [Byte1]: 57

 2811 12:40:34.869279  

 2812 12:40:34.869367  Set Vref, RX VrefLevel [Byte0]: 58

 2813 12:40:34.872894                           [Byte1]: 58

 2814 12:40:34.876920  

 2815 12:40:34.876997  Set Vref, RX VrefLevel [Byte0]: 59

 2816 12:40:34.880871                           [Byte1]: 59

 2817 12:40:34.885212  

 2818 12:40:34.885295  Set Vref, RX VrefLevel [Byte0]: 60

 2819 12:40:34.888254                           [Byte1]: 60

 2820 12:40:34.893398  

 2821 12:40:34.893482  Set Vref, RX VrefLevel [Byte0]: 61

 2822 12:40:34.896474                           [Byte1]: 61

 2823 12:40:34.900794  

 2824 12:40:34.900900  Set Vref, RX VrefLevel [Byte0]: 62

 2825 12:40:34.904135                           [Byte1]: 62

 2826 12:40:34.908535  

 2827 12:40:34.908622  Set Vref, RX VrefLevel [Byte0]: 63

 2828 12:40:34.912405                           [Byte1]: 63

 2829 12:40:34.916810  

 2830 12:40:34.916916  Set Vref, RX VrefLevel [Byte0]: 64

 2831 12:40:34.920076                           [Byte1]: 64

 2832 12:40:34.924639  

 2833 12:40:34.924727  Set Vref, RX VrefLevel [Byte0]: 65

 2834 12:40:34.927789                           [Byte1]: 65

 2835 12:40:34.932625  

 2836 12:40:34.932733  Set Vref, RX VrefLevel [Byte0]: 66

 2837 12:40:34.935563                           [Byte1]: 66

 2838 12:40:34.940467  

 2839 12:40:34.940543  Set Vref, RX VrefLevel [Byte0]: 67

 2840 12:40:34.943674                           [Byte1]: 67

 2841 12:40:34.948198  

 2842 12:40:34.948305  Set Vref, RX VrefLevel [Byte0]: 68

 2843 12:40:34.951459                           [Byte1]: 68

 2844 12:40:34.955989  

 2845 12:40:34.956072  Set Vref, RX VrefLevel [Byte0]: 69

 2846 12:40:34.959670                           [Byte1]: 69

 2847 12:40:34.963678  

 2848 12:40:34.963760  Final RX Vref Byte 0 = 53 to rank0

 2849 12:40:34.967045  Final RX Vref Byte 1 = 47 to rank0

 2850 12:40:34.970880  Final RX Vref Byte 0 = 53 to rank1

 2851 12:40:34.974050  Final RX Vref Byte 1 = 47 to rank1==

 2852 12:40:34.977534  Dram Type= 6, Freq= 0, CH_0, rank 0

 2853 12:40:34.984070  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2854 12:40:34.984191  ==

 2855 12:40:34.984294  DQS Delay:

 2856 12:40:34.984388  DQS0 = 0, DQS1 = 0

 2857 12:40:34.987162  DQM Delay:

 2858 12:40:34.987236  DQM0 = 120, DQM1 = 111

 2859 12:40:34.991128  DQ Delay:

 2860 12:40:34.993945  DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118

 2861 12:40:34.997778  DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =128

 2862 12:40:35.000881  DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =104

 2863 12:40:35.003864  DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =120

 2864 12:40:35.003953  

 2865 12:40:35.004030  

 2866 12:40:35.010976  [DQSOSCAuto] RK0, (LSB)MR18= 0x1711, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps

 2867 12:40:35.014221  CH0 RK0: MR19=404, MR18=1711

 2868 12:40:35.021099  CH0_RK0: MR19=0x404, MR18=0x1711, DQSOSC=401, MR23=63, INC=40, DEC=27

 2869 12:40:35.021188  

 2870 12:40:35.024294  ----->DramcWriteLeveling(PI) begin...

 2871 12:40:35.024392  ==

 2872 12:40:35.027585  Dram Type= 6, Freq= 0, CH_0, rank 1

 2873 12:40:35.030807  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2874 12:40:35.030891  ==

 2875 12:40:35.034744  Write leveling (Byte 0): 34 => 34

 2876 12:40:35.037935  Write leveling (Byte 1): 29 => 29

 2877 12:40:35.041073  DramcWriteLeveling(PI) end<-----

 2878 12:40:35.041167  

 2879 12:40:35.041235  ==

 2880 12:40:35.044086  Dram Type= 6, Freq= 0, CH_0, rank 1

 2881 12:40:35.047598  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2882 12:40:35.050924  ==

 2883 12:40:35.051033  [Gating] SW mode calibration

 2884 12:40:35.061256  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 2885 12:40:35.064316  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 2886 12:40:35.067519   0 15  0 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 0)

 2887 12:40:35.074344   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2888 12:40:35.077657   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2889 12:40:35.081127   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2890 12:40:35.087973   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2891 12:40:35.091039   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2892 12:40:35.094370   0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2893 12:40:35.101302   0 15 28 | B1->B0 | 3030 2e2e | 0 1 | (0 1) (1 0)

 2894 12:40:35.104315   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2895 12:40:35.108036   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2896 12:40:35.114165   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2897 12:40:35.117505   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2898 12:40:35.121277   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2899 12:40:35.127498   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2900 12:40:35.131407   1  0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 2901 12:40:35.134734   1  0 28 | B1->B0 | 3e3e 4141 | 0 1 | (0 0) (0 0)

 2902 12:40:35.137775   1  1  0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)

 2903 12:40:35.144152   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2904 12:40:35.147993   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2905 12:40:35.151073   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2906 12:40:35.157450   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2907 12:40:35.161325   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2908 12:40:35.164487   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2909 12:40:35.170948   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 2910 12:40:35.174699   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 2911 12:40:35.177842   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2912 12:40:35.184601   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2913 12:40:35.188316   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2914 12:40:35.191063   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2915 12:40:35.197985   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2916 12:40:35.201376   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2917 12:40:35.204892   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2918 12:40:35.211466   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2919 12:40:35.214428   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2920 12:40:35.218007   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2921 12:40:35.220997   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2922 12:40:35.227931   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2923 12:40:35.231671   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2924 12:40:35.234847   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2925 12:40:35.241348   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 2926 12:40:35.244549   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2927 12:40:35.247855  Total UI for P1: 0, mck2ui 16

 2928 12:40:35.251537  best dqsien dly found for B0: ( 1,  3, 28)

 2929 12:40:35.254812  Total UI for P1: 0, mck2ui 16

 2930 12:40:35.258004  best dqsien dly found for B1: ( 1,  3, 28)

 2931 12:40:35.261114  best DQS0 dly(MCK, UI, PI) = (1, 3, 28)

 2932 12:40:35.264337  best DQS1 dly(MCK, UI, PI) = (1, 3, 28)

 2933 12:40:35.264437  

 2934 12:40:35.268286  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)

 2935 12:40:35.271435  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)

 2936 12:40:35.274691  [Gating] SW calibration Done

 2937 12:40:35.274765  ==

 2938 12:40:35.277801  Dram Type= 6, Freq= 0, CH_0, rank 1

 2939 12:40:35.281423  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2940 12:40:35.281516  ==

 2941 12:40:35.284766  RX Vref Scan: 0

 2942 12:40:35.284892  

 2943 12:40:35.287934  RX Vref 0 -> 0, step: 1

 2944 12:40:35.288009  

 2945 12:40:35.288072  RX Delay -40 -> 252, step: 8

 2946 12:40:35.294654  iDelay=200, Bit 0, Center 119 (48 ~ 191) 144

 2947 12:40:35.298274  iDelay=200, Bit 1, Center 119 (48 ~ 191) 144

 2948 12:40:35.301404  iDelay=200, Bit 2, Center 119 (48 ~ 191) 144

 2949 12:40:35.304955  iDelay=200, Bit 3, Center 119 (48 ~ 191) 144

 2950 12:40:35.308144  iDelay=200, Bit 4, Center 127 (56 ~ 199) 144

 2951 12:40:35.314720  iDelay=200, Bit 5, Center 119 (48 ~ 191) 144

 2952 12:40:35.318132  iDelay=200, Bit 6, Center 127 (56 ~ 199) 144

 2953 12:40:35.321169  iDelay=200, Bit 7, Center 127 (56 ~ 199) 144

 2954 12:40:35.325125  iDelay=200, Bit 8, Center 99 (32 ~ 167) 136

 2955 12:40:35.328180  iDelay=200, Bit 9, Center 103 (32 ~ 175) 144

 2956 12:40:35.335053  iDelay=200, Bit 10, Center 111 (48 ~ 175) 128

 2957 12:40:35.338335  iDelay=200, Bit 11, Center 107 (40 ~ 175) 136

 2958 12:40:35.341484  iDelay=200, Bit 12, Center 115 (48 ~ 183) 136

 2959 12:40:35.344879  iDelay=200, Bit 13, Center 119 (48 ~ 191) 144

 2960 12:40:35.347980  iDelay=200, Bit 14, Center 123 (56 ~ 191) 136

 2961 12:40:35.355108  iDelay=200, Bit 15, Center 119 (56 ~ 183) 128

 2962 12:40:35.355216  ==

 2963 12:40:35.358177  Dram Type= 6, Freq= 0, CH_0, rank 1

 2964 12:40:35.361408  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2965 12:40:35.361493  ==

 2966 12:40:35.361559  DQS Delay:

 2967 12:40:35.364667  DQS0 = 0, DQS1 = 0

 2968 12:40:35.364782  DQM Delay:

 2969 12:40:35.368397  DQM0 = 122, DQM1 = 112

 2970 12:40:35.368486  DQ Delay:

 2971 12:40:35.371681  DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119

 2972 12:40:35.374864  DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127

 2973 12:40:35.378121  DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107

 2974 12:40:35.381283  DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119

 2975 12:40:35.381361  

 2976 12:40:35.381425  

 2977 12:40:35.384440  ==

 2978 12:40:35.388326  Dram Type= 6, Freq= 0, CH_0, rank 1

 2979 12:40:35.391453  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2980 12:40:35.391538  ==

 2981 12:40:35.391604  

 2982 12:40:35.391666  

 2983 12:40:35.394633  	TX Vref Scan disable

 2984 12:40:35.394718   == TX Byte 0 ==

 2985 12:40:35.398232  Update DQ  dly =853 (3 ,2, 21)  DQ  OEN =(2 ,7)

 2986 12:40:35.404718  Update DQM dly =853 (3 ,2, 21)  DQM OEN =(2 ,7)

 2987 12:40:35.404837   == TX Byte 1 ==

 2988 12:40:35.407668  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 2989 12:40:35.414506  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 2990 12:40:35.414608  ==

 2991 12:40:35.417626  Dram Type= 6, Freq= 0, CH_0, rank 1

 2992 12:40:35.421298  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2993 12:40:35.421378  ==

 2994 12:40:35.433666  TX Vref=22, minBit 1, minWin=24, winSum=416

 2995 12:40:35.436978  TX Vref=24, minBit 0, minWin=26, winSum=423

 2996 12:40:35.440696  TX Vref=26, minBit 0, minWin=26, winSum=429

 2997 12:40:35.443849  TX Vref=28, minBit 3, minWin=25, winSum=430

 2998 12:40:35.447046  TX Vref=30, minBit 1, minWin=26, winSum=430

 2999 12:40:35.450393  TX Vref=32, minBit 5, minWin=25, winSum=425

 3000 12:40:35.457441  [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 30

 3001 12:40:35.457534  

 3002 12:40:35.460535  Final TX Range 1 Vref 30

 3003 12:40:35.460629  

 3004 12:40:35.460696  ==

 3005 12:40:35.464514  Dram Type= 6, Freq= 0, CH_0, rank 1

 3006 12:40:35.467553  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3007 12:40:35.467667  ==

 3008 12:40:35.467762  

 3009 12:40:35.467853  

 3010 12:40:35.470677  	TX Vref Scan disable

 3011 12:40:35.473789   == TX Byte 0 ==

 3012 12:40:35.477661  Update DQ  dly =853 (3 ,2, 21)  DQ  OEN =(2 ,7)

 3013 12:40:35.480932  Update DQM dly =853 (3 ,2, 21)  DQM OEN =(2 ,7)

 3014 12:40:35.484107   == TX Byte 1 ==

 3015 12:40:35.487246  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 3016 12:40:35.490536  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 3017 12:40:35.490621  

 3018 12:40:35.494339  [DATLAT]

 3019 12:40:35.494449  Freq=1200, CH0 RK1

 3020 12:40:35.494543  

 3021 12:40:35.497493  DATLAT Default: 0xd

 3022 12:40:35.497577  0, 0xFFFF, sum = 0

 3023 12:40:35.500560  1, 0xFFFF, sum = 0

 3024 12:40:35.500645  2, 0xFFFF, sum = 0

 3025 12:40:35.503656  3, 0xFFFF, sum = 0

 3026 12:40:35.503744  4, 0xFFFF, sum = 0

 3027 12:40:35.507345  5, 0xFFFF, sum = 0

 3028 12:40:35.507445  6, 0xFFFF, sum = 0

 3029 12:40:35.510640  7, 0xFFFF, sum = 0

 3030 12:40:35.510733  8, 0xFFFF, sum = 0

 3031 12:40:35.514401  9, 0xFFFF, sum = 0

 3032 12:40:35.514486  10, 0xFFFF, sum = 0

 3033 12:40:35.517359  11, 0xFFFF, sum = 0

 3034 12:40:35.520757  12, 0x0, sum = 1

 3035 12:40:35.520860  13, 0x0, sum = 2

 3036 12:40:35.520930  14, 0x0, sum = 3

 3037 12:40:35.523987  15, 0x0, sum = 4

 3038 12:40:35.524067  best_step = 13

 3039 12:40:35.524140  

 3040 12:40:35.524201  ==

 3041 12:40:35.527379  Dram Type= 6, Freq= 0, CH_0, rank 1

 3042 12:40:35.533961  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3043 12:40:35.534058  ==

 3044 12:40:35.534126  RX Vref Scan: 0

 3045 12:40:35.534199  

 3046 12:40:35.537039  RX Vref 0 -> 0, step: 1

 3047 12:40:35.537148  

 3048 12:40:35.540883  RX Delay -13 -> 252, step: 4

 3049 12:40:35.543952  iDelay=195, Bit 0, Center 118 (51 ~ 186) 136

 3050 12:40:35.547505  iDelay=195, Bit 1, Center 120 (55 ~ 186) 132

 3051 12:40:35.554169  iDelay=195, Bit 2, Center 118 (51 ~ 186) 136

 3052 12:40:35.557270  iDelay=195, Bit 3, Center 118 (51 ~ 186) 136

 3053 12:40:35.560473  iDelay=195, Bit 4, Center 122 (55 ~ 190) 136

 3054 12:40:35.563821  iDelay=195, Bit 5, Center 116 (51 ~ 182) 132

 3055 12:40:35.567617  iDelay=195, Bit 6, Center 126 (59 ~ 194) 136

 3056 12:40:35.573999  iDelay=195, Bit 7, Center 128 (63 ~ 194) 132

 3057 12:40:35.577242  iDelay=195, Bit 8, Center 100 (35 ~ 166) 132

 3058 12:40:35.580981  iDelay=195, Bit 9, Center 96 (31 ~ 162) 132

 3059 12:40:35.584222  iDelay=195, Bit 10, Center 110 (47 ~ 174) 128

 3060 12:40:35.587552  iDelay=195, Bit 11, Center 102 (39 ~ 166) 128

 3061 12:40:35.590692  iDelay=195, Bit 12, Center 114 (51 ~ 178) 128

 3062 12:40:35.597710  iDelay=195, Bit 13, Center 114 (51 ~ 178) 128

 3063 12:40:35.600847  iDelay=195, Bit 14, Center 122 (59 ~ 186) 128

 3064 12:40:35.604575  iDelay=195, Bit 15, Center 118 (55 ~ 182) 128

 3065 12:40:35.604649  ==

 3066 12:40:35.607634  Dram Type= 6, Freq= 0, CH_0, rank 1

 3067 12:40:35.610836  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3068 12:40:35.610924  ==

 3069 12:40:35.614234  DQS Delay:

 3070 12:40:35.614321  DQS0 = 0, DQS1 = 0

 3071 12:40:35.617823  DQM Delay:

 3072 12:40:35.617909  DQM0 = 120, DQM1 = 109

 3073 12:40:35.620974  DQ Delay:

 3074 12:40:35.624107  DQ0 =118, DQ1 =120, DQ2 =118, DQ3 =118

 3075 12:40:35.627481  DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =128

 3076 12:40:35.631106  DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =102

 3077 12:40:35.634496  DQ12 =114, DQ13 =114, DQ14 =122, DQ15 =118

 3078 12:40:35.634584  

 3079 12:40:35.634650  

 3080 12:40:35.641133  [DQSOSCAuto] RK1, (LSB)MR18= 0xff0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 404 ps

 3081 12:40:35.644436  CH0 RK1: MR19=403, MR18=FF0

 3082 12:40:35.651310  CH0_RK1: MR19=0x403, MR18=0xFF0, DQSOSC=404, MR23=63, INC=40, DEC=26

 3083 12:40:35.654863  [RxdqsGatingPostProcess] freq 1200

 3084 12:40:35.657902  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 3085 12:40:35.661149  best DQS0 dly(2T, 0.5T) = (0, 11)

 3086 12:40:35.664401  best DQS1 dly(2T, 0.5T) = (0, 12)

 3087 12:40:35.668152  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3088 12:40:35.671473  best DQS1 P1 dly(2T, 0.5T) = (1, 0)

 3089 12:40:35.674560  best DQS0 dly(2T, 0.5T) = (0, 11)

 3090 12:40:35.677895  best DQS1 dly(2T, 0.5T) = (0, 11)

 3091 12:40:35.681105  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3092 12:40:35.684761  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3093 12:40:35.688116  Pre-setting of DQS Precalculation

 3094 12:40:35.691147  [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13

 3095 12:40:35.691231  ==

 3096 12:40:35.694928  Dram Type= 6, Freq= 0, CH_1, rank 0

 3097 12:40:35.701177  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3098 12:40:35.701263  ==

 3099 12:40:35.704949  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3100 12:40:35.711288  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37

 3101 12:40:35.719895  [CA 0] Center 37 (7~68) winsize 62

 3102 12:40:35.723145  [CA 1] Center 37 (7~68) winsize 62

 3103 12:40:35.726442  [CA 2] Center 35 (5~65) winsize 61

 3104 12:40:35.729814  [CA 3] Center 34 (4~64) winsize 61

 3105 12:40:35.733380  [CA 4] Center 34 (4~64) winsize 61

 3106 12:40:35.736867  [CA 5] Center 33 (3~63) winsize 61

 3107 12:40:35.736952  

 3108 12:40:35.739923  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 3109 12:40:35.740008  

 3110 12:40:35.742885  [CATrainingPosCal] consider 1 rank data

 3111 12:40:35.746553  u2DelayCellTimex100 = 270/100 ps

 3112 12:40:35.749476  CA0 delay=37 (7~68),Diff = 4 PI (19 cell)

 3113 12:40:35.756451  CA1 delay=37 (7~68),Diff = 4 PI (19 cell)

 3114 12:40:35.759578  CA2 delay=35 (5~65),Diff = 2 PI (9 cell)

 3115 12:40:35.763013  CA3 delay=34 (4~64),Diff = 1 PI (4 cell)

 3116 12:40:35.766525  CA4 delay=34 (4~64),Diff = 1 PI (4 cell)

 3117 12:40:35.769742  CA5 delay=33 (3~63),Diff = 0 PI (0 cell)

 3118 12:40:35.769828  

 3119 12:40:35.773038  CA PerBit enable=1, Macro0, CA PI delay=33

 3120 12:40:35.773136  

 3121 12:40:35.776216  [CBTSetCACLKResult] CA Dly = 33

 3122 12:40:35.776302  CS Dly: 7 (0~38)

 3123 12:40:35.779411  ==

 3124 12:40:35.779497  Dram Type= 6, Freq= 0, CH_1, rank 1

 3125 12:40:35.786452  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3126 12:40:35.786555  ==

 3127 12:40:35.789621  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3128 12:40:35.796186  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 3129 12:40:35.805570  [CA 0] Center 37 (7~68) winsize 62

 3130 12:40:35.808737  [CA 1] Center 37 (7~68) winsize 62

 3131 12:40:35.812059  [CA 2] Center 35 (5~65) winsize 61

 3132 12:40:35.815273  [CA 3] Center 34 (4~65) winsize 62

 3133 12:40:35.819146  [CA 4] Center 34 (4~65) winsize 62

 3134 12:40:35.822179  [CA 5] Center 34 (4~64) winsize 61

 3135 12:40:35.822269  

 3136 12:40:35.825426  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 3137 12:40:35.825510  

 3138 12:40:35.828711  [CATrainingPosCal] consider 2 rank data

 3139 12:40:35.832624  u2DelayCellTimex100 = 270/100 ps

 3140 12:40:35.835686  CA0 delay=37 (7~68),Diff = 4 PI (19 cell)

 3141 12:40:35.838914  CA1 delay=37 (7~68),Diff = 4 PI (19 cell)

 3142 12:40:35.842617  CA2 delay=35 (5~65),Diff = 2 PI (9 cell)

 3143 12:40:35.848746  CA3 delay=34 (4~64),Diff = 1 PI (4 cell)

 3144 12:40:35.852402  CA4 delay=34 (4~64),Diff = 1 PI (4 cell)

 3145 12:40:35.855324  CA5 delay=33 (4~63),Diff = 0 PI (0 cell)

 3146 12:40:35.855441  

 3147 12:40:35.859045  CA PerBit enable=1, Macro0, CA PI delay=33

 3148 12:40:35.859131  

 3149 12:40:35.862244  [CBTSetCACLKResult] CA Dly = 33

 3150 12:40:35.862329  CS Dly: 8 (0~41)

 3151 12:40:35.862396  

 3152 12:40:35.865981  ----->DramcWriteLeveling(PI) begin...

 3153 12:40:35.866068  ==

 3154 12:40:35.868915  Dram Type= 6, Freq= 0, CH_1, rank 0

 3155 12:40:35.875500  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3156 12:40:35.875606  ==

 3157 12:40:35.879262  Write leveling (Byte 0): 26 => 26

 3158 12:40:35.882404  Write leveling (Byte 1): 29 => 29

 3159 12:40:35.882491  DramcWriteLeveling(PI) end<-----

 3160 12:40:35.882558  

 3161 12:40:35.885684  ==

 3162 12:40:35.885769  Dram Type= 6, Freq= 0, CH_1, rank 0

 3163 12:40:35.892818  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3164 12:40:35.892917  ==

 3165 12:40:35.895738  [Gating] SW mode calibration

 3166 12:40:35.902679  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 3167 12:40:35.905916  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 3168 12:40:35.912795   0 15  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3169 12:40:35.916017   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3170 12:40:35.919252   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3171 12:40:35.925848   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3172 12:40:35.929122   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3173 12:40:35.932965   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3174 12:40:35.936257   0 15 24 | B1->B0 | 3232 2525 | 0 0 | (0 0) (0 0)

 3175 12:40:35.942978   0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 3176 12:40:35.946203   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3177 12:40:35.949367   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3178 12:40:35.956304   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3179 12:40:35.959340   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3180 12:40:35.962873   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3181 12:40:35.969856   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3182 12:40:35.973066   1  0 24 | B1->B0 | 2d2d 3e3e | 1 0 | (0 0) (0 0)

 3183 12:40:35.976194   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3184 12:40:35.982742   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3185 12:40:35.986159   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3186 12:40:35.989850   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3187 12:40:35.996196   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3188 12:40:35.999425   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3189 12:40:36.002967   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3190 12:40:36.009861   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 3191 12:40:36.012883   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 3192 12:40:36.017106   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3193 12:40:36.020093   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3194 12:40:36.026292   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3195 12:40:36.030108   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3196 12:40:36.033220   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3197 12:40:36.039617   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3198 12:40:36.042800   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3199 12:40:36.046173   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3200 12:40:36.052882   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3201 12:40:36.056103   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3202 12:40:36.059790   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3203 12:40:36.066128   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3204 12:40:36.069560   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3205 12:40:36.072927   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3206 12:40:36.079756   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3207 12:40:36.083003   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3208 12:40:36.086078   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3209 12:40:36.089314  Total UI for P1: 0, mck2ui 16

 3210 12:40:36.092898  best dqsien dly found for B0: ( 1,  3, 26)

 3211 12:40:36.096512  Total UI for P1: 0, mck2ui 16

 3212 12:40:36.099735  best dqsien dly found for B1: ( 1,  3, 26)

 3213 12:40:36.102891  best DQS0 dly(MCK, UI, PI) = (1, 3, 26)

 3214 12:40:36.106099  best DQS1 dly(MCK, UI, PI) = (1, 3, 26)

 3215 12:40:36.106184  

 3216 12:40:36.109951  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)

 3217 12:40:36.116012  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)

 3218 12:40:36.116101  [Gating] SW calibration Done

 3219 12:40:36.116169  ==

 3220 12:40:36.119541  Dram Type= 6, Freq= 0, CH_1, rank 0

 3221 12:40:36.126474  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3222 12:40:36.126561  ==

 3223 12:40:36.126629  RX Vref Scan: 0

 3224 12:40:36.126723  

 3225 12:40:36.129730  RX Vref 0 -> 0, step: 1

 3226 12:40:36.129816  

 3227 12:40:36.132750  RX Delay -40 -> 252, step: 8

 3228 12:40:36.136114  iDelay=200, Bit 0, Center 123 (56 ~ 191) 136

 3229 12:40:36.139920  iDelay=200, Bit 1, Center 115 (48 ~ 183) 136

 3230 12:40:36.143064  iDelay=200, Bit 2, Center 107 (40 ~ 175) 136

 3231 12:40:36.149500  iDelay=200, Bit 3, Center 123 (56 ~ 191) 136

 3232 12:40:36.153063  iDelay=200, Bit 4, Center 119 (48 ~ 191) 144

 3233 12:40:36.156210  iDelay=200, Bit 5, Center 127 (56 ~ 199) 144

 3234 12:40:36.159418  iDelay=200, Bit 6, Center 131 (64 ~ 199) 136

 3235 12:40:36.163131  iDelay=200, Bit 7, Center 123 (56 ~ 191) 136

 3236 12:40:36.169415  iDelay=200, Bit 8, Center 103 (40 ~ 167) 128

 3237 12:40:36.173010  iDelay=200, Bit 9, Center 107 (40 ~ 175) 136

 3238 12:40:36.175964  iDelay=200, Bit 10, Center 115 (48 ~ 183) 136

 3239 12:40:36.179596  iDelay=200, Bit 11, Center 111 (48 ~ 175) 128

 3240 12:40:36.182744  iDelay=200, Bit 12, Center 123 (56 ~ 191) 136

 3241 12:40:36.189825  iDelay=200, Bit 13, Center 127 (64 ~ 191) 128

 3242 12:40:36.192986  iDelay=200, Bit 14, Center 123 (56 ~ 191) 136

 3243 12:40:36.196198  iDelay=200, Bit 15, Center 123 (56 ~ 191) 136

 3244 12:40:36.196282  ==

 3245 12:40:36.199417  Dram Type= 6, Freq= 0, CH_1, rank 0

 3246 12:40:36.203133  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3247 12:40:36.203237  ==

 3248 12:40:36.205955  DQS Delay:

 3249 12:40:36.206040  DQS0 = 0, DQS1 = 0

 3250 12:40:36.209843  DQM Delay:

 3251 12:40:36.209928  DQM0 = 121, DQM1 = 116

 3252 12:40:36.209995  DQ Delay:

 3253 12:40:36.213273  DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123

 3254 12:40:36.219559  DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =123

 3255 12:40:36.223184  DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111

 3256 12:40:36.226140  DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123

 3257 12:40:36.226240  

 3258 12:40:36.226321  

 3259 12:40:36.226398  ==

 3260 12:40:36.229939  Dram Type= 6, Freq= 0, CH_1, rank 0

 3261 12:40:36.233006  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3262 12:40:36.233090  ==

 3263 12:40:36.233168  

 3264 12:40:36.233233  

 3265 12:40:36.236012  	TX Vref Scan disable

 3266 12:40:36.240046   == TX Byte 0 ==

 3267 12:40:36.243133  Update DQ  dly =843 (3 ,2, 11)  DQ  OEN =(2 ,7)

 3268 12:40:36.246188  Update DQM dly =843 (3 ,2, 11)  DQM OEN =(2 ,7)

 3269 12:40:36.246274   == TX Byte 1 ==

 3270 12:40:36.253179  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 3271 12:40:36.256303  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 3272 12:40:36.256411  ==

 3273 12:40:36.259478  Dram Type= 6, Freq= 0, CH_1, rank 0

 3274 12:40:36.262791  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3275 12:40:36.262882  ==

 3276 12:40:36.276197  TX Vref=22, minBit 11, minWin=24, winSum=411

 3277 12:40:36.279177  TX Vref=24, minBit 11, minWin=24, winSum=414

 3278 12:40:36.282500  TX Vref=26, minBit 9, minWin=25, winSum=417

 3279 12:40:36.285741  TX Vref=28, minBit 2, minWin=26, winSum=426

 3280 12:40:36.289552  TX Vref=30, minBit 15, minWin=25, winSum=428

 3281 12:40:36.296012  TX Vref=32, minBit 15, minWin=25, winSum=429

 3282 12:40:36.299160  [TxChooseVref] Worse bit 2, Min win 26, Win sum 426, Final Vref 28

 3283 12:40:36.299270  

 3284 12:40:36.302887  Final TX Range 1 Vref 28

 3285 12:40:36.302967  

 3286 12:40:36.303032  ==

 3287 12:40:36.306090  Dram Type= 6, Freq= 0, CH_1, rank 0

 3288 12:40:36.309344  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3289 12:40:36.309432  ==

 3290 12:40:36.312958  

 3291 12:40:36.313037  

 3292 12:40:36.313108  	TX Vref Scan disable

 3293 12:40:36.316164   == TX Byte 0 ==

 3294 12:40:36.319542  Update DQ  dly =843 (3 ,2, 11)  DQ  OEN =(2 ,7)

 3295 12:40:36.322639  Update DQM dly =843 (3 ,2, 11)  DQM OEN =(2 ,7)

 3296 12:40:36.326311   == TX Byte 1 ==

 3297 12:40:36.329337  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 3298 12:40:36.333090  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 3299 12:40:36.333169  

 3300 12:40:36.336020  [DATLAT]

 3301 12:40:36.336100  Freq=1200, CH1 RK0

 3302 12:40:36.336169  

 3303 12:40:36.339608  DATLAT Default: 0xd

 3304 12:40:36.339710  0, 0xFFFF, sum = 0

 3305 12:40:36.342654  1, 0xFFFF, sum = 0

 3306 12:40:36.342761  2, 0xFFFF, sum = 0

 3307 12:40:36.345949  3, 0xFFFF, sum = 0

 3308 12:40:36.346054  4, 0xFFFF, sum = 0

 3309 12:40:36.349723  5, 0xFFFF, sum = 0

 3310 12:40:36.349805  6, 0xFFFF, sum = 0

 3311 12:40:36.353021  7, 0xFFFF, sum = 0

 3312 12:40:36.353129  8, 0xFFFF, sum = 0

 3313 12:40:36.356271  9, 0xFFFF, sum = 0

 3314 12:40:36.359363  10, 0xFFFF, sum = 0

 3315 12:40:36.359444  11, 0xFFFF, sum = 0

 3316 12:40:36.363052  12, 0x0, sum = 1

 3317 12:40:36.363160  13, 0x0, sum = 2

 3318 12:40:36.363260  14, 0x0, sum = 3

 3319 12:40:36.366224  15, 0x0, sum = 4

 3320 12:40:36.366310  best_step = 13

 3321 12:40:36.366402  

 3322 12:40:36.366496  ==

 3323 12:40:36.369493  Dram Type= 6, Freq= 0, CH_1, rank 0

 3324 12:40:36.375881  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3325 12:40:36.375963  ==

 3326 12:40:36.376029  RX Vref Scan: 1

 3327 12:40:36.376095  

 3328 12:40:36.379657  Set Vref Range= 32 -> 127

 3329 12:40:36.379765  

 3330 12:40:36.382673  RX Vref 32 -> 127, step: 1

 3331 12:40:36.382781  

 3332 12:40:36.386401  RX Delay -5 -> 252, step: 4

 3333 12:40:36.386508  

 3334 12:40:36.389336  Set Vref, RX VrefLevel [Byte0]: 32

 3335 12:40:36.392710                           [Byte1]: 32

 3336 12:40:36.392821  

 3337 12:40:36.396051  Set Vref, RX VrefLevel [Byte0]: 33

 3338 12:40:36.399679                           [Byte1]: 33

 3339 12:40:36.399786  

 3340 12:40:36.402978  Set Vref, RX VrefLevel [Byte0]: 34

 3341 12:40:36.406250                           [Byte1]: 34

 3342 12:40:36.410042  

 3343 12:40:36.410160  Set Vref, RX VrefLevel [Byte0]: 35

 3344 12:40:36.413166                           [Byte1]: 35

 3345 12:40:36.418046  

 3346 12:40:36.418164  Set Vref, RX VrefLevel [Byte0]: 36

 3347 12:40:36.421188                           [Byte1]: 36

 3348 12:40:36.425673  

 3349 12:40:36.425785  Set Vref, RX VrefLevel [Byte0]: 37

 3350 12:40:36.428911                           [Byte1]: 37

 3351 12:40:36.433307  

 3352 12:40:36.433400  Set Vref, RX VrefLevel [Byte0]: 38

 3353 12:40:36.437069                           [Byte1]: 38

 3354 12:40:36.441113  

 3355 12:40:36.441203  Set Vref, RX VrefLevel [Byte0]: 39

 3356 12:40:36.444862                           [Byte1]: 39

 3357 12:40:36.448928  

 3358 12:40:36.449002  Set Vref, RX VrefLevel [Byte0]: 40

 3359 12:40:36.452687                           [Byte1]: 40

 3360 12:40:36.457319  

 3361 12:40:36.457396  Set Vref, RX VrefLevel [Byte0]: 41

 3362 12:40:36.460589                           [Byte1]: 41

 3363 12:40:36.465024  

 3364 12:40:36.465124  Set Vref, RX VrefLevel [Byte0]: 42

 3365 12:40:36.468103                           [Byte1]: 42

 3366 12:40:36.472604  

 3367 12:40:36.472708  Set Vref, RX VrefLevel [Byte0]: 43

 3368 12:40:36.475855                           [Byte1]: 43

 3369 12:40:36.480450  

 3370 12:40:36.480551  Set Vref, RX VrefLevel [Byte0]: 44

 3371 12:40:36.484206                           [Byte1]: 44

 3372 12:40:36.488512  

 3373 12:40:36.488612  Set Vref, RX VrefLevel [Byte0]: 45

 3374 12:40:36.491618                           [Byte1]: 45

 3375 12:40:36.496411  

 3376 12:40:36.496514  Set Vref, RX VrefLevel [Byte0]: 46

 3377 12:40:36.499523                           [Byte1]: 46

 3378 12:40:36.504640  

 3379 12:40:36.504743  Set Vref, RX VrefLevel [Byte0]: 47

 3380 12:40:36.507838                           [Byte1]: 47

 3381 12:40:36.512282  

 3382 12:40:36.512396  Set Vref, RX VrefLevel [Byte0]: 48

 3383 12:40:36.515532                           [Byte1]: 48

 3384 12:40:36.520209  

 3385 12:40:36.520313  Set Vref, RX VrefLevel [Byte0]: 49

 3386 12:40:36.523156                           [Byte1]: 49

 3387 12:40:36.527558  

 3388 12:40:36.527670  Set Vref, RX VrefLevel [Byte0]: 50

 3389 12:40:36.531216                           [Byte1]: 50

 3390 12:40:36.535774  

 3391 12:40:36.535879  Set Vref, RX VrefLevel [Byte0]: 51

 3392 12:40:36.539072                           [Byte1]: 51

 3393 12:40:36.543321  

 3394 12:40:36.543411  Set Vref, RX VrefLevel [Byte0]: 52

 3395 12:40:36.546819                           [Byte1]: 52

 3396 12:40:36.550977  

 3397 12:40:36.551076  Set Vref, RX VrefLevel [Byte0]: 53

 3398 12:40:36.554614                           [Byte1]: 53

 3399 12:40:36.559046  

 3400 12:40:36.559169  Set Vref, RX VrefLevel [Byte0]: 54

 3401 12:40:36.562246                           [Byte1]: 54

 3402 12:40:36.566754  

 3403 12:40:36.566870  Set Vref, RX VrefLevel [Byte0]: 55

 3404 12:40:36.570520                           [Byte1]: 55

 3405 12:40:36.575044  

 3406 12:40:36.575144  Set Vref, RX VrefLevel [Byte0]: 56

 3407 12:40:36.578276                           [Byte1]: 56

 3408 12:40:36.582761  

 3409 12:40:36.582887  Set Vref, RX VrefLevel [Byte0]: 57

 3410 12:40:36.586009                           [Byte1]: 57

 3411 12:40:36.590481  

 3412 12:40:36.590609  Set Vref, RX VrefLevel [Byte0]: 58

 3413 12:40:36.593772                           [Byte1]: 58

 3414 12:40:36.598455  

 3415 12:40:36.598571  Set Vref, RX VrefLevel [Byte0]: 59

 3416 12:40:36.601868                           [Byte1]: 59

 3417 12:40:36.606120  

 3418 12:40:36.606226  Set Vref, RX VrefLevel [Byte0]: 60

 3419 12:40:36.609714                           [Byte1]: 60

 3420 12:40:36.614260  

 3421 12:40:36.614342  Set Vref, RX VrefLevel [Byte0]: 61

 3422 12:40:36.617297                           [Byte1]: 61

 3423 12:40:36.621833  

 3424 12:40:36.621951  Set Vref, RX VrefLevel [Byte0]: 62

 3425 12:40:36.625043                           [Byte1]: 62

 3426 12:40:36.630091  

 3427 12:40:36.630181  Set Vref, RX VrefLevel [Byte0]: 63

 3428 12:40:36.633288                           [Byte1]: 63

 3429 12:40:36.637451  

 3430 12:40:36.637538  Set Vref, RX VrefLevel [Byte0]: 64

 3431 12:40:36.641266                           [Byte1]: 64

 3432 12:40:36.645739  

 3433 12:40:36.645824  Set Vref, RX VrefLevel [Byte0]: 65

 3434 12:40:36.649058                           [Byte1]: 65

 3435 12:40:36.653774  

 3436 12:40:36.653903  Set Vref, RX VrefLevel [Byte0]: 66

 3437 12:40:36.656786                           [Byte1]: 66

 3438 12:40:36.661015  

 3439 12:40:36.661110  Set Vref, RX VrefLevel [Byte0]: 67

 3440 12:40:36.664694                           [Byte1]: 67

 3441 12:40:36.669157  

 3442 12:40:36.669241  Set Vref, RX VrefLevel [Byte0]: 68

 3443 12:40:36.672507                           [Byte1]: 68

 3444 12:40:36.676785  

 3445 12:40:36.676880  Set Vref, RX VrefLevel [Byte0]: 69

 3446 12:40:36.680052                           [Byte1]: 69

 3447 12:40:36.684504  

 3448 12:40:36.684591  Final RX Vref Byte 0 = 53 to rank0

 3449 12:40:36.687889  Final RX Vref Byte 1 = 53 to rank0

 3450 12:40:36.691167  Final RX Vref Byte 0 = 53 to rank1

 3451 12:40:36.695014  Final RX Vref Byte 1 = 53 to rank1==

 3452 12:40:36.698023  Dram Type= 6, Freq= 0, CH_1, rank 0

 3453 12:40:36.704758  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3454 12:40:36.704859  ==

 3455 12:40:36.704928  DQS Delay:

 3456 12:40:36.704989  DQS0 = 0, DQS1 = 0

 3457 12:40:36.708354  DQM Delay:

 3458 12:40:36.708430  DQM0 = 120, DQM1 = 117

 3459 12:40:36.711502  DQ Delay:

 3460 12:40:36.714546  DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116

 3461 12:40:36.717974  DQ4 =120, DQ5 =130, DQ6 =130, DQ7 =120

 3462 12:40:36.721025  DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112

 3463 12:40:36.724882  DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126

 3464 12:40:36.724963  

 3465 12:40:36.725031  

 3466 12:40:36.731359  [DQSOSCAuto] RK0, (LSB)MR18= 0x316, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps

 3467 12:40:36.735184  CH1 RK0: MR19=404, MR18=316

 3468 12:40:36.741534  CH1_RK0: MR19=0x404, MR18=0x316, DQSOSC=401, MR23=63, INC=40, DEC=27

 3469 12:40:36.741616  

 3470 12:40:36.745003  ----->DramcWriteLeveling(PI) begin...

 3471 12:40:36.745116  ==

 3472 12:40:36.748265  Dram Type= 6, Freq= 0, CH_1, rank 1

 3473 12:40:36.751571  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3474 12:40:36.751652  ==

 3475 12:40:36.755275  Write leveling (Byte 0): 26 => 26

 3476 12:40:36.758314  Write leveling (Byte 1): 29 => 29

 3477 12:40:36.761366  DramcWriteLeveling(PI) end<-----

 3478 12:40:36.761451  

 3479 12:40:36.761518  ==

 3480 12:40:36.764950  Dram Type= 6, Freq= 0, CH_1, rank 1

 3481 12:40:36.768471  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3482 12:40:36.771399  ==

 3483 12:40:36.771492  [Gating] SW mode calibration

 3484 12:40:36.781519  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 3485 12:40:36.784799  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 3486 12:40:36.788707   0 15  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3487 12:40:36.795048   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3488 12:40:36.798327   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3489 12:40:36.801390   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3490 12:40:36.808303   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3491 12:40:36.811752   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)

 3492 12:40:36.814845   0 15 24 | B1->B0 | 2525 3232 | 0 1 | (0 0) (1 0)

 3493 12:40:36.821693   0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)

 3494 12:40:36.824760   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3495 12:40:36.828213   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3496 12:40:36.834927   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3497 12:40:36.838120   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3498 12:40:36.841249   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3499 12:40:36.848225   1  0 20 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)

 3500 12:40:36.851899   1  0 24 | B1->B0 | 4646 302f | 0 1 | (0 0) (0 0)

 3501 12:40:36.855090   1  0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)

 3502 12:40:36.858450   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3503 12:40:36.864746   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3504 12:40:36.868344   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3505 12:40:36.871408   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3506 12:40:36.878224   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3507 12:40:36.881348   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 3508 12:40:36.884522   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 3509 12:40:36.891603   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 3510 12:40:36.894846   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3511 12:40:36.897993   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3512 12:40:36.904564   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3513 12:40:36.908261   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3514 12:40:36.911256   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3515 12:40:36.917961   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3516 12:40:36.921638   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3517 12:40:36.924779   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3518 12:40:36.931428   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3519 12:40:36.934617   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3520 12:40:36.937867   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3521 12:40:36.944929   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3522 12:40:36.948029   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3523 12:40:36.951194   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 3524 12:40:36.958038   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 3525 12:40:36.961159   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 3526 12:40:36.964921  Total UI for P1: 0, mck2ui 16

 3527 12:40:36.968070  best dqsien dly found for B1: ( 1,  3, 22)

 3528 12:40:36.971052   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3529 12:40:36.974697  Total UI for P1: 0, mck2ui 16

 3530 12:40:36.977719  best dqsien dly found for B0: ( 1,  3, 28)

 3531 12:40:36.981258  best DQS0 dly(MCK, UI, PI) = (1, 3, 28)

 3532 12:40:36.984891  best DQS1 dly(MCK, UI, PI) = (1, 3, 22)

 3533 12:40:36.985030  

 3534 12:40:36.987957  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)

 3535 12:40:36.991174  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)

 3536 12:40:36.994502  [Gating] SW calibration Done

 3537 12:40:36.994585  ==

 3538 12:40:36.997760  Dram Type= 6, Freq= 0, CH_1, rank 1

 3539 12:40:37.004217  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3540 12:40:37.004300  ==

 3541 12:40:37.004366  RX Vref Scan: 0

 3542 12:40:37.004427  

 3543 12:40:37.008082  RX Vref 0 -> 0, step: 1

 3544 12:40:37.008164  

 3545 12:40:37.011268  RX Delay -40 -> 252, step: 8

 3546 12:40:37.014576  iDelay=200, Bit 0, Center 123 (56 ~ 191) 136

 3547 12:40:37.018214  iDelay=200, Bit 1, Center 115 (48 ~ 183) 136

 3548 12:40:37.021156  iDelay=200, Bit 2, Center 107 (40 ~ 175) 136

 3549 12:40:37.027864  iDelay=200, Bit 3, Center 119 (56 ~ 183) 128

 3550 12:40:37.031450  iDelay=200, Bit 4, Center 119 (56 ~ 183) 128

 3551 12:40:37.034555  iDelay=200, Bit 5, Center 131 (64 ~ 199) 136

 3552 12:40:37.037631  iDelay=200, Bit 6, Center 131 (64 ~ 199) 136

 3553 12:40:37.041320  iDelay=200, Bit 7, Center 123 (56 ~ 191) 136

 3554 12:40:37.044428  iDelay=200, Bit 8, Center 103 (40 ~ 167) 128

 3555 12:40:37.050862  iDelay=200, Bit 9, Center 107 (40 ~ 175) 136

 3556 12:40:37.054074  iDelay=200, Bit 10, Center 115 (48 ~ 183) 136

 3557 12:40:37.057290  iDelay=200, Bit 11, Center 111 (48 ~ 175) 128

 3558 12:40:37.060972  iDelay=200, Bit 12, Center 127 (56 ~ 199) 144

 3559 12:40:37.067679  iDelay=200, Bit 13, Center 127 (64 ~ 191) 128

 3560 12:40:37.070687  iDelay=200, Bit 14, Center 123 (56 ~ 191) 136

 3561 12:40:37.074029  iDelay=200, Bit 15, Center 123 (56 ~ 191) 136

 3562 12:40:37.074116  ==

 3563 12:40:37.077828  Dram Type= 6, Freq= 0, CH_1, rank 1

 3564 12:40:37.081002  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3565 12:40:37.081096  ==

 3566 12:40:37.083990  DQS Delay:

 3567 12:40:37.084074  DQS0 = 0, DQS1 = 0

 3568 12:40:37.087573  DQM Delay:

 3569 12:40:37.087660  DQM0 = 121, DQM1 = 117

 3570 12:40:37.087726  DQ Delay:

 3571 12:40:37.091052  DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119

 3572 12:40:37.097783  DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123

 3573 12:40:37.100956  DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111

 3574 12:40:37.104190  DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123

 3575 12:40:37.104275  

 3576 12:40:37.104342  

 3577 12:40:37.104404  ==

 3578 12:40:37.107338  Dram Type= 6, Freq= 0, CH_1, rank 1

 3579 12:40:37.111239  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3580 12:40:37.111327  ==

 3581 12:40:37.111395  

 3582 12:40:37.111478  

 3583 12:40:37.114508  	TX Vref Scan disable

 3584 12:40:37.117976   == TX Byte 0 ==

 3585 12:40:37.120974  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3586 12:40:37.123966  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3587 12:40:37.127800   == TX Byte 1 ==

 3588 12:40:37.130769  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 3589 12:40:37.133930  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 3590 12:40:37.134017  ==

 3591 12:40:37.137120  Dram Type= 6, Freq= 0, CH_1, rank 1

 3592 12:40:37.140775  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3593 12:40:37.143885  ==

 3594 12:40:37.153793  TX Vref=22, minBit 9, minWin=25, winSum=418

 3595 12:40:37.157518  TX Vref=24, minBit 9, minWin=25, winSum=422

 3596 12:40:37.160713  TX Vref=26, minBit 10, minWin=25, winSum=429

 3597 12:40:37.163990  TX Vref=28, minBit 10, minWin=25, winSum=430

 3598 12:40:37.167101  TX Vref=30, minBit 9, minWin=26, winSum=432

 3599 12:40:37.173772  TX Vref=32, minBit 6, minWin=26, winSum=429

 3600 12:40:37.177013  [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 30

 3601 12:40:37.177098  

 3602 12:40:37.180241  Final TX Range 1 Vref 30

 3603 12:40:37.180328  

 3604 12:40:37.180394  ==

 3605 12:40:37.184105  Dram Type= 6, Freq= 0, CH_1, rank 1

 3606 12:40:37.187163  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3607 12:40:37.190384  ==

 3608 12:40:37.190467  

 3609 12:40:37.190533  

 3610 12:40:37.190593  	TX Vref Scan disable

 3611 12:40:37.193547   == TX Byte 0 ==

 3612 12:40:37.196977  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3613 12:40:37.204001  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3614 12:40:37.204090   == TX Byte 1 ==

 3615 12:40:37.207158  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 3616 12:40:37.213576  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 3617 12:40:37.213680  

 3618 12:40:37.213770  [DATLAT]

 3619 12:40:37.213852  Freq=1200, CH1 RK1

 3620 12:40:37.213912  

 3621 12:40:37.216747  DATLAT Default: 0xd

 3622 12:40:37.216884  0, 0xFFFF, sum = 0

 3623 12:40:37.220560  1, 0xFFFF, sum = 0

 3624 12:40:37.223746  2, 0xFFFF, sum = 0

 3625 12:40:37.223844  3, 0xFFFF, sum = 0

 3626 12:40:37.226988  4, 0xFFFF, sum = 0

 3627 12:40:37.227120  5, 0xFFFF, sum = 0

 3628 12:40:37.230369  6, 0xFFFF, sum = 0

 3629 12:40:37.230460  7, 0xFFFF, sum = 0

 3630 12:40:37.233808  8, 0xFFFF, sum = 0

 3631 12:40:37.233894  9, 0xFFFF, sum = 0

 3632 12:40:37.236833  10, 0xFFFF, sum = 0

 3633 12:40:37.236980  11, 0xFFFF, sum = 0

 3634 12:40:37.240549  12, 0x0, sum = 1

 3635 12:40:37.240635  13, 0x0, sum = 2

 3636 12:40:37.243617  14, 0x0, sum = 3

 3637 12:40:37.243707  15, 0x0, sum = 4

 3638 12:40:37.243788  best_step = 13

 3639 12:40:37.247342  

 3640 12:40:37.247452  ==

 3641 12:40:37.250281  Dram Type= 6, Freq= 0, CH_1, rank 1

 3642 12:40:37.253408  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3643 12:40:37.253492  ==

 3644 12:40:37.253560  RX Vref Scan: 0

 3645 12:40:37.253630  

 3646 12:40:37.257241  RX Vref 0 -> 0, step: 1

 3647 12:40:37.257335  

 3648 12:40:37.260008  RX Delay -5 -> 252, step: 4

 3649 12:40:37.263782  iDelay=195, Bit 0, Center 122 (59 ~ 186) 128

 3650 12:40:37.270434  iDelay=195, Bit 1, Center 116 (55 ~ 178) 124

 3651 12:40:37.273647  iDelay=195, Bit 2, Center 110 (51 ~ 170) 120

 3652 12:40:37.276790  iDelay=195, Bit 3, Center 116 (59 ~ 174) 116

 3653 12:40:37.280566  iDelay=195, Bit 4, Center 116 (55 ~ 178) 124

 3654 12:40:37.283572  iDelay=195, Bit 5, Center 132 (71 ~ 194) 124

 3655 12:40:37.290089  iDelay=195, Bit 6, Center 130 (67 ~ 194) 128

 3656 12:40:37.293453  iDelay=195, Bit 7, Center 120 (59 ~ 182) 124

 3657 12:40:37.296433  iDelay=195, Bit 8, Center 106 (47 ~ 166) 120

 3658 12:40:37.300084  iDelay=195, Bit 9, Center 108 (47 ~ 170) 124

 3659 12:40:37.303058  iDelay=195, Bit 10, Center 120 (59 ~ 182) 124

 3660 12:40:37.310166  iDelay=195, Bit 11, Center 112 (51 ~ 174) 124

 3661 12:40:37.313413  iDelay=195, Bit 12, Center 126 (63 ~ 190) 128

 3662 12:40:37.316660  iDelay=195, Bit 13, Center 124 (67 ~ 182) 116

 3663 12:40:37.319887  iDelay=195, Bit 14, Center 124 (67 ~ 182) 116

 3664 12:40:37.326204  iDelay=195, Bit 15, Center 128 (67 ~ 190) 124

 3665 12:40:37.326299  ==

 3666 12:40:37.329573  Dram Type= 6, Freq= 0, CH_1, rank 1

 3667 12:40:37.333405  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3668 12:40:37.333493  ==

 3669 12:40:37.333561  DQS Delay:

 3670 12:40:37.336391  DQS0 = 0, DQS1 = 0

 3671 12:40:37.336474  DQM Delay:

 3672 12:40:37.339958  DQM0 = 120, DQM1 = 118

 3673 12:40:37.340043  DQ Delay:

 3674 12:40:37.342741  DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116

 3675 12:40:37.346463  DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120

 3676 12:40:37.349380  DQ8 =106, DQ9 =108, DQ10 =120, DQ11 =112

 3677 12:40:37.352956  DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128

 3678 12:40:37.353040  

 3679 12:40:37.353105  

 3680 12:40:37.363265  [DQSOSCAuto] RK1, (LSB)MR18= 0x10ed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps

 3681 12:40:37.366098  CH1 RK1: MR19=403, MR18=10ED

 3682 12:40:37.369449  CH1_RK1: MR19=0x403, MR18=0x10ED, DQSOSC=403, MR23=63, INC=40, DEC=26

 3683 12:40:37.372691  [RxdqsGatingPostProcess] freq 1200

 3684 12:40:37.379764  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 3685 12:40:37.382887  best DQS0 dly(2T, 0.5T) = (0, 11)

 3686 12:40:37.386003  best DQS1 dly(2T, 0.5T) = (0, 11)

 3687 12:40:37.389222  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3688 12:40:37.393260  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3689 12:40:37.396429  best DQS0 dly(2T, 0.5T) = (0, 11)

 3690 12:40:37.399535  best DQS1 dly(2T, 0.5T) = (0, 11)

 3691 12:40:37.402621  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3692 12:40:37.406309  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3693 12:40:37.409343  Pre-setting of DQS Precalculation

 3694 12:40:37.412888  [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13

 3695 12:40:37.419060  sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2

 3696 12:40:37.426138  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 3697 12:40:37.429445  

 3698 12:40:37.429546  

 3699 12:40:37.429627  [Calibration Summary] 2400 Mbps

 3700 12:40:37.432690  CH 0, Rank 0

 3701 12:40:37.432798  SW Impedance     : PASS

 3702 12:40:37.435930  DUTY Scan        : NO K

 3703 12:40:37.439151  ZQ Calibration   : PASS

 3704 12:40:37.439250  Jitter Meter     : NO K

 3705 12:40:37.442404  CBT Training     : PASS

 3706 12:40:37.446088  Write leveling   : PASS

 3707 12:40:37.446188  RX DQS gating    : PASS

 3708 12:40:37.449153  RX DQ/DQS(RDDQC) : PASS

 3709 12:40:37.452790  TX DQ/DQS        : PASS

 3710 12:40:37.452985  RX DATLAT        : PASS

 3711 12:40:37.455776  RX DQ/DQS(Engine): PASS

 3712 12:40:37.459302  TX OE            : NO K

 3713 12:40:37.459425  All Pass.

 3714 12:40:37.459557  

 3715 12:40:37.459662  CH 0, Rank 1

 3716 12:40:37.462388  SW Impedance     : PASS

 3717 12:40:37.465869  DUTY Scan        : NO K

 3718 12:40:37.465991  ZQ Calibration   : PASS

 3719 12:40:37.468978  Jitter Meter     : NO K

 3720 12:40:37.469074  CBT Training     : PASS

 3721 12:40:37.472997  Write leveling   : PASS

 3722 12:40:37.475795  RX DQS gating    : PASS

 3723 12:40:37.475897  RX DQ/DQS(RDDQC) : PASS

 3724 12:40:37.479180  TX DQ/DQS        : PASS

 3725 12:40:37.482366  RX DATLAT        : PASS

 3726 12:40:37.482447  RX DQ/DQS(Engine): PASS

 3727 12:40:37.485691  TX OE            : NO K

 3728 12:40:37.485772  All Pass.

 3729 12:40:37.485836  

 3730 12:40:37.489313  CH 1, Rank 0

 3731 12:40:37.489393  SW Impedance     : PASS

 3732 12:40:37.492457  DUTY Scan        : NO K

 3733 12:40:37.495647  ZQ Calibration   : PASS

 3734 12:40:37.495732  Jitter Meter     : NO K

 3735 12:40:37.498930  CBT Training     : PASS

 3736 12:40:37.502199  Write leveling   : PASS

 3737 12:40:37.502282  RX DQS gating    : PASS

 3738 12:40:37.506036  RX DQ/DQS(RDDQC) : PASS

 3739 12:40:37.508964  TX DQ/DQS        : PASS

 3740 12:40:37.509072  RX DATLAT        : PASS

 3741 12:40:37.512685  RX DQ/DQS(Engine): PASS

 3742 12:40:37.512807  TX OE            : NO K

 3743 12:40:37.515773  All Pass.

 3744 12:40:37.515879  

 3745 12:40:37.515984  CH 1, Rank 1

 3746 12:40:37.519396  SW Impedance     : PASS

 3747 12:40:37.519500  DUTY Scan        : NO K

 3748 12:40:37.522345  ZQ Calibration   : PASS

 3749 12:40:37.526118  Jitter Meter     : NO K

 3750 12:40:37.526225  CBT Training     : PASS

 3751 12:40:37.529328  Write leveling   : PASS

 3752 12:40:37.532576  RX DQS gating    : PASS

 3753 12:40:37.532686  RX DQ/DQS(RDDQC) : PASS

 3754 12:40:37.535956  TX DQ/DQS        : PASS

 3755 12:40:37.539062  RX DATLAT        : PASS

 3756 12:40:37.539177  RX DQ/DQS(Engine): PASS

 3757 12:40:37.542472  TX OE            : NO K

 3758 12:40:37.542578  All Pass.

 3759 12:40:37.542671  

 3760 12:40:37.546175  DramC Write-DBI off

 3761 12:40:37.549379  	PER_BANK_REFRESH: Hybrid Mode

 3762 12:40:37.549456  TX_TRACKING: ON

 3763 12:40:37.559235  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1

 3764 12:40:37.562311  [FAST_K] Save calibration result to emmc

 3765 12:40:37.565776  dramc_set_vcore_voltage set vcore to 650000

 3766 12:40:37.569443  Read voltage for 600, 5

 3767 12:40:37.569529  Vio18 = 0

 3768 12:40:37.569596  Vcore = 650000

 3769 12:40:37.572607  Vdram = 0

 3770 12:40:37.572691  Vddq = 0

 3771 12:40:37.572759  Vmddr = 0

 3772 12:40:37.578822  [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0

 3773 12:40:37.582749  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 3774 12:40:37.585686  MEM_TYPE=3, freq_sel=19

 3775 12:40:37.588971  sv_algorithm_assistance_LP4_1600 

 3776 12:40:37.592207  ============ PULL DRAM RESETB DOWN ============

 3777 12:40:37.595976  ========== PULL DRAM RESETB DOWN end =========

 3778 12:40:37.602224  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3779 12:40:37.605861  =================================== 

 3780 12:40:37.605963  LPDDR4 DRAM CONFIGURATION

 3781 12:40:37.609124  =================================== 

 3782 12:40:37.612223  EX_ROW_EN[0]    = 0x0

 3783 12:40:37.615822  EX_ROW_EN[1]    = 0x0

 3784 12:40:37.615942  LP4Y_EN      = 0x0

 3785 12:40:37.618723  WORK_FSP     = 0x0

 3786 12:40:37.618810  WL           = 0x2

 3787 12:40:37.622560  RL           = 0x2

 3788 12:40:37.622636  BL           = 0x2

 3789 12:40:37.626064  RPST         = 0x0

 3790 12:40:37.626149  RD_PRE       = 0x0

 3791 12:40:37.629081  WR_PRE       = 0x1

 3792 12:40:37.629163  WR_PST       = 0x0

 3793 12:40:37.632380  DBI_WR       = 0x0

 3794 12:40:37.632461  DBI_RD       = 0x0

 3795 12:40:37.635723  OTF          = 0x1

 3796 12:40:37.638967  =================================== 

 3797 12:40:37.642209  =================================== 

 3798 12:40:37.642309  ANA top config

 3799 12:40:37.645407  =================================== 

 3800 12:40:37.648688  DLL_ASYNC_EN            =  0

 3801 12:40:37.652513  ALL_SLAVE_EN            =  1

 3802 12:40:37.655735  NEW_RANK_MODE           =  1

 3803 12:40:37.655813  DLL_IDLE_MODE           =  1

 3804 12:40:37.658782  LP45_APHY_COMB_EN       =  1

 3805 12:40:37.662473  TX_ODT_DIS              =  1

 3806 12:40:37.665585  NEW_8X_MODE             =  1

 3807 12:40:37.669202  =================================== 

 3808 12:40:37.672202  =================================== 

 3809 12:40:37.672292  data_rate                  = 1200

 3810 12:40:37.675659  CKR                        = 1

 3811 12:40:37.678729  DQ_P2S_RATIO               = 8

 3812 12:40:37.681913  =================================== 

 3813 12:40:37.685546  CA_P2S_RATIO               = 8

 3814 12:40:37.688645  DQ_CA_OPEN                 = 0

 3815 12:40:37.692209  DQ_SEMI_OPEN               = 0

 3816 12:40:37.692295  CA_SEMI_OPEN               = 0

 3817 12:40:37.695499  CA_FULL_RATE               = 0

 3818 12:40:37.698725  DQ_CKDIV4_EN               = 1

 3819 12:40:37.702041  CA_CKDIV4_EN               = 1

 3820 12:40:37.705505  CA_PREDIV_EN               = 0

 3821 12:40:37.708628  PH8_DLY                    = 0

 3822 12:40:37.708729  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 3823 12:40:37.711840  DQ_AAMCK_DIV               = 4

 3824 12:40:37.715785  CA_AAMCK_DIV               = 4

 3825 12:40:37.718926  CA_ADMCK_DIV               = 4

 3826 12:40:37.721986  DQ_TRACK_CA_EN             = 0

 3827 12:40:37.725519  CA_PICK                    = 600

 3828 12:40:37.729057  CA_MCKIO                   = 600

 3829 12:40:37.729159  MCKIO_SEMI                 = 0

 3830 12:40:37.732178  PLL_FREQ                   = 2288

 3831 12:40:37.735698  DQ_UI_PI_RATIO             = 32

 3832 12:40:37.738817  CA_UI_PI_RATIO             = 0

 3833 12:40:37.742090  =================================== 

 3834 12:40:37.745622  =================================== 

 3835 12:40:37.748693  memory_type:LPDDR4         

 3836 12:40:37.748797  GP_NUM     : 10       

 3837 12:40:37.751949  SRAM_EN    : 1       

 3838 12:40:37.752067  MD32_EN    : 0       

 3839 12:40:37.755116  =================================== 

 3840 12:40:37.759098  [ANA_INIT] >>>>>>>>>>>>>> 

 3841 12:40:37.762092  <<<<<< [CONFIGURE PHASE]: ANA_TX

 3842 12:40:37.765321  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 3843 12:40:37.769046  =================================== 

 3844 12:40:37.772144  data_rate = 1200,PCW = 0X5800

 3845 12:40:37.775795  =================================== 

 3846 12:40:37.778849  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 3847 12:40:37.785427  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 3848 12:40:37.788663  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 3849 12:40:37.794841  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 3850 12:40:37.798458  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 3851 12:40:37.801666  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 3852 12:40:37.801746  [ANA_INIT] flow start 

 3853 12:40:37.805424  [ANA_INIT] PLL >>>>>>>> 

 3854 12:40:37.808538  [ANA_INIT] PLL <<<<<<<< 

 3855 12:40:37.808642  [ANA_INIT] MIDPI >>>>>>>> 

 3856 12:40:37.811686  [ANA_INIT] MIDPI <<<<<<<< 

 3857 12:40:37.814922  [ANA_INIT] DLL >>>>>>>> 

 3858 12:40:37.815048  [ANA_INIT] flow end 

 3859 12:40:37.821416  ============ LP4 DIFF to SE enter ============

 3860 12:40:37.824688  ============ LP4 DIFF to SE exit  ============

 3861 12:40:37.828735  [ANA_INIT] <<<<<<<<<<<<< 

 3862 12:40:37.831590  [Flow] Enable top DCM control >>>>> 

 3863 12:40:37.835217  [Flow] Enable top DCM control <<<<< 

 3864 12:40:37.835323  Enable DLL master slave shuffle 

 3865 12:40:37.841675  ============================================================== 

 3866 12:40:37.845262  Gating Mode config

 3867 12:40:37.848491  ============================================================== 

 3868 12:40:37.851800  Config description: 

 3869 12:40:37.861423  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 3870 12:40:37.867893  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 3871 12:40:37.871118  SELPH_MODE            0: By rank         1: By Phase 

 3872 12:40:37.878018  ============================================================== 

 3873 12:40:37.881534  GAT_TRACK_EN                 =  1

 3874 12:40:37.884576  RX_GATING_MODE               =  2

 3875 12:40:37.888376  RX_GATING_TRACK_MODE         =  2

 3876 12:40:37.891371  SELPH_MODE                   =  1

 3877 12:40:37.891476  PICG_EARLY_EN                =  1

 3878 12:40:37.894448  VALID_LAT_VALUE              =  1

 3879 12:40:37.901212  ============================================================== 

 3880 12:40:37.904290  Enter into Gating configuration >>>> 

 3881 12:40:37.908079  Exit from Gating configuration <<<< 

 3882 12:40:37.911422  Enter into  DVFS_PRE_config >>>>> 

 3883 12:40:37.920893  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 3884 12:40:37.924088  Exit from  DVFS_PRE_config <<<<< 

 3885 12:40:37.927861  Enter into PICG configuration >>>> 

 3886 12:40:37.931092  Exit from PICG configuration <<<< 

 3887 12:40:37.934292  [RX_INPUT] configuration >>>>> 

 3888 12:40:37.937345  [RX_INPUT] configuration <<<<< 

 3889 12:40:37.941182  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 3890 12:40:37.947336  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 3891 12:40:37.954556  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 3892 12:40:37.961032  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 3893 12:40:37.964392  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 3894 12:40:37.971170  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 3895 12:40:37.977665  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 3896 12:40:37.981489  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 3897 12:40:37.984416  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 3898 12:40:37.988214  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 3899 12:40:37.991207  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 3900 12:40:37.997952  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3901 12:40:38.001004  =================================== 

 3902 12:40:38.004756  LPDDR4 DRAM CONFIGURATION

 3903 12:40:38.007766  =================================== 

 3904 12:40:38.007845  EX_ROW_EN[0]    = 0x0

 3905 12:40:38.010850  EX_ROW_EN[1]    = 0x0

 3906 12:40:38.010921  LP4Y_EN      = 0x0

 3907 12:40:38.014661  WORK_FSP     = 0x0

 3908 12:40:38.014742  WL           = 0x2

 3909 12:40:38.017997  RL           = 0x2

 3910 12:40:38.018083  BL           = 0x2

 3911 12:40:38.021154  RPST         = 0x0

 3912 12:40:38.021233  RD_PRE       = 0x0

 3913 12:40:38.024213  WR_PRE       = 0x1

 3914 12:40:38.024311  WR_PST       = 0x0

 3915 12:40:38.027610  DBI_WR       = 0x0

 3916 12:40:38.027685  DBI_RD       = 0x0

 3917 12:40:38.030735  OTF          = 0x1

 3918 12:40:38.034542  =================================== 

 3919 12:40:38.037787  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 3920 12:40:38.041411  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 3921 12:40:38.047799  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3922 12:40:38.051185  =================================== 

 3923 12:40:38.051296  LPDDR4 DRAM CONFIGURATION

 3924 12:40:38.054242  =================================== 

 3925 12:40:38.057745  EX_ROW_EN[0]    = 0x10

 3926 12:40:38.060707  EX_ROW_EN[1]    = 0x0

 3927 12:40:38.060815  LP4Y_EN      = 0x0

 3928 12:40:38.064500  WORK_FSP     = 0x0

 3929 12:40:38.064582  WL           = 0x2

 3930 12:40:38.067843  RL           = 0x2

 3931 12:40:38.067913  BL           = 0x2

 3932 12:40:38.071044  RPST         = 0x0

 3933 12:40:38.071120  RD_PRE       = 0x0

 3934 12:40:38.074140  WR_PRE       = 0x1

 3935 12:40:38.074216  WR_PST       = 0x0

 3936 12:40:38.077402  DBI_WR       = 0x0

 3937 12:40:38.077472  DBI_RD       = 0x0

 3938 12:40:38.081218  OTF          = 0x1

 3939 12:40:38.084327  =================================== 

 3940 12:40:38.091190  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 3941 12:40:38.094137  nWR fixed to 30

 3942 12:40:38.094220  [ModeRegInit_LP4] CH0 RK0

 3943 12:40:38.097849  [ModeRegInit_LP4] CH0 RK1

 3944 12:40:38.100909  [ModeRegInit_LP4] CH1 RK0

 3945 12:40:38.103988  [ModeRegInit_LP4] CH1 RK1

 3946 12:40:38.104095  match AC timing 17

 3947 12:40:38.110779  dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1

 3948 12:40:38.114501  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 3949 12:40:38.117645  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

 3950 12:40:38.123981  [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17

 3951 12:40:38.127675  [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)

 3952 12:40:38.127752  ==

 3953 12:40:38.130825  Dram Type= 6, Freq= 0, CH_0, rank 0

 3954 12:40:38.133980  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3955 12:40:38.134054  ==

 3956 12:40:38.141016  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3957 12:40:38.147156  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 3958 12:40:38.151025  [CA 0] Center 35 (5~66) winsize 62

 3959 12:40:38.154178  [CA 1] Center 35 (5~66) winsize 62

 3960 12:40:38.157280  [CA 2] Center 33 (3~64) winsize 62

 3961 12:40:38.160946  [CA 3] Center 33 (2~64) winsize 63

 3962 12:40:38.164065  [CA 4] Center 33 (2~64) winsize 63

 3963 12:40:38.167685  [CA 5] Center 32 (2~63) winsize 62

 3964 12:40:38.167776  

 3965 12:40:38.170961  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 3966 12:40:38.171044  

 3967 12:40:38.174200  [CATrainingPosCal] consider 1 rank data

 3968 12:40:38.177151  u2DelayCellTimex100 = 270/100 ps

 3969 12:40:38.180378  CA0 delay=35 (5~66),Diff = 3 PI (28 cell)

 3970 12:40:38.183649  CA1 delay=35 (5~66),Diff = 3 PI (28 cell)

 3971 12:40:38.187510  CA2 delay=33 (3~64),Diff = 1 PI (9 cell)

 3972 12:40:38.190750  CA3 delay=33 (2~64),Diff = 1 PI (9 cell)

 3973 12:40:38.193937  CA4 delay=33 (2~64),Diff = 1 PI (9 cell)

 3974 12:40:38.197050  CA5 delay=32 (2~63),Diff = 0 PI (0 cell)

 3975 12:40:38.197126  

 3976 12:40:38.204132  CA PerBit enable=1, Macro0, CA PI delay=32

 3977 12:40:38.204251  

 3978 12:40:38.204351  [CBTSetCACLKResult] CA Dly = 32

 3979 12:40:38.207020  CS Dly: 4 (0~35)

 3980 12:40:38.207123  ==

 3981 12:40:38.210804  Dram Type= 6, Freq= 0, CH_0, rank 1

 3982 12:40:38.213922  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3983 12:40:38.214031  ==

 3984 12:40:38.220496  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3985 12:40:38.226962  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 3986 12:40:38.230201  [CA 0] Center 35 (5~66) winsize 62

 3987 12:40:38.233827  [CA 1] Center 35 (5~66) winsize 62

 3988 12:40:38.236901  [CA 2] Center 34 (3~65) winsize 63

 3989 12:40:38.240162  [CA 3] Center 33 (3~64) winsize 62

 3990 12:40:38.244108  [CA 4] Center 32 (2~63) winsize 62

 3991 12:40:38.247193  [CA 5] Center 32 (2~63) winsize 62

 3992 12:40:38.247274  

 3993 12:40:38.250283  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3994 12:40:38.250389  

 3995 12:40:38.254118  [CATrainingPosCal] consider 2 rank data

 3996 12:40:38.257327  u2DelayCellTimex100 = 270/100 ps

 3997 12:40:38.260527  CA0 delay=35 (5~66),Diff = 3 PI (28 cell)

 3998 12:40:38.263581  CA1 delay=35 (5~66),Diff = 3 PI (28 cell)

 3999 12:40:38.267239  CA2 delay=33 (3~64),Diff = 1 PI (9 cell)

 4000 12:40:38.270303  CA3 delay=33 (3~64),Diff = 1 PI (9 cell)

 4001 12:40:38.273490  CA4 delay=32 (2~63),Diff = 0 PI (0 cell)

 4002 12:40:38.277234  CA5 delay=32 (2~63),Diff = 0 PI (0 cell)

 4003 12:40:38.277315  

 4004 12:40:38.283473  CA PerBit enable=1, Macro0, CA PI delay=32

 4005 12:40:38.283596  

 4006 12:40:38.286714  [CBTSetCACLKResult] CA Dly = 32

 4007 12:40:38.286834  CS Dly: 4 (0~36)

 4008 12:40:38.286931  

 4009 12:40:38.290457  ----->DramcWriteLeveling(PI) begin...

 4010 12:40:38.290575  ==

 4011 12:40:38.293714  Dram Type= 6, Freq= 0, CH_0, rank 0

 4012 12:40:38.297070  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4013 12:40:38.297183  ==

 4014 12:40:38.300215  Write leveling (Byte 0): 34 => 34

 4015 12:40:38.303548  Write leveling (Byte 1): 34 => 34

 4016 12:40:38.306587  DramcWriteLeveling(PI) end<-----

 4017 12:40:38.306705  

 4018 12:40:38.306807  ==

 4019 12:40:38.310206  Dram Type= 6, Freq= 0, CH_0, rank 0

 4020 12:40:38.316820  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4021 12:40:38.316946  ==

 4022 12:40:38.317061  [Gating] SW mode calibration

 4023 12:40:38.326995  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4024 12:40:38.330426  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4025 12:40:38.333709   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4026 12:40:38.339989   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4027 12:40:38.343843   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 4028 12:40:38.347060   0  9 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 1)

 4029 12:40:38.353308   0  9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (1 0)

 4030 12:40:38.356582   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4031 12:40:38.359906   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4032 12:40:38.366352   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4033 12:40:38.370060   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4034 12:40:38.373149   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4035 12:40:38.379801   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4036 12:40:38.383170   0 10 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)

 4037 12:40:38.386220   0 10 16 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)

 4038 12:40:38.392788   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4039 12:40:38.396573   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4040 12:40:38.399757   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4041 12:40:38.406714   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4042 12:40:38.409906   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4043 12:40:38.413109   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4044 12:40:38.419517   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 4045 12:40:38.423150   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 4046 12:40:38.426185   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4047 12:40:38.433016   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4048 12:40:38.436222   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4049 12:40:38.439801   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4050 12:40:38.446266   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4051 12:40:38.449336   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4052 12:40:38.453229   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4053 12:40:38.456290   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4054 12:40:38.462714   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4055 12:40:38.466542   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4056 12:40:38.469663   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4057 12:40:38.475968   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4058 12:40:38.479575   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4059 12:40:38.482532   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4060 12:40:38.489391   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 4061 12:40:38.492343   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4062 12:40:38.496210  Total UI for P1: 0, mck2ui 16

 4063 12:40:38.499486  best dqsien dly found for B0: ( 0, 13, 12)

 4064 12:40:38.502686  Total UI for P1: 0, mck2ui 16

 4065 12:40:38.505865  best dqsien dly found for B1: ( 0, 13, 14)

 4066 12:40:38.509140  best DQS0 dly(MCK, UI, PI) = (0, 13, 12)

 4067 12:40:38.512500  best DQS1 dly(MCK, UI, PI) = (0, 13, 14)

 4068 12:40:38.512627  

 4069 12:40:38.515753  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4070 12:40:38.519611  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4071 12:40:38.522838  [Gating] SW calibration Done

 4072 12:40:38.522960  ==

 4073 12:40:38.525771  Dram Type= 6, Freq= 0, CH_0, rank 0

 4074 12:40:38.533000  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4075 12:40:38.533126  ==

 4076 12:40:38.533237  RX Vref Scan: 0

 4077 12:40:38.533343  

 4078 12:40:38.536033  RX Vref 0 -> 0, step: 1

 4079 12:40:38.536150  

 4080 12:40:38.539096  RX Delay -230 -> 252, step: 16

 4081 12:40:38.542577  iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304

 4082 12:40:38.545738  iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320

 4083 12:40:38.549429  iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304

 4084 12:40:38.555597  iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320

 4085 12:40:38.559382  iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320

 4086 12:40:38.562510  iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320

 4087 12:40:38.565908  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4088 12:40:38.572416  iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320

 4089 12:40:38.575611  iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304

 4090 12:40:38.578879  iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304

 4091 12:40:38.582657  iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320

 4092 12:40:38.585551  iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320

 4093 12:40:38.592182  iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304

 4094 12:40:38.595679  iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304

 4095 12:40:38.598643  iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320

 4096 12:40:38.602537  iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320

 4097 12:40:38.605559  ==

 4098 12:40:38.609045  Dram Type= 6, Freq= 0, CH_0, rank 0

 4099 12:40:38.612185  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4100 12:40:38.612307  ==

 4101 12:40:38.612416  DQS Delay:

 4102 12:40:38.615518  DQS0 = 0, DQS1 = 0

 4103 12:40:38.615628  DQM Delay:

 4104 12:40:38.619176  DQM0 = 51, DQM1 = 45

 4105 12:40:38.619282  DQ Delay:

 4106 12:40:38.622449  DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =41

 4107 12:40:38.625583  DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57

 4108 12:40:38.628747  DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41

 4109 12:40:38.631958  DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57

 4110 12:40:38.632052  

 4111 12:40:38.632119  

 4112 12:40:38.632199  ==

 4113 12:40:38.635622  Dram Type= 6, Freq= 0, CH_0, rank 0

 4114 12:40:38.638723  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4115 12:40:38.638822  ==

 4116 12:40:38.638913  

 4117 12:40:38.639001  

 4118 12:40:38.642121  	TX Vref Scan disable

 4119 12:40:38.645105   == TX Byte 0 ==

 4120 12:40:38.648958  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 4121 12:40:38.652300  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 4122 12:40:38.655300   == TX Byte 1 ==

 4123 12:40:38.658974  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 4124 12:40:38.661957  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 4125 12:40:38.662059  ==

 4126 12:40:38.665096  Dram Type= 6, Freq= 0, CH_0, rank 0

 4127 12:40:38.668914  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4128 12:40:38.672180  ==

 4129 12:40:38.672284  

 4130 12:40:38.672377  

 4131 12:40:38.672468  	TX Vref Scan disable

 4132 12:40:38.676054   == TX Byte 0 ==

 4133 12:40:38.679391  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 4134 12:40:38.685842  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 4135 12:40:38.685969   == TX Byte 1 ==

 4136 12:40:38.689020  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 4137 12:40:38.692628  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 4138 12:40:38.695925  

 4139 12:40:38.696026  [DATLAT]

 4140 12:40:38.696120  Freq=600, CH0 RK0

 4141 12:40:38.696211  

 4142 12:40:38.699002  DATLAT Default: 0x9

 4143 12:40:38.699102  0, 0xFFFF, sum = 0

 4144 12:40:38.702403  1, 0xFFFF, sum = 0

 4145 12:40:38.702513  2, 0xFFFF, sum = 0

 4146 12:40:38.705902  3, 0xFFFF, sum = 0

 4147 12:40:38.706028  4, 0xFFFF, sum = 0

 4148 12:40:38.709394  5, 0xFFFF, sum = 0

 4149 12:40:38.712509  6, 0xFFFF, sum = 0

 4150 12:40:38.712620  7, 0xFFFF, sum = 0

 4151 12:40:38.712736  8, 0x0, sum = 1

 4152 12:40:38.715859  9, 0x0, sum = 2

 4153 12:40:38.715972  10, 0x0, sum = 3

 4154 12:40:38.719138  11, 0x0, sum = 4

 4155 12:40:38.719268  best_step = 9

 4156 12:40:38.719338  

 4157 12:40:38.719429  ==

 4158 12:40:38.722391  Dram Type= 6, Freq= 0, CH_0, rank 0

 4159 12:40:38.729021  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4160 12:40:38.729145  ==

 4161 12:40:38.729258  RX Vref Scan: 1

 4162 12:40:38.729365  

 4163 12:40:38.732053  RX Vref 0 -> 0, step: 1

 4164 12:40:38.732174  

 4165 12:40:38.735881  RX Delay -163 -> 252, step: 8

 4166 12:40:38.735961  

 4167 12:40:38.739213  Set Vref, RX VrefLevel [Byte0]: 53

 4168 12:40:38.742303                           [Byte1]: 47

 4169 12:40:38.742391  

 4170 12:40:38.745447  Final RX Vref Byte 0 = 53 to rank0

 4171 12:40:38.748732  Final RX Vref Byte 1 = 47 to rank0

 4172 12:40:38.752309  Final RX Vref Byte 0 = 53 to rank1

 4173 12:40:38.755481  Final RX Vref Byte 1 = 47 to rank1==

 4174 12:40:38.758662  Dram Type= 6, Freq= 0, CH_0, rank 0

 4175 12:40:38.762096  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4176 12:40:38.762183  ==

 4177 12:40:38.765663  DQS Delay:

 4178 12:40:38.765745  DQS0 = 0, DQS1 = 0

 4179 12:40:38.765809  DQM Delay:

 4180 12:40:38.768683  DQM0 = 53, DQM1 = 45

 4181 12:40:38.768782  DQ Delay:

 4182 12:40:38.772225  DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52

 4183 12:40:38.775231  DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =56

 4184 12:40:38.778430  DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40

 4185 12:40:38.781891  DQ12 =48, DQ13 =48, DQ14 =56, DQ15 =52

 4186 12:40:38.781968  

 4187 12:40:38.782033  

 4188 12:40:38.791711  [DQSOSCAuto] RK0, (LSB)MR18= 0x7164, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 388 ps

 4189 12:40:38.795510  CH0 RK0: MR19=808, MR18=7164

 4190 12:40:38.798537  CH0_RK0: MR19=0x808, MR18=0x7164, DQSOSC=388, MR23=63, INC=174, DEC=116

 4191 12:40:38.801712  

 4192 12:40:38.805254  ----->DramcWriteLeveling(PI) begin...

 4193 12:40:38.805355  ==

 4194 12:40:38.808304  Dram Type= 6, Freq= 0, CH_0, rank 1

 4195 12:40:38.812032  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4196 12:40:38.812129  ==

 4197 12:40:38.814995  Write leveling (Byte 0): 34 => 34

 4198 12:40:38.818310  Write leveling (Byte 1): 33 => 33

 4199 12:40:38.821906  DramcWriteLeveling(PI) end<-----

 4200 12:40:38.821993  

 4201 12:40:38.822061  ==

 4202 12:40:38.825091  Dram Type= 6, Freq= 0, CH_0, rank 1

 4203 12:40:38.828404  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4204 12:40:38.828486  ==

 4205 12:40:38.831646  [Gating] SW mode calibration

 4206 12:40:38.838776  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4207 12:40:38.845075  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4208 12:40:38.848334   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4209 12:40:38.851610   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4210 12:40:38.858043   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 4211 12:40:38.861620   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 1)

 4212 12:40:38.865302   0  9 16 | B1->B0 | 2c2c 2727 | 0 0 | (0 0) (0 0)

 4213 12:40:38.872009   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4214 12:40:38.874981   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4215 12:40:38.878457   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4216 12:40:38.881379   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4217 12:40:38.888420   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4218 12:40:38.891810   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4219 12:40:38.894943   0 10 12 | B1->B0 | 2828 2a2a | 0 0 | (0 0) (1 1)

 4220 12:40:38.901377   0 10 16 | B1->B0 | 4040 4444 | 1 0 | (0 0) (0 0)

 4221 12:40:38.905030   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4222 12:40:38.908138   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4223 12:40:38.915002   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4224 12:40:38.918132   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4225 12:40:38.921288   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4226 12:40:38.927865   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4227 12:40:38.931162   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 4228 12:40:38.935086   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)

 4229 12:40:38.941712   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4230 12:40:38.944779   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4231 12:40:38.947781   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4232 12:40:38.955057   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4233 12:40:38.958203   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4234 12:40:38.961454   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4235 12:40:38.967963   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4236 12:40:38.971206   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4237 12:40:38.974572   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4238 12:40:38.981178   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4239 12:40:38.984343   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4240 12:40:38.988097   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4241 12:40:38.994916   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4242 12:40:38.998153   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4243 12:40:39.001431   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 4244 12:40:39.007842   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4245 12:40:39.007940  Total UI for P1: 0, mck2ui 16

 4246 12:40:39.011567  best dqsien dly found for B0: ( 0, 13, 12)

 4247 12:40:39.014932  Total UI for P1: 0, mck2ui 16

 4248 12:40:39.017998  best dqsien dly found for B1: ( 0, 13, 12)

 4249 12:40:39.021529  best DQS0 dly(MCK, UI, PI) = (0, 13, 12)

 4250 12:40:39.027636  best DQS1 dly(MCK, UI, PI) = (0, 13, 12)

 4251 12:40:39.027778  

 4252 12:40:39.031310  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4253 12:40:39.034374  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4254 12:40:39.038212  [Gating] SW calibration Done

 4255 12:40:39.038315  ==

 4256 12:40:39.041439  Dram Type= 6, Freq= 0, CH_0, rank 1

 4257 12:40:39.044703  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4258 12:40:39.044792  ==

 4259 12:40:39.047919  RX Vref Scan: 0

 4260 12:40:39.048010  

 4261 12:40:39.048101  RX Vref 0 -> 0, step: 1

 4262 12:40:39.048166  

 4263 12:40:39.051020  RX Delay -230 -> 252, step: 16

 4264 12:40:39.054238  iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304

 4265 12:40:39.061026  iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304

 4266 12:40:39.064507  iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304

 4267 12:40:39.067583  iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304

 4268 12:40:39.070835  iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320

 4269 12:40:39.077648  iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320

 4270 12:40:39.080709  iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304

 4271 12:40:39.084409  iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304

 4272 12:40:39.087457  iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304

 4273 12:40:39.091028  iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304

 4274 12:40:39.097286  iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304

 4275 12:40:39.100576  iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304

 4276 12:40:39.104441  iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304

 4277 12:40:39.107652  iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304

 4278 12:40:39.114524  iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304

 4279 12:40:39.117751  iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304

 4280 12:40:39.117845  ==

 4281 12:40:39.120963  Dram Type= 6, Freq= 0, CH_0, rank 1

 4282 12:40:39.124113  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4283 12:40:39.124201  ==

 4284 12:40:39.127650  DQS Delay:

 4285 12:40:39.127734  DQS0 = 0, DQS1 = 0

 4286 12:40:39.127801  DQM Delay:

 4287 12:40:39.130847  DQM0 = 53, DQM1 = 43

 4288 12:40:39.130938  DQ Delay:

 4289 12:40:39.133968  DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49

 4290 12:40:39.137588  DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65

 4291 12:40:39.140699  DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33

 4292 12:40:39.143820  DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49

 4293 12:40:39.143968  

 4294 12:40:39.144080  

 4295 12:40:39.144178  ==

 4296 12:40:39.147066  Dram Type= 6, Freq= 0, CH_0, rank 1

 4297 12:40:39.154082  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4298 12:40:39.154224  ==

 4299 12:40:39.154333  

 4300 12:40:39.154425  

 4301 12:40:39.154516  	TX Vref Scan disable

 4302 12:40:39.157314   == TX Byte 0 ==

 4303 12:40:39.161085  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 4304 12:40:39.164247  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 4305 12:40:39.167637   == TX Byte 1 ==

 4306 12:40:39.170629  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 4307 12:40:39.173834  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 4308 12:40:39.177591  ==

 4309 12:40:39.180504  Dram Type= 6, Freq= 0, CH_0, rank 1

 4310 12:40:39.184347  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4311 12:40:39.184433  ==

 4312 12:40:39.184499  

 4313 12:40:39.184561  

 4314 12:40:39.187261  	TX Vref Scan disable

 4315 12:40:39.190598   == TX Byte 0 ==

 4316 12:40:39.193884  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 4317 12:40:39.197018  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 4318 12:40:39.200911   == TX Byte 1 ==

 4319 12:40:39.203821  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 4320 12:40:39.207053  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 4321 12:40:39.207169  

 4322 12:40:39.207270  [DATLAT]

 4323 12:40:39.210255  Freq=600, CH0 RK1

 4324 12:40:39.210362  

 4325 12:40:39.210456  DATLAT Default: 0x9

 4326 12:40:39.214167  0, 0xFFFF, sum = 0

 4327 12:40:39.217142  1, 0xFFFF, sum = 0

 4328 12:40:39.217252  2, 0xFFFF, sum = 0

 4329 12:40:39.220337  3, 0xFFFF, sum = 0

 4330 12:40:39.220453  4, 0xFFFF, sum = 0

 4331 12:40:39.223556  5, 0xFFFF, sum = 0

 4332 12:40:39.223659  6, 0xFFFF, sum = 0

 4333 12:40:39.226834  7, 0xFFFF, sum = 0

 4334 12:40:39.226941  8, 0x0, sum = 1

 4335 12:40:39.230781  9, 0x0, sum = 2

 4336 12:40:39.230889  10, 0x0, sum = 3

 4337 12:40:39.230990  11, 0x0, sum = 4

 4338 12:40:39.233698  best_step = 9

 4339 12:40:39.233790  

 4340 12:40:39.233885  ==

 4341 12:40:39.236731  Dram Type= 6, Freq= 0, CH_0, rank 1

 4342 12:40:39.240261  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4343 12:40:39.240372  ==

 4344 12:40:39.243301  RX Vref Scan: 0

 4345 12:40:39.243419  

 4346 12:40:39.243515  RX Vref 0 -> 0, step: 1

 4347 12:40:39.246882  

 4348 12:40:39.246965  RX Delay -163 -> 252, step: 8

 4349 12:40:39.254232  iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288

 4350 12:40:39.257868  iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280

 4351 12:40:39.261185  iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288

 4352 12:40:39.264476  iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288

 4353 12:40:39.267742  iDelay=197, Bit 4, Center 52 (-91 ~ 196) 288

 4354 12:40:39.274168  iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288

 4355 12:40:39.277387  iDelay=197, Bit 6, Center 60 (-75 ~ 196) 272

 4356 12:40:39.280668  iDelay=197, Bit 7, Center 60 (-75 ~ 196) 272

 4357 12:40:39.284411  iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288

 4358 12:40:39.290954  iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288

 4359 12:40:39.294310  iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280

 4360 12:40:39.297535  iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280

 4361 12:40:39.301076  iDelay=197, Bit 12, Center 48 (-91 ~ 188) 280

 4362 12:40:39.303959  iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288

 4363 12:40:39.310546  iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280

 4364 12:40:39.314202  iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288

 4365 12:40:39.314324  ==

 4366 12:40:39.317472  Dram Type= 6, Freq= 0, CH_0, rank 1

 4367 12:40:39.320563  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4368 12:40:39.320664  ==

 4369 12:40:39.323652  DQS Delay:

 4370 12:40:39.323751  DQS0 = 0, DQS1 = 0

 4371 12:40:39.323849  DQM Delay:

 4372 12:40:39.327515  DQM0 = 53, DQM1 = 46

 4373 12:40:39.327610  DQ Delay:

 4374 12:40:39.330768  DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52

 4375 12:40:39.334146  DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60

 4376 12:40:39.337354  DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40

 4377 12:40:39.340407  DQ12 =48, DQ13 =52, DQ14 =56, DQ15 =52

 4378 12:40:39.340506  

 4379 12:40:39.340595  

 4380 12:40:39.350686  [DQSOSCAuto] RK1, (LSB)MR18= 0x6423, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps

 4381 12:40:39.350778  CH0 RK1: MR19=808, MR18=6423

 4382 12:40:39.357576  CH0_RK1: MR19=0x808, MR18=0x6423, DQSOSC=391, MR23=63, INC=171, DEC=114

 4383 12:40:39.360862  [RxdqsGatingPostProcess] freq 600

 4384 12:40:39.367169  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 4385 12:40:39.371094  Pre-setting of DQS Precalculation

 4386 12:40:39.373735  [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9

 4387 12:40:39.373818  ==

 4388 12:40:39.377065  Dram Type= 6, Freq= 0, CH_1, rank 0

 4389 12:40:39.380852  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4390 12:40:39.384031  ==

 4391 12:40:39.387245  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4392 12:40:39.393808  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 4393 12:40:39.397552  [CA 0] Center 35 (5~66) winsize 62

 4394 12:40:39.400483  [CA 1] Center 36 (6~67) winsize 62

 4395 12:40:39.404154  [CA 2] Center 34 (4~65) winsize 62

 4396 12:40:39.407175  [CA 3] Center 34 (4~65) winsize 62

 4397 12:40:39.411059  [CA 4] Center 34 (4~65) winsize 62

 4398 12:40:39.413805  [CA 5] Center 34 (4~64) winsize 61

 4399 12:40:39.413888  

 4400 12:40:39.417556  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 4401 12:40:39.417655  

 4402 12:40:39.420447  [CATrainingPosCal] consider 1 rank data

 4403 12:40:39.424103  u2DelayCellTimex100 = 270/100 ps

 4404 12:40:39.427241  CA0 delay=35 (5~66),Diff = 1 PI (9 cell)

 4405 12:40:39.430439  CA1 delay=36 (6~67),Diff = 2 PI (19 cell)

 4406 12:40:39.433555  CA2 delay=34 (4~65),Diff = 0 PI (0 cell)

 4407 12:40:39.437355  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 4408 12:40:39.443696  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 4409 12:40:39.447395  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 4410 12:40:39.447497  

 4411 12:40:39.450465  CA PerBit enable=1, Macro0, CA PI delay=34

 4412 12:40:39.450580  

 4413 12:40:39.453622  [CBTSetCACLKResult] CA Dly = 34

 4414 12:40:39.453735  CS Dly: 5 (0~36)

 4415 12:40:39.453872  ==

 4416 12:40:39.457096  Dram Type= 6, Freq= 0, CH_1, rank 1

 4417 12:40:39.463523  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4418 12:40:39.463630  ==

 4419 12:40:39.467157  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4420 12:40:39.473751  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 4421 12:40:39.476948  [CA 0] Center 36 (5~67) winsize 63

 4422 12:40:39.480307  [CA 1] Center 36 (5~67) winsize 63

 4423 12:40:39.483887  [CA 2] Center 34 (4~65) winsize 62

 4424 12:40:39.487117  [CA 3] Center 34 (4~65) winsize 62

 4425 12:40:39.490469  [CA 4] Center 34 (4~65) winsize 62

 4426 12:40:39.493628  [CA 5] Center 34 (3~65) winsize 63

 4427 12:40:39.493749  

 4428 12:40:39.496872  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 4429 12:40:39.496999  

 4430 12:40:39.500039  [CATrainingPosCal] consider 2 rank data

 4431 12:40:39.503883  u2DelayCellTimex100 = 270/100 ps

 4432 12:40:39.507082  CA0 delay=35 (5~66),Diff = 1 PI (9 cell)

 4433 12:40:39.510346  CA1 delay=36 (6~67),Diff = 2 PI (19 cell)

 4434 12:40:39.513792  CA2 delay=34 (4~65),Diff = 0 PI (0 cell)

 4435 12:40:39.520541  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 4436 12:40:39.524230  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 4437 12:40:39.527010  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 4438 12:40:39.527129  

 4439 12:40:39.530150  CA PerBit enable=1, Macro0, CA PI delay=34

 4440 12:40:39.530276  

 4441 12:40:39.533698  [CBTSetCACLKResult] CA Dly = 34

 4442 12:40:39.533808  CS Dly: 5 (0~37)

 4443 12:40:39.533929  

 4444 12:40:39.536707  ----->DramcWriteLeveling(PI) begin...

 4445 12:40:39.536867  ==

 4446 12:40:39.540485  Dram Type= 6, Freq= 0, CH_1, rank 0

 4447 12:40:39.546982  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4448 12:40:39.547122  ==

 4449 12:40:39.550216  Write leveling (Byte 0): 30 => 30

 4450 12:40:39.553954  Write leveling (Byte 1): 31 => 31

 4451 12:40:39.554095  DramcWriteLeveling(PI) end<-----

 4452 12:40:39.554222  

 4453 12:40:39.556982  ==

 4454 12:40:39.560219  Dram Type= 6, Freq= 0, CH_1, rank 0

 4455 12:40:39.563897  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4456 12:40:39.564013  ==

 4457 12:40:39.566999  [Gating] SW mode calibration

 4458 12:40:39.573227  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4459 12:40:39.577095  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4460 12:40:39.583580   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4461 12:40:39.586881   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4462 12:40:39.589934   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4463 12:40:39.597158   0  9 12 | B1->B0 | 3030 2c2c | 0 0 | (1 0) (1 0)

 4464 12:40:39.600376   0  9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4465 12:40:39.603546   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4466 12:40:39.610133   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4467 12:40:39.613205   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4468 12:40:39.616429   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4469 12:40:39.623175   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4470 12:40:39.626647   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4471 12:40:39.630277   0 10 12 | B1->B0 | 3737 3c3c | 0 0 | (1 1) (1 1)

 4472 12:40:39.636590   0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4473 12:40:39.640225   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4474 12:40:39.643118   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4475 12:40:39.650109   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4476 12:40:39.653300   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4477 12:40:39.656481   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4478 12:40:39.660271   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4479 12:40:39.666709   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 4480 12:40:39.669691   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4481 12:40:39.673307   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4482 12:40:39.679681   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4483 12:40:39.683462   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4484 12:40:39.686681   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4485 12:40:39.693006   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4486 12:40:39.696868   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4487 12:40:39.700013   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4488 12:40:39.706405   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4489 12:40:39.709742   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4490 12:40:39.712851   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4491 12:40:39.720084   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4492 12:40:39.723209   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4493 12:40:39.726243   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4494 12:40:39.732837   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4495 12:40:39.736436   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 4496 12:40:39.739522   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4497 12:40:39.742732  Total UI for P1: 0, mck2ui 16

 4498 12:40:39.746573  best dqsien dly found for B0: ( 0, 13, 12)

 4499 12:40:39.749814  Total UI for P1: 0, mck2ui 16

 4500 12:40:39.753150  best dqsien dly found for B1: ( 0, 13, 14)

 4501 12:40:39.756175  best DQS0 dly(MCK, UI, PI) = (0, 13, 12)

 4502 12:40:39.759420  best DQS1 dly(MCK, UI, PI) = (0, 13, 14)

 4503 12:40:39.759557  

 4504 12:40:39.765969  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4505 12:40:39.769740  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4506 12:40:39.769832  [Gating] SW calibration Done

 4507 12:40:39.772809  ==

 4508 12:40:39.776475  Dram Type= 6, Freq= 0, CH_1, rank 0

 4509 12:40:39.779435  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4510 12:40:39.779549  ==

 4511 12:40:39.779650  RX Vref Scan: 0

 4512 12:40:39.779749  

 4513 12:40:39.783032  RX Vref 0 -> 0, step: 1

 4514 12:40:39.783162  

 4515 12:40:39.786080  RX Delay -230 -> 252, step: 16

 4516 12:40:39.789388  iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320

 4517 12:40:39.792613  iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320

 4518 12:40:39.799407  iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320

 4519 12:40:39.802512  iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320

 4520 12:40:39.806021  iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304

 4521 12:40:39.809147  iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320

 4522 12:40:39.816168  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4523 12:40:39.819339  iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304

 4524 12:40:39.822523  iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304

 4525 12:40:39.825684  iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304

 4526 12:40:39.829405  iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304

 4527 12:40:39.836103  iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320

 4528 12:40:39.839094  iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320

 4529 12:40:39.842773  iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304

 4530 12:40:39.845926  iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304

 4531 12:40:39.852360  iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320

 4532 12:40:39.852454  ==

 4533 12:40:39.855961  Dram Type= 6, Freq= 0, CH_1, rank 0

 4534 12:40:39.859101  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4535 12:40:39.859176  ==

 4536 12:40:39.859238  DQS Delay:

 4537 12:40:39.862736  DQS0 = 0, DQS1 = 0

 4538 12:40:39.862807  DQM Delay:

 4539 12:40:39.865847  DQM0 = 49, DQM1 = 46

 4540 12:40:39.865924  DQ Delay:

 4541 12:40:39.869135  DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41

 4542 12:40:39.872298  DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49

 4543 12:40:39.875461  DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41

 4544 12:40:39.879168  DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57

 4545 12:40:39.879243  

 4546 12:40:39.879304  

 4547 12:40:39.879362  ==

 4548 12:40:39.882165  Dram Type= 6, Freq= 0, CH_1, rank 0

 4549 12:40:39.885766  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4550 12:40:39.885851  ==

 4551 12:40:39.889050  

 4552 12:40:39.889126  

 4553 12:40:39.889189  	TX Vref Scan disable

 4554 12:40:39.892066   == TX Byte 0 ==

 4555 12:40:39.895894  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4556 12:40:39.899055  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4557 12:40:39.902238   == TX Byte 1 ==

 4558 12:40:39.905457  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4559 12:40:39.908693  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4560 12:40:39.908823  ==

 4561 12:40:39.911989  Dram Type= 6, Freq= 0, CH_1, rank 0

 4562 12:40:39.919019  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4563 12:40:39.919152  ==

 4564 12:40:39.919244  

 4565 12:40:39.919307  

 4566 12:40:39.919365  	TX Vref Scan disable

 4567 12:40:39.923538   == TX Byte 0 ==

 4568 12:40:39.926723  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4569 12:40:39.930018  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4570 12:40:39.933966   == TX Byte 1 ==

 4571 12:40:39.936904  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4572 12:40:39.943601  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4573 12:40:39.943689  

 4574 12:40:39.943774  [DATLAT]

 4575 12:40:39.943854  Freq=600, CH1 RK0

 4576 12:40:39.943934  

 4577 12:40:39.946688  DATLAT Default: 0x9

 4578 12:40:39.946774  0, 0xFFFF, sum = 0

 4579 12:40:39.950433  1, 0xFFFF, sum = 0

 4580 12:40:39.950524  2, 0xFFFF, sum = 0

 4581 12:40:39.953373  3, 0xFFFF, sum = 0

 4582 12:40:39.956527  4, 0xFFFF, sum = 0

 4583 12:40:39.956631  5, 0xFFFF, sum = 0

 4584 12:40:39.960223  6, 0xFFFF, sum = 0

 4585 12:40:39.960310  7, 0xFFFF, sum = 0

 4586 12:40:39.963487  8, 0x0, sum = 1

 4587 12:40:39.963564  9, 0x0, sum = 2

 4588 12:40:39.963629  10, 0x0, sum = 3

 4589 12:40:39.966657  11, 0x0, sum = 4

 4590 12:40:39.966736  best_step = 9

 4591 12:40:39.966799  

 4592 12:40:39.966898  ==

 4593 12:40:39.970401  Dram Type= 6, Freq= 0, CH_1, rank 0

 4594 12:40:39.976808  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4595 12:40:39.976902  ==

 4596 12:40:39.976966  RX Vref Scan: 1

 4597 12:40:39.977027  

 4598 12:40:39.980242  RX Vref 0 -> 0, step: 1

 4599 12:40:39.980341  

 4600 12:40:39.983305  RX Delay -163 -> 252, step: 8

 4601 12:40:39.983407  

 4602 12:40:39.987120  Set Vref, RX VrefLevel [Byte0]: 53

 4603 12:40:39.989923                           [Byte1]: 53

 4604 12:40:39.990005  

 4605 12:40:39.993652  Final RX Vref Byte 0 = 53 to rank0

 4606 12:40:39.996699  Final RX Vref Byte 1 = 53 to rank0

 4607 12:40:40.000356  Final RX Vref Byte 0 = 53 to rank1

 4608 12:40:40.003453  Final RX Vref Byte 1 = 53 to rank1==

 4609 12:40:40.006534  Dram Type= 6, Freq= 0, CH_1, rank 0

 4610 12:40:40.009833  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4611 12:40:40.009951  ==

 4612 12:40:40.013092  DQS Delay:

 4613 12:40:40.013165  DQS0 = 0, DQS1 = 0

 4614 12:40:40.013229  DQM Delay:

 4615 12:40:40.016927  DQM0 = 47, DQM1 = 45

 4616 12:40:40.017002  DQ Delay:

 4617 12:40:40.020058  DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44

 4618 12:40:40.023365  DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48

 4619 12:40:40.026659  DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =36

 4620 12:40:40.030246  DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56

 4621 12:40:40.030326  

 4622 12:40:40.030389  

 4623 12:40:40.040153  [DQSOSCAuto] RK0, (LSB)MR18= 0x4c71, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps

 4624 12:40:40.040232  CH1 RK0: MR19=808, MR18=4C71

 4625 12:40:40.046750  CH1_RK0: MR19=0x808, MR18=0x4C71, DQSOSC=388, MR23=63, INC=174, DEC=116

 4626 12:40:40.046856  

 4627 12:40:40.049855  ----->DramcWriteLeveling(PI) begin...

 4628 12:40:40.049932  ==

 4629 12:40:40.053598  Dram Type= 6, Freq= 0, CH_1, rank 1

 4630 12:40:40.060305  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4631 12:40:40.060424  ==

 4632 12:40:40.063383  Write leveling (Byte 0): 30 => 30

 4633 12:40:40.066978  Write leveling (Byte 1): 30 => 30

 4634 12:40:40.067085  DramcWriteLeveling(PI) end<-----

 4635 12:40:40.070132  

 4636 12:40:40.070230  ==

 4637 12:40:40.073333  Dram Type= 6, Freq= 0, CH_1, rank 1

 4638 12:40:40.077023  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4639 12:40:40.077100  ==

 4640 12:40:40.080353  [Gating] SW mode calibration

 4641 12:40:40.086871  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4642 12:40:40.090092  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4643 12:40:40.096902   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4644 12:40:40.099795   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4645 12:40:40.103201   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4646 12:40:40.109760   0  9 12 | B1->B0 | 2828 2f2f | 1 1 | (0 0) (1 1)

 4647 12:40:40.113289   0  9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4648 12:40:40.116576   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4649 12:40:40.123044   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4650 12:40:40.126735   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4651 12:40:40.130620   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4652 12:40:40.136943   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4653 12:40:40.140128   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4654 12:40:40.143406   0 10 12 | B1->B0 | 3939 3635 | 0 1 | (0 0) (0 0)

 4655 12:40:40.150405   0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4656 12:40:40.153250   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4657 12:40:40.156708   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4658 12:40:40.160531   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4659 12:40:40.166555   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4660 12:40:40.170258   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4661 12:40:40.173867   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4662 12:40:40.180153   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 4663 12:40:40.183283   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4664 12:40:40.187044   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4665 12:40:40.193486   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4666 12:40:40.196884   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4667 12:40:40.199847   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4668 12:40:40.206635   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4669 12:40:40.209567   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4670 12:40:40.213185   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4671 12:40:40.219740   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4672 12:40:40.222971   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4673 12:40:40.226223   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4674 12:40:40.233254   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4675 12:40:40.235899   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4676 12:40:40.239447   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4677 12:40:40.246030   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4678 12:40:40.249842   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 4679 12:40:40.253098   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4680 12:40:40.256306  Total UI for P1: 0, mck2ui 16

 4681 12:40:40.259438  best dqsien dly found for B0: ( 0, 13, 14)

 4682 12:40:40.263014  Total UI for P1: 0, mck2ui 16

 4683 12:40:40.265968  best dqsien dly found for B1: ( 0, 13, 12)

 4684 12:40:40.269803  best DQS0 dly(MCK, UI, PI) = (0, 13, 14)

 4685 12:40:40.273103  best DQS1 dly(MCK, UI, PI) = (0, 13, 12)

 4686 12:40:40.273189  

 4687 12:40:40.279606  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4688 12:40:40.282852  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4689 12:40:40.282935  [Gating] SW calibration Done

 4690 12:40:40.285991  ==

 4691 12:40:40.289721  Dram Type= 6, Freq= 0, CH_1, rank 1

 4692 12:40:40.292946  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4693 12:40:40.293030  ==

 4694 12:40:40.293098  RX Vref Scan: 0

 4695 12:40:40.293159  

 4696 12:40:40.296044  RX Vref 0 -> 0, step: 1

 4697 12:40:40.296156  

 4698 12:40:40.300033  RX Delay -230 -> 252, step: 16

 4699 12:40:40.303070  iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304

 4700 12:40:40.306130  iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304

 4701 12:40:40.313119  iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304

 4702 12:40:40.316145  iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304

 4703 12:40:40.319713  iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304

 4704 12:40:40.322840  iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320

 4705 12:40:40.326182  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4706 12:40:40.333068  iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304

 4707 12:40:40.336154  iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304

 4708 12:40:40.339545  iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320

 4709 12:40:40.342591  iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304

 4710 12:40:40.349825  iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320

 4711 12:40:40.352945  iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320

 4712 12:40:40.356062  iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320

 4713 12:40:40.359267  iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304

 4714 12:40:40.366151  iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320

 4715 12:40:40.366275  ==

 4716 12:40:40.369152  Dram Type= 6, Freq= 0, CH_1, rank 1

 4717 12:40:40.372775  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4718 12:40:40.372885  ==

 4719 12:40:40.373043  DQS Delay:

 4720 12:40:40.375688  DQS0 = 0, DQS1 = 0

 4721 12:40:40.375761  DQM Delay:

 4722 12:40:40.379410  DQM0 = 49, DQM1 = 48

 4723 12:40:40.379510  DQ Delay:

 4724 12:40:40.382485  DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49

 4725 12:40:40.386039  DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49

 4726 12:40:40.389243  DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41

 4727 12:40:40.392325  DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57

 4728 12:40:40.392408  

 4729 12:40:40.392472  

 4730 12:40:40.392538  ==

 4731 12:40:40.395483  Dram Type= 6, Freq= 0, CH_1, rank 1

 4732 12:40:40.399471  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4733 12:40:40.399548  ==

 4734 12:40:40.399611  

 4735 12:40:40.402667  

 4736 12:40:40.402750  	TX Vref Scan disable

 4737 12:40:40.405961   == TX Byte 0 ==

 4738 12:40:40.408932  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4739 12:40:40.412721  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4740 12:40:40.416126   == TX Byte 1 ==

 4741 12:40:40.419394  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4742 12:40:40.422492  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4743 12:40:40.422580  ==

 4744 12:40:40.425578  Dram Type= 6, Freq= 0, CH_1, rank 1

 4745 12:40:40.432020  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4746 12:40:40.432139  ==

 4747 12:40:40.432247  

 4748 12:40:40.432337  

 4749 12:40:40.432412  	TX Vref Scan disable

 4750 12:40:40.436882   == TX Byte 0 ==

 4751 12:40:40.440398  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4752 12:40:40.443492  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4753 12:40:40.446747   == TX Byte 1 ==

 4754 12:40:40.450051  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4755 12:40:40.453207  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4756 12:40:40.457188  

 4757 12:40:40.457272  [DATLAT]

 4758 12:40:40.457336  Freq=600, CH1 RK1

 4759 12:40:40.457397  

 4760 12:40:40.460261  DATLAT Default: 0x9

 4761 12:40:40.460359  0, 0xFFFF, sum = 0

 4762 12:40:40.463591  1, 0xFFFF, sum = 0

 4763 12:40:40.463695  2, 0xFFFF, sum = 0

 4764 12:40:40.467048  3, 0xFFFF, sum = 0

 4765 12:40:40.469999  4, 0xFFFF, sum = 0

 4766 12:40:40.470075  5, 0xFFFF, sum = 0

 4767 12:40:40.473093  6, 0xFFFF, sum = 0

 4768 12:40:40.473205  7, 0xFFFF, sum = 0

 4769 12:40:40.473300  8, 0x0, sum = 1

 4770 12:40:40.476500  9, 0x0, sum = 2

 4771 12:40:40.476603  10, 0x0, sum = 3

 4772 12:40:40.479876  11, 0x0, sum = 4

 4773 12:40:40.479965  best_step = 9

 4774 12:40:40.480028  

 4775 12:40:40.480086  ==

 4776 12:40:40.483457  Dram Type= 6, Freq= 0, CH_1, rank 1

 4777 12:40:40.490178  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4778 12:40:40.490255  ==

 4779 12:40:40.490318  RX Vref Scan: 0

 4780 12:40:40.490379  

 4781 12:40:40.493211  RX Vref 0 -> 0, step: 1

 4782 12:40:40.493290  

 4783 12:40:40.496440  RX Delay -163 -> 252, step: 8

 4784 12:40:40.500142  iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288

 4785 12:40:40.506583  iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288

 4786 12:40:40.509862  iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288

 4787 12:40:40.512916  iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288

 4788 12:40:40.516867  iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288

 4789 12:40:40.520111  iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288

 4790 12:40:40.526523  iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288

 4791 12:40:40.529722  iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296

 4792 12:40:40.533323  iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296

 4793 12:40:40.536118  iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288

 4794 12:40:40.539783  iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296

 4795 12:40:40.546425  iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296

 4796 12:40:40.550004  iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304

 4797 12:40:40.553122  iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288

 4798 12:40:40.556145  iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288

 4799 12:40:40.563242  iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296

 4800 12:40:40.563350  ==

 4801 12:40:40.566443  Dram Type= 6, Freq= 0, CH_1, rank 1

 4802 12:40:40.569639  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4803 12:40:40.569709  ==

 4804 12:40:40.569788  DQS Delay:

 4805 12:40:40.572849  DQS0 = 0, DQS1 = 0

 4806 12:40:40.572944  DQM Delay:

 4807 12:40:40.575984  DQM0 = 48, DQM1 = 46

 4808 12:40:40.576053  DQ Delay:

 4809 12:40:40.579956  DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44

 4810 12:40:40.583034  DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48

 4811 12:40:40.586185  DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40

 4812 12:40:40.589164  DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56

 4813 12:40:40.589267  

 4814 12:40:40.589335  

 4815 12:40:40.595870  [DQSOSCAuto] RK1, (LSB)MR18= 0x6b22, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps

 4816 12:40:40.599497  CH1 RK1: MR19=808, MR18=6B22

 4817 12:40:40.605660  CH1_RK1: MR19=0x808, MR18=0x6B22, DQSOSC=389, MR23=63, INC=173, DEC=115

 4818 12:40:40.609469  [RxdqsGatingPostProcess] freq 600

 4819 12:40:40.616198  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 4820 12:40:40.619419  Pre-setting of DQS Precalculation

 4821 12:40:40.622737  [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9

 4822 12:40:40.629037  sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5

 4823 12:40:40.635757  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 4824 12:40:40.635869  

 4825 12:40:40.635945  

 4826 12:40:40.639223  [Calibration Summary] 1200 Mbps

 4827 12:40:40.642913  CH 0, Rank 0

 4828 12:40:40.642999  SW Impedance     : PASS

 4829 12:40:40.645732  DUTY Scan        : NO K

 4830 12:40:40.649367  ZQ Calibration   : PASS

 4831 12:40:40.649498  Jitter Meter     : NO K

 4832 12:40:40.652236  CBT Training     : PASS

 4833 12:40:40.655925  Write leveling   : PASS

 4834 12:40:40.656048  RX DQS gating    : PASS

 4835 12:40:40.659112  RX DQ/DQS(RDDQC) : PASS

 4836 12:40:40.659226  TX DQ/DQS        : PASS

 4837 12:40:40.662330  RX DATLAT        : PASS

 4838 12:40:40.666164  RX DQ/DQS(Engine): PASS

 4839 12:40:40.666251  TX OE            : NO K

 4840 12:40:40.669354  All Pass.

 4841 12:40:40.669443  

 4842 12:40:40.669511  CH 0, Rank 1

 4843 12:40:40.672777  SW Impedance     : PASS

 4844 12:40:40.672857  DUTY Scan        : NO K

 4845 12:40:40.675829  ZQ Calibration   : PASS

 4846 12:40:40.679159  Jitter Meter     : NO K

 4847 12:40:40.679241  CBT Training     : PASS

 4848 12:40:40.682333  Write leveling   : PASS

 4849 12:40:40.685462  RX DQS gating    : PASS

 4850 12:40:40.685539  RX DQ/DQS(RDDQC) : PASS

 4851 12:40:40.688927  TX DQ/DQS        : PASS

 4852 12:40:40.692493  RX DATLAT        : PASS

 4853 12:40:40.692569  RX DQ/DQS(Engine): PASS

 4854 12:40:40.695483  TX OE            : NO K

 4855 12:40:40.695578  All Pass.

 4856 12:40:40.695643  

 4857 12:40:40.698654  CH 1, Rank 0

 4858 12:40:40.698745  SW Impedance     : PASS

 4859 12:40:40.702497  DUTY Scan        : NO K

 4860 12:40:40.705887  ZQ Calibration   : PASS

 4861 12:40:40.705973  Jitter Meter     : NO K

 4862 12:40:40.708922  CBT Training     : PASS

 4863 12:40:40.709019  Write leveling   : PASS

 4864 12:40:40.712682  RX DQS gating    : PASS

 4865 12:40:40.715832  RX DQ/DQS(RDDQC) : PASS

 4866 12:40:40.715929  TX DQ/DQS        : PASS

 4867 12:40:40.718827  RX DATLAT        : PASS

 4868 12:40:40.721955  RX DQ/DQS(Engine): PASS

 4869 12:40:40.722055  TX OE            : NO K

 4870 12:40:40.725853  All Pass.

 4871 12:40:40.725934  

 4872 12:40:40.726000  CH 1, Rank 1

 4873 12:40:40.729060  SW Impedance     : PASS

 4874 12:40:40.729143  DUTY Scan        : NO K

 4875 12:40:40.732259  ZQ Calibration   : PASS

 4876 12:40:40.735504  Jitter Meter     : NO K

 4877 12:40:40.735582  CBT Training     : PASS

 4878 12:40:40.738779  Write leveling   : PASS

 4879 12:40:40.742083  RX DQS gating    : PASS

 4880 12:40:40.742160  RX DQ/DQS(RDDQC) : PASS

 4881 12:40:40.745771  TX DQ/DQS        : PASS

 4882 12:40:40.748867  RX DATLAT        : PASS

 4883 12:40:40.748947  RX DQ/DQS(Engine): PASS

 4884 12:40:40.752030  TX OE            : NO K

 4885 12:40:40.752107  All Pass.

 4886 12:40:40.752178  

 4887 12:40:40.755573  DramC Write-DBI off

 4888 12:40:40.758689  	PER_BANK_REFRESH: Hybrid Mode

 4889 12:40:40.758766  TX_TRACKING: ON

 4890 12:40:40.768742  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1

 4891 12:40:40.771843  [FAST_K] Save calibration result to emmc

 4892 12:40:40.775614  dramc_set_vcore_voltage set vcore to 662500

 4893 12:40:40.778853  Read voltage for 933, 3

 4894 12:40:40.778930  Vio18 = 0

 4895 12:40:40.778995  Vcore = 662500

 4896 12:40:40.782069  Vdram = 0

 4897 12:40:40.782154  Vddq = 0

 4898 12:40:40.782218  Vmddr = 0

 4899 12:40:40.788397  [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0

 4900 12:40:40.791658  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 4901 12:40:40.795574  MEM_TYPE=3, freq_sel=17

 4902 12:40:40.798833  sv_algorithm_assistance_LP4_1600 

 4903 12:40:40.802070  ============ PULL DRAM RESETB DOWN ============

 4904 12:40:40.805192  ========== PULL DRAM RESETB DOWN end =========

 4905 12:40:40.811677  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 4906 12:40:40.815108  =================================== 

 4907 12:40:40.815190  LPDDR4 DRAM CONFIGURATION

 4908 12:40:40.818777  =================================== 

 4909 12:40:40.822008  EX_ROW_EN[0]    = 0x0

 4910 12:40:40.825522  EX_ROW_EN[1]    = 0x0

 4911 12:40:40.825602  LP4Y_EN      = 0x0

 4912 12:40:40.828659  WORK_FSP     = 0x0

 4913 12:40:40.828737  WL           = 0x3

 4914 12:40:40.831857  RL           = 0x3

 4915 12:40:40.831929  BL           = 0x2

 4916 12:40:40.835132  RPST         = 0x0

 4917 12:40:40.835210  RD_PRE       = 0x0

 4918 12:40:40.838377  WR_PRE       = 0x1

 4919 12:40:40.838453  WR_PST       = 0x0

 4920 12:40:40.841694  DBI_WR       = 0x0

 4921 12:40:40.841770  DBI_RD       = 0x0

 4922 12:40:40.844978  OTF          = 0x1

 4923 12:40:40.848303  =================================== 

 4924 12:40:40.851977  =================================== 

 4925 12:40:40.852064  ANA top config

 4926 12:40:40.855171  =================================== 

 4927 12:40:40.858338  DLL_ASYNC_EN            =  0

 4928 12:40:40.861480  ALL_SLAVE_EN            =  1

 4929 12:40:40.861557  NEW_RANK_MODE           =  1

 4930 12:40:40.864995  DLL_IDLE_MODE           =  1

 4931 12:40:40.868103  LP45_APHY_COMB_EN       =  1

 4932 12:40:40.871975  TX_ODT_DIS              =  1

 4933 12:40:40.874905  NEW_8X_MODE             =  1

 4934 12:40:40.878644  =================================== 

 4935 12:40:40.881600  =================================== 

 4936 12:40:40.881692  data_rate                  = 1866

 4937 12:40:40.885370  CKR                        = 1

 4938 12:40:40.888276  DQ_P2S_RATIO               = 8

 4939 12:40:40.891419  =================================== 

 4940 12:40:40.895266  CA_P2S_RATIO               = 8

 4941 12:40:40.898563  DQ_CA_OPEN                 = 0

 4942 12:40:40.901903  DQ_SEMI_OPEN               = 0

 4943 12:40:40.901994  CA_SEMI_OPEN               = 0

 4944 12:40:40.904977  CA_FULL_RATE               = 0

 4945 12:40:40.908233  DQ_CKDIV4_EN               = 1

 4946 12:40:40.911455  CA_CKDIV4_EN               = 1

 4947 12:40:40.915043  CA_PREDIV_EN               = 0

 4948 12:40:40.918083  PH8_DLY                    = 0

 4949 12:40:40.918170  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 4950 12:40:40.921628  DQ_AAMCK_DIV               = 4

 4951 12:40:40.924587  CA_AAMCK_DIV               = 4

 4952 12:40:40.928209  CA_ADMCK_DIV               = 4

 4953 12:40:40.931162  DQ_TRACK_CA_EN             = 0

 4954 12:40:40.934726  CA_PICK                    = 933

 4955 12:40:40.937955  CA_MCKIO                   = 933

 4956 12:40:40.938031  MCKIO_SEMI                 = 0

 4957 12:40:40.941170  PLL_FREQ                   = 3732

 4958 12:40:40.945077  DQ_UI_PI_RATIO             = 32

 4959 12:40:40.948261  CA_UI_PI_RATIO             = 0

 4960 12:40:40.951454  =================================== 

 4961 12:40:40.954772  =================================== 

 4962 12:40:40.957855  memory_type:LPDDR4         

 4963 12:40:40.957928  GP_NUM     : 10       

 4964 12:40:40.961195  SRAM_EN    : 1       

 4965 12:40:40.961268  MD32_EN    : 0       

 4966 12:40:40.964418  =================================== 

 4967 12:40:40.967672  [ANA_INIT] >>>>>>>>>>>>>> 

 4968 12:40:40.971192  <<<<<< [CONFIGURE PHASE]: ANA_TX

 4969 12:40:40.974900  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 4970 12:40:40.977886  =================================== 

 4971 12:40:40.981654  data_rate = 1866,PCW = 0X8f00

 4972 12:40:40.984579  =================================== 

 4973 12:40:40.987652  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 4974 12:40:40.994500  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 4975 12:40:40.997868  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 4976 12:40:41.004609  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 4977 12:40:41.007803  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 4978 12:40:41.010767  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 4979 12:40:41.010859  [ANA_INIT] flow start 

 4980 12:40:41.014008  [ANA_INIT] PLL >>>>>>>> 

 4981 12:40:41.017275  [ANA_INIT] PLL <<<<<<<< 

 4982 12:40:41.017379  [ANA_INIT] MIDPI >>>>>>>> 

 4983 12:40:41.020717  [ANA_INIT] MIDPI <<<<<<<< 

 4984 12:40:41.024339  [ANA_INIT] DLL >>>>>>>> 

 4985 12:40:41.024446  [ANA_INIT] flow end 

 4986 12:40:41.031147  ============ LP4 DIFF to SE enter ============

 4987 12:40:41.034350  ============ LP4 DIFF to SE exit  ============

 4988 12:40:41.037222  [ANA_INIT] <<<<<<<<<<<<< 

 4989 12:40:41.040774  [Flow] Enable top DCM control >>>>> 

 4990 12:40:41.043977  [Flow] Enable top DCM control <<<<< 

 4991 12:40:41.044080  Enable DLL master slave shuffle 

 4992 12:40:41.050982  ============================================================== 

 4993 12:40:41.054334  Gating Mode config

 4994 12:40:41.057484  ============================================================== 

 4995 12:40:41.060669  Config description: 

 4996 12:40:41.070475  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 4997 12:40:41.077353  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 4998 12:40:41.080411  SELPH_MODE            0: By rank         1: By Phase 

 4999 12:40:41.087246  ============================================================== 

 5000 12:40:41.090265  GAT_TRACK_EN                 =  1

 5001 12:40:41.094155  RX_GATING_MODE               =  2

 5002 12:40:41.097048  RX_GATING_TRACK_MODE         =  2

 5003 12:40:41.100956  SELPH_MODE                   =  1

 5004 12:40:41.101069  PICG_EARLY_EN                =  1

 5005 12:40:41.104053  VALID_LAT_VALUE              =  1

 5006 12:40:41.110724  ============================================================== 

 5007 12:40:41.113545  Enter into Gating configuration >>>> 

 5008 12:40:41.116758  Exit from Gating configuration <<<< 

 5009 12:40:41.120636  Enter into  DVFS_PRE_config >>>>> 

 5010 12:40:41.130507  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 5011 12:40:41.133332  Exit from  DVFS_PRE_config <<<<< 

 5012 12:40:41.137016  Enter into PICG configuration >>>> 

 5013 12:40:41.140273  Exit from PICG configuration <<<< 

 5014 12:40:41.143354  [RX_INPUT] configuration >>>>> 

 5015 12:40:41.146942  [RX_INPUT] configuration <<<<< 

 5016 12:40:41.150100  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 5017 12:40:41.156507  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 5018 12:40:41.163517  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 5019 12:40:41.170017  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 5020 12:40:41.176655  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 5021 12:40:41.183352  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 5022 12:40:41.186719  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 5023 12:40:41.190144  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 5024 12:40:41.193495  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 5025 12:40:41.196740  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 5026 12:40:41.203473  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 5027 12:40:41.206429  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 5028 12:40:41.209661  =================================== 

 5029 12:40:41.213480  LPDDR4 DRAM CONFIGURATION

 5030 12:40:41.216656  =================================== 

 5031 12:40:41.216754  EX_ROW_EN[0]    = 0x0

 5032 12:40:41.219875  EX_ROW_EN[1]    = 0x0

 5033 12:40:41.219955  LP4Y_EN      = 0x0

 5034 12:40:41.223201  WORK_FSP     = 0x0

 5035 12:40:41.223305  WL           = 0x3

 5036 12:40:41.226395  RL           = 0x3

 5037 12:40:41.229854  BL           = 0x2

 5038 12:40:41.229939  RPST         = 0x0

 5039 12:40:41.233256  RD_PRE       = 0x0

 5040 12:40:41.233329  WR_PRE       = 0x1

 5041 12:40:41.236383  WR_PST       = 0x0

 5042 12:40:41.236459  DBI_WR       = 0x0

 5043 12:40:41.239408  DBI_RD       = 0x0

 5044 12:40:41.239509  OTF          = 0x1

 5045 12:40:41.243163  =================================== 

 5046 12:40:41.246212  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 5047 12:40:41.253079  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 5048 12:40:41.256225  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 5049 12:40:41.260097  =================================== 

 5050 12:40:41.263316  LPDDR4 DRAM CONFIGURATION

 5051 12:40:41.266584  =================================== 

 5052 12:40:41.266667  EX_ROW_EN[0]    = 0x10

 5053 12:40:41.269648  EX_ROW_EN[1]    = 0x0

 5054 12:40:41.269725  LP4Y_EN      = 0x0

 5055 12:40:41.272884  WORK_FSP     = 0x0

 5056 12:40:41.272961  WL           = 0x3

 5057 12:40:41.276330  RL           = 0x3

 5058 12:40:41.276406  BL           = 0x2

 5059 12:40:41.280188  RPST         = 0x0

 5060 12:40:41.280267  RD_PRE       = 0x0

 5061 12:40:41.283278  WR_PRE       = 0x1

 5062 12:40:41.283358  WR_PST       = 0x0

 5063 12:40:41.286421  DBI_WR       = 0x0

 5064 12:40:41.286522  DBI_RD       = 0x0

 5065 12:40:41.290028  OTF          = 0x1

 5066 12:40:41.293138  =================================== 

 5067 12:40:41.299817  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 5068 12:40:41.302949  nWR fixed to 30

 5069 12:40:41.306398  [ModeRegInit_LP4] CH0 RK0

 5070 12:40:41.306479  [ModeRegInit_LP4] CH0 RK1

 5071 12:40:41.309826  [ModeRegInit_LP4] CH1 RK0

 5072 12:40:41.312727  [ModeRegInit_LP4] CH1 RK1

 5073 12:40:41.312832  match AC timing 9

 5074 12:40:41.319819  dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1

 5075 12:40:41.322901  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 5076 12:40:41.326071  [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10

 5077 12:40:41.333161  [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21

 5078 12:40:41.336435  [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)

 5079 12:40:41.336538  ==

 5080 12:40:41.339428  Dram Type= 6, Freq= 0, CH_0, rank 0

 5081 12:40:41.343024  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5082 12:40:41.343128  ==

 5083 12:40:41.349819  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5084 12:40:41.356637  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 5085 12:40:41.359651  [CA 0] Center 37 (6~68) winsize 63

 5086 12:40:41.362739  [CA 1] Center 37 (7~68) winsize 62

 5087 12:40:41.366688  [CA 2] Center 34 (4~65) winsize 62

 5088 12:40:41.369963  [CA 3] Center 34 (3~65) winsize 63

 5089 12:40:41.372991  [CA 4] Center 33 (3~64) winsize 62

 5090 12:40:41.376230  [CA 5] Center 32 (2~62) winsize 61

 5091 12:40:41.376307  

 5092 12:40:41.379500  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 5093 12:40:41.379602  

 5094 12:40:41.382744  [CATrainingPosCal] consider 1 rank data

 5095 12:40:41.385938  u2DelayCellTimex100 = 270/100 ps

 5096 12:40:41.389849  CA0 delay=37 (6~68),Diff = 5 PI (31 cell)

 5097 12:40:41.393051  CA1 delay=37 (7~68),Diff = 5 PI (31 cell)

 5098 12:40:41.396209  CA2 delay=34 (4~65),Diff = 2 PI (12 cell)

 5099 12:40:41.399239  CA3 delay=34 (3~65),Diff = 2 PI (12 cell)

 5100 12:40:41.403021  CA4 delay=33 (3~64),Diff = 1 PI (6 cell)

 5101 12:40:41.406059  CA5 delay=32 (2~62),Diff = 0 PI (0 cell)

 5102 12:40:41.409630  

 5103 12:40:41.412674  CA PerBit enable=1, Macro0, CA PI delay=32

 5104 12:40:41.412778  

 5105 12:40:41.416347  [CBTSetCACLKResult] CA Dly = 32

 5106 12:40:41.416481  CS Dly: 5 (0~36)

 5107 12:40:41.416577  ==

 5108 12:40:41.419425  Dram Type= 6, Freq= 0, CH_0, rank 1

 5109 12:40:41.422673  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5110 12:40:41.422765  ==

 5111 12:40:41.429614  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5112 12:40:41.436079  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5113 12:40:41.439279  [CA 0] Center 37 (6~68) winsize 63

 5114 12:40:41.442553  [CA 1] Center 37 (7~68) winsize 62

 5115 12:40:41.446300  [CA 2] Center 34 (4~65) winsize 62

 5116 12:40:41.449529  [CA 3] Center 34 (3~65) winsize 63

 5117 12:40:41.452576  [CA 4] Center 33 (3~63) winsize 61

 5118 12:40:41.456162  [CA 5] Center 32 (2~62) winsize 61

 5119 12:40:41.456258  

 5120 12:40:41.459156  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5121 12:40:41.459231  

 5122 12:40:41.462933  [CATrainingPosCal] consider 2 rank data

 5123 12:40:41.466031  u2DelayCellTimex100 = 270/100 ps

 5124 12:40:41.469081  CA0 delay=37 (6~68),Diff = 5 PI (31 cell)

 5125 12:40:41.472364  CA1 delay=37 (7~68),Diff = 5 PI (31 cell)

 5126 12:40:41.475946  CA2 delay=34 (4~65),Diff = 2 PI (12 cell)

 5127 12:40:41.479156  CA3 delay=34 (3~65),Diff = 2 PI (12 cell)

 5128 12:40:41.482546  CA4 delay=33 (3~63),Diff = 1 PI (6 cell)

 5129 12:40:41.488931  CA5 delay=32 (2~62),Diff = 0 PI (0 cell)

 5130 12:40:41.489011  

 5131 12:40:41.492824  CA PerBit enable=1, Macro0, CA PI delay=32

 5132 12:40:41.492927  

 5133 12:40:41.495982  [CBTSetCACLKResult] CA Dly = 32

 5134 12:40:41.496062  CS Dly: 6 (0~38)

 5135 12:40:41.496127  

 5136 12:40:41.499156  ----->DramcWriteLeveling(PI) begin...

 5137 12:40:41.499234  ==

 5138 12:40:41.502177  Dram Type= 6, Freq= 0, CH_0, rank 0

 5139 12:40:41.509207  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5140 12:40:41.509303  ==

 5141 12:40:41.512164  Write leveling (Byte 0): 33 => 33

 5142 12:40:41.512277  Write leveling (Byte 1): 29 => 29

 5143 12:40:41.515987  DramcWriteLeveling(PI) end<-----

 5144 12:40:41.516081  

 5145 12:40:41.516143  ==

 5146 12:40:41.518912  Dram Type= 6, Freq= 0, CH_0, rank 0

 5147 12:40:41.525700  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5148 12:40:41.525812  ==

 5149 12:40:41.528934  [Gating] SW mode calibration

 5150 12:40:41.535300  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5151 12:40:41.539140  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5152 12:40:41.545696   0 14  0 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)

 5153 12:40:41.549048   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5154 12:40:41.552080   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5155 12:40:41.558560   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5156 12:40:41.562161   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5157 12:40:41.565764   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5158 12:40:41.572289   0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)

 5159 12:40:41.575310   0 14 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)

 5160 12:40:41.578538   0 15  0 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (0 0)

 5161 12:40:41.585510   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5162 12:40:41.588739   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5163 12:40:41.591961   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5164 12:40:41.595073   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5165 12:40:41.602223   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5166 12:40:41.605481   0 15 24 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)

 5167 12:40:41.608669   0 15 28 | B1->B0 | 2a2a 3f3f | 1 1 | (0 0) (0 0)

 5168 12:40:41.615541   1  0  0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)

 5169 12:40:41.618480   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5170 12:40:41.622211   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5171 12:40:41.628403   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5172 12:40:41.632169   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5173 12:40:41.635129   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5174 12:40:41.641897   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5175 12:40:41.645137   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 5176 12:40:41.648267   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 5177 12:40:41.654778   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5178 12:40:41.658646   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5179 12:40:41.661721   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5180 12:40:41.668340   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5181 12:40:41.671364   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5182 12:40:41.675105   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5183 12:40:41.681912   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5184 12:40:41.684661   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5185 12:40:41.688358   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5186 12:40:41.694828   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5187 12:40:41.698116   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5188 12:40:41.701484   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5189 12:40:41.708053   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5190 12:40:41.711304   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 5191 12:40:41.714514   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 5192 12:40:41.718358  Total UI for P1: 0, mck2ui 16

 5193 12:40:41.721558  best dqsien dly found for B0: ( 1,  2, 24)

 5194 12:40:41.728230   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 5195 12:40:41.731279   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5196 12:40:41.734933  Total UI for P1: 0, mck2ui 16

 5197 12:40:41.738067  best dqsien dly found for B1: ( 1,  2, 30)

 5198 12:40:41.741731  best DQS0 dly(MCK, UI, PI) = (1, 2, 24)

 5199 12:40:41.744731  best DQS1 dly(MCK, UI, PI) = (1, 2, 30)

 5200 12:40:41.744846  

 5201 12:40:41.747986  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)

 5202 12:40:41.751203  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)

 5203 12:40:41.754454  [Gating] SW calibration Done

 5204 12:40:41.754564  ==

 5205 12:40:41.758345  Dram Type= 6, Freq= 0, CH_0, rank 0

 5206 12:40:41.761574  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5207 12:40:41.761684  ==

 5208 12:40:41.764671  RX Vref Scan: 0

 5209 12:40:41.764769  

 5210 12:40:41.767886  RX Vref 0 -> 0, step: 1

 5211 12:40:41.768015  

 5212 12:40:41.768117  RX Delay -80 -> 252, step: 8

 5213 12:40:41.774503  iDelay=208, Bit 0, Center 103 (8 ~ 199) 192

 5214 12:40:41.777706  iDelay=208, Bit 1, Center 107 (16 ~ 199) 184

 5215 12:40:41.781115  iDelay=208, Bit 2, Center 99 (8 ~ 191) 184

 5216 12:40:41.784697  iDelay=208, Bit 3, Center 99 (8 ~ 191) 184

 5217 12:40:41.787878  iDelay=208, Bit 4, Center 107 (16 ~ 199) 184

 5218 12:40:41.791389  iDelay=208, Bit 5, Center 91 (0 ~ 183) 184

 5219 12:40:41.797740  iDelay=208, Bit 6, Center 115 (24 ~ 207) 184

 5220 12:40:41.801042  iDelay=208, Bit 7, Center 115 (24 ~ 207) 184

 5221 12:40:41.804301  iDelay=208, Bit 8, Center 87 (0 ~ 175) 176

 5222 12:40:41.808199  iDelay=208, Bit 9, Center 87 (0 ~ 175) 176

 5223 12:40:41.811430  iDelay=208, Bit 10, Center 95 (8 ~ 183) 176

 5224 12:40:41.814815  iDelay=208, Bit 11, Center 91 (0 ~ 183) 184

 5225 12:40:41.821331  iDelay=208, Bit 12, Center 99 (8 ~ 191) 184

 5226 12:40:41.824502  iDelay=208, Bit 13, Center 103 (16 ~ 191) 176

 5227 12:40:41.827638  iDelay=208, Bit 14, Center 103 (16 ~ 191) 176

 5228 12:40:41.831107  iDelay=208, Bit 15, Center 99 (8 ~ 191) 184

 5229 12:40:41.831216  ==

 5230 12:40:41.834665  Dram Type= 6, Freq= 0, CH_0, rank 0

 5231 12:40:41.840948  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5232 12:40:41.841029  ==

 5233 12:40:41.841113  DQS Delay:

 5234 12:40:41.841193  DQS0 = 0, DQS1 = 0

 5235 12:40:41.844661  DQM Delay:

 5236 12:40:41.844759  DQM0 = 104, DQM1 = 95

 5237 12:40:41.847678  DQ Delay:

 5238 12:40:41.850784  DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99

 5239 12:40:41.854542  DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115

 5240 12:40:41.857688  DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91

 5241 12:40:41.860948  DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99

 5242 12:40:41.861023  

 5243 12:40:41.861104  

 5244 12:40:41.861180  ==

 5245 12:40:41.864168  Dram Type= 6, Freq= 0, CH_0, rank 0

 5246 12:40:41.867514  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5247 12:40:41.867614  ==

 5248 12:40:41.867713  

 5249 12:40:41.867811  

 5250 12:40:41.871036  	TX Vref Scan disable

 5251 12:40:41.874040   == TX Byte 0 ==

 5252 12:40:41.877280  Update DQ  dly =717 (2 ,6, 13)  DQ  OEN =(2 ,3)

 5253 12:40:41.880699  Update DQM dly =717 (2 ,6, 13)  DQM OEN =(2 ,3)

 5254 12:40:41.883866   == TX Byte 1 ==

 5255 12:40:41.887464  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5256 12:40:41.890920  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5257 12:40:41.890994  ==

 5258 12:40:41.894251  Dram Type= 6, Freq= 0, CH_0, rank 0

 5259 12:40:41.900216  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5260 12:40:41.900286  ==

 5261 12:40:41.900346  

 5262 12:40:41.900409  

 5263 12:40:41.900494  	TX Vref Scan disable

 5264 12:40:41.904487   == TX Byte 0 ==

 5265 12:40:41.907466  Update DQ  dly =716 (2 ,6, 12)  DQ  OEN =(2 ,3)

 5266 12:40:41.914560  Update DQM dly =716 (2 ,6, 12)  DQM OEN =(2 ,3)

 5267 12:40:41.914634   == TX Byte 1 ==

 5268 12:40:41.917844  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5269 12:40:41.924403  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5270 12:40:41.924480  

 5271 12:40:41.924543  [DATLAT]

 5272 12:40:41.924601  Freq=933, CH0 RK0

 5273 12:40:41.924666  

 5274 12:40:41.927627  DATLAT Default: 0xd

 5275 12:40:41.927719  0, 0xFFFF, sum = 0

 5276 12:40:41.930690  1, 0xFFFF, sum = 0

 5277 12:40:41.930759  2, 0xFFFF, sum = 0

 5278 12:40:41.934462  3, 0xFFFF, sum = 0

 5279 12:40:41.937948  4, 0xFFFF, sum = 0

 5280 12:40:41.938022  5, 0xFFFF, sum = 0

 5281 12:40:41.941085  6, 0xFFFF, sum = 0

 5282 12:40:41.941195  7, 0xFFFF, sum = 0

 5283 12:40:41.944164  8, 0xFFFF, sum = 0

 5284 12:40:41.944232  9, 0xFFFF, sum = 0

 5285 12:40:41.947598  10, 0x0, sum = 1

 5286 12:40:41.947690  11, 0x0, sum = 2

 5287 12:40:41.950908  12, 0x0, sum = 3

 5288 12:40:41.950978  13, 0x0, sum = 4

 5289 12:40:41.951037  best_step = 11

 5290 12:40:41.951109  

 5291 12:40:41.954347  ==

 5292 12:40:41.957595  Dram Type= 6, Freq= 0, CH_0, rank 0

 5293 12:40:41.960749  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5294 12:40:41.960867  ==

 5295 12:40:41.960928  RX Vref Scan: 1

 5296 12:40:41.960984  

 5297 12:40:41.964116  RX Vref 0 -> 0, step: 1

 5298 12:40:41.964181  

 5299 12:40:41.967862  RX Delay -45 -> 252, step: 4

 5300 12:40:41.967931  

 5301 12:40:41.971168  Set Vref, RX VrefLevel [Byte0]: 53

 5302 12:40:41.974290                           [Byte1]: 47

 5303 12:40:41.974387  

 5304 12:40:41.978083  Final RX Vref Byte 0 = 53 to rank0

 5305 12:40:41.981196  Final RX Vref Byte 1 = 47 to rank0

 5306 12:40:41.984404  Final RX Vref Byte 0 = 53 to rank1

 5307 12:40:41.988047  Final RX Vref Byte 1 = 47 to rank1==

 5308 12:40:41.991212  Dram Type= 6, Freq= 0, CH_0, rank 0

 5309 12:40:41.994524  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5310 12:40:41.994596  ==

 5311 12:40:41.997672  DQS Delay:

 5312 12:40:41.997744  DQS0 = 0, DQS1 = 0

 5313 12:40:42.001001  DQM Delay:

 5314 12:40:42.001071  DQM0 = 104, DQM1 = 94

 5315 12:40:42.001131  DQ Delay:

 5316 12:40:42.004067  DQ0 =106, DQ1 =104, DQ2 =102, DQ3 =102

 5317 12:40:42.010961  DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110

 5318 12:40:42.011036  DQ8 =84, DQ9 =84, DQ10 =94, DQ11 =90

 5319 12:40:42.017624  DQ12 =100, DQ13 =98, DQ14 =106, DQ15 =102

 5320 12:40:42.017723  

 5321 12:40:42.017811  

 5322 12:40:42.024056  [DQSOSCAuto] RK0, (LSB)MR18= 0x342c, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 405 ps

 5323 12:40:42.027190  CH0 RK0: MR19=505, MR18=342C

 5324 12:40:42.034310  CH0_RK0: MR19=0x505, MR18=0x342C, DQSOSC=405, MR23=63, INC=66, DEC=44

 5325 12:40:42.034384  

 5326 12:40:42.037617  ----->DramcWriteLeveling(PI) begin...

 5327 12:40:42.037687  ==

 5328 12:40:42.040715  Dram Type= 6, Freq= 0, CH_0, rank 1

 5329 12:40:42.043804  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5330 12:40:42.043878  ==

 5331 12:40:42.047399  Write leveling (Byte 0): 33 => 33

 5332 12:40:42.050583  Write leveling (Byte 1): 31 => 31

 5333 12:40:42.054116  DramcWriteLeveling(PI) end<-----

 5334 12:40:42.054193  

 5335 12:40:42.054257  ==

 5336 12:40:42.057102  Dram Type= 6, Freq= 0, CH_0, rank 1

 5337 12:40:42.060242  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5338 12:40:42.060324  ==

 5339 12:40:42.063770  [Gating] SW mode calibration

 5340 12:40:42.070222  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5341 12:40:42.077393  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5342 12:40:42.080522   0 14  0 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 1)

 5343 12:40:42.087026   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5344 12:40:42.090726   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5345 12:40:42.093723   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5346 12:40:42.100453   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5347 12:40:42.104097   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5348 12:40:42.107210   0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)

 5349 12:40:42.110145   0 14 28 | B1->B0 | 2626 2626 | 0 0 | (0 1) (0 0)

 5350 12:40:42.117255   0 15  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5351 12:40:42.120273   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5352 12:40:42.123438   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5353 12:40:42.130244   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5354 12:40:42.133661   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5355 12:40:42.136788   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5356 12:40:42.143351   0 15 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)

 5357 12:40:42.147058   0 15 28 | B1->B0 | 3b3b 3939 | 0 0 | (0 0) (0 0)

 5358 12:40:42.150300   1  0  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5359 12:40:42.157094   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5360 12:40:42.160074   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5361 12:40:42.163916   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5362 12:40:42.170505   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5363 12:40:42.173806   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5364 12:40:42.176987   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5365 12:40:42.183276   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5366 12:40:42.186995   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5367 12:40:42.190201   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5368 12:40:42.196733   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5369 12:40:42.199712   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5370 12:40:42.203449   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5371 12:40:42.209803   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5372 12:40:42.213389   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5373 12:40:42.216623   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5374 12:40:42.223574   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5375 12:40:42.226672   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5376 12:40:42.229810   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5377 12:40:42.236688   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5378 12:40:42.240069   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5379 12:40:42.243274   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5380 12:40:42.249660   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5381 12:40:42.252879   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5382 12:40:42.256657   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5383 12:40:42.259736  Total UI for P1: 0, mck2ui 16

 5384 12:40:42.263438  best dqsien dly found for B0: ( 1,  2, 28)

 5385 12:40:42.266390  Total UI for P1: 0, mck2ui 16

 5386 12:40:42.270122  best dqsien dly found for B1: ( 1,  2, 28)

 5387 12:40:42.273169  best DQS0 dly(MCK, UI, PI) = (1, 2, 28)

 5388 12:40:42.276122  best DQS1 dly(MCK, UI, PI) = (1, 2, 28)

 5389 12:40:42.276204  

 5390 12:40:42.279365  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)

 5391 12:40:42.286524  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)

 5392 12:40:42.286620  [Gating] SW calibration Done

 5393 12:40:42.286684  ==

 5394 12:40:42.289743  Dram Type= 6, Freq= 0, CH_0, rank 1

 5395 12:40:42.296070  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5396 12:40:42.296157  ==

 5397 12:40:42.296221  RX Vref Scan: 0

 5398 12:40:42.296282  

 5399 12:40:42.299458  RX Vref 0 -> 0, step: 1

 5400 12:40:42.299540  

 5401 12:40:42.303146  RX Delay -80 -> 252, step: 8

 5402 12:40:42.306399  iDelay=208, Bit 0, Center 103 (8 ~ 199) 192

 5403 12:40:42.309573  iDelay=208, Bit 1, Center 107 (16 ~ 199) 184

 5404 12:40:42.312988  iDelay=208, Bit 2, Center 99 (8 ~ 191) 184

 5405 12:40:42.316037  iDelay=208, Bit 3, Center 99 (8 ~ 191) 184

 5406 12:40:42.322688  iDelay=208, Bit 4, Center 107 (16 ~ 199) 184

 5407 12:40:42.326325  iDelay=208, Bit 5, Center 95 (0 ~ 191) 192

 5408 12:40:42.329508  iDelay=208, Bit 6, Center 107 (16 ~ 199) 184

 5409 12:40:42.332729  iDelay=208, Bit 7, Center 115 (24 ~ 207) 184

 5410 12:40:42.335834  iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184

 5411 12:40:42.342798  iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184

 5412 12:40:42.346090  iDelay=208, Bit 10, Center 95 (8 ~ 183) 176

 5413 12:40:42.349291  iDelay=208, Bit 11, Center 87 (0 ~ 175) 176

 5414 12:40:42.353077  iDelay=208, Bit 12, Center 95 (8 ~ 183) 176

 5415 12:40:42.356316  iDelay=208, Bit 13, Center 99 (8 ~ 191) 184

 5416 12:40:42.359496  iDelay=208, Bit 14, Center 99 (8 ~ 191) 184

 5417 12:40:42.362702  iDelay=208, Bit 15, Center 99 (8 ~ 191) 184

 5418 12:40:42.366496  ==

 5419 12:40:42.369562  Dram Type= 6, Freq= 0, CH_0, rank 1

 5420 12:40:42.372610  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5421 12:40:42.372696  ==

 5422 12:40:42.372764  DQS Delay:

 5423 12:40:42.375804  DQS0 = 0, DQS1 = 0

 5424 12:40:42.375888  DQM Delay:

 5425 12:40:42.379552  DQM0 = 104, DQM1 = 92

 5426 12:40:42.379637  DQ Delay:

 5427 12:40:42.382619  DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99

 5428 12:40:42.386284  DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =115

 5429 12:40:42.389605  DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87

 5430 12:40:42.392545  DQ12 =95, DQ13 =99, DQ14 =99, DQ15 =99

 5431 12:40:42.392674  

 5432 12:40:42.392741  

 5433 12:40:42.392811  ==

 5434 12:40:42.395880  Dram Type= 6, Freq= 0, CH_0, rank 1

 5435 12:40:42.399136  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5436 12:40:42.399250  ==

 5437 12:40:42.402276  

 5438 12:40:42.402360  

 5439 12:40:42.402426  	TX Vref Scan disable

 5440 12:40:42.405623   == TX Byte 0 ==

 5441 12:40:42.409336  Update DQ  dly =717 (2 ,6, 13)  DQ  OEN =(2 ,3)

 5442 12:40:42.412528  Update DQM dly =717 (2 ,6, 13)  DQM OEN =(2 ,3)

 5443 12:40:42.415571   == TX Byte 1 ==

 5444 12:40:42.419212  Update DQ  dly =714 (2 ,6, 10)  DQ  OEN =(2 ,3)

 5445 12:40:42.422397  Update DQM dly =714 (2 ,6, 10)  DQM OEN =(2 ,3)

 5446 12:40:42.422485  ==

 5447 12:40:42.426409  Dram Type= 6, Freq= 0, CH_0, rank 1

 5448 12:40:42.432277  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5449 12:40:42.432366  ==

 5450 12:40:42.432433  

 5451 12:40:42.432494  

 5452 12:40:42.432553  	TX Vref Scan disable

 5453 12:40:42.436474   == TX Byte 0 ==

 5454 12:40:42.440343  Update DQ  dly =717 (2 ,6, 13)  DQ  OEN =(2 ,3)

 5455 12:40:42.446536  Update DQM dly =717 (2 ,6, 13)  DQM OEN =(2 ,3)

 5456 12:40:42.446623   == TX Byte 1 ==

 5457 12:40:42.449786  Update DQ  dly =714 (2 ,6, 10)  DQ  OEN =(2 ,3)

 5458 12:40:42.457055  Update DQM dly =714 (2 ,6, 10)  DQM OEN =(2 ,3)

 5459 12:40:42.457140  

 5460 12:40:42.457205  [DATLAT]

 5461 12:40:42.457266  Freq=933, CH0 RK1

 5462 12:40:42.457325  

 5463 12:40:42.460019  DATLAT Default: 0xb

 5464 12:40:42.460092  0, 0xFFFF, sum = 0

 5465 12:40:42.463294  1, 0xFFFF, sum = 0

 5466 12:40:42.463362  2, 0xFFFF, sum = 0

 5467 12:40:42.466507  3, 0xFFFF, sum = 0

 5468 12:40:42.469836  4, 0xFFFF, sum = 0

 5469 12:40:42.469908  5, 0xFFFF, sum = 0

 5470 12:40:42.473480  6, 0xFFFF, sum = 0

 5471 12:40:42.473553  7, 0xFFFF, sum = 0

 5472 12:40:42.476569  8, 0xFFFF, sum = 0

 5473 12:40:42.476643  9, 0xFFFF, sum = 0

 5474 12:40:42.479566  10, 0x0, sum = 1

 5475 12:40:42.479637  11, 0x0, sum = 2

 5476 12:40:42.482811  12, 0x0, sum = 3

 5477 12:40:42.482896  13, 0x0, sum = 4

 5478 12:40:42.482955  best_step = 11

 5479 12:40:42.483012  

 5480 12:40:42.486464  ==

 5481 12:40:42.489626  Dram Type= 6, Freq= 0, CH_0, rank 1

 5482 12:40:42.493206  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5483 12:40:42.493283  ==

 5484 12:40:42.493347  RX Vref Scan: 0

 5485 12:40:42.493407  

 5486 12:40:42.496304  RX Vref 0 -> 0, step: 1

 5487 12:40:42.496373  

 5488 12:40:42.499475  RX Delay -53 -> 252, step: 4

 5489 12:40:42.506061  iDelay=199, Bit 0, Center 102 (15 ~ 190) 176

 5490 12:40:42.509357  iDelay=199, Bit 1, Center 106 (19 ~ 194) 176

 5491 12:40:42.513084  iDelay=199, Bit 2, Center 102 (15 ~ 190) 176

 5492 12:40:42.516555  iDelay=199, Bit 3, Center 100 (11 ~ 190) 180

 5493 12:40:42.519479  iDelay=199, Bit 4, Center 106 (19 ~ 194) 176

 5494 12:40:42.522492  iDelay=199, Bit 5, Center 98 (11 ~ 186) 176

 5495 12:40:42.529602  iDelay=199, Bit 6, Center 108 (23 ~ 194) 172

 5496 12:40:42.532934  iDelay=199, Bit 7, Center 112 (27 ~ 198) 172

 5497 12:40:42.535998  iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172

 5498 12:40:42.539481  iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168

 5499 12:40:42.542785  iDelay=199, Bit 10, Center 94 (11 ~ 178) 168

 5500 12:40:42.549743  iDelay=199, Bit 11, Center 88 (7 ~ 170) 164

 5501 12:40:42.552930  iDelay=199, Bit 12, Center 100 (19 ~ 182) 164

 5502 12:40:42.556180  iDelay=199, Bit 13, Center 98 (15 ~ 182) 168

 5503 12:40:42.559447  iDelay=199, Bit 14, Center 102 (19 ~ 186) 168

 5504 12:40:42.562620  iDelay=199, Bit 15, Center 102 (19 ~ 186) 168

 5505 12:40:42.566345  ==

 5506 12:40:42.566430  Dram Type= 6, Freq= 0, CH_0, rank 1

 5507 12:40:42.572708  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5508 12:40:42.572793  ==

 5509 12:40:42.572867  DQS Delay:

 5510 12:40:42.576505  DQS0 = 0, DQS1 = 0

 5511 12:40:42.576590  DQM Delay:

 5512 12:40:42.576656  DQM0 = 104, DQM1 = 93

 5513 12:40:42.579481  DQ Delay:

 5514 12:40:42.582638  DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =100

 5515 12:40:42.586292  DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112

 5516 12:40:42.589690  DQ8 =84, DQ9 =82, DQ10 =94, DQ11 =88

 5517 12:40:42.593072  DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =102

 5518 12:40:42.593159  

 5519 12:40:42.593226  

 5520 12:40:42.599443  [DQSOSCAuto] RK1, (LSB)MR18= 0x2d05, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 407 ps

 5521 12:40:42.602544  CH0 RK1: MR19=505, MR18=2D05

 5522 12:40:42.609589  CH0_RK1: MR19=0x505, MR18=0x2D05, DQSOSC=407, MR23=63, INC=65, DEC=43

 5523 12:40:42.612724  [RxdqsGatingPostProcess] freq 933

 5524 12:40:42.619368  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 5525 12:40:42.622905  best DQS0 dly(2T, 0.5T) = (0, 10)

 5526 12:40:42.625926  best DQS1 dly(2T, 0.5T) = (0, 10)

 5527 12:40:42.629255  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5528 12:40:42.629341  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5529 12:40:42.632763  best DQS0 dly(2T, 0.5T) = (0, 10)

 5530 12:40:42.636002  best DQS1 dly(2T, 0.5T) = (0, 10)

 5531 12:40:42.639222  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5532 12:40:42.642659  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5533 12:40:42.645617  Pre-setting of DQS Precalculation

 5534 12:40:42.652646  [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11

 5535 12:40:42.652733  ==

 5536 12:40:42.655603  Dram Type= 6, Freq= 0, CH_1, rank 0

 5537 12:40:42.659247  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5538 12:40:42.659334  ==

 5539 12:40:42.665729  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5540 12:40:42.672092  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 5541 12:40:42.675890  [CA 0] Center 36 (6~67) winsize 62

 5542 12:40:42.679176  [CA 1] Center 36 (6~67) winsize 62

 5543 12:40:42.682422  [CA 2] Center 34 (4~65) winsize 62

 5544 12:40:42.685384  [CA 3] Center 34 (4~65) winsize 62

 5545 12:40:42.685494  [CA 4] Center 34 (4~64) winsize 61

 5546 12:40:42.688945  [CA 5] Center 33 (3~64) winsize 62

 5547 12:40:42.689038  

 5548 12:40:42.695428  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 5549 12:40:42.695538  

 5550 12:40:42.699181  [CATrainingPosCal] consider 1 rank data

 5551 12:40:42.702248  u2DelayCellTimex100 = 270/100 ps

 5552 12:40:42.705866  CA0 delay=36 (6~67),Diff = 3 PI (18 cell)

 5553 12:40:42.708912  CA1 delay=36 (6~67),Diff = 3 PI (18 cell)

 5554 12:40:42.712173  CA2 delay=34 (4~65),Diff = 1 PI (6 cell)

 5555 12:40:42.715406  CA3 delay=34 (4~65),Diff = 1 PI (6 cell)

 5556 12:40:42.718714  CA4 delay=34 (4~64),Diff = 1 PI (6 cell)

 5557 12:40:42.722306  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 5558 12:40:42.722413  

 5559 12:40:42.725913  CA PerBit enable=1, Macro0, CA PI delay=33

 5560 12:40:42.726025  

 5561 12:40:42.729009  [CBTSetCACLKResult] CA Dly = 33

 5562 12:40:42.732166  CS Dly: 6 (0~37)

 5563 12:40:42.732270  ==

 5564 12:40:42.735474  Dram Type= 6, Freq= 0, CH_1, rank 1

 5565 12:40:42.738820  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5566 12:40:42.738902  ==

 5567 12:40:42.745294  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5568 12:40:42.748690  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 5569 12:40:42.753037  [CA 0] Center 36 (6~67) winsize 62

 5570 12:40:42.756769  [CA 1] Center 37 (7~68) winsize 62

 5571 12:40:42.759971  [CA 2] Center 35 (5~65) winsize 61

 5572 12:40:42.763191  [CA 3] Center 34 (4~65) winsize 62

 5573 12:40:42.766372  [CA 4] Center 34 (4~65) winsize 62

 5574 12:40:42.769571  [CA 5] Center 33 (3~64) winsize 62

 5575 12:40:42.769649  

 5576 12:40:42.773235  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 5577 12:40:42.773313  

 5578 12:40:42.776482  [CATrainingPosCal] consider 2 rank data

 5579 12:40:42.779757  u2DelayCellTimex100 = 270/100 ps

 5580 12:40:42.782963  CA0 delay=36 (6~67),Diff = 3 PI (18 cell)

 5581 12:40:42.790176  CA1 delay=37 (7~67),Diff = 4 PI (24 cell)

 5582 12:40:42.793178  CA2 delay=35 (5~65),Diff = 2 PI (12 cell)

 5583 12:40:42.796343  CA3 delay=34 (4~65),Diff = 1 PI (6 cell)

 5584 12:40:42.799979  CA4 delay=34 (4~64),Diff = 1 PI (6 cell)

 5585 12:40:42.802970  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 5586 12:40:42.803076  

 5587 12:40:42.806519  CA PerBit enable=1, Macro0, CA PI delay=33

 5588 12:40:42.806636  

 5589 12:40:42.809542  [CBTSetCACLKResult] CA Dly = 33

 5590 12:40:42.809649  CS Dly: 7 (0~39)

 5591 12:40:42.813214  

 5592 12:40:42.816672  ----->DramcWriteLeveling(PI) begin...

 5593 12:40:42.816776  ==

 5594 12:40:42.819774  Dram Type= 6, Freq= 0, CH_1, rank 0

 5595 12:40:42.823145  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5596 12:40:42.823247  ==

 5597 12:40:42.826275  Write leveling (Byte 0): 24 => 24

 5598 12:40:42.829474  Write leveling (Byte 1): 26 => 26

 5599 12:40:42.833405  DramcWriteLeveling(PI) end<-----

 5600 12:40:42.833485  

 5601 12:40:42.833576  ==

 5602 12:40:42.836543  Dram Type= 6, Freq= 0, CH_1, rank 0

 5603 12:40:42.839664  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5604 12:40:42.839774  ==

 5605 12:40:42.843294  [Gating] SW mode calibration

 5606 12:40:42.849982  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5607 12:40:42.856560  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5608 12:40:42.860116   0 14  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5609 12:40:42.863274   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5610 12:40:42.869507   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5611 12:40:42.872832   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5612 12:40:42.875977   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5613 12:40:42.883138   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5614 12:40:42.886427   0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)

 5615 12:40:42.889668   0 14 28 | B1->B0 | 2727 2323 | 1 0 | (1 0) (1 0)

 5616 12:40:42.892971   0 15  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5617 12:40:42.899154   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5618 12:40:42.902447   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5619 12:40:42.909215   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5620 12:40:42.912283   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5621 12:40:42.916046   0 15 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)

 5622 12:40:42.919005   0 15 24 | B1->B0 | 2525 3535 | 0 0 | (0 0) (0 0)

 5623 12:40:42.925640   0 15 28 | B1->B0 | 3b3b 4444 | 0 0 | (0 0) (0 0)

 5624 12:40:42.928966   1  0  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5625 12:40:42.932994   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5626 12:40:42.939257   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5627 12:40:42.942466   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5628 12:40:42.945697   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5629 12:40:42.952648   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5630 12:40:42.955601   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5631 12:40:42.959253   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5632 12:40:42.965935   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5633 12:40:42.968727   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5634 12:40:42.972420   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5635 12:40:42.978756   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5636 12:40:42.982506   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5637 12:40:42.985747   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5638 12:40:42.992138   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5639 12:40:42.995406   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5640 12:40:42.999219   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5641 12:40:43.005406   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5642 12:40:43.008706   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5643 12:40:43.012382   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5644 12:40:43.018843   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5645 12:40:43.021994   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5646 12:40:43.025694   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 5647 12:40:43.028614  Total UI for P1: 0, mck2ui 16

 5648 12:40:43.032077  best dqsien dly found for B0: ( 1,  2, 22)

 5649 12:40:43.038438   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5650 12:40:43.038543  Total UI for P1: 0, mck2ui 16

 5651 12:40:43.041718  best dqsien dly found for B1: ( 1,  2, 24)

 5652 12:40:43.048728  best DQS0 dly(MCK, UI, PI) = (1, 2, 22)

 5653 12:40:43.051817  best DQS1 dly(MCK, UI, PI) = (1, 2, 24)

 5654 12:40:43.051900  

 5655 12:40:43.055454  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)

 5656 12:40:43.058777  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)

 5657 12:40:43.061851  [Gating] SW calibration Done

 5658 12:40:43.061998  ==

 5659 12:40:43.065004  Dram Type= 6, Freq= 0, CH_1, rank 0

 5660 12:40:43.068660  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5661 12:40:43.068768  ==

 5662 12:40:43.071732  RX Vref Scan: 0

 5663 12:40:43.071817  

 5664 12:40:43.071883  RX Vref 0 -> 0, step: 1

 5665 12:40:43.071952  

 5666 12:40:43.075612  RX Delay -80 -> 252, step: 8

 5667 12:40:43.078658  iDelay=208, Bit 0, Center 107 (16 ~ 199) 184

 5668 12:40:43.081688  iDelay=208, Bit 1, Center 95 (0 ~ 191) 192

 5669 12:40:43.088767  iDelay=208, Bit 2, Center 91 (0 ~ 183) 184

 5670 12:40:43.091998  iDelay=208, Bit 3, Center 99 (8 ~ 191) 184

 5671 12:40:43.095292  iDelay=208, Bit 4, Center 99 (8 ~ 191) 184

 5672 12:40:43.098405  iDelay=208, Bit 5, Center 115 (24 ~ 207) 184

 5673 12:40:43.101573  iDelay=208, Bit 6, Center 111 (16 ~ 207) 192

 5674 12:40:43.105185  iDelay=208, Bit 7, Center 103 (8 ~ 199) 192

 5675 12:40:43.111733  iDelay=208, Bit 8, Center 87 (0 ~ 175) 176

 5676 12:40:43.114808  iDelay=208, Bit 9, Center 87 (0 ~ 175) 176

 5677 12:40:43.118721  iDelay=208, Bit 10, Center 99 (8 ~ 191) 184

 5678 12:40:43.121887  iDelay=208, Bit 11, Center 91 (0 ~ 183) 184

 5679 12:40:43.125153  iDelay=208, Bit 12, Center 107 (16 ~ 199) 184

 5680 12:40:43.128741  iDelay=208, Bit 13, Center 107 (16 ~ 199) 184

 5681 12:40:43.135445  iDelay=208, Bit 14, Center 107 (16 ~ 199) 184

 5682 12:40:43.138567  iDelay=208, Bit 15, Center 107 (16 ~ 199) 184

 5683 12:40:43.138679  ==

 5684 12:40:43.141489  Dram Type= 6, Freq= 0, CH_1, rank 0

 5685 12:40:43.145421  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5686 12:40:43.145510  ==

 5687 12:40:43.148557  DQS Delay:

 5688 12:40:43.148660  DQS0 = 0, DQS1 = 0

 5689 12:40:43.148754  DQM Delay:

 5690 12:40:43.151727  DQM0 = 102, DQM1 = 99

 5691 12:40:43.151829  DQ Delay:

 5692 12:40:43.155050  DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99

 5693 12:40:43.158198  DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =103

 5694 12:40:43.161879  DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91

 5695 12:40:43.164875  DQ12 =107, DQ13 =107, DQ14 =107, DQ15 =107

 5696 12:40:43.168507  

 5697 12:40:43.168644  

 5698 12:40:43.168741  ==

 5699 12:40:43.171515  Dram Type= 6, Freq= 0, CH_1, rank 0

 5700 12:40:43.174716  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5701 12:40:43.174832  ==

 5702 12:40:43.174929  

 5703 12:40:43.175043  

 5704 12:40:43.178265  	TX Vref Scan disable

 5705 12:40:43.178397   == TX Byte 0 ==

 5706 12:40:43.184671  Update DQ  dly =707 (2 ,5, 35)  DQ  OEN =(2 ,2)

 5707 12:40:43.188417  Update DQM dly =707 (2 ,5, 35)  DQM OEN =(2 ,2)

 5708 12:40:43.188506   == TX Byte 1 ==

 5709 12:40:43.194947  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5710 12:40:43.198146  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5711 12:40:43.198238  ==

 5712 12:40:43.201402  Dram Type= 6, Freq= 0, CH_1, rank 0

 5713 12:40:43.204534  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5714 12:40:43.204620  ==

 5715 12:40:43.204687  

 5716 12:40:43.204749  

 5717 12:40:43.207867  	TX Vref Scan disable

 5718 12:40:43.211500   == TX Byte 0 ==

 5719 12:40:43.214795  Update DQ  dly =707 (2 ,5, 35)  DQ  OEN =(2 ,2)

 5720 12:40:43.217895  Update DQM dly =707 (2 ,5, 35)  DQM OEN =(2 ,2)

 5721 12:40:43.221301   == TX Byte 1 ==

 5722 12:40:43.224544  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5723 12:40:43.228383  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5724 12:40:43.228468  

 5725 12:40:43.231574  [DATLAT]

 5726 12:40:43.231652  Freq=933, CH1 RK0

 5727 12:40:43.231718  

 5728 12:40:43.234555  DATLAT Default: 0xd

 5729 12:40:43.234634  0, 0xFFFF, sum = 0

 5730 12:40:43.238417  1, 0xFFFF, sum = 0

 5731 12:40:43.238505  2, 0xFFFF, sum = 0

 5732 12:40:43.241064  3, 0xFFFF, sum = 0

 5733 12:40:43.241143  4, 0xFFFF, sum = 0

 5734 12:40:43.244727  5, 0xFFFF, sum = 0

 5735 12:40:43.244800  6, 0xFFFF, sum = 0

 5736 12:40:43.248317  7, 0xFFFF, sum = 0

 5737 12:40:43.248406  8, 0xFFFF, sum = 0

 5738 12:40:43.251202  9, 0xFFFF, sum = 0

 5739 12:40:43.251290  10, 0x0, sum = 1

 5740 12:40:43.254470  11, 0x0, sum = 2

 5741 12:40:43.254557  12, 0x0, sum = 3

 5742 12:40:43.257881  13, 0x0, sum = 4

 5743 12:40:43.257968  best_step = 11

 5744 12:40:43.258035  

 5745 12:40:43.258097  ==

 5746 12:40:43.261170  Dram Type= 6, Freq= 0, CH_1, rank 0

 5747 12:40:43.268024  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5748 12:40:43.268138  ==

 5749 12:40:43.268235  RX Vref Scan: 1

 5750 12:40:43.268331  

 5751 12:40:43.271264  RX Vref 0 -> 0, step: 1

 5752 12:40:43.271386  

 5753 12:40:43.274329  RX Delay -45 -> 252, step: 4

 5754 12:40:43.274441  

 5755 12:40:43.277998  Set Vref, RX VrefLevel [Byte0]: 53

 5756 12:40:43.280905                           [Byte1]: 53

 5757 12:40:43.281015  

 5758 12:40:43.284027  Final RX Vref Byte 0 = 53 to rank0

 5759 12:40:43.287355  Final RX Vref Byte 1 = 53 to rank0

 5760 12:40:43.291037  Final RX Vref Byte 0 = 53 to rank1

 5761 12:40:43.294754  Final RX Vref Byte 1 = 53 to rank1==

 5762 12:40:43.297847  Dram Type= 6, Freq= 0, CH_1, rank 0

 5763 12:40:43.301134  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5764 12:40:43.301241  ==

 5765 12:40:43.304345  DQS Delay:

 5766 12:40:43.304453  DQS0 = 0, DQS1 = 0

 5767 12:40:43.304557  DQM Delay:

 5768 12:40:43.307634  DQM0 = 103, DQM1 = 99

 5769 12:40:43.307734  DQ Delay:

 5770 12:40:43.310846  DQ0 =106, DQ1 =98, DQ2 =92, DQ3 =102

 5771 12:40:43.314737  DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =104

 5772 12:40:43.317836  DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =92

 5773 12:40:43.321026  DQ12 =106, DQ13 =104, DQ14 =106, DQ15 =106

 5774 12:40:43.324251  

 5775 12:40:43.324371  

 5776 12:40:43.330856  [DQSOSCAuto] RK0, (LSB)MR18= 0x182f, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps

 5777 12:40:43.334124  CH1 RK0: MR19=505, MR18=182F

 5778 12:40:43.341385  CH1_RK0: MR19=0x505, MR18=0x182F, DQSOSC=407, MR23=63, INC=65, DEC=43

 5779 12:40:43.341496  

 5780 12:40:43.344098  ----->DramcWriteLeveling(PI) begin...

 5781 12:40:43.344201  ==

 5782 12:40:43.347868  Dram Type= 6, Freq= 0, CH_1, rank 1

 5783 12:40:43.350899  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5784 12:40:43.351025  ==

 5785 12:40:43.353938  Write leveling (Byte 0): 25 => 25

 5786 12:40:43.357598  Write leveling (Byte 1): 27 => 27

 5787 12:40:43.360722  DramcWriteLeveling(PI) end<-----

 5788 12:40:43.360834  

 5789 12:40:43.360902  ==

 5790 12:40:43.363893  Dram Type= 6, Freq= 0, CH_1, rank 1

 5791 12:40:43.367478  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5792 12:40:43.367596  ==

 5793 12:40:43.370667  [Gating] SW mode calibration

 5794 12:40:43.377179  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5795 12:40:43.384109  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5796 12:40:43.387076   0 14  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5797 12:40:43.393446   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5798 12:40:43.396692   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5799 12:40:43.400458   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5800 12:40:43.407102   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5801 12:40:43.410398   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)

 5802 12:40:43.413700   0 14 24 | B1->B0 | 2727 3030 | 0 1 | (1 0) (1 0)

 5803 12:40:43.420047   0 14 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)

 5804 12:40:43.423304   0 15  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5805 12:40:43.426290   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5806 12:40:43.433512   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5807 12:40:43.436718   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5808 12:40:43.440149   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5809 12:40:43.443502   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5810 12:40:43.450079   0 15 24 | B1->B0 | 3636 2c2c | 0 0 | (1 1) (0 0)

 5811 12:40:43.453150   0 15 28 | B1->B0 | 4646 4545 | 0 1 | (0 0) (0 0)

 5812 12:40:43.456299   1  0  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5813 12:40:43.462884   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5814 12:40:43.466542   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5815 12:40:43.469728   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5816 12:40:43.476742   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5817 12:40:43.479864   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5818 12:40:43.482963   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5819 12:40:43.490215   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5820 12:40:43.493157   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5821 12:40:43.496238   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5822 12:40:43.502775   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5823 12:40:43.506465   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5824 12:40:43.509413   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5825 12:40:43.516777   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5826 12:40:43.520066   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5827 12:40:43.523200   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5828 12:40:43.529740   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5829 12:40:43.533501   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5830 12:40:43.536942   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5831 12:40:43.543132   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5832 12:40:43.546486   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5833 12:40:43.549640   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5834 12:40:43.552840   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5835 12:40:43.559901   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5836 12:40:43.562978  Total UI for P1: 0, mck2ui 16

 5837 12:40:43.566682  best dqsien dly found for B0: ( 1,  2, 26)

 5838 12:40:43.569739  Total UI for P1: 0, mck2ui 16

 5839 12:40:43.573293  best dqsien dly found for B1: ( 1,  2, 26)

 5840 12:40:43.576585  best DQS0 dly(MCK, UI, PI) = (1, 2, 26)

 5841 12:40:43.579757  best DQS1 dly(MCK, UI, PI) = (1, 2, 26)

 5842 12:40:43.579864  

 5843 12:40:43.582973  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5844 12:40:43.586359  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5845 12:40:43.589488  [Gating] SW calibration Done

 5846 12:40:43.589574  ==

 5847 12:40:43.593042  Dram Type= 6, Freq= 0, CH_1, rank 1

 5848 12:40:43.596374  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5849 12:40:43.596463  ==

 5850 12:40:43.599795  RX Vref Scan: 0

 5851 12:40:43.599957  

 5852 12:40:43.600083  RX Vref 0 -> 0, step: 1

 5853 12:40:43.602798  

 5854 12:40:43.602910  RX Delay -80 -> 252, step: 8

 5855 12:40:43.609363  iDelay=208, Bit 0, Center 111 (24 ~ 199) 176

 5856 12:40:43.613304  iDelay=208, Bit 1, Center 99 (8 ~ 191) 184

 5857 12:40:43.616235  iDelay=208, Bit 2, Center 91 (0 ~ 183) 184

 5858 12:40:43.619758  iDelay=208, Bit 3, Center 99 (8 ~ 191) 184

 5859 12:40:43.622713  iDelay=208, Bit 4, Center 95 (8 ~ 183) 176

 5860 12:40:43.626388  iDelay=208, Bit 5, Center 119 (32 ~ 207) 176

 5861 12:40:43.632680  iDelay=208, Bit 6, Center 115 (24 ~ 207) 184

 5862 12:40:43.636654  iDelay=208, Bit 7, Center 99 (8 ~ 191) 184

 5863 12:40:43.639923  iDelay=208, Bit 8, Center 87 (0 ~ 175) 176

 5864 12:40:43.643137  iDelay=208, Bit 9, Center 91 (0 ~ 183) 184

 5865 12:40:43.646276  iDelay=208, Bit 10, Center 99 (8 ~ 191) 184

 5866 12:40:43.649414  iDelay=208, Bit 11, Center 91 (0 ~ 183) 184

 5867 12:40:43.656460  iDelay=208, Bit 12, Center 107 (16 ~ 199) 184

 5868 12:40:43.660064  iDelay=208, Bit 13, Center 107 (16 ~ 199) 184

 5869 12:40:43.663019  iDelay=208, Bit 14, Center 103 (16 ~ 191) 176

 5870 12:40:43.666340  iDelay=208, Bit 15, Center 107 (16 ~ 199) 184

 5871 12:40:43.666425  ==

 5872 12:40:43.669376  Dram Type= 6, Freq= 0, CH_1, rank 1

 5873 12:40:43.673090  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5874 12:40:43.676101  ==

 5875 12:40:43.676204  DQS Delay:

 5876 12:40:43.676285  DQS0 = 0, DQS1 = 0

 5877 12:40:43.679812  DQM Delay:

 5878 12:40:43.679912  DQM0 = 103, DQM1 = 99

 5879 12:40:43.682959  DQ Delay:

 5880 12:40:43.686259  DQ0 =111, DQ1 =99, DQ2 =91, DQ3 =99

 5881 12:40:43.686359  DQ4 =95, DQ5 =119, DQ6 =115, DQ7 =99

 5882 12:40:43.689468  DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91

 5883 12:40:43.696437  DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107

 5884 12:40:43.696537  

 5885 12:40:43.696635  

 5886 12:40:43.696697  ==

 5887 12:40:43.699674  Dram Type= 6, Freq= 0, CH_1, rank 1

 5888 12:40:43.702629  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5889 12:40:43.702731  ==

 5890 12:40:43.702830  

 5891 12:40:43.702891  

 5892 12:40:43.706694  	TX Vref Scan disable

 5893 12:40:43.706809   == TX Byte 0 ==

 5894 12:40:43.712954  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5895 12:40:43.716273  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5896 12:40:43.716374   == TX Byte 1 ==

 5897 12:40:43.722866  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5898 12:40:43.726667  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5899 12:40:43.726768  ==

 5900 12:40:43.729699  Dram Type= 6, Freq= 0, CH_1, rank 1

 5901 12:40:43.733370  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5902 12:40:43.733474  ==

 5903 12:40:43.733590  

 5904 12:40:43.733712  

 5905 12:40:43.736590  	TX Vref Scan disable

 5906 12:40:43.739832   == TX Byte 0 ==

 5907 12:40:43.743118  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5908 12:40:43.746580  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5909 12:40:43.749699   == TX Byte 1 ==

 5910 12:40:43.752915  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5911 12:40:43.756264  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5912 12:40:43.756365  

 5913 12:40:43.759850  [DATLAT]

 5914 12:40:43.759954  Freq=933, CH1 RK1

 5915 12:40:43.760054  

 5916 12:40:43.763057  DATLAT Default: 0xb

 5917 12:40:43.763162  0, 0xFFFF, sum = 0

 5918 12:40:43.766415  1, 0xFFFF, sum = 0

 5919 12:40:43.766518  2, 0xFFFF, sum = 0

 5920 12:40:43.769657  3, 0xFFFF, sum = 0

 5921 12:40:43.769787  4, 0xFFFF, sum = 0

 5922 12:40:43.772838  5, 0xFFFF, sum = 0

 5923 12:40:43.772954  6, 0xFFFF, sum = 0

 5924 12:40:43.775965  7, 0xFFFF, sum = 0

 5925 12:40:43.776052  8, 0xFFFF, sum = 0

 5926 12:40:43.779837  9, 0xFFFF, sum = 0

 5927 12:40:43.779940  10, 0x0, sum = 1

 5928 12:40:43.782594  11, 0x0, sum = 2

 5929 12:40:43.782695  12, 0x0, sum = 3

 5930 12:40:43.786277  13, 0x0, sum = 4

 5931 12:40:43.786378  best_step = 11

 5932 12:40:43.786477  

 5933 12:40:43.786572  ==

 5934 12:40:43.789366  Dram Type= 6, Freq= 0, CH_1, rank 1

 5935 12:40:43.795864  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5936 12:40:43.795951  ==

 5937 12:40:43.796019  RX Vref Scan: 0

 5938 12:40:43.796084  

 5939 12:40:43.799744  RX Vref 0 -> 0, step: 1

 5940 12:40:43.799829  

 5941 12:40:43.802791  RX Delay -45 -> 252, step: 4

 5942 12:40:43.806153  iDelay=203, Bit 0, Center 108 (27 ~ 190) 164

 5943 12:40:43.810047  iDelay=203, Bit 1, Center 102 (19 ~ 186) 168

 5944 12:40:43.815916  iDelay=203, Bit 2, Center 94 (11 ~ 178) 168

 5945 12:40:43.819523  iDelay=203, Bit 3, Center 100 (19 ~ 182) 164

 5946 12:40:43.822660  iDelay=203, Bit 4, Center 100 (19 ~ 182) 164

 5947 12:40:43.826420  iDelay=203, Bit 5, Center 118 (35 ~ 202) 168

 5948 12:40:43.829525  iDelay=203, Bit 6, Center 112 (27 ~ 198) 172

 5949 12:40:43.836311  iDelay=203, Bit 7, Center 104 (19 ~ 190) 172

 5950 12:40:43.839787  iDelay=203, Bit 8, Center 92 (11 ~ 174) 164

 5951 12:40:43.842982  iDelay=203, Bit 9, Center 92 (7 ~ 178) 172

 5952 12:40:43.846166  iDelay=203, Bit 10, Center 98 (11 ~ 186) 176

 5953 12:40:43.849636  iDelay=203, Bit 11, Center 94 (11 ~ 178) 168

 5954 12:40:43.852652  iDelay=203, Bit 12, Center 108 (19 ~ 198) 180

 5955 12:40:43.859170  iDelay=203, Bit 13, Center 108 (27 ~ 190) 164

 5956 12:40:43.862346  iDelay=203, Bit 14, Center 108 (27 ~ 190) 164

 5957 12:40:43.866129  iDelay=203, Bit 15, Center 108 (23 ~ 194) 172

 5958 12:40:43.866211  ==

 5959 12:40:43.869406  Dram Type= 6, Freq= 0, CH_1, rank 1

 5960 12:40:43.872863  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5961 12:40:43.875995  ==

 5962 12:40:43.876096  DQS Delay:

 5963 12:40:43.876192  DQS0 = 0, DQS1 = 0

 5964 12:40:43.879167  DQM Delay:

 5965 12:40:43.879275  DQM0 = 104, DQM1 = 101

 5966 12:40:43.882887  DQ Delay:

 5967 12:40:43.885912  DQ0 =108, DQ1 =102, DQ2 =94, DQ3 =100

 5968 12:40:43.888939  DQ4 =100, DQ5 =118, DQ6 =112, DQ7 =104

 5969 12:40:43.892699  DQ8 =92, DQ9 =92, DQ10 =98, DQ11 =94

 5970 12:40:43.895863  DQ12 =108, DQ13 =108, DQ14 =108, DQ15 =108

 5971 12:40:43.895963  

 5972 12:40:43.896061  

 5973 12:40:43.902782  [DQSOSCAuto] RK1, (LSB)MR18= 0x2cff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 408 ps

 5974 12:40:43.905911  CH1 RK1: MR19=504, MR18=2CFF

 5975 12:40:43.912501  CH1_RK1: MR19=0x504, MR18=0x2CFF, DQSOSC=408, MR23=63, INC=65, DEC=43

 5976 12:40:43.915650  [RxdqsGatingPostProcess] freq 933

 5977 12:40:43.919289  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 5978 12:40:43.922811  best DQS0 dly(2T, 0.5T) = (0, 10)

 5979 12:40:43.925920  best DQS1 dly(2T, 0.5T) = (0, 10)

 5980 12:40:43.929514  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5981 12:40:43.932409  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5982 12:40:43.935676  best DQS0 dly(2T, 0.5T) = (0, 10)

 5983 12:40:43.938930  best DQS1 dly(2T, 0.5T) = (0, 10)

 5984 12:40:43.942544  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5985 12:40:43.946045  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5986 12:40:43.949113  Pre-setting of DQS Precalculation

 5987 12:40:43.952635  [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11

 5988 12:40:43.962367  sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3

 5989 12:40:43.969381  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 5990 12:40:43.969487  

 5991 12:40:43.969589  

 5992 12:40:43.972639  [Calibration Summary] 1866 Mbps

 5993 12:40:43.972740  CH 0, Rank 0

 5994 12:40:43.975691  SW Impedance     : PASS

 5995 12:40:43.975801  DUTY Scan        : NO K

 5996 12:40:43.979566  ZQ Calibration   : PASS

 5997 12:40:43.982866  Jitter Meter     : NO K

 5998 12:40:43.982972  CBT Training     : PASS

 5999 12:40:43.985938  Write leveling   : PASS

 6000 12:40:43.988860  RX DQS gating    : PASS

 6001 12:40:43.988970  RX DQ/DQS(RDDQC) : PASS

 6002 12:40:43.992558  TX DQ/DQS        : PASS

 6003 12:40:43.995589  RX DATLAT        : PASS

 6004 12:40:43.995711  RX DQ/DQS(Engine): PASS

 6005 12:40:43.999190  TX OE            : NO K

 6006 12:40:43.999299  All Pass.

 6007 12:40:43.999391  

 6008 12:40:44.002628  CH 0, Rank 1

 6009 12:40:44.002731  SW Impedance     : PASS

 6010 12:40:44.005753  DUTY Scan        : NO K

 6011 12:40:44.008826  ZQ Calibration   : PASS

 6012 12:40:44.008954  Jitter Meter     : NO K

 6013 12:40:44.012751  CBT Training     : PASS

 6014 12:40:44.012892  Write leveling   : PASS

 6015 12:40:44.015913  RX DQS gating    : PASS

 6016 12:40:44.019192  RX DQ/DQS(RDDQC) : PASS

 6017 12:40:44.019310  TX DQ/DQS        : PASS

 6018 12:40:44.022432  RX DATLAT        : PASS

 6019 12:40:44.025484  RX DQ/DQS(Engine): PASS

 6020 12:40:44.025612  TX OE            : NO K

 6021 12:40:44.029159  All Pass.

 6022 12:40:44.029262  

 6023 12:40:44.029360  CH 1, Rank 0

 6024 12:40:44.032269  SW Impedance     : PASS

 6025 12:40:44.032357  DUTY Scan        : NO K

 6026 12:40:44.035745  ZQ Calibration   : PASS

 6027 12:40:44.039190  Jitter Meter     : NO K

 6028 12:40:44.039278  CBT Training     : PASS

 6029 12:40:44.042308  Write leveling   : PASS

 6030 12:40:44.045628  RX DQS gating    : PASS

 6031 12:40:44.045716  RX DQ/DQS(RDDQC) : PASS

 6032 12:40:44.048730  TX DQ/DQS        : PASS

 6033 12:40:44.052511  RX DATLAT        : PASS

 6034 12:40:44.052597  RX DQ/DQS(Engine): PASS

 6035 12:40:44.055379  TX OE            : NO K

 6036 12:40:44.055496  All Pass.

 6037 12:40:44.055581  

 6038 12:40:44.059144  CH 1, Rank 1

 6039 12:40:44.059245  SW Impedance     : PASS

 6040 12:40:44.061900  DUTY Scan        : NO K

 6041 12:40:44.065814  ZQ Calibration   : PASS

 6042 12:40:44.065902  Jitter Meter     : NO K

 6043 12:40:44.069028  CBT Training     : PASS

 6044 12:40:44.069137  Write leveling   : PASS

 6045 12:40:44.072356  RX DQS gating    : PASS

 6046 12:40:44.075534  RX DQ/DQS(RDDQC) : PASS

 6047 12:40:44.075620  TX DQ/DQS        : PASS

 6048 12:40:44.078875  RX DATLAT        : PASS

 6049 12:40:44.082078  RX DQ/DQS(Engine): PASS

 6050 12:40:44.082164  TX OE            : NO K

 6051 12:40:44.085412  All Pass.

 6052 12:40:44.085516  

 6053 12:40:44.085617  DramC Write-DBI off

 6054 12:40:44.088486  	PER_BANK_REFRESH: Hybrid Mode

 6055 12:40:44.091706  TX_TRACKING: ON

 6056 12:40:44.098405  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0

 6057 12:40:44.102200  [FAST_K] Save calibration result to emmc

 6058 12:40:44.105247  dramc_set_vcore_voltage set vcore to 650000

 6059 12:40:44.108537  Read voltage for 400, 6

 6060 12:40:44.108633  Vio18 = 0

 6061 12:40:44.111705  Vcore = 650000

 6062 12:40:44.111796  Vdram = 0

 6063 12:40:44.111885  Vddq = 0

 6064 12:40:44.115550  Vmddr = 0

 6065 12:40:44.118767  [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0

 6066 12:40:44.125309  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 6067 12:40:44.125415  MEM_TYPE=3, freq_sel=20

 6068 12:40:44.128466  sv_algorithm_assistance_LP4_800 

 6069 12:40:44.132328  ============ PULL DRAM RESETB DOWN ============

 6070 12:40:44.138693  ========== PULL DRAM RESETB DOWN end =========

 6071 12:40:44.141933  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6072 12:40:44.145306  =================================== 

 6073 12:40:44.148914  LPDDR4 DRAM CONFIGURATION

 6074 12:40:44.152028  =================================== 

 6075 12:40:44.152120  EX_ROW_EN[0]    = 0x0

 6076 12:40:44.155315  EX_ROW_EN[1]    = 0x0

 6077 12:40:44.158387  LP4Y_EN      = 0x0

 6078 12:40:44.158471  WORK_FSP     = 0x0

 6079 12:40:44.161659  WL           = 0x2

 6080 12:40:44.161736  RL           = 0x2

 6081 12:40:44.165204  BL           = 0x2

 6082 12:40:44.165293  RPST         = 0x0

 6083 12:40:44.168601  RD_PRE       = 0x0

 6084 12:40:44.168690  WR_PRE       = 0x1

 6085 12:40:44.171791  WR_PST       = 0x0

 6086 12:40:44.171883  DBI_WR       = 0x0

 6087 12:40:44.175703  DBI_RD       = 0x0

 6088 12:40:44.175806  OTF          = 0x1

 6089 12:40:44.178631  =================================== 

 6090 12:40:44.181851  =================================== 

 6091 12:40:44.185185  ANA top config

 6092 12:40:44.188617  =================================== 

 6093 12:40:44.188696  DLL_ASYNC_EN            =  0

 6094 12:40:44.191801  ALL_SLAVE_EN            =  1

 6095 12:40:44.194935  NEW_RANK_MODE           =  1

 6096 12:40:44.198202  DLL_IDLE_MODE           =  1

 6097 12:40:44.201484  LP45_APHY_COMB_EN       =  1

 6098 12:40:44.201595  TX_ODT_DIS              =  1

 6099 12:40:44.205209  NEW_8X_MODE             =  1

 6100 12:40:44.208343  =================================== 

 6101 12:40:44.211918  =================================== 

 6102 12:40:44.215087  data_rate                  =  800

 6103 12:40:44.218165  CKR                        = 1

 6104 12:40:44.221492  DQ_P2S_RATIO               = 4

 6105 12:40:44.224726  =================================== 

 6106 12:40:44.224839  CA_P2S_RATIO               = 4

 6107 12:40:44.228036  DQ_CA_OPEN                 = 0

 6108 12:40:44.231414  DQ_SEMI_OPEN               = 1

 6109 12:40:44.235105  CA_SEMI_OPEN               = 1

 6110 12:40:44.238378  CA_FULL_RATE               = 0

 6111 12:40:44.241617  DQ_CKDIV4_EN               = 0

 6112 12:40:44.241725  CA_CKDIV4_EN               = 1

 6113 12:40:44.244873  CA_PREDIV_EN               = 0

 6114 12:40:44.248067  PH8_DLY                    = 0

 6115 12:40:44.251432  SEMI_OPEN_CA_PICK_MCK_RATIO= 4

 6116 12:40:44.254677  DQ_AAMCK_DIV               = 0

 6117 12:40:44.258134  CA_AAMCK_DIV               = 0

 6118 12:40:44.258218  CA_ADMCK_DIV               = 4

 6119 12:40:44.261683  DQ_TRACK_CA_EN             = 0

 6120 12:40:44.265005  CA_PICK                    = 800

 6121 12:40:44.267997  CA_MCKIO                   = 400

 6122 12:40:44.271580  MCKIO_SEMI                 = 400

 6123 12:40:44.274903  PLL_FREQ                   = 3016

 6124 12:40:44.277974  DQ_UI_PI_RATIO             = 32

 6125 12:40:44.278103  CA_UI_PI_RATIO             = 32

 6126 12:40:44.281231  =================================== 

 6127 12:40:44.284906  =================================== 

 6128 12:40:44.288119  memory_type:LPDDR4         

 6129 12:40:44.291558  GP_NUM     : 10       

 6130 12:40:44.291666  SRAM_EN    : 1       

 6131 12:40:44.294633  MD32_EN    : 0       

 6132 12:40:44.297891  =================================== 

 6133 12:40:44.301148  [ANA_INIT] >>>>>>>>>>>>>> 

 6134 12:40:44.304382  <<<<<< [CONFIGURE PHASE]: ANA_TX

 6135 12:40:44.308246  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 6136 12:40:44.311479  =================================== 

 6137 12:40:44.311594  data_rate = 800,PCW = 0X7400

 6138 12:40:44.314804  =================================== 

 6139 12:40:44.317970  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 6140 12:40:44.324401  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 6141 12:40:44.338062  WARN: tr->DQ_AAMCK_DIV=  0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 6142 12:40:44.341068  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 6143 12:40:44.344376  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 6144 12:40:44.347532  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 6145 12:40:44.351213  [ANA_INIT] flow start 

 6146 12:40:44.351324  [ANA_INIT] PLL >>>>>>>> 

 6147 12:40:44.354452  [ANA_INIT] PLL <<<<<<<< 

 6148 12:40:44.357660  [ANA_INIT] MIDPI >>>>>>>> 

 6149 12:40:44.357783  [ANA_INIT] MIDPI <<<<<<<< 

 6150 12:40:44.361419  [ANA_INIT] DLL >>>>>>>> 

 6151 12:40:44.364348  [ANA_INIT] flow end 

 6152 12:40:44.367894  ============ LP4 DIFF to SE enter ============

 6153 12:40:44.371319  ============ LP4 DIFF to SE exit  ============

 6154 12:40:44.374413  [ANA_INIT] <<<<<<<<<<<<< 

 6155 12:40:44.377974  [Flow] Enable top DCM control >>>>> 

 6156 12:40:44.380936  [Flow] Enable top DCM control <<<<< 

 6157 12:40:44.384397  Enable DLL master slave shuffle 

 6158 12:40:44.387920  ============================================================== 

 6159 12:40:44.391106  Gating Mode config

 6160 12:40:44.397966  ============================================================== 

 6161 12:40:44.398083  Config description: 

 6162 12:40:44.407595  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 6163 12:40:44.414673  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 6164 12:40:44.417663  SELPH_MODE            0: By rank         1: By Phase 

 6165 12:40:44.424334  ============================================================== 

 6166 12:40:44.427845  GAT_TRACK_EN                 =  0

 6167 12:40:44.430862  RX_GATING_MODE               =  2

 6168 12:40:44.433991  RX_GATING_TRACK_MODE         =  2

 6169 12:40:44.437952  SELPH_MODE                   =  1

 6170 12:40:44.441156  PICG_EARLY_EN                =  1

 6171 12:40:44.444285  VALID_LAT_VALUE              =  1

 6172 12:40:44.447513  ============================================================== 

 6173 12:40:44.450765  Enter into Gating configuration >>>> 

 6174 12:40:44.454047  Exit from Gating configuration <<<< 

 6175 12:40:44.457716  Enter into  DVFS_PRE_config >>>>> 

 6176 12:40:44.470468  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 6177 12:40:44.470586  Exit from  DVFS_PRE_config <<<<< 

 6178 12:40:44.474170  Enter into PICG configuration >>>> 

 6179 12:40:44.477606  Exit from PICG configuration <<<< 

 6180 12:40:44.481034  [RX_INPUT] configuration >>>>> 

 6181 12:40:44.484223  [RX_INPUT] configuration <<<<< 

 6182 12:40:44.490787  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 6183 12:40:44.494047  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 6184 12:40:44.500822  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 6185 12:40:44.507136  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 6186 12:40:44.514273  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 6187 12:40:44.520783  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 6188 12:40:44.524040  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 6189 12:40:44.527657  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 6190 12:40:44.530647  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 6191 12:40:44.536986  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 6192 12:40:44.540724  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 6193 12:40:44.544169  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6194 12:40:44.547230  =================================== 

 6195 12:40:44.550472  LPDDR4 DRAM CONFIGURATION

 6196 12:40:44.553749  =================================== 

 6197 12:40:44.553834  EX_ROW_EN[0]    = 0x0

 6198 12:40:44.557702  EX_ROW_EN[1]    = 0x0

 6199 12:40:44.557790  LP4Y_EN      = 0x0

 6200 12:40:44.560741  WORK_FSP     = 0x0

 6201 12:40:44.564033  WL           = 0x2

 6202 12:40:44.564117  RL           = 0x2

 6203 12:40:44.567251  BL           = 0x2

 6204 12:40:44.567335  RPST         = 0x0

 6205 12:40:44.570427  RD_PRE       = 0x0

 6206 12:40:44.570504  WR_PRE       = 0x1

 6207 12:40:44.573684  WR_PST       = 0x0

 6208 12:40:44.573760  DBI_WR       = 0x0

 6209 12:40:44.576969  DBI_RD       = 0x0

 6210 12:40:44.577042  OTF          = 0x1

 6211 12:40:44.580731  =================================== 

 6212 12:40:44.584289  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 6213 12:40:44.590216  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 6214 12:40:44.593761  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6215 12:40:44.596978  =================================== 

 6216 12:40:44.600664  LPDDR4 DRAM CONFIGURATION

 6217 12:40:44.604166  =================================== 

 6218 12:40:44.604245  EX_ROW_EN[0]    = 0x10

 6219 12:40:44.607396  EX_ROW_EN[1]    = 0x0

 6220 12:40:44.607481  LP4Y_EN      = 0x0

 6221 12:40:44.610551  WORK_FSP     = 0x0

 6222 12:40:44.610630  WL           = 0x2

 6223 12:40:44.613714  RL           = 0x2

 6224 12:40:44.617136  BL           = 0x2

 6225 12:40:44.617213  RPST         = 0x0

 6226 12:40:44.620152  RD_PRE       = 0x0

 6227 12:40:44.620222  WR_PRE       = 0x1

 6228 12:40:44.623420  WR_PST       = 0x0

 6229 12:40:44.623516  DBI_WR       = 0x0

 6230 12:40:44.626676  DBI_RD       = 0x0

 6231 12:40:44.626757  OTF          = 0x1

 6232 12:40:44.630378  =================================== 

 6233 12:40:44.636710  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 6234 12:40:44.641069  nWR fixed to 30

 6235 12:40:44.644056  [ModeRegInit_LP4] CH0 RK0

 6236 12:40:44.644138  [ModeRegInit_LP4] CH0 RK1

 6237 12:40:44.647663  [ModeRegInit_LP4] CH1 RK0

 6238 12:40:44.650775  [ModeRegInit_LP4] CH1 RK1

 6239 12:40:44.650855  match AC timing 19

 6240 12:40:44.657541  dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1

 6241 12:40:44.660867  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 6242 12:40:44.664117  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

 6243 12:40:44.671034  [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17

 6244 12:40:44.674144  [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)

 6245 12:40:44.674226  ==

 6246 12:40:44.677412  Dram Type= 6, Freq= 0, CH_0, rank 0

 6247 12:40:44.680759  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6248 12:40:44.680863  ==

 6249 12:40:44.687713  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6250 12:40:44.694487  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 6251 12:40:44.697563  [CA 0] Center 36 (8~64) winsize 57

 6252 12:40:44.700823  [CA 1] Center 36 (8~64) winsize 57

 6253 12:40:44.700909  [CA 2] Center 36 (8~64) winsize 57

 6254 12:40:44.703908  [CA 3] Center 36 (8~64) winsize 57

 6255 12:40:44.707730  [CA 4] Center 36 (8~64) winsize 57

 6256 12:40:44.710810  [CA 5] Center 36 (8~64) winsize 57

 6257 12:40:44.710891  

 6258 12:40:44.714376  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 6259 12:40:44.714459  

 6260 12:40:44.720688  [CATrainingPosCal] consider 1 rank data

 6261 12:40:44.720797  u2DelayCellTimex100 = 270/100 ps

 6262 12:40:44.727201  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6263 12:40:44.730984  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6264 12:40:44.734081  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6265 12:40:44.737497  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6266 12:40:44.740690  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6267 12:40:44.744399  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6268 12:40:44.744502  

 6269 12:40:44.747338  CA PerBit enable=1, Macro0, CA PI delay=36

 6270 12:40:44.747441  

 6271 12:40:44.751121  [CBTSetCACLKResult] CA Dly = 36

 6272 12:40:44.751198  CS Dly: 1 (0~32)

 6273 12:40:44.754374  ==

 6274 12:40:44.757793  Dram Type= 6, Freq= 0, CH_0, rank 1

 6275 12:40:44.760895  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6276 12:40:44.760979  ==

 6277 12:40:44.764215  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6278 12:40:44.771090  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6279 12:40:44.774346  [CA 0] Center 36 (8~64) winsize 57

 6280 12:40:44.777499  [CA 1] Center 36 (8~64) winsize 57

 6281 12:40:44.780666  [CA 2] Center 36 (8~64) winsize 57

 6282 12:40:44.784000  [CA 3] Center 36 (8~64) winsize 57

 6283 12:40:44.787737  [CA 4] Center 36 (8~64) winsize 57

 6284 12:40:44.790875  [CA 5] Center 36 (8~64) winsize 57

 6285 12:40:44.790959  

 6286 12:40:44.793949  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6287 12:40:44.794035  

 6288 12:40:44.797143  [CATrainingPosCal] consider 2 rank data

 6289 12:40:44.800959  u2DelayCellTimex100 = 270/100 ps

 6290 12:40:44.804042  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6291 12:40:44.807203  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6292 12:40:44.811018  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6293 12:40:44.814007  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6294 12:40:44.820769  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6295 12:40:44.824016  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6296 12:40:44.824111  

 6297 12:40:44.827193  CA PerBit enable=1, Macro0, CA PI delay=36

 6298 12:40:44.827279  

 6299 12:40:44.830481  [CBTSetCACLKResult] CA Dly = 36

 6300 12:40:44.830564  CS Dly: 1 (0~32)

 6301 12:40:44.830648  

 6302 12:40:44.833737  ----->DramcWriteLeveling(PI) begin...

 6303 12:40:44.833816  ==

 6304 12:40:44.836932  Dram Type= 6, Freq= 0, CH_0, rank 0

 6305 12:40:44.844053  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6306 12:40:44.844147  ==

 6307 12:40:44.847331  Write leveling (Byte 0): 40 => 8

 6308 12:40:44.847411  Write leveling (Byte 1): 40 => 8

 6309 12:40:44.850302  DramcWriteLeveling(PI) end<-----

 6310 12:40:44.850376  

 6311 12:40:44.850460  ==

 6312 12:40:44.853939  Dram Type= 6, Freq= 0, CH_0, rank 0

 6313 12:40:44.860854  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6314 12:40:44.860934  ==

 6315 12:40:44.863741  [Gating] SW mode calibration

 6316 12:40:44.870650  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6317 12:40:44.873762  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6318 12:40:44.880350   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6319 12:40:44.884153   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6320 12:40:44.887518   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6321 12:40:44.890771   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6322 12:40:44.897329   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6323 12:40:44.900350   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6324 12:40:44.904159   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6325 12:40:44.910425   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6326 12:40:44.913934   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6327 12:40:44.917086  Total UI for P1: 0, mck2ui 16

 6328 12:40:44.920106  best dqsien dly found for B0: ( 0, 14, 24)

 6329 12:40:44.923547  Total UI for P1: 0, mck2ui 16

 6330 12:40:44.927111  best dqsien dly found for B1: ( 0, 14, 24)

 6331 12:40:44.930342  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6332 12:40:44.933651  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6333 12:40:44.933746  

 6334 12:40:44.936858  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6335 12:40:44.943161  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6336 12:40:44.943247  [Gating] SW calibration Done

 6337 12:40:44.946427  ==

 6338 12:40:44.946512  Dram Type= 6, Freq= 0, CH_0, rank 0

 6339 12:40:44.953027  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6340 12:40:44.953113  ==

 6341 12:40:44.953182  RX Vref Scan: 0

 6342 12:40:44.953245  

 6343 12:40:44.956909  RX Vref 0 -> 0, step: 1

 6344 12:40:44.956993  

 6345 12:40:44.959935  RX Delay -410 -> 252, step: 16

 6346 12:40:44.963594  iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464

 6347 12:40:44.966688  iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480

 6348 12:40:44.972871  iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480

 6349 12:40:44.976531  iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464

 6350 12:40:44.979752  iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464

 6351 12:40:44.983010  iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480

 6352 12:40:44.989766  iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480

 6353 12:40:44.993080  iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464

 6354 12:40:44.996561  iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464

 6355 12:40:44.999643  iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464

 6356 12:40:45.006706  iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464

 6357 12:40:45.009224  iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480

 6358 12:40:45.012928  iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464

 6359 12:40:45.019343  iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464

 6360 12:40:45.022950  iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448

 6361 12:40:45.026163  iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464

 6362 12:40:45.026243  ==

 6363 12:40:45.029140  Dram Type= 6, Freq= 0, CH_0, rank 0

 6364 12:40:45.032975  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6365 12:40:45.033068  ==

 6366 12:40:45.035964  DQS Delay:

 6367 12:40:45.036039  DQS0 = 27, DQS1 = 35

 6368 12:40:45.039314  DQM Delay:

 6369 12:40:45.039394  DQM0 = 10, DQM1 = 12

 6370 12:40:45.042541  DQ Delay:

 6371 12:40:45.042622  DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8

 6372 12:40:45.045739  DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24

 6373 12:40:45.049524  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8

 6374 12:40:45.052810  DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16

 6375 12:40:45.052913  

 6376 12:40:45.052980  

 6377 12:40:45.053039  ==

 6378 12:40:45.056091  Dram Type= 6, Freq= 0, CH_0, rank 0

 6379 12:40:45.062528  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6380 12:40:45.062609  ==

 6381 12:40:45.062674  

 6382 12:40:45.062766  

 6383 12:40:45.062825  	TX Vref Scan disable

 6384 12:40:45.065832   == TX Byte 0 ==

 6385 12:40:45.069265  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6386 12:40:45.072981  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6387 12:40:45.075980   == TX Byte 1 ==

 6388 12:40:45.079660  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6389 12:40:45.082547  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6390 12:40:45.082629  ==

 6391 12:40:45.086333  Dram Type= 6, Freq= 0, CH_0, rank 0

 6392 12:40:45.092855  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6393 12:40:45.092947  ==

 6394 12:40:45.093023  

 6395 12:40:45.093083  

 6396 12:40:45.093141  	TX Vref Scan disable

 6397 12:40:45.095832   == TX Byte 0 ==

 6398 12:40:45.099086  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6399 12:40:45.102443  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6400 12:40:45.106149   == TX Byte 1 ==

 6401 12:40:45.109256  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6402 12:40:45.112439  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6403 12:40:45.112515  

 6404 12:40:45.115624  [DATLAT]

 6405 12:40:45.115723  Freq=400, CH0 RK0

 6406 12:40:45.115787  

 6407 12:40:45.119466  DATLAT Default: 0xf

 6408 12:40:45.119548  0, 0xFFFF, sum = 0

 6409 12:40:45.122677  1, 0xFFFF, sum = 0

 6410 12:40:45.122760  2, 0xFFFF, sum = 0

 6411 12:40:45.125724  3, 0xFFFF, sum = 0

 6412 12:40:45.125812  4, 0xFFFF, sum = 0

 6413 12:40:45.129420  5, 0xFFFF, sum = 0

 6414 12:40:45.129511  6, 0xFFFF, sum = 0

 6415 12:40:45.132651  7, 0xFFFF, sum = 0

 6416 12:40:45.132763  8, 0xFFFF, sum = 0

 6417 12:40:45.135620  9, 0xFFFF, sum = 0

 6418 12:40:45.135695  10, 0xFFFF, sum = 0

 6419 12:40:45.139422  11, 0xFFFF, sum = 0

 6420 12:40:45.142419  12, 0xFFFF, sum = 0

 6421 12:40:45.142502  13, 0x0, sum = 1

 6422 12:40:45.145495  14, 0x0, sum = 2

 6423 12:40:45.145581  15, 0x0, sum = 3

 6424 12:40:45.145649  16, 0x0, sum = 4

 6425 12:40:45.149299  best_step = 14

 6426 12:40:45.149375  

 6427 12:40:45.149436  ==

 6428 12:40:45.152519  Dram Type= 6, Freq= 0, CH_0, rank 0

 6429 12:40:45.155748  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6430 12:40:45.155841  ==

 6431 12:40:45.159093  RX Vref Scan: 1

 6432 12:40:45.159163  

 6433 12:40:45.159223  RX Vref 0 -> 0, step: 1

 6434 12:40:45.162428  

 6435 12:40:45.162505  RX Delay -311 -> 252, step: 8

 6436 12:40:45.162568  

 6437 12:40:45.165749  Set Vref, RX VrefLevel [Byte0]: 53

 6438 12:40:45.169032                           [Byte1]: 47

 6439 12:40:45.174052  

 6440 12:40:45.176938  Final RX Vref Byte 0 = 53 to rank0

 6441 12:40:45.177011  Final RX Vref Byte 1 = 47 to rank0

 6442 12:40:45.180484  Final RX Vref Byte 0 = 53 to rank1

 6443 12:40:45.183740  Final RX Vref Byte 1 = 47 to rank1==

 6444 12:40:45.187257  Dram Type= 6, Freq= 0, CH_0, rank 0

 6445 12:40:45.193621  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6446 12:40:45.193712  ==

 6447 12:40:45.193777  DQS Delay:

 6448 12:40:45.197435  DQS0 = 28, DQS1 = 36

 6449 12:40:45.197515  DQM Delay:

 6450 12:40:45.197579  DQM0 = 12, DQM1 = 13

 6451 12:40:45.200710  DQ Delay:

 6452 12:40:45.203878  DQ0 =12, DQ1 =16, DQ2 =12, DQ3 =8

 6453 12:40:45.207392  DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16

 6454 12:40:45.207473  DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8

 6455 12:40:45.213720  DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20

 6456 12:40:45.213801  

 6457 12:40:45.213865  

 6458 12:40:45.220454  [DQSOSCAuto] RK0, (LSB)MR18= 0xcbb7, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 384 ps

 6459 12:40:45.223829  CH0 RK0: MR19=C0C, MR18=CBB7

 6460 12:40:45.230410  CH0_RK0: MR19=0xC0C, MR18=0xCBB7, DQSOSC=384, MR23=63, INC=400, DEC=267

 6461 12:40:45.230530  ==

 6462 12:40:45.233489  Dram Type= 6, Freq= 0, CH_0, rank 1

 6463 12:40:45.236776  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6464 12:40:45.236902  ==

 6465 12:40:45.240532  [Gating] SW mode calibration

 6466 12:40:45.247396  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6467 12:40:45.253444  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6468 12:40:45.257291   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6469 12:40:45.260533   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6470 12:40:45.267113   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6471 12:40:45.270575   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6472 12:40:45.273798   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6473 12:40:45.279981   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6474 12:40:45.283538   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6475 12:40:45.286499   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6476 12:40:45.293301   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6477 12:40:45.293392  Total UI for P1: 0, mck2ui 16

 6478 12:40:45.296893  best dqsien dly found for B0: ( 0, 14, 24)

 6479 12:40:45.300597  Total UI for P1: 0, mck2ui 16

 6480 12:40:45.303372  best dqsien dly found for B1: ( 0, 14, 24)

 6481 12:40:45.306898  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6482 12:40:45.313677  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6483 12:40:45.313824  

 6484 12:40:45.316866  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6485 12:40:45.320058  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6486 12:40:45.323187  [Gating] SW calibration Done

 6487 12:40:45.323333  ==

 6488 12:40:45.326500  Dram Type= 6, Freq= 0, CH_0, rank 1

 6489 12:40:45.329691  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6490 12:40:45.329812  ==

 6491 12:40:45.333623  RX Vref Scan: 0

 6492 12:40:45.333741  

 6493 12:40:45.333841  RX Vref 0 -> 0, step: 1

 6494 12:40:45.333935  

 6495 12:40:45.336709  RX Delay -410 -> 252, step: 16

 6496 12:40:45.339736  iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464

 6497 12:40:45.346841  iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464

 6498 12:40:45.350214  iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464

 6499 12:40:45.353260  iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464

 6500 12:40:45.356778  iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480

 6501 12:40:45.363434  iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480

 6502 12:40:45.366624  iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464

 6503 12:40:45.369831  iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464

 6504 12:40:45.373065  iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464

 6505 12:40:45.379491  iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464

 6506 12:40:45.383361  iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464

 6507 12:40:45.386504  iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448

 6508 12:40:45.389706  iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464

 6509 12:40:45.396603  iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464

 6510 12:40:45.399544  iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448

 6511 12:40:45.403135  iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464

 6512 12:40:45.403282  ==

 6513 12:40:45.406137  Dram Type= 6, Freq= 0, CH_0, rank 1

 6514 12:40:45.413186  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6515 12:40:45.413327  ==

 6516 12:40:45.413436  DQS Delay:

 6517 12:40:45.416156  DQS0 = 27, DQS1 = 35

 6518 12:40:45.416274  DQM Delay:

 6519 12:40:45.416369  DQM0 = 12, DQM1 = 12

 6520 12:40:45.419886  DQ Delay:

 6521 12:40:45.422902  DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8

 6522 12:40:45.423040  DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24

 6523 12:40:45.426009  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8

 6524 12:40:45.429999  DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16

 6525 12:40:45.430134  

 6526 12:40:45.430236  

 6527 12:40:45.433350  ==

 6528 12:40:45.436457  Dram Type= 6, Freq= 0, CH_0, rank 1

 6529 12:40:45.439732  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6530 12:40:45.439872  ==

 6531 12:40:45.439945  

 6532 12:40:45.440041  

 6533 12:40:45.442929  	TX Vref Scan disable

 6534 12:40:45.443054   == TX Byte 0 ==

 6535 12:40:45.446456  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6536 12:40:45.452824  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6537 12:40:45.452978   == TX Byte 1 ==

 6538 12:40:45.456205  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6539 12:40:45.462899  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6540 12:40:45.463038  ==

 6541 12:40:45.466019  Dram Type= 6, Freq= 0, CH_0, rank 1

 6542 12:40:45.469519  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6543 12:40:45.469618  ==

 6544 12:40:45.469688  

 6545 12:40:45.469749  

 6546 12:40:45.472496  	TX Vref Scan disable

 6547 12:40:45.472613   == TX Byte 0 ==

 6548 12:40:45.476243  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6549 12:40:45.482874  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6550 12:40:45.483024   == TX Byte 1 ==

 6551 12:40:45.486007  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6552 12:40:45.492813  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6553 12:40:45.492907  

 6554 12:40:45.492982  [DATLAT]

 6555 12:40:45.493080  Freq=400, CH0 RK1

 6556 12:40:45.493169  

 6557 12:40:45.496069  DATLAT Default: 0xe

 6558 12:40:45.496171  0, 0xFFFF, sum = 0

 6559 12:40:45.499274  1, 0xFFFF, sum = 0

 6560 12:40:45.502363  2, 0xFFFF, sum = 0

 6561 12:40:45.502484  3, 0xFFFF, sum = 0

 6562 12:40:45.505912  4, 0xFFFF, sum = 0

 6563 12:40:45.506003  5, 0xFFFF, sum = 0

 6564 12:40:45.509841  6, 0xFFFF, sum = 0

 6565 12:40:45.509930  7, 0xFFFF, sum = 0

 6566 12:40:45.512653  8, 0xFFFF, sum = 0

 6567 12:40:45.512758  9, 0xFFFF, sum = 0

 6568 12:40:45.516091  10, 0xFFFF, sum = 0

 6569 12:40:45.516206  11, 0xFFFF, sum = 0

 6570 12:40:45.519241  12, 0xFFFF, sum = 0

 6571 12:40:45.519345  13, 0x0, sum = 1

 6572 12:40:45.522749  14, 0x0, sum = 2

 6573 12:40:45.522862  15, 0x0, sum = 3

 6574 12:40:45.525654  16, 0x0, sum = 4

 6575 12:40:45.525777  best_step = 14

 6576 12:40:45.525876  

 6577 12:40:45.525969  ==

 6578 12:40:45.529273  Dram Type= 6, Freq= 0, CH_0, rank 1

 6579 12:40:45.532950  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6580 12:40:45.536085  ==

 6581 12:40:45.536169  RX Vref Scan: 0

 6582 12:40:45.536250  

 6583 12:40:45.539454  RX Vref 0 -> 0, step: 1

 6584 12:40:45.539561  

 6585 12:40:45.542579  RX Delay -311 -> 252, step: 8

 6586 12:40:45.545757  iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448

 6587 12:40:45.552510  iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448

 6588 12:40:45.555529  iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448

 6589 12:40:45.558834  iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448

 6590 12:40:45.562110  iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448

 6591 12:40:45.569059  iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448

 6592 12:40:45.572354  iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440

 6593 12:40:45.575352  iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448

 6594 12:40:45.579092  iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440

 6595 12:40:45.585434  iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440

 6596 12:40:45.588753  iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440

 6597 12:40:45.592031  iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440

 6598 12:40:45.595806  iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440

 6599 12:40:45.602453  iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440

 6600 12:40:45.605604  iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440

 6601 12:40:45.609414  iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448

 6602 12:40:45.609519  ==

 6603 12:40:45.612320  Dram Type= 6, Freq= 0, CH_0, rank 1

 6604 12:40:45.618706  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6605 12:40:45.618823  ==

 6606 12:40:45.618926  DQS Delay:

 6607 12:40:45.622434  DQS0 = 24, DQS1 = 36

 6608 12:40:45.622544  DQM Delay:

 6609 12:40:45.622638  DQM0 = 8, DQM1 = 13

 6610 12:40:45.625415  DQ Delay:

 6611 12:40:45.629179  DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8

 6612 12:40:45.629266  DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16

 6613 12:40:45.632085  DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8

 6614 12:40:45.635062  DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20

 6615 12:40:45.635163  

 6616 12:40:45.638675  

 6617 12:40:45.645107  [DQSOSCAuto] RK1, (LSB)MR18= 0xba58, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps

 6618 12:40:45.648444  CH0 RK1: MR19=C0C, MR18=BA58

 6619 12:40:45.654983  CH0_RK1: MR19=0xC0C, MR18=0xBA58, DQSOSC=386, MR23=63, INC=396, DEC=264

 6620 12:40:45.658740  [RxdqsGatingPostProcess] freq 400

 6621 12:40:45.661749  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 6622 12:40:45.664979  best DQS0 dly(2T, 0.5T) = (0, 10)

 6623 12:40:45.668574  best DQS1 dly(2T, 0.5T) = (0, 10)

 6624 12:40:45.671815  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6625 12:40:45.675007  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6626 12:40:45.678300  best DQS0 dly(2T, 0.5T) = (0, 10)

 6627 12:40:45.681657  best DQS1 dly(2T, 0.5T) = (0, 10)

 6628 12:40:45.685202  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6629 12:40:45.688745  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6630 12:40:45.692006  Pre-setting of DQS Precalculation

 6631 12:40:45.695363  [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14

 6632 12:40:45.695492  ==

 6633 12:40:45.698410  Dram Type= 6, Freq= 0, CH_1, rank 0

 6634 12:40:45.701634  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6635 12:40:45.704923  ==

 6636 12:40:45.708185  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6637 12:40:45.715103  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 6638 12:40:45.718335  [CA 0] Center 36 (8~64) winsize 57

 6639 12:40:45.721466  [CA 1] Center 36 (8~64) winsize 57

 6640 12:40:45.724753  [CA 2] Center 36 (8~64) winsize 57

 6641 12:40:45.728251  [CA 3] Center 36 (8~64) winsize 57

 6642 12:40:45.731321  [CA 4] Center 36 (8~64) winsize 57

 6643 12:40:45.734822  [CA 5] Center 36 (8~64) winsize 57

 6644 12:40:45.734935  

 6645 12:40:45.738350  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 6646 12:40:45.738448  

 6647 12:40:45.741412  [CATrainingPosCal] consider 1 rank data

 6648 12:40:45.745087  u2DelayCellTimex100 = 270/100 ps

 6649 12:40:45.748301  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6650 12:40:45.751727  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6651 12:40:45.754865  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6652 12:40:45.758028  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6653 12:40:45.761209  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6654 12:40:45.765034  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6655 12:40:45.765120  

 6656 12:40:45.768113  CA PerBit enable=1, Macro0, CA PI delay=36

 6657 12:40:45.771821  

 6658 12:40:45.771922  [CBTSetCACLKResult] CA Dly = 36

 6659 12:40:45.774784  CS Dly: 1 (0~32)

 6660 12:40:45.774862  ==

 6661 12:40:45.778482  Dram Type= 6, Freq= 0, CH_1, rank 1

 6662 12:40:45.781807  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6663 12:40:45.781885  ==

 6664 12:40:45.788171  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6665 12:40:45.795003  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 6666 12:40:45.797947  [CA 0] Center 36 (8~64) winsize 57

 6667 12:40:45.801753  [CA 1] Center 36 (8~64) winsize 57

 6668 12:40:45.801850  [CA 2] Center 36 (8~64) winsize 57

 6669 12:40:45.804880  [CA 3] Center 36 (8~64) winsize 57

 6670 12:40:45.808128  [CA 4] Center 36 (8~64) winsize 57

 6671 12:40:45.811337  [CA 5] Center 36 (8~64) winsize 57

 6672 12:40:45.811450  

 6673 12:40:45.814682  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 6674 12:40:45.814798  

 6675 12:40:45.821394  [CATrainingPosCal] consider 2 rank data

 6676 12:40:45.821500  u2DelayCellTimex100 = 270/100 ps

 6677 12:40:45.824742  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6678 12:40:45.831674  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6679 12:40:45.834693  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6680 12:40:45.838368  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6681 12:40:45.841490  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6682 12:40:45.845106  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6683 12:40:45.845182  

 6684 12:40:45.848068  CA PerBit enable=1, Macro0, CA PI delay=36

 6685 12:40:45.848143  

 6686 12:40:45.851709  [CBTSetCACLKResult] CA Dly = 36

 6687 12:40:45.854939  CS Dly: 1 (0~32)

 6688 12:40:45.855047  

 6689 12:40:45.858203  ----->DramcWriteLeveling(PI) begin...

 6690 12:40:45.858302  ==

 6691 12:40:45.861444  Dram Type= 6, Freq= 0, CH_1, rank 0

 6692 12:40:45.864776  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6693 12:40:45.864884  ==

 6694 12:40:45.867962  Write leveling (Byte 0): 40 => 8

 6695 12:40:45.871791  Write leveling (Byte 1): 40 => 8

 6696 12:40:45.875131  DramcWriteLeveling(PI) end<-----

 6697 12:40:45.875238  

 6698 12:40:45.875363  ==

 6699 12:40:45.878176  Dram Type= 6, Freq= 0, CH_1, rank 0

 6700 12:40:45.881436  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6701 12:40:45.881530  ==

 6702 12:40:45.884689  [Gating] SW mode calibration

 6703 12:40:45.891657  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6704 12:40:45.897910  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6705 12:40:45.901633   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6706 12:40:45.904686   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6707 12:40:45.911069   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6708 12:40:45.914475   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6709 12:40:45.917975   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6710 12:40:45.921610   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6711 12:40:45.928013   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6712 12:40:45.931139   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6713 12:40:45.934948   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6714 12:40:45.938156  Total UI for P1: 0, mck2ui 16

 6715 12:40:45.941175  best dqsien dly found for B0: ( 0, 14, 24)

 6716 12:40:45.944661  Total UI for P1: 0, mck2ui 16

 6717 12:40:45.947705  best dqsien dly found for B1: ( 0, 14, 24)

 6718 12:40:45.951346  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6719 12:40:45.955033  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6720 12:40:45.957983  

 6721 12:40:45.961209  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6722 12:40:45.964452  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6723 12:40:45.967830  [Gating] SW calibration Done

 6724 12:40:45.967913  ==

 6725 12:40:45.971079  Dram Type= 6, Freq= 0, CH_1, rank 0

 6726 12:40:45.974967  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6727 12:40:45.975113  ==

 6728 12:40:45.975219  RX Vref Scan: 0

 6729 12:40:45.975320  

 6730 12:40:45.978229  RX Vref 0 -> 0, step: 1

 6731 12:40:45.978316  

 6732 12:40:45.981433  RX Delay -410 -> 252, step: 16

 6733 12:40:45.984742  iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480

 6734 12:40:45.991421  iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464

 6735 12:40:45.994466  iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464

 6736 12:40:45.997853  iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464

 6737 12:40:46.000965  iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464

 6738 12:40:46.007930  iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464

 6739 12:40:46.011033  iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480

 6740 12:40:46.014738  iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464

 6741 12:40:46.017981  iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464

 6742 12:40:46.024405  iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464

 6743 12:40:46.027597  iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464

 6744 12:40:46.031288  iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480

 6745 12:40:46.034663  iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480

 6746 12:40:46.041148  iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464

 6747 12:40:46.044411  iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464

 6748 12:40:46.047704  iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480

 6749 12:40:46.047821  ==

 6750 12:40:46.051403  Dram Type= 6, Freq= 0, CH_1, rank 0

 6751 12:40:46.054478  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6752 12:40:46.058015  ==

 6753 12:40:46.058139  DQS Delay:

 6754 12:40:46.058240  DQS0 = 35, DQS1 = 35

 6755 12:40:46.061052  DQM Delay:

 6756 12:40:46.061139  DQM0 = 18, DQM1 = 13

 6757 12:40:46.064238  DQ Delay:

 6758 12:40:46.064345  DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16

 6759 12:40:46.068124  DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16

 6760 12:40:46.071352  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8

 6761 12:40:46.074515  DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24

 6762 12:40:46.074651  

 6763 12:40:46.074758  

 6764 12:40:46.077829  ==

 6765 12:40:46.080920  Dram Type= 6, Freq= 0, CH_1, rank 0

 6766 12:40:46.084114  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6767 12:40:46.084204  ==

 6768 12:40:46.084274  

 6769 12:40:46.084336  

 6770 12:40:46.087430  	TX Vref Scan disable

 6771 12:40:46.087504   == TX Byte 0 ==

 6772 12:40:46.091350  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6773 12:40:46.097728  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6774 12:40:46.097807   == TX Byte 1 ==

 6775 12:40:46.100751  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6776 12:40:46.107768  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6777 12:40:46.107865  ==

 6778 12:40:46.111037  Dram Type= 6, Freq= 0, CH_1, rank 0

 6779 12:40:46.114094  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6780 12:40:46.114174  ==

 6781 12:40:46.114239  

 6782 12:40:46.114298  

 6783 12:40:46.117749  	TX Vref Scan disable

 6784 12:40:46.117825   == TX Byte 0 ==

 6785 12:40:46.120702  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6786 12:40:46.127251  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6787 12:40:46.127334   == TX Byte 1 ==

 6788 12:40:46.130441  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6789 12:40:46.137436  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6790 12:40:46.137524  

 6791 12:40:46.137595  [DATLAT]

 6792 12:40:46.137657  Freq=400, CH1 RK0

 6793 12:40:46.137718  

 6794 12:40:46.140984  DATLAT Default: 0xf

 6795 12:40:46.143861  0, 0xFFFF, sum = 0

 6796 12:40:46.143936  1, 0xFFFF, sum = 0

 6797 12:40:46.147190  2, 0xFFFF, sum = 0

 6798 12:40:46.147266  3, 0xFFFF, sum = 0

 6799 12:40:46.150955  4, 0xFFFF, sum = 0

 6800 12:40:46.151028  5, 0xFFFF, sum = 0

 6801 12:40:46.153965  6, 0xFFFF, sum = 0

 6802 12:40:46.154042  7, 0xFFFF, sum = 0

 6803 12:40:46.157788  8, 0xFFFF, sum = 0

 6804 12:40:46.157870  9, 0xFFFF, sum = 0

 6805 12:40:46.161107  10, 0xFFFF, sum = 0

 6806 12:40:46.161184  11, 0xFFFF, sum = 0

 6807 12:40:46.164198  12, 0xFFFF, sum = 0

 6808 12:40:46.164273  13, 0x0, sum = 1

 6809 12:40:46.167672  14, 0x0, sum = 2

 6810 12:40:46.167747  15, 0x0, sum = 3

 6811 12:40:46.170564  16, 0x0, sum = 4

 6812 12:40:46.170639  best_step = 14

 6813 12:40:46.170701  

 6814 12:40:46.170758  ==

 6815 12:40:46.174376  Dram Type= 6, Freq= 0, CH_1, rank 0

 6816 12:40:46.177711  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6817 12:40:46.180986  ==

 6818 12:40:46.181101  RX Vref Scan: 1

 6819 12:40:46.181165  

 6820 12:40:46.184159  RX Vref 0 -> 0, step: 1

 6821 12:40:46.184260  

 6822 12:40:46.187511  RX Delay -311 -> 252, step: 8

 6823 12:40:46.187641  

 6824 12:40:46.190782  Set Vref, RX VrefLevel [Byte0]: 53

 6825 12:40:46.194213                           [Byte1]: 53

 6826 12:40:46.194374  

 6827 12:40:46.197151  Final RX Vref Byte 0 = 53 to rank0

 6828 12:40:46.200429  Final RX Vref Byte 1 = 53 to rank0

 6829 12:40:46.203674  Final RX Vref Byte 0 = 53 to rank1

 6830 12:40:46.207332  Final RX Vref Byte 1 = 53 to rank1==

 6831 12:40:46.210406  Dram Type= 6, Freq= 0, CH_1, rank 0

 6832 12:40:46.213786  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6833 12:40:46.213887  ==

 6834 12:40:46.217099  DQS Delay:

 6835 12:40:46.217171  DQS0 = 32, DQS1 = 32

 6836 12:40:46.220269  DQM Delay:

 6837 12:40:46.220338  DQM0 = 13, DQM1 = 10

 6838 12:40:46.220396  DQ Delay:

 6839 12:40:46.224046  DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12

 6840 12:40:46.227339  DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =12

 6841 12:40:46.230905  DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0

 6842 12:40:46.234002  DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24

 6843 12:40:46.234092  

 6844 12:40:46.234178  

 6845 12:40:46.243866  [DQSOSCAuto] RK0, (LSB)MR18= 0x90c8, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 391 ps

 6846 12:40:46.243962  CH1 RK0: MR19=C0C, MR18=90C8

 6847 12:40:46.250448  CH1_RK0: MR19=0xC0C, MR18=0x90C8, DQSOSC=385, MR23=63, INC=398, DEC=265

 6848 12:40:46.250540  ==

 6849 12:40:46.253669  Dram Type= 6, Freq= 0, CH_1, rank 1

 6850 12:40:46.260641  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6851 12:40:46.260750  ==

 6852 12:40:46.263806  [Gating] SW mode calibration

 6853 12:40:46.270703  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6854 12:40:46.273822  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6855 12:40:46.280181   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6856 12:40:46.283377   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6857 12:40:46.287238   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6858 12:40:46.293783   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6859 12:40:46.296938   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6860 12:40:46.300282   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6861 12:40:46.306671   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6862 12:40:46.309973   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6863 12:40:46.313445   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6864 12:40:46.317032  Total UI for P1: 0, mck2ui 16

 6865 12:40:46.320135  best dqsien dly found for B0: ( 0, 14, 24)

 6866 12:40:46.323327  Total UI for P1: 0, mck2ui 16

 6867 12:40:46.327155  best dqsien dly found for B1: ( 0, 14, 24)

 6868 12:40:46.330418  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6869 12:40:46.334088  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6870 12:40:46.334176  

 6871 12:40:46.336812  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6872 12:40:46.343643  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6873 12:40:46.343724  [Gating] SW calibration Done

 6874 12:40:46.343791  ==

 6875 12:40:46.346848  Dram Type= 6, Freq= 0, CH_1, rank 1

 6876 12:40:46.353760  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6877 12:40:46.353869  ==

 6878 12:40:46.353962  RX Vref Scan: 0

 6879 12:40:46.354054  

 6880 12:40:46.356964  RX Vref 0 -> 0, step: 1

 6881 12:40:46.357042  

 6882 12:40:46.360227  RX Delay -410 -> 252, step: 16

 6883 12:40:46.363933  iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464

 6884 12:40:46.367117  iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464

 6885 12:40:46.373356  iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464

 6886 12:40:46.377187  iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464

 6887 12:40:46.380439  iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464

 6888 12:40:46.383270  iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464

 6889 12:40:46.386974  iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464

 6890 12:40:46.393226  iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464

 6891 12:40:46.396540  iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464

 6892 12:40:46.399800  iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480

 6893 12:40:46.403153  iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464

 6894 12:40:46.410053  iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480

 6895 12:40:46.413361  iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480

 6896 12:40:46.416589  iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464

 6897 12:40:46.423336  iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464

 6898 12:40:46.426405  iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480

 6899 12:40:46.426492  ==

 6900 12:40:46.429681  Dram Type= 6, Freq= 0, CH_1, rank 1

 6901 12:40:46.433347  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6902 12:40:46.433436  ==

 6903 12:40:46.436446  DQS Delay:

 6904 12:40:46.436531  DQS0 = 35, DQS1 = 35

 6905 12:40:46.436598  DQM Delay:

 6906 12:40:46.439659  DQM0 = 18, DQM1 = 14

 6907 12:40:46.439742  DQ Delay:

 6908 12:40:46.443483  DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16

 6909 12:40:46.446563  DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16

 6910 12:40:46.449572  DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8

 6911 12:40:46.453048  DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24

 6912 12:40:46.453135  

 6913 12:40:46.453202  

 6914 12:40:46.453265  ==

 6915 12:40:46.456749  Dram Type= 6, Freq= 0, CH_1, rank 1

 6916 12:40:46.463390  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6917 12:40:46.463478  ==

 6918 12:40:46.463545  

 6919 12:40:46.463607  

 6920 12:40:46.463667  	TX Vref Scan disable

 6921 12:40:46.466694   == TX Byte 0 ==

 6922 12:40:46.469705  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6923 12:40:46.472938  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6924 12:40:46.476150   == TX Byte 1 ==

 6925 12:40:46.479923  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6926 12:40:46.483139  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6927 12:40:46.483253  ==

 6928 12:40:46.486117  Dram Type= 6, Freq= 0, CH_1, rank 1

 6929 12:40:46.493111  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6930 12:40:46.493227  ==

 6931 12:40:46.493326  

 6932 12:40:46.493418  

 6933 12:40:46.493510  	TX Vref Scan disable

 6934 12:40:46.496238   == TX Byte 0 ==

 6935 12:40:46.499403  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6936 12:40:46.502772  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6937 12:40:46.505977   == TX Byte 1 ==

 6938 12:40:46.509735  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6939 12:40:46.512909  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6940 12:40:46.513020  

 6941 12:40:46.516017  [DATLAT]

 6942 12:40:46.516123  Freq=400, CH1 RK1

 6943 12:40:46.516220  

 6944 12:40:46.519390  DATLAT Default: 0xe

 6945 12:40:46.519494  0, 0xFFFF, sum = 0

 6946 12:40:46.522549  1, 0xFFFF, sum = 0

 6947 12:40:46.522661  2, 0xFFFF, sum = 0

 6948 12:40:46.526224  3, 0xFFFF, sum = 0

 6949 12:40:46.526335  4, 0xFFFF, sum = 0

 6950 12:40:46.529155  5, 0xFFFF, sum = 0

 6951 12:40:46.529266  6, 0xFFFF, sum = 0

 6952 12:40:46.533123  7, 0xFFFF, sum = 0

 6953 12:40:46.533209  8, 0xFFFF, sum = 0

 6954 12:40:46.536162  9, 0xFFFF, sum = 0

 6955 12:40:46.536270  10, 0xFFFF, sum = 0

 6956 12:40:46.539261  11, 0xFFFF, sum = 0

 6957 12:40:46.543111  12, 0xFFFF, sum = 0

 6958 12:40:46.543231  13, 0x0, sum = 1

 6959 12:40:46.543329  14, 0x0, sum = 2

 6960 12:40:46.546243  15, 0x0, sum = 3

 6961 12:40:46.546352  16, 0x0, sum = 4

 6962 12:40:46.549484  best_step = 14

 6963 12:40:46.549582  

 6964 12:40:46.549649  ==

 6965 12:40:46.552765  Dram Type= 6, Freq= 0, CH_1, rank 1

 6966 12:40:46.556056  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6967 12:40:46.556170  ==

 6968 12:40:46.559371  RX Vref Scan: 0

 6969 12:40:46.559477  

 6970 12:40:46.559574  RX Vref 0 -> 0, step: 1

 6971 12:40:46.559664  

 6972 12:40:46.562929  RX Delay -311 -> 252, step: 8

 6973 12:40:46.570601  iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440

 6974 12:40:46.573726  iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448

 6975 12:40:46.577260  iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440

 6976 12:40:46.580434  iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440

 6977 12:40:46.587579  iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440

 6978 12:40:46.590470  iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440

 6979 12:40:46.593933  iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448

 6980 12:40:46.597062  iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448

 6981 12:40:46.603671  iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448

 6982 12:40:46.606827  iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448

 6983 12:40:46.610740  iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456

 6984 12:40:46.613775  iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456

 6985 12:40:46.620144  iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456

 6986 12:40:46.623424  iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448

 6987 12:40:46.626738  iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448

 6988 12:40:46.633700  iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456

 6989 12:40:46.633807  ==

 6990 12:40:46.637002  Dram Type= 6, Freq= 0, CH_1, rank 1

 6991 12:40:46.640601  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6992 12:40:46.640732  ==

 6993 12:40:46.640858  DQS Delay:

 6994 12:40:46.643727  DQS0 = 28, DQS1 = 32

 6995 12:40:46.643845  DQM Delay:

 6996 12:40:46.646886  DQM0 = 11, DQM1 = 11

 6997 12:40:46.646976  DQ Delay:

 6998 12:40:46.650659  DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8

 6999 12:40:46.653850  DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =12

 7000 12:40:46.657226  DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4

 7001 12:40:46.660376  DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20

 7002 12:40:46.660507  

 7003 12:40:46.660602  

 7004 12:40:46.667121  [DQSOSCAuto] RK1, (LSB)MR18= 0xc95a, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 384 ps

 7005 12:40:46.670039  CH1 RK1: MR19=C0C, MR18=C95A

 7006 12:40:46.676845  CH1_RK1: MR19=0xC0C, MR18=0xC95A, DQSOSC=384, MR23=63, INC=400, DEC=267

 7007 12:40:46.679940  [RxdqsGatingPostProcess] freq 400

 7008 12:40:46.686918  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 7009 12:40:46.687014  best DQS0 dly(2T, 0.5T) = (0, 10)

 7010 12:40:46.690062  best DQS1 dly(2T, 0.5T) = (0, 10)

 7011 12:40:46.693379  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 7012 12:40:46.696996  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 7013 12:40:46.700355  best DQS0 dly(2T, 0.5T) = (0, 10)

 7014 12:40:46.703600  best DQS1 dly(2T, 0.5T) = (0, 10)

 7015 12:40:46.706585  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 7016 12:40:46.710243  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 7017 12:40:46.713566  Pre-setting of DQS Precalculation

 7018 12:40:46.716653  [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14

 7019 12:40:46.726997  sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6

 7020 12:40:46.733624  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 7021 12:40:46.733732  

 7022 12:40:46.733809  

 7023 12:40:46.736666  [Calibration Summary] 800 Mbps

 7024 12:40:46.736748  CH 0, Rank 0

 7025 12:40:46.739824  SW Impedance     : PASS

 7026 12:40:46.739899  DUTY Scan        : NO K

 7027 12:40:46.743391  ZQ Calibration   : PASS

 7028 12:40:46.746719  Jitter Meter     : NO K

 7029 12:40:46.746815  CBT Training     : PASS

 7030 12:40:46.750434  Write leveling   : PASS

 7031 12:40:46.753367  RX DQS gating    : PASS

 7032 12:40:46.753453  RX DQ/DQS(RDDQC) : PASS

 7033 12:40:46.756518  TX DQ/DQS        : PASS

 7034 12:40:46.759844  RX DATLAT        : PASS

 7035 12:40:46.759935  RX DQ/DQS(Engine): PASS

 7036 12:40:46.763069  TX OE            : NO K

 7037 12:40:46.763174  All Pass.

 7038 12:40:46.763266  

 7039 12:40:46.766854  CH 0, Rank 1

 7040 12:40:46.766932  SW Impedance     : PASS

 7041 12:40:46.770034  DUTY Scan        : NO K

 7042 12:40:46.773134  ZQ Calibration   : PASS

 7043 12:40:46.773217  Jitter Meter     : NO K

 7044 12:40:46.776746  CBT Training     : PASS

 7045 12:40:46.776834  Write leveling   : NO K

 7046 12:40:46.779690  RX DQS gating    : PASS

 7047 12:40:46.783402  RX DQ/DQS(RDDQC) : PASS

 7048 12:40:46.783482  TX DQ/DQS        : PASS

 7049 12:40:46.786603  RX DATLAT        : PASS

 7050 12:40:46.789728  RX DQ/DQS(Engine): PASS

 7051 12:40:46.789809  TX OE            : NO K

 7052 12:40:46.793030  All Pass.

 7053 12:40:46.793106  

 7054 12:40:46.793170  CH 1, Rank 0

 7055 12:40:46.796325  SW Impedance     : PASS

 7056 12:40:46.796401  DUTY Scan        : NO K

 7057 12:40:46.800112  ZQ Calibration   : PASS

 7058 12:40:46.803060  Jitter Meter     : NO K

 7059 12:40:46.803137  CBT Training     : PASS

 7060 12:40:46.806664  Write leveling   : PASS

 7061 12:40:46.809542  RX DQS gating    : PASS

 7062 12:40:46.809632  RX DQ/DQS(RDDQC) : PASS

 7063 12:40:46.813283  TX DQ/DQS        : PASS

 7064 12:40:46.816293  RX DATLAT        : PASS

 7065 12:40:46.816400  RX DQ/DQS(Engine): PASS

 7066 12:40:46.820141  TX OE            : NO K

 7067 12:40:46.820223  All Pass.

 7068 12:40:46.820289  

 7069 12:40:46.823214  CH 1, Rank 1

 7070 12:40:46.823296  SW Impedance     : PASS

 7071 12:40:46.826500  DUTY Scan        : NO K

 7072 12:40:46.829799  ZQ Calibration   : PASS

 7073 12:40:46.829922  Jitter Meter     : NO K

 7074 12:40:46.833090  CBT Training     : PASS

 7075 12:40:46.833205  Write leveling   : NO K

 7076 12:40:46.836290  RX DQS gating    : PASS

 7077 12:40:46.840107  RX DQ/DQS(RDDQC) : PASS

 7078 12:40:46.840215  TX DQ/DQS        : PASS

 7079 12:40:46.843288  RX DATLAT        : PASS

 7080 12:40:46.846471  RX DQ/DQS(Engine): PASS

 7081 12:40:46.846619  TX OE            : NO K

 7082 12:40:46.849667  All Pass.

 7083 12:40:46.849773  

 7084 12:40:46.849884  DramC Write-DBI off

 7085 12:40:46.852747  	PER_BANK_REFRESH: Hybrid Mode

 7086 12:40:46.852859  TX_TRACKING: ON

 7087 12:40:46.862968  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0

 7088 12:40:46.866177  [FAST_K] Save calibration result to emmc

 7089 12:40:46.869469  dramc_set_vcore_voltage set vcore to 725000

 7090 12:40:46.872783  Read voltage for 1600, 0

 7091 12:40:46.872902  Vio18 = 0

 7092 12:40:46.876588  Vcore = 725000

 7093 12:40:46.876693  Vdram = 0

 7094 12:40:46.876811  Vddq = 0

 7095 12:40:46.879718  Vmddr = 0

 7096 12:40:46.882792  [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0

 7097 12:40:46.889582  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 7098 12:40:46.889702  MEM_TYPE=3, freq_sel=13

 7099 12:40:46.893296  sv_algorithm_assistance_LP4_3733 

 7100 12:40:46.899801  ============ PULL DRAM RESETB DOWN ============

 7101 12:40:46.902980  ========== PULL DRAM RESETB DOWN end =========

 7102 12:40:46.906663  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7103 12:40:46.909739  =================================== 

 7104 12:40:46.912679  LPDDR4 DRAM CONFIGURATION

 7105 12:40:46.916488  =================================== 

 7106 12:40:46.916608  EX_ROW_EN[0]    = 0x0

 7107 12:40:46.919429  EX_ROW_EN[1]    = 0x0

 7108 12:40:46.923138  LP4Y_EN      = 0x0

 7109 12:40:46.923235  WORK_FSP     = 0x1

 7110 12:40:46.926131  WL           = 0x5

 7111 12:40:46.926225  RL           = 0x5

 7112 12:40:46.929238  BL           = 0x2

 7113 12:40:46.929361  RPST         = 0x0

 7114 12:40:46.932461  RD_PRE       = 0x0

 7115 12:40:46.932569  WR_PRE       = 0x1

 7116 12:40:46.935761  WR_PST       = 0x1

 7117 12:40:46.935878  DBI_WR       = 0x0

 7118 12:40:46.939747  DBI_RD       = 0x0

 7119 12:40:46.939852  OTF          = 0x1

 7120 12:40:46.942855  =================================== 

 7121 12:40:46.945905  =================================== 

 7122 12:40:46.949144  ANA top config

 7123 12:40:46.952370  =================================== 

 7124 12:40:46.952447  DLL_ASYNC_EN            =  0

 7125 12:40:46.956196  ALL_SLAVE_EN            =  0

 7126 12:40:46.959443  NEW_RANK_MODE           =  1

 7127 12:40:46.962484  DLL_IDLE_MODE           =  1

 7128 12:40:46.965946  LP45_APHY_COMB_EN       =  1

 7129 12:40:46.966028  TX_ODT_DIS              =  0

 7130 12:40:46.969488  NEW_8X_MODE             =  1

 7131 12:40:46.972790  =================================== 

 7132 12:40:46.975919  =================================== 

 7133 12:40:46.979291  data_rate                  = 3200

 7134 12:40:46.982556  CKR                        = 1

 7135 12:40:46.986106  DQ_P2S_RATIO               = 8

 7136 12:40:46.989348  =================================== 

 7137 12:40:46.989437  CA_P2S_RATIO               = 8

 7138 12:40:46.992625  DQ_CA_OPEN                 = 0

 7139 12:40:46.996193  DQ_SEMI_OPEN               = 0

 7140 12:40:46.999201  CA_SEMI_OPEN               = 0

 7141 12:40:47.002903  CA_FULL_RATE               = 0

 7142 12:40:47.006062  DQ_CKDIV4_EN               = 0

 7143 12:40:47.006157  CA_CKDIV4_EN               = 0

 7144 12:40:47.009194  CA_PREDIV_EN               = 0

 7145 12:40:47.012926  PH8_DLY                    = 12

 7146 12:40:47.015906  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 7147 12:40:47.019695  DQ_AAMCK_DIV               = 4

 7148 12:40:47.022884  CA_AAMCK_DIV               = 4

 7149 12:40:47.022973  CA_ADMCK_DIV               = 4

 7150 12:40:47.025908  DQ_TRACK_CA_EN             = 0

 7151 12:40:47.029457  CA_PICK                    = 1600

 7152 12:40:47.032712  CA_MCKIO                   = 1600

 7153 12:40:47.035824  MCKIO_SEMI                 = 0

 7154 12:40:47.039748  PLL_FREQ                   = 3068

 7155 12:40:47.042378  DQ_UI_PI_RATIO             = 32

 7156 12:40:47.042462  CA_UI_PI_RATIO             = 0

 7157 12:40:47.046110  =================================== 

 7158 12:40:47.049210  =================================== 

 7159 12:40:47.053134  memory_type:LPDDR4         

 7160 12:40:47.056366  GP_NUM     : 10       

 7161 12:40:47.056480  SRAM_EN    : 1       

 7162 12:40:47.059047  MD32_EN    : 0       

 7163 12:40:47.062468  =================================== 

 7164 12:40:47.065717  [ANA_INIT] >>>>>>>>>>>>>> 

 7165 12:40:47.069423  <<<<<< [CONFIGURE PHASE]: ANA_TX

 7166 12:40:47.072904  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 7167 12:40:47.075893  =================================== 

 7168 12:40:47.075981  data_rate = 3200,PCW = 0X7600

 7169 12:40:47.079717  =================================== 

 7170 12:40:47.083111  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 7171 12:40:47.089292  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 7172 12:40:47.095851  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 7173 12:40:47.099186  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 7174 12:40:47.102659  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 7175 12:40:47.105701  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 7176 12:40:47.109263  [ANA_INIT] flow start 

 7177 12:40:47.109352  [ANA_INIT] PLL >>>>>>>> 

 7178 12:40:47.112452  [ANA_INIT] PLL <<<<<<<< 

 7179 12:40:47.115938  [ANA_INIT] MIDPI >>>>>>>> 

 7180 12:40:47.119111  [ANA_INIT] MIDPI <<<<<<<< 

 7181 12:40:47.119205  [ANA_INIT] DLL >>>>>>>> 

 7182 12:40:47.122586  [ANA_INIT] DLL <<<<<<<< 

 7183 12:40:47.122676  [ANA_INIT] flow end 

 7184 12:40:47.129543  ============ LP4 DIFF to SE enter ============

 7185 12:40:47.132667  ============ LP4 DIFF to SE exit  ============

 7186 12:40:47.135722  [ANA_INIT] <<<<<<<<<<<<< 

 7187 12:40:47.139458  [Flow] Enable top DCM control >>>>> 

 7188 12:40:47.142609  [Flow] Enable top DCM control <<<<< 

 7189 12:40:47.142719  Enable DLL master slave shuffle 

 7190 12:40:47.149094  ============================================================== 

 7191 12:40:47.152535  Gating Mode config

 7192 12:40:47.156026  ============================================================== 

 7193 12:40:47.159205  Config description: 

 7194 12:40:47.168929  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 7195 12:40:47.176058  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 7196 12:40:47.179210  SELPH_MODE            0: By rank         1: By Phase 

 7197 12:40:47.185622  ============================================================== 

 7198 12:40:47.189505  GAT_TRACK_EN                 =  1

 7199 12:40:47.192495  RX_GATING_MODE               =  2

 7200 12:40:47.195604  RX_GATING_TRACK_MODE         =  2

 7201 12:40:47.198840  SELPH_MODE                   =  1

 7202 12:40:47.198961  PICG_EARLY_EN                =  1

 7203 12:40:47.202820  VALID_LAT_VALUE              =  1

 7204 12:40:47.208890  ============================================================== 

 7205 12:40:47.212718  Enter into Gating configuration >>>> 

 7206 12:40:47.216051  Exit from Gating configuration <<<< 

 7207 12:40:47.219174  Enter into  DVFS_PRE_config >>>>> 

 7208 12:40:47.228924  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 7209 12:40:47.232500  Exit from  DVFS_PRE_config <<<<< 

 7210 12:40:47.235513  Enter into PICG configuration >>>> 

 7211 12:40:47.239346  Exit from PICG configuration <<<< 

 7212 12:40:47.242207  [RX_INPUT] configuration >>>>> 

 7213 12:40:47.245957  [RX_INPUT] configuration <<<<< 

 7214 12:40:47.249209  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 7215 12:40:47.255660  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 7216 12:40:47.262429  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 7217 12:40:47.268783  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 7218 12:40:47.275990  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 7219 12:40:47.279285  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 7220 12:40:47.285562  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 7221 12:40:47.289130  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 7222 12:40:47.292083  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 7223 12:40:47.295494  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 7224 12:40:47.299196  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 7225 12:40:47.305692  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7226 12:40:47.309010  =================================== 

 7227 12:40:47.312451  LPDDR4 DRAM CONFIGURATION

 7228 12:40:47.315667  =================================== 

 7229 12:40:47.315748  EX_ROW_EN[0]    = 0x0

 7230 12:40:47.318710  EX_ROW_EN[1]    = 0x0

 7231 12:40:47.318816  LP4Y_EN      = 0x0

 7232 12:40:47.322424  WORK_FSP     = 0x1

 7233 12:40:47.322533  WL           = 0x5

 7234 12:40:47.325716  RL           = 0x5

 7235 12:40:47.325823  BL           = 0x2

 7236 12:40:47.328916  RPST         = 0x0

 7237 12:40:47.329010  RD_PRE       = 0x0

 7238 12:40:47.331952  WR_PRE       = 0x1

 7239 12:40:47.332038  WR_PST       = 0x1

 7240 12:40:47.335601  DBI_WR       = 0x0

 7241 12:40:47.335705  DBI_RD       = 0x0

 7242 12:40:47.338688  OTF          = 0x1

 7243 12:40:47.342320  =================================== 

 7244 12:40:47.345220  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 7245 12:40:47.348729  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 7246 12:40:47.355413  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7247 12:40:47.358652  =================================== 

 7248 12:40:47.358746  LPDDR4 DRAM CONFIGURATION

 7249 12:40:47.361786  =================================== 

 7250 12:40:47.365400  EX_ROW_EN[0]    = 0x10

 7251 12:40:47.368561  EX_ROW_EN[1]    = 0x0

 7252 12:40:47.368670  LP4Y_EN      = 0x0

 7253 12:40:47.371835  WORK_FSP     = 0x1

 7254 12:40:47.371923  WL           = 0x5

 7255 12:40:47.375775  RL           = 0x5

 7256 12:40:47.375855  BL           = 0x2

 7257 12:40:47.378696  RPST         = 0x0

 7258 12:40:47.378771  RD_PRE       = 0x0

 7259 12:40:47.382036  WR_PRE       = 0x1

 7260 12:40:47.382112  WR_PST       = 0x1

 7261 12:40:47.385160  DBI_WR       = 0x0

 7262 12:40:47.385236  DBI_RD       = 0x0

 7263 12:40:47.388421  OTF          = 0x1

 7264 12:40:47.392145  =================================== 

 7265 12:40:47.398862  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 7266 12:40:47.398945  ==

 7267 12:40:47.401766  Dram Type= 6, Freq= 0, CH_0, rank 0

 7268 12:40:47.405303  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7269 12:40:47.405380  ==

 7270 12:40:47.408430  [Duty_Offset_Calibration]

 7271 12:40:47.408507  	B0:2	B1:1	CA:1

 7272 12:40:47.408571  

 7273 12:40:47.411710  [DutyScan_Calibration_Flow] k_type=0

 7274 12:40:47.422435  

 7275 12:40:47.422526  ==CLK 0==

 7276 12:40:47.426104  Final CLK duty delay cell = 0

 7277 12:40:47.429428  [0] MAX Duty = 5156%(X100), DQS PI = 22

 7278 12:40:47.432526  [0] MIN Duty = 4876%(X100), DQS PI = 48

 7279 12:40:47.432618  [0] AVG Duty = 5016%(X100)

 7280 12:40:47.436184  

 7281 12:40:47.439447  CH0 CLK Duty spec in!! Max-Min= 280%

 7282 12:40:47.442754  [DutyScan_Calibration_Flow] ====Done====

 7283 12:40:47.442844  

 7284 12:40:47.445598  [DutyScan_Calibration_Flow] k_type=1

 7285 12:40:47.461940  

 7286 12:40:47.462080  ==DQS 0 ==

 7287 12:40:47.465463  Final DQS duty delay cell = -4

 7288 12:40:47.468870  [-4] MAX Duty = 5125%(X100), DQS PI = 24

 7289 12:40:47.471748  [-4] MIN Duty = 4657%(X100), DQS PI = 0

 7290 12:40:47.475492  [-4] AVG Duty = 4891%(X100)

 7291 12:40:47.475584  

 7292 12:40:47.475660  ==DQS 1 ==

 7293 12:40:47.478639  Final DQS duty delay cell = 0

 7294 12:40:47.481790  [0] MAX Duty = 5187%(X100), DQS PI = 20

 7295 12:40:47.484962  [0] MIN Duty = 5062%(X100), DQS PI = 32

 7296 12:40:47.488224  [0] AVG Duty = 5124%(X100)

 7297 12:40:47.488333  

 7298 12:40:47.491395  CH0 DQS 0 Duty spec in!! Max-Min= 468%

 7299 12:40:47.491470  

 7300 12:40:47.494721  CH0 DQS 1 Duty spec in!! Max-Min= 125%

 7301 12:40:47.498469  [DutyScan_Calibration_Flow] ====Done====

 7302 12:40:47.498573  

 7303 12:40:47.501523  [DutyScan_Calibration_Flow] k_type=3

 7304 12:40:47.518444  

 7305 12:40:47.518586  ==DQM 0 ==

 7306 12:40:47.522103  Final DQM duty delay cell = 0

 7307 12:40:47.525364  [0] MAX Duty = 5187%(X100), DQS PI = 26

 7308 12:40:47.528438  [0] MIN Duty = 4907%(X100), DQS PI = 56

 7309 12:40:47.528558  [0] AVG Duty = 5047%(X100)

 7310 12:40:47.532102  

 7311 12:40:47.532195  ==DQM 1 ==

 7312 12:40:47.535494  Final DQM duty delay cell = -4

 7313 12:40:47.538613  [-4] MAX Duty = 4969%(X100), DQS PI = 22

 7314 12:40:47.541704  [-4] MIN Duty = 4844%(X100), DQS PI = 12

 7315 12:40:47.545593  [-4] AVG Duty = 4906%(X100)

 7316 12:40:47.545712  

 7317 12:40:47.548653  CH0 DQM 0 Duty spec in!! Max-Min= 280%

 7318 12:40:47.548762  

 7319 12:40:47.551805  CH0 DQM 1 Duty spec in!! Max-Min= 125%

 7320 12:40:47.554971  [DutyScan_Calibration_Flow] ====Done====

 7321 12:40:47.555057  

 7322 12:40:47.558649  [DutyScan_Calibration_Flow] k_type=2

 7323 12:40:47.576290  

 7324 12:40:47.576473  ==DQ 0 ==

 7325 12:40:47.579292  Final DQ duty delay cell = 0

 7326 12:40:47.582911  [0] MAX Duty = 5062%(X100), DQS PI = 24

 7327 12:40:47.586166  [0] MIN Duty = 4907%(X100), DQS PI = 0

 7328 12:40:47.586259  [0] AVG Duty = 4984%(X100)

 7329 12:40:47.586322  

 7330 12:40:47.589456  ==DQ 1 ==

 7331 12:40:47.592669  Final DQ duty delay cell = 0

 7332 12:40:47.595912  [0] MAX Duty = 5094%(X100), DQS PI = 4

 7333 12:40:47.599054  [0] MIN Duty = 4938%(X100), DQS PI = 34

 7334 12:40:47.599136  [0] AVG Duty = 5016%(X100)

 7335 12:40:47.599200  

 7336 12:40:47.602895  CH0 DQ 0 Duty spec in!! Max-Min= 155%

 7337 12:40:47.606111  

 7338 12:40:47.609217  CH0 DQ 1 Duty spec in!! Max-Min= 156%

 7339 12:40:47.612371  [DutyScan_Calibration_Flow] ====Done====

 7340 12:40:47.612481  ==

 7341 12:40:47.616126  Dram Type= 6, Freq= 0, CH_1, rank 0

 7342 12:40:47.619315  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7343 12:40:47.619429  ==

 7344 12:40:47.622325  [Duty_Offset_Calibration]

 7345 12:40:47.622434  	B0:1	B1:0	CA:0

 7346 12:40:47.622531  

 7347 12:40:47.625530  [DutyScan_Calibration_Flow] k_type=0

 7348 12:40:47.635530  

 7349 12:40:47.635667  ==CLK 0==

 7350 12:40:47.638645  Final CLK duty delay cell = -4

 7351 12:40:47.641752  [-4] MAX Duty = 5000%(X100), DQS PI = 22

 7352 12:40:47.645512  [-4] MIN Duty = 4844%(X100), DQS PI = 50

 7353 12:40:47.648725  [-4] AVG Duty = 4922%(X100)

 7354 12:40:47.648841  

 7355 12:40:47.651848  CH1 CLK Duty spec in!! Max-Min= 156%

 7356 12:40:47.655443  [DutyScan_Calibration_Flow] ====Done====

 7357 12:40:47.655553  

 7358 12:40:47.658654  [DutyScan_Calibration_Flow] k_type=1

 7359 12:40:47.674452  

 7360 12:40:47.674582  ==DQS 0 ==

 7361 12:40:47.678255  Final DQS duty delay cell = 0

 7362 12:40:47.681602  [0] MAX Duty = 5094%(X100), DQS PI = 28

 7363 12:40:47.684763  [0] MIN Duty = 4844%(X100), DQS PI = 0

 7364 12:40:47.684878  [0] AVG Duty = 4969%(X100)

 7365 12:40:47.684977  

 7366 12:40:47.688360  ==DQS 1 ==

 7367 12:40:47.691674  Final DQS duty delay cell = -4

 7368 12:40:47.694802  [-4] MAX Duty = 4969%(X100), DQS PI = 16

 7369 12:40:47.698040  [-4] MIN Duty = 4750%(X100), DQS PI = 10

 7370 12:40:47.701343  [-4] AVG Duty = 4859%(X100)

 7371 12:40:47.701452  

 7372 12:40:47.705153  CH1 DQS 0 Duty spec in!! Max-Min= 250%

 7373 12:40:47.705262  

 7374 12:40:47.708230  CH1 DQS 1 Duty spec in!! Max-Min= 219%

 7375 12:40:47.711363  [DutyScan_Calibration_Flow] ====Done====

 7376 12:40:47.711474  

 7377 12:40:47.714657  [DutyScan_Calibration_Flow] k_type=3

 7378 12:40:47.731845  

 7379 12:40:47.732006  ==DQM 0 ==

 7380 12:40:47.735023  Final DQM duty delay cell = 0

 7381 12:40:47.738238  [0] MAX Duty = 5218%(X100), DQS PI = 20

 7382 12:40:47.741716  [0] MIN Duty = 4969%(X100), DQS PI = 48

 7383 12:40:47.745102  [0] AVG Duty = 5093%(X100)

 7384 12:40:47.745209  

 7385 12:40:47.745306  ==DQM 1 ==

 7386 12:40:47.748298  Final DQM duty delay cell = 0

 7387 12:40:47.751983  [0] MAX Duty = 5093%(X100), DQS PI = 16

 7388 12:40:47.755292  [0] MIN Duty = 4938%(X100), DQS PI = 6

 7389 12:40:47.758321  [0] AVG Duty = 5015%(X100)

 7390 12:40:47.758435  

 7391 12:40:47.761510  CH1 DQM 0 Duty spec in!! Max-Min= 249%

 7392 12:40:47.761616  

 7393 12:40:47.764799  CH1 DQM 1 Duty spec in!! Max-Min= 155%

 7394 12:40:47.768072  [DutyScan_Calibration_Flow] ====Done====

 7395 12:40:47.768178  

 7396 12:40:47.771739  [DutyScan_Calibration_Flow] k_type=2

 7397 12:40:47.788147  

 7398 12:40:47.788286  ==DQ 0 ==

 7399 12:40:47.791147  Final DQ duty delay cell = -4

 7400 12:40:47.795060  [-4] MAX Duty = 5062%(X100), DQS PI = 12

 7401 12:40:47.797883  [-4] MIN Duty = 4875%(X100), DQS PI = 46

 7402 12:40:47.801140  [-4] AVG Duty = 4968%(X100)

 7403 12:40:47.801255  

 7404 12:40:47.801350  ==DQ 1 ==

 7405 12:40:47.804340  Final DQ duty delay cell = 0

 7406 12:40:47.808126  [0] MAX Duty = 5124%(X100), DQS PI = 18

 7407 12:40:47.811401  [0] MIN Duty = 4969%(X100), DQS PI = 8

 7408 12:40:47.811518  [0] AVG Duty = 5046%(X100)

 7409 12:40:47.814530  

 7410 12:40:47.817797  CH1 DQ 0 Duty spec in!! Max-Min= 187%

 7411 12:40:47.817905  

 7412 12:40:47.821452  CH1 DQ 1 Duty spec in!! Max-Min= 155%

 7413 12:40:47.824545  [DutyScan_Calibration_Flow] ====Done====

 7414 12:40:47.827839  nWR fixed to 30

 7415 12:40:47.827951  [ModeRegInit_LP4] CH0 RK0

 7416 12:40:47.831317  [ModeRegInit_LP4] CH0 RK1

 7417 12:40:47.834599  [ModeRegInit_LP4] CH1 RK0

 7418 12:40:47.837678  [ModeRegInit_LP4] CH1 RK1

 7419 12:40:47.837795  match AC timing 5

 7420 12:40:47.841216  dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1

 7421 12:40:47.847641  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 7422 12:40:47.851273  [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14

 7423 12:40:47.858056  [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29

 7424 12:40:47.861307  [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)

 7425 12:40:47.861420  [MiockJmeterHQA]

 7426 12:40:47.861515  

 7427 12:40:47.864454  [DramcMiockJmeter] u1RxGatingPI = 0

 7428 12:40:47.867764  0 : 4253, 4027

 7429 12:40:47.867877  4 : 4363, 4138

 7430 12:40:47.871011  8 : 4255, 4029

 7431 12:40:47.871126  12 : 4363, 4137

 7432 12:40:47.871227  16 : 4253, 4026

 7433 12:40:47.874308  20 : 4252, 4027

 7434 12:40:47.874418  24 : 4252, 4027

 7435 12:40:47.877526  28 : 4363, 4137

 7436 12:40:47.877636  32 : 4363, 4138

 7437 12:40:47.881247  36 : 4253, 4026

 7438 12:40:47.881362  40 : 4252, 4027

 7439 12:40:47.884345  44 : 4252, 4027

 7440 12:40:47.884459  48 : 4253, 4026

 7441 12:40:47.884556  52 : 4254, 4029

 7442 12:40:47.887282  56 : 4363, 4137

 7443 12:40:47.887396  60 : 4253, 4027

 7444 12:40:47.891080  64 : 4253, 4026

 7445 12:40:47.891200  68 : 4250, 4026

 7446 12:40:47.894034  72 : 4255, 4030

 7447 12:40:47.894149  76 : 4250, 4026

 7448 12:40:47.894248  80 : 4361, 4137

 7449 12:40:47.897682  84 : 4361, 4136

 7450 12:40:47.897798  88 : 4250, 50

 7451 12:40:47.900860  92 : 4360, 0

 7452 12:40:47.900977  96 : 4250, 0

 7453 12:40:47.901081  100 : 4250, 0

 7454 12:40:47.904379  104 : 4250, 0

 7455 12:40:47.904498  108 : 4250, 0

 7456 12:40:47.907496  112 : 4252, 0

 7457 12:40:47.907614  116 : 4250, 0

 7458 12:40:47.907718  120 : 4250, 0

 7459 12:40:47.911182  124 : 4252, 0

 7460 12:40:47.911300  128 : 4250, 0

 7461 12:40:47.914370  132 : 4360, 0

 7462 12:40:47.914488  136 : 4361, 0

 7463 12:40:47.914594  140 : 4250, 0

 7464 12:40:47.917431  144 : 4250, 0

 7465 12:40:47.917542  148 : 4249, 0

 7466 12:40:47.917647  152 : 4250, 0

 7467 12:40:47.921212  156 : 4250, 0

 7468 12:40:47.921327  160 : 4249, 0

 7469 12:40:47.924422  164 : 4252, 0

 7470 12:40:47.924544  168 : 4250, 0

 7471 12:40:47.924648  172 : 4250, 0

 7472 12:40:47.927566  176 : 4252, 0

 7473 12:40:47.927680  180 : 4361, 0

 7474 12:40:47.930847  184 : 4360, 0

 7475 12:40:47.930967  188 : 4363, 0

 7476 12:40:47.931067  192 : 4250, 0

 7477 12:40:47.934114  196 : 4250, 0

 7478 12:40:47.934230  200 : 4363, 0

 7479 12:40:47.937372  204 : 4250, 1431

 7480 12:40:47.937496  208 : 4363, 4123

 7481 12:40:47.940628  212 : 4249, 4027

 7482 12:40:47.940743  216 : 4250, 4026

 7483 12:40:47.940857  220 : 4250, 4027

 7484 12:40:47.944142  224 : 4252, 4030

 7485 12:40:47.944257  228 : 4250, 4027

 7486 12:40:47.947210  232 : 4250, 4026

 7487 12:40:47.947322  236 : 4361, 4137

 7488 12:40:47.950890  240 : 4250, 4027

 7489 12:40:47.951005  244 : 4250, 4027

 7490 12:40:47.954105  248 : 4360, 4137

 7491 12:40:47.954230  252 : 4250, 4026

 7492 12:40:47.957814  256 : 4250, 4027

 7493 12:40:47.957938  260 : 4363, 4140

 7494 12:40:47.960954  264 : 4250, 4027

 7495 12:40:47.961077  268 : 4250, 4026

 7496 12:40:47.963913  272 : 4250, 4027

 7497 12:40:47.964028  276 : 4252, 4030

 7498 12:40:47.964136  280 : 4249, 4027

 7499 12:40:47.967513  284 : 4250, 4026

 7500 12:40:47.967624  288 : 4361, 4137

 7501 12:40:47.970770  292 : 4253, 4029

 7502 12:40:47.970885  296 : 4250, 4027

 7503 12:40:47.974072  300 : 4360, 4137

 7504 12:40:47.974183  304 : 4250, 4026

 7505 12:40:47.977209  308 : 4250, 3962

 7506 12:40:47.977323  312 : 4363, 1880

 7507 12:40:47.977427  

 7508 12:40:47.980403  	MIOCK jitter meter	ch=0

 7509 12:40:47.980514  

 7510 12:40:47.983769  1T = (312-88) = 224 dly cells

 7511 12:40:47.987673  Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps

 7512 12:40:47.990847  ==

 7513 12:40:47.994174  Dram Type= 6, Freq= 0, CH_0, rank 0

 7514 12:40:47.997672  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7515 12:40:47.997788  ==

 7516 12:40:48.000561  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 7517 12:40:48.007164  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1

 7518 12:40:48.011009  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1

 7519 12:40:48.017131  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 7520 12:40:48.025261  [CA 0] Center 42 (12~73) winsize 62

 7521 12:40:48.029040  [CA 1] Center 42 (12~73) winsize 62

 7522 12:40:48.032178  [CA 2] Center 38 (8~68) winsize 61

 7523 12:40:48.035624  [CA 3] Center 37 (8~67) winsize 60

 7524 12:40:48.038732  [CA 4] Center 36 (6~66) winsize 61

 7525 12:40:48.041981  [CA 5] Center 35 (6~64) winsize 59

 7526 12:40:48.042114  

 7527 12:40:48.045335  [CmdBusTrainingLP45] Vref(ca) range 0: 30

 7528 12:40:48.045440  

 7529 12:40:48.048877  [CATrainingPosCal] consider 1 rank data

 7530 12:40:48.051972  u2DelayCellTimex100 = 290/100 ps

 7531 12:40:48.055125  CA0 delay=42 (12~73),Diff = 7 PI (23 cell)

 7532 12:40:48.062073  CA1 delay=42 (12~73),Diff = 7 PI (23 cell)

 7533 12:40:48.065186  CA2 delay=38 (8~68),Diff = 3 PI (10 cell)

 7534 12:40:48.068746  CA3 delay=37 (8~67),Diff = 2 PI (6 cell)

 7535 12:40:48.071708  CA4 delay=36 (6~66),Diff = 1 PI (3 cell)

 7536 12:40:48.074859  CA5 delay=35 (6~64),Diff = 0 PI (0 cell)

 7537 12:40:48.074931  

 7538 12:40:48.078861  CA PerBit enable=1, Macro0, CA PI delay=35

 7539 12:40:48.078938  

 7540 12:40:48.081907  [CBTSetCACLKResult] CA Dly = 35

 7541 12:40:48.084989  CS Dly: 8 (0~39)

 7542 12:40:48.088332  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0

 7543 12:40:48.091617  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0

 7544 12:40:48.091714  ==

 7545 12:40:48.094825  Dram Type= 6, Freq= 0, CH_0, rank 1

 7546 12:40:48.098754  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7547 12:40:48.101844  ==

 7548 12:40:48.104951  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 7549 12:40:48.108501  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1

 7550 12:40:48.115008  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1

 7551 12:40:48.118713  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 7552 12:40:48.128795  [CA 0] Center 42 (12~73) winsize 62

 7553 12:40:48.132013  [CA 1] Center 42 (12~73) winsize 62

 7554 12:40:48.135121  [CA 2] Center 37 (8~67) winsize 60

 7555 12:40:48.139014  [CA 3] Center 38 (8~68) winsize 61

 7556 12:40:48.142117  [CA 4] Center 35 (5~65) winsize 61

 7557 12:40:48.145291  [CA 5] Center 35 (5~65) winsize 61

 7558 12:40:48.145412  

 7559 12:40:48.148414  [CmdBusTrainingLP45] Vref(ca) range 0: 30

 7560 12:40:48.148519  

 7561 12:40:48.152107  [CATrainingPosCal] consider 2 rank data

 7562 12:40:48.155345  u2DelayCellTimex100 = 290/100 ps

 7563 12:40:48.158654  CA0 delay=42 (12~73),Diff = 7 PI (23 cell)

 7564 12:40:48.165395  CA1 delay=42 (12~73),Diff = 7 PI (23 cell)

 7565 12:40:48.168699  CA2 delay=37 (8~67),Diff = 2 PI (6 cell)

 7566 12:40:48.171680  CA3 delay=37 (8~67),Diff = 2 PI (6 cell)

 7567 12:40:48.175110  CA4 delay=35 (6~65),Diff = 0 PI (0 cell)

 7568 12:40:48.178669  CA5 delay=35 (6~64),Diff = 0 PI (0 cell)

 7569 12:40:48.178774  

 7570 12:40:48.181619  CA PerBit enable=1, Macro0, CA PI delay=35

 7571 12:40:48.181726  

 7572 12:40:48.185356  [CBTSetCACLKResult] CA Dly = 35

 7573 12:40:48.188555  CS Dly: 9 (0~42)

 7574 12:40:48.191913  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0

 7575 12:40:48.195128  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0

 7576 12:40:48.195230  

 7577 12:40:48.198286  ----->DramcWriteLeveling(PI) begin...

 7578 12:40:48.198369  ==

 7579 12:40:48.201526  Dram Type= 6, Freq= 0, CH_0, rank 0

 7580 12:40:48.205388  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7581 12:40:48.208676  ==

 7582 12:40:48.208788  Write leveling (Byte 0): 37 => 37

 7583 12:40:48.211744  Write leveling (Byte 1): 27 => 27

 7584 12:40:48.215472  DramcWriteLeveling(PI) end<-----

 7585 12:40:48.215576  

 7586 12:40:48.215667  ==

 7587 12:40:48.218493  Dram Type= 6, Freq= 0, CH_0, rank 0

 7588 12:40:48.225121  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7589 12:40:48.225236  ==

 7590 12:40:48.225335  [Gating] SW mode calibration

 7591 12:40:48.234915  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 7592 12:40:48.238537  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 7593 12:40:48.241747   1  4  0 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)

 7594 12:40:48.248566   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7595 12:40:48.251742   1  4  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7596 12:40:48.255509   1  4 12 | B1->B0 | 2323 3938 | 0 1 | (0 0) (1 1)

 7597 12:40:48.261899   1  4 16 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)

 7598 12:40:48.265197   1  4 20 | B1->B0 | 3434 3938 | 0 1 | (0 0) (0 0)

 7599 12:40:48.268731   1  4 24 | B1->B0 | 3434 3736 | 1 1 | (1 1) (1 1)

 7600 12:40:48.275210   1  4 28 | B1->B0 | 3434 3737 | 1 0 | (1 1) (1 1)

 7601 12:40:48.278525   1  5  0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)

 7602 12:40:48.282089   1  5  4 | B1->B0 | 3434 3938 | 1 1 | (1 1) (0 0)

 7603 12:40:48.288639   1  5  8 | B1->B0 | 3434 3332 | 1 1 | (1 1) (0 0)

 7604 12:40:48.292097   1  5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)

 7605 12:40:48.294847   1  5 16 | B1->B0 | 3434 2423 | 1 1 | (1 0) (0 0)

 7606 12:40:48.301885   1  5 20 | B1->B0 | 2626 2a29 | 0 1 | (1 0) (1 1)

 7607 12:40:48.305322   1  5 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)

 7608 12:40:48.308287   1  5 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)

 7609 12:40:48.315403   1  6  0 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)

 7610 12:40:48.318571   1  6  4 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)

 7611 12:40:48.321778   1  6  8 | B1->B0 | 2323 3231 | 0 1 | (0 0) (0 0)

 7612 12:40:48.328232   1  6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)

 7613 12:40:48.331465   1  6 16 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)

 7614 12:40:48.335045   1  6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)

 7615 12:40:48.341755   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7616 12:40:48.345271   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7617 12:40:48.348172   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7618 12:40:48.355206   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7619 12:40:48.358448   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 7620 12:40:48.361485   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 7621 12:40:48.365208   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 7622 12:40:48.371540   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7623 12:40:48.374557   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7624 12:40:48.377829   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7625 12:40:48.384917   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7626 12:40:48.388018   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7627 12:40:48.391814   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7628 12:40:48.397968   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7629 12:40:48.401609   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7630 12:40:48.404759   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7631 12:40:48.411922   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7632 12:40:48.415191   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7633 12:40:48.418342   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7634 12:40:48.424735   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7635 12:40:48.428508   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7636 12:40:48.431458   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 7637 12:40:48.438250   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 7638 12:40:48.438390  Total UI for P1: 0, mck2ui 16

 7639 12:40:48.441372  best dqsien dly found for B0: ( 1,  9, 12)

 7640 12:40:48.448494   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 7641 12:40:48.451517   1  9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7642 12:40:48.455103  Total UI for P1: 0, mck2ui 16

 7643 12:40:48.458027  best dqsien dly found for B1: ( 1,  9, 18)

 7644 12:40:48.461428  best DQS0 dly(MCK, UI, PI) = (1, 9, 12)

 7645 12:40:48.464940  best DQS1 dly(MCK, UI, PI) = (1, 9, 18)

 7646 12:40:48.465038  

 7647 12:40:48.468285  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)

 7648 12:40:48.474773  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)

 7649 12:40:48.474863  [Gating] SW calibration Done

 7650 12:40:48.474931  ==

 7651 12:40:48.477853  Dram Type= 6, Freq= 0, CH_0, rank 0

 7652 12:40:48.484927  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7653 12:40:48.485015  ==

 7654 12:40:48.485083  RX Vref Scan: 0

 7655 12:40:48.485155  

 7656 12:40:48.487896  RX Vref 0 -> 0, step: 1

 7657 12:40:48.487983  

 7658 12:40:48.491215  RX Delay 0 -> 252, step: 8

 7659 12:40:48.494863  iDelay=200, Bit 0, Center 135 (80 ~ 191) 112

 7660 12:40:48.498048  iDelay=200, Bit 1, Center 143 (88 ~ 199) 112

 7661 12:40:48.501301  iDelay=200, Bit 2, Center 135 (80 ~ 191) 112

 7662 12:40:48.504488  iDelay=200, Bit 3, Center 131 (80 ~ 183) 104

 7663 12:40:48.511313  iDelay=200, Bit 4, Center 139 (88 ~ 191) 104

 7664 12:40:48.514481  iDelay=200, Bit 5, Center 123 (72 ~ 175) 104

 7665 12:40:48.517826  iDelay=200, Bit 6, Center 147 (96 ~ 199) 104

 7666 12:40:48.521043  iDelay=200, Bit 7, Center 143 (96 ~ 191) 96

 7667 12:40:48.524828  iDelay=200, Bit 8, Center 119 (72 ~ 167) 96

 7668 12:40:48.531222  iDelay=200, Bit 9, Center 123 (72 ~ 175) 104

 7669 12:40:48.534762  iDelay=200, Bit 10, Center 131 (80 ~ 183) 104

 7670 12:40:48.538026  iDelay=200, Bit 11, Center 123 (72 ~ 175) 104

 7671 12:40:48.541205  iDelay=200, Bit 12, Center 135 (80 ~ 191) 112

 7672 12:40:48.547831  iDelay=200, Bit 13, Center 135 (80 ~ 191) 112

 7673 12:40:48.551026  iDelay=200, Bit 14, Center 139 (88 ~ 191) 104

 7674 12:40:48.554151  iDelay=200, Bit 15, Center 135 (80 ~ 191) 112

 7675 12:40:48.554240  ==

 7676 12:40:48.557980  Dram Type= 6, Freq= 0, CH_0, rank 0

 7677 12:40:48.560770  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7678 12:40:48.560874  ==

 7679 12:40:48.564281  DQS Delay:

 7680 12:40:48.564374  DQS0 = 0, DQS1 = 0

 7681 12:40:48.567419  DQM Delay:

 7682 12:40:48.567505  DQM0 = 137, DQM1 = 130

 7683 12:40:48.567572  DQ Delay:

 7684 12:40:48.571104  DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131

 7685 12:40:48.577676  DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143

 7686 12:40:48.580861  DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123

 7687 12:40:48.584864  DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135

 7688 12:40:48.584950  

 7689 12:40:48.585017  

 7690 12:40:48.585080  ==

 7691 12:40:48.587697  Dram Type= 6, Freq= 0, CH_0, rank 0

 7692 12:40:48.590837  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7693 12:40:48.590951  ==

 7694 12:40:48.591048  

 7695 12:40:48.591138  

 7696 12:40:48.594604  	TX Vref Scan disable

 7697 12:40:48.597719   == TX Byte 0 ==

 7698 12:40:48.600795  Update DQ  dly =992 (3 ,6, 32)  DQ  OEN =(3 ,3)

 7699 12:40:48.604525  Update DQM dly =992 (3 ,6, 32)  DQM OEN =(3 ,3)

 7700 12:40:48.607700   == TX Byte 1 ==

 7701 12:40:48.610775  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 7702 12:40:48.614478  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 7703 12:40:48.614566  ==

 7704 12:40:48.617570  Dram Type= 6, Freq= 0, CH_0, rank 0

 7705 12:40:48.620700  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7706 12:40:48.620795  ==

 7707 12:40:48.636260  

 7708 12:40:48.639743  TX Vref early break, caculate TX vref

 7709 12:40:48.643047  TX Vref=16, minBit 0, minWin=23, winSum=379

 7710 12:40:48.646250  TX Vref=18, minBit 0, minWin=23, winSum=387

 7711 12:40:48.649285  TX Vref=20, minBit 0, minWin=23, winSum=396

 7712 12:40:48.653015  TX Vref=22, minBit 0, minWin=24, winSum=406

 7713 12:40:48.655961  TX Vref=24, minBit 4, minWin=24, winSum=412

 7714 12:40:48.662767  TX Vref=26, minBit 0, minWin=25, winSum=422

 7715 12:40:48.665805  TX Vref=28, minBit 2, minWin=24, winSum=419

 7716 12:40:48.669504  TX Vref=30, minBit 6, minWin=24, winSum=410

 7717 12:40:48.673124  TX Vref=32, minBit 0, minWin=24, winSum=402

 7718 12:40:48.676123  TX Vref=34, minBit 1, minWin=23, winSum=392

 7719 12:40:48.682496  [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 26

 7720 12:40:48.682589  

 7721 12:40:48.685762  Final TX Range 0 Vref 26

 7722 12:40:48.685849  

 7723 12:40:48.685917  ==

 7724 12:40:48.689545  Dram Type= 6, Freq= 0, CH_0, rank 0

 7725 12:40:48.692582  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7726 12:40:48.692669  ==

 7727 12:40:48.692735  

 7728 12:40:48.692798  

 7729 12:40:48.696121  	TX Vref Scan disable

 7730 12:40:48.702942  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps

 7731 12:40:48.703068   == TX Byte 0 ==

 7732 12:40:48.706030  u2DelayCellOfst[0]=13 cells (4 PI)

 7733 12:40:48.709156  u2DelayCellOfst[1]=16 cells (5 PI)

 7734 12:40:48.712419  u2DelayCellOfst[2]=13 cells (4 PI)

 7735 12:40:48.715883  u2DelayCellOfst[3]=13 cells (4 PI)

 7736 12:40:48.719562  u2DelayCellOfst[4]=10 cells (3 PI)

 7737 12:40:48.722516  u2DelayCellOfst[5]=0 cells (0 PI)

 7738 12:40:48.725784  u2DelayCellOfst[6]=16 cells (5 PI)

 7739 12:40:48.729003  u2DelayCellOfst[7]=20 cells (6 PI)

 7740 12:40:48.732240  Update DQ  dly =990 (3 ,6, 30)  DQ  OEN =(3 ,3)

 7741 12:40:48.735521  Update DQM dly =993 (3 ,6, 33)  DQM OEN =(3 ,3)

 7742 12:40:48.739419   == TX Byte 1 ==

 7743 12:40:48.739513  u2DelayCellOfst[8]=0 cells (0 PI)

 7744 12:40:48.742484  u2DelayCellOfst[9]=0 cells (0 PI)

 7745 12:40:48.745764  u2DelayCellOfst[10]=6 cells (2 PI)

 7746 12:40:48.748954  u2DelayCellOfst[11]=3 cells (1 PI)

 7747 12:40:48.752135  u2DelayCellOfst[12]=10 cells (3 PI)

 7748 12:40:48.755875  u2DelayCellOfst[13]=10 cells (3 PI)

 7749 12:40:48.758968  u2DelayCellOfst[14]=16 cells (5 PI)

 7750 12:40:48.762749  u2DelayCellOfst[15]=10 cells (3 PI)

 7751 12:40:48.765859  Update DQ  dly =979 (3 ,6, 19)  DQ  OEN =(3 ,3)

 7752 12:40:48.772329  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 7753 12:40:48.772444  DramC Write-DBI on

 7754 12:40:48.772544  ==

 7755 12:40:48.775821  Dram Type= 6, Freq= 0, CH_0, rank 0

 7756 12:40:48.778986  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7757 12:40:48.782494  ==

 7758 12:40:48.782609  

 7759 12:40:48.782705  

 7760 12:40:48.782799  	TX Vref Scan disable

 7761 12:40:48.785586   == TX Byte 0 ==

 7762 12:40:48.789442  Update DQM dly =736 (2 ,6, 32)  DQM OEN =(3 ,3)

 7763 12:40:48.792658   == TX Byte 1 ==

 7764 12:40:48.796018  Update DQM dly =722 (2 ,6, 18)  DQM OEN =(3 ,3)

 7765 12:40:48.799064  DramC Write-DBI off

 7766 12:40:48.799155  

 7767 12:40:48.799222  [DATLAT]

 7768 12:40:48.799285  Freq=1600, CH0 RK0

 7769 12:40:48.799346  

 7770 12:40:48.802456  DATLAT Default: 0xf

 7771 12:40:48.802545  0, 0xFFFF, sum = 0

 7772 12:40:48.805373  1, 0xFFFF, sum = 0

 7773 12:40:48.808702  2, 0xFFFF, sum = 0

 7774 12:40:48.808828  3, 0xFFFF, sum = 0

 7775 12:40:48.812374  4, 0xFFFF, sum = 0

 7776 12:40:48.812485  5, 0xFFFF, sum = 0

 7777 12:40:48.815467  6, 0xFFFF, sum = 0

 7778 12:40:48.815558  7, 0xFFFF, sum = 0

 7779 12:40:48.819257  8, 0xFFFF, sum = 0

 7780 12:40:48.819352  9, 0xFFFF, sum = 0

 7781 12:40:48.822491  10, 0xFFFF, sum = 0

 7782 12:40:48.822579  11, 0xFFFF, sum = 0

 7783 12:40:48.825611  12, 0xFFFF, sum = 0

 7784 12:40:48.825699  13, 0xFFFF, sum = 0

 7785 12:40:48.829292  14, 0x0, sum = 1

 7786 12:40:48.829386  15, 0x0, sum = 2

 7787 12:40:48.832474  16, 0x0, sum = 3

 7788 12:40:48.832566  17, 0x0, sum = 4

 7789 12:40:48.835832  best_step = 15

 7790 12:40:48.835921  

 7791 12:40:48.835989  ==

 7792 12:40:48.839053  Dram Type= 6, Freq= 0, CH_0, rank 0

 7793 12:40:48.842343  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7794 12:40:48.842432  ==

 7795 12:40:48.842500  RX Vref Scan: 1

 7796 12:40:48.845554  

 7797 12:40:48.845644  Set Vref Range= 24 -> 127

 7798 12:40:48.845711  

 7799 12:40:48.849284  RX Vref 24 -> 127, step: 1

 7800 12:40:48.849370  

 7801 12:40:48.852531  RX Delay 27 -> 252, step: 4

 7802 12:40:48.852616  

 7803 12:40:48.855341  Set Vref, RX VrefLevel [Byte0]: 24

 7804 12:40:48.859083                           [Byte1]: 24

 7805 12:40:48.859169  

 7806 12:40:48.862361  Set Vref, RX VrefLevel [Byte0]: 25

 7807 12:40:48.865536                           [Byte1]: 25

 7808 12:40:48.865637  

 7809 12:40:48.869124  Set Vref, RX VrefLevel [Byte0]: 26

 7810 12:40:48.872246                           [Byte1]: 26

 7811 12:40:48.875872  

 7812 12:40:48.875987  Set Vref, RX VrefLevel [Byte0]: 27

 7813 12:40:48.879015                           [Byte1]: 27

 7814 12:40:48.883687  

 7815 12:40:48.883778  Set Vref, RX VrefLevel [Byte0]: 28

 7816 12:40:48.886550                           [Byte1]: 28

 7817 12:40:48.890883  

 7818 12:40:48.890973  Set Vref, RX VrefLevel [Byte0]: 29

 7819 12:40:48.894571                           [Byte1]: 29

 7820 12:40:48.898453  

 7821 12:40:48.898541  Set Vref, RX VrefLevel [Byte0]: 30

 7822 12:40:48.901729                           [Byte1]: 30

 7823 12:40:48.906134  

 7824 12:40:48.906233  Set Vref, RX VrefLevel [Byte0]: 31

 7825 12:40:48.909307                           [Byte1]: 31

 7826 12:40:48.913552  

 7827 12:40:48.913638  Set Vref, RX VrefLevel [Byte0]: 32

 7828 12:40:48.917378                           [Byte1]: 32

 7829 12:40:48.921267  

 7830 12:40:48.921356  Set Vref, RX VrefLevel [Byte0]: 33

 7831 12:40:48.924351                           [Byte1]: 33

 7832 12:40:48.928749  

 7833 12:40:48.928869  Set Vref, RX VrefLevel [Byte0]: 34

 7834 12:40:48.931944                           [Byte1]: 34

 7835 12:40:48.936347  

 7836 12:40:48.936435  Set Vref, RX VrefLevel [Byte0]: 35

 7837 12:40:48.939696                           [Byte1]: 35

 7838 12:40:48.943528  

 7839 12:40:48.943619  Set Vref, RX VrefLevel [Byte0]: 36

 7840 12:40:48.946861                           [Byte1]: 36

 7841 12:40:48.951267  

 7842 12:40:48.951353  Set Vref, RX VrefLevel [Byte0]: 37

 7843 12:40:48.954943                           [Byte1]: 37

 7844 12:40:48.958890  

 7845 12:40:48.958979  Set Vref, RX VrefLevel [Byte0]: 38

 7846 12:40:48.962156                           [Byte1]: 38

 7847 12:40:48.966595  

 7848 12:40:48.966680  Set Vref, RX VrefLevel [Byte0]: 39

 7849 12:40:48.969886                           [Byte1]: 39

 7850 12:40:48.973809  

 7851 12:40:48.973895  Set Vref, RX VrefLevel [Byte0]: 40

 7852 12:40:48.977466                           [Byte1]: 40

 7853 12:40:48.981833  

 7854 12:40:48.981923  Set Vref, RX VrefLevel [Byte0]: 41

 7855 12:40:48.985123                           [Byte1]: 41

 7856 12:40:48.989188  

 7857 12:40:48.989331  Set Vref, RX VrefLevel [Byte0]: 42

 7858 12:40:48.992128                           [Byte1]: 42

 7859 12:40:48.996246  

 7860 12:40:48.996381  Set Vref, RX VrefLevel [Byte0]: 43

 7861 12:40:48.999783                           [Byte1]: 43

 7862 12:40:49.004398  

 7863 12:40:49.004492  Set Vref, RX VrefLevel [Byte0]: 44

 7864 12:40:49.007577                           [Byte1]: 44

 7865 12:40:49.011437  

 7866 12:40:49.011574  Set Vref, RX VrefLevel [Byte0]: 45

 7867 12:40:49.015085                           [Byte1]: 45

 7868 12:40:49.019147  

 7869 12:40:49.019254  Set Vref, RX VrefLevel [Byte0]: 46

 7870 12:40:49.022170                           [Byte1]: 46

 7871 12:40:49.026728  

 7872 12:40:49.026834  Set Vref, RX VrefLevel [Byte0]: 47

 7873 12:40:49.030151                           [Byte1]: 47

 7874 12:40:49.034390  

 7875 12:40:49.034538  Set Vref, RX VrefLevel [Byte0]: 48

 7876 12:40:49.037552                           [Byte1]: 48

 7877 12:40:49.041898  

 7878 12:40:49.042029  Set Vref, RX VrefLevel [Byte0]: 49

 7879 12:40:49.045224                           [Byte1]: 49

 7880 12:40:49.049203  

 7881 12:40:49.049331  Set Vref, RX VrefLevel [Byte0]: 50

 7882 12:40:49.052308                           [Byte1]: 50

 7883 12:40:49.056699  

 7884 12:40:49.056813  Set Vref, RX VrefLevel [Byte0]: 51

 7885 12:40:49.060085                           [Byte1]: 51

 7886 12:40:49.064556  

 7887 12:40:49.064661  Set Vref, RX VrefLevel [Byte0]: 52

 7888 12:40:49.067788                           [Byte1]: 52

 7889 12:40:49.071705  

 7890 12:40:49.071868  Set Vref, RX VrefLevel [Byte0]: 53

 7891 12:40:49.075313                           [Byte1]: 53

 7892 12:40:49.079195  

 7893 12:40:49.079308  Set Vref, RX VrefLevel [Byte0]: 54

 7894 12:40:49.082480                           [Byte1]: 54

 7895 12:40:49.086709  

 7896 12:40:49.086819  Set Vref, RX VrefLevel [Byte0]: 55

 7897 12:40:49.090248                           [Byte1]: 55

 7898 12:40:49.094557  

 7899 12:40:49.094663  Set Vref, RX VrefLevel [Byte0]: 56

 7900 12:40:49.097572                           [Byte1]: 56

 7901 12:40:49.101657  

 7902 12:40:49.101762  Set Vref, RX VrefLevel [Byte0]: 57

 7903 12:40:49.105218                           [Byte1]: 57

 7904 12:40:49.109637  

 7905 12:40:49.109731  Set Vref, RX VrefLevel [Byte0]: 58

 7906 12:40:49.112734                           [Byte1]: 58

 7907 12:40:49.117102  

 7908 12:40:49.117192  Set Vref, RX VrefLevel [Byte0]: 59

 7909 12:40:49.120074                           [Byte1]: 59

 7910 12:40:49.124616  

 7911 12:40:49.124704  Set Vref, RX VrefLevel [Byte0]: 60

 7912 12:40:49.127906                           [Byte1]: 60

 7913 12:40:49.131677  

 7914 12:40:49.131782  Set Vref, RX VrefLevel [Byte0]: 61

 7915 12:40:49.135440                           [Byte1]: 61

 7916 12:40:49.139606  

 7917 12:40:49.139702  Set Vref, RX VrefLevel [Byte0]: 62

 7918 12:40:49.143197                           [Byte1]: 62

 7919 12:40:49.146776  

 7920 12:40:49.146868  Set Vref, RX VrefLevel [Byte0]: 63

 7921 12:40:49.150474                           [Byte1]: 63

 7922 12:40:49.154523  

 7923 12:40:49.154612  Set Vref, RX VrefLevel [Byte0]: 64

 7924 12:40:49.158241                           [Byte1]: 64

 7925 12:40:49.161945  

 7926 12:40:49.162034  Set Vref, RX VrefLevel [Byte0]: 65

 7927 12:40:49.165199                           [Byte1]: 65

 7928 12:40:49.169836  

 7929 12:40:49.169925  Set Vref, RX VrefLevel [Byte0]: 66

 7930 12:40:49.173033                           [Byte1]: 66

 7931 12:40:49.177536  

 7932 12:40:49.177625  Set Vref, RX VrefLevel [Byte0]: 67

 7933 12:40:49.180756                           [Byte1]: 67

 7934 12:40:49.184660  

 7935 12:40:49.184748  Set Vref, RX VrefLevel [Byte0]: 68

 7936 12:40:49.188407                           [Byte1]: 68

 7937 12:40:49.192123  

 7938 12:40:49.192223  Set Vref, RX VrefLevel [Byte0]: 69

 7939 12:40:49.195813                           [Byte1]: 69

 7940 12:40:49.199525  

 7941 12:40:49.199619  Set Vref, RX VrefLevel [Byte0]: 70

 7942 12:40:49.206302                           [Byte1]: 70

 7943 12:40:49.206396  

 7944 12:40:49.209753  Set Vref, RX VrefLevel [Byte0]: 71

 7945 12:40:49.212807                           [Byte1]: 71

 7946 12:40:49.212897  

 7947 12:40:49.216435  Set Vref, RX VrefLevel [Byte0]: 72

 7948 12:40:49.219729                           [Byte1]: 72

 7949 12:40:49.219818  

 7950 12:40:49.222829  Set Vref, RX VrefLevel [Byte0]: 73

 7951 12:40:49.225933                           [Byte1]: 73

 7952 12:40:49.229649  

 7953 12:40:49.229739  Set Vref, RX VrefLevel [Byte0]: 74

 7954 12:40:49.233360                           [Byte1]: 74

 7955 12:40:49.237273  

 7956 12:40:49.237362  Set Vref, RX VrefLevel [Byte0]: 75

 7957 12:40:49.240405                           [Byte1]: 75

 7958 12:40:49.244868  

 7959 12:40:49.244959  Set Vref, RX VrefLevel [Byte0]: 76

 7960 12:40:49.248403                           [Byte1]: 76

 7961 12:40:49.252839  

 7962 12:40:49.252925  Final RX Vref Byte 0 = 59 to rank0

 7963 12:40:49.255736  Final RX Vref Byte 1 = 66 to rank0

 7964 12:40:49.259392  Final RX Vref Byte 0 = 59 to rank1

 7965 12:40:49.262658  Final RX Vref Byte 1 = 66 to rank1==

 7966 12:40:49.265806  Dram Type= 6, Freq= 0, CH_0, rank 0

 7967 12:40:49.272335  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7968 12:40:49.272432  ==

 7969 12:40:49.272501  DQS Delay:

 7970 12:40:49.272564  DQS0 = 0, DQS1 = 0

 7971 12:40:49.275443  DQM Delay:

 7972 12:40:49.275533  DQM0 = 134, DQM1 = 128

 7973 12:40:49.278959  DQ Delay:

 7974 12:40:49.282599  DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =134

 7975 12:40:49.285942  DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140

 7976 12:40:49.289142  DQ8 =118, DQ9 =118, DQ10 =130, DQ11 =120

 7977 12:40:49.292401  DQ12 =132, DQ13 =132, DQ14 =140, DQ15 =136

 7978 12:40:49.292487  

 7979 12:40:49.292554  

 7980 12:40:49.292616  

 7981 12:40:49.295535  [DramC_TX_OE_Calibration] TA2

 7982 12:40:49.299456  Original DQ_B0 (3 6) =30, OEN = 27

 7983 12:40:49.302469  Original DQ_B1 (3 6) =30, OEN = 27

 7984 12:40:49.305554  24, 0x0, End_B0=24 End_B1=24

 7985 12:40:49.305657  25, 0x0, End_B0=25 End_B1=25

 7986 12:40:49.309417  26, 0x0, End_B0=26 End_B1=26

 7987 12:40:49.312279  27, 0x0, End_B0=27 End_B1=27

 7988 12:40:49.315839  28, 0x0, End_B0=28 End_B1=28

 7989 12:40:49.315963  29, 0x0, End_B0=29 End_B1=29

 7990 12:40:49.319008  30, 0x0, End_B0=30 End_B1=30

 7991 12:40:49.322592  31, 0x4141, End_B0=30 End_B1=30

 7992 12:40:49.325764  Byte0 end_step=30  best_step=27

 7993 12:40:49.328813  Byte1 end_step=30  best_step=27

 7994 12:40:49.332481  Byte0 TX OE(2T, 0.5T) = (3, 3)

 7995 12:40:49.335689  Byte1 TX OE(2T, 0.5T) = (3, 3)

 7996 12:40:49.335806  

 7997 12:40:49.335896  

 7998 12:40:49.342210  [DQSOSCAuto] RK0, (LSB)MR18= 0x2723, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps

 7999 12:40:49.345464  CH0 RK0: MR19=303, MR18=2723

 8000 12:40:49.352503  CH0_RK0: MR19=0x303, MR18=0x2723, DQSOSC=390, MR23=63, INC=24, DEC=16

 8001 12:40:49.352623  

 8002 12:40:49.355517  ----->DramcWriteLeveling(PI) begin...

 8003 12:40:49.355599  ==

 8004 12:40:49.358685  Dram Type= 6, Freq= 0, CH_0, rank 1

 8005 12:40:49.362290  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8006 12:40:49.362401  ==

 8007 12:40:49.365410  Write leveling (Byte 0): 35 => 35

 8008 12:40:49.369239  Write leveling (Byte 1): 26 => 26

 8009 12:40:49.372237  DramcWriteLeveling(PI) end<-----

 8010 12:40:49.372314  

 8011 12:40:49.372400  ==

 8012 12:40:49.375473  Dram Type= 6, Freq= 0, CH_0, rank 1

 8013 12:40:49.378670  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8014 12:40:49.378777  ==

 8015 12:40:49.381836  [Gating] SW mode calibration

 8016 12:40:49.388865  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8017 12:40:49.395452  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8018 12:40:49.398506   1  4  0 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)

 8019 12:40:49.402374   1  4  4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)

 8020 12:40:49.408671   1  4  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8021 12:40:49.412310   1  4 12 | B1->B0 | 2323 2f2e | 0 1 | (0 0) (0 0)

 8022 12:40:49.415357   1  4 16 | B1->B0 | 3232 3535 | 0 1 | (0 0) (0 0)

 8023 12:40:49.421827   1  4 20 | B1->B0 | 3434 3b3a | 1 1 | (1 1) (0 0)

 8024 12:40:49.425369   1  4 24 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)

 8025 12:40:49.428436   1  4 28 | B1->B0 | 3434 3939 | 1 1 | (1 1) (1 1)

 8026 12:40:49.435699   1  5  0 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1)

 8027 12:40:49.438771   1  5  4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)

 8028 12:40:49.441892   1  5  8 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)

 8029 12:40:49.448499   1  5 12 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)

 8030 12:40:49.452214   1  5 16 | B1->B0 | 2f2f 2b2b | 0 0 | (1 0) (0 0)

 8031 12:40:49.455520   1  5 20 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)

 8032 12:40:49.461880   1  5 24 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)

 8033 12:40:49.465589   1  5 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)

 8034 12:40:49.468685   1  6  0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 8035 12:40:49.475299   1  6  4 | B1->B0 | 2323 2625 | 0 1 | (0 0) (1 1)

 8036 12:40:49.478849   1  6  8 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)

 8037 12:40:49.482041   1  6 12 | B1->B0 | 2323 3130 | 0 1 | (0 0) (1 1)

 8038 12:40:49.488646   1  6 16 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)

 8039 12:40:49.491843   1  6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)

 8040 12:40:49.495081   1  6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)

 8041 12:40:49.498962   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8042 12:40:49.505376   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8043 12:40:49.508348   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8044 12:40:49.511599   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8045 12:40:49.518355   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8046 12:40:49.521949   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8047 12:40:49.525040   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8048 12:40:49.531468   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8049 12:40:49.535215   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8050 12:40:49.538353   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8051 12:40:49.544993   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8052 12:40:49.548239   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8053 12:40:49.552081   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8054 12:40:49.558392   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8055 12:40:49.561717   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8056 12:40:49.565042   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8057 12:40:49.571924   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8058 12:40:49.575006   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8059 12:40:49.578780   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8060 12:40:49.585212   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8061 12:40:49.588207   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8062 12:40:49.591518   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 8063 12:40:49.595225  Total UI for P1: 0, mck2ui 16

 8064 12:40:49.598360  best dqsien dly found for B0: ( 1,  9, 12)

 8065 12:40:49.601671   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8066 12:40:49.605460  Total UI for P1: 0, mck2ui 16

 8067 12:40:49.608644  best dqsien dly found for B1: ( 1,  9, 14)

 8068 12:40:49.611938  best DQS0 dly(MCK, UI, PI) = (1, 9, 12)

 8069 12:40:49.618487  best DQS1 dly(MCK, UI, PI) = (1, 9, 14)

 8070 12:40:49.618582  

 8071 12:40:49.621425  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)

 8072 12:40:49.625171  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)

 8073 12:40:49.628156  [Gating] SW calibration Done

 8074 12:40:49.628232  ==

 8075 12:40:49.631837  Dram Type= 6, Freq= 0, CH_0, rank 1

 8076 12:40:49.634718  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8077 12:40:49.634829  ==

 8078 12:40:49.638688  RX Vref Scan: 0

 8079 12:40:49.638800  

 8080 12:40:49.638900  RX Vref 0 -> 0, step: 1

 8081 12:40:49.638997  

 8082 12:40:49.641450  RX Delay 0 -> 252, step: 8

 8083 12:40:49.644771  iDelay=200, Bit 0, Center 135 (80 ~ 191) 112

 8084 12:40:49.648105  iDelay=200, Bit 1, Center 139 (88 ~ 191) 104

 8085 12:40:49.654983  iDelay=200, Bit 2, Center 135 (80 ~ 191) 112

 8086 12:40:49.658838  iDelay=200, Bit 3, Center 135 (80 ~ 191) 112

 8087 12:40:49.661836  iDelay=200, Bit 4, Center 139 (88 ~ 191) 104

 8088 12:40:49.665148  iDelay=200, Bit 5, Center 127 (72 ~ 183) 112

 8089 12:40:49.668321  iDelay=200, Bit 6, Center 143 (88 ~ 199) 112

 8090 12:40:49.674800  iDelay=200, Bit 7, Center 143 (88 ~ 199) 112

 8091 12:40:49.678131  iDelay=200, Bit 8, Center 119 (64 ~ 175) 112

 8092 12:40:49.681737  iDelay=200, Bit 9, Center 115 (64 ~ 167) 104

 8093 12:40:49.684877  iDelay=200, Bit 10, Center 127 (72 ~ 183) 112

 8094 12:40:49.687969  iDelay=200, Bit 11, Center 119 (64 ~ 175) 112

 8095 12:40:49.694999  iDelay=200, Bit 12, Center 135 (80 ~ 191) 112

 8096 12:40:49.698122  iDelay=200, Bit 13, Center 135 (80 ~ 191) 112

 8097 12:40:49.702063  iDelay=200, Bit 14, Center 135 (80 ~ 191) 112

 8098 12:40:49.705240  iDelay=200, Bit 15, Center 135 (80 ~ 191) 112

 8099 12:40:49.705364  ==

 8100 12:40:49.708367  Dram Type= 6, Freq= 0, CH_0, rank 1

 8101 12:40:49.714765  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8102 12:40:49.714887  ==

 8103 12:40:49.714988  DQS Delay:

 8104 12:40:49.715080  DQS0 = 0, DQS1 = 0

 8105 12:40:49.718024  DQM Delay:

 8106 12:40:49.718141  DQM0 = 137, DQM1 = 127

 8107 12:40:49.721960  DQ Delay:

 8108 12:40:49.724533  DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135

 8109 12:40:49.728372  DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143

 8110 12:40:49.731404  DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119

 8111 12:40:49.734872  DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135

 8112 12:40:49.734995  

 8113 12:40:49.735097  

 8114 12:40:49.735195  ==

 8115 12:40:49.738092  Dram Type= 6, Freq= 0, CH_0, rank 1

 8116 12:40:49.741593  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8117 12:40:49.745113  ==

 8118 12:40:49.745232  

 8119 12:40:49.745336  

 8120 12:40:49.745435  	TX Vref Scan disable

 8121 12:40:49.748000   == TX Byte 0 ==

 8122 12:40:49.751832  Update DQ  dly =992 (3 ,6, 32)  DQ  OEN =(3 ,3)

 8123 12:40:49.754662  Update DQM dly =992 (3 ,6, 32)  DQM OEN =(3 ,3)

 8124 12:40:49.758261   == TX Byte 1 ==

 8125 12:40:49.761409  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 8126 12:40:49.764410  Update DQM dly =980 (3 ,6, 20)  DQM OEN =(3 ,3)

 8127 12:40:49.764529  ==

 8128 12:40:49.768189  Dram Type= 6, Freq= 0, CH_0, rank 1

 8129 12:40:49.774546  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8130 12:40:49.774669  ==

 8131 12:40:49.788825  

 8132 12:40:49.791951  TX Vref early break, caculate TX vref

 8133 12:40:49.795425  TX Vref=16, minBit 1, minWin=23, winSum=389

 8134 12:40:49.798603  TX Vref=18, minBit 1, minWin=23, winSum=392

 8135 12:40:49.802272  TX Vref=20, minBit 1, minWin=24, winSum=406

 8136 12:40:49.805511  TX Vref=22, minBit 1, minWin=24, winSum=409

 8137 12:40:49.808708  TX Vref=24, minBit 0, minWin=25, winSum=420

 8138 12:40:49.815768  TX Vref=26, minBit 1, minWin=25, winSum=426

 8139 12:40:49.818869  TX Vref=28, minBit 3, minWin=24, winSum=424

 8140 12:40:49.822028  TX Vref=30, minBit 0, minWin=25, winSum=416

 8141 12:40:49.825283  TX Vref=32, minBit 0, minWin=24, winSum=408

 8142 12:40:49.828599  TX Vref=34, minBit 1, minWin=24, winSum=404

 8143 12:40:49.831749  TX Vref=36, minBit 0, minWin=24, winSum=395

 8144 12:40:49.838674  [TxChooseVref] Worse bit 1, Min win 25, Win sum 426, Final Vref 26

 8145 12:40:49.838811  

 8146 12:40:49.841842  Final TX Range 0 Vref 26

 8147 12:40:49.841959  

 8148 12:40:49.842064  ==

 8149 12:40:49.845308  Dram Type= 6, Freq= 0, CH_0, rank 1

 8150 12:40:49.848260  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8151 12:40:49.848373  ==

 8152 12:40:49.848471  

 8153 12:40:49.848576  

 8154 12:40:49.851994  	TX Vref Scan disable

 8155 12:40:49.858745  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps

 8156 12:40:49.858872   == TX Byte 0 ==

 8157 12:40:49.861771  u2DelayCellOfst[0]=13 cells (4 PI)

 8158 12:40:49.865300  u2DelayCellOfst[1]=16 cells (5 PI)

 8159 12:40:49.868235  u2DelayCellOfst[2]=10 cells (3 PI)

 8160 12:40:49.871800  u2DelayCellOfst[3]=10 cells (3 PI)

 8161 12:40:49.875546  u2DelayCellOfst[4]=6 cells (2 PI)

 8162 12:40:49.878736  u2DelayCellOfst[5]=0 cells (0 PI)

 8163 12:40:49.881965  u2DelayCellOfst[6]=13 cells (4 PI)

 8164 12:40:49.885138  u2DelayCellOfst[7]=16 cells (5 PI)

 8165 12:40:49.888415  Update DQ  dly =990 (3 ,6, 30)  DQ  OEN =(3 ,3)

 8166 12:40:49.891536  Update DQM dly =992 (3 ,6, 32)  DQM OEN =(3 ,3)

 8167 12:40:49.895265   == TX Byte 1 ==

 8168 12:40:49.898443  u2DelayCellOfst[8]=3 cells (1 PI)

 8169 12:40:49.901442  u2DelayCellOfst[9]=0 cells (0 PI)

 8170 12:40:49.901562  u2DelayCellOfst[10]=6 cells (2 PI)

 8171 12:40:49.905103  u2DelayCellOfst[11]=3 cells (1 PI)

 8172 12:40:49.908145  u2DelayCellOfst[12]=10 cells (3 PI)

 8173 12:40:49.911831  u2DelayCellOfst[13]=10 cells (3 PI)

 8174 12:40:49.915086  u2DelayCellOfst[14]=13 cells (4 PI)

 8175 12:40:49.918479  u2DelayCellOfst[15]=10 cells (3 PI)

 8176 12:40:49.921610  Update DQ  dly =978 (3 ,6, 18)  DQ  OEN =(3 ,3)

 8177 12:40:49.928133  Update DQM dly =980 (3 ,6, 20)  DQM OEN =(3 ,3)

 8178 12:40:49.928257  DramC Write-DBI on

 8179 12:40:49.928357  ==

 8180 12:40:49.931396  Dram Type= 6, Freq= 0, CH_0, rank 1

 8181 12:40:49.938536  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8182 12:40:49.938669  ==

 8183 12:40:49.938782  

 8184 12:40:49.938881  

 8185 12:40:49.938982  	TX Vref Scan disable

 8186 12:40:49.942151   == TX Byte 0 ==

 8187 12:40:49.945380  Update DQM dly =736 (2 ,6, 32)  DQM OEN =(3 ,3)

 8188 12:40:49.949023   == TX Byte 1 ==

 8189 12:40:49.952003  Update DQM dly =721 (2 ,6, 17)  DQM OEN =(3 ,3)

 8190 12:40:49.955532  DramC Write-DBI off

 8191 12:40:49.955651  

 8192 12:40:49.955757  [DATLAT]

 8193 12:40:49.955863  Freq=1600, CH0 RK1

 8194 12:40:49.955961  

 8195 12:40:49.958599  DATLAT Default: 0xf

 8196 12:40:49.962283  0, 0xFFFF, sum = 0

 8197 12:40:49.962406  1, 0xFFFF, sum = 0

 8198 12:40:49.965462  2, 0xFFFF, sum = 0

 8199 12:40:49.965586  3, 0xFFFF, sum = 0

 8200 12:40:49.968469  4, 0xFFFF, sum = 0

 8201 12:40:49.968588  5, 0xFFFF, sum = 0

 8202 12:40:49.971987  6, 0xFFFF, sum = 0

 8203 12:40:49.972103  7, 0xFFFF, sum = 0

 8204 12:40:49.975533  8, 0xFFFF, sum = 0

 8205 12:40:49.975650  9, 0xFFFF, sum = 0

 8206 12:40:49.978541  10, 0xFFFF, sum = 0

 8207 12:40:49.978665  11, 0xFFFF, sum = 0

 8208 12:40:49.982217  12, 0xFFFF, sum = 0

 8209 12:40:49.982337  13, 0xFFFF, sum = 0

 8210 12:40:49.985520  14, 0x0, sum = 1

 8211 12:40:49.985637  15, 0x0, sum = 2

 8212 12:40:49.988708  16, 0x0, sum = 3

 8213 12:40:49.988830  17, 0x0, sum = 4

 8214 12:40:49.991807  best_step = 15

 8215 12:40:49.991920  

 8216 12:40:49.992021  ==

 8217 12:40:49.995133  Dram Type= 6, Freq= 0, CH_0, rank 1

 8218 12:40:49.998800  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8219 12:40:49.998921  ==

 8220 12:40:50.001805  RX Vref Scan: 0

 8221 12:40:50.001917  

 8222 12:40:50.002020  RX Vref 0 -> 0, step: 1

 8223 12:40:50.002119  

 8224 12:40:50.005306  RX Delay 19 -> 252, step: 4

 8225 12:40:50.008616  iDelay=191, Bit 0, Center 134 (83 ~ 186) 104

 8226 12:40:50.015423  iDelay=191, Bit 1, Center 138 (91 ~ 186) 96

 8227 12:40:50.018953  iDelay=191, Bit 2, Center 130 (79 ~ 182) 104

 8228 12:40:50.021885  iDelay=191, Bit 3, Center 134 (83 ~ 186) 104

 8229 12:40:50.025653  iDelay=191, Bit 4, Center 136 (87 ~ 186) 100

 8230 12:40:50.028767  iDelay=191, Bit 5, Center 126 (75 ~ 178) 104

 8231 12:40:50.035196  iDelay=191, Bit 6, Center 140 (91 ~ 190) 100

 8232 12:40:50.039052  iDelay=191, Bit 7, Center 140 (91 ~ 190) 100

 8233 12:40:50.042313  iDelay=191, Bit 8, Center 120 (71 ~ 170) 100

 8234 12:40:50.045460  iDelay=191, Bit 9, Center 116 (67 ~ 166) 100

 8235 12:40:50.048788  iDelay=191, Bit 10, Center 128 (75 ~ 182) 108

 8236 12:40:50.055316  iDelay=191, Bit 11, Center 120 (71 ~ 170) 100

 8237 12:40:50.058918  iDelay=191, Bit 12, Center 134 (83 ~ 186) 104

 8238 12:40:50.062014  iDelay=191, Bit 13, Center 132 (83 ~ 182) 100

 8239 12:40:50.065104  iDelay=191, Bit 14, Center 134 (83 ~ 186) 104

 8240 12:40:50.068819  iDelay=191, Bit 15, Center 134 (87 ~ 182) 96

 8241 12:40:50.068937  ==

 8242 12:40:50.071942  Dram Type= 6, Freq= 0, CH_0, rank 1

 8243 12:40:50.078659  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8244 12:40:50.078792  ==

 8245 12:40:50.078898  DQS Delay:

 8246 12:40:50.082108  DQS0 = 0, DQS1 = 0

 8247 12:40:50.082221  DQM Delay:

 8248 12:40:50.085106  DQM0 = 134, DQM1 = 127

 8249 12:40:50.085219  DQ Delay:

 8250 12:40:50.088516  DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134

 8251 12:40:50.091875  DQ4 =136, DQ5 =126, DQ6 =140, DQ7 =140

 8252 12:40:50.095631  DQ8 =120, DQ9 =116, DQ10 =128, DQ11 =120

 8253 12:40:50.098955  DQ12 =134, DQ13 =132, DQ14 =134, DQ15 =134

 8254 12:40:50.099085  

 8255 12:40:50.099214  

 8256 12:40:50.099340  

 8257 12:40:50.102267  [DramC_TX_OE_Calibration] TA2

 8258 12:40:50.105267  Original DQ_B0 (3 6) =30, OEN = 27

 8259 12:40:50.108381  Original DQ_B1 (3 6) =30, OEN = 27

 8260 12:40:50.111850  24, 0x0, End_B0=24 End_B1=24

 8261 12:40:50.115536  25, 0x0, End_B0=25 End_B1=25

 8262 12:40:50.115655  26, 0x0, End_B0=26 End_B1=26

 8263 12:40:50.119078  27, 0x0, End_B0=27 End_B1=27

 8264 12:40:50.121840  28, 0x0, End_B0=28 End_B1=28

 8265 12:40:50.125120  29, 0x0, End_B0=29 End_B1=29

 8266 12:40:50.125239  30, 0x0, End_B0=30 End_B1=30

 8267 12:40:50.128653  31, 0x4141, End_B0=30 End_B1=30

 8268 12:40:50.131667  Byte0 end_step=30  best_step=27

 8269 12:40:50.135522  Byte1 end_step=30  best_step=27

 8270 12:40:50.138666  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8271 12:40:50.141915  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8272 12:40:50.142004  

 8273 12:40:50.142093  

 8274 12:40:50.148770  [DQSOSCAuto] RK1, (LSB)MR18= 0x2009, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps

 8275 12:40:50.151963  CH0 RK1: MR19=303, MR18=2009

 8276 12:40:50.158359  CH0_RK1: MR19=0x303, MR18=0x2009, DQSOSC=393, MR23=63, INC=23, DEC=15

 8277 12:40:50.161461  [RxdqsGatingPostProcess] freq 1600

 8278 12:40:50.165157  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 8279 12:40:50.168363  best DQS0 dly(2T, 0.5T) = (1, 1)

 8280 12:40:50.172091  best DQS1 dly(2T, 0.5T) = (1, 1)

 8281 12:40:50.175386  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8282 12:40:50.178519  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8283 12:40:50.182123  best DQS0 dly(2T, 0.5T) = (1, 1)

 8284 12:40:50.185227  best DQS1 dly(2T, 0.5T) = (1, 1)

 8285 12:40:50.188321  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8286 12:40:50.191434  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8287 12:40:50.195069  Pre-setting of DQS Precalculation

 8288 12:40:50.198098  [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15

 8289 12:40:50.198199  ==

 8290 12:40:50.201388  Dram Type= 6, Freq= 0, CH_1, rank 0

 8291 12:40:50.205289  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8292 12:40:50.208522  ==

 8293 12:40:50.211774  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 8294 12:40:50.214864  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1

 8295 12:40:50.221524  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1

 8296 12:40:50.227853  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 8297 12:40:50.235520  [CA 0] Center 41 (12~71) winsize 60

 8298 12:40:50.238362  [CA 1] Center 42 (13~71) winsize 59

 8299 12:40:50.241948  [CA 2] Center 38 (9~68) winsize 60

 8300 12:40:50.245153  [CA 3] Center 37 (8~66) winsize 59

 8301 12:40:50.248413  [CA 4] Center 38 (9~67) winsize 59

 8302 12:40:50.251597  [CA 5] Center 36 (7~66) winsize 60

 8303 12:40:50.251716  

 8304 12:40:50.255468  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 8305 12:40:50.255573  

 8306 12:40:50.258640  [CATrainingPosCal] consider 1 rank data

 8307 12:40:50.261953  u2DelayCellTimex100 = 290/100 ps

 8308 12:40:50.265087  CA0 delay=41 (12~71),Diff = 5 PI (16 cell)

 8309 12:40:50.271802  CA1 delay=42 (13~71),Diff = 6 PI (20 cell)

 8310 12:40:50.274962  CA2 delay=38 (9~68),Diff = 2 PI (6 cell)

 8311 12:40:50.278298  CA3 delay=37 (8~66),Diff = 1 PI (3 cell)

 8312 12:40:50.281443  CA4 delay=38 (9~67),Diff = 2 PI (6 cell)

 8313 12:40:50.285126  CA5 delay=36 (7~66),Diff = 0 PI (0 cell)

 8314 12:40:50.285283  

 8315 12:40:50.288308  CA PerBit enable=1, Macro0, CA PI delay=36

 8316 12:40:50.288400  

 8317 12:40:50.291986  [CBTSetCACLKResult] CA Dly = 36

 8318 12:40:50.295005  CS Dly: 11 (0~42)

 8319 12:40:50.298597  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0

 8320 12:40:50.301454  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0

 8321 12:40:50.301558  ==

 8322 12:40:50.305502  Dram Type= 6, Freq= 0, CH_1, rank 1

 8323 12:40:50.308633  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8324 12:40:50.308720  ==

 8325 12:40:50.315184  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 8326 12:40:50.318254  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1

 8327 12:40:50.325387  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1

 8328 12:40:50.328126  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 8329 12:40:50.338084  [CA 0] Center 42 (12~72) winsize 61

 8330 12:40:50.341942  [CA 1] Center 41 (12~71) winsize 60

 8331 12:40:50.345115  [CA 2] Center 38 (9~68) winsize 60

 8332 12:40:50.348845  [CA 3] Center 38 (8~68) winsize 61

 8333 12:40:50.351628  [CA 4] Center 38 (8~68) winsize 61

 8334 12:40:50.354921  [CA 5] Center 37 (8~67) winsize 60

 8335 12:40:50.355009  

 8336 12:40:50.358741  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 8337 12:40:50.358829  

 8338 12:40:50.361935  [CATrainingPosCal] consider 2 rank data

 8339 12:40:50.365180  u2DelayCellTimex100 = 290/100 ps

 8340 12:40:50.368389  CA0 delay=41 (12~71),Diff = 4 PI (13 cell)

 8341 12:40:50.375254  CA1 delay=42 (13~71),Diff = 5 PI (16 cell)

 8342 12:40:50.378454  CA2 delay=38 (9~68),Diff = 1 PI (3 cell)

 8343 12:40:50.381787  CA3 delay=37 (8~66),Diff = 0 PI (0 cell)

 8344 12:40:50.384874  CA4 delay=38 (9~67),Diff = 1 PI (3 cell)

 8345 12:40:50.388716  CA5 delay=37 (8~66),Diff = 0 PI (0 cell)

 8346 12:40:50.388809  

 8347 12:40:50.391845  CA PerBit enable=1, Macro0, CA PI delay=37

 8348 12:40:50.391930  

 8349 12:40:50.394969  [CBTSetCACLKResult] CA Dly = 37

 8350 12:40:50.398132  CS Dly: 12 (0~45)

 8351 12:40:50.401914  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0

 8352 12:40:50.404959  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0

 8353 12:40:50.405050  

 8354 12:40:50.408346  ----->DramcWriteLeveling(PI) begin...

 8355 12:40:50.408432  ==

 8356 12:40:50.411686  Dram Type= 6, Freq= 0, CH_1, rank 0

 8357 12:40:50.414799  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8358 12:40:50.418090  ==

 8359 12:40:50.418173  Write leveling (Byte 0): 25 => 25

 8360 12:40:50.421386  Write leveling (Byte 1): 27 => 27

 8361 12:40:50.425067  DramcWriteLeveling(PI) end<-----

 8362 12:40:50.425176  

 8363 12:40:50.425272  ==

 8364 12:40:50.428340  Dram Type= 6, Freq= 0, CH_1, rank 0

 8365 12:40:50.435045  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8366 12:40:50.435160  ==

 8367 12:40:50.435257  [Gating] SW mode calibration

 8368 12:40:50.445070  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8369 12:40:50.448397  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8370 12:40:50.454721   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8371 12:40:50.458249   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8372 12:40:50.461284   1  4  8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)

 8373 12:40:50.464905   1  4 12 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)

 8374 12:40:50.471530   1  4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8375 12:40:50.474612   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8376 12:40:50.478406   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8377 12:40:50.484629   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8378 12:40:50.488402   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8379 12:40:50.491659   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8380 12:40:50.498491   1  5  8 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)

 8381 12:40:50.501449   1  5 12 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)

 8382 12:40:50.504595   1  5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8383 12:40:50.511433   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8384 12:40:50.514947   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8385 12:40:50.518263   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8386 12:40:50.524797   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8387 12:40:50.528504   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8388 12:40:50.531742   1  6  8 | B1->B0 | 2525 4242 | 0 0 | (1 1) (0 0)

 8389 12:40:50.538275   1  6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8390 12:40:50.541399   1  6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8391 12:40:50.544798   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8392 12:40:50.551715   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8393 12:40:50.554993   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8394 12:40:50.557996   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8395 12:40:50.561701   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8396 12:40:50.567773   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8397 12:40:50.571133   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8398 12:40:50.574401   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 8399 12:40:50.581187   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8400 12:40:50.584344   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8401 12:40:50.588087   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8402 12:40:50.594491   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8403 12:40:50.597536   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8404 12:40:50.601174   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8405 12:40:50.607969   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8406 12:40:50.611192   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8407 12:40:50.614321   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8408 12:40:50.621017   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8409 12:40:50.624298   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8410 12:40:50.627551   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8411 12:40:50.634460   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8412 12:40:50.637740   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8413 12:40:50.640930   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8414 12:40:50.647945   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8415 12:40:50.648083  Total UI for P1: 0, mck2ui 16

 8416 12:40:50.654183  best dqsien dly found for B0: ( 1,  9, 10)

 8417 12:40:50.654313  Total UI for P1: 0, mck2ui 16

 8418 12:40:50.661083  best dqsien dly found for B1: ( 1,  9, 10)

 8419 12:40:50.664286  best DQS0 dly(MCK, UI, PI) = (1, 9, 10)

 8420 12:40:50.667502  best DQS1 dly(MCK, UI, PI) = (1, 9, 10)

 8421 12:40:50.667624  

 8422 12:40:50.671217  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)

 8423 12:40:50.674200  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)

 8424 12:40:50.677568  [Gating] SW calibration Done

 8425 12:40:50.677683  ==

 8426 12:40:50.681241  Dram Type= 6, Freq= 0, CH_1, rank 0

 8427 12:40:50.684284  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8428 12:40:50.684403  ==

 8429 12:40:50.687458  RX Vref Scan: 0

 8430 12:40:50.687574  

 8431 12:40:50.687678  RX Vref 0 -> 0, step: 1

 8432 12:40:50.687786  

 8433 12:40:50.691282  RX Delay 0 -> 252, step: 8

 8434 12:40:50.694432  iDelay=200, Bit 0, Center 143 (96 ~ 191) 96

 8435 12:40:50.700798  iDelay=200, Bit 1, Center 131 (80 ~ 183) 104

 8436 12:40:50.704584  iDelay=200, Bit 2, Center 123 (72 ~ 175) 104

 8437 12:40:50.707675  iDelay=200, Bit 3, Center 135 (80 ~ 191) 112

 8438 12:40:50.710704  iDelay=200, Bit 4, Center 131 (80 ~ 183) 104

 8439 12:40:50.713957  iDelay=200, Bit 5, Center 147 (96 ~ 199) 104

 8440 12:40:50.717339  iDelay=200, Bit 6, Center 147 (96 ~ 199) 104

 8441 12:40:50.724535  iDelay=200, Bit 7, Center 135 (80 ~ 191) 112

 8442 12:40:50.727628  iDelay=200, Bit 8, Center 119 (72 ~ 167) 96

 8443 12:40:50.730871  iDelay=200, Bit 9, Center 123 (72 ~ 175) 104

 8444 12:40:50.734073  iDelay=200, Bit 10, Center 131 (80 ~ 183) 104

 8445 12:40:50.737870  iDelay=200, Bit 11, Center 127 (80 ~ 175) 96

 8446 12:40:50.744250  iDelay=200, Bit 12, Center 139 (88 ~ 191) 104

 8447 12:40:50.747431  iDelay=200, Bit 13, Center 143 (88 ~ 199) 112

 8448 12:40:50.750704  iDelay=200, Bit 14, Center 139 (88 ~ 191) 104

 8449 12:40:50.753943  iDelay=200, Bit 15, Center 139 (88 ~ 191) 104

 8450 12:40:50.754052  ==

 8451 12:40:50.757672  Dram Type= 6, Freq= 0, CH_1, rank 0

 8452 12:40:50.764391  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8453 12:40:50.764504  ==

 8454 12:40:50.764598  DQS Delay:

 8455 12:40:50.767311  DQS0 = 0, DQS1 = 0

 8456 12:40:50.767414  DQM Delay:

 8457 12:40:50.767508  DQM0 = 136, DQM1 = 132

 8458 12:40:50.770735  DQ Delay:

 8459 12:40:50.773946  DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135

 8460 12:40:50.777165  DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135

 8461 12:40:50.780436  DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127

 8462 12:40:50.783900  DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139

 8463 12:40:50.783985  

 8464 12:40:50.784052  

 8465 12:40:50.784111  ==

 8466 12:40:50.787412  Dram Type= 6, Freq= 0, CH_1, rank 0

 8467 12:40:50.793937  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8468 12:40:50.794023  ==

 8469 12:40:50.794091  

 8470 12:40:50.794151  

 8471 12:40:50.794210  	TX Vref Scan disable

 8472 12:40:50.797069   == TX Byte 0 ==

 8473 12:40:50.800302  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 8474 12:40:50.804141  Update DQM dly =980 (3 ,6, 20)  DQM OEN =(3 ,3)

 8475 12:40:50.807180   == TX Byte 1 ==

 8476 12:40:50.810911  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 8477 12:40:50.813917  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8478 12:40:50.816994  ==

 8479 12:40:50.820285  Dram Type= 6, Freq= 0, CH_1, rank 0

 8480 12:40:50.823468  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8481 12:40:50.823555  ==

 8482 12:40:50.835713  

 8483 12:40:50.838883  TX Vref early break, caculate TX vref

 8484 12:40:50.842577  TX Vref=16, minBit 0, minWin=22, winSum=371

 8485 12:40:50.845651  TX Vref=18, minBit 0, minWin=23, winSum=379

 8486 12:40:50.848884  TX Vref=20, minBit 1, minWin=23, winSum=391

 8487 12:40:50.852406  TX Vref=22, minBit 0, minWin=24, winSum=407

 8488 12:40:50.855600  TX Vref=24, minBit 0, minWin=25, winSum=411

 8489 12:40:50.862718  TX Vref=26, minBit 0, minWin=25, winSum=420

 8490 12:40:50.865942  TX Vref=28, minBit 0, minWin=25, winSum=427

 8491 12:40:50.869000  TX Vref=30, minBit 6, minWin=24, winSum=421

 8492 12:40:50.872507  TX Vref=32, minBit 6, minWin=24, winSum=412

 8493 12:40:50.875810  TX Vref=34, minBit 0, minWin=24, winSum=402

 8494 12:40:50.882031  [TxChooseVref] Worse bit 0, Min win 25, Win sum 427, Final Vref 28

 8495 12:40:50.882147  

 8496 12:40:50.885536  Final TX Range 0 Vref 28

 8497 12:40:50.885655  

 8498 12:40:50.885757  ==

 8499 12:40:50.889064  Dram Type= 6, Freq= 0, CH_1, rank 0

 8500 12:40:50.892232  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8501 12:40:50.892324  ==

 8502 12:40:50.892391  

 8503 12:40:50.892458  

 8504 12:40:50.896046  	TX Vref Scan disable

 8505 12:40:50.901985  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps

 8506 12:40:50.902090   == TX Byte 0 ==

 8507 12:40:50.905879  u2DelayCellOfst[0]=20 cells (6 PI)

 8508 12:40:50.908822  u2DelayCellOfst[1]=13 cells (4 PI)

 8509 12:40:50.911784  u2DelayCellOfst[2]=0 cells (0 PI)

 8510 12:40:50.915633  u2DelayCellOfst[3]=6 cells (2 PI)

 8511 12:40:50.918776  u2DelayCellOfst[4]=10 cells (3 PI)

 8512 12:40:50.922060  u2DelayCellOfst[5]=20 cells (6 PI)

 8513 12:40:50.925299  u2DelayCellOfst[6]=23 cells (7 PI)

 8514 12:40:50.925386  u2DelayCellOfst[7]=6 cells (2 PI)

 8515 12:40:50.932308  Update DQ  dly =977 (3 ,6, 17)  DQ  OEN =(3 ,3)

 8516 12:40:50.935333  Update DQM dly =980 (3 ,6, 20)  DQM OEN =(3 ,3)

 8517 12:40:50.935473   == TX Byte 1 ==

 8518 12:40:50.939012  u2DelayCellOfst[8]=0 cells (0 PI)

 8519 12:40:50.942250  u2DelayCellOfst[9]=3 cells (1 PI)

 8520 12:40:50.945326  u2DelayCellOfst[10]=13 cells (4 PI)

 8521 12:40:50.949052  u2DelayCellOfst[11]=3 cells (1 PI)

 8522 12:40:50.952308  u2DelayCellOfst[12]=13 cells (4 PI)

 8523 12:40:50.955486  u2DelayCellOfst[13]=16 cells (5 PI)

 8524 12:40:50.958664  u2DelayCellOfst[14]=20 cells (6 PI)

 8525 12:40:50.961835  u2DelayCellOfst[15]=20 cells (6 PI)

 8526 12:40:50.965632  Update DQ  dly =979 (3 ,6, 19)  DQ  OEN =(3 ,3)

 8527 12:40:50.972049  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8528 12:40:50.972138  DramC Write-DBI on

 8529 12:40:50.972214  ==

 8530 12:40:50.975270  Dram Type= 6, Freq= 0, CH_1, rank 0

 8531 12:40:50.978972  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8532 12:40:50.979061  ==

 8533 12:40:50.979128  

 8534 12:40:50.981994  

 8535 12:40:50.982083  	TX Vref Scan disable

 8536 12:40:50.985474   == TX Byte 0 ==

 8537 12:40:50.989156  Update DQM dly =722 (2 ,6, 18)  DQM OEN =(3 ,3)

 8538 12:40:50.992359   == TX Byte 1 ==

 8539 12:40:50.995383  Update DQM dly =723 (2 ,6, 19)  DQM OEN =(3 ,3)

 8540 12:40:50.995499  DramC Write-DBI off

 8541 12:40:50.995568  

 8542 12:40:50.998643  [DATLAT]

 8543 12:40:50.998741  Freq=1600, CH1 RK0

 8544 12:40:50.998849  

 8545 12:40:51.002320  DATLAT Default: 0xf

 8546 12:40:51.002439  0, 0xFFFF, sum = 0

 8547 12:40:51.005270  1, 0xFFFF, sum = 0

 8548 12:40:51.005357  2, 0xFFFF, sum = 0

 8549 12:40:51.008672  3, 0xFFFF, sum = 0

 8550 12:40:51.008758  4, 0xFFFF, sum = 0

 8551 12:40:51.012207  5, 0xFFFF, sum = 0

 8552 12:40:51.012295  6, 0xFFFF, sum = 0

 8553 12:40:51.015258  7, 0xFFFF, sum = 0

 8554 12:40:51.015348  8, 0xFFFF, sum = 0

 8555 12:40:51.019049  9, 0xFFFF, sum = 0

 8556 12:40:51.022159  10, 0xFFFF, sum = 0

 8557 12:40:51.022253  11, 0xFFFF, sum = 0

 8558 12:40:51.025702  12, 0xFFFF, sum = 0

 8559 12:40:51.025789  13, 0xFFFF, sum = 0

 8560 12:40:51.028800  14, 0x0, sum = 1

 8561 12:40:51.028896  15, 0x0, sum = 2

 8562 12:40:51.032117  16, 0x0, sum = 3

 8563 12:40:51.032193  17, 0x0, sum = 4

 8564 12:40:51.032256  best_step = 15

 8565 12:40:51.032316  

 8566 12:40:51.035281  ==

 8567 12:40:51.039101  Dram Type= 6, Freq= 0, CH_1, rank 0

 8568 12:40:51.042083  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8569 12:40:51.042202  ==

 8570 12:40:51.042311  RX Vref Scan: 1

 8571 12:40:51.042416  

 8572 12:40:51.045205  Set Vref Range= 24 -> 127

 8573 12:40:51.045310  

 8574 12:40:51.048753  RX Vref 24 -> 127, step: 1

 8575 12:40:51.048871  

 8576 12:40:51.051941  RX Delay 27 -> 252, step: 4

 8577 12:40:51.052026  

 8578 12:40:51.055152  Set Vref, RX VrefLevel [Byte0]: 24

 8579 12:40:51.059042                           [Byte1]: 24

 8580 12:40:51.059146  

 8581 12:40:51.062300  Set Vref, RX VrefLevel [Byte0]: 25

 8582 12:40:51.065533                           [Byte1]: 25

 8583 12:40:51.065626  

 8584 12:40:51.068752  Set Vref, RX VrefLevel [Byte0]: 26

 8585 12:40:51.071976                           [Byte1]: 26

 8586 12:40:51.075716  

 8587 12:40:51.075825  Set Vref, RX VrefLevel [Byte0]: 27

 8588 12:40:51.078372                           [Byte1]: 27

 8589 12:40:51.082899  

 8590 12:40:51.082988  Set Vref, RX VrefLevel [Byte0]: 28

 8591 12:40:51.085986                           [Byte1]: 28

 8592 12:40:51.090319  

 8593 12:40:51.090432  Set Vref, RX VrefLevel [Byte0]: 29

 8594 12:40:51.094110                           [Byte1]: 29

 8595 12:40:51.098003  

 8596 12:40:51.098122  Set Vref, RX VrefLevel [Byte0]: 30

 8597 12:40:51.101066                           [Byte1]: 30

 8598 12:40:51.105382  

 8599 12:40:51.105477  Set Vref, RX VrefLevel [Byte0]: 31

 8600 12:40:51.108522                           [Byte1]: 31

 8601 12:40:51.112850  

 8602 12:40:51.112940  Set Vref, RX VrefLevel [Byte0]: 32

 8603 12:40:51.116063                           [Byte1]: 32

 8604 12:40:51.120663  

 8605 12:40:51.120773  Set Vref, RX VrefLevel [Byte0]: 33

 8606 12:40:51.123842                           [Byte1]: 33

 8607 12:40:51.127876  

 8608 12:40:51.128020  Set Vref, RX VrefLevel [Byte0]: 34

 8609 12:40:51.131546                           [Byte1]: 34

 8610 12:40:51.135451  

 8611 12:40:51.135622  Set Vref, RX VrefLevel [Byte0]: 35

 8612 12:40:51.138623                           [Byte1]: 35

 8613 12:40:51.143116  

 8614 12:40:51.143259  Set Vref, RX VrefLevel [Byte0]: 36

 8615 12:40:51.146228                           [Byte1]: 36

 8616 12:40:51.150373  

 8617 12:40:51.150526  Set Vref, RX VrefLevel [Byte0]: 37

 8618 12:40:51.153629                           [Byte1]: 37

 8619 12:40:51.158429  

 8620 12:40:51.158557  Set Vref, RX VrefLevel [Byte0]: 38

 8621 12:40:51.161662                           [Byte1]: 38

 8622 12:40:51.165629  

 8623 12:40:51.165765  Set Vref, RX VrefLevel [Byte0]: 39

 8624 12:40:51.168918                           [Byte1]: 39

 8625 12:40:51.173247  

 8626 12:40:51.173358  Set Vref, RX VrefLevel [Byte0]: 40

 8627 12:40:51.176460                           [Byte1]: 40

 8628 12:40:51.180440  

 8629 12:40:51.180543  Set Vref, RX VrefLevel [Byte0]: 41

 8630 12:40:51.187368                           [Byte1]: 41

 8631 12:40:51.187451  

 8632 12:40:51.190517  Set Vref, RX VrefLevel [Byte0]: 42

 8633 12:40:51.193833                           [Byte1]: 42

 8634 12:40:51.193910  

 8635 12:40:51.196909  Set Vref, RX VrefLevel [Byte0]: 43

 8636 12:40:51.200707                           [Byte1]: 43

 8637 12:40:51.200844  

 8638 12:40:51.203645  Set Vref, RX VrefLevel [Byte0]: 44

 8639 12:40:51.206855                           [Byte1]: 44

 8640 12:40:51.210873  

 8641 12:40:51.210971  Set Vref, RX VrefLevel [Byte0]: 45

 8642 12:40:51.213955                           [Byte1]: 45

 8643 12:40:51.218465  

 8644 12:40:51.218547  Set Vref, RX VrefLevel [Byte0]: 46

 8645 12:40:51.221679                           [Byte1]: 46

 8646 12:40:51.226194  

 8647 12:40:51.226283  Set Vref, RX VrefLevel [Byte0]: 47

 8648 12:40:51.229232                           [Byte1]: 47

 8649 12:40:51.233349  

 8650 12:40:51.233455  Set Vref, RX VrefLevel [Byte0]: 48

 8651 12:40:51.236477                           [Byte1]: 48

 8652 12:40:51.240640  

 8653 12:40:51.240763  Set Vref, RX VrefLevel [Byte0]: 49

 8654 12:40:51.244453                           [Byte1]: 49

 8655 12:40:51.248438  

 8656 12:40:51.248556  Set Vref, RX VrefLevel [Byte0]: 50

 8657 12:40:51.252113                           [Byte1]: 50

 8658 12:40:51.255800  

 8659 12:40:51.255887  Set Vref, RX VrefLevel [Byte0]: 51

 8660 12:40:51.259520                           [Byte1]: 51

 8661 12:40:51.263633  

 8662 12:40:51.263722  Set Vref, RX VrefLevel [Byte0]: 52

 8663 12:40:51.266857                           [Byte1]: 52

 8664 12:40:51.271269  

 8665 12:40:51.271374  Set Vref, RX VrefLevel [Byte0]: 53

 8666 12:40:51.274499                           [Byte1]: 53

 8667 12:40:51.278392  

 8668 12:40:51.278471  Set Vref, RX VrefLevel [Byte0]: 54

 8669 12:40:51.282205                           [Byte1]: 54

 8670 12:40:51.286282  

 8671 12:40:51.286359  Set Vref, RX VrefLevel [Byte0]: 55

 8672 12:40:51.289470                           [Byte1]: 55

 8673 12:40:51.293885  

 8674 12:40:51.293961  Set Vref, RX VrefLevel [Byte0]: 56

 8675 12:40:51.297152                           [Byte1]: 56

 8676 12:40:51.301014  

 8677 12:40:51.301090  Set Vref, RX VrefLevel [Byte0]: 57

 8678 12:40:51.304725                           [Byte1]: 57

 8679 12:40:51.308915  

 8680 12:40:51.308999  Set Vref, RX VrefLevel [Byte0]: 58

 8681 12:40:51.311951                           [Byte1]: 58

 8682 12:40:51.316495  

 8683 12:40:51.316602  Set Vref, RX VrefLevel [Byte0]: 59

 8684 12:40:51.319763                           [Byte1]: 59

 8685 12:40:51.323733  

 8686 12:40:51.323839  Set Vref, RX VrefLevel [Byte0]: 60

 8687 12:40:51.327448                           [Byte1]: 60

 8688 12:40:51.331154  

 8689 12:40:51.331277  Set Vref, RX VrefLevel [Byte0]: 61

 8690 12:40:51.334300                           [Byte1]: 61

 8691 12:40:51.339038  

 8692 12:40:51.339142  Set Vref, RX VrefLevel [Byte0]: 62

 8693 12:40:51.342383                           [Byte1]: 62

 8694 12:40:51.346490  

 8695 12:40:51.346573  Set Vref, RX VrefLevel [Byte0]: 63

 8696 12:40:51.349612                           [Byte1]: 63

 8697 12:40:51.354109  

 8698 12:40:51.354182  Set Vref, RX VrefLevel [Byte0]: 64

 8699 12:40:51.357078                           [Byte1]: 64

 8700 12:40:51.361539  

 8701 12:40:51.361614  Set Vref, RX VrefLevel [Byte0]: 65

 8702 12:40:51.364700                           [Byte1]: 65

 8703 12:40:51.368748  

 8704 12:40:51.368872  Set Vref, RX VrefLevel [Byte0]: 66

 8705 12:40:51.372045                           [Byte1]: 66

 8706 12:40:51.376725  

 8707 12:40:51.376851  Set Vref, RX VrefLevel [Byte0]: 67

 8708 12:40:51.379874                           [Byte1]: 67

 8709 12:40:51.384296  

 8710 12:40:51.384372  Set Vref, RX VrefLevel [Byte0]: 68

 8711 12:40:51.387519                           [Byte1]: 68

 8712 12:40:51.391499  

 8713 12:40:51.391577  Set Vref, RX VrefLevel [Byte0]: 69

 8714 12:40:51.394696                           [Byte1]: 69

 8715 12:40:51.399035  

 8716 12:40:51.399115  Set Vref, RX VrefLevel [Byte0]: 70

 8717 12:40:51.402308                           [Byte1]: 70

 8718 12:40:51.406748  

 8719 12:40:51.406832  Set Vref, RX VrefLevel [Byte0]: 71

 8720 12:40:51.409899                           [Byte1]: 71

 8721 12:40:51.414173  

 8722 12:40:51.414267  Set Vref, RX VrefLevel [Byte0]: 72

 8723 12:40:51.417248                           [Byte1]: 72

 8724 12:40:51.421526  

 8725 12:40:51.421609  Set Vref, RX VrefLevel [Byte0]: 73

 8726 12:40:51.425131                           [Byte1]: 73

 8727 12:40:51.429427  

 8728 12:40:51.429515  Set Vref, RX VrefLevel [Byte0]: 74

 8729 12:40:51.432708                           [Byte1]: 74

 8730 12:40:51.436484  

 8731 12:40:51.436567  Set Vref, RX VrefLevel [Byte0]: 75

 8732 12:40:51.440251                           [Byte1]: 75

 8733 12:40:51.444392  

 8734 12:40:51.444478  Set Vref, RX VrefLevel [Byte0]: 76

 8735 12:40:51.447419                           [Byte1]: 76

 8736 12:40:51.451799  

 8737 12:40:51.451904  Set Vref, RX VrefLevel [Byte0]: 77

 8738 12:40:51.455263                           [Byte1]: 77

 8739 12:40:51.459531  

 8740 12:40:51.459634  Final RX Vref Byte 0 = 58 to rank0

 8741 12:40:51.464339  Final RX Vref Byte 1 = 60 to rank0

 8742 12:40:51.465956  Final RX Vref Byte 0 = 58 to rank1

 8743 12:40:51.469208  Final RX Vref Byte 1 = 60 to rank1==

 8744 12:40:51.472914  Dram Type= 6, Freq= 0, CH_1, rank 0

 8745 12:40:51.479090  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8746 12:40:51.479195  ==

 8747 12:40:51.479264  DQS Delay:

 8748 12:40:51.479335  DQS0 = 0, DQS1 = 0

 8749 12:40:51.482339  DQM Delay:

 8750 12:40:51.482413  DQM0 = 134, DQM1 = 130

 8751 12:40:51.486053  DQ Delay:

 8752 12:40:51.489234  DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130

 8753 12:40:51.492532  DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =132

 8754 12:40:51.495836  DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =122

 8755 12:40:51.499155  DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140

 8756 12:40:51.499267  

 8757 12:40:51.499360  

 8758 12:40:51.499457  

 8759 12:40:51.502710  [DramC_TX_OE_Calibration] TA2

 8760 12:40:51.505924  Original DQ_B0 (3 6) =30, OEN = 27

 8761 12:40:51.509055  Original DQ_B1 (3 6) =30, OEN = 27

 8762 12:40:51.512420  24, 0x0, End_B0=24 End_B1=24

 8763 12:40:51.512535  25, 0x0, End_B0=25 End_B1=25

 8764 12:40:51.515880  26, 0x0, End_B0=26 End_B1=26

 8765 12:40:51.518901  27, 0x0, End_B0=27 End_B1=27

 8766 12:40:51.522545  28, 0x0, End_B0=28 End_B1=28

 8767 12:40:51.525770  29, 0x0, End_B0=29 End_B1=29

 8768 12:40:51.525887  30, 0x0, End_B0=30 End_B1=30

 8769 12:40:51.529283  31, 0x4141, End_B0=30 End_B1=30

 8770 12:40:51.532375  Byte0 end_step=30  best_step=27

 8771 12:40:51.535475  Byte1 end_step=30  best_step=27

 8772 12:40:51.538702  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8773 12:40:51.542669  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8774 12:40:51.542756  

 8775 12:40:51.542847  

 8776 12:40:51.548985  [DQSOSCAuto] RK0, (LSB)MR18= 0x1724, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps

 8777 12:40:51.552552  CH1 RK0: MR19=303, MR18=1724

 8778 12:40:51.559244  CH1_RK0: MR19=0x303, MR18=0x1724, DQSOSC=391, MR23=63, INC=24, DEC=16

 8779 12:40:51.559335  

 8780 12:40:51.562493  ----->DramcWriteLeveling(PI) begin...

 8781 12:40:51.562586  ==

 8782 12:40:51.565869  Dram Type= 6, Freq= 0, CH_1, rank 1

 8783 12:40:51.568975  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8784 12:40:51.569080  ==

 8785 12:40:51.572083  Write leveling (Byte 0): 25 => 25

 8786 12:40:51.575793  Write leveling (Byte 1): 28 => 28

 8787 12:40:51.578884  DramcWriteLeveling(PI) end<-----

 8788 12:40:51.579000  

 8789 12:40:51.579092  ==

 8790 12:40:51.582110  Dram Type= 6, Freq= 0, CH_1, rank 1

 8791 12:40:51.585443  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8792 12:40:51.585526  ==

 8793 12:40:51.589237  [Gating] SW mode calibration

 8794 12:40:51.595691  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8795 12:40:51.602226  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8796 12:40:51.605849   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8797 12:40:51.608985   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8798 12:40:51.615981   1  4  8 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)

 8799 12:40:51.619129   1  4 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)

 8800 12:40:51.622352   1  4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8801 12:40:51.629176   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8802 12:40:51.632286   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8803 12:40:51.635922   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8804 12:40:51.642701   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8805 12:40:51.645902   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)

 8806 12:40:51.649117   1  5  8 | B1->B0 | 3333 3434 | 0 1 | (0 1) (1 1)

 8807 12:40:51.655689   1  5 12 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 0)

 8808 12:40:51.658749   1  5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8809 12:40:51.662515   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8810 12:40:51.668879   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8811 12:40:51.672198   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8812 12:40:51.675621   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8813 12:40:51.682305   1  6  4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 8814 12:40:51.685413   1  6  8 | B1->B0 | 3434 2525 | 0 0 | (0 0) (1 1)

 8815 12:40:51.688636   1  6 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)

 8816 12:40:51.692418   1  6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8817 12:40:51.698807   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8818 12:40:51.702035   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8819 12:40:51.705413   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8820 12:40:51.712369   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8821 12:40:51.715718   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8822 12:40:51.718922   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 8823 12:40:51.725435   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 8824 12:40:51.728692   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8825 12:40:51.731798   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8826 12:40:51.738846   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8827 12:40:51.741740   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8828 12:40:51.745168   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8829 12:40:51.752141   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8830 12:40:51.755469   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8831 12:40:51.758539   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8832 12:40:51.765522   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8833 12:40:51.768691   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8834 12:40:51.771719   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8835 12:40:51.778366   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8836 12:40:51.781883   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8837 12:40:51.784898   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 8838 12:40:51.791718   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 8839 12:40:51.794986   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 8840 12:40:51.798080  Total UI for P1: 0, mck2ui 16

 8841 12:40:51.801879  best dqsien dly found for B1: ( 1,  9,  6)

 8842 12:40:51.805112   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8843 12:40:51.808226  Total UI for P1: 0, mck2ui 16

 8844 12:40:51.811683  best dqsien dly found for B0: ( 1,  9, 12)

 8845 12:40:51.814659  best DQS0 dly(MCK, UI, PI) = (1, 9, 12)

 8846 12:40:51.817844  best DQS1 dly(MCK, UI, PI) = (1, 9, 6)

 8847 12:40:51.817935  

 8848 12:40:51.824896  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)

 8849 12:40:51.828143  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)

 8850 12:40:51.828255  [Gating] SW calibration Done

 8851 12:40:51.831407  ==

 8852 12:40:51.834607  Dram Type= 6, Freq= 0, CH_1, rank 1

 8853 12:40:51.837699  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8854 12:40:51.837841  ==

 8855 12:40:51.837952  RX Vref Scan: 0

 8856 12:40:51.838051  

 8857 12:40:51.841454  RX Vref 0 -> 0, step: 1

 8858 12:40:51.841574  

 8859 12:40:51.844616  RX Delay 0 -> 252, step: 8

 8860 12:40:51.847676  iDelay=208, Bit 0, Center 139 (88 ~ 191) 104

 8861 12:40:51.851236  iDelay=208, Bit 1, Center 135 (80 ~ 191) 112

 8862 12:40:51.854317  iDelay=208, Bit 2, Center 123 (72 ~ 175) 104

 8863 12:40:51.861198  iDelay=208, Bit 3, Center 131 (80 ~ 183) 104

 8864 12:40:51.864421  iDelay=208, Bit 4, Center 131 (80 ~ 183) 104

 8865 12:40:51.867660  iDelay=208, Bit 5, Center 151 (96 ~ 207) 112

 8866 12:40:51.870910  iDelay=208, Bit 6, Center 143 (88 ~ 199) 112

 8867 12:40:51.874685  iDelay=208, Bit 7, Center 135 (80 ~ 191) 112

 8868 12:40:51.880745  iDelay=208, Bit 8, Center 119 (64 ~ 175) 112

 8869 12:40:51.884477  iDelay=208, Bit 9, Center 119 (64 ~ 175) 112

 8870 12:40:51.887479  iDelay=208, Bit 10, Center 135 (80 ~ 191) 112

 8871 12:40:51.890867  iDelay=208, Bit 11, Center 127 (72 ~ 183) 112

 8872 12:40:51.894442  iDelay=208, Bit 12, Center 143 (88 ~ 199) 112

 8873 12:40:51.901267  iDelay=208, Bit 13, Center 143 (88 ~ 199) 112

 8874 12:40:51.904397  iDelay=208, Bit 14, Center 139 (88 ~ 191) 104

 8875 12:40:51.907851  iDelay=208, Bit 15, Center 143 (88 ~ 199) 112

 8876 12:40:51.907934  ==

 8877 12:40:51.911006  Dram Type= 6, Freq= 0, CH_1, rank 1

 8878 12:40:51.914278  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8879 12:40:51.914397  ==

 8880 12:40:51.918101  DQS Delay:

 8881 12:40:51.918196  DQS0 = 0, DQS1 = 0

 8882 12:40:51.921314  DQM Delay:

 8883 12:40:51.921431  DQM0 = 136, DQM1 = 133

 8884 12:40:51.921523  DQ Delay:

 8885 12:40:51.927849  DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131

 8886 12:40:51.930999  DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135

 8887 12:40:51.934245  DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127

 8888 12:40:51.937574  DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143

 8889 12:40:51.937686  

 8890 12:40:51.937779  

 8891 12:40:51.937877  ==

 8892 12:40:51.941326  Dram Type= 6, Freq= 0, CH_1, rank 1

 8893 12:40:51.944635  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8894 12:40:51.944716  ==

 8895 12:40:51.944779  

 8896 12:40:51.944849  

 8897 12:40:51.947570  	TX Vref Scan disable

 8898 12:40:51.951307   == TX Byte 0 ==

 8899 12:40:51.954417  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 8900 12:40:51.957565  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8901 12:40:51.961346   == TX Byte 1 ==

 8902 12:40:51.964538  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 8903 12:40:51.967698  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8904 12:40:51.967786  ==

 8905 12:40:51.970882  Dram Type= 6, Freq= 0, CH_1, rank 1

 8906 12:40:51.973999  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8907 12:40:51.977234  ==

 8908 12:40:51.989035  

 8909 12:40:51.991956  TX Vref early break, caculate TX vref

 8910 12:40:51.995460  TX Vref=16, minBit 0, minWin=23, winSum=382

 8911 12:40:51.998504  TX Vref=18, minBit 0, minWin=23, winSum=387

 8912 12:40:52.001977  TX Vref=20, minBit 1, minWin=24, winSum=401

 8913 12:40:52.005594  TX Vref=22, minBit 2, minWin=24, winSum=407

 8914 12:40:52.008601  TX Vref=24, minBit 0, minWin=25, winSum=417

 8915 12:40:52.015484  TX Vref=26, minBit 0, minWin=25, winSum=424

 8916 12:40:52.018618  TX Vref=28, minBit 0, minWin=26, winSum=427

 8917 12:40:52.021830  TX Vref=30, minBit 0, minWin=25, winSum=421

 8918 12:40:52.025646  TX Vref=32, minBit 0, minWin=24, winSum=415

 8919 12:40:52.028894  TX Vref=34, minBit 0, minWin=24, winSum=404

 8920 12:40:52.035374  [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 28

 8921 12:40:52.035497  

 8922 12:40:52.038704  Final TX Range 0 Vref 28

 8923 12:40:52.038783  

 8924 12:40:52.038849  ==

 8925 12:40:52.041858  Dram Type= 6, Freq= 0, CH_1, rank 1

 8926 12:40:52.045089  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8927 12:40:52.045167  ==

 8928 12:40:52.045230  

 8929 12:40:52.045290  

 8930 12:40:52.048944  	TX Vref Scan disable

 8931 12:40:52.055021  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps

 8932 12:40:52.055130   == TX Byte 0 ==

 8933 12:40:52.058615  u2DelayCellOfst[0]=16 cells (5 PI)

 8934 12:40:52.061649  u2DelayCellOfst[1]=13 cells (4 PI)

 8935 12:40:52.065381  u2DelayCellOfst[2]=0 cells (0 PI)

 8936 12:40:52.068570  u2DelayCellOfst[3]=6 cells (2 PI)

 8937 12:40:52.071873  u2DelayCellOfst[4]=10 cells (3 PI)

 8938 12:40:52.074957  u2DelayCellOfst[5]=16 cells (5 PI)

 8939 12:40:52.078257  u2DelayCellOfst[6]=16 cells (5 PI)

 8940 12:40:52.078364  u2DelayCellOfst[7]=6 cells (2 PI)

 8941 12:40:52.085391  Update DQ  dly =979 (3 ,6, 19)  DQ  OEN =(3 ,3)

 8942 12:40:52.088660  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8943 12:40:52.088747   == TX Byte 1 ==

 8944 12:40:52.091889  u2DelayCellOfst[8]=0 cells (0 PI)

 8945 12:40:52.095337  u2DelayCellOfst[9]=3 cells (1 PI)

 8946 12:40:52.098405  u2DelayCellOfst[10]=10 cells (3 PI)

 8947 12:40:52.101842  u2DelayCellOfst[11]=3 cells (1 PI)

 8948 12:40:52.104812  u2DelayCellOfst[12]=13 cells (4 PI)

 8949 12:40:52.108461  u2DelayCellOfst[13]=13 cells (4 PI)

 8950 12:40:52.111876  u2DelayCellOfst[14]=16 cells (5 PI)

 8951 12:40:52.114959  u2DelayCellOfst[15]=16 cells (5 PI)

 8952 12:40:52.118525  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 8953 12:40:52.125259  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8954 12:40:52.125376  DramC Write-DBI on

 8955 12:40:52.125471  ==

 8956 12:40:52.128448  Dram Type= 6, Freq= 0, CH_1, rank 1

 8957 12:40:52.131785  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8958 12:40:52.131888  ==

 8959 12:40:52.131980  

 8960 12:40:52.134979  

 8961 12:40:52.135079  	TX Vref Scan disable

 8962 12:40:52.138851   == TX Byte 0 ==

 8963 12:40:52.141968  Update DQM dly =723 (2 ,6, 19)  DQM OEN =(3 ,3)

 8964 12:40:52.145227   == TX Byte 1 ==

 8965 12:40:52.148464  Update DQM dly =723 (2 ,6, 19)  DQM OEN =(3 ,3)

 8966 12:40:52.148546  DramC Write-DBI off

 8967 12:40:52.148636  

 8968 12:40:52.151729  [DATLAT]

 8969 12:40:52.151824  Freq=1600, CH1 RK1

 8970 12:40:52.151888  

 8971 12:40:52.154904  DATLAT Default: 0xf

 8972 12:40:52.154974  0, 0xFFFF, sum = 0

 8973 12:40:52.158524  1, 0xFFFF, sum = 0

 8974 12:40:52.158632  2, 0xFFFF, sum = 0

 8975 12:40:52.161576  3, 0xFFFF, sum = 0

 8976 12:40:52.161702  4, 0xFFFF, sum = 0

 8977 12:40:52.165014  5, 0xFFFF, sum = 0

 8978 12:40:52.165133  6, 0xFFFF, sum = 0

 8979 12:40:52.168511  7, 0xFFFF, sum = 0

 8980 12:40:52.168631  8, 0xFFFF, sum = 0

 8981 12:40:52.171739  9, 0xFFFF, sum = 0

 8982 12:40:52.174800  10, 0xFFFF, sum = 0

 8983 12:40:52.174902  11, 0xFFFF, sum = 0

 8984 12:40:52.178653  12, 0xFFFF, sum = 0

 8985 12:40:52.178746  13, 0xFFFF, sum = 0

 8986 12:40:52.181833  14, 0x0, sum = 1

 8987 12:40:52.181920  15, 0x0, sum = 2

 8988 12:40:52.185042  16, 0x0, sum = 3

 8989 12:40:52.185124  17, 0x0, sum = 4

 8990 12:40:52.185191  best_step = 15

 8991 12:40:52.188293  

 8992 12:40:52.188401  ==

 8993 12:40:52.191491  Dram Type= 6, Freq= 0, CH_1, rank 1

 8994 12:40:52.194706  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8995 12:40:52.194795  ==

 8996 12:40:52.194862  RX Vref Scan: 0

 8997 12:40:52.194933  

 8998 12:40:52.198343  RX Vref 0 -> 0, step: 1

 8999 12:40:52.198428  

 9000 12:40:52.201657  RX Delay 19 -> 252, step: 4

 9001 12:40:52.205316  iDelay=195, Bit 0, Center 138 (91 ~ 186) 96

 9002 12:40:52.208129  iDelay=195, Bit 1, Center 130 (83 ~ 178) 96

 9003 12:40:52.214759  iDelay=195, Bit 2, Center 122 (75 ~ 170) 96

 9004 12:40:52.218166  iDelay=195, Bit 3, Center 130 (83 ~ 178) 96

 9005 12:40:52.221156  iDelay=195, Bit 4, Center 130 (83 ~ 178) 96

 9006 12:40:52.224924  iDelay=195, Bit 5, Center 146 (99 ~ 194) 96

 9007 12:40:52.227858  iDelay=195, Bit 6, Center 144 (95 ~ 194) 100

 9008 12:40:52.234924  iDelay=195, Bit 7, Center 134 (83 ~ 186) 104

 9009 12:40:52.237869  iDelay=195, Bit 8, Center 118 (67 ~ 170) 104

 9010 12:40:52.241099  iDelay=195, Bit 9, Center 118 (67 ~ 170) 104

 9011 12:40:52.244356  iDelay=195, Bit 10, Center 132 (83 ~ 182) 100

 9012 12:40:52.248303  iDelay=195, Bit 11, Center 124 (71 ~ 178) 108

 9013 12:40:52.254691  iDelay=195, Bit 12, Center 142 (91 ~ 194) 104

 9014 12:40:52.257886  iDelay=195, Bit 13, Center 138 (87 ~ 190) 104

 9015 12:40:52.261013  iDelay=195, Bit 14, Center 136 (87 ~ 186) 100

 9016 12:40:52.264721  iDelay=195, Bit 15, Center 140 (91 ~ 190) 100

 9017 12:40:52.264861  ==

 9018 12:40:52.267788  Dram Type= 6, Freq= 0, CH_1, rank 1

 9019 12:40:52.271359  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 9020 12:40:52.274777  ==

 9021 12:40:52.274868  DQS Delay:

 9022 12:40:52.274939  DQS0 = 0, DQS1 = 0

 9023 12:40:52.277792  DQM Delay:

 9024 12:40:52.277872  DQM0 = 134, DQM1 = 131

 9025 12:40:52.281450  DQ Delay:

 9026 12:40:52.284517  DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130

 9027 12:40:52.287724  DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134

 9028 12:40:52.291118  DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124

 9029 12:40:52.294391  DQ12 =142, DQ13 =138, DQ14 =136, DQ15 =140

 9030 12:40:52.294495  

 9031 12:40:52.294586  

 9032 12:40:52.294674  

 9033 12:40:52.298245  [DramC_TX_OE_Calibration] TA2

 9034 12:40:52.301251  Original DQ_B0 (3 6) =30, OEN = 27

 9035 12:40:52.304490  Original DQ_B1 (3 6) =30, OEN = 27

 9036 12:40:52.307830  24, 0x0, End_B0=24 End_B1=24

 9037 12:40:52.307944  25, 0x0, End_B0=25 End_B1=25

 9038 12:40:52.311065  26, 0x0, End_B0=26 End_B1=26

 9039 12:40:52.314481  27, 0x0, End_B0=27 End_B1=27

 9040 12:40:52.318086  28, 0x0, End_B0=28 End_B1=28

 9041 12:40:52.318193  29, 0x0, End_B0=29 End_B1=29

 9042 12:40:52.321082  30, 0x0, End_B0=30 End_B1=30

 9043 12:40:52.324647  31, 0x4141, End_B0=30 End_B1=30

 9044 12:40:52.327691  Byte0 end_step=30  best_step=27

 9045 12:40:52.331175  Byte1 end_step=30  best_step=27

 9046 12:40:52.334324  Byte0 TX OE(2T, 0.5T) = (3, 3)

 9047 12:40:52.334406  Byte1 TX OE(2T, 0.5T) = (3, 3)

 9048 12:40:52.334473  

 9049 12:40:52.338084  

 9050 12:40:52.344369  [DQSOSCAuto] RK1, (LSB)MR18= 0x2108, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps

 9051 12:40:52.348139  CH1 RK1: MR19=303, MR18=2108

 9052 12:40:52.354609  CH1_RK1: MR19=0x303, MR18=0x2108, DQSOSC=393, MR23=63, INC=23, DEC=15

 9053 12:40:52.357934  [RxdqsGatingPostProcess] freq 1600

 9054 12:40:52.361237  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 9055 12:40:52.364502  best DQS0 dly(2T, 0.5T) = (1, 1)

 9056 12:40:52.367722  best DQS1 dly(2T, 0.5T) = (1, 1)

 9057 12:40:52.371312  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 9058 12:40:52.374454  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 9059 12:40:52.377437  best DQS0 dly(2T, 0.5T) = (1, 1)

 9060 12:40:52.381001  best DQS1 dly(2T, 0.5T) = (1, 1)

 9061 12:40:52.384180  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 9062 12:40:52.387228  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 9063 12:40:52.390881  Pre-setting of DQS Precalculation

 9064 12:40:52.394075  [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15

 9065 12:40:52.400509  sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0

 9066 12:40:52.407434  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 9067 12:40:52.407559  

 9068 12:40:52.410702  

 9069 12:40:52.410800  [Calibration Summary] 3200 Mbps

 9070 12:40:52.413913  CH 0, Rank 0

 9071 12:40:52.414022  SW Impedance     : PASS

 9072 12:40:52.417140  DUTY Scan        : NO K

 9073 12:40:52.420901  ZQ Calibration   : PASS

 9074 12:40:52.421002  Jitter Meter     : NO K

 9075 12:40:52.423906  CBT Training     : PASS

 9076 12:40:52.427526  Write leveling   : PASS

 9077 12:40:52.427642  RX DQS gating    : PASS

 9078 12:40:52.430499  RX DQ/DQS(RDDQC) : PASS

 9079 12:40:52.433818  TX DQ/DQS        : PASS

 9080 12:40:52.433908  RX DATLAT        : PASS

 9081 12:40:52.437429  RX DQ/DQS(Engine): PASS

 9082 12:40:52.440487  TX OE            : PASS

 9083 12:40:52.440578  All Pass.

 9084 12:40:52.440646  

 9085 12:40:52.440709  CH 0, Rank 1

 9086 12:40:52.444157  SW Impedance     : PASS

 9087 12:40:52.446995  DUTY Scan        : NO K

 9088 12:40:52.447087  ZQ Calibration   : PASS

 9089 12:40:52.450754  Jitter Meter     : NO K

 9090 12:40:52.450844  CBT Training     : PASS

 9091 12:40:52.453879  Write leveling   : PASS

 9092 12:40:52.457195  RX DQS gating    : PASS

 9093 12:40:52.457289  RX DQ/DQS(RDDQC) : PASS

 9094 12:40:52.460382  TX DQ/DQS        : PASS

 9095 12:40:52.463656  RX DATLAT        : PASS

 9096 12:40:52.463745  RX DQ/DQS(Engine): PASS

 9097 12:40:52.466826  TX OE            : PASS

 9098 12:40:52.466914  All Pass.

 9099 12:40:52.466981  

 9100 12:40:52.470795  CH 1, Rank 0

 9101 12:40:52.470881  SW Impedance     : PASS

 9102 12:40:52.473911  DUTY Scan        : NO K

 9103 12:40:52.476994  ZQ Calibration   : PASS

 9104 12:40:52.477081  Jitter Meter     : NO K

 9105 12:40:52.480554  CBT Training     : PASS

 9106 12:40:52.483556  Write leveling   : PASS

 9107 12:40:52.483645  RX DQS gating    : PASS

 9108 12:40:52.487278  RX DQ/DQS(RDDQC) : PASS

 9109 12:40:52.490259  TX DQ/DQS        : PASS

 9110 12:40:52.490352  RX DATLAT        : PASS

 9111 12:40:52.493429  RX DQ/DQS(Engine): PASS

 9112 12:40:52.497053  TX OE            : PASS

 9113 12:40:52.497149  All Pass.

 9114 12:40:52.497216  

 9115 12:40:52.497280  CH 1, Rank 1

 9116 12:40:52.500346  SW Impedance     : PASS

 9117 12:40:52.503495  DUTY Scan        : NO K

 9118 12:40:52.503582  ZQ Calibration   : PASS

 9119 12:40:52.506840  Jitter Meter     : NO K

 9120 12:40:52.506927  CBT Training     : PASS

 9121 12:40:52.510461  Write leveling   : PASS

 9122 12:40:52.513531  RX DQS gating    : PASS

 9123 12:40:52.513632  RX DQ/DQS(RDDQC) : PASS

 9124 12:40:52.516908  TX DQ/DQS        : PASS

 9125 12:40:52.520001  RX DATLAT        : PASS

 9126 12:40:52.520092  RX DQ/DQS(Engine): PASS

 9127 12:40:52.523596  TX OE            : PASS

 9128 12:40:52.523685  All Pass.

 9129 12:40:52.523752  

 9130 12:40:52.526785  DramC Write-DBI on

 9131 12:40:52.530182  	PER_BANK_REFRESH: Hybrid Mode

 9132 12:40:52.530266  TX_TRACKING: ON

 9133 12:40:52.539857  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0

 9134 12:40:52.547049  sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1

 9135 12:40:52.553194  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 9136 12:40:52.556886  [FAST_K] Save calibration result to emmc

 9137 12:40:52.559921  sync common calibartion params.

 9138 12:40:52.563513  sync cbt_mode0:1, 1:1

 9139 12:40:52.566815  dram_init: ddr_geometry: 2

 9140 12:40:52.566908  dram_init: ddr_geometry: 2

 9141 12:40:52.570065  dram_init: ddr_geometry: 2

 9142 12:40:52.573340  0:dram_rank_size:100000000

 9143 12:40:52.576534  1:dram_rank_size:100000000

 9144 12:40:52.580275  sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000

 9145 12:40:52.583381  DFS_SHUFFLE_HW_MODE: ON

 9146 12:40:52.586981  dramc_set_vcore_voltage set vcore to 725000

 9147 12:40:52.589953  Read voltage for 1600, 0

 9148 12:40:52.590068  Vio18 = 0

 9149 12:40:52.590162  Vcore = 725000

 9150 12:40:52.593460  Vdram = 0

 9151 12:40:52.593547  Vddq = 0

 9152 12:40:52.593614  Vmddr = 0

 9153 12:40:52.596672  switch to 3200 Mbps bootup

 9154 12:40:52.600347  [DramcRunTimeConfig]

 9155 12:40:52.600441  PHYPLL

 9156 12:40:52.600510  DPM_CONTROL_AFTERK: ON

 9157 12:40:52.603454  PER_BANK_REFRESH: ON

 9158 12:40:52.606890  REFRESH_OVERHEAD_REDUCTION: ON

 9159 12:40:52.606980  CMD_PICG_NEW_MODE: OFF

 9160 12:40:52.610291  XRTWTW_NEW_MODE: ON

 9161 12:40:52.610377  XRTRTR_NEW_MODE: ON

 9162 12:40:52.613331  TX_TRACKING: ON

 9163 12:40:52.613425  RDSEL_TRACKING: OFF

 9164 12:40:52.616450  DQS Precalculation for DVFS: ON

 9165 12:40:52.620325  RX_TRACKING: OFF

 9166 12:40:52.620411  HW_GATING DBG: ON

 9167 12:40:52.623166  ZQCS_ENABLE_LP4: ON

 9168 12:40:52.623253  RX_PICG_NEW_MODE: ON

 9169 12:40:52.626844  TX_PICG_NEW_MODE: ON

 9170 12:40:52.630002  ENABLE_RX_DCM_DPHY: ON

 9171 12:40:52.633267  LOWPOWER_GOLDEN_SETTINGS(DCM): ON

 9172 12:40:52.633353  DUMMY_READ_FOR_TRACKING: OFF

 9173 12:40:52.636797  !!! SPM_CONTROL_AFTERK: OFF

 9174 12:40:52.640042  !!! SPM could not control APHY

 9175 12:40:52.643070  IMPEDANCE_TRACKING: ON

 9176 12:40:52.643159  TEMP_SENSOR: ON

 9177 12:40:52.643225  HW_SAVE_FOR_SR: OFF

 9178 12:40:52.646902  CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF

 9179 12:40:52.653414  PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF

 9180 12:40:52.653506  Read ODT Tracking: ON

 9181 12:40:52.656528  Refresh Rate DeBounce: ON

 9182 12:40:52.656616  DFS_NO_QUEUE_FLUSH: ON

 9183 12:40:52.660118  DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF

 9184 12:40:52.663221  ENABLE_DFS_RUNTIME_MRW: OFF

 9185 12:40:52.666819  DDR_RESERVE_NEW_MODE: ON

 9186 12:40:52.666917  MR_CBT_SWITCH_FREQ: ON

 9187 12:40:52.670155  =========================

 9188 12:40:52.689160  [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)

 9189 12:40:52.692479  dram_init: ddr_geometry: 2

 9190 12:40:52.710501  [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)

 9191 12:40:52.713803  dram_init: dram init end (result: 0)

 9192 12:40:52.720669  DRAM-K: Full calibration passed in 24457 msecs

 9193 12:40:52.723980  MRC: failed to locate region type 0.

 9194 12:40:52.724069  DRAM rank0 size:0x100000000,

 9195 12:40:52.727280  DRAM rank1 size=0x100000000

 9196 12:40:52.737365  Mapping address range [0x40000000:0x240000000) as     cacheable | read-write | non-secure | normal

 9197 12:40:52.744068  Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal

 9198 12:40:52.750484  Backing address range [0x40000000:0x80000000) with new page table @0x00112000

 9199 12:40:52.757503  Backing address range [0x40000000:0x40200000) with new page table @0x00113000

 9200 12:40:52.760472  DRAM rank0 size:0x100000000,

 9201 12:40:52.763912  DRAM rank1 size=0x100000000

 9202 12:40:52.764001  CBMEM:

 9203 12:40:52.766858  IMD: root @ 0xfffff000 254 entries.

 9204 12:40:52.770545  IMD: root @ 0xffffec00 62 entries.

 9205 12:40:52.773523  FMAP: area RO_VPD found @ 3f8000 (32768 bytes)

 9206 12:40:52.777307  WARNING: RO_VPD is uninitialized or empty.

 9207 12:40:52.783603  FMAP: area RW_VPD found @ 577000 (16384 bytes)

 9208 12:40:52.790631  CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80

 9209 12:40:52.803216  read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps

 9210 12:40:52.814944  BS: romstage times (exec / console): total (unknown) / 23991 ms

 9211 12:40:52.815082  

 9212 12:40:52.815188  

 9213 12:40:52.825080  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...

 9214 12:40:52.828305  ARM64: Exception handlers installed.

 9215 12:40:52.831728  ARM64: Testing exception

 9216 12:40:52.834600  ARM64: Done test exception

 9217 12:40:52.834710  Enumerating buses...

 9218 12:40:52.837860  Show all devs... Before device enumeration.

 9219 12:40:52.841668  Root Device: enabled 1

 9220 12:40:52.844781  CPU_CLUSTER: 0: enabled 1

 9221 12:40:52.844872  CPU: 00: enabled 1

 9222 12:40:52.847883  Compare with tree...

 9223 12:40:52.847961  Root Device: enabled 1

 9224 12:40:52.851014   CPU_CLUSTER: 0: enabled 1

 9225 12:40:52.854297    CPU: 00: enabled 1

 9226 12:40:52.854400  Root Device scanning...

 9227 12:40:52.858064  scan_static_bus for Root Device

 9228 12:40:52.861344  CPU_CLUSTER: 0 enabled

 9229 12:40:52.864538  scan_static_bus for Root Device done

 9230 12:40:52.867619  scan_bus: bus Root Device finished in 8 msecs

 9231 12:40:52.867705  done

 9232 12:40:52.874393  BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms

 9233 12:40:52.877984  FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)

 9234 12:40:52.884638  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

 9235 12:40:52.887810  BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms

 9236 12:40:52.891070  Allocating resources...

 9237 12:40:52.894348  Reading resources...

 9238 12:40:52.898325  Root Device read_resources bus 0 link: 0

 9239 12:40:52.898413  DRAM rank0 size:0x100000000,

 9240 12:40:52.901198  DRAM rank1 size=0x100000000

 9241 12:40:52.904339  CPU_CLUSTER: 0 read_resources bus 0 link: 0

 9242 12:40:52.907974  CPU: 00 missing read_resources

 9243 12:40:52.910982  CPU_CLUSTER: 0 read_resources bus 0 link: 0 done

 9244 12:40:52.917791  Root Device read_resources bus 0 link: 0 done

 9245 12:40:52.917894  Done reading resources.

 9246 12:40:52.924680  Show resources in subtree (Root Device)...After reading.

 9247 12:40:52.927769   Root Device child on link 0 CPU_CLUSTER: 0

 9248 12:40:52.930976    CPU_CLUSTER: 0 child on link 0 CPU: 00

 9249 12:40:52.941216    CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0

 9250 12:40:52.941325     CPU: 00

 9251 12:40:52.944407  Root Device assign_resources, bus 0 link: 0

 9252 12:40:52.947637  CPU_CLUSTER: 0 missing set_resources

 9253 12:40:52.951384  Root Device assign_resources, bus 0 link: 0 done

 9254 12:40:52.954535  Done setting resources.

 9255 12:40:52.961047  Show resources in subtree (Root Device)...After assigning values.

 9256 12:40:52.964852   Root Device child on link 0 CPU_CLUSTER: 0

 9257 12:40:52.967529    CPU_CLUSTER: 0 child on link 0 CPU: 00

 9258 12:40:52.978250    CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0

 9259 12:40:52.978367     CPU: 00

 9260 12:40:52.981363  Done allocating resources.

 9261 12:40:52.984433  BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms

 9262 12:40:52.987390  Enabling resources...

 9263 12:40:52.987504  done.

 9264 12:40:52.994430  BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms

 9265 12:40:52.994565  Initializing devices...

 9266 12:40:52.997632  Root Device init

 9267 12:40:52.997748  init hardware done!

 9268 12:40:53.000766  0x00000018: ctrlr->caps

 9269 12:40:53.004052  52.000 MHz: ctrlr->f_max

 9270 12:40:53.004176  0.400 MHz: ctrlr->f_min

 9271 12:40:53.007934  0x40ff8080: ctrlr->voltages

 9272 12:40:53.008087  sclk: 390625

 9273 12:40:53.010960  Bus Width = 1

 9274 12:40:53.011065  sclk: 390625

 9275 12:40:53.013960  Bus Width = 1

 9276 12:40:53.014068  Early init status = 3

 9277 12:40:53.020594  out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00 

 9278 12:40:53.023795  in-header: 03 fc 00 00 01 00 00 00 

 9279 12:40:53.023914  in-data: 00 

 9280 12:40:53.030709  out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01 

 9281 12:40:53.033819  in-header: 03 fd 00 00 00 00 00 00 

 9282 12:40:53.037894  in-data: 

 9283 12:40:53.040964  out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00 

 9284 12:40:53.044674  in-header: 03 fc 00 00 01 00 00 00 

 9285 12:40:53.047923  in-data: 00 

 9286 12:40:53.051083  out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01 

 9287 12:40:53.056825  in-header: 03 fd 00 00 00 00 00 00 

 9288 12:40:53.059872  in-data: 

 9289 12:40:53.063069  [SSUSB] Setting up USB HOST controller...

 9290 12:40:53.066192  [SSUSB] u3phy_ports_enable u2p:1, u3p:1

 9291 12:40:53.069589  [SSUSB] phy power-on done.

 9292 12:40:53.073259  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

 9293 12:40:53.079437  CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c

 9294 12:40:53.083202  mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)

 9295 12:40:53.089545  CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c

 9296 12:40:53.096255  read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps

 9297 12:40:53.102679  mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)

 9298 12:40:53.109792  CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204

 9299 12:40:53.116042  read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps

 9300 12:40:53.119149  SPM: binary array size = 0x9dc

 9301 12:40:53.122727  SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)

 9302 12:40:53.129303  spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18

 9303 12:40:53.136021  mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)

 9304 12:40:53.139201  SPM: spm_init done in 34 msecs, spm pc = 0x3f4

 9305 12:40:53.145926  configure_display: Starting display init

 9306 12:40:53.179784  anx7625_power_on_init: Init interface.

 9307 12:40:53.183012  anx7625_disable_pd_protocol: Disabled PD feature.

 9308 12:40:53.186188  anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.

 9309 12:40:53.214030  anx7625_start_dp_work: Secure OCM version=00

 9310 12:40:53.217303  anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91

 9311 12:40:53.231771  sp_tx_get_edid_block: EDID Block = 1

 9312 12:40:53.334567  Extracted contents:

 9313 12:40:53.337998  header:          00 ff ff ff ff ff ff 00

 9314 12:40:53.341072  serial number:   26 cf 7d 05 00 00 00 00 00 1e

 9315 12:40:53.344948  version:         01 04

 9316 12:40:53.347848  basic params:    95 1f 11 78 0a

 9317 12:40:53.350917  chroma info:     76 90 94 55 54 90 27 21 50 54

 9318 12:40:53.354423  established:     00 00 00

 9319 12:40:53.361309  standard:        01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01

 9320 12:40:53.364577  descriptor 1:    38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19

 9321 12:40:53.371180  descriptor 2:    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

 9322 12:40:53.377499  descriptor 3:    00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20

 9323 12:40:53.384217  descriptor 4:    00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a

 9324 12:40:53.387390  extensions:      00

 9325 12:40:53.387478  checksum:        fb

 9326 12:40:53.387545  

 9327 12:40:53.391109  Manufacturer: IVO Model 57d Serial Number 0

 9328 12:40:53.394410  Made week 0 of 2020

 9329 12:40:53.394495  EDID version: 1.4

 9330 12:40:53.397710  Digital display

 9331 12:40:53.400813  6 bits per primary color channel

 9332 12:40:53.400896  DisplayPort interface

 9333 12:40:53.403972  Maximum image size: 31 cm x 17 cm

 9334 12:40:53.407678  Gamma: 220%

 9335 12:40:53.407758  Check DPMS levels

 9336 12:40:53.410698  Supported color formats: RGB 4:4:4, YCrCb 4:2:2

 9337 12:40:53.417689  First detailed timing is preferred timing

 9338 12:40:53.417779  Established timings supported:

 9339 12:40:53.420709  Standard timings supported:

 9340 12:40:53.424344  Detailed timings

 9341 12:40:53.427547  Hex of detail: 383680a07038204018303c0035ae10000019

 9342 12:40:53.430737  Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm

 9343 12:40:53.437668                 0780 0798 07c8 0820 hborder 0

 9344 12:40:53.440743                 0438 043b 0447 0458 vborder 0

 9345 12:40:53.444271                 -hsync -vsync

 9346 12:40:53.444401  Did detailed timing

 9347 12:40:53.450806  Hex of detail: 000000000000000000000000000000000000

 9348 12:40:53.450921  Manufacturer-specified data, tag 0

 9349 12:40:53.457987  Hex of detail: 000000fe00496e666f566973696f6e0a2020

 9350 12:40:53.460554  ASCII string: InfoVision

 9351 12:40:53.464286  Hex of detail: 000000fe00523134304e574635205248200a

 9352 12:40:53.467192  ASCII string: R140NWF5 RH 

 9353 12:40:53.467282  Checksum

 9354 12:40:53.471028  Checksum: 0xfb (valid)

 9355 12:40:53.474125  configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz

 9356 12:40:53.477145  DSI data_rate: 832800000 bps

 9357 12:40:53.483664  anx7625_parse_edid: detected IVO panel, use k value 0x3b

 9358 12:40:53.486957  anx7625_parse_edid: pixelclock(138800).

 9359 12:40:53.490485   hactive(1920), hsync(48), hfp(24), hbp(88)

 9360 12:40:53.493628   vactive(1080), vsync(12), vfp(3), vbp(17)

 9361 12:40:53.497374  anx7625_dsi_config: config dsi.

 9362 12:40:53.503875  anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).

 9363 12:40:53.516646  anx7625_dsi_config: success to config DSI

 9364 12:40:53.519798  anx7625_dp_start: MIPI phy setup OK.

 9365 12:40:53.523173  mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4

 9366 12:40:53.526779  mtk_ddp_mode_set invalid vrefresh 60

 9367 12:40:53.529758  main_disp_path_setup

 9368 12:40:53.529880  ovl_layer_smi_id_en

 9369 12:40:53.533442  ovl_layer_smi_id_en

 9370 12:40:53.533550  ccorr_config

 9371 12:40:53.533658  aal_config

 9372 12:40:53.536724  gamma_config

 9373 12:40:53.536850  postmask_config

 9374 12:40:53.539945  dither_config

 9375 12:40:53.543110  framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32

 9376 12:40:53.549986                     x_res x y_res: 1920 x 1080, size: 8294400 at 0x0

 9377 12:40:53.553445  Root Device init finished in 553 msecs

 9378 12:40:53.553537  CPU_CLUSTER: 0 init

 9379 12:40:53.563144  Mapping address range [0x00200000:0x00300000) as     cacheable | read-write |     secure | device

 9380 12:40:53.566165  INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff

 9381 12:40:53.569689  APU_MBOX 0x190000b0 = 0x10001

 9382 12:40:53.573534  APU_MBOX 0x190001b0 = 0x10001

 9383 12:40:53.576306  APU_MBOX 0x190005b0 = 0x10001

 9384 12:40:53.579946  APU_MBOX 0x190006b0 = 0x10001

 9385 12:40:53.582948  CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c

 9386 12:40:53.595797  read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps

 9387 12:40:53.608130  mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)

 9388 12:40:53.614724  CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0

 9389 12:40:53.626647  read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps

 9390 12:40:53.635811  mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)

 9391 12:40:53.638707  CPU_CLUSTER: 0 init finished in 81 msecs

 9392 12:40:53.641872  Devices initialized

 9393 12:40:53.645507  Show all devs... After init.

 9394 12:40:53.645661  Root Device: enabled 1

 9395 12:40:53.648637  CPU_CLUSTER: 0: enabled 1

 9396 12:40:53.651850  CPU: 00: enabled 1

 9397 12:40:53.655726  BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms

 9398 12:40:53.658881  FMAP: area RW_ELOG found @ 57f000 (4096 bytes)

 9399 12:40:53.661919  ELOG: NV offset 0x57f000 size 0x1000

 9400 12:40:53.668644  read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps

 9401 12:40:53.675368  ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024

 9402 12:40:53.678448  ELOG: Event(17) added with size 13 at 2023-06-14 12:40:39 UTC

 9403 12:40:53.682198  out: cmd=0x121: 03 db 21 01 00 00 00 00 

 9404 12:40:53.685545  in-header: 03 dc 00 00 2c 00 00 00 

 9405 12:40:53.698627  in-data: 83 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 

 9406 12:40:53.705645  ELOG: Event(A1) added with size 10 at 2023-06-14 12:40:39 UTC

 9407 12:40:53.712113  elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b

 9408 12:40:53.719258  ELOG: Event(A0) added with size 9 at 2023-06-14 12:40:39 UTC

 9409 12:40:53.722267  elog_add_boot_reason: Logged dev mode boot

 9410 12:40:53.726081  BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms

 9411 12:40:53.729285  Finalize devices...

 9412 12:40:53.729375  Devices finalized

 9413 12:40:53.735491  BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms

 9414 12:40:53.739307  Writing coreboot table at 0xffe64000

 9415 12:40:53.742403   0. 000000000010a000-0000000000113fff: RAMSTAGE

 9416 12:40:53.745944   1. 0000000040000000-00000000400fffff: RAM

 9417 12:40:53.749108   2. 0000000040100000-000000004032afff: RAMSTAGE

 9418 12:40:53.755277   3. 000000004032b000-00000000545fffff: RAM

 9419 12:40:53.759018   4. 0000000054600000-000000005465ffff: BL31

 9420 12:40:53.762245   5. 0000000054660000-00000000ffe63fff: RAM

 9421 12:40:53.765663   6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES

 9422 12:40:53.772368   7. 0000000100000000-000000023fffffff: RAM

 9423 12:40:53.772503  Passing 5 GPIOs to payload:

 9424 12:40:53.778603              NAME |       PORT | POLARITY |     VALUE

 9425 12:40:53.782161          EC in RW | 0x000000aa |      low | undefined

 9426 12:40:53.788873      EC interrupt | 0x00000005 |      low | undefined

 9427 12:40:53.791956     TPM interrupt | 0x000000ab |     high | undefined

 9428 12:40:53.795364    SD card detect | 0x00000011 |     high | undefined

 9429 12:40:53.802031    speaker enable | 0x00000093 |     high | undefined

 9430 12:40:53.805175  out: cmd=0x6: 03 f7 06 00 00 00 00 00 

 9431 12:40:53.808347  in-header: 03 f9 00 00 02 00 00 00 

 9432 12:40:53.808435  in-data: 02 00 

 9433 12:40:53.812177  ADC[4]: Raw value=905096 ID=7

 9434 12:40:53.815449  ADC[3]: Raw value=213441 ID=1

 9435 12:40:53.815535  RAM Code: 0x71

 9436 12:40:53.818674  ADC[6]: Raw value=75332 ID=0

 9437 12:40:53.821916  ADC[5]: Raw value=213072 ID=1

 9438 12:40:53.822002  SKU Code: 0x1

 9439 12:40:53.828824  Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4e98

 9440 12:40:53.832027  coreboot table: 964 bytes.

 9441 12:40:53.835205  IMD ROOT    0. 0xfffff000 0x00001000

 9442 12:40:53.838369  IMD SMALL   1. 0xffffe000 0x00001000

 9443 12:40:53.841777  RO MCACHE   2. 0xffffc000 0x00001104

 9444 12:40:53.845050  CONSOLE     3. 0xfff7c000 0x00080000

 9445 12:40:53.848608  FMAP        4. 0xfff7b000 0x00000452

 9446 12:40:53.851775  TIME STAMP  5. 0xfff7a000 0x00000910

 9447 12:40:53.855162  VBOOT WORK  6. 0xfff66000 0x00014000

 9448 12:40:53.858240  RAMOOPS     7. 0xffe66000 0x00100000

 9449 12:40:53.862012  COREBOOT    8. 0xffe64000 0x00002000

 9450 12:40:53.862113  IMD small region:

 9451 12:40:53.865164    IMD ROOT    0. 0xffffec00 0x00000400

 9452 12:40:53.868496    VPD         1. 0xffffeba0 0x0000004c

 9453 12:40:53.871557    MMC STATUS  2. 0xffffeb80 0x00000004

 9454 12:40:53.878524  BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms

 9455 12:40:53.881676  Probing TPM:  done!

 9456 12:40:53.885281  Connected to device vid:did:rid of 1ae0:0028:00

 9457 12:40:53.895084  Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523

 9458 12:40:53.898707  Initialized TPM device CR50 revision 0

 9459 12:40:53.902359  Checking cr50 for pending updates

 9460 12:40:53.905318  Reading cr50 TPM mode

 9461 12:40:53.914214  BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms

 9462 12:40:53.920742  CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098

 9463 12:40:53.960765  read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps

 9464 12:40:53.963707  Checking segment from ROM address 0x40100000

 9465 12:40:53.967282  Checking segment from ROM address 0x4010001c

 9466 12:40:53.974324  Loading segment from ROM address 0x40100000

 9467 12:40:53.974447    code (compression=0)

 9468 12:40:53.980565    New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178

 9469 12:40:53.990474  Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178

 9470 12:40:53.990592  it's not compressed!

 9471 12:40:53.997475  [ 0x80000000, 8004f178, 0x821a7280) <- 40100038

 9472 12:40:54.000618  Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108

 9473 12:40:54.021056  Loading segment from ROM address 0x4010001c

 9474 12:40:54.021189    Entry Point 0x80000000

 9475 12:40:54.024216  Loaded segments

 9476 12:40:54.027451  BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms

 9477 12:40:54.034455  Jumping to boot code at 0x80000000(0xffe64000)

 9478 12:40:54.040854  CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes

 9479 12:40:54.047630  CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290

 9480 12:40:54.055406  read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps

 9481 12:40:54.059061  Checking segment from ROM address 0x40100000

 9482 12:40:54.062322  Checking segment from ROM address 0x4010001c

 9483 12:40:54.068654  Loading segment from ROM address 0x40100000

 9484 12:40:54.068769    code (compression=1)

 9485 12:40:54.075585    New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470

 9486 12:40:54.085436  Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470

 9487 12:40:54.085551  using LZMA

 9488 12:40:54.093600  [ 0x54600000, 54614abc, 0x5462e000) <- 40100038

 9489 12:40:54.100704  Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544

 9490 12:40:54.103879  Loading segment from ROM address 0x4010001c

 9491 12:40:54.103991    Entry Point 0x54601000

 9492 12:40:54.106851  Loaded segments

 9493 12:40:54.110095  NOTICE:  MT8192 bl31_setup

 9494 12:40:54.117252  NOTICE:  BL31: v2.4(debug):v2.4-448-gce3ebc861

 9495 12:40:54.121003  NOTICE:  BL31: Built : Sat Sep 11 09:59:37 UTC 2021

 9496 12:40:54.124037  WARNING: region 0:

 9497 12:40:54.127519  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9498 12:40:54.127659  WARNING: region 1:

 9499 12:40:54.133890  WARNING: 	sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d

 9500 12:40:54.137850  WARNING: region 2:

 9501 12:40:54.140760  WARNING: 	sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d

 9502 12:40:54.144082  WARNING: region 3:

 9503 12:40:54.147364  WARNING: 	sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d

 9504 12:40:54.151171  WARNING: region 4:

 9505 12:40:54.154517  WARNING: 	sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d

 9506 12:40:54.157713  WARNING: region 5:

 9507 12:40:54.160763  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9508 12:40:54.164005  WARNING: region 6:

 9509 12:40:54.167760  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9510 12:40:54.167867  WARNING: region 7:

 9511 12:40:54.174675  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9512 12:40:54.181352  INFO:    [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000

 9513 12:40:54.184205  INFO:    [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0

 9514 12:40:54.187784  INFO:    [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff

 9515 12:40:54.194454  INFO:    [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff

 9516 12:40:54.198142  INFO:    [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff

 9517 12:40:54.201283  INFO:    [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00

 9518 12:40:54.207684  INFO:    [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff

 9519 12:40:54.210888  INFO:    [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff

 9520 12:40:54.214018  INFO:    [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff

 9521 12:40:54.221004  INFO:    [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff

 9522 12:40:54.224552  INFO:    [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff

 9523 12:40:54.231376  INFO:    [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff

 9524 12:40:54.234136  INFO:    [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff

 9525 12:40:54.237783  INFO:    [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff

 9526 12:40:54.244093  INFO:    [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff

 9527 12:40:54.247350  INFO:    [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff

 9528 12:40:54.250657  INFO:    [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff

 9529 12:40:54.257760  INFO:    [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff

 9530 12:40:54.261069  INFO:    [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff

 9531 12:40:54.267389  INFO:    [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff

 9532 12:40:54.271236  INFO:    [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff

 9533 12:40:54.274426  INFO:    [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff

 9534 12:40:54.281399  INFO:    [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff

 9535 12:40:54.284510  INFO:    [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff

 9536 12:40:54.287682  INFO:    [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff

 9537 12:40:54.294477  INFO:    [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff

 9538 12:40:54.297565  INFO:    [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff

 9539 12:40:54.304142  INFO:    [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff

 9540 12:40:54.307768  INFO:    [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff

 9541 12:40:54.310979  INFO:    [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff

 9542 12:40:54.318056  INFO:    [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff

 9543 12:40:54.321456  INFO:    [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff

 9544 12:40:54.324671  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0

 9545 12:40:54.330865  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0

 9546 12:40:54.334482  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0

 9547 12:40:54.338108  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0

 9548 12:40:54.341164  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0

 9549 12:40:54.347696  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0

 9550 12:40:54.351360  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0

 9551 12:40:54.354679  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0

 9552 12:40:54.357900  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0

 9553 12:40:54.364504  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0

 9554 12:40:54.367611  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0

 9555 12:40:54.371452  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0

 9556 12:40:54.374754  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0

 9557 12:40:54.381144  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0

 9558 12:40:54.384977  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0

 9559 12:40:54.387714  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0

 9560 12:40:54.394416  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff

 9561 12:40:54.398105  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff

 9562 12:40:54.401128  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff

 9563 12:40:54.407962  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff

 9564 12:40:54.411569  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff

 9565 12:40:54.417926  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff

 9566 12:40:54.421173  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff

 9567 12:40:54.427918  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff

 9568 12:40:54.431631  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff

 9569 12:40:54.434681  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff

 9570 12:40:54.441431  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff

 9571 12:40:54.444403  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff

 9572 12:40:54.451217  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff

 9573 12:40:54.454692  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff

 9574 12:40:54.461175  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff

 9575 12:40:54.465175  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff

 9576 12:40:54.468317  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff

 9577 12:40:54.474766  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff

 9578 12:40:54.477811  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff

 9579 12:40:54.485007  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff

 9580 12:40:54.488136  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff

 9581 12:40:54.494546  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff

 9582 12:40:54.498331  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff

 9583 12:40:54.501511  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff

 9584 12:40:54.508292  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff

 9585 12:40:54.511532  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff

 9586 12:40:54.518468  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff

 9587 12:40:54.521865  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff

 9588 12:40:54.528002  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff

 9589 12:40:54.532105  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff

 9590 12:40:54.534886  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff

 9591 12:40:54.541872  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff

 9592 12:40:54.544871  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff

 9593 12:40:54.551650  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff

 9594 12:40:54.554932  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff

 9595 12:40:54.561622  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff

 9596 12:40:54.565261  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff

 9597 12:40:54.568344  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff

 9598 12:40:54.575494  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff

 9599 12:40:54.578578  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff

 9600 12:40:54.585077  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff

 9601 12:40:54.588569  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff

 9602 12:40:54.591636  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff

 9603 12:40:54.598066  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff

 9604 12:40:54.601875  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff

 9605 12:40:54.608280  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff

 9606 12:40:54.611450  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff

 9607 12:40:54.618429  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff

 9608 12:40:54.621811  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0

 9609 12:40:54.625322  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0

 9610 12:40:54.628373  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0

 9611 12:40:54.635339  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0

 9612 12:40:54.638319  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0

 9613 12:40:54.642123  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff

 9614 12:40:54.648382  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff

 9615 12:40:54.651659  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff

 9616 12:40:54.658372  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff

 9617 12:40:54.662136  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff

 9618 12:40:54.664984  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff

 9619 12:40:54.671875  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff

 9620 12:40:54.675438  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff

 9621 12:40:54.681834  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff

 9622 12:40:54.684940  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff

 9623 12:40:54.688765  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff

 9624 12:40:54.695078  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff

 9625 12:40:54.698962  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff

 9626 12:40:54.702166  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff

 9627 12:40:54.709016  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff

 9628 12:40:54.712301  INFO:    [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18

 9629 12:40:54.715599  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000

 9630 12:40:54.722410  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004

 9631 12:40:54.725721  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0

 9632 12:40:54.728699  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0

 9633 12:40:54.731923  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0

 9634 12:40:54.738625  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0

 9635 12:40:54.742072  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000

 9636 12:40:54.745557  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff

 9637 12:40:54.752335  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff

 9638 12:40:54.755422  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff

 9639 12:40:54.758581  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff

 9640 12:40:54.765463  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff

 9641 12:40:54.768533  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff

 9642 12:40:54.772155  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff

 9643 12:40:54.778728  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc

 9644 12:40:54.782465  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff

 9645 12:40:54.788808  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf

 9646 12:40:54.792088  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff

 9647 12:40:54.796000  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc

 9648 12:40:54.802380  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff

 9649 12:40:54.805741  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff

 9650 12:40:54.812604  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff

 9651 12:40:54.815673  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff

 9652 12:40:54.818839  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff

 9653 12:40:54.825921  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff

 9654 12:40:54.828915  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff

 9655 12:40:54.836187  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff

 9656 12:40:54.839300  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff

 9657 12:40:54.842458  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff

 9658 12:40:54.849501  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff

 9659 12:40:54.852728  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff

 9660 12:40:54.855680  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff

 9661 12:40:54.862799  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff

 9662 12:40:54.865919  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff

 9663 12:40:54.869749  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff

 9664 12:40:54.876582  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff

 9665 12:40:54.879632  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff

 9666 12:40:54.886266  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff

 9667 12:40:54.889442  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff

 9668 12:40:54.893063  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff

 9669 12:40:54.899575  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff

 9670 12:40:54.902585  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff

 9671 12:40:54.906409  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff

 9672 12:40:54.912758  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff

 9673 12:40:54.916456  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff

 9674 12:40:54.923033  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff

 9675 12:40:54.926224  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff

 9676 12:40:54.930118  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff

 9677 12:40:54.936186  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff

 9678 12:40:54.939840  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff

 9679 12:40:54.946316  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff

 9680 12:40:54.949441  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff

 9681 12:40:54.953002  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff

 9682 12:40:54.959712  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff

 9683 12:40:54.963061  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff

 9684 12:40:54.965934  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff

 9685 12:40:54.972629  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff

 9686 12:40:54.976533  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff

 9687 12:40:54.983012  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff

 9688 12:40:54.986058  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff

 9689 12:40:54.989749  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff

 9690 12:40:54.995892  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff

 9691 12:40:54.999010  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff

 9692 12:40:55.005939  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff

 9693 12:40:55.009044  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff

 9694 12:40:55.012347  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff

 9695 12:40:55.019249  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff

 9696 12:40:55.022502  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff

 9697 12:40:55.028873  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff

 9698 12:40:55.032145  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff

 9699 12:40:55.036149  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff

 9700 12:40:55.042196  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff

 9701 12:40:55.045375  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff

 9702 12:40:55.052655  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff

 9703 12:40:55.055818  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff

 9704 12:40:55.062256  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff

 9705 12:40:55.065469  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff

 9706 12:40:55.069218  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff

 9707 12:40:55.075755  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff

 9708 12:40:55.078745  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff

 9709 12:40:55.085639  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff

 9710 12:40:55.089022  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff

 9711 12:40:55.092056  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff

 9712 12:40:55.098806  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff

 9713 12:40:55.102481  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff

 9714 12:40:55.108722  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff

 9715 12:40:55.112051  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff

 9716 12:40:55.119027  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff

 9717 12:40:55.122183  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff

 9718 12:40:55.125190  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff

 9719 12:40:55.132380  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff

 9720 12:40:55.135530  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff

 9721 12:40:55.141989  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff

 9722 12:40:55.145634  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff

 9723 12:40:55.148698  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff

 9724 12:40:55.155698  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff

 9725 12:40:55.158842  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff

 9726 12:40:55.165155  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff

 9727 12:40:55.169096  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff

 9728 12:40:55.172261  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff

 9729 12:40:55.178663  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff

 9730 12:40:55.182096  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff

 9731 12:40:55.188791  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff

 9732 12:40:55.192067  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff

 9733 12:40:55.195629  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff

 9734 12:40:55.202368  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff

 9735 12:40:55.205368  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff

 9736 12:40:55.211860  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff

 9737 12:40:55.215367  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff

 9738 12:40:55.221751  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff

 9739 12:40:55.224931  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff

 9740 12:40:55.228690  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff

 9741 12:40:55.235290  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0

 9742 12:40:55.238441  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0

 9743 12:40:55.241791  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0

 9744 12:40:55.244993  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0

 9745 12:40:55.251747  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0

 9746 12:40:55.254829  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff

 9747 12:40:55.258167  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff

 9748 12:40:55.265199  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff

 9749 12:40:55.268600  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff

 9750 12:40:55.271552  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf

 9751 12:40:55.277985  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff

 9752 12:40:55.281790  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff

 9753 12:40:55.287959  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff

 9754 12:40:55.291652  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff

 9755 12:40:55.294810  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf

 9756 12:40:55.301203  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff

 9757 12:40:55.304971  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff

 9758 12:40:55.307801  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff

 9759 12:40:55.315062  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff

 9760 12:40:55.318339  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf

 9761 12:40:55.321320  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff

 9762 12:40:55.327870  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff

 9763 12:40:55.331004  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff

 9764 12:40:55.338081  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff

 9765 12:40:55.341255  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf

 9766 12:40:55.344453  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff

 9767 12:40:55.351660  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff

 9768 12:40:55.354768  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff

 9769 12:40:55.357864  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff

 9770 12:40:55.364458  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf

 9771 12:40:55.367859  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff

 9772 12:40:55.371147  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff

 9773 12:40:55.378127  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff

 9774 12:40:55.381364  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff

 9775 12:40:55.384607  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf

 9776 12:40:55.391577  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff

 9777 12:40:55.394828  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff

 9778 12:40:55.401352  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff

 9779 12:40:55.405006  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff

 9780 12:40:55.408160  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf

 9781 12:40:55.411325  INFO:    [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0

 9782 12:40:55.417968  INFO:    [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3

 9783 12:40:55.421008  INFO:    [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3

 9784 12:40:55.424526  INFO:    [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3

 9785 12:40:55.427926  INFO:    [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0

 9786 12:40:55.434283  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400

 9787 12:40:55.437849  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0

 9788 12:40:55.440904  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0

 9789 12:40:55.444126  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0

 9790 12:40:55.451388  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0

 9791 12:40:55.454663  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0

 9792 12:40:55.457983  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000

 9793 12:40:55.461198  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0

 9794 12:40:55.467789  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff

 9795 12:40:55.470820  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff

 9796 12:40:55.477924  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff

 9797 12:40:55.480921  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff

 9798 12:40:55.487321  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff

 9799 12:40:55.490526  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff

 9800 12:40:55.493835  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff

 9801 12:40:55.500744  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f

 9802 12:40:55.504009  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3

 9803 12:40:55.510412  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff

 9804 12:40:55.514235  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff

 9805 12:40:55.517295  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff

 9806 12:40:55.523724  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff

 9807 12:40:55.527173  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff

 9808 12:40:55.534035  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff

 9809 12:40:55.537791  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f

 9810 12:40:55.540661  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff

 9811 12:40:55.547656  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff

 9812 12:40:55.550809  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff

 9813 12:40:55.557333  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff

 9814 12:40:55.560720  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff

 9815 12:40:55.567156  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff

 9816 12:40:55.570891  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff

 9817 12:40:55.574074  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f

 9818 12:40:55.580532  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff

 9819 12:40:55.583813  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff

 9820 12:40:55.590567  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff

 9821 12:40:55.593904  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff

 9822 12:40:55.597148  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff

 9823 12:40:55.604106  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff

 9824 12:40:55.607308  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff

 9825 12:40:55.610485  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f

 9826 12:40:55.617104  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff

 9827 12:40:55.620689  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff

 9828 12:40:55.626953  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff

 9829 12:40:55.630096  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff

 9830 12:40:55.636989  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff

 9831 12:40:55.640043  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff

 9832 12:40:55.646994  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff

 9833 12:40:55.650640  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f

 9834 12:40:55.653366  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff

 9835 12:40:55.660353  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff

 9836 12:40:55.663686  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff

 9837 12:40:55.669960  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff

 9838 12:40:55.673152  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff

 9839 12:40:55.676953  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff

 9840 12:40:55.683350  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff

 9841 12:40:55.687054  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f

 9842 12:40:55.689985  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff

 9843 12:40:55.696654  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff

 9844 12:40:55.700135  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff

 9845 12:40:55.706312  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff

 9846 12:40:55.709612  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff

 9847 12:40:55.716597  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff

 9848 12:40:55.719735  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff

 9849 12:40:55.722933  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f

 9850 12:40:55.729655  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff

 9851 12:40:55.733337  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff

 9852 12:40:55.739668  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff

 9853 12:40:55.742717  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff

 9854 12:40:55.746287  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff

 9855 12:40:55.753046  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff

 9856 12:40:55.756611  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff

 9857 12:40:55.763228  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f

 9858 12:40:55.766385  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff

 9859 12:40:55.769805  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff

 9860 12:40:55.776301  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff

 9861 12:40:55.779354  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff

 9862 12:40:55.785940  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff

 9863 12:40:55.789161  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff

 9864 12:40:55.795985  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff

 9865 12:40:55.799692  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f

 9866 12:40:55.802709  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff

 9867 12:40:55.809448  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff

 9868 12:40:55.812637  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff

 9869 12:40:55.819061  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff

 9870 12:40:55.822790  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff

 9871 12:40:55.829362  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff

 9872 12:40:55.832467  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff

 9873 12:40:55.835533  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f

 9874 12:40:55.842702  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff

 9875 12:40:55.845913  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff

 9876 12:40:55.852102  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff

 9877 12:40:55.855699  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff

 9878 12:40:55.862328  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff

 9879 12:40:55.865395  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff

 9880 12:40:55.872540  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff

 9881 12:40:55.875647  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f

 9882 12:40:55.878945  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff

 9883 12:40:55.885247  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff

 9884 12:40:55.889069  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff

 9885 12:40:55.895524  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff

 9886 12:40:55.898740  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff

 9887 12:40:55.905509  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff

 9888 12:40:55.908575  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff

 9889 12:40:55.912385  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f

 9890 12:40:55.918714  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff

 9891 12:40:55.922097  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff

 9892 12:40:55.929007  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff

 9893 12:40:55.932308  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff

 9894 12:40:55.938679  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff

 9895 12:40:55.942311  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff

 9896 12:40:55.945674  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff

 9897 12:40:55.951694  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f

 9898 12:40:55.954935  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff

 9899 12:40:55.961558  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff

 9900 12:40:55.965225  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff

 9901 12:40:55.971994  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff

 9902 12:40:55.975039  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff

 9903 12:40:55.981847  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff

 9904 12:40:55.985043  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff

 9905 12:40:55.988795  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f

 9906 12:40:55.995229  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff

 9907 12:40:55.998414  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff

 9908 12:40:56.005466  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff

 9909 12:40:56.008538  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff

 9910 12:40:56.015226  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff

 9911 12:40:56.018352  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff

 9912 12:40:56.021448  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff

 9913 12:40:56.028540  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f

 9914 12:40:56.031567  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0

 9915 12:40:56.038154  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000

 9916 12:40:56.041330  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff

 9917 12:40:56.045018  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff

 9918 12:40:56.051426  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3

 9919 12:40:56.055080  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff

 9920 12:40:56.062078  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff

 9921 12:40:56.065036  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff

 9922 12:40:56.071998  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff

 9923 12:40:56.074875  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff

 9924 12:40:56.081333  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff

 9925 12:40:56.085078  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff

 9926 12:40:56.091401  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff

 9927 12:40:56.094552  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff

 9928 12:40:56.101084  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff

 9929 12:40:56.104358  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff

 9930 12:40:56.111404  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff

 9931 12:40:56.114492  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff

 9932 12:40:56.121377  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff

 9933 12:40:56.124544  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff

 9934 12:40:56.131331  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff

 9935 12:40:56.134461  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff

 9936 12:40:56.141045  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff

 9937 12:40:56.144236  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff

 9938 12:40:56.151274  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff

 9939 12:40:56.154640  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff

 9940 12:40:56.161200  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff

 9941 12:40:56.164485  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff

 9942 12:40:56.170792  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff

 9943 12:40:56.174336  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff

 9944 12:40:56.181062  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff

 9945 12:40:56.184155  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff

 9946 12:40:56.187825  INFO:    [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0

 9947 12:40:56.191106  INFO:    [APUAPC] vio 0

 9948 12:40:56.197290  INFO:    [APUAPC] set_apusys_ao_apc - SUCCESS!

 9949 12:40:56.200743  INFO:    [APUAPC] set_apusys_noc_dapc - SUCCESS!

 9950 12:40:56.203845  INFO:    [APUAPC] D0_APC_0: 0x400510

 9951 12:40:56.207619  INFO:    [APUAPC] D0_APC_1: 0x0

 9952 12:40:56.210923  INFO:    [APUAPC] D0_APC_2: 0x1540

 9953 12:40:56.214217  INFO:    [APUAPC] D0_APC_3: 0x0

 9954 12:40:56.217450  INFO:    [APUAPC] D1_APC_0: 0xffffffff

 9955 12:40:56.220475  INFO:    [APUAPC] D1_APC_1: 0xffffffff

 9956 12:40:56.224495  INFO:    [APUAPC] D1_APC_2: 0x3fffff

 9957 12:40:56.227487  INFO:    [APUAPC] D1_APC_3: 0x0

 9958 12:40:56.230713  INFO:    [APUAPC] D2_APC_0: 0xffffffff

 9959 12:40:56.233746  INFO:    [APUAPC] D2_APC_1: 0xffffffff

 9960 12:40:56.237829  INFO:    [APUAPC] D2_APC_2: 0x3fffff

 9961 12:40:56.240875  INFO:    [APUAPC] D2_APC_3: 0x0

 9962 12:40:56.244037  INFO:    [APUAPC] D3_APC_0: 0xffffffff

 9963 12:40:56.247211  INFO:    [APUAPC] D3_APC_1: 0xffffffff

 9964 12:40:56.250400  INFO:    [APUAPC] D3_APC_2: 0x3fffff

 9965 12:40:56.250521  INFO:    [APUAPC] D3_APC_3: 0x0

 9966 12:40:56.256849  INFO:    [APUAPC] D4_APC_0: 0xffffffff

 9967 12:40:56.260598  INFO:    [APUAPC] D4_APC_1: 0xffffffff

 9968 12:40:56.263604  INFO:    [APUAPC] D4_APC_2: 0x3fffff

 9969 12:40:56.263709  INFO:    [APUAPC] D4_APC_3: 0x0

 9970 12:40:56.267411  INFO:    [APUAPC] D5_APC_0: 0xffffffff

 9971 12:40:56.270116  INFO:    [APUAPC] D5_APC_1: 0xffffffff

 9972 12:40:56.273975  INFO:    [APUAPC] D5_APC_2: 0x3fffff

 9973 12:40:56.277117  INFO:    [APUAPC] D5_APC_3: 0x0

 9974 12:40:56.280222  INFO:    [APUAPC] D6_APC_0: 0xffffffff

 9975 12:40:56.283730  INFO:    [APUAPC] D6_APC_1: 0xffffffff

 9976 12:40:56.286847  INFO:    [APUAPC] D6_APC_2: 0x3fffff

 9977 12:40:56.290035  INFO:    [APUAPC] D6_APC_3: 0x0

 9978 12:40:56.293872  INFO:    [APUAPC] D7_APC_0: 0xffffffff

 9979 12:40:56.296682  INFO:    [APUAPC] D7_APC_1: 0xffffffff

 9980 12:40:56.300249  INFO:    [APUAPC] D7_APC_2: 0x3fffff

 9981 12:40:56.303636  INFO:    [APUAPC] D7_APC_3: 0x0

 9982 12:40:56.306655  INFO:    [APUAPC] D8_APC_0: 0xffffffff

 9983 12:40:56.309901  INFO:    [APUAPC] D8_APC_1: 0xffffffff

 9984 12:40:56.313809  INFO:    [APUAPC] D8_APC_2: 0x3fffff

 9985 12:40:56.317052  INFO:    [APUAPC] D8_APC_3: 0x0

 9986 12:40:56.320336  INFO:    [APUAPC] D9_APC_0: 0xffffffff

 9987 12:40:56.323442  INFO:    [APUAPC] D9_APC_1: 0xffffffff

 9988 12:40:56.327273  INFO:    [APUAPC] D9_APC_2: 0x3fffff

 9989 12:40:56.330270  INFO:    [APUAPC] D9_APC_3: 0x0

 9990 12:40:56.333398  INFO:    [APUAPC] D10_APC_0: 0xffffffff

 9991 12:40:56.337027  INFO:    [APUAPC] D10_APC_1: 0xffffffff

 9992 12:40:56.340036  INFO:    [APUAPC] D10_APC_2: 0x3fffff

 9993 12:40:56.343804  INFO:    [APUAPC] D10_APC_3: 0x0

 9994 12:40:56.347094  INFO:    [APUAPC] D11_APC_0: 0xffffffff

 9995 12:40:56.350203  INFO:    [APUAPC] D11_APC_1: 0xffffffff

 9996 12:40:56.353456  INFO:    [APUAPC] D11_APC_2: 0x3fffff

 9997 12:40:56.356819  INFO:    [APUAPC] D11_APC_3: 0x0

 9998 12:40:56.360465  INFO:    [APUAPC] D12_APC_0: 0xffffffff

 9999 12:40:56.363079  INFO:    [APUAPC] D12_APC_1: 0xffffffff

10000 12:40:56.367154  INFO:    [APUAPC] D12_APC_2: 0x3fffff

10001 12:40:56.370105  INFO:    [APUAPC] D12_APC_3: 0x0

10002 12:40:56.373189  INFO:    [APUAPC] D13_APC_0: 0xffffffff

10003 12:40:56.376436  INFO:    [APUAPC] D13_APC_1: 0xffffffff

10004 12:40:56.379741  INFO:    [APUAPC] D13_APC_2: 0x3fffff

10005 12:40:56.383376  INFO:    [APUAPC] D13_APC_3: 0x0

10006 12:40:56.386611  INFO:    [APUAPC] D14_APC_0: 0xffffffff

10007 12:40:56.389706  INFO:    [APUAPC] D14_APC_1: 0xffffffff

10008 12:40:56.393484  INFO:    [APUAPC] D14_APC_2: 0x3fffff

10009 12:40:56.396505  INFO:    [APUAPC] D14_APC_3: 0x0

10010 12:40:56.400323  INFO:    [APUAPC] D15_APC_0: 0xffffffff

10011 12:40:56.403312  INFO:    [APUAPC] D15_APC_1: 0xffffffff

10012 12:40:56.406361  INFO:    [APUAPC] D15_APC_2: 0x3fffff

10013 12:40:56.410094  INFO:    [APUAPC] D15_APC_3: 0x0

10014 12:40:56.413361  INFO:    [APUAPC] APC_CON: 0x4

10015 12:40:56.416440  INFO:    [NOCDAPC] D0_APC_0: 0x0

10016 12:40:56.419696  INFO:    [NOCDAPC] D0_APC_1: 0x0

10017 12:40:56.422989  INFO:    [NOCDAPC] D1_APC_0: 0x0

10018 12:40:56.426350  INFO:    [NOCDAPC] D1_APC_1: 0xfff

10019 12:40:56.426428  INFO:    [NOCDAPC] D2_APC_0: 0x0

10020 12:40:56.429939  INFO:    [NOCDAPC] D2_APC_1: 0xfff

10021 12:40:56.432940  INFO:    [NOCDAPC] D3_APC_0: 0x0

10022 12:40:56.436796  INFO:    [NOCDAPC] D3_APC_1: 0xfff

10023 12:40:56.439820  INFO:    [NOCDAPC] D4_APC_0: 0x0

10024 12:40:56.442852  INFO:    [NOCDAPC] D4_APC_1: 0xfff

10025 12:40:56.446608  INFO:    [NOCDAPC] D5_APC_0: 0x0

10026 12:40:56.449570  INFO:    [NOCDAPC] D5_APC_1: 0xfff

10027 12:40:56.452746  INFO:    [NOCDAPC] D6_APC_0: 0x0

10028 12:40:56.456677  INFO:    [NOCDAPC] D6_APC_1: 0xfff

10029 12:40:56.456787  INFO:    [NOCDAPC] D7_APC_0: 0x0

10030 12:40:56.459978  INFO:    [NOCDAPC] D7_APC_1: 0xfff

10031 12:40:56.463178  INFO:    [NOCDAPC] D8_APC_0: 0x0

10032 12:40:56.466378  INFO:    [NOCDAPC] D8_APC_1: 0xfff

10033 12:40:56.469534  INFO:    [NOCDAPC] D9_APC_0: 0x0

10034 12:40:56.473280  INFO:    [NOCDAPC] D9_APC_1: 0xfff

10035 12:40:56.476348  INFO:    [NOCDAPC] D10_APC_0: 0x0

10036 12:40:56.479560  INFO:    [NOCDAPC] D10_APC_1: 0xfff

10037 12:40:56.482781  INFO:    [NOCDAPC] D11_APC_0: 0x0

10038 12:40:56.486128  INFO:    [NOCDAPC] D11_APC_1: 0xfff

10039 12:40:56.489697  INFO:    [NOCDAPC] D12_APC_0: 0x0

10040 12:40:56.492917  INFO:    [NOCDAPC] D12_APC_1: 0xfff

10041 12:40:56.496454  INFO:    [NOCDAPC] D13_APC_0: 0x0

10042 12:40:56.496533  INFO:    [NOCDAPC] D13_APC_1: 0xfff

10043 12:40:56.499754  INFO:    [NOCDAPC] D14_APC_0: 0x0

10044 12:40:56.502892  INFO:    [NOCDAPC] D14_APC_1: 0xfff

10045 12:40:56.506292  INFO:    [NOCDAPC] D15_APC_0: 0x0

10046 12:40:56.510004  INFO:    [NOCDAPC] D15_APC_1: 0xfff

10047 12:40:56.512878  INFO:    [NOCDAPC] APC_CON: 0x4

10048 12:40:56.516521  INFO:    [APUAPC] set_apusys_apc done

10049 12:40:56.519671  INFO:    [DEVAPC] devapc_init done

10050 12:40:56.522796  INFO:    GICv3 without legacy support detected.

10051 12:40:56.525990  INFO:    ARM GICv3 driver initialized in EL3

10052 12:40:56.533114  INFO:    Maximum SPI INTID supported: 639

10053 12:40:56.536221  INFO:    BL31: Initializing runtime services

10054 12:40:56.543161  WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!

10055 12:40:56.543287  INFO:    SPM: enable CPC mode

10056 12:40:56.549834  INFO:    mcdi ready for mcusys-off-idle and system suspend

10057 12:40:56.552825  INFO:    BL31: Preparing for EL3 exit to normal world

10058 12:40:56.556493  INFO:    Entry point address = 0x80000000

10059 12:40:56.559599  INFO:    SPSR = 0x8

10060 12:40:56.565440  

10061 12:40:56.565552  

10062 12:40:56.565646  

10063 12:40:56.568630  Starting depthcharge on Spherion...

10064 12:40:56.568739  

10065 12:40:56.568846  Wipe memory regions:

10066 12:40:56.568937  

10067 12:40:56.569759  end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10068 12:40:56.569900  start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10069 12:40:56.570016  Setting prompt string to ['asurada:']
10070 12:40:56.570387  bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10071 12:40:56.571757  	[0x00000040000000, 0x00000054600000)

10072 12:40:56.693868  

10073 12:40:56.694037  	[0x00000054660000, 0x00000080000000)

10074 12:40:56.954686  

10075 12:40:56.954863  	[0x000000821a7280, 0x000000ffe64000)

10076 12:40:57.699534  

10077 12:40:57.699705  	[0x00000100000000, 0x00000240000000)

10078 12:40:59.589599  

10079 12:40:59.592535  Initializing XHCI USB controller at 0x11200000.

10080 12:41:00.631836  

10081 12:41:00.634962  [firmware-asurada-13885.B-collabora] Dec  7 2021 09:38:38

10082 12:41:00.635089  

10083 12:41:00.635187  

10084 12:41:00.635285  

10085 12:41:00.635608  Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10087 12:41:00.735994  asurada: tftpboot 192.168.201.1 10724866/tftp-deploy-7g8zvg_1/kernel/image.itb 10724866/tftp-deploy-7g8zvg_1/kernel/cmdline 

10088 12:41:00.736206  Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10089 12:41:00.736339  bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10090 12:41:00.740875  tftpboot 192.168.201.1 10724866/tftp-deploy-7g8zvg_1/kernel/image.itp-deploy-7g8zvg_1/kernel/cmdline 

10091 12:41:00.740991  

10092 12:41:00.741069  Waiting for link

10093 12:41:00.901079  

10094 12:41:00.901282  R8152: Initializing

10095 12:41:00.901380  

10096 12:41:00.904827  Version 9 (ocp_data = 6010)

10097 12:41:00.904969  

10098 12:41:00.907671  R8152: Done initializing

10099 12:41:00.907788  

10100 12:41:00.907883  Adding net device

10101 12:41:02.853703  

10102 12:41:02.853866  done.

10103 12:41:02.853937  

10104 12:41:02.854000  MAC: 00:e0:4c:78:7a:aa

10105 12:41:02.854061  

10106 12:41:02.856508  Sending DHCP discover... done.

10107 12:41:02.856597  

10108 12:41:02.860160  Waiting for reply... done.

10109 12:41:02.860250  

10110 12:41:02.863162  Sending DHCP request... done.

10111 12:41:02.863258  

10112 12:41:02.863354  Waiting for reply... done.

10113 12:41:02.863446  

10114 12:41:02.866815  My ip is 192.168.201.12

10115 12:41:02.866903  

10116 12:41:02.870053  The DHCP server ip is 192.168.201.1

10117 12:41:02.870140  

10118 12:41:02.873381  TFTP server IP predefined by user: 192.168.201.1

10119 12:41:02.873467  

10120 12:41:02.879873  Bootfile predefined by user: 10724866/tftp-deploy-7g8zvg_1/kernel/image.itb

10121 12:41:02.879987  

10122 12:41:02.883130  Sending tftp read request... done.

10123 12:41:02.883251  

10124 12:41:02.886437  Waiting for the transfer... 

10125 12:41:02.886532  

10126 12:41:03.190467  00000000 ################################################################

10127 12:41:03.190625  

10128 12:41:03.510018  00080000 ################################################################

10129 12:41:03.510164  

10130 12:41:03.821730  00100000 ################################################################

10131 12:41:03.821879  

10132 12:41:04.127701  00180000 ################################################################

10133 12:41:04.127884  

10134 12:41:04.440755  00200000 ################################################################

10135 12:41:04.440954  

10136 12:41:04.759030  00280000 ################################################################

10137 12:41:04.759207  

10138 12:41:05.099746  00300000 ################################################################

10139 12:41:05.099900  

10140 12:41:05.407720  00380000 ################################################################

10141 12:41:05.407879  

10142 12:41:05.719836  00400000 ################################################################

10143 12:41:05.720035  

10144 12:41:06.036243  00480000 ################################################################

10145 12:41:06.036392  

10146 12:41:06.344645  00500000 ################################################################

10147 12:41:06.344839  

10148 12:41:06.650744  00580000 ################################################################

10149 12:41:06.650896  

10150 12:41:06.959367  00600000 ################################################################

10151 12:41:06.959540  

10152 12:41:07.272294  00680000 ################################################################

10153 12:41:07.272471  

10154 12:41:07.578360  00700000 ################################################################

10155 12:41:07.578538  

10156 12:41:07.879793  00780000 ################################################################

10157 12:41:07.879942  

10158 12:41:08.191235  00800000 ################################################################

10159 12:41:08.191415  

10160 12:41:08.499149  00880000 ################################################################

10161 12:41:08.499333  

10162 12:41:08.811664  00900000 ################################################################

10163 12:41:08.811839  

10164 12:41:09.119793  00980000 ################################################################

10165 12:41:09.119971  

10166 12:41:09.427417  00a00000 ################################################################

10167 12:41:09.427563  

10168 12:41:09.728854  00a80000 ################################################################

10169 12:41:09.729003  

10170 12:41:10.042915  00b00000 ################################################################

10171 12:41:10.043054  

10172 12:41:10.354533  00b80000 ################################################################

10173 12:41:10.354701  

10174 12:41:10.669878  00c00000 ################################################################

10175 12:41:10.670043  

10176 12:41:10.982047  00c80000 ################################################################

10177 12:41:10.982199  

10178 12:41:11.296935  00d00000 ################################################################

10179 12:41:11.297088  

10180 12:41:11.604200  00d80000 ################################################################

10181 12:41:11.604355  

10182 12:41:11.934044  00e00000 ################################################################

10183 12:41:11.934198  

10184 12:41:12.272843  00e80000 ################################################################

10185 12:41:12.273024  

10186 12:41:12.613261  00f00000 ################################################################

10187 12:41:12.613421  

10188 12:41:12.950781  00f80000 ################################################################

10189 12:41:12.950927  

10190 12:41:13.289026  01000000 ################################################################

10191 12:41:13.289172  

10192 12:41:13.629211  01080000 ################################################################

10193 12:41:13.629421  

10194 12:41:13.972652  01100000 ################################################################

10195 12:41:13.972824  

10196 12:41:14.317004  01180000 ################################################################

10197 12:41:14.317177  

10198 12:41:14.653532  01200000 ################################################################

10199 12:41:14.653674  

10200 12:41:14.990904  01280000 ################################################################

10201 12:41:14.991047  

10202 12:41:15.328656  01300000 ################################################################

10203 12:41:15.328840  

10204 12:41:15.660581  01380000 ################################################################

10205 12:41:15.660724  

10206 12:41:15.995992  01400000 ################################################################

10207 12:41:15.996152  

10208 12:41:16.334178  01480000 ################################################################

10209 12:41:16.334343  

10210 12:41:16.666610  01500000 ################################################################

10211 12:41:16.666790  

10212 12:41:17.007675  01580000 ################################################################

10213 12:41:17.007819  

10214 12:41:17.345455  01600000 ################################################################

10215 12:41:17.345595  

10216 12:41:17.689322  01680000 ################################################################

10217 12:41:17.689459  

10218 12:41:18.027784  01700000 ################################################################

10219 12:41:18.027940  

10220 12:41:18.367324  01780000 ################################################################

10221 12:41:18.367497  

10222 12:41:18.704790  01800000 ################################################################

10223 12:41:18.704941  

10224 12:41:19.054693  01880000 ################################################################

10225 12:41:19.054841  

10226 12:41:19.394294  01900000 ################################################################

10227 12:41:19.394449  

10228 12:41:19.736146  01980000 ################################################################

10229 12:41:19.736323  

10230 12:41:20.072263  01a00000 ################################################################

10231 12:41:20.072414  

10232 12:41:20.289737  01a80000 ########################################## done.

10233 12:41:20.289878  

10234 12:41:20.293504  The bootfile was 28130350 bytes long.

10235 12:41:20.293595  

10236 12:41:20.296787  Sending tftp read request... done.

10237 12:41:20.296882  

10238 12:41:20.296954  Waiting for the transfer... 

10239 12:41:20.297015  

10240 12:41:20.300012  00000000 # done.

10241 12:41:20.300088  

10242 12:41:20.306296  Command line loaded dynamically from TFTP file: 10724866/tftp-deploy-7g8zvg_1/kernel/cmdline

10243 12:41:20.306381  

10244 12:41:20.326715  The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10724866/extract-nfsrootfs-176kw0_e,tcp,hard ip=dhcp tftpserverip=192.168.201.1

10245 12:41:20.326832  

10246 12:41:20.329898  Loading FIT.

10247 12:41:20.329973  

10248 12:41:20.333122  Image ramdisk-1 has 17639016 bytes.

10249 12:41:20.333198  

10250 12:41:20.333260  Image fdt-1 has 46924 bytes.

10251 12:41:20.333320  

10252 12:41:20.336397  Image kernel-1 has 10442380 bytes.

10253 12:41:20.336468  

10254 12:41:20.346202  Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion

10255 12:41:20.346285  

10256 12:41:20.362969  Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192

10257 12:41:20.363083  

10258 12:41:20.369994  Choosing best match conf-1 for compat google,spherion-rev2.

10259 12:41:20.373147  

10260 12:41:20.378071  Connected to device vid:did:rid of 1ae0:0028:00

10261 12:41:20.386278  

10262 12:41:20.389875  tpm_get_response: command 0x17b, return code 0x0

10263 12:41:20.389960  

10264 12:41:20.393031  ec_init: CrosEC protocol v3 supported (256, 248)

10265 12:41:20.396724  

10266 12:41:20.400069  tpm_cleanup: add release locality here.

10267 12:41:20.400149  

10268 12:41:20.400214  Shutting down all USB controllers.

10269 12:41:20.403345  

10270 12:41:20.403418  Removing current net device

10271 12:41:20.403483  

10272 12:41:20.409882  Exiting depthcharge with code 4 at timestamp: 53123379

10273 12:41:20.409959  

10274 12:41:20.413781  LZMA decompressing kernel-1 to 0x821a6718

10275 12:41:20.413859  

10276 12:41:20.416774  LZMA decompressing kernel-1 to 0x40000000

10277 12:41:21.727119  

10278 12:41:21.727277  jumping to kernel

10279 12:41:21.727694  end: 2.2.4 bootloader-commands (duration 00:00:25) [common]
10280 12:41:21.727795  start: 2.2.5 auto-login-action (timeout 00:04:00) [common]
10281 12:41:21.727875  Setting prompt string to ['Linux version [0-9]']
10282 12:41:21.727943  Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10283 12:41:21.728014  auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10284 12:41:21.810135  

10285 12:41:21.813695  [    0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]

10286 12:41:21.816954  start: 2.2.5.1 login-action (timeout 00:04:00) [common]
10287 12:41:21.817048  The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10288 12:41:21.817154  Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10289 12:41:21.817229  Using line separator: #'\n'#
10290 12:41:21.817309  No login prompt set.
10291 12:41:21.817373  Parsing kernel messages
10292 12:41:21.817438  ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10293 12:41:21.817553  [login-action] Waiting for messages, (timeout 00:04:00)
10294 12:41:21.836425  [    0.000000] Linux version 6.1.31 (KernelCI@build-j35827-arm64-gcc-10-defconfig-arm64-chromebook-fwl9s) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jun 14 12:30:40 UTC 2023

10295 12:41:21.840208  [    0.000000] random: crng init done

10296 12:41:21.843286  [    0.000000] Machine model: Google Spherion (rev0 - 3)

10297 12:41:21.846511  [    0.000000] efi: UEFI not found.

10298 12:41:21.856528  [    0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB

10299 12:41:21.863023  [    0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool

10300 12:41:21.872952  [    0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB

10301 12:41:21.883406  [    0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool

10302 12:41:21.889885  [    0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')

10303 12:41:21.892969  [    0.000000] printk: bootconsole [mtk8250] enabled

10304 12:41:21.901924  [    0.000000] NUMA: No NUMA configuration found

10305 12:41:21.908418  [    0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]

10306 12:41:21.914899  [    0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]

10307 12:41:21.915005  [    0.000000] Zone ranges:

10308 12:41:21.921675  [    0.000000]   DMA      [mem 0x0000000040000000-0x00000000ffffffff]

10309 12:41:21.924592  [    0.000000]   DMA32    empty

10310 12:41:21.931208  [    0.000000]   Normal   [mem 0x0000000100000000-0x000000023fffffff]

10311 12:41:21.934524  [    0.000000] Movable zone start for each node

10312 12:41:21.937745  [    0.000000] Early memory node ranges

10313 12:41:21.944372  [    0.000000]   node   0: [mem 0x0000000040000000-0x000000004fffffff]

10314 12:41:21.951241  [    0.000000]   node   0: [mem 0x0000000050000000-0x00000000528fffff]

10315 12:41:21.958058  [    0.000000]   node   0: [mem 0x0000000052900000-0x00000000545fffff]

10316 12:41:21.964638  [    0.000000]   node   0: [mem 0x0000000054700000-0x00000000ffdfffff]

10317 12:41:21.971242  [    0.000000]   node   0: [mem 0x0000000100000000-0x000000023fffffff]

10318 12:41:21.977688  [    0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]

10319 12:41:22.034173  [    0.000000] On node 0, zone DMA: 256 pages in unavailable ranges

10320 12:41:22.040757  [    0.000000] On node 0, zone Normal: 512 pages in unavailable ranges

10321 12:41:22.047238  [    0.000000] cma: Reserved 32 MiB at 0x00000000fde00000

10322 12:41:22.050530  [    0.000000] psci: probing for conduit method from DT.

10323 12:41:22.057517  [    0.000000] psci: PSCIv1.1 detected in firmware.

10324 12:41:22.060525  [    0.000000] psci: Using standard PSCI v0.2 function IDs

10325 12:41:22.067613  [    0.000000] psci: MIGRATE_INFO_TYPE not supported.

10326 12:41:22.070899  [    0.000000] psci: SMC Calling Convention v1.2

10327 12:41:22.077318  [    0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016

10328 12:41:22.080606  [    0.000000] Detected VIPT I-cache on CPU0

10329 12:41:22.087222  [    0.000000] CPU features: detected: GIC system register CPU interface

10330 12:41:22.094265  [    0.000000] CPU features: detected: Virtualization Host Extensions

10331 12:41:22.101059  [    0.000000] CPU features: kernel page table isolation forced ON by KASLR

10332 12:41:22.107154  [    0.000000] CPU features: detected: Kernel page table isolation (KPTI)

10333 12:41:22.114082  [    0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009

10334 12:41:22.120275  [    0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923

10335 12:41:22.127493  [    0.000000] alternatives: applying boot alternatives

10336 12:41:22.130657  [    0.000000] Fallback order for Node 0: 0 

10337 12:41:22.136995  [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 2063616

10338 12:41:22.140937  [    0.000000] Policy zone: Normal

10339 12:41:22.163489  [    0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10724866/extract-nfsrootfs-176kw0_e,tcp,hard ip=dhcp tftpserverip=192.168.201.1

10340 12:41:22.173263  <5>[    0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.

10341 12:41:22.184545  <6>[    0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)

10342 12:41:22.194384  <6>[    0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)

10343 12:41:22.201249  <6>[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off

10344 12:41:22.204423  <6>[    0.000000] software IO TLB: area num 8.

10345 12:41:22.261189  <6>[    0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)

10346 12:41:22.410157  <6>[    0.000000] Memory: 7953932K/8385536K available (17984K kernel code, 4098K rwdata, 15868K rodata, 8384K init, 615K bss, 398836K reserved, 32768K cma-reserved)

10347 12:41:22.417012  <6>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1

10348 12:41:22.423622  <6>[    0.000000] rcu: Preemptible hierarchical RCU implementation.

10349 12:41:22.427322  <6>[    0.000000] rcu: 	RCU event tracing is enabled.

10350 12:41:22.433499  <6>[    0.000000] rcu: 	RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.

10351 12:41:22.440294  <6>[    0.000000] 	Trampoline variant of Tasks RCU enabled.

10352 12:41:22.443513  <6>[    0.000000] 	Tracing variant of Tasks RCU enabled.

10353 12:41:22.453272  <6>[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.

10354 12:41:22.460384  <6>[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8

10355 12:41:22.463747  <6>[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0

10356 12:41:22.470966  <6>[    0.000000] GICv3: GIC: Using split EOI/Deactivate mode

10357 12:41:22.474382  <6>[    0.000000] GICv3: 608 SPIs implemented

10358 12:41:22.481373  <6>[    0.000000] GICv3: 0 Extended SPIs implemented

10359 12:41:22.484584  <6>[    0.000000] Root IRQ handler: gic_handle_irq

10360 12:41:22.487730  <6>[    0.000000] GICv3: GICv3 features: 16 PPIs

10361 12:41:22.497538  <6>[    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000

10362 12:41:22.507668  <6>[    0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }

10363 12:41:22.520898  <6>[    0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }

10364 12:41:22.527734  <6>[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.

10365 12:41:22.536548  <6>[    0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).

10366 12:41:22.550431  <6>[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns

10367 12:41:22.556986  <6>[    0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns

10368 12:41:22.563371  <6>[    0.009182] Console: colour dummy device 80x25

10369 12:41:22.573309  <6>[    0.013907] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)

10370 12:41:22.576533  <6>[    0.024350] pid_max: default: 32768 minimum: 301

10371 12:41:22.582991  <6>[    0.029223] LSM: Security Framework initializing

10372 12:41:22.589959  <6>[    0.034163] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)

10373 12:41:22.600259  <6>[    0.042025] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)

10374 12:41:22.607059  <6>[    0.051451] cblist_init_generic: Setting adjustable number of callback queues.

10375 12:41:22.613479  <6>[    0.058904] cblist_init_generic: Setting shift to 3 and lim to 1.

10376 12:41:22.619750  <6>[    0.065242] cblist_init_generic: Setting shift to 3 and lim to 1.

10377 12:41:22.626373  <6>[    0.071649] rcu: Hierarchical SRCU implementation.

10378 12:41:22.629590  <6>[    0.076663] rcu: 	Max phase no-delay instances is 1000.

10379 12:41:22.637639  <6>[    0.083708] EFI services will not be available.

10380 12:41:22.640790  <6>[    0.088708] smp: Bringing up secondary CPUs ...

10381 12:41:22.650268  <6>[    0.093787] Detected VIPT I-cache on CPU1

10382 12:41:22.656935  <6>[    0.093857] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000

10383 12:41:22.663724  <6>[    0.093890] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]

10384 12:41:22.666869  <6>[    0.094228] Detected VIPT I-cache on CPU2

10385 12:41:22.673775  <6>[    0.094277] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000

10386 12:41:22.680135  <6>[    0.094293] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]

10387 12:41:22.686770  <6>[    0.094552] Detected VIPT I-cache on CPU3

10388 12:41:22.693010  <6>[    0.094600] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000

10389 12:41:22.699622  <6>[    0.094614] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]

10390 12:41:22.702863  <6>[    0.094918] CPU features: detected: Spectre-v4

10391 12:41:22.709733  <6>[    0.094925] CPU features: detected: Spectre-BHB

10392 12:41:22.713015  <6>[    0.094930] Detected PIPT I-cache on CPU4

10393 12:41:22.719641  <6>[    0.094990] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000

10394 12:41:22.726430  <6>[    0.095006] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]

10395 12:41:22.733117  <6>[    0.095299] Detected PIPT I-cache on CPU5

10396 12:41:22.739793  <6>[    0.095367] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000

10397 12:41:22.746478  <6>[    0.095383] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]

10398 12:41:22.749481  <6>[    0.095665] Detected PIPT I-cache on CPU6

10399 12:41:22.756139  <6>[    0.095733] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000

10400 12:41:22.762917  <6>[    0.095749] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]

10401 12:41:22.769401  <6>[    0.096049] Detected PIPT I-cache on CPU7

10402 12:41:22.776476  <6>[    0.096116] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000

10403 12:41:22.782835  <6>[    0.096132] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]

10404 12:41:22.786094  <6>[    0.096179] smp: Brought up 1 node, 8 CPUs

10405 12:41:22.792590  <6>[    0.237543] SMP: Total of 8 processors activated.

10406 12:41:22.795774  <6>[    0.242464] CPU features: detected: 32-bit EL0 Support

10407 12:41:22.806362  <6>[    0.247828] CPU features: detected: Data cache clean to the PoU not required for I/D coherence

10408 12:41:22.812542  <6>[    0.256628] CPU features: detected: Common not Private translations

10409 12:41:22.815727  <6>[    0.263104] CPU features: detected: CRC32 instructions

10410 12:41:22.822812  <6>[    0.268455] CPU features: detected: RCpc load-acquire (LDAPR)

10411 12:41:22.829344  <6>[    0.274415] CPU features: detected: LSE atomic instructions

10412 12:41:22.835989  <6>[    0.280232] CPU features: detected: Privileged Access Never

10413 12:41:22.839029  <6>[    0.286012] CPU features: detected: RAS Extension Support

10414 12:41:22.848773  <6>[    0.291620] CPU features: detected: Speculative Store Bypassing Safe (SSBS)

10415 12:41:22.852462  <6>[    0.298884] CPU: All CPU(s) started at EL2

10416 12:41:22.859126  <6>[    0.303227] alternatives: applying system-wide alternatives

10417 12:41:22.867504  <6>[    0.313964] devtmpfs: initialized

10418 12:41:22.880290  <6>[    0.322882] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns

10419 12:41:22.889921  <6>[    0.332844] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)

10420 12:41:22.896638  <6>[    0.340869] pinctrl core: initialized pinctrl subsystem

10421 12:41:22.899742  <6>[    0.347662] DMI not present or invalid.

10422 12:41:22.906936  <6>[    0.352081] NET: Registered PF_NETLINK/PF_ROUTE protocol family

10423 12:41:22.916495  <6>[    0.358965] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations

10424 12:41:22.923479  <6>[    0.366542] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations

10425 12:41:22.933240  <6>[    0.374760] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations

10426 12:41:22.936463  <6>[    0.383001] audit: initializing netlink subsys (disabled)

10427 12:41:22.946487  <5>[    0.388695] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1

10428 12:41:22.952675  <6>[    0.389511] thermal_sys: Registered thermal governor 'step_wise'

10429 12:41:22.959315  <6>[    0.396662] thermal_sys: Registered thermal governor 'power_allocator'

10430 12:41:22.962914  <6>[    0.402918] cpuidle: using governor menu

10431 12:41:22.969175  <6>[    0.413883] NET: Registered PF_QIPCRTR protocol family

10432 12:41:22.976405  <6>[    0.419415] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.

10433 12:41:22.979286  <6>[    0.426516] ASID allocator initialised with 32768 entries

10434 12:41:22.987040  <6>[    0.433131] Serial: AMBA PL011 UART driver

10435 12:41:22.996175  <4>[    0.442172] Trying to register duplicate clock ID: 134

10436 12:41:23.053253  <6>[    0.502397] KASLR enabled

10437 12:41:23.067176  <6>[    0.510197] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages

10438 12:41:23.074205  <6>[    0.517209] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page

10439 12:41:23.080476  <6>[    0.523696] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages

10440 12:41:23.087146  <6>[    0.530700] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page

10441 12:41:23.093989  <6>[    0.537185] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages

10442 12:41:23.100533  <6>[    0.544188] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page

10443 12:41:23.107289  <6>[    0.550675] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages

10444 12:41:23.113798  <6>[    0.557677] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page

10445 12:41:23.117077  <6>[    0.565348] ACPI: Interpreter disabled.

10446 12:41:23.125736  <6>[    0.571783] iommu: Default domain type: Translated 

10447 12:41:23.132084  <6>[    0.576898] iommu: DMA domain TLB invalidation policy: strict mode 

10448 12:41:23.135825  <5>[    0.583562] SCSI subsystem initialized

10449 12:41:23.142363  <6>[    0.587722] usbcore: registered new interface driver usbfs

10450 12:41:23.148773  <6>[    0.593453] usbcore: registered new interface driver hub

10451 12:41:23.152022  <6>[    0.599002] usbcore: registered new device driver usb

10452 12:41:23.159035  <6>[    0.605137] pps_core: LinuxPPS API ver. 1 registered

10453 12:41:23.169033  <6>[    0.610329] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>

10454 12:41:23.172487  <6>[    0.619674] PTP clock support registered

10455 12:41:23.175497  <6>[    0.623912] EDAC MC: Ver: 3.0.0

10456 12:41:23.183065  <6>[    0.629126] FPGA manager framework

10457 12:41:23.186456  <6>[    0.632810] Advanced Linux Sound Architecture Driver Initialized.

10458 12:41:23.189938  <6>[    0.639576] vgaarb: loaded

10459 12:41:23.196946  <6>[    0.642752] clocksource: Switched to clocksource arch_sys_counter

10460 12:41:23.203232  <5>[    0.649202] VFS: Disk quotas dquot_6.6.0

10461 12:41:23.209967  <6>[    0.653386] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)

10462 12:41:23.213088  <6>[    0.660575] pnp: PnP ACPI: disabled

10463 12:41:23.220943  <6>[    0.667281] NET: Registered PF_INET protocol family

10464 12:41:23.231221  <6>[    0.672869] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)

10465 12:41:23.242785  <6>[    0.685140] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)

10466 12:41:23.252715  <6>[    0.693955] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)

10467 12:41:23.258975  <6>[    0.701930] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)

10468 12:41:23.265418  <6>[    0.710629] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)

10469 12:41:23.277772  <6>[    0.720372] TCP: Hash tables configured (established 65536 bind 65536)

10470 12:41:23.284061  <6>[    0.727229] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)

10471 12:41:23.291154  <6>[    0.734423] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)

10472 12:41:23.297713  <6>[    0.742132] NET: Registered PF_UNIX/PF_LOCAL protocol family

10473 12:41:23.303988  <6>[    0.748231] RPC: Registered named UNIX socket transport module.

10474 12:41:23.307713  <6>[    0.754381] RPC: Registered udp transport module.

10475 12:41:23.314192  <6>[    0.759312] RPC: Registered tcp transport module.

10476 12:41:23.320666  <6>[    0.764241] RPC: Registered tcp NFSv4.1 backchannel transport module.

10477 12:41:23.324097  <6>[    0.770907] PCI: CLS 0 bytes, default 64

10478 12:41:23.327307  <6>[    0.775304] Unpacking initramfs...

10479 12:41:23.344493  <6>[    0.787325] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available

10480 12:41:23.354763  <6>[    0.795982] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available

10481 12:41:23.357806  <6>[    0.804838] kvm [1]: IPA Size Limit: 40 bits

10482 12:41:23.364278  <6>[    0.809361] kvm [1]: GICv3: no GICV resource entry

10483 12:41:23.367552  <6>[    0.814380] kvm [1]: disabling GICv2 emulation

10484 12:41:23.374664  <6>[    0.819068] kvm [1]: GIC system register CPU interface enabled

10485 12:41:23.377625  <6>[    0.825225] kvm [1]: vgic interrupt IRQ18

10486 12:41:23.384771  <6>[    0.830830] kvm [1]: VHE mode initialized successfully

10487 12:41:23.391600  <5>[    0.837263] Initialise system trusted keyrings

10488 12:41:23.397814  <6>[    0.842072] workingset: timestamp_bits=42 max_order=21 bucket_order=0

10489 12:41:23.406665  <6>[    0.852314] squashfs: version 4.0 (2009/01/31) Phillip Lougher

10490 12:41:23.412981  <5>[    0.858718] NFS: Registering the id_resolver key type

10491 12:41:23.416091  <5>[    0.864022] Key type id_resolver registered

10492 12:41:23.423225  <5>[    0.868437] Key type id_legacy registered

10493 12:41:23.429828  <6>[    0.872720] nfs4filelayout_init: NFSv4 File Layout Driver Registering...

10494 12:41:23.436175  <6>[    0.879646] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...

10495 12:41:23.442770  <6>[    0.887364] 9p: Installing v9fs 9p2000 file system support

10496 12:41:23.478415  <5>[    0.924745] Key type asymmetric registered

10497 12:41:23.481650  <5>[    0.929078] Asymmetric key parser 'x509' registered

10498 12:41:23.491901  <6>[    0.934237] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)

10499 12:41:23.494919  <6>[    0.941868] io scheduler mq-deadline registered

10500 12:41:23.498686  <6>[    0.946635] io scheduler kyber registered

10501 12:41:23.517532  <6>[    0.963783] EINJ: ACPI disabled.

10502 12:41:23.550062  <4>[    0.989591] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10503 12:41:23.559685  <4>[    1.000209] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10504 12:41:23.575147  <6>[    1.021309] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled

10505 12:41:23.583459  <6>[    1.029432] printk: console [ttyS0] disabled

10506 12:41:23.611344  <6>[    1.054083] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2

10507 12:41:23.618020  <6>[    1.063557] printk: console [ttyS0] enabled

10508 12:41:23.621284  <6>[    1.063557] printk: console [ttyS0] enabled

10509 12:41:23.627735  <6>[    1.072452] printk: bootconsole [mtk8250] disabled

10510 12:41:23.631626  <6>[    1.072452] printk: bootconsole [mtk8250] disabled

10511 12:41:23.638116  <6>[    1.083819] SuperH (H)SCI(F) driver initialized

10512 12:41:23.641533  <6>[    1.089141] msm_serial: driver initialized

10513 12:41:23.655107  <6>[    1.098230] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000

10514 12:41:23.665653  <6>[    1.106780] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000

10515 12:41:23.671942  <6>[    1.115322] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000

10516 12:41:23.682254  <6>[    1.123950] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000

10517 12:41:23.688740  <6>[    1.132657] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000

10518 12:41:23.698231  <6>[    1.141378] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000

10519 12:41:23.708435  <6>[    1.149922] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000

10520 12:41:23.715264  <6>[    1.158736] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000

10521 12:41:23.725065  <6>[    1.167290] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000

10522 12:41:23.736934  <6>[    1.183322] loop: module loaded

10523 12:41:23.743566  <6>[    1.189374] vgpu11_sshub: Bringing 400000uV into 575000-575000uV

10524 12:41:23.766518  <4>[    1.212980] mtk-pmic-keys: Failed to locate of_node [id: -1]

10525 12:41:23.773649  <6>[    1.219786] megasas: 07.719.03.00-rc1

10526 12:41:23.783349  <6>[    1.229374] spi-nor spi2.0: w25q64jwm (8192 Kbytes)

10527 12:41:23.796050  <6>[    1.242138] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2

10528 12:41:23.812738  <6>[    1.258852] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)

10529 12:41:23.869044  <6>[    1.308919] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9

10530 12:41:24.053011  <6>[    1.499269] Freeing initrd memory: 17220K

10531 12:41:24.063699  <6>[    1.509743] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz

10532 12:41:24.074723  <6>[    1.520705] tun: Universal TUN/TAP device driver, 1.6

10533 12:41:24.077945  <6>[    1.526803] thunder_xcv, ver 1.0

10534 12:41:24.081294  <6>[    1.530297] thunder_bgx, ver 1.0

10535 12:41:24.084398  <6>[    1.533791] nicpf, ver 1.0

10536 12:41:24.094696  <6>[    1.537839] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version

10537 12:41:24.098301  <6>[    1.545315] hns3: Copyright (c) 2017 Huawei Corporation.

10538 12:41:24.101373  <6>[    1.550901] hclge is initializing

10539 12:41:24.108376  <6>[    1.554478] e1000: Intel(R) PRO/1000 Network Driver

10540 12:41:24.114894  <6>[    1.559607] e1000: Copyright (c) 1999-2006 Intel Corporation.

10541 12:41:24.118663  <6>[    1.565619] e1000e: Intel(R) PRO/1000 Network Driver

10542 12:41:24.124946  <6>[    1.570834] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.

10543 12:41:24.132088  <6>[    1.577021] igb: Intel(R) Gigabit Ethernet Network Driver

10544 12:41:24.138768  <6>[    1.582671] igb: Copyright (c) 2007-2014 Intel Corporation.

10545 12:41:24.145419  <6>[    1.588507] igbvf: Intel(R) Gigabit Virtual Function Network Driver

10546 12:41:24.148520  <6>[    1.595025] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.

10547 12:41:24.155050  <6>[    1.601486] sky2: driver version 1.30

10548 12:41:24.162156  <6>[    1.606513] VFIO - User Level meta-driver version: 0.3

10549 12:41:24.168414  <6>[    1.614804] usbcore: registered new interface driver usb-storage

10550 12:41:24.175055  <6>[    1.621244] usbcore: registered new device driver onboard-usb-hub

10551 12:41:24.184151  <6>[    1.630380] mt6397-rtc mt6359-rtc: registered as rtc0

10552 12:41:24.193961  <6>[    1.635846] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-14T12:41:09 UTC (1686746469)

10553 12:41:24.197865  <6>[    1.645420] i2c_dev: i2c /dev entries driver

10554 12:41:24.214081  <6>[    1.657267] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)

10555 12:41:24.221355  <6>[    1.667463] sdhci: Secure Digital Host Controller Interface driver

10556 12:41:24.227810  <6>[    1.673901] sdhci: Copyright(c) Pierre Ossman

10557 12:41:24.234208  <6>[    1.679327] Synopsys Designware Multimedia Card Interface Driver

10558 12:41:24.237681  <6>[    1.685932] mmc0: CQHCI version 5.10

10559 12:41:24.244286  <6>[    1.686506] sdhci-pltfm: SDHCI platform and OF driver helper

10560 12:41:24.251688  <6>[    1.697881] ledtrig-cpu: registered to indicate activity on CPUs

10561 12:41:24.261981  <6>[    1.705196] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000

10562 12:41:24.265517  <6>[    1.712616] usbcore: registered new interface driver usbhid

10563 12:41:24.272357  <6>[    1.718450] usbhid: USB HID core driver

10564 12:41:24.278613  <6>[    1.722701] spi_master spi0: will run message pump with realtime priority

10565 12:41:24.326310  <6>[    1.765939] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0

10566 12:41:24.334767  <6>[    1.780592] mmc0: Command Queue Engine enabled

10567 12:41:24.348509  <6>[    1.781435] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1

10568 12:41:24.354889  <6>[    1.785325] mmc0: new HS400 Enhanced strobe MMC card at address 0001

10569 12:41:24.358123  <6>[    1.801627] cros-ec-spi spi0.0: Chrome EC device registered

10570 12:41:24.365060  <6>[    1.805875] mmcblk0: mmc0:0001 DA4128 116 GiB 

10571 12:41:24.374405  <6>[    1.820359]  mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12

10572 12:41:24.381743  <6>[    1.827943] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB 

10573 12:41:24.391360  <6>[    1.829480] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)

10574 12:41:24.394631  <6>[    1.833834] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB 

10575 12:41:24.401776  <6>[    1.844647] NET: Registered PF_PACKET protocol family

10576 12:41:24.408330  <6>[    1.848373] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)

10577 12:41:24.411676  <6>[    1.853130] 9pnet: Installing 9P2000 support

10578 12:41:24.418562  <5>[    1.864107] Key type dns_resolver registered

10579 12:41:24.421723  <6>[    1.869246] registered taskstats version 1

10580 12:41:24.428180  <5>[    1.873687] Loading compiled-in X.509 certificates

10581 12:41:24.461056  <4>[    1.900561] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10582 12:41:24.471138  <4>[    1.911255] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10583 12:41:24.481317  <3>[    1.924163] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)

10584 12:41:24.493394  <6>[    1.939690] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102

10585 12:41:24.500489  <6>[    1.946434] xhci-mtk 11200000.usb: xHCI Host Controller

10586 12:41:24.507150  <6>[    1.951938] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1

10587 12:41:24.516697  <6>[    1.959791] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010

10588 12:41:24.523789  <6>[    1.969230] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000

10589 12:41:24.529996  <6>[    1.975455] xhci-mtk 11200000.usb: xHCI Host Controller

10590 12:41:24.536593  <6>[    1.980953] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2

10591 12:41:24.543568  <6>[    1.988621] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed

10592 12:41:24.550130  <6>[    1.996495] hub 1-0:1.0: USB hub found

10593 12:41:24.553454  <6>[    2.000533] hub 1-0:1.0: 1 port detected

10594 12:41:24.560326  <6>[    2.004896] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.

10595 12:41:24.567609  <6>[    2.013715] hub 2-0:1.0: USB hub found

10596 12:41:24.571296  <6>[    2.017751] hub 2-0:1.0: 1 port detected

10597 12:41:24.578745  <6>[    2.025053] mtk-msdc 11f70000.mmc: Got CD GPIO

10598 12:41:24.600584  <6>[    2.043445] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()

10599 12:41:24.606976  <6>[    2.051502] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()

10600 12:41:24.616939  <4>[    2.059469] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW

10601 12:41:24.627332  <6>[    2.069123] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()

10602 12:41:24.633635  <6>[    2.077204] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()

10603 12:41:24.640798  <6>[    2.085226] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()

10604 12:41:24.650613  <6>[    2.093145] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()

10605 12:41:24.657270  <6>[    2.100965] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()

10606 12:41:24.667046  <6>[    2.108786] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39

10607 12:41:24.677144  <6>[    2.119479] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)

10608 12:41:24.683815  <6>[    2.127857] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)

10609 12:41:24.693830  <6>[    2.136202] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)

10610 12:41:24.700766  <6>[    2.144545] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)

10611 12:41:24.710861  <6>[    2.152890] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)

10612 12:41:24.717384  <6>[    2.161233] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)

10613 12:41:24.727327  <6>[    2.169576] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)

10614 12:41:24.733935  <6>[    2.177920] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)

10615 12:41:24.744038  <6>[    2.186263] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)

10616 12:41:24.750460  <6>[    2.194607] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)

10617 12:41:24.760421  <6>[    2.202951] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)

10618 12:41:24.767108  <6>[    2.211296] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)

10619 12:41:24.777549  <6>[    2.219641] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)

10620 12:41:24.784311  <6>[    2.227985] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)

10621 12:41:24.794302  <6>[    2.236333] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)

10622 12:41:24.800746  <6>[    2.245308] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0

10623 12:41:24.807451  <6>[    2.252823] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0

10624 12:41:24.814182  <6>[    2.259929] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0

10625 12:41:24.820642  <6>[    2.267099] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0

10626 12:41:24.828555  <6>[    2.274441] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0

10627 12:41:24.838328  <6>[    2.281370] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)

10628 12:41:24.848500  <6>[    2.290511] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)

10629 12:41:24.858332  <6>[    2.299639] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)

10630 12:41:24.868233  <6>[    2.308941] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)

10631 12:41:24.878180  <6>[    2.318417] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)

10632 12:41:24.885114  <6>[    2.327892] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)

10633 12:41:24.894874  <6>[    2.337019] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)

10634 12:41:24.904825  <6>[    2.346492] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)

10635 12:41:24.914809  <6>[    2.355620] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)

10636 12:41:24.924727  <6>[    2.364922] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing

10637 12:41:24.934549  <6>[    2.375088] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing

10638 12:41:24.944237  <6>[    2.387073] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0

10639 12:41:24.951346  <6>[    2.397007] Trying to probe devices needed for running init ...

10640 12:41:24.979594  <6>[    2.423009] usb 1-1: new high-speed USB device number 2 using xhci-mtk

10641 12:41:25.133647  <6>[    2.580283] hub 1-1:1.0: USB hub found

10642 12:41:25.137483  <6>[    2.584726] hub 1-1:1.0: 4 ports detected

10643 12:41:25.257261  <6>[    2.703201] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk

10644 12:41:25.284288  <6>[    2.730994] hub 2-1:1.0: USB hub found

10645 12:41:25.287617  <6>[    2.735351] hub 2-1:1.0: 3 ports detected

10646 12:41:25.460217  <6>[    2.903073] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk

10647 12:41:25.592830  <6>[    3.038945] hub 1-1.4:1.0: USB hub found

10648 12:41:25.596067  <6>[    3.043613] hub 1-1.4:1.0: 2 ports detected

10649 12:41:25.672418  <6>[    3.115280] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk

10650 12:41:25.891869  <6>[    3.335024] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk

10651 12:41:26.083729  <6>[    3.527026] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk

10652 12:41:37.248527  <6>[   14.699358] ALSA device list:

10653 12:41:37.255046  <6>[   14.702587]   No soundcards found.

10654 12:41:37.261557  <6>[   14.708957] Freeing unused kernel memory: 8384K

10655 12:41:37.264724  <6>[   14.713860] Run /init as init process

10656 12:41:37.273169  Loading, please wait...

10657 12:41:37.289678  Starting version 247.3-7+deb11u2

10658 12:41:37.593362  <6>[   15.037577] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000

10659 12:41:37.599658  <6>[   15.045842] remoteproc remoteproc0: scp is available

10660 12:41:37.606385  <3>[   15.047111] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10661 12:41:37.616780  <4>[   15.051145] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2

10662 12:41:37.619623  <6>[   15.059514] mc: Linux media interface: v0.10

10663 12:41:37.629731  <6>[   15.059899] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:

10664 12:41:37.636485  <6>[   15.059922] mtk-pcie-gen3 11230000.pcie:      MEM 0x0012000000..0x00127fffff -> 0x0012000000

10665 12:41:37.646193  <6>[   15.059932] mtk-pcie-gen3 11230000.pcie:       IO 0x0012800000..0x0012ffffff -> 0x0012800000

10666 12:41:37.652783  <3>[   15.062080] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10667 12:41:37.663031  <3>[   15.062093] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10668 12:41:37.669177  <3>[   15.062169] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10669 12:41:37.679564  <3>[   15.062177] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10670 12:41:37.686031  <3>[   15.062184] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10671 12:41:37.696099  <3>[   15.062191] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10672 12:41:37.702680  <3>[   15.062198] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10673 12:41:37.709011  <3>[   15.062250] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10674 12:41:37.718868  <3>[   15.062297] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10675 12:41:37.725449  <3>[   15.062304] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10676 12:41:37.735323  <3>[   15.062310] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10677 12:41:37.741880  <3>[   15.062356] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10678 12:41:37.752199  <3>[   15.062363] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10679 12:41:37.758795  <3>[   15.062369] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10680 12:41:37.765377  <3>[   15.062375] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10681 12:41:37.775344  <3>[   15.062382] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10682 12:41:37.782358  <3>[   15.062423] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10683 12:41:37.788746  <6>[   15.069023] remoteproc remoteproc0: powering up scp

10684 12:41:37.798676  <4>[   15.069066] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2

10685 12:41:37.805273  <6>[   15.080998] usbcore: registered new interface driver r8152

10686 12:41:37.811941  <3>[   15.081147] remoteproc remoteproc0: request_firmware failed: -2

10687 12:41:37.818362  <6>[   15.081400] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered

10688 12:41:37.825087  <4>[   15.113650] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.

10689 12:41:37.832285  <4>[   15.113650] Fallback method does not support PEC.

10690 12:41:37.838403  <6>[   15.114092] videodev: Linux video capture interface: v2.00

10691 12:41:37.845154  <6>[   15.180125] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00

10692 12:41:37.851974  <4>[   15.194181] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator

10693 12:41:37.858547  <6>[   15.195572] pci_bus 0000:00: root bus resource [bus 00-ff]

10694 12:41:37.864993  <4>[   15.203741] elants_i2c 4-0010: supply vccio not found, using dummy regulator

10695 12:41:37.871655  <6>[   15.211773] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]

10696 12:41:37.881946  <6>[   15.324524] pci_bus 0000:00: root bus resource [io  0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])

10697 12:41:37.891378  <6>[   15.325286] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003

10698 12:41:37.898529  <6>[   15.334585] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400

10699 12:41:37.905216  <6>[   15.344831] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk

10700 12:41:37.915867  <6>[   15.345764] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2

10701 12:41:37.922227  <6>[   15.350871] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3

10702 12:41:37.932577  <6>[   15.350914] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]

10703 12:41:37.935589  <6>[   15.350985] pci 0000:00:00.0: supports D1 D2

10704 12:41:37.942404  <6>[   15.350988] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold

10705 12:41:37.952227  <6>[   15.352671] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring

10706 12:41:37.955653  <6>[   15.352781] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000

10707 12:41:37.965692  <6>[   15.352810] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]

10708 12:41:37.972401  <6>[   15.352829] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]

10709 12:41:37.978864  <6>[   15.352847] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]

10710 12:41:37.985319  <6>[   15.352959] pci 0000:01:00.0: supports D1 D2

10711 12:41:37.992048  <6>[   15.352962] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold

10712 12:41:37.998878  <6>[   15.362888] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01

10713 12:41:38.002073  <6>[   15.376676] usbcore: registered new interface driver cdc_ether

10714 12:41:38.012721  <6>[   15.383779] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]

10715 12:41:38.019294  <3>[   15.385426] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10716 12:41:38.029082  <4>[   15.386772] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2

10717 12:41:38.038671  <4>[   15.386781] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)

10718 12:41:38.042354  <6>[   15.395440] usbcore: registered new interface driver r8153_ecm

10719 12:41:38.052434  <6>[   15.403468] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]

10720 12:41:38.055457  <6>[   15.404109] Bluetooth: Core ver 2.22

10721 12:41:38.061735  <6>[   15.404154] NET: Registered PF_BLUETOOTH protocol family

10722 12:41:38.068650  <6>[   15.404157] Bluetooth: HCI device and connection manager initialized

10723 12:41:38.071828  <6>[   15.404170] Bluetooth: HCI socket layer initialized

10724 12:41:38.078654  <6>[   15.404175] Bluetooth: L2CAP socket layer initialized

10725 12:41:38.081836  <6>[   15.404184] Bluetooth: SCO socket layer initialized

10726 12:41:38.092178  <6>[   15.410417] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)

10727 12:41:38.098702  <6>[   15.417207] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]

10728 12:41:38.112202  <6>[   15.426266] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4

10729 12:41:38.118812  <6>[   15.432172] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]

10730 12:41:38.124963  <6>[   15.437102] usbcore: registered new interface driver uvcvideo

10731 12:41:38.132027  <6>[   15.443581] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]

10732 12:41:38.138630  <6>[   15.444225] usbcore: registered new interface driver btusb

10733 12:41:38.148657  <4>[   15.445186] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2

10734 12:41:38.155011  <3>[   15.445194] Bluetooth: hci0: Failed to load firmware file (-2)

10735 12:41:38.161501  <3>[   15.445198] Bluetooth: hci0: Failed to set up firmware (-2)

10736 12:41:38.171732  <4>[   15.445201] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.

10737 12:41:38.178220  <6>[   15.457236] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0

10738 12:41:38.181602  <6>[   15.464615] pci 0000:00:00.0: PCI bridge to [bus 01]

10739 12:41:38.191368  <3>[   15.474676] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10740 12:41:38.201274  <6>[   15.482419] pci 0000:00:00.0:   bridge window [mem 0x12000000-0x121fffff 64bit pref]

10741 12:41:38.204579  <6>[   15.482524] pcieport 0000:00:00.0: enabling device (0000 -> 0002)

10742 12:41:38.211647  <6>[   15.506852] r8152 2-1.3:1.0 eth0: v1.12.13

10743 12:41:38.217964  <6>[   15.509184] pcieport 0000:00:00.0: PME: Signaling with IRQ 283

10744 12:41:38.221133  <6>[   15.522080] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0

10745 12:41:38.227755  <6>[   15.525960] pcieport 0000:00:00.0: AER: enabled with IRQ 283

10746 12:41:38.255261  <5>[   15.699702] cfg80211: Loading compiled-in X.509 certificates for regulatory database

10747 12:41:38.273583  <5>[   15.717702] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'

10748 12:41:38.279694  <4>[   15.724565] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2

10749 12:41:38.286259  <6>[   15.733447] cfg80211: failed to load regulatory.db

10750 12:41:38.310250  <6>[   15.754583] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000

10751 12:41:38.316753  <6>[   15.762062] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)

10752 12:41:38.339352  <6>[   15.786922] mt7921e 0000:01:00.0: ASIC revision: 79610010

10753 12:41:38.436518  <4>[   15.877719] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10754 12:41:38.444273  Begin: Loading essential drivers ... done.

10755 12:41:38.447769  Begin: Running /scripts/init-premount ... done.

10756 12:41:38.453818  Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.

10757 12:41:38.464412  Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available

10758 12:41:38.467516  Device /sys/class/net/enx00e04c787aaa found

10759 12:41:38.467604  done.

10760 12:41:38.535483  <4>[   15.976819] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10761 12:41:38.541818  IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP

10762 12:41:38.635654  <4>[   16.076661] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10763 12:41:38.735669  <4>[   16.176792] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10764 12:41:38.835173  <4>[   16.276662] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10765 12:41:38.935647  <4>[   16.376723] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10766 12:41:39.035046  <4>[   16.476641] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10767 12:41:39.135120  <4>[   16.576707] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10768 12:41:39.235223  <4>[   16.676636] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10769 12:41:39.335239  <4>[   16.776687] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10770 12:41:39.426972  <3>[   16.874699] mt7921e 0000:01:00.0: hardware init failed

10771 12:41:39.691004  IP-Config: no re<6>[   17.137107] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on

10772 12:41:39.691187  sponse after 2 secs - giving up

10773 12:41:39.734267  IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP

10774 12:41:40.837935  IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):

10775 12:41:40.844628   address: 192.168.201.12   broadcast: 192.168.201.255  netmask: 255.255.255.0   

10776 12:41:40.850554   gateway: 192.168.201.1    dns0     : 192.168.201.1    dns1   : 0.0.0.0         

10777 12:41:40.857560   host   : mt8192-asurada-spherion-r0-cbg-0                                

10778 12:41:40.864210   domain : lava-rack                                                       

10779 12:41:40.867364   rootserver: 192.168.201.1 rootpath: 

10780 12:41:40.870604   filename  : 

10781 12:41:40.906449  done.

10782 12:41:40.913002  Begin: Running /scripts/nfs-bottom ... done.

10783 12:41:40.924815  Begin: Running /scripts/init-bottom ... done.

10784 12:41:42.008438  <6>[   19.456931] NET: Registered PF_INET6 protocol family

10785 12:41:42.015127  <6>[   19.463188] Segment Routing with IPv6

10786 12:41:42.018450  <6>[   19.467138] In-situ OAM (IOAM) with IPv6

10787 12:41:42.127294  <30>[   19.555822] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)

10788 12:41:42.130700  <30>[   19.579579] systemd[1]: Detected architecture arm64.

10789 12:41:42.150046  

10790 12:41:42.153434  Welcome to Debian GNU/Linux 11 (bullseye)!

10791 12:41:42.153558  

10792 12:41:42.168472  <30>[   19.616904] systemd[1]: Set hostname to <debian-bullseye-arm64>.

10793 12:41:42.668921  <30>[   20.113694] systemd[1]: Queued start job for default target Graphical Interface.

10794 12:41:42.687754  <30>[   20.135922] systemd[1]: Created slice system-getty.slice.

10795 12:41:42.694071  [  OK  ] Created slice system-getty.slice.

10796 12:41:42.711331  <30>[   20.159558] systemd[1]: Created slice system-modprobe.slice.

10797 12:41:42.717708  [  OK  ] Created slice system-modprobe.slice.

10798 12:41:42.735204  <30>[   20.183520] systemd[1]: Created slice system-serial\x2dgetty.slice.

10799 12:41:42.745485  [  OK  ] Created slice system-serial\x2dgetty.slice.

10800 12:41:42.759762  <30>[   20.207604] systemd[1]: Created slice User and Session Slice.

10801 12:41:42.766121  [  OK  ] Created slice User and Session Slice.

10802 12:41:42.786261  <30>[   20.231259] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.

10803 12:41:42.792684  [  OK  ] Started Dispatch Password …ts to Console Directory Watch.

10804 12:41:42.809773  <30>[   20.255165] systemd[1]: Started Forward Password Requests to Wall Directory Watch.

10805 12:41:42.816583  [  OK  ] Started Forward Password R…uests to Wall Directory Watch.

10806 12:41:42.837491  <30>[   20.279075] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.

10807 12:41:42.844031  <30>[   20.291106] systemd[1]: Reached target Local Encrypted Volumes.

10808 12:41:42.850703  [  OK  ] Reached target Local Encrypted Volumes.

10809 12:41:42.867058  <30>[   20.315127] systemd[1]: Reached target Paths.

10810 12:41:42.870360  [  OK  ] Reached target Paths.

10811 12:41:42.886687  <30>[   20.335053] systemd[1]: Reached target Remote File Systems.

10812 12:41:42.893019  [  OK  ] Reached target Remote File Systems.

10813 12:41:42.906820  <30>[   20.354983] systemd[1]: Reached target Slices.

10814 12:41:42.910049  [  OK  ] Reached target Slices.

10815 12:41:42.926548  <30>[   20.375097] systemd[1]: Reached target Swap.

10816 12:41:42.929727  [  OK  ] Reached target Swap.

10817 12:41:42.950156  <30>[   20.395233] systemd[1]: Listening on initctl Compatibility Named Pipe.

10818 12:41:42.956594  [  OK  ] Listening on initctl Compatibility Named Pipe.

10819 12:41:42.971858  <30>[   20.420373] systemd[1]: Listening on Journal Audit Socket.

10820 12:41:42.978454  [  OK  ] Listening on Journal Audit Socket.

10821 12:41:42.995958  <30>[   20.444193] systemd[1]: Listening on Journal Socket (/dev/log).

10822 12:41:43.002467  [  OK  ] Listening on Journal Socket (/dev/log).

10823 12:41:43.019428  <30>[   20.467473] systemd[1]: Listening on Journal Socket.

10824 12:41:43.025586  [  OK  ] Listening on Journal Socket.

10825 12:41:43.042770  <30>[   20.488031] systemd[1]: Listening on Network Service Netlink Socket.

10826 12:41:43.049453  [  OK  ] Listening on Network Service Netlink Socket.

10827 12:41:43.064799  <30>[   20.513285] systemd[1]: Listening on udev Control Socket.

10828 12:41:43.071348  [  OK  ] Listening on udev Control Socket.

10829 12:41:43.086929  <30>[   20.535237] systemd[1]: Listening on udev Kernel Socket.

10830 12:41:43.093684  [  OK  ] Listening on udev Kernel Socket.

10831 12:41:43.126631  <30>[   20.575123] systemd[1]: Mounting Huge Pages File System...

10832 12:41:43.133659           Mounting Huge Pages File System...

10833 12:41:43.148215  <30>[   20.596751] systemd[1]: Mounting POSIX Message Queue File System...

10834 12:41:43.155492           Mounting POSIX Message Queue File System...

10835 12:41:43.172571  <30>[   20.620712] systemd[1]: Mounting Kernel Debug File System...

10836 12:41:43.178606           Mounting Kernel Debug File System...

10837 12:41:43.198059  <30>[   20.643108] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.

10838 12:41:43.258384  <30>[   20.703254] systemd[1]: Starting Create list of static device nodes for the current kernel...

10839 12:41:43.264950           Starting Create list of st…odes for the current kernel...

10840 12:41:43.284713  <30>[   20.732876] systemd[1]: Starting Load Kernel Module configfs...

10841 12:41:43.291353           Starting Load Kernel Module configfs...

10842 12:41:43.308489  <30>[   20.756845] systemd[1]: Starting Load Kernel Module drm...

10843 12:41:43.314764           Starting Load Kernel Module drm...

10844 12:41:43.332295  <30>[   20.780863] systemd[1]: Starting Load Kernel Module fuse...

10845 12:41:43.338803           Starting Load Kernel Module fuse...

10846 12:41:43.366674  <6>[   20.815354] fuse: init (API version 7.37)

10847 12:41:43.376991  <30>[   20.816284] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.

10848 12:41:43.384565  <30>[   20.832622] systemd[1]: Starting Journal Service...

10849 12:41:43.387563           Starting Journal Service...

10850 12:41:43.408603  <30>[   20.856814] systemd[1]: Starting Load Kernel Modules...

10851 12:41:43.414858           Starting Load Kernel Modules...

10852 12:41:43.431955  <30>[   20.876884] systemd[1]: Starting Remount Root and Kernel File Systems...

10853 12:41:43.438447           Starting Remount Root and Kernel File Systems...

10854 12:41:43.456376  <30>[   20.904899] systemd[1]: Starting Coldplug All udev Devices...

10855 12:41:43.463125           Starting Coldplug All udev Devices...

10856 12:41:43.481029  <30>[   20.929441] systemd[1]: Mounted Huge Pages File System.

10857 12:41:43.487944  [  OK  ] Mounted Huge Pages File System.

10858 12:41:43.502695  <30>[   20.951243] systemd[1]: Mounted POSIX Message Queue File System.

10859 12:41:43.509535  [  OK  ] Mounted POSIX Message Queue File System.

10860 12:41:43.532473  <3>[   20.977785] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10861 12:41:43.539477  <30>[   20.987003] systemd[1]: Mounted Kernel Debug File System.

10862 12:41:43.545979  [  OK  ] Mounted Kernel Debug File System.

10863 12:41:43.563507  <30>[   21.007640] systemd[1]: Finished Create list of static device nodes for the current kernel.

10864 12:41:43.573528  <3>[   21.013657] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10865 12:41:43.579556  [  OK  ] Finished Create list of st… nodes for the current kernel.

10866 12:41:43.595411  <30>[   21.043701] systemd[1]: modprobe@configfs.service: Succeeded.

10867 12:41:43.602510  <30>[   21.050473] systemd[1]: Finished Load Kernel Module configfs.

10868 12:41:43.612555  <3>[   21.054511] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10869 12:41:43.618776  [  OK  ] Finished Load Kernel Module configfs.

10870 12:41:43.635559  <30>[   21.083616] systemd[1]: modprobe@drm.service: Succeeded.

10871 12:41:43.645773  <3>[   21.088944] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10872 12:41:43.648918  <30>[   21.089839] systemd[1]: Finished Load Kernel Module drm.

10873 12:41:43.655411  [  OK  ] Finished Load Kernel Module drm.

10874 12:41:43.671341  <30>[   21.119585] systemd[1]: modprobe@fuse.service: Succeeded.

10875 12:41:43.681606  <3>[   21.122143] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10876 12:41:43.684713  <30>[   21.125831] systemd[1]: Finished Load Kernel Module fuse.

10877 12:41:43.691429  [  OK  ] Finished Load Kernel Module fuse.

10878 12:41:43.708592  <30>[   21.155911] systemd[1]: Finished Load Kernel Modules.

10879 12:41:43.715277  <3>[   21.159199] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10880 12:41:43.721938  [  OK  ] Finished Load Kernel Modules.

10881 12:41:43.739262  <30>[   21.183797] systemd[1]: Finished Remount Root and Kernel File Systems.

10882 12:41:43.749474  [  OK  ] Finished [0<3>[   21.193047] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10883 12:41:43.752828  ;1;39mRemount Root and Kernel File Systems.

10884 12:41:43.778343  <3>[   21.223467] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10885 12:41:43.797963  <30>[   21.245445] systemd[1]: Mounting FUSE Control File System...

10886 12:41:43.810740           Mounting FUSE <3>[   21.253431] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10887 12:41:43.810898  Control File System...

10888 12:41:43.832970  <30>[   21.280878] systemd[1]: Mounting Kernel Configuration File System...

10889 12:41:43.842803  <3>[   21.283088] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10890 12:41:43.849204           Mounting Kernel Configuration File System...

10891 12:41:43.873396  <30>[   21.318811] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.

10892 12:41:43.883362  <30>[   21.327792] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.

10893 12:41:43.918524  <30>[   21.367291] systemd[1]: Starting Load/Save Random Seed...

10894 12:41:43.925114           Starting Load/Save Random Seed...

10895 12:41:43.940868  <30>[   21.388806] systemd[1]: Starting Apply Kernel Variables...

10896 12:41:43.947224           Starting Apply Kernel Variables...

10897 12:41:43.964972  <30>[   21.413601] systemd[1]: Starting Create System Users...

10898 12:41:43.971520           Starting Create System Users...

10899 12:41:43.996876  <4>[   21.435017] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent

10900 12:41:44.003107  <30>[   21.436229] systemd[1]: Started Journal Service.

10901 12:41:44.009821  <3>[   21.451164] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5

10902 12:41:44.016583  [  OK  ] Started Journal Service.

10903 12:41:44.032368  [  OK  ] Mounted FUSE Control File System.

10904 12:41:44.050918  [FAILED] Failed to start Coldplug All udev Devices.

10905 12:41:44.066420  See 'systemctl status systemd-udev-trigger.service' for details.

10906 12:41:44.083185  [  OK  ] Mounted Kernel Configuration File System.

10907 12:41:44.103342  [  OK  ] Finished Load/Save Random Seed.

10908 12:41:44.123312  [  OK  ] Finished Apply Kernel Variables.

10909 12:41:44.139588  [  OK  ] Finished Create System Users.

10910 12:41:44.182980           Starting Flush Journal to Persistent Storage...

10911 12:41:44.200423           Starting Create Static Device Nodes in /dev...

10912 12:41:44.235283  <46>[   21.680563] systemd-journald[291]: Received client request to flush runtime journal.

10913 12:41:44.621367  [  OK  ] Finished Create Static Device Nodes in /dev.

10914 12:41:44.634806  [  OK  ] Reached target Local File Systems (Pre).

10915 12:41:44.650803  [  OK  ] Reached target Local File Systems.

10916 12:41:44.686056           Starting Rule-based Manage…for Device Events and Files...

10917 12:41:45.602679  [  OK  ] Finished Flush Journal to Persistent Storage.

10918 12:41:45.659311           Starting Create Volatile Files and Directories...

10919 12:41:45.678120  [  OK  ] Started Rule-based Manager for Device Events and Files.

10920 12:41:45.695766           Starting Network Service...

10921 12:41:45.955078  [  OK  ] Found device /dev/ttyS0.

10922 12:41:45.976680  [  OK  ] Created slice system-systemd\x2dbacklight.slice.

10923 12:41:46.029791           Starting Load/Save Screen …of leds:white:kbd_backlight...

10924 12:41:46.187840  <6>[   23.636854] remoteproc remoteproc0: powering up scp

10925 12:41:46.231951  <4>[   23.677128] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2

10926 12:41:46.238360  <3>[   23.686978] remoteproc remoteproc0: request_firmware failed: -2

10927 12:41:46.248427  <3>[   23.693161] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!

10928 12:41:46.364824  [  OK  ] Finished Load/Save Screen …s of leds:white:kbd_backlight.

10929 12:41:46.378780  [  OK  ] Started Network Service.

10930 12:41:46.424679  [  OK  ] Finished Create Volatile Files and Directories.

10931 12:41:46.443254  [  OK  ] Reached target Bluetooth.

10932 12:41:46.461789  [  OK  ] Listening on Load/Save RF …itch Status /dev/rfkill Watch.

10933 12:41:46.518570           Starting Network Name Resolution...

10934 12:41:46.544664           Starting Network Time Synchronization...

10935 12:41:46.563959           Starting Update UTMP about System Boot/Shutdown...

10936 12:41:46.580701           Starting Load/Save RF Kill Switch Status...

10937 12:41:46.612001  [  OK  ] Started Load/Save RF Kill Switch Status.

10938 12:41:46.634759  [  OK  ] Finished Update UTMP about System Boot/Shutdown.

10939 12:41:46.974417  [  OK  ] Started Network Time Synchronization.

10940 12:41:46.990720  [  OK  ] Reached target System Initialization.

10941 12:41:47.009499  [  OK  ] Started Daily Cleanup of Temporary Directories.

10942 12:41:47.022590  [  OK  ] Reached target System Time Set.

10943 12:41:47.038073  [  OK  ] Reached target System Time Synchronized.

10944 12:41:47.086429  [  OK  ] Started Daily apt download activities.

10945 12:41:47.550320  [  OK  ] Started Daily apt upgrade and clean activities.

10946 12:41:47.818926  [  OK  ] Started Periodic ext4 Onli…ata Check for All Filesystems.

10947 12:41:48.150906  [  OK  ] Started Discard unused blocks once a week.

10948 12:41:48.162435  [  OK  ] Reached target Timers.

10949 12:41:48.182736  [  OK  ] Listening on D-Bus System Message Bus Socket.

10950 12:41:48.198090  [  OK  ] Reached target Sockets.

10951 12:41:48.218388  [  OK  ] Reached target Basic System.

10952 12:41:48.254033  [  OK  ] Started D-Bus System Message Bus.

10953 12:41:48.285453           Starting Remove Stale Onli…t4 Metadata Check Snapshots...

10954 12:41:48.358474           Starting User Login Management...

10955 12:41:48.374501  [  OK  ] Started Network Name Resolution.

10956 12:41:48.391347  [  OK  ] Reached target Network.

10957 12:41:48.409147  [  OK  ] Reached target Host and Network Name Lookups.

10958 12:41:48.462115           Starting Permit User Sessions...

10959 12:41:48.564964  [  OK  ] Finished Remove Stale Onli…ext4 Metadata Check Snapshots.

10960 12:41:48.583509  [  OK  ] Finished Permit User Sessions.

10961 12:41:48.622272  [  OK  ] Started Getty on tty1.

10962 12:41:48.644371  [  OK  ] Started Serial Getty on ttyS0.

10963 12:41:48.662390  [  OK  ] Reached target Login Prompts.

10964 12:41:48.683293  [  OK  ] Started User Login Management.

10965 12:41:48.702916  [  OK  ] Reached target Multi-User System.

10966 12:41:48.718127  [  OK  ] Reached target Graphical Interface.

10967 12:41:48.757823           Starting Update UTMP about System Runlevel Changes...

10968 12:41:48.790294  [  OK  ] Finished Update UTMP about System Runlevel Changes.

10969 12:41:48.837672  

10970 12:41:48.837822  

10971 12:41:48.841040  Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0

10972 12:41:48.841148  

10973 12:41:48.844107  debian-bullseye-arm64 login: root (automatic login)

10974 12:41:48.844191  

10975 12:41:48.844257  

10976 12:41:49.258267  Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Wed Jun 14 12:30:40 UTC 2023 aarch64

10977 12:41:49.258418  

10978 12:41:49.264917  The programs included with the Debian GNU/Linux system are free software;

10979 12:41:49.271478  the exact distribution terms for each program are described in the

10980 12:41:49.274738  individual files in /usr/share/doc/*/copyright.

10981 12:41:49.274874  

10982 12:41:49.281012  Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent

10983 12:41:49.281113  permitted by applicable law.

10984 12:41:49.314911  Matched prompt #10: / #
10986 12:41:49.315196  Setting prompt string to ['/ #']
10987 12:41:49.315291  end: 2.2.5.1 login-action (duration 00:00:27) [common]
10989 12:41:49.315484  end: 2.2.5 auto-login-action (duration 00:00:28) [common]
10990 12:41:49.315571  start: 2.2.6 expect-shell-connection (timeout 00:03:33) [common]
10991 12:41:49.315644  Setting prompt string to ['/ #']
10992 12:41:49.315704  Forcing a shell prompt, looking for ['/ #']
10994 12:41:49.365931  / # 

10995 12:41:49.366116  expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10996 12:41:49.366206  Waiting using forced prompt support (timeout 00:02:30)
10997 12:41:49.370811  

10998 12:41:49.371117  end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10999 12:41:49.371218  start: 2.2.7 export-device-env (timeout 00:03:32) [common]
11001 12:41:49.471599  / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10724866/extract-nfsrootfs-176kw0_e'

11002 12:41:49.477266  export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10724866/extract-nfsrootfs-176kw0_e'

11004 12:41:49.577857  / # export NFS_SERVER_IP='192.168.201.1'

11005 12:41:49.582658  export NFS_SERVER_IP='192.168.201.1'

11006 12:41:49.583011  end: 2.2.7 export-device-env (duration 00:00:00) [common]
11007 12:41:49.583124  end: 2.2 depthcharge-retry (duration 00:01:28) [common]
11008 12:41:49.583212  end: 2 depthcharge-action (duration 00:01:28) [common]
11009 12:41:49.583346  start: 3 lava-test-retry (timeout 00:01:00) [common]
11010 12:41:49.583434  start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11011 12:41:49.583510  Using namespace: common
11013 12:41:49.683813  / # #

11014 12:41:49.683990  lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11015 12:41:49.688625  #

11016 12:41:49.688919  Using /lava-10724866
11018 12:41:49.789278  / # export SHELL=/bin/sh

11019 12:41:49.794743  export SHELL=/bin/sh

11021 12:41:49.895300  / # . /lava-10724866/environment

11022 12:41:49.900717  . /lava-10724866/environment

11024 12:41:50.004258  / # /lava-10724866/bin/lava-test-runner /lava-10724866/0

11025 12:41:50.004422  Test shell timeout: 10s (minimum of the action and connection timeout)
11026 12:41:50.009946  /lava-10724866/bin/lava-test-runner /lava-10724866/0

11027 12:41:50.192144  + export TESTRUN_ID=0_dmesg

11028 12:41:50.195176  + cd /lava-10724866/0/tests/0_dmesg

11029 12:41:50.198517  + cat uuid

11030 12:41:50.205506  + UUID=10724866_1.<8>[   27.652474] <LAVA_SIGNAL_STARTRUN 0_dmesg 10724866_1.6.2.3.1>

11031 12:41:50.205598  6.2.3.1

11032 12:41:50.205876  Received signal: <STARTRUN> 0_dmesg 10724866_1.6.2.3.1
11033 12:41:50.205970  Starting test lava.0_dmesg (10724866_1.6.2.3.1)
11034 12:41:50.206055  Skipping test definition patterns.
11035 12:41:50.208710  + set +x

11036 12:41:50.211885  + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh

11037 12:41:50.280057  <8>[   27.725968] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>

11038 12:41:50.280364  Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11040 12:41:50.368884  <8>[   27.814432] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>

11041 12:41:50.369197  Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11043 12:41:50.415759  <8>[   27.861720] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>

11044 12:41:50.416077  Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11046 12:41:50.422663  + <8>[   27.870999] <LAVA_SIGNAL_ENDRUN 0_dmesg 10724866_1.6.2.3.1>

11047 12:41:50.422754  set +x

11048 12:41:50.422990  Received signal: <ENDRUN> 0_dmesg 10724866_1.6.2.3.1
11049 12:41:50.423072  Ending use of test pattern.
11050 12:41:50.423134  Ending test lava.0_dmesg (10724866_1.6.2.3.1), duration 0.22
11052 12:41:50.426445  <LAVA_TEST_RUNNER EXIT>

11053 12:41:50.426697  ok: lava_test_shell seems to have completed
11054 12:41:50.426799  alert: pass
crit: pass
emerg: pass

11055 12:41:50.426887  end: 3.1 lava-test-shell (duration 00:00:01) [common]
11056 12:41:50.426972  end: 3 lava-test-retry (duration 00:00:01) [common]
11057 12:41:50.427053  start: 4 lava-test-retry (timeout 00:01:00) [common]
11058 12:41:50.427133  start: 4.1 lava-test-shell (timeout 00:01:00) [common]
11059 12:41:50.427196  Using namespace: common
11061 12:41:50.527557  / # #

11062 12:41:50.527739  lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11063 12:41:50.527861  Using /lava-10724866
11065 12:41:50.628197  export SHELL=/bin/sh

11066 12:41:50.628559  #

11068 12:41:50.729162  / # export SHELL=/bin/sh. /lava-10724866/environment

11069 12:41:50.729398  

11071 12:41:50.829945  / # . /lava-10724866/environment/lava-10724866/bin/lava-test-runner /lava-10724866/1

11072 12:41:50.830118  Test shell timeout: 10s (minimum of the action and connection timeout)
11073 12:41:50.830276  

11074 12:41:50.835121  / # /lava-10724866/bin/lava-test-runner /lava-10724866/1

11075 12:41:50.914617  + export TESTRUN_ID=1_bootrr

11076 12:41:50.917697  + cd /lava-10724866/1/tests/1_bootrr

11077 12:41:50.921271  + cat uuid

11078 12:41:50.927433  + UUID=10724866_<8>[   28.373965] <LAVA_SIGNAL_STARTRUN 1_bootrr 10724866_1.6.2.3.5>

11079 12:41:50.927529  1.6.2.3.5

11080 12:41:50.927598  + set +x

11081 12:41:50.927837  Received signal: <STARTRUN> 1_bootrr 10724866_1.6.2.3.5
11082 12:41:50.927933  Starting test lava.1_bootrr (10724866_1.6.2.3.5)
11083 12:41:50.928012  Skipping test definition patterns.
11084 12:41:50.941175  + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-10724866/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin

11085 12:41:50.944050  + cd /opt/bootrr/libexec/bootrr

11086 12:41:50.944171  + sh helpers/bootrr-auto

11087 12:41:50.976907  /lava-10724866/1/../bin/lava-test-case

11088 12:41:50.997180  <8>[   28.443077] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>

11089 12:41:50.997518  Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
11091 12:41:51.023453  /lava-10724866/1/../bin/lava-test-case

11092 12:41:51.039216  <8>[   28.485217] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>

11093 12:41:51.039545  Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
11095 12:41:51.056153  /lava-10724866/1/../bin/lava-test-case

11096 12:41:51.075201  <8>[   28.521035] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>

11097 12:41:51.075506  Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
11099 12:41:51.113572  /lava-10724866/1/../bin/lava-test-case

11100 12:41:51.133764  <8>[   28.579518] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>

11101 12:41:51.134112  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
11103 12:41:51.160740  /lava-10724866/1/../bin/lava-test-case

11104 12:41:51.180197  <8>[   28.626457] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>

11105 12:41:51.180555  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
11107 12:41:51.209765  /lava-10724866/1/../bin/lava-test-case

11108 12:41:51.229573  <8>[   28.675403] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>

11109 12:41:51.229890  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
11111 12:41:51.256280  /lava-10724866/1/../bin/lava-test-case

11112 12:41:51.276172  <8>[   28.722447] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>

11113 12:41:51.276476  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
11115 12:41:51.299068  /lava-10724866/1/../bin/lava-test-case

11116 12:41:51.317390  <8>[   28.763513] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>

11117 12:41:51.317729  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
11119 12:41:51.335300  /lava-10724866/1/../bin/lava-test-case

11120 12:41:51.355753  <8>[   28.801996] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>

11121 12:41:51.356099  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
11123 12:41:51.379929  /lava-10724866/1/../bin/lava-test-case

11124 12:41:51.398535  <8>[   28.844476] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>

11125 12:41:51.398867  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
11127 12:41:51.415378  /lava-10724866/1/../bin/lava-test-case

11128 12:41:51.435159  <8>[   28.881413] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>

11129 12:41:51.435489  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
11131 12:41:51.460046  /lava-10724866/1/../bin/lava-test-case

11132 12:41:51.478372  <8>[   28.924620] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>

11133 12:41:51.478707  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
11135 12:41:51.503655  /lava-10724866/1/../bin/lava-test-case

11136 12:41:51.519860  <8>[   28.965597] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>

11137 12:41:51.520181  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
11139 12:41:51.550505  /lava-10724866/1/../bin/lava-test-case

11140 12:41:51.567519  <8>[   29.013914] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>

11141 12:41:51.567852  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
11143 12:41:51.589544  /lava-10724866/1/../bin/lava-test-case

11144 12:41:51.607309  <8>[   29.052995] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>

11145 12:41:51.607644  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11147 12:41:51.624303  /lava-10724866/1/../bin/lava-test-case

11148 12:41:51.641447  <8>[   29.087566] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>

11149 12:41:51.641750  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11151 12:41:51.662815  /lava-10724866/1/../bin/lava-test-case

11152 12:41:51.680708  <8>[   29.126832] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>

11153 12:41:51.681049  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11155 12:41:51.697690  /lava-10724866/1/../bin/lava-test-case

11156 12:41:51.716704  <8>[   29.163038] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>

11157 12:41:51.717061  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11159 12:41:51.739926  /lava-10724866/1/../bin/lava-test-case

11160 12:41:51.757549  <8>[   29.203790] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>

11161 12:41:51.757856  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11163 12:41:51.775667  /lava-10724866/1/../bin/lava-test-case

11164 12:41:51.794821  <8>[   29.240761] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>

11165 12:41:51.795163  Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11167 12:41:51.817501  /lava-10724866/1/../bin/lava-test-case

11168 12:41:51.836550  <8>[   29.282605] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>

11169 12:41:51.836892  Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11171 12:41:51.862646  /lava-10724866/1/../bin/lava-test-case

11172 12:41:51.879768  <8>[   29.326050] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>

11173 12:41:51.880087  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11175 12:41:51.904306  /lava-10724866/1/../bin/lava-test-case

11176 12:41:51.920738  <8>[   29.366690] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>

11177 12:41:51.921099  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11179 12:41:51.936550  /lava-10724866/1/../bin/lava-test-case

11180 12:41:51.954877  <8>[   29.400960] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>

11181 12:41:51.955181  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11183 12:41:51.980105  /lava-10724866/1/../bin/lava-test-case

11184 12:41:52.000152  <8>[   29.446355] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>

11185 12:41:52.000456  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11187 12:41:52.025663  /lava-10724866/1/../bin/lava-test-case

11188 12:41:52.045684  <8>[   29.491433] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>

11189 12:41:52.045989  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11191 12:41:52.063563  /lava-10724866/1/../bin/lava-test-case

11192 12:41:52.083034  <8>[   29.529121] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>

11193 12:41:52.083336  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11195 12:41:52.109192  /lava-10724866/1/../bin/lava-test-case

11196 12:41:52.128930  <8>[   29.575115] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>

11197 12:41:52.129238  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11199 12:41:52.153080  /lava-10724866/1/../bin/lava-test-case

11200 12:41:52.171643  <8>[   29.617850] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>

11201 12:41:52.171932  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11203 12:41:52.195489  /lava-10724866/1/../bin/lava-test-case

11204 12:41:52.213607  <8>[   29.659682] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>

11205 12:41:52.213881  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11207 12:41:52.240695  /lava-10724866/1/../bin/lava-test-case

11208 12:41:52.260860  <8>[   29.706896] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>

11209 12:41:52.261168  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11211 12:41:52.285238  /lava-10724866/1/../bin/lava-test-case

11212 12:41:52.303863  <8>[   29.749591] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>

11213 12:41:52.304160  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11215 12:41:52.327278  /lava-10724866/1/../bin/lava-test-case

11216 12:41:52.347356  <8>[   29.793310] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>

11217 12:41:52.347680  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11219 12:41:52.364776  /lava-10724866/1/../bin/lava-test-case

11220 12:41:52.383079  <8>[   29.829363] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>

11221 12:41:52.383415  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11223 12:41:52.408291  /lava-10724866/1/../bin/lava-test-case

11224 12:41:52.427384  <8>[   29.873293] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>

11225 12:41:52.427722  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11227 12:41:52.459444  /lava-10724866/1/../bin/lava-test-case

11228 12:41:52.477862  <8>[   29.923806] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>

11229 12:41:52.478178  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11231 12:41:52.493148  /lava-10724866/1/../bin/lava-test-case

11232 12:41:52.512679  <8>[   29.958987] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>

11233 12:41:52.512964  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11235 12:41:52.540077  /lava-10724866/1/../bin/lava-test-case

11236 12:41:52.559448  <8>[   30.005498] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>

11237 12:41:52.559728  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11239 12:41:52.575070  /lava-10724866/1/../bin/lava-test-case

11240 12:41:52.591890  <8>[   30.038270] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>

11241 12:41:52.592151  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11243 12:41:52.615246  /lava-10724866/1/../bin/lava-test-case

11244 12:41:52.631777  <8>[   30.078160] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>

11245 12:41:52.632035  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11247 12:41:52.647952  /lava-10724866/1/../bin/lava-test-case

11248 12:41:52.665575  <8>[   30.111809] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>

11249 12:41:52.665961  Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11251 12:41:52.687791  /lava-10724866/1/../bin/lava-test-case

11252 12:41:52.703718  <8>[   30.149906] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>

11253 12:41:52.704075  Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11255 12:41:52.718579  /lava-10724866/1/../bin/lava-test-case

11256 12:41:52.734754  <8>[   30.181110] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>

11257 12:41:52.735050  Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11259 12:41:52.766238  /lava-10724866/1/../bin/lava-test-case

11260 12:41:52.783045  <8>[   30.228919] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>

11261 12:41:52.783379  Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11263 12:41:52.797631  /lava-10724866/1/../bin/lava-test-case

11264 12:41:52.814897  <8>[   30.261041] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>

11265 12:41:52.815197  Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11267 12:41:52.838435  /lava-10724866/1/../bin/lava-test-case

11268 12:41:52.858375  <8>[   30.304447] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>

11269 12:41:52.858677  Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11271 12:41:52.872742  /lava-10724866/1/../bin/lava-test-case

11272 12:41:52.889221  <8>[   30.335703] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>

11273 12:41:52.889533  Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11275 12:41:52.910297  /lava-10724866/1/../bin/lava-test-case

11276 12:41:52.927184  <8>[   30.373118] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>

11277 12:41:52.927518  Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11279 12:41:52.941556  /lava-10724866/1/../bin/lava-test-case

11280 12:41:52.961625  <8>[   30.408050] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>

11281 12:41:52.961976  Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11283 12:41:52.987459  /lava-10724866/1/../bin/lava-test-case

11284 12:41:53.004195  <8>[   30.450338] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>

11285 12:41:53.004544  Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11287 12:41:53.027497  /lava-10724866/1/../bin/lava-test-case

11288 12:41:53.046618  <8>[   30.492468] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>

11289 12:41:53.046959  Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11291 12:41:54.080696  /lava-10724866/1/../bin/lava-test-case

11292 12:41:54.099045  <8>[   31.545736] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail>

11293 12:41:54.099340  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail
11295 12:41:55.122076  /lava-10724866/1/../bin/lava-test-case

11296 12:41:55.151537  <8>[   32.597357] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked>

11297 12:41:55.152273  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked
11298 12:41:55.152778  Bad test result: blocked
11299 12:41:55.171840  /lava-10724866/1/../bin/lava-test-case

11300 12:41:55.196008  <8>[   32.642197] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>

11301 12:41:55.196707  Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11303 12:41:55.227127  /lava-10724866/1/../bin/lava-test-case

11304 12:41:55.254987  <8>[   32.701224] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>

11305 12:41:55.255698  Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11307 12:41:55.282991  /lava-10724866/1/../bin/lava-test-case

11308 12:41:55.308149  <8>[   32.753994] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>

11309 12:41:55.308870  Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11311 12:41:55.338829  /lava-10724866/1/../bin/lava-test-case

11312 12:41:55.365336  <8>[   32.811141] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>

11313 12:41:55.366139  Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11315 12:41:55.392040  /lava-10724866/1/../bin/lava-test-case

11316 12:41:55.412253  <8>[   32.858438] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>

11317 12:41:55.413240  Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11319 12:41:55.449405  /lava-10724866/1/../bin/lava-test-case

11320 12:41:55.472688  <8>[   32.918532] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>

11321 12:41:55.472985  Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11323 12:41:55.489084  /lava-10724866/1/../bin/lava-test-case

11324 12:41:55.509966  <8>[   32.956413] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>

11325 12:41:55.510237  Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11327 12:41:55.532729  /lava-10724866/1/../bin/lava-test-case

11328 12:41:55.549994  <8>[   32.996719] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>

11329 12:41:55.550269  Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11331 12:41:55.574347  /lava-10724866/1/../bin/lava-test-case

11332 12:41:55.597855  <8>[   33.044438] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>

11333 12:41:55.598126  Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11335 12:41:55.615719  /lava-10724866/1/../bin/lava-test-case

11336 12:41:55.635604  <8>[   33.081856] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>

11337 12:41:55.635870  Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11339 12:41:55.660305  /lava-10724866/1/../bin/lava-test-case

11340 12:41:55.675671  <8>[   33.122535] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>

11341 12:41:55.675955  Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11343 12:41:55.690030  /lava-10724866/1/../bin/lava-test-case

11344 12:41:55.706381  <8>[   33.152724] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>

11345 12:41:55.706641  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11347 12:41:55.729244  /lava-10724866/1/../bin/lava-test-case

11348 12:41:55.748166  <8>[   33.194686] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>

11349 12:41:55.748428  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11351 12:41:55.771962  /lava-10724866/1/../bin/lava-test-case

11352 12:41:55.788120  <8>[   33.234886] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>

11353 12:41:55.788381  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11355 12:41:55.810770  /lava-10724866/1/../bin/lava-test-case

11356 12:41:55.826978  <8>[   33.273577] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>

11357 12:41:55.827275  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11359 12:41:55.849548  /lava-10724866/1/../bin/lava-test-case

11360 12:41:55.867430  <8>[   33.313640] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>

11361 12:41:55.867711  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11363 12:41:55.889568  /lava-10724866/1/../bin/lava-test-case

11364 12:41:55.906954  <8>[   33.353178] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>

11365 12:41:55.907249  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11367 12:41:55.930696  /lava-10724866/1/../bin/lava-test-case

11368 12:41:55.947699  <8>[   33.393758] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>

11369 12:41:55.948005  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11371 12:41:55.972913  /lava-10724866/1/../bin/lava-test-case

11372 12:41:55.991661  <8>[   33.438076] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>

11373 12:41:55.991947  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11375 12:41:56.014820  /lava-10724866/1/../bin/lava-test-case

11376 12:41:56.032636  <8>[   33.479044] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>

11377 12:41:56.032935  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11379 12:41:56.056181  /lava-10724866/1/../bin/lava-test-case

11380 12:41:56.072483  <8>[   33.518986] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>

11381 12:41:56.072765  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11383 12:41:56.102221  /lava-10724866/1/../bin/lava-test-case

11384 12:41:56.118772  <8>[   33.565485] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>

11385 12:41:56.119055  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11387 12:41:56.140026  /lava-10724866/1/../bin/lava-test-case

11388 12:41:56.155512  <8>[   33.602399] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>

11389 12:41:56.155778  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11391 12:41:56.179445  /lava-10724866/1/../bin/lava-test-case

11392 12:41:56.199940  <8>[   33.646369] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>

11393 12:41:56.200204  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11395 12:41:56.222630  /lava-10724866/1/../bin/lava-test-case

11396 12:41:56.242081  <8>[   33.688484] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>

11397 12:41:56.242338  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11399 12:41:56.268297  /lava-10724866/1/../bin/lava-test-case

11400 12:41:56.289079  <8>[   33.735348] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>

11401 12:41:56.289355  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11403 12:41:56.312521  /lava-10724866/1/../bin/lava-test-case

11404 12:41:56.328779  <8>[   33.775134] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>

11405 12:41:56.329059  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11407 12:41:56.359634  /lava-10724866/1/../bin/lava-test-case

11408 12:41:56.385680  <8>[   33.831906] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>

11409 12:41:56.386401  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11411 12:41:56.412902  /lava-10724866/1/../bin/lava-test-case

11412 12:41:56.434782  <8>[   33.881382] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>

11413 12:41:56.435503  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11415 12:41:56.451988  /lava-10724866/1/../bin/lava-test-case

11416 12:41:56.471879  <8>[   33.918437] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>

11417 12:41:56.472638  Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11419 12:41:56.499457  /lava-10724866/1/../bin/lava-test-case

11420 12:41:56.521866  <8>[   33.968061] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>

11421 12:41:56.522723  Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11423 12:41:56.539328  /lava-10724866/1/../bin/lava-test-case

11424 12:41:56.561607  <8>[   34.007814] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>

11425 12:41:56.562335  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11427 12:41:56.584973  /lava-10724866/1/../bin/lava-test-case

11428 12:41:56.601288  <8>[   34.047708] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>

11429 12:41:56.601560  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11431 12:41:56.617369  /lava-10724866/1/../bin/lava-test-case

11432 12:41:56.636463  <8>[   34.082660] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>

11433 12:41:56.636734  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11435 12:41:56.668146  /lava-10724866/1/../bin/lava-test-case

11436 12:41:56.687322  <8>[   34.133860] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>

11437 12:41:56.687581  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11439 12:41:56.704541  /lava-10724866/1/../bin/lava-test-case

11440 12:41:56.723107  <8>[   34.170045] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>

11441 12:41:56.723395  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11443 12:41:56.746024  /lava-10724866/1/../bin/lava-test-case

11444 12:41:56.762958  <8>[   34.209209] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>

11445 12:41:56.763258  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11447 12:41:56.778725  /lava-10724866/1/../bin/lava-test-case

11448 12:41:56.797896  <8>[   34.244463] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>

11449 12:41:56.798165  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11451 12:41:56.819793  /lava-10724866/1/../bin/lava-test-case

11452 12:41:56.834837  <8>[   34.281445] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>

11453 12:41:56.835101  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11455 12:41:56.851253  /lava-10724866/1/../bin/lava-test-case

11456 12:41:56.869494  <8>[   34.315860] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>

11457 12:41:56.869766  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11459 12:41:56.890913  /lava-10724866/1/../bin/lava-test-case

11460 12:41:56.906994  <8>[   34.353892] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>

11461 12:41:56.907265  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11463 12:41:56.932345  /lava-10724866/1/../bin/lava-test-case

11464 12:41:56.951871  <8>[   34.397955] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>

11465 12:41:56.952798  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11467 12:41:56.979204  /lava-10724866/1/../bin/lava-test-case

11468 12:41:57.001945  <8>[   34.448809] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>

11469 12:41:57.002199  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11471 12:41:57.027661  /lava-10724866/1/../bin/lava-test-case

11472 12:41:57.051785  <8>[   34.498362] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>

11473 12:41:57.052121  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11475 12:41:57.067085  /lava-10724866/1/../bin/lava-test-case

11476 12:41:57.084876  <8>[   34.531182] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>

11477 12:41:57.085621  Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11479 12:41:57.112873  /lava-10724866/1/../bin/lava-test-case

11480 12:41:57.135498  <8>[   34.581481] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>

11481 12:41:57.136190  Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11483 12:41:57.154712  /lava-10724866/1/../bin/lava-test-case

11484 12:41:57.176938  <8>[   34.623129] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>

11485 12:41:57.177759  Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11487 12:41:58.218055  /lava-10724866/1/../bin/lava-test-case

11488 12:41:58.234754  <8>[   35.681456] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>

11489 12:41:58.235042  Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11491 12:41:58.249859  /lava-10724866/1/../bin/lava-test-case

11492 12:41:58.266158  <8>[   35.713195] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>

11493 12:41:58.266438  Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11495 12:41:59.294472  /lava-10724866/1/../bin/lava-test-case

11496 12:41:59.317265  <8>[   36.763990] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>

11497 12:41:59.317549  Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11499 12:41:59.335176  /lava-10724866/1/../bin/lava-test-case

11500 12:41:59.355251  <8>[   36.801999] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>

11501 12:41:59.355512  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11503 12:42:00.390026  /lava-10724866/1/../bin/lava-test-case

11504 12:42:00.410651  <8>[   37.857949] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>

11505 12:42:00.410994  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11507 12:42:00.427006  /lava-10724866/1/../bin/lava-test-case

11508 12:42:00.445357  <8>[   37.892541] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>

11509 12:42:00.445621  Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11511 12:42:01.472565  /lava-10724866/1/../bin/lava-test-case

11512 12:42:01.495883  <8>[   38.942732] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>

11513 12:42:01.496207  Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11515 12:42:01.511106  /lava-10724866/1/../bin/lava-test-case

11516 12:42:01.526822  <8>[   38.974219] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>

11517 12:42:01.527130  Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11519 12:42:02.558072  /lava-10724866/1/../bin/lava-test-case

11520 12:42:02.577631  <8>[   40.024894] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>

11521 12:42:02.577919  Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11523 12:42:02.596068  /lava-10724866/1/../bin/lava-test-case

11524 12:42:02.614996  <8>[   40.062208] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>

11525 12:42:02.615265  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11527 12:42:03.643017  /lava-10724866/1/../bin/lava-test-case

11528 12:42:03.667315  <8>[   41.114564] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>

11529 12:42:03.667614  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11531 12:42:03.685502  /lava-10724866/1/../bin/lava-test-case

11532 12:42:03.705111  <8>[   41.152569] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>

11533 12:42:03.705399  Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11535 12:42:04.739968  /lava-10724866/1/../bin/lava-test-case

11536 12:42:04.760249  <8>[   42.207586] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>

11537 12:42:04.760611  Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11539 12:42:04.775947  /lava-10724866/1/../bin/lava-test-case

11540 12:42:04.793772  <8>[   42.241377] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>

11541 12:42:04.794113  Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11543 12:42:04.810263  /lava-10724866/1/../bin/lava-test-case

11544 12:42:04.829442  <8>[   42.276886] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>

11545 12:42:04.829717  Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11547 12:42:05.859495  /lava-10724866/1/../bin/lava-test-case

11548 12:42:05.878359  <8>[   43.326248] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>

11549 12:42:05.878703  Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11551 12:42:05.895583  /lava-10724866/1/../bin/lava-test-case

11552 12:42:05.914039  <8>[   43.361711] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>

11553 12:42:05.914358  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11555 12:42:05.939563  /lava-10724866/1/../bin/lava-test-case

11556 12:42:05.958706  <8>[   43.406491] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>

11557 12:42:05.959000  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11559 12:42:05.973502  /lava-10724866/1/../bin/lava-test-case

11560 12:42:05.989690  <8>[   43.437655] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>

11561 12:42:05.989969  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11563 12:42:06.014980  /lava-10724866/1/../bin/lava-test-case

11564 12:42:06.034215  <8>[   43.482011] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>

11565 12:42:06.034507  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11567 12:42:06.057902  /lava-10724866/1/../bin/lava-test-case

11568 12:42:06.074884  <8>[   43.522816] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>

11569 12:42:06.075176  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11571 12:42:06.099684  /lava-10724866/1/../bin/lava-test-case

11572 12:42:06.118705  <8>[   43.566491] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>

11573 12:42:06.118992  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11575 12:42:06.134546  /lava-10724866/1/../bin/lava-test-case

11576 12:42:06.151382  <8>[   43.598888] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>

11577 12:42:06.151651  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11579 12:42:06.183278  /lava-10724866/1/../bin/lava-test-case

11580 12:42:06.198249  <8>[   43.646073] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>

11581 12:42:06.198540  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11583 12:42:06.223168  /lava-10724866/1/../bin/lava-test-case

11584 12:42:06.241208  <8>[   43.689092] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>

11585 12:42:06.241491  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11587 12:42:06.258613  /lava-10724866/1/../bin/lava-test-case

11588 12:42:06.277118  <8>[   43.725163] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>

11589 12:42:06.277388  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11591 12:42:06.301648  /lava-10724866/1/../bin/lava-test-case

11592 12:42:06.320455  <8>[   43.768389] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>

11593 12:42:06.320736  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11595 12:42:06.336379  /lava-10724866/1/../bin/lava-test-case

11596 12:42:06.354680  <8>[   43.802248] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>

11597 12:42:06.354956  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11599 12:42:06.378399  /lava-10724866/1/../bin/lava-test-case

11600 12:42:06.396157  <8>[   43.843912] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>

11601 12:42:06.396435  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11603 12:42:06.413028  /lava-10724866/1/../bin/lava-test-case

11604 12:42:06.430951  <8>[   43.878631] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>

11605 12:42:06.431269  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11607 12:42:06.454692  /lava-10724866/1/../bin/lava-test-case

11608 12:42:06.471498  <8>[   43.919182] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>

11609 12:42:06.471793  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11611 12:42:06.495879  /lava-10724866/1/../bin/lava-test-case

11612 12:42:06.511653  <8>[   43.959394] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>

11613 12:42:06.511940  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11615 12:42:06.533079  /lava-10724866/1/../bin/lava-test-case

11616 12:42:06.552941  <8>[   44.000465] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>

11617 12:42:06.553211  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11619 12:42:06.567598  /lava-10724866/1/../bin/lava-test-case

11620 12:42:06.583525  <8>[   44.031347] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>

11621 12:42:06.583804  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11623 12:42:06.604454  /lava-10724866/1/../bin/lava-test-case

11624 12:42:06.620831  <8>[   44.068781] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>

11625 12:42:06.621105  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11627 12:42:06.635158  /lava-10724866/1/../bin/lava-test-case

11628 12:42:06.651409  <8>[   44.099049] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>

11629 12:42:06.651704  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11631 12:42:07.682518  /lava-10724866/1/../bin/lava-test-case

11632 12:42:07.701574  <8>[   45.149389] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>

11633 12:42:07.701912  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11635 12:42:08.700402  <6>[   46.155029] vpu: disabling

11636 12:42:08.703883  <6>[   46.158070] vproc2: disabling

11637 12:42:08.707151  <6>[   46.161342] vproc1: disabling

11638 12:42:08.710286  <6>[   46.164602] vaud18: disabling

11639 12:42:08.716867  <6>[   46.168002] vsram_others: disabling

11640 12:42:08.716959  <6>[   46.171871] va09: disabling

11641 12:42:08.723366  <6>[   46.174974] vsram_md: disabling

11642 12:42:08.723518  <6>[   46.178455] Vgpu: disabling

11643 12:42:08.730084  /lava-10724866/1/../bin/lava-test-case

11644 12:42:08.750420  <8>[   46.198318] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>

11645 12:42:08.750785  Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11647 12:42:08.764740  /lava-10724866/1/../bin/lava-test-case

11648 12:42:08.781228  <8>[   46.229586] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>

11649 12:42:08.781539  Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11651 12:42:08.802875  /lava-10724866/1/../bin/lava-test-case

11652 12:42:08.819158  <8>[   46.267041] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>

11653 12:42:08.819499  Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11655 12:42:08.834794  /lava-10724866/1/../bin/lava-test-case

11656 12:42:08.849926  <8>[   46.297881] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>

11657 12:42:08.850236  Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11659 12:42:08.870784  /lava-10724866/1/../bin/lava-test-case

11660 12:42:08.888997  <8>[   46.336756] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>

11661 12:42:08.889321  Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11663 12:42:08.904558  /lava-10724866/1/../bin/lava-test-case

11664 12:42:08.924642  <8>[   46.372467] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>

11665 12:42:08.924955  Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11667 12:42:08.946949  /lava-10724866/1/../bin/lava-test-case

11668 12:42:08.964510  <8>[   46.412895] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>

11669 12:42:08.964831  Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11671 12:42:08.994573  /lava-10724866/1/../bin/lava-test-case

11672 12:42:09.010044  <8>[   46.458375] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>

11673 12:42:09.010348  Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11675 12:42:09.031562  /lava-10724866/1/../bin/lava-test-case

11676 12:42:09.049468  <8>[   46.497499] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>

11677 12:42:09.049780  Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11679 12:42:09.066370  /lava-10724866/1/../bin/lava-test-case

11680 12:42:09.085614  <8>[   46.533495] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>

11681 12:42:09.085959  Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11683 12:42:09.108235  /lava-10724866/1/../bin/lava-test-case

11684 12:42:09.125996  <8>[   46.573899] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>

11685 12:42:09.126297  Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11687 12:42:09.141424  /lava-10724866/1/../bin/lava-test-case

11688 12:42:09.160933  <8>[   46.608952] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>

11689 12:42:09.161239  Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11691 12:42:09.182969  /lava-10724866/1/../bin/lava-test-case

11692 12:42:09.201836  <8>[   46.649848] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>

11693 12:42:09.202132  Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11695 12:42:09.217775  /lava-10724866/1/../bin/lava-test-case

11696 12:42:09.235558  <8>[   46.683329] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>

11697 12:42:09.235861  Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11699 12:42:09.257872  /lava-10724866/1/../bin/lava-test-case

11700 12:42:09.274586  <8>[   46.722433] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>

11701 12:42:09.274903  Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11703 12:42:09.297613  /lava-10724866/1/../bin/lava-test-case

11704 12:42:09.312947  <8>[   46.761240] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>

11705 12:42:09.313280  Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11707 12:42:09.335305  /lava-10724866/1/../bin/lava-test-case

11708 12:42:09.355222  <8>[   46.803250] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>

11709 12:42:09.355547  Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11711 12:42:09.369227  /lava-10724866/1/../bin/lava-test-case

11712 12:42:09.386164  <8>[   46.834105] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>

11713 12:42:09.386486  Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11715 12:42:09.407587  /lava-10724866/1/../bin/lava-test-case

11716 12:42:09.425375  <8>[   46.873822] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>

11717 12:42:09.425693  Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11719 12:42:09.439546  /lava-10724866/1/../bin/lava-test-case

11720 12:42:09.455565  <8>[   46.903973] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>

11721 12:42:09.455839  Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11723 12:42:09.478250  /lava-10724866/1/../bin/lava-test-case

11724 12:42:09.496492  <8>[   46.944456] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>

11725 12:42:09.496828  Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11727 12:42:10.516526  /lava-10724866/1/../bin/lava-test-case

11728 12:42:10.541225  <8>[   47.989461] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>

11729 12:42:10.541560  Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11731 12:42:11.564161  /lava-10724866/1/../bin/lava-test-case

11732 12:42:11.586167  <8>[   49.034773] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>

11733 12:42:11.586482  Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11734 12:42:11.586568  Bad test result: blocked
11735 12:42:11.601799  /lava-10724866/1/../bin/lava-test-case

11736 12:42:11.618143  <8>[   49.066438] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>

11737 12:42:11.618440  Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11739 12:42:12.645495  /lava-10724866/1/../bin/lava-test-case

11740 12:42:12.664978  <8>[   50.113577] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>

11741 12:42:12.665286  Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11743 12:42:12.682560  /lava-10724866/1/../bin/lava-test-case

11744 12:42:12.699898  <8>[   50.148625] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>

11745 12:42:12.700204  Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11747 12:42:12.723593  /lava-10724866/1/../bin/lava-test-case

11748 12:42:12.742619  <8>[   50.190998] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>

11749 12:42:12.742941  Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11751 12:42:12.762905  /lava-10724866/1/../bin/lava-test-case

11752 12:42:12.778630  <8>[   50.227324] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>

11753 12:42:12.778947  Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11755 12:42:12.793861  /lava-10724866/1/../bin/lava-test-case

11756 12:42:12.810190  <8>[   50.258562] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>

11757 12:42:12.810523  Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11759 12:42:12.832174  /lava-10724866/1/../bin/lava-test-case

11760 12:42:12.849393  <8>[   50.297734] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>

11761 12:42:12.849698  Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11763 12:42:12.865134  /lava-10724866/1/../bin/lava-test-case

11764 12:42:12.884517  <8>[   50.332742] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>

11765 12:42:12.884832  Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11767 12:42:13.913896  /lava-10724866/1/../bin/lava-test-case

11768 12:42:13.931106  <8>[   51.380044] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>

11769 12:42:13.931456  Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11771 12:42:13.946642  /lava-10724866/1/../bin/lava-test-case

11772 12:42:13.962503  <8>[   51.411049] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>

11773 12:42:13.962838  Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11775 12:42:14.989770  /lava-10724866/1/../bin/lava-test-case

11776 12:42:15.013006  <8>[   52.461569] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>

11777 12:42:15.013299  Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11779 12:42:15.028874  /lava-10724866/1/../bin/lava-test-case

11780 12:42:15.045523  <8>[   52.494631] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>

11781 12:42:15.045805  Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11783 12:42:16.074269  /lava-10724866/1/../bin/lava-test-case

11784 12:42:16.098394  <8>[   53.547555] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>

11785 12:42:16.098757  Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11787 12:42:16.113518  /lava-10724866/1/../bin/lava-test-case

11788 12:42:16.129570  <8>[   53.578079] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>

11789 12:42:16.129887  Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11791 12:42:17.156958  /lava-10724866/1/../bin/lava-test-case

11792 12:42:17.177799  <8>[   54.626978] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>

11793 12:42:17.178132  Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11795 12:42:17.193925  /lava-10724866/1/../bin/lava-test-case

11796 12:42:17.212252  <8>[   54.661412] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>

11797 12:42:17.212592  Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11799 12:42:17.234982  /lava-10724866/1/../bin/lava-test-case

11800 12:42:17.253669  <8>[   54.702911] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>

11801 12:42:17.253979  Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11803 12:42:17.279611  /lava-10724866/1/../bin/lava-test-case

11804 12:42:17.297444  <8>[   54.746675] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>

11805 12:42:17.297757  Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11807 12:42:17.315931  /lava-10724866/1/../bin/lava-test-case

11808 12:42:17.335006  <8>[   54.784088] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>

11809 12:42:17.335287  Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11811 12:42:17.360489  /lava-10724866/1/../bin/lava-test-case

11812 12:42:17.381810  <8>[   54.830355] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>

11813 12:42:17.382086  Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11815 12:42:17.399886  /lava-10724866/1/../bin/lava-test-case

11816 12:42:17.420619  <8>[   54.869003] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>

11817 12:42:17.421290  Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11819 12:42:17.444117  /lava-10724866/1/../bin/lava-test-case

11820 12:42:17.461017  <8>[   54.909819] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>

11821 12:42:17.461303  Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11823 12:42:17.484124  /lava-10724866/1/../bin/lava-test-case

11824 12:42:17.501129  <8>[   54.950015] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>

11825 12:42:17.501400  Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11827 12:42:18.532604  /lava-10724866/1/../bin/lava-test-case

11828 12:42:18.556033  <8>[   56.005436] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail>

11829 12:42:18.556315  Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail
11831 12:42:18.560573  + set +x

11832 12:42:18.564731  Received signal: <ENDRUN> 1_bootrr 10724866_1.6.2.3.5
11833 12:42:18.564859  Ending use of test pattern.
11834 12:42:18.564955  Ending test lava.1_bootrr (10724866_1.6.2.3.5), duration 27.64
11836 12:42:18.567659  <8>[   56.016594] <LAVA_SIGNAL_ENDRUN 1_bootrr 10724866_1.6.2.3.5>

11837 12:42:18.571024  <LAVA_TEST_RUNNER EXIT>

11838 12:42:18.571273  ok: lava_test_shell seems to have completed
11839 12:42:18.572234  all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: fail
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: fail
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: skip
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass

11840 12:42:18.572377  end: 4.1 lava-test-shell (duration 00:00:28) [common]
11841 12:42:18.572462  end: 4 lava-test-retry (duration 00:00:28) [common]
11842 12:42:18.572548  start: 5 finalize (timeout 00:07:37) [common]
11843 12:42:18.572636  start: 5.1 power-off (timeout 00:00:30) [common]
11844 12:42:18.572820  Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11845 12:42:18.650208  >> Command sent successfully.

11846 12:42:18.657216  Returned 0 in 0 seconds
11847 12:42:18.758153  end: 5.1 power-off (duration 00:00:00) [common]
11849 12:42:18.760114  start: 5.2 read-feedback (timeout 00:07:37) [common]
11850 12:42:18.761428  Listened to connection for namespace 'common' for up to 1s
11851 12:42:19.761897  Finalising connection for namespace 'common'
11852 12:42:19.762099  Disconnecting from shell: Finalise
11853 12:42:19.762200  / # 
11854 12:42:19.862773  end: 5.2 read-feedback (duration 00:00:01) [common]
11855 12:42:19.863099  end: 5 finalize (duration 00:00:01) [common]
11856 12:42:19.863374  Cleaning after the job
11857 12:42:19.863630  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724866/tftp-deploy-7g8zvg_1/ramdisk
11858 12:42:19.868390  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724866/tftp-deploy-7g8zvg_1/kernel
11859 12:42:19.891943  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724866/tftp-deploy-7g8zvg_1/dtb
11860 12:42:19.892343  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724866/tftp-deploy-7g8zvg_1/nfsrootfs
11861 12:42:19.955739  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724866/tftp-deploy-7g8zvg_1/modules
11862 12:42:19.961364  Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10724866
11863 12:42:20.276115  Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10724866
11864 12:42:20.276283  Job finished correctly