Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 34
- Boot result: FAIL
- Warnings: 1
- Kernel Warnings: 27
- Errors: 2
1 12:42:45.651178 lava-dispatcher, installed at version: 2023.05.1
2 12:42:45.651397 start: 0 validate
3 12:42:45.651528 Start time: 2023-06-14 12:42:45.651521+00:00 (UTC)
4 12:42:45.651650 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:42:45.651777 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230609.0%2Farm64%2Frootfs.cpio.gz exists
6 12:42:45.920861 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:42:45.921036 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:42:46.185345 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:42:46.185518 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:42:46.444605 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:42:46.444769 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:42:46.694796 validate duration: 1.04
14 12:42:46.695129 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:42:46.695262 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:42:46.695402 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:42:46.695570 Not decompressing ramdisk as can be used compressed.
18 12:42:46.695684 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230609.0/arm64/rootfs.cpio.gz
19 12:42:46.695776 saving as /var/lib/lava/dispatcher/tmp/10724859/tftp-deploy-wksjipk0/ramdisk/rootfs.cpio.gz
20 12:42:46.695866 total size: 43386660 (41MB)
21 12:42:46.697439 progress 0% (0MB)
22 12:42:46.709028 progress 5% (2MB)
23 12:42:46.720047 progress 10% (4MB)
24 12:42:46.731347 progress 15% (6MB)
25 12:42:46.743399 progress 20% (8MB)
26 12:42:46.755570 progress 25% (10MB)
27 12:42:46.767369 progress 30% (12MB)
28 12:42:46.779559 progress 35% (14MB)
29 12:42:46.791667 progress 40% (16MB)
30 12:42:46.803633 progress 45% (18MB)
31 12:42:46.815832 progress 50% (20MB)
32 12:42:46.827660 progress 55% (22MB)
33 12:42:46.839679 progress 60% (24MB)
34 12:42:46.851416 progress 65% (26MB)
35 12:42:46.862934 progress 70% (28MB)
36 12:42:46.874905 progress 75% (31MB)
37 12:42:46.886709 progress 80% (33MB)
38 12:42:46.898631 progress 85% (35MB)
39 12:42:46.910174 progress 90% (37MB)
40 12:42:46.921671 progress 95% (39MB)
41 12:42:46.933268 progress 100% (41MB)
42 12:42:46.933438 41MB downloaded in 0.24s (174.17MB/s)
43 12:42:46.933644 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:42:46.934016 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:42:46.934108 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:42:46.934190 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:42:46.934325 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:42:46.934428 saving as /var/lib/lava/dispatcher/tmp/10724859/tftp-deploy-wksjipk0/kernel/Image
50 12:42:46.934521 total size: 47581696 (45MB)
51 12:42:46.934613 No compression specified
52 12:42:46.936188 progress 0% (0MB)
53 12:42:46.948790 progress 5% (2MB)
54 12:42:46.961557 progress 10% (4MB)
55 12:42:46.974267 progress 15% (6MB)
56 12:42:46.987315 progress 20% (9MB)
57 12:42:47.000232 progress 25% (11MB)
58 12:42:47.013390 progress 30% (13MB)
59 12:42:47.026166 progress 35% (15MB)
60 12:42:47.038870 progress 40% (18MB)
61 12:42:47.051593 progress 45% (20MB)
62 12:42:47.064299 progress 50% (22MB)
63 12:42:47.077144 progress 55% (24MB)
64 12:42:47.089962 progress 60% (27MB)
65 12:42:47.102652 progress 65% (29MB)
66 12:42:47.115459 progress 70% (31MB)
67 12:42:47.128263 progress 75% (34MB)
68 12:42:47.140987 progress 80% (36MB)
69 12:42:47.153748 progress 85% (38MB)
70 12:42:47.166119 progress 90% (40MB)
71 12:42:47.178973 progress 95% (43MB)
72 12:42:47.191672 progress 100% (45MB)
73 12:42:47.191847 45MB downloaded in 0.26s (176.34MB/s)
74 12:42:47.192056 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:42:47.192424 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:42:47.192539 start: 1.3 download-retry (timeout 00:10:00) [common]
78 12:42:47.192658 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 12:42:47.192829 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:42:47.192932 saving as /var/lib/lava/dispatcher/tmp/10724859/tftp-deploy-wksjipk0/dtb/mt8192-asurada-spherion-r0.dtb
81 12:42:47.193038 total size: 46924 (0MB)
82 12:42:47.193104 No compression specified
83 12:42:47.194294 progress 69% (0MB)
84 12:42:47.194593 progress 100% (0MB)
85 12:42:47.194780 0MB downloaded in 0.00s (25.73MB/s)
86 12:42:47.194945 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:42:47.195315 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:42:47.195432 start: 1.4 download-retry (timeout 00:09:59) [common]
90 12:42:47.195544 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 12:42:47.195687 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:42:47.195782 saving as /var/lib/lava/dispatcher/tmp/10724859/tftp-deploy-wksjipk0/modules/modules.tar
93 12:42:47.195870 total size: 8536768 (8MB)
94 12:42:47.195961 Using unxz to decompress xz
95 12:42:47.200093 progress 0% (0MB)
96 12:42:47.220858 progress 5% (0MB)
97 12:42:47.247708 progress 10% (0MB)
98 12:42:47.278954 progress 15% (1MB)
99 12:42:47.302898 progress 20% (1MB)
100 12:42:47.326351 progress 25% (2MB)
101 12:42:47.350810 progress 30% (2MB)
102 12:42:47.374150 progress 35% (2MB)
103 12:42:47.401482 progress 40% (3MB)
104 12:42:47.426270 progress 45% (3MB)
105 12:42:47.452091 progress 50% (4MB)
106 12:42:47.476956 progress 55% (4MB)
107 12:42:47.502827 progress 60% (4MB)
108 12:42:47.528229 progress 65% (5MB)
109 12:42:47.552969 progress 70% (5MB)
110 12:42:47.577431 progress 75% (6MB)
111 12:42:47.601514 progress 80% (6MB)
112 12:42:47.625248 progress 85% (6MB)
113 12:42:47.650272 progress 90% (7MB)
114 12:42:47.674878 progress 95% (7MB)
115 12:42:47.697567 progress 100% (8MB)
116 12:42:47.704230 8MB downloaded in 0.51s (16.02MB/s)
117 12:42:47.704552 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:42:47.704988 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:42:47.705108 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 12:42:47.705241 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 12:42:47.705377 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:42:47.705506 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 12:42:47.705787 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10724859/lava-overlay-433iwzx5
125 12:42:47.705954 makedir: /var/lib/lava/dispatcher/tmp/10724859/lava-overlay-433iwzx5/lava-10724859/bin
126 12:42:47.706089 makedir: /var/lib/lava/dispatcher/tmp/10724859/lava-overlay-433iwzx5/lava-10724859/tests
127 12:42:47.706224 makedir: /var/lib/lava/dispatcher/tmp/10724859/lava-overlay-433iwzx5/lava-10724859/results
128 12:42:47.706383 Creating /var/lib/lava/dispatcher/tmp/10724859/lava-overlay-433iwzx5/lava-10724859/bin/lava-add-keys
129 12:42:47.706559 Creating /var/lib/lava/dispatcher/tmp/10724859/lava-overlay-433iwzx5/lava-10724859/bin/lava-add-sources
130 12:42:47.706726 Creating /var/lib/lava/dispatcher/tmp/10724859/lava-overlay-433iwzx5/lava-10724859/bin/lava-background-process-start
131 12:42:47.706891 Creating /var/lib/lava/dispatcher/tmp/10724859/lava-overlay-433iwzx5/lava-10724859/bin/lava-background-process-stop
132 12:42:47.707060 Creating /var/lib/lava/dispatcher/tmp/10724859/lava-overlay-433iwzx5/lava-10724859/bin/lava-common-functions
133 12:42:47.707213 Creating /var/lib/lava/dispatcher/tmp/10724859/lava-overlay-433iwzx5/lava-10724859/bin/lava-echo-ipv4
134 12:42:47.707372 Creating /var/lib/lava/dispatcher/tmp/10724859/lava-overlay-433iwzx5/lava-10724859/bin/lava-install-packages
135 12:42:47.707526 Creating /var/lib/lava/dispatcher/tmp/10724859/lava-overlay-433iwzx5/lava-10724859/bin/lava-installed-packages
136 12:42:47.707676 Creating /var/lib/lava/dispatcher/tmp/10724859/lava-overlay-433iwzx5/lava-10724859/bin/lava-os-build
137 12:42:47.707828 Creating /var/lib/lava/dispatcher/tmp/10724859/lava-overlay-433iwzx5/lava-10724859/bin/lava-probe-channel
138 12:42:47.707968 Creating /var/lib/lava/dispatcher/tmp/10724859/lava-overlay-433iwzx5/lava-10724859/bin/lava-probe-ip
139 12:42:47.708088 Creating /var/lib/lava/dispatcher/tmp/10724859/lava-overlay-433iwzx5/lava-10724859/bin/lava-target-ip
140 12:42:47.708230 Creating /var/lib/lava/dispatcher/tmp/10724859/lava-overlay-433iwzx5/lava-10724859/bin/lava-target-mac
141 12:42:47.708421 Creating /var/lib/lava/dispatcher/tmp/10724859/lava-overlay-433iwzx5/lava-10724859/bin/lava-target-storage
142 12:42:47.708601 Creating /var/lib/lava/dispatcher/tmp/10724859/lava-overlay-433iwzx5/lava-10724859/bin/lava-test-case
143 12:42:47.708770 Creating /var/lib/lava/dispatcher/tmp/10724859/lava-overlay-433iwzx5/lava-10724859/bin/lava-test-event
144 12:42:47.708970 Creating /var/lib/lava/dispatcher/tmp/10724859/lava-overlay-433iwzx5/lava-10724859/bin/lava-test-feedback
145 12:42:47.709125 Creating /var/lib/lava/dispatcher/tmp/10724859/lava-overlay-433iwzx5/lava-10724859/bin/lava-test-raise
146 12:42:47.709281 Creating /var/lib/lava/dispatcher/tmp/10724859/lava-overlay-433iwzx5/lava-10724859/bin/lava-test-reference
147 12:42:47.709434 Creating /var/lib/lava/dispatcher/tmp/10724859/lava-overlay-433iwzx5/lava-10724859/bin/lava-test-runner
148 12:42:47.709590 Creating /var/lib/lava/dispatcher/tmp/10724859/lava-overlay-433iwzx5/lava-10724859/bin/lava-test-set
149 12:42:47.709747 Creating /var/lib/lava/dispatcher/tmp/10724859/lava-overlay-433iwzx5/lava-10724859/bin/lava-test-shell
150 12:42:47.709903 Updating /var/lib/lava/dispatcher/tmp/10724859/lava-overlay-433iwzx5/lava-10724859/bin/lava-install-packages (oe)
151 12:42:47.710054 Updating /var/lib/lava/dispatcher/tmp/10724859/lava-overlay-433iwzx5/lava-10724859/bin/lava-installed-packages (oe)
152 12:42:47.710210 Creating /var/lib/lava/dispatcher/tmp/10724859/lava-overlay-433iwzx5/lava-10724859/environment
153 12:42:47.710365 LAVA metadata
154 12:42:47.710469 - LAVA_JOB_ID=10724859
155 12:42:47.710569 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:42:47.710704 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 12:42:47.710803 skipped lava-vland-overlay
158 12:42:47.710913 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:42:47.711037 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 12:42:47.711132 skipped lava-multinode-overlay
161 12:42:47.711238 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:42:47.711350 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 12:42:47.711458 Loading test definitions
164 12:42:47.711585 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 12:42:47.711703 Using /lava-10724859 at stage 0
166 12:42:47.712126 uuid=10724859_1.5.2.3.1 testdef=None
167 12:42:47.712257 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:42:47.712378 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 12:42:47.713151 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:42:47.713505 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 12:42:47.714424 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:42:47.714800 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 12:42:47.715655 runner path: /var/lib/lava/dispatcher/tmp/10724859/lava-overlay-433iwzx5/lava-10724859/0/tests/0_igt-gpu-panfrost test_uuid 10724859_1.5.2.3.1
176 12:42:47.715845 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:42:47.716180 Creating lava-test-runner.conf files
179 12:42:47.716273 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10724859/lava-overlay-433iwzx5/lava-10724859/0 for stage 0
180 12:42:47.716393 - 0_igt-gpu-panfrost
181 12:42:47.716552 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 12:42:47.716694 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 12:42:47.725256 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 12:42:47.725394 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 12:42:47.725528 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 12:42:47.725653 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 12:42:47.725785 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 12:42:49.087982 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 12:42:49.088338 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 12:42:49.088454 extracting modules file /var/lib/lava/dispatcher/tmp/10724859/tftp-deploy-wksjipk0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10724859/extract-overlay-ramdisk-o176njbh/ramdisk
191 12:42:49.300775 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 12:42:49.300932 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 12:42:49.301028 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10724859/compress-overlay-a5d5eqei/overlay-1.5.2.4.tar.gz to ramdisk
194 12:42:49.301099 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10724859/compress-overlay-a5d5eqei/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10724859/extract-overlay-ramdisk-o176njbh/ramdisk
195 12:42:49.307337 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 12:42:49.307454 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 12:42:49.307544 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 12:42:49.307634 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 12:42:49.307713 Building ramdisk /var/lib/lava/dispatcher/tmp/10724859/extract-overlay-ramdisk-o176njbh/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10724859/extract-overlay-ramdisk-o176njbh/ramdisk
200 12:42:50.268829 >> 369088 blocks
201 12:42:56.349670 rename /var/lib/lava/dispatcher/tmp/10724859/extract-overlay-ramdisk-o176njbh/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10724859/tftp-deploy-wksjipk0/ramdisk/ramdisk.cpio.gz
202 12:42:56.350138 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 12:42:56.350262 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 12:42:56.350372 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 12:42:56.350486 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10724859/tftp-deploy-wksjipk0/kernel/Image'
206 12:43:08.660096 Returned 0 in 12 seconds
207 12:43:08.760705 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10724859/tftp-deploy-wksjipk0/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10724859/tftp-deploy-wksjipk0/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10724859/tftp-deploy-wksjipk0/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10724859/tftp-deploy-wksjipk0/kernel/image.itb
208 12:43:09.511743 output: FIT description: Kernel Image image with one or more FDT blobs
209 12:43:09.512124 output: Created: Wed Jun 14 13:43:09 2023
210 12:43:09.512231 output: Image 0 (kernel-1)
211 12:43:09.512331 output: Description:
212 12:43:09.512400 output: Created: Wed Jun 14 13:43:09 2023
213 12:43:09.512462 output: Type: Kernel Image
214 12:43:09.512524 output: Compression: lzma compressed
215 12:43:09.512586 output: Data Size: 10442380 Bytes = 10197.64 KiB = 9.96 MiB
216 12:43:09.512645 output: Architecture: AArch64
217 12:43:09.512724 output: OS: Linux
218 12:43:09.512837 output: Load Address: 0x00000000
219 12:43:09.512915 output: Entry Point: 0x00000000
220 12:43:09.512973 output: Hash algo: crc32
221 12:43:09.513029 output: Hash value: ced21bfe
222 12:43:09.513084 output: Image 1 (fdt-1)
223 12:43:09.513138 output: Description: mt8192-asurada-spherion-r0
224 12:43:09.513192 output: Created: Wed Jun 14 13:43:09 2023
225 12:43:09.513246 output: Type: Flat Device Tree
226 12:43:09.513299 output: Compression: uncompressed
227 12:43:09.513353 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 12:43:09.513406 output: Architecture: AArch64
229 12:43:09.513460 output: Hash algo: crc32
230 12:43:09.513513 output: Hash value: 1df858fa
231 12:43:09.513567 output: Image 2 (ramdisk-1)
232 12:43:09.513620 output: Description: unavailable
233 12:43:09.513673 output: Created: Wed Jun 14 13:43:09 2023
234 12:43:09.513726 output: Type: RAMDisk Image
235 12:43:09.513779 output: Compression: Unknown Compression
236 12:43:09.513833 output: Data Size: 56380861 Bytes = 55059.43 KiB = 53.77 MiB
237 12:43:09.513886 output: Architecture: AArch64
238 12:43:09.513939 output: OS: Linux
239 12:43:09.513992 output: Load Address: unavailable
240 12:43:09.514045 output: Entry Point: unavailable
241 12:43:09.514098 output: Hash algo: crc32
242 12:43:09.514151 output: Hash value: 2ded95b5
243 12:43:09.514203 output: Default Configuration: 'conf-1'
244 12:43:09.514257 output: Configuration 0 (conf-1)
245 12:43:09.514309 output: Description: mt8192-asurada-spherion-r0
246 12:43:09.514362 output: Kernel: kernel-1
247 12:43:09.514415 output: Init Ramdisk: ramdisk-1
248 12:43:09.514468 output: FDT: fdt-1
249 12:43:09.514521 output: Loadables: kernel-1
250 12:43:09.514574 output:
251 12:43:09.514766 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 12:43:09.514862 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 12:43:09.514972 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 12:43:09.515065 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
255 12:43:09.515145 No LXC device requested
256 12:43:09.515224 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 12:43:09.515344 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
258 12:43:09.515469 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 12:43:09.515546 Checking files for TFTP limit of 4294967296 bytes.
260 12:43:09.516045 end: 1 tftp-deploy (duration 00:00:23) [common]
261 12:43:09.516153 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 12:43:09.516245 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 12:43:09.516362 substitutions:
264 12:43:09.516431 - {DTB}: 10724859/tftp-deploy-wksjipk0/dtb/mt8192-asurada-spherion-r0.dtb
265 12:43:09.516500 - {INITRD}: 10724859/tftp-deploy-wksjipk0/ramdisk/ramdisk.cpio.gz
266 12:43:09.516560 - {KERNEL}: 10724859/tftp-deploy-wksjipk0/kernel/Image
267 12:43:09.516619 - {LAVA_MAC}: None
268 12:43:09.516675 - {PRESEED_CONFIG}: None
269 12:43:09.516731 - {PRESEED_LOCAL}: None
270 12:43:09.516787 - {RAMDISK}: 10724859/tftp-deploy-wksjipk0/ramdisk/ramdisk.cpio.gz
271 12:43:09.516888 - {ROOT_PART}: None
272 12:43:09.516944 - {ROOT}: None
273 12:43:09.516998 - {SERVER_IP}: 192.168.201.1
274 12:43:09.517052 - {TEE}: None
275 12:43:09.517106 Parsed boot commands:
276 12:43:09.517160 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 12:43:09.517330 Parsed boot commands: tftpboot 192.168.201.1 10724859/tftp-deploy-wksjipk0/kernel/image.itb 10724859/tftp-deploy-wksjipk0/kernel/cmdline
278 12:43:09.517419 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 12:43:09.517505 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 12:43:09.517597 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 12:43:09.517682 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 12:43:09.517754 Not connected, no need to disconnect.
283 12:43:09.517828 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 12:43:09.517906 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 12:43:09.517972 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-0'
286 12:43:09.521475 Setting prompt string to ['lava-test: # ']
287 12:43:09.521876 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 12:43:09.522005 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 12:43:09.522108 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 12:43:09.522202 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 12:43:09.522399 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 12:43:14.660433 >> Command sent successfully.
293 12:43:14.662828 Returned 0 in 5 seconds
294 12:43:14.763186 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 12:43:14.763745 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 12:43:14.763846 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 12:43:14.763934 Setting prompt string to 'Starting depthcharge on Spherion...'
299 12:43:14.764005 Changing prompt to 'Starting depthcharge on Spherion...'
300 12:43:14.764078 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 12:43:14.764384 [Enter `^Ec?' for help]
302 12:43:14.935919
303 12:43:14.936062
304 12:43:14.936137 F0: 102B 0000
305 12:43:14.936200
306 12:43:14.939675 F3: 1001 0000 [0200]
307 12:43:14.939759
308 12:43:14.939823 F3: 1001 0000
309 12:43:14.939884
310 12:43:14.939942 F7: 102D 0000
311 12:43:14.940000
312 12:43:14.943579 F1: 0000 0000
313 12:43:14.943663
314 12:43:14.943728 V0: 0000 0000 [0001]
315 12:43:14.943792
316 12:43:14.943850 00: 0007 8000
317 12:43:14.943911
318 12:43:14.947525 01: 0000 0000
319 12:43:14.947608
320 12:43:14.947673 BP: 0C00 0209 [0000]
321 12:43:14.947734
322 12:43:14.950818 G0: 1182 0000
323 12:43:14.950900
324 12:43:14.950965 EC: 0000 0021 [4000]
325 12:43:14.951025
326 12:43:14.954541 S7: 0000 0000 [0000]
327 12:43:14.954624
328 12:43:14.954688 CC: 0000 0000 [0001]
329 12:43:14.954750
330 12:43:14.958268 T0: 0000 0040 [010F]
331 12:43:14.958351
332 12:43:14.958417 Jump to BL
333 12:43:14.958477
334 12:43:14.983496
335 12:43:14.983589
336 12:43:14.983655
337 12:43:14.991017 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 12:43:14.994314 ARM64: Exception handlers installed.
339 12:43:14.998313 ARM64: Testing exception
340 12:43:15.002319 ARM64: Done test exception
341 12:43:15.005619 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 12:43:15.017303 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 12:43:15.024481 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 12:43:15.034503 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 12:43:15.040652 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 12:43:15.050939 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 12:43:15.061472 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 12:43:15.068260 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 12:43:15.086435 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 12:43:15.089698 WDT: Last reset was cold boot
351 12:43:15.093086 SPI1(PAD0) initialized at 2873684 Hz
352 12:43:15.096115 SPI5(PAD0) initialized at 992727 Hz
353 12:43:15.099469 VBOOT: Loading verstage.
354 12:43:15.105965 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 12:43:15.109367 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 12:43:15.112722 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 12:43:15.116153 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 12:43:15.123265 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 12:43:15.130270 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 12:43:15.140950 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 12:43:15.141072
362 12:43:15.141137
363 12:43:15.151497 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 12:43:15.154586 ARM64: Exception handlers installed.
365 12:43:15.158498 ARM64: Testing exception
366 12:43:15.158580 ARM64: Done test exception
367 12:43:15.165105 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 12:43:15.168198 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 12:43:15.182233 Probing TPM: . done!
370 12:43:15.182317 TPM ready after 0 ms
371 12:43:15.189674 Connected to device vid:did:rid of 1ae0:0028:00
372 12:43:15.196445 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
373 12:43:15.256920 Initialized TPM device CR50 revision 0
374 12:43:15.268584 tlcl_send_startup: Startup return code is 0
375 12:43:15.268750 TPM: setup succeeded
376 12:43:15.280342 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 12:43:15.289042 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 12:43:15.303428 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 12:43:15.310482 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 12:43:15.313866 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 12:43:15.317911 in-header: 03 07 00 00 08 00 00 00
382 12:43:15.321206 in-data: aa e4 47 04 13 02 00 00
383 12:43:15.321293 Chrome EC: UHEPI supported
384 12:43:15.329274 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 12:43:15.333227 in-header: 03 95 00 00 08 00 00 00
386 12:43:15.337064 in-data: 18 20 20 08 00 00 00 00
387 12:43:15.337148 Phase 1
388 12:43:15.340988 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 12:43:15.347840 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 12:43:15.351819 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 12:43:15.355576 Recovery requested (1009000e)
392 12:43:15.364998 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 12:43:15.369969 tlcl_extend: response is 0
394 12:43:15.379813 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 12:43:15.385205 tlcl_extend: response is 0
396 12:43:15.392013 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 12:43:15.412146 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 12:43:15.418700 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 12:43:15.418791
400 12:43:15.418857
401 12:43:15.429212 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 12:43:15.432477 ARM64: Exception handlers installed.
403 12:43:15.435696 ARM64: Testing exception
404 12:43:15.435779 ARM64: Done test exception
405 12:43:15.457555 pmic_efuse_setting: Set efuses in 11 msecs
406 12:43:15.461257 pmwrap_interface_init: Select PMIF_VLD_RDY
407 12:43:15.467419 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 12:43:15.471204 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 12:43:15.478316 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 12:43:15.482107 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 12:43:15.486225 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 12:43:15.489463 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 12:43:15.497276 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 12:43:15.500474 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 12:43:15.504423 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 12:43:15.511584 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 12:43:15.516270 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 12:43:15.519657 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 12:43:15.523211 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 12:43:15.531145 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 12:43:15.534387 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 12:43:15.541667 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 12:43:15.548824 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 12:43:15.552789 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 12:43:15.560583 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 12:43:15.563488 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 12:43:15.571033 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 12:43:15.574746 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 12:43:15.582394 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 12:43:15.586372 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 12:43:15.590222 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 12:43:15.597600 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 12:43:15.601300 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 12:43:15.608320 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 12:43:15.612382 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 12:43:15.616090 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 12:43:15.622769 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 12:43:15.626782 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 12:43:15.630080 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 12:43:15.637491 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 12:43:15.640750 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 12:43:15.648707 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 12:43:15.652744 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 12:43:15.656145 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 12:43:15.660003 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 12:43:15.663815 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 12:43:15.671579 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 12:43:15.674726 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 12:43:15.678220 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 12:43:15.681964 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 12:43:15.685613 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 12:43:15.693320 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 12:43:15.697233 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 12:43:15.700735 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 12:43:15.704676 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 12:43:15.708542 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 12:43:15.711778 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 12:43:15.719447 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 12:43:15.730579 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 12:43:15.734669 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 12:43:15.742010 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 12:43:15.749243 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 12:43:15.756573 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 12:43:15.760093 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 12:43:15.763332 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 12:43:15.771387 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 12:43:15.774565 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 12:43:15.782788 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 12:43:15.785904 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 12:43:15.795686 [RTC]rtc_get_frequency_meter,154: input=15, output=758
471 12:43:15.804569 [RTC]rtc_get_frequency_meter,154: input=23, output=941
472 12:43:15.814318 [RTC]rtc_get_frequency_meter,154: input=19, output=850
473 12:43:15.823857 [RTC]rtc_get_frequency_meter,154: input=17, output=804
474 12:43:15.833695 [RTC]rtc_get_frequency_meter,154: input=16, output=782
475 12:43:15.842975 [RTC]rtc_get_frequency_meter,154: input=16, output=783
476 12:43:15.852369 [RTC]rtc_get_frequency_meter,154: input=17, output=804
477 12:43:15.856378 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 12:43:15.863780 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 12:43:15.867042 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 12:43:15.870368 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 12:43:15.874919 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 12:43:15.878221 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 12:43:15.882331 ADC[4]: Raw value=905834 ID=7
484 12:43:15.885862 ADC[3]: Raw value=213810 ID=1
485 12:43:15.885949 RAM Code: 0x71
486 12:43:15.889749 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 12:43:15.893634 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 12:43:15.904607 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 12:43:15.911562 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 12:43:15.911731 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 12:43:15.917005 in-header: 03 07 00 00 08 00 00 00
492 12:43:15.920960 in-data: aa e4 47 04 13 02 00 00
493 12:43:15.924809 Chrome EC: UHEPI supported
494 12:43:15.928615 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 12:43:15.933576 in-header: 03 95 00 00 08 00 00 00
496 12:43:15.936959 in-data: 18 20 20 08 00 00 00 00
497 12:43:15.940916 MRC: failed to locate region type 0.
498 12:43:15.948097 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 12:43:15.948176 DRAM-K: Running full calibration
500 12:43:15.956080 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 12:43:15.959982 header.status = 0x0
502 12:43:15.960062 header.version = 0x6 (expected: 0x6)
503 12:43:15.963315 header.size = 0xd00 (expected: 0xd00)
504 12:43:15.967225 header.flags = 0x0
505 12:43:15.970725 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 12:43:15.990490 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
507 12:43:15.997909 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 12:43:16.001667 dram_init: ddr_geometry: 2
509 12:43:16.001814 [EMI] MDL number = 2
510 12:43:16.005644 [EMI] Get MDL freq = 0
511 12:43:16.005721 dram_init: ddr_type: 0
512 12:43:16.009535 is_discrete_lpddr4: 1
513 12:43:16.013240 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 12:43:16.013318
515 12:43:16.013381
516 12:43:16.013444 [Bian_co] ETT version 0.0.0.1
517 12:43:16.020577 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 12:43:16.020654
519 12:43:16.024520 dramc_set_vcore_voltage set vcore to 650000
520 12:43:16.024594 Read voltage for 800, 4
521 12:43:16.024656 Vio18 = 0
522 12:43:16.027867 Vcore = 650000
523 12:43:16.027942 Vdram = 0
524 12:43:16.028008 Vddq = 0
525 12:43:16.031775 Vmddr = 0
526 12:43:16.031875 dram_init: config_dvfs: 1
527 12:43:16.035559 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 12:43:16.043359 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 12:43:16.047402 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 12:43:16.051448 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 12:43:16.054719 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 12:43:16.057938 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 12:43:16.061134 MEM_TYPE=3, freq_sel=18
534 12:43:16.064569 sv_algorithm_assistance_LP4_1600
535 12:43:16.068385 ============ PULL DRAM RESETB DOWN ============
536 12:43:16.071722 ========== PULL DRAM RESETB DOWN end =========
537 12:43:16.075674 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 12:43:16.079163 ===================================
539 12:43:16.082932 LPDDR4 DRAM CONFIGURATION
540 12:43:16.086145 ===================================
541 12:43:16.086231 EX_ROW_EN[0] = 0x0
542 12:43:16.090487 EX_ROW_EN[1] = 0x0
543 12:43:16.090570 LP4Y_EN = 0x0
544 12:43:16.093692 WORK_FSP = 0x0
545 12:43:16.093814 WL = 0x2
546 12:43:16.097520 RL = 0x2
547 12:43:16.097604 BL = 0x2
548 12:43:16.100707 RPST = 0x0
549 12:43:16.100791 RD_PRE = 0x0
550 12:43:16.104047 WR_PRE = 0x1
551 12:43:16.104130 WR_PST = 0x0
552 12:43:16.106997 DBI_WR = 0x0
553 12:43:16.107080 DBI_RD = 0x0
554 12:43:16.110549 OTF = 0x1
555 12:43:16.113843 ===================================
556 12:43:16.117762 ===================================
557 12:43:16.117846 ANA top config
558 12:43:16.121495 ===================================
559 12:43:16.125383 DLL_ASYNC_EN = 0
560 12:43:16.125498 ALL_SLAVE_EN = 1
561 12:43:16.128805 NEW_RANK_MODE = 1
562 12:43:16.132048 DLL_IDLE_MODE = 1
563 12:43:16.135291 LP45_APHY_COMB_EN = 1
564 12:43:16.135375 TX_ODT_DIS = 1
565 12:43:16.138496 NEW_8X_MODE = 1
566 12:43:16.142435 ===================================
567 12:43:16.146335 ===================================
568 12:43:16.149483 data_rate = 1600
569 12:43:16.152875 CKR = 1
570 12:43:16.152960 DQ_P2S_RATIO = 8
571 12:43:16.156224 ===================================
572 12:43:16.159470 CA_P2S_RATIO = 8
573 12:43:16.162706 DQ_CA_OPEN = 0
574 12:43:16.165979 DQ_SEMI_OPEN = 0
575 12:43:16.169424 CA_SEMI_OPEN = 0
576 12:43:16.172675 CA_FULL_RATE = 0
577 12:43:16.172778 DQ_CKDIV4_EN = 1
578 12:43:16.175914 CA_CKDIV4_EN = 1
579 12:43:16.179830 CA_PREDIV_EN = 0
580 12:43:16.183320 PH8_DLY = 0
581 12:43:16.186067 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 12:43:16.186143 DQ_AAMCK_DIV = 4
583 12:43:16.189697 CA_AAMCK_DIV = 4
584 12:43:16.192680 CA_ADMCK_DIV = 4
585 12:43:16.196093 DQ_TRACK_CA_EN = 0
586 12:43:16.199376 CA_PICK = 800
587 12:43:16.203205 CA_MCKIO = 800
588 12:43:16.203280 MCKIO_SEMI = 0
589 12:43:16.206803 PLL_FREQ = 3068
590 12:43:16.210681 DQ_UI_PI_RATIO = 32
591 12:43:16.213796 CA_UI_PI_RATIO = 0
592 12:43:16.217680 ===================================
593 12:43:16.221758 ===================================
594 12:43:16.221839 memory_type:LPDDR4
595 12:43:16.225310 GP_NUM : 10
596 12:43:16.225427 SRAM_EN : 1
597 12:43:16.229420 MD32_EN : 0
598 12:43:16.232493 ===================================
599 12:43:16.232615 [ANA_INIT] >>>>>>>>>>>>>>
600 12:43:16.235974 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 12:43:16.240056 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 12:43:16.243124 ===================================
603 12:43:16.246303 data_rate = 1600,PCW = 0X7600
604 12:43:16.249562 ===================================
605 12:43:16.252842 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 12:43:16.259976 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 12:43:16.263306 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 12:43:16.269896 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 12:43:16.273119 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 12:43:16.276462 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 12:43:16.276536 [ANA_INIT] flow start
612 12:43:16.279773 [ANA_INIT] PLL >>>>>>>>
613 12:43:16.282976 [ANA_INIT] PLL <<<<<<<<
614 12:43:16.283047 [ANA_INIT] MIDPI >>>>>>>>
615 12:43:16.286442 [ANA_INIT] MIDPI <<<<<<<<
616 12:43:16.289766 [ANA_INIT] DLL >>>>>>>>
617 12:43:16.289860 [ANA_INIT] flow end
618 12:43:16.296450 ============ LP4 DIFF to SE enter ============
619 12:43:16.299835 ============ LP4 DIFF to SE exit ============
620 12:43:16.303263 [ANA_INIT] <<<<<<<<<<<<<
621 12:43:16.303341 [Flow] Enable top DCM control >>>>>
622 12:43:16.306383 [Flow] Enable top DCM control <<<<<
623 12:43:16.310183 Enable DLL master slave shuffle
624 12:43:16.316347 ==============================================================
625 12:43:16.320067 Gating Mode config
626 12:43:16.323181 ==============================================================
627 12:43:16.326460 Config description:
628 12:43:16.336734 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 12:43:16.343560 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 12:43:16.346708 SELPH_MODE 0: By rank 1: By Phase
631 12:43:16.353087 ==============================================================
632 12:43:16.356285 GAT_TRACK_EN = 1
633 12:43:16.359990 RX_GATING_MODE = 2
634 12:43:16.360066 RX_GATING_TRACK_MODE = 2
635 12:43:16.363339 SELPH_MODE = 1
636 12:43:16.366707 PICG_EARLY_EN = 1
637 12:43:16.370104 VALID_LAT_VALUE = 1
638 12:43:16.376490 ==============================================================
639 12:43:16.379831 Enter into Gating configuration >>>>
640 12:43:16.383108 Exit from Gating configuration <<<<
641 12:43:16.386521 Enter into DVFS_PRE_config >>>>>
642 12:43:16.396474 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 12:43:16.399673 Exit from DVFS_PRE_config <<<<<
644 12:43:16.403653 Enter into PICG configuration >>>>
645 12:43:16.406981 Exit from PICG configuration <<<<
646 12:43:16.409901 [RX_INPUT] configuration >>>>>
647 12:43:16.412936 [RX_INPUT] configuration <<<<<
648 12:43:16.416717 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 12:43:16.423094 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 12:43:16.429725 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 12:43:16.433596 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 12:43:16.439833 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 12:43:16.446822 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 12:43:16.450171 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 12:43:16.453262 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 12:43:16.459794 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 12:43:16.463496 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 12:43:16.466696 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 12:43:16.473259 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 12:43:16.477133 ===================================
661 12:43:16.477217 LPDDR4 DRAM CONFIGURATION
662 12:43:16.479722 ===================================
663 12:43:16.483259 EX_ROW_EN[0] = 0x0
664 12:43:16.483341 EX_ROW_EN[1] = 0x0
665 12:43:16.486537 LP4Y_EN = 0x0
666 12:43:16.486621 WORK_FSP = 0x0
667 12:43:16.489777 WL = 0x2
668 12:43:16.493186 RL = 0x2
669 12:43:16.493271 BL = 0x2
670 12:43:16.496655 RPST = 0x0
671 12:43:16.496738 RD_PRE = 0x0
672 12:43:16.500528 WR_PRE = 0x1
673 12:43:16.500610 WR_PST = 0x0
674 12:43:16.503217 DBI_WR = 0x0
675 12:43:16.503309 DBI_RD = 0x0
676 12:43:16.507108 OTF = 0x1
677 12:43:16.510459 ===================================
678 12:43:16.513704 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 12:43:16.516836 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 12:43:16.519989 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 12:43:16.523598 ===================================
682 12:43:16.526659 LPDDR4 DRAM CONFIGURATION
683 12:43:16.530313 ===================================
684 12:43:16.533218 EX_ROW_EN[0] = 0x10
685 12:43:16.533317 EX_ROW_EN[1] = 0x0
686 12:43:16.536959 LP4Y_EN = 0x0
687 12:43:16.537072 WORK_FSP = 0x0
688 12:43:16.540055 WL = 0x2
689 12:43:16.540138 RL = 0x2
690 12:43:16.543388 BL = 0x2
691 12:43:16.543471 RPST = 0x0
692 12:43:16.547043 RD_PRE = 0x0
693 12:43:16.547126 WR_PRE = 0x1
694 12:43:16.549927 WR_PST = 0x0
695 12:43:16.550010 DBI_WR = 0x0
696 12:43:16.553705 DBI_RD = 0x0
697 12:43:16.553787 OTF = 0x1
698 12:43:16.557039 ===================================
699 12:43:16.563529 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 12:43:16.568236 nWR fixed to 40
701 12:43:16.571866 [ModeRegInit_LP4] CH0 RK0
702 12:43:16.571952 [ModeRegInit_LP4] CH0 RK1
703 12:43:16.574860 [ModeRegInit_LP4] CH1 RK0
704 12:43:16.578537 [ModeRegInit_LP4] CH1 RK1
705 12:43:16.578616 match AC timing 13
706 12:43:16.585020 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 12:43:16.588502 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 12:43:16.591602 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 12:43:16.598390 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 12:43:16.601502 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 12:43:16.601586 [EMI DOE] emi_dcm 0
712 12:43:16.608270 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 12:43:16.608354 ==
714 12:43:16.611682 Dram Type= 6, Freq= 0, CH_0, rank 0
715 12:43:16.615626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 12:43:16.615711 ==
717 12:43:16.622252 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 12:43:16.625328 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 12:43:16.635847 [CA 0] Center 36 (6~67) winsize 62
720 12:43:16.638878 [CA 1] Center 36 (6~67) winsize 62
721 12:43:16.642669 [CA 2] Center 34 (4~65) winsize 62
722 12:43:16.645888 [CA 3] Center 33 (3~64) winsize 62
723 12:43:16.649473 [CA 4] Center 32 (2~63) winsize 62
724 12:43:16.652395 [CA 5] Center 32 (3~62) winsize 60
725 12:43:16.652477
726 12:43:16.655999 [CmdBusTrainingLP45] Vref(ca) range 1: 32
727 12:43:16.656078
728 12:43:16.659027 [CATrainingPosCal] consider 1 rank data
729 12:43:16.662170 u2DelayCellTimex100 = 270/100 ps
730 12:43:16.666047 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 12:43:16.669419 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 12:43:16.675953 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 12:43:16.679142 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
734 12:43:16.682233 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
735 12:43:16.685945 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
736 12:43:16.686048
737 12:43:16.688944 CA PerBit enable=1, Macro0, CA PI delay=32
738 12:43:16.689025
739 12:43:16.692425 [CBTSetCACLKResult] CA Dly = 32
740 12:43:16.692529 CS Dly: 4 (0~35)
741 12:43:16.692630 ==
742 12:43:16.695541 Dram Type= 6, Freq= 0, CH_0, rank 1
743 12:43:16.702124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 12:43:16.702238 ==
745 12:43:16.706342 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 12:43:16.712122 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 12:43:16.722299 [CA 0] Center 36 (6~67) winsize 62
748 12:43:16.725447 [CA 1] Center 36 (6~67) winsize 62
749 12:43:16.728486 [CA 2] Center 34 (4~65) winsize 62
750 12:43:16.731897 [CA 3] Center 33 (3~64) winsize 62
751 12:43:16.734976 [CA 4] Center 32 (2~63) winsize 62
752 12:43:16.738688 [CA 5] Center 32 (2~63) winsize 62
753 12:43:16.738808
754 12:43:16.741597 [CmdBusTrainingLP45] Vref(ca) range 1: 32
755 12:43:16.741699
756 12:43:16.745176 [CATrainingPosCal] consider 2 rank data
757 12:43:16.748435 u2DelayCellTimex100 = 270/100 ps
758 12:43:16.751968 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 12:43:16.758362 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 12:43:16.762255 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 12:43:16.765273 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
762 12:43:16.768152 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
763 12:43:16.771856 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
764 12:43:16.771965
765 12:43:16.775215 CA PerBit enable=1, Macro0, CA PI delay=32
766 12:43:16.775317
767 12:43:16.778379 [CBTSetCACLKResult] CA Dly = 32
768 12:43:16.778454 CS Dly: 5 (0~37)
769 12:43:16.778517
770 12:43:16.785434 ----->DramcWriteLeveling(PI) begin...
771 12:43:16.785545 ==
772 12:43:16.788898 Dram Type= 6, Freq= 0, CH_0, rank 0
773 12:43:16.792710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 12:43:16.792839 ==
775 12:43:16.796484 Write leveling (Byte 0): 32 => 32
776 12:43:16.796569 Write leveling (Byte 1): 30 => 30
777 12:43:16.799730 DramcWriteLeveling(PI) end<-----
778 12:43:16.799814
779 12:43:16.799880 ==
780 12:43:16.803760 Dram Type= 6, Freq= 0, CH_0, rank 0
781 12:43:16.807052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 12:43:16.809874 ==
783 12:43:16.809985 [Gating] SW mode calibration
784 12:43:16.817365 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 12:43:16.824503 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 12:43:16.827355 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 12:43:16.830497 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 12:43:16.837739 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 12:43:16.841191 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 12:43:16.844283 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 12:43:16.851088 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 12:43:16.854137 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 12:43:16.857849 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 12:43:16.864078 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 12:43:16.867590 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:43:16.871080 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:43:16.877635 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 12:43:16.880925 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 12:43:16.884066 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:43:16.888146 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 12:43:16.894844 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 12:43:16.898115 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:43:16.901184 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 12:43:16.908110 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 12:43:16.911373 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 12:43:16.914618 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 12:43:16.921276 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:43:16.924582 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 12:43:16.928077 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 12:43:16.934516 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 12:43:16.937909 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 12:43:16.941327 0 9 8 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
813 12:43:16.947983 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 12:43:16.951198 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 12:43:16.955059 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 12:43:16.958226 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 12:43:16.964575 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 12:43:16.968328 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 12:43:16.971423 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
820 12:43:16.978203 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 1) (1 0)
821 12:43:16.981435 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
822 12:43:16.984698 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 12:43:16.991345 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 12:43:16.994538 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 12:43:16.997915 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 12:43:17.004767 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 12:43:17.008048 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 12:43:17.011675 0 11 8 | B1->B0 | 2e2e 4444 | 0 0 | (0 0) (0 0)
829 12:43:17.018174 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
830 12:43:17.021541 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 12:43:17.024693 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 12:43:17.031297 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 12:43:17.034625 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 12:43:17.038000 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 12:43:17.041302 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 12:43:17.048646 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
837 12:43:17.051485 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 12:43:17.055545 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 12:43:17.061663 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 12:43:17.065514 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 12:43:17.068515 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 12:43:17.075338 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 12:43:17.078495 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:43:17.081710 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:43:17.088366 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 12:43:17.091674 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 12:43:17.095553 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 12:43:17.101865 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 12:43:17.105172 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 12:43:17.108569 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 12:43:17.115125 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 12:43:17.118208 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 12:43:17.121809 Total UI for P1: 0, mck2ui 16
854 12:43:17.125167 best dqsien dly found for B0: ( 0, 14, 6)
855 12:43:17.128971 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
856 12:43:17.131759 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
857 12:43:17.135230 Total UI for P1: 0, mck2ui 16
858 12:43:17.139366 best dqsien dly found for B1: ( 0, 14, 10)
859 12:43:17.143125 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
860 12:43:17.146482 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
861 12:43:17.146916
862 12:43:17.149709 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
863 12:43:17.156397 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
864 12:43:17.156873 [Gating] SW calibration Done
865 12:43:17.157224 ==
866 12:43:17.159636 Dram Type= 6, Freq= 0, CH_0, rank 0
867 12:43:17.166181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 12:43:17.166618 ==
869 12:43:17.166965 RX Vref Scan: 0
870 12:43:17.167284
871 12:43:17.169355 RX Vref 0 -> 0, step: 1
872 12:43:17.169825
873 12:43:17.173113 RX Delay -130 -> 252, step: 16
874 12:43:17.176553 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
875 12:43:17.179850 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
876 12:43:17.182875 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
877 12:43:17.186174 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
878 12:43:17.193001 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
879 12:43:17.196265 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
880 12:43:17.199896 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
881 12:43:17.203144 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
882 12:43:17.206300 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
883 12:43:17.212995 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
884 12:43:17.216073 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
885 12:43:17.220230 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
886 12:43:17.223348 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
887 12:43:17.226601 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
888 12:43:17.232767 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
889 12:43:17.236120 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
890 12:43:17.236554 ==
891 12:43:17.240185 Dram Type= 6, Freq= 0, CH_0, rank 0
892 12:43:17.243449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 12:43:17.243890 ==
894 12:43:17.246785 DQS Delay:
895 12:43:17.247216 DQS0 = 0, DQS1 = 0
896 12:43:17.247576 DQM Delay:
897 12:43:17.250162 DQM0 = 88, DQM1 = 82
898 12:43:17.250616 DQ Delay:
899 12:43:17.253211 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
900 12:43:17.256718 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
901 12:43:17.259907 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
902 12:43:17.263391 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
903 12:43:17.263835
904 12:43:17.264178
905 12:43:17.264695 ==
906 12:43:17.267150 Dram Type= 6, Freq= 0, CH_0, rank 0
907 12:43:17.270429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 12:43:17.273593 ==
909 12:43:17.274022
910 12:43:17.274380
911 12:43:17.274745 TX Vref Scan disable
912 12:43:17.276648 == TX Byte 0 ==
913 12:43:17.279851 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
914 12:43:17.283794 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
915 12:43:17.286745 == TX Byte 1 ==
916 12:43:17.290311 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
917 12:43:17.293267 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
918 12:43:17.297045 ==
919 12:43:17.297482 Dram Type= 6, Freq= 0, CH_0, rank 0
920 12:43:17.303206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 12:43:17.303643 ==
922 12:43:17.315858 TX Vref=22, minBit 4, minWin=27, winSum=444
923 12:43:17.319134 TX Vref=24, minBit 7, minWin=27, winSum=451
924 12:43:17.322365 TX Vref=26, minBit 0, minWin=28, winSum=455
925 12:43:17.325755 TX Vref=28, minBit 0, minWin=28, winSum=457
926 12:43:17.329112 TX Vref=30, minBit 8, minWin=28, winSum=457
927 12:43:17.332253 TX Vref=32, minBit 0, minWin=28, winSum=455
928 12:43:17.339513 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 28
929 12:43:17.339942
930 12:43:17.341970 Final TX Range 1 Vref 28
931 12:43:17.342399
932 12:43:17.342735 ==
933 12:43:17.345383 Dram Type= 6, Freq= 0, CH_0, rank 0
934 12:43:17.349101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 12:43:17.349590 ==
936 12:43:17.352067
937 12:43:17.352576
938 12:43:17.353015 TX Vref Scan disable
939 12:43:17.355952 == TX Byte 0 ==
940 12:43:17.359314 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
941 12:43:17.362598 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
942 12:43:17.365824 == TX Byte 1 ==
943 12:43:17.369237 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
944 12:43:17.372171 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
945 12:43:17.375551
946 12:43:17.375980 [DATLAT]
947 12:43:17.376323 Freq=800, CH0 RK0
948 12:43:17.376674
949 12:43:17.378819 DATLAT Default: 0xa
950 12:43:17.379250 0, 0xFFFF, sum = 0
951 12:43:17.382661 1, 0xFFFF, sum = 0
952 12:43:17.383098 2, 0xFFFF, sum = 0
953 12:43:17.385695 3, 0xFFFF, sum = 0
954 12:43:17.386140 4, 0xFFFF, sum = 0
955 12:43:17.388974 5, 0xFFFF, sum = 0
956 12:43:17.389416 6, 0xFFFF, sum = 0
957 12:43:17.392759 7, 0xFFFF, sum = 0
958 12:43:17.395885 8, 0xFFFF, sum = 0
959 12:43:17.396324 9, 0x0, sum = 1
960 12:43:17.396678 10, 0x0, sum = 2
961 12:43:17.399026 11, 0x0, sum = 3
962 12:43:17.399463 12, 0x0, sum = 4
963 12:43:17.402220 best_step = 10
964 12:43:17.402666
965 12:43:17.403009 ==
966 12:43:17.405869 Dram Type= 6, Freq= 0, CH_0, rank 0
967 12:43:17.409050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 12:43:17.409499 ==
969 12:43:17.412696 RX Vref Scan: 1
970 12:43:17.413241
971 12:43:17.413593 Set Vref Range= 32 -> 127
972 12:43:17.413981
973 12:43:17.415733 RX Vref 32 -> 127, step: 1
974 12:43:17.416164
975 12:43:17.419091 RX Delay -79 -> 252, step: 8
976 12:43:17.419523
977 12:43:17.422163 Set Vref, RX VrefLevel [Byte0]: 32
978 12:43:17.426047 [Byte1]: 32
979 12:43:17.426528
980 12:43:17.429010 Set Vref, RX VrefLevel [Byte0]: 33
981 12:43:17.432357 [Byte1]: 33
982 12:43:17.435687
983 12:43:17.436201 Set Vref, RX VrefLevel [Byte0]: 34
984 12:43:17.439059 [Byte1]: 34
985 12:43:17.443461
986 12:43:17.443993 Set Vref, RX VrefLevel [Byte0]: 35
987 12:43:17.446862 [Byte1]: 35
988 12:43:17.451361
989 12:43:17.451800 Set Vref, RX VrefLevel [Byte0]: 36
990 12:43:17.454662 [Byte1]: 36
991 12:43:17.458739
992 12:43:17.459182 Set Vref, RX VrefLevel [Byte0]: 37
993 12:43:17.462194 [Byte1]: 37
994 12:43:17.466788
995 12:43:17.467207 Set Vref, RX VrefLevel [Byte0]: 38
996 12:43:17.470239 [Byte1]: 38
997 12:43:17.474189
998 12:43:17.474670 Set Vref, RX VrefLevel [Byte0]: 39
999 12:43:17.477645 [Byte1]: 39
1000 12:43:17.481729
1001 12:43:17.482152 Set Vref, RX VrefLevel [Byte0]: 40
1002 12:43:17.484904 [Byte1]: 40
1003 12:43:17.488562
1004 12:43:17.489026 Set Vref, RX VrefLevel [Byte0]: 41
1005 12:43:17.492074 [Byte1]: 41
1006 12:43:17.496511
1007 12:43:17.496980 Set Vref, RX VrefLevel [Byte0]: 42
1008 12:43:17.499649 [Byte1]: 42
1009 12:43:17.503950
1010 12:43:17.504434 Set Vref, RX VrefLevel [Byte0]: 43
1011 12:43:17.507077 [Byte1]: 43
1012 12:43:17.511346
1013 12:43:17.511820 Set Vref, RX VrefLevel [Byte0]: 44
1014 12:43:17.514627 [Byte1]: 44
1015 12:43:17.519137
1016 12:43:17.519607 Set Vref, RX VrefLevel [Byte0]: 45
1017 12:43:17.521866 [Byte1]: 45
1018 12:43:17.526467
1019 12:43:17.526889 Set Vref, RX VrefLevel [Byte0]: 46
1020 12:43:17.529524 [Byte1]: 46
1021 12:43:17.533999
1022 12:43:17.534428 Set Vref, RX VrefLevel [Byte0]: 47
1023 12:43:17.537136 [Byte1]: 47
1024 12:43:17.541892
1025 12:43:17.542375 Set Vref, RX VrefLevel [Byte0]: 48
1026 12:43:17.545005 [Byte1]: 48
1027 12:43:17.548845
1028 12:43:17.549417 Set Vref, RX VrefLevel [Byte0]: 49
1029 12:43:17.552597 [Byte1]: 49
1030 12:43:17.556584
1031 12:43:17.557044 Set Vref, RX VrefLevel [Byte0]: 50
1032 12:43:17.559821 [Byte1]: 50
1033 12:43:17.564575
1034 12:43:17.565038 Set Vref, RX VrefLevel [Byte0]: 51
1035 12:43:17.567747 [Byte1]: 51
1036 12:43:17.571991
1037 12:43:17.572410 Set Vref, RX VrefLevel [Byte0]: 52
1038 12:43:17.575216 [Byte1]: 52
1039 12:43:17.579537
1040 12:43:17.579957 Set Vref, RX VrefLevel [Byte0]: 53
1041 12:43:17.582831 [Byte1]: 53
1042 12:43:17.586812
1043 12:43:17.587249 Set Vref, RX VrefLevel [Byte0]: 54
1044 12:43:17.589980 [Byte1]: 54
1045 12:43:17.594432
1046 12:43:17.594852 Set Vref, RX VrefLevel [Byte0]: 55
1047 12:43:17.597736 [Byte1]: 55
1048 12:43:17.601717
1049 12:43:17.602133 Set Vref, RX VrefLevel [Byte0]: 56
1050 12:43:17.605216 [Byte1]: 56
1051 12:43:17.609480
1052 12:43:17.609896 Set Vref, RX VrefLevel [Byte0]: 57
1053 12:43:17.612653 [Byte1]: 57
1054 12:43:17.616847
1055 12:43:17.617310 Set Vref, RX VrefLevel [Byte0]: 58
1056 12:43:17.620648 [Byte1]: 58
1057 12:43:17.624772
1058 12:43:17.625318 Set Vref, RX VrefLevel [Byte0]: 59
1059 12:43:17.628044 [Byte1]: 59
1060 12:43:17.632267
1061 12:43:17.632690 Set Vref, RX VrefLevel [Byte0]: 60
1062 12:43:17.635124 [Byte1]: 60
1063 12:43:17.639546
1064 12:43:17.639950 Set Vref, RX VrefLevel [Byte0]: 61
1065 12:43:17.642905 [Byte1]: 61
1066 12:43:17.647255
1067 12:43:17.647655 Set Vref, RX VrefLevel [Byte0]: 62
1068 12:43:17.650367 [Byte1]: 62
1069 12:43:17.654934
1070 12:43:17.655370 Set Vref, RX VrefLevel [Byte0]: 63
1071 12:43:17.658222 [Byte1]: 63
1072 12:43:17.662095
1073 12:43:17.662569 Set Vref, RX VrefLevel [Byte0]: 64
1074 12:43:17.665386 [Byte1]: 64
1075 12:43:17.670410
1076 12:43:17.670957 Set Vref, RX VrefLevel [Byte0]: 65
1077 12:43:17.673472 [Byte1]: 65
1078 12:43:17.677357
1079 12:43:17.677778 Set Vref, RX VrefLevel [Byte0]: 66
1080 12:43:17.680680 [Byte1]: 66
1081 12:43:17.685269
1082 12:43:17.685771 Set Vref, RX VrefLevel [Byte0]: 67
1083 12:43:17.688372 [Byte1]: 67
1084 12:43:17.692405
1085 12:43:17.692915 Set Vref, RX VrefLevel [Byte0]: 68
1086 12:43:17.696066 [Byte1]: 68
1087 12:43:17.700297
1088 12:43:17.700762 Set Vref, RX VrefLevel [Byte0]: 69
1089 12:43:17.703604 [Byte1]: 69
1090 12:43:17.707663
1091 12:43:17.708179 Set Vref, RX VrefLevel [Byte0]: 70
1092 12:43:17.711183 [Byte1]: 70
1093 12:43:17.715044
1094 12:43:17.715542 Set Vref, RX VrefLevel [Byte0]: 71
1095 12:43:17.718872 [Byte1]: 71
1096 12:43:17.722478
1097 12:43:17.723120 Set Vref, RX VrefLevel [Byte0]: 72
1098 12:43:17.726233 [Byte1]: 72
1099 12:43:17.729973
1100 12:43:17.730669 Set Vref, RX VrefLevel [Byte0]: 73
1101 12:43:17.733707 [Byte1]: 73
1102 12:43:17.737540
1103 12:43:17.738041 Set Vref, RX VrefLevel [Byte0]: 74
1104 12:43:17.741210 [Byte1]: 74
1105 12:43:17.745313
1106 12:43:17.745801 Set Vref, RX VrefLevel [Byte0]: 75
1107 12:43:17.748456 [Byte1]: 75
1108 12:43:17.752981
1109 12:43:17.753425 Set Vref, RX VrefLevel [Byte0]: 76
1110 12:43:17.756139 [Byte1]: 76
1111 12:43:17.760464
1112 12:43:17.761096 Set Vref, RX VrefLevel [Byte0]: 77
1113 12:43:17.763757 [Byte1]: 77
1114 12:43:17.768010
1115 12:43:17.768428 Set Vref, RX VrefLevel [Byte0]: 78
1116 12:43:17.771334 [Byte1]: 78
1117 12:43:17.775846
1118 12:43:17.776412 Final RX Vref Byte 0 = 58 to rank0
1119 12:43:17.779254 Final RX Vref Byte 1 = 60 to rank0
1120 12:43:17.782450 Final RX Vref Byte 0 = 58 to rank1
1121 12:43:17.785889 Final RX Vref Byte 1 = 60 to rank1==
1122 12:43:17.788857 Dram Type= 6, Freq= 0, CH_0, rank 0
1123 12:43:17.792200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1124 12:43:17.795682 ==
1125 12:43:17.796105 DQS Delay:
1126 12:43:17.796441 DQS0 = 0, DQS1 = 0
1127 12:43:17.799594 DQM Delay:
1128 12:43:17.800017 DQM0 = 92, DQM1 = 86
1129 12:43:17.802681 DQ Delay:
1130 12:43:17.803235 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1131 12:43:17.805923 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1132 12:43:17.809309 DQ8 =76, DQ9 =76, DQ10 =88, DQ11 =76
1133 12:43:17.812524 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1134 12:43:17.813085
1135 12:43:17.815813
1136 12:43:17.822575 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e45, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
1137 12:43:17.825784 CH0 RK0: MR19=606, MR18=4E45
1138 12:43:17.832614 CH0_RK0: MR19=0x606, MR18=0x4E45, DQSOSC=390, MR23=63, INC=97, DEC=64
1139 12:43:17.833124
1140 12:43:17.835767 ----->DramcWriteLeveling(PI) begin...
1141 12:43:17.836155 ==
1142 12:43:17.839374 Dram Type= 6, Freq= 0, CH_0, rank 1
1143 12:43:17.842697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1144 12:43:17.843147 ==
1145 12:43:17.846044 Write leveling (Byte 0): 31 => 31
1146 12:43:17.849525 Write leveling (Byte 1): 30 => 30
1147 12:43:17.852480 DramcWriteLeveling(PI) end<-----
1148 12:43:17.852940
1149 12:43:17.853279 ==
1150 12:43:17.855932 Dram Type= 6, Freq= 0, CH_0, rank 1
1151 12:43:17.859079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1152 12:43:17.859567 ==
1153 12:43:17.903170 [Gating] SW mode calibration
1154 12:43:17.903722 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1155 12:43:17.904368 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1156 12:43:17.904754 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1157 12:43:17.905155 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1158 12:43:17.905492 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 12:43:17.905847 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 12:43:17.906182 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 12:43:17.906474 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 12:43:17.947227 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 12:43:17.947687 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 12:43:17.948077 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 12:43:17.948720 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 12:43:17.949117 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 12:43:17.949433 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 12:43:17.949733 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 12:43:17.950057 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 12:43:17.950349 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 12:43:17.950637 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 12:43:17.972955 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 12:43:17.973523 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1174 12:43:17.973889 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1175 12:43:17.974544 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 12:43:17.974901 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 12:43:17.976663 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 12:43:17.977296 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 12:43:17.980012 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 12:43:17.983899 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 12:43:17.990073 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 12:43:17.993411 0 9 8 | B1->B0 | 3030 2d2d | 1 1 | (0 0) (0 0)
1183 12:43:17.997102 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 12:43:18.003656 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 12:43:18.006912 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 12:43:18.010260 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 12:43:18.013988 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 12:43:18.020651 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 12:43:18.023907 0 10 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1190 12:43:18.027277 0 10 8 | B1->B0 | 2424 2323 | 1 0 | (1 1) (0 0)
1191 12:43:18.034635 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 12:43:18.038905 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 12:43:18.041958 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 12:43:18.045696 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 12:43:18.048934 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 12:43:18.055599 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 12:43:18.059835 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 12:43:18.063148 0 11 8 | B1->B0 | 3c3c 4141 | 0 0 | (0 0) (0 0)
1199 12:43:18.066325 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 12:43:18.073314 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 12:43:18.076196 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 12:43:18.080021 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 12:43:18.086406 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 12:43:18.089556 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 12:43:18.093177 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 12:43:18.099774 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1207 12:43:18.103366 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 12:43:18.106562 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 12:43:18.113221 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 12:43:18.116436 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 12:43:18.119786 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 12:43:18.126941 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 12:43:18.130257 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 12:43:18.133651 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 12:43:18.136894 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 12:43:18.143452 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 12:43:18.146770 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 12:43:18.150042 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 12:43:18.156759 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 12:43:18.159873 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 12:43:18.163505 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 12:43:18.170034 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1223 12:43:18.173196 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1224 12:43:18.176921 Total UI for P1: 0, mck2ui 16
1225 12:43:18.179826 best dqsien dly found for B0: ( 0, 14, 8)
1226 12:43:18.183524 Total UI for P1: 0, mck2ui 16
1227 12:43:18.187142 best dqsien dly found for B1: ( 0, 14, 10)
1228 12:43:18.190304 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1229 12:43:18.193488 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1230 12:43:18.193907
1231 12:43:18.196580 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1232 12:43:18.199823 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1233 12:43:18.203566 [Gating] SW calibration Done
1234 12:43:18.203980 ==
1235 12:43:18.206647 Dram Type= 6, Freq= 0, CH_0, rank 1
1236 12:43:18.210217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1237 12:43:18.213548 ==
1238 12:43:18.214026 RX Vref Scan: 0
1239 12:43:18.214371
1240 12:43:18.217100 RX Vref 0 -> 0, step: 1
1241 12:43:18.217536
1242 12:43:18.220209 RX Delay -130 -> 252, step: 16
1243 12:43:18.223408 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1244 12:43:18.226748 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1245 12:43:18.230179 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1246 12:43:18.233701 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1247 12:43:18.236887 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1248 12:43:18.243469 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1249 12:43:18.246806 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1250 12:43:18.250358 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
1251 12:43:18.253470 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1252 12:43:18.256901 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1253 12:43:18.263665 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1254 12:43:18.267399 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1255 12:43:18.270317 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1256 12:43:18.273439 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1257 12:43:18.276698 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1258 12:43:18.283555 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1259 12:43:18.284003 ==
1260 12:43:18.286751 Dram Type= 6, Freq= 0, CH_0, rank 1
1261 12:43:18.290539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1262 12:43:18.290973 ==
1263 12:43:18.291415 DQS Delay:
1264 12:43:18.293639 DQS0 = 0, DQS1 = 0
1265 12:43:18.294066 DQM Delay:
1266 12:43:18.296767 DQM0 = 94, DQM1 = 81
1267 12:43:18.297234 DQ Delay:
1268 12:43:18.300481 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1269 12:43:18.303727 DQ4 =93, DQ5 =85, DQ6 =101, DQ7 =109
1270 12:43:18.306679 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1271 12:43:18.310443 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =85
1272 12:43:18.310935
1273 12:43:18.311284
1274 12:43:18.311593 ==
1275 12:43:18.313524 Dram Type= 6, Freq= 0, CH_0, rank 1
1276 12:43:18.317306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1277 12:43:18.317804 ==
1278 12:43:18.320448
1279 12:43:18.321035
1280 12:43:18.321372 TX Vref Scan disable
1281 12:43:18.323619 == TX Byte 0 ==
1282 12:43:18.326786 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1283 12:43:18.330844 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1284 12:43:18.334138 == TX Byte 1 ==
1285 12:43:18.337468 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1286 12:43:18.340788 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1287 12:43:18.341335 ==
1288 12:43:18.344046 Dram Type= 6, Freq= 0, CH_0, rank 1
1289 12:43:18.350752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1290 12:43:18.351331 ==
1291 12:43:18.362550 TX Vref=22, minBit 10, minWin=27, winSum=449
1292 12:43:18.365890 TX Vref=24, minBit 1, minWin=28, winSum=454
1293 12:43:18.369219 TX Vref=26, minBit 1, minWin=28, winSum=454
1294 12:43:18.372390 TX Vref=28, minBit 8, minWin=28, winSum=457
1295 12:43:18.375843 TX Vref=30, minBit 7, minWin=28, winSum=458
1296 12:43:18.378890 TX Vref=32, minBit 4, minWin=28, winSum=455
1297 12:43:18.386251 [TxChooseVref] Worse bit 7, Min win 28, Win sum 458, Final Vref 30
1298 12:43:18.386712
1299 12:43:18.389251 Final TX Range 1 Vref 30
1300 12:43:18.389724
1301 12:43:18.390025 ==
1302 12:43:18.392279 Dram Type= 6, Freq= 0, CH_0, rank 1
1303 12:43:18.395540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1304 12:43:18.395834 ==
1305 12:43:18.396063
1306 12:43:18.399187
1307 12:43:18.399510 TX Vref Scan disable
1308 12:43:18.402261 == TX Byte 0 ==
1309 12:43:18.405396 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1310 12:43:18.408751 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1311 12:43:18.412528 == TX Byte 1 ==
1312 12:43:18.415696 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1313 12:43:18.418869 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1314 12:43:18.422500
1315 12:43:18.422790 [DATLAT]
1316 12:43:18.423019 Freq=800, CH0 RK1
1317 12:43:18.423234
1318 12:43:18.425620 DATLAT Default: 0xa
1319 12:43:18.425915 0, 0xFFFF, sum = 0
1320 12:43:18.429331 1, 0xFFFF, sum = 0
1321 12:43:18.429671 2, 0xFFFF, sum = 0
1322 12:43:18.432568 3, 0xFFFF, sum = 0
1323 12:43:18.432930 4, 0xFFFF, sum = 0
1324 12:43:18.435986 5, 0xFFFF, sum = 0
1325 12:43:18.438760 6, 0xFFFF, sum = 0
1326 12:43:18.439068 7, 0xFFFF, sum = 0
1327 12:43:18.442747 8, 0xFFFF, sum = 0
1328 12:43:18.443129 9, 0x0, sum = 1
1329 12:43:18.443377 10, 0x0, sum = 2
1330 12:43:18.445461 11, 0x0, sum = 3
1331 12:43:18.445761 12, 0x0, sum = 4
1332 12:43:18.448759 best_step = 10
1333 12:43:18.449082
1334 12:43:18.449311 ==
1335 12:43:18.452653 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 12:43:18.456049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 12:43:18.456407 ==
1338 12:43:18.459255 RX Vref Scan: 0
1339 12:43:18.459597
1340 12:43:18.459863 RX Vref 0 -> 0, step: 1
1341 12:43:18.460084
1342 12:43:18.462698 RX Delay -95 -> 252, step: 8
1343 12:43:18.469264 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1344 12:43:18.472608 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1345 12:43:18.475907 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1346 12:43:18.479125 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1347 12:43:18.482398 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1348 12:43:18.489158 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1349 12:43:18.492454 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1350 12:43:18.496121 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1351 12:43:18.499293 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1352 12:43:18.502564 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1353 12:43:18.505659 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1354 12:43:18.512612 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1355 12:43:18.515581 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1356 12:43:18.519312 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1357 12:43:18.522629 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1358 12:43:18.529442 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1359 12:43:18.529990 ==
1360 12:43:18.532583 Dram Type= 6, Freq= 0, CH_0, rank 1
1361 12:43:18.535833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1362 12:43:18.536279 ==
1363 12:43:18.536690 DQS Delay:
1364 12:43:18.539325 DQS0 = 0, DQS1 = 0
1365 12:43:18.539742 DQM Delay:
1366 12:43:18.542593 DQM0 = 93, DQM1 = 82
1367 12:43:18.543001 DQ Delay:
1368 12:43:18.545847 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1369 12:43:18.549009 DQ4 =96, DQ5 =88, DQ6 =100, DQ7 =100
1370 12:43:18.553058 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1371 12:43:18.555758 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =88
1372 12:43:18.556194
1373 12:43:18.556526
1374 12:43:18.562421 [DQSOSCAuto] RK1, (LSB)MR18= 0x4617, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1375 12:43:18.565887 CH0 RK1: MR19=606, MR18=4617
1376 12:43:18.572603 CH0_RK1: MR19=0x606, MR18=0x4617, DQSOSC=392, MR23=63, INC=96, DEC=64
1377 12:43:18.576084 [RxdqsGatingPostProcess] freq 800
1378 12:43:18.582615 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1379 12:43:18.583121 Pre-setting of DQS Precalculation
1380 12:43:18.589169 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1381 12:43:18.589655 ==
1382 12:43:18.592362 Dram Type= 6, Freq= 0, CH_1, rank 0
1383 12:43:18.595858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1384 12:43:18.596442 ==
1385 12:43:18.602350 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1386 12:43:18.609452 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1387 12:43:18.617181 [CA 0] Center 36 (6~67) winsize 62
1388 12:43:18.620679 [CA 1] Center 36 (6~67) winsize 62
1389 12:43:18.623920 [CA 2] Center 35 (5~65) winsize 61
1390 12:43:18.627760 [CA 3] Center 34 (4~65) winsize 62
1391 12:43:18.631000 [CA 4] Center 34 (4~65) winsize 62
1392 12:43:18.634152 [CA 5] Center 34 (4~64) winsize 61
1393 12:43:18.634770
1394 12:43:18.637719 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1395 12:43:18.638181
1396 12:43:18.640874 [CATrainingPosCal] consider 1 rank data
1397 12:43:18.643913 u2DelayCellTimex100 = 270/100 ps
1398 12:43:18.647405 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1399 12:43:18.650467 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1400 12:43:18.657248 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1401 12:43:18.660483 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1402 12:43:18.664587 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1403 12:43:18.667152 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1404 12:43:18.667588
1405 12:43:18.670912 CA PerBit enable=1, Macro0, CA PI delay=34
1406 12:43:18.671359
1407 12:43:18.674113 [CBTSetCACLKResult] CA Dly = 34
1408 12:43:18.674554 CS Dly: 6 (0~37)
1409 12:43:18.674986 ==
1410 12:43:18.677530 Dram Type= 6, Freq= 0, CH_1, rank 1
1411 12:43:18.684139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1412 12:43:18.684623 ==
1413 12:43:18.687541 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1414 12:43:18.694596 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1415 12:43:18.703968 [CA 0] Center 36 (6~67) winsize 62
1416 12:43:18.707578 [CA 1] Center 37 (6~68) winsize 63
1417 12:43:18.711775 [CA 2] Center 35 (4~66) winsize 63
1418 12:43:18.715076 [CA 3] Center 34 (4~65) winsize 62
1419 12:43:18.718785 [CA 4] Center 35 (4~66) winsize 63
1420 12:43:18.722601 [CA 5] Center 34 (4~65) winsize 62
1421 12:43:18.723036
1422 12:43:18.726275 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1423 12:43:18.726821
1424 12:43:18.729980 [CATrainingPosCal] consider 2 rank data
1425 12:43:18.730417 u2DelayCellTimex100 = 270/100 ps
1426 12:43:18.733181 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1427 12:43:18.739702 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1428 12:43:18.743393 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1429 12:43:18.746366 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1430 12:43:18.749932 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1431 12:43:18.753185 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1432 12:43:18.753602
1433 12:43:18.756170 CA PerBit enable=1, Macro0, CA PI delay=34
1434 12:43:18.756587
1435 12:43:18.760044 [CBTSetCACLKResult] CA Dly = 34
1436 12:43:18.760545 CS Dly: 6 (0~38)
1437 12:43:18.763372
1438 12:43:18.766894 ----->DramcWriteLeveling(PI) begin...
1439 12:43:18.767370 ==
1440 12:43:18.770145 Dram Type= 6, Freq= 0, CH_1, rank 0
1441 12:43:18.773560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1442 12:43:18.773989 ==
1443 12:43:18.776873 Write leveling (Byte 0): 27 => 27
1444 12:43:18.779983 Write leveling (Byte 1): 28 => 28
1445 12:43:18.783316 DramcWriteLeveling(PI) end<-----
1446 12:43:18.783788
1447 12:43:18.784144 ==
1448 12:43:18.786768 Dram Type= 6, Freq= 0, CH_1, rank 0
1449 12:43:18.790142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1450 12:43:18.790713 ==
1451 12:43:18.793255 [Gating] SW mode calibration
1452 12:43:18.800052 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1453 12:43:18.803190 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1454 12:43:18.810008 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1455 12:43:18.813794 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1456 12:43:18.817100 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 12:43:18.823819 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 12:43:18.826478 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 12:43:18.829891 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 12:43:18.836669 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 12:43:18.840328 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 12:43:18.843560 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 12:43:18.850350 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 12:43:18.853617 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 12:43:18.857209 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 12:43:18.863438 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 12:43:18.867054 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 12:43:18.870425 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 12:43:18.877063 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 12:43:18.880613 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 12:43:18.883864 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1472 12:43:18.887111 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 12:43:18.893860 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 12:43:18.896911 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 12:43:18.900321 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 12:43:18.906895 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 12:43:18.910244 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 12:43:18.913581 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 12:43:18.920619 0 9 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
1480 12:43:18.923913 0 9 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1481 12:43:18.926988 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 12:43:18.933799 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 12:43:18.936963 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 12:43:18.940212 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 12:43:18.947021 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 12:43:18.950142 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 12:43:18.953834 0 10 4 | B1->B0 | 3333 2d2d | 0 0 | (0 1) (0 1)
1488 12:43:18.957004 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 12:43:18.963951 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 12:43:18.967180 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 12:43:18.970183 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 12:43:18.977258 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 12:43:18.980489 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 12:43:18.983790 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 12:43:18.990475 0 11 4 | B1->B0 | 2525 3636 | 0 0 | (0 0) (0 0)
1496 12:43:18.993802 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
1497 12:43:18.997111 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 12:43:19.003583 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 12:43:19.007404 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 12:43:19.010632 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 12:43:19.016916 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 12:43:19.020389 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1503 12:43:19.023743 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 12:43:19.030450 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1505 12:43:19.033677 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 12:43:19.036710 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 12:43:19.044192 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 12:43:19.047278 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 12:43:19.050450 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 12:43:19.053777 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 12:43:19.060885 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 12:43:19.064037 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 12:43:19.067083 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 12:43:19.073506 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 12:43:19.077278 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 12:43:19.080510 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 12:43:19.087389 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 12:43:19.090644 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1519 12:43:19.093845 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1520 12:43:19.097126 Total UI for P1: 0, mck2ui 16
1521 12:43:19.100458 best dqsien dly found for B1: ( 0, 14, 2)
1522 12:43:19.106999 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1523 12:43:19.107580 Total UI for P1: 0, mck2ui 16
1524 12:43:19.110706 best dqsien dly found for B0: ( 0, 14, 2)
1525 12:43:19.117479 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1526 12:43:19.120762 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1527 12:43:19.121228
1528 12:43:19.124177 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1529 12:43:19.127454 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1530 12:43:19.130888 [Gating] SW calibration Done
1531 12:43:19.131309 ==
1532 12:43:19.134026 Dram Type= 6, Freq= 0, CH_1, rank 0
1533 12:43:19.137301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1534 12:43:19.137774 ==
1535 12:43:19.138137 RX Vref Scan: 0
1536 12:43:19.140598
1537 12:43:19.141126 RX Vref 0 -> 0, step: 1
1538 12:43:19.141480
1539 12:43:19.143999 RX Delay -130 -> 252, step: 16
1540 12:43:19.147189 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1541 12:43:19.150469 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1542 12:43:19.157655 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1543 12:43:19.161069 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1544 12:43:19.164557 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1545 12:43:19.167543 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1546 12:43:19.170677 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1547 12:43:19.177746 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1548 12:43:19.180861 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1549 12:43:19.184290 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1550 12:43:19.187359 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1551 12:43:19.190992 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1552 12:43:19.197964 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1553 12:43:19.201094 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1554 12:43:19.204310 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1555 12:43:19.207547 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1556 12:43:19.208090 ==
1557 12:43:19.211537 Dram Type= 6, Freq= 0, CH_1, rank 0
1558 12:43:19.214717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1559 12:43:19.217913 ==
1560 12:43:19.218412 DQS Delay:
1561 12:43:19.218821 DQS0 = 0, DQS1 = 0
1562 12:43:19.221183 DQM Delay:
1563 12:43:19.221600 DQM0 = 93, DQM1 = 87
1564 12:43:19.224523 DQ Delay:
1565 12:43:19.227782 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1566 12:43:19.228337 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1567 12:43:19.231086 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1568 12:43:19.237834 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1569 12:43:19.238265
1570 12:43:19.238677
1571 12:43:19.238993 ==
1572 12:43:19.241061 Dram Type= 6, Freq= 0, CH_1, rank 0
1573 12:43:19.244370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1574 12:43:19.245000 ==
1575 12:43:19.245486
1576 12:43:19.245857
1577 12:43:19.247900 TX Vref Scan disable
1578 12:43:19.248327 == TX Byte 0 ==
1579 12:43:19.254420 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1580 12:43:19.257842 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1581 12:43:19.258272 == TX Byte 1 ==
1582 12:43:19.264911 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1583 12:43:19.267809 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1584 12:43:19.268235 ==
1585 12:43:19.271205 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 12:43:19.275027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1587 12:43:19.275456 ==
1588 12:43:19.287867 TX Vref=22, minBit 1, minWin=26, winSum=435
1589 12:43:19.291171 TX Vref=24, minBit 0, minWin=27, winSum=441
1590 12:43:19.295192 TX Vref=26, minBit 2, minWin=27, winSum=447
1591 12:43:19.298295 TX Vref=28, minBit 1, minWin=27, winSum=447
1592 12:43:19.301408 TX Vref=30, minBit 1, minWin=27, winSum=451
1593 12:43:19.304477 TX Vref=32, minBit 1, minWin=27, winSum=448
1594 12:43:19.311183 [TxChooseVref] Worse bit 1, Min win 27, Win sum 451, Final Vref 30
1595 12:43:19.311703
1596 12:43:19.314322 Final TX Range 1 Vref 30
1597 12:43:19.314766
1598 12:43:19.315098 ==
1599 12:43:19.318350 Dram Type= 6, Freq= 0, CH_1, rank 0
1600 12:43:19.321424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1601 12:43:19.321853 ==
1602 12:43:19.322211
1603 12:43:19.322525
1604 12:43:19.324791 TX Vref Scan disable
1605 12:43:19.328199 == TX Byte 0 ==
1606 12:43:19.331165 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1607 12:43:19.335095 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1608 12:43:19.337750 == TX Byte 1 ==
1609 12:43:19.341254 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1610 12:43:19.345024 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1611 12:43:19.345431
1612 12:43:19.348423 [DATLAT]
1613 12:43:19.348879 Freq=800, CH1 RK0
1614 12:43:19.349241
1615 12:43:19.351848 DATLAT Default: 0xa
1616 12:43:19.352320 0, 0xFFFF, sum = 0
1617 12:43:19.355097 1, 0xFFFF, sum = 0
1618 12:43:19.355521 2, 0xFFFF, sum = 0
1619 12:43:19.358712 3, 0xFFFF, sum = 0
1620 12:43:19.359245 4, 0xFFFF, sum = 0
1621 12:43:19.361213 5, 0xFFFF, sum = 0
1622 12:43:19.361651 6, 0xFFFF, sum = 0
1623 12:43:19.364616 7, 0xFFFF, sum = 0
1624 12:43:19.365113 8, 0xFFFF, sum = 0
1625 12:43:19.368022 9, 0x0, sum = 1
1626 12:43:19.368467 10, 0x0, sum = 2
1627 12:43:19.371932 11, 0x0, sum = 3
1628 12:43:19.372400 12, 0x0, sum = 4
1629 12:43:19.374844 best_step = 10
1630 12:43:19.375350
1631 12:43:19.375782 ==
1632 12:43:19.378739 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 12:43:19.381963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 12:43:19.382423 ==
1635 12:43:19.382768 RX Vref Scan: 1
1636 12:43:19.385122
1637 12:43:19.385542 Set Vref Range= 32 -> 127
1638 12:43:19.385873
1639 12:43:19.388062 RX Vref 32 -> 127, step: 1
1640 12:43:19.388476
1641 12:43:19.391832 RX Delay -79 -> 252, step: 8
1642 12:43:19.392250
1643 12:43:19.395088 Set Vref, RX VrefLevel [Byte0]: 32
1644 12:43:19.398248 [Byte1]: 32
1645 12:43:19.398665
1646 12:43:19.402273 Set Vref, RX VrefLevel [Byte0]: 33
1647 12:43:19.405293 [Byte1]: 33
1648 12:43:19.405711
1649 12:43:19.408703 Set Vref, RX VrefLevel [Byte0]: 34
1650 12:43:19.411954 [Byte1]: 34
1651 12:43:19.415608
1652 12:43:19.416153 Set Vref, RX VrefLevel [Byte0]: 35
1653 12:43:19.418857 [Byte1]: 35
1654 12:43:19.423301
1655 12:43:19.423847 Set Vref, RX VrefLevel [Byte0]: 36
1656 12:43:19.426696 [Byte1]: 36
1657 12:43:19.430561
1658 12:43:19.430976 Set Vref, RX VrefLevel [Byte0]: 37
1659 12:43:19.434049 [Byte1]: 37
1660 12:43:19.438399
1661 12:43:19.438854 Set Vref, RX VrefLevel [Byte0]: 38
1662 12:43:19.441330 [Byte1]: 38
1663 12:43:19.445744
1664 12:43:19.446163 Set Vref, RX VrefLevel [Byte0]: 39
1665 12:43:19.449136 [Byte1]: 39
1666 12:43:19.453094
1667 12:43:19.453576 Set Vref, RX VrefLevel [Byte0]: 40
1668 12:43:19.457012 [Byte1]: 40
1669 12:43:19.460904
1670 12:43:19.461319 Set Vref, RX VrefLevel [Byte0]: 41
1671 12:43:19.464322 [Byte1]: 41
1672 12:43:19.468541
1673 12:43:19.469051 Set Vref, RX VrefLevel [Byte0]: 42
1674 12:43:19.471949 [Byte1]: 42
1675 12:43:19.475700
1676 12:43:19.476117 Set Vref, RX VrefLevel [Byte0]: 43
1677 12:43:19.479731 [Byte1]: 43
1678 12:43:19.483427
1679 12:43:19.483912 Set Vref, RX VrefLevel [Byte0]: 44
1680 12:43:19.487135 [Byte1]: 44
1681 12:43:19.491084
1682 12:43:19.491507 Set Vref, RX VrefLevel [Byte0]: 45
1683 12:43:19.494099 [Byte1]: 45
1684 12:43:19.498682
1685 12:43:19.499189 Set Vref, RX VrefLevel [Byte0]: 46
1686 12:43:19.501862 [Byte1]: 46
1687 12:43:19.506374
1688 12:43:19.506793 Set Vref, RX VrefLevel [Byte0]: 47
1689 12:43:19.509352 [Byte1]: 47
1690 12:43:19.513885
1691 12:43:19.514314 Set Vref, RX VrefLevel [Byte0]: 48
1692 12:43:19.517334 [Byte1]: 48
1693 12:43:19.521275
1694 12:43:19.521730 Set Vref, RX VrefLevel [Byte0]: 49
1695 12:43:19.524251 [Byte1]: 49
1696 12:43:19.528658
1697 12:43:19.529141 Set Vref, RX VrefLevel [Byte0]: 50
1698 12:43:19.532291 [Byte1]: 50
1699 12:43:19.536323
1700 12:43:19.536739 Set Vref, RX VrefLevel [Byte0]: 51
1701 12:43:19.539625 [Byte1]: 51
1702 12:43:19.544132
1703 12:43:19.544555 Set Vref, RX VrefLevel [Byte0]: 52
1704 12:43:19.547424 [Byte1]: 52
1705 12:43:19.551494
1706 12:43:19.551924 Set Vref, RX VrefLevel [Byte0]: 53
1707 12:43:19.554734 [Byte1]: 53
1708 12:43:19.558713
1709 12:43:19.559150 Set Vref, RX VrefLevel [Byte0]: 54
1710 12:43:19.562064 [Byte1]: 54
1711 12:43:19.566835
1712 12:43:19.567254 Set Vref, RX VrefLevel [Byte0]: 55
1713 12:43:19.569683 [Byte1]: 55
1714 12:43:19.574146
1715 12:43:19.574728 Set Vref, RX VrefLevel [Byte0]: 56
1716 12:43:19.577394 [Byte1]: 56
1717 12:43:19.581559
1718 12:43:19.582011 Set Vref, RX VrefLevel [Byte0]: 57
1719 12:43:19.584761 [Byte1]: 57
1720 12:43:19.588970
1721 12:43:19.589452 Set Vref, RX VrefLevel [Byte0]: 58
1722 12:43:19.592388 [Byte1]: 58
1723 12:43:19.596870
1724 12:43:19.597293 Set Vref, RX VrefLevel [Byte0]: 59
1725 12:43:19.599787 [Byte1]: 59
1726 12:43:19.604142
1727 12:43:19.604559 Set Vref, RX VrefLevel [Byte0]: 60
1728 12:43:19.607306 [Byte1]: 60
1729 12:43:19.611892
1730 12:43:19.612311 Set Vref, RX VrefLevel [Byte0]: 61
1731 12:43:19.615039 [Byte1]: 61
1732 12:43:19.619349
1733 12:43:19.619926 Set Vref, RX VrefLevel [Byte0]: 62
1734 12:43:19.622584 [Byte1]: 62
1735 12:43:19.626855
1736 12:43:19.627291 Set Vref, RX VrefLevel [Byte0]: 63
1737 12:43:19.629976 [Byte1]: 63
1738 12:43:19.634472
1739 12:43:19.634892 Set Vref, RX VrefLevel [Byte0]: 64
1740 12:43:19.637672 [Byte1]: 64
1741 12:43:19.641811
1742 12:43:19.642408 Set Vref, RX VrefLevel [Byte0]: 65
1743 12:43:19.645158 [Byte1]: 65
1744 12:43:19.649798
1745 12:43:19.650406 Set Vref, RX VrefLevel [Byte0]: 66
1746 12:43:19.653173 [Byte1]: 66
1747 12:43:19.656949
1748 12:43:19.657386 Set Vref, RX VrefLevel [Byte0]: 67
1749 12:43:19.660052 [Byte1]: 67
1750 12:43:19.664688
1751 12:43:19.665163 Set Vref, RX VrefLevel [Byte0]: 68
1752 12:43:19.668226 [Byte1]: 68
1753 12:43:19.672184
1754 12:43:19.672605 Set Vref, RX VrefLevel [Byte0]: 69
1755 12:43:19.675357 [Byte1]: 69
1756 12:43:19.679547
1757 12:43:19.680122 Set Vref, RX VrefLevel [Byte0]: 70
1758 12:43:19.682841 [Byte1]: 70
1759 12:43:19.687554
1760 12:43:19.688127 Set Vref, RX VrefLevel [Byte0]: 71
1761 12:43:19.690691 [Byte1]: 71
1762 12:43:19.695254
1763 12:43:19.695677 Set Vref, RX VrefLevel [Byte0]: 72
1764 12:43:19.697923 [Byte1]: 72
1765 12:43:19.702509
1766 12:43:19.703092 Set Vref, RX VrefLevel [Byte0]: 73
1767 12:43:19.705998 [Byte1]: 73
1768 12:43:19.709957
1769 12:43:19.710387 Set Vref, RX VrefLevel [Byte0]: 74
1770 12:43:19.713503 [Byte1]: 74
1771 12:43:19.717612
1772 12:43:19.718054 Final RX Vref Byte 0 = 56 to rank0
1773 12:43:19.720852 Final RX Vref Byte 1 = 57 to rank0
1774 12:43:19.724631 Final RX Vref Byte 0 = 56 to rank1
1775 12:43:19.727695 Final RX Vref Byte 1 = 57 to rank1==
1776 12:43:19.730976 Dram Type= 6, Freq= 0, CH_1, rank 0
1777 12:43:19.734353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1778 12:43:19.737752 ==
1779 12:43:19.738177 DQS Delay:
1780 12:43:19.738511 DQS0 = 0, DQS1 = 0
1781 12:43:19.740918 DQM Delay:
1782 12:43:19.741326 DQM0 = 95, DQM1 = 89
1783 12:43:19.744227 DQ Delay:
1784 12:43:19.747278 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1785 12:43:19.747828 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1786 12:43:19.750871 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1787 12:43:19.754729 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1788 12:43:19.757977
1789 12:43:19.758457
1790 12:43:19.764308 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b47, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
1791 12:43:19.767621 CH1 RK0: MR19=606, MR18=2B47
1792 12:43:19.774312 CH1_RK0: MR19=0x606, MR18=0x2B47, DQSOSC=392, MR23=63, INC=96, DEC=64
1793 12:43:19.774923
1794 12:43:19.777929 ----->DramcWriteLeveling(PI) begin...
1795 12:43:19.778512 ==
1796 12:43:19.781080 Dram Type= 6, Freq= 0, CH_1, rank 1
1797 12:43:19.784343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1798 12:43:19.784934 ==
1799 12:43:19.787736 Write leveling (Byte 0): 27 => 27
1800 12:43:19.791084 Write leveling (Byte 1): 27 => 27
1801 12:43:19.794498 DramcWriteLeveling(PI) end<-----
1802 12:43:19.794939
1803 12:43:19.795277 ==
1804 12:43:19.797681 Dram Type= 6, Freq= 0, CH_1, rank 1
1805 12:43:19.800923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1806 12:43:19.801394 ==
1807 12:43:19.804350 [Gating] SW mode calibration
1808 12:43:19.810922 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1809 12:43:19.817561 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1810 12:43:19.820723 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1811 12:43:19.824367 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1812 12:43:19.830984 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 12:43:19.833996 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 12:43:19.837768 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 12:43:19.844217 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 12:43:19.847788 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 12:43:19.850861 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 12:43:19.857596 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 12:43:19.861226 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 12:43:19.864192 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 12:43:19.870877 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 12:43:19.874075 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 12:43:19.877442 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 12:43:19.880728 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 12:43:19.887402 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 12:43:19.890827 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1827 12:43:19.894137 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1828 12:43:19.900767 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 12:43:19.904024 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 12:43:19.907320 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 12:43:19.914100 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 12:43:19.917326 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 12:43:19.920751 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 12:43:19.927771 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 12:43:19.930899 0 9 4 | B1->B0 | 2a2a 2323 | 1 0 | (1 1) (1 1)
1836 12:43:19.933986 0 9 8 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
1837 12:43:19.940868 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 12:43:19.944269 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 12:43:19.948123 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 12:43:19.954369 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 12:43:19.957929 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 12:43:19.961075 0 10 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1843 12:43:19.964263 0 10 4 | B1->B0 | 2626 3030 | 0 1 | (0 0) (0 1)
1844 12:43:19.971288 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 12:43:19.974146 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 12:43:19.978204 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 12:43:19.984125 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 12:43:19.988218 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 12:43:19.990809 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 12:43:19.997490 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 12:43:20.000752 0 11 4 | B1->B0 | 3737 2f2f | 0 0 | (0 0) (0 0)
1852 12:43:20.004729 0 11 8 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
1853 12:43:20.011409 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 12:43:20.014634 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 12:43:20.018036 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 12:43:20.024729 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 12:43:20.027433 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 12:43:20.031361 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1859 12:43:20.038159 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1860 12:43:20.041349 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 12:43:20.044859 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 12:43:20.048171 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 12:43:20.054809 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 12:43:20.058005 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 12:43:20.061248 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 12:43:20.068023 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 12:43:20.071261 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 12:43:20.074392 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 12:43:20.081344 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 12:43:20.084477 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 12:43:20.087880 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 12:43:20.094585 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 12:43:20.098253 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 12:43:20.101482 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 12:43:20.108178 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1876 12:43:20.111474 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1877 12:43:20.114569 Total UI for P1: 0, mck2ui 16
1878 12:43:20.117913 best dqsien dly found for B0: ( 0, 14, 4)
1879 12:43:20.121206 Total UI for P1: 0, mck2ui 16
1880 12:43:20.124658 best dqsien dly found for B1: ( 0, 14, 4)
1881 12:43:20.127860 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1882 12:43:20.131330 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1883 12:43:20.131897
1884 12:43:20.134684 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1885 12:43:20.137999 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1886 12:43:20.141320 [Gating] SW calibration Done
1887 12:43:20.141893 ==
1888 12:43:20.144611 Dram Type= 6, Freq= 0, CH_1, rank 1
1889 12:43:20.148170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1890 12:43:20.148691 ==
1891 12:43:20.151324 RX Vref Scan: 0
1892 12:43:20.151867
1893 12:43:20.152206 RX Vref 0 -> 0, step: 1
1894 12:43:20.154767
1895 12:43:20.155184 RX Delay -130 -> 252, step: 16
1896 12:43:20.161571 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1897 12:43:20.164501 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1898 12:43:20.167758 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1899 12:43:20.171576 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1900 12:43:20.174519 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1901 12:43:20.181629 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1902 12:43:20.185409 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1903 12:43:20.187839 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1904 12:43:20.191145 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1905 12:43:20.194861 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1906 12:43:20.198250 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1907 12:43:20.204898 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1908 12:43:20.208321 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1909 12:43:20.210983 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1910 12:43:20.214272 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1911 12:43:20.221487 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1912 12:43:20.221920 ==
1913 12:43:20.224769 Dram Type= 6, Freq= 0, CH_1, rank 1
1914 12:43:20.227943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1915 12:43:20.228525 ==
1916 12:43:20.228899 DQS Delay:
1917 12:43:20.231362 DQS0 = 0, DQS1 = 0
1918 12:43:20.231777 DQM Delay:
1919 12:43:20.234733 DQM0 = 93, DQM1 = 87
1920 12:43:20.235210 DQ Delay:
1921 12:43:20.237879 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1922 12:43:20.241322 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1923 12:43:20.244689 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1924 12:43:20.247942 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1925 12:43:20.248505
1926 12:43:20.249003
1927 12:43:20.249331 ==
1928 12:43:20.251246 Dram Type= 6, Freq= 0, CH_1, rank 1
1929 12:43:20.254620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1930 12:43:20.255148 ==
1931 12:43:20.255516
1932 12:43:20.257753
1933 12:43:20.258255 TX Vref Scan disable
1934 12:43:20.261387 == TX Byte 0 ==
1935 12:43:20.264687 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1936 12:43:20.267908 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1937 12:43:20.271604 == TX Byte 1 ==
1938 12:43:20.274792 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1939 12:43:20.277894 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1940 12:43:20.278397 ==
1941 12:43:20.281262 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 12:43:20.287668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 12:43:20.288095 ==
1944 12:43:20.299664 TX Vref=22, minBit 0, minWin=27, winSum=443
1945 12:43:20.302702 TX Vref=24, minBit 0, minWin=27, winSum=444
1946 12:43:20.305992 TX Vref=26, minBit 2, minWin=27, winSum=448
1947 12:43:20.309866 TX Vref=28, minBit 2, minWin=27, winSum=449
1948 12:43:20.313089 TX Vref=30, minBit 2, minWin=27, winSum=449
1949 12:43:20.316660 TX Vref=32, minBit 2, minWin=27, winSum=448
1950 12:43:20.322579 [TxChooseVref] Worse bit 2, Min win 27, Win sum 449, Final Vref 28
1951 12:43:20.323162
1952 12:43:20.326587 Final TX Range 1 Vref 28
1953 12:43:20.327166
1954 12:43:20.327650 ==
1955 12:43:20.329745 Dram Type= 6, Freq= 0, CH_1, rank 1
1956 12:43:20.333229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1957 12:43:20.333742 ==
1958 12:43:20.334090
1959 12:43:20.336488
1960 12:43:20.337000 TX Vref Scan disable
1961 12:43:20.339300 == TX Byte 0 ==
1962 12:43:20.342841 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1963 12:43:20.345901 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1964 12:43:20.349946 == TX Byte 1 ==
1965 12:43:20.352597 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1966 12:43:20.356588 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1967 12:43:20.359287
1968 12:43:20.359756 [DATLAT]
1969 12:43:20.360096 Freq=800, CH1 RK1
1970 12:43:20.360415
1971 12:43:20.363023 DATLAT Default: 0xa
1972 12:43:20.363553 0, 0xFFFF, sum = 0
1973 12:43:20.366235 1, 0xFFFF, sum = 0
1974 12:43:20.366665 2, 0xFFFF, sum = 0
1975 12:43:20.369705 3, 0xFFFF, sum = 0
1976 12:43:20.370266 4, 0xFFFF, sum = 0
1977 12:43:20.372841 5, 0xFFFF, sum = 0
1978 12:43:20.373390 6, 0xFFFF, sum = 0
1979 12:43:20.375975 7, 0xFFFF, sum = 0
1980 12:43:20.379673 8, 0xFFFF, sum = 0
1981 12:43:20.380124 9, 0x0, sum = 1
1982 12:43:20.380470 10, 0x0, sum = 2
1983 12:43:20.382703 11, 0x0, sum = 3
1984 12:43:20.383210 12, 0x0, sum = 4
1985 12:43:20.386192 best_step = 10
1986 12:43:20.386652
1987 12:43:20.387055 ==
1988 12:43:20.389611 Dram Type= 6, Freq= 0, CH_1, rank 1
1989 12:43:20.392873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1990 12:43:20.393321 ==
1991 12:43:20.396033 RX Vref Scan: 0
1992 12:43:20.396483
1993 12:43:20.396973 RX Vref 0 -> 0, step: 1
1994 12:43:20.397376
1995 12:43:20.399988 RX Delay -79 -> 252, step: 8
1996 12:43:20.406022 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1997 12:43:20.409843 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1998 12:43:20.413036 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1999 12:43:20.416297 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2000 12:43:20.419816 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2001 12:43:20.423055 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2002 12:43:20.429524 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2003 12:43:20.432979 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2004 12:43:20.436356 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2005 12:43:20.439652 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2006 12:43:20.442975 iDelay=209, Bit 10, Center 88 (-15 ~ 192) 208
2007 12:43:20.449714 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
2008 12:43:20.453209 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2009 12:43:20.456527 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2010 12:43:20.459851 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2011 12:43:20.463061 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2012 12:43:20.463492 ==
2013 12:43:20.466414 Dram Type= 6, Freq= 0, CH_1, rank 1
2014 12:43:20.473130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2015 12:43:20.473562 ==
2016 12:43:20.473900 DQS Delay:
2017 12:43:20.476754 DQS0 = 0, DQS1 = 0
2018 12:43:20.477351 DQM Delay:
2019 12:43:20.477698 DQM0 = 97, DQM1 = 90
2020 12:43:20.480101 DQ Delay:
2021 12:43:20.483074 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2022 12:43:20.486861 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2023 12:43:20.490032 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
2024 12:43:20.493320 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2025 12:43:20.493755
2026 12:43:20.494269
2027 12:43:20.499965 [DQSOSCAuto] RK1, (LSB)MR18= 0x440f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2028 12:43:20.503542 CH1 RK1: MR19=606, MR18=440F
2029 12:43:20.510359 CH1_RK1: MR19=0x606, MR18=0x440F, DQSOSC=392, MR23=63, INC=96, DEC=64
2030 12:43:20.513656 [RxdqsGatingPostProcess] freq 800
2031 12:43:20.517143 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2032 12:43:20.520285 Pre-setting of DQS Precalculation
2033 12:43:20.526959 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2034 12:43:20.533857 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2035 12:43:20.540564 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2036 12:43:20.541032
2037 12:43:20.541360
2038 12:43:20.543206 [Calibration Summary] 1600 Mbps
2039 12:43:20.543829 CH 0, Rank 0
2040 12:43:20.547040 SW Impedance : PASS
2041 12:43:20.550541 DUTY Scan : NO K
2042 12:43:20.550988 ZQ Calibration : PASS
2043 12:43:20.553886 Jitter Meter : NO K
2044 12:43:20.557377 CBT Training : PASS
2045 12:43:20.557810 Write leveling : PASS
2046 12:43:20.560365 RX DQS gating : PASS
2047 12:43:20.560844 RX DQ/DQS(RDDQC) : PASS
2048 12:43:20.563863 TX DQ/DQS : PASS
2049 12:43:20.567229 RX DATLAT : PASS
2050 12:43:20.567655 RX DQ/DQS(Engine): PASS
2051 12:43:20.570565 TX OE : NO K
2052 12:43:20.570991 All Pass.
2053 12:43:20.571329
2054 12:43:20.573829 CH 0, Rank 1
2055 12:43:20.574278 SW Impedance : PASS
2056 12:43:20.577236 DUTY Scan : NO K
2057 12:43:20.580371 ZQ Calibration : PASS
2058 12:43:20.580796 Jitter Meter : NO K
2059 12:43:20.583395 CBT Training : PASS
2060 12:43:20.587133 Write leveling : PASS
2061 12:43:20.587552 RX DQS gating : PASS
2062 12:43:20.590255 RX DQ/DQS(RDDQC) : PASS
2063 12:43:20.593902 TX DQ/DQS : PASS
2064 12:43:20.594344 RX DATLAT : PASS
2065 12:43:20.596849 RX DQ/DQS(Engine): PASS
2066 12:43:20.597298 TX OE : NO K
2067 12:43:20.600439 All Pass.
2068 12:43:20.600906
2069 12:43:20.601257 CH 1, Rank 0
2070 12:43:20.603674 SW Impedance : PASS
2071 12:43:20.604096 DUTY Scan : NO K
2072 12:43:20.607135 ZQ Calibration : PASS
2073 12:43:20.610397 Jitter Meter : NO K
2074 12:43:20.610829 CBT Training : PASS
2075 12:43:20.613773 Write leveling : PASS
2076 12:43:20.616916 RX DQS gating : PASS
2077 12:43:20.617337 RX DQ/DQS(RDDQC) : PASS
2078 12:43:20.620759 TX DQ/DQS : PASS
2079 12:43:20.623884 RX DATLAT : PASS
2080 12:43:20.624443 RX DQ/DQS(Engine): PASS
2081 12:43:20.627633 TX OE : NO K
2082 12:43:20.628068 All Pass.
2083 12:43:20.628577
2084 12:43:20.630800 CH 1, Rank 1
2085 12:43:20.631297 SW Impedance : PASS
2086 12:43:20.634038 DUTY Scan : NO K
2087 12:43:20.637286 ZQ Calibration : PASS
2088 12:43:20.637842 Jitter Meter : NO K
2089 12:43:20.640475 CBT Training : PASS
2090 12:43:20.641032 Write leveling : PASS
2091 12:43:20.643870 RX DQS gating : PASS
2092 12:43:20.647096 RX DQ/DQS(RDDQC) : PASS
2093 12:43:20.647587 TX DQ/DQS : PASS
2094 12:43:20.650537 RX DATLAT : PASS
2095 12:43:20.653944 RX DQ/DQS(Engine): PASS
2096 12:43:20.654377 TX OE : NO K
2097 12:43:20.657267 All Pass.
2098 12:43:20.657699
2099 12:43:20.658057 DramC Write-DBI off
2100 12:43:20.660544 PER_BANK_REFRESH: Hybrid Mode
2101 12:43:20.661088 TX_TRACKING: ON
2102 12:43:20.663750 [GetDramInforAfterCalByMRR] Vendor 6.
2103 12:43:20.670552 [GetDramInforAfterCalByMRR] Revision 606.
2104 12:43:20.673831 [GetDramInforAfterCalByMRR] Revision 2 0.
2105 12:43:20.674327 MR0 0x3b3b
2106 12:43:20.674679 MR8 0x5151
2107 12:43:20.677326 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2108 12:43:20.677881
2109 12:43:20.680506 MR0 0x3b3b
2110 12:43:20.681051 MR8 0x5151
2111 12:43:20.683789 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2112 12:43:20.684347
2113 12:43:20.694122 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2114 12:43:20.697302 [FAST_K] Save calibration result to emmc
2115 12:43:20.700938 [FAST_K] Save calibration result to emmc
2116 12:43:20.703935 dram_init: config_dvfs: 1
2117 12:43:20.707886 dramc_set_vcore_voltage set vcore to 662500
2118 12:43:20.710787 Read voltage for 1200, 2
2119 12:43:20.711230 Vio18 = 0
2120 12:43:20.711567 Vcore = 662500
2121 12:43:20.711891 Vdram = 0
2122 12:43:20.713968 Vddq = 0
2123 12:43:20.714440 Vmddr = 0
2124 12:43:20.720667 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2125 12:43:20.724776 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2126 12:43:20.727816 MEM_TYPE=3, freq_sel=15
2127 12:43:20.731235 sv_algorithm_assistance_LP4_1600
2128 12:43:20.734217 ============ PULL DRAM RESETB DOWN ============
2129 12:43:20.737360 ========== PULL DRAM RESETB DOWN end =========
2130 12:43:20.744197 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2131 12:43:20.747477 ===================================
2132 12:43:20.747949 LPDDR4 DRAM CONFIGURATION
2133 12:43:20.750727 ===================================
2134 12:43:20.754137 EX_ROW_EN[0] = 0x0
2135 12:43:20.754732 EX_ROW_EN[1] = 0x0
2136 12:43:20.757224 LP4Y_EN = 0x0
2137 12:43:20.760756 WORK_FSP = 0x0
2138 12:43:20.761391 WL = 0x4
2139 12:43:20.764053 RL = 0x4
2140 12:43:20.764634 BL = 0x2
2141 12:43:20.767452 RPST = 0x0
2142 12:43:20.767985 RD_PRE = 0x0
2143 12:43:20.770747 WR_PRE = 0x1
2144 12:43:20.771275 WR_PST = 0x0
2145 12:43:20.773972 DBI_WR = 0x0
2146 12:43:20.774506 DBI_RD = 0x0
2147 12:43:20.777199 OTF = 0x1
2148 12:43:20.780772 ===================================
2149 12:43:20.784089 ===================================
2150 12:43:20.784513 ANA top config
2151 12:43:20.787420 ===================================
2152 12:43:20.790783 DLL_ASYNC_EN = 0
2153 12:43:20.793815 ALL_SLAVE_EN = 0
2154 12:43:20.794287 NEW_RANK_MODE = 1
2155 12:43:20.797164 DLL_IDLE_MODE = 1
2156 12:43:20.800657 LP45_APHY_COMB_EN = 1
2157 12:43:20.804245 TX_ODT_DIS = 1
2158 12:43:20.804671 NEW_8X_MODE = 1
2159 12:43:20.807220 ===================================
2160 12:43:20.811055 ===================================
2161 12:43:20.814282 data_rate = 2400
2162 12:43:20.817430 CKR = 1
2163 12:43:20.820966 DQ_P2S_RATIO = 8
2164 12:43:20.824258 ===================================
2165 12:43:20.827401 CA_P2S_RATIO = 8
2166 12:43:20.830671 DQ_CA_OPEN = 0
2167 12:43:20.831158 DQ_SEMI_OPEN = 0
2168 12:43:20.834530 CA_SEMI_OPEN = 0
2169 12:43:20.837852 CA_FULL_RATE = 0
2170 12:43:20.840974 DQ_CKDIV4_EN = 0
2171 12:43:20.844219 CA_CKDIV4_EN = 0
2172 12:43:20.847338 CA_PREDIV_EN = 0
2173 12:43:20.847935 PH8_DLY = 17
2174 12:43:20.850965 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2175 12:43:20.854035 DQ_AAMCK_DIV = 4
2176 12:43:20.857447 CA_AAMCK_DIV = 4
2177 12:43:20.860551 CA_ADMCK_DIV = 4
2178 12:43:20.863902 DQ_TRACK_CA_EN = 0
2179 12:43:20.864480 CA_PICK = 1200
2180 12:43:20.867290 CA_MCKIO = 1200
2181 12:43:20.871111 MCKIO_SEMI = 0
2182 12:43:20.874302 PLL_FREQ = 2366
2183 12:43:20.877883 DQ_UI_PI_RATIO = 32
2184 12:43:20.881175 CA_UI_PI_RATIO = 0
2185 12:43:20.884569 ===================================
2186 12:43:20.887801 ===================================
2187 12:43:20.888216 memory_type:LPDDR4
2188 12:43:20.891189 GP_NUM : 10
2189 12:43:20.894435 SRAM_EN : 1
2190 12:43:20.894852 MD32_EN : 0
2191 12:43:20.897771 ===================================
2192 12:43:20.901192 [ANA_INIT] >>>>>>>>>>>>>>
2193 12:43:20.904600 <<<<<< [CONFIGURE PHASE]: ANA_TX
2194 12:43:20.907840 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2195 12:43:20.910928 ===================================
2196 12:43:20.914115 data_rate = 2400,PCW = 0X5b00
2197 12:43:20.917798 ===================================
2198 12:43:20.920907 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2199 12:43:20.924570 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2200 12:43:20.931367 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2201 12:43:20.934322 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2202 12:43:20.937988 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2203 12:43:20.941058 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2204 12:43:20.944574 [ANA_INIT] flow start
2205 12:43:20.947582 [ANA_INIT] PLL >>>>>>>>
2206 12:43:20.948007 [ANA_INIT] PLL <<<<<<<<
2207 12:43:20.950928 [ANA_INIT] MIDPI >>>>>>>>
2208 12:43:20.954857 [ANA_INIT] MIDPI <<<<<<<<
2209 12:43:20.955334 [ANA_INIT] DLL >>>>>>>>
2210 12:43:20.957833 [ANA_INIT] DLL <<<<<<<<
2211 12:43:20.960967 [ANA_INIT] flow end
2212 12:43:20.964377 ============ LP4 DIFF to SE enter ============
2213 12:43:20.968051 ============ LP4 DIFF to SE exit ============
2214 12:43:20.971565 [ANA_INIT] <<<<<<<<<<<<<
2215 12:43:20.974884 [Flow] Enable top DCM control >>>>>
2216 12:43:20.978023 [Flow] Enable top DCM control <<<<<
2217 12:43:20.981129 Enable DLL master slave shuffle
2218 12:43:20.984591 ==============================================================
2219 12:43:20.988177 Gating Mode config
2220 12:43:20.994864 ==============================================================
2221 12:43:20.995298 Config description:
2222 12:43:21.004592 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2223 12:43:21.011377 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2224 12:43:21.014815 SELPH_MODE 0: By rank 1: By Phase
2225 12:43:21.021783 ==============================================================
2226 12:43:21.024933 GAT_TRACK_EN = 1
2227 12:43:21.028483 RX_GATING_MODE = 2
2228 12:43:21.031465 RX_GATING_TRACK_MODE = 2
2229 12:43:21.034726 SELPH_MODE = 1
2230 12:43:21.038386 PICG_EARLY_EN = 1
2231 12:43:21.038837 VALID_LAT_VALUE = 1
2232 12:43:21.044796 ==============================================================
2233 12:43:21.048481 Enter into Gating configuration >>>>
2234 12:43:21.051936 Exit from Gating configuration <<<<
2235 12:43:21.054913 Enter into DVFS_PRE_config >>>>>
2236 12:43:21.065276 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2237 12:43:21.068526 Exit from DVFS_PRE_config <<<<<
2238 12:43:21.071728 Enter into PICG configuration >>>>
2239 12:43:21.075146 Exit from PICG configuration <<<<
2240 12:43:21.078496 [RX_INPUT] configuration >>>>>
2241 12:43:21.081618 [RX_INPUT] configuration <<<<<
2242 12:43:21.084893 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2243 12:43:21.091606 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2244 12:43:21.098494 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2245 12:43:21.104919 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2246 12:43:21.108834 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2247 12:43:21.115661 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2248 12:43:21.118850 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2249 12:43:21.125479 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2250 12:43:21.128939 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2251 12:43:21.131916 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2252 12:43:21.135159 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2253 12:43:21.142271 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2254 12:43:21.145317 ===================================
2255 12:43:21.145878 LPDDR4 DRAM CONFIGURATION
2256 12:43:21.149000 ===================================
2257 12:43:21.152349 EX_ROW_EN[0] = 0x0
2258 12:43:21.155375 EX_ROW_EN[1] = 0x0
2259 12:43:21.155812 LP4Y_EN = 0x0
2260 12:43:21.158498 WORK_FSP = 0x0
2261 12:43:21.158971 WL = 0x4
2262 12:43:21.162315 RL = 0x4
2263 12:43:21.162790 BL = 0x2
2264 12:43:21.165674 RPST = 0x0
2265 12:43:21.166099 RD_PRE = 0x0
2266 12:43:21.168925 WR_PRE = 0x1
2267 12:43:21.169357 WR_PST = 0x0
2268 12:43:21.172289 DBI_WR = 0x0
2269 12:43:21.172712 DBI_RD = 0x0
2270 12:43:21.175501 OTF = 0x1
2271 12:43:21.178704 ===================================
2272 12:43:21.182390 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2273 12:43:21.185096 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2274 12:43:21.192123 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2275 12:43:21.195791 ===================================
2276 12:43:21.196240 LPDDR4 DRAM CONFIGURATION
2277 12:43:21.198427 ===================================
2278 12:43:21.202245 EX_ROW_EN[0] = 0x10
2279 12:43:21.205788 EX_ROW_EN[1] = 0x0
2280 12:43:21.206211 LP4Y_EN = 0x0
2281 12:43:21.209066 WORK_FSP = 0x0
2282 12:43:21.209486 WL = 0x4
2283 12:43:21.211991 RL = 0x4
2284 12:43:21.212411 BL = 0x2
2285 12:43:21.215568 RPST = 0x0
2286 12:43:21.215989 RD_PRE = 0x0
2287 12:43:21.218990 WR_PRE = 0x1
2288 12:43:21.219410 WR_PST = 0x0
2289 12:43:21.222138 DBI_WR = 0x0
2290 12:43:21.222559 DBI_RD = 0x0
2291 12:43:21.225561 OTF = 0x1
2292 12:43:21.228534 ===================================
2293 12:43:21.231946 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2294 12:43:21.235701 ==
2295 12:43:21.238939 Dram Type= 6, Freq= 0, CH_0, rank 0
2296 12:43:21.242187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2297 12:43:21.242737 ==
2298 12:43:21.245646 [Duty_Offset_Calibration]
2299 12:43:21.246133 B0:2 B1:1 CA:1
2300 12:43:21.246652
2301 12:43:21.248683 [DutyScan_Calibration_Flow] k_type=0
2302 12:43:21.258269
2303 12:43:21.258692 ==CLK 0==
2304 12:43:21.261432 Final CLK duty delay cell = 0
2305 12:43:21.265365 [0] MAX Duty = 5187%(X100), DQS PI = 24
2306 12:43:21.268545 [0] MIN Duty = 4875%(X100), DQS PI = 0
2307 12:43:21.269100 [0] AVG Duty = 5031%(X100)
2308 12:43:21.269479
2309 12:43:21.274902 CH0 CLK Duty spec in!! Max-Min= 312%
2310 12:43:21.278248 [DutyScan_Calibration_Flow] ====Done====
2311 12:43:21.278658
2312 12:43:21.281545 [DutyScan_Calibration_Flow] k_type=1
2313 12:43:21.296964
2314 12:43:21.297377 ==DQS 0 ==
2315 12:43:21.300270 Final DQS duty delay cell = -4
2316 12:43:21.303674 [-4] MAX Duty = 5156%(X100), DQS PI = 24
2317 12:43:21.306991 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2318 12:43:21.309730 [-4] AVG Duty = 4969%(X100)
2319 12:43:21.310142
2320 12:43:21.310465 ==DQS 1 ==
2321 12:43:21.313590 Final DQS duty delay cell = 0
2322 12:43:21.316959 [0] MAX Duty = 5156%(X100), DQS PI = 62
2323 12:43:21.320283 [0] MIN Duty = 5000%(X100), DQS PI = 36
2324 12:43:21.323577 [0] AVG Duty = 5078%(X100)
2325 12:43:21.323988
2326 12:43:21.326911 CH0 DQS 0 Duty spec in!! Max-Min= 374%
2327 12:43:21.327324
2328 12:43:21.330176 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2329 12:43:21.333570 [DutyScan_Calibration_Flow] ====Done====
2330 12:43:21.333981
2331 12:43:21.336706 [DutyScan_Calibration_Flow] k_type=3
2332 12:43:21.354117
2333 12:43:21.354549 ==DQM 0 ==
2334 12:43:21.357303 Final DQM duty delay cell = 0
2335 12:43:21.360328 [0] MAX Duty = 5156%(X100), DQS PI = 30
2336 12:43:21.363603 [0] MIN Duty = 4906%(X100), DQS PI = 52
2337 12:43:21.367321 [0] AVG Duty = 5031%(X100)
2338 12:43:21.367734
2339 12:43:21.368058 ==DQM 1 ==
2340 12:43:21.370545 Final DQM duty delay cell = 0
2341 12:43:21.373742 [0] MAX Duty = 5125%(X100), DQS PI = 60
2342 12:43:21.376742 [0] MIN Duty = 5031%(X100), DQS PI = 14
2343 12:43:21.379976 [0] AVG Duty = 5078%(X100)
2344 12:43:21.380509
2345 12:43:21.383432 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2346 12:43:21.383850
2347 12:43:21.386744 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2348 12:43:21.390799 [DutyScan_Calibration_Flow] ====Done====
2349 12:43:21.391218
2350 12:43:21.393956 [DutyScan_Calibration_Flow] k_type=2
2351 12:43:21.410219
2352 12:43:21.410695 ==DQ 0 ==
2353 12:43:21.413469 Final DQ duty delay cell = 0
2354 12:43:21.416880 [0] MAX Duty = 5031%(X100), DQS PI = 24
2355 12:43:21.420025 [0] MIN Duty = 4906%(X100), DQS PI = 0
2356 12:43:21.420442 [0] AVG Duty = 4968%(X100)
2357 12:43:21.420771
2358 12:43:21.423945 ==DQ 1 ==
2359 12:43:21.426626 Final DQ duty delay cell = 0
2360 12:43:21.430902 [0] MAX Duty = 5093%(X100), DQS PI = 24
2361 12:43:21.433365 [0] MIN Duty = 4969%(X100), DQS PI = 2
2362 12:43:21.433794 [0] AVG Duty = 5031%(X100)
2363 12:43:21.434157
2364 12:43:21.437250 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2365 12:43:21.437814
2366 12:43:21.440392 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2367 12:43:21.447028 [DutyScan_Calibration_Flow] ====Done====
2368 12:43:21.447442 ==
2369 12:43:21.450522 Dram Type= 6, Freq= 0, CH_1, rank 0
2370 12:43:21.453832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2371 12:43:21.454356 ==
2372 12:43:21.456877 [Duty_Offset_Calibration]
2373 12:43:21.457262 B0:1 B1:0 CA:1
2374 12:43:21.457686
2375 12:43:21.460766 [DutyScan_Calibration_Flow] k_type=0
2376 12:43:21.468922
2377 12:43:21.469369 ==CLK 0==
2378 12:43:21.472762 Final CLK duty delay cell = -4
2379 12:43:21.475936 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2380 12:43:21.479632 [-4] MIN Duty = 4907%(X100), DQS PI = 10
2381 12:43:21.482817 [-4] AVG Duty = 4969%(X100)
2382 12:43:21.483345
2383 12:43:21.485953 CH1 CLK Duty spec in!! Max-Min= 124%
2384 12:43:21.489696 [DutyScan_Calibration_Flow] ====Done====
2385 12:43:21.490192
2386 12:43:21.492477 [DutyScan_Calibration_Flow] k_type=1
2387 12:43:21.509025
2388 12:43:21.509571 ==DQS 0 ==
2389 12:43:21.512847 Final DQS duty delay cell = 0
2390 12:43:21.515635 [0] MAX Duty = 5094%(X100), DQS PI = 26
2391 12:43:21.519717 [0] MIN Duty = 4844%(X100), DQS PI = 0
2392 12:43:21.520233 [0] AVG Duty = 4969%(X100)
2393 12:43:21.522817
2394 12:43:21.523286 ==DQS 1 ==
2395 12:43:21.525919 Final DQS duty delay cell = 0
2396 12:43:21.529212 [0] MAX Duty = 5187%(X100), DQS PI = 20
2397 12:43:21.532499 [0] MIN Duty = 4969%(X100), DQS PI = 8
2398 12:43:21.532938 [0] AVG Duty = 5078%(X100)
2399 12:43:21.533270
2400 12:43:21.539473 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2401 12:43:21.539905
2402 12:43:21.542562 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2403 12:43:21.545677 [DutyScan_Calibration_Flow] ====Done====
2404 12:43:21.546210
2405 12:43:21.548980 [DutyScan_Calibration_Flow] k_type=3
2406 12:43:21.566273
2407 12:43:21.566763 ==DQM 0 ==
2408 12:43:21.568774 Final DQM duty delay cell = 0
2409 12:43:21.572577 [0] MAX Duty = 5156%(X100), DQS PI = 6
2410 12:43:21.575581 [0] MIN Duty = 5031%(X100), DQS PI = 0
2411 12:43:21.576006 [0] AVG Duty = 5093%(X100)
2412 12:43:21.576341
2413 12:43:21.579396 ==DQM 1 ==
2414 12:43:21.582621 Final DQM duty delay cell = 0
2415 12:43:21.585855 [0] MAX Duty = 5031%(X100), DQS PI = 16
2416 12:43:21.588929 [0] MIN Duty = 4907%(X100), DQS PI = 36
2417 12:43:21.589360 [0] AVG Duty = 4969%(X100)
2418 12:43:21.589697
2419 12:43:21.592293 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2420 12:43:21.595822
2421 12:43:21.599578 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2422 12:43:21.602773 [DutyScan_Calibration_Flow] ====Done====
2423 12:43:21.603212
2424 12:43:21.606159 [DutyScan_Calibration_Flow] k_type=2
2425 12:43:21.621634
2426 12:43:21.622067 ==DQ 0 ==
2427 12:43:21.624765 Final DQ duty delay cell = -4
2428 12:43:21.628091 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2429 12:43:21.631322 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2430 12:43:21.631740 [-4] AVG Duty = 5000%(X100)
2431 12:43:21.635159
2432 12:43:21.635790 ==DQ 1 ==
2433 12:43:21.638574 Final DQ duty delay cell = 0
2434 12:43:21.641842 [0] MAX Duty = 5125%(X100), DQS PI = 20
2435 12:43:21.645152 [0] MIN Duty = 4969%(X100), DQS PI = 12
2436 12:43:21.645764 [0] AVG Duty = 5047%(X100)
2437 12:43:21.646339
2438 12:43:21.648353 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2439 12:43:21.652114
2440 12:43:21.652545 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2441 12:43:21.658047 [DutyScan_Calibration_Flow] ====Done====
2442 12:43:21.661369 nWR fixed to 30
2443 12:43:21.661810 [ModeRegInit_LP4] CH0 RK0
2444 12:43:21.664892 [ModeRegInit_LP4] CH0 RK1
2445 12:43:21.668498 [ModeRegInit_LP4] CH1 RK0
2446 12:43:21.669005 [ModeRegInit_LP4] CH1 RK1
2447 12:43:21.671708 match AC timing 7
2448 12:43:21.674888 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2449 12:43:21.678659 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2450 12:43:21.685382 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2451 12:43:21.688718 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2452 12:43:21.695308 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2453 12:43:21.695733 ==
2454 12:43:21.698632 Dram Type= 6, Freq= 0, CH_0, rank 0
2455 12:43:21.701831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2456 12:43:21.702252 ==
2457 12:43:21.709059 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2458 12:43:21.711653 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2459 12:43:21.721656 [CA 0] Center 39 (8~70) winsize 63
2460 12:43:21.724620 [CA 1] Center 39 (8~70) winsize 63
2461 12:43:21.728263 [CA 2] Center 35 (5~66) winsize 62
2462 12:43:21.731560 [CA 3] Center 34 (4~65) winsize 62
2463 12:43:21.734695 [CA 4] Center 33 (3~64) winsize 62
2464 12:43:21.738063 [CA 5] Center 32 (3~62) winsize 60
2465 12:43:21.738536
2466 12:43:21.741264 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2467 12:43:21.741684
2468 12:43:21.744551 [CATrainingPosCal] consider 1 rank data
2469 12:43:21.747970 u2DelayCellTimex100 = 270/100 ps
2470 12:43:21.751390 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2471 12:43:21.754979 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2472 12:43:21.761576 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2473 12:43:21.764857 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2474 12:43:21.768279 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2475 12:43:21.771592 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2476 12:43:21.772202
2477 12:43:21.774902 CA PerBit enable=1, Macro0, CA PI delay=32
2478 12:43:21.775357
2479 12:43:21.778238 [CBTSetCACLKResult] CA Dly = 32
2480 12:43:21.778677 CS Dly: 6 (0~37)
2481 12:43:21.779111 ==
2482 12:43:21.781432 Dram Type= 6, Freq= 0, CH_0, rank 1
2483 12:43:21.788291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2484 12:43:21.788781 ==
2485 12:43:21.791387 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2486 12:43:21.797990 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2487 12:43:21.807413 [CA 0] Center 38 (8~69) winsize 62
2488 12:43:21.810676 [CA 1] Center 38 (8~69) winsize 62
2489 12:43:21.814106 [CA 2] Center 35 (4~66) winsize 63
2490 12:43:21.817605 [CA 3] Center 34 (4~65) winsize 62
2491 12:43:21.820440 [CA 4] Center 33 (3~64) winsize 62
2492 12:43:21.824322 [CA 5] Center 32 (3~62) winsize 60
2493 12:43:21.824915
2494 12:43:21.827411 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2495 12:43:21.827853
2496 12:43:21.830699 [CATrainingPosCal] consider 2 rank data
2497 12:43:21.833780 u2DelayCellTimex100 = 270/100 ps
2498 12:43:21.837683 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2499 12:43:21.841099 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2500 12:43:21.847697 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2501 12:43:21.850903 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2502 12:43:21.854408 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2503 12:43:21.857256 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2504 12:43:21.857679
2505 12:43:21.860603 CA PerBit enable=1, Macro0, CA PI delay=32
2506 12:43:21.861054
2507 12:43:21.864712 [CBTSetCACLKResult] CA Dly = 32
2508 12:43:21.865404 CS Dly: 6 (0~38)
2509 12:43:21.865820
2510 12:43:21.868010 ----->DramcWriteLeveling(PI) begin...
2511 12:43:21.868455 ==
2512 12:43:21.871329 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 12:43:21.878097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 12:43:21.878528 ==
2515 12:43:21.881272 Write leveling (Byte 0): 33 => 33
2516 12:43:21.884761 Write leveling (Byte 1): 29 => 29
2517 12:43:21.885214 DramcWriteLeveling(PI) end<-----
2518 12:43:21.885625
2519 12:43:21.887850 ==
2520 12:43:21.891541 Dram Type= 6, Freq= 0, CH_0, rank 0
2521 12:43:21.894659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2522 12:43:21.895213 ==
2523 12:43:21.897582 [Gating] SW mode calibration
2524 12:43:21.904704 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2525 12:43:21.907911 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2526 12:43:21.914460 0 15 0 | B1->B0 | 2323 3130 | 0 1 | (0 0) (1 1)
2527 12:43:21.917738 0 15 4 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
2528 12:43:21.920895 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 12:43:21.928044 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 12:43:21.931150 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 12:43:21.934453 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 12:43:21.941343 0 15 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
2533 12:43:21.944546 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
2534 12:43:21.947980 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
2535 12:43:21.954504 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 12:43:21.957902 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 12:43:21.961238 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 12:43:21.964352 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 12:43:21.971052 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 12:43:21.974330 1 0 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2541 12:43:21.977715 1 0 28 | B1->B0 | 2626 4545 | 0 1 | (0 0) (0 0)
2542 12:43:21.984355 1 1 0 | B1->B0 | 3232 4646 | 0 0 | (1 1) (0 0)
2543 12:43:21.987555 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 12:43:21.990886 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 12:43:21.998028 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 12:43:22.001080 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 12:43:22.004204 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 12:43:22.011120 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 12:43:22.014078 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2550 12:43:22.017931 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2551 12:43:22.024033 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 12:43:22.027415 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 12:43:22.031096 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 12:43:22.037707 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 12:43:22.041019 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 12:43:22.044422 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 12:43:22.051059 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 12:43:22.054473 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 12:43:22.057752 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 12:43:22.061015 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 12:43:22.067728 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 12:43:22.071537 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 12:43:22.074810 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 12:43:22.081738 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 12:43:22.084223 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2566 12:43:22.088071 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2567 12:43:22.091350 Total UI for P1: 0, mck2ui 16
2568 12:43:22.094610 best dqsien dly found for B0: ( 1, 3, 28)
2569 12:43:22.098064 Total UI for P1: 0, mck2ui 16
2570 12:43:22.101377 best dqsien dly found for B1: ( 1, 3, 30)
2571 12:43:22.104629 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2572 12:43:22.107881 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2573 12:43:22.108309
2574 12:43:22.114784 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2575 12:43:22.117907 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2576 12:43:22.118335 [Gating] SW calibration Done
2577 12:43:22.121024 ==
2578 12:43:22.124717 Dram Type= 6, Freq= 0, CH_0, rank 0
2579 12:43:22.127739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2580 12:43:22.128165 ==
2581 12:43:22.128503 RX Vref Scan: 0
2582 12:43:22.128860
2583 12:43:22.130974 RX Vref 0 -> 0, step: 1
2584 12:43:22.131399
2585 12:43:22.134634 RX Delay -40 -> 252, step: 8
2586 12:43:22.137794 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2587 12:43:22.141642 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2588 12:43:22.144892 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2589 12:43:22.151070 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2590 12:43:22.154975 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2591 12:43:22.158068 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2592 12:43:22.161269 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2593 12:43:22.164380 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2594 12:43:22.171237 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
2595 12:43:22.174631 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2596 12:43:22.177666 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2597 12:43:22.181081 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2598 12:43:22.184858 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2599 12:43:22.191482 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2600 12:43:22.194230 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2601 12:43:22.198083 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2602 12:43:22.198515 ==
2603 12:43:22.201312 Dram Type= 6, Freq= 0, CH_0, rank 0
2604 12:43:22.204766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2605 12:43:22.205389 ==
2606 12:43:22.208202 DQS Delay:
2607 12:43:22.208765 DQS0 = 0, DQS1 = 0
2608 12:43:22.211446 DQM Delay:
2609 12:43:22.212012 DQM0 = 121, DQM1 = 113
2610 12:43:22.212545 DQ Delay:
2611 12:43:22.214733 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2612 12:43:22.221129 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2613 12:43:22.224208 DQ8 =103, DQ9 =107, DQ10 =111, DQ11 =107
2614 12:43:22.227834 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2615 12:43:22.228265
2616 12:43:22.228595
2617 12:43:22.228945 ==
2618 12:43:22.231094 Dram Type= 6, Freq= 0, CH_0, rank 0
2619 12:43:22.234872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2620 12:43:22.235318 ==
2621 12:43:22.235756
2622 12:43:22.236083
2623 12:43:22.238084 TX Vref Scan disable
2624 12:43:22.241073 == TX Byte 0 ==
2625 12:43:22.244936 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2626 12:43:22.248175 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2627 12:43:22.251345 == TX Byte 1 ==
2628 12:43:22.254384 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2629 12:43:22.258160 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2630 12:43:22.258390 ==
2631 12:43:22.261266 Dram Type= 6, Freq= 0, CH_0, rank 0
2632 12:43:22.264207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2633 12:43:22.264393 ==
2634 12:43:22.277766 TX Vref=22, minBit 0, minWin=25, winSum=406
2635 12:43:22.280912 TX Vref=24, minBit 4, minWin=25, winSum=415
2636 12:43:22.284188 TX Vref=26, minBit 7, minWin=25, winSum=419
2637 12:43:22.287516 TX Vref=28, minBit 2, minWin=25, winSum=421
2638 12:43:22.290847 TX Vref=30, minBit 0, minWin=26, winSum=425
2639 12:43:22.294145 TX Vref=32, minBit 0, minWin=26, winSum=424
2640 12:43:22.300717 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 30
2641 12:43:22.300810
2642 12:43:22.304133 Final TX Range 1 Vref 30
2643 12:43:22.304217
2644 12:43:22.304283 ==
2645 12:43:22.307514 Dram Type= 6, Freq= 0, CH_0, rank 0
2646 12:43:22.310750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2647 12:43:22.310835 ==
2648 12:43:22.310901
2649 12:43:22.314180
2650 12:43:22.314263 TX Vref Scan disable
2651 12:43:22.317402 == TX Byte 0 ==
2652 12:43:22.321347 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2653 12:43:22.324460 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2654 12:43:22.327602 == TX Byte 1 ==
2655 12:43:22.330873 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2656 12:43:22.334457 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2657 12:43:22.334575
2658 12:43:22.337617 [DATLAT]
2659 12:43:22.337746 Freq=1200, CH0 RK0
2660 12:43:22.337847
2661 12:43:22.340797 DATLAT Default: 0xd
2662 12:43:22.340933 0, 0xFFFF, sum = 0
2663 12:43:22.344705 1, 0xFFFF, sum = 0
2664 12:43:22.344860 2, 0xFFFF, sum = 0
2665 12:43:22.347642 3, 0xFFFF, sum = 0
2666 12:43:22.347804 4, 0xFFFF, sum = 0
2667 12:43:22.350799 5, 0xFFFF, sum = 0
2668 12:43:22.351036 6, 0xFFFF, sum = 0
2669 12:43:22.354101 7, 0xFFFF, sum = 0
2670 12:43:22.354289 8, 0xFFFF, sum = 0
2671 12:43:22.357385 9, 0xFFFF, sum = 0
2672 12:43:22.361084 10, 0xFFFF, sum = 0
2673 12:43:22.361253 11, 0xFFFF, sum = 0
2674 12:43:22.364382 12, 0x0, sum = 1
2675 12:43:22.364548 13, 0x0, sum = 2
2676 12:43:22.364677 14, 0x0, sum = 3
2677 12:43:22.367674 15, 0x0, sum = 4
2678 12:43:22.367840 best_step = 13
2679 12:43:22.367966
2680 12:43:22.368083 ==
2681 12:43:22.371425 Dram Type= 6, Freq= 0, CH_0, rank 0
2682 12:43:22.377837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2683 12:43:22.378005 ==
2684 12:43:22.378132 RX Vref Scan: 1
2685 12:43:22.378252
2686 12:43:22.381295 Set Vref Range= 32 -> 127
2687 12:43:22.381456
2688 12:43:22.384363 RX Vref 32 -> 127, step: 1
2689 12:43:22.384524
2690 12:43:22.387748 RX Delay -5 -> 252, step: 4
2691 12:43:22.387909
2692 12:43:22.391549 Set Vref, RX VrefLevel [Byte0]: 32
2693 12:43:22.391718 [Byte1]: 32
2694 12:43:22.396205
2695 12:43:22.396367 Set Vref, RX VrefLevel [Byte0]: 33
2696 12:43:22.398969 [Byte1]: 33
2697 12:43:22.403524
2698 12:43:22.403684 Set Vref, RX VrefLevel [Byte0]: 34
2699 12:43:22.406952 [Byte1]: 34
2700 12:43:22.411502
2701 12:43:22.411661 Set Vref, RX VrefLevel [Byte0]: 35
2702 12:43:22.414893 [Byte1]: 35
2703 12:43:22.419428
2704 12:43:22.419590 Set Vref, RX VrefLevel [Byte0]: 36
2705 12:43:22.422649 [Byte1]: 36
2706 12:43:22.427237
2707 12:43:22.427475 Set Vref, RX VrefLevel [Byte0]: 37
2708 12:43:22.430420 [Byte1]: 37
2709 12:43:22.435581
2710 12:43:22.435741 Set Vref, RX VrefLevel [Byte0]: 38
2711 12:43:22.438882 [Byte1]: 38
2712 12:43:22.442981
2713 12:43:22.443143 Set Vref, RX VrefLevel [Byte0]: 39
2714 12:43:22.446116 [Byte1]: 39
2715 12:43:22.451220
2716 12:43:22.451381 Set Vref, RX VrefLevel [Byte0]: 40
2717 12:43:22.454259 [Byte1]: 40
2718 12:43:22.458752
2719 12:43:22.458914 Set Vref, RX VrefLevel [Byte0]: 41
2720 12:43:22.462064 [Byte1]: 41
2721 12:43:22.466439
2722 12:43:22.466612 Set Vref, RX VrefLevel [Byte0]: 42
2723 12:43:22.469841 [Byte1]: 42
2724 12:43:22.474463
2725 12:43:22.474804 Set Vref, RX VrefLevel [Byte0]: 43
2726 12:43:22.477600 [Byte1]: 43
2727 12:43:22.482649
2728 12:43:22.483067 Set Vref, RX VrefLevel [Byte0]: 44
2729 12:43:22.485953 [Byte1]: 44
2730 12:43:22.490773
2731 12:43:22.491194 Set Vref, RX VrefLevel [Byte0]: 45
2732 12:43:22.493873 [Byte1]: 45
2733 12:43:22.498383
2734 12:43:22.498804 Set Vref, RX VrefLevel [Byte0]: 46
2735 12:43:22.501755 [Byte1]: 46
2736 12:43:22.505749
2737 12:43:22.506188 Set Vref, RX VrefLevel [Byte0]: 47
2738 12:43:22.509210 [Byte1]: 47
2739 12:43:22.513709
2740 12:43:22.514127 Set Vref, RX VrefLevel [Byte0]: 48
2741 12:43:22.517124 [Byte1]: 48
2742 12:43:22.521796
2743 12:43:22.522214 Set Vref, RX VrefLevel [Byte0]: 49
2744 12:43:22.525208 [Byte1]: 49
2745 12:43:22.529711
2746 12:43:22.530129 Set Vref, RX VrefLevel [Byte0]: 50
2747 12:43:22.532924 [Byte1]: 50
2748 12:43:22.537588
2749 12:43:22.538007 Set Vref, RX VrefLevel [Byte0]: 51
2750 12:43:22.540837 [Byte1]: 51
2751 12:43:22.545130
2752 12:43:22.545547 Set Vref, RX VrefLevel [Byte0]: 52
2753 12:43:22.548403 [Byte1]: 52
2754 12:43:22.553296
2755 12:43:22.553812 Set Vref, RX VrefLevel [Byte0]: 53
2756 12:43:22.556533 [Byte1]: 53
2757 12:43:22.561007
2758 12:43:22.561411 Set Vref, RX VrefLevel [Byte0]: 54
2759 12:43:22.564296 [Byte1]: 54
2760 12:43:22.568674
2761 12:43:22.569181 Set Vref, RX VrefLevel [Byte0]: 55
2762 12:43:22.571839 [Byte1]: 55
2763 12:43:22.576471
2764 12:43:22.576925 Set Vref, RX VrefLevel [Byte0]: 56
2765 12:43:22.580100 [Byte1]: 56
2766 12:43:22.584308
2767 12:43:22.584915 Set Vref, RX VrefLevel [Byte0]: 57
2768 12:43:22.587541 [Byte1]: 57
2769 12:43:22.592635
2770 12:43:22.593095 Set Vref, RX VrefLevel [Byte0]: 58
2771 12:43:22.595806 [Byte1]: 58
2772 12:43:22.600478
2773 12:43:22.600937 Set Vref, RX VrefLevel [Byte0]: 59
2774 12:43:22.603677 [Byte1]: 59
2775 12:43:22.608196
2776 12:43:22.608698 Set Vref, RX VrefLevel [Byte0]: 60
2777 12:43:22.611497 [Byte1]: 60
2778 12:43:22.616208
2779 12:43:22.616625 Set Vref, RX VrefLevel [Byte0]: 61
2780 12:43:22.619574 [Byte1]: 61
2781 12:43:22.623632
2782 12:43:22.624084 Set Vref, RX VrefLevel [Byte0]: 62
2783 12:43:22.627427 [Byte1]: 62
2784 12:43:22.631429
2785 12:43:22.631854 Set Vref, RX VrefLevel [Byte0]: 63
2786 12:43:22.635263 [Byte1]: 63
2787 12:43:22.639980
2788 12:43:22.640401 Set Vref, RX VrefLevel [Byte0]: 64
2789 12:43:22.643049 [Byte1]: 64
2790 12:43:22.647701
2791 12:43:22.648131 Set Vref, RX VrefLevel [Byte0]: 65
2792 12:43:22.650927 [Byte1]: 65
2793 12:43:22.655012
2794 12:43:22.655691 Set Vref, RX VrefLevel [Byte0]: 66
2795 12:43:22.658778 [Byte1]: 66
2796 12:43:22.663213
2797 12:43:22.663651 Set Vref, RX VrefLevel [Byte0]: 67
2798 12:43:22.666455 [Byte1]: 67
2799 12:43:22.670632
2800 12:43:22.671148 Set Vref, RX VrefLevel [Byte0]: 68
2801 12:43:22.674577 [Byte1]: 68
2802 12:43:22.678931
2803 12:43:22.679443 Set Vref, RX VrefLevel [Byte0]: 69
2804 12:43:22.682300 [Byte1]: 69
2805 12:43:22.686883
2806 12:43:22.687443 Set Vref, RX VrefLevel [Byte0]: 70
2807 12:43:22.690150 [Byte1]: 70
2808 12:43:22.694625
2809 12:43:22.695061 Set Vref, RX VrefLevel [Byte0]: 71
2810 12:43:22.698119 [Byte1]: 71
2811 12:43:22.702430
2812 12:43:22.702865 Set Vref, RX VrefLevel [Byte0]: 72
2813 12:43:22.705733 [Byte1]: 72
2814 12:43:22.709822
2815 12:43:22.710250 Final RX Vref Byte 0 = 55 to rank0
2816 12:43:22.713234 Final RX Vref Byte 1 = 55 to rank0
2817 12:43:22.717260 Final RX Vref Byte 0 = 55 to rank1
2818 12:43:22.720453 Final RX Vref Byte 1 = 55 to rank1==
2819 12:43:22.723901 Dram Type= 6, Freq= 0, CH_0, rank 0
2820 12:43:22.727297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2821 12:43:22.730704 ==
2822 12:43:22.731119 DQS Delay:
2823 12:43:22.731447 DQS0 = 0, DQS1 = 0
2824 12:43:22.733886 DQM Delay:
2825 12:43:22.734303 DQM0 = 120, DQM1 = 113
2826 12:43:22.737429 DQ Delay:
2827 12:43:22.740462 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2828 12:43:22.743858 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2829 12:43:22.747164 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
2830 12:43:22.750403 DQ12 =118, DQ13 =118, DQ14 =126, DQ15 =122
2831 12:43:22.750890
2832 12:43:22.751242
2833 12:43:22.757403 [DQSOSCAuto] RK0, (LSB)MR18= 0x150f, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps
2834 12:43:22.760537 CH0 RK0: MR19=404, MR18=150F
2835 12:43:22.767518 CH0_RK0: MR19=0x404, MR18=0x150F, DQSOSC=401, MR23=63, INC=40, DEC=27
2836 12:43:22.767943
2837 12:43:22.770677 ----->DramcWriteLeveling(PI) begin...
2838 12:43:22.771118 ==
2839 12:43:22.773728 Dram Type= 6, Freq= 0, CH_0, rank 1
2840 12:43:22.777029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2841 12:43:22.777487 ==
2842 12:43:22.780742 Write leveling (Byte 0): 33 => 33
2843 12:43:22.784062 Write leveling (Byte 1): 28 => 28
2844 12:43:22.787247 DramcWriteLeveling(PI) end<-----
2845 12:43:22.787674
2846 12:43:22.788010 ==
2847 12:43:22.790329 Dram Type= 6, Freq= 0, CH_0, rank 1
2848 12:43:22.793544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2849 12:43:22.797478 ==
2850 12:43:22.797902 [Gating] SW mode calibration
2851 12:43:22.807479 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2852 12:43:22.810755 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2853 12:43:22.814156 0 15 0 | B1->B0 | 3434 3131 | 0 1 | (0 0) (1 1)
2854 12:43:22.820539 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 12:43:22.823919 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 12:43:22.827148 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 12:43:22.833908 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 12:43:22.837256 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 12:43:22.840553 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 12:43:22.847284 0 15 28 | B1->B0 | 3232 3232 | 1 1 | (1 0) (1 0)
2861 12:43:22.850497 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
2862 12:43:22.853912 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 12:43:22.857768 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 12:43:22.864148 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 12:43:22.867169 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 12:43:22.870747 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 12:43:22.877736 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2868 12:43:22.880797 1 0 28 | B1->B0 | 3f3f 3f3f | 0 1 | (0 0) (0 0)
2869 12:43:22.883937 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
2870 12:43:22.891017 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 12:43:22.894162 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 12:43:22.897329 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 12:43:22.904529 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 12:43:22.907875 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 12:43:22.911021 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 12:43:22.917855 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2877 12:43:22.920977 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 12:43:22.924198 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 12:43:22.930890 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 12:43:22.934214 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 12:43:22.937446 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 12:43:22.940968 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 12:43:22.947444 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 12:43:22.951508 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 12:43:22.954056 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 12:43:22.960741 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 12:43:22.964167 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 12:43:22.967823 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 12:43:22.974079 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 12:43:22.977765 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 12:43:22.981132 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 12:43:22.987963 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 12:43:22.991086 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2894 12:43:22.994462 Total UI for P1: 0, mck2ui 16
2895 12:43:22.997611 best dqsien dly found for B1: ( 1, 3, 30)
2896 12:43:23.000661 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2897 12:43:23.004645 Total UI for P1: 0, mck2ui 16
2898 12:43:23.007796 best dqsien dly found for B0: ( 1, 4, 0)
2899 12:43:23.011070 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2900 12:43:23.014430 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2901 12:43:23.014851
2902 12:43:23.017559 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2903 12:43:23.024644 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2904 12:43:23.025115 [Gating] SW calibration Done
2905 12:43:23.025457 ==
2906 12:43:23.028087 Dram Type= 6, Freq= 0, CH_0, rank 1
2907 12:43:23.034290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2908 12:43:23.034731 ==
2909 12:43:23.035073 RX Vref Scan: 0
2910 12:43:23.035389
2911 12:43:23.037748 RX Vref 0 -> 0, step: 1
2912 12:43:23.038171
2913 12:43:23.041187 RX Delay -40 -> 252, step: 8
2914 12:43:23.044491 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2915 12:43:23.047839 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2916 12:43:23.051215 iDelay=200, Bit 2, Center 123 (56 ~ 191) 136
2917 12:43:23.057626 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2918 12:43:23.060980 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2919 12:43:23.064317 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2920 12:43:23.067774 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2921 12:43:23.071067 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2922 12:43:23.074183 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2923 12:43:23.080957 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2924 12:43:23.084193 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2925 12:43:23.087955 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2926 12:43:23.090957 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2927 12:43:23.094581 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2928 12:43:23.100882 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2929 12:43:23.104885 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2930 12:43:23.105376 ==
2931 12:43:23.108042 Dram Type= 6, Freq= 0, CH_0, rank 1
2932 12:43:23.111030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2933 12:43:23.111544 ==
2934 12:43:23.114764 DQS Delay:
2935 12:43:23.115260 DQS0 = 0, DQS1 = 0
2936 12:43:23.115599 DQM Delay:
2937 12:43:23.118130 DQM0 = 122, DQM1 = 113
2938 12:43:23.118631 DQ Delay:
2939 12:43:23.121428 DQ0 =119, DQ1 =123, DQ2 =123, DQ3 =119
2940 12:43:23.124613 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2941 12:43:23.127908 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
2942 12:43:23.134668 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
2943 12:43:23.135104
2944 12:43:23.135434
2945 12:43:23.135939 ==
2946 12:43:23.137686 Dram Type= 6, Freq= 0, CH_0, rank 1
2947 12:43:23.141461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2948 12:43:23.142108 ==
2949 12:43:23.142528
2950 12:43:23.142884
2951 12:43:23.144615 TX Vref Scan disable
2952 12:43:23.145189 == TX Byte 0 ==
2953 12:43:23.151449 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2954 12:43:23.154814 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2955 12:43:23.155286 == TX Byte 1 ==
2956 12:43:23.161281 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2957 12:43:23.164600 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2958 12:43:23.165056 ==
2959 12:43:23.168039 Dram Type= 6, Freq= 0, CH_0, rank 1
2960 12:43:23.171191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2961 12:43:23.171682 ==
2962 12:43:23.184217 TX Vref=22, minBit 1, minWin=25, winSum=410
2963 12:43:23.187152 TX Vref=24, minBit 1, minWin=25, winSum=417
2964 12:43:23.190490 TX Vref=26, minBit 13, minWin=25, winSum=421
2965 12:43:23.194280 TX Vref=28, minBit 10, minWin=25, winSum=420
2966 12:43:23.197438 TX Vref=30, minBit 5, minWin=25, winSum=426
2967 12:43:23.203889 TX Vref=32, minBit 12, minWin=25, winSum=419
2968 12:43:23.207411 [TxChooseVref] Worse bit 5, Min win 25, Win sum 426, Final Vref 30
2969 12:43:23.207874
2970 12:43:23.210829 Final TX Range 1 Vref 30
2971 12:43:23.211268
2972 12:43:23.211601 ==
2973 12:43:23.213818 Dram Type= 6, Freq= 0, CH_0, rank 1
2974 12:43:23.217613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2975 12:43:23.220776 ==
2976 12:43:23.221256
2977 12:43:23.221593
2978 12:43:23.221906 TX Vref Scan disable
2979 12:43:23.223831 == TX Byte 0 ==
2980 12:43:23.227876 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2981 12:43:23.231185 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2982 12:43:23.234367 == TX Byte 1 ==
2983 12:43:23.237581 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2984 12:43:23.240791 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2985 12:43:23.244206
2986 12:43:23.244627 [DATLAT]
2987 12:43:23.245016 Freq=1200, CH0 RK1
2988 12:43:23.245337
2989 12:43:23.247324 DATLAT Default: 0xd
2990 12:43:23.247742 0, 0xFFFF, sum = 0
2991 12:43:23.251031 1, 0xFFFF, sum = 0
2992 12:43:23.251457 2, 0xFFFF, sum = 0
2993 12:43:23.254428 3, 0xFFFF, sum = 0
2994 12:43:23.254874 4, 0xFFFF, sum = 0
2995 12:43:23.257768 5, 0xFFFF, sum = 0
2996 12:43:23.261159 6, 0xFFFF, sum = 0
2997 12:43:23.261625 7, 0xFFFF, sum = 0
2998 12:43:23.264365 8, 0xFFFF, sum = 0
2999 12:43:23.264980 9, 0xFFFF, sum = 0
3000 12:43:23.267600 10, 0xFFFF, sum = 0
3001 12:43:23.268040 11, 0xFFFF, sum = 0
3002 12:43:23.270946 12, 0x0, sum = 1
3003 12:43:23.271387 13, 0x0, sum = 2
3004 12:43:23.274275 14, 0x0, sum = 3
3005 12:43:23.274704 15, 0x0, sum = 4
3006 12:43:23.275067 best_step = 13
3007 12:43:23.275379
3008 12:43:23.277867 ==
3009 12:43:23.280983 Dram Type= 6, Freq= 0, CH_0, rank 1
3010 12:43:23.284301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3011 12:43:23.284737 ==
3012 12:43:23.285190 RX Vref Scan: 0
3013 12:43:23.285632
3014 12:43:23.287429 RX Vref 0 -> 0, step: 1
3015 12:43:23.287928
3016 12:43:23.291015 RX Delay -13 -> 252, step: 4
3017 12:43:23.294285 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3018 12:43:23.301091 iDelay=195, Bit 1, Center 122 (59 ~ 186) 128
3019 12:43:23.303918 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3020 12:43:23.307654 iDelay=195, Bit 3, Center 120 (55 ~ 186) 132
3021 12:43:23.310896 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3022 12:43:23.314012 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3023 12:43:23.317314 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3024 12:43:23.324459 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3025 12:43:23.327566 iDelay=195, Bit 8, Center 104 (39 ~ 170) 132
3026 12:43:23.330734 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3027 12:43:23.333915 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3028 12:43:23.337851 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3029 12:43:23.344404 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3030 12:43:23.347812 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3031 12:43:23.350793 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3032 12:43:23.354164 iDelay=195, Bit 15, Center 120 (59 ~ 182) 124
3033 12:43:23.354585 ==
3034 12:43:23.357313 Dram Type= 6, Freq= 0, CH_0, rank 1
3035 12:43:23.364646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3036 12:43:23.365253 ==
3037 12:43:23.365665 DQS Delay:
3038 12:43:23.367844 DQS0 = 0, DQS1 = 0
3039 12:43:23.368282 DQM Delay:
3040 12:43:23.368752 DQM0 = 121, DQM1 = 112
3041 12:43:23.371004 DQ Delay:
3042 12:43:23.374507 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =120
3043 12:43:23.377930 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3044 12:43:23.381173 DQ8 =104, DQ9 =100, DQ10 =112, DQ11 =104
3045 12:43:23.384630 DQ12 =118, DQ13 =118, DQ14 =122, DQ15 =120
3046 12:43:23.385182
3047 12:43:23.385537
3048 12:43:23.391174 [DQSOSCAuto] RK1, (LSB)MR18= 0xef0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 404 ps
3049 12:43:23.394238 CH0 RK1: MR19=403, MR18=EF0
3050 12:43:23.401205 CH0_RK1: MR19=0x403, MR18=0xEF0, DQSOSC=404, MR23=63, INC=40, DEC=26
3051 12:43:23.404375 [RxdqsGatingPostProcess] freq 1200
3052 12:43:23.411142 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3053 12:43:23.414983 best DQS0 dly(2T, 0.5T) = (0, 11)
3054 12:43:23.415410 best DQS1 dly(2T, 0.5T) = (0, 11)
3055 12:43:23.418042 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3056 12:43:23.421153 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3057 12:43:23.424377 best DQS0 dly(2T, 0.5T) = (0, 12)
3058 12:43:23.427590 best DQS1 dly(2T, 0.5T) = (0, 11)
3059 12:43:23.431442 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3060 12:43:23.434687 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3061 12:43:23.437804 Pre-setting of DQS Precalculation
3062 12:43:23.444522 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3063 12:43:23.444997 ==
3064 12:43:23.447827 Dram Type= 6, Freq= 0, CH_1, rank 0
3065 12:43:23.451274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3066 12:43:23.451696 ==
3067 12:43:23.457818 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3068 12:43:23.460925 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3069 12:43:23.470781 [CA 0] Center 37 (7~68) winsize 62
3070 12:43:23.474091 [CA 1] Center 37 (7~68) winsize 62
3071 12:43:23.477314 [CA 2] Center 35 (5~65) winsize 61
3072 12:43:23.480668 [CA 3] Center 34 (4~65) winsize 62
3073 12:43:23.484149 [CA 4] Center 34 (5~64) winsize 60
3074 12:43:23.487390 [CA 5] Center 33 (3~63) winsize 61
3075 12:43:23.487863
3076 12:43:23.490881 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3077 12:43:23.491297
3078 12:43:23.494147 [CATrainingPosCal] consider 1 rank data
3079 12:43:23.497336 u2DelayCellTimex100 = 270/100 ps
3080 12:43:23.500580 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3081 12:43:23.504238 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3082 12:43:23.507441 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3083 12:43:23.514189 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3084 12:43:23.517533 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3085 12:43:23.520700 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3086 12:43:23.521192
3087 12:43:23.523778 CA PerBit enable=1, Macro0, CA PI delay=33
3088 12:43:23.524194
3089 12:43:23.527367 [CBTSetCACLKResult] CA Dly = 33
3090 12:43:23.527783 CS Dly: 7 (0~38)
3091 12:43:23.528108 ==
3092 12:43:23.530668 Dram Type= 6, Freq= 0, CH_1, rank 1
3093 12:43:23.537699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3094 12:43:23.538164 ==
3095 12:43:23.540902 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3096 12:43:23.547149 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3097 12:43:23.555932 [CA 0] Center 37 (7~68) winsize 62
3098 12:43:23.559278 [CA 1] Center 37 (7~68) winsize 62
3099 12:43:23.562700 [CA 2] Center 35 (5~65) winsize 61
3100 12:43:23.566016 [CA 3] Center 34 (4~65) winsize 62
3101 12:43:23.569603 [CA 4] Center 34 (4~65) winsize 62
3102 12:43:23.572988 [CA 5] Center 33 (4~63) winsize 60
3103 12:43:23.573408
3104 12:43:23.576352 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3105 12:43:23.576776
3106 12:43:23.579547 [CATrainingPosCal] consider 2 rank data
3107 12:43:23.582960 u2DelayCellTimex100 = 270/100 ps
3108 12:43:23.586323 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3109 12:43:23.589573 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3110 12:43:23.592950 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3111 12:43:23.599433 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3112 12:43:23.603455 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3113 12:43:23.606656 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3114 12:43:23.607090
3115 12:43:23.609679 CA PerBit enable=1, Macro0, CA PI delay=33
3116 12:43:23.610099
3117 12:43:23.612783 [CBTSetCACLKResult] CA Dly = 33
3118 12:43:23.613370 CS Dly: 8 (0~41)
3119 12:43:23.613837
3120 12:43:23.616928 ----->DramcWriteLeveling(PI) begin...
3121 12:43:23.617386 ==
3122 12:43:23.619642 Dram Type= 6, Freq= 0, CH_1, rank 0
3123 12:43:23.626566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3124 12:43:23.626986 ==
3125 12:43:23.629649 Write leveling (Byte 0): 25 => 25
3126 12:43:23.633506 Write leveling (Byte 1): 26 => 26
3127 12:43:23.633925 DramcWriteLeveling(PI) end<-----
3128 12:43:23.634252
3129 12:43:23.636532 ==
3130 12:43:23.639875 Dram Type= 6, Freq= 0, CH_1, rank 0
3131 12:43:23.643101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3132 12:43:23.643600 ==
3133 12:43:23.646227 [Gating] SW mode calibration
3134 12:43:23.652886 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3135 12:43:23.656598 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3136 12:43:23.663068 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3137 12:43:23.666417 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 12:43:23.669795 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 12:43:23.676592 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 12:43:23.679909 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 12:43:23.683081 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 12:43:23.689750 0 15 24 | B1->B0 | 3232 2f2f | 0 0 | (0 0) (0 1)
3143 12:43:23.693291 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3144 12:43:23.696537 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 12:43:23.699961 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 12:43:23.706498 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 12:43:23.709959 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 12:43:23.713288 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 12:43:23.719922 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 12:43:23.723625 1 0 24 | B1->B0 | 3030 3d3d | 0 0 | (1 1) (0 0)
3151 12:43:23.726615 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 12:43:23.733655 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 12:43:23.736789 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 12:43:23.740058 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 12:43:23.747025 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 12:43:23.750172 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 12:43:23.754004 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 12:43:23.757259 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3159 12:43:23.763457 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3160 12:43:23.767296 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 12:43:23.770359 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 12:43:23.776931 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 12:43:23.780209 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 12:43:23.783918 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 12:43:23.790500 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 12:43:23.793876 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 12:43:23.797115 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 12:43:23.803782 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 12:43:23.807203 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 12:43:23.810601 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 12:43:23.817168 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 12:43:23.820342 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 12:43:23.823437 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 12:43:23.830327 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3175 12:43:23.833528 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3176 12:43:23.837252 Total UI for P1: 0, mck2ui 16
3177 12:43:23.840297 best dqsien dly found for B0: ( 1, 3, 24)
3178 12:43:23.843474 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3179 12:43:23.846870 Total UI for P1: 0, mck2ui 16
3180 12:43:23.850419 best dqsien dly found for B1: ( 1, 3, 26)
3181 12:43:23.853908 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3182 12:43:23.857134 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3183 12:43:23.857561
3184 12:43:23.860254 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3185 12:43:23.867341 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3186 12:43:23.867778 [Gating] SW calibration Done
3187 12:43:23.868115 ==
3188 12:43:23.870625 Dram Type= 6, Freq= 0, CH_1, rank 0
3189 12:43:23.877248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3190 12:43:23.877683 ==
3191 12:43:23.878013 RX Vref Scan: 0
3192 12:43:23.878323
3193 12:43:23.880605 RX Vref 0 -> 0, step: 1
3194 12:43:23.881104
3195 12:43:23.884054 RX Delay -40 -> 252, step: 8
3196 12:43:23.887105 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3197 12:43:23.890285 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3198 12:43:23.893998 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3199 12:43:23.897410 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3200 12:43:23.904125 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3201 12:43:23.907310 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3202 12:43:23.910706 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3203 12:43:23.913913 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3204 12:43:23.917242 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3205 12:43:23.923788 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3206 12:43:23.927035 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3207 12:43:23.930765 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3208 12:43:23.933687 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3209 12:43:23.937380 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3210 12:43:23.943888 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3211 12:43:23.947630 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3212 12:43:23.948059 ==
3213 12:43:23.950792 Dram Type= 6, Freq= 0, CH_1, rank 0
3214 12:43:23.954013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3215 12:43:23.954455 ==
3216 12:43:23.957718 DQS Delay:
3217 12:43:23.958274 DQS0 = 0, DQS1 = 0
3218 12:43:23.958752 DQM Delay:
3219 12:43:23.960908 DQM0 = 119, DQM1 = 116
3220 12:43:23.961345 DQ Delay:
3221 12:43:23.964362 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3222 12:43:23.967397 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3223 12:43:23.970798 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3224 12:43:23.974052 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3225 12:43:23.977856
3226 12:43:23.978277
3227 12:43:23.978608 ==
3228 12:43:23.980917 Dram Type= 6, Freq= 0, CH_1, rank 0
3229 12:43:23.984266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3230 12:43:23.984692 ==
3231 12:43:23.985082
3232 12:43:23.985398
3233 12:43:23.987396 TX Vref Scan disable
3234 12:43:23.987845 == TX Byte 0 ==
3235 12:43:23.994456 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3236 12:43:23.997627 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3237 12:43:23.998087 == TX Byte 1 ==
3238 12:43:24.004629 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3239 12:43:24.007854 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3240 12:43:24.008283 ==
3241 12:43:24.011212 Dram Type= 6, Freq= 0, CH_1, rank 0
3242 12:43:24.014389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3243 12:43:24.014866 ==
3244 12:43:24.026498 TX Vref=22, minBit 10, minWin=24, winSum=412
3245 12:43:24.029946 TX Vref=24, minBit 9, minWin=25, winSum=415
3246 12:43:24.033163 TX Vref=26, minBit 1, minWin=26, winSum=427
3247 12:43:24.036327 TX Vref=28, minBit 2, minWin=26, winSum=427
3248 12:43:24.039558 TX Vref=30, minBit 2, minWin=26, winSum=431
3249 12:43:24.046259 TX Vref=32, minBit 10, minWin=25, winSum=428
3250 12:43:24.049631 [TxChooseVref] Worse bit 2, Min win 26, Win sum 431, Final Vref 30
3251 12:43:24.050147
3252 12:43:24.053269 Final TX Range 1 Vref 30
3253 12:43:24.053705
3254 12:43:24.054217 ==
3255 12:43:24.056130 Dram Type= 6, Freq= 0, CH_1, rank 0
3256 12:43:24.059410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3257 12:43:24.059867 ==
3258 12:43:24.063399
3259 12:43:24.063846
3260 12:43:24.064184 TX Vref Scan disable
3261 12:43:24.066399 == TX Byte 0 ==
3262 12:43:24.070119 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3263 12:43:24.072895 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3264 12:43:24.076047 == TX Byte 1 ==
3265 12:43:24.080077 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3266 12:43:24.083259 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3267 12:43:24.083719
3268 12:43:24.086416 [DATLAT]
3269 12:43:24.086840 Freq=1200, CH1 RK0
3270 12:43:24.087177
3271 12:43:24.089526 DATLAT Default: 0xd
3272 12:43:24.089950 0, 0xFFFF, sum = 0
3273 12:43:24.092872 1, 0xFFFF, sum = 0
3274 12:43:24.093317 2, 0xFFFF, sum = 0
3275 12:43:24.096333 3, 0xFFFF, sum = 0
3276 12:43:24.096947 4, 0xFFFF, sum = 0
3277 12:43:24.099580 5, 0xFFFF, sum = 0
3278 12:43:24.100053 6, 0xFFFF, sum = 0
3279 12:43:24.102913 7, 0xFFFF, sum = 0
3280 12:43:24.105997 8, 0xFFFF, sum = 0
3281 12:43:24.106430 9, 0xFFFF, sum = 0
3282 12:43:24.109761 10, 0xFFFF, sum = 0
3283 12:43:24.110192 11, 0xFFFF, sum = 0
3284 12:43:24.113050 12, 0x0, sum = 1
3285 12:43:24.113483 13, 0x0, sum = 2
3286 12:43:24.116332 14, 0x0, sum = 3
3287 12:43:24.116761 15, 0x0, sum = 4
3288 12:43:24.117213 best_step = 13
3289 12:43:24.117538
3290 12:43:24.119711 ==
3291 12:43:24.122964 Dram Type= 6, Freq= 0, CH_1, rank 0
3292 12:43:24.126331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3293 12:43:24.126747 ==
3294 12:43:24.127072 RX Vref Scan: 1
3295 12:43:24.127380
3296 12:43:24.129599 Set Vref Range= 32 -> 127
3297 12:43:24.130046
3298 12:43:24.132999 RX Vref 32 -> 127, step: 1
3299 12:43:24.133414
3300 12:43:24.136429 RX Delay -5 -> 252, step: 4
3301 12:43:24.136868
3302 12:43:24.139681 Set Vref, RX VrefLevel [Byte0]: 32
3303 12:43:24.143042 [Byte1]: 32
3304 12:43:24.143478
3305 12:43:24.146056 Set Vref, RX VrefLevel [Byte0]: 33
3306 12:43:24.149667 [Byte1]: 33
3307 12:43:24.150133
3308 12:43:24.153111 Set Vref, RX VrefLevel [Byte0]: 34
3309 12:43:24.156260 [Byte1]: 34
3310 12:43:24.160138
3311 12:43:24.160722 Set Vref, RX VrefLevel [Byte0]: 35
3312 12:43:24.163348 [Byte1]: 35
3313 12:43:24.168317
3314 12:43:24.168745 Set Vref, RX VrefLevel [Byte0]: 36
3315 12:43:24.171448 [Byte1]: 36
3316 12:43:24.175823
3317 12:43:24.176365 Set Vref, RX VrefLevel [Byte0]: 37
3318 12:43:24.179046 [Byte1]: 37
3319 12:43:24.183500
3320 12:43:24.184026 Set Vref, RX VrefLevel [Byte0]: 38
3321 12:43:24.186881 [Byte1]: 38
3322 12:43:24.191982
3323 12:43:24.192404 Set Vref, RX VrefLevel [Byte0]: 39
3324 12:43:24.195099 [Byte1]: 39
3325 12:43:24.199667
3326 12:43:24.200115 Set Vref, RX VrefLevel [Byte0]: 40
3327 12:43:24.202994 [Byte1]: 40
3328 12:43:24.207685
3329 12:43:24.208105 Set Vref, RX VrefLevel [Byte0]: 41
3330 12:43:24.210864 [Byte1]: 41
3331 12:43:24.215469
3332 12:43:24.215885 Set Vref, RX VrefLevel [Byte0]: 42
3333 12:43:24.218391 [Byte1]: 42
3334 12:43:24.222863
3335 12:43:24.223283 Set Vref, RX VrefLevel [Byte0]: 43
3336 12:43:24.226262 [Byte1]: 43
3337 12:43:24.231016
3338 12:43:24.231445 Set Vref, RX VrefLevel [Byte0]: 44
3339 12:43:24.234245 [Byte1]: 44
3340 12:43:24.238924
3341 12:43:24.239367 Set Vref, RX VrefLevel [Byte0]: 45
3342 12:43:24.242234 [Byte1]: 45
3343 12:43:24.246237
3344 12:43:24.246663 Set Vref, RX VrefLevel [Byte0]: 46
3345 12:43:24.249587 [Byte1]: 46
3346 12:43:24.254663
3347 12:43:24.255115 Set Vref, RX VrefLevel [Byte0]: 47
3348 12:43:24.258101 [Byte1]: 47
3349 12:43:24.262421
3350 12:43:24.262955 Set Vref, RX VrefLevel [Byte0]: 48
3351 12:43:24.265496 [Byte1]: 48
3352 12:43:24.269933
3353 12:43:24.270387 Set Vref, RX VrefLevel [Byte0]: 49
3354 12:43:24.273741 [Byte1]: 49
3355 12:43:24.278124
3356 12:43:24.278701 Set Vref, RX VrefLevel [Byte0]: 50
3357 12:43:24.281209 [Byte1]: 50
3358 12:43:24.285795
3359 12:43:24.286378 Set Vref, RX VrefLevel [Byte0]: 51
3360 12:43:24.288918 [Byte1]: 51
3361 12:43:24.293998
3362 12:43:24.294530 Set Vref, RX VrefLevel [Byte0]: 52
3363 12:43:24.297180 [Byte1]: 52
3364 12:43:24.301342
3365 12:43:24.301917 Set Vref, RX VrefLevel [Byte0]: 53
3366 12:43:24.304645 [Byte1]: 53
3367 12:43:24.309451
3368 12:43:24.309872 Set Vref, RX VrefLevel [Byte0]: 54
3369 12:43:24.312958 [Byte1]: 54
3370 12:43:24.317647
3371 12:43:24.318158 Set Vref, RX VrefLevel [Byte0]: 55
3372 12:43:24.320778 [Byte1]: 55
3373 12:43:24.325254
3374 12:43:24.325765 Set Vref, RX VrefLevel [Byte0]: 56
3375 12:43:24.328559 [Byte1]: 56
3376 12:43:24.333272
3377 12:43:24.333741 Set Vref, RX VrefLevel [Byte0]: 57
3378 12:43:24.336487 [Byte1]: 57
3379 12:43:24.341070
3380 12:43:24.341500 Set Vref, RX VrefLevel [Byte0]: 58
3381 12:43:24.344284 [Byte1]: 58
3382 12:43:24.349086
3383 12:43:24.349532 Set Vref, RX VrefLevel [Byte0]: 59
3384 12:43:24.351762 [Byte1]: 59
3385 12:43:24.356127
3386 12:43:24.356722 Set Vref, RX VrefLevel [Byte0]: 60
3387 12:43:24.359909 [Byte1]: 60
3388 12:43:24.364575
3389 12:43:24.365035 Set Vref, RX VrefLevel [Byte0]: 61
3390 12:43:24.367702 [Byte1]: 61
3391 12:43:24.372010
3392 12:43:24.372488 Set Vref, RX VrefLevel [Byte0]: 62
3393 12:43:24.375377 [Byte1]: 62
3394 12:43:24.380111
3395 12:43:24.380639 Set Vref, RX VrefLevel [Byte0]: 63
3396 12:43:24.383265 [Byte1]: 63
3397 12:43:24.387652
3398 12:43:24.388153 Set Vref, RX VrefLevel [Byte0]: 64
3399 12:43:24.391472 [Byte1]: 64
3400 12:43:24.395620
3401 12:43:24.396059 Set Vref, RX VrefLevel [Byte0]: 65
3402 12:43:24.399022 [Byte1]: 65
3403 12:43:24.403313
3404 12:43:24.403791 Set Vref, RX VrefLevel [Byte0]: 66
3405 12:43:24.407001 [Byte1]: 66
3406 12:43:24.411250
3407 12:43:24.411689 Set Vref, RX VrefLevel [Byte0]: 67
3408 12:43:24.414729 [Byte1]: 67
3409 12:43:24.419214
3410 12:43:24.419647 Set Vref, RX VrefLevel [Byte0]: 68
3411 12:43:24.422529 [Byte1]: 68
3412 12:43:24.427259
3413 12:43:24.427693 Final RX Vref Byte 0 = 54 to rank0
3414 12:43:24.430544 Final RX Vref Byte 1 = 51 to rank0
3415 12:43:24.433793 Final RX Vref Byte 0 = 54 to rank1
3416 12:43:24.437060 Final RX Vref Byte 1 = 51 to rank1==
3417 12:43:24.440480 Dram Type= 6, Freq= 0, CH_1, rank 0
3418 12:43:24.447425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3419 12:43:24.447865 ==
3420 12:43:24.448199 DQS Delay:
3421 12:43:24.448576 DQS0 = 0, DQS1 = 0
3422 12:43:24.450772 DQM Delay:
3423 12:43:24.451206 DQM0 = 120, DQM1 = 117
3424 12:43:24.454037 DQ Delay:
3425 12:43:24.457443 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3426 12:43:24.460477 DQ4 =120, DQ5 =128, DQ6 =128, DQ7 =120
3427 12:43:24.463753 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =110
3428 12:43:24.466982 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3429 12:43:24.467402
3430 12:43:24.467745
3431 12:43:24.474229 [DQSOSCAuto] RK0, (LSB)MR18= 0x13, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 410 ps
3432 12:43:24.477285 CH1 RK0: MR19=404, MR18=13
3433 12:43:24.484248 CH1_RK0: MR19=0x404, MR18=0x13, DQSOSC=402, MR23=63, INC=40, DEC=27
3434 12:43:24.484674
3435 12:43:24.487095 ----->DramcWriteLeveling(PI) begin...
3436 12:43:24.487581 ==
3437 12:43:24.490266 Dram Type= 6, Freq= 0, CH_1, rank 1
3438 12:43:24.494091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3439 12:43:24.494589 ==
3440 12:43:24.497187 Write leveling (Byte 0): 26 => 26
3441 12:43:24.500392 Write leveling (Byte 1): 29 => 29
3442 12:43:24.504054 DramcWriteLeveling(PI) end<-----
3443 12:43:24.504499
3444 12:43:24.504877 ==
3445 12:43:24.507290 Dram Type= 6, Freq= 0, CH_1, rank 1
3446 12:43:24.510465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3447 12:43:24.513642 ==
3448 12:43:24.514058 [Gating] SW mode calibration
3449 12:43:24.520245 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3450 12:43:24.526925 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3451 12:43:24.530285 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3452 12:43:24.536907 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3453 12:43:24.540584 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3454 12:43:24.543794 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3455 12:43:24.550499 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3456 12:43:24.553876 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3457 12:43:24.557140 0 15 24 | B1->B0 | 2828 3434 | 0 0 | (1 0) (0 0)
3458 12:43:24.563799 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3459 12:43:24.567699 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 12:43:24.570890 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3461 12:43:24.574454 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3462 12:43:24.580745 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3463 12:43:24.583952 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3464 12:43:24.587120 1 0 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3465 12:43:24.594003 1 0 24 | B1->B0 | 4141 2a2a | 0 0 | (0 0) (0 0)
3466 12:43:24.597021 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 12:43:24.600768 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 12:43:24.607043 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 12:43:24.610743 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 12:43:24.613967 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 12:43:24.620337 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 12:43:24.624178 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3473 12:43:24.627088 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3474 12:43:24.633613 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3475 12:43:24.636837 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 12:43:24.640228 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 12:43:24.646858 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 12:43:24.650574 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 12:43:24.653810 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 12:43:24.660442 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 12:43:24.663769 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 12:43:24.667253 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 12:43:24.673499 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 12:43:24.676935 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 12:43:24.680188 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 12:43:24.683604 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 12:43:24.690451 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 12:43:24.693669 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3489 12:43:24.697295 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3490 12:43:24.704026 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3491 12:43:24.707093 Total UI for P1: 0, mck2ui 16
3492 12:43:24.713790 best dqsien dly found for B1: ( 1, 3, 22)
3493 12:43:24.714500 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3494 12:43:24.717273 Total UI for P1: 0, mck2ui 16
3495 12:43:24.720324 best dqsien dly found for B0: ( 1, 3, 24)
3496 12:43:24.723771 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3497 12:43:24.726865 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3498 12:43:24.727321
3499 12:43:24.730401 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3500 12:43:24.733741 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3501 12:43:24.736882 [Gating] SW calibration Done
3502 12:43:24.737332 ==
3503 12:43:24.740234 Dram Type= 6, Freq= 0, CH_1, rank 1
3504 12:43:24.746888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3505 12:43:24.747317 ==
3506 12:43:24.747655 RX Vref Scan: 0
3507 12:43:24.747968
3508 12:43:24.750276 RX Vref 0 -> 0, step: 1
3509 12:43:24.750701
3510 12:43:24.753301 RX Delay -40 -> 252, step: 8
3511 12:43:24.757214 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3512 12:43:24.760308 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3513 12:43:24.763722 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3514 12:43:24.766988 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3515 12:43:24.773685 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3516 12:43:24.776755 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3517 12:43:24.780150 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3518 12:43:24.783377 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3519 12:43:24.786751 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3520 12:43:24.793316 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3521 12:43:24.796555 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3522 12:43:24.800232 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3523 12:43:24.803482 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3524 12:43:24.806722 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3525 12:43:24.813587 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3526 12:43:24.816667 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3527 12:43:24.817228 ==
3528 12:43:24.820005 Dram Type= 6, Freq= 0, CH_1, rank 1
3529 12:43:24.823317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3530 12:43:24.823811 ==
3531 12:43:24.826558 DQS Delay:
3532 12:43:24.826983 DQS0 = 0, DQS1 = 0
3533 12:43:24.827314 DQM Delay:
3534 12:43:24.830317 DQM0 = 120, DQM1 = 118
3535 12:43:24.830767 DQ Delay:
3536 12:43:24.833505 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3537 12:43:24.836735 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =119
3538 12:43:24.843068 DQ8 =107, DQ9 =107, DQ10 =115, DQ11 =115
3539 12:43:24.846775 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3540 12:43:24.847193
3541 12:43:24.847622
3542 12:43:24.847938 ==
3543 12:43:24.850153 Dram Type= 6, Freq= 0, CH_1, rank 1
3544 12:43:24.853532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3545 12:43:24.853966 ==
3546 12:43:24.854294
3547 12:43:24.854599
3548 12:43:24.856901 TX Vref Scan disable
3549 12:43:24.857318 == TX Byte 0 ==
3550 12:43:24.863187 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3551 12:43:24.866350 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3552 12:43:24.866774 == TX Byte 1 ==
3553 12:43:24.873117 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3554 12:43:24.877228 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3555 12:43:24.877648 ==
3556 12:43:24.880344 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 12:43:24.883409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 12:43:24.883828 ==
3559 12:43:24.896190 TX Vref=22, minBit 9, minWin=25, winSum=420
3560 12:43:24.899626 TX Vref=24, minBit 1, minWin=26, winSum=424
3561 12:43:24.902647 TX Vref=26, minBit 1, minWin=26, winSum=430
3562 12:43:24.906120 TX Vref=28, minBit 2, minWin=26, winSum=429
3563 12:43:24.909320 TX Vref=30, minBit 9, minWin=26, winSum=434
3564 12:43:24.916124 TX Vref=32, minBit 9, minWin=26, winSum=433
3565 12:43:24.919168 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 30
3566 12:43:24.919587
3567 12:43:24.922906 Final TX Range 1 Vref 30
3568 12:43:24.923324
3569 12:43:24.923647 ==
3570 12:43:24.926001 Dram Type= 6, Freq= 0, CH_1, rank 1
3571 12:43:24.929234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3572 12:43:24.929677 ==
3573 12:43:24.932873
3574 12:43:24.933372
3575 12:43:24.933706 TX Vref Scan disable
3576 12:43:24.936103 == TX Byte 0 ==
3577 12:43:24.939362 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3578 12:43:24.942418 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3579 12:43:24.946273 == TX Byte 1 ==
3580 12:43:24.949111 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3581 12:43:24.953036 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3582 12:43:24.955603
3583 12:43:24.956194 [DATLAT]
3584 12:43:24.956554 Freq=1200, CH1 RK1
3585 12:43:24.956943
3586 12:43:24.958995 DATLAT Default: 0xd
3587 12:43:24.959418 0, 0xFFFF, sum = 0
3588 12:43:24.962089 1, 0xFFFF, sum = 0
3589 12:43:24.962521 2, 0xFFFF, sum = 0
3590 12:43:24.966039 3, 0xFFFF, sum = 0
3591 12:43:24.969399 4, 0xFFFF, sum = 0
3592 12:43:24.969850 5, 0xFFFF, sum = 0
3593 12:43:24.972488 6, 0xFFFF, sum = 0
3594 12:43:24.972962 7, 0xFFFF, sum = 0
3595 12:43:24.976073 8, 0xFFFF, sum = 0
3596 12:43:24.976504 9, 0xFFFF, sum = 0
3597 12:43:24.979167 10, 0xFFFF, sum = 0
3598 12:43:24.979601 11, 0xFFFF, sum = 0
3599 12:43:24.982533 12, 0x0, sum = 1
3600 12:43:24.982963 13, 0x0, sum = 2
3601 12:43:24.985701 14, 0x0, sum = 3
3602 12:43:24.986138 15, 0x0, sum = 4
3603 12:43:24.988732 best_step = 13
3604 12:43:24.989325
3605 12:43:24.989800 ==
3606 12:43:24.992123 Dram Type= 6, Freq= 0, CH_1, rank 1
3607 12:43:24.995925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3608 12:43:24.996375 ==
3609 12:43:24.996708 RX Vref Scan: 0
3610 12:43:24.997168
3611 12:43:24.999163 RX Vref 0 -> 0, step: 1
3612 12:43:24.999617
3613 12:43:25.002625 RX Delay -5 -> 252, step: 4
3614 12:43:25.005712 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3615 12:43:25.012333 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3616 12:43:25.015569 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3617 12:43:25.019018 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3618 12:43:25.022719 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3619 12:43:25.025578 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3620 12:43:25.029425 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3621 12:43:25.035666 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3622 12:43:25.039188 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3623 12:43:25.042329 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3624 12:43:25.045645 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3625 12:43:25.052518 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3626 12:43:25.055544 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3627 12:43:25.058733 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3628 12:43:25.061964 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3629 12:43:25.065283 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3630 12:43:25.068514 ==
3631 12:43:25.068988 Dram Type= 6, Freq= 0, CH_1, rank 1
3632 12:43:25.075719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3633 12:43:25.076149 ==
3634 12:43:25.076487 DQS Delay:
3635 12:43:25.078933 DQS0 = 0, DQS1 = 0
3636 12:43:25.079373 DQM Delay:
3637 12:43:25.082235 DQM0 = 120, DQM1 = 118
3638 12:43:25.082711 DQ Delay:
3639 12:43:25.085559 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3640 12:43:25.088915 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3641 12:43:25.091908 DQ8 =106, DQ9 =108, DQ10 =116, DQ11 =112
3642 12:43:25.095320 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3643 12:43:25.095746
3644 12:43:25.096078
3645 12:43:25.105342 [DQSOSCAuto] RK1, (LSB)MR18= 0x10ed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3646 12:43:25.108750 CH1 RK1: MR19=403, MR18=10ED
3647 12:43:25.111835 CH1_RK1: MR19=0x403, MR18=0x10ED, DQSOSC=403, MR23=63, INC=40, DEC=26
3648 12:43:25.115160 [RxdqsGatingPostProcess] freq 1200
3649 12:43:25.121619 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3650 12:43:25.125539 best DQS0 dly(2T, 0.5T) = (0, 11)
3651 12:43:25.128178 best DQS1 dly(2T, 0.5T) = (0, 11)
3652 12:43:25.131784 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3653 12:43:25.134983 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3654 12:43:25.138105 best DQS0 dly(2T, 0.5T) = (0, 11)
3655 12:43:25.141713 best DQS1 dly(2T, 0.5T) = (0, 11)
3656 12:43:25.144863 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3657 12:43:25.148639 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3658 12:43:25.149107 Pre-setting of DQS Precalculation
3659 12:43:25.155385 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3660 12:43:25.161878 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3661 12:43:25.168215 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3662 12:43:25.168663
3663 12:43:25.171409
3664 12:43:25.171833 [Calibration Summary] 2400 Mbps
3665 12:43:25.174760 CH 0, Rank 0
3666 12:43:25.175185 SW Impedance : PASS
3667 12:43:25.178250 DUTY Scan : NO K
3668 12:43:25.181410 ZQ Calibration : PASS
3669 12:43:25.181835 Jitter Meter : NO K
3670 12:43:25.184561 CBT Training : PASS
3671 12:43:25.187964 Write leveling : PASS
3672 12:43:25.188390 RX DQS gating : PASS
3673 12:43:25.191227 RX DQ/DQS(RDDQC) : PASS
3674 12:43:25.194986 TX DQ/DQS : PASS
3675 12:43:25.195473 RX DATLAT : PASS
3676 12:43:25.198109 RX DQ/DQS(Engine): PASS
3677 12:43:25.201613 TX OE : NO K
3678 12:43:25.202032 All Pass.
3679 12:43:25.202440
3680 12:43:25.202752 CH 0, Rank 1
3681 12:43:25.204882 SW Impedance : PASS
3682 12:43:25.208270 DUTY Scan : NO K
3683 12:43:25.208688 ZQ Calibration : PASS
3684 12:43:25.211483 Jitter Meter : NO K
3685 12:43:25.211900 CBT Training : PASS
3686 12:43:25.214671 Write leveling : PASS
3687 12:43:25.218078 RX DQS gating : PASS
3688 12:43:25.218494 RX DQ/DQS(RDDQC) : PASS
3689 12:43:25.221399 TX DQ/DQS : PASS
3690 12:43:25.224913 RX DATLAT : PASS
3691 12:43:25.225343 RX DQ/DQS(Engine): PASS
3692 12:43:25.227963 TX OE : NO K
3693 12:43:25.228401 All Pass.
3694 12:43:25.228733
3695 12:43:25.231046 CH 1, Rank 0
3696 12:43:25.231487 SW Impedance : PASS
3697 12:43:25.234378 DUTY Scan : NO K
3698 12:43:25.238001 ZQ Calibration : PASS
3699 12:43:25.238418 Jitter Meter : NO K
3700 12:43:25.241069 CBT Training : PASS
3701 12:43:25.244278 Write leveling : PASS
3702 12:43:25.244694 RX DQS gating : PASS
3703 12:43:25.248133 RX DQ/DQS(RDDQC) : PASS
3704 12:43:25.251276 TX DQ/DQS : PASS
3705 12:43:25.251698 RX DATLAT : PASS
3706 12:43:25.254375 RX DQ/DQS(Engine): PASS
3707 12:43:25.257659 TX OE : NO K
3708 12:43:25.258125 All Pass.
3709 12:43:25.258462
3710 12:43:25.258765 CH 1, Rank 1
3711 12:43:25.261327 SW Impedance : PASS
3712 12:43:25.261744 DUTY Scan : NO K
3713 12:43:25.264463 ZQ Calibration : PASS
3714 12:43:25.268069 Jitter Meter : NO K
3715 12:43:25.268554 CBT Training : PASS
3716 12:43:25.271145 Write leveling : PASS
3717 12:43:25.274210 RX DQS gating : PASS
3718 12:43:25.274624 RX DQ/DQS(RDDQC) : PASS
3719 12:43:25.277674 TX DQ/DQS : PASS
3720 12:43:25.280916 RX DATLAT : PASS
3721 12:43:25.281334 RX DQ/DQS(Engine): PASS
3722 12:43:25.284420 TX OE : NO K
3723 12:43:25.285015 All Pass.
3724 12:43:25.285370
3725 12:43:25.287512 DramC Write-DBI off
3726 12:43:25.290747 PER_BANK_REFRESH: Hybrid Mode
3727 12:43:25.291166 TX_TRACKING: ON
3728 12:43:25.300945 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3729 12:43:25.304164 [FAST_K] Save calibration result to emmc
3730 12:43:25.307633 dramc_set_vcore_voltage set vcore to 650000
3731 12:43:25.310891 Read voltage for 600, 5
3732 12:43:25.311395 Vio18 = 0
3733 12:43:25.311825 Vcore = 650000
3734 12:43:25.314152 Vdram = 0
3735 12:43:25.314594 Vddq = 0
3736 12:43:25.314927 Vmddr = 0
3737 12:43:25.320535 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3738 12:43:25.323831 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3739 12:43:25.327264 MEM_TYPE=3, freq_sel=19
3740 12:43:25.330634 sv_algorithm_assistance_LP4_1600
3741 12:43:25.333966 ============ PULL DRAM RESETB DOWN ============
3742 12:43:25.337674 ========== PULL DRAM RESETB DOWN end =========
3743 12:43:25.344057 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3744 12:43:25.347208 ===================================
3745 12:43:25.351068 LPDDR4 DRAM CONFIGURATION
3746 12:43:25.351495 ===================================
3747 12:43:25.354731 EX_ROW_EN[0] = 0x0
3748 12:43:25.357422 EX_ROW_EN[1] = 0x0
3749 12:43:25.357866 LP4Y_EN = 0x0
3750 12:43:25.360741 WORK_FSP = 0x0
3751 12:43:25.361295 WL = 0x2
3752 12:43:25.363878 RL = 0x2
3753 12:43:25.364498 BL = 0x2
3754 12:43:25.367676 RPST = 0x0
3755 12:43:25.368205 RD_PRE = 0x0
3756 12:43:25.370802 WR_PRE = 0x1
3757 12:43:25.371324 WR_PST = 0x0
3758 12:43:25.373885 DBI_WR = 0x0
3759 12:43:25.374340 DBI_RD = 0x0
3760 12:43:25.377138 OTF = 0x1
3761 12:43:25.380859 ===================================
3762 12:43:25.384011 ===================================
3763 12:43:25.384431 ANA top config
3764 12:43:25.387273 ===================================
3765 12:43:25.390652 DLL_ASYNC_EN = 0
3766 12:43:25.394103 ALL_SLAVE_EN = 1
3767 12:43:25.397490 NEW_RANK_MODE = 1
3768 12:43:25.397966 DLL_IDLE_MODE = 1
3769 12:43:25.400525 LP45_APHY_COMB_EN = 1
3770 12:43:25.403710 TX_ODT_DIS = 1
3771 12:43:25.406931 NEW_8X_MODE = 1
3772 12:43:25.410990 ===================================
3773 12:43:25.413642 ===================================
3774 12:43:25.416920 data_rate = 1200
3775 12:43:25.417389 CKR = 1
3776 12:43:25.420338 DQ_P2S_RATIO = 8
3777 12:43:25.423507 ===================================
3778 12:43:25.426842 CA_P2S_RATIO = 8
3779 12:43:25.430217 DQ_CA_OPEN = 0
3780 12:43:25.433480 DQ_SEMI_OPEN = 0
3781 12:43:25.436913 CA_SEMI_OPEN = 0
3782 12:43:25.437374 CA_FULL_RATE = 0
3783 12:43:25.440921 DQ_CKDIV4_EN = 1
3784 12:43:25.443988 CA_CKDIV4_EN = 1
3785 12:43:25.447156 CA_PREDIV_EN = 0
3786 12:43:25.450329 PH8_DLY = 0
3787 12:43:25.453987 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3788 12:43:25.454569 DQ_AAMCK_DIV = 4
3789 12:43:25.457138 CA_AAMCK_DIV = 4
3790 12:43:25.460215 CA_ADMCK_DIV = 4
3791 12:43:25.464255 DQ_TRACK_CA_EN = 0
3792 12:43:25.467244 CA_PICK = 600
3793 12:43:25.470704 CA_MCKIO = 600
3794 12:43:25.471120 MCKIO_SEMI = 0
3795 12:43:25.473958 PLL_FREQ = 2288
3796 12:43:25.476897 DQ_UI_PI_RATIO = 32
3797 12:43:25.480571 CA_UI_PI_RATIO = 0
3798 12:43:25.483704 ===================================
3799 12:43:25.486730 ===================================
3800 12:43:25.490822 memory_type:LPDDR4
3801 12:43:25.491277 GP_NUM : 10
3802 12:43:25.494244 SRAM_EN : 1
3803 12:43:25.494663 MD32_EN : 0
3804 12:43:25.497377 ===================================
3805 12:43:25.500834 [ANA_INIT] >>>>>>>>>>>>>>
3806 12:43:25.503836 <<<<<< [CONFIGURE PHASE]: ANA_TX
3807 12:43:25.506854 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3808 12:43:25.510624 ===================================
3809 12:43:25.513787 data_rate = 1200,PCW = 0X5800
3810 12:43:25.517235 ===================================
3811 12:43:25.520550 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3812 12:43:25.527148 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3813 12:43:25.530487 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3814 12:43:25.537087 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3815 12:43:25.540555 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3816 12:43:25.543911 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3817 12:43:25.544371 [ANA_INIT] flow start
3818 12:43:25.547112 [ANA_INIT] PLL >>>>>>>>
3819 12:43:25.550423 [ANA_INIT] PLL <<<<<<<<
3820 12:43:25.550867 [ANA_INIT] MIDPI >>>>>>>>
3821 12:43:25.553719 [ANA_INIT] MIDPI <<<<<<<<
3822 12:43:25.556863 [ANA_INIT] DLL >>>>>>>>
3823 12:43:25.557322 [ANA_INIT] flow end
3824 12:43:25.563523 ============ LP4 DIFF to SE enter ============
3825 12:43:25.566648 ============ LP4 DIFF to SE exit ============
3826 12:43:25.569752 [ANA_INIT] <<<<<<<<<<<<<
3827 12:43:25.573163 [Flow] Enable top DCM control >>>>>
3828 12:43:25.576951 [Flow] Enable top DCM control <<<<<
3829 12:43:25.580098 Enable DLL master slave shuffle
3830 12:43:25.583334 ==============================================================
3831 12:43:25.586773 Gating Mode config
3832 12:43:25.590232 ==============================================================
3833 12:43:25.593192 Config description:
3834 12:43:25.603060 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3835 12:43:25.610185 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3836 12:43:25.613229 SELPH_MODE 0: By rank 1: By Phase
3837 12:43:25.619529 ==============================================================
3838 12:43:25.622841 GAT_TRACK_EN = 1
3839 12:43:25.626210 RX_GATING_MODE = 2
3840 12:43:25.629428 RX_GATING_TRACK_MODE = 2
3841 12:43:25.632649 SELPH_MODE = 1
3842 12:43:25.635975 PICG_EARLY_EN = 1
3843 12:43:25.636393 VALID_LAT_VALUE = 1
3844 12:43:25.642553 ==============================================================
3845 12:43:25.645919 Enter into Gating configuration >>>>
3846 12:43:25.649298 Exit from Gating configuration <<<<
3847 12:43:25.652541 Enter into DVFS_PRE_config >>>>>
3848 12:43:25.662499 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3849 12:43:25.666346 Exit from DVFS_PRE_config <<<<<
3850 12:43:25.669464 Enter into PICG configuration >>>>
3851 12:43:25.672433 Exit from PICG configuration <<<<
3852 12:43:25.676344 [RX_INPUT] configuration >>>>>
3853 12:43:25.679533 [RX_INPUT] configuration <<<<<
3854 12:43:25.686135 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3855 12:43:25.689309 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3856 12:43:25.695497 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3857 12:43:25.702410 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3858 12:43:25.708794 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3859 12:43:25.715485 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3860 12:43:25.719108 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3861 12:43:25.722149 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3862 12:43:25.725262 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3863 12:43:25.732486 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3864 12:43:25.735199 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3865 12:43:25.738500 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3866 12:43:25.741939 ===================================
3867 12:43:25.745556 LPDDR4 DRAM CONFIGURATION
3868 12:43:25.749021 ===================================
3869 12:43:25.749460 EX_ROW_EN[0] = 0x0
3870 12:43:25.752181 EX_ROW_EN[1] = 0x0
3871 12:43:25.755445 LP4Y_EN = 0x0
3872 12:43:25.756058 WORK_FSP = 0x0
3873 12:43:25.758878 WL = 0x2
3874 12:43:25.759418 RL = 0x2
3875 12:43:25.762095 BL = 0x2
3876 12:43:25.762725 RPST = 0x0
3877 12:43:25.765184 RD_PRE = 0x0
3878 12:43:25.765607 WR_PRE = 0x1
3879 12:43:25.768747 WR_PST = 0x0
3880 12:43:25.769227 DBI_WR = 0x0
3881 12:43:25.772181 DBI_RD = 0x0
3882 12:43:25.772643 OTF = 0x1
3883 12:43:25.775359 ===================================
3884 12:43:25.778811 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3885 12:43:25.785564 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3886 12:43:25.788735 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3887 12:43:25.792064 ===================================
3888 12:43:25.795421 LPDDR4 DRAM CONFIGURATION
3889 12:43:25.798706 ===================================
3890 12:43:25.799263 EX_ROW_EN[0] = 0x10
3891 12:43:25.802029 EX_ROW_EN[1] = 0x0
3892 12:43:25.802632 LP4Y_EN = 0x0
3893 12:43:25.805571 WORK_FSP = 0x0
3894 12:43:25.806010 WL = 0x2
3895 12:43:25.808687 RL = 0x2
3896 12:43:25.809153 BL = 0x2
3897 12:43:25.811882 RPST = 0x0
3898 12:43:25.815217 RD_PRE = 0x0
3899 12:43:25.815642 WR_PRE = 0x1
3900 12:43:25.818423 WR_PST = 0x0
3901 12:43:25.818866 DBI_WR = 0x0
3902 12:43:25.821704 DBI_RD = 0x0
3903 12:43:25.822123 OTF = 0x1
3904 12:43:25.825555 ===================================
3905 12:43:25.832035 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3906 12:43:25.835410 nWR fixed to 30
3907 12:43:25.839296 [ModeRegInit_LP4] CH0 RK0
3908 12:43:25.839716 [ModeRegInit_LP4] CH0 RK1
3909 12:43:25.842464 [ModeRegInit_LP4] CH1 RK0
3910 12:43:25.845928 [ModeRegInit_LP4] CH1 RK1
3911 12:43:25.846351 match AC timing 17
3912 12:43:25.852684 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3913 12:43:25.855390 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3914 12:43:25.858765 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3915 12:43:25.865526 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3916 12:43:25.869367 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3917 12:43:25.869823 ==
3918 12:43:25.872412 Dram Type= 6, Freq= 0, CH_0, rank 0
3919 12:43:25.875444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3920 12:43:25.875901 ==
3921 12:43:25.882363 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3922 12:43:25.889029 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3923 12:43:25.892284 [CA 0] Center 35 (5~66) winsize 62
3924 12:43:25.895658 [CA 1] Center 36 (5~67) winsize 63
3925 12:43:25.899027 [CA 2] Center 33 (3~64) winsize 62
3926 12:43:25.902027 [CA 3] Center 33 (2~64) winsize 63
3927 12:43:25.905887 [CA 4] Center 33 (2~64) winsize 63
3928 12:43:25.909233 [CA 5] Center 32 (2~63) winsize 62
3929 12:43:25.909657
3930 12:43:25.912360 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3931 12:43:25.912777
3932 12:43:25.915757 [CATrainingPosCal] consider 1 rank data
3933 12:43:25.918802 u2DelayCellTimex100 = 270/100 ps
3934 12:43:25.922045 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3935 12:43:25.925455 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3936 12:43:25.928889 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3937 12:43:25.932074 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3938 12:43:25.935273 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3939 12:43:25.938712 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3940 12:43:25.941910
3941 12:43:25.945812 CA PerBit enable=1, Macro0, CA PI delay=32
3942 12:43:25.946201
3943 12:43:25.949064 [CBTSetCACLKResult] CA Dly = 32
3944 12:43:25.949438 CS Dly: 4 (0~35)
3945 12:43:25.949781 ==
3946 12:43:25.952462 Dram Type= 6, Freq= 0, CH_0, rank 1
3947 12:43:25.955722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3948 12:43:25.956126 ==
3949 12:43:25.962490 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3950 12:43:25.968958 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3951 12:43:25.972283 [CA 0] Center 35 (5~66) winsize 62
3952 12:43:25.975651 [CA 1] Center 35 (5~66) winsize 62
3953 12:43:25.978865 [CA 2] Center 34 (3~65) winsize 63
3954 12:43:25.981903 [CA 3] Center 33 (3~64) winsize 62
3955 12:43:25.985629 [CA 4] Center 32 (2~63) winsize 62
3956 12:43:25.988706 [CA 5] Center 32 (2~63) winsize 62
3957 12:43:25.989189
3958 12:43:25.991839 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3959 12:43:25.992321
3960 12:43:25.995161 [CATrainingPosCal] consider 2 rank data
3961 12:43:25.998332 u2DelayCellTimex100 = 270/100 ps
3962 12:43:26.002143 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3963 12:43:26.005283 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3964 12:43:26.008472 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3965 12:43:26.012189 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3966 12:43:26.015299 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3967 12:43:26.021816 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3968 12:43:26.022332
3969 12:43:26.025172 CA PerBit enable=1, Macro0, CA PI delay=32
3970 12:43:26.025736
3971 12:43:26.028782 [CBTSetCACLKResult] CA Dly = 32
3972 12:43:26.029253 CS Dly: 4 (0~36)
3973 12:43:26.029587
3974 12:43:26.032130 ----->DramcWriteLeveling(PI) begin...
3975 12:43:26.032554 ==
3976 12:43:26.035381 Dram Type= 6, Freq= 0, CH_0, rank 0
3977 12:43:26.041963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3978 12:43:26.042390 ==
3979 12:43:26.044901 Write leveling (Byte 0): 33 => 33
3980 12:43:26.045334 Write leveling (Byte 1): 32 => 32
3981 12:43:26.048205 DramcWriteLeveling(PI) end<-----
3982 12:43:26.048682
3983 12:43:26.049095 ==
3984 12:43:26.055133 Dram Type= 6, Freq= 0, CH_0, rank 0
3985 12:43:26.058359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3986 12:43:26.058814 ==
3987 12:43:26.061704 [Gating] SW mode calibration
3988 12:43:26.068378 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3989 12:43:26.071568 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3990 12:43:26.078193 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3991 12:43:26.081444 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3992 12:43:26.084849 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3993 12:43:26.091041 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 1)
3994 12:43:26.094765 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
3995 12:43:26.097795 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 12:43:26.104022 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 12:43:26.108007 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 12:43:26.110943 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 12:43:26.117702 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 12:43:26.120938 0 10 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
4001 12:43:26.124124 0 10 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
4002 12:43:26.130604 0 10 16 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
4003 12:43:26.134335 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 12:43:26.137532 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 12:43:26.144181 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 12:43:26.147523 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 12:43:26.150671 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 12:43:26.157656 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 12:43:26.160573 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4010 12:43:26.163888 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4011 12:43:26.170685 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 12:43:26.173910 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 12:43:26.177203 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 12:43:26.183948 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 12:43:26.187384 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 12:43:26.190582 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 12:43:26.193960 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 12:43:26.200199 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 12:43:26.203958 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 12:43:26.207330 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 12:43:26.213918 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 12:43:26.217221 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 12:43:26.220448 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 12:43:26.226807 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 12:43:26.229995 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4026 12:43:26.233945 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4027 12:43:26.236944 Total UI for P1: 0, mck2ui 16
4028 12:43:26.240141 best dqsien dly found for B0: ( 0, 13, 12)
4029 12:43:26.246713 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 12:43:26.249953 Total UI for P1: 0, mck2ui 16
4031 12:43:26.253156 best dqsien dly found for B1: ( 0, 13, 18)
4032 12:43:26.257079 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4033 12:43:26.260439 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4034 12:43:26.260895
4035 12:43:26.263548 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4036 12:43:26.266791 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4037 12:43:26.269937 [Gating] SW calibration Done
4038 12:43:26.270412 ==
4039 12:43:26.273312 Dram Type= 6, Freq= 0, CH_0, rank 0
4040 12:43:26.276755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4041 12:43:26.277226 ==
4042 12:43:26.280106 RX Vref Scan: 0
4043 12:43:26.280553
4044 12:43:26.280995 RX Vref 0 -> 0, step: 1
4045 12:43:26.283450
4046 12:43:26.283874 RX Delay -230 -> 252, step: 16
4047 12:43:26.290256 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4048 12:43:26.293548 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4049 12:43:26.296883 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4050 12:43:26.300127 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4051 12:43:26.303442 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4052 12:43:26.310470 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4053 12:43:26.313609 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4054 12:43:26.316597 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4055 12:43:26.320257 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4056 12:43:26.326944 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4057 12:43:26.329911 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4058 12:43:26.333039 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4059 12:43:26.336975 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4060 12:43:26.343420 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4061 12:43:26.346589 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4062 12:43:26.349703 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4063 12:43:26.350331 ==
4064 12:43:26.353132 Dram Type= 6, Freq= 0, CH_0, rank 0
4065 12:43:26.356418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4066 12:43:26.356968 ==
4067 12:43:26.359510 DQS Delay:
4068 12:43:26.360022 DQS0 = 0, DQS1 = 0
4069 12:43:26.362969 DQM Delay:
4070 12:43:26.363422 DQM0 = 53, DQM1 = 49
4071 12:43:26.363896 DQ Delay:
4072 12:43:26.366287 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4073 12:43:26.370107 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4074 12:43:26.373273 DQ8 =41, DQ9 =41, DQ10 =49, DQ11 =49
4075 12:43:26.376513 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4076 12:43:26.377005
4077 12:43:26.377346
4078 12:43:26.379641 ==
4079 12:43:26.382929 Dram Type= 6, Freq= 0, CH_0, rank 0
4080 12:43:26.386251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4081 12:43:26.386675 ==
4082 12:43:26.387006
4083 12:43:26.387365
4084 12:43:26.389598 TX Vref Scan disable
4085 12:43:26.390016 == TX Byte 0 ==
4086 12:43:26.396159 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4087 12:43:26.399572 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4088 12:43:26.400158 == TX Byte 1 ==
4089 12:43:26.406165 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4090 12:43:26.409475 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4091 12:43:26.409933 ==
4092 12:43:26.412645 Dram Type= 6, Freq= 0, CH_0, rank 0
4093 12:43:26.416432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4094 12:43:26.417002 ==
4095 12:43:26.417397
4096 12:43:26.417777
4097 12:43:26.419709 TX Vref Scan disable
4098 12:43:26.422838 == TX Byte 0 ==
4099 12:43:26.426344 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4100 12:43:26.429514 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4101 12:43:26.432793 == TX Byte 1 ==
4102 12:43:26.435913 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4103 12:43:26.439716 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4104 12:43:26.440310
4105 12:43:26.442924 [DATLAT]
4106 12:43:26.443375 Freq=600, CH0 RK0
4107 12:43:26.443766
4108 12:43:26.446064 DATLAT Default: 0x9
4109 12:43:26.446479 0, 0xFFFF, sum = 0
4110 12:43:26.449513 1, 0xFFFF, sum = 0
4111 12:43:26.450166 2, 0xFFFF, sum = 0
4112 12:43:26.452613 3, 0xFFFF, sum = 0
4113 12:43:26.453115 4, 0xFFFF, sum = 0
4114 12:43:26.456584 5, 0xFFFF, sum = 0
4115 12:43:26.457133 6, 0xFFFF, sum = 0
4116 12:43:26.460112 7, 0xFFFF, sum = 0
4117 12:43:26.460566 8, 0x0, sum = 1
4118 12:43:26.463088 9, 0x0, sum = 2
4119 12:43:26.463523 10, 0x0, sum = 3
4120 12:43:26.466510 11, 0x0, sum = 4
4121 12:43:26.466946 best_step = 9
4122 12:43:26.467371
4123 12:43:26.467773 ==
4124 12:43:26.469930 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 12:43:26.473123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 12:43:26.476229 ==
4127 12:43:26.476661 RX Vref Scan: 1
4128 12:43:26.477113
4129 12:43:26.479474 RX Vref 0 -> 0, step: 1
4130 12:43:26.479903
4131 12:43:26.482741 RX Delay -147 -> 252, step: 8
4132 12:43:26.483169
4133 12:43:26.486017 Set Vref, RX VrefLevel [Byte0]: 55
4134 12:43:26.489239 [Byte1]: 55
4135 12:43:26.489667
4136 12:43:26.492445 Final RX Vref Byte 0 = 55 to rank0
4137 12:43:26.495897 Final RX Vref Byte 1 = 55 to rank0
4138 12:43:26.499525 Final RX Vref Byte 0 = 55 to rank1
4139 12:43:26.502698 Final RX Vref Byte 1 = 55 to rank1==
4140 12:43:26.506187 Dram Type= 6, Freq= 0, CH_0, rank 0
4141 12:43:26.509462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4142 12:43:26.509890 ==
4143 12:43:26.510228 DQS Delay:
4144 12:43:26.512268 DQS0 = 0, DQS1 = 0
4145 12:43:26.512692 DQM Delay:
4146 12:43:26.515565 DQM0 = 54, DQM1 = 46
4147 12:43:26.516017 DQ Delay:
4148 12:43:26.519552 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4149 12:43:26.522679 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =64
4150 12:43:26.525689 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4151 12:43:26.529471 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4152 12:43:26.529986
4153 12:43:26.530391
4154 12:43:26.539422 [DQSOSCAuto] RK0, (LSB)MR18= 0x7366, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 388 ps
4155 12:43:26.539901 CH0 RK0: MR19=808, MR18=7366
4156 12:43:26.545642 CH0_RK0: MR19=0x808, MR18=0x7366, DQSOSC=388, MR23=63, INC=174, DEC=116
4157 12:43:26.546249
4158 12:43:26.549001 ----->DramcWriteLeveling(PI) begin...
4159 12:43:26.549584 ==
4160 12:43:26.552137 Dram Type= 6, Freq= 0, CH_0, rank 1
4161 12:43:26.558948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 12:43:26.559378 ==
4163 12:43:26.562623 Write leveling (Byte 0): 33 => 33
4164 12:43:26.565886 Write leveling (Byte 1): 30 => 30
4165 12:43:26.566313 DramcWriteLeveling(PI) end<-----
4166 12:43:26.566647
4167 12:43:26.568877 ==
4168 12:43:26.569180 Dram Type= 6, Freq= 0, CH_0, rank 1
4169 12:43:26.575583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4170 12:43:26.575817 ==
4171 12:43:26.578788 [Gating] SW mode calibration
4172 12:43:26.585465 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4173 12:43:26.588632 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4174 12:43:26.595706 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4175 12:43:26.598979 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4176 12:43:26.602237 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4177 12:43:26.608780 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
4178 12:43:26.612199 0 9 16 | B1->B0 | 2828 2929 | 0 0 | (0 0) (0 0)
4179 12:43:26.615492 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 12:43:26.618791 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 12:43:26.625487 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4182 12:43:26.629157 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 12:43:26.632353 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 12:43:26.638741 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4185 12:43:26.641807 0 10 12 | B1->B0 | 2727 2626 | 0 0 | (0 0) (0 0)
4186 12:43:26.645764 0 10 16 | B1->B0 | 4141 4444 | 0 0 | (0 0) (0 0)
4187 12:43:26.651986 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 12:43:26.655339 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 12:43:26.658659 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 12:43:26.665781 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 12:43:26.668883 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 12:43:26.671861 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 12:43:26.678822 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4194 12:43:26.682217 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 12:43:26.685337 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 12:43:26.691862 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 12:43:26.695131 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 12:43:26.698921 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 12:43:26.705618 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 12:43:26.708747 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 12:43:26.712195 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 12:43:26.718816 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 12:43:26.722307 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 12:43:26.725421 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 12:43:26.731986 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 12:43:26.735063 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 12:43:26.738667 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 12:43:26.741819 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 12:43:26.748733 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 12:43:26.751920 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4211 12:43:26.755167 Total UI for P1: 0, mck2ui 16
4212 12:43:26.758388 best dqsien dly found for B0: ( 0, 13, 14)
4213 12:43:26.761562 Total UI for P1: 0, mck2ui 16
4214 12:43:26.765358 best dqsien dly found for B1: ( 0, 13, 14)
4215 12:43:26.768633 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4216 12:43:26.771925 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4217 12:43:26.772007
4218 12:43:26.775191 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4219 12:43:26.781937 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4220 12:43:26.782019 [Gating] SW calibration Done
4221 12:43:26.782083 ==
4222 12:43:26.785160 Dram Type= 6, Freq= 0, CH_0, rank 1
4223 12:43:26.791498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4224 12:43:26.791581 ==
4225 12:43:26.791658 RX Vref Scan: 0
4226 12:43:26.791749
4227 12:43:26.794967 RX Vref 0 -> 0, step: 1
4228 12:43:26.795078
4229 12:43:26.798258 RX Delay -230 -> 252, step: 16
4230 12:43:26.801641 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4231 12:43:26.804970 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4232 12:43:26.808780 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4233 12:43:26.815291 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4234 12:43:26.818555 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4235 12:43:26.821856 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4236 12:43:26.825171 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4237 12:43:26.831678 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4238 12:43:26.835298 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4239 12:43:26.838411 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4240 12:43:26.841652 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4241 12:43:26.844704 iDelay=218, Bit 11, Center 41 (-102 ~ 185) 288
4242 12:43:26.851513 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4243 12:43:26.854700 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4244 12:43:26.858373 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4245 12:43:26.861754 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4246 12:43:26.864772 ==
4247 12:43:26.868391 Dram Type= 6, Freq= 0, CH_0, rank 1
4248 12:43:26.871710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4249 12:43:26.871800 ==
4250 12:43:26.871895 DQS Delay:
4251 12:43:26.875087 DQS0 = 0, DQS1 = 0
4252 12:43:26.875198 DQM Delay:
4253 12:43:26.878229 DQM0 = 52, DQM1 = 44
4254 12:43:26.878310 DQ Delay:
4255 12:43:26.881428 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4256 12:43:26.884808 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4257 12:43:26.888387 DQ8 =33, DQ9 =25, DQ10 =49, DQ11 =41
4258 12:43:26.891502 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4259 12:43:26.891584
4260 12:43:26.891648
4261 12:43:26.891706 ==
4262 12:43:26.894592 Dram Type= 6, Freq= 0, CH_0, rank 1
4263 12:43:26.898014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4264 12:43:26.898097 ==
4265 12:43:26.898160
4266 12:43:26.898219
4267 12:43:26.901230 TX Vref Scan disable
4268 12:43:26.904470 == TX Byte 0 ==
4269 12:43:26.908354 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4270 12:43:26.911520 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4271 12:43:26.914577 == TX Byte 1 ==
4272 12:43:26.918031 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4273 12:43:26.921494 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4274 12:43:26.921576 ==
4275 12:43:26.924777 Dram Type= 6, Freq= 0, CH_0, rank 1
4276 12:43:26.928041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4277 12:43:26.931391 ==
4278 12:43:26.931471
4279 12:43:26.931535
4280 12:43:26.931594 TX Vref Scan disable
4281 12:43:26.935258 == TX Byte 0 ==
4282 12:43:26.938534 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4283 12:43:26.941931 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4284 12:43:26.945182 == TX Byte 1 ==
4285 12:43:26.948453 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4286 12:43:26.952262 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4287 12:43:26.955257
4288 12:43:26.955337 [DATLAT]
4289 12:43:26.955401 Freq=600, CH0 RK1
4290 12:43:26.955461
4291 12:43:26.958989 DATLAT Default: 0x9
4292 12:43:26.959070 0, 0xFFFF, sum = 0
4293 12:43:26.961984 1, 0xFFFF, sum = 0
4294 12:43:26.962099 2, 0xFFFF, sum = 0
4295 12:43:26.965114 3, 0xFFFF, sum = 0
4296 12:43:26.965195 4, 0xFFFF, sum = 0
4297 12:43:26.968371 5, 0xFFFF, sum = 0
4298 12:43:26.972187 6, 0xFFFF, sum = 0
4299 12:43:26.972268 7, 0xFFFF, sum = 0
4300 12:43:26.972330 8, 0x0, sum = 1
4301 12:43:26.975105 9, 0x0, sum = 2
4302 12:43:26.975218 10, 0x0, sum = 3
4303 12:43:26.978777 11, 0x0, sum = 4
4304 12:43:26.978858 best_step = 9
4305 12:43:26.978920
4306 12:43:26.978978 ==
4307 12:43:26.982119 Dram Type= 6, Freq= 0, CH_0, rank 1
4308 12:43:26.988638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4309 12:43:26.988718 ==
4310 12:43:26.988780 RX Vref Scan: 0
4311 12:43:26.988886
4312 12:43:26.991904 RX Vref 0 -> 0, step: 1
4313 12:43:26.991983
4314 12:43:26.994974 RX Delay -179 -> 252, step: 8
4315 12:43:26.998630 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4316 12:43:27.005053 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4317 12:43:27.008671 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4318 12:43:27.011288 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4319 12:43:27.015183 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4320 12:43:27.018204 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4321 12:43:27.021846 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4322 12:43:27.028225 iDelay=197, Bit 7, Center 60 (-75 ~ 196) 272
4323 12:43:27.031654 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4324 12:43:27.034817 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4325 12:43:27.038209 iDelay=197, Bit 10, Center 44 (-99 ~ 188) 288
4326 12:43:27.044975 iDelay=197, Bit 11, Center 36 (-107 ~ 180) 288
4327 12:43:27.048417 iDelay=197, Bit 12, Center 52 (-91 ~ 196) 288
4328 12:43:27.051728 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4329 12:43:27.054920 iDelay=197, Bit 14, Center 52 (-91 ~ 196) 288
4330 12:43:27.058129 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4331 12:43:27.061336 ==
4332 12:43:27.065127 Dram Type= 6, Freq= 0, CH_0, rank 1
4333 12:43:27.068206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4334 12:43:27.068287 ==
4335 12:43:27.068349 DQS Delay:
4336 12:43:27.071201 DQS0 = 0, DQS1 = 0
4337 12:43:27.071277 DQM Delay:
4338 12:43:27.074865 DQM0 = 53, DQM1 = 45
4339 12:43:27.074972 DQ Delay:
4340 12:43:27.077968 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4341 12:43:27.081715 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =60
4342 12:43:27.084898 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =36
4343 12:43:27.088490 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4344 12:43:27.088621
4345 12:43:27.088684
4346 12:43:27.094878 [DQSOSCAuto] RK1, (LSB)MR18= 0x6021, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4347 12:43:27.098168 CH0 RK1: MR19=808, MR18=6021
4348 12:43:27.105142 CH0_RK1: MR19=0x808, MR18=0x6021, DQSOSC=391, MR23=63, INC=171, DEC=114
4349 12:43:27.108430 [RxdqsGatingPostProcess] freq 600
4350 12:43:27.111566 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4351 12:43:27.114753 Pre-setting of DQS Precalculation
4352 12:43:27.121992 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4353 12:43:27.122077 ==
4354 12:43:27.124608 Dram Type= 6, Freq= 0, CH_1, rank 0
4355 12:43:27.128369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4356 12:43:27.128455 ==
4357 12:43:27.134976 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4358 12:43:27.141599 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4359 12:43:27.144997 [CA 0] Center 36 (5~67) winsize 63
4360 12:43:27.148083 [CA 1] Center 36 (5~67) winsize 63
4361 12:43:27.151432 [CA 2] Center 34 (4~65) winsize 62
4362 12:43:27.154743 [CA 3] Center 34 (4~65) winsize 62
4363 12:43:27.158097 [CA 4] Center 34 (4~65) winsize 62
4364 12:43:27.161353 [CA 5] Center 34 (3~65) winsize 63
4365 12:43:27.161432
4366 12:43:27.164693 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4367 12:43:27.164774
4368 12:43:27.167947 [CATrainingPosCal] consider 1 rank data
4369 12:43:27.171069 u2DelayCellTimex100 = 270/100 ps
4370 12:43:27.174385 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4371 12:43:27.178163 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4372 12:43:27.181483 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4373 12:43:27.184459 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4374 12:43:27.187560 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4375 12:43:27.191438 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4376 12:43:27.191518
4377 12:43:27.198044 CA PerBit enable=1, Macro0, CA PI delay=34
4378 12:43:27.198124
4379 12:43:27.198186 [CBTSetCACLKResult] CA Dly = 34
4380 12:43:27.201347 CS Dly: 5 (0~36)
4381 12:43:27.201430 ==
4382 12:43:27.204610 Dram Type= 6, Freq= 0, CH_1, rank 1
4383 12:43:27.207805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4384 12:43:27.207884 ==
4385 12:43:27.214558 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4386 12:43:27.220730 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4387 12:43:27.224544 [CA 0] Center 36 (5~67) winsize 63
4388 12:43:27.227565 [CA 1] Center 36 (5~67) winsize 63
4389 12:43:27.230869 [CA 2] Center 34 (4~65) winsize 62
4390 12:43:27.234762 [CA 3] Center 34 (4~65) winsize 62
4391 12:43:27.237993 [CA 4] Center 34 (4~65) winsize 62
4392 12:43:27.241360 [CA 5] Center 34 (3~65) winsize 63
4393 12:43:27.241432
4394 12:43:27.244558 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4395 12:43:27.244634
4396 12:43:27.247891 [CATrainingPosCal] consider 2 rank data
4397 12:43:27.251345 u2DelayCellTimex100 = 270/100 ps
4398 12:43:27.254580 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4399 12:43:27.257874 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4400 12:43:27.261162 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4401 12:43:27.264471 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4402 12:43:27.267462 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4403 12:43:27.271055 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4404 12:43:27.274207
4405 12:43:27.277418 CA PerBit enable=1, Macro0, CA PI delay=34
4406 12:43:27.277501
4407 12:43:27.280571 [CBTSetCACLKResult] CA Dly = 34
4408 12:43:27.280675 CS Dly: 6 (0~38)
4409 12:43:27.280772
4410 12:43:27.284440 ----->DramcWriteLeveling(PI) begin...
4411 12:43:27.284513 ==
4412 12:43:27.287729 Dram Type= 6, Freq= 0, CH_1, rank 0
4413 12:43:27.290845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4414 12:43:27.293972 ==
4415 12:43:27.294042 Write leveling (Byte 0): 29 => 29
4416 12:43:27.297760 Write leveling (Byte 1): 32 => 32
4417 12:43:27.300638 DramcWriteLeveling(PI) end<-----
4418 12:43:27.300712
4419 12:43:27.300773 ==
4420 12:43:27.304044 Dram Type= 6, Freq= 0, CH_1, rank 0
4421 12:43:27.310868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4422 12:43:27.310948 ==
4423 12:43:27.311011 [Gating] SW mode calibration
4424 12:43:27.320707 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4425 12:43:27.324125 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4426 12:43:27.327649 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4427 12:43:27.334450 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4428 12:43:27.337696 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4429 12:43:27.340747 0 9 12 | B1->B0 | 2f2f 2f2f | 1 0 | (1 0) (0 0)
4430 12:43:27.347244 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 12:43:27.350561 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 12:43:27.353859 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 12:43:27.360495 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 12:43:27.364326 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 12:43:27.367780 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4436 12:43:27.373877 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4437 12:43:27.377226 0 10 12 | B1->B0 | 3434 3b3b | 0 0 | (0 0) (0 0)
4438 12:43:27.380578 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 12:43:27.387599 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 12:43:27.390568 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 12:43:27.393813 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 12:43:27.400594 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 12:43:27.403741 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 12:43:27.407326 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4445 12:43:27.414062 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4446 12:43:27.417215 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 12:43:27.420457 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 12:43:27.427098 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 12:43:27.431073 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 12:43:27.434312 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 12:43:27.437360 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 12:43:27.443805 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 12:43:27.447545 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 12:43:27.450734 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 12:43:27.457278 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 12:43:27.460676 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 12:43:27.464121 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 12:43:27.470668 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 12:43:27.473799 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 12:43:27.477059 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 12:43:27.483691 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 12:43:27.486948 Total UI for P1: 0, mck2ui 16
4463 12:43:27.490082 best dqsien dly found for B0: ( 0, 13, 10)
4464 12:43:27.490153 Total UI for P1: 0, mck2ui 16
4465 12:43:27.497065 best dqsien dly found for B1: ( 0, 13, 10)
4466 12:43:27.500157 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4467 12:43:27.503871 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4468 12:43:27.503943
4469 12:43:27.507026 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4470 12:43:27.510347 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4471 12:43:27.513363 [Gating] SW calibration Done
4472 12:43:27.513447 ==
4473 12:43:27.517068 Dram Type= 6, Freq= 0, CH_1, rank 0
4474 12:43:27.520252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4475 12:43:27.520335 ==
4476 12:43:27.523385 RX Vref Scan: 0
4477 12:43:27.523468
4478 12:43:27.523531 RX Vref 0 -> 0, step: 1
4479 12:43:27.523592
4480 12:43:27.527223 RX Delay -230 -> 252, step: 16
4481 12:43:27.533804 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4482 12:43:27.536850 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4483 12:43:27.540038 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4484 12:43:27.543369 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4485 12:43:27.547180 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4486 12:43:27.553823 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4487 12:43:27.556814 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4488 12:43:27.560051 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4489 12:43:27.563498 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4490 12:43:27.570201 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4491 12:43:27.573590 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4492 12:43:27.576860 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4493 12:43:27.580004 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4494 12:43:27.586864 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4495 12:43:27.590176 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4496 12:43:27.593404 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4497 12:43:27.593516 ==
4498 12:43:27.596686 Dram Type= 6, Freq= 0, CH_1, rank 0
4499 12:43:27.599859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4500 12:43:27.602917 ==
4501 12:43:27.602998 DQS Delay:
4502 12:43:27.603061 DQS0 = 0, DQS1 = 0
4503 12:43:27.606121 DQM Delay:
4504 12:43:27.606202 DQM0 = 49, DQM1 = 46
4505 12:43:27.609645 DQ Delay:
4506 12:43:27.609747 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4507 12:43:27.613282 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4508 12:43:27.616485 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4509 12:43:27.619829 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4510 12:43:27.619911
4511 12:43:27.622745
4512 12:43:27.622827 ==
4513 12:43:27.626413 Dram Type= 6, Freq= 0, CH_1, rank 0
4514 12:43:27.629403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4515 12:43:27.629486 ==
4516 12:43:27.629551
4517 12:43:27.629612
4518 12:43:27.632584 TX Vref Scan disable
4519 12:43:27.632666 == TX Byte 0 ==
4520 12:43:27.639746 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4521 12:43:27.642956 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4522 12:43:27.643039 == TX Byte 1 ==
4523 12:43:27.649467 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4524 12:43:27.652753 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4525 12:43:27.652860 ==
4526 12:43:27.655965 Dram Type= 6, Freq= 0, CH_1, rank 0
4527 12:43:27.659143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4528 12:43:27.659227 ==
4529 12:43:27.659292
4530 12:43:27.659352
4531 12:43:27.663008 TX Vref Scan disable
4532 12:43:27.666371 == TX Byte 0 ==
4533 12:43:27.669648 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4534 12:43:27.672980 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4535 12:43:27.676190 == TX Byte 1 ==
4536 12:43:27.679794 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4537 12:43:27.682916 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4538 12:43:27.682999
4539 12:43:27.686159 [DATLAT]
4540 12:43:27.686240 Freq=600, CH1 RK0
4541 12:43:27.686306
4542 12:43:27.689411 DATLAT Default: 0x9
4543 12:43:27.689493 0, 0xFFFF, sum = 0
4544 12:43:27.692741 1, 0xFFFF, sum = 0
4545 12:43:27.692869 2, 0xFFFF, sum = 0
4546 12:43:27.696065 3, 0xFFFF, sum = 0
4547 12:43:27.696148 4, 0xFFFF, sum = 0
4548 12:43:27.699421 5, 0xFFFF, sum = 0
4549 12:43:27.699505 6, 0xFFFF, sum = 0
4550 12:43:27.702977 7, 0xFFFF, sum = 0
4551 12:43:27.703061 8, 0x0, sum = 1
4552 12:43:27.705996 9, 0x0, sum = 2
4553 12:43:27.706080 10, 0x0, sum = 3
4554 12:43:27.709128 11, 0x0, sum = 4
4555 12:43:27.709211 best_step = 9
4556 12:43:27.709276
4557 12:43:27.709336 ==
4558 12:43:27.712411 Dram Type= 6, Freq= 0, CH_1, rank 0
4559 12:43:27.718805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4560 12:43:27.718888 ==
4561 12:43:27.718953 RX Vref Scan: 1
4562 12:43:27.719013
4563 12:43:27.722274 RX Vref 0 -> 0, step: 1
4564 12:43:27.722357
4565 12:43:27.725754 RX Delay -163 -> 252, step: 8
4566 12:43:27.725867
4567 12:43:27.728852 Set Vref, RX VrefLevel [Byte0]: 54
4568 12:43:27.732550 [Byte1]: 51
4569 12:43:27.732631
4570 12:43:27.735664 Final RX Vref Byte 0 = 54 to rank0
4571 12:43:27.739250 Final RX Vref Byte 1 = 51 to rank0
4572 12:43:27.742336 Final RX Vref Byte 0 = 54 to rank1
4573 12:43:27.745583 Final RX Vref Byte 1 = 51 to rank1==
4574 12:43:27.749004 Dram Type= 6, Freq= 0, CH_1, rank 0
4575 12:43:27.752259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 12:43:27.752343 ==
4577 12:43:27.755509 DQS Delay:
4578 12:43:27.755591 DQS0 = 0, DQS1 = 0
4579 12:43:27.755657 DQM Delay:
4580 12:43:27.758869 DQM0 = 48, DQM1 = 47
4581 12:43:27.758951 DQ Delay:
4582 12:43:27.762573 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4583 12:43:27.765935 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4584 12:43:27.769227 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =40
4585 12:43:27.772503 DQ12 =56, DQ13 =52, DQ14 =56, DQ15 =60
4586 12:43:27.772586
4587 12:43:27.772650
4588 12:43:27.782553 [DQSOSCAuto] RK0, (LSB)MR18= 0x4469, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 396 ps
4589 12:43:27.782640 CH1 RK0: MR19=808, MR18=4469
4590 12:43:27.788936 CH1_RK0: MR19=0x808, MR18=0x4469, DQSOSC=390, MR23=63, INC=172, DEC=114
4591 12:43:27.789019
4592 12:43:27.792282 ----->DramcWriteLeveling(PI) begin...
4593 12:43:27.795595 ==
4594 12:43:27.795677 Dram Type= 6, Freq= 0, CH_1, rank 1
4595 12:43:27.802246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4596 12:43:27.802330 ==
4597 12:43:27.805551 Write leveling (Byte 0): 30 => 30
4598 12:43:27.808779 Write leveling (Byte 1): 31 => 31
4599 12:43:27.811952 DramcWriteLeveling(PI) end<-----
4600 12:43:27.812043
4601 12:43:27.812108 ==
4602 12:43:27.815242 Dram Type= 6, Freq= 0, CH_1, rank 1
4603 12:43:27.818520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4604 12:43:27.818603 ==
4605 12:43:27.822282 [Gating] SW mode calibration
4606 12:43:27.828936 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4607 12:43:27.832133 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4608 12:43:27.839149 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4609 12:43:27.842242 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4610 12:43:27.845475 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4611 12:43:27.852312 0 9 12 | B1->B0 | 3030 3030 | 0 0 | (1 1) (1 1)
4612 12:43:27.855432 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4613 12:43:27.858494 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4614 12:43:27.865115 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 12:43:27.868776 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4616 12:43:27.872230 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4617 12:43:27.878665 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4618 12:43:27.881794 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4619 12:43:27.885212 0 10 12 | B1->B0 | 3535 3434 | 1 1 | (0 0) (0 0)
4620 12:43:27.892071 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 12:43:27.895412 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 12:43:27.898908 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 12:43:27.905365 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 12:43:27.908887 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 12:43:27.911554 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 12:43:27.918759 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4627 12:43:27.921966 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4628 12:43:27.925102 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 12:43:27.931725 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 12:43:27.934906 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 12:43:27.938770 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 12:43:27.944870 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 12:43:27.948637 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 12:43:27.951949 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 12:43:27.958002 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 12:43:27.961783 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 12:43:27.964891 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 12:43:27.971615 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 12:43:27.974836 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 12:43:27.978496 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 12:43:27.984780 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 12:43:27.988299 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 12:43:27.991573 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4644 12:43:27.994891 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4645 12:43:27.998807 Total UI for P1: 0, mck2ui 16
4646 12:43:28.002247 best dqsien dly found for B0: ( 0, 13, 12)
4647 12:43:28.004918 Total UI for P1: 0, mck2ui 16
4648 12:43:28.008295 best dqsien dly found for B1: ( 0, 13, 12)
4649 12:43:28.011531 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4650 12:43:28.018165 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4651 12:43:28.018666
4652 12:43:28.021466 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4653 12:43:28.025291 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4654 12:43:28.028553 [Gating] SW calibration Done
4655 12:43:28.029066 ==
4656 12:43:28.031838 Dram Type= 6, Freq= 0, CH_1, rank 1
4657 12:43:28.035087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4658 12:43:28.035557 ==
4659 12:43:28.035982 RX Vref Scan: 0
4660 12:43:28.038068
4661 12:43:28.038491 RX Vref 0 -> 0, step: 1
4662 12:43:28.038840
4663 12:43:28.041276 RX Delay -230 -> 252, step: 16
4664 12:43:28.044994 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4665 12:43:28.052000 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4666 12:43:28.054988 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4667 12:43:28.058304 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4668 12:43:28.061174 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4669 12:43:28.065066 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4670 12:43:28.071214 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4671 12:43:28.074975 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4672 12:43:28.078298 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4673 12:43:28.081525 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4674 12:43:28.088620 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4675 12:43:28.091665 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4676 12:43:28.094965 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4677 12:43:28.098304 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4678 12:43:28.101399 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4679 12:43:28.108028 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4680 12:43:28.108454 ==
4681 12:43:28.111351 Dram Type= 6, Freq= 0, CH_1, rank 1
4682 12:43:28.114802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4683 12:43:28.115232 ==
4684 12:43:28.115692 DQS Delay:
4685 12:43:28.118004 DQS0 = 0, DQS1 = 0
4686 12:43:28.118430 DQM Delay:
4687 12:43:28.121364 DQM0 = 48, DQM1 = 48
4688 12:43:28.121810 DQ Delay:
4689 12:43:28.124496 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =49
4690 12:43:28.127888 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4691 12:43:28.131109 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4692 12:43:28.134533 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4693 12:43:28.134958
4694 12:43:28.135289
4695 12:43:28.135606 ==
4696 12:43:28.138083 Dram Type= 6, Freq= 0, CH_1, rank 1
4697 12:43:28.141293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4698 12:43:28.144986 ==
4699 12:43:28.145422
4700 12:43:28.145757
4701 12:43:28.146065 TX Vref Scan disable
4702 12:43:28.148071 == TX Byte 0 ==
4703 12:43:28.151362 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4704 12:43:28.154710 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4705 12:43:28.158293 == TX Byte 1 ==
4706 12:43:28.161222 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4707 12:43:28.164235 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4708 12:43:28.168220 ==
4709 12:43:28.171398 Dram Type= 6, Freq= 0, CH_1, rank 1
4710 12:43:28.174269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4711 12:43:28.174742 ==
4712 12:43:28.175097
4713 12:43:28.175511
4714 12:43:28.178031 TX Vref Scan disable
4715 12:43:28.178494 == TX Byte 0 ==
4716 12:43:28.184416 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4717 12:43:28.188404 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4718 12:43:28.188859 == TX Byte 1 ==
4719 12:43:28.194590 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4720 12:43:28.197920 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4721 12:43:28.198342
4722 12:43:28.198675 [DATLAT]
4723 12:43:28.201106 Freq=600, CH1 RK1
4724 12:43:28.201528
4725 12:43:28.201862 DATLAT Default: 0x9
4726 12:43:28.204325 0, 0xFFFF, sum = 0
4727 12:43:28.204749 1, 0xFFFF, sum = 0
4728 12:43:28.207592 2, 0xFFFF, sum = 0
4729 12:43:28.208043 3, 0xFFFF, sum = 0
4730 12:43:28.211003 4, 0xFFFF, sum = 0
4731 12:43:28.211455 5, 0xFFFF, sum = 0
4732 12:43:28.214657 6, 0xFFFF, sum = 0
4733 12:43:28.218020 7, 0xFFFF, sum = 0
4734 12:43:28.218585 8, 0x0, sum = 1
4735 12:43:28.219077 9, 0x0, sum = 2
4736 12:43:28.220738 10, 0x0, sum = 3
4737 12:43:28.221166 11, 0x0, sum = 4
4738 12:43:28.224681 best_step = 9
4739 12:43:28.225127
4740 12:43:28.225447 ==
4741 12:43:28.228023 Dram Type= 6, Freq= 0, CH_1, rank 1
4742 12:43:28.231104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4743 12:43:28.231705 ==
4744 12:43:28.234366 RX Vref Scan: 0
4745 12:43:28.234994
4746 12:43:28.235502 RX Vref 0 -> 0, step: 1
4747 12:43:28.236028
4748 12:43:28.237791 RX Delay -163 -> 252, step: 8
4749 12:43:28.244420 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4750 12:43:28.248224 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4751 12:43:28.251312 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4752 12:43:28.254993 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4753 12:43:28.258229 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4754 12:43:28.264518 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4755 12:43:28.268027 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4756 12:43:28.271241 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4757 12:43:28.274404 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4758 12:43:28.278159 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4759 12:43:28.284872 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4760 12:43:28.288177 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4761 12:43:28.291410 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4762 12:43:28.294741 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4763 12:43:28.301632 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4764 12:43:28.304799 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4765 12:43:28.305267 ==
4766 12:43:28.308252 Dram Type= 6, Freq= 0, CH_1, rank 1
4767 12:43:28.312112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4768 12:43:28.312569 ==
4769 12:43:28.312950 DQS Delay:
4770 12:43:28.315190 DQS0 = 0, DQS1 = 0
4771 12:43:28.315641 DQM Delay:
4772 12:43:28.318462 DQM0 = 49, DQM1 = 46
4773 12:43:28.318966 DQ Delay:
4774 12:43:28.321903 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4775 12:43:28.324493 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4776 12:43:28.327658 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4777 12:43:28.331557 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4778 12:43:28.331997
4779 12:43:28.332352
4780 12:43:28.341424 [DQSOSCAuto] RK1, (LSB)MR18= 0x671f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
4781 12:43:28.341910 CH1 RK1: MR19=808, MR18=671F
4782 12:43:28.348178 CH1_RK1: MR19=0x808, MR18=0x671F, DQSOSC=390, MR23=63, INC=172, DEC=114
4783 12:43:28.351317 [RxdqsGatingPostProcess] freq 600
4784 12:43:28.358434 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4785 12:43:28.361359 Pre-setting of DQS Precalculation
4786 12:43:28.364481 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4787 12:43:28.370966 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4788 12:43:28.377793 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4789 12:43:28.381521
4790 12:43:28.381985
4791 12:43:28.382446 [Calibration Summary] 1200 Mbps
4792 12:43:28.384673 CH 0, Rank 0
4793 12:43:28.385277 SW Impedance : PASS
4794 12:43:28.387735 DUTY Scan : NO K
4795 12:43:28.391470 ZQ Calibration : PASS
4796 12:43:28.391942 Jitter Meter : NO K
4797 12:43:28.394567 CBT Training : PASS
4798 12:43:28.398011 Write leveling : PASS
4799 12:43:28.398504 RX DQS gating : PASS
4800 12:43:28.401155 RX DQ/DQS(RDDQC) : PASS
4801 12:43:28.404893 TX DQ/DQS : PASS
4802 12:43:28.405464 RX DATLAT : PASS
4803 12:43:28.408089 RX DQ/DQS(Engine): PASS
4804 12:43:28.411292 TX OE : NO K
4805 12:43:28.411775 All Pass.
4806 12:43:28.412110
4807 12:43:28.412458 CH 0, Rank 1
4808 12:43:28.414482 SW Impedance : PASS
4809 12:43:28.417780 DUTY Scan : NO K
4810 12:43:28.418195 ZQ Calibration : PASS
4811 12:43:28.421127 Jitter Meter : NO K
4812 12:43:28.424202 CBT Training : PASS
4813 12:43:28.424657 Write leveling : PASS
4814 12:43:28.428146 RX DQS gating : PASS
4815 12:43:28.428602 RX DQ/DQS(RDDQC) : PASS
4816 12:43:28.431450 TX DQ/DQS : PASS
4817 12:43:28.434169 RX DATLAT : PASS
4818 12:43:28.434653 RX DQ/DQS(Engine): PASS
4819 12:43:28.438065 TX OE : NO K
4820 12:43:28.438613 All Pass.
4821 12:43:28.439143
4822 12:43:28.441317 CH 1, Rank 0
4823 12:43:28.441809 SW Impedance : PASS
4824 12:43:28.444125 DUTY Scan : NO K
4825 12:43:28.447571 ZQ Calibration : PASS
4826 12:43:28.448078 Jitter Meter : NO K
4827 12:43:28.450948 CBT Training : PASS
4828 12:43:28.454236 Write leveling : PASS
4829 12:43:28.454706 RX DQS gating : PASS
4830 12:43:28.457403 RX DQ/DQS(RDDQC) : PASS
4831 12:43:28.460954 TX DQ/DQS : PASS
4832 12:43:28.461412 RX DATLAT : PASS
4833 12:43:28.464224 RX DQ/DQS(Engine): PASS
4834 12:43:28.467778 TX OE : NO K
4835 12:43:28.468206 All Pass.
4836 12:43:28.468654
4837 12:43:28.469277 CH 1, Rank 1
4838 12:43:28.470840 SW Impedance : PASS
4839 12:43:28.474020 DUTY Scan : NO K
4840 12:43:28.474624 ZQ Calibration : PASS
4841 12:43:28.477794 Jitter Meter : NO K
4842 12:43:28.478265 CBT Training : PASS
4843 12:43:28.480761 Write leveling : PASS
4844 12:43:28.484446 RX DQS gating : PASS
4845 12:43:28.484989 RX DQ/DQS(RDDQC) : PASS
4846 12:43:28.487562 TX DQ/DQS : PASS
4847 12:43:28.490727 RX DATLAT : PASS
4848 12:43:28.491317 RX DQ/DQS(Engine): PASS
4849 12:43:28.494284 TX OE : NO K
4850 12:43:28.494739 All Pass.
4851 12:43:28.495227
4852 12:43:28.497367 DramC Write-DBI off
4853 12:43:28.500585 PER_BANK_REFRESH: Hybrid Mode
4854 12:43:28.501114 TX_TRACKING: ON
4855 12:43:28.510685 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4856 12:43:28.513981 [FAST_K] Save calibration result to emmc
4857 12:43:28.517152 dramc_set_vcore_voltage set vcore to 662500
4858 12:43:28.520899 Read voltage for 933, 3
4859 12:43:28.521325 Vio18 = 0
4860 12:43:28.521658 Vcore = 662500
4861 12:43:28.524066 Vdram = 0
4862 12:43:28.524489 Vddq = 0
4863 12:43:28.524861 Vmddr = 0
4864 12:43:28.530628 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4865 12:43:28.534139 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4866 12:43:28.537388 MEM_TYPE=3, freq_sel=17
4867 12:43:28.540934 sv_algorithm_assistance_LP4_1600
4868 12:43:28.543985 ============ PULL DRAM RESETB DOWN ============
4869 12:43:28.547253 ========== PULL DRAM RESETB DOWN end =========
4870 12:43:28.553783 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4871 12:43:28.557138 ===================================
4872 12:43:28.560332 LPDDR4 DRAM CONFIGURATION
4873 12:43:28.563760 ===================================
4874 12:43:28.564187 EX_ROW_EN[0] = 0x0
4875 12:43:28.567117 EX_ROW_EN[1] = 0x0
4876 12:43:28.567563 LP4Y_EN = 0x0
4877 12:43:28.570414 WORK_FSP = 0x0
4878 12:43:28.570840 WL = 0x3
4879 12:43:28.573624 RL = 0x3
4880 12:43:28.574047 BL = 0x2
4881 12:43:28.576892 RPST = 0x0
4882 12:43:28.577324 RD_PRE = 0x0
4883 12:43:28.580697 WR_PRE = 0x1
4884 12:43:28.581165 WR_PST = 0x0
4885 12:43:28.583917 DBI_WR = 0x0
4886 12:43:28.584358 DBI_RD = 0x0
4887 12:43:28.587225 OTF = 0x1
4888 12:43:28.590725 ===================================
4889 12:43:28.593761 ===================================
4890 12:43:28.594180 ANA top config
4891 12:43:28.596949 ===================================
4892 12:43:28.600582 DLL_ASYNC_EN = 0
4893 12:43:28.603438 ALL_SLAVE_EN = 1
4894 12:43:28.607240 NEW_RANK_MODE = 1
4895 12:43:28.607678 DLL_IDLE_MODE = 1
4896 12:43:28.610358 LP45_APHY_COMB_EN = 1
4897 12:43:28.613752 TX_ODT_DIS = 1
4898 12:43:28.617414 NEW_8X_MODE = 1
4899 12:43:28.620427 ===================================
4900 12:43:28.623558 ===================================
4901 12:43:28.627152 data_rate = 1866
4902 12:43:28.627574 CKR = 1
4903 12:43:28.630427 DQ_P2S_RATIO = 8
4904 12:43:28.633736 ===================================
4905 12:43:28.637156 CA_P2S_RATIO = 8
4906 12:43:28.640564 DQ_CA_OPEN = 0
4907 12:43:28.643934 DQ_SEMI_OPEN = 0
4908 12:43:28.647364 CA_SEMI_OPEN = 0
4909 12:43:28.647791 CA_FULL_RATE = 0
4910 12:43:28.650491 DQ_CKDIV4_EN = 1
4911 12:43:28.653817 CA_CKDIV4_EN = 1
4912 12:43:28.657063 CA_PREDIV_EN = 0
4913 12:43:28.660315 PH8_DLY = 0
4914 12:43:28.663720 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4915 12:43:28.664163 DQ_AAMCK_DIV = 4
4916 12:43:28.666996 CA_AAMCK_DIV = 4
4917 12:43:28.670342 CA_ADMCK_DIV = 4
4918 12:43:28.673777 DQ_TRACK_CA_EN = 0
4919 12:43:28.676960 CA_PICK = 933
4920 12:43:28.680195 CA_MCKIO = 933
4921 12:43:28.680787 MCKIO_SEMI = 0
4922 12:43:28.683310 PLL_FREQ = 3732
4923 12:43:28.686788 DQ_UI_PI_RATIO = 32
4924 12:43:28.690536 CA_UI_PI_RATIO = 0
4925 12:43:28.693827 ===================================
4926 12:43:28.696777 ===================================
4927 12:43:28.700707 memory_type:LPDDR4
4928 12:43:28.701192 GP_NUM : 10
4929 12:43:28.703544 SRAM_EN : 1
4930 12:43:28.706670 MD32_EN : 0
4931 12:43:28.710300 ===================================
4932 12:43:28.710734 [ANA_INIT] >>>>>>>>>>>>>>
4933 12:43:28.713482 <<<<<< [CONFIGURE PHASE]: ANA_TX
4934 12:43:28.716878 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4935 12:43:28.719837 ===================================
4936 12:43:28.723712 data_rate = 1866,PCW = 0X8f00
4937 12:43:28.726986 ===================================
4938 12:43:28.730027 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4939 12:43:28.736772 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4940 12:43:28.740070 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4941 12:43:28.746769 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4942 12:43:28.750156 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4943 12:43:28.753211 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4944 12:43:28.753633 [ANA_INIT] flow start
4945 12:43:28.756471 [ANA_INIT] PLL >>>>>>>>
4946 12:43:28.759921 [ANA_INIT] PLL <<<<<<<<
4947 12:43:28.763048 [ANA_INIT] MIDPI >>>>>>>>
4948 12:43:28.763513 [ANA_INIT] MIDPI <<<<<<<<
4949 12:43:28.766460 [ANA_INIT] DLL >>>>>>>>
4950 12:43:28.770051 [ANA_INIT] flow end
4951 12:43:28.773268 ============ LP4 DIFF to SE enter ============
4952 12:43:28.776616 ============ LP4 DIFF to SE exit ============
4953 12:43:28.779313 [ANA_INIT] <<<<<<<<<<<<<
4954 12:43:28.783252 [Flow] Enable top DCM control >>>>>
4955 12:43:28.786598 [Flow] Enable top DCM control <<<<<
4956 12:43:28.788918 Enable DLL master slave shuffle
4957 12:43:28.793087 ==============================================================
4958 12:43:28.795937 Gating Mode config
4959 12:43:28.802763 ==============================================================
4960 12:43:28.803277 Config description:
4961 12:43:28.812632 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4962 12:43:28.819253 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4963 12:43:28.822568 SELPH_MODE 0: By rank 1: By Phase
4964 12:43:28.829521 ==============================================================
4965 12:43:28.832590 GAT_TRACK_EN = 1
4966 12:43:28.835724 RX_GATING_MODE = 2
4967 12:43:28.839601 RX_GATING_TRACK_MODE = 2
4968 12:43:28.842721 SELPH_MODE = 1
4969 12:43:28.846017 PICG_EARLY_EN = 1
4970 12:43:28.849258 VALID_LAT_VALUE = 1
4971 12:43:28.852566 ==============================================================
4972 12:43:28.855762 Enter into Gating configuration >>>>
4973 12:43:28.858910 Exit from Gating configuration <<<<
4974 12:43:28.862785 Enter into DVFS_PRE_config >>>>>
4975 12:43:28.875830 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4976 12:43:28.876343 Exit from DVFS_PRE_config <<<<<
4977 12:43:28.879066 Enter into PICG configuration >>>>
4978 12:43:28.882375 Exit from PICG configuration <<<<
4979 12:43:28.885846 [RX_INPUT] configuration >>>>>
4980 12:43:28.889265 [RX_INPUT] configuration <<<<<
4981 12:43:28.895536 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4982 12:43:28.898795 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4983 12:43:28.905591 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4984 12:43:28.912393 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4985 12:43:28.919188 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4986 12:43:28.925627 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4987 12:43:28.928751 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4988 12:43:28.932423 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4989 12:43:28.935544 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4990 12:43:28.942000 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4991 12:43:28.945296 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4992 12:43:28.948877 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4993 12:43:28.952149 ===================================
4994 12:43:28.955398 LPDDR4 DRAM CONFIGURATION
4995 12:43:28.958820 ===================================
4996 12:43:28.959469 EX_ROW_EN[0] = 0x0
4997 12:43:28.962122 EX_ROW_EN[1] = 0x0
4998 12:43:28.965714 LP4Y_EN = 0x0
4999 12:43:28.966155 WORK_FSP = 0x0
5000 12:43:28.969110 WL = 0x3
5001 12:43:28.969638 RL = 0x3
5002 12:43:28.972551 BL = 0x2
5003 12:43:28.973050 RPST = 0x0
5004 12:43:28.975803 RD_PRE = 0x0
5005 12:43:28.976257 WR_PRE = 0x1
5006 12:43:28.979013 WR_PST = 0x0
5007 12:43:28.979439 DBI_WR = 0x0
5008 12:43:28.982382 DBI_RD = 0x0
5009 12:43:28.982857 OTF = 0x1
5010 12:43:28.985738 ===================================
5011 12:43:28.989061 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5012 12:43:28.995529 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5013 12:43:28.998824 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5014 12:43:29.002042 ===================================
5015 12:43:29.005584 LPDDR4 DRAM CONFIGURATION
5016 12:43:29.008889 ===================================
5017 12:43:29.009381 EX_ROW_EN[0] = 0x10
5018 12:43:29.012118 EX_ROW_EN[1] = 0x0
5019 12:43:29.012535 LP4Y_EN = 0x0
5020 12:43:29.015452 WORK_FSP = 0x0
5021 12:43:29.016019 WL = 0x3
5022 12:43:29.018567 RL = 0x3
5023 12:43:29.019031 BL = 0x2
5024 12:43:29.022048 RPST = 0x0
5025 12:43:29.025063 RD_PRE = 0x0
5026 12:43:29.025541 WR_PRE = 0x1
5027 12:43:29.028929 WR_PST = 0x0
5028 12:43:29.029392 DBI_WR = 0x0
5029 12:43:29.031866 DBI_RD = 0x0
5030 12:43:29.032342 OTF = 0x1
5031 12:43:29.035216 ===================================
5032 12:43:29.041958 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5033 12:43:29.045599 nWR fixed to 30
5034 12:43:29.048693 [ModeRegInit_LP4] CH0 RK0
5035 12:43:29.049165 [ModeRegInit_LP4] CH0 RK1
5036 12:43:29.052047 [ModeRegInit_LP4] CH1 RK0
5037 12:43:29.055691 [ModeRegInit_LP4] CH1 RK1
5038 12:43:29.056248 match AC timing 9
5039 12:43:29.062660 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5040 12:43:29.065760 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5041 12:43:29.069042 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5042 12:43:29.075591 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5043 12:43:29.078925 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5044 12:43:29.079363 ==
5045 12:43:29.082206 Dram Type= 6, Freq= 0, CH_0, rank 0
5046 12:43:29.085436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5047 12:43:29.085859 ==
5048 12:43:29.091922 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5049 12:43:29.098905 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5050 12:43:29.102018 [CA 0] Center 37 (6~68) winsize 63
5051 12:43:29.105209 [CA 1] Center 37 (6~68) winsize 63
5052 12:43:29.108590 [CA 2] Center 34 (4~65) winsize 62
5053 12:43:29.111840 [CA 3] Center 34 (3~65) winsize 63
5054 12:43:29.115220 [CA 4] Center 33 (2~64) winsize 63
5055 12:43:29.118665 [CA 5] Center 32 (2~62) winsize 61
5056 12:43:29.119167
5057 12:43:29.121763 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5058 12:43:29.122184
5059 12:43:29.125206 [CATrainingPosCal] consider 1 rank data
5060 12:43:29.128635 u2DelayCellTimex100 = 270/100 ps
5061 12:43:29.131712 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5062 12:43:29.135498 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5063 12:43:29.138378 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5064 12:43:29.142139 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5065 12:43:29.145172 CA4 delay=33 (2~64),Diff = 1 PI (6 cell)
5066 12:43:29.152082 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5067 12:43:29.152664
5068 12:43:29.155075 CA PerBit enable=1, Macro0, CA PI delay=32
5069 12:43:29.155526
5070 12:43:29.158476 [CBTSetCACLKResult] CA Dly = 32
5071 12:43:29.158898 CS Dly: 5 (0~36)
5072 12:43:29.159230 ==
5073 12:43:29.162231 Dram Type= 6, Freq= 0, CH_0, rank 1
5074 12:43:29.165222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5075 12:43:29.165653 ==
5076 12:43:29.172056 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5077 12:43:29.178205 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5078 12:43:29.181527 [CA 0] Center 37 (7~68) winsize 62
5079 12:43:29.184777 [CA 1] Center 37 (6~68) winsize 63
5080 12:43:29.188071 [CA 2] Center 34 (4~65) winsize 62
5081 12:43:29.191543 [CA 3] Center 34 (3~65) winsize 63
5082 12:43:29.194725 [CA 4] Center 33 (3~63) winsize 61
5083 12:43:29.198261 [CA 5] Center 32 (2~62) winsize 61
5084 12:43:29.198682
5085 12:43:29.201679 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5086 12:43:29.202127
5087 12:43:29.205071 [CATrainingPosCal] consider 2 rank data
5088 12:43:29.208772 u2DelayCellTimex100 = 270/100 ps
5089 12:43:29.211351 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5090 12:43:29.214913 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5091 12:43:29.217984 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5092 12:43:29.221311 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5093 12:43:29.227807 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5094 12:43:29.231282 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5095 12:43:29.231734
5096 12:43:29.235078 CA PerBit enable=1, Macro0, CA PI delay=32
5097 12:43:29.235475
5098 12:43:29.238409 [CBTSetCACLKResult] CA Dly = 32
5099 12:43:29.238902 CS Dly: 5 (0~37)
5100 12:43:29.239360
5101 12:43:29.241642 ----->DramcWriteLeveling(PI) begin...
5102 12:43:29.242075 ==
5103 12:43:29.244907 Dram Type= 6, Freq= 0, CH_0, rank 0
5104 12:43:29.251465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5105 12:43:29.251906 ==
5106 12:43:29.254578 Write leveling (Byte 0): 33 => 33
5107 12:43:29.258319 Write leveling (Byte 1): 30 => 30
5108 12:43:29.258795 DramcWriteLeveling(PI) end<-----
5109 12:43:29.259134
5110 12:43:29.261331 ==
5111 12:43:29.264518 Dram Type= 6, Freq= 0, CH_0, rank 0
5112 12:43:29.267753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5113 12:43:29.268245 ==
5114 12:43:29.271621 [Gating] SW mode calibration
5115 12:43:29.277861 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5116 12:43:29.281488 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5117 12:43:29.288364 0 14 0 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
5118 12:43:29.291656 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5119 12:43:29.294374 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5120 12:43:29.301185 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5121 12:43:29.304404 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5122 12:43:29.307907 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5123 12:43:29.314882 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5124 12:43:29.318401 0 14 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
5125 12:43:29.321050 0 15 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
5126 12:43:29.328190 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5127 12:43:29.331316 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5128 12:43:29.334710 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 12:43:29.341435 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 12:43:29.344670 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5131 12:43:29.348127 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5132 12:43:29.351121 0 15 28 | B1->B0 | 2525 3e3e | 0 0 | (0 0) (0 0)
5133 12:43:29.357894 1 0 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5134 12:43:29.361029 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 12:43:29.364673 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 12:43:29.370783 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 12:43:29.374825 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 12:43:29.377896 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 12:43:29.384477 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5140 12:43:29.388203 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5141 12:43:29.391215 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5142 12:43:29.397746 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 12:43:29.401082 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 12:43:29.404484 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 12:43:29.411089 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 12:43:29.414413 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 12:43:29.417485 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 12:43:29.424238 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 12:43:29.428140 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 12:43:29.431584 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 12:43:29.438105 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 12:43:29.441292 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 12:43:29.444659 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 12:43:29.451194 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 12:43:29.454440 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5156 12:43:29.457790 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5157 12:43:29.461112 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5158 12:43:29.464682 Total UI for P1: 0, mck2ui 16
5159 12:43:29.467841 best dqsien dly found for B0: ( 1, 2, 26)
5160 12:43:29.471172 Total UI for P1: 0, mck2ui 16
5161 12:43:29.474197 best dqsien dly found for B1: ( 1, 2, 30)
5162 12:43:29.477557 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5163 12:43:29.480797 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5164 12:43:29.483791
5165 12:43:29.487820 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5166 12:43:29.490917 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5167 12:43:29.494070 [Gating] SW calibration Done
5168 12:43:29.494192 ==
5169 12:43:29.497115 Dram Type= 6, Freq= 0, CH_0, rank 0
5170 12:43:29.500747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5171 12:43:29.500913 ==
5172 12:43:29.501022 RX Vref Scan: 0
5173 12:43:29.503840
5174 12:43:29.503995 RX Vref 0 -> 0, step: 1
5175 12:43:29.504114
5176 12:43:29.507026 RX Delay -80 -> 252, step: 8
5177 12:43:29.510988 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5178 12:43:29.513897 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5179 12:43:29.520700 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5180 12:43:29.524010 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5181 12:43:29.527412 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5182 12:43:29.530590 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5183 12:43:29.533984 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5184 12:43:29.537275 iDelay=208, Bit 7, Center 119 (32 ~ 207) 176
5185 12:43:29.543766 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5186 12:43:29.547341 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5187 12:43:29.550687 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5188 12:43:29.554023 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5189 12:43:29.557307 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5190 12:43:29.560531 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5191 12:43:29.567101 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5192 12:43:29.570277 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5193 12:43:29.570355 ==
5194 12:43:29.573856 Dram Type= 6, Freq= 0, CH_0, rank 0
5195 12:43:29.576777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5196 12:43:29.576894 ==
5197 12:43:29.580444 DQS Delay:
5198 12:43:29.580514 DQS0 = 0, DQS1 = 0
5199 12:43:29.580574 DQM Delay:
5200 12:43:29.583529 DQM0 = 105, DQM1 = 95
5201 12:43:29.583612 DQ Delay:
5202 12:43:29.587295 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5203 12:43:29.590464 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =119
5204 12:43:29.594171 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5205 12:43:29.597195 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5206 12:43:29.597266
5207 12:43:29.597326
5208 12:43:29.600309 ==
5209 12:43:29.600409 Dram Type= 6, Freq= 0, CH_0, rank 0
5210 12:43:29.607059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5211 12:43:29.607162 ==
5212 12:43:29.607253
5213 12:43:29.607339
5214 12:43:29.610301 TX Vref Scan disable
5215 12:43:29.610377 == TX Byte 0 ==
5216 12:43:29.614008 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5217 12:43:29.620433 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5218 12:43:29.620523 == TX Byte 1 ==
5219 12:43:29.623672 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5220 12:43:29.630301 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5221 12:43:29.630383 ==
5222 12:43:29.633615 Dram Type= 6, Freq= 0, CH_0, rank 0
5223 12:43:29.637011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5224 12:43:29.637089 ==
5225 12:43:29.637153
5226 12:43:29.637213
5227 12:43:29.640462 TX Vref Scan disable
5228 12:43:29.643706 == TX Byte 0 ==
5229 12:43:29.647050 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5230 12:43:29.650278 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5231 12:43:29.653588 == TX Byte 1 ==
5232 12:43:29.657000 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5233 12:43:29.660102 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5234 12:43:29.660200
5235 12:43:29.660283 [DATLAT]
5236 12:43:29.663274 Freq=933, CH0 RK0
5237 12:43:29.663344
5238 12:43:29.666742 DATLAT Default: 0xd
5239 12:43:29.666811 0, 0xFFFF, sum = 0
5240 12:43:29.670071 1, 0xFFFF, sum = 0
5241 12:43:29.670141 2, 0xFFFF, sum = 0
5242 12:43:29.673464 3, 0xFFFF, sum = 0
5243 12:43:29.673532 4, 0xFFFF, sum = 0
5244 12:43:29.676649 5, 0xFFFF, sum = 0
5245 12:43:29.676718 6, 0xFFFF, sum = 0
5246 12:43:29.680364 7, 0xFFFF, sum = 0
5247 12:43:29.680433 8, 0xFFFF, sum = 0
5248 12:43:29.683357 9, 0xFFFF, sum = 0
5249 12:43:29.683442 10, 0x0, sum = 1
5250 12:43:29.686422 11, 0x0, sum = 2
5251 12:43:29.686521 12, 0x0, sum = 3
5252 12:43:29.690231 13, 0x0, sum = 4
5253 12:43:29.690428 best_step = 11
5254 12:43:29.690512
5255 12:43:29.690572 ==
5256 12:43:29.693303 Dram Type= 6, Freq= 0, CH_0, rank 0
5257 12:43:29.696936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5258 12:43:29.697023 ==
5259 12:43:29.700146 RX Vref Scan: 1
5260 12:43:29.700221
5261 12:43:29.703350 RX Vref 0 -> 0, step: 1
5262 12:43:29.703420
5263 12:43:29.703478 RX Delay -53 -> 252, step: 4
5264 12:43:29.703535
5265 12:43:29.706560 Set Vref, RX VrefLevel [Byte0]: 55
5266 12:43:29.709622 [Byte1]: 55
5267 12:43:29.714602
5268 12:43:29.714674 Final RX Vref Byte 0 = 55 to rank0
5269 12:43:29.718173 Final RX Vref Byte 1 = 55 to rank0
5270 12:43:29.721464 Final RX Vref Byte 0 = 55 to rank1
5271 12:43:29.724617 Final RX Vref Byte 1 = 55 to rank1==
5272 12:43:29.728315 Dram Type= 6, Freq= 0, CH_0, rank 0
5273 12:43:29.734875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5274 12:43:29.734959 ==
5275 12:43:29.735024 DQS Delay:
5276 12:43:29.735084 DQS0 = 0, DQS1 = 0
5277 12:43:29.738158 DQM Delay:
5278 12:43:29.738239 DQM0 = 105, DQM1 = 97
5279 12:43:29.741494 DQ Delay:
5280 12:43:29.744924 DQ0 =104, DQ1 =106, DQ2 =104, DQ3 =102
5281 12:43:29.748180 DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =110
5282 12:43:29.751410 DQ8 =88, DQ9 =88, DQ10 =96, DQ11 =92
5283 12:43:29.754723 DQ12 =102, DQ13 =102, DQ14 =106, DQ15 =104
5284 12:43:29.754805
5285 12:43:29.754870
5286 12:43:29.761509 [DQSOSCAuto] RK0, (LSB)MR18= 0x3229, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5287 12:43:29.764573 CH0 RK0: MR19=505, MR18=3229
5288 12:43:29.771185 CH0_RK0: MR19=0x505, MR18=0x3229, DQSOSC=406, MR23=63, INC=65, DEC=43
5289 12:43:29.771268
5290 12:43:29.774392 ----->DramcWriteLeveling(PI) begin...
5291 12:43:29.774503 ==
5292 12:43:29.777753 Dram Type= 6, Freq= 0, CH_0, rank 1
5293 12:43:29.781141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 12:43:29.781228 ==
5295 12:43:29.784478 Write leveling (Byte 0): 32 => 32
5296 12:43:29.788151 Write leveling (Byte 1): 29 => 29
5297 12:43:29.791379 DramcWriteLeveling(PI) end<-----
5298 12:43:29.791471
5299 12:43:29.791542 ==
5300 12:43:29.794484 Dram Type= 6, Freq= 0, CH_0, rank 1
5301 12:43:29.801274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5302 12:43:29.801376 ==
5303 12:43:29.801456 [Gating] SW mode calibration
5304 12:43:29.811183 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5305 12:43:29.814241 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5306 12:43:29.817567 0 14 0 | B1->B0 | 3434 3131 | 0 0 | (0 0) (0 0)
5307 12:43:29.824509 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5308 12:43:29.827503 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5309 12:43:29.831309 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5310 12:43:29.837559 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5311 12:43:29.840813 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5312 12:43:29.847547 0 14 24 | B1->B0 | 3333 3333 | 1 1 | (1 1) (1 1)
5313 12:43:29.850849 0 14 28 | B1->B0 | 2d2d 2c2c | 0 0 | (1 0) (1 0)
5314 12:43:29.854019 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5315 12:43:29.857381 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5316 12:43:29.864130 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5317 12:43:29.867548 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5318 12:43:29.870523 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 12:43:29.877428 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5320 12:43:29.880750 0 15 24 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
5321 12:43:29.884057 0 15 28 | B1->B0 | 3a3a 3938 | 0 1 | (0 0) (0 0)
5322 12:43:29.890853 1 0 0 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
5323 12:43:29.893995 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5324 12:43:29.897811 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 12:43:29.903907 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 12:43:29.907468 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 12:43:29.910716 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 12:43:29.917141 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5329 12:43:29.920507 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5330 12:43:29.924072 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 12:43:29.930393 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 12:43:29.933879 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 12:43:29.937046 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 12:43:29.943828 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 12:43:29.946897 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 12:43:29.950657 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 12:43:29.956966 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 12:43:29.960359 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 12:43:29.963672 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 12:43:29.970351 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 12:43:29.974164 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 12:43:29.977334 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 12:43:29.984006 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 12:43:29.987332 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 12:43:29.990636 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5346 12:43:29.993979 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5347 12:43:29.997167 Total UI for P1: 0, mck2ui 16
5348 12:43:30.000553 best dqsien dly found for B1: ( 1, 2, 28)
5349 12:43:30.006786 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5350 12:43:30.010518 Total UI for P1: 0, mck2ui 16
5351 12:43:30.013655 best dqsien dly found for B0: ( 1, 2, 30)
5352 12:43:30.016685 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5353 12:43:30.020521 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5354 12:43:30.020694
5355 12:43:30.023616 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5356 12:43:30.026877 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5357 12:43:30.030567 [Gating] SW calibration Done
5358 12:43:30.030742 ==
5359 12:43:30.033710 Dram Type= 6, Freq= 0, CH_0, rank 1
5360 12:43:30.036870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5361 12:43:30.037069 ==
5362 12:43:30.039826 RX Vref Scan: 0
5363 12:43:30.040001
5364 12:43:30.040139 RX Vref 0 -> 0, step: 1
5365 12:43:30.043792
5366 12:43:30.043966 RX Delay -80 -> 252, step: 8
5367 12:43:30.050140 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5368 12:43:30.053370 iDelay=208, Bit 1, Center 111 (24 ~ 199) 176
5369 12:43:30.057099 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5370 12:43:30.060284 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5371 12:43:30.063347 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5372 12:43:30.066796 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5373 12:43:30.073561 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5374 12:43:30.076682 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5375 12:43:30.080012 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5376 12:43:30.083138 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5377 12:43:30.086610 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5378 12:43:30.089837 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5379 12:43:30.096483 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5380 12:43:30.099845 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5381 12:43:30.103150 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5382 12:43:30.106483 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5383 12:43:30.106663 ==
5384 12:43:30.109578 Dram Type= 6, Freq= 0, CH_0, rank 1
5385 12:43:30.113488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5386 12:43:30.116639 ==
5387 12:43:30.116824 DQS Delay:
5388 12:43:30.116964 DQS0 = 0, DQS1 = 0
5389 12:43:30.119861 DQM Delay:
5390 12:43:30.120035 DQM0 = 105, DQM1 = 93
5391 12:43:30.122996 DQ Delay:
5392 12:43:30.126805 DQ0 =103, DQ1 =111, DQ2 =103, DQ3 =99
5393 12:43:30.129745 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5394 12:43:30.132932 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5395 12:43:30.136382 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5396 12:43:30.136557
5397 12:43:30.136694
5398 12:43:30.136841 ==
5399 12:43:30.140090 Dram Type= 6, Freq= 0, CH_0, rank 1
5400 12:43:30.143180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5401 12:43:30.143426 ==
5402 12:43:30.143620
5403 12:43:30.143800
5404 12:43:30.146208 TX Vref Scan disable
5405 12:43:30.146451 == TX Byte 0 ==
5406 12:43:30.153274 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5407 12:43:30.156475 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5408 12:43:30.156843 == TX Byte 1 ==
5409 12:43:30.163151 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5410 12:43:30.166574 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5411 12:43:30.166882 ==
5412 12:43:30.169961 Dram Type= 6, Freq= 0, CH_0, rank 1
5413 12:43:30.173302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5414 12:43:30.173675 ==
5415 12:43:30.173800
5416 12:43:30.173877
5417 12:43:30.176435 TX Vref Scan disable
5418 12:43:30.179843 == TX Byte 0 ==
5419 12:43:30.182840 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5420 12:43:30.186378 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5421 12:43:30.189596 == TX Byte 1 ==
5422 12:43:30.192949 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5423 12:43:30.196333 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5424 12:43:30.196411
5425 12:43:30.199675 [DATLAT]
5426 12:43:30.199751 Freq=933, CH0 RK1
5427 12:43:30.199837
5428 12:43:30.202882 DATLAT Default: 0xb
5429 12:43:30.202968 0, 0xFFFF, sum = 0
5430 12:43:30.206132 1, 0xFFFF, sum = 0
5431 12:43:30.206218 2, 0xFFFF, sum = 0
5432 12:43:30.209479 3, 0xFFFF, sum = 0
5433 12:43:30.209571 4, 0xFFFF, sum = 0
5434 12:43:30.212955 5, 0xFFFF, sum = 0
5435 12:43:30.213034 6, 0xFFFF, sum = 0
5436 12:43:30.216238 7, 0xFFFF, sum = 0
5437 12:43:30.216317 8, 0xFFFF, sum = 0
5438 12:43:30.219517 9, 0xFFFF, sum = 0
5439 12:43:30.219595 10, 0x0, sum = 1
5440 12:43:30.223138 11, 0x0, sum = 2
5441 12:43:30.223225 12, 0x0, sum = 3
5442 12:43:30.226137 13, 0x0, sum = 4
5443 12:43:30.226228 best_step = 11
5444 12:43:30.226309
5445 12:43:30.226394 ==
5446 12:43:30.229327 Dram Type= 6, Freq= 0, CH_0, rank 1
5447 12:43:30.236434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5448 12:43:30.236520 ==
5449 12:43:30.236610 RX Vref Scan: 0
5450 12:43:30.236707
5451 12:43:30.239552 RX Vref 0 -> 0, step: 1
5452 12:43:30.239641
5453 12:43:30.242730 RX Delay -53 -> 252, step: 4
5454 12:43:30.246167 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5455 12:43:30.252722 iDelay=199, Bit 1, Center 108 (23 ~ 194) 172
5456 12:43:30.255993 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5457 12:43:30.259259 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5458 12:43:30.263175 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5459 12:43:30.266347 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5460 12:43:30.269500 iDelay=199, Bit 6, Center 110 (23 ~ 198) 176
5461 12:43:30.276236 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5462 12:43:30.279705 iDelay=199, Bit 8, Center 88 (7 ~ 170) 164
5463 12:43:30.282991 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5464 12:43:30.286233 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5465 12:43:30.289395 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5466 12:43:30.296134 iDelay=199, Bit 12, Center 102 (19 ~ 186) 168
5467 12:43:30.299529 iDelay=199, Bit 13, Center 100 (15 ~ 186) 172
5468 12:43:30.302792 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5469 12:43:30.306156 iDelay=199, Bit 15, Center 104 (23 ~ 186) 164
5470 12:43:30.306237 ==
5471 12:43:30.309416 Dram Type= 6, Freq= 0, CH_0, rank 1
5472 12:43:30.312768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5473 12:43:30.316103 ==
5474 12:43:30.316186 DQS Delay:
5475 12:43:30.316252 DQS0 = 0, DQS1 = 0
5476 12:43:30.319438 DQM Delay:
5477 12:43:30.319521 DQM0 = 105, DQM1 = 96
5478 12:43:30.322841 DQ Delay:
5479 12:43:30.326050 DQ0 =102, DQ1 =108, DQ2 =102, DQ3 =102
5480 12:43:30.329177 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5481 12:43:30.332366 DQ8 =88, DQ9 =86, DQ10 =94, DQ11 =92
5482 12:43:30.336046 DQ12 =102, DQ13 =100, DQ14 =104, DQ15 =104
5483 12:43:30.336154
5484 12:43:30.336247
5485 12:43:30.342803 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d05, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 407 ps
5486 12:43:30.345958 CH0 RK1: MR19=505, MR18=2D05
5487 12:43:30.352922 CH0_RK1: MR19=0x505, MR18=0x2D05, DQSOSC=407, MR23=63, INC=65, DEC=43
5488 12:43:30.356027 [RxdqsGatingPostProcess] freq 933
5489 12:43:30.359688 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5490 12:43:30.362723 best DQS0 dly(2T, 0.5T) = (0, 10)
5491 12:43:30.365841 best DQS1 dly(2T, 0.5T) = (0, 10)
5492 12:43:30.369496 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5493 12:43:30.372642 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5494 12:43:30.375966 best DQS0 dly(2T, 0.5T) = (0, 10)
5495 12:43:30.379110 best DQS1 dly(2T, 0.5T) = (0, 10)
5496 12:43:30.382815 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5497 12:43:30.385922 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5498 12:43:30.389026 Pre-setting of DQS Precalculation
5499 12:43:30.392975 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5500 12:43:30.395597 ==
5501 12:43:30.398993 Dram Type= 6, Freq= 0, CH_1, rank 0
5502 12:43:30.402897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5503 12:43:30.402998 ==
5504 12:43:30.406056 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5505 12:43:30.412605 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5506 12:43:30.416011 [CA 0] Center 36 (6~67) winsize 62
5507 12:43:30.419376 [CA 1] Center 36 (6~67) winsize 62
5508 12:43:30.422670 [CA 2] Center 34 (4~65) winsize 62
5509 12:43:30.426082 [CA 3] Center 34 (4~65) winsize 62
5510 12:43:30.429421 [CA 4] Center 34 (4~65) winsize 62
5511 12:43:30.432585 [CA 5] Center 33 (3~64) winsize 62
5512 12:43:30.432688
5513 12:43:30.435946 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5514 12:43:30.436020
5515 12:43:30.439574 [CATrainingPosCal] consider 1 rank data
5516 12:43:30.442725 u2DelayCellTimex100 = 270/100 ps
5517 12:43:30.445840 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5518 12:43:30.449532 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5519 12:43:30.455765 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5520 12:43:30.459286 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5521 12:43:30.462510 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5522 12:43:30.466172 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5523 12:43:30.466255
5524 12:43:30.469153 CA PerBit enable=1, Macro0, CA PI delay=33
5525 12:43:30.469245
5526 12:43:30.472393 [CBTSetCACLKResult] CA Dly = 33
5527 12:43:30.472501 CS Dly: 6 (0~37)
5528 12:43:30.472601 ==
5529 12:43:30.476152 Dram Type= 6, Freq= 0, CH_1, rank 1
5530 12:43:30.482693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5531 12:43:30.482782 ==
5532 12:43:30.486441 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5533 12:43:30.492606 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5534 12:43:30.496531 [CA 0] Center 36 (6~67) winsize 62
5535 12:43:30.499729 [CA 1] Center 37 (7~68) winsize 62
5536 12:43:30.503228 [CA 2] Center 35 (5~65) winsize 61
5537 12:43:30.506436 [CA 3] Center 34 (4~65) winsize 62
5538 12:43:30.509922 [CA 4] Center 34 (4~65) winsize 62
5539 12:43:30.513169 [CA 5] Center 33 (3~64) winsize 62
5540 12:43:30.513250
5541 12:43:30.516442 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5542 12:43:30.516524
5543 12:43:30.519281 [CATrainingPosCal] consider 2 rank data
5544 12:43:30.523215 u2DelayCellTimex100 = 270/100 ps
5545 12:43:30.526444 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5546 12:43:30.529284 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5547 12:43:30.535998 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5548 12:43:30.539211 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5549 12:43:30.542431 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5550 12:43:30.546258 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5551 12:43:30.546337
5552 12:43:30.549371 CA PerBit enable=1, Macro0, CA PI delay=33
5553 12:43:30.549450
5554 12:43:30.552518 [CBTSetCACLKResult] CA Dly = 33
5555 12:43:30.552595 CS Dly: 7 (0~40)
5556 12:43:30.552699
5557 12:43:30.556352 ----->DramcWriteLeveling(PI) begin...
5558 12:43:30.559421 ==
5559 12:43:30.562532 Dram Type= 6, Freq= 0, CH_1, rank 0
5560 12:43:30.565646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5561 12:43:30.565727 ==
5562 12:43:30.569481 Write leveling (Byte 0): 27 => 27
5563 12:43:30.572658 Write leveling (Byte 1): 27 => 27
5564 12:43:30.575605 DramcWriteLeveling(PI) end<-----
5565 12:43:30.575692
5566 12:43:30.575770 ==
5567 12:43:30.578963 Dram Type= 6, Freq= 0, CH_1, rank 0
5568 12:43:30.582040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5569 12:43:30.582116 ==
5570 12:43:30.585864 [Gating] SW mode calibration
5571 12:43:30.592151 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5572 12:43:30.598910 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5573 12:43:30.602804 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5574 12:43:30.606136 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5575 12:43:30.612796 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5576 12:43:30.615490 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 12:43:30.618803 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5578 12:43:30.622056 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5579 12:43:30.628767 0 14 24 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
5580 12:43:30.632155 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (1 1) (0 0)
5581 12:43:30.635415 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5582 12:43:30.642167 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5583 12:43:30.645509 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 12:43:30.648735 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 12:43:30.655620 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5586 12:43:30.658766 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5587 12:43:30.661908 0 15 24 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)
5588 12:43:30.668960 0 15 28 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5589 12:43:30.671954 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5590 12:43:30.675194 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 12:43:30.682115 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 12:43:30.685438 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 12:43:30.688676 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5594 12:43:30.695695 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 12:43:30.698795 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5596 12:43:30.701911 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5597 12:43:30.708824 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 12:43:30.711992 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 12:43:30.715286 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 12:43:30.721912 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 12:43:30.725544 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 12:43:30.728733 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 12:43:30.735408 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 12:43:30.738794 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 12:43:30.742097 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 12:43:30.748494 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 12:43:30.751893 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 12:43:30.755093 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 12:43:30.761423 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 12:43:30.765429 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 12:43:30.768335 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5612 12:43:30.775097 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 12:43:30.775176 Total UI for P1: 0, mck2ui 16
5614 12:43:30.778196 best dqsien dly found for B0: ( 1, 2, 24)
5615 12:43:30.782325 Total UI for P1: 0, mck2ui 16
5616 12:43:30.785220 best dqsien dly found for B1: ( 1, 2, 24)
5617 12:43:30.788248 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5618 12:43:30.794666 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5619 12:43:30.794769
5620 12:43:30.797998 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5621 12:43:30.801267 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5622 12:43:30.805130 [Gating] SW calibration Done
5623 12:43:30.805206 ==
5624 12:43:30.808231 Dram Type= 6, Freq= 0, CH_1, rank 0
5625 12:43:30.811385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5626 12:43:30.811489 ==
5627 12:43:30.811581 RX Vref Scan: 0
5628 12:43:30.815097
5629 12:43:30.815198 RX Vref 0 -> 0, step: 1
5630 12:43:30.815286
5631 12:43:30.818060 RX Delay -80 -> 252, step: 8
5632 12:43:30.821291 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5633 12:43:30.825107 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5634 12:43:30.831776 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5635 12:43:30.834995 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5636 12:43:30.838399 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5637 12:43:30.841592 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5638 12:43:30.844852 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5639 12:43:30.848119 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5640 12:43:30.854723 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5641 12:43:30.858113 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5642 12:43:30.861444 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5643 12:43:30.864741 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5644 12:43:30.867829 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5645 12:43:30.870972 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5646 12:43:30.877791 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5647 12:43:30.880878 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5648 12:43:30.880980 ==
5649 12:43:30.884254 Dram Type= 6, Freq= 0, CH_1, rank 0
5650 12:43:30.888130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5651 12:43:30.888229 ==
5652 12:43:30.891196 DQS Delay:
5653 12:43:30.891272 DQS0 = 0, DQS1 = 0
5654 12:43:30.891335 DQM Delay:
5655 12:43:30.894313 DQM0 = 102, DQM1 = 98
5656 12:43:30.894389 DQ Delay:
5657 12:43:30.898166 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5658 12:43:30.901445 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5659 12:43:30.904673 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5660 12:43:30.908064 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5661 12:43:30.908147
5662 12:43:30.911164
5663 12:43:30.911246 ==
5664 12:43:30.914897 Dram Type= 6, Freq= 0, CH_1, rank 0
5665 12:43:30.918101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5666 12:43:30.918184 ==
5667 12:43:30.918301
5668 12:43:30.918409
5669 12:43:30.921543 TX Vref Scan disable
5670 12:43:30.921627 == TX Byte 0 ==
5671 12:43:30.927766 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5672 12:43:30.931623 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5673 12:43:30.931707 == TX Byte 1 ==
5674 12:43:30.934978 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5675 12:43:30.941832 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5676 12:43:30.941915 ==
5677 12:43:30.944530 Dram Type= 6, Freq= 0, CH_1, rank 0
5678 12:43:30.948445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5679 12:43:30.948542 ==
5680 12:43:30.948641
5681 12:43:30.948730
5682 12:43:30.951684 TX Vref Scan disable
5683 12:43:30.955020 == TX Byte 0 ==
5684 12:43:30.958419 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5685 12:43:30.961135 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5686 12:43:30.964459 == TX Byte 1 ==
5687 12:43:30.967693 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5688 12:43:30.971637 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5689 12:43:30.971726
5690 12:43:30.971806 [DATLAT]
5691 12:43:30.974761 Freq=933, CH1 RK0
5692 12:43:30.974855
5693 12:43:30.977871 DATLAT Default: 0xd
5694 12:43:30.977972 0, 0xFFFF, sum = 0
5695 12:43:30.981196 1, 0xFFFF, sum = 0
5696 12:43:30.981300 2, 0xFFFF, sum = 0
5697 12:43:30.984307 3, 0xFFFF, sum = 0
5698 12:43:30.984476 4, 0xFFFF, sum = 0
5699 12:43:30.987999 5, 0xFFFF, sum = 0
5700 12:43:30.988128 6, 0xFFFF, sum = 0
5701 12:43:30.991194 7, 0xFFFF, sum = 0
5702 12:43:30.991323 8, 0xFFFF, sum = 0
5703 12:43:30.994337 9, 0xFFFF, sum = 0
5704 12:43:30.994474 10, 0x0, sum = 1
5705 12:43:30.997811 11, 0x0, sum = 2
5706 12:43:30.997983 12, 0x0, sum = 3
5707 12:43:31.000971 13, 0x0, sum = 4
5708 12:43:31.001136 best_step = 11
5709 12:43:31.001266
5710 12:43:31.001392 ==
5711 12:43:31.004643 Dram Type= 6, Freq= 0, CH_1, rank 0
5712 12:43:31.007887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5713 12:43:31.011448 ==
5714 12:43:31.011652 RX Vref Scan: 1
5715 12:43:31.011865
5716 12:43:31.014696 RX Vref 0 -> 0, step: 1
5717 12:43:31.014946
5718 12:43:31.018156 RX Delay -45 -> 252, step: 4
5719 12:43:31.018481
5720 12:43:31.018717 Set Vref, RX VrefLevel [Byte0]: 54
5721 12:43:31.021327 [Byte1]: 51
5722 12:43:31.026450
5723 12:43:31.026862 Final RX Vref Byte 0 = 54 to rank0
5724 12:43:31.029579 Final RX Vref Byte 1 = 51 to rank0
5725 12:43:31.032798 Final RX Vref Byte 0 = 54 to rank1
5726 12:43:31.036469 Final RX Vref Byte 1 = 51 to rank1==
5727 12:43:31.039619 Dram Type= 6, Freq= 0, CH_1, rank 0
5728 12:43:31.046383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5729 12:43:31.046792 ==
5730 12:43:31.047272 DQS Delay:
5731 12:43:31.047601 DQS0 = 0, DQS1 = 0
5732 12:43:31.049563 DQM Delay:
5733 12:43:31.049951 DQM0 = 103, DQM1 = 98
5734 12:43:31.052910 DQ Delay:
5735 12:43:31.056235 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =100
5736 12:43:31.059626 DQ4 =104, DQ5 =112, DQ6 =110, DQ7 =102
5737 12:43:31.062856 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =92
5738 12:43:31.066474 DQ12 =104, DQ13 =104, DQ14 =104, DQ15 =104
5739 12:43:31.066883
5740 12:43:31.067220
5741 12:43:31.072758 [DQSOSCAuto] RK0, (LSB)MR18= 0x172e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5742 12:43:31.076064 CH1 RK0: MR19=505, MR18=172E
5743 12:43:31.082909 CH1_RK0: MR19=0x505, MR18=0x172E, DQSOSC=407, MR23=63, INC=65, DEC=43
5744 12:43:31.083281
5745 12:43:31.086064 ----->DramcWriteLeveling(PI) begin...
5746 12:43:31.086463 ==
5747 12:43:31.089161 Dram Type= 6, Freq= 0, CH_1, rank 1
5748 12:43:31.092917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5749 12:43:31.093388 ==
5750 12:43:31.096008 Write leveling (Byte 0): 24 => 24
5751 12:43:31.099252 Write leveling (Byte 1): 30 => 30
5752 12:43:31.102299 DramcWriteLeveling(PI) end<-----
5753 12:43:31.102694
5754 12:43:31.103081 ==
5755 12:43:31.106218 Dram Type= 6, Freq= 0, CH_1, rank 1
5756 12:43:31.113057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5757 12:43:31.113492 ==
5758 12:43:31.113909 [Gating] SW mode calibration
5759 12:43:31.123012 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5760 12:43:31.126329 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5761 12:43:31.129479 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5762 12:43:31.136071 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5763 12:43:31.139385 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5764 12:43:31.143572 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5765 12:43:31.149031 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5766 12:43:31.152320 0 14 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5767 12:43:31.156339 0 14 24 | B1->B0 | 2f2f 3434 | 1 1 | (1 0) (0 1)
5768 12:43:31.162418 0 14 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)
5769 12:43:31.165746 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5770 12:43:31.169141 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5771 12:43:31.175714 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5772 12:43:31.179102 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5773 12:43:31.182353 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5774 12:43:31.188725 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5775 12:43:31.192480 0 15 24 | B1->B0 | 3939 2c2c | 0 0 | (0 0) (1 1)
5776 12:43:31.195592 0 15 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5777 12:43:31.202440 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 12:43:31.205688 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5779 12:43:31.209280 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5780 12:43:31.215560 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 12:43:31.218774 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 12:43:31.221936 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 12:43:31.228767 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5784 12:43:31.231814 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 12:43:31.235405 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 12:43:31.242086 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 12:43:31.245393 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 12:43:31.249136 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 12:43:31.255520 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 12:43:31.258938 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 12:43:31.262044 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 12:43:31.265482 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 12:43:31.272286 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 12:43:31.275521 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 12:43:31.278948 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 12:43:31.285492 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 12:43:31.288784 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 12:43:31.292212 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 12:43:31.298425 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5800 12:43:31.302098 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5801 12:43:31.305181 Total UI for P1: 0, mck2ui 16
5802 12:43:31.309069 best dqsien dly found for B1: ( 1, 2, 24)
5803 12:43:31.311981 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 12:43:31.315050 Total UI for P1: 0, mck2ui 16
5805 12:43:31.318873 best dqsien dly found for B0: ( 1, 2, 26)
5806 12:43:31.321855 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5807 12:43:31.325454 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5808 12:43:31.326055
5809 12:43:31.331764 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5810 12:43:31.335019 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5811 12:43:31.335624 [Gating] SW calibration Done
5812 12:43:31.339097 ==
5813 12:43:31.341690 Dram Type= 6, Freq= 0, CH_1, rank 1
5814 12:43:31.345509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5815 12:43:31.346140 ==
5816 12:43:31.346724 RX Vref Scan: 0
5817 12:43:31.347234
5818 12:43:31.348535 RX Vref 0 -> 0, step: 1
5819 12:43:31.349094
5820 12:43:31.352181 RX Delay -80 -> 252, step: 8
5821 12:43:31.355308 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5822 12:43:31.358391 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5823 12:43:31.361784 iDelay=208, Bit 2, Center 87 (0 ~ 175) 176
5824 12:43:31.368330 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5825 12:43:31.371705 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5826 12:43:31.375002 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5827 12:43:31.378099 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5828 12:43:31.381629 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5829 12:43:31.384899 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5830 12:43:31.391930 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5831 12:43:31.395472 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5832 12:43:31.398652 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5833 12:43:31.402044 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5834 12:43:31.405029 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5835 12:43:31.408258 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5836 12:43:31.414909 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5837 12:43:31.415338 ==
5838 12:43:31.418470 Dram Type= 6, Freq= 0, CH_1, rank 1
5839 12:43:31.421578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5840 12:43:31.422006 ==
5841 12:43:31.422341 DQS Delay:
5842 12:43:31.424773 DQS0 = 0, DQS1 = 0
5843 12:43:31.425243 DQM Delay:
5844 12:43:31.428434 DQM0 = 102, DQM1 = 98
5845 12:43:31.428903 DQ Delay:
5846 12:43:31.431576 DQ0 =111, DQ1 =99, DQ2 =87, DQ3 =95
5847 12:43:31.434820 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5848 12:43:31.438590 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5849 12:43:31.441689 DQ12 =103, DQ13 =107, DQ14 =103, DQ15 =107
5850 12:43:31.442417
5851 12:43:31.442911
5852 12:43:31.443275 ==
5853 12:43:31.445308 Dram Type= 6, Freq= 0, CH_1, rank 1
5854 12:43:31.451658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5855 12:43:31.452170 ==
5856 12:43:31.452558
5857 12:43:31.453140
5858 12:43:31.453668 TX Vref Scan disable
5859 12:43:31.455343 == TX Byte 0 ==
5860 12:43:31.458411 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5861 12:43:31.461619 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5862 12:43:31.465311 == TX Byte 1 ==
5863 12:43:31.468568 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5864 12:43:31.474925 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5865 12:43:31.475352 ==
5866 12:43:31.478352 Dram Type= 6, Freq= 0, CH_1, rank 1
5867 12:43:31.481490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5868 12:43:31.482071 ==
5869 12:43:31.482622
5870 12:43:31.483111
5871 12:43:31.484717 TX Vref Scan disable
5872 12:43:31.485174 == TX Byte 0 ==
5873 12:43:31.491382 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5874 12:43:31.494797 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5875 12:43:31.495349 == TX Byte 1 ==
5876 12:43:31.501352 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5877 12:43:31.504876 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5878 12:43:31.505485
5879 12:43:31.506000 [DATLAT]
5880 12:43:31.508010 Freq=933, CH1 RK1
5881 12:43:31.508572
5882 12:43:31.509161 DATLAT Default: 0xb
5883 12:43:31.511483 0, 0xFFFF, sum = 0
5884 12:43:31.512087 1, 0xFFFF, sum = 0
5885 12:43:31.514544 2, 0xFFFF, sum = 0
5886 12:43:31.515093 3, 0xFFFF, sum = 0
5887 12:43:31.517775 4, 0xFFFF, sum = 0
5888 12:43:31.521546 5, 0xFFFF, sum = 0
5889 12:43:31.521983 6, 0xFFFF, sum = 0
5890 12:43:31.524569 7, 0xFFFF, sum = 0
5891 12:43:31.525100 8, 0xFFFF, sum = 0
5892 12:43:31.528248 9, 0xFFFF, sum = 0
5893 12:43:31.528680 10, 0x0, sum = 1
5894 12:43:31.531369 11, 0x0, sum = 2
5895 12:43:31.531833 12, 0x0, sum = 3
5896 12:43:31.532303 13, 0x0, sum = 4
5897 12:43:31.535100 best_step = 11
5898 12:43:31.535531
5899 12:43:31.535863 ==
5900 12:43:31.538149 Dram Type= 6, Freq= 0, CH_1, rank 1
5901 12:43:31.541293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5902 12:43:31.541719 ==
5903 12:43:31.545019 RX Vref Scan: 0
5904 12:43:31.545442
5905 12:43:31.545778 RX Vref 0 -> 0, step: 1
5906 12:43:31.548087
5907 12:43:31.548511 RX Delay -45 -> 252, step: 4
5908 12:43:31.555480 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5909 12:43:31.558653 iDelay=203, Bit 1, Center 100 (15 ~ 186) 172
5910 12:43:31.562434 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5911 12:43:31.565540 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5912 12:43:31.568707 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5913 12:43:31.575750 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5914 12:43:31.578789 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5915 12:43:31.581986 iDelay=203, Bit 7, Center 102 (19 ~ 186) 168
5916 12:43:31.585383 iDelay=203, Bit 8, Center 88 (3 ~ 174) 172
5917 12:43:31.588734 iDelay=203, Bit 9, Center 90 (3 ~ 178) 176
5918 12:43:31.595383 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5919 12:43:31.598690 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5920 12:43:31.602190 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5921 12:43:31.605592 iDelay=203, Bit 13, Center 102 (19 ~ 186) 168
5922 12:43:31.609068 iDelay=203, Bit 14, Center 108 (27 ~ 190) 164
5923 12:43:31.615544 iDelay=203, Bit 15, Center 106 (19 ~ 194) 176
5924 12:43:31.615961 ==
5925 12:43:31.618434 Dram Type= 6, Freq= 0, CH_1, rank 1
5926 12:43:31.621724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5927 12:43:31.622163 ==
5928 12:43:31.622495 DQS Delay:
5929 12:43:31.625518 DQS0 = 0, DQS1 = 0
5930 12:43:31.625933 DQM Delay:
5931 12:43:31.628907 DQM0 = 104, DQM1 = 99
5932 12:43:31.629360 DQ Delay:
5933 12:43:31.631816 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =100
5934 12:43:31.635447 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =102
5935 12:43:31.638502 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =92
5936 12:43:31.641985 DQ12 =108, DQ13 =102, DQ14 =108, DQ15 =106
5937 12:43:31.642531
5938 12:43:31.642933
5939 12:43:31.652156 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d01, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5940 12:43:31.652609 CH1 RK1: MR19=505, MR18=2D01
5941 12:43:31.658309 CH1_RK1: MR19=0x505, MR18=0x2D01, DQSOSC=407, MR23=63, INC=65, DEC=43
5942 12:43:31.662272 [RxdqsGatingPostProcess] freq 933
5943 12:43:31.668677 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5944 12:43:31.671922 best DQS0 dly(2T, 0.5T) = (0, 10)
5945 12:43:31.675212 best DQS1 dly(2T, 0.5T) = (0, 10)
5946 12:43:31.678394 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5947 12:43:31.682114 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5948 12:43:31.685318 best DQS0 dly(2T, 0.5T) = (0, 10)
5949 12:43:31.688666 best DQS1 dly(2T, 0.5T) = (0, 10)
5950 12:43:31.691989 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5951 12:43:31.692476 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5952 12:43:31.695172 Pre-setting of DQS Precalculation
5953 12:43:31.701853 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5954 12:43:31.708509 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5955 12:43:31.715185 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5956 12:43:31.715608
5957 12:43:31.715973
5958 12:43:31.718670 [Calibration Summary] 1866 Mbps
5959 12:43:31.721342 CH 0, Rank 0
5960 12:43:31.721775 SW Impedance : PASS
5961 12:43:31.724769 DUTY Scan : NO K
5962 12:43:31.725229 ZQ Calibration : PASS
5963 12:43:31.728184 Jitter Meter : NO K
5964 12:43:31.731541 CBT Training : PASS
5965 12:43:31.731971 Write leveling : PASS
5966 12:43:31.735375 RX DQS gating : PASS
5967 12:43:31.738468 RX DQ/DQS(RDDQC) : PASS
5968 12:43:31.739023 TX DQ/DQS : PASS
5969 12:43:31.741959 RX DATLAT : PASS
5970 12:43:31.744883 RX DQ/DQS(Engine): PASS
5971 12:43:31.745309 TX OE : NO K
5972 12:43:31.748052 All Pass.
5973 12:43:31.748509
5974 12:43:31.749036 CH 0, Rank 1
5975 12:43:31.751722 SW Impedance : PASS
5976 12:43:31.752272 DUTY Scan : NO K
5977 12:43:31.755181 ZQ Calibration : PASS
5978 12:43:31.758126 Jitter Meter : NO K
5979 12:43:31.758598 CBT Training : PASS
5980 12:43:31.761807 Write leveling : PASS
5981 12:43:31.764860 RX DQS gating : PASS
5982 12:43:31.765286 RX DQ/DQS(RDDQC) : PASS
5983 12:43:31.768709 TX DQ/DQS : PASS
5984 12:43:31.769373 RX DATLAT : PASS
5985 12:43:31.771565 RX DQ/DQS(Engine): PASS
5986 12:43:31.774918 TX OE : NO K
5987 12:43:31.775480 All Pass.
5988 12:43:31.775974
5989 12:43:31.776300 CH 1, Rank 0
5990 12:43:31.778789 SW Impedance : PASS
5991 12:43:31.781227 DUTY Scan : NO K
5992 12:43:31.781651 ZQ Calibration : PASS
5993 12:43:31.785141 Jitter Meter : NO K
5994 12:43:31.788381 CBT Training : PASS
5995 12:43:31.789001 Write leveling : PASS
5996 12:43:31.791400 RX DQS gating : PASS
5997 12:43:31.794720 RX DQ/DQS(RDDQC) : PASS
5998 12:43:31.795176 TX DQ/DQS : PASS
5999 12:43:31.798455 RX DATLAT : PASS
6000 12:43:31.802000 RX DQ/DQS(Engine): PASS
6001 12:43:31.802556 TX OE : NO K
6002 12:43:31.805397 All Pass.
6003 12:43:31.805892
6004 12:43:31.806287 CH 1, Rank 1
6005 12:43:31.808694 SW Impedance : PASS
6006 12:43:31.809168 DUTY Scan : NO K
6007 12:43:31.811279 ZQ Calibration : PASS
6008 12:43:31.814808 Jitter Meter : NO K
6009 12:43:31.815232 CBT Training : PASS
6010 12:43:31.818552 Write leveling : PASS
6011 12:43:31.819017 RX DQS gating : PASS
6012 12:43:31.821804 RX DQ/DQS(RDDQC) : PASS
6013 12:43:31.824946 TX DQ/DQS : PASS
6014 12:43:31.825440 RX DATLAT : PASS
6015 12:43:31.828143 RX DQ/DQS(Engine): PASS
6016 12:43:31.831449 TX OE : NO K
6017 12:43:31.831870 All Pass.
6018 12:43:31.832199
6019 12:43:31.834932 DramC Write-DBI off
6020 12:43:31.835446 PER_BANK_REFRESH: Hybrid Mode
6021 12:43:31.838333 TX_TRACKING: ON
6022 12:43:31.847889 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6023 12:43:31.851526 [FAST_K] Save calibration result to emmc
6024 12:43:31.854530 dramc_set_vcore_voltage set vcore to 650000
6025 12:43:31.854997 Read voltage for 400, 6
6026 12:43:31.858201 Vio18 = 0
6027 12:43:31.858695 Vcore = 650000
6028 12:43:31.859082 Vdram = 0
6029 12:43:31.861340 Vddq = 0
6030 12:43:31.861838 Vmddr = 0
6031 12:43:31.864349 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6032 12:43:31.871262 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6033 12:43:31.874604 MEM_TYPE=3, freq_sel=20
6034 12:43:31.878458 sv_algorithm_assistance_LP4_800
6035 12:43:31.881420 ============ PULL DRAM RESETB DOWN ============
6036 12:43:31.884309 ========== PULL DRAM RESETB DOWN end =========
6037 12:43:31.891216 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6038 12:43:31.894428 ===================================
6039 12:43:31.894857 LPDDR4 DRAM CONFIGURATION
6040 12:43:31.897809 ===================================
6041 12:43:31.901465 EX_ROW_EN[0] = 0x0
6042 12:43:31.902061 EX_ROW_EN[1] = 0x0
6043 12:43:31.904785 LP4Y_EN = 0x0
6044 12:43:31.905261 WORK_FSP = 0x0
6045 12:43:31.907404 WL = 0x2
6046 12:43:31.910850 RL = 0x2
6047 12:43:31.911271 BL = 0x2
6048 12:43:31.914102 RPST = 0x0
6049 12:43:31.914592 RD_PRE = 0x0
6050 12:43:31.917522 WR_PRE = 0x1
6051 12:43:31.917943 WR_PST = 0x0
6052 12:43:31.920906 DBI_WR = 0x0
6053 12:43:31.921339 DBI_RD = 0x0
6054 12:43:31.924264 OTF = 0x1
6055 12:43:31.927780 ===================================
6056 12:43:31.930692 ===================================
6057 12:43:31.931108 ANA top config
6058 12:43:31.933901 ===================================
6059 12:43:31.937312 DLL_ASYNC_EN = 0
6060 12:43:31.940650 ALL_SLAVE_EN = 1
6061 12:43:31.941143 NEW_RANK_MODE = 1
6062 12:43:31.944079 DLL_IDLE_MODE = 1
6063 12:43:31.947303 LP45_APHY_COMB_EN = 1
6064 12:43:31.950490 TX_ODT_DIS = 1
6065 12:43:31.953756 NEW_8X_MODE = 1
6066 12:43:31.957530 ===================================
6067 12:43:31.960395 ===================================
6068 12:43:31.960855 data_rate = 800
6069 12:43:31.964018 CKR = 1
6070 12:43:31.967126 DQ_P2S_RATIO = 4
6071 12:43:31.970355 ===================================
6072 12:43:31.974111 CA_P2S_RATIO = 4
6073 12:43:31.977199 DQ_CA_OPEN = 0
6074 12:43:31.980310 DQ_SEMI_OPEN = 1
6075 12:43:31.980731 CA_SEMI_OPEN = 1
6076 12:43:31.983713 CA_FULL_RATE = 0
6077 12:43:31.986941 DQ_CKDIV4_EN = 0
6078 12:43:31.990695 CA_CKDIV4_EN = 1
6079 12:43:31.993792 CA_PREDIV_EN = 0
6080 12:43:31.997462 PH8_DLY = 0
6081 12:43:31.997884 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6082 12:43:32.000518 DQ_AAMCK_DIV = 0
6083 12:43:32.004244 CA_AAMCK_DIV = 0
6084 12:43:32.007353 CA_ADMCK_DIV = 4
6085 12:43:32.010359 DQ_TRACK_CA_EN = 0
6086 12:43:32.013734 CA_PICK = 800
6087 12:43:32.014156 CA_MCKIO = 400
6088 12:43:32.016900 MCKIO_SEMI = 400
6089 12:43:32.020848 PLL_FREQ = 3016
6090 12:43:32.024146 DQ_UI_PI_RATIO = 32
6091 12:43:32.027351 CA_UI_PI_RATIO = 32
6092 12:43:32.030638 ===================================
6093 12:43:32.033837 ===================================
6094 12:43:32.037027 memory_type:LPDDR4
6095 12:43:32.037446 GP_NUM : 10
6096 12:43:32.040376 SRAM_EN : 1
6097 12:43:32.040797 MD32_EN : 0
6098 12:43:32.043565 ===================================
6099 12:43:32.046864 [ANA_INIT] >>>>>>>>>>>>>>
6100 12:43:32.050733 <<<<<< [CONFIGURE PHASE]: ANA_TX
6101 12:43:32.054206 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6102 12:43:32.057311 ===================================
6103 12:43:32.060469 data_rate = 800,PCW = 0X7400
6104 12:43:32.063464 ===================================
6105 12:43:32.066818 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6106 12:43:32.073558 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6107 12:43:32.083502 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6108 12:43:32.087123 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6109 12:43:32.090149 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6110 12:43:32.093348 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6111 12:43:32.097207 [ANA_INIT] flow start
6112 12:43:32.100162 [ANA_INIT] PLL >>>>>>>>
6113 12:43:32.100600 [ANA_INIT] PLL <<<<<<<<
6114 12:43:32.103507 [ANA_INIT] MIDPI >>>>>>>>
6115 12:43:32.106855 [ANA_INIT] MIDPI <<<<<<<<
6116 12:43:32.110065 [ANA_INIT] DLL >>>>>>>>
6117 12:43:32.110588 [ANA_INIT] flow end
6118 12:43:32.113842 ============ LP4 DIFF to SE enter ============
6119 12:43:32.120183 ============ LP4 DIFF to SE exit ============
6120 12:43:32.120607 [ANA_INIT] <<<<<<<<<<<<<
6121 12:43:32.123465 [Flow] Enable top DCM control >>>>>
6122 12:43:32.126837 [Flow] Enable top DCM control <<<<<
6123 12:43:32.130211 Enable DLL master slave shuffle
6124 12:43:32.136430 ==============================================================
6125 12:43:32.136512 Gating Mode config
6126 12:43:32.142894 ==============================================================
6127 12:43:32.146243 Config description:
6128 12:43:32.156247 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6129 12:43:32.163433 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6130 12:43:32.166573 SELPH_MODE 0: By rank 1: By Phase
6131 12:43:32.172935 ==============================================================
6132 12:43:32.176449 GAT_TRACK_EN = 0
6133 12:43:32.176531 RX_GATING_MODE = 2
6134 12:43:32.179546 RX_GATING_TRACK_MODE = 2
6135 12:43:32.182654 SELPH_MODE = 1
6136 12:43:32.186426 PICG_EARLY_EN = 1
6137 12:43:32.189936 VALID_LAT_VALUE = 1
6138 12:43:32.195974 ==============================================================
6139 12:43:32.199742 Enter into Gating configuration >>>>
6140 12:43:32.202797 Exit from Gating configuration <<<<
6141 12:43:32.205854 Enter into DVFS_PRE_config >>>>>
6142 12:43:32.215931 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6143 12:43:32.219232 Exit from DVFS_PRE_config <<<<<
6144 12:43:32.222926 Enter into PICG configuration >>>>
6145 12:43:32.226168 Exit from PICG configuration <<<<
6146 12:43:32.229317 [RX_INPUT] configuration >>>>>
6147 12:43:32.232522 [RX_INPUT] configuration <<<<<
6148 12:43:32.235990 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6149 12:43:32.242493 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6150 12:43:32.249919 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6151 12:43:32.252441 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6152 12:43:32.259247 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6153 12:43:32.265705 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6154 12:43:32.269749 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6155 12:43:32.273079 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6156 12:43:32.279432 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6157 12:43:32.283021 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6158 12:43:32.286031 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6159 12:43:32.292959 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6160 12:43:32.296215 ===================================
6161 12:43:32.296301 LPDDR4 DRAM CONFIGURATION
6162 12:43:32.299314 ===================================
6163 12:43:32.302403 EX_ROW_EN[0] = 0x0
6164 12:43:32.306211 EX_ROW_EN[1] = 0x0
6165 12:43:32.306322 LP4Y_EN = 0x0
6166 12:43:32.309454 WORK_FSP = 0x0
6167 12:43:32.309567 WL = 0x2
6168 12:43:32.312764 RL = 0x2
6169 12:43:32.312904 BL = 0x2
6170 12:43:32.315743 RPST = 0x0
6171 12:43:32.315854 RD_PRE = 0x0
6172 12:43:32.318829 WR_PRE = 0x1
6173 12:43:32.318941 WR_PST = 0x0
6174 12:43:32.322515 DBI_WR = 0x0
6175 12:43:32.322618 DBI_RD = 0x0
6176 12:43:32.325689 OTF = 0x1
6177 12:43:32.328836 ===================================
6178 12:43:32.332557 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6179 12:43:32.335794 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6180 12:43:32.342563 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6181 12:43:32.345671 ===================================
6182 12:43:32.345754 LPDDR4 DRAM CONFIGURATION
6183 12:43:32.348834 ===================================
6184 12:43:32.352244 EX_ROW_EN[0] = 0x10
6185 12:43:32.352327 EX_ROW_EN[1] = 0x0
6186 12:43:32.355594 LP4Y_EN = 0x0
6187 12:43:32.359021 WORK_FSP = 0x0
6188 12:43:32.359104 WL = 0x2
6189 12:43:32.362258 RL = 0x2
6190 12:43:32.362340 BL = 0x2
6191 12:43:32.365513 RPST = 0x0
6192 12:43:32.365596 RD_PRE = 0x0
6193 12:43:32.368745 WR_PRE = 0x1
6194 12:43:32.368879 WR_PST = 0x0
6195 12:43:32.372214 DBI_WR = 0x0
6196 12:43:32.372303 DBI_RD = 0x0
6197 12:43:32.375359 OTF = 0x1
6198 12:43:32.378685 ===================================
6199 12:43:32.385341 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6200 12:43:32.388577 nWR fixed to 30
6201 12:43:32.388660 [ModeRegInit_LP4] CH0 RK0
6202 12:43:32.391822 [ModeRegInit_LP4] CH0 RK1
6203 12:43:32.395429 [ModeRegInit_LP4] CH1 RK0
6204 12:43:32.395512 [ModeRegInit_LP4] CH1 RK1
6205 12:43:32.398414 match AC timing 19
6206 12:43:32.402064 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6207 12:43:32.405362 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6208 12:43:32.411960 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6209 12:43:32.415095 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6210 12:43:32.421940 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6211 12:43:32.422022 ==
6212 12:43:32.424970 Dram Type= 6, Freq= 0, CH_0, rank 0
6213 12:43:32.428240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6214 12:43:32.428360 ==
6215 12:43:32.435010 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6216 12:43:32.441379 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6217 12:43:32.441461 [CA 0] Center 36 (8~64) winsize 57
6218 12:43:32.445078 [CA 1] Center 36 (8~64) winsize 57
6219 12:43:32.448340 [CA 2] Center 36 (8~64) winsize 57
6220 12:43:32.451530 [CA 3] Center 36 (8~64) winsize 57
6221 12:43:32.454785 [CA 4] Center 36 (8~64) winsize 57
6222 12:43:32.458089 [CA 5] Center 36 (8~64) winsize 57
6223 12:43:32.458171
6224 12:43:32.461410 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6225 12:43:32.461491
6226 12:43:32.464731 [CATrainingPosCal] consider 1 rank data
6227 12:43:32.468159 u2DelayCellTimex100 = 270/100 ps
6228 12:43:32.471405 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 12:43:32.474760 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 12:43:32.481350 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 12:43:32.484680 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 12:43:32.488024 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 12:43:32.491458 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 12:43:32.491540
6235 12:43:32.494694 CA PerBit enable=1, Macro0, CA PI delay=36
6236 12:43:32.494776
6237 12:43:32.497920 [CBTSetCACLKResult] CA Dly = 36
6238 12:43:32.498001 CS Dly: 1 (0~32)
6239 12:43:32.498065 ==
6240 12:43:32.501731 Dram Type= 6, Freq= 0, CH_0, rank 1
6241 12:43:32.508101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6242 12:43:32.508183 ==
6243 12:43:32.511595 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6244 12:43:32.518039 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6245 12:43:32.521609 [CA 0] Center 36 (8~64) winsize 57
6246 12:43:32.524800 [CA 1] Center 36 (8~64) winsize 57
6247 12:43:32.527865 [CA 2] Center 36 (8~64) winsize 57
6248 12:43:32.531714 [CA 3] Center 36 (8~64) winsize 57
6249 12:43:32.534879 [CA 4] Center 36 (8~64) winsize 57
6250 12:43:32.537982 [CA 5] Center 36 (8~64) winsize 57
6251 12:43:32.538063
6252 12:43:32.541717 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6253 12:43:32.541798
6254 12:43:32.545069 [CATrainingPosCal] consider 2 rank data
6255 12:43:32.547820 u2DelayCellTimex100 = 270/100 ps
6256 12:43:32.551693 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 12:43:32.554823 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 12:43:32.558177 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 12:43:32.561384 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 12:43:32.564933 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 12:43:32.568160 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 12:43:32.568241
6263 12:43:32.574914 CA PerBit enable=1, Macro0, CA PI delay=36
6264 12:43:32.574995
6265 12:43:32.578173 [CBTSetCACLKResult] CA Dly = 36
6266 12:43:32.578253 CS Dly: 1 (0~32)
6267 12:43:32.578317
6268 12:43:32.581519 ----->DramcWriteLeveling(PI) begin...
6269 12:43:32.581602 ==
6270 12:43:32.584729 Dram Type= 6, Freq= 0, CH_0, rank 0
6271 12:43:32.587920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6272 12:43:32.588002 ==
6273 12:43:32.591258 Write leveling (Byte 0): 40 => 8
6274 12:43:32.594671 Write leveling (Byte 1): 40 => 8
6275 12:43:32.597912 DramcWriteLeveling(PI) end<-----
6276 12:43:32.597993
6277 12:43:32.598056 ==
6278 12:43:32.601255 Dram Type= 6, Freq= 0, CH_0, rank 0
6279 12:43:32.605070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6280 12:43:32.608433 ==
6281 12:43:32.608513 [Gating] SW mode calibration
6282 12:43:32.618062 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6283 12:43:32.621289 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6284 12:43:32.625108 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6285 12:43:32.631316 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6286 12:43:32.635008 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6287 12:43:32.638383 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6288 12:43:32.644747 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6289 12:43:32.648077 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6290 12:43:32.651300 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6291 12:43:32.658374 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6292 12:43:32.661200 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6293 12:43:32.664901 Total UI for P1: 0, mck2ui 16
6294 12:43:32.668201 best dqsien dly found for B0: ( 0, 14, 24)
6295 12:43:32.671545 Total UI for P1: 0, mck2ui 16
6296 12:43:32.674812 best dqsien dly found for B1: ( 0, 14, 24)
6297 12:43:32.678060 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6298 12:43:32.681537 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6299 12:43:32.681616
6300 12:43:32.684909 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6301 12:43:32.688136 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6302 12:43:32.691461 [Gating] SW calibration Done
6303 12:43:32.691553 ==
6304 12:43:32.694783 Dram Type= 6, Freq= 0, CH_0, rank 0
6305 12:43:32.698259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6306 12:43:32.698365 ==
6307 12:43:32.701514 RX Vref Scan: 0
6308 12:43:32.701631
6309 12:43:32.704791 RX Vref 0 -> 0, step: 1
6310 12:43:32.704923
6311 12:43:32.708031 RX Delay -410 -> 252, step: 16
6312 12:43:32.711199 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6313 12:43:32.714593 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6314 12:43:32.717949 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6315 12:43:32.724687 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6316 12:43:32.728224 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6317 12:43:32.731438 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6318 12:43:32.734652 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6319 12:43:32.741867 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6320 12:43:32.744710 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6321 12:43:32.747893 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6322 12:43:32.751600 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6323 12:43:32.757926 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6324 12:43:32.761926 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6325 12:43:32.765093 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6326 12:43:32.767978 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6327 12:43:32.774887 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6328 12:43:32.775357 ==
6329 12:43:32.778444 Dram Type= 6, Freq= 0, CH_0, rank 0
6330 12:43:32.781647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 12:43:32.782130 ==
6332 12:43:32.782503 DQS Delay:
6333 12:43:32.785162 DQS0 = 27, DQS1 = 35
6334 12:43:32.785642 DQM Delay:
6335 12:43:32.788354 DQM0 = 9, DQM1 = 11
6336 12:43:32.788763 DQ Delay:
6337 12:43:32.791593 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6338 12:43:32.794884 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6339 12:43:32.798402 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6340 12:43:32.801504 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6341 12:43:32.801914
6342 12:43:32.802238
6343 12:43:32.802540 ==
6344 12:43:32.804841 Dram Type= 6, Freq= 0, CH_0, rank 0
6345 12:43:32.808844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6346 12:43:32.809280 ==
6347 12:43:32.809607
6348 12:43:32.809908
6349 12:43:32.811213 TX Vref Scan disable
6350 12:43:32.811622 == TX Byte 0 ==
6351 12:43:32.818248 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6352 12:43:32.821561 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6353 12:43:32.821976 == TX Byte 1 ==
6354 12:43:32.827955 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6355 12:43:32.831638 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6356 12:43:32.832055 ==
6357 12:43:32.834856 Dram Type= 6, Freq= 0, CH_0, rank 0
6358 12:43:32.838030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6359 12:43:32.838640 ==
6360 12:43:32.838983
6361 12:43:32.839292
6362 12:43:32.841875 TX Vref Scan disable
6363 12:43:32.842374 == TX Byte 0 ==
6364 12:43:32.847918 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6365 12:43:32.851633 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6366 12:43:32.852060 == TX Byte 1 ==
6367 12:43:32.857996 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6368 12:43:32.861137 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6369 12:43:32.861562
6370 12:43:32.861896 [DATLAT]
6371 12:43:32.864768 Freq=400, CH0 RK0
6372 12:43:32.865240
6373 12:43:32.865621 DATLAT Default: 0xf
6374 12:43:32.867985 0, 0xFFFF, sum = 0
6375 12:43:32.868433 1, 0xFFFF, sum = 0
6376 12:43:32.871509 2, 0xFFFF, sum = 0
6377 12:43:32.871940 3, 0xFFFF, sum = 0
6378 12:43:32.874595 4, 0xFFFF, sum = 0
6379 12:43:32.875091 5, 0xFFFF, sum = 0
6380 12:43:32.877740 6, 0xFFFF, sum = 0
6381 12:43:32.878168 7, 0xFFFF, sum = 0
6382 12:43:32.881577 8, 0xFFFF, sum = 0
6383 12:43:32.882031 9, 0xFFFF, sum = 0
6384 12:43:32.884757 10, 0xFFFF, sum = 0
6385 12:43:32.888093 11, 0xFFFF, sum = 0
6386 12:43:32.888522 12, 0xFFFF, sum = 0
6387 12:43:32.891382 13, 0x0, sum = 1
6388 12:43:32.892045 14, 0x0, sum = 2
6389 12:43:32.894638 15, 0x0, sum = 3
6390 12:43:32.895068 16, 0x0, sum = 4
6391 12:43:32.895409 best_step = 14
6392 12:43:32.895719
6393 12:43:32.897917 ==
6394 12:43:32.898343 Dram Type= 6, Freq= 0, CH_0, rank 0
6395 12:43:32.904688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 12:43:32.905249 ==
6397 12:43:32.905604 RX Vref Scan: 1
6398 12:43:32.905922
6399 12:43:32.908065 RX Vref 0 -> 0, step: 1
6400 12:43:32.908489
6401 12:43:32.911307 RX Delay -311 -> 252, step: 8
6402 12:43:32.911733
6403 12:43:32.914772 Set Vref, RX VrefLevel [Byte0]: 55
6404 12:43:32.917815 [Byte1]: 55
6405 12:43:32.921739
6406 12:43:32.922162 Final RX Vref Byte 0 = 55 to rank0
6407 12:43:32.925111 Final RX Vref Byte 1 = 55 to rank0
6408 12:43:32.928313 Final RX Vref Byte 0 = 55 to rank1
6409 12:43:32.931391 Final RX Vref Byte 1 = 55 to rank1==
6410 12:43:32.934757 Dram Type= 6, Freq= 0, CH_0, rank 0
6411 12:43:32.941567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6412 12:43:32.942122 ==
6413 12:43:32.942603 DQS Delay:
6414 12:43:32.943023 DQS0 = 28, DQS1 = 36
6415 12:43:32.944912 DQM Delay:
6416 12:43:32.945333 DQM0 = 11, DQM1 = 13
6417 12:43:32.947908 DQ Delay:
6418 12:43:32.951201 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6419 12:43:32.951627 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6420 12:43:32.954745 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6421 12:43:32.958023 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6422 12:43:32.958450
6423 12:43:32.958782
6424 12:43:32.968053 [DQSOSCAuto] RK0, (LSB)MR18= 0xd1be, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6425 12:43:32.971283 CH0 RK0: MR19=C0C, MR18=D1BE
6426 12:43:32.977928 CH0_RK0: MR19=0xC0C, MR18=0xD1BE, DQSOSC=384, MR23=63, INC=400, DEC=267
6427 12:43:32.978521 ==
6428 12:43:32.981415 Dram Type= 6, Freq= 0, CH_0, rank 1
6429 12:43:32.984535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6430 12:43:32.985139 ==
6431 12:43:32.987729 [Gating] SW mode calibration
6432 12:43:32.994544 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6433 12:43:32.997728 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6434 12:43:33.004551 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6435 12:43:33.007753 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6436 12:43:33.011070 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6437 12:43:33.017720 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6438 12:43:33.021025 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6439 12:43:33.024040 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6440 12:43:33.030754 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6441 12:43:33.034208 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6442 12:43:33.037470 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6443 12:43:33.040688 Total UI for P1: 0, mck2ui 16
6444 12:43:33.044583 best dqsien dly found for B0: ( 0, 14, 24)
6445 12:43:33.047623 Total UI for P1: 0, mck2ui 16
6446 12:43:33.050832 best dqsien dly found for B1: ( 0, 14, 24)
6447 12:43:33.054030 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6448 12:43:33.060742 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6449 12:43:33.061262
6450 12:43:33.063812 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6451 12:43:33.067133 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6452 12:43:33.070927 [Gating] SW calibration Done
6453 12:43:33.071386 ==
6454 12:43:33.073981 Dram Type= 6, Freq= 0, CH_0, rank 1
6455 12:43:33.077110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6456 12:43:33.077540 ==
6457 12:43:33.077878 RX Vref Scan: 0
6458 12:43:33.080320
6459 12:43:33.080780 RX Vref 0 -> 0, step: 1
6460 12:43:33.081280
6461 12:43:33.084122 RX Delay -410 -> 252, step: 16
6462 12:43:33.087327 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6463 12:43:33.093860 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6464 12:43:33.097120 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6465 12:43:33.100499 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6466 12:43:33.104276 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6467 12:43:33.110972 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6468 12:43:33.113778 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6469 12:43:33.117001 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6470 12:43:33.120984 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6471 12:43:33.127416 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6472 12:43:33.130452 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6473 12:43:33.133719 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6474 12:43:33.137125 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6475 12:43:33.143631 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6476 12:43:33.147068 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6477 12:43:33.150292 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6478 12:43:33.150717 ==
6479 12:43:33.153552 Dram Type= 6, Freq= 0, CH_0, rank 1
6480 12:43:33.160509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6481 12:43:33.161095 ==
6482 12:43:33.161533 DQS Delay:
6483 12:43:33.162025 DQS0 = 19, DQS1 = 35
6484 12:43:33.163598 DQM Delay:
6485 12:43:33.164120 DQM0 = 4, DQM1 = 10
6486 12:43:33.167328 DQ Delay:
6487 12:43:33.167881 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6488 12:43:33.170483 DQ4 =8, DQ5 =0, DQ6 =8, DQ7 =16
6489 12:43:33.173598 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6490 12:43:33.176623 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6491 12:43:33.177232
6492 12:43:33.177767
6493 12:43:33.178336 ==
6494 12:43:33.180312 Dram Type= 6, Freq= 0, CH_0, rank 1
6495 12:43:33.186533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6496 12:43:33.187140 ==
6497 12:43:33.187653
6498 12:43:33.188143
6499 12:43:33.188705 TX Vref Scan disable
6500 12:43:33.190503 == TX Byte 0 ==
6501 12:43:33.193880 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6502 12:43:33.197129 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6503 12:43:33.200261 == TX Byte 1 ==
6504 12:43:33.203311 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6505 12:43:33.206778 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6506 12:43:33.210563 ==
6507 12:43:33.211191 Dram Type= 6, Freq= 0, CH_0, rank 1
6508 12:43:33.217397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6509 12:43:33.218082 ==
6510 12:43:33.218659
6511 12:43:33.219213
6512 12:43:33.219872 TX Vref Scan disable
6513 12:43:33.220576 == TX Byte 0 ==
6514 12:43:33.223991 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6515 12:43:33.227017 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6516 12:43:33.230320 == TX Byte 1 ==
6517 12:43:33.233720 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6518 12:43:33.236845 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6519 12:43:33.237295
6520 12:43:33.240073 [DATLAT]
6521 12:43:33.240490 Freq=400, CH0 RK1
6522 12:43:33.240951
6523 12:43:33.243459 DATLAT Default: 0xe
6524 12:43:33.243873 0, 0xFFFF, sum = 0
6525 12:43:33.247000 1, 0xFFFF, sum = 0
6526 12:43:33.247437 2, 0xFFFF, sum = 0
6527 12:43:33.250411 3, 0xFFFF, sum = 0
6528 12:43:33.250877 4, 0xFFFF, sum = 0
6529 12:43:33.253599 5, 0xFFFF, sum = 0
6530 12:43:33.254040 6, 0xFFFF, sum = 0
6531 12:43:33.256767 7, 0xFFFF, sum = 0
6532 12:43:33.257382 8, 0xFFFF, sum = 0
6533 12:43:33.259891 9, 0xFFFF, sum = 0
6534 12:43:33.263679 10, 0xFFFF, sum = 0
6535 12:43:33.264130 11, 0xFFFF, sum = 0
6536 12:43:33.266945 12, 0xFFFF, sum = 0
6537 12:43:33.267392 13, 0x0, sum = 1
6538 12:43:33.270126 14, 0x0, sum = 2
6539 12:43:33.270554 15, 0x0, sum = 3
6540 12:43:33.273109 16, 0x0, sum = 4
6541 12:43:33.273573 best_step = 14
6542 12:43:33.273949
6543 12:43:33.274291 ==
6544 12:43:33.276836 Dram Type= 6, Freq= 0, CH_0, rank 1
6545 12:43:33.279942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6546 12:43:33.280382 ==
6547 12:43:33.283199 RX Vref Scan: 0
6548 12:43:33.283718
6549 12:43:33.286454 RX Vref 0 -> 0, step: 1
6550 12:43:33.286964
6551 12:43:33.287438 RX Delay -311 -> 252, step: 8
6552 12:43:33.295366 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6553 12:43:33.298471 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6554 12:43:33.301902 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6555 12:43:33.305047 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6556 12:43:33.311951 iDelay=217, Bit 4, Center -12 (-231 ~ 208) 440
6557 12:43:33.315459 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6558 12:43:33.318117 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6559 12:43:33.321511 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6560 12:43:33.328329 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6561 12:43:33.332169 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6562 12:43:33.334771 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6563 12:43:33.338085 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6564 12:43:33.345339 iDelay=217, Bit 12, Center -16 (-239 ~ 208) 448
6565 12:43:33.348565 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6566 12:43:33.351915 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6567 12:43:33.358457 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6568 12:43:33.358899 ==
6569 12:43:33.361132 Dram Type= 6, Freq= 0, CH_0, rank 1
6570 12:43:33.365111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6571 12:43:33.365540 ==
6572 12:43:33.365877 DQS Delay:
6573 12:43:33.368090 DQS0 = 24, DQS1 = 32
6574 12:43:33.368513 DQM Delay:
6575 12:43:33.371232 DQM0 = 9, DQM1 = 10
6576 12:43:33.371724 DQ Delay:
6577 12:43:33.374358 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6578 12:43:33.378136 DQ4 =12, DQ5 =0, DQ6 =12, DQ7 =16
6579 12:43:33.381228 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6580 12:43:33.384986 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6581 12:43:33.385487
6582 12:43:33.385846
6583 12:43:33.391252 [DQSOSCAuto] RK1, (LSB)MR18= 0xb958, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6584 12:43:33.394310 CH0 RK1: MR19=C0C, MR18=B958
6585 12:43:33.401335 CH0_RK1: MR19=0xC0C, MR18=0xB958, DQSOSC=386, MR23=63, INC=396, DEC=264
6586 12:43:33.404442 [RxdqsGatingPostProcess] freq 400
6587 12:43:33.411594 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6588 12:43:33.412021 best DQS0 dly(2T, 0.5T) = (0, 10)
6589 12:43:33.414893 best DQS1 dly(2T, 0.5T) = (0, 10)
6590 12:43:33.418149 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6591 12:43:33.421357 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6592 12:43:33.424746 best DQS0 dly(2T, 0.5T) = (0, 10)
6593 12:43:33.428125 best DQS1 dly(2T, 0.5T) = (0, 10)
6594 12:43:33.431329 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6595 12:43:33.434657 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6596 12:43:33.437818 Pre-setting of DQS Precalculation
6597 12:43:33.441691 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6598 12:43:33.442122 ==
6599 12:43:33.444843 Dram Type= 6, Freq= 0, CH_1, rank 0
6600 12:43:33.451358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6601 12:43:33.451790 ==
6602 12:43:33.454703 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6603 12:43:33.461345 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6604 12:43:33.464645 [CA 0] Center 36 (8~64) winsize 57
6605 12:43:33.467995 [CA 1] Center 36 (8~64) winsize 57
6606 12:43:33.471437 [CA 2] Center 36 (8~64) winsize 57
6607 12:43:33.475021 [CA 3] Center 36 (8~64) winsize 57
6608 12:43:33.478229 [CA 4] Center 36 (8~64) winsize 57
6609 12:43:33.481423 [CA 5] Center 36 (8~64) winsize 57
6610 12:43:33.481928
6611 12:43:33.485063 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6612 12:43:33.485519
6613 12:43:33.488129 [CATrainingPosCal] consider 1 rank data
6614 12:43:33.491174 u2DelayCellTimex100 = 270/100 ps
6615 12:43:33.494504 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 12:43:33.498154 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 12:43:33.501677 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 12:43:33.504715 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 12:43:33.507911 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 12:43:33.515036 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 12:43:33.515454
6622 12:43:33.517712 CA PerBit enable=1, Macro0, CA PI delay=36
6623 12:43:33.518130
6624 12:43:33.521592 [CBTSetCACLKResult] CA Dly = 36
6625 12:43:33.522010 CS Dly: 1 (0~32)
6626 12:43:33.522338 ==
6627 12:43:33.524572 Dram Type= 6, Freq= 0, CH_1, rank 1
6628 12:43:33.527941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6629 12:43:33.531160 ==
6630 12:43:33.534384 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6631 12:43:33.541315 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6632 12:43:33.544429 [CA 0] Center 36 (8~64) winsize 57
6633 12:43:33.547851 [CA 1] Center 36 (8~64) winsize 57
6634 12:43:33.550887 [CA 2] Center 36 (8~64) winsize 57
6635 12:43:33.554321 [CA 3] Center 36 (8~64) winsize 57
6636 12:43:33.557751 [CA 4] Center 36 (8~64) winsize 57
6637 12:43:33.561186 [CA 5] Center 36 (8~64) winsize 57
6638 12:43:33.561606
6639 12:43:33.564545 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6640 12:43:33.564995
6641 12:43:33.567554 [CATrainingPosCal] consider 2 rank data
6642 12:43:33.570808 u2DelayCellTimex100 = 270/100 ps
6643 12:43:33.574249 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 12:43:33.577512 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 12:43:33.580496 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 12:43:33.583757 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 12:43:33.587404 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 12:43:33.590638 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 12:43:33.590720
6650 12:43:33.593591 CA PerBit enable=1, Macro0, CA PI delay=36
6651 12:43:33.597444
6652 12:43:33.597525 [CBTSetCACLKResult] CA Dly = 36
6653 12:43:33.600536 CS Dly: 1 (0~32)
6654 12:43:33.600638
6655 12:43:33.603769 ----->DramcWriteLeveling(PI) begin...
6656 12:43:33.603857 ==
6657 12:43:33.606802 Dram Type= 6, Freq= 0, CH_1, rank 0
6658 12:43:33.610654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6659 12:43:33.610786 ==
6660 12:43:33.613862 Write leveling (Byte 0): 40 => 8
6661 12:43:33.616950 Write leveling (Byte 1): 40 => 8
6662 12:43:33.620558 DramcWriteLeveling(PI) end<-----
6663 12:43:33.620631
6664 12:43:33.620691 ==
6665 12:43:33.623806 Dram Type= 6, Freq= 0, CH_1, rank 0
6666 12:43:33.627121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6667 12:43:33.627193 ==
6668 12:43:33.630253 [Gating] SW mode calibration
6669 12:43:33.637430 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6670 12:43:33.644001 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6671 12:43:33.647388 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6672 12:43:33.653699 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6673 12:43:33.657071 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6674 12:43:33.660298 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6675 12:43:33.666944 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6676 12:43:33.670363 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6677 12:43:33.673757 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6678 12:43:33.680230 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6679 12:43:33.683368 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6680 12:43:33.686592 Total UI for P1: 0, mck2ui 16
6681 12:43:33.690395 best dqsien dly found for B0: ( 0, 14, 24)
6682 12:43:33.693430 Total UI for P1: 0, mck2ui 16
6683 12:43:33.697018 best dqsien dly found for B1: ( 0, 14, 24)
6684 12:43:33.700206 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6685 12:43:33.703527 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6686 12:43:33.703609
6687 12:43:33.706552 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6688 12:43:33.710286 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6689 12:43:33.713402 [Gating] SW calibration Done
6690 12:43:33.713484 ==
6691 12:43:33.716955 Dram Type= 6, Freq= 0, CH_1, rank 0
6692 12:43:33.719992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6693 12:43:33.720074 ==
6694 12:43:33.723371 RX Vref Scan: 0
6695 12:43:33.723454
6696 12:43:33.726338 RX Vref 0 -> 0, step: 1
6697 12:43:33.726419
6698 12:43:33.726483 RX Delay -410 -> 252, step: 16
6699 12:43:33.733382 iDelay=230, Bit 0, Center -3 (-234 ~ 229) 464
6700 12:43:33.736696 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6701 12:43:33.740068 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6702 12:43:33.743340 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6703 12:43:33.750417 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6704 12:43:33.753796 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6705 12:43:33.756970 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6706 12:43:33.760166 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6707 12:43:33.766704 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6708 12:43:33.770255 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6709 12:43:33.773478 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6710 12:43:33.776695 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6711 12:43:33.783207 iDelay=230, Bit 12, Center -3 (-234 ~ 229) 464
6712 12:43:33.787174 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6713 12:43:33.790523 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6714 12:43:33.793608 iDelay=230, Bit 15, Center -3 (-234 ~ 229) 464
6715 12:43:33.793691 ==
6716 12:43:33.796903 Dram Type= 6, Freq= 0, CH_1, rank 0
6717 12:43:33.803863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 12:43:33.803963 ==
6719 12:43:33.804043 DQS Delay:
6720 12:43:33.806828 DQS0 = 35, DQS1 = 35
6721 12:43:33.806911 DQM Delay:
6722 12:43:33.806994 DQM0 = 20, DQM1 = 17
6723 12:43:33.809966 DQ Delay:
6724 12:43:33.813227 DQ0 =32, DQ1 =16, DQ2 =0, DQ3 =16
6725 12:43:33.817084 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6726 12:43:33.820080 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6727 12:43:33.823405 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6728 12:43:33.823486
6729 12:43:33.823549
6730 12:43:33.823607 ==
6731 12:43:33.826972 Dram Type= 6, Freq= 0, CH_1, rank 0
6732 12:43:33.830072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6733 12:43:33.830154 ==
6734 12:43:33.830219
6735 12:43:33.830277
6736 12:43:33.833263 TX Vref Scan disable
6737 12:43:33.833344 == TX Byte 0 ==
6738 12:43:33.839998 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6739 12:43:33.843279 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6740 12:43:33.843362 == TX Byte 1 ==
6741 12:43:33.846470 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6742 12:43:33.853708 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6743 12:43:33.853792 ==
6744 12:43:33.856947 Dram Type= 6, Freq= 0, CH_1, rank 0
6745 12:43:33.860214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6746 12:43:33.860298 ==
6747 12:43:33.860364
6748 12:43:33.860425
6749 12:43:33.863303 TX Vref Scan disable
6750 12:43:33.863377 == TX Byte 0 ==
6751 12:43:33.869754 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6752 12:43:33.873260 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6753 12:43:33.873349 == TX Byte 1 ==
6754 12:43:33.879755 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6755 12:43:33.883254 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6756 12:43:33.883337
6757 12:43:33.883420 [DATLAT]
6758 12:43:33.886440 Freq=400, CH1 RK0
6759 12:43:33.886524
6760 12:43:33.886606 DATLAT Default: 0xf
6761 12:43:33.889907 0, 0xFFFF, sum = 0
6762 12:43:33.889993 1, 0xFFFF, sum = 0
6763 12:43:33.893134 2, 0xFFFF, sum = 0
6764 12:43:33.893219 3, 0xFFFF, sum = 0
6765 12:43:33.896384 4, 0xFFFF, sum = 0
6766 12:43:33.896469 5, 0xFFFF, sum = 0
6767 12:43:33.900070 6, 0xFFFF, sum = 0
6768 12:43:33.900155 7, 0xFFFF, sum = 0
6769 12:43:33.903325 8, 0xFFFF, sum = 0
6770 12:43:33.903410 9, 0xFFFF, sum = 0
6771 12:43:33.906544 10, 0xFFFF, sum = 0
6772 12:43:33.906629 11, 0xFFFF, sum = 0
6773 12:43:33.909544 12, 0xFFFF, sum = 0
6774 12:43:33.909630 13, 0x0, sum = 1
6775 12:43:33.913444 14, 0x0, sum = 2
6776 12:43:33.913533 15, 0x0, sum = 3
6777 12:43:33.916630 16, 0x0, sum = 4
6778 12:43:33.916712 best_step = 14
6779 12:43:33.916776
6780 12:43:33.916874 ==
6781 12:43:33.919705 Dram Type= 6, Freq= 0, CH_1, rank 0
6782 12:43:33.926643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 12:43:33.926726 ==
6784 12:43:33.926791 RX Vref Scan: 1
6785 12:43:33.926851
6786 12:43:33.929895 RX Vref 0 -> 0, step: 1
6787 12:43:33.929976
6788 12:43:33.933301 RX Delay -311 -> 252, step: 8
6789 12:43:33.933381
6790 12:43:33.936551 Set Vref, RX VrefLevel [Byte0]: 54
6791 12:43:33.939663 [Byte1]: 51
6792 12:43:33.939744
6793 12:43:33.942890 Final RX Vref Byte 0 = 54 to rank0
6794 12:43:33.946847 Final RX Vref Byte 1 = 51 to rank0
6795 12:43:33.950017 Final RX Vref Byte 0 = 54 to rank1
6796 12:43:33.953092 Final RX Vref Byte 1 = 51 to rank1==
6797 12:43:33.956291 Dram Type= 6, Freq= 0, CH_1, rank 0
6798 12:43:33.959649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6799 12:43:33.962996 ==
6800 12:43:33.963076 DQS Delay:
6801 12:43:33.963140 DQS0 = 32, DQS1 = 32
6802 12:43:33.966285 DQM Delay:
6803 12:43:33.966368 DQM0 = 14, DQM1 = 12
6804 12:43:33.969970 DQ Delay:
6805 12:43:33.970054 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6806 12:43:33.973362 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =12
6807 12:43:33.976761 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6808 12:43:33.979493 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =24
6809 12:43:33.979575
6810 12:43:33.979638
6811 12:43:33.989516 [DQSOSCAuto] RK0, (LSB)MR18= 0x92ca, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6812 12:43:33.992817 CH1 RK0: MR19=C0C, MR18=92CA
6813 12:43:33.999458 CH1_RK0: MR19=0xC0C, MR18=0x92CA, DQSOSC=384, MR23=63, INC=400, DEC=267
6814 12:43:33.999556 ==
6815 12:43:34.003142 Dram Type= 6, Freq= 0, CH_1, rank 1
6816 12:43:34.006334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6817 12:43:34.006418 ==
6818 12:43:34.009769 [Gating] SW mode calibration
6819 12:43:34.016024 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6820 12:43:34.019154 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6821 12:43:34.026496 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6822 12:43:34.029431 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6823 12:43:34.033168 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6824 12:43:34.039129 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6825 12:43:34.042940 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6826 12:43:34.046289 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6827 12:43:34.052752 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6828 12:43:34.056314 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6829 12:43:34.059543 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6830 12:43:34.062724 Total UI for P1: 0, mck2ui 16
6831 12:43:34.066377 best dqsien dly found for B0: ( 0, 14, 24)
6832 12:43:34.069734 Total UI for P1: 0, mck2ui 16
6833 12:43:34.072775 best dqsien dly found for B1: ( 0, 14, 24)
6834 12:43:34.075973 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6835 12:43:34.079388 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6836 12:43:34.079491
6837 12:43:34.085932 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6838 12:43:34.089251 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6839 12:43:34.092616 [Gating] SW calibration Done
6840 12:43:34.092714 ==
6841 12:43:34.096027 Dram Type= 6, Freq= 0, CH_1, rank 1
6842 12:43:34.099382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6843 12:43:34.099471 ==
6844 12:43:34.099535 RX Vref Scan: 0
6845 12:43:34.099595
6846 12:43:34.102756 RX Vref 0 -> 0, step: 1
6847 12:43:34.102838
6848 12:43:34.106053 RX Delay -410 -> 252, step: 16
6849 12:43:34.109338 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6850 12:43:34.115959 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6851 12:43:34.119250 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6852 12:43:34.122993 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6853 12:43:34.126125 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6854 12:43:34.129253 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6855 12:43:34.136171 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6856 12:43:34.139418 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6857 12:43:34.142701 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6858 12:43:34.145905 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6859 12:43:34.152566 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6860 12:43:34.155644 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6861 12:43:34.158856 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6862 12:43:34.165759 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6863 12:43:34.168785 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6864 12:43:34.172687 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6865 12:43:34.172859 ==
6866 12:43:34.175826 Dram Type= 6, Freq= 0, CH_1, rank 1
6867 12:43:34.178985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6868 12:43:34.179124 ==
6869 12:43:34.182654 DQS Delay:
6870 12:43:34.182817 DQS0 = 35, DQS1 = 35
6871 12:43:34.186001 DQM Delay:
6872 12:43:34.186150 DQM0 = 18, DQM1 = 13
6873 12:43:34.189582 DQ Delay:
6874 12:43:34.189753 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6875 12:43:34.192505 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6876 12:43:34.195917 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6877 12:43:34.199456 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6878 12:43:34.199710
6879 12:43:34.199899
6880 12:43:34.202837 ==
6881 12:43:34.205577 Dram Type= 6, Freq= 0, CH_1, rank 1
6882 12:43:34.209101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6883 12:43:34.209512 ==
6884 12:43:34.209876
6885 12:43:34.210174
6886 12:43:34.212257 TX Vref Scan disable
6887 12:43:34.212843 == TX Byte 0 ==
6888 12:43:34.215473 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6889 12:43:34.222233 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6890 12:43:34.222823 == TX Byte 1 ==
6891 12:43:34.226026 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6892 12:43:34.229222 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6893 12:43:34.232445 ==
6894 12:43:34.235663 Dram Type= 6, Freq= 0, CH_1, rank 1
6895 12:43:34.238805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6896 12:43:34.239256 ==
6897 12:43:34.239648
6898 12:43:34.240021
6899 12:43:34.242018 TX Vref Scan disable
6900 12:43:34.242443 == TX Byte 0 ==
6901 12:43:34.245848 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6902 12:43:34.252251 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6903 12:43:34.252670 == TX Byte 1 ==
6904 12:43:34.255469 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6905 12:43:34.262223 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6906 12:43:34.262654
6907 12:43:34.263024 [DATLAT]
6908 12:43:34.263334 Freq=400, CH1 RK1
6909 12:43:34.263663
6910 12:43:34.265496 DATLAT Default: 0xe
6911 12:43:34.265856 0, 0xFFFF, sum = 0
6912 12:43:34.268730 1, 0xFFFF, sum = 0
6913 12:43:34.269246 2, 0xFFFF, sum = 0
6914 12:43:34.272072 3, 0xFFFF, sum = 0
6915 12:43:34.272538 4, 0xFFFF, sum = 0
6916 12:43:34.275917 5, 0xFFFF, sum = 0
6917 12:43:34.278988 6, 0xFFFF, sum = 0
6918 12:43:34.279461 7, 0xFFFF, sum = 0
6919 12:43:34.282315 8, 0xFFFF, sum = 0
6920 12:43:34.282748 9, 0xFFFF, sum = 0
6921 12:43:34.285833 10, 0xFFFF, sum = 0
6922 12:43:34.286380 11, 0xFFFF, sum = 0
6923 12:43:34.288788 12, 0xFFFF, sum = 0
6924 12:43:34.289270 13, 0x0, sum = 1
6925 12:43:34.292097 14, 0x0, sum = 2
6926 12:43:34.292530 15, 0x0, sum = 3
6927 12:43:34.295521 16, 0x0, sum = 4
6928 12:43:34.295949 best_step = 14
6929 12:43:34.296290
6930 12:43:34.296655 ==
6931 12:43:34.298791 Dram Type= 6, Freq= 0, CH_1, rank 1
6932 12:43:34.301901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6933 12:43:34.302330 ==
6934 12:43:34.305428 RX Vref Scan: 0
6935 12:43:34.305973
6936 12:43:34.308896 RX Vref 0 -> 0, step: 1
6937 12:43:34.309330
6938 12:43:34.309664 RX Delay -311 -> 252, step: 8
6939 12:43:34.317525 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6940 12:43:34.320876 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6941 12:43:34.324083 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6942 12:43:34.327331 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6943 12:43:34.333979 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6944 12:43:34.337604 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6945 12:43:34.340565 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6946 12:43:34.344218 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6947 12:43:34.350651 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6948 12:43:34.353975 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6949 12:43:34.357513 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6950 12:43:34.360793 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6951 12:43:34.367162 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6952 12:43:34.370464 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6953 12:43:34.374277 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6954 12:43:34.380902 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6955 12:43:34.381331 ==
6956 12:43:34.383932 Dram Type= 6, Freq= 0, CH_1, rank 1
6957 12:43:34.387223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6958 12:43:34.387654 ==
6959 12:43:34.388013 DQS Delay:
6960 12:43:34.390406 DQS0 = 28, DQS1 = 36
6961 12:43:34.390778 DQM Delay:
6962 12:43:34.393698 DQM0 = 11, DQM1 = 15
6963 12:43:34.394138 DQ Delay:
6964 12:43:34.397323 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6965 12:43:34.400651 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6966 12:43:34.404047 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6967 12:43:34.407419 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6968 12:43:34.407850
6969 12:43:34.408185
6970 12:43:34.414005 [DQSOSCAuto] RK1, (LSB)MR18= 0xc254, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
6971 12:43:34.417250 CH1 RK1: MR19=C0C, MR18=C254
6972 12:43:34.423907 CH1_RK1: MR19=0xC0C, MR18=0xC254, DQSOSC=385, MR23=63, INC=398, DEC=265
6973 12:43:34.427250 [RxdqsGatingPostProcess] freq 400
6974 12:43:34.433435 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6975 12:43:34.433993 best DQS0 dly(2T, 0.5T) = (0, 10)
6976 12:43:34.437117 best DQS1 dly(2T, 0.5T) = (0, 10)
6977 12:43:34.440407 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6978 12:43:34.443441 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6979 12:43:34.447291 best DQS0 dly(2T, 0.5T) = (0, 10)
6980 12:43:34.450199 best DQS1 dly(2T, 0.5T) = (0, 10)
6981 12:43:34.453918 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6982 12:43:34.457220 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6983 12:43:34.460311 Pre-setting of DQS Precalculation
6984 12:43:34.467246 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6985 12:43:34.473606 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6986 12:43:34.480194 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6987 12:43:34.480616
6988 12:43:34.481041
6989 12:43:34.483456 [Calibration Summary] 800 Mbps
6990 12:43:34.483897 CH 0, Rank 0
6991 12:43:34.486683 SW Impedance : PASS
6992 12:43:34.487106 DUTY Scan : NO K
6993 12:43:34.490749 ZQ Calibration : PASS
6994 12:43:34.493360 Jitter Meter : NO K
6995 12:43:34.493787 CBT Training : PASS
6996 12:43:34.497281 Write leveling : PASS
6997 12:43:34.500382 RX DQS gating : PASS
6998 12:43:34.500828 RX DQ/DQS(RDDQC) : PASS
6999 12:43:34.503441 TX DQ/DQS : PASS
7000 12:43:34.507232 RX DATLAT : PASS
7001 12:43:34.507761 RX DQ/DQS(Engine): PASS
7002 12:43:34.510483 TX OE : NO K
7003 12:43:34.510914 All Pass.
7004 12:43:34.511251
7005 12:43:34.513861 CH 0, Rank 1
7006 12:43:34.514287 SW Impedance : PASS
7007 12:43:34.517343 DUTY Scan : NO K
7008 12:43:34.520469 ZQ Calibration : PASS
7009 12:43:34.520927 Jitter Meter : NO K
7010 12:43:34.523738 CBT Training : PASS
7011 12:43:34.524164 Write leveling : NO K
7012 12:43:34.527115 RX DQS gating : PASS
7013 12:43:34.530449 RX DQ/DQS(RDDQC) : PASS
7014 12:43:34.530903 TX DQ/DQS : PASS
7015 12:43:34.533628 RX DATLAT : PASS
7016 12:43:34.536896 RX DQ/DQS(Engine): PASS
7017 12:43:34.537322 TX OE : NO K
7018 12:43:34.540179 All Pass.
7019 12:43:34.540641
7020 12:43:34.541092 CH 1, Rank 0
7021 12:43:34.543405 SW Impedance : PASS
7022 12:43:34.543852 DUTY Scan : NO K
7023 12:43:34.546469 ZQ Calibration : PASS
7024 12:43:34.550459 Jitter Meter : NO K
7025 12:43:34.550885 CBT Training : PASS
7026 12:43:34.553653 Write leveling : PASS
7027 12:43:34.556751 RX DQS gating : PASS
7028 12:43:34.557223 RX DQ/DQS(RDDQC) : PASS
7029 12:43:34.560010 TX DQ/DQS : PASS
7030 12:43:34.563589 RX DATLAT : PASS
7031 12:43:34.564017 RX DQ/DQS(Engine): PASS
7032 12:43:34.566869 TX OE : NO K
7033 12:43:34.567300 All Pass.
7034 12:43:34.567640
7035 12:43:34.569954 CH 1, Rank 1
7036 12:43:34.570379 SW Impedance : PASS
7037 12:43:34.573404 DUTY Scan : NO K
7038 12:43:34.573905 ZQ Calibration : PASS
7039 12:43:34.576768 Jitter Meter : NO K
7040 12:43:34.580082 CBT Training : PASS
7041 12:43:34.580548 Write leveling : NO K
7042 12:43:34.583405 RX DQS gating : PASS
7043 12:43:34.586528 RX DQ/DQS(RDDQC) : PASS
7044 12:43:34.586951 TX DQ/DQS : PASS
7045 12:43:34.590033 RX DATLAT : PASS
7046 12:43:34.593638 RX DQ/DQS(Engine): PASS
7047 12:43:34.594073 TX OE : NO K
7048 12:43:34.596930 All Pass.
7049 12:43:34.597363
7050 12:43:34.597754 DramC Write-DBI off
7051 12:43:34.600110 PER_BANK_REFRESH: Hybrid Mode
7052 12:43:34.600627 TX_TRACKING: ON
7053 12:43:34.610231 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7054 12:43:34.613343 [FAST_K] Save calibration result to emmc
7055 12:43:34.616543 dramc_set_vcore_voltage set vcore to 725000
7056 12:43:34.620581 Read voltage for 1600, 0
7057 12:43:34.621131 Vio18 = 0
7058 12:43:34.623533 Vcore = 725000
7059 12:43:34.624007 Vdram = 0
7060 12:43:34.624336 Vddq = 0
7061 12:43:34.627186 Vmddr = 0
7062 12:43:34.630394 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7063 12:43:34.637233 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7064 12:43:34.637693 MEM_TYPE=3, freq_sel=13
7065 12:43:34.640582 sv_algorithm_assistance_LP4_3733
7066 12:43:34.643853 ============ PULL DRAM RESETB DOWN ============
7067 12:43:34.650365 ========== PULL DRAM RESETB DOWN end =========
7068 12:43:34.653479 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7069 12:43:34.656348 ===================================
7070 12:43:34.660213 LPDDR4 DRAM CONFIGURATION
7071 12:43:34.663296 ===================================
7072 12:43:34.663714 EX_ROW_EN[0] = 0x0
7073 12:43:34.666434 EX_ROW_EN[1] = 0x0
7074 12:43:34.670409 LP4Y_EN = 0x0
7075 12:43:34.670880 WORK_FSP = 0x1
7076 12:43:34.673659 WL = 0x5
7077 12:43:34.674075 RL = 0x5
7078 12:43:34.677149 BL = 0x2
7079 12:43:34.677579 RPST = 0x0
7080 12:43:34.679972 RD_PRE = 0x0
7081 12:43:34.680434 WR_PRE = 0x1
7082 12:43:34.683132 WR_PST = 0x1
7083 12:43:34.683555 DBI_WR = 0x0
7084 12:43:34.686862 DBI_RD = 0x0
7085 12:43:34.687286 OTF = 0x1
7086 12:43:34.690307 ===================================
7087 12:43:34.693447 ===================================
7088 12:43:34.696735 ANA top config
7089 12:43:34.699866 ===================================
7090 12:43:34.700291 DLL_ASYNC_EN = 0
7091 12:43:34.703693 ALL_SLAVE_EN = 0
7092 12:43:34.707057 NEW_RANK_MODE = 1
7093 12:43:34.710122 DLL_IDLE_MODE = 1
7094 12:43:34.710614 LP45_APHY_COMB_EN = 1
7095 12:43:34.713283 TX_ODT_DIS = 0
7096 12:43:34.716509 NEW_8X_MODE = 1
7097 12:43:34.720473 ===================================
7098 12:43:34.723594 ===================================
7099 12:43:34.726954 data_rate = 3200
7100 12:43:34.730357 CKR = 1
7101 12:43:34.733493 DQ_P2S_RATIO = 8
7102 12:43:34.733922 ===================================
7103 12:43:34.736982 CA_P2S_RATIO = 8
7104 12:43:34.740277 DQ_CA_OPEN = 0
7105 12:43:34.743619 DQ_SEMI_OPEN = 0
7106 12:43:34.746810 CA_SEMI_OPEN = 0
7107 12:43:34.750068 CA_FULL_RATE = 0
7108 12:43:34.750516 DQ_CKDIV4_EN = 0
7109 12:43:34.753447 CA_CKDIV4_EN = 0
7110 12:43:34.756537 CA_PREDIV_EN = 0
7111 12:43:34.759740 PH8_DLY = 12
7112 12:43:34.763364 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7113 12:43:34.766453 DQ_AAMCK_DIV = 4
7114 12:43:34.766874 CA_AAMCK_DIV = 4
7115 12:43:34.770165 CA_ADMCK_DIV = 4
7116 12:43:34.773269 DQ_TRACK_CA_EN = 0
7117 12:43:34.776313 CA_PICK = 1600
7118 12:43:34.780072 CA_MCKIO = 1600
7119 12:43:34.783429 MCKIO_SEMI = 0
7120 12:43:34.786702 PLL_FREQ = 3068
7121 12:43:34.789585 DQ_UI_PI_RATIO = 32
7122 12:43:34.790034 CA_UI_PI_RATIO = 0
7123 12:43:34.793124 ===================================
7124 12:43:34.796355 ===================================
7125 12:43:34.799521 memory_type:LPDDR4
7126 12:43:34.802900 GP_NUM : 10
7127 12:43:34.803354 SRAM_EN : 1
7128 12:43:34.806774 MD32_EN : 0
7129 12:43:34.809972 ===================================
7130 12:43:34.812928 [ANA_INIT] >>>>>>>>>>>>>>
7131 12:43:34.816145 <<<<<< [CONFIGURE PHASE]: ANA_TX
7132 12:43:34.820062 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7133 12:43:34.822928 ===================================
7134 12:43:34.823358 data_rate = 3200,PCW = 0X7600
7135 12:43:34.826026 ===================================
7136 12:43:34.829736 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7137 12:43:34.836325 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7138 12:43:34.843149 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7139 12:43:34.846450 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7140 12:43:34.849805 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7141 12:43:34.853051 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7142 12:43:34.856268 [ANA_INIT] flow start
7143 12:43:34.856698 [ANA_INIT] PLL >>>>>>>>
7144 12:43:34.859758 [ANA_INIT] PLL <<<<<<<<
7145 12:43:34.862600 [ANA_INIT] MIDPI >>>>>>>>
7146 12:43:34.865797 [ANA_INIT] MIDPI <<<<<<<<
7147 12:43:34.866245 [ANA_INIT] DLL >>>>>>>>
7148 12:43:34.869645 [ANA_INIT] DLL <<<<<<<<
7149 12:43:34.872671 [ANA_INIT] flow end
7150 12:43:34.875739 ============ LP4 DIFF to SE enter ============
7151 12:43:34.879154 ============ LP4 DIFF to SE exit ============
7152 12:43:34.882342 [ANA_INIT] <<<<<<<<<<<<<
7153 12:43:34.886062 [Flow] Enable top DCM control >>>>>
7154 12:43:34.889132 [Flow] Enable top DCM control <<<<<
7155 12:43:34.892343 Enable DLL master slave shuffle
7156 12:43:34.895735 ==============================================================
7157 12:43:34.899597 Gating Mode config
7158 12:43:34.902916 ==============================================================
7159 12:43:34.906184 Config description:
7160 12:43:34.915810 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7161 12:43:34.922698 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7162 12:43:34.925739 SELPH_MODE 0: By rank 1: By Phase
7163 12:43:34.932267 ==============================================================
7164 12:43:34.936134 GAT_TRACK_EN = 1
7165 12:43:34.939511 RX_GATING_MODE = 2
7166 12:43:34.942836 RX_GATING_TRACK_MODE = 2
7167 12:43:34.945948 SELPH_MODE = 1
7168 12:43:34.949424 PICG_EARLY_EN = 1
7169 12:43:34.949854 VALID_LAT_VALUE = 1
7170 12:43:34.955997 ==============================================================
7171 12:43:34.959281 Enter into Gating configuration >>>>
7172 12:43:34.962288 Exit from Gating configuration <<<<
7173 12:43:34.965752 Enter into DVFS_PRE_config >>>>>
7174 12:43:34.975673 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7175 12:43:34.979409 Exit from DVFS_PRE_config <<<<<
7176 12:43:34.982471 Enter into PICG configuration >>>>
7177 12:43:34.985668 Exit from PICG configuration <<<<
7178 12:43:34.988834 [RX_INPUT] configuration >>>>>
7179 12:43:34.992144 [RX_INPUT] configuration <<<<<
7180 12:43:34.995634 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7181 12:43:35.002568 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7182 12:43:35.009185 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7183 12:43:35.015557 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7184 12:43:35.021944 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7185 12:43:35.028547 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7186 12:43:35.032092 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7187 12:43:35.035425 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7188 12:43:35.038757 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7189 12:43:35.045282 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7190 12:43:35.048644 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7191 12:43:35.051866 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7192 12:43:35.055264 ===================================
7193 12:43:35.058812 LPDDR4 DRAM CONFIGURATION
7194 12:43:35.061970 ===================================
7195 12:43:35.062463 EX_ROW_EN[0] = 0x0
7196 12:43:35.065159 EX_ROW_EN[1] = 0x0
7197 12:43:35.065649 LP4Y_EN = 0x0
7198 12:43:35.068506 WORK_FSP = 0x1
7199 12:43:35.069093 WL = 0x5
7200 12:43:35.072471 RL = 0x5
7201 12:43:35.072983 BL = 0x2
7202 12:43:35.075248 RPST = 0x0
7203 12:43:35.078462 RD_PRE = 0x0
7204 12:43:35.079020 WR_PRE = 0x1
7205 12:43:35.082293 WR_PST = 0x1
7206 12:43:35.082876 DBI_WR = 0x0
7207 12:43:35.085547 DBI_RD = 0x0
7208 12:43:35.085972 OTF = 0x1
7209 12:43:35.088798 ===================================
7210 12:43:35.091873 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7211 12:43:35.095713 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7212 12:43:35.102000 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7213 12:43:35.105169 ===================================
7214 12:43:35.108905 LPDDR4 DRAM CONFIGURATION
7215 12:43:35.112215 ===================================
7216 12:43:35.112680 EX_ROW_EN[0] = 0x10
7217 12:43:35.115152 EX_ROW_EN[1] = 0x0
7218 12:43:35.115586 LP4Y_EN = 0x0
7219 12:43:35.118916 WORK_FSP = 0x1
7220 12:43:35.119340 WL = 0x5
7221 12:43:35.121746 RL = 0x5
7222 12:43:35.122172 BL = 0x2
7223 12:43:35.125345 RPST = 0x0
7224 12:43:35.125785 RD_PRE = 0x0
7225 12:43:35.128701 WR_PRE = 0x1
7226 12:43:35.129188 WR_PST = 0x1
7227 12:43:35.131915 DBI_WR = 0x0
7228 12:43:35.132340 DBI_RD = 0x0
7229 12:43:35.135173 OTF = 0x1
7230 12:43:35.138695 ===================================
7231 12:43:35.145284 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7232 12:43:35.145735 ==
7233 12:43:35.148286 Dram Type= 6, Freq= 0, CH_0, rank 0
7234 12:43:35.151720 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7235 12:43:35.152148 ==
7236 12:43:35.155024 [Duty_Offset_Calibration]
7237 12:43:35.155452 B0:2 B1:1 CA:1
7238 12:43:35.155787
7239 12:43:35.158356 [DutyScan_Calibration_Flow] k_type=0
7240 12:43:35.169570
7241 12:43:35.170055 ==CLK 0==
7242 12:43:35.172848 Final CLK duty delay cell = 0
7243 12:43:35.176258 [0] MAX Duty = 5156%(X100), DQS PI = 22
7244 12:43:35.179615 [0] MIN Duty = 4907%(X100), DQS PI = 0
7245 12:43:35.180055 [0] AVG Duty = 5031%(X100)
7246 12:43:35.182978
7247 12:43:35.186031 CH0 CLK Duty spec in!! Max-Min= 249%
7248 12:43:35.189777 [DutyScan_Calibration_Flow] ====Done====
7249 12:43:35.190253
7250 12:43:35.192981 [DutyScan_Calibration_Flow] k_type=1
7251 12:43:35.208742
7252 12:43:35.209343 ==DQS 0 ==
7253 12:43:35.211860 Final DQS duty delay cell = -4
7254 12:43:35.215721 [-4] MAX Duty = 5156%(X100), DQS PI = 26
7255 12:43:35.218685 [-4] MIN Duty = 4688%(X100), DQS PI = 0
7256 12:43:35.222188 [-4] AVG Duty = 4922%(X100)
7257 12:43:35.222801
7258 12:43:35.223164 ==DQS 1 ==
7259 12:43:35.225395 Final DQS duty delay cell = 0
7260 12:43:35.228617 [0] MAX Duty = 5187%(X100), DQS PI = 20
7261 12:43:35.231823 [0] MIN Duty = 5031%(X100), DQS PI = 52
7262 12:43:35.235150 [0] AVG Duty = 5109%(X100)
7263 12:43:35.235648
7264 12:43:35.238521 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7265 12:43:35.239018
7266 12:43:35.242182 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7267 12:43:35.245569 [DutyScan_Calibration_Flow] ====Done====
7268 12:43:35.246004
7269 12:43:35.248680 [DutyScan_Calibration_Flow] k_type=3
7270 12:43:35.265338
7271 12:43:35.265786 ==DQM 0 ==
7272 12:43:35.268742 Final DQM duty delay cell = 0
7273 12:43:35.271767 [0] MAX Duty = 5218%(X100), DQS PI = 32
7274 12:43:35.275774 [0] MIN Duty = 4876%(X100), DQS PI = 60
7275 12:43:35.276285 [0] AVG Duty = 5047%(X100)
7276 12:43:35.279201
7277 12:43:35.279678 ==DQM 1 ==
7278 12:43:35.282386 Final DQM duty delay cell = -4
7279 12:43:35.285866 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7280 12:43:35.289157 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7281 12:43:35.292339 [-4] AVG Duty = 4906%(X100)
7282 12:43:35.292957
7283 12:43:35.295423 CH0 DQM 0 Duty spec in!! Max-Min= 342%
7284 12:43:35.295847
7285 12:43:35.298931 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7286 12:43:35.302068 [DutyScan_Calibration_Flow] ====Done====
7287 12:43:35.302668
7288 12:43:35.305216 [DutyScan_Calibration_Flow] k_type=2
7289 12:43:35.322775
7290 12:43:35.323379 ==DQ 0 ==
7291 12:43:35.326541 Final DQ duty delay cell = 0
7292 12:43:35.329843 [0] MAX Duty = 5062%(X100), DQS PI = 26
7293 12:43:35.332748 [0] MIN Duty = 4907%(X100), DQS PI = 0
7294 12:43:35.333273 [0] AVG Duty = 4984%(X100)
7295 12:43:35.336342
7296 12:43:35.336713 ==DQ 1 ==
7297 12:43:35.339502 Final DQ duty delay cell = 0
7298 12:43:35.342751 [0] MAX Duty = 5125%(X100), DQS PI = 6
7299 12:43:35.345959 [0] MIN Duty = 4938%(X100), DQS PI = 34
7300 12:43:35.346418 [0] AVG Duty = 5031%(X100)
7301 12:43:35.346743
7302 12:43:35.349408 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7303 12:43:35.352624
7304 12:43:35.356619 CH0 DQ 1 Duty spec in!! Max-Min= 187%
7305 12:43:35.359722 [DutyScan_Calibration_Flow] ====Done====
7306 12:43:35.360235 ==
7307 12:43:35.362793 Dram Type= 6, Freq= 0, CH_1, rank 0
7308 12:43:35.366032 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7309 12:43:35.366509 ==
7310 12:43:35.369512 [Duty_Offset_Calibration]
7311 12:43:35.369971 B0:1 B1:0 CA:0
7312 12:43:35.370367
7313 12:43:35.372868 [DutyScan_Calibration_Flow] k_type=0
7314 12:43:35.382571
7315 12:43:35.383017 ==CLK 0==
7316 12:43:35.385225 Final CLK duty delay cell = -4
7317 12:43:35.389104 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7318 12:43:35.392442 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7319 12:43:35.395793 [-4] AVG Duty = 4922%(X100)
7320 12:43:35.396244
7321 12:43:35.399085 CH1 CLK Duty spec in!! Max-Min= 156%
7322 12:43:35.402400 [DutyScan_Calibration_Flow] ====Done====
7323 12:43:35.402903
7324 12:43:35.405699 [DutyScan_Calibration_Flow] k_type=1
7325 12:43:35.422089
7326 12:43:35.422599 ==DQS 0 ==
7327 12:43:35.425811 Final DQS duty delay cell = 0
7328 12:43:35.428961 [0] MAX Duty = 5094%(X100), DQS PI = 28
7329 12:43:35.432282 [0] MIN Duty = 4844%(X100), DQS PI = 48
7330 12:43:35.435518 [0] AVG Duty = 4969%(X100)
7331 12:43:35.435931
7332 12:43:35.436251 ==DQS 1 ==
7333 12:43:35.439030 Final DQS duty delay cell = 0
7334 12:43:35.442281 [0] MAX Duty = 5249%(X100), DQS PI = 16
7335 12:43:35.445404 [0] MIN Duty = 4969%(X100), DQS PI = 6
7336 12:43:35.448796 [0] AVG Duty = 5109%(X100)
7337 12:43:35.449247
7338 12:43:35.451928 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7339 12:43:35.452381
7340 12:43:35.455414 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7341 12:43:35.458649 [DutyScan_Calibration_Flow] ====Done====
7342 12:43:35.459234
7343 12:43:35.461812 [DutyScan_Calibration_Flow] k_type=3
7344 12:43:35.479410
7345 12:43:35.479858 ==DQM 0 ==
7346 12:43:35.482625 Final DQM duty delay cell = 0
7347 12:43:35.486149 [0] MAX Duty = 5218%(X100), DQS PI = 18
7348 12:43:35.489318 [0] MIN Duty = 4969%(X100), DQS PI = 48
7349 12:43:35.489751 [0] AVG Duty = 5093%(X100)
7350 12:43:35.492707
7351 12:43:35.493224 ==DQM 1 ==
7352 12:43:35.496009 Final DQM duty delay cell = 0
7353 12:43:35.499425 [0] MAX Duty = 5093%(X100), DQS PI = 16
7354 12:43:35.502561 [0] MIN Duty = 4938%(X100), DQS PI = 6
7355 12:43:35.503000 [0] AVG Duty = 5015%(X100)
7356 12:43:35.505768
7357 12:43:35.509072 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7358 12:43:35.509597
7359 12:43:35.512373 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7360 12:43:35.515781 [DutyScan_Calibration_Flow] ====Done====
7361 12:43:35.516374
7362 12:43:35.519048 [DutyScan_Calibration_Flow] k_type=2
7363 12:43:35.535295
7364 12:43:35.535734 ==DQ 0 ==
7365 12:43:35.538655 Final DQ duty delay cell = -4
7366 12:43:35.541772 [-4] MAX Duty = 5062%(X100), DQS PI = 10
7367 12:43:35.545315 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7368 12:43:35.548575 [-4] AVG Duty = 4968%(X100)
7369 12:43:35.549076
7370 12:43:35.549484 ==DQ 1 ==
7371 12:43:35.551876 Final DQ duty delay cell = 0
7372 12:43:35.555033 [0] MAX Duty = 5124%(X100), DQS PI = 16
7373 12:43:35.558468 [0] MIN Duty = 4938%(X100), DQS PI = 10
7374 12:43:35.561700 [0] AVG Duty = 5031%(X100)
7375 12:43:35.562159
7376 12:43:35.565021 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7377 12:43:35.565503
7378 12:43:35.568927 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7379 12:43:35.571949 [DutyScan_Calibration_Flow] ====Done====
7380 12:43:35.575331 nWR fixed to 30
7381 12:43:35.575920 [ModeRegInit_LP4] CH0 RK0
7382 12:43:35.579115 [ModeRegInit_LP4] CH0 RK1
7383 12:43:35.582034 [ModeRegInit_LP4] CH1 RK0
7384 12:43:35.585237 [ModeRegInit_LP4] CH1 RK1
7385 12:43:35.585686 match AC timing 5
7386 12:43:35.589088 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7387 12:43:35.595153 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7388 12:43:35.598401 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7389 12:43:35.605144 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7390 12:43:35.608967 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7391 12:43:35.609395 [MiockJmeterHQA]
7392 12:43:35.609730
7393 12:43:35.611777 [DramcMiockJmeter] u1RxGatingPI = 0
7394 12:43:35.615039 0 : 4255, 4030
7395 12:43:35.615466 4 : 4253, 4027
7396 12:43:35.618316 8 : 4252, 4027
7397 12:43:35.618741 12 : 4253, 4027
7398 12:43:35.619079 16 : 4363, 4138
7399 12:43:35.621848 20 : 4252, 4027
7400 12:43:35.622271 24 : 4252, 4027
7401 12:43:35.624969 28 : 4255, 4029
7402 12:43:35.625414 32 : 4252, 4026
7403 12:43:35.628176 36 : 4363, 4138
7404 12:43:35.628601 40 : 4252, 4027
7405 12:43:35.631682 44 : 4363, 4137
7406 12:43:35.632105 48 : 4253, 4026
7407 12:43:35.632438 52 : 4252, 4026
7408 12:43:35.634767 56 : 4250, 4027
7409 12:43:35.635208 60 : 4360, 4137
7410 12:43:35.638496 64 : 4250, 4027
7411 12:43:35.638937 68 : 4360, 4137
7412 12:43:35.641603 72 : 4250, 4026
7413 12:43:35.642204 76 : 4250, 4027
7414 12:43:35.642573 80 : 4253, 4026
7415 12:43:35.644745 84 : 4250, 4026
7416 12:43:35.645167 88 : 4360, 94
7417 12:43:35.648305 92 : 4250, 0
7418 12:43:35.648733 96 : 4252, 0
7419 12:43:35.649118 100 : 4363, 0
7420 12:43:35.651725 104 : 4360, 0
7421 12:43:35.652326 108 : 4363, 0
7422 12:43:35.654908 112 : 4252, 0
7423 12:43:35.655411 116 : 4252, 0
7424 12:43:35.655806 120 : 4250, 0
7425 12:43:35.657990 124 : 4250, 0
7426 12:43:35.658463 128 : 4252, 0
7427 12:43:35.662022 132 : 4250, 0
7428 12:43:35.662454 136 : 4252, 0
7429 12:43:35.662794 140 : 4255, 0
7430 12:43:35.664846 144 : 4250, 0
7431 12:43:35.665281 148 : 4252, 0
7432 12:43:35.665654 152 : 4363, 0
7433 12:43:35.668735 156 : 4361, 0
7434 12:43:35.669208 160 : 4363, 0
7435 12:43:35.671968 164 : 4252, 0
7436 12:43:35.672397 168 : 4252, 0
7437 12:43:35.672739 172 : 4250, 0
7438 12:43:35.675062 176 : 4250, 0
7439 12:43:35.675631 180 : 4252, 0
7440 12:43:35.678242 184 : 4250, 0
7441 12:43:35.678809 188 : 4252, 0
7442 12:43:35.679301 192 : 4250, 0
7443 12:43:35.681327 196 : 4360, 0
7444 12:43:35.681761 200 : 4250, 0
7445 12:43:35.684785 204 : 4361, 1292
7446 12:43:35.685253 208 : 4250, 3991
7447 12:43:35.688860 212 : 4250, 4027
7448 12:43:35.689297 216 : 4360, 4137
7449 12:43:35.689637 220 : 4360, 4137
7450 12:43:35.691475 224 : 4248, 4024
7451 12:43:35.691906 228 : 4361, 4138
7452 12:43:35.694754 232 : 4360, 4138
7453 12:43:35.695189 236 : 4250, 4026
7454 12:43:35.698026 240 : 4250, 4027
7455 12:43:35.698460 244 : 4250, 4027
7456 12:43:35.701323 248 : 4250, 4027
7457 12:43:35.701758 252 : 4250, 4026
7458 12:43:35.704905 256 : 4250, 4026
7459 12:43:35.705348 260 : 4250, 4026
7460 12:43:35.708109 264 : 4250, 4027
7461 12:43:35.708541 268 : 4360, 4137
7462 12:43:35.711425 272 : 4361, 4137
7463 12:43:35.711864 276 : 4248, 4025
7464 12:43:35.712299 280 : 4361, 4138
7465 12:43:35.715069 284 : 4360, 4137
7466 12:43:35.715504 288 : 4250, 4026
7467 12:43:35.717876 292 : 4250, 4027
7468 12:43:35.718308 296 : 4250, 4027
7469 12:43:35.721238 300 : 4250, 4027
7470 12:43:35.721672 304 : 4250, 4026
7471 12:43:35.724610 308 : 4250, 3978
7472 12:43:35.725093 312 : 4250, 1921
7473 12:43:35.725527
7474 12:43:35.728588 MIOCK jitter meter ch=0
7475 12:43:35.729060
7476 12:43:35.731772 1T = (312-88) = 224 dly cells
7477 12:43:35.734907 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7478 12:43:35.738184 ==
7479 12:43:35.738614 Dram Type= 6, Freq= 0, CH_0, rank 0
7480 12:43:35.744963 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7481 12:43:35.745442 ==
7482 12:43:35.748204 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7483 12:43:35.755327 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7484 12:43:35.758238 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7485 12:43:35.764901 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7486 12:43:35.773224 [CA 0] Center 43 (12~74) winsize 63
7487 12:43:35.776323 [CA 1] Center 43 (13~74) winsize 62
7488 12:43:35.779631 [CA 2] Center 38 (9~68) winsize 60
7489 12:43:35.783306 [CA 3] Center 38 (8~68) winsize 61
7490 12:43:35.786546 [CA 4] Center 37 (7~67) winsize 61
7491 12:43:35.789662 [CA 5] Center 36 (7~65) winsize 59
7492 12:43:35.790091
7493 12:43:35.793222 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7494 12:43:35.793650
7495 12:43:35.796041 [CATrainingPosCal] consider 1 rank data
7496 12:43:35.799428 u2DelayCellTimex100 = 290/100 ps
7497 12:43:35.803294 CA0 delay=43 (12~74),Diff = 7 PI (23 cell)
7498 12:43:35.809474 CA1 delay=43 (13~74),Diff = 7 PI (23 cell)
7499 12:43:35.812829 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7500 12:43:35.816731 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7501 12:43:35.819690 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7502 12:43:35.823041 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7503 12:43:35.823475
7504 12:43:35.826370 CA PerBit enable=1, Macro0, CA PI delay=36
7505 12:43:35.826799
7506 12:43:35.829845 [CBTSetCACLKResult] CA Dly = 36
7507 12:43:35.830274 CS Dly: 9 (0~40)
7508 12:43:35.836472 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7509 12:43:35.839770 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7510 12:43:35.840196 ==
7511 12:43:35.843075 Dram Type= 6, Freq= 0, CH_0, rank 1
7512 12:43:35.846319 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7513 12:43:35.846786 ==
7514 12:43:35.853041 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7515 12:43:35.856179 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7516 12:43:35.862670 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7517 12:43:35.866251 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7518 12:43:35.876510 [CA 0] Center 42 (12~73) winsize 62
7519 12:43:35.879281 [CA 1] Center 42 (12~73) winsize 62
7520 12:43:35.882903 [CA 2] Center 38 (8~68) winsize 61
7521 12:43:35.886259 [CA 3] Center 38 (8~68) winsize 61
7522 12:43:35.889452 [CA 4] Center 36 (6~66) winsize 61
7523 12:43:35.892708 [CA 5] Center 35 (5~65) winsize 61
7524 12:43:35.893157
7525 12:43:35.895694 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7526 12:43:35.896116
7527 12:43:35.899528 [CATrainingPosCal] consider 2 rank data
7528 12:43:35.902650 u2DelayCellTimex100 = 290/100 ps
7529 12:43:35.906207 CA0 delay=42 (12~73),Diff = 6 PI (20 cell)
7530 12:43:35.912725 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7531 12:43:35.916129 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7532 12:43:35.919346 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7533 12:43:35.922606 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7534 12:43:35.925685 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7535 12:43:35.926121
7536 12:43:35.929141 CA PerBit enable=1, Macro0, CA PI delay=36
7537 12:43:35.929561
7538 12:43:35.932400 [CBTSetCACLKResult] CA Dly = 36
7539 12:43:35.935896 CS Dly: 10 (0~42)
7540 12:43:35.939299 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7541 12:43:35.942583 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7542 12:43:35.942999
7543 12:43:35.945971 ----->DramcWriteLeveling(PI) begin...
7544 12:43:35.946394 ==
7545 12:43:35.949315 Dram Type= 6, Freq= 0, CH_0, rank 0
7546 12:43:35.952456 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7547 12:43:35.955703 ==
7548 12:43:35.956226 Write leveling (Byte 0): 35 => 35
7549 12:43:35.959039 Write leveling (Byte 1): 27 => 27
7550 12:43:35.962727 DramcWriteLeveling(PI) end<-----
7551 12:43:35.963112
7552 12:43:35.963505 ==
7553 12:43:35.965962 Dram Type= 6, Freq= 0, CH_0, rank 0
7554 12:43:35.972060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7555 12:43:35.972490 ==
7556 12:43:35.975893 [Gating] SW mode calibration
7557 12:43:35.982606 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7558 12:43:35.985665 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7559 12:43:35.992607 1 4 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7560 12:43:35.995911 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7561 12:43:35.998917 1 4 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7562 12:43:36.005495 1 4 12 | B1->B0 | 2323 3938 | 0 1 | (0 0) (1 1)
7563 12:43:36.008953 1 4 16 | B1->B0 | 2626 3a3a | 0 0 | (0 0) (1 1)
7564 12:43:36.012347 1 4 20 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
7565 12:43:36.015521 1 4 24 | B1->B0 | 3434 3635 | 1 1 | (1 1) (0 0)
7566 12:43:36.022248 1 4 28 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
7567 12:43:36.025453 1 5 0 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7568 12:43:36.028647 1 5 4 | B1->B0 | 3434 3b3b | 1 0 | (1 1) (0 0)
7569 12:43:36.036079 1 5 8 | B1->B0 | 3434 3838 | 1 1 | (1 1) (0 1)
7570 12:43:36.039228 1 5 12 | B1->B0 | 3434 3332 | 1 1 | (1 1) (0 1)
7571 12:43:36.042702 1 5 16 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
7572 12:43:36.048688 1 5 20 | B1->B0 | 2323 2928 | 0 1 | (1 0) (1 1)
7573 12:43:36.052521 1 5 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
7574 12:43:36.055827 1 5 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7575 12:43:36.062351 1 6 0 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7576 12:43:36.065297 1 6 4 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7577 12:43:36.068544 1 6 8 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
7578 12:43:36.075390 1 6 12 | B1->B0 | 2323 4645 | 0 1 | (0 0) (0 0)
7579 12:43:36.079167 1 6 16 | B1->B0 | 2828 4645 | 0 1 | (0 0) (0 0)
7580 12:43:36.082176 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7581 12:43:36.089055 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7582 12:43:36.092094 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7583 12:43:36.095261 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7584 12:43:36.102342 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7585 12:43:36.105382 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7586 12:43:36.108639 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7587 12:43:36.115545 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7588 12:43:36.118973 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7589 12:43:36.122353 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 12:43:36.128935 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 12:43:36.132283 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 12:43:36.135343 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 12:43:36.138616 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 12:43:36.145204 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 12:43:36.148787 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 12:43:36.152072 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 12:43:36.158527 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 12:43:36.162397 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 12:43:36.165392 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 12:43:36.171972 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 12:43:36.175233 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 12:43:36.179143 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7603 12:43:36.185320 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7604 12:43:36.185741 Total UI for P1: 0, mck2ui 16
7605 12:43:36.192168 best dqsien dly found for B0: ( 1, 9, 12)
7606 12:43:36.195460 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7607 12:43:36.198876 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 12:43:36.202065 Total UI for P1: 0, mck2ui 16
7609 12:43:36.205231 best dqsien dly found for B1: ( 1, 9, 20)
7610 12:43:36.208718 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7611 12:43:36.211974 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7612 12:43:36.212530
7613 12:43:36.218586 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7614 12:43:36.222244 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7615 12:43:36.222654 [Gating] SW calibration Done
7616 12:43:36.225429 ==
7617 12:43:36.228777 Dram Type= 6, Freq= 0, CH_0, rank 0
7618 12:43:36.232085 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7619 12:43:36.232594 ==
7620 12:43:36.232974 RX Vref Scan: 0
7621 12:43:36.233308
7622 12:43:36.235427 RX Vref 0 -> 0, step: 1
7623 12:43:36.235872
7624 12:43:36.238580 RX Delay 0 -> 252, step: 8
7625 12:43:36.241908 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7626 12:43:36.245266 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7627 12:43:36.248641 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7628 12:43:36.255414 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7629 12:43:36.258769 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7630 12:43:36.262039 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7631 12:43:36.265410 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7632 12:43:36.268453 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7633 12:43:36.275000 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7634 12:43:36.278385 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7635 12:43:36.281722 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7636 12:43:36.285063 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7637 12:43:36.288693 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7638 12:43:36.294892 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7639 12:43:36.298782 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7640 12:43:36.301629 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7641 12:43:36.302053 ==
7642 12:43:36.304845 Dram Type= 6, Freq= 0, CH_0, rank 0
7643 12:43:36.308426 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7644 12:43:36.308897 ==
7645 12:43:36.311707 DQS Delay:
7646 12:43:36.312195 DQS0 = 0, DQS1 = 0
7647 12:43:36.315467 DQM Delay:
7648 12:43:36.315889 DQM0 = 136, DQM1 = 130
7649 12:43:36.316253 DQ Delay:
7650 12:43:36.318616 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =135
7651 12:43:36.324981 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7652 12:43:36.328119 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7653 12:43:36.331877 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
7654 12:43:36.332306
7655 12:43:36.332641
7656 12:43:36.333007 ==
7657 12:43:36.335227 Dram Type= 6, Freq= 0, CH_0, rank 0
7658 12:43:36.338217 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7659 12:43:36.338713 ==
7660 12:43:36.339083
7661 12:43:36.339403
7662 12:43:36.341562 TX Vref Scan disable
7663 12:43:36.345282 == TX Byte 0 ==
7664 12:43:36.348458 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7665 12:43:36.351784 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7666 12:43:36.355084 == TX Byte 1 ==
7667 12:43:36.358606 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7668 12:43:36.361852 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7669 12:43:36.362367 ==
7670 12:43:36.365170 Dram Type= 6, Freq= 0, CH_0, rank 0
7671 12:43:36.368413 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7672 12:43:36.371587 ==
7673 12:43:36.383644
7674 12:43:36.386792 TX Vref early break, caculate TX vref
7675 12:43:36.390093 TX Vref=16, minBit 4, minWin=23, winSum=382
7676 12:43:36.393219 TX Vref=18, minBit 8, minWin=23, winSum=391
7677 12:43:36.397077 TX Vref=20, minBit 7, minWin=24, winSum=401
7678 12:43:36.400104 TX Vref=22, minBit 1, minWin=24, winSum=410
7679 12:43:36.403063 TX Vref=24, minBit 0, minWin=24, winSum=413
7680 12:43:36.410116 TX Vref=26, minBit 7, minWin=25, winSum=427
7681 12:43:36.413253 TX Vref=28, minBit 6, minWin=25, winSum=426
7682 12:43:36.417059 TX Vref=30, minBit 6, minWin=24, winSum=416
7683 12:43:36.419946 TX Vref=32, minBit 1, minWin=24, winSum=405
7684 12:43:36.423494 TX Vref=34, minBit 6, minWin=23, winSum=394
7685 12:43:36.429999 [TxChooseVref] Worse bit 7, Min win 25, Win sum 427, Final Vref 26
7686 12:43:36.430470
7687 12:43:36.433235 Final TX Range 0 Vref 26
7688 12:43:36.433689
7689 12:43:36.434019 ==
7690 12:43:36.436689 Dram Type= 6, Freq= 0, CH_0, rank 0
7691 12:43:36.439845 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7692 12:43:36.440273 ==
7693 12:43:36.440605
7694 12:43:36.440946
7695 12:43:36.443130 TX Vref Scan disable
7696 12:43:36.449891 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7697 12:43:36.450317 == TX Byte 0 ==
7698 12:43:36.453056 u2DelayCellOfst[0]=10 cells (3 PI)
7699 12:43:36.456356 u2DelayCellOfst[1]=13 cells (4 PI)
7700 12:43:36.459933 u2DelayCellOfst[2]=10 cells (3 PI)
7701 12:43:36.463233 u2DelayCellOfst[3]=10 cells (3 PI)
7702 12:43:36.466383 u2DelayCellOfst[4]=6 cells (2 PI)
7703 12:43:36.469870 u2DelayCellOfst[5]=0 cells (0 PI)
7704 12:43:36.473161 u2DelayCellOfst[6]=16 cells (5 PI)
7705 12:43:36.473583 u2DelayCellOfst[7]=16 cells (5 PI)
7706 12:43:36.479567 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7707 12:43:36.482833 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7708 12:43:36.486253 == TX Byte 1 ==
7709 12:43:36.486707 u2DelayCellOfst[8]=3 cells (1 PI)
7710 12:43:36.489662 u2DelayCellOfst[9]=0 cells (0 PI)
7711 12:43:36.493033 u2DelayCellOfst[10]=6 cells (2 PI)
7712 12:43:36.496282 u2DelayCellOfst[11]=6 cells (2 PI)
7713 12:43:36.499441 u2DelayCellOfst[12]=10 cells (3 PI)
7714 12:43:36.503334 u2DelayCellOfst[13]=10 cells (3 PI)
7715 12:43:36.506445 u2DelayCellOfst[14]=16 cells (5 PI)
7716 12:43:36.509808 u2DelayCellOfst[15]=10 cells (3 PI)
7717 12:43:36.512791 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7718 12:43:36.519856 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7719 12:43:36.520275 DramC Write-DBI on
7720 12:43:36.520604 ==
7721 12:43:36.522858 Dram Type= 6, Freq= 0, CH_0, rank 0
7722 12:43:36.526496 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7723 12:43:36.526920 ==
7724 12:43:36.529548
7725 12:43:36.529963
7726 12:43:36.530287 TX Vref Scan disable
7727 12:43:36.533164 == TX Byte 0 ==
7728 12:43:36.536439 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7729 12:43:36.539763 == TX Byte 1 ==
7730 12:43:36.543083 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7731 12:43:36.546046 DramC Write-DBI off
7732 12:43:36.546461
7733 12:43:36.546789 [DATLAT]
7734 12:43:36.547103 Freq=1600, CH0 RK0
7735 12:43:36.547407
7736 12:43:36.549318 DATLAT Default: 0xf
7737 12:43:36.549734 0, 0xFFFF, sum = 0
7738 12:43:36.553039 1, 0xFFFF, sum = 0
7739 12:43:36.556085 2, 0xFFFF, sum = 0
7740 12:43:36.556506 3, 0xFFFF, sum = 0
7741 12:43:36.559699 4, 0xFFFF, sum = 0
7742 12:43:36.560134 5, 0xFFFF, sum = 0
7743 12:43:36.563026 6, 0xFFFF, sum = 0
7744 12:43:36.563449 7, 0xFFFF, sum = 0
7745 12:43:36.566377 8, 0xFFFF, sum = 0
7746 12:43:36.566798 9, 0xFFFF, sum = 0
7747 12:43:36.569788 10, 0xFFFF, sum = 0
7748 12:43:36.570212 11, 0xFFFF, sum = 0
7749 12:43:36.572987 12, 0xFFFF, sum = 0
7750 12:43:36.573409 13, 0xFFFF, sum = 0
7751 12:43:36.576433 14, 0x0, sum = 1
7752 12:43:36.576885 15, 0x0, sum = 2
7753 12:43:36.579586 16, 0x0, sum = 3
7754 12:43:36.580015 17, 0x0, sum = 4
7755 12:43:36.582734 best_step = 15
7756 12:43:36.583196
7757 12:43:36.583581 ==
7758 12:43:36.586242 Dram Type= 6, Freq= 0, CH_0, rank 0
7759 12:43:36.589527 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7760 12:43:36.589969 ==
7761 12:43:36.590301 RX Vref Scan: 1
7762 12:43:36.592781
7763 12:43:36.593249 Set Vref Range= 24 -> 127
7764 12:43:36.593583
7765 12:43:36.596256 RX Vref 24 -> 127, step: 1
7766 12:43:36.596675
7767 12:43:36.599636 RX Delay 27 -> 252, step: 4
7768 12:43:36.600054
7769 12:43:36.602710 Set Vref, RX VrefLevel [Byte0]: 24
7770 12:43:36.606224 [Byte1]: 24
7771 12:43:36.606857
7772 12:43:36.609571 Set Vref, RX VrefLevel [Byte0]: 25
7773 12:43:36.612496 [Byte1]: 25
7774 12:43:36.613022
7775 12:43:36.616289 Set Vref, RX VrefLevel [Byte0]: 26
7776 12:43:36.619151 [Byte1]: 26
7777 12:43:36.622964
7778 12:43:36.623386 Set Vref, RX VrefLevel [Byte0]: 27
7779 12:43:36.626446 [Byte1]: 27
7780 12:43:36.630690
7781 12:43:36.631205 Set Vref, RX VrefLevel [Byte0]: 28
7782 12:43:36.633803 [Byte1]: 28
7783 12:43:36.638444
7784 12:43:36.638830 Set Vref, RX VrefLevel [Byte0]: 29
7785 12:43:36.641203 [Byte1]: 29
7786 12:43:36.645541
7787 12:43:36.645963 Set Vref, RX VrefLevel [Byte0]: 30
7788 12:43:36.648981 [Byte1]: 30
7789 12:43:36.653325
7790 12:43:36.653748 Set Vref, RX VrefLevel [Byte0]: 31
7791 12:43:36.656490 [Byte1]: 31
7792 12:43:36.660782
7793 12:43:36.661248 Set Vref, RX VrefLevel [Byte0]: 32
7794 12:43:36.664265 [Byte1]: 32
7795 12:43:36.668679
7796 12:43:36.669171 Set Vref, RX VrefLevel [Byte0]: 33
7797 12:43:36.671366 [Byte1]: 33
7798 12:43:36.675982
7799 12:43:36.676407 Set Vref, RX VrefLevel [Byte0]: 34
7800 12:43:36.679443 [Byte1]: 34
7801 12:43:36.683116
7802 12:43:36.683563 Set Vref, RX VrefLevel [Byte0]: 35
7803 12:43:36.686400 [Byte1]: 35
7804 12:43:36.691248
7805 12:43:36.691662 Set Vref, RX VrefLevel [Byte0]: 36
7806 12:43:36.694425 [Byte1]: 36
7807 12:43:36.698411
7808 12:43:36.698938 Set Vref, RX VrefLevel [Byte0]: 37
7809 12:43:36.701913 [Byte1]: 37
7810 12:43:36.705629
7811 12:43:36.706041 Set Vref, RX VrefLevel [Byte0]: 38
7812 12:43:36.708984 [Byte1]: 38
7813 12:43:36.713911
7814 12:43:36.714346 Set Vref, RX VrefLevel [Byte0]: 39
7815 12:43:36.717276 [Byte1]: 39
7816 12:43:36.720915
7817 12:43:36.721478 Set Vref, RX VrefLevel [Byte0]: 40
7818 12:43:36.724276 [Byte1]: 40
7819 12:43:36.728867
7820 12:43:36.729296 Set Vref, RX VrefLevel [Byte0]: 41
7821 12:43:36.731841 [Byte1]: 41
7822 12:43:36.736184
7823 12:43:36.736605 Set Vref, RX VrefLevel [Byte0]: 42
7824 12:43:36.739285 [Byte1]: 42
7825 12:43:36.743356
7826 12:43:36.743824 Set Vref, RX VrefLevel [Byte0]: 43
7827 12:43:36.747145 [Byte1]: 43
7828 12:43:36.750805
7829 12:43:36.751364 Set Vref, RX VrefLevel [Byte0]: 44
7830 12:43:36.754398 [Byte1]: 44
7831 12:43:36.758827
7832 12:43:36.759251 Set Vref, RX VrefLevel [Byte0]: 45
7833 12:43:36.762079 [Byte1]: 45
7834 12:43:36.765987
7835 12:43:36.766416 Set Vref, RX VrefLevel [Byte0]: 46
7836 12:43:36.769638 [Byte1]: 46
7837 12:43:36.773899
7838 12:43:36.774324 Set Vref, RX VrefLevel [Byte0]: 47
7839 12:43:36.776790 [Byte1]: 47
7840 12:43:36.781804
7841 12:43:36.782225 Set Vref, RX VrefLevel [Byte0]: 48
7842 12:43:36.784916 [Byte1]: 48
7843 12:43:36.788762
7844 12:43:36.789236 Set Vref, RX VrefLevel [Byte0]: 49
7845 12:43:36.791999 [Byte1]: 49
7846 12:43:36.796625
7847 12:43:36.797130 Set Vref, RX VrefLevel [Byte0]: 50
7848 12:43:36.799904 [Byte1]: 50
7849 12:43:36.803836
7850 12:43:36.804340 Set Vref, RX VrefLevel [Byte0]: 51
7851 12:43:36.807138 [Byte1]: 51
7852 12:43:36.811082
7853 12:43:36.811597 Set Vref, RX VrefLevel [Byte0]: 52
7854 12:43:36.815023 [Byte1]: 52
7855 12:43:36.818944
7856 12:43:36.819528 Set Vref, RX VrefLevel [Byte0]: 53
7857 12:43:36.822503 [Byte1]: 53
7858 12:43:36.826363
7859 12:43:36.826948 Set Vref, RX VrefLevel [Byte0]: 54
7860 12:43:36.829714 [Byte1]: 54
7861 12:43:36.834354
7862 12:43:36.834782 Set Vref, RX VrefLevel [Byte0]: 55
7863 12:43:36.837725 [Byte1]: 55
7864 12:43:36.841871
7865 12:43:36.842294 Set Vref, RX VrefLevel [Byte0]: 56
7866 12:43:36.844965 [Byte1]: 56
7867 12:43:36.849394
7868 12:43:36.849839 Set Vref, RX VrefLevel [Byte0]: 57
7869 12:43:36.852395 [Byte1]: 57
7870 12:43:36.856716
7871 12:43:36.857189 Set Vref, RX VrefLevel [Byte0]: 58
7872 12:43:36.859963 [Byte1]: 58
7873 12:43:36.864465
7874 12:43:36.864946 Set Vref, RX VrefLevel [Byte0]: 59
7875 12:43:36.867600 [Byte1]: 59
7876 12:43:36.871946
7877 12:43:36.872413 Set Vref, RX VrefLevel [Byte0]: 60
7878 12:43:36.874694 [Byte1]: 60
7879 12:43:36.878898
7880 12:43:36.879371 Set Vref, RX VrefLevel [Byte0]: 61
7881 12:43:36.882624 [Byte1]: 61
7882 12:43:36.886593
7883 12:43:36.887143 Set Vref, RX VrefLevel [Byte0]: 62
7884 12:43:36.889724 [Byte1]: 62
7885 12:43:36.894447
7886 12:43:36.894867 Set Vref, RX VrefLevel [Byte0]: 63
7887 12:43:36.897443 [Byte1]: 63
7888 12:43:36.902114
7889 12:43:36.902545 Set Vref, RX VrefLevel [Byte0]: 64
7890 12:43:36.904874 [Byte1]: 64
7891 12:43:36.909325
7892 12:43:36.909830 Set Vref, RX VrefLevel [Byte0]: 65
7893 12:43:36.912540 [Byte1]: 65
7894 12:43:36.916911
7895 12:43:36.917469 Set Vref, RX VrefLevel [Byte0]: 66
7896 12:43:36.920099 [Byte1]: 66
7897 12:43:36.924313
7898 12:43:36.924906 Set Vref, RX VrefLevel [Byte0]: 67
7899 12:43:36.927482 [Byte1]: 67
7900 12:43:36.932107
7901 12:43:36.932545 Set Vref, RX VrefLevel [Byte0]: 68
7902 12:43:36.935385 [Byte1]: 68
7903 12:43:36.939466
7904 12:43:36.939903 Set Vref, RX VrefLevel [Byte0]: 69
7905 12:43:36.942746 [Byte1]: 69
7906 12:43:36.947275
7907 12:43:36.947697 Set Vref, RX VrefLevel [Byte0]: 70
7908 12:43:36.950425 [Byte1]: 70
7909 12:43:36.954437
7910 12:43:36.954878 Set Vref, RX VrefLevel [Byte0]: 71
7911 12:43:36.957487 [Byte1]: 71
7912 12:43:36.961865
7913 12:43:36.962305 Set Vref, RX VrefLevel [Byte0]: 72
7914 12:43:36.965054 [Byte1]: 72
7915 12:43:36.969399
7916 12:43:36.969841 Set Vref, RX VrefLevel [Byte0]: 73
7917 12:43:36.973140 [Byte1]: 73
7918 12:43:36.977109
7919 12:43:36.977541 Set Vref, RX VrefLevel [Byte0]: 74
7920 12:43:36.980169 [Byte1]: 74
7921 12:43:36.984589
7922 12:43:36.985046 Final RX Vref Byte 0 = 53 to rank0
7923 12:43:36.987748 Final RX Vref Byte 1 = 59 to rank0
7924 12:43:36.991047 Final RX Vref Byte 0 = 53 to rank1
7925 12:43:36.994795 Final RX Vref Byte 1 = 59 to rank1==
7926 12:43:36.997974 Dram Type= 6, Freq= 0, CH_0, rank 0
7927 12:43:37.004390 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7928 12:43:37.004881 ==
7929 12:43:37.005233 DQS Delay:
7930 12:43:37.005547 DQS0 = 0, DQS1 = 0
7931 12:43:37.007741 DQM Delay:
7932 12:43:37.008165 DQM0 = 133, DQM1 = 128
7933 12:43:37.010974 DQ Delay:
7934 12:43:37.014339 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =130
7935 12:43:37.017653 DQ4 =132, DQ5 =122, DQ6 =140, DQ7 =138
7936 12:43:37.021061 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7937 12:43:37.024473 DQ12 =132, DQ13 =132, DQ14 =140, DQ15 =136
7938 12:43:37.024927
7939 12:43:37.025262
7940 12:43:37.025570
7941 12:43:37.027721 [DramC_TX_OE_Calibration] TA2
7942 12:43:37.031075 Original DQ_B0 (3 6) =30, OEN = 27
7943 12:43:37.034285 Original DQ_B1 (3 6) =30, OEN = 27
7944 12:43:37.037532 24, 0x0, End_B0=24 End_B1=24
7945 12:43:37.037973 25, 0x0, End_B0=25 End_B1=25
7946 12:43:37.040988 26, 0x0, End_B0=26 End_B1=26
7947 12:43:37.044464 27, 0x0, End_B0=27 End_B1=27
7948 12:43:37.047680 28, 0x0, End_B0=28 End_B1=28
7949 12:43:37.048114 29, 0x0, End_B0=29 End_B1=29
7950 12:43:37.050928 30, 0x0, End_B0=30 End_B1=30
7951 12:43:37.054872 31, 0x4141, End_B0=30 End_B1=30
7952 12:43:37.057682 Byte0 end_step=30 best_step=27
7953 12:43:37.060900 Byte1 end_step=30 best_step=27
7954 12:43:37.064681 Byte0 TX OE(2T, 0.5T) = (3, 3)
7955 12:43:37.067840 Byte1 TX OE(2T, 0.5T) = (3, 3)
7956 12:43:37.068272
7957 12:43:37.068702
7958 12:43:37.074864 [DQSOSCAuto] RK0, (LSB)MR18= 0x2521, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
7959 12:43:37.077753 CH0 RK0: MR19=303, MR18=2521
7960 12:43:37.084532 CH0_RK0: MR19=0x303, MR18=0x2521, DQSOSC=391, MR23=63, INC=24, DEC=16
7961 12:43:37.085020
7962 12:43:37.087787 ----->DramcWriteLeveling(PI) begin...
7963 12:43:37.088287 ==
7964 12:43:37.090939 Dram Type= 6, Freq= 0, CH_0, rank 1
7965 12:43:37.094233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7966 12:43:37.094657 ==
7967 12:43:37.097384 Write leveling (Byte 0): 37 => 37
7968 12:43:37.100641 Write leveling (Byte 1): 27 => 27
7969 12:43:37.104450 DramcWriteLeveling(PI) end<-----
7970 12:43:37.104904
7971 12:43:37.105243 ==
7972 12:43:37.107399 Dram Type= 6, Freq= 0, CH_0, rank 1
7973 12:43:37.110676 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7974 12:43:37.111100 ==
7975 12:43:37.114159 [Gating] SW mode calibration
7976 12:43:37.120792 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7977 12:43:37.127682 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7978 12:43:37.130738 1 4 0 | B1->B0 | 2323 2524 | 0 1 | (0 0) (1 1)
7979 12:43:37.134004 1 4 4 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7980 12:43:37.140704 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7981 12:43:37.144764 1 4 12 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (1 1)
7982 12:43:37.147349 1 4 16 | B1->B0 | 2d2d 3838 | 1 0 | (1 1) (0 0)
7983 12:43:37.153955 1 4 20 | B1->B0 | 3434 3737 | 1 1 | (1 1) (0 0)
7984 12:43:37.157664 1 4 24 | B1->B0 | 3434 3838 | 1 0 | (1 1) (0 0)
7985 12:43:37.160912 1 4 28 | B1->B0 | 3434 3838 | 1 1 | (1 1) (0 0)
7986 12:43:37.167344 1 5 0 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
7987 12:43:37.171043 1 5 4 | B1->B0 | 3434 3837 | 1 1 | (1 1) (1 1)
7988 12:43:37.174077 1 5 8 | B1->B0 | 3434 3636 | 1 0 | (1 0) (0 0)
7989 12:43:37.181089 1 5 12 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
7990 12:43:37.184185 1 5 16 | B1->B0 | 2e2e 2a29 | 0 1 | (0 1) (1 0)
7991 12:43:37.187327 1 5 20 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
7992 12:43:37.193985 1 5 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
7993 12:43:37.197191 1 5 28 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
7994 12:43:37.200309 1 6 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7995 12:43:37.207290 1 6 4 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (1 1)
7996 12:43:37.210394 1 6 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7997 12:43:37.214193 1 6 12 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
7998 12:43:37.220545 1 6 16 | B1->B0 | 3535 4443 | 0 1 | (0 0) (0 0)
7999 12:43:37.223747 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8000 12:43:37.227034 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8001 12:43:37.233774 1 6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8002 12:43:37.237119 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8003 12:43:37.240323 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8004 12:43:37.246985 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8005 12:43:37.250175 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8006 12:43:37.253534 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8007 12:43:37.259979 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 12:43:37.263447 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 12:43:37.266542 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 12:43:37.269981 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 12:43:37.276564 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 12:43:37.279893 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 12:43:37.283752 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 12:43:37.289860 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 12:43:37.293588 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 12:43:37.296696 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 12:43:37.302980 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 12:43:37.306713 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 12:43:37.309764 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 12:43:37.316861 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 12:43:37.319941 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8022 12:43:37.323097 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8023 12:43:37.329566 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8024 12:43:37.333431 Total UI for P1: 0, mck2ui 16
8025 12:43:37.336627 best dqsien dly found for B0: ( 1, 9, 14)
8026 12:43:37.337164 Total UI for P1: 0, mck2ui 16
8027 12:43:37.343429 best dqsien dly found for B1: ( 1, 9, 14)
8028 12:43:37.346265 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8029 12:43:37.349776 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8030 12:43:37.350204
8031 12:43:37.353304 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8032 12:43:37.356682 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8033 12:43:37.359479 [Gating] SW calibration Done
8034 12:43:37.359905 ==
8035 12:43:37.363448 Dram Type= 6, Freq= 0, CH_0, rank 1
8036 12:43:37.366687 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8037 12:43:37.367084 ==
8038 12:43:37.369826 RX Vref Scan: 0
8039 12:43:37.370252
8040 12:43:37.370613 RX Vref 0 -> 0, step: 1
8041 12:43:37.370952
8042 12:43:37.373187 RX Delay 0 -> 252, step: 8
8043 12:43:37.376503 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8044 12:43:37.383257 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8045 12:43:37.386410 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8046 12:43:37.389983 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8047 12:43:37.393119 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8048 12:43:37.396116 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8049 12:43:37.403315 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8050 12:43:37.406438 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8051 12:43:37.409385 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8052 12:43:37.413120 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8053 12:43:37.416217 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8054 12:43:37.423009 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8055 12:43:37.426132 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8056 12:43:37.429633 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8057 12:43:37.433524 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8058 12:43:37.436402 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8059 12:43:37.439799 ==
8060 12:43:37.443217 Dram Type= 6, Freq= 0, CH_0, rank 1
8061 12:43:37.446743 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8062 12:43:37.447193 ==
8063 12:43:37.447526 DQS Delay:
8064 12:43:37.449843 DQS0 = 0, DQS1 = 0
8065 12:43:37.450271 DQM Delay:
8066 12:43:37.453337 DQM0 = 136, DQM1 = 128
8067 12:43:37.453765 DQ Delay:
8068 12:43:37.456564 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8069 12:43:37.459874 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8070 12:43:37.463199 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8071 12:43:37.466518 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8072 12:43:37.467014
8073 12:43:37.467349
8074 12:43:37.467659 ==
8075 12:43:37.470069 Dram Type= 6, Freq= 0, CH_0, rank 1
8076 12:43:37.476595 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8077 12:43:37.477142 ==
8078 12:43:37.477571
8079 12:43:37.477975
8080 12:43:37.478368 TX Vref Scan disable
8081 12:43:37.479983 == TX Byte 0 ==
8082 12:43:37.483395 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8083 12:43:37.486630 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8084 12:43:37.489804 == TX Byte 1 ==
8085 12:43:37.493106 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8086 12:43:37.496329 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8087 12:43:37.499602 ==
8088 12:43:37.503233 Dram Type= 6, Freq= 0, CH_0, rank 1
8089 12:43:37.506442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8090 12:43:37.506864 ==
8091 12:43:37.520082
8092 12:43:37.523200 TX Vref early break, caculate TX vref
8093 12:43:37.526862 TX Vref=16, minBit 3, minWin=23, winSum=392
8094 12:43:37.530023 TX Vref=18, minBit 3, minWin=23, winSum=393
8095 12:43:37.533324 TX Vref=20, minBit 1, minWin=24, winSum=405
8096 12:43:37.536777 TX Vref=22, minBit 3, minWin=24, winSum=409
8097 12:43:37.539903 TX Vref=24, minBit 1, minWin=24, winSum=419
8098 12:43:37.546896 TX Vref=26, minBit 3, minWin=25, winSum=429
8099 12:43:37.550513 TX Vref=28, minBit 2, minWin=25, winSum=425
8100 12:43:37.553072 TX Vref=30, minBit 0, minWin=25, winSum=418
8101 12:43:37.556257 TX Vref=32, minBit 4, minWin=24, winSum=411
8102 12:43:37.559622 TX Vref=34, minBit 0, minWin=24, winSum=404
8103 12:43:37.566239 [TxChooseVref] Worse bit 3, Min win 25, Win sum 429, Final Vref 26
8104 12:43:37.566739
8105 12:43:37.569614 Final TX Range 0 Vref 26
8106 12:43:37.570099
8107 12:43:37.570455 ==
8108 12:43:37.572978 Dram Type= 6, Freq= 0, CH_0, rank 1
8109 12:43:37.576215 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8110 12:43:37.576639 ==
8111 12:43:37.577127
8112 12:43:37.577477
8113 12:43:37.579534 TX Vref Scan disable
8114 12:43:37.586187 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8115 12:43:37.586678 == TX Byte 0 ==
8116 12:43:37.589336 u2DelayCellOfst[0]=13 cells (4 PI)
8117 12:43:37.592866 u2DelayCellOfst[1]=16 cells (5 PI)
8118 12:43:37.596084 u2DelayCellOfst[2]=13 cells (4 PI)
8119 12:43:37.599322 u2DelayCellOfst[3]=10 cells (3 PI)
8120 12:43:37.602985 u2DelayCellOfst[4]=10 cells (3 PI)
8121 12:43:37.605828 u2DelayCellOfst[5]=0 cells (0 PI)
8122 12:43:37.609711 u2DelayCellOfst[6]=16 cells (5 PI)
8123 12:43:37.612774 u2DelayCellOfst[7]=16 cells (5 PI)
8124 12:43:37.616399 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8125 12:43:37.619430 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8126 12:43:37.622327 == TX Byte 1 ==
8127 12:43:37.625984 u2DelayCellOfst[8]=3 cells (1 PI)
8128 12:43:37.626468 u2DelayCellOfst[9]=0 cells (0 PI)
8129 12:43:37.629179 u2DelayCellOfst[10]=6 cells (2 PI)
8130 12:43:37.633038 u2DelayCellOfst[11]=3 cells (1 PI)
8131 12:43:37.636138 u2DelayCellOfst[12]=10 cells (3 PI)
8132 12:43:37.639290 u2DelayCellOfst[13]=13 cells (4 PI)
8133 12:43:37.642490 u2DelayCellOfst[14]=16 cells (5 PI)
8134 12:43:37.645466 u2DelayCellOfst[15]=10 cells (3 PI)
8135 12:43:37.649036 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8136 12:43:37.655479 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8137 12:43:37.655860 DramC Write-DBI on
8138 12:43:37.656212 ==
8139 12:43:37.658802 Dram Type= 6, Freq= 0, CH_0, rank 1
8140 12:43:37.665393 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8141 12:43:37.665819 ==
8142 12:43:37.666143
8143 12:43:37.666472
8144 12:43:37.666763 TX Vref Scan disable
8145 12:43:37.669500 == TX Byte 0 ==
8146 12:43:37.672875 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8147 12:43:37.676067 == TX Byte 1 ==
8148 12:43:37.679516 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8149 12:43:37.682794 DramC Write-DBI off
8150 12:43:37.683214
8151 12:43:37.683601 [DATLAT]
8152 12:43:37.683920 Freq=1600, CH0 RK1
8153 12:43:37.684227
8154 12:43:37.686173 DATLAT Default: 0xf
8155 12:43:37.686593 0, 0xFFFF, sum = 0
8156 12:43:37.689368 1, 0xFFFF, sum = 0
8157 12:43:37.693174 2, 0xFFFF, sum = 0
8158 12:43:37.693602 3, 0xFFFF, sum = 0
8159 12:43:37.696595 4, 0xFFFF, sum = 0
8160 12:43:37.697070 5, 0xFFFF, sum = 0
8161 12:43:37.699686 6, 0xFFFF, sum = 0
8162 12:43:37.700114 7, 0xFFFF, sum = 0
8163 12:43:37.702973 8, 0xFFFF, sum = 0
8164 12:43:37.703409 9, 0xFFFF, sum = 0
8165 12:43:37.706272 10, 0xFFFF, sum = 0
8166 12:43:37.706705 11, 0xFFFF, sum = 0
8167 12:43:37.709737 12, 0xFFFF, sum = 0
8168 12:43:37.710171 13, 0xFFFF, sum = 0
8169 12:43:37.712783 14, 0x0, sum = 1
8170 12:43:37.713245 15, 0x0, sum = 2
8171 12:43:37.716093 16, 0x0, sum = 3
8172 12:43:37.716542 17, 0x0, sum = 4
8173 12:43:37.719661 best_step = 15
8174 12:43:37.720087
8175 12:43:37.720444 ==
8176 12:43:37.722487 Dram Type= 6, Freq= 0, CH_0, rank 1
8177 12:43:37.726440 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8178 12:43:37.726863 ==
8179 12:43:37.729421 RX Vref Scan: 0
8180 12:43:37.729855
8181 12:43:37.730247 RX Vref 0 -> 0, step: 1
8182 12:43:37.730590
8183 12:43:37.732941 RX Delay 19 -> 252, step: 4
8184 12:43:37.736092 iDelay=191, Bit 0, Center 132 (79 ~ 186) 108
8185 12:43:37.743087 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8186 12:43:37.745935 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8187 12:43:37.749885 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8188 12:43:37.752881 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8189 12:43:37.756042 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8190 12:43:37.762799 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8191 12:43:37.766103 iDelay=191, Bit 7, Center 142 (95 ~ 190) 96
8192 12:43:37.769128 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8193 12:43:37.772848 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8194 12:43:37.776041 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8195 12:43:37.782615 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8196 12:43:37.785889 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8197 12:43:37.789152 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8198 12:43:37.792533 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8199 12:43:37.795800 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8200 12:43:37.796218 ==
8201 12:43:37.799209 Dram Type= 6, Freq= 0, CH_0, rank 1
8202 12:43:37.806421 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8203 12:43:37.806885 ==
8204 12:43:37.807315 DQS Delay:
8205 12:43:37.809755 DQS0 = 0, DQS1 = 0
8206 12:43:37.810251 DQM Delay:
8207 12:43:37.812923 DQM0 = 134, DQM1 = 127
8208 12:43:37.813417 DQ Delay:
8209 12:43:37.816394 DQ0 =132, DQ1 =138, DQ2 =130, DQ3 =134
8210 12:43:37.819700 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =142
8211 12:43:37.822895 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8212 12:43:37.825864 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8213 12:43:37.826370
8214 12:43:37.826748
8215 12:43:37.827076
8216 12:43:37.829732 [DramC_TX_OE_Calibration] TA2
8217 12:43:37.832348 Original DQ_B0 (3 6) =30, OEN = 27
8218 12:43:37.836244 Original DQ_B1 (3 6) =30, OEN = 27
8219 12:43:37.839233 24, 0x0, End_B0=24 End_B1=24
8220 12:43:37.839665 25, 0x0, End_B0=25 End_B1=25
8221 12:43:37.842998 26, 0x0, End_B0=26 End_B1=26
8222 12:43:37.845955 27, 0x0, End_B0=27 End_B1=27
8223 12:43:37.849460 28, 0x0, End_B0=28 End_B1=28
8224 12:43:37.852588 29, 0x0, End_B0=29 End_B1=29
8225 12:43:37.853083 30, 0x0, End_B0=30 End_B1=30
8226 12:43:37.856035 31, 0x4141, End_B0=30 End_B1=30
8227 12:43:37.859197 Byte0 end_step=30 best_step=27
8228 12:43:37.863061 Byte1 end_step=30 best_step=27
8229 12:43:37.866031 Byte0 TX OE(2T, 0.5T) = (3, 3)
8230 12:43:37.869189 Byte1 TX OE(2T, 0.5T) = (3, 3)
8231 12:43:37.869633
8232 12:43:37.869973
8233 12:43:37.876192 [DQSOSCAuto] RK1, (LSB)MR18= 0x2209, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
8234 12:43:37.879283 CH0 RK1: MR19=303, MR18=2209
8235 12:43:37.886059 CH0_RK1: MR19=0x303, MR18=0x2209, DQSOSC=392, MR23=63, INC=24, DEC=16
8236 12:43:37.889379 [RxdqsGatingPostProcess] freq 1600
8237 12:43:37.892710 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8238 12:43:37.896045 best DQS0 dly(2T, 0.5T) = (1, 1)
8239 12:43:37.899553 best DQS1 dly(2T, 0.5T) = (1, 1)
8240 12:43:37.902903 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8241 12:43:37.906348 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8242 12:43:37.909461 best DQS0 dly(2T, 0.5T) = (1, 1)
8243 12:43:37.912777 best DQS1 dly(2T, 0.5T) = (1, 1)
8244 12:43:37.916006 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8245 12:43:37.919511 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8246 12:43:37.922687 Pre-setting of DQS Precalculation
8247 12:43:37.926120 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8248 12:43:37.926563 ==
8249 12:43:37.929405 Dram Type= 6, Freq= 0, CH_1, rank 0
8250 12:43:37.932562 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8251 12:43:37.933017 ==
8252 12:43:37.939349 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8253 12:43:37.942893 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8254 12:43:37.948702 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8255 12:43:37.952329 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8256 12:43:37.962420 [CA 0] Center 42 (13~72) winsize 60
8257 12:43:37.965540 [CA 1] Center 42 (13~72) winsize 60
8258 12:43:37.968975 [CA 2] Center 39 (10~68) winsize 59
8259 12:43:37.972024 [CA 3] Center 39 (10~68) winsize 59
8260 12:43:37.975879 [CA 4] Center 39 (10~68) winsize 59
8261 12:43:37.979031 [CA 5] Center 37 (8~67) winsize 60
8262 12:43:37.979115
8263 12:43:37.982046 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8264 12:43:37.982171
8265 12:43:37.985830 [CATrainingPosCal] consider 1 rank data
8266 12:43:37.988840 u2DelayCellTimex100 = 290/100 ps
8267 12:43:37.992192 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8268 12:43:37.998721 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8269 12:43:38.002189 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8270 12:43:38.005476 CA3 delay=39 (10~68),Diff = 2 PI (6 cell)
8271 12:43:38.008727 CA4 delay=39 (10~68),Diff = 2 PI (6 cell)
8272 12:43:38.012045 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8273 12:43:38.012129
8274 12:43:38.015409 CA PerBit enable=1, Macro0, CA PI delay=37
8275 12:43:38.015498
8276 12:43:38.018721 [CBTSetCACLKResult] CA Dly = 37
8277 12:43:38.022142 CS Dly: 10 (0~41)
8278 12:43:38.025601 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8279 12:43:38.028983 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8280 12:43:38.029097 ==
8281 12:43:38.032245 Dram Type= 6, Freq= 0, CH_1, rank 1
8282 12:43:38.035517 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8283 12:43:38.038850 ==
8284 12:43:38.041959 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8285 12:43:38.045680 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8286 12:43:38.052484 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8287 12:43:38.055681 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8288 12:43:38.066250 [CA 0] Center 42 (13~72) winsize 60
8289 12:43:38.069787 [CA 1] Center 42 (13~72) winsize 60
8290 12:43:38.072739 [CA 2] Center 38 (9~68) winsize 60
8291 12:43:38.076293 [CA 3] Center 38 (9~68) winsize 60
8292 12:43:38.079553 [CA 4] Center 39 (9~69) winsize 61
8293 12:43:38.082676 [CA 5] Center 37 (8~67) winsize 60
8294 12:43:38.083165
8295 12:43:38.086651 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8296 12:43:38.087061
8297 12:43:38.089746 [CATrainingPosCal] consider 2 rank data
8298 12:43:38.092780 u2DelayCellTimex100 = 290/100 ps
8299 12:43:38.096079 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8300 12:43:38.102554 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8301 12:43:38.105958 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8302 12:43:38.109369 CA3 delay=39 (10~68),Diff = 2 PI (6 cell)
8303 12:43:38.112511 CA4 delay=39 (10~68),Diff = 2 PI (6 cell)
8304 12:43:38.115956 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8305 12:43:38.116547
8306 12:43:38.119206 CA PerBit enable=1, Macro0, CA PI delay=37
8307 12:43:38.119835
8308 12:43:38.122526 [CBTSetCACLKResult] CA Dly = 37
8309 12:43:38.126443 CS Dly: 12 (0~45)
8310 12:43:38.129672 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8311 12:43:38.132982 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8312 12:43:38.133394
8313 12:43:38.135737 ----->DramcWriteLeveling(PI) begin...
8314 12:43:38.136245 ==
8315 12:43:38.139047 Dram Type= 6, Freq= 0, CH_1, rank 0
8316 12:43:38.145829 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8317 12:43:38.146243 ==
8318 12:43:38.149328 Write leveling (Byte 0): 27 => 27
8319 12:43:38.149737 Write leveling (Byte 1): 28 => 28
8320 12:43:38.152273 DramcWriteLeveling(PI) end<-----
8321 12:43:38.152757
8322 12:43:38.156051 ==
8323 12:43:38.156487 Dram Type= 6, Freq= 0, CH_1, rank 0
8324 12:43:38.162798 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8325 12:43:38.163266 ==
8326 12:43:38.165787 [Gating] SW mode calibration
8327 12:43:38.172480 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8328 12:43:38.175652 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8329 12:43:38.182477 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8330 12:43:38.185491 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8331 12:43:38.189362 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8332 12:43:38.195768 1 4 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
8333 12:43:38.198929 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8334 12:43:38.202443 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8335 12:43:38.209469 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8336 12:43:38.212492 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8337 12:43:38.215816 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8338 12:43:38.222338 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8339 12:43:38.225853 1 5 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
8340 12:43:38.229217 1 5 12 | B1->B0 | 2727 2323 | 0 0 | (1 0) (1 0)
8341 12:43:38.235882 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8342 12:43:38.238503 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8343 12:43:38.241876 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8344 12:43:38.245673 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8345 12:43:38.252424 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 12:43:38.255828 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8347 12:43:38.258873 1 6 8 | B1->B0 | 2424 3b3b | 0 1 | (0 0) (0 0)
8348 12:43:38.265364 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8349 12:43:38.268843 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8350 12:43:38.271904 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8351 12:43:38.278653 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8352 12:43:38.281713 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8353 12:43:38.285122 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8354 12:43:38.291468 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8355 12:43:38.294880 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8356 12:43:38.298251 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8357 12:43:38.304683 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 12:43:38.307956 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 12:43:38.311224 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 12:43:38.318163 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 12:43:38.321502 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 12:43:38.324715 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 12:43:38.330993 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 12:43:38.334369 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 12:43:38.337831 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 12:43:38.344472 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 12:43:38.347740 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 12:43:38.351249 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 12:43:38.357753 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 12:43:38.360977 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 12:43:38.364275 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8372 12:43:38.371416 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8373 12:43:38.371491 Total UI for P1: 0, mck2ui 16
8374 12:43:38.377719 best dqsien dly found for B1: ( 1, 9, 10)
8375 12:43:38.381393 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8376 12:43:38.384520 Total UI for P1: 0, mck2ui 16
8377 12:43:38.387723 best dqsien dly found for B0: ( 1, 9, 10)
8378 12:43:38.391638 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8379 12:43:38.394796 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8380 12:43:38.394871
8381 12:43:38.397957 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8382 12:43:38.401288 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8383 12:43:38.404394 [Gating] SW calibration Done
8384 12:43:38.404468 ==
8385 12:43:38.407840 Dram Type= 6, Freq= 0, CH_1, rank 0
8386 12:43:38.410928 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8387 12:43:38.411012 ==
8388 12:43:38.414539 RX Vref Scan: 0
8389 12:43:38.414627
8390 12:43:38.417701 RX Vref 0 -> 0, step: 1
8391 12:43:38.417802
8392 12:43:38.417896 RX Delay 0 -> 252, step: 8
8393 12:43:38.424789 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8394 12:43:38.428001 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8395 12:43:38.431326 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8396 12:43:38.434601 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8397 12:43:38.437916 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8398 12:43:38.444338 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8399 12:43:38.447766 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8400 12:43:38.451252 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8401 12:43:38.454755 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8402 12:43:38.458061 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8403 12:43:38.464777 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8404 12:43:38.467912 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8405 12:43:38.471164 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8406 12:43:38.474365 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8407 12:43:38.477725 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8408 12:43:38.484313 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8409 12:43:38.484742 ==
8410 12:43:38.487871 Dram Type= 6, Freq= 0, CH_1, rank 0
8411 12:43:38.490895 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8412 12:43:38.491397 ==
8413 12:43:38.491774 DQS Delay:
8414 12:43:38.494602 DQS0 = 0, DQS1 = 0
8415 12:43:38.495103 DQM Delay:
8416 12:43:38.497664 DQM0 = 136, DQM1 = 132
8417 12:43:38.498144 DQ Delay:
8418 12:43:38.500743 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8419 12:43:38.504655 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8420 12:43:38.507557 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8421 12:43:38.510735 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =143
8422 12:43:38.511201
8423 12:43:38.514398
8424 12:43:38.514832 ==
8425 12:43:38.517551 Dram Type= 6, Freq= 0, CH_1, rank 0
8426 12:43:38.520782 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8427 12:43:38.521223 ==
8428 12:43:38.521590
8429 12:43:38.521930
8430 12:43:38.523859 TX Vref Scan disable
8431 12:43:38.524321 == TX Byte 0 ==
8432 12:43:38.531086 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8433 12:43:38.534162 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8434 12:43:38.534694 == TX Byte 1 ==
8435 12:43:38.540744 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8436 12:43:38.544044 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8437 12:43:38.544478 ==
8438 12:43:38.547624 Dram Type= 6, Freq= 0, CH_1, rank 0
8439 12:43:38.550757 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8440 12:43:38.551180 ==
8441 12:43:38.564081
8442 12:43:38.567699 TX Vref early break, caculate TX vref
8443 12:43:38.570051 TX Vref=16, minBit 0, minWin=22, winSum=375
8444 12:43:38.573932 TX Vref=18, minBit 0, minWin=23, winSum=384
8445 12:43:38.577208 TX Vref=20, minBit 1, minWin=23, winSum=396
8446 12:43:38.580591 TX Vref=22, minBit 0, minWin=24, winSum=405
8447 12:43:38.583940 TX Vref=24, minBit 0, minWin=24, winSum=410
8448 12:43:38.590429 TX Vref=26, minBit 0, minWin=25, winSum=422
8449 12:43:38.593412 TX Vref=28, minBit 0, minWin=25, winSum=422
8450 12:43:38.597083 TX Vref=30, minBit 0, minWin=24, winSum=417
8451 12:43:38.600219 TX Vref=32, minBit 0, minWin=24, winSum=413
8452 12:43:38.603808 TX Vref=34, minBit 0, minWin=23, winSum=398
8453 12:43:38.610507 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 26
8454 12:43:38.610936
8455 12:43:38.613698 Final TX Range 0 Vref 26
8456 12:43:38.614115
8457 12:43:38.614543 ==
8458 12:43:38.616678 Dram Type= 6, Freq= 0, CH_1, rank 0
8459 12:43:38.619890 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8460 12:43:38.620438 ==
8461 12:43:38.620994
8462 12:43:38.621347
8463 12:43:38.623512 TX Vref Scan disable
8464 12:43:38.630454 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8465 12:43:38.630910 == TX Byte 0 ==
8466 12:43:38.633444 u2DelayCellOfst[0]=13 cells (4 PI)
8467 12:43:38.636593 u2DelayCellOfst[1]=10 cells (3 PI)
8468 12:43:38.639802 u2DelayCellOfst[2]=0 cells (0 PI)
8469 12:43:38.643576 u2DelayCellOfst[3]=6 cells (2 PI)
8470 12:43:38.646565 u2DelayCellOfst[4]=6 cells (2 PI)
8471 12:43:38.650523 u2DelayCellOfst[5]=16 cells (5 PI)
8472 12:43:38.651006 u2DelayCellOfst[6]=16 cells (5 PI)
8473 12:43:38.653306 u2DelayCellOfst[7]=6 cells (2 PI)
8474 12:43:38.660014 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8475 12:43:38.663237 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8476 12:43:38.663676 == TX Byte 1 ==
8477 12:43:38.666543 u2DelayCellOfst[8]=0 cells (0 PI)
8478 12:43:38.670135 u2DelayCellOfst[9]=3 cells (1 PI)
8479 12:43:38.673553 u2DelayCellOfst[10]=13 cells (4 PI)
8480 12:43:38.677294 u2DelayCellOfst[11]=6 cells (2 PI)
8481 12:43:38.680312 u2DelayCellOfst[12]=16 cells (5 PI)
8482 12:43:38.683672 u2DelayCellOfst[13]=16 cells (5 PI)
8483 12:43:38.687126 u2DelayCellOfst[14]=20 cells (6 PI)
8484 12:43:38.690364 u2DelayCellOfst[15]=16 cells (5 PI)
8485 12:43:38.693711 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8486 12:43:38.697055 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8487 12:43:38.700098 DramC Write-DBI on
8488 12:43:38.700514 ==
8489 12:43:38.703308 Dram Type= 6, Freq= 0, CH_1, rank 0
8490 12:43:38.706989 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8491 12:43:38.707417 ==
8492 12:43:38.707850
8493 12:43:38.708173
8494 12:43:38.710224 TX Vref Scan disable
8495 12:43:38.713905 == TX Byte 0 ==
8496 12:43:38.716891 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8497 12:43:38.717371 == TX Byte 1 ==
8498 12:43:38.723936 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8499 12:43:38.724372 DramC Write-DBI off
8500 12:43:38.724939
8501 12:43:38.727071 [DATLAT]
8502 12:43:38.727655 Freq=1600, CH1 RK0
8503 12:43:38.728322
8504 12:43:38.730500 DATLAT Default: 0xf
8505 12:43:38.730951 0, 0xFFFF, sum = 0
8506 12:43:38.733567 1, 0xFFFF, sum = 0
8507 12:43:38.734071 2, 0xFFFF, sum = 0
8508 12:43:38.736651 3, 0xFFFF, sum = 0
8509 12:43:38.737134 4, 0xFFFF, sum = 0
8510 12:43:38.739930 5, 0xFFFF, sum = 0
8511 12:43:38.740355 6, 0xFFFF, sum = 0
8512 12:43:38.743186 7, 0xFFFF, sum = 0
8513 12:43:38.743616 8, 0xFFFF, sum = 0
8514 12:43:38.746996 9, 0xFFFF, sum = 0
8515 12:43:38.747425 10, 0xFFFF, sum = 0
8516 12:43:38.750335 11, 0xFFFF, sum = 0
8517 12:43:38.753268 12, 0xFFFF, sum = 0
8518 12:43:38.753690 13, 0xFFFF, sum = 0
8519 12:43:38.757025 14, 0x0, sum = 1
8520 12:43:38.757451 15, 0x0, sum = 2
8521 12:43:38.757788 16, 0x0, sum = 3
8522 12:43:38.760469 17, 0x0, sum = 4
8523 12:43:38.760930 best_step = 15
8524 12:43:38.761270
8525 12:43:38.763631 ==
8526 12:43:38.764052 Dram Type= 6, Freq= 0, CH_1, rank 0
8527 12:43:38.770466 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8528 12:43:38.770904 ==
8529 12:43:38.771237 RX Vref Scan: 1
8530 12:43:38.771547
8531 12:43:38.773581 Set Vref Range= 24 -> 127
8532 12:43:38.774000
8533 12:43:38.776960 RX Vref 24 -> 127, step: 1
8534 12:43:38.777378
8535 12:43:38.780122 RX Delay 27 -> 252, step: 4
8536 12:43:38.780542
8537 12:43:38.783200 Set Vref, RX VrefLevel [Byte0]: 24
8538 12:43:38.786434 [Byte1]: 24
8539 12:43:38.786873
8540 12:43:38.789847 Set Vref, RX VrefLevel [Byte0]: 25
8541 12:43:38.792748 [Byte1]: 25
8542 12:43:38.792884
8543 12:43:38.796150 Set Vref, RX VrefLevel [Byte0]: 26
8544 12:43:38.799492 [Byte1]: 26
8545 12:43:38.799573
8546 12:43:38.803373 Set Vref, RX VrefLevel [Byte0]: 27
8547 12:43:38.806588 [Byte1]: 27
8548 12:43:38.809887
8549 12:43:38.809968 Set Vref, RX VrefLevel [Byte0]: 28
8550 12:43:38.813885 [Byte1]: 28
8551 12:43:38.818149
8552 12:43:38.818241 Set Vref, RX VrefLevel [Byte0]: 29
8553 12:43:38.821211 [Byte1]: 29
8554 12:43:38.825371
8555 12:43:38.825453 Set Vref, RX VrefLevel [Byte0]: 30
8556 12:43:38.828502 [Byte1]: 30
8557 12:43:38.832985
8558 12:43:38.833066 Set Vref, RX VrefLevel [Byte0]: 31
8559 12:43:38.835755 [Byte1]: 31
8560 12:43:38.840328
8561 12:43:38.840408 Set Vref, RX VrefLevel [Byte0]: 32
8562 12:43:38.843399 [Byte1]: 32
8563 12:43:38.847828
8564 12:43:38.847909 Set Vref, RX VrefLevel [Byte0]: 33
8565 12:43:38.851096 [Byte1]: 33
8566 12:43:38.855537
8567 12:43:38.855618 Set Vref, RX VrefLevel [Byte0]: 34
8568 12:43:38.858828 [Byte1]: 34
8569 12:43:38.863218
8570 12:43:38.863305 Set Vref, RX VrefLevel [Byte0]: 35
8571 12:43:38.866388 [Byte1]: 35
8572 12:43:38.870414
8573 12:43:38.870496 Set Vref, RX VrefLevel [Byte0]: 36
8574 12:43:38.873731 [Byte1]: 36
8575 12:43:38.877725
8576 12:43:38.877806 Set Vref, RX VrefLevel [Byte0]: 37
8577 12:43:38.881550 [Byte1]: 37
8578 12:43:38.885485
8579 12:43:38.885566 Set Vref, RX VrefLevel [Byte0]: 38
8580 12:43:38.889274 [Byte1]: 38
8581 12:43:38.892707
8582 12:43:38.892854 Set Vref, RX VrefLevel [Byte0]: 39
8583 12:43:38.896622 [Byte1]: 39
8584 12:43:38.900517
8585 12:43:38.900596 Set Vref, RX VrefLevel [Byte0]: 40
8586 12:43:38.903868 [Byte1]: 40
8587 12:43:38.908447
8588 12:43:38.908518 Set Vref, RX VrefLevel [Byte0]: 41
8589 12:43:38.911743 [Byte1]: 41
8590 12:43:38.915608
8591 12:43:38.915681 Set Vref, RX VrefLevel [Byte0]: 42
8592 12:43:38.919004 [Byte1]: 42
8593 12:43:38.923351
8594 12:43:38.923451 Set Vref, RX VrefLevel [Byte0]: 43
8595 12:43:38.926469 [Byte1]: 43
8596 12:43:38.930839
8597 12:43:38.930948 Set Vref, RX VrefLevel [Byte0]: 44
8598 12:43:38.933829 [Byte1]: 44
8599 12:43:38.938525
8600 12:43:38.938617 Set Vref, RX VrefLevel [Byte0]: 45
8601 12:43:38.941507 [Byte1]: 45
8602 12:43:38.945829
8603 12:43:38.945940 Set Vref, RX VrefLevel [Byte0]: 46
8604 12:43:38.948889 [Byte1]: 46
8605 12:43:38.953509
8606 12:43:38.953654 Set Vref, RX VrefLevel [Byte0]: 47
8607 12:43:38.956627 [Byte1]: 47
8608 12:43:38.961014
8609 12:43:38.961147 Set Vref, RX VrefLevel [Byte0]: 48
8610 12:43:38.964204 [Byte1]: 48
8611 12:43:38.968579
8612 12:43:38.968778 Set Vref, RX VrefLevel [Byte0]: 49
8613 12:43:38.971931 [Byte1]: 49
8614 12:43:38.976293
8615 12:43:38.976504 Set Vref, RX VrefLevel [Byte0]: 50
8616 12:43:38.979766 [Byte1]: 50
8617 12:43:38.983724
8618 12:43:38.984126 Set Vref, RX VrefLevel [Byte0]: 51
8619 12:43:38.987081 [Byte1]: 51
8620 12:43:38.991613
8621 12:43:38.992035 Set Vref, RX VrefLevel [Byte0]: 52
8622 12:43:38.994766 [Byte1]: 52
8623 12:43:38.998663
8624 12:43:38.999058 Set Vref, RX VrefLevel [Byte0]: 53
8625 12:43:39.002188 [Byte1]: 53
8626 12:43:39.006192
8627 12:43:39.006672 Set Vref, RX VrefLevel [Byte0]: 54
8628 12:43:39.009433 [Byte1]: 54
8629 12:43:39.013936
8630 12:43:39.014428 Set Vref, RX VrefLevel [Byte0]: 55
8631 12:43:39.017260 [Byte1]: 55
8632 12:43:39.021104
8633 12:43:39.021530 Set Vref, RX VrefLevel [Byte0]: 56
8634 12:43:39.024509 [Byte1]: 56
8635 12:43:39.029098
8636 12:43:39.029523 Set Vref, RX VrefLevel [Byte0]: 57
8637 12:43:39.032382 [Byte1]: 57
8638 12:43:39.036858
8639 12:43:39.037306 Set Vref, RX VrefLevel [Byte0]: 58
8640 12:43:39.039792 [Byte1]: 58
8641 12:43:39.044098
8642 12:43:39.044480 Set Vref, RX VrefLevel [Byte0]: 59
8643 12:43:39.047385 [Byte1]: 59
8644 12:43:39.051728
8645 12:43:39.052293 Set Vref, RX VrefLevel [Byte0]: 60
8646 12:43:39.054922 [Byte1]: 60
8647 12:43:39.059242
8648 12:43:39.059690 Set Vref, RX VrefLevel [Byte0]: 61
8649 12:43:39.062389 [Byte1]: 61
8650 12:43:39.067081
8651 12:43:39.067664 Set Vref, RX VrefLevel [Byte0]: 62
8652 12:43:39.069630 [Byte1]: 62
8653 12:43:39.073991
8654 12:43:39.074438 Set Vref, RX VrefLevel [Byte0]: 63
8655 12:43:39.077627 [Byte1]: 63
8656 12:43:39.081923
8657 12:43:39.082543 Set Vref, RX VrefLevel [Byte0]: 64
8658 12:43:39.085295 [Byte1]: 64
8659 12:43:39.089246
8660 12:43:39.089669 Set Vref, RX VrefLevel [Byte0]: 65
8661 12:43:39.092432 [Byte1]: 65
8662 12:43:39.097063
8663 12:43:39.097488 Set Vref, RX VrefLevel [Byte0]: 66
8664 12:43:39.100149 [Byte1]: 66
8665 12:43:39.104293
8666 12:43:39.104714 Set Vref, RX VrefLevel [Byte0]: 67
8667 12:43:39.107677 [Byte1]: 67
8668 12:43:39.111568
8669 12:43:39.112108 Set Vref, RX VrefLevel [Byte0]: 68
8670 12:43:39.114796 [Byte1]: 68
8671 12:43:39.119355
8672 12:43:39.119809 Set Vref, RX VrefLevel [Byte0]: 69
8673 12:43:39.122682 [Byte1]: 69
8674 12:43:39.127273
8675 12:43:39.127696 Set Vref, RX VrefLevel [Byte0]: 70
8676 12:43:39.130500 [Byte1]: 70
8677 12:43:39.134430
8678 12:43:39.134849 Set Vref, RX VrefLevel [Byte0]: 71
8679 12:43:39.137752 [Byte1]: 71
8680 12:43:39.141786
8681 12:43:39.142218 Set Vref, RX VrefLevel [Byte0]: 72
8682 12:43:39.145196 [Byte1]: 72
8683 12:43:39.149606
8684 12:43:39.150107 Set Vref, RX VrefLevel [Byte0]: 73
8685 12:43:39.152562 [Byte1]: 73
8686 12:43:39.156890
8687 12:43:39.157378 Set Vref, RX VrefLevel [Byte0]: 74
8688 12:43:39.160630 [Byte1]: 74
8689 12:43:39.164882
8690 12:43:39.165325 Set Vref, RX VrefLevel [Byte0]: 75
8691 12:43:39.168073 [Byte1]: 75
8692 12:43:39.172017
8693 12:43:39.172577 Set Vref, RX VrefLevel [Byte0]: 76
8694 12:43:39.175286 [Byte1]: 76
8695 12:43:39.179649
8696 12:43:39.180064 Final RX Vref Byte 0 = 57 to rank0
8697 12:43:39.182831 Final RX Vref Byte 1 = 56 to rank0
8698 12:43:39.186490 Final RX Vref Byte 0 = 57 to rank1
8699 12:43:39.189666 Final RX Vref Byte 1 = 56 to rank1==
8700 12:43:39.192885 Dram Type= 6, Freq= 0, CH_1, rank 0
8701 12:43:39.199179 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8702 12:43:39.199623 ==
8703 12:43:39.199960 DQS Delay:
8704 12:43:39.200269 DQS0 = 0, DQS1 = 0
8705 12:43:39.202466 DQM Delay:
8706 12:43:39.203013 DQM0 = 134, DQM1 = 131
8707 12:43:39.206478 DQ Delay:
8708 12:43:39.209661 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8709 12:43:39.213141 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =134
8710 12:43:39.215715 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =124
8711 12:43:39.219551 DQ12 =140, DQ13 =140, DQ14 =140, DQ15 =140
8712 12:43:39.219973
8713 12:43:39.220329
8714 12:43:39.220639
8715 12:43:39.222654 [DramC_TX_OE_Calibration] TA2
8716 12:43:39.226026 Original DQ_B0 (3 6) =30, OEN = 27
8717 12:43:39.229352 Original DQ_B1 (3 6) =30, OEN = 27
8718 12:43:39.232560 24, 0x0, End_B0=24 End_B1=24
8719 12:43:39.233048 25, 0x0, End_B0=25 End_B1=25
8720 12:43:39.235936 26, 0x0, End_B0=26 End_B1=26
8721 12:43:39.239100 27, 0x0, End_B0=27 End_B1=27
8722 12:43:39.242389 28, 0x0, End_B0=28 End_B1=28
8723 12:43:39.245575 29, 0x0, End_B0=29 End_B1=29
8724 12:43:39.246001 30, 0x0, End_B0=30 End_B1=30
8725 12:43:39.249506 31, 0x4545, End_B0=30 End_B1=30
8726 12:43:39.252647 Byte0 end_step=30 best_step=27
8727 12:43:39.255949 Byte1 end_step=30 best_step=27
8728 12:43:39.259091 Byte0 TX OE(2T, 0.5T) = (3, 3)
8729 12:43:39.262585 Byte1 TX OE(2T, 0.5T) = (3, 3)
8730 12:43:39.263036
8731 12:43:39.263375
8732 12:43:39.269441 [DQSOSCAuto] RK0, (LSB)MR18= 0x1724, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8733 12:43:39.272451 CH1 RK0: MR19=303, MR18=1724
8734 12:43:39.279375 CH1_RK0: MR19=0x303, MR18=0x1724, DQSOSC=391, MR23=63, INC=24, DEC=16
8735 12:43:39.279914
8736 12:43:39.282298 ----->DramcWriteLeveling(PI) begin...
8737 12:43:39.282729 ==
8738 12:43:39.285606 Dram Type= 6, Freq= 0, CH_1, rank 1
8739 12:43:39.288883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8740 12:43:39.289358 ==
8741 12:43:39.292575 Write leveling (Byte 0): 26 => 26
8742 12:43:39.295697 Write leveling (Byte 1): 30 => 30
8743 12:43:39.299266 DramcWriteLeveling(PI) end<-----
8744 12:43:39.299690
8745 12:43:39.300027 ==
8746 12:43:39.302426 Dram Type= 6, Freq= 0, CH_1, rank 1
8747 12:43:39.305933 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8748 12:43:39.306507 ==
8749 12:43:39.309125 [Gating] SW mode calibration
8750 12:43:39.315776 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8751 12:43:39.322409 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8752 12:43:39.325793 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8753 12:43:39.328908 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8754 12:43:39.335308 1 4 8 | B1->B0 | 2c2c 2323 | 1 0 | (0 0) (0 0)
8755 12:43:39.338916 1 4 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
8756 12:43:39.342188 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8757 12:43:39.348714 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8758 12:43:39.351993 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8759 12:43:39.355743 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8760 12:43:39.362361 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8761 12:43:39.365385 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8762 12:43:39.369050 1 5 8 | B1->B0 | 3232 3434 | 1 1 | (1 0) (1 1)
8763 12:43:39.375531 1 5 12 | B1->B0 | 2626 3232 | 0 1 | (0 0) (1 0)
8764 12:43:39.378956 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8765 12:43:39.382437 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8766 12:43:39.388766 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 12:43:39.392249 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 12:43:39.395471 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 12:43:39.402613 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 12:43:39.405725 1 6 8 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
8771 12:43:39.408993 1 6 12 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
8772 12:43:39.412525 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8773 12:43:39.419147 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8774 12:43:39.422361 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8775 12:43:39.425833 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8776 12:43:39.432305 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 12:43:39.435289 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8778 12:43:39.438682 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8779 12:43:39.445361 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8780 12:43:39.448795 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8781 12:43:39.452162 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 12:43:39.459282 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 12:43:39.462531 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 12:43:39.465942 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 12:43:39.472225 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 12:43:39.475575 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 12:43:39.478790 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 12:43:39.485966 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 12:43:39.489046 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 12:43:39.492122 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 12:43:39.499056 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 12:43:39.502388 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 12:43:39.505277 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 12:43:39.512440 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8795 12:43:39.515773 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8796 12:43:39.518832 Total UI for P1: 0, mck2ui 16
8797 12:43:39.522208 best dqsien dly found for B1: ( 1, 9, 8)
8798 12:43:39.525294 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 12:43:39.528722 Total UI for P1: 0, mck2ui 16
8800 12:43:39.531976 best dqsien dly found for B0: ( 1, 9, 12)
8801 12:43:39.535188 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8802 12:43:39.538417 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8803 12:43:39.538868
8804 12:43:39.541682 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8805 12:43:39.548598 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8806 12:43:39.549179 [Gating] SW calibration Done
8807 12:43:39.549552 ==
8808 12:43:39.551717 Dram Type= 6, Freq= 0, CH_1, rank 1
8809 12:43:39.558446 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8810 12:43:39.558939 ==
8811 12:43:39.559395 RX Vref Scan: 0
8812 12:43:39.559800
8813 12:43:39.561862 RX Vref 0 -> 0, step: 1
8814 12:43:39.562291
8815 12:43:39.565051 RX Delay 0 -> 252, step: 8
8816 12:43:39.568303 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8817 12:43:39.571757 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8818 12:43:39.574876 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8819 12:43:39.582298 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8820 12:43:39.585207 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8821 12:43:39.588434 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8822 12:43:39.591699 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8823 12:43:39.595296 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8824 12:43:39.598557 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8825 12:43:39.605045 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8826 12:43:39.608717 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8827 12:43:39.611379 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8828 12:43:39.614646 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8829 12:43:39.621190 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8830 12:43:39.625116 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8831 12:43:39.628214 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8832 12:43:39.628641 ==
8833 12:43:39.631316 Dram Type= 6, Freq= 0, CH_1, rank 1
8834 12:43:39.634581 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8835 12:43:39.635004 ==
8836 12:43:39.637999 DQS Delay:
8837 12:43:39.638456 DQS0 = 0, DQS1 = 0
8838 12:43:39.641308 DQM Delay:
8839 12:43:39.641777 DQM0 = 135, DQM1 = 133
8840 12:43:39.642124 DQ Delay:
8841 12:43:39.648292 DQ0 =139, DQ1 =135, DQ2 =119, DQ3 =131
8842 12:43:39.651632 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8843 12:43:39.655123 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8844 12:43:39.657916 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8845 12:43:39.658338
8846 12:43:39.658748
8847 12:43:39.659079 ==
8848 12:43:39.661256 Dram Type= 6, Freq= 0, CH_1, rank 1
8849 12:43:39.664543 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8850 12:43:39.665041 ==
8851 12:43:39.665388
8852 12:43:39.665702
8853 12:43:39.667925 TX Vref Scan disable
8854 12:43:39.671194 == TX Byte 0 ==
8855 12:43:39.674574 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8856 12:43:39.677796 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8857 12:43:39.681223 == TX Byte 1 ==
8858 12:43:39.684596 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8859 12:43:39.687813 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8860 12:43:39.688252 ==
8861 12:43:39.691138 Dram Type= 6, Freq= 0, CH_1, rank 1
8862 12:43:39.694761 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8863 12:43:39.697917 ==
8864 12:43:39.708987
8865 12:43:39.712213 TX Vref early break, caculate TX vref
8866 12:43:39.715540 TX Vref=16, minBit 1, minWin=23, winSum=383
8867 12:43:39.719370 TX Vref=18, minBit 0, minWin=24, winSum=395
8868 12:43:39.722727 TX Vref=20, minBit 1, minWin=24, winSum=404
8869 12:43:39.725882 TX Vref=22, minBit 6, minWin=24, winSum=409
8870 12:43:39.729076 TX Vref=24, minBit 6, minWin=24, winSum=416
8871 12:43:39.735814 TX Vref=26, minBit 0, minWin=25, winSum=421
8872 12:43:39.739112 TX Vref=28, minBit 0, minWin=25, winSum=427
8873 12:43:39.742384 TX Vref=30, minBit 0, minWin=25, winSum=417
8874 12:43:39.745721 TX Vref=32, minBit 6, minWin=24, winSum=409
8875 12:43:39.748932 TX Vref=34, minBit 0, minWin=24, winSum=402
8876 12:43:39.755330 [TxChooseVref] Worse bit 0, Min win 25, Win sum 427, Final Vref 28
8877 12:43:39.755801
8878 12:43:39.758796 Final TX Range 0 Vref 28
8879 12:43:39.759221
8880 12:43:39.759556 ==
8881 12:43:39.762130 Dram Type= 6, Freq= 0, CH_1, rank 1
8882 12:43:39.765551 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8883 12:43:39.765978 ==
8884 12:43:39.766316
8885 12:43:39.766632
8886 12:43:39.768960 TX Vref Scan disable
8887 12:43:39.775483 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8888 12:43:39.775963 == TX Byte 0 ==
8889 12:43:39.778795 u2DelayCellOfst[0]=16 cells (5 PI)
8890 12:43:39.781975 u2DelayCellOfst[1]=13 cells (4 PI)
8891 12:43:39.785941 u2DelayCellOfst[2]=0 cells (0 PI)
8892 12:43:39.789152 u2DelayCellOfst[3]=6 cells (2 PI)
8893 12:43:39.792586 u2DelayCellOfst[4]=6 cells (2 PI)
8894 12:43:39.795299 u2DelayCellOfst[5]=16 cells (5 PI)
8895 12:43:39.799162 u2DelayCellOfst[6]=20 cells (6 PI)
8896 12:43:39.799590 u2DelayCellOfst[7]=6 cells (2 PI)
8897 12:43:39.805730 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8898 12:43:39.808795 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8899 12:43:39.809309 == TX Byte 1 ==
8900 12:43:39.811849 u2DelayCellOfst[8]=0 cells (0 PI)
8901 12:43:39.815622 u2DelayCellOfst[9]=3 cells (1 PI)
8902 12:43:39.818703 u2DelayCellOfst[10]=13 cells (4 PI)
8903 12:43:39.822103 u2DelayCellOfst[11]=3 cells (1 PI)
8904 12:43:39.825352 u2DelayCellOfst[12]=13 cells (4 PI)
8905 12:43:39.828408 u2DelayCellOfst[13]=16 cells (5 PI)
8906 12:43:39.832305 u2DelayCellOfst[14]=16 cells (5 PI)
8907 12:43:39.835450 u2DelayCellOfst[15]=16 cells (5 PI)
8908 12:43:39.838664 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8909 12:43:39.845082 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8910 12:43:39.845516 DramC Write-DBI on
8911 12:43:39.845945 ==
8912 12:43:39.848774 Dram Type= 6, Freq= 0, CH_1, rank 1
8913 12:43:39.852306 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8914 12:43:39.852744 ==
8915 12:43:39.853209
8916 12:43:39.855287
8917 12:43:39.855724 TX Vref Scan disable
8918 12:43:39.858859 == TX Byte 0 ==
8919 12:43:39.861959 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8920 12:43:39.865221 == TX Byte 1 ==
8921 12:43:39.868592 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8922 12:43:39.869126 DramC Write-DBI off
8923 12:43:39.869482
8924 12:43:39.872016 [DATLAT]
8925 12:43:39.872462 Freq=1600, CH1 RK1
8926 12:43:39.873004
8927 12:43:39.875371 DATLAT Default: 0xf
8928 12:43:39.875877 0, 0xFFFF, sum = 0
8929 12:43:39.878574 1, 0xFFFF, sum = 0
8930 12:43:39.879083 2, 0xFFFF, sum = 0
8931 12:43:39.881969 3, 0xFFFF, sum = 0
8932 12:43:39.882578 4, 0xFFFF, sum = 0
8933 12:43:39.885197 5, 0xFFFF, sum = 0
8934 12:43:39.885807 6, 0xFFFF, sum = 0
8935 12:43:39.888325 7, 0xFFFF, sum = 0
8936 12:43:39.892300 8, 0xFFFF, sum = 0
8937 12:43:39.892729 9, 0xFFFF, sum = 0
8938 12:43:39.895608 10, 0xFFFF, sum = 0
8939 12:43:39.896113 11, 0xFFFF, sum = 0
8940 12:43:39.898575 12, 0xFFFF, sum = 0
8941 12:43:39.899174 13, 0xFFFF, sum = 0
8942 12:43:39.901666 14, 0x0, sum = 1
8943 12:43:39.902264 15, 0x0, sum = 2
8944 12:43:39.905393 16, 0x0, sum = 3
8945 12:43:39.905832 17, 0x0, sum = 4
8946 12:43:39.906174 best_step = 15
8947 12:43:39.908611
8948 12:43:39.909208 ==
8949 12:43:39.911722 Dram Type= 6, Freq= 0, CH_1, rank 1
8950 12:43:39.915421 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8951 12:43:39.915940 ==
8952 12:43:39.916285 RX Vref Scan: 0
8953 12:43:39.916629
8954 12:43:39.918486 RX Vref 0 -> 0, step: 1
8955 12:43:39.918940
8956 12:43:39.921603 RX Delay 19 -> 252, step: 4
8957 12:43:39.925583 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8958 12:43:39.931676 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
8959 12:43:39.935004 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8960 12:43:39.938268 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8961 12:43:39.941559 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8962 12:43:39.945470 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8963 12:43:39.948686 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8964 12:43:39.955020 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8965 12:43:39.958130 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8966 12:43:39.961969 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8967 12:43:39.964557 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8968 12:43:39.968471 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8969 12:43:39.974542 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8970 12:43:39.978602 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8971 12:43:39.981695 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8972 12:43:39.984974 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8973 12:43:39.985472 ==
8974 12:43:39.988303 Dram Type= 6, Freq= 0, CH_1, rank 1
8975 12:43:39.994899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8976 12:43:39.995340 ==
8977 12:43:39.995717 DQS Delay:
8978 12:43:39.996069 DQS0 = 0, DQS1 = 0
8979 12:43:39.998613 DQM Delay:
8980 12:43:39.999037 DQM0 = 134, DQM1 = 130
8981 12:43:40.001387 DQ Delay:
8982 12:43:40.004899 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
8983 12:43:40.008194 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8984 12:43:40.011905 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
8985 12:43:40.015086 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8986 12:43:40.015644
8987 12:43:40.016071
8988 12:43:40.016540
8989 12:43:40.018393 [DramC_TX_OE_Calibration] TA2
8990 12:43:40.021518 Original DQ_B0 (3 6) =30, OEN = 27
8991 12:43:40.024604 Original DQ_B1 (3 6) =30, OEN = 27
8992 12:43:40.028377 24, 0x0, End_B0=24 End_B1=24
8993 12:43:40.028848 25, 0x0, End_B0=25 End_B1=25
8994 12:43:40.031641 26, 0x0, End_B0=26 End_B1=26
8995 12:43:40.034869 27, 0x0, End_B0=27 End_B1=27
8996 12:43:40.038081 28, 0x0, End_B0=28 End_B1=28
8997 12:43:40.041676 29, 0x0, End_B0=29 End_B1=29
8998 12:43:40.042110 30, 0x0, End_B0=30 End_B1=30
8999 12:43:40.044905 31, 0x4141, End_B0=30 End_B1=30
9000 12:43:40.047838 Byte0 end_step=30 best_step=27
9001 12:43:40.051181 Byte1 end_step=30 best_step=27
9002 12:43:40.054574 Byte0 TX OE(2T, 0.5T) = (3, 3)
9003 12:43:40.057741 Byte1 TX OE(2T, 0.5T) = (3, 3)
9004 12:43:40.058189
9005 12:43:40.058524
9006 12:43:40.064628 [DQSOSCAuto] RK1, (LSB)MR18= 0x250a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 391 ps
9007 12:43:40.068445 CH1 RK1: MR19=303, MR18=250A
9008 12:43:40.075111 CH1_RK1: MR19=0x303, MR18=0x250A, DQSOSC=391, MR23=63, INC=24, DEC=16
9009 12:43:40.078301 [RxdqsGatingPostProcess] freq 1600
9010 12:43:40.081062 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9011 12:43:40.085061 best DQS0 dly(2T, 0.5T) = (1, 1)
9012 12:43:40.088169 best DQS1 dly(2T, 0.5T) = (1, 1)
9013 12:43:40.091537 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9014 12:43:40.094899 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9015 12:43:40.098058 best DQS0 dly(2T, 0.5T) = (1, 1)
9016 12:43:40.101305 best DQS1 dly(2T, 0.5T) = (1, 1)
9017 12:43:40.104759 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9018 12:43:40.107853 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9019 12:43:40.111211 Pre-setting of DQS Precalculation
9020 12:43:40.115036 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9021 12:43:40.121377 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9022 12:43:40.127766 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9023 12:43:40.128216
9024 12:43:40.131436
9025 12:43:40.131895 [Calibration Summary] 3200 Mbps
9026 12:43:40.134454 CH 0, Rank 0
9027 12:43:40.134987 SW Impedance : PASS
9028 12:43:40.137596 DUTY Scan : NO K
9029 12:43:40.141585 ZQ Calibration : PASS
9030 12:43:40.142043 Jitter Meter : NO K
9031 12:43:40.144693 CBT Training : PASS
9032 12:43:40.148063 Write leveling : PASS
9033 12:43:40.148509 RX DQS gating : PASS
9034 12:43:40.151043 RX DQ/DQS(RDDQC) : PASS
9035 12:43:40.154749 TX DQ/DQS : PASS
9036 12:43:40.155223 RX DATLAT : PASS
9037 12:43:40.158017 RX DQ/DQS(Engine): PASS
9038 12:43:40.161131 TX OE : PASS
9039 12:43:40.161620 All Pass.
9040 12:43:40.162011
9041 12:43:40.162400 CH 0, Rank 1
9042 12:43:40.164515 SW Impedance : PASS
9043 12:43:40.167692 DUTY Scan : NO K
9044 12:43:40.168120 ZQ Calibration : PASS
9045 12:43:40.170955 Jitter Meter : NO K
9046 12:43:40.171382 CBT Training : PASS
9047 12:43:40.174362 Write leveling : PASS
9048 12:43:40.178198 RX DQS gating : PASS
9049 12:43:40.178672 RX DQ/DQS(RDDQC) : PASS
9050 12:43:40.181029 TX DQ/DQS : PASS
9051 12:43:40.184347 RX DATLAT : PASS
9052 12:43:40.184911 RX DQ/DQS(Engine): PASS
9053 12:43:40.187736 TX OE : PASS
9054 12:43:40.188315 All Pass.
9055 12:43:40.188724
9056 12:43:40.190956 CH 1, Rank 0
9057 12:43:40.191436 SW Impedance : PASS
9058 12:43:40.194380 DUTY Scan : NO K
9059 12:43:40.197626 ZQ Calibration : PASS
9060 12:43:40.198092 Jitter Meter : NO K
9061 12:43:40.200884 CBT Training : PASS
9062 12:43:40.204160 Write leveling : PASS
9063 12:43:40.204619 RX DQS gating : PASS
9064 12:43:40.208088 RX DQ/DQS(RDDQC) : PASS
9065 12:43:40.211201 TX DQ/DQS : PASS
9066 12:43:40.211678 RX DATLAT : PASS
9067 12:43:40.214620 RX DQ/DQS(Engine): PASS
9068 12:43:40.215014 TX OE : PASS
9069 12:43:40.217915 All Pass.
9070 12:43:40.218337
9071 12:43:40.218689 CH 1, Rank 1
9072 12:43:40.221401 SW Impedance : PASS
9073 12:43:40.221842 DUTY Scan : NO K
9074 12:43:40.224679 ZQ Calibration : PASS
9075 12:43:40.227796 Jitter Meter : NO K
9076 12:43:40.228235 CBT Training : PASS
9077 12:43:40.231078 Write leveling : PASS
9078 12:43:40.234290 RX DQS gating : PASS
9079 12:43:40.234935 RX DQ/DQS(RDDQC) : PASS
9080 12:43:40.237837 TX DQ/DQS : PASS
9081 12:43:40.240942 RX DATLAT : PASS
9082 12:43:40.241377 RX DQ/DQS(Engine): PASS
9083 12:43:40.244040 TX OE : PASS
9084 12:43:40.244546 All Pass.
9085 12:43:40.244936
9086 12:43:40.247378 DramC Write-DBI on
9087 12:43:40.251245 PER_BANK_REFRESH: Hybrid Mode
9088 12:43:40.251668 TX_TRACKING: ON
9089 12:43:40.260601 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9090 12:43:40.267905 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9091 12:43:40.274471 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9092 12:43:40.277782 [FAST_K] Save calibration result to emmc
9093 12:43:40.280786 sync common calibartion params.
9094 12:43:40.284575 sync cbt_mode0:1, 1:1
9095 12:43:40.287716 dram_init: ddr_geometry: 2
9096 12:43:40.288147 dram_init: ddr_geometry: 2
9097 12:43:40.291033 dram_init: ddr_geometry: 2
9098 12:43:40.294555 0:dram_rank_size:100000000
9099 12:43:40.294992 1:dram_rank_size:100000000
9100 12:43:40.301314 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9101 12:43:40.304528 DFS_SHUFFLE_HW_MODE: ON
9102 12:43:40.307788 dramc_set_vcore_voltage set vcore to 725000
9103 12:43:40.310818 Read voltage for 1600, 0
9104 12:43:40.311347 Vio18 = 0
9105 12:43:40.311699 Vcore = 725000
9106 12:43:40.314289 Vdram = 0
9107 12:43:40.314716 Vddq = 0
9108 12:43:40.315076 Vmddr = 0
9109 12:43:40.317666 switch to 3200 Mbps bootup
9110 12:43:40.318092 [DramcRunTimeConfig]
9111 12:43:40.320866 PHYPLL
9112 12:43:40.321300 DPM_CONTROL_AFTERK: ON
9113 12:43:40.324174 PER_BANK_REFRESH: ON
9114 12:43:40.327570 REFRESH_OVERHEAD_REDUCTION: ON
9115 12:43:40.328018 CMD_PICG_NEW_MODE: OFF
9116 12:43:40.330787 XRTWTW_NEW_MODE: ON
9117 12:43:40.331214 XRTRTR_NEW_MODE: ON
9118 12:43:40.333920 TX_TRACKING: ON
9119 12:43:40.334348 RDSEL_TRACKING: OFF
9120 12:43:40.337217 DQS Precalculation for DVFS: ON
9121 12:43:40.340700 RX_TRACKING: OFF
9122 12:43:40.341238 HW_GATING DBG: ON
9123 12:43:40.343979 ZQCS_ENABLE_LP4: ON
9124 12:43:40.344410 RX_PICG_NEW_MODE: ON
9125 12:43:40.347077 TX_PICG_NEW_MODE: ON
9126 12:43:40.350763 ENABLE_RX_DCM_DPHY: ON
9127 12:43:40.351348 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9128 12:43:40.353956 DUMMY_READ_FOR_TRACKING: OFF
9129 12:43:40.357428 !!! SPM_CONTROL_AFTERK: OFF
9130 12:43:40.360353 !!! SPM could not control APHY
9131 12:43:40.360860 IMPEDANCE_TRACKING: ON
9132 12:43:40.363701 TEMP_SENSOR: ON
9133 12:43:40.364116 HW_SAVE_FOR_SR: OFF
9134 12:43:40.367097 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9135 12:43:40.370182 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9136 12:43:40.373774 Read ODT Tracking: ON
9137 12:43:40.376921 Refresh Rate DeBounce: ON
9138 12:43:40.377348 DFS_NO_QUEUE_FLUSH: ON
9139 12:43:40.380324 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9140 12:43:40.383495 ENABLE_DFS_RUNTIME_MRW: OFF
9141 12:43:40.387184 DDR_RESERVE_NEW_MODE: ON
9142 12:43:40.387700 MR_CBT_SWITCH_FREQ: ON
9143 12:43:40.390512 =========================
9144 12:43:40.409480 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9145 12:43:40.412706 dram_init: ddr_geometry: 2
9146 12:43:40.430709 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9147 12:43:40.434147 dram_init: dram init end (result: 0)
9148 12:43:40.441226 DRAM-K: Full calibration passed in 24479 msecs
9149 12:43:40.444552 MRC: failed to locate region type 0.
9150 12:43:40.445130 DRAM rank0 size:0x100000000,
9151 12:43:40.447720 DRAM rank1 size=0x100000000
9152 12:43:40.457881 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9153 12:43:40.464180 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9154 12:43:40.471319 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9155 12:43:40.477912 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9156 12:43:40.481003 DRAM rank0 size:0x100000000,
9157 12:43:40.484173 DRAM rank1 size=0x100000000
9158 12:43:40.484739 CBMEM:
9159 12:43:40.487578 IMD: root @ 0xfffff000 254 entries.
9160 12:43:40.491536 IMD: root @ 0xffffec00 62 entries.
9161 12:43:40.494595 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9162 12:43:40.497959 WARNING: RO_VPD is uninitialized or empty.
9163 12:43:40.504143 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9164 12:43:40.510956 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9165 12:43:40.523872 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9166 12:43:40.535097 BS: romstage times (exec / console): total (unknown) / 24009 ms
9167 12:43:40.535524
9168 12:43:40.535923
9169 12:43:40.545379 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9170 12:43:40.548635 ARM64: Exception handlers installed.
9171 12:43:40.552042 ARM64: Testing exception
9172 12:43:40.555672 ARM64: Done test exception
9173 12:43:40.556092 Enumerating buses...
9174 12:43:40.558613 Show all devs... Before device enumeration.
9175 12:43:40.561618 Root Device: enabled 1
9176 12:43:40.565179 CPU_CLUSTER: 0: enabled 1
9177 12:43:40.565603 CPU: 00: enabled 1
9178 12:43:40.568376 Compare with tree...
9179 12:43:40.568799 Root Device: enabled 1
9180 12:43:40.571913 CPU_CLUSTER: 0: enabled 1
9181 12:43:40.575096 CPU: 00: enabled 1
9182 12:43:40.575683 Root Device scanning...
9183 12:43:40.578306 scan_static_bus for Root Device
9184 12:43:40.582166 CPU_CLUSTER: 0 enabled
9185 12:43:40.585179 scan_static_bus for Root Device done
9186 12:43:40.588382 scan_bus: bus Root Device finished in 8 msecs
9187 12:43:40.588966 done
9188 12:43:40.594946 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9189 12:43:40.598868 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9190 12:43:40.605097 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9191 12:43:40.608376 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9192 12:43:40.611605 Allocating resources...
9193 12:43:40.612150 Reading resources...
9194 12:43:40.618317 Root Device read_resources bus 0 link: 0
9195 12:43:40.618918 DRAM rank0 size:0x100000000,
9196 12:43:40.621617 DRAM rank1 size=0x100000000
9197 12:43:40.625349 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9198 12:43:40.627989 CPU: 00 missing read_resources
9199 12:43:40.631421 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9200 12:43:40.638063 Root Device read_resources bus 0 link: 0 done
9201 12:43:40.638522 Done reading resources.
9202 12:43:40.644699 Show resources in subtree (Root Device)...After reading.
9203 12:43:40.648001 Root Device child on link 0 CPU_CLUSTER: 0
9204 12:43:40.651371 CPU_CLUSTER: 0 child on link 0 CPU: 00
9205 12:43:40.661285 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9206 12:43:40.661794 CPU: 00
9207 12:43:40.664435 Root Device assign_resources, bus 0 link: 0
9208 12:43:40.668110 CPU_CLUSTER: 0 missing set_resources
9209 12:43:40.674867 Root Device assign_resources, bus 0 link: 0 done
9210 12:43:40.675293 Done setting resources.
9211 12:43:40.681138 Show resources in subtree (Root Device)...After assigning values.
9212 12:43:40.684911 Root Device child on link 0 CPU_CLUSTER: 0
9213 12:43:40.688294 CPU_CLUSTER: 0 child on link 0 CPU: 00
9214 12:43:40.698202 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9215 12:43:40.698628 CPU: 00
9216 12:43:40.701498 Done allocating resources.
9217 12:43:40.704390 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9218 12:43:40.707892 Enabling resources...
9219 12:43:40.708411 done.
9220 12:43:40.714310 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9221 12:43:40.714806 Initializing devices...
9222 12:43:40.718245 Root Device init
9223 12:43:40.718720 init hardware done!
9224 12:43:40.721668 0x00000018: ctrlr->caps
9225 12:43:40.724843 52.000 MHz: ctrlr->f_max
9226 12:43:40.725484 0.400 MHz: ctrlr->f_min
9227 12:43:40.727857 0x40ff8080: ctrlr->voltages
9228 12:43:40.728421 sclk: 390625
9229 12:43:40.731267 Bus Width = 1
9230 12:43:40.731872 sclk: 390625
9231 12:43:40.734747 Bus Width = 1
9232 12:43:40.735179 Early init status = 3
9233 12:43:40.741318 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9234 12:43:40.744680 in-header: 03 fc 00 00 01 00 00 00
9235 12:43:40.745181 in-data: 00
9236 12:43:40.750554 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9237 12:43:40.755211 in-header: 03 fd 00 00 00 00 00 00
9238 12:43:40.757852 in-data:
9239 12:43:40.761141 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9240 12:43:40.765616 in-header: 03 fc 00 00 01 00 00 00
9241 12:43:40.769045 in-data: 00
9242 12:43:40.772172 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9243 12:43:40.777763 in-header: 03 fd 00 00 00 00 00 00
9244 12:43:40.781522 in-data:
9245 12:43:40.784486 [SSUSB] Setting up USB HOST controller...
9246 12:43:40.788259 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9247 12:43:40.791136 [SSUSB] phy power-on done.
9248 12:43:40.794434 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9249 12:43:40.801166 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9250 12:43:40.804507 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9251 12:43:40.811393 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9252 12:43:40.817550 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9253 12:43:40.824568 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9254 12:43:40.831067 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9255 12:43:40.837643 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9256 12:43:40.840869 SPM: binary array size = 0x9dc
9257 12:43:40.844057 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9258 12:43:40.851132 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9259 12:43:40.857552 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9260 12:43:40.860851 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9261 12:43:40.867623 configure_display: Starting display init
9262 12:43:40.901376 anx7625_power_on_init: Init interface.
9263 12:43:40.904543 anx7625_disable_pd_protocol: Disabled PD feature.
9264 12:43:40.907700 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9265 12:43:40.935834 anx7625_start_dp_work: Secure OCM version=00
9266 12:43:40.939185 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9267 12:43:40.953488 sp_tx_get_edid_block: EDID Block = 1
9268 12:43:41.056324 Extracted contents:
9269 12:43:41.059757 header: 00 ff ff ff ff ff ff 00
9270 12:43:41.063021 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9271 12:43:41.066409 version: 01 04
9272 12:43:41.069706 basic params: 95 1f 11 78 0a
9273 12:43:41.073184 chroma info: 76 90 94 55 54 90 27 21 50 54
9274 12:43:41.076396 established: 00 00 00
9275 12:43:41.082856 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9276 12:43:41.086334 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9277 12:43:41.093169 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9278 12:43:41.099145 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9279 12:43:41.106146 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9280 12:43:41.109157 extensions: 00
9281 12:43:41.109578 checksum: fb
9282 12:43:41.109916
9283 12:43:41.112127 Manufacturer: IVO Model 57d Serial Number 0
9284 12:43:41.115683 Made week 0 of 2020
9285 12:43:41.116226 EDID version: 1.4
9286 12:43:41.118947 Digital display
9287 12:43:41.122248 6 bits per primary color channel
9288 12:43:41.122682 DisplayPort interface
9289 12:43:41.125863 Maximum image size: 31 cm x 17 cm
9290 12:43:41.128902 Gamma: 220%
9291 12:43:41.129497 Check DPMS levels
9292 12:43:41.132397 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9293 12:43:41.139269 First detailed timing is preferred timing
9294 12:43:41.139716 Established timings supported:
9295 12:43:41.142501 Standard timings supported:
9296 12:43:41.145605 Detailed timings
9297 12:43:41.148694 Hex of detail: 383680a07038204018303c0035ae10000019
9298 12:43:41.152342 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9299 12:43:41.158815 0780 0798 07c8 0820 hborder 0
9300 12:43:41.162144 0438 043b 0447 0458 vborder 0
9301 12:43:41.165542 -hsync -vsync
9302 12:43:41.165779 Did detailed timing
9303 12:43:41.172076 Hex of detail: 000000000000000000000000000000000000
9304 12:43:41.172314 Manufacturer-specified data, tag 0
9305 12:43:41.178536 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9306 12:43:41.178618 ASCII string: InfoVision
9307 12:43:41.185543 Hex of detail: 000000fe00523134304e574635205248200a
9308 12:43:41.189009 ASCII string: R140NWF5 RH
9309 12:43:41.189090 Checksum
9310 12:43:41.189155 Checksum: 0xfb (valid)
9311 12:43:41.195607 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9312 12:43:41.198926 DSI data_rate: 832800000 bps
9313 12:43:41.204921 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9314 12:43:41.208191 anx7625_parse_edid: pixelclock(138800).
9315 12:43:41.211965 hactive(1920), hsync(48), hfp(24), hbp(88)
9316 12:43:41.215347 vactive(1080), vsync(12), vfp(3), vbp(17)
9317 12:43:41.218971 anx7625_dsi_config: config dsi.
9318 12:43:41.224946 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9319 12:43:41.237834 anx7625_dsi_config: success to config DSI
9320 12:43:41.241540 anx7625_dp_start: MIPI phy setup OK.
9321 12:43:41.244500 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9322 12:43:41.247686 mtk_ddp_mode_set invalid vrefresh 60
9323 12:43:41.251015 main_disp_path_setup
9324 12:43:41.251122 ovl_layer_smi_id_en
9325 12:43:41.254331 ovl_layer_smi_id_en
9326 12:43:41.254410 ccorr_config
9327 12:43:41.254473 aal_config
9328 12:43:41.257272 gamma_config
9329 12:43:41.257351 postmask_config
9330 12:43:41.261089 dither_config
9331 12:43:41.264213 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9332 12:43:41.270803 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9333 12:43:41.273976 Root Device init finished in 554 msecs
9334 12:43:41.277442 CPU_CLUSTER: 0 init
9335 12:43:41.284193 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9336 12:43:41.290731 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9337 12:43:41.290895 APU_MBOX 0x190000b0 = 0x10001
9338 12:43:41.294160 APU_MBOX 0x190001b0 = 0x10001
9339 12:43:41.297583 APU_MBOX 0x190005b0 = 0x10001
9340 12:43:41.300796 APU_MBOX 0x190006b0 = 0x10001
9341 12:43:41.304237 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9342 12:43:41.316933 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9343 12:43:41.329727 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9344 12:43:41.336191 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9345 12:43:41.348008 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9346 12:43:41.357418 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9347 12:43:41.360366 CPU_CLUSTER: 0 init finished in 81 msecs
9348 12:43:41.363953 Devices initialized
9349 12:43:41.367246 Show all devs... After init.
9350 12:43:41.367743 Root Device: enabled 1
9351 12:43:41.370310 CPU_CLUSTER: 0: enabled 1
9352 12:43:41.373499 CPU: 00: enabled 1
9353 12:43:41.377195 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9354 12:43:41.380454 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9355 12:43:41.383714 ELOG: NV offset 0x57f000 size 0x1000
9356 12:43:41.390442 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9357 12:43:41.396849 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9358 12:43:41.400266 ELOG: Event(17) added with size 13 at 2023-06-14 12:43:26 UTC
9359 12:43:41.403827 out: cmd=0x121: 03 db 21 01 00 00 00 00
9360 12:43:41.407137 in-header: 03 c5 00 00 2c 00 00 00
9361 12:43:41.420408 in-data: 9a 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9362 12:43:41.426967 ELOG: Event(A1) added with size 10 at 2023-06-14 12:43:26 UTC
9363 12:43:41.433757 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9364 12:43:41.440497 ELOG: Event(A0) added with size 9 at 2023-06-14 12:43:26 UTC
9365 12:43:41.443742 elog_add_boot_reason: Logged dev mode boot
9366 12:43:41.447586 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9367 12:43:41.450629 Finalize devices...
9368 12:43:41.451081 Devices finalized
9369 12:43:41.456926 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9370 12:43:41.460559 Writing coreboot table at 0xffe64000
9371 12:43:41.463780 0. 000000000010a000-0000000000113fff: RAMSTAGE
9372 12:43:41.467034 1. 0000000040000000-00000000400fffff: RAM
9373 12:43:41.470788 2. 0000000040100000-000000004032afff: RAMSTAGE
9374 12:43:41.477151 3. 000000004032b000-00000000545fffff: RAM
9375 12:43:41.480244 4. 0000000054600000-000000005465ffff: BL31
9376 12:43:41.483553 5. 0000000054660000-00000000ffe63fff: RAM
9377 12:43:41.486948 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9378 12:43:41.493797 7. 0000000100000000-000000023fffffff: RAM
9379 12:43:41.494255 Passing 5 GPIOs to payload:
9380 12:43:41.500175 NAME | PORT | POLARITY | VALUE
9381 12:43:41.503741 EC in RW | 0x000000aa | low | undefined
9382 12:43:41.510402 EC interrupt | 0x00000005 | low | undefined
9383 12:43:41.513692 TPM interrupt | 0x000000ab | high | undefined
9384 12:43:41.516919 SD card detect | 0x00000011 | high | undefined
9385 12:43:41.523335 speaker enable | 0x00000093 | high | undefined
9386 12:43:41.526782 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9387 12:43:41.530167 in-header: 03 f9 00 00 02 00 00 00
9388 12:43:41.530605 in-data: 02 00
9389 12:43:41.533332 ADC[4]: Raw value=905096 ID=7
9390 12:43:41.536707 ADC[3]: Raw value=213441 ID=1
9391 12:43:41.537329 RAM Code: 0x71
9392 12:43:41.539865 ADC[6]: Raw value=75332 ID=0
9393 12:43:41.543325 ADC[5]: Raw value=213441 ID=1
9394 12:43:41.543834 SKU Code: 0x1
9395 12:43:41.550244 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4e98
9396 12:43:41.553312 coreboot table: 964 bytes.
9397 12:43:41.556478 IMD ROOT 0. 0xfffff000 0x00001000
9398 12:43:41.560235 IMD SMALL 1. 0xffffe000 0x00001000
9399 12:43:41.563673 RO MCACHE 2. 0xffffc000 0x00001104
9400 12:43:41.566560 CONSOLE 3. 0xfff7c000 0x00080000
9401 12:43:41.570043 FMAP 4. 0xfff7b000 0x00000452
9402 12:43:41.573472 TIME STAMP 5. 0xfff7a000 0x00000910
9403 12:43:41.576430 VBOOT WORK 6. 0xfff66000 0x00014000
9404 12:43:41.579816 RAMOOPS 7. 0xffe66000 0x00100000
9405 12:43:41.583375 COREBOOT 8. 0xffe64000 0x00002000
9406 12:43:41.583926 IMD small region:
9407 12:43:41.586597 IMD ROOT 0. 0xffffec00 0x00000400
9408 12:43:41.589736 VPD 1. 0xffffeba0 0x0000004c
9409 12:43:41.593614 MMC STATUS 2. 0xffffeb80 0x00000004
9410 12:43:41.600235 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9411 12:43:41.603328 Probing TPM: done!
9412 12:43:41.606673 Connected to device vid:did:rid of 1ae0:0028:00
9413 12:43:41.616681 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
9414 12:43:41.620225 Initialized TPM device CR50 revision 0
9415 12:43:41.623471 Checking cr50 for pending updates
9416 12:43:41.626801 Reading cr50 TPM mode
9417 12:43:41.635556 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9418 12:43:41.641986 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9419 12:43:41.682210 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9420 12:43:41.685506 Checking segment from ROM address 0x40100000
9421 12:43:41.688647 Checking segment from ROM address 0x4010001c
9422 12:43:41.695475 Loading segment from ROM address 0x40100000
9423 12:43:41.695948 code (compression=0)
9424 12:43:41.705424 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9425 12:43:41.712498 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9426 12:43:41.713002 it's not compressed!
9427 12:43:41.719107 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9428 12:43:41.725211 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9429 12:43:41.742896 Loading segment from ROM address 0x4010001c
9430 12:43:41.743348 Entry Point 0x80000000
9431 12:43:41.746066 Loaded segments
9432 12:43:41.749236 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9433 12:43:41.755840 Jumping to boot code at 0x80000000(0xffe64000)
9434 12:43:41.762646 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9435 12:43:41.769454 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9436 12:43:41.776883 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9437 12:43:41.780532 Checking segment from ROM address 0x40100000
9438 12:43:41.783583 Checking segment from ROM address 0x4010001c
9439 12:43:41.790522 Loading segment from ROM address 0x40100000
9440 12:43:41.790978 code (compression=1)
9441 12:43:41.797378 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9442 12:43:41.807437 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9443 12:43:41.807868 using LZMA
9444 12:43:41.815587 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9445 12:43:41.822140 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9446 12:43:41.825471 Loading segment from ROM address 0x4010001c
9447 12:43:41.825962 Entry Point 0x54601000
9448 12:43:41.828864 Loaded segments
9449 12:43:41.832015 NOTICE: MT8192 bl31_setup
9450 12:43:41.839360 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9451 12:43:41.842789 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9452 12:43:41.846304 WARNING: region 0:
9453 12:43:41.848895 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9454 12:43:41.849345 WARNING: region 1:
9455 12:43:41.855875 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9456 12:43:41.859093 WARNING: region 2:
9457 12:43:41.862508 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9458 12:43:41.865943 WARNING: region 3:
9459 12:43:41.869223 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9460 12:43:41.872271 WARNING: region 4:
9461 12:43:41.879241 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9462 12:43:41.879675 WARNING: region 5:
9463 12:43:41.882137 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9464 12:43:41.885837 WARNING: region 6:
9465 12:43:41.889262 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9466 12:43:41.889709 WARNING: region 7:
9467 12:43:41.895690 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9468 12:43:41.902525 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9469 12:43:41.905743 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9470 12:43:41.908796 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9471 12:43:41.915789 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9472 12:43:41.918852 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9473 12:43:41.922809 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9474 12:43:41.929056 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9475 12:43:41.932279 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9476 12:43:41.935805 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9477 12:43:41.942756 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9478 12:43:41.946121 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9479 12:43:41.952927 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9480 12:43:41.955961 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9481 12:43:41.959130 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9482 12:43:41.965987 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9483 12:43:41.969249 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9484 12:43:41.972465 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9485 12:43:41.979713 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9486 12:43:41.982983 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9487 12:43:41.986210 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9488 12:43:41.992712 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9489 12:43:41.996491 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9490 12:43:42.002690 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9491 12:43:42.005942 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9492 12:43:42.009791 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9493 12:43:42.016066 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9494 12:43:42.019251 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9495 12:43:42.026023 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9496 12:43:42.029839 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9497 12:43:42.032851 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9498 12:43:42.039313 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9499 12:43:42.042708 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9500 12:43:42.046436 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9501 12:43:42.053211 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9502 12:43:42.056383 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9503 12:43:42.059702 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9504 12:43:42.063007 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9505 12:43:42.069473 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9506 12:43:42.072707 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9507 12:43:42.076197 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9508 12:43:42.079344 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9509 12:43:42.082889 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9510 12:43:42.089617 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9511 12:43:42.092743 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9512 12:43:42.096040 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9513 12:43:42.102799 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9514 12:43:42.106051 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9515 12:43:42.109815 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9516 12:43:42.116264 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9517 12:43:42.119807 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9518 12:43:42.122876 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9519 12:43:42.129837 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9520 12:43:42.132930 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9521 12:43:42.139424 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9522 12:43:42.142487 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9523 12:43:42.145886 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9524 12:43:42.153182 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9525 12:43:42.156411 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9526 12:43:42.163082 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9527 12:43:42.166332 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9528 12:43:42.173044 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9529 12:43:42.176268 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9530 12:43:42.179586 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9531 12:43:42.186189 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9532 12:43:42.189468 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9533 12:43:42.196416 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9534 12:43:42.199879 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9535 12:43:42.206204 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9536 12:43:42.209288 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9537 12:43:42.212983 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9538 12:43:42.219390 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9539 12:43:42.222551 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9540 12:43:42.229467 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9541 12:43:42.232615 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9542 12:43:42.239118 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9543 12:43:42.242405 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9544 12:43:42.249711 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9545 12:43:42.252945 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9546 12:43:42.256122 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9547 12:43:42.262694 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9548 12:43:42.265972 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9549 12:43:42.272478 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9550 12:43:42.275729 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9551 12:43:42.282468 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9552 12:43:42.286367 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9553 12:43:42.289652 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9554 12:43:42.296281 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9555 12:43:42.299489 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9556 12:43:42.306133 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9557 12:43:42.309665 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9558 12:43:42.315779 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9559 12:43:42.319321 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9560 12:43:42.322777 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9561 12:43:42.329136 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9562 12:43:42.332845 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9563 12:43:42.339243 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9564 12:43:42.342556 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9565 12:43:42.346251 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9566 12:43:42.352678 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9567 12:43:42.356036 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9568 12:43:42.359263 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9569 12:43:42.362720 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9570 12:43:42.369273 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9571 12:43:42.372722 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9572 12:43:42.379173 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9573 12:43:42.382680 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9574 12:43:42.385785 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9575 12:43:42.392426 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9576 12:43:42.395673 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9577 12:43:42.402455 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9578 12:43:42.406359 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9579 12:43:42.409687 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9580 12:43:42.415708 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9581 12:43:42.419628 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9582 12:43:42.425947 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9583 12:43:42.429613 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9584 12:43:42.432708 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9585 12:43:42.439390 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9586 12:43:42.442478 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9587 12:43:42.446199 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9588 12:43:42.449342 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9589 12:43:42.456491 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9590 12:43:42.459533 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9591 12:43:42.462635 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9592 12:43:42.466082 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9593 12:43:42.472578 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9594 12:43:42.475938 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9595 12:43:42.483168 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9596 12:43:42.486350 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9597 12:43:42.489696 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9598 12:43:42.496248 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9599 12:43:42.499590 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9600 12:43:42.502806 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9601 12:43:42.509707 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9602 12:43:42.513000 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9603 12:43:42.519592 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9604 12:43:42.522901 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9605 12:43:42.526342 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9606 12:43:42.532908 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9607 12:43:42.535925 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9608 12:43:42.542856 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9609 12:43:42.546077 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9610 12:43:42.549300 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9611 12:43:42.556235 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9612 12:43:42.559304 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9613 12:43:42.563133 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9614 12:43:42.569478 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9615 12:43:42.572527 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9616 12:43:42.579617 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9617 12:43:42.582893 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9618 12:43:42.586059 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9619 12:43:42.592662 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9620 12:43:42.596760 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9621 12:43:42.599932 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9622 12:43:42.606564 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9623 12:43:42.609955 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9624 12:43:42.616552 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9625 12:43:42.619744 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9626 12:43:42.623292 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9627 12:43:42.630051 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9628 12:43:42.633094 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9629 12:43:42.640433 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9630 12:43:42.643156 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9631 12:43:42.646742 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9632 12:43:42.653036 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9633 12:43:42.656674 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9634 12:43:42.659613 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9635 12:43:42.666664 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9636 12:43:42.669839 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9637 12:43:42.676503 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9638 12:43:42.680362 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9639 12:43:42.683705 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9640 12:43:42.690143 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9641 12:43:42.693587 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9642 12:43:42.699639 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9643 12:43:42.703188 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9644 12:43:42.706364 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9645 12:43:42.713016 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9646 12:43:42.716238 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9647 12:43:42.720054 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9648 12:43:42.726256 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9649 12:43:42.729672 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9650 12:43:42.736270 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9651 12:43:42.739877 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9652 12:43:42.743075 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9653 12:43:42.749852 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9654 12:43:42.753220 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9655 12:43:42.760076 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9656 12:43:42.763222 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9657 12:43:42.766939 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9658 12:43:42.773191 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9659 12:43:42.776326 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9660 12:43:42.783368 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9661 12:43:42.786458 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9662 12:43:42.793505 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9663 12:43:42.796412 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9664 12:43:42.799796 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9665 12:43:42.807009 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9666 12:43:42.810307 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9667 12:43:42.816425 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9668 12:43:42.819794 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9669 12:43:42.823704 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9670 12:43:42.829778 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9671 12:43:42.833076 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9672 12:43:42.839814 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9673 12:43:42.843733 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9674 12:43:42.846946 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9675 12:43:42.853587 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9676 12:43:42.856730 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9677 12:43:42.863161 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9678 12:43:42.866668 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9679 12:43:42.872919 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9680 12:43:42.876519 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9681 12:43:42.879577 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9682 12:43:42.886637 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9683 12:43:42.889606 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9684 12:43:42.896379 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9685 12:43:42.899372 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9686 12:43:42.902532 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9687 12:43:42.909587 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9688 12:43:42.912885 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9689 12:43:42.919663 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9690 12:43:42.922996 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9691 12:43:42.929482 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9692 12:43:42.933063 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9693 12:43:42.936228 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9694 12:43:42.943032 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9695 12:43:42.946372 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9696 12:43:42.952716 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9697 12:43:42.955923 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9698 12:43:42.959326 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9699 12:43:42.962652 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9700 12:43:42.969106 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9701 12:43:42.972741 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9702 12:43:42.975977 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9703 12:43:42.982833 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9704 12:43:42.986007 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9705 12:43:42.989249 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9706 12:43:42.996028 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9707 12:43:42.999093 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9708 12:43:43.002848 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9709 12:43:43.008884 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9710 12:43:43.012186 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9711 12:43:43.015498 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9712 12:43:43.022603 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9713 12:43:43.026059 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9714 12:43:43.032591 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9715 12:43:43.035847 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9716 12:43:43.039809 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9717 12:43:43.045877 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9718 12:43:43.049209 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9719 12:43:43.052401 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9720 12:43:43.058896 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9721 12:43:43.062225 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9722 12:43:43.065488 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9723 12:43:43.072046 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9724 12:43:43.075478 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9725 12:43:43.082609 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9726 12:43:43.085558 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9727 12:43:43.089162 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9728 12:43:43.095484 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9729 12:43:43.099436 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9730 12:43:43.102567 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9731 12:43:43.108761 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9732 12:43:43.112033 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9733 12:43:43.115262 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9734 12:43:43.121888 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9735 12:43:43.125755 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9736 12:43:43.128824 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9737 12:43:43.135422 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9738 12:43:43.139307 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9739 12:43:43.142427 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9740 12:43:43.145592 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9741 12:43:43.148903 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9742 12:43:43.155467 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9743 12:43:43.158802 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9744 12:43:43.161841 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9745 12:43:43.168697 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9746 12:43:43.171948 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9747 12:43:43.175415 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9748 12:43:43.178739 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9749 12:43:43.184993 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9750 12:43:43.188915 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9751 12:43:43.192160 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9752 12:43:43.198901 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9753 12:43:43.202348 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9754 12:43:43.208770 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9755 12:43:43.211883 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9756 12:43:43.218513 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9757 12:43:43.221750 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9758 12:43:43.225012 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9759 12:43:43.231740 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9760 12:43:43.234798 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9761 12:43:43.241637 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9762 12:43:43.244685 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9763 12:43:43.251330 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9764 12:43:43.254880 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9765 12:43:43.258220 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9766 12:43:43.264603 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9767 12:43:43.268339 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9768 12:43:43.274985 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9769 12:43:43.278392 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9770 12:43:43.281818 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9771 12:43:43.288313 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9772 12:43:43.291700 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9773 12:43:43.295044 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9774 12:43:43.301309 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9775 12:43:43.304559 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9776 12:43:43.311514 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9777 12:43:43.314631 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9778 12:43:43.321574 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9779 12:43:43.324728 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9780 12:43:43.327894 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9781 12:43:43.335277 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9782 12:43:43.338567 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9783 12:43:43.344553 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9784 12:43:43.348290 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9785 12:43:43.351514 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9786 12:43:43.358174 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9787 12:43:43.361592 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9788 12:43:43.368067 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9789 12:43:43.371327 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9790 12:43:43.374741 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9791 12:43:43.381218 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9792 12:43:43.384446 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9793 12:43:43.391065 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9794 12:43:43.394422 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9795 12:43:43.397895 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9796 12:43:43.404592 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9797 12:43:43.407719 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9798 12:43:43.414861 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9799 12:43:43.417953 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9800 12:43:43.421069 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9801 12:43:43.427881 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9802 12:43:43.431132 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9803 12:43:43.437959 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9804 12:43:43.441206 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9805 12:43:43.444545 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9806 12:43:43.451167 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9807 12:43:43.454417 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9808 12:43:43.460832 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9809 12:43:43.464274 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9810 12:43:43.470819 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9811 12:43:43.474047 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9812 12:43:43.477341 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9813 12:43:43.484037 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9814 12:43:43.487315 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9815 12:43:43.494023 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9816 12:43:43.497243 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9817 12:43:43.500677 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9818 12:43:43.507284 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9819 12:43:43.510553 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9820 12:43:43.517477 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9821 12:43:43.520658 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9822 12:43:43.524355 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9823 12:43:43.530711 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9824 12:43:43.533824 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9825 12:43:43.540935 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9826 12:43:43.544026 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9827 12:43:43.550891 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9828 12:43:43.554096 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9829 12:43:43.557465 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9830 12:43:43.564156 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9831 12:43:43.567337 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9832 12:43:43.573916 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9833 12:43:43.577158 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9834 12:43:43.584378 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9835 12:43:43.587597 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9836 12:43:43.594296 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9837 12:43:43.597634 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9838 12:43:43.600921 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9839 12:43:43.607667 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9840 12:43:43.610950 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9841 12:43:43.617341 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9842 12:43:43.620681 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9843 12:43:43.627541 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9844 12:43:43.630759 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9845 12:43:43.633854 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9846 12:43:43.640745 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9847 12:43:43.644056 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9848 12:43:43.650429 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9849 12:43:43.653481 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9850 12:43:43.660155 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9851 12:43:43.664192 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9852 12:43:43.667378 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9853 12:43:43.673802 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9854 12:43:43.676837 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9855 12:43:43.683184 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9856 12:43:43.686542 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9857 12:43:43.693260 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9858 12:43:43.696506 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9859 12:43:43.703350 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9860 12:43:43.706806 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9861 12:43:43.710115 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9862 12:43:43.716107 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9863 12:43:43.720067 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9864 12:43:43.726143 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9865 12:43:43.729422 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9866 12:43:43.736328 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9867 12:43:43.739304 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9868 12:43:43.746311 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9869 12:43:43.749298 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9870 12:43:43.752485 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9871 12:43:43.759928 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9872 12:43:43.763365 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9873 12:43:43.769705 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9874 12:43:43.773055 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9875 12:43:43.779406 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9876 12:43:43.783188 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9877 12:43:43.786272 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9878 12:43:43.792700 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9879 12:43:43.795997 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9880 12:43:43.802799 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9881 12:43:43.806216 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9882 12:43:43.812865 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9883 12:43:43.816222 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9884 12:43:43.822648 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9885 12:43:43.826191 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9886 12:43:43.832983 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9887 12:43:43.836311 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9888 12:43:43.842514 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9889 12:43:43.846137 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9890 12:43:43.852758 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9891 12:43:43.855736 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9892 12:43:43.862360 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9893 12:43:43.865835 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9894 12:43:43.872210 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9895 12:43:43.876119 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9896 12:43:43.882520 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9897 12:43:43.885518 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9898 12:43:43.892547 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9899 12:43:43.895622 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9900 12:43:43.902120 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9901 12:43:43.906562 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9902 12:43:43.909194 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9903 12:43:43.912346 INFO: [APUAPC] vio 0
9904 12:43:43.918860 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9905 12:43:43.922245 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9906 12:43:43.925658 INFO: [APUAPC] D0_APC_0: 0x400510
9907 12:43:43.928903 INFO: [APUAPC] D0_APC_1: 0x0
9908 12:43:43.932416 INFO: [APUAPC] D0_APC_2: 0x1540
9909 12:43:43.935526 INFO: [APUAPC] D0_APC_3: 0x0
9910 12:43:43.939127 INFO: [APUAPC] D1_APC_0: 0xffffffff
9911 12:43:43.942420 INFO: [APUAPC] D1_APC_1: 0xffffffff
9912 12:43:43.945634 INFO: [APUAPC] D1_APC_2: 0x3fffff
9913 12:43:43.949100 INFO: [APUAPC] D1_APC_3: 0x0
9914 12:43:43.952188 INFO: [APUAPC] D2_APC_0: 0xffffffff
9915 12:43:43.956089 INFO: [APUAPC] D2_APC_1: 0xffffffff
9916 12:43:43.958638 INFO: [APUAPC] D2_APC_2: 0x3fffff
9917 12:43:43.962242 INFO: [APUAPC] D2_APC_3: 0x0
9918 12:43:43.965499 INFO: [APUAPC] D3_APC_0: 0xffffffff
9919 12:43:43.968704 INFO: [APUAPC] D3_APC_1: 0xffffffff
9920 12:43:43.971855 INFO: [APUAPC] D3_APC_2: 0x3fffff
9921 12:43:43.972283 INFO: [APUAPC] D3_APC_3: 0x0
9922 12:43:43.975385 INFO: [APUAPC] D4_APC_0: 0xffffffff
9923 12:43:43.982667 INFO: [APUAPC] D4_APC_1: 0xffffffff
9924 12:43:43.983227 INFO: [APUAPC] D4_APC_2: 0x3fffff
9925 12:43:43.985280 INFO: [APUAPC] D4_APC_3: 0x0
9926 12:43:43.988464 INFO: [APUAPC] D5_APC_0: 0xffffffff
9927 12:43:43.991891 INFO: [APUAPC] D5_APC_1: 0xffffffff
9928 12:43:43.995729 INFO: [APUAPC] D5_APC_2: 0x3fffff
9929 12:43:43.999029 INFO: [APUAPC] D5_APC_3: 0x0
9930 12:43:44.002256 INFO: [APUAPC] D6_APC_0: 0xffffffff
9931 12:43:44.005419 INFO: [APUAPC] D6_APC_1: 0xffffffff
9932 12:43:44.008773 INFO: [APUAPC] D6_APC_2: 0x3fffff
9933 12:43:44.012046 INFO: [APUAPC] D6_APC_3: 0x0
9934 12:43:44.015401 INFO: [APUAPC] D7_APC_0: 0xffffffff
9935 12:43:44.018523 INFO: [APUAPC] D7_APC_1: 0xffffffff
9936 12:43:44.021656 INFO: [APUAPC] D7_APC_2: 0x3fffff
9937 12:43:44.024999 INFO: [APUAPC] D7_APC_3: 0x0
9938 12:43:44.028325 INFO: [APUAPC] D8_APC_0: 0xffffffff
9939 12:43:44.031744 INFO: [APUAPC] D8_APC_1: 0xffffffff
9940 12:43:44.035687 INFO: [APUAPC] D8_APC_2: 0x3fffff
9941 12:43:44.038337 INFO: [APUAPC] D8_APC_3: 0x0
9942 12:43:44.041598 INFO: [APUAPC] D9_APC_0: 0xffffffff
9943 12:43:44.044979 INFO: [APUAPC] D9_APC_1: 0xffffffff
9944 12:43:44.048354 INFO: [APUAPC] D9_APC_2: 0x3fffff
9945 12:43:44.051686 INFO: [APUAPC] D9_APC_3: 0x0
9946 12:43:44.054937 INFO: [APUAPC] D10_APC_0: 0xffffffff
9947 12:43:44.058914 INFO: [APUAPC] D10_APC_1: 0xffffffff
9948 12:43:44.061686 INFO: [APUAPC] D10_APC_2: 0x3fffff
9949 12:43:44.065399 INFO: [APUAPC] D10_APC_3: 0x0
9950 12:43:44.068364 INFO: [APUAPC] D11_APC_0: 0xffffffff
9951 12:43:44.072150 INFO: [APUAPC] D11_APC_1: 0xffffffff
9952 12:43:44.075143 INFO: [APUAPC] D11_APC_2: 0x3fffff
9953 12:43:44.078604 INFO: [APUAPC] D11_APC_3: 0x0
9954 12:43:44.081646 INFO: [APUAPC] D12_APC_0: 0xffffffff
9955 12:43:44.085714 INFO: [APUAPC] D12_APC_1: 0xffffffff
9956 12:43:44.088973 INFO: [APUAPC] D12_APC_2: 0x3fffff
9957 12:43:44.091965 INFO: [APUAPC] D12_APC_3: 0x0
9958 12:43:44.095521 INFO: [APUAPC] D13_APC_0: 0xffffffff
9959 12:43:44.098671 INFO: [APUAPC] D13_APC_1: 0xffffffff
9960 12:43:44.101958 INFO: [APUAPC] D13_APC_2: 0x3fffff
9961 12:43:44.105824 INFO: [APUAPC] D13_APC_3: 0x0
9962 12:43:44.108292 INFO: [APUAPC] D14_APC_0: 0xffffffff
9963 12:43:44.111856 INFO: [APUAPC] D14_APC_1: 0xffffffff
9964 12:43:44.114961 INFO: [APUAPC] D14_APC_2: 0x3fffff
9965 12:43:44.118194 INFO: [APUAPC] D14_APC_3: 0x0
9966 12:43:44.121453 INFO: [APUAPC] D15_APC_0: 0xffffffff
9967 12:43:44.124771 INFO: [APUAPC] D15_APC_1: 0xffffffff
9968 12:43:44.128132 INFO: [APUAPC] D15_APC_2: 0x3fffff
9969 12:43:44.131760 INFO: [APUAPC] D15_APC_3: 0x0
9970 12:43:44.135129 INFO: [APUAPC] APC_CON: 0x4
9971 12:43:44.138562 INFO: [NOCDAPC] D0_APC_0: 0x0
9972 12:43:44.141878 INFO: [NOCDAPC] D0_APC_1: 0x0
9973 12:43:44.145226 INFO: [NOCDAPC] D1_APC_0: 0x0
9974 12:43:44.145715 INFO: [NOCDAPC] D1_APC_1: 0xfff
9975 12:43:44.148414 INFO: [NOCDAPC] D2_APC_0: 0x0
9976 12:43:44.151879 INFO: [NOCDAPC] D2_APC_1: 0xfff
9977 12:43:44.154499 INFO: [NOCDAPC] D3_APC_0: 0x0
9978 12:43:44.158009 INFO: [NOCDAPC] D3_APC_1: 0xfff
9979 12:43:44.161712 INFO: [NOCDAPC] D4_APC_0: 0x0
9980 12:43:44.164889 INFO: [NOCDAPC] D4_APC_1: 0xfff
9981 12:43:44.167788 INFO: [NOCDAPC] D5_APC_0: 0x0
9982 12:43:44.171425 INFO: [NOCDAPC] D5_APC_1: 0xfff
9983 12:43:44.174595 INFO: [NOCDAPC] D6_APC_0: 0x0
9984 12:43:44.178287 INFO: [NOCDAPC] D6_APC_1: 0xfff
9985 12:43:44.178695 INFO: [NOCDAPC] D7_APC_0: 0x0
9986 12:43:44.181177 INFO: [NOCDAPC] D7_APC_1: 0xfff
9987 12:43:44.184721 INFO: [NOCDAPC] D8_APC_0: 0x0
9988 12:43:44.187816 INFO: [NOCDAPC] D8_APC_1: 0xfff
9989 12:43:44.191159 INFO: [NOCDAPC] D9_APC_0: 0x0
9990 12:43:44.194407 INFO: [NOCDAPC] D9_APC_1: 0xfff
9991 12:43:44.197910 INFO: [NOCDAPC] D10_APC_0: 0x0
9992 12:43:44.201027 INFO: [NOCDAPC] D10_APC_1: 0xfff
9993 12:43:44.204437 INFO: [NOCDAPC] D11_APC_0: 0x0
9994 12:43:44.208174 INFO: [NOCDAPC] D11_APC_1: 0xfff
9995 12:43:44.211568 INFO: [NOCDAPC] D12_APC_0: 0x0
9996 12:43:44.214547 INFO: [NOCDAPC] D12_APC_1: 0xfff
9997 12:43:44.217977 INFO: [NOCDAPC] D13_APC_0: 0x0
9998 12:43:44.218395 INFO: [NOCDAPC] D13_APC_1: 0xfff
9999 12:43:44.221169 INFO: [NOCDAPC] D14_APC_0: 0x0
10000 12:43:44.224256 INFO: [NOCDAPC] D14_APC_1: 0xfff
10001 12:43:44.228214 INFO: [NOCDAPC] D15_APC_0: 0x0
10002 12:43:44.231467 INFO: [NOCDAPC] D15_APC_1: 0xfff
10003 12:43:44.234685 INFO: [NOCDAPC] APC_CON: 0x4
10004 12:43:44.238213 INFO: [APUAPC] set_apusys_apc done
10005 12:43:44.241564 INFO: [DEVAPC] devapc_init done
10006 12:43:44.244555 INFO: GICv3 without legacy support detected.
10007 12:43:44.247800 INFO: ARM GICv3 driver initialized in EL3
10008 12:43:44.254692 INFO: Maximum SPI INTID supported: 639
10009 12:43:44.257923 INFO: BL31: Initializing runtime services
10010 12:43:44.264527 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10011 12:43:44.265014 INFO: SPM: enable CPC mode
10012 12:43:44.271057 INFO: mcdi ready for mcusys-off-idle and system suspend
10013 12:43:44.274278 INFO: BL31: Preparing for EL3 exit to normal world
10014 12:43:44.278253 INFO: Entry point address = 0x80000000
10015 12:43:44.281354 INFO: SPSR = 0x8
10016 12:43:44.286977
10017 12:43:44.287399
10018 12:43:44.287731
10019 12:43:44.289909 Starting depthcharge on Spherion...
10020 12:43:44.290426
10021 12:43:44.290808 Wipe memory regions:
10022 12:43:44.291122
10023 12:43:44.293471 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10024 12:43:44.293956 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10025 12:43:44.294358 Setting prompt string to ['asurada:']
10026 12:43:44.294766 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10027 12:43:44.295425 [0x00000040000000, 0x00000054600000)
10028 12:43:44.415574
10029 12:43:44.416063 [0x00000054660000, 0x00000080000000)
10030 12:43:44.676537
10031 12:43:44.677071 [0x000000821a7280, 0x000000ffe64000)
10032 12:43:45.421240
10033 12:43:45.421785 [0x00000100000000, 0x00000240000000)
10034 12:43:47.311505
10035 12:43:47.314569 Initializing XHCI USB controller at 0x11200000.
10036 12:43:48.352618
10037 12:43:48.355737 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10038 12:43:48.356187
10039 12:43:48.356522
10040 12:43:48.356874
10041 12:43:48.357644 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10043 12:43:48.458856 asurada: tftpboot 192.168.201.1 10724859/tftp-deploy-wksjipk0/kernel/image.itb 10724859/tftp-deploy-wksjipk0/kernel/cmdline
10044 12:43:48.459562 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10045 12:43:48.460191 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10046 12:43:48.465261 tftpboot 192.168.201.1 10724859/tftp-deploy-wksjipk0/kernel/image.itp-deploy-wksjipk0/kernel/cmdline
10047 12:43:48.465850
10048 12:43:48.466389 Waiting for link
10049 12:43:48.624978
10050 12:43:48.625137 R8152: Initializing
10051 12:43:48.625234
10052 12:43:48.628454 Version 9 (ocp_data = 6010)
10053 12:43:48.628567
10054 12:43:48.631723 R8152: Done initializing
10055 12:43:48.631834
10056 12:43:48.631930 Adding net device
10057 12:43:50.573979
10058 12:43:50.574484 done.
10059 12:43:50.574827
10060 12:43:50.575180 MAC: 00:e0:4c:78:7a:aa
10061 12:43:50.575513
10062 12:43:50.577912 Sending DHCP discover... done.
10063 12:43:50.578339
10064 12:43:50.580652 Waiting for reply... done.
10065 12:43:50.581157
10066 12:43:50.584618 Sending DHCP request... done.
10067 12:43:50.585094
10068 12:43:50.585427 Waiting for reply... done.
10069 12:43:50.587647
10070 12:43:50.588064 My ip is 192.168.201.12
10071 12:43:50.588397
10072 12:43:50.595433 The DHCP server ip is 192.168.201.1
10073 12:43:50.596050
10074 12:43:50.596403 TFTP server IP predefined by user: 192.168.201.1
10075 12:43:50.596717
10076 12:43:50.600542 Bootfile predefined by user: 10724859/tftp-deploy-wksjipk0/kernel/image.itb
10077 12:43:50.601078
10078 12:43:50.604459 Sending tftp read request... done.
10079 12:43:50.604922
10080 12:43:50.612117 Waiting for the transfer...
10081 12:43:50.612558
10082 12:43:50.924171 00000000 ################################################################
10083 12:43:50.924307
10084 12:43:51.191001 00080000 ################################################################
10085 12:43:51.191133
10086 12:43:51.447955 00100000 ################################################################
10087 12:43:51.448096
10088 12:43:51.709441 00180000 ################################################################
10089 12:43:51.709597
10090 12:43:51.963698 00200000 ################################################################
10091 12:43:51.963858
10092 12:43:52.228772 00280000 ################################################################
10093 12:43:52.228945
10094 12:43:52.519551 00300000 ################################################################
10095 12:43:52.519692
10096 12:43:52.799673 00380000 ################################################################
10097 12:43:52.799836
10098 12:43:53.084525 00400000 ################################################################
10099 12:43:53.084681
10100 12:43:53.360977 00480000 ################################################################
10101 12:43:53.361133
10102 12:43:53.629125 00500000 ################################################################
10103 12:43:53.629284
10104 12:43:53.897236 00580000 ################################################################
10105 12:43:53.897367
10106 12:43:54.153999 00600000 ################################################################
10107 12:43:54.154135
10108 12:43:54.406299 00680000 ################################################################
10109 12:43:54.406450
10110 12:43:54.658501 00700000 ################################################################
10111 12:43:54.658634
10112 12:43:54.913842 00780000 ################################################################
10113 12:43:54.913980
10114 12:43:55.168373 00800000 ################################################################
10115 12:43:55.168507
10116 12:43:55.435038 00880000 ################################################################
10117 12:43:55.435171
10118 12:43:55.705130 00900000 ################################################################
10119 12:43:55.705262
10120 12:43:55.973642 00980000 ################################################################
10121 12:43:55.973801
10122 12:43:56.229722 00a00000 ################################################################
10123 12:43:56.229898
10124 12:43:56.483385 00a80000 ################################################################
10125 12:43:56.483523
10126 12:43:56.737448 00b00000 ################################################################
10127 12:43:56.737580
10128 12:43:56.989015 00b80000 ################################################################
10129 12:43:56.989149
10130 12:43:57.251554 00c00000 ################################################################
10131 12:43:57.251690
10132 12:43:57.509523 00c80000 ################################################################
10133 12:43:57.509667
10134 12:43:57.778645 00d00000 ################################################################
10135 12:43:57.778778
10136 12:43:58.035079 00d80000 ################################################################
10137 12:43:58.035238
10138 12:43:58.302866 00e00000 ################################################################
10139 12:43:58.303021
10140 12:43:58.554256 00e80000 ################################################################
10141 12:43:58.554392
10142 12:43:58.821470 00f00000 ################################################################
10143 12:43:58.821602
10144 12:43:59.074720 00f80000 ################################################################
10145 12:43:59.074854
10146 12:43:59.324069 01000000 ################################################################
10147 12:43:59.324197
10148 12:43:59.582232 01080000 ################################################################
10149 12:43:59.582369
10150 12:43:59.856019 01100000 ################################################################
10151 12:43:59.856173
10152 12:44:00.113748 01180000 ################################################################
10153 12:44:00.113880
10154 12:44:00.366884 01200000 ################################################################
10155 12:44:00.367044
10156 12:44:00.620714 01280000 ################################################################
10157 12:44:00.620917
10158 12:44:00.880282 01300000 ################################################################
10159 12:44:00.880447
10160 12:44:01.151515 01380000 ################################################################
10161 12:44:01.151649
10162 12:44:01.410452 01400000 ################################################################
10163 12:44:01.410586
10164 12:44:01.675113 01480000 ################################################################
10165 12:44:01.675269
10166 12:44:01.940101 01500000 ################################################################
10167 12:44:01.940262
10168 12:44:02.189430 01580000 ################################################################
10169 12:44:02.189584
10170 12:44:02.441584 01600000 ################################################################
10171 12:44:02.441715
10172 12:44:02.700056 01680000 ################################################################
10173 12:44:02.700185
10174 12:44:02.972781 01700000 ################################################################
10175 12:44:02.972954
10176 12:44:03.241532 01780000 ################################################################
10177 12:44:03.241671
10178 12:44:03.517322 01800000 ################################################################
10179 12:44:03.517452
10180 12:44:03.771370 01880000 ################################################################
10181 12:44:03.771501
10182 12:44:04.044974 01900000 ################################################################
10183 12:44:04.045104
10184 12:44:04.311868 01980000 ################################################################
10185 12:44:04.311992
10186 12:44:04.572152 01a00000 ################################################################
10187 12:44:04.572286
10188 12:44:04.857250 01a80000 ################################################################
10189 12:44:04.857384
10190 12:44:05.129897 01b00000 ################################################################
10191 12:44:05.130032
10192 12:44:05.389037 01b80000 ################################################################
10193 12:44:05.389167
10194 12:44:05.642287 01c00000 ################################################################
10195 12:44:05.642427
10196 12:44:05.908442 01c80000 ################################################################
10197 12:44:05.908578
10198 12:44:06.182267 01d00000 ################################################################
10199 12:44:06.182427
10200 12:44:06.435440 01d80000 ################################################################
10201 12:44:06.435600
10202 12:44:06.689880 01e00000 ################################################################
10203 12:44:06.690041
10204 12:44:06.941220 01e80000 ################################################################
10205 12:44:06.941355
10206 12:44:07.197009 01f00000 ################################################################
10207 12:44:07.197144
10208 12:44:07.460639 01f80000 ################################################################
10209 12:44:07.460813
10210 12:44:07.727063 02000000 ################################################################
10211 12:44:07.727197
10212 12:44:07.983147 02080000 ################################################################
10213 12:44:07.983282
10214 12:44:08.236549 02100000 ################################################################
10215 12:44:08.236698
10216 12:44:08.492258 02180000 ################################################################
10217 12:44:08.492388
10218 12:44:08.743313 02200000 ################################################################
10219 12:44:08.743448
10220 12:44:09.011047 02280000 ################################################################
10221 12:44:09.011187
10222 12:44:09.282129 02300000 ################################################################
10223 12:44:09.282261
10224 12:44:09.539820 02380000 ################################################################
10225 12:44:09.539974
10226 12:44:09.800661 02400000 ################################################################
10227 12:44:09.800826
10228 12:44:10.066656 02480000 ################################################################
10229 12:44:10.066786
10230 12:44:10.329435 02500000 ################################################################
10231 12:44:10.329572
10232 12:44:10.604096 02580000 ################################################################
10233 12:44:10.604229
10234 12:44:10.865845 02600000 ################################################################
10235 12:44:10.865973
10236 12:44:11.141085 02680000 ################################################################
10237 12:44:11.141213
10238 12:44:11.400105 02700000 ################################################################
10239 12:44:11.400243
10240 12:44:11.668187 02780000 ################################################################
10241 12:44:11.668328
10242 12:44:11.934938 02800000 ################################################################
10243 12:44:11.935100
10244 12:44:12.213501 02880000 ################################################################
10245 12:44:12.213640
10246 12:44:12.489142 02900000 ################################################################
10247 12:44:12.489278
10248 12:44:12.751672 02980000 ################################################################
10249 12:44:12.751847
10250 12:44:13.027276 02a00000 ################################################################
10251 12:44:13.027410
10252 12:44:13.291899 02a80000 ################################################################
10253 12:44:13.292030
10254 12:44:13.549424 02b00000 ################################################################
10255 12:44:13.549573
10256 12:44:13.804568 02b80000 ################################################################
10257 12:44:13.804705
10258 12:44:14.092235 02c00000 ################################################################
10259 12:44:14.092401
10260 12:44:14.365591 02c80000 ################################################################
10261 12:44:14.365745
10262 12:44:14.633715 02d00000 ################################################################
10263 12:44:14.633870
10264 12:44:14.896649 02d80000 ################################################################
10265 12:44:14.896851
10266 12:44:15.176472 02e00000 ################################################################
10267 12:44:15.176611
10268 12:44:15.431272 02e80000 ################################################################
10269 12:44:15.431439
10270 12:44:15.713039 02f00000 ################################################################
10271 12:44:15.713176
10272 12:44:15.978438 02f80000 ################################################################
10273 12:44:15.978599
10274 12:44:16.247066 03000000 ################################################################
10275 12:44:16.247233
10276 12:44:16.533914 03080000 ################################################################
10277 12:44:16.534048
10278 12:44:16.807557 03100000 ################################################################
10279 12:44:16.807722
10280 12:44:17.068519 03180000 ################################################################
10281 12:44:17.068652
10282 12:44:17.337757 03200000 ################################################################
10283 12:44:17.337918
10284 12:44:17.614360 03280000 ################################################################
10285 12:44:17.614498
10286 12:44:17.893821 03300000 ################################################################
10287 12:44:17.893961
10288 12:44:18.184615 03380000 ################################################################
10289 12:44:18.184753
10290 12:44:18.443428 03400000 ################################################################
10291 12:44:18.443564
10292 12:44:18.707325 03480000 ################################################################
10293 12:44:18.707456
10294 12:44:18.960378 03500000 ################################################################
10295 12:44:18.960509
10296 12:44:19.224967 03580000 ################################################################
10297 12:44:19.225098
10298 12:44:19.501666 03600000 ################################################################
10299 12:44:19.501821
10300 12:44:19.756874 03680000 ################################################################
10301 12:44:19.757005
10302 12:44:20.032394 03700000 ################################################################
10303 12:44:20.032526
10304 12:44:20.309622 03780000 ################################################################
10305 12:44:20.309754
10306 12:44:20.595687 03800000 ################################################################
10307 12:44:20.595844
10308 12:44:20.887570 03880000 ################################################################
10309 12:44:20.887700
10310 12:44:21.150431 03900000 ################################################################
10311 12:44:21.150566
10312 12:44:21.425581 03980000 ################################################################
10313 12:44:21.425714
10314 12:44:21.709373 03a00000 ################################################################
10315 12:44:21.709509
10316 12:44:21.972168 03a80000 ################################################################
10317 12:44:21.972324
10318 12:44:22.235498 03b00000 ################################################################
10319 12:44:22.235634
10320 12:44:22.522215 03b80000 ################################################################
10321 12:44:22.522346
10322 12:44:22.803599 03c00000 ################################################################
10323 12:44:22.803728
10324 12:44:23.076024 03c80000 ################################################################
10325 12:44:23.076156
10326 12:44:23.343751 03d00000 ################################################################
10327 12:44:23.343884
10328 12:44:23.596717 03d80000 ################################################################
10329 12:44:23.596913
10330 12:44:23.857387 03e00000 ################################################################
10331 12:44:23.857518
10332 12:44:24.122738 03e80000 ################################################################
10333 12:44:24.122871
10334 12:44:24.378777 03f00000 ################################################################
10335 12:44:24.378910
10336 12:44:24.515345 03f80000 #################################### done.
10337 12:44:24.515490
10338 12:44:24.518892 The bootfile was 66872198 bytes long.
10339 12:44:24.518983
10340 12:44:24.522584 Sending tftp read request... done.
10341 12:44:24.522688
10342 12:44:24.522763 Waiting for the transfer...
10343 12:44:24.525813
10344 12:44:24.525969 00000000 # done.
10345 12:44:24.526063
10346 12:44:24.532284 Command line loaded dynamically from TFTP file: 10724859/tftp-deploy-wksjipk0/kernel/cmdline
10347 12:44:24.532462
10348 12:44:24.545440 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10349 12:44:24.545653
10350 12:44:24.545774 Loading FIT.
10351 12:44:24.545880
10352 12:44:24.548710 Image ramdisk-1 has 56380861 bytes.
10353 12:44:24.548890
10354 12:44:24.552391 Image fdt-1 has 46924 bytes.
10355 12:44:24.552573
10356 12:44:24.555499 Image kernel-1 has 10442380 bytes.
10357 12:44:24.555675
10358 12:44:24.565431 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10359 12:44:24.565807
10360 12:44:24.582696 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10361 12:44:24.583149
10362 12:44:24.585275 Choosing best match conf-1 for compat google,spherion-rev2.
10363 12:44:24.591346
10364 12:44:24.596089 Connected to device vid:did:rid of 1ae0:0028:00
10365 12:44:24.603836
10366 12:44:24.607145 tpm_get_response: command 0x17b, return code 0x0
10367 12:44:24.607599
10368 12:44:24.611005 ec_init: CrosEC protocol v3 supported (256, 248)
10369 12:44:24.615852
10370 12:44:24.619042 tpm_cleanup: add release locality here.
10371 12:44:24.619501
10372 12:44:24.619839 Shutting down all USB controllers.
10373 12:44:24.622560
10374 12:44:24.623021 Removing current net device
10375 12:44:24.623422
10376 12:44:24.628649 Exiting depthcharge with code 4 at timestamp: 69641556
10377 12:44:24.629121
10378 12:44:24.632411 LZMA decompressing kernel-1 to 0x821a6718
10379 12:44:24.632886
10380 12:44:24.635512 LZMA decompressing kernel-1 to 0x40000000
10381 12:44:25.945399
10382 12:44:25.945535 jumping to kernel
10383 12:44:25.945983 end: 2.2.4 bootloader-commands (duration 00:00:42) [common]
10384 12:44:25.946091 start: 2.2.5 auto-login-action (timeout 00:03:44) [common]
10385 12:44:25.946173 Setting prompt string to ['Linux version [0-9]']
10386 12:44:25.946251 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10387 12:44:25.946326 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10388 12:44:26.027356
10389 12:44:26.030966 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10390 12:44:26.034505 start: 2.2.5.1 login-action (timeout 00:03:43) [common]
10391 12:44:26.034953 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10392 12:44:26.035375 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10393 12:44:26.035752 Using line separator: #'\n'#
10394 12:44:26.036069 No login prompt set.
10395 12:44:26.036379 Parsing kernel messages
10396 12:44:26.036663 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10397 12:44:26.037244 [login-action] Waiting for messages, (timeout 00:03:43)
10398 12:44:26.053713 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j35827-arm64-gcc-10-defconfig-arm64-chromebook-fwl9s) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jun 14 12:30:40 UTC 2023
10399 12:44:26.056747 [ 0.000000] random: crng init done
10400 12:44:26.060638 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10401 12:44:26.063576 [ 0.000000] efi: UEFI not found.
10402 12:44:26.073541 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10403 12:44:26.080333 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10404 12:44:26.089858 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10405 12:44:26.099577 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10406 12:44:26.106521 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10407 12:44:26.112844 [ 0.000000] printk: bootconsole [mtk8250] enabled
10408 12:44:26.116031 [ 0.000000] NUMA: No NUMA configuration found
10409 12:44:26.126311 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10410 12:44:26.129660 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10411 12:44:26.133389 [ 0.000000] Zone ranges:
10412 12:44:26.139923 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10413 12:44:26.143039 [ 0.000000] DMA32 empty
10414 12:44:26.149881 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10415 12:44:26.152922 [ 0.000000] Movable zone start for each node
10416 12:44:26.155987 [ 0.000000] Early memory node ranges
10417 12:44:26.163056 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10418 12:44:26.169114 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10419 12:44:26.176214 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10420 12:44:26.182385 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10421 12:44:26.185637 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10422 12:44:26.195887 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10423 12:44:26.251210 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10424 12:44:26.257507 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10425 12:44:26.264298 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10426 12:44:26.267319 [ 0.000000] psci: probing for conduit method from DT.
10427 12:44:26.274359 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10428 12:44:26.277328 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10429 12:44:26.284405 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10430 12:44:26.287447 [ 0.000000] psci: SMC Calling Convention v1.2
10431 12:44:26.294279 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10432 12:44:26.297601 [ 0.000000] Detected VIPT I-cache on CPU0
10433 12:44:26.304663 [ 0.000000] CPU features: detected: GIC system register CPU interface
10434 12:44:26.311066 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10435 12:44:26.317502 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10436 12:44:26.323990 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10437 12:44:26.331046 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10438 12:44:26.340562 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10439 12:44:26.344036 [ 0.000000] alternatives: applying boot alternatives
10440 12:44:26.351102 [ 0.000000] Fallback order for Node 0: 0
10441 12:44:26.357481 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10442 12:44:26.360625 [ 0.000000] Policy zone: Normal
10443 12:44:26.370762 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10444 12:44:26.380642 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10445 12:44:26.393645 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10446 12:44:26.403200 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10447 12:44:26.410056 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10448 12:44:26.413546 <6>[ 0.000000] software IO TLB: area num 8.
10449 12:44:26.470112 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10450 12:44:26.619295 <6>[ 0.000000] Memory: 7916100K/8385536K available (17984K kernel code, 4098K rwdata, 15868K rodata, 8384K init, 615K bss, 436668K reserved, 32768K cma-reserved)
10451 12:44:26.625523 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10452 12:44:26.632584 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10453 12:44:26.635521 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10454 12:44:26.642233 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10455 12:44:26.649283 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10456 12:44:26.652287 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10457 12:44:26.662099 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10458 12:44:26.668858 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10459 12:44:26.672412 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10460 12:44:26.680051 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10461 12:44:26.683338 <6>[ 0.000000] GICv3: 608 SPIs implemented
10462 12:44:26.690043 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10463 12:44:26.693152 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10464 12:44:26.697033 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10465 12:44:26.707010 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10466 12:44:26.716910 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10467 12:44:26.730242 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10468 12:44:26.736708 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10469 12:44:26.745784 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10470 12:44:26.758840 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10471 12:44:26.765672 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10472 12:44:26.772391 <6>[ 0.009176] Console: colour dummy device 80x25
10473 12:44:26.781821 <6>[ 0.013901] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10474 12:44:26.788887 <6>[ 0.024344] pid_max: default: 32768 minimum: 301
10475 12:44:26.792054 <6>[ 0.029248] LSM: Security Framework initializing
10476 12:44:26.798894 <6>[ 0.034217] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10477 12:44:26.808768 <6>[ 0.042032] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10478 12:44:26.815687 <6>[ 0.051461] cblist_init_generic: Setting adjustable number of callback queues.
10479 12:44:26.821826 <6>[ 0.058914] cblist_init_generic: Setting shift to 3 and lim to 1.
10480 12:44:26.828572 <6>[ 0.065253] cblist_init_generic: Setting shift to 3 and lim to 1.
10481 12:44:26.835454 <6>[ 0.071661] rcu: Hierarchical SRCU implementation.
10482 12:44:26.839199 <6>[ 0.076674] rcu: Max phase no-delay instances is 1000.
10483 12:44:26.846585 <6>[ 0.083691] EFI services will not be available.
10484 12:44:26.849926 <6>[ 0.088666] smp: Bringing up secondary CPUs ...
10485 12:44:26.858998 <6>[ 0.093718] Detected VIPT I-cache on CPU1
10486 12:44:26.865552 <6>[ 0.093791] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10487 12:44:26.872286 <6>[ 0.093821] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10488 12:44:26.875438 <6>[ 0.094165] Detected VIPT I-cache on CPU2
10489 12:44:26.881977 <6>[ 0.094219] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10490 12:44:26.888299 <6>[ 0.094238] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10491 12:44:26.895279 <6>[ 0.094501] Detected VIPT I-cache on CPU3
10492 12:44:26.902147 <6>[ 0.094550] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10493 12:44:26.908592 <6>[ 0.094565] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10494 12:44:26.911952 <6>[ 0.094876] CPU features: detected: Spectre-v4
10495 12:44:26.918250 <6>[ 0.094884] CPU features: detected: Spectre-BHB
10496 12:44:26.921347 <6>[ 0.094890] Detected PIPT I-cache on CPU4
10497 12:44:26.928440 <6>[ 0.094948] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10498 12:44:26.935145 <6>[ 0.094965] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10499 12:44:26.941472 <6>[ 0.095262] Detected PIPT I-cache on CPU5
10500 12:44:26.947804 <6>[ 0.095326] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10501 12:44:26.954691 <6>[ 0.095343] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10502 12:44:26.957943 <6>[ 0.095627] Detected PIPT I-cache on CPU6
10503 12:44:26.964572 <6>[ 0.095695] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10504 12:44:26.971065 <6>[ 0.095711] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10505 12:44:26.978108 <6>[ 0.096007] Detected PIPT I-cache on CPU7
10506 12:44:26.985096 <6>[ 0.096073] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10507 12:44:26.991497 <6>[ 0.096089] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10508 12:44:26.994975 <6>[ 0.096136] smp: Brought up 1 node, 8 CPUs
10509 12:44:27.001515 <6>[ 0.237470] SMP: Total of 8 processors activated.
10510 12:44:27.005203 <6>[ 0.242390] CPU features: detected: 32-bit EL0 Support
10511 12:44:27.014990 <6>[ 0.247754] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10512 12:44:27.021283 <6>[ 0.256554] CPU features: detected: Common not Private translations
10513 12:44:27.024937 <6>[ 0.263070] CPU features: detected: CRC32 instructions
10514 12:44:27.031194 <6>[ 0.268455] CPU features: detected: RCpc load-acquire (LDAPR)
10515 12:44:27.037955 <6>[ 0.274415] CPU features: detected: LSE atomic instructions
10516 12:44:27.044885 <6>[ 0.280231] CPU features: detected: Privileged Access Never
10517 12:44:27.048118 <6>[ 0.286011] CPU features: detected: RAS Extension Support
10518 12:44:27.058244 <6>[ 0.291620] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10519 12:44:27.061369 <6>[ 0.298843] CPU: All CPU(s) started at EL2
10520 12:44:27.068006 <6>[ 0.303159] alternatives: applying system-wide alternatives
10521 12:44:27.076680 <6>[ 0.313868] devtmpfs: initialized
10522 12:44:27.088711 <6>[ 0.322612] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10523 12:44:27.098968 <6>[ 0.332573] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10524 12:44:27.105170 <6>[ 0.340799] pinctrl core: initialized pinctrl subsystem
10525 12:44:27.109095 <6>[ 0.347475] DMI not present or invalid.
10526 12:44:27.115560 <6>[ 0.351883] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10527 12:44:27.125489 <6>[ 0.358749] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10528 12:44:27.131794 <6>[ 0.366333] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10529 12:44:27.141835 <6>[ 0.374551] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10530 12:44:27.144907 <6>[ 0.382796] audit: initializing netlink subsys (disabled)
10531 12:44:27.154700 <5>[ 0.388480] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10532 12:44:27.161529 <6>[ 0.389180] thermal_sys: Registered thermal governor 'step_wise'
10533 12:44:27.168211 <6>[ 0.396445] thermal_sys: Registered thermal governor 'power_allocator'
10534 12:44:27.171651 <6>[ 0.402699] cpuidle: using governor menu
10535 12:44:27.177917 <6>[ 0.413659] NET: Registered PF_QIPCRTR protocol family
10536 12:44:27.185005 <6>[ 0.419158] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10537 12:44:27.191549 <6>[ 0.426256] ASID allocator initialised with 32768 entries
10538 12:44:27.194677 <6>[ 0.432824] Serial: AMBA PL011 UART driver
10539 12:44:27.204427 <4>[ 0.441480] Trying to register duplicate clock ID: 134
10540 12:44:27.257692 <6>[ 0.498691] KASLR enabled
10541 12:44:27.272160 <6>[ 0.506322] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10542 12:44:27.278712 <6>[ 0.513336] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10543 12:44:27.285538 <6>[ 0.519826] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10544 12:44:27.291749 <6>[ 0.526828] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10545 12:44:27.298963 <6>[ 0.533315] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10546 12:44:27.305045 <6>[ 0.540320] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10547 12:44:27.311780 <6>[ 0.546808] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10548 12:44:27.318293 <6>[ 0.553813] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10549 12:44:27.321830 <6>[ 0.561270] ACPI: Interpreter disabled.
10550 12:44:27.330479 <6>[ 0.567680] iommu: Default domain type: Translated
10551 12:44:27.336579 <6>[ 0.572794] iommu: DMA domain TLB invalidation policy: strict mode
10552 12:44:27.340388 <5>[ 0.579447] SCSI subsystem initialized
10553 12:44:27.347206 <6>[ 0.583689] usbcore: registered new interface driver usbfs
10554 12:44:27.353144 <6>[ 0.589419] usbcore: registered new interface driver hub
10555 12:44:27.356764 <6>[ 0.594971] usbcore: registered new device driver usb
10556 12:44:27.363623 <6>[ 0.601069] pps_core: LinuxPPS API ver. 1 registered
10557 12:44:27.373400 <6>[ 0.606261] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10558 12:44:27.376551 <6>[ 0.615601] PTP clock support registered
10559 12:44:27.380063 <6>[ 0.619840] EDAC MC: Ver: 3.0.0
10560 12:44:27.387713 <6>[ 0.625020] FPGA manager framework
10561 12:44:27.393889 <6>[ 0.628695] Advanced Linux Sound Architecture Driver Initialized.
10562 12:44:27.397536 <6>[ 0.635465] vgaarb: loaded
10563 12:44:27.404315 <6>[ 0.638615] clocksource: Switched to clocksource arch_sys_counter
10564 12:44:27.407226 <5>[ 0.645064] VFS: Disk quotas dquot_6.6.0
10565 12:44:27.414038 <6>[ 0.649251] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10566 12:44:27.417157 <6>[ 0.656423] pnp: PnP ACPI: disabled
10567 12:44:27.426189 <6>[ 0.663125] NET: Registered PF_INET protocol family
10568 12:44:27.435502 <6>[ 0.668726] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10569 12:44:27.446728 <6>[ 0.681042] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10570 12:44:27.456545 <6>[ 0.689854] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10571 12:44:27.463391 <6>[ 0.697823] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10572 12:44:27.470152 <6>[ 0.706501] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10573 12:44:27.481871 <6>[ 0.716237] TCP: Hash tables configured (established 65536 bind 65536)
10574 12:44:27.488769 <6>[ 0.723093] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10575 12:44:27.495431 <6>[ 0.730291] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10576 12:44:27.502144 <6>[ 0.737989] NET: Registered PF_UNIX/PF_LOCAL protocol family
10577 12:44:27.508687 <6>[ 0.744155] RPC: Registered named UNIX socket transport module.
10578 12:44:27.511720 <6>[ 0.750313] RPC: Registered udp transport module.
10579 12:44:27.518560 <6>[ 0.755249] RPC: Registered tcp transport module.
10580 12:44:27.525333 <6>[ 0.760182] RPC: Registered tcp NFSv4.1 backchannel transport module.
10581 12:44:27.528260 <6>[ 0.766845] PCI: CLS 0 bytes, default 64
10582 12:44:27.532091 <6>[ 0.771233] Unpacking initramfs...
10583 12:44:27.548687 <6>[ 0.783133] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10584 12:44:27.558866 <6>[ 0.791784] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10585 12:44:27.562036 <6>[ 0.800633] kvm [1]: IPA Size Limit: 40 bits
10586 12:44:27.568719 <6>[ 0.805159] kvm [1]: GICv3: no GICV resource entry
10587 12:44:27.571840 <6>[ 0.810182] kvm [1]: disabling GICv2 emulation
10588 12:44:27.578711 <6>[ 0.814864] kvm [1]: GIC system register CPU interface enabled
10589 12:44:27.581825 <6>[ 0.821029] kvm [1]: vgic interrupt IRQ18
10590 12:44:27.588432 <6>[ 0.825395] kvm [1]: VHE mode initialized successfully
10591 12:44:27.595036 <5>[ 0.831813] Initialise system trusted keyrings
10592 12:44:27.601851 <6>[ 0.836618] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10593 12:44:27.608772 <6>[ 0.846565] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10594 12:44:27.615483 <5>[ 0.852927] NFS: Registering the id_resolver key type
10595 12:44:27.619088 <5>[ 0.858230] Key type id_resolver registered
10596 12:44:27.625990 <5>[ 0.862644] Key type id_legacy registered
10597 12:44:27.632535 <6>[ 0.866937] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10598 12:44:27.638863 <6>[ 0.873858] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10599 12:44:27.645714 <6>[ 0.881570] 9p: Installing v9fs 9p2000 file system support
10600 12:44:27.681388 <5>[ 0.918916] Key type asymmetric registered
10601 12:44:27.684492 <5>[ 0.923246] Asymmetric key parser 'x509' registered
10602 12:44:27.694726 <6>[ 0.928386] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10603 12:44:27.698108 <6>[ 0.935999] io scheduler mq-deadline registered
10604 12:44:27.700966 <6>[ 0.940774] io scheduler kyber registered
10605 12:44:27.719833 <6>[ 0.957514] EINJ: ACPI disabled.
10606 12:44:27.751772 <4>[ 0.982846] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10607 12:44:27.762048 <4>[ 0.993496] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10608 12:44:27.776515 <6>[ 1.013961] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10609 12:44:27.784564 <6>[ 1.022002] printk: console [ttyS0] disabled
10610 12:44:27.812212 <6>[ 1.046649] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10611 12:44:27.819200 <6>[ 1.056125] printk: console [ttyS0] enabled
10612 12:44:27.822551 <6>[ 1.056125] printk: console [ttyS0] enabled
10613 12:44:27.828846 <6>[ 1.065017] printk: bootconsole [mtk8250] disabled
10614 12:44:27.832423 <6>[ 1.065017] printk: bootconsole [mtk8250] disabled
10615 12:44:27.839150 <6>[ 1.076094] SuperH (H)SCI(F) driver initialized
10616 12:44:27.842161 <6>[ 1.081364] msm_serial: driver initialized
10617 12:44:27.855685 <6>[ 1.090275] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10618 12:44:27.866033 <6>[ 1.098825] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10619 12:44:27.872659 <6>[ 1.107367] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10620 12:44:27.882317 <6>[ 1.115994] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10621 12:44:27.888997 <6>[ 1.124698] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10622 12:44:27.899027 <6>[ 1.133420] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10623 12:44:27.908974 <6>[ 1.141961] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10624 12:44:27.915869 <6>[ 1.150775] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10625 12:44:27.925378 <6>[ 1.159317] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10626 12:44:27.937878 <6>[ 1.175058] loop: module loaded
10627 12:44:27.944174 <6>[ 1.181000] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10628 12:44:27.967064 <4>[ 1.204397] mtk-pmic-keys: Failed to locate of_node [id: -1]
10629 12:44:27.973556 <6>[ 1.211356] megasas: 07.719.03.00-rc1
10630 12:44:27.983289 <6>[ 1.221116] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10631 12:44:27.992773 <6>[ 1.230000] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10632 12:44:28.008782 <6>[ 1.246717] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10633 12:44:28.066215 <6>[ 1.297426] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9
10634 12:44:29.925999 <6>[ 3.164135] Freeing initrd memory: 55052K
10635 12:44:29.936488 <6>[ 3.174222] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10636 12:44:29.947125 <6>[ 3.185020] tun: Universal TUN/TAP device driver, 1.6
10637 12:44:29.950323 <6>[ 3.191069] thunder_xcv, ver 1.0
10638 12:44:29.953921 <6>[ 3.194565] thunder_bgx, ver 1.0
10639 12:44:29.956691 <6>[ 3.198061] nicpf, ver 1.0
10640 12:44:29.967787 <6>[ 3.202081] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10641 12:44:29.970733 <6>[ 3.209557] hns3: Copyright (c) 2017 Huawei Corporation.
10642 12:44:29.974096 <6>[ 3.215146] hclge is initializing
10643 12:44:29.980667 <6>[ 3.218725] e1000: Intel(R) PRO/1000 Network Driver
10644 12:44:29.987731 <6>[ 3.223854] e1000: Copyright (c) 1999-2006 Intel Corporation.
10645 12:44:29.990643 <6>[ 3.229866] e1000e: Intel(R) PRO/1000 Network Driver
10646 12:44:29.997520 <6>[ 3.235082] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10647 12:44:30.004190 <6>[ 3.241267] igb: Intel(R) Gigabit Ethernet Network Driver
10648 12:44:30.010802 <6>[ 3.246916] igb: Copyright (c) 2007-2014 Intel Corporation.
10649 12:44:30.017535 <6>[ 3.252754] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10650 12:44:30.023744 <6>[ 3.259272] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10651 12:44:30.027426 <6>[ 3.265728] sky2: driver version 1.30
10652 12:44:30.033854 <6>[ 3.270700] VFIO - User Level meta-driver version: 0.3
10653 12:44:30.041374 <6>[ 3.278941] usbcore: registered new interface driver usb-storage
10654 12:44:30.047858 <6>[ 3.285382] usbcore: registered new device driver onboard-usb-hub
10655 12:44:30.056748 <6>[ 3.294428] mt6397-rtc mt6359-rtc: registered as rtc0
10656 12:44:30.066670 <6>[ 3.299893] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-14T12:44:14 UTC (1686746654)
10657 12:44:30.069777 <6>[ 3.309451] i2c_dev: i2c /dev entries driver
10658 12:44:30.086265 <6>[ 3.320960] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10659 12:44:30.093035 <6>[ 3.331107] sdhci: Secure Digital Host Controller Interface driver
10660 12:44:30.099762 <6>[ 3.337545] sdhci: Copyright(c) Pierre Ossman
10661 12:44:30.106623 <6>[ 3.342929] Synopsys Designware Multimedia Card Interface Driver
10662 12:44:30.109772 <6>[ 3.349525] mmc0: CQHCI version 5.10
10663 12:44:30.116479 <6>[ 3.350068] sdhci-pltfm: SDHCI platform and OF driver helper
10664 12:44:30.123577 <6>[ 3.361366] ledtrig-cpu: registered to indicate activity on CPUs
10665 12:44:30.134101 <6>[ 3.368706] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10666 12:44:30.137721 <6>[ 3.376094] usbcore: registered new interface driver usbhid
10667 12:44:30.143953 <6>[ 3.381926] usbhid: USB HID core driver
10668 12:44:30.151013 <6>[ 3.386161] spi_master spi0: will run message pump with realtime priority
10669 12:44:30.200491 <6>[ 3.431528] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10670 12:44:30.219198 <6>[ 3.447133] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10671 12:44:30.222791 <6>[ 3.460718] mmc0: Command Queue Engine enabled
10672 12:44:30.230095 <6>[ 3.462037] cros-ec-spi spi0.0: Chrome EC device registered
10673 12:44:30.236507 <6>[ 3.465451] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10674 12:44:30.239830 <6>[ 3.478714] mmcblk0: mmc0:0001 DA4128 116 GiB
10675 12:44:30.251151 <6>[ 3.488960] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10676 12:44:30.261024 <6>[ 3.489329] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10677 12:44:30.267547 <6>[ 3.496376] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10678 12:44:30.271256 <6>[ 3.506321] NET: Registered PF_PACKET protocol family
10679 12:44:30.277347 <6>[ 3.510071] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10680 12:44:30.281033 <6>[ 3.514857] 9pnet: Installing 9P2000 support
10681 12:44:30.287821 <6>[ 3.520640] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10682 12:44:30.293947 <5>[ 3.524524] Key type dns_resolver registered
10683 12:44:30.297597 <6>[ 3.536112] registered taskstats version 1
10684 12:44:30.303906 <5>[ 3.540550] Loading compiled-in X.509 certificates
10685 12:44:30.337156 <4>[ 3.568047] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10686 12:44:30.347232 <4>[ 3.578822] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10687 12:44:30.356905 <3>[ 3.591548] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10688 12:44:30.369434 <6>[ 3.607093] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10689 12:44:30.376644 <6>[ 3.613947] xhci-mtk 11200000.usb: xHCI Host Controller
10690 12:44:30.383067 <6>[ 3.619473] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10691 12:44:30.393323 <6>[ 3.627341] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10692 12:44:30.399663 <6>[ 3.636777] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10693 12:44:30.406541 <6>[ 3.642957] xhci-mtk 11200000.usb: xHCI Host Controller
10694 12:44:30.413190 <6>[ 3.648451] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10695 12:44:30.419902 <6>[ 3.656110] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10696 12:44:30.426668 <6>[ 3.663992] hub 1-0:1.0: USB hub found
10697 12:44:30.429878 <6>[ 3.668025] hub 1-0:1.0: 1 port detected
10698 12:44:30.439874 <6>[ 3.672373] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10699 12:44:30.442891 <6>[ 3.681182] hub 2-0:1.0: USB hub found
10700 12:44:30.446010 <6>[ 3.685219] hub 2-0:1.0: 1 port detected
10701 12:44:30.455131 <6>[ 3.692355] mtk-msdc 11f70000.mmc: Got CD GPIO
10702 12:44:30.472992 <6>[ 3.706985] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10703 12:44:30.479304 <6>[ 3.715014] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10704 12:44:30.489387 <4>[ 3.722990] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10705 12:44:30.499756 <6>[ 3.732651] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10706 12:44:30.506332 <6>[ 3.740734] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10707 12:44:30.512584 <6>[ 3.748772] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10708 12:44:30.523036 <6>[ 3.756686] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10709 12:44:30.529756 <6>[ 3.764507] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10710 12:44:30.538964 <6>[ 3.772327] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10711 12:44:30.548995 <6>[ 3.782940] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10712 12:44:30.555683 <6>[ 3.791313] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10713 12:44:30.565737 <6>[ 3.799666] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10714 12:44:30.572192 <6>[ 3.808009] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10715 12:44:30.582642 <6>[ 3.816354] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10716 12:44:30.589077 <6>[ 3.824698] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10717 12:44:30.598848 <6>[ 3.833042] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10718 12:44:30.605474 <6>[ 3.841386] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10719 12:44:30.615743 <6>[ 3.849730] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10720 12:44:30.622443 <6>[ 3.858078] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10721 12:44:30.632139 <6>[ 3.866422] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10722 12:44:30.642168 <6>[ 3.874764] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10723 12:44:30.648593 <6>[ 3.883107] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10724 12:44:30.658214 <6>[ 3.891450] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10725 12:44:30.664900 <6>[ 3.899801] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10726 12:44:30.671734 <6>[ 3.908683] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10727 12:44:30.678670 <6>[ 3.916155] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10728 12:44:30.685591 <6>[ 3.923241] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10729 12:44:30.696110 <6>[ 3.930375] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10730 12:44:30.702522 <6>[ 3.937719] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10731 12:44:30.712685 <6>[ 3.944678] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10732 12:44:30.719332 <6>[ 3.953835] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10733 12:44:30.728850 <6>[ 3.962963] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10734 12:44:30.739029 <6>[ 3.972265] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10735 12:44:30.749046 <6>[ 3.981739] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10736 12:44:30.758963 <6>[ 3.991220] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10737 12:44:30.765548 <6>[ 4.000348] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10738 12:44:30.775283 <6>[ 4.009822] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10739 12:44:30.785917 <6>[ 4.018953] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10740 12:44:30.795632 <6>[ 4.028255] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10741 12:44:30.805516 <6>[ 4.038422] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10742 12:44:30.816008 <6>[ 4.050477] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10743 12:44:30.836704 <6>[ 4.071005] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10744 12:44:30.865797 <6>[ 4.103262] hub 2-1:1.0: USB hub found
10745 12:44:30.869062 <6>[ 4.107755] hub 2-1:1.0: 3 ports detected
10746 12:44:30.988844 <6>[ 4.222862] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10747 12:44:31.141503 <6>[ 4.378946] hub 1-1:1.0: USB hub found
10748 12:44:31.144709 <6>[ 4.383303] hub 1-1:1.0: 4 ports detected
10749 12:44:31.220464 <6>[ 4.455146] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10750 12:44:31.464683 <6>[ 4.698887] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10751 12:44:31.597711 <6>[ 4.835207] hub 1-1.4:1.0: USB hub found
10752 12:44:31.600781 <6>[ 4.839903] hub 1-1.4:1.0: 2 ports detected
10753 12:44:31.900078 <6>[ 5.134748] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10754 12:44:32.092444 <6>[ 5.326889] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10755 12:44:43.089016 <6>[ 16.331446] ALSA device list:
10756 12:44:43.095067 <6>[ 16.334702] No soundcards found.
10757 12:44:43.107650 <6>[ 16.347105] Freeing unused kernel memory: 8384K
10758 12:44:43.110856 <6>[ 16.352027] Run /init as init process
10759 12:44:43.141780 <6>[ 16.380932] NET: Registered PF_INET6 protocol family
10760 12:44:43.147953 <6>[ 16.387241] Segment Routing with IPv6
10761 12:44:43.151433 <6>[ 16.391176] In-situ OAM (IOAM) with IPv6
10762 12:44:43.185936 <30>[ 16.405327] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10763 12:44:43.189142 <30>[ 16.429219] systemd[1]: Detected architecture arm64.
10764 12:44:43.189252
10765 12:44:43.195461 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10766 12:44:43.195562
10767 12:44:43.211565 <30>[ 16.450990] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10768 12:44:43.354159 <30>[ 16.590340] systemd[1]: Queued start job for default target Graphical Interface.
10769 12:44:43.393055 <30>[ 16.632236] systemd[1]: Created slice system-getty.slice.
10770 12:44:43.399396 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10771 12:44:43.416303 <30>[ 16.655497] systemd[1]: Created slice system-modprobe.slice.
10772 12:44:43.422675 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10773 12:44:43.440761 <30>[ 16.680033] systemd[1]: Created slice system-serial\x2dgetty.slice.
10774 12:44:43.450469 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10775 12:44:43.464015 <30>[ 16.703380] systemd[1]: Created slice User and Session Slice.
10776 12:44:43.470623 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10777 12:44:43.491654 <30>[ 16.727438] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10778 12:44:43.501123 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10779 12:44:43.518987 <30>[ 16.755051] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10780 12:44:43.525753 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10781 12:44:43.546673 <30>[ 16.779006] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10782 12:44:43.552631 <30>[ 16.791041] systemd[1]: Reached target Local Encrypted Volumes.
10783 12:44:43.559571 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10784 12:44:43.575969 <30>[ 16.815005] systemd[1]: Reached target Paths.
10785 12:44:43.578912 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10786 12:44:43.595503 <30>[ 16.834934] systemd[1]: Reached target Remote File Systems.
10787 12:44:43.602374 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10788 12:44:43.615544 <30>[ 16.854921] systemd[1]: Reached target Slices.
10789 12:44:43.618689 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10790 12:44:43.635520 <30>[ 16.874930] systemd[1]: Reached target Swap.
10791 12:44:43.638715 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10792 12:44:43.659111 <30>[ 16.895172] systemd[1]: Listening on initctl Compatibility Named Pipe.
10793 12:44:43.665713 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10794 12:44:43.672031 <30>[ 16.909916] systemd[1]: Listening on Journal Audit Socket.
10795 12:44:43.678839 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10796 12:44:43.691454 <30>[ 16.931170] systemd[1]: Listening on Journal Socket (/dev/log).
10797 12:44:43.698089 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10798 12:44:43.715950 <30>[ 16.955216] systemd[1]: Listening on Journal Socket.
10799 12:44:43.722660 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10800 12:44:43.735674 <30>[ 16.975189] systemd[1]: Listening on udev Control Socket.
10801 12:44:43.742601 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10802 12:44:43.760515 <30>[ 16.999563] systemd[1]: Listening on udev Kernel Socket.
10803 12:44:43.766863 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10804 12:44:43.803868 <30>[ 17.043241] systemd[1]: Mounting Huge Pages File System...
10805 12:44:43.810516 Mounting [0;1;39mHuge Pages File System[0m...
10806 12:44:43.828649 <30>[ 17.064940] systemd[1]: Mounting POSIX Message Queue File System...
10807 12:44:43.831708 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10808 12:44:43.849279 <30>[ 17.088925] systemd[1]: Mounting Kernel Debug File System...
10809 12:44:43.856292 Mounting [0;1;39mKernel Debug File System[0m...
10810 12:44:43.874844 <30>[ 17.111228] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10811 12:44:43.886304 <30>[ 17.122173] systemd[1]: Starting Create list of static device nodes for the current kernel...
10812 12:44:43.892839 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10813 12:44:43.909607 <30>[ 17.149195] systemd[1]: Starting Load Kernel Module configfs...
10814 12:44:43.916145 Starting [0;1;39mLoad Kernel Module configfs[0m...
10815 12:44:43.933953 <30>[ 17.173161] systemd[1]: Starting Load Kernel Module drm...
10816 12:44:43.940703 Starting [0;1;39mLoad Kernel Module drm[0m...
10817 12:44:43.959000 <30>[ 17.195071] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10818 12:44:43.988071 <30>[ 17.227571] systemd[1]: Starting Journal Service...
10819 12:44:43.991554 Starting [0;1;39mJournal Service[0m...
10820 12:44:44.010483 <30>[ 17.249670] systemd[1]: Starting Load Kernel Modules...
10821 12:44:44.016739 Starting [0;1;39mLoad Kernel Modules[0m...
10822 12:44:44.037948 <30>[ 17.274144] systemd[1]: Starting Remount Root and Kernel File Systems...
10823 12:44:44.044715 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10824 12:44:44.096591 <30>[ 17.335802] systemd[1]: Starting Coldplug All udev Devices...
10825 12:44:44.102924 Starting [0;1;39mColdplug All udev Devices[0m...
10826 12:44:44.118149 <30>[ 17.357672] systemd[1]: Started Journal Service.
10827 12:44:44.124807 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10828 12:44:44.141646 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10829 12:44:44.160418 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10830 12:44:44.176689 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10831 12:44:44.199800 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10832 12:44:44.221446 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10833 12:44:44.241232 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10834 12:44:44.260754 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10835 12:44:44.285337 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10836 12:44:44.303148 See 'systemctl status systemd-remount-fs.service' for details.
10837 12:44:44.344317 Mounting [0;1;39mKernel Configuration File System[0m...
10838 12:44:44.366324 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10839 12:44:44.383875 <46>[ 17.619962] systemd-journald[182]: Received client request to flush runtime journal.
10840 12:44:44.394416 Starting [0;1;39mLoad/Save Random Seed[0m...
10841 12:44:44.410951 Starting [0;1;39mApply Kernel Variables[0m...
10842 12:44:44.430304 Starting [0;1;39mCreate System Users[0m...
10843 12:44:44.451740 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10844 12:44:44.475578 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10845 12:44:44.492682 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10846 12:44:44.508849 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10847 12:44:44.524351 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10848 12:44:44.540639 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10849 12:44:44.580171 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10850 12:44:44.603312 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10851 12:44:44.619451 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10852 12:44:44.639331 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10853 12:44:44.699616 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10854 12:44:44.723364 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10855 12:44:44.740788 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10856 12:44:44.760529 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10857 12:44:44.781079 Starting [0;1;39mNetwork Time Synchronization[0m...
10858 12:44:44.798750 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10859 12:44:44.837531 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10860 12:44:44.889320 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10861 12:44:44.906589 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10862 12:44:44.927380 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10863 12:44:44.934088 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10864 12:44:44.952329 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10865 12:44:44.965993 <6>[ 18.201960] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10866 12:44:44.972399 [[0;32m OK [0m] Started [0;<6>[ 18.212615] remoteproc remoteproc0: scp is available
10867 12:44:44.982276 1;39mDiscard unu<6>[ 18.213351] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10868 12:44:44.995763 sed blocks once <4>[ 18.220378] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10869 12:44:44.995853 a week[0m.
10870 12:44:45.005458 <6>[ 18.230017] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10871 12:44:45.009120 <6>[ 18.239751] remoteproc remoteproc0: powering up scp
10872 12:44:45.018618 <6>[ 18.248699] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10873 12:44:45.025585 <3>[ 18.250259] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10874 12:44:45.035583 <3>[ 18.250286] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10875 12:44:45.042240 <3>[ 18.250300] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10876 12:44:45.051974 <4>[ 18.253937] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10877 12:44:45.058650 <3>[ 18.254440] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10878 12:44:45.068231 <3>[ 18.254460] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10879 12:44:45.074993 <3>[ 18.254467] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10880 12:44:45.085006 <3>[ 18.254477] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10881 12:44:45.091672 <3>[ 18.254484] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10882 12:44:45.098971 <6>[ 18.255844] mc: Linux media interface: v0.10
10883 12:44:45.104830 <3>[ 18.255892] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10884 12:44:45.111692 <6>[ 18.256252] usbcore: registered new interface driver r8152
10885 12:44:45.118503 <3>[ 18.256514] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10886 12:44:45.128029 <3>[ 18.256527] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10887 12:44:45.134818 <3>[ 18.256535] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10888 12:44:45.145067 <3>[ 18.256749] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10889 12:44:45.151378 <3>[ 18.256762] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10890 12:44:45.161054 <3>[ 18.256770] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10891 12:44:45.167840 <3>[ 18.256793] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10892 12:44:45.177996 <3>[ 18.256801] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10893 12:44:45.184275 <3>[ 18.256844] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10894 12:44:45.190668 <6>[ 18.275271] videodev: Linux video capture interface: v2.00
10895 12:44:45.197866 <3>[ 18.279111] remoteproc remoteproc0: request_firmware failed: -2
10896 12:44:45.204763 <4>[ 18.283394] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10897 12:44:45.211870 <4>[ 18.317548] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10898 12:44:45.218287 <6>[ 18.326057] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10899 12:44:45.225234 <6>[ 18.337367] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10900 12:44:45.231613 <6>[ 18.388022] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10901 12:44:45.241817 <4>[ 18.410384] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10902 12:44:45.248509 <6>[ 18.413833] pci_bus 0000:00: root bus resource [bus 00-ff]
10903 12:44:45.258083 <6>[ 18.421528] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10904 12:44:45.264727 <4>[ 18.421969] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10905 12:44:45.275041 <6>[ 18.429311] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10906 12:44:45.281586 <6>[ 18.436074] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10907 12:44:45.291437 <4>[ 18.436686] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10908 12:44:45.294722 <4>[ 18.436686] Fallback method does not support PEC.
10909 12:44:45.304486 <6>[ 18.441432] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10910 12:44:45.314978 <6>[ 18.443907] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10911 12:44:45.321110 <6>[ 18.456300] usbcore: registered new interface driver cdc_ether
10912 12:44:45.327957 <6>[ 18.463666] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10913 12:44:45.337978 <3>[ 18.464290] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10914 12:44:45.340969 <6>[ 18.477788] r8152 2-1.3:1.0 eth0: v1.12.13
10915 12:44:45.347976 <6>[ 18.478494] usbcore: registered new interface driver r8153_ecm
10916 12:44:45.351327 <6>[ 18.478506] Bluetooth: Core ver 2.22
10917 12:44:45.354571 <6>[ 18.478573] NET: Registered PF_BLUETOOTH protocol family
10918 12:44:45.361795 <6>[ 18.478576] Bluetooth: HCI device and connection manager initialized
10919 12:44:45.368671 <6>[ 18.478600] Bluetooth: HCI socket layer initialized
10920 12:44:45.372293 <6>[ 18.478645] Bluetooth: L2CAP socket layer initialized
10921 12:44:45.379747 <6>[ 18.478668] Bluetooth: SCO socket layer initialized
10922 12:44:45.386391 <6>[ 18.486706] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10923 12:44:45.389951 <6>[ 18.486806] pci 0000:00:00.0: supports D1 D2
10924 12:44:45.396706 <6>[ 18.503818] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10925 12:44:45.403422 <6>[ 18.504436] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10926 12:44:45.416941 <6>[ 18.505692] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10927 12:44:45.423010 <6>[ 18.505873] usbcore: registered new interface driver uvcvideo
10928 12:44:45.430252 <6>[ 18.510660] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10929 12:44:45.437172 <6>[ 18.513204] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10930 12:44:45.444142 <6>[ 18.519697] usbcore: registered new interface driver btusb
10931 12:44:45.454284 <4>[ 18.520158] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10932 12:44:45.461012 <3>[ 18.520175] Bluetooth: hci0: Failed to load firmware file (-2)
10933 12:44:45.463957 <3>[ 18.520179] Bluetooth: hci0: Failed to set up firmware (-2)
10934 12:44:45.474245 <4>[ 18.520185] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10935 12:44:45.480910 <6>[ 18.527047] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10936 12:44:45.487458 <6>[ 18.560598] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10937 12:44:45.498289 <6>[ 18.565837] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10938 12:44:45.501473 <6>[ 18.576037] remoteproc remoteproc0: powering up scp
10939 12:44:45.507738 <6>[ 18.580859] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10940 12:44:45.517869 <4>[ 18.585246] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10941 12:44:45.525084 <6>[ 18.591295] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10942 12:44:45.532150 <3>[ 18.595116] remoteproc remoteproc0: request_firmware failed: -2
10943 12:44:45.535830 <6>[ 18.600787] pci 0000:01:00.0: supports D1 D2
10944 12:44:45.545570 <3>[ 18.607279] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10945 12:44:45.552551 <6>[ 18.612406] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10946 12:44:45.559568 <3>[ 18.616901] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 12:44:45.569662 <3>[ 18.619504] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10948 12:44:45.575842 <6>[ 18.634885] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10949 12:44:45.582604 <3>[ 18.639234] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10950 12:44:45.593407 <3>[ 18.639992] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10951 12:44:45.599700 <6>[ 18.641107] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10952 12:44:45.610407 <3>[ 18.675244] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10953 12:44:45.617309 <6>[ 18.681640] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10954 12:44:45.627481 <6>[ 18.681656] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10955 12:44:45.635241 <3>[ 18.707645] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10956 12:44:45.641459 <6>[ 18.709817] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10957 12:44:45.651784 <3>[ 18.741859] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10958 12:44:45.658661 <6>[ 18.745606] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10959 12:44:45.668797 <3>[ 18.773236] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10960 12:44:45.671904 <6>[ 18.776544] pci 0000:00:00.0: PCI bridge to [bus 01]
10961 12:44:45.681914 <3>[ 18.801531] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10962 12:44:45.688678 <6>[ 18.804265] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10963 12:44:45.695286 <6>[ 18.804506] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10964 12:44:45.705359 [[0;32m OK [<6>[ 18.942205] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10965 12:44:45.711788 0m] Reached targ<6>[ 18.949742] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10966 12:44:45.714834 et [0;1;39mTimers[0m.
10967 12:44:45.731014 <5>[ 18.967233] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10968 12:44:45.737783 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10969 12:44:45.750142 <5>[ 18.986274] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10970 12:44:45.756683 <4>[ 18.993292] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10971 12:44:45.763047 <6>[ 19.002200] cfg80211: failed to load regulatory.db
10972 12:44:45.769447 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10973 12:44:45.784418 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10974 12:44:45.809745 <6>[ 19.045970] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10975 12:44:45.816017 <6>[ 19.053500] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10976 12:44:45.842440 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0<6>[ 19.080245] mt7921e 0000:01:00.0: ASIC revision: 79610010
10977 12:44:45.842623 m.
10978 12:44:45.869505 Starting [0;1;39mUser Login Management[0m...
10979 12:44:45.885719 Starting [0;1;39mPermit User Sessions[0m...
10980 12:44:45.903538 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10981 12:44:45.933311 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10982 12:44:45.952360 <4>[ 19.185323] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10983 12:44:46.076095 <4>[ 19.309066] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10984 12:44:46.136369 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10985 12:44:46.147272 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10986 12:44:46.163610 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10987 12:44:46.185471 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10988 12:44:46.194957 <4>[ 19.430149] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10989 12:44:46.241229 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10990 12:44:46.292439 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10991 12:44:46.301393 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10992 12:44:46.316969 <4>[ 19.550276] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10993 12:44:46.324100 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10994 12:44:46.340459 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10995 12:44:46.379767 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10996 12:44:46.402169 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10997 12:44:46.426964 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10998 12:44:46.439738 <4>[ 19.671462] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10999 12:44:46.461995 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11000 12:44:46.480687 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11001 12:44:46.504150 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11002 12:44:46.552088
11003 12:44:46.552224
11004 12:44:46.562087 Debian GNU/Linux<4>[ 19.795306] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11005 12:44:46.565124 11 debian-bullseye-arm64 ttyS0
11006 12:44:46.565227
11007 12:44:46.571824 debian-bullseye-arm64 login: root (automatic login)
11008 12:44:46.571930
11009 12:44:46.571997
11010 12:44:46.578407 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Wed Jun 14 12:30:40 UTC 2023 aarch64
11011 12:44:46.578511
11012 12:44:46.585088 The programs included with the Debian GNU/Linux system are free software;
11013 12:44:46.591947 the exact distribution terms for each program are described in the
11014 12:44:46.595106 individual files in /usr/share/doc/*/copyright.
11015 12:44:46.595211
11016 12:44:46.601742 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11017 12:44:46.604703 permitted by applicable law.
11018 12:44:46.605069 Matched prompt #10: / #
11020 12:44:46.605271 Setting prompt string to ['/ #']
11021 12:44:46.605400 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11023 12:44:46.605593 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11024 12:44:46.605679 start: 2.2.6 expect-shell-connection (timeout 00:03:23) [common]
11025 12:44:46.605748 Setting prompt string to ['/ #']
11026 12:44:46.605808 Forcing a shell prompt, looking for ['/ #']
11028 12:44:46.656042 / #
11029 12:44:46.656206 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11030 12:44:46.656289 Waiting using forced prompt support (timeout 00:02:30)
11031 12:44:46.661280
11032 12:44:46.661585 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11033 12:44:46.661689 start: 2.2.7 export-device-env (timeout 00:03:23) [common]
11034 12:44:46.661788 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11035 12:44:46.661874 end: 2.2 depthcharge-retry (duration 00:01:37) [common]
11036 12:44:46.661955 end: 2 depthcharge-action (duration 00:01:37) [common]
11037 12:44:46.662041 start: 3 lava-test-retry (timeout 00:08:00) [common]
11038 12:44:46.662125 start: 3.1 lava-test-shell (timeout 00:08:00) [common]
11039 12:44:46.662196 Using namespace: common
11041 12:44:46.762518 / # #
11042 12:44:46.762678 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11043 12:44:46.762807 <4>[ 19.917558] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11044 12:44:46.767435 #
11045 12:44:46.767732 Using /lava-10724859
11047 12:44:46.868124 / # export SHELL=/bin/sh
11048 12:44:46.868324 <4>[ 20.037319] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11049 12:44:46.873406 export SHELL=/bin/sh
11051 12:44:46.973977 / # . /lava-10724859/environment
11052 12:44:46.974175 <4>[ 20.157000] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11053 12:44:46.978932 . /lava-10724859/environment
11055 12:44:47.079490 / # /lava-10724859/bin/lava-test-runner /lava-10724859/0
11056 12:44:47.079685 Test shell timeout: 10s (minimum of the action and connection timeout)
11057 12:44:47.080257 <4>[ 20.276631] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11058 12:44:47.085161 /lava-10724859/bin/lava-test-run
11059 12:44:47.128915 -sh: 5: /lava-10724859/bin/lava-test-run: not found
11060 12:44:47.154589 / # <3>[ 20.394433] mt7921e 0000:01:00.0: hardware init failed
11061 12:45:14.956853 <6>[ 48.203132] vpu: disabling
11062 12:45:14.960083 <6>[ 48.206217] vproc2: disabling
11063 12:45:14.963189 <6>[ 48.209501] vproc1: disabling
11064 12:45:14.966457 <6>[ 48.212762] vaud18: disabling
11065 12:45:14.973595 <6>[ 48.216172] vsram_others: disabling
11066 12:45:14.976549 <6>[ 48.220048] va09: disabling
11067 12:45:14.979973 <6>[ 48.223152] vsram_md: disabling
11068 12:45:14.983259 <6>[ 48.226650] Vgpu: disabling
11070 12:52:46.662942 end: 3.1 lava-test-shell (duration 00:08:00) [common]
11072 12:52:46.663901 lava-test-retry failed: 1 of 1 attempts. 'lava-test-shell timed out after 480 seconds'
11074 12:52:46.664619 end: 3 lava-test-retry (duration 00:08:00) [common]
11076 12:52:46.665873 Cleaning after the job
11077 12:52:46.666346 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724859/tftp-deploy-wksjipk0/ramdisk
11078 12:52:46.690904 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724859/tftp-deploy-wksjipk0/kernel
11079 12:52:46.714789 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724859/tftp-deploy-wksjipk0/dtb
11080 12:52:46.715052 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724859/tftp-deploy-wksjipk0/modules
11081 12:52:46.721681 start: 4.1 power-off (timeout 00:00:30) [common]
11082 12:52:46.721880 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11083 12:52:46.805601 >> Command sent successfully.
11084 12:52:46.816039 Returned 0 in 0 seconds
11085 12:52:46.917252 end: 4.1 power-off (duration 00:00:00) [common]
11087 12:52:46.919054 start: 4.2 read-feedback (timeout 00:10:00) [common]
11088 12:52:46.920486 Listened to connection for namespace 'common' for up to 1s
11089 12:52:47.921043 Finalising connection for namespace 'common'
11090 12:52:47.921748 Disconnecting from shell: Finalise
11091 12:52:48.022859 end: 4.2 read-feedback (duration 00:00:01) [common]
11092 12:52:48.023499 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10724859
11093 12:52:48.158455 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10724859
11094 12:52:48.158656 TestError: A test failed to run, look at the error message.