Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 42
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 30
- Errors: 0
1 12:39:30.625372 lava-dispatcher, installed at version: 2023.05.1
2 12:39:30.625612 start: 0 validate
3 12:39:30.625765 Start time: 2023-06-14 12:39:30.625758+00:00 (UTC)
4 12:39:30.625903 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:39:30.626028 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230609.0%2Farm64%2Finitrd.cpio.gz exists
6 12:39:30.896581 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:39:30.897427 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:40:04.167710 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:40:04.168469 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:40:04.439990 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:40:04.440692 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230609.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:40:04.972360 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:40:04.973083 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:40:11.986434 validate duration: 41.36
16 12:40:11.986705 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:40:11.986805 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:40:11.986896 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:40:11.987030 Not decompressing ramdisk as can be used compressed.
20 12:40:11.987130 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230609.0/arm64/initrd.cpio.gz
21 12:40:11.987199 saving as /var/lib/lava/dispatcher/tmp/10724840/tftp-deploy-os1kguat/ramdisk/initrd.cpio.gz
22 12:40:11.987264 total size: 4665397 (4MB)
23 12:40:12.253234 progress 0% (0MB)
24 12:40:12.254685 progress 5% (0MB)
25 12:40:12.255933 progress 10% (0MB)
26 12:40:12.257197 progress 15% (0MB)
27 12:40:12.258424 progress 20% (0MB)
28 12:40:12.259644 progress 25% (1MB)
29 12:40:12.260850 progress 30% (1MB)
30 12:40:12.262089 progress 35% (1MB)
31 12:40:12.263291 progress 40% (1MB)
32 12:40:12.264650 progress 45% (2MB)
33 12:40:12.265893 progress 50% (2MB)
34 12:40:12.267101 progress 55% (2MB)
35 12:40:12.268306 progress 60% (2MB)
36 12:40:12.269520 progress 65% (2MB)
37 12:40:12.270725 progress 70% (3MB)
38 12:40:12.271932 progress 75% (3MB)
39 12:40:12.273181 progress 80% (3MB)
40 12:40:12.274541 progress 85% (3MB)
41 12:40:12.275741 progress 90% (4MB)
42 12:40:12.276999 progress 95% (4MB)
43 12:40:12.278226 progress 100% (4MB)
44 12:40:12.278378 4MB downloaded in 0.29s (15.28MB/s)
45 12:40:12.278530 end: 1.1.1 http-download (duration 00:00:00) [common]
47 12:40:12.278773 end: 1.1 download-retry (duration 00:00:00) [common]
48 12:40:12.278861 start: 1.2 download-retry (timeout 00:10:00) [common]
49 12:40:12.278948 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 12:40:12.279087 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:40:12.279160 saving as /var/lib/lava/dispatcher/tmp/10724840/tftp-deploy-os1kguat/kernel/Image
52 12:40:12.279226 total size: 47581696 (45MB)
53 12:40:12.279289 No compression specified
54 12:40:12.280387 progress 0% (0MB)
55 12:40:12.292310 progress 5% (2MB)
56 12:40:12.304485 progress 10% (4MB)
57 12:40:12.316490 progress 15% (6MB)
58 12:40:12.328694 progress 20% (9MB)
59 12:40:12.340821 progress 25% (11MB)
60 12:40:12.352726 progress 30% (13MB)
61 12:40:12.364953 progress 35% (15MB)
62 12:40:12.377259 progress 40% (18MB)
63 12:40:12.389405 progress 45% (20MB)
64 12:40:12.401470 progress 50% (22MB)
65 12:40:12.413495 progress 55% (24MB)
66 12:40:12.425736 progress 60% (27MB)
67 12:40:12.438353 progress 65% (29MB)
68 12:40:12.451338 progress 70% (31MB)
69 12:40:12.464040 progress 75% (34MB)
70 12:40:12.476792 progress 80% (36MB)
71 12:40:12.489539 progress 85% (38MB)
72 12:40:12.502057 progress 90% (40MB)
73 12:40:12.514853 progress 95% (43MB)
74 12:40:12.528007 progress 100% (45MB)
75 12:40:12.528234 45MB downloaded in 0.25s (182.25MB/s)
76 12:40:12.528440 end: 1.2.1 http-download (duration 00:00:00) [common]
78 12:40:12.528897 end: 1.2 download-retry (duration 00:00:00) [common]
79 12:40:12.529042 start: 1.3 download-retry (timeout 00:09:59) [common]
80 12:40:12.529148 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 12:40:12.529281 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:40:12.529355 saving as /var/lib/lava/dispatcher/tmp/10724840/tftp-deploy-os1kguat/dtb/mt8192-asurada-spherion-r0.dtb
83 12:40:12.529418 total size: 46924 (0MB)
84 12:40:12.529478 No compression specified
85 12:40:12.530634 progress 69% (0MB)
86 12:40:12.530940 progress 100% (0MB)
87 12:40:12.531155 0MB downloaded in 0.00s (25.81MB/s)
88 12:40:12.531366 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:40:12.531733 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:40:12.531850 start: 1.4 download-retry (timeout 00:09:59) [common]
92 12:40:12.531968 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 12:40:12.532111 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230609.0/arm64/full.rootfs.tar.xz
94 12:40:12.532209 saving as /var/lib/lava/dispatcher/tmp/10724840/tftp-deploy-os1kguat/nfsrootfs/full.rootfs.tar
95 12:40:12.532300 total size: 200816996 (191MB)
96 12:40:12.532389 Using unxz to decompress xz
97 12:40:12.536514 progress 0% (0MB)
98 12:40:13.075754 progress 5% (9MB)
99 12:40:13.584918 progress 10% (19MB)
100 12:40:14.162869 progress 15% (28MB)
101 12:40:14.536323 progress 20% (38MB)
102 12:40:14.853419 progress 25% (47MB)
103 12:40:15.436518 progress 30% (57MB)
104 12:40:15.978790 progress 35% (67MB)
105 12:40:16.569868 progress 40% (76MB)
106 12:40:17.136417 progress 45% (86MB)
107 12:40:17.727604 progress 50% (95MB)
108 12:40:18.364906 progress 55% (105MB)
109 12:40:19.020428 progress 60% (114MB)
110 12:40:19.136228 progress 65% (124MB)
111 12:40:19.272532 progress 70% (134MB)
112 12:40:19.355379 progress 75% (143MB)
113 12:40:19.426823 progress 80% (153MB)
114 12:40:19.500965 progress 85% (162MB)
115 12:40:19.603312 progress 90% (172MB)
116 12:40:19.885589 progress 95% (181MB)
117 12:40:20.463308 progress 100% (191MB)
118 12:40:20.468719 191MB downloaded in 7.94s (24.13MB/s)
119 12:40:20.469044 end: 1.4.1 http-download (duration 00:00:08) [common]
121 12:40:20.469316 end: 1.4 download-retry (duration 00:00:08) [common]
122 12:40:20.469404 start: 1.5 download-retry (timeout 00:09:52) [common]
123 12:40:20.469491 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 12:40:20.471266 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:40:20.471342 saving as /var/lib/lava/dispatcher/tmp/10724840/tftp-deploy-os1kguat/modules/modules.tar
126 12:40:20.471405 total size: 8536768 (8MB)
127 12:40:20.471467 Using unxz to decompress xz
128 12:40:20.738757 progress 0% (0MB)
129 12:40:20.760419 progress 5% (0MB)
130 12:40:20.787625 progress 10% (0MB)
131 12:40:20.818285 progress 15% (1MB)
132 12:40:20.842176 progress 20% (1MB)
133 12:40:20.865713 progress 25% (2MB)
134 12:40:20.890389 progress 30% (2MB)
135 12:40:20.914146 progress 35% (2MB)
136 12:40:20.940920 progress 40% (3MB)
137 12:40:20.965627 progress 45% (3MB)
138 12:40:20.991436 progress 50% (4MB)
139 12:40:21.016387 progress 55% (4MB)
140 12:40:21.041745 progress 60% (4MB)
141 12:40:21.067015 progress 65% (5MB)
142 12:40:21.091836 progress 70% (5MB)
143 12:40:21.116273 progress 75% (6MB)
144 12:40:21.140346 progress 80% (6MB)
145 12:40:21.164196 progress 85% (6MB)
146 12:40:21.189452 progress 90% (7MB)
147 12:40:21.214413 progress 95% (7MB)
148 12:40:21.236954 progress 100% (8MB)
149 12:40:21.243514 8MB downloaded in 0.77s (10.54MB/s)
150 12:40:21.243811 end: 1.5.1 http-download (duration 00:00:01) [common]
152 12:40:21.244073 end: 1.5 download-retry (duration 00:00:01) [common]
153 12:40:21.244165 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 12:40:21.244259 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 12:40:24.390935 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10724840/extract-nfsrootfs-0nvap_bc
156 12:40:24.391148 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 12:40:24.391256 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 12:40:24.391430 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648
159 12:40:24.391561 makedir: /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648/lava-10724840/bin
160 12:40:24.391663 makedir: /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648/lava-10724840/tests
161 12:40:24.391761 makedir: /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648/lava-10724840/results
162 12:40:24.391864 Creating /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648/lava-10724840/bin/lava-add-keys
163 12:40:24.392007 Creating /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648/lava-10724840/bin/lava-add-sources
164 12:40:24.392133 Creating /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648/lava-10724840/bin/lava-background-process-start
165 12:40:24.392257 Creating /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648/lava-10724840/bin/lava-background-process-stop
166 12:40:24.392379 Creating /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648/lava-10724840/bin/lava-common-functions
167 12:40:24.392503 Creating /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648/lava-10724840/bin/lava-echo-ipv4
168 12:40:24.392624 Creating /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648/lava-10724840/bin/lava-install-packages
169 12:40:24.392743 Creating /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648/lava-10724840/bin/lava-installed-packages
170 12:40:24.392864 Creating /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648/lava-10724840/bin/lava-os-build
171 12:40:24.392990 Creating /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648/lava-10724840/bin/lava-probe-channel
172 12:40:24.393111 Creating /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648/lava-10724840/bin/lava-probe-ip
173 12:40:24.393231 Creating /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648/lava-10724840/bin/lava-target-ip
174 12:40:24.393357 Creating /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648/lava-10724840/bin/lava-target-mac
175 12:40:24.393477 Creating /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648/lava-10724840/bin/lava-target-storage
176 12:40:24.393598 Creating /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648/lava-10724840/bin/lava-test-case
177 12:40:24.393718 Creating /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648/lava-10724840/bin/lava-test-event
178 12:40:24.393836 Creating /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648/lava-10724840/bin/lava-test-feedback
179 12:40:24.393956 Creating /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648/lava-10724840/bin/lava-test-raise
180 12:40:24.394074 Creating /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648/lava-10724840/bin/lava-test-reference
181 12:40:24.394193 Creating /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648/lava-10724840/bin/lava-test-runner
182 12:40:24.394312 Creating /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648/lava-10724840/bin/lava-test-set
183 12:40:24.394436 Creating /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648/lava-10724840/bin/lava-test-shell
184 12:40:24.394558 Updating /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648/lava-10724840/bin/lava-add-keys (debian)
185 12:40:24.394708 Updating /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648/lava-10724840/bin/lava-add-sources (debian)
186 12:40:24.394853 Updating /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648/lava-10724840/bin/lava-install-packages (debian)
187 12:40:24.394993 Updating /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648/lava-10724840/bin/lava-installed-packages (debian)
188 12:40:24.395131 Updating /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648/lava-10724840/bin/lava-os-build (debian)
189 12:40:24.395253 Creating /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648/lava-10724840/environment
190 12:40:24.395350 LAVA metadata
191 12:40:24.395422 - LAVA_JOB_ID=10724840
192 12:40:24.395487 - LAVA_DISPATCHER_IP=192.168.201.1
193 12:40:24.395587 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 12:40:24.395655 skipped lava-vland-overlay
195 12:40:24.395730 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 12:40:24.395810 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 12:40:24.395872 skipped lava-multinode-overlay
198 12:40:24.395946 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 12:40:24.396025 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 12:40:24.396099 Loading test definitions
201 12:40:24.396190 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 12:40:24.396264 Using /lava-10724840 at stage 0
203 12:40:24.396539 uuid=10724840_1.6.2.3.1 testdef=None
204 12:40:24.396628 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 12:40:24.396714 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 12:40:24.397277 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 12:40:24.397506 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 12:40:24.398055 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 12:40:24.398283 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 12:40:24.398806 runner path: /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648/lava-10724840/0/tests/0_timesync-off test_uuid 10724840_1.6.2.3.1
213 12:40:24.398956 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 12:40:24.399179 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 12:40:24.399252 Using /lava-10724840 at stage 0
217 12:40:24.399349 Fetching tests from https://github.com/kernelci/test-definitions.git
218 12:40:24.399427 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648/lava-10724840/0/tests/1_kselftest-arm64'
219 12:40:27.805986 Running '/usr/bin/git checkout kernelci.org
220 12:40:27.947562 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648/lava-10724840/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 12:40:27.948293 uuid=10724840_1.6.2.3.5 testdef=None
222 12:40:27.948461 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 12:40:27.948727 start: 1.6.2.3.6 test-overlay (timeout 00:09:44) [common]
225 12:40:27.949544 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 12:40:27.949788 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:44) [common]
228 12:40:27.950819 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 12:40:27.951064 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:44) [common]
231 12:40:27.952061 runner path: /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648/lava-10724840/0/tests/1_kselftest-arm64 test_uuid 10724840_1.6.2.3.5
232 12:40:27.952155 BOARD='mt8192-asurada-spherion-r0'
233 12:40:27.952222 BRANCH='cip'
234 12:40:27.952297 SKIPFILE='/dev/null'
235 12:40:27.952358 SKIP_INSTALL='True'
236 12:40:27.952415 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 12:40:27.952474 TST_CASENAME=''
238 12:40:27.952539 TST_CMDFILES='arm64'
239 12:40:27.952680 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 12:40:27.952892 Creating lava-test-runner.conf files
242 12:40:27.952957 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10724840/lava-overlay-paicg648/lava-10724840/0 for stage 0
243 12:40:27.953102 - 0_timesync-off
244 12:40:27.953172 - 1_kselftest-arm64
245 12:40:27.953273 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 12:40:27.953363 start: 1.6.2.4 compress-overlay (timeout 00:09:44) [common]
247 12:40:35.429408 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 12:40:35.429560 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:37) [common]
249 12:40:35.429658 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 12:40:35.429771 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 12:40:35.429900 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:37) [common]
252 12:40:35.544591 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 12:40:35.544979 start: 1.6.4 extract-modules (timeout 00:09:36) [common]
254 12:40:35.545123 extracting modules file /var/lib/lava/dispatcher/tmp/10724840/tftp-deploy-os1kguat/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10724840/extract-nfsrootfs-0nvap_bc
255 12:40:35.751684 extracting modules file /var/lib/lava/dispatcher/tmp/10724840/tftp-deploy-os1kguat/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10724840/extract-overlay-ramdisk-qfig5leu/ramdisk
256 12:40:35.972299 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 12:40:35.972464 start: 1.6.5 apply-overlay-tftp (timeout 00:09:36) [common]
258 12:40:35.972574 [common] Applying overlay to NFS
259 12:40:35.972664 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10724840/compress-overlay-izc4bkgk/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10724840/extract-nfsrootfs-0nvap_bc
260 12:40:36.859560 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 12:40:36.859799 start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
262 12:40:36.859917 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 12:40:36.860010 start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
264 12:40:36.860098 Building ramdisk /var/lib/lava/dispatcher/tmp/10724840/extract-overlay-ramdisk-qfig5leu/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10724840/extract-overlay-ramdisk-qfig5leu/ramdisk
265 12:40:37.120244 >> 117806 blocks
266 12:40:38.975893 rename /var/lib/lava/dispatcher/tmp/10724840/extract-overlay-ramdisk-qfig5leu/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10724840/tftp-deploy-os1kguat/ramdisk/ramdisk.cpio.gz
267 12:40:38.976322 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 12:40:38.976445 start: 1.6.8 prepare-kernel (timeout 00:09:33) [common]
269 12:40:38.976545 start: 1.6.8.1 prepare-fit (timeout 00:09:33) [common]
270 12:40:38.976648 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10724840/tftp-deploy-os1kguat/kernel/Image'
271 12:40:50.634255 Returned 0 in 11 seconds
272 12:40:50.734869 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10724840/tftp-deploy-os1kguat/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10724840/tftp-deploy-os1kguat/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10724840/tftp-deploy-os1kguat/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10724840/tftp-deploy-os1kguat/kernel/image.itb
273 12:40:51.097959 output: FIT description: Kernel Image image with one or more FDT blobs
274 12:40:51.098322 output: Created: Wed Jun 14 13:40:51 2023
275 12:40:51.098403 output: Image 0 (kernel-1)
276 12:40:51.098473 output: Description:
277 12:40:51.098537 output: Created: Wed Jun 14 13:40:51 2023
278 12:40:51.098601 output: Type: Kernel Image
279 12:40:51.098665 output: Compression: lzma compressed
280 12:40:51.098728 output: Data Size: 10442380 Bytes = 10197.64 KiB = 9.96 MiB
281 12:40:51.098788 output: Architecture: AArch64
282 12:40:51.098849 output: OS: Linux
283 12:40:51.098905 output: Load Address: 0x00000000
284 12:40:51.098962 output: Entry Point: 0x00000000
285 12:40:51.099018 output: Hash algo: crc32
286 12:40:51.099073 output: Hash value: ced21bfe
287 12:40:51.099127 output: Image 1 (fdt-1)
288 12:40:51.099181 output: Description: mt8192-asurada-spherion-r0
289 12:40:51.099235 output: Created: Wed Jun 14 13:40:51 2023
290 12:40:51.099289 output: Type: Flat Device Tree
291 12:40:51.099343 output: Compression: uncompressed
292 12:40:51.099397 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 12:40:51.099451 output: Architecture: AArch64
294 12:40:51.099505 output: Hash algo: crc32
295 12:40:51.099559 output: Hash value: 1df858fa
296 12:40:51.099613 output: Image 2 (ramdisk-1)
297 12:40:51.099666 output: Description: unavailable
298 12:40:51.099719 output: Created: Wed Jun 14 13:40:51 2023
299 12:40:51.099773 output: Type: RAMDisk Image
300 12:40:51.099827 output: Compression: Unknown Compression
301 12:40:51.099881 output: Data Size: 17643815 Bytes = 17230.29 KiB = 16.83 MiB
302 12:40:51.099935 output: Architecture: AArch64
303 12:40:51.099989 output: OS: Linux
304 12:40:51.100042 output: Load Address: unavailable
305 12:40:51.100096 output: Entry Point: unavailable
306 12:40:51.100149 output: Hash algo: crc32
307 12:40:51.100202 output: Hash value: 869a3eeb
308 12:40:51.100256 output: Default Configuration: 'conf-1'
309 12:40:51.100310 output: Configuration 0 (conf-1)
310 12:40:51.100363 output: Description: mt8192-asurada-spherion-r0
311 12:40:51.100416 output: Kernel: kernel-1
312 12:40:51.100470 output: Init Ramdisk: ramdisk-1
313 12:40:51.100523 output: FDT: fdt-1
314 12:40:51.100577 output: Loadables: kernel-1
315 12:40:51.100630 output:
316 12:40:51.100822 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 12:40:51.100920 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 12:40:51.101068 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
319 12:40:51.101170 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:21) [common]
320 12:40:51.101253 No LXC device requested
321 12:40:51.101333 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 12:40:51.101423 start: 1.8 deploy-device-env (timeout 00:09:21) [common]
323 12:40:51.101503 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 12:40:51.101573 Checking files for TFTP limit of 4294967296 bytes.
325 12:40:51.102064 end: 1 tftp-deploy (duration 00:00:39) [common]
326 12:40:51.102173 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 12:40:51.102272 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 12:40:51.102401 substitutions:
329 12:40:51.102472 - {DTB}: 10724840/tftp-deploy-os1kguat/dtb/mt8192-asurada-spherion-r0.dtb
330 12:40:51.102538 - {INITRD}: 10724840/tftp-deploy-os1kguat/ramdisk/ramdisk.cpio.gz
331 12:40:51.102599 - {KERNEL}: 10724840/tftp-deploy-os1kguat/kernel/Image
332 12:40:51.102658 - {LAVA_MAC}: None
333 12:40:51.102717 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10724840/extract-nfsrootfs-0nvap_bc
334 12:40:51.102775 - {NFS_SERVER_IP}: 192.168.201.1
335 12:40:51.102831 - {PRESEED_CONFIG}: None
336 12:40:51.102887 - {PRESEED_LOCAL}: None
337 12:40:51.102942 - {RAMDISK}: 10724840/tftp-deploy-os1kguat/ramdisk/ramdisk.cpio.gz
338 12:40:51.102998 - {ROOT_PART}: None
339 12:40:51.103053 - {ROOT}: None
340 12:40:51.103109 - {SERVER_IP}: 192.168.201.1
341 12:40:51.103164 - {TEE}: None
342 12:40:51.103219 Parsed boot commands:
343 12:40:51.103273 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 12:40:51.103445 Parsed boot commands: tftpboot 192.168.201.1 10724840/tftp-deploy-os1kguat/kernel/image.itb 10724840/tftp-deploy-os1kguat/kernel/cmdline
345 12:40:51.103539 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 12:40:51.103624 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 12:40:51.103718 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 12:40:51.103809 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 12:40:51.103880 Not connected, no need to disconnect.
350 12:40:51.103955 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 12:40:51.104036 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 12:40:51.104105 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-1'
353 12:40:51.107324 Setting prompt string to ['lava-test: # ']
354 12:40:51.107656 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 12:40:51.107767 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 12:40:51.107868 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 12:40:51.107965 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 12:40:51.108157 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
359 12:40:56.234944 >> Command sent successfully.
360 12:40:56.237285 Returned 0 in 5 seconds
361 12:40:56.337669 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 12:40:56.337987 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 12:40:56.338095 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 12:40:56.338189 Setting prompt string to 'Starting depthcharge on Spherion...'
366 12:40:56.338262 Changing prompt to 'Starting depthcharge on Spherion...'
367 12:40:56.338332 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 12:40:56.338598 [Enter `^Ec?' for help]
369 12:40:56.512972
370 12:40:56.513153
371 12:40:56.513228 F0: 102B 0000
372 12:40:56.513296
373 12:40:56.513361 F3: 1001 0000 [0200]
374 12:40:56.515703
375 12:40:56.515776 F3: 1001 0000
376 12:40:56.515843
377 12:40:56.515905 F7: 102D 0000
378 12:40:56.515966
379 12:40:56.519059 F1: 0000 0000
380 12:40:56.519133
381 12:40:56.519195 V0: 0000 0000 [0001]
382 12:40:56.519258
383 12:40:56.522354 00: 0007 8000
384 12:40:56.522430
385 12:40:56.522496 01: 0000 0000
386 12:40:56.522556
387 12:40:56.525713 BP: 0C00 0209 [0000]
388 12:40:56.525786
389 12:40:56.525846 G0: 1182 0000
390 12:40:56.525910
391 12:40:56.528847 EC: 0000 0021 [4000]
392 12:40:56.528917
393 12:40:56.528983 S7: 0000 0000 [0000]
394 12:40:56.529084
395 12:40:56.532631 CC: 0000 0000 [0001]
396 12:40:56.532710
397 12:40:56.532774 T0: 0000 0040 [010F]
398 12:40:56.532835
399 12:40:56.532894 Jump to BL
400 12:40:56.535951
401 12:40:56.559336
402 12:40:56.559427
403 12:40:56.559497
404 12:40:56.566291 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 12:40:56.569229 ARM64: Exception handlers installed.
406 12:40:56.573124 ARM64: Testing exception
407 12:40:56.576667 ARM64: Done test exception
408 12:40:56.583276 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 12:40:56.593294 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 12:40:56.600201 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 12:40:56.610174 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 12:40:56.616780 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 12:40:56.627337 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 12:40:56.637931 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 12:40:56.644533 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 12:40:56.662140 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 12:40:56.665472 WDT: Last reset was cold boot
418 12:40:56.669479 SPI1(PAD0) initialized at 2873684 Hz
419 12:40:56.672173 SPI5(PAD0) initialized at 992727 Hz
420 12:40:56.675528 VBOOT: Loading verstage.
421 12:40:56.681968 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 12:40:56.685723 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 12:40:56.688759 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 12:40:56.692083 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 12:40:56.699574 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 12:40:56.706309 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 12:40:56.717091 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 12:40:56.717178
429 12:40:56.717246
430 12:40:56.727158 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 12:40:56.730460 ARM64: Exception handlers installed.
432 12:40:56.733521 ARM64: Testing exception
433 12:40:56.733607 ARM64: Done test exception
434 12:40:56.740784 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 12:40:56.743559 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 12:40:56.758234 Probing TPM: . done!
437 12:40:56.758318 TPM ready after 0 ms
438 12:40:56.765153 Connected to device vid:did:rid of 1ae0:0028:00
439 12:40:56.772662 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 12:40:56.775530 Initialized TPM device CR50 revision 0
441 12:40:56.841332 tlcl_send_startup: Startup return code is 0
442 12:40:56.841423 TPM: setup succeeded
443 12:40:56.852413 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 12:40:56.861212 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 12:40:56.871281 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 12:40:56.880676 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 12:40:56.884205 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 12:40:56.891629 in-header: 03 07 00 00 08 00 00 00
449 12:40:56.895103 in-data: aa e4 47 04 13 02 00 00
450 12:40:56.898497 Chrome EC: UHEPI supported
451 12:40:56.905657 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 12:40:56.909272 in-header: 03 ad 00 00 08 00 00 00
453 12:40:56.912809 in-data: 00 20 20 08 00 00 00 00
454 12:40:56.912894 Phase 1
455 12:40:56.916587 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 12:40:56.923848 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 12:40:56.927570 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 12:40:56.931140 Recovery requested (1009000e)
459 12:40:56.940854 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 12:40:56.946777 tlcl_extend: response is 0
461 12:40:56.956800 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 12:40:56.963145 tlcl_extend: response is 0
463 12:40:56.969366 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 12:40:56.990023 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 12:40:56.996965 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 12:40:56.997089
467 12:40:56.997157
468 12:40:57.006643 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 12:40:57.010547 ARM64: Exception handlers installed.
470 12:40:57.010637 ARM64: Testing exception
471 12:40:57.013597 ARM64: Done test exception
472 12:40:57.035261 pmic_efuse_setting: Set efuses in 11 msecs
473 12:40:57.038716 pmwrap_interface_init: Select PMIF_VLD_RDY
474 12:40:57.045871 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 12:40:57.048956 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 12:40:57.055988 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 12:40:57.059280 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 12:40:57.063040 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 12:40:57.070284 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 12:40:57.074279 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 12:40:57.077788 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 12:40:57.081329 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 12:40:57.088700 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 12:40:57.092465 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 12:40:57.095678 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 12:40:57.102228 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 12:40:57.108963 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 12:40:57.112525 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 12:40:57.119056 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 12:40:57.126217 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 12:40:57.129934 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 12:40:57.136541 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 12:40:57.143209 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 12:40:57.146699 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 12:40:57.153527 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 12:40:57.156946 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 12:40:57.163918 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 12:40:57.170019 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 12:40:57.173314 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 12:40:57.180467 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 12:40:57.183332 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 12:40:57.190123 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 12:40:57.193363 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 12:40:57.200009 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 12:40:57.203256 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 12:40:57.209778 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 12:40:57.213234 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 12:40:57.219672 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 12:40:57.222892 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 12:40:57.229649 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 12:40:57.233121 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 12:40:57.240124 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 12:40:57.243753 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 12:40:57.247116 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 12:40:57.250717 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 12:40:57.257280 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 12:40:57.260461 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 12:40:57.264145 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 12:40:57.270570 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 12:40:57.274076 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 12:40:57.277538 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 12:40:57.280462 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 12:40:57.287702 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 12:40:57.290728 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 12:40:57.296918 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 12:40:57.307136 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 12:40:57.310405 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 12:40:57.320510 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 12:40:57.327168 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 12:40:57.333760 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 12:40:57.336982 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 12:40:57.340382 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 12:40:57.348290 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x4
534 12:40:57.354759 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 12:40:57.358076 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 12:40:57.361224 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 12:40:57.373304 [RTC]rtc_get_frequency_meter,154: input=15, output=772
538 12:40:57.381961 [RTC]rtc_get_frequency_meter,154: input=23, output=957
539 12:40:57.391450 [RTC]rtc_get_frequency_meter,154: input=19, output=864
540 12:40:57.400945 [RTC]rtc_get_frequency_meter,154: input=17, output=818
541 12:40:57.410538 [RTC]rtc_get_frequency_meter,154: input=16, output=794
542 12:40:57.414112 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
543 12:40:57.420644 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
544 12:40:57.423753 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
545 12:40:57.427064 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
546 12:40:57.430812 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
547 12:40:57.434189 ADC[4]: Raw value=903614 ID=7
548 12:40:57.437374 ADC[3]: Raw value=213179 ID=1
549 12:40:57.440452 RAM Code: 0x71
550 12:40:57.444560 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
551 12:40:57.447009 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
552 12:40:57.457361 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
553 12:40:57.463735 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 12:40:57.467134 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
555 12:40:57.470241 in-header: 03 07 00 00 08 00 00 00
556 12:40:57.473733 in-data: aa e4 47 04 13 02 00 00
557 12:40:57.477790 Chrome EC: UHEPI supported
558 12:40:57.483665 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
559 12:40:57.486906 in-header: 03 ed 00 00 08 00 00 00
560 12:40:57.490674 in-data: 80 20 60 08 00 00 00 00
561 12:40:57.493681 MRC: failed to locate region type 0.
562 12:40:57.500395 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
563 12:40:57.503729 DRAM-K: Running full calibration
564 12:40:57.506985 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
565 12:40:57.510131 header.status = 0x0
566 12:40:57.513551 header.version = 0x6 (expected: 0x6)
567 12:40:57.516890 header.size = 0xd00 (expected: 0xd00)
568 12:40:57.520246 header.flags = 0x0
569 12:40:57.523414 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
570 12:40:57.542385 read SPI 0x72590 0x1c583: 12501 us, 9287 KB/s, 74.296 Mbps
571 12:40:57.549177 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
572 12:40:57.552449 dram_init: ddr_geometry: 2
573 12:40:57.556169 [EMI] MDL number = 2
574 12:40:57.556254 [EMI] Get MDL freq = 0
575 12:40:57.559060 dram_init: ddr_type: 0
576 12:40:57.559145 is_discrete_lpddr4: 1
577 12:40:57.562155 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
578 12:40:57.562240
579 12:40:57.562308
580 12:40:57.566008 [Bian_co] ETT version 0.0.0.1
581 12:40:57.573086 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
582 12:40:57.573173
583 12:40:57.576691 dramc_set_vcore_voltage set vcore to 650000
584 12:40:57.576777 Read voltage for 800, 4
585 12:40:57.576845 Vio18 = 0
586 12:40:57.580852 Vcore = 650000
587 12:40:57.580963 Vdram = 0
588 12:40:57.581073 Vddq = 0
589 12:40:57.584160 Vmddr = 0
590 12:40:57.584245 dram_init: config_dvfs: 1
591 12:40:57.591510 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
592 12:40:57.594723 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
593 12:40:57.598299 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
594 12:40:57.601837 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
595 12:40:57.605528 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
596 12:40:57.609067 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
597 12:40:57.613160 MEM_TYPE=3, freq_sel=18
598 12:40:57.617009 sv_algorithm_assistance_LP4_1600
599 12:40:57.620376 ============ PULL DRAM RESETB DOWN ============
600 12:40:57.624082 ========== PULL DRAM RESETB DOWN end =========
601 12:40:57.628101 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
602 12:40:57.631224 ===================================
603 12:40:57.634528 LPDDR4 DRAM CONFIGURATION
604 12:40:57.637856 ===================================
605 12:40:57.641160 EX_ROW_EN[0] = 0x0
606 12:40:57.641247 EX_ROW_EN[1] = 0x0
607 12:40:57.644830 LP4Y_EN = 0x0
608 12:40:57.644916 WORK_FSP = 0x0
609 12:40:57.647712 WL = 0x2
610 12:40:57.647798 RL = 0x2
611 12:40:57.651289 BL = 0x2
612 12:40:57.651376 RPST = 0x0
613 12:40:57.654578 RD_PRE = 0x0
614 12:40:57.654664 WR_PRE = 0x1
615 12:40:57.657911 WR_PST = 0x0
616 12:40:57.657997 DBI_WR = 0x0
617 12:40:57.661153 DBI_RD = 0x0
618 12:40:57.661239 OTF = 0x1
619 12:40:57.664351 ===================================
620 12:40:57.667869 ===================================
621 12:40:57.671070 ANA top config
622 12:40:57.674526 ===================================
623 12:40:57.674613 DLL_ASYNC_EN = 0
624 12:40:57.678325 ALL_SLAVE_EN = 1
625 12:40:57.681478 NEW_RANK_MODE = 1
626 12:40:57.685578 DLL_IDLE_MODE = 1
627 12:40:57.685664 LP45_APHY_COMB_EN = 1
628 12:40:57.688639 TX_ODT_DIS = 1
629 12:40:57.692316 NEW_8X_MODE = 1
630 12:40:57.696341 ===================================
631 12:40:57.699990 ===================================
632 12:40:57.700077 data_rate = 1600
633 12:40:57.703762 CKR = 1
634 12:40:57.707545 DQ_P2S_RATIO = 8
635 12:40:57.711026 ===================================
636 12:40:57.714075 CA_P2S_RATIO = 8
637 12:40:57.714161 DQ_CA_OPEN = 0
638 12:40:57.717755 DQ_SEMI_OPEN = 0
639 12:40:57.721197 CA_SEMI_OPEN = 0
640 12:40:57.724326 CA_FULL_RATE = 0
641 12:40:57.727505 DQ_CKDIV4_EN = 1
642 12:40:57.727594 CA_CKDIV4_EN = 1
643 12:40:57.731251 CA_PREDIV_EN = 0
644 12:40:57.734466 PH8_DLY = 0
645 12:40:57.738008 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
646 12:40:57.741388 DQ_AAMCK_DIV = 4
647 12:40:57.744557 CA_AAMCK_DIV = 4
648 12:40:57.744643 CA_ADMCK_DIV = 4
649 12:40:57.747801 DQ_TRACK_CA_EN = 0
650 12:40:57.750986 CA_PICK = 800
651 12:40:57.754430 CA_MCKIO = 800
652 12:40:57.757747 MCKIO_SEMI = 0
653 12:40:57.761163 PLL_FREQ = 3068
654 12:40:57.764535 DQ_UI_PI_RATIO = 32
655 12:40:57.764621 CA_UI_PI_RATIO = 0
656 12:40:57.767852 ===================================
657 12:40:57.771054 ===================================
658 12:40:57.774528 memory_type:LPDDR4
659 12:40:57.777679 GP_NUM : 10
660 12:40:57.777765 SRAM_EN : 1
661 12:40:57.780973 MD32_EN : 0
662 12:40:57.784736 ===================================
663 12:40:57.788356 [ANA_INIT] >>>>>>>>>>>>>>
664 12:40:57.788441 <<<<<< [CONFIGURE PHASE]: ANA_TX
665 12:40:57.792023 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
666 12:40:57.795668 ===================================
667 12:40:57.799533 data_rate = 1600,PCW = 0X7600
668 12:40:57.803175 ===================================
669 12:40:57.807047 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
670 12:40:57.810919 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
671 12:40:57.818011 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
672 12:40:57.821586 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
673 12:40:57.824941 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
674 12:40:57.828209 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
675 12:40:57.831531 [ANA_INIT] flow start
676 12:40:57.831616 [ANA_INIT] PLL >>>>>>>>
677 12:40:57.834797 [ANA_INIT] PLL <<<<<<<<
678 12:40:57.838246 [ANA_INIT] MIDPI >>>>>>>>
679 12:40:57.838332 [ANA_INIT] MIDPI <<<<<<<<
680 12:40:57.841755 [ANA_INIT] DLL >>>>>>>>
681 12:40:57.844922 [ANA_INIT] flow end
682 12:40:57.848212 ============ LP4 DIFF to SE enter ============
683 12:40:57.851353 ============ LP4 DIFF to SE exit ============
684 12:40:57.854782 [ANA_INIT] <<<<<<<<<<<<<
685 12:40:57.858063 [Flow] Enable top DCM control >>>>>
686 12:40:57.861261 [Flow] Enable top DCM control <<<<<
687 12:40:57.864556 Enable DLL master slave shuffle
688 12:40:57.868027 ==============================================================
689 12:40:57.871610 Gating Mode config
690 12:40:57.878121 ==============================================================
691 12:40:57.878207 Config description:
692 12:40:57.888118 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
693 12:40:57.894757 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
694 12:40:57.897730 SELPH_MODE 0: By rank 1: By Phase
695 12:40:57.904422 ==============================================================
696 12:40:57.907998 GAT_TRACK_EN = 1
697 12:40:57.911340 RX_GATING_MODE = 2
698 12:40:57.914139 RX_GATING_TRACK_MODE = 2
699 12:40:57.917495 SELPH_MODE = 1
700 12:40:57.920996 PICG_EARLY_EN = 1
701 12:40:57.924596 VALID_LAT_VALUE = 1
702 12:40:57.927599 ==============================================================
703 12:40:57.930985 Enter into Gating configuration >>>>
704 12:40:57.934221 Exit from Gating configuration <<<<
705 12:40:57.937617 Enter into DVFS_PRE_config >>>>>
706 12:40:57.950960 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
707 12:40:57.951053 Exit from DVFS_PRE_config <<<<<
708 12:40:57.954527 Enter into PICG configuration >>>>
709 12:40:57.957715 Exit from PICG configuration <<<<
710 12:40:57.961077 [RX_INPUT] configuration >>>>>
711 12:40:57.963971 [RX_INPUT] configuration <<<<<
712 12:40:57.970878 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
713 12:40:57.974205 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
714 12:40:57.980713 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
715 12:40:57.987384 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
716 12:40:57.994195 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
717 12:40:58.000732 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
718 12:40:58.004474 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
719 12:40:58.007706 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
720 12:40:58.011200 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
721 12:40:58.014760 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
722 12:40:58.021400 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
723 12:40:58.024665 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
724 12:40:58.027888 ===================================
725 12:40:58.031159 LPDDR4 DRAM CONFIGURATION
726 12:40:58.034658 ===================================
727 12:40:58.034743 EX_ROW_EN[0] = 0x0
728 12:40:58.037788 EX_ROW_EN[1] = 0x0
729 12:40:58.037874 LP4Y_EN = 0x0
730 12:40:58.041007 WORK_FSP = 0x0
731 12:40:58.041095 WL = 0x2
732 12:40:58.044292 RL = 0x2
733 12:40:58.044378 BL = 0x2
734 12:40:58.048081 RPST = 0x0
735 12:40:58.048166 RD_PRE = 0x0
736 12:40:58.051691 WR_PRE = 0x1
737 12:40:58.051776 WR_PST = 0x0
738 12:40:58.055272 DBI_WR = 0x0
739 12:40:58.055357 DBI_RD = 0x0
740 12:40:58.058984 OTF = 0x1
741 12:40:58.062973 ===================================
742 12:40:58.066369 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
743 12:40:58.070459 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
744 12:40:58.073775 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
745 12:40:58.077756 ===================================
746 12:40:58.081298 LPDDR4 DRAM CONFIGURATION
747 12:40:58.084877 ===================================
748 12:40:58.084962 EX_ROW_EN[0] = 0x10
749 12:40:58.088545 EX_ROW_EN[1] = 0x0
750 12:40:58.088630 LP4Y_EN = 0x0
751 12:40:58.092223 WORK_FSP = 0x0
752 12:40:58.092309 WL = 0x2
753 12:40:58.095605 RL = 0x2
754 12:40:58.095691 BL = 0x2
755 12:40:58.099297 RPST = 0x0
756 12:40:58.099382 RD_PRE = 0x0
757 12:40:58.103168 WR_PRE = 0x1
758 12:40:58.103262 WR_PST = 0x0
759 12:40:58.103330 DBI_WR = 0x0
760 12:40:58.106592 DBI_RD = 0x0
761 12:40:58.106677 OTF = 0x1
762 12:40:58.110258 ===================================
763 12:40:58.116995 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
764 12:40:58.121406 nWR fixed to 40
765 12:40:58.124861 [ModeRegInit_LP4] CH0 RK0
766 12:40:58.124986 [ModeRegInit_LP4] CH0 RK1
767 12:40:58.128172 [ModeRegInit_LP4] CH1 RK0
768 12:40:58.131784 [ModeRegInit_LP4] CH1 RK1
769 12:40:58.131869 match AC timing 13
770 12:40:58.135769 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
771 12:40:58.139065 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
772 12:40:58.146723 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
773 12:40:58.150438 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
774 12:40:58.154016 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
775 12:40:58.157488 [EMI DOE] emi_dcm 0
776 12:40:58.161575 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
777 12:40:58.161683 ==
778 12:40:58.164938 Dram Type= 6, Freq= 0, CH_0, rank 0
779 12:40:58.168823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 12:40:58.168910 ==
781 12:40:58.172510 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 12:40:58.179666 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 12:40:58.188972 [CA 0] Center 38 (7~69) winsize 63
784 12:40:58.192815 [CA 1] Center 38 (7~69) winsize 63
785 12:40:58.195825 [CA 2] Center 35 (5~66) winsize 62
786 12:40:58.199565 [CA 3] Center 35 (5~66) winsize 62
787 12:40:58.202927 [CA 4] Center 34 (4~65) winsize 62
788 12:40:58.206150 [CA 5] Center 33 (3~64) winsize 62
789 12:40:58.206235
790 12:40:58.210059 [CmdBusTrainingLP45] Vref(ca) range 1: 32
791 12:40:58.210144
792 12:40:58.213740 [CATrainingPosCal] consider 1 rank data
793 12:40:58.217581 u2DelayCellTimex100 = 270/100 ps
794 12:40:58.220851 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
795 12:40:58.224366 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
796 12:40:58.228530 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
797 12:40:58.231859 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
798 12:40:58.235722 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
799 12:40:58.239598 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
800 12:40:58.239684
801 12:40:58.243086 CA PerBit enable=1, Macro0, CA PI delay=33
802 12:40:58.243173
803 12:40:58.246531 [CBTSetCACLKResult] CA Dly = 33
804 12:40:58.246618 CS Dly: 6 (0~37)
805 12:40:58.246686 ==
806 12:40:58.250412 Dram Type= 6, Freq= 0, CH_0, rank 1
807 12:40:58.254052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
808 12:40:58.254139 ==
809 12:40:58.261426 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
810 12:40:58.264950 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
811 12:40:58.275227 [CA 0] Center 38 (7~69) winsize 63
812 12:40:58.278680 [CA 1] Center 38 (7~69) winsize 63
813 12:40:58.282527 [CA 2] Center 36 (6~67) winsize 62
814 12:40:58.286403 [CA 3] Center 35 (5~66) winsize 62
815 12:40:58.289681 [CA 4] Center 35 (4~66) winsize 63
816 12:40:58.293327 [CA 5] Center 34 (4~65) winsize 62
817 12:40:58.293405
818 12:40:58.297090 [CmdBusTrainingLP45] Vref(ca) range 1: 32
819 12:40:58.297166
820 12:40:58.300684 [CATrainingPosCal] consider 2 rank data
821 12:40:58.304721 u2DelayCellTimex100 = 270/100 ps
822 12:40:58.308076 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
823 12:40:58.312210 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
824 12:40:58.315684 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
825 12:40:58.315788 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
826 12:40:58.322977 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
827 12:40:58.326334 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
828 12:40:58.326433
829 12:40:58.329728 CA PerBit enable=1, Macro0, CA PI delay=34
830 12:40:58.329804
831 12:40:58.333185 [CBTSetCACLKResult] CA Dly = 34
832 12:40:58.333259 CS Dly: 6 (0~38)
833 12:40:58.333322
834 12:40:58.337131 ----->DramcWriteLeveling(PI) begin...
835 12:40:58.337207 ==
836 12:40:58.340686 Dram Type= 6, Freq= 0, CH_0, rank 0
837 12:40:58.344304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
838 12:40:58.344381 ==
839 12:40:58.347990 Write leveling (Byte 0): 33 => 33
840 12:40:58.351823 Write leveling (Byte 1): 30 => 30
841 12:40:58.354959 DramcWriteLeveling(PI) end<-----
842 12:40:58.355060
843 12:40:58.355154 ==
844 12:40:58.358211 Dram Type= 6, Freq= 0, CH_0, rank 0
845 12:40:58.361611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
846 12:40:58.361688 ==
847 12:40:58.364923 [Gating] SW mode calibration
848 12:40:58.371949 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
849 12:40:58.376203 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
850 12:40:58.379904 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
851 12:40:58.386618 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
852 12:40:58.390141 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
853 12:40:58.393752 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 12:40:58.397375 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 12:40:58.404121 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 12:40:58.407466 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 12:40:58.410952 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 12:40:58.417716 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 12:40:58.420798 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 12:40:58.424107 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 12:40:58.431190 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 12:40:58.433940 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 12:40:58.437589 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 12:40:58.440813 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 12:40:58.447426 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 12:40:58.450643 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
867 12:40:58.454281 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
868 12:40:58.460543 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
869 12:40:58.463865 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 12:40:58.466947 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 12:40:58.474050 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 12:40:58.477115 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 12:40:58.480626 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 12:40:58.487167 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 12:40:58.490233 0 9 4 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
876 12:40:58.493687 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
877 12:40:58.500444 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
878 12:40:58.503803 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 12:40:58.507271 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 12:40:58.513808 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 12:40:58.516753 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 12:40:58.520354 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
883 12:40:58.526963 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
884 12:40:58.530190 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
885 12:40:58.533766 0 10 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
886 12:40:58.540023 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 12:40:58.543725 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 12:40:58.546836 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 12:40:58.553533 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 12:40:58.557600 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 12:40:58.560118 0 11 4 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 1)
892 12:40:58.567066 0 11 8 | B1->B0 | 2727 4545 | 0 0 | (0 0) (0 0)
893 12:40:58.570338 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
894 12:40:58.573865 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 12:40:58.577062 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 12:40:58.583417 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 12:40:58.586811 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 12:40:58.590480 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 12:40:58.596926 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
900 12:40:58.600007 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 12:40:58.603392 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 12:40:58.610760 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 12:40:58.613648 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 12:40:58.616893 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 12:40:58.623391 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 12:40:58.626695 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 12:40:58.630548 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 12:40:58.637077 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 12:40:58.639998 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 12:40:58.643454 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 12:40:58.650301 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 12:40:58.653644 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 12:40:58.656953 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 12:40:58.663613 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 12:40:58.666994 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
916 12:40:58.670376 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
917 12:40:58.673538 Total UI for P1: 0, mck2ui 16
918 12:40:58.677119 best dqsien dly found for B0: ( 0, 14, 4)
919 12:40:58.680260 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
920 12:40:58.683974 Total UI for P1: 0, mck2ui 16
921 12:40:58.686872 best dqsien dly found for B1: ( 0, 14, 10)
922 12:40:58.690252 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
923 12:40:58.696962 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
924 12:40:58.697090
925 12:40:58.700343 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
926 12:40:58.703591 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
927 12:40:58.706776 [Gating] SW calibration Done
928 12:40:58.706865 ==
929 12:40:58.710280 Dram Type= 6, Freq= 0, CH_0, rank 0
930 12:40:58.713307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 12:40:58.713387 ==
932 12:40:58.713456 RX Vref Scan: 0
933 12:40:58.716828
934 12:40:58.716931 RX Vref 0 -> 0, step: 1
935 12:40:58.717051
936 12:40:58.720229 RX Delay -130 -> 252, step: 16
937 12:40:58.723228 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
938 12:40:58.726561 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
939 12:40:58.733589 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
940 12:40:58.736628 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
941 12:40:58.740020 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
942 12:40:58.743693 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
943 12:40:58.746752 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
944 12:40:58.753598 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
945 12:40:58.756381 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
946 12:40:58.759798 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
947 12:40:58.763473 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
948 12:40:58.766806 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
949 12:40:58.773248 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
950 12:40:58.776651 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
951 12:40:58.779845 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
952 12:40:58.783221 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
953 12:40:58.783307 ==
954 12:40:58.786421 Dram Type= 6, Freq= 0, CH_0, rank 0
955 12:40:58.793089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
956 12:40:58.793175 ==
957 12:40:58.793243 DQS Delay:
958 12:40:58.796424 DQS0 = 0, DQS1 = 0
959 12:40:58.796522 DQM Delay:
960 12:40:58.799771 DQM0 = 93, DQM1 = 81
961 12:40:58.799855 DQ Delay:
962 12:40:58.803287 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
963 12:40:58.806247 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
964 12:40:58.809947 DQ8 =77, DQ9 =61, DQ10 =85, DQ11 =77
965 12:40:58.813264 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
966 12:40:58.813352
967 12:40:58.813419
968 12:40:58.813480 ==
969 12:40:58.816384 Dram Type= 6, Freq= 0, CH_0, rank 0
970 12:40:58.820135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 12:40:58.820221 ==
972 12:40:58.820289
973 12:40:58.820351
974 12:40:58.823217 TX Vref Scan disable
975 12:40:58.826725 == TX Byte 0 ==
976 12:40:58.830203 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
977 12:40:58.833325 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
978 12:40:58.836541 == TX Byte 1 ==
979 12:40:58.840167 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
980 12:40:58.843353 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
981 12:40:58.843439 ==
982 12:40:58.846373 Dram Type= 6, Freq= 0, CH_0, rank 0
983 12:40:58.849859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
984 12:40:58.849944 ==
985 12:40:58.864318 TX Vref=22, minBit 6, minWin=27, winSum=440
986 12:40:58.867778 TX Vref=24, minBit 8, minWin=27, winSum=444
987 12:40:58.871068 TX Vref=26, minBit 10, minWin=27, winSum=448
988 12:40:58.874516 TX Vref=28, minBit 8, minWin=27, winSum=450
989 12:40:58.877547 TX Vref=30, minBit 8, minWin=27, winSum=455
990 12:40:58.884447 TX Vref=32, minBit 10, minWin=27, winSum=453
991 12:40:58.887741 [TxChooseVref] Worse bit 8, Min win 27, Win sum 455, Final Vref 30
992 12:40:58.887827
993 12:40:58.890762 Final TX Range 1 Vref 30
994 12:40:58.890847
995 12:40:58.890914 ==
996 12:40:58.894218 Dram Type= 6, Freq= 0, CH_0, rank 0
997 12:40:58.897779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
998 12:40:58.900758 ==
999 12:40:58.900842
1000 12:40:58.900916
1001 12:40:58.900986 TX Vref Scan disable
1002 12:40:58.904350 == TX Byte 0 ==
1003 12:40:58.907943 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1004 12:40:58.911656 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1005 12:40:58.914532 == TX Byte 1 ==
1006 12:40:58.918049 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1007 12:40:58.924432 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1008 12:40:58.924517
1009 12:40:58.924584 [DATLAT]
1010 12:40:58.924646 Freq=800, CH0 RK0
1011 12:40:58.924708
1012 12:40:58.927747 DATLAT Default: 0xa
1013 12:40:58.927831 0, 0xFFFF, sum = 0
1014 12:40:58.931006 1, 0xFFFF, sum = 0
1015 12:40:58.931092 2, 0xFFFF, sum = 0
1016 12:40:58.934382 3, 0xFFFF, sum = 0
1017 12:40:58.937993 4, 0xFFFF, sum = 0
1018 12:40:58.938079 5, 0xFFFF, sum = 0
1019 12:40:58.941026 6, 0xFFFF, sum = 0
1020 12:40:58.941112 7, 0xFFFF, sum = 0
1021 12:40:58.944414 8, 0xFFFF, sum = 0
1022 12:40:58.944499 9, 0x0, sum = 1
1023 12:40:58.944568 10, 0x0, sum = 2
1024 12:40:58.947899 11, 0x0, sum = 3
1025 12:40:58.947992 12, 0x0, sum = 4
1026 12:40:58.951147 best_step = 10
1027 12:40:58.951236
1028 12:40:58.951301 ==
1029 12:40:58.954386 Dram Type= 6, Freq= 0, CH_0, rank 0
1030 12:40:58.957980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1031 12:40:58.958064 ==
1032 12:40:58.961121 RX Vref Scan: 1
1033 12:40:58.961204
1034 12:40:58.961270 Set Vref Range= 32 -> 127
1035 12:40:58.964586
1036 12:40:58.964669 RX Vref 32 -> 127, step: 1
1037 12:40:58.964735
1038 12:40:58.968050 RX Delay -95 -> 252, step: 8
1039 12:40:58.968133
1040 12:40:58.971194 Set Vref, RX VrefLevel [Byte0]: 32
1041 12:40:58.974728 [Byte1]: 32
1042 12:40:58.974811
1043 12:40:58.978003 Set Vref, RX VrefLevel [Byte0]: 33
1044 12:40:58.980917 [Byte1]: 33
1045 12:40:58.985157
1046 12:40:58.985239 Set Vref, RX VrefLevel [Byte0]: 34
1047 12:40:58.988331 [Byte1]: 34
1048 12:40:58.992916
1049 12:40:58.993021 Set Vref, RX VrefLevel [Byte0]: 35
1050 12:40:58.995923 [Byte1]: 35
1051 12:40:59.000125
1052 12:40:59.000249 Set Vref, RX VrefLevel [Byte0]: 36
1053 12:40:59.003727 [Byte1]: 36
1054 12:40:59.007794
1055 12:40:59.007877 Set Vref, RX VrefLevel [Byte0]: 37
1056 12:40:59.011130 [Byte1]: 37
1057 12:40:59.015350
1058 12:40:59.015461 Set Vref, RX VrefLevel [Byte0]: 38
1059 12:40:59.018411 [Byte1]: 38
1060 12:40:59.023005
1061 12:40:59.023089 Set Vref, RX VrefLevel [Byte0]: 39
1062 12:40:59.029135 [Byte1]: 39
1063 12:40:59.029218
1064 12:40:59.032796 Set Vref, RX VrefLevel [Byte0]: 40
1065 12:40:59.036224 [Byte1]: 40
1066 12:40:59.036308
1067 12:40:59.040354 Set Vref, RX VrefLevel [Byte0]: 41
1068 12:40:59.043384 [Byte1]: 41
1069 12:40:59.043495
1070 12:40:59.046996 Set Vref, RX VrefLevel [Byte0]: 42
1071 12:40:59.050593 [Byte1]: 42
1072 12:40:59.050677
1073 12:40:59.054456 Set Vref, RX VrefLevel [Byte0]: 43
1074 12:40:59.057994 [Byte1]: 43
1075 12:40:59.061154
1076 12:40:59.061256 Set Vref, RX VrefLevel [Byte0]: 44
1077 12:40:59.064847 [Byte1]: 44
1078 12:40:59.068703
1079 12:40:59.068805 Set Vref, RX VrefLevel [Byte0]: 45
1080 12:40:59.071972 [Byte1]: 45
1081 12:40:59.076115
1082 12:40:59.076188 Set Vref, RX VrefLevel [Byte0]: 46
1083 12:40:59.079492 [Byte1]: 46
1084 12:40:59.083654
1085 12:40:59.083724 Set Vref, RX VrefLevel [Byte0]: 47
1086 12:40:59.086824 [Byte1]: 47
1087 12:40:59.091854
1088 12:40:59.091951 Set Vref, RX VrefLevel [Byte0]: 48
1089 12:40:59.094701 [Byte1]: 48
1090 12:40:59.098881
1091 12:40:59.098990 Set Vref, RX VrefLevel [Byte0]: 49
1092 12:40:59.101882 [Byte1]: 49
1093 12:40:59.106160
1094 12:40:59.106232 Set Vref, RX VrefLevel [Byte0]: 50
1095 12:40:59.109801 [Byte1]: 50
1096 12:40:59.114016
1097 12:40:59.114089 Set Vref, RX VrefLevel [Byte0]: 51
1098 12:40:59.117257 [Byte1]: 51
1099 12:40:59.121513
1100 12:40:59.121609 Set Vref, RX VrefLevel [Byte0]: 52
1101 12:40:59.124868 [Byte1]: 52
1102 12:40:59.128952
1103 12:40:59.129054 Set Vref, RX VrefLevel [Byte0]: 53
1104 12:40:59.132796 [Byte1]: 53
1105 12:40:59.136617
1106 12:40:59.136715 Set Vref, RX VrefLevel [Byte0]: 54
1107 12:40:59.140292 [Byte1]: 54
1108 12:40:59.144517
1109 12:40:59.144615 Set Vref, RX VrefLevel [Byte0]: 55
1110 12:40:59.147636 [Byte1]: 55
1111 12:40:59.151719
1112 12:40:59.151817 Set Vref, RX VrefLevel [Byte0]: 56
1113 12:40:59.155152 [Byte1]: 56
1114 12:40:59.160014
1115 12:40:59.160109 Set Vref, RX VrefLevel [Byte0]: 57
1116 12:40:59.162909 [Byte1]: 57
1117 12:40:59.167375
1118 12:40:59.167446 Set Vref, RX VrefLevel [Byte0]: 58
1119 12:40:59.170331 [Byte1]: 58
1120 12:40:59.174751
1121 12:40:59.174821 Set Vref, RX VrefLevel [Byte0]: 59
1122 12:40:59.178300 [Byte1]: 59
1123 12:40:59.182587
1124 12:40:59.182655 Set Vref, RX VrefLevel [Byte0]: 60
1125 12:40:59.185646 [Byte1]: 60
1126 12:40:59.190167
1127 12:40:59.190238 Set Vref, RX VrefLevel [Byte0]: 61
1128 12:40:59.193139 [Byte1]: 61
1129 12:40:59.197909
1130 12:40:59.198020 Set Vref, RX VrefLevel [Byte0]: 62
1131 12:40:59.200721 [Byte1]: 62
1132 12:40:59.204989
1133 12:40:59.205093 Set Vref, RX VrefLevel [Byte0]: 63
1134 12:40:59.208208 [Byte1]: 63
1135 12:40:59.212477
1136 12:40:59.212575 Set Vref, RX VrefLevel [Byte0]: 64
1137 12:40:59.216242 [Byte1]: 64
1138 12:40:59.220171
1139 12:40:59.220268 Set Vref, RX VrefLevel [Byte0]: 65
1140 12:40:59.224206 [Byte1]: 65
1141 12:40:59.228110
1142 12:40:59.228208 Set Vref, RX VrefLevel [Byte0]: 66
1143 12:40:59.231283 [Byte1]: 66
1144 12:40:59.235678
1145 12:40:59.235774 Set Vref, RX VrefLevel [Byte0]: 67
1146 12:40:59.239110 [Byte1]: 67
1147 12:40:59.243246
1148 12:40:59.243343 Set Vref, RX VrefLevel [Byte0]: 68
1149 12:40:59.246202 [Byte1]: 68
1150 12:40:59.250636
1151 12:40:59.250707 Set Vref, RX VrefLevel [Byte0]: 69
1152 12:40:59.254074 [Byte1]: 69
1153 12:40:59.258304
1154 12:40:59.258376 Set Vref, RX VrefLevel [Byte0]: 70
1155 12:40:59.261727 [Byte1]: 70
1156 12:40:59.265871
1157 12:40:59.265945 Set Vref, RX VrefLevel [Byte0]: 71
1158 12:40:59.269338 [Byte1]: 71
1159 12:40:59.273644
1160 12:40:59.273714 Set Vref, RX VrefLevel [Byte0]: 72
1161 12:40:59.276636 [Byte1]: 72
1162 12:40:59.281139
1163 12:40:59.281208 Set Vref, RX VrefLevel [Byte0]: 73
1164 12:40:59.284653 [Byte1]: 73
1165 12:40:59.288863
1166 12:40:59.288931 Set Vref, RX VrefLevel [Byte0]: 74
1167 12:40:59.292161 [Byte1]: 74
1168 12:40:59.296415
1169 12:40:59.296526 Set Vref, RX VrefLevel [Byte0]: 75
1170 12:40:59.299499 [Byte1]: 75
1171 12:40:59.303903
1172 12:40:59.304008 Set Vref, RX VrefLevel [Byte0]: 76
1173 12:40:59.307244 [Byte1]: 76
1174 12:40:59.311729
1175 12:40:59.311829 Final RX Vref Byte 0 = 60 to rank0
1176 12:40:59.314893 Final RX Vref Byte 1 = 62 to rank0
1177 12:40:59.318385 Final RX Vref Byte 0 = 60 to rank1
1178 12:40:59.321392 Final RX Vref Byte 1 = 62 to rank1==
1179 12:40:59.324761 Dram Type= 6, Freq= 0, CH_0, rank 0
1180 12:40:59.331745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1181 12:40:59.331848 ==
1182 12:40:59.331949 DQS Delay:
1183 12:40:59.332039 DQS0 = 0, DQS1 = 0
1184 12:40:59.334952 DQM Delay:
1185 12:40:59.335049 DQM0 = 93, DQM1 = 83
1186 12:40:59.338174 DQ Delay:
1187 12:40:59.341593 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1188 12:40:59.344792 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1189 12:40:59.348214 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1190 12:40:59.351241 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
1191 12:40:59.351337
1192 12:40:59.351430
1193 12:40:59.358250 [DQSOSCAuto] RK0, (LSB)MR18= 0x3833, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
1194 12:40:59.361440 CH0 RK0: MR19=606, MR18=3833
1195 12:40:59.368104 CH0_RK0: MR19=0x606, MR18=0x3833, DQSOSC=395, MR23=63, INC=94, DEC=63
1196 12:40:59.368201
1197 12:40:59.371455 ----->DramcWriteLeveling(PI) begin...
1198 12:40:59.371552 ==
1199 12:40:59.374731 Dram Type= 6, Freq= 0, CH_0, rank 1
1200 12:40:59.377702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1201 12:40:59.377784 ==
1202 12:40:59.381498 Write leveling (Byte 0): 32 => 32
1203 12:40:59.384660 Write leveling (Byte 1): 30 => 30
1204 12:40:59.388201 DramcWriteLeveling(PI) end<-----
1205 12:40:59.388303
1206 12:40:59.388392 ==
1207 12:40:59.391272 Dram Type= 6, Freq= 0, CH_0, rank 1
1208 12:40:59.394787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1209 12:40:59.394873 ==
1210 12:40:59.398099 [Gating] SW mode calibration
1211 12:40:59.404407 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1212 12:40:59.411141 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1213 12:40:59.414514 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1214 12:40:59.418089 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1215 12:40:59.424494 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 12:40:59.427921 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 12:40:59.431202 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 12:40:59.438047 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 12:40:59.482062 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 12:40:59.482503 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 12:40:59.482588 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 12:40:59.483056 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 12:40:59.483445 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 12:40:59.483710 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 12:40:59.484262 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 12:40:59.484349 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 12:40:59.484605 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 12:40:59.484895 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 12:40:59.496714 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 12:40:59.497191 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1231 12:40:59.497275 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 12:40:59.500246 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 12:40:59.503819 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 12:40:59.506861 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 12:40:59.510343 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 12:40:59.516774 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 12:40:59.520173 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 12:40:59.523209 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (1 1) (1 1)
1239 12:40:59.530128 0 9 8 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
1240 12:40:59.533127 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 12:40:59.536476 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 12:40:59.543305 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 12:40:59.546707 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 12:40:59.549880 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 12:40:59.556514 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 12:40:59.559943 0 10 4 | B1->B0 | 3333 2f2f | 0 0 | (0 1) (0 1)
1247 12:40:59.563198 0 10 8 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
1248 12:40:59.569845 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 12:40:59.573213 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 12:40:59.576214 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 12:40:59.582924 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 12:40:59.586280 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 12:40:59.589709 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 12:40:59.596171 0 11 4 | B1->B0 | 2626 2e2e | 0 0 | (0 0) (0 0)
1255 12:40:59.599771 0 11 8 | B1->B0 | 3d3d 4444 | 1 0 | (0 0) (0 0)
1256 12:40:59.603052 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 12:40:59.610148 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 12:40:59.613203 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 12:40:59.616880 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 12:40:59.620753 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 12:40:59.627542 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 12:40:59.631303 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 12:40:59.634940 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 12:40:59.638035 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 12:40:59.644994 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 12:40:59.648381 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 12:40:59.651546 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 12:40:59.658310 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 12:40:59.661777 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 12:40:59.664859 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 12:40:59.671533 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 12:40:59.675254 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 12:40:59.678469 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 12:40:59.681792 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 12:40:59.688478 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 12:40:59.691999 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 12:40:59.694838 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 12:40:59.701537 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1279 12:40:59.705028 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1280 12:40:59.708551 Total UI for P1: 0, mck2ui 16
1281 12:40:59.711709 best dqsien dly found for B1: ( 0, 14, 6)
1282 12:40:59.714733 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1283 12:40:59.718628 Total UI for P1: 0, mck2ui 16
1284 12:40:59.721797 best dqsien dly found for B0: ( 0, 14, 6)
1285 12:40:59.725081 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1286 12:40:59.728520 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1287 12:40:59.728919
1288 12:40:59.734998 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1289 12:40:59.738344 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1290 12:40:59.741672 [Gating] SW calibration Done
1291 12:40:59.742145 ==
1292 12:40:59.744883 Dram Type= 6, Freq= 0, CH_0, rank 1
1293 12:40:59.748211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1294 12:40:59.748688 ==
1295 12:40:59.749093 RX Vref Scan: 0
1296 12:40:59.749446
1297 12:40:59.751828 RX Vref 0 -> 0, step: 1
1298 12:40:59.752395
1299 12:40:59.754990 RX Delay -130 -> 252, step: 16
1300 12:40:59.758383 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1301 12:40:59.761930 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1302 12:40:59.768592 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1303 12:40:59.772159 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1304 12:40:59.775473 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1305 12:40:59.778613 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1306 12:40:59.782256 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1307 12:40:59.788775 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1308 12:40:59.791632 iDelay=222, Bit 8, Center 69 (-34 ~ 173) 208
1309 12:40:59.795088 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1310 12:40:59.798297 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1311 12:40:59.801706 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1312 12:40:59.808076 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1313 12:40:59.811704 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1314 12:40:59.815174 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1315 12:40:59.818388 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1316 12:40:59.818957 ==
1317 12:40:59.821877 Dram Type= 6, Freq= 0, CH_0, rank 1
1318 12:40:59.828141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1319 12:40:59.828713 ==
1320 12:40:59.829124 DQS Delay:
1321 12:40:59.829472 DQS0 = 0, DQS1 = 0
1322 12:40:59.831550 DQM Delay:
1323 12:40:59.832119 DQM0 = 90, DQM1 = 80
1324 12:40:59.834636 DQ Delay:
1325 12:40:59.838321 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1326 12:40:59.841632 DQ4 =93, DQ5 =77, DQ6 =109, DQ7 =101
1327 12:40:59.844754 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1328 12:40:59.847891 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =93
1329 12:40:59.848386
1330 12:40:59.848753
1331 12:40:59.849126 ==
1332 12:40:59.851488 Dram Type= 6, Freq= 0, CH_0, rank 1
1333 12:40:59.854822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1334 12:40:59.855401 ==
1335 12:40:59.855773
1336 12:40:59.856115
1337 12:40:59.858046 TX Vref Scan disable
1338 12:40:59.858516 == TX Byte 0 ==
1339 12:40:59.864738 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1340 12:40:59.868255 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1341 12:40:59.868874 == TX Byte 1 ==
1342 12:40:59.874948 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1343 12:40:59.877897 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1344 12:40:59.878382 ==
1345 12:40:59.881520 Dram Type= 6, Freq= 0, CH_0, rank 1
1346 12:40:59.884536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1347 12:40:59.885147 ==
1348 12:40:59.898994 TX Vref=22, minBit 1, minWin=27, winSum=445
1349 12:40:59.901892 TX Vref=24, minBit 8, minWin=27, winSum=448
1350 12:40:59.905955 TX Vref=26, minBit 8, minWin=27, winSum=451
1351 12:40:59.908816 TX Vref=28, minBit 8, minWin=27, winSum=455
1352 12:40:59.912139 TX Vref=30, minBit 8, minWin=27, winSum=456
1353 12:40:59.919339 TX Vref=32, minBit 8, minWin=28, winSum=459
1354 12:40:59.922673 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 32
1355 12:40:59.923250
1356 12:40:59.925580 Final TX Range 1 Vref 32
1357 12:40:59.926054
1358 12:40:59.926422 ==
1359 12:40:59.928858 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 12:40:59.931983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 12:40:59.932448 ==
1362 12:40:59.935145
1363 12:40:59.935601
1364 12:40:59.935956 TX Vref Scan disable
1365 12:40:59.939075 == TX Byte 0 ==
1366 12:40:59.942049 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1367 12:40:59.948747 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1368 12:40:59.949274 == TX Byte 1 ==
1369 12:40:59.952040 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1370 12:40:59.958735 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1371 12:40:59.959078
1372 12:40:59.959334 [DATLAT]
1373 12:40:59.959571 Freq=800, CH0 RK1
1374 12:40:59.959798
1375 12:40:59.961673 DATLAT Default: 0xa
1376 12:40:59.962093 0, 0xFFFF, sum = 0
1377 12:40:59.965141 1, 0xFFFF, sum = 0
1378 12:40:59.968415 2, 0xFFFF, sum = 0
1379 12:40:59.968750 3, 0xFFFF, sum = 0
1380 12:40:59.972018 4, 0xFFFF, sum = 0
1381 12:40:59.972456 5, 0xFFFF, sum = 0
1382 12:40:59.974927 6, 0xFFFF, sum = 0
1383 12:40:59.975349 7, 0xFFFF, sum = 0
1384 12:40:59.978982 8, 0xFFFF, sum = 0
1385 12:40:59.979413 9, 0x0, sum = 1
1386 12:40:59.981835 10, 0x0, sum = 2
1387 12:40:59.982270 11, 0x0, sum = 3
1388 12:40:59.982541 12, 0x0, sum = 4
1389 12:40:59.985039 best_step = 10
1390 12:40:59.985363
1391 12:40:59.985618 ==
1392 12:40:59.988397 Dram Type= 6, Freq= 0, CH_0, rank 1
1393 12:40:59.991725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1394 12:40:59.992151 ==
1395 12:40:59.994972 RX Vref Scan: 0
1396 12:40:59.995396
1397 12:40:59.998196 RX Vref 0 -> 0, step: 1
1398 12:40:59.998519
1399 12:40:59.998787 RX Delay -79 -> 252, step: 8
1400 12:41:00.005345 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1401 12:41:00.008949 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1402 12:41:00.012064 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1403 12:41:00.015599 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1404 12:41:00.018871 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1405 12:41:00.025591 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1406 12:41:00.028756 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1407 12:41:00.031943 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1408 12:41:00.035407 iDelay=209, Bit 8, Center 76 (-23 ~ 176) 200
1409 12:41:00.038632 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1410 12:41:00.045136 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1411 12:41:00.048437 iDelay=209, Bit 11, Center 76 (-23 ~ 176) 200
1412 12:41:00.052152 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1413 12:41:00.055148 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1414 12:41:00.062009 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1415 12:41:00.065053 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1416 12:41:00.065666 ==
1417 12:41:00.068391 Dram Type= 6, Freq= 0, CH_0, rank 1
1418 12:41:00.072098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1419 12:41:00.072665 ==
1420 12:41:00.075569 DQS Delay:
1421 12:41:00.076177 DQS0 = 0, DQS1 = 0
1422 12:41:00.076617 DQM Delay:
1423 12:41:00.078148 DQM0 = 91, DQM1 = 81
1424 12:41:00.078608 DQ Delay:
1425 12:41:00.081560 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1426 12:41:00.084942 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1427 12:41:00.088166 DQ8 =76, DQ9 =72, DQ10 =80, DQ11 =76
1428 12:41:00.091721 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1429 12:41:00.092428
1430 12:41:00.092810
1431 12:41:00.101333 [DQSOSCAuto] RK1, (LSB)MR18= 0x4721, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
1432 12:41:00.104454 CH0 RK1: MR19=606, MR18=4721
1433 12:41:00.107878 CH0_RK1: MR19=0x606, MR18=0x4721, DQSOSC=392, MR23=63, INC=96, DEC=64
1434 12:41:00.111754 [RxdqsGatingPostProcess] freq 800
1435 12:41:00.118100 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1436 12:41:00.121523 Pre-setting of DQS Precalculation
1437 12:41:00.124540 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1438 12:41:00.125147 ==
1439 12:41:00.127737 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 12:41:00.134265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 12:41:00.134836 ==
1442 12:41:00.137610 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1443 12:41:00.144461 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1444 12:41:00.154029 [CA 0] Center 36 (6~67) winsize 62
1445 12:41:00.157856 [CA 1] Center 36 (6~67) winsize 62
1446 12:41:00.160355 [CA 2] Center 35 (5~65) winsize 61
1447 12:41:00.163710 [CA 3] Center 34 (3~65) winsize 63
1448 12:41:00.166898 [CA 4] Center 34 (4~65) winsize 62
1449 12:41:00.170247 [CA 5] Center 33 (3~64) winsize 62
1450 12:41:00.170709
1451 12:41:00.174144 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1452 12:41:00.174619
1453 12:41:00.177121 [CATrainingPosCal] consider 1 rank data
1454 12:41:00.180415 u2DelayCellTimex100 = 270/100 ps
1455 12:41:00.183747 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1456 12:41:00.190673 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1457 12:41:00.193727 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1458 12:41:00.197106 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1459 12:41:00.200641 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1460 12:41:00.203359 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1461 12:41:00.203818
1462 12:41:00.207086 CA PerBit enable=1, Macro0, CA PI delay=33
1463 12:41:00.207647
1464 12:41:00.210205 [CBTSetCACLKResult] CA Dly = 33
1465 12:41:00.210690 CS Dly: 5 (0~36)
1466 12:41:00.213897 ==
1467 12:41:00.216907 Dram Type= 6, Freq= 0, CH_1, rank 1
1468 12:41:00.220544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1469 12:41:00.221156 ==
1470 12:41:00.224119 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1471 12:41:00.230359 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1472 12:41:00.240267 [CA 0] Center 37 (6~68) winsize 63
1473 12:41:00.243820 [CA 1] Center 37 (6~68) winsize 63
1474 12:41:00.246823 [CA 2] Center 35 (5~66) winsize 62
1475 12:41:00.250232 [CA 3] Center 34 (4~65) winsize 62
1476 12:41:00.253824 [CA 4] Center 34 (4~65) winsize 62
1477 12:41:00.256952 [CA 5] Center 34 (4~64) winsize 61
1478 12:41:00.257559
1479 12:41:00.260269 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1480 12:41:00.260841
1481 12:41:00.263238 [CATrainingPosCal] consider 2 rank data
1482 12:41:00.266732 u2DelayCellTimex100 = 270/100 ps
1483 12:41:00.270001 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1484 12:41:00.277123 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1485 12:41:00.280013 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1486 12:41:00.283667 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1487 12:41:00.287085 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1488 12:41:00.290745 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1489 12:41:00.291261
1490 12:41:00.294361 CA PerBit enable=1, Macro0, CA PI delay=34
1491 12:41:00.294832
1492 12:41:00.297577 [CBTSetCACLKResult] CA Dly = 34
1493 12:41:00.298048 CS Dly: 6 (0~38)
1494 12:41:00.298421
1495 12:41:00.300949 ----->DramcWriteLeveling(PI) begin...
1496 12:41:00.301494 ==
1497 12:41:00.304724 Dram Type= 6, Freq= 0, CH_1, rank 0
1498 12:41:00.308348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1499 12:41:00.308822 ==
1500 12:41:00.312006 Write leveling (Byte 0): 26 => 26
1501 12:41:00.315569 Write leveling (Byte 1): 28 => 28
1502 12:41:00.319136 DramcWriteLeveling(PI) end<-----
1503 12:41:00.319714
1504 12:41:00.320096 ==
1505 12:41:00.322143 Dram Type= 6, Freq= 0, CH_1, rank 0
1506 12:41:00.325567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1507 12:41:00.326047 ==
1508 12:41:00.329096 [Gating] SW mode calibration
1509 12:41:00.335299 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1510 12:41:00.342399 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1511 12:41:00.345684 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1512 12:41:00.349056 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1513 12:41:00.355684 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 12:41:00.359457 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 12:41:00.362430 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 12:41:00.369464 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 12:41:00.372197 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 12:41:00.375689 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 12:41:00.382842 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 12:41:00.385545 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 12:41:00.388810 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 12:41:00.395254 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 12:41:00.398521 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 12:41:00.402052 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 12:41:00.408671 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 12:41:00.412026 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 12:41:00.415447 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1528 12:41:00.421726 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1529 12:41:00.425284 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1530 12:41:00.428614 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 12:41:00.435656 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 12:41:00.439121 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 12:41:00.441986 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 12:41:00.448702 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 12:41:00.452296 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 12:41:00.455137 0 9 4 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (0 0)
1537 12:41:00.461798 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 12:41:00.465459 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 12:41:00.468482 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 12:41:00.471914 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 12:41:00.478625 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 12:41:00.481802 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 12:41:00.485340 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
1544 12:41:00.491880 0 10 4 | B1->B0 | 2929 2929 | 1 0 | (1 0) (0 0)
1545 12:41:00.495063 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 12:41:00.498560 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 12:41:00.504816 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 12:41:00.508524 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 12:41:00.511442 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 12:41:00.518359 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 12:41:00.521430 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1552 12:41:00.525013 0 11 4 | B1->B0 | 3030 3636 | 0 0 | (1 1) (0 0)
1553 12:41:00.531269 0 11 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1554 12:41:00.535164 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 12:41:00.538144 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 12:41:00.545764 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 12:41:00.548384 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 12:41:00.552127 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 12:41:00.558367 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1560 12:41:00.561710 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1561 12:41:00.565010 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 12:41:00.571710 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 12:41:00.574956 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 12:41:00.578395 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 12:41:00.585031 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 12:41:00.588212 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 12:41:00.591346 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 12:41:00.598010 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 12:41:00.601329 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 12:41:00.604611 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 12:41:00.607899 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 12:41:00.614794 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 12:41:00.617583 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 12:41:00.620892 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 12:41:00.627783 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1576 12:41:00.631279 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1577 12:41:00.634602 Total UI for P1: 0, mck2ui 16
1578 12:41:00.638107 best dqsien dly found for B0: ( 0, 14, 0)
1579 12:41:00.640915 Total UI for P1: 0, mck2ui 16
1580 12:41:00.644534 best dqsien dly found for B1: ( 0, 14, 2)
1581 12:41:00.647847 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1582 12:41:00.650763 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1583 12:41:00.651238
1584 12:41:00.654638 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1585 12:41:00.657837 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1586 12:41:00.661241 [Gating] SW calibration Done
1587 12:41:00.661816 ==
1588 12:41:00.664255 Dram Type= 6, Freq= 0, CH_1, rank 0
1589 12:41:00.671290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1590 12:41:00.671860 ==
1591 12:41:00.672234 RX Vref Scan: 0
1592 12:41:00.672578
1593 12:41:00.674405 RX Vref 0 -> 0, step: 1
1594 12:41:00.674973
1595 12:41:00.677617 RX Delay -130 -> 252, step: 16
1596 12:41:00.680903 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1597 12:41:00.684127 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1598 12:41:00.687688 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1599 12:41:00.690814 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1600 12:41:00.697374 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1601 12:41:00.700608 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1602 12:41:00.704152 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1603 12:41:00.707665 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1604 12:41:00.710654 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1605 12:41:00.717637 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1606 12:41:00.720572 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1607 12:41:00.724023 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1608 12:41:00.727402 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1609 12:41:00.733998 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1610 12:41:00.737483 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1611 12:41:00.740824 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1612 12:41:00.741431 ==
1613 12:41:00.744235 Dram Type= 6, Freq= 0, CH_1, rank 0
1614 12:41:00.747161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1615 12:41:00.747736 ==
1616 12:41:00.750804 DQS Delay:
1617 12:41:00.751376 DQS0 = 0, DQS1 = 0
1618 12:41:00.753897 DQM Delay:
1619 12:41:00.754469 DQM0 = 92, DQM1 = 81
1620 12:41:00.754845 DQ Delay:
1621 12:41:00.757694 DQ0 =101, DQ1 =77, DQ2 =77, DQ3 =93
1622 12:41:00.761229 DQ4 =85, DQ5 =101, DQ6 =109, DQ7 =93
1623 12:41:00.763968 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1624 12:41:00.767171 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1625 12:41:00.767641
1626 12:41:00.768016
1627 12:41:00.770934 ==
1628 12:41:00.773896 Dram Type= 6, Freq= 0, CH_1, rank 0
1629 12:41:00.777269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1630 12:41:00.777846 ==
1631 12:41:00.778222
1632 12:41:00.778564
1633 12:41:00.780590 TX Vref Scan disable
1634 12:41:00.781201 == TX Byte 0 ==
1635 12:41:00.783937 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1636 12:41:00.790551 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1637 12:41:00.791120 == TX Byte 1 ==
1638 12:41:00.793994 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1639 12:41:00.800446 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1640 12:41:00.800946 ==
1641 12:41:00.803554 Dram Type= 6, Freq= 0, CH_1, rank 0
1642 12:41:00.807012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1643 12:41:00.807488 ==
1644 12:41:00.820083 TX Vref=22, minBit 8, minWin=27, winSum=448
1645 12:41:00.823676 TX Vref=24, minBit 15, minWin=27, winSum=459
1646 12:41:00.826462 TX Vref=26, minBit 15, minWin=27, winSum=457
1647 12:41:00.829834 TX Vref=28, minBit 9, minWin=28, winSum=461
1648 12:41:00.833118 TX Vref=30, minBit 15, minWin=27, winSum=461
1649 12:41:00.839874 TX Vref=32, minBit 8, minWin=28, winSum=460
1650 12:41:00.843154 [TxChooseVref] Worse bit 9, Min win 28, Win sum 461, Final Vref 28
1651 12:41:00.843290
1652 12:41:00.846379 Final TX Range 1 Vref 28
1653 12:41:00.846522
1654 12:41:00.846629 ==
1655 12:41:00.849797 Dram Type= 6, Freq= 0, CH_1, rank 0
1656 12:41:00.853231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1657 12:41:00.856642 ==
1658 12:41:00.857136
1659 12:41:00.857504
1660 12:41:00.857844 TX Vref Scan disable
1661 12:41:00.860334 == TX Byte 0 ==
1662 12:41:00.863654 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1663 12:41:00.867043 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1664 12:41:00.870555 == TX Byte 1 ==
1665 12:41:00.874199 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1666 12:41:00.877596 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1667 12:41:00.878063
1668 12:41:00.880940 [DATLAT]
1669 12:41:00.881381 Freq=800, CH1 RK0
1670 12:41:00.881716
1671 12:41:00.884004 DATLAT Default: 0xa
1672 12:41:00.884426 0, 0xFFFF, sum = 0
1673 12:41:00.887463 1, 0xFFFF, sum = 0
1674 12:41:00.887893 2, 0xFFFF, sum = 0
1675 12:41:00.891042 3, 0xFFFF, sum = 0
1676 12:41:00.891472 4, 0xFFFF, sum = 0
1677 12:41:00.893899 5, 0xFFFF, sum = 0
1678 12:41:00.894329 6, 0xFFFF, sum = 0
1679 12:41:00.897148 7, 0xFFFF, sum = 0
1680 12:41:00.897576 8, 0xFFFF, sum = 0
1681 12:41:00.900964 9, 0x0, sum = 1
1682 12:41:00.901422 10, 0x0, sum = 2
1683 12:41:00.903989 11, 0x0, sum = 3
1684 12:41:00.904414 12, 0x0, sum = 4
1685 12:41:00.907371 best_step = 10
1686 12:41:00.907895
1687 12:41:00.908231 ==
1688 12:41:00.911100 Dram Type= 6, Freq= 0, CH_1, rank 0
1689 12:41:00.914642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1690 12:41:00.915310 ==
1691 12:41:00.917310 RX Vref Scan: 1
1692 12:41:00.917747
1693 12:41:00.918086 Set Vref Range= 32 -> 127
1694 12:41:00.918395
1695 12:41:00.920269 RX Vref 32 -> 127, step: 1
1696 12:41:00.920694
1697 12:41:00.923862 RX Delay -95 -> 252, step: 8
1698 12:41:00.924387
1699 12:41:00.927069 Set Vref, RX VrefLevel [Byte0]: 32
1700 12:41:00.930674 [Byte1]: 32
1701 12:41:00.931226
1702 12:41:00.933703 Set Vref, RX VrefLevel [Byte0]: 33
1703 12:41:00.937141 [Byte1]: 33
1704 12:41:00.940706
1705 12:41:00.941290 Set Vref, RX VrefLevel [Byte0]: 34
1706 12:41:00.944110 [Byte1]: 34
1707 12:41:00.948572
1708 12:41:00.949127 Set Vref, RX VrefLevel [Byte0]: 35
1709 12:41:00.951621 [Byte1]: 35
1710 12:41:00.956252
1711 12:41:00.956816 Set Vref, RX VrefLevel [Byte0]: 36
1712 12:41:00.959451 [Byte1]: 36
1713 12:41:00.963690
1714 12:41:00.964255 Set Vref, RX VrefLevel [Byte0]: 37
1715 12:41:00.966460 [Byte1]: 37
1716 12:41:00.971309
1717 12:41:00.971875 Set Vref, RX VrefLevel [Byte0]: 38
1718 12:41:00.974358 [Byte1]: 38
1719 12:41:00.978517
1720 12:41:00.979083 Set Vref, RX VrefLevel [Byte0]: 39
1721 12:41:00.981896 [Byte1]: 39
1722 12:41:00.986504
1723 12:41:00.987066 Set Vref, RX VrefLevel [Byte0]: 40
1724 12:41:00.993144 [Byte1]: 40
1725 12:41:00.993708
1726 12:41:00.996461 Set Vref, RX VrefLevel [Byte0]: 41
1727 12:41:00.999349 [Byte1]: 41
1728 12:41:00.999966
1729 12:41:01.002461 Set Vref, RX VrefLevel [Byte0]: 42
1730 12:41:01.005757 [Byte1]: 42
1731 12:41:01.006288
1732 12:41:01.009291 Set Vref, RX VrefLevel [Byte0]: 43
1733 12:41:01.012796 [Byte1]: 43
1734 12:41:01.017111
1735 12:41:01.017673 Set Vref, RX VrefLevel [Byte0]: 44
1736 12:41:01.020028 [Byte1]: 44
1737 12:41:01.024246
1738 12:41:01.024810 Set Vref, RX VrefLevel [Byte0]: 45
1739 12:41:01.027647 [Byte1]: 45
1740 12:41:01.031685
1741 12:41:01.032147 Set Vref, RX VrefLevel [Byte0]: 46
1742 12:41:01.035472 [Byte1]: 46
1743 12:41:01.039400
1744 12:41:01.039975 Set Vref, RX VrefLevel [Byte0]: 47
1745 12:41:01.042629 [Byte1]: 47
1746 12:41:01.046976
1747 12:41:01.047442 Set Vref, RX VrefLevel [Byte0]: 48
1748 12:41:01.050330 [Byte1]: 48
1749 12:41:01.054836
1750 12:41:01.055398 Set Vref, RX VrefLevel [Byte0]: 49
1751 12:41:01.058060 [Byte1]: 49
1752 12:41:01.062460
1753 12:41:01.063025 Set Vref, RX VrefLevel [Byte0]: 50
1754 12:41:01.065665 [Byte1]: 50
1755 12:41:01.069830
1756 12:41:01.070395 Set Vref, RX VrefLevel [Byte0]: 51
1757 12:41:01.073237 [Byte1]: 51
1758 12:41:01.077514
1759 12:41:01.078080 Set Vref, RX VrefLevel [Byte0]: 52
1760 12:41:01.081041 [Byte1]: 52
1761 12:41:01.085402
1762 12:41:01.085970 Set Vref, RX VrefLevel [Byte0]: 53
1763 12:41:01.091628 [Byte1]: 53
1764 12:41:01.092196
1765 12:41:01.095048 Set Vref, RX VrefLevel [Byte0]: 54
1766 12:41:01.098278 [Byte1]: 54
1767 12:41:01.098748
1768 12:41:01.101090 Set Vref, RX VrefLevel [Byte0]: 55
1769 12:41:01.104607 [Byte1]: 55
1770 12:41:01.105144
1771 12:41:01.108097 Set Vref, RX VrefLevel [Byte0]: 56
1772 12:41:01.111697 [Byte1]: 56
1773 12:41:01.115552
1774 12:41:01.116116 Set Vref, RX VrefLevel [Byte0]: 57
1775 12:41:01.118909 [Byte1]: 57
1776 12:41:01.122950
1777 12:41:01.123516 Set Vref, RX VrefLevel [Byte0]: 58
1778 12:41:01.126503 [Byte1]: 58
1779 12:41:01.130820
1780 12:41:01.131383 Set Vref, RX VrefLevel [Byte0]: 59
1781 12:41:01.133808 [Byte1]: 59
1782 12:41:01.138040
1783 12:41:01.138530 Set Vref, RX VrefLevel [Byte0]: 60
1784 12:41:01.141578 [Byte1]: 60
1785 12:41:01.146119
1786 12:41:01.146590 Set Vref, RX VrefLevel [Byte0]: 61
1787 12:41:01.149377 [Byte1]: 61
1788 12:41:01.153606
1789 12:41:01.154074 Set Vref, RX VrefLevel [Byte0]: 62
1790 12:41:01.156723 [Byte1]: 62
1791 12:41:01.160803
1792 12:41:01.161317 Set Vref, RX VrefLevel [Byte0]: 63
1793 12:41:01.164365 [Byte1]: 63
1794 12:41:01.168777
1795 12:41:01.169443 Set Vref, RX VrefLevel [Byte0]: 64
1796 12:41:01.172192 [Byte1]: 64
1797 12:41:01.176691
1798 12:41:01.177283 Set Vref, RX VrefLevel [Byte0]: 65
1799 12:41:01.179358 [Byte1]: 65
1800 12:41:01.183967
1801 12:41:01.184526 Set Vref, RX VrefLevel [Byte0]: 66
1802 12:41:01.187323 [Byte1]: 66
1803 12:41:01.191636
1804 12:41:01.192198 Set Vref, RX VrefLevel [Byte0]: 67
1805 12:41:01.195028 [Byte1]: 67
1806 12:41:01.199220
1807 12:41:01.199784 Set Vref, RX VrefLevel [Byte0]: 68
1808 12:41:01.202383 [Byte1]: 68
1809 12:41:01.206767
1810 12:41:01.207236 Set Vref, RX VrefLevel [Byte0]: 69
1811 12:41:01.209792 [Byte1]: 69
1812 12:41:01.214264
1813 12:41:01.214730 Set Vref, RX VrefLevel [Byte0]: 70
1814 12:41:01.217851 [Byte1]: 70
1815 12:41:01.221630
1816 12:41:01.222099 Set Vref, RX VrefLevel [Byte0]: 71
1817 12:41:01.225334 [Byte1]: 71
1818 12:41:01.229547
1819 12:41:01.230110 Set Vref, RX VrefLevel [Byte0]: 72
1820 12:41:01.232520 [Byte1]: 72
1821 12:41:01.237078
1822 12:41:01.237542 Set Vref, RX VrefLevel [Byte0]: 73
1823 12:41:01.241001 [Byte1]: 73
1824 12:41:01.244373
1825 12:41:01.244931 Set Vref, RX VrefLevel [Byte0]: 74
1826 12:41:01.247745 [Byte1]: 74
1827 12:41:01.252067
1828 12:41:01.252538 Set Vref, RX VrefLevel [Byte0]: 75
1829 12:41:01.255599 [Byte1]: 75
1830 12:41:01.259567
1831 12:41:01.260033 Set Vref, RX VrefLevel [Byte0]: 76
1832 12:41:01.262832 [Byte1]: 76
1833 12:41:01.267400
1834 12:41:01.267969 Set Vref, RX VrefLevel [Byte0]: 77
1835 12:41:01.270879 [Byte1]: 77
1836 12:41:01.274749
1837 12:41:01.275215 Final RX Vref Byte 0 = 50 to rank0
1838 12:41:01.278014 Final RX Vref Byte 1 = 61 to rank0
1839 12:41:01.281651 Final RX Vref Byte 0 = 50 to rank1
1840 12:41:01.285167 Final RX Vref Byte 1 = 61 to rank1==
1841 12:41:01.288276 Dram Type= 6, Freq= 0, CH_1, rank 0
1842 12:41:01.294858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1843 12:41:01.295426 ==
1844 12:41:01.295794 DQS Delay:
1845 12:41:01.296135 DQS0 = 0, DQS1 = 0
1846 12:41:01.298278 DQM Delay:
1847 12:41:01.298738 DQM0 = 92, DQM1 = 82
1848 12:41:01.301650 DQ Delay:
1849 12:41:01.304771 DQ0 =96, DQ1 =84, DQ2 =84, DQ3 =88
1850 12:41:01.308015 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =88
1851 12:41:01.311359 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =80
1852 12:41:01.315144 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1853 12:41:01.315707
1854 12:41:01.316076
1855 12:41:01.321726 [DQSOSCAuto] RK0, (LSB)MR18= 0x3451, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
1856 12:41:01.324682 CH1 RK0: MR19=606, MR18=3451
1857 12:41:01.331487 CH1_RK0: MR19=0x606, MR18=0x3451, DQSOSC=389, MR23=63, INC=97, DEC=65
1858 12:41:01.332065
1859 12:41:01.335077 ----->DramcWriteLeveling(PI) begin...
1860 12:41:01.335701 ==
1861 12:41:01.337923 Dram Type= 6, Freq= 0, CH_1, rank 1
1862 12:41:01.341604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1863 12:41:01.342077 ==
1864 12:41:01.344429 Write leveling (Byte 0): 26 => 26
1865 12:41:01.348233 Write leveling (Byte 1): 28 => 28
1866 12:41:01.351261 DramcWriteLeveling(PI) end<-----
1867 12:41:01.351826
1868 12:41:01.352196 ==
1869 12:41:01.354478 Dram Type= 6, Freq= 0, CH_1, rank 1
1870 12:41:01.358149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1871 12:41:01.358722 ==
1872 12:41:01.361669 [Gating] SW mode calibration
1873 12:41:01.367935 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1874 12:41:01.374845 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1875 12:41:01.378125 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1876 12:41:01.381425 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1877 12:41:01.388049 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1878 12:41:01.391504 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 12:41:01.395354 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 12:41:01.401358 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 12:41:01.404894 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 12:41:01.408052 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 12:41:01.414771 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 12:41:01.417801 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 12:41:01.421297 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 12:41:01.428220 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 12:41:01.431732 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 12:41:01.435074 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 12:41:01.441310 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 12:41:01.444601 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 12:41:01.447919 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1892 12:41:01.454580 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1893 12:41:01.457711 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1894 12:41:01.461116 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 12:41:01.467503 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 12:41:01.470768 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 12:41:01.474122 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 12:41:01.480892 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 12:41:01.484333 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 12:41:01.487777 0 9 4 | B1->B0 | 2827 2424 | 1 0 | (0 0) (0 0)
1901 12:41:01.494380 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1902 12:41:01.497768 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 12:41:01.500927 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1904 12:41:01.507618 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1905 12:41:01.511032 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1906 12:41:01.513872 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1907 12:41:01.517573 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1908 12:41:01.524533 0 10 4 | B1->B0 | 2d2d 2f2f | 1 0 | (1 0) (0 0)
1909 12:41:01.527557 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 12:41:01.530816 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 12:41:01.537334 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 12:41:01.540759 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 12:41:01.544165 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 12:41:01.550369 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 12:41:01.553766 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 12:41:01.556945 0 11 4 | B1->B0 | 3535 3333 | 0 0 | (1 1) (0 0)
1917 12:41:01.563503 0 11 8 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1918 12:41:01.566842 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 12:41:01.570035 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 12:41:01.576577 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1921 12:41:01.580090 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1922 12:41:01.583605 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1923 12:41:01.589977 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 12:41:01.593206 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1925 12:41:01.596757 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1926 12:41:01.602806 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 12:41:01.606388 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 12:41:01.609668 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 12:41:01.616443 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 12:41:01.619635 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 12:41:01.622731 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 12:41:01.629440 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 12:41:01.633225 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 12:41:01.636302 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 12:41:01.642766 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 12:41:01.646155 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 12:41:01.649607 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 12:41:01.656638 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 12:41:01.659561 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 12:41:01.662821 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1941 12:41:01.669806 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1942 12:41:01.670135 Total UI for P1: 0, mck2ui 16
1943 12:41:01.672652 best dqsien dly found for B1: ( 0, 14, 4)
1944 12:41:01.679828 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1945 12:41:01.682975 Total UI for P1: 0, mck2ui 16
1946 12:41:01.686324 best dqsien dly found for B0: ( 0, 14, 6)
1947 12:41:01.689743 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1948 12:41:01.693128 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1949 12:41:01.693513
1950 12:41:01.696698 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1951 12:41:01.699446 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1952 12:41:01.702882 [Gating] SW calibration Done
1953 12:41:01.703329 ==
1954 12:41:01.706310 Dram Type= 6, Freq= 0, CH_1, rank 1
1955 12:41:01.709802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1956 12:41:01.710256 ==
1957 12:41:01.712608 RX Vref Scan: 0
1958 12:41:01.713067
1959 12:41:01.716568 RX Vref 0 -> 0, step: 1
1960 12:41:01.717042
1961 12:41:01.717428 RX Delay -130 -> 252, step: 16
1962 12:41:01.722923 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1963 12:41:01.726236 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1964 12:41:01.729313 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1965 12:41:01.732668 iDelay=206, Bit 3, Center 85 (-18 ~ 189) 208
1966 12:41:01.736275 iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208
1967 12:41:01.742539 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1968 12:41:01.745838 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1969 12:41:01.749332 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1970 12:41:01.752580 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1971 12:41:01.755831 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1972 12:41:01.762393 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1973 12:41:01.766282 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1974 12:41:01.769759 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1975 12:41:01.772680 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1976 12:41:01.776227 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1977 12:41:01.782552 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1978 12:41:01.782648 ==
1979 12:41:01.785762 Dram Type= 6, Freq= 0, CH_1, rank 1
1980 12:41:01.789166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1981 12:41:01.789250 ==
1982 12:41:01.789316 DQS Delay:
1983 12:41:01.792214 DQS0 = 0, DQS1 = 0
1984 12:41:01.792297 DQM Delay:
1985 12:41:01.795838 DQM0 = 88, DQM1 = 82
1986 12:41:01.795920 DQ Delay:
1987 12:41:01.798815 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1988 12:41:01.802590 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1989 12:41:01.805506 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1990 12:41:01.808902 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1991 12:41:01.808994
1992 12:41:01.809073
1993 12:41:01.809162 ==
1994 12:41:01.811924 Dram Type= 6, Freq= 0, CH_1, rank 1
1995 12:41:01.815873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1996 12:41:01.818584 ==
1997 12:41:01.818667
1998 12:41:01.818732
1999 12:41:01.818791 TX Vref Scan disable
2000 12:41:01.822023 == TX Byte 0 ==
2001 12:41:01.825400 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2002 12:41:01.828686 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2003 12:41:01.831888 == TX Byte 1 ==
2004 12:41:01.835335 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2005 12:41:01.838777 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2006 12:41:01.842132 ==
2007 12:41:01.845251 Dram Type= 6, Freq= 0, CH_1, rank 1
2008 12:41:01.848463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2009 12:41:01.848559 ==
2010 12:41:01.860779 TX Vref=22, minBit 13, minWin=27, winSum=453
2011 12:41:01.864032 TX Vref=24, minBit 15, minWin=27, winSum=456
2012 12:41:01.867703 TX Vref=26, minBit 3, minWin=28, winSum=457
2013 12:41:01.871204 TX Vref=28, minBit 8, minWin=28, winSum=457
2014 12:41:01.874149 TX Vref=30, minBit 8, minWin=28, winSum=460
2015 12:41:01.880770 TX Vref=32, minBit 8, minWin=28, winSum=459
2016 12:41:01.884527 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 30
2017 12:41:01.884721
2018 12:41:01.887475 Final TX Range 1 Vref 30
2019 12:41:01.887681
2020 12:41:01.887792 ==
2021 12:41:01.890805 Dram Type= 6, Freq= 0, CH_1, rank 1
2022 12:41:01.894452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2023 12:41:01.897483 ==
2024 12:41:01.897724
2025 12:41:01.897861
2026 12:41:01.897982 TX Vref Scan disable
2027 12:41:01.901302 == TX Byte 0 ==
2028 12:41:01.904497 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2029 12:41:01.907872 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2030 12:41:01.910938 == TX Byte 1 ==
2031 12:41:01.914330 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2032 12:41:01.921066 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2033 12:41:01.921464
2034 12:41:01.921775 [DATLAT]
2035 12:41:01.922069 Freq=800, CH1 RK1
2036 12:41:01.922352
2037 12:41:01.924158 DATLAT Default: 0xa
2038 12:41:01.924548 0, 0xFFFF, sum = 0
2039 12:41:01.927434 1, 0xFFFF, sum = 0
2040 12:41:01.927519 2, 0xFFFF, sum = 0
2041 12:41:01.930948 3, 0xFFFF, sum = 0
2042 12:41:01.934313 4, 0xFFFF, sum = 0
2043 12:41:01.934397 5, 0xFFFF, sum = 0
2044 12:41:01.937308 6, 0xFFFF, sum = 0
2045 12:41:01.937391 7, 0xFFFF, sum = 0
2046 12:41:01.940867 8, 0xFFFF, sum = 0
2047 12:41:01.940951 9, 0x0, sum = 1
2048 12:41:01.941059 10, 0x0, sum = 2
2049 12:41:01.943794 11, 0x0, sum = 3
2050 12:41:01.943878 12, 0x0, sum = 4
2051 12:41:01.947340 best_step = 10
2052 12:41:01.947423
2053 12:41:01.947488 ==
2054 12:41:01.950549 Dram Type= 6, Freq= 0, CH_1, rank 1
2055 12:41:01.954013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2056 12:41:01.954096 ==
2057 12:41:01.957211 RX Vref Scan: 0
2058 12:41:01.957294
2059 12:41:01.957358 RX Vref 0 -> 0, step: 1
2060 12:41:01.957419
2061 12:41:01.960580 RX Delay -95 -> 252, step: 8
2062 12:41:01.967308 iDelay=209, Bit 0, Center 92 (-7 ~ 192) 200
2063 12:41:01.970811 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
2064 12:41:01.973879 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2065 12:41:01.977972 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2066 12:41:01.981171 iDelay=209, Bit 4, Center 96 (-7 ~ 200) 208
2067 12:41:01.987499 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2068 12:41:01.990793 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2069 12:41:01.994206 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2070 12:41:01.997733 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2071 12:41:02.001136 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2072 12:41:02.007430 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2073 12:41:02.011315 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2074 12:41:02.014560 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2075 12:41:02.017785 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2076 12:41:02.021089 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2077 12:41:02.027548 iDelay=209, Bit 15, Center 92 (-23 ~ 208) 232
2078 12:41:02.027780 ==
2079 12:41:02.031189 Dram Type= 6, Freq= 0, CH_1, rank 1
2080 12:41:02.034060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2081 12:41:02.034238 ==
2082 12:41:02.034378 DQS Delay:
2083 12:41:02.037502 DQS0 = 0, DQS1 = 0
2084 12:41:02.037585 DQM Delay:
2085 12:41:02.040776 DQM0 = 90, DQM1 = 83
2086 12:41:02.040860 DQ Delay:
2087 12:41:02.043933 DQ0 =92, DQ1 =84, DQ2 =80, DQ3 =88
2088 12:41:02.047042 DQ4 =96, DQ5 =100, DQ6 =96, DQ7 =88
2089 12:41:02.050610 DQ8 =68, DQ9 =72, DQ10 =84, DQ11 =80
2090 12:41:02.053616 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =92
2091 12:41:02.053698
2092 12:41:02.053764
2093 12:41:02.064204 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a0f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
2094 12:41:02.064288 CH1 RK1: MR19=606, MR18=3A0F
2095 12:41:02.070498 CH1_RK1: MR19=0x606, MR18=0x3A0F, DQSOSC=395, MR23=63, INC=94, DEC=63
2096 12:41:02.073801 [RxdqsGatingPostProcess] freq 800
2097 12:41:02.080772 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2098 12:41:02.084175 Pre-setting of DQS Precalculation
2099 12:41:02.087014 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2100 12:41:02.093875 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2101 12:41:02.100521 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2102 12:41:02.103888
2103 12:41:02.103969
2104 12:41:02.104034 [Calibration Summary] 1600 Mbps
2105 12:41:02.107089 CH 0, Rank 0
2106 12:41:02.107171 SW Impedance : PASS
2107 12:41:02.110301 DUTY Scan : NO K
2108 12:41:02.113616 ZQ Calibration : PASS
2109 12:41:02.113698 Jitter Meter : NO K
2110 12:41:02.116727 CBT Training : PASS
2111 12:41:02.120167 Write leveling : PASS
2112 12:41:02.120278 RX DQS gating : PASS
2113 12:41:02.123870 RX DQ/DQS(RDDQC) : PASS
2114 12:41:02.127047 TX DQ/DQS : PASS
2115 12:41:02.127159 RX DATLAT : PASS
2116 12:41:02.130617 RX DQ/DQS(Engine): PASS
2117 12:41:02.133433 TX OE : NO K
2118 12:41:02.133545 All Pass.
2119 12:41:02.133640
2120 12:41:02.133738 CH 0, Rank 1
2121 12:41:02.137077 SW Impedance : PASS
2122 12:41:02.140393 DUTY Scan : NO K
2123 12:41:02.140505 ZQ Calibration : PASS
2124 12:41:02.143355 Jitter Meter : NO K
2125 12:41:02.146767 CBT Training : PASS
2126 12:41:02.146849 Write leveling : PASS
2127 12:41:02.150160 RX DQS gating : PASS
2128 12:41:02.150243 RX DQ/DQS(RDDQC) : PASS
2129 12:41:02.153490 TX DQ/DQS : PASS
2130 12:41:02.156936 RX DATLAT : PASS
2131 12:41:02.157054 RX DQ/DQS(Engine): PASS
2132 12:41:02.160295 TX OE : NO K
2133 12:41:02.160377 All Pass.
2134 12:41:02.160460
2135 12:41:02.163778 CH 1, Rank 0
2136 12:41:02.163860 SW Impedance : PASS
2137 12:41:02.166683 DUTY Scan : NO K
2138 12:41:02.169946 ZQ Calibration : PASS
2139 12:41:02.170028 Jitter Meter : NO K
2140 12:41:02.173214 CBT Training : PASS
2141 12:41:02.176715 Write leveling : PASS
2142 12:41:02.176798 RX DQS gating : PASS
2143 12:41:02.179973 RX DQ/DQS(RDDQC) : PASS
2144 12:41:02.183202 TX DQ/DQS : PASS
2145 12:41:02.183292 RX DATLAT : PASS
2146 12:41:02.186560 RX DQ/DQS(Engine): PASS
2147 12:41:02.189734 TX OE : NO K
2148 12:41:02.189841 All Pass.
2149 12:41:02.189911
2150 12:41:02.189979 CH 1, Rank 1
2151 12:41:02.193258 SW Impedance : PASS
2152 12:41:02.196557 DUTY Scan : NO K
2153 12:41:02.196663 ZQ Calibration : PASS
2154 12:41:02.200099 Jitter Meter : NO K
2155 12:41:02.203086 CBT Training : PASS
2156 12:41:02.203203 Write leveling : PASS
2157 12:41:02.206387 RX DQS gating : PASS
2158 12:41:02.206492 RX DQ/DQS(RDDQC) : PASS
2159 12:41:02.209970 TX DQ/DQS : PASS
2160 12:41:02.213288 RX DATLAT : PASS
2161 12:41:02.213412 RX DQ/DQS(Engine): PASS
2162 12:41:02.216569 TX OE : NO K
2163 12:41:02.216652 All Pass.
2164 12:41:02.216718
2165 12:41:02.219780 DramC Write-DBI off
2166 12:41:02.223213 PER_BANK_REFRESH: Hybrid Mode
2167 12:41:02.223295 TX_TRACKING: ON
2168 12:41:02.226544 [GetDramInforAfterCalByMRR] Vendor 6.
2169 12:41:02.229714 [GetDramInforAfterCalByMRR] Revision 606.
2170 12:41:02.232969 [GetDramInforAfterCalByMRR] Revision 2 0.
2171 12:41:02.236660 MR0 0x3b3b
2172 12:41:02.236743 MR8 0x5151
2173 12:41:02.240007 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2174 12:41:02.240090
2175 12:41:02.243130 MR0 0x3b3b
2176 12:41:02.243213 MR8 0x5151
2177 12:41:02.246561 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2178 12:41:02.246650
2179 12:41:02.256063 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2180 12:41:02.259462 [FAST_K] Save calibration result to emmc
2181 12:41:02.262837 [FAST_K] Save calibration result to emmc
2182 12:41:02.266325 dram_init: config_dvfs: 1
2183 12:41:02.269903 dramc_set_vcore_voltage set vcore to 662500
2184 12:41:02.270008 Read voltage for 1200, 2
2185 12:41:02.272628 Vio18 = 0
2186 12:41:02.272786 Vcore = 662500
2187 12:41:02.272932 Vdram = 0
2188 12:41:02.276069 Vddq = 0
2189 12:41:02.276223 Vmddr = 0
2190 12:41:02.279445 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2191 12:41:02.286193 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2192 12:41:02.289315 MEM_TYPE=3, freq_sel=15
2193 12:41:02.292996 sv_algorithm_assistance_LP4_1600
2194 12:41:02.296657 ============ PULL DRAM RESETB DOWN ============
2195 12:41:02.299645 ========== PULL DRAM RESETB DOWN end =========
2196 12:41:02.306190 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2197 12:41:02.309791 ===================================
2198 12:41:02.310302 LPDDR4 DRAM CONFIGURATION
2199 12:41:02.312659 ===================================
2200 12:41:02.316153 EX_ROW_EN[0] = 0x0
2201 12:41:02.316626 EX_ROW_EN[1] = 0x0
2202 12:41:02.319966 LP4Y_EN = 0x0
2203 12:41:02.320397 WORK_FSP = 0x0
2204 12:41:02.322979 WL = 0x4
2205 12:41:02.326249 RL = 0x4
2206 12:41:02.326680 BL = 0x2
2207 12:41:02.329277 RPST = 0x0
2208 12:41:02.329709 RD_PRE = 0x0
2209 12:41:02.332549 WR_PRE = 0x1
2210 12:41:02.333005 WR_PST = 0x0
2211 12:41:02.335949 DBI_WR = 0x0
2212 12:41:02.336387 DBI_RD = 0x0
2213 12:41:02.339264 OTF = 0x1
2214 12:41:02.343164 ===================================
2215 12:41:02.346135 ===================================
2216 12:41:02.346562 ANA top config
2217 12:41:02.349398 ===================================
2218 12:41:02.352763 DLL_ASYNC_EN = 0
2219 12:41:02.356196 ALL_SLAVE_EN = 0
2220 12:41:02.356843 NEW_RANK_MODE = 1
2221 12:41:02.359560 DLL_IDLE_MODE = 1
2222 12:41:02.362353 LP45_APHY_COMB_EN = 1
2223 12:41:02.365618 TX_ODT_DIS = 1
2224 12:41:02.369140 NEW_8X_MODE = 1
2225 12:41:02.369255 ===================================
2226 12:41:02.372269 ===================================
2227 12:41:02.375598 data_rate = 2400
2228 12:41:02.378983 CKR = 1
2229 12:41:02.382404 DQ_P2S_RATIO = 8
2230 12:41:02.385574 ===================================
2231 12:41:02.389278 CA_P2S_RATIO = 8
2232 12:41:02.392127 DQ_CA_OPEN = 0
2233 12:41:02.395825 DQ_SEMI_OPEN = 0
2234 12:41:02.395925 CA_SEMI_OPEN = 0
2235 12:41:02.398920 CA_FULL_RATE = 0
2236 12:41:02.402329 DQ_CKDIV4_EN = 0
2237 12:41:02.405846 CA_CKDIV4_EN = 0
2238 12:41:02.409164 CA_PREDIV_EN = 0
2239 12:41:02.412456 PH8_DLY = 17
2240 12:41:02.412637 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2241 12:41:02.415636 DQ_AAMCK_DIV = 4
2242 12:41:02.418933 CA_AAMCK_DIV = 4
2243 12:41:02.422653 CA_ADMCK_DIV = 4
2244 12:41:02.425938 DQ_TRACK_CA_EN = 0
2245 12:41:02.428933 CA_PICK = 1200
2246 12:41:02.429224 CA_MCKIO = 1200
2247 12:41:02.432465 MCKIO_SEMI = 0
2248 12:41:02.435767 PLL_FREQ = 2366
2249 12:41:02.439012 DQ_UI_PI_RATIO = 32
2250 12:41:02.442666 CA_UI_PI_RATIO = 0
2251 12:41:02.445539 ===================================
2252 12:41:02.448634 ===================================
2253 12:41:02.452107 memory_type:LPDDR4
2254 12:41:02.452192 GP_NUM : 10
2255 12:41:02.455306 SRAM_EN : 1
2256 12:41:02.458741 MD32_EN : 0
2257 12:41:02.458838 ===================================
2258 12:41:02.461924 [ANA_INIT] >>>>>>>>>>>>>>
2259 12:41:02.465443 <<<<<< [CONFIGURE PHASE]: ANA_TX
2260 12:41:02.468903 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2261 12:41:02.472428 ===================================
2262 12:41:02.475577 data_rate = 2400,PCW = 0X5b00
2263 12:41:02.478887 ===================================
2264 12:41:02.481992 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2265 12:41:02.488725 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2266 12:41:02.492246 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2267 12:41:02.498452 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2268 12:41:02.501982 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2269 12:41:02.504951 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2270 12:41:02.505155 [ANA_INIT] flow start
2271 12:41:02.508493 [ANA_INIT] PLL >>>>>>>>
2272 12:41:02.511618 [ANA_INIT] PLL <<<<<<<<
2273 12:41:02.511774 [ANA_INIT] MIDPI >>>>>>>>
2274 12:41:02.515024 [ANA_INIT] MIDPI <<<<<<<<
2275 12:41:02.518571 [ANA_INIT] DLL >>>>>>>>
2276 12:41:02.518738 [ANA_INIT] DLL <<<<<<<<
2277 12:41:02.522031 [ANA_INIT] flow end
2278 12:41:02.525040 ============ LP4 DIFF to SE enter ============
2279 12:41:02.531536 ============ LP4 DIFF to SE exit ============
2280 12:41:02.531719 [ANA_INIT] <<<<<<<<<<<<<
2281 12:41:02.535198 [Flow] Enable top DCM control >>>>>
2282 12:41:02.538483 [Flow] Enable top DCM control <<<<<
2283 12:41:02.541775 Enable DLL master slave shuffle
2284 12:41:02.548665 ==============================================================
2285 12:41:02.548840 Gating Mode config
2286 12:41:02.555304 ==============================================================
2287 12:41:02.558149 Config description:
2288 12:41:02.565373 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2289 12:41:02.571530 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2290 12:41:02.578561 SELPH_MODE 0: By rank 1: By Phase
2291 12:41:02.584895 ==============================================================
2292 12:41:02.585260 GAT_TRACK_EN = 1
2293 12:41:02.588147 RX_GATING_MODE = 2
2294 12:41:02.591648 RX_GATING_TRACK_MODE = 2
2295 12:41:02.595088 SELPH_MODE = 1
2296 12:41:02.598300 PICG_EARLY_EN = 1
2297 12:41:02.601467 VALID_LAT_VALUE = 1
2298 12:41:02.608130 ==============================================================
2299 12:41:02.611468 Enter into Gating configuration >>>>
2300 12:41:02.614824 Exit from Gating configuration <<<<
2301 12:41:02.618121 Enter into DVFS_PRE_config >>>>>
2302 12:41:02.628426 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2303 12:41:02.631600 Exit from DVFS_PRE_config <<<<<
2304 12:41:02.635052 Enter into PICG configuration >>>>
2305 12:41:02.638074 Exit from PICG configuration <<<<
2306 12:41:02.641473 [RX_INPUT] configuration >>>>>
2307 12:41:02.641775 [RX_INPUT] configuration <<<<<
2308 12:41:02.648194 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2309 12:41:02.654644 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2310 12:41:02.661230 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2311 12:41:02.664772 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2312 12:41:02.671244 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2313 12:41:02.677934 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2314 12:41:02.681178 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2315 12:41:02.684372 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2316 12:41:02.690965 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2317 12:41:02.694417 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2318 12:41:02.698100 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2319 12:41:02.704390 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2320 12:41:02.707710 ===================================
2321 12:41:02.708106 LPDDR4 DRAM CONFIGURATION
2322 12:41:02.711061 ===================================
2323 12:41:02.714278 EX_ROW_EN[0] = 0x0
2324 12:41:02.717561 EX_ROW_EN[1] = 0x0
2325 12:41:02.717865 LP4Y_EN = 0x0
2326 12:41:02.720779 WORK_FSP = 0x0
2327 12:41:02.721102 WL = 0x4
2328 12:41:02.724153 RL = 0x4
2329 12:41:02.724455 BL = 0x2
2330 12:41:02.727583 RPST = 0x0
2331 12:41:02.727886 RD_PRE = 0x0
2332 12:41:02.731064 WR_PRE = 0x1
2333 12:41:02.731366 WR_PST = 0x0
2334 12:41:02.734389 DBI_WR = 0x0
2335 12:41:02.734714 DBI_RD = 0x0
2336 12:41:02.737511 OTF = 0x1
2337 12:41:02.741128 ===================================
2338 12:41:02.744287 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2339 12:41:02.748032 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2340 12:41:02.753917 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2341 12:41:02.757452 ===================================
2342 12:41:02.757761 LPDDR4 DRAM CONFIGURATION
2343 12:41:02.760701 ===================================
2344 12:41:02.764244 EX_ROW_EN[0] = 0x10
2345 12:41:02.764611 EX_ROW_EN[1] = 0x0
2346 12:41:02.767417 LP4Y_EN = 0x0
2347 12:41:02.767811 WORK_FSP = 0x0
2348 12:41:02.770761 WL = 0x4
2349 12:41:02.774188 RL = 0x4
2350 12:41:02.774561 BL = 0x2
2351 12:41:02.777713 RPST = 0x0
2352 12:41:02.778081 RD_PRE = 0x0
2353 12:41:02.780863 WR_PRE = 0x1
2354 12:41:02.781297 WR_PST = 0x0
2355 12:41:02.783964 DBI_WR = 0x0
2356 12:41:02.784339 DBI_RD = 0x0
2357 12:41:02.787080 OTF = 0x1
2358 12:41:02.790829 ===================================
2359 12:41:02.797173 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2360 12:41:02.797467 ==
2361 12:41:02.800325 Dram Type= 6, Freq= 0, CH_0, rank 0
2362 12:41:02.804066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2363 12:41:02.804360 ==
2364 12:41:02.807117 [Duty_Offset_Calibration]
2365 12:41:02.807527 B0:2 B1:0 CA:1
2366 12:41:02.807867
2367 12:41:02.810199 [DutyScan_Calibration_Flow] k_type=0
2368 12:41:02.819467
2369 12:41:02.819758 ==CLK 0==
2370 12:41:02.822671 Final CLK duty delay cell = -4
2371 12:41:02.825911 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2372 12:41:02.829368 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2373 12:41:02.833048 [-4] AVG Duty = 4953%(X100)
2374 12:41:02.833341
2375 12:41:02.836028 CH0 CLK Duty spec in!! Max-Min= 156%
2376 12:41:02.839311 [DutyScan_Calibration_Flow] ====Done====
2377 12:41:02.839605
2378 12:41:02.842599 [DutyScan_Calibration_Flow] k_type=1
2379 12:41:02.858383
2380 12:41:02.858673 ==DQS 0 ==
2381 12:41:02.861738 Final DQS duty delay cell = 0
2382 12:41:02.865269 [0] MAX Duty = 5187%(X100), DQS PI = 30
2383 12:41:02.868592 [0] MIN Duty = 4938%(X100), DQS PI = 0
2384 12:41:02.868973 [0] AVG Duty = 5062%(X100)
2385 12:41:02.872137
2386 12:41:02.872687 ==DQS 1 ==
2387 12:41:02.875235 Final DQS duty delay cell = -4
2388 12:41:02.878481 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2389 12:41:02.881685 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2390 12:41:02.885197 [-4] AVG Duty = 5031%(X100)
2391 12:41:02.885837
2392 12:41:02.888596 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2393 12:41:02.889275
2394 12:41:02.891730 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2395 12:41:02.894973 [DutyScan_Calibration_Flow] ====Done====
2396 12:41:02.895563
2397 12:41:02.898249 [DutyScan_Calibration_Flow] k_type=3
2398 12:41:02.914659
2399 12:41:02.915156 ==DQM 0 ==
2400 12:41:02.917736 Final DQM duty delay cell = 0
2401 12:41:02.920808 [0] MAX Duty = 5062%(X100), DQS PI = 24
2402 12:41:02.924578 [0] MIN Duty = 4875%(X100), DQS PI = 0
2403 12:41:02.927585 [0] AVG Duty = 4968%(X100)
2404 12:41:02.928006
2405 12:41:02.928333 ==DQM 1 ==
2406 12:41:02.931043 Final DQM duty delay cell = -4
2407 12:41:02.934581 [-4] MAX Duty = 5000%(X100), DQS PI = 32
2408 12:41:02.937545 [-4] MIN Duty = 4813%(X100), DQS PI = 12
2409 12:41:02.940819 [-4] AVG Duty = 4906%(X100)
2410 12:41:02.941264
2411 12:41:02.944673 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2412 12:41:02.945234
2413 12:41:02.947462 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2414 12:41:02.951025 [DutyScan_Calibration_Flow] ====Done====
2415 12:41:02.951439
2416 12:41:02.954421 [DutyScan_Calibration_Flow] k_type=2
2417 12:41:02.971457
2418 12:41:02.971977 ==DQ 0 ==
2419 12:41:02.974486 Final DQ duty delay cell = -4
2420 12:41:02.977927 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2421 12:41:02.981205 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2422 12:41:02.984457 [-4] AVG Duty = 4984%(X100)
2423 12:41:02.984868
2424 12:41:02.985282 ==DQ 1 ==
2425 12:41:02.987989 Final DQ duty delay cell = 4
2426 12:41:02.991199 [4] MAX Duty = 5093%(X100), DQS PI = 6
2427 12:41:02.994741 [4] MIN Duty = 5031%(X100), DQS PI = 2
2428 12:41:02.995154 [4] AVG Duty = 5062%(X100)
2429 12:41:02.998321
2430 12:41:03.001453 CH0 DQ 0 Duty spec in!! Max-Min= 155%
2431 12:41:03.001907
2432 12:41:03.004844 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2433 12:41:03.007936 [DutyScan_Calibration_Flow] ====Done====
2434 12:41:03.008393 ==
2435 12:41:03.011683 Dram Type= 6, Freq= 0, CH_1, rank 0
2436 12:41:03.014628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2437 12:41:03.015116 ==
2438 12:41:03.018038 [Duty_Offset_Calibration]
2439 12:41:03.018490 B0:0 B1:-1 CA:2
2440 12:41:03.018849
2441 12:41:03.021261 [DutyScan_Calibration_Flow] k_type=0
2442 12:41:03.031283
2443 12:41:03.031737 ==CLK 0==
2444 12:41:03.034645 Final CLK duty delay cell = 0
2445 12:41:03.038272 [0] MAX Duty = 5156%(X100), DQS PI = 14
2446 12:41:03.041508 [0] MIN Duty = 4938%(X100), DQS PI = 44
2447 12:41:03.041972 [0] AVG Duty = 5047%(X100)
2448 12:41:03.045049
2449 12:41:03.048158 CH1 CLK Duty spec in!! Max-Min= 218%
2450 12:41:03.051403 [DutyScan_Calibration_Flow] ====Done====
2451 12:41:03.051861
2452 12:41:03.055044 [DutyScan_Calibration_Flow] k_type=1
2453 12:41:03.071048
2454 12:41:03.071510 ==DQS 0 ==
2455 12:41:03.074077 Final DQS duty delay cell = 0
2456 12:41:03.077347 [0] MAX Duty = 5093%(X100), DQS PI = 22
2457 12:41:03.080561 [0] MIN Duty = 4969%(X100), DQS PI = 2
2458 12:41:03.084022 [0] AVG Duty = 5031%(X100)
2459 12:41:03.084563
2460 12:41:03.085025 ==DQS 1 ==
2461 12:41:03.087476 Final DQS duty delay cell = 0
2462 12:41:03.091131 [0] MAX Duty = 5156%(X100), DQS PI = 0
2463 12:41:03.094014 [0] MIN Duty = 4813%(X100), DQS PI = 36
2464 12:41:03.097506 [0] AVG Duty = 4984%(X100)
2465 12:41:03.097975
2466 12:41:03.101019 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2467 12:41:03.101492
2468 12:41:03.104333 CH1 DQS 1 Duty spec in!! Max-Min= 343%
2469 12:41:03.107390 [DutyScan_Calibration_Flow] ====Done====
2470 12:41:03.107863
2471 12:41:03.110577 [DutyScan_Calibration_Flow] k_type=3
2472 12:41:03.127497
2473 12:41:03.127962 ==DQM 0 ==
2474 12:41:03.130620 Final DQM duty delay cell = 4
2475 12:41:03.133789 [4] MAX Duty = 5093%(X100), DQS PI = 4
2476 12:41:03.137387 [4] MIN Duty = 4969%(X100), DQS PI = 28
2477 12:41:03.140823 [4] AVG Duty = 5031%(X100)
2478 12:41:03.141459
2479 12:41:03.141842 ==DQM 1 ==
2480 12:41:03.144154 Final DQM duty delay cell = -4
2481 12:41:03.147856 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2482 12:41:03.150527 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2483 12:41:03.154521 [-4] AVG Duty = 4875%(X100)
2484 12:41:03.155110
2485 12:41:03.157726 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2486 12:41:03.158200
2487 12:41:03.161089 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2488 12:41:03.164457 [DutyScan_Calibration_Flow] ====Done====
2489 12:41:03.165089
2490 12:41:03.167867 [DutyScan_Calibration_Flow] k_type=2
2491 12:41:03.184202
2492 12:41:03.184775 ==DQ 0 ==
2493 12:41:03.187683 Final DQ duty delay cell = 0
2494 12:41:03.190878 [0] MAX Duty = 5062%(X100), DQS PI = 16
2495 12:41:03.194657 [0] MIN Duty = 4938%(X100), DQS PI = 44
2496 12:41:03.195226 [0] AVG Duty = 5000%(X100)
2497 12:41:03.197329
2498 12:41:03.197799 ==DQ 1 ==
2499 12:41:03.200783 Final DQ duty delay cell = 0
2500 12:41:03.204513 [0] MAX Duty = 5031%(X100), DQS PI = 2
2501 12:41:03.207206 [0] MIN Duty = 4813%(X100), DQS PI = 34
2502 12:41:03.207678 [0] AVG Duty = 4922%(X100)
2503 12:41:03.208048
2504 12:41:03.214210 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2505 12:41:03.214778
2506 12:41:03.217343 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2507 12:41:03.220917 [DutyScan_Calibration_Flow] ====Done====
2508 12:41:03.224145 nWR fixed to 30
2509 12:41:03.224708 [ModeRegInit_LP4] CH0 RK0
2510 12:41:03.227480 [ModeRegInit_LP4] CH0 RK1
2511 12:41:03.230877 [ModeRegInit_LP4] CH1 RK0
2512 12:41:03.234408 [ModeRegInit_LP4] CH1 RK1
2513 12:41:03.234973 match AC timing 7
2514 12:41:03.237428 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2515 12:41:03.243881 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2516 12:41:03.247462 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2517 12:41:03.253869 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2518 12:41:03.257346 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2519 12:41:03.257919 ==
2520 12:41:03.260607 Dram Type= 6, Freq= 0, CH_0, rank 0
2521 12:41:03.264169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2522 12:41:03.264735 ==
2523 12:41:03.270813 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2524 12:41:03.277332 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2525 12:41:03.284240 [CA 0] Center 38 (8~69) winsize 62
2526 12:41:03.287564 [CA 1] Center 38 (7~69) winsize 63
2527 12:41:03.291204 [CA 2] Center 35 (5~66) winsize 62
2528 12:41:03.294122 [CA 3] Center 35 (4~66) winsize 63
2529 12:41:03.297618 [CA 4] Center 34 (4~65) winsize 62
2530 12:41:03.301044 [CA 5] Center 33 (3~63) winsize 61
2531 12:41:03.301619
2532 12:41:03.304062 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2533 12:41:03.304547
2534 12:41:03.307809 [CATrainingPosCal] consider 1 rank data
2535 12:41:03.310955 u2DelayCellTimex100 = 270/100 ps
2536 12:41:03.314197 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2537 12:41:03.317230 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2538 12:41:03.324177 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2539 12:41:03.327535 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2540 12:41:03.331016 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2541 12:41:03.334224 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2542 12:41:03.334798
2543 12:41:03.337544 CA PerBit enable=1, Macro0, CA PI delay=33
2544 12:41:03.338040
2545 12:41:03.341343 [CBTSetCACLKResult] CA Dly = 33
2546 12:41:03.341915 CS Dly: 6 (0~37)
2547 12:41:03.344210 ==
2548 12:41:03.347023 Dram Type= 6, Freq= 0, CH_0, rank 1
2549 12:41:03.350286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2550 12:41:03.350766 ==
2551 12:41:03.354246 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2552 12:41:03.360593 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2553 12:41:03.370114 [CA 0] Center 39 (8~70) winsize 63
2554 12:41:03.372957 [CA 1] Center 38 (8~69) winsize 62
2555 12:41:03.376724 [CA 2] Center 35 (5~66) winsize 62
2556 12:41:03.379830 [CA 3] Center 35 (5~66) winsize 62
2557 12:41:03.382764 [CA 4] Center 34 (4~65) winsize 62
2558 12:41:03.386255 [CA 5] Center 34 (4~64) winsize 61
2559 12:41:03.386839
2560 12:41:03.389351 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2561 12:41:03.389826
2562 12:41:03.392872 [CATrainingPosCal] consider 2 rank data
2563 12:41:03.396333 u2DelayCellTimex100 = 270/100 ps
2564 12:41:03.399475 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2565 12:41:03.405865 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2566 12:41:03.409285 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2567 12:41:03.412568 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2568 12:41:03.416098 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2569 12:41:03.419754 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2570 12:41:03.420318
2571 12:41:03.422523 CA PerBit enable=1, Macro0, CA PI delay=33
2572 12:41:03.423094
2573 12:41:03.426315 [CBTSetCACLKResult] CA Dly = 33
2574 12:41:03.429572 CS Dly: 7 (0~39)
2575 12:41:03.430134
2576 12:41:03.432840 ----->DramcWriteLeveling(PI) begin...
2577 12:41:03.433443 ==
2578 12:41:03.436029 Dram Type= 6, Freq= 0, CH_0, rank 0
2579 12:41:03.439111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2580 12:41:03.439681 ==
2581 12:41:03.442535 Write leveling (Byte 0): 34 => 34
2582 12:41:03.445917 Write leveling (Byte 1): 31 => 31
2583 12:41:03.449377 DramcWriteLeveling(PI) end<-----
2584 12:41:03.449974
2585 12:41:03.450348 ==
2586 12:41:03.452546 Dram Type= 6, Freq= 0, CH_0, rank 0
2587 12:41:03.455726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2588 12:41:03.456206 ==
2589 12:41:03.458924 [Gating] SW mode calibration
2590 12:41:03.465712 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2591 12:41:03.472148 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2592 12:41:03.475366 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2593 12:41:03.478816 0 15 4 | B1->B0 | 2b2b 3434 | 1 1 | (0 0) (1 1)
2594 12:41:03.485160 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2595 12:41:03.488751 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2596 12:41:03.492408 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2597 12:41:03.498612 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2598 12:41:03.501914 0 15 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
2599 12:41:03.505328 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
2600 12:41:03.511736 1 0 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (1 0)
2601 12:41:03.515231 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2602 12:41:03.518140 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2603 12:41:03.525209 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2604 12:41:03.528668 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2605 12:41:03.531930 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2606 12:41:03.538541 1 0 24 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
2607 12:41:03.541304 1 0 28 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
2608 12:41:03.544683 1 1 0 | B1->B0 | 2b2b 4646 | 1 0 | (0 0) (0 0)
2609 12:41:03.551205 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 12:41:03.554710 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2611 12:41:03.557897 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2612 12:41:03.564638 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2613 12:41:03.567503 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2614 12:41:03.571100 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2615 12:41:03.577617 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2616 12:41:03.581062 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2617 12:41:03.584285 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2618 12:41:03.590987 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 12:41:03.594371 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 12:41:03.597884 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 12:41:03.603933 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 12:41:03.607597 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 12:41:03.610882 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 12:41:03.617201 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 12:41:03.620937 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 12:41:03.624166 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 12:41:03.631099 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 12:41:03.634109 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 12:41:03.637441 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 12:41:03.644557 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2631 12:41:03.647831 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2632 12:41:03.651350 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2633 12:41:03.654803 Total UI for P1: 0, mck2ui 16
2634 12:41:03.657430 best dqsien dly found for B0: ( 1, 3, 26)
2635 12:41:03.660861 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2636 12:41:03.664088 Total UI for P1: 0, mck2ui 16
2637 12:41:03.667447 best dqsien dly found for B1: ( 1, 4, 0)
2638 12:41:03.671051 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2639 12:41:03.674173 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2640 12:41:03.677613
2641 12:41:03.680896 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2642 12:41:03.684161 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2643 12:41:03.687705 [Gating] SW calibration Done
2644 12:41:03.688286 ==
2645 12:41:03.691215 Dram Type= 6, Freq= 0, CH_0, rank 0
2646 12:41:03.694472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2647 12:41:03.695052 ==
2648 12:41:03.695432 RX Vref Scan: 0
2649 12:41:03.695782
2650 12:41:03.697180 RX Vref 0 -> 0, step: 1
2651 12:41:03.697658
2652 12:41:03.700488 RX Delay -40 -> 252, step: 8
2653 12:41:03.703719 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2654 12:41:03.707251 iDelay=208, Bit 1, Center 119 (48 ~ 191) 144
2655 12:41:03.713676 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2656 12:41:03.717187 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2657 12:41:03.720200 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2658 12:41:03.723899 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2659 12:41:03.727171 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2660 12:41:03.733886 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2661 12:41:03.736902 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2662 12:41:03.740415 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2663 12:41:03.743603 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2664 12:41:03.747218 iDelay=208, Bit 11, Center 103 (40 ~ 167) 128
2665 12:41:03.753476 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2666 12:41:03.756756 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2667 12:41:03.760061 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2668 12:41:03.763549 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2669 12:41:03.763709 ==
2670 12:41:03.766790 Dram Type= 6, Freq= 0, CH_0, rank 0
2671 12:41:03.773045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2672 12:41:03.773207 ==
2673 12:41:03.773333 DQS Delay:
2674 12:41:03.773451 DQS0 = 0, DQS1 = 0
2675 12:41:03.777153 DQM Delay:
2676 12:41:03.777314 DQM0 = 122, DQM1 = 109
2677 12:41:03.780212 DQ Delay:
2678 12:41:03.783291 DQ0 =123, DQ1 =119, DQ2 =119, DQ3 =119
2679 12:41:03.786318 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2680 12:41:03.789683 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =103
2681 12:41:03.793036 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2682 12:41:03.793198
2683 12:41:03.793325
2684 12:41:03.793441 ==
2685 12:41:03.796585 Dram Type= 6, Freq= 0, CH_0, rank 0
2686 12:41:03.800418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2687 12:41:03.800580 ==
2688 12:41:03.803057
2689 12:41:03.803216
2690 12:41:03.803342 TX Vref Scan disable
2691 12:41:03.806419 == TX Byte 0 ==
2692 12:41:03.809507 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2693 12:41:03.812908 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2694 12:41:03.816133 == TX Byte 1 ==
2695 12:41:03.819394 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2696 12:41:03.823264 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2697 12:41:03.823426 ==
2698 12:41:03.826183 Dram Type= 6, Freq= 0, CH_0, rank 0
2699 12:41:03.832762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2700 12:41:03.832974 ==
2701 12:41:03.843839 TX Vref=22, minBit 1, minWin=23, winSum=401
2702 12:41:03.847245 TX Vref=24, minBit 0, minWin=24, winSum=411
2703 12:41:03.850279 TX Vref=26, minBit 1, minWin=24, winSum=415
2704 12:41:03.853663 TX Vref=28, minBit 1, minWin=24, winSum=418
2705 12:41:03.857537 TX Vref=30, minBit 0, minWin=25, winSum=416
2706 12:41:03.860163 TX Vref=32, minBit 7, minWin=24, winSum=416
2707 12:41:03.867267 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 30
2708 12:41:03.867351
2709 12:41:03.870156 Final TX Range 1 Vref 30
2710 12:41:03.870246
2711 12:41:03.870311 ==
2712 12:41:03.873515 Dram Type= 6, Freq= 0, CH_0, rank 0
2713 12:41:03.876989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2714 12:41:03.877085 ==
2715 12:41:03.880282
2716 12:41:03.880364
2717 12:41:03.880429 TX Vref Scan disable
2718 12:41:03.883523 == TX Byte 0 ==
2719 12:41:03.886739 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2720 12:41:03.890225 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2721 12:41:03.893585 == TX Byte 1 ==
2722 12:41:03.897141 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2723 12:41:03.899905 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2724 12:41:03.903418
2725 12:41:03.903525 [DATLAT]
2726 12:41:03.903619 Freq=1200, CH0 RK0
2727 12:41:03.903709
2728 12:41:03.906850 DATLAT Default: 0xd
2729 12:41:03.906927 0, 0xFFFF, sum = 0
2730 12:41:03.910434 1, 0xFFFF, sum = 0
2731 12:41:03.910509 2, 0xFFFF, sum = 0
2732 12:41:03.913354 3, 0xFFFF, sum = 0
2733 12:41:03.913444 4, 0xFFFF, sum = 0
2734 12:41:03.916965 5, 0xFFFF, sum = 0
2735 12:41:03.920163 6, 0xFFFF, sum = 0
2736 12:41:03.920290 7, 0xFFFF, sum = 0
2737 12:41:03.923393 8, 0xFFFF, sum = 0
2738 12:41:03.923540 9, 0xFFFF, sum = 0
2739 12:41:03.927291 10, 0xFFFF, sum = 0
2740 12:41:03.927441 11, 0xFFFF, sum = 0
2741 12:41:03.930145 12, 0x0, sum = 1
2742 12:41:03.930295 13, 0x0, sum = 2
2743 12:41:03.934042 14, 0x0, sum = 3
2744 12:41:03.934247 15, 0x0, sum = 4
2745 12:41:03.934357 best_step = 13
2746 12:41:03.934453
2747 12:41:03.936877 ==
2748 12:41:03.940256 Dram Type= 6, Freq= 0, CH_0, rank 0
2749 12:41:03.943424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2750 12:41:03.943578 ==
2751 12:41:03.943700 RX Vref Scan: 1
2752 12:41:03.943812
2753 12:41:03.947085 Set Vref Range= 32 -> 127
2754 12:41:03.947258
2755 12:41:03.950106 RX Vref 32 -> 127, step: 1
2756 12:41:03.950279
2757 12:41:03.953440 RX Delay -13 -> 252, step: 4
2758 12:41:03.953642
2759 12:41:03.957344 Set Vref, RX VrefLevel [Byte0]: 32
2760 12:41:03.960710 [Byte1]: 32
2761 12:41:03.961133
2762 12:41:03.964049 Set Vref, RX VrefLevel [Byte0]: 33
2763 12:41:03.967364 [Byte1]: 33
2764 12:41:03.967875
2765 12:41:03.970968 Set Vref, RX VrefLevel [Byte0]: 34
2766 12:41:03.973937 [Byte1]: 34
2767 12:41:03.978195
2768 12:41:03.978759 Set Vref, RX VrefLevel [Byte0]: 35
2769 12:41:03.982068 [Byte1]: 35
2770 12:41:03.986249
2771 12:41:03.986813 Set Vref, RX VrefLevel [Byte0]: 36
2772 12:41:03.989372 [Byte1]: 36
2773 12:41:03.994402
2774 12:41:03.994969 Set Vref, RX VrefLevel [Byte0]: 37
2775 12:41:03.997565 [Byte1]: 37
2776 12:41:04.001900
2777 12:41:04.002463 Set Vref, RX VrefLevel [Byte0]: 38
2778 12:41:04.005470 [Byte1]: 38
2779 12:41:04.009956
2780 12:41:04.010432 Set Vref, RX VrefLevel [Byte0]: 39
2781 12:41:04.013486 [Byte1]: 39
2782 12:41:04.017589
2783 12:41:04.018064 Set Vref, RX VrefLevel [Byte0]: 40
2784 12:41:04.021373 [Byte1]: 40
2785 12:41:04.025600
2786 12:41:04.026162 Set Vref, RX VrefLevel [Byte0]: 41
2787 12:41:04.029029 [Byte1]: 41
2788 12:41:04.033294
2789 12:41:04.033846 Set Vref, RX VrefLevel [Byte0]: 42
2790 12:41:04.036510 [Byte1]: 42
2791 12:41:04.041097
2792 12:41:04.041575 Set Vref, RX VrefLevel [Byte0]: 43
2793 12:41:04.044502 [Byte1]: 43
2794 12:41:04.049056
2795 12:41:04.049702 Set Vref, RX VrefLevel [Byte0]: 44
2796 12:41:04.052163 [Byte1]: 44
2797 12:41:04.057099
2798 12:41:04.057586 Set Vref, RX VrefLevel [Byte0]: 45
2799 12:41:04.060425 [Byte1]: 45
2800 12:41:04.065368
2801 12:41:04.065937 Set Vref, RX VrefLevel [Byte0]: 46
2802 12:41:04.068544 [Byte1]: 46
2803 12:41:04.072649
2804 12:41:04.073165 Set Vref, RX VrefLevel [Byte0]: 47
2805 12:41:04.076314 [Byte1]: 47
2806 12:41:04.080728
2807 12:41:04.081374 Set Vref, RX VrefLevel [Byte0]: 48
2808 12:41:04.084151 [Byte1]: 48
2809 12:41:04.089031
2810 12:41:04.089599 Set Vref, RX VrefLevel [Byte0]: 49
2811 12:41:04.092070 [Byte1]: 49
2812 12:41:04.096612
2813 12:41:04.097205 Set Vref, RX VrefLevel [Byte0]: 50
2814 12:41:04.099807 [Byte1]: 50
2815 12:41:04.104405
2816 12:41:04.104963 Set Vref, RX VrefLevel [Byte0]: 51
2817 12:41:04.107750 [Byte1]: 51
2818 12:41:04.112365
2819 12:41:04.112928 Set Vref, RX VrefLevel [Byte0]: 52
2820 12:41:04.115535 [Byte1]: 52
2821 12:41:04.120499
2822 12:41:04.121132 Set Vref, RX VrefLevel [Byte0]: 53
2823 12:41:04.123658 [Byte1]: 53
2824 12:41:04.128310
2825 12:41:04.128876 Set Vref, RX VrefLevel [Byte0]: 54
2826 12:41:04.131253 [Byte1]: 54
2827 12:41:04.135806
2828 12:41:04.136278 Set Vref, RX VrefLevel [Byte0]: 55
2829 12:41:04.139145 [Byte1]: 55
2830 12:41:04.143977
2831 12:41:04.144653 Set Vref, RX VrefLevel [Byte0]: 56
2832 12:41:04.147062 [Byte1]: 56
2833 12:41:04.151306
2834 12:41:04.151975 Set Vref, RX VrefLevel [Byte0]: 57
2835 12:41:04.155007 [Byte1]: 57
2836 12:41:04.159340
2837 12:41:04.160018 Set Vref, RX VrefLevel [Byte0]: 58
2838 12:41:04.162755 [Byte1]: 58
2839 12:41:04.167609
2840 12:41:04.170456 Set Vref, RX VrefLevel [Byte0]: 59
2841 12:41:04.171081 [Byte1]: 59
2842 12:41:04.175354
2843 12:41:04.175830 Set Vref, RX VrefLevel [Byte0]: 60
2844 12:41:04.178434 [Byte1]: 60
2845 12:41:04.183153
2846 12:41:04.183622 Set Vref, RX VrefLevel [Byte0]: 61
2847 12:41:04.186485 [Byte1]: 61
2848 12:41:04.190938
2849 12:41:04.191352 Set Vref, RX VrefLevel [Byte0]: 62
2850 12:41:04.194227 [Byte1]: 62
2851 12:41:04.198637
2852 12:41:04.198870 Set Vref, RX VrefLevel [Byte0]: 63
2853 12:41:04.202165 [Byte1]: 63
2854 12:41:04.206745
2855 12:41:04.206977 Set Vref, RX VrefLevel [Byte0]: 64
2856 12:41:04.210066 [Byte1]: 64
2857 12:41:04.214763
2858 12:41:04.215082 Set Vref, RX VrefLevel [Byte0]: 65
2859 12:41:04.218430 [Byte1]: 65
2860 12:41:04.222653
2861 12:41:04.222977 Set Vref, RX VrefLevel [Byte0]: 66
2862 12:41:04.226124 [Byte1]: 66
2863 12:41:04.230538
2864 12:41:04.230855 Set Vref, RX VrefLevel [Byte0]: 67
2865 12:41:04.233969 [Byte1]: 67
2866 12:41:04.238371
2867 12:41:04.238740 Set Vref, RX VrefLevel [Byte0]: 68
2868 12:41:04.241615 [Byte1]: 68
2869 12:41:04.246732
2870 12:41:04.247300 Set Vref, RX VrefLevel [Byte0]: 69
2871 12:41:04.249609 [Byte1]: 69
2872 12:41:04.254369
2873 12:41:04.254940 Set Vref, RX VrefLevel [Byte0]: 70
2874 12:41:04.257799 [Byte1]: 70
2875 12:41:04.262108
2876 12:41:04.262688 Final RX Vref Byte 0 = 57 to rank0
2877 12:41:04.265692 Final RX Vref Byte 1 = 49 to rank0
2878 12:41:04.269024 Final RX Vref Byte 0 = 57 to rank1
2879 12:41:04.272215 Final RX Vref Byte 1 = 49 to rank1==
2880 12:41:04.275839 Dram Type= 6, Freq= 0, CH_0, rank 0
2881 12:41:04.281906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2882 12:41:04.282464 ==
2883 12:41:04.282837 DQS Delay:
2884 12:41:04.283181 DQS0 = 0, DQS1 = 0
2885 12:41:04.285944 DQM Delay:
2886 12:41:04.286415 DQM0 = 123, DQM1 = 109
2887 12:41:04.288851 DQ Delay:
2888 12:41:04.292146 DQ0 =122, DQ1 =124, DQ2 =118, DQ3 =120
2889 12:41:04.295552 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2890 12:41:04.298840 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =106
2891 12:41:04.302198 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2892 12:41:04.302768
2893 12:41:04.303138
2894 12:41:04.309088 [DQSOSCAuto] RK0, (LSB)MR18= 0xa06, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 406 ps
2895 12:41:04.312440 CH0 RK0: MR19=404, MR18=A06
2896 12:41:04.319129 CH0_RK0: MR19=0x404, MR18=0xA06, DQSOSC=406, MR23=63, INC=39, DEC=26
2897 12:41:04.319697
2898 12:41:04.322449 ----->DramcWriteLeveling(PI) begin...
2899 12:41:04.323024 ==
2900 12:41:04.325552 Dram Type= 6, Freq= 0, CH_0, rank 1
2901 12:41:04.329015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2902 12:41:04.332112 ==
2903 12:41:04.332674 Write leveling (Byte 0): 34 => 34
2904 12:41:04.335420 Write leveling (Byte 1): 31 => 31
2905 12:41:04.338651 DramcWriteLeveling(PI) end<-----
2906 12:41:04.339119
2907 12:41:04.339482 ==
2908 12:41:04.341771 Dram Type= 6, Freq= 0, CH_0, rank 1
2909 12:41:04.348964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2910 12:41:04.349564 ==
2911 12:41:04.349996 [Gating] SW mode calibration
2912 12:41:04.359092 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2913 12:41:04.362300 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2914 12:41:04.365634 0 15 0 | B1->B0 | 3130 3434 | 1 1 | (0 0) (1 1)
2915 12:41:04.371936 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2916 12:41:04.375250 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2917 12:41:04.378729 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2918 12:41:04.385891 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2919 12:41:04.388831 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2920 12:41:04.392548 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2921 12:41:04.398381 0 15 28 | B1->B0 | 3030 2c2c | 1 0 | (1 1) (0 1)
2922 12:41:04.401854 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2923 12:41:04.405267 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2924 12:41:04.411629 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2925 12:41:04.415073 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2926 12:41:04.418274 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2927 12:41:04.425408 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2928 12:41:04.428637 1 0 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2929 12:41:04.432217 1 0 28 | B1->B0 | 3232 3b3b | 0 0 | (0 0) (0 0)
2930 12:41:04.438767 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2931 12:41:04.441830 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2932 12:41:04.445509 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2933 12:41:04.451875 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2934 12:41:04.455577 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 12:41:04.458774 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 12:41:04.465227 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2937 12:41:04.468194 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2938 12:41:04.471330 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2939 12:41:04.478322 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 12:41:04.481815 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 12:41:04.484659 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 12:41:04.488042 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 12:41:04.494660 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 12:41:04.498365 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 12:41:04.501431 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 12:41:04.508353 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 12:41:04.511151 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 12:41:04.514665 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 12:41:04.521209 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 12:41:04.524470 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 12:41:04.527993 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 12:41:04.534539 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2953 12:41:04.537781 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2954 12:41:04.541389 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2955 12:41:04.548071 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2956 12:41:04.548501 Total UI for P1: 0, mck2ui 16
2957 12:41:04.554853 best dqsien dly found for B0: ( 1, 3, 28)
2958 12:41:04.555284 Total UI for P1: 0, mck2ui 16
2959 12:41:04.561054 best dqsien dly found for B1: ( 1, 4, 0)
2960 12:41:04.564172 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2961 12:41:04.567728 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2962 12:41:04.567956
2963 12:41:04.570847 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2964 12:41:04.574559 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2965 12:41:04.577592 [Gating] SW calibration Done
2966 12:41:04.577822 ==
2967 12:41:04.580783 Dram Type= 6, Freq= 0, CH_0, rank 1
2968 12:41:04.584122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2969 12:41:04.584354 ==
2970 12:41:04.587668 RX Vref Scan: 0
2971 12:41:04.587991
2972 12:41:04.588237 RX Vref 0 -> 0, step: 1
2973 12:41:04.588517
2974 12:41:04.590914 RX Delay -40 -> 252, step: 8
2975 12:41:04.593988 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2976 12:41:04.600590 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2977 12:41:04.604022 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2978 12:41:04.607253 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2979 12:41:04.610706 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2980 12:41:04.614413 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2981 12:41:04.620866 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2982 12:41:04.623704 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2983 12:41:04.627410 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2984 12:41:04.630754 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2985 12:41:04.634094 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2986 12:41:04.640375 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2987 12:41:04.643778 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2988 12:41:04.647527 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2989 12:41:04.650520 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2990 12:41:04.654002 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2991 12:41:04.656988 ==
2992 12:41:04.660339 Dram Type= 6, Freq= 0, CH_0, rank 1
2993 12:41:04.663542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2994 12:41:04.663776 ==
2995 12:41:04.663959 DQS Delay:
2996 12:41:04.666843 DQS0 = 0, DQS1 = 0
2997 12:41:04.667076 DQM Delay:
2998 12:41:04.670599 DQM0 = 120, DQM1 = 108
2999 12:41:04.670830 DQ Delay:
3000 12:41:04.673577 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
3001 12:41:04.677067 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
3002 12:41:04.680255 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3003 12:41:04.683396 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
3004 12:41:04.683480
3005 12:41:04.683546
3006 12:41:04.683606 ==
3007 12:41:04.686868 Dram Type= 6, Freq= 0, CH_0, rank 1
3008 12:41:04.693462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3009 12:41:04.693550 ==
3010 12:41:04.693631
3011 12:41:04.693704
3012 12:41:04.693778 TX Vref Scan disable
3013 12:41:04.696642 == TX Byte 0 ==
3014 12:41:04.700218 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3015 12:41:04.706767 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3016 12:41:04.706851 == TX Byte 1 ==
3017 12:41:04.710315 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3018 12:41:04.717354 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3019 12:41:04.717450 ==
3020 12:41:04.720075 Dram Type= 6, Freq= 0, CH_0, rank 1
3021 12:41:04.723438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3022 12:41:04.723543 ==
3023 12:41:04.735100 TX Vref=22, minBit 0, minWin=24, winSum=407
3024 12:41:04.738814 TX Vref=24, minBit 0, minWin=25, winSum=418
3025 12:41:04.742071 TX Vref=26, minBit 7, minWin=24, winSum=414
3026 12:41:04.745386 TX Vref=28, minBit 0, minWin=25, winSum=418
3027 12:41:04.748652 TX Vref=30, minBit 1, minWin=25, winSum=418
3028 12:41:04.751991 TX Vref=32, minBit 7, minWin=24, winSum=419
3029 12:41:04.758925 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 24
3030 12:41:04.759260
3031 12:41:04.762157 Final TX Range 1 Vref 24
3032 12:41:04.762560
3033 12:41:04.762810 ==
3034 12:41:04.765480 Dram Type= 6, Freq= 0, CH_0, rank 1
3035 12:41:04.768881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3036 12:41:04.769297 ==
3037 12:41:04.769610
3038 12:41:04.772093
3039 12:41:04.772655 TX Vref Scan disable
3040 12:41:04.775133 == TX Byte 0 ==
3041 12:41:04.778414 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3042 12:41:04.785092 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3043 12:41:04.785778 == TX Byte 1 ==
3044 12:41:04.788502 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3045 12:41:04.791668 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3046 12:41:04.794873
3047 12:41:04.795530 [DATLAT]
3048 12:41:04.796122 Freq=1200, CH0 RK1
3049 12:41:04.796676
3050 12:41:04.798762 DATLAT Default: 0xd
3051 12:41:04.799296 0, 0xFFFF, sum = 0
3052 12:41:04.801606 1, 0xFFFF, sum = 0
3053 12:41:04.802228 2, 0xFFFF, sum = 0
3054 12:41:04.804730 3, 0xFFFF, sum = 0
3055 12:41:04.808125 4, 0xFFFF, sum = 0
3056 12:41:04.808601 5, 0xFFFF, sum = 0
3057 12:41:04.811556 6, 0xFFFF, sum = 0
3058 12:41:04.812016 7, 0xFFFF, sum = 0
3059 12:41:04.815004 8, 0xFFFF, sum = 0
3060 12:41:04.815607 9, 0xFFFF, sum = 0
3061 12:41:04.818281 10, 0xFFFF, sum = 0
3062 12:41:04.819001 11, 0xFFFF, sum = 0
3063 12:41:04.821486 12, 0x0, sum = 1
3064 12:41:04.821964 13, 0x0, sum = 2
3065 12:41:04.824943 14, 0x0, sum = 3
3066 12:41:04.825471 15, 0x0, sum = 4
3067 12:41:04.825855 best_step = 13
3068 12:41:04.828166
3069 12:41:04.828632 ==
3070 12:41:04.831536 Dram Type= 6, Freq= 0, CH_0, rank 1
3071 12:41:04.834803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3072 12:41:04.835288 ==
3073 12:41:04.835656 RX Vref Scan: 0
3074 12:41:04.835998
3075 12:41:04.838384 RX Vref 0 -> 0, step: 1
3076 12:41:04.838851
3077 12:41:04.841417 RX Delay -21 -> 252, step: 4
3078 12:41:04.844818 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3079 12:41:04.851616 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3080 12:41:04.855233 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3081 12:41:04.858644 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3082 12:41:04.861951 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3083 12:41:04.865052 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3084 12:41:04.871548 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3085 12:41:04.875185 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3086 12:41:04.878058 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3087 12:41:04.881567 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3088 12:41:04.884402 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3089 12:41:04.891316 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3090 12:41:04.894493 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3091 12:41:04.897703 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3092 12:41:04.901097 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3093 12:41:04.904688 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3094 12:41:04.907711 ==
3095 12:41:04.908013 Dram Type= 6, Freq= 0, CH_0, rank 1
3096 12:41:04.914316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3097 12:41:04.914581 ==
3098 12:41:04.914785 DQS Delay:
3099 12:41:04.918066 DQS0 = 0, DQS1 = 0
3100 12:41:04.918377 DQM Delay:
3101 12:41:04.920873 DQM0 = 119, DQM1 = 107
3102 12:41:04.921150 DQ Delay:
3103 12:41:04.924397 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =114
3104 12:41:04.927955 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3105 12:41:04.930856 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =104
3106 12:41:04.934196 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3107 12:41:04.934446
3108 12:41:04.934626
3109 12:41:04.944262 [DQSOSCAuto] RK1, (LSB)MR18= 0xef6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 404 ps
3110 12:41:04.944494 CH0 RK1: MR19=403, MR18=EF6
3111 12:41:04.950895 CH0_RK1: MR19=0x403, MR18=0xEF6, DQSOSC=404, MR23=63, INC=40, DEC=26
3112 12:41:04.954141 [RxdqsGatingPostProcess] freq 1200
3113 12:41:04.960713 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3114 12:41:04.964229 best DQS0 dly(2T, 0.5T) = (0, 11)
3115 12:41:04.967490 best DQS1 dly(2T, 0.5T) = (0, 12)
3116 12:41:04.970669 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3117 12:41:04.974161 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3118 12:41:04.977154 best DQS0 dly(2T, 0.5T) = (0, 11)
3119 12:41:04.977228 best DQS1 dly(2T, 0.5T) = (0, 12)
3120 12:41:04.980675 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3121 12:41:04.984127 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3122 12:41:04.987358 Pre-setting of DQS Precalculation
3123 12:41:04.994330 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3124 12:41:04.994770 ==
3125 12:41:04.997972 Dram Type= 6, Freq= 0, CH_1, rank 0
3126 12:41:05.001032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3127 12:41:05.001457 ==
3128 12:41:05.007675 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3129 12:41:05.014547 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3130 12:41:05.021294 [CA 0] Center 37 (7~68) winsize 62
3131 12:41:05.024464 [CA 1] Center 37 (7~68) winsize 62
3132 12:41:05.028017 [CA 2] Center 35 (5~65) winsize 61
3133 12:41:05.031614 [CA 3] Center 34 (4~65) winsize 62
3134 12:41:05.035172 [CA 4] Center 33 (3~64) winsize 62
3135 12:41:05.037816 [CA 5] Center 33 (3~64) winsize 62
3136 12:41:05.038290
3137 12:41:05.041344 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3138 12:41:05.041913
3139 12:41:05.044515 [CATrainingPosCal] consider 1 rank data
3140 12:41:05.047742 u2DelayCellTimex100 = 270/100 ps
3141 12:41:05.051202 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3142 12:41:05.054351 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3143 12:41:05.061060 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3144 12:41:05.064655 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3145 12:41:05.067997 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3146 12:41:05.071036 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3147 12:41:05.071506
3148 12:41:05.074462 CA PerBit enable=1, Macro0, CA PI delay=33
3149 12:41:05.075049
3150 12:41:05.077924 [CBTSetCACLKResult] CA Dly = 33
3151 12:41:05.078493 CS Dly: 5 (0~36)
3152 12:41:05.081088 ==
3153 12:41:05.081658 Dram Type= 6, Freq= 0, CH_1, rank 1
3154 12:41:05.087676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3155 12:41:05.088282 ==
3156 12:41:05.090796 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3157 12:41:05.097349 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3158 12:41:05.106645 [CA 0] Center 38 (8~68) winsize 61
3159 12:41:05.110044 [CA 1] Center 38 (7~69) winsize 63
3160 12:41:05.113926 [CA 2] Center 35 (5~66) winsize 62
3161 12:41:05.117063 [CA 3] Center 34 (4~65) winsize 62
3162 12:41:05.120412 [CA 4] Center 35 (5~65) winsize 61
3163 12:41:05.123570 [CA 5] Center 34 (4~64) winsize 61
3164 12:41:05.124039
3165 12:41:05.126524 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3166 12:41:05.126989
3167 12:41:05.129991 [CATrainingPosCal] consider 2 rank data
3168 12:41:05.133343 u2DelayCellTimex100 = 270/100 ps
3169 12:41:05.137106 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3170 12:41:05.143658 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3171 12:41:05.146842 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3172 12:41:05.149979 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3173 12:41:05.153397 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
3174 12:41:05.156689 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3175 12:41:05.157311
3176 12:41:05.159804 CA PerBit enable=1, Macro0, CA PI delay=34
3177 12:41:05.160281
3178 12:41:05.163192 [CBTSetCACLKResult] CA Dly = 34
3179 12:41:05.163666 CS Dly: 6 (0~39)
3180 12:41:05.166661
3181 12:41:05.169910 ----->DramcWriteLeveling(PI) begin...
3182 12:41:05.170541 ==
3183 12:41:05.173411 Dram Type= 6, Freq= 0, CH_1, rank 0
3184 12:41:05.176394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3185 12:41:05.176872 ==
3186 12:41:05.179889 Write leveling (Byte 0): 24 => 24
3187 12:41:05.183500 Write leveling (Byte 1): 28 => 28
3188 12:41:05.186422 DramcWriteLeveling(PI) end<-----
3189 12:41:05.186897
3190 12:41:05.187267 ==
3191 12:41:05.189686 Dram Type= 6, Freq= 0, CH_1, rank 0
3192 12:41:05.193104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3193 12:41:05.193667 ==
3194 12:41:05.196856 [Gating] SW mode calibration
3195 12:41:05.203045 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3196 12:41:05.209768 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3197 12:41:05.213089 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3198 12:41:05.216690 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3199 12:41:05.223092 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3200 12:41:05.226329 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3201 12:41:05.229437 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3202 12:41:05.236177 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3203 12:41:05.239800 0 15 24 | B1->B0 | 2828 2323 | 0 0 | (0 1) (1 0)
3204 12:41:05.242768 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3205 12:41:05.246273 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3206 12:41:05.253044 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3207 12:41:05.256585 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3208 12:41:05.259654 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3209 12:41:05.266302 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3210 12:41:05.269871 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3211 12:41:05.273031 1 0 24 | B1->B0 | 3b3b 4444 | 0 0 | (0 0) (0 0)
3212 12:41:05.279518 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3213 12:41:05.282773 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3214 12:41:05.286488 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 12:41:05.293062 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3216 12:41:05.296361 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 12:41:05.299624 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3218 12:41:05.306037 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 12:41:05.309493 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3220 12:41:05.312651 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3221 12:41:05.319094 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 12:41:05.322525 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 12:41:05.325795 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 12:41:05.332444 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 12:41:05.335780 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 12:41:05.339221 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 12:41:05.346172 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 12:41:05.348957 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 12:41:05.352470 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 12:41:05.358987 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 12:41:05.362785 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 12:41:05.366082 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 12:41:05.372795 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 12:41:05.375733 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3235 12:41:05.379435 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3236 12:41:05.382776 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3237 12:41:05.385813 Total UI for P1: 0, mck2ui 16
3238 12:41:05.389114 best dqsien dly found for B0: ( 1, 3, 22)
3239 12:41:05.392893 Total UI for P1: 0, mck2ui 16
3240 12:41:05.396007 best dqsien dly found for B1: ( 1, 3, 24)
3241 12:41:05.399248 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3242 12:41:05.405864 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3243 12:41:05.406452
3244 12:41:05.408810 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3245 12:41:05.412344 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3246 12:41:05.416009 [Gating] SW calibration Done
3247 12:41:05.416588 ==
3248 12:41:05.419282 Dram Type= 6, Freq= 0, CH_1, rank 0
3249 12:41:05.422495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3250 12:41:05.422973 ==
3251 12:41:05.423348 RX Vref Scan: 0
3252 12:41:05.425521
3253 12:41:05.425995 RX Vref 0 -> 0, step: 1
3254 12:41:05.426371
3255 12:41:05.429318 RX Delay -40 -> 252, step: 8
3256 12:41:05.433024 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3257 12:41:05.435576 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3258 12:41:05.442382 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3259 12:41:05.445450 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3260 12:41:05.448921 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3261 12:41:05.452628 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3262 12:41:05.455998 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3263 12:41:05.462428 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3264 12:41:05.465879 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3265 12:41:05.469572 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3266 12:41:05.472264 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3267 12:41:05.475489 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3268 12:41:05.483282 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3269 12:41:05.485472 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3270 12:41:05.489102 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3271 12:41:05.492177 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3272 12:41:05.492745 ==
3273 12:41:05.495456 Dram Type= 6, Freq= 0, CH_1, rank 0
3274 12:41:05.502460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3275 12:41:05.503031 ==
3276 12:41:05.503412 DQS Delay:
3277 12:41:05.505808 DQS0 = 0, DQS1 = 0
3278 12:41:05.506369 DQM Delay:
3279 12:41:05.506746 DQM0 = 119, DQM1 = 112
3280 12:41:05.508486 DQ Delay:
3281 12:41:05.511918 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3282 12:41:05.515151 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3283 12:41:05.518896 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3284 12:41:05.522229 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3285 12:41:05.522708
3286 12:41:05.523083
3287 12:41:05.523432 ==
3288 12:41:05.525268 Dram Type= 6, Freq= 0, CH_1, rank 0
3289 12:41:05.528799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3290 12:41:05.531954 ==
3291 12:41:05.532513
3292 12:41:05.532880
3293 12:41:05.533281 TX Vref Scan disable
3294 12:41:05.535575 == TX Byte 0 ==
3295 12:41:05.538408 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3296 12:41:05.541686 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3297 12:41:05.545036 == TX Byte 1 ==
3298 12:41:05.548874 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3299 12:41:05.551428 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3300 12:41:05.554765 ==
3301 12:41:05.555238 Dram Type= 6, Freq= 0, CH_1, rank 0
3302 12:41:05.561602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3303 12:41:05.562175 ==
3304 12:41:05.572794 TX Vref=22, minBit 7, minWin=24, winSum=403
3305 12:41:05.576093 TX Vref=24, minBit 1, minWin=25, winSum=411
3306 12:41:05.579639 TX Vref=26, minBit 8, minWin=25, winSum=414
3307 12:41:05.582798 TX Vref=28, minBit 3, minWin=25, winSum=418
3308 12:41:05.585897 TX Vref=30, minBit 11, minWin=25, winSum=423
3309 12:41:05.592860 TX Vref=32, minBit 9, minWin=25, winSum=421
3310 12:41:05.595795 [TxChooseVref] Worse bit 11, Min win 25, Win sum 423, Final Vref 30
3311 12:41:05.596394
3312 12:41:05.599495 Final TX Range 1 Vref 30
3313 12:41:05.600060
3314 12:41:05.600447 ==
3315 12:41:05.602796 Dram Type= 6, Freq= 0, CH_1, rank 0
3316 12:41:05.605946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3317 12:41:05.609075 ==
3318 12:41:05.609641
3319 12:41:05.610010
3320 12:41:05.610352 TX Vref Scan disable
3321 12:41:05.612496 == TX Byte 0 ==
3322 12:41:05.616305 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3323 12:41:05.622461 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3324 12:41:05.623070 == TX Byte 1 ==
3325 12:41:05.625815 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3326 12:41:05.632740 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3327 12:41:05.633523
3328 12:41:05.633909 [DATLAT]
3329 12:41:05.634253 Freq=1200, CH1 RK0
3330 12:41:05.634598
3331 12:41:05.635379 DATLAT Default: 0xd
3332 12:41:05.635751 0, 0xFFFF, sum = 0
3333 12:41:05.639331 1, 0xFFFF, sum = 0
3334 12:41:05.639903 2, 0xFFFF, sum = 0
3335 12:41:05.642407 3, 0xFFFF, sum = 0
3336 12:41:05.645876 4, 0xFFFF, sum = 0
3337 12:41:05.646447 5, 0xFFFF, sum = 0
3338 12:41:05.649085 6, 0xFFFF, sum = 0
3339 12:41:05.649696 7, 0xFFFF, sum = 0
3340 12:41:05.652325 8, 0xFFFF, sum = 0
3341 12:41:05.652897 9, 0xFFFF, sum = 0
3342 12:41:05.655774 10, 0xFFFF, sum = 0
3343 12:41:05.656453 11, 0xFFFF, sum = 0
3344 12:41:05.659025 12, 0x0, sum = 1
3345 12:41:05.659598 13, 0x0, sum = 2
3346 12:41:05.662240 14, 0x0, sum = 3
3347 12:41:05.662714 15, 0x0, sum = 4
3348 12:41:05.665548 best_step = 13
3349 12:41:05.666015
3350 12:41:05.666382 ==
3351 12:41:05.669074 Dram Type= 6, Freq= 0, CH_1, rank 0
3352 12:41:05.672082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3353 12:41:05.672550 ==
3354 12:41:05.672920 RX Vref Scan: 1
3355 12:41:05.673357
3356 12:41:05.676097 Set Vref Range= 32 -> 127
3357 12:41:05.676694
3358 12:41:05.679139 RX Vref 32 -> 127, step: 1
3359 12:41:05.679709
3360 12:41:05.682241 RX Delay -13 -> 252, step: 4
3361 12:41:05.682696
3362 12:41:05.685420 Set Vref, RX VrefLevel [Byte0]: 32
3363 12:41:05.688822 [Byte1]: 32
3364 12:41:05.689313
3365 12:41:05.692072 Set Vref, RX VrefLevel [Byte0]: 33
3366 12:41:05.695365 [Byte1]: 33
3367 12:41:05.698785
3368 12:41:05.699239 Set Vref, RX VrefLevel [Byte0]: 34
3369 12:41:05.701968 [Byte1]: 34
3370 12:41:05.707484
3371 12:41:05.708031 Set Vref, RX VrefLevel [Byte0]: 35
3372 12:41:05.709995 [Byte1]: 35
3373 12:41:05.714840
3374 12:41:05.715389 Set Vref, RX VrefLevel [Byte0]: 36
3375 12:41:05.717964 [Byte1]: 36
3376 12:41:05.722967
3377 12:41:05.723520 Set Vref, RX VrefLevel [Byte0]: 37
3378 12:41:05.725844 [Byte1]: 37
3379 12:41:05.730984
3380 12:41:05.731549 Set Vref, RX VrefLevel [Byte0]: 38
3381 12:41:05.733737 [Byte1]: 38
3382 12:41:05.738814
3383 12:41:05.739425 Set Vref, RX VrefLevel [Byte0]: 39
3384 12:41:05.741602 [Byte1]: 39
3385 12:41:05.746291
3386 12:41:05.746844 Set Vref, RX VrefLevel [Byte0]: 40
3387 12:41:05.749638 [Byte1]: 40
3388 12:41:05.754822
3389 12:41:05.755373 Set Vref, RX VrefLevel [Byte0]: 41
3390 12:41:05.760698 [Byte1]: 41
3391 12:41:05.761286
3392 12:41:05.763946 Set Vref, RX VrefLevel [Byte0]: 42
3393 12:41:05.767204 [Byte1]: 42
3394 12:41:05.767756
3395 12:41:05.770347 Set Vref, RX VrefLevel [Byte0]: 43
3396 12:41:05.773610 [Byte1]: 43
3397 12:41:05.777668
3398 12:41:05.778213 Set Vref, RX VrefLevel [Byte0]: 44
3399 12:41:05.781110 [Byte1]: 44
3400 12:41:05.785560
3401 12:41:05.786112 Set Vref, RX VrefLevel [Byte0]: 45
3402 12:41:05.789101 [Byte1]: 45
3403 12:41:05.793782
3404 12:41:05.794341 Set Vref, RX VrefLevel [Byte0]: 46
3405 12:41:05.796772 [Byte1]: 46
3406 12:41:05.801567
3407 12:41:05.802121 Set Vref, RX VrefLevel [Byte0]: 47
3408 12:41:05.805021 [Byte1]: 47
3409 12:41:05.809473
3410 12:41:05.810034 Set Vref, RX VrefLevel [Byte0]: 48
3411 12:41:05.812792 [Byte1]: 48
3412 12:41:05.817229
3413 12:41:05.817779 Set Vref, RX VrefLevel [Byte0]: 49
3414 12:41:05.820676 [Byte1]: 49
3415 12:41:05.825085
3416 12:41:05.825550 Set Vref, RX VrefLevel [Byte0]: 50
3417 12:41:05.828344 [Byte1]: 50
3418 12:41:05.833240
3419 12:41:05.833797 Set Vref, RX VrefLevel [Byte0]: 51
3420 12:41:05.836691 [Byte1]: 51
3421 12:41:05.841070
3422 12:41:05.841653 Set Vref, RX VrefLevel [Byte0]: 52
3423 12:41:05.844422 [Byte1]: 52
3424 12:41:05.849064
3425 12:41:05.849628 Set Vref, RX VrefLevel [Byte0]: 53
3426 12:41:05.852106 [Byte1]: 53
3427 12:41:05.856638
3428 12:41:05.860172 Set Vref, RX VrefLevel [Byte0]: 54
3429 12:41:05.860735 [Byte1]: 54
3430 12:41:05.864744
3431 12:41:05.865341 Set Vref, RX VrefLevel [Byte0]: 55
3432 12:41:05.868355 [Byte1]: 55
3433 12:41:05.872498
3434 12:41:05.873119 Set Vref, RX VrefLevel [Byte0]: 56
3435 12:41:05.875605 [Byte1]: 56
3436 12:41:05.880299
3437 12:41:05.880853 Set Vref, RX VrefLevel [Byte0]: 57
3438 12:41:05.883906 [Byte1]: 57
3439 12:41:05.888670
3440 12:41:05.889218 Set Vref, RX VrefLevel [Byte0]: 58
3441 12:41:05.891678 [Byte1]: 58
3442 12:41:05.896171
3443 12:41:05.896728 Set Vref, RX VrefLevel [Byte0]: 59
3444 12:41:05.899681 [Byte1]: 59
3445 12:41:05.904320
3446 12:41:05.904872 Set Vref, RX VrefLevel [Byte0]: 60
3447 12:41:05.907379 [Byte1]: 60
3448 12:41:05.911759
3449 12:41:05.912545 Set Vref, RX VrefLevel [Byte0]: 61
3450 12:41:05.914783 [Byte1]: 61
3451 12:41:05.920509
3452 12:41:05.921244 Set Vref, RX VrefLevel [Byte0]: 62
3453 12:41:05.926277 [Byte1]: 62
3454 12:41:05.927069
3455 12:41:05.929535 Set Vref, RX VrefLevel [Byte0]: 63
3456 12:41:05.932617 [Byte1]: 63
3457 12:41:05.933400
3458 12:41:05.936136 Set Vref, RX VrefLevel [Byte0]: 64
3459 12:41:05.939183 [Byte1]: 64
3460 12:41:05.943179
3461 12:41:05.943582 Set Vref, RX VrefLevel [Byte0]: 65
3462 12:41:05.946601 [Byte1]: 65
3463 12:41:05.950904
3464 12:41:05.951310 Set Vref, RX VrefLevel [Byte0]: 66
3465 12:41:05.955104 [Byte1]: 66
3466 12:41:05.958783
3467 12:41:05.959257 Set Vref, RX VrefLevel [Byte0]: 67
3468 12:41:05.962168 [Byte1]: 67
3469 12:41:05.966933
3470 12:41:05.967344 Final RX Vref Byte 0 = 53 to rank0
3471 12:41:05.970379 Final RX Vref Byte 1 = 53 to rank0
3472 12:41:05.973416 Final RX Vref Byte 0 = 53 to rank1
3473 12:41:05.976691 Final RX Vref Byte 1 = 53 to rank1==
3474 12:41:05.980075 Dram Type= 6, Freq= 0, CH_1, rank 0
3475 12:41:05.986518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3476 12:41:05.986729 ==
3477 12:41:05.986906 DQS Delay:
3478 12:41:05.987052 DQS0 = 0, DQS1 = 0
3479 12:41:05.990246 DQM Delay:
3480 12:41:05.990574 DQM0 = 119, DQM1 = 112
3481 12:41:05.993231 DQ Delay:
3482 12:41:05.996523 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3483 12:41:05.999846 DQ4 =118, DQ5 =126, DQ6 =130, DQ7 =118
3484 12:41:06.003132 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3485 12:41:06.006930 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =118
3486 12:41:06.007129
3487 12:41:06.007282
3488 12:41:06.013221 [DQSOSCAuto] RK0, (LSB)MR18= 0x417, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3489 12:41:06.016619 CH1 RK0: MR19=404, MR18=417
3490 12:41:06.023416 CH1_RK0: MR19=0x404, MR18=0x417, DQSOSC=401, MR23=63, INC=40, DEC=27
3491 12:41:06.023741
3492 12:41:06.026881 ----->DramcWriteLeveling(PI) begin...
3493 12:41:06.027106 ==
3494 12:41:06.029896 Dram Type= 6, Freq= 0, CH_1, rank 1
3495 12:41:06.033149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3496 12:41:06.036188 ==
3497 12:41:06.036280 Write leveling (Byte 0): 26 => 26
3498 12:41:06.039620 Write leveling (Byte 1): 29 => 29
3499 12:41:06.042968 DramcWriteLeveling(PI) end<-----
3500 12:41:06.043052
3501 12:41:06.043118 ==
3502 12:41:06.046596 Dram Type= 6, Freq= 0, CH_1, rank 1
3503 12:41:06.053396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3504 12:41:06.053870 ==
3505 12:41:06.054248 [Gating] SW mode calibration
3506 12:41:06.063426 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3507 12:41:06.067056 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3508 12:41:06.073532 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3509 12:41:06.077364 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3510 12:41:06.079855 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3511 12:41:06.086750 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3512 12:41:06.089789 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3513 12:41:06.093320 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3514 12:41:06.099595 0 15 24 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 0)
3515 12:41:06.103055 0 15 28 | B1->B0 | 2323 2727 | 0 0 | (1 0) (0 1)
3516 12:41:06.106273 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3517 12:41:06.109529 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3518 12:41:06.115957 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3519 12:41:06.119514 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3520 12:41:06.122717 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3521 12:41:06.129715 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3522 12:41:06.132787 1 0 24 | B1->B0 | 3838 2b2b | 0 0 | (1 1) (0 0)
3523 12:41:06.136404 1 0 28 | B1->B0 | 4646 4040 | 0 0 | (0 0) (0 0)
3524 12:41:06.142824 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3525 12:41:06.145944 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3526 12:41:06.149854 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3527 12:41:06.155937 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 12:41:06.159256 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3529 12:41:06.162787 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3530 12:41:06.169068 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3531 12:41:06.172104 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3532 12:41:06.175753 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 12:41:06.182872 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 12:41:06.185558 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 12:41:06.189125 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 12:41:06.195720 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 12:41:06.199437 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 12:41:06.202263 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 12:41:06.208724 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 12:41:06.212377 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 12:41:06.216010 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 12:41:06.222122 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 12:41:06.225526 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 12:41:06.229156 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 12:41:06.235619 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 12:41:06.238488 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3547 12:41:06.241841 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3548 12:41:06.245371 Total UI for P1: 0, mck2ui 16
3549 12:41:06.249133 best dqsien dly found for B0: ( 1, 3, 24)
3550 12:41:06.252240 Total UI for P1: 0, mck2ui 16
3551 12:41:06.255538 best dqsien dly found for B1: ( 1, 3, 24)
3552 12:41:06.258525 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3553 12:41:06.262468 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3554 12:41:06.263050
3555 12:41:06.268671 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3556 12:41:06.272284 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3557 12:41:06.272859 [Gating] SW calibration Done
3558 12:41:06.275224 ==
3559 12:41:06.278293 Dram Type= 6, Freq= 0, CH_1, rank 1
3560 12:41:06.281727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3561 12:41:06.282204 ==
3562 12:41:06.282577 RX Vref Scan: 0
3563 12:41:06.282920
3564 12:41:06.285276 RX Vref 0 -> 0, step: 1
3565 12:41:06.285749
3566 12:41:06.288569 RX Delay -40 -> 252, step: 8
3567 12:41:06.292048 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3568 12:41:06.295071 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3569 12:41:06.301470 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3570 12:41:06.305037 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3571 12:41:06.308502 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3572 12:41:06.311530 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3573 12:41:06.314906 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3574 12:41:06.321431 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3575 12:41:06.324731 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3576 12:41:06.328629 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3577 12:41:06.331636 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3578 12:41:06.335056 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3579 12:41:06.341324 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3580 12:41:06.345134 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3581 12:41:06.348044 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3582 12:41:06.351135 iDelay=200, Bit 15, Center 123 (48 ~ 199) 152
3583 12:41:06.351667 ==
3584 12:41:06.354402 Dram Type= 6, Freq= 0, CH_1, rank 1
3585 12:41:06.361414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3586 12:41:06.361985 ==
3587 12:41:06.362358 DQS Delay:
3588 12:41:06.364418 DQS0 = 0, DQS1 = 0
3589 12:41:06.364880 DQM Delay:
3590 12:41:06.365284 DQM0 = 120, DQM1 = 112
3591 12:41:06.367760 DQ Delay:
3592 12:41:06.371278 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =119
3593 12:41:06.374217 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3594 12:41:06.377708 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3595 12:41:06.381156 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =123
3596 12:41:06.381721
3597 12:41:06.382112
3598 12:41:06.382456 ==
3599 12:41:06.384118 Dram Type= 6, Freq= 0, CH_1, rank 1
3600 12:41:06.387790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3601 12:41:06.390814 ==
3602 12:41:06.391390
3603 12:41:06.391762
3604 12:41:06.392110 TX Vref Scan disable
3605 12:41:06.394200 == TX Byte 0 ==
3606 12:41:06.397566 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3607 12:41:06.400746 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3608 12:41:06.403996 == TX Byte 1 ==
3609 12:41:06.407194 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3610 12:41:06.410485 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3611 12:41:06.413981 ==
3612 12:41:06.417246 Dram Type= 6, Freq= 0, CH_1, rank 1
3613 12:41:06.420284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3614 12:41:06.420868 ==
3615 12:41:06.431703 TX Vref=22, minBit 1, minWin=25, winSum=419
3616 12:41:06.435261 TX Vref=24, minBit 0, minWin=26, winSum=422
3617 12:41:06.438882 TX Vref=26, minBit 3, minWin=26, winSum=426
3618 12:41:06.441636 TX Vref=28, minBit 9, minWin=25, winSum=428
3619 12:41:06.445114 TX Vref=30, minBit 1, minWin=26, winSum=425
3620 12:41:06.451659 TX Vref=32, minBit 1, minWin=26, winSum=426
3621 12:41:06.454732 [TxChooseVref] Worse bit 3, Min win 26, Win sum 426, Final Vref 26
3622 12:41:06.455226
3623 12:41:06.457831 Final TX Range 1 Vref 26
3624 12:41:06.458320
3625 12:41:06.458798 ==
3626 12:41:06.461140 Dram Type= 6, Freq= 0, CH_1, rank 1
3627 12:41:06.464308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3628 12:41:06.467806 ==
3629 12:41:06.468290
3630 12:41:06.468772
3631 12:41:06.469256 TX Vref Scan disable
3632 12:41:06.471182 == TX Byte 0 ==
3633 12:41:06.474698 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3634 12:41:06.481658 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3635 12:41:06.482245 == TX Byte 1 ==
3636 12:41:06.484715 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3637 12:41:06.491232 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3638 12:41:06.491815
3639 12:41:06.492299 [DATLAT]
3640 12:41:06.492749 Freq=1200, CH1 RK1
3641 12:41:06.493270
3642 12:41:06.494243 DATLAT Default: 0xd
3643 12:41:06.494725 0, 0xFFFF, sum = 0
3644 12:41:06.498078 1, 0xFFFF, sum = 0
3645 12:41:06.500731 2, 0xFFFF, sum = 0
3646 12:41:06.501259 3, 0xFFFF, sum = 0
3647 12:41:06.503984 4, 0xFFFF, sum = 0
3648 12:41:06.504474 5, 0xFFFF, sum = 0
3649 12:41:06.507415 6, 0xFFFF, sum = 0
3650 12:41:06.507908 7, 0xFFFF, sum = 0
3651 12:41:06.510666 8, 0xFFFF, sum = 0
3652 12:41:06.511147 9, 0xFFFF, sum = 0
3653 12:41:06.514202 10, 0xFFFF, sum = 0
3654 12:41:06.514758 11, 0xFFFF, sum = 0
3655 12:41:06.517696 12, 0x0, sum = 1
3656 12:41:06.518217 13, 0x0, sum = 2
3657 12:41:06.520957 14, 0x0, sum = 3
3658 12:41:06.521558 15, 0x0, sum = 4
3659 12:41:06.524147 best_step = 13
3660 12:41:06.524736
3661 12:41:06.525136 ==
3662 12:41:06.527618 Dram Type= 6, Freq= 0, CH_1, rank 1
3663 12:41:06.530618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3664 12:41:06.531096 ==
3665 12:41:06.531476 RX Vref Scan: 0
3666 12:41:06.533663
3667 12:41:06.534201 RX Vref 0 -> 0, step: 1
3668 12:41:06.534583
3669 12:41:06.537341 RX Delay -13 -> 252, step: 4
3670 12:41:06.544046 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3671 12:41:06.547474 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3672 12:41:06.550576 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3673 12:41:06.553748 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3674 12:41:06.557750 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3675 12:41:06.563879 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3676 12:41:06.567024 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3677 12:41:06.570413 iDelay=195, Bit 7, Center 118 (59 ~ 178) 120
3678 12:41:06.573590 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3679 12:41:06.576661 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3680 12:41:06.583219 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3681 12:41:06.586490 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3682 12:41:06.590040 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3683 12:41:06.593320 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3684 12:41:06.599938 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3685 12:41:06.603452 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3686 12:41:06.604019 ==
3687 12:41:06.606462 Dram Type= 6, Freq= 0, CH_1, rank 1
3688 12:41:06.609937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3689 12:41:06.610419 ==
3690 12:41:06.612603 DQS Delay:
3691 12:41:06.613118 DQS0 = 0, DQS1 = 0
3692 12:41:06.613505 DQM Delay:
3693 12:41:06.616850 DQM0 = 119, DQM1 = 113
3694 12:41:06.617376 DQ Delay:
3695 12:41:06.619512 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3696 12:41:06.622880 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =118
3697 12:41:06.626028 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =108
3698 12:41:06.632889 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3699 12:41:06.633474
3700 12:41:06.633851
3701 12:41:06.639512 [DQSOSCAuto] RK1, (LSB)MR18= 0xbf0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 405 ps
3702 12:41:06.642946 CH1 RK1: MR19=403, MR18=BF0
3703 12:41:06.649125 CH1_RK1: MR19=0x403, MR18=0xBF0, DQSOSC=405, MR23=63, INC=39, DEC=26
3704 12:41:06.652587 [RxdqsGatingPostProcess] freq 1200
3705 12:41:06.656024 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3706 12:41:06.659556 best DQS0 dly(2T, 0.5T) = (0, 11)
3707 12:41:06.663013 best DQS1 dly(2T, 0.5T) = (0, 11)
3708 12:41:06.666320 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3709 12:41:06.669438 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3710 12:41:06.672749 best DQS0 dly(2T, 0.5T) = (0, 11)
3711 12:41:06.676321 best DQS1 dly(2T, 0.5T) = (0, 11)
3712 12:41:06.679304 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3713 12:41:06.682594 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3714 12:41:06.685798 Pre-setting of DQS Precalculation
3715 12:41:06.689363 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3716 12:41:06.699171 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3717 12:41:06.706210 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3718 12:41:06.706778
3719 12:41:06.707157
3720 12:41:06.709489 [Calibration Summary] 2400 Mbps
3721 12:41:06.710057 CH 0, Rank 0
3722 12:41:06.712226 SW Impedance : PASS
3723 12:41:06.712699 DUTY Scan : NO K
3724 12:41:06.715996 ZQ Calibration : PASS
3725 12:41:06.719155 Jitter Meter : NO K
3726 12:41:06.719735 CBT Training : PASS
3727 12:41:06.722497 Write leveling : PASS
3728 12:41:06.725460 RX DQS gating : PASS
3729 12:41:06.725935 RX DQ/DQS(RDDQC) : PASS
3730 12:41:06.728606 TX DQ/DQS : PASS
3731 12:41:06.732129 RX DATLAT : PASS
3732 12:41:06.732605 RX DQ/DQS(Engine): PASS
3733 12:41:06.735427 TX OE : NO K
3734 12:41:06.736110 All Pass.
3735 12:41:06.736498
3736 12:41:06.738525 CH 0, Rank 1
3737 12:41:06.738998 SW Impedance : PASS
3738 12:41:06.742042 DUTY Scan : NO K
3739 12:41:06.742519 ZQ Calibration : PASS
3740 12:41:06.745529 Jitter Meter : NO K
3741 12:41:06.748485 CBT Training : PASS
3742 12:41:06.749027 Write leveling : PASS
3743 12:41:06.752012 RX DQS gating : PASS
3744 12:41:06.755477 RX DQ/DQS(RDDQC) : PASS
3745 12:41:06.756059 TX DQ/DQS : PASS
3746 12:41:06.758953 RX DATLAT : PASS
3747 12:41:06.762088 RX DQ/DQS(Engine): PASS
3748 12:41:06.762656 TX OE : NO K
3749 12:41:06.765546 All Pass.
3750 12:41:06.766109
3751 12:41:06.766485 CH 1, Rank 0
3752 12:41:06.768777 SW Impedance : PASS
3753 12:41:06.769365 DUTY Scan : NO K
3754 12:41:06.772240 ZQ Calibration : PASS
3755 12:41:06.775987 Jitter Meter : NO K
3756 12:41:06.776551 CBT Training : PASS
3757 12:41:06.778824 Write leveling : PASS
3758 12:41:06.781871 RX DQS gating : PASS
3759 12:41:06.782471 RX DQ/DQS(RDDQC) : PASS
3760 12:41:06.785148 TX DQ/DQS : PASS
3761 12:41:06.788755 RX DATLAT : PASS
3762 12:41:06.789399 RX DQ/DQS(Engine): PASS
3763 12:41:06.791980 TX OE : NO K
3764 12:41:06.792546 All Pass.
3765 12:41:06.792922
3766 12:41:06.794962 CH 1, Rank 1
3767 12:41:06.795436 SW Impedance : PASS
3768 12:41:06.798635 DUTY Scan : NO K
3769 12:41:06.801620 ZQ Calibration : PASS
3770 12:41:06.802188 Jitter Meter : NO K
3771 12:41:06.805082 CBT Training : PASS
3772 12:41:06.805649 Write leveling : PASS
3773 12:41:06.808601 RX DQS gating : PASS
3774 12:41:06.811576 RX DQ/DQS(RDDQC) : PASS
3775 12:41:06.812171 TX DQ/DQS : PASS
3776 12:41:06.815175 RX DATLAT : PASS
3777 12:41:06.818183 RX DQ/DQS(Engine): PASS
3778 12:41:06.818751 TX OE : NO K
3779 12:41:06.822012 All Pass.
3780 12:41:06.822485
3781 12:41:06.822857 DramC Write-DBI off
3782 12:41:06.824937 PER_BANK_REFRESH: Hybrid Mode
3783 12:41:06.828230 TX_TRACKING: ON
3784 12:41:06.834764 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3785 12:41:06.837698 [FAST_K] Save calibration result to emmc
3786 12:41:06.841116 dramc_set_vcore_voltage set vcore to 650000
3787 12:41:06.844342 Read voltage for 600, 5
3788 12:41:06.844817 Vio18 = 0
3789 12:41:06.847989 Vcore = 650000
3790 12:41:06.848572 Vdram = 0
3791 12:41:06.848948 Vddq = 0
3792 12:41:06.851009 Vmddr = 0
3793 12:41:06.854583 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3794 12:41:06.861416 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3795 12:41:06.861981 MEM_TYPE=3, freq_sel=19
3796 12:41:06.864557 sv_algorithm_assistance_LP4_1600
3797 12:41:06.871074 ============ PULL DRAM RESETB DOWN ============
3798 12:41:06.874584 ========== PULL DRAM RESETB DOWN end =========
3799 12:41:06.877872 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3800 12:41:06.881138 ===================================
3801 12:41:06.884142 LPDDR4 DRAM CONFIGURATION
3802 12:41:06.887625 ===================================
3803 12:41:06.890958 EX_ROW_EN[0] = 0x0
3804 12:41:06.891528 EX_ROW_EN[1] = 0x0
3805 12:41:06.893965 LP4Y_EN = 0x0
3806 12:41:06.894524 WORK_FSP = 0x0
3807 12:41:06.897528 WL = 0x2
3808 12:41:06.898099 RL = 0x2
3809 12:41:06.900743 BL = 0x2
3810 12:41:06.901344 RPST = 0x0
3811 12:41:06.904209 RD_PRE = 0x0
3812 12:41:06.904772 WR_PRE = 0x1
3813 12:41:06.907563 WR_PST = 0x0
3814 12:41:06.908125 DBI_WR = 0x0
3815 12:41:06.910504 DBI_RD = 0x0
3816 12:41:06.914037 OTF = 0x1
3817 12:41:06.914516 ===================================
3818 12:41:06.917144 ===================================
3819 12:41:06.921073 ANA top config
3820 12:41:06.923808 ===================================
3821 12:41:06.927018 DLL_ASYNC_EN = 0
3822 12:41:06.927632 ALL_SLAVE_EN = 1
3823 12:41:06.930592 NEW_RANK_MODE = 1
3824 12:41:06.933657 DLL_IDLE_MODE = 1
3825 12:41:06.936831 LP45_APHY_COMB_EN = 1
3826 12:41:06.940184 TX_ODT_DIS = 1
3827 12:41:06.940660 NEW_8X_MODE = 1
3828 12:41:06.943371 ===================================
3829 12:41:06.947334 ===================================
3830 12:41:06.950011 data_rate = 1200
3831 12:41:06.953648 CKR = 1
3832 12:41:06.956925 DQ_P2S_RATIO = 8
3833 12:41:06.960100 ===================================
3834 12:41:06.963568 CA_P2S_RATIO = 8
3835 12:41:06.966982 DQ_CA_OPEN = 0
3836 12:41:06.967551 DQ_SEMI_OPEN = 0
3837 12:41:06.970423 CA_SEMI_OPEN = 0
3838 12:41:06.973566 CA_FULL_RATE = 0
3839 12:41:06.976770 DQ_CKDIV4_EN = 1
3840 12:41:06.980094 CA_CKDIV4_EN = 1
3841 12:41:06.983176 CA_PREDIV_EN = 0
3842 12:41:06.983745 PH8_DLY = 0
3843 12:41:06.986762 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3844 12:41:06.989878 DQ_AAMCK_DIV = 4
3845 12:41:06.993407 CA_AAMCK_DIV = 4
3846 12:41:06.996745 CA_ADMCK_DIV = 4
3847 12:41:06.999948 DQ_TRACK_CA_EN = 0
3848 12:41:07.000518 CA_PICK = 600
3849 12:41:07.003306 CA_MCKIO = 600
3850 12:41:07.006902 MCKIO_SEMI = 0
3851 12:41:07.010054 PLL_FREQ = 2288
3852 12:41:07.012749 DQ_UI_PI_RATIO = 32
3853 12:41:07.016212 CA_UI_PI_RATIO = 0
3854 12:41:07.019561 ===================================
3855 12:41:07.023051 ===================================
3856 12:41:07.026482 memory_type:LPDDR4
3857 12:41:07.026951 GP_NUM : 10
3858 12:41:07.029741 SRAM_EN : 1
3859 12:41:07.030207 MD32_EN : 0
3860 12:41:07.033244 ===================================
3861 12:41:07.036571 [ANA_INIT] >>>>>>>>>>>>>>
3862 12:41:07.039935 <<<<<< [CONFIGURE PHASE]: ANA_TX
3863 12:41:07.042674 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3864 12:41:07.046149 ===================================
3865 12:41:07.049275 data_rate = 1200,PCW = 0X5800
3866 12:41:07.052637 ===================================
3867 12:41:07.055633 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3868 12:41:07.062708 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3869 12:41:07.065637 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3870 12:41:07.072536 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3871 12:41:07.076049 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3872 12:41:07.079348 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3873 12:41:07.079918 [ANA_INIT] flow start
3874 12:41:07.082421 [ANA_INIT] PLL >>>>>>>>
3875 12:41:07.085503 [ANA_INIT] PLL <<<<<<<<
3876 12:41:07.086071 [ANA_INIT] MIDPI >>>>>>>>
3877 12:41:07.089359 [ANA_INIT] MIDPI <<<<<<<<
3878 12:41:07.092417 [ANA_INIT] DLL >>>>>>>>
3879 12:41:07.093006 [ANA_INIT] flow end
3880 12:41:07.099174 ============ LP4 DIFF to SE enter ============
3881 12:41:07.101903 ============ LP4 DIFF to SE exit ============
3882 12:41:07.105666 [ANA_INIT] <<<<<<<<<<<<<
3883 12:41:07.108888 [Flow] Enable top DCM control >>>>>
3884 12:41:07.112160 [Flow] Enable top DCM control <<<<<
3885 12:41:07.112806 Enable DLL master slave shuffle
3886 12:41:07.119028 ==============================================================
3887 12:41:07.121899 Gating Mode config
3888 12:41:07.125261 ==============================================================
3889 12:41:07.128755 Config description:
3890 12:41:07.138789 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3891 12:41:07.144889 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3892 12:41:07.148888 SELPH_MODE 0: By rank 1: By Phase
3893 12:41:07.154685 ==============================================================
3894 12:41:07.158376 GAT_TRACK_EN = 1
3895 12:41:07.161451 RX_GATING_MODE = 2
3896 12:41:07.165216 RX_GATING_TRACK_MODE = 2
3897 12:41:07.168419 SELPH_MODE = 1
3898 12:41:07.171625 PICG_EARLY_EN = 1
3899 12:41:07.172192 VALID_LAT_VALUE = 1
3900 12:41:07.178279 ==============================================================
3901 12:41:07.181374 Enter into Gating configuration >>>>
3902 12:41:07.185104 Exit from Gating configuration <<<<
3903 12:41:07.188341 Enter into DVFS_PRE_config >>>>>
3904 12:41:07.198029 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3905 12:41:07.201262 Exit from DVFS_PRE_config <<<<<
3906 12:41:07.204712 Enter into PICG configuration >>>>
3907 12:41:07.208026 Exit from PICG configuration <<<<
3908 12:41:07.211242 [RX_INPUT] configuration >>>>>
3909 12:41:07.214627 [RX_INPUT] configuration <<<<<
3910 12:41:07.221088 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3911 12:41:07.224358 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3912 12:41:07.230937 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3913 12:41:07.237909 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3914 12:41:07.244338 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3915 12:41:07.250593 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3916 12:41:07.254294 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3917 12:41:07.257299 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3918 12:41:07.261259 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3919 12:41:07.267092 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3920 12:41:07.270375 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3921 12:41:07.273952 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3922 12:41:07.277036 ===================================
3923 12:41:07.281319 LPDDR4 DRAM CONFIGURATION
3924 12:41:07.283913 ===================================
3925 12:41:07.284480 EX_ROW_EN[0] = 0x0
3926 12:41:07.287038 EX_ROW_EN[1] = 0x0
3927 12:41:07.290466 LP4Y_EN = 0x0
3928 12:41:07.291034 WORK_FSP = 0x0
3929 12:41:07.293806 WL = 0x2
3930 12:41:07.294366 RL = 0x2
3931 12:41:07.297053 BL = 0x2
3932 12:41:07.297524 RPST = 0x0
3933 12:41:07.300471 RD_PRE = 0x0
3934 12:41:07.301090 WR_PRE = 0x1
3935 12:41:07.303764 WR_PST = 0x0
3936 12:41:07.304329 DBI_WR = 0x0
3937 12:41:07.307281 DBI_RD = 0x0
3938 12:41:07.307849 OTF = 0x1
3939 12:41:07.310466 ===================================
3940 12:41:07.313624 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3941 12:41:07.320216 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3942 12:41:07.323442 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3943 12:41:07.326711 ===================================
3944 12:41:07.330327 LPDDR4 DRAM CONFIGURATION
3945 12:41:07.333430 ===================================
3946 12:41:07.333904 EX_ROW_EN[0] = 0x10
3947 12:41:07.336823 EX_ROW_EN[1] = 0x0
3948 12:41:07.340287 LP4Y_EN = 0x0
3949 12:41:07.340853 WORK_FSP = 0x0
3950 12:41:07.343914 WL = 0x2
3951 12:41:07.344475 RL = 0x2
3952 12:41:07.346617 BL = 0x2
3953 12:41:07.347086 RPST = 0x0
3954 12:41:07.349959 RD_PRE = 0x0
3955 12:41:07.350428 WR_PRE = 0x1
3956 12:41:07.353549 WR_PST = 0x0
3957 12:41:07.354111 DBI_WR = 0x0
3958 12:41:07.357030 DBI_RD = 0x0
3959 12:41:07.357621 OTF = 0x1
3960 12:41:07.359791 ===================================
3961 12:41:07.366604 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3962 12:41:07.371029 nWR fixed to 30
3963 12:41:07.374469 [ModeRegInit_LP4] CH0 RK0
3964 12:41:07.375039 [ModeRegInit_LP4] CH0 RK1
3965 12:41:07.377091 [ModeRegInit_LP4] CH1 RK0
3966 12:41:07.380462 [ModeRegInit_LP4] CH1 RK1
3967 12:41:07.380934 match AC timing 17
3968 12:41:07.387129 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3969 12:41:07.390363 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3970 12:41:07.394416 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3971 12:41:07.400907 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3972 12:41:07.403975 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3973 12:41:07.404557 ==
3974 12:41:07.407209 Dram Type= 6, Freq= 0, CH_0, rank 0
3975 12:41:07.410599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3976 12:41:07.411184 ==
3977 12:41:07.417159 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3978 12:41:07.423666 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3979 12:41:07.426747 [CA 0] Center 36 (6~67) winsize 62
3980 12:41:07.430265 [CA 1] Center 36 (6~67) winsize 62
3981 12:41:07.433405 [CA 2] Center 34 (4~65) winsize 62
3982 12:41:07.436870 [CA 3] Center 34 (4~65) winsize 62
3983 12:41:07.440033 [CA 4] Center 34 (3~65) winsize 63
3984 12:41:07.443228 [CA 5] Center 33 (2~64) winsize 63
3985 12:41:07.443805
3986 12:41:07.446237 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3987 12:41:07.446718
3988 12:41:07.449921 [CATrainingPosCal] consider 1 rank data
3989 12:41:07.453435 u2DelayCellTimex100 = 270/100 ps
3990 12:41:07.456607 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3991 12:41:07.459999 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3992 12:41:07.462979 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3993 12:41:07.469671 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3994 12:41:07.473267 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3995 12:41:07.476191 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3996 12:41:07.476768
3997 12:41:07.480093 CA PerBit enable=1, Macro0, CA PI delay=33
3998 12:41:07.480677
3999 12:41:07.482844 [CBTSetCACLKResult] CA Dly = 33
4000 12:41:07.483325 CS Dly: 5 (0~36)
4001 12:41:07.483800 ==
4002 12:41:07.486013 Dram Type= 6, Freq= 0, CH_0, rank 1
4003 12:41:07.493129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4004 12:41:07.493892 ==
4005 12:41:07.496095 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4006 12:41:07.502534 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4007 12:41:07.506167 [CA 0] Center 36 (6~67) winsize 62
4008 12:41:07.509633 [CA 1] Center 36 (6~67) winsize 62
4009 12:41:07.512692 [CA 2] Center 34 (4~65) winsize 62
4010 12:41:07.516294 [CA 3] Center 34 (4~65) winsize 62
4011 12:41:07.519387 [CA 4] Center 34 (3~65) winsize 63
4012 12:41:07.522713 [CA 5] Center 33 (3~64) winsize 62
4013 12:41:07.523277
4014 12:41:07.525948 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4015 12:41:07.526522
4016 12:41:07.529711 [CATrainingPosCal] consider 2 rank data
4017 12:41:07.532444 u2DelayCellTimex100 = 270/100 ps
4018 12:41:07.535974 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4019 12:41:07.541993 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4020 12:41:07.545776 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4021 12:41:07.549079 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4022 12:41:07.552316 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4023 12:41:07.555490 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4024 12:41:07.556070
4025 12:41:07.558584 CA PerBit enable=1, Macro0, CA PI delay=33
4026 12:41:07.559061
4027 12:41:07.562177 [CBTSetCACLKResult] CA Dly = 33
4028 12:41:07.565369 CS Dly: 5 (0~36)
4029 12:41:07.565944
4030 12:41:07.568954 ----->DramcWriteLeveling(PI) begin...
4031 12:41:07.569567 ==
4032 12:41:07.572450 Dram Type= 6, Freq= 0, CH_0, rank 0
4033 12:41:07.575348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4034 12:41:07.575932 ==
4035 12:41:07.578904 Write leveling (Byte 0): 34 => 34
4036 12:41:07.581660 Write leveling (Byte 1): 30 => 30
4037 12:41:07.584675 DramcWriteLeveling(PI) end<-----
4038 12:41:07.585191
4039 12:41:07.585573 ==
4040 12:41:07.588139 Dram Type= 6, Freq= 0, CH_0, rank 0
4041 12:41:07.591277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4042 12:41:07.591752 ==
4043 12:41:07.595457 [Gating] SW mode calibration
4044 12:41:07.601601 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4045 12:41:07.608280 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4046 12:41:07.611341 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4047 12:41:07.617851 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4048 12:41:07.621551 0 9 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
4049 12:41:07.624306 0 9 12 | B1->B0 | 3434 2d2d | 0 0 | (0 0) (0 0)
4050 12:41:07.630892 0 9 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4051 12:41:07.634216 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4052 12:41:07.637858 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4053 12:41:07.644820 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4054 12:41:07.647735 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4055 12:41:07.650944 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4056 12:41:07.657878 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4057 12:41:07.661082 0 10 12 | B1->B0 | 2424 3939 | 0 1 | (0 0) (0 0)
4058 12:41:07.663985 0 10 16 | B1->B0 | 4141 4646 | 0 0 | (1 1) (0 0)
4059 12:41:07.670663 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 12:41:07.673899 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4061 12:41:07.677581 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4062 12:41:07.684208 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 12:41:07.687054 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 12:41:07.690475 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 12:41:07.697201 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4066 12:41:07.700757 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4067 12:41:07.703913 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 12:41:07.707051 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 12:41:07.713865 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 12:41:07.717067 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 12:41:07.720424 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 12:41:07.727346 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 12:41:07.730613 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 12:41:07.733596 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 12:41:07.740446 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 12:41:07.743550 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 12:41:07.746807 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 12:41:07.753911 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 12:41:07.757006 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 12:41:07.760294 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 12:41:07.767117 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4082 12:41:07.770234 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4083 12:41:07.773729 Total UI for P1: 0, mck2ui 16
4084 12:41:07.777144 best dqsien dly found for B0: ( 0, 13, 12)
4085 12:41:07.780532 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4086 12:41:07.783381 Total UI for P1: 0, mck2ui 16
4087 12:41:07.786647 best dqsien dly found for B1: ( 0, 13, 16)
4088 12:41:07.790013 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4089 12:41:07.793434 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4090 12:41:07.793999
4091 12:41:07.799705 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4092 12:41:07.803143 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4093 12:41:07.806247 [Gating] SW calibration Done
4094 12:41:07.806730 ==
4095 12:41:07.809815 Dram Type= 6, Freq= 0, CH_0, rank 0
4096 12:41:07.813271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4097 12:41:07.813900 ==
4098 12:41:07.814279 RX Vref Scan: 0
4099 12:41:07.814627
4100 12:41:07.816494 RX Vref 0 -> 0, step: 1
4101 12:41:07.816963
4102 12:41:07.819801 RX Delay -230 -> 252, step: 16
4103 12:41:07.823365 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4104 12:41:07.829828 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4105 12:41:07.832859 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4106 12:41:07.836130 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4107 12:41:07.839439 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4108 12:41:07.843015 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4109 12:41:07.849176 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4110 12:41:07.852918 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4111 12:41:07.855863 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4112 12:41:07.859292 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4113 12:41:07.865875 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4114 12:41:07.869413 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4115 12:41:07.872759 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4116 12:41:07.876533 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4117 12:41:07.882822 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4118 12:41:07.885839 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4119 12:41:07.886430 ==
4120 12:41:07.889288 Dram Type= 6, Freq= 0, CH_0, rank 0
4121 12:41:07.892307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4122 12:41:07.892884 ==
4123 12:41:07.895821 DQS Delay:
4124 12:41:07.896400 DQS0 = 0, DQS1 = 0
4125 12:41:07.896779 DQM Delay:
4126 12:41:07.899238 DQM0 = 51, DQM1 = 38
4127 12:41:07.899830 DQ Delay:
4128 12:41:07.902506 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =41
4129 12:41:07.905941 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4130 12:41:07.909150 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =25
4131 12:41:07.912207 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =49
4132 12:41:07.912778
4133 12:41:07.913199
4134 12:41:07.913555 ==
4135 12:41:07.915465 Dram Type= 6, Freq= 0, CH_0, rank 0
4136 12:41:07.921869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4137 12:41:07.922421 ==
4138 12:41:07.922792
4139 12:41:07.923134
4140 12:41:07.923467 TX Vref Scan disable
4141 12:41:07.925877 == TX Byte 0 ==
4142 12:41:07.929208 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4143 12:41:07.935803 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4144 12:41:07.936361 == TX Byte 1 ==
4145 12:41:07.939380 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4146 12:41:07.945536 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4147 12:41:07.946011 ==
4148 12:41:07.948758 Dram Type= 6, Freq= 0, CH_0, rank 0
4149 12:41:07.952357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4150 12:41:07.952922 ==
4151 12:41:07.953346
4152 12:41:07.953693
4153 12:41:07.955827 TX Vref Scan disable
4154 12:41:07.958690 == TX Byte 0 ==
4155 12:41:07.962543 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4156 12:41:07.965731 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4157 12:41:07.969058 == TX Byte 1 ==
4158 12:41:07.972366 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4159 12:41:07.975781 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4160 12:41:07.976350
4161 12:41:07.976723 [DATLAT]
4162 12:41:07.979176 Freq=600, CH0 RK0
4163 12:41:07.979754
4164 12:41:07.982550 DATLAT Default: 0x9
4165 12:41:07.983021 0, 0xFFFF, sum = 0
4166 12:41:07.985902 1, 0xFFFF, sum = 0
4167 12:41:07.986479 2, 0xFFFF, sum = 0
4168 12:41:07.988869 3, 0xFFFF, sum = 0
4169 12:41:07.989495 4, 0xFFFF, sum = 0
4170 12:41:07.992265 5, 0xFFFF, sum = 0
4171 12:41:07.992831 6, 0xFFFF, sum = 0
4172 12:41:07.995635 7, 0xFFFF, sum = 0
4173 12:41:07.996204 8, 0x0, sum = 1
4174 12:41:07.998940 9, 0x0, sum = 2
4175 12:41:07.999513 10, 0x0, sum = 3
4176 12:41:07.999924 11, 0x0, sum = 4
4177 12:41:08.001953 best_step = 9
4178 12:41:08.002421
4179 12:41:08.002792 ==
4180 12:41:08.005044 Dram Type= 6, Freq= 0, CH_0, rank 0
4181 12:41:08.008732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4182 12:41:08.009357 ==
4183 12:41:08.011939 RX Vref Scan: 1
4184 12:41:08.012410
4185 12:41:08.015297 RX Vref 0 -> 0, step: 1
4186 12:41:08.015858
4187 12:41:08.016232 RX Delay -179 -> 252, step: 8
4188 12:41:08.016580
4189 12:41:08.018621 Set Vref, RX VrefLevel [Byte0]: 57
4190 12:41:08.021881 [Byte1]: 49
4191 12:41:08.026416
4192 12:41:08.026999 Final RX Vref Byte 0 = 57 to rank0
4193 12:41:08.029703 Final RX Vref Byte 1 = 49 to rank0
4194 12:41:08.032835 Final RX Vref Byte 0 = 57 to rank1
4195 12:41:08.036576 Final RX Vref Byte 1 = 49 to rank1==
4196 12:41:08.039718 Dram Type= 6, Freq= 0, CH_0, rank 0
4197 12:41:08.046203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4198 12:41:08.046801 ==
4199 12:41:08.047177 DQS Delay:
4200 12:41:08.049365 DQS0 = 0, DQS1 = 0
4201 12:41:08.049835 DQM Delay:
4202 12:41:08.050202 DQM0 = 50, DQM1 = 36
4203 12:41:08.052751 DQ Delay:
4204 12:41:08.056116 DQ0 =44, DQ1 =52, DQ2 =44, DQ3 =44
4205 12:41:08.059196 DQ4 =52, DQ5 =40, DQ6 =64, DQ7 =60
4206 12:41:08.062909 DQ8 =32, DQ9 =20, DQ10 =36, DQ11 =32
4207 12:41:08.066331 DQ12 =40, DQ13 =40, DQ14 =48, DQ15 =44
4208 12:41:08.066904
4209 12:41:08.067278
4210 12:41:08.072535 [DQSOSCAuto] RK0, (LSB)MR18= 0x5a54, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4211 12:41:08.076002 CH0 RK0: MR19=808, MR18=5A54
4212 12:41:08.082436 CH0_RK0: MR19=0x808, MR18=0x5A54, DQSOSC=392, MR23=63, INC=170, DEC=113
4213 12:41:08.083010
4214 12:41:08.085593 ----->DramcWriteLeveling(PI) begin...
4215 12:41:08.086173 ==
4216 12:41:08.088739 Dram Type= 6, Freq= 0, CH_0, rank 1
4217 12:41:08.092846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4218 12:41:08.093492 ==
4219 12:41:08.095630 Write leveling (Byte 0): 35 => 35
4220 12:41:08.099322 Write leveling (Byte 1): 29 => 29
4221 12:41:08.102195 DramcWriteLeveling(PI) end<-----
4222 12:41:08.102836
4223 12:41:08.103214 ==
4224 12:41:08.105613 Dram Type= 6, Freq= 0, CH_0, rank 1
4225 12:41:08.108869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4226 12:41:08.112218 ==
4227 12:41:08.112832 [Gating] SW mode calibration
4228 12:41:08.122040 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4229 12:41:08.125238 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4230 12:41:08.128487 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4231 12:41:08.134739 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4232 12:41:08.138415 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4233 12:41:08.141935 0 9 12 | B1->B0 | 3333 3333 | 0 1 | (0 1) (0 1)
4234 12:41:08.148478 0 9 16 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
4235 12:41:08.151965 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 12:41:08.155147 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4237 12:41:08.161912 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4238 12:41:08.164803 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 12:41:08.168478 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 12:41:08.174927 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 12:41:08.178248 0 10 12 | B1->B0 | 2f2f 3232 | 0 0 | (0 0) (1 1)
4242 12:41:08.181470 0 10 16 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
4243 12:41:08.188087 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 12:41:08.191395 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 12:41:08.194883 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 12:41:08.201369 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 12:41:08.204798 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 12:41:08.208192 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 12:41:08.214690 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4250 12:41:08.218239 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 12:41:08.221562 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 12:41:08.227852 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 12:41:08.231437 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 12:41:08.234939 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 12:41:08.241277 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 12:41:08.244566 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 12:41:08.247803 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 12:41:08.254504 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 12:41:08.257776 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 12:41:08.261373 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 12:41:08.264852 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 12:41:08.271602 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 12:41:08.274937 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 12:41:08.278158 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4265 12:41:08.284844 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4266 12:41:08.287466 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4267 12:41:08.290997 Total UI for P1: 0, mck2ui 16
4268 12:41:08.294561 best dqsien dly found for B0: ( 0, 13, 10)
4269 12:41:08.297860 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4270 12:41:08.300913 Total UI for P1: 0, mck2ui 16
4271 12:41:08.304486 best dqsien dly found for B1: ( 0, 13, 12)
4272 12:41:08.307719 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4273 12:41:08.314173 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4274 12:41:08.314746
4275 12:41:08.317490 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4276 12:41:08.320808 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4277 12:41:08.324177 [Gating] SW calibration Done
4278 12:41:08.324740 ==
4279 12:41:08.327379 Dram Type= 6, Freq= 0, CH_0, rank 1
4280 12:41:08.330691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4281 12:41:08.331261 ==
4282 12:41:08.333742 RX Vref Scan: 0
4283 12:41:08.334307
4284 12:41:08.334685 RX Vref 0 -> 0, step: 1
4285 12:41:08.335037
4286 12:41:08.337124 RX Delay -230 -> 252, step: 16
4287 12:41:08.340549 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4288 12:41:08.347030 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4289 12:41:08.350464 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4290 12:41:08.354128 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4291 12:41:08.356917 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4292 12:41:08.363860 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4293 12:41:08.367255 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4294 12:41:08.370262 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4295 12:41:08.374065 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4296 12:41:08.377126 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4297 12:41:08.383304 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4298 12:41:08.387066 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4299 12:41:08.390041 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4300 12:41:08.393431 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4301 12:41:08.400093 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4302 12:41:08.403066 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4303 12:41:08.403545 ==
4304 12:41:08.406893 Dram Type= 6, Freq= 0, CH_0, rank 1
4305 12:41:08.409984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4306 12:41:08.410458 ==
4307 12:41:08.413482 DQS Delay:
4308 12:41:08.414051 DQS0 = 0, DQS1 = 0
4309 12:41:08.416822 DQM Delay:
4310 12:41:08.417340 DQM0 = 51, DQM1 = 41
4311 12:41:08.417781 DQ Delay:
4312 12:41:08.419679 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4313 12:41:08.423267 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =57
4314 12:41:08.426459 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4315 12:41:08.429666 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =49
4316 12:41:08.430236
4317 12:41:08.430613
4318 12:41:08.433031 ==
4319 12:41:08.433598 Dram Type= 6, Freq= 0, CH_0, rank 1
4320 12:41:08.439610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4321 12:41:08.440171 ==
4322 12:41:08.440550
4323 12:41:08.440898
4324 12:41:08.442704 TX Vref Scan disable
4325 12:41:08.443182 == TX Byte 0 ==
4326 12:41:08.449342 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4327 12:41:08.452732 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4328 12:41:08.453301 == TX Byte 1 ==
4329 12:41:08.459583 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4330 12:41:08.462779 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4331 12:41:08.463269 ==
4332 12:41:08.465977 Dram Type= 6, Freq= 0, CH_0, rank 1
4333 12:41:08.469334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4334 12:41:08.469957 ==
4335 12:41:08.470354
4336 12:41:08.470705
4337 12:41:08.472570 TX Vref Scan disable
4338 12:41:08.475999 == TX Byte 0 ==
4339 12:41:08.479460 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4340 12:41:08.482873 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4341 12:41:08.486187 == TX Byte 1 ==
4342 12:41:08.489269 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4343 12:41:08.492861 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4344 12:41:08.493470
4345 12:41:08.495890 [DATLAT]
4346 12:41:08.496452 Freq=600, CH0 RK1
4347 12:41:08.496828
4348 12:41:08.499304 DATLAT Default: 0x9
4349 12:41:08.499869 0, 0xFFFF, sum = 0
4350 12:41:08.502494 1, 0xFFFF, sum = 0
4351 12:41:08.503064 2, 0xFFFF, sum = 0
4352 12:41:08.506054 3, 0xFFFF, sum = 0
4353 12:41:08.506530 4, 0xFFFF, sum = 0
4354 12:41:08.509078 5, 0xFFFF, sum = 0
4355 12:41:08.509655 6, 0xFFFF, sum = 0
4356 12:41:08.512205 7, 0xFFFF, sum = 0
4357 12:41:08.512683 8, 0x0, sum = 1
4358 12:41:08.515654 9, 0x0, sum = 2
4359 12:41:08.516125 10, 0x0, sum = 3
4360 12:41:08.518905 11, 0x0, sum = 4
4361 12:41:08.519367 best_step = 9
4362 12:41:08.519726
4363 12:41:08.520059 ==
4364 12:41:08.522273 Dram Type= 6, Freq= 0, CH_0, rank 1
4365 12:41:08.528643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4366 12:41:08.529134 ==
4367 12:41:08.529498 RX Vref Scan: 0
4368 12:41:08.529834
4369 12:41:08.531984 RX Vref 0 -> 0, step: 1
4370 12:41:08.532439
4371 12:41:08.535421 RX Delay -163 -> 252, step: 8
4372 12:41:08.538593 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4373 12:41:08.545273 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4374 12:41:08.548473 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4375 12:41:08.551798 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4376 12:41:08.555127 iDelay=205, Bit 4, Center 52 (-91 ~ 196) 288
4377 12:41:08.558500 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4378 12:41:08.564948 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4379 12:41:08.568349 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4380 12:41:08.571767 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4381 12:41:08.574913 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4382 12:41:08.581800 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4383 12:41:08.585061 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4384 12:41:08.588189 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4385 12:41:08.591778 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280
4386 12:41:08.594811 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4387 12:41:08.601679 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4388 12:41:08.602237 ==
4389 12:41:08.605062 Dram Type= 6, Freq= 0, CH_0, rank 1
4390 12:41:08.607974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4391 12:41:08.608526 ==
4392 12:41:08.608888 DQS Delay:
4393 12:41:08.611167 DQS0 = 0, DQS1 = 0
4394 12:41:08.611659 DQM Delay:
4395 12:41:08.614348 DQM0 = 48, DQM1 = 42
4396 12:41:08.614809 DQ Delay:
4397 12:41:08.617787 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4398 12:41:08.621134 DQ4 =52, DQ5 =40, DQ6 =56, DQ7 =56
4399 12:41:08.624920 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =36
4400 12:41:08.627775 DQ12 =48, DQ13 =48, DQ14 =52, DQ15 =52
4401 12:41:08.628330
4402 12:41:08.628686
4403 12:41:08.637413 [DQSOSCAuto] RK1, (LSB)MR18= 0x6634, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
4404 12:41:08.637970 CH0 RK1: MR19=808, MR18=6634
4405 12:41:08.644432 CH0_RK1: MR19=0x808, MR18=0x6634, DQSOSC=390, MR23=63, INC=172, DEC=114
4406 12:41:08.647246 [RxdqsGatingPostProcess] freq 600
4407 12:41:08.653916 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4408 12:41:08.657075 Pre-setting of DQS Precalculation
4409 12:41:08.660678 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4410 12:41:08.661301 ==
4411 12:41:08.663784 Dram Type= 6, Freq= 0, CH_1, rank 0
4412 12:41:08.670098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4413 12:41:08.670566 ==
4414 12:41:08.673684 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4415 12:41:08.680216 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4416 12:41:08.683823 [CA 0] Center 35 (5~66) winsize 62
4417 12:41:08.687102 [CA 1] Center 35 (5~66) winsize 62
4418 12:41:08.690456 [CA 2] Center 34 (3~65) winsize 63
4419 12:41:08.693587 [CA 3] Center 33 (3~64) winsize 62
4420 12:41:08.696789 [CA 4] Center 33 (3~64) winsize 62
4421 12:41:08.700229 [CA 5] Center 33 (3~64) winsize 62
4422 12:41:08.700781
4423 12:41:08.703562 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4424 12:41:08.704115
4425 12:41:08.706790 [CATrainingPosCal] consider 1 rank data
4426 12:41:08.710078 u2DelayCellTimex100 = 270/100 ps
4427 12:41:08.713468 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4428 12:41:08.719820 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4429 12:41:08.723451 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4430 12:41:08.726718 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4431 12:41:08.729793 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4432 12:41:08.733092 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4433 12:41:08.733647
4434 12:41:08.736820 CA PerBit enable=1, Macro0, CA PI delay=33
4435 12:41:08.737437
4436 12:41:08.739539 [CBTSetCACLKResult] CA Dly = 33
4437 12:41:08.743142 CS Dly: 5 (0~36)
4438 12:41:08.743705 ==
4439 12:41:08.746587 Dram Type= 6, Freq= 0, CH_1, rank 1
4440 12:41:08.749685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4441 12:41:08.750147 ==
4442 12:41:08.756293 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4443 12:41:08.759756 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4444 12:41:08.763635 [CA 0] Center 35 (5~66) winsize 62
4445 12:41:08.766790 [CA 1] Center 35 (5~66) winsize 62
4446 12:41:08.770555 [CA 2] Center 34 (4~65) winsize 62
4447 12:41:08.773599 [CA 3] Center 34 (4~65) winsize 62
4448 12:41:08.777162 [CA 4] Center 34 (4~65) winsize 62
4449 12:41:08.780373 [CA 5] Center 33 (3~64) winsize 62
4450 12:41:08.780826
4451 12:41:08.783611 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4452 12:41:08.784201
4453 12:41:08.787215 [CATrainingPosCal] consider 2 rank data
4454 12:41:08.789953 u2DelayCellTimex100 = 270/100 ps
4455 12:41:08.793294 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4456 12:41:08.800116 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4457 12:41:08.803394 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4458 12:41:08.806476 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4459 12:41:08.809988 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4460 12:41:08.813424 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4461 12:41:08.813992
4462 12:41:08.816497 CA PerBit enable=1, Macro0, CA PI delay=33
4463 12:41:08.816965
4464 12:41:08.819806 [CBTSetCACLKResult] CA Dly = 33
4465 12:41:08.823303 CS Dly: 5 (0~36)
4466 12:41:08.823868
4467 12:41:08.826597 ----->DramcWriteLeveling(PI) begin...
4468 12:41:08.827189 ==
4469 12:41:08.829623 Dram Type= 6, Freq= 0, CH_1, rank 0
4470 12:41:08.833439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4471 12:41:08.834010 ==
4472 12:41:08.836047 Write leveling (Byte 0): 30 => 30
4473 12:41:08.839468 Write leveling (Byte 1): 31 => 31
4474 12:41:08.843423 DramcWriteLeveling(PI) end<-----
4475 12:41:08.843991
4476 12:41:08.844367 ==
4477 12:41:08.846235 Dram Type= 6, Freq= 0, CH_1, rank 0
4478 12:41:08.849712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4479 12:41:08.850285 ==
4480 12:41:08.853027 [Gating] SW mode calibration
4481 12:41:08.859435 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4482 12:41:08.866428 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4483 12:41:08.869415 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4484 12:41:08.872579 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4485 12:41:08.879404 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4486 12:41:08.882464 0 9 12 | B1->B0 | 2f2f 2d2d | 0 0 | (0 0) (1 1)
4487 12:41:08.885967 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4488 12:41:08.893086 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4489 12:41:08.895996 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4490 12:41:08.899322 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4491 12:41:08.905514 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4492 12:41:08.909015 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4493 12:41:08.912442 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4494 12:41:08.918598 0 10 12 | B1->B0 | 3b3b 3d3d | 0 0 | (0 0) (0 0)
4495 12:41:08.922089 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 12:41:08.925858 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4497 12:41:08.932309 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4498 12:41:08.935470 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4499 12:41:08.938599 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 12:41:08.945600 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 12:41:08.948941 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 12:41:08.951874 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4503 12:41:08.958450 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 12:41:08.962027 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 12:41:08.965516 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 12:41:08.971763 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 12:41:08.975059 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 12:41:08.978142 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 12:41:08.985151 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 12:41:08.988120 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 12:41:08.991229 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 12:41:08.998248 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 12:41:09.001867 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 12:41:09.005029 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 12:41:09.011378 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 12:41:09.014858 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 12:41:09.017658 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4518 12:41:09.024860 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4519 12:41:09.025460 Total UI for P1: 0, mck2ui 16
4520 12:41:09.030902 best dqsien dly found for B0: ( 0, 13, 8)
4521 12:41:09.031466 Total UI for P1: 0, mck2ui 16
4522 12:41:09.037902 best dqsien dly found for B1: ( 0, 13, 8)
4523 12:41:09.040940 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4524 12:41:09.044461 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4525 12:41:09.045061
4526 12:41:09.047867 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4527 12:41:09.050729 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4528 12:41:09.054574 [Gating] SW calibration Done
4529 12:41:09.055141 ==
4530 12:41:09.057942 Dram Type= 6, Freq= 0, CH_1, rank 0
4531 12:41:09.061087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4532 12:41:09.061655 ==
4533 12:41:09.064512 RX Vref Scan: 0
4534 12:41:09.065116
4535 12:41:09.065492 RX Vref 0 -> 0, step: 1
4536 12:41:09.065840
4537 12:41:09.067734 RX Delay -230 -> 252, step: 16
4538 12:41:09.070890 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4539 12:41:09.077912 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4540 12:41:09.080847 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4541 12:41:09.084268 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4542 12:41:09.087327 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4543 12:41:09.094013 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4544 12:41:09.097312 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4545 12:41:09.101058 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4546 12:41:09.104120 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4547 12:41:09.107068 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4548 12:41:09.113580 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4549 12:41:09.116698 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4550 12:41:09.120119 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4551 12:41:09.126947 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4552 12:41:09.130040 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4553 12:41:09.133515 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4554 12:41:09.133983 ==
4555 12:41:09.136647 Dram Type= 6, Freq= 0, CH_1, rank 0
4556 12:41:09.140018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4557 12:41:09.140485 ==
4558 12:41:09.143648 DQS Delay:
4559 12:41:09.144215 DQS0 = 0, DQS1 = 0
4560 12:41:09.146530 DQM Delay:
4561 12:41:09.146996 DQM0 = 51, DQM1 = 42
4562 12:41:09.147363 DQ Delay:
4563 12:41:09.150081 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4564 12:41:09.153429 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4565 12:41:09.157012 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4566 12:41:09.160074 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =49
4567 12:41:09.160639
4568 12:41:09.161045
4569 12:41:09.162760 ==
4570 12:41:09.166455 Dram Type= 6, Freq= 0, CH_1, rank 0
4571 12:41:09.169865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4572 12:41:09.170437 ==
4573 12:41:09.170812
4574 12:41:09.171149
4575 12:41:09.173410 TX Vref Scan disable
4576 12:41:09.173976 == TX Byte 0 ==
4577 12:41:09.179808 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4578 12:41:09.183634 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4579 12:41:09.184206 == TX Byte 1 ==
4580 12:41:09.189533 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4581 12:41:09.193126 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4582 12:41:09.193698 ==
4583 12:41:09.196198 Dram Type= 6, Freq= 0, CH_1, rank 0
4584 12:41:09.199479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4585 12:41:09.200047 ==
4586 12:41:09.200421
4587 12:41:09.200763
4588 12:41:09.202866 TX Vref Scan disable
4589 12:41:09.206311 == TX Byte 0 ==
4590 12:41:09.209506 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4591 12:41:09.213051 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4592 12:41:09.215714 == TX Byte 1 ==
4593 12:41:09.219075 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4594 12:41:09.222407 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4595 12:41:09.223022
4596 12:41:09.225569 [DATLAT]
4597 12:41:09.226033 Freq=600, CH1 RK0
4598 12:41:09.226403
4599 12:41:09.229373 DATLAT Default: 0x9
4600 12:41:09.229940 0, 0xFFFF, sum = 0
4601 12:41:09.232183 1, 0xFFFF, sum = 0
4602 12:41:09.232654 2, 0xFFFF, sum = 0
4603 12:41:09.235688 3, 0xFFFF, sum = 0
4604 12:41:09.236163 4, 0xFFFF, sum = 0
4605 12:41:09.238575 5, 0xFFFF, sum = 0
4606 12:41:09.241971 6, 0xFFFF, sum = 0
4607 12:41:09.242485 7, 0xFFFF, sum = 0
4608 12:41:09.245362 8, 0x0, sum = 1
4609 12:41:09.245834 9, 0x0, sum = 2
4610 12:41:09.246213 10, 0x0, sum = 3
4611 12:41:09.249166 11, 0x0, sum = 4
4612 12:41:09.249732 best_step = 9
4613 12:41:09.250125
4614 12:41:09.250466 ==
4615 12:41:09.252443 Dram Type= 6, Freq= 0, CH_1, rank 0
4616 12:41:09.258437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4617 12:41:09.258910 ==
4618 12:41:09.259277 RX Vref Scan: 1
4619 12:41:09.259618
4620 12:41:09.261768 RX Vref 0 -> 0, step: 1
4621 12:41:09.262334
4622 12:41:09.265528 RX Delay -163 -> 252, step: 8
4623 12:41:09.266095
4624 12:41:09.268571 Set Vref, RX VrefLevel [Byte0]: 53
4625 12:41:09.271993 [Byte1]: 53
4626 12:41:09.272564
4627 12:41:09.275129 Final RX Vref Byte 0 = 53 to rank0
4628 12:41:09.278469 Final RX Vref Byte 1 = 53 to rank0
4629 12:41:09.281862 Final RX Vref Byte 0 = 53 to rank1
4630 12:41:09.284869 Final RX Vref Byte 1 = 53 to rank1==
4631 12:41:09.288536 Dram Type= 6, Freq= 0, CH_1, rank 0
4632 12:41:09.291829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4633 12:41:09.292396 ==
4634 12:41:09.294882 DQS Delay:
4635 12:41:09.295444 DQS0 = 0, DQS1 = 0
4636 12:41:09.298345 DQM Delay:
4637 12:41:09.298912 DQM0 = 47, DQM1 = 40
4638 12:41:09.301424 DQ Delay:
4639 12:41:09.301885 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4640 12:41:09.304638 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =44
4641 12:41:09.308210 DQ8 =28, DQ9 =24, DQ10 =44, DQ11 =32
4642 12:41:09.311439 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4643 12:41:09.312006
4644 12:41:09.314987
4645 12:41:09.321078 [DQSOSCAuto] RK0, (LSB)MR18= 0x5076, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
4646 12:41:09.324470 CH1 RK0: MR19=808, MR18=5076
4647 12:41:09.331259 CH1_RK0: MR19=0x808, MR18=0x5076, DQSOSC=387, MR23=63, INC=175, DEC=116
4648 12:41:09.331731
4649 12:41:09.334593 ----->DramcWriteLeveling(PI) begin...
4650 12:41:09.335155 ==
4651 12:41:09.337817 Dram Type= 6, Freq= 0, CH_1, rank 1
4652 12:41:09.340857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4653 12:41:09.341388 ==
4654 12:41:09.344274 Write leveling (Byte 0): 29 => 29
4655 12:41:09.347930 Write leveling (Byte 1): 29 => 29
4656 12:41:09.350861 DramcWriteLeveling(PI) end<-----
4657 12:41:09.351330
4658 12:41:09.351696 ==
4659 12:41:09.354102 Dram Type= 6, Freq= 0, CH_1, rank 1
4660 12:41:09.357581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4661 12:41:09.358155 ==
4662 12:41:09.360935 [Gating] SW mode calibration
4663 12:41:09.367607 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4664 12:41:09.373774 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4665 12:41:09.377588 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4666 12:41:09.383933 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4667 12:41:09.387361 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4668 12:41:09.390520 0 9 12 | B1->B0 | 2c2c 2f2f | 0 0 | (0 0) (0 0)
4669 12:41:09.393845 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4670 12:41:09.400505 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4671 12:41:09.403837 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4672 12:41:09.407211 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4673 12:41:09.413658 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4674 12:41:09.417285 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4675 12:41:09.420220 0 10 8 | B1->B0 | 2525 2323 | 1 0 | (0 0) (0 0)
4676 12:41:09.427739 0 10 12 | B1->B0 | 3838 2d2d | 0 0 | (0 0) (0 0)
4677 12:41:09.430020 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4678 12:41:09.433629 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4679 12:41:09.439949 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4680 12:41:09.443298 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 12:41:09.446829 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4682 12:41:09.453163 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 12:41:09.456536 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 12:41:09.459945 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4685 12:41:09.466644 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 12:41:09.470402 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 12:41:09.473231 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 12:41:09.480230 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 12:41:09.483367 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 12:41:09.486355 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 12:41:09.492889 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 12:41:09.496483 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 12:41:09.499321 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 12:41:09.506694 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 12:41:09.509692 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 12:41:09.512926 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 12:41:09.519280 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 12:41:09.522489 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 12:41:09.526089 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4700 12:41:09.533122 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4701 12:41:09.536204 Total UI for P1: 0, mck2ui 16
4702 12:41:09.539121 best dqsien dly found for B0: ( 0, 13, 8)
4703 12:41:09.542545 Total UI for P1: 0, mck2ui 16
4704 12:41:09.545623 best dqsien dly found for B1: ( 0, 13, 8)
4705 12:41:09.548751 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4706 12:41:09.552073 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4707 12:41:09.552541
4708 12:41:09.555570 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4709 12:41:09.559020 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4710 12:41:09.562334 [Gating] SW calibration Done
4711 12:41:09.562802 ==
4712 12:41:09.565769 Dram Type= 6, Freq= 0, CH_1, rank 1
4713 12:41:09.569063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4714 12:41:09.569534 ==
4715 12:41:09.572533 RX Vref Scan: 0
4716 12:41:09.573136
4717 12:41:09.573516 RX Vref 0 -> 0, step: 1
4718 12:41:09.573859
4719 12:41:09.575636 RX Delay -230 -> 252, step: 16
4720 12:41:09.582295 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4721 12:41:09.585672 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4722 12:41:09.588841 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4723 12:41:09.591922 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4724 12:41:09.595387 iDelay=218, Bit 4, Center 57 (-86 ~ 201) 288
4725 12:41:09.601935 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4726 12:41:09.605800 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4727 12:41:09.608884 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4728 12:41:09.612158 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4729 12:41:09.618879 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4730 12:41:09.621859 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4731 12:41:09.625140 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4732 12:41:09.628516 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4733 12:41:09.635122 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4734 12:41:09.638295 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4735 12:41:09.641818 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4736 12:41:09.642604 ==
4737 12:41:09.644809 Dram Type= 6, Freq= 0, CH_1, rank 1
4738 12:41:09.648356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4739 12:41:09.648829 ==
4740 12:41:09.651360 DQS Delay:
4741 12:41:09.651837 DQS0 = 0, DQS1 = 0
4742 12:41:09.655163 DQM Delay:
4743 12:41:09.655747 DQM0 = 52, DQM1 = 47
4744 12:41:09.656130 DQ Delay:
4745 12:41:09.657895 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4746 12:41:09.661165 DQ4 =57, DQ5 =65, DQ6 =57, DQ7 =49
4747 12:41:09.664348 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4748 12:41:09.668003 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =65
4749 12:41:09.668641
4750 12:41:09.669078
4751 12:41:09.671596 ==
4752 12:41:09.674655 Dram Type= 6, Freq= 0, CH_1, rank 1
4753 12:41:09.678110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4754 12:41:09.678754 ==
4755 12:41:09.679137
4756 12:41:09.679483
4757 12:41:09.681151 TX Vref Scan disable
4758 12:41:09.681719 == TX Byte 0 ==
4759 12:41:09.687980 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4760 12:41:09.690963 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4761 12:41:09.691441 == TX Byte 1 ==
4762 12:41:09.697923 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4763 12:41:09.701450 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4764 12:41:09.702016 ==
4765 12:41:09.704420 Dram Type= 6, Freq= 0, CH_1, rank 1
4766 12:41:09.707777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4767 12:41:09.708256 ==
4768 12:41:09.708638
4769 12:41:09.709011
4770 12:41:09.711273 TX Vref Scan disable
4771 12:41:09.714333 == TX Byte 0 ==
4772 12:41:09.717928 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4773 12:41:09.720878 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4774 12:41:09.724663 == TX Byte 1 ==
4775 12:41:09.727969 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4776 12:41:09.730898 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4777 12:41:09.731377
4778 12:41:09.733984 [DATLAT]
4779 12:41:09.734456 Freq=600, CH1 RK1
4780 12:41:09.734835
4781 12:41:09.737495 DATLAT Default: 0x9
4782 12:41:09.738061 0, 0xFFFF, sum = 0
4783 12:41:09.740715 1, 0xFFFF, sum = 0
4784 12:41:09.741228 2, 0xFFFF, sum = 0
4785 12:41:09.743907 3, 0xFFFF, sum = 0
4786 12:41:09.744558 4, 0xFFFF, sum = 0
4787 12:41:09.747716 5, 0xFFFF, sum = 0
4788 12:41:09.748289 6, 0xFFFF, sum = 0
4789 12:41:09.750778 7, 0xFFFF, sum = 0
4790 12:41:09.751376 8, 0x0, sum = 1
4791 12:41:09.754286 9, 0x0, sum = 2
4792 12:41:09.754864 10, 0x0, sum = 3
4793 12:41:09.757269 11, 0x0, sum = 4
4794 12:41:09.757760 best_step = 9
4795 12:41:09.758164
4796 12:41:09.758509 ==
4797 12:41:09.760884 Dram Type= 6, Freq= 0, CH_1, rank 1
4798 12:41:09.767286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4799 12:41:09.767850 ==
4800 12:41:09.768288 RX Vref Scan: 0
4801 12:41:09.768819
4802 12:41:09.771335 RX Vref 0 -> 0, step: 1
4803 12:41:09.771800
4804 12:41:09.773659 RX Delay -163 -> 252, step: 8
4805 12:41:09.777084 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4806 12:41:09.780538 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4807 12:41:09.787010 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4808 12:41:09.790189 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4809 12:41:09.793531 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4810 12:41:09.796834 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4811 12:41:09.800271 iDelay=205, Bit 6, Center 52 (-91 ~ 196) 288
4812 12:41:09.807174 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4813 12:41:09.810390 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4814 12:41:09.813915 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4815 12:41:09.817344 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4816 12:41:09.823543 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4817 12:41:09.826895 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4818 12:41:09.830266 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4819 12:41:09.833758 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4820 12:41:09.840174 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4821 12:41:09.840738 ==
4822 12:41:09.843478 Dram Type= 6, Freq= 0, CH_1, rank 1
4823 12:41:09.846378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4824 12:41:09.846857 ==
4825 12:41:09.847230 DQS Delay:
4826 12:41:09.849824 DQS0 = 0, DQS1 = 0
4827 12:41:09.850294 DQM Delay:
4828 12:41:09.853084 DQM0 = 49, DQM1 = 44
4829 12:41:09.853656 DQ Delay:
4830 12:41:09.856433 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =48
4831 12:41:09.859920 DQ4 =48, DQ5 =60, DQ6 =52, DQ7 =48
4832 12:41:09.862945 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4833 12:41:09.866324 DQ12 =48, DQ13 =52, DQ14 =48, DQ15 =56
4834 12:41:09.866814
4835 12:41:09.867183
4836 12:41:09.873347 [DQSOSCAuto] RK1, (LSB)MR18= 0x5d24, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
4837 12:41:09.876657 CH1 RK1: MR19=808, MR18=5D24
4838 12:41:09.882864 CH1_RK1: MR19=0x808, MR18=0x5D24, DQSOSC=392, MR23=63, INC=170, DEC=113
4839 12:41:09.886095 [RxdqsGatingPostProcess] freq 600
4840 12:41:09.892820 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4841 12:41:09.895987 Pre-setting of DQS Precalculation
4842 12:41:09.899821 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4843 12:41:09.906006 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4844 12:41:09.912659 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4845 12:41:09.913275
4846 12:41:09.913652
4847 12:41:09.916088 [Calibration Summary] 1200 Mbps
4848 12:41:09.919306 CH 0, Rank 0
4849 12:41:09.919894 SW Impedance : PASS
4850 12:41:09.922687 DUTY Scan : NO K
4851 12:41:09.925538 ZQ Calibration : PASS
4852 12:41:09.926015 Jitter Meter : NO K
4853 12:41:09.929903 CBT Training : PASS
4854 12:41:09.932516 Write leveling : PASS
4855 12:41:09.933134 RX DQS gating : PASS
4856 12:41:09.935840 RX DQ/DQS(RDDQC) : PASS
4857 12:41:09.939295 TX DQ/DQS : PASS
4858 12:41:09.939877 RX DATLAT : PASS
4859 12:41:09.943149 RX DQ/DQS(Engine): PASS
4860 12:41:09.945584 TX OE : NO K
4861 12:41:09.946062 All Pass.
4862 12:41:09.946437
4863 12:41:09.946786 CH 0, Rank 1
4864 12:41:09.948637 SW Impedance : PASS
4865 12:41:09.952654 DUTY Scan : NO K
4866 12:41:09.953263 ZQ Calibration : PASS
4867 12:41:09.955975 Jitter Meter : NO K
4868 12:41:09.956536 CBT Training : PASS
4869 12:41:09.959094 Write leveling : PASS
4870 12:41:09.962292 RX DQS gating : PASS
4871 12:41:09.962892 RX DQ/DQS(RDDQC) : PASS
4872 12:41:09.965308 TX DQ/DQS : PASS
4873 12:41:09.969236 RX DATLAT : PASS
4874 12:41:09.969802 RX DQ/DQS(Engine): PASS
4875 12:41:09.972222 TX OE : NO K
4876 12:41:09.972793 All Pass.
4877 12:41:09.973210
4878 12:41:09.976042 CH 1, Rank 0
4879 12:41:09.976606 SW Impedance : PASS
4880 12:41:09.978801 DUTY Scan : NO K
4881 12:41:09.981831 ZQ Calibration : PASS
4882 12:41:09.982307 Jitter Meter : NO K
4883 12:41:09.985416 CBT Training : PASS
4884 12:41:09.988898 Write leveling : PASS
4885 12:41:09.989540 RX DQS gating : PASS
4886 12:41:09.991974 RX DQ/DQS(RDDQC) : PASS
4887 12:41:09.995140 TX DQ/DQS : PASS
4888 12:41:09.995621 RX DATLAT : PASS
4889 12:41:09.998723 RX DQ/DQS(Engine): PASS
4890 12:41:10.001723 TX OE : NO K
4891 12:41:10.002199 All Pass.
4892 12:41:10.002573
4893 12:41:10.002919 CH 1, Rank 1
4894 12:41:10.005029 SW Impedance : PASS
4895 12:41:10.008323 DUTY Scan : NO K
4896 12:41:10.008884 ZQ Calibration : PASS
4897 12:41:10.012188 Jitter Meter : NO K
4898 12:41:10.015039 CBT Training : PASS
4899 12:41:10.015608 Write leveling : PASS
4900 12:41:10.018584 RX DQS gating : PASS
4901 12:41:10.019052 RX DQ/DQS(RDDQC) : PASS
4902 12:41:10.021524 TX DQ/DQS : PASS
4903 12:41:10.025039 RX DATLAT : PASS
4904 12:41:10.025504 RX DQ/DQS(Engine): PASS
4905 12:41:10.028511 TX OE : NO K
4906 12:41:10.029110 All Pass.
4907 12:41:10.029484
4908 12:41:10.031683 DramC Write-DBI off
4909 12:41:10.035024 PER_BANK_REFRESH: Hybrid Mode
4910 12:41:10.035594 TX_TRACKING: ON
4911 12:41:10.044897 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4912 12:41:10.048648 [FAST_K] Save calibration result to emmc
4913 12:41:10.051408 dramc_set_vcore_voltage set vcore to 662500
4914 12:41:10.055071 Read voltage for 933, 3
4915 12:41:10.055641 Vio18 = 0
4916 12:41:10.057974 Vcore = 662500
4917 12:41:10.058459 Vdram = 0
4918 12:41:10.058829 Vddq = 0
4919 12:41:10.059171 Vmddr = 0
4920 12:41:10.065051 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4921 12:41:10.068109 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4922 12:41:10.071614 MEM_TYPE=3, freq_sel=17
4923 12:41:10.074955 sv_algorithm_assistance_LP4_1600
4924 12:41:10.078309 ============ PULL DRAM RESETB DOWN ============
4925 12:41:10.085085 ========== PULL DRAM RESETB DOWN end =========
4926 12:41:10.088247 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4927 12:41:10.090910 ===================================
4928 12:41:10.094566 LPDDR4 DRAM CONFIGURATION
4929 12:41:10.097628 ===================================
4930 12:41:10.098199 EX_ROW_EN[0] = 0x0
4931 12:41:10.101116 EX_ROW_EN[1] = 0x0
4932 12:41:10.101579 LP4Y_EN = 0x0
4933 12:41:10.104496 WORK_FSP = 0x0
4934 12:41:10.104964 WL = 0x3
4935 12:41:10.107431 RL = 0x3
4936 12:41:10.110819 BL = 0x2
4937 12:41:10.111284 RPST = 0x0
4938 12:41:10.114201 RD_PRE = 0x0
4939 12:41:10.114668 WR_PRE = 0x1
4940 12:41:10.117421 WR_PST = 0x0
4941 12:41:10.117996 DBI_WR = 0x0
4942 12:41:10.120944 DBI_RD = 0x0
4943 12:41:10.121450 OTF = 0x1
4944 12:41:10.124205 ===================================
4945 12:41:10.127910 ===================================
4946 12:41:10.130640 ANA top config
4947 12:41:10.134263 ===================================
4948 12:41:10.134732 DLL_ASYNC_EN = 0
4949 12:41:10.137866 ALL_SLAVE_EN = 1
4950 12:41:10.141106 NEW_RANK_MODE = 1
4951 12:41:10.144586 DLL_IDLE_MODE = 1
4952 12:41:10.145403 LP45_APHY_COMB_EN = 1
4953 12:41:10.147610 TX_ODT_DIS = 1
4954 12:41:10.150774 NEW_8X_MODE = 1
4955 12:41:10.154080 ===================================
4956 12:41:10.157663 ===================================
4957 12:41:10.161150 data_rate = 1866
4958 12:41:10.164767 CKR = 1
4959 12:41:10.167158 DQ_P2S_RATIO = 8
4960 12:41:10.170926 ===================================
4961 12:41:10.171492 CA_P2S_RATIO = 8
4962 12:41:10.173775 DQ_CA_OPEN = 0
4963 12:41:10.177415 DQ_SEMI_OPEN = 0
4964 12:41:10.180657 CA_SEMI_OPEN = 0
4965 12:41:10.183982 CA_FULL_RATE = 0
4966 12:41:10.187382 DQ_CKDIV4_EN = 1
4967 12:41:10.187945 CA_CKDIV4_EN = 1
4968 12:41:10.190402 CA_PREDIV_EN = 0
4969 12:41:10.193826 PH8_DLY = 0
4970 12:41:10.197090 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4971 12:41:10.200523 DQ_AAMCK_DIV = 4
4972 12:41:10.203933 CA_AAMCK_DIV = 4
4973 12:41:10.204500 CA_ADMCK_DIV = 4
4974 12:41:10.207227 DQ_TRACK_CA_EN = 0
4975 12:41:10.209923 CA_PICK = 933
4976 12:41:10.213542 CA_MCKIO = 933
4977 12:41:10.217168 MCKIO_SEMI = 0
4978 12:41:10.220207 PLL_FREQ = 3732
4979 12:41:10.223693 DQ_UI_PI_RATIO = 32
4980 12:41:10.224262 CA_UI_PI_RATIO = 0
4981 12:41:10.226390 ===================================
4982 12:41:10.229972 ===================================
4983 12:41:10.233434 memory_type:LPDDR4
4984 12:41:10.236552 GP_NUM : 10
4985 12:41:10.237044 SRAM_EN : 1
4986 12:41:10.240349 MD32_EN : 0
4987 12:41:10.243814 ===================================
4988 12:41:10.246551 [ANA_INIT] >>>>>>>>>>>>>>
4989 12:41:10.249756 <<<<<< [CONFIGURE PHASE]: ANA_TX
4990 12:41:10.253560 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4991 12:41:10.256510 ===================================
4992 12:41:10.257119 data_rate = 1866,PCW = 0X8f00
4993 12:41:10.259701 ===================================
4994 12:41:10.265983 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4995 12:41:10.269832 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4996 12:41:10.276369 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4997 12:41:10.279639 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4998 12:41:10.283238 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4999 12:41:10.286219 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5000 12:41:10.289537 [ANA_INIT] flow start
5001 12:41:10.292579 [ANA_INIT] PLL >>>>>>>>
5002 12:41:10.293178 [ANA_INIT] PLL <<<<<<<<
5003 12:41:10.295989 [ANA_INIT] MIDPI >>>>>>>>
5004 12:41:10.299730 [ANA_INIT] MIDPI <<<<<<<<
5005 12:41:10.300293 [ANA_INIT] DLL >>>>>>>>
5006 12:41:10.302795 [ANA_INIT] flow end
5007 12:41:10.305948 ============ LP4 DIFF to SE enter ============
5008 12:41:10.309295 ============ LP4 DIFF to SE exit ============
5009 12:41:10.312605 [ANA_INIT] <<<<<<<<<<<<<
5010 12:41:10.316489 [Flow] Enable top DCM control >>>>>
5011 12:41:10.319071 [Flow] Enable top DCM control <<<<<
5012 12:41:10.322309 Enable DLL master slave shuffle
5013 12:41:10.329030 ==============================================================
5014 12:41:10.329616 Gating Mode config
5015 12:41:10.336208 ==============================================================
5016 12:41:10.339115 Config description:
5017 12:41:10.345917 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5018 12:41:10.352340 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5019 12:41:10.359156 SELPH_MODE 0: By rank 1: By Phase
5020 12:41:10.366015 ==============================================================
5021 12:41:10.366580 GAT_TRACK_EN = 1
5022 12:41:10.368686 RX_GATING_MODE = 2
5023 12:41:10.372308 RX_GATING_TRACK_MODE = 2
5024 12:41:10.375641 SELPH_MODE = 1
5025 12:41:10.378665 PICG_EARLY_EN = 1
5026 12:41:10.382393 VALID_LAT_VALUE = 1
5027 12:41:10.388903 ==============================================================
5028 12:41:10.391812 Enter into Gating configuration >>>>
5029 12:41:10.395375 Exit from Gating configuration <<<<
5030 12:41:10.398671 Enter into DVFS_PRE_config >>>>>
5031 12:41:10.408615 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5032 12:41:10.412074 Exit from DVFS_PRE_config <<<<<
5033 12:41:10.415217 Enter into PICG configuration >>>>
5034 12:41:10.418550 Exit from PICG configuration <<<<
5035 12:41:10.421965 [RX_INPUT] configuration >>>>>
5036 12:41:10.425253 [RX_INPUT] configuration <<<<<
5037 12:41:10.428541 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5038 12:41:10.434682 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5039 12:41:10.441624 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5040 12:41:10.444802 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5041 12:41:10.452230 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5042 12:41:10.458500 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5043 12:41:10.461618 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5044 12:41:10.468202 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5045 12:41:10.471294 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5046 12:41:10.474836 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5047 12:41:10.478357 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5048 12:41:10.484607 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5049 12:41:10.487955 ===================================
5050 12:41:10.488534 LPDDR4 DRAM CONFIGURATION
5051 12:41:10.491211 ===================================
5052 12:41:10.494332 EX_ROW_EN[0] = 0x0
5053 12:41:10.497870 EX_ROW_EN[1] = 0x0
5054 12:41:10.498436 LP4Y_EN = 0x0
5055 12:41:10.501246 WORK_FSP = 0x0
5056 12:41:10.501815 WL = 0x3
5057 12:41:10.504239 RL = 0x3
5058 12:41:10.504804 BL = 0x2
5059 12:41:10.507634 RPST = 0x0
5060 12:41:10.508200 RD_PRE = 0x0
5061 12:41:10.511391 WR_PRE = 0x1
5062 12:41:10.511957 WR_PST = 0x0
5063 12:41:10.514477 DBI_WR = 0x0
5064 12:41:10.515047 DBI_RD = 0x0
5065 12:41:10.517781 OTF = 0x1
5066 12:41:10.520804 ===================================
5067 12:41:10.524294 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5068 12:41:10.527532 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5069 12:41:10.534154 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5070 12:41:10.537652 ===================================
5071 12:41:10.538238 LPDDR4 DRAM CONFIGURATION
5072 12:41:10.540272 ===================================
5073 12:41:10.543932 EX_ROW_EN[0] = 0x10
5074 12:41:10.547507 EX_ROW_EN[1] = 0x0
5075 12:41:10.547975 LP4Y_EN = 0x0
5076 12:41:10.550378 WORK_FSP = 0x0
5077 12:41:10.550841 WL = 0x3
5078 12:41:10.553694 RL = 0x3
5079 12:41:10.554160 BL = 0x2
5080 12:41:10.556952 RPST = 0x0
5081 12:41:10.557451 RD_PRE = 0x0
5082 12:41:10.560233 WR_PRE = 0x1
5083 12:41:10.560694 WR_PST = 0x0
5084 12:41:10.563940 DBI_WR = 0x0
5085 12:41:10.564502 DBI_RD = 0x0
5086 12:41:10.567155 OTF = 0x1
5087 12:41:10.570491 ===================================
5088 12:41:10.577281 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5089 12:41:10.581077 nWR fixed to 30
5090 12:41:10.583789 [ModeRegInit_LP4] CH0 RK0
5091 12:41:10.584357 [ModeRegInit_LP4] CH0 RK1
5092 12:41:10.586821 [ModeRegInit_LP4] CH1 RK0
5093 12:41:10.590183 [ModeRegInit_LP4] CH1 RK1
5094 12:41:10.590783 match AC timing 9
5095 12:41:10.596720 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5096 12:41:10.600155 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5097 12:41:10.603627 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5098 12:41:10.609967 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5099 12:41:10.613419 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5100 12:41:10.613986 ==
5101 12:41:10.616734 Dram Type= 6, Freq= 0, CH_0, rank 0
5102 12:41:10.620170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5103 12:41:10.620736 ==
5104 12:41:10.626342 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5105 12:41:10.633185 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5106 12:41:10.636552 [CA 0] Center 37 (7~68) winsize 62
5107 12:41:10.640255 [CA 1] Center 38 (7~69) winsize 63
5108 12:41:10.643171 [CA 2] Center 35 (5~66) winsize 62
5109 12:41:10.646404 [CA 3] Center 35 (5~66) winsize 62
5110 12:41:10.649550 [CA 4] Center 34 (4~65) winsize 62
5111 12:41:10.653122 [CA 5] Center 33 (3~64) winsize 62
5112 12:41:10.653595
5113 12:41:10.656417 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5114 12:41:10.656917
5115 12:41:10.659304 [CATrainingPosCal] consider 1 rank data
5116 12:41:10.662743 u2DelayCellTimex100 = 270/100 ps
5117 12:41:10.666454 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5118 12:41:10.669186 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5119 12:41:10.672675 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5120 12:41:10.676162 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5121 12:41:10.682403 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5122 12:41:10.685768 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5123 12:41:10.686334
5124 12:41:10.689373 CA PerBit enable=1, Macro0, CA PI delay=33
5125 12:41:10.689843
5126 12:41:10.692412 [CBTSetCACLKResult] CA Dly = 33
5127 12:41:10.692879 CS Dly: 6 (0~37)
5128 12:41:10.693311 ==
5129 12:41:10.695756 Dram Type= 6, Freq= 0, CH_0, rank 1
5130 12:41:10.702391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5131 12:41:10.702961 ==
5132 12:41:10.705862 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5133 12:41:10.712259 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5134 12:41:10.715740 [CA 0] Center 38 (8~69) winsize 62
5135 12:41:10.718868 [CA 1] Center 38 (8~69) winsize 62
5136 12:41:10.722607 [CA 2] Center 36 (6~66) winsize 61
5137 12:41:10.725687 [CA 3] Center 35 (5~66) winsize 62
5138 12:41:10.728970 [CA 4] Center 34 (4~65) winsize 62
5139 12:41:10.732275 [CA 5] Center 34 (4~65) winsize 62
5140 12:41:10.732861
5141 12:41:10.735602 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5142 12:41:10.736166
5143 12:41:10.739015 [CATrainingPosCal] consider 2 rank data
5144 12:41:10.741977 u2DelayCellTimex100 = 270/100 ps
5145 12:41:10.745837 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5146 12:41:10.748844 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5147 12:41:10.755864 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5148 12:41:10.758483 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5149 12:41:10.762148 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5150 12:41:10.765398 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5151 12:41:10.765867
5152 12:41:10.768857 CA PerBit enable=1, Macro0, CA PI delay=34
5153 12:41:10.769467
5154 12:41:10.772167 [CBTSetCACLKResult] CA Dly = 34
5155 12:41:10.772733 CS Dly: 7 (0~39)
5156 12:41:10.773157
5157 12:41:10.775152 ----->DramcWriteLeveling(PI) begin...
5158 12:41:10.778631 ==
5159 12:41:10.782211 Dram Type= 6, Freq= 0, CH_0, rank 0
5160 12:41:10.785226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5161 12:41:10.785797 ==
5162 12:41:10.788548 Write leveling (Byte 0): 32 => 32
5163 12:41:10.791644 Write leveling (Byte 1): 28 => 28
5164 12:41:10.795160 DramcWriteLeveling(PI) end<-----
5165 12:41:10.795799
5166 12:41:10.796181 ==
5167 12:41:10.798172 Dram Type= 6, Freq= 0, CH_0, rank 0
5168 12:41:10.801843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5169 12:41:10.802441 ==
5170 12:41:10.805186 [Gating] SW mode calibration
5171 12:41:10.811814 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5172 12:41:10.818293 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5173 12:41:10.821752 0 14 0 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
5174 12:41:10.825083 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5175 12:41:10.831606 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5176 12:41:10.834860 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5177 12:41:10.838366 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5178 12:41:10.844738 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5179 12:41:10.848359 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
5180 12:41:10.851752 0 14 28 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
5181 12:41:10.858244 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5182 12:41:10.861274 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5183 12:41:10.864400 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5184 12:41:10.871211 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5185 12:41:10.874336 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5186 12:41:10.877659 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5187 12:41:10.884373 0 15 24 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
5188 12:41:10.887803 0 15 28 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
5189 12:41:10.891125 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5190 12:41:10.897644 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 12:41:10.900805 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5192 12:41:10.904247 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 12:41:10.910509 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5194 12:41:10.914102 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5195 12:41:10.917115 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5196 12:41:10.923748 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5197 12:41:10.927336 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 12:41:10.930934 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 12:41:10.936862 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 12:41:10.940693 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 12:41:10.943745 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 12:41:10.947019 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 12:41:10.953455 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 12:41:10.956901 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 12:41:10.960329 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 12:41:10.966816 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 12:41:10.970262 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 12:41:10.973409 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 12:41:10.979844 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 12:41:10.983153 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 12:41:10.986834 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5212 12:41:10.993218 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5213 12:41:10.996369 Total UI for P1: 0, mck2ui 16
5214 12:41:11.000072 best dqsien dly found for B0: ( 1, 2, 24)
5215 12:41:11.003251 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5216 12:41:11.006639 Total UI for P1: 0, mck2ui 16
5217 12:41:11.009852 best dqsien dly found for B1: ( 1, 2, 28)
5218 12:41:11.013137 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5219 12:41:11.016404 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5220 12:41:11.017002
5221 12:41:11.019778 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5222 12:41:11.026734 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5223 12:41:11.027300 [Gating] SW calibration Done
5224 12:41:11.027833 ==
5225 12:41:11.029303 Dram Type= 6, Freq= 0, CH_0, rank 0
5226 12:41:11.036369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5227 12:41:11.036941 ==
5228 12:41:11.037355 RX Vref Scan: 0
5229 12:41:11.037704
5230 12:41:11.039385 RX Vref 0 -> 0, step: 1
5231 12:41:11.039946
5232 12:41:11.042890 RX Delay -80 -> 252, step: 8
5233 12:41:11.046219 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5234 12:41:11.049489 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5235 12:41:11.052666 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5236 12:41:11.059426 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5237 12:41:11.062896 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5238 12:41:11.066041 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5239 12:41:11.069518 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5240 12:41:11.072666 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5241 12:41:11.076038 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5242 12:41:11.082747 iDelay=208, Bit 9, Center 83 (0 ~ 167) 168
5243 12:41:11.085797 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5244 12:41:11.088902 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5245 12:41:11.092391 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5246 12:41:11.095689 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5247 12:41:11.098932 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5248 12:41:11.105955 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5249 12:41:11.106532 ==
5250 12:41:11.109197 Dram Type= 6, Freq= 0, CH_0, rank 0
5251 12:41:11.112173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5252 12:41:11.112648 ==
5253 12:41:11.113045 DQS Delay:
5254 12:41:11.115789 DQS0 = 0, DQS1 = 0
5255 12:41:11.116382 DQM Delay:
5256 12:41:11.119302 DQM0 = 105, DQM1 = 90
5257 12:41:11.119876 DQ Delay:
5258 12:41:11.122075 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5259 12:41:11.125768 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5260 12:41:11.129079 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =87
5261 12:41:11.132227 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5262 12:41:11.133013
5263 12:41:11.133415
5264 12:41:11.133762 ==
5265 12:41:11.135375 Dram Type= 6, Freq= 0, CH_0, rank 0
5266 12:41:11.138813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 12:41:11.142407 ==
5268 12:41:11.142983
5269 12:41:11.143357
5270 12:41:11.143699 TX Vref Scan disable
5271 12:41:11.145503 == TX Byte 0 ==
5272 12:41:11.148791 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5273 12:41:11.152014 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5274 12:41:11.155461 == TX Byte 1 ==
5275 12:41:11.158465 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5276 12:41:11.162011 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5277 12:41:11.165313 ==
5278 12:41:11.168559 Dram Type= 6, Freq= 0, CH_0, rank 0
5279 12:41:11.171913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5280 12:41:11.172487 ==
5281 12:41:11.172862
5282 12:41:11.173266
5283 12:41:11.175565 TX Vref Scan disable
5284 12:41:11.176139 == TX Byte 0 ==
5285 12:41:11.181890 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5286 12:41:11.185041 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5287 12:41:11.185612 == TX Byte 1 ==
5288 12:41:11.192206 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5289 12:41:11.195070 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5290 12:41:11.195675
5291 12:41:11.196051 [DATLAT]
5292 12:41:11.198456 Freq=933, CH0 RK0
5293 12:41:11.198928
5294 12:41:11.199304 DATLAT Default: 0xd
5295 12:41:11.201664 0, 0xFFFF, sum = 0
5296 12:41:11.202157 1, 0xFFFF, sum = 0
5297 12:41:11.204945 2, 0xFFFF, sum = 0
5298 12:41:11.205561 3, 0xFFFF, sum = 0
5299 12:41:11.207961 4, 0xFFFF, sum = 0
5300 12:41:11.211279 5, 0xFFFF, sum = 0
5301 12:41:11.211859 6, 0xFFFF, sum = 0
5302 12:41:11.214903 7, 0xFFFF, sum = 0
5303 12:41:11.215487 8, 0xFFFF, sum = 0
5304 12:41:11.218283 9, 0xFFFF, sum = 0
5305 12:41:11.218869 10, 0x0, sum = 1
5306 12:41:11.221383 11, 0x0, sum = 2
5307 12:41:11.221862 12, 0x0, sum = 3
5308 12:41:11.222244 13, 0x0, sum = 4
5309 12:41:11.224795 best_step = 11
5310 12:41:11.225307
5311 12:41:11.225679 ==
5312 12:41:11.227789 Dram Type= 6, Freq= 0, CH_0, rank 0
5313 12:41:11.231439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5314 12:41:11.232012 ==
5315 12:41:11.234895 RX Vref Scan: 1
5316 12:41:11.235498
5317 12:41:11.237967 RX Vref 0 -> 0, step: 1
5318 12:41:11.238438
5319 12:41:11.238808 RX Delay -53 -> 252, step: 4
5320 12:41:11.239154
5321 12:41:11.241265 Set Vref, RX VrefLevel [Byte0]: 57
5322 12:41:11.244237 [Byte1]: 49
5323 12:41:11.249327
5324 12:41:11.249901 Final RX Vref Byte 0 = 57 to rank0
5325 12:41:11.252277 Final RX Vref Byte 1 = 49 to rank0
5326 12:41:11.255625 Final RX Vref Byte 0 = 57 to rank1
5327 12:41:11.258994 Final RX Vref Byte 1 = 49 to rank1==
5328 12:41:11.262435 Dram Type= 6, Freq= 0, CH_0, rank 0
5329 12:41:11.269178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5330 12:41:11.269739 ==
5331 12:41:11.270122 DQS Delay:
5332 12:41:11.270476 DQS0 = 0, DQS1 = 0
5333 12:41:11.272455 DQM Delay:
5334 12:41:11.273080 DQM0 = 107, DQM1 = 92
5335 12:41:11.275828 DQ Delay:
5336 12:41:11.279335 DQ0 =108, DQ1 =106, DQ2 =102, DQ3 =106
5337 12:41:11.282411 DQ4 =106, DQ5 =98, DQ6 =116, DQ7 =114
5338 12:41:11.285456 DQ8 =86, DQ9 =80, DQ10 =92, DQ11 =92
5339 12:41:11.288465 DQ12 =94, DQ13 =92, DQ14 =104, DQ15 =100
5340 12:41:11.288941
5341 12:41:11.289393
5342 12:41:11.295134 [DQSOSCAuto] RK0, (LSB)MR18= 0x221e, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
5343 12:41:11.299002 CH0 RK0: MR19=505, MR18=221E
5344 12:41:11.305352 CH0_RK0: MR19=0x505, MR18=0x221E, DQSOSC=411, MR23=63, INC=64, DEC=42
5345 12:41:11.305920
5346 12:41:11.308564 ----->DramcWriteLeveling(PI) begin...
5347 12:41:11.309081 ==
5348 12:41:11.311777 Dram Type= 6, Freq= 0, CH_0, rank 1
5349 12:41:11.315122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5350 12:41:11.318369 ==
5351 12:41:11.318802 Write leveling (Byte 0): 31 => 31
5352 12:41:11.321534 Write leveling (Byte 1): 30 => 30
5353 12:41:11.325005 DramcWriteLeveling(PI) end<-----
5354 12:41:11.325498
5355 12:41:11.325840 ==
5356 12:41:11.328577 Dram Type= 6, Freq= 0, CH_0, rank 1
5357 12:41:11.334810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5358 12:41:11.335380 ==
5359 12:41:11.338229 [Gating] SW mode calibration
5360 12:41:11.344895 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5361 12:41:11.348227 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5362 12:41:11.354752 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5363 12:41:11.357835 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5364 12:41:11.361542 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5365 12:41:11.367819 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5366 12:41:11.371519 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5367 12:41:11.374486 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5368 12:41:11.381572 0 14 24 | B1->B0 | 3434 3232 | 0 1 | (0 0) (1 1)
5369 12:41:11.384740 0 14 28 | B1->B0 | 2e2e 2626 | 1 0 | (1 0) (0 0)
5370 12:41:11.387578 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5371 12:41:11.394228 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5372 12:41:11.397483 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5373 12:41:11.400736 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5374 12:41:11.407321 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5375 12:41:11.411008 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5376 12:41:11.414402 0 15 24 | B1->B0 | 2424 2929 | 0 0 | (0 0) (0 0)
5377 12:41:11.420692 0 15 28 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5378 12:41:11.424311 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 12:41:11.427610 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 12:41:11.434167 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 12:41:11.437189 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5382 12:41:11.440601 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 12:41:11.447147 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 12:41:11.450411 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5385 12:41:11.453577 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5386 12:41:11.460276 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 12:41:11.463742 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 12:41:11.467370 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 12:41:11.473924 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 12:41:11.477089 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 12:41:11.480363 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 12:41:11.487011 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 12:41:11.490462 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 12:41:11.493377 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 12:41:11.496640 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 12:41:12.083739 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 12:41:12.084594 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 12:41:12.084962 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 12:41:12.085332 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 12:41:12.085704 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 12:41:12.086017 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5402 12:41:12.086313 Total UI for P1: 0, mck2ui 16
5403 12:41:12.086606 best dqsien dly found for B0: ( 1, 2, 26)
5404 12:41:12.086896 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5405 12:41:12.087181 Total UI for P1: 0, mck2ui 16
5406 12:41:12.087503 best dqsien dly found for B1: ( 1, 2, 28)
5407 12:41:12.087876 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5408 12:41:12.088191 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5409 12:41:12.088436
5410 12:41:12.088491 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5411 12:41:12.088573 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5412 12:41:12.088640 [Gating] SW calibration Done
5413 12:41:12.088723 ==
5414 12:41:12.088775 Dram Type= 6, Freq= 0, CH_0, rank 1
5415 12:41:12.088845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5416 12:41:12.088899 ==
5417 12:41:12.088953 RX Vref Scan: 0
5418 12:41:12.089048
5419 12:41:12.089116 RX Vref 0 -> 0, step: 1
5420 12:41:12.089169
5421 12:41:12.089222 RX Delay -80 -> 252, step: 8
5422 12:41:12.089276 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5423 12:41:12.089329 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5424 12:41:12.089384 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5425 12:41:12.089438 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5426 12:41:12.089491 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5427 12:41:12.089559 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5428 12:41:12.089642 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5429 12:41:12.089709 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5430 12:41:12.089762 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5431 12:41:12.089831 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5432 12:41:12.089905 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5433 12:41:12.089988 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5434 12:41:12.090041 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5435 12:41:12.090094 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5436 12:41:12.090147 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5437 12:41:12.090200 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5438 12:41:12.090252 ==
5439 12:41:12.090305 Dram Type= 6, Freq= 0, CH_0, rank 1
5440 12:41:12.090359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5441 12:41:12.090412 ==
5442 12:41:12.090481 DQS Delay:
5443 12:41:12.090534 DQS0 = 0, DQS1 = 0
5444 12:41:12.090588 DQM Delay:
5445 12:41:12.090654 DQM0 = 104, DQM1 = 90
5446 12:41:12.090707 DQ Delay:
5447 12:41:12.090760 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5448 12:41:12.090813 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5449 12:41:12.090867 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5450 12:41:12.090920 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5451 12:41:12.090973
5452 12:41:12.091026
5453 12:41:12.091078 ==
5454 12:41:12.091130 Dram Type= 6, Freq= 0, CH_0, rank 1
5455 12:41:12.091182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5456 12:41:12.091235 ==
5457 12:41:12.091304
5458 12:41:12.091359
5459 12:41:12.091415 TX Vref Scan disable
5460 12:41:12.091472 == TX Byte 0 ==
5461 12:41:12.091527 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5462 12:41:12.091584 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5463 12:41:12.091640 == TX Byte 1 ==
5464 12:41:12.091696 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5465 12:41:12.091753 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5466 12:41:12.091809 ==
5467 12:41:12.091866 Dram Type= 6, Freq= 0, CH_0, rank 1
5468 12:41:12.091922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5469 12:41:12.091979 ==
5470 12:41:12.092035
5471 12:41:12.092091
5472 12:41:12.092148 TX Vref Scan disable
5473 12:41:12.092204 == TX Byte 0 ==
5474 12:41:12.092260 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5475 12:41:12.092316 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5476 12:41:12.092372 == TX Byte 1 ==
5477 12:41:12.092428 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5478 12:41:12.092484 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5479 12:41:12.092540
5480 12:41:12.092596 [DATLAT]
5481 12:41:12.092652 Freq=933, CH0 RK1
5482 12:41:12.092708
5483 12:41:12.092764 DATLAT Default: 0xb
5484 12:41:12.092820 0, 0xFFFF, sum = 0
5485 12:41:12.092877 1, 0xFFFF, sum = 0
5486 12:41:12.092935 2, 0xFFFF, sum = 0
5487 12:41:12.092996 3, 0xFFFF, sum = 0
5488 12:41:12.093053 4, 0xFFFF, sum = 0
5489 12:41:12.093111 5, 0xFFFF, sum = 0
5490 12:41:12.093168 6, 0xFFFF, sum = 0
5491 12:41:12.093225 7, 0xFFFF, sum = 0
5492 12:41:12.093282 8, 0xFFFF, sum = 0
5493 12:41:12.093339 9, 0xFFFF, sum = 0
5494 12:41:12.093396 10, 0x0, sum = 1
5495 12:41:12.093453 11, 0x0, sum = 2
5496 12:41:12.093510 12, 0x0, sum = 3
5497 12:41:12.093566 13, 0x0, sum = 4
5498 12:41:12.093623 best_step = 11
5499 12:41:12.093678
5500 12:41:12.093734 ==
5501 12:41:12.093789 Dram Type= 6, Freq= 0, CH_0, rank 1
5502 12:41:12.093846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5503 12:41:12.093902 ==
5504 12:41:12.093959 RX Vref Scan: 0
5505 12:41:12.094015
5506 12:41:12.094072 RX Vref 0 -> 0, step: 1
5507 12:41:12.094128
5508 12:41:12.094183 RX Delay -53 -> 252, step: 4
5509 12:41:12.094239 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5510 12:41:12.094295 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5511 12:41:12.094352 iDelay=199, Bit 2, Center 102 (19 ~ 186) 168
5512 12:41:12.094408 iDelay=199, Bit 3, Center 100 (19 ~ 182) 164
5513 12:41:12.094463 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5514 12:41:12.094519 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5515 12:41:12.094575 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5516 12:41:12.094632 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5517 12:41:12.094688 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5518 12:41:12.094744 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5519 12:41:12.094801 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5520 12:41:12.094858 iDelay=199, Bit 11, Center 90 (7 ~ 174) 168
5521 12:41:12.094914 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5522 12:41:12.094970 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5523 12:41:12.095024 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5524 12:41:12.095080 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5525 12:41:12.095135 ==
5526 12:41:12.095190 Dram Type= 6, Freq= 0, CH_0, rank 1
5527 12:41:12.095245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5528 12:41:12.095302 ==
5529 12:41:12.095357 DQS Delay:
5530 12:41:12.095413 DQS0 = 0, DQS1 = 0
5531 12:41:12.095468 DQM Delay:
5532 12:41:12.095524 DQM0 = 104, DQM1 = 92
5533 12:41:12.095579 DQ Delay:
5534 12:41:12.095636 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =100
5535 12:41:12.095692 DQ4 =104, DQ5 =98, DQ6 =112, DQ7 =112
5536 12:41:12.095748 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =90
5537 12:41:12.095999 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =98
5538 12:41:12.096066
5539 12:41:12.096124
5540 12:41:12.096181 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e0f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 407 ps
5541 12:41:12.096240 CH0 RK1: MR19=505, MR18=2E0F
5542 12:41:12.096297 CH0_RK1: MR19=0x505, MR18=0x2E0F, DQSOSC=407, MR23=63, INC=65, DEC=43
5543 12:41:12.096355 [RxdqsGatingPostProcess] freq 933
5544 12:41:12.096412 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5545 12:41:12.096469 best DQS0 dly(2T, 0.5T) = (0, 10)
5546 12:41:12.096526 best DQS1 dly(2T, 0.5T) = (0, 10)
5547 12:41:12.096582 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5548 12:41:12.096638 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5549 12:41:12.096694 best DQS0 dly(2T, 0.5T) = (0, 10)
5550 12:41:12.096751 best DQS1 dly(2T, 0.5T) = (0, 10)
5551 12:41:12.096807 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5552 12:41:12.096863 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5553 12:41:12.096919 Pre-setting of DQS Precalculation
5554 12:41:12.096983 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5555 12:41:12.097042 ==
5556 12:41:12.097100 Dram Type= 6, Freq= 0, CH_1, rank 0
5557 12:41:12.097157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5558 12:41:12.097213 ==
5559 12:41:12.097270 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5560 12:41:12.097327 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5561 12:41:12.097389 [CA 0] Center 37 (7~68) winsize 62
5562 12:41:12.097464 [CA 1] Center 37 (7~68) winsize 62
5563 12:41:12.097523 [CA 2] Center 36 (6~66) winsize 61
5564 12:41:12.097579 [CA 3] Center 34 (4~65) winsize 62
5565 12:41:12.097636 [CA 4] Center 35 (5~66) winsize 62
5566 12:41:12.097692 [CA 5] Center 34 (4~65) winsize 62
5567 12:41:12.097748
5568 12:41:12.097805 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5569 12:41:12.097862
5570 12:41:12.097919 [CATrainingPosCal] consider 1 rank data
5571 12:41:12.097975 u2DelayCellTimex100 = 270/100 ps
5572 12:41:12.098032 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5573 12:41:12.098089 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5574 12:41:12.098145 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5575 12:41:12.098201 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5576 12:41:12.098258 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5577 12:41:12.098314 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5578 12:41:12.098370
5579 12:41:12.098427 CA PerBit enable=1, Macro0, CA PI delay=34
5580 12:41:12.098484
5581 12:41:12.098540 [CBTSetCACLKResult] CA Dly = 34
5582 12:41:12.098597 CS Dly: 7 (0~38)
5583 12:41:12.098653 ==
5584 12:41:12.098710 Dram Type= 6, Freq= 0, CH_1, rank 1
5585 12:41:12.098767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5586 12:41:12.098823 ==
5587 12:41:12.098880 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5588 12:41:12.098937 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5589 12:41:12.098994 [CA 0] Center 38 (8~69) winsize 62
5590 12:41:12.099050 [CA 1] Center 38 (8~69) winsize 62
5591 12:41:12.099107 [CA 2] Center 36 (6~66) winsize 61
5592 12:41:12.099163 [CA 3] Center 35 (5~65) winsize 61
5593 12:41:12.099219 [CA 4] Center 35 (5~65) winsize 61
5594 12:41:12.099275 [CA 5] Center 34 (4~64) winsize 61
5595 12:41:12.099330
5596 12:41:12.099386 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5597 12:41:12.099442
5598 12:41:12.099498 [CATrainingPosCal] consider 2 rank data
5599 12:41:12.099555 u2DelayCellTimex100 = 270/100 ps
5600 12:41:12.099612 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5601 12:41:12.099668 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5602 12:41:12.099725 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5603 12:41:12.099781 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5604 12:41:12.099837 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5605 12:41:12.099893 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5606 12:41:12.099949
5607 12:41:12.100005 CA PerBit enable=1, Macro0, CA PI delay=34
5608 12:41:12.100061
5609 12:41:12.100118 [CBTSetCACLKResult] CA Dly = 34
5610 12:41:12.100174 CS Dly: 7 (0~39)
5611 12:41:12.100230
5612 12:41:12.100286 ----->DramcWriteLeveling(PI) begin...
5613 12:41:12.100344 ==
5614 12:41:12.100401 Dram Type= 6, Freq= 0, CH_1, rank 0
5615 12:41:12.100458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5616 12:41:12.100515 ==
5617 12:41:12.100586 Write leveling (Byte 0): 26 => 26
5618 12:41:12.100646 Write leveling (Byte 1): 30 => 30
5619 12:41:12.103915 DramcWriteLeveling(PI) end<-----
5620 12:41:12.104003
5621 12:41:12.104073 ==
5622 12:41:12.107759 Dram Type= 6, Freq= 0, CH_1, rank 0
5623 12:41:12.111000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5624 12:41:12.111168 ==
5625 12:41:12.113790 [Gating] SW mode calibration
5626 12:41:12.121010 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5627 12:41:12.127538 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5628 12:41:12.130686 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5629 12:41:12.134018 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5630 12:41:12.140344 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5631 12:41:12.143856 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5632 12:41:12.147882 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5633 12:41:12.153898 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5634 12:41:12.157483 0 14 24 | B1->B0 | 3131 2f2f | 1 0 | (1 0) (0 0)
5635 12:41:12.160825 0 14 28 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
5636 12:41:12.167755 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5637 12:41:12.170842 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5638 12:41:12.174204 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5639 12:41:12.180787 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5640 12:41:12.184193 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5641 12:41:12.187459 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5642 12:41:12.193651 0 15 24 | B1->B0 | 2525 2f2f | 0 0 | (0 0) (0 0)
5643 12:41:12.197172 0 15 28 | B1->B0 | 3a3a 3d3d | 0 0 | (0 0) (0 0)
5644 12:41:12.200901 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 12:41:12.207265 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5646 12:41:12.210756 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5647 12:41:12.213613 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5648 12:41:12.220914 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5649 12:41:12.224228 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5650 12:41:12.227277 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5651 12:41:12.231029 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 12:41:12.236872 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 12:41:12.240502 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 12:41:12.243890 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 12:41:12.250352 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 12:41:12.253576 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 12:41:12.256947 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 12:41:12.263324 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 12:41:12.267166 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 12:41:12.270105 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 12:41:12.276834 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 12:41:12.280499 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 12:41:12.283757 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 12:41:12.290260 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 12:41:12.293547 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 12:41:12.296630 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5667 12:41:12.299931 Total UI for P1: 0, mck2ui 16
5668 12:41:12.303134 best dqsien dly found for B0: ( 1, 2, 22)
5669 12:41:12.309984 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5670 12:41:12.313677 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5671 12:41:12.316301 Total UI for P1: 0, mck2ui 16
5672 12:41:12.319828 best dqsien dly found for B1: ( 1, 2, 26)
5673 12:41:12.323249 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5674 12:41:12.326331 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5675 12:41:12.326808
5676 12:41:12.329799 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5677 12:41:12.333058 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5678 12:41:12.336539 [Gating] SW calibration Done
5679 12:41:12.337147 ==
5680 12:41:12.339586 Dram Type= 6, Freq= 0, CH_1, rank 0
5681 12:41:12.343157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5682 12:41:12.346473 ==
5683 12:41:12.346951 RX Vref Scan: 0
5684 12:41:12.347321
5685 12:41:12.349584 RX Vref 0 -> 0, step: 1
5686 12:41:12.350149
5687 12:41:12.353163 RX Delay -80 -> 252, step: 8
5688 12:41:12.356144 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5689 12:41:12.359568 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5690 12:41:12.362580 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5691 12:41:12.366525 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5692 12:41:12.369517 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5693 12:41:12.376675 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5694 12:41:12.379723 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5695 12:41:12.382782 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5696 12:41:12.386096 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5697 12:41:12.389189 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5698 12:41:12.396003 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5699 12:41:12.398966 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5700 12:41:12.402298 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5701 12:41:12.405642 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5702 12:41:12.409158 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5703 12:41:12.412561 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5704 12:41:12.415403 ==
5705 12:41:12.419015 Dram Type= 6, Freq= 0, CH_1, rank 0
5706 12:41:12.422531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5707 12:41:12.423115 ==
5708 12:41:12.423494 DQS Delay:
5709 12:41:12.425427 DQS0 = 0, DQS1 = 0
5710 12:41:12.425917 DQM Delay:
5711 12:41:12.429389 DQM0 = 101, DQM1 = 95
5712 12:41:12.429959 DQ Delay:
5713 12:41:12.432057 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5714 12:41:12.435758 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5715 12:41:12.439078 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5716 12:41:12.442269 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5717 12:41:12.442840
5718 12:41:12.443215
5719 12:41:12.443559 ==
5720 12:41:12.445638 Dram Type= 6, Freq= 0, CH_1, rank 0
5721 12:41:12.449272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 12:41:12.449838 ==
5723 12:41:12.452499
5724 12:41:12.453101
5725 12:41:12.453487 TX Vref Scan disable
5726 12:41:12.455295 == TX Byte 0 ==
5727 12:41:12.458670 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5728 12:41:12.461884 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5729 12:41:12.465225 == TX Byte 1 ==
5730 12:41:12.468624 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5731 12:41:12.472039 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5732 12:41:12.475446 ==
5733 12:41:12.476010 Dram Type= 6, Freq= 0, CH_1, rank 0
5734 12:41:12.481739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5735 12:41:12.482297 ==
5736 12:41:12.482665
5737 12:41:12.483002
5738 12:41:12.484967 TX Vref Scan disable
5739 12:41:12.485562 == TX Byte 0 ==
5740 12:41:12.492025 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5741 12:41:12.495124 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5742 12:41:12.495692 == TX Byte 1 ==
5743 12:41:12.501908 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5744 12:41:12.504945 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5745 12:41:12.505541
5746 12:41:12.505911 [DATLAT]
5747 12:41:12.508019 Freq=933, CH1 RK0
5748 12:41:12.508728
5749 12:41:12.509155 DATLAT Default: 0xd
5750 12:41:12.511377 0, 0xFFFF, sum = 0
5751 12:41:12.511965 1, 0xFFFF, sum = 0
5752 12:41:12.514703 2, 0xFFFF, sum = 0
5753 12:41:12.515178 3, 0xFFFF, sum = 0
5754 12:41:12.517970 4, 0xFFFF, sum = 0
5755 12:41:12.521607 5, 0xFFFF, sum = 0
5756 12:41:12.522202 6, 0xFFFF, sum = 0
5757 12:41:12.524848 7, 0xFFFF, sum = 0
5758 12:41:12.525479 8, 0xFFFF, sum = 0
5759 12:41:12.527703 9, 0xFFFF, sum = 0
5760 12:41:12.528179 10, 0x0, sum = 1
5761 12:41:12.531194 11, 0x0, sum = 2
5762 12:41:12.531686 12, 0x0, sum = 3
5763 12:41:12.532067 13, 0x0, sum = 4
5764 12:41:12.534420 best_step = 11
5765 12:41:12.534904
5766 12:41:12.535277 ==
5767 12:41:12.537795 Dram Type= 6, Freq= 0, CH_1, rank 0
5768 12:41:12.540953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5769 12:41:12.541445 ==
5770 12:41:12.544448 RX Vref Scan: 1
5771 12:41:12.544913
5772 12:41:12.547771 RX Vref 0 -> 0, step: 1
5773 12:41:12.548239
5774 12:41:12.548610 RX Delay -53 -> 252, step: 4
5775 12:41:12.548957
5776 12:41:12.551451 Set Vref, RX VrefLevel [Byte0]: 53
5777 12:41:12.554452 [Byte1]: 53
5778 12:41:12.558838
5779 12:41:12.559307 Final RX Vref Byte 0 = 53 to rank0
5780 12:41:12.561867 Final RX Vref Byte 1 = 53 to rank0
5781 12:41:12.565642 Final RX Vref Byte 0 = 53 to rank1
5782 12:41:12.568715 Final RX Vref Byte 1 = 53 to rank1==
5783 12:41:12.572444 Dram Type= 6, Freq= 0, CH_1, rank 0
5784 12:41:12.579126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5785 12:41:12.579703 ==
5786 12:41:12.580082 DQS Delay:
5787 12:41:12.581936 DQS0 = 0, DQS1 = 0
5788 12:41:12.582405 DQM Delay:
5789 12:41:12.582776 DQM0 = 104, DQM1 = 97
5790 12:41:12.585262 DQ Delay:
5791 12:41:12.588576 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5792 12:41:12.592157 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5793 12:41:12.595589 DQ8 =88, DQ9 =88, DQ10 =100, DQ11 =92
5794 12:41:12.598466 DQ12 =108, DQ13 =100, DQ14 =104, DQ15 =102
5795 12:41:12.598937
5796 12:41:12.599308
5797 12:41:12.605056 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f37, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 412 ps
5798 12:41:12.608095 CH1 RK0: MR19=505, MR18=1F37
5799 12:41:12.615760 CH1_RK0: MR19=0x505, MR18=0x1F37, DQSOSC=404, MR23=63, INC=66, DEC=44
5800 12:41:12.616362
5801 12:41:12.618153 ----->DramcWriteLeveling(PI) begin...
5802 12:41:12.618631 ==
5803 12:41:12.621647 Dram Type= 6, Freq= 0, CH_1, rank 1
5804 12:41:12.627834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5805 12:41:12.628397 ==
5806 12:41:12.631307 Write leveling (Byte 0): 30 => 30
5807 12:41:12.631776 Write leveling (Byte 1): 30 => 30
5808 12:41:12.634735 DramcWriteLeveling(PI) end<-----
5809 12:41:12.635311
5810 12:41:12.637795 ==
5811 12:41:12.638336 Dram Type= 6, Freq= 0, CH_1, rank 1
5812 12:41:12.644758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5813 12:41:12.645367 ==
5814 12:41:12.647775 [Gating] SW mode calibration
5815 12:41:12.654976 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5816 12:41:12.657462 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5817 12:41:12.664652 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5818 12:41:12.667891 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5819 12:41:12.670963 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5820 12:41:12.677757 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5821 12:41:12.681174 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5822 12:41:12.684706 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5823 12:41:12.690633 0 14 24 | B1->B0 | 3131 3434 | 0 1 | (0 1) (1 0)
5824 12:41:12.694200 0 14 28 | B1->B0 | 2323 2b2b | 0 0 | (1 0) (1 0)
5825 12:41:12.697460 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5826 12:41:12.704522 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5827 12:41:12.707673 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5828 12:41:12.711030 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5829 12:41:12.717868 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5830 12:41:12.720962 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5831 12:41:12.724316 0 15 24 | B1->B0 | 2929 2424 | 0 0 | (0 0) (0 0)
5832 12:41:12.730703 0 15 28 | B1->B0 | 3f3f 3838 | 1 1 | (0 0) (0 0)
5833 12:41:12.734002 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5834 12:41:12.737135 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5835 12:41:12.744045 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5836 12:41:12.747192 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5837 12:41:12.750418 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5838 12:41:12.756864 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5839 12:41:12.760030 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5840 12:41:12.763863 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5841 12:41:12.770559 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 12:41:12.773618 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 12:41:12.777428 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 12:41:12.783377 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 12:41:12.786705 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 12:41:12.789821 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 12:41:12.796811 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 12:41:12.799393 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 12:41:12.802895 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 12:41:12.809561 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 12:41:12.813463 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 12:41:12.816332 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 12:41:12.822918 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 12:41:12.826461 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 12:41:12.829723 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5856 12:41:12.836437 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5857 12:41:12.837037 Total UI for P1: 0, mck2ui 16
5858 12:41:12.842533 best dqsien dly found for B1: ( 1, 2, 24)
5859 12:41:12.845902 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5860 12:41:12.849353 Total UI for P1: 0, mck2ui 16
5861 12:41:12.852818 best dqsien dly found for B0: ( 1, 2, 26)
5862 12:41:12.855967 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5863 12:41:12.859307 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5864 12:41:12.859866
5865 12:41:12.862710 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5866 12:41:12.865914 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5867 12:41:12.869566 [Gating] SW calibration Done
5868 12:41:12.870042 ==
5869 12:41:12.872869 Dram Type= 6, Freq= 0, CH_1, rank 1
5870 12:41:12.876538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5871 12:41:12.877158 ==
5872 12:41:12.879402 RX Vref Scan: 0
5873 12:41:12.879968
5874 12:41:12.883197 RX Vref 0 -> 0, step: 1
5875 12:41:12.883764
5876 12:41:12.884144 RX Delay -80 -> 252, step: 8
5877 12:41:12.889336 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5878 12:41:12.892766 iDelay=208, Bit 1, Center 99 (16 ~ 183) 168
5879 12:41:12.896189 iDelay=208, Bit 2, Center 87 (0 ~ 175) 176
5880 12:41:12.899151 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5881 12:41:12.902569 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5882 12:41:12.909139 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5883 12:41:12.912354 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5884 12:41:12.915616 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5885 12:41:12.919081 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5886 12:41:12.922484 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5887 12:41:12.929181 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5888 12:41:12.932277 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5889 12:41:12.935320 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5890 12:41:12.938739 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5891 12:41:12.941927 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5892 12:41:12.948818 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5893 12:41:12.949432 ==
5894 12:41:12.951811 Dram Type= 6, Freq= 0, CH_1, rank 1
5895 12:41:12.955387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5896 12:41:12.955959 ==
5897 12:41:12.956361 DQS Delay:
5898 12:41:12.958467 DQS0 = 0, DQS1 = 0
5899 12:41:12.958939 DQM Delay:
5900 12:41:12.962179 DQM0 = 103, DQM1 = 96
5901 12:41:12.962655 DQ Delay:
5902 12:41:12.965149 DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =103
5903 12:41:12.968496 DQ4 =103, DQ5 =115, DQ6 =107, DQ7 =103
5904 12:41:12.971907 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5905 12:41:12.975058 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =107
5906 12:41:12.975631
5907 12:41:12.976010
5908 12:41:12.976358 ==
5909 12:41:12.978444 Dram Type= 6, Freq= 0, CH_1, rank 1
5910 12:41:12.985034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5911 12:41:12.985612 ==
5912 12:41:12.985993
5913 12:41:12.986339
5914 12:41:12.986671 TX Vref Scan disable
5915 12:41:12.988327 == TX Byte 0 ==
5916 12:41:12.991621 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5917 12:41:12.998296 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5918 12:41:12.998864 == TX Byte 1 ==
5919 12:41:13.001516 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5920 12:41:13.008353 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5921 12:41:13.008922 ==
5922 12:41:13.011864 Dram Type= 6, Freq= 0, CH_1, rank 1
5923 12:41:13.015398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5924 12:41:13.015975 ==
5925 12:41:13.016355
5926 12:41:13.016703
5927 12:41:13.018061 TX Vref Scan disable
5928 12:41:13.018537 == TX Byte 0 ==
5929 12:41:13.024925 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5930 12:41:13.028264 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5931 12:41:13.028950 == TX Byte 1 ==
5932 12:41:13.034670 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5933 12:41:13.038334 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5934 12:41:13.038903
5935 12:41:13.039278 [DATLAT]
5936 12:41:13.041197 Freq=933, CH1 RK1
5937 12:41:13.041766
5938 12:41:13.042146 DATLAT Default: 0xb
5939 12:41:13.044844 0, 0xFFFF, sum = 0
5940 12:41:13.047775 1, 0xFFFF, sum = 0
5941 12:41:13.048348 2, 0xFFFF, sum = 0
5942 12:41:13.050879 3, 0xFFFF, sum = 0
5943 12:41:13.051361 4, 0xFFFF, sum = 0
5944 12:41:13.054654 5, 0xFFFF, sum = 0
5945 12:41:13.055233 6, 0xFFFF, sum = 0
5946 12:41:13.058056 7, 0xFFFF, sum = 0
5947 12:41:13.058537 8, 0xFFFF, sum = 0
5948 12:41:13.061328 9, 0xFFFF, sum = 0
5949 12:41:13.061807 10, 0x0, sum = 1
5950 12:41:13.064487 11, 0x0, sum = 2
5951 12:41:13.065055 12, 0x0, sum = 3
5952 12:41:13.067714 13, 0x0, sum = 4
5953 12:41:13.068193 best_step = 11
5954 12:41:13.068566
5955 12:41:13.068950 ==
5956 12:41:13.071040 Dram Type= 6, Freq= 0, CH_1, rank 1
5957 12:41:13.074381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5958 12:41:13.074856 ==
5959 12:41:13.077838 RX Vref Scan: 0
5960 12:41:13.078313
5961 12:41:13.080742 RX Vref 0 -> 0, step: 1
5962 12:41:13.081240
5963 12:41:13.081615 RX Delay -53 -> 252, step: 4
5964 12:41:13.088591 iDelay=199, Bit 0, Center 110 (35 ~ 186) 152
5965 12:41:13.091710 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5966 12:41:13.095647 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5967 12:41:13.098625 iDelay=199, Bit 3, Center 104 (23 ~ 186) 164
5968 12:41:13.101745 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5969 12:41:13.108672 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5970 12:41:13.111940 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5971 12:41:13.114998 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5972 12:41:13.118705 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5973 12:41:13.121461 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5974 12:41:13.128258 iDelay=199, Bit 10, Center 96 (11 ~ 182) 172
5975 12:41:13.131521 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5976 12:41:13.135066 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5977 12:41:13.138462 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5978 12:41:13.141153 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
5979 12:41:13.148242 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5980 12:41:13.148809 ==
5981 12:41:13.151484 Dram Type= 6, Freq= 0, CH_1, rank 1
5982 12:41:13.154664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5983 12:41:13.155265 ==
5984 12:41:13.155738 DQS Delay:
5985 12:41:13.157712 DQS0 = 0, DQS1 = 0
5986 12:41:13.158173 DQM Delay:
5987 12:41:13.161369 DQM0 = 104, DQM1 = 97
5988 12:41:13.161855 DQ Delay:
5989 12:41:13.164327 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =104
5990 12:41:13.167813 DQ4 =106, DQ5 =114, DQ6 =110, DQ7 =102
5991 12:41:13.171039 DQ8 =84, DQ9 =88, DQ10 =96, DQ11 =92
5992 12:41:13.174426 DQ12 =106, DQ13 =102, DQ14 =102, DQ15 =106
5993 12:41:13.174991
5994 12:41:13.175369
5995 12:41:13.184175 [DQSOSCAuto] RK1, (LSB)MR18= 0x2401, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
5996 12:41:13.187720 CH1 RK1: MR19=505, MR18=2401
5997 12:41:13.194027 CH1_RK1: MR19=0x505, MR18=0x2401, DQSOSC=410, MR23=63, INC=64, DEC=42
5998 12:41:13.194595 [RxdqsGatingPostProcess] freq 933
5999 12:41:13.200835 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6000 12:41:13.204292 best DQS0 dly(2T, 0.5T) = (0, 10)
6001 12:41:13.207450 best DQS1 dly(2T, 0.5T) = (0, 10)
6002 12:41:13.211179 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6003 12:41:13.214604 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6004 12:41:13.217198 best DQS0 dly(2T, 0.5T) = (0, 10)
6005 12:41:13.220944 best DQS1 dly(2T, 0.5T) = (0, 10)
6006 12:41:13.224149 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6007 12:41:13.227616 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6008 12:41:13.230670 Pre-setting of DQS Precalculation
6009 12:41:13.233955 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6010 12:41:13.240736 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6011 12:41:13.247992 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6012 12:41:13.250516
6013 12:41:13.251084
6014 12:41:13.251460 [Calibration Summary] 1866 Mbps
6015 12:41:13.253599 CH 0, Rank 0
6016 12:41:13.254069 SW Impedance : PASS
6017 12:41:13.257238 DUTY Scan : NO K
6018 12:41:13.260498 ZQ Calibration : PASS
6019 12:41:13.261056 Jitter Meter : NO K
6020 12:41:13.263830 CBT Training : PASS
6021 12:41:13.267286 Write leveling : PASS
6022 12:41:13.267755 RX DQS gating : PASS
6023 12:41:13.270140 RX DQ/DQS(RDDQC) : PASS
6024 12:41:13.273831 TX DQ/DQS : PASS
6025 12:41:13.274408 RX DATLAT : PASS
6026 12:41:13.276771 RX DQ/DQS(Engine): PASS
6027 12:41:13.280532 TX OE : NO K
6028 12:41:13.281142 All Pass.
6029 12:41:13.281521
6030 12:41:13.281866 CH 0, Rank 1
6031 12:41:13.283651 SW Impedance : PASS
6032 12:41:13.286897 DUTY Scan : NO K
6033 12:41:13.287474 ZQ Calibration : PASS
6034 12:41:13.289941 Jitter Meter : NO K
6035 12:41:13.293651 CBT Training : PASS
6036 12:41:13.294205 Write leveling : PASS
6037 12:41:13.296716 RX DQS gating : PASS
6038 12:41:13.300171 RX DQ/DQS(RDDQC) : PASS
6039 12:41:13.300753 TX DQ/DQS : PASS
6040 12:41:13.303384 RX DATLAT : PASS
6041 12:41:13.306919 RX DQ/DQS(Engine): PASS
6042 12:41:13.307502 TX OE : NO K
6043 12:41:13.307878 All Pass.
6044 12:41:13.308224
6045 12:41:13.310059 CH 1, Rank 0
6046 12:41:13.313609 SW Impedance : PASS
6047 12:41:13.314182 DUTY Scan : NO K
6048 12:41:13.316650 ZQ Calibration : PASS
6049 12:41:13.317265 Jitter Meter : NO K
6050 12:41:13.319983 CBT Training : PASS
6051 12:41:13.323455 Write leveling : PASS
6052 12:41:13.324027 RX DQS gating : PASS
6053 12:41:13.326369 RX DQ/DQS(RDDQC) : PASS
6054 12:41:13.329502 TX DQ/DQS : PASS
6055 12:41:13.329974 RX DATLAT : PASS
6056 12:41:13.332911 RX DQ/DQS(Engine): PASS
6057 12:41:13.336712 TX OE : NO K
6058 12:41:13.337327 All Pass.
6059 12:41:13.337703
6060 12:41:13.338049 CH 1, Rank 1
6061 12:41:13.339432 SW Impedance : PASS
6062 12:41:13.342874 DUTY Scan : NO K
6063 12:41:13.343340 ZQ Calibration : PASS
6064 12:41:13.346575 Jitter Meter : NO K
6065 12:41:13.349803 CBT Training : PASS
6066 12:41:13.350276 Write leveling : PASS
6067 12:41:13.353147 RX DQS gating : PASS
6068 12:41:13.356869 RX DQ/DQS(RDDQC) : PASS
6069 12:41:13.357480 TX DQ/DQS : PASS
6070 12:41:13.359625 RX DATLAT : PASS
6071 12:41:13.363107 RX DQ/DQS(Engine): PASS
6072 12:41:13.363758 TX OE : NO K
6073 12:41:13.366126 All Pass.
6074 12:41:13.366591
6075 12:41:13.366959 DramC Write-DBI off
6076 12:41:13.369579 PER_BANK_REFRESH: Hybrid Mode
6077 12:41:13.370050 TX_TRACKING: ON
6078 12:41:13.379581 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6079 12:41:13.383103 [FAST_K] Save calibration result to emmc
6080 12:41:13.385716 dramc_set_vcore_voltage set vcore to 650000
6081 12:41:13.389646 Read voltage for 400, 6
6082 12:41:13.390220 Vio18 = 0
6083 12:41:13.393137 Vcore = 650000
6084 12:41:13.393717 Vdram = 0
6085 12:41:13.394100 Vddq = 0
6086 12:41:13.394450 Vmddr = 0
6087 12:41:13.399467 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6088 12:41:13.405773 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6089 12:41:13.406252 MEM_TYPE=3, freq_sel=20
6090 12:41:13.409609 sv_algorithm_assistance_LP4_800
6091 12:41:13.412657 ============ PULL DRAM RESETB DOWN ============
6092 12:41:13.419296 ========== PULL DRAM RESETB DOWN end =========
6093 12:41:13.422630 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6094 12:41:13.426027 ===================================
6095 12:41:13.429648 LPDDR4 DRAM CONFIGURATION
6096 12:41:13.432812 ===================================
6097 12:41:13.433419 EX_ROW_EN[0] = 0x0
6098 12:41:13.436115 EX_ROW_EN[1] = 0x0
6099 12:41:13.436681 LP4Y_EN = 0x0
6100 12:41:13.438964 WORK_FSP = 0x0
6101 12:41:13.442614 WL = 0x2
6102 12:41:13.443181 RL = 0x2
6103 12:41:13.445593 BL = 0x2
6104 12:41:13.446064 RPST = 0x0
6105 12:41:13.449261 RD_PRE = 0x0
6106 12:41:13.449833 WR_PRE = 0x1
6107 12:41:13.452645 WR_PST = 0x0
6108 12:41:13.453253 DBI_WR = 0x0
6109 12:41:13.455576 DBI_RD = 0x0
6110 12:41:13.456141 OTF = 0x1
6111 12:41:13.458624 ===================================
6112 12:41:13.462325 ===================================
6113 12:41:13.465651 ANA top config
6114 12:41:13.468747 ===================================
6115 12:41:13.469263 DLL_ASYNC_EN = 0
6116 12:41:13.472461 ALL_SLAVE_EN = 1
6117 12:41:13.475736 NEW_RANK_MODE = 1
6118 12:41:13.478852 DLL_IDLE_MODE = 1
6119 12:41:13.481887 LP45_APHY_COMB_EN = 1
6120 12:41:13.482364 TX_ODT_DIS = 1
6121 12:41:13.485470 NEW_8X_MODE = 1
6122 12:41:13.488917 ===================================
6123 12:41:13.492123 ===================================
6124 12:41:13.495457 data_rate = 800
6125 12:41:13.498553 CKR = 1
6126 12:41:13.501658 DQ_P2S_RATIO = 4
6127 12:41:13.505151 ===================================
6128 12:41:13.505648 CA_P2S_RATIO = 4
6129 12:41:13.508279 DQ_CA_OPEN = 0
6130 12:41:13.511820 DQ_SEMI_OPEN = 1
6131 12:41:13.515529 CA_SEMI_OPEN = 1
6132 12:41:13.518599 CA_FULL_RATE = 0
6133 12:41:13.521781 DQ_CKDIV4_EN = 0
6134 12:41:13.522503 CA_CKDIV4_EN = 1
6135 12:41:13.524616 CA_PREDIV_EN = 0
6136 12:41:13.528078 PH8_DLY = 0
6137 12:41:13.531755 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6138 12:41:13.535300 DQ_AAMCK_DIV = 0
6139 12:41:13.537994 CA_AAMCK_DIV = 0
6140 12:41:13.538469 CA_ADMCK_DIV = 4
6141 12:41:13.541506 DQ_TRACK_CA_EN = 0
6142 12:41:13.545137 CA_PICK = 800
6143 12:41:13.548412 CA_MCKIO = 400
6144 12:41:13.551400 MCKIO_SEMI = 400
6145 12:41:13.554987 PLL_FREQ = 3016
6146 12:41:13.558275 DQ_UI_PI_RATIO = 32
6147 12:41:13.561367 CA_UI_PI_RATIO = 32
6148 12:41:13.564556 ===================================
6149 12:41:13.568157 ===================================
6150 12:41:13.568725 memory_type:LPDDR4
6151 12:41:13.571076 GP_NUM : 10
6152 12:41:13.574823 SRAM_EN : 1
6153 12:41:13.575508 MD32_EN : 0
6154 12:41:13.578068 ===================================
6155 12:41:13.581342 [ANA_INIT] >>>>>>>>>>>>>>
6156 12:41:13.584356 <<<<<< [CONFIGURE PHASE]: ANA_TX
6157 12:41:13.588055 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6158 12:41:13.591298 ===================================
6159 12:41:13.594571 data_rate = 800,PCW = 0X7400
6160 12:41:13.597594 ===================================
6161 12:41:13.601128 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6162 12:41:13.604076 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6163 12:41:13.617302 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6164 12:41:13.620968 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6165 12:41:13.623802 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6166 12:41:13.627504 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6167 12:41:13.630906 [ANA_INIT] flow start
6168 12:41:13.634203 [ANA_INIT] PLL >>>>>>>>
6169 12:41:13.634679 [ANA_INIT] PLL <<<<<<<<
6170 12:41:13.637870 [ANA_INIT] MIDPI >>>>>>>>
6171 12:41:13.640545 [ANA_INIT] MIDPI <<<<<<<<
6172 12:41:13.641146 [ANA_INIT] DLL >>>>>>>>
6173 12:41:13.643956 [ANA_INIT] flow end
6174 12:41:13.647414 ============ LP4 DIFF to SE enter ============
6175 12:41:13.650415 ============ LP4 DIFF to SE exit ============
6176 12:41:13.653635 [ANA_INIT] <<<<<<<<<<<<<
6177 12:41:13.656935 [Flow] Enable top DCM control >>>>>
6178 12:41:13.660055 [Flow] Enable top DCM control <<<<<
6179 12:41:13.663647 Enable DLL master slave shuffle
6180 12:41:13.670074 ==============================================================
6181 12:41:13.670638 Gating Mode config
6182 12:41:13.677054 ==============================================================
6183 12:41:13.680398 Config description:
6184 12:41:13.686706 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6185 12:41:13.693503 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6186 12:41:13.700255 SELPH_MODE 0: By rank 1: By Phase
6187 12:41:13.706683 ==============================================================
6188 12:41:13.709786 GAT_TRACK_EN = 0
6189 12:41:13.710354 RX_GATING_MODE = 2
6190 12:41:13.713112 RX_GATING_TRACK_MODE = 2
6191 12:41:13.716320 SELPH_MODE = 1
6192 12:41:13.719614 PICG_EARLY_EN = 1
6193 12:41:13.723122 VALID_LAT_VALUE = 1
6194 12:41:13.729449 ==============================================================
6195 12:41:13.733011 Enter into Gating configuration >>>>
6196 12:41:13.736433 Exit from Gating configuration <<<<
6197 12:41:13.739596 Enter into DVFS_PRE_config >>>>>
6198 12:41:13.749582 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6199 12:41:13.752769 Exit from DVFS_PRE_config <<<<<
6200 12:41:13.755831 Enter into PICG configuration >>>>
6201 12:41:13.759655 Exit from PICG configuration <<<<
6202 12:41:13.763025 [RX_INPUT] configuration >>>>>
6203 12:41:13.765834 [RX_INPUT] configuration <<<<<
6204 12:41:13.769512 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6205 12:41:13.776309 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6206 12:41:13.782832 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6207 12:41:13.786175 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6208 12:41:13.792237 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6209 12:41:13.799138 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6210 12:41:13.802564 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6211 12:41:13.809023 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6212 12:41:13.812326 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6213 12:41:13.815830 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6214 12:41:13.819197 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6215 12:41:13.825661 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6216 12:41:13.828677 ===================================
6217 12:41:13.829222 LPDDR4 DRAM CONFIGURATION
6218 12:41:13.832888 ===================================
6219 12:41:13.835489 EX_ROW_EN[0] = 0x0
6220 12:41:13.838857 EX_ROW_EN[1] = 0x0
6221 12:41:13.839418 LP4Y_EN = 0x0
6222 12:41:13.841871 WORK_FSP = 0x0
6223 12:41:13.842345 WL = 0x2
6224 12:41:13.845338 RL = 0x2
6225 12:41:13.845810 BL = 0x2
6226 12:41:13.848924 RPST = 0x0
6227 12:41:13.849488 RD_PRE = 0x0
6228 12:41:13.852242 WR_PRE = 0x1
6229 12:41:13.852802 WR_PST = 0x0
6230 12:41:13.855373 DBI_WR = 0x0
6231 12:41:13.855929 DBI_RD = 0x0
6232 12:41:13.858509 OTF = 0x1
6233 12:41:13.861793 ===================================
6234 12:41:13.865367 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6235 12:41:13.868493 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6236 12:41:13.875389 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6237 12:41:13.878474 ===================================
6238 12:41:13.879036 LPDDR4 DRAM CONFIGURATION
6239 12:41:13.881855 ===================================
6240 12:41:13.885610 EX_ROW_EN[0] = 0x10
6241 12:41:13.888263 EX_ROW_EN[1] = 0x0
6242 12:41:13.888738 LP4Y_EN = 0x0
6243 12:41:13.891901 WORK_FSP = 0x0
6244 12:41:13.892461 WL = 0x2
6245 12:41:13.894882 RL = 0x2
6246 12:41:13.895357 BL = 0x2
6247 12:41:13.898265 RPST = 0x0
6248 12:41:13.898833 RD_PRE = 0x0
6249 12:41:13.901825 WR_PRE = 0x1
6250 12:41:13.902385 WR_PST = 0x0
6251 12:41:13.904677 DBI_WR = 0x0
6252 12:41:13.905189 DBI_RD = 0x0
6253 12:41:13.908652 OTF = 0x1
6254 12:41:13.911699 ===================================
6255 12:41:13.918496 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6256 12:41:13.921589 nWR fixed to 30
6257 12:41:13.924860 [ModeRegInit_LP4] CH0 RK0
6258 12:41:13.925457 [ModeRegInit_LP4] CH0 RK1
6259 12:41:13.928145 [ModeRegInit_LP4] CH1 RK0
6260 12:41:13.931654 [ModeRegInit_LP4] CH1 RK1
6261 12:41:13.932215 match AC timing 19
6262 12:41:13.938052 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6263 12:41:13.941316 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6264 12:41:13.944782 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6265 12:41:13.951182 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6266 12:41:13.954500 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6267 12:41:13.954976 ==
6268 12:41:13.957955 Dram Type= 6, Freq= 0, CH_0, rank 0
6269 12:41:13.961598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6270 12:41:13.962070 ==
6271 12:41:13.967716 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6272 12:41:13.974867 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6273 12:41:13.977541 [CA 0] Center 36 (8~64) winsize 57
6274 12:41:13.981311 [CA 1] Center 36 (8~64) winsize 57
6275 12:41:13.981877 [CA 2] Center 36 (8~64) winsize 57
6276 12:41:13.984555 [CA 3] Center 36 (8~64) winsize 57
6277 12:41:13.987699 [CA 4] Center 36 (8~64) winsize 57
6278 12:41:13.991478 [CA 5] Center 36 (8~64) winsize 57
6279 12:41:13.992042
6280 12:41:13.994464 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6281 12:41:13.997581
6282 12:41:14.000876 [CATrainingPosCal] consider 1 rank data
6283 12:41:14.004111 u2DelayCellTimex100 = 270/100 ps
6284 12:41:14.007795 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 12:41:14.011005 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 12:41:14.014507 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 12:41:14.017160 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 12:41:14.020657 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 12:41:14.024129 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 12:41:14.024712
6291 12:41:14.027241 CA PerBit enable=1, Macro0, CA PI delay=36
6292 12:41:14.027719
6293 12:41:14.030354 [CBTSetCACLKResult] CA Dly = 36
6294 12:41:14.033642 CS Dly: 1 (0~32)
6295 12:41:14.034231 ==
6296 12:41:14.037620 Dram Type= 6, Freq= 0, CH_0, rank 1
6297 12:41:14.040543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6298 12:41:14.041149 ==
6299 12:41:14.047408 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6300 12:41:14.050479 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6301 12:41:14.053816 [CA 0] Center 36 (8~64) winsize 57
6302 12:41:14.057001 [CA 1] Center 36 (8~64) winsize 57
6303 12:41:14.060525 [CA 2] Center 36 (8~64) winsize 57
6304 12:41:14.063993 [CA 3] Center 36 (8~64) winsize 57
6305 12:41:14.066825 [CA 4] Center 36 (8~64) winsize 57
6306 12:41:14.070259 [CA 5] Center 36 (8~64) winsize 57
6307 12:41:14.070735
6308 12:41:14.073365 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6309 12:41:14.073841
6310 12:41:14.076843 [CATrainingPosCal] consider 2 rank data
6311 12:41:14.080575 u2DelayCellTimex100 = 270/100 ps
6312 12:41:14.083670 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 12:41:14.089955 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 12:41:14.093643 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6315 12:41:14.096751 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6316 12:41:14.099864 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6317 12:41:14.103046 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 12:41:14.103526
6319 12:41:14.106939 CA PerBit enable=1, Macro0, CA PI delay=36
6320 12:41:14.107520
6321 12:41:14.109622 [CBTSetCACLKResult] CA Dly = 36
6322 12:41:14.110095 CS Dly: 1 (0~32)
6323 12:41:14.113562
6324 12:41:14.117240 ----->DramcWriteLeveling(PI) begin...
6325 12:41:14.117846 ==
6326 12:41:14.120071 Dram Type= 6, Freq= 0, CH_0, rank 0
6327 12:41:14.123119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6328 12:41:14.123752 ==
6329 12:41:14.126539 Write leveling (Byte 0): 40 => 8
6330 12:41:14.129888 Write leveling (Byte 1): 32 => 0
6331 12:41:14.132825 DramcWriteLeveling(PI) end<-----
6332 12:41:14.133372
6333 12:41:14.133755 ==
6334 12:41:14.136106 Dram Type= 6, Freq= 0, CH_0, rank 0
6335 12:41:14.139466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6336 12:41:14.139944 ==
6337 12:41:14.143148 [Gating] SW mode calibration
6338 12:41:14.149767 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6339 12:41:14.156224 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6340 12:41:14.159361 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6341 12:41:14.162660 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6342 12:41:14.169069 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6343 12:41:14.172388 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6344 12:41:14.175929 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6345 12:41:14.182551 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6346 12:41:14.185745 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6347 12:41:14.189409 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6348 12:41:14.196126 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6349 12:41:14.196701 Total UI for P1: 0, mck2ui 16
6350 12:41:14.202357 best dqsien dly found for B0: ( 0, 14, 24)
6351 12:41:14.202916 Total UI for P1: 0, mck2ui 16
6352 12:41:14.209031 best dqsien dly found for B1: ( 0, 14, 24)
6353 12:41:14.212607 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6354 12:41:14.215925 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6355 12:41:14.216497
6356 12:41:14.219029 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6357 12:41:14.222338 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6358 12:41:14.225977 [Gating] SW calibration Done
6359 12:41:14.226546 ==
6360 12:41:14.228927 Dram Type= 6, Freq= 0, CH_0, rank 0
6361 12:41:14.232106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6362 12:41:14.232567 ==
6363 12:41:14.235614 RX Vref Scan: 0
6364 12:41:14.236073
6365 12:41:14.236434 RX Vref 0 -> 0, step: 1
6366 12:41:14.236771
6367 12:41:14.238984 RX Delay -410 -> 252, step: 16
6368 12:41:14.245298 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6369 12:41:14.248429 iDelay=230, Bit 1, Center -3 (-234 ~ 229) 464
6370 12:41:14.252494 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6371 12:41:14.255503 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6372 12:41:14.262305 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6373 12:41:14.265336 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6374 12:41:14.268370 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6375 12:41:14.271888 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6376 12:41:14.275487 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6377 12:41:14.281826 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6378 12:41:14.285390 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6379 12:41:14.288563 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6380 12:41:14.295012 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6381 12:41:14.298642 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6382 12:41:14.301506 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6383 12:41:14.305036 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6384 12:41:14.308449 ==
6385 12:41:14.308914 Dram Type= 6, Freq= 0, CH_0, rank 0
6386 12:41:14.315263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6387 12:41:14.315819 ==
6388 12:41:14.316191 DQS Delay:
6389 12:41:14.318374 DQS0 = 27, DQS1 = 43
6390 12:41:14.318924 DQM Delay:
6391 12:41:14.321708 DQM0 = 14, DQM1 = 13
6392 12:41:14.322195 DQ Delay:
6393 12:41:14.325228 DQ0 =8, DQ1 =24, DQ2 =8, DQ3 =8
6394 12:41:14.328288 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6395 12:41:14.331405 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6396 12:41:14.334695 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6397 12:41:14.335160
6398 12:41:14.335526
6399 12:41:14.335859 ==
6400 12:41:14.338246 Dram Type= 6, Freq= 0, CH_0, rank 0
6401 12:41:14.341767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6402 12:41:14.342325 ==
6403 12:41:14.342697
6404 12:41:14.343036
6405 12:41:14.345148 TX Vref Scan disable
6406 12:41:14.345702 == TX Byte 0 ==
6407 12:41:14.351461 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6408 12:41:14.355002 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6409 12:41:14.355556 == TX Byte 1 ==
6410 12:41:14.361417 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6411 12:41:14.364597 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6412 12:41:14.365231 ==
6413 12:41:14.367919 Dram Type= 6, Freq= 0, CH_0, rank 0
6414 12:41:14.371765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6415 12:41:14.372327 ==
6416 12:41:14.372700
6417 12:41:14.373073
6418 12:41:14.374689 TX Vref Scan disable
6419 12:41:14.375144 == TX Byte 0 ==
6420 12:41:14.381561 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6421 12:41:14.384419 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6422 12:41:14.384879 == TX Byte 1 ==
6423 12:41:14.391506 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6424 12:41:14.394611 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6425 12:41:14.395165
6426 12:41:14.395530 [DATLAT]
6427 12:41:14.397837 Freq=400, CH0 RK0
6428 12:41:14.398299
6429 12:41:14.398659 DATLAT Default: 0xf
6430 12:41:14.401152 0, 0xFFFF, sum = 0
6431 12:41:14.401707 1, 0xFFFF, sum = 0
6432 12:41:14.404503 2, 0xFFFF, sum = 0
6433 12:41:14.405102 3, 0xFFFF, sum = 0
6434 12:41:14.408209 4, 0xFFFF, sum = 0
6435 12:41:14.411665 5, 0xFFFF, sum = 0
6436 12:41:14.412227 6, 0xFFFF, sum = 0
6437 12:41:14.415119 7, 0xFFFF, sum = 0
6438 12:41:14.415682 8, 0xFFFF, sum = 0
6439 12:41:14.417466 9, 0xFFFF, sum = 0
6440 12:41:14.417932 10, 0xFFFF, sum = 0
6441 12:41:14.421024 11, 0xFFFF, sum = 0
6442 12:41:14.421493 12, 0xFFFF, sum = 0
6443 12:41:14.424038 13, 0x0, sum = 1
6444 12:41:14.424597 14, 0x0, sum = 2
6445 12:41:14.427670 15, 0x0, sum = 3
6446 12:41:14.428230 16, 0x0, sum = 4
6447 12:41:14.430494 best_step = 14
6448 12:41:14.430980
6449 12:41:14.431345 ==
6450 12:41:14.434209 Dram Type= 6, Freq= 0, CH_0, rank 0
6451 12:41:14.437724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6452 12:41:14.438192 ==
6453 12:41:14.438558 RX Vref Scan: 1
6454 12:41:14.440890
6455 12:41:14.441476 RX Vref 0 -> 0, step: 1
6456 12:41:14.441841
6457 12:41:14.443958 RX Delay -327 -> 252, step: 8
6458 12:41:14.444513
6459 12:41:14.447639 Set Vref, RX VrefLevel [Byte0]: 57
6460 12:41:14.450844 [Byte1]: 49
6461 12:41:14.454971
6462 12:41:14.455522 Final RX Vref Byte 0 = 57 to rank0
6463 12:41:14.458888 Final RX Vref Byte 1 = 49 to rank0
6464 12:41:14.461810 Final RX Vref Byte 0 = 57 to rank1
6465 12:41:14.465096 Final RX Vref Byte 1 = 49 to rank1==
6466 12:41:14.468121 Dram Type= 6, Freq= 0, CH_0, rank 0
6467 12:41:14.474842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6468 12:41:14.475401 ==
6469 12:41:14.475770 DQS Delay:
6470 12:41:14.478179 DQS0 = 28, DQS1 = 48
6471 12:41:14.478773 DQM Delay:
6472 12:41:14.479148 DQM0 = 12, DQM1 = 15
6473 12:41:14.481269 DQ Delay:
6474 12:41:14.484360 DQ0 =12, DQ1 =12, DQ2 =12, DQ3 =8
6475 12:41:14.487560 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6476 12:41:14.491125 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6477 12:41:14.494565 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6478 12:41:14.495119
6479 12:41:14.495480
6480 12:41:14.500645 [DQSOSCAuto] RK0, (LSB)MR18= 0xaaa2, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6481 12:41:14.505083 CH0 RK0: MR19=C0C, MR18=AAA2
6482 12:41:14.510927 CH0_RK0: MR19=0xC0C, MR18=0xAAA2, DQSOSC=388, MR23=63, INC=392, DEC=261
6483 12:41:14.511481 ==
6484 12:41:14.514715 Dram Type= 6, Freq= 0, CH_0, rank 1
6485 12:41:14.517630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6486 12:41:14.518196 ==
6487 12:41:14.520422 [Gating] SW mode calibration
6488 12:41:14.527121 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6489 12:41:14.533707 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6490 12:41:14.537469 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6491 12:41:14.540645 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6492 12:41:14.547211 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6493 12:41:14.550348 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6494 12:41:14.553841 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6495 12:41:14.560202 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6496 12:41:14.563848 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6497 12:41:14.567030 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6498 12:41:14.573512 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6499 12:41:14.576682 Total UI for P1: 0, mck2ui 16
6500 12:41:14.580033 best dqsien dly found for B0: ( 0, 14, 24)
6501 12:41:14.583351 Total UI for P1: 0, mck2ui 16
6502 12:41:14.586777 best dqsien dly found for B1: ( 0, 14, 24)
6503 12:41:14.589946 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6504 12:41:14.593223 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6505 12:41:14.593711
6506 12:41:14.596615 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6507 12:41:14.599803 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6508 12:41:14.603311 [Gating] SW calibration Done
6509 12:41:14.603796 ==
6510 12:41:14.606276 Dram Type= 6, Freq= 0, CH_0, rank 1
6511 12:41:14.609774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6512 12:41:14.610264 ==
6513 12:41:14.613151 RX Vref Scan: 0
6514 12:41:14.613737
6515 12:41:14.616190 RX Vref 0 -> 0, step: 1
6516 12:41:14.616772
6517 12:41:14.617303 RX Delay -410 -> 252, step: 16
6518 12:41:14.623066 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6519 12:41:14.626548 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6520 12:41:14.629838 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6521 12:41:14.635940 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6522 12:41:14.639740 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6523 12:41:14.642928 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6524 12:41:14.646289 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6525 12:41:14.652534 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6526 12:41:14.656141 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6527 12:41:14.659598 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6528 12:41:14.662850 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6529 12:41:14.669540 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6530 12:41:14.672609 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6531 12:41:14.675972 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6532 12:41:14.679234 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6533 12:41:14.685676 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6534 12:41:14.686278 ==
6535 12:41:14.689144 Dram Type= 6, Freq= 0, CH_0, rank 1
6536 12:41:14.692444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6537 12:41:14.693052 ==
6538 12:41:14.693437 DQS Delay:
6539 12:41:14.695660 DQS0 = 27, DQS1 = 43
6540 12:41:14.696229 DQM Delay:
6541 12:41:14.698810 DQM0 = 10, DQM1 = 16
6542 12:41:14.699376 DQ Delay:
6543 12:41:14.702140 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6544 12:41:14.705787 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =16
6545 12:41:14.708936 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6546 12:41:14.712291 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6547 12:41:14.712853
6548 12:41:14.713307
6549 12:41:14.713657 ==
6550 12:41:14.715287 Dram Type= 6, Freq= 0, CH_0, rank 1
6551 12:41:14.718579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6552 12:41:14.719052 ==
6553 12:41:14.719423
6554 12:41:14.722242
6555 12:41:14.722805 TX Vref Scan disable
6556 12:41:14.725335 == TX Byte 0 ==
6557 12:41:14.728639 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6558 12:41:14.731856 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6559 12:41:14.734873 == TX Byte 1 ==
6560 12:41:14.738765 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6561 12:41:14.741823 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6562 12:41:14.742423 ==
6563 12:41:14.745431 Dram Type= 6, Freq= 0, CH_0, rank 1
6564 12:41:14.748874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6565 12:41:14.752369 ==
6566 12:41:14.752933
6567 12:41:14.753368
6568 12:41:14.753720 TX Vref Scan disable
6569 12:41:14.754853 == TX Byte 0 ==
6570 12:41:14.758932 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6571 12:41:14.761868 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6572 12:41:14.765430 == TX Byte 1 ==
6573 12:41:14.768242 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6574 12:41:14.772094 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6575 12:41:14.772646
6576 12:41:14.775036 [DATLAT]
6577 12:41:14.775609 Freq=400, CH0 RK1
6578 12:41:14.775986
6579 12:41:14.778450 DATLAT Default: 0xe
6580 12:41:14.779019 0, 0xFFFF, sum = 0
6581 12:41:14.781538 1, 0xFFFF, sum = 0
6582 12:41:14.782017 2, 0xFFFF, sum = 0
6583 12:41:14.785207 3, 0xFFFF, sum = 0
6584 12:41:14.785776 4, 0xFFFF, sum = 0
6585 12:41:14.788397 5, 0xFFFF, sum = 0
6586 12:41:14.789017 6, 0xFFFF, sum = 0
6587 12:41:14.791449 7, 0xFFFF, sum = 0
6588 12:41:14.792030 8, 0xFFFF, sum = 0
6589 12:41:14.794662 9, 0xFFFF, sum = 0
6590 12:41:14.795142 10, 0xFFFF, sum = 0
6591 12:41:14.798362 11, 0xFFFF, sum = 0
6592 12:41:14.798941 12, 0xFFFF, sum = 0
6593 12:41:14.801347 13, 0x0, sum = 1
6594 12:41:14.801827 14, 0x0, sum = 2
6595 12:41:14.804860 15, 0x0, sum = 3
6596 12:41:14.805477 16, 0x0, sum = 4
6597 12:41:14.808034 best_step = 14
6598 12:41:14.808607
6599 12:41:14.809014 ==
6600 12:41:14.811261 Dram Type= 6, Freq= 0, CH_0, rank 1
6601 12:41:14.814971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6602 12:41:14.815445 ==
6603 12:41:14.818096 RX Vref Scan: 0
6604 12:41:14.818661
6605 12:41:14.819040 RX Vref 0 -> 0, step: 1
6606 12:41:14.819398
6607 12:41:14.820967 RX Delay -327 -> 252, step: 8
6608 12:41:14.829566 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6609 12:41:14.832761 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6610 12:41:14.836049 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6611 12:41:14.839085 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6612 12:41:14.846102 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6613 12:41:14.849421 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6614 12:41:14.852497 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6615 12:41:14.856103 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6616 12:41:14.862429 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6617 12:41:14.865776 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6618 12:41:14.869268 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6619 12:41:14.872410 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6620 12:41:14.879057 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6621 12:41:14.882731 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6622 12:41:14.885854 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6623 12:41:14.892188 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6624 12:41:14.892772 ==
6625 12:41:14.895809 Dram Type= 6, Freq= 0, CH_0, rank 1
6626 12:41:14.899241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6627 12:41:14.899957 ==
6628 12:41:14.900352 DQS Delay:
6629 12:41:14.902308 DQS0 = 28, DQS1 = 44
6630 12:41:14.902780 DQM Delay:
6631 12:41:14.905786 DQM0 = 10, DQM1 = 15
6632 12:41:14.906354 DQ Delay:
6633 12:41:14.908931 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =4
6634 12:41:14.912285 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6635 12:41:14.915751 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6636 12:41:14.918955 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6637 12:41:14.919602
6638 12:41:14.919993
6639 12:41:14.925233 [DQSOSCAuto] RK1, (LSB)MR18= 0xc275, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 385 ps
6640 12:41:14.928671 CH0 RK1: MR19=C0C, MR18=C275
6641 12:41:14.935019 CH0_RK1: MR19=0xC0C, MR18=0xC275, DQSOSC=385, MR23=63, INC=398, DEC=265
6642 12:41:14.938554 [RxdqsGatingPostProcess] freq 400
6643 12:41:14.945038 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6644 12:41:14.948678 best DQS0 dly(2T, 0.5T) = (0, 10)
6645 12:41:14.951971 best DQS1 dly(2T, 0.5T) = (0, 10)
6646 12:41:14.952554 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6647 12:41:14.955384 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6648 12:41:14.958374 best DQS0 dly(2T, 0.5T) = (0, 10)
6649 12:41:14.961717 best DQS1 dly(2T, 0.5T) = (0, 10)
6650 12:41:14.965187 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6651 12:41:14.967973 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6652 12:41:14.971757 Pre-setting of DQS Precalculation
6653 12:41:14.977970 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6654 12:41:14.978551 ==
6655 12:41:14.981466 Dram Type= 6, Freq= 0, CH_1, rank 0
6656 12:41:14.984824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6657 12:41:14.985437 ==
6658 12:41:14.991458 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6659 12:41:14.997965 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6660 12:41:15.001352 [CA 0] Center 36 (8~64) winsize 57
6661 12:41:15.001966 [CA 1] Center 36 (8~64) winsize 57
6662 12:41:15.004429 [CA 2] Center 36 (8~64) winsize 57
6663 12:41:15.008053 [CA 3] Center 36 (8~64) winsize 57
6664 12:41:15.011606 [CA 4] Center 36 (8~64) winsize 57
6665 12:41:15.014903 [CA 5] Center 36 (8~64) winsize 57
6666 12:41:15.015485
6667 12:41:15.017638 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6668 12:41:15.018116
6669 12:41:15.024342 [CATrainingPosCal] consider 1 rank data
6670 12:41:15.024922 u2DelayCellTimex100 = 270/100 ps
6671 12:41:15.027859 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 12:41:15.034092 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 12:41:15.037380 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 12:41:15.040868 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 12:41:15.044555 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 12:41:15.047170 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 12:41:15.047732
6678 12:41:15.051024 CA PerBit enable=1, Macro0, CA PI delay=36
6679 12:41:15.051606
6680 12:41:15.053867 [CBTSetCACLKResult] CA Dly = 36
6681 12:41:15.057396 CS Dly: 1 (0~32)
6682 12:41:15.057973 ==
6683 12:41:15.060528 Dram Type= 6, Freq= 0, CH_1, rank 1
6684 12:41:15.064182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6685 12:41:15.064781 ==
6686 12:41:15.070602 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6687 12:41:15.073685 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6688 12:41:15.077312 [CA 0] Center 36 (8~64) winsize 57
6689 12:41:15.080674 [CA 1] Center 36 (8~64) winsize 57
6690 12:41:15.083542 [CA 2] Center 36 (8~64) winsize 57
6691 12:41:15.087182 [CA 3] Center 36 (8~64) winsize 57
6692 12:41:15.090387 [CA 4] Center 36 (8~64) winsize 57
6693 12:41:15.094002 [CA 5] Center 36 (8~64) winsize 57
6694 12:41:15.094584
6695 12:41:15.097217 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6696 12:41:15.097801
6697 12:41:15.100385 [CATrainingPosCal] consider 2 rank data
6698 12:41:15.103765 u2DelayCellTimex100 = 270/100 ps
6699 12:41:15.106642 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 12:41:15.110585 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 12:41:15.116802 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6702 12:41:15.120262 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6703 12:41:15.123410 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6704 12:41:15.126855 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 12:41:15.127452
6706 12:41:15.130145 CA PerBit enable=1, Macro0, CA PI delay=36
6707 12:41:15.130618
6708 12:41:15.133222 [CBTSetCACLKResult] CA Dly = 36
6709 12:41:15.133799 CS Dly: 1 (0~32)
6710 12:41:15.134181
6711 12:41:15.136417 ----->DramcWriteLeveling(PI) begin...
6712 12:41:15.139940 ==
6713 12:41:15.143028 Dram Type= 6, Freq= 0, CH_1, rank 0
6714 12:41:15.146635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6715 12:41:15.147115 ==
6716 12:41:15.149855 Write leveling (Byte 0): 40 => 8
6717 12:41:15.153091 Write leveling (Byte 1): 32 => 0
6718 12:41:15.156390 DramcWriteLeveling(PI) end<-----
6719 12:41:15.156967
6720 12:41:15.157404 ==
6721 12:41:15.159554 Dram Type= 6, Freq= 0, CH_1, rank 0
6722 12:41:15.162891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6723 12:41:15.163370 ==
6724 12:41:15.165980 [Gating] SW mode calibration
6725 12:41:15.172703 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6726 12:41:15.179851 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6727 12:41:15.182852 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6728 12:41:15.186284 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6729 12:41:15.192938 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6730 12:41:15.196042 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6731 12:41:15.199817 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6732 12:41:15.206059 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6733 12:41:15.209300 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6734 12:41:15.212791 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6735 12:41:15.219329 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6736 12:41:15.219908 Total UI for P1: 0, mck2ui 16
6737 12:41:15.222487 best dqsien dly found for B0: ( 0, 14, 24)
6738 12:41:15.225873 Total UI for P1: 0, mck2ui 16
6739 12:41:15.228960 best dqsien dly found for B1: ( 0, 14, 24)
6740 12:41:15.235573 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6741 12:41:15.239418 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6742 12:41:15.239995
6743 12:41:15.242112 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6744 12:41:15.245611 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6745 12:41:15.248878 [Gating] SW calibration Done
6746 12:41:15.249386 ==
6747 12:41:15.252044 Dram Type= 6, Freq= 0, CH_1, rank 0
6748 12:41:15.255474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6749 12:41:15.255950 ==
6750 12:41:15.258782 RX Vref Scan: 0
6751 12:41:15.259354
6752 12:41:15.259735 RX Vref 0 -> 0, step: 1
6753 12:41:15.260090
6754 12:41:15.262139 RX Delay -410 -> 252, step: 16
6755 12:41:15.268401 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6756 12:41:15.271744 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6757 12:41:15.275114 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6758 12:41:15.278797 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6759 12:41:15.285237 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6760 12:41:15.288801 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6761 12:41:15.292158 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6762 12:41:15.295354 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6763 12:41:15.301778 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6764 12:41:15.305089 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6765 12:41:15.308413 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6766 12:41:15.312162 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6767 12:41:15.318675 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6768 12:41:15.321445 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6769 12:41:15.325078 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6770 12:41:15.328715 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6771 12:41:15.331513 ==
6772 12:41:15.334606 Dram Type= 6, Freq= 0, CH_1, rank 0
6773 12:41:15.338168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6774 12:41:15.338642 ==
6775 12:41:15.339014 DQS Delay:
6776 12:41:15.341214 DQS0 = 27, DQS1 = 43
6777 12:41:15.341684 DQM Delay:
6778 12:41:15.345187 DQM0 = 6, DQM1 = 16
6779 12:41:15.345756 DQ Delay:
6780 12:41:15.348416 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6781 12:41:15.351301 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6782 12:41:15.354970 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6783 12:41:15.357828 DQ12 =32, DQ13 =16, DQ14 =16, DQ15 =24
6784 12:41:15.358390
6785 12:41:15.358822
6786 12:41:15.359318 ==
6787 12:41:15.361425 Dram Type= 6, Freq= 0, CH_1, rank 0
6788 12:41:15.364489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6789 12:41:15.364967 ==
6790 12:41:15.365376
6791 12:41:15.365821
6792 12:41:15.367833 TX Vref Scan disable
6793 12:41:15.368299 == TX Byte 0 ==
6794 12:41:15.374300 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6795 12:41:15.377630 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6796 12:41:15.378102 == TX Byte 1 ==
6797 12:41:15.384115 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6798 12:41:15.387732 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6799 12:41:15.388305 ==
6800 12:41:15.391239 Dram Type= 6, Freq= 0, CH_1, rank 0
6801 12:41:15.394400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6802 12:41:15.394979 ==
6803 12:41:15.395359
6804 12:41:15.395709
6805 12:41:15.397681 TX Vref Scan disable
6806 12:41:15.400750 == TX Byte 0 ==
6807 12:41:15.404424 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6808 12:41:15.407348 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6809 12:41:15.410803 == TX Byte 1 ==
6810 12:41:15.414080 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6811 12:41:15.417428 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6812 12:41:15.417907
6813 12:41:15.418281 [DATLAT]
6814 12:41:15.420766 Freq=400, CH1 RK0
6815 12:41:15.421392
6816 12:41:15.424047 DATLAT Default: 0xf
6817 12:41:15.424622 0, 0xFFFF, sum = 0
6818 12:41:15.427393 1, 0xFFFF, sum = 0
6819 12:41:15.427975 2, 0xFFFF, sum = 0
6820 12:41:15.430544 3, 0xFFFF, sum = 0
6821 12:41:15.431024 4, 0xFFFF, sum = 0
6822 12:41:15.434124 5, 0xFFFF, sum = 0
6823 12:41:15.434701 6, 0xFFFF, sum = 0
6824 12:41:15.437334 7, 0xFFFF, sum = 0
6825 12:41:15.437814 8, 0xFFFF, sum = 0
6826 12:41:15.440620 9, 0xFFFF, sum = 0
6827 12:41:15.441252 10, 0xFFFF, sum = 0
6828 12:41:15.444336 11, 0xFFFF, sum = 0
6829 12:41:15.444917 12, 0xFFFF, sum = 0
6830 12:41:15.447355 13, 0x0, sum = 1
6831 12:41:15.447837 14, 0x0, sum = 2
6832 12:41:15.450234 15, 0x0, sum = 3
6833 12:41:15.450820 16, 0x0, sum = 4
6834 12:41:15.453648 best_step = 14
6835 12:41:15.454229
6836 12:41:15.454609 ==
6837 12:41:15.457345 Dram Type= 6, Freq= 0, CH_1, rank 0
6838 12:41:15.459900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6839 12:41:15.460375 ==
6840 12:41:15.463360 RX Vref Scan: 1
6841 12:41:15.463832
6842 12:41:15.464207 RX Vref 0 -> 0, step: 1
6843 12:41:15.464557
6844 12:41:15.467026 RX Delay -327 -> 252, step: 8
6845 12:41:15.467498
6846 12:41:15.469954 Set Vref, RX VrefLevel [Byte0]: 53
6847 12:41:15.473273 [Byte1]: 53
6848 12:41:15.477994
6849 12:41:15.478468 Final RX Vref Byte 0 = 53 to rank0
6850 12:41:15.481041 Final RX Vref Byte 1 = 53 to rank0
6851 12:41:15.484636 Final RX Vref Byte 0 = 53 to rank1
6852 12:41:15.488013 Final RX Vref Byte 1 = 53 to rank1==
6853 12:41:15.491374 Dram Type= 6, Freq= 0, CH_1, rank 0
6854 12:41:15.497635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6855 12:41:15.498192 ==
6856 12:41:15.498574 DQS Delay:
6857 12:41:15.501407 DQS0 = 28, DQS1 = 40
6858 12:41:15.501972 DQM Delay:
6859 12:41:15.502356 DQM0 = 7, DQM1 = 11
6860 12:41:15.504000 DQ Delay:
6861 12:41:15.507411 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6862 12:41:15.507898 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6863 12:41:15.511096 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6864 12:41:15.514434 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6865 12:41:15.514998
6866 12:41:15.517946
6867 12:41:15.524442 [DQSOSCAuto] RK0, (LSB)MR18= 0x99d3, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6868 12:41:15.527674 CH1 RK0: MR19=C0C, MR18=99D3
6869 12:41:15.534270 CH1_RK0: MR19=0xC0C, MR18=0x99D3, DQSOSC=383, MR23=63, INC=402, DEC=268
6870 12:41:15.534841 ==
6871 12:41:15.537204 Dram Type= 6, Freq= 0, CH_1, rank 1
6872 12:41:15.540820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6873 12:41:15.541428 ==
6874 12:41:15.544231 [Gating] SW mode calibration
6875 12:41:15.550680 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6876 12:41:15.557169 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6877 12:41:15.560600 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6878 12:41:15.564519 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6879 12:41:15.570392 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6880 12:41:15.574003 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6881 12:41:15.576780 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6882 12:41:15.583581 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6883 12:41:15.586867 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6884 12:41:15.590447 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6885 12:41:15.596742 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6886 12:41:15.597362 Total UI for P1: 0, mck2ui 16
6887 12:41:15.603306 best dqsien dly found for B0: ( 0, 14, 24)
6888 12:41:15.603865 Total UI for P1: 0, mck2ui 16
6889 12:41:15.610203 best dqsien dly found for B1: ( 0, 14, 24)
6890 12:41:15.613487 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6891 12:41:15.616714 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6892 12:41:15.617326
6893 12:41:15.619942 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6894 12:41:15.622919 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6895 12:41:15.626399 [Gating] SW calibration Done
6896 12:41:15.626970 ==
6897 12:41:15.629792 Dram Type= 6, Freq= 0, CH_1, rank 1
6898 12:41:15.633233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6899 12:41:15.633799 ==
6900 12:41:15.636548 RX Vref Scan: 0
6901 12:41:15.637044
6902 12:41:15.637421 RX Vref 0 -> 0, step: 1
6903 12:41:15.637767
6904 12:41:15.640111 RX Delay -410 -> 252, step: 16
6905 12:41:15.646586 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6906 12:41:15.649731 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6907 12:41:15.653083 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6908 12:41:15.656541 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6909 12:41:15.663118 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6910 12:41:15.666461 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6911 12:41:15.669723 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6912 12:41:15.673286 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6913 12:41:15.679944 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6914 12:41:15.683036 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6915 12:41:15.686177 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6916 12:41:15.689341 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6917 12:41:15.696128 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6918 12:41:15.699394 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6919 12:41:15.702894 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6920 12:41:15.706110 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6921 12:41:15.709603 ==
6922 12:41:15.712497 Dram Type= 6, Freq= 0, CH_1, rank 1
6923 12:41:15.716222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6924 12:41:15.716794 ==
6925 12:41:15.717199 DQS Delay:
6926 12:41:15.719681 DQS0 = 35, DQS1 = 43
6927 12:41:15.720245 DQM Delay:
6928 12:41:15.722760 DQM0 = 17, DQM1 = 20
6929 12:41:15.723328 DQ Delay:
6930 12:41:15.726170 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6931 12:41:15.729436 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6932 12:41:15.732651 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6933 12:41:15.735697 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6934 12:41:15.736163
6935 12:41:15.736528
6936 12:41:15.736870 ==
6937 12:41:15.738876 Dram Type= 6, Freq= 0, CH_1, rank 1
6938 12:41:15.742480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6939 12:41:15.743043 ==
6940 12:41:15.743420
6941 12:41:15.743760
6942 12:41:15.745443 TX Vref Scan disable
6943 12:41:15.745906 == TX Byte 0 ==
6944 12:41:15.752328 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6945 12:41:15.756021 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6946 12:41:15.756587 == TX Byte 1 ==
6947 12:41:15.762705 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6948 12:41:15.765804 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6949 12:41:15.766363 ==
6950 12:41:15.769238 Dram Type= 6, Freq= 0, CH_1, rank 1
6951 12:41:15.772484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6952 12:41:15.773100 ==
6953 12:41:15.773485
6954 12:41:15.773828
6955 12:41:15.775658 TX Vref Scan disable
6956 12:41:15.778898 == TX Byte 0 ==
6957 12:41:15.782403 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6958 12:41:15.785223 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6959 12:41:15.789111 == TX Byte 1 ==
6960 12:41:15.792258 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6961 12:41:15.795471 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6962 12:41:15.796048
6963 12:41:15.796429 [DATLAT]
6964 12:41:15.798744 Freq=400, CH1 RK1
6965 12:41:15.799313
6966 12:41:15.799689 DATLAT Default: 0xe
6967 12:41:15.802032 0, 0xFFFF, sum = 0
6968 12:41:15.802545 1, 0xFFFF, sum = 0
6969 12:41:15.805283 2, 0xFFFF, sum = 0
6970 12:41:15.808743 3, 0xFFFF, sum = 0
6971 12:41:15.809235 4, 0xFFFF, sum = 0
6972 12:41:15.811994 5, 0xFFFF, sum = 0
6973 12:41:15.812464 6, 0xFFFF, sum = 0
6974 12:41:15.815530 7, 0xFFFF, sum = 0
6975 12:41:15.816105 8, 0xFFFF, sum = 0
6976 12:41:15.818652 9, 0xFFFF, sum = 0
6977 12:41:15.819225 10, 0xFFFF, sum = 0
6978 12:41:15.821896 11, 0xFFFF, sum = 0
6979 12:41:15.822372 12, 0xFFFF, sum = 0
6980 12:41:15.825496 13, 0x0, sum = 1
6981 12:41:15.826071 14, 0x0, sum = 2
6982 12:41:15.828603 15, 0x0, sum = 3
6983 12:41:15.829209 16, 0x0, sum = 4
6984 12:41:15.831857 best_step = 14
6985 12:41:15.832374
6986 12:41:15.832780 ==
6987 12:41:15.835154 Dram Type= 6, Freq= 0, CH_1, rank 1
6988 12:41:15.838576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6989 12:41:15.839144 ==
6990 12:41:15.839519 RX Vref Scan: 0
6991 12:41:15.842208
6992 12:41:15.842768 RX Vref 0 -> 0, step: 1
6993 12:41:15.843145
6994 12:41:15.845231 RX Delay -327 -> 252, step: 8
6995 12:41:15.852500 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6996 12:41:15.856137 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6997 12:41:15.859174 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6998 12:41:15.865712 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6999 12:41:15.868966 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
7000 12:41:15.872449 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
7001 12:41:15.875725 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
7002 12:41:15.882355 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
7003 12:41:15.885691 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
7004 12:41:15.888849 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
7005 12:41:15.892004 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
7006 12:41:15.899088 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
7007 12:41:15.902207 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
7008 12:41:15.905417 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
7009 12:41:15.908424 iDelay=217, Bit 14, Center -24 (-255 ~ 208) 464
7010 12:41:15.915304 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
7011 12:41:15.915872 ==
7012 12:41:15.918414 Dram Type= 6, Freq= 0, CH_1, rank 1
7013 12:41:15.922060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7014 12:41:15.922532 ==
7015 12:41:15.922905 DQS Delay:
7016 12:41:15.925102 DQS0 = 32, DQS1 = 36
7017 12:41:15.925569 DQM Delay:
7018 12:41:15.928485 DQM0 = 13, DQM1 = 10
7019 12:41:15.929079 DQ Delay:
7020 12:41:15.931792 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
7021 12:41:15.934807 DQ4 =16, DQ5 =20, DQ6 =20, DQ7 =12
7022 12:41:15.938571 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
7023 12:41:15.941844 DQ12 =16, DQ13 =20, DQ14 =12, DQ15 =20
7024 12:41:15.942415
7025 12:41:15.942788
7026 12:41:15.951753 [DQSOSCAuto] RK1, (LSB)MR18= 0xb159, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 387 ps
7027 12:41:15.952326 CH1 RK1: MR19=C0C, MR18=B159
7028 12:41:15.958311 CH1_RK1: MR19=0xC0C, MR18=0xB159, DQSOSC=387, MR23=63, INC=394, DEC=262
7029 12:41:15.961682 [RxdqsGatingPostProcess] freq 400
7030 12:41:15.967873 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7031 12:41:15.971373 best DQS0 dly(2T, 0.5T) = (0, 10)
7032 12:41:15.974724 best DQS1 dly(2T, 0.5T) = (0, 10)
7033 12:41:15.978070 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7034 12:41:15.981755 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7035 12:41:15.984826 best DQS0 dly(2T, 0.5T) = (0, 10)
7036 12:41:15.985435 best DQS1 dly(2T, 0.5T) = (0, 10)
7037 12:41:15.988147 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7038 12:41:15.990990 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7039 12:41:15.994923 Pre-setting of DQS Precalculation
7040 12:41:16.001608 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7041 12:41:16.008030 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7042 12:41:16.014474 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7043 12:41:16.015042
7044 12:41:16.015414
7045 12:41:16.018003 [Calibration Summary] 800 Mbps
7046 12:41:16.018568 CH 0, Rank 0
7047 12:41:16.021547 SW Impedance : PASS
7048 12:41:16.024456 DUTY Scan : NO K
7049 12:41:16.025043 ZQ Calibration : PASS
7050 12:41:16.027626 Jitter Meter : NO K
7051 12:41:16.031235 CBT Training : PASS
7052 12:41:16.031799 Write leveling : PASS
7053 12:41:16.033997 RX DQS gating : PASS
7054 12:41:16.037814 RX DQ/DQS(RDDQC) : PASS
7055 12:41:16.038379 TX DQ/DQS : PASS
7056 12:41:16.040695 RX DATLAT : PASS
7057 12:41:16.044331 RX DQ/DQS(Engine): PASS
7058 12:41:16.044908 TX OE : NO K
7059 12:41:16.047714 All Pass.
7060 12:41:16.048186
7061 12:41:16.048559 CH 0, Rank 1
7062 12:41:16.051339 SW Impedance : PASS
7063 12:41:16.051913 DUTY Scan : NO K
7064 12:41:16.054401 ZQ Calibration : PASS
7065 12:41:16.057746 Jitter Meter : NO K
7066 12:41:16.058317 CBT Training : PASS
7067 12:41:16.060954 Write leveling : NO K
7068 12:41:16.061565 RX DQS gating : PASS
7069 12:41:16.064272 RX DQ/DQS(RDDQC) : PASS
7070 12:41:16.068104 TX DQ/DQS : PASS
7071 12:41:16.068678 RX DATLAT : PASS
7072 12:41:16.070893 RX DQ/DQS(Engine): PASS
7073 12:41:16.074290 TX OE : NO K
7074 12:41:16.074868 All Pass.
7075 12:41:16.075246
7076 12:41:16.075592 CH 1, Rank 0
7077 12:41:16.077495 SW Impedance : PASS
7078 12:41:16.081015 DUTY Scan : NO K
7079 12:41:16.081492 ZQ Calibration : PASS
7080 12:41:16.084304 Jitter Meter : NO K
7081 12:41:16.087295 CBT Training : PASS
7082 12:41:16.087865 Write leveling : PASS
7083 12:41:16.090418 RX DQS gating : PASS
7084 12:41:16.094342 RX DQ/DQS(RDDQC) : PASS
7085 12:41:16.094916 TX DQ/DQS : PASS
7086 12:41:16.097186 RX DATLAT : PASS
7087 12:41:16.101255 RX DQ/DQS(Engine): PASS
7088 12:41:16.101826 TX OE : NO K
7089 12:41:16.104330 All Pass.
7090 12:41:16.104904
7091 12:41:16.105400 CH 1, Rank 1
7092 12:41:16.107296 SW Impedance : PASS
7093 12:41:16.107870 DUTY Scan : NO K
7094 12:41:16.110865 ZQ Calibration : PASS
7095 12:41:16.113858 Jitter Meter : NO K
7096 12:41:16.114432 CBT Training : PASS
7097 12:41:16.117344 Write leveling : NO K
7098 12:41:16.120776 RX DQS gating : PASS
7099 12:41:16.121395 RX DQ/DQS(RDDQC) : PASS
7100 12:41:16.124020 TX DQ/DQS : PASS
7101 12:41:16.124642 RX DATLAT : PASS
7102 12:41:16.127310 RX DQ/DQS(Engine): PASS
7103 12:41:16.130548 TX OE : NO K
7104 12:41:16.131020 All Pass.
7105 12:41:16.131390
7106 12:41:16.133674 DramC Write-DBI off
7107 12:41:16.134143 PER_BANK_REFRESH: Hybrid Mode
7108 12:41:16.137082 TX_TRACKING: ON
7109 12:41:16.147262 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7110 12:41:16.150826 [FAST_K] Save calibration result to emmc
7111 12:41:16.153910 dramc_set_vcore_voltage set vcore to 725000
7112 12:41:16.154392 Read voltage for 1600, 0
7113 12:41:16.157260 Vio18 = 0
7114 12:41:16.157825 Vcore = 725000
7115 12:41:16.158202 Vdram = 0
7116 12:41:16.160362 Vddq = 0
7117 12:41:16.160926 Vmddr = 0
7118 12:41:16.167051 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7119 12:41:16.170444 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7120 12:41:16.173847 MEM_TYPE=3, freq_sel=13
7121 12:41:16.176910 sv_algorithm_assistance_LP4_3733
7122 12:41:16.180365 ============ PULL DRAM RESETB DOWN ============
7123 12:41:16.183671 ========== PULL DRAM RESETB DOWN end =========
7124 12:41:16.190186 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7125 12:41:16.193701 ===================================
7126 12:41:16.194276 LPDDR4 DRAM CONFIGURATION
7127 12:41:16.196655 ===================================
7128 12:41:16.200366 EX_ROW_EN[0] = 0x0
7129 12:41:16.203455 EX_ROW_EN[1] = 0x0
7130 12:41:16.204027 LP4Y_EN = 0x0
7131 12:41:16.206701 WORK_FSP = 0x1
7132 12:41:16.207176 WL = 0x5
7133 12:41:16.209870 RL = 0x5
7134 12:41:16.210434 BL = 0x2
7135 12:41:16.213549 RPST = 0x0
7136 12:41:16.214116 RD_PRE = 0x0
7137 12:41:16.216782 WR_PRE = 0x1
7138 12:41:16.217376 WR_PST = 0x1
7139 12:41:16.220285 DBI_WR = 0x0
7140 12:41:16.220850 DBI_RD = 0x0
7141 12:41:16.223201 OTF = 0x1
7142 12:41:16.226422 ===================================
7143 12:41:16.229774 ===================================
7144 12:41:16.230260 ANA top config
7145 12:41:16.232775 ===================================
7146 12:41:16.236337 DLL_ASYNC_EN = 0
7147 12:41:16.239456 ALL_SLAVE_EN = 0
7148 12:41:16.243002 NEW_RANK_MODE = 1
7149 12:41:16.243504 DLL_IDLE_MODE = 1
7150 12:41:16.246313 LP45_APHY_COMB_EN = 1
7151 12:41:16.249623 TX_ODT_DIS = 0
7152 12:41:16.252879 NEW_8X_MODE = 1
7153 12:41:16.256206 ===================================
7154 12:41:16.259714 ===================================
7155 12:41:16.263069 data_rate = 3200
7156 12:41:16.263540 CKR = 1
7157 12:41:16.265852 DQ_P2S_RATIO = 8
7158 12:41:16.269321 ===================================
7159 12:41:16.272731 CA_P2S_RATIO = 8
7160 12:41:16.276317 DQ_CA_OPEN = 0
7161 12:41:16.279342 DQ_SEMI_OPEN = 0
7162 12:41:16.282656 CA_SEMI_OPEN = 0
7163 12:41:16.283134 CA_FULL_RATE = 0
7164 12:41:16.285786 DQ_CKDIV4_EN = 0
7165 12:41:16.289901 CA_CKDIV4_EN = 0
7166 12:41:16.292823 CA_PREDIV_EN = 0
7167 12:41:16.296049 PH8_DLY = 12
7168 12:41:16.299242 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7169 12:41:16.299828 DQ_AAMCK_DIV = 4
7170 12:41:16.302797 CA_AAMCK_DIV = 4
7171 12:41:16.305666 CA_ADMCK_DIV = 4
7172 12:41:16.309631 DQ_TRACK_CA_EN = 0
7173 12:41:16.312637 CA_PICK = 1600
7174 12:41:16.316183 CA_MCKIO = 1600
7175 12:41:16.319037 MCKIO_SEMI = 0
7176 12:41:16.319606 PLL_FREQ = 3068
7177 12:41:16.322448 DQ_UI_PI_RATIO = 32
7178 12:41:16.325722 CA_UI_PI_RATIO = 0
7179 12:41:16.329210 ===================================
7180 12:41:16.332473 ===================================
7181 12:41:16.335303 memory_type:LPDDR4
7182 12:41:16.339056 GP_NUM : 10
7183 12:41:16.339625 SRAM_EN : 1
7184 12:41:16.342347 MD32_EN : 0
7185 12:41:16.345353 ===================================
7186 12:41:16.345823 [ANA_INIT] >>>>>>>>>>>>>>
7187 12:41:16.348836 <<<<<< [CONFIGURE PHASE]: ANA_TX
7188 12:41:16.352230 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7189 12:41:16.355552 ===================================
7190 12:41:16.358522 data_rate = 3200,PCW = 0X7600
7191 12:41:16.361750 ===================================
7192 12:41:16.365172 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7193 12:41:16.371833 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7194 12:41:16.378484 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7195 12:41:16.381822 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7196 12:41:16.385432 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7197 12:41:16.388545 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7198 12:41:16.391964 [ANA_INIT] flow start
7199 12:41:16.392531 [ANA_INIT] PLL >>>>>>>>
7200 12:41:16.395456 [ANA_INIT] PLL <<<<<<<<
7201 12:41:16.398419 [ANA_INIT] MIDPI >>>>>>>>
7202 12:41:16.398986 [ANA_INIT] MIDPI <<<<<<<<
7203 12:41:16.401821 [ANA_INIT] DLL >>>>>>>>
7204 12:41:16.404923 [ANA_INIT] DLL <<<<<<<<
7205 12:41:16.405517 [ANA_INIT] flow end
7206 12:41:16.412040 ============ LP4 DIFF to SE enter ============
7207 12:41:16.415379 ============ LP4 DIFF to SE exit ============
7208 12:41:16.418246 [ANA_INIT] <<<<<<<<<<<<<
7209 12:41:16.421658 [Flow] Enable top DCM control >>>>>
7210 12:41:16.425027 [Flow] Enable top DCM control <<<<<
7211 12:41:16.425635 Enable DLL master slave shuffle
7212 12:41:16.431388 ==============================================================
7213 12:41:16.434999 Gating Mode config
7214 12:41:16.438070 ==============================================================
7215 12:41:16.441648 Config description:
7216 12:41:16.451480 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7217 12:41:16.457820 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7218 12:41:16.461041 SELPH_MODE 0: By rank 1: By Phase
7219 12:41:16.468116 ==============================================================
7220 12:41:16.470941 GAT_TRACK_EN = 1
7221 12:41:16.474591 RX_GATING_MODE = 2
7222 12:41:16.477557 RX_GATING_TRACK_MODE = 2
7223 12:41:16.481080 SELPH_MODE = 1
7224 12:41:16.484692 PICG_EARLY_EN = 1
7225 12:41:16.485303 VALID_LAT_VALUE = 1
7226 12:41:16.491282 ==============================================================
7227 12:41:16.494665 Enter into Gating configuration >>>>
7228 12:41:16.497847 Exit from Gating configuration <<<<
7229 12:41:16.501220 Enter into DVFS_PRE_config >>>>>
7230 12:41:16.510869 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7231 12:41:16.514508 Exit from DVFS_PRE_config <<<<<
7232 12:41:16.517428 Enter into PICG configuration >>>>
7233 12:41:16.520887 Exit from PICG configuration <<<<
7234 12:41:16.523925 [RX_INPUT] configuration >>>>>
7235 12:41:16.527601 [RX_INPUT] configuration <<<<<
7236 12:41:16.533709 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7237 12:41:16.537272 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7238 12:41:16.544199 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7239 12:41:16.550166 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7240 12:41:16.556876 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7241 12:41:16.563472 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7242 12:41:16.566417 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7243 12:41:16.569724 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7244 12:41:16.573969 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7245 12:41:16.579639 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7246 12:41:16.583234 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7247 12:41:16.586674 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7248 12:41:16.589862 ===================================
7249 12:41:16.593193 LPDDR4 DRAM CONFIGURATION
7250 12:41:16.596474 ===================================
7251 12:41:16.599919 EX_ROW_EN[0] = 0x0
7252 12:41:16.600488 EX_ROW_EN[1] = 0x0
7253 12:41:16.603230 LP4Y_EN = 0x0
7254 12:41:16.603798 WORK_FSP = 0x1
7255 12:41:16.606118 WL = 0x5
7256 12:41:16.606585 RL = 0x5
7257 12:41:16.609929 BL = 0x2
7258 12:41:16.610494 RPST = 0x0
7259 12:41:16.612862 RD_PRE = 0x0
7260 12:41:16.613455 WR_PRE = 0x1
7261 12:41:16.616572 WR_PST = 0x1
7262 12:41:16.617178 DBI_WR = 0x0
7263 12:41:16.619797 DBI_RD = 0x0
7264 12:41:16.620358 OTF = 0x1
7265 12:41:16.623082 ===================================
7266 12:41:16.629699 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7267 12:41:16.632833 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7268 12:41:16.636336 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7269 12:41:16.639538 ===================================
7270 12:41:16.642447 LPDDR4 DRAM CONFIGURATION
7271 12:41:16.645874 ===================================
7272 12:41:16.649624 EX_ROW_EN[0] = 0x10
7273 12:41:16.650191 EX_ROW_EN[1] = 0x0
7274 12:41:16.652906 LP4Y_EN = 0x0
7275 12:41:16.653503 WORK_FSP = 0x1
7276 12:41:16.656346 WL = 0x5
7277 12:41:16.656916 RL = 0x5
7278 12:41:16.659171 BL = 0x2
7279 12:41:16.659764 RPST = 0x0
7280 12:41:16.662494 RD_PRE = 0x0
7281 12:41:16.663057 WR_PRE = 0x1
7282 12:41:16.665851 WR_PST = 0x1
7283 12:41:16.666412 DBI_WR = 0x0
7284 12:41:16.669157 DBI_RD = 0x0
7285 12:41:16.669627 OTF = 0x1
7286 12:41:16.672329 ===================================
7287 12:41:16.678975 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7288 12:41:16.679541 ==
7289 12:41:16.682732 Dram Type= 6, Freq= 0, CH_0, rank 0
7290 12:41:16.688758 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7291 12:41:16.689381 ==
7292 12:41:16.689878 [Duty_Offset_Calibration]
7293 12:41:16.692377 B0:2 B1:0 CA:1
7294 12:41:16.692944
7295 12:41:16.695341 [DutyScan_Calibration_Flow] k_type=0
7296 12:41:16.704026
7297 12:41:16.704592 ==CLK 0==
7298 12:41:16.707020 Final CLK duty delay cell = -4
7299 12:41:16.710656 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7300 12:41:16.714318 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7301 12:41:16.717181 [-4] AVG Duty = 4906%(X100)
7302 12:41:16.717738
7303 12:41:16.720626 CH0 CLK Duty spec in!! Max-Min= 187%
7304 12:41:16.723935 [DutyScan_Calibration_Flow] ====Done====
7305 12:41:16.724499
7306 12:41:16.726932 [DutyScan_Calibration_Flow] k_type=1
7307 12:41:16.743572
7308 12:41:16.744135 ==DQS 0 ==
7309 12:41:16.746751 Final DQS duty delay cell = 0
7310 12:41:16.750008 [0] MAX Duty = 5249%(X100), DQS PI = 32
7311 12:41:16.753131 [0] MIN Duty = 4969%(X100), DQS PI = 2
7312 12:41:16.756810 [0] AVG Duty = 5109%(X100)
7313 12:41:16.757425
7314 12:41:16.757801 ==DQS 1 ==
7315 12:41:16.759738 Final DQS duty delay cell = -4
7316 12:41:16.763195 [-4] MAX Duty = 5125%(X100), DQS PI = 28
7317 12:41:16.766379 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7318 12:41:16.769581 [-4] AVG Duty = 5000%(X100)
7319 12:41:16.770048
7320 12:41:16.773175 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7321 12:41:16.773737
7322 12:41:16.776266 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7323 12:41:16.779508 [DutyScan_Calibration_Flow] ====Done====
7324 12:41:16.779979
7325 12:41:16.783064 [DutyScan_Calibration_Flow] k_type=3
7326 12:41:16.800234
7327 12:41:16.800837 ==DQM 0 ==
7328 12:41:16.803157 Final DQM duty delay cell = 0
7329 12:41:16.806735 [0] MAX Duty = 5093%(X100), DQS PI = 26
7330 12:41:16.809784 [0] MIN Duty = 4813%(X100), DQS PI = 52
7331 12:41:16.813182 [0] AVG Duty = 4953%(X100)
7332 12:41:16.813752
7333 12:41:16.814129 ==DQM 1 ==
7334 12:41:16.816624 Final DQM duty delay cell = -4
7335 12:41:16.820161 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7336 12:41:16.823590 [-4] MIN Duty = 4751%(X100), DQS PI = 20
7337 12:41:16.826390 [-4] AVG Duty = 4891%(X100)
7338 12:41:16.826860
7339 12:41:16.830163 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7340 12:41:16.830740
7341 12:41:16.833096 CH0 DQM 1 Duty spec in!! Max-Min= 280%
7342 12:41:16.836967 [DutyScan_Calibration_Flow] ====Done====
7343 12:41:16.837579
7344 12:41:16.839718 [DutyScan_Calibration_Flow] k_type=2
7345 12:41:16.857581
7346 12:41:16.858149 ==DQ 0 ==
7347 12:41:16.860961 Final DQ duty delay cell = 0
7348 12:41:16.864055 [0] MAX Duty = 5156%(X100), DQS PI = 36
7349 12:41:16.867450 [0] MIN Duty = 5000%(X100), DQS PI = 16
7350 12:41:16.870756 [0] AVG Duty = 5078%(X100)
7351 12:41:16.871333
7352 12:41:16.871728 ==DQ 1 ==
7353 12:41:16.874188 Final DQ duty delay cell = 0
7354 12:41:16.877187 [0] MAX Duty = 4969%(X100), DQS PI = 44
7355 12:41:16.880492 [0] MIN Duty = 4875%(X100), DQS PI = 10
7356 12:41:16.883550 [0] AVG Duty = 4922%(X100)
7357 12:41:16.884027
7358 12:41:16.887314 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7359 12:41:16.887895
7360 12:41:16.890524 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7361 12:41:16.893406 [DutyScan_Calibration_Flow] ====Done====
7362 12:41:16.893952 ==
7363 12:41:16.897249 Dram Type= 6, Freq= 0, CH_1, rank 0
7364 12:41:16.900257 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7365 12:41:16.900721 ==
7366 12:41:16.903472 [Duty_Offset_Calibration]
7367 12:41:16.903930 B0:0 B1:-1 CA:2
7368 12:41:16.904294
7369 12:41:16.906974 [DutyScan_Calibration_Flow] k_type=0
7370 12:41:16.917922
7371 12:41:16.918492 ==CLK 0==
7372 12:41:16.921215 Final CLK duty delay cell = 0
7373 12:41:16.924543 [0] MAX Duty = 5156%(X100), DQS PI = 10
7374 12:41:16.927716 [0] MIN Duty = 4938%(X100), DQS PI = 44
7375 12:41:16.930841 [0] AVG Duty = 5047%(X100)
7376 12:41:16.931403
7377 12:41:16.934198 CH1 CLK Duty spec in!! Max-Min= 218%
7378 12:41:16.937124 [DutyScan_Calibration_Flow] ====Done====
7379 12:41:16.937597
7380 12:41:16.940585 [DutyScan_Calibration_Flow] k_type=1
7381 12:41:16.957545
7382 12:41:16.958117 ==DQS 0 ==
7383 12:41:16.960904 Final DQS duty delay cell = 0
7384 12:41:16.964272 [0] MAX Duty = 5124%(X100), DQS PI = 26
7385 12:41:16.967273 [0] MIN Duty = 5000%(X100), DQS PI = 0
7386 12:41:16.970547 [0] AVG Duty = 5062%(X100)
7387 12:41:16.971010
7388 12:41:16.971375 ==DQS 1 ==
7389 12:41:16.973961 Final DQS duty delay cell = 0
7390 12:41:16.977354 [0] MAX Duty = 5187%(X100), DQS PI = 0
7391 12:41:16.981061 [0] MIN Duty = 4844%(X100), DQS PI = 34
7392 12:41:16.983692 [0] AVG Duty = 5015%(X100)
7393 12:41:16.984157
7394 12:41:16.987098 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7395 12:41:16.987662
7396 12:41:16.990502 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7397 12:41:16.993930 [DutyScan_Calibration_Flow] ====Done====
7398 12:41:16.994500
7399 12:41:16.996720 [DutyScan_Calibration_Flow] k_type=3
7400 12:41:17.015107
7401 12:41:17.015670 ==DQM 0 ==
7402 12:41:17.018316 Final DQM duty delay cell = 4
7403 12:41:17.021578 [4] MAX Duty = 5125%(X100), DQS PI = 8
7404 12:41:17.025096 [4] MIN Duty = 5000%(X100), DQS PI = 30
7405 12:41:17.028503 [4] AVG Duty = 5062%(X100)
7406 12:41:17.029105
7407 12:41:17.029479 ==DQM 1 ==
7408 12:41:17.031551 Final DQM duty delay cell = 0
7409 12:41:17.034768 [0] MAX Duty = 5281%(X100), DQS PI = 58
7410 12:41:17.038244 [0] MIN Duty = 4907%(X100), DQS PI = 34
7411 12:41:17.041384 [0] AVG Duty = 5094%(X100)
7412 12:41:17.041851
7413 12:41:17.044777 CH1 DQM 0 Duty spec in!! Max-Min= 125%
7414 12:41:17.045375
7415 12:41:17.048189 CH1 DQM 1 Duty spec in!! Max-Min= 374%
7416 12:41:17.051888 [DutyScan_Calibration_Flow] ====Done====
7417 12:41:17.052466
7418 12:41:17.054906 [DutyScan_Calibration_Flow] k_type=2
7419 12:41:17.072053
7420 12:41:17.072632 ==DQ 0 ==
7421 12:41:17.075443 Final DQ duty delay cell = 0
7422 12:41:17.078578 [0] MAX Duty = 5093%(X100), DQS PI = 20
7423 12:41:17.082035 [0] MIN Duty = 5000%(X100), DQS PI = 30
7424 12:41:17.082656 [0] AVG Duty = 5046%(X100)
7425 12:41:17.085083
7426 12:41:17.085557 ==DQ 1 ==
7427 12:41:17.088853 Final DQ duty delay cell = 0
7428 12:41:17.091752 [0] MAX Duty = 5062%(X100), DQS PI = 2
7429 12:41:17.094993 [0] MIN Duty = 4844%(X100), DQS PI = 32
7430 12:41:17.095518 [0] AVG Duty = 4953%(X100)
7431 12:41:17.098484
7432 12:41:17.101465 CH1 DQ 0 Duty spec in!! Max-Min= 93%
7433 12:41:17.101945
7434 12:41:17.105317 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7435 12:41:17.108155 [DutyScan_Calibration_Flow] ====Done====
7436 12:41:17.111579 nWR fixed to 30
7437 12:41:17.112055 [ModeRegInit_LP4] CH0 RK0
7438 12:41:17.114552 [ModeRegInit_LP4] CH0 RK1
7439 12:41:17.118114 [ModeRegInit_LP4] CH1 RK0
7440 12:41:17.121378 [ModeRegInit_LP4] CH1 RK1
7441 12:41:17.121969 match AC timing 5
7442 12:41:17.127837 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7443 12:41:17.131051 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7444 12:41:17.135344 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7445 12:41:17.141214 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7446 12:41:17.144846 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7447 12:41:17.145456 [MiockJmeterHQA]
7448 12:41:17.145839
7449 12:41:17.147773 [DramcMiockJmeter] u1RxGatingPI = 0
7450 12:41:17.151018 0 : 4257, 4030
7451 12:41:17.151499 4 : 4363, 4137
7452 12:41:17.155252 8 : 4253, 4026
7453 12:41:17.155831 12 : 4253, 4027
7454 12:41:17.156222 16 : 4253, 4026
7455 12:41:17.157483 20 : 4363, 4137
7456 12:41:17.157963 24 : 4253, 4027
7457 12:41:17.161209 28 : 4252, 4027
7458 12:41:17.161788 32 : 4253, 4027
7459 12:41:17.164414 36 : 4255, 4029
7460 12:41:17.165018 40 : 4252, 4027
7461 12:41:17.167440 44 : 4363, 4137
7462 12:41:17.167919 48 : 4363, 4138
7463 12:41:17.168296 52 : 4253, 4026
7464 12:41:17.170971 56 : 4253, 4027
7465 12:41:17.171453 60 : 4253, 4026
7466 12:41:17.174562 64 : 4253, 4026
7467 12:41:17.175144 68 : 4250, 4027
7468 12:41:17.177547 72 : 4252, 4027
7469 12:41:17.178121 76 : 4252, 4027
7470 12:41:17.180899 80 : 4250, 4026
7471 12:41:17.181521 84 : 4250, 4026
7472 12:41:17.181908 88 : 4252, 3611
7473 12:41:17.184180 92 : 4252, 0
7474 12:41:17.184666 96 : 4250, 0
7475 12:41:17.187751 100 : 4253, 0
7476 12:41:17.188341 104 : 4252, 0
7477 12:41:17.188731 108 : 4249, 0
7478 12:41:17.190855 112 : 4250, 0
7479 12:41:17.191440 116 : 4253, 0
7480 12:41:17.193729 120 : 4253, 0
7481 12:41:17.194215 124 : 4255, 0
7482 12:41:17.194598 128 : 4255, 0
7483 12:41:17.197183 132 : 4252, 0
7484 12:41:17.197667 136 : 4361, 0
7485 12:41:17.200654 140 : 4361, 0
7486 12:41:17.201423 144 : 4250, 0
7487 12:41:17.201934 148 : 4249, 0
7488 12:41:17.203714 152 : 4250, 0
7489 12:41:17.204195 156 : 4253, 0
7490 12:41:17.204580 160 : 4249, 0
7491 12:41:17.207607 164 : 4361, 0
7492 12:41:17.208274 168 : 4250, 0
7493 12:41:17.210372 172 : 4363, 0
7494 12:41:17.210859 176 : 4250, 0
7495 12:41:17.211240 180 : 4250, 0
7496 12:41:17.213919 184 : 4255, 0
7497 12:41:17.214525 188 : 4249, 0
7498 12:41:17.217285 192 : 4363, 0
7499 12:41:17.217888 196 : 4255, 0
7500 12:41:17.218285 200 : 4250, 6
7501 12:41:17.220378 204 : 4250, 2589
7502 12:41:17.220959 208 : 4363, 4140
7503 12:41:17.223873 212 : 4253, 4026
7504 12:41:17.224486 216 : 4250, 4026
7505 12:41:17.227117 220 : 4250, 4027
7506 12:41:17.227706 224 : 4250, 4026
7507 12:41:17.230310 228 : 4249, 4027
7508 12:41:17.230793 232 : 4250, 4027
7509 12:41:17.233240 236 : 4250, 4027
7510 12:41:17.233724 240 : 4250, 4027
7511 12:41:17.236933 244 : 4250, 4027
7512 12:41:17.237458 248 : 4250, 4026
7513 12:41:17.239894 252 : 4253, 4029
7514 12:41:17.240447 256 : 4250, 4027
7515 12:41:17.240850 260 : 4250, 4027
7516 12:41:17.243443 264 : 4360, 4137
7517 12:41:17.244031 268 : 4250, 4026
7518 12:41:17.246873 272 : 4361, 4137
7519 12:41:17.247463 276 : 4250, 4027
7520 12:41:17.250215 280 : 4252, 4027
7521 12:41:17.250799 284 : 4250, 4027
7522 12:41:17.253470 288 : 4250, 4027
7523 12:41:17.253949 292 : 4250, 4027
7524 12:41:17.256830 296 : 4254, 4029
7525 12:41:17.257441 300 : 4250, 4026
7526 12:41:17.260156 304 : 4253, 4029
7527 12:41:17.260739 308 : 4250, 4027
7528 12:41:17.263772 312 : 4254, 3898
7529 12:41:17.264359 316 : 4360, 2147
7530 12:41:17.264745
7531 12:41:17.266802 MIOCK jitter meter ch=0
7532 12:41:17.267277
7533 12:41:17.269644 1T = (316-92) = 224 dly cells
7534 12:41:17.273152 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7535 12:41:17.273628 ==
7536 12:41:17.276472 Dram Type= 6, Freq= 0, CH_0, rank 0
7537 12:41:17.283224 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7538 12:41:17.283854 ==
7539 12:41:17.286588 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7540 12:41:17.293510 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7541 12:41:17.296677 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7542 12:41:17.303092 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7543 12:41:17.310766 [CA 0] Center 43 (13~73) winsize 61
7544 12:41:17.314106 [CA 1] Center 43 (13~73) winsize 61
7545 12:41:17.317341 [CA 2] Center 38 (8~68) winsize 61
7546 12:41:17.320388 [CA 3] Center 37 (8~67) winsize 60
7547 12:41:17.323946 [CA 4] Center 36 (6~66) winsize 61
7548 12:41:17.327287 [CA 5] Center 35 (5~65) winsize 61
7549 12:41:17.327922
7550 12:41:17.330406 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7551 12:41:17.330892
7552 12:41:17.337025 [CATrainingPosCal] consider 1 rank data
7553 12:41:17.337618 u2DelayCellTimex100 = 290/100 ps
7554 12:41:17.343561 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7555 12:41:17.347210 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7556 12:41:17.350735 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7557 12:41:17.353497 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7558 12:41:17.357132 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7559 12:41:17.360208 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7560 12:41:17.360788
7561 12:41:17.363455 CA PerBit enable=1, Macro0, CA PI delay=35
7562 12:41:17.364032
7563 12:41:17.366568 [CBTSetCACLKResult] CA Dly = 35
7564 12:41:17.370065 CS Dly: 9 (0~40)
7565 12:41:17.373565 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7566 12:41:17.376627 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7567 12:41:17.377229 ==
7568 12:41:17.379894 Dram Type= 6, Freq= 0, CH_0, rank 1
7569 12:41:17.386767 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7570 12:41:17.387347 ==
7571 12:41:17.389618 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7572 12:41:17.396813 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7573 12:41:17.399613 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7574 12:41:17.406202 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7575 12:41:17.414357 [CA 0] Center 44 (14~74) winsize 61
7576 12:41:17.417794 [CA 1] Center 43 (13~73) winsize 61
7577 12:41:17.420932 [CA 2] Center 38 (9~68) winsize 60
7578 12:41:17.424438 [CA 3] Center 38 (9~68) winsize 60
7579 12:41:17.427616 [CA 4] Center 37 (7~67) winsize 61
7580 12:41:17.430945 [CA 5] Center 36 (6~66) winsize 61
7581 12:41:17.431424
7582 12:41:17.434064 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7583 12:41:17.434798
7584 12:41:17.440231 [CATrainingPosCal] consider 2 rank data
7585 12:41:17.440830 u2DelayCellTimex100 = 290/100 ps
7586 12:41:17.447082 CA0 delay=43 (14~73),Diff = 8 PI (26 cell)
7587 12:41:17.450016 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7588 12:41:17.453299 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7589 12:41:17.457017 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7590 12:41:17.460575 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7591 12:41:17.463896 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7592 12:41:17.464477
7593 12:41:17.466803 CA PerBit enable=1, Macro0, CA PI delay=35
7594 12:41:17.467383
7595 12:41:17.469991 [CBTSetCACLKResult] CA Dly = 35
7596 12:41:17.473753 CS Dly: 10 (0~43)
7597 12:41:17.476668 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7598 12:41:17.480469 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7599 12:41:17.481089
7600 12:41:17.483479 ----->DramcWriteLeveling(PI) begin...
7601 12:41:17.483965 ==
7602 12:41:17.486780 Dram Type= 6, Freq= 0, CH_0, rank 0
7603 12:41:17.493479 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7604 12:41:17.494063 ==
7605 12:41:17.496878 Write leveling (Byte 0): 37 => 37
7606 12:41:17.500173 Write leveling (Byte 1): 30 => 30
7607 12:41:17.500753 DramcWriteLeveling(PI) end<-----
7608 12:41:17.503594
7609 12:41:17.504169 ==
7610 12:41:17.506364 Dram Type= 6, Freq= 0, CH_0, rank 0
7611 12:41:17.509587 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7612 12:41:17.510068 ==
7613 12:41:17.513285 [Gating] SW mode calibration
7614 12:41:17.520131 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7615 12:41:17.523133 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7616 12:41:17.529770 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7617 12:41:17.533594 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7618 12:41:17.536452 1 4 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7619 12:41:17.543234 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7620 12:41:17.546305 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7621 12:41:17.549851 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7622 12:41:17.556606 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7623 12:41:17.559348 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7624 12:41:17.562889 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7625 12:41:17.569467 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7626 12:41:17.573012 1 5 8 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
7627 12:41:17.576205 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7628 12:41:17.582853 1 5 16 | B1->B0 | 3333 2323 | 0 0 | (0 0) (1 0)
7629 12:41:17.585922 1 5 20 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
7630 12:41:17.589519 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7631 12:41:17.596196 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7632 12:41:17.599516 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7633 12:41:17.603275 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7634 12:41:17.609335 1 6 8 | B1->B0 | 2323 3d3d | 0 1 | (0 0) (0 0)
7635 12:41:17.612411 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7636 12:41:17.615507 1 6 16 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
7637 12:41:17.622570 1 6 20 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7638 12:41:17.625782 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7639 12:41:17.629416 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7640 12:41:17.636220 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7641 12:41:17.638865 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7642 12:41:17.642430 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7643 12:41:17.648722 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7644 12:41:17.651848 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7645 12:41:17.655459 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7646 12:41:17.662148 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7647 12:41:17.665356 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 12:41:17.668294 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 12:41:17.675320 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 12:41:17.679179 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 12:41:17.682134 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 12:41:17.688806 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 12:41:17.691987 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 12:41:17.695207 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 12:41:17.701913 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 12:41:17.705180 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 12:41:17.708534 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 12:41:17.715123 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7659 12:41:17.718600 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7660 12:41:17.721824 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7661 12:41:17.724837 Total UI for P1: 0, mck2ui 16
7662 12:41:17.728381 best dqsien dly found for B0: ( 1, 9, 10)
7663 12:41:17.734861 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7664 12:41:17.738034 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7665 12:41:17.741360 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7666 12:41:17.744546 Total UI for P1: 0, mck2ui 16
7667 12:41:17.747773 best dqsien dly found for B1: ( 1, 9, 20)
7668 12:41:17.751445 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7669 12:41:17.754027 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7670 12:41:17.754497
7671 12:41:17.761300 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7672 12:41:17.764050 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7673 12:41:17.767527 [Gating] SW calibration Done
7674 12:41:17.768091 ==
7675 12:41:17.770668 Dram Type= 6, Freq= 0, CH_0, rank 0
7676 12:41:17.774099 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7677 12:41:17.774695 ==
7678 12:41:17.775181 RX Vref Scan: 0
7679 12:41:17.775625
7680 12:41:17.777455 RX Vref 0 -> 0, step: 1
7681 12:41:17.777934
7682 12:41:17.780726 RX Delay 0 -> 252, step: 8
7683 12:41:17.784227 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7684 12:41:17.787568 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7685 12:41:17.794164 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7686 12:41:17.797490 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7687 12:41:17.800892 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7688 12:41:17.803945 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7689 12:41:17.807556 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7690 12:41:17.810333 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7691 12:41:17.817420 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7692 12:41:17.820591 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7693 12:41:17.824059 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7694 12:41:17.826959 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7695 12:41:17.833867 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7696 12:41:17.836969 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7697 12:41:17.840193 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7698 12:41:17.843582 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7699 12:41:17.844167 ==
7700 12:41:17.846688 Dram Type= 6, Freq= 0, CH_0, rank 0
7701 12:41:17.850198 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7702 12:41:17.853527 ==
7703 12:41:17.854010 DQS Delay:
7704 12:41:17.854571 DQS0 = 0, DQS1 = 0
7705 12:41:17.856555 DQM Delay:
7706 12:41:17.857100 DQM0 = 138, DQM1 = 126
7707 12:41:17.860322 DQ Delay:
7708 12:41:17.863500 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7709 12:41:17.866448 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7710 12:41:17.869927 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7711 12:41:17.873275 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7712 12:41:17.873800
7713 12:41:17.874280
7714 12:41:17.874733 ==
7715 12:41:17.876355 Dram Type= 6, Freq= 0, CH_0, rank 0
7716 12:41:17.879911 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7717 12:41:17.883385 ==
7718 12:41:17.883987
7719 12:41:17.884478
7720 12:41:17.884932 TX Vref Scan disable
7721 12:41:17.886514 == TX Byte 0 ==
7722 12:41:17.889467 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7723 12:41:17.893137 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7724 12:41:17.896592 == TX Byte 1 ==
7725 12:41:17.899559 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7726 12:41:17.903217 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7727 12:41:17.906765 ==
7728 12:41:17.909536 Dram Type= 6, Freq= 0, CH_0, rank 0
7729 12:41:17.912942 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7730 12:41:17.913543 ==
7731 12:41:17.925877
7732 12:41:17.928858 TX Vref early break, caculate TX vref
7733 12:41:17.932253 TX Vref=16, minBit 7, minWin=22, winSum=377
7734 12:41:17.935306 TX Vref=18, minBit 12, minWin=23, winSum=390
7735 12:41:17.938755 TX Vref=20, minBit 0, minWin=24, winSum=399
7736 12:41:17.941878 TX Vref=22, minBit 7, minWin=24, winSum=405
7737 12:41:17.945681 TX Vref=24, minBit 0, minWin=25, winSum=414
7738 12:41:17.952329 TX Vref=26, minBit 2, minWin=25, winSum=424
7739 12:41:17.954976 TX Vref=28, minBit 0, minWin=26, winSum=430
7740 12:41:17.958575 TX Vref=30, minBit 0, minWin=26, winSum=424
7741 12:41:17.961525 TX Vref=32, minBit 0, minWin=25, winSum=418
7742 12:41:17.965124 TX Vref=34, minBit 0, minWin=25, winSum=407
7743 12:41:17.971488 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 28
7744 12:41:17.972072
7745 12:41:17.974842 Final TX Range 0 Vref 28
7746 12:41:17.975322
7747 12:41:17.975691 ==
7748 12:41:17.978069 Dram Type= 6, Freq= 0, CH_0, rank 0
7749 12:41:17.981339 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7750 12:41:17.981815 ==
7751 12:41:17.982191
7752 12:41:17.982538
7753 12:41:17.984889 TX Vref Scan disable
7754 12:41:17.991452 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7755 12:41:17.991930 == TX Byte 0 ==
7756 12:41:17.994906 u2DelayCellOfst[0]=13 cells (4 PI)
7757 12:41:17.997628 u2DelayCellOfst[1]=20 cells (6 PI)
7758 12:41:18.001250 u2DelayCellOfst[2]=13 cells (4 PI)
7759 12:41:18.004793 u2DelayCellOfst[3]=13 cells (4 PI)
7760 12:41:18.007782 u2DelayCellOfst[4]=10 cells (3 PI)
7761 12:41:18.011120 u2DelayCellOfst[5]=0 cells (0 PI)
7762 12:41:18.014499 u2DelayCellOfst[6]=20 cells (6 PI)
7763 12:41:18.017841 u2DelayCellOfst[7]=16 cells (5 PI)
7764 12:41:18.021406 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7765 12:41:18.024503 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7766 12:41:18.027753 == TX Byte 1 ==
7767 12:41:18.030959 u2DelayCellOfst[8]=0 cells (0 PI)
7768 12:41:18.034648 u2DelayCellOfst[9]=0 cells (0 PI)
7769 12:41:18.037343 u2DelayCellOfst[10]=6 cells (2 PI)
7770 12:41:18.040809 u2DelayCellOfst[11]=3 cells (1 PI)
7771 12:41:18.041458 u2DelayCellOfst[12]=10 cells (3 PI)
7772 12:41:18.044377 u2DelayCellOfst[13]=10 cells (3 PI)
7773 12:41:18.047469 u2DelayCellOfst[14]=13 cells (4 PI)
7774 12:41:18.050746 u2DelayCellOfst[15]=10 cells (3 PI)
7775 12:41:18.057660 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7776 12:41:18.060713 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7777 12:41:18.061325 DramC Write-DBI on
7778 12:41:18.063925 ==
7779 12:41:18.067271 Dram Type= 6, Freq= 0, CH_0, rank 0
7780 12:41:18.070858 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7781 12:41:18.071337 ==
7782 12:41:18.071710
7783 12:41:18.072130
7784 12:41:18.074025 TX Vref Scan disable
7785 12:41:18.074527 == TX Byte 0 ==
7786 12:41:18.080510 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7787 12:41:18.081114 == TX Byte 1 ==
7788 12:41:18.083850 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7789 12:41:18.087030 DramC Write-DBI off
7790 12:41:18.087531
7791 12:41:18.087902 [DATLAT]
7792 12:41:18.090379 Freq=1600, CH0 RK0
7793 12:41:18.090953
7794 12:41:18.091332 DATLAT Default: 0xf
7795 12:41:18.093642 0, 0xFFFF, sum = 0
7796 12:41:18.094123 1, 0xFFFF, sum = 0
7797 12:41:18.096964 2, 0xFFFF, sum = 0
7798 12:41:18.097483 3, 0xFFFF, sum = 0
7799 12:41:18.100531 4, 0xFFFF, sum = 0
7800 12:41:18.101145 5, 0xFFFF, sum = 0
7801 12:41:18.103527 6, 0xFFFF, sum = 0
7802 12:41:18.107254 7, 0xFFFF, sum = 0
7803 12:41:18.107837 8, 0xFFFF, sum = 0
7804 12:41:18.110237 9, 0xFFFF, sum = 0
7805 12:41:18.110716 10, 0xFFFF, sum = 0
7806 12:41:18.113473 11, 0xFFFF, sum = 0
7807 12:41:18.114048 12, 0xFFFF, sum = 0
7808 12:41:18.116931 13, 0xFFFF, sum = 0
7809 12:41:18.117578 14, 0x0, sum = 1
7810 12:41:18.120421 15, 0x0, sum = 2
7811 12:41:18.121041 16, 0x0, sum = 3
7812 12:41:18.124252 17, 0x0, sum = 4
7813 12:41:18.124823 best_step = 15
7814 12:41:18.125296
7815 12:41:18.125652 ==
7816 12:41:18.126614 Dram Type= 6, Freq= 0, CH_0, rank 0
7817 12:41:18.130078 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7818 12:41:18.133416 ==
7819 12:41:18.133982 RX Vref Scan: 1
7820 12:41:18.134356
7821 12:41:18.137063 Set Vref Range= 24 -> 127
7822 12:41:18.137628
7823 12:41:18.138006 RX Vref 24 -> 127, step: 1
7824 12:41:18.139837
7825 12:41:18.140308 RX Delay 19 -> 252, step: 4
7826 12:41:18.140695
7827 12:41:18.143135 Set Vref, RX VrefLevel [Byte0]: 24
7828 12:41:18.146936 [Byte1]: 24
7829 12:41:18.150630
7830 12:41:18.151193 Set Vref, RX VrefLevel [Byte0]: 25
7831 12:41:18.156529 [Byte1]: 25
7832 12:41:18.157027
7833 12:41:18.160294 Set Vref, RX VrefLevel [Byte0]: 26
7834 12:41:18.163678 [Byte1]: 26
7835 12:41:18.164246
7836 12:41:18.166969 Set Vref, RX VrefLevel [Byte0]: 27
7837 12:41:18.169984 [Byte1]: 27
7838 12:41:18.170460
7839 12:41:18.173181 Set Vref, RX VrefLevel [Byte0]: 28
7840 12:41:18.176642 [Byte1]: 28
7841 12:41:18.180740
7842 12:41:18.181341 Set Vref, RX VrefLevel [Byte0]: 29
7843 12:41:18.184044 [Byte1]: 29
7844 12:41:18.187877
7845 12:41:18.188357 Set Vref, RX VrefLevel [Byte0]: 30
7846 12:41:18.191281 [Byte1]: 30
7847 12:41:18.195730
7848 12:41:18.196296 Set Vref, RX VrefLevel [Byte0]: 31
7849 12:41:18.199020 [Byte1]: 31
7850 12:41:18.203558
7851 12:41:18.204116 Set Vref, RX VrefLevel [Byte0]: 32
7852 12:41:18.206625 [Byte1]: 32
7853 12:41:18.210802
7854 12:41:18.211270 Set Vref, RX VrefLevel [Byte0]: 33
7855 12:41:18.214612 [Byte1]: 33
7856 12:41:18.218781
7857 12:41:18.219351 Set Vref, RX VrefLevel [Byte0]: 34
7858 12:41:18.221684 [Byte1]: 34
7859 12:41:18.226380
7860 12:41:18.226956 Set Vref, RX VrefLevel [Byte0]: 35
7861 12:41:18.229447 [Byte1]: 35
7862 12:41:18.233755
7863 12:41:18.234317 Set Vref, RX VrefLevel [Byte0]: 36
7864 12:41:18.237087 [Byte1]: 36
7865 12:41:18.241555
7866 12:41:18.242124 Set Vref, RX VrefLevel [Byte0]: 37
7867 12:41:18.244212 [Byte1]: 37
7868 12:41:18.248599
7869 12:41:18.249195 Set Vref, RX VrefLevel [Byte0]: 38
7870 12:41:18.252021 [Byte1]: 38
7871 12:41:18.256823
7872 12:41:18.257422 Set Vref, RX VrefLevel [Byte0]: 39
7873 12:41:18.259710 [Byte1]: 39
7874 12:41:18.263951
7875 12:41:18.264521 Set Vref, RX VrefLevel [Byte0]: 40
7876 12:41:18.267137 [Byte1]: 40
7877 12:41:18.271958
7878 12:41:18.272522 Set Vref, RX VrefLevel [Byte0]: 41
7879 12:41:18.274502 [Byte1]: 41
7880 12:41:18.279227
7881 12:41:18.279814 Set Vref, RX VrefLevel [Byte0]: 42
7882 12:41:18.282489 [Byte1]: 42
7883 12:41:18.287161
7884 12:41:18.287778 Set Vref, RX VrefLevel [Byte0]: 43
7885 12:41:18.289921 [Byte1]: 43
7886 12:41:18.294011
7887 12:41:18.294478 Set Vref, RX VrefLevel [Byte0]: 44
7888 12:41:18.297394 [Byte1]: 44
7889 12:41:18.301772
7890 12:41:18.302342 Set Vref, RX VrefLevel [Byte0]: 45
7891 12:41:18.305362 [Byte1]: 45
7892 12:41:18.309146
7893 12:41:18.309734 Set Vref, RX VrefLevel [Byte0]: 46
7894 12:41:18.312463 [Byte1]: 46
7895 12:41:18.316770
7896 12:41:18.317388 Set Vref, RX VrefLevel [Byte0]: 47
7897 12:41:18.320259 [Byte1]: 47
7898 12:41:18.324872
7899 12:41:18.325475 Set Vref, RX VrefLevel [Byte0]: 48
7900 12:41:18.327584 [Byte1]: 48
7901 12:41:18.332551
7902 12:41:18.333158 Set Vref, RX VrefLevel [Byte0]: 49
7903 12:41:18.335447 [Byte1]: 49
7904 12:41:18.339667
7905 12:41:18.340241 Set Vref, RX VrefLevel [Byte0]: 50
7906 12:41:18.342579 [Byte1]: 50
7907 12:41:18.347698
7908 12:41:18.348276 Set Vref, RX VrefLevel [Byte0]: 51
7909 12:41:18.350543 [Byte1]: 51
7910 12:41:18.354894
7911 12:41:18.355477 Set Vref, RX VrefLevel [Byte0]: 52
7912 12:41:18.358321 [Byte1]: 52
7913 12:41:18.362395
7914 12:41:18.362961 Set Vref, RX VrefLevel [Byte0]: 53
7915 12:41:18.365651 [Byte1]: 53
7916 12:41:18.369931
7917 12:41:18.370497 Set Vref, RX VrefLevel [Byte0]: 54
7918 12:41:18.373099 [Byte1]: 54
7919 12:41:18.377849
7920 12:41:18.378415 Set Vref, RX VrefLevel [Byte0]: 55
7921 12:41:18.380682 [Byte1]: 55
7922 12:41:18.385728
7923 12:41:18.386302 Set Vref, RX VrefLevel [Byte0]: 56
7924 12:41:18.388364 [Byte1]: 56
7925 12:41:18.392441
7926 12:41:18.392915 Set Vref, RX VrefLevel [Byte0]: 57
7927 12:41:18.395957 [Byte1]: 57
7928 12:41:18.400025
7929 12:41:18.400495 Set Vref, RX VrefLevel [Byte0]: 58
7930 12:41:18.403582 [Byte1]: 58
7931 12:41:18.407671
7932 12:41:18.408148 Set Vref, RX VrefLevel [Byte0]: 59
7933 12:41:18.410570 [Byte1]: 59
7934 12:41:18.415117
7935 12:41:18.415587 Set Vref, RX VrefLevel [Byte0]: 60
7936 12:41:18.418675 [Byte1]: 60
7937 12:41:18.422932
7938 12:41:18.423499 Set Vref, RX VrefLevel [Byte0]: 61
7939 12:41:18.426524 [Byte1]: 61
7940 12:41:18.430569
7941 12:41:18.431133 Set Vref, RX VrefLevel [Byte0]: 62
7942 12:41:18.433411 [Byte1]: 62
7943 12:41:18.437865
7944 12:41:18.438440 Set Vref, RX VrefLevel [Byte0]: 63
7945 12:41:18.441189 [Byte1]: 63
7946 12:41:18.445774
7947 12:41:18.446335 Set Vref, RX VrefLevel [Byte0]: 64
7948 12:41:18.449303 [Byte1]: 64
7949 12:41:18.453193
7950 12:41:18.453759 Set Vref, RX VrefLevel [Byte0]: 65
7951 12:41:18.456460 [Byte1]: 65
7952 12:41:18.460744
7953 12:41:18.461333 Set Vref, RX VrefLevel [Byte0]: 66
7954 12:41:18.463884 [Byte1]: 66
7955 12:41:18.468025
7956 12:41:18.468496 Set Vref, RX VrefLevel [Byte0]: 67
7957 12:41:18.471448 [Byte1]: 67
7958 12:41:18.475632
7959 12:41:18.476100 Set Vref, RX VrefLevel [Byte0]: 68
7960 12:41:18.479030 [Byte1]: 68
7961 12:41:18.483450
7962 12:41:18.483915 Set Vref, RX VrefLevel [Byte0]: 69
7963 12:41:18.486685 [Byte1]: 69
7964 12:41:18.490870
7965 12:41:18.491336 Set Vref, RX VrefLevel [Byte0]: 70
7966 12:41:18.494598 [Byte1]: 70
7967 12:41:18.498293
7968 12:41:18.498759 Set Vref, RX VrefLevel [Byte0]: 71
7969 12:41:18.501896 [Byte1]: 71
7970 12:41:18.506036
7971 12:41:18.506502 Set Vref, RX VrefLevel [Byte0]: 72
7972 12:41:18.509309 [Byte1]: 72
7973 12:41:18.513764
7974 12:41:18.514227 Set Vref, RX VrefLevel [Byte0]: 73
7975 12:41:18.516963 [Byte1]: 73
7976 12:41:18.521627
7977 12:41:18.522196 Set Vref, RX VrefLevel [Byte0]: 74
7978 12:41:18.524425 [Byte1]: 74
7979 12:41:18.528615
7980 12:41:18.529210 Set Vref, RX VrefLevel [Byte0]: 75
7981 12:41:18.532077 [Byte1]: 75
7982 12:41:18.536604
7983 12:41:18.537202 Set Vref, RX VrefLevel [Byte0]: 76
7984 12:41:18.539959 [Byte1]: 76
7985 12:41:18.543803
7986 12:41:18.544268 Set Vref, RX VrefLevel [Byte0]: 77
7987 12:41:18.547444 [Byte1]: 77
7988 12:41:18.551667
7989 12:41:18.552231 Set Vref, RX VrefLevel [Byte0]: 78
7990 12:41:18.554949 [Byte1]: 78
7991 12:41:18.559416
7992 12:41:18.559978 Set Vref, RX VrefLevel [Byte0]: 79
7993 12:41:18.562444 [Byte1]: 79
7994 12:41:18.566800
7995 12:41:18.567361 Final RX Vref Byte 0 = 59 to rank0
7996 12:41:18.569883 Final RX Vref Byte 1 = 62 to rank0
7997 12:41:18.573190 Final RX Vref Byte 0 = 59 to rank1
7998 12:41:18.576808 Final RX Vref Byte 1 = 62 to rank1==
7999 12:41:18.580140 Dram Type= 6, Freq= 0, CH_0, rank 0
8000 12:41:18.586740 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8001 12:41:18.587314 ==
8002 12:41:18.587686 DQS Delay:
8003 12:41:18.589714 DQS0 = 0, DQS1 = 0
8004 12:41:18.590364 DQM Delay:
8005 12:41:18.590773 DQM0 = 135, DQM1 = 125
8006 12:41:18.593338 DQ Delay:
8007 12:41:18.596362 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =132
8008 12:41:18.599668 DQ4 =138, DQ5 =124, DQ6 =142, DQ7 =144
8009 12:41:18.603168 DQ8 =116, DQ9 =114, DQ10 =126, DQ11 =118
8010 12:41:18.606464 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =134
8011 12:41:18.607029
8012 12:41:18.607399
8013 12:41:18.607746
8014 12:41:18.609330 [DramC_TX_OE_Calibration] TA2
8015 12:41:18.612664 Original DQ_B0 (3 6) =30, OEN = 27
8016 12:41:18.616377 Original DQ_B1 (3 6) =30, OEN = 27
8017 12:41:18.619822 24, 0x0, End_B0=24 End_B1=24
8018 12:41:18.620398 25, 0x0, End_B0=25 End_B1=25
8019 12:41:18.623044 26, 0x0, End_B0=26 End_B1=26
8020 12:41:18.626141 27, 0x0, End_B0=27 End_B1=27
8021 12:41:18.629313 28, 0x0, End_B0=28 End_B1=28
8022 12:41:18.632443 29, 0x0, End_B0=29 End_B1=29
8023 12:41:18.632917 30, 0x0, End_B0=30 End_B1=30
8024 12:41:18.636171 31, 0x4141, End_B0=30 End_B1=30
8025 12:41:18.638996 Byte0 end_step=30 best_step=27
8026 12:41:18.642531 Byte1 end_step=30 best_step=27
8027 12:41:18.645960 Byte0 TX OE(2T, 0.5T) = (3, 3)
8028 12:41:18.649480 Byte1 TX OE(2T, 0.5T) = (3, 3)
8029 12:41:18.650061
8030 12:41:18.650458
8031 12:41:18.656185 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
8032 12:41:18.659472 CH0 RK0: MR19=303, MR18=1F1D
8033 12:41:18.665585 CH0_RK0: MR19=0x303, MR18=0x1F1D, DQSOSC=394, MR23=63, INC=23, DEC=15
8034 12:41:18.666165
8035 12:41:18.668870 ----->DramcWriteLeveling(PI) begin...
8036 12:41:18.669592 ==
8037 12:41:18.672060 Dram Type= 6, Freq= 0, CH_0, rank 1
8038 12:41:18.675220 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8039 12:41:18.675748 ==
8040 12:41:18.678841 Write leveling (Byte 0): 36 => 36
8041 12:41:18.681629 Write leveling (Byte 1): 30 => 30
8042 12:41:18.685508 DramcWriteLeveling(PI) end<-----
8043 12:41:18.686090
8044 12:41:18.686468 ==
8045 12:41:18.688564 Dram Type= 6, Freq= 0, CH_0, rank 1
8046 12:41:18.695555 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8047 12:41:18.696139 ==
8048 12:41:18.696522 [Gating] SW mode calibration
8049 12:41:18.705256 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8050 12:41:18.708383 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8051 12:41:18.711789 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8052 12:41:18.718520 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8053 12:41:18.721324 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8054 12:41:18.724745 1 4 12 | B1->B0 | 2525 3131 | 1 1 | (0 0) (0 0)
8055 12:41:18.731446 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8056 12:41:18.734439 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8057 12:41:18.737812 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8058 12:41:18.744498 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8059 12:41:18.747842 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8060 12:41:18.754839 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8061 12:41:18.757660 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8062 12:41:18.760793 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 0)
8063 12:41:18.764653 1 5 16 | B1->B0 | 2828 2323 | 0 0 | (0 1) (0 0)
8064 12:41:18.770774 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8065 12:41:18.774305 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8066 12:41:18.777750 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8067 12:41:18.784521 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8068 12:41:18.787643 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8069 12:41:18.790524 1 6 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8070 12:41:18.797853 1 6 12 | B1->B0 | 2c2c 4040 | 0 0 | (0 0) (1 1)
8071 12:41:18.800888 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8072 12:41:18.804155 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8073 12:41:18.810752 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8074 12:41:18.814222 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8075 12:41:18.817264 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8076 12:41:18.824097 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8077 12:41:18.827038 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8078 12:41:18.830464 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8079 12:41:18.837136 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8080 12:41:18.840439 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 12:41:18.843673 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 12:41:18.850132 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 12:41:18.853906 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 12:41:18.857716 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 12:41:18.863347 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 12:41:18.867183 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 12:41:18.870108 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 12:41:18.876638 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 12:41:18.879842 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 12:41:18.883422 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 12:41:18.889966 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 12:41:18.893073 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 12:41:18.896928 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 12:41:18.903452 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8095 12:41:18.906662 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8096 12:41:18.909792 Total UI for P1: 0, mck2ui 16
8097 12:41:18.913024 best dqsien dly found for B0: ( 1, 9, 12)
8098 12:41:18.916344 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8099 12:41:18.923032 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8100 12:41:18.923607 Total UI for P1: 0, mck2ui 16
8101 12:41:18.929546 best dqsien dly found for B1: ( 1, 9, 16)
8102 12:41:18.932932 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8103 12:41:18.936434 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8104 12:41:18.937088
8105 12:41:18.939691 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8106 12:41:18.942687 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8107 12:41:18.946398 [Gating] SW calibration Done
8108 12:41:18.946964 ==
8109 12:41:18.949324 Dram Type= 6, Freq= 0, CH_0, rank 1
8110 12:41:18.952949 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8111 12:41:18.953559 ==
8112 12:41:18.956232 RX Vref Scan: 0
8113 12:41:18.956697
8114 12:41:18.957095 RX Vref 0 -> 0, step: 1
8115 12:41:18.957444
8116 12:41:18.959796 RX Delay 0 -> 252, step: 8
8117 12:41:18.962621 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8118 12:41:18.969680 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8119 12:41:18.972556 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8120 12:41:18.976009 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8121 12:41:18.979550 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8122 12:41:18.982319 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8123 12:41:18.989610 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8124 12:41:18.992307 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8125 12:41:18.995745 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8126 12:41:18.999405 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8127 12:41:19.005863 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8128 12:41:19.009089 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8129 12:41:19.012542 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8130 12:41:19.015845 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8131 12:41:19.019411 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8132 12:41:19.026006 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8133 12:41:19.026571 ==
8134 12:41:19.029248 Dram Type= 6, Freq= 0, CH_0, rank 1
8135 12:41:19.032679 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8136 12:41:19.033291 ==
8137 12:41:19.033711 DQS Delay:
8138 12:41:19.035600 DQS0 = 0, DQS1 = 0
8139 12:41:19.036167 DQM Delay:
8140 12:41:19.039115 DQM0 = 136, DQM1 = 125
8141 12:41:19.039635 DQ Delay:
8142 12:41:19.042112 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8143 12:41:19.045801 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8144 12:41:19.048772 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8145 12:41:19.052451 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8146 12:41:19.053057
8147 12:41:19.053439
8148 12:41:19.055537 ==
8149 12:41:19.058630 Dram Type= 6, Freq= 0, CH_0, rank 1
8150 12:41:19.061747 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8151 12:41:19.062221 ==
8152 12:41:19.062592
8153 12:41:19.062931
8154 12:41:19.064940 TX Vref Scan disable
8155 12:41:19.065444 == TX Byte 0 ==
8156 12:41:19.072041 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8157 12:41:19.074833 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8158 12:41:19.075264 == TX Byte 1 ==
8159 12:41:19.081862 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8160 12:41:19.085026 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8161 12:41:19.085549 ==
8162 12:41:19.088316 Dram Type= 6, Freq= 0, CH_0, rank 1
8163 12:41:19.091965 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8164 12:41:19.092498 ==
8165 12:41:19.107398
8166 12:41:19.110009 TX Vref early break, caculate TX vref
8167 12:41:19.113411 TX Vref=16, minBit 8, minWin=22, winSum=384
8168 12:41:19.116846 TX Vref=18, minBit 0, minWin=24, winSum=400
8169 12:41:19.120168 TX Vref=20, minBit 0, minWin=24, winSum=406
8170 12:41:19.123623 TX Vref=22, minBit 1, minWin=25, winSum=413
8171 12:41:19.126832 TX Vref=24, minBit 0, minWin=25, winSum=422
8172 12:41:19.133634 TX Vref=26, minBit 0, minWin=26, winSum=428
8173 12:41:19.136563 TX Vref=28, minBit 4, minWin=25, winSum=426
8174 12:41:19.140296 TX Vref=30, minBit 4, minWin=25, winSum=425
8175 12:41:19.143291 TX Vref=32, minBit 0, minWin=25, winSum=413
8176 12:41:19.146444 TX Vref=34, minBit 0, minWin=24, winSum=409
8177 12:41:19.150194 TX Vref=36, minBit 2, minWin=23, winSum=399
8178 12:41:19.156384 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 26
8179 12:41:19.156951
8180 12:41:19.160011 Final TX Range 0 Vref 26
8181 12:41:19.160578
8182 12:41:19.160949 ==
8183 12:41:19.162855 Dram Type= 6, Freq= 0, CH_0, rank 1
8184 12:41:19.166456 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8185 12:41:19.167031 ==
8186 12:41:19.169582
8187 12:41:19.170048
8188 12:41:19.170413 TX Vref Scan disable
8189 12:41:19.176128 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8190 12:41:19.176594 == TX Byte 0 ==
8191 12:41:19.180175 u2DelayCellOfst[0]=10 cells (3 PI)
8192 12:41:19.182851 u2DelayCellOfst[1]=16 cells (5 PI)
8193 12:41:19.186357 u2DelayCellOfst[2]=10 cells (3 PI)
8194 12:41:19.189440 u2DelayCellOfst[3]=10 cells (3 PI)
8195 12:41:19.192972 u2DelayCellOfst[4]=6 cells (2 PI)
8196 12:41:19.196027 u2DelayCellOfst[5]=0 cells (0 PI)
8197 12:41:19.199571 u2DelayCellOfst[6]=16 cells (5 PI)
8198 12:41:19.202941 u2DelayCellOfst[7]=16 cells (5 PI)
8199 12:41:19.205887 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8200 12:41:19.209246 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8201 12:41:19.212522 == TX Byte 1 ==
8202 12:41:19.215937 u2DelayCellOfst[8]=0 cells (0 PI)
8203 12:41:19.219481 u2DelayCellOfst[9]=3 cells (1 PI)
8204 12:41:19.222551 u2DelayCellOfst[10]=10 cells (3 PI)
8205 12:41:19.225884 u2DelayCellOfst[11]=3 cells (1 PI)
8206 12:41:19.229134 u2DelayCellOfst[12]=13 cells (4 PI)
8207 12:41:19.232590 u2DelayCellOfst[13]=13 cells (4 PI)
8208 12:41:19.235939 u2DelayCellOfst[14]=16 cells (5 PI)
8209 12:41:19.236460 u2DelayCellOfst[15]=13 cells (4 PI)
8210 12:41:19.242756 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8211 12:41:19.245707 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8212 12:41:19.249593 DramC Write-DBI on
8213 12:41:19.250115 ==
8214 12:41:19.252136 Dram Type= 6, Freq= 0, CH_0, rank 1
8215 12:41:19.255646 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8216 12:41:19.256177 ==
8217 12:41:19.256519
8218 12:41:19.256830
8219 12:41:19.258831 TX Vref Scan disable
8220 12:41:19.259253 == TX Byte 0 ==
8221 12:41:19.265805 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8222 12:41:19.266338 == TX Byte 1 ==
8223 12:41:19.268731 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8224 12:41:19.271991 DramC Write-DBI off
8225 12:41:19.272410
8226 12:41:19.272741 [DATLAT]
8227 12:41:19.275336 Freq=1600, CH0 RK1
8228 12:41:19.275762
8229 12:41:19.276096 DATLAT Default: 0xf
8230 12:41:19.278677 0, 0xFFFF, sum = 0
8231 12:41:19.279209 1, 0xFFFF, sum = 0
8232 12:41:19.281719 2, 0xFFFF, sum = 0
8233 12:41:19.285431 3, 0xFFFF, sum = 0
8234 12:41:19.285858 4, 0xFFFF, sum = 0
8235 12:41:19.289112 5, 0xFFFF, sum = 0
8236 12:41:19.289642 6, 0xFFFF, sum = 0
8237 12:41:19.291957 7, 0xFFFF, sum = 0
8238 12:41:19.292489 8, 0xFFFF, sum = 0
8239 12:41:19.295037 9, 0xFFFF, sum = 0
8240 12:41:19.295471 10, 0xFFFF, sum = 0
8241 12:41:19.298545 11, 0xFFFF, sum = 0
8242 12:41:19.299077 12, 0xFFFF, sum = 0
8243 12:41:19.302499 13, 0xFFFF, sum = 0
8244 12:41:19.303033 14, 0x0, sum = 1
8245 12:41:19.304898 15, 0x0, sum = 2
8246 12:41:19.305358 16, 0x0, sum = 3
8247 12:41:19.308670 17, 0x0, sum = 4
8248 12:41:19.309245 best_step = 15
8249 12:41:19.309595
8250 12:41:19.309918 ==
8251 12:41:19.311871 Dram Type= 6, Freq= 0, CH_0, rank 1
8252 12:41:19.315786 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8253 12:41:19.318381 ==
8254 12:41:19.318807 RX Vref Scan: 0
8255 12:41:19.319143
8256 12:41:19.321833 RX Vref 0 -> 0, step: 1
8257 12:41:19.322357
8258 12:41:19.325207 RX Delay 11 -> 252, step: 4
8259 12:41:19.328287 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8260 12:41:19.331481 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8261 12:41:19.335071 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8262 12:41:19.341551 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8263 12:41:19.344958 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8264 12:41:19.348244 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8265 12:41:19.351729 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8266 12:41:19.355063 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8267 12:41:19.361099 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8268 12:41:19.364384 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8269 12:41:19.368178 iDelay=191, Bit 10, Center 126 (79 ~ 174) 96
8270 12:41:19.371499 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8271 12:41:19.374470 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8272 12:41:19.381548 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8273 12:41:19.384804 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8274 12:41:19.387971 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8275 12:41:19.388547 ==
8276 12:41:19.391243 Dram Type= 6, Freq= 0, CH_0, rank 1
8277 12:41:19.394349 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8278 12:41:19.394868 ==
8279 12:41:19.397871 DQS Delay:
8280 12:41:19.398339 DQS0 = 0, DQS1 = 0
8281 12:41:19.401098 DQM Delay:
8282 12:41:19.401559 DQM0 = 133, DQM1 = 123
8283 12:41:19.404143 DQ Delay:
8284 12:41:19.407881 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =130
8285 12:41:19.411381 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =138
8286 12:41:19.414680 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =120
8287 12:41:19.417442 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =130
8288 12:41:19.417864
8289 12:41:19.418196
8290 12:41:19.418502
8291 12:41:19.420845 [DramC_TX_OE_Calibration] TA2
8292 12:41:19.424720 Original DQ_B0 (3 6) =30, OEN = 27
8293 12:41:19.427738 Original DQ_B1 (3 6) =30, OEN = 27
8294 12:41:19.428265 24, 0x0, End_B0=24 End_B1=24
8295 12:41:19.430972 25, 0x0, End_B0=25 End_B1=25
8296 12:41:19.434461 26, 0x0, End_B0=26 End_B1=26
8297 12:41:19.437531 27, 0x0, End_B0=27 End_B1=27
8298 12:41:19.440631 28, 0x0, End_B0=28 End_B1=28
8299 12:41:19.441087 29, 0x0, End_B0=29 End_B1=29
8300 12:41:19.444194 30, 0x0, End_B0=30 End_B1=30
8301 12:41:19.447486 31, 0x4141, End_B0=30 End_B1=30
8302 12:41:19.450440 Byte0 end_step=30 best_step=27
8303 12:41:19.453880 Byte1 end_step=30 best_step=27
8304 12:41:19.457668 Byte0 TX OE(2T, 0.5T) = (3, 3)
8305 12:41:19.458194 Byte1 TX OE(2T, 0.5T) = (3, 3)
8306 12:41:19.458533
8307 12:41:19.460567
8308 12:41:19.467319 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f0b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 394 ps
8309 12:41:19.470646 CH0 RK1: MR19=303, MR18=1F0B
8310 12:41:19.476952 CH0_RK1: MR19=0x303, MR18=0x1F0B, DQSOSC=394, MR23=63, INC=23, DEC=15
8311 12:41:19.480292 [RxdqsGatingPostProcess] freq 1600
8312 12:41:19.483526 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8313 12:41:19.487328 best DQS0 dly(2T, 0.5T) = (1, 1)
8314 12:41:19.490134 best DQS1 dly(2T, 0.5T) = (1, 1)
8315 12:41:19.493453 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8316 12:41:19.496574 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8317 12:41:19.500040 best DQS0 dly(2T, 0.5T) = (1, 1)
8318 12:41:19.503701 best DQS1 dly(2T, 0.5T) = (1, 1)
8319 12:41:19.507105 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8320 12:41:19.510008 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8321 12:41:19.513714 Pre-setting of DQS Precalculation
8322 12:41:19.516797 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8323 12:41:19.517356 ==
8324 12:41:19.520035 Dram Type= 6, Freq= 0, CH_1, rank 0
8325 12:41:19.523516 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8326 12:41:19.524044 ==
8327 12:41:19.530338 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8328 12:41:19.533476 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8329 12:41:19.540127 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8330 12:41:19.543318 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8331 12:41:19.553522 [CA 0] Center 40 (11~70) winsize 60
8332 12:41:19.556519 [CA 1] Center 41 (11~71) winsize 61
8333 12:41:19.560050 [CA 2] Center 37 (8~67) winsize 60
8334 12:41:19.563270 [CA 3] Center 36 (7~66) winsize 60
8335 12:41:19.566785 [CA 4] Center 36 (7~66) winsize 60
8336 12:41:19.569893 [CA 5] Center 36 (6~66) winsize 61
8337 12:41:19.570460
8338 12:41:19.572922 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8339 12:41:19.573493
8340 12:41:19.576791 [CATrainingPosCal] consider 1 rank data
8341 12:41:19.579964 u2DelayCellTimex100 = 290/100 ps
8342 12:41:19.583116 CA0 delay=40 (11~70),Diff = 4 PI (13 cell)
8343 12:41:19.589509 CA1 delay=41 (11~71),Diff = 5 PI (16 cell)
8344 12:41:19.593388 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8345 12:41:19.596286 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8346 12:41:19.600035 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8347 12:41:19.602708 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8348 12:41:19.603279
8349 12:41:19.605841 CA PerBit enable=1, Macro0, CA PI delay=36
8350 12:41:19.606318
8351 12:41:19.609218 [CBTSetCACLKResult] CA Dly = 36
8352 12:41:19.612596 CS Dly: 8 (0~39)
8353 12:41:19.615857 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8354 12:41:19.619214 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8355 12:41:19.619791 ==
8356 12:41:19.622348 Dram Type= 6, Freq= 0, CH_1, rank 1
8357 12:41:19.629171 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8358 12:41:19.629743 ==
8359 12:41:19.633121 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8360 12:41:19.639028 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8361 12:41:19.642286 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8362 12:41:19.648712 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8363 12:41:19.656595 [CA 0] Center 42 (12~72) winsize 61
8364 12:41:19.659436 [CA 1] Center 41 (11~71) winsize 61
8365 12:41:19.663206 [CA 2] Center 37 (8~67) winsize 60
8366 12:41:19.666561 [CA 3] Center 37 (8~66) winsize 59
8367 12:41:19.669847 [CA 4] Center 37 (8~67) winsize 60
8368 12:41:19.673203 [CA 5] Center 36 (7~66) winsize 60
8369 12:41:19.673759
8370 12:41:19.676041 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8371 12:41:19.676530
8372 12:41:19.679470 [CATrainingPosCal] consider 2 rank data
8373 12:41:19.682898 u2DelayCellTimex100 = 290/100 ps
8374 12:41:19.686119 CA0 delay=41 (12~70),Diff = 5 PI (16 cell)
8375 12:41:19.692581 CA1 delay=41 (11~71),Diff = 5 PI (16 cell)
8376 12:41:19.696047 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8377 12:41:19.699454 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8378 12:41:19.702770 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8379 12:41:19.705842 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8380 12:41:19.706308
8381 12:41:19.709015 CA PerBit enable=1, Macro0, CA PI delay=36
8382 12:41:19.709464
8383 12:41:19.712584 [CBTSetCACLKResult] CA Dly = 36
8384 12:41:19.715849 CS Dly: 9 (0~42)
8385 12:41:19.719451 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8386 12:41:19.722772 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8387 12:41:19.723279
8388 12:41:19.725598 ----->DramcWriteLeveling(PI) begin...
8389 12:41:19.726021 ==
8390 12:41:19.729704 Dram Type= 6, Freq= 0, CH_1, rank 0
8391 12:41:19.736181 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8392 12:41:19.736740 ==
8393 12:41:19.738925 Write leveling (Byte 0): 25 => 25
8394 12:41:19.739479 Write leveling (Byte 1): 28 => 28
8395 12:41:19.742781 DramcWriteLeveling(PI) end<-----
8396 12:41:19.743332
8397 12:41:19.745593 ==
8398 12:41:19.746054 Dram Type= 6, Freq= 0, CH_1, rank 0
8399 12:41:19.752564 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8400 12:41:19.753172 ==
8401 12:41:19.755340 [Gating] SW mode calibration
8402 12:41:19.762506 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8403 12:41:19.765883 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8404 12:41:19.772136 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 12:41:19.775630 1 4 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8406 12:41:19.778546 1 4 8 | B1->B0 | 2d2d 3232 | 0 1 | (0 0) (1 1)
8407 12:41:19.785747 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8408 12:41:19.788659 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8409 12:41:19.792143 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8410 12:41:19.798614 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8411 12:41:19.801845 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8412 12:41:19.805096 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8413 12:41:19.811947 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8414 12:41:19.815092 1 5 8 | B1->B0 | 3030 2d2d | 0 0 | (1 0) (1 0)
8415 12:41:19.818315 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8416 12:41:19.824767 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8417 12:41:19.828230 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8418 12:41:19.831417 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8419 12:41:19.838374 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8420 12:41:19.841331 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8421 12:41:19.845162 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8422 12:41:19.851256 1 6 8 | B1->B0 | 3a3a 4444 | 0 0 | (1 1) (0 0)
8423 12:41:19.854289 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8424 12:41:19.857792 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8425 12:41:19.864876 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8426 12:41:19.868255 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8427 12:41:19.871360 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8428 12:41:19.877885 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8429 12:41:19.881649 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8430 12:41:19.884638 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8431 12:41:19.890915 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8432 12:41:19.894129 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 12:41:19.897494 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 12:41:19.904058 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 12:41:19.907450 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 12:41:19.910727 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 12:41:19.917244 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 12:41:19.920584 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 12:41:19.924024 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 12:41:19.930730 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 12:41:19.933797 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 12:41:19.937803 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 12:41:19.943906 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 12:41:19.947211 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 12:41:19.950338 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8446 12:41:19.956969 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8447 12:41:19.960032 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8448 12:41:19.963370 Total UI for P1: 0, mck2ui 16
8449 12:41:19.966456 best dqsien dly found for B0: ( 1, 9, 6)
8450 12:41:19.969911 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8451 12:41:19.973705 Total UI for P1: 0, mck2ui 16
8452 12:41:19.976763 best dqsien dly found for B1: ( 1, 9, 10)
8453 12:41:19.980049 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8454 12:41:19.984187 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8455 12:41:19.984784
8456 12:41:19.989776 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8457 12:41:19.993676 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8458 12:41:19.994245 [Gating] SW calibration Done
8459 12:41:19.996860 ==
8460 12:41:19.997493 Dram Type= 6, Freq= 0, CH_1, rank 0
8461 12:41:20.003505 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8462 12:41:20.004074 ==
8463 12:41:20.004449 RX Vref Scan: 0
8464 12:41:20.004793
8465 12:41:20.006583 RX Vref 0 -> 0, step: 1
8466 12:41:20.007150
8467 12:41:20.010208 RX Delay 0 -> 252, step: 8
8468 12:41:20.013062 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8469 12:41:20.016403 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8470 12:41:20.019733 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8471 12:41:20.026420 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8472 12:41:20.029836 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8473 12:41:20.032759 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8474 12:41:20.036429 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8475 12:41:20.039508 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8476 12:41:20.046308 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8477 12:41:20.049583 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8478 12:41:20.052833 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8479 12:41:20.055831 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8480 12:41:20.059072 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8481 12:41:20.065877 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8482 12:41:20.069394 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8483 12:41:20.072724 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8484 12:41:20.073328 ==
8485 12:41:20.075857 Dram Type= 6, Freq= 0, CH_1, rank 0
8486 12:41:20.079026 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8487 12:41:20.082522 ==
8488 12:41:20.083091 DQS Delay:
8489 12:41:20.083465 DQS0 = 0, DQS1 = 0
8490 12:41:20.086034 DQM Delay:
8491 12:41:20.086596 DQM0 = 138, DQM1 = 130
8492 12:41:20.088757 DQ Delay:
8493 12:41:20.092375 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =139
8494 12:41:20.095729 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8495 12:41:20.098809 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8496 12:41:20.102188 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =139
8497 12:41:20.102657
8498 12:41:20.103024
8499 12:41:20.103366 ==
8500 12:41:20.105499 Dram Type= 6, Freq= 0, CH_1, rank 0
8501 12:41:20.108747 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8502 12:41:20.109366 ==
8503 12:41:20.109804
8504 12:41:20.111965
8505 12:41:20.112461 TX Vref Scan disable
8506 12:41:20.115488 == TX Byte 0 ==
8507 12:41:20.119354 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8508 12:41:20.121684 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8509 12:41:20.125196 == TX Byte 1 ==
8510 12:41:20.128726 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8511 12:41:20.131833 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8512 12:41:20.132305 ==
8513 12:41:20.135395 Dram Type= 6, Freq= 0, CH_1, rank 0
8514 12:41:20.141877 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8515 12:41:20.142349 ==
8516 12:41:20.154686
8517 12:41:20.157583 TX Vref early break, caculate TX vref
8518 12:41:20.160958 TX Vref=16, minBit 10, minWin=21, winSum=365
8519 12:41:20.164458 TX Vref=18, minBit 10, minWin=22, winSum=378
8520 12:41:20.167288 TX Vref=20, minBit 15, minWin=22, winSum=391
8521 12:41:20.170956 TX Vref=22, minBit 10, minWin=23, winSum=398
8522 12:41:20.177607 TX Vref=24, minBit 10, minWin=24, winSum=405
8523 12:41:20.180653 TX Vref=26, minBit 10, minWin=24, winSum=414
8524 12:41:20.183956 TX Vref=28, minBit 10, minWin=24, winSum=416
8525 12:41:20.187392 TX Vref=30, minBit 9, minWin=24, winSum=414
8526 12:41:20.190718 TX Vref=32, minBit 8, minWin=24, winSum=408
8527 12:41:20.197121 TX Vref=34, minBit 11, minWin=23, winSum=396
8528 12:41:20.200498 TX Vref=36, minBit 8, minWin=23, winSum=388
8529 12:41:20.207163 [TxChooseVref] Worse bit 10, Min win 24, Win sum 416, Final Vref 28
8530 12:41:20.207732
8531 12:41:20.208100 Final TX Range 0 Vref 28
8532 12:41:20.208445
8533 12:41:20.208771 ==
8534 12:41:20.210519 Dram Type= 6, Freq= 0, CH_1, rank 0
8535 12:41:20.217051 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8536 12:41:20.217627 ==
8537 12:41:20.218049
8538 12:41:20.218397
8539 12:41:20.218724 TX Vref Scan disable
8540 12:41:20.224287 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8541 12:41:20.224850 == TX Byte 0 ==
8542 12:41:20.227838 u2DelayCellOfst[0]=13 cells (4 PI)
8543 12:41:20.230995 u2DelayCellOfst[1]=10 cells (3 PI)
8544 12:41:20.234449 u2DelayCellOfst[2]=0 cells (0 PI)
8545 12:41:20.237322 u2DelayCellOfst[3]=6 cells (2 PI)
8546 12:41:20.240459 u2DelayCellOfst[4]=6 cells (2 PI)
8547 12:41:20.244008 u2DelayCellOfst[5]=16 cells (5 PI)
8548 12:41:20.247360 u2DelayCellOfst[6]=16 cells (5 PI)
8549 12:41:20.251079 u2DelayCellOfst[7]=3 cells (1 PI)
8550 12:41:20.253950 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8551 12:41:20.257612 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8552 12:41:20.260468 == TX Byte 1 ==
8553 12:41:20.264094 u2DelayCellOfst[8]=0 cells (0 PI)
8554 12:41:20.267334 u2DelayCellOfst[9]=3 cells (1 PI)
8555 12:41:20.270622 u2DelayCellOfst[10]=13 cells (4 PI)
8556 12:41:20.273334 u2DelayCellOfst[11]=3 cells (1 PI)
8557 12:41:20.276591 u2DelayCellOfst[12]=16 cells (5 PI)
8558 12:41:20.280236 u2DelayCellOfst[13]=20 cells (6 PI)
8559 12:41:20.283546 u2DelayCellOfst[14]=20 cells (6 PI)
8560 12:41:20.284117 u2DelayCellOfst[15]=16 cells (5 PI)
8561 12:41:20.290309 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8562 12:41:20.293709 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8563 12:41:20.297141 DramC Write-DBI on
8564 12:41:20.297702 ==
8565 12:41:20.299871 Dram Type= 6, Freq= 0, CH_1, rank 0
8566 12:41:20.303230 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8567 12:41:20.303801 ==
8568 12:41:20.304171
8569 12:41:20.304512
8570 12:41:20.306582 TX Vref Scan disable
8571 12:41:20.307153 == TX Byte 0 ==
8572 12:41:20.313198 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8573 12:41:20.313770 == TX Byte 1 ==
8574 12:41:20.316549 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8575 12:41:20.319696 DramC Write-DBI off
8576 12:41:20.320262
8577 12:41:20.320631 [DATLAT]
8578 12:41:20.323124 Freq=1600, CH1 RK0
8579 12:41:20.323712
8580 12:41:20.324102 DATLAT Default: 0xf
8581 12:41:20.326364 0, 0xFFFF, sum = 0
8582 12:41:20.329703 1, 0xFFFF, sum = 0
8583 12:41:20.330228 2, 0xFFFF, sum = 0
8584 12:41:20.332846 3, 0xFFFF, sum = 0
8585 12:41:20.333349 4, 0xFFFF, sum = 0
8586 12:41:20.336225 5, 0xFFFF, sum = 0
8587 12:41:20.336702 6, 0xFFFF, sum = 0
8588 12:41:20.339466 7, 0xFFFF, sum = 0
8589 12:41:20.340035 8, 0xFFFF, sum = 0
8590 12:41:20.342629 9, 0xFFFF, sum = 0
8591 12:41:20.343101 10, 0xFFFF, sum = 0
8592 12:41:20.345904 11, 0xFFFF, sum = 0
8593 12:41:20.346429 12, 0xFFFF, sum = 0
8594 12:41:20.349329 13, 0xFFFF, sum = 0
8595 12:41:20.349802 14, 0x0, sum = 1
8596 12:41:20.352721 15, 0x0, sum = 2
8597 12:41:20.353238 16, 0x0, sum = 3
8598 12:41:20.355792 17, 0x0, sum = 4
8599 12:41:20.356266 best_step = 15
8600 12:41:20.356631
8601 12:41:20.356970 ==
8602 12:41:20.359215 Dram Type= 6, Freq= 0, CH_1, rank 0
8603 12:41:20.366178 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8604 12:41:20.366715 ==
8605 12:41:20.367058 RX Vref Scan: 1
8606 12:41:20.367370
8607 12:41:20.369328 Set Vref Range= 24 -> 127
8608 12:41:20.369751
8609 12:41:20.372425 RX Vref 24 -> 127, step: 1
8610 12:41:20.372949
8611 12:41:20.375484 RX Delay 19 -> 252, step: 4
8612 12:41:20.375908
8613 12:41:20.378727 Set Vref, RX VrefLevel [Byte0]: 24
8614 12:41:20.382402 [Byte1]: 24
8615 12:41:20.382946
8616 12:41:20.385516 Set Vref, RX VrefLevel [Byte0]: 25
8617 12:41:20.389219 [Byte1]: 25
8618 12:41:20.389744
8619 12:41:20.392286 Set Vref, RX VrefLevel [Byte0]: 26
8620 12:41:20.395414 [Byte1]: 26
8621 12:41:20.395938
8622 12:41:20.398799 Set Vref, RX VrefLevel [Byte0]: 27
8623 12:41:20.402103 [Byte1]: 27
8624 12:41:20.406317
8625 12:41:20.406898 Set Vref, RX VrefLevel [Byte0]: 28
8626 12:41:20.409129 [Byte1]: 28
8627 12:41:20.413755
8628 12:41:20.414341 Set Vref, RX VrefLevel [Byte0]: 29
8629 12:41:20.416690 [Byte1]: 29
8630 12:41:20.421352
8631 12:41:20.421914 Set Vref, RX VrefLevel [Byte0]: 30
8632 12:41:20.424612 [Byte1]: 30
8633 12:41:20.428896
8634 12:41:20.429495 Set Vref, RX VrefLevel [Byte0]: 31
8635 12:41:20.432347 [Byte1]: 31
8636 12:41:20.436252
8637 12:41:20.436819 Set Vref, RX VrefLevel [Byte0]: 32
8638 12:41:20.439764 [Byte1]: 32
8639 12:41:20.444030
8640 12:41:20.444597 Set Vref, RX VrefLevel [Byte0]: 33
8641 12:41:20.447054 [Byte1]: 33
8642 12:41:20.451752
8643 12:41:20.452318 Set Vref, RX VrefLevel [Byte0]: 34
8644 12:41:20.454656 [Byte1]: 34
8645 12:41:20.459314
8646 12:41:20.459949 Set Vref, RX VrefLevel [Byte0]: 35
8647 12:41:20.462263 [Byte1]: 35
8648 12:41:20.466334
8649 12:41:20.466800 Set Vref, RX VrefLevel [Byte0]: 36
8650 12:41:20.470255 [Byte1]: 36
8651 12:41:20.474238
8652 12:41:20.474819 Set Vref, RX VrefLevel [Byte0]: 37
8653 12:41:20.478013 [Byte1]: 37
8654 12:41:20.481851
8655 12:41:20.482410 Set Vref, RX VrefLevel [Byte0]: 38
8656 12:41:20.485312 [Byte1]: 38
8657 12:41:20.489344
8658 12:41:20.489907 Set Vref, RX VrefLevel [Byte0]: 39
8659 12:41:20.492770 [Byte1]: 39
8660 12:41:20.497255
8661 12:41:20.497831 Set Vref, RX VrefLevel [Byte0]: 40
8662 12:41:20.500534 [Byte1]: 40
8663 12:41:20.504683
8664 12:41:20.505286 Set Vref, RX VrefLevel [Byte0]: 41
8665 12:41:20.507990 [Byte1]: 41
8666 12:41:20.512271
8667 12:41:20.512832 Set Vref, RX VrefLevel [Byte0]: 42
8668 12:41:20.515480 [Byte1]: 42
8669 12:41:20.520046
8670 12:41:20.520613 Set Vref, RX VrefLevel [Byte0]: 43
8671 12:41:20.523019 [Byte1]: 43
8672 12:41:20.527200
8673 12:41:20.527764 Set Vref, RX VrefLevel [Byte0]: 44
8674 12:41:20.530464 [Byte1]: 44
8675 12:41:20.534864
8676 12:41:20.538104 Set Vref, RX VrefLevel [Byte0]: 45
8677 12:41:20.541228 [Byte1]: 45
8678 12:41:20.541791
8679 12:41:20.544858 Set Vref, RX VrefLevel [Byte0]: 46
8680 12:41:20.547623 [Byte1]: 46
8681 12:41:20.548109
8682 12:41:20.551031 Set Vref, RX VrefLevel [Byte0]: 47
8683 12:41:20.554439 [Byte1]: 47
8684 12:41:20.555008
8685 12:41:20.557747 Set Vref, RX VrefLevel [Byte0]: 48
8686 12:41:20.561069 [Byte1]: 48
8687 12:41:20.565162
8688 12:41:20.565636 Set Vref, RX VrefLevel [Byte0]: 49
8689 12:41:20.568637 [Byte1]: 49
8690 12:41:20.572879
8691 12:41:20.573481 Set Vref, RX VrefLevel [Byte0]: 50
8692 12:41:20.576043 [Byte1]: 50
8693 12:41:20.580356
8694 12:41:20.580924 Set Vref, RX VrefLevel [Byte0]: 51
8695 12:41:20.583419 [Byte1]: 51
8696 12:41:20.587912
8697 12:41:20.588480 Set Vref, RX VrefLevel [Byte0]: 52
8698 12:41:20.591341 [Byte1]: 52
8699 12:41:20.595693
8700 12:41:20.596257 Set Vref, RX VrefLevel [Byte0]: 53
8701 12:41:20.598677 [Byte1]: 53
8702 12:41:20.603012
8703 12:41:20.603586 Set Vref, RX VrefLevel [Byte0]: 54
8704 12:41:20.606215 [Byte1]: 54
8705 12:41:20.610502
8706 12:41:20.610976 Set Vref, RX VrefLevel [Byte0]: 55
8707 12:41:20.613491 [Byte1]: 55
8708 12:41:20.618407
8709 12:41:20.619021 Set Vref, RX VrefLevel [Byte0]: 56
8710 12:41:20.621473 [Byte1]: 56
8711 12:41:20.625775
8712 12:41:20.626337 Set Vref, RX VrefLevel [Byte0]: 57
8713 12:41:20.629131 [Byte1]: 57
8714 12:41:20.633546
8715 12:41:20.634114 Set Vref, RX VrefLevel [Byte0]: 58
8716 12:41:20.636580 [Byte1]: 58
8717 12:41:20.640862
8718 12:41:20.641469 Set Vref, RX VrefLevel [Byte0]: 59
8719 12:41:20.644250 [Byte1]: 59
8720 12:41:20.648359
8721 12:41:20.648926 Set Vref, RX VrefLevel [Byte0]: 60
8722 12:41:20.652287 [Byte1]: 60
8723 12:41:20.656143
8724 12:41:20.656716 Set Vref, RX VrefLevel [Byte0]: 61
8725 12:41:20.659049 [Byte1]: 61
8726 12:41:20.663549
8727 12:41:20.664108 Set Vref, RX VrefLevel [Byte0]: 62
8728 12:41:20.666802 [Byte1]: 62
8729 12:41:20.671548
8730 12:41:20.672113 Set Vref, RX VrefLevel [Byte0]: 63
8731 12:41:20.674165 [Byte1]: 63
8732 12:41:20.678576
8733 12:41:20.679145 Set Vref, RX VrefLevel [Byte0]: 64
8734 12:41:20.682352 [Byte1]: 64
8735 12:41:20.686066
8736 12:41:20.686532 Set Vref, RX VrefLevel [Byte0]: 65
8737 12:41:20.689549 [Byte1]: 65
8738 12:41:20.693858
8739 12:41:20.694418 Set Vref, RX VrefLevel [Byte0]: 66
8740 12:41:20.697240 [Byte1]: 66
8741 12:41:20.701938
8742 12:41:20.702692 Set Vref, RX VrefLevel [Byte0]: 67
8743 12:41:20.704654 [Byte1]: 67
8744 12:41:20.708957
8745 12:41:20.709574 Set Vref, RX VrefLevel [Byte0]: 68
8746 12:41:20.712438 [Byte1]: 68
8747 12:41:20.716527
8748 12:41:20.717129 Set Vref, RX VrefLevel [Byte0]: 69
8749 12:41:20.720181 [Byte1]: 69
8750 12:41:20.724444
8751 12:41:20.725054 Set Vref, RX VrefLevel [Byte0]: 70
8752 12:41:20.727374 [Byte1]: 70
8753 12:41:20.731803
8754 12:41:20.732379 Set Vref, RX VrefLevel [Byte0]: 71
8755 12:41:20.734963 [Byte1]: 71
8756 12:41:20.738891
8757 12:41:20.739355 Set Vref, RX VrefLevel [Byte0]: 72
8758 12:41:20.742418 [Byte1]: 72
8759 12:41:20.747359
8760 12:41:20.747929 Set Vref, RX VrefLevel [Byte0]: 73
8761 12:41:20.750075 [Byte1]: 73
8762 12:41:20.754619
8763 12:41:20.755188 Set Vref, RX VrefLevel [Byte0]: 74
8764 12:41:20.757598 [Byte1]: 74
8765 12:41:20.761626
8766 12:41:20.762093 Final RX Vref Byte 0 = 54 to rank0
8767 12:41:20.765148 Final RX Vref Byte 1 = 63 to rank0
8768 12:41:20.768937 Final RX Vref Byte 0 = 54 to rank1
8769 12:41:20.772117 Final RX Vref Byte 1 = 63 to rank1==
8770 12:41:20.775364 Dram Type= 6, Freq= 0, CH_1, rank 0
8771 12:41:20.781846 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8772 12:41:20.782427 ==
8773 12:41:20.782805 DQS Delay:
8774 12:41:20.783145 DQS0 = 0, DQS1 = 0
8775 12:41:20.785794 DQM Delay:
8776 12:41:20.786270 DQM0 = 133, DQM1 = 129
8777 12:41:20.788831 DQ Delay:
8778 12:41:20.792218 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8779 12:41:20.795122 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
8780 12:41:20.798448 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =122
8781 12:41:20.802008 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =136
8782 12:41:20.802647
8783 12:41:20.803218
8784 12:41:20.803581
8785 12:41:20.804799 [DramC_TX_OE_Calibration] TA2
8786 12:41:20.808601 Original DQ_B0 (3 6) =30, OEN = 27
8787 12:41:20.812287 Original DQ_B1 (3 6) =30, OEN = 27
8788 12:41:20.815008 24, 0x0, End_B0=24 End_B1=24
8789 12:41:20.815605 25, 0x0, End_B0=25 End_B1=25
8790 12:41:20.818051 26, 0x0, End_B0=26 End_B1=26
8791 12:41:20.821650 27, 0x0, End_B0=27 End_B1=27
8792 12:41:20.824844 28, 0x0, End_B0=28 End_B1=28
8793 12:41:20.828155 29, 0x0, End_B0=29 End_B1=29
8794 12:41:20.828735 30, 0x0, End_B0=30 End_B1=30
8795 12:41:20.831444 31, 0x4141, End_B0=30 End_B1=30
8796 12:41:20.834859 Byte0 end_step=30 best_step=27
8797 12:41:20.838187 Byte1 end_step=30 best_step=27
8798 12:41:20.841401 Byte0 TX OE(2T, 0.5T) = (3, 3)
8799 12:41:20.844936 Byte1 TX OE(2T, 0.5T) = (3, 3)
8800 12:41:20.845534
8801 12:41:20.845904
8802 12:41:20.851031 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a28, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
8803 12:41:20.854271 CH1 RK0: MR19=303, MR18=1A28
8804 12:41:20.861306 CH1_RK0: MR19=0x303, MR18=0x1A28, DQSOSC=389, MR23=63, INC=24, DEC=16
8805 12:41:20.861878
8806 12:41:20.864506 ----->DramcWriteLeveling(PI) begin...
8807 12:41:20.865118 ==
8808 12:41:20.867652 Dram Type= 6, Freq= 0, CH_1, rank 1
8809 12:41:20.870997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8810 12:41:20.871588 ==
8811 12:41:20.874576 Write leveling (Byte 0): 24 => 24
8812 12:41:20.877362 Write leveling (Byte 1): 29 => 29
8813 12:41:20.880726 DramcWriteLeveling(PI) end<-----
8814 12:41:20.881319
8815 12:41:20.881693 ==
8816 12:41:20.884038 Dram Type= 6, Freq= 0, CH_1, rank 1
8817 12:41:20.887667 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8818 12:41:20.890898 ==
8819 12:41:20.891478 [Gating] SW mode calibration
8820 12:41:20.900440 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8821 12:41:20.903887 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8822 12:41:20.907699 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8823 12:41:20.913653 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8824 12:41:20.917128 1 4 8 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
8825 12:41:20.920758 1 4 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
8826 12:41:20.927497 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8827 12:41:20.930491 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8828 12:41:20.933741 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8829 12:41:20.940413 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8830 12:41:20.943644 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8831 12:41:20.947198 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8832 12:41:20.953660 1 5 8 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 0)
8833 12:41:20.956946 1 5 12 | B1->B0 | 2323 2c2c | 0 1 | (1 0) (1 0)
8834 12:41:20.960385 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8835 12:41:20.966507 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8836 12:41:20.970277 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8837 12:41:20.973625 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8838 12:41:20.979812 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8839 12:41:20.983702 1 6 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8840 12:41:20.986375 1 6 8 | B1->B0 | 4646 2424 | 0 0 | (0 0) (0 0)
8841 12:41:20.992878 1 6 12 | B1->B0 | 4646 3434 | 0 0 | (0 0) (0 0)
8842 12:41:20.996822 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8843 12:41:20.999967 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8844 12:41:21.006257 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8845 12:41:21.009381 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8846 12:41:21.012487 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8847 12:41:21.019436 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8848 12:41:21.022828 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8849 12:41:21.026132 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8850 12:41:21.032874 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 12:41:21.036076 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 12:41:21.039302 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 12:41:21.046004 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 12:41:21.049289 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 12:41:21.052560 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 12:41:21.059320 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 12:41:21.062251 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 12:41:21.065698 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 12:41:21.072558 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 12:41:21.075368 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 12:41:21.078723 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 12:41:21.085314 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 12:41:21.088631 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 12:41:21.091975 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8865 12:41:21.098322 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8866 12:41:21.101758 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8867 12:41:21.104729 Total UI for P1: 0, mck2ui 16
8868 12:41:21.108212 best dqsien dly found for B0: ( 1, 9, 10)
8869 12:41:21.111753 Total UI for P1: 0, mck2ui 16
8870 12:41:21.115145 best dqsien dly found for B1: ( 1, 9, 10)
8871 12:41:21.118181 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8872 12:41:21.121460 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8873 12:41:21.122027
8874 12:41:21.125174 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8875 12:41:21.128282 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8876 12:41:21.131503 [Gating] SW calibration Done
8877 12:41:21.132070 ==
8878 12:41:21.135330 Dram Type= 6, Freq= 0, CH_1, rank 1
8879 12:41:21.141622 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8880 12:41:21.142194 ==
8881 12:41:21.142570 RX Vref Scan: 0
8882 12:41:21.142970
8883 12:41:21.144727 RX Vref 0 -> 0, step: 1
8884 12:41:21.145363
8885 12:41:21.147841 RX Delay 0 -> 252, step: 8
8886 12:41:21.151068 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8887 12:41:21.154676 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8888 12:41:21.158300 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8889 12:41:21.161669 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8890 12:41:21.168144 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8891 12:41:21.171322 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8892 12:41:21.174961 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8893 12:41:21.178081 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8894 12:41:21.181100 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8895 12:41:21.187682 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8896 12:41:21.190715 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8897 12:41:21.194295 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8898 12:41:21.197678 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8899 12:41:21.204264 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8900 12:41:21.207401 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8901 12:41:21.211101 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8902 12:41:21.211670 ==
8903 12:41:21.213921 Dram Type= 6, Freq= 0, CH_1, rank 1
8904 12:41:21.217161 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8905 12:41:21.217642 ==
8906 12:41:21.220844 DQS Delay:
8907 12:41:21.221471 DQS0 = 0, DQS1 = 0
8908 12:41:21.223946 DQM Delay:
8909 12:41:21.224511 DQM0 = 136, DQM1 = 133
8910 12:41:21.224889 DQ Delay:
8911 12:41:21.227634 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8912 12:41:21.233775 DQ4 =135, DQ5 =147, DQ6 =139, DQ7 =135
8913 12:41:21.237278 DQ8 =115, DQ9 =123, DQ10 =135, DQ11 =127
8914 12:41:21.240681 DQ12 =143, DQ13 =139, DQ14 =139, DQ15 =143
8915 12:41:21.241296
8916 12:41:21.241699
8917 12:41:21.242046 ==
8918 12:41:21.244008 Dram Type= 6, Freq= 0, CH_1, rank 1
8919 12:41:21.246696 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8920 12:41:21.247177 ==
8921 12:41:21.247591
8922 12:41:21.247954
8923 12:41:21.250389 TX Vref Scan disable
8924 12:41:21.253523 == TX Byte 0 ==
8925 12:41:21.257069 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8926 12:41:21.260419 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8927 12:41:21.263807 == TX Byte 1 ==
8928 12:41:21.266753 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8929 12:41:21.269854 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8930 12:41:21.270331 ==
8931 12:41:21.273299 Dram Type= 6, Freq= 0, CH_1, rank 1
8932 12:41:21.279898 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8933 12:41:21.280377 ==
8934 12:41:21.291577
8935 12:41:21.294805 TX Vref early break, caculate TX vref
8936 12:41:21.298226 TX Vref=16, minBit 9, minWin=21, winSum=379
8937 12:41:21.301516 TX Vref=18, minBit 13, minWin=22, winSum=388
8938 12:41:21.305033 TX Vref=20, minBit 8, minWin=23, winSum=393
8939 12:41:21.308686 TX Vref=22, minBit 11, minWin=22, winSum=400
8940 12:41:21.311503 TX Vref=24, minBit 9, minWin=24, winSum=411
8941 12:41:21.318075 TX Vref=26, minBit 13, minWin=24, winSum=420
8942 12:41:21.321850 TX Vref=28, minBit 8, minWin=24, winSum=417
8943 12:41:21.324436 TX Vref=30, minBit 8, minWin=24, winSum=411
8944 12:41:21.327912 TX Vref=32, minBit 10, minWin=24, winSum=404
8945 12:41:21.331639 TX Vref=34, minBit 10, minWin=23, winSum=397
8946 12:41:21.337767 [TxChooseVref] Worse bit 13, Min win 24, Win sum 420, Final Vref 26
8947 12:41:21.338326
8948 12:41:21.341405 Final TX Range 0 Vref 26
8949 12:41:21.341993
8950 12:41:21.342367 ==
8951 12:41:21.344586 Dram Type= 6, Freq= 0, CH_1, rank 1
8952 12:41:21.348438 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8953 12:41:21.349053 ==
8954 12:41:21.351031
8955 12:41:21.351601
8956 12:41:21.351973 TX Vref Scan disable
8957 12:41:21.357867 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8958 12:41:21.358449 == TX Byte 0 ==
8959 12:41:21.360955 u2DelayCellOfst[0]=16 cells (5 PI)
8960 12:41:21.364376 u2DelayCellOfst[1]=13 cells (4 PI)
8961 12:41:21.368089 u2DelayCellOfst[2]=0 cells (0 PI)
8962 12:41:21.370845 u2DelayCellOfst[3]=6 cells (2 PI)
8963 12:41:21.374517 u2DelayCellOfst[4]=10 cells (3 PI)
8964 12:41:21.377809 u2DelayCellOfst[5]=20 cells (6 PI)
8965 12:41:21.381047 u2DelayCellOfst[6]=20 cells (6 PI)
8966 12:41:21.384476 u2DelayCellOfst[7]=6 cells (2 PI)
8967 12:41:21.387810 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8968 12:41:21.390911 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8969 12:41:21.394082 == TX Byte 1 ==
8970 12:41:21.397865 u2DelayCellOfst[8]=0 cells (0 PI)
8971 12:41:21.401120 u2DelayCellOfst[9]=6 cells (2 PI)
8972 12:41:21.404069 u2DelayCellOfst[10]=10 cells (3 PI)
8973 12:41:21.407131 u2DelayCellOfst[11]=6 cells (2 PI)
8974 12:41:21.407600 u2DelayCellOfst[12]=16 cells (5 PI)
8975 12:41:21.410769 u2DelayCellOfst[13]=16 cells (5 PI)
8976 12:41:21.414213 u2DelayCellOfst[14]=20 cells (6 PI)
8977 12:41:21.417358 u2DelayCellOfst[15]=20 cells (6 PI)
8978 12:41:21.423797 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8979 12:41:21.427050 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8980 12:41:21.427622 DramC Write-DBI on
8981 12:41:21.430849 ==
8982 12:41:21.433722 Dram Type= 6, Freq= 0, CH_1, rank 1
8983 12:41:21.437027 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8984 12:41:21.437616 ==
8985 12:41:21.437990
8986 12:41:21.438331
8987 12:41:21.440001 TX Vref Scan disable
8988 12:41:21.440467 == TX Byte 0 ==
8989 12:41:21.446971 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8990 12:41:21.447543 == TX Byte 1 ==
8991 12:41:21.450239 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8992 12:41:21.453585 DramC Write-DBI off
8993 12:41:21.454152
8994 12:41:21.454527 [DATLAT]
8995 12:41:21.456646 Freq=1600, CH1 RK1
8996 12:41:21.457154
8997 12:41:21.457527 DATLAT Default: 0xf
8998 12:41:21.459850 0, 0xFFFF, sum = 0
8999 12:41:21.460426 1, 0xFFFF, sum = 0
9000 12:41:21.463117 2, 0xFFFF, sum = 0
9001 12:41:21.463681 3, 0xFFFF, sum = 0
9002 12:41:21.467042 4, 0xFFFF, sum = 0
9003 12:41:21.467619 5, 0xFFFF, sum = 0
9004 12:41:21.469838 6, 0xFFFF, sum = 0
9005 12:41:21.473535 7, 0xFFFF, sum = 0
9006 12:41:21.474107 8, 0xFFFF, sum = 0
9007 12:41:21.476763 9, 0xFFFF, sum = 0
9008 12:41:21.477375 10, 0xFFFF, sum = 0
9009 12:41:21.480047 11, 0xFFFF, sum = 0
9010 12:41:21.480623 12, 0xFFFF, sum = 0
9011 12:41:21.483187 13, 0xFFFF, sum = 0
9012 12:41:21.483768 14, 0x0, sum = 1
9013 12:41:21.486435 15, 0x0, sum = 2
9014 12:41:21.487009 16, 0x0, sum = 3
9015 12:41:21.489809 17, 0x0, sum = 4
9016 12:41:21.490389 best_step = 15
9017 12:41:21.490767
9018 12:41:21.491111 ==
9019 12:41:21.493309 Dram Type= 6, Freq= 0, CH_1, rank 1
9020 12:41:21.496699 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9021 12:41:21.499851 ==
9022 12:41:21.500419 RX Vref Scan: 0
9023 12:41:21.500792
9024 12:41:21.503167 RX Vref 0 -> 0, step: 1
9025 12:41:21.503736
9026 12:41:21.504111 RX Delay 19 -> 252, step: 4
9027 12:41:21.510017 iDelay=195, Bit 0, Center 136 (95 ~ 178) 84
9028 12:41:21.513481 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9029 12:41:21.517213 iDelay=195, Bit 2, Center 122 (75 ~ 170) 96
9030 12:41:21.519934 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9031 12:41:21.523440 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9032 12:41:21.530192 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9033 12:41:21.533483 iDelay=195, Bit 6, Center 140 (95 ~ 186) 92
9034 12:41:21.536780 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
9035 12:41:21.540005 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
9036 12:41:21.543212 iDelay=195, Bit 9, Center 120 (71 ~ 170) 100
9037 12:41:21.549823 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9038 12:41:21.553066 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
9039 12:41:21.556810 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9040 12:41:21.559637 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9041 12:41:21.566248 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9042 12:41:21.569498 iDelay=195, Bit 15, Center 142 (91 ~ 194) 104
9043 12:41:21.570065 ==
9044 12:41:21.573023 Dram Type= 6, Freq= 0, CH_1, rank 1
9045 12:41:21.576246 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9046 12:41:21.576803 ==
9047 12:41:21.577231 DQS Delay:
9048 12:41:21.579527 DQS0 = 0, DQS1 = 0
9049 12:41:21.580095 DQM Delay:
9050 12:41:21.582722 DQM0 = 133, DQM1 = 130
9051 12:41:21.583288 DQ Delay:
9052 12:41:21.586109 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =130
9053 12:41:21.589483 DQ4 =134, DQ5 =146, DQ6 =140, DQ7 =130
9054 12:41:21.593250 DQ8 =112, DQ9 =120, DQ10 =130, DQ11 =126
9055 12:41:21.596076 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =142
9056 12:41:21.599922
9057 12:41:21.600486
9058 12:41:21.600858
9059 12:41:21.601254 [DramC_TX_OE_Calibration] TA2
9060 12:41:21.603081 Original DQ_B0 (3 6) =30, OEN = 27
9061 12:41:21.606252 Original DQ_B1 (3 6) =30, OEN = 27
9062 12:41:21.609566 24, 0x0, End_B0=24 End_B1=24
9063 12:41:21.612654 25, 0x0, End_B0=25 End_B1=25
9064 12:41:21.616394 26, 0x0, End_B0=26 End_B1=26
9065 12:41:21.617012 27, 0x0, End_B0=27 End_B1=27
9066 12:41:21.619064 28, 0x0, End_B0=28 End_B1=28
9067 12:41:21.622694 29, 0x0, End_B0=29 End_B1=29
9068 12:41:21.625624 30, 0x0, End_B0=30 End_B1=30
9069 12:41:21.629276 31, 0x4141, End_B0=30 End_B1=30
9070 12:41:21.632500 Byte0 end_step=30 best_step=27
9071 12:41:21.633001 Byte1 end_step=30 best_step=27
9072 12:41:21.635830 Byte0 TX OE(2T, 0.5T) = (3, 3)
9073 12:41:21.639502 Byte1 TX OE(2T, 0.5T) = (3, 3)
9074 12:41:21.640234
9075 12:41:21.640640
9076 12:41:21.648930 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e09, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
9077 12:41:21.649531 CH1 RK1: MR19=303, MR18=1E09
9078 12:41:21.655822 CH1_RK1: MR19=0x303, MR18=0x1E09, DQSOSC=394, MR23=63, INC=23, DEC=15
9079 12:41:21.658842 [RxdqsGatingPostProcess] freq 1600
9080 12:41:21.665614 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9081 12:41:21.669315 best DQS0 dly(2T, 0.5T) = (1, 1)
9082 12:41:21.671947 best DQS1 dly(2T, 0.5T) = (1, 1)
9083 12:41:21.675389 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9084 12:41:21.678901 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9085 12:41:21.679472 best DQS0 dly(2T, 0.5T) = (1, 1)
9086 12:41:21.682011 best DQS1 dly(2T, 0.5T) = (1, 1)
9087 12:41:21.685271 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9088 12:41:21.688540 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9089 12:41:21.692298 Pre-setting of DQS Precalculation
9090 12:41:21.698944 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9091 12:41:21.705539 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9092 12:41:21.712019 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9093 12:41:21.712592
9094 12:41:21.712964
9095 12:41:21.715150 [Calibration Summary] 3200 Mbps
9096 12:41:21.715711 CH 0, Rank 0
9097 12:41:21.718106 SW Impedance : PASS
9098 12:41:21.721606 DUTY Scan : NO K
9099 12:41:21.722077 ZQ Calibration : PASS
9100 12:41:21.724896 Jitter Meter : NO K
9101 12:41:21.727986 CBT Training : PASS
9102 12:41:21.728554 Write leveling : PASS
9103 12:41:21.731444 RX DQS gating : PASS
9104 12:41:21.734680 RX DQ/DQS(RDDQC) : PASS
9105 12:41:21.735152 TX DQ/DQS : PASS
9106 12:41:21.737991 RX DATLAT : PASS
9107 12:41:21.741007 RX DQ/DQS(Engine): PASS
9108 12:41:21.741621 TX OE : PASS
9109 12:41:21.744550 All Pass.
9110 12:41:21.745050
9111 12:41:21.745429 CH 0, Rank 1
9112 12:41:21.747558 SW Impedance : PASS
9113 12:41:21.748027 DUTY Scan : NO K
9114 12:41:21.751112 ZQ Calibration : PASS
9115 12:41:21.754546 Jitter Meter : NO K
9116 12:41:21.755132 CBT Training : PASS
9117 12:41:21.757592 Write leveling : PASS
9118 12:41:21.761413 RX DQS gating : PASS
9119 12:41:21.761982 RX DQ/DQS(RDDQC) : PASS
9120 12:41:21.763961 TX DQ/DQS : PASS
9121 12:41:21.767562 RX DATLAT : PASS
9122 12:41:21.768131 RX DQ/DQS(Engine): PASS
9123 12:41:21.770538 TX OE : PASS
9124 12:41:21.771069 All Pass.
9125 12:41:21.771449
9126 12:41:21.774463 CH 1, Rank 0
9127 12:41:21.775033 SW Impedance : PASS
9128 12:41:21.777442 DUTY Scan : NO K
9129 12:41:21.780891 ZQ Calibration : PASS
9130 12:41:21.781497 Jitter Meter : NO K
9131 12:41:21.784051 CBT Training : PASS
9132 12:41:21.784617 Write leveling : PASS
9133 12:41:21.787550 RX DQS gating : PASS
9134 12:41:21.790639 RX DQ/DQS(RDDQC) : PASS
9135 12:41:21.791208 TX DQ/DQS : PASS
9136 12:41:21.794258 RX DATLAT : PASS
9137 12:41:21.797548 RX DQ/DQS(Engine): PASS
9138 12:41:21.798115 TX OE : PASS
9139 12:41:21.800642 All Pass.
9140 12:41:21.801243
9141 12:41:21.801619 CH 1, Rank 1
9142 12:41:21.804046 SW Impedance : PASS
9143 12:41:21.804613 DUTY Scan : NO K
9144 12:41:21.807058 ZQ Calibration : PASS
9145 12:41:21.810721 Jitter Meter : NO K
9146 12:41:21.811288 CBT Training : PASS
9147 12:41:21.813748 Write leveling : PASS
9148 12:41:21.817243 RX DQS gating : PASS
9149 12:41:21.817803 RX DQ/DQS(RDDQC) : PASS
9150 12:41:21.820585 TX DQ/DQS : PASS
9151 12:41:21.824042 RX DATLAT : PASS
9152 12:41:21.824612 RX DQ/DQS(Engine): PASS
9153 12:41:21.827127 TX OE : PASS
9154 12:41:21.827702 All Pass.
9155 12:41:21.828079
9156 12:41:21.830294 DramC Write-DBI on
9157 12:41:21.833806 PER_BANK_REFRESH: Hybrid Mode
9158 12:41:21.834277 TX_TRACKING: ON
9159 12:41:21.843490 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9160 12:41:21.849867 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9161 12:41:21.856560 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9162 12:41:21.860248 [FAST_K] Save calibration result to emmc
9163 12:41:21.863600 sync common calibartion params.
9164 12:41:21.866770 sync cbt_mode0:1, 1:1
9165 12:41:21.869980 dram_init: ddr_geometry: 2
9166 12:41:21.870551 dram_init: ddr_geometry: 2
9167 12:41:21.873614 dram_init: ddr_geometry: 2
9168 12:41:21.876519 0:dram_rank_size:100000000
9169 12:41:21.879713 1:dram_rank_size:100000000
9170 12:41:21.883486 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9171 12:41:21.886276 DFS_SHUFFLE_HW_MODE: ON
9172 12:41:21.889623 dramc_set_vcore_voltage set vcore to 725000
9173 12:41:21.893387 Read voltage for 1600, 0
9174 12:41:21.893953 Vio18 = 0
9175 12:41:21.894331 Vcore = 725000
9176 12:41:21.896471 Vdram = 0
9177 12:41:21.897065 Vddq = 0
9178 12:41:21.897441 Vmddr = 0
9179 12:41:21.899891 switch to 3200 Mbps bootup
9180 12:41:21.903304 [DramcRunTimeConfig]
9181 12:41:21.903869 PHYPLL
9182 12:41:21.904244 DPM_CONTROL_AFTERK: ON
9183 12:41:21.906613 PER_BANK_REFRESH: ON
9184 12:41:21.909394 REFRESH_OVERHEAD_REDUCTION: ON
9185 12:41:21.913103 CMD_PICG_NEW_MODE: OFF
9186 12:41:21.913661 XRTWTW_NEW_MODE: ON
9187 12:41:21.916107 XRTRTR_NEW_MODE: ON
9188 12:41:21.916674 TX_TRACKING: ON
9189 12:41:21.919399 RDSEL_TRACKING: OFF
9190 12:41:21.919974 DQS Precalculation for DVFS: ON
9191 12:41:21.923203 RX_TRACKING: OFF
9192 12:41:21.923769 HW_GATING DBG: ON
9193 12:41:21.926025 ZQCS_ENABLE_LP4: ON
9194 12:41:21.929278 RX_PICG_NEW_MODE: ON
9195 12:41:21.929744 TX_PICG_NEW_MODE: ON
9196 12:41:21.932909 ENABLE_RX_DCM_DPHY: ON
9197 12:41:21.935960 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9198 12:41:21.936533 DUMMY_READ_FOR_TRACKING: OFF
9199 12:41:21.939365 !!! SPM_CONTROL_AFTERK: OFF
9200 12:41:21.942694 !!! SPM could not control APHY
9201 12:41:21.945821 IMPEDANCE_TRACKING: ON
9202 12:41:21.946357 TEMP_SENSOR: ON
9203 12:41:21.949615 HW_SAVE_FOR_SR: OFF
9204 12:41:21.952333 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9205 12:41:21.955708 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9206 12:41:21.956321 Read ODT Tracking: ON
9207 12:41:21.959432 Refresh Rate DeBounce: ON
9208 12:41:21.962520 DFS_NO_QUEUE_FLUSH: ON
9209 12:41:21.965609 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9210 12:41:21.966125 ENABLE_DFS_RUNTIME_MRW: OFF
9211 12:41:21.969153 DDR_RESERVE_NEW_MODE: ON
9212 12:41:21.972311 MR_CBT_SWITCH_FREQ: ON
9213 12:41:21.972885 =========================
9214 12:41:21.992666 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9215 12:41:21.995769 dram_init: ddr_geometry: 2
9216 12:41:22.013947 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9217 12:41:22.017132 dram_init: dram init end (result: 0)
9218 12:41:22.023631 DRAM-K: Full calibration passed in 24509 msecs
9219 12:41:22.026869 MRC: failed to locate region type 0.
9220 12:41:22.027438 DRAM rank0 size:0x100000000,
9221 12:41:22.030548 DRAM rank1 size=0x100000000
9222 12:41:22.040451 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9223 12:41:22.046950 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9224 12:41:22.053409 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9225 12:41:22.063274 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9226 12:41:22.063856 DRAM rank0 size:0x100000000,
9227 12:41:22.066871 DRAM rank1 size=0x100000000
9228 12:41:22.067437 CBMEM:
9229 12:41:22.069641 IMD: root @ 0xfffff000 254 entries.
9230 12:41:22.073217 IMD: root @ 0xffffec00 62 entries.
9231 12:41:22.076498 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9232 12:41:22.082771 WARNING: RO_VPD is uninitialized or empty.
9233 12:41:22.086317 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9234 12:41:22.093718 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9235 12:41:22.106391 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9236 12:41:22.118168 BS: romstage times (exec / console): total (unknown) / 24009 ms
9237 12:41:22.118733
9238 12:41:22.119104
9239 12:41:22.127745 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9240 12:41:22.131127 ARM64: Exception handlers installed.
9241 12:41:22.134511 ARM64: Testing exception
9242 12:41:22.137875 ARM64: Done test exception
9243 12:41:22.138430 Enumerating buses...
9244 12:41:22.141327 Show all devs... Before device enumeration.
9245 12:41:22.144276 Root Device: enabled 1
9246 12:41:22.147756 CPU_CLUSTER: 0: enabled 1
9247 12:41:22.148317 CPU: 00: enabled 1
9248 12:41:22.151132 Compare with tree...
9249 12:41:22.151723 Root Device: enabled 1
9250 12:41:22.154398 CPU_CLUSTER: 0: enabled 1
9251 12:41:22.157801 CPU: 00: enabled 1
9252 12:41:22.158366 Root Device scanning...
9253 12:41:22.161292 scan_static_bus for Root Device
9254 12:41:22.164783 CPU_CLUSTER: 0 enabled
9255 12:41:22.167863 scan_static_bus for Root Device done
9256 12:41:22.170696 scan_bus: bus Root Device finished in 8 msecs
9257 12:41:22.171196 done
9258 12:41:22.177313 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9259 12:41:22.180588 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9260 12:41:22.187566 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9261 12:41:22.190977 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9262 12:41:22.194142 Allocating resources...
9263 12:41:22.197622 Reading resources...
9264 12:41:22.200840 Root Device read_resources bus 0 link: 0
9265 12:41:22.201461 DRAM rank0 size:0x100000000,
9266 12:41:22.204351 DRAM rank1 size=0x100000000
9267 12:41:22.208198 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9268 12:41:22.210588 CPU: 00 missing read_resources
9269 12:41:22.217122 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9270 12:41:22.220448 Root Device read_resources bus 0 link: 0 done
9271 12:41:22.221059 Done reading resources.
9272 12:41:22.227096 Show resources in subtree (Root Device)...After reading.
9273 12:41:22.230419 Root Device child on link 0 CPU_CLUSTER: 0
9274 12:41:22.233691 CPU_CLUSTER: 0 child on link 0 CPU: 00
9275 12:41:22.243989 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9276 12:41:22.244568 CPU: 00
9277 12:41:22.246999 Root Device assign_resources, bus 0 link: 0
9278 12:41:22.250391 CPU_CLUSTER: 0 missing set_resources
9279 12:41:22.256699 Root Device assign_resources, bus 0 link: 0 done
9280 12:41:22.257317 Done setting resources.
9281 12:41:22.263447 Show resources in subtree (Root Device)...After assigning values.
9282 12:41:22.266552 Root Device child on link 0 CPU_CLUSTER: 0
9283 12:41:22.270045 CPU_CLUSTER: 0 child on link 0 CPU: 00
9284 12:41:22.279753 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9285 12:41:22.280392 CPU: 00
9286 12:41:22.283158 Done allocating resources.
9287 12:41:22.289715 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9288 12:41:22.290189 Enabling resources...
9289 12:41:22.290561 done.
9290 12:41:22.296448 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9291 12:41:22.299721 Initializing devices...
9292 12:41:22.300194 Root Device init
9293 12:41:22.302962 init hardware done!
9294 12:41:22.303433 0x00000018: ctrlr->caps
9295 12:41:22.305949 52.000 MHz: ctrlr->f_max
9296 12:41:22.309592 0.400 MHz: ctrlr->f_min
9297 12:41:22.310097 0x40ff8080: ctrlr->voltages
9298 12:41:22.312895 sclk: 390625
9299 12:41:22.313391 Bus Width = 1
9300 12:41:22.313781 sclk: 390625
9301 12:41:22.316141 Bus Width = 1
9302 12:41:22.316605 Early init status = 3
9303 12:41:22.323134 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9304 12:41:22.326175 in-header: 03 fc 00 00 01 00 00 00
9305 12:41:22.329620 in-data: 00
9306 12:41:22.332718 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9307 12:41:22.336899 in-header: 03 fd 00 00 00 00 00 00
9308 12:41:22.339858 in-data:
9309 12:41:22.343281 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9310 12:41:22.347390 in-header: 03 fc 00 00 01 00 00 00
9311 12:41:22.350667 in-data: 00
9312 12:41:22.354088 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9313 12:41:22.359667 in-header: 03 fd 00 00 00 00 00 00
9314 12:41:22.363384 in-data:
9315 12:41:22.366217 [SSUSB] Setting up USB HOST controller...
9316 12:41:22.369608 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9317 12:41:22.372708 [SSUSB] phy power-on done.
9318 12:41:22.376344 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9319 12:41:22.382616 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9320 12:41:22.385949 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9321 12:41:22.392574 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9322 12:41:22.399268 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9323 12:41:22.405675 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9324 12:41:22.412268 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9325 12:41:22.419123 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9326 12:41:22.422024 SPM: binary array size = 0x9dc
9327 12:41:22.425715 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9328 12:41:22.432473 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9329 12:41:22.438529 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9330 12:41:22.445677 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9331 12:41:22.448736 configure_display: Starting display init
9332 12:41:22.482783 anx7625_power_on_init: Init interface.
9333 12:41:22.486319 anx7625_disable_pd_protocol: Disabled PD feature.
9334 12:41:22.489751 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9335 12:41:22.517262 anx7625_start_dp_work: Secure OCM version=00
9336 12:41:22.520615 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9337 12:41:22.535653 sp_tx_get_edid_block: EDID Block = 1
9338 12:41:22.637968 Extracted contents:
9339 12:41:22.641422 header: 00 ff ff ff ff ff ff 00
9340 12:41:22.644627 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9341 12:41:22.647898 version: 01 04
9342 12:41:22.650937 basic params: 95 1f 11 78 0a
9343 12:41:22.654144 chroma info: 76 90 94 55 54 90 27 21 50 54
9344 12:41:22.657845 established: 00 00 00
9345 12:41:22.664330 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9346 12:41:22.670987 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9347 12:41:22.673801 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9348 12:41:22.680874 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9349 12:41:22.687337 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9350 12:41:22.690400 extensions: 00
9351 12:41:22.690891 checksum: fb
9352 12:41:22.691381
9353 12:41:22.697225 Manufacturer: IVO Model 57d Serial Number 0
9354 12:41:22.697827 Made week 0 of 2020
9355 12:41:22.700421 EDID version: 1.4
9356 12:41:22.701028 Digital display
9357 12:41:22.703785 6 bits per primary color channel
9358 12:41:22.704386 DisplayPort interface
9359 12:41:22.706945 Maximum image size: 31 cm x 17 cm
9360 12:41:22.710312 Gamma: 220%
9361 12:41:22.710887 Check DPMS levels
9362 12:41:22.717124 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9363 12:41:22.720020 First detailed timing is preferred timing
9364 12:41:22.720505 Established timings supported:
9365 12:41:22.723443 Standard timings supported:
9366 12:41:22.726668 Detailed timings
9367 12:41:22.730118 Hex of detail: 383680a07038204018303c0035ae10000019
9368 12:41:22.736687 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9369 12:41:22.740113 0780 0798 07c8 0820 hborder 0
9370 12:41:22.743829 0438 043b 0447 0458 vborder 0
9371 12:41:22.746375 -hsync -vsync
9372 12:41:22.746660 Did detailed timing
9373 12:41:22.752851 Hex of detail: 000000000000000000000000000000000000
9374 12:41:22.756194 Manufacturer-specified data, tag 0
9375 12:41:22.759430 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9376 12:41:22.762587 ASCII string: InfoVision
9377 12:41:22.765725 Hex of detail: 000000fe00523134304e574635205248200a
9378 12:41:22.769234 ASCII string: R140NWF5 RH
9379 12:41:22.769342 Checksum
9380 12:41:22.772547 Checksum: 0xfb (valid)
9381 12:41:22.775846 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9382 12:41:22.779222 DSI data_rate: 832800000 bps
9383 12:41:22.785840 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9384 12:41:22.789231 anx7625_parse_edid: pixelclock(138800).
9385 12:41:22.792470 hactive(1920), hsync(48), hfp(24), hbp(88)
9386 12:41:22.796020 vactive(1080), vsync(12), vfp(3), vbp(17)
9387 12:41:22.799168 anx7625_dsi_config: config dsi.
9388 12:41:22.805557 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9389 12:41:22.819334 anx7625_dsi_config: success to config DSI
9390 12:41:22.822681 anx7625_dp_start: MIPI phy setup OK.
9391 12:41:22.826130 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9392 12:41:22.829524 mtk_ddp_mode_set invalid vrefresh 60
9393 12:41:22.833047 main_disp_path_setup
9394 12:41:22.833501 ovl_layer_smi_id_en
9395 12:41:22.836514 ovl_layer_smi_id_en
9396 12:41:22.836966 ccorr_config
9397 12:41:22.837367 aal_config
9398 12:41:22.839905 gamma_config
9399 12:41:22.840454 postmask_config
9400 12:41:22.843371 dither_config
9401 12:41:22.846262 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9402 12:41:22.853422 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9403 12:41:22.856204 Root Device init finished in 553 msecs
9404 12:41:22.859717 CPU_CLUSTER: 0 init
9405 12:41:22.866509 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9406 12:41:22.869683 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9407 12:41:22.873337 APU_MBOX 0x190000b0 = 0x10001
9408 12:41:22.876269 APU_MBOX 0x190001b0 = 0x10001
9409 12:41:22.879318 APU_MBOX 0x190005b0 = 0x10001
9410 12:41:22.882696 APU_MBOX 0x190006b0 = 0x10001
9411 12:41:22.889292 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9412 12:41:22.898866 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9413 12:41:22.911289 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9414 12:41:22.917622 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9415 12:41:22.929352 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9416 12:41:22.938836 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9417 12:41:22.941856 CPU_CLUSTER: 0 init finished in 81 msecs
9418 12:41:22.945642 Devices initialized
9419 12:41:22.948592 Show all devs... After init.
9420 12:41:22.949212 Root Device: enabled 1
9421 12:41:22.951697 CPU_CLUSTER: 0: enabled 1
9422 12:41:22.955417 CPU: 00: enabled 1
9423 12:41:22.958829 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9424 12:41:22.961825 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9425 12:41:22.965087 ELOG: NV offset 0x57f000 size 0x1000
9426 12:41:22.972143 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9427 12:41:22.978075 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9428 12:41:22.981502 ELOG: Event(17) added with size 13 at 2023-06-14 12:41:18 UTC
9429 12:41:22.988704 out: cmd=0x121: 03 db 21 01 00 00 00 00
9430 12:41:22.991697 in-header: 03 29 00 00 2c 00 00 00
9431 12:41:23.001482 in-data: 36 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9432 12:41:23.008279 ELOG: Event(A1) added with size 10 at 2023-06-14 12:41:18 UTC
9433 12:41:23.014409 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9434 12:41:23.021134 ELOG: Event(A0) added with size 9 at 2023-06-14 12:41:18 UTC
9435 12:41:23.024497 elog_add_boot_reason: Logged dev mode boot
9436 12:41:23.030821 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9437 12:41:23.031465 Finalize devices...
9438 12:41:23.034297 Devices finalized
9439 12:41:23.037423 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9440 12:41:23.040638 Writing coreboot table at 0xffe64000
9441 12:41:23.044374 0. 000000000010a000-0000000000113fff: RAMSTAGE
9442 12:41:23.050586 1. 0000000040000000-00000000400fffff: RAM
9443 12:41:23.054140 2. 0000000040100000-000000004032afff: RAMSTAGE
9444 12:41:23.057057 3. 000000004032b000-00000000545fffff: RAM
9445 12:41:23.060873 4. 0000000054600000-000000005465ffff: BL31
9446 12:41:23.063846 5. 0000000054660000-00000000ffe63fff: RAM
9447 12:41:23.070351 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9448 12:41:23.073636 7. 0000000100000000-000000023fffffff: RAM
9449 12:41:23.076949 Passing 5 GPIOs to payload:
9450 12:41:23.080048 NAME | PORT | POLARITY | VALUE
9451 12:41:23.086985 EC in RW | 0x000000aa | low | undefined
9452 12:41:23.090066 EC interrupt | 0x00000005 | low | undefined
9453 12:41:23.097001 TPM interrupt | 0x000000ab | high | undefined
9454 12:41:23.100033 SD card detect | 0x00000011 | high | undefined
9455 12:41:23.103227 speaker enable | 0x00000093 | high | undefined
9456 12:41:23.106601 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9457 12:41:23.109944 in-header: 03 f9 00 00 02 00 00 00
9458 12:41:23.113117 in-data: 02 00
9459 12:41:23.116307 ADC[4]: Raw value=901401 ID=7
9460 12:41:23.120042 ADC[3]: Raw value=213179 ID=1
9461 12:41:23.120509 RAM Code: 0x71
9462 12:41:23.122868 ADC[6]: Raw value=74502 ID=0
9463 12:41:23.126116 ADC[5]: Raw value=212072 ID=1
9464 12:41:23.126515 SKU Code: 0x1
9465 12:41:23.132557 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4bb3
9466 12:41:23.132802 coreboot table: 964 bytes.
9467 12:41:23.135863 IMD ROOT 0. 0xfffff000 0x00001000
9468 12:41:23.139239 IMD SMALL 1. 0xffffe000 0x00001000
9469 12:41:23.142234 RO MCACHE 2. 0xffffc000 0x00001104
9470 12:41:23.145713 CONSOLE 3. 0xfff7c000 0x00080000
9471 12:41:23.148872 FMAP 4. 0xfff7b000 0x00000452
9472 12:41:23.152211 TIME STAMP 5. 0xfff7a000 0x00000910
9473 12:41:23.155974 VBOOT WORK 6. 0xfff66000 0x00014000
9474 12:41:23.159113 RAMOOPS 7. 0xffe66000 0x00100000
9475 12:41:23.162578 COREBOOT 8. 0xffe64000 0x00002000
9476 12:41:23.165959 IMD small region:
9477 12:41:23.169110 IMD ROOT 0. 0xffffec00 0x00000400
9478 12:41:23.172522 VPD 1. 0xffffeba0 0x0000004c
9479 12:41:23.175737 MMC STATUS 2. 0xffffeb80 0x00000004
9480 12:41:23.182598 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9481 12:41:23.182892 Probing TPM: done!
9482 12:41:23.188882 Connected to device vid:did:rid of 1ae0:0028:00
9483 12:41:23.195781 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9484 12:41:23.198974 Initialized TPM device CR50 revision 0
9485 12:41:23.202309 Checking cr50 for pending updates
9486 12:41:23.207794 Reading cr50 TPM mode
9487 12:41:23.216860 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9488 12:41:23.223194 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9489 12:41:23.263185 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9490 12:41:23.266224 Checking segment from ROM address 0x40100000
9491 12:41:23.269553 Checking segment from ROM address 0x4010001c
9492 12:41:23.276578 Loading segment from ROM address 0x40100000
9493 12:41:23.276668 code (compression=0)
9494 12:41:23.286123 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9495 12:41:23.292850 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9496 12:41:23.293005 it's not compressed!
9497 12:41:23.299799 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9498 12:41:23.306256 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9499 12:41:23.323777 Loading segment from ROM address 0x4010001c
9500 12:41:23.324076 Entry Point 0x80000000
9501 12:41:23.326978 Loaded segments
9502 12:41:23.330253 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9503 12:41:23.337130 Jumping to boot code at 0x80000000(0xffe64000)
9504 12:41:23.343873 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9505 12:41:23.350206 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9506 12:41:23.358625 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9507 12:41:23.361485 Checking segment from ROM address 0x40100000
9508 12:41:23.365085 Checking segment from ROM address 0x4010001c
9509 12:41:23.371460 Loading segment from ROM address 0x40100000
9510 12:41:23.371932 code (compression=1)
9511 12:41:23.377963 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9512 12:41:23.387754 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9513 12:41:23.388227 using LZMA
9514 12:41:23.396812 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9515 12:41:23.403411 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9516 12:41:23.407218 Loading segment from ROM address 0x4010001c
9517 12:41:23.407744 Entry Point 0x54601000
9518 12:41:23.410242 Loaded segments
9519 12:41:23.413423 NOTICE: MT8192 bl31_setup
9520 12:41:23.420228 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9521 12:41:23.423639 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9522 12:41:23.426572 WARNING: region 0:
9523 12:41:23.429969 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9524 12:41:23.430479 WARNING: region 1:
9525 12:41:23.436833 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9526 12:41:23.440137 WARNING: region 2:
9527 12:41:23.443132 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9528 12:41:23.446825 WARNING: region 3:
9529 12:41:23.449999 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9530 12:41:23.453274 WARNING: region 4:
9531 12:41:23.459995 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9532 12:41:23.460506 WARNING: region 5:
9533 12:41:23.463217 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9534 12:41:23.466630 WARNING: region 6:
9535 12:41:23.470035 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9536 12:41:23.473042 WARNING: region 7:
9537 12:41:23.477078 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9538 12:41:23.483542 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9539 12:41:23.486367 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9540 12:41:23.489789 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9541 12:41:23.496941 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9542 12:41:23.500010 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9543 12:41:23.502989 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9544 12:41:23.509775 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9545 12:41:23.513282 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9546 12:41:23.519702 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9547 12:41:23.522735 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9548 12:41:23.526116 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9549 12:41:23.532670 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9550 12:41:23.536055 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9551 12:41:23.542848 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9552 12:41:23.546450 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9553 12:41:23.549353 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9554 12:41:23.555807 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9555 12:41:23.559036 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9556 12:41:23.562602 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9557 12:41:23.568962 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9558 12:41:23.572479 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9559 12:41:23.579110 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9560 12:41:23.582494 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9561 12:41:23.585545 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9562 12:41:23.592564 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9563 12:41:23.596344 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9564 12:41:23.602534 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9565 12:41:23.605678 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9566 12:41:23.609314 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9567 12:41:23.615885 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9568 12:41:23.618973 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9569 12:41:23.625429 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9570 12:41:23.629453 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9571 12:41:23.633106 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9572 12:41:23.636316 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9573 12:41:23.642545 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9574 12:41:23.645812 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9575 12:41:23.649238 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9576 12:41:23.652624 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9577 12:41:23.660042 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9578 12:41:23.663139 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9579 12:41:23.665862 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9580 12:41:23.669364 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9581 12:41:23.675816 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9582 12:41:23.679377 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9583 12:41:23.682836 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9584 12:41:23.685768 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9585 12:41:23.692331 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9586 12:41:23.695949 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9587 12:41:23.702744 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9588 12:41:23.706287 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9589 12:41:23.709361 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9590 12:41:23.716300 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9591 12:41:23.718832 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9592 12:41:23.725999 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9593 12:41:23.729046 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9594 12:41:23.732682 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9595 12:41:23.739626 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9596 12:41:23.742404 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9597 12:41:23.749160 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9598 12:41:23.752589 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9599 12:41:23.759172 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9600 12:41:23.762434 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9601 12:41:23.768998 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9602 12:41:23.772643 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9603 12:41:23.778587 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9604 12:41:23.782263 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9605 12:41:23.785317 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9606 12:41:23.791884 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9607 12:41:23.795599 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9608 12:41:23.802258 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9609 12:41:23.805728 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9610 12:41:23.809159 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9611 12:41:23.815545 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9612 12:41:23.818855 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9613 12:41:23.825334 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9614 12:41:23.828624 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9615 12:41:23.835269 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9616 12:41:23.838846 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9617 12:41:23.845045 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9618 12:41:23.848500 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9619 12:41:23.851766 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9620 12:41:23.858420 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9621 12:41:23.861788 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9622 12:41:23.868827 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9623 12:41:23.872179 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9624 12:41:23.878507 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9625 12:41:23.881757 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9626 12:41:23.884818 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9627 12:41:23.891761 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9628 12:41:23.895067 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9629 12:41:23.901821 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9630 12:41:23.904657 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9631 12:41:23.911682 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9632 12:41:23.915155 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9633 12:41:23.921616 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9634 12:41:23.925136 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9635 12:41:23.928457 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9636 12:41:23.931676 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9637 12:41:23.938169 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9638 12:41:23.941491 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9639 12:41:23.945269 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9640 12:41:23.951892 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9641 12:41:23.954954 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9642 12:41:23.961396 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9643 12:41:23.964745 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9644 12:41:23.968621 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9645 12:41:23.975099 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9646 12:41:23.977770 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9647 12:41:23.984729 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9648 12:41:23.988125 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9649 12:41:23.991405 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9650 12:41:23.997728 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9651 12:41:24.001107 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9652 12:41:24.007818 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9653 12:41:24.011470 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9654 12:41:24.014670 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9655 12:41:24.020669 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9656 12:41:24.024332 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9657 12:41:24.027938 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9658 12:41:24.030873 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9659 12:41:24.037823 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9660 12:41:24.041223 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9661 12:41:24.044169 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9662 12:41:24.051124 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9663 12:41:24.053976 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9664 12:41:24.057483 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9665 12:41:24.064298 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9666 12:41:24.067536 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9667 12:41:24.070936 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9668 12:41:24.077571 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9669 12:41:24.080682 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9670 12:41:24.087027 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9671 12:41:24.090690 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9672 12:41:24.093803 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9673 12:41:24.100565 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9674 12:41:24.103998 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9675 12:41:24.110755 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9676 12:41:24.113862 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9677 12:41:24.117858 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9678 12:41:24.123812 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9679 12:41:24.126760 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9680 12:41:24.133797 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9681 12:41:24.137117 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9682 12:41:24.139855 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9683 12:41:24.146844 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9684 12:41:24.150393 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9685 12:41:24.156827 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9686 12:41:24.160561 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9687 12:41:24.163575 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9688 12:41:24.170309 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9689 12:41:24.173291 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9690 12:41:24.177366 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9691 12:41:24.183481 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9692 12:41:24.187189 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9693 12:41:24.193717 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9694 12:41:24.196962 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9695 12:41:24.200125 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9696 12:41:24.206573 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9697 12:41:24.209988 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9698 12:41:24.216494 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9699 12:41:24.219821 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9700 12:41:24.223193 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9701 12:41:24.229587 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9702 12:41:24.233074 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9703 12:41:24.239676 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9704 12:41:24.243017 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9705 12:41:24.246350 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9706 12:41:24.253171 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9707 12:41:24.256203 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9708 12:41:24.262798 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9709 12:41:24.265992 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9710 12:41:24.269202 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9711 12:41:24.276066 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9712 12:41:24.279221 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9713 12:41:24.286259 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9714 12:41:24.289704 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9715 12:41:24.292610 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9716 12:41:24.299100 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9717 12:41:24.302951 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9718 12:41:24.309454 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9719 12:41:24.312387 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9720 12:41:24.315922 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9721 12:41:24.322166 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9722 12:41:24.325865 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9723 12:41:24.332051 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9724 12:41:24.335417 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9725 12:41:24.338535 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9726 12:41:24.345295 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9727 12:41:24.348320 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9728 12:41:24.355214 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9729 12:41:24.358316 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9730 12:41:24.365097 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9731 12:41:24.368606 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9732 12:41:24.371609 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9733 12:41:24.378267 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9734 12:41:24.381549 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9735 12:41:24.388599 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9736 12:41:24.391483 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9737 12:41:24.398427 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9738 12:41:24.401775 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9739 12:41:24.404534 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9740 12:41:24.411481 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9741 12:41:24.414794 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9742 12:41:24.421083 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9743 12:41:24.424692 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9744 12:41:24.431118 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9745 12:41:24.434433 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9746 12:41:24.437372 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9747 12:41:24.444900 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9748 12:41:24.447630 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9749 12:41:24.454199 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9750 12:41:24.457267 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9751 12:41:24.464344 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9752 12:41:24.467395 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9753 12:41:24.470850 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9754 12:41:24.477432 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9755 12:41:24.480619 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9756 12:41:24.487319 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9757 12:41:24.490602 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9758 12:41:24.494021 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9759 12:41:24.500535 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9760 12:41:24.503717 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9761 12:41:24.510044 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9762 12:41:24.513867 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9763 12:41:24.520067 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9764 12:41:24.523131 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9765 12:41:24.526655 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9766 12:41:24.533344 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9767 12:41:24.536420 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9768 12:41:24.539886 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9769 12:41:24.543117 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9770 12:41:24.549830 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9771 12:41:24.553831 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9772 12:41:24.557059 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9773 12:41:24.562979 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9774 12:41:24.566561 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9775 12:41:24.573399 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9776 12:41:24.576957 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9777 12:41:24.579725 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9778 12:41:24.586090 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9779 12:41:24.589567 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9780 12:41:24.592860 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9781 12:41:24.599641 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9782 12:41:24.602448 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9783 12:41:24.609273 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9784 12:41:24.612686 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9785 12:41:24.615978 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9786 12:41:24.622494 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9787 12:41:24.626101 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9788 12:41:24.629082 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9789 12:41:24.635604 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9790 12:41:24.639360 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9791 12:41:24.642737 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9792 12:41:24.649072 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9793 12:41:24.652491 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9794 12:41:24.659444 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9795 12:41:24.662077 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9796 12:41:24.665907 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9797 12:41:24.672222 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9798 12:41:24.675493 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9799 12:41:24.682074 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9800 12:41:24.685544 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9801 12:41:24.688766 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9802 12:41:24.695210 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9803 12:41:24.698375 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9804 12:41:24.701614 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9805 12:41:24.708521 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9806 12:41:24.711392 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9807 12:41:24.714729 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9808 12:41:24.721411 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9809 12:41:24.724396 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9810 12:41:24.727719 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9811 12:41:24.731039 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9812 12:41:24.738026 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9813 12:41:24.741023 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9814 12:41:24.744568 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9815 12:41:24.747864 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9816 12:41:24.754305 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9817 12:41:24.757373 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9818 12:41:24.761117 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9819 12:41:24.764303 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9820 12:41:24.770856 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9821 12:41:24.773911 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9822 12:41:24.780821 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9823 12:41:24.784025 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9824 12:41:24.790514 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9825 12:41:24.793862 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9826 12:41:24.797069 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9827 12:41:24.803999 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9828 12:41:24.807340 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9829 12:41:24.813752 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9830 12:41:24.817420 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9831 12:41:24.820502 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9832 12:41:24.827305 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9833 12:41:24.830286 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9834 12:41:24.836956 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9835 12:41:24.840258 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9836 12:41:24.843159 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9837 12:41:24.849966 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9838 12:41:24.853847 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9839 12:41:24.860109 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9840 12:41:24.863145 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9841 12:41:24.869572 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9842 12:41:24.873021 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9843 12:41:24.876129 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9844 12:41:24.882845 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9845 12:41:24.886036 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9846 12:41:24.892663 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9847 12:41:24.896098 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9848 12:41:24.902616 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9849 12:41:24.906194 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9850 12:41:24.909440 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9851 12:41:24.916579 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9852 12:41:24.919823 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9853 12:41:24.925933 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9854 12:41:24.928970 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9855 12:41:24.932588 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9856 12:41:24.939123 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9857 12:41:24.942793 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9858 12:41:24.949439 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9859 12:41:24.952651 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9860 12:41:24.955568 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9861 12:41:24.962560 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9862 12:41:24.965548 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9863 12:41:24.972252 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9864 12:41:24.975947 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9865 12:41:24.982156 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9866 12:41:24.985547 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9867 12:41:24.989184 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9868 12:41:24.995729 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9869 12:41:24.998991 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9870 12:41:25.005526 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9871 12:41:25.009166 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9872 12:41:25.012475 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9873 12:41:25.018916 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9874 12:41:25.022048 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9875 12:41:25.028399 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9876 12:41:25.031660 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9877 12:41:25.038507 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9878 12:41:25.041650 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9879 12:41:25.045053 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9880 12:41:25.051663 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9881 12:41:25.054925 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9882 12:41:25.061551 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9883 12:41:25.064884 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9884 12:41:25.068202 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9885 12:41:25.074615 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9886 12:41:25.077622 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9887 12:41:25.084366 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9888 12:41:25.087998 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9889 12:41:25.094667 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9890 12:41:25.098034 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9891 12:41:25.101255 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9892 12:41:25.108097 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9893 12:41:25.111224 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9894 12:41:25.117845 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9895 12:41:25.121255 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9896 12:41:25.127530 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9897 12:41:25.131065 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9898 12:41:25.137281 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9899 12:41:25.140593 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9900 12:41:25.144197 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9901 12:41:25.150816 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9902 12:41:25.153920 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9903 12:41:25.160951 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9904 12:41:25.163933 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9905 12:41:25.170542 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9906 12:41:25.173852 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9907 12:41:25.177387 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9908 12:41:25.183859 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9909 12:41:25.187016 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9910 12:41:25.193659 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9911 12:41:25.197144 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9912 12:41:25.204015 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9913 12:41:25.207516 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9914 12:41:25.213779 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9915 12:41:25.217093 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9916 12:41:25.220811 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9917 12:41:25.226548 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9918 12:41:25.229634 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9919 12:41:25.236888 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9920 12:41:25.239655 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9921 12:41:25.246740 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9922 12:41:25.249567 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9923 12:41:25.252850 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9924 12:41:25.259533 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9925 12:41:25.263461 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9926 12:41:25.269779 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9927 12:41:25.273121 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9928 12:41:25.279571 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9929 12:41:25.282897 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9930 12:41:25.289276 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9931 12:41:25.292563 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9932 12:41:25.296245 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9933 12:41:25.302952 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9934 12:41:25.306164 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9935 12:41:25.312969 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9936 12:41:25.316202 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9937 12:41:25.322550 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9938 12:41:25.325563 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9939 12:41:25.328884 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9940 12:41:25.335929 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9941 12:41:25.338916 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9942 12:41:25.345394 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9943 12:41:25.348677 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9944 12:41:25.355936 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9945 12:41:25.358563 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9946 12:41:25.365353 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9947 12:41:25.368588 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9948 12:41:25.375621 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9949 12:41:25.378775 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9950 12:41:25.385069 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9951 12:41:25.388753 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9952 12:41:25.395052 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9953 12:41:25.398650 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9954 12:41:25.405244 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9955 12:41:25.408473 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9956 12:41:25.415199 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9957 12:41:25.418296 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9958 12:41:25.424768 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9959 12:41:25.427835 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9960 12:41:25.434658 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9961 12:41:25.437709 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9962 12:41:25.444201 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9963 12:41:25.447872 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9964 12:41:25.454157 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9965 12:41:25.457631 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9966 12:41:25.464066 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9967 12:41:25.467563 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9968 12:41:25.473986 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9969 12:41:25.476991 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9970 12:41:25.483802 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9971 12:41:25.487375 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9972 12:41:25.490275 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9973 12:41:25.493774 INFO: [APUAPC] vio 0
9974 12:41:25.500773 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9975 12:41:25.503768 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9976 12:41:25.507483 INFO: [APUAPC] D0_APC_0: 0x400510
9977 12:41:25.510698 INFO: [APUAPC] D0_APC_1: 0x0
9978 12:41:25.513783 INFO: [APUAPC] D0_APC_2: 0x1540
9979 12:41:25.517617 INFO: [APUAPC] D0_APC_3: 0x0
9980 12:41:25.520713 INFO: [APUAPC] D1_APC_0: 0xffffffff
9981 12:41:25.523892 INFO: [APUAPC] D1_APC_1: 0xffffffff
9982 12:41:25.527302 INFO: [APUAPC] D1_APC_2: 0x3fffff
9983 12:41:25.530515 INFO: [APUAPC] D1_APC_3: 0x0
9984 12:41:25.533932 INFO: [APUAPC] D2_APC_0: 0xffffffff
9985 12:41:25.537806 INFO: [APUAPC] D2_APC_1: 0xffffffff
9986 12:41:25.540564 INFO: [APUAPC] D2_APC_2: 0x3fffff
9987 12:41:25.543471 INFO: [APUAPC] D2_APC_3: 0x0
9988 12:41:25.547324 INFO: [APUAPC] D3_APC_0: 0xffffffff
9989 12:41:25.549828 INFO: [APUAPC] D3_APC_1: 0xffffffff
9990 12:41:25.553636 INFO: [APUAPC] D3_APC_2: 0x3fffff
9991 12:41:25.557219 INFO: [APUAPC] D3_APC_3: 0x0
9992 12:41:25.560026 INFO: [APUAPC] D4_APC_0: 0xffffffff
9993 12:41:25.562983 INFO: [APUAPC] D4_APC_1: 0xffffffff
9994 12:41:25.566477 INFO: [APUAPC] D4_APC_2: 0x3fffff
9995 12:41:25.567262 INFO: [APUAPC] D4_APC_3: 0x0
9996 12:41:25.573345 INFO: [APUAPC] D5_APC_0: 0xffffffff
9997 12:41:25.576527 INFO: [APUAPC] D5_APC_1: 0xffffffff
9998 12:41:25.579802 INFO: [APUAPC] D5_APC_2: 0x3fffff
9999 12:41:25.580397 INFO: [APUAPC] D5_APC_3: 0x0
10000 12:41:25.583262 INFO: [APUAPC] D6_APC_0: 0xffffffff
10001 12:41:25.589510 INFO: [APUAPC] D6_APC_1: 0xffffffff
10002 12:41:25.590066 INFO: [APUAPC] D6_APC_2: 0x3fffff
10003 12:41:25.593068 INFO: [APUAPC] D6_APC_3: 0x0
10004 12:41:25.596145 INFO: [APUAPC] D7_APC_0: 0xffffffff
10005 12:41:25.599588 INFO: [APUAPC] D7_APC_1: 0xffffffff
10006 12:41:25.602953 INFO: [APUAPC] D7_APC_2: 0x3fffff
10007 12:41:25.606222 INFO: [APUAPC] D7_APC_3: 0x0
10008 12:41:25.609237 INFO: [APUAPC] D8_APC_0: 0xffffffff
10009 12:41:25.612470 INFO: [APUAPC] D8_APC_1: 0xffffffff
10010 12:41:25.616368 INFO: [APUAPC] D8_APC_2: 0x3fffff
10011 12:41:25.619611 INFO: [APUAPC] D8_APC_3: 0x0
10012 12:41:25.622898 INFO: [APUAPC] D9_APC_0: 0xffffffff
10013 12:41:25.625975 INFO: [APUAPC] D9_APC_1: 0xffffffff
10014 12:41:25.629274 INFO: [APUAPC] D9_APC_2: 0x3fffff
10015 12:41:25.632774 INFO: [APUAPC] D9_APC_3: 0x0
10016 12:41:25.636530 INFO: [APUAPC] D10_APC_0: 0xffffffff
10017 12:41:25.639406 INFO: [APUAPC] D10_APC_1: 0xffffffff
10018 12:41:25.642924 INFO: [APUAPC] D10_APC_2: 0x3fffff
10019 12:41:25.646195 INFO: [APUAPC] D10_APC_3: 0x0
10020 12:41:25.649192 INFO: [APUAPC] D11_APC_0: 0xffffffff
10021 12:41:25.652186 INFO: [APUAPC] D11_APC_1: 0xffffffff
10022 12:41:25.655861 INFO: [APUAPC] D11_APC_2: 0x3fffff
10023 12:41:25.659237 INFO: [APUAPC] D11_APC_3: 0x0
10024 12:41:25.662414 INFO: [APUAPC] D12_APC_0: 0xffffffff
10025 12:41:25.665881 INFO: [APUAPC] D12_APC_1: 0xffffffff
10026 12:41:25.669347 INFO: [APUAPC] D12_APC_2: 0x3fffff
10027 12:41:25.672263 INFO: [APUAPC] D12_APC_3: 0x0
10028 12:41:25.675905 INFO: [APUAPC] D13_APC_0: 0xffffffff
10029 12:41:25.678882 INFO: [APUAPC] D13_APC_1: 0xffffffff
10030 12:41:25.682491 INFO: [APUAPC] D13_APC_2: 0x3fffff
10031 12:41:25.685447 INFO: [APUAPC] D13_APC_3: 0x0
10032 12:41:25.688762 INFO: [APUAPC] D14_APC_0: 0xffffffff
10033 12:41:25.695333 INFO: [APUAPC] D14_APC_1: 0xffffffff
10034 12:41:25.699147 INFO: [APUAPC] D14_APC_2: 0x3fffff
10035 12:41:25.699719 INFO: [APUAPC] D14_APC_3: 0x0
10036 12:41:25.705198 INFO: [APUAPC] D15_APC_0: 0xffffffff
10037 12:41:25.708584 INFO: [APUAPC] D15_APC_1: 0xffffffff
10038 12:41:25.711848 INFO: [APUAPC] D15_APC_2: 0x3fffff
10039 12:41:25.712449 INFO: [APUAPC] D15_APC_3: 0x0
10040 12:41:25.714832 INFO: [APUAPC] APC_CON: 0x4
10041 12:41:25.718424 INFO: [NOCDAPC] D0_APC_0: 0x0
10042 12:41:25.721699 INFO: [NOCDAPC] D0_APC_1: 0x0
10043 12:41:25.725128 INFO: [NOCDAPC] D1_APC_0: 0x0
10044 12:41:25.727976 INFO: [NOCDAPC] D1_APC_1: 0xfff
10045 12:41:25.731465 INFO: [NOCDAPC] D2_APC_0: 0x0
10046 12:41:25.734941 INFO: [NOCDAPC] D2_APC_1: 0xfff
10047 12:41:25.738244 INFO: [NOCDAPC] D3_APC_0: 0x0
10048 12:41:25.741551 INFO: [NOCDAPC] D3_APC_1: 0xfff
10049 12:41:25.742120 INFO: [NOCDAPC] D4_APC_0: 0x0
10050 12:41:25.744952 INFO: [NOCDAPC] D4_APC_1: 0xfff
10051 12:41:25.748110 INFO: [NOCDAPC] D5_APC_0: 0x0
10052 12:41:25.751857 INFO: [NOCDAPC] D5_APC_1: 0xfff
10053 12:41:25.754862 INFO: [NOCDAPC] D6_APC_0: 0x0
10054 12:41:25.757957 INFO: [NOCDAPC] D6_APC_1: 0xfff
10055 12:41:25.761292 INFO: [NOCDAPC] D7_APC_0: 0x0
10056 12:41:25.764432 INFO: [NOCDAPC] D7_APC_1: 0xfff
10057 12:41:25.768227 INFO: [NOCDAPC] D8_APC_0: 0x0
10058 12:41:25.771419 INFO: [NOCDAPC] D8_APC_1: 0xfff
10059 12:41:25.774722 INFO: [NOCDAPC] D9_APC_0: 0x0
10060 12:41:25.778107 INFO: [NOCDAPC] D9_APC_1: 0xfff
10061 12:41:25.778654 INFO: [NOCDAPC] D10_APC_0: 0x0
10062 12:41:25.781275 INFO: [NOCDAPC] D10_APC_1: 0xfff
10063 12:41:25.784630 INFO: [NOCDAPC] D11_APC_0: 0x0
10064 12:41:25.787586 INFO: [NOCDAPC] D11_APC_1: 0xfff
10065 12:41:25.791138 INFO: [NOCDAPC] D12_APC_0: 0x0
10066 12:41:25.794591 INFO: [NOCDAPC] D12_APC_1: 0xfff
10067 12:41:25.797864 INFO: [NOCDAPC] D13_APC_0: 0x0
10068 12:41:25.800958 INFO: [NOCDAPC] D13_APC_1: 0xfff
10069 12:41:25.804325 INFO: [NOCDAPC] D14_APC_0: 0x0
10070 12:41:25.807875 INFO: [NOCDAPC] D14_APC_1: 0xfff
10071 12:41:25.811046 INFO: [NOCDAPC] D15_APC_0: 0x0
10072 12:41:25.814348 INFO: [NOCDAPC] D15_APC_1: 0xfff
10073 12:41:25.817690 INFO: [NOCDAPC] APC_CON: 0x4
10074 12:41:25.820884 INFO: [APUAPC] set_apusys_apc done
10075 12:41:25.823979 INFO: [DEVAPC] devapc_init done
10076 12:41:25.827507 INFO: GICv3 without legacy support detected.
10077 12:41:25.830752 INFO: ARM GICv3 driver initialized in EL3
10078 12:41:25.834087 INFO: Maximum SPI INTID supported: 639
10079 12:41:25.837306 INFO: BL31: Initializing runtime services
10080 12:41:25.844083 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10081 12:41:25.847538 INFO: SPM: enable CPC mode
10082 12:41:25.853870 INFO: mcdi ready for mcusys-off-idle and system suspend
10083 12:41:25.857861 INFO: BL31: Preparing for EL3 exit to normal world
10084 12:41:25.860292 INFO: Entry point address = 0x80000000
10085 12:41:25.863699 INFO: SPSR = 0x8
10086 12:41:25.868718
10087 12:41:25.869327
10088 12:41:25.869712
10089 12:41:25.871451 Starting depthcharge on Spherion...
10090 12:41:25.871926
10091 12:41:25.872299 Wipe memory regions:
10092 12:41:25.872654
10093 12:41:25.875202 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10094 12:41:25.875777 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10095 12:41:25.876240 Setting prompt string to ['asurada:']
10096 12:41:25.876662 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10097 12:41:25.877351 [0x00000040000000, 0x00000054600000)
10098 12:41:25.997530
10099 12:41:25.998101 [0x00000054660000, 0x00000080000000)
10100 12:41:26.258015
10101 12:41:26.258606 [0x000000821a7280, 0x000000ffe64000)
10102 12:41:27.003303
10103 12:41:27.003888 [0x00000100000000, 0x00000240000000)
10104 12:41:28.893244
10105 12:41:28.896048 Initializing XHCI USB controller at 0x11200000.
10106 12:41:29.934193
10107 12:41:29.937556 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10108 12:41:29.938153
10109 12:41:29.938547
10110 12:41:29.938897
10111 12:41:29.939704 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10113 12:41:30.041015 asurada: tftpboot 192.168.201.1 10724840/tftp-deploy-os1kguat/kernel/image.itb 10724840/tftp-deploy-os1kguat/kernel/cmdline
10114 12:41:30.041674 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10115 12:41:30.042137 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10116 12:41:30.046662 tftpboot 192.168.201.1 10724840/tftp-deploy-os1kguat/kernel/image.itp-deploy-os1kguat/kernel/cmdline
10117 12:41:30.047244
10118 12:41:30.047624 Waiting for link
10119 12:41:30.206881
10120 12:41:30.207054 R8152: Initializing
10121 12:41:30.207122
10122 12:41:30.210404 Version 9 (ocp_data = 6010)
10123 12:41:30.210488
10124 12:41:30.213237 R8152: Done initializing
10125 12:41:30.213320
10126 12:41:30.213387 Adding net device
10127 12:41:32.155185
10128 12:41:32.155451 done.
10129 12:41:32.155599
10130 12:41:32.155736 MAC: 00:e0:4c:72:2d:d6
10131 12:41:32.155866
10132 12:41:32.158308 Sending DHCP discover... done.
10133 12:41:32.158493
10134 12:41:32.162548 Waiting for reply... done.
10135 12:41:32.162735
10136 12:41:32.164916 Sending DHCP request... done.
10137 12:41:32.165121
10138 12:41:32.168543 Waiting for reply... done.
10139 12:41:32.168726
10140 12:41:32.168872 My ip is 192.168.201.21
10141 12:41:32.169023
10142 12:41:32.171729 The DHCP server ip is 192.168.201.1
10143 12:41:32.171913
10144 12:41:32.175566 TFTP server IP predefined by user: 192.168.201.1
10145 12:41:32.178305
10146 12:41:32.181780 Bootfile predefined by user: 10724840/tftp-deploy-os1kguat/kernel/image.itb
10147 12:41:32.185100
10148 12:41:32.185366 Sending tftp read request... done.
10149 12:41:32.185524
10150 12:41:32.191907 Waiting for the transfer...
10151 12:41:32.192256
10152 12:41:32.455755 00000000 ################################################################
10153 12:41:32.455907
10154 12:41:32.705293 00080000 ################################################################
10155 12:41:32.705444
10156 12:41:32.952746 00100000 ################################################################
10157 12:41:32.952896
10158 12:41:33.198817 00180000 ################################################################
10159 12:41:33.198990
10160 12:41:33.445087 00200000 ################################################################
10161 12:41:33.445239
10162 12:41:33.697569 00280000 ################################################################
10163 12:41:33.697728
10164 12:41:33.944228 00300000 ################################################################
10165 12:41:33.944373
10166 12:41:34.202314 00380000 ################################################################
10167 12:41:34.202467
10168 12:41:34.464031 00400000 ################################################################
10169 12:41:34.464182
10170 12:41:34.710100 00480000 ################################################################
10171 12:41:34.710249
10172 12:41:34.983197 00500000 ################################################################
10173 12:41:34.983348
10174 12:41:35.245544 00580000 ################################################################
10175 12:41:35.245705
10176 12:41:35.525248 00600000 ################################################################
10177 12:41:35.525401
10178 12:41:35.797985 00680000 ################################################################
10179 12:41:35.798138
10180 12:41:36.059079 00700000 ################################################################
10181 12:41:36.059215
10182 12:41:36.326277 00780000 ################################################################
10183 12:41:36.326414
10184 12:41:36.595828 00800000 ################################################################
10185 12:41:36.595998
10186 12:41:36.879851 00880000 ################################################################
10187 12:41:36.880002
10188 12:41:37.129183 00900000 ################################################################
10189 12:41:37.129324
10190 12:41:37.389798 00980000 ################################################################
10191 12:41:37.389940
10192 12:41:37.651283 00a00000 ################################################################
10193 12:41:37.651431
10194 12:41:37.900667 00a80000 ################################################################
10195 12:41:37.900814
10196 12:41:38.174250 00b00000 ################################################################
10197 12:41:38.174389
10198 12:41:38.467953 00b80000 ################################################################
10199 12:41:38.468103
10200 12:41:38.765498 00c00000 ################################################################
10201 12:41:38.765643
10202 12:41:39.062938 00c80000 ################################################################
10203 12:41:39.063081
10204 12:41:39.323125 00d00000 ################################################################
10205 12:41:39.323267
10206 12:41:39.584552 00d80000 ################################################################
10207 12:41:39.584698
10208 12:41:39.861444 00e00000 ################################################################
10209 12:41:39.861583
10210 12:41:40.154885 00e80000 ################################################################
10211 12:41:40.155024
10212 12:41:40.448655 00f00000 ################################################################
10213 12:41:40.448798
10214 12:41:40.744638 00f80000 ################################################################
10215 12:41:40.744782
10216 12:41:41.041040 01000000 ################################################################
10217 12:41:41.041182
10218 12:41:41.336914 01080000 ################################################################
10219 12:41:41.337091
10220 12:41:41.628748 01100000 ################################################################
10221 12:41:41.628889
10222 12:41:41.919196 01180000 ################################################################
10223 12:41:41.919339
10224 12:41:42.215298 01200000 ################################################################
10225 12:41:42.215438
10226 12:41:42.468380 01280000 ################################################################
10227 12:41:42.468518
10228 12:41:42.717683 01300000 ################################################################
10229 12:41:42.717855
10230 12:41:43.011821 01380000 ################################################################
10231 12:41:43.011965
10232 12:41:43.305230 01400000 ################################################################
10233 12:41:43.305378
10234 12:41:43.560083 01480000 ################################################################
10235 12:41:43.560229
10236 12:41:43.812142 01500000 ################################################################
10237 12:41:43.812287
10238 12:41:44.078585 01580000 ################################################################
10239 12:41:44.078734
10240 12:41:44.355599 01600000 ################################################################
10241 12:41:44.355752
10242 12:41:44.627564 01680000 ################################################################
10243 12:41:44.627716
10244 12:41:44.873002 01700000 ################################################################
10245 12:41:44.873138
10246 12:41:45.134334 01780000 ################################################################
10247 12:41:45.134480
10248 12:41:45.430265 01800000 ################################################################
10249 12:41:45.430414
10250 12:41:45.720161 01880000 ################################################################
10251 12:41:45.720308
10252 12:41:46.003322 01900000 ################################################################
10253 12:41:46.003472
10254 12:41:46.299052 01980000 ################################################################
10255 12:41:46.299195
10256 12:41:46.578324 01a00000 ################################################################
10257 12:41:46.578468
10258 12:41:46.768319 01a80000 ########################################### done.
10259 12:41:46.768452
10260 12:41:46.771791 The bootfile was 28135150 bytes long.
10261 12:41:46.771876
10262 12:41:46.774844 Sending tftp read request... done.
10263 12:41:46.774928
10264 12:41:46.778032 Waiting for the transfer...
10265 12:41:46.778115
10266 12:41:46.778181 00000000 # done.
10267 12:41:46.778246
10268 12:41:46.787895 Command line loaded dynamically from TFTP file: 10724840/tftp-deploy-os1kguat/kernel/cmdline
10269 12:41:46.787980
10270 12:41:46.807743 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10724840/extract-nfsrootfs-0nvap_bc,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10271 12:41:46.807834
10272 12:41:46.807900 Loading FIT.
10273 12:41:46.807961
10274 12:41:46.811163 Image ramdisk-1 has 17643815 bytes.
10275 12:41:46.811246
10276 12:41:46.814699 Image fdt-1 has 46924 bytes.
10277 12:41:46.814782
10278 12:41:46.817772 Image kernel-1 has 10442380 bytes.
10279 12:41:46.817855
10280 12:41:46.827746 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10281 12:41:46.827830
10282 12:41:46.844370 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10283 12:41:46.844459
10284 12:41:46.847531 Choosing best match conf-1 for compat google,spherion-rev2.
10285 12:41:46.851120
10286 12:41:46.854448 Connected to device vid:did:rid of 1ae0:0028:00
10287 12:41:46.864648
10288 12:41:46.867814 tpm_get_response: command 0x17b, return code 0x0
10289 12:41:46.867898
10290 12:41:46.871485 ec_init: CrosEC protocol v3 supported (256, 248)
10291 12:41:46.875659
10292 12:41:46.878923 tpm_cleanup: add release locality here.
10293 12:41:46.879006
10294 12:41:46.879072 Shutting down all USB controllers.
10295 12:41:46.881889
10296 12:41:46.881972 Removing current net device
10297 12:41:46.882038
10298 12:41:46.888585 Exiting depthcharge with code 4 at timestamp: 50325895
10299 12:41:46.888669
10300 12:41:46.892131 LZMA decompressing kernel-1 to 0x821a6718
10301 12:41:46.892212
10302 12:41:46.895523 LZMA decompressing kernel-1 to 0x40000000
10303 12:41:48.206099
10304 12:41:48.206251 jumping to kernel
10305 12:41:48.206651 end: 2.2.4 bootloader-commands (duration 00:00:22) [common]
10306 12:41:48.206755 start: 2.2.5 auto-login-action (timeout 00:04:03) [common]
10307 12:41:48.206831 Setting prompt string to ['Linux version [0-9]']
10308 12:41:48.206904 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10309 12:41:48.206974 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10310 12:41:48.287610
10311 12:41:48.291232 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10312 12:41:48.294258 start: 2.2.5.1 login-action (timeout 00:04:03) [common]
10313 12:41:48.294351 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10314 12:41:48.294436 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10315 12:41:48.294513 Using line separator: #'\n'#
10316 12:41:48.294574 No login prompt set.
10317 12:41:48.294638 Parsing kernel messages
10318 12:41:48.294693 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10319 12:41:48.294795 [login-action] Waiting for messages, (timeout 00:04:03)
10320 12:41:48.314838 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j35827-arm64-gcc-10-defconfig-arm64-chromebook-fwl9s) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jun 14 12:30:40 UTC 2023
10321 12:41:48.317766 [ 0.000000] random: crng init done
10322 12:41:48.321232 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10323 12:41:48.323932 [ 0.000000] efi: UEFI not found.
10324 12:41:48.333955 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10325 12:41:48.341205 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10326 12:41:48.350645 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10327 12:41:48.360249 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10328 12:41:48.366859 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10329 12:41:48.370840 [ 0.000000] printk: bootconsole [mtk8250] enabled
10330 12:41:48.378961 [ 0.000000] NUMA: No NUMA configuration found
10331 12:41:48.385713 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10332 12:41:48.392115 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10333 12:41:48.392201 [ 0.000000] Zone ranges:
10334 12:41:48.399272 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10335 12:41:48.402281 [ 0.000000] DMA32 empty
10336 12:41:48.408877 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10337 12:41:48.411983 [ 0.000000] Movable zone start for each node
10338 12:41:48.415862 [ 0.000000] Early memory node ranges
10339 12:41:48.421892 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10340 12:41:48.428456 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10341 12:41:48.435212 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10342 12:41:48.441619 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10343 12:41:48.448459 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10344 12:41:48.454797 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10345 12:41:48.511351 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10346 12:41:48.518155 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10347 12:41:48.524610 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10348 12:41:48.528161 [ 0.000000] psci: probing for conduit method from DT.
10349 12:41:48.534985 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10350 12:41:48.538114 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10351 12:41:48.544498 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10352 12:41:48.548225 [ 0.000000] psci: SMC Calling Convention v1.2
10353 12:41:48.554653 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10354 12:41:48.557965 [ 0.000000] Detected VIPT I-cache on CPU0
10355 12:41:48.564501 [ 0.000000] CPU features: detected: GIC system register CPU interface
10356 12:41:48.570982 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10357 12:41:48.578017 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10358 12:41:48.584249 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10359 12:41:48.590845 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10360 12:41:48.601275 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10361 12:41:48.604199 [ 0.000000] alternatives: applying boot alternatives
10362 12:41:48.610902 [ 0.000000] Fallback order for Node 0: 0
10363 12:41:48.617769 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10364 12:41:48.620698 [ 0.000000] Policy zone: Normal
10365 12:41:48.640639 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10724840/extract-nfsrootfs-0nvap_bc,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10366 12:41:48.650828 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10367 12:41:48.661256 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10368 12:41:48.671525 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10369 12:41:48.678073 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10370 12:41:48.681183 <6>[ 0.000000] software IO TLB: area num 8.
10371 12:41:48.737451 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10372 12:41:48.886752 <6>[ 0.000000] Memory: 7953932K/8385536K available (17984K kernel code, 4098K rwdata, 15868K rodata, 8384K init, 615K bss, 398836K reserved, 32768K cma-reserved)
10373 12:41:48.893314 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10374 12:41:48.899872 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10375 12:41:48.903209 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10376 12:41:48.909923 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10377 12:41:48.916758 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10378 12:41:48.920240 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10379 12:41:48.929936 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10380 12:41:48.936776 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10381 12:41:48.943438 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10382 12:41:48.949638 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10383 12:41:48.953252 <6>[ 0.000000] GICv3: 608 SPIs implemented
10384 12:41:48.956375 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10385 12:41:48.963407 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10386 12:41:48.966403 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10387 12:41:48.973245 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10388 12:41:48.986118 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10389 12:41:48.999635 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10390 12:41:49.006129 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10391 12:41:49.013830 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10392 12:41:49.027160 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10393 12:41:49.033344 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10394 12:41:49.040461 <6>[ 0.009181] Console: colour dummy device 80x25
10395 12:41:49.049930 <6>[ 0.013907] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10396 12:41:49.056824 <6>[ 0.024350] pid_max: default: 32768 minimum: 301
10397 12:41:49.060139 <6>[ 0.029247] LSM: Security Framework initializing
10398 12:41:49.066906 <6>[ 0.034187] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10399 12:41:49.076406 <6>[ 0.041999] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10400 12:41:49.086586 <6>[ 0.051425] cblist_init_generic: Setting adjustable number of callback queues.
10401 12:41:49.089460 <6>[ 0.058924] cblist_init_generic: Setting shift to 3 and lim to 1.
10402 12:41:49.095924 <6>[ 0.065263] cblist_init_generic: Setting shift to 3 and lim to 1.
10403 12:41:49.102825 <6>[ 0.071706] rcu: Hierarchical SRCU implementation.
10404 12:41:49.109237 <6>[ 0.076720] rcu: Max phase no-delay instances is 1000.
10405 12:41:49.116084 <6>[ 0.083738] EFI services will not be available.
10406 12:41:49.119232 <6>[ 0.088735] smp: Bringing up secondary CPUs ...
10407 12:41:49.127114 <6>[ 0.093788] Detected VIPT I-cache on CPU1
10408 12:41:49.133672 <6>[ 0.093860] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10409 12:41:49.140251 <6>[ 0.093892] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10410 12:41:49.143771 <6>[ 0.094233] Detected VIPT I-cache on CPU2
10411 12:41:49.150533 <6>[ 0.094286] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10412 12:41:49.160251 <6>[ 0.094304] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10413 12:41:49.163656 <6>[ 0.094564] Detected VIPT I-cache on CPU3
10414 12:41:49.170167 <6>[ 0.094612] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10415 12:41:49.176731 <6>[ 0.094627] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10416 12:41:49.180168 <6>[ 0.094934] CPU features: detected: Spectre-v4
10417 12:41:49.186920 <6>[ 0.094942] CPU features: detected: Spectre-BHB
10418 12:41:49.190258 <6>[ 0.094949] Detected PIPT I-cache on CPU4
10419 12:41:49.196564 <6>[ 0.095006] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10420 12:41:49.203619 <6>[ 0.095023] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10421 12:41:49.209770 <6>[ 0.095316] Detected PIPT I-cache on CPU5
10422 12:41:49.216799 <6>[ 0.095379] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10423 12:41:49.223046 <6>[ 0.095395] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10424 12:41:49.226335 <6>[ 0.095677] Detected PIPT I-cache on CPU6
10425 12:41:49.233165 <6>[ 0.095741] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10426 12:41:49.240109 <6>[ 0.095757] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10427 12:41:49.246566 <6>[ 0.096058] Detected PIPT I-cache on CPU7
10428 12:41:49.252681 <6>[ 0.096116] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10429 12:41:49.259775 <6>[ 0.096132] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10430 12:41:49.262623 <6>[ 0.096177] smp: Brought up 1 node, 8 CPUs
10431 12:41:49.269866 <6>[ 0.237451] SMP: Total of 8 processors activated.
10432 12:41:49.272835 <6>[ 0.242372] CPU features: detected: 32-bit EL0 Support
10433 12:41:49.283042 <6>[ 0.247735] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10434 12:41:49.288901 <6>[ 0.256535] CPU features: detected: Common not Private translations
10435 12:41:49.295808 <6>[ 0.263011] CPU features: detected: CRC32 instructions
10436 12:41:49.299092 <6>[ 0.268396] CPU features: detected: RCpc load-acquire (LDAPR)
10437 12:41:49.305981 <6>[ 0.274392] CPU features: detected: LSE atomic instructions
10438 12:41:49.312571 <6>[ 0.280209] CPU features: detected: Privileged Access Never
10439 12:41:49.318859 <6>[ 0.286025] CPU features: detected: RAS Extension Support
10440 12:41:49.325189 <6>[ 0.291634] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10441 12:41:49.328778 <6>[ 0.298854] CPU: All CPU(s) started at EL2
10442 12:41:49.335629 <6>[ 0.303170] alternatives: applying system-wide alternatives
10443 12:41:49.345023 <6>[ 0.313893] devtmpfs: initialized
10444 12:41:49.360478 <6>[ 0.322694] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10445 12:41:49.367128 <6>[ 0.332656] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10446 12:41:49.373123 <6>[ 0.340847] pinctrl core: initialized pinctrl subsystem
10447 12:41:49.376435 <6>[ 0.347505] DMI not present or invalid.
10448 12:41:49.383062 <6>[ 0.351911] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10449 12:41:49.393190 <6>[ 0.358782] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10450 12:41:49.399465 <6>[ 0.366368] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10451 12:41:49.409586 <6>[ 0.374587] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10452 12:41:49.416182 <6>[ 0.382829] audit: initializing netlink subsys (disabled)
10453 12:41:49.422643 <5>[ 0.388521] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10454 12:41:49.429104 <6>[ 0.389215] thermal_sys: Registered thermal governor 'step_wise'
10455 12:41:49.435860 <6>[ 0.396487] thermal_sys: Registered thermal governor 'power_allocator'
10456 12:41:49.439378 <6>[ 0.402743] cpuidle: using governor menu
10457 12:41:49.445906 <6>[ 0.413704] NET: Registered PF_QIPCRTR protocol family
10458 12:41:49.452570 <6>[ 0.419187] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10459 12:41:49.459170 <6>[ 0.426291] ASID allocator initialised with 32768 entries
10460 12:41:49.462109 <6>[ 0.432854] Serial: AMBA PL011 UART driver
10461 12:41:49.472636 <4>[ 0.441521] Trying to register duplicate clock ID: 134
10462 12:41:49.526170 <6>[ 0.498587] KASLR enabled
10463 12:41:49.540393 <6>[ 0.506244] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10464 12:41:49.547140 <6>[ 0.513257] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10465 12:41:49.553891 <6>[ 0.519744] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10466 12:41:49.560552 <6>[ 0.526748] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10467 12:41:49.566896 <6>[ 0.533234] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10468 12:41:49.573513 <6>[ 0.540238] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10469 12:41:49.580450 <6>[ 0.546725] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10470 12:41:49.586428 <6>[ 0.553729] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10471 12:41:49.590014 <6>[ 0.561200] ACPI: Interpreter disabled.
10472 12:41:49.598501 <6>[ 0.567607] iommu: Default domain type: Translated
10473 12:41:49.605263 <6>[ 0.572717] iommu: DMA domain TLB invalidation policy: strict mode
10474 12:41:49.608549 <5>[ 0.579381] SCSI subsystem initialized
10475 12:41:49.615359 <6>[ 0.583614] usbcore: registered new interface driver usbfs
10476 12:41:49.622149 <6>[ 0.589344] usbcore: registered new interface driver hub
10477 12:41:49.624849 <6>[ 0.594897] usbcore: registered new device driver usb
10478 12:41:49.631999 <6>[ 0.600996] pps_core: LinuxPPS API ver. 1 registered
10479 12:41:49.641711 <6>[ 0.606187] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10480 12:41:49.645385 <6>[ 0.615529] PTP clock support registered
10481 12:41:49.648495 <6>[ 0.619767] EDAC MC: Ver: 3.0.0
10482 12:41:49.655998 <6>[ 0.624955] FPGA manager framework
10483 12:41:49.662786 <6>[ 0.628629] Advanced Linux Sound Architecture Driver Initialized.
10484 12:41:49.665765 <6>[ 0.635396] vgaarb: loaded
10485 12:41:49.672314 <6>[ 0.638558] clocksource: Switched to clocksource arch_sys_counter
10486 12:41:49.675527 <5>[ 0.645004] VFS: Disk quotas dquot_6.6.0
10487 12:41:49.682378 <6>[ 0.649187] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10488 12:41:49.685228 <6>[ 0.656375] pnp: PnP ACPI: disabled
10489 12:41:49.693991 <6>[ 0.663001] NET: Registered PF_INET protocol family
10490 12:41:49.703981 <6>[ 0.668584] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10491 12:41:49.715135 <6>[ 0.680883] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10492 12:41:49.725393 <6>[ 0.689698] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10493 12:41:49.732068 <6>[ 0.697667] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10494 12:41:49.741852 <6>[ 0.706366] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10495 12:41:49.748103 <6>[ 0.716108] TCP: Hash tables configured (established 65536 bind 65536)
10496 12:41:49.754804 <6>[ 0.722965] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10497 12:41:49.764718 <6>[ 0.730164] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10498 12:41:49.771103 <6>[ 0.737864] NET: Registered PF_UNIX/PF_LOCAL protocol family
10499 12:41:49.777601 <6>[ 0.744027] RPC: Registered named UNIX socket transport module.
10500 12:41:49.781343 <6>[ 0.750181] RPC: Registered udp transport module.
10501 12:41:49.784575 <6>[ 0.755116] RPC: Registered tcp transport module.
10502 12:41:49.794135 <6>[ 0.760049] RPC: Registered tcp NFSv4.1 backchannel transport module.
10503 12:41:49.797497 <6>[ 0.766715] PCI: CLS 0 bytes, default 64
10504 12:41:49.800482 <6>[ 0.771094] Unpacking initramfs...
10505 12:41:49.810517 <6>[ 0.774904] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10506 12:41:49.817340 <6>[ 0.783513] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10507 12:41:49.823867 <6>[ 0.792336] kvm [1]: IPA Size Limit: 40 bits
10508 12:41:49.827234 <6>[ 0.796861] kvm [1]: GICv3: no GICV resource entry
10509 12:41:49.833892 <6>[ 0.801882] kvm [1]: disabling GICv2 emulation
10510 12:41:49.837233 <6>[ 0.806566] kvm [1]: GIC system register CPU interface enabled
10511 12:41:49.843770 <6>[ 0.812732] kvm [1]: vgic interrupt IRQ18
10512 12:41:49.846769 <6>[ 0.817085] kvm [1]: VHE mode initialized successfully
10513 12:41:49.854273 <5>[ 0.823554] Initialise system trusted keyrings
10514 12:41:49.860738 <6>[ 0.828351] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10515 12:41:49.869366 <6>[ 0.838348] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10516 12:41:49.875914 <5>[ 0.844726] NFS: Registering the id_resolver key type
10517 12:41:49.879080 <5>[ 0.850029] Key type id_resolver registered
10518 12:41:49.885882 <5>[ 0.854445] Key type id_legacy registered
10519 12:41:49.892595 <6>[ 0.858727] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10520 12:41:49.898843 <6>[ 0.865649] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10521 12:41:49.905154 <6>[ 0.873350] 9p: Installing v9fs 9p2000 file system support
10522 12:41:49.942340 <5>[ 0.911447] Key type asymmetric registered
10523 12:41:49.945690 <5>[ 0.915777] Asymmetric key parser 'x509' registered
10524 12:41:49.955439 <6>[ 0.920908] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10525 12:41:49.958621 <6>[ 0.928521] io scheduler mq-deadline registered
10526 12:41:49.962388 <6>[ 0.933281] io scheduler kyber registered
10527 12:41:49.980824 <6>[ 0.949961] EINJ: ACPI disabled.
10528 12:41:50.013308 <4>[ 0.975662] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10529 12:41:50.022795 <4>[ 0.986282] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10530 12:41:50.038148 <6>[ 1.007382] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10531 12:41:50.046573 <6>[ 1.015522] printk: console [ttyS0] disabled
10532 12:41:50.074229 <6>[ 1.040171] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10533 12:41:50.081174 <6>[ 1.049644] printk: console [ttyS0] enabled
10534 12:41:50.084393 <6>[ 1.049644] printk: console [ttyS0] enabled
10535 12:41:50.090971 <6>[ 1.058539] printk: bootconsole [mtk8250] disabled
10536 12:41:50.094031 <6>[ 1.058539] printk: bootconsole [mtk8250] disabled
10537 12:41:50.100961 <6>[ 1.069755] SuperH (H)SCI(F) driver initialized
10538 12:41:50.103981 <6>[ 1.075028] msm_serial: driver initialized
10539 12:41:50.118348 <6>[ 1.083954] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10540 12:41:50.127679 <6>[ 1.092501] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10541 12:41:50.134211 <6>[ 1.101041] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10542 12:41:50.144226 <6>[ 1.109671] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10543 12:41:50.154298 <6>[ 1.118378] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10544 12:41:50.160461 <6>[ 1.127097] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10545 12:41:50.170456 <6>[ 1.135638] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10546 12:41:50.177280 <6>[ 1.144444] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10547 12:41:50.187060 <6>[ 1.152987] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10548 12:41:50.199011 <6>[ 1.168326] loop: module loaded
10549 12:41:50.205412 <6>[ 1.174329] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10550 12:41:50.228155 <4>[ 1.197604] mtk-pmic-keys: Failed to locate of_node [id: -1]
10551 12:41:50.234489 <6>[ 1.204322] megasas: 07.719.03.00-rc1
10552 12:41:50.244440 <6>[ 1.213919] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10553 12:41:50.252409 <6>[ 1.221940] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10554 12:41:50.268874 <6>[ 1.238598] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10555 12:41:50.329747 <6>[ 1.292852] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10556 12:41:50.529061 <6>[ 1.498016] Freeing initrd memory: 17224K
10557 12:41:50.538945 <6>[ 1.507946] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10558 12:41:50.549660 <6>[ 1.519009] tun: Universal TUN/TAP device driver, 1.6
10559 12:41:50.553424 <6>[ 1.525064] thunder_xcv, ver 1.0
10560 12:41:50.556825 <6>[ 1.528569] thunder_bgx, ver 1.0
10561 12:41:50.559695 <6>[ 1.532061] nicpf, ver 1.0
10562 12:41:50.570273 <6>[ 1.536068] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10563 12:41:50.573691 <6>[ 1.543543] hns3: Copyright (c) 2017 Huawei Corporation.
10564 12:41:50.577023 <6>[ 1.549129] hclge is initializing
10565 12:41:50.583534 <6>[ 1.552713] e1000: Intel(R) PRO/1000 Network Driver
10566 12:41:50.590137 <6>[ 1.557842] e1000: Copyright (c) 1999-2006 Intel Corporation.
10567 12:41:50.593599 <6>[ 1.563855] e1000e: Intel(R) PRO/1000 Network Driver
10568 12:41:50.600388 <6>[ 1.569071] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10569 12:41:50.607106 <6>[ 1.575257] igb: Intel(R) Gigabit Ethernet Network Driver
10570 12:41:50.613818 <6>[ 1.580907] igb: Copyright (c) 2007-2014 Intel Corporation.
10571 12:41:50.620214 <6>[ 1.586743] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10572 12:41:50.626871 <6>[ 1.593262] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10573 12:41:50.630338 <6>[ 1.599718] sky2: driver version 1.30
10574 12:41:50.636657 <6>[ 1.604683] VFIO - User Level meta-driver version: 0.3
10575 12:41:50.643694 <6>[ 1.612896] usbcore: registered new interface driver usb-storage
10576 12:41:50.650781 <6>[ 1.619337] usbcore: registered new device driver onboard-usb-hub
10577 12:41:50.659277 <6>[ 1.628447] mt6397-rtc mt6359-rtc: registered as rtc0
10578 12:41:50.669340 <6>[ 1.633916] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-14T12:41:46 UTC (1686746506)
10579 12:41:50.672606 <6>[ 1.643473] i2c_dev: i2c /dev entries driver
10580 12:41:50.689582 <6>[ 1.655203] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10581 12:41:50.695953 <6>[ 1.665400] sdhci: Secure Digital Host Controller Interface driver
10582 12:41:50.702894 <6>[ 1.671839] sdhci: Copyright(c) Pierre Ossman
10583 12:41:50.709773 <6>[ 1.677234] Synopsys Designware Multimedia Card Interface Driver
10584 12:41:50.712701 <6>[ 1.683852] mmc0: CQHCI version 5.10
10585 12:41:50.719524 <6>[ 1.684372] sdhci-pltfm: SDHCI platform and OF driver helper
10586 12:41:50.726163 <6>[ 1.695699] ledtrig-cpu: registered to indicate activity on CPUs
10587 12:41:50.737243 <6>[ 1.703046] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10588 12:41:50.740496 <6>[ 1.710459] usbcore: registered new interface driver usbhid
10589 12:41:50.747131 <6>[ 1.716291] usbhid: USB HID core driver
10590 12:41:50.753618 <6>[ 1.720546] spi_master spi0: will run message pump with realtime priority
10591 12:41:50.798602 <6>[ 1.761297] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10592 12:41:50.818576 <6>[ 1.777645] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10593 12:41:50.822240 <6>[ 1.791233] mmc0: Command Queue Engine enabled
10594 12:41:50.829176 <6>[ 1.792891] cros-ec-spi spi0.0: Chrome EC device registered
10595 12:41:50.835649 <6>[ 1.795964] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10596 12:41:50.838990 <6>[ 1.809117] mmcblk0: mmc0:0001 DA4128 116 GiB
10597 12:41:50.853423 <6>[ 1.819411] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10598 12:41:50.860487 <6>[ 1.820808] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10599 12:41:50.866947 <6>[ 1.830842] NET: Registered PF_PACKET protocol family
10600 12:41:50.870866 <6>[ 1.836066] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10601 12:41:50.877141 <6>[ 1.840075] 9pnet: Installing 9P2000 support
10602 12:41:50.880659 <6>[ 1.845806] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10603 12:41:50.883657 <5>[ 1.849739] Key type dns_resolver registered
10604 12:41:50.890103 <6>[ 1.855566] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10605 12:41:50.896910 <6>[ 1.860060] registered taskstats version 1
10606 12:41:50.900589 <5>[ 1.870405] Loading compiled-in X.509 certificates
10607 12:41:50.936220 <4>[ 1.898995] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10608 12:41:50.946114 <4>[ 1.909678] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10609 12:41:50.956604 <3>[ 1.922441] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10610 12:41:50.968588 <6>[ 1.937867] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10611 12:41:50.975321 <6>[ 1.944686] xhci-mtk 11200000.usb: xHCI Host Controller
10612 12:41:50.982074 <6>[ 1.950193] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10613 12:41:50.992087 <6>[ 1.958055] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10614 12:41:50.998713 <6>[ 1.967486] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10615 12:41:51.005498 <6>[ 1.973686] xhci-mtk 11200000.usb: xHCI Host Controller
10616 12:41:51.011961 <6>[ 1.979183] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10617 12:41:51.018603 <6>[ 1.986841] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10618 12:41:51.025517 <6>[ 1.994754] hub 1-0:1.0: USB hub found
10619 12:41:51.028758 <6>[ 1.998780] hub 1-0:1.0: 1 port detected
10620 12:41:51.038570 <6>[ 2.003125] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10621 12:41:51.041625 <6>[ 2.011929] hub 2-0:1.0: USB hub found
10622 12:41:51.045075 <6>[ 2.015960] hub 2-0:1.0: 1 port detected
10623 12:41:51.053316 <6>[ 2.023144] mtk-msdc 11f70000.mmc: Got CD GPIO
10624 12:41:51.071534 <6>[ 2.037670] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10625 12:41:51.078269 <6>[ 2.045732] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10626 12:41:51.088440 <4>[ 2.053707] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10627 12:41:51.097972 <6>[ 2.063377] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10628 12:41:51.104879 <6>[ 2.071461] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10629 12:41:51.111936 <6>[ 2.079487] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10630 12:41:51.121864 <6>[ 2.087406] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10631 12:41:51.128568 <6>[ 2.095227] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10632 12:41:51.138506 <6>[ 2.103048] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10633 12:41:51.148133 <6>[ 2.113755] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10634 12:41:51.154754 <6>[ 2.122123] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10635 12:41:51.164854 <6>[ 2.130475] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10636 12:41:51.171636 <6>[ 2.138820] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10637 12:41:51.181651 <6>[ 2.147164] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10638 12:41:51.188520 <6>[ 2.155506] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10639 12:41:51.198093 <6>[ 2.163850] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10640 12:41:51.205146 <6>[ 2.172194] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10641 12:41:51.214634 <6>[ 2.180538] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10642 12:41:51.224776 <6>[ 2.188883] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10643 12:41:51.231364 <6>[ 2.197227] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10644 12:41:51.241348 <6>[ 2.205572] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10645 12:41:51.247614 <6>[ 2.213926] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10646 12:41:51.257878 <6>[ 2.222270] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10647 12:41:51.263939 <6>[ 2.230615] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10648 12:41:51.270912 <6>[ 2.239519] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10649 12:41:51.277408 <6>[ 2.246958] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10650 12:41:51.284815 <6>[ 2.253965] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10651 12:41:51.295005 <6>[ 2.261047] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10652 12:41:51.301426 <6>[ 2.268313] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10653 12:41:51.311779 <6>[ 2.275149] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10654 12:41:51.318101 <6>[ 2.284290] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10655 12:41:51.328243 <6>[ 2.293417] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10656 12:41:51.337835 <6>[ 2.302720] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10657 12:41:51.347500 <6>[ 2.312194] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10658 12:41:51.357748 <6>[ 2.321668] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10659 12:41:51.367430 <6>[ 2.330794] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10660 12:41:51.374137 <6>[ 2.340268] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10661 12:41:51.384042 <6>[ 2.349395] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10662 12:41:51.394318 <6>[ 2.358696] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10663 12:41:51.404311 <6>[ 2.368862] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10664 12:41:51.414870 <6>[ 2.380794] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10665 12:41:51.421258 <6>[ 2.390769] Trying to probe devices needed for running init ...
10666 12:41:51.436656 <6>[ 2.402827] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10667 12:41:51.463452 <6>[ 2.432803] hub 2-1:1.0: USB hub found
10668 12:41:51.466814 <6>[ 2.437163] hub 2-1:1.0: 3 ports detected
10669 12:41:51.588634 <6>[ 2.554806] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10670 12:41:51.741429 <6>[ 2.711160] hub 1-1:1.0: USB hub found
10671 12:41:51.744873 <6>[ 2.715567] hub 1-1:1.0: 4 ports detected
10672 12:41:51.820555 <6>[ 2.787080] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10673 12:41:52.064960 <6>[ 3.030834] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10674 12:41:52.197640 <6>[ 3.167054] hub 1-1.4:1.0: USB hub found
10675 12:41:52.201324 <6>[ 3.171733] hub 1-1.4:1.0: 2 ports detected
10676 12:41:52.496707 <6>[ 3.462829] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10677 12:41:52.688676 <6>[ 3.654829] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10678 12:42:03.692901 <6>[ 14.667380] ALSA device list:
10679 12:42:03.699265 <6>[ 14.670638] No soundcards found.
10680 12:42:03.711737 <6>[ 14.683020] Freeing unused kernel memory: 8384K
10681 12:42:03.714911 <6>[ 14.687945] Run /init as init process
10682 12:42:03.725586 Loading, please wait...
10683 12:42:03.745160 Starting version 247.3-7+deb11u2
10684 12:42:04.091044 <6>[ 15.058982] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10685 12:42:04.101845 <3>[ 15.070039] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10686 12:42:04.108683 <3>[ 15.078216] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10687 12:42:04.118330 <3>[ 15.086370] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10688 12:42:04.130634 <3>[ 15.098777] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10689 12:42:04.137528 <3>[ 15.106973] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10690 12:42:04.147679 <3>[ 15.115071] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10691 12:42:04.150973 <6>[ 15.118274] remoteproc remoteproc0: scp is available
10692 12:42:04.160856 <6>[ 15.118577] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10693 12:42:04.167169 <3>[ 15.123161] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10694 12:42:04.177284 <3>[ 15.123179] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10695 12:42:04.184081 <4>[ 15.128480] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10696 12:42:04.191026 <6>[ 15.145250] mc: Linux media interface: v0.10
10697 12:42:04.197942 <4>[ 15.148347] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10698 12:42:04.204471 <4>[ 15.148347] Fallback method does not support PEC.
10699 12:42:04.207503 <6>[ 15.152236] remoteproc remoteproc0: powering up scp
10700 12:42:04.217923 <4>[ 15.152277] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10701 12:42:04.227781 <3>[ 15.153133] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10702 12:42:04.234972 <4>[ 15.153788] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10703 12:42:04.241619 <6>[ 15.154921] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10704 12:42:04.251247 <6>[ 15.154953] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10705 12:42:04.257825 <6>[ 15.154963] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10706 12:42:04.268123 <4>[ 15.158898] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10707 12:42:04.274288 <3>[ 15.159075] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10708 12:42:04.284236 <3>[ 15.159129] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10709 12:42:04.290904 <3>[ 15.159161] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10710 12:42:04.300854 <3>[ 15.163569] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10711 12:42:04.307500 <3>[ 15.166585] remoteproc remoteproc0: request_firmware failed: -2
10712 12:42:04.314216 <3>[ 15.168306] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10713 12:42:04.320552 <3>[ 15.169581] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10714 12:42:04.330802 <3>[ 15.169599] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10715 12:42:04.337563 <3>[ 15.169610] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10716 12:42:04.347171 <3>[ 15.169618] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10717 12:42:04.354072 <3>[ 15.171768] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10718 12:42:04.360634 <6>[ 15.174265] usbcore: registered new interface driver r8152
10719 12:42:04.366897 <6>[ 15.186296] videodev: Linux video capture interface: v2.00
10720 12:42:04.373661 <3>[ 15.209140] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10721 12:42:04.383605 <6>[ 15.248058] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10722 12:42:04.390030 <3>[ 15.262852] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10723 12:42:04.400044 <6>[ 15.268193] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10724 12:42:04.406758 <6>[ 15.276076] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10725 12:42:04.413334 <6>[ 15.282444] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10726 12:42:04.419911 <6>[ 15.290283] pci_bus 0000:00: root bus resource [bus 00-ff]
10727 12:42:04.429999 <4>[ 15.318675] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10728 12:42:04.436243 <6>[ 15.322591] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10729 12:42:04.443218 <4>[ 15.330700] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10730 12:42:04.453148 <6>[ 15.336495] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10731 12:42:04.459296 <3>[ 15.378731] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10732 12:42:04.466168 <6>[ 15.383363] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10733 12:42:04.472594 <6>[ 15.406844] r8152 2-1.3:1.0 eth0: v1.12.13
10734 12:42:04.479552 <6>[ 15.412378] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10735 12:42:04.482408 <6>[ 15.454936] pci 0000:00:00.0: supports D1 D2
10736 12:42:04.489221 <6>[ 15.459466] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10737 12:42:04.499928 <6>[ 15.468195] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10738 12:42:04.506665 <6>[ 15.476575] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10739 12:42:04.513355 <6>[ 15.482861] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10740 12:42:04.519851 <6>[ 15.490349] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10741 12:42:04.526459 <3>[ 15.490822] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10742 12:42:04.536394 <6>[ 15.497836] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10743 12:42:04.542897 <3>[ 15.504586] elants_i2c 4-0010: (read fw id) unexpected response: ff ff
10744 12:42:04.546514 <6>[ 15.511838] pci 0000:01:00.0: supports D1 D2
10745 12:42:04.556593 <6>[ 15.518640] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10746 12:42:04.562721 <6>[ 15.523034] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10747 12:42:04.570919 <6>[ 15.541828] usbcore: registered new interface driver cdc_ether
10748 12:42:04.578889 <6>[ 15.550306] usbcore: registered new interface driver r8153_ecm
10749 12:42:04.586030 <6>[ 15.554733] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10750 12:42:04.595369 <6>[ 15.563479] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10751 12:42:04.598826 <6>[ 15.564913] Bluetooth: Core ver 2.22
10752 12:42:04.605479 <6>[ 15.565763] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10753 12:42:04.612320 <6>[ 15.567020] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10754 12:42:04.625276 <6>[ 15.567169] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10755 12:42:04.631947 <6>[ 15.567308] usbcore: registered new interface driver uvcvideo
10756 12:42:04.638957 <6>[ 15.571577] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10757 12:42:04.644846 <6>[ 15.571592] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10758 12:42:04.651679 <6>[ 15.575487] NET: Registered PF_BLUETOOTH protocol family
10759 12:42:04.661396 <6>[ 15.582481] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10760 12:42:04.667945 <6>[ 15.588549] Bluetooth: HCI device and connection manager initialized
10761 12:42:04.674831 <6>[ 15.589310] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10762 12:42:04.681287 <6>[ 15.600977] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10763 12:42:04.687876 <6>[ 15.606994] Bluetooth: HCI socket layer initialized
10764 12:42:04.691228 <6>[ 15.614962] pci 0000:00:00.0: PCI bridge to [bus 01]
10765 12:42:04.697825 <6>[ 15.622959] Bluetooth: L2CAP socket layer initialized
10766 12:42:04.704126 <6>[ 15.628521] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10767 12:42:04.711056 <6>[ 15.636519] Bluetooth: SCO socket layer initialized
10768 12:42:04.717662 <6>[ 15.643259] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10769 12:42:04.720761 <6>[ 15.687069] usbcore: registered new interface driver btusb
10770 12:42:04.734058 <4>[ 15.687865] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10771 12:42:04.737450 <3>[ 15.687874] Bluetooth: hci0: Failed to load firmware file (-2)
10772 12:42:04.743939 <3>[ 15.687877] Bluetooth: hci0: Failed to set up firmware (-2)
10773 12:42:04.754151 <4>[ 15.687880] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10774 12:42:04.760483 <6>[ 15.693597] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10775 12:42:04.767059 <6>[ 15.737786] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10776 12:42:04.786512 <5>[ 15.754692] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10777 12:42:04.805612 <5>[ 15.773803] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10778 12:42:04.812115 <4>[ 15.780711] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10779 12:42:04.818675 <6>[ 15.789596] cfg80211: failed to load regulatory.db
10780 12:42:04.868901 <6>[ 15.837221] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10781 12:42:04.875405 <6>[ 15.844815] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10782 12:42:04.900468 <6>[ 15.871646] mt7921e 0000:01:00.0: ASIC revision: 79610010
10783 12:42:05.005902 <4>[ 15.970672] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10784 12:42:05.009832 Begin: Loading essential drivers ... done.
10785 12:42:05.015658 Begin: Running /scripts/init-premount ... done.
10786 12:42:05.022692 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10787 12:42:05.029283 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10788 12:42:05.035475 Device /sys/class/net/enx00e04c722dd6 found
10789 12:42:05.035583 done.
10790 12:42:05.078498 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10791 12:42:05.127956 <4>[ 16.092996] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10792 12:42:05.247845 <4>[ 16.212713] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10793 12:42:05.367859 <4>[ 16.332562] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10794 12:42:05.483338 <4>[ 16.448416] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10795 12:42:05.599575 <4>[ 16.564359] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10796 12:42:05.741510 <4>[ 16.680272] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10797 12:42:05.831344 <4>[ 16.796252] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10798 12:42:05.947557 <4>[ 16.912545] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10799 12:42:06.063521 <4>[ 17.028091] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10800 12:42:06.099868 <6>[ 17.071191] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
10801 12:42:06.162716 IP-Config: no response after 2 secs - giving up
10802 12:42:06.170732 <3>[ 17.142376] mt7921e 0000:01:00.0: hardware init failed
10803 12:42:06.206239 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10804 12:42:07.308886 IP-Config: enx00e04c722dd6 complete (dhcp from 192.168.201.1):
10805 12:42:07.315315 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10806 12:42:07.321788 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10807 12:42:07.328441 host : mt8192-asurada-spherion-r0-cbg-1
10808 12:42:07.334914 domain : lava-rack
10809 12:42:07.341411 rootserver: 192.168.201.1 rootpath:
10810 12:42:07.341510 filename :
10811 12:42:07.366581 done.
10812 12:42:07.373265 Begin: Running /scripts/nfs-bottom ... done.
10813 12:42:07.390013 Begin: Running /scripts/init-bottom ... done.
10814 12:42:08.491832 <6>[ 19.463672] NET: Registered PF_INET6 protocol family
10815 12:42:08.498816 <6>[ 19.470536] Segment Routing with IPv6
10816 12:42:08.501985 <6>[ 19.474504] In-situ OAM (IOAM) with IPv6
10817 12:42:08.609023 <30>[ 19.561155] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10818 12:42:08.612090 <30>[ 19.584955] systemd[1]: Detected architecture arm64.
10819 12:42:08.631925
10820 12:42:08.635033 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10821 12:42:08.635117
10822 12:42:08.656879 <30>[ 19.628903] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10823 12:42:09.108721 <30>[ 20.077388] systemd[1]: Queued start job for default target Graphical Interface.
10824 12:42:09.148040 <30>[ 20.119923] systemd[1]: Created slice system-getty.slice.
10825 12:42:09.154557 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10826 12:42:09.171443 <30>[ 20.143429] systemd[1]: Created slice system-modprobe.slice.
10827 12:42:09.177909 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10828 12:42:09.196159 <30>[ 20.168006] systemd[1]: Created slice system-serial\x2dgetty.slice.
10829 12:42:09.206132 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10830 12:42:09.219807 <30>[ 20.191361] systemd[1]: Created slice User and Session Slice.
10831 12:42:09.226069 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10832 12:42:09.246783 <30>[ 20.215404] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10833 12:42:09.257087 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10834 12:42:09.274179 <30>[ 20.242995] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10835 12:42:09.280745 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10836 12:42:09.301543 <30>[ 20.266944] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10837 12:42:09.308434 <30>[ 20.278969] systemd[1]: Reached target Local Encrypted Volumes.
10838 12:42:09.314698 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10839 12:42:09.331046 <30>[ 20.303101] systemd[1]: Reached target Paths.
10840 12:42:09.334245 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10841 12:42:09.350674 <30>[ 20.322873] systemd[1]: Reached target Remote File Systems.
10842 12:42:09.357382 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10843 12:42:09.370886 <30>[ 20.342845] systemd[1]: Reached target Slices.
10844 12:42:09.374153 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10845 12:42:09.391291 <30>[ 20.362877] systemd[1]: Reached target Swap.
10846 12:42:09.394351 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10847 12:42:09.414744 <30>[ 20.383170] systemd[1]: Listening on initctl Compatibility Named Pipe.
10848 12:42:09.420893 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10849 12:42:09.436585 <30>[ 20.408444] systemd[1]: Listening on Journal Audit Socket.
10850 12:42:09.442818 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10851 12:42:09.460400 <30>[ 20.432203] systemd[1]: Listening on Journal Socket (/dev/log).
10852 12:42:09.466479 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10853 12:42:09.483023 <30>[ 20.455172] systemd[1]: Listening on Journal Socket.
10854 12:42:09.489741 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10855 12:42:09.507570 <30>[ 20.475801] systemd[1]: Listening on Network Service Netlink Socket.
10856 12:42:09.513600 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10857 12:42:09.529134 <30>[ 20.500814] systemd[1]: Listening on udev Control Socket.
10858 12:42:09.535308 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10859 12:42:09.551545 <30>[ 20.523116] systemd[1]: Listening on udev Kernel Socket.
10860 12:42:09.557603 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10861 12:42:09.607584 <30>[ 20.579126] systemd[1]: Mounting Huge Pages File System...
10862 12:42:09.613873 Mounting [0;1;39mHuge Pages File System[0m...
10863 12:42:09.629138 <30>[ 20.601327] systemd[1]: Mounting POSIX Message Queue File System...
10864 12:42:09.636129 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10865 12:42:09.653729 <30>[ 20.625394] systemd[1]: Mounting Kernel Debug File System...
10866 12:42:09.660048 Mounting [0;1;39mKernel Debug File System[0m...
10867 12:42:09.678766 <30>[ 20.647161] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10868 12:42:09.722634 <30>[ 20.691319] systemd[1]: Starting Create list of static device nodes for the current kernel...
10869 12:42:09.729353 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10870 12:42:09.749301 <30>[ 20.721414] systemd[1]: Starting Load Kernel Module configfs...
10871 12:42:09.756775 Starting [0;1;39mLoad Kernel Module configfs[0m...
10872 12:42:09.773772 <30>[ 20.745413] systemd[1]: Starting Load Kernel Module drm...
10873 12:42:09.780238 Starting [0;1;39mLoad Kernel Module drm[0m...
10874 12:42:09.797423 <30>[ 20.769460] systemd[1]: Starting Load Kernel Module fuse...
10875 12:42:09.804034 Starting [0;1;39mLoad Kernel Module fuse[0m...
10876 12:42:09.834022 <6>[ 20.805423] fuse: init (API version 7.37)
10877 12:42:09.843240 <30>[ 20.805995] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10878 12:42:09.851958 <30>[ 20.823869] systemd[1]: Starting Journal Service...
10879 12:42:09.855094 Starting [0;1;39mJournal Service[0m...
10880 12:42:09.877102 <30>[ 20.849072] systemd[1]: Starting Load Kernel Modules...
10881 12:42:09.883624 Starting [0;1;39mLoad Kernel Modules[0m...
10882 12:42:09.926833 <30>[ 20.895505] systemd[1]: Starting Remount Root and Kernel File Systems...
10883 12:42:09.933157 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10884 12:42:09.949619 <30>[ 20.921759] systemd[1]: Starting Coldplug All udev Devices...
10885 12:42:09.956483 Starting [0;1;39mColdplug All udev Devices[0m...
10886 12:42:09.973790 <30>[ 20.945806] systemd[1]: Mounted Huge Pages File System.
10887 12:42:09.980273 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10888 12:42:09.995159 <30>[ 20.967293] systemd[1]: Mounted POSIX Message Queue File System.
10889 12:42:10.002094 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10890 12:42:10.013942 <3>[ 20.982812] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10891 12:42:10.020662 <30>[ 20.992357] systemd[1]: Mounted Kernel Debug File System.
10892 12:42:10.027161 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10893 12:42:10.044993 <3>[ 21.013877] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10894 12:42:10.055166 <30>[ 21.023687] systemd[1]: Finished Create list of static device nodes for the current kernel.
10895 12:42:10.065145 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10896 12:42:10.080154 <30>[ 21.051856] systemd[1]: modprobe@configfs.service: Succeeded.
10897 12:42:10.086791 <30>[ 21.058495] systemd[1]: Finished Load Kernel Module configfs.
10898 12:42:10.096909 <3>[ 21.061395] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10899 12:42:10.103861 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10900 12:42:10.119851 <30>[ 21.091701] systemd[1]: modprobe@drm.service: Succeeded.
10901 12:42:10.130216 <3>[ 21.095649] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10902 12:42:10.133299 <30>[ 21.097891] systemd[1]: Finished Load Kernel Module drm.
10903 12:42:10.140276 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10904 12:42:10.156284 <30>[ 21.128216] systemd[1]: modprobe@fuse.service: Succeeded.
10905 12:42:10.166032 <3>[ 21.129145] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10906 12:42:10.172509 <30>[ 21.134505] systemd[1]: Finished Load Kernel Module fuse.
10907 12:42:10.175939 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10908 12:42:10.191817 <30>[ 21.163836] systemd[1]: Finished Load Kernel Modules.
10909 12:42:10.201909 <3>[ 21.164046] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10910 12:42:10.208372 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10911 12:42:10.227790 <30>[ 21.196236] systemd[1]: Finished Remount Root and Kernel File Systems.
10912 12:42:10.234305 <3>[ 21.201032] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 12:42:10.241112 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10914 12:42:10.268155 <3>[ 21.237133] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10915 12:42:10.287481 <30>[ 21.259245] systemd[1]: Mounting FUSE Control File System...
10916 12:42:10.294480 Mounting [0;1;39mFUSE Control File System[0m...
10917 12:42:10.304220 <3>[ 21.270888] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10918 12:42:10.314061 <30>[ 21.282830] systemd[1]: Mounting Kernel Configuration File System...
10919 12:42:10.317126 Mounting [0;1;39mKernel Configuration File System[0m...
10920 12:42:10.336055 <3>[ 21.304878] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 12:42:10.348889 <30>[ 21.317774] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10922 12:42:10.359405 <30>[ 21.326890] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10923 12:42:10.391563 <30>[ 21.363435] systemd[1]: Starting Load/Save Random Seed...
10924 12:42:10.397769 Starting [0;1;39mLoad/Save Random Seed[0m...
10925 12:42:10.413673 <30>[ 21.385862] systemd[1]: Starting Apply Kernel Variables...
10926 12:42:10.420237 Starting [0;1;39mApply Kernel Variables[0m...
10927 12:42:10.455324 <30>[ 21.427341] systemd[1]: Starting Create System Users...
10928 12:42:10.461921 Starting [0;1;39mCreate System Users[0m...
10929 12:42:10.480889 <30>[ 21.452970] systemd[1]: Started Journal Service.
10930 12:42:10.487200 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10931 12:42:10.505215 <4>[ 21.467291] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10932 12:42:10.515380 <3>[ 21.482980] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10933 12:42:10.518781 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10934 12:42:10.535912 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10935 12:42:10.559854 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10936 12:42:10.574798 See 'systemctl status systemd-udev-trigger.service' for details.
10937 12:42:10.592028 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10938 12:42:10.607930 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10939 12:42:10.623444 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10940 12:42:10.656059 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10941 12:42:10.677707 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10942 12:42:10.697289 <46>[ 21.666196] systemd-journald[292]: Received client request to flush runtime journal.
10943 12:42:11.771824 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10944 12:42:11.783281 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10945 12:42:11.798845 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10946 12:42:11.850853 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10947 12:42:12.064635 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10948 12:42:12.111335 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10949 12:42:12.159200 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10950 12:42:12.216658 Starting [0;1;39mNetwork Service[0m...
10951 12:42:12.302611 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10952 12:42:12.363272 Starting [0;1;39mNetwork Time Synchronization[0m...
10953 12:42:12.391923 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10954 12:42:12.535161 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10955 12:42:12.558195 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10956 12:42:12.591049 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10957 12:42:12.803113 <6>[ 23.775588] remoteproc remoteproc0: powering up scp
10958 12:42:12.822433 <4>[ 23.791310] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10959 12:42:12.829207 <3>[ 23.801211] remoteproc remoteproc0: request_firmware failed: -2
10960 12:42:12.838822 <3>[ 23.807436] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10961 12:42:12.912056 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10962 12:42:12.930623 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10963 12:42:12.947134 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10964 12:42:12.967048 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10965 12:42:13.015610 Starting [0;1;39mNetwork Name Resolution[0m...
10966 12:42:13.033778 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10967 12:42:13.051726 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10968 12:42:13.071251 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10969 12:42:13.089398 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10970 12:42:13.110918 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10971 12:42:13.126461 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10972 12:42:13.142987 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10973 12:42:13.833512 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10974 12:42:14.169472 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10975 12:42:14.200051 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10976 12:42:14.224685 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10977 12:42:14.238449 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10978 12:42:14.262651 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10979 12:42:14.274562 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10980 12:42:14.290091 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10981 12:42:14.347064 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10982 12:42:14.478023 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10983 12:42:14.611505 Starting [0;1;39mUser Login Management[0m...
10984 12:42:14.627345 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10985 12:42:14.872752 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10986 12:42:14.895185 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10987 12:42:14.914163 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10988 12:42:14.979378 Starting [0;1;39mPermit User Sessions[0m...
10989 12:42:14.999914 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10990 12:42:15.016721 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10991 12:42:15.071252 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10992 12:42:15.090023 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10993 12:42:15.096142 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10994 12:42:15.110990 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10995 12:42:15.118327 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10996 12:42:15.134740 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10997 12:42:15.174782 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10998 12:42:15.212857 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10999 12:42:15.267546
11000 12:42:15.267696
11001 12:42:15.271120 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11002 12:42:15.271207
11003 12:42:15.274171 debian-bullseye-arm64 login: root (automatic login)
11004 12:42:15.274258
11005 12:42:15.274324
11006 12:42:15.540640 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Wed Jun 14 12:30:40 UTC 2023 aarch64
11007 12:42:15.540821
11008 12:42:15.546931 The programs included with the Debian GNU/Linux system are free software;
11009 12:42:15.553710 the exact distribution terms for each program are described in the
11010 12:42:15.556927 individual files in /usr/share/doc/*/copyright.
11011 12:42:15.557047
11012 12:42:15.563719 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11013 12:42:15.566712 permitted by applicable law.
11014 12:42:16.317239 Matched prompt #10: / #
11016 12:42:16.317518 Setting prompt string to ['/ #']
11017 12:42:16.317616 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11019 12:42:16.317812 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11020 12:42:16.317902 start: 2.2.6 expect-shell-connection (timeout 00:03:35) [common]
11021 12:42:16.317976 Setting prompt string to ['/ #']
11022 12:42:16.318039 Forcing a shell prompt, looking for ['/ #']
11024 12:42:16.368258 / #
11025 12:42:16.368365 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11026 12:42:16.368458 Waiting using forced prompt support (timeout 00:02:30)
11027 12:42:16.373180
11028 12:42:16.373452 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11029 12:42:16.373549 start: 2.2.7 export-device-env (timeout 00:03:35) [common]
11031 12:42:16.473893 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10724840/extract-nfsrootfs-0nvap_bc'
11032 12:42:16.478687 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10724840/extract-nfsrootfs-0nvap_bc'
11034 12:42:16.579174 / # export NFS_SERVER_IP='192.168.201.1'
11035 12:42:16.584009 export NFS_SERVER_IP='192.168.201.1'
11036 12:42:16.584296 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11037 12:42:16.584397 end: 2.2 depthcharge-retry (duration 00:01:25) [common]
11038 12:42:16.584492 end: 2 depthcharge-action (duration 00:01:25) [common]
11039 12:42:16.584583 start: 3 lava-test-retry (timeout 00:07:55) [common]
11040 12:42:16.584673 start: 3.1 lava-test-shell (timeout 00:07:55) [common]
11041 12:42:16.584769 Using namespace: common
11043 12:42:16.685044 / # #
11044 12:42:16.685190 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11045 12:42:16.690128 #
11046 12:42:16.690395 Using /lava-10724840
11048 12:42:16.790724 / # export SHELL=/bin/bash
11049 12:42:16.795844 export SHELL=/bin/bash
11051 12:42:16.896361 / # . /lava-10724840/environment
11052 12:42:16.901285 . /lava-10724840/environment
11054 12:42:17.006171 / # /lava-10724840/bin/lava-test-runner /lava-10724840/0
11055 12:42:17.006281 Test shell timeout: 10s (minimum of the action and connection timeout)
11056 12:42:17.011635 /lava-10724840/bin/lava-test-runner /lava-10724840/0
11057 12:42:17.214617 + export TESTRUN_ID=0_timesync-off
11058 12:42:17.217977 + TESTRUN_ID=0_timesync-off
11059 12:42:17.221251 + cd /lava-10724840/0/tests/0_timesync-off
11060 12:42:17.224291 ++ cat uuid
11061 12:42:17.224375 + UUID=10724840_1.6.2.3.1
11062 12:42:17.227570 + set +x
11063 12:42:17.231119 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10724840_1.6.2.3.1>
11064 12:42:17.231382 Received signal: <STARTRUN> 0_timesync-off 10724840_1.6.2.3.1
11065 12:42:17.231457 Starting test lava.0_timesync-off (10724840_1.6.2.3.1)
11066 12:42:17.231546 Skipping test definition patterns.
11067 12:42:17.234402 + systemctl stop systemd-timesyncd
11068 12:42:17.255385 + set +x
11069 12:42:17.258082 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10724840_1.6.2.3.1>
11070 12:42:17.258338 Received signal: <ENDRUN> 0_timesync-off 10724840_1.6.2.3.1
11071 12:42:17.258424 Ending use of test pattern.
11072 12:42:17.258489 Ending test lava.0_timesync-off (10724840_1.6.2.3.1), duration 0.03
11074 12:42:17.304322 + export TESTRUN_ID=1_kselftest-arm64
11075 12:42:17.304408 + TESTRUN_ID=1_kselftest-arm64
11076 12:42:17.310837 + cd /lava-10724840/0/tests/1_kselftest-arm64
11077 12:42:17.310922 ++ cat uuid
11078 12:42:17.314231 + UUID=10724840_1.6.2.3.5
11079 12:42:17.314314 + set +x
11080 12:42:17.317681 Received signal: <STARTRUN> 1_kselftest-arm64 10724840_1.6.2.3.5
11081 12:42:17.317764 Starting test lava.1_kselftest-arm64 (10724840_1.6.2.3.5)
11082 12:42:17.317845 Skipping test definition patterns.
11083 12:42:17.320886 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 10724840_1.6.2.3.5>
11084 12:42:17.321028 + cd ./automated/linux/kselftest/
11085 12:42:17.347335 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11086 12:42:17.354737 INFO: install_deps skipped
11087 12:42:17.453165 --2023-06-14 12:42:12-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11088 12:42:17.456233 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11089 12:42:17.582977 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11090 12:42:17.716049 HTTP request sent, awaiting response... 200 OK
11091 12:42:17.718998 Length: 2878416 (2.7M) [application/octet-stream]
11092 12:42:17.722497 Saving to: 'kselftest.tar.xz'
11093 12:42:17.722582
11094 12:42:17.722648
11095 12:42:17.981094 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11096 12:42:18.247269 kselftest.tar.xz 1%[ ] 47.81K 181KB/s
11097 12:42:18.695835 kselftest.tar.xz 7%[> ] 217.50K 410KB/s
11098 12:42:18.973067 kselftest.tar.xz 29%[====> ] 825.54K 843KB/s
11099 12:42:18.979307 kselftest.tar.xz 88%[================> ] 2.42M 1.92MB/s
11100 12:42:18.985991 kselftest.tar.xz 100%[===================>] 2.74M 2.18MB/s in 1.3s
11101 12:42:18.986075
11102 12:42:19.229312 2023-06-14 12:42:14 (2.18 MB/s) - 'kselftest.tar.xz' saved [2878416/2878416]
11103 12:42:19.229454
11104 12:42:23.632302 skiplist:
11105 12:42:23.635536 ========================================
11106 12:42:23.639015 ========================================
11107 12:42:23.667881 arm64:tags_test
11108 12:42:23.671626 arm64:run_tags_test.sh
11109 12:42:23.671712 arm64:fake_sigreturn_bad_magic
11110 12:42:23.674795 arm64:fake_sigreturn_bad_size
11111 12:42:23.677899 arm64:fake_sigreturn_bad_size_for_magic0
11112 12:42:23.681421 arm64:fake_sigreturn_duplicated_fpsimd
11113 12:42:23.684766 arm64:fake_sigreturn_misaligned_sp
11114 12:42:23.687994 arm64:fake_sigreturn_missing_fpsimd
11115 12:42:23.691379 arm64:fake_sigreturn_sme_change_vl
11116 12:42:23.694495 arm64:fake_sigreturn_sve_change_vl
11117 12:42:23.697698 arm64:mangle_pstate_invalid_compat_toggle
11118 12:42:23.700867 arm64:mangle_pstate_invalid_daif_bits
11119 12:42:23.704551 arm64:mangle_pstate_invalid_mode_el1h
11120 12:42:23.707746 arm64:mangle_pstate_invalid_mode_el1t
11121 12:42:23.710878 arm64:mangle_pstate_invalid_mode_el2h
11122 12:42:23.717751 arm64:mangle_pstate_invalid_mode_el2t
11123 12:42:23.720768 arm64:mangle_pstate_invalid_mode_el3h
11124 12:42:23.723996 arm64:mangle_pstate_invalid_mode_el3t
11125 12:42:23.724072 arm64:sme_trap_no_sm
11126 12:42:23.727601 arm64:sme_trap_non_streaming
11127 12:42:23.727683 arm64:sme_trap_za
11128 12:42:23.731127 arm64:sme_vl
11129 12:42:23.731203 arm64:ssve_regs
11130 12:42:23.733816 arm64:sve_regs
11131 12:42:23.733899 arm64:sve_vl
11132 12:42:23.737389 arm64:za_no_regs
11133 12:42:23.737470 arm64:za_regs
11134 12:42:23.737535 arm64:pac
11135 12:42:23.740238 arm64:fp-stress
11136 12:42:23.740312 arm64:sve-ptrace
11137 12:42:23.743757 arm64:sve-probe-vls
11138 12:42:23.743837 arm64:vec-syscfg
11139 12:42:23.746838 arm64:za-fork
11140 12:42:23.746912 arm64:za-ptrace
11141 12:42:23.750462 arm64:check_buffer_fill
11142 12:42:23.750539 arm64:check_child_memory
11143 12:42:23.753441 arm64:check_gcr_el1_cswitch
11144 12:42:23.756896 arm64:check_ksm_options
11145 12:42:23.757006 arm64:check_mmap_options
11146 12:42:23.760413 arm64:check_prctl
11147 12:42:23.763488 arm64:check_tags_inclusion
11148 12:42:23.763569 arm64:check_user_mem
11149 12:42:23.766846 arm64:btitest
11150 12:42:23.766920 arm64:nobtitest
11151 12:42:23.766990 arm64:hwcap
11152 12:42:23.770186 arm64:ptrace
11153 12:42:23.770259 arm64:syscall-abi
11154 12:42:23.773611 arm64:tpidr2
11155 12:42:23.776532 ============== Tests to run ===============
11156 12:42:23.776620 arm64:tags_test
11157 12:42:23.779844 arm64:run_tags_test.sh
11158 12:42:23.783439 arm64:fake_sigreturn_bad_magic
11159 12:42:23.786706 arm64:fake_sigreturn_bad_size
11160 12:42:23.789845 arm64:fake_sigreturn_bad_size_for_magic0
11161 12:42:23.793295 arm64:fake_sigreturn_duplicated_fpsimd
11162 12:42:23.796373 arm64:fake_sigreturn_misaligned_sp
11163 12:42:23.800267 arm64:fake_sigreturn_missing_fpsimd
11164 12:42:23.803026 arm64:fake_sigreturn_sme_change_vl
11165 12:42:23.806726 arm64:fake_sigreturn_sve_change_vl
11166 12:42:23.809807 arm64:mangle_pstate_invalid_compat_toggle
11167 12:42:23.813431 arm64:mangle_pstate_invalid_daif_bits
11168 12:42:23.816414 arm64:mangle_pstate_invalid_mode_el1h
11169 12:42:23.819931 arm64:mangle_pstate_invalid_mode_el1t
11170 12:42:23.822947 arm64:mangle_pstate_invalid_mode_el2h
11171 12:42:23.826364 arm64:mangle_pstate_invalid_mode_el2t
11172 12:42:23.829497 arm64:mangle_pstate_invalid_mode_el3h
11173 12:42:23.832776 arm64:mangle_pstate_invalid_mode_el3t
11174 12:42:23.832855 arm64:sme_trap_no_sm
11175 12:42:23.836244 arm64:sme_trap_non_streaming
11176 12:42:23.839517 arm64:sme_trap_za
11177 12:42:23.839601 arm64:sme_vl
11178 12:42:23.842676 arm64:ssve_regs
11179 12:42:23.842760 arm64:sve_regs
11180 12:42:23.842827 arm64:sve_vl
11181 12:42:23.846071 arm64:za_no_regs
11182 12:42:23.846155 arm64:za_regs
11183 12:42:23.849968 arm64:pac
11184 12:42:23.850050 arm64:fp-stress
11185 12:42:23.850115 arm64:sve-ptrace
11186 12:42:23.852551 arm64:sve-probe-vls
11187 12:42:23.852633 arm64:vec-syscfg
11188 12:42:23.855980 arm64:za-fork
11189 12:42:23.856055 arm64:za-ptrace
11190 12:42:23.859155 arm64:check_buffer_fill
11191 12:42:23.862364 arm64:check_child_memory
11192 12:42:23.862445 arm64:check_gcr_el1_cswitch
11193 12:42:23.865840 arm64:check_ksm_options
11194 12:42:23.869205 arm64:check_mmap_options
11195 12:42:23.869279 arm64:check_prctl
11196 12:42:23.872370 arm64:check_tags_inclusion
11197 12:42:23.875697 arm64:check_user_mem
11198 12:42:23.875778 arm64:btitest
11199 12:42:23.875840 arm64:nobtitest
11200 12:42:23.878863 arm64:hwcap
11201 12:42:23.878942 arm64:ptrace
11202 12:42:23.882375 arm64:syscall-abi
11203 12:42:23.882454 arm64:tpidr2
11204 12:42:23.885816 ===========End Tests to run ===============
11205 12:42:24.004527 <12>[ 34.978145] kselftest: Running tests in arm64
11206 12:42:24.012022 TAP version 13
11207 12:42:24.022685 1..48
11208 12:42:24.035439 # selftests: arm64: tags_test
11209 12:42:24.378479 ok 1 selftests: arm64: tags_test
11210 12:42:24.390080 # selftests: arm64: run_tags_test.sh
11211 12:42:24.439237 # --------------------
11212 12:42:24.442793 # running tags test
11213 12:42:24.442877 # --------------------
11214 12:42:24.446163 # [PASS]
11215 12:42:24.449264 ok 2 selftests: arm64: run_tags_test.sh
11216 12:42:24.458112 # selftests: arm64: fake_sigreturn_bad_magic
11217 12:42:24.502773 # Registered handlers for all signals.
11218 12:42:24.502870 # Detected MINSTKSIGSZ:4720
11219 12:42:24.506234 # Testcase initialized.
11220 12:42:24.509120 # uc context validated.
11221 12:42:24.512775 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11222 12:42:24.515694 # Handled SIG_COPYCTX
11223 12:42:24.515770 # Available space:3568
11224 12:42:24.522516 # Using badly built context - ERR: BAD MAGIC !
11225 12:42:24.529241 # SIG_OK -- SP:0xFFFFFEEAA1F0 si_addr@:0xfffffeeaa1f0 si_code:2 token@:0xfffffeea8f90 offset:-4704
11226 12:42:24.532653 # ==>> completed. PASS(1)
11227 12:42:24.539029 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11228 12:42:24.545418 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFEEA8F90
11229 12:42:24.552073 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11230 12:42:24.555254 # selftests: arm64: fake_sigreturn_bad_size
11231 12:42:24.562401 # Registered handlers for all signals.
11232 12:42:24.562480 # Detected MINSTKSIGSZ:4720
11233 12:42:24.566006 # Testcase initialized.
11234 12:42:24.569413 # uc context validated.
11235 12:42:24.572861 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11236 12:42:24.575883 # Handled SIG_COPYCTX
11237 12:42:24.575966 # Available space:3568
11238 12:42:24.578976 # uc context validated.
11239 12:42:24.586179 # Using badly built context - ERR: Bad size for esr_context
11240 12:42:24.592468 # SIG_OK -- SP:0xFFFFC0FA7F80 si_addr@:0xffffc0fa7f80 si_code:2 token@:0xffffc0fa6d20 offset:-4704
11241 12:42:24.595643 # ==>> completed. PASS(1)
11242 12:42:24.602218 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11243 12:42:24.608735 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC0FA6D20
11244 12:42:24.612209 ok 4 selftests: arm64: fake_sigreturn_bad_size
11245 12:42:24.618498 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11246 12:42:24.625390 # Registered handlers for all signals.
11247 12:42:24.625475 # Detected MINSTKSIGSZ:4720
11248 12:42:24.628588 # Testcase initialized.
11249 12:42:24.631648 # uc context validated.
11250 12:42:24.635201 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11251 12:42:24.638512 # Handled SIG_COPYCTX
11252 12:42:24.638594 # Available space:3568
11253 12:42:24.645536 # Using badly built context - ERR: Bad size for terminator
11254 12:42:24.654927 # SIG_OK -- SP:0xFFFFE86D9310 si_addr@:0xffffe86d9310 si_code:2 token@:0xffffe86d80b0 offset:-4704
11255 12:42:24.655007 # ==>> completed. PASS(1)
11256 12:42:24.664645 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11257 12:42:24.671306 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE86D80B0
11258 12:42:24.674719 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11259 12:42:24.681378 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11260 12:42:24.684550 # Registered handlers for all signals.
11261 12:42:24.687757 # Detected MINSTKSIGSZ:4720
11262 12:42:24.687837 # Testcase initialized.
11263 12:42:24.691234 # uc context validated.
11264 12:42:24.698329 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11265 12:42:24.698413 # Handled SIG_COPYCTX
11266 12:42:24.700874 # Available space:3568
11267 12:42:24.704301 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11268 12:42:24.714318 # SIG_OK -- SP:0xFFFFDA6A1150 si_addr@:0xffffda6a1150 si_code:2 token@:0xffffda69fef0 offset:-4704
11269 12:42:24.717555 # ==>> completed. PASS(1)
11270 12:42:24.724284 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11271 12:42:24.730712 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDA69FEF0
11272 12:42:24.734086 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11273 12:42:24.740571 # selftests: arm64: fake_sigreturn_misaligned_sp
11274 12:42:24.744183 # Registered handlers for all signals.
11275 12:42:24.747206 # Detected MINSTKSIGSZ:4720
11276 12:42:24.747281 # Testcase initialized.
11277 12:42:24.750448 # uc context validated.
11278 12:42:24.754080 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11279 12:42:24.757532 # Handled SIG_COPYCTX
11280 12:42:24.766991 # SIG_OK -- SP:0xFFFFD4E9A903 si_addr@:0xffffd4e9a903 si_code:2 token@:0xffffd4e9a903 offset:0
11281 12:42:24.767070 # ==>> completed. PASS(1)
11282 12:42:24.777071 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11283 12:42:24.783646 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD4E9A903
11284 12:42:24.787085 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11285 12:42:24.790169 # selftests: arm64: fake_sigreturn_missing_fpsimd
11286 12:42:24.804675 # Registered handlers for all signals.
11287 12:42:24.804756 # Detected MINSTKSIGSZ:4720
11288 12:42:24.807770 # Testcase initialized.
11289 12:42:24.811412 # uc context validated.
11290 12:42:24.814669 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11291 12:42:24.818015 # Handled SIG_COPYCTX
11292 12:42:24.821171 # Mangling template header. Spare space:4096
11293 12:42:24.824298 # Using badly built context - ERR: Missing FPSIMD
11294 12:42:24.834163 # SIG_OK -- SP:0xFFFFE80604B0 si_addr@:0xffffe80604b0 si_code:2 token@:0xffffe805f250 offset:-4704
11295 12:42:24.837742 # ==>> completed. PASS(1)
11296 12:42:24.844580 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11297 12:42:24.851071 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE805F250
11298 12:42:24.854331 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11299 12:42:24.860727 # selftests: arm64: fake_sigreturn_sme_change_vl
11300 12:42:24.864035 # Registered handlers for all signals.
11301 12:42:24.867711 # Detected MINSTKSIGSZ:4720
11302 12:42:24.867897 # ==>> completed. SKIP.
11303 12:42:24.874334 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11304 12:42:24.880622 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11305 12:42:24.883990 # selftests: arm64: fake_sigreturn_sve_change_vl
11306 12:42:24.925270 # Registered handlers for all signals.
11307 12:42:24.925413 # Detected MINSTKSIGSZ:4720
11308 12:42:24.928587 # ==>> completed. SKIP.
11309 12:42:24.935506 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11310 12:42:24.938497 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11311 12:42:24.944927 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11312 12:42:24.987886 # Registered handlers for all signals.
11313 12:42:24.988033 # Detected MINSTKSIGSZ:4720
11314 12:42:24.990857 # Testcase initialized.
11315 12:42:24.994315 # uc context validated.
11316 12:42:24.994401 # Handled SIG_TRIG
11317 12:42:25.004390 # SIG_OK -- SP:0xFFFFE1A0A180 si_addr@:0xffffe1a0a180 si_code:2 token@:(nil) offset:-281474467144064
11318 12:42:25.007807 # ==>> completed. PASS(1)
11319 12:42:25.014020 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11320 12:42:25.020788 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11321 12:42:25.023887 # selftests: arm64: mangle_pstate_invalid_daif_bits
11322 12:42:25.048413 # Registered handlers for all signals.
11323 12:42:25.048546 # Detected MINSTKSIGSZ:4720
11324 12:42:25.051309 # Testcase initialized.
11325 12:42:25.054670 # uc context validated.
11326 12:42:25.054769 # Handled SIG_TRIG
11327 12:42:25.064730 # SIG_OK -- SP:0xFFFFE80F92E0 si_addr@:0xffffe80f92e0 si_code:2 token@:(nil) offset:-281474575078112
11328 12:42:25.067844 # ==>> completed. PASS(1)
11329 12:42:25.074550 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11330 12:42:25.078207 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11331 12:42:25.084352 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11332 12:42:25.109547 # Registered handlers for all signals.
11333 12:42:25.109692 # Detected MINSTKSIGSZ:4720
11334 12:42:25.112475 # Testcase initialized.
11335 12:42:25.115988 # uc context validated.
11336 12:42:25.116077 # Handled SIG_TRIG
11337 12:42:25.126296 # SIG_OK -- SP:0xFFFFEABAD310 si_addr@:0xffffeabad310 si_code:2 token@:(nil) offset:-281474619855632
11338 12:42:25.129288 # ==>> completed. PASS(1)
11339 12:42:25.135875 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11340 12:42:25.138957 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11341 12:42:25.145716 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11342 12:42:25.168344 # Registered handlers for all signals.
11343 12:42:25.168478 # Detected MINSTKSIGSZ:4720
11344 12:42:25.171879 # Testcase initialized.
11345 12:42:25.174846 # uc context validated.
11346 12:42:25.174933 # Handled SIG_TRIG
11347 12:42:25.184856 # SIG_OK -- SP:0xFFFFF7649F30 si_addr@:0xfffff7649f30 si_code:2 token@:(nil) offset:-281474832310064
11348 12:42:25.188106 # ==>> completed. PASS(1)
11349 12:42:25.194979 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11350 12:42:25.198015 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11351 12:42:25.204542 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11352 12:42:25.229457 # Registered handlers for all signals.
11353 12:42:25.229604 # Detected MINSTKSIGSZ:4720
11354 12:42:25.232748 # Testcase initialized.
11355 12:42:25.236148 # uc context validated.
11356 12:42:25.236295 # Handled SIG_TRIG
11357 12:42:25.245871 # SIG_OK -- SP:0xFFFFEDC6D7C0 si_addr@:0xffffedc6d7c0 si_code:2 token@:(nil) offset:-281474670974912
11358 12:42:25.249140 # ==>> completed. PASS(1)
11359 12:42:25.255625 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11360 12:42:25.259146 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11361 12:42:25.265604 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11362 12:42:25.290316 # Registered handlers for all signals.
11363 12:42:25.290452 # Detected MINSTKSIGSZ:4720
11364 12:42:25.293993 # Testcase initialized.
11365 12:42:25.297041 # uc context validated.
11366 12:42:25.297127 # Handled SIG_TRIG
11367 12:42:25.307253 # SIG_OK -- SP:0xFFFFD1FFB3C0 si_addr@:0xffffd1ffb3c0 si_code:2 token@:(nil) offset:-281474204939200
11368 12:42:25.310383 # ==>> completed. PASS(1)
11369 12:42:25.316716 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11370 12:42:25.320368 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11371 12:42:25.326648 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11372 12:42:25.353759 # Registered handlers for all signals.
11373 12:42:25.353910 # Detected MINSTKSIGSZ:4720
11374 12:42:25.357461 # Testcase initialized.
11375 12:42:25.360366 # uc context validated.
11376 12:42:25.360449 # Handled SIG_TRIG
11377 12:42:25.370459 # SIG_OK -- SP:0xFFFFFA314210 si_addr@:0xfffffa314210 si_code:2 token@:(nil) offset:-281474879275536
11378 12:42:25.373735 # ==>> completed. PASS(1)
11379 12:42:25.380448 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11380 12:42:25.383507 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11381 12:42:25.390130 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11382 12:42:25.413293 # Registered handlers for all signals.
11383 12:42:25.413497 # Detected MINSTKSIGSZ:4720
11384 12:42:25.416330 # Testcase initialized.
11385 12:42:25.419553 # uc context validated.
11386 12:42:25.419760 # Handled SIG_TRIG
11387 12:42:25.429446 # SIG_OK -- SP:0xFFFFFA7F32A0 si_addr@:0xfffffa7f32a0 si_code:2 token@:(nil) offset:-281474884383392
11388 12:42:25.432826 # ==>> completed. PASS(1)
11389 12:42:25.439458 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11390 12:42:25.442867 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11391 12:42:25.446079 # selftests: arm64: sme_trap_no_sm
11392 12:42:25.475279 # Registered handlers for all signals.
11393 12:42:25.475621 # Detected MINSTKSIGSZ:4720
11394 12:42:25.478611 # ==>> completed. SKIP.
11395 12:42:25.488799 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11396 12:42:25.492088 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11397 12:42:25.495197 # selftests: arm64: sme_trap_non_streaming
11398 12:42:25.542629 # Registered handlers for all signals.
11399 12:42:25.543031 # Detected MINSTKSIGSZ:4720
11400 12:42:25.545471 # ==>> completed. SKIP.
11401 12:42:25.555692 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11402 12:42:25.561921 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11403 12:42:25.565514 # selftests: arm64: sme_trap_za
11404 12:42:25.605001 # Registered handlers for all signals.
11405 12:42:25.605156 # Detected MINSTKSIGSZ:4720
11406 12:42:25.608182 # Testcase initialized.
11407 12:42:25.618262 # SIG_OK -- SP:0xFFFFC1745BF0 si_addr@:0xaaaad2a52510 si_code:1 token@:(nil) offset:-187650655200528
11408 12:42:25.618350 # ==>> completed. PASS(1)
11409 12:42:25.627951 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11410 12:42:25.631449 ok 21 selftests: arm64: sme_trap_za
11411 12:42:25.631550 # selftests: arm64: sme_vl
11412 12:42:25.666702 # Registered handlers for all signals.
11413 12:42:25.666850 # Detected MINSTKSIGSZ:4720
11414 12:42:25.669912 # ==>> completed. SKIP.
11415 12:42:25.677100 # # SME VL :: Check that we get the right SME VL reported
11416 12:42:25.679978 ok 22 selftests: arm64: sme_vl # SKIP
11417 12:42:25.680146 # selftests: arm64: ssve_regs
11418 12:42:25.727534 # Registered handlers for all signals.
11419 12:42:25.727681 # Detected MINSTKSIGSZ:4720
11420 12:42:25.730276 # ==>> completed. SKIP.
11421 12:42:25.737148 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11422 12:42:25.743688 ok 23 selftests: arm64: ssve_regs # SKIP
11423 12:42:25.743796 # selftests: arm64: sve_regs
11424 12:42:25.789373 # Registered handlers for all signals.
11425 12:42:25.789506 # Detected MINSTKSIGSZ:4720
11426 12:42:25.793149 # ==>> completed. SKIP.
11427 12:42:25.799602 # # SVE registers :: Check that we get the right SVE registers reported
11428 12:42:25.803293 ok 24 selftests: arm64: sve_regs # SKIP
11429 12:42:25.806245 # selftests: arm64: sve_vl
11430 12:42:25.851800 # Registered handlers for all signals.
11431 12:42:25.851939 # Detected MINSTKSIGSZ:4720
11432 12:42:25.854653 # ==>> completed. SKIP.
11433 12:42:25.861498 # # SVE VL :: Check that we get the right SVE VL reported
11434 12:42:25.864956 ok 25 selftests: arm64: sve_vl # SKIP
11435 12:42:25.865086 # selftests: arm64: za_no_regs
11436 12:42:25.913455 # Registered handlers for all signals.
11437 12:42:25.913632 # Detected MINSTKSIGSZ:4720
11438 12:42:25.916501 # ==>> completed. SKIP.
11439 12:42:25.923433 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11440 12:42:25.926585 ok 26 selftests: arm64: za_no_regs # SKIP
11441 12:42:25.929697 # selftests: arm64: za_regs
11442 12:42:25.973778 # Registered handlers for all signals.
11443 12:42:25.973970 # Detected MINSTKSIGSZ:4720
11444 12:42:25.976548 # ==>> completed. SKIP.
11445 12:42:25.982972 # # ZA register :: Check that we get the right ZA registers reported
11446 12:42:25.986557 ok 27 selftests: arm64: za_regs # SKIP
11447 12:42:25.986659 # selftests: arm64: pac
11448 12:42:26.030764 # TAP version 13
11449 12:42:26.030904 # 1..7
11450 12:42:26.033802 # # Starting 7 tests from 1 test cases.
11451 12:42:26.037089 # # RUN global.corrupt_pac ...
11452 12:42:26.040399 # # SKIP PAUTH not enabled
11453 12:42:26.043465 # # OK global.corrupt_pac
11454 12:42:26.047013 # ok 1 # SKIP PAUTH not enabled
11455 12:42:26.053790 # # RUN global.pac_instructions_not_nop ...
11456 12:42:26.056650 # # SKIP PAUTH not enabled
11457 12:42:26.060200 # # OK global.pac_instructions_not_nop
11458 12:42:26.063921 # ok 2 # SKIP PAUTH not enabled
11459 12:42:26.070469 # # RUN global.pac_instructions_not_nop_generic ...
11460 12:42:26.073459 # # SKIP Generic PAUTH not enabled
11461 12:42:26.076619 # # OK global.pac_instructions_not_nop_generic
11462 12:42:26.083281 # ok 3 # SKIP Generic PAUTH not enabled
11463 12:42:26.086405 # # RUN global.single_thread_different_keys ...
11464 12:42:26.089989 # # SKIP PAUTH not enabled
11465 12:42:26.096531 # # OK global.single_thread_different_keys
11466 12:42:26.096616 # ok 4 # SKIP PAUTH not enabled
11467 12:42:26.103289 # # RUN global.exec_changed_keys ...
11468 12:42:26.106104 # # SKIP PAUTH not enabled
11469 12:42:26.109838 # # OK global.exec_changed_keys
11470 12:42:26.113185 # ok 5 # SKIP PAUTH not enabled
11471 12:42:26.116048 # # RUN global.context_switch_keep_keys ...
11472 12:42:26.119681 # # SKIP PAUTH not enabled
11473 12:42:26.126584 # # OK global.context_switch_keep_keys
11474 12:42:26.126731 # ok 6 # SKIP PAUTH not enabled
11475 12:42:26.132852 # # RUN global.context_switch_keep_keys_generic ...
11476 12:42:26.136202 # # SKIP Generic PAUTH not enabled
11477 12:42:26.142729 # # OK global.context_switch_keep_keys_generic
11478 12:42:26.145924 # ok 7 # SKIP Generic PAUTH not enabled
11479 12:42:26.149067 # # PASSED: 7 / 7 tests passed.
11480 12:42:26.152696 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11481 12:42:26.156184 ok 28 selftests: arm64: pac
11482 12:42:26.159302 # selftests: arm64: fp-stress
11483 12:42:35.176360 <6>[ 46.154635] vpu: disabling
11484 12:42:35.179804 <6>[ 46.157691] vproc2: disabling
11485 12:42:35.183062 <6>[ 46.160966] vproc1: disabling
11486 12:42:35.189109 <6>[ 46.164248] vaud18: disabling
11487 12:42:35.193176 <6>[ 46.167680] vsram_others: disabling
11488 12:42:35.196070 <6>[ 46.171570] va09: disabling
11489 12:42:35.199233 <6>[ 46.174695] vsram_md: disabling
11490 12:42:35.202546 <6>[ 46.178193] Vgpu: disabling
11491 12:42:36.100648 # TAP version 13
11492 12:42:36.100800 # 1..16
11493 12:42:36.103795 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11494 12:42:36.107145 # # Will run for 10s
11495 12:42:36.107229 # # Started FPSIMD-0-0
11496 12:42:36.110653 # # Started FPSIMD-0-1
11497 12:42:36.113725 # # Started FPSIMD-1-0
11498 12:42:36.113810 # # Started FPSIMD-1-1
11499 12:42:36.117153 # # Started FPSIMD-2-0
11500 12:42:36.117239 # # Started FPSIMD-2-1
11501 12:42:36.120464 # # Started FPSIMD-3-0
11502 12:42:36.123549 # # Started FPSIMD-3-1
11503 12:42:36.123636 # # Started FPSIMD-4-0
11504 12:42:36.127023 # # Started FPSIMD-4-1
11505 12:42:36.130696 # # Started FPSIMD-5-0
11506 12:42:36.130814 # # Started FPSIMD-5-1
11507 12:42:36.133520 # # Started FPSIMD-6-0
11508 12:42:36.136936 # # Started FPSIMD-6-1
11509 12:42:36.137062 # # Started FPSIMD-7-0
11510 12:42:36.140081 # # Started FPSIMD-7-1
11511 12:42:36.143918 # # FPSIMD-0-1: Vector length: 128 bits
11512 12:42:36.147002 # # FPSIMD-0-1: PID: 1127
11513 12:42:36.150140 # # FPSIMD-0-0: Vector length: 128 bits
11514 12:42:36.150224 # # FPSIMD-0-0: PID: 1126
11515 12:42:36.153607 # # FPSIMD-1-0: Vector length: 128 bits
11516 12:42:36.156720 # # FPSIMD-1-0: PID: 1128
11517 12:42:36.160240 # # FPSIMD-3-0: Vector length: 128 bits
11518 12:42:36.163100 # # FPSIMD-3-0: PID: 1132
11519 12:42:36.166880 # # FPSIMD-2-1: Vector length: 128 bits
11520 12:42:36.170138 # # FPSIMD-2-1: PID: 1131
11521 12:42:36.173293 # # FPSIMD-4-0: Vector length: 128 bits
11522 12:42:36.176355 # # FPSIMD-4-0: PID: 1134
11523 12:42:36.179620 # # FPSIMD-3-1: Vector length: 128 bits
11524 12:42:36.179771 # # FPSIMD-3-1: PID: 1133
11525 12:42:36.183176 # # FPSIMD-2-0: Vector length: 128 bits
11526 12:42:36.186498 # # FPSIMD-2-0: PID: 1130
11527 12:42:36.190340 # # FPSIMD-1-1: Vector length: 128 bits
11528 12:42:36.192746 # # FPSIMD-1-1: PID: 1129
11529 12:42:36.196334 # # FPSIMD-6-0: Vector length: 128 bits
11530 12:42:36.199736 # # FPSIMD-6-0: PID: 1138
11531 12:42:36.202857 # # FPSIMD-7-1: Vector length: 128 bits
11532 12:42:36.206185 # # FPSIMD-5-0: Vector length: 128 bits
11533 12:42:36.209613 # # FPSIMD-5-0: PID: 1136
11534 12:42:36.209697 # # FPSIMD-7-1: PID: 1141
11535 12:42:36.212604 # # FPSIMD-4-1: Vector length: 128 bits
11536 12:42:36.216151 # # FPSIMD-4-1: PID: 1135
11537 12:42:36.219478 # # FPSIMD-5-1: Vector length: 128 bits
11538 12:42:36.222561 # # FPSIMD-5-1: PID: 1137
11539 12:42:36.226090 # # FPSIMD-7-0: Vector length: 128 bits
11540 12:42:36.229216 # # FPSIMD-7-0: PID: 1140
11541 12:42:36.232298 # # FPSIMD-6-1: Vector length: 128 bits
11542 12:42:36.232376 # # FPSIMD-6-1: PID: 1139
11543 12:42:36.235924 # # Finishing up...
11544 12:42:36.242236 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=774703, signals=10
11545 12:42:36.248800 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=1317769, signals=10
11546 12:42:36.255999 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=729413, signals=10
11547 12:42:36.265680 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=975428, signals=10
11548 12:42:36.272039 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=367896, signals=10
11549 12:42:36.278898 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=550318, signals=10
11550 12:42:36.285341 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=1392408, signals=10
11551 12:42:36.288460 # ok 1 FPSIMD-0-0
11552 12:42:36.288553 # ok 2 FPSIMD-0-1
11553 12:42:36.292338 # ok 3 FPSIMD-1-0
11554 12:42:36.292417 # ok 4 FPSIMD-1-1
11555 12:42:36.295069 # ok 5 FPSIMD-2-0
11556 12:42:36.295173 # ok 6 FPSIMD-2-1
11557 12:42:36.298836 # ok 7 FPSIMD-3-0
11558 12:42:36.298938 # ok 8 FPSIMD-3-1
11559 12:42:36.302181 # ok 9 FPSIMD-4-0
11560 12:42:36.302287 # ok 10 FPSIMD-4-1
11561 12:42:36.305652 # ok 11 FPSIMD-5-0
11562 12:42:36.305729 # ok 12 FPSIMD-5-1
11563 12:42:36.308392 # ok 13 FPSIMD-6-0
11564 12:42:36.308499 # ok 14 FPSIMD-6-1
11565 12:42:36.311609 # ok 15 FPSIMD-7-0
11566 12:42:36.311731 # ok 16 FPSIMD-7-1
11567 12:42:36.318198 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=589022, signals=9
11568 12:42:36.328230 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=1417135, signals=10
11569 12:42:36.335041 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=648373, signals=10
11570 12:42:36.341541 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=1071360, signals=9
11571 12:42:36.348060 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=578288, signals=9
11572 12:42:36.354663 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=449377, signals=10
11573 12:42:36.361221 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=952628, signals=10
11574 12:42:36.368077 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=570407, signals=10
11575 12:42:36.377993 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=375143, signals=9
11576 12:42:36.380892 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11577 12:42:36.384460 ok 29 selftests: arm64: fp-stress
11578 12:42:36.387793 # selftests: arm64: sve-ptrace
11579 12:42:36.387899 # TAP version 13
11580 12:42:36.390961 # 1..4104
11581 12:42:36.394708 # ok 2 # SKIP SVE not available
11582 12:42:36.397336 # # Planned tests != run tests (4104 != 1)
11583 12:42:36.401271 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11584 12:42:36.404328 ok 30 selftests: arm64: sve-ptrace # SKIP
11585 12:42:36.407678 # selftests: arm64: sve-probe-vls
11586 12:42:36.410900 # TAP version 13
11587 12:42:36.411003 # 1..2
11588 12:42:36.413902 # ok 2 # SKIP SVE not available
11589 12:42:36.417318 # # Planned tests != run tests (2 != 1)
11590 12:42:36.420618 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11591 12:42:36.427859 ok 31 selftests: arm64: sve-probe-vls # SKIP
11592 12:42:36.430810 # selftests: arm64: vec-syscfg
11593 12:42:36.430889 # TAP version 13
11594 12:42:36.430957 # 1..20
11595 12:42:36.433792 # ok 1 # SKIP SVE not supported
11596 12:42:36.436997 # ok 2 # SKIP SVE not supported
11597 12:42:36.440541 # ok 3 # SKIP SVE not supported
11598 12:42:36.443837 # ok 4 # SKIP SVE not supported
11599 12:42:36.446936 # ok 5 # SKIP SVE not supported
11600 12:42:36.447044 # ok 6 # SKIP SVE not supported
11601 12:42:36.450244 # ok 7 # SKIP SVE not supported
11602 12:42:36.453801 # ok 8 # SKIP SVE not supported
11603 12:42:36.456870 # ok 9 # SKIP SVE not supported
11604 12:42:36.460314 # ok 10 # SKIP SVE not supported
11605 12:42:36.463781 # ok 11 # SKIP SME not supported
11606 12:42:36.466629 # ok 12 # SKIP SME not supported
11607 12:42:36.470146 # ok 13 # SKIP SME not supported
11608 12:42:36.473239 # ok 14 # SKIP SME not supported
11609 12:42:36.473317 # ok 15 # SKIP SME not supported
11610 12:42:36.476736 # ok 16 # SKIP SME not supported
11611 12:42:36.480021 # ok 17 # SKIP SME not supported
11612 12:42:36.483446 # ok 18 # SKIP SME not supported
11613 12:42:36.486554 # ok 19 # SKIP SME not supported
11614 12:42:36.490361 # ok 20 # SKIP SME not supported
11615 12:42:36.493527 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11616 12:42:36.496347 ok 32 selftests: arm64: vec-syscfg
11617 12:42:36.499831 # selftests: arm64: za-fork
11618 12:42:36.503461 # TAP version 13
11619 12:42:36.503545 # 1..1
11620 12:42:36.503611 # # PID: 1212
11621 12:42:36.506607 # # SME support not present
11622 12:42:36.506679 # ok 0 skipped
11623 12:42:36.513498 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11624 12:42:36.516483 ok 33 selftests: arm64: za-fork
11625 12:42:36.519605 # selftests: arm64: za-ptrace
11626 12:42:36.519682 # TAP version 13
11627 12:42:36.519747 # 1..1
11628 12:42:36.522912 # ok 2 # SKIP SME not available
11629 12:42:36.529527 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11630 12:42:36.532882 ok 34 selftests: arm64: za-ptrace # SKIP
11631 12:42:36.536520 # selftests: arm64: check_buffer_fill
11632 12:42:36.539581 # # SKIP: MTE features unavailable
11633 12:42:36.542840 ok 35 selftests: arm64: check_buffer_fill # SKIP
11634 12:42:36.546400 # selftests: arm64: check_child_memory
11635 12:42:36.549704 # # SKIP: MTE features unavailable
11636 12:42:36.552880 ok 36 selftests: arm64: check_child_memory # SKIP
11637 12:42:36.556427 # selftests: arm64: check_gcr_el1_cswitch
11638 12:42:36.593525 # # SKIP: MTE features unavailable
11639 12:42:36.600855 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11640 12:42:36.613025 # selftests: arm64: check_ksm_options
11641 12:42:36.655371 # # SKIP: MTE features unavailable
11642 12:42:36.662139 ok 38 selftests: arm64: check_ksm_options # SKIP
11643 12:42:36.675540 # selftests: arm64: check_mmap_options
11644 12:42:36.717837 # # SKIP: MTE features unavailable
11645 12:42:36.724387 ok 39 selftests: arm64: check_mmap_options # SKIP
11646 12:42:36.732548 # selftests: arm64: check_prctl
11647 12:42:36.776789 # TAP version 13
11648 12:42:36.776961 # 1..5
11649 12:42:36.780227 # ok 1 check_basic_read
11650 12:42:36.780332 # ok 2 NONE
11651 12:42:36.783443 # ok 3 # SKIP SYNC
11652 12:42:36.783551 # ok 4 # SKIP ASYNC
11653 12:42:36.786609 # ok 5 # SKIP SYNC+ASYNC
11654 12:42:36.790227 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11655 12:42:36.793390 ok 40 selftests: arm64: check_prctl
11656 12:42:36.799811 # selftests: arm64: check_tags_inclusion
11657 12:42:36.836487 # # SKIP: MTE features unavailable
11658 12:42:36.843333 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11659 12:42:36.852816 # selftests: arm64: check_user_mem
11660 12:42:36.897942 # # SKIP: MTE features unavailable
11661 12:42:36.904506 ok 42 selftests: arm64: check_user_mem # SKIP
11662 12:42:36.913796 # selftests: arm64: btitest
11663 12:42:36.957494 # TAP version 13
11664 12:42:36.957627 # 1..18
11665 12:42:36.960836 # # HWCAP_PACA not present
11666 12:42:36.963913 # # HWCAP2_BTI not present
11667 12:42:36.964005 # # Test binary built for BTI
11668 12:42:36.970798 # ok 1 nohint_func/call_using_br_x0 # SKIP
11669 12:42:36.973692 # ok 1 nohint_func/call_using_br_x16 # SKIP
11670 12:42:36.977235 # ok 1 nohint_func/call_using_blr # SKIP
11671 12:42:36.980581 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11672 12:42:36.983878 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11673 12:42:36.990492 # ok 1 bti_none_func/call_using_blr # SKIP
11674 12:42:36.993704 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11675 12:42:36.996846 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11676 12:42:37.000351 # ok 1 bti_c_func/call_using_blr # SKIP
11677 12:42:37.003524 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11678 12:42:37.006849 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11679 12:42:37.010424 # ok 1 bti_j_func/call_using_blr # SKIP
11680 12:42:37.013368 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11681 12:42:37.019908 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11682 12:42:37.023150 # ok 1 bti_jc_func/call_using_blr # SKIP
11683 12:42:37.026453 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11684 12:42:37.029879 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11685 12:42:37.033140 # ok 1 paciasp_func/call_using_blr # SKIP
11686 12:42:37.039732 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11687 12:42:37.042876 # # WARNING - EXPECTED TEST COUNT WRONG
11688 12:42:37.046569 ok 43 selftests: arm64: btitest
11689 12:42:37.049515 # selftests: arm64: nobtitest
11690 12:42:37.049598 # TAP version 13
11691 12:42:37.049664 # 1..18
11692 12:42:37.053023 # # HWCAP_PACA not present
11693 12:42:37.056586 # # HWCAP2_BTI not present
11694 12:42:37.059700 # # Test binary not built for BTI
11695 12:42:37.063096 # ok 1 nohint_func/call_using_br_x0 # SKIP
11696 12:42:37.066650 # ok 1 nohint_func/call_using_br_x16 # SKIP
11697 12:42:37.069382 # ok 1 nohint_func/call_using_blr # SKIP
11698 12:42:37.073103 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11699 12:42:37.079824 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11700 12:42:37.082600 # ok 1 bti_none_func/call_using_blr # SKIP
11701 12:42:37.085926 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11702 12:42:37.089462 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11703 12:42:37.092933 # ok 1 bti_c_func/call_using_blr # SKIP
11704 12:42:37.095777 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11705 12:42:37.099124 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11706 12:42:37.102578 # ok 1 bti_j_func/call_using_blr # SKIP
11707 12:42:37.108902 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11708 12:42:37.112718 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11709 12:42:37.115813 # ok 1 bti_jc_func/call_using_blr # SKIP
11710 12:42:37.119215 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11711 12:42:37.122211 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11712 12:42:37.126097 # ok 1 paciasp_func/call_using_blr # SKIP
11713 12:42:37.132541 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11714 12:42:37.135731 # # WARNING - EXPECTED TEST COUNT WRONG
11715 12:42:37.138872 ok 44 selftests: arm64: nobtitest
11716 12:42:37.142355 # selftests: arm64: hwcap
11717 12:42:37.142455 # TAP version 13
11718 12:42:37.142547 # 1..28
11719 12:42:37.145498 # ok 1 cpuinfo_match_RNG
11720 12:42:37.148773 # # SIGILL reported for RNG
11721 12:42:37.151764 # ok 2 # SKIP sigill_RNG
11722 12:42:37.151875 # ok 3 cpuinfo_match_SME
11723 12:42:37.155267 # ok 4 sigill_SME
11724 12:42:37.155350 # ok 5 cpuinfo_match_SVE
11725 12:42:37.158612 # ok 6 sigill_SVE
11726 12:42:37.162256 # ok 7 cpuinfo_match_SVE 2
11727 12:42:37.162332 # # SIGILL reported for SVE 2
11728 12:42:37.164898 # ok 8 # SKIP sigill_SVE 2
11729 12:42:37.168255 # ok 9 cpuinfo_match_SVE AES
11730 12:42:37.172274 # # SIGILL reported for SVE AES
11731 12:42:37.174923 # ok 10 # SKIP sigill_SVE AES
11732 12:42:37.178419 # ok 11 cpuinfo_match_SVE2 PMULL
11733 12:42:37.178503 # # SIGILL reported for SVE2 PMULL
11734 12:42:37.181504 # ok 12 # SKIP sigill_SVE2 PMULL
11735 12:42:37.185117 # ok 13 cpuinfo_match_SVE2 BITPERM
11736 12:42:37.188318 # # SIGILL reported for SVE2 BITPERM
11737 12:42:37.191433 # ok 14 # SKIP sigill_SVE2 BITPERM
11738 12:42:37.194625 # ok 15 cpuinfo_match_SVE2 SHA3
11739 12:42:37.198414 # # SIGILL reported for SVE2 SHA3
11740 12:42:37.201446 # ok 16 # SKIP sigill_SVE2 SHA3
11741 12:42:37.204551 # ok 17 cpuinfo_match_SVE2 SM4
11742 12:42:37.207805 # # SIGILL reported for SVE2 SM4
11743 12:42:37.211603 # ok 18 # SKIP sigill_SVE2 SM4
11744 12:42:37.211683 # ok 19 cpuinfo_match_SVE2 I8MM
11745 12:42:37.214524 # # SIGILL reported for SVE2 I8MM
11746 12:42:37.217713 # ok 20 # SKIP sigill_SVE2 I8MM
11747 12:42:37.221705 # ok 21 cpuinfo_match_SVE2 F32MM
11748 12:42:37.224625 # # SIGILL reported for SVE2 F32MM
11749 12:42:37.227536 # ok 22 # SKIP sigill_SVE2 F32MM
11750 12:42:37.230873 # ok 23 cpuinfo_match_SVE2 F64MM
11751 12:42:37.234222 # # SIGILL reported for SVE2 F64MM
11752 12:42:37.237827 # ok 24 # SKIP sigill_SVE2 F64MM
11753 12:42:37.237911 # ok 25 cpuinfo_match_SVE2 BF16
11754 12:42:37.241132 # # SIGILL reported for SVE2 BF16
11755 12:42:37.244284 # ok 26 # SKIP sigill_SVE2 BF16
11756 12:42:37.247715 # ok 27 cpuinfo_match_SVE2 EBF16
11757 12:42:37.251024 # ok 28 # SKIP sigill_SVE2 EBF16
11758 12:42:37.257525 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11759 12:42:37.257610 ok 45 selftests: arm64: hwcap
11760 12:42:37.260808 # selftests: arm64: ptrace
11761 12:42:37.264645 # TAP version 13
11762 12:42:37.264735 # 1..7
11763 12:42:37.267486 # # Parent is 1441, child is 1442
11764 12:42:37.267568 # ok 1 read_tpidr_one
11765 12:42:37.270568 # ok 2 write_tpidr_one
11766 12:42:37.273878 # ok 3 verify_tpidr_one
11767 12:42:37.273985 # ok 4 count_tpidrs
11768 12:42:37.277194 # ok 5 tpidr2_write
11769 12:42:37.277313 # ok 6 tpidr2_read
11770 12:42:37.280576 # ok 7 write_tpidr_only
11771 12:42:37.287411 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11772 12:42:37.287504 ok 46 selftests: arm64: ptrace
11773 12:42:37.290333 # selftests: arm64: syscall-abi
11774 12:42:37.294005 # TAP version 13
11775 12:42:37.294088 # 1..2
11776 12:42:37.296898 # ok 1 getpid() FPSIMD
11777 12:42:37.297003 # ok 2 sched_yield() FPSIMD
11778 12:42:37.303769 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11779 12:42:37.306756 ok 47 selftests: arm64: syscall-abi
11780 12:42:37.310390 # selftests: arm64: tpidr2
11781 12:42:37.310504 # TAP version 13
11782 12:42:37.310595 # 1..5
11783 12:42:37.313710 # # PID: 1476
11784 12:42:37.313792 # # SME support not present
11785 12:42:37.317224 # ok 0 skipped, TPIDR2 not supported
11786 12:42:37.320327 # ok 1 skipped, TPIDR2 not supported
11787 12:42:37.323595 # ok 2 skipped, TPIDR2 not supported
11788 12:42:37.326641 # ok 3 skipped, TPIDR2 not supported
11789 12:42:37.330189 # ok 4 skipped, TPIDR2 not supported
11790 12:42:37.336631 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11791 12:42:37.339825 ok 48 selftests: arm64: tpidr2
11792 12:42:37.764355 arm64_tags_test pass
11793 12:42:37.767571 arm64_run_tags_test_sh pass
11794 12:42:37.770620 arm64_fake_sigreturn_bad_magic pass
11795 12:42:37.773742 arm64_fake_sigreturn_bad_size pass
11796 12:42:37.777244 arm64_fake_sigreturn_bad_size_for_magic0 pass
11797 12:42:37.780523 arm64_fake_sigreturn_duplicated_fpsimd pass
11798 12:42:37.783694 arm64_fake_sigreturn_misaligned_sp pass
11799 12:42:37.787067 arm64_fake_sigreturn_missing_fpsimd pass
11800 12:42:37.790306 arm64_fake_sigreturn_sme_change_vl skip
11801 12:42:37.796845 arm64_fake_sigreturn_sve_change_vl skip
11802 12:42:37.800141 arm64_mangle_pstate_invalid_compat_toggle pass
11803 12:42:37.803639 arm64_mangle_pstate_invalid_daif_bits pass
11804 12:42:37.806974 arm64_mangle_pstate_invalid_mode_el1h pass
11805 12:42:37.810090 arm64_mangle_pstate_invalid_mode_el1t pass
11806 12:42:37.813101 arm64_mangle_pstate_invalid_mode_el2h pass
11807 12:42:37.820173 arm64_mangle_pstate_invalid_mode_el2t pass
11808 12:42:37.823279 arm64_mangle_pstate_invalid_mode_el3h pass
11809 12:42:37.826609 arm64_mangle_pstate_invalid_mode_el3t pass
11810 12:42:37.829962 arm64_sme_trap_no_sm skip
11811 12:42:37.832908 arm64_sme_trap_non_streaming skip
11812 12:42:37.833033 arm64_sme_trap_za pass
11813 12:42:37.836267 arm64_sme_vl skip
11814 12:42:37.836345 arm64_ssve_regs skip
11815 12:42:37.839671 arm64_sve_regs skip
11816 12:42:37.839780 arm64_sve_vl skip
11817 12:42:37.842681 arm64_za_no_regs skip
11818 12:42:37.846329 arm64_za_regs skip
11819 12:42:37.846441 arm64_pac_PAUTH_not_enabled skip
11820 12:42:37.849285 arm64_pac_PAUTH_not_enabled skip
11821 12:42:37.853104 arm64_pac_Generic_PAUTH_not_enabled skip
11822 12:42:37.856587 arm64_pac_PAUTH_not_enabled skip
11823 12:42:37.859267 arm64_pac_PAUTH_not_enabled skip
11824 12:42:37.862559 arm64_pac_PAUTH_not_enabled skip
11825 12:42:37.865862 arm64_pac_Generic_PAUTH_not_enabled skip
11826 12:42:37.869311 arm64_pac pass
11827 12:42:37.872432 arm64_fp-stress_FPSIMD-0-0 pass
11828 12:42:37.872546 arm64_fp-stress_FPSIMD-0-1 pass
11829 12:42:37.875934 arm64_fp-stress_FPSIMD-1-0 pass
11830 12:42:37.878913 arm64_fp-stress_FPSIMD-1-1 pass
11831 12:42:37.882389 arm64_fp-stress_FPSIMD-2-0 pass
11832 12:42:37.885506 arm64_fp-stress_FPSIMD-2-1 pass
11833 12:42:37.888926 arm64_fp-stress_FPSIMD-3-0 pass
11834 12:42:37.892244 arm64_fp-stress_FPSIMD-3-1 pass
11835 12:42:37.892386 arm64_fp-stress_FPSIMD-4-0 pass
11836 12:42:37.895593 arm64_fp-stress_FPSIMD-4-1 pass
11837 12:42:37.898996 arm64_fp-stress_FPSIMD-5-0 pass
11838 12:42:37.902058 arm64_fp-stress_FPSIMD-5-1 pass
11839 12:42:37.905448 arm64_fp-stress_FPSIMD-6-0 pass
11840 12:42:37.908628 arm64_fp-stress_FPSIMD-6-1 pass
11841 12:42:37.911844 arm64_fp-stress_FPSIMD-7-0 pass
11842 12:42:37.915514 arm64_fp-stress_FPSIMD-7-1 pass
11843 12:42:37.915595 arm64_fp-stress pass
11844 12:42:37.919143 arm64_sve-ptrace_SVE_not_available skip
11845 12:42:37.921675 arm64_sve-ptrace skip
11846 12:42:37.925310 arm64_sve-probe-vls_SVE_not_available skip
11847 12:42:37.928452 arm64_sve-probe-vls skip
11848 12:42:37.931753 arm64_vec-syscfg_SVE_not_supported skip
11849 12:42:37.935108 arm64_vec-syscfg_SVE_not_supported skip
11850 12:42:37.938596 arm64_vec-syscfg_SVE_not_supported skip
11851 12:42:37.941785 arm64_vec-syscfg_SVE_not_supported skip
11852 12:42:37.945254 arm64_vec-syscfg_SVE_not_supported skip
11853 12:42:37.948625 arm64_vec-syscfg_SVE_not_supported skip
11854 12:42:37.951897 arm64_vec-syscfg_SVE_not_supported skip
11855 12:42:37.955190 arm64_vec-syscfg_SVE_not_supported skip
11856 12:42:37.958557 arm64_vec-syscfg_SVE_not_supported skip
11857 12:42:37.961882 arm64_vec-syscfg_SVE_not_supported skip
11858 12:42:37.964814 arm64_vec-syscfg_SME_not_supported skip
11859 12:42:37.971572 arm64_vec-syscfg_SME_not_supported skip
11860 12:42:37.974765 arm64_vec-syscfg_SME_not_supported skip
11861 12:42:37.978088 arm64_vec-syscfg_SME_not_supported skip
11862 12:42:37.981546 arm64_vec-syscfg_SME_not_supported skip
11863 12:42:37.984688 arm64_vec-syscfg_SME_not_supported skip
11864 12:42:37.988235 arm64_vec-syscfg_SME_not_supported skip
11865 12:42:37.991344 arm64_vec-syscfg_SME_not_supported skip
11866 12:42:37.994800 arm64_vec-syscfg_SME_not_supported skip
11867 12:42:37.997951 arm64_vec-syscfg_SME_not_supported skip
11868 12:42:38.001499 arm64_vec-syscfg pass
11869 12:42:38.004345 arm64_za-fork_skipped pass
11870 12:42:38.004454 arm64_za-fork pass
11871 12:42:38.007848 arm64_za-ptrace_SME_not_available skip
11872 12:42:38.011296 arm64_za-ptrace skip
11873 12:42:38.011396 arm64_check_buffer_fill skip
11874 12:42:38.014507 arm64_check_child_memory skip
11875 12:42:38.017672 arm64_check_gcr_el1_cswitch skip
11876 12:42:38.021173 arm64_check_ksm_options skip
11877 12:42:38.024490 arm64_check_mmap_options skip
11878 12:42:38.027610 arm64_check_prctl_check_basic_read pass
11879 12:42:38.030790 arm64_check_prctl_NONE pass
11880 12:42:38.030880 arm64_check_prctl_SYNC skip
11881 12:42:38.034641 arm64_check_prctl_ASYNC skip
11882 12:42:38.037630 arm64_check_prctl_SYNC_ASYNC skip
11883 12:42:38.041446 arm64_check_prctl pass
11884 12:42:38.044236 arm64_check_tags_inclusion skip
11885 12:42:38.044319 arm64_check_user_mem skip
11886 12:42:38.051081 arm64_btitest_nohint_func_call_using_br_x0 skip
11887 12:42:38.053916 arm64_btitest_nohint_func_call_using_br_x16 skip
11888 12:42:38.057362 arm64_btitest_nohint_func_call_using_blr skip
11889 12:42:38.060536 arm64_btitest_bti_none_func_call_using_br_x0 skip
11890 12:42:38.067311 arm64_btitest_bti_none_func_call_using_br_x16 skip
11891 12:42:38.070440 arm64_btitest_bti_none_func_call_using_blr skip
11892 12:42:38.073851 arm64_btitest_bti_c_func_call_using_br_x0 skip
11893 12:42:38.080241 arm64_btitest_bti_c_func_call_using_br_x16 skip
11894 12:42:38.083702 arm64_btitest_bti_c_func_call_using_blr skip
11895 12:42:38.087245 arm64_btitest_bti_j_func_call_using_br_x0 skip
11896 12:42:38.090744 arm64_btitest_bti_j_func_call_using_br_x16 skip
11897 12:42:38.096967 arm64_btitest_bti_j_func_call_using_blr skip
11898 12:42:38.100184 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11899 12:42:38.103519 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11900 12:42:38.106914 arm64_btitest_bti_jc_func_call_using_blr skip
11901 12:42:38.113639 arm64_btitest_paciasp_func_call_using_br_x0 skip
11902 12:42:38.117111 arm64_btitest_paciasp_func_call_using_br_x16 skip
11903 12:42:38.120229 arm64_btitest_paciasp_func_call_using_blr skip
11904 12:42:38.123721 arm64_btitest pass
11905 12:42:38.126826 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11906 12:42:38.133172 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11907 12:42:38.136666 arm64_nobtitest_nohint_func_call_using_blr skip
11908 12:42:38.139940 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11909 12:42:38.146662 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11910 12:42:38.150057 arm64_nobtitest_bti_none_func_call_using_blr skip
11911 12:42:38.153038 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11912 12:42:38.160004 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11913 12:42:38.163509 arm64_nobtitest_bti_c_func_call_using_blr skip
11914 12:42:38.166275 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11915 12:42:38.173301 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11916 12:42:38.176452 arm64_nobtitest_bti_j_func_call_using_blr skip
11917 12:42:38.179842 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11918 12:42:38.186135 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11919 12:42:38.189930 arm64_nobtitest_bti_jc_func_call_using_blr skip
11920 12:42:38.192784 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11921 12:42:38.199511 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11922 12:42:38.202819 arm64_nobtitest_paciasp_func_call_using_blr skip
11923 12:42:38.206012 arm64_nobtitest pass
11924 12:42:38.206121 arm64_hwcap_cpuinfo_match_RNG pass
11925 12:42:38.209445 arm64_hwcap_sigill_RNG skip
11926 12:42:38.212580 arm64_hwcap_cpuinfo_match_SME pass
11927 12:42:38.215905 arm64_hwcap_sigill_SME pass
11928 12:42:38.219106 arm64_hwcap_cpuinfo_match_SVE pass
11929 12:42:38.222754 arm64_hwcap_sigill_SVE pass
11930 12:42:38.225871 arm64_hwcap_cpuinfo_match_SVE_2 pass
11931 12:42:38.225959 arm64_hwcap_sigill_SVE_2 skip
11932 12:42:38.232290 arm64_hwcap_cpuinfo_match_SVE_AES pass
11933 12:42:38.232392 arm64_hwcap_sigill_SVE_AES skip
11934 12:42:38.238998 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11935 12:42:38.239075 arm64_hwcap_sigill_SVE2_PMULL skip
11936 12:42:38.245633 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11937 12:42:38.249943 arm64_hwcap_sigill_SVE2_BITPERM skip
11938 12:42:38.252278 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11939 12:42:38.255450 arm64_hwcap_sigill_SVE2_SHA3 skip
11940 12:42:38.259152 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11941 12:42:38.262142 arm64_hwcap_sigill_SVE2_SM4 skip
11942 12:42:38.265259 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11943 12:42:38.268620 arm64_hwcap_sigill_SVE2_I8MM skip
11944 12:42:38.272277 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11945 12:42:38.275161 arm64_hwcap_sigill_SVE2_F32MM skip
11946 12:42:38.278697 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11947 12:42:38.282163 arm64_hwcap_sigill_SVE2_F64MM skip
11948 12:42:38.285392 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
11949 12:42:38.288287 arm64_hwcap_sigill_SVE2_BF16 skip
11950 12:42:38.291740 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
11951 12:42:38.294945 arm64_hwcap_sigill_SVE2_EBF16 skip
11952 12:42:38.295047 arm64_hwcap pass
11953 12:42:38.298405 arm64_ptrace_read_tpidr_one pass
11954 12:42:38.301993 arm64_ptrace_write_tpidr_one pass
11955 12:42:38.305361 arm64_ptrace_verify_tpidr_one pass
11956 12:42:38.308264 arm64_ptrace_count_tpidrs pass
11957 12:42:38.311707 arm64_ptrace_tpidr2_write pass
11958 12:42:38.314875 arm64_ptrace_tpidr2_read pass
11959 12:42:38.318711 arm64_ptrace_write_tpidr_only pass
11960 12:42:38.318786 arm64_ptrace pass
11961 12:42:38.321579 arm64_syscall-abi_getpid_FPSIMD pass
11962 12:42:38.324925 arm64_syscall-abi_sched_yield_FPSIMD pass
11963 12:42:38.328162 arm64_syscall-abi pass
11964 12:42:38.331760 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11965 12:42:38.334654 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11966 12:42:38.341191 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11967 12:42:38.344984 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11968 12:42:38.347969 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11969 12:42:38.351430 arm64_tpidr2 pass
11970 12:42:38.354654 + ../../utils/send-to-lava.sh ./output/result.txt
11971 12:42:38.360933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
11972 12:42:38.361257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
11974 12:42:38.367838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
11975 12:42:38.368094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
11977 12:42:38.374239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
11978 12:42:38.374526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
11980 12:42:38.380989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
11981 12:42:38.381275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
11983 12:42:38.387811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
11984 12:42:38.388117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
11986 12:42:38.394219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
11987 12:42:38.394545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
11989 12:42:38.404112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
11990 12:42:38.404365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
11992 12:42:38.410504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
11993 12:42:38.410781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
11995 12:42:38.430137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
11996 12:42:38.430400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
11998 12:42:38.463381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
11999 12:42:38.463691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
12001 12:42:38.495911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
12002 12:42:38.496242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
12004 12:42:38.528382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
12005 12:42:38.528692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
12007 12:42:38.562403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
12008 12:42:38.562704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
12010 12:42:38.600169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
12011 12:42:38.600482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
12013 12:42:38.633495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
12014 12:42:38.633816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
12016 12:42:38.666658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
12017 12:42:38.667006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
12019 12:42:38.698485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
12020 12:42:38.698827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
12022 12:42:38.734519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
12023 12:42:38.734837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
12025 12:42:38.763412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
12026 12:42:38.763760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
12028 12:42:38.795017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
12030 12:42:38.798473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
12031 12:42:38.829679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
12032 12:42:38.829988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
12034 12:42:38.863878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
12035 12:42:38.864201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
12037 12:42:38.895146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
12038 12:42:38.895494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
12040 12:42:38.925854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
12041 12:42:38.926210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
12043 12:42:38.954539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
12044 12:42:38.954894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
12046 12:42:38.985171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
12047 12:42:38.985542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
12049 12:42:39.018775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
12050 12:42:39.019101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
12052 12:42:39.054126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12054 12:42:39.057005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12055 12:42:39.083754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12057 12:42:39.086794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12058 12:42:39.119317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
12059 12:42:39.119679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
12061 12:42:39.147609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12063 12:42:39.150357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12064 12:42:39.182115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12066 12:42:39.185019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12067 12:42:39.220419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12069 12:42:39.223637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12070 12:42:39.253659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
12071 12:42:39.253983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
12073 12:42:39.281498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
12074 12:42:39.281839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
12076 12:42:39.307798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
12077 12:42:39.308155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
12079 12:42:39.334563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
12080 12:42:39.334921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
12082 12:42:39.364294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
12083 12:42:39.364643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
12085 12:42:39.396872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
12086 12:42:39.397252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
12088 12:42:39.430295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
12089 12:42:39.430645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
12091 12:42:39.464402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
12092 12:42:39.464720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
12094 12:42:39.497493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
12095 12:42:39.497810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
12097 12:42:39.529384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
12098 12:42:39.529685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12100 12:42:39.562564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12101 12:42:39.562904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12103 12:42:39.593503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12104 12:42:39.593833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12106 12:42:39.622658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12107 12:42:39.622968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12109 12:42:39.653230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12110 12:42:39.653525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12112 12:42:39.683619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12113 12:42:39.683945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12115 12:42:39.711608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12116 12:42:39.711934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12118 12:42:39.743797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12119 12:42:39.744114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12121 12:42:39.774754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12122 12:42:39.775054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12124 12:42:39.808222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12125 12:42:39.808588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12127 12:42:39.841955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip>
12128 12:42:39.842249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip
12130 12:42:39.868238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12131 12:42:39.868523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12133 12:42:39.901931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip>
12134 12:42:39.902243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip
12136 12:42:39.926450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12137 12:42:39.926729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12139 12:42:39.957160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12140 12:42:39.957453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12142 12:42:39.986242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12143 12:42:39.986584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12145 12:42:40.015787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12146 12:42:40.016139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12148 12:42:40.046630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12149 12:42:40.046959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12151 12:42:40.080782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12152 12:42:40.081088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12154 12:42:40.110098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12155 12:42:40.110449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12157 12:42:40.140218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12158 12:42:40.140520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12160 12:42:40.171063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12161 12:42:40.171348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12163 12:42:40.201191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12164 12:42:40.201493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12166 12:42:40.228039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12167 12:42:40.228328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12169 12:42:40.256749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12170 12:42:40.257057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12172 12:42:40.284906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12173 12:42:40.285210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12175 12:42:40.313558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12176 12:42:40.313879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12178 12:42:40.342028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12179 12:42:40.342314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12181 12:42:40.369943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12182 12:42:40.370223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12184 12:42:40.400957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12185 12:42:40.401291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12187 12:42:40.428304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12188 12:42:40.428589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12190 12:42:40.457928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12191 12:42:40.458221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12193 12:42:40.488278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12194 12:42:40.488557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12196 12:42:40.524375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12197 12:42:40.524713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12199 12:42:40.564386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12200 12:42:40.564706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12202 12:42:40.598289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12203 12:42:40.598573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12205 12:42:40.633633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12206 12:42:40.633899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12208 12:42:40.672125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip>
12209 12:42:40.672413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip
12211 12:42:40.701937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12212 12:42:40.702210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12214 12:42:40.730564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12215 12:42:40.730835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12217 12:42:40.758593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12218 12:42:40.758920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12220 12:42:40.787445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12222 12:42:40.790570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12223 12:42:40.814189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12224 12:42:40.814451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12226 12:42:40.846388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12227 12:42:40.846667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12229 12:42:40.880766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12230 12:42:40.881050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12232 12:42:40.911305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12233 12:42:40.911591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12235 12:42:40.941694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip>
12236 12:42:40.942008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip
12238 12:42:40.974626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip>
12239 12:42:40.974897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip
12241 12:42:41.006335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip
12243 12:42:41.009176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip>
12244 12:42:41.035735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12245 12:42:41.036000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12247 12:42:41.062971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12248 12:42:41.063265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12250 12:42:41.090527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12251 12:42:41.090811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12253 12:42:41.126075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12254 12:42:41.126363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12256 12:42:41.156704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12257 12:42:41.156956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12259 12:42:41.184930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12260 12:42:41.185214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12262 12:42:41.215271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12263 12:42:41.215573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12265 12:42:41.247512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12266 12:42:41.247769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12268 12:42:41.281865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12269 12:42:41.282132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12271 12:42:41.312071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12272 12:42:41.312341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12274 12:42:41.340843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12275 12:42:41.341123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12277 12:42:41.371789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12278 12:42:41.372045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12280 12:42:41.403426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12281 12:42:41.403686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12283 12:42:41.437927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12284 12:42:41.438185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12286 12:42:41.467997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12287 12:42:41.468284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12289 12:42:41.498459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12290 12:42:41.498716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12292 12:42:41.530195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12293 12:42:41.530523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12295 12:42:41.558289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12296 12:42:41.558542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12298 12:42:41.593183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12299 12:42:41.593442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12301 12:42:41.626454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12302 12:42:41.626708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12304 12:42:41.654592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12305 12:42:41.654863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12307 12:42:41.680139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12308 12:42:41.680404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12310 12:42:41.714863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12311 12:42:41.715126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12313 12:42:41.749398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12314 12:42:41.749655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12316 12:42:41.780444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12317 12:42:41.780698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12319 12:42:41.814126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12320 12:42:41.814387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12322 12:42:41.845175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12323 12:42:41.845453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12325 12:42:41.875732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12326 12:42:41.875990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12328 12:42:41.911303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12329 12:42:41.911562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12331 12:42:41.948188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12332 12:42:41.948442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12334 12:42:41.984128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12335 12:42:41.984387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12337 12:42:42.021779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12338 12:42:42.022045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12340 12:42:42.056728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12341 12:42:42.057013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12343 12:42:42.088411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12344 12:42:42.088667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12346 12:42:42.121266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12347 12:42:42.121527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12349 12:42:42.153782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12350 12:42:42.154035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12352 12:42:42.188431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12353 12:42:42.188689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12355 12:42:42.222210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12356 12:42:42.222474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12358 12:42:42.260669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12359 12:42:42.260922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12361 12:42:42.297610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12362 12:42:42.297900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12364 12:42:42.326933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12365 12:42:42.327205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12367 12:42:42.361639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12368 12:42:42.361947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12370 12:42:42.392524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip>
12371 12:42:42.392830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip
12373 12:42:42.430383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12374 12:42:42.430691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12376 12:42:42.465076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12377 12:42:42.465394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12379 12:42:42.502958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12380 12:42:42.503261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12382 12:42:42.537272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12383 12:42:42.537573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12385 12:42:42.572319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12386 12:42:42.572604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12388 12:42:42.600510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip>
12389 12:42:42.600814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip
12391 12:42:42.635047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12392 12:42:42.635375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12394 12:42:42.664737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip>
12395 12:42:42.665014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip
12397 12:42:42.699380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12398 12:42:42.699701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12400 12:42:42.799576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip>
12401 12:42:42.799899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip
12403 12:42:42.959229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12404 12:42:42.959561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12406 12:42:43.088265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip>
12407 12:42:43.088625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip
12409 12:42:43.120783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12410 12:42:43.121125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12412 12:42:43.254158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip
12414 12:42:43.257001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip>
12415 12:42:43.294212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12416 12:42:43.294627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12418 12:42:43.319467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip
12420 12:42:43.322777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip>
12421 12:42:43.353246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12422 12:42:43.353591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12424 12:42:43.378965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip
12426 12:42:43.381999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip>
12427 12:42:43.409235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12428 12:42:43.409564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12430 12:42:43.436660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip>
12431 12:42:43.437002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip
12433 12:42:43.473881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12434 12:42:43.474256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12436 12:42:43.504288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip>
12437 12:42:43.504652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip
12439 12:42:43.535898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12440 12:42:43.536287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12442 12:42:43.563648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip
12444 12:42:43.566644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip>
12445 12:42:43.599009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12446 12:42:43.599360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12448 12:42:43.629649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
12449 12:42:43.630025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
12451 12:42:43.655968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12452 12:42:43.656309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12454 12:42:43.684623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12456 12:42:43.687666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12457 12:42:43.714912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12459 12:42:43.717721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12460 12:42:43.746340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12461 12:42:43.746691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12463 12:42:43.772017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12464 12:42:43.772350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12466 12:42:43.802045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12467 12:42:43.802382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12469 12:42:43.832075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12470 12:42:43.832403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12472 12:42:43.866927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12473 12:42:43.867254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12475 12:42:43.894128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12476 12:42:43.894488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12478 12:42:43.928434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12479 12:42:43.928760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12481 12:42:43.959565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12482 12:42:43.959899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12484 12:42:43.986745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12485 12:42:43.987103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12487 12:42:44.020659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12488 12:42:44.020989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12490 12:42:44.049324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12491 12:42:44.049633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12493 12:42:44.077581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12494 12:42:44.077939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12496 12:42:44.113220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12497 12:42:44.113555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12499 12:42:44.142706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12500 12:42:44.143031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12502 12:42:44.168856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12503 12:42:44.169017 + set +x
12504 12:42:44.169263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12506 12:42:44.175669 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 10724840_1.6.2.3.5>
12507 12:42:44.176013 Received signal: <ENDRUN> 1_kselftest-arm64 10724840_1.6.2.3.5
12508 12:42:44.176100 Ending use of test pattern.
12509 12:42:44.176165 Ending test lava.1_kselftest-arm64 (10724840_1.6.2.3.5), duration 26.86
12511 12:42:44.178906 <LAVA_TEST_RUNNER EXIT>
12512 12:42:44.179176 ok: lava_test_shell seems to have completed
12513 12:42:44.180224 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: skip
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: skip
arm64_check_prctl_SYNC_ASYNC: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: skip
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: skip
arm64_hwcap_sigill_SVE2_BITPERM: skip
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: skip
arm64_hwcap_sigill_SVE2_F64MM: skip
arm64_hwcap_sigill_SVE2_I8MM: skip
arm64_hwcap_sigill_SVE2_PMULL: skip
arm64_hwcap_sigill_SVE2_SHA3: skip
arm64_hwcap_sigill_SVE2_SM4: skip
arm64_hwcap_sigill_SVE_2: skip
arm64_hwcap_sigill_SVE_AES: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_Generic_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_SVE_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_SVE_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_not_supported: skip
arm64_vec-syscfg_SVE_not_supported: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_SME_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
12514 12:42:44.180385 end: 3.1 lava-test-shell (duration 00:00:28) [common]
12515 12:42:44.180478 end: 3 lava-test-retry (duration 00:00:28) [common]
12516 12:42:44.180575 start: 4 finalize (timeout 00:07:28) [common]
12517 12:42:44.180668 start: 4.1 power-off (timeout 00:00:30) [common]
12518 12:42:44.180824 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
12519 12:42:44.260385 >> Command sent successfully.
12520 12:42:44.262707 Returned 0 in 0 seconds
12521 12:42:44.363072 end: 4.1 power-off (duration 00:00:00) [common]
12523 12:42:44.363415 start: 4.2 read-feedback (timeout 00:07:28) [common]
12524 12:42:44.363671 Listened to connection for namespace 'common' for up to 1s
12525 12:42:45.364607 Finalising connection for namespace 'common'
12526 12:42:45.364821 Disconnecting from shell: Finalise
12527 12:42:45.364956 / #
12528 12:42:45.465350 end: 4.2 read-feedback (duration 00:00:01) [common]
12529 12:42:45.465573 end: 4 finalize (duration 00:00:01) [common]
12530 12:42:45.465734 Cleaning after the job
12531 12:42:45.465872 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724840/tftp-deploy-os1kguat/ramdisk
12532 12:42:45.467894 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724840/tftp-deploy-os1kguat/kernel
12533 12:42:45.476890 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724840/tftp-deploy-os1kguat/dtb
12534 12:42:45.477118 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724840/tftp-deploy-os1kguat/nfsrootfs
12535 12:42:45.542481 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724840/tftp-deploy-os1kguat/modules
12536 12:42:45.547556 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10724840
12537 12:42:46.087526 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10724840
12538 12:42:46.087707 Job finished correctly