Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 39
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 29
- Errors: 0
1 12:43:11.340246 lava-dispatcher, installed at version: 2023.05.1
2 12:43:11.340436 start: 0 validate
3 12:43:11.340559 Start time: 2023-06-14 12:43:11.340552+00:00 (UTC)
4 12:43:11.340672 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:43:11.340796 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230609.0%2Farm64%2Finitrd.cpio.gz exists
6 12:43:11.610877 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:43:11.611704 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:43:11.884020 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:43:11.884818 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:43:12.156331 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:43:12.157094 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230609.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:43:12.420625 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:43:12.421324 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:43:12.698213 validate duration: 1.36
16 12:43:12.699505 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:43:12.700042 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:43:12.700543 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:43:12.701150 Not decompressing ramdisk as can be used compressed.
20 12:43:12.701650 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230609.0/arm64/initrd.cpio.gz
21 12:43:12.702014 saving as /var/lib/lava/dispatcher/tmp/10724879/tftp-deploy-49u57mqi/ramdisk/initrd.cpio.gz
22 12:43:12.702359 total size: 4665397 (4MB)
23 12:43:12.707512 progress 0% (0MB)
24 12:43:12.715503 progress 5% (0MB)
25 12:43:12.721840 progress 10% (0MB)
26 12:43:12.726305 progress 15% (0MB)
27 12:43:12.729828 progress 20% (0MB)
28 12:43:12.732820 progress 25% (1MB)
29 12:43:12.735582 progress 30% (1MB)
30 12:43:12.737877 progress 35% (1MB)
31 12:43:12.740189 progress 40% (1MB)
32 12:43:12.742445 progress 45% (2MB)
33 12:43:12.744422 progress 50% (2MB)
34 12:43:12.746321 progress 55% (2MB)
35 12:43:12.748065 progress 60% (2MB)
36 12:43:12.749783 progress 65% (2MB)
37 12:43:12.751452 progress 70% (3MB)
38 12:43:12.752987 progress 75% (3MB)
39 12:43:12.754516 progress 80% (3MB)
40 12:43:12.756178 progress 85% (3MB)
41 12:43:12.757552 progress 90% (4MB)
42 12:43:12.758939 progress 95% (4MB)
43 12:43:12.760340 progress 100% (4MB)
44 12:43:12.760500 4MB downloaded in 0.06s (76.52MB/s)
45 12:43:12.760652 end: 1.1.1 http-download (duration 00:00:00) [common]
47 12:43:12.760896 end: 1.1 download-retry (duration 00:00:00) [common]
48 12:43:12.760985 start: 1.2 download-retry (timeout 00:10:00) [common]
49 12:43:12.761072 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 12:43:12.761201 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:43:12.761280 saving as /var/lib/lava/dispatcher/tmp/10724879/tftp-deploy-49u57mqi/kernel/Image
52 12:43:12.761343 total size: 47581696 (45MB)
53 12:43:12.761404 No compression specified
54 12:43:12.762538 progress 0% (0MB)
55 12:43:12.774620 progress 5% (2MB)
56 12:43:12.786614 progress 10% (4MB)
57 12:43:12.798415 progress 15% (6MB)
58 12:43:12.810167 progress 20% (9MB)
59 12:43:12.822013 progress 25% (11MB)
60 12:43:12.833708 progress 30% (13MB)
61 12:43:12.845651 progress 35% (15MB)
62 12:43:12.857417 progress 40% (18MB)
63 12:43:12.869230 progress 45% (20MB)
64 12:43:12.881099 progress 50% (22MB)
65 12:43:12.892709 progress 55% (24MB)
66 12:43:12.904615 progress 60% (27MB)
67 12:43:12.916266 progress 65% (29MB)
68 12:43:12.928122 progress 70% (31MB)
69 12:43:12.939967 progress 75% (34MB)
70 12:43:12.951641 progress 80% (36MB)
71 12:43:12.963429 progress 85% (38MB)
72 12:43:12.975178 progress 90% (40MB)
73 12:43:12.986823 progress 95% (43MB)
74 12:43:12.999662 progress 100% (45MB)
75 12:43:12.999784 45MB downloaded in 0.24s (190.31MB/s)
76 12:43:12.999926 end: 1.2.1 http-download (duration 00:00:00) [common]
78 12:43:13.000155 end: 1.2 download-retry (duration 00:00:00) [common]
79 12:43:13.000243 start: 1.3 download-retry (timeout 00:10:00) [common]
80 12:43:13.000371 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 12:43:13.000534 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:43:13.000613 saving as /var/lib/lava/dispatcher/tmp/10724879/tftp-deploy-49u57mqi/dtb/mt8192-asurada-spherion-r0.dtb
83 12:43:13.000675 total size: 46924 (0MB)
84 12:43:13.000734 No compression specified
85 12:43:13.001821 progress 69% (0MB)
86 12:43:13.002083 progress 100% (0MB)
87 12:43:13.002231 0MB downloaded in 0.00s (28.80MB/s)
88 12:43:13.002370 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:43:13.002602 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:43:13.002684 start: 1.4 download-retry (timeout 00:10:00) [common]
92 12:43:13.002764 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 12:43:13.002898 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230609.0/arm64/full.rootfs.tar.xz
94 12:43:13.002979 saving as /var/lib/lava/dispatcher/tmp/10724879/tftp-deploy-49u57mqi/nfsrootfs/full.rootfs.tar
95 12:43:13.003038 total size: 200816996 (191MB)
96 12:43:13.003095 Using unxz to decompress xz
97 12:43:13.006622 progress 0% (0MB)
98 12:43:13.531315 progress 5% (9MB)
99 12:43:14.034519 progress 10% (19MB)
100 12:43:14.604538 progress 15% (28MB)
101 12:43:14.974237 progress 20% (38MB)
102 12:43:15.289145 progress 25% (47MB)
103 12:43:15.862826 progress 30% (57MB)
104 12:43:16.399466 progress 35% (67MB)
105 12:43:16.983620 progress 40% (76MB)
106 12:43:17.528337 progress 45% (86MB)
107 12:43:18.100064 progress 50% (95MB)
108 12:43:18.717868 progress 55% (105MB)
109 12:43:19.391126 progress 60% (114MB)
110 12:43:19.509385 progress 65% (124MB)
111 12:43:19.645413 progress 70% (134MB)
112 12:43:19.729439 progress 75% (143MB)
113 12:43:19.803292 progress 80% (153MB)
114 12:43:19.881223 progress 85% (162MB)
115 12:43:19.987737 progress 90% (172MB)
116 12:43:20.264417 progress 95% (181MB)
117 12:43:20.826415 progress 100% (191MB)
118 12:43:20.831712 191MB downloaded in 7.83s (24.46MB/s)
119 12:43:20.832002 end: 1.4.1 http-download (duration 00:00:08) [common]
121 12:43:20.832267 end: 1.4 download-retry (duration 00:00:08) [common]
122 12:43:20.832360 start: 1.5 download-retry (timeout 00:09:52) [common]
123 12:43:20.832448 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 12:43:20.832598 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:43:20.832670 saving as /var/lib/lava/dispatcher/tmp/10724879/tftp-deploy-49u57mqi/modules/modules.tar
126 12:43:20.832732 total size: 8536768 (8MB)
127 12:43:20.832795 Using unxz to decompress xz
128 12:43:20.836410 progress 0% (0MB)
129 12:43:20.856979 progress 5% (0MB)
130 12:43:20.883286 progress 10% (0MB)
131 12:43:20.913384 progress 15% (1MB)
132 12:43:20.936785 progress 20% (1MB)
133 12:43:20.959662 progress 25% (2MB)
134 12:43:20.983535 progress 30% (2MB)
135 12:43:21.006460 progress 35% (2MB)
136 12:43:21.032884 progress 40% (3MB)
137 12:43:21.056846 progress 45% (3MB)
138 12:43:21.082169 progress 50% (4MB)
139 12:43:21.106566 progress 55% (4MB)
140 12:43:21.131337 progress 60% (4MB)
141 12:43:21.155875 progress 65% (5MB)
142 12:43:21.180281 progress 70% (5MB)
143 12:43:21.204008 progress 75% (6MB)
144 12:43:21.227488 progress 80% (6MB)
145 12:43:21.250914 progress 85% (6MB)
146 12:43:21.275674 progress 90% (7MB)
147 12:43:21.299935 progress 95% (7MB)
148 12:43:21.322033 progress 100% (8MB)
149 12:43:21.328579 8MB downloaded in 0.50s (16.42MB/s)
150 12:43:21.328857 end: 1.5.1 http-download (duration 00:00:00) [common]
152 12:43:21.329145 end: 1.5 download-retry (duration 00:00:00) [common]
153 12:43:21.329251 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 12:43:21.329360 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 12:43:24.891591 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10724879/extract-nfsrootfs-vz66w8m2
156 12:43:24.891791 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 12:43:24.891891 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 12:43:24.892058 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy
159 12:43:24.892178 makedir: /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy/lava-10724879/bin
160 12:43:24.892273 makedir: /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy/lava-10724879/tests
161 12:43:24.892364 makedir: /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy/lava-10724879/results
162 12:43:24.892462 Creating /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy/lava-10724879/bin/lava-add-keys
163 12:43:24.892600 Creating /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy/lava-10724879/bin/lava-add-sources
164 12:43:24.892722 Creating /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy/lava-10724879/bin/lava-background-process-start
165 12:43:24.892846 Creating /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy/lava-10724879/bin/lava-background-process-stop
166 12:43:24.892966 Creating /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy/lava-10724879/bin/lava-common-functions
167 12:43:24.893085 Creating /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy/lava-10724879/bin/lava-echo-ipv4
168 12:43:24.893203 Creating /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy/lava-10724879/bin/lava-install-packages
169 12:43:24.893357 Creating /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy/lava-10724879/bin/lava-installed-packages
170 12:43:24.893473 Creating /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy/lava-10724879/bin/lava-os-build
171 12:43:24.893589 Creating /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy/lava-10724879/bin/lava-probe-channel
172 12:43:24.893704 Creating /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy/lava-10724879/bin/lava-probe-ip
173 12:43:24.893820 Creating /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy/lava-10724879/bin/lava-target-ip
174 12:43:24.893936 Creating /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy/lava-10724879/bin/lava-target-mac
175 12:43:24.894051 Creating /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy/lava-10724879/bin/lava-target-storage
176 12:43:24.894170 Creating /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy/lava-10724879/bin/lava-test-case
177 12:43:24.894288 Creating /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy/lava-10724879/bin/lava-test-event
178 12:43:24.894403 Creating /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy/lava-10724879/bin/lava-test-feedback
179 12:43:24.894520 Creating /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy/lava-10724879/bin/lava-test-raise
180 12:43:24.894636 Creating /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy/lava-10724879/bin/lava-test-reference
181 12:43:24.894753 Creating /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy/lava-10724879/bin/lava-test-runner
182 12:43:24.894915 Creating /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy/lava-10724879/bin/lava-test-set
183 12:43:24.895046 Creating /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy/lava-10724879/bin/lava-test-shell
184 12:43:24.895164 Updating /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy/lava-10724879/bin/lava-add-keys (debian)
185 12:43:24.895305 Updating /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy/lava-10724879/bin/lava-add-sources (debian)
186 12:43:24.895448 Updating /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy/lava-10724879/bin/lava-install-packages (debian)
187 12:43:24.895580 Updating /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy/lava-10724879/bin/lava-installed-packages (debian)
188 12:43:24.895715 Updating /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy/lava-10724879/bin/lava-os-build (debian)
189 12:43:24.895834 Creating /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy/lava-10724879/environment
190 12:43:24.895928 LAVA metadata
191 12:43:24.895995 - LAVA_JOB_ID=10724879
192 12:43:24.896056 - LAVA_DISPATCHER_IP=192.168.201.1
193 12:43:24.896150 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 12:43:24.896214 skipped lava-vland-overlay
195 12:43:24.896285 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 12:43:24.896363 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 12:43:24.896421 skipped lava-multinode-overlay
198 12:43:24.896491 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 12:43:24.896566 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 12:43:24.896636 Loading test definitions
201 12:43:24.896724 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 12:43:24.896795 Using /lava-10724879 at stage 0
203 12:43:24.897058 uuid=10724879_1.6.2.3.1 testdef=None
204 12:43:24.897143 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 12:43:24.897226 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 12:43:24.897652 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 12:43:24.897861 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 12:43:24.898389 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 12:43:24.898612 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 12:43:24.899187 runner path: /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy/lava-10724879/0/tests/0_timesync-off test_uuid 10724879_1.6.2.3.1
213 12:43:24.899333 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 12:43:24.899547 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 12:43:24.899616 Using /lava-10724879 at stage 0
217 12:43:24.899709 Fetching tests from https://github.com/kernelci/test-definitions.git
218 12:43:24.899787 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy/lava-10724879/0/tests/1_kselftest-rtc'
219 12:43:29.411022 Running '/usr/bin/git checkout kernelci.org
220 12:43:29.554295 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy/lava-10724879/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 12:43:29.555035 uuid=10724879_1.6.2.3.5 testdef=None
222 12:43:29.555198 end: 1.6.2.3.5 git-repo-action (duration 00:00:05) [common]
224 12:43:29.555449 start: 1.6.2.3.6 test-overlay (timeout 00:09:43) [common]
225 12:43:29.556180 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 12:43:29.556409 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:43) [common]
228 12:43:29.557362 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 12:43:29.557595 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:43) [common]
231 12:43:29.558513 runner path: /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy/lava-10724879/0/tests/1_kselftest-rtc test_uuid 10724879_1.6.2.3.5
232 12:43:29.558604 BOARD='mt8192-asurada-spherion-r0'
233 12:43:29.558669 BRANCH='cip'
234 12:43:29.558728 SKIPFILE='/dev/null'
235 12:43:29.558786 SKIP_INSTALL='True'
236 12:43:29.558869 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 12:43:29.558942 TST_CASENAME=''
238 12:43:29.558997 TST_CMDFILES='rtc'
239 12:43:29.559134 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 12:43:29.559337 Creating lava-test-runner.conf files
242 12:43:29.559402 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10724879/lava-overlay-ixb8osxy/lava-10724879/0 for stage 0
243 12:43:29.559498 - 0_timesync-off
244 12:43:29.559568 - 1_kselftest-rtc
245 12:43:29.559662 end: 1.6.2.3 test-definition (duration 00:00:05) [common]
246 12:43:29.559751 start: 1.6.2.4 compress-overlay (timeout 00:09:43) [common]
247 12:43:36.962468 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 12:43:36.962625 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:36) [common]
249 12:43:36.962721 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 12:43:36.962821 end: 1.6.2 lava-overlay (duration 00:00:12) [common]
251 12:43:36.962921 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:36) [common]
252 12:43:37.076894 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 12:43:37.077259 start: 1.6.4 extract-modules (timeout 00:09:36) [common]
254 12:43:37.077384 extracting modules file /var/lib/lava/dispatcher/tmp/10724879/tftp-deploy-49u57mqi/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10724879/extract-nfsrootfs-vz66w8m2
255 12:43:37.279394 extracting modules file /var/lib/lava/dispatcher/tmp/10724879/tftp-deploy-49u57mqi/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10724879/extract-overlay-ramdisk-mdghy6f2/ramdisk
256 12:43:37.486763 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 12:43:37.486935 start: 1.6.5 apply-overlay-tftp (timeout 00:09:35) [common]
258 12:43:37.487025 [common] Applying overlay to NFS
259 12:43:37.487096 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10724879/compress-overlay-dhasdy9i/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10724879/extract-nfsrootfs-vz66w8m2
260 12:43:38.384616 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 12:43:38.384790 start: 1.6.6 configure-preseed-file (timeout 00:09:34) [common]
262 12:43:38.384890 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 12:43:38.384985 start: 1.6.7 compress-ramdisk (timeout 00:09:34) [common]
264 12:43:38.385069 Building ramdisk /var/lib/lava/dispatcher/tmp/10724879/extract-overlay-ramdisk-mdghy6f2/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10724879/extract-overlay-ramdisk-mdghy6f2/ramdisk
265 12:43:38.683993 >> 117806 blocks
266 12:43:40.588960 rename /var/lib/lava/dispatcher/tmp/10724879/extract-overlay-ramdisk-mdghy6f2/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10724879/tftp-deploy-49u57mqi/ramdisk/ramdisk.cpio.gz
267 12:43:40.589396 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 12:43:40.589523 start: 1.6.8 prepare-kernel (timeout 00:09:32) [common]
269 12:43:40.589621 start: 1.6.8.1 prepare-fit (timeout 00:09:32) [common]
270 12:43:40.589725 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10724879/tftp-deploy-49u57mqi/kernel/Image'
271 12:43:52.630834 Returned 0 in 12 seconds
272 12:43:52.731482 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10724879/tftp-deploy-49u57mqi/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10724879/tftp-deploy-49u57mqi/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10724879/tftp-deploy-49u57mqi/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10724879/tftp-deploy-49u57mqi/kernel/image.itb
273 12:43:53.042986 output: FIT description: Kernel Image image with one or more FDT blobs
274 12:43:53.043344 output: Created: Wed Jun 14 13:43:52 2023
275 12:43:53.043420 output: Image 0 (kernel-1)
276 12:43:53.043487 output: Description:
277 12:43:53.043555 output: Created: Wed Jun 14 13:43:52 2023
278 12:43:53.043617 output: Type: Kernel Image
279 12:43:53.043677 output: Compression: lzma compressed
280 12:43:53.043737 output: Data Size: 10442380 Bytes = 10197.64 KiB = 9.96 MiB
281 12:43:53.043796 output: Architecture: AArch64
282 12:43:53.043854 output: OS: Linux
283 12:43:53.043909 output: Load Address: 0x00000000
284 12:43:53.043968 output: Entry Point: 0x00000000
285 12:43:53.044024 output: Hash algo: crc32
286 12:43:53.044077 output: Hash value: ced21bfe
287 12:43:53.044130 output: Image 1 (fdt-1)
288 12:43:53.044183 output: Description: mt8192-asurada-spherion-r0
289 12:43:53.044236 output: Created: Wed Jun 14 13:43:52 2023
290 12:43:53.044289 output: Type: Flat Device Tree
291 12:43:53.044341 output: Compression: uncompressed
292 12:43:53.044393 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 12:43:53.044446 output: Architecture: AArch64
294 12:43:53.044499 output: Hash algo: crc32
295 12:43:53.044551 output: Hash value: 1df858fa
296 12:43:53.044602 output: Image 2 (ramdisk-1)
297 12:43:53.044655 output: Description: unavailable
298 12:43:53.044707 output: Created: Wed Jun 14 13:43:52 2023
299 12:43:53.044760 output: Type: RAMDisk Image
300 12:43:53.044813 output: Compression: Unknown Compression
301 12:43:53.044866 output: Data Size: 17643246 Bytes = 17229.73 KiB = 16.83 MiB
302 12:43:53.044919 output: Architecture: AArch64
303 12:43:53.044971 output: OS: Linux
304 12:43:53.045024 output: Load Address: unavailable
305 12:43:53.045076 output: Entry Point: unavailable
306 12:43:53.045128 output: Hash algo: crc32
307 12:43:53.045179 output: Hash value: b058c9ff
308 12:43:53.045232 output: Default Configuration: 'conf-1'
309 12:43:53.045284 output: Configuration 0 (conf-1)
310 12:43:53.045336 output: Description: mt8192-asurada-spherion-r0
311 12:43:53.045389 output: Kernel: kernel-1
312 12:43:53.045441 output: Init Ramdisk: ramdisk-1
313 12:43:53.045493 output: FDT: fdt-1
314 12:43:53.045546 output: Loadables: kernel-1
315 12:43:53.045598 output:
316 12:43:53.045798 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 12:43:53.045897 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 12:43:53.045997 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 12:43:53.046092 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
320 12:43:53.046167 No LXC device requested
321 12:43:53.046243 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 12:43:53.046328 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
323 12:43:53.046404 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 12:43:53.046474 Checking files for TFTP limit of 4294967296 bytes.
325 12:43:53.047002 end: 1 tftp-deploy (duration 00:00:40) [common]
326 12:43:53.047113 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 12:43:53.047205 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 12:43:53.047328 substitutions:
329 12:43:53.047396 - {DTB}: 10724879/tftp-deploy-49u57mqi/dtb/mt8192-asurada-spherion-r0.dtb
330 12:43:53.047460 - {INITRD}: 10724879/tftp-deploy-49u57mqi/ramdisk/ramdisk.cpio.gz
331 12:43:53.047519 - {KERNEL}: 10724879/tftp-deploy-49u57mqi/kernel/Image
332 12:43:53.047576 - {LAVA_MAC}: None
333 12:43:53.047632 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10724879/extract-nfsrootfs-vz66w8m2
334 12:43:53.047688 - {NFS_SERVER_IP}: 192.168.201.1
335 12:43:53.047743 - {PRESEED_CONFIG}: None
336 12:43:53.047798 - {PRESEED_LOCAL}: None
337 12:43:53.047853 - {RAMDISK}: 10724879/tftp-deploy-49u57mqi/ramdisk/ramdisk.cpio.gz
338 12:43:53.047907 - {ROOT_PART}: None
339 12:43:53.047961 - {ROOT}: None
340 12:43:53.048015 - {SERVER_IP}: 192.168.201.1
341 12:43:53.048069 - {TEE}: None
342 12:43:53.048123 Parsed boot commands:
343 12:43:53.048176 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 12:43:53.048351 Parsed boot commands: tftpboot 192.168.201.1 10724879/tftp-deploy-49u57mqi/kernel/image.itb 10724879/tftp-deploy-49u57mqi/kernel/cmdline
345 12:43:53.048441 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 12:43:53.048527 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 12:43:53.048617 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 12:43:53.048707 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 12:43:53.048778 Not connected, no need to disconnect.
350 12:43:53.048852 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 12:43:53.048935 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 12:43:53.049001 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-8'
353 12:43:53.052478 Setting prompt string to ['lava-test: # ']
354 12:43:53.052825 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 12:43:53.052934 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 12:43:53.053036 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 12:43:53.053127 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 12:43:53.053321 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
359 12:43:58.189217 >> Command sent successfully.
360 12:43:58.191621 Returned 0 in 5 seconds
361 12:43:58.292019 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 12:43:58.292362 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 12:43:58.292473 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 12:43:58.292563 Setting prompt string to 'Starting depthcharge on Spherion...'
366 12:43:58.292627 Changing prompt to 'Starting depthcharge on Spherion...'
367 12:43:58.292697 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 12:43:58.292965 [Enter `^Ec?' for help]
369 12:43:58.464338
370 12:43:58.464484
371 12:43:58.464556 F0: 102B 0000
372 12:43:58.464621
373 12:43:58.464681 F3: 1001 0000 [0200]
374 12:43:58.464741
375 12:43:58.468150 F3: 1001 0000
376 12:43:58.468235
377 12:43:58.468302 F7: 102D 0000
378 12:43:58.468365
379 12:43:58.471701 F1: 0000 0000
380 12:43:58.471784
381 12:43:58.471850 V0: 0000 0000 [0001]
382 12:43:58.471914
383 12:43:58.471973 00: 0007 8000
384 12:43:58.472035
385 12:43:58.475121 01: 0000 0000
386 12:43:58.475204
387 12:43:58.475270 BP: 0C00 0209 [0000]
388 12:43:58.475331
389 12:43:58.479025 G0: 1182 0000
390 12:43:58.479108
391 12:43:58.479173 EC: 0000 0021 [4000]
392 12:43:58.479234
393 12:43:58.482592 S7: 0000 0000 [0000]
394 12:43:58.482674
395 12:43:58.482740 CC: 0000 0000 [0001]
396 12:43:58.482801
397 12:43:58.485780 T0: 0000 0040 [010F]
398 12:43:58.485866
399 12:43:58.485932 Jump to BL
400 12:43:58.485995
401 12:43:58.511414
402 12:43:58.511499
403 12:43:58.511564
404 12:43:58.518788 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 12:43:58.522659 ARM64: Exception handlers installed.
406 12:43:58.526269 ARM64: Testing exception
407 12:43:58.529539 ARM64: Done test exception
408 12:43:58.536757 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 12:43:58.543827 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 12:43:58.553964 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 12:43:58.564134 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 12:43:58.570483 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 12:43:58.577229 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 12:43:58.587736 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 12:43:58.594407 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 12:43:58.613926 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 12:43:58.617608 WDT: Last reset was cold boot
418 12:43:58.620971 SPI1(PAD0) initialized at 2873684 Hz
419 12:43:58.624030 SPI5(PAD0) initialized at 992727 Hz
420 12:43:58.627628 VBOOT: Loading verstage.
421 12:43:58.634553 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 12:43:58.637772 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 12:43:58.640720 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 12:43:58.644443 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 12:43:58.651737 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 12:43:58.658412 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 12:43:58.669283 read SPI 0x96554 0xa1eb: 4593 us, 9024 KB/s, 72.192 Mbps
428 12:43:58.669651
429 12:43:58.669941
430 12:43:58.679628 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 12:43:58.682735 ARM64: Exception handlers installed.
432 12:43:58.686074 ARM64: Testing exception
433 12:43:58.686470 ARM64: Done test exception
434 12:43:58.692457 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 12:43:58.696319 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 12:43:58.709947 Probing TPM: . done!
437 12:43:58.710310 TPM ready after 0 ms
438 12:43:58.717155 Connected to device vid:did:rid of 1ae0:0028:00
439 12:43:58.723610 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 12:43:58.766174 Initialized TPM device CR50 revision 0
441 12:43:58.776663 tlcl_send_startup: Startup return code is 0
442 12:43:58.777057 TPM: setup succeeded
443 12:43:58.788205 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 12:43:58.797077 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 12:43:58.808736 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 12:43:58.818455 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 12:43:58.821446 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 12:43:58.825553 in-header: 03 07 00 00 08 00 00 00
449 12:43:58.828890 in-data: aa e4 47 04 13 02 00 00
450 12:43:58.832892 Chrome EC: UHEPI supported
451 12:43:58.839450 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 12:43:58.843082 in-header: 03 9d 00 00 08 00 00 00
453 12:43:58.847145 in-data: 10 20 20 08 00 00 00 00
454 12:43:58.847545 Phase 1
455 12:43:58.850914 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 12:43:58.858001 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 12:43:58.865781 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 12:43:58.866314 Recovery requested (1009000e)
459 12:43:58.874079 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 12:43:58.879422 tlcl_extend: response is 0
461 12:43:58.887385 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 12:43:58.893044 tlcl_extend: response is 0
463 12:43:58.899564 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 12:43:58.920355 read SPI 0x210d4 0x2173b: 15147 us, 9045 KB/s, 72.360 Mbps
465 12:43:58.927549 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 12:43:58.927948
467 12:43:58.928262
468 12:43:58.938050 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 12:43:58.941670 ARM64: Exception handlers installed.
470 12:43:58.942043 ARM64: Testing exception
471 12:43:58.945050 ARM64: Done test exception
472 12:43:58.965614 pmic_efuse_setting: Set efuses in 11 msecs
473 12:43:58.969158 pmwrap_interface_init: Select PMIF_VLD_RDY
474 12:43:58.976065 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 12:43:58.979274 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 12:43:58.983283 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 12:43:58.990387 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 12:43:58.993980 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 12:43:58.997544 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 12:43:59.004590 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 12:43:59.008311 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 12:43:59.011564 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 12:43:59.018227 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 12:43:59.021745 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 12:43:59.027947 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 12:43:59.031504 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 12:43:59.037817 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 12:43:59.044192 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 12:43:59.047861 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 12:43:59.054400 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 12:43:59.060836 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 12:43:59.065065 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 12:43:59.072098 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 12:43:59.075587 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 12:43:59.082902 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 12:43:59.089589 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 12:43:59.092556 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 12:43:59.099650 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 12:43:59.106019 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 12:43:59.109261 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 12:43:59.116603 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 12:43:59.119410 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 12:43:59.123326 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 12:43:59.130268 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 12:43:59.133342 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 12:43:59.140941 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 12:43:59.144686 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 12:43:59.148606 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 12:43:59.155573 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 12:43:59.159134 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 12:43:59.166069 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 12:43:59.169066 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 12:43:59.172709 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 12:43:59.179370 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 12:43:59.182408 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 12:43:59.185659 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 12:43:59.192351 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 12:43:59.195796 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 12:43:59.199541 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 12:43:59.202776 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 12:43:59.209106 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 12:43:59.212718 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 12:43:59.215584 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 12:43:59.219203 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 12:43:59.229096 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 12:43:59.235504 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 12:43:59.242067 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 12:43:59.249064 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 12:43:59.259030 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 12:43:59.262575 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 12:43:59.265717 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 12:43:59.272522 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 12:43:59.278925 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
534 12:43:59.285638 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 12:43:59.288396 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 12:43:59.291885 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 12:43:59.302532 [RTC]rtc_get_frequency_meter,154: input=15, output=793
538 12:43:59.305895 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
539 12:43:59.312367 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
540 12:43:59.316166 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
541 12:43:59.318956 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
542 12:43:59.322435 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
543 12:43:59.325970 ADC[4]: Raw value=897780 ID=7
544 12:43:59.329216 ADC[3]: Raw value=213440 ID=1
545 12:43:59.332535 RAM Code: 0x71
546 12:43:59.335614 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
547 12:43:59.339264 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
548 12:43:59.348904 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
549 12:43:59.356127 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
550 12:43:59.359715 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
551 12:43:59.362659 in-header: 03 07 00 00 08 00 00 00
552 12:43:59.366352 in-data: aa e4 47 04 13 02 00 00
553 12:43:59.369402 Chrome EC: UHEPI supported
554 12:43:59.376190 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
555 12:43:59.379805 in-header: 03 95 00 00 08 00 00 00
556 12:43:59.383311 in-data: 18 20 20 08 00 00 00 00
557 12:43:59.383762 MRC: failed to locate region type 0.
558 12:43:59.390509 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
559 12:43:59.394769 DRAM-K: Running full calibration
560 12:43:59.401399 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
561 12:43:59.401825 header.status = 0x0
562 12:43:59.404262 header.version = 0x6 (expected: 0x6)
563 12:43:59.408258 header.size = 0xd00 (expected: 0xd00)
564 12:43:59.411228 header.flags = 0x0
565 12:43:59.417615 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
566 12:43:59.434941 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps
567 12:43:59.441074 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
568 12:43:59.444840 dram_init: ddr_geometry: 2
569 12:43:59.447974 [EMI] MDL number = 2
570 12:43:59.448412 [EMI] Get MDL freq = 0
571 12:43:59.451331 dram_init: ddr_type: 0
572 12:43:59.451894 is_discrete_lpddr4: 1
573 12:43:59.454789 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
574 12:43:59.455323
575 12:43:59.455670
576 12:43:59.458156 [Bian_co] ETT version 0.0.0.1
577 12:43:59.464623 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
578 12:43:59.465187
579 12:43:59.468096 dramc_set_vcore_voltage set vcore to 650000
580 12:43:59.470892 Read voltage for 800, 4
581 12:43:59.471319 Vio18 = 0
582 12:43:59.471660 Vcore = 650000
583 12:43:59.474665 Vdram = 0
584 12:43:59.475236 Vddq = 0
585 12:43:59.475588 Vmddr = 0
586 12:43:59.477959 dram_init: config_dvfs: 1
587 12:43:59.481431 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
588 12:43:59.488188 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
589 12:43:59.491190 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
590 12:43:59.494723 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
591 12:43:59.497873 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
592 12:43:59.500766 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
593 12:43:59.504458 MEM_TYPE=3, freq_sel=18
594 12:43:59.507730 sv_algorithm_assistance_LP4_1600
595 12:43:59.510932 ============ PULL DRAM RESETB DOWN ============
596 12:43:59.517277 ========== PULL DRAM RESETB DOWN end =========
597 12:43:59.520900 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
598 12:43:59.524425 ===================================
599 12:43:59.527576 LPDDR4 DRAM CONFIGURATION
600 12:43:59.531198 ===================================
601 12:43:59.531728 EX_ROW_EN[0] = 0x0
602 12:43:59.533828 EX_ROW_EN[1] = 0x0
603 12:43:59.534258 LP4Y_EN = 0x0
604 12:43:59.537158 WORK_FSP = 0x0
605 12:43:59.537610 WL = 0x2
606 12:43:59.540564 RL = 0x2
607 12:43:59.543515 BL = 0x2
608 12:43:59.544071 RPST = 0x0
609 12:43:59.547143 RD_PRE = 0x0
610 12:43:59.547615 WR_PRE = 0x1
611 12:43:59.550609 WR_PST = 0x0
612 12:43:59.551154 DBI_WR = 0x0
613 12:43:59.553663 DBI_RD = 0x0
614 12:43:59.554122 OTF = 0x1
615 12:43:59.556874 ===================================
616 12:43:59.560352 ===================================
617 12:43:59.563705 ANA top config
618 12:43:59.567029 ===================================
619 12:43:59.567477 DLL_ASYNC_EN = 0
620 12:43:59.570413 ALL_SLAVE_EN = 1
621 12:43:59.573713 NEW_RANK_MODE = 1
622 12:43:59.576723 DLL_IDLE_MODE = 1
623 12:43:59.577150 LP45_APHY_COMB_EN = 1
624 12:43:59.580517 TX_ODT_DIS = 1
625 12:43:59.583716 NEW_8X_MODE = 1
626 12:43:59.587372 ===================================
627 12:43:59.590138 ===================================
628 12:43:59.593498 data_rate = 1600
629 12:43:59.596877 CKR = 1
630 12:43:59.600579 DQ_P2S_RATIO = 8
631 12:43:59.603479 ===================================
632 12:43:59.603917 CA_P2S_RATIO = 8
633 12:43:59.607177 DQ_CA_OPEN = 0
634 12:43:59.610285 DQ_SEMI_OPEN = 0
635 12:43:59.613610 CA_SEMI_OPEN = 0
636 12:43:59.616914 CA_FULL_RATE = 0
637 12:43:59.620049 DQ_CKDIV4_EN = 1
638 12:43:59.620482 CA_CKDIV4_EN = 1
639 12:43:59.623667 CA_PREDIV_EN = 0
640 12:43:59.626943 PH8_DLY = 0
641 12:43:59.630344 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
642 12:43:59.633590 DQ_AAMCK_DIV = 4
643 12:43:59.637154 CA_AAMCK_DIV = 4
644 12:43:59.637722 CA_ADMCK_DIV = 4
645 12:43:59.639936 DQ_TRACK_CA_EN = 0
646 12:43:59.643373 CA_PICK = 800
647 12:43:59.646885 CA_MCKIO = 800
648 12:43:59.650639 MCKIO_SEMI = 0
649 12:43:59.653633 PLL_FREQ = 3068
650 12:43:59.656914 DQ_UI_PI_RATIO = 32
651 12:43:59.657347 CA_UI_PI_RATIO = 0
652 12:43:59.660492 ===================================
653 12:43:59.663373 ===================================
654 12:43:59.666811 memory_type:LPDDR4
655 12:43:59.669920 GP_NUM : 10
656 12:43:59.670468 SRAM_EN : 1
657 12:43:59.673067 MD32_EN : 0
658 12:43:59.676991 ===================================
659 12:43:59.680926 [ANA_INIT] >>>>>>>>>>>>>>
660 12:43:59.681503 <<<<<< [CONFIGURE PHASE]: ANA_TX
661 12:43:59.684110 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
662 12:43:59.687427 ===================================
663 12:43:59.691412 data_rate = 1600,PCW = 0X7600
664 12:43:59.695227 ===================================
665 12:43:59.698516 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
666 12:43:59.702194 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
667 12:43:59.709481 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
668 12:43:59.713131 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
669 12:43:59.716932 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
670 12:43:59.720552 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
671 12:43:59.723825 [ANA_INIT] flow start
672 12:43:59.724260 [ANA_INIT] PLL >>>>>>>>
673 12:43:59.727680 [ANA_INIT] PLL <<<<<<<<
674 12:43:59.728117 [ANA_INIT] MIDPI >>>>>>>>
675 12:43:59.731140 [ANA_INIT] MIDPI <<<<<<<<
676 12:43:59.734386 [ANA_INIT] DLL >>>>>>>>
677 12:43:59.734790 [ANA_INIT] flow end
678 12:43:59.738250 ============ LP4 DIFF to SE enter ============
679 12:43:59.745779 ============ LP4 DIFF to SE exit ============
680 12:43:59.746240 [ANA_INIT] <<<<<<<<<<<<<
681 12:43:59.749144 [Flow] Enable top DCM control >>>>>
682 12:43:59.753146 [Flow] Enable top DCM control <<<<<
683 12:43:59.756690 Enable DLL master slave shuffle
684 12:43:59.760336 ==============================================================
685 12:43:59.764195 Gating Mode config
686 12:43:59.767283 ==============================================================
687 12:43:59.770910 Config description:
688 12:43:59.778664 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
689 12:43:59.786218 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
690 12:43:59.793608 SELPH_MODE 0: By rank 1: By Phase
691 12:43:59.797141 ==============================================================
692 12:43:59.800406 GAT_TRACK_EN = 1
693 12:43:59.804815 RX_GATING_MODE = 2
694 12:43:59.808582 RX_GATING_TRACK_MODE = 2
695 12:43:59.809124 SELPH_MODE = 1
696 12:43:59.811559 PICG_EARLY_EN = 1
697 12:43:59.814904 VALID_LAT_VALUE = 1
698 12:43:59.821769 ==============================================================
699 12:43:59.824455 Enter into Gating configuration >>>>
700 12:43:59.828001 Exit from Gating configuration <<<<
701 12:43:59.831360 Enter into DVFS_PRE_config >>>>>
702 12:43:59.841302 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
703 12:43:59.844225 Exit from DVFS_PRE_config <<<<<
704 12:43:59.847904 Enter into PICG configuration >>>>
705 12:43:59.851802 Exit from PICG configuration <<<<
706 12:43:59.854953 [RX_INPUT] configuration >>>>>
707 12:43:59.857556 [RX_INPUT] configuration <<<<<
708 12:43:59.861317 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
709 12:43:59.867976 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
710 12:43:59.874746 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
711 12:43:59.881444 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
712 12:43:59.884931 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
713 12:43:59.890806 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
714 12:43:59.894675 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
715 12:43:59.900959 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
716 12:43:59.904399 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
717 12:43:59.907714 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
718 12:43:59.910560 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
719 12:43:59.917520 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
720 12:43:59.921317 ===================================
721 12:43:59.921879 LPDDR4 DRAM CONFIGURATION
722 12:43:59.924728 ===================================
723 12:43:59.927603 EX_ROW_EN[0] = 0x0
724 12:43:59.931261 EX_ROW_EN[1] = 0x0
725 12:43:59.931718 LP4Y_EN = 0x0
726 12:43:59.934502 WORK_FSP = 0x0
727 12:43:59.935028 WL = 0x2
728 12:43:59.938565 RL = 0x2
729 12:43:59.939100 BL = 0x2
730 12:43:59.939474 RPST = 0x0
731 12:43:59.941864 RD_PRE = 0x0
732 12:43:59.942491 WR_PRE = 0x1
733 12:43:59.945276 WR_PST = 0x0
734 12:43:59.945710 DBI_WR = 0x0
735 12:43:59.949286 DBI_RD = 0x0
736 12:43:59.949943 OTF = 0x1
737 12:43:59.952526 ===================================
738 12:43:59.956139 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
739 12:43:59.959804 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
740 12:43:59.967006 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
741 12:43:59.970600 ===================================
742 12:43:59.971057 LPDDR4 DRAM CONFIGURATION
743 12:43:59.974857 ===================================
744 12:43:59.978414 EX_ROW_EN[0] = 0x10
745 12:43:59.979154 EX_ROW_EN[1] = 0x0
746 12:43:59.981563 LP4Y_EN = 0x0
747 12:43:59.981990 WORK_FSP = 0x0
748 12:43:59.985498 WL = 0x2
749 12:43:59.985926 RL = 0x2
750 12:43:59.989132 BL = 0x2
751 12:43:59.989559 RPST = 0x0
752 12:43:59.992736 RD_PRE = 0x0
753 12:43:59.993164 WR_PRE = 0x1
754 12:43:59.996514 WR_PST = 0x0
755 12:43:59.997085 DBI_WR = 0x0
756 12:44:00.000261 DBI_RD = 0x0
757 12:44:00.000726 OTF = 0x1
758 12:44:00.003197 ===================================
759 12:44:00.010553 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
760 12:44:00.014591 nWR fixed to 40
761 12:44:00.015087 [ModeRegInit_LP4] CH0 RK0
762 12:44:00.018526 [ModeRegInit_LP4] CH0 RK1
763 12:44:00.021696 [ModeRegInit_LP4] CH1 RK0
764 12:44:00.022138 [ModeRegInit_LP4] CH1 RK1
765 12:44:00.025276 match AC timing 13
766 12:44:00.029557 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
767 12:44:00.032328 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
768 12:44:00.036414 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
769 12:44:00.044008 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
770 12:44:00.047451 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
771 12:44:00.047880 [EMI DOE] emi_dcm 0
772 12:44:00.051119 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
773 12:44:00.051548 ==
774 12:44:00.054663 Dram Type= 6, Freq= 0, CH_0, rank 0
775 12:44:00.058732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
776 12:44:00.062259 ==
777 12:44:00.065035 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
778 12:44:00.072087 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
779 12:44:00.080630 [CA 0] Center 38 (7~69) winsize 63
780 12:44:00.084451 [CA 1] Center 37 (7~68) winsize 62
781 12:44:00.087766 [CA 2] Center 35 (5~66) winsize 62
782 12:44:00.092076 [CA 3] Center 35 (5~66) winsize 62
783 12:44:00.095342 [CA 4] Center 34 (4~65) winsize 62
784 12:44:00.099165 [CA 5] Center 34 (4~65) winsize 62
785 12:44:00.099597
786 12:44:00.102594 [CmdBusTrainingLP45] Vref(ca) range 1: 34
787 12:44:00.103079
788 12:44:00.105943 [CATrainingPosCal] consider 1 rank data
789 12:44:00.109926 u2DelayCellTimex100 = 270/100 ps
790 12:44:00.113487 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
791 12:44:00.117091 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
792 12:44:00.120859 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
793 12:44:00.124796 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
794 12:44:00.128521 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
795 12:44:00.132130 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
796 12:44:00.132569
797 12:44:00.135524 CA PerBit enable=1, Macro0, CA PI delay=34
798 12:44:00.136003
799 12:44:00.136352 [CBTSetCACLKResult] CA Dly = 34
800 12:44:00.139802 CS Dly: 6 (0~37)
801 12:44:00.140233 ==
802 12:44:00.143306 Dram Type= 6, Freq= 0, CH_0, rank 1
803 12:44:00.146948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
804 12:44:00.147390 ==
805 12:44:00.150654 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
806 12:44:00.157965 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
807 12:44:00.166678 [CA 0] Center 38 (7~69) winsize 63
808 12:44:00.170472 [CA 1] Center 38 (7~69) winsize 63
809 12:44:00.174867 [CA 2] Center 35 (5~66) winsize 62
810 12:44:00.178158 [CA 3] Center 35 (5~66) winsize 62
811 12:44:00.181669 [CA 4] Center 34 (4~65) winsize 62
812 12:44:00.185803 [CA 5] Center 34 (4~65) winsize 62
813 12:44:00.186235
814 12:44:00.189169 [CmdBusTrainingLP45] Vref(ca) range 1: 34
815 12:44:00.189620
816 12:44:00.193368 [CATrainingPosCal] consider 2 rank data
817 12:44:00.193922 u2DelayCellTimex100 = 270/100 ps
818 12:44:00.196682 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
819 12:44:00.200333 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
820 12:44:00.204042 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
821 12:44:00.208001 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
822 12:44:00.214435 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
823 12:44:00.217815 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
824 12:44:00.218243
825 12:44:00.221016 CA PerBit enable=1, Macro0, CA PI delay=34
826 12:44:00.221549
827 12:44:00.224276 [CBTSetCACLKResult] CA Dly = 34
828 12:44:00.224708 CS Dly: 6 (0~38)
829 12:44:00.225052
830 12:44:00.227453 ----->DramcWriteLeveling(PI) begin...
831 12:44:00.227896 ==
832 12:44:00.230932 Dram Type= 6, Freq= 0, CH_0, rank 0
833 12:44:00.237761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
834 12:44:00.238315 ==
835 12:44:00.241128 Write leveling (Byte 0): 33 => 33
836 12:44:00.241653 Write leveling (Byte 1): 32 => 32
837 12:44:00.244102 DramcWriteLeveling(PI) end<-----
838 12:44:00.244542
839 12:44:00.247725 ==
840 12:44:00.248160 Dram Type= 6, Freq= 0, CH_0, rank 0
841 12:44:00.254380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
842 12:44:00.254971 ==
843 12:44:00.257331 [Gating] SW mode calibration
844 12:44:00.264102 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
845 12:44:00.267499 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
846 12:44:00.274157 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
847 12:44:00.277474 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
848 12:44:00.281002 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
849 12:44:00.287519 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
850 12:44:00.290764 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 12:44:00.294227 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 12:44:00.300323 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 12:44:00.303867 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 12:44:00.307503 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 12:44:00.310938 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 12:44:00.318777 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 12:44:00.322156 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 12:44:00.325312 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 12:44:00.328676 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 12:44:00.336433 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 12:44:00.339386 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 12:44:00.342813 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 12:44:00.346461 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 12:44:00.352584 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
865 12:44:00.356014 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
866 12:44:00.359467 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 12:44:00.366313 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 12:44:00.369106 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 12:44:00.372485 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 12:44:00.379694 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 12:44:00.382569 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 12:44:00.385606 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 12:44:00.392626 0 9 12 | B1->B0 | 2525 3030 | 1 0 | (1 1) (0 0)
874 12:44:00.396183 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
875 12:44:00.399615 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
876 12:44:00.406413 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
877 12:44:00.409349 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 12:44:00.412907 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 12:44:00.418814 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 12:44:00.422288 0 10 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
881 12:44:00.425918 0 10 12 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
882 12:44:00.432420 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
883 12:44:00.435695 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
884 12:44:00.439185 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
885 12:44:00.445608 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 12:44:00.449389 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 12:44:00.452084 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 12:44:00.458901 0 11 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
889 12:44:00.462473 0 11 12 | B1->B0 | 3232 4242 | 0 0 | (0 0) (0 0)
890 12:44:00.465673 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 12:44:00.468959 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
892 12:44:00.475420 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 12:44:00.478902 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 12:44:00.482319 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 12:44:00.488599 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 12:44:00.492099 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
897 12:44:00.495436 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
898 12:44:00.502339 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 12:44:00.505371 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 12:44:00.508805 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 12:44:00.515427 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 12:44:00.519119 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 12:44:00.522444 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 12:44:00.529124 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 12:44:00.532375 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 12:44:00.535700 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 12:44:00.541817 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 12:44:00.545568 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 12:44:00.548543 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 12:44:00.555804 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 12:44:00.558877 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 12:44:00.562131 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
913 12:44:00.565242 Total UI for P1: 0, mck2ui 16
914 12:44:00.568837 best dqsien dly found for B0: ( 0, 14, 6)
915 12:44:00.575289 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
916 12:44:00.578972 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
917 12:44:00.581915 Total UI for P1: 0, mck2ui 16
918 12:44:00.585281 best dqsien dly found for B1: ( 0, 14, 14)
919 12:44:00.588544 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
920 12:44:00.591846 best DQS1 dly(MCK, UI, PI) = (0, 14, 14)
921 12:44:00.592316
922 12:44:00.595169 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
923 12:44:00.598201 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 14)
924 12:44:00.601945 [Gating] SW calibration Done
925 12:44:00.602514 ==
926 12:44:00.605224 Dram Type= 6, Freq= 0, CH_0, rank 0
927 12:44:00.608521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 12:44:00.609056 ==
929 12:44:00.611710 RX Vref Scan: 0
930 12:44:00.612135
931 12:44:00.615266 RX Vref 0 -> 0, step: 1
932 12:44:00.615694
933 12:44:00.616035 RX Delay -130 -> 252, step: 16
934 12:44:00.621514 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
935 12:44:00.625092 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
936 12:44:00.628458 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
937 12:44:00.631613 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
938 12:44:00.638281 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
939 12:44:00.641712 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
940 12:44:00.644877 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
941 12:44:00.648186 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
942 12:44:00.651443 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
943 12:44:00.654777 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
944 12:44:00.661470 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
945 12:44:00.664798 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
946 12:44:00.668299 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
947 12:44:00.671389 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
948 12:44:00.678350 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
949 12:44:00.681320 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
950 12:44:00.681866 ==
951 12:44:00.685014 Dram Type= 6, Freq= 0, CH_0, rank 0
952 12:44:00.687763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
953 12:44:00.688256 ==
954 12:44:00.691634 DQS Delay:
955 12:44:00.692190 DQS0 = 0, DQS1 = 0
956 12:44:00.692574 DQM Delay:
957 12:44:00.694179 DQM0 = 79, DQM1 = 70
958 12:44:00.694610 DQ Delay:
959 12:44:00.697758 DQ0 =77, DQ1 =77, DQ2 =77, DQ3 =77
960 12:44:00.701164 DQ4 =77, DQ5 =69, DQ6 =85, DQ7 =93
961 12:44:00.704327 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
962 12:44:00.708111 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
963 12:44:00.708646
964 12:44:00.709001
965 12:44:00.709326 ==
966 12:44:00.711267 Dram Type= 6, Freq= 0, CH_0, rank 0
967 12:44:00.714820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 12:44:00.717961 ==
969 12:44:00.718408
970 12:44:00.718754
971 12:44:00.719148 TX Vref Scan disable
972 12:44:00.721801 == TX Byte 0 ==
973 12:44:00.724798 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
974 12:44:00.728418 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
975 12:44:00.731202 == TX Byte 1 ==
976 12:44:00.734882 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
977 12:44:00.738071 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
978 12:44:00.738510 ==
979 12:44:00.741620 Dram Type= 6, Freq= 0, CH_0, rank 0
980 12:44:00.748205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
981 12:44:00.748646 ==
982 12:44:00.760233 TX Vref=22, minBit 12, minWin=26, winSum=436
983 12:44:00.763516 TX Vref=24, minBit 11, minWin=26, winSum=437
984 12:44:00.767099 TX Vref=26, minBit 12, minWin=26, winSum=440
985 12:44:00.769930 TX Vref=28, minBit 5, minWin=27, winSum=445
986 12:44:00.773325 TX Vref=30, minBit 9, minWin=27, winSum=444
987 12:44:00.779910 TX Vref=32, minBit 12, minWin=26, winSum=440
988 12:44:00.783730 [TxChooseVref] Worse bit 5, Min win 27, Win sum 445, Final Vref 28
989 12:44:00.784306
990 12:44:00.787135 Final TX Range 1 Vref 28
991 12:44:00.787713
992 12:44:00.788096 ==
993 12:44:00.790088 Dram Type= 6, Freq= 0, CH_0, rank 0
994 12:44:00.793628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
995 12:44:00.796434 ==
996 12:44:00.796912
997 12:44:00.797291
998 12:44:00.797643 TX Vref Scan disable
999 12:44:00.800420 == TX Byte 0 ==
1000 12:44:00.803762 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1001 12:44:00.810012 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1002 12:44:00.810547 == TX Byte 1 ==
1003 12:44:00.813996 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1004 12:44:00.820302 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1005 12:44:00.820841
1006 12:44:00.821186 [DATLAT]
1007 12:44:00.821510 Freq=800, CH0 RK0
1008 12:44:00.821825
1009 12:44:00.823343 DATLAT Default: 0xa
1010 12:44:00.823775 0, 0xFFFF, sum = 0
1011 12:44:00.827160 1, 0xFFFF, sum = 0
1012 12:44:00.827603 2, 0xFFFF, sum = 0
1013 12:44:00.830647 3, 0xFFFF, sum = 0
1014 12:44:00.833291 4, 0xFFFF, sum = 0
1015 12:44:00.833732 5, 0xFFFF, sum = 0
1016 12:44:00.836801 6, 0xFFFF, sum = 0
1017 12:44:00.837238 7, 0xFFFF, sum = 0
1018 12:44:00.840572 8, 0xFFFF, sum = 0
1019 12:44:00.841118 9, 0x0, sum = 1
1020 12:44:00.843789 10, 0x0, sum = 2
1021 12:44:00.844330 11, 0x0, sum = 3
1022 12:44:00.844706 12, 0x0, sum = 4
1023 12:44:00.846758 best_step = 10
1024 12:44:00.847229
1025 12:44:00.847638 ==
1026 12:44:00.850385 Dram Type= 6, Freq= 0, CH_0, rank 0
1027 12:44:00.853580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1028 12:44:00.854015 ==
1029 12:44:00.856588 RX Vref Scan: 1
1030 12:44:00.857117
1031 12:44:00.859710 Set Vref Range= 32 -> 127
1032 12:44:00.860140
1033 12:44:00.860482 RX Vref 32 -> 127, step: 1
1034 12:44:00.860803
1035 12:44:00.862971 RX Delay -111 -> 252, step: 8
1036 12:44:00.863423
1037 12:44:00.866412 Set Vref, RX VrefLevel [Byte0]: 32
1038 12:44:00.870021 [Byte1]: 32
1039 12:44:00.873047
1040 12:44:00.873641 Set Vref, RX VrefLevel [Byte0]: 33
1041 12:44:00.876861 [Byte1]: 33
1042 12:44:00.880977
1043 12:44:00.881508 Set Vref, RX VrefLevel [Byte0]: 34
1044 12:44:00.884696 [Byte1]: 34
1045 12:44:00.888701
1046 12:44:00.889229 Set Vref, RX VrefLevel [Byte0]: 35
1047 12:44:00.891707 [Byte1]: 35
1048 12:44:00.895982
1049 12:44:00.896524 Set Vref, RX VrefLevel [Byte0]: 36
1050 12:44:00.899381 [Byte1]: 36
1051 12:44:00.903508
1052 12:44:00.904034 Set Vref, RX VrefLevel [Byte0]: 37
1053 12:44:00.907100 [Byte1]: 37
1054 12:44:00.911729
1055 12:44:00.912265 Set Vref, RX VrefLevel [Byte0]: 38
1056 12:44:00.914583 [Byte1]: 38
1057 12:44:00.919040
1058 12:44:00.919467 Set Vref, RX VrefLevel [Byte0]: 39
1059 12:44:00.922904 [Byte1]: 39
1060 12:44:00.927020
1061 12:44:00.927551 Set Vref, RX VrefLevel [Byte0]: 40
1062 12:44:00.930435 [Byte1]: 40
1063 12:44:00.934752
1064 12:44:00.935332 Set Vref, RX VrefLevel [Byte0]: 41
1065 12:44:00.937627 [Byte1]: 41
1066 12:44:00.942281
1067 12:44:00.942890 Set Vref, RX VrefLevel [Byte0]: 42
1068 12:44:00.945431 [Byte1]: 42
1069 12:44:00.950011
1070 12:44:00.950580 Set Vref, RX VrefLevel [Byte0]: 43
1071 12:44:00.953171 [Byte1]: 43
1072 12:44:00.957575
1073 12:44:00.958145 Set Vref, RX VrefLevel [Byte0]: 44
1074 12:44:00.963822 [Byte1]: 44
1075 12:44:00.964295
1076 12:44:00.967202 Set Vref, RX VrefLevel [Byte0]: 45
1077 12:44:00.971034 [Byte1]: 45
1078 12:44:00.971591
1079 12:44:00.974319 Set Vref, RX VrefLevel [Byte0]: 46
1080 12:44:00.978148 [Byte1]: 46
1081 12:44:00.978569
1082 12:44:00.981967 Set Vref, RX VrefLevel [Byte0]: 47
1083 12:44:00.985283 [Byte1]: 47
1084 12:44:00.985853
1085 12:44:00.988851 Set Vref, RX VrefLevel [Byte0]: 48
1086 12:44:00.991868 [Byte1]: 48
1087 12:44:00.995836
1088 12:44:00.996302 Set Vref, RX VrefLevel [Byte0]: 49
1089 12:44:00.999278 [Byte1]: 49
1090 12:44:01.003275
1091 12:44:01.003845 Set Vref, RX VrefLevel [Byte0]: 50
1092 12:44:01.007070 [Byte1]: 50
1093 12:44:01.011009
1094 12:44:01.011605 Set Vref, RX VrefLevel [Byte0]: 51
1095 12:44:01.014484 [Byte1]: 51
1096 12:44:01.018444
1097 12:44:01.018954 Set Vref, RX VrefLevel [Byte0]: 52
1098 12:44:01.021669 [Byte1]: 52
1099 12:44:01.026334
1100 12:44:01.026769 Set Vref, RX VrefLevel [Byte0]: 53
1101 12:44:01.029557 [Byte1]: 53
1102 12:44:01.033589
1103 12:44:01.034030 Set Vref, RX VrefLevel [Byte0]: 54
1104 12:44:01.036904 [Byte1]: 54
1105 12:44:01.041502
1106 12:44:01.042051 Set Vref, RX VrefLevel [Byte0]: 55
1107 12:44:01.044568 [Byte1]: 55
1108 12:44:01.048776
1109 12:44:01.049211 Set Vref, RX VrefLevel [Byte0]: 56
1110 12:44:01.052653 [Byte1]: 56
1111 12:44:01.056705
1112 12:44:01.057143 Set Vref, RX VrefLevel [Byte0]: 57
1113 12:44:01.062636 [Byte1]: 57
1114 12:44:01.063103
1115 12:44:01.066417 Set Vref, RX VrefLevel [Byte0]: 58
1116 12:44:01.069456 [Byte1]: 58
1117 12:44:01.070035
1118 12:44:01.073017 Set Vref, RX VrefLevel [Byte0]: 59
1119 12:44:01.076202 [Byte1]: 59
1120 12:44:01.079386
1121 12:44:01.079815 Set Vref, RX VrefLevel [Byte0]: 60
1122 12:44:01.082797 [Byte1]: 60
1123 12:44:01.087147
1124 12:44:01.087592 Set Vref, RX VrefLevel [Byte0]: 61
1125 12:44:01.090524 [Byte1]: 61
1126 12:44:01.094998
1127 12:44:01.095519 Set Vref, RX VrefLevel [Byte0]: 62
1128 12:44:01.098483 [Byte1]: 62
1129 12:44:01.102586
1130 12:44:01.103154 Set Vref, RX VrefLevel [Byte0]: 63
1131 12:44:01.106040 [Byte1]: 63
1132 12:44:01.110473
1133 12:44:01.111079 Set Vref, RX VrefLevel [Byte0]: 64
1134 12:44:01.113453 [Byte1]: 64
1135 12:44:01.118180
1136 12:44:01.118790 Set Vref, RX VrefLevel [Byte0]: 65
1137 12:44:01.121075 [Byte1]: 65
1138 12:44:01.125567
1139 12:44:01.126133 Set Vref, RX VrefLevel [Byte0]: 66
1140 12:44:01.128665 [Byte1]: 66
1141 12:44:01.133501
1142 12:44:01.134066 Set Vref, RX VrefLevel [Byte0]: 67
1143 12:44:01.136639 [Byte1]: 67
1144 12:44:01.140886
1145 12:44:01.141449 Set Vref, RX VrefLevel [Byte0]: 68
1146 12:44:01.144105 [Byte1]: 68
1147 12:44:01.148331
1148 12:44:01.149027 Set Vref, RX VrefLevel [Byte0]: 69
1149 12:44:01.151564 [Byte1]: 69
1150 12:44:01.156390
1151 12:44:01.156954 Set Vref, RX VrefLevel [Byte0]: 70
1152 12:44:01.162283 [Byte1]: 70
1153 12:44:01.162807
1154 12:44:01.165851 Set Vref, RX VrefLevel [Byte0]: 71
1155 12:44:01.169201 [Byte1]: 71
1156 12:44:01.169729
1157 12:44:01.172233 Set Vref, RX VrefLevel [Byte0]: 72
1158 12:44:01.175629 [Byte1]: 72
1159 12:44:01.178973
1160 12:44:01.179502 Set Vref, RX VrefLevel [Byte0]: 73
1161 12:44:01.182270 [Byte1]: 73
1162 12:44:01.186466
1163 12:44:01.187042 Set Vref, RX VrefLevel [Byte0]: 74
1164 12:44:01.189778 [Byte1]: 74
1165 12:44:01.193997
1166 12:44:01.194417 Set Vref, RX VrefLevel [Byte0]: 75
1167 12:44:01.197431 [Byte1]: 75
1168 12:44:01.202264
1169 12:44:01.202772 Set Vref, RX VrefLevel [Byte0]: 76
1170 12:44:01.205194 [Byte1]: 76
1171 12:44:01.210085
1172 12:44:01.210625 Set Vref, RX VrefLevel [Byte0]: 77
1173 12:44:01.212835 [Byte1]: 77
1174 12:44:01.216837
1175 12:44:01.217299 Set Vref, RX VrefLevel [Byte0]: 78
1176 12:44:01.220377 [Byte1]: 78
1177 12:44:01.224556
1178 12:44:01.225076 Final RX Vref Byte 0 = 55 to rank0
1179 12:44:01.228125 Final RX Vref Byte 1 = 57 to rank0
1180 12:44:01.231572 Final RX Vref Byte 0 = 55 to rank1
1181 12:44:01.234610 Final RX Vref Byte 1 = 57 to rank1==
1182 12:44:01.238289 Dram Type= 6, Freq= 0, CH_0, rank 0
1183 12:44:01.244452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1184 12:44:01.244968 ==
1185 12:44:01.245306 DQS Delay:
1186 12:44:01.247759 DQS0 = 0, DQS1 = 0
1187 12:44:01.248183 DQM Delay:
1188 12:44:01.248521 DQM0 = 82, DQM1 = 68
1189 12:44:01.251293 DQ Delay:
1190 12:44:01.254938 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1191 12:44:01.258199 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1192 12:44:01.260961 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1193 12:44:01.264403 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1194 12:44:01.264829
1195 12:44:01.265166
1196 12:44:01.271083 [DQSOSCAuto] RK0, (LSB)MR18= 0x2323, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
1197 12:44:01.274666 CH0 RK0: MR19=606, MR18=2323
1198 12:44:01.281355 CH0_RK0: MR19=0x606, MR18=0x2323, DQSOSC=401, MR23=63, INC=91, DEC=61
1199 12:44:01.281935
1200 12:44:01.284806 ----->DramcWriteLeveling(PI) begin...
1201 12:44:01.285283 ==
1202 12:44:01.287693 Dram Type= 6, Freq= 0, CH_0, rank 1
1203 12:44:01.290936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1204 12:44:01.291413 ==
1205 12:44:01.294323 Write leveling (Byte 0): 31 => 31
1206 12:44:01.298041 Write leveling (Byte 1): 31 => 31
1207 12:44:01.301363 DramcWriteLeveling(PI) end<-----
1208 12:44:01.301793
1209 12:44:01.302132 ==
1210 12:44:01.304420 Dram Type= 6, Freq= 0, CH_0, rank 1
1211 12:44:01.307438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1212 12:44:01.307864 ==
1213 12:44:01.311059 [Gating] SW mode calibration
1214 12:44:01.317875 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1215 12:44:01.324658 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1216 12:44:01.327677 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1217 12:44:01.331032 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1218 12:44:01.337943 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1219 12:44:01.341182 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 12:44:01.343989 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 12:44:01.350631 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 12:44:01.354073 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 12:44:01.357732 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 12:44:01.364111 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 12:44:01.367103 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 12:44:01.370808 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 12:44:01.377323 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 12:44:01.380851 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 12:44:01.384368 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 12:44:01.431668 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 12:44:01.432286 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 12:44:01.433043 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 12:44:01.433429 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1234 12:44:01.433785 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1235 12:44:01.434121 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 12:44:01.434451 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 12:44:01.434774 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 12:44:01.435152 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 12:44:01.435556 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 12:44:01.436238 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 12:44:01.436593 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 12:44:01.443576 0 9 8 | B1->B0 | 2323 2929 | 0 1 | (0 0) (1 1)
1243 12:44:01.446587 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1244 12:44:01.449838 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 12:44:01.456537 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 12:44:01.460034 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 12:44:01.462971 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 12:44:01.469532 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 12:44:01.473246 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1250 12:44:01.476143 0 10 8 | B1->B0 | 3030 2424 | 0 0 | (0 0) (0 0)
1251 12:44:01.482998 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 12:44:01.486201 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 12:44:01.489645 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 12:44:01.496288 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 12:44:01.499594 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 12:44:01.502986 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 12:44:01.509874 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 12:44:01.513263 0 11 8 | B1->B0 | 3030 3f3f | 0 0 | (0 0) (0 0)
1259 12:44:01.516048 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1260 12:44:01.523006 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 12:44:01.526103 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 12:44:01.529463 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 12:44:01.536117 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 12:44:01.539210 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 12:44:01.542792 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1266 12:44:01.549565 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1267 12:44:01.553041 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1268 12:44:01.556923 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 12:44:01.560413 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 12:44:01.563658 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 12:44:01.570476 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 12:44:01.574069 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 12:44:01.578416 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 12:44:01.584757 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 12:44:01.587923 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 12:44:01.591498 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 12:44:01.594483 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 12:44:01.601554 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 12:44:01.604732 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 12:44:01.607808 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 12:44:01.614770 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 12:44:01.617841 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1283 12:44:01.621175 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1284 12:44:01.624770 Total UI for P1: 0, mck2ui 16
1285 12:44:01.627625 best dqsien dly found for B0: ( 0, 14, 8)
1286 12:44:01.631201 Total UI for P1: 0, mck2ui 16
1287 12:44:01.634368 best dqsien dly found for B1: ( 0, 14, 10)
1288 12:44:01.637491 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1289 12:44:01.644331 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1290 12:44:01.644893
1291 12:44:01.647844 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1292 12:44:01.650727 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1293 12:44:01.654425 [Gating] SW calibration Done
1294 12:44:01.654939 ==
1295 12:44:01.657744 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 12:44:01.660936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 12:44:01.661505 ==
1298 12:44:01.661880 RX Vref Scan: 0
1299 12:44:01.664552
1300 12:44:01.665105 RX Vref 0 -> 0, step: 1
1301 12:44:01.665481
1302 12:44:01.667270 RX Delay -130 -> 252, step: 16
1303 12:44:01.670476 iDelay=206, Bit 0, Center 77 (-50 ~ 205) 256
1304 12:44:01.673667 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1305 12:44:01.680383 iDelay=206, Bit 2, Center 77 (-50 ~ 205) 256
1306 12:44:01.683806 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1307 12:44:01.687412 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1308 12:44:01.690983 iDelay=206, Bit 5, Center 61 (-66 ~ 189) 256
1309 12:44:01.694077 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1310 12:44:01.700742 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1311 12:44:01.703494 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1312 12:44:01.707200 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1313 12:44:01.710490 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1314 12:44:01.716773 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1315 12:44:01.720038 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1316 12:44:01.723329 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1317 12:44:01.726521 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1318 12:44:01.730451 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1319 12:44:01.733600 ==
1320 12:44:01.734070 Dram Type= 6, Freq= 0, CH_0, rank 1
1321 12:44:01.740309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1322 12:44:01.740875 ==
1323 12:44:01.741254 DQS Delay:
1324 12:44:01.743590 DQS0 = 0, DQS1 = 0
1325 12:44:01.744055 DQM Delay:
1326 12:44:01.746920 DQM0 = 76, DQM1 = 69
1327 12:44:01.747480 DQ Delay:
1328 12:44:01.750204 DQ0 =77, DQ1 =77, DQ2 =77, DQ3 =69
1329 12:44:01.753126 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =85
1330 12:44:01.756628 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1331 12:44:01.760258 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1332 12:44:01.760786
1333 12:44:01.761181
1334 12:44:01.761499 ==
1335 12:44:01.763559 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 12:44:01.766801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 12:44:01.767364 ==
1338 12:44:01.767709
1339 12:44:01.768021
1340 12:44:01.770083 TX Vref Scan disable
1341 12:44:01.773367 == TX Byte 0 ==
1342 12:44:01.776888 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1343 12:44:01.779841 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1344 12:44:01.783350 == TX Byte 1 ==
1345 12:44:01.786897 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1346 12:44:01.790005 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1347 12:44:01.790525 ==
1348 12:44:01.793185 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 12:44:01.796604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 12:44:01.799377 ==
1351 12:44:01.811101 TX Vref=22, minBit 11, minWin=26, winSum=434
1352 12:44:01.814546 TX Vref=24, minBit 1, minWin=27, winSum=437
1353 12:44:01.817604 TX Vref=26, minBit 1, minWin=27, winSum=441
1354 12:44:01.821040 TX Vref=28, minBit 11, minWin=26, winSum=444
1355 12:44:01.824491 TX Vref=30, minBit 11, minWin=26, winSum=444
1356 12:44:01.830600 TX Vref=32, minBit 8, minWin=27, winSum=442
1357 12:44:01.833811 [TxChooseVref] Worse bit 8, Min win 27, Win sum 442, Final Vref 32
1358 12:44:01.834281
1359 12:44:01.837547 Final TX Range 1 Vref 32
1360 12:44:01.837963
1361 12:44:01.838289 ==
1362 12:44:01.840743 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 12:44:01.844208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 12:44:01.847156 ==
1365 12:44:01.847569
1366 12:44:01.847893
1367 12:44:01.848196 TX Vref Scan disable
1368 12:44:01.851132 == TX Byte 0 ==
1369 12:44:01.854084 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1370 12:44:01.860615 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1371 12:44:01.861030 == TX Byte 1 ==
1372 12:44:01.864312 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1373 12:44:01.871429 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1374 12:44:01.871949
1375 12:44:01.872281 [DATLAT]
1376 12:44:01.872585 Freq=800, CH0 RK1
1377 12:44:01.872882
1378 12:44:01.874145 DATLAT Default: 0xa
1379 12:44:01.874557 0, 0xFFFF, sum = 0
1380 12:44:01.878201 1, 0xFFFF, sum = 0
1381 12:44:01.880830 2, 0xFFFF, sum = 0
1382 12:44:01.881255 3, 0xFFFF, sum = 0
1383 12:44:01.884401 4, 0xFFFF, sum = 0
1384 12:44:01.884923 5, 0xFFFF, sum = 0
1385 12:44:01.887504 6, 0xFFFF, sum = 0
1386 12:44:01.887931 7, 0xFFFF, sum = 0
1387 12:44:01.890571 8, 0xFFFF, sum = 0
1388 12:44:01.891036 9, 0x0, sum = 1
1389 12:44:01.893828 10, 0x0, sum = 2
1390 12:44:01.894249 11, 0x0, sum = 3
1391 12:44:01.894580 12, 0x0, sum = 4
1392 12:44:01.897413 best_step = 10
1393 12:44:01.897827
1394 12:44:01.898151 ==
1395 12:44:01.900606 Dram Type= 6, Freq= 0, CH_0, rank 1
1396 12:44:01.904191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1397 12:44:01.904609 ==
1398 12:44:01.907413 RX Vref Scan: 0
1399 12:44:01.907824
1400 12:44:01.910802 RX Vref 0 -> 0, step: 1
1401 12:44:01.911348
1402 12:44:01.911679 RX Delay -111 -> 252, step: 8
1403 12:44:01.917968 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1404 12:44:01.921036 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1405 12:44:01.924746 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1406 12:44:01.927746 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
1407 12:44:01.934586 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1408 12:44:01.937734 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1409 12:44:01.941002 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1410 12:44:01.944331 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1411 12:44:01.947571 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1412 12:44:01.953851 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1413 12:44:01.957620 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1414 12:44:01.960832 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1415 12:44:01.963858 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1416 12:44:01.967479 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1417 12:44:01.973587 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1418 12:44:01.977304 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1419 12:44:01.977718 ==
1420 12:44:01.980167 Dram Type= 6, Freq= 0, CH_0, rank 1
1421 12:44:01.984073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1422 12:44:01.984489 ==
1423 12:44:01.986893 DQS Delay:
1424 12:44:01.987252 DQS0 = 0, DQS1 = 0
1425 12:44:01.987482 DQM Delay:
1426 12:44:01.990133 DQM0 = 79, DQM1 = 70
1427 12:44:01.990424 DQ Delay:
1428 12:44:01.993669 DQ0 =80, DQ1 =84, DQ2 =76, DQ3 =76
1429 12:44:01.996866 DQ4 =76, DQ5 =64, DQ6 =88, DQ7 =92
1430 12:44:02.000293 DQ8 =60, DQ9 =56, DQ10 =72, DQ11 =64
1431 12:44:02.003252 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =76
1432 12:44:02.003403
1433 12:44:02.003519
1434 12:44:02.013757 [DQSOSCAuto] RK1, (LSB)MR18= 0x4924, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
1435 12:44:02.016518 CH0 RK1: MR19=606, MR18=4924
1436 12:44:02.019871 CH0_RK1: MR19=0x606, MR18=0x4924, DQSOSC=391, MR23=63, INC=96, DEC=64
1437 12:44:02.023305 [RxdqsGatingPostProcess] freq 800
1438 12:44:02.029864 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1439 12:44:02.033553 Pre-setting of DQS Precalculation
1440 12:44:02.036217 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1441 12:44:02.036373 ==
1442 12:44:02.039749 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 12:44:02.046515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 12:44:02.046718 ==
1445 12:44:02.049539 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1446 12:44:02.056270 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1447 12:44:02.066325 [CA 0] Center 36 (6~67) winsize 62
1448 12:44:02.069354 [CA 1] Center 36 (6~67) winsize 62
1449 12:44:02.072630 [CA 2] Center 34 (5~64) winsize 60
1450 12:44:02.076275 [CA 3] Center 34 (4~64) winsize 61
1451 12:44:02.079206 [CA 4] Center 35 (5~65) winsize 61
1452 12:44:02.082766 [CA 5] Center 34 (4~64) winsize 61
1453 12:44:02.083223
1454 12:44:02.086346 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1455 12:44:02.087111
1456 12:44:02.089363 [CATrainingPosCal] consider 1 rank data
1457 12:44:02.092651 u2DelayCellTimex100 = 270/100 ps
1458 12:44:02.095587 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1459 12:44:02.102637 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1460 12:44:02.105498 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1461 12:44:02.109229 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1462 12:44:02.112383 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1463 12:44:02.116011 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1464 12:44:02.116577
1465 12:44:02.119142 CA PerBit enable=1, Macro0, CA PI delay=34
1466 12:44:02.119610
1467 12:44:02.122709 [CBTSetCACLKResult] CA Dly = 34
1468 12:44:02.125470 CS Dly: 5 (0~36)
1469 12:44:02.126039 ==
1470 12:44:02.129081 Dram Type= 6, Freq= 0, CH_1, rank 1
1471 12:44:02.131951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1472 12:44:02.132422 ==
1473 12:44:02.138991 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1474 12:44:02.141970 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1475 12:44:02.152161 [CA 0] Center 37 (7~67) winsize 61
1476 12:44:02.155470 [CA 1] Center 36 (6~67) winsize 62
1477 12:44:02.158894 [CA 2] Center 35 (5~65) winsize 61
1478 12:44:02.162295 [CA 3] Center 34 (4~64) winsize 61
1479 12:44:02.165362 [CA 4] Center 34 (4~65) winsize 62
1480 12:44:02.168473 [CA 5] Center 33 (3~64) winsize 62
1481 12:44:02.168947
1482 12:44:02.171791 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1483 12:44:02.172261
1484 12:44:02.175464 [CATrainingPosCal] consider 2 rank data
1485 12:44:02.178957 u2DelayCellTimex100 = 270/100 ps
1486 12:44:02.182044 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1487 12:44:02.188842 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1488 12:44:02.191731 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1489 12:44:02.195431 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1490 12:44:02.198707 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1491 12:44:02.202086 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1492 12:44:02.202655
1493 12:44:02.205388 CA PerBit enable=1, Macro0, CA PI delay=34
1494 12:44:02.205958
1495 12:44:02.208786 [CBTSetCACLKResult] CA Dly = 34
1496 12:44:02.209350 CS Dly: 5 (0~37)
1497 12:44:02.209734
1498 12:44:02.212540 ----->DramcWriteLeveling(PI) begin...
1499 12:44:02.213147 ==
1500 12:44:02.216289 Dram Type= 6, Freq= 0, CH_1, rank 0
1501 12:44:02.219944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1502 12:44:02.223430 ==
1503 12:44:02.224045 Write leveling (Byte 0): 27 => 27
1504 12:44:02.227263 Write leveling (Byte 1): 29 => 29
1505 12:44:02.230744 DramcWriteLeveling(PI) end<-----
1506 12:44:02.231367
1507 12:44:02.231739 ==
1508 12:44:02.234721 Dram Type= 6, Freq= 0, CH_1, rank 0
1509 12:44:02.238149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1510 12:44:02.238616 ==
1511 12:44:02.241634 [Gating] SW mode calibration
1512 12:44:02.248680 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1513 12:44:02.255198 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1514 12:44:02.258231 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1515 12:44:02.261945 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1516 12:44:02.268573 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1517 12:44:02.271472 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 12:44:02.274711 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 12:44:02.281908 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 12:44:02.284718 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 12:44:02.288239 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 12:44:02.295119 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 12:44:02.297881 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 12:44:02.301573 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 12:44:02.304681 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 12:44:02.311609 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 12:44:02.314949 0 7 20 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1528 12:44:02.318452 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 12:44:02.324729 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 12:44:02.327611 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 12:44:02.331139 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 12:44:02.337974 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1533 12:44:02.341304 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 12:44:02.344333 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 12:44:02.351353 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 12:44:02.354130 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 12:44:02.357724 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 12:44:02.364191 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 12:44:02.367379 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1540 12:44:02.371026 0 9 8 | B1->B0 | 2929 2929 | 0 0 | (0 0) (0 0)
1541 12:44:02.377590 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 12:44:02.380788 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 12:44:02.383901 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 12:44:02.390982 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 12:44:02.393914 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 12:44:02.397581 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 12:44:02.404162 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 12:44:02.407670 0 10 8 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (0 0)
1549 12:44:02.410857 0 10 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1550 12:44:02.417487 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 12:44:02.420629 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 12:44:02.424431 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 12:44:02.430464 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 12:44:02.434015 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 12:44:02.437290 0 11 4 | B1->B0 | 2525 2727 | 0 0 | (0 0) (1 1)
1556 12:44:02.443616 0 11 8 | B1->B0 | 3939 3737 | 1 0 | (0 0) (0 0)
1557 12:44:02.447007 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 12:44:02.450498 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 12:44:02.457061 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 12:44:02.460369 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 12:44:02.463388 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 12:44:02.470304 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 12:44:02.473973 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 12:44:02.476710 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1565 12:44:02.483667 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 12:44:02.486747 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 12:44:02.489887 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 12:44:02.496832 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 12:44:02.499997 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 12:44:02.503444 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 12:44:02.509826 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 12:44:02.513501 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 12:44:02.516662 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 12:44:02.523312 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 12:44:02.526440 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 12:44:02.530201 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 12:44:02.536596 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 12:44:02.540076 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 12:44:02.542940 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 12:44:02.550053 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1581 12:44:02.550627 Total UI for P1: 0, mck2ui 16
1582 12:44:02.553034 best dqsien dly found for B0: ( 0, 14, 6)
1583 12:44:02.559973 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1584 12:44:02.562786 Total UI for P1: 0, mck2ui 16
1585 12:44:02.566699 best dqsien dly found for B1: ( 0, 14, 8)
1586 12:44:02.569559 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1587 12:44:02.572893 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1588 12:44:02.573367
1589 12:44:02.575809 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1590 12:44:02.579753 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1591 12:44:02.582797 [Gating] SW calibration Done
1592 12:44:02.583404 ==
1593 12:44:02.586392 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 12:44:02.589790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 12:44:02.590365 ==
1596 12:44:02.592737 RX Vref Scan: 0
1597 12:44:02.593311
1598 12:44:02.595838 RX Vref 0 -> 0, step: 1
1599 12:44:02.596307
1600 12:44:02.596697 RX Delay -130 -> 252, step: 16
1601 12:44:02.602450 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1602 12:44:02.606240 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1603 12:44:02.609279 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1604 12:44:02.612654 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1605 12:44:02.615773 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1606 12:44:02.622603 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1607 12:44:02.625659 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1608 12:44:02.629403 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1609 12:44:02.632216 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1610 12:44:02.635794 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1611 12:44:02.642389 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1612 12:44:02.645742 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1613 12:44:02.648959 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1614 12:44:02.652122 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1615 12:44:02.658896 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1616 12:44:02.662247 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1617 12:44:02.662721 ==
1618 12:44:02.665887 Dram Type= 6, Freq= 0, CH_1, rank 0
1619 12:44:02.668738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1620 12:44:02.669309 ==
1621 12:44:02.672080 DQS Delay:
1622 12:44:02.672545 DQS0 = 0, DQS1 = 0
1623 12:44:02.672914 DQM Delay:
1624 12:44:02.675560 DQM0 = 81, DQM1 = 70
1625 12:44:02.676025 DQ Delay:
1626 12:44:02.678679 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1627 12:44:02.682391 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1628 12:44:02.685202 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1629 12:44:02.689162 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1630 12:44:02.689732
1631 12:44:02.690103
1632 12:44:02.690449 ==
1633 12:44:02.691785 Dram Type= 6, Freq= 0, CH_1, rank 0
1634 12:44:02.698952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1635 12:44:02.699515 ==
1636 12:44:02.699928
1637 12:44:02.700290
1638 12:44:02.700623 TX Vref Scan disable
1639 12:44:02.701708 == TX Byte 0 ==
1640 12:44:02.705063 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1641 12:44:02.711781 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1642 12:44:02.712255 == TX Byte 1 ==
1643 12:44:02.715034 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1644 12:44:02.721512 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1645 12:44:02.722094 ==
1646 12:44:02.724769 Dram Type= 6, Freq= 0, CH_1, rank 0
1647 12:44:02.728436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1648 12:44:02.728907 ==
1649 12:44:02.740776 TX Vref=22, minBit 1, minWin=27, winSum=440
1650 12:44:02.744507 TX Vref=24, minBit 1, minWin=26, winSum=440
1651 12:44:02.747334 TX Vref=26, minBit 1, minWin=27, winSum=445
1652 12:44:02.751080 TX Vref=28, minBit 1, minWin=27, winSum=445
1653 12:44:02.754885 TX Vref=30, minBit 5, minWin=27, winSum=448
1654 12:44:02.760864 TX Vref=32, minBit 0, minWin=27, winSum=446
1655 12:44:02.764197 [TxChooseVref] Worse bit 5, Min win 27, Win sum 448, Final Vref 30
1656 12:44:02.764665
1657 12:44:02.768255 Final TX Range 1 Vref 30
1658 12:44:02.768822
1659 12:44:02.769197 ==
1660 12:44:02.770891 Dram Type= 6, Freq= 0, CH_1, rank 0
1661 12:44:02.774417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1662 12:44:02.775025 ==
1663 12:44:02.777259
1664 12:44:02.777722
1665 12:44:02.778089 TX Vref Scan disable
1666 12:44:02.780988 == TX Byte 0 ==
1667 12:44:02.784567 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1668 12:44:02.788152 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1669 12:44:02.791406 == TX Byte 1 ==
1670 12:44:02.794995 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1671 12:44:02.798473 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1672 12:44:02.799085
1673 12:44:02.801022 [DATLAT]
1674 12:44:02.801493 Freq=800, CH1 RK0
1675 12:44:02.801866
1676 12:44:02.804644 DATLAT Default: 0xa
1677 12:44:02.805110 0, 0xFFFF, sum = 0
1678 12:44:02.807774 1, 0xFFFF, sum = 0
1679 12:44:02.808253 2, 0xFFFF, sum = 0
1680 12:44:02.811319 3, 0xFFFF, sum = 0
1681 12:44:02.811793 4, 0xFFFF, sum = 0
1682 12:44:02.815110 5, 0xFFFF, sum = 0
1683 12:44:02.815688 6, 0xFFFF, sum = 0
1684 12:44:02.818032 7, 0xFFFF, sum = 0
1685 12:44:02.818515 8, 0xFFFF, sum = 0
1686 12:44:02.821258 9, 0x0, sum = 1
1687 12:44:02.821767 10, 0x0, sum = 2
1688 12:44:02.824483 11, 0x0, sum = 3
1689 12:44:02.824960 12, 0x0, sum = 4
1690 12:44:02.827861 best_step = 10
1691 12:44:02.828325
1692 12:44:02.828724 ==
1693 12:44:02.831020 Dram Type= 6, Freq= 0, CH_1, rank 0
1694 12:44:02.834211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1695 12:44:02.834682 ==
1696 12:44:02.837833 RX Vref Scan: 1
1697 12:44:02.838301
1698 12:44:02.838668 Set Vref Range= 32 -> 127
1699 12:44:02.839132
1700 12:44:02.841204 RX Vref 32 -> 127, step: 1
1701 12:44:02.841763
1702 12:44:02.844459 RX Delay -111 -> 252, step: 8
1703 12:44:02.844929
1704 12:44:02.847428 Set Vref, RX VrefLevel [Byte0]: 32
1705 12:44:02.851233 [Byte1]: 32
1706 12:44:02.851801
1707 12:44:02.854001 Set Vref, RX VrefLevel [Byte0]: 33
1708 12:44:02.857606 [Byte1]: 33
1709 12:44:02.861497
1710 12:44:02.862083 Set Vref, RX VrefLevel [Byte0]: 34
1711 12:44:02.864851 [Byte1]: 34
1712 12:44:02.869032
1713 12:44:02.869616 Set Vref, RX VrefLevel [Byte0]: 35
1714 12:44:02.871962 [Byte1]: 35
1715 12:44:02.876706
1716 12:44:02.877267 Set Vref, RX VrefLevel [Byte0]: 36
1717 12:44:02.880175 [Byte1]: 36
1718 12:44:02.884145
1719 12:44:02.884615 Set Vref, RX VrefLevel [Byte0]: 37
1720 12:44:02.887701 [Byte1]: 37
1721 12:44:02.891832
1722 12:44:02.892393 Set Vref, RX VrefLevel [Byte0]: 38
1723 12:44:02.895236 [Byte1]: 38
1724 12:44:02.899323
1725 12:44:02.899937 Set Vref, RX VrefLevel [Byte0]: 39
1726 12:44:02.902697 [Byte1]: 39
1727 12:44:02.906666
1728 12:44:02.907175 Set Vref, RX VrefLevel [Byte0]: 40
1729 12:44:02.910325 [Byte1]: 40
1730 12:44:02.914614
1731 12:44:02.915160 Set Vref, RX VrefLevel [Byte0]: 41
1732 12:44:02.918137 [Byte1]: 41
1733 12:44:02.922584
1734 12:44:02.923086 Set Vref, RX VrefLevel [Byte0]: 42
1735 12:44:02.925677 [Byte1]: 42
1736 12:44:02.930124
1737 12:44:02.930696 Set Vref, RX VrefLevel [Byte0]: 43
1738 12:44:02.933356 [Byte1]: 43
1739 12:44:02.937856
1740 12:44:02.938426 Set Vref, RX VrefLevel [Byte0]: 44
1741 12:44:02.941103 [Byte1]: 44
1742 12:44:02.945535
1743 12:44:02.946133 Set Vref, RX VrefLevel [Byte0]: 45
1744 12:44:02.948680 [Byte1]: 45
1745 12:44:02.953376
1746 12:44:02.953932 Set Vref, RX VrefLevel [Byte0]: 46
1747 12:44:02.956183 [Byte1]: 46
1748 12:44:02.960876
1749 12:44:02.961344 Set Vref, RX VrefLevel [Byte0]: 47
1750 12:44:02.963882 [Byte1]: 47
1751 12:44:02.968299
1752 12:44:02.968861 Set Vref, RX VrefLevel [Byte0]: 48
1753 12:44:02.971764 [Byte1]: 48
1754 12:44:02.975831
1755 12:44:02.976394 Set Vref, RX VrefLevel [Byte0]: 49
1756 12:44:02.979026 [Byte1]: 49
1757 12:44:02.983780
1758 12:44:02.984343 Set Vref, RX VrefLevel [Byte0]: 50
1759 12:44:02.987055 [Byte1]: 50
1760 12:44:02.991117
1761 12:44:02.991679 Set Vref, RX VrefLevel [Byte0]: 51
1762 12:44:02.994367 [Byte1]: 51
1763 12:44:02.998804
1764 12:44:02.999403 Set Vref, RX VrefLevel [Byte0]: 52
1765 12:44:03.002448 [Byte1]: 52
1766 12:44:03.006453
1767 12:44:03.007108 Set Vref, RX VrefLevel [Byte0]: 53
1768 12:44:03.009590 [Byte1]: 53
1769 12:44:03.014686
1770 12:44:03.015288 Set Vref, RX VrefLevel [Byte0]: 54
1771 12:44:03.017669 [Byte1]: 54
1772 12:44:03.021852
1773 12:44:03.022414 Set Vref, RX VrefLevel [Byte0]: 55
1774 12:44:03.024841 [Byte1]: 55
1775 12:44:03.029693
1776 12:44:03.030251 Set Vref, RX VrefLevel [Byte0]: 56
1777 12:44:03.032547 [Byte1]: 56
1778 12:44:03.037471
1779 12:44:03.038046 Set Vref, RX VrefLevel [Byte0]: 57
1780 12:44:03.040400 [Byte1]: 57
1781 12:44:03.044756
1782 12:44:03.045219 Set Vref, RX VrefLevel [Byte0]: 58
1783 12:44:03.048024 [Byte1]: 58
1784 12:44:03.052608
1785 12:44:03.053168 Set Vref, RX VrefLevel [Byte0]: 59
1786 12:44:03.058932 [Byte1]: 59
1787 12:44:03.059401
1788 12:44:03.061898 Set Vref, RX VrefLevel [Byte0]: 60
1789 12:44:03.066059 [Byte1]: 60
1790 12:44:03.066622
1791 12:44:03.068489 Set Vref, RX VrefLevel [Byte0]: 61
1792 12:44:03.072078 [Byte1]: 61
1793 12:44:03.075374
1794 12:44:03.075939 Set Vref, RX VrefLevel [Byte0]: 62
1795 12:44:03.078478 [Byte1]: 62
1796 12:44:03.083481
1797 12:44:03.084044 Set Vref, RX VrefLevel [Byte0]: 63
1798 12:44:03.086460 [Byte1]: 63
1799 12:44:03.090775
1800 12:44:03.091377 Set Vref, RX VrefLevel [Byte0]: 64
1801 12:44:03.094058 [Byte1]: 64
1802 12:44:03.097970
1803 12:44:03.098434 Set Vref, RX VrefLevel [Byte0]: 65
1804 12:44:03.101595 [Byte1]: 65
1805 12:44:03.105774
1806 12:44:03.106238 Set Vref, RX VrefLevel [Byte0]: 66
1807 12:44:03.109598 [Byte1]: 66
1808 12:44:03.113992
1809 12:44:03.114560 Set Vref, RX VrefLevel [Byte0]: 67
1810 12:44:03.116972 [Byte1]: 67
1811 12:44:03.121128
1812 12:44:03.121686 Set Vref, RX VrefLevel [Byte0]: 68
1813 12:44:03.124527 [Byte1]: 68
1814 12:44:03.128682
1815 12:44:03.129148 Set Vref, RX VrefLevel [Byte0]: 69
1816 12:44:03.132373 [Byte1]: 69
1817 12:44:03.136906
1818 12:44:03.137475 Set Vref, RX VrefLevel [Byte0]: 70
1819 12:44:03.139780 [Byte1]: 70
1820 12:44:03.144208
1821 12:44:03.144674 Set Vref, RX VrefLevel [Byte0]: 71
1822 12:44:03.147459 [Byte1]: 71
1823 12:44:03.151791
1824 12:44:03.152258 Set Vref, RX VrefLevel [Byte0]: 72
1825 12:44:03.154939 [Byte1]: 72
1826 12:44:03.159439
1827 12:44:03.159907 Set Vref, RX VrefLevel [Byte0]: 73
1828 12:44:03.162654 [Byte1]: 73
1829 12:44:03.167301
1830 12:44:03.167767 Set Vref, RX VrefLevel [Byte0]: 74
1831 12:44:03.170205 [Byte1]: 74
1832 12:44:03.175191
1833 12:44:03.175657 Final RX Vref Byte 0 = 58 to rank0
1834 12:44:03.177982 Final RX Vref Byte 1 = 54 to rank0
1835 12:44:03.181841 Final RX Vref Byte 0 = 58 to rank1
1836 12:44:03.184543 Final RX Vref Byte 1 = 54 to rank1==
1837 12:44:03.188219 Dram Type= 6, Freq= 0, CH_1, rank 0
1838 12:44:03.194505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1839 12:44:03.195105 ==
1840 12:44:03.195487 DQS Delay:
1841 12:44:03.198048 DQS0 = 0, DQS1 = 0
1842 12:44:03.198611 DQM Delay:
1843 12:44:03.199035 DQM0 = 81, DQM1 = 71
1844 12:44:03.201675 DQ Delay:
1845 12:44:03.204319 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1846 12:44:03.208263 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1847 12:44:03.210805 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1848 12:44:03.214130 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1849 12:44:03.214597
1850 12:44:03.215007
1851 12:44:03.221179 [DQSOSCAuto] RK0, (LSB)MR18= 0xc15, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 406 ps
1852 12:44:03.224948 CH1 RK0: MR19=606, MR18=C15
1853 12:44:03.231127 CH1_RK0: MR19=0x606, MR18=0xC15, DQSOSC=404, MR23=63, INC=90, DEC=60
1854 12:44:03.231600
1855 12:44:03.234714 ----->DramcWriteLeveling(PI) begin...
1856 12:44:03.235319 ==
1857 12:44:03.237939 Dram Type= 6, Freq= 0, CH_1, rank 1
1858 12:44:03.240844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1859 12:44:03.241347 ==
1860 12:44:03.244485 Write leveling (Byte 0): 27 => 27
1861 12:44:03.247607 Write leveling (Byte 1): 28 => 28
1862 12:44:03.251269 DramcWriteLeveling(PI) end<-----
1863 12:44:03.251837
1864 12:44:03.252208 ==
1865 12:44:03.254473 Dram Type= 6, Freq= 0, CH_1, rank 1
1866 12:44:03.257707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1867 12:44:03.258196 ==
1868 12:44:03.260834 [Gating] SW mode calibration
1869 12:44:03.267548 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1870 12:44:03.274074 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1871 12:44:03.277622 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1872 12:44:03.280826 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1873 12:44:03.287259 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1874 12:44:03.290890 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 12:44:03.293737 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 12:44:03.301041 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 12:44:03.303567 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 12:44:03.307205 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 12:44:03.314187 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 12:44:03.316818 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 12:44:03.320174 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 12:44:03.326578 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 12:44:03.330268 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 12:44:03.333487 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 12:44:03.340376 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 12:44:03.343650 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 12:44:03.346402 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1888 12:44:03.353081 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1889 12:44:03.356589 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 12:44:03.359437 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 12:44:03.366759 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 12:44:03.369755 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 12:44:03.373225 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 12:44:03.379699 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 12:44:03.382735 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 12:44:03.386448 0 9 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1897 12:44:03.392611 0 9 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1898 12:44:03.396164 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 12:44:03.399119 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 12:44:03.406175 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 12:44:03.409492 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 12:44:03.412381 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 12:44:03.419503 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1904 12:44:03.422441 0 10 4 | B1->B0 | 3131 2d2d | 1 0 | (1 0) (0 0)
1905 12:44:03.425891 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
1906 12:44:03.432190 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 12:44:03.436009 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 12:44:03.438879 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 12:44:03.445708 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 12:44:03.449139 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 12:44:03.452191 0 11 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1912 12:44:03.459395 0 11 4 | B1->B0 | 2c2c 3636 | 1 1 | (0 0) (0 0)
1913 12:44:03.462122 0 11 8 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
1914 12:44:03.465797 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 12:44:03.472699 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 12:44:03.475614 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 12:44:03.478971 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 12:44:03.485496 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 12:44:03.488991 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 12:44:03.492372 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1921 12:44:03.498723 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1922 12:44:03.501666 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 12:44:03.505145 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 12:44:03.512366 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 12:44:03.515523 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 12:44:03.518990 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 12:44:03.525421 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 12:44:03.528670 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 12:44:03.531552 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 12:44:03.538728 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 12:44:03.542155 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 12:44:03.545555 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 12:44:03.551763 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 12:44:03.555152 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 12:44:03.558199 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 12:44:03.565290 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1937 12:44:03.568040 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1938 12:44:03.571902 Total UI for P1: 0, mck2ui 16
1939 12:44:03.574750 best dqsien dly found for B0: ( 0, 14, 4)
1940 12:44:03.577985 Total UI for P1: 0, mck2ui 16
1941 12:44:03.581651 best dqsien dly found for B1: ( 0, 14, 6)
1942 12:44:03.584912 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1943 12:44:03.588269 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1944 12:44:03.588731
1945 12:44:03.591573 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1946 12:44:03.594996 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1947 12:44:03.598144 [Gating] SW calibration Done
1948 12:44:03.598712 ==
1949 12:44:03.601675 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 12:44:03.604816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 12:44:03.605456 ==
1952 12:44:03.607787 RX Vref Scan: 0
1953 12:44:03.608265
1954 12:44:03.611377 RX Vref 0 -> 0, step: 1
1955 12:44:03.611885
1956 12:44:03.612359 RX Delay -130 -> 252, step: 16
1957 12:44:03.617888 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1958 12:44:03.621246 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1959 12:44:03.624672 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1960 12:44:03.627738 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1961 12:44:03.631205 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1962 12:44:03.637792 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1963 12:44:03.641164 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1964 12:44:03.644370 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1965 12:44:03.647779 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1966 12:44:03.650950 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1967 12:44:03.657620 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1968 12:44:03.660625 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1969 12:44:03.664231 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1970 12:44:03.667734 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1971 12:44:03.674090 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1972 12:44:03.677704 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1973 12:44:03.678126 ==
1974 12:44:03.681085 Dram Type= 6, Freq= 0, CH_1, rank 1
1975 12:44:03.684611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1976 12:44:03.685163 ==
1977 12:44:03.685504 DQS Delay:
1978 12:44:03.687698 DQS0 = 0, DQS1 = 0
1979 12:44:03.688117 DQM Delay:
1980 12:44:03.690629 DQM0 = 80, DQM1 = 77
1981 12:44:03.691093 DQ Delay:
1982 12:44:03.694061 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1983 12:44:03.697367 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1984 12:44:03.700763 DQ8 =61, DQ9 =61, DQ10 =85, DQ11 =69
1985 12:44:03.704190 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1986 12:44:03.704719
1987 12:44:03.705058
1988 12:44:03.705365 ==
1989 12:44:03.707374 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 12:44:03.710939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 12:44:03.714480 ==
1992 12:44:03.715053
1993 12:44:03.715420
1994 12:44:03.715736 TX Vref Scan disable
1995 12:44:03.717212 == TX Byte 0 ==
1996 12:44:03.720814 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1997 12:44:03.723769 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1998 12:44:03.727291 == TX Byte 1 ==
1999 12:44:03.730775 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2000 12:44:03.733824 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2001 12:44:03.737464 ==
2002 12:44:03.740306 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 12:44:03.743322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 12:44:03.743744 ==
2005 12:44:03.756014 TX Vref=22, minBit 5, minWin=27, winSum=447
2006 12:44:03.759300 TX Vref=24, minBit 6, minWin=27, winSum=453
2007 12:44:03.762552 TX Vref=26, minBit 0, minWin=28, winSum=457
2008 12:44:03.766311 TX Vref=28, minBit 1, minWin=27, winSum=458
2009 12:44:03.769415 TX Vref=30, minBit 1, minWin=28, winSum=460
2010 12:44:03.776313 TX Vref=32, minBit 5, minWin=27, winSum=460
2011 12:44:03.779342 [TxChooseVref] Worse bit 1, Min win 28, Win sum 460, Final Vref 30
2012 12:44:03.779815
2013 12:44:03.782312 Final TX Range 1 Vref 30
2014 12:44:03.782739
2015 12:44:03.783161 ==
2016 12:44:03.786321 Dram Type= 6, Freq= 0, CH_1, rank 1
2017 12:44:03.788952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2018 12:44:03.789379 ==
2019 12:44:03.792251
2020 12:44:03.792670
2021 12:44:03.793008 TX Vref Scan disable
2022 12:44:03.795813 == TX Byte 0 ==
2023 12:44:03.799031 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2024 12:44:03.806113 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2025 12:44:03.806536 == TX Byte 1 ==
2026 12:44:03.809578 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2027 12:44:03.815932 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2028 12:44:03.816356
2029 12:44:03.816689 [DATLAT]
2030 12:44:03.817002 Freq=800, CH1 RK1
2031 12:44:03.817302
2032 12:44:03.818941 DATLAT Default: 0xa
2033 12:44:03.819364 0, 0xFFFF, sum = 0
2034 12:44:03.822669 1, 0xFFFF, sum = 0
2035 12:44:03.823132 2, 0xFFFF, sum = 0
2036 12:44:03.825528 3, 0xFFFF, sum = 0
2037 12:44:03.829200 4, 0xFFFF, sum = 0
2038 12:44:03.829629 5, 0xFFFF, sum = 0
2039 12:44:03.832648 6, 0xFFFF, sum = 0
2040 12:44:03.833077 7, 0xFFFF, sum = 0
2041 12:44:03.835603 8, 0xFFFF, sum = 0
2042 12:44:03.836028 9, 0x0, sum = 1
2043 12:44:03.839075 10, 0x0, sum = 2
2044 12:44:03.839503 11, 0x0, sum = 3
2045 12:44:03.839863 12, 0x0, sum = 4
2046 12:44:03.842091 best_step = 10
2047 12:44:03.842511
2048 12:44:03.842885 ==
2049 12:44:03.845713 Dram Type= 6, Freq= 0, CH_1, rank 1
2050 12:44:03.848830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2051 12:44:03.849253 ==
2052 12:44:03.852567 RX Vref Scan: 0
2053 12:44:03.852988
2054 12:44:03.855698 RX Vref 0 -> 0, step: 1
2055 12:44:03.856127
2056 12:44:03.856480 RX Delay -111 -> 252, step: 8
2057 12:44:03.862467 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2058 12:44:03.866390 iDelay=209, Bit 1, Center 68 (-55 ~ 192) 248
2059 12:44:03.869179 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
2060 12:44:03.873047 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2061 12:44:03.876270 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2062 12:44:03.882763 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2063 12:44:03.885746 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2064 12:44:03.889651 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2065 12:44:03.892391 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2066 12:44:03.895844 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2067 12:44:03.902249 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2068 12:44:03.906023 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2069 12:44:03.908809 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2070 12:44:03.912483 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2071 12:44:03.919183 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2072 12:44:03.922669 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2073 12:44:03.923146 ==
2074 12:44:03.925564 Dram Type= 6, Freq= 0, CH_1, rank 1
2075 12:44:03.929143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2076 12:44:03.929566 ==
2077 12:44:03.932731 DQS Delay:
2078 12:44:03.933148 DQS0 = 0, DQS1 = 0
2079 12:44:03.933482 DQM Delay:
2080 12:44:03.936047 DQM0 = 76, DQM1 = 73
2081 12:44:03.936571 DQ Delay:
2082 12:44:03.939405 DQ0 =80, DQ1 =68, DQ2 =64, DQ3 =72
2083 12:44:03.942287 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2084 12:44:03.945599 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
2085 12:44:03.948884 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2086 12:44:03.949301
2087 12:44:03.949632
2088 12:44:03.958734 [DQSOSCAuto] RK1, (LSB)MR18= 0x2139, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2089 12:44:03.959286 CH1 RK1: MR19=606, MR18=2139
2090 12:44:03.965408 CH1_RK1: MR19=0x606, MR18=0x2139, DQSOSC=395, MR23=63, INC=94, DEC=63
2091 12:44:03.968891 [RxdqsGatingPostProcess] freq 800
2092 12:44:03.975640 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2093 12:44:03.978965 Pre-setting of DQS Precalculation
2094 12:44:03.982608 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2095 12:44:03.989063 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2096 12:44:03.998925 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2097 12:44:03.999541
2098 12:44:03.999927
2099 12:44:04.001615 [Calibration Summary] 1600 Mbps
2100 12:44:04.002243 CH 0, Rank 0
2101 12:44:04.004946 SW Impedance : PASS
2102 12:44:04.005584 DUTY Scan : NO K
2103 12:44:04.008742 ZQ Calibration : PASS
2104 12:44:04.011683 Jitter Meter : NO K
2105 12:44:04.012275 CBT Training : PASS
2106 12:44:04.015078 Write leveling : PASS
2107 12:44:04.015554 RX DQS gating : PASS
2108 12:44:04.018354 RX DQ/DQS(RDDQC) : PASS
2109 12:44:04.021650 TX DQ/DQS : PASS
2110 12:44:04.022123 RX DATLAT : PASS
2111 12:44:04.024888 RX DQ/DQS(Engine): PASS
2112 12:44:04.028670 TX OE : NO K
2113 12:44:04.029143 All Pass.
2114 12:44:04.029708
2115 12:44:04.030097 CH 0, Rank 1
2116 12:44:04.031461 SW Impedance : PASS
2117 12:44:04.035246 DUTY Scan : NO K
2118 12:44:04.035862 ZQ Calibration : PASS
2119 12:44:04.038269 Jitter Meter : NO K
2120 12:44:04.041906 CBT Training : PASS
2121 12:44:04.042336 Write leveling : PASS
2122 12:44:04.044826 RX DQS gating : PASS
2123 12:44:04.048425 RX DQ/DQS(RDDQC) : PASS
2124 12:44:04.048852 TX DQ/DQS : PASS
2125 12:44:04.052015 RX DATLAT : PASS
2126 12:44:04.054901 RX DQ/DQS(Engine): PASS
2127 12:44:04.055381 TX OE : NO K
2128 12:44:04.058271 All Pass.
2129 12:44:04.058738
2130 12:44:04.059109 CH 1, Rank 0
2131 12:44:04.061905 SW Impedance : PASS
2132 12:44:04.062370 DUTY Scan : NO K
2133 12:44:04.064958 ZQ Calibration : PASS
2134 12:44:04.068489 Jitter Meter : NO K
2135 12:44:04.068913 CBT Training : PASS
2136 12:44:04.072061 Write leveling : PASS
2137 12:44:04.072589 RX DQS gating : PASS
2138 12:44:04.074848 RX DQ/DQS(RDDQC) : PASS
2139 12:44:04.077912 TX DQ/DQS : PASS
2140 12:44:04.078337 RX DATLAT : PASS
2141 12:44:04.081191 RX DQ/DQS(Engine): PASS
2142 12:44:04.084873 TX OE : NO K
2143 12:44:04.085545 All Pass.
2144 12:44:04.085905
2145 12:44:04.086222 CH 1, Rank 1
2146 12:44:04.087960 SW Impedance : PASS
2147 12:44:04.091455 DUTY Scan : NO K
2148 12:44:04.091878 ZQ Calibration : PASS
2149 12:44:04.095103 Jitter Meter : NO K
2150 12:44:04.098146 CBT Training : PASS
2151 12:44:04.098677 Write leveling : PASS
2152 12:44:04.101512 RX DQS gating : PASS
2153 12:44:04.104527 RX DQ/DQS(RDDQC) : PASS
2154 12:44:04.104951 TX DQ/DQS : PASS
2155 12:44:04.108174 RX DATLAT : PASS
2156 12:44:04.111494 RX DQ/DQS(Engine): PASS
2157 12:44:04.111927 TX OE : NO K
2158 12:44:04.114672 All Pass.
2159 12:44:04.115250
2160 12:44:04.115596 DramC Write-DBI off
2161 12:44:04.118193 PER_BANK_REFRESH: Hybrid Mode
2162 12:44:04.118744 TX_TRACKING: ON
2163 12:44:04.121652 [GetDramInforAfterCalByMRR] Vendor 6.
2164 12:44:04.127675 [GetDramInforAfterCalByMRR] Revision 606.
2165 12:44:04.130978 [GetDramInforAfterCalByMRR] Revision 2 0.
2166 12:44:04.131405 MR0 0x3b3b
2167 12:44:04.131743 MR8 0x5151
2168 12:44:04.134360 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2169 12:44:04.134784
2170 12:44:04.137811 MR0 0x3b3b
2171 12:44:04.138332 MR8 0x5151
2172 12:44:04.141145 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2173 12:44:04.141567
2174 12:44:04.151411 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2175 12:44:04.154505 [FAST_K] Save calibration result to emmc
2176 12:44:04.158296 [FAST_K] Save calibration result to emmc
2177 12:44:04.160898 dram_init: config_dvfs: 1
2178 12:44:04.164457 dramc_set_vcore_voltage set vcore to 662500
2179 12:44:04.167670 Read voltage for 1200, 2
2180 12:44:04.168138 Vio18 = 0
2181 12:44:04.168569 Vcore = 662500
2182 12:44:04.170966 Vdram = 0
2183 12:44:04.171430 Vddq = 0
2184 12:44:04.171799 Vmddr = 0
2185 12:44:04.178032 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2186 12:44:04.181030 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2187 12:44:04.184355 MEM_TYPE=3, freq_sel=15
2188 12:44:04.187698 sv_algorithm_assistance_LP4_1600
2189 12:44:04.190575 ============ PULL DRAM RESETB DOWN ============
2190 12:44:04.193799 ========== PULL DRAM RESETB DOWN end =========
2191 12:44:04.200636 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2192 12:44:04.204194 ===================================
2193 12:44:04.204767 LPDDR4 DRAM CONFIGURATION
2194 12:44:04.207302 ===================================
2195 12:44:04.210819 EX_ROW_EN[0] = 0x0
2196 12:44:04.213941 EX_ROW_EN[1] = 0x0
2197 12:44:04.214422 LP4Y_EN = 0x0
2198 12:44:04.217607 WORK_FSP = 0x0
2199 12:44:04.218144 WL = 0x4
2200 12:44:04.220561 RL = 0x4
2201 12:44:04.221085 BL = 0x2
2202 12:44:04.224210 RPST = 0x0
2203 12:44:04.224700 RD_PRE = 0x0
2204 12:44:04.227179 WR_PRE = 0x1
2205 12:44:04.227652 WR_PST = 0x0
2206 12:44:04.230464 DBI_WR = 0x0
2207 12:44:04.230964 DBI_RD = 0x0
2208 12:44:04.234490 OTF = 0x1
2209 12:44:04.237561 ===================================
2210 12:44:04.240374 ===================================
2211 12:44:04.240867 ANA top config
2212 12:44:04.244193 ===================================
2213 12:44:04.247264 DLL_ASYNC_EN = 0
2214 12:44:04.250189 ALL_SLAVE_EN = 0
2215 12:44:04.253787 NEW_RANK_MODE = 1
2216 12:44:04.254259 DLL_IDLE_MODE = 1
2217 12:44:04.257335 LP45_APHY_COMB_EN = 1
2218 12:44:04.260351 TX_ODT_DIS = 1
2219 12:44:04.263709 NEW_8X_MODE = 1
2220 12:44:04.267384 ===================================
2221 12:44:04.270372 ===================================
2222 12:44:04.273655 data_rate = 2400
2223 12:44:04.274229 CKR = 1
2224 12:44:04.277007 DQ_P2S_RATIO = 8
2225 12:44:04.280198 ===================================
2226 12:44:04.283468 CA_P2S_RATIO = 8
2227 12:44:04.286907 DQ_CA_OPEN = 0
2228 12:44:04.290532 DQ_SEMI_OPEN = 0
2229 12:44:04.293582 CA_SEMI_OPEN = 0
2230 12:44:04.294047 CA_FULL_RATE = 0
2231 12:44:04.296531 DQ_CKDIV4_EN = 0
2232 12:44:04.300118 CA_CKDIV4_EN = 0
2233 12:44:04.303323 CA_PREDIV_EN = 0
2234 12:44:04.307155 PH8_DLY = 17
2235 12:44:04.310111 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2236 12:44:04.310594 DQ_AAMCK_DIV = 4
2237 12:44:04.313876 CA_AAMCK_DIV = 4
2238 12:44:04.317130 CA_ADMCK_DIV = 4
2239 12:44:04.320361 DQ_TRACK_CA_EN = 0
2240 12:44:04.323456 CA_PICK = 1200
2241 12:44:04.326803 CA_MCKIO = 1200
2242 12:44:04.330448 MCKIO_SEMI = 0
2243 12:44:04.330991 PLL_FREQ = 2366
2244 12:44:04.333295 DQ_UI_PI_RATIO = 32
2245 12:44:04.336766 CA_UI_PI_RATIO = 0
2246 12:44:04.339864 ===================================
2247 12:44:04.343241 ===================================
2248 12:44:04.346597 memory_type:LPDDR4
2249 12:44:04.349746 GP_NUM : 10
2250 12:44:04.350266 SRAM_EN : 1
2251 12:44:04.353868 MD32_EN : 0
2252 12:44:04.356534 ===================================
2253 12:44:04.359915 [ANA_INIT] >>>>>>>>>>>>>>
2254 12:44:04.360386 <<<<<< [CONFIGURE PHASE]: ANA_TX
2255 12:44:04.362889 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2256 12:44:04.366261 ===================================
2257 12:44:04.369684 data_rate = 2400,PCW = 0X5b00
2258 12:44:04.373431 ===================================
2259 12:44:04.376473 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2260 12:44:04.382973 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2261 12:44:04.389496 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2262 12:44:04.392837 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2263 12:44:04.396375 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2264 12:44:04.399259 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2265 12:44:04.402963 [ANA_INIT] flow start
2266 12:44:04.403433 [ANA_INIT] PLL >>>>>>>>
2267 12:44:04.405896 [ANA_INIT] PLL <<<<<<<<
2268 12:44:04.409246 [ANA_INIT] MIDPI >>>>>>>>
2269 12:44:04.412469 [ANA_INIT] MIDPI <<<<<<<<
2270 12:44:04.412940 [ANA_INIT] DLL >>>>>>>>
2271 12:44:04.415763 [ANA_INIT] DLL <<<<<<<<
2272 12:44:04.416234 [ANA_INIT] flow end
2273 12:44:04.422570 ============ LP4 DIFF to SE enter ============
2274 12:44:04.426134 ============ LP4 DIFF to SE exit ============
2275 12:44:04.428917 [ANA_INIT] <<<<<<<<<<<<<
2276 12:44:04.432909 [Flow] Enable top DCM control >>>>>
2277 12:44:04.436039 [Flow] Enable top DCM control <<<<<
2278 12:44:04.436467 Enable DLL master slave shuffle
2279 12:44:04.442633 ==============================================================
2280 12:44:04.445782 Gating Mode config
2281 12:44:04.449417 ==============================================================
2282 12:44:04.452069 Config description:
2283 12:44:04.462396 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2284 12:44:04.468880 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2285 12:44:04.472292 SELPH_MODE 0: By rank 1: By Phase
2286 12:44:04.478631 ==============================================================
2287 12:44:04.482163 GAT_TRACK_EN = 1
2288 12:44:04.485594 RX_GATING_MODE = 2
2289 12:44:04.488897 RX_GATING_TRACK_MODE = 2
2290 12:44:04.492065 SELPH_MODE = 1
2291 12:44:04.495332 PICG_EARLY_EN = 1
2292 12:44:04.495761 VALID_LAT_VALUE = 1
2293 12:44:04.502366 ==============================================================
2294 12:44:04.505356 Enter into Gating configuration >>>>
2295 12:44:04.508834 Exit from Gating configuration <<<<
2296 12:44:04.511866 Enter into DVFS_PRE_config >>>>>
2297 12:44:04.521976 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2298 12:44:04.525308 Exit from DVFS_PRE_config <<<<<
2299 12:44:04.528435 Enter into PICG configuration >>>>
2300 12:44:04.531825 Exit from PICG configuration <<<<
2301 12:44:04.534962 [RX_INPUT] configuration >>>>>
2302 12:44:04.538424 [RX_INPUT] configuration <<<<<
2303 12:44:04.545196 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2304 12:44:04.548113 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2305 12:44:04.554672 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2306 12:44:04.561108 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2307 12:44:04.568159 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2308 12:44:04.574655 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2309 12:44:04.578198 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2310 12:44:04.581049 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2311 12:44:04.584534 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2312 12:44:04.591199 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2313 12:44:04.594873 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2314 12:44:04.597755 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2315 12:44:04.601297 ===================================
2316 12:44:04.604646 LPDDR4 DRAM CONFIGURATION
2317 12:44:04.607260 ===================================
2318 12:44:04.610700 EX_ROW_EN[0] = 0x0
2319 12:44:04.611305 EX_ROW_EN[1] = 0x0
2320 12:44:04.614171 LP4Y_EN = 0x0
2321 12:44:04.614653 WORK_FSP = 0x0
2322 12:44:04.617654 WL = 0x4
2323 12:44:04.618120 RL = 0x4
2324 12:44:04.620721 BL = 0x2
2325 12:44:04.621287 RPST = 0x0
2326 12:44:04.623858 RD_PRE = 0x0
2327 12:44:04.624352 WR_PRE = 0x1
2328 12:44:04.627281 WR_PST = 0x0
2329 12:44:04.627747 DBI_WR = 0x0
2330 12:44:04.630601 DBI_RD = 0x0
2331 12:44:04.631096 OTF = 0x1
2332 12:44:04.633952 ===================================
2333 12:44:04.640632 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2334 12:44:04.643628 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2335 12:44:04.647525 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2336 12:44:04.650490 ===================================
2337 12:44:04.653801 LPDDR4 DRAM CONFIGURATION
2338 12:44:04.657344 ===================================
2339 12:44:04.660158 EX_ROW_EN[0] = 0x10
2340 12:44:04.660622 EX_ROW_EN[1] = 0x0
2341 12:44:04.663689 LP4Y_EN = 0x0
2342 12:44:04.664157 WORK_FSP = 0x0
2343 12:44:04.667069 WL = 0x4
2344 12:44:04.667560 RL = 0x4
2345 12:44:04.670302 BL = 0x2
2346 12:44:04.670774 RPST = 0x0
2347 12:44:04.673949 RD_PRE = 0x0
2348 12:44:04.674528 WR_PRE = 0x1
2349 12:44:04.676877 WR_PST = 0x0
2350 12:44:04.677348 DBI_WR = 0x0
2351 12:44:04.680186 DBI_RD = 0x0
2352 12:44:04.680833 OTF = 0x1
2353 12:44:04.683694 ===================================
2354 12:44:04.690293 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2355 12:44:04.690891 ==
2356 12:44:04.693460 Dram Type= 6, Freq= 0, CH_0, rank 0
2357 12:44:04.700372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2358 12:44:04.700966 ==
2359 12:44:04.701487 [Duty_Offset_Calibration]
2360 12:44:04.703712 B0:2 B1:0 CA:3
2361 12:44:04.704171
2362 12:44:04.706611 [DutyScan_Calibration_Flow] k_type=0
2363 12:44:04.715585
2364 12:44:04.716043 ==CLK 0==
2365 12:44:04.718965 Final CLK duty delay cell = 0
2366 12:44:04.721944 [0] MAX Duty = 5031%(X100), DQS PI = 12
2367 12:44:04.725394 [0] MIN Duty = 4875%(X100), DQS PI = 58
2368 12:44:04.725861 [0] AVG Duty = 4953%(X100)
2369 12:44:04.728908
2370 12:44:04.729319 CH0 CLK Duty spec in!! Max-Min= 156%
2371 12:44:04.735941 [DutyScan_Calibration_Flow] ====Done====
2372 12:44:04.736369
2373 12:44:04.738454 [DutyScan_Calibration_Flow] k_type=1
2374 12:44:04.754125
2375 12:44:04.754446 ==DQS 0 ==
2376 12:44:04.757415 Final DQS duty delay cell = 0
2377 12:44:04.760523 [0] MAX Duty = 5093%(X100), DQS PI = 12
2378 12:44:04.764009 [0] MIN Duty = 4907%(X100), DQS PI = 44
2379 12:44:04.767420 [0] AVG Duty = 5000%(X100)
2380 12:44:04.767956
2381 12:44:04.768479 ==DQS 1 ==
2382 12:44:04.770347 Final DQS duty delay cell = -4
2383 12:44:04.774080 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2384 12:44:04.777192 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2385 12:44:04.780160 [-4] AVG Duty = 4922%(X100)
2386 12:44:04.780613
2387 12:44:04.783573 CH0 DQS 0 Duty spec in!! Max-Min= 186%
2388 12:44:04.784050
2389 12:44:04.787002 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2390 12:44:04.790556 [DutyScan_Calibration_Flow] ====Done====
2391 12:44:04.791182
2392 12:44:04.793707 [DutyScan_Calibration_Flow] k_type=3
2393 12:44:04.811672
2394 12:44:04.812223 ==DQM 0 ==
2395 12:44:04.815055 Final DQM duty delay cell = 0
2396 12:44:04.818211 [0] MAX Duty = 5124%(X100), DQS PI = 28
2397 12:44:04.821484 [0] MIN Duty = 4876%(X100), DQS PI = 0
2398 12:44:04.821940 [0] AVG Duty = 5000%(X100)
2399 12:44:04.824826
2400 12:44:04.825277 ==DQM 1 ==
2401 12:44:04.828487 Final DQM duty delay cell = 4
2402 12:44:04.831602 [4] MAX Duty = 5124%(X100), DQS PI = 50
2403 12:44:04.834812 [4] MIN Duty = 5000%(X100), DQS PI = 14
2404 12:44:04.838074 [4] AVG Duty = 5062%(X100)
2405 12:44:04.838534
2406 12:44:04.841403 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2407 12:44:04.841857
2408 12:44:04.844872 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2409 12:44:04.848488 [DutyScan_Calibration_Flow] ====Done====
2410 12:44:04.848949
2411 12:44:04.851027 [DutyScan_Calibration_Flow] k_type=2
2412 12:44:04.866609
2413 12:44:04.867112 ==DQ 0 ==
2414 12:44:04.869793 Final DQ duty delay cell = -4
2415 12:44:04.873215 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2416 12:44:04.876562 [-4] MIN Duty = 4907%(X100), DQS PI = 50
2417 12:44:04.879660 [-4] AVG Duty = 4969%(X100)
2418 12:44:04.880118
2419 12:44:04.880538 ==DQ 1 ==
2420 12:44:04.882893 Final DQ duty delay cell = -4
2421 12:44:04.886170 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2422 12:44:04.889734 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2423 12:44:04.892970 [-4] AVG Duty = 4922%(X100)
2424 12:44:04.893536
2425 12:44:04.896093 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2426 12:44:04.896562
2427 12:44:04.899504 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2428 12:44:04.902822 [DutyScan_Calibration_Flow] ====Done====
2429 12:44:04.903463 ==
2430 12:44:04.906062 Dram Type= 6, Freq= 0, CH_1, rank 0
2431 12:44:04.909182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2432 12:44:04.909649 ==
2433 12:44:04.912746 [Duty_Offset_Calibration]
2434 12:44:04.913265 B0:1 B1:-2 CA:0
2435 12:44:04.916223
2436 12:44:04.919043 [DutyScan_Calibration_Flow] k_type=0
2437 12:44:04.927789
2438 12:44:04.928298 ==CLK 0==
2439 12:44:04.930669 Final CLK duty delay cell = 4
2440 12:44:04.934036 [4] MAX Duty = 5156%(X100), DQS PI = 0
2441 12:44:04.937543 [4] MIN Duty = 5031%(X100), DQS PI = 24
2442 12:44:04.938029 [4] AVG Duty = 5093%(X100)
2443 12:44:04.941127
2444 12:44:04.944490 CH1 CLK Duty spec in!! Max-Min= 125%
2445 12:44:04.947727 [DutyScan_Calibration_Flow] ====Done====
2446 12:44:04.948288
2447 12:44:04.951082 [DutyScan_Calibration_Flow] k_type=1
2448 12:44:04.966252
2449 12:44:04.966787 ==DQS 0 ==
2450 12:44:04.969071 Final DQS duty delay cell = -4
2451 12:44:04.972903 [-4] MAX Duty = 5000%(X100), DQS PI = 56
2452 12:44:04.975873 [-4] MIN Duty = 4907%(X100), DQS PI = 4
2453 12:44:04.979169 [-4] AVG Duty = 4953%(X100)
2454 12:44:04.979639
2455 12:44:04.980009 ==DQS 1 ==
2456 12:44:04.982374 Final DQS duty delay cell = 0
2457 12:44:04.985815 [0] MAX Duty = 5093%(X100), DQS PI = 32
2458 12:44:04.989168 [0] MIN Duty = 4844%(X100), DQS PI = 58
2459 12:44:04.992444 [0] AVG Duty = 4968%(X100)
2460 12:44:04.992911
2461 12:44:04.995800 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2462 12:44:04.996269
2463 12:44:04.999438 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2464 12:44:05.003142 [DutyScan_Calibration_Flow] ====Done====
2465 12:44:05.003718
2466 12:44:05.005737 [DutyScan_Calibration_Flow] k_type=3
2467 12:44:05.023080
2468 12:44:05.023634 ==DQM 0 ==
2469 12:44:05.026114 Final DQM duty delay cell = 0
2470 12:44:05.029394 [0] MAX Duty = 5000%(X100), DQS PI = 54
2471 12:44:05.032656 [0] MIN Duty = 4876%(X100), DQS PI = 18
2472 12:44:05.036226 [0] AVG Duty = 4938%(X100)
2473 12:44:05.036692
2474 12:44:05.037114 ==DQM 1 ==
2475 12:44:05.039370 Final DQM duty delay cell = 0
2476 12:44:05.042600 [0] MAX Duty = 5031%(X100), DQS PI = 4
2477 12:44:05.045954 [0] MIN Duty = 4907%(X100), DQS PI = 46
2478 12:44:05.049273 [0] AVG Duty = 4969%(X100)
2479 12:44:05.049751
2480 12:44:05.052309 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2481 12:44:05.052810
2482 12:44:05.055765 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2483 12:44:05.058783 [DutyScan_Calibration_Flow] ====Done====
2484 12:44:05.059290
2485 12:44:05.062163 [DutyScan_Calibration_Flow] k_type=2
2486 12:44:05.079141
2487 12:44:05.079713 ==DQ 0 ==
2488 12:44:05.082341 Final DQ duty delay cell = 0
2489 12:44:05.085956 [0] MAX Duty = 5093%(X100), DQS PI = 52
2490 12:44:05.089527 [0] MIN Duty = 4938%(X100), DQS PI = 24
2491 12:44:05.090108 [0] AVG Duty = 5015%(X100)
2492 12:44:05.092534
2493 12:44:05.093011 ==DQ 1 ==
2494 12:44:05.096062 Final DQ duty delay cell = 0
2495 12:44:05.098999 [0] MAX Duty = 5156%(X100), DQS PI = 14
2496 12:44:05.102424 [0] MIN Duty = 4969%(X100), DQS PI = 58
2497 12:44:05.103067 [0] AVG Duty = 5062%(X100)
2498 12:44:05.103546
2499 12:44:05.106078 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2500 12:44:05.108857
2501 12:44:05.112570 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2502 12:44:05.115360 [DutyScan_Calibration_Flow] ====Done====
2503 12:44:05.119078 nWR fixed to 30
2504 12:44:05.119667 [ModeRegInit_LP4] CH0 RK0
2505 12:44:05.122575 [ModeRegInit_LP4] CH0 RK1
2506 12:44:05.125635 [ModeRegInit_LP4] CH1 RK0
2507 12:44:05.128806 [ModeRegInit_LP4] CH1 RK1
2508 12:44:05.129284 match AC timing 7
2509 12:44:05.135506 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2510 12:44:05.139037 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2511 12:44:05.142129 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2512 12:44:05.148550 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2513 12:44:05.151669 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2514 12:44:05.152247 ==
2515 12:44:05.155225 Dram Type= 6, Freq= 0, CH_0, rank 0
2516 12:44:05.158820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 12:44:05.159453 ==
2518 12:44:05.165246 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2519 12:44:05.171569 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2520 12:44:05.179192 [CA 0] Center 40 (10~71) winsize 62
2521 12:44:05.182754 [CA 1] Center 39 (9~70) winsize 62
2522 12:44:05.185855 [CA 2] Center 36 (6~66) winsize 61
2523 12:44:05.189152 [CA 3] Center 35 (5~66) winsize 62
2524 12:44:05.192737 [CA 4] Center 34 (4~65) winsize 62
2525 12:44:05.196058 [CA 5] Center 33 (3~64) winsize 62
2526 12:44:05.196650
2527 12:44:05.199313 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2528 12:44:05.199791
2529 12:44:05.202363 [CATrainingPosCal] consider 1 rank data
2530 12:44:05.205512 u2DelayCellTimex100 = 270/100 ps
2531 12:44:05.208818 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2532 12:44:05.215382 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2533 12:44:05.219110 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2534 12:44:05.222176 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2535 12:44:05.225554 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2536 12:44:05.228921 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2537 12:44:05.229392
2538 12:44:05.231959 CA PerBit enable=1, Macro0, CA PI delay=33
2539 12:44:05.232426
2540 12:44:05.235575 [CBTSetCACLKResult] CA Dly = 33
2541 12:44:05.238450 CS Dly: 7 (0~38)
2542 12:44:05.238985 ==
2543 12:44:05.241897 Dram Type= 6, Freq= 0, CH_0, rank 1
2544 12:44:05.244950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2545 12:44:05.245421 ==
2546 12:44:05.252083 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2547 12:44:05.255100 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2548 12:44:05.265021 [CA 0] Center 40 (10~70) winsize 61
2549 12:44:05.268645 [CA 1] Center 39 (9~70) winsize 62
2550 12:44:05.272399 [CA 2] Center 35 (5~66) winsize 62
2551 12:44:05.274939 [CA 3] Center 35 (5~66) winsize 62
2552 12:44:05.278346 [CA 4] Center 34 (4~65) winsize 62
2553 12:44:05.281863 [CA 5] Center 33 (3~64) winsize 62
2554 12:44:05.282331
2555 12:44:05.285545 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2556 12:44:05.286126
2557 12:44:05.289004 [CATrainingPosCal] consider 2 rank data
2558 12:44:05.291786 u2DelayCellTimex100 = 270/100 ps
2559 12:44:05.295709 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2560 12:44:05.301879 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2561 12:44:05.305325 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2562 12:44:05.308464 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2563 12:44:05.311521 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2564 12:44:05.315041 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2565 12:44:05.315740
2566 12:44:05.318220 CA PerBit enable=1, Macro0, CA PI delay=33
2567 12:44:05.318689
2568 12:44:05.321344 [CBTSetCACLKResult] CA Dly = 33
2569 12:44:05.324812 CS Dly: 8 (0~40)
2570 12:44:05.325433
2571 12:44:05.327793 ----->DramcWriteLeveling(PI) begin...
2572 12:44:05.328279 ==
2573 12:44:05.331478 Dram Type= 6, Freq= 0, CH_0, rank 0
2574 12:44:05.334311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2575 12:44:05.334823 ==
2576 12:44:05.337866 Write leveling (Byte 0): 33 => 33
2577 12:44:05.341361 Write leveling (Byte 1): 29 => 29
2578 12:44:05.344745 DramcWriteLeveling(PI) end<-----
2579 12:44:05.345240
2580 12:44:05.345716 ==
2581 12:44:05.347742 Dram Type= 6, Freq= 0, CH_0, rank 0
2582 12:44:05.351353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2583 12:44:05.351837 ==
2584 12:44:05.355006 [Gating] SW mode calibration
2585 12:44:05.361284 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2586 12:44:05.367578 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2587 12:44:05.370939 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2588 12:44:05.374437 0 15 4 | B1->B0 | 2626 3333 | 1 1 | (1 1) (1 1)
2589 12:44:05.380960 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 12:44:05.384678 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2591 12:44:05.387563 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2592 12:44:05.394536 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2593 12:44:05.397553 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2594 12:44:05.400975 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2595 12:44:05.407382 1 0 0 | B1->B0 | 3030 2b2b | 1 0 | (1 1) (0 1)
2596 12:44:05.410961 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2597 12:44:05.414265 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 12:44:05.420680 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 12:44:05.423975 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2600 12:44:05.427312 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 12:44:05.434436 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2602 12:44:05.437350 1 0 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
2603 12:44:05.440907 1 1 0 | B1->B0 | 2d2d 3a3a | 0 1 | (0 0) (0 0)
2604 12:44:05.447258 1 1 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2605 12:44:05.450705 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 12:44:05.453641 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 12:44:05.460922 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 12:44:05.463708 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 12:44:05.466964 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 12:44:05.473962 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2611 12:44:05.477667 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2612 12:44:05.480474 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 12:44:05.487123 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 12:44:05.490487 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 12:44:05.493602 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 12:44:05.497076 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 12:44:05.503354 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 12:44:05.507150 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 12:44:05.510454 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 12:44:05.517102 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 12:44:05.520061 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 12:44:05.523383 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 12:44:05.530266 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 12:44:05.533548 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 12:44:05.536863 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 12:44:05.543410 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 12:44:05.546478 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2628 12:44:05.549882 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2629 12:44:05.553222 Total UI for P1: 0, mck2ui 16
2630 12:44:05.557011 best dqsien dly found for B0: ( 1, 4, 0)
2631 12:44:05.563009 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2632 12:44:05.566770 Total UI for P1: 0, mck2ui 16
2633 12:44:05.569727 best dqsien dly found for B1: ( 1, 4, 4)
2634 12:44:05.573135 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2635 12:44:05.576728 best DQS1 dly(MCK, UI, PI) = (1, 4, 4)
2636 12:44:05.577226
2637 12:44:05.579549 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2638 12:44:05.583079 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 4)
2639 12:44:05.586367 [Gating] SW calibration Done
2640 12:44:05.586882 ==
2641 12:44:05.589636 Dram Type= 6, Freq= 0, CH_0, rank 0
2642 12:44:05.593127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2643 12:44:05.593622 ==
2644 12:44:05.596222 RX Vref Scan: 0
2645 12:44:05.596717
2646 12:44:05.597089 RX Vref 0 -> 0, step: 1
2647 12:44:05.597480
2648 12:44:05.599662 RX Delay -40 -> 252, step: 8
2649 12:44:05.603170 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2650 12:44:05.609476 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2651 12:44:05.613286 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2652 12:44:05.616011 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2653 12:44:05.619458 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2654 12:44:05.622443 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2655 12:44:05.629377 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2656 12:44:05.632743 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2657 12:44:05.635837 iDelay=200, Bit 8, Center 95 (16 ~ 175) 160
2658 12:44:05.638986 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2659 12:44:05.642145 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2660 12:44:05.648993 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2661 12:44:05.652459 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2662 12:44:05.655682 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2663 12:44:05.659235 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2664 12:44:05.665709 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2665 12:44:05.666226 ==
2666 12:44:05.669262 Dram Type= 6, Freq= 0, CH_0, rank 0
2667 12:44:05.672311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2668 12:44:05.672773 ==
2669 12:44:05.673112 DQS Delay:
2670 12:44:05.675513 DQS0 = 0, DQS1 = 0
2671 12:44:05.675933 DQM Delay:
2672 12:44:05.678970 DQM0 = 112, DQM1 = 103
2673 12:44:05.679481 DQ Delay:
2674 12:44:05.682258 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2675 12:44:05.685559 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2676 12:44:05.689007 DQ8 =95, DQ9 =87, DQ10 =103, DQ11 =99
2677 12:44:05.692195 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2678 12:44:05.692623
2679 12:44:05.692957
2680 12:44:05.693268 ==
2681 12:44:05.695499 Dram Type= 6, Freq= 0, CH_0, rank 0
2682 12:44:05.702160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2683 12:44:05.702615 ==
2684 12:44:05.703111
2685 12:44:05.703559
2686 12:44:05.703991 TX Vref Scan disable
2687 12:44:05.705909 == TX Byte 0 ==
2688 12:44:05.708746 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2689 12:44:05.715550 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2690 12:44:05.716000 == TX Byte 1 ==
2691 12:44:05.718896 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2692 12:44:05.725313 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2693 12:44:05.725741 ==
2694 12:44:05.728932 Dram Type= 6, Freq= 0, CH_0, rank 0
2695 12:44:05.731851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2696 12:44:05.732282 ==
2697 12:44:05.744127 TX Vref=22, minBit 11, minWin=25, winSum=417
2698 12:44:05.747356 TX Vref=24, minBit 1, minWin=26, winSum=423
2699 12:44:05.750247 TX Vref=26, minBit 4, minWin=26, winSum=432
2700 12:44:05.753557 TX Vref=28, minBit 8, minWin=26, winSum=434
2701 12:44:05.756906 TX Vref=30, minBit 10, minWin=26, winSum=432
2702 12:44:05.763646 TX Vref=32, minBit 2, minWin=26, winSum=427
2703 12:44:05.766796 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 28
2704 12:44:05.767242
2705 12:44:05.769842 Final TX Range 1 Vref 28
2706 12:44:05.770268
2707 12:44:05.770604 ==
2708 12:44:05.773546 Dram Type= 6, Freq= 0, CH_0, rank 0
2709 12:44:05.776816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2710 12:44:05.780234 ==
2711 12:44:05.780671
2712 12:44:05.781006
2713 12:44:05.781320 TX Vref Scan disable
2714 12:44:05.783694 == TX Byte 0 ==
2715 12:44:05.787052 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2716 12:44:05.793755 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2717 12:44:05.794185 == TX Byte 1 ==
2718 12:44:05.796861 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2719 12:44:05.803588 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2720 12:44:05.804018
2721 12:44:05.804354 [DATLAT]
2722 12:44:05.804665 Freq=1200, CH0 RK0
2723 12:44:05.804969
2724 12:44:05.806782 DATLAT Default: 0xd
2725 12:44:05.810113 0, 0xFFFF, sum = 0
2726 12:44:05.810574 1, 0xFFFF, sum = 0
2727 12:44:05.813223 2, 0xFFFF, sum = 0
2728 12:44:05.813699 3, 0xFFFF, sum = 0
2729 12:44:05.816501 4, 0xFFFF, sum = 0
2730 12:44:05.817066 5, 0xFFFF, sum = 0
2731 12:44:05.819819 6, 0xFFFF, sum = 0
2732 12:44:05.820379 7, 0xFFFF, sum = 0
2733 12:44:05.823416 8, 0xFFFF, sum = 0
2734 12:44:05.823880 9, 0xFFFF, sum = 0
2735 12:44:05.826847 10, 0xFFFF, sum = 0
2736 12:44:05.827416 11, 0xFFFF, sum = 0
2737 12:44:05.829739 12, 0x0, sum = 1
2738 12:44:05.830242 13, 0x0, sum = 2
2739 12:44:05.833311 14, 0x0, sum = 3
2740 12:44:05.833744 15, 0x0, sum = 4
2741 12:44:05.836323 best_step = 13
2742 12:44:05.836764
2743 12:44:05.837096 ==
2744 12:44:05.839806 Dram Type= 6, Freq= 0, CH_0, rank 0
2745 12:44:05.843118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2746 12:44:05.843542 ==
2747 12:44:05.846552 RX Vref Scan: 1
2748 12:44:05.847023
2749 12:44:05.847371 Set Vref Range= 32 -> 127
2750 12:44:05.847689
2751 12:44:05.849772 RX Vref 32 -> 127, step: 1
2752 12:44:05.850197
2753 12:44:05.852825 RX Delay -37 -> 252, step: 4
2754 12:44:05.853250
2755 12:44:05.856278 Set Vref, RX VrefLevel [Byte0]: 32
2756 12:44:05.859694 [Byte1]: 32
2757 12:44:05.860117
2758 12:44:05.863114 Set Vref, RX VrefLevel [Byte0]: 33
2759 12:44:05.865819 [Byte1]: 33
2760 12:44:05.870468
2761 12:44:05.871088 Set Vref, RX VrefLevel [Byte0]: 34
2762 12:44:05.873842 [Byte1]: 34
2763 12:44:05.878648
2764 12:44:05.879114 Set Vref, RX VrefLevel [Byte0]: 35
2765 12:44:05.881421 [Byte1]: 35
2766 12:44:05.886506
2767 12:44:05.886991 Set Vref, RX VrefLevel [Byte0]: 36
2768 12:44:05.889631 [Byte1]: 36
2769 12:44:05.894343
2770 12:44:05.894938 Set Vref, RX VrefLevel [Byte0]: 37
2771 12:44:05.897706 [Byte1]: 37
2772 12:44:05.902558
2773 12:44:05.903014 Set Vref, RX VrefLevel [Byte0]: 38
2774 12:44:05.905405 [Byte1]: 38
2775 12:44:05.910168
2776 12:44:05.910754 Set Vref, RX VrefLevel [Byte0]: 39
2777 12:44:05.913388 [Byte1]: 39
2778 12:44:05.918078
2779 12:44:05.918692 Set Vref, RX VrefLevel [Byte0]: 40
2780 12:44:05.921514 [Byte1]: 40
2781 12:44:05.926001
2782 12:44:05.926471 Set Vref, RX VrefLevel [Byte0]: 41
2783 12:44:05.929734 [Byte1]: 41
2784 12:44:05.934222
2785 12:44:05.934743 Set Vref, RX VrefLevel [Byte0]: 42
2786 12:44:05.937798 [Byte1]: 42
2787 12:44:05.942072
2788 12:44:05.942652 Set Vref, RX VrefLevel [Byte0]: 43
2789 12:44:05.945387 [Byte1]: 43
2790 12:44:05.950579
2791 12:44:05.951056 Set Vref, RX VrefLevel [Byte0]: 44
2792 12:44:05.953499 [Byte1]: 44
2793 12:44:05.958392
2794 12:44:05.958886 Set Vref, RX VrefLevel [Byte0]: 45
2795 12:44:05.961809 [Byte1]: 45
2796 12:44:05.966249
2797 12:44:05.966801 Set Vref, RX VrefLevel [Byte0]: 46
2798 12:44:05.969628 [Byte1]: 46
2799 12:44:05.974435
2800 12:44:05.974937 Set Vref, RX VrefLevel [Byte0]: 47
2801 12:44:05.977814 [Byte1]: 47
2802 12:44:05.982501
2803 12:44:05.983070 Set Vref, RX VrefLevel [Byte0]: 48
2804 12:44:05.985659 [Byte1]: 48
2805 12:44:05.990349
2806 12:44:05.990918 Set Vref, RX VrefLevel [Byte0]: 49
2807 12:44:05.993817 [Byte1]: 49
2808 12:44:05.998036
2809 12:44:06.001483 Set Vref, RX VrefLevel [Byte0]: 50
2810 12:44:06.004587 [Byte1]: 50
2811 12:44:06.005109
2812 12:44:06.008190 Set Vref, RX VrefLevel [Byte0]: 51
2813 12:44:06.011282 [Byte1]: 51
2814 12:44:06.011828
2815 12:44:06.014822 Set Vref, RX VrefLevel [Byte0]: 52
2816 12:44:06.017804 [Byte1]: 52
2817 12:44:06.022033
2818 12:44:06.022452 Set Vref, RX VrefLevel [Byte0]: 53
2819 12:44:06.025735 [Byte1]: 53
2820 12:44:06.030367
2821 12:44:06.030785 Set Vref, RX VrefLevel [Byte0]: 54
2822 12:44:06.033808 [Byte1]: 54
2823 12:44:06.038470
2824 12:44:06.038968 Set Vref, RX VrefLevel [Byte0]: 55
2825 12:44:06.041852 [Byte1]: 55
2826 12:44:06.046566
2827 12:44:06.047081 Set Vref, RX VrefLevel [Byte0]: 56
2828 12:44:06.049466 [Byte1]: 56
2829 12:44:06.054106
2830 12:44:06.054560 Set Vref, RX VrefLevel [Byte0]: 57
2831 12:44:06.057625 [Byte1]: 57
2832 12:44:06.062265
2833 12:44:06.062885 Set Vref, RX VrefLevel [Byte0]: 58
2834 12:44:06.065422 [Byte1]: 58
2835 12:44:06.070312
2836 12:44:06.070923 Set Vref, RX VrefLevel [Byte0]: 59
2837 12:44:06.073726 [Byte1]: 59
2838 12:44:06.078340
2839 12:44:06.078952 Set Vref, RX VrefLevel [Byte0]: 60
2840 12:44:06.081798 [Byte1]: 60
2841 12:44:06.086349
2842 12:44:06.086768 Set Vref, RX VrefLevel [Byte0]: 61
2843 12:44:06.089962 [Byte1]: 61
2844 12:44:06.094002
2845 12:44:06.094556 Set Vref, RX VrefLevel [Byte0]: 62
2846 12:44:06.100917 [Byte1]: 62
2847 12:44:06.101414
2848 12:44:06.103781 Set Vref, RX VrefLevel [Byte0]: 63
2849 12:44:06.107529 [Byte1]: 63
2850 12:44:06.108104
2851 12:44:06.110331 Set Vref, RX VrefLevel [Byte0]: 64
2852 12:44:06.114056 [Byte1]: 64
2853 12:44:06.118147
2854 12:44:06.118723 Set Vref, RX VrefLevel [Byte0]: 65
2855 12:44:06.121815 [Byte1]: 65
2856 12:44:06.126473
2857 12:44:06.127097 Set Vref, RX VrefLevel [Byte0]: 66
2858 12:44:06.129476 [Byte1]: 66
2859 12:44:06.134466
2860 12:44:06.135068 Set Vref, RX VrefLevel [Byte0]: 67
2861 12:44:06.137591 [Byte1]: 67
2862 12:44:06.142060
2863 12:44:06.142461 Set Vref, RX VrefLevel [Byte0]: 68
2864 12:44:06.145323 [Byte1]: 68
2865 12:44:06.150239
2866 12:44:06.150660 Set Vref, RX VrefLevel [Byte0]: 69
2867 12:44:06.153799 [Byte1]: 69
2868 12:44:06.158365
2869 12:44:06.158784 Set Vref, RX VrefLevel [Byte0]: 70
2870 12:44:06.161262 [Byte1]: 70
2871 12:44:06.166121
2872 12:44:06.166543 Set Vref, RX VrefLevel [Byte0]: 71
2873 12:44:06.169822 [Byte1]: 71
2874 12:44:06.174169
2875 12:44:06.174790 Set Vref, RX VrefLevel [Byte0]: 72
2876 12:44:06.177326 [Byte1]: 72
2877 12:44:06.182238
2878 12:44:06.182665 Set Vref, RX VrefLevel [Byte0]: 73
2879 12:44:06.185556 [Byte1]: 73
2880 12:44:06.190145
2881 12:44:06.190572 Set Vref, RX VrefLevel [Byte0]: 74
2882 12:44:06.193490 [Byte1]: 74
2883 12:44:06.198215
2884 12:44:06.198666 Final RX Vref Byte 0 = 61 to rank0
2885 12:44:06.201594 Final RX Vref Byte 1 = 48 to rank0
2886 12:44:06.205146 Final RX Vref Byte 0 = 61 to rank1
2887 12:44:06.208215 Final RX Vref Byte 1 = 48 to rank1==
2888 12:44:06.211611 Dram Type= 6, Freq= 0, CH_0, rank 0
2889 12:44:06.218141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2890 12:44:06.218571 ==
2891 12:44:06.218949 DQS Delay:
2892 12:44:06.219270 DQS0 = 0, DQS1 = 0
2893 12:44:06.221792 DQM Delay:
2894 12:44:06.222267 DQM0 = 112, DQM1 = 100
2895 12:44:06.224548 DQ Delay:
2896 12:44:06.228058 DQ0 =112, DQ1 =112, DQ2 =112, DQ3 =108
2897 12:44:06.231569 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2898 12:44:06.235058 DQ8 =90, DQ9 =84, DQ10 =100, DQ11 =94
2899 12:44:06.238178 DQ12 =106, DQ13 =106, DQ14 =114, DQ15 =108
2900 12:44:06.238797
2901 12:44:06.239216
2902 12:44:06.244446 [DQSOSCAuto] RK0, (LSB)MR18= 0xf9f9, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
2903 12:44:06.247846 CH0 RK0: MR19=303, MR18=F9F9
2904 12:44:06.254288 CH0_RK0: MR19=0x303, MR18=0xF9F9, DQSOSC=412, MR23=63, INC=38, DEC=25
2905 12:44:06.254773
2906 12:44:06.257921 ----->DramcWriteLeveling(PI) begin...
2907 12:44:06.258366 ==
2908 12:44:06.261348 Dram Type= 6, Freq= 0, CH_0, rank 1
2909 12:44:06.267866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2910 12:44:06.268292 ==
2911 12:44:06.271515 Write leveling (Byte 0): 32 => 32
2912 12:44:06.272123 Write leveling (Byte 1): 32 => 32
2913 12:44:06.274507 DramcWriteLeveling(PI) end<-----
2914 12:44:06.274967
2915 12:44:06.275312 ==
2916 12:44:06.277472 Dram Type= 6, Freq= 0, CH_0, rank 1
2917 12:44:06.284231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2918 12:44:06.284744 ==
2919 12:44:06.287388 [Gating] SW mode calibration
2920 12:44:06.294484 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2921 12:44:06.297371 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2922 12:44:06.304510 0 15 0 | B1->B0 | 2626 3434 | 0 0 | (0 0) (0 0)
2923 12:44:06.307344 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2924 12:44:06.310760 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2925 12:44:06.317292 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2926 12:44:06.320773 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2927 12:44:06.323858 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2928 12:44:06.330362 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2929 12:44:06.333935 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 0) (1 0)
2930 12:44:06.337384 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2931 12:44:06.343779 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2932 12:44:06.347332 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2933 12:44:06.350272 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2934 12:44:06.356971 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2935 12:44:06.360431 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2936 12:44:06.363684 1 0 24 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
2937 12:44:06.370067 1 0 28 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
2938 12:44:06.373718 1 1 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
2939 12:44:06.376796 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 12:44:06.383154 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 12:44:06.386870 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 12:44:06.390293 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2943 12:44:06.397023 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2944 12:44:06.400269 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2945 12:44:06.403653 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2946 12:44:06.407005 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2947 12:44:06.413513 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 12:44:06.416962 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 12:44:06.419877 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 12:44:06.426504 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 12:44:06.430029 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 12:44:06.432971 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 12:44:06.440111 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 12:44:06.443059 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 12:44:06.446430 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 12:44:06.452887 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 12:44:06.456233 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 12:44:06.459584 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 12:44:06.466471 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 12:44:06.469865 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2961 12:44:06.473368 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2962 12:44:06.479932 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2963 12:44:06.482932 Total UI for P1: 0, mck2ui 16
2964 12:44:06.486438 best dqsien dly found for B0: ( 1, 3, 26)
2965 12:44:06.490067 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2966 12:44:06.493031 Total UI for P1: 0, mck2ui 16
2967 12:44:06.496464 best dqsien dly found for B1: ( 1, 3, 30)
2968 12:44:06.499997 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2969 12:44:06.502862 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2970 12:44:06.503300
2971 12:44:06.506252 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2972 12:44:06.509875 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2973 12:44:06.513027 [Gating] SW calibration Done
2974 12:44:06.513451 ==
2975 12:44:06.516509 Dram Type= 6, Freq= 0, CH_0, rank 1
2976 12:44:06.519562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2977 12:44:06.522883 ==
2978 12:44:06.523308 RX Vref Scan: 0
2979 12:44:06.523651
2980 12:44:06.526461 RX Vref 0 -> 0, step: 1
2981 12:44:06.526942
2982 12:44:06.529377 RX Delay -40 -> 252, step: 8
2983 12:44:06.532940 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2984 12:44:06.536536 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2985 12:44:06.539409 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2986 12:44:06.543172 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2987 12:44:06.549388 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2988 12:44:06.553142 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2989 12:44:06.556429 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2990 12:44:06.559324 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2991 12:44:06.562883 iDelay=200, Bit 8, Center 87 (16 ~ 159) 144
2992 12:44:06.566083 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2993 12:44:06.572811 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2994 12:44:06.576019 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2995 12:44:06.579808 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2996 12:44:06.582554 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2997 12:44:06.586356 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2998 12:44:06.593144 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2999 12:44:06.593568 ==
3000 12:44:06.595855 Dram Type= 6, Freq= 0, CH_0, rank 1
3001 12:44:06.599288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3002 12:44:06.599714 ==
3003 12:44:06.600072 DQS Delay:
3004 12:44:06.602866 DQS0 = 0, DQS1 = 0
3005 12:44:06.603293 DQM Delay:
3006 12:44:06.605722 DQM0 = 112, DQM1 = 100
3007 12:44:06.606141 DQ Delay:
3008 12:44:06.609274 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
3009 12:44:06.612777 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =123
3010 12:44:06.615707 DQ8 =87, DQ9 =83, DQ10 =103, DQ11 =95
3011 12:44:06.619393 DQ12 =107, DQ13 =107, DQ14 =111, DQ15 =107
3012 12:44:06.619855
3013 12:44:06.622387
3014 12:44:06.622962 ==
3015 12:44:06.625612 Dram Type= 6, Freq= 0, CH_0, rank 1
3016 12:44:06.628994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3017 12:44:06.629423 ==
3018 12:44:06.629760
3019 12:44:06.630071
3020 12:44:06.632472 TX Vref Scan disable
3021 12:44:06.632900 == TX Byte 0 ==
3022 12:44:06.638941 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3023 12:44:06.642329 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3024 12:44:06.642822 == TX Byte 1 ==
3025 12:44:06.648990 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3026 12:44:06.652496 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3027 12:44:06.652923 ==
3028 12:44:06.655797 Dram Type= 6, Freq= 0, CH_0, rank 1
3029 12:44:06.658726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3030 12:44:06.659203 ==
3031 12:44:06.671587 TX Vref=22, minBit 0, minWin=26, winSum=421
3032 12:44:06.674337 TX Vref=24, minBit 1, minWin=26, winSum=428
3033 12:44:06.677733 TX Vref=26, minBit 10, minWin=26, winSum=436
3034 12:44:06.681249 TX Vref=28, minBit 1, minWin=26, winSum=440
3035 12:44:06.684497 TX Vref=30, minBit 1, minWin=27, winSum=438
3036 12:44:06.690729 TX Vref=32, minBit 3, minWin=26, winSum=436
3037 12:44:06.694306 [TxChooseVref] Worse bit 1, Min win 27, Win sum 438, Final Vref 30
3038 12:44:06.694799
3039 12:44:06.697785 Final TX Range 1 Vref 30
3040 12:44:06.698297
3041 12:44:06.698852 ==
3042 12:44:06.700905 Dram Type= 6, Freq= 0, CH_0, rank 1
3043 12:44:06.704369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3044 12:44:06.707397 ==
3045 12:44:06.707930
3046 12:44:06.708357
3047 12:44:06.708691 TX Vref Scan disable
3048 12:44:06.710897 == TX Byte 0 ==
3049 12:44:06.714212 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3050 12:44:06.721092 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3051 12:44:06.721668 == TX Byte 1 ==
3052 12:44:06.724330 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3053 12:44:06.730595 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3054 12:44:06.731118
3055 12:44:06.731522 [DATLAT]
3056 12:44:06.731843 Freq=1200, CH0 RK1
3057 12:44:06.732187
3058 12:44:06.734366 DATLAT Default: 0xd
3059 12:44:06.734797 0, 0xFFFF, sum = 0
3060 12:44:06.737210 1, 0xFFFF, sum = 0
3061 12:44:06.740751 2, 0xFFFF, sum = 0
3062 12:44:06.741264 3, 0xFFFF, sum = 0
3063 12:44:06.744073 4, 0xFFFF, sum = 0
3064 12:44:06.744533 5, 0xFFFF, sum = 0
3065 12:44:06.747253 6, 0xFFFF, sum = 0
3066 12:44:06.747742 7, 0xFFFF, sum = 0
3067 12:44:06.750794 8, 0xFFFF, sum = 0
3068 12:44:06.751297 9, 0xFFFF, sum = 0
3069 12:44:06.753818 10, 0xFFFF, sum = 0
3070 12:44:06.754243 11, 0xFFFF, sum = 0
3071 12:44:06.757422 12, 0x0, sum = 1
3072 12:44:06.757884 13, 0x0, sum = 2
3073 12:44:06.760711 14, 0x0, sum = 3
3074 12:44:06.761208 15, 0x0, sum = 4
3075 12:44:06.763594 best_step = 13
3076 12:44:06.764052
3077 12:44:06.764390 ==
3078 12:44:06.767172 Dram Type= 6, Freq= 0, CH_0, rank 1
3079 12:44:06.770635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3080 12:44:06.771183 ==
3081 12:44:06.771588 RX Vref Scan: 0
3082 12:44:06.773559
3083 12:44:06.774020 RX Vref 0 -> 0, step: 1
3084 12:44:06.774399
3085 12:44:06.777068 RX Delay -37 -> 252, step: 4
3086 12:44:06.784111 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3087 12:44:06.787168 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3088 12:44:06.790579 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3089 12:44:06.793503 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3090 12:44:06.797374 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3091 12:44:06.803539 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3092 12:44:06.807074 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3093 12:44:06.810581 iDelay=195, Bit 7, Center 118 (47 ~ 190) 144
3094 12:44:06.813426 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3095 12:44:06.816675 iDelay=195, Bit 9, Center 82 (11 ~ 154) 144
3096 12:44:06.823337 iDelay=195, Bit 10, Center 102 (31 ~ 174) 144
3097 12:44:06.826926 iDelay=195, Bit 11, Center 90 (23 ~ 158) 136
3098 12:44:06.830167 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3099 12:44:06.833451 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3100 12:44:06.836905 iDelay=195, Bit 14, Center 112 (47 ~ 178) 132
3101 12:44:06.843784 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3102 12:44:06.844215 ==
3103 12:44:06.846578 Dram Type= 6, Freq= 0, CH_0, rank 1
3104 12:44:06.849945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3105 12:44:06.850370 ==
3106 12:44:06.850719 DQS Delay:
3107 12:44:06.853220 DQS0 = 0, DQS1 = 0
3108 12:44:06.853644 DQM Delay:
3109 12:44:06.856593 DQM0 = 110, DQM1 = 100
3110 12:44:06.857017 DQ Delay:
3111 12:44:06.860076 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3112 12:44:06.862808 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =118
3113 12:44:06.866218 DQ8 =90, DQ9 =82, DQ10 =102, DQ11 =90
3114 12:44:06.869805 DQ12 =108, DQ13 =108, DQ14 =112, DQ15 =108
3115 12:44:06.870250
3116 12:44:06.870588
3117 12:44:06.880048 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 403 ps
3118 12:44:06.882898 CH0 RK1: MR19=403, MR18=11F9
3119 12:44:06.889595 CH0_RK1: MR19=0x403, MR18=0x11F9, DQSOSC=403, MR23=63, INC=40, DEC=26
3120 12:44:06.890055 [RxdqsGatingPostProcess] freq 1200
3121 12:44:06.896113 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3122 12:44:06.899602 best DQS0 dly(2T, 0.5T) = (0, 12)
3123 12:44:06.902980 best DQS1 dly(2T, 0.5T) = (0, 12)
3124 12:44:06.906194 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3125 12:44:06.909646 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3126 12:44:06.912945 best DQS0 dly(2T, 0.5T) = (0, 11)
3127 12:44:06.916510 best DQS1 dly(2T, 0.5T) = (0, 11)
3128 12:44:06.919357 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3129 12:44:06.922806 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3130 12:44:06.926255 Pre-setting of DQS Precalculation
3131 12:44:06.929753 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3132 12:44:06.930184 ==
3133 12:44:06.932919 Dram Type= 6, Freq= 0, CH_1, rank 0
3134 12:44:06.936333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3135 12:44:06.936764 ==
3136 12:44:06.942887 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3137 12:44:06.949304 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3138 12:44:06.957303 [CA 0] Center 38 (8~68) winsize 61
3139 12:44:06.960825 [CA 1] Center 38 (8~69) winsize 62
3140 12:44:06.963737 [CA 2] Center 35 (5~65) winsize 61
3141 12:44:06.967299 [CA 3] Center 34 (4~65) winsize 62
3142 12:44:06.970753 [CA 4] Center 35 (5~65) winsize 61
3143 12:44:06.973719 [CA 5] Center 34 (4~64) winsize 61
3144 12:44:06.974162
3145 12:44:06.977135 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3146 12:44:06.977561
3147 12:44:06.980829 [CATrainingPosCal] consider 1 rank data
3148 12:44:06.983707 u2DelayCellTimex100 = 270/100 ps
3149 12:44:06.987318 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3150 12:44:06.993848 CA1 delay=38 (8~69),Diff = 4 PI (19 cell)
3151 12:44:06.996691 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3152 12:44:07.000306 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3153 12:44:07.003651 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3154 12:44:07.007403 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3155 12:44:07.007921
3156 12:44:07.010307 CA PerBit enable=1, Macro0, CA PI delay=34
3157 12:44:07.010938
3158 12:44:07.013818 [CBTSetCACLKResult] CA Dly = 34
3159 12:44:07.014333 CS Dly: 6 (0~37)
3160 12:44:07.016811 ==
3161 12:44:07.020337 Dram Type= 6, Freq= 0, CH_1, rank 1
3162 12:44:07.023450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3163 12:44:07.023873 ==
3164 12:44:07.026953 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3165 12:44:07.033497 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3166 12:44:07.042825 [CA 0] Center 38 (8~68) winsize 61
3167 12:44:07.046568 [CA 1] Center 38 (8~69) winsize 62
3168 12:44:07.049415 [CA 2] Center 35 (5~66) winsize 62
3169 12:44:07.052991 [CA 3] Center 34 (4~65) winsize 62
3170 12:44:07.056134 [CA 4] Center 35 (5~65) winsize 61
3171 12:44:07.059299 [CA 5] Center 33 (3~64) winsize 62
3172 12:44:07.059743
3173 12:44:07.062688 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3174 12:44:07.063142
3175 12:44:07.066365 [CATrainingPosCal] consider 2 rank data
3176 12:44:07.069325 u2DelayCellTimex100 = 270/100 ps
3177 12:44:07.072743 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3178 12:44:07.079509 CA1 delay=38 (8~69),Diff = 4 PI (19 cell)
3179 12:44:07.082943 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3180 12:44:07.085944 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3181 12:44:07.089526 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3182 12:44:07.092493 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3183 12:44:07.093099
3184 12:44:07.096039 CA PerBit enable=1, Macro0, CA PI delay=34
3185 12:44:07.096657
3186 12:44:07.099178 [CBTSetCACLKResult] CA Dly = 34
3187 12:44:07.099493 CS Dly: 8 (0~41)
3188 12:44:07.102381
3189 12:44:07.105826 ----->DramcWriteLeveling(PI) begin...
3190 12:44:07.106162 ==
3191 12:44:07.108765 Dram Type= 6, Freq= 0, CH_1, rank 0
3192 12:44:07.112183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3193 12:44:07.112339 ==
3194 12:44:07.115794 Write leveling (Byte 0): 26 => 26
3195 12:44:07.118740 Write leveling (Byte 1): 27 => 27
3196 12:44:07.122622 DramcWriteLeveling(PI) end<-----
3197 12:44:07.122741
3198 12:44:07.122843 ==
3199 12:44:07.125561 Dram Type= 6, Freq= 0, CH_1, rank 0
3200 12:44:07.128874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3201 12:44:07.128981 ==
3202 12:44:07.132364 [Gating] SW mode calibration
3203 12:44:07.139237 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3204 12:44:07.145139 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3205 12:44:07.148477 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3206 12:44:07.151892 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3207 12:44:07.158539 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3208 12:44:07.161985 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3209 12:44:07.165226 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3210 12:44:07.172093 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3211 12:44:07.175116 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3212 12:44:07.178990 0 15 28 | B1->B0 | 3434 3434 | 0 0 | (0 1) (1 0)
3213 12:44:07.185314 1 0 0 | B1->B0 | 2323 2323 | 1 0 | (1 0) (1 0)
3214 12:44:07.189049 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3215 12:44:07.192230 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3216 12:44:07.198753 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3217 12:44:07.202170 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3218 12:44:07.205030 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3219 12:44:07.208518 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3220 12:44:07.215376 1 0 28 | B1->B0 | 3030 2928 | 1 1 | (0 0) (0 0)
3221 12:44:07.218811 1 1 0 | B1->B0 | 4040 4141 | 0 0 | (1 1) (0 0)
3222 12:44:07.222005 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 12:44:07.228840 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 12:44:07.232117 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 12:44:07.235594 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 12:44:07.241602 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3227 12:44:07.245148 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3228 12:44:07.248835 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3229 12:44:07.255222 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 12:44:07.258463 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 12:44:07.262033 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 12:44:07.268718 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 12:44:07.271671 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 12:44:07.275507 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 12:44:07.281808 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 12:44:07.285282 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 12:44:07.288316 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 12:44:07.294893 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 12:44:07.298382 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 12:44:07.301498 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 12:44:07.308372 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 12:44:07.311406 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 12:44:07.314805 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 12:44:07.321482 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3245 12:44:07.324423 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3246 12:44:07.327867 Total UI for P1: 0, mck2ui 16
3247 12:44:07.330979 best dqsien dly found for B0: ( 1, 3, 28)
3248 12:44:07.334531 Total UI for P1: 0, mck2ui 16
3249 12:44:07.337948 best dqsien dly found for B1: ( 1, 3, 28)
3250 12:44:07.340893 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3251 12:44:07.344091 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3252 12:44:07.344200
3253 12:44:07.347332 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3254 12:44:07.350834 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3255 12:44:07.354424 [Gating] SW calibration Done
3256 12:44:07.354512 ==
3257 12:44:07.357398 Dram Type= 6, Freq= 0, CH_1, rank 0
3258 12:44:07.360983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3259 12:44:07.364336 ==
3260 12:44:07.364422 RX Vref Scan: 0
3261 12:44:07.364507
3262 12:44:07.368028 RX Vref 0 -> 0, step: 1
3263 12:44:07.368113
3264 12:44:07.368198 RX Delay -40 -> 252, step: 8
3265 12:44:07.374788 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3266 12:44:07.377838 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3267 12:44:07.381065 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3268 12:44:07.384202 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3269 12:44:07.387825 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3270 12:44:07.394536 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3271 12:44:07.397471 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3272 12:44:07.401155 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3273 12:44:07.404750 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3274 12:44:07.407799 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3275 12:44:07.414293 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3276 12:44:07.417417 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3277 12:44:07.420934 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3278 12:44:07.424336 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3279 12:44:07.430801 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3280 12:44:07.434097 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3281 12:44:07.434572 ==
3282 12:44:07.437187 Dram Type= 6, Freq= 0, CH_1, rank 0
3283 12:44:07.440818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3284 12:44:07.441285 ==
3285 12:44:07.444129 DQS Delay:
3286 12:44:07.444707 DQS0 = 0, DQS1 = 0
3287 12:44:07.445083 DQM Delay:
3288 12:44:07.447314 DQM0 = 117, DQM1 = 107
3289 12:44:07.447777 DQ Delay:
3290 12:44:07.450693 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3291 12:44:07.453925 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =119
3292 12:44:07.457290 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =103
3293 12:44:07.463845 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3294 12:44:07.464376
3295 12:44:07.464791
3296 12:44:07.465206 ==
3297 12:44:07.467069 Dram Type= 6, Freq= 0, CH_1, rank 0
3298 12:44:07.470717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3299 12:44:07.471247 ==
3300 12:44:07.471667
3301 12:44:07.472017
3302 12:44:07.473440 TX Vref Scan disable
3303 12:44:07.473907 == TX Byte 0 ==
3304 12:44:07.480375 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3305 12:44:07.483992 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3306 12:44:07.484464 == TX Byte 1 ==
3307 12:44:07.490508 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3308 12:44:07.493844 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3309 12:44:07.494433 ==
3310 12:44:07.496803 Dram Type= 6, Freq= 0, CH_1, rank 0
3311 12:44:07.500544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3312 12:44:07.501151 ==
3313 12:44:07.513060 TX Vref=22, minBit 0, minWin=25, winSum=408
3314 12:44:07.516083 TX Vref=24, minBit 1, minWin=25, winSum=411
3315 12:44:07.519790 TX Vref=26, minBit 1, minWin=25, winSum=416
3316 12:44:07.523273 TX Vref=28, minBit 1, minWin=25, winSum=417
3317 12:44:07.525950 TX Vref=30, minBit 3, minWin=24, winSum=419
3318 12:44:07.532550 TX Vref=32, minBit 1, minWin=25, winSum=417
3319 12:44:07.535950 [TxChooseVref] Worse bit 1, Min win 25, Win sum 417, Final Vref 28
3320 12:44:07.536537
3321 12:44:07.539110 Final TX Range 1 Vref 28
3322 12:44:07.539669
3323 12:44:07.540046 ==
3324 12:44:07.542789 Dram Type= 6, Freq= 0, CH_1, rank 0
3325 12:44:07.545693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3326 12:44:07.549161 ==
3327 12:44:07.549475
3328 12:44:07.549780
3329 12:44:07.550076 TX Vref Scan disable
3330 12:44:07.552567 == TX Byte 0 ==
3331 12:44:07.555496 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3332 12:44:07.562164 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3333 12:44:07.562308 == TX Byte 1 ==
3334 12:44:07.565624 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3335 12:44:07.572215 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3336 12:44:07.572340
3337 12:44:07.572429 [DATLAT]
3338 12:44:07.572509 Freq=1200, CH1 RK0
3339 12:44:07.572586
3340 12:44:07.575775 DATLAT Default: 0xd
3341 12:44:07.575885 0, 0xFFFF, sum = 0
3342 12:44:07.578717 1, 0xFFFF, sum = 0
3343 12:44:07.582266 2, 0xFFFF, sum = 0
3344 12:44:07.582361 3, 0xFFFF, sum = 0
3345 12:44:07.585501 4, 0xFFFF, sum = 0
3346 12:44:07.585590 5, 0xFFFF, sum = 0
3347 12:44:07.588808 6, 0xFFFF, sum = 0
3348 12:44:07.588894 7, 0xFFFF, sum = 0
3349 12:44:07.592201 8, 0xFFFF, sum = 0
3350 12:44:07.592314 9, 0xFFFF, sum = 0
3351 12:44:07.595411 10, 0xFFFF, sum = 0
3352 12:44:07.595495 11, 0xFFFF, sum = 0
3353 12:44:07.598720 12, 0x0, sum = 1
3354 12:44:07.598804 13, 0x0, sum = 2
3355 12:44:07.601924 14, 0x0, sum = 3
3356 12:44:07.602012 15, 0x0, sum = 4
3357 12:44:07.602081 best_step = 13
3358 12:44:07.605341
3359 12:44:07.605423 ==
3360 12:44:07.608912 Dram Type= 6, Freq= 0, CH_1, rank 0
3361 12:44:07.611915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3362 12:44:07.612022 ==
3363 12:44:07.612119 RX Vref Scan: 1
3364 12:44:07.612184
3365 12:44:07.615582 Set Vref Range= 32 -> 127
3366 12:44:07.615663
3367 12:44:07.619088 RX Vref 32 -> 127, step: 1
3368 12:44:07.619167
3369 12:44:07.622102 RX Delay -13 -> 252, step: 4
3370 12:44:07.622181
3371 12:44:07.626080 Set Vref, RX VrefLevel [Byte0]: 32
3372 12:44:07.628695 [Byte1]: 32
3373 12:44:07.628777
3374 12:44:07.632342 Set Vref, RX VrefLevel [Byte0]: 33
3375 12:44:07.635330 [Byte1]: 33
3376 12:44:07.639151
3377 12:44:07.639258 Set Vref, RX VrefLevel [Byte0]: 34
3378 12:44:07.642222 [Byte1]: 34
3379 12:44:07.646769
3380 12:44:07.646860 Set Vref, RX VrefLevel [Byte0]: 35
3381 12:44:07.649727 [Byte1]: 35
3382 12:44:07.654317
3383 12:44:07.654410 Set Vref, RX VrefLevel [Byte0]: 36
3384 12:44:07.657709 [Byte1]: 36
3385 12:44:07.662379
3386 12:44:07.662487 Set Vref, RX VrefLevel [Byte0]: 37
3387 12:44:07.665998 [Byte1]: 37
3388 12:44:07.670546
3389 12:44:07.670741 Set Vref, RX VrefLevel [Byte0]: 38
3390 12:44:07.673709 [Byte1]: 38
3391 12:44:07.677987
3392 12:44:07.678136 Set Vref, RX VrefLevel [Byte0]: 39
3393 12:44:07.681515 [Byte1]: 39
3394 12:44:07.686138
3395 12:44:07.686290 Set Vref, RX VrefLevel [Byte0]: 40
3396 12:44:07.689565 [Byte1]: 40
3397 12:44:07.693849
3398 12:44:07.693999 Set Vref, RX VrefLevel [Byte0]: 41
3399 12:44:07.697675 [Byte1]: 41
3400 12:44:07.702184
3401 12:44:07.702639 Set Vref, RX VrefLevel [Byte0]: 42
3402 12:44:07.705199 [Byte1]: 42
3403 12:44:07.709688
3404 12:44:07.710142 Set Vref, RX VrefLevel [Byte0]: 43
3405 12:44:07.713067 [Byte1]: 43
3406 12:44:07.717665
3407 12:44:07.718130 Set Vref, RX VrefLevel [Byte0]: 44
3408 12:44:07.721272 [Byte1]: 44
3409 12:44:07.726081
3410 12:44:07.726531 Set Vref, RX VrefLevel [Byte0]: 45
3411 12:44:07.729054 [Byte1]: 45
3412 12:44:07.733634
3413 12:44:07.734088 Set Vref, RX VrefLevel [Byte0]: 46
3414 12:44:07.737122 [Byte1]: 46
3415 12:44:07.741316
3416 12:44:07.741770 Set Vref, RX VrefLevel [Byte0]: 47
3417 12:44:07.744947 [Byte1]: 47
3418 12:44:07.749587
3419 12:44:07.752626 Set Vref, RX VrefLevel [Byte0]: 48
3420 12:44:07.756146 [Byte1]: 48
3421 12:44:07.756634
3422 12:44:07.759234 Set Vref, RX VrefLevel [Byte0]: 49
3423 12:44:07.762676 [Byte1]: 49
3424 12:44:07.763241
3425 12:44:07.765987 Set Vref, RX VrefLevel [Byte0]: 50
3426 12:44:07.768792 [Byte1]: 50
3427 12:44:07.772817
3428 12:44:07.773174 Set Vref, RX VrefLevel [Byte0]: 51
3429 12:44:07.776229 [Byte1]: 51
3430 12:44:07.780486
3431 12:44:07.780793 Set Vref, RX VrefLevel [Byte0]: 52
3432 12:44:07.784024 [Byte1]: 52
3433 12:44:07.788289
3434 12:44:07.788448 Set Vref, RX VrefLevel [Byte0]: 53
3435 12:44:07.791890 [Byte1]: 53
3436 12:44:07.796640
3437 12:44:07.796794 Set Vref, RX VrefLevel [Byte0]: 54
3438 12:44:07.799564 [Byte1]: 54
3439 12:44:07.804105
3440 12:44:07.804275 Set Vref, RX VrefLevel [Byte0]: 55
3441 12:44:07.807437 [Byte1]: 55
3442 12:44:07.812006
3443 12:44:07.812182 Set Vref, RX VrefLevel [Byte0]: 56
3444 12:44:07.815192 [Byte1]: 56
3445 12:44:07.820049
3446 12:44:07.820151 Set Vref, RX VrefLevel [Byte0]: 57
3447 12:44:07.823294 [Byte1]: 57
3448 12:44:07.827579
3449 12:44:07.827658 Set Vref, RX VrefLevel [Byte0]: 58
3450 12:44:07.831386 [Byte1]: 58
3451 12:44:07.835529
3452 12:44:07.835639 Set Vref, RX VrefLevel [Byte0]: 59
3453 12:44:07.838973 [Byte1]: 59
3454 12:44:07.843820
3455 12:44:07.843914 Set Vref, RX VrefLevel [Byte0]: 60
3456 12:44:07.846683 [Byte1]: 60
3457 12:44:07.851474
3458 12:44:07.851589 Set Vref, RX VrefLevel [Byte0]: 61
3459 12:44:07.854823 [Byte1]: 61
3460 12:44:07.859783
3461 12:44:07.859918 Set Vref, RX VrefLevel [Byte0]: 62
3462 12:44:07.862691 [Byte1]: 62
3463 12:44:07.867239
3464 12:44:07.867506 Set Vref, RX VrefLevel [Byte0]: 63
3465 12:44:07.870523 [Byte1]: 63
3466 12:44:07.875142
3467 12:44:07.875473 Set Vref, RX VrefLevel [Byte0]: 64
3468 12:44:07.878500 [Byte1]: 64
3469 12:44:07.883325
3470 12:44:07.883727 Set Vref, RX VrefLevel [Byte0]: 65
3471 12:44:07.886582 [Byte1]: 65
3472 12:44:07.891255
3473 12:44:07.891740 Final RX Vref Byte 0 = 57 to rank0
3474 12:44:07.894815 Final RX Vref Byte 1 = 55 to rank0
3475 12:44:07.897835 Final RX Vref Byte 0 = 57 to rank1
3476 12:44:07.901306 Final RX Vref Byte 1 = 55 to rank1==
3477 12:44:07.904602 Dram Type= 6, Freq= 0, CH_1, rank 0
3478 12:44:07.910930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3479 12:44:07.911334 ==
3480 12:44:07.911692 DQS Delay:
3481 12:44:07.911988 DQS0 = 0, DQS1 = 0
3482 12:44:07.914345 DQM Delay:
3483 12:44:07.914747 DQM0 = 117, DQM1 = 109
3484 12:44:07.917534 DQ Delay:
3485 12:44:07.921235 DQ0 =120, DQ1 =112, DQ2 =110, DQ3 =114
3486 12:44:07.924100 DQ4 =116, DQ5 =124, DQ6 =128, DQ7 =114
3487 12:44:07.927383 DQ8 =96, DQ9 =100, DQ10 =108, DQ11 =104
3488 12:44:07.931423 DQ12 =118, DQ13 =116, DQ14 =118, DQ15 =118
3489 12:44:07.931964
3490 12:44:07.932476
3491 12:44:07.940663 [DQSOSCAuto] RK0, (LSB)MR18= 0xebf1, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 418 ps
3492 12:44:07.941074 CH1 RK0: MR19=303, MR18=EBF1
3493 12:44:07.947369 CH1_RK0: MR19=0x303, MR18=0xEBF1, DQSOSC=416, MR23=63, INC=37, DEC=25
3494 12:44:07.947819
3495 12:44:07.950931 ----->DramcWriteLeveling(PI) begin...
3496 12:44:07.951351 ==
3497 12:44:07.954609 Dram Type= 6, Freq= 0, CH_1, rank 1
3498 12:44:07.961009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3499 12:44:07.961457 ==
3500 12:44:07.964076 Write leveling (Byte 0): 25 => 25
3501 12:44:07.964533 Write leveling (Byte 1): 28 => 28
3502 12:44:07.967404 DramcWriteLeveling(PI) end<-----
3503 12:44:07.967795
3504 12:44:07.970914 ==
3505 12:44:07.971325 Dram Type= 6, Freq= 0, CH_1, rank 1
3506 12:44:07.977504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3507 12:44:07.977912 ==
3508 12:44:07.980790 [Gating] SW mode calibration
3509 12:44:07.987197 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3510 12:44:07.990730 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3511 12:44:07.997198 0 15 0 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
3512 12:44:08.000915 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3513 12:44:08.003771 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3514 12:44:08.010366 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3515 12:44:08.013437 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3516 12:44:08.016989 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3517 12:44:08.023636 0 15 24 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
3518 12:44:08.026926 0 15 28 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
3519 12:44:08.030372 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3520 12:44:08.036817 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3521 12:44:08.040210 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3522 12:44:08.043242 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3523 12:44:08.050075 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3524 12:44:08.053542 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3525 12:44:08.056545 1 0 24 | B1->B0 | 2323 3939 | 0 1 | (0 0) (0 0)
3526 12:44:08.063432 1 0 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3527 12:44:08.066519 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 12:44:08.070019 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3529 12:44:08.076619 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3530 12:44:08.080089 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3531 12:44:08.083309 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3532 12:44:08.089854 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3533 12:44:08.093420 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3534 12:44:08.096233 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3535 12:44:08.103074 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 12:44:08.106064 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 12:44:08.109617 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 12:44:08.115881 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 12:44:08.119441 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 12:44:08.123009 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 12:44:08.129351 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 12:44:08.132577 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 12:44:08.135842 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 12:44:08.142659 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 12:44:08.146110 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 12:44:08.149191 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 12:44:08.155664 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 12:44:08.158928 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3549 12:44:08.162480 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3550 12:44:08.168582 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3551 12:44:08.169212 Total UI for P1: 0, mck2ui 16
3552 12:44:08.175198 best dqsien dly found for B0: ( 1, 3, 22)
3553 12:44:08.175825 Total UI for P1: 0, mck2ui 16
3554 12:44:08.181785 best dqsien dly found for B1: ( 1, 3, 24)
3555 12:44:08.185129 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3556 12:44:08.188616 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3557 12:44:08.189254
3558 12:44:08.191959 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3559 12:44:08.195293 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3560 12:44:08.198182 [Gating] SW calibration Done
3561 12:44:08.198643 ==
3562 12:44:08.201591 Dram Type= 6, Freq= 0, CH_1, rank 1
3563 12:44:08.205199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3564 12:44:08.205842 ==
3565 12:44:08.208484 RX Vref Scan: 0
3566 12:44:08.209124
3567 12:44:08.209655 RX Vref 0 -> 0, step: 1
3568 12:44:08.210140
3569 12:44:08.211364 RX Delay -40 -> 252, step: 8
3570 12:44:08.218005 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3571 12:44:08.221479 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3572 12:44:08.224514 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3573 12:44:08.228252 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3574 12:44:08.231125 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3575 12:44:08.237987 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3576 12:44:08.241010 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3577 12:44:08.244714 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3578 12:44:08.247791 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3579 12:44:08.251000 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3580 12:44:08.257518 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3581 12:44:08.261098 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3582 12:44:08.264097 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3583 12:44:08.267555 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3584 12:44:08.271082 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3585 12:44:08.277553 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3586 12:44:08.278204 ==
3587 12:44:08.281035 Dram Type= 6, Freq= 0, CH_1, rank 1
3588 12:44:08.283747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3589 12:44:08.284225 ==
3590 12:44:08.284604 DQS Delay:
3591 12:44:08.287411 DQS0 = 0, DQS1 = 0
3592 12:44:08.287883 DQM Delay:
3593 12:44:08.290531 DQM0 = 113, DQM1 = 112
3594 12:44:08.291217 DQ Delay:
3595 12:44:08.293750 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =111
3596 12:44:08.297342 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3597 12:44:08.300500 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3598 12:44:08.306822 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3599 12:44:08.307373
3600 12:44:08.307776
3601 12:44:08.308150 ==
3602 12:44:08.310315 Dram Type= 6, Freq= 0, CH_1, rank 1
3603 12:44:08.313762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3604 12:44:08.314271 ==
3605 12:44:08.314625
3606 12:44:08.314972
3607 12:44:08.317169 TX Vref Scan disable
3608 12:44:08.317669 == TX Byte 0 ==
3609 12:44:08.323809 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3610 12:44:08.326455 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3611 12:44:08.326907 == TX Byte 1 ==
3612 12:44:08.333456 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3613 12:44:08.336509 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3614 12:44:08.336959 ==
3615 12:44:08.340053 Dram Type= 6, Freq= 0, CH_1, rank 1
3616 12:44:08.343002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3617 12:44:08.343443 ==
3618 12:44:08.356392 TX Vref=22, minBit 0, minWin=25, winSum=409
3619 12:44:08.359719 TX Vref=24, minBit 3, minWin=25, winSum=417
3620 12:44:08.362763 TX Vref=26, minBit 0, minWin=26, winSum=424
3621 12:44:08.365810 TX Vref=28, minBit 11, minWin=25, winSum=425
3622 12:44:08.369336 TX Vref=30, minBit 0, minWin=26, winSum=421
3623 12:44:08.375597 TX Vref=32, minBit 0, minWin=26, winSum=421
3624 12:44:08.379265 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 26
3625 12:44:08.379771
3626 12:44:08.382746 Final TX Range 1 Vref 26
3627 12:44:08.383302
3628 12:44:08.383735 ==
3629 12:44:08.385818 Dram Type= 6, Freq= 0, CH_1, rank 1
3630 12:44:08.389022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3631 12:44:08.392631 ==
3632 12:44:08.393199
3633 12:44:08.393669
3634 12:44:08.394146 TX Vref Scan disable
3635 12:44:08.396067 == TX Byte 0 ==
3636 12:44:08.399015 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3637 12:44:08.405769 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3638 12:44:08.406268 == TX Byte 1 ==
3639 12:44:08.408997 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3640 12:44:08.415451 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3641 12:44:08.415899
3642 12:44:08.416334 [DATLAT]
3643 12:44:08.416741 Freq=1200, CH1 RK1
3644 12:44:08.417142
3645 12:44:08.418898 DATLAT Default: 0xd
3646 12:44:08.422175 0, 0xFFFF, sum = 0
3647 12:44:08.422629 1, 0xFFFF, sum = 0
3648 12:44:08.425289 2, 0xFFFF, sum = 0
3649 12:44:08.425727 3, 0xFFFF, sum = 0
3650 12:44:08.428774 4, 0xFFFF, sum = 0
3651 12:44:08.429214 5, 0xFFFF, sum = 0
3652 12:44:08.432091 6, 0xFFFF, sum = 0
3653 12:44:08.432633 7, 0xFFFF, sum = 0
3654 12:44:08.435690 8, 0xFFFF, sum = 0
3655 12:44:08.436142 9, 0xFFFF, sum = 0
3656 12:44:08.438670 10, 0xFFFF, sum = 0
3657 12:44:08.439191 11, 0xFFFF, sum = 0
3658 12:44:08.441615 12, 0x0, sum = 1
3659 12:44:08.442101 13, 0x0, sum = 2
3660 12:44:08.445203 14, 0x0, sum = 3
3661 12:44:08.445642 15, 0x0, sum = 4
3662 12:44:08.448713 best_step = 13
3663 12:44:08.449144
3664 12:44:08.449577 ==
3665 12:44:08.451619 Dram Type= 6, Freq= 0, CH_1, rank 1
3666 12:44:08.455151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3667 12:44:08.455602 ==
3668 12:44:08.458116 RX Vref Scan: 0
3669 12:44:08.458546
3670 12:44:08.458928 RX Vref 0 -> 0, step: 1
3671 12:44:08.459261
3672 12:44:08.461574 RX Delay -13 -> 252, step: 4
3673 12:44:08.468173 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3674 12:44:08.471626 iDelay=195, Bit 1, Center 112 (47 ~ 178) 132
3675 12:44:08.474756 iDelay=195, Bit 2, Center 104 (39 ~ 170) 132
3676 12:44:08.477818 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3677 12:44:08.481234 iDelay=195, Bit 4, Center 112 (47 ~ 178) 132
3678 12:44:08.488159 iDelay=195, Bit 5, Center 122 (51 ~ 194) 144
3679 12:44:08.491322 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3680 12:44:08.494790 iDelay=195, Bit 7, Center 112 (47 ~ 178) 132
3681 12:44:08.497773 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3682 12:44:08.501341 iDelay=195, Bit 9, Center 104 (43 ~ 166) 124
3683 12:44:08.507862 iDelay=195, Bit 10, Center 116 (51 ~ 182) 132
3684 12:44:08.511324 iDelay=195, Bit 11, Center 108 (47 ~ 170) 124
3685 12:44:08.514106 iDelay=195, Bit 12, Center 124 (63 ~ 186) 124
3686 12:44:08.517396 iDelay=195, Bit 13, Center 120 (59 ~ 182) 124
3687 12:44:08.524007 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3688 12:44:08.527575 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3689 12:44:08.528114 ==
3690 12:44:08.530883 Dram Type= 6, Freq= 0, CH_1, rank 1
3691 12:44:08.534253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3692 12:44:08.534729 ==
3693 12:44:08.537570 DQS Delay:
3694 12:44:08.538042 DQS0 = 0, DQS1 = 0
3695 12:44:08.538415 DQM Delay:
3696 12:44:08.540596 DQM0 = 114, DQM1 = 115
3697 12:44:08.541065 DQ Delay:
3698 12:44:08.544116 DQ0 =116, DQ1 =112, DQ2 =104, DQ3 =112
3699 12:44:08.547150 DQ4 =112, DQ5 =122, DQ6 =124, DQ7 =112
3700 12:44:08.553726 DQ8 =100, DQ9 =104, DQ10 =116, DQ11 =108
3701 12:44:08.557004 DQ12 =124, DQ13 =120, DQ14 =124, DQ15 =124
3702 12:44:08.557374
3703 12:44:08.557637
3704 12:44:08.563576 [DQSOSCAuto] RK1, (LSB)MR18= 0xf908, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 412 ps
3705 12:44:08.567110 CH1 RK1: MR19=304, MR18=F908
3706 12:44:08.573248 CH1_RK1: MR19=0x304, MR18=0xF908, DQSOSC=406, MR23=63, INC=39, DEC=26
3707 12:44:08.577195 [RxdqsGatingPostProcess] freq 1200
3708 12:44:08.583246 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3709 12:44:08.583563 best DQS0 dly(2T, 0.5T) = (0, 11)
3710 12:44:08.586695 best DQS1 dly(2T, 0.5T) = (0, 11)
3711 12:44:08.589856 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3712 12:44:08.593678 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3713 12:44:08.596706 best DQS0 dly(2T, 0.5T) = (0, 11)
3714 12:44:08.599715 best DQS1 dly(2T, 0.5T) = (0, 11)
3715 12:44:08.603204 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3716 12:44:08.606229 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3717 12:44:08.609979 Pre-setting of DQS Precalculation
3718 12:44:08.616502 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3719 12:44:08.623077 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3720 12:44:08.630023 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3721 12:44:08.630378
3722 12:44:08.630714
3723 12:44:08.632839 [Calibration Summary] 2400 Mbps
3724 12:44:08.633121 CH 0, Rank 0
3725 12:44:08.636187 SW Impedance : PASS
3726 12:44:08.639545 DUTY Scan : NO K
3727 12:44:08.639845 ZQ Calibration : PASS
3728 12:44:08.642692 Jitter Meter : NO K
3729 12:44:08.646293 CBT Training : PASS
3730 12:44:08.646635 Write leveling : PASS
3731 12:44:08.649337 RX DQS gating : PASS
3732 12:44:08.652799 RX DQ/DQS(RDDQC) : PASS
3733 12:44:08.653174 TX DQ/DQS : PASS
3734 12:44:08.655940 RX DATLAT : PASS
3735 12:44:08.659357 RX DQ/DQS(Engine): PASS
3736 12:44:08.659863 TX OE : NO K
3737 12:44:08.660242 All Pass.
3738 12:44:08.660710
3739 12:44:08.662705 CH 0, Rank 1
3740 12:44:08.666350 SW Impedance : PASS
3741 12:44:08.666886 DUTY Scan : NO K
3742 12:44:08.669236 ZQ Calibration : PASS
3743 12:44:08.669809 Jitter Meter : NO K
3744 12:44:08.672995 CBT Training : PASS
3745 12:44:08.676098 Write leveling : PASS
3746 12:44:08.676564 RX DQS gating : PASS
3747 12:44:08.679223 RX DQ/DQS(RDDQC) : PASS
3748 12:44:08.682670 TX DQ/DQS : PASS
3749 12:44:08.683159 RX DATLAT : PASS
3750 12:44:08.685565 RX DQ/DQS(Engine): PASS
3751 12:44:08.689208 TX OE : NO K
3752 12:44:08.689717 All Pass.
3753 12:44:08.690204
3754 12:44:08.690630 CH 1, Rank 0
3755 12:44:08.692390 SW Impedance : PASS
3756 12:44:08.695825 DUTY Scan : NO K
3757 12:44:08.696217 ZQ Calibration : PASS
3758 12:44:08.699417 Jitter Meter : NO K
3759 12:44:08.702678 CBT Training : PASS
3760 12:44:08.703247 Write leveling : PASS
3761 12:44:08.705980 RX DQS gating : PASS
3762 12:44:08.709037 RX DQ/DQS(RDDQC) : PASS
3763 12:44:08.709504 TX DQ/DQS : PASS
3764 12:44:08.712452 RX DATLAT : PASS
3765 12:44:08.715309 RX DQ/DQS(Engine): PASS
3766 12:44:08.715814 TX OE : NO K
3767 12:44:08.716252 All Pass.
3768 12:44:08.719298
3769 12:44:08.719801 CH 1, Rank 1
3770 12:44:08.722427 SW Impedance : PASS
3771 12:44:08.722991 DUTY Scan : NO K
3772 12:44:08.725808 ZQ Calibration : PASS
3773 12:44:08.728694 Jitter Meter : NO K
3774 12:44:08.729231 CBT Training : PASS
3775 12:44:08.732155 Write leveling : PASS
3776 12:44:08.732545 RX DQS gating : PASS
3777 12:44:08.735499 RX DQ/DQS(RDDQC) : PASS
3778 12:44:08.738745 TX DQ/DQS : PASS
3779 12:44:08.739294 RX DATLAT : PASS
3780 12:44:08.742251 RX DQ/DQS(Engine): PASS
3781 12:44:08.745884 TX OE : NO K
3782 12:44:08.746381 All Pass.
3783 12:44:08.746820
3784 12:44:08.748462 DramC Write-DBI off
3785 12:44:08.748966 PER_BANK_REFRESH: Hybrid Mode
3786 12:44:08.751940 TX_TRACKING: ON
3787 12:44:08.761585 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3788 12:44:08.764998 [FAST_K] Save calibration result to emmc
3789 12:44:08.768355 dramc_set_vcore_voltage set vcore to 650000
3790 12:44:08.771986 Read voltage for 600, 5
3791 12:44:08.772373 Vio18 = 0
3792 12:44:08.772693 Vcore = 650000
3793 12:44:08.774989 Vdram = 0
3794 12:44:08.775449 Vddq = 0
3795 12:44:08.775773 Vmddr = 0
3796 12:44:08.781638 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3797 12:44:08.785123 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3798 12:44:08.788441 MEM_TYPE=3, freq_sel=19
3799 12:44:08.791605 sv_algorithm_assistance_LP4_1600
3800 12:44:08.794774 ============ PULL DRAM RESETB DOWN ============
3801 12:44:08.797816 ========== PULL DRAM RESETB DOWN end =========
3802 12:44:08.804630 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3803 12:44:08.808004 ===================================
3804 12:44:08.808559 LPDDR4 DRAM CONFIGURATION
3805 12:44:08.811303 ===================================
3806 12:44:08.814660 EX_ROW_EN[0] = 0x0
3807 12:44:08.817534 EX_ROW_EN[1] = 0x0
3808 12:44:08.817927 LP4Y_EN = 0x0
3809 12:44:08.821248 WORK_FSP = 0x0
3810 12:44:08.821690 WL = 0x2
3811 12:44:08.824145 RL = 0x2
3812 12:44:08.824540 BL = 0x2
3813 12:44:08.827689 RPST = 0x0
3814 12:44:08.828084 RD_PRE = 0x0
3815 12:44:08.831115 WR_PRE = 0x1
3816 12:44:08.831507 WR_PST = 0x0
3817 12:44:08.834542 DBI_WR = 0x0
3818 12:44:08.834972 DBI_RD = 0x0
3819 12:44:08.837496 OTF = 0x1
3820 12:44:08.841069 ===================================
3821 12:44:08.844442 ===================================
3822 12:44:08.844838 ANA top config
3823 12:44:08.847263 ===================================
3824 12:44:08.850695 DLL_ASYNC_EN = 0
3825 12:44:08.854198 ALL_SLAVE_EN = 1
3826 12:44:08.857586 NEW_RANK_MODE = 1
3827 12:44:08.858041 DLL_IDLE_MODE = 1
3828 12:44:08.860846 LP45_APHY_COMB_EN = 1
3829 12:44:08.864421 TX_ODT_DIS = 1
3830 12:44:08.867331 NEW_8X_MODE = 1
3831 12:44:08.870511 ===================================
3832 12:44:08.874441 ===================================
3833 12:44:08.877124 data_rate = 1200
3834 12:44:08.880262 CKR = 1
3835 12:44:08.880661 DQ_P2S_RATIO = 8
3836 12:44:08.883572 ===================================
3837 12:44:08.887185 CA_P2S_RATIO = 8
3838 12:44:08.889948 DQ_CA_OPEN = 0
3839 12:44:08.893343 DQ_SEMI_OPEN = 0
3840 12:44:08.896829 CA_SEMI_OPEN = 0
3841 12:44:08.900409 CA_FULL_RATE = 0
3842 12:44:08.900817 DQ_CKDIV4_EN = 1
3843 12:44:08.903281 CA_CKDIV4_EN = 1
3844 12:44:08.906540 CA_PREDIV_EN = 0
3845 12:44:08.910545 PH8_DLY = 0
3846 12:44:08.913413 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3847 12:44:08.916725 DQ_AAMCK_DIV = 4
3848 12:44:08.917118 CA_AAMCK_DIV = 4
3849 12:44:08.919772 CA_ADMCK_DIV = 4
3850 12:44:08.923185 DQ_TRACK_CA_EN = 0
3851 12:44:08.926290 CA_PICK = 600
3852 12:44:08.929910 CA_MCKIO = 600
3853 12:44:08.933205 MCKIO_SEMI = 0
3854 12:44:08.936278 PLL_FREQ = 2288
3855 12:44:08.936674 DQ_UI_PI_RATIO = 32
3856 12:44:08.939804 CA_UI_PI_RATIO = 0
3857 12:44:08.943426 ===================================
3858 12:44:08.946303 ===================================
3859 12:44:08.949760 memory_type:LPDDR4
3860 12:44:08.953051 GP_NUM : 10
3861 12:44:08.953575 SRAM_EN : 1
3862 12:44:08.956031 MD32_EN : 0
3863 12:44:08.959475 ===================================
3864 12:44:08.963115 [ANA_INIT] >>>>>>>>>>>>>>
3865 12:44:08.963588 <<<<<< [CONFIGURE PHASE]: ANA_TX
3866 12:44:08.969613 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3867 12:44:08.972728 ===================================
3868 12:44:08.973204 data_rate = 1200,PCW = 0X5800
3869 12:44:08.976078 ===================================
3870 12:44:08.979975 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3871 12:44:08.985793 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3872 12:44:08.992906 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3873 12:44:08.995711 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3874 12:44:08.999467 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3875 12:44:09.002913 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3876 12:44:09.005758 [ANA_INIT] flow start
3877 12:44:09.009177 [ANA_INIT] PLL >>>>>>>>
3878 12:44:09.009632 [ANA_INIT] PLL <<<<<<<<
3879 12:44:09.012549 [ANA_INIT] MIDPI >>>>>>>>
3880 12:44:09.016011 [ANA_INIT] MIDPI <<<<<<<<
3881 12:44:09.016613 [ANA_INIT] DLL >>>>>>>>
3882 12:44:09.018632 [ANA_INIT] flow end
3883 12:44:09.022391 ============ LP4 DIFF to SE enter ============
3884 12:44:09.025547 ============ LP4 DIFF to SE exit ============
3885 12:44:09.028652 [ANA_INIT] <<<<<<<<<<<<<
3886 12:44:09.032186 [Flow] Enable top DCM control >>>>>
3887 12:44:09.035361 [Flow] Enable top DCM control <<<<<
3888 12:44:09.038305 Enable DLL master slave shuffle
3889 12:44:09.045082 ==============================================================
3890 12:44:09.045648 Gating Mode config
3891 12:44:09.052082 ==============================================================
3892 12:44:09.055255 Config description:
3893 12:44:09.061390 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3894 12:44:09.068405 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3895 12:44:09.074593 SELPH_MODE 0: By rank 1: By Phase
3896 12:44:09.081460 ==============================================================
3897 12:44:09.084379 GAT_TRACK_EN = 1
3898 12:44:09.084945 RX_GATING_MODE = 2
3899 12:44:09.087903 RX_GATING_TRACK_MODE = 2
3900 12:44:09.090790 SELPH_MODE = 1
3901 12:44:09.094487 PICG_EARLY_EN = 1
3902 12:44:09.098123 VALID_LAT_VALUE = 1
3903 12:44:09.104264 ==============================================================
3904 12:44:09.107700 Enter into Gating configuration >>>>
3905 12:44:09.111020 Exit from Gating configuration <<<<
3906 12:44:09.114285 Enter into DVFS_PRE_config >>>>>
3907 12:44:09.124157 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3908 12:44:09.126945 Exit from DVFS_PRE_config <<<<<
3909 12:44:09.130190 Enter into PICG configuration >>>>
3910 12:44:09.134000 Exit from PICG configuration <<<<
3911 12:44:09.136847 [RX_INPUT] configuration >>>>>
3912 12:44:09.140481 [RX_INPUT] configuration <<<<<
3913 12:44:09.143555 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3914 12:44:09.150090 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3915 12:44:09.156504 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3916 12:44:09.163507 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3917 12:44:09.170258 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3918 12:44:09.173127 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3919 12:44:09.179387 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3920 12:44:09.182781 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3921 12:44:09.186459 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3922 12:44:09.189727 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3923 12:44:09.196450 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3924 12:44:09.199539 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3925 12:44:09.203020 ===================================
3926 12:44:09.206019 LPDDR4 DRAM CONFIGURATION
3927 12:44:09.209523 ===================================
3928 12:44:09.209961 EX_ROW_EN[0] = 0x0
3929 12:44:09.212990 EX_ROW_EN[1] = 0x0
3930 12:44:09.213415 LP4Y_EN = 0x0
3931 12:44:09.215938 WORK_FSP = 0x0
3932 12:44:09.219238 WL = 0x2
3933 12:44:09.219667 RL = 0x2
3934 12:44:09.222615 BL = 0x2
3935 12:44:09.223101 RPST = 0x0
3936 12:44:09.225972 RD_PRE = 0x0
3937 12:44:09.226405 WR_PRE = 0x1
3938 12:44:09.229067 WR_PST = 0x0
3939 12:44:09.229494 DBI_WR = 0x0
3940 12:44:09.232628 DBI_RD = 0x0
3941 12:44:09.233059 OTF = 0x1
3942 12:44:09.235917 ===================================
3943 12:44:09.239183 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3944 12:44:09.245639 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3945 12:44:09.248993 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3946 12:44:09.252288 ===================================
3947 12:44:09.255629 LPDDR4 DRAM CONFIGURATION
3948 12:44:09.259133 ===================================
3949 12:44:09.259566 EX_ROW_EN[0] = 0x10
3950 12:44:09.262213 EX_ROW_EN[1] = 0x0
3951 12:44:09.262638 LP4Y_EN = 0x0
3952 12:44:09.265645 WORK_FSP = 0x0
3953 12:44:09.268591 WL = 0x2
3954 12:44:09.269021 RL = 0x2
3955 12:44:09.272181 BL = 0x2
3956 12:44:09.272610 RPST = 0x0
3957 12:44:09.275450 RD_PRE = 0x0
3958 12:44:09.275877 WR_PRE = 0x1
3959 12:44:09.278305 WR_PST = 0x0
3960 12:44:09.278731 DBI_WR = 0x0
3961 12:44:09.281721 DBI_RD = 0x0
3962 12:44:09.282150 OTF = 0x1
3963 12:44:09.285538 ===================================
3964 12:44:09.291579 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3965 12:44:09.296056 nWR fixed to 30
3966 12:44:09.298976 [ModeRegInit_LP4] CH0 RK0
3967 12:44:09.299405 [ModeRegInit_LP4] CH0 RK1
3968 12:44:09.302530 [ModeRegInit_LP4] CH1 RK0
3969 12:44:09.305655 [ModeRegInit_LP4] CH1 RK1
3970 12:44:09.306081 match AC timing 17
3971 12:44:09.312103 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3972 12:44:09.315686 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3973 12:44:09.318605 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3974 12:44:09.325494 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3975 12:44:09.329157 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3976 12:44:09.329652 ==
3977 12:44:09.332047 Dram Type= 6, Freq= 0, CH_0, rank 0
3978 12:44:09.335147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3979 12:44:09.338598 ==
3980 12:44:09.342010 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3981 12:44:09.348205 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3982 12:44:09.351823 [CA 0] Center 37 (7~67) winsize 61
3983 12:44:09.355176 [CA 1] Center 36 (6~67) winsize 62
3984 12:44:09.358267 [CA 2] Center 35 (5~65) winsize 61
3985 12:44:09.361818 [CA 3] Center 35 (5~65) winsize 61
3986 12:44:09.365227 [CA 4] Center 34 (4~65) winsize 62
3987 12:44:09.368189 [CA 5] Center 34 (4~64) winsize 61
3988 12:44:09.368612
3989 12:44:09.371392 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3990 12:44:09.371817
3991 12:44:09.374780 [CATrainingPosCal] consider 1 rank data
3992 12:44:09.378237 u2DelayCellTimex100 = 270/100 ps
3993 12:44:09.381077 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3994 12:44:09.384810 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
3995 12:44:09.391302 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3996 12:44:09.394217 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3997 12:44:09.397547 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3998 12:44:09.401056 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3999 12:44:09.401647
4000 12:44:09.404593 CA PerBit enable=1, Macro0, CA PI delay=34
4001 12:44:09.405015
4002 12:44:09.407528 [CBTSetCACLKResult] CA Dly = 34
4003 12:44:09.407952 CS Dly: 6 (0~37)
4004 12:44:09.411168 ==
4005 12:44:09.413990 Dram Type= 6, Freq= 0, CH_0, rank 1
4006 12:44:09.417382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4007 12:44:09.417812 ==
4008 12:44:09.421043 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4009 12:44:09.427267 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4010 12:44:09.431221 [CA 0] Center 37 (7~67) winsize 61
4011 12:44:09.434339 [CA 1] Center 37 (7~67) winsize 61
4012 12:44:09.437907 [CA 2] Center 35 (5~65) winsize 61
4013 12:44:09.440894 [CA 3] Center 35 (5~65) winsize 61
4014 12:44:09.444556 [CA 4] Center 34 (4~65) winsize 62
4015 12:44:09.447479 [CA 5] Center 34 (4~64) winsize 61
4016 12:44:09.447562
4017 12:44:09.451063 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4018 12:44:09.451146
4019 12:44:09.454006 [CATrainingPosCal] consider 2 rank data
4020 12:44:09.457329 u2DelayCellTimex100 = 270/100 ps
4021 12:44:09.460371 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4022 12:44:09.467018 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4023 12:44:09.470241 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4024 12:44:09.473705 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4025 12:44:09.477195 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4026 12:44:09.480248 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4027 12:44:09.480331
4028 12:44:09.483262 CA PerBit enable=1, Macro0, CA PI delay=34
4029 12:44:09.483346
4030 12:44:09.486678 [CBTSetCACLKResult] CA Dly = 34
4031 12:44:09.490044 CS Dly: 6 (0~38)
4032 12:44:09.490128
4033 12:44:09.493515 ----->DramcWriteLeveling(PI) begin...
4034 12:44:09.493595 ==
4035 12:44:09.496969 Dram Type= 6, Freq= 0, CH_0, rank 0
4036 12:44:09.499986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4037 12:44:09.500063 ==
4038 12:44:09.503458 Write leveling (Byte 0): 31 => 31
4039 12:44:09.506352 Write leveling (Byte 1): 32 => 32
4040 12:44:09.509509 DramcWriteLeveling(PI) end<-----
4041 12:44:09.509585
4042 12:44:09.509690 ==
4043 12:44:09.513036 Dram Type= 6, Freq= 0, CH_0, rank 0
4044 12:44:09.516732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4045 12:44:09.516857 ==
4046 12:44:09.519476 [Gating] SW mode calibration
4047 12:44:09.526255 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4048 12:44:09.532451 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4049 12:44:09.535728 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4050 12:44:09.542812 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4051 12:44:09.545956 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4052 12:44:09.549313 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
4053 12:44:09.555915 0 9 16 | B1->B0 | 2f2f 2d2d | 0 0 | (1 0) (0 0)
4054 12:44:09.558864 0 9 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
4055 12:44:09.562070 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4056 12:44:09.568965 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4057 12:44:09.572318 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4058 12:44:09.575536 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4059 12:44:09.582262 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4060 12:44:09.585843 0 10 12 | B1->B0 | 2424 2c2c | 0 0 | (0 0) (0 0)
4061 12:44:09.588848 0 10 16 | B1->B0 | 3131 3939 | 1 0 | (0 0) (1 1)
4062 12:44:09.595793 0 10 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4063 12:44:09.599186 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 12:44:09.601893 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 12:44:09.608371 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4066 12:44:09.611827 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4067 12:44:09.615208 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 12:44:09.621940 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4069 12:44:09.625396 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4070 12:44:09.628162 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4071 12:44:09.635040 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 12:44:09.638023 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 12:44:09.641381 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 12:44:09.648491 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 12:44:09.651473 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 12:44:09.654363 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 12:44:09.661110 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 12:44:09.664749 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 12:44:09.667696 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 12:44:09.674608 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 12:44:09.678111 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 12:44:09.681633 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 12:44:09.688166 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 12:44:09.691139 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4085 12:44:09.694741 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4086 12:44:09.697599 Total UI for P1: 0, mck2ui 16
4087 12:44:09.701329 best dqsien dly found for B0: ( 0, 13, 12)
4088 12:44:09.707448 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4089 12:44:09.707934 Total UI for P1: 0, mck2ui 16
4090 12:44:09.714121 best dqsien dly found for B1: ( 0, 13, 16)
4091 12:44:09.717564 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4092 12:44:09.721023 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4093 12:44:09.721588
4094 12:44:09.723857 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4095 12:44:09.727087 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4096 12:44:09.730662 [Gating] SW calibration Done
4097 12:44:09.731223 ==
4098 12:44:09.734159 Dram Type= 6, Freq= 0, CH_0, rank 0
4099 12:44:09.737431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4100 12:44:09.737906 ==
4101 12:44:09.740414 RX Vref Scan: 0
4102 12:44:09.740889
4103 12:44:09.741261 RX Vref 0 -> 0, step: 1
4104 12:44:09.743840
4105 12:44:09.744309 RX Delay -230 -> 252, step: 16
4106 12:44:09.750860 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4107 12:44:09.753671 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4108 12:44:09.757279 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4109 12:44:09.760324 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4110 12:44:09.766815 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4111 12:44:09.770336 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4112 12:44:09.773915 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4113 12:44:09.776477 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4114 12:44:09.780081 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4115 12:44:09.786473 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4116 12:44:09.789920 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4117 12:44:09.793451 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4118 12:44:09.796740 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4119 12:44:09.803231 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4120 12:44:09.806311 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4121 12:44:09.809629 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4122 12:44:09.810086 ==
4123 12:44:09.813205 Dram Type= 6, Freq= 0, CH_0, rank 0
4124 12:44:09.819351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4125 12:44:09.819762 ==
4126 12:44:09.820089 DQS Delay:
4127 12:44:09.822758 DQS0 = 0, DQS1 = 0
4128 12:44:09.823215 DQM Delay:
4129 12:44:09.823552 DQM0 = 37, DQM1 = 29
4130 12:44:09.826189 DQ Delay:
4131 12:44:09.829102 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4132 12:44:09.832129 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4133 12:44:09.835412 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4134 12:44:09.838781 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4135 12:44:09.838912
4136 12:44:09.838977
4137 12:44:09.839037 ==
4138 12:44:09.842096 Dram Type= 6, Freq= 0, CH_0, rank 0
4139 12:44:09.845767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4140 12:44:09.845850 ==
4141 12:44:09.845916
4142 12:44:09.845974
4143 12:44:09.848586 TX Vref Scan disable
4144 12:44:09.851956 == TX Byte 0 ==
4145 12:44:09.855481 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4146 12:44:09.858388 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4147 12:44:09.861933 == TX Byte 1 ==
4148 12:44:09.865039 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4149 12:44:09.868602 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4150 12:44:09.868685 ==
4151 12:44:09.871630 Dram Type= 6, Freq= 0, CH_0, rank 0
4152 12:44:09.875162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 12:44:09.878257 ==
4154 12:44:09.878338
4155 12:44:09.878403
4156 12:44:09.878463 TX Vref Scan disable
4157 12:44:09.882117 == TX Byte 0 ==
4158 12:44:09.885674 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4159 12:44:09.892359 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4160 12:44:09.892446 == TX Byte 1 ==
4161 12:44:09.895033 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4162 12:44:09.901860 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4163 12:44:09.901946
4164 12:44:09.902031 [DATLAT]
4165 12:44:09.902112 Freq=600, CH0 RK0
4166 12:44:09.902191
4167 12:44:09.905468 DATLAT Default: 0x9
4168 12:44:09.908734 0, 0xFFFF, sum = 0
4169 12:44:09.908821 1, 0xFFFF, sum = 0
4170 12:44:09.911856 2, 0xFFFF, sum = 0
4171 12:44:09.911943 3, 0xFFFF, sum = 0
4172 12:44:09.915059 4, 0xFFFF, sum = 0
4173 12:44:09.915146 5, 0xFFFF, sum = 0
4174 12:44:09.918534 6, 0xFFFF, sum = 0
4175 12:44:09.918621 7, 0xFFFF, sum = 0
4176 12:44:09.921449 8, 0x0, sum = 1
4177 12:44:09.921536 9, 0x0, sum = 2
4178 12:44:09.924814 10, 0x0, sum = 3
4179 12:44:09.924901 11, 0x0, sum = 4
4180 12:44:09.924988 best_step = 9
4181 12:44:09.925069
4182 12:44:09.928324 ==
4183 12:44:09.931267 Dram Type= 6, Freq= 0, CH_0, rank 0
4184 12:44:09.934835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4185 12:44:09.934935 ==
4186 12:44:09.935020 RX Vref Scan: 1
4187 12:44:09.935101
4188 12:44:09.938148 RX Vref 0 -> 0, step: 1
4189 12:44:09.938234
4190 12:44:09.941440 RX Delay -195 -> 252, step: 8
4191 12:44:09.941526
4192 12:44:09.944584 Set Vref, RX VrefLevel [Byte0]: 61
4193 12:44:09.948133 [Byte1]: 48
4194 12:44:09.948218
4195 12:44:09.951081 Final RX Vref Byte 0 = 61 to rank0
4196 12:44:09.954511 Final RX Vref Byte 1 = 48 to rank0
4197 12:44:09.957929 Final RX Vref Byte 0 = 61 to rank1
4198 12:44:09.960891 Final RX Vref Byte 1 = 48 to rank1==
4199 12:44:09.964469 Dram Type= 6, Freq= 0, CH_0, rank 0
4200 12:44:09.970908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4201 12:44:09.971014 ==
4202 12:44:09.971109 DQS Delay:
4203 12:44:09.971206 DQS0 = 0, DQS1 = 0
4204 12:44:09.974322 DQM Delay:
4205 12:44:09.974406 DQM0 = 36, DQM1 = 28
4206 12:44:09.977557 DQ Delay:
4207 12:44:09.980989 DQ0 =36, DQ1 =40, DQ2 =36, DQ3 =32
4208 12:44:09.983871 DQ4 =32, DQ5 =24, DQ6 =40, DQ7 =48
4209 12:44:09.987515 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4210 12:44:09.991180 DQ12 =36, DQ13 =32, DQ14 =40, DQ15 =36
4211 12:44:09.991266
4212 12:44:09.991350
4213 12:44:09.997801 [DQSOSCAuto] RK0, (LSB)MR18= 0x4140, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4214 12:44:10.000604 CH0 RK0: MR19=808, MR18=4140
4215 12:44:10.007517 CH0_RK0: MR19=0x808, MR18=0x4140, DQSOSC=397, MR23=63, INC=166, DEC=110
4216 12:44:10.007627
4217 12:44:10.010798 ----->DramcWriteLeveling(PI) begin...
4218 12:44:10.010912 ==
4219 12:44:10.014451 Dram Type= 6, Freq= 0, CH_0, rank 1
4220 12:44:10.017874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4221 12:44:10.017961 ==
4222 12:44:10.020505 Write leveling (Byte 0): 31 => 31
4223 12:44:10.023956 Write leveling (Byte 1): 31 => 31
4224 12:44:10.027471 DramcWriteLeveling(PI) end<-----
4225 12:44:10.027583
4226 12:44:10.027677 ==
4227 12:44:10.030817 Dram Type= 6, Freq= 0, CH_0, rank 1
4228 12:44:10.034188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4229 12:44:10.034271 ==
4230 12:44:10.037013 [Gating] SW mode calibration
4231 12:44:10.043845 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4232 12:44:10.050625 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4233 12:44:10.053867 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4234 12:44:10.060030 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4235 12:44:10.064088 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4236 12:44:10.066761 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 1)
4237 12:44:10.073542 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
4238 12:44:10.076443 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 12:44:10.079956 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 12:44:10.086322 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 12:44:10.089821 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4242 12:44:10.093315 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4243 12:44:10.099905 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4244 12:44:10.103017 0 10 12 | B1->B0 | 2525 3535 | 0 0 | (0 0) (1 1)
4245 12:44:10.106486 0 10 16 | B1->B0 | 3535 4444 | 0 0 | (0 0) (0 0)
4246 12:44:10.113268 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 12:44:10.116868 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 12:44:10.119476 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 12:44:10.126347 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4250 12:44:10.129891 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 12:44:10.133360 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4252 12:44:10.139329 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4253 12:44:10.142618 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4254 12:44:10.146056 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 12:44:10.152561 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 12:44:10.155944 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 12:44:10.159446 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 12:44:10.165749 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 12:44:10.168909 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 12:44:10.172793 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 12:44:10.178964 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 12:44:10.182459 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 12:44:10.185947 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 12:44:10.192468 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 12:44:10.195610 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 12:44:10.199184 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 12:44:10.205693 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 12:44:10.208723 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4269 12:44:10.212189 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4270 12:44:10.215806 Total UI for P1: 0, mck2ui 16
4271 12:44:10.218876 best dqsien dly found for B0: ( 0, 13, 12)
4272 12:44:10.225745 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4273 12:44:10.226221 Total UI for P1: 0, mck2ui 16
4274 12:44:10.232013 best dqsien dly found for B1: ( 0, 13, 16)
4275 12:44:10.235317 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4276 12:44:10.238980 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4277 12:44:10.239453
4278 12:44:10.242149 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4279 12:44:10.245518 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4280 12:44:10.248683 [Gating] SW calibration Done
4281 12:44:10.249157 ==
4282 12:44:10.251700 Dram Type= 6, Freq= 0, CH_0, rank 1
4283 12:44:10.255439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4284 12:44:10.255958 ==
4285 12:44:10.258737 RX Vref Scan: 0
4286 12:44:10.259380
4287 12:44:10.259765 RX Vref 0 -> 0, step: 1
4288 12:44:10.260126
4289 12:44:10.262017 RX Delay -230 -> 252, step: 16
4290 12:44:10.268504 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4291 12:44:10.271719 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4292 12:44:10.275375 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4293 12:44:10.278734 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4294 12:44:10.285450 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4295 12:44:10.288195 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4296 12:44:10.291775 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4297 12:44:10.294682 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4298 12:44:10.298358 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4299 12:44:10.304699 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4300 12:44:10.308341 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4301 12:44:10.311278 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4302 12:44:10.315096 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4303 12:44:10.321411 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4304 12:44:10.324328 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4305 12:44:10.327998 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4306 12:44:10.328469 ==
4307 12:44:10.331076 Dram Type= 6, Freq= 0, CH_0, rank 1
4308 12:44:10.337424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4309 12:44:10.337979 ==
4310 12:44:10.338360 DQS Delay:
4311 12:44:10.338712 DQS0 = 0, DQS1 = 0
4312 12:44:10.341189 DQM Delay:
4313 12:44:10.341657 DQM0 = 35, DQM1 = 28
4314 12:44:10.344075 DQ Delay:
4315 12:44:10.347432 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4316 12:44:10.347899 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4317 12:44:10.350812 DQ8 =17, DQ9 =9, DQ10 =33, DQ11 =17
4318 12:44:10.354622 DQ12 =33, DQ13 =41, DQ14 =41, DQ15 =33
4319 12:44:10.357725
4320 12:44:10.358292
4321 12:44:10.358670 ==
4322 12:44:10.360772 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 12:44:10.364057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 12:44:10.364526 ==
4325 12:44:10.364900
4326 12:44:10.365242
4327 12:44:10.367430 TX Vref Scan disable
4328 12:44:10.367934 == TX Byte 0 ==
4329 12:44:10.374119 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4330 12:44:10.377015 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4331 12:44:10.377488 == TX Byte 1 ==
4332 12:44:10.383819 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4333 12:44:10.387163 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4334 12:44:10.387783 ==
4335 12:44:10.390551 Dram Type= 6, Freq= 0, CH_0, rank 1
4336 12:44:10.393769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4337 12:44:10.394344 ==
4338 12:44:10.394725
4339 12:44:10.397293
4340 12:44:10.397860 TX Vref Scan disable
4341 12:44:10.400584 == TX Byte 0 ==
4342 12:44:10.403531 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4343 12:44:10.410324 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4344 12:44:10.411064 == TX Byte 1 ==
4345 12:44:10.413885 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4346 12:44:10.420319 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4347 12:44:10.420889
4348 12:44:10.421269 [DATLAT]
4349 12:44:10.421619 Freq=600, CH0 RK1
4350 12:44:10.421956
4351 12:44:10.423129 DATLAT Default: 0x9
4352 12:44:10.426688 0, 0xFFFF, sum = 0
4353 12:44:10.427302 1, 0xFFFF, sum = 0
4354 12:44:10.429680 2, 0xFFFF, sum = 0
4355 12:44:10.430164 3, 0xFFFF, sum = 0
4356 12:44:10.433521 4, 0xFFFF, sum = 0
4357 12:44:10.434098 5, 0xFFFF, sum = 0
4358 12:44:10.436265 6, 0xFFFF, sum = 0
4359 12:44:10.436743 7, 0xFFFF, sum = 0
4360 12:44:10.439836 8, 0x0, sum = 1
4361 12:44:10.440304 9, 0x0, sum = 2
4362 12:44:10.442785 10, 0x0, sum = 3
4363 12:44:10.443286 11, 0x0, sum = 4
4364 12:44:10.443657 best_step = 9
4365 12:44:10.444000
4366 12:44:10.446565 ==
4367 12:44:10.449738 Dram Type= 6, Freq= 0, CH_0, rank 1
4368 12:44:10.453064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4369 12:44:10.453528 ==
4370 12:44:10.453894 RX Vref Scan: 0
4371 12:44:10.454235
4372 12:44:10.456363 RX Vref 0 -> 0, step: 1
4373 12:44:10.456843
4374 12:44:10.459416 RX Delay -195 -> 252, step: 8
4375 12:44:10.466152 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4376 12:44:10.469085 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4377 12:44:10.472191 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4378 12:44:10.475642 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4379 12:44:10.482038 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4380 12:44:10.485536 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4381 12:44:10.489016 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4382 12:44:10.492466 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4383 12:44:10.498864 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4384 12:44:10.501842 iDelay=205, Bit 9, Center 12 (-139 ~ 164) 304
4385 12:44:10.505332 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4386 12:44:10.508894 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4387 12:44:10.515290 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4388 12:44:10.519082 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4389 12:44:10.522064 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4390 12:44:10.525511 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4391 12:44:10.526084 ==
4392 12:44:10.528256 Dram Type= 6, Freq= 0, CH_0, rank 1
4393 12:44:10.535391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4394 12:44:10.535905 ==
4395 12:44:10.536283 DQS Delay:
4396 12:44:10.538757 DQS0 = 0, DQS1 = 0
4397 12:44:10.539349 DQM Delay:
4398 12:44:10.539720 DQM0 = 34, DQM1 = 28
4399 12:44:10.541362 DQ Delay:
4400 12:44:10.545259 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4401 12:44:10.548503 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4402 12:44:10.551478 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4403 12:44:10.555002 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4404 12:44:10.555553
4405 12:44:10.555919
4406 12:44:10.561462 [DQSOSCAuto] RK1, (LSB)MR18= 0x6e3d, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4407 12:44:10.565084 CH0 RK1: MR19=808, MR18=6E3D
4408 12:44:10.571570 CH0_RK1: MR19=0x808, MR18=0x6E3D, DQSOSC=389, MR23=63, INC=173, DEC=115
4409 12:44:10.574773 [RxdqsGatingPostProcess] freq 600
4410 12:44:10.578112 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4411 12:44:10.581400 Pre-setting of DQS Precalculation
4412 12:44:10.588366 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4413 12:44:10.588926 ==
4414 12:44:10.591137 Dram Type= 6, Freq= 0, CH_1, rank 0
4415 12:44:10.594617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4416 12:44:10.595133 ==
4417 12:44:10.600926 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4418 12:44:10.607889 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4419 12:44:10.610734 [CA 0] Center 36 (7~66) winsize 60
4420 12:44:10.614235 [CA 1] Center 36 (6~67) winsize 62
4421 12:44:10.618041 [CA 2] Center 34 (4~65) winsize 62
4422 12:44:10.620699 [CA 3] Center 34 (4~65) winsize 62
4423 12:44:10.624406 [CA 4] Center 34 (4~65) winsize 62
4424 12:44:10.627670 [CA 5] Center 34 (4~65) winsize 62
4425 12:44:10.628145
4426 12:44:10.630931 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4427 12:44:10.631488
4428 12:44:10.634481 [CATrainingPosCal] consider 1 rank data
4429 12:44:10.637203 u2DelayCellTimex100 = 270/100 ps
4430 12:44:10.640997 CA0 delay=36 (7~66),Diff = 2 PI (19 cell)
4431 12:44:10.643958 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4432 12:44:10.647658 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4433 12:44:10.650606 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4434 12:44:10.654113 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4435 12:44:10.660358 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4436 12:44:10.660931
4437 12:44:10.663943 CA PerBit enable=1, Macro0, CA PI delay=34
4438 12:44:10.664416
4439 12:44:10.666794 [CBTSetCACLKResult] CA Dly = 34
4440 12:44:10.667416 CS Dly: 4 (0~35)
4441 12:44:10.667796 ==
4442 12:44:10.670485 Dram Type= 6, Freq= 0, CH_1, rank 1
4443 12:44:10.673776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4444 12:44:10.676720 ==
4445 12:44:10.679674 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4446 12:44:10.686464 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4447 12:44:10.689606 [CA 0] Center 37 (7~67) winsize 61
4448 12:44:10.693433 [CA 1] Center 36 (6~67) winsize 62
4449 12:44:10.696720 [CA 2] Center 35 (5~65) winsize 61
4450 12:44:10.699859 [CA 3] Center 34 (4~65) winsize 62
4451 12:44:10.703287 [CA 4] Center 34 (4~65) winsize 62
4452 12:44:10.706656 [CA 5] Center 34 (4~65) winsize 62
4453 12:44:10.707177
4454 12:44:10.709690 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4455 12:44:10.710260
4456 12:44:10.712923 [CATrainingPosCal] consider 2 rank data
4457 12:44:10.716871 u2DelayCellTimex100 = 270/100 ps
4458 12:44:10.719319 CA0 delay=36 (7~66),Diff = 2 PI (19 cell)
4459 12:44:10.723159 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4460 12:44:10.729568 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4461 12:44:10.732998 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4462 12:44:10.736500 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4463 12:44:10.739554 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4464 12:44:10.740120
4465 12:44:10.742403 CA PerBit enable=1, Macro0, CA PI delay=34
4466 12:44:10.743012
4467 12:44:10.746129 [CBTSetCACLKResult] CA Dly = 34
4468 12:44:10.746688 CS Dly: 5 (0~37)
4469 12:44:10.749220
4470 12:44:10.752588 ----->DramcWriteLeveling(PI) begin...
4471 12:44:10.753065 ==
4472 12:44:10.755646 Dram Type= 6, Freq= 0, CH_1, rank 0
4473 12:44:10.759196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4474 12:44:10.759763 ==
4475 12:44:10.762863 Write leveling (Byte 0): 28 => 28
4476 12:44:10.765774 Write leveling (Byte 1): 31 => 31
4477 12:44:10.768855 DramcWriteLeveling(PI) end<-----
4478 12:44:10.769324
4479 12:44:10.769722 ==
4480 12:44:10.772328 Dram Type= 6, Freq= 0, CH_1, rank 0
4481 12:44:10.775816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4482 12:44:10.776291 ==
4483 12:44:10.779091 [Gating] SW mode calibration
4484 12:44:10.785149 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4485 12:44:10.792186 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4486 12:44:10.795192 0 9 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
4487 12:44:10.798737 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4488 12:44:10.805458 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4489 12:44:10.808627 0 9 12 | B1->B0 | 3333 3232 | 0 1 | (0 1) (1 0)
4490 12:44:10.811969 0 9 16 | B1->B0 | 2828 2525 | 1 0 | (1 0) (0 0)
4491 12:44:10.818191 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4492 12:44:10.821530 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4493 12:44:10.824383 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4494 12:44:10.831459 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4495 12:44:10.834405 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4496 12:44:10.837934 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4497 12:44:10.844467 0 10 12 | B1->B0 | 2e2e 2b2b | 0 1 | (1 1) (0 0)
4498 12:44:10.847528 0 10 16 | B1->B0 | 3d3d 4040 | 0 0 | (1 1) (0 0)
4499 12:44:10.851017 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 12:44:10.857485 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 12:44:10.860507 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 12:44:10.863926 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 12:44:10.870477 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 12:44:10.873817 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 12:44:10.877469 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4506 12:44:10.883651 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 12:44:10.887011 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 12:44:10.890587 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 12:44:10.897187 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 12:44:10.900059 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 12:44:10.903562 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 12:44:10.910161 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 12:44:10.913524 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 12:44:10.916840 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 12:44:10.923354 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 12:44:10.926694 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 12:44:10.929824 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 12:44:10.936208 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 12:44:10.939212 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 12:44:10.942788 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 12:44:10.949379 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4522 12:44:10.952295 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4523 12:44:10.955849 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4524 12:44:10.959338 Total UI for P1: 0, mck2ui 16
4525 12:44:10.962249 best dqsien dly found for B0: ( 0, 13, 14)
4526 12:44:10.966085 Total UI for P1: 0, mck2ui 16
4527 12:44:10.968986 best dqsien dly found for B1: ( 0, 13, 16)
4528 12:44:10.975486 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4529 12:44:10.978952 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4530 12:44:10.979028
4531 12:44:10.982454 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4532 12:44:10.985313 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4533 12:44:10.988744 [Gating] SW calibration Done
4534 12:44:10.988817 ==
4535 12:44:10.991873 Dram Type= 6, Freq= 0, CH_1, rank 0
4536 12:44:10.994923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4537 12:44:10.995002 ==
4538 12:44:10.998615 RX Vref Scan: 0
4539 12:44:10.998722
4540 12:44:10.998812 RX Vref 0 -> 0, step: 1
4541 12:44:10.998927
4542 12:44:11.001935 RX Delay -230 -> 252, step: 16
4543 12:44:11.008204 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4544 12:44:11.011592 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4545 12:44:11.014984 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4546 12:44:11.018462 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4547 12:44:11.021304 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4548 12:44:11.028392 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4549 12:44:11.031706 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4550 12:44:11.034392 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4551 12:44:11.038116 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4552 12:44:11.044539 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4553 12:44:11.048085 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4554 12:44:11.051024 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4555 12:44:11.054611 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4556 12:44:11.061149 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4557 12:44:11.064799 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4558 12:44:11.067727 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4559 12:44:11.067806 ==
4560 12:44:11.071305 Dram Type= 6, Freq= 0, CH_1, rank 0
4561 12:44:11.074198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4562 12:44:11.077786 ==
4563 12:44:11.077889 DQS Delay:
4564 12:44:11.077980 DQS0 = 0, DQS1 = 0
4565 12:44:11.081413 DQM Delay:
4566 12:44:11.081486 DQM0 = 39, DQM1 = 27
4567 12:44:11.084194 DQ Delay:
4568 12:44:11.084263 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4569 12:44:11.087801 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4570 12:44:11.090731 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4571 12:44:11.094352 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4572 12:44:11.097569
4573 12:44:11.097701
4574 12:44:11.097797 ==
4575 12:44:11.100715 Dram Type= 6, Freq= 0, CH_1, rank 0
4576 12:44:11.104143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4577 12:44:11.104242 ==
4578 12:44:11.104332
4579 12:44:11.104418
4580 12:44:11.107535 TX Vref Scan disable
4581 12:44:11.107631 == TX Byte 0 ==
4582 12:44:11.114185 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4583 12:44:11.117626 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4584 12:44:11.117738 == TX Byte 1 ==
4585 12:44:11.123994 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4586 12:44:11.127533 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4587 12:44:11.127635 ==
4588 12:44:11.130388 Dram Type= 6, Freq= 0, CH_1, rank 0
4589 12:44:11.133830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4590 12:44:11.133914 ==
4591 12:44:11.134010
4592 12:44:11.134099
4593 12:44:11.137243 TX Vref Scan disable
4594 12:44:11.140764 == TX Byte 0 ==
4595 12:44:11.143558 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4596 12:44:11.150166 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4597 12:44:11.150260 == TX Byte 1 ==
4598 12:44:11.153729 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4599 12:44:11.160167 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4600 12:44:11.160292
4601 12:44:11.160373 [DATLAT]
4602 12:44:11.160434 Freq=600, CH1 RK0
4603 12:44:11.160491
4604 12:44:11.163599 DATLAT Default: 0x9
4605 12:44:11.163683 0, 0xFFFF, sum = 0
4606 12:44:11.166699 1, 0xFFFF, sum = 0
4607 12:44:11.170278 2, 0xFFFF, sum = 0
4608 12:44:11.170386 3, 0xFFFF, sum = 0
4609 12:44:11.173165 4, 0xFFFF, sum = 0
4610 12:44:11.173248 5, 0xFFFF, sum = 0
4611 12:44:11.176704 6, 0xFFFF, sum = 0
4612 12:44:11.176794 7, 0xFFFF, sum = 0
4613 12:44:11.180192 8, 0x0, sum = 1
4614 12:44:11.180302 9, 0x0, sum = 2
4615 12:44:11.183211 10, 0x0, sum = 3
4616 12:44:11.183296 11, 0x0, sum = 4
4617 12:44:11.183362 best_step = 9
4618 12:44:11.183420
4619 12:44:11.186485 ==
4620 12:44:11.189989 Dram Type= 6, Freq= 0, CH_1, rank 0
4621 12:44:11.193137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4622 12:44:11.193229 ==
4623 12:44:11.193318 RX Vref Scan: 1
4624 12:44:11.193400
4625 12:44:11.196624 RX Vref 0 -> 0, step: 1
4626 12:44:11.196729
4627 12:44:11.200034 RX Delay -195 -> 252, step: 8
4628 12:44:11.200124
4629 12:44:11.203265 Set Vref, RX VrefLevel [Byte0]: 57
4630 12:44:11.206720 [Byte1]: 55
4631 12:44:11.206808
4632 12:44:11.209655 Final RX Vref Byte 0 = 57 to rank0
4633 12:44:11.213037 Final RX Vref Byte 1 = 55 to rank0
4634 12:44:11.216083 Final RX Vref Byte 0 = 57 to rank1
4635 12:44:11.219541 Final RX Vref Byte 1 = 55 to rank1==
4636 12:44:11.222775 Dram Type= 6, Freq= 0, CH_1, rank 0
4637 12:44:11.226302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4638 12:44:11.229766 ==
4639 12:44:11.229852 DQS Delay:
4640 12:44:11.229941 DQS0 = 0, DQS1 = 0
4641 12:44:11.232963 DQM Delay:
4642 12:44:11.233049 DQM0 = 41, DQM1 = 31
4643 12:44:11.236186 DQ Delay:
4644 12:44:11.236271 DQ0 =48, DQ1 =36, DQ2 =28, DQ3 =36
4645 12:44:11.239721 DQ4 =40, DQ5 =52, DQ6 =52, DQ7 =36
4646 12:44:11.243093 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =24
4647 12:44:11.245852 DQ12 =40, DQ13 =36, DQ14 =40, DQ15 =40
4648 12:44:11.245937
4649 12:44:11.249282
4650 12:44:11.255861 [DQSOSCAuto] RK0, (LSB)MR18= 0x2633, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 402 ps
4651 12:44:11.259347 CH1 RK0: MR19=808, MR18=2633
4652 12:44:11.265832 CH1_RK0: MR19=0x808, MR18=0x2633, DQSOSC=400, MR23=63, INC=163, DEC=109
4653 12:44:11.265918
4654 12:44:11.269370 ----->DramcWriteLeveling(PI) begin...
4655 12:44:11.269457 ==
4656 12:44:11.272279 Dram Type= 6, Freq= 0, CH_1, rank 1
4657 12:44:11.275874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4658 12:44:11.275960 ==
4659 12:44:11.279308 Write leveling (Byte 0): 28 => 28
4660 12:44:11.282208 Write leveling (Byte 1): 32 => 32
4661 12:44:11.285727 DramcWriteLeveling(PI) end<-----
4662 12:44:11.285812
4663 12:44:11.285898 ==
4664 12:44:11.289343 Dram Type= 6, Freq= 0, CH_1, rank 1
4665 12:44:11.292150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4666 12:44:11.292237 ==
4667 12:44:11.295206 [Gating] SW mode calibration
4668 12:44:11.301902 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4669 12:44:11.308576 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4670 12:44:11.312029 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4671 12:44:11.318582 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4672 12:44:11.321855 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4673 12:44:11.324969 0 9 12 | B1->B0 | 3131 2f2f | 1 0 | (1 0) (0 0)
4674 12:44:11.331974 0 9 16 | B1->B0 | 2d2d 2424 | 0 0 | (0 0) (0 0)
4675 12:44:11.335184 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4676 12:44:11.338501 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4677 12:44:11.344877 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4678 12:44:11.348156 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4679 12:44:11.351672 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4680 12:44:11.357890 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4681 12:44:11.361139 0 10 12 | B1->B0 | 2d2d 3f3f | 0 0 | (0 0) (1 1)
4682 12:44:11.364384 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4683 12:44:11.371188 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 12:44:11.374716 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 12:44:11.378126 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4686 12:44:11.384495 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4687 12:44:11.388062 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4688 12:44:11.391086 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4689 12:44:11.397767 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4690 12:44:11.400642 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 12:44:11.404157 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 12:44:11.410696 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 12:44:11.414098 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 12:44:11.417334 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 12:44:11.423898 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 12:44:11.427170 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 12:44:11.430329 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 12:44:11.437211 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 12:44:11.440507 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 12:44:11.443864 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 12:44:11.450142 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 12:44:11.453701 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 12:44:11.456902 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 12:44:11.463401 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 12:44:11.466382 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4706 12:44:11.470188 Total UI for P1: 0, mck2ui 16
4707 12:44:11.473169 best dqsien dly found for B0: ( 0, 13, 10)
4708 12:44:11.476540 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4709 12:44:11.479512 Total UI for P1: 0, mck2ui 16
4710 12:44:11.483373 best dqsien dly found for B1: ( 0, 13, 12)
4711 12:44:11.486311 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4712 12:44:11.489862 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4713 12:44:11.489940
4714 12:44:11.496272 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4715 12:44:11.499805 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4716 12:44:11.503187 [Gating] SW calibration Done
4717 12:44:11.503266 ==
4718 12:44:11.506050 Dram Type= 6, Freq= 0, CH_1, rank 1
4719 12:44:11.509640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4720 12:44:11.509720 ==
4721 12:44:11.509784 RX Vref Scan: 0
4722 12:44:11.512552
4723 12:44:11.512634 RX Vref 0 -> 0, step: 1
4724 12:44:11.512698
4725 12:44:11.516220 RX Delay -230 -> 252, step: 16
4726 12:44:11.519047 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4727 12:44:11.526185 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4728 12:44:11.529399 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4729 12:44:11.532299 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4730 12:44:11.535471 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4731 12:44:11.542202 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4732 12:44:11.545291 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4733 12:44:11.548684 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4734 12:44:11.551974 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4735 12:44:11.555437 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4736 12:44:11.561819 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4737 12:44:11.565260 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4738 12:44:11.568957 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4739 12:44:11.572325 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4740 12:44:11.578609 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4741 12:44:11.581682 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4742 12:44:11.581767 ==
4743 12:44:11.585066 Dram Type= 6, Freq= 0, CH_1, rank 1
4744 12:44:11.588361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4745 12:44:11.588439 ==
4746 12:44:11.591895 DQS Delay:
4747 12:44:11.591983 DQS0 = 0, DQS1 = 0
4748 12:44:11.595390 DQM Delay:
4749 12:44:11.595475 DQM0 = 37, DQM1 = 31
4750 12:44:11.595558 DQ Delay:
4751 12:44:11.598396 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4752 12:44:11.601896 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4753 12:44:11.604681 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4754 12:44:11.608182 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =41
4755 12:44:11.608262
4756 12:44:11.608343
4757 12:44:11.611770 ==
4758 12:44:11.611848 Dram Type= 6, Freq= 0, CH_1, rank 1
4759 12:44:11.618129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4760 12:44:11.618212 ==
4761 12:44:11.618300
4762 12:44:11.618376
4763 12:44:11.621446 TX Vref Scan disable
4764 12:44:11.621522 == TX Byte 0 ==
4765 12:44:11.627846 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4766 12:44:11.631189 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4767 12:44:11.631275 == TX Byte 1 ==
4768 12:44:11.638038 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4769 12:44:11.641362 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4770 12:44:11.641469 ==
4771 12:44:11.644544 Dram Type= 6, Freq= 0, CH_1, rank 1
4772 12:44:11.647919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4773 12:44:11.648022 ==
4774 12:44:11.648122
4775 12:44:11.648224
4776 12:44:11.651125 TX Vref Scan disable
4777 12:44:11.654330 == TX Byte 0 ==
4778 12:44:11.657716 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4779 12:44:11.660702 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4780 12:44:11.664120 == TX Byte 1 ==
4781 12:44:11.667467 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4782 12:44:11.673727 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4783 12:44:11.673815
4784 12:44:11.673882 [DATLAT]
4785 12:44:11.673943 Freq=600, CH1 RK1
4786 12:44:11.674001
4787 12:44:11.677230 DATLAT Default: 0x9
4788 12:44:11.677300 0, 0xFFFF, sum = 0
4789 12:44:11.680647 1, 0xFFFF, sum = 0
4790 12:44:11.680731 2, 0xFFFF, sum = 0
4791 12:44:11.683865 3, 0xFFFF, sum = 0
4792 12:44:11.687365 4, 0xFFFF, sum = 0
4793 12:44:11.687448 5, 0xFFFF, sum = 0
4794 12:44:11.690666 6, 0xFFFF, sum = 0
4795 12:44:11.690775 7, 0xFFFF, sum = 0
4796 12:44:11.693817 8, 0x0, sum = 1
4797 12:44:11.693901 9, 0x0, sum = 2
4798 12:44:11.693972 10, 0x0, sum = 3
4799 12:44:11.697335 11, 0x0, sum = 4
4800 12:44:11.697419 best_step = 9
4801 12:44:11.697484
4802 12:44:11.697544 ==
4803 12:44:11.700193 Dram Type= 6, Freq= 0, CH_1, rank 1
4804 12:44:11.707119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4805 12:44:11.707203 ==
4806 12:44:11.707300 RX Vref Scan: 0
4807 12:44:11.707407
4808 12:44:11.710425 RX Vref 0 -> 0, step: 1
4809 12:44:11.710506
4810 12:44:11.713303 RX Delay -195 -> 252, step: 8
4811 12:44:11.720216 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4812 12:44:11.723126 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4813 12:44:11.726719 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4814 12:44:11.729718 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4815 12:44:11.733123 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4816 12:44:11.739657 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4817 12:44:11.743394 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4818 12:44:11.746417 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4819 12:44:11.749591 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4820 12:44:11.756393 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4821 12:44:11.759822 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4822 12:44:11.762784 iDelay=205, Bit 11, Center 28 (-131 ~ 188) 320
4823 12:44:11.766051 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4824 12:44:11.773000 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4825 12:44:11.776330 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4826 12:44:11.779415 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4827 12:44:11.779498 ==
4828 12:44:11.782765 Dram Type= 6, Freq= 0, CH_1, rank 1
4829 12:44:11.786036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4830 12:44:11.789337 ==
4831 12:44:11.789419 DQS Delay:
4832 12:44:11.789489 DQS0 = 0, DQS1 = 0
4833 12:44:11.792807 DQM Delay:
4834 12:44:11.792889 DQM0 = 38, DQM1 = 31
4835 12:44:11.795630 DQ Delay:
4836 12:44:11.798990 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4837 12:44:11.799074 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =32
4838 12:44:11.802266 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4839 12:44:11.808764 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =36
4840 12:44:11.808849
4841 12:44:11.808919
4842 12:44:11.815763 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b5a, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
4843 12:44:11.819257 CH1 RK1: MR19=808, MR18=3B5A
4844 12:44:11.825739 CH1_RK1: MR19=0x808, MR18=0x3B5A, DQSOSC=392, MR23=63, INC=170, DEC=113
4845 12:44:11.828651 [RxdqsGatingPostProcess] freq 600
4846 12:44:11.832217 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4847 12:44:11.835063 Pre-setting of DQS Precalculation
4848 12:44:11.841981 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4849 12:44:11.848807 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4850 12:44:11.855242 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4851 12:44:11.855352
4852 12:44:11.855418
4853 12:44:11.858409 [Calibration Summary] 1200 Mbps
4854 12:44:11.858483 CH 0, Rank 0
4855 12:44:11.861620 SW Impedance : PASS
4856 12:44:11.865187 DUTY Scan : NO K
4857 12:44:11.865329 ZQ Calibration : PASS
4858 12:44:11.868293 Jitter Meter : NO K
4859 12:44:11.871738 CBT Training : PASS
4860 12:44:11.871828 Write leveling : PASS
4861 12:44:11.875015 RX DQS gating : PASS
4862 12:44:11.878424 RX DQ/DQS(RDDQC) : PASS
4863 12:44:11.878494 TX DQ/DQS : PASS
4864 12:44:11.881692 RX DATLAT : PASS
4865 12:44:11.885284 RX DQ/DQS(Engine): PASS
4866 12:44:11.885393 TX OE : NO K
4867 12:44:11.885486 All Pass.
4868 12:44:11.888049
4869 12:44:11.888138 CH 0, Rank 1
4870 12:44:11.891436 SW Impedance : PASS
4871 12:44:11.891596 DUTY Scan : NO K
4872 12:44:11.894681 ZQ Calibration : PASS
4873 12:44:11.894788 Jitter Meter : NO K
4874 12:44:11.898148 CBT Training : PASS
4875 12:44:11.901683 Write leveling : PASS
4876 12:44:11.901785 RX DQS gating : PASS
4877 12:44:11.904968 RX DQ/DQS(RDDQC) : PASS
4878 12:44:11.908339 TX DQ/DQS : PASS
4879 12:44:11.908411 RX DATLAT : PASS
4880 12:44:11.911358 RX DQ/DQS(Engine): PASS
4881 12:44:11.914882 TX OE : NO K
4882 12:44:11.914956 All Pass.
4883 12:44:11.915018
4884 12:44:11.915076 CH 1, Rank 0
4885 12:44:11.918543 SW Impedance : PASS
4886 12:44:11.921349 DUTY Scan : NO K
4887 12:44:11.921431 ZQ Calibration : PASS
4888 12:44:11.924680 Jitter Meter : NO K
4889 12:44:11.928189 CBT Training : PASS
4890 12:44:11.928271 Write leveling : PASS
4891 12:44:11.931067 RX DQS gating : PASS
4892 12:44:11.934641 RX DQ/DQS(RDDQC) : PASS
4893 12:44:11.934723 TX DQ/DQS : PASS
4894 12:44:11.938092 RX DATLAT : PASS
4895 12:44:11.941101 RX DQ/DQS(Engine): PASS
4896 12:44:11.941183 TX OE : NO K
4897 12:44:11.944621 All Pass.
4898 12:44:11.944703
4899 12:44:11.944768 CH 1, Rank 1
4900 12:44:11.947454 SW Impedance : PASS
4901 12:44:11.947536 DUTY Scan : NO K
4902 12:44:11.951332 ZQ Calibration : PASS
4903 12:44:11.954516 Jitter Meter : NO K
4904 12:44:11.954598 CBT Training : PASS
4905 12:44:11.957813 Write leveling : PASS
4906 12:44:11.961099 RX DQS gating : PASS
4907 12:44:11.961180 RX DQ/DQS(RDDQC) : PASS
4908 12:44:11.964204 TX DQ/DQS : PASS
4909 12:44:11.964286 RX DATLAT : PASS
4910 12:44:11.967290 RX DQ/DQS(Engine): PASS
4911 12:44:11.970988 TX OE : NO K
4912 12:44:11.971071 All Pass.
4913 12:44:11.971136
4914 12:44:11.974284 DramC Write-DBI off
4915 12:44:11.977217 PER_BANK_REFRESH: Hybrid Mode
4916 12:44:11.977300 TX_TRACKING: ON
4917 12:44:11.987408 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4918 12:44:11.990262 [FAST_K] Save calibration result to emmc
4919 12:44:11.993797 dramc_set_vcore_voltage set vcore to 662500
4920 12:44:11.997173 Read voltage for 933, 3
4921 12:44:11.997248 Vio18 = 0
4922 12:44:11.997311 Vcore = 662500
4923 12:44:12.000259 Vdram = 0
4924 12:44:12.000363 Vddq = 0
4925 12:44:12.000451 Vmddr = 0
4926 12:44:12.006784 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4927 12:44:12.010226 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4928 12:44:12.013659 MEM_TYPE=3, freq_sel=17
4929 12:44:12.016692 sv_algorithm_assistance_LP4_1600
4930 12:44:12.020066 ============ PULL DRAM RESETB DOWN ============
4931 12:44:12.023608 ========== PULL DRAM RESETB DOWN end =========
4932 12:44:12.029917 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4933 12:44:12.033456 ===================================
4934 12:44:12.033556 LPDDR4 DRAM CONFIGURATION
4935 12:44:12.036496 ===================================
4936 12:44:12.039934 EX_ROW_EN[0] = 0x0
4937 12:44:12.043315 EX_ROW_EN[1] = 0x0
4938 12:44:12.043418 LP4Y_EN = 0x0
4939 12:44:12.046930 WORK_FSP = 0x0
4940 12:44:12.047027 WL = 0x3
4941 12:44:12.049853 RL = 0x3
4942 12:44:12.049921 BL = 0x2
4943 12:44:12.053154 RPST = 0x0
4944 12:44:12.053236 RD_PRE = 0x0
4945 12:44:12.056386 WR_PRE = 0x1
4946 12:44:12.056468 WR_PST = 0x0
4947 12:44:12.059781 DBI_WR = 0x0
4948 12:44:12.059863 DBI_RD = 0x0
4949 12:44:12.063356 OTF = 0x1
4950 12:44:12.066160 ===================================
4951 12:44:12.069475 ===================================
4952 12:44:12.069557 ANA top config
4953 12:44:12.072779 ===================================
4954 12:44:12.076192 DLL_ASYNC_EN = 0
4955 12:44:12.079455 ALL_SLAVE_EN = 1
4956 12:44:12.083109 NEW_RANK_MODE = 1
4957 12:44:12.083192 DLL_IDLE_MODE = 1
4958 12:44:12.086345 LP45_APHY_COMB_EN = 1
4959 12:44:12.089452 TX_ODT_DIS = 1
4960 12:44:12.092605 NEW_8X_MODE = 1
4961 12:44:12.095788 ===================================
4962 12:44:12.099393 ===================================
4963 12:44:12.102812 data_rate = 1866
4964 12:44:12.105666 CKR = 1
4965 12:44:12.105774 DQ_P2S_RATIO = 8
4966 12:44:12.108928 ===================================
4967 12:44:12.112450 CA_P2S_RATIO = 8
4968 12:44:12.116094 DQ_CA_OPEN = 0
4969 12:44:12.118763 DQ_SEMI_OPEN = 0
4970 12:44:12.122272 CA_SEMI_OPEN = 0
4971 12:44:12.125762 CA_FULL_RATE = 0
4972 12:44:12.125881 DQ_CKDIV4_EN = 1
4973 12:44:12.128930 CA_CKDIV4_EN = 1
4974 12:44:12.131974 CA_PREDIV_EN = 0
4975 12:44:12.135471 PH8_DLY = 0
4976 12:44:12.138373 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4977 12:44:12.141846 DQ_AAMCK_DIV = 4
4978 12:44:12.144909 CA_AAMCK_DIV = 4
4979 12:44:12.144993 CA_ADMCK_DIV = 4
4980 12:44:12.148380 DQ_TRACK_CA_EN = 0
4981 12:44:12.151935 CA_PICK = 933
4982 12:44:12.154720 CA_MCKIO = 933
4983 12:44:12.158094 MCKIO_SEMI = 0
4984 12:44:12.161428 PLL_FREQ = 3732
4985 12:44:12.165145 DQ_UI_PI_RATIO = 32
4986 12:44:12.165228 CA_UI_PI_RATIO = 0
4987 12:44:12.168009 ===================================
4988 12:44:12.171699 ===================================
4989 12:44:12.174910 memory_type:LPDDR4
4990 12:44:12.177897 GP_NUM : 10
4991 12:44:12.177980 SRAM_EN : 1
4992 12:44:12.181140 MD32_EN : 0
4993 12:44:12.184866 ===================================
4994 12:44:12.188057 [ANA_INIT] >>>>>>>>>>>>>>
4995 12:44:12.191318 <<<<<< [CONFIGURE PHASE]: ANA_TX
4996 12:44:12.194457 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4997 12:44:12.197656 ===================================
4998 12:44:12.197740 data_rate = 1866,PCW = 0X8f00
4999 12:44:12.201199 ===================================
5000 12:44:12.207251 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5001 12:44:12.211040 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5002 12:44:12.217433 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5003 12:44:12.220850 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5004 12:44:12.223877 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5005 12:44:12.227718 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5006 12:44:12.230404 [ANA_INIT] flow start
5007 12:44:12.233866 [ANA_INIT] PLL >>>>>>>>
5008 12:44:12.233949 [ANA_INIT] PLL <<<<<<<<
5009 12:44:12.237381 [ANA_INIT] MIDPI >>>>>>>>
5010 12:44:12.240340 [ANA_INIT] MIDPI <<<<<<<<
5011 12:44:12.240423 [ANA_INIT] DLL >>>>>>>>
5012 12:44:12.243814 [ANA_INIT] flow end
5013 12:44:12.247323 ============ LP4 DIFF to SE enter ============
5014 12:44:12.253739 ============ LP4 DIFF to SE exit ============
5015 12:44:12.253822 [ANA_INIT] <<<<<<<<<<<<<
5016 12:44:12.257230 [Flow] Enable top DCM control >>>>>
5017 12:44:12.260350 [Flow] Enable top DCM control <<<<<
5018 12:44:12.263484 Enable DLL master slave shuffle
5019 12:44:12.270400 ==============================================================
5020 12:44:12.270483 Gating Mode config
5021 12:44:12.276939 ==============================================================
5022 12:44:12.280260 Config description:
5023 12:44:12.290208 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5024 12:44:12.296601 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5025 12:44:12.299941 SELPH_MODE 0: By rank 1: By Phase
5026 12:44:12.306601 ==============================================================
5027 12:44:12.309570 GAT_TRACK_EN = 1
5028 12:44:12.313168 RX_GATING_MODE = 2
5029 12:44:12.313251 RX_GATING_TRACK_MODE = 2
5030 12:44:12.316535 SELPH_MODE = 1
5031 12:44:12.319730 PICG_EARLY_EN = 1
5032 12:44:12.322965 VALID_LAT_VALUE = 1
5033 12:44:12.329813 ==============================================================
5034 12:44:12.332724 Enter into Gating configuration >>>>
5035 12:44:12.336367 Exit from Gating configuration <<<<
5036 12:44:12.339455 Enter into DVFS_PRE_config >>>>>
5037 12:44:12.349258 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5038 12:44:12.352804 Exit from DVFS_PRE_config <<<<<
5039 12:44:12.356332 Enter into PICG configuration >>>>
5040 12:44:12.359292 Exit from PICG configuration <<<<
5041 12:44:12.362789 [RX_INPUT] configuration >>>>>
5042 12:44:12.365679 [RX_INPUT] configuration <<<<<
5043 12:44:12.369040 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5044 12:44:12.375991 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5045 12:44:12.382356 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5046 12:44:12.388780 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5047 12:44:12.395287 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5048 12:44:12.398782 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5049 12:44:12.405395 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5050 12:44:12.408514 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5051 12:44:12.412416 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5052 12:44:12.415206 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5053 12:44:12.422117 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5054 12:44:12.425381 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5055 12:44:12.428622 ===================================
5056 12:44:12.431976 LPDDR4 DRAM CONFIGURATION
5057 12:44:12.434738 ===================================
5058 12:44:12.434823 EX_ROW_EN[0] = 0x0
5059 12:44:12.438187 EX_ROW_EN[1] = 0x0
5060 12:44:12.438272 LP4Y_EN = 0x0
5061 12:44:12.441382 WORK_FSP = 0x0
5062 12:44:12.441465 WL = 0x3
5063 12:44:12.444930 RL = 0x3
5064 12:44:12.448429 BL = 0x2
5065 12:44:12.448512 RPST = 0x0
5066 12:44:12.451359 RD_PRE = 0x0
5067 12:44:12.451442 WR_PRE = 0x1
5068 12:44:12.454958 WR_PST = 0x0
5069 12:44:12.455041 DBI_WR = 0x0
5070 12:44:12.458557 DBI_RD = 0x0
5071 12:44:12.458640 OTF = 0x1
5072 12:44:12.461295 ===================================
5073 12:44:12.464836 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5074 12:44:12.471334 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5075 12:44:12.474735 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5076 12:44:12.478191 ===================================
5077 12:44:12.481138 LPDDR4 DRAM CONFIGURATION
5078 12:44:12.484584 ===================================
5079 12:44:12.484667 EX_ROW_EN[0] = 0x10
5080 12:44:12.487907 EX_ROW_EN[1] = 0x0
5081 12:44:12.487990 LP4Y_EN = 0x0
5082 12:44:12.491449 WORK_FSP = 0x0
5083 12:44:12.491532 WL = 0x3
5084 12:44:12.494378 RL = 0x3
5085 12:44:12.497790 BL = 0x2
5086 12:44:12.497873 RPST = 0x0
5087 12:44:12.501353 RD_PRE = 0x0
5088 12:44:12.501436 WR_PRE = 0x1
5089 12:44:12.504664 WR_PST = 0x0
5090 12:44:12.504747 DBI_WR = 0x0
5091 12:44:12.507474 DBI_RD = 0x0
5092 12:44:12.507556 OTF = 0x1
5093 12:44:12.510994 ===================================
5094 12:44:12.517419 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5095 12:44:12.521260 nWR fixed to 30
5096 12:44:12.524880 [ModeRegInit_LP4] CH0 RK0
5097 12:44:12.524963 [ModeRegInit_LP4] CH0 RK1
5098 12:44:12.527978 [ModeRegInit_LP4] CH1 RK0
5099 12:44:12.531178 [ModeRegInit_LP4] CH1 RK1
5100 12:44:12.531261 match AC timing 9
5101 12:44:12.537757 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5102 12:44:12.540977 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5103 12:44:12.544454 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5104 12:44:12.551016 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5105 12:44:12.554533 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5106 12:44:12.554611 ==
5107 12:44:12.557345 Dram Type= 6, Freq= 0, CH_0, rank 0
5108 12:44:12.561019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5109 12:44:12.561100 ==
5110 12:44:12.567331 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5111 12:44:12.574372 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5112 12:44:12.577768 [CA 0] Center 38 (8~69) winsize 62
5113 12:44:12.580661 [CA 1] Center 38 (8~69) winsize 62
5114 12:44:12.584095 [CA 2] Center 35 (5~65) winsize 61
5115 12:44:12.587595 [CA 3] Center 35 (5~65) winsize 61
5116 12:44:12.590844 [CA 4] Center 34 (4~64) winsize 61
5117 12:44:12.594115 [CA 5] Center 33 (3~64) winsize 62
5118 12:44:12.594198
5119 12:44:12.597648 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5120 12:44:12.597760
5121 12:44:12.600514 [CATrainingPosCal] consider 1 rank data
5122 12:44:12.604042 u2DelayCellTimex100 = 270/100 ps
5123 12:44:12.607389 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5124 12:44:12.610690 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5125 12:44:12.613676 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5126 12:44:12.617154 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5127 12:44:12.623984 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5128 12:44:12.627147 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5129 12:44:12.627243
5130 12:44:12.630322 CA PerBit enable=1, Macro0, CA PI delay=33
5131 12:44:12.630411
5132 12:44:12.633909 [CBTSetCACLKResult] CA Dly = 33
5133 12:44:12.633991 CS Dly: 7 (0~38)
5134 12:44:12.634056 ==
5135 12:44:12.636949 Dram Type= 6, Freq= 0, CH_0, rank 1
5136 12:44:12.643923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5137 12:44:12.644016 ==
5138 12:44:12.646734 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5139 12:44:12.653399 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5140 12:44:12.656745 [CA 0] Center 38 (8~69) winsize 62
5141 12:44:12.659907 [CA 1] Center 38 (8~69) winsize 62
5142 12:44:12.663243 [CA 2] Center 35 (5~66) winsize 62
5143 12:44:12.666608 [CA 3] Center 35 (5~66) winsize 62
5144 12:44:12.670066 [CA 4] Center 34 (4~65) winsize 62
5145 12:44:12.673525 [CA 5] Center 33 (3~64) winsize 62
5146 12:44:12.673607
5147 12:44:12.676358 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5148 12:44:12.676441
5149 12:44:12.679752 [CATrainingPosCal] consider 2 rank data
5150 12:44:12.683111 u2DelayCellTimex100 = 270/100 ps
5151 12:44:12.686578 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5152 12:44:12.692959 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5153 12:44:12.696361 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5154 12:44:12.699917 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5155 12:44:12.702819 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5156 12:44:12.706320 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5157 12:44:12.706405
5158 12:44:12.709848 CA PerBit enable=1, Macro0, CA PI delay=33
5159 12:44:12.709932
5160 12:44:12.713039 [CBTSetCACLKResult] CA Dly = 33
5161 12:44:12.716407 CS Dly: 7 (0~39)
5162 12:44:12.716492
5163 12:44:12.719376 ----->DramcWriteLeveling(PI) begin...
5164 12:44:12.719489 ==
5165 12:44:12.722923 Dram Type= 6, Freq= 0, CH_0, rank 0
5166 12:44:12.726335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5167 12:44:12.726455 ==
5168 12:44:12.729365 Write leveling (Byte 0): 35 => 35
5169 12:44:12.732762 Write leveling (Byte 1): 29 => 29
5170 12:44:12.736159 DramcWriteLeveling(PI) end<-----
5171 12:44:12.736309
5172 12:44:12.736409 ==
5173 12:44:12.739208 Dram Type= 6, Freq= 0, CH_0, rank 0
5174 12:44:12.742296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5175 12:44:12.742407 ==
5176 12:44:12.745897 [Gating] SW mode calibration
5177 12:44:12.752260 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5178 12:44:12.758980 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5179 12:44:12.762027 0 14 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5180 12:44:12.768635 0 14 4 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
5181 12:44:12.771863 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5182 12:44:12.775255 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5183 12:44:12.781999 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5184 12:44:12.785509 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5185 12:44:12.788361 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5186 12:44:12.795389 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5187 12:44:12.798368 0 15 0 | B1->B0 | 3333 2828 | 0 0 | (0 0) (0 0)
5188 12:44:12.801659 0 15 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5189 12:44:12.808060 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5190 12:44:12.811695 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5191 12:44:12.814510 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5192 12:44:12.821253 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5193 12:44:12.824810 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5194 12:44:12.827738 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5195 12:44:12.834602 1 0 0 | B1->B0 | 2e2e 3b3b | 0 0 | (0 0) (0 0)
5196 12:44:12.837591 1 0 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5197 12:44:12.841217 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 12:44:12.847587 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5199 12:44:12.850697 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5200 12:44:12.853931 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5201 12:44:12.860973 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5202 12:44:12.864089 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5203 12:44:12.867509 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5204 12:44:12.873873 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 12:44:12.877128 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 12:44:12.880401 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 12:44:12.887495 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 12:44:12.890311 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 12:44:12.893754 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 12:44:12.900175 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 12:44:12.903503 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 12:44:12.907062 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 12:44:12.913397 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 12:44:12.916876 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 12:44:12.920418 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 12:44:12.926601 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 12:44:12.930018 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 12:44:12.933524 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 12:44:12.940024 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5220 12:44:12.942983 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5221 12:44:12.946432 Total UI for P1: 0, mck2ui 16
5222 12:44:12.949877 best dqsien dly found for B0: ( 1, 3, 0)
5223 12:44:12.953172 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5224 12:44:12.956315 Total UI for P1: 0, mck2ui 16
5225 12:44:12.959453 best dqsien dly found for B1: ( 1, 3, 4)
5226 12:44:12.963168 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5227 12:44:12.966371 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5228 12:44:12.966463
5229 12:44:12.970122 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5230 12:44:12.976339 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5231 12:44:12.976455 [Gating] SW calibration Done
5232 12:44:12.976525 ==
5233 12:44:12.979445 Dram Type= 6, Freq= 0, CH_0, rank 0
5234 12:44:12.985757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5235 12:44:12.985878 ==
5236 12:44:12.985947 RX Vref Scan: 0
5237 12:44:12.986009
5238 12:44:12.989541 RX Vref 0 -> 0, step: 1
5239 12:44:12.989669
5240 12:44:12.992417 RX Delay -80 -> 252, step: 8
5241 12:44:12.995862 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5242 12:44:12.999476 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5243 12:44:13.002267 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5244 12:44:13.009111 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5245 12:44:13.012028 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5246 12:44:13.015602 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5247 12:44:13.019098 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5248 12:44:13.022048 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5249 12:44:13.025458 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5250 12:44:13.032214 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5251 12:44:13.035202 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5252 12:44:13.038869 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5253 12:44:13.042194 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5254 12:44:13.048747 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5255 12:44:13.051775 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5256 12:44:13.054997 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5257 12:44:13.055081 ==
5258 12:44:13.058204 Dram Type= 6, Freq= 0, CH_0, rank 0
5259 12:44:13.061715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5260 12:44:13.061802 ==
5261 12:44:13.065115 DQS Delay:
5262 12:44:13.065199 DQS0 = 0, DQS1 = 0
5263 12:44:13.068494 DQM Delay:
5264 12:44:13.068586 DQM0 = 94, DQM1 = 82
5265 12:44:13.068654 DQ Delay:
5266 12:44:13.072097 DQ0 =95, DQ1 =95, DQ2 =91, DQ3 =91
5267 12:44:13.075354 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5268 12:44:13.078136 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5269 12:44:13.081933 DQ12 =87, DQ13 =87, DQ14 =91, DQ15 =91
5270 12:44:13.082024
5271 12:44:13.082088
5272 12:44:13.085607 ==
5273 12:44:13.088258 Dram Type= 6, Freq= 0, CH_0, rank 0
5274 12:44:13.091392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5275 12:44:13.091518 ==
5276 12:44:13.091583
5277 12:44:13.091643
5278 12:44:13.094814 TX Vref Scan disable
5279 12:44:13.094935 == TX Byte 0 ==
5280 12:44:13.101203 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5281 12:44:13.104663 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5282 12:44:13.104751 == TX Byte 1 ==
5283 12:44:13.111079 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5284 12:44:13.114406 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5285 12:44:13.114494 ==
5286 12:44:13.117471 Dram Type= 6, Freq= 0, CH_0, rank 0
5287 12:44:13.120876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5288 12:44:13.120956 ==
5289 12:44:13.121024
5290 12:44:13.121088
5291 12:44:13.124339 TX Vref Scan disable
5292 12:44:13.127814 == TX Byte 0 ==
5293 12:44:13.130651 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5294 12:44:13.134459 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5295 12:44:13.137407 == TX Byte 1 ==
5296 12:44:13.140860 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5297 12:44:13.144345 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5298 12:44:13.144432
5299 12:44:13.147333 [DATLAT]
5300 12:44:13.147428 Freq=933, CH0 RK0
5301 12:44:13.147514
5302 12:44:13.150789 DATLAT Default: 0xd
5303 12:44:13.150919 0, 0xFFFF, sum = 0
5304 12:44:13.153719 1, 0xFFFF, sum = 0
5305 12:44:13.153807 2, 0xFFFF, sum = 0
5306 12:44:13.157344 3, 0xFFFF, sum = 0
5307 12:44:13.157431 4, 0xFFFF, sum = 0
5308 12:44:13.160608 5, 0xFFFF, sum = 0
5309 12:44:13.160695 6, 0xFFFF, sum = 0
5310 12:44:13.163816 7, 0xFFFF, sum = 0
5311 12:44:13.166788 8, 0xFFFF, sum = 0
5312 12:44:13.166920 9, 0xFFFF, sum = 0
5313 12:44:13.170284 10, 0x0, sum = 1
5314 12:44:13.170371 11, 0x0, sum = 2
5315 12:44:13.170457 12, 0x0, sum = 3
5316 12:44:13.173853 13, 0x0, sum = 4
5317 12:44:13.173941 best_step = 11
5318 12:44:13.174055
5319 12:44:13.177114 ==
5320 12:44:13.180095 Dram Type= 6, Freq= 0, CH_0, rank 0
5321 12:44:13.183639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5322 12:44:13.183727 ==
5323 12:44:13.183812 RX Vref Scan: 1
5324 12:44:13.183893
5325 12:44:13.186824 RX Vref 0 -> 0, step: 1
5326 12:44:13.186934
5327 12:44:13.190087 RX Delay -69 -> 252, step: 4
5328 12:44:13.190172
5329 12:44:13.193222 Set Vref, RX VrefLevel [Byte0]: 61
5330 12:44:13.196612 [Byte1]: 48
5331 12:44:13.196699
5332 12:44:13.200283 Final RX Vref Byte 0 = 61 to rank0
5333 12:44:13.203914 Final RX Vref Byte 1 = 48 to rank0
5334 12:44:13.206714 Final RX Vref Byte 0 = 61 to rank1
5335 12:44:13.209774 Final RX Vref Byte 1 = 48 to rank1==
5336 12:44:13.212975 Dram Type= 6, Freq= 0, CH_0, rank 0
5337 12:44:13.216373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5338 12:44:13.219887 ==
5339 12:44:13.219978 DQS Delay:
5340 12:44:13.220066 DQS0 = 0, DQS1 = 0
5341 12:44:13.222863 DQM Delay:
5342 12:44:13.222981 DQM0 = 95, DQM1 = 83
5343 12:44:13.226235 DQ Delay:
5344 12:44:13.229770 DQ0 =94, DQ1 =94, DQ2 =92, DQ3 =94
5345 12:44:13.232628 DQ4 =94, DQ5 =84, DQ6 =104, DQ7 =106
5346 12:44:13.235966 DQ8 =74, DQ9 =70, DQ10 =84, DQ11 =78
5347 12:44:13.239738 DQ12 =86, DQ13 =88, DQ14 =96, DQ15 =88
5348 12:44:13.239824
5349 12:44:13.239905
5350 12:44:13.246119 [DQSOSCAuto] RK0, (LSB)MR18= 0x1211, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 416 ps
5351 12:44:13.249348 CH0 RK0: MR19=505, MR18=1211
5352 12:44:13.256030 CH0_RK0: MR19=0x505, MR18=0x1211, DQSOSC=416, MR23=63, INC=62, DEC=41
5353 12:44:13.256146
5354 12:44:13.259007 ----->DramcWriteLeveling(PI) begin...
5355 12:44:13.259093 ==
5356 12:44:13.262296 Dram Type= 6, Freq= 0, CH_0, rank 1
5357 12:44:13.265766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5358 12:44:13.265850 ==
5359 12:44:13.269119 Write leveling (Byte 0): 31 => 31
5360 12:44:13.272186 Write leveling (Byte 1): 29 => 29
5361 12:44:13.275605 DramcWriteLeveling(PI) end<-----
5362 12:44:13.275688
5363 12:44:13.275752 ==
5364 12:44:13.279151 Dram Type= 6, Freq= 0, CH_0, rank 1
5365 12:44:13.282400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5366 12:44:13.285623 ==
5367 12:44:13.285706 [Gating] SW mode calibration
5368 12:44:13.295242 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5369 12:44:13.299088 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5370 12:44:13.302216 0 14 0 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
5371 12:44:13.308888 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5372 12:44:13.312194 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5373 12:44:13.315474 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5374 12:44:13.322220 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5375 12:44:13.325410 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5376 12:44:13.328340 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5377 12:44:13.335304 0 14 28 | B1->B0 | 3131 2f2f | 0 0 | (0 0) (0 0)
5378 12:44:13.338221 0 15 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
5379 12:44:13.341875 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5380 12:44:13.348333 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5381 12:44:13.351964 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5382 12:44:13.354724 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5383 12:44:13.361630 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5384 12:44:13.365026 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5385 12:44:13.367948 0 15 28 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5386 12:44:13.374637 1 0 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5387 12:44:13.378070 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 12:44:13.381551 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5389 12:44:13.387804 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5390 12:44:13.391373 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5391 12:44:13.394251 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5392 12:44:13.401030 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5393 12:44:13.404330 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5394 12:44:13.407634 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5395 12:44:13.413928 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5396 12:44:13.417337 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 12:44:13.420814 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 12:44:13.427250 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 12:44:13.430338 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 12:44:13.433923 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 12:44:13.440415 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 12:44:13.443772 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 12:44:13.446819 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 12:44:13.453758 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 12:44:13.456685 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 12:44:13.460156 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 12:44:13.466651 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 12:44:13.470013 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 12:44:13.473545 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 12:44:13.479768 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5411 12:44:13.483265 Total UI for P1: 0, mck2ui 16
5412 12:44:13.486263 best dqsien dly found for B0: ( 1, 2, 30)
5413 12:44:13.489639 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5414 12:44:13.492933 Total UI for P1: 0, mck2ui 16
5415 12:44:13.496401 best dqsien dly found for B1: ( 1, 3, 0)
5416 12:44:13.499889 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5417 12:44:13.503165 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5418 12:44:13.503251
5419 12:44:13.506337 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5420 12:44:13.509836 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5421 12:44:13.512977 [Gating] SW calibration Done
5422 12:44:13.513063 ==
5423 12:44:13.516185 Dram Type= 6, Freq= 0, CH_0, rank 1
5424 12:44:13.522818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5425 12:44:13.522915 ==
5426 12:44:13.522982 RX Vref Scan: 0
5427 12:44:13.523044
5428 12:44:13.526090 RX Vref 0 -> 0, step: 1
5429 12:44:13.526174
5430 12:44:13.528973 RX Delay -80 -> 252, step: 8
5431 12:44:13.532389 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5432 12:44:13.535668 iDelay=208, Bit 1, Center 95 (-8 ~ 199) 208
5433 12:44:13.539078 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5434 12:44:13.545634 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5435 12:44:13.549056 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5436 12:44:13.552306 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5437 12:44:13.555579 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5438 12:44:13.558593 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5439 12:44:13.562109 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5440 12:44:13.568617 iDelay=208, Bit 9, Center 67 (-24 ~ 159) 184
5441 12:44:13.571908 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5442 12:44:13.575379 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5443 12:44:13.578731 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5444 12:44:13.585063 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5445 12:44:13.588529 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5446 12:44:13.591453 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5447 12:44:13.591561 ==
5448 12:44:13.594893 Dram Type= 6, Freq= 0, CH_0, rank 1
5449 12:44:13.598453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5450 12:44:13.598550 ==
5451 12:44:13.602039 DQS Delay:
5452 12:44:13.602182 DQS0 = 0, DQS1 = 0
5453 12:44:13.604656 DQM Delay:
5454 12:44:13.604773 DQM0 = 92, DQM1 = 83
5455 12:44:13.604865 DQ Delay:
5456 12:44:13.607827 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =87
5457 12:44:13.611465 DQ4 =91, DQ5 =79, DQ6 =103, DQ7 =103
5458 12:44:13.614338 DQ8 =75, DQ9 =67, DQ10 =87, DQ11 =79
5459 12:44:13.617720 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =87
5460 12:44:13.617857
5461 12:44:13.617977
5462 12:44:13.621386 ==
5463 12:44:13.624472 Dram Type= 6, Freq= 0, CH_0, rank 1
5464 12:44:13.627789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5465 12:44:13.627873 ==
5466 12:44:13.627939
5467 12:44:13.627999
5468 12:44:13.630929 TX Vref Scan disable
5469 12:44:13.631012 == TX Byte 0 ==
5470 12:44:13.637680 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5471 12:44:13.641022 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5472 12:44:13.641137 == TX Byte 1 ==
5473 12:44:13.647267 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5474 12:44:13.650615 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5475 12:44:13.650699 ==
5476 12:44:13.653938 Dram Type= 6, Freq= 0, CH_0, rank 1
5477 12:44:13.657336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5478 12:44:13.657419 ==
5479 12:44:13.657485
5480 12:44:13.657546
5481 12:44:13.660822 TX Vref Scan disable
5482 12:44:13.663910 == TX Byte 0 ==
5483 12:44:13.667380 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5484 12:44:13.670238 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5485 12:44:13.673811 == TX Byte 1 ==
5486 12:44:13.677299 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5487 12:44:13.680330 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5488 12:44:13.680419
5489 12:44:13.683957 [DATLAT]
5490 12:44:13.684046 Freq=933, CH0 RK1
5491 12:44:13.684112
5492 12:44:13.686777 DATLAT Default: 0xb
5493 12:44:13.686941 0, 0xFFFF, sum = 0
5494 12:44:13.690341 1, 0xFFFF, sum = 0
5495 12:44:13.690484 2, 0xFFFF, sum = 0
5496 12:44:13.693892 3, 0xFFFF, sum = 0
5497 12:44:13.693995 4, 0xFFFF, sum = 0
5498 12:44:13.696900 5, 0xFFFF, sum = 0
5499 12:44:13.696984 6, 0xFFFF, sum = 0
5500 12:44:13.700195 7, 0xFFFF, sum = 0
5501 12:44:13.703663 8, 0xFFFF, sum = 0
5502 12:44:13.703747 9, 0xFFFF, sum = 0
5503 12:44:13.706604 10, 0x0, sum = 1
5504 12:44:13.706739 11, 0x0, sum = 2
5505 12:44:13.706887 12, 0x0, sum = 3
5506 12:44:13.710004 13, 0x0, sum = 4
5507 12:44:13.710111 best_step = 11
5508 12:44:13.710206
5509 12:44:13.713331 ==
5510 12:44:13.713412 Dram Type= 6, Freq= 0, CH_0, rank 1
5511 12:44:13.719846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5512 12:44:13.719930 ==
5513 12:44:13.719997 RX Vref Scan: 0
5514 12:44:13.720058
5515 12:44:13.723137 RX Vref 0 -> 0, step: 1
5516 12:44:13.723220
5517 12:44:13.726278 RX Delay -69 -> 252, step: 4
5518 12:44:13.729923 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5519 12:44:13.736462 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5520 12:44:13.739837 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5521 12:44:13.743162 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5522 12:44:13.746385 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5523 12:44:13.749989 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5524 12:44:13.756222 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5525 12:44:13.759907 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5526 12:44:13.762802 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5527 12:44:13.766200 iDelay=199, Bit 9, Center 68 (-17 ~ 154) 172
5528 12:44:13.769100 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5529 12:44:13.776184 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5530 12:44:13.779053 iDelay=199, Bit 12, Center 88 (-5 ~ 182) 188
5531 12:44:13.782529 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5532 12:44:13.786050 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5533 12:44:13.788783 iDelay=199, Bit 15, Center 90 (-1 ~ 182) 184
5534 12:44:13.788888 ==
5535 12:44:13.792244 Dram Type= 6, Freq= 0, CH_0, rank 1
5536 12:44:13.798737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5537 12:44:13.798823 ==
5538 12:44:13.798929 DQS Delay:
5539 12:44:13.802120 DQS0 = 0, DQS1 = 0
5540 12:44:13.802203 DQM Delay:
5541 12:44:13.805454 DQM0 = 92, DQM1 = 83
5542 12:44:13.805539 DQ Delay:
5543 12:44:13.808976 DQ0 =90, DQ1 =94, DQ2 =88, DQ3 =88
5544 12:44:13.812042 DQ4 =90, DQ5 =80, DQ6 =104, DQ7 =104
5545 12:44:13.815341 DQ8 =76, DQ9 =68, DQ10 =86, DQ11 =76
5546 12:44:13.818731 DQ12 =88, DQ13 =90, DQ14 =96, DQ15 =90
5547 12:44:13.818823
5548 12:44:13.818934
5549 12:44:13.825358 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c0e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 408 ps
5550 12:44:13.828601 CH0 RK1: MR19=505, MR18=2C0E
5551 12:44:13.835182 CH0_RK1: MR19=0x505, MR18=0x2C0E, DQSOSC=408, MR23=63, INC=65, DEC=43
5552 12:44:13.838436 [RxdqsGatingPostProcess] freq 933
5553 12:44:13.845434 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5554 12:44:13.848599 best DQS0 dly(2T, 0.5T) = (0, 11)
5555 12:44:13.848710 best DQS1 dly(2T, 0.5T) = (0, 11)
5556 12:44:13.851854 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5557 12:44:13.855256 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5558 12:44:13.858321 best DQS0 dly(2T, 0.5T) = (0, 10)
5559 12:44:13.861862 best DQS1 dly(2T, 0.5T) = (0, 11)
5560 12:44:13.864777 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5561 12:44:13.868132 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5562 12:44:13.871288 Pre-setting of DQS Precalculation
5563 12:44:13.878059 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5564 12:44:13.878175 ==
5565 12:44:13.881642 Dram Type= 6, Freq= 0, CH_1, rank 0
5566 12:44:13.884709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5567 12:44:13.884784 ==
5568 12:44:13.891192 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5569 12:44:13.897635 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5570 12:44:13.901327 [CA 0] Center 38 (8~68) winsize 61
5571 12:44:13.904502 [CA 1] Center 38 (8~69) winsize 62
5572 12:44:13.907366 [CA 2] Center 35 (6~65) winsize 60
5573 12:44:13.910748 [CA 3] Center 35 (5~65) winsize 61
5574 12:44:13.914250 [CA 4] Center 36 (6~66) winsize 61
5575 12:44:13.917652 [CA 5] Center 34 (5~64) winsize 60
5576 12:44:13.917767
5577 12:44:13.920947 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5578 12:44:13.921052
5579 12:44:13.923968 [CATrainingPosCal] consider 1 rank data
5580 12:44:13.927586 u2DelayCellTimex100 = 270/100 ps
5581 12:44:13.930441 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5582 12:44:13.934004 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5583 12:44:13.937138 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5584 12:44:13.940395 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5585 12:44:13.943804 CA4 delay=36 (6~66),Diff = 2 PI (12 cell)
5586 12:44:13.947053 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5587 12:44:13.947136
5588 12:44:13.953983 CA PerBit enable=1, Macro0, CA PI delay=34
5589 12:44:13.954068
5590 12:44:13.957195 [CBTSetCACLKResult] CA Dly = 34
5591 12:44:13.957280 CS Dly: 7 (0~38)
5592 12:44:13.957347 ==
5593 12:44:13.960272 Dram Type= 6, Freq= 0, CH_1, rank 1
5594 12:44:13.963419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5595 12:44:13.963496 ==
5596 12:44:13.970372 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5597 12:44:13.976456 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5598 12:44:13.980249 [CA 0] Center 38 (8~69) winsize 62
5599 12:44:13.983530 [CA 1] Center 38 (8~69) winsize 62
5600 12:44:13.986394 [CA 2] Center 36 (6~66) winsize 61
5601 12:44:13.989869 [CA 3] Center 35 (5~65) winsize 61
5602 12:44:13.993303 [CA 4] Center 35 (5~65) winsize 61
5603 12:44:13.996669 [CA 5] Center 34 (4~65) winsize 62
5604 12:44:13.996741
5605 12:44:13.999526 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5606 12:44:13.999607
5607 12:44:14.003167 [CATrainingPosCal] consider 2 rank data
5608 12:44:14.006174 u2DelayCellTimex100 = 270/100 ps
5609 12:44:14.009514 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5610 12:44:14.012911 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5611 12:44:14.016245 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5612 12:44:14.022602 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5613 12:44:14.025943 CA4 delay=35 (6~65),Diff = 1 PI (6 cell)
5614 12:44:14.029479 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5615 12:44:14.029552
5616 12:44:14.032501 CA PerBit enable=1, Macro0, CA PI delay=34
5617 12:44:14.032577
5618 12:44:14.035830 [CBTSetCACLKResult] CA Dly = 34
5619 12:44:14.035899 CS Dly: 7 (0~39)
5620 12:44:14.035995
5621 12:44:14.039306 ----->DramcWriteLeveling(PI) begin...
5622 12:44:14.039375 ==
5623 12:44:14.043003 Dram Type= 6, Freq= 0, CH_1, rank 0
5624 12:44:14.049173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5625 12:44:14.049246 ==
5626 12:44:14.052580 Write leveling (Byte 0): 27 => 27
5627 12:44:14.055318 Write leveling (Byte 1): 28 => 28
5628 12:44:14.058653 DramcWriteLeveling(PI) end<-----
5629 12:44:14.058728
5630 12:44:14.058789 ==
5631 12:44:14.061855 Dram Type= 6, Freq= 0, CH_1, rank 0
5632 12:44:14.065674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5633 12:44:14.065750 ==
5634 12:44:14.068855 [Gating] SW mode calibration
5635 12:44:14.075618 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5636 12:44:14.081696 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5637 12:44:14.085135 0 14 0 | B1->B0 | 2f2e 3030 | 1 0 | (0 0) (0 0)
5638 12:44:14.088388 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5639 12:44:14.094838 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5640 12:44:14.098251 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5641 12:44:14.101807 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5642 12:44:14.108466 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5643 12:44:14.111763 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5644 12:44:14.114619 0 14 28 | B1->B0 | 2f2f 2f2f | 1 0 | (0 0) (0 0)
5645 12:44:14.121304 0 15 0 | B1->B0 | 2d2d 2e2e | 1 1 | (1 0) (1 0)
5646 12:44:14.124776 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5647 12:44:14.127745 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5648 12:44:14.134246 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5649 12:44:14.137636 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5650 12:44:14.141092 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5651 12:44:14.147672 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5652 12:44:14.150956 0 15 28 | B1->B0 | 2f2f 2e2e | 0 0 | (0 0) (0 0)
5653 12:44:14.154301 1 0 0 | B1->B0 | 4242 4141 | 0 0 | (0 0) (0 0)
5654 12:44:14.160379 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5655 12:44:14.163929 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5656 12:44:14.167209 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5657 12:44:14.173537 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5658 12:44:14.176991 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5659 12:44:14.180228 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5660 12:44:14.186843 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5661 12:44:14.190302 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5662 12:44:14.193632 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 12:44:14.200150 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 12:44:14.203350 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 12:44:14.206384 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 12:44:14.213039 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 12:44:14.216699 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 12:44:14.219988 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 12:44:14.226160 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 12:44:14.229444 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 12:44:14.232780 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 12:44:14.239366 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 12:44:14.242956 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 12:44:14.245964 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 12:44:14.252300 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5676 12:44:14.255823 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5677 12:44:14.259290 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5678 12:44:14.265673 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5679 12:44:14.269109 Total UI for P1: 0, mck2ui 16
5680 12:44:14.271982 best dqsien dly found for B0: ( 1, 2, 30)
5681 12:44:14.275348 Total UI for P1: 0, mck2ui 16
5682 12:44:14.278560 best dqsien dly found for B1: ( 1, 2, 28)
5683 12:44:14.281828 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5684 12:44:14.285575 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5685 12:44:14.285648
5686 12:44:14.288748 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5687 12:44:14.291934 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5688 12:44:14.295155 [Gating] SW calibration Done
5689 12:44:14.295237 ==
5690 12:44:14.298614 Dram Type= 6, Freq= 0, CH_1, rank 0
5691 12:44:14.301928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5692 12:44:14.302013 ==
5693 12:44:14.305376 RX Vref Scan: 0
5694 12:44:14.305448
5695 12:44:14.308241 RX Vref 0 -> 0, step: 1
5696 12:44:14.308312
5697 12:44:14.308374 RX Delay -80 -> 252, step: 8
5698 12:44:14.315195 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5699 12:44:14.318708 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5700 12:44:14.321629 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5701 12:44:14.325028 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5702 12:44:14.328449 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5703 12:44:14.334772 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5704 12:44:14.338224 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5705 12:44:14.341253 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5706 12:44:14.344705 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5707 12:44:14.348284 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5708 12:44:14.354667 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5709 12:44:14.358018 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5710 12:44:14.361382 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5711 12:44:14.364744 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5712 12:44:14.367864 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5713 12:44:14.371055 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5714 12:44:14.374553 ==
5715 12:44:14.377466 Dram Type= 6, Freq= 0, CH_1, rank 0
5716 12:44:14.380698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 12:44:14.380767 ==
5718 12:44:14.380828 DQS Delay:
5719 12:44:14.384511 DQS0 = 0, DQS1 = 0
5720 12:44:14.384576 DQM Delay:
5721 12:44:14.387429 DQM0 = 97, DQM1 = 89
5722 12:44:14.387495 DQ Delay:
5723 12:44:14.390793 DQ0 =103, DQ1 =91, DQ2 =83, DQ3 =95
5724 12:44:14.394118 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =95
5725 12:44:14.397716 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5726 12:44:14.400757 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =91
5727 12:44:14.400838
5728 12:44:14.400906
5729 12:44:14.400968 ==
5730 12:44:14.404201 Dram Type= 6, Freq= 0, CH_1, rank 0
5731 12:44:14.407551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 12:44:14.407624 ==
5733 12:44:14.407686
5734 12:44:14.410945
5735 12:44:14.411022 TX Vref Scan disable
5736 12:44:14.414439 == TX Byte 0 ==
5737 12:44:14.417691 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5738 12:44:14.420590 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5739 12:44:14.424083 == TX Byte 1 ==
5740 12:44:14.427527 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5741 12:44:14.430913 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5742 12:44:14.430984 ==
5743 12:44:14.433783 Dram Type= 6, Freq= 0, CH_1, rank 0
5744 12:44:14.440597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5745 12:44:14.440683 ==
5746 12:44:14.440745
5747 12:44:14.440803
5748 12:44:14.440860 TX Vref Scan disable
5749 12:44:14.444743 == TX Byte 0 ==
5750 12:44:14.448161 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5751 12:44:14.454605 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5752 12:44:14.454675 == TX Byte 1 ==
5753 12:44:14.457440 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5754 12:44:14.464489 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5755 12:44:14.464560
5756 12:44:14.464624 [DATLAT]
5757 12:44:14.464698 Freq=933, CH1 RK0
5758 12:44:14.464757
5759 12:44:14.467446 DATLAT Default: 0xd
5760 12:44:14.470750 0, 0xFFFF, sum = 0
5761 12:44:14.470824 1, 0xFFFF, sum = 0
5762 12:44:14.474028 2, 0xFFFF, sum = 0
5763 12:44:14.474104 3, 0xFFFF, sum = 0
5764 12:44:14.477459 4, 0xFFFF, sum = 0
5765 12:44:14.477537 5, 0xFFFF, sum = 0
5766 12:44:14.480778 6, 0xFFFF, sum = 0
5767 12:44:14.480863 7, 0xFFFF, sum = 0
5768 12:44:14.484149 8, 0xFFFF, sum = 0
5769 12:44:14.484220 9, 0xFFFF, sum = 0
5770 12:44:14.487337 10, 0x0, sum = 1
5771 12:44:14.487403 11, 0x0, sum = 2
5772 12:44:14.490721 12, 0x0, sum = 3
5773 12:44:14.490803 13, 0x0, sum = 4
5774 12:44:14.493768 best_step = 11
5775 12:44:14.493850
5776 12:44:14.493923 ==
5777 12:44:14.497184 Dram Type= 6, Freq= 0, CH_1, rank 0
5778 12:44:14.500412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5779 12:44:14.500497 ==
5780 12:44:14.500563 RX Vref Scan: 1
5781 12:44:14.503641
5782 12:44:14.503710 RX Vref 0 -> 0, step: 1
5783 12:44:14.503770
5784 12:44:14.507020 RX Delay -61 -> 252, step: 4
5785 12:44:14.507092
5786 12:44:14.510305 Set Vref, RX VrefLevel [Byte0]: 57
5787 12:44:14.513556 [Byte1]: 55
5788 12:44:14.517234
5789 12:44:14.517322 Final RX Vref Byte 0 = 57 to rank0
5790 12:44:14.520370 Final RX Vref Byte 1 = 55 to rank0
5791 12:44:14.523518 Final RX Vref Byte 0 = 57 to rank1
5792 12:44:14.526993 Final RX Vref Byte 1 = 55 to rank1==
5793 12:44:14.530544 Dram Type= 6, Freq= 0, CH_1, rank 0
5794 12:44:14.536742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5795 12:44:14.536846 ==
5796 12:44:14.536909 DQS Delay:
5797 12:44:14.540250 DQS0 = 0, DQS1 = 0
5798 12:44:14.540315 DQM Delay:
5799 12:44:14.540374 DQM0 = 99, DQM1 = 92
5800 12:44:14.543156 DQ Delay:
5801 12:44:14.546558 DQ0 =104, DQ1 =94, DQ2 =88, DQ3 =96
5802 12:44:14.550175 DQ4 =96, DQ5 =108, DQ6 =112, DQ7 =94
5803 12:44:14.553526 DQ8 =82, DQ9 =84, DQ10 =90, DQ11 =86
5804 12:44:14.556958 DQ12 =100, DQ13 =98, DQ14 =98, DQ15 =98
5805 12:44:14.557026
5806 12:44:14.557086
5807 12:44:14.563350 [DQSOSCAuto] RK0, (LSB)MR18= 0x20a, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 421 ps
5808 12:44:14.566816 CH1 RK0: MR19=505, MR18=20A
5809 12:44:14.573481 CH1_RK0: MR19=0x505, MR18=0x20A, DQSOSC=418, MR23=63, INC=62, DEC=41
5810 12:44:14.573559
5811 12:44:14.576290 ----->DramcWriteLeveling(PI) begin...
5812 12:44:14.576364 ==
5813 12:44:14.579700 Dram Type= 6, Freq= 0, CH_1, rank 1
5814 12:44:14.583152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5815 12:44:14.583235 ==
5816 12:44:14.585940 Write leveling (Byte 0): 23 => 23
5817 12:44:14.589263 Write leveling (Byte 1): 25 => 25
5818 12:44:14.593090 DramcWriteLeveling(PI) end<-----
5819 12:44:14.593163
5820 12:44:14.593224 ==
5821 12:44:14.596060 Dram Type= 6, Freq= 0, CH_1, rank 1
5822 12:44:14.602448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5823 12:44:14.602528 ==
5824 12:44:14.602593 [Gating] SW mode calibration
5825 12:44:14.612740 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5826 12:44:14.615979 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5827 12:44:14.619359 0 14 0 | B1->B0 | 2e2e 3434 | 0 1 | (1 1) (1 1)
5828 12:44:14.625733 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5829 12:44:14.629254 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5830 12:44:14.632489 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5831 12:44:14.638795 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5832 12:44:14.642172 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5833 12:44:14.645714 0 14 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
5834 12:44:14.651987 0 14 28 | B1->B0 | 2f2f 2424 | 1 0 | (1 0) (0 0)
5835 12:44:14.655440 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5836 12:44:14.658978 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5837 12:44:14.665331 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5838 12:44:14.668848 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5839 12:44:14.671959 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5840 12:44:14.678723 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5841 12:44:14.681581 0 15 24 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (0 0)
5842 12:44:14.684939 0 15 28 | B1->B0 | 3030 4040 | 0 0 | (0 0) (0 0)
5843 12:44:14.691562 1 0 0 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
5844 12:44:14.695249 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5845 12:44:14.698206 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5846 12:44:14.704718 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5847 12:44:14.708085 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5848 12:44:14.711267 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5849 12:44:14.717826 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5850 12:44:14.721188 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5851 12:44:14.724385 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 12:44:14.730932 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 12:44:14.734237 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 12:44:14.740652 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 12:44:14.744686 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 12:44:14.747392 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 12:44:14.754226 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 12:44:14.757279 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 12:44:14.760678 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 12:44:14.767090 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 12:44:14.770529 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 12:44:14.774218 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 12:44:14.780489 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 12:44:14.783400 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 12:44:14.786835 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5866 12:44:14.793628 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5867 12:44:14.793730 Total UI for P1: 0, mck2ui 16
5868 12:44:14.800041 best dqsien dly found for B0: ( 1, 2, 24)
5869 12:44:14.803394 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5870 12:44:14.806507 Total UI for P1: 0, mck2ui 16
5871 12:44:14.809874 best dqsien dly found for B1: ( 1, 2, 30)
5872 12:44:14.813273 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5873 12:44:14.816656 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5874 12:44:14.816729
5875 12:44:14.819661 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5876 12:44:14.823098 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5877 12:44:14.826617 [Gating] SW calibration Done
5878 12:44:14.826715 ==
5879 12:44:14.829567 Dram Type= 6, Freq= 0, CH_1, rank 1
5880 12:44:14.832725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5881 12:44:14.836321 ==
5882 12:44:14.836394 RX Vref Scan: 0
5883 12:44:14.836456
5884 12:44:14.839721 RX Vref 0 -> 0, step: 1
5885 12:44:14.839796
5886 12:44:14.842987 RX Delay -80 -> 252, step: 8
5887 12:44:14.846220 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5888 12:44:14.849422 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5889 12:44:14.852554 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5890 12:44:14.855886 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5891 12:44:14.859182 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5892 12:44:14.865970 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5893 12:44:14.869103 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5894 12:44:14.872411 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5895 12:44:14.875879 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5896 12:44:14.878877 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5897 12:44:14.885931 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5898 12:44:14.888802 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5899 12:44:14.892417 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5900 12:44:14.895845 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5901 12:44:14.898786 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5902 12:44:14.905816 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5903 12:44:14.905920 ==
5904 12:44:14.908890 Dram Type= 6, Freq= 0, CH_1, rank 1
5905 12:44:14.912066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5906 12:44:14.912145 ==
5907 12:44:14.912208 DQS Delay:
5908 12:44:14.915629 DQS0 = 0, DQS1 = 0
5909 12:44:14.915705 DQM Delay:
5910 12:44:14.918623 DQM0 = 95, DQM1 = 92
5911 12:44:14.918724 DQ Delay:
5912 12:44:14.922084 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5913 12:44:14.925012 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5914 12:44:14.928750 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =87
5915 12:44:14.931633 DQ12 =103, DQ13 =99, DQ14 =95, DQ15 =95
5916 12:44:14.931735
5917 12:44:14.931825
5918 12:44:14.931911 ==
5919 12:44:14.934944 Dram Type= 6, Freq= 0, CH_1, rank 1
5920 12:44:14.938327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5921 12:44:14.942044 ==
5922 12:44:14.942120
5923 12:44:14.942183
5924 12:44:14.942241 TX Vref Scan disable
5925 12:44:14.945095 == TX Byte 0 ==
5926 12:44:14.948160 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5927 12:44:14.951602 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5928 12:44:14.954820 == TX Byte 1 ==
5929 12:44:14.958109 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5930 12:44:14.961760 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5931 12:44:14.964823 ==
5932 12:44:14.968003 Dram Type= 6, Freq= 0, CH_1, rank 1
5933 12:44:14.971368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5934 12:44:14.971469 ==
5935 12:44:14.971559
5936 12:44:14.971648
5937 12:44:14.974728 TX Vref Scan disable
5938 12:44:14.974826 == TX Byte 0 ==
5939 12:44:14.981063 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5940 12:44:14.984689 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5941 12:44:14.984765 == TX Byte 1 ==
5942 12:44:14.991177 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5943 12:44:14.994731 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5944 12:44:14.994868
5945 12:44:14.994959 [DATLAT]
5946 12:44:14.997435 Freq=933, CH1 RK1
5947 12:44:14.997537
5948 12:44:14.997622 DATLAT Default: 0xb
5949 12:44:15.000937 0, 0xFFFF, sum = 0
5950 12:44:15.001023 1, 0xFFFF, sum = 0
5951 12:44:15.003920 2, 0xFFFF, sum = 0
5952 12:44:15.007382 3, 0xFFFF, sum = 0
5953 12:44:15.007468 4, 0xFFFF, sum = 0
5954 12:44:15.010966 5, 0xFFFF, sum = 0
5955 12:44:15.011055 6, 0xFFFF, sum = 0
5956 12:44:15.013779 7, 0xFFFF, sum = 0
5957 12:44:15.013864 8, 0xFFFF, sum = 0
5958 12:44:15.017151 9, 0xFFFF, sum = 0
5959 12:44:15.017237 10, 0x0, sum = 1
5960 12:44:15.020330 11, 0x0, sum = 2
5961 12:44:15.020415 12, 0x0, sum = 3
5962 12:44:15.023753 13, 0x0, sum = 4
5963 12:44:15.023839 best_step = 11
5964 12:44:15.023923
5965 12:44:15.024004 ==
5966 12:44:15.027225 Dram Type= 6, Freq= 0, CH_1, rank 1
5967 12:44:15.030329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5968 12:44:15.030413 ==
5969 12:44:15.033845 RX Vref Scan: 0
5970 12:44:15.033930
5971 12:44:15.037266 RX Vref 0 -> 0, step: 1
5972 12:44:15.037351
5973 12:44:15.037484 RX Delay -61 -> 252, step: 4
5974 12:44:15.045576 iDelay=203, Bit 0, Center 100 (7 ~ 194) 188
5975 12:44:15.048341 iDelay=203, Bit 1, Center 88 (-5 ~ 182) 188
5976 12:44:15.051679 iDelay=203, Bit 2, Center 84 (-9 ~ 178) 188
5977 12:44:15.055049 iDelay=203, Bit 3, Center 90 (-5 ~ 186) 192
5978 12:44:15.058271 iDelay=203, Bit 4, Center 92 (-1 ~ 186) 188
5979 12:44:15.065322 iDelay=203, Bit 5, Center 104 (11 ~ 198) 188
5980 12:44:15.068470 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5981 12:44:15.071825 iDelay=203, Bit 7, Center 92 (-1 ~ 186) 188
5982 12:44:15.074916 iDelay=203, Bit 8, Center 82 (-9 ~ 174) 184
5983 12:44:15.078144 iDelay=203, Bit 9, Center 84 (-5 ~ 174) 180
5984 12:44:15.081624 iDelay=203, Bit 10, Center 96 (3 ~ 190) 188
5985 12:44:15.088109 iDelay=203, Bit 11, Center 86 (-5 ~ 178) 184
5986 12:44:15.090966 iDelay=203, Bit 12, Center 102 (11 ~ 194) 184
5987 12:44:15.094473 iDelay=203, Bit 13, Center 100 (11 ~ 190) 180
5988 12:44:15.097897 iDelay=203, Bit 14, Center 100 (11 ~ 190) 180
5989 12:44:15.104301 iDelay=203, Bit 15, Center 100 (11 ~ 190) 180
5990 12:44:15.104382 ==
5991 12:44:15.107752 Dram Type= 6, Freq= 0, CH_1, rank 1
5992 12:44:15.111360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5993 12:44:15.111447 ==
5994 12:44:15.111547 DQS Delay:
5995 12:44:15.114123 DQS0 = 0, DQS1 = 0
5996 12:44:15.114201 DQM Delay:
5997 12:44:15.117707 DQM0 = 94, DQM1 = 93
5998 12:44:15.117790 DQ Delay:
5999 12:44:15.120939 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =90
6000 12:44:15.124127 DQ4 =92, DQ5 =104, DQ6 =106, DQ7 =92
6001 12:44:15.127759 DQ8 =82, DQ9 =84, DQ10 =96, DQ11 =86
6002 12:44:15.131187 DQ12 =102, DQ13 =100, DQ14 =100, DQ15 =100
6003 12:44:15.131269
6004 12:44:15.131335
6005 12:44:15.140849 [DQSOSCAuto] RK1, (LSB)MR18= 0xb1f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 418 ps
6006 12:44:15.140933 CH1 RK1: MR19=505, MR18=B1F
6007 12:44:15.147659 CH1_RK1: MR19=0x505, MR18=0xB1F, DQSOSC=412, MR23=63, INC=63, DEC=42
6008 12:44:15.150665 [RxdqsGatingPostProcess] freq 933
6009 12:44:15.157231 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6010 12:44:15.160546 best DQS0 dly(2T, 0.5T) = (0, 10)
6011 12:44:15.163854 best DQS1 dly(2T, 0.5T) = (0, 10)
6012 12:44:15.167332 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6013 12:44:15.170762 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6014 12:44:15.173928 best DQS0 dly(2T, 0.5T) = (0, 10)
6015 12:44:15.174011 best DQS1 dly(2T, 0.5T) = (0, 10)
6016 12:44:15.177249 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6017 12:44:15.180574 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6018 12:44:15.183805 Pre-setting of DQS Precalculation
6019 12:44:15.190383 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6020 12:44:15.196930 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6021 12:44:15.203435 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6022 12:44:15.203519
6023 12:44:15.203644
6024 12:44:15.206928 [Calibration Summary] 1866 Mbps
6025 12:44:15.210331 CH 0, Rank 0
6026 12:44:15.210414 SW Impedance : PASS
6027 12:44:15.213334 DUTY Scan : NO K
6028 12:44:15.216781 ZQ Calibration : PASS
6029 12:44:15.216894 Jitter Meter : NO K
6030 12:44:15.220224 CBT Training : PASS
6031 12:44:15.220307 Write leveling : PASS
6032 12:44:15.223211 RX DQS gating : PASS
6033 12:44:15.226590 RX DQ/DQS(RDDQC) : PASS
6034 12:44:15.226691 TX DQ/DQS : PASS
6035 12:44:15.230301 RX DATLAT : PASS
6036 12:44:15.233427 RX DQ/DQS(Engine): PASS
6037 12:44:15.233510 TX OE : NO K
6038 12:44:15.236282 All Pass.
6039 12:44:15.236365
6040 12:44:15.236431 CH 0, Rank 1
6041 12:44:15.239586 SW Impedance : PASS
6042 12:44:15.239669 DUTY Scan : NO K
6043 12:44:15.243427 ZQ Calibration : PASS
6044 12:44:15.246642 Jitter Meter : NO K
6045 12:44:15.246741 CBT Training : PASS
6046 12:44:15.249962 Write leveling : PASS
6047 12:44:15.253341 RX DQS gating : PASS
6048 12:44:15.253414 RX DQ/DQS(RDDQC) : PASS
6049 12:44:15.256232 TX DQ/DQS : PASS
6050 12:44:15.259856 RX DATLAT : PASS
6051 12:44:15.259952 RX DQ/DQS(Engine): PASS
6052 12:44:15.263234 TX OE : NO K
6053 12:44:15.263348 All Pass.
6054 12:44:15.263445
6055 12:44:15.266045 CH 1, Rank 0
6056 12:44:15.266154 SW Impedance : PASS
6057 12:44:15.269363 DUTY Scan : NO K
6058 12:44:15.273138 ZQ Calibration : PASS
6059 12:44:15.273221 Jitter Meter : NO K
6060 12:44:15.276099 CBT Training : PASS
6061 12:44:15.279267 Write leveling : PASS
6062 12:44:15.279349 RX DQS gating : PASS
6063 12:44:15.282533 RX DQ/DQS(RDDQC) : PASS
6064 12:44:15.285678 TX DQ/DQS : PASS
6065 12:44:15.285761 RX DATLAT : PASS
6066 12:44:15.289065 RX DQ/DQS(Engine): PASS
6067 12:44:15.289147 TX OE : NO K
6068 12:44:15.292352 All Pass.
6069 12:44:15.292433
6070 12:44:15.292498 CH 1, Rank 1
6071 12:44:15.295756 SW Impedance : PASS
6072 12:44:15.299303 DUTY Scan : NO K
6073 12:44:15.299385 ZQ Calibration : PASS
6074 12:44:15.302724 Jitter Meter : NO K
6075 12:44:15.302805 CBT Training : PASS
6076 12:44:15.305665 Write leveling : PASS
6077 12:44:15.309159 RX DQS gating : PASS
6078 12:44:15.309241 RX DQ/DQS(RDDQC) : PASS
6079 12:44:15.312583 TX DQ/DQS : PASS
6080 12:44:15.315754 RX DATLAT : PASS
6081 12:44:15.315835 RX DQ/DQS(Engine): PASS
6082 12:44:15.319126 TX OE : NO K
6083 12:44:15.319208 All Pass.
6084 12:44:15.319273
6085 12:44:15.321873 DramC Write-DBI off
6086 12:44:15.325315 PER_BANK_REFRESH: Hybrid Mode
6087 12:44:15.325396 TX_TRACKING: ON
6088 12:44:15.335076 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6089 12:44:15.338683 [FAST_K] Save calibration result to emmc
6090 12:44:15.342167 dramc_set_vcore_voltage set vcore to 650000
6091 12:44:15.344988 Read voltage for 400, 6
6092 12:44:15.345070 Vio18 = 0
6093 12:44:15.348409 Vcore = 650000
6094 12:44:15.348490 Vdram = 0
6095 12:44:15.348556 Vddq = 0
6096 12:44:15.348616 Vmddr = 0
6097 12:44:15.354728 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6098 12:44:15.361569 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6099 12:44:15.361655 MEM_TYPE=3, freq_sel=20
6100 12:44:15.365241 sv_algorithm_assistance_LP4_800
6101 12:44:15.367997 ============ PULL DRAM RESETB DOWN ============
6102 12:44:15.374653 ========== PULL DRAM RESETB DOWN end =========
6103 12:44:15.378189 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6104 12:44:15.381470 ===================================
6105 12:44:15.384745 LPDDR4 DRAM CONFIGURATION
6106 12:44:15.388179 ===================================
6107 12:44:15.388262 EX_ROW_EN[0] = 0x0
6108 12:44:15.391476 EX_ROW_EN[1] = 0x0
6109 12:44:15.391558 LP4Y_EN = 0x0
6110 12:44:15.394809 WORK_FSP = 0x0
6111 12:44:15.397616 WL = 0x2
6112 12:44:15.397698 RL = 0x2
6113 12:44:15.400984 BL = 0x2
6114 12:44:15.401067 RPST = 0x0
6115 12:44:15.404408 RD_PRE = 0x0
6116 12:44:15.404491 WR_PRE = 0x1
6117 12:44:15.407885 WR_PST = 0x0
6118 12:44:15.407967 DBI_WR = 0x0
6119 12:44:15.411272 DBI_RD = 0x0
6120 12:44:15.411353 OTF = 0x1
6121 12:44:15.414231 ===================================
6122 12:44:15.417657 ===================================
6123 12:44:15.421090 ANA top config
6124 12:44:15.424436 ===================================
6125 12:44:15.424520 DLL_ASYNC_EN = 0
6126 12:44:15.427332 ALL_SLAVE_EN = 1
6127 12:44:15.430796 NEW_RANK_MODE = 1
6128 12:44:15.434176 DLL_IDLE_MODE = 1
6129 12:44:15.437578 LP45_APHY_COMB_EN = 1
6130 12:44:15.437661 TX_ODT_DIS = 1
6131 12:44:15.440503 NEW_8X_MODE = 1
6132 12:44:15.444029 ===================================
6133 12:44:15.447429 ===================================
6134 12:44:15.450977 data_rate = 800
6135 12:44:15.453840 CKR = 1
6136 12:44:15.457353 DQ_P2S_RATIO = 4
6137 12:44:15.460544 ===================================
6138 12:44:15.463755 CA_P2S_RATIO = 4
6139 12:44:15.463837 DQ_CA_OPEN = 0
6140 12:44:15.466909 DQ_SEMI_OPEN = 1
6141 12:44:15.470463 CA_SEMI_OPEN = 1
6142 12:44:15.473840 CA_FULL_RATE = 0
6143 12:44:15.477123 DQ_CKDIV4_EN = 0
6144 12:44:15.480532 CA_CKDIV4_EN = 1
6145 12:44:15.480615 CA_PREDIV_EN = 0
6146 12:44:15.483403 PH8_DLY = 0
6147 12:44:15.486755 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6148 12:44:15.490019 DQ_AAMCK_DIV = 0
6149 12:44:15.493556 CA_AAMCK_DIV = 0
6150 12:44:15.496802 CA_ADMCK_DIV = 4
6151 12:44:15.496880 DQ_TRACK_CA_EN = 0
6152 12:44:15.500123 CA_PICK = 800
6153 12:44:15.503385 CA_MCKIO = 400
6154 12:44:15.506636 MCKIO_SEMI = 400
6155 12:44:15.509882 PLL_FREQ = 3016
6156 12:44:15.513386 DQ_UI_PI_RATIO = 32
6157 12:44:15.516813 CA_UI_PI_RATIO = 32
6158 12:44:15.519732 ===================================
6159 12:44:15.523291 ===================================
6160 12:44:15.523367 memory_type:LPDDR4
6161 12:44:15.526352 GP_NUM : 10
6162 12:44:15.529717 SRAM_EN : 1
6163 12:44:15.529796 MD32_EN : 0
6164 12:44:15.533224 ===================================
6165 12:44:15.536654 [ANA_INIT] >>>>>>>>>>>>>>
6166 12:44:15.539529 <<<<<< [CONFIGURE PHASE]: ANA_TX
6167 12:44:15.542781 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6168 12:44:15.546275 ===================================
6169 12:44:15.549596 data_rate = 800,PCW = 0X7400
6170 12:44:15.552968 ===================================
6171 12:44:15.556344 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6172 12:44:15.559329 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6173 12:44:15.572631 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6174 12:44:15.575969 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6175 12:44:15.579332 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6176 12:44:15.582657 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6177 12:44:15.586036 [ANA_INIT] flow start
6178 12:44:15.589044 [ANA_INIT] PLL >>>>>>>>
6179 12:44:15.589142 [ANA_INIT] PLL <<<<<<<<
6180 12:44:15.592823 [ANA_INIT] MIDPI >>>>>>>>
6181 12:44:15.595819 [ANA_INIT] MIDPI <<<<<<<<
6182 12:44:15.595902 [ANA_INIT] DLL >>>>>>>>
6183 12:44:15.599283 [ANA_INIT] flow end
6184 12:44:15.602195 ============ LP4 DIFF to SE enter ============
6185 12:44:15.608822 ============ LP4 DIFF to SE exit ============
6186 12:44:15.608905 [ANA_INIT] <<<<<<<<<<<<<
6187 12:44:15.611934 [Flow] Enable top DCM control >>>>>
6188 12:44:15.615195 [Flow] Enable top DCM control <<<<<
6189 12:44:15.618991 Enable DLL master slave shuffle
6190 12:44:15.625661 ==============================================================
6191 12:44:15.625743 Gating Mode config
6192 12:44:15.631969 ==============================================================
6193 12:44:15.635166 Config description:
6194 12:44:15.644934 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6195 12:44:15.651944 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6196 12:44:15.654742 SELPH_MODE 0: By rank 1: By Phase
6197 12:44:15.661638 ==============================================================
6198 12:44:15.664630 GAT_TRACK_EN = 0
6199 12:44:15.668161 RX_GATING_MODE = 2
6200 12:44:15.668244 RX_GATING_TRACK_MODE = 2
6201 12:44:15.671501 SELPH_MODE = 1
6202 12:44:15.674960 PICG_EARLY_EN = 1
6203 12:44:15.677699 VALID_LAT_VALUE = 1
6204 12:44:15.684706 ==============================================================
6205 12:44:15.687933 Enter into Gating configuration >>>>
6206 12:44:15.691412 Exit from Gating configuration <<<<
6207 12:44:15.694374 Enter into DVFS_PRE_config >>>>>
6208 12:44:15.704577 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6209 12:44:15.707673 Exit from DVFS_PRE_config <<<<<
6210 12:44:15.711112 Enter into PICG configuration >>>>
6211 12:44:15.714537 Exit from PICG configuration <<<<
6212 12:44:15.717411 [RX_INPUT] configuration >>>>>
6213 12:44:15.721111 [RX_INPUT] configuration <<<<<
6214 12:44:15.724170 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6215 12:44:15.730777 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6216 12:44:15.737097 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6217 12:44:15.743953 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6218 12:44:15.750666 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6219 12:44:15.757104 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6220 12:44:15.760405 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6221 12:44:15.763924 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6222 12:44:15.766768 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6223 12:44:15.773219 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6224 12:44:15.776524 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6225 12:44:15.780087 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6226 12:44:15.783513 ===================================
6227 12:44:15.787214 LPDDR4 DRAM CONFIGURATION
6228 12:44:15.790186 ===================================
6229 12:44:15.790268 EX_ROW_EN[0] = 0x0
6230 12:44:15.793323 EX_ROW_EN[1] = 0x0
6231 12:44:15.796692 LP4Y_EN = 0x0
6232 12:44:15.796775 WORK_FSP = 0x0
6233 12:44:15.800142 WL = 0x2
6234 12:44:15.800224 RL = 0x2
6235 12:44:15.803192 BL = 0x2
6236 12:44:15.803273 RPST = 0x0
6237 12:44:15.806484 RD_PRE = 0x0
6238 12:44:15.806565 WR_PRE = 0x1
6239 12:44:15.809850 WR_PST = 0x0
6240 12:44:15.809932 DBI_WR = 0x0
6241 12:44:15.813345 DBI_RD = 0x0
6242 12:44:15.813427 OTF = 0x1
6243 12:44:15.816327 ===================================
6244 12:44:15.819684 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6245 12:44:15.826132 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6246 12:44:15.829688 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6247 12:44:15.832863 ===================================
6248 12:44:15.836286 LPDDR4 DRAM CONFIGURATION
6249 12:44:15.839679 ===================================
6250 12:44:15.839761 EX_ROW_EN[0] = 0x10
6251 12:44:15.842477 EX_ROW_EN[1] = 0x0
6252 12:44:15.842601 LP4Y_EN = 0x0
6253 12:44:15.845995 WORK_FSP = 0x0
6254 12:44:15.849461 WL = 0x2
6255 12:44:15.849542 RL = 0x2
6256 12:44:15.852793 BL = 0x2
6257 12:44:15.852875 RPST = 0x0
6258 12:44:15.855657 RD_PRE = 0x0
6259 12:44:15.855740 WR_PRE = 0x1
6260 12:44:15.859025 WR_PST = 0x0
6261 12:44:15.859107 DBI_WR = 0x0
6262 12:44:15.862482 DBI_RD = 0x0
6263 12:44:15.862563 OTF = 0x1
6264 12:44:15.865924 ===================================
6265 12:44:15.872365 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6266 12:44:15.876447 nWR fixed to 30
6267 12:44:15.879783 [ModeRegInit_LP4] CH0 RK0
6268 12:44:15.879865 [ModeRegInit_LP4] CH0 RK1
6269 12:44:15.883416 [ModeRegInit_LP4] CH1 RK0
6270 12:44:15.886329 [ModeRegInit_LP4] CH1 RK1
6271 12:44:15.886411 match AC timing 19
6272 12:44:15.893266 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6273 12:44:15.896419 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6274 12:44:15.899667 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6275 12:44:15.906270 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6276 12:44:15.909151 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6277 12:44:15.909235 ==
6278 12:44:15.912485 Dram Type= 6, Freq= 0, CH_0, rank 0
6279 12:44:15.915877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6280 12:44:15.915961 ==
6281 12:44:15.922799 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6282 12:44:15.929103 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6283 12:44:15.932928 [CA 0] Center 36 (8~64) winsize 57
6284 12:44:15.935610 [CA 1] Center 36 (8~64) winsize 57
6285 12:44:15.939231 [CA 2] Center 36 (8~64) winsize 57
6286 12:44:15.942457 [CA 3] Center 36 (8~64) winsize 57
6287 12:44:15.945791 [CA 4] Center 36 (8~64) winsize 57
6288 12:44:15.949089 [CA 5] Center 36 (8~64) winsize 57
6289 12:44:15.949173
6290 12:44:15.951941 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6291 12:44:15.952023
6292 12:44:15.955246 [CATrainingPosCal] consider 1 rank data
6293 12:44:15.958595 u2DelayCellTimex100 = 270/100 ps
6294 12:44:15.961982 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 12:44:15.965576 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 12:44:15.968955 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 12:44:15.971895 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 12:44:15.975341 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 12:44:15.978796 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 12:44:15.978940
6301 12:44:15.984840 CA PerBit enable=1, Macro0, CA PI delay=36
6302 12:44:15.984942
6303 12:44:15.985010 [CBTSetCACLKResult] CA Dly = 36
6304 12:44:15.988349 CS Dly: 1 (0~32)
6305 12:44:15.988432 ==
6306 12:44:15.991779 Dram Type= 6, Freq= 0, CH_0, rank 1
6307 12:44:15.995259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6308 12:44:15.995343 ==
6309 12:44:16.001847 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6310 12:44:16.008395 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6311 12:44:16.011760 [CA 0] Center 36 (8~64) winsize 57
6312 12:44:16.014689 [CA 1] Center 36 (8~64) winsize 57
6313 12:44:16.018214 [CA 2] Center 36 (8~64) winsize 57
6314 12:44:16.021936 [CA 3] Center 36 (8~64) winsize 57
6315 12:44:16.024923 [CA 4] Center 36 (8~64) winsize 57
6316 12:44:16.025004 [CA 5] Center 36 (8~64) winsize 57
6317 12:44:16.027871
6318 12:44:16.031465 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6319 12:44:16.031537
6320 12:44:16.034308 [CATrainingPosCal] consider 2 rank data
6321 12:44:16.037728 u2DelayCellTimex100 = 270/100 ps
6322 12:44:16.040916 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 12:44:16.044228 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6324 12:44:16.048138 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 12:44:16.051007 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6326 12:44:16.054281 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6327 12:44:16.057851 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6328 12:44:16.057926
6329 12:44:16.060579 CA PerBit enable=1, Macro0, CA PI delay=36
6330 12:44:16.064440
6331 12:44:16.064510 [CBTSetCACLKResult] CA Dly = 36
6332 12:44:16.067232 CS Dly: 1 (0~32)
6333 12:44:16.067303
6334 12:44:16.070740 ----->DramcWriteLeveling(PI) begin...
6335 12:44:16.070860 ==
6336 12:44:16.074258 Dram Type= 6, Freq= 0, CH_0, rank 0
6337 12:44:16.077226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6338 12:44:16.077321 ==
6339 12:44:16.080676 Write leveling (Byte 0): 40 => 8
6340 12:44:16.084148 Write leveling (Byte 1): 40 => 8
6341 12:44:16.086928 DramcWriteLeveling(PI) end<-----
6342 12:44:16.087000
6343 12:44:16.087081 ==
6344 12:44:16.090292 Dram Type= 6, Freq= 0, CH_0, rank 0
6345 12:44:16.093778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6346 12:44:16.096888 ==
6347 12:44:16.096960 [Gating] SW mode calibration
6348 12:44:16.107380 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6349 12:44:16.110226 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6350 12:44:16.113416 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6351 12:44:16.120320 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6352 12:44:16.123249 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6353 12:44:16.126789 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6354 12:44:16.133439 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6355 12:44:16.136944 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6356 12:44:16.139831 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6357 12:44:16.146466 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6358 12:44:16.149853 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6359 12:44:16.153308 Total UI for P1: 0, mck2ui 16
6360 12:44:16.156512 best dqsien dly found for B0: ( 0, 14, 24)
6361 12:44:16.159801 Total UI for P1: 0, mck2ui 16
6362 12:44:16.163053 best dqsien dly found for B1: ( 0, 14, 24)
6363 12:44:16.166236 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6364 12:44:16.169500 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6365 12:44:16.169576
6366 12:44:16.172894 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6367 12:44:16.179295 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6368 12:44:16.179372 [Gating] SW calibration Done
6369 12:44:16.179435 ==
6370 12:44:16.182772 Dram Type= 6, Freq= 0, CH_0, rank 0
6371 12:44:16.189234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6372 12:44:16.189316 ==
6373 12:44:16.189377 RX Vref Scan: 0
6374 12:44:16.189435
6375 12:44:16.192281 RX Vref 0 -> 0, step: 1
6376 12:44:16.192351
6377 12:44:16.195624 RX Delay -410 -> 252, step: 16
6378 12:44:16.199127 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6379 12:44:16.202687 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6380 12:44:16.209246 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6381 12:44:16.212264 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6382 12:44:16.215415 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6383 12:44:16.219156 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6384 12:44:16.225914 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6385 12:44:16.228911 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6386 12:44:16.232211 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6387 12:44:16.235668 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6388 12:44:16.241935 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6389 12:44:16.245323 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6390 12:44:16.248650 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6391 12:44:16.255621 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6392 12:44:16.258387 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6393 12:44:16.261944 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6394 12:44:16.262018 ==
6395 12:44:16.265204 Dram Type= 6, Freq= 0, CH_0, rank 0
6396 12:44:16.268401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6397 12:44:16.271889 ==
6398 12:44:16.271983 DQS Delay:
6399 12:44:16.272048 DQS0 = 59, DQS1 = 59
6400 12:44:16.275056 DQM Delay:
6401 12:44:16.275156 DQM0 = 18, DQM1 = 11
6402 12:44:16.278429 DQ Delay:
6403 12:44:16.281257 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6404 12:44:16.281331 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6405 12:44:16.284698 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6406 12:44:16.288155 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6407 12:44:16.288228
6408 12:44:16.291685
6409 12:44:16.291759 ==
6410 12:44:16.294603 Dram Type= 6, Freq= 0, CH_0, rank 0
6411 12:44:16.297911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6412 12:44:16.297986 ==
6413 12:44:16.298124
6414 12:44:16.298191
6415 12:44:16.301309 TX Vref Scan disable
6416 12:44:16.301397 == TX Byte 0 ==
6417 12:44:16.304867 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6418 12:44:16.311240 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6419 12:44:16.311344 == TX Byte 1 ==
6420 12:44:16.314680 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6421 12:44:16.321129 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6422 12:44:16.321210 ==
6423 12:44:16.324220 Dram Type= 6, Freq= 0, CH_0, rank 0
6424 12:44:16.327458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6425 12:44:16.327537 ==
6426 12:44:16.327601
6427 12:44:16.327660
6428 12:44:16.330686 TX Vref Scan disable
6429 12:44:16.330755 == TX Byte 0 ==
6430 12:44:16.337701 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6431 12:44:16.341150 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6432 12:44:16.341223 == TX Byte 1 ==
6433 12:44:16.347458 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6434 12:44:16.350774 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6435 12:44:16.350890
6436 12:44:16.350954 [DATLAT]
6437 12:44:16.354064 Freq=400, CH0 RK0
6438 12:44:16.354137
6439 12:44:16.354199 DATLAT Default: 0xf
6440 12:44:16.356908 0, 0xFFFF, sum = 0
6441 12:44:16.356988 1, 0xFFFF, sum = 0
6442 12:44:16.360383 2, 0xFFFF, sum = 0
6443 12:44:16.360460 3, 0xFFFF, sum = 0
6444 12:44:16.363885 4, 0xFFFF, sum = 0
6445 12:44:16.363962 5, 0xFFFF, sum = 0
6446 12:44:16.366941 6, 0xFFFF, sum = 0
6447 12:44:16.367010 7, 0xFFFF, sum = 0
6448 12:44:16.370221 8, 0xFFFF, sum = 0
6449 12:44:16.370293 9, 0xFFFF, sum = 0
6450 12:44:16.373575 10, 0xFFFF, sum = 0
6451 12:44:16.376999 11, 0xFFFF, sum = 0
6452 12:44:16.377078 12, 0xFFFF, sum = 0
6453 12:44:16.380234 13, 0x0, sum = 1
6454 12:44:16.380310 14, 0x0, sum = 2
6455 12:44:16.383457 15, 0x0, sum = 3
6456 12:44:16.383525 16, 0x0, sum = 4
6457 12:44:16.383632 best_step = 14
6458 12:44:16.383719
6459 12:44:16.386749 ==
6460 12:44:16.389937 Dram Type= 6, Freq= 0, CH_0, rank 0
6461 12:44:16.393188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6462 12:44:16.393263 ==
6463 12:44:16.393325 RX Vref Scan: 1
6464 12:44:16.393388
6465 12:44:16.396727 RX Vref 0 -> 0, step: 1
6466 12:44:16.396802
6467 12:44:16.400320 RX Delay -359 -> 252, step: 8
6468 12:44:16.400393
6469 12:44:16.403582 Set Vref, RX VrefLevel [Byte0]: 61
6470 12:44:16.406448 [Byte1]: 48
6471 12:44:16.410658
6472 12:44:16.410733 Final RX Vref Byte 0 = 61 to rank0
6473 12:44:16.413490 Final RX Vref Byte 1 = 48 to rank0
6474 12:44:16.416965 Final RX Vref Byte 0 = 61 to rank1
6475 12:44:16.420638 Final RX Vref Byte 1 = 48 to rank1==
6476 12:44:16.423591 Dram Type= 6, Freq= 0, CH_0, rank 0
6477 12:44:16.430094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6478 12:44:16.430167 ==
6479 12:44:16.430230 DQS Delay:
6480 12:44:16.433292 DQS0 = 60, DQS1 = 68
6481 12:44:16.433358 DQM Delay:
6482 12:44:16.433418 DQM0 = 14, DQM1 = 14
6483 12:44:16.436954 DQ Delay:
6484 12:44:16.439904 DQ0 =12, DQ1 =16, DQ2 =12, DQ3 =8
6485 12:44:16.443406 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6486 12:44:16.446642 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6487 12:44:16.450094 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6488 12:44:16.450173
6489 12:44:16.450236
6490 12:44:16.456377 [DQSOSCAuto] RK0, (LSB)MR18= 0x7a79, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
6491 12:44:16.459622 CH0 RK0: MR19=C0C, MR18=7A79
6492 12:44:16.466622 CH0_RK0: MR19=0xC0C, MR18=0x7A79, DQSOSC=394, MR23=63, INC=380, DEC=253
6493 12:44:16.466701 ==
6494 12:44:16.469882 Dram Type= 6, Freq= 0, CH_0, rank 1
6495 12:44:16.473045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6496 12:44:16.473119 ==
6497 12:44:16.476358 [Gating] SW mode calibration
6498 12:44:16.483116 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6499 12:44:16.489676 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6500 12:44:16.492949 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6501 12:44:16.495714 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6502 12:44:16.502404 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6503 12:44:16.505791 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6504 12:44:16.509206 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6505 12:44:16.515482 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6506 12:44:16.518979 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6507 12:44:16.522598 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6508 12:44:16.529198 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6509 12:44:16.532576 Total UI for P1: 0, mck2ui 16
6510 12:44:16.535499 best dqsien dly found for B0: ( 0, 14, 24)
6511 12:44:16.538756 Total UI for P1: 0, mck2ui 16
6512 12:44:16.542942 best dqsien dly found for B1: ( 0, 14, 24)
6513 12:44:16.545482 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6514 12:44:16.548682 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6515 12:44:16.548763
6516 12:44:16.552059 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6517 12:44:16.555408 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6518 12:44:16.558679 [Gating] SW calibration Done
6519 12:44:16.558785 ==
6520 12:44:16.562244 Dram Type= 6, Freq= 0, CH_0, rank 1
6521 12:44:16.565658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6522 12:44:16.565740 ==
6523 12:44:16.569095 RX Vref Scan: 0
6524 12:44:16.569176
6525 12:44:16.571965 RX Vref 0 -> 0, step: 1
6526 12:44:16.572071
6527 12:44:16.572151 RX Delay -410 -> 252, step: 16
6528 12:44:16.578751 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6529 12:44:16.582137 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6530 12:44:16.585457 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6531 12:44:16.592062 iDelay=230, Bit 3, Center -51 (-314 ~ 213) 528
6532 12:44:16.594805 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6533 12:44:16.598192 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6534 12:44:16.601911 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6535 12:44:16.608070 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6536 12:44:16.611500 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6537 12:44:16.614852 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6538 12:44:16.618524 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6539 12:44:16.624866 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6540 12:44:16.628277 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6541 12:44:16.631232 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6542 12:44:16.634731 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6543 12:44:16.641252 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6544 12:44:16.641355 ==
6545 12:44:16.644676 Dram Type= 6, Freq= 0, CH_0, rank 1
6546 12:44:16.648424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6547 12:44:16.648529 ==
6548 12:44:16.651153 DQS Delay:
6549 12:44:16.651260 DQS0 = 59, DQS1 = 59
6550 12:44:16.651349 DQM Delay:
6551 12:44:16.654316 DQM0 = 15, DQM1 = 10
6552 12:44:16.654402 DQ Delay:
6553 12:44:16.657784 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =8
6554 12:44:16.661337 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6555 12:44:16.664527 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6556 12:44:16.667773 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6557 12:44:16.667864
6558 12:44:16.667959
6559 12:44:16.668053 ==
6560 12:44:16.670775 Dram Type= 6, Freq= 0, CH_0, rank 1
6561 12:44:16.677651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6562 12:44:16.677740 ==
6563 12:44:16.677807
6564 12:44:16.677867
6565 12:44:16.677923 TX Vref Scan disable
6566 12:44:16.680996 == TX Byte 0 ==
6567 12:44:16.684009 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6568 12:44:16.687097 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6569 12:44:16.690491 == TX Byte 1 ==
6570 12:44:16.693740 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6571 12:44:16.696988 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6572 12:44:16.700195 ==
6573 12:44:16.700368 Dram Type= 6, Freq= 0, CH_0, rank 1
6574 12:44:16.707413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6575 12:44:16.707505 ==
6576 12:44:16.707573
6577 12:44:16.707634
6578 12:44:16.710296 TX Vref Scan disable
6579 12:44:16.710379 == TX Byte 0 ==
6580 12:44:16.713585 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6581 12:44:16.720614 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6582 12:44:16.720707 == TX Byte 1 ==
6583 12:44:16.723749 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6584 12:44:16.730259 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6585 12:44:16.730346
6586 12:44:16.730412 [DATLAT]
6587 12:44:16.730471 Freq=400, CH0 RK1
6588 12:44:16.730530
6589 12:44:16.733267 DATLAT Default: 0xe
6590 12:44:16.736884 0, 0xFFFF, sum = 0
6591 12:44:16.736969 1, 0xFFFF, sum = 0
6592 12:44:16.740142 2, 0xFFFF, sum = 0
6593 12:44:16.740230 3, 0xFFFF, sum = 0
6594 12:44:16.743067 4, 0xFFFF, sum = 0
6595 12:44:16.743153 5, 0xFFFF, sum = 0
6596 12:44:16.746407 6, 0xFFFF, sum = 0
6597 12:44:16.746493 7, 0xFFFF, sum = 0
6598 12:44:16.749803 8, 0xFFFF, sum = 0
6599 12:44:16.749905 9, 0xFFFF, sum = 0
6600 12:44:16.753208 10, 0xFFFF, sum = 0
6601 12:44:16.753293 11, 0xFFFF, sum = 0
6602 12:44:16.756312 12, 0xFFFF, sum = 0
6603 12:44:16.756398 13, 0x0, sum = 1
6604 12:44:16.759650 14, 0x0, sum = 2
6605 12:44:16.759737 15, 0x0, sum = 3
6606 12:44:16.763538 16, 0x0, sum = 4
6607 12:44:16.763730 best_step = 14
6608 12:44:16.763807
6609 12:44:16.763871 ==
6610 12:44:16.766642 Dram Type= 6, Freq= 0, CH_0, rank 1
6611 12:44:16.772856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6612 12:44:16.772943 ==
6613 12:44:16.773011 RX Vref Scan: 0
6614 12:44:16.773072
6615 12:44:16.776413 RX Vref 0 -> 0, step: 1
6616 12:44:16.776497
6617 12:44:16.779248 RX Delay -359 -> 252, step: 8
6618 12:44:16.785751 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6619 12:44:16.789173 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6620 12:44:16.792627 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6621 12:44:16.798906 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6622 12:44:16.802312 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6623 12:44:16.805571 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6624 12:44:16.808899 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6625 12:44:16.815482 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6626 12:44:16.818699 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6627 12:44:16.821897 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6628 12:44:16.825709 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6629 12:44:16.832078 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6630 12:44:16.835601 iDelay=217, Bit 12, Center -48 (-295 ~ 200) 496
6631 12:44:16.838521 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6632 12:44:16.842199 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6633 12:44:16.848471 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6634 12:44:16.848563 ==
6635 12:44:16.851980 Dram Type= 6, Freq= 0, CH_0, rank 1
6636 12:44:16.855283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6637 12:44:16.855368 ==
6638 12:44:16.855434 DQS Delay:
6639 12:44:16.858258 DQS0 = 60, DQS1 = 72
6640 12:44:16.858388 DQM Delay:
6641 12:44:16.861634 DQM0 = 11, DQM1 = 17
6642 12:44:16.861724 DQ Delay:
6643 12:44:16.864869 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6644 12:44:16.868062 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6645 12:44:16.872029 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6646 12:44:16.874759 DQ12 =24, DQ13 =28, DQ14 =28, DQ15 =24
6647 12:44:16.874869
6648 12:44:16.874974
6649 12:44:16.881511 [DQSOSCAuto] RK1, (LSB)MR18= 0xc378, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6650 12:44:16.884774 CH0 RK1: MR19=C0C, MR18=C378
6651 12:44:16.891688 CH0_RK1: MR19=0xC0C, MR18=0xC378, DQSOSC=385, MR23=63, INC=398, DEC=265
6652 12:44:16.894468 [RxdqsGatingPostProcess] freq 400
6653 12:44:16.901590 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6654 12:44:16.904797 best DQS0 dly(2T, 0.5T) = (0, 10)
6655 12:44:16.907951 best DQS1 dly(2T, 0.5T) = (0, 10)
6656 12:44:16.911332 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6657 12:44:16.914639 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6658 12:44:16.917890 best DQS0 dly(2T, 0.5T) = (0, 10)
6659 12:44:16.917980 best DQS1 dly(2T, 0.5T) = (0, 10)
6660 12:44:16.921078 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6661 12:44:16.924340 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6662 12:44:16.928004 Pre-setting of DQS Precalculation
6663 12:44:16.934465 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6664 12:44:16.934566 ==
6665 12:44:16.937383 Dram Type= 6, Freq= 0, CH_1, rank 0
6666 12:44:16.941155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6667 12:44:16.941247 ==
6668 12:44:16.947401 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6669 12:44:16.953811 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6670 12:44:16.957273 [CA 0] Center 36 (8~64) winsize 57
6671 12:44:16.960661 [CA 1] Center 36 (8~64) winsize 57
6672 12:44:16.963442 [CA 2] Center 36 (8~64) winsize 57
6673 12:44:16.966916 [CA 3] Center 36 (8~64) winsize 57
6674 12:44:16.970369 [CA 4] Center 36 (8~64) winsize 57
6675 12:44:16.970458 [CA 5] Center 36 (8~64) winsize 57
6676 12:44:16.973656
6677 12:44:16.976834 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6678 12:44:16.976922
6679 12:44:16.980411 [CATrainingPosCal] consider 1 rank data
6680 12:44:16.983210 u2DelayCellTimex100 = 270/100 ps
6681 12:44:16.986477 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 12:44:16.989751 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 12:44:16.993010 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 12:44:16.996492 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 12:44:16.999488 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 12:44:17.002999 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 12:44:17.003091
6688 12:44:17.009417 CA PerBit enable=1, Macro0, CA PI delay=36
6689 12:44:17.009526
6690 12:44:17.009593 [CBTSetCACLKResult] CA Dly = 36
6691 12:44:17.012747 CS Dly: 1 (0~32)
6692 12:44:17.012832 ==
6693 12:44:17.016035 Dram Type= 6, Freq= 0, CH_1, rank 1
6694 12:44:17.019648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6695 12:44:17.019739 ==
6696 12:44:17.026219 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6697 12:44:17.032687 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6698 12:44:17.035914 [CA 0] Center 36 (8~64) winsize 57
6699 12:44:17.039033 [CA 1] Center 36 (8~64) winsize 57
6700 12:44:17.042482 [CA 2] Center 36 (8~64) winsize 57
6701 12:44:17.046068 [CA 3] Center 36 (8~64) winsize 57
6702 12:44:17.046157 [CA 4] Center 36 (8~64) winsize 57
6703 12:44:17.049043 [CA 5] Center 36 (8~64) winsize 57
6704 12:44:17.049127
6705 12:44:17.055426 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6706 12:44:17.055519
6707 12:44:17.058806 [CATrainingPosCal] consider 2 rank data
6708 12:44:17.062129 u2DelayCellTimex100 = 270/100 ps
6709 12:44:17.065937 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 12:44:17.068507 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6711 12:44:17.071991 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 12:44:17.075598 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6713 12:44:17.078751 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6714 12:44:17.082258 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6715 12:44:17.082384
6716 12:44:17.085528 CA PerBit enable=1, Macro0, CA PI delay=36
6717 12:44:17.085632
6718 12:44:17.088321 [CBTSetCACLKResult] CA Dly = 36
6719 12:44:17.091616 CS Dly: 1 (0~32)
6720 12:44:17.091722
6721 12:44:17.095280 ----->DramcWriteLeveling(PI) begin...
6722 12:44:17.095367 ==
6723 12:44:17.098627 Dram Type= 6, Freq= 0, CH_1, rank 0
6724 12:44:17.102081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6725 12:44:17.102173 ==
6726 12:44:17.104999 Write leveling (Byte 0): 40 => 8
6727 12:44:17.108558 Write leveling (Byte 1): 40 => 8
6728 12:44:17.111421 DramcWriteLeveling(PI) end<-----
6729 12:44:17.111508
6730 12:44:17.111575 ==
6731 12:44:17.115082 Dram Type= 6, Freq= 0, CH_1, rank 0
6732 12:44:17.118515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6733 12:44:17.118605 ==
6734 12:44:17.121364 [Gating] SW mode calibration
6735 12:44:17.127811 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6736 12:44:17.134719 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6737 12:44:17.137810 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6738 12:44:17.144873 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6739 12:44:17.148069 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6740 12:44:17.150979 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6741 12:44:17.157391 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6742 12:44:17.160959 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6743 12:44:17.164415 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6744 12:44:17.170619 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6745 12:44:17.174030 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6746 12:44:17.177494 Total UI for P1: 0, mck2ui 16
6747 12:44:17.180489 best dqsien dly found for B0: ( 0, 14, 24)
6748 12:44:17.184159 Total UI for P1: 0, mck2ui 16
6749 12:44:17.187486 best dqsien dly found for B1: ( 0, 14, 24)
6750 12:44:17.190241 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6751 12:44:17.193631 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6752 12:44:17.193720
6753 12:44:17.196939 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6754 12:44:17.203856 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6755 12:44:17.203966 [Gating] SW calibration Done
6756 12:44:17.204038 ==
6757 12:44:17.207451 Dram Type= 6, Freq= 0, CH_1, rank 0
6758 12:44:17.213639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6759 12:44:17.213738 ==
6760 12:44:17.213807 RX Vref Scan: 0
6761 12:44:17.213871
6762 12:44:17.217154 RX Vref 0 -> 0, step: 1
6763 12:44:17.217240
6764 12:44:17.219995 RX Delay -410 -> 252, step: 16
6765 12:44:17.223425 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6766 12:44:17.227021 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6767 12:44:17.233398 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6768 12:44:17.236764 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6769 12:44:17.239829 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6770 12:44:17.243196 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6771 12:44:17.249999 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6772 12:44:17.252835 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6773 12:44:17.256597 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6774 12:44:17.259829 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6775 12:44:17.266321 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6776 12:44:17.269741 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6777 12:44:17.272879 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6778 12:44:17.279253 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6779 12:44:17.282684 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6780 12:44:17.285740 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6781 12:44:17.285852 ==
6782 12:44:17.289209 Dram Type= 6, Freq= 0, CH_1, rank 0
6783 12:44:17.292688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6784 12:44:17.295929 ==
6785 12:44:17.296048 DQS Delay:
6786 12:44:17.296145 DQS0 = 43, DQS1 = 67
6787 12:44:17.299179 DQM Delay:
6788 12:44:17.299266 DQM0 = 6, DQM1 = 18
6789 12:44:17.302538 DQ Delay:
6790 12:44:17.302625 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6791 12:44:17.305497 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6792 12:44:17.308961 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6793 12:44:17.312265 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =24
6794 12:44:17.312354
6795 12:44:17.312420
6796 12:44:17.315792 ==
6797 12:44:17.318626 Dram Type= 6, Freq= 0, CH_1, rank 0
6798 12:44:17.322227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6799 12:44:17.322322 ==
6800 12:44:17.322390
6801 12:44:17.322452
6802 12:44:17.325567 TX Vref Scan disable
6803 12:44:17.325653 == TX Byte 0 ==
6804 12:44:17.328364 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6805 12:44:17.335428 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6806 12:44:17.335525 == TX Byte 1 ==
6807 12:44:17.338669 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6808 12:44:17.345337 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6809 12:44:17.345438 ==
6810 12:44:17.348485 Dram Type= 6, Freq= 0, CH_1, rank 0
6811 12:44:17.351846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6812 12:44:17.351936 ==
6813 12:44:17.352003
6814 12:44:17.352064
6815 12:44:17.355215 TX Vref Scan disable
6816 12:44:17.355303 == TX Byte 0 ==
6817 12:44:17.358431 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6818 12:44:17.365048 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6819 12:44:17.365151 == TX Byte 1 ==
6820 12:44:17.368060 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6821 12:44:17.374901 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6822 12:44:17.375005
6823 12:44:17.375072 [DATLAT]
6824 12:44:17.378182 Freq=400, CH1 RK0
6825 12:44:17.378269
6826 12:44:17.378334 DATLAT Default: 0xf
6827 12:44:17.381600 0, 0xFFFF, sum = 0
6828 12:44:17.381688 1, 0xFFFF, sum = 0
6829 12:44:17.384430 2, 0xFFFF, sum = 0
6830 12:44:17.384514 3, 0xFFFF, sum = 0
6831 12:44:17.387990 4, 0xFFFF, sum = 0
6832 12:44:17.388076 5, 0xFFFF, sum = 0
6833 12:44:17.391501 6, 0xFFFF, sum = 0
6834 12:44:17.391589 7, 0xFFFF, sum = 0
6835 12:44:17.394446 8, 0xFFFF, sum = 0
6836 12:44:17.394532 9, 0xFFFF, sum = 0
6837 12:44:17.397859 10, 0xFFFF, sum = 0
6838 12:44:17.397945 11, 0xFFFF, sum = 0
6839 12:44:17.401007 12, 0xFFFF, sum = 0
6840 12:44:17.401152 13, 0x0, sum = 1
6841 12:44:17.404305 14, 0x0, sum = 2
6842 12:44:17.404425 15, 0x0, sum = 3
6843 12:44:17.407621 16, 0x0, sum = 4
6844 12:44:17.407833 best_step = 14
6845 12:44:17.407998
6846 12:44:17.408123 ==
6847 12:44:17.411139 Dram Type= 6, Freq= 0, CH_1, rank 0
6848 12:44:17.417632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6849 12:44:17.417727 ==
6850 12:44:17.417793 RX Vref Scan: 1
6851 12:44:17.417854
6852 12:44:17.421161 RX Vref 0 -> 0, step: 1
6853 12:44:17.421248
6854 12:44:17.424043 RX Delay -375 -> 252, step: 8
6855 12:44:17.424160
6856 12:44:17.427587 Set Vref, RX VrefLevel [Byte0]: 57
6857 12:44:17.430945 [Byte1]: 55
6858 12:44:17.434423
6859 12:44:17.434510 Final RX Vref Byte 0 = 57 to rank0
6860 12:44:17.437978 Final RX Vref Byte 1 = 55 to rank0
6861 12:44:17.440770 Final RX Vref Byte 0 = 57 to rank1
6862 12:44:17.444604 Final RX Vref Byte 1 = 55 to rank1==
6863 12:44:17.447415 Dram Type= 6, Freq= 0, CH_1, rank 0
6864 12:44:17.454205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6865 12:44:17.454303 ==
6866 12:44:17.454372 DQS Delay:
6867 12:44:17.457443 DQS0 = 52, DQS1 = 64
6868 12:44:17.457540 DQM Delay:
6869 12:44:17.457612 DQM0 = 9, DQM1 = 10
6870 12:44:17.460853 DQ Delay:
6871 12:44:17.464208 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6872 12:44:17.464287 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =4
6873 12:44:17.467431 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6874 12:44:17.470970 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6875 12:44:17.471091
6876 12:44:17.474285
6877 12:44:17.480565 [DQSOSCAuto] RK0, (LSB)MR18= 0x5063, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 399 ps
6878 12:44:17.483901 CH1 RK0: MR19=C0C, MR18=5063
6879 12:44:17.490364 CH1_RK0: MR19=0xC0C, MR18=0x5063, DQSOSC=397, MR23=63, INC=374, DEC=249
6880 12:44:17.490459 ==
6881 12:44:17.493905 Dram Type= 6, Freq= 0, CH_1, rank 1
6882 12:44:17.497144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6883 12:44:17.497226 ==
6884 12:44:17.500253 [Gating] SW mode calibration
6885 12:44:17.507001 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6886 12:44:17.513359 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6887 12:44:17.516804 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6888 12:44:17.519785 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6889 12:44:17.526592 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6890 12:44:17.529628 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6891 12:44:17.533119 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6892 12:44:17.539870 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6893 12:44:17.543173 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6894 12:44:17.546132 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6895 12:44:17.553167 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6896 12:44:17.553294 Total UI for P1: 0, mck2ui 16
6897 12:44:17.559312 best dqsien dly found for B0: ( 0, 14, 24)
6898 12:44:17.559444 Total UI for P1: 0, mck2ui 16
6899 12:44:17.566048 best dqsien dly found for B1: ( 0, 14, 24)
6900 12:44:17.569244 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6901 12:44:17.572521 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6902 12:44:17.572629
6903 12:44:17.575826 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6904 12:44:17.579119 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6905 12:44:17.582603 [Gating] SW calibration Done
6906 12:44:17.582714 ==
6907 12:44:17.585834 Dram Type= 6, Freq= 0, CH_1, rank 1
6908 12:44:17.589305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6909 12:44:17.589411 ==
6910 12:44:17.592246 RX Vref Scan: 0
6911 12:44:17.592345
6912 12:44:17.595790 RX Vref 0 -> 0, step: 1
6913 12:44:17.595865
6914 12:44:17.595943 RX Delay -410 -> 252, step: 16
6915 12:44:17.602321 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6916 12:44:17.605751 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6917 12:44:17.608672 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6918 12:44:17.615799 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6919 12:44:17.618531 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6920 12:44:17.622272 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6921 12:44:17.625130 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6922 12:44:17.631853 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6923 12:44:17.635413 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6924 12:44:17.638724 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6925 12:44:17.641669 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6926 12:44:17.648763 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6927 12:44:17.652137 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6928 12:44:17.654782 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6929 12:44:17.658389 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6930 12:44:17.665150 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6931 12:44:17.665265 ==
6932 12:44:17.668023 Dram Type= 6, Freq= 0, CH_1, rank 1
6933 12:44:17.671730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6934 12:44:17.671826 ==
6935 12:44:17.671893 DQS Delay:
6936 12:44:17.675069 DQS0 = 59, DQS1 = 67
6937 12:44:17.675156 DQM Delay:
6938 12:44:17.678214 DQM0 = 19, DQM1 = 21
6939 12:44:17.678335 DQ Delay:
6940 12:44:17.681310 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6941 12:44:17.684845 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6942 12:44:17.688048 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6943 12:44:17.691385 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =32
6944 12:44:17.691475
6945 12:44:17.691539
6946 12:44:17.691599 ==
6947 12:44:17.694725 Dram Type= 6, Freq= 0, CH_1, rank 1
6948 12:44:17.697656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6949 12:44:17.701303 ==
6950 12:44:17.701389
6951 12:44:17.701455
6952 12:44:17.701514 TX Vref Scan disable
6953 12:44:17.704257 == TX Byte 0 ==
6954 12:44:17.707759 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6955 12:44:17.711007 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6956 12:44:17.714518 == TX Byte 1 ==
6957 12:44:17.718022 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6958 12:44:17.720847 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6959 12:44:17.720937 ==
6960 12:44:17.724146 Dram Type= 6, Freq= 0, CH_1, rank 1
6961 12:44:17.731200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6962 12:44:17.731304 ==
6963 12:44:17.731384
6964 12:44:17.731448
6965 12:44:17.731506 TX Vref Scan disable
6966 12:44:17.734611 == TX Byte 0 ==
6967 12:44:17.737387 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6968 12:44:17.744441 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6969 12:44:17.744577 == TX Byte 1 ==
6970 12:44:17.747295 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6971 12:44:17.754113 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6972 12:44:17.754216
6973 12:44:17.754326 [DATLAT]
6974 12:44:17.754395 Freq=400, CH1 RK1
6975 12:44:17.754455
6976 12:44:17.757417 DATLAT Default: 0xe
6977 12:44:17.757538 0, 0xFFFF, sum = 0
6978 12:44:17.760808 1, 0xFFFF, sum = 0
6979 12:44:17.764237 2, 0xFFFF, sum = 0
6980 12:44:17.764341 3, 0xFFFF, sum = 0
6981 12:44:17.767208 4, 0xFFFF, sum = 0
6982 12:44:17.767369 5, 0xFFFF, sum = 0
6983 12:44:17.770997 6, 0xFFFF, sum = 0
6984 12:44:17.771085 7, 0xFFFF, sum = 0
6985 12:44:17.773666 8, 0xFFFF, sum = 0
6986 12:44:17.773770 9, 0xFFFF, sum = 0
6987 12:44:17.777200 10, 0xFFFF, sum = 0
6988 12:44:17.777307 11, 0xFFFF, sum = 0
6989 12:44:17.780387 12, 0xFFFF, sum = 0
6990 12:44:17.780497 13, 0x0, sum = 1
6991 12:44:17.783713 14, 0x0, sum = 2
6992 12:44:17.783800 15, 0x0, sum = 3
6993 12:44:17.786991 16, 0x0, sum = 4
6994 12:44:17.787077 best_step = 14
6995 12:44:17.787143
6996 12:44:17.787202 ==
6997 12:44:17.790146 Dram Type= 6, Freq= 0, CH_1, rank 1
6998 12:44:17.796639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6999 12:44:17.796740 ==
7000 12:44:17.796808 RX Vref Scan: 0
7001 12:44:17.796871
7002 12:44:17.800456 RX Vref 0 -> 0, step: 1
7003 12:44:17.800561
7004 12:44:17.803305 RX Delay -375 -> 252, step: 8
7005 12:44:17.809890 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
7006 12:44:17.813352 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7007 12:44:17.816521 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
7008 12:44:17.819866 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7009 12:44:17.826348 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
7010 12:44:17.829759 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7011 12:44:17.832992 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7012 12:44:17.836279 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
7013 12:44:17.842985 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
7014 12:44:17.846325 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
7015 12:44:17.849843 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7016 12:44:17.856261 iDelay=217, Bit 11, Center -56 (-311 ~ 200) 512
7017 12:44:17.859566 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7018 12:44:17.862918 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7019 12:44:17.866007 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7020 12:44:17.872548 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7021 12:44:17.872647 ==
7022 12:44:17.875880 Dram Type= 6, Freq= 0, CH_1, rank 1
7023 12:44:17.879156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7024 12:44:17.879238 ==
7025 12:44:17.879312 DQS Delay:
7026 12:44:17.882590 DQS0 = 60, DQS1 = 64
7027 12:44:17.882682 DQM Delay:
7028 12:44:17.886290 DQM0 = 12, DQM1 = 11
7029 12:44:17.886379 DQ Delay:
7030 12:44:17.889275 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7031 12:44:17.892463 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
7032 12:44:17.895758 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
7033 12:44:17.898648 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7034 12:44:17.898739
7035 12:44:17.898808
7036 12:44:17.905559 [DQSOSCAuto] RK1, (LSB)MR18= 0x74a5, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
7037 12:44:17.908506 CH1 RK1: MR19=C0C, MR18=74A5
7038 12:44:17.915344 CH1_RK1: MR19=0xC0C, MR18=0x74A5, DQSOSC=389, MR23=63, INC=390, DEC=260
7039 12:44:17.918753 [RxdqsGatingPostProcess] freq 400
7040 12:44:17.925167 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7041 12:44:17.928593 best DQS0 dly(2T, 0.5T) = (0, 10)
7042 12:44:17.932078 best DQS1 dly(2T, 0.5T) = (0, 10)
7043 12:44:17.935503 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7044 12:44:17.938821 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7045 12:44:17.938915 best DQS0 dly(2T, 0.5T) = (0, 10)
7046 12:44:17.941790 best DQS1 dly(2T, 0.5T) = (0, 10)
7047 12:44:17.945444 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7048 12:44:17.948619 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7049 12:44:17.951431 Pre-setting of DQS Precalculation
7050 12:44:17.958336 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7051 12:44:17.965186 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7052 12:44:17.971510 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7053 12:44:17.971625
7054 12:44:17.971696
7055 12:44:17.974879 [Calibration Summary] 800 Mbps
7056 12:44:17.974969 CH 0, Rank 0
7057 12:44:17.978357 SW Impedance : PASS
7058 12:44:17.981276 DUTY Scan : NO K
7059 12:44:17.981364 ZQ Calibration : PASS
7060 12:44:17.984723 Jitter Meter : NO K
7061 12:44:17.987859 CBT Training : PASS
7062 12:44:17.987950 Write leveling : PASS
7063 12:44:17.991196 RX DQS gating : PASS
7064 12:44:17.994321 RX DQ/DQS(RDDQC) : PASS
7065 12:44:17.994409 TX DQ/DQS : PASS
7066 12:44:17.997781 RX DATLAT : PASS
7067 12:44:18.001012 RX DQ/DQS(Engine): PASS
7068 12:44:18.001104 TX OE : NO K
7069 12:44:18.004401 All Pass.
7070 12:44:18.004495
7071 12:44:18.004563 CH 0, Rank 1
7072 12:44:18.007599 SW Impedance : PASS
7073 12:44:18.007710 DUTY Scan : NO K
7074 12:44:18.010822 ZQ Calibration : PASS
7075 12:44:18.014308 Jitter Meter : NO K
7076 12:44:18.014398 CBT Training : PASS
7077 12:44:18.017789 Write leveling : NO K
7078 12:44:18.020630 RX DQS gating : PASS
7079 12:44:18.020719 RX DQ/DQS(RDDQC) : PASS
7080 12:44:18.024108 TX DQ/DQS : PASS
7081 12:44:18.027083 RX DATLAT : PASS
7082 12:44:18.027172 RX DQ/DQS(Engine): PASS
7083 12:44:18.030581 TX OE : NO K
7084 12:44:18.030670 All Pass.
7085 12:44:18.030738
7086 12:44:18.033573 CH 1, Rank 0
7087 12:44:18.033686 SW Impedance : PASS
7088 12:44:18.036933 DUTY Scan : NO K
7089 12:44:18.040373 ZQ Calibration : PASS
7090 12:44:18.040471 Jitter Meter : NO K
7091 12:44:18.043818 CBT Training : PASS
7092 12:44:18.046999 Write leveling : PASS
7093 12:44:18.047115 RX DQS gating : PASS
7094 12:44:18.049996 RX DQ/DQS(RDDQC) : PASS
7095 12:44:18.053307 TX DQ/DQS : PASS
7096 12:44:18.053400 RX DATLAT : PASS
7097 12:44:18.056646 RX DQ/DQS(Engine): PASS
7098 12:44:18.060331 TX OE : NO K
7099 12:44:18.060426 All Pass.
7100 12:44:18.060494
7101 12:44:18.060556 CH 1, Rank 1
7102 12:44:18.063592 SW Impedance : PASS
7103 12:44:18.066526 DUTY Scan : NO K
7104 12:44:18.066616 ZQ Calibration : PASS
7105 12:44:18.070178 Jitter Meter : NO K
7106 12:44:18.072862 CBT Training : PASS
7107 12:44:18.072948 Write leveling : NO K
7108 12:44:18.076566 RX DQS gating : PASS
7109 12:44:18.079823 RX DQ/DQS(RDDQC) : PASS
7110 12:44:18.079914 TX DQ/DQS : PASS
7111 12:44:18.083270 RX DATLAT : PASS
7112 12:44:18.083356 RX DQ/DQS(Engine): PASS
7113 12:44:18.086170 TX OE : NO K
7114 12:44:18.086256 All Pass.
7115 12:44:18.086323
7116 12:44:18.089554 DramC Write-DBI off
7117 12:44:18.092884 PER_BANK_REFRESH: Hybrid Mode
7118 12:44:18.092973 TX_TRACKING: ON
7119 12:44:18.102968 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7120 12:44:18.106038 [FAST_K] Save calibration result to emmc
7121 12:44:18.109191 dramc_set_vcore_voltage set vcore to 725000
7122 12:44:18.112368 Read voltage for 1600, 0
7123 12:44:18.112463 Vio18 = 0
7124 12:44:18.115625 Vcore = 725000
7125 12:44:18.115724 Vdram = 0
7126 12:44:18.115813 Vddq = 0
7127 12:44:18.115889 Vmddr = 0
7128 12:44:18.122222 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7129 12:44:18.128762 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7130 12:44:18.128874 MEM_TYPE=3, freq_sel=13
7131 12:44:18.132619 sv_algorithm_assistance_LP4_3733
7132 12:44:18.138543 ============ PULL DRAM RESETB DOWN ============
7133 12:44:18.142350 ========== PULL DRAM RESETB DOWN end =========
7134 12:44:18.145278 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7135 12:44:18.148749 ===================================
7136 12:44:18.152036 LPDDR4 DRAM CONFIGURATION
7137 12:44:18.155421 ===================================
7138 12:44:18.158860 EX_ROW_EN[0] = 0x0
7139 12:44:18.158964 EX_ROW_EN[1] = 0x0
7140 12:44:18.162009 LP4Y_EN = 0x0
7141 12:44:18.162096 WORK_FSP = 0x1
7142 12:44:18.165438 WL = 0x5
7143 12:44:18.165525 RL = 0x5
7144 12:44:18.168726 BL = 0x2
7145 12:44:18.168814 RPST = 0x0
7146 12:44:18.171751 RD_PRE = 0x0
7147 12:44:18.171836 WR_PRE = 0x1
7148 12:44:18.175015 WR_PST = 0x1
7149 12:44:18.175104 DBI_WR = 0x0
7150 12:44:18.178489 DBI_RD = 0x0
7151 12:44:18.178575 OTF = 0x1
7152 12:44:18.181439 ===================================
7153 12:44:18.184950 ===================================
7154 12:44:18.188381 ANA top config
7155 12:44:18.191409 ===================================
7156 12:44:18.194809 DLL_ASYNC_EN = 0
7157 12:44:18.194920 ALL_SLAVE_EN = 0
7158 12:44:18.198270 NEW_RANK_MODE = 1
7159 12:44:18.201647 DLL_IDLE_MODE = 1
7160 12:44:18.204469 LP45_APHY_COMB_EN = 1
7161 12:44:18.207719 TX_ODT_DIS = 0
7162 12:44:18.207855 NEW_8X_MODE = 1
7163 12:44:18.211076 ===================================
7164 12:44:18.214812 ===================================
7165 12:44:18.217969 data_rate = 3200
7166 12:44:18.221179 CKR = 1
7167 12:44:18.224367 DQ_P2S_RATIO = 8
7168 12:44:18.227595 ===================================
7169 12:44:18.231193 CA_P2S_RATIO = 8
7170 12:44:18.234620 DQ_CA_OPEN = 0
7171 12:44:18.234706 DQ_SEMI_OPEN = 0
7172 12:44:18.237582 CA_SEMI_OPEN = 0
7173 12:44:18.241027 CA_FULL_RATE = 0
7174 12:44:18.244482 DQ_CKDIV4_EN = 0
7175 12:44:18.247281 CA_CKDIV4_EN = 0
7176 12:44:18.250810 CA_PREDIV_EN = 0
7177 12:44:18.250948 PH8_DLY = 12
7178 12:44:18.254384 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7179 12:44:18.257702 DQ_AAMCK_DIV = 4
7180 12:44:18.260840 CA_AAMCK_DIV = 4
7181 12:44:18.264248 CA_ADMCK_DIV = 4
7182 12:44:18.267006 DQ_TRACK_CA_EN = 0
7183 12:44:18.270320 CA_PICK = 1600
7184 12:44:18.270404 CA_MCKIO = 1600
7185 12:44:18.273721 MCKIO_SEMI = 0
7186 12:44:18.276996 PLL_FREQ = 3068
7187 12:44:18.280371 DQ_UI_PI_RATIO = 32
7188 12:44:18.283894 CA_UI_PI_RATIO = 0
7189 12:44:18.286764 ===================================
7190 12:44:18.290236 ===================================
7191 12:44:18.293767 memory_type:LPDDR4
7192 12:44:18.293880 GP_NUM : 10
7193 12:44:18.297367 SRAM_EN : 1
7194 12:44:18.297470 MD32_EN : 0
7195 12:44:18.300149 ===================================
7196 12:44:18.303584 [ANA_INIT] >>>>>>>>>>>>>>
7197 12:44:18.307023 <<<<<< [CONFIGURE PHASE]: ANA_TX
7198 12:44:18.310382 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7199 12:44:18.313846 ===================================
7200 12:44:18.316585 data_rate = 3200,PCW = 0X7600
7201 12:44:18.320040 ===================================
7202 12:44:18.323170 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7203 12:44:18.329824 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7204 12:44:18.333202 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7205 12:44:18.340117 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7206 12:44:18.342971 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7207 12:44:18.346537 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7208 12:44:18.346622 [ANA_INIT] flow start
7209 12:44:18.349895 [ANA_INIT] PLL >>>>>>>>
7210 12:44:18.352807 [ANA_INIT] PLL <<<<<<<<
7211 12:44:18.352885 [ANA_INIT] MIDPI >>>>>>>>
7212 12:44:18.356294 [ANA_INIT] MIDPI <<<<<<<<
7213 12:44:18.359794 [ANA_INIT] DLL >>>>>>>>
7214 12:44:18.362668 [ANA_INIT] DLL <<<<<<<<
7215 12:44:18.362768 [ANA_INIT] flow end
7216 12:44:18.366225 ============ LP4 DIFF to SE enter ============
7217 12:44:18.372498 ============ LP4 DIFF to SE exit ============
7218 12:44:18.372624 [ANA_INIT] <<<<<<<<<<<<<
7219 12:44:18.376297 [Flow] Enable top DCM control >>>>>
7220 12:44:18.379166 [Flow] Enable top DCM control <<<<<
7221 12:44:18.382593 Enable DLL master slave shuffle
7222 12:44:18.389034 ==============================================================
7223 12:44:18.392565 Gating Mode config
7224 12:44:18.395543 ==============================================================
7225 12:44:18.398962 Config description:
7226 12:44:18.408807 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7227 12:44:18.415622 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7228 12:44:18.418800 SELPH_MODE 0: By rank 1: By Phase
7229 12:44:18.425400 ==============================================================
7230 12:44:18.428612 GAT_TRACK_EN = 1
7231 12:44:18.432148 RX_GATING_MODE = 2
7232 12:44:18.435532 RX_GATING_TRACK_MODE = 2
7233 12:44:18.435630 SELPH_MODE = 1
7234 12:44:18.438689 PICG_EARLY_EN = 1
7235 12:44:18.442002 VALID_LAT_VALUE = 1
7236 12:44:18.448581 ==============================================================
7237 12:44:18.451533 Enter into Gating configuration >>>>
7238 12:44:18.454815 Exit from Gating configuration <<<<
7239 12:44:18.458377 Enter into DVFS_PRE_config >>>>>
7240 12:44:18.468344 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7241 12:44:18.471635 Exit from DVFS_PRE_config <<<<<
7242 12:44:18.474975 Enter into PICG configuration >>>>
7243 12:44:18.477899 Exit from PICG configuration <<<<
7244 12:44:18.481280 [RX_INPUT] configuration >>>>>
7245 12:44:18.484498 [RX_INPUT] configuration <<<<<
7246 12:44:18.491077 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7247 12:44:18.494482 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7248 12:44:18.500832 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7249 12:44:18.507820 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7250 12:44:18.514074 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7251 12:44:18.520868 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7252 12:44:18.524179 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7253 12:44:18.527506 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7254 12:44:18.531073 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7255 12:44:18.537104 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7256 12:44:18.540415 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7257 12:44:18.543657 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7258 12:44:18.547515 ===================================
7259 12:44:18.550441 LPDDR4 DRAM CONFIGURATION
7260 12:44:18.553862 ===================================
7261 12:44:18.553970 EX_ROW_EN[0] = 0x0
7262 12:44:18.557339 EX_ROW_EN[1] = 0x0
7263 12:44:18.560196 LP4Y_EN = 0x0
7264 12:44:18.560299 WORK_FSP = 0x1
7265 12:44:18.563797 WL = 0x5
7266 12:44:18.563903 RL = 0x5
7267 12:44:18.566727 BL = 0x2
7268 12:44:18.566814 RPST = 0x0
7269 12:44:18.570227 RD_PRE = 0x0
7270 12:44:18.570313 WR_PRE = 0x1
7271 12:44:18.573672 WR_PST = 0x1
7272 12:44:18.573758 DBI_WR = 0x0
7273 12:44:18.577063 DBI_RD = 0x0
7274 12:44:18.577151 OTF = 0x1
7275 12:44:18.580245 ===================================
7276 12:44:18.586725 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7277 12:44:18.590114 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7278 12:44:18.593344 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7279 12:44:18.596702 ===================================
7280 12:44:18.600061 LPDDR4 DRAM CONFIGURATION
7281 12:44:18.602856 ===================================
7282 12:44:18.606428 EX_ROW_EN[0] = 0x10
7283 12:44:18.606526 EX_ROW_EN[1] = 0x0
7284 12:44:18.609966 LP4Y_EN = 0x0
7285 12:44:18.610062 WORK_FSP = 0x1
7286 12:44:18.612876 WL = 0x5
7287 12:44:18.612964 RL = 0x5
7288 12:44:18.616296 BL = 0x2
7289 12:44:18.616384 RPST = 0x0
7290 12:44:18.619771 RD_PRE = 0x0
7291 12:44:18.619859 WR_PRE = 0x1
7292 12:44:18.623163 WR_PST = 0x1
7293 12:44:18.623260 DBI_WR = 0x0
7294 12:44:18.626097 DBI_RD = 0x0
7295 12:44:18.626182 OTF = 0x1
7296 12:44:18.629598 ===================================
7297 12:44:18.636220 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7298 12:44:18.636326 ==
7299 12:44:18.639446 Dram Type= 6, Freq= 0, CH_0, rank 0
7300 12:44:18.646225 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7301 12:44:18.646339 ==
7302 12:44:18.646410 [Duty_Offset_Calibration]
7303 12:44:18.649455 B0:2 B1:0 CA:3
7304 12:44:18.649543
7305 12:44:18.652598 [DutyScan_Calibration_Flow] k_type=0
7306 12:44:18.661889
7307 12:44:18.662006 ==CLK 0==
7308 12:44:18.665350 Final CLK duty delay cell = 0
7309 12:44:18.668748 [0] MAX Duty = 5031%(X100), DQS PI = 12
7310 12:44:18.671698 [0] MIN Duty = 4907%(X100), DQS PI = 6
7311 12:44:18.671805 [0] AVG Duty = 4969%(X100)
7312 12:44:18.675165
7313 12:44:18.678127 CH0 CLK Duty spec in!! Max-Min= 124%
7314 12:44:18.681584 [DutyScan_Calibration_Flow] ====Done====
7315 12:44:18.681677
7316 12:44:18.684858 [DutyScan_Calibration_Flow] k_type=1
7317 12:44:18.701881
7318 12:44:18.702027 ==DQS 0 ==
7319 12:44:18.704778 Final DQS duty delay cell = 0
7320 12:44:18.708090 [0] MAX Duty = 5125%(X100), DQS PI = 30
7321 12:44:18.711511 [0] MIN Duty = 4875%(X100), DQS PI = 48
7322 12:44:18.714981 [0] AVG Duty = 5000%(X100)
7323 12:44:18.715079
7324 12:44:18.715147 ==DQS 1 ==
7325 12:44:18.717917 Final DQS duty delay cell = 0
7326 12:44:18.721158 [0] MAX Duty = 5156%(X100), DQS PI = 30
7327 12:44:18.724637 [0] MIN Duty = 5062%(X100), DQS PI = 8
7328 12:44:18.728061 [0] AVG Duty = 5109%(X100)
7329 12:44:18.728155
7330 12:44:18.731004 CH0 DQS 0 Duty spec in!! Max-Min= 250%
7331 12:44:18.731092
7332 12:44:18.734588 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7333 12:44:18.737942 [DutyScan_Calibration_Flow] ====Done====
7334 12:44:18.738031
7335 12:44:18.741495 [DutyScan_Calibration_Flow] k_type=3
7336 12:44:18.759315
7337 12:44:18.759472 ==DQM 0 ==
7338 12:44:18.762500 Final DQM duty delay cell = 0
7339 12:44:18.765856 [0] MAX Duty = 5156%(X100), DQS PI = 30
7340 12:44:18.769191 [0] MIN Duty = 4875%(X100), DQS PI = 2
7341 12:44:18.772141 [0] AVG Duty = 5015%(X100)
7342 12:44:18.772245
7343 12:44:18.772341 ==DQM 1 ==
7344 12:44:18.775643 Final DQM duty delay cell = 4
7345 12:44:18.779197 [4] MAX Duty = 5187%(X100), DQS PI = 62
7346 12:44:18.782685 [4] MIN Duty = 5031%(X100), DQS PI = 12
7347 12:44:18.785563 [4] AVG Duty = 5109%(X100)
7348 12:44:18.785707
7349 12:44:18.789122 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7350 12:44:18.789210
7351 12:44:18.792749 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7352 12:44:18.795718 [DutyScan_Calibration_Flow] ====Done====
7353 12:44:18.795807
7354 12:44:18.799045 [DutyScan_Calibration_Flow] k_type=2
7355 12:44:18.815324
7356 12:44:18.815480 ==DQ 0 ==
7357 12:44:18.818738 Final DQ duty delay cell = -4
7358 12:44:18.822102 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7359 12:44:18.825428 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7360 12:44:18.828742 [-4] AVG Duty = 4938%(X100)
7361 12:44:18.828842
7362 12:44:18.828906 ==DQ 1 ==
7363 12:44:18.832214 Final DQ duty delay cell = 0
7364 12:44:18.835181 [0] MAX Duty = 5156%(X100), DQS PI = 58
7365 12:44:18.838717 [0] MIN Duty = 5000%(X100), DQS PI = 16
7366 12:44:18.841603 [0] AVG Duty = 5078%(X100)
7367 12:44:18.841697
7368 12:44:18.845028 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7369 12:44:18.845112
7370 12:44:18.848362 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7371 12:44:18.851714 [DutyScan_Calibration_Flow] ====Done====
7372 12:44:18.851801 ==
7373 12:44:18.854925 Dram Type= 6, Freq= 0, CH_1, rank 0
7374 12:44:18.858558 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7375 12:44:18.858657 ==
7376 12:44:18.861443 [Duty_Offset_Calibration]
7377 12:44:18.861527 B0:1 B1:-2 CA:0
7378 12:44:18.864815
7379 12:44:18.864902 [DutyScan_Calibration_Flow] k_type=0
7380 12:44:18.876054
7381 12:44:18.876185 ==CLK 0==
7382 12:44:18.879062 Final CLK duty delay cell = 0
7383 12:44:18.882558 [0] MAX Duty = 5062%(X100), DQS PI = 22
7384 12:44:18.886349 [0] MIN Duty = 4844%(X100), DQS PI = 2
7385 12:44:18.888820 [0] AVG Duty = 4953%(X100)
7386 12:44:18.888905
7387 12:44:18.892426 CH1 CLK Duty spec in!! Max-Min= 218%
7388 12:44:18.895961 [DutyScan_Calibration_Flow] ====Done====
7389 12:44:18.896046
7390 12:44:18.898744 [DutyScan_Calibration_Flow] k_type=1
7391 12:44:18.914442
7392 12:44:18.914587 ==DQS 0 ==
7393 12:44:18.917711 Final DQS duty delay cell = -4
7394 12:44:18.921170 [-4] MAX Duty = 4969%(X100), DQS PI = 24
7395 12:44:18.924416 [-4] MIN Duty = 4844%(X100), DQS PI = 46
7396 12:44:18.927828 [-4] AVG Duty = 4906%(X100)
7397 12:44:18.927916
7398 12:44:18.927980 ==DQS 1 ==
7399 12:44:18.931100 Final DQS duty delay cell = 0
7400 12:44:18.934492 [0] MAX Duty = 5093%(X100), DQS PI = 60
7401 12:44:18.938081 [0] MIN Duty = 4844%(X100), DQS PI = 24
7402 12:44:18.941314 [0] AVG Duty = 4968%(X100)
7403 12:44:18.941401
7404 12:44:18.944548 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7405 12:44:18.944647
7406 12:44:18.947599 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7407 12:44:18.950924 [DutyScan_Calibration_Flow] ====Done====
7408 12:44:18.951006
7409 12:44:18.954340 [DutyScan_Calibration_Flow] k_type=3
7410 12:44:18.971619
7411 12:44:18.971758 ==DQM 0 ==
7412 12:44:18.974839 Final DQM duty delay cell = 0
7413 12:44:18.978446 [0] MAX Duty = 5031%(X100), DQS PI = 24
7414 12:44:18.981843 [0] MIN Duty = 4813%(X100), DQS PI = 54
7415 12:44:18.984663 [0] AVG Duty = 4922%(X100)
7416 12:44:18.984749
7417 12:44:18.984812 ==DQM 1 ==
7418 12:44:18.988150 Final DQM duty delay cell = 0
7419 12:44:18.991643 [0] MAX Duty = 5093%(X100), DQS PI = 36
7420 12:44:18.994571 [0] MIN Duty = 4875%(X100), DQS PI = 24
7421 12:44:18.998201 [0] AVG Duty = 4984%(X100)
7422 12:44:18.998329
7423 12:44:19.001644 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7424 12:44:19.001730
7425 12:44:19.004590 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7426 12:44:19.008086 [DutyScan_Calibration_Flow] ====Done====
7427 12:44:19.008189
7428 12:44:19.010976 [DutyScan_Calibration_Flow] k_type=2
7429 12:44:19.028910
7430 12:44:19.029063 ==DQ 0 ==
7431 12:44:19.031816 Final DQ duty delay cell = 0
7432 12:44:19.035118 [0] MAX Duty = 5093%(X100), DQS PI = 22
7433 12:44:19.038228 [0] MIN Duty = 4938%(X100), DQS PI = 0
7434 12:44:19.038318 [0] AVG Duty = 5015%(X100)
7435 12:44:19.041776
7436 12:44:19.041864 ==DQ 1 ==
7437 12:44:19.044846 Final DQ duty delay cell = 0
7438 12:44:19.048195 [0] MAX Duty = 5156%(X100), DQS PI = 36
7439 12:44:19.051622 [0] MIN Duty = 4969%(X100), DQS PI = 24
7440 12:44:19.051713 [0] AVG Duty = 5062%(X100)
7441 12:44:19.055185
7442 12:44:19.057962 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7443 12:44:19.058048
7444 12:44:19.061371 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7445 12:44:19.064912 [DutyScan_Calibration_Flow] ====Done====
7446 12:44:19.067863 nWR fixed to 30
7447 12:44:19.071795 [ModeRegInit_LP4] CH0 RK0
7448 12:44:19.071889 [ModeRegInit_LP4] CH0 RK1
7449 12:44:19.074674 [ModeRegInit_LP4] CH1 RK0
7450 12:44:19.077781 [ModeRegInit_LP4] CH1 RK1
7451 12:44:19.077873 match AC timing 5
7452 12:44:19.084672 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7453 12:44:19.087876 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7454 12:44:19.091024 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7455 12:44:19.097621 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7456 12:44:19.100983 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7457 12:44:19.101083 [MiockJmeterHQA]
7458 12:44:19.101149
7459 12:44:19.104334 [DramcMiockJmeter] u1RxGatingPI = 0
7460 12:44:19.107803 0 : 4255, 4027
7461 12:44:19.107901 4 : 4260, 4034
7462 12:44:19.111275 8 : 4255, 4029
7463 12:44:19.111407 12 : 4365, 4140
7464 12:44:19.114728 16 : 4255, 4029
7465 12:44:19.114816 20 : 4366, 4140
7466 12:44:19.114926 24 : 4258, 4029
7467 12:44:19.117825 28 : 4365, 4140
7468 12:44:19.117910 32 : 4255, 4030
7469 12:44:19.120723 36 : 4252, 4029
7470 12:44:19.120809 40 : 4360, 4138
7471 12:44:19.124266 44 : 4254, 4029
7472 12:44:19.124354 48 : 4255, 4030
7473 12:44:19.127596 52 : 4252, 4029
7474 12:44:19.127697 56 : 4257, 4032
7475 12:44:19.127765 60 : 4253, 4029
7476 12:44:19.130414 64 : 4363, 4140
7477 12:44:19.130529 68 : 4255, 4029
7478 12:44:19.133707 72 : 4252, 4030
7479 12:44:19.133794 76 : 4250, 4027
7480 12:44:19.137502 80 : 4255, 4029
7481 12:44:19.137591 84 : 4255, 4029
7482 12:44:19.140777 88 : 4365, 4140
7483 12:44:19.140865 92 : 4253, 4029
7484 12:44:19.140933 96 : 4253, 4029
7485 12:44:19.144304 100 : 4255, 4029
7486 12:44:19.144391 104 : 4253, 3580
7487 12:44:19.147197 108 : 4252, 1
7488 12:44:19.147284 112 : 4366, 0
7489 12:44:19.150779 116 : 4253, 0
7490 12:44:19.150902 120 : 4363, 0
7491 12:44:19.150973 124 : 4252, 0
7492 12:44:19.153694 128 : 4252, 0
7493 12:44:19.153780 132 : 4253, 0
7494 12:44:19.157269 136 : 4252, 0
7495 12:44:19.157355 140 : 4368, 0
7496 12:44:19.157423 144 : 4252, 0
7497 12:44:19.160258 148 : 4252, 0
7498 12:44:19.160344 152 : 4253, 0
7499 12:44:19.163733 156 : 4368, 0
7500 12:44:19.163818 160 : 4255, 0
7501 12:44:19.163885 164 : 4253, 0
7502 12:44:19.167159 168 : 4368, 0
7503 12:44:19.167278 172 : 4363, 0
7504 12:44:19.167345 176 : 4363, 0
7505 12:44:19.170151 180 : 4250, 0
7506 12:44:19.170236 184 : 4253, 0
7507 12:44:19.173948 188 : 4252, 0
7508 12:44:19.174036 192 : 4363, 0
7509 12:44:19.174104 196 : 4252, 0
7510 12:44:19.176433 200 : 4252, 0
7511 12:44:19.176520 204 : 4363, 0
7512 12:44:19.180071 208 : 4252, 0
7513 12:44:19.180159 212 : 4252, 0
7514 12:44:19.180225 216 : 4253, 0
7515 12:44:19.183270 220 : 4368, 0
7516 12:44:19.183356 224 : 4363, 0
7517 12:44:19.186555 228 : 4365, 0
7518 12:44:19.186626 232 : 4368, 1
7519 12:44:19.186689 236 : 4252, 1137
7520 12:44:19.189807 240 : 4255, 4032
7521 12:44:19.189895 244 : 4254, 4029
7522 12:44:19.193140 248 : 4363, 4140
7523 12:44:19.193258 252 : 4365, 4140
7524 12:44:19.196773 256 : 4250, 4027
7525 12:44:19.196863 260 : 4255, 4030
7526 12:44:19.199980 264 : 4252, 4030
7527 12:44:19.200066 268 : 4252, 4029
7528 12:44:19.202866 272 : 4252, 4029
7529 12:44:19.202966 276 : 4257, 4032
7530 12:44:19.206404 280 : 4366, 4140
7531 12:44:19.206500 284 : 4253, 4027
7532 12:44:19.209976 288 : 4252, 4030
7533 12:44:19.210086 292 : 4366, 4140
7534 12:44:19.212801 296 : 4255, 4029
7535 12:44:19.212915 300 : 4253, 4029
7536 12:44:19.213018 304 : 4252, 4029
7537 12:44:19.216323 308 : 4367, 4143
7538 12:44:19.216425 312 : 4255, 4029
7539 12:44:19.219629 316 : 4253, 4029
7540 12:44:19.219708 320 : 4360, 4137
7541 12:44:19.223029 324 : 4255, 4029
7542 12:44:19.223114 328 : 4252, 4029
7543 12:44:19.225821 332 : 4253, 4029
7544 12:44:19.225924 336 : 4252, 4029
7545 12:44:19.229237 340 : 4254, 4029
7546 12:44:19.229324 344 : 4368, 4143
7547 12:44:19.232690 348 : 4253, 4029
7548 12:44:19.232767 352 : 4252, 4020
7549 12:44:19.236050 356 : 4252, 2901
7550 12:44:19.236151 360 : 4258, 1
7551 12:44:19.236241
7552 12:44:19.239370 MIOCK jitter meter ch=0
7553 12:44:19.239451
7554 12:44:19.242647 1T = (360-108) = 252 dly cells
7555 12:44:19.245985 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7556 12:44:19.246099 ==
7557 12:44:19.249339 Dram Type= 6, Freq= 0, CH_0, rank 0
7558 12:44:19.256168 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7559 12:44:19.256281 ==
7560 12:44:19.259024 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7561 12:44:19.265403 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7562 12:44:19.268873 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7563 12:44:19.275742 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7564 12:44:19.283372 [CA 0] Center 44 (14~74) winsize 61
7565 12:44:19.286734 [CA 1] Center 43 (13~74) winsize 62
7566 12:44:19.289937 [CA 2] Center 39 (10~68) winsize 59
7567 12:44:19.293341 [CA 3] Center 38 (9~68) winsize 60
7568 12:44:19.296621 [CA 4] Center 36 (7~66) winsize 60
7569 12:44:19.299908 [CA 5] Center 36 (7~66) winsize 60
7570 12:44:19.300021
7571 12:44:19.302979 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7572 12:44:19.303068
7573 12:44:19.309752 [CATrainingPosCal] consider 1 rank data
7574 12:44:19.309865 u2DelayCellTimex100 = 258/100 ps
7575 12:44:19.316091 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7576 12:44:19.319573 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7577 12:44:19.323195 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7578 12:44:19.326231 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7579 12:44:19.329514 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7580 12:44:19.332901 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7581 12:44:19.332992
7582 12:44:19.336407 CA PerBit enable=1, Macro0, CA PI delay=36
7583 12:44:19.336494
7584 12:44:19.339320 [CBTSetCACLKResult] CA Dly = 36
7585 12:44:19.342684 CS Dly: 11 (0~42)
7586 12:44:19.346139 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7587 12:44:19.349355 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7588 12:44:19.349529 ==
7589 12:44:19.352598 Dram Type= 6, Freq= 0, CH_0, rank 1
7590 12:44:19.359440 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7591 12:44:19.359557 ==
7592 12:44:19.362678 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7593 12:44:19.369093 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7594 12:44:19.372462 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7595 12:44:19.378716 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7596 12:44:19.387552 [CA 0] Center 44 (13~75) winsize 63
7597 12:44:19.390428 [CA 1] Center 43 (13~74) winsize 62
7598 12:44:19.393706 [CA 2] Center 39 (10~69) winsize 60
7599 12:44:19.396921 [CA 3] Center 39 (10~69) winsize 60
7600 12:44:19.400410 [CA 4] Center 37 (8~67) winsize 60
7601 12:44:19.403472 [CA 5] Center 36 (7~66) winsize 60
7602 12:44:19.403632
7603 12:44:19.406750 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7604 12:44:19.410120
7605 12:44:19.413615 [CATrainingPosCal] consider 2 rank data
7606 12:44:19.416419 u2DelayCellTimex100 = 258/100 ps
7607 12:44:19.419799 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7608 12:44:19.423444 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7609 12:44:19.426322 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7610 12:44:19.429797 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7611 12:44:19.433106 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7612 12:44:19.436391 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7613 12:44:19.436484
7614 12:44:19.443088 CA PerBit enable=1, Macro0, CA PI delay=36
7615 12:44:19.443186
7616 12:44:19.443256 [CBTSetCACLKResult] CA Dly = 36
7617 12:44:19.446485 CS Dly: 11 (0~43)
7618 12:44:19.449535 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7619 12:44:19.456224 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7620 12:44:19.456334
7621 12:44:19.459542 ----->DramcWriteLeveling(PI) begin...
7622 12:44:19.459631 ==
7623 12:44:19.462400 Dram Type= 6, Freq= 0, CH_0, rank 0
7624 12:44:19.465748 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7625 12:44:19.465838 ==
7626 12:44:19.469240 Write leveling (Byte 0): 35 => 35
7627 12:44:19.472311 Write leveling (Byte 1): 28 => 28
7628 12:44:19.475728 DramcWriteLeveling(PI) end<-----
7629 12:44:19.475820
7630 12:44:19.475889 ==
7631 12:44:19.479165 Dram Type= 6, Freq= 0, CH_0, rank 0
7632 12:44:19.482799 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7633 12:44:19.482903 ==
7634 12:44:19.485782 [Gating] SW mode calibration
7635 12:44:19.492153 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7636 12:44:19.498708 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7637 12:44:19.502129 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7638 12:44:19.505360 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7639 12:44:19.512175 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7640 12:44:19.515357 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7641 12:44:19.518585 1 4 16 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7642 12:44:19.525162 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7643 12:44:19.528801 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
7644 12:44:19.531794 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7645 12:44:19.538620 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7646 12:44:19.541997 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7647 12:44:19.545425 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7648 12:44:19.551961 1 5 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7649 12:44:19.555081 1 5 16 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 0)
7650 12:44:19.558247 1 5 20 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
7651 12:44:19.565279 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
7652 12:44:19.568424 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7653 12:44:19.571841 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7654 12:44:19.578178 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7655 12:44:19.581709 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7656 12:44:19.584616 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7657 12:44:19.591541 1 6 16 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
7658 12:44:19.594467 1 6 20 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)
7659 12:44:19.597993 1 6 24 | B1->B0 | 4040 4646 | 0 0 | (1 1) (0 0)
7660 12:44:19.604285 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7661 12:44:19.607789 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7662 12:44:19.611114 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7663 12:44:19.617741 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7664 12:44:19.621122 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7665 12:44:19.624032 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7666 12:44:19.631142 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7667 12:44:19.634033 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7668 12:44:19.637732 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 12:44:19.643790 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 12:44:19.646947 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 12:44:19.650568 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 12:44:19.657171 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7673 12:44:19.660484 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7674 12:44:19.663900 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7675 12:44:19.670478 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7676 12:44:19.673458 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 12:44:19.676714 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7678 12:44:19.683382 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7679 12:44:19.686916 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7680 12:44:19.689800 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7681 12:44:19.696668 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7682 12:44:19.700117 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7683 12:44:19.703022 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7684 12:44:19.706510 Total UI for P1: 0, mck2ui 16
7685 12:44:19.709971 best dqsien dly found for B0: ( 1, 9, 16)
7686 12:44:19.716637 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7687 12:44:19.719579 Total UI for P1: 0, mck2ui 16
7688 12:44:19.722923 best dqsien dly found for B1: ( 1, 9, 24)
7689 12:44:19.726249 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7690 12:44:19.729518 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7691 12:44:19.729601
7692 12:44:19.732581 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7693 12:44:19.736276 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7694 12:44:19.739711 [Gating] SW calibration Done
7695 12:44:19.739798 ==
7696 12:44:19.742636 Dram Type= 6, Freq= 0, CH_0, rank 0
7697 12:44:19.746043 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7698 12:44:19.746123 ==
7699 12:44:19.749435 RX Vref Scan: 0
7700 12:44:19.749512
7701 12:44:19.752672 RX Vref 0 -> 0, step: 1
7702 12:44:19.752762
7703 12:44:19.752826 RX Delay 0 -> 252, step: 8
7704 12:44:19.758957 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7705 12:44:19.762464 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7706 12:44:19.766033 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7707 12:44:19.768907 iDelay=200, Bit 3, Center 119 (64 ~ 175) 112
7708 12:44:19.772304 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7709 12:44:19.778707 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
7710 12:44:19.782199 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7711 12:44:19.785433 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7712 12:44:19.789057 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7713 12:44:19.791968 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7714 12:44:19.798413 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7715 12:44:19.801917 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7716 12:44:19.805470 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7717 12:44:19.808399 iDelay=200, Bit 13, Center 127 (72 ~ 183) 112
7718 12:44:19.815209 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7719 12:44:19.818586 iDelay=200, Bit 15, Center 127 (72 ~ 183) 112
7720 12:44:19.818678 ==
7721 12:44:19.821368 Dram Type= 6, Freq= 0, CH_0, rank 0
7722 12:44:19.824974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7723 12:44:19.825058 ==
7724 12:44:19.828693 DQS Delay:
7725 12:44:19.828775 DQS0 = 0, DQS1 = 0
7726 12:44:19.828845 DQM Delay:
7727 12:44:19.831565 DQM0 = 128, DQM1 = 123
7728 12:44:19.831640 DQ Delay:
7729 12:44:19.834917 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119
7730 12:44:19.838115 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =143
7731 12:44:19.844545 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7732 12:44:19.847919 DQ12 =127, DQ13 =127, DQ14 =135, DQ15 =127
7733 12:44:19.848009
7734 12:44:19.848074
7735 12:44:19.848134 ==
7736 12:44:19.850991 Dram Type= 6, Freq= 0, CH_0, rank 0
7737 12:44:19.854548 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7738 12:44:19.854644 ==
7739 12:44:19.854711
7740 12:44:19.854771
7741 12:44:19.857761 TX Vref Scan disable
7742 12:44:19.861236 == TX Byte 0 ==
7743 12:44:19.864545 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7744 12:44:19.867905 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7745 12:44:19.870811 == TX Byte 1 ==
7746 12:44:19.874428 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7747 12:44:19.877374 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7748 12:44:19.877481 ==
7749 12:44:19.880627 Dram Type= 6, Freq= 0, CH_0, rank 0
7750 12:44:19.887380 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7751 12:44:19.887482 ==
7752 12:44:19.899535
7753 12:44:19.903233 TX Vref early break, caculate TX vref
7754 12:44:19.905863 TX Vref=16, minBit 8, minWin=21, winSum=361
7755 12:44:19.909376 TX Vref=18, minBit 8, minWin=21, winSum=365
7756 12:44:19.912919 TX Vref=20, minBit 11, minWin=22, winSum=376
7757 12:44:19.915881 TX Vref=22, minBit 4, minWin=23, winSum=388
7758 12:44:19.919485 TX Vref=24, minBit 4, minWin=24, winSum=401
7759 12:44:19.926086 TX Vref=26, minBit 11, minWin=24, winSum=406
7760 12:44:19.929539 TX Vref=28, minBit 9, minWin=24, winSum=407
7761 12:44:19.932323 TX Vref=30, minBit 8, minWin=23, winSum=399
7762 12:44:19.935903 TX Vref=32, minBit 8, minWin=23, winSum=386
7763 12:44:19.939361 TX Vref=34, minBit 8, minWin=22, winSum=381
7764 12:44:19.945410 [TxChooseVref] Worse bit 9, Min win 24, Win sum 407, Final Vref 28
7765 12:44:19.945508
7766 12:44:19.949056 Final TX Range 0 Vref 28
7767 12:44:19.949137
7768 12:44:19.949204 ==
7769 12:44:19.952297 Dram Type= 6, Freq= 0, CH_0, rank 0
7770 12:44:19.955500 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7771 12:44:19.955583 ==
7772 12:44:19.955649
7773 12:44:19.955712
7774 12:44:19.959003 TX Vref Scan disable
7775 12:44:19.965522 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7776 12:44:19.965622 == TX Byte 0 ==
7777 12:44:19.968928 u2DelayCellOfst[0]=15 cells (4 PI)
7778 12:44:19.972276 u2DelayCellOfst[1]=22 cells (6 PI)
7779 12:44:19.975410 u2DelayCellOfst[2]=15 cells (4 PI)
7780 12:44:19.978713 u2DelayCellOfst[3]=15 cells (4 PI)
7781 12:44:19.981609 u2DelayCellOfst[4]=11 cells (3 PI)
7782 12:44:19.985150 u2DelayCellOfst[5]=0 cells (0 PI)
7783 12:44:19.988568 u2DelayCellOfst[6]=22 cells (6 PI)
7784 12:44:19.991808 u2DelayCellOfst[7]=22 cells (6 PI)
7785 12:44:19.994897 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7786 12:44:19.998228 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7787 12:44:20.001452 == TX Byte 1 ==
7788 12:44:20.004893 u2DelayCellOfst[8]=0 cells (0 PI)
7789 12:44:20.008303 u2DelayCellOfst[9]=3 cells (1 PI)
7790 12:44:20.011677 u2DelayCellOfst[10]=7 cells (2 PI)
7791 12:44:20.014573 u2DelayCellOfst[11]=7 cells (2 PI)
7792 12:44:20.018173 u2DelayCellOfst[12]=15 cells (4 PI)
7793 12:44:20.021534 u2DelayCellOfst[13]=11 cells (3 PI)
7794 12:44:20.024425 u2DelayCellOfst[14]=15 cells (4 PI)
7795 12:44:20.027845 u2DelayCellOfst[15]=11 cells (3 PI)
7796 12:44:20.031097 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7797 12:44:20.034378 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7798 12:44:20.037872 DramC Write-DBI on
7799 12:44:20.037961 ==
7800 12:44:20.040919 Dram Type= 6, Freq= 0, CH_0, rank 0
7801 12:44:20.044314 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7802 12:44:20.044418 ==
7803 12:44:20.044515
7804 12:44:20.044606
7805 12:44:20.047766 TX Vref Scan disable
7806 12:44:20.050640 == TX Byte 0 ==
7807 12:44:20.053888 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7808 12:44:20.053993 == TX Byte 1 ==
7809 12:44:20.060801 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7810 12:44:20.060904 DramC Write-DBI off
7811 12:44:20.060973
7812 12:44:20.061035 [DATLAT]
7813 12:44:20.064123 Freq=1600, CH0 RK0
7814 12:44:20.064209
7815 12:44:20.066983 DATLAT Default: 0xf
7816 12:44:20.067078 0, 0xFFFF, sum = 0
7817 12:44:20.070319 1, 0xFFFF, sum = 0
7818 12:44:20.070438 2, 0xFFFF, sum = 0
7819 12:44:20.073873 3, 0xFFFF, sum = 0
7820 12:44:20.073953 4, 0xFFFF, sum = 0
7821 12:44:20.077232 5, 0xFFFF, sum = 0
7822 12:44:20.077314 6, 0xFFFF, sum = 0
7823 12:44:20.080174 7, 0xFFFF, sum = 0
7824 12:44:20.080252 8, 0xFFFF, sum = 0
7825 12:44:20.083537 9, 0xFFFF, sum = 0
7826 12:44:20.083615 10, 0xFFFF, sum = 0
7827 12:44:20.086984 11, 0xFFFF, sum = 0
7828 12:44:20.087062 12, 0xFFFF, sum = 0
7829 12:44:20.090059 13, 0xEFFF, sum = 0
7830 12:44:20.090132 14, 0x0, sum = 1
7831 12:44:20.093451 15, 0x0, sum = 2
7832 12:44:20.093559 16, 0x0, sum = 3
7833 12:44:20.096826 17, 0x0, sum = 4
7834 12:44:20.096903 best_step = 15
7835 12:44:20.096972
7836 12:44:20.097031 ==
7837 12:44:20.100085 Dram Type= 6, Freq= 0, CH_0, rank 0
7838 12:44:20.106573 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7839 12:44:20.106724 ==
7840 12:44:20.106839 RX Vref Scan: 1
7841 12:44:20.106933
7842 12:44:20.109967 Set Vref Range= 24 -> 127
7843 12:44:20.110086
7844 12:44:20.113569 RX Vref 24 -> 127, step: 1
7845 12:44:20.113673
7846 12:44:20.116514 RX Delay 11 -> 252, step: 4
7847 12:44:20.116618
7848 12:44:20.119695 Set Vref, RX VrefLevel [Byte0]: 24
7849 12:44:20.123210 [Byte1]: 24
7850 12:44:20.123292
7851 12:44:20.126753 Set Vref, RX VrefLevel [Byte0]: 25
7852 12:44:20.129719 [Byte1]: 25
7853 12:44:20.129841
7854 12:44:20.132933 Set Vref, RX VrefLevel [Byte0]: 26
7855 12:44:20.136270 [Byte1]: 26
7856 12:44:20.139828
7857 12:44:20.139935 Set Vref, RX VrefLevel [Byte0]: 27
7858 12:44:20.142743 [Byte1]: 27
7859 12:44:20.147440
7860 12:44:20.147555 Set Vref, RX VrefLevel [Byte0]: 28
7861 12:44:20.150999 [Byte1]: 28
7862 12:44:20.155142
7863 12:44:20.155248 Set Vref, RX VrefLevel [Byte0]: 29
7864 12:44:20.158393 [Byte1]: 29
7865 12:44:20.162463
7866 12:44:20.162577 Set Vref, RX VrefLevel [Byte0]: 30
7867 12:44:20.165852 [Byte1]: 30
7868 12:44:20.170184
7869 12:44:20.170302 Set Vref, RX VrefLevel [Byte0]: 31
7870 12:44:20.173412 [Byte1]: 31
7871 12:44:20.177971
7872 12:44:20.178082 Set Vref, RX VrefLevel [Byte0]: 32
7873 12:44:20.181128 [Byte1]: 32
7874 12:44:20.185194
7875 12:44:20.185305 Set Vref, RX VrefLevel [Byte0]: 33
7876 12:44:20.188750 [Byte1]: 33
7877 12:44:20.192806
7878 12:44:20.192898 Set Vref, RX VrefLevel [Byte0]: 34
7879 12:44:20.196412 [Byte1]: 34
7880 12:44:20.200354
7881 12:44:20.200445 Set Vref, RX VrefLevel [Byte0]: 35
7882 12:44:20.203820 [Byte1]: 35
7883 12:44:20.208170
7884 12:44:20.208316 Set Vref, RX VrefLevel [Byte0]: 36
7885 12:44:20.211442 [Byte1]: 36
7886 12:44:20.215920
7887 12:44:20.216020 Set Vref, RX VrefLevel [Byte0]: 37
7888 12:44:20.219272 [Byte1]: 37
7889 12:44:20.223440
7890 12:44:20.223535 Set Vref, RX VrefLevel [Byte0]: 38
7891 12:44:20.226702 [Byte1]: 38
7892 12:44:20.231332
7893 12:44:20.231432 Set Vref, RX VrefLevel [Byte0]: 39
7894 12:44:20.234137 [Byte1]: 39
7895 12:44:20.238628
7896 12:44:20.238722 Set Vref, RX VrefLevel [Byte0]: 40
7897 12:44:20.241964 [Byte1]: 40
7898 12:44:20.246032
7899 12:44:20.246128 Set Vref, RX VrefLevel [Byte0]: 41
7900 12:44:20.249666 [Byte1]: 41
7901 12:44:20.253672
7902 12:44:20.253779 Set Vref, RX VrefLevel [Byte0]: 42
7903 12:44:20.257203 [Byte1]: 42
7904 12:44:20.261624
7905 12:44:20.261731 Set Vref, RX VrefLevel [Byte0]: 43
7906 12:44:20.264585 [Byte1]: 43
7907 12:44:20.269222
7908 12:44:20.269315 Set Vref, RX VrefLevel [Byte0]: 44
7909 12:44:20.272134 [Byte1]: 44
7910 12:44:20.276573
7911 12:44:20.276666 Set Vref, RX VrefLevel [Byte0]: 45
7912 12:44:20.279926 [Byte1]: 45
7913 12:44:20.284246
7914 12:44:20.284340 Set Vref, RX VrefLevel [Byte0]: 46
7915 12:44:20.287929 [Byte1]: 46
7916 12:44:20.291807
7917 12:44:20.291899 Set Vref, RX VrefLevel [Byte0]: 47
7918 12:44:20.295339 [Byte1]: 47
7919 12:44:20.299771
7920 12:44:20.299861 Set Vref, RX VrefLevel [Byte0]: 48
7921 12:44:20.302813 [Byte1]: 48
7922 12:44:20.306815
7923 12:44:20.306934 Set Vref, RX VrefLevel [Byte0]: 49
7924 12:44:20.310223 [Byte1]: 49
7925 12:44:20.314810
7926 12:44:20.314947 Set Vref, RX VrefLevel [Byte0]: 50
7927 12:44:20.317798 [Byte1]: 50
7928 12:44:20.322684
7929 12:44:20.322808 Set Vref, RX VrefLevel [Byte0]: 51
7930 12:44:20.325933 [Byte1]: 51
7931 12:44:20.329678
7932 12:44:20.329763 Set Vref, RX VrefLevel [Byte0]: 52
7933 12:44:20.333438 [Byte1]: 52
7934 12:44:20.337767
7935 12:44:20.337852 Set Vref, RX VrefLevel [Byte0]: 53
7936 12:44:20.340987 [Byte1]: 53
7937 12:44:20.345240
7938 12:44:20.345331 Set Vref, RX VrefLevel [Byte0]: 54
7939 12:44:20.348164 [Byte1]: 54
7940 12:44:20.352903
7941 12:44:20.352985 Set Vref, RX VrefLevel [Byte0]: 55
7942 12:44:20.355840 [Byte1]: 55
7943 12:44:20.360621
7944 12:44:20.360709 Set Vref, RX VrefLevel [Byte0]: 56
7945 12:44:20.363367 [Byte1]: 56
7946 12:44:20.367963
7947 12:44:20.368052 Set Vref, RX VrefLevel [Byte0]: 57
7948 12:44:20.371788 [Byte1]: 57
7949 12:44:20.375328
7950 12:44:20.375411 Set Vref, RX VrefLevel [Byte0]: 58
7951 12:44:20.378968 [Byte1]: 58
7952 12:44:20.383548
7953 12:44:20.383637 Set Vref, RX VrefLevel [Byte0]: 59
7954 12:44:20.386858 [Byte1]: 59
7955 12:44:20.391040
7956 12:44:20.391139 Set Vref, RX VrefLevel [Byte0]: 60
7957 12:44:20.394017 [Byte1]: 60
7958 12:44:20.398528
7959 12:44:20.398629 Set Vref, RX VrefLevel [Byte0]: 61
7960 12:44:20.401943 [Byte1]: 61
7961 12:44:20.406100
7962 12:44:20.406193 Set Vref, RX VrefLevel [Byte0]: 62
7963 12:44:20.409684 [Byte1]: 62
7964 12:44:20.413693
7965 12:44:20.413781 Set Vref, RX VrefLevel [Byte0]: 63
7966 12:44:20.417043 [Byte1]: 63
7967 12:44:20.421197
7968 12:44:20.421282 Set Vref, RX VrefLevel [Byte0]: 64
7969 12:44:20.424529 [Byte1]: 64
7970 12:44:20.428850
7971 12:44:20.428944 Set Vref, RX VrefLevel [Byte0]: 65
7972 12:44:20.432155 [Byte1]: 65
7973 12:44:20.436336
7974 12:44:20.436421 Set Vref, RX VrefLevel [Byte0]: 66
7975 12:44:20.439606 [Byte1]: 66
7976 12:44:20.444348
7977 12:44:20.444480 Set Vref, RX VrefLevel [Byte0]: 67
7978 12:44:20.447401 [Byte1]: 67
7979 12:44:20.451748
7980 12:44:20.451842 Set Vref, RX VrefLevel [Byte0]: 68
7981 12:44:20.455104 [Byte1]: 68
7982 12:44:20.459171
7983 12:44:20.459262 Set Vref, RX VrefLevel [Byte0]: 69
7984 12:44:20.462716 [Byte1]: 69
7985 12:44:20.466841
7986 12:44:20.466930 Set Vref, RX VrefLevel [Byte0]: 70
7987 12:44:20.470158 [Byte1]: 70
7988 12:44:20.474782
7989 12:44:20.474910 Set Vref, RX VrefLevel [Byte0]: 71
7990 12:44:20.477687 [Byte1]: 71
7991 12:44:20.482050
7992 12:44:20.482160 Set Vref, RX VrefLevel [Byte0]: 72
7993 12:44:20.485562 [Byte1]: 72
7994 12:44:20.489991
7995 12:44:20.490085 Set Vref, RX VrefLevel [Byte0]: 73
7996 12:44:20.493178 [Byte1]: 73
7997 12:44:20.497635
7998 12:44:20.497730 Set Vref, RX VrefLevel [Byte0]: 74
7999 12:44:20.500894 [Byte1]: 74
8000 12:44:20.504943
8001 12:44:20.505034 Set Vref, RX VrefLevel [Byte0]: 75
8002 12:44:20.508458 [Byte1]: 75
8003 12:44:20.512529
8004 12:44:20.512623 Set Vref, RX VrefLevel [Byte0]: 76
8005 12:44:20.516043 [Byte1]: 76
8006 12:44:20.520151
8007 12:44:20.520242 Final RX Vref Byte 0 = 63 to rank0
8008 12:44:20.523606 Final RX Vref Byte 1 = 60 to rank0
8009 12:44:20.527227 Final RX Vref Byte 0 = 63 to rank1
8010 12:44:20.529916 Final RX Vref Byte 1 = 60 to rank1==
8011 12:44:20.533401 Dram Type= 6, Freq= 0, CH_0, rank 0
8012 12:44:20.540112 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8013 12:44:20.540219 ==
8014 12:44:20.540288 DQS Delay:
8015 12:44:20.543067 DQS0 = 0, DQS1 = 0
8016 12:44:20.543152 DQM Delay:
8017 12:44:20.543219 DQM0 = 126, DQM1 = 120
8018 12:44:20.546734 DQ Delay:
8019 12:44:20.549942 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
8020 12:44:20.553230 DQ4 =126, DQ5 =112, DQ6 =132, DQ7 =138
8021 12:44:20.556603 DQ8 =112, DQ9 =108, DQ10 =120, DQ11 =114
8022 12:44:20.559723 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
8023 12:44:20.559816
8024 12:44:20.559883
8025 12:44:20.559945
8026 12:44:20.562630 [DramC_TX_OE_Calibration] TA2
8027 12:44:20.566126 Original DQ_B0 (3 6) =30, OEN = 27
8028 12:44:20.569757 Original DQ_B1 (3 6) =30, OEN = 27
8029 12:44:20.572595 24, 0x0, End_B0=24 End_B1=24
8030 12:44:20.575998 25, 0x0, End_B0=25 End_B1=25
8031 12:44:20.576088 26, 0x0, End_B0=26 End_B1=26
8032 12:44:20.579472 27, 0x0, End_B0=27 End_B1=27
8033 12:44:20.582747 28, 0x0, End_B0=28 End_B1=28
8034 12:44:20.585952 29, 0x0, End_B0=29 End_B1=29
8035 12:44:20.589427 30, 0x0, End_B0=30 End_B1=30
8036 12:44:20.589520 31, 0x4545, End_B0=30 End_B1=30
8037 12:44:20.592798 Byte0 end_step=30 best_step=27
8038 12:44:20.595720 Byte1 end_step=30 best_step=27
8039 12:44:20.599147 Byte0 TX OE(2T, 0.5T) = (3, 3)
8040 12:44:20.602370 Byte1 TX OE(2T, 0.5T) = (3, 3)
8041 12:44:20.602479
8042 12:44:20.602561
8043 12:44:20.609041 [DQSOSCAuto] RK0, (LSB)MR18= 0x1313, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
8044 12:44:20.612542 CH0 RK0: MR19=303, MR18=1313
8045 12:44:20.618982 CH0_RK0: MR19=0x303, MR18=0x1313, DQSOSC=400, MR23=63, INC=23, DEC=15
8046 12:44:20.619087
8047 12:44:20.622221 ----->DramcWriteLeveling(PI) begin...
8048 12:44:20.622310 ==
8049 12:44:20.625753 Dram Type= 6, Freq= 0, CH_0, rank 1
8050 12:44:20.628658 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8051 12:44:20.628747 ==
8052 12:44:20.632207 Write leveling (Byte 0): 31 => 31
8053 12:44:20.635017 Write leveling (Byte 1): 29 => 29
8054 12:44:20.638427 DramcWriteLeveling(PI) end<-----
8055 12:44:20.638515
8056 12:44:20.638582 ==
8057 12:44:20.642304 Dram Type= 6, Freq= 0, CH_0, rank 1
8058 12:44:20.648590 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8059 12:44:20.648694 ==
8060 12:44:20.651814 [Gating] SW mode calibration
8061 12:44:20.658259 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8062 12:44:20.661370 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8063 12:44:20.668268 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8064 12:44:20.671137 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8065 12:44:20.674613 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8066 12:44:20.681513 1 4 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8067 12:44:20.684332 1 4 16 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
8068 12:44:20.687644 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8069 12:44:20.694302 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8070 12:44:20.697717 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8071 12:44:20.701308 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8072 12:44:20.707449 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8073 12:44:20.710794 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8074 12:44:20.714068 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
8075 12:44:20.721039 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8076 12:44:20.723959 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8077 12:44:20.727385 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 12:44:20.733761 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8079 12:44:20.737159 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8080 12:44:20.740510 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8081 12:44:20.746687 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8082 12:44:20.750007 1 6 12 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
8083 12:44:20.753281 1 6 16 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
8084 12:44:20.760169 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 12:44:20.763131 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 12:44:20.766623 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 12:44:20.773312 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 12:44:20.776454 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8089 12:44:20.779755 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8090 12:44:20.786317 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8091 12:44:20.789764 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8092 12:44:20.793134 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8093 12:44:20.799860 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 12:44:20.802763 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 12:44:20.806255 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 12:44:20.812971 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 12:44:20.816308 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 12:44:20.819563 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 12:44:20.826079 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 12:44:20.829192 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 12:44:20.832507 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 12:44:20.838972 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 12:44:20.842473 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 12:44:20.845926 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8105 12:44:20.852336 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8106 12:44:20.855846 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8107 12:44:20.858960 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8108 12:44:20.862133 Total UI for P1: 0, mck2ui 16
8109 12:44:20.865931 best dqsien dly found for B0: ( 1, 9, 8)
8110 12:44:20.872369 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8111 12:44:20.872525 Total UI for P1: 0, mck2ui 16
8112 12:44:20.878774 best dqsien dly found for B1: ( 1, 9, 16)
8113 12:44:20.882260 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8114 12:44:20.885075 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8115 12:44:20.885163
8116 12:44:20.888495 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8117 12:44:20.891793 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8118 12:44:20.895202 [Gating] SW calibration Done
8119 12:44:20.895292 ==
8120 12:44:20.898417 Dram Type= 6, Freq= 0, CH_0, rank 1
8121 12:44:20.901827 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8122 12:44:20.901918 ==
8123 12:44:20.905179 RX Vref Scan: 0
8124 12:44:20.905268
8125 12:44:20.905336 RX Vref 0 -> 0, step: 1
8126 12:44:20.908313
8127 12:44:20.908439 RX Delay 0 -> 252, step: 8
8128 12:44:20.915139 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8129 12:44:20.918064 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8130 12:44:20.921847 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8131 12:44:20.925237 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8132 12:44:20.927935 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8133 12:44:20.934783 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8134 12:44:20.938343 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8135 12:44:20.941438 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8136 12:44:20.944885 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8137 12:44:20.947940 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8138 12:44:20.954501 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8139 12:44:20.958020 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8140 12:44:20.961027 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8141 12:44:20.964444 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8142 12:44:20.967794 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8143 12:44:20.974249 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8144 12:44:20.974356 ==
8145 12:44:20.977505 Dram Type= 6, Freq= 0, CH_0, rank 1
8146 12:44:20.980827 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8147 12:44:20.980919 ==
8148 12:44:20.980988 DQS Delay:
8149 12:44:20.984106 DQS0 = 0, DQS1 = 0
8150 12:44:20.984191 DQM Delay:
8151 12:44:20.987283 DQM0 = 128, DQM1 = 121
8152 12:44:20.987368 DQ Delay:
8153 12:44:20.990596 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8154 12:44:20.993980 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8155 12:44:20.997432 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8156 12:44:21.004230 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8157 12:44:21.004337
8158 12:44:21.004405
8159 12:44:21.004467 ==
8160 12:44:21.007687 Dram Type= 6, Freq= 0, CH_0, rank 1
8161 12:44:21.010566 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8162 12:44:21.010656 ==
8163 12:44:21.010723
8164 12:44:21.010785
8165 12:44:21.013980 TX Vref Scan disable
8166 12:44:21.014064 == TX Byte 0 ==
8167 12:44:21.020321 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8168 12:44:21.023773 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8169 12:44:21.023864 == TX Byte 1 ==
8170 12:44:21.030386 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8171 12:44:21.033718 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8172 12:44:21.033810 ==
8173 12:44:21.036604 Dram Type= 6, Freq= 0, CH_0, rank 1
8174 12:44:21.040080 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8175 12:44:21.040166 ==
8176 12:44:21.055171
8177 12:44:21.058566 TX Vref early break, caculate TX vref
8178 12:44:21.061524 TX Vref=16, minBit 8, minWin=21, winSum=367
8179 12:44:21.064956 TX Vref=18, minBit 8, minWin=22, winSum=376
8180 12:44:21.068471 TX Vref=20, minBit 0, minWin=23, winSum=385
8181 12:44:21.071932 TX Vref=22, minBit 0, minWin=24, winSum=399
8182 12:44:21.074835 TX Vref=24, minBit 0, minWin=25, winSum=406
8183 12:44:21.081826 TX Vref=26, minBit 1, minWin=24, winSum=405
8184 12:44:21.084909 TX Vref=28, minBit 8, minWin=25, winSum=411
8185 12:44:21.088075 TX Vref=30, minBit 8, minWin=24, winSum=411
8186 12:44:21.091197 TX Vref=32, minBit 8, minWin=24, winSum=402
8187 12:44:21.094966 TX Vref=34, minBit 8, minWin=23, winSum=394
8188 12:44:21.101501 TX Vref=36, minBit 8, minWin=23, winSum=386
8189 12:44:21.104830 [TxChooseVref] Worse bit 8, Min win 25, Win sum 411, Final Vref 28
8190 12:44:21.104924
8191 12:44:21.108120 Final TX Range 0 Vref 28
8192 12:44:21.108206
8193 12:44:21.108270 ==
8194 12:44:21.110922 Dram Type= 6, Freq= 0, CH_0, rank 1
8195 12:44:21.114418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8196 12:44:21.118038 ==
8197 12:44:21.118122
8198 12:44:21.118191
8199 12:44:21.118252 TX Vref Scan disable
8200 12:44:21.124701 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8201 12:44:21.124796 == TX Byte 0 ==
8202 12:44:21.127923 u2DelayCellOfst[0]=15 cells (4 PI)
8203 12:44:21.131247 u2DelayCellOfst[1]=22 cells (6 PI)
8204 12:44:21.134559 u2DelayCellOfst[2]=15 cells (4 PI)
8205 12:44:21.137706 u2DelayCellOfst[3]=15 cells (4 PI)
8206 12:44:21.141105 u2DelayCellOfst[4]=11 cells (3 PI)
8207 12:44:21.144462 u2DelayCellOfst[5]=0 cells (0 PI)
8208 12:44:21.147357 u2DelayCellOfst[6]=22 cells (6 PI)
8209 12:44:21.150726 u2DelayCellOfst[7]=22 cells (6 PI)
8210 12:44:21.154367 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8211 12:44:21.157700 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
8212 12:44:21.160547 == TX Byte 1 ==
8213 12:44:21.164027 u2DelayCellOfst[8]=0 cells (0 PI)
8214 12:44:21.167529 u2DelayCellOfst[9]=0 cells (0 PI)
8215 12:44:21.170939 u2DelayCellOfst[10]=7 cells (2 PI)
8216 12:44:21.174112 u2DelayCellOfst[11]=3 cells (1 PI)
8217 12:44:21.177466 u2DelayCellOfst[12]=11 cells (3 PI)
8218 12:44:21.180390 u2DelayCellOfst[13]=11 cells (3 PI)
8219 12:44:21.183588 u2DelayCellOfst[14]=15 cells (4 PI)
8220 12:44:21.183674 u2DelayCellOfst[15]=7 cells (2 PI)
8221 12:44:21.190348 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8222 12:44:21.193537 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8223 12:44:21.197006 DramC Write-DBI on
8224 12:44:21.197090 ==
8225 12:44:21.200248 Dram Type= 6, Freq= 0, CH_0, rank 1
8226 12:44:21.203255 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8227 12:44:21.203336 ==
8228 12:44:21.203401
8229 12:44:21.203466
8230 12:44:21.206609 TX Vref Scan disable
8231 12:44:21.206687 == TX Byte 0 ==
8232 12:44:21.213398 Update DQM dly =731 (2 ,6, 27) DQM OEN =(3 ,3)
8233 12:44:21.213513 == TX Byte 1 ==
8234 12:44:21.220069 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8235 12:44:21.220174 DramC Write-DBI off
8236 12:44:21.220243
8237 12:44:21.220306 [DATLAT]
8238 12:44:21.223091 Freq=1600, CH0 RK1
8239 12:44:21.223167
8240 12:44:21.226651 DATLAT Default: 0xf
8241 12:44:21.226753 0, 0xFFFF, sum = 0
8242 12:44:21.229578 1, 0xFFFF, sum = 0
8243 12:44:21.229654 2, 0xFFFF, sum = 0
8244 12:44:21.232928 3, 0xFFFF, sum = 0
8245 12:44:21.233007 4, 0xFFFF, sum = 0
8246 12:44:21.236468 5, 0xFFFF, sum = 0
8247 12:44:21.236548 6, 0xFFFF, sum = 0
8248 12:44:21.239702 7, 0xFFFF, sum = 0
8249 12:44:21.239783 8, 0xFFFF, sum = 0
8250 12:44:21.242559 9, 0xFFFF, sum = 0
8251 12:44:21.242640 10, 0xFFFF, sum = 0
8252 12:44:21.246169 11, 0xFFFF, sum = 0
8253 12:44:21.246248 12, 0xFFFF, sum = 0
8254 12:44:21.249574 13, 0xCFFF, sum = 0
8255 12:44:21.249654 14, 0x0, sum = 1
8256 12:44:21.252521 15, 0x0, sum = 2
8257 12:44:21.252598 16, 0x0, sum = 3
8258 12:44:21.256024 17, 0x0, sum = 4
8259 12:44:21.256101 best_step = 15
8260 12:44:21.256168
8261 12:44:21.256227 ==
8262 12:44:21.258941 Dram Type= 6, Freq= 0, CH_0, rank 1
8263 12:44:21.265894 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8264 12:44:21.266030 ==
8265 12:44:21.266103 RX Vref Scan: 0
8266 12:44:21.266165
8267 12:44:21.269108 RX Vref 0 -> 0, step: 1
8268 12:44:21.269184
8269 12:44:21.272755 RX Delay 3 -> 252, step: 4
8270 12:44:21.275530 iDelay=191, Bit 0, Center 122 (67 ~ 178) 112
8271 12:44:21.278984 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8272 12:44:21.285631 iDelay=191, Bit 2, Center 120 (67 ~ 174) 108
8273 12:44:21.289060 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8274 12:44:21.292354 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8275 12:44:21.295662 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8276 12:44:21.298804 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8277 12:44:21.305260 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8278 12:44:21.308546 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8279 12:44:21.311813 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8280 12:44:21.315011 iDelay=191, Bit 10, Center 116 (59 ~ 174) 116
8281 12:44:21.321386 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8282 12:44:21.324764 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8283 12:44:21.328285 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8284 12:44:21.331791 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8285 12:44:21.334716 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8286 12:44:21.338265 ==
8287 12:44:21.341120 Dram Type= 6, Freq= 0, CH_0, rank 1
8288 12:44:21.344466 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8289 12:44:21.344611 ==
8290 12:44:21.344714 DQS Delay:
8291 12:44:21.347807 DQS0 = 0, DQS1 = 0
8292 12:44:21.347889 DQM Delay:
8293 12:44:21.350942 DQM0 = 124, DQM1 = 117
8294 12:44:21.351021 DQ Delay:
8295 12:44:21.354654 DQ0 =122, DQ1 =126, DQ2 =120, DQ3 =122
8296 12:44:21.357804 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8297 12:44:21.360853 DQ8 =110, DQ9 =104, DQ10 =116, DQ11 =112
8298 12:44:21.364588 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8299 12:44:21.364691
8300 12:44:21.364760
8301 12:44:21.364827
8302 12:44:21.367550 [DramC_TX_OE_Calibration] TA2
8303 12:44:21.371018 Original DQ_B0 (3 6) =30, OEN = 27
8304 12:44:21.374348 Original DQ_B1 (3 6) =30, OEN = 27
8305 12:44:21.377326 24, 0x0, End_B0=24 End_B1=24
8306 12:44:21.380804 25, 0x0, End_B0=25 End_B1=25
8307 12:44:21.384357 26, 0x0, End_B0=26 End_B1=26
8308 12:44:21.384451 27, 0x0, End_B0=27 End_B1=27
8309 12:44:21.387330 28, 0x0, End_B0=28 End_B1=28
8310 12:44:21.390845 29, 0x0, End_B0=29 End_B1=29
8311 12:44:21.393761 30, 0x0, End_B0=30 End_B1=30
8312 12:44:21.397124 31, 0x5151, End_B0=30 End_B1=30
8313 12:44:21.397216 Byte0 end_step=30 best_step=27
8314 12:44:21.400420 Byte1 end_step=30 best_step=27
8315 12:44:21.403678 Byte0 TX OE(2T, 0.5T) = (3, 3)
8316 12:44:21.407326 Byte1 TX OE(2T, 0.5T) = (3, 3)
8317 12:44:21.407418
8318 12:44:21.407492
8319 12:44:21.413666 [DQSOSCAuto] RK1, (LSB)MR18= 0x2613, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
8320 12:44:21.417240 CH0 RK1: MR19=303, MR18=2613
8321 12:44:21.423817 CH0_RK1: MR19=0x303, MR18=0x2613, DQSOSC=390, MR23=63, INC=24, DEC=16
8322 12:44:21.427145 [RxdqsGatingPostProcess] freq 1600
8323 12:44:21.433734 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8324 12:44:21.437201 best DQS0 dly(2T, 0.5T) = (1, 1)
8325 12:44:21.439946 best DQS1 dly(2T, 0.5T) = (1, 1)
8326 12:44:21.443516 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8327 12:44:21.443610 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8328 12:44:21.446745 best DQS0 dly(2T, 0.5T) = (1, 1)
8329 12:44:21.450075 best DQS1 dly(2T, 0.5T) = (1, 1)
8330 12:44:21.453489 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8331 12:44:21.456398 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8332 12:44:21.459782 Pre-setting of DQS Precalculation
8333 12:44:21.466233 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8334 12:44:21.466347 ==
8335 12:44:21.469575 Dram Type= 6, Freq= 0, CH_1, rank 0
8336 12:44:21.473179 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8337 12:44:21.473272 ==
8338 12:44:21.479620 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8339 12:44:21.483099 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8340 12:44:21.486101 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8341 12:44:21.493111 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8342 12:44:21.501863 [CA 0] Center 41 (13~70) winsize 58
8343 12:44:21.505215 [CA 1] Center 42 (12~72) winsize 61
8344 12:44:21.507985 [CA 2] Center 37 (8~66) winsize 59
8345 12:44:21.511511 [CA 3] Center 36 (7~66) winsize 60
8346 12:44:21.515042 [CA 4] Center 37 (8~67) winsize 60
8347 12:44:21.517806 [CA 5] Center 36 (7~66) winsize 60
8348 12:44:21.517895
8349 12:44:21.521225 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8350 12:44:21.521315
8351 12:44:21.528060 [CATrainingPosCal] consider 1 rank data
8352 12:44:21.528166 u2DelayCellTimex100 = 258/100 ps
8353 12:44:21.534589 CA0 delay=41 (13~70),Diff = 5 PI (18 cell)
8354 12:44:21.537958 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8355 12:44:21.540933 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8356 12:44:21.544408 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8357 12:44:21.547583 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8358 12:44:21.551060 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8359 12:44:21.551149
8360 12:44:21.554296 CA PerBit enable=1, Macro0, CA PI delay=36
8361 12:44:21.554378
8362 12:44:21.557248 [CBTSetCACLKResult] CA Dly = 36
8363 12:44:21.560669 CS Dly: 9 (0~40)
8364 12:44:21.563958 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8365 12:44:21.567155 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8366 12:44:21.567233 ==
8367 12:44:21.570418 Dram Type= 6, Freq= 0, CH_1, rank 1
8368 12:44:21.577178 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8369 12:44:21.577285 ==
8370 12:44:21.580358 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8371 12:44:21.586974 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8372 12:44:21.590586 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8373 12:44:21.596953 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8374 12:44:21.604654 [CA 0] Center 42 (13~71) winsize 59
8375 12:44:21.608030 [CA 1] Center 42 (12~72) winsize 61
8376 12:44:21.611354 [CA 2] Center 38 (9~67) winsize 59
8377 12:44:21.614620 [CA 3] Center 36 (7~66) winsize 60
8378 12:44:21.617820 [CA 4] Center 38 (8~68) winsize 61
8379 12:44:21.621114 [CA 5] Center 36 (6~67) winsize 62
8380 12:44:21.621204
8381 12:44:21.625071 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8382 12:44:21.625159
8383 12:44:21.631440 [CATrainingPosCal] consider 2 rank data
8384 12:44:21.631537 u2DelayCellTimex100 = 258/100 ps
8385 12:44:21.637639 CA0 delay=41 (13~70),Diff = 5 PI (18 cell)
8386 12:44:21.640783 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8387 12:44:21.644169 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8388 12:44:21.647859 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8389 12:44:21.650890 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8390 12:44:21.654319 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8391 12:44:21.654407
8392 12:44:21.657371 CA PerBit enable=1, Macro0, CA PI delay=36
8393 12:44:21.657454
8394 12:44:21.660739 [CBTSetCACLKResult] CA Dly = 36
8395 12:44:21.664170 CS Dly: 11 (0~44)
8396 12:44:21.667119 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8397 12:44:21.670347 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8398 12:44:21.670434
8399 12:44:21.673840 ----->DramcWriteLeveling(PI) begin...
8400 12:44:21.673925 ==
8401 12:44:21.677298 Dram Type= 6, Freq= 0, CH_1, rank 0
8402 12:44:21.683906 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8403 12:44:21.684011 ==
8404 12:44:21.687143 Write leveling (Byte 0): 24 => 24
8405 12:44:21.690297 Write leveling (Byte 1): 30 => 30
8406 12:44:21.693809 DramcWriteLeveling(PI) end<-----
8407 12:44:21.693898
8408 12:44:21.693963 ==
8409 12:44:21.696777 Dram Type= 6, Freq= 0, CH_1, rank 0
8410 12:44:21.700221 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8411 12:44:21.700305 ==
8412 12:44:21.703821 [Gating] SW mode calibration
8413 12:44:21.710419 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8414 12:44:21.716901 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8415 12:44:21.720283 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8416 12:44:21.723532 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8417 12:44:21.726974 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8418 12:44:21.733264 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8419 12:44:21.736658 1 4 16 | B1->B0 | 3434 3333 | 0 0 | (0 0) (1 1)
8420 12:44:21.739939 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8421 12:44:21.746503 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8422 12:44:21.749966 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8423 12:44:21.753023 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8424 12:44:21.759658 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8425 12:44:21.762786 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8426 12:44:21.766210 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8427 12:44:21.772749 1 5 16 | B1->B0 | 2a2a 2b2b | 0 0 | (1 0) (0 0)
8428 12:44:21.776060 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8429 12:44:21.779573 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8430 12:44:21.785957 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8431 12:44:21.789826 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8432 12:44:21.793168 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8433 12:44:21.799317 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8434 12:44:21.803038 1 6 12 | B1->B0 | 2525 2424 | 0 1 | (0 0) (0 0)
8435 12:44:21.805885 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8436 12:44:21.812479 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8437 12:44:21.815908 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 12:44:21.819395 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8439 12:44:21.826033 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8440 12:44:21.829268 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8441 12:44:21.832430 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8442 12:44:21.839280 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8443 12:44:21.842649 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8444 12:44:21.845481 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8445 12:44:21.852149 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 12:44:21.855526 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 12:44:21.858968 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 12:44:21.865516 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 12:44:21.868386 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 12:44:21.871899 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 12:44:21.878756 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 12:44:21.881606 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 12:44:21.885401 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 12:44:21.891796 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 12:44:21.895389 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 12:44:21.898155 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 12:44:21.904726 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8458 12:44:21.908171 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8459 12:44:21.911727 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8460 12:44:21.918058 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8461 12:44:21.921665 Total UI for P1: 0, mck2ui 16
8462 12:44:21.924552 best dqsien dly found for B0: ( 1, 9, 14)
8463 12:44:21.928138 Total UI for P1: 0, mck2ui 16
8464 12:44:21.931270 best dqsien dly found for B1: ( 1, 9, 14)
8465 12:44:21.934657 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8466 12:44:21.937942 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8467 12:44:21.938036
8468 12:44:21.941306 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8469 12:44:21.944431 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8470 12:44:21.947868 [Gating] SW calibration Done
8471 12:44:21.947964 ==
8472 12:44:21.951014 Dram Type= 6, Freq= 0, CH_1, rank 0
8473 12:44:21.954214 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8474 12:44:21.954304 ==
8475 12:44:21.957501 RX Vref Scan: 0
8476 12:44:21.957588
8477 12:44:21.960899 RX Vref 0 -> 0, step: 1
8478 12:44:21.960985
8479 12:44:21.961053 RX Delay 0 -> 252, step: 8
8480 12:44:21.967422 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8481 12:44:21.970898 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8482 12:44:21.973805 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8483 12:44:21.977300 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8484 12:44:21.980778 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8485 12:44:21.987150 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8486 12:44:21.990722 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8487 12:44:21.994072 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8488 12:44:21.997027 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8489 12:44:22.000554 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8490 12:44:22.006747 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8491 12:44:22.010062 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8492 12:44:22.013497 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8493 12:44:22.017221 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8494 12:44:22.023524 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8495 12:44:22.026495 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8496 12:44:22.026622 ==
8497 12:44:22.030027 Dram Type= 6, Freq= 0, CH_1, rank 0
8498 12:44:22.033404 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8499 12:44:22.033529 ==
8500 12:44:22.036555 DQS Delay:
8501 12:44:22.036660 DQS0 = 0, DQS1 = 0
8502 12:44:22.036759 DQM Delay:
8503 12:44:22.039542 DQM0 = 131, DQM1 = 126
8504 12:44:22.039648 DQ Delay:
8505 12:44:22.042960 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8506 12:44:22.046126 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8507 12:44:22.053158 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8508 12:44:22.056447 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8509 12:44:22.056541
8510 12:44:22.056624
8511 12:44:22.056700 ==
8512 12:44:22.059735 Dram Type= 6, Freq= 0, CH_1, rank 0
8513 12:44:22.062939 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8514 12:44:22.063039 ==
8515 12:44:22.063110
8516 12:44:22.063172
8517 12:44:22.066218 TX Vref Scan disable
8518 12:44:22.069778 == TX Byte 0 ==
8519 12:44:22.072735 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8520 12:44:22.076260 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8521 12:44:22.079161 == TX Byte 1 ==
8522 12:44:22.082762 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8523 12:44:22.086253 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8524 12:44:22.086347 ==
8525 12:44:22.089629 Dram Type= 6, Freq= 0, CH_1, rank 0
8526 12:44:22.092607 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8527 12:44:22.095889 ==
8528 12:44:22.107210
8529 12:44:22.110642 TX Vref early break, caculate TX vref
8530 12:44:22.114184 TX Vref=16, minBit 8, minWin=20, winSum=357
8531 12:44:22.117269 TX Vref=18, minBit 11, minWin=21, winSum=369
8532 12:44:22.120987 TX Vref=20, minBit 8, minWin=22, winSum=379
8533 12:44:22.123759 TX Vref=22, minBit 8, minWin=22, winSum=386
8534 12:44:22.127211 TX Vref=24, minBit 4, minWin=24, winSum=393
8535 12:44:22.133551 TX Vref=26, minBit 8, minWin=25, winSum=412
8536 12:44:22.136958 TX Vref=28, minBit 0, minWin=25, winSum=413
8537 12:44:22.140341 TX Vref=30, minBit 9, minWin=23, winSum=402
8538 12:44:22.143771 TX Vref=32, minBit 9, minWin=23, winSum=397
8539 12:44:22.146998 TX Vref=34, minBit 0, minWin=23, winSum=386
8540 12:44:22.153435 [TxChooseVref] Worse bit 0, Min win 25, Win sum 413, Final Vref 28
8541 12:44:22.153543
8542 12:44:22.156735 Final TX Range 0 Vref 28
8543 12:44:22.156824
8544 12:44:22.156890 ==
8545 12:44:22.160205 Dram Type= 6, Freq= 0, CH_1, rank 0
8546 12:44:22.163405 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8547 12:44:22.163494 ==
8548 12:44:22.163562
8549 12:44:22.163622
8550 12:44:22.166539 TX Vref Scan disable
8551 12:44:22.172954 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8552 12:44:22.173054 == TX Byte 0 ==
8553 12:44:22.176494 u2DelayCellOfst[0]=22 cells (6 PI)
8554 12:44:22.179964 u2DelayCellOfst[1]=15 cells (4 PI)
8555 12:44:22.183447 u2DelayCellOfst[2]=0 cells (0 PI)
8556 12:44:22.186411 u2DelayCellOfst[3]=7 cells (2 PI)
8557 12:44:22.189903 u2DelayCellOfst[4]=11 cells (3 PI)
8558 12:44:22.192802 u2DelayCellOfst[5]=22 cells (6 PI)
8559 12:44:22.196408 u2DelayCellOfst[6]=22 cells (6 PI)
8560 12:44:22.199970 u2DelayCellOfst[7]=7 cells (2 PI)
8561 12:44:22.202973 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8562 12:44:22.206337 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8563 12:44:22.209737 == TX Byte 1 ==
8564 12:44:22.212850 u2DelayCellOfst[8]=0 cells (0 PI)
8565 12:44:22.216234 u2DelayCellOfst[9]=7 cells (2 PI)
8566 12:44:22.219501 u2DelayCellOfst[10]=11 cells (3 PI)
8567 12:44:22.222808 u2DelayCellOfst[11]=7 cells (2 PI)
8568 12:44:22.222937 u2DelayCellOfst[12]=15 cells (4 PI)
8569 12:44:22.226207 u2DelayCellOfst[13]=15 cells (4 PI)
8570 12:44:22.229229 u2DelayCellOfst[14]=15 cells (4 PI)
8571 12:44:22.232757 u2DelayCellOfst[15]=15 cells (4 PI)
8572 12:44:22.239104 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8573 12:44:22.242528 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8574 12:44:22.242625 DramC Write-DBI on
8575 12:44:22.245497 ==
8576 12:44:22.248967 Dram Type= 6, Freq= 0, CH_1, rank 0
8577 12:44:22.252207 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8578 12:44:22.252297 ==
8579 12:44:22.252384
8580 12:44:22.252464
8581 12:44:22.255364 TX Vref Scan disable
8582 12:44:22.255450 == TX Byte 0 ==
8583 12:44:22.262788 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8584 12:44:22.262909 == TX Byte 1 ==
8585 12:44:22.265519 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8586 12:44:22.268809 DramC Write-DBI off
8587 12:44:22.268897
8588 12:44:22.268963 [DATLAT]
8589 12:44:22.272106 Freq=1600, CH1 RK0
8590 12:44:22.272191
8591 12:44:22.272257 DATLAT Default: 0xf
8592 12:44:22.275368 0, 0xFFFF, sum = 0
8593 12:44:22.275453 1, 0xFFFF, sum = 0
8594 12:44:22.278448 2, 0xFFFF, sum = 0
8595 12:44:22.278538 3, 0xFFFF, sum = 0
8596 12:44:22.282115 4, 0xFFFF, sum = 0
8597 12:44:22.282206 5, 0xFFFF, sum = 0
8598 12:44:22.285053 6, 0xFFFF, sum = 0
8599 12:44:22.288624 7, 0xFFFF, sum = 0
8600 12:44:22.288714 8, 0xFFFF, sum = 0
8601 12:44:22.292026 9, 0xFFFF, sum = 0
8602 12:44:22.292115 10, 0xFFFF, sum = 0
8603 12:44:22.295069 11, 0xFFFF, sum = 0
8604 12:44:22.295175 12, 0xFFFF, sum = 0
8605 12:44:22.298711 13, 0x8FFF, sum = 0
8606 12:44:22.298798 14, 0x0, sum = 1
8607 12:44:22.301475 15, 0x0, sum = 2
8608 12:44:22.301562 16, 0x0, sum = 3
8609 12:44:22.304962 17, 0x0, sum = 4
8610 12:44:22.305053 best_step = 15
8611 12:44:22.305139
8612 12:44:22.305219 ==
8613 12:44:22.308448 Dram Type= 6, Freq= 0, CH_1, rank 0
8614 12:44:22.311780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8615 12:44:22.315122 ==
8616 12:44:22.315216 RX Vref Scan: 1
8617 12:44:22.315301
8618 12:44:22.317950 Set Vref Range= 24 -> 127
8619 12:44:22.318035
8620 12:44:22.321794 RX Vref 24 -> 127, step: 1
8621 12:44:22.321882
8622 12:44:22.321967 RX Delay 11 -> 252, step: 4
8623 12:44:22.322048
8624 12:44:22.325035 Set Vref, RX VrefLevel [Byte0]: 24
8625 12:44:22.328335 [Byte1]: 24
8626 12:44:22.332202
8627 12:44:22.332293 Set Vref, RX VrefLevel [Byte0]: 25
8628 12:44:22.335206 [Byte1]: 25
8629 12:44:22.339705
8630 12:44:22.339795 Set Vref, RX VrefLevel [Byte0]: 26
8631 12:44:22.342661 [Byte1]: 26
8632 12:44:22.347273
8633 12:44:22.347367 Set Vref, RX VrefLevel [Byte0]: 27
8634 12:44:22.350731 [Byte1]: 27
8635 12:44:22.354793
8636 12:44:22.354892 Set Vref, RX VrefLevel [Byte0]: 28
8637 12:44:22.358360 [Byte1]: 28
8638 12:44:22.362188
8639 12:44:22.362278 Set Vref, RX VrefLevel [Byte0]: 29
8640 12:44:22.365938 [Byte1]: 29
8641 12:44:22.370224
8642 12:44:22.370316 Set Vref, RX VrefLevel [Byte0]: 30
8643 12:44:22.373378 [Byte1]: 30
8644 12:44:22.377900
8645 12:44:22.377992 Set Vref, RX VrefLevel [Byte0]: 31
8646 12:44:22.380705 [Byte1]: 31
8647 12:44:22.385254
8648 12:44:22.385351 Set Vref, RX VrefLevel [Byte0]: 32
8649 12:44:22.388794 [Byte1]: 32
8650 12:44:22.392828
8651 12:44:22.392919 Set Vref, RX VrefLevel [Byte0]: 33
8652 12:44:22.396287 [Byte1]: 33
8653 12:44:22.400332
8654 12:44:22.400423 Set Vref, RX VrefLevel [Byte0]: 34
8655 12:44:22.403758 [Byte1]: 34
8656 12:44:22.407819
8657 12:44:22.407911 Set Vref, RX VrefLevel [Byte0]: 35
8658 12:44:22.414720 [Byte1]: 35
8659 12:44:22.414836
8660 12:44:22.418131 Set Vref, RX VrefLevel [Byte0]: 36
8661 12:44:22.421185 [Byte1]: 36
8662 12:44:22.421272
8663 12:44:22.424345 Set Vref, RX VrefLevel [Byte0]: 37
8664 12:44:22.427857 [Byte1]: 37
8665 12:44:22.431175
8666 12:44:22.431268 Set Vref, RX VrefLevel [Byte0]: 38
8667 12:44:22.434377 [Byte1]: 38
8668 12:44:22.438753
8669 12:44:22.438873 Set Vref, RX VrefLevel [Byte0]: 39
8670 12:44:22.441670 [Byte1]: 39
8671 12:44:22.446333
8672 12:44:22.446427 Set Vref, RX VrefLevel [Byte0]: 40
8673 12:44:22.449269 [Byte1]: 40
8674 12:44:22.453999
8675 12:44:22.454089 Set Vref, RX VrefLevel [Byte0]: 41
8676 12:44:22.456987 [Byte1]: 41
8677 12:44:22.461545
8678 12:44:22.461634 Set Vref, RX VrefLevel [Byte0]: 42
8679 12:44:22.465181 [Byte1]: 42
8680 12:44:22.469073
8681 12:44:22.469160 Set Vref, RX VrefLevel [Byte0]: 43
8682 12:44:22.472104 [Byte1]: 43
8683 12:44:22.476389
8684 12:44:22.476499 Set Vref, RX VrefLevel [Byte0]: 44
8685 12:44:22.479697 [Byte1]: 44
8686 12:44:22.484634
8687 12:44:22.484735 Set Vref, RX VrefLevel [Byte0]: 45
8688 12:44:22.487493 [Byte1]: 45
8689 12:44:22.491789
8690 12:44:22.491881 Set Vref, RX VrefLevel [Byte0]: 46
8691 12:44:22.494968 [Byte1]: 46
8692 12:44:22.499458
8693 12:44:22.499555 Set Vref, RX VrefLevel [Byte0]: 47
8694 12:44:22.502805 [Byte1]: 47
8695 12:44:22.506934
8696 12:44:22.507026 Set Vref, RX VrefLevel [Byte0]: 48
8697 12:44:22.510387 [Byte1]: 48
8698 12:44:22.515033
8699 12:44:22.515135 Set Vref, RX VrefLevel [Byte0]: 49
8700 12:44:22.517842 [Byte1]: 49
8701 12:44:22.522427
8702 12:44:22.522521 Set Vref, RX VrefLevel [Byte0]: 50
8703 12:44:22.526033 [Byte1]: 50
8704 12:44:22.529835
8705 12:44:22.529924 Set Vref, RX VrefLevel [Byte0]: 51
8706 12:44:22.533304 [Byte1]: 51
8707 12:44:22.537760
8708 12:44:22.537850 Set Vref, RX VrefLevel [Byte0]: 52
8709 12:44:22.541011 [Byte1]: 52
8710 12:44:22.545302
8711 12:44:22.545394 Set Vref, RX VrefLevel [Byte0]: 53
8712 12:44:22.548217 [Byte1]: 53
8713 12:44:22.552761
8714 12:44:22.552852 Set Vref, RX VrefLevel [Byte0]: 54
8715 12:44:22.556298 [Byte1]: 54
8716 12:44:22.560286
8717 12:44:22.560374 Set Vref, RX VrefLevel [Byte0]: 55
8718 12:44:22.563875 [Byte1]: 55
8719 12:44:22.567925
8720 12:44:22.568016 Set Vref, RX VrefLevel [Byte0]: 56
8721 12:44:22.571429 [Byte1]: 56
8722 12:44:22.575522
8723 12:44:22.575613 Set Vref, RX VrefLevel [Byte0]: 57
8724 12:44:22.578777 [Byte1]: 57
8725 12:44:22.582982
8726 12:44:22.583076 Set Vref, RX VrefLevel [Byte0]: 58
8727 12:44:22.587054 [Byte1]: 58
8728 12:44:22.591089
8729 12:44:22.591181 Set Vref, RX VrefLevel [Byte0]: 59
8730 12:44:22.594081 [Byte1]: 59
8731 12:44:22.598384
8732 12:44:22.598477 Set Vref, RX VrefLevel [Byte0]: 60
8733 12:44:22.601952 [Byte1]: 60
8734 12:44:22.606611
8735 12:44:22.606715 Set Vref, RX VrefLevel [Byte0]: 61
8736 12:44:22.609426 [Byte1]: 61
8737 12:44:22.613564
8738 12:44:22.613664 Set Vref, RX VrefLevel [Byte0]: 62
8739 12:44:22.617151 [Byte1]: 62
8740 12:44:22.621080
8741 12:44:22.621173 Set Vref, RX VrefLevel [Byte0]: 63
8742 12:44:22.624499 [Byte1]: 63
8743 12:44:22.628783
8744 12:44:22.628875 Set Vref, RX VrefLevel [Byte0]: 64
8745 12:44:22.632013 [Byte1]: 64
8746 12:44:22.636781
8747 12:44:22.636876 Set Vref, RX VrefLevel [Byte0]: 65
8748 12:44:22.639673 [Byte1]: 65
8749 12:44:22.644061
8750 12:44:22.644154 Set Vref, RX VrefLevel [Byte0]: 66
8751 12:44:22.647389 [Byte1]: 66
8752 12:44:22.651648
8753 12:44:22.651742 Set Vref, RX VrefLevel [Byte0]: 67
8754 12:44:22.655115 [Byte1]: 67
8755 12:44:22.659089
8756 12:44:22.659182 Set Vref, RX VrefLevel [Byte0]: 68
8757 12:44:22.662989 [Byte1]: 68
8758 12:44:22.666729
8759 12:44:22.666856 Set Vref, RX VrefLevel [Byte0]: 69
8760 12:44:22.670229 [Byte1]: 69
8761 12:44:22.674367
8762 12:44:22.674457 Set Vref, RX VrefLevel [Byte0]: 70
8763 12:44:22.677902 [Byte1]: 70
8764 12:44:22.681905
8765 12:44:22.681997 Set Vref, RX VrefLevel [Byte0]: 71
8766 12:44:22.685370 [Byte1]: 71
8767 12:44:22.689844
8768 12:44:22.689937 Final RX Vref Byte 0 = 57 to rank0
8769 12:44:22.693022 Final RX Vref Byte 1 = 53 to rank0
8770 12:44:22.696420 Final RX Vref Byte 0 = 57 to rank1
8771 12:44:22.699827 Final RX Vref Byte 1 = 53 to rank1==
8772 12:44:22.703084 Dram Type= 6, Freq= 0, CH_1, rank 0
8773 12:44:22.709579 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8774 12:44:22.709686 ==
8775 12:44:22.709756 DQS Delay:
8776 12:44:22.712837 DQS0 = 0, DQS1 = 0
8777 12:44:22.712929 DQM Delay:
8778 12:44:22.712996 DQM0 = 131, DQM1 = 123
8779 12:44:22.716454 DQ Delay:
8780 12:44:22.719347 DQ0 =138, DQ1 =126, DQ2 =120, DQ3 =128
8781 12:44:22.723039 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =128
8782 12:44:22.726255 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8783 12:44:22.729703 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =130
8784 12:44:22.729798
8785 12:44:22.729865
8786 12:44:22.729925
8787 12:44:22.732644 [DramC_TX_OE_Calibration] TA2
8788 12:44:22.736185 Original DQ_B0 (3 6) =30, OEN = 27
8789 12:44:22.739652 Original DQ_B1 (3 6) =30, OEN = 27
8790 12:44:22.742640 24, 0x0, End_B0=24 End_B1=24
8791 12:44:22.742731 25, 0x0, End_B0=25 End_B1=25
8792 12:44:22.745996 26, 0x0, End_B0=26 End_B1=26
8793 12:44:22.749264 27, 0x0, End_B0=27 End_B1=27
8794 12:44:22.752463 28, 0x0, End_B0=28 End_B1=28
8795 12:44:22.755817 29, 0x0, End_B0=29 End_B1=29
8796 12:44:22.755907 30, 0x0, End_B0=30 End_B1=30
8797 12:44:22.759218 31, 0x4141, End_B0=30 End_B1=30
8798 12:44:22.762560 Byte0 end_step=30 best_step=27
8799 12:44:22.765449 Byte1 end_step=30 best_step=27
8800 12:44:22.768954 Byte0 TX OE(2T, 0.5T) = (3, 3)
8801 12:44:22.772513 Byte1 TX OE(2T, 0.5T) = (3, 3)
8802 12:44:22.772601
8803 12:44:22.772667
8804 12:44:22.778990 [DQSOSCAuto] RK0, (LSB)MR18= 0x60a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 406 ps
8805 12:44:22.781921 CH1 RK0: MR19=303, MR18=60A
8806 12:44:22.788923 CH1_RK0: MR19=0x303, MR18=0x60A, DQSOSC=404, MR23=63, INC=22, DEC=15
8807 12:44:22.789028
8808 12:44:22.791759 ----->DramcWriteLeveling(PI) begin...
8809 12:44:22.791846 ==
8810 12:44:22.795261 Dram Type= 6, Freq= 0, CH_1, rank 1
8811 12:44:22.798432 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8812 12:44:22.798520 ==
8813 12:44:22.801860 Write leveling (Byte 0): 24 => 24
8814 12:44:22.804800 Write leveling (Byte 1): 28 => 28
8815 12:44:22.808649 DramcWriteLeveling(PI) end<-----
8816 12:44:22.808741
8817 12:44:22.808808 ==
8818 12:44:22.811795 Dram Type= 6, Freq= 0, CH_1, rank 1
8819 12:44:22.815082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8820 12:44:22.815174 ==
8821 12:44:22.818320 [Gating] SW mode calibration
8822 12:44:22.824877 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8823 12:44:22.831856 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8824 12:44:22.834781 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8825 12:44:22.841584 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8826 12:44:22.845214 1 4 8 | B1->B0 | 2323 3232 | 1 1 | (1 1) (1 1)
8827 12:44:22.848048 1 4 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
8828 12:44:22.854957 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8829 12:44:22.858237 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8830 12:44:22.861366 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8831 12:44:22.868176 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8832 12:44:22.871166 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8833 12:44:22.874978 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8834 12:44:22.881038 1 5 8 | B1->B0 | 3434 2424 | 1 0 | (1 0) (1 0)
8835 12:44:22.884602 1 5 12 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
8836 12:44:22.887455 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8837 12:44:22.894259 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8838 12:44:22.897829 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8839 12:44:22.900705 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8840 12:44:22.907306 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8841 12:44:22.910667 1 6 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
8842 12:44:22.913871 1 6 8 | B1->B0 | 2424 4545 | 0 0 | (0 0) (0 0)
8843 12:44:22.920473 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8844 12:44:22.923973 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8845 12:44:22.927221 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8846 12:44:22.933754 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8847 12:44:22.937056 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8848 12:44:22.940331 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8849 12:44:22.946739 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8850 12:44:22.950303 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8851 12:44:22.953230 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8852 12:44:22.960006 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 12:44:22.963313 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 12:44:22.966664 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 12:44:22.973169 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 12:44:22.976771 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 12:44:22.979730 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 12:44:22.986751 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 12:44:22.989771 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 12:44:22.993227 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 12:44:23.000023 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 12:44:23.003059 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 12:44:23.006336 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 12:44:23.012987 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 12:44:23.015919 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 12:44:23.019400 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8867 12:44:23.026068 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8868 12:44:23.029277 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8869 12:44:23.033024 Total UI for P1: 0, mck2ui 16
8870 12:44:23.036181 best dqsien dly found for B0: ( 1, 9, 10)
8871 12:44:23.038941 Total UI for P1: 0, mck2ui 16
8872 12:44:23.042453 best dqsien dly found for B1: ( 1, 9, 12)
8873 12:44:23.045640 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8874 12:44:23.049042 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8875 12:44:23.049131
8876 12:44:23.052405 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8877 12:44:23.058786 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8878 12:44:23.058916 [Gating] SW calibration Done
8879 12:44:23.059020 ==
8880 12:44:23.062265 Dram Type= 6, Freq= 0, CH_1, rank 1
8881 12:44:23.068586 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8882 12:44:23.068709 ==
8883 12:44:23.068812 RX Vref Scan: 0
8884 12:44:23.068903
8885 12:44:23.071686 RX Vref 0 -> 0, step: 1
8886 12:44:23.071769
8887 12:44:23.075025 RX Delay 0 -> 252, step: 8
8888 12:44:23.078530 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8889 12:44:23.081604 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8890 12:44:23.085201 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8891 12:44:23.091468 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8892 12:44:23.095109 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8893 12:44:23.098385 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8894 12:44:23.101685 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8895 12:44:23.105113 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8896 12:44:23.111560 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8897 12:44:23.114835 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8898 12:44:23.118220 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8899 12:44:23.120989 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8900 12:44:23.124679 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8901 12:44:23.131114 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8902 12:44:23.134461 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8903 12:44:23.138091 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8904 12:44:23.138182 ==
8905 12:44:23.140833 Dram Type= 6, Freq= 0, CH_1, rank 1
8906 12:44:23.147327 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8907 12:44:23.147442 ==
8908 12:44:23.147516 DQS Delay:
8909 12:44:23.147578 DQS0 = 0, DQS1 = 0
8910 12:44:23.151145 DQM Delay:
8911 12:44:23.151234 DQM0 = 132, DQM1 = 127
8912 12:44:23.154336 DQ Delay:
8913 12:44:23.157534 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8914 12:44:23.160910 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8915 12:44:23.164363 DQ8 =111, DQ9 =119, DQ10 =131, DQ11 =123
8916 12:44:23.167808 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8917 12:44:23.167900
8918 12:44:23.167969
8919 12:44:23.168034 ==
8920 12:44:23.170690 Dram Type= 6, Freq= 0, CH_1, rank 1
8921 12:44:23.174141 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8922 12:44:23.177449 ==
8923 12:44:23.177542
8924 12:44:23.177610
8925 12:44:23.177671 TX Vref Scan disable
8926 12:44:23.181199 == TX Byte 0 ==
8927 12:44:23.183997 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8928 12:44:23.186968 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8929 12:44:23.190388 == TX Byte 1 ==
8930 12:44:23.194059 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8931 12:44:23.196956 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8932 12:44:23.200476 ==
8933 12:44:23.203312 Dram Type= 6, Freq= 0, CH_1, rank 1
8934 12:44:23.206657 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8935 12:44:23.206778 ==
8936 12:44:23.220881
8937 12:44:23.223694 TX Vref early break, caculate TX vref
8938 12:44:23.227269 TX Vref=16, minBit 0, minWin=23, winSum=383
8939 12:44:23.230617 TX Vref=18, minBit 0, minWin=23, winSum=392
8940 12:44:23.233537 TX Vref=20, minBit 0, minWin=23, winSum=399
8941 12:44:23.236972 TX Vref=22, minBit 0, minWin=24, winSum=407
8942 12:44:23.239977 TX Vref=24, minBit 0, minWin=24, winSum=416
8943 12:44:23.247046 TX Vref=26, minBit 13, minWin=25, winSum=420
8944 12:44:23.249778 TX Vref=28, minBit 0, minWin=26, winSum=425
8945 12:44:23.253325 TX Vref=30, minBit 1, minWin=25, winSum=423
8946 12:44:23.256568 TX Vref=32, minBit 1, minWin=24, winSum=413
8947 12:44:23.259738 TX Vref=34, minBit 5, minWin=23, winSum=403
8948 12:44:23.266698 TX Vref=36, minBit 1, minWin=22, winSum=392
8949 12:44:23.269874 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 28
8950 12:44:23.269971
8951 12:44:23.273312 Final TX Range 0 Vref 28
8952 12:44:23.273418
8953 12:44:23.273510 ==
8954 12:44:23.276227 Dram Type= 6, Freq= 0, CH_1, rank 1
8955 12:44:23.279716 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8956 12:44:23.283407 ==
8957 12:44:23.283501
8958 12:44:23.283569
8959 12:44:23.283630 TX Vref Scan disable
8960 12:44:23.290025 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8961 12:44:23.290124 == TX Byte 0 ==
8962 12:44:23.292821 u2DelayCellOfst[0]=18 cells (5 PI)
8963 12:44:23.296344 u2DelayCellOfst[1]=18 cells (5 PI)
8964 12:44:23.299842 u2DelayCellOfst[2]=0 cells (0 PI)
8965 12:44:23.302651 u2DelayCellOfst[3]=7 cells (2 PI)
8966 12:44:23.306278 u2DelayCellOfst[4]=11 cells (3 PI)
8967 12:44:23.309457 u2DelayCellOfst[5]=22 cells (6 PI)
8968 12:44:23.313085 u2DelayCellOfst[6]=22 cells (6 PI)
8969 12:44:23.315920 u2DelayCellOfst[7]=11 cells (3 PI)
8970 12:44:23.319506 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8971 12:44:23.322751 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8972 12:44:23.326119 == TX Byte 1 ==
8973 12:44:23.329111 u2DelayCellOfst[8]=0 cells (0 PI)
8974 12:44:23.332518 u2DelayCellOfst[9]=7 cells (2 PI)
8975 12:44:23.335921 u2DelayCellOfst[10]=15 cells (4 PI)
8976 12:44:23.339494 u2DelayCellOfst[11]=7 cells (2 PI)
8977 12:44:23.342392 u2DelayCellOfst[12]=18 cells (5 PI)
8978 12:44:23.346015 u2DelayCellOfst[13]=18 cells (5 PI)
8979 12:44:23.348828 u2DelayCellOfst[14]=22 cells (6 PI)
8980 12:44:23.352130 u2DelayCellOfst[15]=22 cells (6 PI)
8981 12:44:23.355477 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8982 12:44:23.358776 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8983 12:44:23.362021 DramC Write-DBI on
8984 12:44:23.362116 ==
8985 12:44:23.365386 Dram Type= 6, Freq= 0, CH_1, rank 1
8986 12:44:23.368557 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8987 12:44:23.368650 ==
8988 12:44:23.368723
8989 12:44:23.368785
8990 12:44:23.372070 TX Vref Scan disable
8991 12:44:23.375511 == TX Byte 0 ==
8992 12:44:23.378570 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8993 12:44:23.378681 == TX Byte 1 ==
8994 12:44:23.385014 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8995 12:44:23.385114 DramC Write-DBI off
8996 12:44:23.385184
8997 12:44:23.385247 [DATLAT]
8998 12:44:23.388564 Freq=1600, CH1 RK1
8999 12:44:23.388640
9000 12:44:23.391841 DATLAT Default: 0xf
9001 12:44:23.391945 0, 0xFFFF, sum = 0
9002 12:44:23.395204 1, 0xFFFF, sum = 0
9003 12:44:23.395293 2, 0xFFFF, sum = 0
9004 12:44:23.398385 3, 0xFFFF, sum = 0
9005 12:44:23.398475 4, 0xFFFF, sum = 0
9006 12:44:23.401939 5, 0xFFFF, sum = 0
9007 12:44:23.402034 6, 0xFFFF, sum = 0
9008 12:44:23.404873 7, 0xFFFF, sum = 0
9009 12:44:23.404963 8, 0xFFFF, sum = 0
9010 12:44:23.408544 9, 0xFFFF, sum = 0
9011 12:44:23.408636 10, 0xFFFF, sum = 0
9012 12:44:23.411436 11, 0xFFFF, sum = 0
9013 12:44:23.411541 12, 0xFFFF, sum = 0
9014 12:44:23.414816 13, 0x8FFF, sum = 0
9015 12:44:23.414945 14, 0x0, sum = 1
9016 12:44:23.418498 15, 0x0, sum = 2
9017 12:44:23.418589 16, 0x0, sum = 3
9018 12:44:23.421666 17, 0x0, sum = 4
9019 12:44:23.421755 best_step = 15
9020 12:44:23.421823
9021 12:44:23.421883 ==
9022 12:44:23.424530 Dram Type= 6, Freq= 0, CH_1, rank 1
9023 12:44:23.431533 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9024 12:44:23.431690 ==
9025 12:44:23.431794 RX Vref Scan: 0
9026 12:44:23.431881
9027 12:44:23.434889 RX Vref 0 -> 0, step: 1
9028 12:44:23.434975
9029 12:44:23.437722 RX Delay 3 -> 252, step: 4
9030 12:44:23.441338 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
9031 12:44:23.444170 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
9032 12:44:23.451227 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
9033 12:44:23.454113 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
9034 12:44:23.457320 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
9035 12:44:23.460937 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
9036 12:44:23.464175 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
9037 12:44:23.470855 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
9038 12:44:23.474280 iDelay=195, Bit 8, Center 110 (51 ~ 170) 120
9039 12:44:23.477416 iDelay=195, Bit 9, Center 114 (63 ~ 166) 104
9040 12:44:23.480527 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9041 12:44:23.484574 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9042 12:44:23.490766 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9043 12:44:23.493617 iDelay=195, Bit 13, Center 134 (79 ~ 190) 112
9044 12:44:23.496872 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9045 12:44:23.500275 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9046 12:44:23.500361 ==
9047 12:44:23.503465 Dram Type= 6, Freq= 0, CH_1, rank 1
9048 12:44:23.510528 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9049 12:44:23.510622 ==
9050 12:44:23.510690 DQS Delay:
9051 12:44:23.513508 DQS0 = 0, DQS1 = 0
9052 12:44:23.513594 DQM Delay:
9053 12:44:23.516969 DQM0 = 130, DQM1 = 125
9054 12:44:23.517054 DQ Delay:
9055 12:44:23.520336 DQ0 =134, DQ1 =128, DQ2 =116, DQ3 =126
9056 12:44:23.523905 DQ4 =126, DQ5 =140, DQ6 =142, DQ7 =128
9057 12:44:23.526734 DQ8 =110, DQ9 =114, DQ10 =128, DQ11 =120
9058 12:44:23.530074 DQ12 =132, DQ13 =134, DQ14 =130, DQ15 =136
9059 12:44:23.530159
9060 12:44:23.530243
9061 12:44:23.530323
9062 12:44:23.533607 [DramC_TX_OE_Calibration] TA2
9063 12:44:23.536436 Original DQ_B0 (3 6) =30, OEN = 27
9064 12:44:23.539967 Original DQ_B1 (3 6) =30, OEN = 27
9065 12:44:23.543693 24, 0x0, End_B0=24 End_B1=24
9066 12:44:23.546618 25, 0x0, End_B0=25 End_B1=25
9067 12:44:23.546704 26, 0x0, End_B0=26 End_B1=26
9068 12:44:23.550039 27, 0x0, End_B0=27 End_B1=27
9069 12:44:23.553036 28, 0x0, End_B0=28 End_B1=28
9070 12:44:23.556500 29, 0x0, End_B0=29 End_B1=29
9071 12:44:23.559838 30, 0x0, End_B0=30 End_B1=30
9072 12:44:23.559925 31, 0x4141, End_B0=30 End_B1=30
9073 12:44:23.563388 Byte0 end_step=30 best_step=27
9074 12:44:23.566184 Byte1 end_step=30 best_step=27
9075 12:44:23.569766 Byte0 TX OE(2T, 0.5T) = (3, 3)
9076 12:44:23.573145 Byte1 TX OE(2T, 0.5T) = (3, 3)
9077 12:44:23.573231
9078 12:44:23.573316
9079 12:44:23.579394 [DQSOSCAuto] RK1, (LSB)MR18= 0xe1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
9080 12:44:23.582751 CH1 RK1: MR19=303, MR18=E1A
9081 12:44:23.589297 CH1_RK1: MR19=0x303, MR18=0xE1A, DQSOSC=396, MR23=63, INC=23, DEC=15
9082 12:44:23.592995 [RxdqsGatingPostProcess] freq 1600
9083 12:44:23.599271 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9084 12:44:23.599360 best DQS0 dly(2T, 0.5T) = (1, 1)
9085 12:44:23.602644 best DQS1 dly(2T, 0.5T) = (1, 1)
9086 12:44:23.605972 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9087 12:44:23.609600 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9088 12:44:23.612674 best DQS0 dly(2T, 0.5T) = (1, 1)
9089 12:44:23.615607 best DQS1 dly(2T, 0.5T) = (1, 1)
9090 12:44:23.619210 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9091 12:44:23.622491 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9092 12:44:23.626058 Pre-setting of DQS Precalculation
9093 12:44:23.628917 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9094 12:44:23.639026 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9095 12:44:23.645961 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9096 12:44:23.646050
9097 12:44:23.646136
9098 12:44:23.648970 [Calibration Summary] 3200 Mbps
9099 12:44:23.649055 CH 0, Rank 0
9100 12:44:23.651955 SW Impedance : PASS
9101 12:44:23.652040 DUTY Scan : NO K
9102 12:44:23.655520 ZQ Calibration : PASS
9103 12:44:23.658613 Jitter Meter : NO K
9104 12:44:23.658714 CBT Training : PASS
9105 12:44:23.661843 Write leveling : PASS
9106 12:44:23.665233 RX DQS gating : PASS
9107 12:44:23.665306 RX DQ/DQS(RDDQC) : PASS
9108 12:44:23.668207 TX DQ/DQS : PASS
9109 12:44:23.671777 RX DATLAT : PASS
9110 12:44:23.671850 RX DQ/DQS(Engine): PASS
9111 12:44:23.675267 TX OE : PASS
9112 12:44:23.675339 All Pass.
9113 12:44:23.675400
9114 12:44:23.678521 CH 0, Rank 1
9115 12:44:23.678595 SW Impedance : PASS
9116 12:44:23.681367 DUTY Scan : NO K
9117 12:44:23.684850 ZQ Calibration : PASS
9118 12:44:23.684923 Jitter Meter : NO K
9119 12:44:23.688191 CBT Training : PASS
9120 12:44:23.691908 Write leveling : PASS
9121 12:44:23.691984 RX DQS gating : PASS
9122 12:44:23.694624 RX DQ/DQS(RDDQC) : PASS
9123 12:44:23.698110 TX DQ/DQS : PASS
9124 12:44:23.698188 RX DATLAT : PASS
9125 12:44:23.701248 RX DQ/DQS(Engine): PASS
9126 12:44:23.704566 TX OE : PASS
9127 12:44:23.704641 All Pass.
9128 12:44:23.704704
9129 12:44:23.704762 CH 1, Rank 0
9130 12:44:23.708095 SW Impedance : PASS
9131 12:44:23.711489 DUTY Scan : NO K
9132 12:44:23.711565 ZQ Calibration : PASS
9133 12:44:23.714695 Jitter Meter : NO K
9134 12:44:23.718077 CBT Training : PASS
9135 12:44:23.718155 Write leveling : PASS
9136 12:44:23.721026 RX DQS gating : PASS
9137 12:44:23.721100 RX DQ/DQS(RDDQC) : PASS
9138 12:44:23.724465 TX DQ/DQS : PASS
9139 12:44:23.727790 RX DATLAT : PASS
9140 12:44:23.727867 RX DQ/DQS(Engine): PASS
9141 12:44:23.731221 TX OE : PASS
9142 12:44:23.731299 All Pass.
9143 12:44:23.731363
9144 12:44:23.734201 CH 1, Rank 1
9145 12:44:23.734300 SW Impedance : PASS
9146 12:44:23.737622 DUTY Scan : NO K
9147 12:44:23.741099 ZQ Calibration : PASS
9148 12:44:23.741172 Jitter Meter : NO K
9149 12:44:23.744444 CBT Training : PASS
9150 12:44:23.747355 Write leveling : PASS
9151 12:44:23.747431 RX DQS gating : PASS
9152 12:44:23.750757 RX DQ/DQS(RDDQC) : PASS
9153 12:44:23.754318 TX DQ/DQS : PASS
9154 12:44:23.754393 RX DATLAT : PASS
9155 12:44:23.757425 RX DQ/DQS(Engine): PASS
9156 12:44:23.760892 TX OE : PASS
9157 12:44:23.760966 All Pass.
9158 12:44:23.761028
9159 12:44:23.763939 DramC Write-DBI on
9160 12:44:23.764009 PER_BANK_REFRESH: Hybrid Mode
9161 12:44:23.767237 TX_TRACKING: ON
9162 12:44:23.777195 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9163 12:44:23.783639 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9164 12:44:23.790360 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9165 12:44:23.793513 [FAST_K] Save calibration result to emmc
9166 12:44:23.797028 sync common calibartion params.
9167 12:44:23.800228 sync cbt_mode0:1, 1:1
9168 12:44:23.800306 dram_init: ddr_geometry: 2
9169 12:44:23.803540 dram_init: ddr_geometry: 2
9170 12:44:23.806799 dram_init: ddr_geometry: 2
9171 12:44:23.809756 0:dram_rank_size:100000000
9172 12:44:23.809832 1:dram_rank_size:100000000
9173 12:44:23.816837 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9174 12:44:23.819524 DFS_SHUFFLE_HW_MODE: ON
9175 12:44:23.823238 dramc_set_vcore_voltage set vcore to 725000
9176 12:44:23.826123 Read voltage for 1600, 0
9177 12:44:23.826202 Vio18 = 0
9178 12:44:23.826264 Vcore = 725000
9179 12:44:23.829513 Vdram = 0
9180 12:44:23.829585 Vddq = 0
9181 12:44:23.829645 Vmddr = 0
9182 12:44:23.832836 switch to 3200 Mbps bootup
9183 12:44:23.832910 [DramcRunTimeConfig]
9184 12:44:23.836254 PHYPLL
9185 12:44:23.836352 DPM_CONTROL_AFTERK: ON
9186 12:44:23.839702 PER_BANK_REFRESH: ON
9187 12:44:23.843151 REFRESH_OVERHEAD_REDUCTION: ON
9188 12:44:23.843227 CMD_PICG_NEW_MODE: OFF
9189 12:44:23.846163 XRTWTW_NEW_MODE: ON
9190 12:44:23.846249 XRTRTR_NEW_MODE: ON
9191 12:44:23.849439 TX_TRACKING: ON
9192 12:44:23.849521 RDSEL_TRACKING: OFF
9193 12:44:23.852707 DQS Precalculation for DVFS: ON
9194 12:44:23.856252 RX_TRACKING: OFF
9195 12:44:23.856328 HW_GATING DBG: ON
9196 12:44:23.859267 ZQCS_ENABLE_LP4: ON
9197 12:44:23.859374 RX_PICG_NEW_MODE: ON
9198 12:44:23.862710 TX_PICG_NEW_MODE: ON
9199 12:44:23.866298 ENABLE_RX_DCM_DPHY: ON
9200 12:44:23.866380 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9201 12:44:23.869149 DUMMY_READ_FOR_TRACKING: OFF
9202 12:44:23.872470 !!! SPM_CONTROL_AFTERK: OFF
9203 12:44:23.876058 !!! SPM could not control APHY
9204 12:44:23.879472 IMPEDANCE_TRACKING: ON
9205 12:44:23.879570 TEMP_SENSOR: ON
9206 12:44:23.882665 HW_SAVE_FOR_SR: OFF
9207 12:44:23.882747 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9208 12:44:23.889359 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9209 12:44:23.889468 Read ODT Tracking: ON
9210 12:44:23.892202 Refresh Rate DeBounce: ON
9211 12:44:23.892279 DFS_NO_QUEUE_FLUSH: ON
9212 12:44:23.895759 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9213 12:44:23.899075 ENABLE_DFS_RUNTIME_MRW: OFF
9214 12:44:23.902270 DDR_RESERVE_NEW_MODE: ON
9215 12:44:23.902371 MR_CBT_SWITCH_FREQ: ON
9216 12:44:23.905780 =========================
9217 12:44:23.925289 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9218 12:44:23.928369 dram_init: ddr_geometry: 2
9219 12:44:23.946624 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9220 12:44:23.950168 dram_init: dram init end (result: 0)
9221 12:44:23.956515 DRAM-K: Full calibration passed in 24550 msecs
9222 12:44:23.959637 MRC: failed to locate region type 0.
9223 12:44:23.959722 DRAM rank0 size:0x100000000,
9224 12:44:23.963118 DRAM rank1 size=0x100000000
9225 12:44:23.972956 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9226 12:44:23.979842 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9227 12:44:23.986248 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9228 12:44:23.995786 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9229 12:44:23.995902 DRAM rank0 size:0x100000000,
9230 12:44:23.999455 DRAM rank1 size=0x100000000
9231 12:44:23.999542 CBMEM:
9232 12:44:24.002268 IMD: root @ 0xfffff000 254 entries.
9233 12:44:24.005685 IMD: root @ 0xffffec00 62 entries.
9234 12:44:24.012382 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9235 12:44:24.015932 WARNING: RO_VPD is uninitialized or empty.
9236 12:44:24.018691 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9237 12:44:24.026632 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9238 12:44:24.039506 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9239 12:44:24.050854 BS: romstage times (exec / console): total (unknown) / 24022 ms
9240 12:44:24.050986
9241 12:44:24.051080
9242 12:44:24.060637 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9243 12:44:24.064229 ARM64: Exception handlers installed.
9244 12:44:24.067268 ARM64: Testing exception
9245 12:44:24.070758 ARM64: Done test exception
9246 12:44:24.070884 Enumerating buses...
9247 12:44:24.073597 Show all devs... Before device enumeration.
9248 12:44:24.077202 Root Device: enabled 1
9249 12:44:24.080439 CPU_CLUSTER: 0: enabled 1
9250 12:44:24.080529 CPU: 00: enabled 1
9251 12:44:24.083971 Compare with tree...
9252 12:44:24.084058 Root Device: enabled 1
9253 12:44:24.086944 CPU_CLUSTER: 0: enabled 1
9254 12:44:24.090423 CPU: 00: enabled 1
9255 12:44:24.090511 Root Device scanning...
9256 12:44:24.093815 scan_static_bus for Root Device
9257 12:44:24.097051 CPU_CLUSTER: 0 enabled
9258 12:44:24.100585 scan_static_bus for Root Device done
9259 12:44:24.103381 scan_bus: bus Root Device finished in 8 msecs
9260 12:44:24.103466 done
9261 12:44:24.110214 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9262 12:44:24.113156 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9263 12:44:24.119981 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9264 12:44:24.126627 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9265 12:44:24.126775 Allocating resources...
9266 12:44:24.129584 Reading resources...
9267 12:44:24.133091 Root Device read_resources bus 0 link: 0
9268 12:44:24.136384 DRAM rank0 size:0x100000000,
9269 12:44:24.136468 DRAM rank1 size=0x100000000
9270 12:44:24.142820 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9271 12:44:24.142924 CPU: 00 missing read_resources
9272 12:44:24.149403 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9273 12:44:24.152799 Root Device read_resources bus 0 link: 0 done
9274 12:44:24.156198 Done reading resources.
9275 12:44:24.159222 Show resources in subtree (Root Device)...After reading.
9276 12:44:24.162660 Root Device child on link 0 CPU_CLUSTER: 0
9277 12:44:24.166105 CPU_CLUSTER: 0 child on link 0 CPU: 00
9278 12:44:24.176099 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9279 12:44:24.176195 CPU: 00
9280 12:44:24.182445 Root Device assign_resources, bus 0 link: 0
9281 12:44:24.185732 CPU_CLUSTER: 0 missing set_resources
9282 12:44:24.188704 Root Device assign_resources, bus 0 link: 0 done
9283 12:44:24.192283 Done setting resources.
9284 12:44:24.195314 Show resources in subtree (Root Device)...After assigning values.
9285 12:44:24.201826 Root Device child on link 0 CPU_CLUSTER: 0
9286 12:44:24.205272 CPU_CLUSTER: 0 child on link 0 CPU: 00
9287 12:44:24.211805 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9288 12:44:24.215238 CPU: 00
9289 12:44:24.215334 Done allocating resources.
9290 12:44:24.221613 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9291 12:44:24.225021 Enabling resources...
9292 12:44:24.225111 done.
9293 12:44:24.228496 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9294 12:44:24.231680 Initializing devices...
9295 12:44:24.231772 Root Device init
9296 12:44:24.234807 init hardware done!
9297 12:44:24.238299 0x00000018: ctrlr->caps
9298 12:44:24.238388 52.000 MHz: ctrlr->f_max
9299 12:44:24.241177 0.400 MHz: ctrlr->f_min
9300 12:44:24.244476 0x40ff8080: ctrlr->voltages
9301 12:44:24.244570 sclk: 390625
9302 12:44:24.244637 Bus Width = 1
9303 12:44:24.248133 sclk: 390625
9304 12:44:24.248247 Bus Width = 1
9305 12:44:24.251441 Early init status = 3
9306 12:44:24.254521 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9307 12:44:24.258297 in-header: 03 fc 00 00 01 00 00 00
9308 12:44:24.261728 in-data: 00
9309 12:44:24.264863 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9310 12:44:24.269570 in-header: 03 fd 00 00 00 00 00 00
9311 12:44:24.272977 in-data:
9312 12:44:24.275909 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9313 12:44:24.280065 in-header: 03 fc 00 00 01 00 00 00
9314 12:44:24.283033 in-data: 00
9315 12:44:24.286477 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9316 12:44:24.291446 in-header: 03 fd 00 00 00 00 00 00
9317 12:44:24.294374 in-data:
9318 12:44:24.297858 [SSUSB] Setting up USB HOST controller...
9319 12:44:24.301246 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9320 12:44:24.304652 [SSUSB] phy power-on done.
9321 12:44:24.307922 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9322 12:44:24.314333 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9323 12:44:24.317972 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9324 12:44:24.324144 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9325 12:44:24.330809 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9326 12:44:24.337577 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9327 12:44:24.343855 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9328 12:44:24.350508 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9329 12:44:24.354186 SPM: binary array size = 0x9dc
9330 12:44:24.357165 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9331 12:44:24.363853 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9332 12:44:24.370554 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9333 12:44:24.377066 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9334 12:44:24.379890 configure_display: Starting display init
9335 12:44:24.414471 anx7625_power_on_init: Init interface.
9336 12:44:24.418483 anx7625_disable_pd_protocol: Disabled PD feature.
9337 12:44:24.421096 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9338 12:44:24.448837 anx7625_start_dp_work: Secure OCM version=00
9339 12:44:24.452307 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9340 12:44:24.466863 sp_tx_get_edid_block: EDID Block = 1
9341 12:44:24.569785 Extracted contents:
9342 12:44:24.573210 header: 00 ff ff ff ff ff ff 00
9343 12:44:24.576497 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9344 12:44:24.579277 version: 01 04
9345 12:44:24.582712 basic params: 95 1f 11 78 0a
9346 12:44:24.586110 chroma info: 76 90 94 55 54 90 27 21 50 54
9347 12:44:24.589692 established: 00 00 00
9348 12:44:24.595978 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9349 12:44:24.602792 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9350 12:44:24.605715 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9351 12:44:24.612203 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9352 12:44:24.619153 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9353 12:44:24.622524 extensions: 00
9354 12:44:24.622612 checksum: fb
9355 12:44:24.622678
9356 12:44:24.629052 Manufacturer: IVO Model 57d Serial Number 0
9357 12:44:24.629137 Made week 0 of 2020
9358 12:44:24.632014 EDID version: 1.4
9359 12:44:24.632097 Digital display
9360 12:44:24.635394 6 bits per primary color channel
9361 12:44:24.638442 DisplayPort interface
9362 12:44:24.638524 Maximum image size: 31 cm x 17 cm
9363 12:44:24.641662 Gamma: 220%
9364 12:44:24.641743 Check DPMS levels
9365 12:44:24.648541 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9366 12:44:24.652045 First detailed timing is preferred timing
9367 12:44:24.654899 Established timings supported:
9368 12:44:24.654980 Standard timings supported:
9369 12:44:24.658339 Detailed timings
9370 12:44:24.661795 Hex of detail: 383680a07038204018303c0035ae10000019
9371 12:44:24.668253 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9372 12:44:24.671414 0780 0798 07c8 0820 hborder 0
9373 12:44:24.675157 0438 043b 0447 0458 vborder 0
9374 12:44:24.678279 -hsync -vsync
9375 12:44:24.678364 Did detailed timing
9376 12:44:24.684779 Hex of detail: 000000000000000000000000000000000000
9377 12:44:24.688193 Manufacturer-specified data, tag 0
9378 12:44:24.691516 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9379 12:44:24.694854 ASCII string: InfoVision
9380 12:44:24.698309 Hex of detail: 000000fe00523134304e574635205248200a
9381 12:44:24.701635 ASCII string: R140NWF5 RH
9382 12:44:24.701721 Checksum
9383 12:44:24.704473 Checksum: 0xfb (valid)
9384 12:44:24.707952 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9385 12:44:24.711440 DSI data_rate: 832800000 bps
9386 12:44:24.718059 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9387 12:44:24.720986 anx7625_parse_edid: pixelclock(138800).
9388 12:44:24.724304 hactive(1920), hsync(48), hfp(24), hbp(88)
9389 12:44:24.727783 vactive(1080), vsync(12), vfp(3), vbp(17)
9390 12:44:24.731315 anx7625_dsi_config: config dsi.
9391 12:44:24.737271 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9392 12:44:24.751721 anx7625_dsi_config: success to config DSI
9393 12:44:24.754709 anx7625_dp_start: MIPI phy setup OK.
9394 12:44:24.758299 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9395 12:44:24.761671 mtk_ddp_mode_set invalid vrefresh 60
9396 12:44:24.764630 main_disp_path_setup
9397 12:44:24.764714 ovl_layer_smi_id_en
9398 12:44:24.768043 ovl_layer_smi_id_en
9399 12:44:24.768127 ccorr_config
9400 12:44:24.768191 aal_config
9401 12:44:24.771417 gamma_config
9402 12:44:24.771501 postmask_config
9403 12:44:24.774617 dither_config
9404 12:44:24.777818 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9405 12:44:24.785003 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9406 12:44:24.787733 Root Device init finished in 552 msecs
9407 12:44:24.790957 CPU_CLUSTER: 0 init
9408 12:44:24.797524 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9409 12:44:24.804563 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9410 12:44:24.804656 APU_MBOX 0x190000b0 = 0x10001
9411 12:44:24.807413 APU_MBOX 0x190001b0 = 0x10001
9412 12:44:24.810696 APU_MBOX 0x190005b0 = 0x10001
9413 12:44:24.814003 APU_MBOX 0x190006b0 = 0x10001
9414 12:44:24.820844 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9415 12:44:24.830571 read SPI 0x539f4 0xe237: 6250 us, 9265 KB/s, 74.120 Mbps
9416 12:44:24.842864 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9417 12:44:24.849626 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9418 12:44:24.861241 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9419 12:44:24.870516 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9420 12:44:24.873943 CPU_CLUSTER: 0 init finished in 81 msecs
9421 12:44:24.876843 Devices initialized
9422 12:44:24.880460 Show all devs... After init.
9423 12:44:24.880546 Root Device: enabled 1
9424 12:44:24.883397 CPU_CLUSTER: 0: enabled 1
9425 12:44:24.886987 CPU: 00: enabled 1
9426 12:44:24.890183 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9427 12:44:24.893475 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9428 12:44:24.896547 ELOG: NV offset 0x57f000 size 0x1000
9429 12:44:24.903757 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9430 12:44:24.910384 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9431 12:44:24.913269 ELOG: Event(17) added with size 13 at 2023-06-14 12:44:25 UTC
9432 12:44:24.920216 out: cmd=0x121: 03 db 21 01 00 00 00 00
9433 12:44:24.923262 in-header: 03 71 00 00 2c 00 00 00
9434 12:44:24.932965 in-data: ee 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9435 12:44:24.939849 ELOG: Event(A1) added with size 10 at 2023-06-14 12:44:25 UTC
9436 12:44:24.946540 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9437 12:44:24.952963 ELOG: Event(A0) added with size 9 at 2023-06-14 12:44:25 UTC
9438 12:44:24.955879 elog_add_boot_reason: Logged dev mode boot
9439 12:44:24.962778 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9440 12:44:24.962908 Finalize devices...
9441 12:44:24.965754 Devices finalized
9442 12:44:24.969187 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9443 12:44:24.972527 Writing coreboot table at 0xffe64000
9444 12:44:24.976371 0. 000000000010a000-0000000000113fff: RAMSTAGE
9445 12:44:24.982359 1. 0000000040000000-00000000400fffff: RAM
9446 12:44:24.985841 2. 0000000040100000-000000004032afff: RAMSTAGE
9447 12:44:24.989267 3. 000000004032b000-00000000545fffff: RAM
9448 12:44:24.992151 4. 0000000054600000-000000005465ffff: BL31
9449 12:44:24.995452 5. 0000000054660000-00000000ffe63fff: RAM
9450 12:44:25.002470 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9451 12:44:25.005201 7. 0000000100000000-000000023fffffff: RAM
9452 12:44:25.009191 Passing 5 GPIOs to payload:
9453 12:44:25.012251 NAME | PORT | POLARITY | VALUE
9454 12:44:25.019057 EC in RW | 0x000000aa | low | undefined
9455 12:44:25.021817 EC interrupt | 0x00000005 | low | undefined
9456 12:44:25.028634 TPM interrupt | 0x000000ab | high | undefined
9457 12:44:25.032118 SD card detect | 0x00000011 | high | undefined
9458 12:44:25.035058 speaker enable | 0x00000093 | high | undefined
9459 12:44:25.038468 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9460 12:44:25.041972 in-header: 03 f9 00 00 02 00 00 00
9461 12:44:25.045557 in-data: 02 00
9462 12:44:25.048583 ADC[4]: Raw value=894821 ID=7
9463 12:44:25.051897 ADC[3]: Raw value=212700 ID=1
9464 12:44:25.051985 RAM Code: 0x71
9465 12:44:25.054889 ADC[6]: Raw value=74722 ID=0
9466 12:44:25.058206 ADC[5]: Raw value=212700 ID=1
9467 12:44:25.058304 SKU Code: 0x1
9468 12:44:25.064735 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7dbf
9469 12:44:25.064831 coreboot table: 964 bytes.
9470 12:44:25.068476 IMD ROOT 0. 0xfffff000 0x00001000
9471 12:44:25.071466 IMD SMALL 1. 0xffffe000 0x00001000
9472 12:44:25.074745 RO MCACHE 2. 0xffffc000 0x00001104
9473 12:44:25.078106 CONSOLE 3. 0xfff7c000 0x00080000
9474 12:44:25.081587 FMAP 4. 0xfff7b000 0x00000452
9475 12:44:25.084516 TIME STAMP 5. 0xfff7a000 0x00000910
9476 12:44:25.087860 VBOOT WORK 6. 0xfff66000 0x00014000
9477 12:44:25.091274 RAMOOPS 7. 0xffe66000 0x00100000
9478 12:44:25.094965 COREBOOT 8. 0xffe64000 0x00002000
9479 12:44:25.098095 IMD small region:
9480 12:44:25.101330 IMD ROOT 0. 0xffffec00 0x00000400
9481 12:44:25.104778 VPD 1. 0xffffeba0 0x0000004c
9482 12:44:25.107611 MMC STATUS 2. 0xffffeb80 0x00000004
9483 12:44:25.114502 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9484 12:44:25.114623 Probing TPM: done!
9485 12:44:25.121290 Connected to device vid:did:rid of 1ae0:0028:00
9486 12:44:25.127586 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9487 12:44:25.130667 Initialized TPM device CR50 revision 0
9488 12:44:25.134715 Checking cr50 for pending updates
9489 12:44:25.139874 Reading cr50 TPM mode
9490 12:44:25.148965 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9491 12:44:25.154967 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9492 12:44:25.195368 read SPI 0x3990ec 0x4f1b0: 34859 us, 9295 KB/s, 74.360 Mbps
9493 12:44:25.198786 Checking segment from ROM address 0x40100000
9494 12:44:25.201785 Checking segment from ROM address 0x4010001c
9495 12:44:25.208509 Loading segment from ROM address 0x40100000
9496 12:44:25.208622 code (compression=0)
9497 12:44:25.218709 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9498 12:44:25.225451 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9499 12:44:25.225559 it's not compressed!
9500 12:44:25.232145 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9501 12:44:25.235291 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9502 12:44:25.255703 Loading segment from ROM address 0x4010001c
9503 12:44:25.255831 Entry Point 0x80000000
9504 12:44:25.259213 Loaded segments
9505 12:44:25.262177 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9506 12:44:25.269068 Jumping to boot code at 0x80000000(0xffe64000)
9507 12:44:25.275656 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9508 12:44:25.282139 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9509 12:44:25.290109 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9510 12:44:25.293622 Checking segment from ROM address 0x40100000
9511 12:44:25.296577 Checking segment from ROM address 0x4010001c
9512 12:44:25.303662 Loading segment from ROM address 0x40100000
9513 12:44:25.303759 code (compression=1)
9514 12:44:25.310076 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9515 12:44:25.319976 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9516 12:44:25.320097 using LZMA
9517 12:44:25.328574 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9518 12:44:25.335352 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9519 12:44:25.338259 Loading segment from ROM address 0x4010001c
9520 12:44:25.338379 Entry Point 0x54601000
9521 12:44:25.341972 Loaded segments
9522 12:44:25.344890 NOTICE: MT8192 bl31_setup
9523 12:44:25.352120 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9524 12:44:25.355258 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9525 12:44:25.358947 WARNING: region 0:
9526 12:44:25.362055 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9527 12:44:25.362140 WARNING: region 1:
9528 12:44:25.368917 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9529 12:44:25.372259 WARNING: region 2:
9530 12:44:25.375257 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9531 12:44:25.378714 WARNING: region 3:
9532 12:44:25.381599 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9533 12:44:25.385266 WARNING: region 4:
9534 12:44:25.391929 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9535 12:44:25.392031 WARNING: region 5:
9536 12:44:25.394804 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9537 12:44:25.398467 WARNING: region 6:
9538 12:44:25.401415 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9539 12:44:25.404926 WARNING: region 7:
9540 12:44:25.408369 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9541 12:44:25.414615 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9542 12:44:25.418118 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9543 12:44:25.424525 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9544 12:44:25.427954 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9545 12:44:25.431301 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9546 12:44:25.437822 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9547 12:44:25.441304 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9548 12:44:25.444965 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9549 12:44:25.451102 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9550 12:44:25.454385 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9551 12:44:25.461158 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9552 12:44:25.464077 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9553 12:44:25.467668 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9554 12:44:25.474234 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9555 12:44:25.477776 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9556 12:44:25.480784 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9557 12:44:25.487423 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9558 12:44:25.490764 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9559 12:44:25.497889 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9560 12:44:25.500770 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9561 12:44:25.504107 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9562 12:44:25.511048 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9563 12:44:25.513770 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9564 12:44:25.520644 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9565 12:44:25.524025 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9566 12:44:25.526879 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9567 12:44:25.533624 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9568 12:44:25.536996 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9569 12:44:25.543968 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9570 12:44:25.547318 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9571 12:44:25.550695 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9572 12:44:25.557089 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9573 12:44:25.560411 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9574 12:44:25.563780 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9575 12:44:25.570351 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9576 12:44:25.573312 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9577 12:44:25.577168 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9578 12:44:25.580447 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9579 12:44:25.586715 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9580 12:44:25.590079 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9581 12:44:25.593534 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9582 12:44:25.596859 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9583 12:44:25.603565 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9584 12:44:25.607037 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9585 12:44:25.609768 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9586 12:44:25.613253 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9587 12:44:25.620060 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9588 12:44:25.623636 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9589 12:44:25.626865 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9590 12:44:25.633411 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9591 12:44:25.636668 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9592 12:44:25.643438 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9593 12:44:25.646635 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9594 12:44:25.650156 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9595 12:44:25.656718 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9596 12:44:25.659950 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9597 12:44:25.666576 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9598 12:44:25.669885 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9599 12:44:25.676553 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9600 12:44:25.679905 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9601 12:44:25.686738 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9602 12:44:25.689981 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9603 12:44:25.693712 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9604 12:44:25.699442 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9605 12:44:25.702966 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9606 12:44:25.709559 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9607 12:44:25.713014 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9608 12:44:25.719732 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9609 12:44:25.723368 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9610 12:44:25.729605 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9611 12:44:25.732868 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9612 12:44:25.736225 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9613 12:44:25.742966 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9614 12:44:25.746381 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9615 12:44:25.752420 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9616 12:44:25.755620 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9617 12:44:25.762219 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9618 12:44:25.766214 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9619 12:44:25.772634 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9620 12:44:25.775998 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9621 12:44:25.779426 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9622 12:44:25.785446 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9623 12:44:25.789215 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9624 12:44:25.795513 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9625 12:44:25.799126 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9626 12:44:25.805969 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9627 12:44:25.808803 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9628 12:44:25.812020 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9629 12:44:25.818843 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9630 12:44:25.822329 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9631 12:44:25.828857 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9632 12:44:25.831992 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9633 12:44:25.838798 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9634 12:44:25.841752 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9635 12:44:25.848600 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9636 12:44:25.851979 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9637 12:44:25.855312 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9638 12:44:25.861802 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9639 12:44:25.865093 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9640 12:44:25.868885 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9641 12:44:25.871627 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9642 12:44:25.878668 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9643 12:44:25.882081 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9644 12:44:25.888147 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9645 12:44:25.891476 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9646 12:44:25.894698 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9647 12:44:25.901589 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9648 12:44:25.904764 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9649 12:44:25.911670 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9650 12:44:25.915018 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9651 12:44:25.917868 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9652 12:44:25.924722 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9653 12:44:25.928421 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9654 12:44:25.934317 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9655 12:44:25.937731 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9656 12:44:25.941188 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9657 12:44:25.947928 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9658 12:44:25.951300 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9659 12:44:25.954734 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9660 12:44:25.961456 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9661 12:44:25.964769 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9662 12:44:25.967869 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9663 12:44:25.970878 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9664 12:44:25.977967 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9665 12:44:25.980907 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9666 12:44:25.984231 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9667 12:44:25.990821 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9668 12:44:25.994244 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9669 12:44:26.000593 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9670 12:44:26.003942 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9671 12:44:26.007263 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9672 12:44:26.013629 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9673 12:44:26.017311 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9674 12:44:26.024079 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9675 12:44:26.026942 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9676 12:44:26.030226 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9677 12:44:26.037281 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9678 12:44:26.040422 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9679 12:44:26.047337 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9680 12:44:26.050509 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9681 12:44:26.053922 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9682 12:44:26.060655 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9683 12:44:26.063560 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9684 12:44:26.070358 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9685 12:44:26.073651 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9686 12:44:26.076728 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9687 12:44:26.083633 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9688 12:44:26.086775 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9689 12:44:26.093420 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9690 12:44:26.096641 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9691 12:44:26.100061 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9692 12:44:26.106885 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9693 12:44:26.110358 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9694 12:44:26.113285 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9695 12:44:26.120126 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9696 12:44:26.123329 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9697 12:44:26.129914 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9698 12:44:26.133478 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9699 12:44:26.136788 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9700 12:44:26.143052 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9701 12:44:26.146546 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9702 12:44:26.152798 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9703 12:44:26.156786 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9704 12:44:26.159641 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9705 12:44:26.166378 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9706 12:44:26.169699 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9707 12:44:26.175937 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9708 12:44:26.179153 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9709 12:44:26.182611 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9710 12:44:26.189380 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9711 12:44:26.192966 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9712 12:44:26.199175 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9713 12:44:26.202264 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9714 12:44:26.205930 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9715 12:44:26.212767 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9716 12:44:26.215883 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9717 12:44:26.222267 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9718 12:44:26.225636 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9719 12:44:26.229089 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9720 12:44:26.235295 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9721 12:44:26.238666 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9722 12:44:26.245399 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9723 12:44:26.248490 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9724 12:44:26.251921 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9725 12:44:26.258276 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9726 12:44:26.261669 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9727 12:44:26.268315 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9728 12:44:26.271792 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9729 12:44:26.278036 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9730 12:44:26.281510 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9731 12:44:26.284793 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9732 12:44:26.291287 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9733 12:44:26.294975 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9734 12:44:26.301326 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9735 12:44:26.304433 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9736 12:44:26.307952 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9737 12:44:26.314732 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9738 12:44:26.317949 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9739 12:44:26.324446 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9740 12:44:26.328073 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9741 12:44:26.334281 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9742 12:44:26.337484 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9743 12:44:26.340731 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9744 12:44:26.347662 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9745 12:44:26.351007 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9746 12:44:26.357037 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9747 12:44:26.360378 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9748 12:44:26.367045 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9749 12:44:26.370475 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9750 12:44:26.377126 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9751 12:44:26.380566 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9752 12:44:26.383487 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9753 12:44:26.390020 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9754 12:44:26.393279 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9755 12:44:26.399825 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9756 12:44:26.403527 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9757 12:44:26.406760 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9758 12:44:26.413299 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9759 12:44:26.416417 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9760 12:44:26.423265 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9761 12:44:26.426759 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9762 12:44:26.433125 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9763 12:44:26.436105 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9764 12:44:26.439887 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9765 12:44:26.446039 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9766 12:44:26.449729 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9767 12:44:26.455923 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9768 12:44:26.459426 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9769 12:44:26.466164 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9770 12:44:26.469105 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9771 12:44:26.472631 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9772 12:44:26.476196 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9773 12:44:26.482284 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9774 12:44:26.485625 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9775 12:44:26.489101 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9776 12:44:26.495757 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9777 12:44:26.498626 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9778 12:44:26.502615 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9779 12:44:26.508692 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9780 12:44:26.512058 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9781 12:44:26.515625 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9782 12:44:26.521646 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9783 12:44:26.525246 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9784 12:44:26.531992 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9785 12:44:26.535150 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9786 12:44:26.538674 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9787 12:44:26.545287 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9788 12:44:26.548497 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9789 12:44:26.551422 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9790 12:44:26.558076 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9791 12:44:26.561713 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9792 12:44:26.568181 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9793 12:44:26.571493 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9794 12:44:26.574416 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9795 12:44:26.581272 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9796 12:44:26.584656 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9797 12:44:26.590852 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9798 12:44:26.594323 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9799 12:44:26.597563 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9800 12:44:26.604434 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9801 12:44:26.607628 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9802 12:44:26.610905 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9803 12:44:26.617776 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9804 12:44:26.620635 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9805 12:44:26.623857 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9806 12:44:26.630902 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9807 12:44:26.634069 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9808 12:44:26.640510 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9809 12:44:26.643660 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9810 12:44:26.646787 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9811 12:44:26.650509 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9812 12:44:26.656758 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9813 12:44:26.660088 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9814 12:44:26.663532 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9815 12:44:26.666689 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9816 12:44:26.673300 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9817 12:44:26.676880 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9818 12:44:26.679851 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9819 12:44:26.683250 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9820 12:44:26.689583 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9821 12:44:26.693259 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9822 12:44:26.696266 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9823 12:44:26.702807 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9824 12:44:26.706317 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9825 12:44:26.713282 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9826 12:44:26.716108 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9827 12:44:26.722650 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9828 12:44:26.726162 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9829 12:44:26.729533 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9830 12:44:26.736146 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9831 12:44:26.739290 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9832 12:44:26.745641 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9833 12:44:26.748754 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9834 12:44:26.752564 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9835 12:44:26.758758 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9836 12:44:26.762143 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9837 12:44:26.768353 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9838 12:44:26.771751 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9839 12:44:26.778183 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9840 12:44:26.781523 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9841 12:44:26.784816 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9842 12:44:26.791716 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9843 12:44:26.794553 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9844 12:44:26.801325 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9845 12:44:26.804455 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9846 12:44:26.807934 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9847 12:44:26.814818 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9848 12:44:26.818047 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9849 12:44:26.824538 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9850 12:44:26.827865 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9851 12:44:26.834670 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9852 12:44:26.838072 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9853 12:44:26.844161 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9854 12:44:26.847480 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9855 12:44:26.850749 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9856 12:44:26.857731 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9857 12:44:26.860749 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9858 12:44:26.867783 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9859 12:44:26.870662 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9860 12:44:26.874082 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9861 12:44:26.881166 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9862 12:44:26.883986 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9863 12:44:26.890728 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9864 12:44:26.893794 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9865 12:44:26.897301 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9866 12:44:26.904000 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9867 12:44:26.907332 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9868 12:44:26.913460 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9869 12:44:26.916913 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9870 12:44:26.920381 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9871 12:44:26.926603 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9872 12:44:26.930333 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9873 12:44:26.936860 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9874 12:44:26.940283 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9875 12:44:26.946747 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9876 12:44:26.950235 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9877 12:44:26.953165 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9878 12:44:26.959850 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9879 12:44:26.962966 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9880 12:44:26.970005 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9881 12:44:26.972879 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9882 12:44:26.979862 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9883 12:44:26.983256 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9884 12:44:26.986180 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9885 12:44:26.992815 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9886 12:44:26.996342 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9887 12:44:27.002747 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9888 12:44:27.005985 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9889 12:44:27.009461 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9890 12:44:27.015501 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9891 12:44:27.018812 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9892 12:44:27.025722 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9893 12:44:27.029143 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9894 12:44:27.032091 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9895 12:44:27.039254 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9896 12:44:27.042266 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9897 12:44:27.048717 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9898 12:44:27.051986 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9899 12:44:27.058416 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9900 12:44:27.061740 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9901 12:44:27.068217 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9902 12:44:27.071869 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9903 12:44:27.078307 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9904 12:44:27.081478 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9905 12:44:27.084871 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9906 12:44:27.091590 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9907 12:44:27.094993 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9908 12:44:27.101597 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9909 12:44:27.104625 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9910 12:44:27.111293 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9911 12:44:27.114609 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9912 12:44:27.121067 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9913 12:44:27.124381 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9914 12:44:27.130974 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9915 12:44:27.134450 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9916 12:44:27.137299 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9917 12:44:27.143997 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9918 12:44:27.147001 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9919 12:44:27.153771 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9920 12:44:27.157091 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9921 12:44:27.164134 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9922 12:44:27.166755 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9923 12:44:27.173465 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9924 12:44:27.177199 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9925 12:44:27.183543 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9926 12:44:27.186748 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9927 12:44:27.189935 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9928 12:44:27.196656 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9929 12:44:27.199890 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9930 12:44:27.206944 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9931 12:44:27.210071 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9932 12:44:27.216681 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9933 12:44:27.219734 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9934 12:44:27.223080 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9935 12:44:27.229846 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9936 12:44:27.233314 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9937 12:44:27.239548 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9938 12:44:27.242824 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9939 12:44:27.249804 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9940 12:44:27.252779 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9941 12:44:27.259225 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9942 12:44:27.263149 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9943 12:44:27.265990 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9944 12:44:27.272777 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9945 12:44:27.276377 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9946 12:44:27.282599 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9947 12:44:27.286294 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9948 12:44:27.292251 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9949 12:44:27.295898 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9950 12:44:27.302397 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9951 12:44:27.305349 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9952 12:44:27.312157 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9953 12:44:27.315928 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9954 12:44:27.321877 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9955 12:44:27.325479 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9956 12:44:27.332231 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9957 12:44:27.335718 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9958 12:44:27.341938 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9959 12:44:27.345340 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9960 12:44:27.348705 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9961 12:44:27.355126 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9962 12:44:27.358716 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9963 12:44:27.365168 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9964 12:44:27.368388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9965 12:44:27.375284 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9966 12:44:27.378608 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9967 12:44:27.384747 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9968 12:44:27.391655 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9969 12:44:27.394754 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9970 12:44:27.401665 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9971 12:44:27.404770 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9972 12:44:27.411589 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9973 12:44:27.414408 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9974 12:44:27.421400 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9975 12:44:27.424224 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9976 12:44:27.428024 INFO: [APUAPC] vio 0
9977 12:44:27.431139 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9978 12:44:27.434322 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9979 12:44:27.437588 INFO: [APUAPC] D0_APC_0: 0x400510
9980 12:44:27.441301 INFO: [APUAPC] D0_APC_1: 0x0
9981 12:44:27.444081 INFO: [APUAPC] D0_APC_2: 0x1540
9982 12:44:27.447400 INFO: [APUAPC] D0_APC_3: 0x0
9983 12:44:27.450676 INFO: [APUAPC] D1_APC_0: 0xffffffff
9984 12:44:27.454165 INFO: [APUAPC] D1_APC_1: 0xffffffff
9985 12:44:27.457191 INFO: [APUAPC] D1_APC_2: 0x3fffff
9986 12:44:27.460458 INFO: [APUAPC] D1_APC_3: 0x0
9987 12:44:27.463896 INFO: [APUAPC] D2_APC_0: 0xffffffff
9988 12:44:27.467125 INFO: [APUAPC] D2_APC_1: 0xffffffff
9989 12:44:27.470470 INFO: [APUAPC] D2_APC_2: 0x3fffff
9990 12:44:27.473618 INFO: [APUAPC] D2_APC_3: 0x0
9991 12:44:27.477033 INFO: [APUAPC] D3_APC_0: 0xffffffff
9992 12:44:27.480414 INFO: [APUAPC] D3_APC_1: 0xffffffff
9993 12:44:27.483782 INFO: [APUAPC] D3_APC_2: 0x3fffff
9994 12:44:27.486714 INFO: [APUAPC] D3_APC_3: 0x0
9995 12:44:27.490365 INFO: [APUAPC] D4_APC_0: 0xffffffff
9996 12:44:27.493529 INFO: [APUAPC] D4_APC_1: 0xffffffff
9997 12:44:27.496923 INFO: [APUAPC] D4_APC_2: 0x3fffff
9998 12:44:27.500092 INFO: [APUAPC] D4_APC_3: 0x0
9999 12:44:27.503251 INFO: [APUAPC] D5_APC_0: 0xffffffff
10000 12:44:27.506632 INFO: [APUAPC] D5_APC_1: 0xffffffff
10001 12:44:27.509897 INFO: [APUAPC] D5_APC_2: 0x3fffff
10002 12:44:27.512902 INFO: [APUAPC] D5_APC_3: 0x0
10003 12:44:27.516345 INFO: [APUAPC] D6_APC_0: 0xffffffff
10004 12:44:27.519449 INFO: [APUAPC] D6_APC_1: 0xffffffff
10005 12:44:27.523043 INFO: [APUAPC] D6_APC_2: 0x3fffff
10006 12:44:27.526152 INFO: [APUAPC] D6_APC_3: 0x0
10007 12:44:27.529631 INFO: [APUAPC] D7_APC_0: 0xffffffff
10008 12:44:27.533127 INFO: [APUAPC] D7_APC_1: 0xffffffff
10009 12:44:27.536180 INFO: [APUAPC] D7_APC_2: 0x3fffff
10010 12:44:27.539567 INFO: [APUAPC] D7_APC_3: 0x0
10011 12:44:27.542958 INFO: [APUAPC] D8_APC_0: 0xffffffff
10012 12:44:27.546182 INFO: [APUAPC] D8_APC_1: 0xffffffff
10013 12:44:27.549499 INFO: [APUAPC] D8_APC_2: 0x3fffff
10014 12:44:27.552401 INFO: [APUAPC] D8_APC_3: 0x0
10015 12:44:27.555760 INFO: [APUAPC] D9_APC_0: 0xffffffff
10016 12:44:27.559130 INFO: [APUAPC] D9_APC_1: 0xffffffff
10017 12:44:27.562457 INFO: [APUAPC] D9_APC_2: 0x3fffff
10018 12:44:27.565945 INFO: [APUAPC] D9_APC_3: 0x0
10019 12:44:27.568887 INFO: [APUAPC] D10_APC_0: 0xffffffff
10020 12:44:27.572252 INFO: [APUAPC] D10_APC_1: 0xffffffff
10021 12:44:27.575682 INFO: [APUAPC] D10_APC_2: 0x3fffff
10022 12:44:27.579071 INFO: [APUAPC] D10_APC_3: 0x0
10023 12:44:27.581939 INFO: [APUAPC] D11_APC_0: 0xffffffff
10024 12:44:27.585221 INFO: [APUAPC] D11_APC_1: 0xffffffff
10025 12:44:27.588563 INFO: [APUAPC] D11_APC_2: 0x3fffff
10026 12:44:27.592049 INFO: [APUAPC] D11_APC_3: 0x0
10027 12:44:27.595389 INFO: [APUAPC] D12_APC_0: 0xffffffff
10028 12:44:27.598705 INFO: [APUAPC] D12_APC_1: 0xffffffff
10029 12:44:27.601941 INFO: [APUAPC] D12_APC_2: 0x3fffff
10030 12:44:27.605300 INFO: [APUAPC] D12_APC_3: 0x0
10031 12:44:27.608695 INFO: [APUAPC] D13_APC_0: 0xffffffff
10032 12:44:27.611721 INFO: [APUAPC] D13_APC_1: 0xffffffff
10033 12:44:27.615067 INFO: [APUAPC] D13_APC_2: 0x3fffff
10034 12:44:27.618042 INFO: [APUAPC] D13_APC_3: 0x0
10035 12:44:27.621665 INFO: [APUAPC] D14_APC_0: 0xffffffff
10036 12:44:27.624967 INFO: [APUAPC] D14_APC_1: 0xffffffff
10037 12:44:27.628289 INFO: [APUAPC] D14_APC_2: 0x3fffff
10038 12:44:27.631804 INFO: [APUAPC] D14_APC_3: 0x0
10039 12:44:27.635052 INFO: [APUAPC] D15_APC_0: 0xffffffff
10040 12:44:27.637838 INFO: [APUAPC] D15_APC_1: 0xffffffff
10041 12:44:27.641674 INFO: [APUAPC] D15_APC_2: 0x3fffff
10042 12:44:27.644599 INFO: [APUAPC] D15_APC_3: 0x0
10043 12:44:27.648111 INFO: [APUAPC] APC_CON: 0x4
10044 12:44:27.651142 INFO: [NOCDAPC] D0_APC_0: 0x0
10045 12:44:27.654305 INFO: [NOCDAPC] D0_APC_1: 0x0
10046 12:44:27.657621 INFO: [NOCDAPC] D1_APC_0: 0x0
10047 12:44:27.661004 INFO: [NOCDAPC] D1_APC_1: 0xfff
10048 12:44:27.664359 INFO: [NOCDAPC] D2_APC_0: 0x0
10049 12:44:27.664443 INFO: [NOCDAPC] D2_APC_1: 0xfff
10050 12:44:27.667665 INFO: [NOCDAPC] D3_APC_0: 0x0
10051 12:44:27.671085 INFO: [NOCDAPC] D3_APC_1: 0xfff
10052 12:44:27.674021 INFO: [NOCDAPC] D4_APC_0: 0x0
10053 12:44:27.677470 INFO: [NOCDAPC] D4_APC_1: 0xfff
10054 12:44:27.680636 INFO: [NOCDAPC] D5_APC_0: 0x0
10055 12:44:27.684054 INFO: [NOCDAPC] D5_APC_1: 0xfff
10056 12:44:27.687285 INFO: [NOCDAPC] D6_APC_0: 0x0
10057 12:44:27.690508 INFO: [NOCDAPC] D6_APC_1: 0xfff
10058 12:44:27.693618 INFO: [NOCDAPC] D7_APC_0: 0x0
10059 12:44:27.697055 INFO: [NOCDAPC] D7_APC_1: 0xfff
10060 12:44:27.700332 INFO: [NOCDAPC] D8_APC_0: 0x0
10061 12:44:27.703622 INFO: [NOCDAPC] D8_APC_1: 0xfff
10062 12:44:27.703705 INFO: [NOCDAPC] D9_APC_0: 0x0
10063 12:44:27.706968 INFO: [NOCDAPC] D9_APC_1: 0xfff
10064 12:44:27.710341 INFO: [NOCDAPC] D10_APC_0: 0x0
10065 12:44:27.713394 INFO: [NOCDAPC] D10_APC_1: 0xfff
10066 12:44:27.716805 INFO: [NOCDAPC] D11_APC_0: 0x0
10067 12:44:27.720065 INFO: [NOCDAPC] D11_APC_1: 0xfff
10068 12:44:27.723390 INFO: [NOCDAPC] D12_APC_0: 0x0
10069 12:44:27.726609 INFO: [NOCDAPC] D12_APC_1: 0xfff
10070 12:44:27.730041 INFO: [NOCDAPC] D13_APC_0: 0x0
10071 12:44:27.733289 INFO: [NOCDAPC] D13_APC_1: 0xfff
10072 12:44:27.736632 INFO: [NOCDAPC] D14_APC_0: 0x0
10073 12:44:27.739749 INFO: [NOCDAPC] D14_APC_1: 0xfff
10074 12:44:27.743547 INFO: [NOCDAPC] D15_APC_0: 0x0
10075 12:44:27.746594 INFO: [NOCDAPC] D15_APC_1: 0xfff
10076 12:44:27.749421 INFO: [NOCDAPC] APC_CON: 0x4
10077 12:44:27.753181 INFO: [APUAPC] set_apusys_apc done
10078 12:44:27.753265 INFO: [DEVAPC] devapc_init done
10079 12:44:27.759460 INFO: GICv3 without legacy support detected.
10080 12:44:27.762728 INFO: ARM GICv3 driver initialized in EL3
10081 12:44:27.766578 INFO: Maximum SPI INTID supported: 639
10082 12:44:27.769534 INFO: BL31: Initializing runtime services
10083 12:44:27.776221 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10084 12:44:27.779711 INFO: SPM: enable CPC mode
10085 12:44:27.782583 INFO: mcdi ready for mcusys-off-idle and system suspend
10086 12:44:27.789198 INFO: BL31: Preparing for EL3 exit to normal world
10087 12:44:27.792653 INFO: Entry point address = 0x80000000
10088 12:44:27.795969 INFO: SPSR = 0x8
10089 12:44:27.800407
10090 12:44:27.800490
10091 12:44:27.800556
10092 12:44:27.803311 Starting depthcharge on Spherion...
10093 12:44:27.803394
10094 12:44:27.803459 Wipe memory regions:
10095 12:44:27.803521
10096 12:44:27.804164 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10097 12:44:27.804270 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10098 12:44:27.804354 Setting prompt string to ['asurada:']
10099 12:44:27.804431 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10100 12:44:27.806972 [0x00000040000000, 0x00000054600000)
10101 12:44:27.929267
10102 12:44:27.929423 [0x00000054660000, 0x00000080000000)
10103 12:44:28.190045
10104 12:44:28.190202 [0x000000821a7280, 0x000000ffe64000)
10105 12:44:28.934362
10106 12:44:28.934518 [0x00000100000000, 0x00000240000000)
10107 12:44:30.824398
10108 12:44:30.827623 Initializing XHCI USB controller at 0x11200000.
10109 12:44:31.865622
10110 12:44:31.869129 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10111 12:44:31.869700
10112 12:44:31.870075
10113 12:44:31.870424
10114 12:44:31.871228 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10116 12:44:31.972494 asurada: tftpboot 192.168.201.1 10724879/tftp-deploy-49u57mqi/kernel/image.itb 10724879/tftp-deploy-49u57mqi/kernel/cmdline
10117 12:44:31.973069 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10118 12:44:31.973537 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10119 12:44:31.977814 tftpboot 192.168.201.1 10724879/tftp-deploy-49u57mqi/kernel/image.itp-deploy-49u57mqi/kernel/cmdline
10120 12:44:31.978428
10121 12:44:31.978774 Waiting for link
10122 12:44:32.138381
10123 12:44:32.138989 R8152: Initializing
10124 12:44:32.139371
10125 12:44:32.141430 Version 6 (ocp_data = 5c30)
10126 12:44:32.141895
10127 12:44:32.144419 R8152: Done initializing
10128 12:44:32.144880
10129 12:44:32.145267 Adding net device
10130 12:44:34.044436
10131 12:44:34.044577 done.
10132 12:44:34.044686
10133 12:44:34.044747 MAC: 00:24:32:30:78:ff
10134 12:44:34.044806
10135 12:44:34.047830 Sending DHCP discover... done.
10136 12:44:34.047913
10137 12:44:34.050717 Waiting for reply... done.
10138 12:44:34.050865
10139 12:44:34.054266 Sending DHCP request... done.
10140 12:44:34.054375
10141 12:44:34.059934 Waiting for reply... done.
10142 12:44:34.060017
10143 12:44:34.060083 My ip is 192.168.201.21
10144 12:44:34.060155
10145 12:44:34.063308 The DHCP server ip is 192.168.201.1
10146 12:44:34.063393
10147 12:44:34.069832 TFTP server IP predefined by user: 192.168.201.1
10148 12:44:34.069917
10149 12:44:34.076667 Bootfile predefined by user: 10724879/tftp-deploy-49u57mqi/kernel/image.itb
10150 12:44:34.076751
10151 12:44:34.079358 Sending tftp read request... done.
10152 12:44:34.079442
10153 12:44:34.083488 Waiting for the transfer...
10154 12:44:34.083572
10155 12:44:34.630432 00000000 ################################################################
10156 12:44:34.630611
10157 12:44:35.177505 00080000 ################################################################
10158 12:44:35.177709
10159 12:44:35.710861 00100000 ################################################################
10160 12:44:35.711010
10161 12:44:36.236463 00180000 ################################################################
10162 12:44:36.236612
10163 12:44:36.776343 00200000 ################################################################
10164 12:44:36.776496
10165 12:44:37.340979 00280000 ################################################################
10166 12:44:37.341188
10167 12:44:37.915644 00300000 ################################################################
10168 12:44:37.915804
10169 12:44:38.495134 00380000 ################################################################
10170 12:44:38.495278
10171 12:44:39.070427 00400000 ################################################################
10172 12:44:39.070564
10173 12:44:39.633170 00480000 ################################################################
10174 12:44:39.633344
10175 12:44:40.184617 00500000 ################################################################
10176 12:44:40.184761
10177 12:44:40.741888 00580000 ################################################################
10178 12:44:40.742058
10179 12:44:41.276009 00600000 ################################################################
10180 12:44:41.276192
10181 12:44:41.831661 00680000 ################################################################
10182 12:44:41.831839
10183 12:44:42.382081 00700000 ################################################################
10184 12:44:42.382261
10185 12:44:42.927938 00780000 ################################################################
10186 12:44:42.928087
10187 12:44:43.496423 00800000 ################################################################
10188 12:44:43.496577
10189 12:44:44.052350 00880000 ################################################################
10190 12:44:44.052507
10191 12:44:44.617897 00900000 ################################################################
10192 12:44:44.618056
10193 12:44:45.195857 00980000 ################################################################
10194 12:44:45.196011
10195 12:44:45.774320 00a00000 ################################################################
10196 12:44:45.774477
10197 12:44:46.354328 00a80000 ################################################################
10198 12:44:46.354468
10199 12:44:46.923392 00b00000 ################################################################
10200 12:44:46.923543
10201 12:44:47.501633 00b80000 ################################################################
10202 12:44:47.501809
10203 12:44:48.063446 00c00000 ################################################################
10204 12:44:48.063603
10205 12:44:48.629932 00c80000 ################################################################
10206 12:44:48.630113
10207 12:44:49.188545 00d00000 ################################################################
10208 12:44:49.188682
10209 12:44:49.744065 00d80000 ################################################################
10210 12:44:49.744224
10211 12:44:50.308365 00e00000 ################################################################
10212 12:44:50.308522
10213 12:44:50.876178 00e80000 ################################################################
10214 12:44:50.876353
10215 12:44:51.449860 00f00000 ################################################################
10216 12:44:51.450036
10217 12:44:52.022762 00f80000 ################################################################
10218 12:44:52.022938
10219 12:44:52.598411 01000000 ################################################################
10220 12:44:52.598564
10221 12:44:53.130205 01080000 ################################################################
10222 12:44:53.130360
10223 12:44:53.661084 01100000 ################################################################
10224 12:44:53.661304
10225 12:44:54.193012 01180000 ################################################################
10226 12:44:54.193171
10227 12:44:54.721055 01200000 ################################################################
10228 12:44:54.721224
10229 12:44:55.270362 01280000 ################################################################
10230 12:44:55.270526
10231 12:44:55.817136 01300000 ################################################################
10232 12:44:55.817317
10233 12:44:56.367705 01380000 ################################################################
10234 12:44:56.367863
10235 12:44:56.907195 01400000 ################################################################
10236 12:44:56.907344
10237 12:44:57.460429 01480000 ################################################################
10238 12:44:57.460581
10239 12:44:58.016119 01500000 ################################################################
10240 12:44:58.016261
10241 12:44:58.571149 01580000 ################################################################
10242 12:44:58.571305
10243 12:44:59.120491 01600000 ################################################################
10244 12:44:59.120656
10245 12:44:59.662197 01680000 ################################################################
10246 12:44:59.662387
10247 12:45:00.211698 01700000 ################################################################
10248 12:45:00.211853
10249 12:45:00.753234 01780000 ################################################################
10250 12:45:00.753381
10251 12:45:01.316837 01800000 ################################################################
10252 12:45:01.316993
10253 12:45:01.872542 01880000 ################################################################
10254 12:45:01.872716
10255 12:45:02.405658 01900000 ################################################################
10256 12:45:02.405822
10257 12:45:02.939854 01980000 ################################################################
10258 12:45:02.940015
10259 12:45:03.470067 01a00000 ################################################################
10260 12:45:03.470206
10261 12:45:03.824880 01a80000 ########################################### done.
10262 12:45:03.825026
10263 12:45:03.828919 The bootfile was 28134582 bytes long.
10264 12:45:03.829072
10265 12:45:03.831865 Sending tftp read request... done.
10266 12:45:03.831963
10267 12:45:03.832033 Waiting for the transfer...
10268 12:45:03.832095
10269 12:45:03.834583 00000000 # done.
10270 12:45:03.834700
10271 12:45:03.841668 Command line loaded dynamically from TFTP file: 10724879/tftp-deploy-49u57mqi/kernel/cmdline
10272 12:45:03.841819
10273 12:45:03.861408 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10724879/extract-nfsrootfs-vz66w8m2,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10274 12:45:03.861578
10275 12:45:03.864461 Loading FIT.
10276 12:45:03.864587
10277 12:45:03.867403 Image ramdisk-1 has 17643246 bytes.
10278 12:45:03.867516
10279 12:45:03.867609 Image fdt-1 has 46924 bytes.
10280 12:45:03.871068
10281 12:45:03.871174 Image kernel-1 has 10442380 bytes.
10282 12:45:03.871265
10283 12:45:03.880822 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10284 12:45:03.880922
10285 12:45:03.897577 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10286 12:45:03.900533
10287 12:45:03.903841 Choosing best match conf-1 for compat google,spherion-rev2.
10288 12:45:03.908348
10289 12:45:03.912579 Connected to device vid:did:rid of 1ae0:0028:00
10290 12:45:03.920150
10291 12:45:03.923919 tpm_get_response: command 0x17b, return code 0x0
10292 12:45:03.924058
10293 12:45:03.926218 ec_init: CrosEC protocol v3 supported (256, 248)
10294 12:45:03.930996
10295 12:45:03.933974 tpm_cleanup: add release locality here.
10296 12:45:03.934095
10297 12:45:03.934197 Shutting down all USB controllers.
10298 12:45:03.937327
10299 12:45:03.937434 Removing current net device
10300 12:45:03.937528
10301 12:45:03.943545 Exiting depthcharge with code 4 at timestamp: 65429042
10302 12:45:03.943659
10303 12:45:03.946606 LZMA decompressing kernel-1 to 0x821a6718
10304 12:45:03.946717
10305 12:45:03.950264 LZMA decompressing kernel-1 to 0x40000000
10306 12:45:05.260642
10307 12:45:05.260808 jumping to kernel
10308 12:45:05.261364 end: 2.2.4 bootloader-commands (duration 00:00:37) [common]
10309 12:45:05.261497 start: 2.2.5 auto-login-action (timeout 00:03:48) [common]
10310 12:45:05.261602 Setting prompt string to ['Linux version [0-9]']
10311 12:45:05.261705 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10312 12:45:05.261807 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10313 12:45:05.342458
10314 12:45:05.346228 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10315 12:45:05.349681 start: 2.2.5.1 login-action (timeout 00:03:48) [common]
10316 12:45:05.349772 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10317 12:45:05.349865 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10318 12:45:05.349951 Using line separator: #'\n'#
10319 12:45:05.350022 No login prompt set.
10320 12:45:05.350086 Parsing kernel messages
10321 12:45:05.350142 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10322 12:45:05.350246 [login-action] Waiting for messages, (timeout 00:03:48)
10323 12:45:05.368780 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j35827-arm64-gcc-10-defconfig-arm64-chromebook-fwl9s) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jun 14 12:30:40 UTC 2023
10324 12:45:05.372200 [ 0.000000] random: crng init done
10325 12:45:05.375616 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10326 12:45:05.379137 [ 0.000000] efi: UEFI not found.
10327 12:45:05.389179 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10328 12:45:05.395623 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10329 12:45:05.405600 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10330 12:45:05.415091 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10331 12:45:05.421934 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10332 12:45:05.428505 [ 0.000000] printk: bootconsole [mtk8250] enabled
10333 12:45:05.434757 [ 0.000000] NUMA: No NUMA configuration found
10334 12:45:05.441542 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10335 12:45:05.444628 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10336 12:45:05.448044 [ 0.000000] Zone ranges:
10337 12:45:05.454687 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10338 12:45:05.458165 [ 0.000000] DMA32 empty
10339 12:45:05.464566 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10340 12:45:05.468018 [ 0.000000] Movable zone start for each node
10341 12:45:05.471081 [ 0.000000] Early memory node ranges
10342 12:45:05.477969 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10343 12:45:05.484352 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10344 12:45:05.491354 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10345 12:45:05.497615 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10346 12:45:05.504446 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10347 12:45:05.510681 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10348 12:45:05.566685 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10349 12:45:05.573073 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10350 12:45:05.580117 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10351 12:45:05.583002 [ 0.000000] psci: probing for conduit method from DT.
10352 12:45:05.589880 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10353 12:45:05.592897 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10354 12:45:05.599565 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10355 12:45:05.602916 [ 0.000000] psci: SMC Calling Convention v1.2
10356 12:45:05.609095 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10357 12:45:05.612600 [ 0.000000] Detected VIPT I-cache on CPU0
10358 12:45:05.619149 [ 0.000000] CPU features: detected: GIC system register CPU interface
10359 12:45:05.625508 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10360 12:45:05.632189 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10361 12:45:05.638671 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10362 12:45:05.648577 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10363 12:45:05.655203 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10364 12:45:05.658822 [ 0.000000] alternatives: applying boot alternatives
10365 12:45:05.665480 [ 0.000000] Fallback order for Node 0: 0
10366 12:45:05.672002 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10367 12:45:05.675626 [ 0.000000] Policy zone: Normal
10368 12:45:05.694924 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10724879/extract-nfsrootfs-vz66w8m2,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10369 12:45:05.704847 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10370 12:45:05.717374 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10371 12:45:05.726921 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10372 12:45:05.733467 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10373 12:45:05.736765 <6>[ 0.000000] software IO TLB: area num 8.
10374 12:45:05.793708 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10375 12:45:05.942539 <6>[ 0.000000] Memory: 7953932K/8385536K available (17984K kernel code, 4098K rwdata, 15868K rodata, 8384K init, 615K bss, 398836K reserved, 32768K cma-reserved)
10376 12:45:05.949514 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10377 12:45:05.955923 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10378 12:45:05.958970 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10379 12:45:05.965501 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10380 12:45:05.972192 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10381 12:45:05.975641 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10382 12:45:05.985913 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10383 12:45:05.992446 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10384 12:45:05.998595 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10385 12:45:06.005515 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10386 12:45:06.008535 <6>[ 0.000000] GICv3: 608 SPIs implemented
10387 12:45:06.012360 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10388 12:45:06.018493 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10389 12:45:06.021955 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10390 12:45:06.028718 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10391 12:45:06.041789 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10392 12:45:06.054972 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10393 12:45:06.061298 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10394 12:45:06.068902 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10395 12:45:06.082582 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10396 12:45:06.089156 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10397 12:45:06.095572 <6>[ 0.009226] Console: colour dummy device 80x25
10398 12:45:06.105757 <6>[ 0.013951] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10399 12:45:06.112153 <6>[ 0.024458] pid_max: default: 32768 minimum: 301
10400 12:45:06.115398 <6>[ 0.029332] LSM: Security Framework initializing
10401 12:45:06.122163 <6>[ 0.034272] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10402 12:45:06.132064 <6>[ 0.042129] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10403 12:45:06.142087 <6>[ 0.051550] cblist_init_generic: Setting adjustable number of callback queues.
10404 12:45:06.145172 <6>[ 0.059002] cblist_init_generic: Setting shift to 3 and lim to 1.
10405 12:45:06.151913 <6>[ 0.065341] cblist_init_generic: Setting shift to 3 and lim to 1.
10406 12:45:06.158476 <6>[ 0.071789] rcu: Hierarchical SRCU implementation.
10407 12:45:06.165013 <6>[ 0.076803] rcu: Max phase no-delay instances is 1000.
10408 12:45:06.171513 <6>[ 0.083813] EFI services will not be available.
10409 12:45:06.174880 <6>[ 0.088788] smp: Bringing up secondary CPUs ...
10410 12:45:06.183011 <6>[ 0.093839] Detected VIPT I-cache on CPU1
10411 12:45:06.189056 <6>[ 0.093913] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10412 12:45:06.195958 <6>[ 0.093943] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10413 12:45:06.198850 <6>[ 0.094280] Detected VIPT I-cache on CPU2
10414 12:45:06.209182 <6>[ 0.094332] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10415 12:45:06.215312 <6>[ 0.094348] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10416 12:45:06.218507 <6>[ 0.094608] Detected VIPT I-cache on CPU3
10417 12:45:06.225430 <6>[ 0.094655] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10418 12:45:06.231817 <6>[ 0.094669] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10419 12:45:06.238693 <6>[ 0.094974] CPU features: detected: Spectre-v4
10420 12:45:06.241662 <6>[ 0.094982] CPU features: detected: Spectre-BHB
10421 12:45:06.245274 <6>[ 0.094988] Detected PIPT I-cache on CPU4
10422 12:45:06.251719 <6>[ 0.095046] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10423 12:45:06.261549 <6>[ 0.095063] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10424 12:45:06.265022 <6>[ 0.095356] Detected PIPT I-cache on CPU5
10425 12:45:06.271650 <6>[ 0.095419] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10426 12:45:06.278339 <6>[ 0.095436] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10427 12:45:06.281775 <6>[ 0.095718] Detected PIPT I-cache on CPU6
10428 12:45:06.288194 <6>[ 0.095783] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10429 12:45:06.298103 <6>[ 0.095798] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10430 12:45:06.301455 <6>[ 0.096097] Detected PIPT I-cache on CPU7
10431 12:45:06.307748 <6>[ 0.096160] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10432 12:45:06.314243 <6>[ 0.096176] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10433 12:45:06.317459 <6>[ 0.096222] smp: Brought up 1 node, 8 CPUs
10434 12:45:06.324622 <6>[ 0.237400] SMP: Total of 8 processors activated.
10435 12:45:06.327451 <6>[ 0.242320] CPU features: detected: 32-bit EL0 Support
10436 12:45:06.337582 <6>[ 0.247717] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10437 12:45:06.344368 <6>[ 0.256517] CPU features: detected: Common not Private translations
10438 12:45:06.350874 <6>[ 0.262993] CPU features: detected: CRC32 instructions
10439 12:45:06.357458 <6>[ 0.268344] CPU features: detected: RCpc load-acquire (LDAPR)
10440 12:45:06.360413 <6>[ 0.274303] CPU features: detected: LSE atomic instructions
10441 12:45:06.367367 <6>[ 0.280085] CPU features: detected: Privileged Access Never
10442 12:45:06.373881 <6>[ 0.285865] CPU features: detected: RAS Extension Support
10443 12:45:06.380336 <6>[ 0.291508] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10444 12:45:06.383956 <6>[ 0.298728] CPU: All CPU(s) started at EL2
10445 12:45:06.389903 <6>[ 0.303045] alternatives: applying system-wide alternatives
10446 12:45:06.400461 <6>[ 0.313757] devtmpfs: initialized
10447 12:45:06.415829 <6>[ 0.322571] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10448 12:45:06.422291 <6>[ 0.332538] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10449 12:45:06.429043 <6>[ 0.340764] pinctrl core: initialized pinctrl subsystem
10450 12:45:06.431884 <6>[ 0.347434] DMI not present or invalid.
10451 12:45:06.438303 <6>[ 0.351843] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10452 12:45:06.448495 <6>[ 0.358729] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10453 12:45:06.454951 <6>[ 0.366315] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10454 12:45:06.465135 <6>[ 0.374540] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10455 12:45:06.471578 <6>[ 0.382779] audit: initializing netlink subsys (disabled)
10456 12:45:06.478187 <5>[ 0.388472] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10457 12:45:06.484979 <6>[ 0.389146] thermal_sys: Registered thermal governor 'step_wise'
10458 12:45:06.491612 <6>[ 0.396438] thermal_sys: Registered thermal governor 'power_allocator'
10459 12:45:06.494572 <6>[ 0.402693] cpuidle: using governor menu
10460 12:45:06.501195 <6>[ 0.413651] NET: Registered PF_QIPCRTR protocol family
10461 12:45:06.507758 <6>[ 0.419144] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10462 12:45:06.514672 <6>[ 0.426246] ASID allocator initialised with 32768 entries
10463 12:45:06.517696 <6>[ 0.432827] Serial: AMBA PL011 UART driver
10464 12:45:06.527992 <4>[ 0.441502] Trying to register duplicate clock ID: 134
10465 12:45:06.582204 <6>[ 0.498968] KASLR enabled
10466 12:45:06.596639 <6>[ 0.506828] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10467 12:45:06.603186 <6>[ 0.513842] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10468 12:45:06.609489 <6>[ 0.520333] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10469 12:45:06.616449 <6>[ 0.527338] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10470 12:45:06.622926 <6>[ 0.533825] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10471 12:45:06.629363 <6>[ 0.540830] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10472 12:45:06.635789 <6>[ 0.547316] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10473 12:45:06.642446 <6>[ 0.554322] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10474 12:45:06.648960 <6>[ 0.561827] ACPI: Interpreter disabled.
10475 12:45:06.655489 <6>[ 0.568209] iommu: Default domain type: Translated
10476 12:45:06.662119 <6>[ 0.573321] iommu: DMA domain TLB invalidation policy: strict mode
10477 12:45:06.665338 <5>[ 0.579974] SCSI subsystem initialized
10478 12:45:06.671881 <6>[ 0.584138] usbcore: registered new interface driver usbfs
10479 12:45:06.678415 <6>[ 0.589868] usbcore: registered new interface driver hub
10480 12:45:06.681852 <6>[ 0.595418] usbcore: registered new device driver usb
10481 12:45:06.688562 <6>[ 0.601484] pps_core: LinuxPPS API ver. 1 registered
10482 12:45:06.698023 <6>[ 0.606678] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10483 12:45:06.701487 <6>[ 0.616025] PTP clock support registered
10484 12:45:06.705099 <6>[ 0.620268] EDAC MC: Ver: 3.0.0
10485 12:45:06.711858 <6>[ 0.625405] FPGA manager framework
10486 12:45:06.718207 <6>[ 0.629082] Advanced Linux Sound Architecture Driver Initialized.
10487 12:45:06.721788 <6>[ 0.635855] vgaarb: loaded
10488 12:45:06.728025 <6>[ 0.639027] clocksource: Switched to clocksource arch_sys_counter
10489 12:45:06.731086 <5>[ 0.645469] VFS: Disk quotas dquot_6.6.0
10490 12:45:06.738077 <6>[ 0.649650] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10491 12:45:06.741544 <6>[ 0.656821] pnp: PnP ACPI: disabled
10492 12:45:06.750004 <6>[ 0.663542] NET: Registered PF_INET protocol family
10493 12:45:06.759595 <6>[ 0.669139] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10494 12:45:06.771132 <6>[ 0.681431] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10495 12:45:06.781220 <6>[ 0.690243] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10496 12:45:06.787501 <6>[ 0.698213] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10497 12:45:06.797730 <6>[ 0.706911] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10498 12:45:06.803863 <6>[ 0.716661] TCP: Hash tables configured (established 65536 bind 65536)
10499 12:45:06.810398 <6>[ 0.723510] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10500 12:45:06.820442 <6>[ 0.730707] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10501 12:45:06.827116 <6>[ 0.738397] NET: Registered PF_UNIX/PF_LOCAL protocol family
10502 12:45:06.833484 <6>[ 0.744474] RPC: Registered named UNIX socket transport module.
10503 12:45:06.836923 <6>[ 0.750618] RPC: Registered udp transport module.
10504 12:45:06.843354 <6>[ 0.755551] RPC: Registered tcp transport module.
10505 12:45:06.850205 <6>[ 0.760484] RPC: Registered tcp NFSv4.1 backchannel transport module.
10506 12:45:06.853244 <6>[ 0.767147] PCI: CLS 0 bytes, default 64
10507 12:45:06.856594 <6>[ 0.771489] Unpacking initramfs...
10508 12:45:06.873217 <6>[ 0.783593] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10509 12:45:06.883074 <6>[ 0.792253] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10510 12:45:06.886460 <6>[ 0.801094] kvm [1]: IPA Size Limit: 40 bits
10511 12:45:06.892868 <6>[ 0.805622] kvm [1]: GICv3: no GICV resource entry
10512 12:45:06.896584 <6>[ 0.810644] kvm [1]: disabling GICv2 emulation
10513 12:45:06.903219 <6>[ 0.815336] kvm [1]: GIC system register CPU interface enabled
10514 12:45:06.905995 <6>[ 0.821501] kvm [1]: vgic interrupt IRQ18
10515 12:45:06.912695 <6>[ 0.825904] kvm [1]: VHE mode initialized successfully
10516 12:45:06.919547 <5>[ 0.832279] Initialise system trusted keyrings
10517 12:45:06.926174 <6>[ 0.837086] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10518 12:45:06.933475 <6>[ 0.847100] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10519 12:45:06.940147 <5>[ 0.853508] NFS: Registering the id_resolver key type
10520 12:45:06.943172 <5>[ 0.858814] Key type id_resolver registered
10521 12:45:06.949660 <5>[ 0.863230] Key type id_legacy registered
10522 12:45:06.956543 <6>[ 0.867511] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10523 12:45:06.963092 <6>[ 0.874433] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10524 12:45:06.969373 <6>[ 0.882160] 9p: Installing v9fs 9p2000 file system support
10525 12:45:07.006497 <5>[ 0.920155] Key type asymmetric registered
10526 12:45:07.009996 <5>[ 0.924487] Asymmetric key parser 'x509' registered
10527 12:45:07.019634 <6>[ 0.929636] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10528 12:45:07.023000 <6>[ 0.937254] io scheduler mq-deadline registered
10529 12:45:07.026466 <6>[ 0.942012] io scheduler kyber registered
10530 12:45:07.044870 <6>[ 0.958790] EINJ: ACPI disabled.
10531 12:45:07.076878 <4>[ 0.984133] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10532 12:45:07.087014 <4>[ 0.994755] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10533 12:45:07.101621 <6>[ 1.015172] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10534 12:45:07.109554 <6>[ 1.023158] printk: console [ttyS0] disabled
10535 12:45:07.137745 <6>[ 1.047817] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10536 12:45:07.143812 <6>[ 1.057300] printk: console [ttyS0] enabled
10537 12:45:07.147417 <6>[ 1.057300] printk: console [ttyS0] enabled
10538 12:45:07.153839 <6>[ 1.066198] printk: bootconsole [mtk8250] disabled
10539 12:45:07.157479 <6>[ 1.066198] printk: bootconsole [mtk8250] disabled
10540 12:45:07.164096 <6>[ 1.077454] SuperH (H)SCI(F) driver initialized
10541 12:45:07.167018 <6>[ 1.082734] msm_serial: driver initialized
10542 12:45:07.181330 <6>[ 1.091662] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10543 12:45:07.191177 <6>[ 1.100212] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10544 12:45:07.197616 <6>[ 1.108753] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10545 12:45:07.207664 <6>[ 1.117380] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10546 12:45:07.217899 <6>[ 1.126086] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10547 12:45:07.224165 <6>[ 1.134803] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10548 12:45:07.234039 <6>[ 1.143343] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10549 12:45:07.240598 <6>[ 1.152149] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10550 12:45:07.250602 <6>[ 1.160696] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10551 12:45:07.262913 <6>[ 1.176469] loop: module loaded
10552 12:45:07.269493 <6>[ 1.182517] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10553 12:45:07.292718 <4>[ 1.206165] mtk-pmic-keys: Failed to locate of_node [id: -1]
10554 12:45:07.299538 <6>[ 1.213177] megasas: 07.719.03.00-rc1
10555 12:45:07.309326 <6>[ 1.222959] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10556 12:45:07.316969 <6>[ 1.230400] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10557 12:45:07.333330 <6>[ 1.246872] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10558 12:45:07.392926 <6>[ 1.299887] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10559 12:45:07.580557 <6>[ 1.494299] Freeing initrd memory: 17224K
10560 12:45:07.591026 <6>[ 1.504389] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10561 12:45:07.601790 <6>[ 1.515499] tun: Universal TUN/TAP device driver, 1.6
10562 12:45:07.605068 <6>[ 1.521557] thunder_xcv, ver 1.0
10563 12:45:07.608539 <6>[ 1.525064] thunder_bgx, ver 1.0
10564 12:45:07.611938 <6>[ 1.528559] nicpf, ver 1.0
10565 12:45:07.622445 <6>[ 1.532587] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10566 12:45:07.625397 <6>[ 1.540063] hns3: Copyright (c) 2017 Huawei Corporation.
10567 12:45:07.631945 <6>[ 1.545651] hclge is initializing
10568 12:45:07.635484 <6>[ 1.549233] e1000: Intel(R) PRO/1000 Network Driver
10569 12:45:07.642299 <6>[ 1.554362] e1000: Copyright (c) 1999-2006 Intel Corporation.
10570 12:45:07.645266 <6>[ 1.560374] e1000e: Intel(R) PRO/1000 Network Driver
10571 12:45:07.651805 <6>[ 1.565591] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10572 12:45:07.658774 <6>[ 1.571779] igb: Intel(R) Gigabit Ethernet Network Driver
10573 12:45:07.665221 <6>[ 1.577429] igb: Copyright (c) 2007-2014 Intel Corporation.
10574 12:45:07.671693 <6>[ 1.583266] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10575 12:45:07.678688 <6>[ 1.589784] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10576 12:45:07.681628 <6>[ 1.596241] sky2: driver version 1.30
10577 12:45:07.688330 <6>[ 1.601229] VFIO - User Level meta-driver version: 0.3
10578 12:45:07.695966 <6>[ 1.609427] usbcore: registered new interface driver usb-storage
10579 12:45:07.702231 <6>[ 1.615874] usbcore: registered new device driver onboard-usb-hub
10580 12:45:07.711047 <6>[ 1.624989] mt6397-rtc mt6359-rtc: registered as rtc0
10581 12:45:07.721507 <6>[ 1.630456] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-14T12:45:08 UTC (1686746708)
10582 12:45:07.724294 <6>[ 1.640037] i2c_dev: i2c /dev entries driver
10583 12:45:07.741126 <6>[ 1.651630] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10584 12:45:07.747965 <6>[ 1.661839] sdhci: Secure Digital Host Controller Interface driver
10585 12:45:07.754702 <6>[ 1.668276] sdhci: Copyright(c) Pierre Ossman
10586 12:45:07.761536 <6>[ 1.673667] Synopsys Designware Multimedia Card Interface Driver
10587 12:45:07.764918 <6>[ 1.680246] mmc0: CQHCI version 5.10
10588 12:45:07.771445 <6>[ 1.680807] sdhci-pltfm: SDHCI platform and OF driver helper
10589 12:45:07.778650 <6>[ 1.692412] ledtrig-cpu: registered to indicate activity on CPUs
10590 12:45:07.789403 <6>[ 1.699769] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10591 12:45:07.796117 <6>[ 1.707178] usbcore: registered new interface driver usbhid
10592 12:45:07.799152 <6>[ 1.713006] usbhid: USB HID core driver
10593 12:45:07.805950 <6>[ 1.717243] spi_master spi0: will run message pump with realtime priority
10594 12:45:07.850398 <6>[ 1.757543] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10595 12:45:07.868757 <6>[ 1.772497] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10596 12:45:07.872364 <6>[ 1.786079] mmc0: Command Queue Engine enabled
10597 12:45:07.879415 <6>[ 1.788133] cros-ec-spi spi0.0: Chrome EC device registered
10598 12:45:07.885947 <6>[ 1.790807] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10599 12:45:07.889033 <6>[ 1.803937] mmcblk0: mmc0:0001 DA4128 116 GiB
10600 12:45:07.903490 <6>[ 1.813645] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10601 12:45:07.909728 <6>[ 1.814814] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10602 12:45:07.916419 <6>[ 1.825036] NET: Registered PF_PACKET protocol family
10603 12:45:07.919918 <6>[ 1.830225] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10604 12:45:07.926553 <6>[ 1.834302] 9pnet: Installing 9P2000 support
10605 12:45:07.929370 <6>[ 1.840092] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10606 12:45:07.936305 <5>[ 1.843974] Key type dns_resolver registered
10607 12:45:07.943177 <6>[ 1.849825] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10608 12:45:07.946072 <6>[ 1.854187] registered taskstats version 1
10609 12:45:07.949585 <5>[ 1.864594] Loading compiled-in X.509 certificates
10610 12:45:07.983740 <4>[ 1.891002] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10611 12:45:07.994036 <4>[ 1.901765] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10612 12:45:08.004317 <3>[ 1.914763] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10613 12:45:08.017127 <6>[ 1.930493] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10614 12:45:08.023808 <6>[ 1.937299] xhci-mtk 11200000.usb: xHCI Host Controller
10615 12:45:08.030047 <6>[ 1.942803] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10616 12:45:08.040059 <6>[ 1.950656] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10617 12:45:08.047384 <6>[ 1.960088] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10618 12:45:08.053549 <6>[ 1.966290] xhci-mtk 11200000.usb: xHCI Host Controller
10619 12:45:08.060108 <6>[ 1.971788] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10620 12:45:08.066581 <6>[ 1.979447] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10621 12:45:08.073994 <6>[ 1.987371] hub 1-0:1.0: USB hub found
10622 12:45:08.076858 <6>[ 1.991407] hub 1-0:1.0: 1 port detected
10623 12:45:08.086821 <6>[ 1.995753] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10624 12:45:08.090206 <6>[ 2.004565] hub 2-0:1.0: USB hub found
10625 12:45:08.093663 <6>[ 2.008599] hub 2-0:1.0: 1 port detected
10626 12:45:08.102297 <6>[ 2.015634] mtk-msdc 11f70000.mmc: Got CD GPIO
10627 12:45:08.119019 <6>[ 2.029172] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10628 12:45:08.125560 <6>[ 2.037204] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10629 12:45:08.135223 <4>[ 2.045175] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10630 12:45:08.145244 <6>[ 2.054832] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10631 12:45:08.151911 <6>[ 2.062914] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10632 12:45:08.161748 <6>[ 2.070943] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10633 12:45:08.168082 <6>[ 2.078865] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10634 12:45:08.175313 <6>[ 2.086686] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10635 12:45:08.185123 <6>[ 2.094514] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10636 12:45:08.194786 <6>[ 2.105126] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10637 12:45:08.201348 <6>[ 2.113498] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10638 12:45:08.211561 <6>[ 2.121852] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10639 12:45:08.221714 <6>[ 2.130196] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10640 12:45:08.228120 <6>[ 2.138539] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10641 12:45:08.237774 <6>[ 2.146883] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10642 12:45:08.244436 <6>[ 2.155227] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10643 12:45:08.254479 <6>[ 2.163571] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10644 12:45:08.261434 <6>[ 2.171914] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10645 12:45:08.271164 <6>[ 2.180258] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10646 12:45:08.277789 <6>[ 2.188601] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10647 12:45:08.287584 <6>[ 2.196945] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10648 12:45:08.294471 <6>[ 2.205289] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10649 12:45:08.304029 <6>[ 2.213633] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10650 12:45:08.310634 <6>[ 2.221977] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10651 12:45:08.317205 <6>[ 2.230902] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10652 12:45:08.324447 <6>[ 2.238396] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10653 12:45:08.331503 <6>[ 2.245487] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10654 12:45:08.342151 <6>[ 2.252635] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10655 12:45:08.348459 <6>[ 2.259942] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10656 12:45:08.358628 <6>[ 2.266852] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10657 12:45:08.365235 <6>[ 2.275993] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10658 12:45:08.375427 <6>[ 2.285121] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10659 12:45:08.384773 <6>[ 2.294422] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10660 12:45:08.394869 <6>[ 2.303897] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10661 12:45:08.404666 <6>[ 2.313372] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10662 12:45:08.414931 <6>[ 2.322499] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10663 12:45:08.421595 <6>[ 2.331977] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10664 12:45:08.430992 <6>[ 2.341104] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10665 12:45:08.441314 <6>[ 2.350411] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10666 12:45:08.451161 <6>[ 2.360577] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10667 12:45:08.461261 <6>[ 2.371958] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10668 12:45:08.468573 <6>[ 2.382085] Trying to probe devices needed for running init ...
10669 12:45:08.485037 <6>[ 2.395294] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10670 12:45:08.511809 <6>[ 2.425335] hub 2-1:1.0: USB hub found
10671 12:45:08.515131 <6>[ 2.429708] hub 2-1:1.0: 3 ports detected
10672 12:45:08.636738 <6>[ 2.547297] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10673 12:45:08.791450 <6>[ 2.705007] hub 1-1:1.0: USB hub found
10674 12:45:08.794584 <6>[ 2.709454] hub 1-1:1.0: 4 ports detected
10675 12:45:08.872928 <6>[ 2.783537] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10676 12:45:09.116514 <6>[ 3.027302] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10677 12:45:09.250034 <6>[ 3.163587] hub 1-1.4:1.0: USB hub found
10678 12:45:09.253252 <6>[ 3.168273] hub 1-1.4:1.0: 2 ports detected
10679 12:45:09.552754 <6>[ 3.463299] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10680 12:45:09.744750 <6>[ 3.655298] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10681 12:45:20.749495 <6>[ 14.667620] ALSA device list:
10682 12:45:20.755836 <6>[ 14.670848] No soundcards found.
10683 12:45:20.762259 <6>[ 14.677213] Freeing unused kernel memory: 8384K
10684 12:45:20.765803 <6>[ 14.682118] Run /init as init process
10685 12:45:20.774176 Loading, please wait...
10686 12:45:20.790785 Starting version 247.3-7+deb11u2
10687 12:45:21.081961 <6>[ 14.993970] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10688 12:45:21.088617 <6>[ 15.002406] remoteproc remoteproc0: scp is available
10689 12:45:21.098420 <4>[ 15.007732] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10690 12:45:21.102146 <6>[ 15.017599] remoteproc remoteproc0: powering up scp
10691 12:45:21.112104 <3>[ 15.021076] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10692 12:45:21.122062 <4>[ 15.022757] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10693 12:45:21.128189 <6>[ 15.026618] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10694 12:45:21.138671 <6>[ 15.026643] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10695 12:45:21.144670 <6>[ 15.026653] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10696 12:45:21.154778 <3>[ 15.030823] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10697 12:45:21.161099 <3>[ 15.047049] remoteproc remoteproc0: request_firmware failed: -2
10698 12:45:21.167939 <3>[ 15.048197] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10699 12:45:21.171248 <6>[ 15.050170] mc: Linux media interface: v0.10
10700 12:45:21.177696 <6>[ 15.066181] videodev: Linux video capture interface: v2.00
10701 12:45:21.187485 <3>[ 15.076639] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10702 12:45:21.194204 <4>[ 15.088439] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10703 12:45:21.200913 <3>[ 15.092514] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10704 12:45:21.207619 <4>[ 15.103101] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10705 12:45:21.217584 <3>[ 15.106353] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10706 12:45:21.223803 <6>[ 15.133054] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10707 12:45:21.233679 <3>[ 15.137163] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10708 12:45:21.240284 <6>[ 15.152363] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10709 12:45:21.246899 <3>[ 15.152889] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10710 12:45:21.253653 <6>[ 15.159766] pci_bus 0000:00: root bus resource [bus 00-ff]
10711 12:45:21.260342 <3>[ 15.167868] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10712 12:45:21.270249 <6>[ 15.173607] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10713 12:45:21.277522 <3>[ 15.181683] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10714 12:45:21.284450 <4>[ 15.182281] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10715 12:45:21.291051 <4>[ 15.182281] Fallback method does not support PEC.
10716 12:45:21.301663 <6>[ 15.188781] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10717 12:45:21.307986 <3>[ 15.196860] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10718 12:45:21.318162 <3>[ 15.198216] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10719 12:45:21.328045 <6>[ 15.199465] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10720 12:45:21.334813 <6>[ 15.199776] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10721 12:45:21.341587 <6>[ 15.210519] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10722 12:45:21.351517 <3>[ 15.220400] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10723 12:45:21.357645 <3>[ 15.221724] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10724 12:45:21.367616 <6>[ 15.223413] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10725 12:45:21.374070 <6>[ 15.227531] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10726 12:45:21.384226 <6>[ 15.228510] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10727 12:45:21.390751 <3>[ 15.237321] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10728 12:45:21.397441 <6>[ 15.247432] pci 0000:00:00.0: supports D1 D2
10729 12:45:21.404233 <3>[ 15.256512] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10730 12:45:21.410479 <6>[ 15.262693] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10731 12:45:21.413866 <6>[ 15.263439] Bluetooth: Core ver 2.22
10732 12:45:21.420475 <6>[ 15.263484] NET: Registered PF_BLUETOOTH protocol family
10733 12:45:21.427182 <6>[ 15.263487] Bluetooth: HCI device and connection manager initialized
10734 12:45:21.430230 <6>[ 15.263500] Bluetooth: HCI socket layer initialized
10735 12:45:21.437020 <6>[ 15.263505] Bluetooth: L2CAP socket layer initialized
10736 12:45:21.443739 <6>[ 15.263514] Bluetooth: SCO socket layer initialized
10737 12:45:21.450523 <3>[ 15.270776] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10738 12:45:21.460424 <6>[ 15.281171] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10739 12:45:21.466454 <3>[ 15.286683] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10740 12:45:21.473181 <6>[ 15.296103] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10741 12:45:21.483270 <4>[ 15.296997] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10742 12:45:21.489952 <4>[ 15.297009] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10743 12:45:21.499777 <3>[ 15.303482] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10744 12:45:21.506553 <6>[ 15.304365] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10745 12:45:21.516172 <6>[ 15.305774] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10746 12:45:21.523002 <6>[ 15.305890] usbcore: registered new interface driver uvcvideo
10747 12:45:21.532984 <6>[ 15.311598] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10748 12:45:21.536017 <6>[ 15.312287] usbcore: registered new interface driver btusb
10749 12:45:21.549523 <4>[ 15.312754] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10750 12:45:21.552656 <3>[ 15.312763] Bluetooth: hci0: Failed to load firmware file (-2)
10751 12:45:21.559472 <3>[ 15.312766] Bluetooth: hci0: Failed to set up firmware (-2)
10752 12:45:21.568830 <4>[ 15.312769] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10753 12:45:21.579180 <3>[ 15.316124] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10754 12:45:21.585638 <6>[ 15.324190] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10755 12:45:21.592265 <6>[ 15.335354] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10756 12:45:21.599115 <6>[ 15.340450] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10757 12:45:21.605211 <6>[ 15.371325] r8152 2-1.3:1.0 eth0: v1.12.13
10758 12:45:21.608753 <6>[ 15.379051] pci 0000:01:00.0: supports D1 D2
10759 12:45:21.615822 <6>[ 15.387219] usbcore: registered new interface driver r8152
10760 12:45:21.621729 <6>[ 15.393323] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10761 12:45:21.628543 <6>[ 15.425788] usbcore: registered new interface driver cdc_ether
10762 12:45:21.634774 <6>[ 15.447209] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10763 12:45:21.638326 <6>[ 15.457450] usbcore: registered new interface driver r8153_ecm
10764 12:45:21.648210 <6>[ 15.467783] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10765 12:45:21.655121 <6>[ 15.482264] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10766 12:45:21.661319 <6>[ 15.490103] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10767 12:45:21.671353 <6>[ 15.490117] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10768 12:45:21.678382 <6>[ 15.590288] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10769 12:45:21.687874 <6>[ 15.598301] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10770 12:45:21.691483 <6>[ 15.606308] pci 0000:00:00.0: PCI bridge to [bus 01]
10771 12:45:21.701167 <6>[ 15.611529] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10772 12:45:21.704111 <6>[ 15.619638] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10773 12:45:21.711516 <6>[ 15.626777] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10774 12:45:21.717980 <6>[ 15.633397] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10775 12:45:21.735814 <5>[ 15.647858] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10776 12:45:21.754457 <5>[ 15.665990] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10777 12:45:21.760420 <4>[ 15.672851] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10778 12:45:21.767134 <6>[ 15.681731] cfg80211: failed to load regulatory.db
10779 12:45:21.790714 <6>[ 15.702621] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10780 12:45:21.797379 <6>[ 15.710103] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10781 12:45:21.820138 <6>[ 15.735185] mt7921e 0000:01:00.0: ASIC revision: 79610010
10782 12:45:21.917156 <4>[ 15.825901] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10783 12:45:21.920657 Begin: Loading essential drivers ... done.
10784 12:45:21.923905 Begin: Running /scripts/init-premount ... done.
10785 12:45:21.930797 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10786 12:45:21.940682 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10787 12:45:21.943665 Device /sys/class/net/enx0024323078ff found
10788 12:45:21.943750 done.
10789 12:45:21.983306 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10790 12:45:22.016709 <4>[ 15.925033] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10791 12:45:22.116310 <4>[ 16.024934] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10792 12:45:22.216240 <4>[ 16.124918] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10793 12:45:22.316264 <4>[ 16.224913] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10794 12:45:22.416199 <4>[ 16.324925] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10795 12:45:22.516290 <4>[ 16.424901] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10796 12:45:22.616202 <4>[ 16.524912] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10797 12:45:22.716320 <4>[ 16.624893] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10798 12:45:22.816338 <4>[ 16.724911] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10799 12:45:22.907431 <3>[ 16.822940] mt7921e 0000:01:00.0: hardware init failed
10800 12:45:23.162175 <6>[ 17.077843] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10801 12:45:23.214802 IP-Config: no response after 2 secs - giving up
10802 12:45:23.247080 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10803 12:45:23.260343 IP-Config: enx0024323078ff complete (dhcp from 192.168.201.1):
10804 12:45:23.266708 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10805 12:45:23.273437 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10806 12:45:23.279737 host : mt8192-asurada-spherion-r0-cbg-8
10807 12:45:23.286658 domain : lava-rack
10808 12:45:23.292973 rootserver: 192.168.201.1 rootpath:
10809 12:45:23.293064 filename :
10810 12:45:23.312406 done.
10811 12:45:23.320176 Begin: Running /scripts/nfs-bottom ... done.
10812 12:45:23.331813 Begin: Running /scripts/init-bottom ... done.
10813 12:45:24.462702 <6>[ 18.378540] NET: Registered PF_INET6 protocol family
10814 12:45:24.469417 <6>[ 18.385050] Segment Routing with IPv6
10815 12:45:24.472411 <6>[ 18.389008] In-situ OAM (IOAM) with IPv6
10816 12:45:24.588839 <30>[ 18.484786] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10817 12:45:24.592478 <30>[ 18.508511] systemd[1]: Detected architecture arm64.
10818 12:45:24.611755
10819 12:45:24.615375 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10820 12:45:24.615483
10821 12:45:24.633686 <30>[ 18.549532] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10822 12:45:25.251018 <30>[ 19.163355] systemd[1]: Queued start job for default target Graphical Interface.
10823 12:45:25.276804 <30>[ 19.192186] systemd[1]: Created slice system-getty.slice.
10824 12:45:25.283073 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10825 12:45:25.300406 <30>[ 19.215850] systemd[1]: Created slice system-modprobe.slice.
10826 12:45:25.306533 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10827 12:45:25.324348 <30>[ 19.239787] systemd[1]: Created slice system-serial\x2dgetty.slice.
10828 12:45:25.334426 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10829 12:45:25.348305 <30>[ 19.263915] systemd[1]: Created slice User and Session Slice.
10830 12:45:25.354937 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10831 12:45:25.375197 <30>[ 19.287499] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10832 12:45:25.385289 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10833 12:45:25.399215 <30>[ 19.311360] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10834 12:45:25.405776 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10835 12:45:25.426759 <30>[ 19.335332] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10836 12:45:25.432925 <30>[ 19.347346] systemd[1]: Reached target Local Encrypted Volumes.
10837 12:45:25.439883 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10838 12:45:25.456105 <30>[ 19.371431] systemd[1]: Reached target Paths.
10839 12:45:25.458990 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10840 12:45:25.475735 <30>[ 19.391269] systemd[1]: Reached target Remote File Systems.
10841 12:45:25.482387 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10842 12:45:25.495446 <30>[ 19.411254] systemd[1]: Reached target Slices.
10843 12:45:25.498697 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10844 12:45:25.515648 <30>[ 19.431275] systemd[1]: Reached target Swap.
10845 12:45:25.518576 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10846 12:45:25.539265 <30>[ 19.451562] systemd[1]: Listening on initctl Compatibility Named Pipe.
10847 12:45:25.545569 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10848 12:45:25.561070 <30>[ 19.476736] systemd[1]: Listening on Journal Audit Socket.
10849 12:45:25.567483 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10850 12:45:25.584943 <30>[ 19.500472] systemd[1]: Listening on Journal Socket (/dev/log).
10851 12:45:25.591186 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10852 12:45:25.608102 <30>[ 19.523746] systemd[1]: Listening on Journal Socket.
10853 12:45:25.614623 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10854 12:45:25.632366 <30>[ 19.544415] systemd[1]: Listening on Network Service Netlink Socket.
10855 12:45:25.638540 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10856 12:45:25.654038 <30>[ 19.569926] systemd[1]: Listening on udev Control Socket.
10857 12:45:25.660627 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10858 12:45:25.675928 <30>[ 19.591506] systemd[1]: Listening on udev Kernel Socket.
10859 12:45:25.682484 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10860 12:45:25.715527 <30>[ 19.631458] systemd[1]: Mounting Huge Pages File System...
10861 12:45:25.722375 Mounting [0;1;39mHuge Pages File System[0m...
10862 12:45:25.737448 <30>[ 19.653089] systemd[1]: Mounting POSIX Message Queue File System...
10863 12:45:25.743686 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10864 12:45:25.761354 <30>[ 19.676976] systemd[1]: Mounting Kernel Debug File System...
10865 12:45:25.767852 Mounting [0;1;39mKernel Debug File System[0m...
10866 12:45:25.786946 <30>[ 19.699354] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10867 12:45:25.815131 <30>[ 19.727496] systemd[1]: Starting Create list of static device nodes for the current kernel...
10868 12:45:25.822348 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10869 12:45:25.841367 <30>[ 19.757160] systemd[1]: Starting Load Kernel Module configfs...
10870 12:45:25.848207 Starting [0;1;39mLoad Kernel Module configfs[0m...
10871 12:45:25.865795 <30>[ 19.781095] systemd[1]: Starting Load Kernel Module drm...
10872 12:45:25.872014 Starting [0;1;39mLoad Kernel Module drm[0m...
10873 12:45:25.889855 <30>[ 19.805250] systemd[1]: Starting Load Kernel Module fuse...
10874 12:45:25.896323 Starting [0;1;39mLoad Kernel Module fuse[0m...
10875 12:45:25.929383 <6>[ 19.844809] fuse: init (API version 7.37)
10876 12:45:25.939215 <30>[ 19.846175] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10877 12:45:25.964068 <30>[ 19.879476] systemd[1]: Starting Journal Service...
10878 12:45:25.967266 Starting [0;1;39mJournal Service[0m...
10879 12:45:25.990793 <30>[ 19.906453] systemd[1]: Starting Load Kernel Modules...
10880 12:45:25.997436 Starting [0;1;39mLoad Kernel Modules[0m...
10881 12:45:26.016855 <30>[ 19.929036] systemd[1]: Starting Remount Root and Kernel File Systems...
10882 12:45:26.022892 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10883 12:45:26.037553 <30>[ 19.953059] systemd[1]: Starting Coldplug All udev Devices...
10884 12:45:26.043796 Starting [0;1;39mColdplug All udev Devices[0m...
10885 12:45:26.061894 <30>[ 19.977721] systemd[1]: Mounted Huge Pages File System.
10886 12:45:26.068705 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10887 12:45:26.087537 <30>[ 20.003522] systemd[1]: Mounted POSIX Message Queue File System.
10888 12:45:26.094426 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10889 12:45:26.116571 <30>[ 20.031420] systemd[1]: Mounted Kernel Debug File System.
10890 12:45:26.126203 <3>[ 20.036877] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10891 12:45:26.129876 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10892 12:45:26.154729 <3>[ 20.066892] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 12:45:26.164431 <30>[ 20.076500] systemd[1]: Finished Create list of static device nodes for the current kernel.
10894 12:45:26.174196 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10895 12:45:26.188993 <30>[ 20.104186] systemd[1]: modprobe@configfs.service: Succeeded.
10896 12:45:26.195279 <30>[ 20.110780] systemd[1]: Finished Load Kernel Module configfs.
10897 12:45:26.205070 <3>[ 20.113163] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10898 12:45:26.211742 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10899 12:45:26.228593 <30>[ 20.143891] systemd[1]: modprobe@drm.service: Succeeded.
10900 12:45:26.238153 <3>[ 20.147744] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10901 12:45:26.241918 <30>[ 20.150063] systemd[1]: Finished Load Kernel Module drm.
10902 12:45:26.248290 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10903 12:45:26.264418 <30>[ 20.179907] systemd[1]: modprobe@fuse.service: Succeeded.
10904 12:45:26.274148 <3>[ 20.180531] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10905 12:45:26.280702 <30>[ 20.186275] systemd[1]: Finished Load Kernel Module fuse.
10906 12:45:26.284537 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10907 12:45:26.303213 <3>[ 20.215682] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10908 12:45:26.309827 <30>[ 20.216079] systemd[1]: Finished Load Kernel Modules.
10909 12:45:26.316564 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10910 12:45:26.332223 <30>[ 20.244173] systemd[1]: Finished Remount Root and Kernel File Systems.
10911 12:45:26.338444 <3>[ 20.248254] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10912 12:45:26.345338 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10913 12:45:26.370472 <3>[ 20.282605] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10914 12:45:26.394691 <30>[ 20.309843] systemd[1]: Mounting FUSE Control File System...
10915 12:45:26.408204 Mounting [0;1;39mFUSE <3>[ 20.317569] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 12:45:26.408311 Control File System[0m...
10917 12:45:26.426105 <30>[ 20.341113] systemd[1]: Mounting Kernel Configuration File System...
10918 12:45:26.436140 <3>[ 20.347514] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10919 12:45:26.442481 Mounting [0;1;39mKernel Configuration File System[0m...
10920 12:45:26.463582 <30>[ 20.376039] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10921 12:45:26.473844 <3>[ 20.376820] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10922 12:45:26.483464 <30>[ 20.384981] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10923 12:45:26.501887 <3>[ 20.413614] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10924 12:45:26.507857 <30>[ 20.422823] systemd[1]: Starting Load/Save Random Seed...
10925 12:45:26.514569 Starting [0;1;39mLoad/Save Random Seed[0m...
10926 12:45:26.529898 <30>[ 20.445033] systemd[1]: Starting Apply Kernel Variables...
10927 12:45:26.540012 Startin<3>[ 20.452214] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10928 12:45:26.550057 g [0;1;39mApply<3>[ 20.453002] power_supply sbs-5-000b: driver failed to report `current_now' property: -6
10929 12:45:26.553062 Kernel Variables[0m...
10930 12:45:26.569605 <3>[ 20.481872] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 12:45:26.577640 <30>[ 20.493369] systemd[1]: Starting Create System Users...
10932 12:45:26.583856 Starting [0;1;39mCreate System Users[0m...
10933 12:45:26.601357 <30>[ 20.516527] systemd[1]: Mounted FUSE Control File System.
10934 12:45:26.621758 [[0;32m OK [0m] Mounted [0;1;39mFUSE Contro<4>[ 20.525797] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10935 12:45:26.631722 l File System[0<3>[ 20.542179] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -6
10936 12:45:26.631879 m.
10937 12:45:26.647800 <30>[ 20.563520] systemd[1]: Mounted Kernel Configuration File System.
10938 12:45:26.654555 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10939 12:45:26.675261 <29>[ 20.587588] systemd[1]: systemd-udev-trigger.service: Main process exited, code=exited, status=1/FAILURE
10940 12:45:26.685183 <28>[ 20.597716] systemd[1]: systemd-udev-trigger.service: Failed with result 'exit-code'.
10941 12:45:26.691890 <27>[ 20.606437] systemd[1]: Failed to start Coldplug All udev Devices.
10942 12:45:26.698412 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10943 12:45:26.711749 See 'systemctl status systemd-udev-trigger.service' for details.
10944 12:45:26.727768 <30>[ 20.643670] systemd[1]: Started Journal Service.
10945 12:45:26.734175 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10946 12:45:26.749622 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10947 12:45:26.768082 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10948 12:45:26.788588 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10949 12:45:26.835589 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10950 12:45:26.857298 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10951 12:45:26.895446 <46>[ 20.807481] systemd-journald[294]: Received client request to flush runtime journal.
10952 12:45:27.644712 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10953 12:45:27.659406 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10954 12:45:27.675731 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10955 12:45:27.722937 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10956 12:45:28.168118 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10957 12:45:28.220336 Starting [0;1;39mNetwork Service[0m...
10958 12:45:28.617995 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10959 12:45:28.633889 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10960 12:45:28.655998 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10961 12:45:28.698626 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10962 12:45:28.713285 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10963 12:45:28.767423 <6>[ 22.683509] remoteproc remoteproc0: powering up scp
10964 12:45:28.798595 <4>[ 22.711553] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10965 12:45:28.805384 <3>[ 22.721447] remoteproc remoteproc0: request_firmware failed: -2
10966 12:45:28.815583 <3>[ 22.727636] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10967 12:45:28.942088 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10968 12:45:29.017317 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10969 12:45:29.034399 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10970 12:45:29.087709 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10971 12:45:29.178960 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10972 12:45:29.195404 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10973 12:45:29.350218 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10974 12:45:29.407783 Starting [0;1;39mNetwork Name Resolution[0m...
10975 12:45:29.430526 Starting [0;1;39mNetwork Time Synchronization[0m...
10976 12:45:29.444701 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10977 12:45:29.495073 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10978 12:45:29.691347 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10979 12:45:29.707658 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10980 12:45:29.726740 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10981 12:45:29.743093 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10982 12:45:29.759391 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10983 12:45:29.866312 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10984 12:45:29.898985 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10985 12:45:29.924710 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10986 12:45:29.954069 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10987 12:45:29.967364 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10988 12:45:30.015814 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10989 12:45:30.027255 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10990 12:45:30.043416 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10991 12:45:30.091195 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10992 12:45:30.798347 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10993 12:45:31.159376 Starting [0;1;39mUser Login Management[0m...
10994 12:45:31.175890 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10995 12:45:31.192566 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10996 12:45:31.210214 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10997 12:45:31.255274 Starting [0;1;39mPermit User Sessions[0m...
10998 12:45:31.351355 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10999 12:45:31.403237 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11000 12:45:31.420948 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11001 12:45:31.435451 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11002 12:45:31.456449 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11003 12:45:31.476463 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11004 12:45:31.496517 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11005 12:45:31.515396 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11006 12:45:31.570669 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11007 12:45:31.610115 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11008 12:45:31.677758
11009 12:45:31.677872
11010 12:45:31.681437 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11011 12:45:31.681521
11012 12:45:31.715290 debian-bullseye-arm64 login: root (automatic login)
11013 12:45:31.715393
11014 12:45:31.715460
11015 12:45:32.050570 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Wed Jun 14 12:30:40 UTC 2023 aarch64
11016 12:45:32.050704
11017 12:45:32.056873 The programs included with the Debian GNU/Linux system are free software;
11018 12:45:32.063429 the exact distribution terms for each program are described in the
11019 12:45:32.066544 individual files in /usr/share/doc/*/copyright.
11020 12:45:32.066639
11021 12:45:32.073708 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11022 12:45:32.076802 permitted by applicable law.
11023 12:45:32.911636 Matched prompt #10: / #
11025 12:45:32.911906 Setting prompt string to ['/ #']
11026 12:45:32.912000 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11028 12:45:32.912195 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11029 12:45:32.912284 start: 2.2.6 expect-shell-connection (timeout 00:03:20) [common]
11030 12:45:32.912356 Setting prompt string to ['/ #']
11031 12:45:32.912418 Forcing a shell prompt, looking for ['/ #']
11033 12:45:32.962639 / #
11034 12:45:32.962762 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11035 12:45:32.962883 Waiting using forced prompt support (timeout 00:02:30)
11036 12:45:32.967575
11037 12:45:32.967853 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11038 12:45:32.967950 start: 2.2.7 export-device-env (timeout 00:03:20) [common]
11040 12:45:33.068302 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10724879/extract-nfsrootfs-vz66w8m2'
11041 12:45:33.073289 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10724879/extract-nfsrootfs-vz66w8m2'
11043 12:45:33.173827 / # export NFS_SERVER_IP='192.168.201.1'
11044 12:45:33.178320 export NFS_SERVER_IP='192.168.201.1'
11045 12:45:33.178608 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11046 12:45:33.178714 end: 2.2 depthcharge-retry (duration 00:01:40) [common]
11047 12:45:33.178805 end: 2 depthcharge-action (duration 00:01:40) [common]
11048 12:45:33.178907 start: 3 lava-test-retry (timeout 00:07:40) [common]
11049 12:45:33.178995 start: 3.1 lava-test-shell (timeout 00:07:40) [common]
11050 12:45:33.179068 Using namespace: common
11052 12:45:33.279388 / # #
11053 12:45:33.279530 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11054 12:45:33.284180 #
11055 12:45:33.284450 Using /lava-10724879
11057 12:45:33.384797 / # export SHELL=/bin/bash
11058 12:45:33.390262 export SHELL=/bin/bash
11060 12:45:33.490802 / # . /lava-10724879/environment
11061 12:45:33.495604 . /lava-10724879/environment
11063 12:45:33.600812 / # /lava-10724879/bin/lava-test-runner /lava-10724879/0
11064 12:45:33.600948 Test shell timeout: 10s (minimum of the action and connection timeout)
11065 12:45:33.605878 /lava-10724879/bin/lava-test-runner /lava-10724879/0
11066 12:45:33.867121 + export TESTRUN_ID=0_timesync-off
11067 12:45:33.870056 + TESTRUN_ID=0_timesync-off
11068 12:45:33.873777 + cd /lava-10724879/0/tests/0_timesync-off
11069 12:45:33.876651 ++ cat uuid
11070 12:45:33.880320 + UUID=10724879_1.6.2.3.1
11071 12:45:33.880438 + set +x
11072 12:45:33.886642 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10724879_1.6.2.3.1>
11073 12:45:33.886979 Received signal: <STARTRUN> 0_timesync-off 10724879_1.6.2.3.1
11074 12:45:33.887068 Starting test lava.0_timesync-off (10724879_1.6.2.3.1)
11075 12:45:33.887157 Skipping test definition patterns.
11076 12:45:33.890091 + systemctl stop systemd-timesyncd
11077 12:45:33.925295 + set +x
11078 12:45:33.928387 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10724879_1.6.2.3.1>
11079 12:45:33.928654 Received signal: <ENDRUN> 0_timesync-off 10724879_1.6.2.3.1
11080 12:45:33.928744 Ending use of test pattern.
11081 12:45:33.928807 Ending test lava.0_timesync-off (10724879_1.6.2.3.1), duration 0.04
11083 12:45:34.264127 + export TESTRUN_ID=1_kselftest-rtc
11084 12:45:34.267704 + TESTRUN_ID=1_kselftest-rtc
11085 12:45:34.270499 + cd /lava-10724879/0/tests/1_kselftest-rtc
11086 12:45:34.274245 ++ cat uuid
11087 12:45:34.277972 + UUID=10724879_1.6.2.3.5
11088 12:45:34.278056 + set +x
11089 12:45:34.284146 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 10724879_1.6.2.3.5>
11090 12:45:34.284454 Received signal: <STARTRUN> 1_kselftest-rtc 10724879_1.6.2.3.5
11091 12:45:34.284534 Starting test lava.1_kselftest-rtc (10724879_1.6.2.3.5)
11092 12:45:34.284627 Skipping test definition patterns.
11093 12:45:34.287652 + cd ./automated/linux/kselftest/
11094 12:45:34.313681 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11095 12:45:34.344363 INFO: install_deps skipped
11096 12:45:34.461132 --2023-06-14 12:45:34-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11097 12:45:34.463941 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11098 12:45:34.593065 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11099 12:45:34.724429 HTTP request sent, awaiting response... 200 OK
11100 12:45:34.728010 Length: 2878416 (2.7M) [application/octet-stream]
11101 12:45:34.730808 Saving to: 'kselftest.tar.xz'
11102 12:45:34.730950
11103 12:45:34.731045
11104 12:45:34.981762 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11105 12:45:35.242654 kselftest.tar.xz 1%[ ] 47.81K 187KB/s
11106 12:45:35.536560 kselftest.tar.xz 7%[> ] 217.50K 421KB/s
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11111 12:45:36.062650
11112 12:45:36.344811 2023-06-14 12:45:36 (2.06 MB/s) - 'kselftest.tar.xz' saved [2878416/2878416]
11113 12:45:36.344972
11114 12:45:41.870091 skiplist:
11115 12:45:41.873213 ========================================
11116 12:45:41.876928 ========================================
11117 12:45:41.921861 rtc:rtctest
11118 12:45:41.941680 ============== Tests to run ===============
11119 12:45:41.941819 rtc:rtctest
11120 12:45:41.944833 ===========End Tests to run ===============
11121 12:45:42.052562 <12>[ 35.970099] kselftest: Running tests in rtc
11122 12:45:42.060726 TAP version 13
11123 12:45:42.072846 1..1
11124 12:45:42.100904 # selftests: rtc: rtctest
11125 12:45:42.475553 # TAP version 13
11126 12:45:42.475691 # 1..8
11127 12:45:42.479316 # # Starting 8 tests from 2 test cases.
11128 12:45:42.482450 # # RUN rtc.date_read ...
11129 12:45:42.488887 # # rtctest.c:49:date_read:Current RTC date/time is 14/06/2023 12:45:42.
11130 12:45:42.491957 # # OK rtc.date_read
11131 12:45:42.495629 # ok 1 rtc.date_read
11132 12:45:42.498649 # # RUN rtc.date_read_loop ...
11133 12:45:42.508521 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11134 12:45:52.233465 <6>[ 46.155170] vpu: disabling
11135 12:45:52.236228 <6>[ 46.158210] vproc2: disabling
11136 12:45:52.239722 <6>[ 46.161477] vproc1: disabling
11137 12:45:52.242802 <6>[ 46.164738] vaud18: disabling
11138 12:45:52.249885 <6>[ 46.168139] vsram_others: disabling
11139 12:45:52.253258 <6>[ 46.172009] va09: disabling
11140 12:45:52.256103 <6>[ 46.175111] vsram_md: disabling
11141 12:45:52.259599 <6>[ 46.178589] Vgpu: disabling
11142 12:46:13.015024 # # rtctest.c:115:date_read_loop:Performed 2745 RTC time reads.
11143 12:46:13.018373 # # OK rtc.date_read_loop
11144 12:46:13.021894 # ok 2 rtc.date_read_loop
11145 12:46:13.024850 # # RUN rtc.uie_read ...
11146 12:46:16.001431 # # OK rtc.uie_read
11147 12:46:16.004720 # ok 3 rtc.uie_read
11148 12:46:16.007969 # # RUN rtc.uie_select ...
11149 12:46:19.000735 # # OK rtc.uie_select
11150 12:46:19.004141 # ok 4 rtc.uie_select
11151 12:46:19.007466 # # RUN rtc.alarm_alm_set ...
11152 12:46:19.013917 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 12:46:22.
11153 12:46:19.017380 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11154 12:46:19.023972 # # alarm_alm_set: Test terminated by assertion
11155 12:46:19.027466 # # FAIL rtc.alarm_alm_set
11156 12:46:19.030334 # not ok 5 rtc.alarm_alm_set
11157 12:46:19.033913 # # RUN rtc.alarm_wkalm_set ...
11158 12:46:19.040102 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 14/06/2023 12:46:22.
11159 12:46:22.003575 # # OK rtc.alarm_wkalm_set
11160 12:46:22.003752 # ok 6 rtc.alarm_wkalm_set
11161 12:46:22.010242 # # RUN rtc.alarm_alm_set_minute ...
11162 12:46:22.013322 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 12:47:00.
11163 12:46:22.020383 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11164 12:46:22.026200 # # alarm_alm_set_minute: Test terminated by assertion
11165 12:46:22.029485 # # FAIL rtc.alarm_alm_set_minute
11166 12:46:22.033228 # not ok 7 rtc.alarm_alm_set_minute
11167 12:46:22.036022 # # RUN rtc.alarm_wkalm_set_minute ...
11168 12:46:22.046183 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 14/06/2023 12:47:00.
11169 12:46:59.999173 # # OK rtc.alarm_wkalm_set_minute
11170 12:47:00.002558 # ok 8 rtc.alarm_wkalm_set_minute
11171 12:47:00.005613 # # FAILED: 6 / 8 tests passed.
11172 12:47:00.009240 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11173 12:47:00.012334 not ok 1 selftests: rtc: rtctest # exit=1
11174 12:47:00.557963 rtc_rtctest_rtc_date_read pass
11175 12:47:00.560948 rtc_rtctest_rtc_date_read_loop pass
11176 12:47:00.564344 rtc_rtctest_rtc_uie_read pass
11177 12:47:00.567295 rtc_rtctest_rtc_uie_select pass
11178 12:47:00.570920 rtc_rtctest_rtc_alarm_alm_set fail
11179 12:47:00.573909 rtc_rtctest_rtc_alarm_wkalm_set pass
11180 12:47:00.577464 rtc_rtctest_rtc_alarm_alm_set_minute fail
11181 12:47:00.580475 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11182 12:47:00.584050 rtc_rtctest fail
11183 12:47:00.587174 + ../../utils/send-to-lava.sh ./output/result.txt
11184 12:47:00.648914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11185 12:47:00.649265 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11187 12:47:00.711236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11188 12:47:00.711583 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11190 12:47:00.764167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11191 12:47:00.764472 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11193 12:47:00.825808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11194 12:47:00.826124 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11196 12:47:00.883017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11197 12:47:00.883333 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11199 12:47:00.945666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11200 12:47:00.945981 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11202 12:47:01.000240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11203 12:47:01.000576 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11205 12:47:01.051546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11206 12:47:01.051928 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11208 12:47:01.102795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11209 12:47:01.102953 + set +x
11210 12:47:01.103200 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11212 12:47:01.109561 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 10724879_1.6.2.3.5>
11213 12:47:01.109841 Received signal: <ENDRUN> 1_kselftest-rtc 10724879_1.6.2.3.5
11214 12:47:01.109941 Ending use of test pattern.
11215 12:47:01.110021 Ending test lava.1_kselftest-rtc (10724879_1.6.2.3.5), duration 86.83
11217 12:47:01.110244 ok: lava_test_shell seems to have completed
11218 12:47:01.110370 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
11219 12:47:01.110461 end: 3.1 lava-test-shell (duration 00:01:28) [common]
11220 12:47:01.110570 end: 3 lava-test-retry (duration 00:01:28) [common]
11221 12:47:01.110682 start: 4 finalize (timeout 00:06:12) [common]
11222 12:47:01.110801 start: 4.1 power-off (timeout 00:00:30) [common]
11223 12:47:01.111005 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11224 12:47:01.188513 >> Command sent successfully.
11225 12:47:01.190940 Returned 0 in 0 seconds
11226 12:47:01.291336 end: 4.1 power-off (duration 00:00:00) [common]
11228 12:47:01.291670 start: 4.2 read-feedback (timeout 00:06:11) [common]
11230 12:47:01.292220 Listened to connection for namespace 'common' for up to 1s
11231 12:47:02.292843 Finalising connection for namespace 'common'
11232 12:47:02.293004 Disconnecting from shell: Finalise
11233 12:47:02.293088 / #
11234 12:47:02.393423 end: 4.2 read-feedback (duration 00:00:01) [common]
11235 12:47:02.393611 end: 4 finalize (duration 00:00:01) [common]
11236 12:47:02.393725 Cleaning after the job
11237 12:47:02.393821 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724879/tftp-deploy-49u57mqi/ramdisk
11238 12:47:02.396097 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724879/tftp-deploy-49u57mqi/kernel
11239 12:47:02.405105 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724879/tftp-deploy-49u57mqi/dtb
11240 12:47:02.405314 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724879/tftp-deploy-49u57mqi/nfsrootfs
11241 12:47:02.472360 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724879/tftp-deploy-49u57mqi/modules
11242 12:47:02.478422 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10724879
11243 12:47:02.997947 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10724879
11244 12:47:02.998122 Job finished correctly