Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 47
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 34
- Errors: 0
1 12:39:16.562782 lava-dispatcher, installed at version: 2023.05.1
2 12:39:16.562998 start: 0 validate
3 12:39:16.563131 Start time: 2023-06-14 12:39:16.563123+00:00 (UTC)
4 12:39:16.563281 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:39:16.563465 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230609.0%2Farm64%2Finitrd.cpio.gz exists
6 12:39:16.817057 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:39:16.817246 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:39:47.104308 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:39:47.105118 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:39:47.370017 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:39:47.370728 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230609.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:39:47.892757 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:39:47.892913 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:39:52.900803 validate duration: 36.34
16 12:39:52.901054 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:39:52.901148 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:39:52.901236 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:39:52.901361 Not decompressing ramdisk as can be used compressed.
20 12:39:52.901445 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230609.0/arm64/initrd.cpio.gz
21 12:39:52.901509 saving as /var/lib/lava/dispatcher/tmp/10724841/tftp-deploy-p8zw_5gu/ramdisk/initrd.cpio.gz
22 12:39:52.901569 total size: 4665397 (4MB)
23 12:39:53.162071 progress 0% (0MB)
24 12:39:53.163468 progress 5% (0MB)
25 12:39:53.164755 progress 10% (0MB)
26 12:39:53.166001 progress 15% (0MB)
27 12:39:53.167233 progress 20% (0MB)
28 12:39:53.168444 progress 25% (1MB)
29 12:39:53.169842 progress 30% (1MB)
30 12:39:53.171092 progress 35% (1MB)
31 12:39:53.172316 progress 40% (1MB)
32 12:39:53.173734 progress 45% (2MB)
33 12:39:53.174944 progress 50% (2MB)
34 12:39:53.176184 progress 55% (2MB)
35 12:39:53.177524 progress 60% (2MB)
36 12:39:53.178740 progress 65% (2MB)
37 12:39:53.179983 progress 70% (3MB)
38 12:39:53.181256 progress 75% (3MB)
39 12:39:53.182519 progress 80% (3MB)
40 12:39:53.183891 progress 85% (3MB)
41 12:39:53.185141 progress 90% (4MB)
42 12:39:53.186346 progress 95% (4MB)
43 12:39:53.187574 progress 100% (4MB)
44 12:39:53.187727 4MB downloaded in 0.29s (15.55MB/s)
45 12:39:53.187877 end: 1.1.1 http-download (duration 00:00:00) [common]
47 12:39:53.188121 end: 1.1 download-retry (duration 00:00:00) [common]
48 12:39:53.188210 start: 1.2 download-retry (timeout 00:10:00) [common]
49 12:39:53.188297 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 12:39:53.188429 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:39:53.188501 saving as /var/lib/lava/dispatcher/tmp/10724841/tftp-deploy-p8zw_5gu/kernel/Image
52 12:39:53.188606 total size: 47581696 (45MB)
53 12:39:53.188668 No compression specified
54 12:39:53.189792 progress 0% (0MB)
55 12:39:53.202100 progress 5% (2MB)
56 12:39:53.214241 progress 10% (4MB)
57 12:39:53.226156 progress 15% (6MB)
58 12:39:53.238164 progress 20% (9MB)
59 12:39:53.250236 progress 25% (11MB)
60 12:39:53.262486 progress 30% (13MB)
61 12:39:53.274812 progress 35% (15MB)
62 12:39:53.287006 progress 40% (18MB)
63 12:39:53.299456 progress 45% (20MB)
64 12:39:53.311843 progress 50% (22MB)
65 12:39:53.324306 progress 55% (24MB)
66 12:39:53.336495 progress 60% (27MB)
67 12:39:53.348638 progress 65% (29MB)
68 12:39:53.360968 progress 70% (31MB)
69 12:39:53.373477 progress 75% (34MB)
70 12:39:53.386489 progress 80% (36MB)
71 12:39:53.399606 progress 85% (38MB)
72 12:39:53.412192 progress 90% (40MB)
73 12:39:53.424215 progress 95% (43MB)
74 12:39:53.436442 progress 100% (45MB)
75 12:39:53.436663 45MB downloaded in 0.25s (182.95MB/s)
76 12:39:53.436832 end: 1.2.1 http-download (duration 00:00:00) [common]
78 12:39:53.437074 end: 1.2 download-retry (duration 00:00:00) [common]
79 12:39:53.437167 start: 1.3 download-retry (timeout 00:09:59) [common]
80 12:39:53.437289 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 12:39:53.437419 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:39:53.437491 saving as /var/lib/lava/dispatcher/tmp/10724841/tftp-deploy-p8zw_5gu/dtb/mt8192-asurada-spherion-r0.dtb
83 12:39:53.437553 total size: 46924 (0MB)
84 12:39:53.437633 No compression specified
85 12:39:53.438778 progress 69% (0MB)
86 12:39:53.439082 progress 100% (0MB)
87 12:39:53.439235 0MB downloaded in 0.00s (26.64MB/s)
88 12:39:53.439356 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:39:53.439623 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:39:53.439711 start: 1.4 download-retry (timeout 00:09:59) [common]
92 12:39:53.439795 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 12:39:53.439907 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230609.0/arm64/full.rootfs.tar.xz
94 12:39:53.440008 saving as /var/lib/lava/dispatcher/tmp/10724841/tftp-deploy-p8zw_5gu/nfsrootfs/full.rootfs.tar
95 12:39:53.440070 total size: 200816996 (191MB)
96 12:39:53.440130 Using unxz to decompress xz
97 12:39:53.443808 progress 0% (0MB)
98 12:39:53.996501 progress 5% (9MB)
99 12:39:54.539676 progress 10% (19MB)
100 12:39:55.126597 progress 15% (28MB)
101 12:39:55.509845 progress 20% (38MB)
102 12:39:55.836764 progress 25% (47MB)
103 12:39:56.431306 progress 30% (57MB)
104 12:39:56.987731 progress 35% (67MB)
105 12:39:57.614094 progress 40% (76MB)
106 12:39:58.183364 progress 45% (86MB)
107 12:39:58.777487 progress 50% (95MB)
108 12:39:59.430106 progress 55% (105MB)
109 12:40:00.131867 progress 60% (114MB)
110 12:40:00.260253 progress 65% (124MB)
111 12:40:00.406972 progress 70% (134MB)
112 12:40:00.499643 progress 75% (143MB)
113 12:40:00.579517 progress 80% (153MB)
114 12:40:00.661198 progress 85% (162MB)
115 12:40:00.785098 progress 90% (172MB)
116 12:40:01.075912 progress 95% (181MB)
117 12:40:01.667554 progress 100% (191MB)
118 12:40:01.673095 191MB downloaded in 8.23s (23.26MB/s)
119 12:40:01.673539 end: 1.4.1 http-download (duration 00:00:08) [common]
121 12:40:01.673942 end: 1.4 download-retry (duration 00:00:08) [common]
122 12:40:01.674076 start: 1.5 download-retry (timeout 00:09:51) [common]
123 12:40:01.674204 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 12:40:01.674408 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:40:01.674513 saving as /var/lib/lava/dispatcher/tmp/10724841/tftp-deploy-p8zw_5gu/modules/modules.tar
126 12:40:01.674608 total size: 8536768 (8MB)
127 12:40:01.674705 Using unxz to decompress xz
128 12:40:01.938295 progress 0% (0MB)
129 12:40:01.959412 progress 5% (0MB)
130 12:40:01.986387 progress 10% (0MB)
131 12:40:02.017217 progress 15% (1MB)
132 12:40:02.041260 progress 20% (1MB)
133 12:40:02.065091 progress 25% (2MB)
134 12:40:02.089886 progress 30% (2MB)
135 12:40:02.113924 progress 35% (2MB)
136 12:40:02.141513 progress 40% (3MB)
137 12:40:02.167943 progress 45% (3MB)
138 12:40:02.194648 progress 50% (4MB)
139 12:40:02.220587 progress 55% (4MB)
140 12:40:02.246551 progress 60% (4MB)
141 12:40:02.272492 progress 65% (5MB)
142 12:40:02.297828 progress 70% (5MB)
143 12:40:02.323041 progress 75% (6MB)
144 12:40:02.347846 progress 80% (6MB)
145 12:40:02.372490 progress 85% (6MB)
146 12:40:02.398246 progress 90% (7MB)
147 12:40:02.424007 progress 95% (7MB)
148 12:40:02.447579 progress 100% (8MB)
149 12:40:02.454260 8MB downloaded in 0.78s (10.44MB/s)
150 12:40:02.454604 end: 1.5.1 http-download (duration 00:00:01) [common]
152 12:40:02.454885 end: 1.5 download-retry (duration 00:00:01) [common]
153 12:40:02.454984 start: 1.6 prepare-tftp-overlay (timeout 00:09:50) [common]
154 12:40:02.455078 start: 1.6.1 extract-nfsrootfs (timeout 00:09:50) [common]
155 12:40:05.795887 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10724841/extract-nfsrootfs-sun8wizn
156 12:40:05.796098 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 12:40:05.796199 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 12:40:05.796364 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0
159 12:40:05.796492 makedir: /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0/lava-10724841/bin
160 12:40:05.796636 makedir: /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0/lava-10724841/tests
161 12:40:05.796742 makedir: /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0/lava-10724841/results
162 12:40:05.796843 Creating /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0/lava-10724841/bin/lava-add-keys
163 12:40:05.796989 Creating /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0/lava-10724841/bin/lava-add-sources
164 12:40:05.797124 Creating /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0/lava-10724841/bin/lava-background-process-start
165 12:40:05.797262 Creating /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0/lava-10724841/bin/lava-background-process-stop
166 12:40:05.797417 Creating /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0/lava-10724841/bin/lava-common-functions
167 12:40:05.797540 Creating /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0/lava-10724841/bin/lava-echo-ipv4
168 12:40:05.797667 Creating /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0/lava-10724841/bin/lava-install-packages
169 12:40:05.797788 Creating /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0/lava-10724841/bin/lava-installed-packages
170 12:40:05.797906 Creating /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0/lava-10724841/bin/lava-os-build
171 12:40:05.798025 Creating /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0/lava-10724841/bin/lava-probe-channel
172 12:40:05.798145 Creating /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0/lava-10724841/bin/lava-probe-ip
173 12:40:05.798267 Creating /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0/lava-10724841/bin/lava-target-ip
174 12:40:05.798387 Creating /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0/lava-10724841/bin/lava-target-mac
175 12:40:05.798506 Creating /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0/lava-10724841/bin/lava-target-storage
176 12:40:05.798628 Creating /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0/lava-10724841/bin/lava-test-case
177 12:40:05.798749 Creating /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0/lava-10724841/bin/lava-test-event
178 12:40:05.798869 Creating /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0/lava-10724841/bin/lava-test-feedback
179 12:40:05.798991 Creating /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0/lava-10724841/bin/lava-test-raise
180 12:40:05.799111 Creating /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0/lava-10724841/bin/lava-test-reference
181 12:40:05.799232 Creating /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0/lava-10724841/bin/lava-test-runner
182 12:40:05.799412 Creating /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0/lava-10724841/bin/lava-test-set
183 12:40:05.799563 Creating /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0/lava-10724841/bin/lava-test-shell
184 12:40:05.799685 Updating /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0/lava-10724841/bin/lava-add-keys (debian)
185 12:40:05.799833 Updating /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0/lava-10724841/bin/lava-add-sources (debian)
186 12:40:05.799969 Updating /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0/lava-10724841/bin/lava-install-packages (debian)
187 12:40:05.800104 Updating /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0/lava-10724841/bin/lava-installed-packages (debian)
188 12:40:05.800238 Updating /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0/lava-10724841/bin/lava-os-build (debian)
189 12:40:05.800355 Creating /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0/lava-10724841/environment
190 12:40:05.800452 LAVA metadata
191 12:40:05.800528 - LAVA_JOB_ID=10724841
192 12:40:05.800613 - LAVA_DISPATCHER_IP=192.168.201.1
193 12:40:05.800738 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 12:40:05.800805 skipped lava-vland-overlay
195 12:40:05.800881 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 12:40:05.800964 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 12:40:05.801028 skipped lava-multinode-overlay
198 12:40:05.801116 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 12:40:05.801197 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 12:40:05.801272 Loading test definitions
201 12:40:05.801364 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 12:40:05.801436 Using /lava-10724841 at stage 0
203 12:40:05.801711 uuid=10724841_1.6.2.3.1 testdef=None
204 12:40:05.801800 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 12:40:05.801885 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 12:40:05.802328 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 12:40:05.802548 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 12:40:05.803092 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 12:40:05.803327 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 12:40:05.803859 runner path: /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0/lava-10724841/0/tests/0_timesync-off test_uuid 10724841_1.6.2.3.1
213 12:40:05.804011 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 12:40:05.804234 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 12:40:05.804306 Using /lava-10724841 at stage 0
217 12:40:05.804402 Fetching tests from https://github.com/kernelci/test-definitions.git
218 12:40:05.804479 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0/lava-10724841/0/tests/1_kselftest-tpm2'
219 12:40:15.504238 Running '/usr/bin/git checkout kernelci.org
220 12:40:15.647815 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 12:40:15.648527 uuid=10724841_1.6.2.3.5 testdef=None
222 12:40:15.648730 end: 1.6.2.3.5 git-repo-action (duration 00:00:10) [common]
224 12:40:15.648980 start: 1.6.2.3.6 test-overlay (timeout 00:09:37) [common]
225 12:40:15.649754 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 12:40:15.649989 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:37) [common]
228 12:40:15.650936 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 12:40:15.651179 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:37) [common]
231 12:40:15.652128 runner path: /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0/lava-10724841/0/tests/1_kselftest-tpm2 test_uuid 10724841_1.6.2.3.5
232 12:40:15.652222 BOARD='mt8192-asurada-spherion-r0'
233 12:40:15.652287 BRANCH='cip'
234 12:40:15.652348 SKIPFILE='/dev/null'
235 12:40:15.652407 SKIP_INSTALL='True'
236 12:40:15.652464 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 12:40:15.652549 TST_CASENAME=''
238 12:40:15.652622 TST_CMDFILES='tpm2'
239 12:40:15.652765 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 12:40:15.652972 Creating lava-test-runner.conf files
242 12:40:15.653037 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10724841/lava-overlay-7vbb1dc0/lava-10724841/0 for stage 0
243 12:40:15.653128 - 0_timesync-off
244 12:40:15.653198 - 1_kselftest-tpm2
245 12:40:15.653293 end: 1.6.2.3 test-definition (duration 00:00:10) [common]
246 12:40:15.653385 start: 1.6.2.4 compress-overlay (timeout 00:09:37) [common]
247 12:40:23.175996 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 12:40:23.176158 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:30) [common]
249 12:40:23.176256 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 12:40:23.176357 end: 1.6.2 lava-overlay (duration 00:00:17) [common]
251 12:40:23.176447 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:30) [common]
252 12:40:23.291540 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 12:40:23.291903 start: 1.6.4 extract-modules (timeout 00:09:30) [common]
254 12:40:23.292024 extracting modules file /var/lib/lava/dispatcher/tmp/10724841/tftp-deploy-p8zw_5gu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10724841/extract-nfsrootfs-sun8wizn
255 12:40:23.492404 extracting modules file /var/lib/lava/dispatcher/tmp/10724841/tftp-deploy-p8zw_5gu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10724841/extract-overlay-ramdisk-q4h26d_v/ramdisk
256 12:40:23.697067 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 12:40:23.697242 start: 1.6.5 apply-overlay-tftp (timeout 00:09:29) [common]
258 12:40:23.697344 [common] Applying overlay to NFS
259 12:40:23.697414 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10724841/compress-overlay-j3cxqako/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10724841/extract-nfsrootfs-sun8wizn
260 12:40:24.588246 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 12:40:24.588414 start: 1.6.6 configure-preseed-file (timeout 00:09:28) [common]
262 12:40:24.588508 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 12:40:24.588646 start: 1.6.7 compress-ramdisk (timeout 00:09:28) [common]
264 12:40:24.588735 Building ramdisk /var/lib/lava/dispatcher/tmp/10724841/extract-overlay-ramdisk-q4h26d_v/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10724841/extract-overlay-ramdisk-q4h26d_v/ramdisk
265 12:40:24.886930 >> 117806 blocks
266 12:40:26.788703 rename /var/lib/lava/dispatcher/tmp/10724841/extract-overlay-ramdisk-q4h26d_v/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10724841/tftp-deploy-p8zw_5gu/ramdisk/ramdisk.cpio.gz
267 12:40:26.789133 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 12:40:26.789262 start: 1.6.8 prepare-kernel (timeout 00:09:26) [common]
269 12:40:26.789363 start: 1.6.8.1 prepare-fit (timeout 00:09:26) [common]
270 12:40:26.789468 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10724841/tftp-deploy-p8zw_5gu/kernel/Image'
271 12:40:39.452227 Returned 0 in 12 seconds
272 12:40:39.552887 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10724841/tftp-deploy-p8zw_5gu/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10724841/tftp-deploy-p8zw_5gu/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10724841/tftp-deploy-p8zw_5gu/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10724841/tftp-deploy-p8zw_5gu/kernel/image.itb
273 12:40:39.869111 output: FIT description: Kernel Image image with one or more FDT blobs
274 12:40:39.869523 output: Created: Wed Jun 14 13:40:39 2023
275 12:40:39.869633 output: Image 0 (kernel-1)
276 12:40:39.869743 output: Description:
277 12:40:39.869849 output: Created: Wed Jun 14 13:40:39 2023
278 12:40:39.869956 output: Type: Kernel Image
279 12:40:39.870053 output: Compression: lzma compressed
280 12:40:39.870143 output: Data Size: 10442380 Bytes = 10197.64 KiB = 9.96 MiB
281 12:40:39.870245 output: Architecture: AArch64
282 12:40:39.870338 output: OS: Linux
283 12:40:39.870433 output: Load Address: 0x00000000
284 12:40:39.870531 output: Entry Point: 0x00000000
285 12:40:39.870619 output: Hash algo: crc32
286 12:40:39.870716 output: Hash value: ced21bfe
287 12:40:39.870803 output: Image 1 (fdt-1)
288 12:40:39.870887 output: Description: mt8192-asurada-spherion-r0
289 12:40:39.870981 output: Created: Wed Jun 14 13:40:39 2023
290 12:40:39.871068 output: Type: Flat Device Tree
291 12:40:39.871152 output: Compression: uncompressed
292 12:40:39.871245 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 12:40:39.871333 output: Architecture: AArch64
294 12:40:39.871419 output: Hash algo: crc32
295 12:40:39.871515 output: Hash value: 1df858fa
296 12:40:39.871600 output: Image 2 (ramdisk-1)
297 12:40:39.871692 output: Description: unavailable
298 12:40:39.871779 output: Created: Wed Jun 14 13:40:39 2023
299 12:40:39.871863 output: Type: RAMDisk Image
300 12:40:39.871952 output: Compression: Unknown Compression
301 12:40:39.872040 output: Data Size: 17645078 Bytes = 17231.52 KiB = 16.83 MiB
302 12:40:39.872125 output: Architecture: AArch64
303 12:40:39.872216 output: OS: Linux
304 12:40:39.872300 output: Load Address: unavailable
305 12:40:39.872399 output: Entry Point: unavailable
306 12:40:39.872487 output: Hash algo: crc32
307 12:40:39.872613 output: Hash value: 30c64fbd
308 12:40:39.872707 output: Default Configuration: 'conf-1'
309 12:40:39.872791 output: Configuration 0 (conf-1)
310 12:40:39.872876 output: Description: mt8192-asurada-spherion-r0
311 12:40:39.872967 output: Kernel: kernel-1
312 12:40:39.873053 output: Init Ramdisk: ramdisk-1
313 12:40:39.873136 output: FDT: fdt-1
314 12:40:39.873228 output: Loadables: kernel-1
315 12:40:39.873314 output:
316 12:40:39.873555 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 12:40:39.873700 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 12:40:39.873846 end: 1.6 prepare-tftp-overlay (duration 00:00:37) [common]
319 12:40:39.873986 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:13) [common]
320 12:40:39.874095 No LXC device requested
321 12:40:39.874215 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 12:40:39.874339 start: 1.8 deploy-device-env (timeout 00:09:13) [common]
323 12:40:39.874458 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 12:40:39.874561 Checking files for TFTP limit of 4294967296 bytes.
325 12:40:39.875241 end: 1 tftp-deploy (duration 00:00:47) [common]
326 12:40:39.875379 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 12:40:39.875513 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 12:40:39.875689 substitutions:
329 12:40:39.875793 - {DTB}: 10724841/tftp-deploy-p8zw_5gu/dtb/mt8192-asurada-spherion-r0.dtb
330 12:40:39.875887 - {INITRD}: 10724841/tftp-deploy-p8zw_5gu/ramdisk/ramdisk.cpio.gz
331 12:40:39.875993 - {KERNEL}: 10724841/tftp-deploy-p8zw_5gu/kernel/Image
332 12:40:39.876085 - {LAVA_MAC}: None
333 12:40:39.876174 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10724841/extract-nfsrootfs-sun8wizn
334 12:40:39.876271 - {NFS_SERVER_IP}: 192.168.201.1
335 12:40:39.876361 - {PRESEED_CONFIG}: None
336 12:40:39.876455 - {PRESEED_LOCAL}: None
337 12:40:39.876583 - {RAMDISK}: 10724841/tftp-deploy-p8zw_5gu/ramdisk/ramdisk.cpio.gz
338 12:40:39.876670 - {ROOT_PART}: None
339 12:40:39.876767 - {ROOT}: None
340 12:40:39.876868 - {SERVER_IP}: 192.168.201.1
341 12:40:39.876959 - {TEE}: None
342 12:40:39.877053 Parsed boot commands:
343 12:40:39.877139 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 12:40:39.877364 Parsed boot commands: tftpboot 192.168.201.1 10724841/tftp-deploy-p8zw_5gu/kernel/image.itb 10724841/tftp-deploy-p8zw_5gu/kernel/cmdline
345 12:40:39.877496 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 12:40:39.877614 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 12:40:39.877741 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 12:40:39.877865 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 12:40:39.877971 Not connected, no need to disconnect.
350 12:40:39.878080 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 12:40:39.878194 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 12:40:39.878291 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-9'
353 12:40:39.881981 Setting prompt string to ['lava-test: # ']
354 12:40:39.882374 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 12:40:39.882527 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 12:40:39.882674 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 12:40:39.882810 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 12:40:39.883148 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
359 12:40:45.018693 >> Command sent successfully.
360 12:40:45.021144 Returned 0 in 5 seconds
361 12:40:45.121533 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 12:40:45.121970 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 12:40:45.122113 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 12:40:45.122237 Setting prompt string to 'Starting depthcharge on Spherion...'
366 12:40:45.122344 Changing prompt to 'Starting depthcharge on Spherion...'
367 12:40:45.122467 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 12:40:45.122815 [Enter `^Ec?' for help]
369 12:40:45.294238
370 12:40:45.294386
371 12:40:45.294481 F0: 102B 0000
372 12:40:45.294562
373 12:40:45.294661 F3: 1001 0000 [0200]
374 12:40:45.297644
375 12:40:45.297723 F3: 1001 0000
376 12:40:45.297805
377 12:40:45.297883 F7: 102D 0000
378 12:40:45.297959
379 12:40:45.301000 F1: 0000 0000
380 12:40:45.301110
381 12:40:45.301214 V0: 0000 0000 [0001]
382 12:40:45.301314
383 12:40:45.304333 00: 0007 8000
384 12:40:45.304449
385 12:40:45.304583 01: 0000 0000
386 12:40:45.304666
387 12:40:45.307675 BP: 0C00 0209 [0000]
388 12:40:45.307773
389 12:40:45.307871 G0: 1182 0000
390 12:40:45.307968
391 12:40:45.308064 EC: 0000 0021 [4000]
392 12:40:45.311558
393 12:40:45.311656 S7: 0000 0000 [0000]
394 12:40:45.311734
395 12:40:45.315247 CC: 0000 0000 [0001]
396 12:40:45.315332
397 12:40:45.315417 T0: 0000 0040 [010F]
398 12:40:45.315500
399 12:40:45.315578 Jump to BL
400 12:40:45.315655
401 12:40:45.341269
402 12:40:45.341369
403 12:40:45.341438
404 12:40:45.348836 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 12:40:45.352777 ARM64: Exception handlers installed.
406 12:40:45.356174 ARM64: Testing exception
407 12:40:45.359700 ARM64: Done test exception
408 12:40:45.366967 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 12:40:45.374031 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 12:40:45.381574 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 12:40:45.392707 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 12:40:45.399636 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 12:40:45.406316 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 12:40:45.417572 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 12:40:45.423915 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 12:40:45.444170 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 12:40:45.447677 WDT: Last reset was cold boot
418 12:40:45.450484 SPI1(PAD0) initialized at 2873684 Hz
419 12:40:45.454194 SPI5(PAD0) initialized at 992727 Hz
420 12:40:45.457094 VBOOT: Loading verstage.
421 12:40:45.464279 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 12:40:45.467112 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 12:40:45.470461 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 12:40:45.473770 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 12:40:45.481720 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 12:40:45.488073 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 12:40:45.499401 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 12:40:45.499492
429 12:40:45.499559
430 12:40:45.509053 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 12:40:45.512444 ARM64: Exception handlers installed.
432 12:40:45.515787 ARM64: Testing exception
433 12:40:45.515872 ARM64: Done test exception
434 12:40:45.521821 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 12:40:45.525184 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 12:40:45.539803 Probing TPM: . done!
437 12:40:45.539900 TPM ready after 0 ms
438 12:40:45.546916 Connected to device vid:did:rid of 1ae0:0028:00
439 12:40:45.553552 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 12:40:45.594677 Initialized TPM device CR50 revision 0
441 12:40:45.606843 tlcl_send_startup: Startup return code is 0
442 12:40:45.606947 TPM: setup succeeded
443 12:40:45.619668 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 12:40:45.628068 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 12:40:45.638597 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 12:40:45.646761 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 12:40:45.650339 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 12:40:45.653561 in-header: 03 07 00 00 08 00 00 00
449 12:40:45.657059 in-data: aa e4 47 04 13 02 00 00
450 12:40:45.660655 Chrome EC: UHEPI supported
451 12:40:45.666756 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 12:40:45.670479 in-header: 03 ad 00 00 08 00 00 00
453 12:40:45.673533 in-data: 00 20 20 08 00 00 00 00
454 12:40:45.673617 Phase 1
455 12:40:45.679921 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 12:40:45.683389 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 12:40:45.690430 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 12:40:45.693373 Recovery requested (1009000e)
459 12:40:45.697883 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 12:40:45.706458 tlcl_extend: response is 0
461 12:40:45.715004 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 12:40:45.719788 tlcl_extend: response is 0
463 12:40:45.726119 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 12:40:45.746711 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 12:40:45.754110 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 12:40:45.754201
467 12:40:45.754269
468 12:40:45.763865 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 12:40:45.767428 ARM64: Exception handlers installed.
470 12:40:45.770792 ARM64: Testing exception
471 12:40:45.770869 ARM64: Done test exception
472 12:40:45.792889 pmic_efuse_setting: Set efuses in 11 msecs
473 12:40:45.796205 pmwrap_interface_init: Select PMIF_VLD_RDY
474 12:40:45.803302 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 12:40:45.806508 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 12:40:45.809930 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 12:40:45.816695 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 12:40:45.819883 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 12:40:45.827005 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 12:40:45.829645 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 12:40:45.836341 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 12:40:45.839783 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 12:40:45.846511 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 12:40:45.849735 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 12:40:45.853022 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 12:40:45.859292 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 12:40:45.866084 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 12:40:45.869577 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 12:40:45.875895 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 12:40:45.882590 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 12:40:45.886123 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 12:40:45.892873 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 12:40:45.899219 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 12:40:45.902824 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 12:40:45.909999 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 12:40:45.914015 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 12:40:45.921246 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 12:40:45.924897 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 12:40:45.930864 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 12:40:45.938821 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 12:40:45.941660 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 12:40:45.944996 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 12:40:45.952328 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 12:40:45.955799 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 12:40:45.962687 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 12:40:45.966110 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 12:40:45.972460 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 12:40:45.975821 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 12:40:45.982488 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 12:40:45.985616 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 12:40:45.992235 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 12:40:45.996227 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 12:40:45.999782 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 12:40:46.003188 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 12:40:46.009800 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 12:40:46.013320 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 12:40:46.016489 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 12:40:46.023223 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 12:40:46.026240 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 12:40:46.029662 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 12:40:46.036286 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 12:40:46.039603 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 12:40:46.043110 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 12:40:46.046558 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 12:40:46.056230 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 12:40:46.063168 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 12:40:46.069545 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 12:40:46.076105 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 12:40:46.086285 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 12:40:46.089638 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 12:40:46.093297 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 12:40:46.099347 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 12:40:46.106000 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x1f
534 12:40:46.109443 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 12:40:46.116791 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
536 12:40:46.120119 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 12:40:46.129629 [RTC]rtc_get_frequency_meter,154: input=15, output=834
538 12:40:46.139005 [RTC]rtc_get_frequency_meter,154: input=7, output=709
539 12:40:46.148785 [RTC]rtc_get_frequency_meter,154: input=11, output=772
540 12:40:46.157995 [RTC]rtc_get_frequency_meter,154: input=13, output=803
541 12:40:46.167450 [RTC]rtc_get_frequency_meter,154: input=12, output=788
542 12:40:46.177037 [RTC]rtc_get_frequency_meter,154: input=12, output=787
543 12:40:46.186974 [RTC]rtc_get_frequency_meter,154: input=13, output=803
544 12:40:46.189743 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
545 12:40:46.196965 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
546 12:40:46.200341 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 12:40:46.203673 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 12:40:46.210579 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 12:40:46.213604 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 12:40:46.217252 ADC[4]: Raw value=906357 ID=7
551 12:40:46.217339 ADC[3]: Raw value=214021 ID=1
552 12:40:46.220128 RAM Code: 0x71
553 12:40:46.223471 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 12:40:46.230145 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 12:40:46.237096 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 12:40:46.243755 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 12:40:46.246973 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 12:40:46.250315 in-header: 03 07 00 00 08 00 00 00
559 12:40:46.253971 in-data: aa e4 47 04 13 02 00 00
560 12:40:46.256964 Chrome EC: UHEPI supported
561 12:40:46.264038 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 12:40:46.267054 in-header: 03 dd 00 00 08 00 00 00
563 12:40:46.270196 in-data: 90 20 60 08 00 00 00 00
564 12:40:46.274047 MRC: failed to locate region type 0.
565 12:40:46.280398 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 12:40:46.283313 DRAM-K: Running full calibration
567 12:40:46.290300 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 12:40:46.290408 header.status = 0x0
569 12:40:46.293698 header.version = 0x6 (expected: 0x6)
570 12:40:46.297188 header.size = 0xd00 (expected: 0xd00)
571 12:40:46.300099 header.flags = 0x0
572 12:40:46.306671 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 12:40:46.323180 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 12:40:46.329647 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 12:40:46.332941 dram_init: ddr_geometry: 2
576 12:40:46.336757 [EMI] MDL number = 2
577 12:40:46.336844 [EMI] Get MDL freq = 0
578 12:40:46.339583 dram_init: ddr_type: 0
579 12:40:46.339667 is_discrete_lpddr4: 1
580 12:40:46.343036 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 12:40:46.343122
582 12:40:46.346780
583 12:40:46.346866 [Bian_co] ETT version 0.0.0.1
584 12:40:46.353048 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 12:40:46.353134
586 12:40:46.356480 dramc_set_vcore_voltage set vcore to 650000
587 12:40:46.359968 Read voltage for 800, 4
588 12:40:46.360053 Vio18 = 0
589 12:40:46.360121 Vcore = 650000
590 12:40:46.363074 Vdram = 0
591 12:40:46.363159 Vddq = 0
592 12:40:46.363228 Vmddr = 0
593 12:40:46.366332 dram_init: config_dvfs: 1
594 12:40:46.369964 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 12:40:46.376060 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 12:40:46.379441 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
597 12:40:46.382731 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
598 12:40:46.386253 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
599 12:40:46.392698 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
600 12:40:46.392786 MEM_TYPE=3, freq_sel=18
601 12:40:46.396025 sv_algorithm_assistance_LP4_1600
602 12:40:46.399560 ============ PULL DRAM RESETB DOWN ============
603 12:40:46.405922 ========== PULL DRAM RESETB DOWN end =========
604 12:40:46.409571 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 12:40:46.412891 ===================================
606 12:40:46.416288 LPDDR4 DRAM CONFIGURATION
607 12:40:46.419678 ===================================
608 12:40:46.419773 EX_ROW_EN[0] = 0x0
609 12:40:46.422534 EX_ROW_EN[1] = 0x0
610 12:40:46.422619 LP4Y_EN = 0x0
611 12:40:46.425854 WORK_FSP = 0x0
612 12:40:46.425940 WL = 0x2
613 12:40:46.429385 RL = 0x2
614 12:40:46.432747 BL = 0x2
615 12:40:46.432869 RPST = 0x0
616 12:40:46.436203 RD_PRE = 0x0
617 12:40:46.436318 WR_PRE = 0x1
618 12:40:46.439163 WR_PST = 0x0
619 12:40:46.439249 DBI_WR = 0x0
620 12:40:46.442509 DBI_RD = 0x0
621 12:40:46.442594 OTF = 0x1
622 12:40:46.445680 ===================================
623 12:40:46.449276 ===================================
624 12:40:46.452847 ANA top config
625 12:40:46.455622 ===================================
626 12:40:46.455713 DLL_ASYNC_EN = 0
627 12:40:46.458968 ALL_SLAVE_EN = 1
628 12:40:46.462286 NEW_RANK_MODE = 1
629 12:40:46.465684 DLL_IDLE_MODE = 1
630 12:40:46.465755 LP45_APHY_COMB_EN = 1
631 12:40:46.469140 TX_ODT_DIS = 1
632 12:40:46.472465 NEW_8X_MODE = 1
633 12:40:46.475707 ===================================
634 12:40:46.478675 ===================================
635 12:40:46.482457 data_rate = 1600
636 12:40:46.485431 CKR = 1
637 12:40:46.488684 DQ_P2S_RATIO = 8
638 12:40:46.492255 ===================================
639 12:40:46.492329 CA_P2S_RATIO = 8
640 12:40:46.495206 DQ_CA_OPEN = 0
641 12:40:46.499016 DQ_SEMI_OPEN = 0
642 12:40:46.502085 CA_SEMI_OPEN = 0
643 12:40:46.505638 CA_FULL_RATE = 0
644 12:40:46.505711 DQ_CKDIV4_EN = 1
645 12:40:46.509132 CA_CKDIV4_EN = 1
646 12:40:46.512073 CA_PREDIV_EN = 0
647 12:40:46.515767 PH8_DLY = 0
648 12:40:46.518539 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 12:40:46.522099 DQ_AAMCK_DIV = 4
650 12:40:46.522182 CA_AAMCK_DIV = 4
651 12:40:46.525549 CA_ADMCK_DIV = 4
652 12:40:46.529049 DQ_TRACK_CA_EN = 0
653 12:40:46.531790 CA_PICK = 800
654 12:40:46.535269 CA_MCKIO = 800
655 12:40:46.538718 MCKIO_SEMI = 0
656 12:40:46.542106 PLL_FREQ = 3068
657 12:40:46.545380 DQ_UI_PI_RATIO = 32
658 12:40:46.545464 CA_UI_PI_RATIO = 0
659 12:40:46.548671 ===================================
660 12:40:46.552005 ===================================
661 12:40:46.555499 memory_type:LPDDR4
662 12:40:46.558185 GP_NUM : 10
663 12:40:46.558268 SRAM_EN : 1
664 12:40:46.561992 MD32_EN : 0
665 12:40:46.565006 ===================================
666 12:40:46.568162 [ANA_INIT] >>>>>>>>>>>>>>
667 12:40:46.571647 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 12:40:46.574911 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 12:40:46.578299 ===================================
670 12:40:46.578383 data_rate = 1600,PCW = 0X7600
671 12:40:46.581873 ===================================
672 12:40:46.584912 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 12:40:46.591827 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 12:40:46.598186 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 12:40:46.601736 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 12:40:46.604569 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 12:40:46.608133 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 12:40:46.611256 [ANA_INIT] flow start
679 12:40:46.611339 [ANA_INIT] PLL >>>>>>>>
680 12:40:46.615284 [ANA_INIT] PLL <<<<<<<<
681 12:40:46.617827 [ANA_INIT] MIDPI >>>>>>>>
682 12:40:46.621649 [ANA_INIT] MIDPI <<<<<<<<
683 12:40:46.621732 [ANA_INIT] DLL >>>>>>>>
684 12:40:46.624872 [ANA_INIT] flow end
685 12:40:46.627988 ============ LP4 DIFF to SE enter ============
686 12:40:46.631462 ============ LP4 DIFF to SE exit ============
687 12:40:46.634870 [ANA_INIT] <<<<<<<<<<<<<
688 12:40:46.637688 [Flow] Enable top DCM control >>>>>
689 12:40:46.641618 [Flow] Enable top DCM control <<<<<
690 12:40:46.644623 Enable DLL master slave shuffle
691 12:40:46.651414 ==============================================================
692 12:40:46.651497 Gating Mode config
693 12:40:46.657791 ==============================================================
694 12:40:46.657901 Config description:
695 12:40:46.667484 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 12:40:46.674517 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 12:40:46.680727 SELPH_MODE 0: By rank 1: By Phase
698 12:40:46.684158 ==============================================================
699 12:40:46.687576 GAT_TRACK_EN = 1
700 12:40:46.691124 RX_GATING_MODE = 2
701 12:40:46.694557 RX_GATING_TRACK_MODE = 2
702 12:40:46.697328 SELPH_MODE = 1
703 12:40:46.700811 PICG_EARLY_EN = 1
704 12:40:46.704235 VALID_LAT_VALUE = 1
705 12:40:46.710917 ==============================================================
706 12:40:46.713975 Enter into Gating configuration >>>>
707 12:40:46.717307 Exit from Gating configuration <<<<
708 12:40:46.720583 Enter into DVFS_PRE_config >>>>>
709 12:40:46.730528 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 12:40:46.733753 Exit from DVFS_PRE_config <<<<<
711 12:40:46.737337 Enter into PICG configuration >>>>
712 12:40:46.740884 Exit from PICG configuration <<<<
713 12:40:46.744207 [RX_INPUT] configuration >>>>>
714 12:40:46.744290 [RX_INPUT] configuration <<<<<
715 12:40:46.750519 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 12:40:46.754403 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 12:40:46.761148 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 12:40:46.768123 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 12:40:46.775351 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 12:40:46.779603 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 12:40:46.782468 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 12:40:46.789895 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 12:40:46.793330 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 12:40:46.797171 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 12:40:46.800440 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 12:40:46.803945 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 12:40:46.807909 ===================================
728 12:40:46.811529 LPDDR4 DRAM CONFIGURATION
729 12:40:46.815026 ===================================
730 12:40:46.815141 EX_ROW_EN[0] = 0x0
731 12:40:46.818338 EX_ROW_EN[1] = 0x0
732 12:40:46.818421 LP4Y_EN = 0x0
733 12:40:46.821933 WORK_FSP = 0x0
734 12:40:46.822016 WL = 0x2
735 12:40:46.825866 RL = 0x2
736 12:40:46.825985 BL = 0x2
737 12:40:46.829362 RPST = 0x0
738 12:40:46.829445 RD_PRE = 0x0
739 12:40:46.833005 WR_PRE = 0x1
740 12:40:46.833088 WR_PST = 0x0
741 12:40:46.836952 DBI_WR = 0x0
742 12:40:46.837036 DBI_RD = 0x0
743 12:40:46.840694 OTF = 0x1
744 12:40:46.840817 ===================================
745 12:40:46.844219 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 12:40:46.851935 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 12:40:46.854790 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 12:40:46.858658 ===================================
749 12:40:46.862514 LPDDR4 DRAM CONFIGURATION
750 12:40:46.862594 ===================================
751 12:40:46.865851 EX_ROW_EN[0] = 0x10
752 12:40:46.865936 EX_ROW_EN[1] = 0x0
753 12:40:46.869842 LP4Y_EN = 0x0
754 12:40:46.869926 WORK_FSP = 0x0
755 12:40:46.873439 WL = 0x2
756 12:40:46.873524 RL = 0x2
757 12:40:46.877561 BL = 0x2
758 12:40:46.877645 RPST = 0x0
759 12:40:46.880947 RD_PRE = 0x0
760 12:40:46.881031 WR_PRE = 0x1
761 12:40:46.884832 WR_PST = 0x0
762 12:40:46.884916 DBI_WR = 0x0
763 12:40:46.888411 DBI_RD = 0x0
764 12:40:46.888526 OTF = 0x1
765 12:40:46.891499 ===================================
766 12:40:46.898837 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 12:40:46.902283 nWR fixed to 40
768 12:40:46.902371 [ModeRegInit_LP4] CH0 RK0
769 12:40:46.905671 [ModeRegInit_LP4] CH0 RK1
770 12:40:46.909091 [ModeRegInit_LP4] CH1 RK0
771 12:40:46.909178 [ModeRegInit_LP4] CH1 RK1
772 12:40:46.912449 match AC timing 13
773 12:40:46.916079 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 12:40:46.918814 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 12:40:46.926285 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 12:40:46.929667 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 12:40:46.936260 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 12:40:46.936345 [EMI DOE] emi_dcm 0
779 12:40:46.939372 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 12:40:46.942672 ==
781 12:40:46.945773 Dram Type= 6, Freq= 0, CH_0, rank 0
782 12:40:46.949210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 12:40:46.949295 ==
784 12:40:46.952602 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 12:40:46.959285 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 12:40:46.969171 [CA 0] Center 37 (7~68) winsize 62
787 12:40:46.972570 [CA 1] Center 36 (6~67) winsize 62
788 12:40:46.976365 [CA 2] Center 34 (4~65) winsize 62
789 12:40:46.979676 [CA 3] Center 34 (4~65) winsize 62
790 12:40:46.983217 [CA 4] Center 33 (3~64) winsize 62
791 12:40:46.986714 [CA 5] Center 33 (3~64) winsize 62
792 12:40:46.986802
793 12:40:46.989788 [CmdBusTrainingLP45] Vref(ca) range 1: 32
794 12:40:46.989872
795 12:40:46.992877 [CATrainingPosCal] consider 1 rank data
796 12:40:46.996463 u2DelayCellTimex100 = 270/100 ps
797 12:40:46.999907 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 12:40:47.003103 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
799 12:40:47.006684 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 12:40:47.009982 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 12:40:47.016325 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 12:40:47.019857 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 12:40:47.019941
804 12:40:47.023317 CA PerBit enable=1, Macro0, CA PI delay=33
805 12:40:47.023402
806 12:40:47.026666 [CBTSetCACLKResult] CA Dly = 33
807 12:40:47.026750 CS Dly: 6 (0~37)
808 12:40:47.026817 ==
809 12:40:47.029991 Dram Type= 6, Freq= 0, CH_0, rank 1
810 12:40:47.033004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 12:40:47.036479 ==
812 12:40:47.039553 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 12:40:47.046286 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 12:40:47.055371 [CA 0] Center 37 (6~68) winsize 63
815 12:40:47.058486 [CA 1] Center 37 (6~68) winsize 63
816 12:40:47.061910 [CA 2] Center 34 (4~65) winsize 62
817 12:40:47.065256 [CA 3] Center 34 (4~65) winsize 62
818 12:40:47.068325 [CA 4] Center 33 (3~64) winsize 62
819 12:40:47.071656 [CA 5] Center 33 (3~64) winsize 62
820 12:40:47.071740
821 12:40:47.074878 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 12:40:47.074961
823 12:40:47.078248 [CATrainingPosCal] consider 2 rank data
824 12:40:47.081578 u2DelayCellTimex100 = 270/100 ps
825 12:40:47.084979 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 12:40:47.088797 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
827 12:40:47.092125 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 12:40:47.098528 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 12:40:47.102741 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 12:40:47.106232 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 12:40:47.106317
832 12:40:47.109942 CA PerBit enable=1, Macro0, CA PI delay=33
833 12:40:47.110027
834 12:40:47.110098 [CBTSetCACLKResult] CA Dly = 33
835 12:40:47.114074 CS Dly: 6 (0~38)
836 12:40:47.114159
837 12:40:47.116984 ----->DramcWriteLeveling(PI) begin...
838 12:40:47.117073 ==
839 12:40:47.120498 Dram Type= 6, Freq= 0, CH_0, rank 0
840 12:40:47.123973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 12:40:47.124058 ==
842 12:40:47.127342 Write leveling (Byte 0): 34 => 34
843 12:40:47.130915 Write leveling (Byte 1): 30 => 30
844 12:40:47.133841 DramcWriteLeveling(PI) end<-----
845 12:40:47.133926
846 12:40:47.133992 ==
847 12:40:47.137222 Dram Type= 6, Freq= 0, CH_0, rank 0
848 12:40:47.140282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 12:40:47.140367 ==
850 12:40:47.143517 [Gating] SW mode calibration
851 12:40:47.150533 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 12:40:47.156816 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 12:40:47.160283 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 12:40:47.166912 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 12:40:47.170839 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
856 12:40:47.173577 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 12:40:47.176946 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 12:40:47.183749 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 12:40:47.187454 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 12:40:47.190075 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 12:40:47.197080 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 12:40:47.200456 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 12:40:47.203917 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 12:40:47.210006 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 12:40:47.213680 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 12:40:47.216734 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 12:40:47.224010 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 12:40:47.226696 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 12:40:47.230132 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 12:40:47.237049 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 12:40:47.239849 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
872 12:40:47.243264 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 12:40:47.249805 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 12:40:47.253469 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 12:40:47.256725 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 12:40:47.263103 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 12:40:47.266371 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 12:40:47.269745 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 12:40:47.276430 0 9 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
880 12:40:47.279889 0 9 12 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
881 12:40:47.283241 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 12:40:47.289861 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 12:40:47.293040 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 12:40:47.296277 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 12:40:47.302789 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 12:40:47.306767 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
887 12:40:47.309818 0 10 8 | B1->B0 | 3232 2a2a | 1 1 | (1 1) (1 0)
888 12:40:47.316317 0 10 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
889 12:40:47.319672 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 12:40:47.323174 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 12:40:47.329951 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 12:40:47.332749 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 12:40:47.336419 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 12:40:47.343032 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
895 12:40:47.346414 0 11 8 | B1->B0 | 2424 3b3b | 0 0 | (0 0) (0 0)
896 12:40:47.349838 0 11 12 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
897 12:40:47.352821 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 12:40:47.359857 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 12:40:47.363296 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 12:40:47.366218 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 12:40:47.373206 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 12:40:47.376206 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 12:40:47.379567 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
904 12:40:47.386862 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 12:40:47.390031 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 12:40:47.393275 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 12:40:47.399655 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 12:40:47.402780 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 12:40:47.406252 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 12:40:47.413092 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 12:40:47.416365 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 12:40:47.419861 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 12:40:47.425926 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 12:40:47.429793 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 12:40:47.432503 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 12:40:47.439369 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 12:40:47.442850 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 12:40:47.445706 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 12:40:47.452494 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 12:40:47.452587 Total UI for P1: 0, mck2ui 16
921 12:40:47.456155 best dqsien dly found for B0: ( 0, 14, 4)
922 12:40:47.463288 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 12:40:47.463374 Total UI for P1: 0, mck2ui 16
924 12:40:47.467355 best dqsien dly found for B1: ( 0, 14, 8)
925 12:40:47.470861 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
926 12:40:47.474656 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 12:40:47.474741
928 12:40:47.478516 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
929 12:40:47.481410 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 12:40:47.485279 [Gating] SW calibration Done
931 12:40:47.485366 ==
932 12:40:47.489265 Dram Type= 6, Freq= 0, CH_0, rank 0
933 12:40:47.492824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 12:40:47.492909 ==
935 12:40:47.496555 RX Vref Scan: 0
936 12:40:47.496640
937 12:40:47.496708 RX Vref 0 -> 0, step: 1
938 12:40:47.496772
939 12:40:47.500264 RX Delay -130 -> 252, step: 16
940 12:40:47.503606 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 12:40:47.506920 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 12:40:47.510531 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 12:40:47.517938 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 12:40:47.521597 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
945 12:40:47.524982 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
946 12:40:47.528507 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
947 12:40:47.532257 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
948 12:40:47.535655 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
949 12:40:47.539049 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
950 12:40:47.545300 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
951 12:40:47.548811 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 12:40:47.551874 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
953 12:40:47.555126 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
954 12:40:47.561838 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 12:40:47.565790 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
956 12:40:47.565876 ==
957 12:40:47.569036 Dram Type= 6, Freq= 0, CH_0, rank 0
958 12:40:47.573056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 12:40:47.573142 ==
960 12:40:47.573209 DQS Delay:
961 12:40:47.576505 DQS0 = 0, DQS1 = 0
962 12:40:47.576655 DQM Delay:
963 12:40:47.576760 DQM0 = 86, DQM1 = 73
964 12:40:47.580429 DQ Delay:
965 12:40:47.583254 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 12:40:47.587078 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
967 12:40:47.590398 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
968 12:40:47.594160 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
969 12:40:47.594257
970 12:40:47.594340
971 12:40:47.594422 ==
972 12:40:47.597805 Dram Type= 6, Freq= 0, CH_0, rank 0
973 12:40:47.601067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 12:40:47.601151 ==
975 12:40:47.601236
976 12:40:47.601314
977 12:40:47.603932 TX Vref Scan disable
978 12:40:47.604045 == TX Byte 0 ==
979 12:40:47.611109 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
980 12:40:47.614018 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
981 12:40:47.614096 == TX Byte 1 ==
982 12:40:47.620822 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
983 12:40:47.624142 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
984 12:40:47.624222 ==
985 12:40:47.627433 Dram Type= 6, Freq= 0, CH_0, rank 0
986 12:40:47.630382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 12:40:47.630474 ==
988 12:40:47.644728 TX Vref=22, minBit 0, minWin=27, winSum=439
989 12:40:47.647951 TX Vref=24, minBit 2, minWin=27, winSum=443
990 12:40:47.650826 TX Vref=26, minBit 8, minWin=27, winSum=447
991 12:40:47.654398 TX Vref=28, minBit 8, minWin=27, winSum=449
992 12:40:47.657799 TX Vref=30, minBit 10, minWin=27, winSum=449
993 12:40:47.664527 TX Vref=32, minBit 0, minWin=27, winSum=444
994 12:40:47.667909 [TxChooseVref] Worse bit 8, Min win 27, Win sum 449, Final Vref 28
995 12:40:47.668071
996 12:40:47.671204 Final TX Range 1 Vref 28
997 12:40:47.671367
998 12:40:47.671494 ==
999 12:40:47.674719 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 12:40:47.677562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 12:40:47.681124 ==
1002 12:40:47.681289
1003 12:40:47.681414
1004 12:40:47.681531 TX Vref Scan disable
1005 12:40:47.684486 == TX Byte 0 ==
1006 12:40:47.687902 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1007 12:40:47.694114 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1008 12:40:47.694276 == TX Byte 1 ==
1009 12:40:47.697359 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1010 12:40:47.704068 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1011 12:40:47.704234
1012 12:40:47.704362 [DATLAT]
1013 12:40:47.704479 Freq=800, CH0 RK0
1014 12:40:47.704616
1015 12:40:47.707198 DATLAT Default: 0xa
1016 12:40:47.707354 0, 0xFFFF, sum = 0
1017 12:40:47.710644 1, 0xFFFF, sum = 0
1018 12:40:47.714135 2, 0xFFFF, sum = 0
1019 12:40:47.714293 3, 0xFFFF, sum = 0
1020 12:40:47.717719 4, 0xFFFF, sum = 0
1021 12:40:47.717877 5, 0xFFFF, sum = 0
1022 12:40:47.720979 6, 0xFFFF, sum = 0
1023 12:40:47.721137 7, 0xFFFF, sum = 0
1024 12:40:47.724322 8, 0xFFFF, sum = 0
1025 12:40:47.724573 9, 0x0, sum = 1
1026 12:40:47.727145 10, 0x0, sum = 2
1027 12:40:47.727366 11, 0x0, sum = 3
1028 12:40:47.727550 12, 0x0, sum = 4
1029 12:40:47.730860 best_step = 10
1030 12:40:47.731056
1031 12:40:47.731240 ==
1032 12:40:47.734445 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 12:40:47.737108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 12:40:47.737320 ==
1035 12:40:47.740491 RX Vref Scan: 1
1036 12:40:47.740705
1037 12:40:47.743845 Set Vref Range= 32 -> 127
1038 12:40:47.744015
1039 12:40:47.744143 RX Vref 32 -> 127, step: 1
1040 12:40:47.744262
1041 12:40:47.747324 RX Delay -95 -> 252, step: 8
1042 12:40:47.747482
1043 12:40:47.750724 Set Vref, RX VrefLevel [Byte0]: 32
1044 12:40:47.754038 [Byte1]: 32
1045 12:40:47.754198
1046 12:40:47.757519 Set Vref, RX VrefLevel [Byte0]: 33
1047 12:40:47.760480 [Byte1]: 33
1048 12:40:47.764546
1049 12:40:47.764684 Set Vref, RX VrefLevel [Byte0]: 34
1050 12:40:47.768158 [Byte1]: 34
1051 12:40:47.772404
1052 12:40:47.772562 Set Vref, RX VrefLevel [Byte0]: 35
1053 12:40:47.775754 [Byte1]: 35
1054 12:40:47.779621
1055 12:40:47.779737 Set Vref, RX VrefLevel [Byte0]: 36
1056 12:40:47.783281 [Byte1]: 36
1057 12:40:47.787300
1058 12:40:47.790733 Set Vref, RX VrefLevel [Byte0]: 37
1059 12:40:47.790852 [Byte1]: 37
1060 12:40:47.794809
1061 12:40:47.794925 Set Vref, RX VrefLevel [Byte0]: 38
1062 12:40:47.798584 [Byte1]: 38
1063 12:40:47.802867
1064 12:40:47.802950 Set Vref, RX VrefLevel [Byte0]: 39
1065 12:40:47.805780 [Byte1]: 39
1066 12:40:47.810196
1067 12:40:47.810293 Set Vref, RX VrefLevel [Byte0]: 40
1068 12:40:47.813656 [Byte1]: 40
1069 12:40:47.818027
1070 12:40:47.818110 Set Vref, RX VrefLevel [Byte0]: 41
1071 12:40:47.820962 [Byte1]: 41
1072 12:40:47.825422
1073 12:40:47.825505 Set Vref, RX VrefLevel [Byte0]: 42
1074 12:40:47.828791 [Byte1]: 42
1075 12:40:47.833178
1076 12:40:47.833262 Set Vref, RX VrefLevel [Byte0]: 43
1077 12:40:47.836416 [Byte1]: 43
1078 12:40:47.840378
1079 12:40:47.840461 Set Vref, RX VrefLevel [Byte0]: 44
1080 12:40:47.843916 [Byte1]: 44
1081 12:40:47.848416
1082 12:40:47.848500 Set Vref, RX VrefLevel [Byte0]: 45
1083 12:40:47.851300 [Byte1]: 45
1084 12:40:47.856084
1085 12:40:47.856167 Set Vref, RX VrefLevel [Byte0]: 46
1086 12:40:47.859045 [Byte1]: 46
1087 12:40:47.863717
1088 12:40:47.863799 Set Vref, RX VrefLevel [Byte0]: 47
1089 12:40:47.866949 [Byte1]: 47
1090 12:40:47.871144
1091 12:40:47.871227 Set Vref, RX VrefLevel [Byte0]: 48
1092 12:40:47.874491 [Byte1]: 48
1093 12:40:47.878481
1094 12:40:47.878565 Set Vref, RX VrefLevel [Byte0]: 49
1095 12:40:47.881654 [Byte1]: 49
1096 12:40:47.886291
1097 12:40:47.886374 Set Vref, RX VrefLevel [Byte0]: 50
1098 12:40:47.889227 [Byte1]: 50
1099 12:40:47.893489
1100 12:40:47.893572 Set Vref, RX VrefLevel [Byte0]: 51
1101 12:40:47.897393 [Byte1]: 51
1102 12:40:47.901579
1103 12:40:47.901662 Set Vref, RX VrefLevel [Byte0]: 52
1104 12:40:47.904830 [Byte1]: 52
1105 12:40:47.908735
1106 12:40:47.908819 Set Vref, RX VrefLevel [Byte0]: 53
1107 12:40:47.912669 [Byte1]: 53
1108 12:40:47.916740
1109 12:40:47.916824 Set Vref, RX VrefLevel [Byte0]: 54
1110 12:40:47.919597 [Byte1]: 54
1111 12:40:47.924005
1112 12:40:47.924088 Set Vref, RX VrefLevel [Byte0]: 55
1113 12:40:47.927536 [Byte1]: 55
1114 12:40:47.931881
1115 12:40:47.931965 Set Vref, RX VrefLevel [Byte0]: 56
1116 12:40:47.934785 [Byte1]: 56
1117 12:40:47.939223
1118 12:40:47.939306 Set Vref, RX VrefLevel [Byte0]: 57
1119 12:40:47.942685 [Byte1]: 57
1120 12:40:47.946657
1121 12:40:47.950496 Set Vref, RX VrefLevel [Byte0]: 58
1122 12:40:47.950579 [Byte1]: 58
1123 12:40:47.954350
1124 12:40:47.954434 Set Vref, RX VrefLevel [Byte0]: 59
1125 12:40:47.957830 [Byte1]: 59
1126 12:40:47.962419
1127 12:40:47.962502 Set Vref, RX VrefLevel [Byte0]: 60
1128 12:40:47.965320 [Byte1]: 60
1129 12:40:47.969960
1130 12:40:47.970043 Set Vref, RX VrefLevel [Byte0]: 61
1131 12:40:47.973194 [Byte1]: 61
1132 12:40:47.977444
1133 12:40:47.977527 Set Vref, RX VrefLevel [Byte0]: 62
1134 12:40:47.980344 [Byte1]: 62
1135 12:40:47.984688
1136 12:40:47.984771 Set Vref, RX VrefLevel [Byte0]: 63
1137 12:40:47.988018 [Byte1]: 63
1138 12:40:47.992209
1139 12:40:47.992292 Set Vref, RX VrefLevel [Byte0]: 64
1140 12:40:47.995670 [Byte1]: 64
1141 12:40:48.000200
1142 12:40:48.000283 Set Vref, RX VrefLevel [Byte0]: 65
1143 12:40:48.003158 [Byte1]: 65
1144 12:40:48.007755
1145 12:40:48.007838 Set Vref, RX VrefLevel [Byte0]: 66
1146 12:40:48.011027 [Byte1]: 66
1147 12:40:48.015640
1148 12:40:48.015723 Set Vref, RX VrefLevel [Byte0]: 67
1149 12:40:48.018785 [Byte1]: 67
1150 12:40:48.022997
1151 12:40:48.026376 Set Vref, RX VrefLevel [Byte0]: 68
1152 12:40:48.026486 [Byte1]: 68
1153 12:40:48.030372
1154 12:40:48.030456 Set Vref, RX VrefLevel [Byte0]: 69
1155 12:40:48.033715 [Byte1]: 69
1156 12:40:48.038268
1157 12:40:48.038351 Set Vref, RX VrefLevel [Byte0]: 70
1158 12:40:48.041120 [Byte1]: 70
1159 12:40:48.045419
1160 12:40:48.048966 Set Vref, RX VrefLevel [Byte0]: 71
1161 12:40:48.052263 [Byte1]: 71
1162 12:40:48.052346
1163 12:40:48.055525 Set Vref, RX VrefLevel [Byte0]: 72
1164 12:40:48.058997 [Byte1]: 72
1165 12:40:48.059081
1166 12:40:48.061792 Set Vref, RX VrefLevel [Byte0]: 73
1167 12:40:48.065094 [Byte1]: 73
1168 12:40:48.065177
1169 12:40:48.068808 Set Vref, RX VrefLevel [Byte0]: 74
1170 12:40:48.072019 [Byte1]: 74
1171 12:40:48.076299
1172 12:40:48.076383 Set Vref, RX VrefLevel [Byte0]: 75
1173 12:40:48.079456 [Byte1]: 75
1174 12:40:48.083782
1175 12:40:48.083866 Set Vref, RX VrefLevel [Byte0]: 76
1176 12:40:48.087162 [Byte1]: 76
1177 12:40:48.091181
1178 12:40:48.091264 Set Vref, RX VrefLevel [Byte0]: 77
1179 12:40:48.094804 [Byte1]: 77
1180 12:40:48.099213
1181 12:40:48.099296 Set Vref, RX VrefLevel [Byte0]: 78
1182 12:40:48.102023 [Byte1]: 78
1183 12:40:48.107186
1184 12:40:48.107270 Set Vref, RX VrefLevel [Byte0]: 79
1185 12:40:48.109886 [Byte1]: 79
1186 12:40:48.114284
1187 12:40:48.114370 Set Vref, RX VrefLevel [Byte0]: 80
1188 12:40:48.117761 [Byte1]: 80
1189 12:40:48.121534
1190 12:40:48.121617 Set Vref, RX VrefLevel [Byte0]: 81
1191 12:40:48.124835 [Byte1]: 81
1192 12:40:48.129246
1193 12:40:48.129329 Set Vref, RX VrefLevel [Byte0]: 82
1194 12:40:48.133250 [Byte1]: 82
1195 12:40:48.137268
1196 12:40:48.137351 Set Vref, RX VrefLevel [Byte0]: 83
1197 12:40:48.140813 [Byte1]: 83
1198 12:40:48.144673
1199 12:40:48.144757 Set Vref, RX VrefLevel [Byte0]: 84
1200 12:40:48.148202 [Byte1]: 84
1201 12:40:48.151960
1202 12:40:48.152043 Final RX Vref Byte 0 = 62 to rank0
1203 12:40:48.155856 Final RX Vref Byte 1 = 59 to rank0
1204 12:40:48.159726 Final RX Vref Byte 0 = 62 to rank1
1205 12:40:48.163299 Final RX Vref Byte 1 = 59 to rank1==
1206 12:40:48.166270 Dram Type= 6, Freq= 0, CH_0, rank 0
1207 12:40:48.170294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1208 12:40:48.170406 ==
1209 12:40:48.170509 DQS Delay:
1210 12:40:48.173705 DQS0 = 0, DQS1 = 0
1211 12:40:48.173836 DQM Delay:
1212 12:40:48.177682 DQM0 = 87, DQM1 = 74
1213 12:40:48.177766 DQ Delay:
1214 12:40:48.181597 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1215 12:40:48.184454 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1216 12:40:48.187918 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1217 12:40:48.191283 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =80
1218 12:40:48.191366
1219 12:40:48.191433
1220 12:40:48.198635 [DQSOSCAuto] RK0, (LSB)MR18= 0x4022, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
1221 12:40:48.202044 CH0 RK0: MR19=606, MR18=4022
1222 12:40:48.209344 CH0_RK0: MR19=0x606, MR18=0x4022, DQSOSC=393, MR23=63, INC=95, DEC=63
1223 12:40:48.209436
1224 12:40:48.212439 ----->DramcWriteLeveling(PI) begin...
1225 12:40:48.212572 ==
1226 12:40:48.215947 Dram Type= 6, Freq= 0, CH_0, rank 1
1227 12:40:48.260370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1228 12:40:48.260493 ==
1229 12:40:48.260607 Write leveling (Byte 0): 32 => 32
1230 12:40:48.260971 Write leveling (Byte 1): 31 => 31
1231 12:40:48.261075 DramcWriteLeveling(PI) end<-----
1232 12:40:48.261147
1233 12:40:48.261228 ==
1234 12:40:48.261469 Dram Type= 6, Freq= 0, CH_0, rank 1
1235 12:40:48.261535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1236 12:40:48.261596 ==
1237 12:40:48.261653 [Gating] SW mode calibration
1238 12:40:48.262548 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1239 12:40:48.262846 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1240 12:40:48.262947 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1241 12:40:48.263040 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1242 12:40:48.282318 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1243 12:40:48.282604 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 12:40:48.282697 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 12:40:48.282763 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 12:40:48.282836 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 12:40:48.285783 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 12:40:48.289225 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 12:40:48.295996 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 12:40:48.299407 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 12:40:48.302263 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 12:40:48.308900 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 12:40:48.312266 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 12:40:48.315628 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 12:40:48.322380 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 12:40:48.325826 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 12:40:48.329265 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1258 12:40:48.335613 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1259 12:40:48.339037 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 12:40:48.342596 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 12:40:48.349439 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 12:40:48.352450 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 12:40:48.355815 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1264 12:40:48.359325 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1265 12:40:48.366059 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1266 12:40:48.368874 0 9 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
1267 12:40:48.375804 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1268 12:40:48.378709 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1269 12:40:48.382130 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1270 12:40:48.388714 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1271 12:40:48.392142 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1272 12:40:48.395465 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1273 12:40:48.401666 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1274 12:40:48.405195 0 10 8 | B1->B0 | 2f2f 2525 | 1 1 | (1 1) (1 0)
1275 12:40:48.408341 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1276 12:40:48.411917 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1277 12:40:48.418415 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1278 12:40:48.421942 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1279 12:40:48.425332 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1280 12:40:48.431964 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1281 12:40:48.435259 0 11 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1282 12:40:48.438384 0 11 8 | B1->B0 | 2d2d 3c3c | 0 0 | (0 0) (0 0)
1283 12:40:48.445090 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1284 12:40:48.448482 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1285 12:40:48.451735 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1286 12:40:48.458158 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1287 12:40:48.461772 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1288 12:40:48.465001 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1289 12:40:48.471962 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1290 12:40:48.475317 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1291 12:40:48.478775 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1292 12:40:48.484913 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1293 12:40:48.488452 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1294 12:40:48.491825 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1295 12:40:48.498065 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1296 12:40:48.501513 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1297 12:40:48.504862 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1298 12:40:48.511520 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1299 12:40:48.514911 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1300 12:40:48.518804 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1301 12:40:48.521957 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1302 12:40:48.529530 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1303 12:40:48.533341 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1304 12:40:48.536743 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1305 12:40:48.540592 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1306 12:40:48.544503 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1307 12:40:48.551268 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1308 12:40:48.551352 Total UI for P1: 0, mck2ui 16
1309 12:40:48.555198 best dqsien dly found for B0: ( 0, 14, 8)
1310 12:40:48.562245 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1311 12:40:48.562329 Total UI for P1: 0, mck2ui 16
1312 12:40:48.566277 best dqsien dly found for B1: ( 0, 14, 12)
1313 12:40:48.569614 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1314 12:40:48.573146 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
1315 12:40:48.573229
1316 12:40:48.576453 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1317 12:40:48.583734 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
1318 12:40:48.583854 [Gating] SW calibration Done
1319 12:40:48.583923 ==
1320 12:40:48.587377 Dram Type= 6, Freq= 0, CH_0, rank 1
1321 12:40:48.590975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1322 12:40:48.591059 ==
1323 12:40:48.594616 RX Vref Scan: 0
1324 12:40:48.594698
1325 12:40:48.594764 RX Vref 0 -> 0, step: 1
1326 12:40:48.594826
1327 12:40:48.598426 RX Delay -130 -> 252, step: 16
1328 12:40:48.601897 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1329 12:40:48.605619 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1330 12:40:48.613528 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1331 12:40:48.617020 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1332 12:40:48.620709 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1333 12:40:48.624189 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1334 12:40:48.627584 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1335 12:40:48.631349 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1336 12:40:48.634821 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1337 12:40:48.638216 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1338 12:40:48.642035 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1339 12:40:48.645268 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1340 12:40:48.652426 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1341 12:40:48.655960 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1342 12:40:48.659718 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1343 12:40:48.663727 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1344 12:40:48.663818 ==
1345 12:40:48.667082 Dram Type= 6, Freq= 0, CH_0, rank 1
1346 12:40:48.670520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1347 12:40:48.670604 ==
1348 12:40:48.670670 DQS Delay:
1349 12:40:48.674592 DQS0 = 0, DQS1 = 0
1350 12:40:48.674675 DQM Delay:
1351 12:40:48.677992 DQM0 = 85, DQM1 = 78
1352 12:40:48.678075 DQ Delay:
1353 12:40:48.681845 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1354 12:40:48.685953 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1355 12:40:48.689122 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1356 12:40:48.689206 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1357 12:40:48.692875
1358 12:40:48.692966
1359 12:40:48.693045 ==
1360 12:40:48.696535 Dram Type= 6, Freq= 0, CH_0, rank 1
1361 12:40:48.700008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1362 12:40:48.700110 ==
1363 12:40:48.700180
1364 12:40:48.700241
1365 12:40:48.700298 TX Vref Scan disable
1366 12:40:48.704123 == TX Byte 0 ==
1367 12:40:48.707452 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1368 12:40:48.711106 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1369 12:40:48.714869 == TX Byte 1 ==
1370 12:40:48.718457 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1371 12:40:48.721691 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1372 12:40:48.721772 ==
1373 12:40:48.725553 Dram Type= 6, Freq= 0, CH_0, rank 1
1374 12:40:48.728890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1375 12:40:48.728973 ==
1376 12:40:48.743253 TX Vref=22, minBit 9, minWin=27, winSum=443
1377 12:40:48.746593 TX Vref=24, minBit 8, minWin=27, winSum=446
1378 12:40:48.750511 TX Vref=26, minBit 9, minWin=27, winSum=444
1379 12:40:48.754285 TX Vref=28, minBit 9, minWin=27, winSum=447
1380 12:40:48.758276 TX Vref=30, minBit 9, minWin=27, winSum=449
1381 12:40:48.761429 TX Vref=32, minBit 8, minWin=27, winSum=447
1382 12:40:48.768449 [TxChooseVref] Worse bit 9, Min win 27, Win sum 449, Final Vref 30
1383 12:40:48.768573
1384 12:40:48.768643 Final TX Range 1 Vref 30
1385 12:40:48.768704
1386 12:40:48.768762 ==
1387 12:40:48.772156 Dram Type= 6, Freq= 0, CH_0, rank 1
1388 12:40:48.775835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1389 12:40:48.775921 ==
1390 12:40:48.779238
1391 12:40:48.779320
1392 12:40:48.779384 TX Vref Scan disable
1393 12:40:48.782832 == TX Byte 0 ==
1394 12:40:48.786430 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1395 12:40:48.790083 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1396 12:40:48.793352 == TX Byte 1 ==
1397 12:40:48.797336 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1398 12:40:48.800741 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1399 12:40:48.800816
1400 12:40:48.800889 [DATLAT]
1401 12:40:48.804197 Freq=800, CH0 RK1
1402 12:40:48.804274
1403 12:40:48.804336 DATLAT Default: 0xa
1404 12:40:48.807818 0, 0xFFFF, sum = 0
1405 12:40:48.807893 1, 0xFFFF, sum = 0
1406 12:40:48.811835 2, 0xFFFF, sum = 0
1407 12:40:48.811909 3, 0xFFFF, sum = 0
1408 12:40:48.815783 4, 0xFFFF, sum = 0
1409 12:40:48.815869 5, 0xFFFF, sum = 0
1410 12:40:48.819276 6, 0xFFFF, sum = 0
1411 12:40:48.819383 7, 0xFFFF, sum = 0
1412 12:40:48.822859 8, 0xFFFF, sum = 0
1413 12:40:48.822941 9, 0x0, sum = 1
1414 12:40:48.823007 10, 0x0, sum = 2
1415 12:40:48.826214 11, 0x0, sum = 3
1416 12:40:48.826318 12, 0x0, sum = 4
1417 12:40:48.829933 best_step = 10
1418 12:40:48.830011
1419 12:40:48.830074 ==
1420 12:40:48.833920 Dram Type= 6, Freq= 0, CH_0, rank 1
1421 12:40:48.837222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1422 12:40:48.837300 ==
1423 12:40:48.837364 RX Vref Scan: 0
1424 12:40:48.837423
1425 12:40:48.841175 RX Vref 0 -> 0, step: 1
1426 12:40:48.841252
1427 12:40:48.844459 RX Delay -95 -> 252, step: 8
1428 12:40:48.848488 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1429 12:40:48.852399 iDelay=209, Bit 1, Center 88 (-31 ~ 208) 240
1430 12:40:48.855872 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1431 12:40:48.858951 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1432 12:40:48.865206 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1433 12:40:48.868512 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1434 12:40:48.871881 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1435 12:40:48.875224 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1436 12:40:48.878649 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1437 12:40:48.885291 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
1438 12:40:48.888612 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
1439 12:40:48.891976 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1440 12:40:48.895102 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1441 12:40:48.898399 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1442 12:40:48.905421 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1443 12:40:48.908767 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1444 12:40:48.908872 ==
1445 12:40:48.911821 Dram Type= 6, Freq= 0, CH_0, rank 1
1446 12:40:48.915208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 12:40:48.915281 ==
1448 12:40:48.918522 DQS Delay:
1449 12:40:48.918619 DQS0 = 0, DQS1 = 0
1450 12:40:48.918708 DQM Delay:
1451 12:40:48.921900 DQM0 = 86, DQM1 = 77
1452 12:40:48.921980 DQ Delay:
1453 12:40:48.925317 DQ0 =80, DQ1 =88, DQ2 =80, DQ3 =84
1454 12:40:48.928734 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1455 12:40:48.931542 DQ8 =68, DQ9 =60, DQ10 =84, DQ11 =68
1456 12:40:48.935281 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =84
1457 12:40:48.935379
1458 12:40:48.935475
1459 12:40:48.944673 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d04, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
1460 12:40:48.948065 CH0 RK1: MR19=606, MR18=3D04
1461 12:40:48.951448 CH0_RK1: MR19=0x606, MR18=0x3D04, DQSOSC=394, MR23=63, INC=95, DEC=63
1462 12:40:48.954690 [RxdqsGatingPostProcess] freq 800
1463 12:40:48.961316 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1464 12:40:48.964951 Pre-setting of DQS Precalculation
1465 12:40:48.967985 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1466 12:40:48.968069 ==
1467 12:40:48.971215 Dram Type= 6, Freq= 0, CH_1, rank 0
1468 12:40:48.978700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1469 12:40:48.978785 ==
1470 12:40:48.981485 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1471 12:40:48.988086 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1472 12:40:48.997723 [CA 0] Center 36 (6~67) winsize 62
1473 12:40:49.000803 [CA 1] Center 36 (6~67) winsize 62
1474 12:40:49.003785 [CA 2] Center 34 (4~65) winsize 62
1475 12:40:49.007153 [CA 3] Center 34 (3~65) winsize 63
1476 12:40:49.010753 [CA 4] Center 34 (4~65) winsize 62
1477 12:40:49.014153 [CA 5] Center 34 (3~65) winsize 63
1478 12:40:49.014236
1479 12:40:49.017080 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1480 12:40:49.017163
1481 12:40:49.020477 [CATrainingPosCal] consider 1 rank data
1482 12:40:49.023870 u2DelayCellTimex100 = 270/100 ps
1483 12:40:49.026942 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1484 12:40:49.033768 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1485 12:40:49.037183 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1486 12:40:49.040513 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1487 12:40:49.043921 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1488 12:40:49.047377 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1489 12:40:49.047461
1490 12:40:49.050622 CA PerBit enable=1, Macro0, CA PI delay=34
1491 12:40:49.050706
1492 12:40:49.054055 [CBTSetCACLKResult] CA Dly = 34
1493 12:40:49.054139 CS Dly: 5 (0~36)
1494 12:40:49.057372 ==
1495 12:40:49.060296 Dram Type= 6, Freq= 0, CH_1, rank 1
1496 12:40:49.063556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1497 12:40:49.063640 ==
1498 12:40:49.067340 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1499 12:40:49.073794 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1500 12:40:49.083820 [CA 0] Center 36 (6~67) winsize 62
1501 12:40:49.087265 [CA 1] Center 36 (6~67) winsize 62
1502 12:40:49.090388 [CA 2] Center 34 (4~65) winsize 62
1503 12:40:49.093280 [CA 3] Center 34 (3~65) winsize 63
1504 12:40:49.096755 [CA 4] Center 34 (4~65) winsize 62
1505 12:40:49.100102 [CA 5] Center 34 (3~65) winsize 63
1506 12:40:49.100185
1507 12:40:49.103300 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1508 12:40:49.103384
1509 12:40:49.106580 [CATrainingPosCal] consider 2 rank data
1510 12:40:49.110144 u2DelayCellTimex100 = 270/100 ps
1511 12:40:49.113298 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1512 12:40:49.119699 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1513 12:40:49.123539 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1514 12:40:49.126446 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1515 12:40:49.129977 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1516 12:40:49.133061 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1517 12:40:49.133144
1518 12:40:49.136645 CA PerBit enable=1, Macro0, CA PI delay=34
1519 12:40:49.136729
1520 12:40:49.140048 [CBTSetCACLKResult] CA Dly = 34
1521 12:40:49.140131 CS Dly: 6 (0~38)
1522 12:40:49.143435
1523 12:40:49.146741 ----->DramcWriteLeveling(PI) begin...
1524 12:40:49.146827 ==
1525 12:40:49.149976 Dram Type= 6, Freq= 0, CH_1, rank 0
1526 12:40:49.152863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1527 12:40:49.152947 ==
1528 12:40:49.156241 Write leveling (Byte 0): 26 => 26
1529 12:40:49.159703 Write leveling (Byte 1): 27 => 27
1530 12:40:49.162946 DramcWriteLeveling(PI) end<-----
1531 12:40:49.163030
1532 12:40:49.163095 ==
1533 12:40:49.166149 Dram Type= 6, Freq= 0, CH_1, rank 0
1534 12:40:49.169656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1535 12:40:49.169740 ==
1536 12:40:49.173077 [Gating] SW mode calibration
1537 12:40:49.179522 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1538 12:40:49.185958 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1539 12:40:49.189630 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1540 12:40:49.192734 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1541 12:40:49.199683 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 12:40:49.203063 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 12:40:49.206234 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 12:40:49.212486 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 12:40:49.216211 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 12:40:49.219437 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 12:40:49.225857 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 12:40:49.229434 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 12:40:49.232829 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 12:40:49.239029 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 12:40:49.242468 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 12:40:49.246151 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 12:40:49.252231 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 12:40:49.255784 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 12:40:49.259005 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 12:40:49.265714 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1557 12:40:49.268812 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1558 12:40:49.272215 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 12:40:49.278984 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 12:40:49.282213 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 12:40:49.285953 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1562 12:40:49.289330 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1563 12:40:49.295920 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1564 12:40:49.299192 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1565 12:40:49.302163 0 9 8 | B1->B0 | 2a2a 3030 | 1 1 | (0 0) (0 0)
1566 12:40:49.309024 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1567 12:40:49.312322 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1568 12:40:49.315395 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1569 12:40:49.322221 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1570 12:40:49.325218 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1571 12:40:49.328802 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1572 12:40:49.335173 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 0) (1 1)
1573 12:40:49.339155 0 10 8 | B1->B0 | 2525 2424 | 0 0 | (1 1) (0 0)
1574 12:40:49.341914 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1575 12:40:49.348660 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1576 12:40:49.351884 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1577 12:40:49.355147 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1578 12:40:49.361542 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1579 12:40:49.364847 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1580 12:40:49.368885 0 11 4 | B1->B0 | 2525 2727 | 0 0 | (0 0) (0 0)
1581 12:40:49.375056 0 11 8 | B1->B0 | 3737 3a3a | 1 1 | (0 0) (0 0)
1582 12:40:49.378412 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1583 12:40:49.381829 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1584 12:40:49.388677 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1585 12:40:49.391510 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1586 12:40:49.395311 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1587 12:40:49.401531 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1588 12:40:49.404962 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1589 12:40:49.408148 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1590 12:40:49.414914 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1591 12:40:49.418162 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1592 12:40:49.421641 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1593 12:40:49.428187 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1594 12:40:49.430988 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1595 12:40:49.434528 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1596 12:40:49.441562 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1597 12:40:49.444232 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1598 12:40:49.447656 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1599 12:40:49.454209 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1600 12:40:49.457738 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1601 12:40:49.461106 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1602 12:40:49.467769 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1603 12:40:49.471078 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1604 12:40:49.474513 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1605 12:40:49.481007 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1606 12:40:49.481091 Total UI for P1: 0, mck2ui 16
1607 12:40:49.484431 best dqsien dly found for B0: ( 0, 14, 2)
1608 12:40:49.487391 Total UI for P1: 0, mck2ui 16
1609 12:40:49.490840 best dqsien dly found for B1: ( 0, 14, 6)
1610 12:40:49.494590 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1611 12:40:49.501030 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1612 12:40:49.501113
1613 12:40:49.504225 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1614 12:40:49.507515 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1615 12:40:49.510782 [Gating] SW calibration Done
1616 12:40:49.510866 ==
1617 12:40:49.514235 Dram Type= 6, Freq= 0, CH_1, rank 0
1618 12:40:49.517345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1619 12:40:49.517428 ==
1620 12:40:49.517525 RX Vref Scan: 0
1621 12:40:49.520933
1622 12:40:49.521015 RX Vref 0 -> 0, step: 1
1623 12:40:49.521080
1624 12:40:49.524359 RX Delay -130 -> 252, step: 16
1625 12:40:49.527282 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1626 12:40:49.530731 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1627 12:40:49.537469 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1628 12:40:49.540934 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1629 12:40:49.543762 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1630 12:40:49.547135 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1631 12:40:49.554144 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1632 12:40:49.557061 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1633 12:40:49.560502 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1634 12:40:49.563666 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1635 12:40:49.567271 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1636 12:40:49.573443 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1637 12:40:49.577215 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1638 12:40:49.580146 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1639 12:40:49.583615 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1640 12:40:49.586878 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1641 12:40:49.590377 ==
1642 12:40:49.593595 Dram Type= 6, Freq= 0, CH_1, rank 0
1643 12:40:49.597097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1644 12:40:49.597180 ==
1645 12:40:49.597247 DQS Delay:
1646 12:40:49.600387 DQS0 = 0, DQS1 = 0
1647 12:40:49.600469 DQM Delay:
1648 12:40:49.603515 DQM0 = 89, DQM1 = 80
1649 12:40:49.603598 DQ Delay:
1650 12:40:49.606775 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1651 12:40:49.610452 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1652 12:40:49.613351 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1653 12:40:49.617179 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =93
1654 12:40:49.617262
1655 12:40:49.617328
1656 12:40:49.617388 ==
1657 12:40:49.620428 Dram Type= 6, Freq= 0, CH_1, rank 0
1658 12:40:49.623756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1659 12:40:49.623839 ==
1660 12:40:49.623906
1661 12:40:49.623967
1662 12:40:49.626706 TX Vref Scan disable
1663 12:40:49.630146 == TX Byte 0 ==
1664 12:40:49.633561 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1665 12:40:49.636980 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1666 12:40:49.639949 == TX Byte 1 ==
1667 12:40:49.643439 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1668 12:40:49.646865 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1669 12:40:49.646947 ==
1670 12:40:49.650313 Dram Type= 6, Freq= 0, CH_1, rank 0
1671 12:40:49.656490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1672 12:40:49.656620 ==
1673 12:40:49.668211 TX Vref=22, minBit 3, minWin=27, winSum=443
1674 12:40:49.671435 TX Vref=24, minBit 15, minWin=27, winSum=451
1675 12:40:49.675013 TX Vref=26, minBit 10, minWin=27, winSum=449
1676 12:40:49.678478 TX Vref=28, minBit 13, minWin=27, winSum=450
1677 12:40:49.681898 TX Vref=30, minBit 8, minWin=27, winSum=447
1678 12:40:49.687963 TX Vref=32, minBit 8, minWin=27, winSum=445
1679 12:40:49.691261 [TxChooseVref] Worse bit 15, Min win 27, Win sum 451, Final Vref 24
1680 12:40:49.691352
1681 12:40:49.694886 Final TX Range 1 Vref 24
1682 12:40:49.694969
1683 12:40:49.695037 ==
1684 12:40:49.698297 Dram Type= 6, Freq= 0, CH_1, rank 0
1685 12:40:49.701195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1686 12:40:49.705080 ==
1687 12:40:49.705162
1688 12:40:49.705228
1689 12:40:49.705290 TX Vref Scan disable
1690 12:40:49.708276 == TX Byte 0 ==
1691 12:40:49.711778 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1692 12:40:49.718513 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1693 12:40:49.718604 == TX Byte 1 ==
1694 12:40:49.721358 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1695 12:40:49.728482 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1696 12:40:49.728602
1697 12:40:49.728668 [DATLAT]
1698 12:40:49.728729 Freq=800, CH1 RK0
1699 12:40:49.728789
1700 12:40:49.731846 DATLAT Default: 0xa
1701 12:40:49.731928 0, 0xFFFF, sum = 0
1702 12:40:49.734724 1, 0xFFFF, sum = 0
1703 12:40:49.738236 2, 0xFFFF, sum = 0
1704 12:40:49.738320 3, 0xFFFF, sum = 0
1705 12:40:49.741857 4, 0xFFFF, sum = 0
1706 12:40:49.741941 5, 0xFFFF, sum = 0
1707 12:40:49.744520 6, 0xFFFF, sum = 0
1708 12:40:49.744604 7, 0xFFFF, sum = 0
1709 12:40:49.748171 8, 0xFFFF, sum = 0
1710 12:40:49.748255 9, 0x0, sum = 1
1711 12:40:49.751714 10, 0x0, sum = 2
1712 12:40:49.751797 11, 0x0, sum = 3
1713 12:40:49.751864 12, 0x0, sum = 4
1714 12:40:49.754514 best_step = 10
1715 12:40:49.754596
1716 12:40:49.754662 ==
1717 12:40:49.757807 Dram Type= 6, Freq= 0, CH_1, rank 0
1718 12:40:49.761302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1719 12:40:49.761387 ==
1720 12:40:49.764620 RX Vref Scan: 1
1721 12:40:49.764702
1722 12:40:49.767762 Set Vref Range= 32 -> 127
1723 12:40:49.767844
1724 12:40:49.767911 RX Vref 32 -> 127, step: 1
1725 12:40:49.767972
1726 12:40:49.771232 RX Delay -95 -> 252, step: 8
1727 12:40:49.771314
1728 12:40:49.774703 Set Vref, RX VrefLevel [Byte0]: 32
1729 12:40:49.778037 [Byte1]: 32
1730 12:40:49.781230
1731 12:40:49.781312 Set Vref, RX VrefLevel [Byte0]: 33
1732 12:40:49.784777 [Byte1]: 33
1733 12:40:49.789233
1734 12:40:49.789315 Set Vref, RX VrefLevel [Byte0]: 34
1735 12:40:49.791853 [Byte1]: 34
1736 12:40:49.796334
1737 12:40:49.796420 Set Vref, RX VrefLevel [Byte0]: 35
1738 12:40:49.799752 [Byte1]: 35
1739 12:40:49.803876
1740 12:40:49.803959 Set Vref, RX VrefLevel [Byte0]: 36
1741 12:40:49.807390 [Byte1]: 36
1742 12:40:49.811567
1743 12:40:49.811649 Set Vref, RX VrefLevel [Byte0]: 37
1744 12:40:49.814708 [Byte1]: 37
1745 12:40:49.819037
1746 12:40:49.819118 Set Vref, RX VrefLevel [Byte0]: 38
1747 12:40:49.822336 [Byte1]: 38
1748 12:40:49.826723
1749 12:40:49.826819 Set Vref, RX VrefLevel [Byte0]: 39
1750 12:40:49.830337 [Byte1]: 39
1751 12:40:49.834593
1752 12:40:49.834676 Set Vref, RX VrefLevel [Byte0]: 40
1753 12:40:49.837806 [Byte1]: 40
1754 12:40:49.842047
1755 12:40:49.842128 Set Vref, RX VrefLevel [Byte0]: 41
1756 12:40:49.845263 [Byte1]: 41
1757 12:40:49.849471
1758 12:40:49.849553 Set Vref, RX VrefLevel [Byte0]: 42
1759 12:40:49.852861 [Byte1]: 42
1760 12:40:49.857014
1761 12:40:49.857097 Set Vref, RX VrefLevel [Byte0]: 43
1762 12:40:49.860337 [Byte1]: 43
1763 12:40:49.864695
1764 12:40:49.864778 Set Vref, RX VrefLevel [Byte0]: 44
1765 12:40:49.868223 [Byte1]: 44
1766 12:40:49.872458
1767 12:40:49.872582 Set Vref, RX VrefLevel [Byte0]: 45
1768 12:40:49.875808 [Byte1]: 45
1769 12:40:49.879971
1770 12:40:49.880053 Set Vref, RX VrefLevel [Byte0]: 46
1771 12:40:49.883299 [Byte1]: 46
1772 12:40:49.887532
1773 12:40:49.887614 Set Vref, RX VrefLevel [Byte0]: 47
1774 12:40:49.891122 [Byte1]: 47
1775 12:40:49.895645
1776 12:40:49.895727 Set Vref, RX VrefLevel [Byte0]: 48
1777 12:40:49.898362 [Byte1]: 48
1778 12:40:49.902875
1779 12:40:49.902956 Set Vref, RX VrefLevel [Byte0]: 49
1780 12:40:49.905703 [Byte1]: 49
1781 12:40:49.910351
1782 12:40:49.910488 Set Vref, RX VrefLevel [Byte0]: 50
1783 12:40:49.913831 [Byte1]: 50
1784 12:40:49.917730
1785 12:40:49.917815 Set Vref, RX VrefLevel [Byte0]: 51
1786 12:40:49.920847 [Byte1]: 51
1787 12:40:49.925619
1788 12:40:49.925702 Set Vref, RX VrefLevel [Byte0]: 52
1789 12:40:49.928680 [Byte1]: 52
1790 12:40:49.933018
1791 12:40:49.933101 Set Vref, RX VrefLevel [Byte0]: 53
1792 12:40:49.936046 [Byte1]: 53
1793 12:40:49.940410
1794 12:40:49.943918 Set Vref, RX VrefLevel [Byte0]: 54
1795 12:40:49.947169 [Byte1]: 54
1796 12:40:49.947253
1797 12:40:49.950294 Set Vref, RX VrefLevel [Byte0]: 55
1798 12:40:49.953795 [Byte1]: 55
1799 12:40:49.953882
1800 12:40:49.956701 Set Vref, RX VrefLevel [Byte0]: 56
1801 12:40:49.960046 [Byte1]: 56
1802 12:40:49.963731
1803 12:40:49.963812 Set Vref, RX VrefLevel [Byte0]: 57
1804 12:40:49.967074 [Byte1]: 57
1805 12:40:49.970926
1806 12:40:49.971012 Set Vref, RX VrefLevel [Byte0]: 58
1807 12:40:49.974222 [Byte1]: 58
1808 12:40:49.978847
1809 12:40:49.978928 Set Vref, RX VrefLevel [Byte0]: 59
1810 12:40:49.982343 [Byte1]: 59
1811 12:40:49.986404
1812 12:40:49.986485 Set Vref, RX VrefLevel [Byte0]: 60
1813 12:40:49.989623 [Byte1]: 60
1814 12:40:49.993926
1815 12:40:49.994006 Set Vref, RX VrefLevel [Byte0]: 61
1816 12:40:49.997322 [Byte1]: 61
1817 12:40:50.001885
1818 12:40:50.001967 Set Vref, RX VrefLevel [Byte0]: 62
1819 12:40:50.004471 [Byte1]: 62
1820 12:40:50.009195
1821 12:40:50.009277 Set Vref, RX VrefLevel [Byte0]: 63
1822 12:40:50.012157 [Byte1]: 63
1823 12:40:50.016857
1824 12:40:50.016937 Set Vref, RX VrefLevel [Byte0]: 64
1825 12:40:50.019670 [Byte1]: 64
1826 12:40:50.023976
1827 12:40:50.024056 Set Vref, RX VrefLevel [Byte0]: 65
1828 12:40:50.027654 [Byte1]: 65
1829 12:40:50.031996
1830 12:40:50.032078 Set Vref, RX VrefLevel [Byte0]: 66
1831 12:40:50.035004 [Byte1]: 66
1832 12:40:50.038974
1833 12:40:50.042390 Set Vref, RX VrefLevel [Byte0]: 67
1834 12:40:50.045659 [Byte1]: 67
1835 12:40:50.045745
1836 12:40:50.048870 Set Vref, RX VrefLevel [Byte0]: 68
1837 12:40:50.052442 [Byte1]: 68
1838 12:40:50.052564
1839 12:40:50.055820 Set Vref, RX VrefLevel [Byte0]: 69
1840 12:40:50.059165 [Byte1]: 69
1841 12:40:50.059247
1842 12:40:50.062233 Set Vref, RX VrefLevel [Byte0]: 70
1843 12:40:50.065863 [Byte1]: 70
1844 12:40:50.069654
1845 12:40:50.069736 Set Vref, RX VrefLevel [Byte0]: 71
1846 12:40:50.076105 [Byte1]: 71
1847 12:40:50.076188
1848 12:40:50.079626 Set Vref, RX VrefLevel [Byte0]: 72
1849 12:40:50.082766 [Byte1]: 72
1850 12:40:50.082848
1851 12:40:50.086242 Set Vref, RX VrefLevel [Byte0]: 73
1852 12:40:50.089838 [Byte1]: 73
1853 12:40:50.092507
1854 12:40:50.092630 Final RX Vref Byte 0 = 56 to rank0
1855 12:40:50.095844 Final RX Vref Byte 1 = 65 to rank0
1856 12:40:50.099268 Final RX Vref Byte 0 = 56 to rank1
1857 12:40:50.102704 Final RX Vref Byte 1 = 65 to rank1==
1858 12:40:50.106113 Dram Type= 6, Freq= 0, CH_1, rank 0
1859 12:40:50.112926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1860 12:40:50.113011 ==
1861 12:40:50.113077 DQS Delay:
1862 12:40:50.113139 DQS0 = 0, DQS1 = 0
1863 12:40:50.115884 DQM Delay:
1864 12:40:50.115967 DQM0 = 87, DQM1 = 79
1865 12:40:50.119413 DQ Delay:
1866 12:40:50.122854 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1867 12:40:50.125836 DQ4 =84, DQ5 =100, DQ6 =100, DQ7 =80
1868 12:40:50.128919 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1869 12:40:50.132330 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1870 12:40:50.132412
1871 12:40:50.132477
1872 12:40:50.139707 [DQSOSCAuto] RK0, (LSB)MR18= 0x331f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
1873 12:40:50.142423 CH1 RK0: MR19=606, MR18=331F
1874 12:40:50.148804 CH1_RK0: MR19=0x606, MR18=0x331F, DQSOSC=396, MR23=63, INC=94, DEC=62
1875 12:40:50.148888
1876 12:40:50.152045 ----->DramcWriteLeveling(PI) begin...
1877 12:40:50.152129 ==
1878 12:40:50.155739 Dram Type= 6, Freq= 0, CH_1, rank 1
1879 12:40:50.159104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1880 12:40:50.159187 ==
1881 12:40:50.162039 Write leveling (Byte 0): 27 => 27
1882 12:40:50.165333 Write leveling (Byte 1): 29 => 29
1883 12:40:50.168868 DramcWriteLeveling(PI) end<-----
1884 12:40:50.168950
1885 12:40:50.169014 ==
1886 12:40:50.172007 Dram Type= 6, Freq= 0, CH_1, rank 1
1887 12:40:50.175432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1888 12:40:50.175514 ==
1889 12:40:50.178969 [Gating] SW mode calibration
1890 12:40:50.185540 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1891 12:40:50.191842 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1892 12:40:50.195253 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1893 12:40:50.201893 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1894 12:40:50.205101 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 12:40:50.208645 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 12:40:50.215474 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 12:40:50.218385 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 12:40:50.221886 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 12:40:50.225332 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 12:40:50.231774 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 12:40:50.234914 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 12:40:50.238153 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 12:40:50.245236 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 12:40:50.248449 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 12:40:50.251710 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 12:40:50.258669 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 12:40:50.261937 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 12:40:50.265392 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1909 12:40:50.271603 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1910 12:40:50.274951 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1911 12:40:50.278303 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 12:40:50.285260 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 12:40:50.288323 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 12:40:50.291838 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 12:40:50.298129 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 12:40:50.301478 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 12:40:50.304678 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 12:40:50.311492 0 9 8 | B1->B0 | 3131 2a29 | 1 1 | (1 1) (0 0)
1919 12:40:50.314897 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1920 12:40:50.318435 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1921 12:40:50.324766 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1922 12:40:50.328162 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1923 12:40:50.331227 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1924 12:40:50.337999 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1925 12:40:50.340960 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1926 12:40:50.344656 0 10 8 | B1->B0 | 2626 2e2e | 0 0 | (0 0) (1 0)
1927 12:40:50.351442 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1928 12:40:50.354695 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1929 12:40:50.357770 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1930 12:40:50.364433 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1931 12:40:50.367735 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1932 12:40:50.371232 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1933 12:40:50.377519 0 11 4 | B1->B0 | 2b2b 2727 | 0 0 | (1 1) (0 0)
1934 12:40:50.380858 0 11 8 | B1->B0 | 4444 3737 | 0 0 | (0 0) (1 1)
1935 12:40:50.384126 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1936 12:40:50.390853 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1937 12:40:50.394178 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1938 12:40:50.397654 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1939 12:40:50.404150 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1940 12:40:50.407847 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1941 12:40:50.411287 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1942 12:40:50.414492 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1943 12:40:50.421186 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 12:40:50.424098 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 12:40:50.427544 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 12:40:50.434086 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 12:40:50.437522 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 12:40:50.440947 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 12:40:50.447518 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1950 12:40:50.450776 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 12:40:50.454465 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1952 12:40:50.460547 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1953 12:40:50.463823 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1954 12:40:50.467075 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1955 12:40:50.473793 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1956 12:40:50.476984 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1957 12:40:50.480663 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1958 12:40:50.487135 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1959 12:40:50.490113 Total UI for P1: 0, mck2ui 16
1960 12:40:50.494026 best dqsien dly found for B1: ( 0, 14, 4)
1961 12:40:50.497029 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1962 12:40:50.500296 Total UI for P1: 0, mck2ui 16
1963 12:40:50.503595 best dqsien dly found for B0: ( 0, 14, 6)
1964 12:40:50.507262 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1965 12:40:50.509984 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1966 12:40:50.510057
1967 12:40:50.513600 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1968 12:40:50.516831 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1969 12:40:50.520152 [Gating] SW calibration Done
1970 12:40:50.520249 ==
1971 12:40:50.523665 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 12:40:50.526858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 12:40:50.529932 ==
1974 12:40:50.530031 RX Vref Scan: 0
1975 12:40:50.530128
1976 12:40:50.533304 RX Vref 0 -> 0, step: 1
1977 12:40:50.533377
1978 12:40:50.536918 RX Delay -130 -> 252, step: 16
1979 12:40:50.539837 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1980 12:40:50.543182 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1981 12:40:50.547175 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1982 12:40:50.549884 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1983 12:40:50.557128 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1984 12:40:50.560354 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1985 12:40:50.563116 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1986 12:40:50.566714 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1987 12:40:50.570054 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1988 12:40:50.576342 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1989 12:40:50.579726 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1990 12:40:50.583395 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1991 12:40:50.586459 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1992 12:40:50.593201 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1993 12:40:50.596749 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1994 12:40:50.599602 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1995 12:40:50.599685 ==
1996 12:40:50.603141 Dram Type= 6, Freq= 0, CH_1, rank 1
1997 12:40:50.606687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1998 12:40:50.606770 ==
1999 12:40:50.609935 DQS Delay:
2000 12:40:50.610017 DQS0 = 0, DQS1 = 0
2001 12:40:50.610083 DQM Delay:
2002 12:40:50.612963 DQM0 = 87, DQM1 = 78
2003 12:40:50.613045 DQ Delay:
2004 12:40:50.616641 DQ0 =93, DQ1 =77, DQ2 =69, DQ3 =85
2005 12:40:50.619690 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
2006 12:40:50.623065 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
2007 12:40:50.626162 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2008 12:40:50.626245
2009 12:40:50.626311
2010 12:40:50.626372 ==
2011 12:40:50.629667 Dram Type= 6, Freq= 0, CH_1, rank 1
2012 12:40:50.636024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2013 12:40:50.636108 ==
2014 12:40:50.636176
2015 12:40:50.636238
2016 12:40:50.639546 TX Vref Scan disable
2017 12:40:50.639638 == TX Byte 0 ==
2018 12:40:50.643066 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2019 12:40:50.649311 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2020 12:40:50.649404 == TX Byte 1 ==
2021 12:40:50.652931 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2022 12:40:50.659459 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2023 12:40:50.659543 ==
2024 12:40:50.662672 Dram Type= 6, Freq= 0, CH_1, rank 1
2025 12:40:50.665772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2026 12:40:50.665856 ==
2027 12:40:50.679484 TX Vref=22, minBit 1, minWin=27, winSum=441
2028 12:40:50.682846 TX Vref=24, minBit 9, minWin=27, winSum=447
2029 12:40:50.685785 TX Vref=26, minBit 8, minWin=26, winSum=446
2030 12:40:50.689666 TX Vref=28, minBit 13, minWin=27, winSum=448
2031 12:40:50.692464 TX Vref=30, minBit 8, minWin=27, winSum=451
2032 12:40:50.699352 TX Vref=32, minBit 8, minWin=27, winSum=445
2033 12:40:50.702677 [TxChooseVref] Worse bit 8, Min win 27, Win sum 451, Final Vref 30
2034 12:40:50.702769
2035 12:40:50.706027 Final TX Range 1 Vref 30
2036 12:40:50.706112
2037 12:40:50.706177 ==
2038 12:40:50.708947 Dram Type= 6, Freq= 0, CH_1, rank 1
2039 12:40:50.712309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2040 12:40:50.715849 ==
2041 12:40:50.715932
2042 12:40:50.716007
2043 12:40:50.716069 TX Vref Scan disable
2044 12:40:50.719195 == TX Byte 0 ==
2045 12:40:50.722583 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2046 12:40:50.729288 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2047 12:40:50.729386 == TX Byte 1 ==
2048 12:40:50.732720 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2049 12:40:50.739661 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2050 12:40:50.739745
2051 12:40:50.739811 [DATLAT]
2052 12:40:50.739873 Freq=800, CH1 RK1
2053 12:40:50.739931
2054 12:40:50.742639 DATLAT Default: 0xa
2055 12:40:50.742708 0, 0xFFFF, sum = 0
2056 12:40:50.745906 1, 0xFFFF, sum = 0
2057 12:40:50.745979 2, 0xFFFF, sum = 0
2058 12:40:50.749356 3, 0xFFFF, sum = 0
2059 12:40:50.752784 4, 0xFFFF, sum = 0
2060 12:40:50.752861 5, 0xFFFF, sum = 0
2061 12:40:50.755666 6, 0xFFFF, sum = 0
2062 12:40:50.755739 7, 0xFFFF, sum = 0
2063 12:40:50.759244 8, 0xFFFF, sum = 0
2064 12:40:50.759314 9, 0x0, sum = 1
2065 12:40:50.762467 10, 0x0, sum = 2
2066 12:40:50.762538 11, 0x0, sum = 3
2067 12:40:50.762600 12, 0x0, sum = 4
2068 12:40:50.765749 best_step = 10
2069 12:40:50.765821
2070 12:40:50.765881 ==
2071 12:40:50.769098 Dram Type= 6, Freq= 0, CH_1, rank 1
2072 12:40:50.772178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2073 12:40:50.772247 ==
2074 12:40:50.775622 RX Vref Scan: 0
2075 12:40:50.775696
2076 12:40:50.775758 RX Vref 0 -> 0, step: 1
2077 12:40:50.778932
2078 12:40:50.779006 RX Delay -95 -> 252, step: 8
2079 12:40:50.785764 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2080 12:40:50.789423 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2081 12:40:50.792584 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2082 12:40:50.795889 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2083 12:40:50.802542 iDelay=217, Bit 4, Center 88 (-23 ~ 200) 224
2084 12:40:50.805440 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2085 12:40:50.809108 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2086 12:40:50.812261 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2087 12:40:50.815684 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2088 12:40:50.822111 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2089 12:40:50.825251 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2090 12:40:50.828543 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2091 12:40:50.832169 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2092 12:40:50.835564 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2093 12:40:50.842004 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2094 12:40:50.845528 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2095 12:40:50.845606 ==
2096 12:40:50.849120 Dram Type= 6, Freq= 0, CH_1, rank 1
2097 12:40:50.851792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2098 12:40:50.851865 ==
2099 12:40:50.855175 DQS Delay:
2100 12:40:50.855245 DQS0 = 0, DQS1 = 0
2101 12:40:50.855307 DQM Delay:
2102 12:40:50.858750 DQM0 = 87, DQM1 = 78
2103 12:40:50.858819 DQ Delay:
2104 12:40:50.861718 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2105 12:40:50.865032 DQ4 =88, DQ5 =96, DQ6 =100, DQ7 =84
2106 12:40:50.868323 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
2107 12:40:50.871680 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2108 12:40:50.871755
2109 12:40:50.871816
2110 12:40:50.881579 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b13, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2111 12:40:50.884915 CH1 RK1: MR19=606, MR18=1B13
2112 12:40:50.888825 CH1_RK1: MR19=0x606, MR18=0x1B13, DQSOSC=403, MR23=63, INC=90, DEC=60
2113 12:40:50.891472 [RxdqsGatingPostProcess] freq 800
2114 12:40:50.898458 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2115 12:40:50.901710 Pre-setting of DQS Precalculation
2116 12:40:50.905051 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2117 12:40:50.914968 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2118 12:40:50.921498 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2119 12:40:50.921577
2120 12:40:50.921648
2121 12:40:50.924958 [Calibration Summary] 1600 Mbps
2122 12:40:50.925035 CH 0, Rank 0
2123 12:40:50.928181 SW Impedance : PASS
2124 12:40:50.928281 DUTY Scan : NO K
2125 12:40:50.931717 ZQ Calibration : PASS
2126 12:40:50.935097 Jitter Meter : NO K
2127 12:40:50.935175 CBT Training : PASS
2128 12:40:50.938589 Write leveling : PASS
2129 12:40:50.941387 RX DQS gating : PASS
2130 12:40:50.941464 RX DQ/DQS(RDDQC) : PASS
2131 12:40:50.944918 TX DQ/DQS : PASS
2132 12:40:50.947881 RX DATLAT : PASS
2133 12:40:50.947954 RX DQ/DQS(Engine): PASS
2134 12:40:50.951239 TX OE : NO K
2135 12:40:50.951318 All Pass.
2136 12:40:50.951387
2137 12:40:50.954672 CH 0, Rank 1
2138 12:40:50.954742 SW Impedance : PASS
2139 12:40:50.957825 DUTY Scan : NO K
2140 12:40:50.961275 ZQ Calibration : PASS
2141 12:40:50.961351 Jitter Meter : NO K
2142 12:40:50.964699 CBT Training : PASS
2143 12:40:50.967559 Write leveling : PASS
2144 12:40:50.967632 RX DQS gating : PASS
2145 12:40:50.970888 RX DQ/DQS(RDDQC) : PASS
2146 12:40:50.970959 TX DQ/DQS : PASS
2147 12:40:50.974345 RX DATLAT : PASS
2148 12:40:50.977653 RX DQ/DQS(Engine): PASS
2149 12:40:50.977725 TX OE : NO K
2150 12:40:50.980816 All Pass.
2151 12:40:50.980894
2152 12:40:50.980960 CH 1, Rank 0
2153 12:40:50.984304 SW Impedance : PASS
2154 12:40:50.984377 DUTY Scan : NO K
2155 12:40:50.987641 ZQ Calibration : PASS
2156 12:40:50.991304 Jitter Meter : NO K
2157 12:40:50.991386 CBT Training : PASS
2158 12:40:50.994560 Write leveling : PASS
2159 12:40:50.998014 RX DQS gating : PASS
2160 12:40:50.998086 RX DQ/DQS(RDDQC) : PASS
2161 12:40:51.001119 TX DQ/DQS : PASS
2162 12:40:51.004412 RX DATLAT : PASS
2163 12:40:51.004559 RX DQ/DQS(Engine): PASS
2164 12:40:51.007505 TX OE : NO K
2165 12:40:51.007585 All Pass.
2166 12:40:51.007650
2167 12:40:51.010895 CH 1, Rank 1
2168 12:40:51.010976 SW Impedance : PASS
2169 12:40:51.014434 DUTY Scan : NO K
2170 12:40:51.017634 ZQ Calibration : PASS
2171 12:40:51.017717 Jitter Meter : NO K
2172 12:40:51.020922 CBT Training : PASS
2173 12:40:51.020992 Write leveling : PASS
2174 12:40:51.024313 RX DQS gating : PASS
2175 12:40:51.027652 RX DQ/DQS(RDDQC) : PASS
2176 12:40:51.027731 TX DQ/DQS : PASS
2177 12:40:51.031179 RX DATLAT : PASS
2178 12:40:51.034358 RX DQ/DQS(Engine): PASS
2179 12:40:51.034432 TX OE : NO K
2180 12:40:51.037840 All Pass.
2181 12:40:51.037924
2182 12:40:51.038027 DramC Write-DBI off
2183 12:40:51.040735 PER_BANK_REFRESH: Hybrid Mode
2184 12:40:51.043866 TX_TRACKING: ON
2185 12:40:51.047471 [GetDramInforAfterCalByMRR] Vendor 6.
2186 12:40:51.051016 [GetDramInforAfterCalByMRR] Revision 606.
2187 12:40:51.054326 [GetDramInforAfterCalByMRR] Revision 2 0.
2188 12:40:51.054406 MR0 0x3b3b
2189 12:40:51.054473 MR8 0x5151
2190 12:40:51.060606 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2191 12:40:51.060684
2192 12:40:51.060751 MR0 0x3b3b
2193 12:40:51.060811 MR8 0x5151
2194 12:40:51.064198 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2195 12:40:51.064298
2196 12:40:51.074059 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2197 12:40:51.077336 [FAST_K] Save calibration result to emmc
2198 12:40:51.080257 [FAST_K] Save calibration result to emmc
2199 12:40:51.083902 dram_init: config_dvfs: 1
2200 12:40:51.087418 dramc_set_vcore_voltage set vcore to 662500
2201 12:40:51.090243 Read voltage for 1200, 2
2202 12:40:51.090325 Vio18 = 0
2203 12:40:51.093633 Vcore = 662500
2204 12:40:51.093719 Vdram = 0
2205 12:40:51.093786 Vddq = 0
2206 12:40:51.093848 Vmddr = 0
2207 12:40:51.100310 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2208 12:40:51.103955 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2209 12:40:51.106818 MEM_TYPE=3, freq_sel=15
2210 12:40:51.110401 sv_algorithm_assistance_LP4_1600
2211 12:40:51.113795 ============ PULL DRAM RESETB DOWN ============
2212 12:40:51.120714 ========== PULL DRAM RESETB DOWN end =========
2213 12:40:51.123566 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2214 12:40:51.126887 ===================================
2215 12:40:51.130279 LPDDR4 DRAM CONFIGURATION
2216 12:40:51.133339 ===================================
2217 12:40:51.133411 EX_ROW_EN[0] = 0x0
2218 12:40:51.136758 EX_ROW_EN[1] = 0x0
2219 12:40:51.136843 LP4Y_EN = 0x0
2220 12:40:51.139909 WORK_FSP = 0x0
2221 12:40:51.140017 WL = 0x4
2222 12:40:51.143567 RL = 0x4
2223 12:40:51.143649 BL = 0x2
2224 12:40:51.147011 RPST = 0x0
2225 12:40:51.147094 RD_PRE = 0x0
2226 12:40:51.150381 WR_PRE = 0x1
2227 12:40:51.153854 WR_PST = 0x0
2228 12:40:51.153936 DBI_WR = 0x0
2229 12:40:51.156727 DBI_RD = 0x0
2230 12:40:51.156809 OTF = 0x1
2231 12:40:51.160195 ===================================
2232 12:40:51.163594 ===================================
2233 12:40:51.163676 ANA top config
2234 12:40:51.166980 ===================================
2235 12:40:51.170005 DLL_ASYNC_EN = 0
2236 12:40:51.173387 ALL_SLAVE_EN = 0
2237 12:40:51.177062 NEW_RANK_MODE = 1
2238 12:40:51.179815 DLL_IDLE_MODE = 1
2239 12:40:51.179900 LP45_APHY_COMB_EN = 1
2240 12:40:51.183379 TX_ODT_DIS = 1
2241 12:40:51.186564 NEW_8X_MODE = 1
2242 12:40:51.190429 ===================================
2243 12:40:51.193672 ===================================
2244 12:40:51.196954 data_rate = 2400
2245 12:40:51.199806 CKR = 1
2246 12:40:51.199890 DQ_P2S_RATIO = 8
2247 12:40:51.203701 ===================================
2248 12:40:51.206615 CA_P2S_RATIO = 8
2249 12:40:51.209890 DQ_CA_OPEN = 0
2250 12:40:51.213431 DQ_SEMI_OPEN = 0
2251 12:40:51.216834 CA_SEMI_OPEN = 0
2252 12:40:51.220029 CA_FULL_RATE = 0
2253 12:40:51.220114 DQ_CKDIV4_EN = 0
2254 12:40:51.223193 CA_CKDIV4_EN = 0
2255 12:40:51.226476 CA_PREDIV_EN = 0
2256 12:40:51.229770 PH8_DLY = 17
2257 12:40:51.233186 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2258 12:40:51.236697 DQ_AAMCK_DIV = 4
2259 12:40:51.236780 CA_AAMCK_DIV = 4
2260 12:40:51.239810 CA_ADMCK_DIV = 4
2261 12:40:51.243387 DQ_TRACK_CA_EN = 0
2262 12:40:51.246077 CA_PICK = 1200
2263 12:40:51.249468 CA_MCKIO = 1200
2264 12:40:51.252639 MCKIO_SEMI = 0
2265 12:40:51.256252 PLL_FREQ = 2366
2266 12:40:51.259474 DQ_UI_PI_RATIO = 32
2267 12:40:51.259575 CA_UI_PI_RATIO = 0
2268 12:40:51.263051 ===================================
2269 12:40:51.266508 ===================================
2270 12:40:51.269332 memory_type:LPDDR4
2271 12:40:51.272715 GP_NUM : 10
2272 12:40:51.272788 SRAM_EN : 1
2273 12:40:51.276297 MD32_EN : 0
2274 12:40:51.279801 ===================================
2275 12:40:51.282500 [ANA_INIT] >>>>>>>>>>>>>>
2276 12:40:51.286194 <<<<<< [CONFIGURE PHASE]: ANA_TX
2277 12:40:51.289044 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2278 12:40:51.292745 ===================================
2279 12:40:51.292856 data_rate = 2400,PCW = 0X5b00
2280 12:40:51.295885 ===================================
2281 12:40:51.299264 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2282 12:40:51.305987 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2283 12:40:51.312489 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2284 12:40:51.315609 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2285 12:40:51.318956 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2286 12:40:51.322362 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2287 12:40:51.325486 [ANA_INIT] flow start
2288 12:40:51.328965 [ANA_INIT] PLL >>>>>>>>
2289 12:40:51.329066 [ANA_INIT] PLL <<<<<<<<
2290 12:40:51.332378 [ANA_INIT] MIDPI >>>>>>>>
2291 12:40:51.335521 [ANA_INIT] MIDPI <<<<<<<<
2292 12:40:51.335624 [ANA_INIT] DLL >>>>>>>>
2293 12:40:51.339117 [ANA_INIT] DLL <<<<<<<<
2294 12:40:51.342366 [ANA_INIT] flow end
2295 12:40:51.345707 ============ LP4 DIFF to SE enter ============
2296 12:40:51.348442 ============ LP4 DIFF to SE exit ============
2297 12:40:51.351892 [ANA_INIT] <<<<<<<<<<<<<
2298 12:40:51.355665 [Flow] Enable top DCM control >>>>>
2299 12:40:51.358944 [Flow] Enable top DCM control <<<<<
2300 12:40:51.362356 Enable DLL master slave shuffle
2301 12:40:51.365323 ==============================================================
2302 12:40:51.368586 Gating Mode config
2303 12:40:51.375081 ==============================================================
2304 12:40:51.375164 Config description:
2305 12:40:51.385488 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2306 12:40:51.391836 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2307 12:40:51.395023 SELPH_MODE 0: By rank 1: By Phase
2308 12:40:51.401524 ==============================================================
2309 12:40:51.404957 GAT_TRACK_EN = 1
2310 12:40:51.408329 RX_GATING_MODE = 2
2311 12:40:51.411730 RX_GATING_TRACK_MODE = 2
2312 12:40:51.414948 SELPH_MODE = 1
2313 12:40:51.418640 PICG_EARLY_EN = 1
2314 12:40:51.421799 VALID_LAT_VALUE = 1
2315 12:40:51.425116 ==============================================================
2316 12:40:51.428284 Enter into Gating configuration >>>>
2317 12:40:51.431473 Exit from Gating configuration <<<<
2318 12:40:51.434807 Enter into DVFS_PRE_config >>>>>
2319 12:40:51.448526 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2320 12:40:51.448628 Exit from DVFS_PRE_config <<<<<
2321 12:40:51.451305 Enter into PICG configuration >>>>
2322 12:40:51.454696 Exit from PICG configuration <<<<
2323 12:40:51.458137 [RX_INPUT] configuration >>>>>
2324 12:40:51.461235 [RX_INPUT] configuration <<<<<
2325 12:40:51.468070 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2326 12:40:51.471073 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2327 12:40:51.478208 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2328 12:40:51.484552 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2329 12:40:51.490843 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2330 12:40:51.498078 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2331 12:40:51.500756 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2332 12:40:51.504330 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2333 12:40:51.507534 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2334 12:40:51.514292 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2335 12:40:51.517596 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2336 12:40:51.521158 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2337 12:40:51.524415 ===================================
2338 12:40:51.527349 LPDDR4 DRAM CONFIGURATION
2339 12:40:51.531013 ===================================
2340 12:40:51.534376 EX_ROW_EN[0] = 0x0
2341 12:40:51.534452 EX_ROW_EN[1] = 0x0
2342 12:40:51.537585 LP4Y_EN = 0x0
2343 12:40:51.537658 WORK_FSP = 0x0
2344 12:40:51.540618 WL = 0x4
2345 12:40:51.540706 RL = 0x4
2346 12:40:51.544330 BL = 0x2
2347 12:40:51.544400 RPST = 0x0
2348 12:40:51.547032 RD_PRE = 0x0
2349 12:40:51.547106 WR_PRE = 0x1
2350 12:40:51.550913 WR_PST = 0x0
2351 12:40:51.550992 DBI_WR = 0x0
2352 12:40:51.554106 DBI_RD = 0x0
2353 12:40:51.554176 OTF = 0x1
2354 12:40:51.556975 ===================================
2355 12:40:51.564251 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2356 12:40:51.567253 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2357 12:40:51.570718 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2358 12:40:51.573801 ===================================
2359 12:40:51.577186 LPDDR4 DRAM CONFIGURATION
2360 12:40:51.580749 ===================================
2361 12:40:51.583497 EX_ROW_EN[0] = 0x10
2362 12:40:51.583565 EX_ROW_EN[1] = 0x0
2363 12:40:51.586831 LP4Y_EN = 0x0
2364 12:40:51.586899 WORK_FSP = 0x0
2365 12:40:51.590301 WL = 0x4
2366 12:40:51.590370 RL = 0x4
2367 12:40:51.593808 BL = 0x2
2368 12:40:51.593877 RPST = 0x0
2369 12:40:51.596808 RD_PRE = 0x0
2370 12:40:51.596879 WR_PRE = 0x1
2371 12:40:51.600412 WR_PST = 0x0
2372 12:40:51.600509 DBI_WR = 0x0
2373 12:40:51.603547 DBI_RD = 0x0
2374 12:40:51.603615 OTF = 0x1
2375 12:40:51.606823 ===================================
2376 12:40:51.613676 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2377 12:40:51.613751 ==
2378 12:40:51.617065 Dram Type= 6, Freq= 0, CH_0, rank 0
2379 12:40:51.623627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2380 12:40:51.623702 ==
2381 12:40:51.623764 [Duty_Offset_Calibration]
2382 12:40:51.626710 B0:1 B1:-1 CA:0
2383 12:40:51.626789
2384 12:40:51.630175 [DutyScan_Calibration_Flow] k_type=0
2385 12:40:51.639349
2386 12:40:51.639428 ==CLK 0==
2387 12:40:51.642225 Final CLK duty delay cell = 0
2388 12:40:51.645968 [0] MAX Duty = 5125%(X100), DQS PI = 24
2389 12:40:51.649122 [0] MIN Duty = 4907%(X100), DQS PI = 8
2390 12:40:51.649227 [0] AVG Duty = 5016%(X100)
2391 12:40:51.652545
2392 12:40:51.652620 CH0 CLK Duty spec in!! Max-Min= 218%
2393 12:40:51.659012 [DutyScan_Calibration_Flow] ====Done====
2394 12:40:51.659084
2395 12:40:51.662166 [DutyScan_Calibration_Flow] k_type=1
2396 12:40:51.676510
2397 12:40:51.676621 ==DQS 0 ==
2398 12:40:51.680157 Final DQS duty delay cell = -4
2399 12:40:51.683543 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2400 12:40:51.686536 [-4] MIN Duty = 4875%(X100), DQS PI = 56
2401 12:40:51.689931 [-4] AVG Duty = 4968%(X100)
2402 12:40:51.690002
2403 12:40:51.690063 ==DQS 1 ==
2404 12:40:51.692860 Final DQS duty delay cell = -4
2405 12:40:51.696271 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2406 12:40:51.699590 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2407 12:40:51.702942 [-4] AVG Duty = 4938%(X100)
2408 12:40:51.703009
2409 12:40:51.705998 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2410 12:40:51.706064
2411 12:40:51.709815 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2412 12:40:51.713233 [DutyScan_Calibration_Flow] ====Done====
2413 12:40:51.713304
2414 12:40:51.716165 [DutyScan_Calibration_Flow] k_type=3
2415 12:40:51.734662
2416 12:40:51.734746 ==DQM 0 ==
2417 12:40:51.738149 Final DQM duty delay cell = 0
2418 12:40:51.741349 [0] MAX Duty = 5062%(X100), DQS PI = 18
2419 12:40:51.744627 [0] MIN Duty = 4875%(X100), DQS PI = 8
2420 12:40:51.744700 [0] AVG Duty = 4968%(X100)
2421 12:40:51.747818
2422 12:40:51.747888 ==DQM 1 ==
2423 12:40:51.751139 Final DQM duty delay cell = 4
2424 12:40:51.754441 [4] MAX Duty = 5187%(X100), DQS PI = 14
2425 12:40:51.757752 [4] MIN Duty = 4969%(X100), DQS PI = 26
2426 12:40:51.761404 [4] AVG Duty = 5078%(X100)
2427 12:40:51.761486
2428 12:40:51.764500 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2429 12:40:51.764594
2430 12:40:51.767796 CH0 DQM 1 Duty spec in!! Max-Min= 218%
2431 12:40:51.771649 [DutyScan_Calibration_Flow] ====Done====
2432 12:40:51.771732
2433 12:40:51.774808 [DutyScan_Calibration_Flow] k_type=2
2434 12:40:51.789654
2435 12:40:51.789731 ==DQ 0 ==
2436 12:40:51.792757 Final DQ duty delay cell = -4
2437 12:40:51.796307 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2438 12:40:51.799844 [-4] MIN Duty = 4907%(X100), DQS PI = 48
2439 12:40:51.802737 [-4] AVG Duty = 4969%(X100)
2440 12:40:51.802823
2441 12:40:51.802889 ==DQ 1 ==
2442 12:40:51.806229 Final DQ duty delay cell = -4
2443 12:40:51.809758 [-4] MAX Duty = 5000%(X100), DQS PI = 54
2444 12:40:51.812699 [-4] MIN Duty = 4876%(X100), DQS PI = 40
2445 12:40:51.816017 [-4] AVG Duty = 4938%(X100)
2446 12:40:51.816124
2447 12:40:51.819265 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2448 12:40:51.819337
2449 12:40:51.822697 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2450 12:40:51.825906 [DutyScan_Calibration_Flow] ====Done====
2451 12:40:51.825977 ==
2452 12:40:51.829381 Dram Type= 6, Freq= 0, CH_1, rank 0
2453 12:40:51.832731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2454 12:40:51.832804 ==
2455 12:40:51.836232 [Duty_Offset_Calibration]
2456 12:40:51.836329 B0:-1 B1:1 CA:1
2457 12:40:51.839093
2458 12:40:51.842450 [DutyScan_Calibration_Flow] k_type=0
2459 12:40:51.850278
2460 12:40:51.850364 ==CLK 0==
2461 12:40:51.853543 Final CLK duty delay cell = 0
2462 12:40:51.856775 [0] MAX Duty = 5187%(X100), DQS PI = 22
2463 12:40:51.860414 [0] MIN Duty = 4969%(X100), DQS PI = 62
2464 12:40:51.863741 [0] AVG Duty = 5078%(X100)
2465 12:40:51.863820
2466 12:40:51.866938 CH1 CLK Duty spec in!! Max-Min= 218%
2467 12:40:51.870097 [DutyScan_Calibration_Flow] ====Done====
2468 12:40:51.870175
2469 12:40:51.873516 [DutyScan_Calibration_Flow] k_type=1
2470 12:40:51.889698
2471 12:40:51.889785 ==DQS 0 ==
2472 12:40:51.892915 Final DQS duty delay cell = 0
2473 12:40:51.896468 [0] MAX Duty = 5156%(X100), DQS PI = 50
2474 12:40:51.899519 [0] MIN Duty = 4907%(X100), DQS PI = 8
2475 12:40:51.899596 [0] AVG Duty = 5031%(X100)
2476 12:40:51.902959
2477 12:40:51.903036 ==DQS 1 ==
2478 12:40:51.905977 Final DQS duty delay cell = 0
2479 12:40:51.909453 [0] MAX Duty = 5094%(X100), DQS PI = 12
2480 12:40:51.912785 [0] MIN Duty = 4969%(X100), DQS PI = 58
2481 12:40:51.916117 [0] AVG Duty = 5031%(X100)
2482 12:40:51.916195
2483 12:40:51.919542 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2484 12:40:51.919642
2485 12:40:51.922420 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2486 12:40:51.926166 [DutyScan_Calibration_Flow] ====Done====
2487 12:40:51.926245
2488 12:40:51.929463 [DutyScan_Calibration_Flow] k_type=3
2489 12:40:51.944976
2490 12:40:51.945055 ==DQM 0 ==
2491 12:40:51.948402 Final DQM duty delay cell = -4
2492 12:40:51.951908 [-4] MAX Duty = 5062%(X100), DQS PI = 36
2493 12:40:51.955159 [-4] MIN Duty = 4876%(X100), DQS PI = 6
2494 12:40:51.958399 [-4] AVG Duty = 4969%(X100)
2495 12:40:51.958473
2496 12:40:51.958536 ==DQM 1 ==
2497 12:40:51.961562 Final DQM duty delay cell = 0
2498 12:40:51.965174 [0] MAX Duty = 5187%(X100), DQS PI = 6
2499 12:40:51.968377 [0] MIN Duty = 4969%(X100), DQS PI = 28
2500 12:40:51.971621 [0] AVG Duty = 5078%(X100)
2501 12:40:51.971696
2502 12:40:51.974768 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2503 12:40:51.974841
2504 12:40:51.978573 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2505 12:40:51.981600 [DutyScan_Calibration_Flow] ====Done====
2506 12:40:51.981702
2507 12:40:51.985001 [DutyScan_Calibration_Flow] k_type=2
2508 12:40:52.001898
2509 12:40:52.001986 ==DQ 0 ==
2510 12:40:52.005340 Final DQ duty delay cell = 0
2511 12:40:52.008673 [0] MAX Duty = 5187%(X100), DQS PI = 32
2512 12:40:52.011680 [0] MIN Duty = 4907%(X100), DQS PI = 8
2513 12:40:52.011755 [0] AVG Duty = 5047%(X100)
2514 12:40:52.015024
2515 12:40:52.015101 ==DQ 1 ==
2516 12:40:52.018412 Final DQ duty delay cell = 0
2517 12:40:52.021622 [0] MAX Duty = 5156%(X100), DQS PI = 10
2518 12:40:52.025166 [0] MIN Duty = 4969%(X100), DQS PI = 60
2519 12:40:52.025250 [0] AVG Duty = 5062%(X100)
2520 12:40:52.025318
2521 12:40:52.028326 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2522 12:40:52.031712
2523 12:40:52.035175 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2524 12:40:52.038513 [DutyScan_Calibration_Flow] ====Done====
2525 12:40:52.041605 nWR fixed to 30
2526 12:40:52.041689 [ModeRegInit_LP4] CH0 RK0
2527 12:40:52.044973 [ModeRegInit_LP4] CH0 RK1
2528 12:40:52.048630 [ModeRegInit_LP4] CH1 RK0
2529 12:40:52.052049 [ModeRegInit_LP4] CH1 RK1
2530 12:40:52.052128 match AC timing 7
2531 12:40:52.054944 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2532 12:40:52.061454 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2533 12:40:52.064950 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2534 12:40:52.071331 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2535 12:40:52.074730 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2536 12:40:52.074822 ==
2537 12:40:52.078016 Dram Type= 6, Freq= 0, CH_0, rank 0
2538 12:40:52.081759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2539 12:40:52.081845 ==
2540 12:40:52.088014 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2541 12:40:52.094507 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2542 12:40:52.101669 [CA 0] Center 39 (9~70) winsize 62
2543 12:40:52.105199 [CA 1] Center 39 (9~69) winsize 61
2544 12:40:52.108711 [CA 2] Center 35 (5~66) winsize 62
2545 12:40:52.112196 [CA 3] Center 35 (5~66) winsize 62
2546 12:40:52.115143 [CA 4] Center 33 (4~63) winsize 60
2547 12:40:52.118505 [CA 5] Center 33 (3~63) winsize 61
2548 12:40:52.118583
2549 12:40:52.121509 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2550 12:40:52.121588
2551 12:40:52.124924 [CATrainingPosCal] consider 1 rank data
2552 12:40:52.128216 u2DelayCellTimex100 = 270/100 ps
2553 12:40:52.131530 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2554 12:40:52.138459 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2555 12:40:52.142000 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2556 12:40:52.144926 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2557 12:40:52.147854 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2558 12:40:52.151239 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2559 12:40:52.151324
2560 12:40:52.154685 CA PerBit enable=1, Macro0, CA PI delay=33
2561 12:40:52.154782
2562 12:40:52.157759 [CBTSetCACLKResult] CA Dly = 33
2563 12:40:52.161478 CS Dly: 8 (0~39)
2564 12:40:52.161559 ==
2565 12:40:52.164789 Dram Type= 6, Freq= 0, CH_0, rank 1
2566 12:40:52.167899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2567 12:40:52.167977 ==
2568 12:40:52.174874 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2569 12:40:52.178023 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2570 12:40:52.187600 [CA 0] Center 39 (8~70) winsize 63
2571 12:40:52.191002 [CA 1] Center 39 (9~70) winsize 62
2572 12:40:52.194402 [CA 2] Center 35 (5~66) winsize 62
2573 12:40:52.197671 [CA 3] Center 34 (4~65) winsize 62
2574 12:40:52.200785 [CA 4] Center 33 (3~64) winsize 62
2575 12:40:52.204056 [CA 5] Center 33 (3~63) winsize 61
2576 12:40:52.204159
2577 12:40:52.207419 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2578 12:40:52.207527
2579 12:40:52.210936 [CATrainingPosCal] consider 2 rank data
2580 12:40:52.214484 u2DelayCellTimex100 = 270/100 ps
2581 12:40:52.217485 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2582 12:40:52.223812 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2583 12:40:52.227156 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2584 12:40:52.230852 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2585 12:40:52.234323 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2586 12:40:52.237033 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2587 12:40:52.237126
2588 12:40:52.240301 CA PerBit enable=1, Macro0, CA PI delay=33
2589 12:40:52.240377
2590 12:40:52.243818 [CBTSetCACLKResult] CA Dly = 33
2591 12:40:52.243898 CS Dly: 9 (0~41)
2592 12:40:52.247174
2593 12:40:52.250317 ----->DramcWriteLeveling(PI) begin...
2594 12:40:52.250401 ==
2595 12:40:52.254296 Dram Type= 6, Freq= 0, CH_0, rank 0
2596 12:40:52.257136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2597 12:40:52.257235 ==
2598 12:40:52.260542 Write leveling (Byte 0): 31 => 31
2599 12:40:52.264004 Write leveling (Byte 1): 27 => 27
2600 12:40:52.267427 DramcWriteLeveling(PI) end<-----
2601 12:40:52.267530
2602 12:40:52.267628 ==
2603 12:40:52.270624 Dram Type= 6, Freq= 0, CH_0, rank 0
2604 12:40:52.273648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2605 12:40:52.273727 ==
2606 12:40:52.277164 [Gating] SW mode calibration
2607 12:40:52.283669 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2608 12:40:52.290074 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2609 12:40:52.293832 0 15 0 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
2610 12:40:52.296920 0 15 4 | B1->B0 | 2626 3434 | 1 1 | (0 0) (1 1)
2611 12:40:52.303675 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2612 12:40:52.307355 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2613 12:40:52.310286 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2614 12:40:52.316727 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2615 12:40:52.320139 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2616 12:40:52.323549 0 15 28 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (0 0)
2617 12:40:52.329887 1 0 0 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
2618 12:40:52.333685 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2619 12:40:52.336593 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2620 12:40:52.343323 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2621 12:40:52.346561 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2622 12:40:52.350002 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2623 12:40:52.356953 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2624 12:40:52.360409 1 0 28 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
2625 12:40:52.363412 1 1 0 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
2626 12:40:52.366575 1 1 4 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2627 12:40:52.373202 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2628 12:40:52.376592 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2629 12:40:52.380034 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2630 12:40:52.386328 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2631 12:40:52.389822 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2632 12:40:52.392994 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2633 12:40:52.399332 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2634 12:40:52.402998 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2635 12:40:52.409189 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 12:40:52.412774 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 12:40:52.415836 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 12:40:52.419376 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 12:40:52.425741 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 12:40:52.429279 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2641 12:40:52.432700 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2642 12:40:52.439223 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2643 12:40:52.442193 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2644 12:40:52.445439 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2645 12:40:52.452309 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2646 12:40:52.455715 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2647 12:40:52.459196 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2648 12:40:52.465626 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2649 12:40:52.469080 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2650 12:40:52.472448 Total UI for P1: 0, mck2ui 16
2651 12:40:52.475799 best dqsien dly found for B0: ( 1, 3, 26)
2652 12:40:52.478867 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2653 12:40:52.482297 Total UI for P1: 0, mck2ui 16
2654 12:40:52.485761 best dqsien dly found for B1: ( 1, 4, 0)
2655 12:40:52.488598 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2656 12:40:52.492050 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2657 12:40:52.492133
2658 12:40:52.498720 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2659 12:40:52.502033 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2660 12:40:52.505548 [Gating] SW calibration Done
2661 12:40:52.505630 ==
2662 12:40:52.508564 Dram Type= 6, Freq= 0, CH_0, rank 0
2663 12:40:52.511935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2664 12:40:52.512018 ==
2665 12:40:52.512083 RX Vref Scan: 0
2666 12:40:52.512144
2667 12:40:52.515238 RX Vref 0 -> 0, step: 1
2668 12:40:52.515337
2669 12:40:52.518634 RX Delay -40 -> 252, step: 8
2670 12:40:52.522047 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2671 12:40:52.525615 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2672 12:40:52.532057 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2673 12:40:52.535446 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2674 12:40:52.538527 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2675 12:40:52.541870 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2676 12:40:52.545393 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2677 12:40:52.551664 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2678 12:40:52.555038 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2679 12:40:52.558341 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2680 12:40:52.561752 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2681 12:40:52.565135 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2682 12:40:52.571421 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2683 12:40:52.574914 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2684 12:40:52.578639 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2685 12:40:52.581985 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2686 12:40:52.582068 ==
2687 12:40:52.585324 Dram Type= 6, Freq= 0, CH_0, rank 0
2688 12:40:52.591475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2689 12:40:52.591558 ==
2690 12:40:52.591624 DQS Delay:
2691 12:40:52.591684 DQS0 = 0, DQS1 = 0
2692 12:40:52.595002 DQM Delay:
2693 12:40:52.595084 DQM0 = 119, DQM1 = 106
2694 12:40:52.597955 DQ Delay:
2695 12:40:52.601148 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2696 12:40:52.604563 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2697 12:40:52.607866 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2698 12:40:52.611168 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2699 12:40:52.611250
2700 12:40:52.611316
2701 12:40:52.611376 ==
2702 12:40:52.614329 Dram Type= 6, Freq= 0, CH_0, rank 0
2703 12:40:52.617869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2704 12:40:52.621263 ==
2705 12:40:52.621345
2706 12:40:52.621410
2707 12:40:52.621470 TX Vref Scan disable
2708 12:40:52.624321 == TX Byte 0 ==
2709 12:40:52.627778 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2710 12:40:52.631511 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2711 12:40:52.634358 == TX Byte 1 ==
2712 12:40:52.637848 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2713 12:40:52.641231 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2714 12:40:52.641313 ==
2715 12:40:52.644485 Dram Type= 6, Freq= 0, CH_0, rank 0
2716 12:40:52.650958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2717 12:40:52.651066 ==
2718 12:40:52.662181 TX Vref=22, minBit 5, minWin=25, winSum=412
2719 12:40:52.665640 TX Vref=24, minBit 7, minWin=25, winSum=417
2720 12:40:52.668511 TX Vref=26, minBit 1, minWin=26, winSum=422
2721 12:40:52.672054 TX Vref=28, minBit 1, minWin=26, winSum=427
2722 12:40:52.675403 TX Vref=30, minBit 4, minWin=26, winSum=428
2723 12:40:52.681706 TX Vref=32, minBit 4, minWin=26, winSum=428
2724 12:40:52.684995 [TxChooseVref] Worse bit 4, Min win 26, Win sum 428, Final Vref 30
2725 12:40:52.685079
2726 12:40:52.688468 Final TX Range 1 Vref 30
2727 12:40:52.688600
2728 12:40:52.688665 ==
2729 12:40:52.691882 Dram Type= 6, Freq= 0, CH_0, rank 0
2730 12:40:52.695336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2731 12:40:52.698571 ==
2732 12:40:52.698652
2733 12:40:52.698717
2734 12:40:52.698777 TX Vref Scan disable
2735 12:40:52.701970 == TX Byte 0 ==
2736 12:40:52.704971 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2737 12:40:52.712228 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2738 12:40:52.712310 == TX Byte 1 ==
2739 12:40:52.714945 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2740 12:40:52.721969 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2741 12:40:52.722052
2742 12:40:52.722116 [DATLAT]
2743 12:40:52.722176 Freq=1200, CH0 RK0
2744 12:40:52.722234
2745 12:40:52.724884 DATLAT Default: 0xd
2746 12:40:52.728206 0, 0xFFFF, sum = 0
2747 12:40:52.728315 1, 0xFFFF, sum = 0
2748 12:40:52.731452 2, 0xFFFF, sum = 0
2749 12:40:52.731541 3, 0xFFFF, sum = 0
2750 12:40:52.734965 4, 0xFFFF, sum = 0
2751 12:40:52.735051 5, 0xFFFF, sum = 0
2752 12:40:52.738487 6, 0xFFFF, sum = 0
2753 12:40:52.738560 7, 0xFFFF, sum = 0
2754 12:40:52.741446 8, 0xFFFF, sum = 0
2755 12:40:52.741530 9, 0xFFFF, sum = 0
2756 12:40:52.744992 10, 0xFFFF, sum = 0
2757 12:40:52.745076 11, 0xFFFF, sum = 0
2758 12:40:52.748090 12, 0x0, sum = 1
2759 12:40:52.748174 13, 0x0, sum = 2
2760 12:40:52.751675 14, 0x0, sum = 3
2761 12:40:52.751760 15, 0x0, sum = 4
2762 12:40:52.754966 best_step = 13
2763 12:40:52.755050
2764 12:40:52.755116 ==
2765 12:40:52.758209 Dram Type= 6, Freq= 0, CH_0, rank 0
2766 12:40:52.761640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2767 12:40:52.761724 ==
2768 12:40:52.764800 RX Vref Scan: 1
2769 12:40:52.764883
2770 12:40:52.764950 Set Vref Range= 32 -> 127
2771 12:40:52.765012
2772 12:40:52.768284 RX Vref 32 -> 127, step: 1
2773 12:40:52.768354
2774 12:40:52.771070 RX Delay -21 -> 252, step: 4
2775 12:40:52.771168
2776 12:40:52.774561 Set Vref, RX VrefLevel [Byte0]: 32
2777 12:40:52.778113 [Byte1]: 32
2778 12:40:52.778194
2779 12:40:52.780975 Set Vref, RX VrefLevel [Byte0]: 33
2780 12:40:52.784365 [Byte1]: 33
2781 12:40:52.788217
2782 12:40:52.788320 Set Vref, RX VrefLevel [Byte0]: 34
2783 12:40:52.791770 [Byte1]: 34
2784 12:40:52.796460
2785 12:40:52.796572 Set Vref, RX VrefLevel [Byte0]: 35
2786 12:40:52.799774 [Byte1]: 35
2787 12:40:52.804379
2788 12:40:52.804456 Set Vref, RX VrefLevel [Byte0]: 36
2789 12:40:52.807702 [Byte1]: 36
2790 12:40:52.812210
2791 12:40:52.812288 Set Vref, RX VrefLevel [Byte0]: 37
2792 12:40:52.815469 [Byte1]: 37
2793 12:40:52.820107
2794 12:40:52.820210 Set Vref, RX VrefLevel [Byte0]: 38
2795 12:40:52.823435 [Byte1]: 38
2796 12:40:52.828442
2797 12:40:52.828575 Set Vref, RX VrefLevel [Byte0]: 39
2798 12:40:52.831661 [Byte1]: 39
2799 12:40:52.835745
2800 12:40:52.835821 Set Vref, RX VrefLevel [Byte0]: 40
2801 12:40:52.839359 [Byte1]: 40
2802 12:40:52.843862
2803 12:40:52.843937 Set Vref, RX VrefLevel [Byte0]: 41
2804 12:40:52.847334 [Byte1]: 41
2805 12:40:52.851814
2806 12:40:52.851891 Set Vref, RX VrefLevel [Byte0]: 42
2807 12:40:52.854946 [Byte1]: 42
2808 12:40:52.860196
2809 12:40:52.860270 Set Vref, RX VrefLevel [Byte0]: 43
2810 12:40:52.863461 [Byte1]: 43
2811 12:40:52.867923
2812 12:40:52.867996 Set Vref, RX VrefLevel [Byte0]: 44
2813 12:40:52.870802 [Byte1]: 44
2814 12:40:52.875407
2815 12:40:52.875481 Set Vref, RX VrefLevel [Byte0]: 45
2816 12:40:52.878805 [Byte1]: 45
2817 12:40:52.883438
2818 12:40:52.883509 Set Vref, RX VrefLevel [Byte0]: 46
2819 12:40:52.886824 [Byte1]: 46
2820 12:40:52.891343
2821 12:40:52.891416 Set Vref, RX VrefLevel [Byte0]: 47
2822 12:40:52.894527 [Byte1]: 47
2823 12:40:52.899226
2824 12:40:52.899298 Set Vref, RX VrefLevel [Byte0]: 48
2825 12:40:52.902745 [Byte1]: 48
2826 12:40:52.907268
2827 12:40:52.907337 Set Vref, RX VrefLevel [Byte0]: 49
2828 12:40:52.910650 [Byte1]: 49
2829 12:40:52.914990
2830 12:40:52.918394 Set Vref, RX VrefLevel [Byte0]: 50
2831 12:40:52.921462 [Byte1]: 50
2832 12:40:52.921553
2833 12:40:52.924979 Set Vref, RX VrefLevel [Byte0]: 51
2834 12:40:52.928352 [Byte1]: 51
2835 12:40:52.928477
2836 12:40:52.931542 Set Vref, RX VrefLevel [Byte0]: 52
2837 12:40:52.934711 [Byte1]: 52
2838 12:40:52.939055
2839 12:40:52.939126 Set Vref, RX VrefLevel [Byte0]: 53
2840 12:40:52.942373 [Byte1]: 53
2841 12:40:52.947011
2842 12:40:52.947083 Set Vref, RX VrefLevel [Byte0]: 54
2843 12:40:52.950446 [Byte1]: 54
2844 12:40:52.955031
2845 12:40:52.955114 Set Vref, RX VrefLevel [Byte0]: 55
2846 12:40:52.958017 [Byte1]: 55
2847 12:40:52.962720
2848 12:40:52.962792 Set Vref, RX VrefLevel [Byte0]: 56
2849 12:40:52.965820 [Byte1]: 56
2850 12:40:52.970905
2851 12:40:52.970978 Set Vref, RX VrefLevel [Byte0]: 57
2852 12:40:52.973942 [Byte1]: 57
2853 12:40:52.978791
2854 12:40:52.978863 Set Vref, RX VrefLevel [Byte0]: 58
2855 12:40:52.985295 [Byte1]: 58
2856 12:40:52.985369
2857 12:40:52.988711 Set Vref, RX VrefLevel [Byte0]: 59
2858 12:40:52.991483 [Byte1]: 59
2859 12:40:52.991556
2860 12:40:52.994974 Set Vref, RX VrefLevel [Byte0]: 60
2861 12:40:52.998168 [Byte1]: 60
2862 12:40:53.002719
2863 12:40:53.002797 Set Vref, RX VrefLevel [Byte0]: 61
2864 12:40:53.006053 [Byte1]: 61
2865 12:40:53.010478
2866 12:40:53.010579 Set Vref, RX VrefLevel [Byte0]: 62
2867 12:40:53.013619 [Byte1]: 62
2868 12:40:53.018329
2869 12:40:53.018400 Set Vref, RX VrefLevel [Byte0]: 63
2870 12:40:53.021410 [Byte1]: 63
2871 12:40:53.025890
2872 12:40:53.025964 Set Vref, RX VrefLevel [Byte0]: 64
2873 12:40:53.029264 [Byte1]: 64
2874 12:40:53.033822
2875 12:40:53.033898 Set Vref, RX VrefLevel [Byte0]: 65
2876 12:40:53.037634 [Byte1]: 65
2877 12:40:53.041882
2878 12:40:53.041990 Set Vref, RX VrefLevel [Byte0]: 66
2879 12:40:53.045220 [Byte1]: 66
2880 12:40:53.049949
2881 12:40:53.050034 Set Vref, RX VrefLevel [Byte0]: 67
2882 12:40:53.053434 [Byte1]: 67
2883 12:40:53.057922
2884 12:40:53.058059 Set Vref, RX VrefLevel [Byte0]: 68
2885 12:40:53.060938 [Byte1]: 68
2886 12:40:53.066111
2887 12:40:53.066195 Set Vref, RX VrefLevel [Byte0]: 69
2888 12:40:53.069233 [Byte1]: 69
2889 12:40:53.073547
2890 12:40:53.073655 Set Vref, RX VrefLevel [Byte0]: 70
2891 12:40:53.076756 [Byte1]: 70
2892 12:40:53.081385
2893 12:40:53.081469 Set Vref, RX VrefLevel [Byte0]: 71
2894 12:40:53.084845 [Byte1]: 71
2895 12:40:53.089504
2896 12:40:53.089604 Set Vref, RX VrefLevel [Byte0]: 72
2897 12:40:53.092970 [Byte1]: 72
2898 12:40:53.097590
2899 12:40:53.097673 Set Vref, RX VrefLevel [Byte0]: 73
2900 12:40:53.100858 [Byte1]: 73
2901 12:40:53.105922
2902 12:40:53.106015 Set Vref, RX VrefLevel [Byte0]: 74
2903 12:40:53.108794 [Byte1]: 74
2904 12:40:53.113224
2905 12:40:53.113310 Set Vref, RX VrefLevel [Byte0]: 75
2906 12:40:53.116705 [Byte1]: 75
2907 12:40:53.121177
2908 12:40:53.121283 Set Vref, RX VrefLevel [Byte0]: 76
2909 12:40:53.124724 [Byte1]: 76
2910 12:40:53.129372
2911 12:40:53.129480 Set Vref, RX VrefLevel [Byte0]: 77
2912 12:40:53.132572 [Byte1]: 77
2913 12:40:53.137041
2914 12:40:53.137187 Set Vref, RX VrefLevel [Byte0]: 78
2915 12:40:53.140282 [Byte1]: 78
2916 12:40:53.145252
2917 12:40:53.145386 Final RX Vref Byte 0 = 59 to rank0
2918 12:40:53.148435 Final RX Vref Byte 1 = 49 to rank0
2919 12:40:53.151584 Final RX Vref Byte 0 = 59 to rank1
2920 12:40:53.155068 Final RX Vref Byte 1 = 49 to rank1==
2921 12:40:53.158751 Dram Type= 6, Freq= 0, CH_0, rank 0
2922 12:40:53.164767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2923 12:40:53.164865 ==
2924 12:40:53.164931 DQS Delay:
2925 12:40:53.164990 DQS0 = 0, DQS1 = 0
2926 12:40:53.168489 DQM Delay:
2927 12:40:53.168601 DQM0 = 119, DQM1 = 106
2928 12:40:53.171644 DQ Delay:
2929 12:40:53.174865 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2930 12:40:53.178569 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
2931 12:40:53.181316 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =100
2932 12:40:53.185101 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =116
2933 12:40:53.185186
2934 12:40:53.185283
2935 12:40:53.191446 [DQSOSCAuto] RK0, (LSB)MR18= 0xffb, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 404 ps
2936 12:40:53.194940 CH0 RK0: MR19=403, MR18=FFB
2937 12:40:53.201401 CH0_RK0: MR19=0x403, MR18=0xFFB, DQSOSC=404, MR23=63, INC=40, DEC=26
2938 12:40:53.201487
2939 12:40:53.204674 ----->DramcWriteLeveling(PI) begin...
2940 12:40:53.204759 ==
2941 12:40:53.207842 Dram Type= 6, Freq= 0, CH_0, rank 1
2942 12:40:53.211310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2943 12:40:53.214725 ==
2944 12:40:53.214809 Write leveling (Byte 0): 32 => 32
2945 12:40:53.218030 Write leveling (Byte 1): 30 => 30
2946 12:40:53.221585 DramcWriteLeveling(PI) end<-----
2947 12:40:53.221670
2948 12:40:53.221736 ==
2949 12:40:53.225011 Dram Type= 6, Freq= 0, CH_0, rank 1
2950 12:40:53.231103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2951 12:40:53.231188 ==
2952 12:40:53.231256 [Gating] SW mode calibration
2953 12:40:53.241485 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2954 12:40:53.244857 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2955 12:40:53.251579 0 15 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 1)
2956 12:40:53.254421 0 15 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2957 12:40:53.257749 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2958 12:40:53.261207 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2959 12:40:53.268125 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2960 12:40:53.271239 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2961 12:40:53.274568 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2962 12:40:53.280945 0 15 28 | B1->B0 | 3434 3131 | 1 0 | (1 1) (1 0)
2963 12:40:53.284791 1 0 0 | B1->B0 | 2c2c 2424 | 0 0 | (1 0) (0 0)
2964 12:40:53.288026 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2965 12:40:53.294287 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2966 12:40:53.297661 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2967 12:40:53.301119 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2968 12:40:53.307801 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2969 12:40:53.311302 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2970 12:40:53.314672 1 0 28 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2971 12:40:53.320865 1 1 0 | B1->B0 | 3333 4646 | 0 0 | (1 1) (0 0)
2972 12:40:53.324142 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2973 12:40:53.327718 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2974 12:40:53.333918 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2975 12:40:53.337298 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2976 12:40:53.340667 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2977 12:40:53.347280 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2978 12:40:53.350629 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2979 12:40:53.353945 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2980 12:40:53.360638 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 12:40:53.363884 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 12:40:53.367572 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2983 12:40:53.373689 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2984 12:40:53.377515 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 12:40:53.380991 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 12:40:53.387653 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 12:40:53.390413 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 12:40:53.393819 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2989 12:40:53.400681 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2990 12:40:53.404190 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2991 12:40:53.407170 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2992 12:40:53.413688 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2993 12:40:53.416881 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2994 12:40:53.420362 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2995 12:40:53.427090 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2996 12:40:53.427179 Total UI for P1: 0, mck2ui 16
2997 12:40:53.430240 best dqsien dly found for B0: ( 1, 3, 26)
2998 12:40:53.433738 Total UI for P1: 0, mck2ui 16
2999 12:40:53.437234 best dqsien dly found for B1: ( 1, 3, 30)
3000 12:40:53.440592 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3001 12:40:53.446976 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3002 12:40:53.447059
3003 12:40:53.450078 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3004 12:40:53.453685 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3005 12:40:53.456412 [Gating] SW calibration Done
3006 12:40:53.456570 ==
3007 12:40:53.459891 Dram Type= 6, Freq= 0, CH_0, rank 1
3008 12:40:53.463214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3009 12:40:53.463298 ==
3010 12:40:53.466587 RX Vref Scan: 0
3011 12:40:53.466670
3012 12:40:53.466736 RX Vref 0 -> 0, step: 1
3013 12:40:53.466799
3014 12:40:53.469969 RX Delay -40 -> 252, step: 8
3015 12:40:53.473481 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
3016 12:40:53.480014 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3017 12:40:53.483408 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3018 12:40:53.486786 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3019 12:40:53.490115 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3020 12:40:53.493429 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3021 12:40:53.496722 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3022 12:40:53.503135 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3023 12:40:53.506641 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3024 12:40:53.509917 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3025 12:40:53.513287 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3026 12:40:53.516710 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3027 12:40:53.523212 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3028 12:40:53.526592 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3029 12:40:53.529847 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3030 12:40:53.532810 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3031 12:40:53.532882 ==
3032 12:40:53.536286 Dram Type= 6, Freq= 0, CH_0, rank 1
3033 12:40:53.542974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3034 12:40:53.543050 ==
3035 12:40:53.543115 DQS Delay:
3036 12:40:53.546597 DQS0 = 0, DQS1 = 0
3037 12:40:53.546669 DQM Delay:
3038 12:40:53.549559 DQM0 = 117, DQM1 = 108
3039 12:40:53.549630 DQ Delay:
3040 12:40:53.552971 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
3041 12:40:53.556161 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
3042 12:40:53.559488 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3043 12:40:53.562875 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
3044 12:40:53.562946
3045 12:40:53.563024
3046 12:40:53.563086 ==
3047 12:40:53.566218 Dram Type= 6, Freq= 0, CH_0, rank 1
3048 12:40:53.572851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3049 12:40:53.572924 ==
3050 12:40:53.572986
3051 12:40:53.573047
3052 12:40:53.573103 TX Vref Scan disable
3053 12:40:53.576311 == TX Byte 0 ==
3054 12:40:53.579585 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3055 12:40:53.582756 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3056 12:40:53.586037 == TX Byte 1 ==
3057 12:40:53.589444 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3058 12:40:53.592829 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3059 12:40:53.596240 ==
3060 12:40:53.599494 Dram Type= 6, Freq= 0, CH_0, rank 1
3061 12:40:53.602698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3062 12:40:53.602786 ==
3063 12:40:53.613913 TX Vref=22, minBit 1, minWin=25, winSum=418
3064 12:40:53.617220 TX Vref=24, minBit 1, minWin=26, winSum=424
3065 12:40:53.620546 TX Vref=26, minBit 1, minWin=26, winSum=431
3066 12:40:53.624097 TX Vref=28, minBit 13, minWin=26, winSum=435
3067 12:40:53.627529 TX Vref=30, minBit 5, minWin=26, winSum=434
3068 12:40:53.634414 TX Vref=32, minBit 11, minWin=26, winSum=431
3069 12:40:53.637292 [TxChooseVref] Worse bit 13, Min win 26, Win sum 435, Final Vref 28
3070 12:40:53.637378
3071 12:40:53.640736 Final TX Range 1 Vref 28
3072 12:40:53.640820
3073 12:40:53.640885 ==
3074 12:40:53.643924 Dram Type= 6, Freq= 0, CH_0, rank 1
3075 12:40:53.647421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3076 12:40:53.650721 ==
3077 12:40:53.650806
3078 12:40:53.650871
3079 12:40:53.650936 TX Vref Scan disable
3080 12:40:53.654100 == TX Byte 0 ==
3081 12:40:53.657252 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3082 12:40:53.663803 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3083 12:40:53.663887 == TX Byte 1 ==
3084 12:40:53.666849 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3085 12:40:53.674024 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3086 12:40:53.674108
3087 12:40:53.674173 [DATLAT]
3088 12:40:53.674234 Freq=1200, CH0 RK1
3089 12:40:53.674295
3090 12:40:53.676936 DATLAT Default: 0xd
3091 12:40:53.677018 0, 0xFFFF, sum = 0
3092 12:40:53.680387 1, 0xFFFF, sum = 0
3093 12:40:53.683831 2, 0xFFFF, sum = 0
3094 12:40:53.683915 3, 0xFFFF, sum = 0
3095 12:40:53.687246 4, 0xFFFF, sum = 0
3096 12:40:53.687330 5, 0xFFFF, sum = 0
3097 12:40:53.690525 6, 0xFFFF, sum = 0
3098 12:40:53.690609 7, 0xFFFF, sum = 0
3099 12:40:53.693860 8, 0xFFFF, sum = 0
3100 12:40:53.693944 9, 0xFFFF, sum = 0
3101 12:40:53.697162 10, 0xFFFF, sum = 0
3102 12:40:53.697246 11, 0xFFFF, sum = 0
3103 12:40:53.700041 12, 0x0, sum = 1
3104 12:40:53.700124 13, 0x0, sum = 2
3105 12:40:53.703360 14, 0x0, sum = 3
3106 12:40:53.703444 15, 0x0, sum = 4
3107 12:40:53.706700 best_step = 13
3108 12:40:53.706783
3109 12:40:53.706849 ==
3110 12:40:53.710196 Dram Type= 6, Freq= 0, CH_0, rank 1
3111 12:40:53.713699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3112 12:40:53.713786 ==
3113 12:40:53.713853 RX Vref Scan: 0
3114 12:40:53.716673
3115 12:40:53.716755 RX Vref 0 -> 0, step: 1
3116 12:40:53.716821
3117 12:40:53.720005 RX Delay -21 -> 252, step: 4
3118 12:40:53.726811 iDelay=199, Bit 0, Center 112 (47 ~ 178) 132
3119 12:40:53.729962 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3120 12:40:53.733571 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3121 12:40:53.736435 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3122 12:40:53.739886 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3123 12:40:53.746677 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3124 12:40:53.750145 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3125 12:40:53.753358 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3126 12:40:53.756500 iDelay=199, Bit 8, Center 96 (27 ~ 166) 140
3127 12:40:53.760059 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3128 12:40:53.763108 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3129 12:40:53.770047 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3130 12:40:53.773470 iDelay=199, Bit 12, Center 114 (47 ~ 182) 136
3131 12:40:53.776477 iDelay=199, Bit 13, Center 114 (47 ~ 182) 136
3132 12:40:53.780013 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3133 12:40:53.786455 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3134 12:40:53.786539 ==
3135 12:40:53.790130 Dram Type= 6, Freq= 0, CH_0, rank 1
3136 12:40:53.792949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3137 12:40:53.793038 ==
3138 12:40:53.793104 DQS Delay:
3139 12:40:53.796400 DQS0 = 0, DQS1 = 0
3140 12:40:53.796483 DQM Delay:
3141 12:40:53.799755 DQM0 = 116, DQM1 = 107
3142 12:40:53.799868 DQ Delay:
3143 12:40:53.803060 DQ0 =112, DQ1 =118, DQ2 =110, DQ3 =114
3144 12:40:53.806595 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3145 12:40:53.809836 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3146 12:40:53.813290 DQ12 =114, DQ13 =114, DQ14 =118, DQ15 =116
3147 12:40:53.813373
3148 12:40:53.813439
3149 12:40:53.823258 [DQSOSCAuto] RK1, (LSB)MR18= 0xfea, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 404 ps
3150 12:40:53.826055 CH0 RK1: MR19=403, MR18=FEA
3151 12:40:53.829642 CH0_RK1: MR19=0x403, MR18=0xFEA, DQSOSC=404, MR23=63, INC=40, DEC=26
3152 12:40:53.832781 [RxdqsGatingPostProcess] freq 1200
3153 12:40:53.839684 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3154 12:40:53.843055 best DQS0 dly(2T, 0.5T) = (0, 11)
3155 12:40:53.845859 best DQS1 dly(2T, 0.5T) = (0, 12)
3156 12:40:53.849409 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3157 12:40:53.852679 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3158 12:40:53.856337 best DQS0 dly(2T, 0.5T) = (0, 11)
3159 12:40:53.859339 best DQS1 dly(2T, 0.5T) = (0, 11)
3160 12:40:53.862743 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3161 12:40:53.866006 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3162 12:40:53.869171 Pre-setting of DQS Precalculation
3163 12:40:53.872553 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3164 12:40:53.872640 ==
3165 12:40:53.876314 Dram Type= 6, Freq= 0, CH_1, rank 0
3166 12:40:53.879129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3167 12:40:53.879213 ==
3168 12:40:53.885987 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3169 12:40:53.892784 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3170 12:40:53.900026 [CA 0] Center 37 (7~68) winsize 62
3171 12:40:53.903690 [CA 1] Center 38 (8~68) winsize 61
3172 12:40:53.906552 [CA 2] Center 34 (4~64) winsize 61
3173 12:40:53.909845 [CA 3] Center 33 (3~64) winsize 62
3174 12:40:53.913281 [CA 4] Center 34 (4~64) winsize 61
3175 12:40:53.916748 [CA 5] Center 33 (3~64) winsize 62
3176 12:40:53.916834
3177 12:40:53.920218 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3178 12:40:53.920300
3179 12:40:53.923049 [CATrainingPosCal] consider 1 rank data
3180 12:40:53.926483 u2DelayCellTimex100 = 270/100 ps
3181 12:40:53.929884 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3182 12:40:53.936585 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3183 12:40:53.940007 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3184 12:40:53.942930 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3185 12:40:53.946658 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3186 12:40:53.949587 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3187 12:40:53.949669
3188 12:40:53.953071 CA PerBit enable=1, Macro0, CA PI delay=33
3189 12:40:53.953158
3190 12:40:53.956394 [CBTSetCACLKResult] CA Dly = 33
3191 12:40:53.956477 CS Dly: 6 (0~37)
3192 12:40:53.959940 ==
3193 12:40:53.963352 Dram Type= 6, Freq= 0, CH_1, rank 1
3194 12:40:53.966328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3195 12:40:53.966411 ==
3196 12:40:53.969647 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3197 12:40:53.975965 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3198 12:40:53.985680 [CA 0] Center 37 (7~67) winsize 61
3199 12:40:53.989265 [CA 1] Center 38 (8~68) winsize 61
3200 12:40:53.992165 [CA 2] Center 34 (4~65) winsize 62
3201 12:40:53.995528 [CA 3] Center 33 (3~64) winsize 62
3202 12:40:53.998654 [CA 4] Center 34 (4~65) winsize 62
3203 12:40:54.002047 [CA 5] Center 33 (3~64) winsize 62
3204 12:40:54.002147
3205 12:40:54.005774 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3206 12:40:54.005857
3207 12:40:54.008959 [CATrainingPosCal] consider 2 rank data
3208 12:40:54.012046 u2DelayCellTimex100 = 270/100 ps
3209 12:40:54.015722 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3210 12:40:54.022363 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3211 12:40:54.025415 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3212 12:40:54.028932 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3213 12:40:54.031911 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3214 12:40:54.035395 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3215 12:40:54.035494
3216 12:40:54.038713 CA PerBit enable=1, Macro0, CA PI delay=33
3217 12:40:54.038798
3218 12:40:54.042202 [CBTSetCACLKResult] CA Dly = 33
3219 12:40:54.042286 CS Dly: 7 (0~40)
3220 12:40:54.045729
3221 12:40:54.049113 ----->DramcWriteLeveling(PI) begin...
3222 12:40:54.049198 ==
3223 12:40:54.052047 Dram Type= 6, Freq= 0, CH_1, rank 0
3224 12:40:54.055643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3225 12:40:54.055728 ==
3226 12:40:54.059163 Write leveling (Byte 0): 24 => 24
3227 12:40:54.062208 Write leveling (Byte 1): 27 => 27
3228 12:40:54.065567 DramcWriteLeveling(PI) end<-----
3229 12:40:54.065663
3230 12:40:54.065739 ==
3231 12:40:54.069152 Dram Type= 6, Freq= 0, CH_1, rank 0
3232 12:40:54.072026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3233 12:40:54.072140 ==
3234 12:40:54.075831 [Gating] SW mode calibration
3235 12:40:54.082384 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3236 12:40:54.088431 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3237 12:40:54.092097 0 15 0 | B1->B0 | 2f2f 3232 | 0 1 | (0 0) (1 1)
3238 12:40:54.095179 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3239 12:40:54.102008 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3240 12:40:54.105630 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3241 12:40:54.108689 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3242 12:40:54.115428 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3243 12:40:54.118862 0 15 24 | B1->B0 | 3434 2e2e | 1 1 | (1 0) (1 0)
3244 12:40:54.122110 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (1 0)
3245 12:40:54.128558 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3246 12:40:54.131761 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3247 12:40:54.135018 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3248 12:40:54.141855 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3249 12:40:54.145187 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3250 12:40:54.148214 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3251 12:40:54.154952 1 0 24 | B1->B0 | 2424 3333 | 0 1 | (0 0) (0 0)
3252 12:40:54.158789 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3253 12:40:54.162036 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3254 12:40:54.168489 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3255 12:40:54.171415 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3256 12:40:54.175053 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3257 12:40:54.181726 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3258 12:40:54.184682 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3259 12:40:54.188022 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3260 12:40:54.191657 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3261 12:40:54.198084 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3262 12:40:54.201575 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3263 12:40:54.204923 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3264 12:40:54.211698 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3265 12:40:54.215319 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3266 12:40:54.217894 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3267 12:40:54.224511 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3268 12:40:54.227939 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3269 12:40:54.231426 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3270 12:40:54.237864 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3271 12:40:54.241245 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3272 12:40:54.244742 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3273 12:40:54.251136 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3274 12:40:54.254756 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3275 12:40:54.257594 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3276 12:40:54.264374 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3277 12:40:54.267651 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3278 12:40:54.271011 Total UI for P1: 0, mck2ui 16
3279 12:40:54.274163 best dqsien dly found for B0: ( 1, 3, 26)
3280 12:40:54.277990 Total UI for P1: 0, mck2ui 16
3281 12:40:54.281108 best dqsien dly found for B1: ( 1, 3, 26)
3282 12:40:54.284427 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3283 12:40:54.287723 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3284 12:40:54.288155
3285 12:40:54.290742 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3286 12:40:54.294370 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3287 12:40:54.297289 [Gating] SW calibration Done
3288 12:40:54.297720 ==
3289 12:40:54.300997 Dram Type= 6, Freq= 0, CH_1, rank 0
3290 12:40:54.304239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3291 12:40:54.307802 ==
3292 12:40:54.308341 RX Vref Scan: 0
3293 12:40:54.308724
3294 12:40:54.310764 RX Vref 0 -> 0, step: 1
3295 12:40:54.311195
3296 12:40:54.314374 RX Delay -40 -> 252, step: 8
3297 12:40:54.317224 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3298 12:40:54.320673 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3299 12:40:54.324449 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3300 12:40:54.327409 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3301 12:40:54.334285 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3302 12:40:54.336843 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3303 12:40:54.340618 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3304 12:40:54.344107 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3305 12:40:54.347607 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3306 12:40:54.353584 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3307 12:40:54.357479 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3308 12:40:54.360263 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3309 12:40:54.363480 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3310 12:40:54.367471 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3311 12:40:54.373782 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3312 12:40:54.376876 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3313 12:40:54.377307 ==
3314 12:40:54.380646 Dram Type= 6, Freq= 0, CH_1, rank 0
3315 12:40:54.383462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3316 12:40:54.383897 ==
3317 12:40:54.387364 DQS Delay:
3318 12:40:54.387920 DQS0 = 0, DQS1 = 0
3319 12:40:54.388271 DQM Delay:
3320 12:40:54.390368 DQM0 = 117, DQM1 = 109
3321 12:40:54.390800 DQ Delay:
3322 12:40:54.393825 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3323 12:40:54.397164 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3324 12:40:54.400289 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3325 12:40:54.406790 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3326 12:40:54.407240
3327 12:40:54.407681
3328 12:40:54.408066 ==
3329 12:40:54.410172 Dram Type= 6, Freq= 0, CH_1, rank 0
3330 12:40:54.413533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3331 12:40:54.414037 ==
3332 12:40:54.414412
3333 12:40:54.414756
3334 12:40:54.416958 TX Vref Scan disable
3335 12:40:54.417386 == TX Byte 0 ==
3336 12:40:54.423612 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3337 12:40:54.426694 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3338 12:40:54.427166 == TX Byte 1 ==
3339 12:40:54.433640 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3340 12:40:54.437086 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3341 12:40:54.437512 ==
3342 12:40:54.439885 Dram Type= 6, Freq= 0, CH_1, rank 0
3343 12:40:54.443327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3344 12:40:54.443795 ==
3345 12:40:54.455955 TX Vref=22, minBit 9, minWin=25, winSum=419
3346 12:40:54.459442 TX Vref=24, minBit 9, minWin=25, winSum=421
3347 12:40:54.462661 TX Vref=26, minBit 9, minWin=25, winSum=428
3348 12:40:54.466019 TX Vref=28, minBit 10, minWin=25, winSum=435
3349 12:40:54.469408 TX Vref=30, minBit 11, minWin=25, winSum=431
3350 12:40:54.476001 TX Vref=32, minBit 9, minWin=26, winSum=432
3351 12:40:54.479346 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 32
3352 12:40:54.479834
3353 12:40:54.482536 Final TX Range 1 Vref 32
3354 12:40:54.482958
3355 12:40:54.483292 ==
3356 12:40:54.486061 Dram Type= 6, Freq= 0, CH_1, rank 0
3357 12:40:54.488935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3358 12:40:54.492165 ==
3359 12:40:54.492764
3360 12:40:54.493114
3361 12:40:54.493425 TX Vref Scan disable
3362 12:40:54.495786 == TX Byte 0 ==
3363 12:40:54.499005 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3364 12:40:54.505966 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3365 12:40:54.506382 == TX Byte 1 ==
3366 12:40:54.508998 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3367 12:40:54.515519 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3368 12:40:54.515937
3369 12:40:54.516264 [DATLAT]
3370 12:40:54.516502 Freq=1200, CH1 RK0
3371 12:40:54.516753
3372 12:40:54.518962 DATLAT Default: 0xd
3373 12:40:54.522404 0, 0xFFFF, sum = 0
3374 12:40:54.522704 1, 0xFFFF, sum = 0
3375 12:40:54.525670 2, 0xFFFF, sum = 0
3376 12:40:54.525981 3, 0xFFFF, sum = 0
3377 12:40:54.528597 4, 0xFFFF, sum = 0
3378 12:40:54.528894 5, 0xFFFF, sum = 0
3379 12:40:54.531950 6, 0xFFFF, sum = 0
3380 12:40:54.532249 7, 0xFFFF, sum = 0
3381 12:40:54.535325 8, 0xFFFF, sum = 0
3382 12:40:54.535637 9, 0xFFFF, sum = 0
3383 12:40:54.538597 10, 0xFFFF, sum = 0
3384 12:40:54.538895 11, 0xFFFF, sum = 0
3385 12:40:54.542094 12, 0x0, sum = 1
3386 12:40:54.542426 13, 0x0, sum = 2
3387 12:40:54.545562 14, 0x0, sum = 3
3388 12:40:54.545859 15, 0x0, sum = 4
3389 12:40:54.548924 best_step = 13
3390 12:40:54.549215
3391 12:40:54.549446 ==
3392 12:40:54.551855 Dram Type= 6, Freq= 0, CH_1, rank 0
3393 12:40:54.555352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3394 12:40:54.555767 ==
3395 12:40:54.558476 RX Vref Scan: 1
3396 12:40:54.558888
3397 12:40:54.559213 Set Vref Range= 32 -> 127
3398 12:40:54.559516
3399 12:40:54.562376 RX Vref 32 -> 127, step: 1
3400 12:40:54.562788
3401 12:40:54.565525 RX Delay -21 -> 252, step: 4
3402 12:40:54.565936
3403 12:40:54.568598 Set Vref, RX VrefLevel [Byte0]: 32
3404 12:40:54.571996 [Byte1]: 32
3405 12:40:54.572417
3406 12:40:54.575681 Set Vref, RX VrefLevel [Byte0]: 33
3407 12:40:54.578920 [Byte1]: 33
3408 12:40:54.582454
3409 12:40:54.582861 Set Vref, RX VrefLevel [Byte0]: 34
3410 12:40:54.585646 [Byte1]: 34
3411 12:40:54.590214
3412 12:40:54.590622 Set Vref, RX VrefLevel [Byte0]: 35
3413 12:40:54.593596 [Byte1]: 35
3414 12:40:54.598517
3415 12:40:54.598937 Set Vref, RX VrefLevel [Byte0]: 36
3416 12:40:54.601256 [Byte1]: 36
3417 12:40:54.606529
3418 12:40:54.606968 Set Vref, RX VrefLevel [Byte0]: 37
3419 12:40:54.609509 [Byte1]: 37
3420 12:40:54.614334
3421 12:40:54.614798 Set Vref, RX VrefLevel [Byte0]: 38
3422 12:40:54.617585 [Byte1]: 38
3423 12:40:54.622221
3424 12:40:54.622641 Set Vref, RX VrefLevel [Byte0]: 39
3425 12:40:54.625367 [Byte1]: 39
3426 12:40:54.629902
3427 12:40:54.630363 Set Vref, RX VrefLevel [Byte0]: 40
3428 12:40:54.633762 [Byte1]: 40
3429 12:40:54.637931
3430 12:40:54.638393 Set Vref, RX VrefLevel [Byte0]: 41
3431 12:40:54.640934 [Byte1]: 41
3432 12:40:54.645694
3433 12:40:54.646157 Set Vref, RX VrefLevel [Byte0]: 42
3434 12:40:54.649236 [Byte1]: 42
3435 12:40:54.653718
3436 12:40:54.654148 Set Vref, RX VrefLevel [Byte0]: 43
3437 12:40:54.657105 [Byte1]: 43
3438 12:40:54.662073
3439 12:40:54.662600 Set Vref, RX VrefLevel [Byte0]: 44
3440 12:40:54.664617 [Byte1]: 44
3441 12:40:54.669994
3442 12:40:54.670426 Set Vref, RX VrefLevel [Byte0]: 45
3443 12:40:54.672898 [Byte1]: 45
3444 12:40:54.677301
3445 12:40:54.677733 Set Vref, RX VrefLevel [Byte0]: 46
3446 12:40:54.680653 [Byte1]: 46
3447 12:40:54.685218
3448 12:40:54.685782 Set Vref, RX VrefLevel [Byte0]: 47
3449 12:40:54.688630 [Byte1]: 47
3450 12:40:54.693084
3451 12:40:54.693560 Set Vref, RX VrefLevel [Byte0]: 48
3452 12:40:54.696691 [Byte1]: 48
3453 12:40:54.700994
3454 12:40:54.704294 Set Vref, RX VrefLevel [Byte0]: 49
3455 12:40:54.707623 [Byte1]: 49
3456 12:40:54.708104
3457 12:40:54.710873 Set Vref, RX VrefLevel [Byte0]: 50
3458 12:40:54.714370 [Byte1]: 50
3459 12:40:54.714802
3460 12:40:54.717919 Set Vref, RX VrefLevel [Byte0]: 51
3461 12:40:54.721022 [Byte1]: 51
3462 12:40:54.725118
3463 12:40:54.725538 Set Vref, RX VrefLevel [Byte0]: 52
3464 12:40:54.728243 [Byte1]: 52
3465 12:40:54.732696
3466 12:40:54.733191 Set Vref, RX VrefLevel [Byte0]: 53
3467 12:40:54.736633 [Byte1]: 53
3468 12:40:54.741066
3469 12:40:54.741488 Set Vref, RX VrefLevel [Byte0]: 54
3470 12:40:54.744380 [Byte1]: 54
3471 12:40:54.748825
3472 12:40:54.749250 Set Vref, RX VrefLevel [Byte0]: 55
3473 12:40:54.752065 [Byte1]: 55
3474 12:40:54.756783
3475 12:40:54.757296 Set Vref, RX VrefLevel [Byte0]: 56
3476 12:40:54.760019 [Byte1]: 56
3477 12:40:54.764877
3478 12:40:54.765400 Set Vref, RX VrefLevel [Byte0]: 57
3479 12:40:54.767815 [Byte1]: 57
3480 12:40:54.772544
3481 12:40:54.772973 Set Vref, RX VrefLevel [Byte0]: 58
3482 12:40:54.775833 [Byte1]: 58
3483 12:40:54.780291
3484 12:40:54.780755 Set Vref, RX VrefLevel [Byte0]: 59
3485 12:40:54.783728 [Byte1]: 59
3486 12:40:54.788274
3487 12:40:54.788741 Set Vref, RX VrefLevel [Byte0]: 60
3488 12:40:54.791830 [Byte1]: 60
3489 12:40:54.796078
3490 12:40:54.796559 Set Vref, RX VrefLevel [Byte0]: 61
3491 12:40:54.799630 [Byte1]: 61
3492 12:40:54.804223
3493 12:40:54.804681 Set Vref, RX VrefLevel [Byte0]: 62
3494 12:40:54.807772 [Byte1]: 62
3495 12:40:54.812194
3496 12:40:54.812761 Set Vref, RX VrefLevel [Byte0]: 63
3497 12:40:54.815149 [Byte1]: 63
3498 12:40:54.820059
3499 12:40:54.820670 Set Vref, RX VrefLevel [Byte0]: 64
3500 12:40:54.823130 [Byte1]: 64
3501 12:40:54.827652
3502 12:40:54.828189 Set Vref, RX VrefLevel [Byte0]: 65
3503 12:40:54.831206 [Byte1]: 65
3504 12:40:54.835681
3505 12:40:54.836129 Set Vref, RX VrefLevel [Byte0]: 66
3506 12:40:54.838804 [Byte1]: 66
3507 12:40:54.844032
3508 12:40:54.844594 Set Vref, RX VrefLevel [Byte0]: 67
3509 12:40:54.847335 [Byte1]: 67
3510 12:40:54.851764
3511 12:40:54.852207 Set Vref, RX VrefLevel [Byte0]: 68
3512 12:40:54.854672 [Byte1]: 68
3513 12:40:54.859243
3514 12:40:54.859662 Set Vref, RX VrefLevel [Byte0]: 69
3515 12:40:54.862881 [Byte1]: 69
3516 12:40:54.867317
3517 12:40:54.867737 Final RX Vref Byte 0 = 52 to rank0
3518 12:40:54.870761 Final RX Vref Byte 1 = 54 to rank0
3519 12:40:54.874088 Final RX Vref Byte 0 = 52 to rank1
3520 12:40:54.877326 Final RX Vref Byte 1 = 54 to rank1==
3521 12:40:54.880440 Dram Type= 6, Freq= 0, CH_1, rank 0
3522 12:40:54.887368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3523 12:40:54.887911 ==
3524 12:40:54.888360 DQS Delay:
3525 12:40:54.888873 DQS0 = 0, DQS1 = 0
3526 12:40:54.890444 DQM Delay:
3527 12:40:54.890865 DQM0 = 116, DQM1 = 110
3528 12:40:54.894092 DQ Delay:
3529 12:40:54.897302 DQ0 =120, DQ1 =112, DQ2 =110, DQ3 =114
3530 12:40:54.900229 DQ4 =114, DQ5 =128, DQ6 =124, DQ7 =112
3531 12:40:54.903644 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =98
3532 12:40:54.907137 DQ12 =118, DQ13 =118, DQ14 =120, DQ15 =118
3533 12:40:54.907581
3534 12:40:54.907913
3535 12:40:54.916852 [DQSOSCAuto] RK0, (LSB)MR18= 0x5f8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 408 ps
3536 12:40:54.917303 CH1 RK0: MR19=403, MR18=5F8
3537 12:40:54.923882 CH1_RK0: MR19=0x403, MR18=0x5F8, DQSOSC=408, MR23=63, INC=39, DEC=26
3538 12:40:54.924398
3539 12:40:54.926702 ----->DramcWriteLeveling(PI) begin...
3540 12:40:54.927155 ==
3541 12:40:54.930193 Dram Type= 6, Freq= 0, CH_1, rank 1
3542 12:40:54.936726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3543 12:40:54.937157 ==
3544 12:40:54.939888 Write leveling (Byte 0): 25 => 25
3545 12:40:54.940315 Write leveling (Byte 1): 27 => 27
3546 12:40:54.943768 DramcWriteLeveling(PI) end<-----
3547 12:40:54.944196
3548 12:40:54.944570 ==
3549 12:40:54.946396 Dram Type= 6, Freq= 0, CH_1, rank 1
3550 12:40:54.953419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3551 12:40:54.953847 ==
3552 12:40:54.956490 [Gating] SW mode calibration
3553 12:40:54.963734 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3554 12:40:54.968247 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3555 12:40:54.973073 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3556 12:40:54.976422 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3557 12:40:54.979895 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3558 12:40:54.986823 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3559 12:40:54.989969 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3560 12:40:54.993202 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3561 12:40:54.999654 0 15 24 | B1->B0 | 2c2c 3434 | 1 1 | (1 0) (1 0)
3562 12:40:55.003130 0 15 28 | B1->B0 | 2323 2727 | 0 1 | (1 0) (1 0)
3563 12:40:55.006447 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3564 12:40:55.012876 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3565 12:40:55.015820 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3566 12:40:55.019583 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3567 12:40:55.025905 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3568 12:40:55.029332 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3569 12:40:55.032998 1 0 24 | B1->B0 | 3131 2525 | 1 0 | (0 0) (0 0)
3570 12:40:55.039586 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3571 12:40:55.042360 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3572 12:40:55.045616 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3573 12:40:55.052165 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3574 12:40:55.055952 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3575 12:40:55.058954 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3576 12:40:55.065660 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3577 12:40:55.068914 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3578 12:40:55.072553 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3579 12:40:55.079333 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3580 12:40:55.082010 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3581 12:40:55.085910 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3582 12:40:55.091964 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3583 12:40:55.095322 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3584 12:40:55.098593 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3585 12:40:55.105140 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3586 12:40:55.108862 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3587 12:40:55.111727 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3588 12:40:55.118672 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3589 12:40:55.121754 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3590 12:40:55.125315 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3591 12:40:55.131750 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3592 12:40:55.135066 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3593 12:40:55.138381 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3594 12:40:55.141676 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3595 12:40:55.148379 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3596 12:40:55.151842 Total UI for P1: 0, mck2ui 16
3597 12:40:55.155133 best dqsien dly found for B0: ( 1, 3, 26)
3598 12:40:55.158254 Total UI for P1: 0, mck2ui 16
3599 12:40:55.161538 best dqsien dly found for B1: ( 1, 3, 26)
3600 12:40:55.165035 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3601 12:40:55.167982 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3602 12:40:55.168407
3603 12:40:55.171244 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3604 12:40:55.174481 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3605 12:40:55.177824 [Gating] SW calibration Done
3606 12:40:55.178245 ==
3607 12:40:55.181334 Dram Type= 6, Freq= 0, CH_1, rank 1
3608 12:40:55.184845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3609 12:40:55.185271 ==
3610 12:40:55.188651 RX Vref Scan: 0
3611 12:40:55.189164
3612 12:40:55.191536 RX Vref 0 -> 0, step: 1
3613 12:40:55.191980
3614 12:40:55.192323 RX Delay -40 -> 252, step: 8
3615 12:40:55.197710 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3616 12:40:55.201029 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3617 12:40:55.204418 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3618 12:40:55.207975 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3619 12:40:55.214028 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3620 12:40:55.217476 iDelay=208, Bit 5, Center 127 (56 ~ 199) 144
3621 12:40:55.220875 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3622 12:40:55.224072 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3623 12:40:55.227250 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3624 12:40:55.230842 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3625 12:40:55.237065 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3626 12:40:55.240414 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3627 12:40:55.244021 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3628 12:40:55.247407 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3629 12:40:55.254180 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3630 12:40:55.256908 iDelay=208, Bit 15, Center 115 (40 ~ 191) 152
3631 12:40:55.257334 ==
3632 12:40:55.260360 Dram Type= 6, Freq= 0, CH_1, rank 1
3633 12:40:55.263525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3634 12:40:55.263980 ==
3635 12:40:55.267353 DQS Delay:
3636 12:40:55.267780 DQS0 = 0, DQS1 = 0
3637 12:40:55.268125 DQM Delay:
3638 12:40:55.270118 DQM0 = 117, DQM1 = 109
3639 12:40:55.270548 DQ Delay:
3640 12:40:55.273574 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3641 12:40:55.276777 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =115
3642 12:40:55.280254 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3643 12:40:55.286478 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =115
3644 12:40:55.287001
3645 12:40:55.287346
3646 12:40:55.287663 ==
3647 12:40:55.289964 Dram Type= 6, Freq= 0, CH_1, rank 1
3648 12:40:55.293431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3649 12:40:55.293868 ==
3650 12:40:55.294213
3651 12:40:55.294530
3652 12:40:55.296698 TX Vref Scan disable
3653 12:40:55.297127 == TX Byte 0 ==
3654 12:40:55.303322 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3655 12:40:55.306198 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3656 12:40:55.306633 == TX Byte 1 ==
3657 12:40:55.313096 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3658 12:40:55.316229 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3659 12:40:55.316695 ==
3660 12:40:55.319555 Dram Type= 6, Freq= 0, CH_1, rank 1
3661 12:40:55.323156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3662 12:40:55.323683 ==
3663 12:40:55.335860 TX Vref=22, minBit 9, minWin=25, winSum=423
3664 12:40:55.339093 TX Vref=24, minBit 9, minWin=26, winSum=432
3665 12:40:55.342833 TX Vref=26, minBit 13, minWin=26, winSum=437
3666 12:40:55.345762 TX Vref=28, minBit 9, minWin=26, winSum=436
3667 12:40:55.349294 TX Vref=30, minBit 9, minWin=26, winSum=436
3668 12:40:55.355999 TX Vref=32, minBit 9, minWin=26, winSum=433
3669 12:40:55.358773 [TxChooseVref] Worse bit 13, Min win 26, Win sum 437, Final Vref 26
3670 12:40:55.359209
3671 12:40:55.362638 Final TX Range 1 Vref 26
3672 12:40:55.363072
3673 12:40:55.363412 ==
3674 12:40:55.366108 Dram Type= 6, Freq= 0, CH_1, rank 1
3675 12:40:55.368953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3676 12:40:55.372262 ==
3677 12:40:55.372737
3678 12:40:55.373084
3679 12:40:55.373403 TX Vref Scan disable
3680 12:40:55.375694 == TX Byte 0 ==
3681 12:40:55.378965 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3682 12:40:55.385678 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3683 12:40:55.386124 == TX Byte 1 ==
3684 12:40:55.388998 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3685 12:40:55.395286 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3686 12:40:55.395860
3687 12:40:55.396257 [DATLAT]
3688 12:40:55.396671 Freq=1200, CH1 RK1
3689 12:40:55.397000
3690 12:40:55.398735 DATLAT Default: 0xd
3691 12:40:55.402293 0, 0xFFFF, sum = 0
3692 12:40:55.402858 1, 0xFFFF, sum = 0
3693 12:40:55.405235 2, 0xFFFF, sum = 0
3694 12:40:55.405759 3, 0xFFFF, sum = 0
3695 12:40:55.408988 4, 0xFFFF, sum = 0
3696 12:40:55.409604 5, 0xFFFF, sum = 0
3697 12:40:55.411992 6, 0xFFFF, sum = 0
3698 12:40:55.412439 7, 0xFFFF, sum = 0
3699 12:40:55.415455 8, 0xFFFF, sum = 0
3700 12:40:55.416064 9, 0xFFFF, sum = 0
3701 12:40:55.419003 10, 0xFFFF, sum = 0
3702 12:40:55.419617 11, 0xFFFF, sum = 0
3703 12:40:55.421694 12, 0x0, sum = 1
3704 12:40:55.422255 13, 0x0, sum = 2
3705 12:40:55.425368 14, 0x0, sum = 3
3706 12:40:55.425797 15, 0x0, sum = 4
3707 12:40:55.428410 best_step = 13
3708 12:40:55.428871
3709 12:40:55.429204 ==
3710 12:40:55.431840 Dram Type= 6, Freq= 0, CH_1, rank 1
3711 12:40:55.435321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3712 12:40:55.435749 ==
3713 12:40:55.438310 RX Vref Scan: 0
3714 12:40:55.438789
3715 12:40:55.439165 RX Vref 0 -> 0, step: 1
3716 12:40:55.439483
3717 12:40:55.441966 RX Delay -21 -> 252, step: 4
3718 12:40:55.448495 iDelay=199, Bit 0, Center 120 (51 ~ 190) 140
3719 12:40:55.452072 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3720 12:40:55.454975 iDelay=199, Bit 2, Center 110 (47 ~ 174) 128
3721 12:40:55.458091 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3722 12:40:55.461475 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3723 12:40:55.468190 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3724 12:40:55.472026 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3725 12:40:55.474803 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3726 12:40:55.477815 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3727 12:40:55.481752 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3728 12:40:55.488171 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3729 12:40:55.491116 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3730 12:40:55.494530 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3731 12:40:55.497778 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3732 12:40:55.504323 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3733 12:40:55.507661 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3734 12:40:55.508239 ==
3735 12:40:55.510985 Dram Type= 6, Freq= 0, CH_1, rank 1
3736 12:40:55.514400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3737 12:40:55.514826 ==
3738 12:40:55.515163 DQS Delay:
3739 12:40:55.517816 DQS0 = 0, DQS1 = 0
3740 12:40:55.518238 DQM Delay:
3741 12:40:55.521184 DQM0 = 117, DQM1 = 110
3742 12:40:55.521605 DQ Delay:
3743 12:40:55.524097 DQ0 =120, DQ1 =112, DQ2 =110, DQ3 =112
3744 12:40:55.527311 DQ4 =116, DQ5 =126, DQ6 =130, DQ7 =116
3745 12:40:55.530707 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =100
3746 12:40:55.537309 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =120
3747 12:40:55.537850
3748 12:40:55.538198
3749 12:40:55.543813 [DQSOSCAuto] RK1, (LSB)MR18= 0xf5f0, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
3750 12:40:55.547306 CH1 RK1: MR19=303, MR18=F5F0
3751 12:40:55.554085 CH1_RK1: MR19=0x303, MR18=0xF5F0, DQSOSC=414, MR23=63, INC=38, DEC=25
3752 12:40:55.557029 [RxdqsGatingPostProcess] freq 1200
3753 12:40:55.560583 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3754 12:40:55.563836 best DQS0 dly(2T, 0.5T) = (0, 11)
3755 12:40:55.567238 best DQS1 dly(2T, 0.5T) = (0, 11)
3756 12:40:55.570756 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3757 12:40:55.573630 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3758 12:40:55.577089 best DQS0 dly(2T, 0.5T) = (0, 11)
3759 12:40:55.580639 best DQS1 dly(2T, 0.5T) = (0, 11)
3760 12:40:55.583691 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3761 12:40:55.586868 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3762 12:40:55.590514 Pre-setting of DQS Precalculation
3763 12:40:55.593643 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3764 12:40:55.603604 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3765 12:40:55.609865 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3766 12:40:55.610360
3767 12:40:55.610697
3768 12:40:55.613156 [Calibration Summary] 2400 Mbps
3769 12:40:55.613585 CH 0, Rank 0
3770 12:40:55.616593 SW Impedance : PASS
3771 12:40:55.619691 DUTY Scan : NO K
3772 12:40:55.620125 ZQ Calibration : PASS
3773 12:40:55.623054 Jitter Meter : NO K
3774 12:40:55.623488 CBT Training : PASS
3775 12:40:55.626075 Write leveling : PASS
3776 12:40:55.629439 RX DQS gating : PASS
3777 12:40:55.629871 RX DQ/DQS(RDDQC) : PASS
3778 12:40:55.633265 TX DQ/DQS : PASS
3779 12:40:55.636332 RX DATLAT : PASS
3780 12:40:55.636874 RX DQ/DQS(Engine): PASS
3781 12:40:55.639620 TX OE : NO K
3782 12:40:55.640090 All Pass.
3783 12:40:55.640436
3784 12:40:55.643031 CH 0, Rank 1
3785 12:40:55.643462 SW Impedance : PASS
3786 12:40:55.646212 DUTY Scan : NO K
3787 12:40:55.649795 ZQ Calibration : PASS
3788 12:40:55.650228 Jitter Meter : NO K
3789 12:40:55.653221 CBT Training : PASS
3790 12:40:55.656309 Write leveling : PASS
3791 12:40:55.656852 RX DQS gating : PASS
3792 12:40:55.659545 RX DQ/DQS(RDDQC) : PASS
3793 12:40:55.663223 TX DQ/DQS : PASS
3794 12:40:55.663694 RX DATLAT : PASS
3795 12:40:55.666220 RX DQ/DQS(Engine): PASS
3796 12:40:55.666685 TX OE : NO K
3797 12:40:55.669493 All Pass.
3798 12:40:55.669948
3799 12:40:55.670304 CH 1, Rank 0
3800 12:40:55.672926 SW Impedance : PASS
3801 12:40:55.673352 DUTY Scan : NO K
3802 12:40:55.676590 ZQ Calibration : PASS
3803 12:40:55.679285 Jitter Meter : NO K
3804 12:40:55.679737 CBT Training : PASS
3805 12:40:55.682791 Write leveling : PASS
3806 12:40:55.686322 RX DQS gating : PASS
3807 12:40:55.686771 RX DQ/DQS(RDDQC) : PASS
3808 12:40:55.689556 TX DQ/DQS : PASS
3809 12:40:55.692752 RX DATLAT : PASS
3810 12:40:55.693197 RX DQ/DQS(Engine): PASS
3811 12:40:55.696498 TX OE : NO K
3812 12:40:55.697119 All Pass.
3813 12:40:55.697485
3814 12:40:55.699232 CH 1, Rank 1
3815 12:40:55.699657 SW Impedance : PASS
3816 12:40:55.702776 DUTY Scan : NO K
3817 12:40:55.706067 ZQ Calibration : PASS
3818 12:40:55.706513 Jitter Meter : NO K
3819 12:40:55.709181 CBT Training : PASS
3820 12:40:55.712805 Write leveling : PASS
3821 12:40:55.713231 RX DQS gating : PASS
3822 12:40:55.715574 RX DQ/DQS(RDDQC) : PASS
3823 12:40:55.718961 TX DQ/DQS : PASS
3824 12:40:55.719410 RX DATLAT : PASS
3825 12:40:55.722516 RX DQ/DQS(Engine): PASS
3826 12:40:55.725576 TX OE : NO K
3827 12:40:55.726102 All Pass.
3828 12:40:55.726498
3829 12:40:55.726836 DramC Write-DBI off
3830 12:40:55.729139 PER_BANK_REFRESH: Hybrid Mode
3831 12:40:55.732127 TX_TRACKING: ON
3832 12:40:55.738755 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3833 12:40:55.745803 [FAST_K] Save calibration result to emmc
3834 12:40:55.749321 dramc_set_vcore_voltage set vcore to 650000
3835 12:40:55.749764 Read voltage for 600, 5
3836 12:40:55.752338 Vio18 = 0
3837 12:40:55.752827 Vcore = 650000
3838 12:40:55.753183 Vdram = 0
3839 12:40:55.755187 Vddq = 0
3840 12:40:55.755609 Vmddr = 0
3841 12:40:55.758561 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3842 12:40:55.765441 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3843 12:40:55.768829 MEM_TYPE=3, freq_sel=19
3844 12:40:55.772153 sv_algorithm_assistance_LP4_1600
3845 12:40:55.775400 ============ PULL DRAM RESETB DOWN ============
3846 12:40:55.778525 ========== PULL DRAM RESETB DOWN end =========
3847 12:40:55.785534 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3848 12:40:55.786066 ===================================
3849 12:40:55.788315 LPDDR4 DRAM CONFIGURATION
3850 12:40:55.791606 ===================================
3851 12:40:55.795141 EX_ROW_EN[0] = 0x0
3852 12:40:55.795660 EX_ROW_EN[1] = 0x0
3853 12:40:55.798534 LP4Y_EN = 0x0
3854 12:40:55.798959 WORK_FSP = 0x0
3855 12:40:55.801502 WL = 0x2
3856 12:40:55.801956 RL = 0x2
3857 12:40:55.805194 BL = 0x2
3858 12:40:55.805640 RPST = 0x0
3859 12:40:55.808600 RD_PRE = 0x0
3860 12:40:55.812025 WR_PRE = 0x1
3861 12:40:55.812633 WR_PST = 0x0
3862 12:40:55.815032 DBI_WR = 0x0
3863 12:40:55.815673 DBI_RD = 0x0
3864 12:40:55.818513 OTF = 0x1
3865 12:40:55.821728 ===================================
3866 12:40:55.824907 ===================================
3867 12:40:55.825354 ANA top config
3868 12:40:55.828311 ===================================
3869 12:40:55.831564 DLL_ASYNC_EN = 0
3870 12:40:55.834598 ALL_SLAVE_EN = 1
3871 12:40:55.835044 NEW_RANK_MODE = 1
3872 12:40:55.838143 DLL_IDLE_MODE = 1
3873 12:40:55.841050 LP45_APHY_COMB_EN = 1
3874 12:40:55.844392 TX_ODT_DIS = 1
3875 12:40:55.847939 NEW_8X_MODE = 1
3876 12:40:55.851313 ===================================
3877 12:40:55.851739 ===================================
3878 12:40:55.854615 data_rate = 1200
3879 12:40:55.858228 CKR = 1
3880 12:40:55.860809 DQ_P2S_RATIO = 8
3881 12:40:55.864682 ===================================
3882 12:40:55.867840 CA_P2S_RATIO = 8
3883 12:40:55.871035 DQ_CA_OPEN = 0
3884 12:40:55.874268 DQ_SEMI_OPEN = 0
3885 12:40:55.874690 CA_SEMI_OPEN = 0
3886 12:40:55.877915 CA_FULL_RATE = 0
3887 12:40:55.881153 DQ_CKDIV4_EN = 1
3888 12:40:55.884072 CA_CKDIV4_EN = 1
3889 12:40:55.887424 CA_PREDIV_EN = 0
3890 12:40:55.891018 PH8_DLY = 0
3891 12:40:55.891445 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3892 12:40:55.894241 DQ_AAMCK_DIV = 4
3893 12:40:55.897225 CA_AAMCK_DIV = 4
3894 12:40:55.900545 CA_ADMCK_DIV = 4
3895 12:40:55.903780 DQ_TRACK_CA_EN = 0
3896 12:40:55.907224 CA_PICK = 600
3897 12:40:55.910615 CA_MCKIO = 600
3898 12:40:55.911041 MCKIO_SEMI = 0
3899 12:40:55.914205 PLL_FREQ = 2288
3900 12:40:55.917553 DQ_UI_PI_RATIO = 32
3901 12:40:55.920551 CA_UI_PI_RATIO = 0
3902 12:40:55.923727 ===================================
3903 12:40:55.927019 ===================================
3904 12:40:55.930178 memory_type:LPDDR4
3905 12:40:55.930619 GP_NUM : 10
3906 12:40:55.933295 SRAM_EN : 1
3907 12:40:55.936480 MD32_EN : 0
3908 12:40:55.940233 ===================================
3909 12:40:55.940855 [ANA_INIT] >>>>>>>>>>>>>>
3910 12:40:55.943164 <<<<<< [CONFIGURE PHASE]: ANA_TX
3911 12:40:55.946550 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3912 12:40:55.949954 ===================================
3913 12:40:55.952910 data_rate = 1200,PCW = 0X5800
3914 12:40:55.956427 ===================================
3915 12:40:55.960080 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3916 12:40:55.966516 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3917 12:40:55.972771 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3918 12:40:55.976202 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3919 12:40:55.979986 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3920 12:40:55.982716 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3921 12:40:55.986071 [ANA_INIT] flow start
3922 12:40:55.986562 [ANA_INIT] PLL >>>>>>>>
3923 12:40:55.989657 [ANA_INIT] PLL <<<<<<<<
3924 12:40:55.992513 [ANA_INIT] MIDPI >>>>>>>>
3925 12:40:55.993007 [ANA_INIT] MIDPI <<<<<<<<
3926 12:40:55.996083 [ANA_INIT] DLL >>>>>>>>
3927 12:40:55.999407 [ANA_INIT] flow end
3928 12:40:56.002934 ============ LP4 DIFF to SE enter ============
3929 12:40:56.005821 ============ LP4 DIFF to SE exit ============
3930 12:40:56.009037 [ANA_INIT] <<<<<<<<<<<<<
3931 12:40:56.012232 [Flow] Enable top DCM control >>>>>
3932 12:40:56.015580 [Flow] Enable top DCM control <<<<<
3933 12:40:56.019142 Enable DLL master slave shuffle
3934 12:40:56.022441 ==============================================================
3935 12:40:56.025795 Gating Mode config
3936 12:40:56.032486 ==============================================================
3937 12:40:56.032966 Config description:
3938 12:40:56.042839 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3939 12:40:56.049075 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3940 12:40:56.055504 SELPH_MODE 0: By rank 1: By Phase
3941 12:40:56.058967 ==============================================================
3942 12:40:56.062410 GAT_TRACK_EN = 1
3943 12:40:56.065438 RX_GATING_MODE = 2
3944 12:40:56.069089 RX_GATING_TRACK_MODE = 2
3945 12:40:56.072187 SELPH_MODE = 1
3946 12:40:56.075345 PICG_EARLY_EN = 1
3947 12:40:56.078867 VALID_LAT_VALUE = 1
3948 12:40:56.081864 ==============================================================
3949 12:40:56.085304 Enter into Gating configuration >>>>
3950 12:40:56.088446 Exit from Gating configuration <<<<
3951 12:40:56.091939 Enter into DVFS_PRE_config >>>>>
3952 12:40:56.104923 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3953 12:40:56.108236 Exit from DVFS_PRE_config <<<<<
3954 12:40:56.111763 Enter into PICG configuration >>>>
3955 12:40:56.115012 Exit from PICG configuration <<<<
3956 12:40:56.115593 [RX_INPUT] configuration >>>>>
3957 12:40:56.117905 [RX_INPUT] configuration <<<<<
3958 12:40:56.124612 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3959 12:40:56.127791 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3960 12:40:56.134880 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3961 12:40:56.141669 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3962 12:40:56.147844 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3963 12:40:56.154210 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3964 12:40:56.157610 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3965 12:40:56.161183 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3966 12:40:56.167558 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3967 12:40:56.171186 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3968 12:40:56.174054 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3969 12:40:56.181067 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3970 12:40:56.183852 ===================================
3971 12:40:56.184336 LPDDR4 DRAM CONFIGURATION
3972 12:40:56.187355 ===================================
3973 12:40:56.190447 EX_ROW_EN[0] = 0x0
3974 12:40:56.191027 EX_ROW_EN[1] = 0x0
3975 12:40:56.193734 LP4Y_EN = 0x0
3976 12:40:56.194197 WORK_FSP = 0x0
3977 12:40:56.197416 WL = 0x2
3978 12:40:56.200869 RL = 0x2
3979 12:40:56.201311 BL = 0x2
3980 12:40:56.203753 RPST = 0x0
3981 12:40:56.204174 RD_PRE = 0x0
3982 12:40:56.207110 WR_PRE = 0x1
3983 12:40:56.207530 WR_PST = 0x0
3984 12:40:56.210308 DBI_WR = 0x0
3985 12:40:56.210728 DBI_RD = 0x0
3986 12:40:56.213920 OTF = 0x1
3987 12:40:56.216800 ===================================
3988 12:40:56.220177 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3989 12:40:56.223320 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3990 12:40:56.230265 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3991 12:40:56.233517 ===================================
3992 12:40:56.233826 LPDDR4 DRAM CONFIGURATION
3993 12:40:56.236984 ===================================
3994 12:40:56.239830 EX_ROW_EN[0] = 0x10
3995 12:40:56.243112 EX_ROW_EN[1] = 0x0
3996 12:40:56.243454 LP4Y_EN = 0x0
3997 12:40:56.246642 WORK_FSP = 0x0
3998 12:40:56.246976 WL = 0x2
3999 12:40:56.249397 RL = 0x2
4000 12:40:56.249699 BL = 0x2
4001 12:40:56.253009 RPST = 0x0
4002 12:40:56.253317 RD_PRE = 0x0
4003 12:40:56.256384 WR_PRE = 0x1
4004 12:40:56.256732 WR_PST = 0x0
4005 12:40:56.259592 DBI_WR = 0x0
4006 12:40:56.259931 DBI_RD = 0x0
4007 12:40:56.262947 OTF = 0x1
4008 12:40:56.266285 ===================================
4009 12:40:56.272776 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4010 12:40:56.276567 nWR fixed to 30
4011 12:40:56.277097 [ModeRegInit_LP4] CH0 RK0
4012 12:40:56.279742 [ModeRegInit_LP4] CH0 RK1
4013 12:40:56.283236 [ModeRegInit_LP4] CH1 RK0
4014 12:40:56.286315 [ModeRegInit_LP4] CH1 RK1
4015 12:40:56.286846 match AC timing 17
4016 12:40:56.292754 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4017 12:40:56.296177 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4018 12:40:56.299371 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4019 12:40:56.305800 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4020 12:40:56.309212 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4021 12:40:56.309664 ==
4022 12:40:56.312285 Dram Type= 6, Freq= 0, CH_0, rank 0
4023 12:40:56.315816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4024 12:40:56.316286 ==
4025 12:40:56.322326 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4026 12:40:56.328732 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4027 12:40:56.332090 [CA 0] Center 36 (6~66) winsize 61
4028 12:40:56.335338 [CA 1] Center 36 (6~66) winsize 61
4029 12:40:56.338837 [CA 2] Center 34 (4~65) winsize 62
4030 12:40:56.342232 [CA 3] Center 34 (4~65) winsize 62
4031 12:40:56.345204 [CA 4] Center 33 (3~64) winsize 62
4032 12:40:56.348654 [CA 5] Center 33 (3~64) winsize 62
4033 12:40:56.349117
4034 12:40:56.351772 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4035 12:40:56.352216
4036 12:40:56.355078 [CATrainingPosCal] consider 1 rank data
4037 12:40:56.358829 u2DelayCellTimex100 = 270/100 ps
4038 12:40:56.361954 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4039 12:40:56.365365 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4040 12:40:56.368233 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4041 12:40:56.371630 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4042 12:40:56.375122 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4043 12:40:56.381958 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4044 12:40:56.382403
4045 12:40:56.386158 CA PerBit enable=1, Macro0, CA PI delay=33
4046 12:40:56.386601
4047 12:40:56.388603 [CBTSetCACLKResult] CA Dly = 33
4048 12:40:56.389003 CS Dly: 5 (0~36)
4049 12:40:56.389422 ==
4050 12:40:56.391990 Dram Type= 6, Freq= 0, CH_0, rank 1
4051 12:40:56.395530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4052 12:40:56.398766 ==
4053 12:40:56.401823 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4054 12:40:56.408429 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4055 12:40:56.411803 [CA 0] Center 35 (5~66) winsize 62
4056 12:40:56.414777 [CA 1] Center 36 (6~66) winsize 61
4057 12:40:56.418153 [CA 2] Center 34 (3~65) winsize 63
4058 12:40:56.421724 [CA 3] Center 34 (4~64) winsize 61
4059 12:40:56.425097 [CA 4] Center 33 (3~64) winsize 62
4060 12:40:56.428129 [CA 5] Center 33 (3~64) winsize 62
4061 12:40:56.428614
4062 12:40:56.431443 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4063 12:40:56.431889
4064 12:40:56.434817 [CATrainingPosCal] consider 2 rank data
4065 12:40:56.437857 u2DelayCellTimex100 = 270/100 ps
4066 12:40:56.441433 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4067 12:40:56.444308 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4068 12:40:56.448114 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4069 12:40:56.454427 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4070 12:40:56.458203 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4071 12:40:56.460825 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4072 12:40:56.461355
4073 12:40:56.464827 CA PerBit enable=1, Macro0, CA PI delay=33
4074 12:40:56.465421
4075 12:40:56.468021 [CBTSetCACLKResult] CA Dly = 33
4076 12:40:56.468665 CS Dly: 5 (0~37)
4077 12:40:56.469172
4078 12:40:56.471065 ----->DramcWriteLeveling(PI) begin...
4079 12:40:56.474374 ==
4080 12:40:56.474857 Dram Type= 6, Freq= 0, CH_0, rank 0
4081 12:40:56.480681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4082 12:40:56.481139 ==
4083 12:40:56.484043 Write leveling (Byte 0): 32 => 32
4084 12:40:56.487336 Write leveling (Byte 1): 32 => 32
4085 12:40:56.490804 DramcWriteLeveling(PI) end<-----
4086 12:40:56.491132
4087 12:40:56.491378 ==
4088 12:40:56.493772 Dram Type= 6, Freq= 0, CH_0, rank 0
4089 12:40:56.497296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4090 12:40:56.497705 ==
4091 12:40:56.500403 [Gating] SW mode calibration
4092 12:40:56.507487 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4093 12:40:56.513925 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4094 12:40:56.517194 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4095 12:40:56.520392 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4096 12:40:56.523706 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4097 12:40:56.530075 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
4098 12:40:56.533848 0 9 16 | B1->B0 | 2f2f 2828 | 0 0 | (0 1) (0 0)
4099 12:40:56.540594 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4100 12:40:56.543943 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4101 12:40:56.546603 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4102 12:40:56.553282 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4103 12:40:56.556561 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4104 12:40:56.560193 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4105 12:40:56.566948 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4106 12:40:56.569454 0 10 16 | B1->B0 | 3232 4040 | 0 0 | (0 0) (0 0)
4107 12:40:56.573002 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4108 12:40:56.579671 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4109 12:40:56.583091 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4110 12:40:56.585933 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4111 12:40:56.592855 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4112 12:40:56.596345 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4113 12:40:56.599384 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4114 12:40:56.606233 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4115 12:40:56.609400 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4116 12:40:56.612855 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4117 12:40:56.619402 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4118 12:40:56.622904 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4119 12:40:56.625849 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4120 12:40:56.629467 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4121 12:40:56.635930 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4122 12:40:56.639289 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4123 12:40:56.642584 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4124 12:40:56.649219 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4125 12:40:56.652503 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4126 12:40:56.655559 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4127 12:40:56.662105 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4128 12:40:56.665228 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4129 12:40:56.668714 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4130 12:40:56.675229 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4131 12:40:56.678799 Total UI for P1: 0, mck2ui 16
4132 12:40:56.681697 best dqsien dly found for B0: ( 0, 13, 14)
4133 12:40:56.685141 Total UI for P1: 0, mck2ui 16
4134 12:40:56.688972 best dqsien dly found for B1: ( 0, 13, 14)
4135 12:40:56.691861 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4136 12:40:56.695409 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4137 12:40:56.695955
4138 12:40:56.698698 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4139 12:40:56.701891 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4140 12:40:56.705241 [Gating] SW calibration Done
4141 12:40:56.705667 ==
4142 12:40:56.708343 Dram Type= 6, Freq= 0, CH_0, rank 0
4143 12:40:56.711378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4144 12:40:56.715048 ==
4145 12:40:56.715474 RX Vref Scan: 0
4146 12:40:56.715814
4147 12:40:56.718314 RX Vref 0 -> 0, step: 1
4148 12:40:56.718741
4149 12:40:56.721701 RX Delay -230 -> 252, step: 16
4150 12:40:56.724703 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4151 12:40:56.727880 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4152 12:40:56.731081 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4153 12:40:56.738241 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4154 12:40:56.741413 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4155 12:40:56.744503 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4156 12:40:56.748047 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4157 12:40:56.751592 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4158 12:40:56.757642 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4159 12:40:56.760978 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4160 12:40:56.764605 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4161 12:40:56.768153 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4162 12:40:56.774183 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4163 12:40:56.777466 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4164 12:40:56.781009 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4165 12:40:56.784392 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4166 12:40:56.787450 ==
4167 12:40:56.787749 Dram Type= 6, Freq= 0, CH_0, rank 0
4168 12:40:56.794089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4169 12:40:56.794501 ==
4170 12:40:56.794849 DQS Delay:
4171 12:40:56.797500 DQS0 = 0, DQS1 = 0
4172 12:40:56.797806 DQM Delay:
4173 12:40:56.800557 DQM0 = 43, DQM1 = 31
4174 12:40:56.800865 DQ Delay:
4175 12:40:56.803852 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4176 12:40:56.807332 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4177 12:40:56.810688 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4178 12:40:56.813685 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4179 12:40:56.814083
4180 12:40:56.814478
4181 12:40:56.814777 ==
4182 12:40:56.817162 Dram Type= 6, Freq= 0, CH_0, rank 0
4183 12:40:56.820269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4184 12:40:56.820711 ==
4185 12:40:56.821073
4186 12:40:56.821374
4187 12:40:56.823812 TX Vref Scan disable
4188 12:40:56.827361 == TX Byte 0 ==
4189 12:40:56.830219 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4190 12:40:56.833738 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4191 12:40:56.836623 == TX Byte 1 ==
4192 12:40:56.840139 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4193 12:40:56.843429 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4194 12:40:56.843992 ==
4195 12:40:56.846984 Dram Type= 6, Freq= 0, CH_0, rank 0
4196 12:40:56.853380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4197 12:40:56.853792 ==
4198 12:40:56.854160
4199 12:40:56.854654
4200 12:40:56.854970 TX Vref Scan disable
4201 12:40:56.857578 == TX Byte 0 ==
4202 12:40:56.861175 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4203 12:40:56.867759 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4204 12:40:56.868168 == TX Byte 1 ==
4205 12:40:56.871249 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4206 12:40:56.877918 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4207 12:40:56.878341
4208 12:40:56.878693 [DATLAT]
4209 12:40:56.879168 Freq=600, CH0 RK0
4210 12:40:56.879625
4211 12:40:56.880568 DATLAT Default: 0x9
4212 12:40:56.880929 0, 0xFFFF, sum = 0
4213 12:40:56.884043 1, 0xFFFF, sum = 0
4214 12:40:56.887246 2, 0xFFFF, sum = 0
4215 12:40:56.887768 3, 0xFFFF, sum = 0
4216 12:40:56.891041 4, 0xFFFF, sum = 0
4217 12:40:56.891577 5, 0xFFFF, sum = 0
4218 12:40:56.894311 6, 0xFFFF, sum = 0
4219 12:40:56.894821 7, 0xFFFF, sum = 0
4220 12:40:56.897200 8, 0x0, sum = 1
4221 12:40:56.897608 9, 0x0, sum = 2
4222 12:40:56.900759 10, 0x0, sum = 3
4223 12:40:56.901161 11, 0x0, sum = 4
4224 12:40:56.901486 best_step = 9
4225 12:40:56.901784
4226 12:40:56.903674 ==
4227 12:40:56.907234 Dram Type= 6, Freq= 0, CH_0, rank 0
4228 12:40:56.910621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4229 12:40:56.911055 ==
4230 12:40:56.911530 RX Vref Scan: 1
4231 12:40:56.911907
4232 12:40:56.913621 RX Vref 0 -> 0, step: 1
4233 12:40:56.914087
4234 12:40:56.917281 RX Delay -195 -> 252, step: 8
4235 12:40:56.917835
4236 12:40:56.920501 Set Vref, RX VrefLevel [Byte0]: 59
4237 12:40:56.923756 [Byte1]: 49
4238 12:40:56.924238
4239 12:40:56.927023 Final RX Vref Byte 0 = 59 to rank0
4240 12:40:56.930696 Final RX Vref Byte 1 = 49 to rank0
4241 12:40:56.933558 Final RX Vref Byte 0 = 59 to rank1
4242 12:40:56.936888 Final RX Vref Byte 1 = 49 to rank1==
4243 12:40:56.940320 Dram Type= 6, Freq= 0, CH_0, rank 0
4244 12:40:56.946477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4245 12:40:56.947013 ==
4246 12:40:56.947487 DQS Delay:
4247 12:40:56.947879 DQS0 = 0, DQS1 = 0
4248 12:40:56.950105 DQM Delay:
4249 12:40:56.950550 DQM0 = 43, DQM1 = 32
4250 12:40:56.953014 DQ Delay:
4251 12:40:56.956478 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4252 12:40:56.960145 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4253 12:40:56.962888 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =24
4254 12:40:56.965991 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4255 12:40:56.966082
4256 12:40:56.966147
4257 12:40:56.972838 [DQSOSCAuto] RK0, (LSB)MR18= 0x623a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 391 ps
4258 12:40:56.976325 CH0 RK0: MR19=808, MR18=623A
4259 12:40:56.982385 CH0_RK0: MR19=0x808, MR18=0x623A, DQSOSC=391, MR23=63, INC=171, DEC=114
4260 12:40:56.982466
4261 12:40:56.986279 ----->DramcWriteLeveling(PI) begin...
4262 12:40:56.986352 ==
4263 12:40:56.989511 Dram Type= 6, Freq= 0, CH_0, rank 1
4264 12:40:56.992554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4265 12:40:56.992655 ==
4266 12:40:56.995964 Write leveling (Byte 0): 33 => 33
4267 12:40:56.998974 Write leveling (Byte 1): 29 => 29
4268 12:40:57.002217 DramcWriteLeveling(PI) end<-----
4269 12:40:57.002301
4270 12:40:57.002366 ==
4271 12:40:57.005523 Dram Type= 6, Freq= 0, CH_0, rank 1
4272 12:40:57.009044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4273 12:40:57.012511 ==
4274 12:40:57.012619 [Gating] SW mode calibration
4275 12:40:57.018948 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4276 12:40:57.025680 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4277 12:40:57.028854 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4278 12:40:57.036027 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4279 12:40:57.038810 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4280 12:40:57.042153 0 9 12 | B1->B0 | 3434 3333 | 0 0 | (0 0) (0 1)
4281 12:40:57.049313 0 9 16 | B1->B0 | 2d2d 2828 | 1 0 | (1 0) (0 0)
4282 12:40:57.052059 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4283 12:40:57.055562 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4284 12:40:57.062097 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4285 12:40:57.065251 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4286 12:40:57.068837 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4287 12:40:57.075041 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4288 12:40:57.078561 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4289 12:40:57.082082 0 10 16 | B1->B0 | 3b3b 4141 | 0 0 | (0 0) (0 0)
4290 12:40:57.088795 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4291 12:40:57.092049 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4292 12:40:57.095523 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4293 12:40:57.102016 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4294 12:40:57.105283 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4295 12:40:57.108387 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4296 12:40:57.114894 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4297 12:40:57.118578 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4298 12:40:57.121747 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4299 12:40:57.128139 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4300 12:40:57.131323 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4301 12:40:57.134858 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4302 12:40:57.141339 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4303 12:40:57.144913 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4304 12:40:57.147886 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4305 12:40:57.154784 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4306 12:40:57.157689 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4307 12:40:57.161026 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4308 12:40:57.167431 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4309 12:40:57.170769 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4310 12:40:57.174129 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4311 12:40:57.181077 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4312 12:40:57.184092 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4313 12:40:57.187512 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4314 12:40:57.190717 Total UI for P1: 0, mck2ui 16
4315 12:40:57.193878 best dqsien dly found for B0: ( 0, 13, 12)
4316 12:40:57.197066 Total UI for P1: 0, mck2ui 16
4317 12:40:57.200251 best dqsien dly found for B1: ( 0, 13, 14)
4318 12:40:57.203745 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4319 12:40:57.206843 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4320 12:40:57.206925
4321 12:40:57.213423 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4322 12:40:57.217049 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4323 12:40:57.217133 [Gating] SW calibration Done
4324 12:40:57.220010 ==
4325 12:40:57.223873 Dram Type= 6, Freq= 0, CH_0, rank 1
4326 12:40:57.226923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4327 12:40:57.226997 ==
4328 12:40:57.227060 RX Vref Scan: 0
4329 12:40:57.227119
4330 12:40:57.230340 RX Vref 0 -> 0, step: 1
4331 12:40:57.230409
4332 12:40:57.233132 RX Delay -230 -> 252, step: 16
4333 12:40:57.236504 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4334 12:40:57.240312 iDelay=218, Bit 1, Center 41 (-134 ~ 217) 352
4335 12:40:57.247578 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4336 12:40:57.250320 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4337 12:40:57.253806 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4338 12:40:57.256621 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4339 12:40:57.263123 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4340 12:40:57.266435 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4341 12:40:57.269914 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4342 12:40:57.273562 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4343 12:40:57.276335 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4344 12:40:57.283208 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4345 12:40:57.286761 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4346 12:40:57.290189 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4347 12:40:57.293111 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4348 12:40:57.299821 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4349 12:40:57.299910 ==
4350 12:40:57.303004 Dram Type= 6, Freq= 0, CH_0, rank 1
4351 12:40:57.306304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4352 12:40:57.306389 ==
4353 12:40:57.306474 DQS Delay:
4354 12:40:57.309857 DQS0 = 0, DQS1 = 0
4355 12:40:57.309941 DQM Delay:
4356 12:40:57.312780 DQM0 = 40, DQM1 = 34
4357 12:40:57.312864 DQ Delay:
4358 12:40:57.316195 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4359 12:40:57.319712 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4360 12:40:57.322840 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4361 12:40:57.326249 DQ12 =33, DQ13 =49, DQ14 =49, DQ15 =33
4362 12:40:57.326329
4363 12:40:57.326392
4364 12:40:57.326450 ==
4365 12:40:57.329601 Dram Type= 6, Freq= 0, CH_0, rank 1
4366 12:40:57.332815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4367 12:40:57.336320 ==
4368 12:40:57.336401
4369 12:40:57.336463
4370 12:40:57.336548 TX Vref Scan disable
4371 12:40:57.339388 == TX Byte 0 ==
4372 12:40:57.342666 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4373 12:40:57.349170 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4374 12:40:57.349251 == TX Byte 1 ==
4375 12:40:57.352615 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4376 12:40:57.358962 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4377 12:40:57.359043 ==
4378 12:40:57.362255 Dram Type= 6, Freq= 0, CH_0, rank 1
4379 12:40:57.365948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4380 12:40:57.366029 ==
4381 12:40:57.366093
4382 12:40:57.366151
4383 12:40:57.368883 TX Vref Scan disable
4384 12:40:57.372434 == TX Byte 0 ==
4385 12:40:57.375306 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4386 12:40:57.379160 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4387 12:40:57.382241 == TX Byte 1 ==
4388 12:40:57.385604 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4389 12:40:57.388660 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4390 12:40:57.388812
4391 12:40:57.392114 [DATLAT]
4392 12:40:57.392246 Freq=600, CH0 RK1
4393 12:40:57.392327
4394 12:40:57.395432 DATLAT Default: 0x9
4395 12:40:57.395542 0, 0xFFFF, sum = 0
4396 12:40:57.398527 1, 0xFFFF, sum = 0
4397 12:40:57.398649 2, 0xFFFF, sum = 0
4398 12:40:57.402048 3, 0xFFFF, sum = 0
4399 12:40:57.402171 4, 0xFFFF, sum = 0
4400 12:40:57.405222 5, 0xFFFF, sum = 0
4401 12:40:57.405400 6, 0xFFFF, sum = 0
4402 12:40:57.408492 7, 0xFFFF, sum = 0
4403 12:40:57.408663 8, 0x0, sum = 1
4404 12:40:57.411678 9, 0x0, sum = 2
4405 12:40:57.411831 10, 0x0, sum = 3
4406 12:40:57.415092 11, 0x0, sum = 4
4407 12:40:57.415265 best_step = 9
4408 12:40:57.415399
4409 12:40:57.415523 ==
4410 12:40:57.418403 Dram Type= 6, Freq= 0, CH_0, rank 1
4411 12:40:57.421968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4412 12:40:57.425271 ==
4413 12:40:57.425518 RX Vref Scan: 0
4414 12:40:57.425773
4415 12:40:57.428555 RX Vref 0 -> 0, step: 1
4416 12:40:57.428866
4417 12:40:57.431925 RX Delay -179 -> 252, step: 8
4418 12:40:57.435317 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4419 12:40:57.438650 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4420 12:40:57.444764 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4421 12:40:57.448122 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4422 12:40:57.451343 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4423 12:40:57.454971 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4424 12:40:57.461934 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4425 12:40:57.464782 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4426 12:40:57.467875 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4427 12:40:57.470892 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4428 12:40:57.477397 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4429 12:40:57.480804 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4430 12:40:57.484167 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4431 12:40:57.487805 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4432 12:40:57.494148 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4433 12:40:57.497732 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4434 12:40:57.497816 ==
4435 12:40:57.501070 Dram Type= 6, Freq= 0, CH_0, rank 1
4436 12:40:57.504485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4437 12:40:57.504592 ==
4438 12:40:57.504664 DQS Delay:
4439 12:40:57.507215 DQS0 = 0, DQS1 = 0
4440 12:40:57.507309 DQM Delay:
4441 12:40:57.511107 DQM0 = 41, DQM1 = 36
4442 12:40:57.511203 DQ Delay:
4443 12:40:57.514328 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4444 12:40:57.517647 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4445 12:40:57.521199 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4446 12:40:57.523952 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4447 12:40:57.524125
4448 12:40:57.524272
4449 12:40:57.533868 [DQSOSCAuto] RK1, (LSB)MR18= 0x6417, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
4450 12:40:57.534040 CH0 RK1: MR19=808, MR18=6417
4451 12:40:57.540566 CH0_RK1: MR19=0x808, MR18=0x6417, DQSOSC=391, MR23=63, INC=171, DEC=114
4452 12:40:57.544079 [RxdqsGatingPostProcess] freq 600
4453 12:40:57.550686 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4454 12:40:57.554028 Pre-setting of DQS Precalculation
4455 12:40:57.557700 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4456 12:40:57.558021 ==
4457 12:40:57.561149 Dram Type= 6, Freq= 0, CH_1, rank 0
4458 12:40:57.567529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4459 12:40:57.567988 ==
4460 12:40:57.571015 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4461 12:40:57.577261 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4462 12:40:57.580748 [CA 0] Center 35 (5~66) winsize 62
4463 12:40:57.583995 [CA 1] Center 35 (5~66) winsize 62
4464 12:40:57.587296 [CA 2] Center 34 (4~65) winsize 62
4465 12:40:57.590749 [CA 3] Center 33 (3~64) winsize 62
4466 12:40:57.594100 [CA 4] Center 34 (4~64) winsize 61
4467 12:40:57.596829 [CA 5] Center 33 (3~64) winsize 62
4468 12:40:57.597368
4469 12:40:57.600403 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4470 12:40:57.600891
4471 12:40:57.603707 [CATrainingPosCal] consider 1 rank data
4472 12:40:57.607181 u2DelayCellTimex100 = 270/100 ps
4473 12:40:57.610027 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4474 12:40:57.616746 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4475 12:40:57.620038 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4476 12:40:57.623301 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4477 12:40:57.626765 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4478 12:40:57.629785 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4479 12:40:57.630237
4480 12:40:57.633912 CA PerBit enable=1, Macro0, CA PI delay=33
4481 12:40:57.634476
4482 12:40:57.636739 [CBTSetCACLKResult] CA Dly = 33
4483 12:40:57.637184 CS Dly: 5 (0~36)
4484 12:40:57.640012 ==
4485 12:40:57.643101 Dram Type= 6, Freq= 0, CH_1, rank 1
4486 12:40:57.646980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4487 12:40:57.647432 ==
4488 12:40:57.649904 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4489 12:40:57.656947 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4490 12:40:57.660438 [CA 0] Center 35 (5~66) winsize 62
4491 12:40:57.663581 [CA 1] Center 36 (6~66) winsize 61
4492 12:40:57.667280 [CA 2] Center 34 (4~65) winsize 62
4493 12:40:57.670597 [CA 3] Center 34 (4~65) winsize 62
4494 12:40:57.673712 [CA 4] Center 34 (4~65) winsize 62
4495 12:40:57.677234 [CA 5] Center 34 (3~65) winsize 63
4496 12:40:57.677683
4497 12:40:57.680215 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4498 12:40:57.680776
4499 12:40:57.683719 [CATrainingPosCal] consider 2 rank data
4500 12:40:57.687153 u2DelayCellTimex100 = 270/100 ps
4501 12:40:57.689835 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4502 12:40:57.696450 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4503 12:40:57.700006 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4504 12:40:57.702970 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4505 12:40:57.706349 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4506 12:40:57.709897 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4507 12:40:57.710369
4508 12:40:57.712795 CA PerBit enable=1, Macro0, CA PI delay=33
4509 12:40:57.713270
4510 12:40:57.716819 [CBTSetCACLKResult] CA Dly = 33
4511 12:40:57.719545 CS Dly: 5 (0~37)
4512 12:40:57.719973
4513 12:40:57.723537 ----->DramcWriteLeveling(PI) begin...
4514 12:40:57.723973 ==
4515 12:40:57.726530 Dram Type= 6, Freq= 0, CH_1, rank 0
4516 12:40:57.729529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4517 12:40:57.730001 ==
4518 12:40:57.732973 Write leveling (Byte 0): 30 => 30
4519 12:40:57.736094 Write leveling (Byte 1): 29 => 29
4520 12:40:57.739366 DramcWriteLeveling(PI) end<-----
4521 12:40:57.739797
4522 12:40:57.740177 ==
4523 12:40:57.742741 Dram Type= 6, Freq= 0, CH_1, rank 0
4524 12:40:57.746523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4525 12:40:57.746958 ==
4526 12:40:57.749656 [Gating] SW mode calibration
4527 12:40:57.756344 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4528 12:40:57.762521 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4529 12:40:57.765989 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4530 12:40:57.769392 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4531 12:40:57.776169 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4532 12:40:57.779185 0 9 12 | B1->B0 | 3333 2e2e | 1 0 | (0 0) (1 0)
4533 12:40:57.782807 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4534 12:40:57.789179 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4535 12:40:57.792546 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4536 12:40:57.795802 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4537 12:40:57.802181 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4538 12:40:57.805653 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4539 12:40:57.808822 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
4540 12:40:57.816199 0 10 12 | B1->B0 | 2f2f 3434 | 0 0 | (0 0) (0 0)
4541 12:40:57.819013 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4542 12:40:57.822596 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4543 12:40:57.829097 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4544 12:40:57.832035 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4545 12:40:57.835689 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4546 12:40:57.842294 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4547 12:40:57.845052 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4548 12:40:57.848396 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4549 12:40:57.855344 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4550 12:40:57.858811 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4551 12:40:57.861671 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4552 12:40:57.868424 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4553 12:40:57.871879 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4554 12:40:57.875056 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4555 12:40:57.881840 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4556 12:40:57.884927 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4557 12:40:57.888148 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4558 12:40:57.895159 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4559 12:40:57.898387 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4560 12:40:57.901774 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4561 12:40:57.908091 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4562 12:40:57.911530 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4563 12:40:57.915029 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4564 12:40:57.921556 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4565 12:40:57.922234 Total UI for P1: 0, mck2ui 16
4566 12:40:57.928279 best dqsien dly found for B0: ( 0, 13, 8)
4567 12:40:57.931114 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4568 12:40:57.934672 Total UI for P1: 0, mck2ui 16
4569 12:40:57.937693 best dqsien dly found for B1: ( 0, 13, 12)
4570 12:40:57.941161 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4571 12:40:57.944309 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4572 12:40:57.944773
4573 12:40:57.947645 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4574 12:40:57.951341 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4575 12:40:57.954003 [Gating] SW calibration Done
4576 12:40:57.954440 ==
4577 12:40:57.957581 Dram Type= 6, Freq= 0, CH_1, rank 0
4578 12:40:57.964455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4579 12:40:57.965087 ==
4580 12:40:57.965477 RX Vref Scan: 0
4581 12:40:57.965800
4582 12:40:57.967521 RX Vref 0 -> 0, step: 1
4583 12:40:57.967998
4584 12:40:57.970712 RX Delay -230 -> 252, step: 16
4585 12:40:57.974297 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4586 12:40:57.977146 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4587 12:40:57.980494 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4588 12:40:57.987321 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4589 12:40:57.990912 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4590 12:40:57.993739 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4591 12:40:57.997240 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4592 12:40:58.003948 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4593 12:40:58.007160 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4594 12:40:58.010287 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4595 12:40:58.013931 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4596 12:40:58.016966 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4597 12:40:58.023752 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4598 12:40:58.027283 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4599 12:40:58.029919 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4600 12:40:58.036799 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4601 12:40:58.037233 ==
4602 12:40:58.039984 Dram Type= 6, Freq= 0, CH_1, rank 0
4603 12:40:58.043300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4604 12:40:58.043777 ==
4605 12:40:58.044123 DQS Delay:
4606 12:40:58.046231 DQS0 = 0, DQS1 = 0
4607 12:40:58.046720 DQM Delay:
4608 12:40:58.049664 DQM0 = 47, DQM1 = 38
4609 12:40:58.050097 DQ Delay:
4610 12:40:58.053042 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4611 12:40:58.056392 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4612 12:40:58.059760 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4613 12:40:58.063122 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4614 12:40:58.063590
4615 12:40:58.063941
4616 12:40:58.064311 ==
4617 12:40:58.066679 Dram Type= 6, Freq= 0, CH_1, rank 0
4618 12:40:58.069900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4619 12:40:58.070334 ==
4620 12:40:58.070717
4621 12:40:58.071040
4622 12:40:58.072948 TX Vref Scan disable
4623 12:40:58.076464 == TX Byte 0 ==
4624 12:40:58.079681 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4625 12:40:58.083351 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4626 12:40:58.086555 == TX Byte 1 ==
4627 12:40:58.089487 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4628 12:40:58.092792 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4629 12:40:58.093373 ==
4630 12:40:58.096160 Dram Type= 6, Freq= 0, CH_1, rank 0
4631 12:40:58.102598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4632 12:40:58.103048 ==
4633 12:40:58.103393
4634 12:40:58.103722
4635 12:40:58.104027 TX Vref Scan disable
4636 12:40:58.107311 == TX Byte 0 ==
4637 12:40:58.110385 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4638 12:40:58.116765 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4639 12:40:58.117192 == TX Byte 1 ==
4640 12:40:58.120576 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4641 12:40:58.126896 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4642 12:40:58.127328
4643 12:40:58.127702 [DATLAT]
4644 12:40:58.128025 Freq=600, CH1 RK0
4645 12:40:58.128368
4646 12:40:58.130413 DATLAT Default: 0x9
4647 12:40:58.130845 0, 0xFFFF, sum = 0
4648 12:40:58.133759 1, 0xFFFF, sum = 0
4649 12:40:58.137138 2, 0xFFFF, sum = 0
4650 12:40:58.137595 3, 0xFFFF, sum = 0
4651 12:40:58.139978 4, 0xFFFF, sum = 0
4652 12:40:58.140491 5, 0xFFFF, sum = 0
4653 12:40:58.143073 6, 0xFFFF, sum = 0
4654 12:40:58.143545 7, 0xFFFF, sum = 0
4655 12:40:58.146831 8, 0x0, sum = 1
4656 12:40:58.147339 9, 0x0, sum = 2
4657 12:40:58.149986 10, 0x0, sum = 3
4658 12:40:58.150414 11, 0x0, sum = 4
4659 12:40:58.150841 best_step = 9
4660 12:40:58.151283
4661 12:40:58.153269 ==
4662 12:40:58.156714 Dram Type= 6, Freq= 0, CH_1, rank 0
4663 12:40:58.159605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4664 12:40:58.160029 ==
4665 12:40:58.160361 RX Vref Scan: 1
4666 12:40:58.160781
4667 12:40:58.163116 RX Vref 0 -> 0, step: 1
4668 12:40:58.163533
4669 12:40:58.166471 RX Delay -179 -> 252, step: 8
4670 12:40:58.166972
4671 12:40:58.169663 Set Vref, RX VrefLevel [Byte0]: 52
4672 12:40:58.172998 [Byte1]: 54
4673 12:40:58.173498
4674 12:40:58.176271 Final RX Vref Byte 0 = 52 to rank0
4675 12:40:58.179705 Final RX Vref Byte 1 = 54 to rank0
4676 12:40:58.182776 Final RX Vref Byte 0 = 52 to rank1
4677 12:40:58.186129 Final RX Vref Byte 1 = 54 to rank1==
4678 12:40:58.189377 Dram Type= 6, Freq= 0, CH_1, rank 0
4679 12:40:58.192786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4680 12:40:58.196478 ==
4681 12:40:58.197117 DQS Delay:
4682 12:40:58.197465 DQS0 = 0, DQS1 = 0
4683 12:40:58.199244 DQM Delay:
4684 12:40:58.199667 DQM0 = 46, DQM1 = 36
4685 12:40:58.202660 DQ Delay:
4686 12:40:58.206095 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =40
4687 12:40:58.206594 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4688 12:40:58.209040 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4689 12:40:58.216136 DQ12 =48, DQ13 =40, DQ14 =44, DQ15 =48
4690 12:40:58.216673
4691 12:40:58.217057
4692 12:40:58.222430 [DQSOSCAuto] RK0, (LSB)MR18= 0x472c, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
4693 12:40:58.225982 CH1 RK0: MR19=808, MR18=472C
4694 12:40:58.232673 CH1_RK0: MR19=0x808, MR18=0x472C, DQSOSC=396, MR23=63, INC=167, DEC=111
4695 12:40:58.233150
4696 12:40:58.235585 ----->DramcWriteLeveling(PI) begin...
4697 12:40:58.236022 ==
4698 12:40:58.239084 Dram Type= 6, Freq= 0, CH_1, rank 1
4699 12:40:58.241997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4700 12:40:58.242431 ==
4701 12:40:58.245812 Write leveling (Byte 0): 29 => 29
4702 12:40:58.249031 Write leveling (Byte 1): 31 => 31
4703 12:40:58.251865 DramcWriteLeveling(PI) end<-----
4704 12:40:58.252336
4705 12:40:58.252734 ==
4706 12:40:58.255284 Dram Type= 6, Freq= 0, CH_1, rank 1
4707 12:40:58.258517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4708 12:40:58.258951 ==
4709 12:40:58.262035 [Gating] SW mode calibration
4710 12:40:58.268765 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4711 12:40:58.275109 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4712 12:40:58.278783 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4713 12:40:58.285177 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4714 12:40:58.288680 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4715 12:40:58.291870 0 9 12 | B1->B0 | 2e2e 3232 | 0 0 | (0 0) (0 0)
4716 12:40:58.298293 0 9 16 | B1->B0 | 2626 2929 | 0 0 | (0 0) (0 0)
4717 12:40:58.301616 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4718 12:40:58.304675 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4719 12:40:58.311662 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4720 12:40:58.314362 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4721 12:40:58.317766 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4722 12:40:58.324588 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4723 12:40:58.327991 0 10 12 | B1->B0 | 3131 2929 | 0 1 | (0 0) (0 0)
4724 12:40:58.331074 0 10 16 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
4725 12:40:58.337511 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4726 12:40:58.340924 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4727 12:40:58.344426 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4728 12:40:58.351150 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4729 12:40:58.354214 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4730 12:40:58.357607 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4731 12:40:58.364181 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4732 12:40:58.367675 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4733 12:40:58.370421 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4734 12:40:58.377008 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4735 12:40:58.380439 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4736 12:40:58.384263 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4737 12:40:58.390569 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4738 12:40:58.393710 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4739 12:40:58.397235 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4740 12:40:58.404003 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4741 12:40:58.406990 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4742 12:40:58.410053 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4743 12:40:58.417039 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4744 12:40:58.420200 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4745 12:40:58.423592 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4746 12:40:58.429943 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4747 12:40:58.433353 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4748 12:40:58.436750 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4749 12:40:58.440187 Total UI for P1: 0, mck2ui 16
4750 12:40:58.443065 best dqsien dly found for B0: ( 0, 13, 12)
4751 12:40:58.446572 Total UI for P1: 0, mck2ui 16
4752 12:40:58.449574 best dqsien dly found for B1: ( 0, 13, 12)
4753 12:40:58.452874 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4754 12:40:58.456071 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4755 12:40:58.459629
4756 12:40:58.462678 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4757 12:40:58.466440 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4758 12:40:58.469728 [Gating] SW calibration Done
4759 12:40:58.470155 ==
4760 12:40:58.472603 Dram Type= 6, Freq= 0, CH_1, rank 1
4761 12:40:58.476131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4762 12:40:58.476592 ==
4763 12:40:58.476936 RX Vref Scan: 0
4764 12:40:58.479567
4765 12:40:58.479986 RX Vref 0 -> 0, step: 1
4766 12:40:58.480319
4767 12:40:58.482463 RX Delay -230 -> 252, step: 16
4768 12:40:58.485801 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4769 12:40:58.492306 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4770 12:40:58.496238 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4771 12:40:58.498945 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4772 12:40:58.502488 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4773 12:40:58.506137 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4774 12:40:58.512391 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4775 12:40:58.515662 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4776 12:40:58.519300 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4777 12:40:58.522665 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4778 12:40:58.528858 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4779 12:40:58.532054 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4780 12:40:58.535708 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4781 12:40:58.539094 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4782 12:40:58.545621 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4783 12:40:58.548656 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4784 12:40:58.549150 ==
4785 12:40:58.552089 Dram Type= 6, Freq= 0, CH_1, rank 1
4786 12:40:58.555360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4787 12:40:58.555865 ==
4788 12:40:58.558882 DQS Delay:
4789 12:40:58.559381 DQS0 = 0, DQS1 = 0
4790 12:40:58.559769 DQM Delay:
4791 12:40:58.562248 DQM0 = 42, DQM1 = 36
4792 12:40:58.562672 DQ Delay:
4793 12:40:58.565433 DQ0 =57, DQ1 =33, DQ2 =25, DQ3 =41
4794 12:40:58.568826 DQ4 =33, DQ5 =57, DQ6 =57, DQ7 =33
4795 12:40:58.571928 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4796 12:40:58.575095 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =49
4797 12:40:58.575541
4798 12:40:58.575981
4799 12:40:58.576396 ==
4800 12:40:58.578525 Dram Type= 6, Freq= 0, CH_1, rank 1
4801 12:40:58.584979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4802 12:40:58.585424 ==
4803 12:40:58.585866
4804 12:40:58.586282
4805 12:40:58.586691 TX Vref Scan disable
4806 12:40:58.588845 == TX Byte 0 ==
4807 12:40:58.592325 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4808 12:40:58.598740 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4809 12:40:58.599176 == TX Byte 1 ==
4810 12:40:58.601855 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4811 12:40:58.608557 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4812 12:40:58.608878 ==
4813 12:40:58.611491 Dram Type= 6, Freq= 0, CH_1, rank 1
4814 12:40:58.614911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4815 12:40:58.615148 ==
4816 12:40:58.615365
4817 12:40:58.615617
4818 12:40:58.618024 TX Vref Scan disable
4819 12:40:58.621930 == TX Byte 0 ==
4820 12:40:58.624884 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4821 12:40:58.628086 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4822 12:40:58.631357 == TX Byte 1 ==
4823 12:40:58.634802 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4824 12:40:58.638072 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4825 12:40:58.638400
4826 12:40:58.641788 [DATLAT]
4827 12:40:58.642019 Freq=600, CH1 RK1
4828 12:40:58.642213
4829 12:40:58.644383 DATLAT Default: 0x9
4830 12:40:58.644673 0, 0xFFFF, sum = 0
4831 12:40:58.648144 1, 0xFFFF, sum = 0
4832 12:40:58.648380 2, 0xFFFF, sum = 0
4833 12:40:58.650969 3, 0xFFFF, sum = 0
4834 12:40:58.651223 4, 0xFFFF, sum = 0
4835 12:40:58.654292 5, 0xFFFF, sum = 0
4836 12:40:58.654619 6, 0xFFFF, sum = 0
4837 12:40:58.657914 7, 0xFFFF, sum = 0
4838 12:40:58.658148 8, 0x0, sum = 1
4839 12:40:58.661357 9, 0x0, sum = 2
4840 12:40:58.661592 10, 0x0, sum = 3
4841 12:40:58.664184 11, 0x0, sum = 4
4842 12:40:58.664422 best_step = 9
4843 12:40:58.664673
4844 12:40:58.664873 ==
4845 12:40:58.668185 Dram Type= 6, Freq= 0, CH_1, rank 1
4846 12:40:58.670762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4847 12:40:58.670999 ==
4848 12:40:58.674049 RX Vref Scan: 0
4849 12:40:58.674283
4850 12:40:58.677797 RX Vref 0 -> 0, step: 1
4851 12:40:58.678029
4852 12:40:58.680579 RX Delay -195 -> 252, step: 8
4853 12:40:58.683914 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4854 12:40:58.687199 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4855 12:40:58.693731 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4856 12:40:58.697093 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4857 12:40:58.700695 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4858 12:40:58.703960 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4859 12:40:58.710350 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4860 12:40:58.713619 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4861 12:40:58.716799 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4862 12:40:58.720509 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4863 12:40:58.723821 iDelay=213, Bit 10, Center 32 (-123 ~ 188) 312
4864 12:40:58.730083 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4865 12:40:58.733359 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4866 12:40:58.736716 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4867 12:40:58.743642 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4868 12:40:58.746383 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4869 12:40:58.746523 ==
4870 12:40:58.749739 Dram Type= 6, Freq= 0, CH_1, rank 1
4871 12:40:58.753287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4872 12:40:58.753365 ==
4873 12:40:58.753430 DQS Delay:
4874 12:40:58.756952 DQS0 = 0, DQS1 = 0
4875 12:40:58.757046 DQM Delay:
4876 12:40:58.759888 DQM0 = 45, DQM1 = 36
4877 12:40:58.759973 DQ Delay:
4878 12:40:58.763233 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4879 12:40:58.766508 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4880 12:40:58.769887 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4881 12:40:58.773146 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4882 12:40:58.773231
4883 12:40:58.773297
4884 12:40:58.782671 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a21, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4885 12:40:58.782758 CH1 RK1: MR19=808, MR18=2A21
4886 12:40:58.789448 CH1_RK1: MR19=0x808, MR18=0x2A21, DQSOSC=401, MR23=63, INC=163, DEC=108
4887 12:40:58.793057 [RxdqsGatingPostProcess] freq 600
4888 12:40:58.799306 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4889 12:40:58.802888 Pre-setting of DQS Precalculation
4890 12:40:58.805967 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4891 12:40:58.815794 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4892 12:40:58.822902 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4893 12:40:58.823041
4894 12:40:58.823172
4895 12:40:58.825824 [Calibration Summary] 1200 Mbps
4896 12:40:58.825963 CH 0, Rank 0
4897 12:40:58.828974 SW Impedance : PASS
4898 12:40:58.829129 DUTY Scan : NO K
4899 12:40:58.832153 ZQ Calibration : PASS
4900 12:40:58.835952 Jitter Meter : NO K
4901 12:40:58.836131 CBT Training : PASS
4902 12:40:58.838878 Write leveling : PASS
4903 12:40:58.842196 RX DQS gating : PASS
4904 12:40:58.842492 RX DQ/DQS(RDDQC) : PASS
4905 12:40:58.846105 TX DQ/DQS : PASS
4906 12:40:58.849237 RX DATLAT : PASS
4907 12:40:58.849546 RX DQ/DQS(Engine): PASS
4908 12:40:58.852679 TX OE : NO K
4909 12:40:58.853092 All Pass.
4910 12:40:58.853498
4911 12:40:58.855600 CH 0, Rank 1
4912 12:40:58.856057 SW Impedance : PASS
4913 12:40:58.859090 DUTY Scan : NO K
4914 12:40:58.862616 ZQ Calibration : PASS
4915 12:40:58.863063 Jitter Meter : NO K
4916 12:40:58.865616 CBT Training : PASS
4917 12:40:58.866148 Write leveling : PASS
4918 12:40:58.869257 RX DQS gating : PASS
4919 12:40:58.872017 RX DQ/DQS(RDDQC) : PASS
4920 12:40:58.872474 TX DQ/DQS : PASS
4921 12:40:58.875778 RX DATLAT : PASS
4922 12:40:58.878880 RX DQ/DQS(Engine): PASS
4923 12:40:58.879429 TX OE : NO K
4924 12:40:58.882194 All Pass.
4925 12:40:58.882634
4926 12:40:58.883086 CH 1, Rank 0
4927 12:40:58.885717 SW Impedance : PASS
4928 12:40:58.886219 DUTY Scan : NO K
4929 12:40:58.889153 ZQ Calibration : PASS
4930 12:40:58.891889 Jitter Meter : NO K
4931 12:40:58.892379 CBT Training : PASS
4932 12:40:58.895469 Write leveling : PASS
4933 12:40:58.898805 RX DQS gating : PASS
4934 12:40:58.899286 RX DQ/DQS(RDDQC) : PASS
4935 12:40:58.901907 TX DQ/DQS : PASS
4936 12:40:58.905117 RX DATLAT : PASS
4937 12:40:58.905560 RX DQ/DQS(Engine): PASS
4938 12:40:58.908391 TX OE : NO K
4939 12:40:58.908878 All Pass.
4940 12:40:58.909410
4941 12:40:58.911904 CH 1, Rank 1
4942 12:40:58.912482 SW Impedance : PASS
4943 12:40:58.915016 DUTY Scan : NO K
4944 12:40:58.918544 ZQ Calibration : PASS
4945 12:40:58.919151 Jitter Meter : NO K
4946 12:40:58.921581 CBT Training : PASS
4947 12:40:58.925168 Write leveling : PASS
4948 12:40:58.925783 RX DQS gating : PASS
4949 12:40:58.928392 RX DQ/DQS(RDDQC) : PASS
4950 12:40:58.929040 TX DQ/DQS : PASS
4951 12:40:58.931806 RX DATLAT : PASS
4952 12:40:58.935521 RX DQ/DQS(Engine): PASS
4953 12:40:58.935928 TX OE : NO K
4954 12:40:58.938827 All Pass.
4955 12:40:58.939125
4956 12:40:58.939383 DramC Write-DBI off
4957 12:40:58.941234 PER_BANK_REFRESH: Hybrid Mode
4958 12:40:58.944624 TX_TRACKING: ON
4959 12:40:58.951048 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4960 12:40:58.954425 [FAST_K] Save calibration result to emmc
4961 12:40:58.957928 dramc_set_vcore_voltage set vcore to 662500
4962 12:40:58.961299 Read voltage for 933, 3
4963 12:40:58.961430 Vio18 = 0
4964 12:40:58.964777 Vcore = 662500
4965 12:40:58.964860 Vdram = 0
4966 12:40:58.964927 Vddq = 0
4967 12:40:58.967660 Vmddr = 0
4968 12:40:58.971074 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4969 12:40:58.978047 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4970 12:40:58.978133 MEM_TYPE=3, freq_sel=17
4971 12:40:58.980758 sv_algorithm_assistance_LP4_1600
4972 12:40:58.987687 ============ PULL DRAM RESETB DOWN ============
4973 12:40:58.991007 ========== PULL DRAM RESETB DOWN end =========
4974 12:40:58.994049 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4975 12:40:58.997528 ===================================
4976 12:40:59.000979 LPDDR4 DRAM CONFIGURATION
4977 12:40:59.004647 ===================================
4978 12:40:59.007326 EX_ROW_EN[0] = 0x0
4979 12:40:59.007410 EX_ROW_EN[1] = 0x0
4980 12:40:59.010496 LP4Y_EN = 0x0
4981 12:40:59.010580 WORK_FSP = 0x0
4982 12:40:59.014018 WL = 0x3
4983 12:40:59.014102 RL = 0x3
4984 12:40:59.017470 BL = 0x2
4985 12:40:59.017555 RPST = 0x0
4986 12:40:59.020323 RD_PRE = 0x0
4987 12:40:59.020432 WR_PRE = 0x1
4988 12:40:59.023899 WR_PST = 0x0
4989 12:40:59.024035 DBI_WR = 0x0
4990 12:40:59.026892 DBI_RD = 0x0
4991 12:40:59.027003 OTF = 0x1
4992 12:40:59.030311 ===================================
4993 12:40:59.033829 ===================================
4994 12:40:59.036985 ANA top config
4995 12:40:59.040344 ===================================
4996 12:40:59.043760 DLL_ASYNC_EN = 0
4997 12:40:59.043865 ALL_SLAVE_EN = 1
4998 12:40:59.046866 NEW_RANK_MODE = 1
4999 12:40:59.050134 DLL_IDLE_MODE = 1
5000 12:40:59.053630 LP45_APHY_COMB_EN = 1
5001 12:40:59.057096 TX_ODT_DIS = 1
5002 12:40:59.057174 NEW_8X_MODE = 1
5003 12:40:59.060143 ===================================
5004 12:40:59.063544 ===================================
5005 12:40:59.067023 data_rate = 1866
5006 12:40:59.070012 CKR = 1
5007 12:40:59.073607 DQ_P2S_RATIO = 8
5008 12:40:59.077206 ===================================
5009 12:40:59.079877 CA_P2S_RATIO = 8
5010 12:40:59.083345 DQ_CA_OPEN = 0
5011 12:40:59.083441 DQ_SEMI_OPEN = 0
5012 12:40:59.086784 CA_SEMI_OPEN = 0
5013 12:40:59.089953 CA_FULL_RATE = 0
5014 12:40:59.093597 DQ_CKDIV4_EN = 1
5015 12:40:59.096844 CA_CKDIV4_EN = 1
5016 12:40:59.099825 CA_PREDIV_EN = 0
5017 12:40:59.099951 PH8_DLY = 0
5018 12:40:59.103244 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5019 12:40:59.106679 DQ_AAMCK_DIV = 4
5020 12:40:59.109693 CA_AAMCK_DIV = 4
5021 12:40:59.113043 CA_ADMCK_DIV = 4
5022 12:40:59.116680 DQ_TRACK_CA_EN = 0
5023 12:40:59.119888 CA_PICK = 933
5024 12:40:59.120094 CA_MCKIO = 933
5025 12:40:59.123303 MCKIO_SEMI = 0
5026 12:40:59.126593 PLL_FREQ = 3732
5027 12:40:59.129686 DQ_UI_PI_RATIO = 32
5028 12:40:59.133062 CA_UI_PI_RATIO = 0
5029 12:40:59.136221 ===================================
5030 12:40:59.139466 ===================================
5031 12:40:59.142793 memory_type:LPDDR4
5032 12:40:59.143237 GP_NUM : 10
5033 12:40:59.146615 SRAM_EN : 1
5034 12:40:59.147065 MD32_EN : 0
5035 12:40:59.149882 ===================================
5036 12:40:59.152651 [ANA_INIT] >>>>>>>>>>>>>>
5037 12:40:59.156673 <<<<<< [CONFIGURE PHASE]: ANA_TX
5038 12:40:59.159469 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5039 12:40:59.162778 ===================================
5040 12:40:59.166380 data_rate = 1866,PCW = 0X8f00
5041 12:40:59.169713 ===================================
5042 12:40:59.172635 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5043 12:40:59.179437 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5044 12:40:59.183021 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5045 12:40:59.189331 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5046 12:40:59.192624 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5047 12:40:59.195945 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5048 12:40:59.196391 [ANA_INIT] flow start
5049 12:40:59.199206 [ANA_INIT] PLL >>>>>>>>
5050 12:40:59.202167 [ANA_INIT] PLL <<<<<<<<
5051 12:40:59.202590 [ANA_INIT] MIDPI >>>>>>>>
5052 12:40:59.205555 [ANA_INIT] MIDPI <<<<<<<<
5053 12:40:59.208824 [ANA_INIT] DLL >>>>>>>>
5054 12:40:59.209400 [ANA_INIT] flow end
5055 12:40:59.215362 ============ LP4 DIFF to SE enter ============
5056 12:40:59.218930 ============ LP4 DIFF to SE exit ============
5057 12:40:59.221912 [ANA_INIT] <<<<<<<<<<<<<
5058 12:40:59.225282 [Flow] Enable top DCM control >>>>>
5059 12:40:59.228531 [Flow] Enable top DCM control <<<<<
5060 12:40:59.231963 Enable DLL master slave shuffle
5061 12:40:59.235441 ==============================================================
5062 12:40:59.238407 Gating Mode config
5063 12:40:59.241918 ==============================================================
5064 12:40:59.244937 Config description:
5065 12:40:59.254958 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5066 12:40:59.261703 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5067 12:40:59.265146 SELPH_MODE 0: By rank 1: By Phase
5068 12:40:59.271714 ==============================================================
5069 12:40:59.274676 GAT_TRACK_EN = 1
5070 12:40:59.277943 RX_GATING_MODE = 2
5071 12:40:59.281428 RX_GATING_TRACK_MODE = 2
5072 12:40:59.284420 SELPH_MODE = 1
5073 12:40:59.287845 PICG_EARLY_EN = 1
5074 12:40:59.291218 VALID_LAT_VALUE = 1
5075 12:40:59.294856 ==============================================================
5076 12:40:59.297635 Enter into Gating configuration >>>>
5077 12:40:59.300824 Exit from Gating configuration <<<<
5078 12:40:59.304406 Enter into DVFS_PRE_config >>>>>
5079 12:40:59.317676 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5080 12:40:59.321283 Exit from DVFS_PRE_config <<<<<
5081 12:40:59.321715 Enter into PICG configuration >>>>
5082 12:40:59.324144 Exit from PICG configuration <<<<
5083 12:40:59.327308 [RX_INPUT] configuration >>>>>
5084 12:40:59.330749 [RX_INPUT] configuration <<<<<
5085 12:40:59.337424 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5086 12:40:59.340961 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5087 12:40:59.347315 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5088 12:40:59.353752 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5089 12:40:59.360251 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5090 12:40:59.367481 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5091 12:40:59.370589 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5092 12:40:59.374021 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5093 12:40:59.380048 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5094 12:40:59.383280 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5095 12:40:59.386900 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5096 12:40:59.389929 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5097 12:40:59.393435 ===================================
5098 12:40:59.396800 LPDDR4 DRAM CONFIGURATION
5099 12:40:59.400018 ===================================
5100 12:40:59.403357 EX_ROW_EN[0] = 0x0
5101 12:40:59.403778 EX_ROW_EN[1] = 0x0
5102 12:40:59.406803 LP4Y_EN = 0x0
5103 12:40:59.407222 WORK_FSP = 0x0
5104 12:40:59.410233 WL = 0x3
5105 12:40:59.410650 RL = 0x3
5106 12:40:59.413160 BL = 0x2
5107 12:40:59.413769 RPST = 0x0
5108 12:40:59.416540 RD_PRE = 0x0
5109 12:40:59.416969 WR_PRE = 0x1
5110 12:40:59.419922 WR_PST = 0x0
5111 12:40:59.423383 DBI_WR = 0x0
5112 12:40:59.423804 DBI_RD = 0x0
5113 12:40:59.426726 OTF = 0x1
5114 12:40:59.429767 ===================================
5115 12:40:59.433291 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5116 12:40:59.436607 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5117 12:40:59.439765 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5118 12:40:59.442842 ===================================
5119 12:40:59.446176 LPDDR4 DRAM CONFIGURATION
5120 12:40:59.449721 ===================================
5121 12:40:59.453242 EX_ROW_EN[0] = 0x10
5122 12:40:59.453711 EX_ROW_EN[1] = 0x0
5123 12:40:59.456361 LP4Y_EN = 0x0
5124 12:40:59.456916 WORK_FSP = 0x0
5125 12:40:59.459682 WL = 0x3
5126 12:40:59.460142 RL = 0x3
5127 12:40:59.463062 BL = 0x2
5128 12:40:59.463494 RPST = 0x0
5129 12:40:59.466288 RD_PRE = 0x0
5130 12:40:59.468905 WR_PRE = 0x1
5131 12:40:59.469476 WR_PST = 0x0
5132 12:40:59.472578 DBI_WR = 0x0
5133 12:40:59.473029 DBI_RD = 0x0
5134 12:40:59.475895 OTF = 0x1
5135 12:40:59.479804 ===================================
5136 12:40:59.482683 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5137 12:40:59.487851 nWR fixed to 30
5138 12:40:59.490930 [ModeRegInit_LP4] CH0 RK0
5139 12:40:59.491428 [ModeRegInit_LP4] CH0 RK1
5140 12:40:59.494382 [ModeRegInit_LP4] CH1 RK0
5141 12:40:59.497563 [ModeRegInit_LP4] CH1 RK1
5142 12:40:59.497994 match AC timing 9
5143 12:40:59.504187 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5144 12:40:59.507300 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5145 12:40:59.510865 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5146 12:40:59.517372 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5147 12:40:59.520778 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5148 12:40:59.521218 ==
5149 12:40:59.523885 Dram Type= 6, Freq= 0, CH_0, rank 0
5150 12:40:59.527348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5151 12:40:59.527807 ==
5152 12:40:59.533737 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5153 12:40:59.541100 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5154 12:40:59.543801 [CA 0] Center 37 (7~68) winsize 62
5155 12:40:59.547282 [CA 1] Center 37 (7~68) winsize 62
5156 12:40:59.550778 [CA 2] Center 34 (4~65) winsize 62
5157 12:40:59.554321 [CA 3] Center 34 (4~65) winsize 62
5158 12:40:59.557301 [CA 4] Center 33 (3~64) winsize 62
5159 12:40:59.560585 [CA 5] Center 33 (3~64) winsize 62
5160 12:40:59.561021
5161 12:40:59.564104 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5162 12:40:59.564577
5163 12:40:59.567298 [CATrainingPosCal] consider 1 rank data
5164 12:40:59.570751 u2DelayCellTimex100 = 270/100 ps
5165 12:40:59.573922 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5166 12:40:59.577049 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5167 12:40:59.580325 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5168 12:40:59.583556 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5169 12:40:59.586889 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5170 12:40:59.593501 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5171 12:40:59.593934
5172 12:40:59.597045 CA PerBit enable=1, Macro0, CA PI delay=33
5173 12:40:59.597560
5174 12:40:59.600254 [CBTSetCACLKResult] CA Dly = 33
5175 12:40:59.600773 CS Dly: 7 (0~38)
5176 12:40:59.601154 ==
5177 12:40:59.603542 Dram Type= 6, Freq= 0, CH_0, rank 1
5178 12:40:59.606855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5179 12:40:59.610237 ==
5180 12:40:59.613446 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5181 12:40:59.620320 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5182 12:40:59.623702 [CA 0] Center 37 (7~68) winsize 62
5183 12:40:59.626455 [CA 1] Center 37 (7~68) winsize 62
5184 12:40:59.629875 [CA 2] Center 34 (4~65) winsize 62
5185 12:40:59.633559 [CA 3] Center 35 (5~65) winsize 61
5186 12:40:59.636438 [CA 4] Center 33 (3~64) winsize 62
5187 12:40:59.639832 [CA 5] Center 32 (2~63) winsize 62
5188 12:40:59.640284
5189 12:40:59.643190 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5190 12:40:59.643749
5191 12:40:59.646732 [CATrainingPosCal] consider 2 rank data
5192 12:40:59.649867 u2DelayCellTimex100 = 270/100 ps
5193 12:40:59.652918 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5194 12:40:59.656469 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5195 12:40:59.662858 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5196 12:40:59.666196 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5197 12:40:59.669515 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5198 12:40:59.673062 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5199 12:40:59.673662
5200 12:40:59.675781 CA PerBit enable=1, Macro0, CA PI delay=33
5201 12:40:59.676334
5202 12:40:59.678982 [CBTSetCACLKResult] CA Dly = 33
5203 12:40:59.679429 CS Dly: 7 (0~39)
5204 12:40:59.679830
5205 12:40:59.686176 ----->DramcWriteLeveling(PI) begin...
5206 12:40:59.686634 ==
5207 12:40:59.689308 Dram Type= 6, Freq= 0, CH_0, rank 0
5208 12:40:59.692479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5209 12:40:59.692946 ==
5210 12:40:59.695725 Write leveling (Byte 0): 31 => 31
5211 12:40:59.698731 Write leveling (Byte 1): 27 => 27
5212 12:40:59.702014 DramcWriteLeveling(PI) end<-----
5213 12:40:59.702448
5214 12:40:59.702807 ==
5215 12:40:59.706260 Dram Type= 6, Freq= 0, CH_0, rank 0
5216 12:40:59.708607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5217 12:40:59.709149 ==
5218 12:40:59.712148 [Gating] SW mode calibration
5219 12:40:59.718758 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5220 12:40:59.724969 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5221 12:40:59.728508 0 14 0 | B1->B0 | 2323 3232 | 1 1 | (1 1) (1 1)
5222 12:40:59.731838 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5223 12:40:59.738417 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5224 12:40:59.741910 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5225 12:40:59.745100 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5226 12:40:59.751368 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5227 12:40:59.754584 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5228 12:40:59.758111 0 14 28 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 1)
5229 12:40:59.764492 0 15 0 | B1->B0 | 3030 2727 | 0 0 | (1 0) (0 0)
5230 12:40:59.768166 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5231 12:40:59.771328 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5232 12:40:59.777573 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5233 12:40:59.780910 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5234 12:40:59.783984 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5235 12:40:59.790814 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5236 12:40:59.794243 0 15 28 | B1->B0 | 2323 3635 | 0 1 | (0 0) (1 1)
5237 12:40:59.797456 1 0 0 | B1->B0 | 2e2e 4141 | 0 0 | (0 0) (0 0)
5238 12:40:59.804115 1 0 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5239 12:40:59.807474 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5240 12:40:59.811192 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5241 12:40:59.817755 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5242 12:40:59.821021 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5243 12:40:59.823892 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5244 12:40:59.830758 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5245 12:40:59.833687 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5246 12:40:59.837395 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5247 12:40:59.843781 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5248 12:40:59.847320 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5249 12:40:59.850723 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5250 12:40:59.856689 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5251 12:40:59.860202 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5252 12:40:59.863735 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5253 12:40:59.870074 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5254 12:40:59.873404 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5255 12:40:59.876296 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5256 12:40:59.883014 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5257 12:40:59.886754 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5258 12:40:59.892715 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5259 12:40:59.896277 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5260 12:40:59.899415 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5261 12:40:59.906582 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5262 12:40:59.907027 Total UI for P1: 0, mck2ui 16
5263 12:40:59.909626 best dqsien dly found for B0: ( 1, 2, 28)
5264 12:40:59.915757 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5265 12:40:59.919679 Total UI for P1: 0, mck2ui 16
5266 12:40:59.923089 best dqsien dly found for B1: ( 1, 3, 0)
5267 12:40:59.926298 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5268 12:40:59.929439 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5269 12:40:59.929879
5270 12:40:59.932613 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5271 12:40:59.935623 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5272 12:40:59.938981 [Gating] SW calibration Done
5273 12:40:59.939461 ==
5274 12:40:59.942583 Dram Type= 6, Freq= 0, CH_0, rank 0
5275 12:40:59.945886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5276 12:40:59.946362 ==
5277 12:40:59.949149 RX Vref Scan: 0
5278 12:40:59.949648
5279 12:40:59.952104 RX Vref 0 -> 0, step: 1
5280 12:40:59.952619
5281 12:40:59.952993 RX Delay -80 -> 252, step: 8
5282 12:40:59.958908 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5283 12:40:59.962163 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5284 12:40:59.967175 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5285 12:40:59.968768 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5286 12:40:59.972119 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5287 12:40:59.975168 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5288 12:40:59.982094 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5289 12:40:59.985559 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5290 12:40:59.988920 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5291 12:40:59.992057 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5292 12:40:59.995462 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5293 12:41:00.001824 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5294 12:41:00.005013 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5295 12:41:00.008934 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5296 12:41:00.011955 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5297 12:41:00.014879 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5298 12:41:00.018271 ==
5299 12:41:00.021489 Dram Type= 6, Freq= 0, CH_0, rank 0
5300 12:41:00.024843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5301 12:41:00.025282 ==
5302 12:41:00.025726 DQS Delay:
5303 12:41:00.028243 DQS0 = 0, DQS1 = 0
5304 12:41:00.028753 DQM Delay:
5305 12:41:00.031541 DQM0 = 97, DQM1 = 85
5306 12:41:00.031975 DQ Delay:
5307 12:41:00.035181 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5308 12:41:00.038004 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5309 12:41:00.041568 DQ8 =79, DQ9 =75, DQ10 =83, DQ11 =79
5310 12:41:00.044495 DQ12 =87, DQ13 =91, DQ14 =95, DQ15 =91
5311 12:41:00.044938
5312 12:41:00.045292
5313 12:41:00.045645 ==
5314 12:41:00.047899 Dram Type= 6, Freq= 0, CH_0, rank 0
5315 12:41:00.050935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5316 12:41:00.054545 ==
5317 12:41:00.054973
5318 12:41:00.055310
5319 12:41:00.055650 TX Vref Scan disable
5320 12:41:00.057332 == TX Byte 0 ==
5321 12:41:00.060554 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5322 12:41:00.063861 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5323 12:41:00.067347 == TX Byte 1 ==
5324 12:41:00.070899 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5325 12:41:00.074115 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5326 12:41:00.077338 ==
5327 12:41:00.077774 Dram Type= 6, Freq= 0, CH_0, rank 0
5328 12:41:00.083993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5329 12:41:00.084417 ==
5330 12:41:00.084838
5331 12:41:00.085168
5332 12:41:00.087313 TX Vref Scan disable
5333 12:41:00.087695 == TX Byte 0 ==
5334 12:41:00.093841 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5335 12:41:00.097208 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5336 12:41:00.097625 == TX Byte 1 ==
5337 12:41:00.103769 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5338 12:41:00.106887 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5339 12:41:00.107004
5340 12:41:00.107112 [DATLAT]
5341 12:41:00.110297 Freq=933, CH0 RK0
5342 12:41:00.110446
5343 12:41:00.110566 DATLAT Default: 0xd
5344 12:41:00.113069 0, 0xFFFF, sum = 0
5345 12:41:00.113165 1, 0xFFFF, sum = 0
5346 12:41:00.116289 2, 0xFFFF, sum = 0
5347 12:41:00.116400 3, 0xFFFF, sum = 0
5348 12:41:00.119934 4, 0xFFFF, sum = 0
5349 12:41:00.123294 5, 0xFFFF, sum = 0
5350 12:41:00.123417 6, 0xFFFF, sum = 0
5351 12:41:00.126128 7, 0xFFFF, sum = 0
5352 12:41:00.126250 8, 0xFFFF, sum = 0
5353 12:41:00.129695 9, 0xFFFF, sum = 0
5354 12:41:00.129782 10, 0x0, sum = 1
5355 12:41:00.133338 11, 0x0, sum = 2
5356 12:41:00.133418 12, 0x0, sum = 3
5357 12:41:00.133484 13, 0x0, sum = 4
5358 12:41:00.136359 best_step = 11
5359 12:41:00.136459
5360 12:41:00.136557 ==
5361 12:41:00.139959 Dram Type= 6, Freq= 0, CH_0, rank 0
5362 12:41:00.142665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5363 12:41:00.142741 ==
5364 12:41:00.146357 RX Vref Scan: 1
5365 12:41:00.146432
5366 12:41:00.149420 RX Vref 0 -> 0, step: 1
5367 12:41:00.149499
5368 12:41:00.149567 RX Delay -61 -> 252, step: 4
5369 12:41:00.149630
5370 12:41:00.152710 Set Vref, RX VrefLevel [Byte0]: 59
5371 12:41:00.155758 [Byte1]: 49
5372 12:41:00.161327
5373 12:41:00.161785 Final RX Vref Byte 0 = 59 to rank0
5374 12:41:00.164764 Final RX Vref Byte 1 = 49 to rank0
5375 12:41:00.167820 Final RX Vref Byte 0 = 59 to rank1
5376 12:41:00.171136 Final RX Vref Byte 1 = 49 to rank1==
5377 12:41:00.174471 Dram Type= 6, Freq= 0, CH_0, rank 0
5378 12:41:00.181038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5379 12:41:00.181460 ==
5380 12:41:00.181801 DQS Delay:
5381 12:41:00.184618 DQS0 = 0, DQS1 = 0
5382 12:41:00.185066 DQM Delay:
5383 12:41:00.185409 DQM0 = 97, DQM1 = 84
5384 12:41:00.187651 DQ Delay:
5385 12:41:00.190837 DQ0 =94, DQ1 =98, DQ2 =94, DQ3 =92
5386 12:41:00.194154 DQ4 =96, DQ5 =88, DQ6 =108, DQ7 =106
5387 12:41:00.197495 DQ8 =76, DQ9 =74, DQ10 =84, DQ11 =80
5388 12:41:00.200719 DQ12 =88, DQ13 =88, DQ14 =98, DQ15 =90
5389 12:41:00.201150
5390 12:41:00.201508
5391 12:41:00.207511 [DQSOSCAuto] RK0, (LSB)MR18= 0x260c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 409 ps
5392 12:41:00.211124 CH0 RK0: MR19=505, MR18=260C
5393 12:41:00.217295 CH0_RK0: MR19=0x505, MR18=0x260C, DQSOSC=409, MR23=63, INC=64, DEC=43
5394 12:41:00.217778
5395 12:41:00.221146 ----->DramcWriteLeveling(PI) begin...
5396 12:41:00.221573 ==
5397 12:41:00.223929 Dram Type= 6, Freq= 0, CH_0, rank 1
5398 12:41:00.227122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5399 12:41:00.227552 ==
5400 12:41:00.230559 Write leveling (Byte 0): 32 => 32
5401 12:41:00.233814 Write leveling (Byte 1): 29 => 29
5402 12:41:00.237109 DramcWriteLeveling(PI) end<-----
5403 12:41:00.237584
5404 12:41:00.237979 ==
5405 12:41:00.240364 Dram Type= 6, Freq= 0, CH_0, rank 1
5406 12:41:00.243797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5407 12:41:00.246990 ==
5408 12:41:00.247432 [Gating] SW mode calibration
5409 12:41:00.253898 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5410 12:41:00.260210 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5411 12:41:00.263864 0 14 0 | B1->B0 | 2b2b 3434 | 1 0 | (1 1) (0 0)
5412 12:41:00.270731 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5413 12:41:00.273838 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5414 12:41:00.277138 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5415 12:41:00.283551 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5416 12:41:00.287154 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5417 12:41:00.290445 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5418 12:41:00.296906 0 14 28 | B1->B0 | 3434 2b2b | 0 0 | (0 0) (0 0)
5419 12:41:00.299926 0 15 0 | B1->B0 | 2a2a 2323 | 1 0 | (0 0) (0 0)
5420 12:41:00.303331 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5421 12:41:00.309940 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5422 12:41:00.313425 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5423 12:41:00.316384 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5424 12:41:00.323028 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5425 12:41:00.326302 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5426 12:41:00.329586 0 15 28 | B1->B0 | 2626 3434 | 1 0 | (0 0) (1 1)
5427 12:41:00.336031 1 0 0 | B1->B0 | 3e3e 4646 | 0 0 | (1 1) (0 0)
5428 12:41:00.339514 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5429 12:41:00.342753 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5430 12:41:00.349136 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5431 12:41:00.352775 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5432 12:41:00.355819 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5433 12:41:00.362472 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5434 12:41:00.366008 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5435 12:41:00.368891 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5436 12:41:00.375543 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5437 12:41:00.378855 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5438 12:41:00.382320 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 12:41:00.389198 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 12:41:00.392264 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 12:41:00.395614 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5442 12:41:00.402038 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5443 12:41:00.405318 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5444 12:41:00.408776 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5445 12:41:00.415531 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5446 12:41:00.418977 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5447 12:41:00.422460 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5448 12:41:00.428637 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5449 12:41:00.432239 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5450 12:41:00.435407 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5451 12:41:00.441986 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5452 12:41:00.442429 Total UI for P1: 0, mck2ui 16
5453 12:41:00.448874 best dqsien dly found for B0: ( 1, 2, 28)
5454 12:41:00.451976 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5455 12:41:00.455211 Total UI for P1: 0, mck2ui 16
5456 12:41:00.458719 best dqsien dly found for B1: ( 1, 2, 30)
5457 12:41:00.462116 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5458 12:41:00.465066 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5459 12:41:00.465506
5460 12:41:00.468644 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5461 12:41:00.471875 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5462 12:41:00.474863 [Gating] SW calibration Done
5463 12:41:00.475305 ==
5464 12:41:00.478247 Dram Type= 6, Freq= 0, CH_0, rank 1
5465 12:41:00.481501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5466 12:41:00.481943 ==
5467 12:41:00.484330 RX Vref Scan: 0
5468 12:41:00.484434
5469 12:41:00.487920 RX Vref 0 -> 0, step: 1
5470 12:41:00.488006
5471 12:41:00.488091 RX Delay -80 -> 252, step: 8
5472 12:41:00.494949 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5473 12:41:00.497735 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5474 12:41:00.501241 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5475 12:41:00.504472 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5476 12:41:00.507907 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5477 12:41:00.511304 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5478 12:41:00.517975 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5479 12:41:00.521025 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5480 12:41:00.524525 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5481 12:41:00.527988 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5482 12:41:00.530923 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5483 12:41:00.537804 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5484 12:41:00.540944 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5485 12:41:00.544299 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5486 12:41:00.547699 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5487 12:41:00.551106 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5488 12:41:00.553949 ==
5489 12:41:00.554196 Dram Type= 6, Freq= 0, CH_0, rank 1
5490 12:41:00.560812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5491 12:41:00.561121 ==
5492 12:41:00.561365 DQS Delay:
5493 12:41:00.564401 DQS0 = 0, DQS1 = 0
5494 12:41:00.564839 DQM Delay:
5495 12:41:00.567412 DQM0 = 97, DQM1 = 88
5496 12:41:00.567839 DQ Delay:
5497 12:41:00.570618 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5498 12:41:00.574217 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5499 12:41:00.577782 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =87
5500 12:41:00.580651 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5501 12:41:00.581082
5502 12:41:00.581419
5503 12:41:00.581735 ==
5504 12:41:00.584191 Dram Type= 6, Freq= 0, CH_0, rank 1
5505 12:41:00.587279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5506 12:41:00.587863 ==
5507 12:41:00.588226
5508 12:41:00.588713
5509 12:41:00.590628 TX Vref Scan disable
5510 12:41:00.593963 == TX Byte 0 ==
5511 12:41:00.597267 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5512 12:41:00.600339 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5513 12:41:00.603617 == TX Byte 1 ==
5514 12:41:00.608163 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5515 12:41:00.610249 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5516 12:41:00.610705 ==
5517 12:41:00.614273 Dram Type= 6, Freq= 0, CH_0, rank 1
5518 12:41:00.620197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5519 12:41:00.620876 ==
5520 12:41:00.621253
5521 12:41:00.621576
5522 12:41:00.621895 TX Vref Scan disable
5523 12:41:00.624226 == TX Byte 0 ==
5524 12:41:00.627825 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5525 12:41:00.634628 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5526 12:41:00.635184 == TX Byte 1 ==
5527 12:41:00.637539 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5528 12:41:00.644546 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5529 12:41:00.644994
5530 12:41:00.645463 [DATLAT]
5531 12:41:00.645876 Freq=933, CH0 RK1
5532 12:41:00.646277
5533 12:41:00.647686 DATLAT Default: 0xb
5534 12:41:00.648334 0, 0xFFFF, sum = 0
5535 12:41:00.651037 1, 0xFFFF, sum = 0
5536 12:41:00.654289 2, 0xFFFF, sum = 0
5537 12:41:00.654731 3, 0xFFFF, sum = 0
5538 12:41:00.657960 4, 0xFFFF, sum = 0
5539 12:41:00.658398 5, 0xFFFF, sum = 0
5540 12:41:00.660841 6, 0xFFFF, sum = 0
5541 12:41:00.661439 7, 0xFFFF, sum = 0
5542 12:41:00.663951 8, 0xFFFF, sum = 0
5543 12:41:00.664395 9, 0xFFFF, sum = 0
5544 12:41:00.667152 10, 0x0, sum = 1
5545 12:41:00.667597 11, 0x0, sum = 2
5546 12:41:00.670570 12, 0x0, sum = 3
5547 12:41:00.671016 13, 0x0, sum = 4
5548 12:41:00.671461 best_step = 11
5549 12:41:00.673998
5550 12:41:00.674436 ==
5551 12:41:00.677226 Dram Type= 6, Freq= 0, CH_0, rank 1
5552 12:41:00.680451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5553 12:41:00.680939 ==
5554 12:41:00.681378 RX Vref Scan: 0
5555 12:41:00.681793
5556 12:41:00.683728 RX Vref 0 -> 0, step: 1
5557 12:41:00.684165
5558 12:41:00.687081 RX Delay -61 -> 252, step: 4
5559 12:41:00.693816 iDelay=199, Bit 0, Center 92 (-1 ~ 186) 188
5560 12:41:00.697030 iDelay=199, Bit 1, Center 96 (-1 ~ 194) 196
5561 12:41:00.700473 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5562 12:41:00.703818 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5563 12:41:00.706643 iDelay=199, Bit 4, Center 94 (-1 ~ 190) 192
5564 12:41:00.710136 iDelay=199, Bit 5, Center 86 (-9 ~ 182) 192
5565 12:41:00.716807 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5566 12:41:00.720142 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5567 12:41:00.723602 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5568 12:41:00.726997 iDelay=199, Bit 9, Center 74 (-17 ~ 166) 184
5569 12:41:00.730416 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5570 12:41:00.736449 iDelay=199, Bit 11, Center 78 (-13 ~ 170) 184
5571 12:41:00.739887 iDelay=199, Bit 12, Center 92 (-1 ~ 186) 188
5572 12:41:00.743052 iDelay=199, Bit 13, Center 94 (-1 ~ 190) 192
5573 12:41:00.746658 iDelay=199, Bit 14, Center 96 (3 ~ 190) 188
5574 12:41:00.750133 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5575 12:41:00.752843 ==
5576 12:41:00.756123 Dram Type= 6, Freq= 0, CH_0, rank 1
5577 12:41:00.759933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5578 12:41:00.760384 ==
5579 12:41:00.760859 DQS Delay:
5580 12:41:00.763387 DQS0 = 0, DQS1 = 0
5581 12:41:00.763834 DQM Delay:
5582 12:41:00.766024 DQM0 = 95, DQM1 = 86
5583 12:41:00.766504 DQ Delay:
5584 12:41:00.769348 DQ0 =92, DQ1 =96, DQ2 =90, DQ3 =94
5585 12:41:00.772825 DQ4 =94, DQ5 =86, DQ6 =104, DQ7 =104
5586 12:41:00.776062 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =78
5587 12:41:00.779465 DQ12 =92, DQ13 =94, DQ14 =96, DQ15 =92
5588 12:41:00.779922
5589 12:41:00.780269
5590 12:41:00.789191 [DQSOSCAuto] RK1, (LSB)MR18= 0x2afb, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 408 ps
5591 12:41:00.789729 CH0 RK1: MR19=504, MR18=2AFB
5592 12:41:00.795905 CH0_RK1: MR19=0x504, MR18=0x2AFB, DQSOSC=408, MR23=63, INC=65, DEC=43
5593 12:41:00.798830 [RxdqsGatingPostProcess] freq 933
5594 12:41:00.805672 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5595 12:41:00.809059 best DQS0 dly(2T, 0.5T) = (0, 10)
5596 12:41:00.812038 best DQS1 dly(2T, 0.5T) = (0, 11)
5597 12:41:00.815611 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5598 12:41:00.818866 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5599 12:41:00.819489 best DQS0 dly(2T, 0.5T) = (0, 10)
5600 12:41:00.822373 best DQS1 dly(2T, 0.5T) = (0, 10)
5601 12:41:00.825098 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5602 12:41:00.828980 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5603 12:41:00.832247 Pre-setting of DQS Precalculation
5604 12:41:00.838757 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5605 12:41:00.839182 ==
5606 12:41:00.841670 Dram Type= 6, Freq= 0, CH_1, rank 0
5607 12:41:00.845136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5608 12:41:00.845565 ==
5609 12:41:00.851972 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5610 12:41:00.858367 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5611 12:41:00.861697 [CA 0] Center 36 (6~67) winsize 62
5612 12:41:00.864630 [CA 1] Center 36 (6~67) winsize 62
5613 12:41:00.868299 [CA 2] Center 34 (4~65) winsize 62
5614 12:41:00.870998 [CA 3] Center 33 (3~64) winsize 62
5615 12:41:00.874907 [CA 4] Center 34 (4~64) winsize 61
5616 12:41:00.878179 [CA 5] Center 33 (3~64) winsize 62
5617 12:41:00.878606
5618 12:41:00.881133 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5619 12:41:00.881601
5620 12:41:00.884717 [CATrainingPosCal] consider 1 rank data
5621 12:41:00.887622 u2DelayCellTimex100 = 270/100 ps
5622 12:41:00.891006 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5623 12:41:00.894243 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5624 12:41:00.897599 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5625 12:41:00.900983 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5626 12:41:00.904578 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5627 12:41:00.907778 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5628 12:41:00.911096
5629 12:41:00.914114 CA PerBit enable=1, Macro0, CA PI delay=33
5630 12:41:00.914643
5631 12:41:00.917642 [CBTSetCACLKResult] CA Dly = 33
5632 12:41:00.918078 CS Dly: 6 (0~37)
5633 12:41:00.918427 ==
5634 12:41:00.921047 Dram Type= 6, Freq= 0, CH_1, rank 1
5635 12:41:00.924289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5636 12:41:00.924804 ==
5637 12:41:00.930867 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5638 12:41:00.937558 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5639 12:41:00.941212 [CA 0] Center 36 (6~67) winsize 62
5640 12:41:00.944126 [CA 1] Center 36 (6~67) winsize 62
5641 12:41:00.947590 [CA 2] Center 34 (4~65) winsize 62
5642 12:41:00.950305 [CA 3] Center 33 (3~64) winsize 62
5643 12:41:00.954208 [CA 4] Center 34 (3~65) winsize 63
5644 12:41:00.957216 [CA 5] Center 33 (3~64) winsize 62
5645 12:41:00.957648
5646 12:41:00.960903 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5647 12:41:00.961462
5648 12:41:00.963942 [CATrainingPosCal] consider 2 rank data
5649 12:41:00.967331 u2DelayCellTimex100 = 270/100 ps
5650 12:41:00.970445 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5651 12:41:00.974146 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5652 12:41:00.976755 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5653 12:41:00.983450 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5654 12:41:00.986534 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5655 12:41:00.990178 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5656 12:41:00.990720
5657 12:41:00.993412 CA PerBit enable=1, Macro0, CA PI delay=33
5658 12:41:00.993886
5659 12:41:00.996725 [CBTSetCACLKResult] CA Dly = 33
5660 12:41:00.997197 CS Dly: 7 (0~39)
5661 12:41:00.997542
5662 12:41:01.000224 ----->DramcWriteLeveling(PI) begin...
5663 12:41:01.000749 ==
5664 12:41:01.003394 Dram Type= 6, Freq= 0, CH_1, rank 0
5665 12:41:01.010045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5666 12:41:01.010473 ==
5667 12:41:01.013258 Write leveling (Byte 0): 25 => 25
5668 12:41:01.016636 Write leveling (Byte 1): 27 => 27
5669 12:41:01.019686 DramcWriteLeveling(PI) end<-----
5670 12:41:01.020104
5671 12:41:01.020461 ==
5672 12:41:01.023089 Dram Type= 6, Freq= 0, CH_1, rank 0
5673 12:41:01.026559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5674 12:41:01.027089 ==
5675 12:41:01.029803 [Gating] SW mode calibration
5676 12:41:01.036424 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5677 12:41:01.042702 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5678 12:41:01.046150 0 14 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5679 12:41:01.049424 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5680 12:41:01.056086 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5681 12:41:01.059260 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5682 12:41:01.062794 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5683 12:41:01.066226 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5684 12:41:01.073035 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
5685 12:41:01.075992 0 14 28 | B1->B0 | 2f2f 2d2d | 0 1 | (0 1) (1 0)
5686 12:41:01.079346 0 15 0 | B1->B0 | 2828 2323 | 0 0 | (1 1) (0 0)
5687 12:41:01.086159 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5688 12:41:01.089356 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5689 12:41:01.092689 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5690 12:41:01.098940 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5691 12:41:01.102476 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5692 12:41:01.105566 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5693 12:41:01.112333 0 15 28 | B1->B0 | 3434 3939 | 0 1 | (1 1) (0 0)
5694 12:41:01.115992 1 0 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5695 12:41:01.118742 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5696 12:41:01.125442 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5697 12:41:01.129077 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5698 12:41:01.132457 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5699 12:41:01.138438 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5700 12:41:01.142298 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5701 12:41:01.145825 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5702 12:41:01.152252 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5703 12:41:01.155018 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5704 12:41:01.158689 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5705 12:41:01.165296 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5706 12:41:01.168964 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5707 12:41:01.171978 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5708 12:41:01.178668 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5709 12:41:01.182054 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5710 12:41:01.184810 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5711 12:41:01.191927 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5712 12:41:01.195250 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5713 12:41:01.198070 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5714 12:41:01.205266 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5715 12:41:01.208155 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5716 12:41:01.211562 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5717 12:41:01.217791 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5718 12:41:01.221057 Total UI for P1: 0, mck2ui 16
5719 12:41:01.224147 best dqsien dly found for B0: ( 1, 2, 24)
5720 12:41:01.227715 Total UI for P1: 0, mck2ui 16
5721 12:41:01.231206 best dqsien dly found for B1: ( 1, 2, 24)
5722 12:41:01.234190 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5723 12:41:01.237921 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5724 12:41:01.238369
5725 12:41:01.240656 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5726 12:41:01.244081 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5727 12:41:01.247486 [Gating] SW calibration Done
5728 12:41:01.247942 ==
5729 12:41:01.251027 Dram Type= 6, Freq= 0, CH_1, rank 0
5730 12:41:01.254413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5731 12:41:01.254861 ==
5732 12:41:01.257762 RX Vref Scan: 0
5733 12:41:01.258200
5734 12:41:01.260740 RX Vref 0 -> 0, step: 1
5735 12:41:01.261189
5736 12:41:01.261588 RX Delay -80 -> 252, step: 8
5737 12:41:01.267422 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5738 12:41:01.270860 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5739 12:41:01.273904 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5740 12:41:01.277306 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5741 12:41:01.280707 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5742 12:41:01.283903 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5743 12:41:01.290232 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5744 12:41:01.293967 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5745 12:41:01.296982 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5746 12:41:01.300151 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5747 12:41:01.303386 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5748 12:41:01.309932 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5749 12:41:01.313238 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5750 12:41:01.316633 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5751 12:41:01.319753 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5752 12:41:01.323597 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5753 12:41:01.326780 ==
5754 12:41:01.329566 Dram Type= 6, Freq= 0, CH_1, rank 0
5755 12:41:01.333625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5756 12:41:01.333937 ==
5757 12:41:01.334183 DQS Delay:
5758 12:41:01.336393 DQS0 = 0, DQS1 = 0
5759 12:41:01.336764 DQM Delay:
5760 12:41:01.339925 DQM0 = 102, DQM1 = 91
5761 12:41:01.340229 DQ Delay:
5762 12:41:01.343145 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5763 12:41:01.345932 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5764 12:41:01.349250 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =79
5765 12:41:01.352922 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =103
5766 12:41:01.353227
5767 12:41:01.353470
5768 12:41:01.353699 ==
5769 12:41:01.355954 Dram Type= 6, Freq= 0, CH_1, rank 0
5770 12:41:01.359373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5771 12:41:01.359682 ==
5772 12:41:01.363018
5773 12:41:01.363425
5774 12:41:01.363770 TX Vref Scan disable
5775 12:41:01.366407 == TX Byte 0 ==
5776 12:41:01.369188 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5777 12:41:01.372497 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5778 12:41:01.375992 == TX Byte 1 ==
5779 12:41:01.379470 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5780 12:41:01.382283 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5781 12:41:01.385709 ==
5782 12:41:01.386236 Dram Type= 6, Freq= 0, CH_1, rank 0
5783 12:41:01.392817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5784 12:41:01.393251 ==
5785 12:41:01.393595
5786 12:41:01.393940
5787 12:41:01.395513 TX Vref Scan disable
5788 12:41:01.395942 == TX Byte 0 ==
5789 12:41:01.402118 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5790 12:41:01.404926 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5791 12:41:01.405395 == TX Byte 1 ==
5792 12:41:01.412269 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5793 12:41:01.415630 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5794 12:41:01.416085
5795 12:41:01.416680 [DATLAT]
5796 12:41:01.418931 Freq=933, CH1 RK0
5797 12:41:01.419397
5798 12:41:01.419745 DATLAT Default: 0xd
5799 12:41:01.422042 0, 0xFFFF, sum = 0
5800 12:41:01.422681 1, 0xFFFF, sum = 0
5801 12:41:01.425323 2, 0xFFFF, sum = 0
5802 12:41:01.428545 3, 0xFFFF, sum = 0
5803 12:41:01.429011 4, 0xFFFF, sum = 0
5804 12:41:01.431886 5, 0xFFFF, sum = 0
5805 12:41:01.432361 6, 0xFFFF, sum = 0
5806 12:41:01.434547 7, 0xFFFF, sum = 0
5807 12:41:01.435001 8, 0xFFFF, sum = 0
5808 12:41:01.437995 9, 0xFFFF, sum = 0
5809 12:41:01.438435 10, 0x0, sum = 1
5810 12:41:01.441650 11, 0x0, sum = 2
5811 12:41:01.442111 12, 0x0, sum = 3
5812 12:41:01.444897 13, 0x0, sum = 4
5813 12:41:01.445332 best_step = 11
5814 12:41:01.445708
5815 12:41:01.446028 ==
5816 12:41:01.448196 Dram Type= 6, Freq= 0, CH_1, rank 0
5817 12:41:01.451510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5818 12:41:01.451975 ==
5819 12:41:01.454412 RX Vref Scan: 1
5820 12:41:01.454892
5821 12:41:01.457921 RX Vref 0 -> 0, step: 1
5822 12:41:01.458353
5823 12:41:01.458723 RX Delay -69 -> 252, step: 4
5824 12:41:01.459052
5825 12:41:01.461475 Set Vref, RX VrefLevel [Byte0]: 52
5826 12:41:01.465030 [Byte1]: 54
5827 12:41:01.469641
5828 12:41:01.470088 Final RX Vref Byte 0 = 52 to rank0
5829 12:41:01.473065 Final RX Vref Byte 1 = 54 to rank0
5830 12:41:01.475913 Final RX Vref Byte 0 = 52 to rank1
5831 12:41:01.479608 Final RX Vref Byte 1 = 54 to rank1==
5832 12:41:01.483038 Dram Type= 6, Freq= 0, CH_1, rank 0
5833 12:41:01.489314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5834 12:41:01.489825 ==
5835 12:41:01.490198 DQS Delay:
5836 12:41:01.490529 DQS0 = 0, DQS1 = 0
5837 12:41:01.492659 DQM Delay:
5838 12:41:01.493103 DQM0 = 100, DQM1 = 93
5839 12:41:01.496032 DQ Delay:
5840 12:41:01.499572 DQ0 =104, DQ1 =96, DQ2 =92, DQ3 =98
5841 12:41:01.502645 DQ4 =98, DQ5 =112, DQ6 =110, DQ7 =96
5842 12:41:01.506207 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =86
5843 12:41:01.508997 DQ12 =100, DQ13 =98, DQ14 =106, DQ15 =102
5844 12:41:01.509444
5845 12:41:01.509798
5846 12:41:01.515657 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d0d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 412 ps
5847 12:41:01.519279 CH1 RK0: MR19=505, MR18=1D0D
5848 12:41:01.525832 CH1_RK0: MR19=0x505, MR18=0x1D0D, DQSOSC=412, MR23=63, INC=63, DEC=42
5849 12:41:01.526266
5850 12:41:01.529047 ----->DramcWriteLeveling(PI) begin...
5851 12:41:01.529485 ==
5852 12:41:01.532037 Dram Type= 6, Freq= 0, CH_1, rank 1
5853 12:41:01.535323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5854 12:41:01.535753 ==
5855 12:41:01.538589 Write leveling (Byte 0): 26 => 26
5856 12:41:01.542000 Write leveling (Byte 1): 28 => 28
5857 12:41:01.545584 DramcWriteLeveling(PI) end<-----
5858 12:41:01.546011
5859 12:41:01.546344 ==
5860 12:41:01.548258 Dram Type= 6, Freq= 0, CH_1, rank 1
5861 12:41:01.554907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5862 12:41:01.555335 ==
5863 12:41:01.555677 [Gating] SW mode calibration
5864 12:41:01.565053 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5865 12:41:01.568664 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5866 12:41:01.575041 0 14 0 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
5867 12:41:01.578205 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5868 12:41:01.581575 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5869 12:41:01.588615 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5870 12:41:01.591355 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5871 12:41:01.594555 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5872 12:41:01.601661 0 14 24 | B1->B0 | 3131 3434 | 1 1 | (1 0) (1 1)
5873 12:41:01.604779 0 14 28 | B1->B0 | 2929 2f2f | 0 0 | (0 0) (0 0)
5874 12:41:01.607663 0 15 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5875 12:41:01.614919 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5876 12:41:01.617927 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5877 12:41:01.621031 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5878 12:41:01.627750 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5879 12:41:01.630868 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5880 12:41:01.633976 0 15 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5881 12:41:01.640562 0 15 28 | B1->B0 | 3c3c 3232 | 0 0 | (0 0) (0 0)
5882 12:41:01.643871 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (1 1)
5883 12:41:01.647580 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5884 12:41:01.653801 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5885 12:41:01.657342 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5886 12:41:01.660597 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5887 12:41:01.667002 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5888 12:41:01.670557 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5889 12:41:01.674435 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5890 12:41:01.680470 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5891 12:41:01.683678 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5892 12:41:01.686959 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5893 12:41:01.693432 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5894 12:41:01.697041 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5895 12:41:01.700062 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5896 12:41:01.706513 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5897 12:41:01.710035 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5898 12:41:01.713225 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5899 12:41:01.719743 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5900 12:41:01.723325 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5901 12:41:01.726694 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5902 12:41:01.733061 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5903 12:41:01.736466 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5904 12:41:01.739682 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5905 12:41:01.746379 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5906 12:41:01.746942 Total UI for P1: 0, mck2ui 16
5907 12:41:01.753175 best dqsien dly found for B1: ( 1, 2, 26)
5908 12:41:01.756053 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5909 12:41:01.759293 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5910 12:41:01.762796 Total UI for P1: 0, mck2ui 16
5911 12:41:01.765993 best dqsien dly found for B0: ( 1, 2, 30)
5912 12:41:01.769499 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5913 12:41:01.772547 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5914 12:41:01.773008
5915 12:41:01.779127 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5916 12:41:01.782451 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5917 12:41:01.782912 [Gating] SW calibration Done
5918 12:41:01.785926 ==
5919 12:41:01.789132 Dram Type= 6, Freq= 0, CH_1, rank 1
5920 12:41:01.792423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5921 12:41:01.792926 ==
5922 12:41:01.793275 RX Vref Scan: 0
5923 12:41:01.793634
5924 12:41:01.795961 RX Vref 0 -> 0, step: 1
5925 12:41:01.796435
5926 12:41:01.798900 RX Delay -80 -> 252, step: 8
5927 12:41:01.802781 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5928 12:41:01.806139 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5929 12:41:01.809130 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5930 12:41:01.815610 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5931 12:41:01.818932 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5932 12:41:01.822308 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5933 12:41:01.825696 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5934 12:41:01.828619 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5935 12:41:01.835158 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5936 12:41:01.838336 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5937 12:41:01.841658 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5938 12:41:01.844990 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5939 12:41:01.848120 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5940 12:41:01.851504 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5941 12:41:01.858506 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5942 12:41:01.861949 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5943 12:41:01.862600 ==
5944 12:41:01.865130 Dram Type= 6, Freq= 0, CH_1, rank 1
5945 12:41:01.868618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5946 12:41:01.869042 ==
5947 12:41:01.871744 DQS Delay:
5948 12:41:01.872166 DQS0 = 0, DQS1 = 0
5949 12:41:01.872503 DQM Delay:
5950 12:41:01.874490 DQM0 = 99, DQM1 = 91
5951 12:41:01.874912 DQ Delay:
5952 12:41:01.877959 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5953 12:41:01.881693 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5954 12:41:01.884975 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =87
5955 12:41:01.888466 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5956 12:41:01.889030
5957 12:41:01.889372
5958 12:41:01.889682 ==
5959 12:41:01.891184 Dram Type= 6, Freq= 0, CH_1, rank 1
5960 12:41:01.897995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5961 12:41:01.898423 ==
5962 12:41:01.898759
5963 12:41:01.899068
5964 12:41:01.900979 TX Vref Scan disable
5965 12:41:01.901401 == TX Byte 0 ==
5966 12:41:01.904541 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5967 12:41:01.910923 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5968 12:41:01.911351 == TX Byte 1 ==
5969 12:41:01.914606 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5970 12:41:01.920737 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5971 12:41:01.921165 ==
5972 12:41:01.924391 Dram Type= 6, Freq= 0, CH_1, rank 1
5973 12:41:01.927645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5974 12:41:01.928069 ==
5975 12:41:01.928405
5976 12:41:01.928763
5977 12:41:01.931138 TX Vref Scan disable
5978 12:41:01.934346 == TX Byte 0 ==
5979 12:41:01.937344 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5980 12:41:01.940982 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5981 12:41:01.944006 == TX Byte 1 ==
5982 12:41:01.947422 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5983 12:41:01.950400 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5984 12:41:01.950824
5985 12:41:01.953635 [DATLAT]
5986 12:41:01.954058 Freq=933, CH1 RK1
5987 12:41:01.954395
5988 12:41:01.956969 DATLAT Default: 0xb
5989 12:41:01.957391 0, 0xFFFF, sum = 0
5990 12:41:01.960360 1, 0xFFFF, sum = 0
5991 12:41:01.960821 2, 0xFFFF, sum = 0
5992 12:41:01.963930 3, 0xFFFF, sum = 0
5993 12:41:01.964358 4, 0xFFFF, sum = 0
5994 12:41:01.966757 5, 0xFFFF, sum = 0
5995 12:41:01.967184 6, 0xFFFF, sum = 0
5996 12:41:01.970555 7, 0xFFFF, sum = 0
5997 12:41:01.970983 8, 0xFFFF, sum = 0
5998 12:41:01.973465 9, 0xFFFF, sum = 0
5999 12:41:01.973892 10, 0x0, sum = 1
6000 12:41:01.976927 11, 0x0, sum = 2
6001 12:41:01.977446 12, 0x0, sum = 3
6002 12:41:01.980179 13, 0x0, sum = 4
6003 12:41:01.980633 best_step = 11
6004 12:41:01.980978
6005 12:41:01.981289 ==
6006 12:41:01.983129 Dram Type= 6, Freq= 0, CH_1, rank 1
6007 12:41:01.989888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6008 12:41:01.990314 ==
6009 12:41:01.990650 RX Vref Scan: 0
6010 12:41:01.990966
6011 12:41:01.993268 RX Vref 0 -> 0, step: 1
6012 12:41:01.993692
6013 12:41:01.996173 RX Delay -61 -> 252, step: 4
6014 12:41:01.999761 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
6015 12:41:02.006258 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
6016 12:41:02.009773 iDelay=207, Bit 2, Center 88 (-1 ~ 178) 180
6017 12:41:02.013170 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
6018 12:41:02.016316 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
6019 12:41:02.019561 iDelay=207, Bit 5, Center 110 (19 ~ 202) 184
6020 12:41:02.022569 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
6021 12:41:02.029723 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
6022 12:41:02.032440 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
6023 12:41:02.035963 iDelay=207, Bit 9, Center 82 (-9 ~ 174) 184
6024 12:41:02.039226 iDelay=207, Bit 10, Center 94 (7 ~ 182) 176
6025 12:41:02.042397 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
6026 12:41:02.049031 iDelay=207, Bit 12, Center 104 (15 ~ 194) 180
6027 12:41:02.052410 iDelay=207, Bit 13, Center 98 (7 ~ 190) 184
6028 12:41:02.056169 iDelay=207, Bit 14, Center 100 (11 ~ 190) 180
6029 12:41:02.059572 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
6030 12:41:02.060046 ==
6031 12:41:02.062957 Dram Type= 6, Freq= 0, CH_1, rank 1
6032 12:41:02.069109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6033 12:41:02.069672 ==
6034 12:41:02.070056 DQS Delay:
6035 12:41:02.070378 DQS0 = 0, DQS1 = 0
6036 12:41:02.072493 DQM Delay:
6037 12:41:02.072998 DQM0 = 100, DQM1 = 93
6038 12:41:02.075837 DQ Delay:
6039 12:41:02.078667 DQ0 =104, DQ1 =94, DQ2 =88, DQ3 =98
6040 12:41:02.082210 DQ4 =98, DQ5 =110, DQ6 =114, DQ7 =98
6041 12:41:02.085418 DQ8 =82, DQ9 =82, DQ10 =94, DQ11 =84
6042 12:41:02.088961 DQ12 =104, DQ13 =98, DQ14 =100, DQ15 =102
6043 12:41:02.089464
6044 12:41:02.089858
6045 12:41:02.095138 [DQSOSCAuto] RK1, (LSB)MR18= 0x802, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps
6046 12:41:02.098579 CH1 RK1: MR19=505, MR18=802
6047 12:41:02.105220 CH1_RK1: MR19=0x505, MR18=0x802, DQSOSC=419, MR23=63, INC=61, DEC=41
6048 12:41:02.108670 [RxdqsGatingPostProcess] freq 933
6049 12:41:02.115351 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6050 12:41:02.115891 best DQS0 dly(2T, 0.5T) = (0, 10)
6051 12:41:02.118682 best DQS1 dly(2T, 0.5T) = (0, 10)
6052 12:41:02.121537 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6053 12:41:02.125063 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6054 12:41:02.128435 best DQS0 dly(2T, 0.5T) = (0, 10)
6055 12:41:02.132014 best DQS1 dly(2T, 0.5T) = (0, 10)
6056 12:41:02.135608 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6057 12:41:02.138373 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6058 12:41:02.141652 Pre-setting of DQS Precalculation
6059 12:41:02.148356 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6060 12:41:02.154500 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6061 12:41:02.161061 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6062 12:41:02.161487
6063 12:41:02.161872
6064 12:41:02.165020 [Calibration Summary] 1866 Mbps
6065 12:41:02.165448 CH 0, Rank 0
6066 12:41:02.167781 SW Impedance : PASS
6067 12:41:02.171280 DUTY Scan : NO K
6068 12:41:02.171709 ZQ Calibration : PASS
6069 12:41:02.174679 Jitter Meter : NO K
6070 12:41:02.175216 CBT Training : PASS
6071 12:41:02.178203 Write leveling : PASS
6072 12:41:02.181205 RX DQS gating : PASS
6073 12:41:02.181634 RX DQ/DQS(RDDQC) : PASS
6074 12:41:02.184636 TX DQ/DQS : PASS
6075 12:41:02.187865 RX DATLAT : PASS
6076 12:41:02.188290 RX DQ/DQS(Engine): PASS
6077 12:41:02.191126 TX OE : NO K
6078 12:41:02.191554 All Pass.
6079 12:41:02.191890
6080 12:41:02.194481 CH 0, Rank 1
6081 12:41:02.194909 SW Impedance : PASS
6082 12:41:02.197937 DUTY Scan : NO K
6083 12:41:02.200860 ZQ Calibration : PASS
6084 12:41:02.201285 Jitter Meter : NO K
6085 12:41:02.204215 CBT Training : PASS
6086 12:41:02.207364 Write leveling : PASS
6087 12:41:02.207789 RX DQS gating : PASS
6088 12:41:02.210980 RX DQ/DQS(RDDQC) : PASS
6089 12:41:02.214038 TX DQ/DQS : PASS
6090 12:41:02.214464 RX DATLAT : PASS
6091 12:41:02.217555 RX DQ/DQS(Engine): PASS
6092 12:41:02.220611 TX OE : NO K
6093 12:41:02.221039 All Pass.
6094 12:41:02.221378
6095 12:41:02.221691 CH 1, Rank 0
6096 12:41:02.224018 SW Impedance : PASS
6097 12:41:02.227558 DUTY Scan : NO K
6098 12:41:02.228153 ZQ Calibration : PASS
6099 12:41:02.230946 Jitter Meter : NO K
6100 12:41:02.233937 CBT Training : PASS
6101 12:41:02.234478 Write leveling : PASS
6102 12:41:02.237362 RX DQS gating : PASS
6103 12:41:02.240579 RX DQ/DQS(RDDQC) : PASS
6104 12:41:02.241038 TX DQ/DQS : PASS
6105 12:41:02.243996 RX DATLAT : PASS
6106 12:41:02.244511 RX DQ/DQS(Engine): PASS
6107 12:41:02.247054 TX OE : NO K
6108 12:41:02.247492 All Pass.
6109 12:41:02.247876
6110 12:41:02.250250 CH 1, Rank 1
6111 12:41:02.253492 SW Impedance : PASS
6112 12:41:02.253943 DUTY Scan : NO K
6113 12:41:02.256865 ZQ Calibration : PASS
6114 12:41:02.257296 Jitter Meter : NO K
6115 12:41:02.260439 CBT Training : PASS
6116 12:41:02.263768 Write leveling : PASS
6117 12:41:02.264230 RX DQS gating : PASS
6118 12:41:02.266835 RX DQ/DQS(RDDQC) : PASS
6119 12:41:02.269796 TX DQ/DQS : PASS
6120 12:41:02.270235 RX DATLAT : PASS
6121 12:41:02.273014 RX DQ/DQS(Engine): PASS
6122 12:41:02.276706 TX OE : NO K
6123 12:41:02.277262 All Pass.
6124 12:41:02.277711
6125 12:41:02.279969 DramC Write-DBI off
6126 12:41:02.280409 PER_BANK_REFRESH: Hybrid Mode
6127 12:41:02.283443 TX_TRACKING: ON
6128 12:41:02.292854 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6129 12:41:02.296233 [FAST_K] Save calibration result to emmc
6130 12:41:02.299999 dramc_set_vcore_voltage set vcore to 650000
6131 12:41:02.300458 Read voltage for 400, 6
6132 12:41:02.303396 Vio18 = 0
6133 12:41:02.303852 Vcore = 650000
6134 12:41:02.304326 Vdram = 0
6135 12:41:02.306352 Vddq = 0
6136 12:41:02.306949 Vmddr = 0
6137 12:41:02.312941 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6138 12:41:02.316243 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6139 12:41:02.319452 MEM_TYPE=3, freq_sel=20
6140 12:41:02.323056 sv_algorithm_assistance_LP4_800
6141 12:41:02.325900 ============ PULL DRAM RESETB DOWN ============
6142 12:41:02.329412 ========== PULL DRAM RESETB DOWN end =========
6143 12:41:02.335807 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6144 12:41:02.339101 ===================================
6145 12:41:02.339531 LPDDR4 DRAM CONFIGURATION
6146 12:41:02.342566 ===================================
6147 12:41:02.346091 EX_ROW_EN[0] = 0x0
6148 12:41:02.349203 EX_ROW_EN[1] = 0x0
6149 12:41:02.349629 LP4Y_EN = 0x0
6150 12:41:02.352540 WORK_FSP = 0x0
6151 12:41:02.352973 WL = 0x2
6152 12:41:02.355845 RL = 0x2
6153 12:41:02.356267 BL = 0x2
6154 12:41:02.359066 RPST = 0x0
6155 12:41:02.359485 RD_PRE = 0x0
6156 12:41:02.362525 WR_PRE = 0x1
6157 12:41:02.363085 WR_PST = 0x0
6158 12:41:02.365632 DBI_WR = 0x0
6159 12:41:02.366057 DBI_RD = 0x0
6160 12:41:02.368872 OTF = 0x1
6161 12:41:02.372057 ===================================
6162 12:41:02.375586 ===================================
6163 12:41:02.376128 ANA top config
6164 12:41:02.378955 ===================================
6165 12:41:02.382646 DLL_ASYNC_EN = 0
6166 12:41:02.385514 ALL_SLAVE_EN = 1
6167 12:41:02.388613 NEW_RANK_MODE = 1
6168 12:41:02.389048 DLL_IDLE_MODE = 1
6169 12:41:02.392204 LP45_APHY_COMB_EN = 1
6170 12:41:02.395483 TX_ODT_DIS = 1
6171 12:41:02.398495 NEW_8X_MODE = 1
6172 12:41:02.402074 ===================================
6173 12:41:02.405054 ===================================
6174 12:41:02.408436 data_rate = 800
6175 12:41:02.408922 CKR = 1
6176 12:41:02.411863 DQ_P2S_RATIO = 4
6177 12:41:02.415364 ===================================
6178 12:41:02.418241 CA_P2S_RATIO = 4
6179 12:41:02.421562 DQ_CA_OPEN = 0
6180 12:41:02.424893 DQ_SEMI_OPEN = 1
6181 12:41:02.428289 CA_SEMI_OPEN = 1
6182 12:41:02.428759 CA_FULL_RATE = 0
6183 12:41:02.431715 DQ_CKDIV4_EN = 0
6184 12:41:02.434952 CA_CKDIV4_EN = 1
6185 12:41:02.438413 CA_PREDIV_EN = 0
6186 12:41:02.441123 PH8_DLY = 0
6187 12:41:02.444851 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6188 12:41:02.448381 DQ_AAMCK_DIV = 0
6189 12:41:02.448849 CA_AAMCK_DIV = 0
6190 12:41:02.451076 CA_ADMCK_DIV = 4
6191 12:41:02.454816 DQ_TRACK_CA_EN = 0
6192 12:41:02.457918 CA_PICK = 800
6193 12:41:02.461266 CA_MCKIO = 400
6194 12:41:02.464361 MCKIO_SEMI = 400
6195 12:41:02.467638 PLL_FREQ = 3016
6196 12:41:02.468067 DQ_UI_PI_RATIO = 32
6197 12:41:02.471024 CA_UI_PI_RATIO = 32
6198 12:41:02.475040 ===================================
6199 12:41:02.478222 ===================================
6200 12:41:02.480876 memory_type:LPDDR4
6201 12:41:02.484442 GP_NUM : 10
6202 12:41:02.484917 SRAM_EN : 1
6203 12:41:02.487898 MD32_EN : 0
6204 12:41:02.491201 ===================================
6205 12:41:02.493985 [ANA_INIT] >>>>>>>>>>>>>>
6206 12:41:02.494419 <<<<<< [CONFIGURE PHASE]: ANA_TX
6207 12:41:02.500863 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6208 12:41:02.504118 ===================================
6209 12:41:02.504596 data_rate = 800,PCW = 0X7400
6210 12:41:02.507941 ===================================
6211 12:41:02.510973 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6212 12:41:02.517377 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6213 12:41:02.530601 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6214 12:41:02.534095 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6215 12:41:02.536987 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6216 12:41:02.540316 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6217 12:41:02.543847 [ANA_INIT] flow start
6218 12:41:02.544304 [ANA_INIT] PLL >>>>>>>>
6219 12:41:02.547230 [ANA_INIT] PLL <<<<<<<<
6220 12:41:02.550102 [ANA_INIT] MIDPI >>>>>>>>
6221 12:41:02.550523 [ANA_INIT] MIDPI <<<<<<<<
6222 12:41:02.553417 [ANA_INIT] DLL >>>>>>>>
6223 12:41:02.556748 [ANA_INIT] flow end
6224 12:41:02.559900 ============ LP4 DIFF to SE enter ============
6225 12:41:02.563267 ============ LP4 DIFF to SE exit ============
6226 12:41:02.566729 [ANA_INIT] <<<<<<<<<<<<<
6227 12:41:02.570136 [Flow] Enable top DCM control >>>>>
6228 12:41:02.573095 [Flow] Enable top DCM control <<<<<
6229 12:41:02.576278 Enable DLL master slave shuffle
6230 12:41:02.583103 ==============================================================
6231 12:41:02.583525 Gating Mode config
6232 12:41:02.589270 ==============================================================
6233 12:41:02.589693 Config description:
6234 12:41:02.599289 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6235 12:41:02.606088 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6236 12:41:02.612404 SELPH_MODE 0: By rank 1: By Phase
6237 12:41:02.615828 ==============================================================
6238 12:41:02.619430 GAT_TRACK_EN = 0
6239 12:41:02.622625 RX_GATING_MODE = 2
6240 12:41:02.625578 RX_GATING_TRACK_MODE = 2
6241 12:41:02.629069 SELPH_MODE = 1
6242 12:41:02.632403 PICG_EARLY_EN = 1
6243 12:41:02.635994 VALID_LAT_VALUE = 1
6244 12:41:02.642274 ==============================================================
6245 12:41:02.645721 Enter into Gating configuration >>>>
6246 12:41:02.648890 Exit from Gating configuration <<<<
6247 12:41:02.652140 Enter into DVFS_PRE_config >>>>>
6248 12:41:02.662563 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6249 12:41:02.665590 Exit from DVFS_PRE_config <<<<<
6250 12:41:02.668684 Enter into PICG configuration >>>>
6251 12:41:02.672205 Exit from PICG configuration <<<<
6252 12:41:02.675588 [RX_INPUT] configuration >>>>>
6253 12:41:02.676010 [RX_INPUT] configuration <<<<<
6254 12:41:02.682088 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6255 12:41:02.688782 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6256 12:41:02.692019 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6257 12:41:02.698462 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6258 12:41:02.704882 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6259 12:41:02.711490 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6260 12:41:02.714890 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6261 12:41:02.718272 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6262 12:41:02.725092 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6263 12:41:02.728086 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6264 12:41:02.731532 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6265 12:41:02.738326 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6266 12:41:02.741047 ===================================
6267 12:41:02.741477 LPDDR4 DRAM CONFIGURATION
6268 12:41:02.744688 ===================================
6269 12:41:02.748107 EX_ROW_EN[0] = 0x0
6270 12:41:02.751403 EX_ROW_EN[1] = 0x0
6271 12:41:02.751826 LP4Y_EN = 0x0
6272 12:41:02.754799 WORK_FSP = 0x0
6273 12:41:02.755235 WL = 0x2
6274 12:41:02.757633 RL = 0x2
6275 12:41:02.758155 BL = 0x2
6276 12:41:02.761188 RPST = 0x0
6277 12:41:02.761673 RD_PRE = 0x0
6278 12:41:02.764730 WR_PRE = 0x1
6279 12:41:02.765207 WR_PST = 0x0
6280 12:41:02.768132 DBI_WR = 0x0
6281 12:41:02.768654 DBI_RD = 0x0
6282 12:41:02.770801 OTF = 0x1
6283 12:41:02.774796 ===================================
6284 12:41:02.777373 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6285 12:41:02.780746 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6286 12:41:02.787194 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6287 12:41:02.791074 ===================================
6288 12:41:02.791555 LPDDR4 DRAM CONFIGURATION
6289 12:41:02.793834 ===================================
6290 12:41:02.797268 EX_ROW_EN[0] = 0x10
6291 12:41:02.800199 EX_ROW_EN[1] = 0x0
6292 12:41:02.800787 LP4Y_EN = 0x0
6293 12:41:02.803851 WORK_FSP = 0x0
6294 12:41:02.804334 WL = 0x2
6295 12:41:02.806962 RL = 0x2
6296 12:41:02.807397 BL = 0x2
6297 12:41:02.810728 RPST = 0x0
6298 12:41:02.811340 RD_PRE = 0x0
6299 12:41:02.813896 WR_PRE = 0x1
6300 12:41:02.814419 WR_PST = 0x0
6301 12:41:02.817037 DBI_WR = 0x0
6302 12:41:02.817529 DBI_RD = 0x0
6303 12:41:02.820162 OTF = 0x1
6304 12:41:02.823522 ===================================
6305 12:41:02.830238 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6306 12:41:02.833719 nWR fixed to 30
6307 12:41:02.836556 [ModeRegInit_LP4] CH0 RK0
6308 12:41:02.836987 [ModeRegInit_LP4] CH0 RK1
6309 12:41:02.840446 [ModeRegInit_LP4] CH1 RK0
6310 12:41:02.843325 [ModeRegInit_LP4] CH1 RK1
6311 12:41:02.843744 match AC timing 19
6312 12:41:02.850096 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6313 12:41:02.853126 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6314 12:41:02.856502 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6315 12:41:02.863085 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6316 12:41:02.866225 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6317 12:41:02.866647 ==
6318 12:41:02.869648 Dram Type= 6, Freq= 0, CH_0, rank 0
6319 12:41:02.873006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6320 12:41:02.873431 ==
6321 12:41:02.880003 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6322 12:41:02.886097 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6323 12:41:02.889861 [CA 0] Center 36 (8~64) winsize 57
6324 12:41:02.892627 [CA 1] Center 36 (8~64) winsize 57
6325 12:41:02.896609 [CA 2] Center 36 (8~64) winsize 57
6326 12:41:02.899823 [CA 3] Center 36 (8~64) winsize 57
6327 12:41:02.900378 [CA 4] Center 36 (8~64) winsize 57
6328 12:41:02.902935 [CA 5] Center 36 (8~64) winsize 57
6329 12:41:02.903461
6330 12:41:02.909449 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6331 12:41:02.909875
6332 12:41:02.912648 [CATrainingPosCal] consider 1 rank data
6333 12:41:02.916098 u2DelayCellTimex100 = 270/100 ps
6334 12:41:02.919999 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6335 12:41:02.922893 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6336 12:41:02.925791 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6337 12:41:02.929107 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6338 12:41:02.932475 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6339 12:41:02.935813 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6340 12:41:02.936239
6341 12:41:02.939433 CA PerBit enable=1, Macro0, CA PI delay=36
6342 12:41:02.939855
6343 12:41:02.942670 [CBTSetCACLKResult] CA Dly = 36
6344 12:41:02.945643 CS Dly: 1 (0~32)
6345 12:41:02.946064 ==
6346 12:41:02.949196 Dram Type= 6, Freq= 0, CH_0, rank 1
6347 12:41:02.952178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 12:41:02.952622 ==
6349 12:41:02.959173 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6350 12:41:02.965823 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6351 12:41:02.969169 [CA 0] Center 36 (8~64) winsize 57
6352 12:41:02.969676 [CA 1] Center 36 (8~64) winsize 57
6353 12:41:02.972562 [CA 2] Center 36 (8~64) winsize 57
6354 12:41:02.975641 [CA 3] Center 36 (8~64) winsize 57
6355 12:41:02.978814 [CA 4] Center 36 (8~64) winsize 57
6356 12:41:02.982058 [CA 5] Center 36 (8~64) winsize 57
6357 12:41:02.982658
6358 12:41:02.985456 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6359 12:41:02.985878
6360 12:41:02.991707 [CATrainingPosCal] consider 2 rank data
6361 12:41:02.992162 u2DelayCellTimex100 = 270/100 ps
6362 12:41:02.998348 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6363 12:41:03.001614 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6364 12:41:03.005305 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6365 12:41:03.008344 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6366 12:41:03.011926 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6367 12:41:03.015059 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6368 12:41:03.015475
6369 12:41:03.018519 CA PerBit enable=1, Macro0, CA PI delay=36
6370 12:41:03.019274
6371 12:41:03.021694 [CBTSetCACLKResult] CA Dly = 36
6372 12:41:03.025108 CS Dly: 1 (0~32)
6373 12:41:03.025594
6374 12:41:03.028821 ----->DramcWriteLeveling(PI) begin...
6375 12:41:03.029393 ==
6376 12:41:03.031938 Dram Type= 6, Freq= 0, CH_0, rank 0
6377 12:41:03.035037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6378 12:41:03.035454 ==
6379 12:41:03.038397 Write leveling (Byte 0): 40 => 8
6380 12:41:03.041857 Write leveling (Byte 1): 32 => 0
6381 12:41:03.045351 DramcWriteLeveling(PI) end<-----
6382 12:41:03.045764
6383 12:41:03.046085 ==
6384 12:41:03.048189 Dram Type= 6, Freq= 0, CH_0, rank 0
6385 12:41:03.051556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6386 12:41:03.052023 ==
6387 12:41:03.055402 [Gating] SW mode calibration
6388 12:41:03.061652 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6389 12:41:03.068160 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6390 12:41:03.071780 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6391 12:41:03.074890 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6392 12:41:03.081206 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6393 12:41:03.084713 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6394 12:41:03.087870 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6395 12:41:03.094964 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6396 12:41:03.097635 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6397 12:41:03.100976 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6398 12:41:03.107872 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6399 12:41:03.108293 Total UI for P1: 0, mck2ui 16
6400 12:41:03.114655 best dqsien dly found for B0: ( 0, 14, 24)
6401 12:41:03.115070 Total UI for P1: 0, mck2ui 16
6402 12:41:03.121205 best dqsien dly found for B1: ( 0, 14, 24)
6403 12:41:03.124816 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6404 12:41:03.127526 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6405 12:41:03.127941
6406 12:41:03.130870 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6407 12:41:03.134167 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6408 12:41:03.137437 [Gating] SW calibration Done
6409 12:41:03.137853 ==
6410 12:41:03.140612 Dram Type= 6, Freq= 0, CH_0, rank 0
6411 12:41:03.144317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6412 12:41:03.144775 ==
6413 12:41:03.147727 RX Vref Scan: 0
6414 12:41:03.148172
6415 12:41:03.148499 RX Vref 0 -> 0, step: 1
6416 12:41:03.150647
6417 12:41:03.151140 RX Delay -410 -> 252, step: 16
6418 12:41:03.157173 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6419 12:41:03.160772 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6420 12:41:03.163834 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6421 12:41:03.170612 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6422 12:41:03.173426 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6423 12:41:03.177041 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6424 12:41:03.180431 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6425 12:41:03.186546 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6426 12:41:03.189969 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6427 12:41:03.193465 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6428 12:41:03.196549 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6429 12:41:03.203537 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6430 12:41:03.206737 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6431 12:41:03.210136 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6432 12:41:03.213095 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6433 12:41:03.219529 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6434 12:41:03.219962 ==
6435 12:41:03.222818 Dram Type= 6, Freq= 0, CH_0, rank 0
6436 12:41:03.226682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6437 12:41:03.227116 ==
6438 12:41:03.227461 DQS Delay:
6439 12:41:03.229402 DQS0 = 43, DQS1 = 59
6440 12:41:03.229831 DQM Delay:
6441 12:41:03.232713 DQM0 = 10, DQM1 = 12
6442 12:41:03.233144 DQ Delay:
6443 12:41:03.236224 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6444 12:41:03.239267 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6445 12:41:03.242576 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6446 12:41:03.246081 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6447 12:41:03.246511
6448 12:41:03.246852
6449 12:41:03.247170 ==
6450 12:41:03.249564 Dram Type= 6, Freq= 0, CH_0, rank 0
6451 12:41:03.252389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6452 12:41:03.255764 ==
6453 12:41:03.256243
6454 12:41:03.256666
6455 12:41:03.257010 TX Vref Scan disable
6456 12:41:03.259097 == TX Byte 0 ==
6457 12:41:03.262417 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6458 12:41:03.266182 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6459 12:41:03.269003 == TX Byte 1 ==
6460 12:41:03.273044 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6461 12:41:03.275924 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6462 12:41:03.276542 ==
6463 12:41:03.279269 Dram Type= 6, Freq= 0, CH_0, rank 0
6464 12:41:03.285687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6465 12:41:03.286376 ==
6466 12:41:03.286782
6467 12:41:03.287149
6468 12:41:03.287501 TX Vref Scan disable
6469 12:41:03.288835 == TX Byte 0 ==
6470 12:41:03.292274 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6471 12:41:03.295624 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6472 12:41:03.298660 == TX Byte 1 ==
6473 12:41:03.302190 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6474 12:41:03.305786 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6475 12:41:03.306224
6476 12:41:03.308853 [DATLAT]
6477 12:41:03.309420 Freq=400, CH0 RK0
6478 12:41:03.309778
6479 12:41:03.312003 DATLAT Default: 0xf
6480 12:41:03.312436 0, 0xFFFF, sum = 0
6481 12:41:03.315129 1, 0xFFFF, sum = 0
6482 12:41:03.315565 2, 0xFFFF, sum = 0
6483 12:41:03.318540 3, 0xFFFF, sum = 0
6484 12:41:03.319094 4, 0xFFFF, sum = 0
6485 12:41:03.322022 5, 0xFFFF, sum = 0
6486 12:41:03.322461 6, 0xFFFF, sum = 0
6487 12:41:03.325307 7, 0xFFFF, sum = 0
6488 12:41:03.328667 8, 0xFFFF, sum = 0
6489 12:41:03.329111 9, 0xFFFF, sum = 0
6490 12:41:03.331798 10, 0xFFFF, sum = 0
6491 12:41:03.332235 11, 0xFFFF, sum = 0
6492 12:41:03.334990 12, 0xFFFF, sum = 0
6493 12:41:03.335427 13, 0x0, sum = 1
6494 12:41:03.338360 14, 0x0, sum = 2
6495 12:41:03.338802 15, 0x0, sum = 3
6496 12:41:03.341492 16, 0x0, sum = 4
6497 12:41:03.341951 best_step = 14
6498 12:41:03.342292
6499 12:41:03.342613 ==
6500 12:41:03.345067 Dram Type= 6, Freq= 0, CH_0, rank 0
6501 12:41:03.348472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6502 12:41:03.348947 ==
6503 12:41:03.351480 RX Vref Scan: 1
6504 12:41:03.351907
6505 12:41:03.355127 RX Vref 0 -> 0, step: 1
6506 12:41:03.355666
6507 12:41:03.356016 RX Delay -359 -> 252, step: 8
6508 12:41:03.358373
6509 12:41:03.358805 Set Vref, RX VrefLevel [Byte0]: 59
6510 12:41:03.361798 [Byte1]: 49
6511 12:41:03.367506
6512 12:41:03.368045 Final RX Vref Byte 0 = 59 to rank0
6513 12:41:03.370336 Final RX Vref Byte 1 = 49 to rank0
6514 12:41:03.374076 Final RX Vref Byte 0 = 59 to rank1
6515 12:41:03.377512 Final RX Vref Byte 1 = 49 to rank1==
6516 12:41:03.380375 Dram Type= 6, Freq= 0, CH_0, rank 0
6517 12:41:03.387233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6518 12:41:03.387753 ==
6519 12:41:03.388101 DQS Delay:
6520 12:41:03.390163 DQS0 = 48, DQS1 = 60
6521 12:41:03.390593 DQM Delay:
6522 12:41:03.390936 DQM0 = 11, DQM1 = 12
6523 12:41:03.393707 DQ Delay:
6524 12:41:03.397186 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6525 12:41:03.400207 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6526 12:41:03.400659 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6527 12:41:03.403604 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6528 12:41:03.407066
6529 12:41:03.407589
6530 12:41:03.413730 [DQSOSCAuto] RK0, (LSB)MR18= 0xbe81, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6531 12:41:03.416440 CH0 RK0: MR19=C0C, MR18=BE81
6532 12:41:03.423275 CH0_RK0: MR19=0xC0C, MR18=0xBE81, DQSOSC=386, MR23=63, INC=396, DEC=264
6533 12:41:03.423709 ==
6534 12:41:03.426497 Dram Type= 6, Freq= 0, CH_0, rank 1
6535 12:41:03.429942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6536 12:41:03.430383 ==
6537 12:41:03.433203 [Gating] SW mode calibration
6538 12:41:03.439701 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6539 12:41:03.446445 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6540 12:41:03.449838 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6541 12:41:03.452982 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6542 12:41:03.460091 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6543 12:41:03.462847 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6544 12:41:03.466257 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6545 12:41:03.472762 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6546 12:41:03.475973 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6547 12:41:03.479565 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6548 12:41:03.485855 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6549 12:41:03.489332 Total UI for P1: 0, mck2ui 16
6550 12:41:03.492911 best dqsien dly found for B0: ( 0, 14, 24)
6551 12:41:03.493344 Total UI for P1: 0, mck2ui 16
6552 12:41:03.499075 best dqsien dly found for B1: ( 0, 14, 24)
6553 12:41:03.502407 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6554 12:41:03.505345 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6555 12:41:03.505578
6556 12:41:03.508544 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6557 12:41:03.512383 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6558 12:41:03.515270 [Gating] SW calibration Done
6559 12:41:03.515443 ==
6560 12:41:03.519055 Dram Type= 6, Freq= 0, CH_0, rank 1
6561 12:41:03.522033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6562 12:41:03.522183 ==
6563 12:41:03.525238 RX Vref Scan: 0
6564 12:41:03.525357
6565 12:41:03.528411 RX Vref 0 -> 0, step: 1
6566 12:41:03.528573
6567 12:41:03.528694 RX Delay -410 -> 252, step: 16
6568 12:41:03.535186 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6569 12:41:03.538472 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6570 12:41:03.541924 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6571 12:41:03.548497 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6572 12:41:03.551658 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6573 12:41:03.555193 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6574 12:41:03.558551 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6575 12:41:03.565003 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6576 12:41:03.568344 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6577 12:41:03.571775 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6578 12:41:03.575325 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6579 12:41:03.581382 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6580 12:41:03.585111 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6581 12:41:03.587966 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6582 12:41:03.591406 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6583 12:41:03.597966 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6584 12:41:03.598200 ==
6585 12:41:03.601465 Dram Type= 6, Freq= 0, CH_0, rank 1
6586 12:41:03.604861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6587 12:41:03.605148 ==
6588 12:41:03.605375 DQS Delay:
6589 12:41:03.608035 DQS0 = 43, DQS1 = 59
6590 12:41:03.608441 DQM Delay:
6591 12:41:03.611330 DQM0 = 11, DQM1 = 16
6592 12:41:03.611732 DQ Delay:
6593 12:41:03.615091 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6594 12:41:03.617938 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6595 12:41:03.621287 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6596 12:41:03.625052 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6597 12:41:03.625484
6598 12:41:03.625864
6599 12:41:03.626179 ==
6600 12:41:03.627871 Dram Type= 6, Freq= 0, CH_0, rank 1
6601 12:41:03.631397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6602 12:41:03.631870 ==
6603 12:41:03.632222
6604 12:41:03.634686
6605 12:41:03.635114 TX Vref Scan disable
6606 12:41:03.637705 == TX Byte 0 ==
6607 12:41:03.640847 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6608 12:41:03.644491 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6609 12:41:03.647553 == TX Byte 1 ==
6610 12:41:03.651105 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6611 12:41:03.654004 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6612 12:41:03.654439 ==
6613 12:41:03.657345 Dram Type= 6, Freq= 0, CH_0, rank 1
6614 12:41:03.661015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6615 12:41:03.664114 ==
6616 12:41:03.664576
6617 12:41:03.664943
6618 12:41:03.665260 TX Vref Scan disable
6619 12:41:03.667605 == TX Byte 0 ==
6620 12:41:03.671120 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6621 12:41:03.673910 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6622 12:41:03.677396 == TX Byte 1 ==
6623 12:41:03.680617 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6624 12:41:03.684254 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6625 12:41:03.684836
6626 12:41:03.685250 [DATLAT]
6627 12:41:03.687150 Freq=400, CH0 RK1
6628 12:41:03.687640
6629 12:41:03.690494 DATLAT Default: 0xe
6630 12:41:03.691011 0, 0xFFFF, sum = 0
6631 12:41:03.694110 1, 0xFFFF, sum = 0
6632 12:41:03.694603 2, 0xFFFF, sum = 0
6633 12:41:03.697554 3, 0xFFFF, sum = 0
6634 12:41:03.698056 4, 0xFFFF, sum = 0
6635 12:41:03.700503 5, 0xFFFF, sum = 0
6636 12:41:03.700987 6, 0xFFFF, sum = 0
6637 12:41:03.704153 7, 0xFFFF, sum = 0
6638 12:41:03.704789 8, 0xFFFF, sum = 0
6639 12:41:03.707084 9, 0xFFFF, sum = 0
6640 12:41:03.707628 10, 0xFFFF, sum = 0
6641 12:41:03.710484 11, 0xFFFF, sum = 0
6642 12:41:03.711080 12, 0xFFFF, sum = 0
6643 12:41:03.713754 13, 0x0, sum = 1
6644 12:41:03.714290 14, 0x0, sum = 2
6645 12:41:03.716683 15, 0x0, sum = 3
6646 12:41:03.717201 16, 0x0, sum = 4
6647 12:41:03.720272 best_step = 14
6648 12:41:03.720832
6649 12:41:03.721275 ==
6650 12:41:03.723593 Dram Type= 6, Freq= 0, CH_0, rank 1
6651 12:41:03.727019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6652 12:41:03.727542 ==
6653 12:41:03.730150 RX Vref Scan: 0
6654 12:41:03.730576
6655 12:41:03.731018 RX Vref 0 -> 0, step: 1
6656 12:41:03.731355
6657 12:41:03.733196 RX Delay -359 -> 252, step: 8
6658 12:41:03.741809 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6659 12:41:03.744891 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6660 12:41:03.748235 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6661 12:41:03.751652 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6662 12:41:03.758089 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6663 12:41:03.761549 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6664 12:41:03.765061 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6665 12:41:03.768269 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6666 12:41:03.774772 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6667 12:41:03.778111 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6668 12:41:03.781383 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6669 12:41:03.788190 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6670 12:41:03.791775 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6671 12:41:03.794331 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6672 12:41:03.797930 iDelay=217, Bit 14, Center -32 (-271 ~ 208) 480
6673 12:41:03.804377 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6674 12:41:03.804861 ==
6675 12:41:03.807812 Dram Type= 6, Freq= 0, CH_0, rank 1
6676 12:41:03.811225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6677 12:41:03.811674 ==
6678 12:41:03.812014 DQS Delay:
6679 12:41:03.814285 DQS0 = 44, DQS1 = 60
6680 12:41:03.814732 DQM Delay:
6681 12:41:03.817858 DQM0 = 8, DQM1 = 15
6682 12:41:03.818403 DQ Delay:
6683 12:41:03.821316 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =4
6684 12:41:03.824232 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6685 12:41:03.827581 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6686 12:41:03.831414 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6687 12:41:03.831861
6688 12:41:03.832199
6689 12:41:03.837580 [DQSOSCAuto] RK1, (LSB)MR18= 0xb843, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 386 ps
6690 12:41:03.840579 CH0 RK1: MR19=C0C, MR18=B843
6691 12:41:03.847467 CH0_RK1: MR19=0xC0C, MR18=0xB843, DQSOSC=386, MR23=63, INC=396, DEC=264
6692 12:41:03.850580 [RxdqsGatingPostProcess] freq 400
6693 12:41:03.857497 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6694 12:41:03.860343 best DQS0 dly(2T, 0.5T) = (0, 10)
6695 12:41:03.863638 best DQS1 dly(2T, 0.5T) = (0, 10)
6696 12:41:03.867061 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6697 12:41:03.870485 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6698 12:41:03.870998 best DQS0 dly(2T, 0.5T) = (0, 10)
6699 12:41:03.874233 best DQS1 dly(2T, 0.5T) = (0, 10)
6700 12:41:03.877428 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6701 12:41:03.880387 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6702 12:41:03.883760 Pre-setting of DQS Precalculation
6703 12:41:03.890254 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6704 12:41:03.890692 ==
6705 12:41:03.893604 Dram Type= 6, Freq= 0, CH_1, rank 0
6706 12:41:03.897073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6707 12:41:03.897513 ==
6708 12:41:03.903649 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6709 12:41:03.910338 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6710 12:41:03.913050 [CA 0] Center 36 (8~64) winsize 57
6711 12:41:03.916610 [CA 1] Center 36 (8~64) winsize 57
6712 12:41:03.917127 [CA 2] Center 36 (8~64) winsize 57
6713 12:41:03.919926 [CA 3] Center 36 (8~64) winsize 57
6714 12:41:03.922984 [CA 4] Center 36 (8~64) winsize 57
6715 12:41:03.926643 [CA 5] Center 36 (8~64) winsize 57
6716 12:41:03.927174
6717 12:41:03.929802 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6718 12:41:03.932677
6719 12:41:03.936625 [CATrainingPosCal] consider 1 rank data
6720 12:41:03.937053 u2DelayCellTimex100 = 270/100 ps
6721 12:41:03.942756 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6722 12:41:03.946212 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6723 12:41:03.949594 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6724 12:41:03.952998 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6725 12:41:03.956225 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6726 12:41:03.959322 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6727 12:41:03.959773
6728 12:41:03.962803 CA PerBit enable=1, Macro0, CA PI delay=36
6729 12:41:03.963231
6730 12:41:03.966263 [CBTSetCACLKResult] CA Dly = 36
6731 12:41:03.969921 CS Dly: 1 (0~32)
6732 12:41:03.970353 ==
6733 12:41:03.973030 Dram Type= 6, Freq= 0, CH_1, rank 1
6734 12:41:03.976000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 12:41:03.976435 ==
6736 12:41:03.982648 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6737 12:41:03.985686 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6738 12:41:03.989391 [CA 0] Center 36 (8~64) winsize 57
6739 12:41:03.992300 [CA 1] Center 36 (8~64) winsize 57
6740 12:41:03.995946 [CA 2] Center 36 (8~64) winsize 57
6741 12:41:03.999132 [CA 3] Center 36 (8~64) winsize 57
6742 12:41:04.002827 [CA 4] Center 36 (8~64) winsize 57
6743 12:41:04.005806 [CA 5] Center 36 (8~64) winsize 57
6744 12:41:04.006238
6745 12:41:04.009250 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6746 12:41:04.009727
6747 12:41:04.012537 [CATrainingPosCal] consider 2 rank data
6748 12:41:04.015602 u2DelayCellTimex100 = 270/100 ps
6749 12:41:04.018827 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6750 12:41:04.022553 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6751 12:41:04.028664 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6752 12:41:04.032050 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6753 12:41:04.035366 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6754 12:41:04.038562 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6755 12:41:04.038989
6756 12:41:04.042192 CA PerBit enable=1, Macro0, CA PI delay=36
6757 12:41:04.042620
6758 12:41:04.045641 [CBTSetCACLKResult] CA Dly = 36
6759 12:41:04.046072 CS Dly: 1 (0~32)
6760 12:41:04.046572
6761 12:41:04.051756 ----->DramcWriteLeveling(PI) begin...
6762 12:41:04.052189 ==
6763 12:41:04.055284 Dram Type= 6, Freq= 0, CH_1, rank 0
6764 12:41:04.058560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6765 12:41:04.058990 ==
6766 12:41:04.062269 Write leveling (Byte 0): 40 => 8
6767 12:41:04.065431 Write leveling (Byte 1): 32 => 0
6768 12:41:04.068587 DramcWriteLeveling(PI) end<-----
6769 12:41:04.069270
6770 12:41:04.069663 ==
6771 12:41:04.071456 Dram Type= 6, Freq= 0, CH_1, rank 0
6772 12:41:04.075305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6773 12:41:04.075835 ==
6774 12:41:04.078465 [Gating] SW mode calibration
6775 12:41:04.084711 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6776 12:41:04.091631 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6777 12:41:04.094758 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6778 12:41:04.098729 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6779 12:41:04.104966 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6780 12:41:04.108462 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6781 12:41:04.111805 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6782 12:41:04.118664 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6783 12:41:04.121756 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6784 12:41:04.124621 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6785 12:41:04.131499 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6786 12:41:04.131922 Total UI for P1: 0, mck2ui 16
6787 12:41:04.137966 best dqsien dly found for B0: ( 0, 14, 24)
6788 12:41:04.138391 Total UI for P1: 0, mck2ui 16
6789 12:41:04.141466 best dqsien dly found for B1: ( 0, 14, 24)
6790 12:41:04.147659 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6791 12:41:04.150867 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6792 12:41:04.151295
6793 12:41:04.154449 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6794 12:41:04.157807 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6795 12:41:04.160969 [Gating] SW calibration Done
6796 12:41:04.161395 ==
6797 12:41:04.164275 Dram Type= 6, Freq= 0, CH_1, rank 0
6798 12:41:04.167803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6799 12:41:04.168351 ==
6800 12:41:04.170793 RX Vref Scan: 0
6801 12:41:04.171373
6802 12:41:04.171729 RX Vref 0 -> 0, step: 1
6803 12:41:04.172049
6804 12:41:04.173902 RX Delay -410 -> 252, step: 16
6805 12:41:04.181125 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6806 12:41:04.183770 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6807 12:41:04.187579 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6808 12:41:04.190484 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6809 12:41:04.197056 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6810 12:41:04.200720 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6811 12:41:04.203584 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6812 12:41:04.207399 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6813 12:41:04.213887 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6814 12:41:04.216780 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6815 12:41:04.220255 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6816 12:41:04.223592 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6817 12:41:04.230164 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6818 12:41:04.233534 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6819 12:41:04.236833 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6820 12:41:04.243767 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6821 12:41:04.244190 ==
6822 12:41:04.247174 Dram Type= 6, Freq= 0, CH_1, rank 0
6823 12:41:04.249895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6824 12:41:04.250323 ==
6825 12:41:04.250702 DQS Delay:
6826 12:41:04.253401 DQS0 = 43, DQS1 = 51
6827 12:41:04.253821 DQM Delay:
6828 12:41:04.256892 DQM0 = 12, DQM1 = 14
6829 12:41:04.257352 DQ Delay:
6830 12:41:04.259965 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6831 12:41:04.263653 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6832 12:41:04.266825 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6833 12:41:04.270100 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6834 12:41:04.270523
6835 12:41:04.270860
6836 12:41:04.271169 ==
6837 12:41:04.273288 Dram Type= 6, Freq= 0, CH_1, rank 0
6838 12:41:04.276737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6839 12:41:04.277162 ==
6840 12:41:04.277499
6841 12:41:04.277865
6842 12:41:04.280033 TX Vref Scan disable
6843 12:41:04.280453 == TX Byte 0 ==
6844 12:41:04.286736 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6845 12:41:04.289767 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6846 12:41:04.290196 == TX Byte 1 ==
6847 12:41:04.296225 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6848 12:41:04.299421 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6849 12:41:04.299892 ==
6850 12:41:04.303019 Dram Type= 6, Freq= 0, CH_1, rank 0
6851 12:41:04.306173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6852 12:41:04.306778 ==
6853 12:41:04.309375
6854 12:41:04.309822
6855 12:41:04.310319 TX Vref Scan disable
6856 12:41:04.312366 == TX Byte 0 ==
6857 12:41:04.316171 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6858 12:41:04.319285 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6859 12:41:04.322686 == TX Byte 1 ==
6860 12:41:04.326414 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6861 12:41:04.329650 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6862 12:41:04.330080
6863 12:41:04.332412 [DATLAT]
6864 12:41:04.332884 Freq=400, CH1 RK0
6865 12:41:04.333227
6866 12:41:04.335881 DATLAT Default: 0xf
6867 12:41:04.336426 0, 0xFFFF, sum = 0
6868 12:41:04.338892 1, 0xFFFF, sum = 0
6869 12:41:04.339323 2, 0xFFFF, sum = 0
6870 12:41:04.342453 3, 0xFFFF, sum = 0
6871 12:41:04.342888 4, 0xFFFF, sum = 0
6872 12:41:04.345969 5, 0xFFFF, sum = 0
6873 12:41:04.346401 6, 0xFFFF, sum = 0
6874 12:41:04.348894 7, 0xFFFF, sum = 0
6875 12:41:04.349326 8, 0xFFFF, sum = 0
6876 12:41:04.352191 9, 0xFFFF, sum = 0
6877 12:41:04.352662 10, 0xFFFF, sum = 0
6878 12:41:04.355937 11, 0xFFFF, sum = 0
6879 12:41:04.356407 12, 0xFFFF, sum = 0
6880 12:41:04.358594 13, 0x0, sum = 1
6881 12:41:04.359025 14, 0x0, sum = 2
6882 12:41:04.362280 15, 0x0, sum = 3
6883 12:41:04.362714 16, 0x0, sum = 4
6884 12:41:04.365656 best_step = 14
6885 12:41:04.366096
6886 12:41:04.366471 ==
6887 12:41:04.368896 Dram Type= 6, Freq= 0, CH_1, rank 0
6888 12:41:04.372393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6889 12:41:04.372855 ==
6890 12:41:04.375622 RX Vref Scan: 1
6891 12:41:04.376047
6892 12:41:04.376382 RX Vref 0 -> 0, step: 1
6893 12:41:04.376811
6894 12:41:04.378821 RX Delay -343 -> 252, step: 8
6895 12:41:04.379250
6896 12:41:04.382034 Set Vref, RX VrefLevel [Byte0]: 52
6897 12:41:04.385404 [Byte1]: 54
6898 12:41:04.390065
6899 12:41:04.390586 Final RX Vref Byte 0 = 52 to rank0
6900 12:41:04.393782 Final RX Vref Byte 1 = 54 to rank0
6901 12:41:04.396792 Final RX Vref Byte 0 = 52 to rank1
6902 12:41:04.400034 Final RX Vref Byte 1 = 54 to rank1==
6903 12:41:04.403676 Dram Type= 6, Freq= 0, CH_1, rank 0
6904 12:41:04.409763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6905 12:41:04.410257 ==
6906 12:41:04.410607 DQS Delay:
6907 12:41:04.413274 DQS0 = 44, DQS1 = 56
6908 12:41:04.413707 DQM Delay:
6909 12:41:04.414071 DQM0 = 9, DQM1 = 14
6910 12:41:04.416474 DQ Delay:
6911 12:41:04.419674 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6912 12:41:04.420104 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =4
6913 12:41:04.423284 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6914 12:41:04.426350 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6915 12:41:04.426781
6916 12:41:04.429721
6917 12:41:04.436292 [DQSOSCAuto] RK0, (LSB)MR18= 0x956b, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6918 12:41:04.439758 CH1 RK0: MR19=C0C, MR18=956B
6919 12:41:04.446198 CH1_RK0: MR19=0xC0C, MR18=0x956B, DQSOSC=391, MR23=63, INC=386, DEC=257
6920 12:41:04.446631 ==
6921 12:41:04.449631 Dram Type= 6, Freq= 0, CH_1, rank 1
6922 12:41:04.453070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6923 12:41:04.453506 ==
6924 12:41:04.456327 [Gating] SW mode calibration
6925 12:41:04.463044 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6926 12:41:04.469364 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6927 12:41:04.472795 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6928 12:41:04.476163 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6929 12:41:04.482328 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6930 12:41:04.486009 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6931 12:41:04.489480 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6932 12:41:04.495779 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6933 12:41:04.499060 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6934 12:41:04.502126 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6935 12:41:04.508897 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6936 12:41:04.509352 Total UI for P1: 0, mck2ui 16
6937 12:41:04.515376 best dqsien dly found for B0: ( 0, 14, 24)
6938 12:41:04.515852 Total UI for P1: 0, mck2ui 16
6939 12:41:04.522219 best dqsien dly found for B1: ( 0, 14, 24)
6940 12:41:04.525411 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6941 12:41:04.528578 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6942 12:41:04.529055
6943 12:41:04.532337 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6944 12:41:04.535217 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6945 12:41:04.538700 [Gating] SW calibration Done
6946 12:41:04.539223 ==
6947 12:41:04.542099 Dram Type= 6, Freq= 0, CH_1, rank 1
6948 12:41:04.545353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6949 12:41:04.545801 ==
6950 12:41:04.548280 RX Vref Scan: 0
6951 12:41:04.548796
6952 12:41:04.549158 RX Vref 0 -> 0, step: 1
6953 12:41:04.551943
6954 12:41:04.552436 RX Delay -410 -> 252, step: 16
6955 12:41:04.558312 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6956 12:41:04.561804 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6957 12:41:04.565185 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6958 12:41:04.568437 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6959 12:41:04.575256 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6960 12:41:04.578162 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6961 12:41:04.581519 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6962 12:41:04.584845 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6963 12:41:04.591484 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6964 12:41:04.594813 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6965 12:41:04.597885 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6966 12:41:04.604843 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6967 12:41:04.607986 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6968 12:41:04.611140 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6969 12:41:04.614425 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6970 12:41:04.621273 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6971 12:41:04.621694 ==
6972 12:41:04.624680 Dram Type= 6, Freq= 0, CH_1, rank 1
6973 12:41:04.627381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6974 12:41:04.627807 ==
6975 12:41:04.628301 DQS Delay:
6976 12:41:04.631097 DQS0 = 43, DQS1 = 51
6977 12:41:04.631536 DQM Delay:
6978 12:41:04.634363 DQM0 = 12, DQM1 = 14
6979 12:41:04.634898 DQ Delay:
6980 12:41:04.637388 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6981 12:41:04.640946 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6982 12:41:04.643903 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6983 12:41:04.647393 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6984 12:41:04.647815
6985 12:41:04.648151
6986 12:41:04.648460 ==
6987 12:41:04.650836 Dram Type= 6, Freq= 0, CH_1, rank 1
6988 12:41:04.653792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6989 12:41:04.654222 ==
6990 12:41:04.654561
6991 12:41:04.654876
6992 12:41:04.657333 TX Vref Scan disable
6993 12:41:04.660898 == TX Byte 0 ==
6994 12:41:04.664246 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6995 12:41:04.667252 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6996 12:41:04.670474 == TX Byte 1 ==
6997 12:41:04.673748 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6998 12:41:04.677254 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6999 12:41:04.677677 ==
7000 12:41:04.680817 Dram Type= 6, Freq= 0, CH_1, rank 1
7001 12:41:04.683973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7002 12:41:04.684396 ==
7003 12:41:04.687033
7004 12:41:04.687456
7005 12:41:04.687787 TX Vref Scan disable
7006 12:41:04.690109 == TX Byte 0 ==
7007 12:41:04.693990 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
7008 12:41:04.697017 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
7009 12:41:04.700348 == TX Byte 1 ==
7010 12:41:04.703437 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
7011 12:41:04.706857 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
7012 12:41:04.707323
7013 12:41:04.707664 [DATLAT]
7014 12:41:04.709886 Freq=400, CH1 RK1
7015 12:41:04.710329
7016 12:41:04.713160 DATLAT Default: 0xe
7017 12:41:04.713583 0, 0xFFFF, sum = 0
7018 12:41:04.717135 1, 0xFFFF, sum = 0
7019 12:41:04.717563 2, 0xFFFF, sum = 0
7020 12:41:04.719754 3, 0xFFFF, sum = 0
7021 12:41:04.720322 4, 0xFFFF, sum = 0
7022 12:41:04.722948 5, 0xFFFF, sum = 0
7023 12:41:04.723375 6, 0xFFFF, sum = 0
7024 12:41:04.726276 7, 0xFFFF, sum = 0
7025 12:41:04.726706 8, 0xFFFF, sum = 0
7026 12:41:04.730033 9, 0xFFFF, sum = 0
7027 12:41:04.730463 10, 0xFFFF, sum = 0
7028 12:41:04.733262 11, 0xFFFF, sum = 0
7029 12:41:04.733689 12, 0xFFFF, sum = 0
7030 12:41:04.736717 13, 0x0, sum = 1
7031 12:41:04.737143 14, 0x0, sum = 2
7032 12:41:04.739483 15, 0x0, sum = 3
7033 12:41:04.740022 16, 0x0, sum = 4
7034 12:41:04.742956 best_step = 14
7035 12:41:04.743375
7036 12:41:04.743712 ==
7037 12:41:04.746752 Dram Type= 6, Freq= 0, CH_1, rank 1
7038 12:41:04.749549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7039 12:41:04.749973 ==
7040 12:41:04.753136 RX Vref Scan: 0
7041 12:41:04.753557
7042 12:41:04.753894 RX Vref 0 -> 0, step: 1
7043 12:41:04.754209
7044 12:41:04.755937 RX Delay -343 -> 252, step: 8
7045 12:41:04.764412 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
7046 12:41:04.767776 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
7047 12:41:04.770600 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
7048 12:41:04.777714 iDelay=225, Bit 3, Center -36 (-271 ~ 200) 472
7049 12:41:04.781130 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7050 12:41:04.784251 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
7051 12:41:04.787564 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7052 12:41:04.793898 iDelay=225, Bit 7, Center -36 (-279 ~ 208) 488
7053 12:41:04.797251 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7054 12:41:04.800326 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7055 12:41:04.803536 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7056 12:41:04.810623 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7057 12:41:04.813684 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7058 12:41:04.817479 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7059 12:41:04.820425 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7060 12:41:04.826877 iDelay=225, Bit 15, Center -32 (-279 ~ 216) 496
7061 12:41:04.827310 ==
7062 12:41:04.829906 Dram Type= 6, Freq= 0, CH_1, rank 1
7063 12:41:04.833172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7064 12:41:04.833440 ==
7065 12:41:04.833623 DQS Delay:
7066 12:41:04.836431 DQS0 = 44, DQS1 = 56
7067 12:41:04.836689 DQM Delay:
7068 12:41:04.839985 DQM0 = 10, DQM1 = 11
7069 12:41:04.840185 DQ Delay:
7070 12:41:04.843080 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
7071 12:41:04.846334 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
7072 12:41:04.849833 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7073 12:41:04.853401 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
7074 12:41:04.853517
7075 12:41:04.853608
7076 12:41:04.859364 [DQSOSCAuto] RK1, (LSB)MR18= 0x6050, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
7077 12:41:04.862811 CH1 RK1: MR19=C0C, MR18=6050
7078 12:41:04.869194 CH1_RK1: MR19=0xC0C, MR18=0x6050, DQSOSC=397, MR23=63, INC=374, DEC=249
7079 12:41:04.872447 [RxdqsGatingPostProcess] freq 400
7080 12:41:04.879599 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7081 12:41:04.882581 best DQS0 dly(2T, 0.5T) = (0, 10)
7082 12:41:04.886418 best DQS1 dly(2T, 0.5T) = (0, 10)
7083 12:41:04.889802 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7084 12:41:04.892869 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7085 12:41:04.892953 best DQS0 dly(2T, 0.5T) = (0, 10)
7086 12:41:04.896305 best DQS1 dly(2T, 0.5T) = (0, 10)
7087 12:41:04.899438 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7088 12:41:04.902629 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7089 12:41:04.906448 Pre-setting of DQS Precalculation
7090 12:41:04.912785 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7091 12:41:04.918882 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7092 12:41:04.925594 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7093 12:41:04.925754
7094 12:41:04.925821
7095 12:41:04.928746 [Calibration Summary] 800 Mbps
7096 12:41:04.928882 CH 0, Rank 0
7097 12:41:04.932402 SW Impedance : PASS
7098 12:41:04.935719 DUTY Scan : NO K
7099 12:41:04.935839 ZQ Calibration : PASS
7100 12:41:04.938989 Jitter Meter : NO K
7101 12:41:04.942224 CBT Training : PASS
7102 12:41:04.942344 Write leveling : PASS
7103 12:41:04.945430 RX DQS gating : PASS
7104 12:41:04.949123 RX DQ/DQS(RDDQC) : PASS
7105 12:41:04.949207 TX DQ/DQS : PASS
7106 12:41:04.951931 RX DATLAT : PASS
7107 12:41:04.955159 RX DQ/DQS(Engine): PASS
7108 12:41:04.955242 TX OE : NO K
7109 12:41:04.958434 All Pass.
7110 12:41:04.958517
7111 12:41:04.958582 CH 0, Rank 1
7112 12:41:04.962064 SW Impedance : PASS
7113 12:41:04.962146 DUTY Scan : NO K
7114 12:41:04.965897 ZQ Calibration : PASS
7115 12:41:04.968665 Jitter Meter : NO K
7116 12:41:04.968778 CBT Training : PASS
7117 12:41:04.971620 Write leveling : NO K
7118 12:41:04.975244 RX DQS gating : PASS
7119 12:41:04.975343 RX DQ/DQS(RDDQC) : PASS
7120 12:41:04.978679 TX DQ/DQS : PASS
7121 12:41:04.981626 RX DATLAT : PASS
7122 12:41:04.981712 RX DQ/DQS(Engine): PASS
7123 12:41:04.984795 TX OE : NO K
7124 12:41:04.984890 All Pass.
7125 12:41:04.984965
7126 12:41:04.988464 CH 1, Rank 0
7127 12:41:04.988589 SW Impedance : PASS
7128 12:41:04.991704 DUTY Scan : NO K
7129 12:41:04.994727 ZQ Calibration : PASS
7130 12:41:04.994847 Jitter Meter : NO K
7131 12:41:04.998074 CBT Training : PASS
7132 12:41:04.998197 Write leveling : PASS
7133 12:41:05.001748 RX DQS gating : PASS
7134 12:41:05.004891 RX DQ/DQS(RDDQC) : PASS
7135 12:41:05.005026 TX DQ/DQS : PASS
7136 12:41:05.007932 RX DATLAT : PASS
7137 12:41:05.011284 RX DQ/DQS(Engine): PASS
7138 12:41:05.011437 TX OE : NO K
7139 12:41:05.015101 All Pass.
7140 12:41:05.015274
7141 12:41:05.015411 CH 1, Rank 1
7142 12:41:05.018151 SW Impedance : PASS
7143 12:41:05.018353 DUTY Scan : NO K
7144 12:41:05.021286 ZQ Calibration : PASS
7145 12:41:05.024712 Jitter Meter : NO K
7146 12:41:05.025018 CBT Training : PASS
7147 12:41:05.027809 Write leveling : NO K
7148 12:41:05.031198 RX DQS gating : PASS
7149 12:41:05.031498 RX DQ/DQS(RDDQC) : PASS
7150 12:41:05.034689 TX DQ/DQS : PASS
7151 12:41:05.037904 RX DATLAT : PASS
7152 12:41:05.038331 RX DQ/DQS(Engine): PASS
7153 12:41:05.041524 TX OE : NO K
7154 12:41:05.041950 All Pass.
7155 12:41:05.042285
7156 12:41:05.044287 DramC Write-DBI off
7157 12:41:05.047643 PER_BANK_REFRESH: Hybrid Mode
7158 12:41:05.048079 TX_TRACKING: ON
7159 12:41:05.057908 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7160 12:41:05.061040 [FAST_K] Save calibration result to emmc
7161 12:41:05.064168 dramc_set_vcore_voltage set vcore to 725000
7162 12:41:05.067475 Read voltage for 1600, 0
7163 12:41:05.067896 Vio18 = 0
7164 12:41:05.068232 Vcore = 725000
7165 12:41:05.070992 Vdram = 0
7166 12:41:05.071414 Vddq = 0
7167 12:41:05.071748 Vmddr = 0
7168 12:41:05.077500 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7169 12:41:05.080883 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7170 12:41:05.084701 MEM_TYPE=3, freq_sel=13
7171 12:41:05.087703 sv_algorithm_assistance_LP4_3733
7172 12:41:05.090928 ============ PULL DRAM RESETB DOWN ============
7173 12:41:05.097624 ========== PULL DRAM RESETB DOWN end =========
7174 12:41:05.100974 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7175 12:41:05.104257 ===================================
7176 12:41:05.107342 LPDDR4 DRAM CONFIGURATION
7177 12:41:05.110644 ===================================
7178 12:41:05.111068 EX_ROW_EN[0] = 0x0
7179 12:41:05.113809 EX_ROW_EN[1] = 0x0
7180 12:41:05.114256 LP4Y_EN = 0x0
7181 12:41:05.117117 WORK_FSP = 0x1
7182 12:41:05.117536 WL = 0x5
7183 12:41:05.120605 RL = 0x5
7184 12:41:05.121026 BL = 0x2
7185 12:41:05.123796 RPST = 0x0
7186 12:41:05.124223 RD_PRE = 0x0
7187 12:41:05.127283 WR_PRE = 0x1
7188 12:41:05.130720 WR_PST = 0x1
7189 12:41:05.131141 DBI_WR = 0x0
7190 12:41:05.133681 DBI_RD = 0x0
7191 12:41:05.134112 OTF = 0x1
7192 12:41:05.137331 ===================================
7193 12:41:05.140339 ===================================
7194 12:41:05.140847 ANA top config
7195 12:41:05.143514 ===================================
7196 12:41:05.147286 DLL_ASYNC_EN = 0
7197 12:41:05.150602 ALL_SLAVE_EN = 0
7198 12:41:05.153810 NEW_RANK_MODE = 1
7199 12:41:05.157026 DLL_IDLE_MODE = 1
7200 12:41:05.157456 LP45_APHY_COMB_EN = 1
7201 12:41:05.160118 TX_ODT_DIS = 0
7202 12:41:05.163441 NEW_8X_MODE = 1
7203 12:41:05.166781 ===================================
7204 12:41:05.170118 ===================================
7205 12:41:05.173398 data_rate = 3200
7206 12:41:05.176598 CKR = 1
7207 12:41:05.180443 DQ_P2S_RATIO = 8
7208 12:41:05.180970 ===================================
7209 12:41:05.183624 CA_P2S_RATIO = 8
7210 12:41:05.187576 DQ_CA_OPEN = 0
7211 12:41:05.189891 DQ_SEMI_OPEN = 0
7212 12:41:05.193616 CA_SEMI_OPEN = 0
7213 12:41:05.196684 CA_FULL_RATE = 0
7214 12:41:05.197114 DQ_CKDIV4_EN = 0
7215 12:41:05.199935 CA_CKDIV4_EN = 0
7216 12:41:05.203206 CA_PREDIV_EN = 0
7217 12:41:05.206838 PH8_DLY = 12
7218 12:41:05.209775 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7219 12:41:05.213290 DQ_AAMCK_DIV = 4
7220 12:41:05.216234 CA_AAMCK_DIV = 4
7221 12:41:05.216730 CA_ADMCK_DIV = 4
7222 12:41:05.219876 DQ_TRACK_CA_EN = 0
7223 12:41:05.222797 CA_PICK = 1600
7224 12:41:05.226486 CA_MCKIO = 1600
7225 12:41:05.229483 MCKIO_SEMI = 0
7226 12:41:05.233223 PLL_FREQ = 3068
7227 12:41:05.236296 DQ_UI_PI_RATIO = 32
7228 12:41:05.236761 CA_UI_PI_RATIO = 0
7229 12:41:05.239665 ===================================
7230 12:41:05.242889 ===================================
7231 12:41:05.245811 memory_type:LPDDR4
7232 12:41:05.249378 GP_NUM : 10
7233 12:41:05.249803 SRAM_EN : 1
7234 12:41:05.252728 MD32_EN : 0
7235 12:41:05.255536 ===================================
7236 12:41:05.259191 [ANA_INIT] >>>>>>>>>>>>>>
7237 12:41:05.262133 <<<<<< [CONFIGURE PHASE]: ANA_TX
7238 12:41:05.265398 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7239 12:41:05.269346 ===================================
7240 12:41:05.272110 data_rate = 3200,PCW = 0X7600
7241 12:41:05.275957 ===================================
7242 12:41:05.279097 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7243 12:41:05.281881 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7244 12:41:05.288941 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7245 12:41:05.291813 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7246 12:41:05.295207 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7247 12:41:05.298670 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7248 12:41:05.302006 [ANA_INIT] flow start
7249 12:41:05.305158 [ANA_INIT] PLL >>>>>>>>
7250 12:41:05.305589 [ANA_INIT] PLL <<<<<<<<
7251 12:41:05.308290 [ANA_INIT] MIDPI >>>>>>>>
7252 12:41:05.311932 [ANA_INIT] MIDPI <<<<<<<<
7253 12:41:05.314937 [ANA_INIT] DLL >>>>>>>>
7254 12:41:05.315440 [ANA_INIT] DLL <<<<<<<<
7255 12:41:05.318592 [ANA_INIT] flow end
7256 12:41:05.321939 ============ LP4 DIFF to SE enter ============
7257 12:41:05.324772 ============ LP4 DIFF to SE exit ============
7258 12:41:05.328468 [ANA_INIT] <<<<<<<<<<<<<
7259 12:41:05.331674 [Flow] Enable top DCM control >>>>>
7260 12:41:05.334966 [Flow] Enable top DCM control <<<<<
7261 12:41:05.338252 Enable DLL master slave shuffle
7262 12:41:05.345022 ==============================================================
7263 12:41:05.345457 Gating Mode config
7264 12:41:05.351329 ==============================================================
7265 12:41:05.351784 Config description:
7266 12:41:05.361427 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7267 12:41:05.367861 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7268 12:41:05.374699 SELPH_MODE 0: By rank 1: By Phase
7269 12:41:05.377994 ==============================================================
7270 12:41:05.380947 GAT_TRACK_EN = 1
7271 12:41:05.384932 RX_GATING_MODE = 2
7272 12:41:05.388126 RX_GATING_TRACK_MODE = 2
7273 12:41:05.391551 SELPH_MODE = 1
7274 12:41:05.394750 PICG_EARLY_EN = 1
7275 12:41:05.397948 VALID_LAT_VALUE = 1
7276 12:41:05.404377 ==============================================================
7277 12:41:05.407790 Enter into Gating configuration >>>>
7278 12:41:05.410701 Exit from Gating configuration <<<<
7279 12:41:05.414100 Enter into DVFS_PRE_config >>>>>
7280 12:41:05.424347 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7281 12:41:05.427856 Exit from DVFS_PRE_config <<<<<
7282 12:41:05.431136 Enter into PICG configuration >>>>
7283 12:41:05.434103 Exit from PICG configuration <<<<
7284 12:41:05.437678 [RX_INPUT] configuration >>>>>
7285 12:41:05.438105 [RX_INPUT] configuration <<<<<
7286 12:41:05.444325 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7287 12:41:05.450712 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7288 12:41:05.453741 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7289 12:41:05.460554 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7290 12:41:05.467153 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7291 12:41:05.473525 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7292 12:41:05.476836 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7293 12:41:05.480500 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7294 12:41:05.486942 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7295 12:41:05.489991 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7296 12:41:05.493191 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7297 12:41:05.499883 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7298 12:41:05.503248 ===================================
7299 12:41:05.503895 LPDDR4 DRAM CONFIGURATION
7300 12:41:05.506134 ===================================
7301 12:41:05.509500 EX_ROW_EN[0] = 0x0
7302 12:41:05.513282 EX_ROW_EN[1] = 0x0
7303 12:41:05.513712 LP4Y_EN = 0x0
7304 12:41:05.516594 WORK_FSP = 0x1
7305 12:41:05.517046 WL = 0x5
7306 12:41:05.519834 RL = 0x5
7307 12:41:05.520283 BL = 0x2
7308 12:41:05.523343 RPST = 0x0
7309 12:41:05.523792 RD_PRE = 0x0
7310 12:41:05.526331 WR_PRE = 0x1
7311 12:41:05.526798 WR_PST = 0x1
7312 12:41:05.529286 DBI_WR = 0x0
7313 12:41:05.529715 DBI_RD = 0x0
7314 12:41:05.532913 OTF = 0x1
7315 12:41:05.536235 ===================================
7316 12:41:05.539470 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7317 12:41:05.542994 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7318 12:41:05.549382 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7319 12:41:05.552634 ===================================
7320 12:41:05.553089 LPDDR4 DRAM CONFIGURATION
7321 12:41:05.555672 ===================================
7322 12:41:05.559234 EX_ROW_EN[0] = 0x10
7323 12:41:05.562305 EX_ROW_EN[1] = 0x0
7324 12:41:05.562804 LP4Y_EN = 0x0
7325 12:41:05.565897 WORK_FSP = 0x1
7326 12:41:05.566485 WL = 0x5
7327 12:41:05.569434 RL = 0x5
7328 12:41:05.569933 BL = 0x2
7329 12:41:05.572498 RPST = 0x0
7330 12:41:05.572967 RD_PRE = 0x0
7331 12:41:05.575461 WR_PRE = 0x1
7332 12:41:05.575976 WR_PST = 0x1
7333 12:41:05.578677 DBI_WR = 0x0
7334 12:41:05.579096 DBI_RD = 0x0
7335 12:41:05.582251 OTF = 0x1
7336 12:41:05.585181 ===================================
7337 12:41:05.591725 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7338 12:41:05.592164 ==
7339 12:41:05.595612 Dram Type= 6, Freq= 0, CH_0, rank 0
7340 12:41:05.598574 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7341 12:41:05.599014 ==
7342 12:41:05.602150 [Duty_Offset_Calibration]
7343 12:41:05.602588 B0:1 B1:-1 CA:0
7344 12:41:05.603025
7345 12:41:05.605353 [DutyScan_Calibration_Flow] k_type=0
7346 12:41:05.616316
7347 12:41:05.616771 ==CLK 0==
7348 12:41:05.619578 Final CLK duty delay cell = 0
7349 12:41:05.623066 [0] MAX Duty = 5125%(X100), DQS PI = 20
7350 12:41:05.626456 [0] MIN Duty = 4907%(X100), DQS PI = 6
7351 12:41:05.629418 [0] AVG Duty = 5016%(X100)
7352 12:41:05.629850
7353 12:41:05.633421 CH0 CLK Duty spec in!! Max-Min= 218%
7354 12:41:05.636536 [DutyScan_Calibration_Flow] ====Done====
7355 12:41:05.637013
7356 12:41:05.639452 [DutyScan_Calibration_Flow] k_type=1
7357 12:41:05.655691
7358 12:41:05.656159 ==DQS 0 ==
7359 12:41:05.658853 Final DQS duty delay cell = -4
7360 12:41:05.662071 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7361 12:41:05.665631 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7362 12:41:05.668978 [-4] AVG Duty = 4922%(X100)
7363 12:41:05.669416
7364 12:41:05.669746 ==DQS 1 ==
7365 12:41:05.672303 Final DQS duty delay cell = 0
7366 12:41:05.675521 [0] MAX Duty = 5156%(X100), DQS PI = 2
7367 12:41:05.678727 [0] MIN Duty = 5031%(X100), DQS PI = 18
7368 12:41:05.681932 [0] AVG Duty = 5093%(X100)
7369 12:41:05.682354
7370 12:41:05.685672 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7371 12:41:05.685966
7372 12:41:05.688538 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7373 12:41:05.691949 [DutyScan_Calibration_Flow] ====Done====
7374 12:41:05.692356
7375 12:41:05.694991 [DutyScan_Calibration_Flow] k_type=3
7376 12:41:05.712951
7377 12:41:05.713250 ==DQM 0 ==
7378 12:41:05.716278 Final DQM duty delay cell = 0
7379 12:41:05.719450 [0] MAX Duty = 5093%(X100), DQS PI = 20
7380 12:41:05.722626 [0] MIN Duty = 4876%(X100), DQS PI = 10
7381 12:41:05.726036 [0] AVG Duty = 4984%(X100)
7382 12:41:05.726453
7383 12:41:05.726803 ==DQM 1 ==
7384 12:41:05.729574 Final DQM duty delay cell = 0
7385 12:41:05.733059 [0] MAX Duty = 5000%(X100), DQS PI = 4
7386 12:41:05.736197 [0] MIN Duty = 4813%(X100), DQS PI = 20
7387 12:41:05.739433 [0] AVG Duty = 4906%(X100)
7388 12:41:05.739902
7389 12:41:05.742900 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7390 12:41:05.743384
7391 12:41:05.745837 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7392 12:41:05.749628 [DutyScan_Calibration_Flow] ====Done====
7393 12:41:05.750050
7394 12:41:05.752332 [DutyScan_Calibration_Flow] k_type=2
7395 12:41:05.769204
7396 12:41:05.769754 ==DQ 0 ==
7397 12:41:05.772674 Final DQ duty delay cell = -4
7398 12:41:05.776076 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7399 12:41:05.779150 [-4] MIN Duty = 4876%(X100), DQS PI = 54
7400 12:41:05.782381 [-4] AVG Duty = 4953%(X100)
7401 12:41:05.782861
7402 12:41:05.783202 ==DQ 1 ==
7403 12:41:05.786268 Final DQ duty delay cell = 0
7404 12:41:05.789387 [0] MAX Duty = 5125%(X100), DQS PI = 2
7405 12:41:05.792708 [0] MIN Duty = 4969%(X100), DQS PI = 38
7406 12:41:05.795510 [0] AVG Duty = 5047%(X100)
7407 12:41:05.795957
7408 12:41:05.798926 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7409 12:41:05.799348
7410 12:41:05.802092 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7411 12:41:05.805412 [DutyScan_Calibration_Flow] ====Done====
7412 12:41:05.805833 ==
7413 12:41:05.808843 Dram Type= 6, Freq= 0, CH_1, rank 0
7414 12:41:05.812171 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7415 12:41:05.812671 ==
7416 12:41:05.815306 [Duty_Offset_Calibration]
7417 12:41:05.815725 B0:-1 B1:1 CA:2
7418 12:41:05.816110
7419 12:41:05.818900 [DutyScan_Calibration_Flow] k_type=0
7420 12:41:05.830133
7421 12:41:05.830552 ==CLK 0==
7422 12:41:05.833270 Final CLK duty delay cell = 0
7423 12:41:05.836781 [0] MAX Duty = 5187%(X100), DQS PI = 24
7424 12:41:05.840026 [0] MIN Duty = 5000%(X100), DQS PI = 0
7425 12:41:05.840676 [0] AVG Duty = 5093%(X100)
7426 12:41:05.843318
7427 12:41:05.846598 CH1 CLK Duty spec in!! Max-Min= 187%
7428 12:41:05.849941 [DutyScan_Calibration_Flow] ====Done====
7429 12:41:05.850611
7430 12:41:05.853215 [DutyScan_Calibration_Flow] k_type=1
7431 12:41:05.869958
7432 12:41:05.870423 ==DQS 0 ==
7433 12:41:05.873224 Final DQS duty delay cell = 0
7434 12:41:05.876403 [0] MAX Duty = 5156%(X100), DQS PI = 18
7435 12:41:05.879379 [0] MIN Duty = 4907%(X100), DQS PI = 10
7436 12:41:05.882797 [0] AVG Duty = 5031%(X100)
7437 12:41:05.883223
7438 12:41:05.883560 ==DQS 1 ==
7439 12:41:05.886145 Final DQS duty delay cell = 0
7440 12:41:05.889429 [0] MAX Duty = 5093%(X100), DQS PI = 26
7441 12:41:05.892823 [0] MIN Duty = 4969%(X100), DQS PI = 56
7442 12:41:05.896177 [0] AVG Duty = 5031%(X100)
7443 12:41:05.896633
7444 12:41:05.899277 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7445 12:41:05.899708
7446 12:41:05.902676 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7447 12:41:05.906428 [DutyScan_Calibration_Flow] ====Done====
7448 12:41:05.906861
7449 12:41:05.909413 [DutyScan_Calibration_Flow] k_type=3
7450 12:41:05.925825
7451 12:41:05.926254 ==DQM 0 ==
7452 12:41:05.929799 Final DQM duty delay cell = -4
7453 12:41:05.932476 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7454 12:41:05.935733 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7455 12:41:05.939176 [-4] AVG Duty = 4937%(X100)
7456 12:41:05.939596
7457 12:41:05.939931 ==DQM 1 ==
7458 12:41:05.942444 Final DQM duty delay cell = 0
7459 12:41:05.945734 [0] MAX Duty = 5156%(X100), DQS PI = 2
7460 12:41:05.949201 [0] MIN Duty = 4969%(X100), DQS PI = 32
7461 12:41:05.953051 [0] AVG Duty = 5062%(X100)
7462 12:41:05.953527
7463 12:41:05.955229 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7464 12:41:05.955708
7465 12:41:05.959115 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7466 12:41:05.962423 [DutyScan_Calibration_Flow] ====Done====
7467 12:41:05.962921
7468 12:41:05.965246 [DutyScan_Calibration_Flow] k_type=2
7469 12:41:05.983095
7470 12:41:05.983617 ==DQ 0 ==
7471 12:41:05.986482 Final DQ duty delay cell = 0
7472 12:41:05.989527 [0] MAX Duty = 5187%(X100), DQS PI = 32
7473 12:41:05.993329 [0] MIN Duty = 4906%(X100), DQS PI = 10
7474 12:41:05.993754 [0] AVG Duty = 5046%(X100)
7475 12:41:05.996221
7476 12:41:05.996823 ==DQ 1 ==
7477 12:41:05.999530 Final DQ duty delay cell = 0
7478 12:41:06.002865 [0] MAX Duty = 5156%(X100), DQS PI = 8
7479 12:41:06.006286 [0] MIN Duty = 4969%(X100), DQS PI = 56
7480 12:41:06.006713 [0] AVG Duty = 5062%(X100)
7481 12:41:06.007048
7482 12:41:06.009452 CH1 DQ 0 Duty spec in!! Max-Min= 281%
7483 12:41:06.009874
7484 12:41:06.016003 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7485 12:41:06.019301 [DutyScan_Calibration_Flow] ====Done====
7486 12:41:06.022910 nWR fixed to 30
7487 12:41:06.023335 [ModeRegInit_LP4] CH0 RK0
7488 12:41:06.026177 [ModeRegInit_LP4] CH0 RK1
7489 12:41:06.029562 [ModeRegInit_LP4] CH1 RK0
7490 12:41:06.032482 [ModeRegInit_LP4] CH1 RK1
7491 12:41:06.032953 match AC timing 5
7492 12:41:06.035973 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7493 12:41:06.042584 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7494 12:41:06.045681 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7495 12:41:06.052384 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7496 12:41:06.055786 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7497 12:41:06.056219 [MiockJmeterHQA]
7498 12:41:06.056741
7499 12:41:06.059110 [DramcMiockJmeter] u1RxGatingPI = 0
7500 12:41:06.062083 0 : 4252, 4027
7501 12:41:06.062544 4 : 4253, 4026
7502 12:41:06.065424 8 : 4363, 4137
7503 12:41:06.065862 12 : 4363, 4137
7504 12:41:06.066393 16 : 4363, 4137
7505 12:41:06.068764 20 : 4253, 4027
7506 12:41:06.069268 24 : 4252, 4026
7507 12:41:06.071900 28 : 4252, 4027
7508 12:41:06.072506 32 : 4361, 4137
7509 12:41:06.075367 36 : 4253, 4026
7510 12:41:06.075872 40 : 4360, 4138
7511 12:41:06.078511 44 : 4250, 4026
7512 12:41:06.078951 48 : 4250, 4027
7513 12:41:06.079440 52 : 4249, 4027
7514 12:41:06.081776 56 : 4253, 4029
7515 12:41:06.082291 60 : 4250, 4027
7516 12:41:06.085653 64 : 4250, 4026
7517 12:41:06.086092 68 : 4363, 4140
7518 12:41:06.088425 72 : 4249, 4027
7519 12:41:06.088921 76 : 4253, 4029
7520 12:41:06.091884 80 : 4250, 4027
7521 12:41:06.092329 84 : 4361, 4137
7522 12:41:06.092794 88 : 4250, 4026
7523 12:41:06.095026 92 : 4360, 1092
7524 12:41:06.095532 96 : 4250, 0
7525 12:41:06.098606 100 : 4252, 0
7526 12:41:06.099112 104 : 4250, 0
7527 12:41:06.099469 108 : 4253, 0
7528 12:41:06.102004 112 : 4250, 0
7529 12:41:06.102503 116 : 4361, 0
7530 12:41:06.105027 120 : 4361, 0
7531 12:41:06.105477 124 : 4250, 0
7532 12:41:06.105955 128 : 4360, 0
7533 12:41:06.108169 132 : 4249, 0
7534 12:41:06.108694 136 : 4250, 0
7535 12:41:06.111514 140 : 4250, 0
7536 12:41:06.112010 144 : 4250, 0
7537 12:41:06.112443 148 : 4252, 0
7538 12:41:06.115096 152 : 4361, 0
7539 12:41:06.115589 156 : 4250, 0
7540 12:41:06.118306 160 : 4250, 0
7541 12:41:06.118806 164 : 4250, 0
7542 12:41:06.119232 168 : 4361, 0
7543 12:41:06.121662 172 : 4361, 0
7544 12:41:06.122110 176 : 4250, 0
7545 12:41:06.124863 180 : 4249, 0
7546 12:41:06.125355 184 : 4250, 0
7547 12:41:06.125844 188 : 4252, 0
7548 12:41:06.128148 192 : 4250, 0
7549 12:41:06.128661 196 : 4250, 0
7550 12:41:06.129115 200 : 4252, 0
7551 12:41:06.131529 204 : 4250, 0
7552 12:41:06.132018 208 : 4250, 0
7553 12:41:06.134833 212 : 4253, 0
7554 12:41:06.135280 216 : 4361, 0
7555 12:41:06.135766 220 : 4360, 0
7556 12:41:06.138064 224 : 4363, 126
7557 12:41:06.138562 228 : 4249, 3202
7558 12:41:06.141618 232 : 4361, 4137
7559 12:41:06.142118 236 : 4250, 4026
7560 12:41:06.144878 240 : 4250, 4027
7561 12:41:06.145381 244 : 4360, 4137
7562 12:41:06.147989 248 : 4360, 4137
7563 12:41:06.148421 252 : 4250, 4026
7564 12:41:06.152033 256 : 4363, 4140
7565 12:41:06.152553 260 : 4361, 4137
7566 12:41:06.154547 264 : 4250, 4027
7567 12:41:06.154996 268 : 4250, 4026
7568 12:41:06.157605 272 : 4253, 4029
7569 12:41:06.158091 276 : 4250, 4027
7570 12:41:06.160964 280 : 4250, 4027
7571 12:41:06.161488 284 : 4250, 4026
7572 12:41:06.161853 288 : 4250, 4026
7573 12:41:06.164310 292 : 4250, 4027
7574 12:41:06.164895 296 : 4361, 4137
7575 12:41:06.167446 300 : 4361, 4137
7576 12:41:06.168065 304 : 4250, 4026
7577 12:41:06.171526 308 : 4363, 4140
7578 12:41:06.171956 312 : 4361, 4137
7579 12:41:06.174108 316 : 4249, 4027
7580 12:41:06.174560 320 : 4250, 4026
7581 12:41:06.177295 324 : 4253, 4029
7582 12:41:06.177750 328 : 4250, 4027
7583 12:41:06.180954 332 : 4250, 4027
7584 12:41:06.181384 336 : 4250, 3986
7585 12:41:06.184121 340 : 4253, 2433
7586 12:41:06.184601 344 : 4250, 168
7587 12:41:06.184951
7588 12:41:06.187563 MIOCK jitter meter ch=0
7589 12:41:06.187980
7590 12:41:06.190646 1T = (344-92) = 252 dly cells
7591 12:41:06.194066 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7592 12:41:06.194490 ==
7593 12:41:06.197528 Dram Type= 6, Freq= 0, CH_0, rank 0
7594 12:41:06.203882 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7595 12:41:06.204410 ==
7596 12:41:06.207226 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7597 12:41:06.213585 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7598 12:41:06.217393 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7599 12:41:06.223639 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7600 12:41:06.231318 [CA 0] Center 43 (13~74) winsize 62
7601 12:41:06.234774 [CA 1] Center 43 (13~74) winsize 62
7602 12:41:06.238411 [CA 2] Center 39 (10~68) winsize 59
7603 12:41:06.241340 [CA 3] Center 38 (9~68) winsize 60
7604 12:41:06.244713 [CA 4] Center 37 (8~66) winsize 59
7605 12:41:06.247891 [CA 5] Center 36 (7~66) winsize 60
7606 12:41:06.248312
7607 12:41:06.251116 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7608 12:41:06.251536
7609 12:41:06.257741 [CATrainingPosCal] consider 1 rank data
7610 12:41:06.258181 u2DelayCellTimex100 = 258/100 ps
7611 12:41:06.264218 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7612 12:41:06.267641 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7613 12:41:06.271206 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7614 12:41:06.274539 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7615 12:41:06.277681 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7616 12:41:06.280836 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7617 12:41:06.281262
7618 12:41:06.284071 CA PerBit enable=1, Macro0, CA PI delay=36
7619 12:41:06.284582
7620 12:41:06.287741 [CBTSetCACLKResult] CA Dly = 36
7621 12:41:06.290723 CS Dly: 11 (0~42)
7622 12:41:06.293911 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7623 12:41:06.297183 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7624 12:41:06.297606 ==
7625 12:41:06.300722 Dram Type= 6, Freq= 0, CH_0, rank 1
7626 12:41:06.306962 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7627 12:41:06.307424 ==
7628 12:41:06.310560 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7629 12:41:06.316830 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7630 12:41:06.320234 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7631 12:41:06.327072 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7632 12:41:06.335122 [CA 0] Center 43 (13~74) winsize 62
7633 12:41:06.338487 [CA 1] Center 44 (14~74) winsize 61
7634 12:41:06.341905 [CA 2] Center 38 (9~68) winsize 60
7635 12:41:06.344734 [CA 3] Center 38 (9~68) winsize 60
7636 12:41:06.348574 [CA 4] Center 36 (7~66) winsize 60
7637 12:41:06.351435 [CA 5] Center 36 (7~66) winsize 60
7638 12:41:06.351882
7639 12:41:06.354652 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7640 12:41:06.355085
7641 12:41:06.361795 [CATrainingPosCal] consider 2 rank data
7642 12:41:06.362258 u2DelayCellTimex100 = 258/100 ps
7643 12:41:06.368371 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7644 12:41:06.371095 CA1 delay=44 (14~74),Diff = 8 PI (30 cell)
7645 12:41:06.374479 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7646 12:41:06.378082 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7647 12:41:06.381620 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7648 12:41:06.384786 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7649 12:41:06.385233
7650 12:41:06.387967 CA PerBit enable=1, Macro0, CA PI delay=36
7651 12:41:06.388425
7652 12:41:06.391300 [CBTSetCACLKResult] CA Dly = 36
7653 12:41:06.394505 CS Dly: 12 (0~44)
7654 12:41:06.397764 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7655 12:41:06.401068 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7656 12:41:06.401516
7657 12:41:06.404415 ----->DramcWriteLeveling(PI) begin...
7658 12:41:06.404975 ==
7659 12:41:06.407674 Dram Type= 6, Freq= 0, CH_0, rank 0
7660 12:41:06.414533 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7661 12:41:06.415050 ==
7662 12:41:06.417837 Write leveling (Byte 0): 35 => 35
7663 12:41:06.420903 Write leveling (Byte 1): 27 => 27
7664 12:41:06.421365 DramcWriteLeveling(PI) end<-----
7665 12:41:06.424379
7666 12:41:06.424882 ==
7667 12:41:06.427474 Dram Type= 6, Freq= 0, CH_0, rank 0
7668 12:41:06.431421 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7669 12:41:06.431892 ==
7670 12:41:06.434436 [Gating] SW mode calibration
7671 12:41:06.440833 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7672 12:41:06.444195 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7673 12:41:06.450944 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7674 12:41:06.454209 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7675 12:41:06.460424 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7676 12:41:06.463912 1 4 12 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7677 12:41:06.467279 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7678 12:41:06.470712 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7679 12:41:06.477195 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7680 12:41:06.480282 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7681 12:41:06.483776 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7682 12:41:06.489939 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7683 12:41:06.493262 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7684 12:41:06.500223 1 5 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
7685 12:41:06.503415 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7686 12:41:06.506811 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7687 12:41:06.509713 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
7688 12:41:06.516246 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7689 12:41:06.520122 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7690 12:41:06.523276 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7691 12:41:06.529943 1 6 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7692 12:41:06.533022 1 6 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
7693 12:41:06.536292 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7694 12:41:06.543037 1 6 20 | B1->B0 | 2c2c 4646 | 1 0 | (0 0) (0 0)
7695 12:41:06.546459 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7696 12:41:06.549947 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7697 12:41:06.556379 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7698 12:41:06.559619 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7699 12:41:06.562710 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7700 12:41:06.569405 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7701 12:41:06.572734 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7702 12:41:06.576470 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7703 12:41:06.582841 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7704 12:41:06.585776 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7705 12:41:06.589105 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7706 12:41:06.595698 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7707 12:41:06.598991 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7708 12:41:06.602629 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7709 12:41:06.608681 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7710 12:41:06.611925 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7711 12:41:06.615494 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7712 12:41:06.621872 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7713 12:41:06.625878 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7714 12:41:06.628788 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7715 12:41:06.635644 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7716 12:41:06.638655 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7717 12:41:06.641674 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7718 12:41:06.645362 Total UI for P1: 0, mck2ui 16
7719 12:41:06.648237 best dqsien dly found for B0: ( 1, 9, 10)
7720 12:41:06.655278 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7721 12:41:06.658464 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7722 12:41:06.661508 Total UI for P1: 0, mck2ui 16
7723 12:41:06.664619 best dqsien dly found for B1: ( 1, 9, 18)
7724 12:41:06.668131 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7725 12:41:06.671486 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7726 12:41:06.671928
7727 12:41:06.674733 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7728 12:41:06.681073 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7729 12:41:06.681513 [Gating] SW calibration Done
7730 12:41:06.684853 ==
7731 12:41:06.685306 Dram Type= 6, Freq= 0, CH_0, rank 0
7732 12:41:06.691023 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7733 12:41:06.691454 ==
7734 12:41:06.691810 RX Vref Scan: 0
7735 12:41:06.692128
7736 12:41:06.694448 RX Vref 0 -> 0, step: 1
7737 12:41:06.694972
7738 12:41:06.697936 RX Delay 0 -> 252, step: 8
7739 12:41:06.701192 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7740 12:41:06.704392 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7741 12:41:06.707847 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7742 12:41:06.714511 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7743 12:41:06.718000 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7744 12:41:06.720992 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7745 12:41:06.724235 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7746 12:41:06.727716 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7747 12:41:06.734405 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7748 12:41:06.737938 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7749 12:41:06.740829 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7750 12:41:06.744273 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7751 12:41:06.747307 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7752 12:41:06.754009 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7753 12:41:06.757288 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7754 12:41:06.760737 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7755 12:41:06.761166 ==
7756 12:41:06.763639 Dram Type= 6, Freq= 0, CH_0, rank 0
7757 12:41:06.766805 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7758 12:41:06.770384 ==
7759 12:41:06.770808 DQS Delay:
7760 12:41:06.771148 DQS0 = 0, DQS1 = 0
7761 12:41:06.773803 DQM Delay:
7762 12:41:06.774281 DQM0 = 136, DQM1 = 127
7763 12:41:06.776957 DQ Delay:
7764 12:41:06.780307 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7765 12:41:06.783841 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7766 12:41:06.786927 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7767 12:41:06.790406 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =131
7768 12:41:06.790837
7769 12:41:06.791253
7770 12:41:06.791575 ==
7771 12:41:06.794032 Dram Type= 6, Freq= 0, CH_0, rank 0
7772 12:41:06.797069 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7773 12:41:06.800429 ==
7774 12:41:06.800921
7775 12:41:06.801320
7776 12:41:06.801657 TX Vref Scan disable
7777 12:41:06.803621 == TX Byte 0 ==
7778 12:41:06.806589 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7779 12:41:06.810010 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7780 12:41:06.813155 == TX Byte 1 ==
7781 12:41:06.816383 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7782 12:41:06.819738 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7783 12:41:06.823192 ==
7784 12:41:06.826378 Dram Type= 6, Freq= 0, CH_0, rank 0
7785 12:41:06.829675 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7786 12:41:06.830110 ==
7787 12:41:06.843022
7788 12:41:06.845689 TX Vref early break, caculate TX vref
7789 12:41:06.848996 TX Vref=16, minBit 4, minWin=22, winSum=372
7790 12:41:06.852465 TX Vref=18, minBit 14, minWin=22, winSum=379
7791 12:41:06.855803 TX Vref=20, minBit 14, minWin=23, winSum=392
7792 12:41:06.859006 TX Vref=22, minBit 1, minWin=24, winSum=397
7793 12:41:06.865388 TX Vref=24, minBit 2, minWin=25, winSum=411
7794 12:41:06.868704 TX Vref=26, minBit 2, minWin=25, winSum=412
7795 12:41:06.872414 TX Vref=28, minBit 0, minWin=25, winSum=418
7796 12:41:06.875300 TX Vref=30, minBit 4, minWin=24, winSum=407
7797 12:41:06.878734 TX Vref=32, minBit 0, minWin=24, winSum=402
7798 12:41:06.882185 TX Vref=34, minBit 4, minWin=23, winSum=391
7799 12:41:06.888610 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 28
7800 12:41:06.889042
7801 12:41:06.891839 Final TX Range 0 Vref 28
7802 12:41:06.892372
7803 12:41:06.892821 ==
7804 12:41:06.895204 Dram Type= 6, Freq= 0, CH_0, rank 0
7805 12:41:06.898289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7806 12:41:06.898724 ==
7807 12:41:06.899067
7808 12:41:06.901443
7809 12:41:06.901871 TX Vref Scan disable
7810 12:41:06.908150 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7811 12:41:06.908613 == TX Byte 0 ==
7812 12:41:06.911730 u2DelayCellOfst[0]=18 cells (5 PI)
7813 12:41:06.914722 u2DelayCellOfst[1]=18 cells (5 PI)
7814 12:41:06.918171 u2DelayCellOfst[2]=15 cells (4 PI)
7815 12:41:06.921913 u2DelayCellOfst[3]=18 cells (5 PI)
7816 12:41:06.924734 u2DelayCellOfst[4]=11 cells (3 PI)
7817 12:41:06.928301 u2DelayCellOfst[5]=0 cells (0 PI)
7818 12:41:06.931635 u2DelayCellOfst[6]=18 cells (5 PI)
7819 12:41:06.935031 u2DelayCellOfst[7]=22 cells (6 PI)
7820 12:41:06.937991 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7821 12:41:06.941352 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7822 12:41:06.944649 == TX Byte 1 ==
7823 12:41:06.947712 u2DelayCellOfst[8]=0 cells (0 PI)
7824 12:41:06.951136 u2DelayCellOfst[9]=0 cells (0 PI)
7825 12:41:06.955089 u2DelayCellOfst[10]=7 cells (2 PI)
7826 12:41:06.957969 u2DelayCellOfst[11]=0 cells (0 PI)
7827 12:41:06.961188 u2DelayCellOfst[12]=11 cells (3 PI)
7828 12:41:06.961651 u2DelayCellOfst[13]=11 cells (3 PI)
7829 12:41:06.964593 u2DelayCellOfst[14]=15 cells (4 PI)
7830 12:41:06.967662 u2DelayCellOfst[15]=11 cells (3 PI)
7831 12:41:06.974149 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7832 12:41:06.977646 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7833 12:41:06.978069 DramC Write-DBI on
7834 12:41:06.980914 ==
7835 12:41:06.984155 Dram Type= 6, Freq= 0, CH_0, rank 0
7836 12:41:06.987698 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7837 12:41:06.988122 ==
7838 12:41:06.988455
7839 12:41:06.988828
7840 12:41:06.991145 TX Vref Scan disable
7841 12:41:06.991565 == TX Byte 0 ==
7842 12:41:06.997815 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7843 12:41:06.998239 == TX Byte 1 ==
7844 12:41:07.000512 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7845 12:41:07.004195 DramC Write-DBI off
7846 12:41:07.004640
7847 12:41:07.004977 [DATLAT]
7848 12:41:07.007427 Freq=1600, CH0 RK0
7849 12:41:07.007851
7850 12:41:07.008187 DATLAT Default: 0xf
7851 12:41:07.010757 0, 0xFFFF, sum = 0
7852 12:41:07.011183 1, 0xFFFF, sum = 0
7853 12:41:07.013933 2, 0xFFFF, sum = 0
7854 12:41:07.014380 3, 0xFFFF, sum = 0
7855 12:41:07.017270 4, 0xFFFF, sum = 0
7856 12:41:07.021027 5, 0xFFFF, sum = 0
7857 12:41:07.021459 6, 0xFFFF, sum = 0
7858 12:41:07.024254 7, 0xFFFF, sum = 0
7859 12:41:07.024715 8, 0xFFFF, sum = 0
7860 12:41:07.027359 9, 0xFFFF, sum = 0
7861 12:41:07.027787 10, 0xFFFF, sum = 0
7862 12:41:07.030464 11, 0xFFFF, sum = 0
7863 12:41:07.030896 12, 0xFFFF, sum = 0
7864 12:41:07.033959 13, 0xFFFF, sum = 0
7865 12:41:07.034392 14, 0x0, sum = 1
7866 12:41:07.037264 15, 0x0, sum = 2
7867 12:41:07.037695 16, 0x0, sum = 3
7868 12:41:07.040267 17, 0x0, sum = 4
7869 12:41:07.040716 best_step = 15
7870 12:41:07.041051
7871 12:41:07.041364 ==
7872 12:41:07.043788 Dram Type= 6, Freq= 0, CH_0, rank 0
7873 12:41:07.046832 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7874 12:41:07.050143 ==
7875 12:41:07.050569 RX Vref Scan: 1
7876 12:41:07.050906
7877 12:41:07.054062 Set Vref Range= 24 -> 127
7878 12:41:07.054486
7879 12:41:07.056906 RX Vref 24 -> 127, step: 1
7880 12:41:07.057335
7881 12:41:07.057673 RX Delay 19 -> 252, step: 4
7882 12:41:07.057993
7883 12:41:07.060650 Set Vref, RX VrefLevel [Byte0]: 24
7884 12:41:07.063271 [Byte1]: 24
7885 12:41:07.067544
7886 12:41:07.067973 Set Vref, RX VrefLevel [Byte0]: 25
7887 12:41:07.070609 [Byte1]: 25
7888 12:41:07.075595
7889 12:41:07.076080 Set Vref, RX VrefLevel [Byte0]: 26
7890 12:41:07.078034 [Byte1]: 26
7891 12:41:07.082506
7892 12:41:07.082933 Set Vref, RX VrefLevel [Byte0]: 27
7893 12:41:07.085479 [Byte1]: 27
7894 12:41:07.090126
7895 12:41:07.090550 Set Vref, RX VrefLevel [Byte0]: 28
7896 12:41:07.093387 [Byte1]: 28
7897 12:41:07.097306
7898 12:41:07.097732 Set Vref, RX VrefLevel [Byte0]: 29
7899 12:41:07.101333 [Byte1]: 29
7900 12:41:07.105446
7901 12:41:07.106034 Set Vref, RX VrefLevel [Byte0]: 30
7902 12:41:07.108652 [Byte1]: 30
7903 12:41:07.112956
7904 12:41:07.113427 Set Vref, RX VrefLevel [Byte0]: 31
7905 12:41:07.116390 [Byte1]: 31
7906 12:41:07.120500
7907 12:41:07.120998 Set Vref, RX VrefLevel [Byte0]: 32
7908 12:41:07.124068 [Byte1]: 32
7909 12:41:07.127931
7910 12:41:07.128360 Set Vref, RX VrefLevel [Byte0]: 33
7911 12:41:07.131411 [Byte1]: 33
7912 12:41:07.135808
7913 12:41:07.136256 Set Vref, RX VrefLevel [Byte0]: 34
7914 12:41:07.138767 [Byte1]: 34
7915 12:41:07.143373
7916 12:41:07.143931 Set Vref, RX VrefLevel [Byte0]: 35
7917 12:41:07.146360 [Byte1]: 35
7918 12:41:07.150727
7919 12:41:07.151158 Set Vref, RX VrefLevel [Byte0]: 36
7920 12:41:07.153610 [Byte1]: 36
7921 12:41:07.158500
7922 12:41:07.158948 Set Vref, RX VrefLevel [Byte0]: 37
7923 12:41:07.161718 [Byte1]: 37
7924 12:41:07.166109
7925 12:41:07.166536 Set Vref, RX VrefLevel [Byte0]: 38
7926 12:41:07.169243 [Byte1]: 38
7927 12:41:07.173343
7928 12:41:07.173773 Set Vref, RX VrefLevel [Byte0]: 39
7929 12:41:07.176616 [Byte1]: 39
7930 12:41:07.181075
7931 12:41:07.181519 Set Vref, RX VrefLevel [Byte0]: 40
7932 12:41:07.184396 [Byte1]: 40
7933 12:41:07.188565
7934 12:41:07.188999 Set Vref, RX VrefLevel [Byte0]: 41
7935 12:41:07.191996 [Byte1]: 41
7936 12:41:07.196644
7937 12:41:07.197171 Set Vref, RX VrefLevel [Byte0]: 42
7938 12:41:07.199768 [Byte1]: 42
7939 12:41:07.203559
7940 12:41:07.204021 Set Vref, RX VrefLevel [Byte0]: 43
7941 12:41:07.207378 [Byte1]: 43
7942 12:41:07.211040
7943 12:41:07.211490 Set Vref, RX VrefLevel [Byte0]: 44
7944 12:41:07.214697 [Byte1]: 44
7945 12:41:07.218750
7946 12:41:07.219183 Set Vref, RX VrefLevel [Byte0]: 45
7947 12:41:07.221930 [Byte1]: 45
7948 12:41:07.226271
7949 12:41:07.226704 Set Vref, RX VrefLevel [Byte0]: 46
7950 12:41:07.229607 [Byte1]: 46
7951 12:41:07.234119
7952 12:41:07.234547 Set Vref, RX VrefLevel [Byte0]: 47
7953 12:41:07.237579 [Byte1]: 47
7954 12:41:07.241964
7955 12:41:07.242395 Set Vref, RX VrefLevel [Byte0]: 48
7956 12:41:07.245085 [Byte1]: 48
7957 12:41:07.248885
7958 12:41:07.249312 Set Vref, RX VrefLevel [Byte0]: 49
7959 12:41:07.252458 [Byte1]: 49
7960 12:41:07.257174
7961 12:41:07.257606 Set Vref, RX VrefLevel [Byte0]: 50
7962 12:41:07.260355 [Byte1]: 50
7963 12:41:07.264359
7964 12:41:07.264827 Set Vref, RX VrefLevel [Byte0]: 51
7965 12:41:07.267823 [Byte1]: 51
7966 12:41:07.272038
7967 12:41:07.272467 Set Vref, RX VrefLevel [Byte0]: 52
7968 12:41:07.275065 [Byte1]: 52
7969 12:41:07.279797
7970 12:41:07.280225 Set Vref, RX VrefLevel [Byte0]: 53
7971 12:41:07.283382 [Byte1]: 53
7972 12:41:07.287081
7973 12:41:07.287643 Set Vref, RX VrefLevel [Byte0]: 54
7974 12:41:07.290802 [Byte1]: 54
7975 12:41:07.294522
7976 12:41:07.295041 Set Vref, RX VrefLevel [Byte0]: 55
7977 12:41:07.297576 [Byte1]: 55
7978 12:41:07.302575
7979 12:41:07.303003 Set Vref, RX VrefLevel [Byte0]: 56
7980 12:41:07.305435 [Byte1]: 56
7981 12:41:07.309339
7982 12:41:07.312613 Set Vref, RX VrefLevel [Byte0]: 57
7983 12:41:07.315879 [Byte1]: 57
7984 12:41:07.316349
7985 12:41:07.319631 Set Vref, RX VrefLevel [Byte0]: 58
7986 12:41:07.323183 [Byte1]: 58
7987 12:41:07.323747
7988 12:41:07.326042 Set Vref, RX VrefLevel [Byte0]: 59
7989 12:41:07.329283 [Byte1]: 59
7990 12:41:07.329714
7991 12:41:07.332988 Set Vref, RX VrefLevel [Byte0]: 60
7992 12:41:07.336066 [Byte1]: 60
7993 12:41:07.340428
7994 12:41:07.341022 Set Vref, RX VrefLevel [Byte0]: 61
7995 12:41:07.343536 [Byte1]: 61
7996 12:41:07.347671
7997 12:41:07.348099 Set Vref, RX VrefLevel [Byte0]: 62
7998 12:41:07.350935 [Byte1]: 62
7999 12:41:07.355248
8000 12:41:07.355809 Set Vref, RX VrefLevel [Byte0]: 63
8001 12:41:07.358350 [Byte1]: 63
8002 12:41:07.362646
8003 12:41:07.363067 Set Vref, RX VrefLevel [Byte0]: 64
8004 12:41:07.366170 [Byte1]: 64
8005 12:41:07.370810
8006 12:41:07.371307 Set Vref, RX VrefLevel [Byte0]: 65
8007 12:41:07.373518 [Byte1]: 65
8008 12:41:07.377855
8009 12:41:07.378329 Set Vref, RX VrefLevel [Byte0]: 66
8010 12:41:07.380996 [Byte1]: 66
8011 12:41:07.385228
8012 12:41:07.385715 Set Vref, RX VrefLevel [Byte0]: 67
8013 12:41:07.388856 [Byte1]: 67
8014 12:41:07.393349
8015 12:41:07.393965 Set Vref, RX VrefLevel [Byte0]: 68
8016 12:41:07.396719 [Byte1]: 68
8017 12:41:07.400681
8018 12:41:07.401156 Set Vref, RX VrefLevel [Byte0]: 69
8019 12:41:07.403674 [Byte1]: 69
8020 12:41:07.408417
8021 12:41:07.409009 Set Vref, RX VrefLevel [Byte0]: 70
8022 12:41:07.411629 [Byte1]: 70
8023 12:41:07.415705
8024 12:41:07.416148 Set Vref, RX VrefLevel [Byte0]: 71
8025 12:41:07.418904 [Byte1]: 71
8026 12:41:07.423203
8027 12:41:07.423646 Set Vref, RX VrefLevel [Byte0]: 72
8028 12:41:07.426968 [Byte1]: 72
8029 12:41:07.431131
8030 12:41:07.431670 Set Vref, RX VrefLevel [Byte0]: 73
8031 12:41:07.434293 [Byte1]: 73
8032 12:41:07.438315
8033 12:41:07.438743 Set Vref, RX VrefLevel [Byte0]: 74
8034 12:41:07.444643 [Byte1]: 74
8035 12:41:07.445092
8036 12:41:07.448432 Set Vref, RX VrefLevel [Byte0]: 75
8037 12:41:07.451625 [Byte1]: 75
8038 12:41:07.452178
8039 12:41:07.454700 Set Vref, RX VrefLevel [Byte0]: 76
8040 12:41:07.458036 [Byte1]: 76
8041 12:41:07.458463
8042 12:41:07.461105 Set Vref, RX VrefLevel [Byte0]: 77
8043 12:41:07.464646 [Byte1]: 77
8044 12:41:07.468980
8045 12:41:07.469450 Set Vref, RX VrefLevel [Byte0]: 78
8046 12:41:07.472040 [Byte1]: 78
8047 12:41:07.476289
8048 12:41:07.476826 Set Vref, RX VrefLevel [Byte0]: 79
8049 12:41:07.479882 [Byte1]: 79
8050 12:41:07.483623
8051 12:41:07.484094 Set Vref, RX VrefLevel [Byte0]: 80
8052 12:41:07.487097 [Byte1]: 80
8053 12:41:07.491561
8054 12:41:07.492129 Final RX Vref Byte 0 = 66 to rank0
8055 12:41:07.494534 Final RX Vref Byte 1 = 60 to rank0
8056 12:41:07.498281 Final RX Vref Byte 0 = 66 to rank1
8057 12:41:07.501323 Final RX Vref Byte 1 = 60 to rank1==
8058 12:41:07.504764 Dram Type= 6, Freq= 0, CH_0, rank 0
8059 12:41:07.511288 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8060 12:41:07.511733 ==
8061 12:41:07.512092 DQS Delay:
8062 12:41:07.514818 DQS0 = 0, DQS1 = 0
8063 12:41:07.515362 DQM Delay:
8064 12:41:07.517366 DQM0 = 133, DQM1 = 123
8065 12:41:07.517791 DQ Delay:
8066 12:41:07.521056 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =132
8067 12:41:07.524269 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =142
8068 12:41:07.527711 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8069 12:41:07.530792 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =128
8070 12:41:07.531340
8071 12:41:07.531698
8072 12:41:07.532015
8073 12:41:07.534213 [DramC_TX_OE_Calibration] TA2
8074 12:41:07.537453 Original DQ_B0 (3 6) =30, OEN = 27
8075 12:41:07.541057 Original DQ_B1 (3 6) =30, OEN = 27
8076 12:41:07.544291 24, 0x0, End_B0=24 End_B1=24
8077 12:41:07.547505 25, 0x0, End_B0=25 End_B1=25
8078 12:41:07.547937 26, 0x0, End_B0=26 End_B1=26
8079 12:41:07.550503 27, 0x0, End_B0=27 End_B1=27
8080 12:41:07.553907 28, 0x0, End_B0=28 End_B1=28
8081 12:41:07.557554 29, 0x0, End_B0=29 End_B1=29
8082 12:41:07.558005 30, 0x0, End_B0=30 End_B1=30
8083 12:41:07.560310 31, 0x5151, End_B0=30 End_B1=30
8084 12:41:07.563967 Byte0 end_step=30 best_step=27
8085 12:41:07.567269 Byte1 end_step=30 best_step=27
8086 12:41:07.570600 Byte0 TX OE(2T, 0.5T) = (3, 3)
8087 12:41:07.573683 Byte1 TX OE(2T, 0.5T) = (3, 3)
8088 12:41:07.574110
8089 12:41:07.574469
8090 12:41:07.580291 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 394 ps
8091 12:41:07.583725 CH0 RK0: MR19=303, MR18=1F10
8092 12:41:07.589971 CH0_RK0: MR19=0x303, MR18=0x1F10, DQSOSC=394, MR23=63, INC=23, DEC=15
8093 12:41:07.590408
8094 12:41:07.593454 ----->DramcWriteLeveling(PI) begin...
8095 12:41:07.593925 ==
8096 12:41:07.596836 Dram Type= 6, Freq= 0, CH_0, rank 1
8097 12:41:07.599917 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8098 12:41:07.600341 ==
8099 12:41:07.603205 Write leveling (Byte 0): 35 => 35
8100 12:41:07.606685 Write leveling (Byte 1): 29 => 29
8101 12:41:07.609736 DramcWriteLeveling(PI) end<-----
8102 12:41:07.610159
8103 12:41:07.610494 ==
8104 12:41:07.613098 Dram Type= 6, Freq= 0, CH_0, rank 1
8105 12:41:07.619775 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8106 12:41:07.620200 ==
8107 12:41:07.620580 [Gating] SW mode calibration
8108 12:41:07.629166 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8109 12:41:07.632746 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8110 12:41:07.639912 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8111 12:41:07.642480 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8112 12:41:07.645880 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8113 12:41:07.652644 1 4 12 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8114 12:41:07.656144 1 4 16 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
8115 12:41:07.659201 1 4 20 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
8116 12:41:07.665986 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8117 12:41:07.668957 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8118 12:41:07.672437 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8119 12:41:07.678832 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8120 12:41:07.682217 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8121 12:41:07.685659 1 5 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8122 12:41:07.692110 1 5 16 | B1->B0 | 3434 2626 | 1 0 | (1 0) (0 0)
8123 12:41:07.695166 1 5 20 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
8124 12:41:07.698484 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8125 12:41:07.705054 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8126 12:41:07.708504 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8127 12:41:07.711788 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8128 12:41:07.718960 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8129 12:41:07.721568 1 6 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8130 12:41:07.725018 1 6 16 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8131 12:41:07.732134 1 6 20 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
8132 12:41:07.734753 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8133 12:41:07.738477 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8134 12:41:07.745298 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8135 12:41:07.748107 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8136 12:41:07.751670 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8137 12:41:07.757845 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8138 12:41:07.761751 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8139 12:41:07.764639 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8140 12:41:07.771323 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8141 12:41:07.774615 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8142 12:41:07.778348 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8143 12:41:07.781419 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8144 12:41:07.787969 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8145 12:41:07.791555 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8146 12:41:07.794766 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8147 12:41:07.801121 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8148 12:41:07.804441 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8149 12:41:07.807867 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8150 12:41:07.814459 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8151 12:41:07.817346 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8152 12:41:07.820741 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8153 12:41:07.828047 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8154 12:41:07.831281 Total UI for P1: 0, mck2ui 16
8155 12:41:07.834013 best dqsien dly found for B0: ( 1, 9, 8)
8156 12:41:07.837451 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8157 12:41:07.840548 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8158 12:41:07.847207 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8159 12:41:07.850705 Total UI for P1: 0, mck2ui 16
8160 12:41:07.853975 best dqsien dly found for B1: ( 1, 9, 16)
8161 12:41:07.857309 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8162 12:41:07.860649 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8163 12:41:07.861075
8164 12:41:07.863668 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8165 12:41:07.867454 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8166 12:41:07.870777 [Gating] SW calibration Done
8167 12:41:07.871310 ==
8168 12:41:07.873713 Dram Type= 6, Freq= 0, CH_0, rank 1
8169 12:41:07.877406 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8170 12:41:07.877862 ==
8171 12:41:07.880496 RX Vref Scan: 0
8172 12:41:07.880956
8173 12:41:07.883861 RX Vref 0 -> 0, step: 1
8174 12:41:07.884288
8175 12:41:07.884672 RX Delay 0 -> 252, step: 8
8176 12:41:07.890116 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8177 12:41:07.893554 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8178 12:41:07.896954 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8179 12:41:07.900333 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8180 12:41:07.903478 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8181 12:41:07.909852 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8182 12:41:07.913778 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8183 12:41:07.916696 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8184 12:41:07.920008 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8185 12:41:07.923653 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8186 12:41:07.929747 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8187 12:41:07.933011 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8188 12:41:07.936785 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8189 12:41:07.940226 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8190 12:41:07.946350 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8191 12:41:07.949383 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8192 12:41:07.949842 ==
8193 12:41:07.952807 Dram Type= 6, Freq= 0, CH_0, rank 1
8194 12:41:07.956501 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8195 12:41:07.956966 ==
8196 12:41:07.957307 DQS Delay:
8197 12:41:07.959507 DQS0 = 0, DQS1 = 0
8198 12:41:07.959931 DQM Delay:
8199 12:41:07.963026 DQM0 = 133, DQM1 = 128
8200 12:41:07.963454 DQ Delay:
8201 12:41:07.966183 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8202 12:41:07.970060 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8203 12:41:07.973028 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8204 12:41:07.979338 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8205 12:41:07.979764
8206 12:41:07.980099
8207 12:41:07.980413 ==
8208 12:41:07.983057 Dram Type= 6, Freq= 0, CH_0, rank 1
8209 12:41:07.986270 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8210 12:41:07.986698 ==
8211 12:41:07.987036
8212 12:41:07.987347
8213 12:41:07.989136 TX Vref Scan disable
8214 12:41:07.989558 == TX Byte 0 ==
8215 12:41:07.996071 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8216 12:41:07.999103 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8217 12:41:07.999531 == TX Byte 1 ==
8218 12:41:08.006160 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8219 12:41:08.009042 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8220 12:41:08.009471 ==
8221 12:41:08.012579 Dram Type= 6, Freq= 0, CH_0, rank 1
8222 12:41:08.016047 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8223 12:41:08.016632 ==
8224 12:41:08.030424
8225 12:41:08.033400 TX Vref early break, caculate TX vref
8226 12:41:08.036991 TX Vref=16, minBit 0, minWin=22, winSum=379
8227 12:41:08.040181 TX Vref=18, minBit 1, minWin=22, winSum=385
8228 12:41:08.043074 TX Vref=20, minBit 0, minWin=23, winSum=395
8229 12:41:08.046799 TX Vref=22, minBit 0, minWin=24, winSum=406
8230 12:41:08.049782 TX Vref=24, minBit 4, minWin=24, winSum=413
8231 12:41:08.056872 TX Vref=26, minBit 1, minWin=24, winSum=418
8232 12:41:08.059837 TX Vref=28, minBit 0, minWin=24, winSum=416
8233 12:41:08.063600 TX Vref=30, minBit 1, minWin=24, winSum=408
8234 12:41:08.066348 TX Vref=32, minBit 0, minWin=24, winSum=397
8235 12:41:08.069630 TX Vref=34, minBit 0, minWin=23, winSum=392
8236 12:41:08.076293 [TxChooseVref] Worse bit 1, Min win 24, Win sum 418, Final Vref 26
8237 12:41:08.076805
8238 12:41:08.079711 Final TX Range 0 Vref 26
8239 12:41:08.080180
8240 12:41:08.080559 ==
8241 12:41:08.082553 Dram Type= 6, Freq= 0, CH_0, rank 1
8242 12:41:08.085974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8243 12:41:08.086446 ==
8244 12:41:08.086794
8245 12:41:08.087142
8246 12:41:08.089594 TX Vref Scan disable
8247 12:41:08.096076 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8248 12:41:08.096506 == TX Byte 0 ==
8249 12:41:08.099096 u2DelayCellOfst[0]=15 cells (4 PI)
8250 12:41:08.102426 u2DelayCellOfst[1]=22 cells (6 PI)
8251 12:41:08.105912 u2DelayCellOfst[2]=15 cells (4 PI)
8252 12:41:08.109182 u2DelayCellOfst[3]=15 cells (4 PI)
8253 12:41:08.112717 u2DelayCellOfst[4]=11 cells (3 PI)
8254 12:41:08.115850 u2DelayCellOfst[5]=0 cells (0 PI)
8255 12:41:08.119267 u2DelayCellOfst[6]=22 cells (6 PI)
8256 12:41:08.122058 u2DelayCellOfst[7]=22 cells (6 PI)
8257 12:41:08.125526 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8258 12:41:08.128832 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8259 12:41:08.132547 == TX Byte 1 ==
8260 12:41:08.135619 u2DelayCellOfst[8]=0 cells (0 PI)
8261 12:41:08.139108 u2DelayCellOfst[9]=3 cells (1 PI)
8262 12:41:08.141854 u2DelayCellOfst[10]=11 cells (3 PI)
8263 12:41:08.145555 u2DelayCellOfst[11]=3 cells (1 PI)
8264 12:41:08.148470 u2DelayCellOfst[12]=15 cells (4 PI)
8265 12:41:08.148941 u2DelayCellOfst[13]=15 cells (4 PI)
8266 12:41:08.151890 u2DelayCellOfst[14]=18 cells (5 PI)
8267 12:41:08.155495 u2DelayCellOfst[15]=15 cells (4 PI)
8268 12:41:08.162006 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8269 12:41:08.165194 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8270 12:41:08.165802 DramC Write-DBI on
8271 12:41:08.168421 ==
8272 12:41:08.171918 Dram Type= 6, Freq= 0, CH_0, rank 1
8273 12:41:08.175067 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8274 12:41:08.175712 ==
8275 12:41:08.176079
8276 12:41:08.176396
8277 12:41:08.178196 TX Vref Scan disable
8278 12:41:08.178620 == TX Byte 0 ==
8279 12:41:08.185076 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8280 12:41:08.185610 == TX Byte 1 ==
8281 12:41:08.187867 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8282 12:41:08.191668 DramC Write-DBI off
8283 12:41:08.192089
8284 12:41:08.192423 [DATLAT]
8285 12:41:08.195001 Freq=1600, CH0 RK1
8286 12:41:08.195522
8287 12:41:08.195855 DATLAT Default: 0xf
8288 12:41:08.198376 0, 0xFFFF, sum = 0
8289 12:41:08.198809 1, 0xFFFF, sum = 0
8290 12:41:08.201550 2, 0xFFFF, sum = 0
8291 12:41:08.204591 3, 0xFFFF, sum = 0
8292 12:41:08.205023 4, 0xFFFF, sum = 0
8293 12:41:08.207663 5, 0xFFFF, sum = 0
8294 12:41:08.208088 6, 0xFFFF, sum = 0
8295 12:41:08.211061 7, 0xFFFF, sum = 0
8296 12:41:08.211486 8, 0xFFFF, sum = 0
8297 12:41:08.214332 9, 0xFFFF, sum = 0
8298 12:41:08.214760 10, 0xFFFF, sum = 0
8299 12:41:08.217787 11, 0xFFFF, sum = 0
8300 12:41:08.218215 12, 0xFFFF, sum = 0
8301 12:41:08.221177 13, 0xFFFF, sum = 0
8302 12:41:08.221609 14, 0x0, sum = 1
8303 12:41:08.224415 15, 0x0, sum = 2
8304 12:41:08.224870 16, 0x0, sum = 3
8305 12:41:08.227537 17, 0x0, sum = 4
8306 12:41:08.227961 best_step = 15
8307 12:41:08.228296
8308 12:41:08.228650 ==
8309 12:41:08.230841 Dram Type= 6, Freq= 0, CH_0, rank 1
8310 12:41:08.237380 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8311 12:41:08.237805 ==
8312 12:41:08.238140 RX Vref Scan: 0
8313 12:41:08.238452
8314 12:41:08.240609 RX Vref 0 -> 0, step: 1
8315 12:41:08.241030
8316 12:41:08.243863 RX Delay 11 -> 252, step: 4
8317 12:41:08.247499 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8318 12:41:08.250503 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8319 12:41:08.256965 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8320 12:41:08.260435 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8321 12:41:08.264122 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8322 12:41:08.266934 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8323 12:41:08.270580 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8324 12:41:08.276615 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8325 12:41:08.280183 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8326 12:41:08.283684 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8327 12:41:08.286858 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8328 12:41:08.289851 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8329 12:41:08.296968 iDelay=195, Bit 12, Center 130 (79 ~ 182) 104
8330 12:41:08.299649 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8331 12:41:08.303150 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8332 12:41:08.306764 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8333 12:41:08.307305 ==
8334 12:41:08.310011 Dram Type= 6, Freq= 0, CH_0, rank 1
8335 12:41:08.316318 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8336 12:41:08.316776 ==
8337 12:41:08.317114 DQS Delay:
8338 12:41:08.319875 DQS0 = 0, DQS1 = 0
8339 12:41:08.320298 DQM Delay:
8340 12:41:08.323240 DQM0 = 130, DQM1 = 125
8341 12:41:08.323665 DQ Delay:
8342 12:41:08.326397 DQ0 =128, DQ1 =134, DQ2 =124, DQ3 =128
8343 12:41:08.329564 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =140
8344 12:41:08.333193 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8345 12:41:08.335993 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =132
8346 12:41:08.336418
8347 12:41:08.336789
8348 12:41:08.337102
8349 12:41:08.339263 [DramC_TX_OE_Calibration] TA2
8350 12:41:08.342826 Original DQ_B0 (3 6) =30, OEN = 27
8351 12:41:08.346197 Original DQ_B1 (3 6) =30, OEN = 27
8352 12:41:08.349451 24, 0x0, End_B0=24 End_B1=24
8353 12:41:08.352944 25, 0x0, End_B0=25 End_B1=25
8354 12:41:08.353377 26, 0x0, End_B0=26 End_B1=26
8355 12:41:08.356453 27, 0x0, End_B0=27 End_B1=27
8356 12:41:08.359206 28, 0x0, End_B0=28 End_B1=28
8357 12:41:08.362781 29, 0x0, End_B0=29 End_B1=29
8358 12:41:08.365843 30, 0x0, End_B0=30 End_B1=30
8359 12:41:08.366273 31, 0x4141, End_B0=30 End_B1=30
8360 12:41:08.369353 Byte0 end_step=30 best_step=27
8361 12:41:08.372618 Byte1 end_step=30 best_step=27
8362 12:41:08.375659 Byte0 TX OE(2T, 0.5T) = (3, 3)
8363 12:41:08.379139 Byte1 TX OE(2T, 0.5T) = (3, 3)
8364 12:41:08.379551
8365 12:41:08.379877
8366 12:41:08.385673 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f03, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 394 ps
8367 12:41:08.388679 CH0 RK1: MR19=303, MR18=1F03
8368 12:41:08.395269 CH0_RK1: MR19=0x303, MR18=0x1F03, DQSOSC=394, MR23=63, INC=23, DEC=15
8369 12:41:08.398624 [RxdqsGatingPostProcess] freq 1600
8370 12:41:08.405569 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8371 12:41:08.408700 best DQS0 dly(2T, 0.5T) = (1, 1)
8372 12:41:08.409118 best DQS1 dly(2T, 0.5T) = (1, 1)
8373 12:41:08.412458 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8374 12:41:08.415617 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8375 12:41:08.418345 best DQS0 dly(2T, 0.5T) = (1, 1)
8376 12:41:08.421773 best DQS1 dly(2T, 0.5T) = (1, 1)
8377 12:41:08.425212 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8378 12:41:08.428733 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8379 12:41:08.431787 Pre-setting of DQS Precalculation
8380 12:41:08.435161 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8381 12:41:08.438747 ==
8382 12:41:08.439163 Dram Type= 6, Freq= 0, CH_1, rank 0
8383 12:41:08.445264 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8384 12:41:08.445773 ==
8385 12:41:08.448821 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8386 12:41:08.454873 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8387 12:41:08.458339 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8388 12:41:08.464645 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8389 12:41:08.473141 [CA 0] Center 41 (12~71) winsize 60
8390 12:41:08.476331 [CA 1] Center 42 (13~71) winsize 59
8391 12:41:08.479364 [CA 2] Center 37 (8~66) winsize 59
8392 12:41:08.482933 [CA 3] Center 36 (7~66) winsize 60
8393 12:41:08.485923 [CA 4] Center 37 (7~67) winsize 61
8394 12:41:08.489791 [CA 5] Center 36 (7~66) winsize 60
8395 12:41:08.490204
8396 12:41:08.492798 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8397 12:41:08.493213
8398 12:41:08.496743 [CATrainingPosCal] consider 1 rank data
8399 12:41:08.499280 u2DelayCellTimex100 = 258/100 ps
8400 12:41:08.506156 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8401 12:41:08.509110 CA1 delay=42 (13~71),Diff = 6 PI (22 cell)
8402 12:41:08.512788 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8403 12:41:08.515788 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8404 12:41:08.518905 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8405 12:41:08.522806 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8406 12:41:08.523221
8407 12:41:08.525603 CA PerBit enable=1, Macro0, CA PI delay=36
8408 12:41:08.526017
8409 12:41:08.528830 [CBTSetCACLKResult] CA Dly = 36
8410 12:41:08.532254 CS Dly: 9 (0~40)
8411 12:41:08.535601 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8412 12:41:08.538936 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8413 12:41:08.539462 ==
8414 12:41:08.542155 Dram Type= 6, Freq= 0, CH_1, rank 1
8415 12:41:08.548983 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8416 12:41:08.549514 ==
8417 12:41:08.552036 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8418 12:41:08.558768 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8419 12:41:08.562093 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8420 12:41:08.568439 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8421 12:41:08.576226 [CA 0] Center 42 (12~72) winsize 61
8422 12:41:08.579629 [CA 1] Center 42 (12~72) winsize 61
8423 12:41:08.582981 [CA 2] Center 37 (8~67) winsize 60
8424 12:41:08.585788 [CA 3] Center 36 (7~66) winsize 60
8425 12:41:08.589679 [CA 4] Center 37 (8~67) winsize 60
8426 12:41:08.592445 [CA 5] Center 37 (7~67) winsize 61
8427 12:41:08.592897
8428 12:41:08.595915 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8429 12:41:08.596332
8430 12:41:08.599176 [CATrainingPosCal] consider 2 rank data
8431 12:41:08.602656 u2DelayCellTimex100 = 258/100 ps
8432 12:41:08.608919 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8433 12:41:08.612244 CA1 delay=42 (13~71),Diff = 6 PI (22 cell)
8434 12:41:08.615989 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8435 12:41:08.619043 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8436 12:41:08.622411 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8437 12:41:08.625300 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8438 12:41:08.625718
8439 12:41:08.628793 CA PerBit enable=1, Macro0, CA PI delay=36
8440 12:41:08.629209
8441 12:41:08.631874 [CBTSetCACLKResult] CA Dly = 36
8442 12:41:08.635202 CS Dly: 11 (0~44)
8443 12:41:08.638657 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8444 12:41:08.641974 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8445 12:41:08.642513
8446 12:41:08.645131 ----->DramcWriteLeveling(PI) begin...
8447 12:41:08.645627 ==
8448 12:41:08.648404 Dram Type= 6, Freq= 0, CH_1, rank 0
8449 12:41:08.654927 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8450 12:41:08.655345 ==
8451 12:41:08.658320 Write leveling (Byte 0): 24 => 24
8452 12:41:08.661591 Write leveling (Byte 1): 26 => 26
8453 12:41:08.662005 DramcWriteLeveling(PI) end<-----
8454 12:41:08.665021
8455 12:41:08.665433 ==
8456 12:41:08.668373 Dram Type= 6, Freq= 0, CH_1, rank 0
8457 12:41:08.671371 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8458 12:41:08.671787 ==
8459 12:41:08.675052 [Gating] SW mode calibration
8460 12:41:08.681616 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8461 12:41:08.688184 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8462 12:41:08.691124 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8463 12:41:08.694612 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8464 12:41:08.698515 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8465 12:41:08.704859 1 4 12 | B1->B0 | 3332 3434 | 1 0 | (0 0) (0 0)
8466 12:41:08.707677 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8467 12:41:08.714594 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8468 12:41:08.717855 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8469 12:41:08.721117 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8470 12:41:08.727739 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8471 12:41:08.731117 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8472 12:41:08.734711 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8473 12:41:08.740742 1 5 12 | B1->B0 | 3232 2424 | 1 0 | (1 0) (1 0)
8474 12:41:08.743996 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8475 12:41:08.747190 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8476 12:41:08.754189 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8477 12:41:08.757460 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8478 12:41:08.760613 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8479 12:41:08.767234 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8480 12:41:08.770688 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8481 12:41:08.773824 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8482 12:41:08.780849 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8483 12:41:08.783665 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8484 12:41:08.787228 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8485 12:41:08.790630 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8486 12:41:08.797111 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8487 12:41:08.800389 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8488 12:41:08.803775 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8489 12:41:08.810582 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8490 12:41:08.813920 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8491 12:41:08.817184 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8492 12:41:08.823536 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8493 12:41:08.826783 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8494 12:41:08.830735 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8495 12:41:08.837158 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8496 12:41:08.840835 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8497 12:41:08.843381 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8498 12:41:08.849931 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8499 12:41:08.853232 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8500 12:41:08.856405 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8501 12:41:08.862963 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8502 12:41:08.866935 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8503 12:41:08.869507 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8504 12:41:08.876445 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8505 12:41:08.879895 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8506 12:41:08.882965 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8507 12:41:08.886092 Total UI for P1: 0, mck2ui 16
8508 12:41:08.889310 best dqsien dly found for B0: ( 1, 9, 10)
8509 12:41:08.892794 Total UI for P1: 0, mck2ui 16
8510 12:41:08.896018 best dqsien dly found for B1: ( 1, 9, 10)
8511 12:41:08.899461 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8512 12:41:08.902777 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8513 12:41:08.903210
8514 12:41:08.909678 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8515 12:41:08.913058 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8516 12:41:08.916215 [Gating] SW calibration Done
8517 12:41:08.916686 ==
8518 12:41:08.919555 Dram Type= 6, Freq= 0, CH_1, rank 0
8519 12:41:08.922886 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8520 12:41:08.923309 ==
8521 12:41:08.923645 RX Vref Scan: 0
8522 12:41:08.923956
8523 12:41:08.925756 RX Vref 0 -> 0, step: 1
8524 12:41:08.926223
8525 12:41:08.929153 RX Delay 0 -> 252, step: 8
8526 12:41:08.932636 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8527 12:41:08.935948 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8528 12:41:08.942556 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8529 12:41:08.946018 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8530 12:41:08.949137 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8531 12:41:08.952602 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8532 12:41:08.955350 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8533 12:41:08.962090 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8534 12:41:08.965296 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8535 12:41:08.969143 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8536 12:41:08.971840 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8537 12:41:08.975231 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8538 12:41:08.981976 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8539 12:41:08.985489 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8540 12:41:08.988497 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8541 12:41:08.992123 iDelay=208, Bit 15, Center 139 (88 ~ 191) 104
8542 12:41:08.992590 ==
8543 12:41:08.995834 Dram Type= 6, Freq= 0, CH_1, rank 0
8544 12:41:09.001585 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8545 12:41:09.002099 ==
8546 12:41:09.002455 DQS Delay:
8547 12:41:09.004624 DQS0 = 0, DQS1 = 0
8548 12:41:09.005051 DQM Delay:
8549 12:41:09.008456 DQM0 = 138, DQM1 = 130
8550 12:41:09.009007 DQ Delay:
8551 12:41:09.011693 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =139
8552 12:41:09.015237 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8553 12:41:09.018318 DQ8 =115, DQ9 =115, DQ10 =135, DQ11 =123
8554 12:41:09.022047 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8555 12:41:09.022474
8556 12:41:09.022832
8557 12:41:09.023153 ==
8558 12:41:09.024980 Dram Type= 6, Freq= 0, CH_1, rank 0
8559 12:41:09.031753 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8560 12:41:09.032198 ==
8561 12:41:09.032580
8562 12:41:09.032925
8563 12:41:09.033232 TX Vref Scan disable
8564 12:41:09.035015 == TX Byte 0 ==
8565 12:41:09.038241 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8566 12:41:09.045387 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8567 12:41:09.045902 == TX Byte 1 ==
8568 12:41:09.048676 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8569 12:41:09.054706 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8570 12:41:09.055141 ==
8571 12:41:09.057826 Dram Type= 6, Freq= 0, CH_1, rank 0
8572 12:41:09.061116 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8573 12:41:09.061557 ==
8574 12:41:09.073648
8575 12:41:09.077092 TX Vref early break, caculate TX vref
8576 12:41:09.080467 TX Vref=16, minBit 0, minWin=22, winSum=377
8577 12:41:09.083972 TX Vref=18, minBit 5, minWin=22, winSum=384
8578 12:41:09.086993 TX Vref=20, minBit 0, minWin=24, winSum=397
8579 12:41:09.090667 TX Vref=22, minBit 0, minWin=24, winSum=402
8580 12:41:09.093495 TX Vref=24, minBit 5, minWin=23, winSum=409
8581 12:41:09.100335 TX Vref=26, minBit 5, minWin=24, winSum=419
8582 12:41:09.103664 TX Vref=28, minBit 0, minWin=25, winSum=422
8583 12:41:09.106477 TX Vref=30, minBit 1, minWin=24, winSum=413
8584 12:41:09.109730 TX Vref=32, minBit 1, minWin=23, winSum=405
8585 12:41:09.113323 TX Vref=34, minBit 0, minWin=23, winSum=396
8586 12:41:09.120067 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 28
8587 12:41:09.120498
8588 12:41:09.123219 Final TX Range 0 Vref 28
8589 12:41:09.123680
8590 12:41:09.124162 ==
8591 12:41:09.126484 Dram Type= 6, Freq= 0, CH_1, rank 0
8592 12:41:09.129963 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8593 12:41:09.130392 ==
8594 12:41:09.130743
8595 12:41:09.131052
8596 12:41:09.132980 TX Vref Scan disable
8597 12:41:09.139852 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8598 12:41:09.140289 == TX Byte 0 ==
8599 12:41:09.143154 u2DelayCellOfst[0]=15 cells (4 PI)
8600 12:41:09.146133 u2DelayCellOfst[1]=15 cells (4 PI)
8601 12:41:09.149801 u2DelayCellOfst[2]=0 cells (0 PI)
8602 12:41:09.153023 u2DelayCellOfst[3]=3 cells (1 PI)
8603 12:41:09.156464 u2DelayCellOfst[4]=7 cells (2 PI)
8604 12:41:09.159811 u2DelayCellOfst[5]=22 cells (6 PI)
8605 12:41:09.163068 u2DelayCellOfst[6]=18 cells (5 PI)
8606 12:41:09.165978 u2DelayCellOfst[7]=7 cells (2 PI)
8607 12:41:09.169531 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8608 12:41:09.172775 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8609 12:41:09.175994 == TX Byte 1 ==
8610 12:41:09.179134 u2DelayCellOfst[8]=0 cells (0 PI)
8611 12:41:09.179561 u2DelayCellOfst[9]=3 cells (1 PI)
8612 12:41:09.182502 u2DelayCellOfst[10]=11 cells (3 PI)
8613 12:41:09.185879 u2DelayCellOfst[11]=7 cells (2 PI)
8614 12:41:09.189312 u2DelayCellOfst[12]=15 cells (4 PI)
8615 12:41:09.192454 u2DelayCellOfst[13]=18 cells (5 PI)
8616 12:41:09.196139 u2DelayCellOfst[14]=18 cells (5 PI)
8617 12:41:09.199003 u2DelayCellOfst[15]=18 cells (5 PI)
8618 12:41:09.202849 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8619 12:41:09.209036 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8620 12:41:09.209478 DramC Write-DBI on
8621 12:41:09.209825 ==
8622 12:41:09.212114 Dram Type= 6, Freq= 0, CH_1, rank 0
8623 12:41:09.219095 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8624 12:41:09.219524 ==
8625 12:41:09.219939
8626 12:41:09.220279
8627 12:41:09.220697 TX Vref Scan disable
8628 12:41:09.223163 == TX Byte 0 ==
8629 12:41:09.226530 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8630 12:41:09.229602 == TX Byte 1 ==
8631 12:41:09.232767 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8632 12:41:09.236242 DramC Write-DBI off
8633 12:41:09.236702
8634 12:41:09.237042 [DATLAT]
8635 12:41:09.237355 Freq=1600, CH1 RK0
8636 12:41:09.237658
8637 12:41:09.239497 DATLAT Default: 0xf
8638 12:41:09.239919 0, 0xFFFF, sum = 0
8639 12:41:09.243185 1, 0xFFFF, sum = 0
8640 12:41:09.245891 2, 0xFFFF, sum = 0
8641 12:41:09.246349 3, 0xFFFF, sum = 0
8642 12:41:09.249307 4, 0xFFFF, sum = 0
8643 12:41:09.249735 5, 0xFFFF, sum = 0
8644 12:41:09.252580 6, 0xFFFF, sum = 0
8645 12:41:09.253011 7, 0xFFFF, sum = 0
8646 12:41:09.255789 8, 0xFFFF, sum = 0
8647 12:41:09.256219 9, 0xFFFF, sum = 0
8648 12:41:09.259728 10, 0xFFFF, sum = 0
8649 12:41:09.260156 11, 0xFFFF, sum = 0
8650 12:41:09.262990 12, 0xFFFF, sum = 0
8651 12:41:09.263427 13, 0xFFFF, sum = 0
8652 12:41:09.265641 14, 0x0, sum = 1
8653 12:41:09.266075 15, 0x0, sum = 2
8654 12:41:09.269353 16, 0x0, sum = 3
8655 12:41:09.269787 17, 0x0, sum = 4
8656 12:41:09.272614 best_step = 15
8657 12:41:09.273037
8658 12:41:09.273374 ==
8659 12:41:09.275969 Dram Type= 6, Freq= 0, CH_1, rank 0
8660 12:41:09.279393 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8661 12:41:09.279865 ==
8662 12:41:09.282371 RX Vref Scan: 1
8663 12:41:09.282794
8664 12:41:09.283127 Set Vref Range= 24 -> 127
8665 12:41:09.283440
8666 12:41:09.285816 RX Vref 24 -> 127, step: 1
8667 12:41:09.286238
8668 12:41:09.288789 RX Delay 11 -> 252, step: 4
8669 12:41:09.289214
8670 12:41:09.292164 Set Vref, RX VrefLevel [Byte0]: 24
8671 12:41:09.295910 [Byte1]: 24
8672 12:41:09.296333
8673 12:41:09.299314 Set Vref, RX VrefLevel [Byte0]: 25
8674 12:41:09.302080 [Byte1]: 25
8675 12:41:09.306008
8676 12:41:09.306432 Set Vref, RX VrefLevel [Byte0]: 26
8677 12:41:09.309023 [Byte1]: 26
8678 12:41:09.313312
8679 12:41:09.313739 Set Vref, RX VrefLevel [Byte0]: 27
8680 12:41:09.316547 [Byte1]: 27
8681 12:41:09.320994
8682 12:41:09.321417 Set Vref, RX VrefLevel [Byte0]: 28
8683 12:41:09.324386 [Byte1]: 28
8684 12:41:09.328553
8685 12:41:09.328981 Set Vref, RX VrefLevel [Byte0]: 29
8686 12:41:09.332037 [Byte1]: 29
8687 12:41:09.336118
8688 12:41:09.336690 Set Vref, RX VrefLevel [Byte0]: 30
8689 12:41:09.339419 [Byte1]: 30
8690 12:41:09.343798
8691 12:41:09.344220 Set Vref, RX VrefLevel [Byte0]: 31
8692 12:41:09.347310 [Byte1]: 31
8693 12:41:09.351801
8694 12:41:09.352222 Set Vref, RX VrefLevel [Byte0]: 32
8695 12:41:09.354999 [Byte1]: 32
8696 12:41:09.358743
8697 12:41:09.359312 Set Vref, RX VrefLevel [Byte0]: 33
8698 12:41:09.362119 [Byte1]: 33
8699 12:41:09.366805
8700 12:41:09.367228 Set Vref, RX VrefLevel [Byte0]: 34
8701 12:41:09.369975 [Byte1]: 34
8702 12:41:09.373974
8703 12:41:09.374399 Set Vref, RX VrefLevel [Byte0]: 35
8704 12:41:09.377430 [Byte1]: 35
8705 12:41:09.381773
8706 12:41:09.382193 Set Vref, RX VrefLevel [Byte0]: 36
8707 12:41:09.385051 [Byte1]: 36
8708 12:41:09.389568
8709 12:41:09.392391 Set Vref, RX VrefLevel [Byte0]: 37
8710 12:41:09.395837 [Byte1]: 37
8711 12:41:09.396259
8712 12:41:09.399688 Set Vref, RX VrefLevel [Byte0]: 38
8713 12:41:09.402298 [Byte1]: 38
8714 12:41:09.402726
8715 12:41:09.405948 Set Vref, RX VrefLevel [Byte0]: 39
8716 12:41:09.408819 [Byte1]: 39
8717 12:41:09.412132
8718 12:41:09.412566 Set Vref, RX VrefLevel [Byte0]: 40
8719 12:41:09.415581 [Byte1]: 40
8720 12:41:09.419938
8721 12:41:09.420382 Set Vref, RX VrefLevel [Byte0]: 41
8722 12:41:09.426186 [Byte1]: 41
8723 12:41:09.426616
8724 12:41:09.429720 Set Vref, RX VrefLevel [Byte0]: 42
8725 12:41:09.432809 [Byte1]: 42
8726 12:41:09.433240
8727 12:41:09.436348 Set Vref, RX VrefLevel [Byte0]: 43
8728 12:41:09.439549 [Byte1]: 43
8729 12:41:09.443157
8730 12:41:09.443587 Set Vref, RX VrefLevel [Byte0]: 44
8731 12:41:09.446403 [Byte1]: 44
8732 12:41:09.450255
8733 12:41:09.450682 Set Vref, RX VrefLevel [Byte0]: 45
8734 12:41:09.453650 [Byte1]: 45
8735 12:41:09.457893
8736 12:41:09.458343 Set Vref, RX VrefLevel [Byte0]: 46
8737 12:41:09.461316 [Byte1]: 46
8738 12:41:09.465532
8739 12:41:09.465961 Set Vref, RX VrefLevel [Byte0]: 47
8740 12:41:09.468988 [Byte1]: 47
8741 12:41:09.472981
8742 12:41:09.473407 Set Vref, RX VrefLevel [Byte0]: 48
8743 12:41:09.476273 [Byte1]: 48
8744 12:41:09.480559
8745 12:41:09.480991 Set Vref, RX VrefLevel [Byte0]: 49
8746 12:41:09.484323 [Byte1]: 49
8747 12:41:09.488324
8748 12:41:09.488787 Set Vref, RX VrefLevel [Byte0]: 50
8749 12:41:09.492198 [Byte1]: 50
8750 12:41:09.495990
8751 12:41:09.496416 Set Vref, RX VrefLevel [Byte0]: 51
8752 12:41:09.499460 [Byte1]: 51
8753 12:41:09.503869
8754 12:41:09.504392 Set Vref, RX VrefLevel [Byte0]: 52
8755 12:41:09.507052 [Byte1]: 52
8756 12:41:09.511294
8757 12:41:09.511850 Set Vref, RX VrefLevel [Byte0]: 53
8758 12:41:09.514603 [Byte1]: 53
8759 12:41:09.518765
8760 12:41:09.519306 Set Vref, RX VrefLevel [Byte0]: 54
8761 12:41:09.525159 [Byte1]: 54
8762 12:41:09.525680
8763 12:41:09.528621 Set Vref, RX VrefLevel [Byte0]: 55
8764 12:41:09.532169 [Byte1]: 55
8765 12:41:09.532635
8766 12:41:09.535431 Set Vref, RX VrefLevel [Byte0]: 56
8767 12:41:09.538834 [Byte1]: 56
8768 12:41:09.541683
8769 12:41:09.542226 Set Vref, RX VrefLevel [Byte0]: 57
8770 12:41:09.544887 [Byte1]: 57
8771 12:41:09.549170
8772 12:41:09.549721 Set Vref, RX VrefLevel [Byte0]: 58
8773 12:41:09.552715 [Byte1]: 58
8774 12:41:09.556970
8775 12:41:09.557390 Set Vref, RX VrefLevel [Byte0]: 59
8776 12:41:09.560231 [Byte1]: 59
8777 12:41:09.564376
8778 12:41:09.564849 Set Vref, RX VrefLevel [Byte0]: 60
8779 12:41:09.567931 [Byte1]: 60
8780 12:41:09.572347
8781 12:41:09.572791 Set Vref, RX VrefLevel [Byte0]: 61
8782 12:41:09.575172 [Byte1]: 61
8783 12:41:09.579698
8784 12:41:09.580117 Set Vref, RX VrefLevel [Byte0]: 62
8785 12:41:09.582760 [Byte1]: 62
8786 12:41:09.587440
8787 12:41:09.588064 Set Vref, RX VrefLevel [Byte0]: 63
8788 12:41:09.590756 [Byte1]: 63
8789 12:41:09.595111
8790 12:41:09.595684 Set Vref, RX VrefLevel [Byte0]: 64
8791 12:41:09.598314 [Byte1]: 64
8792 12:41:09.602489
8793 12:41:09.602906 Set Vref, RX VrefLevel [Byte0]: 65
8794 12:41:09.606099 [Byte1]: 65
8795 12:41:09.610342
8796 12:41:09.610760 Set Vref, RX VrefLevel [Byte0]: 66
8797 12:41:09.613596 [Byte1]: 66
8798 12:41:09.618453
8799 12:41:09.618997 Set Vref, RX VrefLevel [Byte0]: 67
8800 12:41:09.620970 [Byte1]: 67
8801 12:41:09.625919
8802 12:41:09.626337 Set Vref, RX VrefLevel [Byte0]: 68
8803 12:41:09.628481 [Byte1]: 68
8804 12:41:09.632969
8805 12:41:09.633388 Set Vref, RX VrefLevel [Byte0]: 69
8806 12:41:09.636548 [Byte1]: 69
8807 12:41:09.640493
8808 12:41:09.640951 Set Vref, RX VrefLevel [Byte0]: 70
8809 12:41:09.643842 [Byte1]: 70
8810 12:41:09.648321
8811 12:41:09.648864 Set Vref, RX VrefLevel [Byte0]: 71
8812 12:41:09.651519 [Byte1]: 71
8813 12:41:09.656278
8814 12:41:09.656823 Set Vref, RX VrefLevel [Byte0]: 72
8815 12:41:09.658964 [Byte1]: 72
8816 12:41:09.663829
8817 12:41:09.664250 Final RX Vref Byte 0 = 52 to rank0
8818 12:41:09.667330 Final RX Vref Byte 1 = 59 to rank0
8819 12:41:09.670380 Final RX Vref Byte 0 = 52 to rank1
8820 12:41:09.673607 Final RX Vref Byte 1 = 59 to rank1==
8821 12:41:09.676959 Dram Type= 6, Freq= 0, CH_1, rank 0
8822 12:41:09.683187 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8823 12:41:09.683658 ==
8824 12:41:09.684000 DQS Delay:
8825 12:41:09.686708 DQS0 = 0, DQS1 = 0
8826 12:41:09.687130 DQM Delay:
8827 12:41:09.687464 DQM0 = 134, DQM1 = 129
8828 12:41:09.689632 DQ Delay:
8829 12:41:09.692941 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =130
8830 12:41:09.696397 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =128
8831 12:41:09.699499 DQ8 =116, DQ9 =116, DQ10 =130, DQ11 =118
8832 12:41:09.703769 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =138
8833 12:41:09.704328
8834 12:41:09.704738
8835 12:41:09.705057
8836 12:41:09.706536 [DramC_TX_OE_Calibration] TA2
8837 12:41:09.709396 Original DQ_B0 (3 6) =30, OEN = 27
8838 12:41:09.713396 Original DQ_B1 (3 6) =30, OEN = 27
8839 12:41:09.715954 24, 0x0, End_B0=24 End_B1=24
8840 12:41:09.719245 25, 0x0, End_B0=25 End_B1=25
8841 12:41:09.719677 26, 0x0, End_B0=26 End_B1=26
8842 12:41:09.722563 27, 0x0, End_B0=27 End_B1=27
8843 12:41:09.725840 28, 0x0, End_B0=28 End_B1=28
8844 12:41:09.729621 29, 0x0, End_B0=29 End_B1=29
8845 12:41:09.730185 30, 0x0, End_B0=30 End_B1=30
8846 12:41:09.733006 31, 0x4141, End_B0=30 End_B1=30
8847 12:41:09.736081 Byte0 end_step=30 best_step=27
8848 12:41:09.739384 Byte1 end_step=30 best_step=27
8849 12:41:09.742803 Byte0 TX OE(2T, 0.5T) = (3, 3)
8850 12:41:09.745911 Byte1 TX OE(2T, 0.5T) = (3, 3)
8851 12:41:09.746367
8852 12:41:09.746713
8853 12:41:09.752392 [DQSOSCAuto] RK0, (LSB)MR18= 0x190f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8854 12:41:09.756061 CH1 RK0: MR19=303, MR18=190F
8855 12:41:09.762739 CH1_RK0: MR19=0x303, MR18=0x190F, DQSOSC=397, MR23=63, INC=23, DEC=15
8856 12:41:09.763175
8857 12:41:09.765637 ----->DramcWriteLeveling(PI) begin...
8858 12:41:09.766272 ==
8859 12:41:09.768872 Dram Type= 6, Freq= 0, CH_1, rank 1
8860 12:41:09.772144 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8861 12:41:09.772608 ==
8862 12:41:09.775964 Write leveling (Byte 0): 24 => 24
8863 12:41:09.779081 Write leveling (Byte 1): 27 => 27
8864 12:41:09.782519 DramcWriteLeveling(PI) end<-----
8865 12:41:09.782943
8866 12:41:09.783281 ==
8867 12:41:09.785634 Dram Type= 6, Freq= 0, CH_1, rank 1
8868 12:41:09.788621 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8869 12:41:09.792211 ==
8870 12:41:09.792674 [Gating] SW mode calibration
8871 12:41:09.802074 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8872 12:41:09.805071 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8873 12:41:09.808335 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8874 12:41:09.815416 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8875 12:41:09.818802 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8876 12:41:09.821601 1 4 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8877 12:41:09.828317 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8878 12:41:09.831508 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8879 12:41:09.835272 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8880 12:41:09.841402 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8881 12:41:09.844868 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8882 12:41:09.848563 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8883 12:41:09.854953 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8884 12:41:09.857934 1 5 12 | B1->B0 | 2424 3434 | 0 1 | (1 0) (1 0)
8885 12:41:09.861665 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8886 12:41:09.867956 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8887 12:41:09.871633 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8888 12:41:09.874513 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8889 12:41:09.881302 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8890 12:41:09.884398 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8891 12:41:09.887848 1 6 8 | B1->B0 | 2525 2323 | 1 0 | (0 0) (0 0)
8892 12:41:09.894497 1 6 12 | B1->B0 | 4342 2828 | 1 0 | (0 0) (0 0)
8893 12:41:09.897950 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8894 12:41:09.901750 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8895 12:41:09.907949 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8896 12:41:09.911258 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8897 12:41:09.914268 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8898 12:41:09.921163 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8899 12:41:09.924492 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8900 12:41:09.927393 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8901 12:41:09.934177 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8902 12:41:09.937239 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8903 12:41:09.940649 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8904 12:41:09.947392 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8905 12:41:09.950669 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8906 12:41:09.954064 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8907 12:41:09.960302 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8908 12:41:09.964014 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8909 12:41:09.966976 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8910 12:41:09.973917 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8911 12:41:09.977273 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8912 12:41:09.980661 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8913 12:41:09.987493 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8914 12:41:09.990296 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8915 12:41:09.993610 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8916 12:41:10.000339 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8917 12:41:10.000911 Total UI for P1: 0, mck2ui 16
8918 12:41:10.006902 best dqsien dly found for B1: ( 1, 9, 8)
8919 12:41:10.010286 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8920 12:41:10.013543 Total UI for P1: 0, mck2ui 16
8921 12:41:10.017050 best dqsien dly found for B0: ( 1, 9, 12)
8922 12:41:10.020272 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8923 12:41:10.023643 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8924 12:41:10.024082
8925 12:41:10.026562 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8926 12:41:10.030191 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8927 12:41:10.033653 [Gating] SW calibration Done
8928 12:41:10.034076 ==
8929 12:41:10.036480 Dram Type= 6, Freq= 0, CH_1, rank 1
8930 12:41:10.040322 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8931 12:41:10.043385 ==
8932 12:41:10.043810 RX Vref Scan: 0
8933 12:41:10.044147
8934 12:41:10.046759 RX Vref 0 -> 0, step: 1
8935 12:41:10.047182
8936 12:41:10.047554 RX Delay 0 -> 252, step: 8
8937 12:41:10.053099 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8938 12:41:10.056375 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8939 12:41:10.059710 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8940 12:41:10.062782 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8941 12:41:10.069545 iDelay=208, Bit 4, Center 135 (72 ~ 199) 128
8942 12:41:10.072632 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8943 12:41:10.075990 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8944 12:41:10.079260 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8945 12:41:10.083173 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8946 12:41:10.089159 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8947 12:41:10.092919 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8948 12:41:10.095842 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8949 12:41:10.099523 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8950 12:41:10.102938 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8951 12:41:10.109133 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8952 12:41:10.112970 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8953 12:41:10.113395 ==
8954 12:41:10.116183 Dram Type= 6, Freq= 0, CH_1, rank 1
8955 12:41:10.119242 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8956 12:41:10.119669 ==
8957 12:41:10.122797 DQS Delay:
8958 12:41:10.123225 DQS0 = 0, DQS1 = 0
8959 12:41:10.123567 DQM Delay:
8960 12:41:10.125557 DQM0 = 136, DQM1 = 129
8961 12:41:10.125999 DQ Delay:
8962 12:41:10.128943 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8963 12:41:10.132416 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8964 12:41:10.139273 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8965 12:41:10.142143 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8966 12:41:10.142566
8967 12:41:10.142900
8968 12:41:10.143211 ==
8969 12:41:10.146079 Dram Type= 6, Freq= 0, CH_1, rank 1
8970 12:41:10.148863 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8971 12:41:10.149294 ==
8972 12:41:10.149637
8973 12:41:10.149999
8974 12:41:10.152154 TX Vref Scan disable
8975 12:41:10.155455 == TX Byte 0 ==
8976 12:41:10.158755 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8977 12:41:10.162183 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8978 12:41:10.165059 == TX Byte 1 ==
8979 12:41:10.168290 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8980 12:41:10.171950 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8981 12:41:10.172376 ==
8982 12:41:10.174901 Dram Type= 6, Freq= 0, CH_1, rank 1
8983 12:41:10.178479 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8984 12:41:10.181609 ==
8985 12:41:10.192948
8986 12:41:10.196267 TX Vref early break, caculate TX vref
8987 12:41:10.199468 TX Vref=16, minBit 1, minWin=22, winSum=387
8988 12:41:10.203137 TX Vref=18, minBit 0, minWin=24, winSum=393
8989 12:41:10.205945 TX Vref=20, minBit 0, minWin=24, winSum=402
8990 12:41:10.209913 TX Vref=22, minBit 0, minWin=24, winSum=406
8991 12:41:10.213176 TX Vref=24, minBit 0, minWin=24, winSum=413
8992 12:41:10.220016 TX Vref=26, minBit 0, minWin=25, winSum=421
8993 12:41:10.222815 TX Vref=28, minBit 0, minWin=24, winSum=419
8994 12:41:10.225866 TX Vref=30, minBit 0, minWin=24, winSum=418
8995 12:41:10.229430 TX Vref=32, minBit 0, minWin=24, winSum=405
8996 12:41:10.232672 TX Vref=34, minBit 0, minWin=23, winSum=396
8997 12:41:10.239038 [TxChooseVref] Worse bit 0, Min win 25, Win sum 421, Final Vref 26
8998 12:41:10.239475
8999 12:41:10.242292 Final TX Range 0 Vref 26
9000 12:41:10.242719
9001 12:41:10.243069 ==
9002 12:41:10.246495 Dram Type= 6, Freq= 0, CH_1, rank 1
9003 12:41:10.249553 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9004 12:41:10.249998 ==
9005 12:41:10.250350
9006 12:41:10.250663
9007 12:41:10.252658 TX Vref Scan disable
9008 12:41:10.258652 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
9009 12:41:10.259086 == TX Byte 0 ==
9010 12:41:10.262549 u2DelayCellOfst[0]=18 cells (5 PI)
9011 12:41:10.265384 u2DelayCellOfst[1]=11 cells (3 PI)
9012 12:41:10.268801 u2DelayCellOfst[2]=0 cells (0 PI)
9013 12:41:10.272278 u2DelayCellOfst[3]=3 cells (1 PI)
9014 12:41:10.275452 u2DelayCellOfst[4]=7 cells (2 PI)
9015 12:41:10.278900 u2DelayCellOfst[5]=22 cells (6 PI)
9016 12:41:10.282120 u2DelayCellOfst[6]=22 cells (6 PI)
9017 12:41:10.285759 u2DelayCellOfst[7]=7 cells (2 PI)
9018 12:41:10.288626 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9019 12:41:10.292060 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
9020 12:41:10.294966 == TX Byte 1 ==
9021 12:41:10.298721 u2DelayCellOfst[8]=0 cells (0 PI)
9022 12:41:10.299257 u2DelayCellOfst[9]=7 cells (2 PI)
9023 12:41:10.301527 u2DelayCellOfst[10]=11 cells (3 PI)
9024 12:41:10.305054 u2DelayCellOfst[11]=7 cells (2 PI)
9025 12:41:10.308382 u2DelayCellOfst[12]=15 cells (4 PI)
9026 12:41:10.311776 u2DelayCellOfst[13]=18 cells (5 PI)
9027 12:41:10.315125 u2DelayCellOfst[14]=18 cells (5 PI)
9028 12:41:10.318452 u2DelayCellOfst[15]=18 cells (5 PI)
9029 12:41:10.324574 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9030 12:41:10.328371 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9031 12:41:10.328832 DramC Write-DBI on
9032 12:41:10.329172 ==
9033 12:41:10.331692 Dram Type= 6, Freq= 0, CH_1, rank 1
9034 12:41:10.338345 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9035 12:41:10.338796 ==
9036 12:41:10.339151
9037 12:41:10.339493
9038 12:41:10.339806 TX Vref Scan disable
9039 12:41:10.342360 == TX Byte 0 ==
9040 12:41:10.346076 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9041 12:41:10.348664 == TX Byte 1 ==
9042 12:41:10.352009 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9043 12:41:10.355394 DramC Write-DBI off
9044 12:41:10.355823
9045 12:41:10.356204 [DATLAT]
9046 12:41:10.356564 Freq=1600, CH1 RK1
9047 12:41:10.356930
9048 12:41:10.358844 DATLAT Default: 0xf
9049 12:41:10.362099 0, 0xFFFF, sum = 0
9050 12:41:10.362597 1, 0xFFFF, sum = 0
9051 12:41:10.365554 2, 0xFFFF, sum = 0
9052 12:41:10.366011 3, 0xFFFF, sum = 0
9053 12:41:10.368279 4, 0xFFFF, sum = 0
9054 12:41:10.368764 5, 0xFFFF, sum = 0
9055 12:41:10.372571 6, 0xFFFF, sum = 0
9056 12:41:10.373027 7, 0xFFFF, sum = 0
9057 12:41:10.375546 8, 0xFFFF, sum = 0
9058 12:41:10.375999 9, 0xFFFF, sum = 0
9059 12:41:10.378923 10, 0xFFFF, sum = 0
9060 12:41:10.379413 11, 0xFFFF, sum = 0
9061 12:41:10.381959 12, 0xFFFF, sum = 0
9062 12:41:10.382462 13, 0xFFFF, sum = 0
9063 12:41:10.384730 14, 0x0, sum = 1
9064 12:41:10.385192 15, 0x0, sum = 2
9065 12:41:10.388150 16, 0x0, sum = 3
9066 12:41:10.388669 17, 0x0, sum = 4
9067 12:41:10.391235 best_step = 15
9068 12:41:10.391669
9069 12:41:10.392041 ==
9070 12:41:10.394679 Dram Type= 6, Freq= 0, CH_1, rank 1
9071 12:41:10.398158 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9072 12:41:10.398591 ==
9073 12:41:10.401285 RX Vref Scan: 0
9074 12:41:10.401752
9075 12:41:10.402100 RX Vref 0 -> 0, step: 1
9076 12:41:10.402448
9077 12:41:10.404392 RX Delay 11 -> 252, step: 4
9078 12:41:10.411183 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9079 12:41:10.414527 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9080 12:41:10.417863 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9081 12:41:10.421394 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9082 12:41:10.424439 iDelay=203, Bit 4, Center 132 (75 ~ 190) 116
9083 12:41:10.431053 iDelay=203, Bit 5, Center 146 (95 ~ 198) 104
9084 12:41:10.434146 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9085 12:41:10.437212 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9086 12:41:10.440794 iDelay=203, Bit 8, Center 114 (59 ~ 170) 112
9087 12:41:10.444454 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9088 12:41:10.450684 iDelay=203, Bit 10, Center 128 (75 ~ 182) 108
9089 12:41:10.454281 iDelay=203, Bit 11, Center 118 (67 ~ 170) 104
9090 12:41:10.457572 iDelay=203, Bit 12, Center 136 (83 ~ 190) 108
9091 12:41:10.460683 iDelay=203, Bit 13, Center 136 (83 ~ 190) 108
9092 12:41:10.467059 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9093 12:41:10.470362 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9094 12:41:10.470792 ==
9095 12:41:10.473802 Dram Type= 6, Freq= 0, CH_1, rank 1
9096 12:41:10.477023 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9097 12:41:10.477470 ==
9098 12:41:10.480464 DQS Delay:
9099 12:41:10.480938 DQS0 = 0, DQS1 = 0
9100 12:41:10.481296 DQM Delay:
9101 12:41:10.484247 DQM0 = 134, DQM1 = 127
9102 12:41:10.484773 DQ Delay:
9103 12:41:10.487134 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9104 12:41:10.490317 DQ4 =132, DQ5 =146, DQ6 =146, DQ7 =130
9105 12:41:10.497293 DQ8 =114, DQ9 =116, DQ10 =128, DQ11 =118
9106 12:41:10.499829 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =138
9107 12:41:10.500276
9108 12:41:10.500681
9109 12:41:10.501011
9110 12:41:10.503471 [DramC_TX_OE_Calibration] TA2
9111 12:41:10.507127 Original DQ_B0 (3 6) =30, OEN = 27
9112 12:41:10.510209 Original DQ_B1 (3 6) =30, OEN = 27
9113 12:41:10.510671 24, 0x0, End_B0=24 End_B1=24
9114 12:41:10.513609 25, 0x0, End_B0=25 End_B1=25
9115 12:41:10.516691 26, 0x0, End_B0=26 End_B1=26
9116 12:41:10.520350 27, 0x0, End_B0=27 End_B1=27
9117 12:41:10.520826 28, 0x0, End_B0=28 End_B1=28
9118 12:41:10.523421 29, 0x0, End_B0=29 End_B1=29
9119 12:41:10.526585 30, 0x0, End_B0=30 End_B1=30
9120 12:41:10.530363 31, 0x5151, End_B0=30 End_B1=30
9121 12:41:10.533375 Byte0 end_step=30 best_step=27
9122 12:41:10.536856 Byte1 end_step=30 best_step=27
9123 12:41:10.537282 Byte0 TX OE(2T, 0.5T) = (3, 3)
9124 12:41:10.539892 Byte1 TX OE(2T, 0.5T) = (3, 3)
9125 12:41:10.540359
9126 12:41:10.540813
9127 12:41:10.549921 [DQSOSCAuto] RK1, (LSB)MR18= 0x904, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 405 ps
9128 12:41:10.553229 CH1 RK1: MR19=303, MR18=904
9129 12:41:10.556675 CH1_RK1: MR19=0x303, MR18=0x904, DQSOSC=405, MR23=63, INC=22, DEC=15
9130 12:41:10.560034 [RxdqsGatingPostProcess] freq 1600
9131 12:41:10.566186 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9132 12:41:10.569544 best DQS0 dly(2T, 0.5T) = (1, 1)
9133 12:41:10.572906 best DQS1 dly(2T, 0.5T) = (1, 1)
9134 12:41:10.576398 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9135 12:41:10.579331 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9136 12:41:10.582621 best DQS0 dly(2T, 0.5T) = (1, 1)
9137 12:41:10.583045 best DQS1 dly(2T, 0.5T) = (1, 1)
9138 12:41:10.586088 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9139 12:41:10.589713 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9140 12:41:10.592770 Pre-setting of DQS Precalculation
9141 12:41:10.599548 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9142 12:41:10.605973 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9143 12:41:10.612308 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9144 12:41:10.612878
9145 12:41:10.613223
9146 12:41:10.615888 [Calibration Summary] 3200 Mbps
9147 12:41:10.619240 CH 0, Rank 0
9148 12:41:10.619793 SW Impedance : PASS
9149 12:41:10.622571 DUTY Scan : NO K
9150 12:41:10.623000 ZQ Calibration : PASS
9151 12:41:10.625738 Jitter Meter : NO K
9152 12:41:10.629054 CBT Training : PASS
9153 12:41:10.629520 Write leveling : PASS
9154 12:41:10.632354 RX DQS gating : PASS
9155 12:41:10.636167 RX DQ/DQS(RDDQC) : PASS
9156 12:41:10.636681 TX DQ/DQS : PASS
9157 12:41:10.638929 RX DATLAT : PASS
9158 12:41:10.642256 RX DQ/DQS(Engine): PASS
9159 12:41:10.642777 TX OE : PASS
9160 12:41:10.645550 All Pass.
9161 12:41:10.645977
9162 12:41:10.646361 CH 0, Rank 1
9163 12:41:10.649157 SW Impedance : PASS
9164 12:41:10.649764 DUTY Scan : NO K
9165 12:41:10.652507 ZQ Calibration : PASS
9166 12:41:10.655546 Jitter Meter : NO K
9167 12:41:10.656020 CBT Training : PASS
9168 12:41:10.659221 Write leveling : PASS
9169 12:41:10.662635 RX DQS gating : PASS
9170 12:41:10.663108 RX DQ/DQS(RDDQC) : PASS
9171 12:41:10.665625 TX DQ/DQS : PASS
9172 12:41:10.666053 RX DATLAT : PASS
9173 12:41:10.668815 RX DQ/DQS(Engine): PASS
9174 12:41:10.672251 TX OE : PASS
9175 12:41:10.672755 All Pass.
9176 12:41:10.673105
9177 12:41:10.675529 CH 1, Rank 0
9178 12:41:10.675959 SW Impedance : PASS
9179 12:41:10.678840 DUTY Scan : NO K
9180 12:41:10.679270 ZQ Calibration : PASS
9181 12:41:10.682386 Jitter Meter : NO K
9182 12:41:10.685257 CBT Training : PASS
9183 12:41:10.685675 Write leveling : PASS
9184 12:41:10.689137 RX DQS gating : PASS
9185 12:41:10.692445 RX DQ/DQS(RDDQC) : PASS
9186 12:41:10.692913 TX DQ/DQS : PASS
9187 12:41:10.695499 RX DATLAT : PASS
9188 12:41:10.698925 RX DQ/DQS(Engine): PASS
9189 12:41:10.699346 TX OE : PASS
9190 12:41:10.702104 All Pass.
9191 12:41:10.702634
9192 12:41:10.702975 CH 1, Rank 1
9193 12:41:10.705287 SW Impedance : PASS
9194 12:41:10.705728 DUTY Scan : NO K
9195 12:41:10.708936 ZQ Calibration : PASS
9196 12:41:10.711947 Jitter Meter : NO K
9197 12:41:10.712585 CBT Training : PASS
9198 12:41:10.715393 Write leveling : PASS
9199 12:41:10.718949 RX DQS gating : PASS
9200 12:41:10.719369 RX DQ/DQS(RDDQC) : PASS
9201 12:41:10.721951 TX DQ/DQS : PASS
9202 12:41:10.725102 RX DATLAT : PASS
9203 12:41:10.725534 RX DQ/DQS(Engine): PASS
9204 12:41:10.728633 TX OE : PASS
9205 12:41:10.729188 All Pass.
9206 12:41:10.729533
9207 12:41:10.731593 DramC Write-DBI on
9208 12:41:10.735423 PER_BANK_REFRESH: Hybrid Mode
9209 12:41:10.735844 TX_TRACKING: ON
9210 12:41:10.744999 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9211 12:41:10.751483 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9212 12:41:10.757885 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9213 12:41:10.761270 [FAST_K] Save calibration result to emmc
9214 12:41:10.764748 sync common calibartion params.
9215 12:41:10.767615 sync cbt_mode0:1, 1:1
9216 12:41:10.771060 dram_init: ddr_geometry: 2
9217 12:41:10.771468 dram_init: ddr_geometry: 2
9218 12:41:10.774686 dram_init: ddr_geometry: 2
9219 12:41:10.777980 0:dram_rank_size:100000000
9220 12:41:10.781333 1:dram_rank_size:100000000
9221 12:41:10.784449 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9222 12:41:10.787715 DFS_SHUFFLE_HW_MODE: ON
9223 12:41:10.791198 dramc_set_vcore_voltage set vcore to 725000
9224 12:41:10.794112 Read voltage for 1600, 0
9225 12:41:10.794531 Vio18 = 0
9226 12:41:10.794866 Vcore = 725000
9227 12:41:10.797599 Vdram = 0
9228 12:41:10.798121 Vddq = 0
9229 12:41:10.798471 Vmddr = 0
9230 12:41:10.801213 switch to 3200 Mbps bootup
9231 12:41:10.804147 [DramcRunTimeConfig]
9232 12:41:10.804592 PHYPLL
9233 12:41:10.804933 DPM_CONTROL_AFTERK: ON
9234 12:41:10.807937 PER_BANK_REFRESH: ON
9235 12:41:10.810502 REFRESH_OVERHEAD_REDUCTION: ON
9236 12:41:10.813828 CMD_PICG_NEW_MODE: OFF
9237 12:41:10.814247 XRTWTW_NEW_MODE: ON
9238 12:41:10.817626 XRTRTR_NEW_MODE: ON
9239 12:41:10.818169 TX_TRACKING: ON
9240 12:41:10.820657 RDSEL_TRACKING: OFF
9241 12:41:10.821079 DQS Precalculation for DVFS: ON
9242 12:41:10.824042 RX_TRACKING: OFF
9243 12:41:10.824458 HW_GATING DBG: ON
9244 12:41:10.826967 ZQCS_ENABLE_LP4: ON
9245 12:41:10.830404 RX_PICG_NEW_MODE: ON
9246 12:41:10.830857 TX_PICG_NEW_MODE: ON
9247 12:41:10.834101 ENABLE_RX_DCM_DPHY: ON
9248 12:41:10.837256 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9249 12:41:10.837837 DUMMY_READ_FOR_TRACKING: OFF
9250 12:41:10.840563 !!! SPM_CONTROL_AFTERK: OFF
9251 12:41:10.843773 !!! SPM could not control APHY
9252 12:41:10.847006 IMPEDANCE_TRACKING: ON
9253 12:41:10.847427 TEMP_SENSOR: ON
9254 12:41:10.850318 HW_SAVE_FOR_SR: OFF
9255 12:41:10.853490 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9256 12:41:10.856691 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9257 12:41:10.857113 Read ODT Tracking: ON
9258 12:41:10.860308 Refresh Rate DeBounce: ON
9259 12:41:10.863128 DFS_NO_QUEUE_FLUSH: ON
9260 12:41:10.866451 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9261 12:41:10.866871 ENABLE_DFS_RUNTIME_MRW: OFF
9262 12:41:10.870000 DDR_RESERVE_NEW_MODE: ON
9263 12:41:10.873379 MR_CBT_SWITCH_FREQ: ON
9264 12:41:10.873801 =========================
9265 12:41:10.893806 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9266 12:41:10.896550 dram_init: ddr_geometry: 2
9267 12:41:10.915141 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9268 12:41:10.918421 dram_init: dram init end (result: 0)
9269 12:41:10.924989 DRAM-K: Full calibration passed in 24629 msecs
9270 12:41:10.928380 MRC: failed to locate region type 0.
9271 12:41:10.928831 DRAM rank0 size:0x100000000,
9272 12:41:10.931344 DRAM rank1 size=0x100000000
9273 12:41:10.940980 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9274 12:41:10.947671 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9275 12:41:10.958056 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9276 12:41:10.964478 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9277 12:41:10.964932 DRAM rank0 size:0x100000000,
9278 12:41:10.967381 DRAM rank1 size=0x100000000
9279 12:41:10.967802 CBMEM:
9280 12:41:10.971182 IMD: root @ 0xfffff000 254 entries.
9281 12:41:10.974538 IMD: root @ 0xffffec00 62 entries.
9282 12:41:10.980798 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9283 12:41:10.983885 WARNING: RO_VPD is uninitialized or empty.
9284 12:41:10.987259 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9285 12:41:10.994957 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9286 12:41:11.008112 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9287 12:41:11.019117 BS: romstage times (exec / console): total (unknown) / 24123 ms
9288 12:41:11.019639
9289 12:41:11.019977
9290 12:41:11.029746 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9291 12:41:11.032212 ARM64: Exception handlers installed.
9292 12:41:11.035781 ARM64: Testing exception
9293 12:41:11.038725 ARM64: Done test exception
9294 12:41:11.039239 Enumerating buses...
9295 12:41:11.042160 Show all devs... Before device enumeration.
9296 12:41:11.045352 Root Device: enabled 1
9297 12:41:11.048924 CPU_CLUSTER: 0: enabled 1
9298 12:41:11.049349 CPU: 00: enabled 1
9299 12:41:11.052298 Compare with tree...
9300 12:41:11.052752 Root Device: enabled 1
9301 12:41:11.055226 CPU_CLUSTER: 0: enabled 1
9302 12:41:11.058908 CPU: 00: enabled 1
9303 12:41:11.059333 Root Device scanning...
9304 12:41:11.061831 scan_static_bus for Root Device
9305 12:41:11.065378 CPU_CLUSTER: 0 enabled
9306 12:41:11.068513 scan_static_bus for Root Device done
9307 12:41:11.071608 scan_bus: bus Root Device finished in 8 msecs
9308 12:41:11.072033 done
9309 12:41:11.078488 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9310 12:41:11.081927 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9311 12:41:11.088708 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9312 12:41:11.091946 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9313 12:41:11.094723 Allocating resources...
9314 12:41:11.098045 Reading resources...
9315 12:41:11.101234 Root Device read_resources bus 0 link: 0
9316 12:41:11.104663 DRAM rank0 size:0x100000000,
9317 12:41:11.105086 DRAM rank1 size=0x100000000
9318 12:41:11.111611 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9319 12:41:11.112034 CPU: 00 missing read_resources
9320 12:41:11.117866 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9321 12:41:11.121665 Root Device read_resources bus 0 link: 0 done
9322 12:41:11.124391 Done reading resources.
9323 12:41:11.127724 Show resources in subtree (Root Device)...After reading.
9324 12:41:11.131134 Root Device child on link 0 CPU_CLUSTER: 0
9325 12:41:11.134540 CPU_CLUSTER: 0 child on link 0 CPU: 00
9326 12:41:11.144557 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9327 12:41:11.144996 CPU: 00
9328 12:41:11.151019 Root Device assign_resources, bus 0 link: 0
9329 12:41:11.151447 CPU_CLUSTER: 0 missing set_resources
9330 12:41:11.157469 Root Device assign_resources, bus 0 link: 0 done
9331 12:41:11.157895 Done setting resources.
9332 12:41:11.164326 Show resources in subtree (Root Device)...After assigning values.
9333 12:41:11.167848 Root Device child on link 0 CPU_CLUSTER: 0
9334 12:41:11.170811 CPU_CLUSTER: 0 child on link 0 CPU: 00
9335 12:41:11.180909 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9336 12:41:11.181339 CPU: 00
9337 12:41:11.183936 Done allocating resources.
9338 12:41:11.191012 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9339 12:41:11.191445 Enabling resources...
9340 12:41:11.194136 done.
9341 12:41:11.197186 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9342 12:41:11.200668 Initializing devices...
9343 12:41:11.201098 Root Device init
9344 12:41:11.203803 init hardware done!
9345 12:41:11.204233 0x00000018: ctrlr->caps
9346 12:41:11.207085 52.000 MHz: ctrlr->f_max
9347 12:41:11.210514 0.400 MHz: ctrlr->f_min
9348 12:41:11.210954 0x40ff8080: ctrlr->voltages
9349 12:41:11.213976 sclk: 390625
9350 12:41:11.214405 Bus Width = 1
9351 12:41:11.217337 sclk: 390625
9352 12:41:11.217812 Bus Width = 1
9353 12:41:11.220303 Early init status = 3
9354 12:41:11.223752 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9355 12:41:11.227484 in-header: 03 fc 00 00 01 00 00 00
9356 12:41:11.231044 in-data: 00
9357 12:41:11.234560 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9358 12:41:11.241419 in-header: 03 fd 00 00 00 00 00 00
9359 12:41:11.244660 in-data:
9360 12:41:11.248228 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9361 12:41:11.252078 in-header: 03 fc 00 00 01 00 00 00
9362 12:41:11.255576 in-data: 00
9363 12:41:11.258839 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9364 12:41:11.263989 in-header: 03 fd 00 00 00 00 00 00
9365 12:41:11.267067 in-data:
9366 12:41:11.270278 [SSUSB] Setting up USB HOST controller...
9367 12:41:11.273467 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9368 12:41:11.277014 [SSUSB] phy power-on done.
9369 12:41:11.280116 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9370 12:41:11.286713 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9371 12:41:11.290082 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9372 12:41:11.296614 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9373 12:41:11.303371 read SPI 0x50eb0 0x2ad3: 1173 us, 9346 KB/s, 74.768 Mbps
9374 12:41:11.310186 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9375 12:41:11.316617 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9376 12:41:11.323278 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9377 12:41:11.326384 SPM: binary array size = 0x9dc
9378 12:41:11.329596 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9379 12:41:11.336500 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9380 12:41:11.342576 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9381 12:41:11.349312 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9382 12:41:11.352769 configure_display: Starting display init
9383 12:41:11.387062 anx7625_power_on_init: Init interface.
9384 12:41:11.390496 anx7625_disable_pd_protocol: Disabled PD feature.
9385 12:41:11.393584 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9386 12:41:11.421462 anx7625_start_dp_work: Secure OCM version=00
9387 12:41:11.424441 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9388 12:41:11.440104 sp_tx_get_edid_block: EDID Block = 1
9389 12:41:11.542265 Extracted contents:
9390 12:41:11.545667 header: 00 ff ff ff ff ff ff 00
9391 12:41:11.549150 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9392 12:41:11.551786 version: 01 04
9393 12:41:11.555428 basic params: 95 1f 11 78 0a
9394 12:41:11.558870 chroma info: 76 90 94 55 54 90 27 21 50 54
9395 12:41:11.562164 established: 00 00 00
9396 12:41:11.568372 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9397 12:41:11.575156 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9398 12:41:11.578411 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9399 12:41:11.585126 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9400 12:41:11.591598 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9401 12:41:11.594817 extensions: 00
9402 12:41:11.595382 checksum: fb
9403 12:41:11.595752
9404 12:41:11.601043 Manufacturer: IVO Model 57d Serial Number 0
9405 12:41:11.601553 Made week 0 of 2020
9406 12:41:11.604479 EDID version: 1.4
9407 12:41:11.604963 Digital display
9408 12:41:11.608322 6 bits per primary color channel
9409 12:41:11.610984 DisplayPort interface
9410 12:41:11.611465 Maximum image size: 31 cm x 17 cm
9411 12:41:11.614334 Gamma: 220%
9412 12:41:11.614820 Check DPMS levels
9413 12:41:11.621357 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9414 12:41:11.624207 First detailed timing is preferred timing
9415 12:41:11.627978 Established timings supported:
9416 12:41:11.628433 Standard timings supported:
9417 12:41:11.630901 Detailed timings
9418 12:41:11.634491 Hex of detail: 383680a07038204018303c0035ae10000019
9419 12:41:11.641112 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9420 12:41:11.644246 0780 0798 07c8 0820 hborder 0
9421 12:41:11.647345 0438 043b 0447 0458 vborder 0
9422 12:41:11.650795 -hsync -vsync
9423 12:41:11.651284 Did detailed timing
9424 12:41:11.657478 Hex of detail: 000000000000000000000000000000000000
9425 12:41:11.660658 Manufacturer-specified data, tag 0
9426 12:41:11.663807 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9427 12:41:11.667241 ASCII string: InfoVision
9428 12:41:11.670500 Hex of detail: 000000fe00523134304e574635205248200a
9429 12:41:11.673679 ASCII string: R140NWF5 RH
9430 12:41:11.674194 Checksum
9431 12:41:11.677126 Checksum: 0xfb (valid)
9432 12:41:11.680256 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9433 12:41:11.683821 DSI data_rate: 832800000 bps
9434 12:41:11.690502 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9435 12:41:11.693669 anx7625_parse_edid: pixelclock(138800).
9436 12:41:11.696838 hactive(1920), hsync(48), hfp(24), hbp(88)
9437 12:41:11.700244 vactive(1080), vsync(12), vfp(3), vbp(17)
9438 12:41:11.703790 anx7625_dsi_config: config dsi.
9439 12:41:11.710044 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9440 12:41:11.724294 anx7625_dsi_config: success to config DSI
9441 12:41:11.727664 anx7625_dp_start: MIPI phy setup OK.
9442 12:41:11.730493 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9443 12:41:11.733904 mtk_ddp_mode_set invalid vrefresh 60
9444 12:41:11.737133 main_disp_path_setup
9445 12:41:11.737552 ovl_layer_smi_id_en
9446 12:41:11.740428 ovl_layer_smi_id_en
9447 12:41:11.740896 ccorr_config
9448 12:41:11.741231 aal_config
9449 12:41:11.743849 gamma_config
9450 12:41:11.744266 postmask_config
9451 12:41:11.747230 dither_config
9452 12:41:11.750283 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9453 12:41:11.757036 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9454 12:41:11.760583 Root Device init finished in 556 msecs
9455 12:41:11.763543 CPU_CLUSTER: 0 init
9456 12:41:11.769768 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9457 12:41:11.776739 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9458 12:41:11.777192 APU_MBOX 0x190000b0 = 0x10001
9459 12:41:11.779912 APU_MBOX 0x190001b0 = 0x10001
9460 12:41:11.783173 APU_MBOX 0x190005b0 = 0x10001
9461 12:41:11.786594 APU_MBOX 0x190006b0 = 0x10001
9462 12:41:11.792679 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9463 12:41:11.803391 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9464 12:41:11.815590 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9465 12:41:11.822335 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9466 12:41:11.834234 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9467 12:41:11.843150 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9468 12:41:11.846259 CPU_CLUSTER: 0 init finished in 81 msecs
9469 12:41:11.849628 Devices initialized
9470 12:41:11.852942 Show all devs... After init.
9471 12:41:11.853372 Root Device: enabled 1
9472 12:41:11.856339 CPU_CLUSTER: 0: enabled 1
9473 12:41:11.859287 CPU: 00: enabled 1
9474 12:41:11.862931 BS: BS_DEV_INIT run times (exec / console): 214 / 447 ms
9475 12:41:11.866420 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9476 12:41:11.869592 ELOG: NV offset 0x57f000 size 0x1000
9477 12:41:11.875791 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9478 12:41:11.882704 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9479 12:41:11.886005 ELOG: Event(17) added with size 13 at 2023-06-14 12:41:12 UTC
9480 12:41:11.892621 out: cmd=0x121: 03 db 21 01 00 00 00 00
9481 12:41:11.895716 in-header: 03 b6 00 00 2c 00 00 00
9482 12:41:11.908697 in-data: a9 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9483 12:41:11.912323 ELOG: Event(A1) added with size 10 at 2023-06-14 12:41:12 UTC
9484 12:41:11.918688 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9485 12:41:11.925785 ELOG: Event(A0) added with size 9 at 2023-06-14 12:41:12 UTC
9486 12:41:11.928772 elog_add_boot_reason: Logged dev mode boot
9487 12:41:11.935613 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9488 12:41:11.936044 Finalize devices...
9489 12:41:11.938470 Devices finalized
9490 12:41:11.941813 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9491 12:41:11.945256 Writing coreboot table at 0xffe64000
9492 12:41:11.951662 0. 000000000010a000-0000000000113fff: RAMSTAGE
9493 12:41:11.954811 1. 0000000040000000-00000000400fffff: RAM
9494 12:41:11.958212 2. 0000000040100000-000000004032afff: RAMSTAGE
9495 12:41:11.962012 3. 000000004032b000-00000000545fffff: RAM
9496 12:41:11.965201 4. 0000000054600000-000000005465ffff: BL31
9497 12:41:11.971634 5. 0000000054660000-00000000ffe63fff: RAM
9498 12:41:11.975158 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9499 12:41:11.977935 7. 0000000100000000-000000023fffffff: RAM
9500 12:41:11.981529 Passing 5 GPIOs to payload:
9501 12:41:11.984696 NAME | PORT | POLARITY | VALUE
9502 12:41:11.991620 EC in RW | 0x000000aa | low | undefined
9503 12:41:11.994757 EC interrupt | 0x00000005 | low | undefined
9504 12:41:12.001626 TPM interrupt | 0x000000ab | high | undefined
9505 12:41:12.004651 SD card detect | 0x00000011 | high | undefined
9506 12:41:12.007854 speaker enable | 0x00000093 | high | undefined
9507 12:41:12.014391 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9508 12:41:12.018103 in-header: 03 f9 00 00 02 00 00 00
9509 12:41:12.018546 in-data: 02 00
9510 12:41:12.021227 ADC[4]: Raw value=904509 ID=7
9511 12:41:12.024343 ADC[3]: Raw value=213652 ID=1
9512 12:41:12.024819 RAM Code: 0x71
9513 12:41:12.027884 ADC[6]: Raw value=75406 ID=0
9514 12:41:12.030732 ADC[5]: Raw value=213652 ID=1
9515 12:41:12.031171 SKU Code: 0x1
9516 12:41:12.038117 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a169
9517 12:41:12.041227 coreboot table: 964 bytes.
9518 12:41:12.044466 IMD ROOT 0. 0xfffff000 0x00001000
9519 12:41:12.047261 IMD SMALL 1. 0xffffe000 0x00001000
9520 12:41:12.051261 RO MCACHE 2. 0xffffc000 0x00001104
9521 12:41:12.053897 CONSOLE 3. 0xfff7c000 0x00080000
9522 12:41:12.057235 FMAP 4. 0xfff7b000 0x00000452
9523 12:41:12.060677 TIME STAMP 5. 0xfff7a000 0x00000910
9524 12:41:12.063922 VBOOT WORK 6. 0xfff66000 0x00014000
9525 12:41:12.066918 RAMOOPS 7. 0xffe66000 0x00100000
9526 12:41:12.070056 COREBOOT 8. 0xffe64000 0x00002000
9527 12:41:12.070504 IMD small region:
9528 12:41:12.073860 IMD ROOT 0. 0xffffec00 0x00000400
9529 12:41:12.077117 VPD 1. 0xffffeba0 0x0000004c
9530 12:41:12.080368 MMC STATUS 2. 0xffffeb80 0x00000004
9531 12:41:12.086749 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9532 12:41:12.087200 Probing TPM: done!
9533 12:41:12.093531 Connected to device vid:did:rid of 1ae0:0028:00
9534 12:41:12.103448 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9535 12:41:12.107004 Initialized TPM device CR50 revision 0
9536 12:41:12.107491 Checking cr50 for pending updates
9537 12:41:12.113129 Reading cr50 TPM mode
9538 12:41:12.121630 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9539 12:41:12.128481 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9540 12:41:12.168987 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9541 12:41:12.171529 Checking segment from ROM address 0x40100000
9542 12:41:12.175023 Checking segment from ROM address 0x4010001c
9543 12:41:12.181847 Loading segment from ROM address 0x40100000
9544 12:41:12.182468 code (compression=0)
9545 12:41:12.191622 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9546 12:41:12.198241 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9547 12:41:12.198737 it's not compressed!
9548 12:41:12.205139 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9549 12:41:12.211204 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9550 12:41:12.228714 Loading segment from ROM address 0x4010001c
9551 12:41:12.229161 Entry Point 0x80000000
9552 12:41:12.232246 Loaded segments
9553 12:41:12.235567 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9554 12:41:12.241852 Jumping to boot code at 0x80000000(0xffe64000)
9555 12:41:12.248362 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9556 12:41:12.255283 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9557 12:41:12.263285 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9558 12:41:12.266767 Checking segment from ROM address 0x40100000
9559 12:41:12.270204 Checking segment from ROM address 0x4010001c
9560 12:41:12.276420 Loading segment from ROM address 0x40100000
9561 12:41:12.276896 code (compression=1)
9562 12:41:12.283218 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9563 12:41:12.293173 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9564 12:41:12.293706 using LZMA
9565 12:41:12.301864 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9566 12:41:12.308841 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9567 12:41:12.311784 Loading segment from ROM address 0x4010001c
9568 12:41:12.312214 Entry Point 0x54601000
9569 12:41:12.314968 Loaded segments
9570 12:41:12.318147 NOTICE: MT8192 bl31_setup
9571 12:41:12.325310 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9572 12:41:12.328447 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9573 12:41:12.332382 WARNING: region 0:
9574 12:41:12.335412 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9575 12:41:12.335839 WARNING: region 1:
9576 12:41:12.341711 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9577 12:41:12.345152 WARNING: region 2:
9578 12:41:12.348660 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9579 12:41:12.351946 WARNING: region 3:
9580 12:41:12.355362 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9581 12:41:12.358949 WARNING: region 4:
9582 12:41:12.365057 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9583 12:41:12.365496 WARNING: region 5:
9584 12:41:12.368719 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9585 12:41:12.371793 WARNING: region 6:
9586 12:41:12.375086 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9587 12:41:12.378412 WARNING: region 7:
9588 12:41:12.381608 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9589 12:41:12.388336 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9590 12:41:12.391581 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9591 12:41:12.394752 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9592 12:41:12.401490 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9593 12:41:12.404927 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9594 12:41:12.407879 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9595 12:41:12.414892 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9596 12:41:12.418351 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9597 12:41:12.424789 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9598 12:41:12.428540 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9599 12:41:12.431844 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9600 12:41:12.438490 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9601 12:41:12.441575 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9602 12:41:12.444679 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9603 12:41:12.451237 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9604 12:41:12.454676 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9605 12:41:12.461319 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9606 12:41:12.464698 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9607 12:41:12.468167 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9608 12:41:12.475238 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9609 12:41:12.477986 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9610 12:41:12.481853 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9611 12:41:12.488314 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9612 12:41:12.491403 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9613 12:41:12.498495 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9614 12:41:12.501211 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9615 12:41:12.508036 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9616 12:41:12.511344 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9617 12:41:12.515037 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9618 12:41:12.521445 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9619 12:41:12.525049 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9620 12:41:12.528321 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9621 12:41:12.534879 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9622 12:41:12.538175 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9623 12:41:12.541327 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9624 12:41:12.544976 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9625 12:41:12.551469 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9626 12:41:12.554735 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9627 12:41:12.558198 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9628 12:41:12.561460 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9629 12:41:12.567689 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9630 12:41:12.571273 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9631 12:41:12.574452 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9632 12:41:12.578082 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9633 12:41:12.584966 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9634 12:41:12.588317 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9635 12:41:12.590940 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9636 12:41:12.597644 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9637 12:41:12.600858 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9638 12:41:12.604186 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9639 12:41:12.610953 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9640 12:41:12.614138 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9641 12:41:12.620701 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9642 12:41:12.624305 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9643 12:41:12.630575 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9644 12:41:12.633962 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9645 12:41:12.637185 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9646 12:41:12.644075 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9647 12:41:12.647320 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9648 12:41:12.653916 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9649 12:41:12.657239 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9650 12:41:12.663881 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9651 12:41:12.667105 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9652 12:41:12.673598 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9653 12:41:12.677174 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9654 12:41:12.683711 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9655 12:41:12.686888 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9656 12:41:12.690134 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9657 12:41:12.696637 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9658 12:41:12.700050 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9659 12:41:12.706360 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9660 12:41:12.709908 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9661 12:41:12.716692 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9662 12:41:12.719772 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9663 12:41:12.726510 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9664 12:41:12.729974 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9665 12:41:12.733377 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9666 12:41:12.740115 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9667 12:41:12.743178 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9668 12:41:12.749432 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9669 12:41:12.753146 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9670 12:41:12.759331 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9671 12:41:12.763079 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9672 12:41:12.765960 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9673 12:41:12.772652 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9674 12:41:12.776245 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9675 12:41:12.782536 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9676 12:41:12.786466 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9677 12:41:12.792615 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9678 12:41:12.795832 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9679 12:41:12.803169 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9680 12:41:12.805644 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9681 12:41:12.809187 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9682 12:41:12.815990 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9683 12:41:12.819290 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9684 12:41:12.825988 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9685 12:41:12.829526 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9686 12:41:12.832944 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9687 12:41:12.839435 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9688 12:41:12.842760 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9689 12:41:12.846152 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9690 12:41:12.849264 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9691 12:41:12.855591 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9692 12:41:12.859170 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9693 12:41:12.865814 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9694 12:41:12.868932 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9695 12:41:12.872556 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9696 12:41:12.878898 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9697 12:41:12.882469 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9698 12:41:12.889113 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9699 12:41:12.892289 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9700 12:41:12.898902 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9701 12:41:12.902169 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9702 12:41:12.905429 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9703 12:41:12.912331 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9704 12:41:12.915860 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9705 12:41:12.918527 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9706 12:41:12.925408 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9707 12:41:12.928794 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9708 12:41:12.932408 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9709 12:41:12.935539 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9710 12:41:12.942117 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9711 12:41:12.945460 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9712 12:41:12.949037 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9713 12:41:12.955244 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9714 12:41:12.958347 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9715 12:41:12.961603 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9716 12:41:12.968585 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9717 12:41:12.971589 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9718 12:41:12.978692 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9719 12:41:12.981622 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9720 12:41:12.984810 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9721 12:41:12.991670 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9722 12:41:12.994828 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9723 12:41:13.001488 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9724 12:41:13.004741 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9725 12:41:13.008268 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9726 12:41:13.015244 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9727 12:41:13.018355 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9728 12:41:13.024603 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9729 12:41:13.027960 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9730 12:41:13.031651 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9731 12:41:13.038041 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9732 12:41:13.041448 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9733 12:41:13.047650 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9734 12:41:13.051490 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9735 12:41:13.054369 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9736 12:41:13.061143 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9737 12:41:13.064764 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9738 12:41:13.071120 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9739 12:41:13.074395 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9740 12:41:13.077645 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9741 12:41:13.084229 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9742 12:41:13.087626 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9743 12:41:13.093840 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9744 12:41:13.097378 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9745 12:41:13.101126 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9746 12:41:13.107412 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9747 12:41:13.110698 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9748 12:41:13.117115 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9749 12:41:13.120557 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9750 12:41:13.123954 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9751 12:41:13.130338 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9752 12:41:13.133844 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9753 12:41:13.140455 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9754 12:41:13.143895 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9755 12:41:13.146942 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9756 12:41:13.153304 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9757 12:41:13.157041 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9758 12:41:13.163541 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9759 12:41:13.166597 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9760 12:41:13.170050 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9761 12:41:13.176607 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9762 12:41:13.179947 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9763 12:41:13.183522 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9764 12:41:13.189665 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9765 12:41:13.193404 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9766 12:41:13.199642 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9767 12:41:13.203173 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9768 12:41:13.206347 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9769 12:41:13.213140 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9770 12:41:13.216320 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9771 12:41:13.222708 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9772 12:41:13.226039 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9773 12:41:13.232619 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9774 12:41:13.235955 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9775 12:41:13.239300 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9776 12:41:13.246014 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9777 12:41:13.249336 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9778 12:41:13.255779 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9779 12:41:13.259145 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9780 12:41:13.262864 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9781 12:41:13.269016 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9782 12:41:13.272178 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9783 12:41:13.279203 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9784 12:41:13.282318 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9785 12:41:13.288660 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9786 12:41:13.292207 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9787 12:41:13.295215 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9788 12:41:13.302000 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9789 12:41:13.305124 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9790 12:41:13.311743 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9791 12:41:13.315590 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9792 12:41:13.321927 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9793 12:41:13.325544 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9794 12:41:13.328348 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9795 12:41:13.335074 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9796 12:41:13.338298 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9797 12:41:13.345112 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9798 12:41:13.348586 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9799 12:41:13.351609 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9800 12:41:13.358055 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9801 12:41:13.361601 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9802 12:41:13.368045 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9803 12:41:13.371900 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9804 12:41:13.377925 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9805 12:41:13.381462 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9806 12:41:13.384676 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9807 12:41:13.391272 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9808 12:41:13.394599 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9809 12:41:13.401030 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9810 12:41:13.404603 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9811 12:41:13.411455 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9812 12:41:13.414623 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9813 12:41:13.417921 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9814 12:41:13.424582 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9815 12:41:13.427790 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9816 12:41:13.434082 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9817 12:41:13.437557 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9818 12:41:13.441152 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9819 12:41:13.447376 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9820 12:41:13.450751 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9821 12:41:13.454059 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9822 12:41:13.457203 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9823 12:41:13.464319 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9824 12:41:13.466962 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9825 12:41:13.470614 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9826 12:41:13.476738 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9827 12:41:13.480607 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9828 12:41:13.486982 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9829 12:41:13.490127 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9830 12:41:13.493523 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9831 12:41:13.500312 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9832 12:41:13.503242 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9833 12:41:13.506457 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9834 12:41:13.513203 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9835 12:41:13.516423 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9836 12:41:13.522945 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9837 12:41:13.526510 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9838 12:41:13.529934 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9839 12:41:13.536280 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9840 12:41:13.539688 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9841 12:41:13.543526 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9842 12:41:13.549852 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9843 12:41:13.553104 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9844 12:41:13.559641 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9845 12:41:13.562764 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9846 12:41:13.565967 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9847 12:41:13.572908 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9848 12:41:13.576308 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9849 12:41:13.579472 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9850 12:41:13.586200 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9851 12:41:13.589375 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9852 12:41:13.592632 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9853 12:41:13.599502 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9854 12:41:13.602509 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9855 12:41:13.609167 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9856 12:41:13.612377 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9857 12:41:13.615536 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9858 12:41:13.622406 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9859 12:41:13.625460 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9860 12:41:13.629317 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9861 12:41:13.632311 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9862 12:41:13.635489 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9863 12:41:13.642071 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9864 12:41:13.645023 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9865 12:41:13.648719 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9866 12:41:13.655262 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9867 12:41:13.658134 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9868 12:41:13.661751 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9869 12:41:13.664820 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9870 12:41:13.671513 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9871 12:41:13.675063 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9872 12:41:13.681143 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9873 12:41:13.684633 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9874 12:41:13.687882 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9875 12:41:13.694528 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9876 12:41:13.697822 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9877 12:41:13.704203 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9878 12:41:13.707621 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9879 12:41:13.711155 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9880 12:41:13.717818 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9881 12:41:13.720887 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9882 12:41:13.727101 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9883 12:41:13.730476 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9884 12:41:13.737449 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9885 12:41:13.740716 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9886 12:41:13.744494 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9887 12:41:13.750489 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9888 12:41:13.753877 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9889 12:41:13.760743 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9890 12:41:13.763710 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9891 12:41:13.770284 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9892 12:41:13.774246 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9893 12:41:13.777201 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9894 12:41:13.784027 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9895 12:41:13.787247 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9896 12:41:13.793732 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9897 12:41:13.796963 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9898 12:41:13.800478 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9899 12:41:13.806765 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9900 12:41:13.810277 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9901 12:41:13.816669 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9902 12:41:13.820152 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9903 12:41:13.823706 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9904 12:41:13.829615 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9905 12:41:13.833101 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9906 12:41:13.839748 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9907 12:41:13.842866 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9908 12:41:13.849673 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9909 12:41:13.853005 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9910 12:41:13.856341 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9911 12:41:13.862968 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9912 12:41:13.865885 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9913 12:41:13.872755 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9914 12:41:13.875961 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9915 12:41:13.882369 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9916 12:41:13.885897 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9917 12:41:13.889195 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9918 12:41:13.895941 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9919 12:41:13.899100 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9920 12:41:13.905521 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9921 12:41:13.908591 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9922 12:41:13.912464 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9923 12:41:13.919182 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9924 12:41:13.921843 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9925 12:41:13.928790 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9926 12:41:13.932040 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9927 12:41:13.938542 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9928 12:41:13.941774 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9929 12:41:13.945046 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9930 12:41:13.951570 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9931 12:41:13.954803 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9932 12:41:13.961824 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9933 12:41:13.964615 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9934 12:41:13.968018 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9935 12:41:13.974734 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9936 12:41:13.978017 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9937 12:41:13.984852 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9938 12:41:13.988159 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9939 12:41:13.994625 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9940 12:41:13.997813 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9941 12:41:14.001175 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9942 12:41:14.007521 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9943 12:41:14.010874 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9944 12:41:14.017931 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9945 12:41:14.021040 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9946 12:41:14.027918 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9947 12:41:14.030950 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9948 12:41:14.037672 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9949 12:41:14.040851 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9950 12:41:14.043999 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9951 12:41:14.050589 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9952 12:41:14.053674 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9953 12:41:14.060462 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9954 12:41:14.063612 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9955 12:41:14.070716 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9956 12:41:14.074049 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9957 12:41:14.080397 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9958 12:41:14.084353 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9959 12:41:14.086877 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9960 12:41:14.093294 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9961 12:41:14.096557 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9962 12:41:14.103273 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9963 12:41:14.106538 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9964 12:41:14.113634 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9965 12:41:14.116653 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9966 12:41:14.119801 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9967 12:41:14.126393 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9968 12:41:14.129710 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9969 12:41:14.136398 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9970 12:41:14.139357 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9971 12:41:14.146210 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9972 12:41:14.149374 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9973 12:41:14.156155 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9974 12:41:14.159357 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9975 12:41:14.162967 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9976 12:41:14.169421 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9977 12:41:14.172412 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9978 12:41:14.178976 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9979 12:41:14.182327 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9980 12:41:14.189117 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9981 12:41:14.192107 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9982 12:41:14.198957 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9983 12:41:14.202294 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9984 12:41:14.205473 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9985 12:41:14.212438 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9986 12:41:14.215457 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9987 12:41:14.221869 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9988 12:41:14.225075 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9989 12:41:14.232144 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9990 12:41:14.235218 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9991 12:41:14.238174 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9992 12:41:14.245170 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9993 12:41:14.248369 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9994 12:41:14.255078 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9995 12:41:14.258151 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9996 12:41:14.264762 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9997 12:41:14.267715 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9998 12:41:14.274431 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9999 12:41:14.277736 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
10000 12:41:14.284565 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
10001 12:41:14.287450 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
10002 12:41:14.294586 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
10003 12:41:14.297490 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
10004 12:41:14.304215 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
10005 12:41:14.307619 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
10006 12:41:14.313814 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
10007 12:41:14.317033 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
10008 12:41:14.323952 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
10009 12:41:14.326986 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
10010 12:41:14.333941 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10011 12:41:14.336694 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10012 12:41:14.343520 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10013 12:41:14.346720 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10014 12:41:14.353422 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10015 12:41:14.356433 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10016 12:41:14.363365 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10017 12:41:14.366578 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10018 12:41:14.373101 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10019 12:41:14.380204 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10020 12:41:14.383090 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10021 12:41:14.389761 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10022 12:41:14.392930 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10023 12:41:14.396069 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10024 12:41:14.399210 INFO: [APUAPC] vio 0
10025 12:41:14.402763 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10026 12:41:14.409601 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10027 12:41:14.412910 INFO: [APUAPC] D0_APC_0: 0x400510
10028 12:41:14.416265 INFO: [APUAPC] D0_APC_1: 0x0
10029 12:41:14.419277 INFO: [APUAPC] D0_APC_2: 0x1540
10030 12:41:14.419706 INFO: [APUAPC] D0_APC_3: 0x0
10031 12:41:14.426121 INFO: [APUAPC] D1_APC_0: 0xffffffff
10032 12:41:14.429180 INFO: [APUAPC] D1_APC_1: 0xffffffff
10033 12:41:14.432594 INFO: [APUAPC] D1_APC_2: 0x3fffff
10034 12:41:14.433020 INFO: [APUAPC] D1_APC_3: 0x0
10035 12:41:14.435906 INFO: [APUAPC] D2_APC_0: 0xffffffff
10036 12:41:14.442726 INFO: [APUAPC] D2_APC_1: 0xffffffff
10037 12:41:14.445666 INFO: [APUAPC] D2_APC_2: 0x3fffff
10038 12:41:14.446092 INFO: [APUAPC] D2_APC_3: 0x0
10039 12:41:14.448982 INFO: [APUAPC] D3_APC_0: 0xffffffff
10040 12:41:14.452272 INFO: [APUAPC] D3_APC_1: 0xffffffff
10041 12:41:14.455452 INFO: [APUAPC] D3_APC_2: 0x3fffff
10042 12:41:14.458546 INFO: [APUAPC] D3_APC_3: 0x0
10043 12:41:14.462092 INFO: [APUAPC] D4_APC_0: 0xffffffff
10044 12:41:14.465112 INFO: [APUAPC] D4_APC_1: 0xffffffff
10045 12:41:14.468973 INFO: [APUAPC] D4_APC_2: 0x3fffff
10046 12:41:14.472087 INFO: [APUAPC] D4_APC_3: 0x0
10047 12:41:14.475531 INFO: [APUAPC] D5_APC_0: 0xffffffff
10048 12:41:14.478517 INFO: [APUAPC] D5_APC_1: 0xffffffff
10049 12:41:14.481803 INFO: [APUAPC] D5_APC_2: 0x3fffff
10050 12:41:14.485287 INFO: [APUAPC] D5_APC_3: 0x0
10051 12:41:14.488457 INFO: [APUAPC] D6_APC_0: 0xffffffff
10052 12:41:14.491654 INFO: [APUAPC] D6_APC_1: 0xffffffff
10053 12:41:14.494867 INFO: [APUAPC] D6_APC_2: 0x3fffff
10054 12:41:14.498864 INFO: [APUAPC] D6_APC_3: 0x0
10055 12:41:14.501790 INFO: [APUAPC] D7_APC_0: 0xffffffff
10056 12:41:14.505055 INFO: [APUAPC] D7_APC_1: 0xffffffff
10057 12:41:14.508349 INFO: [APUAPC] D7_APC_2: 0x3fffff
10058 12:41:14.511615 INFO: [APUAPC] D7_APC_3: 0x0
10059 12:41:14.514982 INFO: [APUAPC] D8_APC_0: 0xffffffff
10060 12:41:14.518490 INFO: [APUAPC] D8_APC_1: 0xffffffff
10061 12:41:14.521494 INFO: [APUAPC] D8_APC_2: 0x3fffff
10062 12:41:14.525054 INFO: [APUAPC] D8_APC_3: 0x0
10063 12:41:14.528049 INFO: [APUAPC] D9_APC_0: 0xffffffff
10064 12:41:14.531782 INFO: [APUAPC] D9_APC_1: 0xffffffff
10065 12:41:14.534742 INFO: [APUAPC] D9_APC_2: 0x3fffff
10066 12:41:14.538404 INFO: [APUAPC] D9_APC_3: 0x0
10067 12:41:14.541392 INFO: [APUAPC] D10_APC_0: 0xffffffff
10068 12:41:14.544417 INFO: [APUAPC] D10_APC_1: 0xffffffff
10069 12:41:14.548289 INFO: [APUAPC] D10_APC_2: 0x3fffff
10070 12:41:14.551183 INFO: [APUAPC] D10_APC_3: 0x0
10071 12:41:14.554520 INFO: [APUAPC] D11_APC_0: 0xffffffff
10072 12:41:14.557827 INFO: [APUAPC] D11_APC_1: 0xffffffff
10073 12:41:14.561106 INFO: [APUAPC] D11_APC_2: 0x3fffff
10074 12:41:14.564346 INFO: [APUAPC] D11_APC_3: 0x0
10075 12:41:14.568002 INFO: [APUAPC] D12_APC_0: 0xffffffff
10076 12:41:14.571393 INFO: [APUAPC] D12_APC_1: 0xffffffff
10077 12:41:14.574434 INFO: [APUAPC] D12_APC_2: 0x3fffff
10078 12:41:14.577694 INFO: [APUAPC] D12_APC_3: 0x0
10079 12:41:14.580819 INFO: [APUAPC] D13_APC_0: 0xffffffff
10080 12:41:14.584225 INFO: [APUAPC] D13_APC_1: 0xffffffff
10081 12:41:14.588161 INFO: [APUAPC] D13_APC_2: 0x3fffff
10082 12:41:14.590917 INFO: [APUAPC] D13_APC_3: 0x0
10083 12:41:14.594092 INFO: [APUAPC] D14_APC_0: 0xffffffff
10084 12:41:14.597258 INFO: [APUAPC] D14_APC_1: 0xffffffff
10085 12:41:14.600596 INFO: [APUAPC] D14_APC_2: 0x3fffff
10086 12:41:14.604108 INFO: [APUAPC] D14_APC_3: 0x0
10087 12:41:14.607377 INFO: [APUAPC] D15_APC_0: 0xffffffff
10088 12:41:14.610687 INFO: [APUAPC] D15_APC_1: 0xffffffff
10089 12:41:14.614006 INFO: [APUAPC] D15_APC_2: 0x3fffff
10090 12:41:14.617246 INFO: [APUAPC] D15_APC_3: 0x0
10091 12:41:14.620478 INFO: [APUAPC] APC_CON: 0x4
10092 12:41:14.623745 INFO: [NOCDAPC] D0_APC_0: 0x0
10093 12:41:14.627268 INFO: [NOCDAPC] D0_APC_1: 0x0
10094 12:41:14.630628 INFO: [NOCDAPC] D1_APC_0: 0x0
10095 12:41:14.633795 INFO: [NOCDAPC] D1_APC_1: 0xfff
10096 12:41:14.637212 INFO: [NOCDAPC] D2_APC_0: 0x0
10097 12:41:14.640654 INFO: [NOCDAPC] D2_APC_1: 0xfff
10098 12:41:14.641093 INFO: [NOCDAPC] D3_APC_0: 0x0
10099 12:41:14.643295 INFO: [NOCDAPC] D3_APC_1: 0xfff
10100 12:41:14.646998 INFO: [NOCDAPC] D4_APC_0: 0x0
10101 12:41:14.649969 INFO: [NOCDAPC] D4_APC_1: 0xfff
10102 12:41:14.653364 INFO: [NOCDAPC] D5_APC_0: 0x0
10103 12:41:14.656745 INFO: [NOCDAPC] D5_APC_1: 0xfff
10104 12:41:14.660093 INFO: [NOCDAPC] D6_APC_0: 0x0
10105 12:41:14.663362 INFO: [NOCDAPC] D6_APC_1: 0xfff
10106 12:41:14.666762 INFO: [NOCDAPC] D7_APC_0: 0x0
10107 12:41:14.670259 INFO: [NOCDAPC] D7_APC_1: 0xfff
10108 12:41:14.673366 INFO: [NOCDAPC] D8_APC_0: 0x0
10109 12:41:14.676242 INFO: [NOCDAPC] D8_APC_1: 0xfff
10110 12:41:14.676733 INFO: [NOCDAPC] D9_APC_0: 0x0
10111 12:41:14.680150 INFO: [NOCDAPC] D9_APC_1: 0xfff
10112 12:41:14.683306 INFO: [NOCDAPC] D10_APC_0: 0x0
10113 12:41:14.686382 INFO: [NOCDAPC] D10_APC_1: 0xfff
10114 12:41:14.689645 INFO: [NOCDAPC] D11_APC_0: 0x0
10115 12:41:14.692977 INFO: [NOCDAPC] D11_APC_1: 0xfff
10116 12:41:14.696480 INFO: [NOCDAPC] D12_APC_0: 0x0
10117 12:41:14.699451 INFO: [NOCDAPC] D12_APC_1: 0xfff
10118 12:41:14.703542 INFO: [NOCDAPC] D13_APC_0: 0x0
10119 12:41:14.706530 INFO: [NOCDAPC] D13_APC_1: 0xfff
10120 12:41:14.709760 INFO: [NOCDAPC] D14_APC_0: 0x0
10121 12:41:14.712680 INFO: [NOCDAPC] D14_APC_1: 0xfff
10122 12:41:14.716086 INFO: [NOCDAPC] D15_APC_0: 0x0
10123 12:41:14.719753 INFO: [NOCDAPC] D15_APC_1: 0xfff
10124 12:41:14.722852 INFO: [NOCDAPC] APC_CON: 0x4
10125 12:41:14.726379 INFO: [APUAPC] set_apusys_apc done
10126 12:41:14.726800 INFO: [DEVAPC] devapc_init done
10127 12:41:14.732627 INFO: GICv3 without legacy support detected.
10128 12:41:14.735885 INFO: ARM GICv3 driver initialized in EL3
10129 12:41:14.739136 INFO: Maximum SPI INTID supported: 639
10130 12:41:14.742768 INFO: BL31: Initializing runtime services
10131 12:41:14.749298 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10132 12:41:14.753143 INFO: SPM: enable CPC mode
10133 12:41:14.755994 INFO: mcdi ready for mcusys-off-idle and system suspend
10134 12:41:14.762701 INFO: BL31: Preparing for EL3 exit to normal world
10135 12:41:14.765969 INFO: Entry point address = 0x80000000
10136 12:41:14.769150 INFO: SPSR = 0x8
10137 12:41:14.773034
10138 12:41:14.773484
10139 12:41:14.773828
10140 12:41:14.776697 Starting depthcharge on Spherion...
10141 12:41:14.777124
10142 12:41:14.777463 Wipe memory regions:
10143 12:41:14.777777
10144 12:41:14.780117 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10145 12:41:14.780658 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10146 12:41:14.781080 Setting prompt string to ['asurada:']
10147 12:41:14.781495 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10148 12:41:14.782147 [0x00000040000000, 0x00000054600000)
10149 12:41:14.902535
10150 12:41:14.903101 [0x00000054660000, 0x00000080000000)
10151 12:41:15.162674
10152 12:41:15.163204 [0x000000821a7280, 0x000000ffe64000)
10153 12:41:15.907108
10154 12:41:15.907649 [0x00000100000000, 0x00000240000000)
10155 12:41:17.797025
10156 12:41:17.800243 Initializing XHCI USB controller at 0x11200000.
10157 12:41:18.781673
10158 12:41:18.781857 R8152: Initializing
10159 12:41:18.781960
10160 12:41:18.784943 Version 9 (ocp_data = 6010)
10161 12:41:18.785082
10162 12:41:18.788401 R8152: Done initializing
10163 12:41:18.788580
10164 12:41:18.788710 Adding net device
10165 12:41:19.310169
10166 12:41:19.313452 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10167 12:41:19.313573
10168 12:41:19.313640
10169 12:41:19.313702
10170 12:41:19.313985 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10172 12:41:19.414305 asurada: tftpboot 192.168.201.1 10724841/tftp-deploy-p8zw_5gu/kernel/image.itb 10724841/tftp-deploy-p8zw_5gu/kernel/cmdline
10173 12:41:19.414478 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10174 12:41:19.414565 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10175 12:41:19.418799 tftpboot 192.168.201.1 10724841/tftp-deploy-p8zw_5gu/kernel/image.itp-deploy-p8zw_5gu/kernel/cmdline
10176 12:41:19.418896
10177 12:41:19.418965 Waiting for link
10178 12:41:19.621889
10179 12:41:19.622030 done.
10180 12:41:19.622100
10181 12:41:19.622162 MAC: f4:f5:e8:50:de:0a
10182 12:41:19.622226
10183 12:41:19.624549 Sending DHCP discover... done.
10184 12:41:19.624637
10185 12:41:19.628308 Waiting for reply... done.
10186 12:41:19.628410
10187 12:41:19.631643 Sending DHCP request... done.
10188 12:41:19.631720
10189 12:41:19.636647 Waiting for reply... done.
10190 12:41:19.636728
10191 12:41:19.636793 My ip is 192.168.201.14
10192 12:41:19.636854
10193 12:41:19.640087 The DHCP server ip is 192.168.201.1
10194 12:41:19.640176
10195 12:41:19.647052 TFTP server IP predefined by user: 192.168.201.1
10196 12:41:19.647163
10197 12:41:19.653354 Bootfile predefined by user: 10724841/tftp-deploy-p8zw_5gu/kernel/image.itb
10198 12:41:19.653465
10199 12:41:19.656608 Sending tftp read request... done.
10200 12:41:19.656700
10201 12:41:19.659803 Waiting for the transfer...
10202 12:41:19.659916
10203 12:41:19.895960 00000000 ################################################################
10204 12:41:19.896120
10205 12:41:20.140039 00080000 ################################################################
10206 12:41:20.140184
10207 12:41:20.371429 00100000 ################################################################
10208 12:41:20.371577
10209 12:41:20.598366 00180000 ################################################################
10210 12:41:20.598501
10211 12:41:20.823596 00200000 ################################################################
10212 12:41:20.823755
10213 12:41:21.058847 00280000 ################################################################
10214 12:41:21.059012
10215 12:41:21.287311 00300000 ################################################################
10216 12:41:21.287476
10217 12:41:21.515525 00380000 ################################################################
10218 12:41:21.515690
10219 12:41:21.748489 00400000 ################################################################
10220 12:41:21.748654
10221 12:41:21.990044 00480000 ################################################################
10222 12:41:21.990190
10223 12:41:22.236461 00500000 ################################################################
10224 12:41:22.236631
10225 12:41:22.476199 00580000 ################################################################
10226 12:41:22.476334
10227 12:41:22.721736 00600000 ################################################################
10228 12:41:22.721880
10229 12:41:22.952058 00680000 ################################################################
10230 12:41:22.952213
10231 12:41:23.198297 00700000 ################################################################
10232 12:41:23.198447
10233 12:41:23.432621 00780000 ################################################################
10234 12:41:23.432769
10235 12:41:23.667408 00800000 ################################################################
10236 12:41:23.667560
10237 12:41:23.898676 00880000 ################################################################
10238 12:41:23.898830
10239 12:41:24.138072 00900000 ################################################################
10240 12:41:24.138222
10241 12:41:24.375875 00980000 ################################################################
10242 12:41:24.376047
10243 12:41:24.625200 00a00000 ################################################################
10244 12:41:24.625353
10245 12:41:24.863456 00a80000 ################################################################
10246 12:41:24.863594
10247 12:41:25.105329 00b00000 ################################################################
10248 12:41:25.105479
10249 12:41:25.334175 00b80000 ################################################################
10250 12:41:25.334314
10251 12:41:25.575624 00c00000 ################################################################
10252 12:41:25.575769
10253 12:41:25.827443 00c80000 ################################################################
10254 12:41:25.827593
10255 12:41:26.053309 00d00000 ################################################################
10256 12:41:26.053447
10257 12:41:26.293735 00d80000 ################################################################
10258 12:41:26.293871
10259 12:41:26.561286 00e00000 ################################################################
10260 12:41:26.561428
10261 12:41:26.811021 00e80000 ################################################################
10262 12:41:26.811171
10263 12:41:27.058393 00f00000 ################################################################
10264 12:41:27.058533
10265 12:41:27.284425 00f80000 ################################################################
10266 12:41:27.284613
10267 12:41:27.535549 01000000 ################################################################
10268 12:41:27.535687
10269 12:41:27.769409 01080000 ################################################################
10270 12:41:27.769546
10271 12:41:28.012694 01100000 ################################################################
10272 12:41:28.012826
10273 12:41:28.238887 01180000 ################################################################
10274 12:41:28.239042
10275 12:41:28.473284 01200000 ################################################################
10276 12:41:28.473418
10277 12:41:28.709377 01280000 ################################################################
10278 12:41:28.709513
10279 12:41:28.945891 01300000 ################################################################
10280 12:41:28.946051
10281 12:41:29.211789 01380000 ################################################################
10282 12:41:29.211924
10283 12:41:29.463999 01400000 ################################################################
10284 12:41:29.464133
10285 12:41:29.692381 01480000 ################################################################
10286 12:41:29.692564
10287 12:41:29.927241 01500000 ################################################################
10288 12:41:29.927403
10289 12:41:30.167601 01580000 ################################################################
10290 12:41:30.167732
10291 12:41:30.412559 01600000 ################################################################
10292 12:41:30.412689
10293 12:41:30.649866 01680000 ################################################################
10294 12:41:30.650010
10295 12:41:30.897587 01700000 ################################################################
10296 12:41:30.897728
10297 12:41:31.131257 01780000 ################################################################
10298 12:41:31.131391
10299 12:41:31.369591 01800000 ################################################################
10300 12:41:31.369725
10301 12:41:31.613773 01880000 ################################################################
10302 12:41:31.613909
10303 12:41:31.861699 01900000 ################################################################
10304 12:41:31.861828
10305 12:41:32.091784 01980000 ################################################################
10306 12:41:32.091911
10307 12:41:32.342705 01a00000 ################################################################
10308 12:41:32.342848
10309 12:41:32.503081 01a80000 ########################################### done.
10310 12:41:32.503207
10311 12:41:32.507067 The bootfile was 28136414 bytes long.
10312 12:41:32.507248
10313 12:41:32.509804 Sending tftp read request... done.
10314 12:41:32.509965
10315 12:41:32.514080 Waiting for the transfer...
10316 12:41:32.514272
10317 12:41:32.514414 00000000 # done.
10318 12:41:32.516568
10319 12:41:32.523324 Command line loaded dynamically from TFTP file: 10724841/tftp-deploy-p8zw_5gu/kernel/cmdline
10320 12:41:32.523440
10321 12:41:32.542970 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10724841/extract-nfsrootfs-sun8wizn,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10322 12:41:32.543231
10323 12:41:32.543386 Loading FIT.
10324 12:41:32.543527
10325 12:41:32.546337 Image ramdisk-1 has 17645078 bytes.
10326 12:41:32.546597
10327 12:41:32.549225 Image fdt-1 has 46924 bytes.
10328 12:41:32.549504
10329 12:41:32.552547 Image kernel-1 has 10442380 bytes.
10330 12:41:32.552802
10331 12:41:32.562910 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10332 12:41:32.563425
10333 12:41:32.579294 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10334 12:41:32.579889
10335 12:41:32.585991 Choosing best match conf-1 for compat google,spherion-rev2.
10336 12:41:32.586561
10337 12:41:32.593323 Connected to device vid:did:rid of 1ae0:0028:00
10338 12:41:32.600797
10339 12:41:32.604078 tpm_get_response: command 0x17b, return code 0x0
10340 12:41:32.604600
10341 12:41:32.607264 ec_init: CrosEC protocol v3 supported (256, 248)
10342 12:41:32.611156
10343 12:41:32.614419 tpm_cleanup: add release locality here.
10344 12:41:32.614867
10345 12:41:32.615306 Shutting down all USB controllers.
10346 12:41:32.618114
10347 12:41:32.618680 Removing current net device
10348 12:41:32.619138
10349 12:41:32.624487 Exiting depthcharge with code 4 at timestamp: 47279105
10350 12:41:32.625084
10351 12:41:32.627492 LZMA decompressing kernel-1 to 0x821a6718
10352 12:41:32.627916
10353 12:41:32.630652 LZMA decompressing kernel-1 to 0x40000000
10354 12:41:33.941804
10355 12:41:33.942418 jumping to kernel
10356 12:41:33.944169 end: 2.2.4 bootloader-commands (duration 00:00:19) [common]
10357 12:41:33.944753 start: 2.2.5 auto-login-action (timeout 00:04:06) [common]
10358 12:41:33.945175 Setting prompt string to ['Linux version [0-9]']
10359 12:41:33.945550 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10360 12:41:33.945974 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10361 12:41:34.023837
10362 12:41:34.027008 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10363 12:41:34.030881 start: 2.2.5.1 login-action (timeout 00:04:06) [common]
10364 12:41:34.031414 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10365 12:41:34.031899 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10366 12:41:34.032316 Using line separator: #'\n'#
10367 12:41:34.032695 No login prompt set.
10368 12:41:34.033054 Parsing kernel messages
10369 12:41:34.033372 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10370 12:41:34.033937 [login-action] Waiting for messages, (timeout 00:04:06)
10371 12:41:34.049768 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j35827-arm64-gcc-10-defconfig-arm64-chromebook-fwl9s) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jun 14 12:30:40 UTC 2023
10372 12:41:34.053056 [ 0.000000] random: crng init done
10373 12:41:34.056649 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10374 12:41:34.059898 [ 0.000000] efi: UEFI not found.
10375 12:41:34.069545 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10376 12:41:34.076741 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10377 12:41:34.086214 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10378 12:41:34.096899 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10379 12:41:34.103402 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10380 12:41:34.106273 [ 0.000000] printk: bootconsole [mtk8250] enabled
10381 12:41:34.115286 [ 0.000000] NUMA: No NUMA configuration found
10382 12:41:34.121333 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10383 12:41:34.127914 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10384 12:41:34.128451 [ 0.000000] Zone ranges:
10385 12:41:34.134392 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10386 12:41:34.137954 [ 0.000000] DMA32 empty
10387 12:41:34.144836 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10388 12:41:34.147462 [ 0.000000] Movable zone start for each node
10389 12:41:34.151110 [ 0.000000] Early memory node ranges
10390 12:41:34.157745 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10391 12:41:34.164428 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10392 12:41:34.170822 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10393 12:41:34.177407 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10394 12:41:34.184285 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10395 12:41:34.190575 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10396 12:41:34.247668 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10397 12:41:34.253811 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10398 12:41:34.260489 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10399 12:41:34.264001 [ 0.000000] psci: probing for conduit method from DT.
10400 12:41:34.270435 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10401 12:41:34.273942 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10402 12:41:34.280414 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10403 12:41:34.283837 [ 0.000000] psci: SMC Calling Convention v1.2
10404 12:41:34.290281 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10405 12:41:34.293432 [ 0.000000] Detected VIPT I-cache on CPU0
10406 12:41:34.300043 [ 0.000000] CPU features: detected: GIC system register CPU interface
10407 12:41:34.307049 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10408 12:41:34.313239 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10409 12:41:34.320433 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10410 12:41:34.330115 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10411 12:41:34.336197 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10412 12:41:34.339783 [ 0.000000] alternatives: applying boot alternatives
10413 12:41:34.346536 [ 0.000000] Fallback order for Node 0: 0
10414 12:41:34.352794 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10415 12:41:34.356232 [ 0.000000] Policy zone: Normal
10416 12:41:34.376492 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10724841/extract-nfsrootfs-sun8wizn,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10417 12:41:34.386045 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10418 12:41:34.397850 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10419 12:41:34.407997 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10420 12:41:34.414723 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10421 12:41:34.417311 <6>[ 0.000000] software IO TLB: area num 8.
10422 12:41:34.474094 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10423 12:41:34.623156 <6>[ 0.000000] Memory: 7953932K/8385536K available (17984K kernel code, 4098K rwdata, 15868K rodata, 8384K init, 615K bss, 398836K reserved, 32768K cma-reserved)
10424 12:41:34.630068 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10425 12:41:34.636445 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10426 12:41:34.639646 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10427 12:41:34.646649 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10428 12:41:34.653239 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10429 12:41:34.656199 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10430 12:41:34.665988 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10431 12:41:34.673048 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10432 12:41:34.679448 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10433 12:41:34.686040 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10434 12:41:34.689205 <6>[ 0.000000] GICv3: 608 SPIs implemented
10435 12:41:34.692490 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10436 12:41:34.699323 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10437 12:41:34.702146 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10438 12:41:34.708969 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10439 12:41:34.721849 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10440 12:41:34.735616 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10441 12:41:34.741701 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10442 12:41:34.749744 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10443 12:41:34.763251 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10444 12:41:34.769491 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10445 12:41:34.776132 <6>[ 0.009173] Console: colour dummy device 80x25
10446 12:41:34.786593 <6>[ 0.013892] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10447 12:41:34.792613 <6>[ 0.024335] pid_max: default: 32768 minimum: 301
10448 12:41:34.796440 <6>[ 0.029209] LSM: Security Framework initializing
10449 12:41:34.802547 <6>[ 0.034148] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10450 12:41:34.812580 <6>[ 0.041964] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10451 12:41:34.822053 <6>[ 0.051387] cblist_init_generic: Setting adjustable number of callback queues.
10452 12:41:34.825859 <6>[ 0.058840] cblist_init_generic: Setting shift to 3 and lim to 1.
10453 12:41:34.832007 <6>[ 0.065178] cblist_init_generic: Setting shift to 3 and lim to 1.
10454 12:41:34.838730 <6>[ 0.071624] rcu: Hierarchical SRCU implementation.
10455 12:41:34.845475 <6>[ 0.076636] rcu: Max phase no-delay instances is 1000.
10456 12:41:34.851749 <6>[ 0.083681] EFI services will not be available.
10457 12:41:34.855030 <6>[ 0.088681] smp: Bringing up secondary CPUs ...
10458 12:41:34.863047 <6>[ 0.093760] Detected VIPT I-cache on CPU1
10459 12:41:34.870142 <6>[ 0.093832] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10460 12:41:34.876328 <6>[ 0.093863] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10461 12:41:34.880003 <6>[ 0.094205] Detected VIPT I-cache on CPU2
10462 12:41:34.886675 <6>[ 0.094261] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10463 12:41:34.896381 <6>[ 0.094279] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10464 12:41:34.899477 <6>[ 0.094546] Detected VIPT I-cache on CPU3
10465 12:41:34.906060 <6>[ 0.094593] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10466 12:41:34.912661 <6>[ 0.094608] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10467 12:41:34.915865 <6>[ 0.094916] CPU features: detected: Spectre-v4
10468 12:41:34.922626 <6>[ 0.094924] CPU features: detected: Spectre-BHB
10469 12:41:34.925834 <6>[ 0.094930] Detected PIPT I-cache on CPU4
10470 12:41:34.933134 <6>[ 0.094987] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10471 12:41:34.942707 <6>[ 0.095003] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10472 12:41:34.945536 <6>[ 0.095295] Detected PIPT I-cache on CPU5
10473 12:41:34.952076 <6>[ 0.095357] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10474 12:41:34.958878 <6>[ 0.095374] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10475 12:41:34.961979 <6>[ 0.095656] Detected PIPT I-cache on CPU6
10476 12:41:34.972098 <6>[ 0.095721] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10477 12:41:34.978438 <6>[ 0.095737] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10478 12:41:34.981886 <6>[ 0.096037] Detected PIPT I-cache on CPU7
10479 12:41:34.988261 <6>[ 0.096102] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10480 12:41:34.995338 <6>[ 0.096118] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10481 12:41:34.998137 <6>[ 0.096166] smp: Brought up 1 node, 8 CPUs
10482 12:41:35.004980 <6>[ 0.237702] SMP: Total of 8 processors activated.
10483 12:41:35.011299 <6>[ 0.242623] CPU features: detected: 32-bit EL0 Support
10484 12:41:35.018001 <6>[ 0.247986] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10485 12:41:35.024990 <6>[ 0.256786] CPU features: detected: Common not Private translations
10486 12:41:35.031313 <6>[ 0.263302] CPU features: detected: CRC32 instructions
10487 12:41:35.038152 <6>[ 0.268687] CPU features: detected: RCpc load-acquire (LDAPR)
10488 12:41:35.041064 <6>[ 0.274647] CPU features: detected: LSE atomic instructions
10489 12:41:35.047736 <6>[ 0.280464] CPU features: detected: Privileged Access Never
10490 12:41:35.054438 <6>[ 0.286244] CPU features: detected: RAS Extension Support
10491 12:41:35.061231 <6>[ 0.291853] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10492 12:41:35.064119 <6>[ 0.299075] CPU: All CPU(s) started at EL2
10493 12:41:35.071080 <6>[ 0.303391] alternatives: applying system-wide alternatives
10494 12:41:35.081172 <6>[ 0.314098] devtmpfs: initialized
10495 12:41:35.093484 <6>[ 0.323165] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10496 12:41:35.103488 <6>[ 0.333129] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10497 12:41:35.110007 <6>[ 0.341328] pinctrl core: initialized pinctrl subsystem
10498 12:41:35.113607 <6>[ 0.348000] DMI not present or invalid.
10499 12:41:35.120110 <6>[ 0.352413] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10500 12:41:35.129828 <6>[ 0.359289] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10501 12:41:35.136653 <6>[ 0.366864] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10502 12:41:35.146805 <6>[ 0.375085] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10503 12:41:35.149828 <6>[ 0.383326] audit: initializing netlink subsys (disabled)
10504 12:41:35.159699 <5>[ 0.389021] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10505 12:41:35.166406 <6>[ 0.389721] thermal_sys: Registered thermal governor 'step_wise'
10506 12:41:35.172720 <6>[ 0.396986] thermal_sys: Registered thermal governor 'power_allocator'
10507 12:41:35.176288 <6>[ 0.403243] cpuidle: using governor menu
10508 12:41:35.182673 <6>[ 0.414203] NET: Registered PF_QIPCRTR protocol family
10509 12:41:35.189039 <6>[ 0.419689] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10510 12:41:35.196144 <6>[ 0.426791] ASID allocator initialised with 32768 entries
10511 12:41:35.199076 <6>[ 0.433333] Serial: AMBA PL011 UART driver
10512 12:41:35.208899 <4>[ 0.442047] Trying to register duplicate clock ID: 134
10513 12:41:35.265727 <6>[ 0.501560] KASLR enabled
10514 12:41:35.279858 <6>[ 0.509332] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10515 12:41:35.285992 <6>[ 0.516348] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10516 12:41:35.292826 <6>[ 0.522838] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10517 12:41:35.299061 <6>[ 0.529843] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10518 12:41:35.305919 <6>[ 0.536329] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10519 12:41:35.312633 <6>[ 0.543333] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10520 12:41:35.318891 <6>[ 0.549819] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10521 12:41:35.325581 <6>[ 0.556820] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10522 12:41:35.328894 <6>[ 0.564337] ACPI: Interpreter disabled.
10523 12:41:35.338078 <6>[ 0.570746] iommu: Default domain type: Translated
10524 12:41:35.344202 <6>[ 0.575861] iommu: DMA domain TLB invalidation policy: strict mode
10525 12:41:35.347405 <5>[ 0.582517] SCSI subsystem initialized
10526 12:41:35.354597 <6>[ 0.586683] usbcore: registered new interface driver usbfs
10527 12:41:35.361048 <6>[ 0.592417] usbcore: registered new interface driver hub
10528 12:41:35.364273 <6>[ 0.597969] usbcore: registered new device driver usb
10529 12:41:35.371090 <6>[ 0.604060] pps_core: LinuxPPS API ver. 1 registered
10530 12:41:35.381226 <6>[ 0.609251] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10531 12:41:35.384146 <6>[ 0.618593] PTP clock support registered
10532 12:41:35.387796 <6>[ 0.622836] EDAC MC: Ver: 3.0.0
10533 12:41:35.395137 <6>[ 0.627986] FPGA manager framework
10534 12:41:35.401296 <6>[ 0.631668] Advanced Linux Sound Architecture Driver Initialized.
10535 12:41:35.404739 <6>[ 0.638451] vgaarb: loaded
10536 12:41:35.410963 <6>[ 0.641625] clocksource: Switched to clocksource arch_sys_counter
10537 12:41:35.414591 <5>[ 0.648066] VFS: Disk quotas dquot_6.6.0
10538 12:41:35.421203 <6>[ 0.652251] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10539 12:41:35.425001 <6>[ 0.659443] pnp: PnP ACPI: disabled
10540 12:41:35.433252 <6>[ 0.666208] NET: Registered PF_INET protocol family
10541 12:41:35.443439 <6>[ 0.671807] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10542 12:41:35.454416 <6>[ 0.684040] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10543 12:41:35.464243 <6>[ 0.692853] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10544 12:41:35.470895 <6>[ 0.700818] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10545 12:41:35.480456 <6>[ 0.709515] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10546 12:41:35.487217 <6>[ 0.719230] TCP: Hash tables configured (established 65536 bind 65536)
10547 12:41:35.494079 <6>[ 0.726086] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10548 12:41:35.503947 <6>[ 0.733286] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10549 12:41:35.510608 <6>[ 0.740983] NET: Registered PF_UNIX/PF_LOCAL protocol family
10550 12:41:35.513623 <6>[ 0.747142] RPC: Registered named UNIX socket transport module.
10551 12:41:35.520256 <6>[ 0.753298] RPC: Registered udp transport module.
10552 12:41:35.523785 <6>[ 0.758232] RPC: Registered tcp transport module.
10553 12:41:35.530615 <6>[ 0.763166] RPC: Registered tcp NFSv4.1 backchannel transport module.
10554 12:41:35.537182 <6>[ 0.769832] PCI: CLS 0 bytes, default 64
10555 12:41:35.540445 <6>[ 0.774153] Unpacking initramfs...
10556 12:41:35.556708 <6>[ 0.786228] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10557 12:41:35.566209 <6>[ 0.794894] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10558 12:41:35.569714 <6>[ 0.803738] kvm [1]: IPA Size Limit: 40 bits
10559 12:41:35.576062 <6>[ 0.808270] kvm [1]: GICv3: no GICV resource entry
10560 12:41:35.579733 <6>[ 0.813293] kvm [1]: disabling GICv2 emulation
10561 12:41:35.585999 <6>[ 0.817976] kvm [1]: GIC system register CPU interface enabled
10562 12:41:35.589431 <6>[ 0.824141] kvm [1]: vgic interrupt IRQ18
10563 12:41:35.596603 <6>[ 0.828533] kvm [1]: VHE mode initialized successfully
10564 12:41:35.603019 <5>[ 0.834891] Initialise system trusted keyrings
10565 12:41:35.609268 <6>[ 0.839727] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10566 12:41:35.617248 <6>[ 0.849795] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10567 12:41:35.623601 <5>[ 0.856185] NFS: Registering the id_resolver key type
10568 12:41:35.626722 <5>[ 0.861491] Key type id_resolver registered
10569 12:41:35.633411 <5>[ 0.865906] Key type id_legacy registered
10570 12:41:35.639688 <6>[ 0.870187] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10571 12:41:35.646665 <6>[ 0.877110] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10572 12:41:35.653331 <6>[ 0.884874] 9p: Installing v9fs 9p2000 file system support
10573 12:41:35.689379 <5>[ 0.922258] Key type asymmetric registered
10574 12:41:35.692450 <5>[ 0.926591] Asymmetric key parser 'x509' registered
10575 12:41:35.702867 <6>[ 0.931747] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10576 12:41:35.706015 <6>[ 0.939364] io scheduler mq-deadline registered
10577 12:41:35.708889 <6>[ 0.944144] io scheduler kyber registered
10578 12:41:35.728067 <6>[ 0.961056] EINJ: ACPI disabled.
10579 12:41:35.760020 <4>[ 0.986434] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10580 12:41:35.769598 <4>[ 0.997076] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10581 12:41:35.784935 <6>[ 1.017933] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10582 12:41:35.793005 <6>[ 1.025964] printk: console [ttyS0] disabled
10583 12:41:35.821017 <6>[ 1.050617] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10584 12:41:35.827417 <6>[ 1.060097] printk: console [ttyS0] enabled
10585 12:41:35.830792 <6>[ 1.060097] printk: console [ttyS0] enabled
10586 12:41:35.837239 <6>[ 1.068990] printk: bootconsole [mtk8250] disabled
10587 12:41:35.840585 <6>[ 1.068990] printk: bootconsole [mtk8250] disabled
10588 12:41:35.847069 <6>[ 1.080211] SuperH (H)SCI(F) driver initialized
10589 12:41:35.850194 <6>[ 1.085490] msm_serial: driver initialized
10590 12:41:35.865333 <6>[ 1.094504] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10591 12:41:35.874893 <6>[ 1.103054] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10592 12:41:35.881127 <6>[ 1.111597] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10593 12:41:35.891363 <6>[ 1.120225] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10594 12:41:35.901398 <6>[ 1.128934] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10595 12:41:35.908084 <6>[ 1.137650] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10596 12:41:35.917921 <6>[ 1.146192] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10597 12:41:35.924646 <6>[ 1.155010] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10598 12:41:35.935035 <6>[ 1.163554] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10599 12:41:35.946270 <6>[ 1.179335] loop: module loaded
10600 12:41:35.952627 <6>[ 1.185387] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10601 12:41:35.975870 <4>[ 1.208791] mtk-pmic-keys: Failed to locate of_node [id: -1]
10602 12:41:35.982672 <6>[ 1.215600] megasas: 07.719.03.00-rc1
10603 12:41:35.992021 <6>[ 1.225192] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10604 12:41:36.000631 <6>[ 1.233001] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10605 12:41:36.017174 <6>[ 1.249671] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10606 12:41:36.077237 <6>[ 1.303919] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10607 12:41:36.266506 <6>[ 1.499446] Freeing initrd memory: 17224K
10608 12:41:36.276308 <6>[ 1.509389] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10609 12:41:36.287440 <6>[ 1.520314] tun: Universal TUN/TAP device driver, 1.6
10610 12:41:36.291174 <6>[ 1.526371] thunder_xcv, ver 1.0
10611 12:41:36.294450 <6>[ 1.529875] thunder_bgx, ver 1.0
10612 12:41:36.297444 <6>[ 1.533364] nicpf, ver 1.0
10613 12:41:36.307893 <6>[ 1.537382] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10614 12:41:36.311002 <6>[ 1.544858] hns3: Copyright (c) 2017 Huawei Corporation.
10615 12:41:36.317782 <6>[ 1.550444] hclge is initializing
10616 12:41:36.321182 <6>[ 1.554025] e1000: Intel(R) PRO/1000 Network Driver
10617 12:41:36.328119 <6>[ 1.559154] e1000: Copyright (c) 1999-2006 Intel Corporation.
10618 12:41:36.330857 <6>[ 1.565166] e1000e: Intel(R) PRO/1000 Network Driver
10619 12:41:36.337591 <6>[ 1.570382] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10620 12:41:36.344374 <6>[ 1.576570] igb: Intel(R) Gigabit Ethernet Network Driver
10621 12:41:36.351007 <6>[ 1.582220] igb: Copyright (c) 2007-2014 Intel Corporation.
10622 12:41:36.357446 <6>[ 1.588056] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10623 12:41:36.364374 <6>[ 1.594574] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10624 12:41:36.367572 <6>[ 1.601038] sky2: driver version 1.30
10625 12:41:36.373586 <6>[ 1.606022] VFIO - User Level meta-driver version: 0.3
10626 12:41:36.381461 <6>[ 1.614243] usbcore: registered new interface driver usb-storage
10627 12:41:36.387591 <6>[ 1.620686] usbcore: registered new device driver onboard-usb-hub
10628 12:41:36.396455 <6>[ 1.629797] mt6397-rtc mt6359-rtc: registered as rtc0
10629 12:41:36.406457 <6>[ 1.635260] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-14T12:41:37 UTC (1686746497)
10630 12:41:36.410403 <6>[ 1.644822] i2c_dev: i2c /dev entries driver
10631 12:41:36.426811 <6>[ 1.656513] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10632 12:41:36.433464 <6>[ 1.666739] sdhci: Secure Digital Host Controller Interface driver
10633 12:41:36.440310 <6>[ 1.673176] sdhci: Copyright(c) Pierre Ossman
10634 12:41:36.447183 <6>[ 1.678579] Synopsys Designware Multimedia Card Interface Driver
10635 12:41:36.449986 <6>[ 1.685179] mmc0: CQHCI version 5.10
10636 12:41:36.456861 <6>[ 1.685736] sdhci-pltfm: SDHCI platform and OF driver helper
10637 12:41:36.464378 <6>[ 1.697045] ledtrig-cpu: registered to indicate activity on CPUs
10638 12:41:36.474436 <6>[ 1.704397] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10639 12:41:36.478105 <6>[ 1.711791] usbcore: registered new interface driver usbhid
10640 12:41:36.484598 <6>[ 1.717624] usbhid: USB HID core driver
10641 12:41:36.491161 <6>[ 1.721878] spi_master spi0: will run message pump with realtime priority
10642 12:41:36.536255 <6>[ 1.762995] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10643 12:41:36.555034 <6>[ 1.778461] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10644 12:41:36.558695 <6>[ 1.792043] mmc0: Command Queue Engine enabled
10645 12:41:36.565190 <6>[ 1.795174] cros-ec-spi spi0.0: Chrome EC device registered
10646 12:41:36.572028 <6>[ 1.796788] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10647 12:41:36.575306 <6>[ 1.809950] mmcblk0: mmc0:0001 DA4128 116 GiB
10648 12:41:36.591159 <6>[ 1.820848] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10649 12:41:36.597346 <6>[ 1.821186] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10650 12:41:36.603997 <6>[ 1.832292] NET: Registered PF_PACKET protocol family
10651 12:41:36.607654 <6>[ 1.837423] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10652 12:41:36.614241 <6>[ 1.841527] 9pnet: Installing 9P2000 support
10653 12:41:36.617105 <6>[ 1.847309] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10654 12:41:36.623773 <5>[ 1.851193] Key type dns_resolver registered
10655 12:41:36.630457 <6>[ 1.857055] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10656 12:41:36.633731 <6>[ 1.861443] registered taskstats version 1
10657 12:41:36.636669 <5>[ 1.871846] Loading compiled-in X.509 certificates
10658 12:41:36.672128 <4>[ 1.898921] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10659 12:41:36.682191 <4>[ 1.909628] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10660 12:41:36.692434 <3>[ 1.922580] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10661 12:41:36.704328 <6>[ 1.937953] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10662 12:41:36.711845 <6>[ 1.944953] xhci-mtk 11200000.usb: xHCI Host Controller
10663 12:41:36.718208 <6>[ 1.950479] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10664 12:41:36.728032 <6>[ 1.958332] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10665 12:41:36.734908 <6>[ 1.967762] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10666 12:41:36.741533 <6>[ 1.973856] xhci-mtk 11200000.usb: xHCI Host Controller
10667 12:41:36.748146 <6>[ 1.979338] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10668 12:41:36.755163 <6>[ 1.986988] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10669 12:41:36.761532 <6>[ 1.994694] hub 1-0:1.0: USB hub found
10670 12:41:36.764881 <6>[ 1.998716] hub 1-0:1.0: 1 port detected
10671 12:41:36.771621 <6>[ 2.003061] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10672 12:41:36.778437 <6>[ 2.011651] hub 2-0:1.0: USB hub found
10673 12:41:36.781412 <6>[ 2.015667] hub 2-0:1.0: 1 port detected
10674 12:41:36.789365 <6>[ 2.022992] mtk-msdc 11f70000.mmc: Got CD GPIO
10675 12:41:36.807486 <6>[ 2.037490] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10676 12:41:36.814428 <6>[ 2.045528] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10677 12:41:36.824237 <4>[ 2.053500] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10678 12:41:36.834106 <6>[ 2.063168] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10679 12:41:36.840897 <6>[ 2.071250] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10680 12:41:36.847882 <6>[ 2.079286] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10681 12:41:36.857764 <6>[ 2.087207] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10682 12:41:36.863887 <6>[ 2.095029] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10683 12:41:36.873879 <6>[ 2.102853] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10684 12:41:36.884131 <6>[ 2.113516] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10685 12:41:36.891171 <6>[ 2.121898] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10686 12:41:36.900387 <6>[ 2.130250] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10687 12:41:36.907510 <6>[ 2.138594] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10688 12:41:36.917400 <6>[ 2.146941] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10689 12:41:36.927236 <6>[ 2.155286] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10690 12:41:36.934008 <6>[ 2.163629] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10691 12:41:36.944049 <6>[ 2.171973] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10692 12:41:36.950420 <6>[ 2.180316] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10693 12:41:36.960269 <6>[ 2.188660] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10694 12:41:36.966610 <6>[ 2.197003] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10695 12:41:36.976876 <6>[ 2.205346] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10696 12:41:36.984003 <6>[ 2.213691] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10697 12:41:36.993408 <6>[ 2.222034] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10698 12:41:36.999616 <6>[ 2.230380] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10699 12:41:37.006276 <6>[ 2.239279] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10700 12:41:37.013732 <6>[ 2.246734] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10701 12:41:37.020625 <6>[ 2.253768] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10702 12:41:37.031567 <6>[ 2.260854] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10703 12:41:37.037406 <6>[ 2.268132] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10704 12:41:37.047315 <6>[ 2.275033] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10705 12:41:37.053883 <6>[ 2.284172] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10706 12:41:37.063991 <6>[ 2.293299] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10707 12:41:37.074000 <6>[ 2.302604] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10708 12:41:37.084025 <6>[ 2.312079] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10709 12:41:37.093507 <6>[ 2.321554] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10710 12:41:37.103511 <6>[ 2.330681] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10711 12:41:37.110568 <6>[ 2.340155] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10712 12:41:37.119878 <6>[ 2.349283] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10713 12:41:37.130090 <6>[ 2.358589] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10714 12:41:37.140337 <6>[ 2.368755] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10715 12:41:37.151381 <6>[ 2.380269] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10716 12:41:37.157039 <6>[ 2.390300] Trying to probe devices needed for running init ...
10717 12:41:37.171818 <6>[ 2.401900] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10718 12:41:37.199550 <6>[ 2.432418] hub 2-1:1.0: USB hub found
10719 12:41:37.202845 <6>[ 2.436827] hub 2-1:1.0: 3 ports detected
10720 12:41:37.323719 <6>[ 2.553859] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10721 12:41:37.478222 <6>[ 2.711345] hub 1-1:1.0: USB hub found
10722 12:41:37.481766 <6>[ 2.715824] hub 1-1:1.0: 4 ports detected
10723 12:41:37.803784 <6>[ 3.033899] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10724 12:41:37.934764 <6>[ 3.167960] hub 1-1.1:1.0: USB hub found
10725 12:41:37.938056 <6>[ 3.172243] hub 1-1.1:1.0: 4 ports detected
10726 12:41:38.051335 <6>[ 3.281652] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10727 12:41:38.184199 <6>[ 3.418138] hub 1-1.4:1.0: USB hub found
10728 12:41:38.187530 <6>[ 3.422788] hub 1-1.4:1.0: 2 ports detected
10729 12:41:38.263709 <6>[ 3.493900] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10730 12:41:38.451332 <6>[ 3.681900] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10731 12:41:38.536287 <3>[ 3.770111] usb 1-1.1.4: device descriptor read/64, error -32
10732 12:41:38.728348 <3>[ 3.962113] usb 1-1.1.4: device descriptor read/64, error -32
10733 12:41:38.923293 <6>[ 4.153908] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk
10734 12:41:39.111120 <6>[ 4.341900] usb 1-1.1.4: new full-speed USB device number 8 using xhci-mtk
10735 12:41:39.196805 <3>[ 4.430057] usb 1-1.1.4: device descriptor read/64, error -32
10736 12:41:39.387836 <3>[ 4.621982] usb 1-1.1.4: device descriptor read/64, error -32
10737 12:41:39.500419 <6>[ 4.734477] usb 1-1.1-port4: attempt power cycle
10738 12:41:39.587667 <6>[ 4.817899] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10739 12:41:40.111369 <6>[ 5.341898] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10740 12:41:40.117652 <4>[ 5.349250] usb 1-1.1.4: Device not responding to setup address.
10741 12:41:40.328043 <4>[ 5.562189] usb 1-1.1.4: Device not responding to setup address.
10742 12:41:40.539746 <3>[ 5.773892] usb 1-1.1.4: device not accepting address 10, error -71
10743 12:41:40.627438 <6>[ 5.857898] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10744 12:41:40.633776 <4>[ 5.865349] usb 1-1.1.4: Device not responding to setup address.
10745 12:41:40.844115 <4>[ 6.078171] usb 1-1.1.4: Device not responding to setup address.
10746 12:41:41.055696 <3>[ 6.289888] usb 1-1.1.4: device not accepting address 11, error -71
10747 12:41:41.062934 <3>[ 6.296838] usb 1-1.1-port4: unable to enumerate USB device
10748 12:41:49.428422 <6>[ 14.666462] ALSA device list:
10749 12:41:49.434469 <6>[ 14.669718] No soundcards found.
10750 12:41:49.447068 <6>[ 14.682087] Freeing unused kernel memory: 8384K
10751 12:41:49.450421 <6>[ 14.686987] Run /init as init process
10752 12:41:49.461271 Loading, please wait...
10753 12:41:49.480664 Starting version 247.3-7+deb11u2
10754 12:41:49.800034 <6>[ 15.031713] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10755 12:41:49.808831 <6>[ 15.044094] remoteproc remoteproc0: scp is available
10756 12:41:49.819265 <4>[ 15.049794] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10757 12:41:49.825642 <6>[ 15.059716] remoteproc remoteproc0: powering up scp
10758 12:41:49.835328 <4>[ 15.064894] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10759 12:41:49.841968 <3>[ 15.068528] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10760 12:41:49.848898 <3>[ 15.074722] remoteproc remoteproc0: request_firmware failed: -2
10761 12:41:49.859679 <6>[ 15.075904] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10762 12:41:49.865273 <6>[ 15.077022] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10763 12:41:49.871749 <3>[ 15.085990] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10764 12:41:49.878129 <6>[ 15.089562] mc: Linux media interface: v0.10
10765 12:41:49.882178 <6>[ 15.090335] usbcore: registered new interface driver r8152
10766 12:41:49.892350 <3>[ 15.099409] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10767 12:41:49.895578 <6>[ 15.104953] usbcore: registered new interface driver cdc_ether
10768 12:41:49.905739 <4>[ 15.107031] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10769 12:41:49.912406 <4>[ 15.107031] Fallback method does not support PEC.
10770 12:41:49.918699 <3>[ 15.116045] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10771 12:41:49.925274 <4>[ 15.121541] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10772 12:41:49.935314 <3>[ 15.123245] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10773 12:41:49.941655 <3>[ 15.125701] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10774 12:41:49.951797 <6>[ 15.128364] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10775 12:41:49.961487 <6>[ 15.128383] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10776 12:41:49.968454 <4>[ 15.138794] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10777 12:41:49.975103 <3>[ 15.148065] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10778 12:41:49.984965 <3>[ 15.150616] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10779 12:41:49.991121 <3>[ 15.150629] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10780 12:41:49.997961 <6>[ 15.168063] videodev: Linux video capture interface: v2.00
10781 12:41:50.009160 <3>[ 15.174097] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10782 12:41:50.014948 <3>[ 15.174201] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10783 12:41:50.021023 <6>[ 15.183212] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10784 12:41:50.031309 <3>[ 15.191700] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10785 12:41:50.040794 <6>[ 15.230460] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10786 12:41:50.047458 <3>[ 15.232569] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10787 12:41:50.057743 <6>[ 15.238654] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10788 12:41:50.064062 <6>[ 15.243038] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10789 12:41:50.070627 <6>[ 15.243046] pci_bus 0000:00: root bus resource [bus 00-ff]
10790 12:41:50.077504 <6>[ 15.243058] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10791 12:41:50.087439 <6>[ 15.243064] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10792 12:41:50.093945 <6>[ 15.243097] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10793 12:41:50.100456 <6>[ 15.243115] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10794 12:41:50.103616 <6>[ 15.243198] pci 0000:00:00.0: supports D1 D2
10795 12:41:50.113398 <6>[ 15.243201] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10796 12:41:50.120246 <6>[ 15.245046] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10797 12:41:50.126429 <6>[ 15.245154] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10798 12:41:50.133124 <6>[ 15.245184] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10799 12:41:50.139762 <6>[ 15.245205] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10800 12:41:50.150015 <6>[ 15.245223] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10801 12:41:50.153137 <6>[ 15.245337] pci 0000:01:00.0: supports D1 D2
10802 12:41:50.160205 <6>[ 15.245341] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10803 12:41:50.169581 <3>[ 15.246380] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10804 12:41:50.176358 <3>[ 15.246440] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10805 12:41:50.182656 <6>[ 15.253696] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10806 12:41:50.192885 <6>[ 15.253733] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10807 12:41:50.199567 <6>[ 15.253741] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10808 12:41:50.205866 <6>[ 15.253753] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10809 12:41:50.215960 <6>[ 15.253770] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10810 12:41:50.222795 <6>[ 15.253786] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10811 12:41:50.229266 <6>[ 15.253801] pci 0000:00:00.0: PCI bridge to [bus 01]
10812 12:41:50.236019 <6>[ 15.253808] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10813 12:41:50.242160 <6>[ 15.253948] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10814 12:41:50.248928 <6>[ 15.254991] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10815 12:41:50.255622 <3>[ 15.261764] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10816 12:41:50.265234 <3>[ 15.261773] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10817 12:41:50.272073 <3>[ 15.261781] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10818 12:41:50.278694 <6>[ 15.270259] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10819 12:41:50.288608 <6>[ 15.278759] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10820 12:41:50.295033 <3>[ 15.279936] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10821 12:41:50.305431 <3>[ 15.280008] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10822 12:41:50.311618 <6>[ 15.289667] usbcore: registered new interface driver r8153_ecm
10823 12:41:50.314934 <6>[ 15.306197] Bluetooth: Core ver 2.22
10824 12:41:50.324778 <4>[ 15.307875] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10825 12:41:50.331615 <4>[ 15.307885] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10826 12:41:50.341366 <5>[ 15.308446] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10827 12:41:50.348284 <5>[ 15.320686] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10828 12:41:50.351358 <6>[ 15.326997] NET: Registered PF_BLUETOOTH protocol family
10829 12:41:50.357879 <6>[ 15.328165] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10830 12:41:50.371324 <6>[ 15.329398] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10831 12:41:50.377461 <6>[ 15.329539] usbcore: registered new interface driver uvcvideo
10832 12:41:50.380797 <6>[ 15.333273] r8152 1-1.1.1:1.0 eth0: v1.12.13
10833 12:41:50.390694 <4>[ 15.333818] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10834 12:41:50.397780 <6>[ 15.333828] cfg80211: failed to load regulatory.db
10835 12:41:50.404130 <6>[ 15.340656] Bluetooth: HCI device and connection manager initialized
10836 12:41:50.407456 <6>[ 15.340679] Bluetooth: HCI socket layer initialized
10837 12:41:50.414086 <6>[ 15.346279] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10838 12:41:50.420400 <6>[ 15.352056] Bluetooth: L2CAP socket layer initialized
10839 12:41:50.423872 <6>[ 15.352082] Bluetooth: SCO socket layer initialized
10840 12:41:50.430742 <6>[ 15.354873] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10841 12:41:50.441512 <6>[ 15.676814] usbcore: registered new interface driver btusb
10842 12:41:50.451635 <4>[ 15.677289] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10843 12:41:50.458076 <3>[ 15.693164] Bluetooth: hci0: Failed to load firmware file (-2)
10844 12:41:50.464689 <3>[ 15.699251] Bluetooth: hci0: Failed to set up firmware (-2)
10845 12:41:50.474503 <4>[ 15.705414] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10846 12:41:50.524953 <6>[ 15.756844] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10847 12:41:50.531648 <6>[ 15.764359] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10848 12:41:50.555668 <6>[ 15.791040] mt7921e 0000:01:00.0: ASIC revision: 79610010
10849 12:41:50.660981 <4>[ 15.889329] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10850 12:41:50.664142 Begin: Loading essential drivers ... done.
10851 12:41:50.670660 Begin: Running /scripts/init-premount ... done.
10852 12:41:50.677363 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10853 12:41:50.683738 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10854 12:41:50.687618 Device /sys/class/net/enxf4f5e850de0a found
10855 12:41:50.690309 done.
10856 12:41:50.722628 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10857 12:41:50.779252 <4>[ 16.007946] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10858 12:41:50.899398 <4>[ 16.127570] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10859 12:41:51.014693 <4>[ 16.243456] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10860 12:41:51.130720 <4>[ 16.359293] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10861 12:41:51.246366 <4>[ 16.475236] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10862 12:41:51.362391 <4>[ 16.591248] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10863 12:41:51.478426 <4>[ 16.707162] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10864 12:41:51.594234 <4>[ 16.823064] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10865 12:41:51.710466 <4>[ 16.939054] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10866 12:41:51.804487 <6>[ 17.039886] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
10867 12:41:51.817719 <3>[ 17.052875] mt7921e 0000:01:00.0: hardware init failed
10868 12:41:51.899817 IP-Config: no response after 2 secs - giving up
10869 12:41:51.938011 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10870 12:41:51.940943 IP-Config: enxf4f5e850de0a complete (dhcp from 192.168.201.1):
10871 12:41:51.948129 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10872 12:41:51.957795 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10873 12:41:51.964081 host : mt8192-asurada-spherion-r0-cbg-9
10874 12:41:51.970859 domain : lava-rack
10875 12:41:51.974384 rootserver: 192.168.201.1 rootpath:
10876 12:41:51.974463 filename :
10877 12:41:51.986346 done.
10878 12:41:51.992812 Begin: Running /scripts/nfs-bottom ... done.
10879 12:41:52.010640 Begin: Running /scripts/init-bottom ... done.
10880 12:41:53.091279 <6>[ 18.326512] NET: Registered PF_INET6 protocol family
10881 12:41:53.098176 <6>[ 18.333452] Segment Routing with IPv6
10882 12:41:53.101468 <6>[ 18.337441] In-situ OAM (IOAM) with IPv6
10883 12:41:53.203302 <30>[ 18.419091] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10884 12:41:53.206575 <30>[ 18.442877] systemd[1]: Detected architecture arm64.
10885 12:41:53.224969
10886 12:41:53.228149 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10887 12:41:53.228254
10888 12:41:53.244228 <30>[ 18.479475] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10889 12:41:53.694221 <30>[ 18.926497] systemd[1]: Queued start job for default target Graphical Interface.
10890 12:41:53.723365 <30>[ 18.959033] systemd[1]: Created slice system-getty.slice.
10891 12:41:53.730254 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10892 12:41:53.746997 <30>[ 18.982733] systemd[1]: Created slice system-modprobe.slice.
10893 12:41:53.753813 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10894 12:41:53.771691 <30>[ 19.007079] systemd[1]: Created slice system-serial\x2dgetty.slice.
10895 12:41:53.781743 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10896 12:41:53.794980 <30>[ 19.030438] systemd[1]: Created slice User and Session Slice.
10897 12:41:53.801775 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10898 12:41:53.821789 <30>[ 19.054108] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10899 12:41:53.828834 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10900 12:41:53.850158 <30>[ 19.082087] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10901 12:41:53.856834 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10902 12:41:53.877220 <30>[ 19.106017] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10903 12:41:53.883517 <30>[ 19.118044] systemd[1]: Reached target Local Encrypted Volumes.
10904 12:41:53.890057 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10905 12:41:53.906639 <30>[ 19.142134] systemd[1]: Reached target Paths.
10906 12:41:53.909845 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10907 12:41:53.926572 <30>[ 19.162209] systemd[1]: Reached target Remote File Systems.
10908 12:41:53.933226 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10909 12:41:53.950843 <30>[ 19.186170] systemd[1]: Reached target Slices.
10910 12:41:53.957354 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10911 12:41:53.970800 <30>[ 19.205961] systemd[1]: Reached target Swap.
10912 12:41:53.973733 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10913 12:41:53.994353 <30>[ 19.226415] systemd[1]: Listening on initctl Compatibility Named Pipe.
10914 12:41:54.000858 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10915 12:41:54.007375 <30>[ 19.241778] systemd[1]: Listening on Journal Audit Socket.
10916 12:41:54.013745 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10917 12:41:54.027534 <30>[ 19.262776] systemd[1]: Listening on Journal Socket (/dev/log).
10918 12:41:54.033547 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10919 12:41:54.051398 <30>[ 19.286721] systemd[1]: Listening on Journal Socket.
10920 12:41:54.057579 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10921 12:41:54.075045 <30>[ 19.307144] systemd[1]: Listening on Network Service Netlink Socket.
10922 12:41:54.081123 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10923 12:41:54.096604 <30>[ 19.332226] systemd[1]: Listening on udev Control Socket.
10924 12:41:54.103240 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10925 12:41:54.118987 <30>[ 19.354208] systemd[1]: Listening on udev Kernel Socket.
10926 12:41:54.125212 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10927 12:41:54.174681 <30>[ 19.410202] systemd[1]: Mounting Huge Pages File System...
10928 12:41:54.181317 Mounting [0;1;39mHuge Pages File System[0m...
10929 12:41:54.196651 <30>[ 19.431997] systemd[1]: Mounting POSIX Message Queue File System...
10930 12:41:54.203470 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10931 12:41:54.220905 <30>[ 19.456135] systemd[1]: Mounting Kernel Debug File System...
10932 12:41:54.226996 Mounting [0;1;39mKernel Debug File System[0m...
10933 12:41:54.246074 <30>[ 19.478218] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10934 12:41:54.286561 <30>[ 19.518565] systemd[1]: Starting Create list of static device nodes for the current kernel...
10935 12:41:54.292831 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10936 12:41:54.316702 <30>[ 19.552436] systemd[1]: Starting Load Kernel Module configfs...
10937 12:41:54.323322 Starting [0;1;39mLoad Kernel Module configfs[0m...
10938 12:41:54.341104 <30>[ 19.576382] systemd[1]: Starting Load Kernel Module drm...
10939 12:41:54.347238 Starting [0;1;39mLoad Kernel Module drm[0m...
10940 12:41:54.365410 <30>[ 19.600322] systemd[1]: Starting Load Kernel Module fuse...
10941 12:41:54.371109 Starting [0;1;39mLoad Kernel Module fuse[0m...
10942 12:41:54.398403 <30>[ 19.630416] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10943 12:41:54.404925 <6>[ 19.630607] fuse: init (API version 7.37)
10944 12:41:54.411432 <30>[ 19.646433] systemd[1]: Starting Journal Service...
10945 12:41:54.414365 Starting [0;1;39mJournal Service[0m...
10946 12:41:54.436881 <30>[ 19.672543] systemd[1]: Starting Load Kernel Modules...
10947 12:41:54.443612 Starting [0;1;39mLoad Kernel Modules[0m...
10948 12:41:54.464319 <30>[ 19.696577] systemd[1]: Starting Remount Root and Kernel File Systems...
10949 12:41:54.470750 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10950 12:41:54.485778 <30>[ 19.721103] systemd[1]: Starting Coldplug All udev Devices...
10951 12:41:54.491786 Starting [0;1;39mColdplug All udev Devices[0m...
10952 12:41:54.508782 <30>[ 19.744726] systemd[1]: Mounted Huge Pages File System.
10953 12:41:54.515679 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10954 12:41:54.531043 <30>[ 19.766496] systemd[1]: Mounted POSIX Message Queue File System.
10955 12:41:54.537729 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10956 12:41:54.554831 <30>[ 19.790283] systemd[1]: Mounted Kernel Debug File System.
10957 12:41:54.568485 [[0;32m OK [0m] Mounted [0;1;39mKernel Debu<3>[ 19.799306] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10958 12:41:54.571168 g File System[0m.
10959 12:41:54.591179 <30>[ 19.822863] systemd[1]: Finished Create list of static device nodes for the current kernel.
10960 12:41:54.601590 [[0;32m OK [0m] Finished [0<3>[ 19.833396] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10961 12:41:54.607407 ;1;39mCreate list of st… nodes for the current kernel[0m.
10962 12:41:54.623183 <30>[ 19.858871] systemd[1]: modprobe@configfs.service: Succeeded.
10963 12:41:54.630464 <30>[ 19.865551] systemd[1]: Finished Load Kernel Module configfs.
10964 12:41:54.636596 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10965 12:41:54.653067 <3>[ 19.885558] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10966 12:41:54.659827 <30>[ 19.895695] systemd[1]: modprobe@drm.service: Succeeded.
10967 12:41:54.666779 <30>[ 19.901946] systemd[1]: Finished Load Kernel Module drm.
10968 12:41:54.673158 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10969 12:41:54.685794 <3>[ 19.918350] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10970 12:41:54.692884 <30>[ 19.928452] systemd[1]: modprobe@fuse.service: Succeeded.
10971 12:41:54.699371 <30>[ 19.934819] systemd[1]: Finished Load Kernel Module fuse.
10972 12:41:54.706098 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10973 12:41:54.722192 <3>[ 19.954477] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10974 12:41:54.729686 <30>[ 19.965253] systemd[1]: Finished Load Kernel Modules.
10975 12:41:54.736318 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10976 12:41:54.751948 <30>[ 19.987128] systemd[1]: Finished Remount Root and Kernel File Systems.
10977 12:41:54.761777 <3>[ 19.989637] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10978 12:41:54.768021 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10979 12:41:54.795154 <3>[ 20.027777] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10980 12:41:54.822311 <30>[ 20.057613] systemd[1]: Mounting FUSE Control File System...
10981 12:41:54.832484 <3>[ 20.060892] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10982 12:41:54.839230 Mounting [0;1;39mFUSE Control File System[0m...
10983 12:41:54.853254 <30>[ 20.088385] systemd[1]: Mounting Kernel Configuration File System...
10984 12:41:54.860333 Mounting [0;1;39mKernel Configuration File System[0m...
10985 12:41:54.885194 <30>[ 20.117187] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10986 12:41:54.895216 <30>[ 20.126223] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10987 12:41:54.902950 <30>[ 20.138559] systemd[1]: Starting Load/Save Random Seed...
10988 12:41:54.909421 Starting [0;1;39mLoad/Save Random Seed[0m...
10989 12:41:54.942900 <30>[ 20.178432] systemd[1]: Starting Apply Kernel Variables...
10990 12:41:54.949579 Starting [0;1;39mApply Kernel Variables[0m...
10991 12:41:54.965563 <30>[ 20.201204] systemd[1]: Starting Create System Users...
10992 12:41:54.972067 <4>[ 20.202816] power_supply_show_property: 2 callbacks suppressed
10993 12:41:54.982095 <3>[ 20.202825] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10994 12:41:54.985972 Starting [0;1;39mCreate System Users[0m...
10995 12:41:54.995574 <3>[ 20.226778] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10996 12:41:55.004204 <30>[ 20.239408] systemd[1]: Started Journal Service.
10997 12:41:55.010367 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10998 12:41:55.034587 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0<3>[ 20.264894] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10999 12:41:55.034690 m.
11000 12:41:55.057755 [[0;32m OK [0m] Mounted [0;<3>[ 20.288541] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11001 12:41:55.074563 1;39mKernel Conf<4>[ 20.298226] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11002 12:41:55.084543 iguration File S<3>[ 20.307851] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11003 12:41:55.091170 <3>[ 20.315212] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11004 12:41:55.094323 ystem[0m.
11005 12:41:55.111635 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
11006 12:41:55.127927 <3>[ 20.360354] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11007 12:41:55.134565 See 'systemctl status systemd-udev-trigger.service' for details.
11008 12:41:55.161580 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.<3>[ 20.391605] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11009 12:41:55.161681
11010 12:41:55.175711 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
11011 12:41:55.189436 <3>[ 20.421689] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11012 12:41:55.195930 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
11013 12:41:55.223798 <3>[ 20.456072] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11014 12:41:55.242872 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
11015 12:41:55.259101 <3>[ 20.491345] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11016 12:41:55.268938 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11017 12:41:55.325756 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11018 12:41:55.343008 <46>[ 20.575474] systemd-journald[300]: Received client request to flush runtime journal.
11019 12:41:55.349784 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11020 12:41:55.370871 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11021 12:41:55.434369 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11022 12:41:56.713605 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11023 12:41:56.766904 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11024 12:41:56.788330 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11025 12:41:56.811086 Starting [0;1;39mNetwork Service[0m...
11026 12:41:57.143191 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11027 12:41:57.162797 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11028 12:41:57.214849 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11029 12:41:57.395236 <6>[ 22.631187] remoteproc remoteproc0: powering up scp
11030 12:41:57.418814 <4>[ 22.651496] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11031 12:41:57.425866 <3>[ 22.661413] remoteproc remoteproc0: request_firmware failed: -2
11032 12:41:57.435215 <3>[ 22.667613] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
11033 12:41:57.517472 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11034 12:41:57.534449 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11035 12:41:57.550563 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
11036 12:41:57.570734 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11037 12:41:57.596732 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11038 12:41:57.643224 Starting [0;1;39mNetwork Name Resolution[0m...
11039 12:41:57.661030 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11040 12:41:57.685941 Starting [0;1;39mNetwork Time Synchronization[0m...
11041 12:41:57.704781 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11042 12:41:57.723358 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11043 12:41:57.761657 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11044 12:41:57.922660 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11045 12:41:57.938869 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11046 12:41:57.961263 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11047 12:41:57.973892 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11048 12:41:57.989956 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11049 12:41:58.085460 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
11050 12:41:58.131443 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
11051 12:41:58.164422 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
11052 12:41:58.196249 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11053 12:41:58.210153 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11054 12:41:58.556348 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11055 12:41:58.570112 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11056 12:41:58.585810 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11057 12:41:58.618546 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11058 12:41:58.954399 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11059 12:41:59.322991 Starting [0;1;39mUser Login Management[0m...
11060 12:41:59.339357 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11061 12:41:59.355478 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11062 12:41:59.372882 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11063 12:41:59.410406 Starting [0;1;39mPermit User Sessions[0m...
11064 12:41:59.505826 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11065 12:41:59.531499 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11066 12:41:59.587443 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11067 12:41:59.605075 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11068 12:41:59.622350 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11069 12:41:59.643389 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11070 12:41:59.663353 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11071 12:41:59.678037 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11072 12:41:59.731036 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11073 12:41:59.771657 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11074 12:41:59.823075
11075 12:41:59.823237
11076 12:41:59.826269 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11077 12:41:59.826356
11078 12:41:59.829413 debian-bullseye-arm64 login: root (automatic login)
11079 12:41:59.829498
11080 12:41:59.829567
11081 12:42:00.161202 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Wed Jun 14 12:30:40 UTC 2023 aarch64
11082 12:42:00.161334
11083 12:42:00.168048 The programs included with the Debian GNU/Linux system are free software;
11084 12:42:00.174334 the exact distribution terms for each program are described in the
11085 12:42:00.178107 individual files in /usr/share/doc/*/copyright.
11086 12:42:00.178222
11087 12:42:00.184418 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11088 12:42:00.184537 permitted by applicable law.
11089 12:42:00.927411 Matched prompt #10: / #
11091 12:42:00.927710 Setting prompt string to ['/ #']
11092 12:42:00.927804 end: 2.2.5.1 login-action (duration 00:00:27) [common]
11094 12:42:00.927997 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
11095 12:42:00.928086 start: 2.2.6 expect-shell-connection (timeout 00:03:39) [common]
11096 12:42:00.928157 Setting prompt string to ['/ #']
11097 12:42:00.928219 Forcing a shell prompt, looking for ['/ #']
11099 12:42:00.978439 / #
11100 12:42:00.978588 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11101 12:42:00.978703 Waiting using forced prompt support (timeout 00:02:30)
11102 12:42:00.983420
11103 12:42:00.983702 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11104 12:42:00.983794 start: 2.2.7 export-device-env (timeout 00:03:39) [common]
11106 12:42:01.084164 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10724841/extract-nfsrootfs-sun8wizn'
11107 12:42:01.089577 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10724841/extract-nfsrootfs-sun8wizn'
11109 12:42:01.190128 / # export NFS_SERVER_IP='192.168.201.1'
11110 12:42:01.195207 export NFS_SERVER_IP='192.168.201.1'
11111 12:42:01.195499 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11112 12:42:01.195605 end: 2.2 depthcharge-retry (duration 00:01:21) [common]
11113 12:42:01.195695 end: 2 depthcharge-action (duration 00:01:21) [common]
11114 12:42:01.195785 start: 3 lava-test-retry (timeout 00:07:52) [common]
11115 12:42:01.195875 start: 3.1 lava-test-shell (timeout 00:07:52) [common]
11116 12:42:01.195951 Using namespace: common
11118 12:42:01.296337 / # #
11119 12:42:01.296501 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11120 12:42:01.301260 #
11121 12:42:01.301532 Using /lava-10724841
11123 12:42:01.401878 / # export SHELL=/bin/bash
11124 12:42:01.407040 export SHELL=/bin/bash
11126 12:42:01.507624 / # . /lava-10724841/environment
11127 12:42:01.512483 . /lava-10724841/environment
11129 12:42:01.618069 / # /lava-10724841/bin/lava-test-runner /lava-10724841/0
11130 12:42:01.618220 Test shell timeout: 10s (minimum of the action and connection timeout)
11131 12:42:01.623065 /lava-10724841/bin/lava-test-runner /lava-10724841/0
11132 12:42:01.824481 + export TESTRUN_ID=0_timesync-off
11133 12:42:01.828062 + TESTRUN_ID=0_timesync-off
11134 12:42:01.831196 + cd /lava-10724841/0/tests/0_timesync-off
11135 12:42:01.834847 ++ cat uuid
11136 12:42:01.834924 + UUID=10724841_1.6.2.3.1
11137 12:42:01.838440 + set +x
11138 12:42:01.841446 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10724841_1.6.2.3.1>
11139 12:42:01.841753 Received signal: <STARTRUN> 0_timesync-off 10724841_1.6.2.3.1
11140 12:42:01.841862 Starting test lava.0_timesync-off (10724841_1.6.2.3.1)
11141 12:42:01.841998 Skipping test definition patterns.
11142 12:42:01.844235 + systemctl stop systemd-timesyncd
11143 12:42:01.868950 + set +x
11144 12:42:01.872162 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10724841_1.6.2.3.1>
11145 12:42:01.872445 Received signal: <ENDRUN> 0_timesync-off 10724841_1.6.2.3.1
11146 12:42:01.872573 Ending use of test pattern.
11147 12:42:01.872663 Ending test lava.0_timesync-off (10724841_1.6.2.3.1), duration 0.03
11149 12:42:01.916673 + export TESTRUN_ID=1_kselftest-tpm2
11150 12:42:01.920117 + TESTRUN_ID=1_kselftest-tpm2
11151 12:42:01.926712 + cd /lava-10724841/0/tests/1_kselftest-tpm2
11152 12:42:01.926815 ++ cat uuid
11153 12:42:01.929627 + UUID=10724841_1.6.2.3.5
11154 12:42:01.929753 + set +x
11155 12:42:01.933096 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 10724841_1.6.2.3.5>
11156 12:42:01.933388 Received signal: <STARTRUN> 1_kselftest-tpm2 10724841_1.6.2.3.5
11157 12:42:01.933495 Starting test lava.1_kselftest-tpm2 (10724841_1.6.2.3.5)
11158 12:42:01.933627 Skipping test definition patterns.
11159 12:42:01.936583 + cd ./automated/linux/kselftest/
11160 12:42:01.963368 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11161 12:42:01.977527 INFO: install_deps skipped
11162 12:42:02.079129 --2023-06-14 12:42:02-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11163 12:42:02.082292 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11164 12:42:02.209162 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11165 12:42:02.340260 HTTP request sent, awaiting response... 200 OK
11166 12:42:02.343830 Length: 2878416 (2.7M) [application/octet-stream]
11167 12:42:02.346731 Saving to: 'kselftest.tar.xz'
11168 12:42:02.346836
11169 12:42:02.346904
11170 12:42:02.600426 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11171 12:42:02.861566 kselftest.tar.xz 1%[ ] 47.81K 185KB/s
11172 12:42:03.172492 kselftest.tar.xz 7%[> ] 217.50K 418KB/s
11173 12:42:03.443324 kselftest.tar.xz 29%[====> ] 817.06K 983KB/s
11174 12:42:03.555259 kselftest.tar.xz 71%[=============> ] 1.96M 1.77MB/s
11175 12:42:03.561842 kselftest.tar.xz 100%[===================>] 2.74M 2.26MB/s in 1.2s
11176 12:42:03.561988
11177 12:42:03.811230 2023-06-14 12:42:03 (2.26 MB/s) - 'kselftest.tar.xz' saved [2878416/2878416]
11178 12:42:03.811385
11179 12:42:08.300617 skiplist:
11180 12:42:08.303695 ========================================
11181 12:42:08.306751 ========================================
11182 12:42:08.341268 tpm2:test_smoke.sh
11183 12:42:08.343943 tpm2:test_space.sh
11184 12:42:08.356353 ============== Tests to run ===============
11185 12:42:08.356562 tpm2:test_smoke.sh
11186 12:42:08.360149 tpm2:test_space.sh
11187 12:42:08.363427 ===========End Tests to run ===============
11188 12:42:08.438116 <12>[ 33.675226] kselftest: Running tests in tpm2
11189 12:42:08.445796 TAP version 13
11190 12:42:08.455896 1..2
11191 12:42:08.477012 # selftests: tpm2: test_smoke.sh
11192 12:42:09.615797 # test_read_partial_overwrite (tpm2_tests.SmokeTest) ... ERROR
11193 12:42:09.619309 # test_read_partial_resp (tpm2_tests.SmokeTest) ... ERROR
11194 12:42:09.625536 # Exception ignored in: <function Client.__del__ at 0xffffb147ad30>
11195 12:42:09.629357 # Traceback (most recent call last):
11196 12:42:09.639154 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11197 12:42:09.642140 # if self.tpm:
11198 12:42:09.645653 # AttributeError: 'Client' object has no attribute 'tpm'
11199 12:42:09.652379 # test_seal_with_auth (tpm2_tests.SmokeTest) ... ERROR
11200 12:42:09.655392 # Exception ignored in: <function Client.__del__ at 0xffffb147ad30>
11201 12:42:09.659016 # Traceback (most recent call last):
11202 12:42:09.668412 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11203 12:42:09.672066 # if self.tpm:
11204 12:42:09.675353 # AttributeError: 'Client' object has no attribute 'tpm'
11205 12:42:09.681767 # test_seal_with_policy (tpm2_tests.SmokeTest) ... ERROR
11206 12:42:09.688305 # Exception ignored in: <function Client.__del__ at 0xffffb147ad30>
11207 12:42:09.692078 # Traceback (most recent call last):
11208 12:42:09.701692 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11209 12:42:09.701873 # if self.tpm:
11210 12:42:09.708406 # AttributeError: 'Client' object has no attribute 'tpm'
11211 12:42:09.711625 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest) ... ERROR
11212 12:42:09.719190 # Exception ignored in: <function Client.__del__ at 0xffffb147ad30>
11213 12:42:09.721867 # Traceback (most recent call last):
11214 12:42:09.731611 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11215 12:42:09.735080 # if self.tpm:
11216 12:42:09.737948 # AttributeError: 'Client' object has no attribute 'tpm'
11217 12:42:09.744778 # test_send_two_cmds (tpm2_tests.SmokeTest) ... ERROR
11218 12:42:09.748280 # Exception ignored in: <function Client.__del__ at 0xffffb147ad30>
11219 12:42:09.751348 # Traceback (most recent call last):
11220 12:42:09.761177 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11221 12:42:09.764541 # if self.tpm:
11222 12:42:09.767807 # AttributeError: 'Client' object has no attribute 'tpm'
11223 12:42:09.774426 # test_too_short_cmd (tpm2_tests.SmokeTest) ... ERROR
11224 12:42:09.781195 # Exception ignored in: <function Client.__del__ at 0xffffb147ad30>
11225 12:42:09.784417 # Traceback (most recent call last):
11226 12:42:09.794428 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11227 12:42:09.794563 # if self.tpm:
11228 12:42:09.800956 # AttributeError: 'Client' object has no attribute 'tpm'
11229 12:42:09.804465 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest) ... ERROR
11230 12:42:09.810917 # Exception ignored in: <function Client.__del__ at 0xffffb147ad30>
11231 12:42:09.814263 # Traceback (most recent call last):
11232 12:42:09.823981 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11233 12:42:09.827200 # if self.tpm:
11234 12:42:09.831144 # AttributeError: 'Client' object has no attribute 'tpm'
11235 12:42:09.837218 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest) ... ERROR
11236 12:42:09.844376 # Exception ignored in: <function Client.__del__ at 0xffffb147ad30>
11237 12:42:09.847232 # Traceback (most recent call last):
11238 12:42:09.858027 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11239 12:42:09.858166 # if self.tpm:
11240 12:42:09.863835 # AttributeError: 'Client' object has no attribute 'tpm'
11241 12:42:09.863946 #
11242 12:42:09.870416 # ======================================================================
11243 12:42:09.873829 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest)
11244 12:42:09.880414 # ----------------------------------------------------------------------
11245 12:42:09.883968 # Traceback (most recent call last):
11246 12:42:09.896182 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11247 12:42:09.899147 # self.root_key = self.client.create_root_key()
11248 12:42:09.909355 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11249 12:42:09.915830 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11250 12:42:09.926083 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11251 12:42:09.928834 # raise ProtocolError(cc, rc)
11252 12:42:09.935812 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11253 12:42:09.935925 #
11254 12:42:09.942269 # ======================================================================
11255 12:42:09.945712 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest)
11256 12:42:09.952276 # ----------------------------------------------------------------------
11257 12:42:09.955981 # Traceback (most recent call last):
11258 12:42:09.965611 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11259 12:42:09.969204 # self.client = tpm2.Client()
11260 12:42:09.978821 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11261 12:42:09.982339 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11262 12:42:09.988784 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11263 12:42:09.988911 #
11264 12:42:09.995553 # ======================================================================
11265 12:42:10.002311 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest)
11266 12:42:10.005612 # ----------------------------------------------------------------------
11267 12:42:10.008622 # Traceback (most recent call last):
11268 12:42:10.018583 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11269 12:42:10.022255 # self.client = tpm2.Client()
11270 12:42:10.031633 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11271 12:42:10.038350 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11272 12:42:10.041448 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11273 12:42:10.045219 #
11274 12:42:10.051519 # ======================================================================
11275 12:42:10.055122 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest)
11276 12:42:10.061226 # ----------------------------------------------------------------------
11277 12:42:10.064723 # Traceback (most recent call last):
11278 12:42:10.075129 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11279 12:42:10.078470 # self.client = tpm2.Client()
11280 12:42:10.088009 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11281 12:42:10.091017 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11282 12:42:10.097807 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11283 12:42:10.097932 #
11284 12:42:10.104642 # ======================================================================
11285 12:42:10.110978 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest)
11286 12:42:10.117578 # ----------------------------------------------------------------------
11287 12:42:10.120895 # Traceback (most recent call last):
11288 12:42:10.130611 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11289 12:42:10.133883 # self.client = tpm2.Client()
11290 12:42:10.143822 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11291 12:42:10.147052 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11292 12:42:10.153668 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11293 12:42:10.153785 #
11294 12:42:10.160860 # ======================================================================
11295 12:42:10.163765 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest)
11296 12:42:10.170367 # ----------------------------------------------------------------------
11297 12:42:10.173782 # Traceback (most recent call last):
11298 12:42:10.183925 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11299 12:42:10.187310 # self.client = tpm2.Client()
11300 12:42:10.197476 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11301 12:42:10.204713 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11302 12:42:10.207845 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11303 12:42:10.207959 #
11304 12:42:10.212647 # ======================================================================
11305 12:42:10.218403 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest)
11306 12:42:10.225652 # ----------------------------------------------------------------------
11307 12:42:10.230484 # Traceback (most recent call last):
11308 12:42:10.238772 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11309 12:42:10.242006 # self.client = tpm2.Client()
11310 12:42:10.249772 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11311 12:42:10.255874 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11312 12:42:10.259325 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11313 12:42:10.259431 #
11314 12:42:10.265915 # ======================================================================
11315 12:42:10.272670 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest)
11316 12:42:10.279605 # ----------------------------------------------------------------------
11317 12:42:10.282544 # Traceback (most recent call last):
11318 12:42:10.293214 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11319 12:42:10.295983 # self.client = tpm2.Client()
11320 12:42:10.305949 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11321 12:42:10.309321 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11322 12:42:10.316247 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11323 12:42:10.316370 #
11324 12:42:10.322339 # ======================================================================
11325 12:42:10.329133 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest)
11326 12:42:10.335869 # ----------------------------------------------------------------------
11327 12:42:10.338990 # Traceback (most recent call last):
11328 12:42:10.348655 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11329 12:42:10.352017 # self.client = tpm2.Client()
11330 12:42:10.362148 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11331 12:42:10.365336 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11332 12:42:10.371803 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11333 12:42:10.371923 #
11334 12:42:10.378723 # ----------------------------------------------------------------------
11335 12:42:10.378853 # Ran 9 tests in 0.024s
11336 12:42:10.378924 #
11337 12:42:10.381791 # FAILED (errors=9)
11338 12:42:10.385423 # test_async (tpm2_tests.AsyncTest) ... ok
11339 12:42:10.392238 # test_flush_invalid_context (tpm2_tests.AsyncTest) ... ok
11340 12:42:10.392353 #
11341 12:42:10.398372 # ----------------------------------------------------------------------
11342 12:42:10.398493 # Ran 2 tests in 0.031s
11343 12:42:10.398581 #
11344 12:42:10.402110 # OK
11345 12:42:10.405332 ok 1 selftests: tpm2: test_smoke.sh
11346 12:42:10.405430 # selftests: tpm2: test_space.sh
11347 12:42:10.412106 # test_flush_context (tpm2_tests.SpaceTest) ... ERROR
11348 12:42:10.414977 # test_get_handles (tpm2_tests.SpaceTest) ... ERROR
11349 12:42:10.421796 # test_invalid_cc (tpm2_tests.SpaceTest) ... ERROR
11350 12:42:10.425396 # test_make_two_spaces (tpm2_tests.SpaceTest) ... ERROR
11351 12:42:10.425494 #
11352 12:42:10.431470 # ======================================================================
11353 12:42:10.438205 # ERROR: test_flush_context (tpm2_tests.SpaceTest)
11354 12:42:10.444668 # ----------------------------------------------------------------------
11355 12:42:10.447949 # Traceback (most recent call last):
11356 12:42:10.457972 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11357 12:42:10.461748 # root1 = space1.create_root_key()
11358 12:42:10.471399 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11359 12:42:10.477777 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11360 12:42:10.488052 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11361 12:42:10.491084 # raise ProtocolError(cc, rc)
11362 12:42:10.497997 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11363 12:42:10.498117 #
11364 12:42:10.504605 # ======================================================================
11365 12:42:10.507892 # ERROR: test_get_handles (tpm2_tests.SpaceTest)
11366 12:42:10.514625 # ----------------------------------------------------------------------
11367 12:42:10.517641 # Traceback (most recent call last):
11368 12:42:10.527837 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11369 12:42:10.530629 # space1.create_root_key()
11370 12:42:10.540703 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11371 12:42:10.547380 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11372 12:42:10.557056 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11373 12:42:10.560986 # raise ProtocolError(cc, rc)
11374 12:42:10.567201 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11375 12:42:10.567328 #
11376 12:42:10.573610 # ======================================================================
11377 12:42:10.576832 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest)
11378 12:42:10.583766 # ----------------------------------------------------------------------
11379 12:42:10.587204 # Traceback (most recent call last):
11380 12:42:10.596753 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11381 12:42:10.600132 # root1 = space1.create_root_key()
11382 12:42:10.609986 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11383 12:42:10.616560 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11384 12:42:10.626489 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11385 12:42:10.630206 # raise ProtocolError(cc, rc)
11386 12:42:10.636702 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11387 12:42:10.636828 #
11388 12:42:10.642930 # ======================================================================
11389 12:42:10.646683 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest)
11390 12:42:10.652822 # ----------------------------------------------------------------------
11391 12:42:10.656210 # Traceback (most recent call last):
11392 12:42:10.669826 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11393 12:42:10.673251 # root1 = space1.create_root_key()
11394 12:42:10.683158 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11395 12:42:10.689325 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11396 12:42:10.699223 # File "/lava-10724841/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11397 12:42:10.702456 # raise ProtocolError(cc, rc)
11398 12:42:10.706039 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11399 12:42:10.706172 #
11400 12:42:10.712745 # ----------------------------------------------------------------------
11401 12:42:10.715910 # Ran 4 tests in 0.054s
11402 12:42:10.716025 #
11403 12:42:10.719417 # FAILED (errors=4)
11404 12:42:10.722411 not ok 2 selftests: tpm2: test_space.sh # exit=1
11405 12:42:10.729465 tpm2_test_smoke_sh pass
11406 12:42:10.732960 tpm2_test_space_sh fail
11407 12:42:10.749292 + ../../utils/send-to-lava.sh ./output/result.txt
11408 12:42:10.797005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11409 12:42:10.797357 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11411 12:42:10.829673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11412 12:42:10.829994 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11414 12:42:10.833051 + set +x
11415 12:42:10.836178 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 10724841_1.6.2.3.5>
11416 12:42:10.836465 Received signal: <ENDRUN> 1_kselftest-tpm2 10724841_1.6.2.3.5
11417 12:42:10.836573 Ending use of test pattern.
11418 12:42:10.836642 Ending test lava.1_kselftest-tpm2 (10724841_1.6.2.3.5), duration 8.90
11420 12:42:10.839629 <LAVA_TEST_RUNNER EXIT>
11421 12:42:10.839895 ok: lava_test_shell seems to have completed
11422 12:42:10.840003 tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11423 12:42:10.840101 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11424 12:42:10.840191 end: 3 lava-test-retry (duration 00:00:10) [common]
11425 12:42:10.840295 start: 4 finalize (timeout 00:07:42) [common]
11426 12:42:10.840422 start: 4.1 power-off (timeout 00:00:30) [common]
11427 12:42:10.840633 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11428 12:42:10.917492 >> Command sent successfully.
11429 12:42:10.920386 Returned 0 in 0 seconds
11430 12:42:11.020856 end: 4.1 power-off (duration 00:00:00) [common]
11432 12:42:11.021230 start: 4.2 read-feedback (timeout 00:07:42) [common]
11433 12:42:11.021502 Listened to connection for namespace 'common' for up to 1s
11434 12:42:12.022451 Finalising connection for namespace 'common'
11435 12:42:12.022640 Disconnecting from shell: Finalise
11436 12:42:12.022718 / #
11437 12:42:12.123145 end: 4.2 read-feedback (duration 00:00:01) [common]
11438 12:42:12.123339 end: 4 finalize (duration 00:00:01) [common]
11439 12:42:12.123483 Cleaning after the job
11440 12:42:12.123590 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724841/tftp-deploy-p8zw_5gu/ramdisk
11441 12:42:12.125913 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724841/tftp-deploy-p8zw_5gu/kernel
11442 12:42:12.135098 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724841/tftp-deploy-p8zw_5gu/dtb
11443 12:42:12.135331 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724841/tftp-deploy-p8zw_5gu/nfsrootfs
11444 12:42:12.205145 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724841/tftp-deploy-p8zw_5gu/modules
11445 12:42:12.210656 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10724841
11446 12:42:12.748958 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10724841
11447 12:42:12.749162 Job finished correctly